From: w00623716 <wushuai51@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I9EMOF CVE: NA Reference: NA --------------------------------- The RDMA driver supports the following features: Supports Huawei SP600 series NICs; Supports RoCEv2; Supports RoCE XRC, UD, UC, and RC modes; Supports RoCE UC, RC, and UD local switching; Supports RoCE MR, PD, CQ, QoS, QP, and SRQ management; Supports RoCE congestion control; Supports RoCE Bond; Supports RoCE FLR; Supports RoCE entry specifications; Supports RoCE error detection and reporting; Signed-off-by: w00623716 <wushuai51@huawei.com> --- arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + drivers/infiniband/Kconfig | 1 + drivers/infiniband/hw/Makefile | 1 + drivers/infiniband/hw/hiroce3/Kconfig | 14 + drivers/infiniband/hw/hiroce3/Makefile | 157 + .../infiniband/hw/hiroce3/bond/roce_bond.h | 149 + .../hw/hiroce3/bond/roce_bond_common.c | 950 + drivers/infiniband/hw/hiroce3/cq/roce_cq.h | 265 + .../infiniband/hw/hiroce3/cq/roce_cq_common.c | 202 + .../infiniband/hw/hiroce3/cq/roce_cq_cqe.c | 731 + .../infiniband/hw/hiroce3/cq/roce_cq_create.c | 604 + .../infiniband/hw/hiroce3/cq/roce_cq_ctrl.c | 872 + .../hw/hiroce3/cq/roce_cq_destroy.c | 298 + drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c | 126 + drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h | 184 + .../infiniband/hw/hiroce3/dfx/roce_dfx_cap.c | 676 + .../infiniband/hw/hiroce3/dfx/roce_dfx_cap.h | 184 + .../hw/hiroce3/dfx/roce_dfx_query.c | 615 + .../hiroce3/extension/roce_cdev_extension.c | 18 + .../hiroce3/extension/roce_event_extension.c | 30 + .../hiroce3/extension/roce_main_extension.c | 206 + .../hw/hiroce3/extension/roce_mr_extension.c | 38 + .../hiroce3/extension/roce_netdev_extension.c | 174 + .../hw/hiroce3/extension/roce_qp_extension.c | 251 + .../extension/roce_qp_post_send_extension.c | 20 + .../hw/hiroce3/extension/roce_srq_extension.c | 35 + .../hw/hiroce3/host/crypt/hisec_cfg.c | 148 + .../hw/hiroce3/host/crypt/hisec_cfg.h | 26 + .../hw/hiroce3/host/crypt/hisec_hwrand.c | 229 + .../hw/hiroce3/host/crypt/hisec_hwrand.h | 14 + .../host/crypt/linux/kernel/hisec_crypt_dev.h | 29 + .../crypt/linux/kernel/hisec_crypt_main.c | 123 + .../hw/hiroce3/host/crypt/readme.txt | 1 + .../hw/hiroce3/host/hmm/hmm_buddy.c | 170 + .../hw/hiroce3/host/hmm/hmm_buddy.h | 36 + .../infiniband/hw/hiroce3/host/hmm/hmm_comp.c | 165 + .../infiniband/hw/hiroce3/host/hmm/hmm_comp.h | 225 + .../hw/hiroce3/host/hmm/hmm_comp_init.c | 131 + .../hw/hiroce3/host/hmm/hmm_comp_mtt.c | 497 + .../hw/hiroce3/host/hmm/hmm_comp_mw_mr.c | 222 + .../hw/hiroce3/host/hmm/hmm_comp_res.c | 63 + .../infiniband/hw/hiroce3/host/hmm/hmm_em.c | 348 + .../infiniband/hw/hiroce3/host/hmm/hmm_em.h | 48 + .../infiniband/hw/hiroce3/host/hmm/hmm_mr.c | 403 + .../infiniband/hw/hiroce3/host/hmm/hmm_mr.h | 34 + .../infiniband/hw/hiroce3/host/hmm/hmm_umem.c | 322 + .../infiniband/hw/hiroce3/host/hmm/hmm_umem.h | 124 + .../hw/hiroce3/host/mt/hinic3_devlink.c | 428 + .../hw/hiroce3/host/mt/hinic3_devlink.h | 173 + .../hw/hiroce3/host/mt/hinic3_hw_mt.c | 605 + .../hw/hiroce3/host/mt/hinic3_hw_mt.h | 49 + .../hw/hiroce3/host/mt/hinic3_nictool.c | 982 + .../hw/hiroce3/host/mt/hinic3_nictool.h | 35 + .../infiniband/hw/hiroce3/host/mt/readme.txt | 1 + .../hw/hiroce3/host/vram/vram_common.c | 192 + .../hw/hiroce3/include/crypt/hisec_mpu_cmd.h | 38 + .../include/crypt/hisec_mpu_cmd_defs.h | 118 + .../hw/hiroce3/include/crypt/hisec_npu_cmd.h | 30 + .../include/crypt/hisec_npu_cmd_defs.h | 415 + .../hw/hiroce3/include/hinic3_hmm.h | 83 + .../hw/hiroce3/include/hinic3_rdma.h | 203 + .../hw/hiroce3/include/hinic3_srv_nic.h | 218 + .../hw/hiroce3/include/hw/db_srv_type_pub.h | 126 + .../hw/hiroce3/include/hw/node_id.h | 58 + .../hw/register/infra/cnb_c_union_define.h | 318 + .../hw/register/infra/cnb_reg_offset.h | 42 + .../hw/register/infra/cpb_c_union_define.h | 8234 + .../hw/register/infra/cpb_reg_offset.h | 1157 + .../hw/register/infra/cpi_c_union_define.h | 23677 +++ .../register/infra/cpi_dfx_glb_reg_offset.h | 236 + .../hw/register/infra/cpi_reg_offset.h | 4698 + .../hw/register/infra/crypto_c_union_define.h | 6226 + .../hw/register/infra/crypto_reg_offset.h | 1181 + .../hw/register/infra/esch_c_union_define.h | 1340 + .../hw/register/infra/esch_reg_offset.h | 802 + .../infra/hi1823_csr_sm_addr_define.h | 384 + .../hw/register/infra/hi1823_csr_sm_typedef.h | 12259 ++ .../register/infra/hinic3_csr_addr_common.h | 254 + .../hw/register/infra/icdq_c_union_define.h | 1062 + .../hw/register/infra/icdq_reg_offset.h | 114 + .../hw/register/infra/ipsurx_c_union_define.h | 4805 + .../hw/register/infra/ipsurx_reg_offset.h | 1469 + .../hw/register/infra/ipsurx_typedef.h | 30688 ++++ .../hw/register/infra/ipsutx_c_union_define.h | 2872 + .../hw/register/infra/ipsutx_reg_offset.h | 429 + .../hw/register/infra/lcam_c_union_define.h | 741 + .../hw/register/infra/lcam_reg_offset.h | 72 + .../hw/register/infra/mqm_c_union_define.h | 11885 ++ .../hw/register/infra/mqm_reg_offset.h | 3696 + .../hw/register/infra/oq_c_union_define.h | 2285 + .../include/hw/register/infra/oq_reg_offset.h | 261 + .../hw/register/infra/pe_c_union_define.h | 1819 + .../include/hw/register/infra/pe_reg_offset.h | 493 + .../hw/register/infra/pqm_c_union_define.h | 2091 + .../hw/register/infra/pqm_reg_offset.h | 291 + .../hw/register/infra/prmrx_c_union_define.h | 2937 + .../hw/register/infra/prmrx_reg_offset.h | 258 + .../hw/register/infra/prmtx_c_union_define.h | 2758 + .../hw/register/infra/prmtx_reg_offset.h | 264 + .../register/infra/ring_cnb_c_union_define.h | 314 + .../hw/register/infra/ring_cnb_reg_offset.h | 52 + .../hw/register/infra/sm_c_union_define.h | 6441 + .../include/hw/register/infra/sm_reg_offset.h | 860 + .../hw/register/infra/stffq_c_union_define.h | 6438 + .../hw/register/infra/stffq_reg_offset.h | 1059 + .../hw/register/infra/stfiq_c_union_define.h | 1413 + .../hw/register/infra/stfiq_reg_offset.h | 148 + .../register/infra/stfisch_c_union_define.h | 420 + .../hw/register/infra/stfisch_reg_offset.h | 828 + .../hw/register/infra/stlfq_c_union_define.h | 6358 + .../hw/register/infra/stlfq_reg_offset.h | 535 + .../hw/register/infra/stliq_c_union_define.h | 1109 + .../hw/register/infra/stliq_reg_offset.h | 106 + .../register/infra/stlisch_c_union_define.h | 425 + .../hw/register/infra/stlisch_reg_offset.h | 527 + .../hw/register/infra/tile_c_union_define.h | 3399 + .../hw/register/infra/tile_reg_offset.h | 399 + .../hw/register/infra/virtio_c_union_define.h | 4349 + .../hw/register/infra/virtio_reg_offset.h | 275 + .../hw/register/mag/c_union_define_mag_top.h | 1695 + .../hw/register/mag/c_union_define_smag_cfg.h | 1457 + .../mag/hi1822_csr_mag_offset_union_define.h | 22 + .../hw/register/mag/mac_reg_an_lth60_offset.h | 483 + .../hw/register/mag/mac_reg_com_offset.h | 33 + .../hw/register/mag/mac_reg_mib_offset.h | 26 + .../hw/register/mag/mac_reg_rx_brfec_offset.h | 68 + .../hw/register/mag/mac_reg_rx_mac_offset.h | 95 + .../hw/register/mag/mac_reg_rx_pcs_offset.h | 343 + .../hw/register/mag/mac_reg_rx_rsfec_offset.h | 503 + .../register/mag/mac_reg_rxpma_core_offset.h | 213 + .../register/mag/mac_reg_rxpma_lane_offset.h | 44 + .../hw/register/mag/mac_reg_tx_brfec_offset.h | 62 + .../hw/register/mag/mac_reg_tx_mac_offset.h | 109 + .../hw/register/mag/mac_reg_tx_pcs_offset.h | 169 + .../hw/register/mag/mac_reg_tx_rsfec_offset.h | 75 + .../register/mag/mac_reg_txpma_core_offset.h | 19 + .../register/mag/mac_reg_txpma_lane_offset.h | 43 + .../mag/mag_fc_sds_harden_reg_offset.h | 60 + .../hw/register/mag/mag_top_reg_offset.h | 379 + .../hw/register/mag/smag_cfg_reg_offset.h | 277 + .../hw/register/misc/sfc_c_union_define.h | 721 + .../include/hw/register/misc/sfc_reg_offset.h | 217 + .../hw/register/mpu/c_union_define_crg.h | 625 + .../include/hw/register/mpu/crg_reg_offset.h | 68 + .../hw/register/mpu/mpu_c_union_define.h | 15330 ++ .../register/mpu/mpu_harden_c_union_define.h | 795 + .../hw/register/mpu/mpu_harden_reg_offset.h | 461 + .../include/hw/register/mpu/mpu_reg_offset.h | 2115 + .../hw/register/pcie/hva_peh_c_union_define.h | 3236 + .../hw/register/pcie/hva_peh_reg_offset.h | 214 + .../hw/register/pcie/pcie5_ap_addr_define.h | 40529 +++++ .../hw/register/pcie/pcie5_ap_typedef.h | 42419 ++++++ .../hw/register/pcie/pcie5_core_addr_define.h | 3233 + .../hw/register/pcie/pcie5_core_typedef.h | 118101 +++++++++++++++ .../hw/register/pcie/pcie5_pcs_addr_define.h | 286 + .../hw/register/pcie/pcie5_pcs_typedef.h | 11995 ++ .../hw/register/rxtx/apb2ff_reg_offset.h | 68 + .../hw/register/rxtx/c_union_define_apb2ff.h | 82 + .../register/top/mag_harden_c_union_define.h | 484 + .../hw/register/top/mag_harden_reg_offset.h | 55 + .../register/top/pcie_harden_c_union_define.h | 738 + .../hw/register/top/pcie_harden_reg_offset.h | 65 + .../register/top/smf0_harden_c_union_define.h | 1611 + .../hw/register/top/smf0_harden_reg_offset.h | 69 + .../top/stlqu_harden_c_union_define.h | 662 + .../hw/register/top/stlqu_harden_reg_offset.h | 69 + .../register/top/top_cpb_harden_reg_offset.h | 42 + .../top_encryp_decryp_harden_c_union_define.h | 48 + .../top/top_encryp_decryp_harden_reg_offset.h | 73 + .../hw/register/top/top_iocfg_reg_offset.h | 81 + .../register/totem/arm_ras_c_union_define.h | 192 + .../hw/register/totem/avs_reg_offset.h | 875 + .../register/totem/ddrc_arm_ras_reg_offset.h | 31 + .../hw/register/totem/ddrc_dmc_c_union_def.h | 102 + .../hw/register/totem/ddrc_dmc_reg_offset.h | 314 + .../register/totem/ddrc_rasc_c_union_define.h | 1411 + .../hw/register/totem/ddrc_rasc_reg_offset.h | 192 + .../hw/register/totem/efuse_reg_offset.h | 125 + .../hw/register/totem/fabric_c_union_define.h | 1629 + .../hw/register/totem/fabric_reg_offset.h | 102 + .../hw/register/totem/hha_c_union_def.h | 62 + .../hw/register/totem/hva_c_union_define.h | 1287 + .../hw/register/totem/hva_reg_offset.h | 110 + .../register/totem/hva_sm23_c_union_define.h | 43 + .../hw/register/totem/hva_sm23_reg_offset.h | 37 + .../register/totem/hva_smf_c_union_define.h | 1194 + .../hw/register/totem/hva_smf_reg_offset.h | 189 + .../hw/register/totem/mbigen_c_union_define.h | 643 + .../hw/register/totem/mbigen_reg_offset.h | 956 + .../hw/register/totem/pcie4_c_union_define.h | 5992 + .../hw/register/totem/pcie4_reg_offset.h | 2240 + .../register/totem/phosphor_c_union_define.h | 2841 + .../hw/register/totem/phosphor_reg_offset.h | 149 + .../include/hw/register/totem/plat_efuse.h | 368 + .../hw/register/totem/ras_c_union_define.h | 295 + .../hw/register/totem/ras_reg_offset.h | 110 + .../hw/register/totem/sioe_reg_offset.h | 426 + .../hw/register/totem/sllc_reg_offset.h | 150 + .../hw/register/totem/smmu_c_union_define.h | 2448 + .../hw/register/totem/smmu_reg_offset.h | 256 + .../hw/register/totem/sysctrl_reg_offset.h | 316 + .../hw/hiroce3/include/hw/service_type_pub.h | 135 + .../hw/hiroce3/include/hw/smf_cache_type.h | 142 + .../hw/hiroce3/include/hw/smf_instance_id.h | 168 + .../hw/hiroce3/include/hw/sml_table.h | 4079 + .../include/hw/sml_table_define_cloud.h | 273 + .../include/hw/sml_table_define_compute_dpu.h | 12 + .../hw/sml_table_define_compute_roce.h | 137 + .../hw/sml_table_define_compute_standard.h | 234 + .../include/hw/sml_table_define_fpga.h | 340 + .../hiroce3/include/hw/sml_table_define_llt.h | 361 + .../include/hw/sml_table_define_storage_fc.h | 65 + .../hw/sml_table_define_storage_fc_adapt.h | 65 + .../hw/sml_table_define_storage_roce.h | 149 + .../hw/sml_table_define_storage_roceaa.h | 164 + .../include/hw/sml_table_define_storage_toe.h | 113 + .../hw/hiroce3/include/hw/sml_table_pub.h | 330 + .../hw/hiroce3/include/hw/tile_spec.h | 28 + .../hw/hiroce3/include/mag/mag_mpu_cmd.h | 77 + .../hw/hiroce3/include/mag/mag_mpu_cmd_defs.h | 928 + .../include/micro_log/hinic3_micro_log.c | 1156 + .../include/micro_log/hinic3_micro_log.h | 169 + .../hw/hiroce3/include/nic/nic_cfg_comm.h | 62 + .../hw/hiroce3/include/nic/nic_mpu_cmd.h | 147 + .../hw/hiroce3/include/nic/nic_mpu_cmd_defs.h | 1317 + .../hw/hiroce3/include/nic/nic_npu_cmd.h | 31 + .../hw/hiroce3/include/nic/nic_npu_cmd_defs.h | 140 + .../hw/hiroce3/include/nic/nic_npu_wqe_defs.h | 240 + .../include/public/npu_cmdq_base_defs.h | 241 + .../include/rdma/rdma_context_format.h | 4435 + .../include/rdma/rdma_ext_ctx_format.h | 382 + .../hw/hiroce3/include/rdma/roce_ccf_format.h | 725 + .../hiroce3/include/rdma/roce_compile_macro.h | 91 + .../hw/hiroce3/include/rdma/roce_ctx_api.h | 265 + .../hw/hiroce3/include/rdma/roce_dif_format.h | 459 + .../hw/hiroce3/include/rdma/roce_err_type.h | 125 + .../hiroce3/include/rdma/roce_hmm_context.h | 196 + .../hw/hiroce3/include/rdma/roce_mpu_common.h | 241 + .../include/rdma/roce_mpu_ulp_common.h | 56 + .../hw/hiroce3/include/rdma/roce_pub.h | 262 + .../hw/hiroce3/include/rdma/roce_pub_cmd.h | 264 + .../hw/hiroce3/include/rdma/roce_ulp.h | 177 + .../hw/hiroce3/include/rdma/roce_vbs_format.h | 208 + .../hw/hiroce3/include/rdma/roce_verbs_attr.h | 400 + .../include/rdma/roce_verbs_attr_qpc_chip.h | 355 + .../hw/hiroce3/include/rdma/roce_verbs_cmd.h | 250 + .../hiroce3/include/rdma/roce_verbs_cq_attr.h | 170 + .../include/rdma/roce_verbs_ext_attr.h | 51 + .../hiroce3/include/rdma/roce_verbs_format.h | 134 + .../include/rdma/roce_verbs_gid_attr.h | 112 + .../hiroce3/include/rdma/roce_verbs_mr_attr.h | 299 + .../hw/hiroce3/include/rdma/roce_verbs_pub.h | 226 + .../include/rdma/roce_verbs_srq_attr.h | 229 + .../include/rdma/roce_verbs_ulp_format.h | 94 + .../hw/hiroce3/include/rdma/roce_wqe_format.h | 825 + .../hw/hiroce3/include/rdma/roce_xqe_format.h | 500 + .../infiniband/hw/hiroce3/include/readme.txt | 1 + .../hw/hiroce3/include/roce_cdev_extension.h | 20 + .../hw/hiroce3/include/roce_event_extension.h | 20 + .../hw/hiroce3/include/roce_main_extension.h | 84 + .../hw/hiroce3/include/roce_mr_extension.h | 24 + .../hiroce3/include/roce_netdev_extension.h | 26 + .../hw/hiroce3/include/roce_qp_extension.h | 69 + .../include/roce_qp_post_send_extension.h | 24 + .../hw/hiroce3/include/roce_srq_extension.h | 20 + drivers/infiniband/hw/hiroce3/mr/roce_mr.c | 1305 + drivers/infiniband/hw/hiroce3/mr/roce_mr.h | 105 + drivers/infiniband/hw/hiroce3/qp/roce_post.h | 198 + drivers/infiniband/hw/hiroce3/qp/roce_qp.h | 255 + .../infiniband/hw/hiroce3/qp/roce_qp_create.c | 1296 + .../hw/hiroce3/qp/roce_qp_destroy.c | 289 + .../infiniband/hw/hiroce3/qp/roce_qp_exp.h | 86 + .../infiniband/hw/hiroce3/qp/roce_qp_modify.c | 2162 + .../hw/hiroce3/qp/roce_qp_post_recv.c | 253 + .../hw/hiroce3/qp/roce_qp_post_send.c | 1257 + .../infiniband/hw/hiroce3/qp/roce_qp_query.c | 386 + .../infiniband/hw/hiroce3/rdma/rdma_bitmap.c | 141 + .../infiniband/hw/hiroce3/rdma/rdma_bitmap.h | 41 + .../infiniband/hw/hiroce3/rdma/rdma_comp.c | 29 + .../infiniband/hw/hiroce3/rdma/rdma_comp.h | 138 + .../hw/hiroce3/rdma/rdma_comp_gid.c | 275 + .../hw/hiroce3/rdma/rdma_comp_init.c | 387 + .../hw/hiroce3/rdma/rdma_comp_mw_mr.c | 244 + .../infiniband/hw/hiroce3/rdma/rdma_comp_pd.c | 57 + .../hw/hiroce3/rdma/rdma_comp_res.c | 247 + drivers/infiniband/hw/hiroce3/roce.h | 635 + drivers/infiniband/hw/hiroce3/roce_cdev.c | 1218 + drivers/infiniband/hw/hiroce3/roce_cmd.c | 753 + drivers/infiniband/hw/hiroce3/roce_cmd.h | 78 + drivers/infiniband/hw/hiroce3/roce_compat.h | 60 + drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c | 57 + drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h | 20 + drivers/infiniband/hw/hiroce3/roce_db.c | 103 + drivers/infiniband/hw/hiroce3/roce_db.h | 36 + drivers/infiniband/hw/hiroce3/roce_event.c | 568 + drivers/infiniband/hw/hiroce3/roce_event.h | 43 + drivers/infiniband/hw/hiroce3/roce_k_ioctl.h | 96 + drivers/infiniband/hw/hiroce3/roce_main.c | 1752 + drivers/infiniband/hw/hiroce3/roce_mix.c | 1402 + drivers/infiniband/hw/hiroce3/roce_mix.h | 210 + drivers/infiniband/hw/hiroce3/roce_netdev.c | 858 + drivers/infiniband/hw/hiroce3/roce_netdev.h | 65 + drivers/infiniband/hw/hiroce3/roce_netlink.c | 368 + drivers/infiniband/hw/hiroce3/roce_netlink.h | 171 + drivers/infiniband/hw/hiroce3/roce_pd.c | 137 + drivers/infiniband/hw/hiroce3/roce_pd.h | 31 + drivers/infiniband/hw/hiroce3/roce_sysfs.c | 1787 + drivers/infiniband/hw/hiroce3/roce_sysfs.h | 115 + drivers/infiniband/hw/hiroce3/roce_user.h | 72 + drivers/infiniband/hw/hiroce3/roce_xrc.c | 203 + drivers/infiniband/hw/hiroce3/roce_xrc.h | 30 + drivers/infiniband/hw/hiroce3/srq/roce_srq.h | 204 + .../infiniband/hw/hiroce3/srq/roce_srq_comm.c | 97 + .../hw/hiroce3/srq/roce_srq_create.c | 710 + .../infiniband/hw/hiroce3/srq/roce_srq_ctrl.c | 634 + 316 files changed, 502006 insertions(+) create mode 100644 drivers/infiniband/hw/hiroce3/Kconfig create mode 100755 drivers/infiniband/hw/hiroce3/Makefile create mode 100644 drivers/infiniband/hw/hiroce3/bond/roce_bond.h create mode 100644 drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq.h create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c create mode 100755 drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c create mode 100644 drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h create mode 100644 drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c create 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create mode 100644 drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_cfg_comm.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_npu_wqe_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/public/npu_cmdq_base_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/rdma_context_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/rdma_ext_ctx_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_ccf_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_compile_macro.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_ctx_api.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_dif_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_err_type.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_hmm_context.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_common.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_ulp_common.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_pub.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_pub_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_ulp.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_vbs_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr_qpc_chip.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cq_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ext_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_gid_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_mr_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_pub.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_srq_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ulp_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_wqe_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_xqe_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/readme.txt create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_cdev_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_event_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_main_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_mr_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_netdev_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_qp_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_qp_post_send_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_srq_extension.h create mode 100755 drivers/infiniband/hw/hiroce3/mr/roce_mr.c create mode 100644 drivers/infiniband/hw/hiroce3/mr/roce_mr.h create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_post.h create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp.h create mode 100755 drivers/infiniband/hw/hiroce3/qp/roce_qp_create.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_destroy.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_exp.h create mode 100755 drivers/infiniband/hw/hiroce3/qp/roce_qp_modify.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_post_recv.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_post_send.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_query.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.h create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp.h create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_gid.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_init.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_mw_mr.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_pd.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_res.c create mode 100755 drivers/infiniband/hw/hiroce3/roce.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_cdev.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_cmd.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_compat.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_db.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_db.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_event.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_event.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_k_ioctl.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_main.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_mix.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_mix.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_netdev.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_netdev.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_netlink.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_netlink.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_pd.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_pd.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_sysfs.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_sysfs.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_user.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_xrc.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_xrc.h create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq.h create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq_comm.c create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq_create.c create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq_ctrl.c diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 95bc227d2..2089bb228 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -6167,6 +6167,7 @@ CONFIG_MLX5_INFINIBAND=m # CONFIG_INFINIBAND_MTHCA is not set # CONFIG_INFINIBAND_OCRDMA is not set CONFIG_INFINIBAND_QEDR=m +CONFIG_HIROCE3=m CONFIG_RDMA_RXE=m # CONFIG_RDMA_SIW is not set CONFIG_INFINIBAND_IPOIB=m diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 8f336547c..087a9f4f1 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -6849,6 +6849,7 @@ CONFIG_INFINIBAND_QEDR=m CONFIG_INFINIBAND_USNIC=m CONFIG_INFINIBAND_VMWARE_PVRDMA=m CONFIG_INFINIBAND_RDMAVT=m +CONFIG_HIROCE3=m CONFIG_RDMA_RXE=m # CONFIG_RDMA_SIW is not set CONFIG_INFINIBAND_IPOIB=m diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig index a5827d11e..e8270b8d6 100644 --- a/drivers/infiniband/Kconfig +++ b/drivers/infiniband/Kconfig @@ -95,6 +95,7 @@ source "drivers/infiniband/hw/qedr/Kconfig" source "drivers/infiniband/hw/qib/Kconfig" source "drivers/infiniband/hw/usnic/Kconfig" source "drivers/infiniband/hw/vmw_pvrdma/Kconfig" +source "drivers/infiniband/hw/hiroce3/Kconfig" source "drivers/infiniband/sw/rdmavt/Kconfig" endif # !UML source "drivers/infiniband/sw/rxe/Kconfig" diff --git a/drivers/infiniband/hw/Makefile b/drivers/infiniband/hw/Makefile index 1211f4317..46faec393 100644 --- a/drivers/infiniband/hw/Makefile +++ b/drivers/infiniband/hw/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_INFINIBAND_HNS) += hns/ obj-$(CONFIG_INFINIBAND_QEDR) += qedr/ obj-$(CONFIG_INFINIBAND_BNXT_RE) += bnxt_re/ obj-$(CONFIG_INFINIBAND_ERDMA) += erdma/ +obj-$(CONFIG_HIROCE3) += hiroce3/ diff --git a/drivers/infiniband/hw/hiroce3/Kconfig b/drivers/infiniband/hw/hiroce3/Kconfig new file mode 100644 index 000000000..6657310b7 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Huawei driver configuration +# + +config HIROCE3 + tristate "Huawei Intelligent Network Interface Card Driver for RDMA" + depends on HINIC3 && PCI_MSI && NUMA && PCI_IOV && DCB && (X86 || ARM64) + help + This driver supports HiROCE PCIE Ethernet cards. + To compile this driver as part of the kernel, choose Y here. + If unsure, choose N. + The default is N. + diff --git a/drivers/infiniband/hw/hiroce3/Makefile b/drivers/infiniband/hw/hiroce3/Makefile new file mode 100755 index 000000000..96525f9ae --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/Makefile @@ -0,0 +1,157 @@ +EXPORT_SYMBOL := true + +GLOBAL_VERSION="16.13.8.1" +OFED_VERSION := OFED_MLNX_5_8 + +KBUILD_EXTRA_SYMBOLS += $(srctree)/drivers/net/ethernet/huawei/hinic3/Module.symvers + +EXTRA_CFLAGS += -DHW_CONVERT_ENDIAN +EXTRA_CFLAGS += -DROCE_SERVICE +EXTRA_CFLAGS += -D__ROCE_DFX__ +EXTRA_CFLAGS += -DROCE_CC_EN +EXTRA_CFLAGS += -Werror -Wall + +EXTRA_CFLAGS += -Werror -Wno-implicit-fallthrough + +EXTRA_CFLAGS += -fstack-protector-all + +ORIGN_LINUXINCLUDE := $(LINUXINCLUDE) + +THIRDPARTY_INC = /usr/src/ofa_kernel/default/ +EXTRA_CFLAGS += -D$(OFED_VERSION) +LINUXINCLUDE := -I$(THIRDPARTY_INC)/include/ -I$(THIRDPARTY_INC)/include/uapi $(ORIGN_LINUXINCLUDE) + +EXTRA_CFLAGS += -DROCE_COMPUTE +EXTRA_CFLAGS += -DROCE_BONDING_EN +EXTRA_CFLAGS += -DROCE_STANDARD +EXTRA_CFLAGS += -DOFED_MLNX_5_8 + +# Set CFLAGS from default file directories +EXTRA_CFLAGS += -I$(srctree)/include/linux +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3 +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/host/include +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/host/hmm +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/bond +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/cq +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/dfx +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/extension +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/nic +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/rdma +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/hw +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/mag +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/mr +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/qp +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/rdma +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/srq +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3 +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/hw +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/bond +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/cfg_mgmt +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/mpu +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/bond +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/cqm + +export KLIB_BUILD +export KERN_VERSION +export MAKE +export KBUILD_EXTRA_SYMBOLS + +$(info ============== INFO ==============) +$(info Building kernel modules) +$(info Driver Version: $(VERSION)) +$(info Kernel Version: $(KERN_VERSION)) +$(info os type: $(HI1823_OS_TYPE)) +$(info Kernel Sources: $(KSRC)) +$(info Thirdparty Source: $(THIRDPARTY_INC)) +$(info linux include: $(LINUXINCLUDE)) +$(info Thirdparty Symbols: $(KBUILD_EXTRA_SYMBOLS)) +$(info build_dir: $(HI1823_BUILD_DIR)) +$(info ==================================) +$(info linux version $(LINUX_VERSION_CODE)) +$(info $(EXTRA_CFLAGS)) +$(info ==================================) + +obj-$(CONFIG_HIROCE3) += hiroce3.o + +hiroce3-y := cq/roce_cq_common.o \ + cq/roce_cq_cqe.o \ + cq/roce_cq_create.o \ + cq/roce_cq_ctrl.o \ + cq/roce_cq_destroy.o \ + extension/roce_event_extension.o \ + extension/roce_main_extension.o \ + extension/roce_mr_extension.o \ + extension/roce_netdev_extension.o \ + extension/roce_qp_extension.o \ + extension/roce_qp_post_send_extension.o \ + extension/roce_srq_extension.o \ + extension/roce_cdev_extension.o \ + roce_db.o \ + roce_main.o \ + roce_netlink.o \ + roce_event.o \ + roce_netdev.o \ + roce_mix.o \ + mr/roce_mr.o \ + roce_pd.o \ + qp/roce_qp_create.o \ + qp/roce_qp_destroy.o \ + qp/roce_qp_modify.o \ + qp/roce_qp_post_recv.o \ + qp/roce_qp_post_send.o \ + qp/roce_qp_query.o \ + roce_xrc.o \ + dfx/roce_dfx.o \ + dfx/roce_dfx_query.o \ + roce_cdev.o \ + roce_sysfs.o \ + roce_cmd.o \ + roce_cqm_cmd.o \ + bond/roce_bond_common.o \ + rdma/rdma_bitmap.o \ + rdma/rdma_comp.o \ + rdma/rdma_comp_res.o \ + rdma/rdma_comp_gid.o \ + rdma/rdma_comp_init.o \ + rdma/rdma_comp_pd.o \ + rdma/rdma_comp_mw_mr.o \ + srq/roce_srq_comm.o \ + srq/roce_srq_create.o \ + srq/roce_srq_ctrl.o \ + host/hmm/hmm_buddy.o \ + host/hmm/hmm_comp.o \ + host/hmm/hmm_comp_init.o \ + host/hmm/hmm_comp_mtt.o \ + host/hmm/hmm_comp_mw_mr.o \ + host/hmm/hmm_comp_res.o \ + host/hmm/hmm_em.o \ + host/hmm/hmm_mr.o \ + host/hmm/hmm_umem.o + +hiroce3-y +=dfx/roce_dfx_cap.o + + +SYS_TIME=$(shell date +%Y-%m-%d_%H:%M:%S) +ccflags-y += -D __TIME_STR__=\"$(SYS_TIME)\" +ccflags-y += -DGLOBAL_VERSION_STR=\"$(GLOBAL_VERSION)\" + +$(warning cflags, $(ccflags-y)) +V ?= 0 + +ccflags-y += -DHW_CONVERT_ENDIAN + +ccflags-y += -D__LINUX__ + +EXTRA_CFLAGS += -DSECUREC_EXPORT_KERNEL_SYMBOL=0 + +KERNEL_VER := $(shell uname -r 2>null) + +KERNEL_DIR := /lib/modules/$(KERNEL_VER)/build + +default: + $(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) -W modules + +clean: + rm -rf *.o *.ko *.order .*.cmd *.mod.* .H* .tm* .tmp_versions Module.symvers *.ko.unsigned null diff --git a/drivers/infiniband/hw/hiroce3/bond/roce_bond.h b/drivers/infiniband/hw/hiroce3/bond/roce_bond.h new file mode 100644 index 000000000..96e9f9f91 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/bond/roce_bond.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_bond_register.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE bond common macros, function prototypes. + */ + +#ifndef ROCE_BOND_H +#define ROCE_BOND_H + +#include <net/bonding.h> +#include <linux/netdevice.h> + +#include "hinic3_bond.h" + +#include "roce.h" +#include "roce_qp.h" +#include "roce_cmd.h" +#include "roce_verbs_attr.h" + +#define ROCE_BOND_MAX_GROUPS 2 +#define ROCE_BOND_2_100G_MAX_GROUPS 1 +#define ROCE_BOND_4_25G_MAX_GROUPS 2 + +/* Adding two roce at a time consumes one bit of the array. + * Currently, a maximum of 33 nodes are supported, and at least 17. + * To support roce hot swap, the code logic needs to be reconstructed. + */ +#define ROCE_BOND_HCA_NUM 17 + +#define ROCE_BOND_MAX_PORTS 4 +#define ROCE_BOND_MAX_FUNCS 4 + +#define ROCE_BOND_NO_VLAN_ID 0 +#define ROCE_BOND_RSVD_VLAN_ID 4095 + +#define ROCE_BOND_PORT_ENABLE 1 +#define ROCE_BOND_PORT_DISABLE 0 + +#define ROCE_BOND_ADD_MAC_TBL 1 +#define ROCE_BOND_DEL_MAC_TBL 0 + +#define ROCE_BOND_FWD_ID_TBL_ALL_BITS 32 +#define ROCE_BOND_FWD_ID_TBL_PER_BITS 3 +#define ROCE_BOND_FWD_ID_TBL_PER_BITS_MASK 0x7 + +#define ROCE_BOND_MAX_ACX_QP_NUM 32 +#define ROCE_BOND_ACX_QP_ENABLE 1 +#define ROCE_BOND_ACX_QP_DISABLE 0 + +#define ROCE_BOND_WAIT_ACTIVE_500MS 500 +enum { + ROCE_BOND_FUNC_OWN_FLAG = (1 << 0) +}; + +enum { + ROCE_BOND_FLAG = (1 << 0) +}; + +enum { + ROCE_BOND_WANT_TWO_SLAVES = 2, /* 2 slaves per bond_dev */ + ROCE_BOND_WANT_THREE_SLAVES = 3, /* 3 slaves per bond_dev */ + ROCE_BOND_WANT_FOUR_SLAVES = 4 /* 4 slaves per bond_dev */ +}; + +enum { + ROCE_BOND_WANT_TWO_SLAVES_MASK = 0x3, + ROCE_BOND_WANT_THREE_SLAVES_MASK = 0x7, + ROCE_BOND_WANT_FOUR_SLAVES_MASK = 0xf +}; + +enum { + ROCE_BOND_2_PORT_NUM = 2, + ROCE_BOND_4_PORT_NUM = 4 +}; + +enum { + ROCE_BOND_25G_PORT_SPEED = 25, + ROCE_BOND_100G_PORT_SPEED = 100 +}; + +enum { + ROCE_BOND_2_FUNC_NUM = 2, + ROCE_BOND_4_FUNC_NUM = 4 +}; + +enum { + ROCE_BOND_INVALID_HCA = -1, + ROCE_BOND_2_100G_HCA = 0, + ROCE_BOND_4_25G_HCA = 1, + ROCE_BOND_2_25G_HCA = 2 +}; + +#define SDI_BOND_SUPPORT_ROCE_FUNC_BIT 1 +#define SDI_BOND_SUPPORT_ROCE_FUNC_CNT 1 +#define SDI_BOND_SLAVES_FUNC_NUM 2 + +struct roce3_bond_slave { + struct net_device *netdev; + struct hinic3_lld_dev *lld_dev; + struct hinic3_lld_dev *ppf_dev; + struct netdev_lag_lower_state_info netdev_state; + u32 update_cnt; + u16 func_id; + u8 er_id; + bool is_ppf; +}; + +typedef void (*roce3_bond_service_func)(const char *bond_name, struct bond_attr *attr); + +struct roce3_bond_device { + char name[IFNAMSIZ]; + struct list_head entry; + struct roce3_bond_slave slaves[ROCE_BOND_MAX_FUNCS]; + struct mutex slave_lock; + u32 slave_cnt; + atomic_t next_port; + struct work_struct detach_work; + struct roce3_device *attached_rdev; + struct bond_attr attr; +}; + +bool roce3_bond_is_active(struct roce3_device *rdev); +struct net_device *roce3_bond_get_netdev(struct roce3_device *rdev); + +int roce3_add_bond_real_slave_mac(struct roce3_device *rdev, u8 *mac); +int roce3_add_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id); +void roce3_del_bond_real_slave_mac(struct roce3_device *rdev); +void roce3_del_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id); + +int roce3_bond_is_eth_port_of_netdev(struct roce3_device *rdev, struct net_device *event_ndev); + +void roce3_bond_rr_set_flow(struct roce3_device *rdev, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr); + +int roce3_bond_event_cfg_rdev(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev); +int roce3_bonded_port_event_report(struct roce3_device *rdev, const struct hinic3_event_info *event); +void roce3_handle_bonded_port_state_event(struct roce3_device *rdev); + +bool roce3_get_bond_ipsurx_en(void); +void roce3_set_bond_ipsurx_en(bool ipsurx_en); + +int roce3_bond_attach(struct roce3_device *rdev); +int roce3_bond_init(void); +void roce3_bond_pre_exit(void); +void roce3_bond_exit(void); +#endif + diff --git a/drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c b/drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c new file mode 100644 index 000000000..8fc1eddac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c @@ -0,0 +1,950 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_bond_register.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE bond common functions. + */ + +#ifdef ROCE_BONDING_EN + +#include <rdma/ib_user_verbs.h> +#include <rdma/ib_addr.h> +#include <rdma/ib_cache.h> + +#include <net/bonding.h> + +#include "bond_common_defs.h" + +#include "hinic3_hw.h" +#include "hinic3_srv_nic.h" + +#include "roce_bond.h" +#include "roce_cmd.h" +#include "roce_netdev.h" + +static bool g_roce3_bond_ipsurx_en = true; + +static LIST_HEAD(g_roce3_bond_list); +static DEFINE_MUTEX(g_roce3_bond_mutex); + +static struct workqueue_struct *g_bond_wq; + +struct roce3_detach_work { + u16 bond_id; + struct work_struct work; +}; + +struct roce3_bond_work { + char name[IFNAMSIZ]; + struct work_struct work; +}; + +bool roce3_get_bond_ipsurx_en(void) +{ + return g_roce3_bond_ipsurx_en; +} + +void roce3_set_bond_ipsurx_en(bool ipsurx_en) +{ + g_roce3_bond_ipsurx_en = ipsurx_en; +} + +static enum netdev_lag_tx_type roce3_get_tx_type_by_bond_mode(u16 bond_mode) +{ + switch (bond_mode) { + case BOND_MODE_8023AD: + case BOND_MODE_XOR: + return NETDEV_LAG_TX_TYPE_HASH; + case BOND_MODE_ACTIVEBACKUP: + return NETDEV_LAG_TX_TYPE_ACTIVEBACKUP; + default: + return NETDEV_LAG_TX_TYPE_UNKNOWN; + } +} + +static bool roce3_bond_mode_is_supported(u16 bond_mode) +{ + enum netdev_lag_tx_type tx_type = roce3_get_tx_type_by_bond_mode(bond_mode); + if ((tx_type != NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) && (tx_type != NETDEV_LAG_TX_TYPE_HASH)) { + pr_err("[ROCE, ERR] %s: Failed to support bond mode(%d)\n", __func__, tx_type); + return false; + } + return true; +} + +static bool is_hinic3_netdev(struct net_device *netdev) +{ + return (hinic3_get_lld_dev_by_netdev(netdev) != NULL); +} + +static bool roce3_can_do_bond(struct bonding *bond) +{ + bool ret = false; + int slave_cnt = 0; + struct slave *slave = NULL; + struct list_head *iter = NULL; + struct hinic3_lld_dev *lld_dev = NULL; + struct hinic3_lld_dev *ppf_dev = NULL; + + if (!bond || !roce3_bond_mode_is_supported(bond->params.mode)) { + return ret; + } + + rcu_read_lock(); + bond_for_each_slave_rcu(bond, slave, iter) + { + lld_dev = hinic3_get_lld_dev_by_netdev(slave->dev); + if (!lld_dev) { + goto out; + } + + if (!hinic3_support_roce(lld_dev->hwdev, NULL)) { + goto out; + } + + if (!ppf_dev) { + ppf_dev = hinic3_get_ppf_lld_dev(lld_dev); + if (!ppf_dev) { + goto out; + } + } + + if (hinic3_get_ppf_lld_dev(lld_dev) != ppf_dev) { + goto out; + } + + slave_cnt++; + pr_info("%s:can do bond? slave_cnt(%d), slave_name(%s)", __func__, slave_cnt, slave->dev->name); + } + + ret = (slave_cnt == ROCE_BOND_2_FUNC_NUM); +out: + rcu_read_unlock(); + return ret; +} + +struct net_device *roce3_bond_get_netdev(struct roce3_device *rdev) +{ + int i; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct net_device *ret_dev = NULL; + struct slave *slave = NULL; + + mutex_lock(&g_roce3_bond_mutex); + if (!bond_dev) { + mutex_unlock(&g_roce3_bond_mutex); + return ret_dev; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + rcu_read_lock(); + slave = bond_slave_get_rcu(bond_dev->slaves[i].netdev); + rcu_read_unlock(); + if (!slave) { + continue; + } + if (bond_is_active_slave(slave)) { + if (netif_running(bond_dev->slaves[i].netdev) && netif_carrier_ok(bond_dev->slaves[i].netdev)) { + ret_dev = bond_dev->slaves[i].netdev; + } else if (netif_running(bond_dev->slaves[(i + 1) % bond_dev->slave_cnt].netdev) && + netif_carrier_ok(bond_dev->slaves[(i + 1) % bond_dev->slave_cnt].netdev)) { + ret_dev = bond_dev->slaves[(i + 1) % bond_dev->slave_cnt].netdev; + } else { + ret_dev = bond_dev->slaves[i].netdev; + } + dev_hold(ret_dev); + mutex_unlock(&bond_dev->slave_lock); + mutex_unlock(&g_roce3_bond_mutex); + return ret_dev; + } + } + mutex_unlock(&bond_dev->slave_lock); + mutex_unlock(&g_roce3_bond_mutex); + return ret_dev; +} + +void roce3_bond_rr_set_flow(struct roce3_device *rdev, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr) +{ + u32 bond_tx_hash; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!bond_dev) { + return; + } + + bond_tx_hash = (u32)atomic_add_return(1, &bond_dev->next_port); + rqp->tx_hash_value = bond_tx_hash; + + qp_attr->path_info.dw0.bs.bond_tx_hash_value = (u16)bond_tx_hash; +} + +static int roce3_bond_modify_mac_tbl_for_sdi(struct roce3_device *rdev, u8 *mac, roce3_modify_mac_tbl modify_mac_tbl) +{ + u16 func_id; + int ret; + + for (func_id = 0; func_id < SDI_BOND_SLAVES_FUNC_NUM; func_id++) { + if (func_id == rdev->glb_func_id) { + continue; + } + + ret = modify_mac_tbl(rdev->hwdev, mac, ROCE_BOND_RSVD_VLAN_ID, rdev->glb_func_id, func_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to modify mac table, ret(%d)\n", __func__, ret); + return ret; + } + } + + return 0; +} + +int roce3_add_bond_real_slave_mac(struct roce3_device *rdev, u8 *mac) +{ + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct roce3_bond_slave *slave = NULL; + int ret; + int i; + + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: Failed to find bond_dev\n", __func__); + return -EINVAL; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + ret = roce3_add_mac_tbl_mac_entry(rdev->hwdev, mac, ROCE_BOND_RSVD_VLAN_ID, rdev->glb_func_id, slave->func_id); + if (ret != 0) { + mutex_unlock(&bond_dev->slave_lock); + pr_err("[ROCE, ERR] %s: Failed to add mac_vlan entry, ret(%d)\n", __func__, ret); + return ret; + } + + if (slave->func_id != rdev->glb_func_id) { + /* The IPSU MAC table is used for fast forwarding. Even if the addition fails, the forwarding information + can still be obtained by checking the MAC table later, without judging the execution result. */ + (void)roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, mac, 0, rdev->glb_func_id, slave->er_id); + } + } + mutex_unlock(&bond_dev->slave_lock); + + if (rdev->sdi_bond_name != NULL) { + ret = roce3_bond_modify_mac_tbl_for_sdi(rdev, mac, roce3_add_mac_tbl_mac_entry); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to modify mac table of sdi, ret(%d)\n", __func__, ret); + return ret; + } + } + + return 0; +} + +int roce3_add_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id) +{ + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct roce3_bond_slave *slave = NULL; + int ret; + int i; + + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: Failed to find bond_dev\n", __func__); + return -EINVAL; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id == rdev->glb_func_id) { + continue; + } + + ret = roce3_add_mac_tbl_mac_entry(rdev->hwdev, mac, vlan_id, slave->func_id, slave->func_id); + if (ret != 0) { + mutex_unlock(&bond_dev->slave_lock); + pr_err("[ROCE, ERR] %s: Failed to add mac_vlan entry, ret(%d)\n", __func__, ret); + return ret; + } + + /* The IPSU MAC table is used for fast forwarding. Even if the addition fails, the forwarding information + can still be obtained by checking the MAC table later, without judging the execution result. */ + (void)roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, mac, vlan_id, rdev->glb_func_id, slave->er_id); + } + mutex_unlock(&bond_dev->slave_lock); + + return 0; +} + +void roce3_del_bond_real_slave_mac(struct roce3_device *rdev) +{ + int i; + struct roce3_bond_slave *slave = NULL; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!bond_dev) { + return; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id != rdev->glb_func_id) { + (void)roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, rdev->mac, 0, rdev->glb_func_id, slave->er_id); + } + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, rdev->mac, ROCE_BOND_RSVD_VLAN_ID, rdev->glb_func_id, + slave->func_id); + } + mutex_unlock(&bond_dev->slave_lock); + + if (rdev->sdi_bond_name != NULL) { + (void)roce3_bond_modify_mac_tbl_for_sdi(rdev, rdev->mac, roce3_del_mac_tbl_mac_entry); + } +} + +void roce3_del_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id) +{ + int i; + struct roce3_bond_slave *slave = NULL; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!bond_dev) { + return; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id == rdev->glb_func_id) { + continue; + } + + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, mac, vlan_id, slave->func_id, slave->er_id); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, mac, vlan_id, rdev->glb_func_id, slave->er_id); + } + mutex_unlock(&bond_dev->slave_lock); +} + +bool roce3_bond_is_active(struct roce3_device *rdev) +{ + return (rdev->bond_dev != NULL); +} + +int roce3_bond_event_cfg_rdev(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev) +{ + int i; + struct roce3_bond_device *bond_dev = NULL; + + if (lld_dev == NULL) { + pr_err("[ROCE, ERR] %s: Lld_dev is null\n", __func__); + return -EINVAL; + } + + if (uld_dev != NULL) { + *rdev = (struct roce3_device *)uld_dev; + return 0; + } + + mutex_lock(&g_roce3_bond_mutex); + list_for_each_entry(bond_dev, &g_roce3_bond_list, entry) + { + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (bond_dev->slaves[i].lld_dev == lld_dev) { + *rdev = bond_dev->attached_rdev; + mutex_unlock(&bond_dev->slave_lock); + goto out; + } + } + mutex_unlock(&bond_dev->slave_lock); + } + +out: + mutex_unlock(&g_roce3_bond_mutex); + return *rdev ? 0 : -EINVAL; +} + +int roce3_bonded_port_event_report(struct roce3_device *rdev, const struct hinic3_event_info *event) +{ + u32 type = HINIC3_SRV_EVENT_TYPE(event->service, event->type); + if ((type != HINIC3_SRV_EVENT_TYPE(EVENT_SRV_NIC, EVENT_NIC_LINK_UP)) && + (type != HINIC3_SRV_EVENT_TYPE(EVENT_SRV_NIC, EVENT_NIC_LINK_DOWN))) { + pr_err("[ROCE] %s: event_service(%d), type(%d)\n", __func__, event->service, event->type); + return -ERANGE; + } + + return 0; +} + +int roce3_bond_is_eth_port_of_netdev(struct roce3_device *rdev, struct net_device *event_ndev) +{ + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct net_device *tmp_ndev = NULL; + int ret; + int i; + /* judge current net device */ + tmp_ndev = rdev->ndev; + ret = roce3_is_eth_port_of_netdev(tmp_ndev, event_ndev); + if (ret != 0) { + return 1; + } + + if (!bond_dev) { + return 0; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (roce3_is_eth_port_of_netdev(bond_dev->slaves[i].netdev, event_ndev)) { + mutex_unlock(&bond_dev->slave_lock); + return 1; + } + } + mutex_unlock(&bond_dev->slave_lock); + + return 0; +} + +struct roce3_bond_device *roce3_get_bond_dev(const char *bond_name) +{ + struct roce3_bond_device *bdev = NULL; + + list_for_each_entry(bdev, &g_roce3_bond_list, entry) + { + if (!strcmp(bdev->name, bond_name)) { + return bdev; + } + } + + return NULL; +} + +struct roce3_bond_device *roce3_get_bond_dev_by_name(const char *bond_name) +{ + struct roce3_bond_device *bdev = NULL; + + mutex_lock(&g_roce3_bond_mutex); + bdev = roce3_get_bond_dev(bond_name); + mutex_unlock(&g_roce3_bond_mutex); + return bdev; +} + +void roce3_bond_init_slave(struct roce3_bond_slave *slave, struct bond_tracker *tracker, int index, + struct bond_attr *attr) +{ + void *hwdev; + + slave->func_id = index; + slave->netdev = tracker->ndev[index]; + + dev_hold(slave->netdev); + pr_info("[ROCE, INFO] %s: dev_hold: name(%s),tracker_cnt(%d)\n", + __func__, slave->netdev->name, tracker->cnt); + slave->lld_dev = hinic3_get_lld_dev_by_netdev(slave->netdev); + slave->ppf_dev = hinic3_get_ppf_lld_dev(slave->lld_dev); + hwdev = slave->lld_dev->hwdev; + slave->is_ppf = hinic3_func_type(hwdev) == TYPE_PPF; + slave->er_id = hinic3_er_id(hwdev); + slave->netdev_state.link_up = tracker->netdev_state[index].link_up; + slave->netdev_state.tx_enabled = tracker->netdev_state[index].tx_enabled; + + if (slave->is_ppf) { + attr->first_roce_func = slave->func_id; + } else { + hinic3_detach_service(slave->lld_dev, SERVICE_T_ROCE); + } + return; +} + +bool roce3_bond_before_active_check(struct bond_tracker *tracker, struct bond_attr *attr) +{ + int i; + struct hinic3_lld_dev *lld_dev = NULL; + struct hinic3_lld_dev *ppf_dev = NULL; + + if (!roce3_bond_mode_is_supported(attr->bond_mode)) { + return false; + } + + for (i = 0; i < ROCE_BOND_2_FUNC_NUM; i++) { + lld_dev = hinic3_get_lld_dev_by_netdev(tracker->ndev[i]); + if (!lld_dev) { + pr_err("[ROCE, ERR] %s: get lld dev err\n", __func__); + return false; + } + + if (!hinic3_support_roce(lld_dev->hwdev, NULL)) { + pr_err("[ROCE, ERR] %s: Not support roce\n", __func__); + return false; + } + + if (!ppf_dev) { + ppf_dev = hinic3_get_ppf_lld_dev(lld_dev); + if (!ppf_dev) { + pr_err("[ROCE, ERR] %s: get ppf dev err\n", __func__); + return false; + } + } + + if (hinic3_get_ppf_lld_dev(lld_dev) != ppf_dev) { + return false; + } + } + + return true; +} + +void roce3_detach_nic_bond_work(struct work_struct *work) +{ + struct roce3_detach_work *detach_work = container_of(work, struct roce3_detach_work, work); + + hinic3_bond_detach(detach_work->bond_id, HINIC3_BOND_USER_ROCE); + + kfree(detach_work); +} + +static void roce3_attach_bond_work(struct work_struct *_work) +{ + u16 bond_id; + struct roce3_bond_work *work = container_of(_work, struct roce3_bond_work, work); + pr_info("roce_attach: %s: work_name(%s)\n", __func__, work->name); + hinic3_bond_attach(work->name, HINIC3_BOND_USER_ROCE, &bond_id); + + kfree(work); + return; +} +void roce3_deatch_bond(u16 bond_id) +{ + struct roce3_detach_work *detach_work = NULL; + + detach_work = kmalloc(sizeof *detach_work, GFP_KERNEL); + if (!detach_work) { + pr_err("[ROCE, ERR] %s: malloc failed, bond id(%d)\n", __func__, bond_id); + return; + } + + detach_work->bond_id = bond_id; + INIT_WORK(&detach_work->work, roce3_detach_nic_bond_work); + queue_work(g_bond_wq, &detach_work->work); +} + +bool roce3_bond_tracker_get(const char *bond_name, struct bond_tracker *tracker) +{ + int ret = 0; + + ret = hinic3_get_bond_tracker_by_name(bond_name, tracker); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: get bond tracker failed name(%s), ret(%d)\n", __func__, bond_name, ret); + return false; + } + if (!tracker->is_bonded) { + pr_err("[ROCE, ERR] %s: tracker is NOT bond (%s)\n", __func__, bond_name); + return false; + } + if (tracker->cnt == ROCE_BOND_2_FUNC_NUM) { + return true; + } + + pr_err("[ROCE, ERR] %s: get tracker cnt fail, cnt(%d) name(%s)\n", __func__, tracker->cnt, bond_name); + return false; +} + +void roce3_before_bond_active(const char *bond_name, struct bond_attr *attr) +{ + struct roce3_bond_device *bond_dev = NULL; + struct roce3_bond_slave *slave = NULL; + struct bond_tracker tracker; + int i; + + if (!roce3_bond_tracker_get(bond_name, &tracker)) { + pr_err("[ROCE, ERR] %s: get bond tracker failed\n", __func__); + goto err; + } + + if (!roce3_bond_before_active_check(&tracker, attr)) { + pr_err("[ROCE, ERR] %s: active check failed\n", __func__); + goto err; + } + + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (bond_dev) { + pr_info("[ROCE, INFO] %s: Find exist bond device\n", __func__); + return; + } + + bond_dev = kzalloc(sizeof *bond_dev, GFP_KERNEL); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: Malloc memory failed\n", __func__); + goto err; + } + + (void)strncpy(bond_dev->name, bond_name, strlen(bond_name)); + + bond_dev->attr = *attr; + bond_dev->slave_cnt = tracker.cnt; + mutex_init(&bond_dev->slave_lock); + + for (i = 0; i < ROCE_BOND_2_FUNC_NUM; i++) { + slave = &bond_dev->slaves[i]; + roce3_bond_init_slave(slave, &tracker, i, attr); + } + + hinic3_detach_service(bond_dev->slaves[0].ppf_dev, SERVICE_T_ROCE); + mutex_lock(&g_roce3_bond_mutex); + list_add_tail(&bond_dev->entry, &g_roce3_bond_list); + mutex_unlock(&g_roce3_bond_mutex); + return; +err: + roce3_deatch_bond(attr->bond_id); + return; +} + +void roce3_after_bond_active(const char *bond_name, struct bond_attr *attr) +{ + int ret; + struct roce3_bond_device *bond_dev = NULL; + + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + return; + } + + ret = hinic3_attach_service(bond_dev->slaves[0].ppf_dev, SERVICE_T_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to attach roce device, ret(%d), bond name(%s)\n", __func__, ret, bond_name); + } + + return; +} + +void roce3_after_bond_modify(const char *bond_name, struct bond_attr *attr) +{ + struct roce3_bond_device *bond_dev = NULL; + struct bond_tracker tracker; + int i; + int j; + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + return; + } + + if (hinic3_get_bond_tracker_by_name(bond_name, &tracker) != 0) { + pr_err("[ROCE, ERR] %s: get bond tracker failed\n", __func__); + return; + } + + bond_dev->attr = *attr; + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < BOND_PORT_MAX_NUM; i++) { + for (j = 0; j < bond_dev->slave_cnt; j++) { + if (bond_dev->slaves[j].netdev != tracker.ndev[i]) { + continue; + } + bond_dev->slaves[j].netdev_state.link_up = tracker.netdev_state[i].link_up; + bond_dev->slaves[j].netdev_state.tx_enabled = tracker.netdev_state[i].tx_enabled; + break; + } + } + mutex_unlock(&bond_dev->slave_lock); + + return; +} + +void roce3_before_bond_deactive(const char *bond_name, struct bond_attr *attr) +{ + return; +} + +void roce3_after_bond_deactive(const char *bond_name, struct bond_attr *attr) +{ + return; +} + +void roce3_bond_destroy(const char *bond_name) +{ + int ret; + int i; + struct roce3_bond_device *bond_dev = NULL; + + mutex_lock(&g_roce3_bond_mutex); + bond_dev = roce3_get_bond_dev(bond_name); + if (bond_dev) { + list_del(&bond_dev->entry); + } + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + mutex_unlock(&g_roce3_bond_mutex); + return; + } + if (bond_dev->attached_rdev != NULL) { + bond_dev->attached_rdev->bond_dev = NULL; + } + mutex_unlock(&g_roce3_bond_mutex); + + hinic3_detach_service(bond_dev->slaves[0].ppf_dev, SERVICE_T_ROCE); + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + ret = hinic3_attach_service(bond_dev->slaves[i].lld_dev, SERVICE_T_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to attach roce device, ret(%d)\n", __func__, ret); + } + dev_put(bond_dev->slaves[i].netdev); + pr_info("[ROCE, INFO] %s: dev_put: name(%s),slave_cnt(%d), slave_name(%s)\n", + __func__, bond_name, bond_dev->slave_cnt, bond_dev->slaves[i].netdev->name); + } + bond_dev->slave_cnt = 0; + mutex_unlock(&bond_dev->slave_lock); + + hinic3_bond_detach(bond_dev->attr.bond_id, HINIC3_BOND_USER_ROCE); + kfree(bond_dev); + return; +} + +void roce3_before_bond_modify(const char *bond_name, struct bond_attr *attr) +{ + struct roce3_bond_device *bond_dev = NULL; + struct bond_tracker tracker; + int i; + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + return; + } + + if (hinic3_get_bond_tracker_by_name(bond_name, &tracker) != 0) { + pr_err("[ROCE, ERR] %s: get bond tracker failed\n", __func__); + return; + } + + if (tracker.cnt == bond_dev->slave_cnt) { + bond_dev->attr = *attr; + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (bond_dev->slaves[i].is_ppf) { + attr->first_roce_func = bond_dev->slaves[i].func_id; + break; + } + } + return; + } + + if (tracker.cnt > bond_dev->slave_cnt) { + pr_err("[ROCE, ERR] %s: Add slave is not support, bond name(%s)\n", __func__, bond_name); + return; + } + + if (tracker.cnt < ROCE_BOND_2_FUNC_NUM) { + roce3_bond_destroy(bond_dev->name); + return; + } + + return; +} + +static roce3_bond_service_func g_roce3_bond_proc[] = { + roce3_before_bond_active, + roce3_after_bond_active, + roce3_before_bond_modify, + roce3_after_bond_modify, + roce3_before_bond_deactive, + roce3_after_bond_deactive, +}; + +void roce3_bond_service_proc(const char *bond_name, void *bond_attr, enum bond_service_proc_pos pos) +{ + struct bond_attr *attr = (struct bond_attr *)bond_attr; + + if (bond_name == NULL) { + pr_err("[ROCE, ERR] %s: Bond_name is NULL\n", __func__); + return; + } + + if (pos >= BOND_POS_MAX) { + pr_err("[ROCE, ERR] %s: The pos is out of the range of proc_func\n", __func__); + return; + } + + if (g_roce3_bond_proc[pos] != NULL) { + g_roce3_bond_proc[pos](bond_name, attr); + } +} + +int roce3_bond_attach(struct roce3_device *rdev) +{ + int i; + int ret = 0; + struct roce3_bond_device *bond_dev; + + mutex_lock(&g_roce3_bond_mutex); + list_for_each_entry(bond_dev, &g_roce3_bond_list, entry) + { + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (rdev->ndev != bond_dev->slaves[i].netdev) { + continue; + } + + if (bond_dev->attached_rdev == NULL) { + bond_dev->attached_rdev = rdev; + rdev->bond_dev = bond_dev; + } else { + ret = -EEXIST; + } + mutex_unlock(&bond_dev->slave_lock); + goto out; + } + mutex_unlock(&bond_dev->slave_lock); + } +out: + mutex_unlock(&g_roce3_bond_mutex); + return ret; +} + +static void roce3_detach_bond_work(struct work_struct *_work) +{ + struct roce3_bond_work *work = container_of(_work, struct roce3_bond_work, work); + + roce3_bond_destroy(work->name); + + kfree(work); + return; +} + +void roce3_queue_bond_work(struct net_device *upper_netdev, work_func_t func) +{ + struct roce3_bond_work *work; + struct bonding *bond = netdev_priv(upper_netdev); + + if (!bond) { + pr_info("%s: (name:%s) has no bond dev.\n", __func__, upper_netdev->name); + return; + } + + work = kzalloc(sizeof *work, GFP_KERNEL); + if (!work) { + return; + } + + (void)strncpy(work->name, upper_netdev->name, strlen(upper_netdev->name)); + INIT_WORK(&work->work, func); + queue_work(g_bond_wq, &work->work); + return; +} + +int roce3_bond_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *net_dev = NULL; + struct netdev_notifier_changeupper_info *info = NULL; + struct net_device *upper_netdev = NULL; + + info = (struct netdev_notifier_changeupper_info *)ptr; + net_dev = netdev_notifier_info_to_dev(ptr); + if (net_eq(dev_net(net_dev), &init_net) == 0) { + return NOTIFY_DONE; + } + + if (event != NETDEV_CHANGEUPPER) { + return NOTIFY_DONE; + } + + if (!is_hinic3_netdev(net_dev)) { + return NOTIFY_DONE; + } + + upper_netdev = info->upper_dev; + if (upper_netdev == NULL) { + return NOTIFY_DONE; + } + + if (!netif_is_lag_master(upper_netdev)) { + return NOTIFY_DONE; + } + + if (!roce3_can_do_bond(netdev_priv(upper_netdev))) { + roce3_queue_bond_work(upper_netdev, roce3_detach_bond_work); + return NOTIFY_DONE; + } + + roce3_queue_bond_work(upper_netdev, roce3_attach_bond_work); + return NOTIFY_DONE; +} + +static struct notifier_block nb_netdevice = { + .notifier_call = roce3_bond_netdev_event +}; + +int roce3_bond_init(void) +{ + int ret; + struct net_device *upper_netdev; + + g_bond_wq = alloc_ordered_workqueue("roce3-bond-wq", 0); + if (!g_bond_wq) { + pr_err("[ROCE, ERR] %s: Failed to alloc workqueue\n", __func__); + return -ENOMEM; + } + + ret = register_netdevice_notifier(&nb_netdevice); + if (ret) { + pr_err("[ROCE, ERR] %s: Failed to register netdevice notifier(%d)\n", __func__, ret); + goto nb_err; + } + + ret = hinic3_bond_register_service_func(HINIC3_BOND_USER_ROCE, roce3_bond_service_proc); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to register bond(%d)\n", __func__, ret); + goto err; + } + + rtnl_lock(); + for_each_netdev(&init_net, upper_netdev) + { + if (netif_is_bond_master(upper_netdev) && roce3_can_do_bond(netdev_priv(upper_netdev))) { + roce3_queue_bond_work(upper_netdev, roce3_attach_bond_work); + } + } + rtnl_unlock(); + + return 0; +err: + unregister_netdevice_notifier(&nb_netdevice); +nb_err: + destroy_workqueue(g_bond_wq); + return ret; +} + +void roce3_bond_pre_exit(void) +{ + int ret; + + ret = hinic3_bond_unregister_service_func(HINIC3_BOND_USER_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to unregister service func(%d)\n", __func__, ret); + } + + unregister_netdevice_notifier(&nb_netdevice); + destroy_workqueue(g_bond_wq); +} + +void roce3_bond_exit(void) +{ + struct roce3_bond_device *bond_dev = NULL; + int i; + while (!list_empty(&g_roce3_bond_list)) { + bond_dev = list_first_entry(&g_roce3_bond_list, struct roce3_bond_device, entry); + list_del(&bond_dev->entry); + for (i = 0; i < bond_dev->slave_cnt; i++) { + pr_info("[ROCE, INFO] %s: EXIT dev_put: bond_name(%s),slave_cnt(%d), slave_name(%s)\n", + __func__, bond_dev->name, bond_dev->slave_cnt, bond_dev->slaves[i].netdev->name); + dev_put(bond_dev->slaves[i].netdev); + } + hinic3_bond_detach(bond_dev->attr.bond_id, HINIC3_BOND_USER_ROCE); + kfree(bond_dev); + } +} + +#endif diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq.h b/drivers/infiniband/hw/hiroce3/cq/roce_cq.h new file mode 100644 index 000000000..71259a0d4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq.h + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ common header. + */ + +#ifndef ROCE_CQ_H +#define ROCE_CQ_H + +#include <rdma/ib_verbs.h> +#include <linux/slab.h> + +#include "hinic3_hw.h" +#include "hinic3_rdma.h" + +#include "rdma_context_format.h" + +#include "roce.h" +#include "roce_compat.h" +#include "roce_srq.h" +#include "roce_xrc.h" +#include "roce_user.h" +#include "hinic3_hmm.h" + +#define ROCE_CQN_INVLD 0xFFFFFFFF + +/* DB type of ARM_CQ */ +enum { + ROCE_CQ_DB_REQ_NOT_SOL = 1, + ROCE_CQ_DB_REQ_NOT = 2 +}; + +#define CQ_GPA_SIG_LEN 3 +#define CQ_DW_TO_BYTE 4 + +/* the type of err cqe +IB compliant completion with error syndrome: + 0x01 - Local Length Error () + 0x02 - Local QP Operation Error + 0x04 - Local Protection Error + 0x05 - Work Request Flushed Error + 0x06 - Memory Window Bind Error + 0x10 - Bad Response Error + 0x11 - Local Access Error + 0x12 - Remote Invalid Request Error + 0x13 - Remote Access Error + 0x14 - Remote Operation Error + 0x15 - Transport Retry Counter Exceeded + 0x16 - RNR Retry Counter Exceeded + 0x22 - Remote Aborted Error + other - reserved +Syndrome is defined according to the InfiniBand Architecture Specification, +Volume 1. For a detailed explanation of the syndromes, refer to the Software +Transport Interface and Software Transport Verbs chapters of the IB specifica- +tion. +*/ +enum roce3_cqe_syndrome { + ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01, + ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02, + ROCE_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04, + ROCE_CQE_SYNDROME_WR_FLUSH_ERR = 0x05, + + ROCE_CQE_SYNDROME_MW_BIND_ERR = 0x06, + ROCE_CQE_SYNDROME_BAD_RESP_ERR = 0x10, + + ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11, + ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, + ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13, + ROCE_CQE_SYNDROME_REMOTE_OP_ERR = 0x14, + ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15, + + ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16, + + ROCE_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, + ROCE_CQE_SYNDROME_MAX = 0x23 +}; + +/* +1.Same type of operation as SQ WQE +8'h00-Send +8'h01-Send with Invalidate +8'h02-Send with Immediate Data +8'h03-reserved + +8'h04-RDMA Write +8'h05-RDMA Write with Immediate Data +8'h06-reserved +8'h07-reserved + +8'h08-RDMA Read +8'h09-reserved +8'h0a-reserved +8'h0b-reserved + +8'h0c-Atomic Compare & Swap +8'h0d-Atomic Fetch & Add +8'h0e-Atomic Masked Compare & Swap (Extended Atomic operation) +8'h0f-Atomic Masked Fetch & Add (Extended Atomic operation) + +8'h10-Fast Register PMR +8'h11-Local Invalidate +8'h12-Bind Memory Window Type1/2 +8'h13-Local opreation(Extended for further local opreation) +other-Reserved + +2.Receive +00000 - RDMA Write with Immediate +00001 - Send +00010 - Send with Immediate +00011 - Send & Invalidate + +3.The following are general +11110 Error coding +10110 Resize coding +*/ +enum roce3_cqe_send_opcode { + ROCE_OPCODE_SEND = 0x0, + ROCE_OPCODE_SEND_WITH_INV = 0x1, + ROCE_OPCODE_SEND_WITH_IMM = 0x2, + /* 0x3 reserved */ + + ROCE_OPCODE_RDMA_WRITE = 0x4, + ROCE_OPCODE_RDMA_WRITE_WITH_IMM = 0x5, + /* 0x6 and 0x7 reserved */ + + ROCE_OPCODE_RDMA_READ = 0x8, + /* 0x9~0xb reserved */ + + ROCE_OPCODE_ATOMIC_COMP_AND_SWP = 0xc, + ROCE_OPCODE_ATOMIC_FETCH_AND_ADD = 0xd, + ROCE_OPCODE_ATOMIC_MASKED_COMP_AND_SWP = 0xe, + ROCE_OPCODE_ATOMIC_MASKED_FETCH_AND_ADD = 0xf, + + ROCE_OPCODE_FAST_REG_PMR = 0x10, + ROCE_OPCODE_LOCAL_INV = 0x11, + ROCE_OPCODE_BIND_TYPE2_MW = 0x12, + ROCE_OPCODE_REG_SIG_MR = 0x13, + + ROCE_OPCODE_RESIZE_CQE = 0x16, + ROCE_OPCODE_ERR = 0x1e, + ROCE_OPCODE_CQE_UNUSED = 0x1f /* Be used in new CQ buf when reszie cq */ +}; + +enum roce3_cqe_recv_opcode { + ROCE_RECV_OPCODE_RDMA_WRITE_WITH_IMM = 0x0, + ROCE_RECV_OPCODE_SEND = 0x1, + ROCE_RECV_OPCODE_SEND_WITH_IMM = 0x2, + ROCE_RECV_OPCODE_SEND_WITH_INV = 0x3 +}; + +/* Define the state type of the CQ */ +enum cq_state { + ROCE_CQ_STATE_INVALID = 0x0, + ROCE_CQ_STATE_ERR = 0x1, + ROCE_CQ_STATE_OVERFLOW = 0x2, + ROCE_CQ_STATE_VALID = 0xf, + ROCE_CQ_STATE_MEM_INIT = 0xa /* Initial value of Host Memory */ +}; + +#define ROCE_CQ_TIME_OUT_CHECK_VALUE 0xe +#define ROCE_CQ_STATE_CHECK_VALUE 0x0 + +#define ROCE_CQE_RQ_INLINE 1 +#define ROCE_CQE_RQ_NORMAL 0 +#define ROCE_CQE_SEND_COMP 1 +#define ROCE_CQE_RECV_COMP 0 + +#define ATOMIC_DATA_LEN 8 /* Specified as 8B by protocol */ + +#define ROCE_CQE_INVALID_VALUE 0xff +#define ROCE_CQ_RESIZE_POLL_TIMES 100 + +/* roce Commands, bufs and data structures related to cq */ +struct roce3_cq_query_outbuf { + struct roce_cq_context cqc; +}; + +struct roce3_cq_buf { + struct tag_cqm_buf *buf; /* pointer to describe the buf structure b cqm */ + struct rdma_mtt mtt; /* the mtt struct used by kernel mode and user mode to discribe buf */ + int entry_size; /* the size of cqe */ + int buf_size; /* the size of cq_buf */ +}; + +struct roce3_cq_resize_buf { + struct roce3_cq_buf buf; /* the size of buf that was resized */ + int cqe; /* the number of resized cqe */ +}; + +struct roce3_cq { + struct ib_cq ibcq; + cqm_queue_s *cqm_cq; /* Save the handle obtained from cqm */ + struct roce3_db db; /* The address information of the software DB that stores the CI user mode/kernel mode */ + __be32 *set_ci_db; /* Kernel-mode software DB */ + u32 cons_index; /* consumer pointer */ + + u32 arm_sn; /* the serial number of arm */ + int arm_flag; /* Used to determine whether the arm command has been sent, to avoid repeated sending */ + u32 cqn; + unsigned int vector; /* associated to the eq used */ + struct roce3_cq_buf buf; /* pointer describing the buf structure of cqm */ + struct roce3_cq_resize_buf *resize_buf; /* resize buf struction */ + + spinlock_t lock; /* Need to lock when operating cq */ + struct mutex resize_mutex; /* resize the mutex of cq */ + struct ib_umem *umem; /* record the infomation mapped by User-mode buf */ + struct ib_umem *resize_umem; /* record the infomation mapped by buf which the User-mode resized */ + + struct list_head send_qp_list; /* send queue qp */ + struct list_head recv_qp_list; /* receive queue qp */ + + int reset_notify_added; + struct list_head reset_notify; + + void (*reset_flow_comp)(struct roce3_cq *); +}; + +/* cross ibcroce3_e_cq */ +static inline struct roce3_cq *to_roce3_cq(const struct ib_cq *ibcq) +{ + return container_of(ibcq, struct roce3_cq, ibcq); +} + +/* obroce3_roce_cq crossing cqm */ +static inline struct roce3_cq *cqmobj_to_roce3_cq(const cqm_object_s *object) +{ + cqm_queue_s *cqm_cq; + cqm_cq = container_of(object, cqm_queue_s, object); + return (struct roce3_cq *)cqm_cq->priv; +} + +/* Used when destroy QP */ +void roce3_cq_clean(struct roce3_cq *cq, u32 qpn, struct roce3_srq *srq); +void roce3_cq_async_event(struct roce3_device *rdev, struct roce3_cq *cq, int type); +void roce3_cq_clean_process(struct roce3_cq *cq, u32 qpn, struct roce3_srq *srq); +void roce3_cq_put_umem(struct roce3_device *rdev, struct roce3_cq_buf *buf, struct ib_umem **umem); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(OFED_MLNX_5_8) +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_udata *udata, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe); +int roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_udata *udata, struct roce3_cq *rcq, u32 index); +#else +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_ucontext *context, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe); +struct ib_cq *roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata, u32 index); +#endif + +void *roce3_get_sw_cqe(struct roce3_cq *cq, unsigned int n); +void *roce3_get_cqe_from_buf(struct roce3_cq_buf *buf, unsigned int n); +void roce3_cq_set_ci(struct roce3_cq *cq); +void roce3_cq_buf_init(struct roce3_cq_buf *buf); +void *roce3_get_cqe(struct roce3_cq *cq, unsigned int n); +void roce_reset_flow_comp(struct roce3_cq *rcq); + +void roce3_lock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __acquires(&roce3_send_cq->lock) + __acquires(&roce3_recv_cq->lock); +void roce3_unlock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __releases(&roce3_send_cq->lock) + __releases(&roce3_recv_cq->lock); + +#endif // ROCE_CQ_H diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c new file mode 100644 index 000000000..d6fbef241 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_common.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE CQ kernel functions. + */ + +#include <linux/slab.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_mix.h" +#include "roce_xrc.h" +#include "roce_user.h" +#include "roce_cq.h" +#include "roce_pub_cmd.h" +#include "hinic3_hmm.h" + +/* **************************************************************************** + Prototype : roce3_cq_async_event + Description : roce3_cq_async_event + Input : struct roce3_device *rdev + struct roce3_cq *cq + int type + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_async_event(struct roce3_device *rdev, struct roce3_cq *cq, int type) +{ + struct ib_cq *ibcq = &cq->ibcq; + struct ib_event event; + + memset(&event, 0, sizeof(event)); + if (type != ROCE_EVENT_TYPE_CQ_ERROR) { + dev_warn_ratelimited(rdev->hwdev_hdl, "[ROCE] %s: Unexpected event type(0x%x) on CQ(%06x), func_id(%d)\n", + __func__, type, cq->cqn, rdev->glb_func_id); + return; + } + + if (ibcq->event_handler) { + event.device = ibcq->device; + event.event = IB_EVENT_CQ_ERR; + event.element.cq = ibcq; + ibcq->event_handler(&event, ibcq->cq_context); + } +} + +/* **************************************************************************** + Prototype : roce3_cq_buf_init + Description : roce3_cq_buf_init + Input : struct roce3_cq_buf *buf + Output : None + + 1.Date : 2015/11/9 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_buf_init(struct roce3_cq_buf *buf) +{ + /* optype was initialized into ROCE_OPCODE_CQE_UNUSED(0x1f) */ + memset(buf->buf->direct.va, ROCE_CQE_INVALID_VALUE, + (unsigned long)((unsigned)buf->buf_size)); +} + +/* **************************************************************************** + Prototype : roce3_cq_put_umem + Description : Release umem and corresponding mtt, corresponding to put + Input : struct roce3_device *rdev + struct roce3_cq_buf *buf + struct ib_umem **umem + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_put_umem(struct roce3_device *rdev, struct roce3_cq_buf *buf, struct ib_umem **umem) +{ + /* free MTT of Buffer */ + hmm_rdma_mtt_free(rdev->hwdev, &buf->mtt, SERVICE_T_ROCE); + + /* release umem */ + ib_umem_release(*umem); +} + +static void *roce3_cq_buf_offset(struct tag_cqm_buf *buf, unsigned int offset) +{ + return (void *)((char *)buf->direct.va + offset); +} + +void *roce3_get_cqe_from_buf(struct roce3_cq_buf *buf, unsigned int n) +{ + return roce3_cq_buf_offset(buf->buf, (n * buf->entry_size)); +} + +void *roce3_get_cqe(struct roce3_cq *cq, unsigned int n) +{ + return roce3_get_cqe_from_buf(&cq->buf, n); +} + +/* **************************************************************************** + Prototype : roce3_get_sw_cqe + Description : roce3_get_sw_cqe + Input : struct roce3_cq *cq + unsigned int n + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void *roce3_get_sw_cqe(struct roce3_cq *cq, unsigned int n) +{ + struct roce_cqe *cqe = (struct roce_cqe *)roce3_get_cqe(cq, (n & ((unsigned int)cq->ibcq.cqe))); + struct roce_cqe tmp_cqe; + unsigned int tmp_val; + + tmp_cqe.dw0.value = roce3_convert_cpu32(cqe->dw0.value); + tmp_cqe.dw1.value = roce3_convert_cpu32(cqe->dw1.value); + + /* Add judgment condition: the optype of CQE cannot be UNUSED, UNUSED means that it has been initialized in resize + cq */ + tmp_val = ((n & ((unsigned int)cq->ibcq.cqe + 1)) == 0) ? 1 : 0; + if ((ROCE_LIKELY(tmp_cqe.dw1.bs.op_type != ROCE_OPCODE_CQE_UNUSED)) && ((tmp_cqe.dw0.bs.owner ^ tmp_val) != 0)) { + return cqe; + } + + return NULL; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(OFED_MLNX_5_8) +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_udata *udata, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe) +#else +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_ucontext *context, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe) +#endif +{ + int ret = 0; + u32 npages = 0; + int page_shift = 0; + int cqe_size = (int)rdev->rdma_cap.cqe_size; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + *umem = ib_umem_get(&rdev->ib_dev, buf_addr, (unsigned long)(cqe * cqe_size), IB_ACCESS_LOCAL_WRITE); +#elif defined(OFED_MLNX_5_8) + *umem = ib_umem_get(udata, buf_addr, (unsigned long)(cqe * cqe_size), IB_ACCESS_LOCAL_WRITE); +#else + *umem = ib_umem_get(context, buf_addr, (unsigned long)(unsigned)(cqe * cqe_size), IB_ACCESS_LOCAL_WRITE, 1); +#endif + if (IS_ERR(*umem)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get ib_umem, func_id(%d)\n", __func__, rdev->glb_func_id); + return (int)PTR_ERR(*umem); + } + + npages = (u32)ib_umem_num_pages(*umem); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + page_shift = PAGE_SHIFT; +#else + page_shift = (*umem)->page_shift; +#endif + + buf->mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, npages, (u32)page_shift, &buf->mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma_mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_buf; + } + + ret = roce3_umem_write_mtt(rdev, &buf->mtt, *umem); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt for umem, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_mtt; + } + + return 0; + +err_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &buf->mtt, SERVICE_T_ROCE); + +err_buf: + ib_umem_release(*umem); + + return ret; +} + +void roce_reset_flow_comp(struct roce3_cq *rcq) +{ + struct ib_cq *ibcq = &rcq->ibcq; + + ibcq->comp_handler(ibcq, ibcq->cq_context); +} diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c new file mode 100644 index 000000000..40737a0a1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c @@ -0,0 +1,731 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_cqe.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE CQ kernel CQE related functions. + */ + +#include <linux/slab.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_mix.h" +#include "roce_xrc.h" +#include "roce_cq.h" + +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : roce3_next_cqe_sw + Description : roce3_next_cqe_sw + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static struct roce_cqe *roce3_next_cqe_sw(struct roce3_cq *cq) +{ + return (struct roce_cqe *)roce3_get_sw_cqe(cq, cq->cons_index); +} + +/*lint -e26*/ +static int g_error_cqe_to_wc[ROCE_CQE_SYNDROME_MAX] = { + [ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR] = IB_WC_LOC_LEN_ERR, + [ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR] = IB_WC_LOC_QP_OP_ERR, + [ROCE_CQE_SYNDROME_LOCAL_PROT_ERR] = IB_WC_LOC_PROT_ERR, + [ROCE_CQE_SYNDROME_WR_FLUSH_ERR] = IB_WC_WR_FLUSH_ERR, + + [ROCE_CQE_SYNDROME_MW_BIND_ERR] = IB_WC_MW_BIND_ERR, + [ROCE_CQE_SYNDROME_BAD_RESP_ERR] = IB_WC_BAD_RESP_ERR, + + [ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR] = IB_WC_LOC_ACCESS_ERR, + [ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR] = IB_WC_REM_INV_REQ_ERR, + [ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR] = IB_WC_REM_ACCESS_ERR, + [ROCE_CQE_SYNDROME_REMOTE_OP_ERR] = IB_WC_REM_OP_ERR, + [ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR] = IB_WC_RETRY_EXC_ERR, + + [ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR] = IB_WC_RNR_RETRY_EXC_ERR, + + [ROCE_CQE_SYNDROME_REMOTE_ABORTED_ERR] = IB_WC_REM_ABORT_ERR, +}; +/*lint +e26*/ + +/* **************************************************************************** + Prototype : roce3_handle_error_cqe + Description : roce3_handle_error_cqe + Input : struct roce_err_cqe *cqe + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_handle_error_cqe(struct roce_err_cqe *cqe, struct ib_wc *wc) +{ + if (cqe->dw7.bs.syndrome >= ROCE_CQE_SYNDROME_MAX) { + wc->status = IB_WC_GENERAL_ERR; + } else if (cqe->dw7.bs.syndrome > 0) { + wc->status = g_error_cqe_to_wc[cqe->dw7.bs.syndrome]; + if (wc->status == 0) { + wc->status = IB_WC_GENERAL_ERR; + } + } + + wc->vendor_err = cqe->dw7.bs.vendor_err; +} + +static void roce3_get_local_opcode_from_cqe(const struct roce_cqe *cqe, struct ib_wc *wc) +{ + switch (cqe->dw1.bs.op_type) { + case ROCE_OPCODE_LOCAL_INV: + wc->opcode = IB_WC_LOCAL_INV; + break; + case ROCE_OPCODE_REG_SIG_MR: + wc->opcode = IB_WC_REG_MR; + break; + + default: + pr_warn("[ROCE] %s: Unknown cqe optype\n", __func__); + break; + } +} + +static void roce3_get_opcode_type_part_1(struct roce_cqe *cqe, struct ib_wc *wc) +{ + switch (cqe->dw1.bs.op_type) { + case ROCE_OPCODE_RDMA_WRITE_WITH_IMM: + wc->opcode = IB_WC_RDMA_WRITE; + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_IMM); + break; + + case ROCE_OPCODE_RDMA_WRITE: + wc->opcode = IB_WC_RDMA_WRITE; + break; + + case ROCE_OPCODE_SEND_WITH_IMM: + wc->opcode = IB_WC_SEND; + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_IMM); + break; + + case ROCE_OPCODE_SEND: + wc->opcode = IB_WC_SEND; + break; + + case ROCE_OPCODE_SEND_WITH_INV: + wc->opcode = IB_WC_SEND; + break; + default: + roce3_get_local_opcode_from_cqe(cqe, wc); + break; + } +} + +static void roce3_get_opcode_type_part_2(struct roce_cqe *cqe, struct ib_wc *wc) +{ + switch (cqe->dw1.bs.op_type) { + case ROCE_OPCODE_RDMA_READ: + wc->opcode = IB_WC_RDMA_READ; + wc->byte_len = cqe->byte_cnt; + break; + + case ROCE_OPCODE_ATOMIC_COMP_AND_SWP: + wc->opcode = IB_WC_COMP_SWAP; + wc->byte_len = ATOMIC_DATA_LEN; + break; + + case ROCE_OPCODE_ATOMIC_FETCH_AND_ADD: + wc->opcode = IB_WC_FETCH_ADD; + wc->byte_len = ATOMIC_DATA_LEN; + break; + + case ROCE_OPCODE_ATOMIC_MASKED_COMP_AND_SWP: + wc->opcode = IB_WC_MASKED_COMP_SWAP; + wc->byte_len = ATOMIC_DATA_LEN; + break; + + case ROCE_OPCODE_ATOMIC_MASKED_FETCH_AND_ADD: + wc->opcode = IB_WC_MASKED_FETCH_ADD; + wc->byte_len = ATOMIC_DATA_LEN; + break; + case ROCE_OPCODE_FAST_REG_PMR: + wc->opcode = IB_WC_REG_MR; + break; + + default: + roce3_get_local_opcode_from_cqe(cqe, wc); + break; + } +} + +/* **************************************************************************** + Prototype : roce3_get_opcode_from_scqe + Description : Set the opcode/flag/byte_len of wc according to the opcode of send_cqe + Input : struct roce_cqe *cqe + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_get_opcode_from_scqe(struct roce_cqe *cqe, struct ib_wc *wc) +{ + wc->wc_flags = 0; + + if (cqe->dw1.bs.op_type < ROCE_OPCODE_RDMA_READ) { + roce3_get_opcode_type_part_1(cqe, wc); + } else { + roce3_get_opcode_type_part_2(cqe, wc); + } +} + +/* **************************************************************************** + Prototype : roce3_get_opcode_from_rcqe + Description : Set the opcode/flag/byte_len of wc according to the opcode of send_cqe + Input : struct roce_cqe *cqe + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_get_opcode_from_rcqe(struct roce_cqe *cqe, struct ib_wc *wc) +{ + wc->byte_len = cqe->byte_cnt; + + switch (cqe->dw1.bs.op_type) { + case ROCE_RECV_OPCODE_RDMA_WRITE_WITH_IMM: + wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; + wc->wc_flags = IB_WC_WITH_IMM; + /* The driver does not perform big or small endian conversion for immediate data, but the incoming CQE + has been converted to the CPU endian, so it needs to be converted back */ + wc->ex.imm_data = roce3_convert_be32(cqe->imm_invalid_rkey); + break; + + case ROCE_RECV_OPCODE_SEND_WITH_INV: + wc->opcode = IB_WC_RECV; + wc->wc_flags = IB_WC_WITH_INVALIDATE; + wc->ex.invalidate_rkey = cqe->imm_invalid_rkey; + break; + + case ROCE_RECV_OPCODE_SEND: + wc->opcode = IB_WC_RECV; + wc->wc_flags = 0; + break; + + case ROCE_RECV_OPCODE_SEND_WITH_IMM: + wc->opcode = IB_WC_RECV; + wc->wc_flags = IB_WC_WITH_IMM; + /* The driver does not perform big or small endian conversion for immediate data, but the incoming CQE + has been converted to the CPU endian, so it needs to be converted back */ + wc->ex.imm_data = roce3_convert_be32(cqe->imm_invalid_rkey); + break; + + default: + pr_warn("[ROCE] %s: Not supported\n", __func__); + break; + } +} + +/* **************************************************************************** + Prototype : roce3_cq_poll_and_resize + Description : roce3_cq_poll_and_resize + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static void roce3_cq_poll_and_resize(struct roce3_device *rdev, struct roce3_cq *cq) +{ + if (ROCE_LIKELY(cq->resize_buf != NULL)) { + /* Release the original Buffer of CQ */ + hiudk_cqm_object_resize_free_old(rdev->hwdev, &cq->cqm_cq->object); + cq->buf = cq->resize_buf->buf; + cq->ibcq.cqe = cq->resize_buf->cqe; + + kfree(cq->resize_buf); + cq->resize_buf = NULL; + } + + --cq->cons_index; + + return; +} + +/* **************************************************************************** + Prototype : roce3_cq_get_cur_qp + Description : roce3_cq_get_cur_qp + Input : struct roce3_cq *cq + struct roce3_qp **cur_qp + struct roce_cqe *cqe + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_get_cur_qp(struct roce3_cq *cq, struct roce3_qp **cur_qp, struct roce_cqe *cqe) +{ + struct roce3_device *rdev = NULL; + cqm_object_s *cqm_obj_qp = NULL; + + if ((!*cur_qp) || (cqe->dw0.bs.qpn != (u32)(*cur_qp)->qpn)) { + /* + * We do not have to take the QP table lock here, + * because CQs will be locked while QPs are removed + * from the table. + */ + rdev = to_roce3_dev(cq->ibcq.device); + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, cqe->dw0.bs.qpn, false); + if (cqm_obj_qp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: CQ(%06x) with entry for unknown QPN(%06x), func_id(%d)\n", + __func__, cq->cqn, cqe->dw0.bs.qpn, rdev->glb_func_id); + return -EINVAL; + } + + *cur_qp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_get_xrc_srq + Description : roce3_cq_get_xrc_srq + Input : struct roce3_cq *cq + struct roce3_srq **srq + struct roce_cqe *cqe + u32 qp_type + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_get_xrc_srq(struct roce3_cq *cq, struct roce3_srq **srq, struct roce_cqe *cqe, u32 qp_type) +{ + u32 srq_num = 0; + struct roce3_device *rdev = NULL; + cqm_object_s *cqm_obj_srq = NULL; + + if (qp_type == IB_QPT_XRC_TGT) { + srq_num = cqe->dw6.bs.srqn_rqpn; + + /* SRQ is also in the radix tree */ + rdev = to_roce3_dev(cq->ibcq.device); + cqm_obj_srq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srq_num, false); + if (cqm_obj_srq == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: CQ(%06x) with entry for unknown SRQN(%06x), func_id(%d)\n", + __func__, cq->cqn, srq_num, rdev->glb_func_id); + return -EINVAL; + } + + /* Get roce3__srq structure through cqm object */ + *srq = cqmobj_to_roce3_srq(cqm_obj_srq); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_srq); + } + + return 0; +} + +static int roce3_poll_recv_cqe(struct roce3_qp *cur_qp, struct roce3_srq *srq, struct roce_cqe trans_cqe, + struct ib_wc *wc) +{ + u16 wqe_ctr = 0; + unsigned int tail = 0; + struct roce3_srq *srq_tmp; + + if (cur_qp->ibqp.srq) { + srq_tmp = to_roce3_srq(cur_qp->ibqp.srq); + + wqe_ctr = (u16)trans_cqe.dw1.bs.wqebb_cnt; + /* Determine whether to overflow */ + if (wqe_ctr > srq_tmp->max_depth) { + pr_err("[ROCE, ERR] %s: Get wqe index(0x%x) from cqe\n", __func__, wqe_ctr); + return -EINVAL; + } + + wc->wr_id = srq_tmp->wrid[wqe_ctr]; + roce3_free_srq_wqe(srq_tmp, wqe_ctr); + } else if (srq) { + wqe_ctr = (u16)trans_cqe.dw1.bs.wqebb_cnt; + /* Determine whether to overflow */ + if (wqe_ctr > srq->max_depth) { + pr_err("[ROCE, ERR] %s: Get wqe index(0x%x) from cqe\n", __func__, wqe_ctr); + return -EINVAL; + } + + wc->wr_id = srq->wrid[wqe_ctr]; + roce3_free_srq_wqe(srq, wqe_ctr); + } else { + struct roce3_wq *wq = &(cur_qp->rq); + tail = (u32)(wq->tail & ((unsigned int)wq->wqebb_cnt - 1)); + wc->wr_id = wq->wrid[tail]; + ++wq->tail; + } + + return 0; +} + +static void roce3_poll_move_tail(const struct roce3_qp *cur_qp, struct roce3_wq *wq, struct roce_cqe *trans_cqe) +{ + u16 wqe_ctr = 0; + if (cur_qp->sq_signal_bits == 0) { + wqe_ctr = trans_cqe->dw7.bs.wqe_cnt; + wq->tail += (u16)(wqe_ctr - (u16)wq->tail); + } +} + +static void roce3_poll_one_get_av_info(const struct roce3_qp *cur_qp, struct ib_wc *wc, struct roce_cqe trans_cqe, + struct roce_cqe *cqe) +{ + if ((cur_qp->qp_type == IB_QPT_UD) || (cur_qp->qp_type == IB_QPT_GSI)) { + wc->sl = trans_cqe.dw4.bs.vlan_pri; + wc->src_qp = trans_cqe.dw6.bs.srqn_rqpn; + wc->network_hdr_type = trans_cqe.dw6.bs.stp; + wc->smac[0] = (u8)(trans_cqe.dw4.bs.smac_h >> 8); /* Take the first Byte data, shift 8bit */ + wc->smac[1] = (u8)(trans_cqe.dw4.bs.smac_h & 0xff); + memcpy(&wc->smac[2], &cqe->smac_l, sizeof(cqe->smac_l)); // 2 : smac array idx + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_SMAC); + if (trans_cqe.dw6.bs.vlan_pre != 0) { + wc->vlan_id = trans_cqe.dw4.bs.vlan_id; + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_VLAN); + } + } +} + +static int roce3_poll_one_get_qp_and_srq(struct roce3_cq *cq, struct roce3_qp **cur_qp, struct ib_wc *wc, + struct roce_cqe *trans_cqe, struct roce3_srq **srq) +{ + int ret = 0; + ret = roce3_cq_get_cur_qp(cq, cur_qp, trans_cqe); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get current qp\n", __func__); + return ret; + } + + wc->qp = &((*cur_qp)->ibqp); + + ret = roce3_cq_get_xrc_srq(cq, srq, trans_cqe, wc->qp->qp_type); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get xrc srq\n", __func__); + return ret; + } + + return ret; +} + +static void roce3_bytes_trans(u32 *addr, int dw_num) +{ + u32 *dw = addr; + int i = 0; + + for (i = 0; i < dw_num; i++) { + *dw = roce3_convert_cpu32(*dw); + dw++; + } +} + +static int roce3_get_and_trans_cqe(struct roce3_device *rdev, struct roce3_cq *cq, struct roce_cqe *trans_cqe, + int *is_send, struct roce_cqe **cqe) +{ + do { + *cqe = roce3_next_cqe_sw(cq); + if (*cqe == NULL) { + return -EAGAIN; + } + + /* Later, it is necessary to perform big and small end conversion on CQE. + In order to avoid turning back after processing, copy a copy */ + memcpy((void *)trans_cqe, (void *)*cqe, sizeof(struct roce_cqe)); + ++cq->cons_index; + + /* + * Make sure we read CQ entry contents after we've checked the + * ownership bit. + */ + rmb(); + + /* Convert the CQE into the CPU endian corresponding to the running environment */ + roce3_bytes_trans((u32 *)(void *)trans_cqe, (int)(sizeof(struct roce_cqe) / CQ_DW_TO_BYTE)); + + *is_send = trans_cqe->dw1.bs.s_r; + /* Resize CQ operation in progress */ + if (ROCE_UNLIKELY(trans_cqe->dw1.bs.op_type == ROCE_OPCODE_RESIZE_CQE)) { + roce3_cq_poll_and_resize(rdev, cq); + } + } while (ROCE_UNLIKELY(trans_cqe->dw1.bs.op_type == ROCE_OPCODE_RESIZE_CQE)); + + return 0; +} + +static void roce3_poll_send_cqe(struct roce3_qp *cur_qp, struct roce_cqe *trans_cqe, struct ib_wc *wc) +{ + struct roce3_wq *wq = &(cur_qp->sq); + /* QP of type IB_SIGNAL_REQ_WR, tail needs to skip several WRs that do not generate CQE */ + roce3_poll_move_tail(cur_qp, wq, trans_cqe); + + wc->wr_id = wq->wrid[wq->tail & ((unsigned int)wq->wqebb_cnt - 1)]; + ++wq->tail; + + if (trans_cqe->dw1.bs.op_type == ROCE_OPCODE_ERR) { + roce3_handle_error_cqe((struct roce_err_cqe *)(void *)trans_cqe, wc); + return; + } + + roce3_get_opcode_from_scqe(trans_cqe, wc); +} + +/* **************************************************************************** + Prototype : roce3_poll_one + Description : roce3_poll_one + Input : struct roce3_cq *cq + struct roce3_qp **cur_qp + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_poll_one(struct roce3_device *rdev, struct roce3_cq *cq, struct roce3_qp **cur_qp, struct ib_wc *wc) +{ + int ret = 0; + struct roce_cqe *cqe = NULL; + struct roce_cqe trans_cqe; + struct roce3_srq *srq = NULL; + int is_send = 0; + bool need_poll = true; + + while (need_poll) { + ret = roce3_get_and_trans_cqe(rdev, cq, &trans_cqe, &is_send, &cqe); + if (ret != 0) { + return -EAGAIN; + } + + ret = roce3_poll_one_get_qp_and_srq(cq, cur_qp, wc, &trans_cqe, &srq); + if (ret != 0) { + return ret; + } + + /* Poll cq exception handling, generally cq judges user state information, xrc judges wrid */ + if ((*cur_qp)->umem || ((*cur_qp)->ibqp.xrcd && !(srq->wrid))) { + pr_err("[ROCE, ERR] %s: qp(%u) create in user space , but poll cq in kernel. NOT PERMIT!\n", __func__, + (*cur_qp)->qpn); + return -EACCES; + } + + if (trans_cqe.dw1.bs.fake != 0) { + pr_info("[ROCE] %s: Fake cqe go repoll.\n", __FUNCTION__); + continue; + } + + wc->status = IB_WC_SUCCESS; + if (is_send != 0) { + roce3_poll_send_cqe(*cur_qp, &trans_cqe, wc); + return 0; + } else { + ret = roce3_poll_recv_cqe(*cur_qp, srq, trans_cqe, wc); + if (ret != 0) { + return ret; + } + } + + if (trans_cqe.dw1.bs.op_type == ROCE_OPCODE_ERR) { + roce3_handle_error_cqe((struct roce_err_cqe *)(void *)&trans_cqe, wc); + return 0; + } + + roce3_get_opcode_from_rcqe(&trans_cqe, wc); + wc->wc_flags = (int)((unsigned int)wc->wc_flags | IB_WC_GRH); + wc->pkey_index = 0; + wc->vlan_id = 0xffff; + wc->sl = 0; + + /* avoid cm_req_handler()->ib_lid_be16() trigger call trace */ + wc->slid = 0; + + roce3_poll_one_get_av_info((*cur_qp), wc, trans_cqe, cqe); + + /* Kernel mode does not support receiving inline */ + if (trans_cqe.dw1.bs.inline_r == ROCE_CQE_RQ_INLINE) { + pr_err("[ROCE, ERR] %s: Receive inline not supported in kernel space\n", __func__); + return -EINVAL; + } + need_poll = false; + } + + return 0; +} + +static int sw_send_comp(struct roce3_qp *rqp, int num_entries, int *npolled, struct ib_wc *wc) +{ + struct roce3_wq *wq = &rqp->sq; + unsigned int cur = wq->head - wq->tail; + unsigned int i; + + if (cur == 0) { + goto out; + } + + for (i = 0; (i < cur) && (*npolled < num_entries); i++) { + wc[*npolled].wr_id = wq->wrid[wq->tail & (wq->wqebb_cnt - 1)]; + wc[*npolled].status = IB_WC_WR_FLUSH_ERR; + wc[*npolled].vendor_err = ROCE_CQE_SYNDROME_WR_FLUSH_ERR; + wc[*npolled].qp = &rqp->ibqp; + wq->tail++; + (*npolled)++; + } + +out: + return (*npolled >= num_entries); +} + +static int sw_recv_comp(struct roce3_qp *rqp, int num_entries, int *npolled, struct ib_wc *wc) +{ + struct roce3_wq *wq = &rqp->rq; + unsigned int cur = wq->head - wq->tail; + unsigned int i; + + if (cur == 0) { + goto out; + } + + for (i = 0; (i < cur) && (*npolled < num_entries); i++) { + wc[*npolled].wr_id = wq->wrid[wq->tail & (wq->wqebb_cnt - 1)]; + wc[*npolled].status = IB_WC_WR_FLUSH_ERR; + wc[*npolled].vendor_err = ROCE_CQE_SYNDROME_WR_FLUSH_ERR; + wc[*npolled].qp = &rqp->ibqp; + wq->tail++; + (*npolled)++; + } + +out: + return (*npolled >= num_entries); +} + +static int roce_poll_sw_comp(const struct roce3_cq *rcq, int num_entries, struct ib_wc *wc) +{ + struct roce3_qp *rqp = NULL; + int npolled = 0; + + list_for_each_entry(rqp, &rcq->send_qp_list, cq_send_list) + { + if (sw_send_comp(rqp, num_entries, &npolled, wc) != 0) { + return npolled; + } + } + + list_for_each_entry(rqp, &rcq->recv_qp_list, cq_recv_list) + { + if (sw_recv_comp(rqp, num_entries, &npolled, wc) != 0) { + return npolled; + } + } + + return npolled; +} + +/* the format of cq_ci DB:the bits of ci less than 24bit */ +void roce3_cq_set_ci(struct roce3_cq *cq) +{ + *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff); +} + +int roce3_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) +{ + struct roce3_device *rdev = NULL; + struct roce3_cq *rcq = to_roce3_cq(ibcq); + struct roce3_qp *cur_qp = NULL; + unsigned long flags = 0; + int npolled = 0; + int ret = 0; + + spin_lock_irqsave(&rcq->lock, flags); + + rdev = to_roce3_dev(ibcq->device); + if (roce3_hca_is_present(rdev) == 0) { + npolled = roce_poll_sw_comp(rcq, num_entries, wc); + goto poll_out; + } + + for (npolled = 0; npolled < num_entries; ++npolled) { + ret = roce3_poll_one(rdev, rcq, &cur_qp, wc + npolled); + if (ret != 0) { + break; + } + } + + roce3_cq_set_ci(rcq); + +poll_out: + spin_unlock_irqrestore(&rcq->lock, flags); + + if ((ret == 0) || (ret == -EAGAIN)) { + return npolled; + } + + return ret; +} + +static void roce3_cq_arm(struct roce3_cq *cq, u32 cmd, void __iomem *uar_page) +{ + struct roce_db_cq_arm db_value; + + memset(&db_value, 0, sizeof(db_value)); + + db_value.dw0.bs.type = 3; + db_value.dw0.bs.cos = 0; /* arm_cq don't need cos */ + db_value.dw0.bs.cp = 1; /* 1 for cp */ + db_value.dw0.bs.non_filter = 1; + db_value.dw0.bs.cqc_type = 0; + db_value.dw0.bs.cqn = cq->cqn; + db_value.dw0.value = roce3_convert_be32(db_value.dw0.value); + + db_value.dw1.bs.cmd_sn = cq->arm_sn; + db_value.dw1.bs.cmd = cmd; + db_value.dw1.bs.ci = cq->cons_index; + db_value.dw1.value = roce3_convert_be32(db_value.dw1.value); + + /* + * Make sure that the doorbell record in host memory is + * written before ringing the doorbell via PCI MMIO. + */ + wmb(); + + roce3_write64((u32 *)(void *)&db_value, uar_page); +} + +int roce3_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) +{ + unsigned long lock_flags = 0; + struct roce3_cq *cq = to_roce3_cq(ibcq); + + spin_lock_irqsave(&cq->lock, lock_flags); + if (cq->arm_flag != 0) { + spin_unlock_irqrestore(&cq->lock, lock_flags); + return 0; + } + + cq->arm_flag = 1; + spin_unlock_irqrestore(&cq->lock, lock_flags); + + /* Only 64-bit is supported, 64-bit writes are atomic, no need to lock */ + roce3_cq_arm(to_roce3_cq(ibcq), + (((unsigned int)flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED) ? ROCE_CQ_DB_REQ_NOT_SOL : ROCE_CQ_DB_REQ_NOT, + to_roce3_dev(ibcq->device)->kernel_db_map); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c new file mode 100644 index 000000000..f05942b5c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c @@ -0,0 +1,604 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_create.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ create realted functions. + */ + +#include "roce_cq.h" +#include "roce_pub_cmd.h" +#include "roce_cqm_cmd.h" +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : roce_cq_attr_assign + Description : Assign value to CQC + Input : struct roce_cq_attr *cq_attr + struct roce3_cq *rcq + int eqn + int page_shift + Output : None + + 1.Date : 2019/10/13 + Modification : Created function + +**************************************************************************** */ +static void roce_cq_attr_assign(roce_verbs_cq_attr_s *cq_attr, struct roce3_cq *rcq, int eqn, int page_shift) +{ + /* Assign value to CQ */ + /* dw0 */ + cq_attr->dw0.bs.size = (u32)ROCE_ILOG2((unsigned)(rcq->ibcq.cqe + 1)); + cq_attr->dw0.bs.page_size = (u32)page_shift; + cq_attr->dw0.bs.cqe_size = + (u32)ROCE_ILOG2((unsigned)(rcq->buf.entry_size / 16)); /* entry_size=(2^cq_cqe_size)*16B. */ + cq_attr->dw0.bs.mtt_page_size = rcq->buf.mtt.mtt_page_shift - PAGE_SHIFT_4K; + cq_attr->dw0.bs.tss_timer_num = 7; /* 7 : The maximum number of timers supported by cq */ + cq_attr->dw0.bs.arm_timer_en = 0; + cq_attr->dw0.bs.timer_mode = 0; + cq_attr->dw0.bs.cnt_adjust_en = 1; + cq_attr->dw0.bs.cnt_clear_en = 1; + cq_attr->dw0.bs.ci_on_chip = 0; + cq_attr->dw0.value = cpu_to_be32(cq_attr->dw0.value); + + /* dw1 */ + cq_attr->dw1.bs.dma_attr_idx = 0; + cq_attr->dw1.bs.so_ro = 0; + cq_attr->dw1.bs.state = ROCE_CQ_STATE_VALID; + cq_attr->dw1.value = cpu_to_be32(cq_attr->dw1.value); + + /* dw2 */ + cq_attr->dw2.bs.idle_max_count = 0; + cq_attr->dw2.bs.cqecnt_lth = 6; /* update ci threshhold: 2^6=64 */ + cq_attr->dw2.bs.cqecnt_rctl_en = 0; + cq_attr->dw2.bs.ceqe_en = 1; + cq_attr->dw2.bs.arm_ceqe_en = 1; + cq_attr->dw2.bs.ceqn = (u8)eqn; + cq_attr->dw2.value = cpu_to_be32(cq_attr->dw2.value); + + /* dw3 */ + cq_attr->dw3.bs.timeout = 0; /* The timeout mechanism is disabled by default when CQ is created */ + cq_attr->dw3.bs.max_cnt = 0; /* The overtime mechanism is disabled by default when CQ is created */ + cq_attr->dw3.value = cpu_to_be32(cq_attr->dw3.value); + + /* dw4 - dw5 */ + cq_attr->cqc_l0mtt_gpa = rcq->buf.mtt.mtt_paddr; + cq_attr->cqc_l0mtt_gpa = cpu_to_be64(cq_attr->cqc_l0mtt_gpa); + + /* dw6 - dw7 */ + cq_attr->ci_record_gpa_at_hop_num = cpu_to_be64((rcq->db.dma & (~0x3uLL)) | rcq->buf.mtt.mtt_layers); + + return; +} + +static int roce3_cq_fill_create_inbuf(struct roce3_device *rdev, struct roce3_cq *rcq, int vector, int page_shift, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + int eqn = 0; + roce_verbs_cq_attr_s *cq_attr = NULL; + roce_uni_cmd_creat_cq_s *cq_sw2hw_inbuf = NULL; + + cq_sw2hw_inbuf = (roce_uni_cmd_creat_cq_s *)cqm_cmd_inbuf->buf; + cq_sw2hw_inbuf->com.index = cpu_to_be32(rcq->cqn); + cq_sw2hw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_attr = &cq_sw2hw_inbuf->cq_attr; + + /* Get the EQN of the CEQ based on the Vector index */ + eqn = hinic3_vector_to_eqn(rdev->hwdev, SERVICE_T_ROCE, vector); + if (eqn < 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get eqn from hinic vector, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + roce_cq_attr_assign(cq_attr, rcq, eqn, page_shift); + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_sw2hw + Description : Send the cqc configuration command + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int vector + int page_shift + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_sw2hw(struct roce3_device *rdev, struct roce3_cq *rcq, int vector, int page_shift) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_creat_cq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + ret = roce3_cq_fill_create_inbuf(rdev, rcq, vector, page_shift, cqm_cmd_inbuf); + if (ret != 0) { + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return ret; + } + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_SW2HW_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send SW2HW_CQ command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(SW2HW_CQ), CQN(0x%x), func_id(%hu)\n", __func__, + rcq->cqn, rdev->glb_func_id); + + /* CMDq times out or CMDq does not work, update the device status, notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + ret = -1; + goto err_send_cmd; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + rcq->cons_index = 0; + rcq->arm_sn = 1; + rcq->arm_flag = 0; + rcq->vector = (u32)vector; + + return 0; + +err_send_cmd: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_create_cq_check + Description : roce3_create_cq_check + Input : struct ib_device *ibdev + int entries + int vector + struct ib_ucontext *ibcontext + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_cq_check(struct ib_device *ibdev, int entries, int vector, const struct ib_ucontext *ibcontext, + const struct ib_udata *udata) +{ + struct roce3_device *rdev = NULL; + + if (ibdev == NULL) { + pr_err("[ROCE, ERR] %s: Ibdev is null\n", __func__); + return -EINVAL; + } + + if ((ibcontext != NULL) && (udata == NULL)) { + pr_err("[ROCE, ERR] %s: Udata is null ptr, but ibcontext is not null ptr\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if ((entries < 1) || (entries > (int)rdev->rdma_cap.max_cqes)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Cqe number invalid, entries(%d), func_id(%d)\n", __func__, entries, + rdev->glb_func_id); + return -EINVAL; + } + + if (vector > (int)rdev->rdma_cap.num_comp_vectors) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Vector over range, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} + +static int roce3_check_cq_create_flags(u32 flags) +{ + /* + * It returns non-zero value for unsupported CQ + * create flags, otherwise it returns zero. + */ + return (int)(flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); /*lint !e40*/ +} + +static int roce3_cq_cqc_cfg(struct roce3_device *rdev, struct roce3_cq *rcq, int vector, struct ib_udata *udata) +{ + int ret = 0; + int page_shift = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + page_shift = rcq->umem->page_shift - PAGE_SHIFT_4K; +#endif + + /* configurate CQC */ + ret = roce3_cq_sw2hw(rdev, rcq, vector, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle cq sw2hw, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + /* User mode requires outgoing CQN */ + if (ib_copy_to_udata(udata, &rcq->cqn, sizeof(u32)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data to user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EFAULT; + return ret; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_create_user_cq + Description : roce3_create_user_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + int vector + struct ib_ucontext *ibcontext + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_user_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, int vector, + struct ib_ucontext *ibcontext, struct ib_udata *udata, u32 index) +{ + int ret = 0; + struct roce3_create_cq_cmd ucmd = { 0 }; + + rcq->cqm_cq = cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_SCQ, 0, rcq, false, index); + if (rcq->cqm_cq == NULL) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to create rdma queue from cqm object, func_id(%d), index(%d)\n", __func__, + rdev->glb_func_id, index); + return -ENOMEM; + } + + /* record CQN */ + rcq->cqn = rcq->cqm_cq->index; + + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EFAULT; + goto err_free_cqm_cq; + } + + /* Entries has been decreased by one when it was input by User Mode, and it is the expected value exactly + after increased by one by Kernel Mode */ +#if defined(OFED_MLNX_5_8) + ret = roce3_cq_get_umem(rdev, udata, &rcq->buf, &rcq->umem, ucmd.buf_addr, entries); +#else + ret = roce3_cq_get_umem(rdev, ibcontext, &rcq->buf, &rcq->umem, ucmd.buf_addr, entries); +#endif + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get umem, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_free_cqm_cq; + } + + ret = roce3_db_map_user(to_roce3_ucontext(ibcontext), (unsigned long)ucmd.db_addr, &rcq->db); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to map kernel_mem to user_mem, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_mtt; + } + + ret = roce3_cq_cqc_cfg(rdev, rcq, vector, udata); + if (ret != 0) { + goto err_unmap_db; + } + + return 0; + +err_unmap_db: + roce3_db_unmap_user(to_roce3_ucontext(ibcontext), &rcq->db); + +err_free_mtt: + roce3_cq_put_umem(rdev, &rcq->buf, &rcq->umem); + rcq->umem = NULL; + +err_free_cqm_cq: + hiudk_cqm_object_delete(rdev->hwdev, &rcq->cqm_cq->object); + + return ret; +} + +static void roce3_fill_rcq_info(struct roce3_cq *rcq) +{ + rcq->cqn = rcq->cqm_cq->index; + rcq->buf.buf = &rcq->cqm_cq->q_room_buf_1; + + /* Initialize buf to unused */ + roce3_cq_buf_init(&rcq->buf); + + /* Software DB assignment */ + rcq->set_ci_db = (__be32 *)(void *)(&rcq->cqm_cq->q_header_vaddr->doorbell_record); + *rcq->set_ci_db = 0; + rcq->db.db_record = (__be32 *)(void *)(&rcq->cqm_cq->q_header_vaddr->doorbell_record); + rcq->db.dma = rcq->cqm_cq->q_header_paddr; +} + +/* **************************************************************************** + Prototype : roce3_create_kernel_cq + Description : roce3_create_kernel_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + int vector + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_kernel_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, int vector, u32 index) +{ + int ret = 0; + int page_shift = 0; + + rcq->buf.buf_size = entries * (int)rdev->rdma_cap.cqe_size; + rcq->cqm_cq = cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_SCQ, (u32)rcq->buf.buf_size, + rcq, true, index); + if (rcq->cqm_cq == NULL) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to create rdma_queue from cqm_object, func_id(%d), index(%d)\n", __func__, + rdev->glb_func_id, index); + return (-ENOMEM); + } + + /* Buffer is obtained from room1 when the queue is just created */ + if (rcq->cqm_cq->current_q_room != CQM_RDMA_Q_ROOM_1) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Not use CQM_RDMA_Q_ROOM_1, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EINVAL; + goto err_free_cqm_cq; + } + + roce3_fill_rcq_info(rcq); + + page_shift = ROCE_ILOG2(rcq->cqm_cq->q_room_buf_1.buf_size); + + /* allocate MTT */ + rcq->buf.mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, rcq->buf.buf->buf_number, (u32)page_shift, &rcq->buf.mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_cqm_cq; + } + + /* Write the PA of the CQ Buffer to the MTT */ + ret = roce3_buf_write_mtt(rdev, &rcq->buf.mtt, rcq->buf.buf); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_mtt; + } + + /*lint -e834*/ + page_shift = ROCE_ILOG2(rcq->cqm_cq->q_room_buf_1.buf_size) - PAGE_SHIFT_4K; + /*lint +e834*/ + + /* configurate CQC */ + ret = roce3_cq_sw2hw(rdev, rcq, vector, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to configure CQC, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_free_mtt; + } + + return 0; + +err_free_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + +err_free_cqm_cq: + hiudk_cqm_object_delete(rdev->hwdev, &rcq->cqm_cq->object); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_do_create_cq + Description : OFED_3_12 + Input : struct ib_device *ibdev + struct ib_ucontext *ibcontext + struct ib_ucontext *ibcontext + struct ib_udata *udata + struct roce3_cq *rcq + u32 index + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + 2.Date : 2015/8/10 + Modification : modify function + 3.Date : 2017/11/10 + Modification : modify function + +**************************************************************************** */ +static int roce3_do_create_cq(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata, struct roce3_cq *rcq, u32 index) +{ + struct roce3_device *rdev = NULL; + int ret = 0; + int vector = attr->comp_vector; + int entries = (int)attr->cqe; + + /* The CQE queue should reserve a special CQE for resize cq */ + entries++; + entries = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)entries) & 0xffffffff); /*lint !e587*/ + + rdev = to_roce3_dev(ibdev); + /* Chip Constraints: Minimum queue depth needs to be page-aligned */ + if ((u32)((u32)entries * rdev->rdma_cap.cqe_size) < PAGE_SIZE) { + entries = (PAGE_SIZE >> (u32)ROCE_ILOG2(rdev->rdma_cap.cqe_size)); + } + + /* Check if max spec is exceeded */ + if (entries > ((int)rdev->rdma_cap.max_cqes + 1)) { + ret = (-EINVAL); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Over range after align, entries(%d), max_cqes(%d), func_id(%d)\n", + __func__, entries, rdev->rdma_cap.max_cqes + 1, rdev->glb_func_id); + return ret; + } + + rcq->ibcq.cqe = entries - 1; + mutex_init(&rcq->resize_mutex); + /*lint -e708*/ + spin_lock_init(&rcq->lock); + /*lint +e708*/ + rcq->resize_buf = NULL; + rcq->resize_umem = NULL; + rcq->buf.entry_size = (int)rdev->rdma_cap.cqe_size; + + INIT_LIST_HEAD(&rcq->send_qp_list); + INIT_LIST_HEAD(&rcq->recv_qp_list); + if (ibcontext) { + ret = roce3_create_user_cq(rdev, rcq, entries, vector, ibcontext, udata, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create user_cq, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } else { + ret = roce3_create_kernel_cq(rdev, rcq, entries, vector, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create kernel_cq, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + + rcq->reset_flow_comp = roce_reset_flow_comp; + + return 0; +} + +#if defined(OFED_MLNX_5_8) +int roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_udata *udata, struct roce3_cq *rcq, u32 index) +{ + int ret; + struct roce3_device *rdev = to_roce3_dev(ibdev); + struct roce3_ucontext *context = rdma_udata_to_drv_context( + udata, struct roce3_ucontext, ibucontext); + int vector = attr->comp_vector; + int entries = (int)attr->cqe; + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if (roce3_check_cq_create_flags(attr->flags) != 0) { + pr_err("[ROCE, ERR] %s: Not support the cq_create flag(%x)\n", __func__, attr->flags); + return -EOPNOTSUPP; + } + + ret = roce3_create_cq_check(ibdev, entries, vector, &context->ibucontext, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check cq information\n", __func__); + return ret; + } + + return roce3_do_create_cq(ibdev, attr, &context->ibucontext, udata, rcq, index); +} + +int roce3_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, struct ib_udata *udata) +{ + struct roce3_cq *rcq = to_roce3_cq(ibcq); + return roce3_create_cq_common(ibcq->device, attr, udata, rcq, ROCE_CQN_INVLD); +} +#else +struct ib_cq *roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata, u32 index) +{ + int ret = 0; + struct roce3_cq *rcq = NULL; + int vector = attr->comp_vector; + int entries = (int)attr->cqe; + struct roce3_device *rdev = to_roce3_dev(ibdev); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ERR_PTR((long)-EPERM); + } + + if (roce3_check_cq_create_flags(attr->flags) != 0) { + pr_err("[ROCE, ERR] %s: Not support the cq_create flag(%x)\n", __func__, attr->flags); + return ERR_PTR((long)(-EOPNOTSUPP)); + } + + ret = roce3_create_cq_check(ibdev, entries, vector, ibcontext, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check cq information\n", __func__); + goto err_out; + } + + rcq = (struct roce3_cq *)kzalloc(sizeof(*rcq), GFP_KERNEL); + if (rcq == NULL) { + ret = -ENOMEM; + pr_err("[ROCE, ERR] %s: Failed to alloc rcq\n", __func__); + goto err_out; + } + + ret = roce3_do_create_cq(ibdev, attr, ibcontext, udata, rcq, index); + if (ret != 0) { + goto err_free_cq; + } + + return &rcq->ibcq; + +err_free_cq: + kfree(rcq); + +err_out: + return (struct ib_cq *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : roce3_create_cq + Description : OFED_3_12 + Input : struct ib_device *ibdev + struct ib_cq_init_attr *attr(flags for exp) + struct ib_ucontext *ibcontext + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + 2.Date : 2015/8/10 + Modification : modify function + 3.Date : 2017/11/10 + Modification : modify function + 4.Date : 2021/1/7 + Modification : modified function + +**************************************************************************** */ +struct ib_cq *roce3_create_cq(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata) +{ + return roce3_create_cq_common(ibdev, attr, ibcontext, udata, ROCE_CQN_INVLD); +} +#endif + diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c new file mode 100644 index 000000000..60315e9e4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c @@ -0,0 +1,872 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_ctrl.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ control realted functions. + */ + +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : roce3_cq_modify + Description : Send the command of cq_modify + Input : struct roce3_device *rdev + struct roce3_cq *cq + u32 cnt + u32 period + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_modify(struct roce3_device *rdev, struct roce3_cq *cq, u32 cnt, u32 period) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_modify_cq_s *cq_modify_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_modify_cq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + cq_modify_inbuf = (roce_cmd_modify_cq_s *)cqm_cmd_inbuf->buf; + cq_modify_inbuf->com.index = cpu_to_be32(cq->cqn); + cq_modify_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_modify_inbuf->max_cnt = cpu_to_be32(cnt); + cq_modify_inbuf->timeout = cpu_to_be32(period); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_MODIFY_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to send MODIFY_CQ, cqn(0x%x), ret(%d), func_id(%hu)\n", __func__, + cq->cqn, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(MODIFY_CQ), cqn(0x%x), func_id(%hu)\n", __func__, + cq->cqn, rdev->glb_func_id); + + /* CMDq times out or CMDq does not work, update the device status, + notify the PCIe module to reset the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + /* CMDq may return a positive number, so its return value cannot be used directly */ + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return 0; +} + +/* **************************************************************************** + Prototype : roce3_modify_cq + Description : OFED_3_12 + Input : struct ib_cq *ibcq + u16 cq_count + u16 cq_period + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_modify_cq(struct ib_cq *ibcq, u16 cq_count, u16 cq_period) +{ + int ret = 0; + struct roce3_cq *cq = NULL; + struct roce3_device *rdev = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + cq = to_roce3_cq(ibcq); + rdev = to_roce3_dev(ibcq->device); + + ret = roce3_cq_modify(rdev, cq, cq_count, cq_period); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify cq, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_alloc_resize_buf + Description : Kernel mode applies for resize_buf, and its corresponding MTT + When there is an error in execution, this function ensures that all intermediate resources are released; + when the execution is successful, this function can confirm that all resources are acquired. + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_alloc_resize_buf(struct roce3_device *rdev, struct roce3_cq *rcq, int entries) +{ + int ret = 0; + int page_shift = 0; + + if (rcq->resize_buf) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Resize buffer is busy, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EBUSY; + } + + /* Apply for resize_buf and assign it */ + rcq->resize_buf = (struct roce3_cq_resize_buf *)kmalloc(sizeof(*rcq->resize_buf), GFP_ATOMIC); + if (rcq->resize_buf == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc resize buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + rcq->resize_buf->buf.entry_size = rcq->buf.entry_size; + rcq->resize_buf->buf.buf_size = entries * rcq->buf.entry_size; + ret = hiudk_cqm_object_resize_alloc_new(rdev->hwdev, &rcq->cqm_cq->object, (u32)rcq->resize_buf->buf.buf_size); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize cq buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_resize_buf_alloc; + } + + /* If the application is successful, record the buffer information of the new buffer */ + rcq->resize_buf->cqe = entries - 1; + rcq->resize_buf->buf.buf = &rcq->cqm_cq->q_room_buf_2; + + /* Initialize new buf to unused state */ + roce3_cq_buf_init(&rcq->resize_buf->buf); + + page_shift = (int)ROCE_ILOG2(rcq->resize_buf->buf.buf->buf_size); + + /* Apply MTT for resize_buf */ + rcq->buf.mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, rcq->resize_buf->buf.buf->buf_number, + (u32)page_shift, &rcq->resize_buf->buf.mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_mtt_alloc; + } + + /* configurate MTT, write PA of resize_buf to MTT */ + ret = roce3_buf_write_mtt(rdev, &rcq->resize_buf->buf.mtt, rcq->resize_buf->buf.buf); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_mtt_write; + } + + return 0; + +err_mtt_write: + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + +err_mtt_alloc: + /* free resize_buf */ + hiudk_cqm_object_resize_free_new(rdev->hwdev, &rcq->cqm_cq->object); + +err_resize_buf_alloc: + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_cq_free_resize_buf + Description : Kernel Mode releases resize_buf and its corresponding MTT + Input : struct roce3_device *rdev + struct roce3_cq *rcq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_cq_free_resize_buf(struct roce3_device *rdev, struct roce3_cq *rcq) +{ + /* Release the MTT of resize_buf first */ + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + + /* free resize_buf */ + hiudk_cqm_object_resize_free_new(rdev->hwdev, &rcq->cqm_cq->object); + + /* free the resize_buf pointer itself */ + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; +} + +/* **************************************************************************** + Prototype : roce3_cq_alloc_resize_umem + Description : User mode applies for umem of resize_buf, and MTT corresponding to user mode buf + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_alloc_resize_umem(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, + struct ib_udata *udata) +{ + int ret = 0; + struct roce3_resize_cq_cmd ucmd = { 0 }; + + /* If a resize is being executed, it is not allowed to execute another resize at the same time */ + if (rcq->resize_umem) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Resize_umem is busy, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EBUSY; + } + + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EFAULT; + } + + rcq->resize_buf = (struct roce3_cq_resize_buf *)kmalloc(sizeof(*rcq->resize_buf), GFP_ATOMIC); + if (rcq->resize_buf == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cq resize buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + ret = roce3_cq_get_umem(rdev, udata, &rcq->resize_buf->buf, &rcq->resize_umem, ucmd.buf_addr, entries); +#else + ret = roce3_cq_get_umem(rdev, rcq->umem->context, &rcq->resize_buf->buf, &rcq->resize_umem, ucmd.buf_addr, entries); +#endif + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get umem, func_id(%d)\n", __func__, rdev->glb_func_id); + + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + + return ret; + } + + rcq->resize_buf->buf.entry_size = rcq->buf.entry_size; + rcq->resize_buf->buf.buf_size = entries * rcq->buf.entry_size; + rcq->resize_buf->cqe = entries - 1; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_free_resize_umem + Description : User mode applies for umem of resize_buf, and MTT corresponding to user mode buf + Input : struct roce3_device *rdev + struct roce3_cq *rcq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_cq_free_resize_umem(struct roce3_device *rdev, struct roce3_cq *rcq) +{ + /* Free MTT and umem of resize_buf */ + roce3_cq_put_umem(rdev, &rcq->resize_buf->buf, &rcq->resize_umem); + rcq->resize_umem = NULL; + + /* free resize_buf itself */ + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + + return; +} + +/* **************************************************************************** + Prototype : roce3_cq_get_outstanding_cqes + Description : roce3_cq_get_outstanding_cqes + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_get_outstanding_cqes(struct roce3_cq *cq) +{ + u32 i = 0; + + i = cq->cons_index; + while (roce3_get_sw_cqe(cq, i)) { + ++i; + } + + return (int)(i - cq->cons_index); +} + +static int roce3_cq_get_next_cqe(struct roce_cqe **cqe, struct roce3_cq *cq, unsigned int *i, u32 *times, + const struct roce_cqe *start_cqe) +{ + int ret = 0; + do { + *cqe = (struct roce_cqe *)roce3_get_sw_cqe(cq, ++(*i)); + if (*cqe == NULL) { + ROCE_MDELAY(MS_DELAY); + --(*times); + } + } while ((*cqe == NULL) && (*times != 0)); + + if ((*cqe == start_cqe) || (*cqe == NULL)) { + pr_err("[ROCE, ERR] %s: Failed to get resize CQE, CQN(0x%x)\n", __func__, cq->cqn); + return -ENOMEM; + } + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_cq_resize_copy_cqes + Description : roce3_cq_resize_copy_cqes + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_resize_copy_cqes(struct roce3_cq *cq) +{ + struct roce_cqe *cqe = NULL; + struct roce_cqe *new_cqe = NULL; + struct roce_cqe *start_cqe = NULL; + u32 times; + unsigned int i = 0; + int ret = 0; + + i = cq->cons_index; + + times = ROCE_CQ_RESIZE_POLL_TIMES; + do { + cqe = (struct roce_cqe *)roce3_get_sw_cqe(cq, i); + if (cqe == NULL) { + ROCE_MDELAY(MS_DELAY); + --times; + } + } while ((cqe == NULL) && (times != 0)); + + if (cqe == NULL) { + pr_err("[ROCE, ERR] %s: Failed to get resize CQE, CQN(0x%x)\n", __func__, cq->cqn); + return -ENOMEM; + } + + start_cqe = cqe; + + /* r_cqe:resize_cqe + CI + +--------+-----+-----+-----+----------+ + old_buf: | | CQE | CQE |R_CQE| | + +--------+-----+-----+-----+----------+ + | | + | | + +--------+-----+-----+-----+----------+ + new_buf: | | CQE | CQE | | | + +--------+-----+-----+-----+----------+ + */ + /* Convert the fields needed by CQE to little endian */ + cqe->dw0.value = roce3_convert_cpu32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_cpu32(cqe->dw1.value); + while (cqe->dw1.bs.op_type != ROCE_OPCODE_RESIZE_CQE) { + /* The resized PI can be inherited, and the index of the original CQE remains unchanged in resize_buf */ + new_cqe = + (struct roce_cqe *)roce3_get_cqe_from_buf(&cq->resize_buf->buf, (i & ((unsigned)cq->resize_buf->cqe))); + + memcpy((void *)new_cqe, (void *)cqe, sizeof(struct roce_cqe)); + + /* If the CQE has been wrapped in resize_buf, the corresponding Owner bit needs to be modified + to be owned by the software. + * The rule is: when the owner bit is owned by CQE software, the O bit is opposite to the high bit of ci; + when the owner bit is owned by hardware, the O bit is the same as the high bit of CI. + */ + new_cqe->dw0.bs.owner = ((i & ((unsigned)cq->resize_buf->cqe + 1)) != 0) ? 1 : 0; + + /* After processing, turn the DW0/DW1 of CQE back to big endian */ + cqe->dw0.value = roce3_convert_be32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_be32(cqe->dw1.value); + + /* Convert DW0/DW1 of the CQE in the new queue back to big endian */ + new_cqe->dw0.value = roce3_convert_be32(new_cqe->dw0.value); + new_cqe->dw1.value = roce3_convert_be32(new_cqe->dw1.value); + + /* Get the next CQE */ + ret = roce3_cq_get_next_cqe(&cqe, cq, &i, ×, start_cqe); + if (ret != 0) { + return ret; + } + + /* Convert DW0/DW1 of CQE to little endian */ + cqe->dw0.value = roce3_convert_cpu32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_cpu32(cqe->dw1.value); + } + + return 0; +} + +static void roce3_cq_fill_resize_inbuf(struct roce3_device *rdev, struct roce3_cq *rcq, int page_shift, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + struct rdma_service_cap *rdma_cap = NULL; + u32 cq_size = 0; + u32 mtt_layer = 0; + u64 mtt_paddr = 0; + u32 mtt_page_size = 0; + roce_cmd_resize_cq_s *cq_resize_inbuf = NULL; + + rdma_cap = &rdev->rdma_cap; + cq_size = (u32)rcq->resize_buf->cqe + 1; + cq_size = (u32)ROCE_ILOG2(cq_size); + mtt_layer = rcq->resize_buf->buf.mtt.mtt_layers; + mtt_paddr = rcq->resize_buf->buf.mtt.mtt_paddr; + mtt_page_size = rcq->resize_buf->buf.mtt.mtt_page_shift - PAGE_SHIFT_4K; + + cq_resize_inbuf = (roce_cmd_resize_cq_s *)cqm_cmd_inbuf->buf; + cq_resize_inbuf->com.index = cpu_to_be32(rcq->cqn); + cq_resize_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_resize_inbuf->page_size = cpu_to_be32((u32)page_shift); + cq_resize_inbuf->log_cq_size = cpu_to_be32(cq_size); + cq_resize_inbuf->mtt_layer_num = cpu_to_be32(mtt_layer); + cq_resize_inbuf->mtt_base_addr = mtt_paddr; + cq_resize_inbuf->mtt_base_addr = cpu_to_be64(cq_resize_inbuf->mtt_base_addr); + cq_resize_inbuf->mtt_page_size = cpu_to_be32(mtt_page_size); + + cq_resize_inbuf->mtt_info.mtt_flags = 0; + cq_resize_inbuf->mtt_info.mtt_num = 0; + cq_resize_inbuf->mtt_info.mtt_cache_line_start = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_start); + cq_resize_inbuf->mtt_info.mtt_cache_line_end = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_end); + cq_resize_inbuf->mtt_info.mtt_cache_line_size = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_sz); +} + +/* **************************************************************************** + Prototype : roce3_cq_resize + Description : roce3_cq_resize + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int page_shift + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_resize(struct roce3_device *rdev, struct roce3_cq *rcq, int page_shift) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_resize_cq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + roce3_cq_fill_resize_inbuf(rdev, rcq, page_shift, cqm_cmd_inbuf); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_RESIZE_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send RESIZE_CQ command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(RESIZE_CQ), cqn(0x%x), func_id(%hu)\n", __func__, + rcq->cqn, rdev->glb_func_id); + + /* When CMDq times out or CMDq cannot work, update the device status and notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + ret = -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return ret; +} + +/* **************************************************************************** + Prototype : roce3_user_cq_resize + Description : roce3_user_cq_resize + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_user_cq_resize(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, struct ib_udata *udata) +{ + int page_shift = 0; + int ret = 0; + + /* Cannot exceed max size after power-of-2 alignment */ + if (entries > ((int)rdev->rdma_cap.max_cqes + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Over range after align, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + ret = roce3_cq_alloc_resize_umem(rdev, rcq, entries, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc resize_umem, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + page_shift = rcq->resize_umem->page_shift - PAGE_SHIFT_4K; +#endif + + /* Send the cq_resize command to configure CQC. After the configuration is successful, the new CQE is written to + resize_buf, and the old buffer may still retain the old CQE. */ + ret = roce3_cq_resize(rdev, rcq, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + roce3_cq_free_resize_umem(rdev, rcq); + return ret; + } + + rcq->ibcq.cqe = rcq->resize_buf->cqe; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_resize_user_cq + Description : roce3_resize_user_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_resize_user_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_resize_cq_cmd ucmd = { 0 }; + int cqe_entries = entries; + + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EFAULT; + } + + if (ucmd.stage == 1) { + goto release_flow; + } + + mutex_lock(&rcq->resize_mutex); + + cqe_entries++; + cqe_entries = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)cqe_entries) & 0xffffffff); /*lint !e587*/ + // Minimum queue depth needs to be aligned by page + if ((u32)(cqe_entries * (int)rdev->rdma_cap.cqe_size) < PAGE_SIZE) { + cqe_entries = (int)(PAGE_SIZE >> (unsigned int)ROCE_ILOG2(rdev->rdma_cap.cqe_size)); + } + + /* The new depth of CQ cannot be the same as the old depth. A special CQE space is reserved when CQ is created, + so the value of ibcq->cqe is 1 smaller than the actual value */ + if (cqe_entries == (rcq->ibcq.cqe + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: No need to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + ret = 0; + goto out; + } + + ret = roce3_user_cq_resize(rdev, rcq, cqe_entries, udata); + if (ret != 0) { + goto out; + } + + mutex_unlock(&rcq->resize_mutex); + + return 0; + +release_flow: + /* free old MTT */ + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + + rcq->buf = rcq->resize_buf->buf; + ib_umem_release(rcq->umem); + rcq->umem = rcq->resize_umem; + + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + rcq->resize_umem = NULL; + +out: + mutex_unlock(&rcq->resize_mutex); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_kernel_cq_resize + Description : roce3_kernel_cq_resize + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_kernel_cq_resize(struct roce3_device *rdev, struct roce3_cq *rcq, int entries) +{ + int outst_cqe = 0; + int page_shift = 0; + int ret = 0; + + /* Cannot exceed max size after power-of-2 alignment */ + if (entries > ((int)rdev->rdma_cap.max_cqes + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Over range after align, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + /* The number of resized CQEs cannot be smaller than the number of outstanding CQEs */ + outst_cqe = roce3_cq_get_outstanding_cqes(rcq); + if (entries < (outst_cqe + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Can't resize, \ + because smaller than the number of outstanding CQES, func_id(%d)\n", + __func__, rdev->glb_func_id); + return -EINVAL; + } + + ret = roce3_cq_alloc_resize_buf(rdev, rcq, entries); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc resize buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + /*lint -e834*/ + page_shift = ROCE_ILOG2(rcq->cqm_cq->q_room_buf_2.buf_size) - PAGE_SHIFT_4K; + /*lint +e834*/ + + /* Send the cq_resize command to configure CQC. After the configuration is successful, the new CQE is written to + resize_buf, and the old buffer may still retain the old CQE. */ + ret = roce3_cq_resize(rdev, rcq, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + roce3_cq_free_resize_buf(rdev, rcq); + return ret; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_resize_kernel_cq + Description : roce3_resize_kernel_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_resize_kernel_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries) +{ + int ret = 0; + int tmp_cqe = 0; + int cqe_entries = entries; + + mutex_lock(&rcq->resize_mutex); + + cqe_entries++; + cqe_entries = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)cqe_entries) & 0xffffffff); /*lint !e587*/ + /* Minimum queue depth needs to be aligned by page */ + if ((u32)(cqe_entries * (int)rdev->rdma_cap.cqe_size) < PAGE_SIZE) { + cqe_entries = (PAGE_SIZE >> (unsigned int)ROCE_ILOG2(rdev->rdma_cap.cqe_size)); + } + + /* The new depth of CQ cannot be the same as the old depth. A special CQE space is reserved when CQ is created, + so the value of ibcq->cqe is 1 smaller than the actual value */ + if (cqe_entries == (rcq->ibcq.cqe + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: No need to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + mutex_unlock(&rcq->resize_mutex); + return 0; + } + + ret = roce3_kernel_cq_resize(rdev, rcq, cqe_entries); + if (ret != 0) { + goto out; + } + + /* free old MTT */ + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + + /* When copying CQE from the old buffer to resize_buf, the user may be polling cqe from the old buf, so + it needs to be locked.If CQE of the old buffer has been polled in the polling process, polling process will + free old buffer and switch to new buffer. + */ + spin_lock_irq(&rcq->lock); + + /* If the new buf has been switched to, nothing needs to be done */ + if (rcq->resize_buf) { + ret = roce3_cq_resize_copy_cqes(rcq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Have not polled resize cqe(fuc:%d, cqn:%u, ret:%d)\n", __func__, + rdev->glb_func_id, rcq->cqn, ret); + spin_unlock_irq(&rcq->lock); + mutex_unlock(&rcq->resize_mutex); + return ret; + } + tmp_cqe = rcq->ibcq.cqe; + rcq->buf = rcq->resize_buf->buf; + rcq->ibcq.cqe = rcq->resize_buf->cqe; + + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + } + + spin_unlock_irq(&rcq->lock); + + /* Non-0 means that the above resize_buf non-empty branch has been entered, the old buffer needs to be released */ + if (tmp_cqe != 0) { + hiudk_cqm_object_resize_free_old(rdev->hwdev, &rcq->cqm_cq->object); + } + +out: + mutex_unlock(&rcq->resize_mutex); + + return ret; +} + +static int roce3_resize_cq_check(struct ib_cq *ibcq, int entries, const struct ib_udata *udata) +{ + struct roce3_device *rdev = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + if ((ibcq->uobject != NULL) && (udata == NULL)) { + pr_err("[ROCE, ERR] %s: Udata is null, but uobject is not null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcq->device); + if ((entries < 1) || (entries > (int)rdev->rdma_cap.max_cqes)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: resize CQEs invalid. entries(%d), func_id(%d)\n", __func__, entries, + rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_resize_cq + Description : roce3_resize_cq + Input : struct ib_cq *ibcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_cq *rcq = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_resize_cq_check(ibcq, entries, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: failed to check resize_cq\n", __func__); + return ret; + } + + rcq = to_roce3_cq(ibcq); + rdev = to_roce3_dev(ibcq->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -1; + } + + if (ibcq->uobject) { + ret = roce3_resize_user_cq(rdev, rcq, entries, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize user cq, func_id(%u) ret(%d)\n", __func__, + (u32)rdev->glb_func_id, ret); + return ret; + } + } else { + ret = roce3_resize_kernel_cq(rdev, rcq, entries); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize kernel cq, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + + return 0; +} + +void roce3_lock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __acquires(&roce3_send_cq->lock) + __acquires(&roce3_recv_cq->lock) +{ + if (roce3_send_cq == roce3_recv_cq) { + spin_lock_irq(&roce3_send_cq->lock); + __acquire(&roce3_recv_cq->lock); + } else if (roce3_send_cq->cqn < roce3_recv_cq->cqn) { + spin_lock_irq(&roce3_send_cq->lock); + spin_lock_nested(&roce3_recv_cq->lock, SINGLE_DEPTH_NESTING); + } else { + spin_lock_irq(&roce3_recv_cq->lock); + spin_lock_nested(&roce3_send_cq->lock, SINGLE_DEPTH_NESTING); + } +} + +void roce3_unlock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __releases(&roce3_send_cq->lock) + __releases(&roce3_recv_cq->lock) +{ + if (roce3_send_cq == roce3_recv_cq) { + __release(&roce3_recv_cq->lock); + spin_unlock_irq(&roce3_send_cq->lock); + } else if (roce3_send_cq->cqn < roce3_recv_cq->cqn) { + spin_unlock(&roce3_recv_cq->lock); + spin_unlock_irq(&roce3_send_cq->lock); + } else { + spin_unlock(&roce3_send_cq->lock); + spin_unlock_irq(&roce3_recv_cq->lock); + } +} diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c new file mode 100644 index 000000000..418159413 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_destroy.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ destroy realted functions. + */ + +#include <linux/slab.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_mix.h" +#include "roce_xrc.h" +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_pub_cmd.h" +#include "hinic3_hmm.h" +#include "roce_main_extension.h" + +static int roce3_check_cqc_data_state(struct roce3_device *rdev, const struct roce3_cq *cq, + struct roce_cq_context *cqc_data, u32 check_state) +{ + int read_back_flag = 0; + int times = rdev->try_times; + struct roce_cq_context check_cqc_data; + + while ((times--) != 0) { + if (roce3_hca_is_present(rdev) == 0) { + return 0; + } + + check_cqc_data.dw2.value = be32_to_cpu(cqc_data->dw2.value); + if (check_cqc_data.dw2.bs.state == check_state) { + read_back_flag = 1; + break; + } + ROCE_UDELAY(US_PERF_DELAY); + } + + if (read_back_flag == 0) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to read back after try %d times, CQ state(0x%x), func_id(%u)\n", __func__, + rdev->try_times, cqc_data->dw2.value, (u32)rdev->glb_func_id); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Cqn(0x%x), timer_dw(0x%x), func_id(%u)\n", __func__, cq->cqn, + cqc_data->dw2.value, (u32)rdev->glb_func_id); + return -1; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_hw2sw + Description : roce3_cq_hw2sw + Input : struct roce3_device *rdev + struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_cq_hw2sw(struct roce3_device *rdev, struct roce3_cq *cq) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct roce_cq_context *cqc_data = NULL; + roce_cmd_cq_hw2sw_s *cq_hw2sw_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_cq_hw2sw_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + cq_hw2sw_inbuf = (roce_cmd_cq_hw2sw_s *)cqm_cmd_inbuf->buf; + cq_hw2sw_inbuf->com.index = cpu_to_be32((u32)cq->cqn); + cq_hw2sw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + + cqc_data = (struct roce_cq_context *)((void *)cq->cqm_cq->q_ctx_vaddr); + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_HW2SW_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send HW2SW_CQ command, func_id(%u), cqn(0x%x), (ret:%d)\n", + __func__, (u32)rdev->glb_func_id, cq->cqn, ret); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(HW2SW_CQ), cqn(0x%x), func_id(%hu)\n", __func__, + cq->cqn, rdev->glb_func_id); + + /* When CMDq times out or CMDq cannot work, update the device status and notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + /* CMDq may return a positive number, so its return value cannot be used directly */ + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return roce3_check_cqc_data_state(rdev, cq, cqc_data, ROCE_CQ_TIME_OUT_CHECK_VALUE); +} + +static int roce3_cq_cache_out(struct roce3_device *rdev, struct roce3_cq *cq) +{ + int ret = 0; + struct rdma_service_cap *rdma_cap = NULL; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_cq_cache_invalidate_s *cq_cache_invld_inbuf = NULL; + + /* Send the cache out command */ + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_cq_cache_invalidate_s), NULL, + 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + dev_dbg(rdev->hwdev_hdl, "[ROCE, INFO] %s: func_id(%d) cqn(%d)\n", __func__, rdev->glb_func_id, cq->cqn); + rdma_cap = &rdev->rdma_cap; + cq_cache_invld_inbuf = (roce_cmd_cq_cache_invalidate_s *)cqm_cmd_inbuf->buf; + cq_cache_invld_inbuf->com.index = cpu_to_be32((u32)cq->cqn); + cq_cache_invld_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_cache_invld_inbuf->mtt_info.mtt_flags = 0; + cq_cache_invld_inbuf->mtt_info.mtt_num = 0; + cq_cache_invld_inbuf->mtt_info.mtt_cache_line_start = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_start); + cq_cache_invld_inbuf->mtt_info.mtt_cache_line_end = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_end); + cq_cache_invld_inbuf->mtt_info.mtt_cache_line_size = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_sz); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_MISC_CQ_CACHE_INVLD, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send CQ_CACHE_INVLD command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(CQ_CACHE_INVLD), cqn(0x%x), func_id(%hu)\n", __func__, + cq->cqn, rdev->glb_func_id); + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + /* When CMDq times out or CMDq cannot work, update the device status and notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return -1; + } + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return 0; +} + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +static void destroy_cq_user(struct roce3_cq *cq, struct ib_udata *udata) +{ + struct roce3_ucontext *context = rdma_udata_to_drv_context( + udata, struct roce3_ucontext, ibucontext); + + roce3_db_unmap_user(context, &cq->db); + ib_umem_release(cq->umem); +} + +int roce3_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_cq *cq = NULL; + struct roce_cq_context *cqc_data = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcq->device); + cq = to_roce3_cq(ibcq); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return ok), func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_roce_cq_free; + } + + /* Modify CQC to be owned by the software */ + ret = roce3_cq_hw2sw(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify CQC, ret(%d), func_id(%hu), cqn(0x%x)\n", + __func__, ret, rdev->glb_func_id, cq->cqn); + return ret; + } + + /* Send the cache out command */ + ret = roce3_cq_cache_out(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to modify cqc, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + return ret; + } + + cqc_data = (struct roce_cq_context *)((void *)cq->cqm_cq->q_ctx_vaddr); + ret = roce3_check_cqc_data_state(rdev, cq, cqc_data, ROCE_CQ_STATE_CHECK_VALUE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: check cqc data state fail, func_id(%hu)\n", __func__, rdev->glb_func_id); + return ret; + } + +err_roce_cq_free: + /* Release the MTT corresponding to cq_buf */ + hmm_rdma_mtt_free(rdev->hwdev, &cq->buf.mtt, SERVICE_T_ROCE); + + /* Call the CQM interface to release CQN and CQC. Since there is no cq_buf and software DB in user mode, + it does not need to be released; since kernel mode has both, it needs to be released */ + hiudk_cqm_object_delete(rdev->hwdev, &cq->cqm_cq->object); + + /* If it is user mode, you also need to cancel the mapping of the corresponding software DB */ + if (ibcq->uobject) { + destroy_cq_user(cq, udata); + } + + return 0; +} +#else +int roce3_destroy_cq(struct ib_cq *ibcq) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_cq *cq = NULL; + struct roce_cq_context *cqc_data = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcq->device); + cq = to_roce3_cq(ibcq); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return ok), func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_roce_cq_free; + } + + /* Modify CQC to be owned by the software */ + ret = roce3_cq_hw2sw(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify CQC, ret(%d), func_id(%d), cqn(0x%x)\n", + __func__, ret, rdev->glb_func_id, cq->cqn); + return ret; + } + + /* Send the cache out command */ + ret = roce3_cq_cache_out(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to modify cqc, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + return ret; + } + + cqc_data = (struct roce_cq_context *)((void *)cq->cqm_cq->q_ctx_vaddr); + ret = roce3_check_cqc_data_state(rdev, cq, cqc_data, ROCE_CQ_STATE_CHECK_VALUE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: check cqc data state fail, func_id(%hu)\n", __func__, rdev->glb_func_id); + return ret; + } + +err_roce_cq_free: + /* Release the MTT corresponding to cq_buf */ + hmm_rdma_mtt_free(rdev->hwdev, &cq->buf.mtt, SERVICE_T_ROCE); + + /* Call the CQM interface to release CQN and CQC. Since there is no cq_buf and software DB in user mode, + it does not need to be released; since kernel mode has both, it needs to be released */ + hiudk_cqm_object_delete(rdev->hwdev, &cq->cqm_cq->object); + + /* If it is user mode, you also need to cancel the mapping of the corresponding software DB */ + if (ibcq->uobject) { + roce3_db_unmap_user(to_roce3_ucontext(ibcq->uobject->context), &cq->db); + ib_umem_release(cq->umem); + } + + kfree(cq); + + return 0; +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c new file mode 100644 index 000000000..8afffe554 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx.c + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of callback functions and internal functions of RoCE driver dfx features. + */ + +#ifdef __ROCE_DFX__ + +#include <linux/fs.h> +#include <linux/slab.h> + +#include "hinic3_mt.h" + +#include "roce.h" +#include "roce_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_dfx.h" + + +void roce3_dfx_clean_up(struct roce3_device *rdev) +{ +#ifdef ROCE_PKT_CAP_EN + (void)roce3_dfx_stop_cap_pkt(rdev, NULL, NULL); +#endif +} + +int roce3_get_drv_version(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct drv_version_info *ver_info = buf_out; + int rc; + + if (!buf_out) { + pr_err("Buf_out is NULL.\n"); + return -EINVAL; + } + + if (*out_size != sizeof(*ver_info)) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", *out_size, sizeof(*ver_info)); + return -EINVAL; + } + + rc = snprintf(ver_info->ver, sizeof(ver_info->ver), "%s %s", + HIROCE3_DRV_VERSION, __TIME_STR__); + if (rc == -1) { + pr_err("Snprintf roce version err\n"); + return -EFAULT; + } + + return 0; +} + +static int roce3_dfx_enable_bw_ctrl(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + if (rdev->hw_info.hca_type == ROCE3_2_100G_HCA) { + inbuf->ctrl_param.cir = ROCE3_100G_CIR; + inbuf->ctrl_param.pir = ROCE3_100G_PIR; + inbuf->ctrl_param.cnp = ROCE3_100G_CNP; + } else { + inbuf->ctrl_param.cir = ROCE3_25G_CIR; + inbuf->ctrl_param.pir = ROCE3_25G_PIR; + inbuf->ctrl_param.cnp = ROCE3_25G_CNP; + } + return roce3_set_bw_ctrl_state(rdev, ROCE_BW_CTRL_EN, inbuf); +} + +static int roce3_dfx_disable_bw_ctrl(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + inbuf->ctrl_param.cir = 0; + inbuf->ctrl_param.pir = 0; + inbuf->ctrl_param.cnp = 0; + return roce3_set_bw_ctrl_state(rdev, ROCE_BW_CTRL_DIS, inbuf); +} + +static int roce3_dfx_change_bw_ctrl_param(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + return roce3_set_bw_ctrl_state(rdev, ROCE_BW_CTRL_RESET, inbuf); +} + +static int roce3_dfx_query_bw_ctrl_param(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + return roce3_query_bw_ctrl_state(rdev, &outbuf->bw_ctrl_param); +} + +typedef int (*roce3_adm_dfx_bw_ctrl_func_t)(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf); + +/*lint -e26*/ +static roce3_adm_dfx_bw_ctrl_func_t g_roce3_adm_dfx_bw_ctrl_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [ROCE_CMD_ENABLE_BW_CTRL] = roce3_dfx_enable_bw_ctrl, + [ROCE_CMD_DISABLE_BW_CTRL] = roce3_dfx_disable_bw_ctrl, + [ROCE_CMD_CHANGE_BW_CTRL_PARAM] = roce3_dfx_change_bw_ctrl_param, + [ROCE_CMD_QUERY_BW_CTRL_PARAM] = roce3_dfx_query_bw_ctrl_param, +}; +/*lint +e26*/ + +int roce3_adm_dfx_bw_ctrl(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct roce3_bw_ctrl_inbuf *inbuf = (struct roce3_bw_ctrl_inbuf *)buf_in; + struct roce3_bw_ctrl_outbuf *outbuf = (struct roce3_bw_ctrl_outbuf *)buf_out; + roce3_adm_dfx_bw_ctrl_func_t roce3_adm_dfx_bw_ctrl_func; + + memset(buf_out, 0, sizeof(struct roce3_bw_ctrl_outbuf)); + *out_size = sizeof(struct roce3_bw_ctrl_outbuf); + + if (inbuf->cmd_type >= COMMON_CMD_VM_COMPAT_TEST) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + roce3_adm_dfx_bw_ctrl_func = g_roce3_adm_dfx_bw_ctrl_funcs[inbuf->cmd_type]; + if (roce3_adm_dfx_bw_ctrl_func == NULL) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + return roce3_adm_dfx_bw_ctrl_func(rdev, inbuf, outbuf); +} +#endif /* __ROCE_DFX__ */ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h new file mode 100644 index 000000000..86f099002 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx.h + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of macros, data structure, function prototype etc of RoCE driver dfx features. + */ + +#ifndef ROCE_DFX_H +#define ROCE_DFX_H + +#include <linux/types.h> + +#include "hinic3_rdma.h" + +#include "roce_sysfs.h" +#include "roce.h" +#include "roce_verbs_cmd.h" +#include "rdma_context_format.h" + +#ifdef ROCE_PKT_CAP_EN +#include "roce_dfx_cap.h" +#endif + +#define MR_KEY_2_INDEX_SHIFT 8 + +#define ROCE_IO_DFX_CFG_VADDR_ID 0 +#define ROCE_IO_DFX_CFG_PADDR_ID 1 +#define ROCE_IO_DFX_CFG_ADDR_NUM 2 + +struct roce3_mpt_query_outbuf { + struct roce_mpt_context mpt_entry; +}; + +#define roce3_dfx_print(fmt, args...) \ + do { \ + (void)printk("[roce3_dfx] : " fmt "\n", ##args); \ + } while (0) + +struct roce3_dfx_query_inbuf { + u32 cmd_type; + /*lint -e658*/ + union { + u32 qpn; + u32 cqn; + u32 srqn; + u32 mpt_key; + u32 gid_index; + struct { + u32 qpn; + u32 cqn; + } query_pi_ci; + }; + /*lint +e658*/ +}; + +struct roce3_dfx_pi_ci { + u32 qpc_sq_pi_on_chip; + u32 qpc_sq_pi; + u32 qpc_sq_load_pi; + u32 qpc_rq_pi_on_chip; + u32 qpc_rq_load_pi; + u32 qpc_rq_pi; + u32 qpc_rc_pi; + u32 qpc_sq_ci; + u32 qpc_sq_wqe_prefetch_ci; + u32 qpc_sq_mtt_prefetch_wqe_ci; + u32 qpc_sqa_ci; + u32 qpc_sqa_wqe_prefetch_ci; + u32 qpc_rq_ci; + u32 qpc_rq_wqe_prefetch_ci; + u32 qpc_rq_mtt_prefetch_wqe_ci; + u32 qpc_rq_base_ci; + u32 qpc_rc_ci; + u32 qpc_rc_prefetch_ci; + u32 cq_ci_on_chip; + u32 cq_ci; + u32 cq_load_ci; + u64 cq_ci_record_gpa_at_hop_num; + u32 cq_last_solicited_pi; + u32 cq_pi; + u32 cq_last_notified_pi; +}; + +struct roce3_dfx_qp_count { + u32 qp_alloced; + u32 qp_deleted; + u32 qp_alive; +}; + +union roce3_dfx_query_outbuf { + struct roce_qp_context qp_ctx; + struct roce_cq_context cq_ctx; + struct roce_srq_context srq_ctx; + struct roce_mpt_context mpt; + struct rdma_gid_entry gid_entry; + struct roce3_dfx_pi_ci pi_ci; + struct roce3_dfx_qp_count qp_count; + u32 algo_type; +}; + +enum roce3_bw_ctrl_cmd_e { + ROCE_BW_CTRL_DIS, + ROCE_BW_CTRL_EN, + ROCE_BW_CTRL_RESET +}; +struct rdma_gid_query_outbuf { + struct rdma_gid_entry gid_entry; +}; + +struct roce3_bw_ctrl_inbuf { + u32 cmd_type; + struct { + u32 cir; + u32 pir; + u32 cnp; + } ctrl_param; +}; + +struct roce3_bw_ctrl_param { + u8 color_type; + u16 ptype; + u8 hw_wred_mode; + + u32 cir; + u32 pir; + u32 cbs; + u32 xbs; + u32 cnp; + u32 enable; +}; + +struct roce3_bw_ctrl_outbuf { + struct roce3_bw_ctrl_param bw_ctrl_param; +}; + +enum roce3_dfx_io_cmd_type { + ROCE_IO_CTRL_DIS, + ROCE_IO_CTRL_EN +}; + +struct roce3_dfx_io_alarm { + enum roce3_dfx_io_cmd_type en_flag; + u16 pf_id; + u16 rsvd; + u16 io_latency_thd; + u16 exec_time; + u32 exp_qpn; + void *rcd_uaddr; + struct timespec64 start; + struct mutex io_alarm_mutex; +}; + +struct roce3_dfx_io_inbuf { + u32 cmd_type; + struct roce3_dfx_io_alarm io_alarm; +}; + +struct roce3_dfx_io_outbuf { + struct roce3_dfx_io_alarm io_alarm; +}; + +int roce3_get_drv_version(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +int roce3_adm_dfx_query(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +int roce3_adm_dfx_bw_ctrl(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +void roce3_dfx_clean_up(struct roce3_device *rdev); + +void *global_roce3_io_alarm_va_get(void); + +void global_roce3_io_alarm_va_set(u64 va); + +void global_roce3_io_alarm_pa_set(dma_addr_t pa); + +dma_addr_t global_roce3_io_alarm_pa_get(void); + +int roce3_dfx_cmd_query_qp(struct roce3_device *rdev, u32 qpn, struct roce_qp_context *qp_ctx); + +int roce3_dfx_cmd_query_cq(struct roce3_device *rdev, u32 cqn, struct roce_cq_context *cq_ctx); + +int roce3_dfx_cmd_query_srq(struct roce3_device *rdev, u32 srqn, struct roce_srq_context *srq_ctx); + +#endif // __ROCE_DFX_H__ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c new file mode 100644 index 000000000..c511a4dfd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c @@ -0,0 +1,676 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_dfx_cap.c + * Version : v2.1 + * Created : 2022/7/28 + * Last Modified : 2022/7/28 + * Description : The definition of callback functions and internal functions of RoCE driver dfx cap features. + */ + +#ifdef ROCE_PKT_CAP_EN + +#include <linux/mutex.h> +#include <linux/kthread.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> +#include <linux/etherdevice.h> +#include <rdma/ib_verbs.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_dfx.h" +#include "roce_dfx_cap.h" +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +static struct roce3_cap_block_num_attr g_nattr[8] = { + { .block_num_idx = 0, .shift = 4, .num = 16 }, + { .block_num_idx = 1, .shift = 5, .num = 32 }, + { .block_num_idx = 2, .shift = 6, .num = 64 }, + { .block_num_idx = 3, .shift = 7, .num = 128 }, + { .block_num_idx = 4, .shift = 8, .num = 256 }, + { .block_num_idx = 5, .shift = 9, .num = 512 }, + { .block_num_idx = 6, .shift = 10, .num = 1024 }, + { .block_num_idx = 7, .shift = 11, .num = 2048 }, +}; + +struct roce3_pkt_cap_info g_roce3_cap_info = { + .cap_status = ROCE_CAPTURE_STOP, + .cap_mode = 1, + .poll_ci = 0, + .rdev = NULL, + .func_id = 0, + // Configurable, currently using 4, when modifying, the size of cfg bl needs to be modified synchronously + .block_num_idx = 4, + .mode = 0, + .qp_list_cnt = 0, + .qp_list_head = LIST_HEAD_INIT(g_roce3_cap_info.qp_list_head), +}; + +static void roce3_stop_thread(struct sdk_thread_info *thread_info) +{ + if (thread_info->thread_obj) { + (void)kthread_stop(thread_info->thread_obj); + thread_info->thread_obj = NULL; + } +} + +static int roce3_linux_thread_func(void *thread) +{ + struct sdk_thread_info *info = (struct sdk_thread_info *)thread; + + while (!kthread_should_stop()) { + info->thread_fn(info->data); + + // Warning: kernel thread should reschedule + schedule(); + } + + return 0; +} +#ifdef ROCE_BONDING_EN +static struct net_device *roce3_get_roce_bond_ndev(struct roce3_device *rdev) +{ + struct bonding *bond = NULL; + struct slave *slave = NULL; + struct net_device *netdev = rdev->ndev; + + if (netif_is_lag_master(netdev)) { + bond = netdev_priv(netdev); + } else if (netif_is_bond_slave(netdev)) { + rcu_read_lock(); + slave = bond_slave_get_rcu(netdev); + rcu_read_unlock(); + if (slave) { + bond = bond_get_bond_by_slave(slave); + } + } + + if ((bond == NULL) || (bond->dev == NULL)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Bond/bond->dev is NULL\n", __func__); + return NULL; + } + + return bond->dev; +} +#endif +static void roce3_netif_skb_info(struct roce3_device *rdev, const char *pkt, u8 len) +{ + struct sk_buff *skb = NULL; + unsigned char *packet = NULL; + struct net_device *netdev = rdev->ndev; +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + netdev = roce3_get_roce_bond_ndev(rdev); + if (netdev == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get roce_bond ndev\n", __func__); + return; + } + } +#endif + /* alloc skb and set skb->dev */ + skb = netdev_alloc_skb_ip_align(netdev, CAP_NUM_PER_BLOCK + 1); + if (unlikely(skb == NULL)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc skb\n", __func__); + return; + } + + skb_reserve(skb, CAP_COUNTER_TWO); + + /* put space for pkt */ + packet = (unsigned char *)skb_put(skb, len); + if (packet == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get packet\n", __func__); + kfree_skb(skb); + return; + } + + /* copy pkt hdr */ + memcpy(packet, pkt, len); + + prefetchw(skb->data); + + /* resolve protocol and type */ + skb->protocol = eth_type_trans(skb, netdev); + + /* force to host */ + skb->pkt_type = 0; + + netif_receive_skb(skb); +} + +static int roce3_set_cap_func_disable(struct roce3_device *rdev) +{ + int ret; + + ret = hinic3_set_func_capture_en(rdev->hwdev, rdev->glb_func_id, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set capture disable, ret(%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +static int roce3_create_thread(struct sdk_thread_info *thread_info) +{ + thread_info->thread_obj = kthread_run(roce3_linux_thread_func, thread_info, thread_info->name); + if (!thread_info->thread_obj) { + pr_err("[ROCE, ERR] %s: Failed to create thread\n", __func__); + return (-EFAULT); + } + + return 0; +} + +static int roce3_set_cap_func_en(struct roce3_device *rdev) +{ + int ret; + + ret = hinic3_set_func_capture_en(rdev->hwdev, rdev->glb_func_id, 1); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set capture func enable, ret(%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +static int roce3_pkt_cap_poll_check(struct roce3_device *rdev) +{ + if (rdev == NULL) { + pr_err("[ROCE] %s: Rdev is null\n", __func__); + return (-EINVAL); + } + + if (rdev->hwdev == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Rdev->hwdev is null\n", __func__); + return (-EINVAL); + } + + if (g_roce3_cap_info.cap_status == ROCE_CAPTURE_STOP) { + /* Don't add log here */ + return (-EINVAL); + } + + return 0; +} + +static int roce3_cap_hdr_vld(const roce3_cap_hdr_u *cap_hdr) +{ + return (cap_hdr->value != 0); +} + +static void roce3_fill_cap_cfg(struct roce3_dfx_cap_cfg_tbl *cfg_info, u32 state, u32 ci_index, u8 mode) +{ + cfg_info->ci_index = ci_index; + + cfg_info->dw1.bs.cap_block_num_shift = (u8)g_nattr[g_roce3_cap_info.block_num_idx].shift; // 8 + cfg_info->dw1.bs.cap_mode = (u8)g_roce3_cap_info.cap_mode; + cfg_info->dw1.bs.qp_mode = mode; + + cfg_info->dw2.bs.state = state; + cfg_info->dw2.bs.cap_func = g_roce3_cap_info.func_id; + + cfg_info->maxnum = g_nattr[g_roce3_cap_info.block_num_idx].num * CAP_NUM_PER_BLOCK; +} + +static void roce3_pkt_cap_poll_hdr(struct roce3_pkt_cap_info *cap_info, union roce3_cap_hdr **cap_hdr, + union roce3_cap_hdr *hdr_value) +{ + u32 lt_index; + u32 lt_offset; + u8 sel; + u32 block_num_per_entry = g_nattr[g_roce3_cap_info.block_num_idx].num; + u32 block_num_shift = g_nattr[g_roce3_cap_info.block_num_idx].shift; + + /* resolve index and offset */ + lt_index = (((cap_info->poll_ci) / block_num_per_entry) % CAP_PA_TBL_ENTRY_NUM); + lt_offset = ((cap_info->poll_ci) % (block_num_per_entry >> 1)); + sel = ((cap_info->poll_ci >> (block_num_shift - 1)) & 0x1); + + *cap_hdr = (roce3_cap_hdr_u *)(cap_info->que_addr[sel][0][lt_index] + (lt_offset * CAP_PKT_ITEM_SIZE)); + + hdr_value->value = (*cap_hdr)->value; + /* First, execute big endian and small endian switch operation for ctrl information */ + hdr_value->value = ntohl(hdr_value->value); +} + +static void roce3_pkt_cap_poll(void *data) +{ + int ret; + u32 count = 0; + struct roce3_dfx_cap_cfg_tbl cfg_info = { 0 }; + union roce3_cap_hdr hdr_value = { { 0 } }; + struct roce3_pkt_cap_info *cap_info = (struct roce3_pkt_cap_info *)data; + struct roce3_device *rdev = cap_info->rdev; + union roce3_cap_hdr *cap_hdr = NULL; + + if (roce3_pkt_cap_poll_check(rdev) != 0) { + return; + } + + roce3_pkt_cap_poll_hdr(cap_info, &cap_hdr, &hdr_value); + + if (roce3_cap_hdr_vld(&hdr_value) == 0) { + return; + } + + do { + if (g_roce3_cap_info.cap_status == ROCE_CAPTURE_STOP) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Cap is stopped\n", __func__); + return; + } + + roce3_netif_skb_info(rdev, ((u8 *)cap_hdr + CAP_HDR_OFFSET + hdr_value.cap_ctrl_info.pad), CAP_SKB_LEN); + + /* reset to 0 */ + cap_hdr->value = 0; + cap_info->poll_ci++; + + if (g_roce3_cap_info.cap_mode != 0) { + count++; + if (count >= (FILL_CAP_CFG_PKT_NUM)) { + roce3_fill_cap_cfg(&cfg_info, 0, cap_info->poll_ci, 0); + + (void)roce3_set_cap_cfg(rdev->hwdev, CAP_PA_TBL_ENTRY_NUM, (u32 *)&cfg_info); + + count = 0; + } + } + + roce3_pkt_cap_poll_hdr(cap_info, &cap_hdr, &hdr_value); + + if (unlikely(kthread_should_stop())) { + break; + } + + schedule(); + } while (roce3_cap_hdr_vld(&hdr_value) != 0); + + roce3_fill_cap_cfg(&cfg_info, 0, cap_info->poll_ci, 0); + + ret = roce3_set_cap_cfg(rdev->hwdev, CAP_PA_TBL_ENTRY_NUM, (u32 *)&cfg_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap cfg, ret(%d)\n", __func__, ret); + return; + } +} + +static int roce3_dfx_dma_alloc_addr(struct roce3_device *rdev, int cap_index, int que_index, + struct roce3_dfx_cap_tbl *pa_info) +{ + u64 v_addr; + u64 p_addr = 0; + + v_addr = (uintptr_t)(u64 *)dma_alloc_coherent(&rdev->pdev->dev, + (unsigned long)(CAP_PKT_ITEM_SIZE * ((g_nattr[g_roce3_cap_info.block_num_idx].num) >> 1)), &p_addr, GFP_KERNEL); + if (v_addr == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to alloc v_addr for que_index %d\n", __func__, que_index); + return -ENOMEM; + } + + g_roce3_cap_info.que_addr[que_index][0][cap_index] = v_addr; + g_roce3_cap_info.que_addr[que_index][1][cap_index] = p_addr; + + pa_info->pa[que_index].wr_init_pc_h32 = (u32)((p_addr >> CAP_ADDR_COMBIN_SHIFT) & 0xffffffff); + pa_info->pa[que_index].wr_init_pc_l32 = (u32)(p_addr & 0xffffffff); + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: v_addr que_index(%d), cap_index(%d), PA:0x%x %x\n", __func__, que_index, + cap_index, pa_info->pa[que_index].wr_init_pc_h32, pa_info->pa[que_index].wr_init_pc_l32); + + return 0; +} + +static void roce3_dfx_dma_free_addr(struct roce3_device *rdev, int cap_index, int que_index) +{ + u64 v_addr; + u64 p_addr; + + v_addr = g_roce3_cap_info.que_addr[que_index][0][cap_index]; + p_addr = g_roce3_cap_info.que_addr[que_index][1][cap_index]; + dma_free_coherent(&rdev->pdev->dev, + (unsigned long)(CAP_PKT_ITEM_SIZE * ((g_nattr[g_roce3_cap_info.block_num_idx].num) >> 1)), (void *)v_addr, + (dma_addr_t)p_addr); +} + +static int roce3_dfx_alloc_mem_for_one_cap(struct roce3_device *rdev, int cap_index) +{ + struct roce3_dfx_cap_tbl pa_info; + int ret; + + memset(&pa_info, 0x0, sizeof(pa_info)); + + ret = roce3_dfx_dma_alloc_addr(rdev, cap_index, 0, &pa_info); + if (ret != 0) { + return ret; + } + + ret = roce3_dfx_dma_alloc_addr(rdev, cap_index, 1, &pa_info); + if (ret != 0) { + goto err_dma_mem_alloc_free_1; + } + + ret = roce3_set_cap_cfg(rdev->hwdev, (u16)cap_index, (u32 *)&pa_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap cfg, ret(%d)\n", __func__, ret); + goto err_dma_mem_alloc_free; + } + + return 0; + +err_dma_mem_alloc_free: + roce3_dfx_dma_free_addr(rdev, cap_index, 1); + +err_dma_mem_alloc_free_1: + roce3_dfx_dma_free_addr(rdev, cap_index, 0); + return ret; +} + +static void roce3_dfx_free_mem_for_one_cap(struct roce3_device *rdev, int cap_index) +{ + roce3_dfx_dma_free_addr(rdev, cap_index, 1); + roce3_dfx_dma_free_addr(rdev, cap_index, 0); +} + +static int roce3_dfx_alloc_cap(struct roce3_device *rdev) +{ + u32 counter, times; + int ret; + int i; + + /* alloc lt memory resource */ + for (i = 0; i < CAP_PA_TBL_ENTRY_NUM; i++) { + ret = roce3_dfx_alloc_mem_for_one_cap(rdev, i); + if (ret != 0) { + goto err_dma_mem_alloc_free; + } + } + + for (times = 0; times < CLEAR_CAP_TRYING_TIMES; times++) { + if (times == CLEAR_CAP_TRYING_TIMES - 1) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear pi\n", __func__); + goto err_dma_mem_alloc_free; + } + + /* clear pi */ + ret = roce3_clear_cap_counter(rdev->hwdev, ROCE_CAP_COUNTER_INDEX, &counter); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to read counter(lt index %x), ret(%d)\n", __func__, + ROCE_CAP_COUNTER_INDEX, ret); + goto err_dma_mem_alloc_free; + } + + if (counter == 0) { + break; + } + + msleep(CLEAR_SLEEP_TIME); + } + + return 0; + +err_dma_mem_alloc_free: + for (i--; i >= 0; i--) { + roce3_dfx_free_mem_for_one_cap(rdev, i); + } + + return ret; +} + +static void roce3_dfx_free_cap(struct roce3_device *rdev) +{ + int i; + + for (i = 0; i < CAP_PA_TBL_ENTRY_NUM; i++) { + roce3_dfx_free_mem_for_one_cap(rdev, i); + } +} + +static void roce3_dfx_init_g_cap_info(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf) +{ + u32 mode = inbuf->mode; + + g_roce3_cap_info.func_id = rdev->glb_func_id; + g_roce3_cap_info.task.data = &g_roce3_cap_info; + g_roce3_cap_info.task.thread_fn = roce3_pkt_cap_poll; + g_roce3_cap_info.task.name = "capture_thread"; + g_roce3_cap_info.rdev = rdev; + g_roce3_cap_info.poll_ci = 0; + g_roce3_cap_info.block_num_per_entry = g_nattr[g_roce3_cap_info.block_num_idx].num; + g_roce3_cap_info.maxnum = (g_nattr[g_roce3_cap_info.block_num_idx].num) * CAP_PA_TBL_ENTRY_NUM; + g_roce3_cap_info.mode = mode; + g_roce3_cap_info.qp_list_cnt = 0; +} + +static int roce3_dfx_start_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf) +{ + struct roce3_dfx_cap_cfg_tbl cfg_info; + int ret; + + mutex_lock(&cap_mutex); + if (g_roce3_cap_info.cap_status == ROCE_CAPTURE_START) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Capture is running\n", __func__); + mutex_unlock(&cap_mutex); + return (-EBUSY); + } + + ret = roce3_dfx_alloc_cap(rdev); + if (ret != 0) { + mutex_unlock(&cap_mutex); + return ret; + } + + roce3_dfx_init_g_cap_info(rdev, inbuf); + + memset(&cfg_info, 0, sizeof(cfg_info)); + roce3_fill_cap_cfg(&cfg_info, 0, 0, 0); + + ret = roce3_set_cap_cfg(rdev->hwdev, CAP_PA_TBL_ENTRY_NUM, (u32 *)&cfg_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap cfg, ret(%d)\n", __func__, ret); + goto err_alloc_cap; + } + + dev_err(rdev->hwdev_hdl, "[ROCE] %s: roce create thread\n", __func__); + ret = roce3_create_thread(&(g_roce3_cap_info.task)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to create thread, ret(%d)\n", __func__, ret); + goto err_alloc_cap; + } + + ret = roce3_set_cap_func_en(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap enable, ret(%d)\n", __func__, ret); + goto err_thread_release; + } + + g_roce3_cap_info.cap_status = ROCE_CAPTURE_START; + INIT_LIST_HEAD(&g_roce3_cap_info.qp_list_head); + mutex_unlock(&cap_mutex); + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: Start to capture pkt, func(%u)\n", __func__, g_roce3_cap_info.func_id); + return 0; + +err_thread_release: + roce3_stop_thread(&(g_roce3_cap_info.task)); + msleep(CAP_STOP_SLEEP_TIME); + +err_alloc_cap: + roce3_dfx_free_cap(rdev); + + g_roce3_cap_info.cap_status = ROCE_CAPTURE_STOP; + mutex_unlock(&cap_mutex); + + return ret; +} + +static int roce3_clear_cap_counter_encap(struct roce3_device *rdev, u16 lt_index) +{ + int ret; + u32 counter = 0; + u32 times; + + for (times = 0; times < CLEAR_CAP_TRYING_TIMES; times++) { + if (times == CLEAR_CAP_TRYING_TIMES - 1) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear pi\n", __func__); + return -EFAULT; + } + + ret = roce3_clear_cap_counter(rdev->hwdev, lt_index, &counter); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear cap counter(lt index 1), ret(%d)\n", __func__, ret); + return -EFAULT; + } + + if (counter == 0) { + break; + } + + msleep(CLEAR_SLEEP_TIME); + } + + return 0; +} + +int roce3_dfx_stop_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf) +{ + int ret = 0; + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: start to stop cap, \n", __func__); + + mutex_lock(&cap_mutex); + if (g_roce3_cap_info.cap_status != ROCE_CAPTURE_START) { // 1:RUNNING + mutex_unlock(&cap_mutex); + return 0; + } + + if (g_roce3_cap_info.func_id != rdev->glb_func_id) { + mutex_unlock(&cap_mutex); + return 0; + } + + roce3_stop_thread(&(g_roce3_cap_info.task)); + + /* stop cap */ + ret = roce3_set_cap_func_disable(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap enable, ret(%d)\n", __func__, ret); + ret = -EFAULT; + goto err; + } + + msleep(CAP_STOP_SLEEP_TIME); + + /* release lt mem resource */ + roce3_dfx_free_cap(rdev); + + /* lt index_1 */ + ret = roce3_clear_cap_counter_encap(rdev, ROCE_CAP_COUNTER_INDEX); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear pi(lt index %x), ret(%d)\n", __func__, + ROCE_CAP_COUNTER_INDEX, ret); + goto err; + } + + g_roce3_cap_info.cap_status = ROCE_CAPTURE_STOP; + g_roce3_cap_info.poll_ci = 0; + g_roce3_cap_info.func_id = 0; + g_roce3_cap_info.rdev = NULL; + dev_info(rdev->hwdev_hdl, "[ROCE] %s: Stop capture pkt, func(%d)\n", __func__, rdev->glb_func_id); + +err: + mutex_unlock(&cap_mutex); + return ret; +} + +static int roce3_dfx_query_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf) +{ + int ret; + u32 pi = 0; + u32 total = 0; + struct roce3_dfx_cap_cfg_tbl cfg_info; + struct roce3_dfx_capture_info *capture_info = &outbuf->capture_info; + + memset(&cfg_info, 0, sizeof(cfg_info)); + ret = roce3_get_cap_cfg(rdev->hwdev, CAP_NUM_PER_BLOCK, (u32 *)&cfg_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read table, ret(%d)\n", __func__, ret); + return -EFAULT; + } + + ret = roce3_read_cap_counter(rdev->hwdev, CAP_COUNTER_TWO, &total); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read counter(lt index 2), ret(%d)\n", __func__, ret); + return -EFAULT; + } + + ret = roce3_read_cap_counter(rdev->hwdev, ROCE_CAP_COUNTER_INDEX, &pi); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read counter(lt index %x), ret(%d)\n", __func__, + ROCE_CAP_COUNTER_INDEX, ret); + return -EFAULT; + } + + capture_info->cap_status = g_roce3_cap_info.cap_status; + capture_info->cap_mode = cfg_info.dw1.bs.cap_mode; + capture_info->qp_mode = cfg_info.dw1.bs.qp_mode; + capture_info->cap_block_num_shift = cfg_info.dw1.bs.cap_block_num_shift; + capture_info->cap_func = cfg_info.dw2.bs.cap_func; + capture_info->cap_state = cfg_info.dw2.bs.state; + capture_info->cap_max_num = cfg_info.maxnum; + capture_info->cap_ci = g_roce3_cap_info.poll_ci; + capture_info->cap_pi = pi; + capture_info->cap_total = total; + + return 0; +} + +typedef int (*roce3_adm_dfx_capture_func_t)(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf); + +/*lint -e26*/ +static roce3_adm_dfx_capture_func_t g_roce3_adm_dfx_capture_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [ROCE_CMD_START_CAP_PACKET] = roce3_dfx_start_cap_pkt, + [ROCE_CMD_STOP_CAP_PACKET] = roce3_dfx_stop_cap_pkt, + [ROCE_CMD_QUERY_CAP_INFO] = roce3_dfx_query_cap_pkt, + [ROCE_CMD_ENABLE_QP_CAP_PACKET] = NULL, + [ROCE_CMD_DISABLE_QP_CAP_PACKET] = NULL, + [ROCE_CMD_QUERY_QP_CAP_INFO] = NULL, +}; +/*lint +e26*/ + +int roce3_adm_dfx_capture(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int ret; + const struct roce3_dfx_capture_inbuf *inbuf = (struct roce3_dfx_capture_inbuf *)buf_in; + union roce3_dfx_capture_outbuf *outbuf = (union roce3_dfx_capture_outbuf *)buf_out; + roce3_adm_dfx_capture_func_t roce3_adm_dfx_capture_func; + + memset(buf_out, 0, sizeof(union roce3_dfx_capture_outbuf)); + *out_size = sizeof(union roce3_dfx_capture_outbuf); + + if (inbuf->cmd_type >= COMMON_CMD_VM_COMPAT_TEST) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + roce3_adm_dfx_capture_func = g_roce3_adm_dfx_capture_funcs[inbuf->cmd_type]; + if (roce3_adm_dfx_capture_func == NULL) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + return roce3_adm_dfx_capture_func(rdev, inbuf, outbuf); +} + +#endif /* ROCE_PKT_CAP_EN */ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h new file mode 100644 index 000000000..0800ff4b9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx.h + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of macros, data structure, function prototype etc of RoCE driver dfx features. + */ + +#ifndef ROCE_DFX_CAP_H +#define ROCE_DFX_CAP_H + +#include <linux/types.h> + +#include "hinic3_rdma.h" + +#include "roce_sysfs.h" +#include "roce.h" + +#define CAP_PKT_ITEM_SIZE 128 + +#define CAP_NUM_PER_BLOCK 255 + +#define CAP_SKB_LEN 120 + +#define CAP_HDR_OFFSET 4 + +#define FILL_CAP_CFG_PKT_NUM 8192 + +#define CAP_LOOP 255 + +#define CLEAR_MAX_TRY_TIME 10 + +#define CLEAR_SLEEP_TIME 2 + +#define CAP_STOP_SLEEP_TIME 50 + +#define CAP_COUNTER_TWO 2 + +#define CAP_PA_TBL_ENTRY_NUM 255 + +#define CAP_ADDR_COMBIN_SHIFT 32 + +#define CLEAR_CAP_TRYING_TIMES 10 + +#define ROCE_CAP_COUNTER_INDEX 0x39ff + +typedef union roce3_cap_hdr { + struct { + u32 rsvd : 16; + u32 pad : 8; + u32 rsvd0 : 2; + u32 col_num : 4; + u32 tx_rx : 1; + u32 vld : 1; + } cap_ctrl_info; + u32 value; +} roce3_cap_hdr_u; + +typedef struct roce3_dfx_cap_pa_entry { + u32 wr_init_pc_h32; + u32 wr_init_pc_l32; +} roce3_dfx_cap_pa_entry_s; + +typedef struct roce3_dfx_cap_tbl { + roce3_dfx_cap_pa_entry_s pa[2]; +} roce3_dfx_cap_tbl_s; + +typedef struct roce3_dfx_cap_cfg_tbl { + u32 ci_index; + + union { + struct { + /* Driver configurate bit offset by the number of per pa block, for example, 7 means 128, 8 means 256 */ + u8 cap_block_num_shift; + u8 cap_mode; /* Packet Capture mode */ + u8 qp_mode; /* according to qp Packet Capture */ + u8 rsvd; /* reserved */ + } bs; + u32 value; + } dw1; + + union { + struct { + u32 state : 8; /* Packet Capture rate control */ + u32 rsvd : 8; + u32 cap_func : 16; /* Packet Capture function */ + } bs; + u32 value; + } dw2; + + u32 maxnum; +} roce3_dfx_cap_cfg_tbl_s; + +struct roce3_qp_cap_pkt_list { + u32 xid; + struct list_head list; +}; + +struct roce3_cap_block_num_attr { + u32 block_num_idx; + u32 shift; + u32 num; +}; + +struct sdk_thread_info { + struct task_struct *thread_obj; + char *name; + void (*thread_fn)(void *); + void *thread_event; + void *data; +}; + +struct roce3_pkt_cap_info { + struct roce3_device *rdev; + u32 func_id; + u32 poll_ci; + u32 cap_mode; /* 0 : drop mode 1: overwrite mode */ + u32 mode; /* 0 : func mode 1: qp mode */ + u32 cap_status; /* 0 : stopped 1: running */ + u32 block_num_idx; + u32 block_num_per_entry; + u32 maxnum; + struct sdk_thread_info task; + char thread_name[20]; + u64 que_addr[2][2][256]; + struct list_head qp_list_head; /* Based on qp Packet Capture linked list */ + u32 qp_list_cnt; +}; + +#define ROCE_DFX_MAX_CAPTURE_QP_NUM 511 + +struct roce3_qp_cap_pkt { + __be32 xid; +}; + +struct roce3_dfx_capture_inbuf { + u32 cmd_type; + u32 mode; + u32 qpn; +}; + +struct roce3_dfx_capture_info { + u32 cap_status; + u32 cap_mode; + u32 qp_mode; + u32 cap_block_num_shift; + u32 cap_func; + u32 cap_state; + u32 cap_max_num; + u32 cap_pi; + u32 cap_ci; + u32 cap_total; +}; + +struct roce3_dfx_qp_capture_info { + u32 qp_num; + u32 qpn[ROCE_DFX_MAX_CAPTURE_QP_NUM]; +}; + +union roce3_dfx_capture_outbuf { + struct roce3_dfx_capture_info capture_info; + struct roce3_dfx_qp_capture_info qp_capture_info; +}; + +enum roce3_dfx_capture_mode { + ROCE_CAPTURE_MODE_CAP_FUNC = 0, + ROCE_CAPTURE_MODE_CAP_QP, +}; + +enum roce3_dfx_capture_state { + ROCE_CAPTURE_START = 0, + ROCE_CAPTURE_STOP, +}; + +extern int hinic3_set_func_capture_en(void *hwdev, u16 func_id, bool cap_en); + +int roce3_adm_dfx_capture(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +int roce3_dfx_stop_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf); +static DEFINE_MUTEX(cap_mutex); + +#endif /* ROCE_DFX_CAP_H */ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c new file mode 100644 index 000000000..804a3235d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c @@ -0,0 +1,615 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx_query.c + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of callback functions and internal functions of RoCE driver dfx features on qp level. + */ + +#ifdef __ROCE_DFX__ + +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/mutex.h> +#include <linux/kthread.h> + +#include <rdma/ib_verbs.h> +#include "roce_compat.h" +#include "roce.h" +#include "roce_dfx.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_cq.h" +#include "hinic3_hw.h" +#include "roce_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_cqm_cmd.h" + +int roce3_dfx_cmd_query_qp(struct roce3_device *rdev, u32 qpn, struct roce_qp_context *qp_ctx) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_qp_query_s *qp_query_inbuf = NULL; + struct roce3_qp_query_outbuf *qp_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_qp_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_qp_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + qp_query_inbuf = (roce_cmd_qp_query_s *)cqm_cmd_inbuf->buf; + qp_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + qp_query_inbuf->com.index = cpu_to_be32(qpn); + + if ((rdev->cfg_info.lb_en != 0) && (rdev->cfg_info.lb_mode == ROCE_LB_MODE_1)) { + u8 cos = qpn & 0x3; + roce3_dfx_print("lb_mode1 roce3_dfx_cmd_query_qp func_id(%d) qpn:%u cos:%u \n", rdev->glb_func_id, qpn, cos); + ret = cqm_lb_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_QP, cos, cqm_cmd_inbuf, cqm_cmd_outbuf, + NULL, ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + } else { + roce3_dfx_print("Not lb_mode1 roce3_dfx_cmd_query_qp func_id(%d) qpn:%u\n", rdev->glb_func_id, qpn); + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_QP, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + } + + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_QP"); + ret = -1; + goto out; + } + + qp_query_outbuf = (struct roce3_qp_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(qp_ctx, &qp_query_outbuf->qpc, sizeof(struct roce_qp_context)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return ret; +} + +static int roce3_dfx_get_dev_algo(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + u32 cc_algo; + struct roce3_ecn_ctx ecn_ctx; + u32 *algo_type = &outbuf->algo_type; + + if (rdev == NULL) { + pr_err("[ROCE, ERR] %s: Failed to get roce device.\n", __func__); + return -EINVAL; + } + ecn_ctx = rdev->ecn_ctx; + cc_algo = ecn_ctx.cc_algo; + *algo_type = cc_algo; + + return 0; +} + +static int roce3_dfx_get_qp_count(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + struct roce3_dfx_qp_count *qp_count = &outbuf->qp_count; + + qp_count->qp_alloced = rdev->qp_cnt.alloc_qp_cnt; + qp_count->qp_deleted = rdev->qp_cnt.del_qp_cnt; + qp_count->qp_alive = rdev->qp_cnt.alloc_qp_cnt - rdev->qp_cnt.del_qp_cnt; + + return 0; +} + +/* QPC is statically allocated, so it is not necessary to judge whether it exists when querying the cache content */ +static int roce3_dfx_query_cache_qpc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + u32 qpn = inbuf->qpn; + struct roce_qp_context *qp_ctx = &outbuf->qp_ctx; + + memset(qp_ctx, 0, sizeof(struct roce_qp_context)); + ret = roce3_dfx_cmd_query_qp(rdev, qpn, qp_ctx); + if (ret != 0) { + roce3_dfx_print("Failed to query QPC from cache!"); + roce3_dfx_print("******************From Cache: qpn(%#x) ********************", qpn); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY QPC FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: qpn(%#x) ********************", qpn); + + return ret; + } + + return 0; +} + +static int roce3_dfx_query_host_qpc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + cqm_object_s *cqm_obj_qp = NULL; + struct roce3_qp *rqp = NULL; + u32 qpn = inbuf->qpn; + struct roce_qp_context *qp_ctx = &outbuf->qp_ctx; + + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, qpn, false); + if (cqm_obj_qp == NULL) { + roce3_dfx_print("Failed to get cqm_obj_qp."); + roce3_dfx_print("******************From Host: qpn(%#x) ********************", qpn); + roce3_dfx_print(">>>>>>>>>>> QUERY QPC FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: qpn(%#x) ********************", qpn); + + return -EINVAL; + } + + rqp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + + memcpy(qp_ctx, rqp->qpc_info->vaddr, sizeof(struct roce_qp_context)); + + return 0; +} + +int roce3_dfx_cmd_query_cq(struct roce3_device *rdev, u32 cqn, struct roce_cq_context *cq_ctx) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_cq_query_s *cq_query_inbuf = NULL; + struct roce3_cq_query_outbuf *cq_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_cq_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_cq_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + cq_query_inbuf = (roce_cmd_cq_query_s *)cqm_cmd_inbuf->buf; + cq_query_inbuf->com.index = cpu_to_be32(cqn); + cq_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_CQ, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_CQ, ret=%d", ret); + ret = -1; + goto out; + } + + cq_query_outbuf = (struct roce3_cq_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(cq_ctx, &cq_query_outbuf->cqc, sizeof(struct roce_cq_context)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* CQC is dynamic allocation. When querying cache content, you need to determine whether it exists or not. */ +static int roce3_dfx_query_cache_cqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + cqm_object_s *cqm_obj_cq = NULL; + u32 cqn = inbuf->cqn; + struct roce_cq_context *cq_ctx = &outbuf->cq_ctx; + + cqm_obj_cq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SCQ, cqn, false); + if (cqm_obj_cq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_cq."); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + roce3_dfx_print(">>>>>>>>>>> QUERY CQC FROM CACHE FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + + return -EINVAL; + } + + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_cq); + + memset(cq_ctx, 0, sizeof(struct roce_cq_context)); + ret = roce3_dfx_cmd_query_cq(rdev, cqn, cq_ctx); + if (ret != 0) { + roce3_dfx_print("Failed to query cq from cache!"); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY CQC FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + + return -EINVAL; + } + + return 0; +} + +static int roce3_dfx_query_host_cqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + cqm_object_s *cqm_obj_cq = NULL; + struct roce3_cq *rcq = NULL; + u32 cqn = inbuf->cqn; + struct roce_cq_context *cq_ctx = &outbuf->cq_ctx; + + cqm_obj_cq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SCQ, cqn, false); + if (cqm_obj_cq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_cq."); + roce3_dfx_print("******************From Host: cqn(%#x) ********************", cqn); + roce3_dfx_print(">>>>>>>>>>> QUERY CQC FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: cqn(%#x) ********************", cqn); + + return -EINVAL; + } + + rcq = cqmobj_to_roce3_cq(cqm_obj_cq); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_cq); + + memcpy(cq_ctx, rcq->cqm_cq->q_ctx_vaddr, sizeof(struct roce_cq_context)); + + return 0; +} + +int roce3_dfx_cmd_query_srq(struct roce3_device *rdev, u32 srqn, struct roce_srq_context *srq_ctx) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_srq_query_s *srq_query_inbuf = NULL; + struct roce3_srq_query_outbuf *srq_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_srq_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_srq_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + srq_query_inbuf = (roce_cmd_srq_query_s *)cqm_cmd_inbuf->buf; + srq_query_inbuf->com.index = cpu_to_be32(srqn); + srq_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_SRQ_BITMASK); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_SRQ, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_SRQ, ret=%d", ret); + ret = -1; + goto out; + } + + srq_query_outbuf = (struct roce3_srq_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(srq_ctx, srq_query_outbuf, + sizeof(struct roce3_srq_query_outbuf)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* SRQC is dynamic allocation. When querying the cache content, you need to determine whether it exists or not. */ +static int roce3_dfx_query_cache_srqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + cqm_object_s *cqm_obj_srq = NULL; + u32 srqn = inbuf->srqn; + struct roce_srq_context *srq_ctx = &outbuf->srq_ctx; + + cqm_obj_srq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srqn, false); + if (cqm_obj_srq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_srq"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + roce3_dfx_print(">>>>>>>>>>> QUERY CQC FROM CACHE FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + + return -EINVAL; + } + + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_srq); + + memset(srq_ctx, 0, sizeof(struct roce_srq_context)); + ret = roce3_dfx_cmd_query_srq(rdev, srqn, srq_ctx); + if (ret != 0) { + roce3_dfx_print("Failed to query srq from cache"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY SRQC FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + + return -EINVAL; + } + + return 0; +} + +static int roce3_dfx_query_host_srqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + cqm_object_s *cqm_obj_srq = NULL; + struct roce3_srq *rsrq = NULL; + u32 srqn = inbuf->srqn; + struct roce_srq_context *srq_ctx = &outbuf->srq_ctx; + + cqm_obj_srq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srqn, false); + if (cqm_obj_srq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_srq."); + roce3_dfx_print("******************From Host: srqn(%#x) ********************", srqn); + roce3_dfx_print(">>>>>>>>>>> QUERY SRQC FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: srqn(%#x) ********************", srqn); + + return -EINVAL; + } + + rsrq = cqmobj_to_roce3_srq(cqm_obj_srq); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_srq); + + memcpy(srq_ctx, rsrq->cqm_srq->q_ctx_vaddr, sizeof(struct roce_srq_context)); + + return 0; +} + +static int roce3_dfx_cmd_query_mpt(struct roce3_device *rdev, u32 key, struct roce_mpt_context *mpt_entry) +{ + int ret; + u32 mpt_index; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_mpt_query_s *mpt_query_inbuf = NULL; + struct roce3_mpt_query_outbuf *mpt_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_mpt_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_mpt_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + mpt_query_inbuf = (roce_cmd_mpt_query_s *)cqm_cmd_inbuf->buf; + mpt_index = (key >> MR_KEY_2_INDEX_SHIFT) & 0xFFFFFF; + mpt_query_inbuf->com.index = cpu_to_be32(mpt_index); + mpt_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_MPT, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_MPT"); + ret = -1; + goto out; + } + + mpt_query_outbuf = (struct roce3_mpt_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(mpt_entry, &mpt_query_outbuf->mpt_entry, + sizeof(struct roce_mpt_context)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return ret; +} + +static int roce3_dfx_cmd_query_gid(struct roce3_device *rdev, u32 port, u32 gid_index, struct rdma_gid_entry *gid_entry) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_query_gid_s *gid_query_inbuf = NULL; + struct rdma_gid_query_outbuf *gid_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_query_gid_s), &cqm_cmd_outbuf, + (u16)sizeof(struct rdma_gid_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + gid_query_inbuf = (roce_cmd_query_gid_s *)cqm_cmd_inbuf->buf; + gid_query_inbuf->port = cpu_to_be32(port); + gid_query_inbuf->com.index = cpu_to_be32(gid_index); + gid_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_GID_BITMASK); + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_GID, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_GID"); + ret = -1; + goto out; + } + + gid_query_outbuf = (struct rdma_gid_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(gid_entry, &gid_query_outbuf->gid_entry, sizeof(struct rdma_gid_entry)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* MPT is statically allocated, so it is not necessary to judge whether it exists when querying the cache content */ +static int roce3_dfx_query_cache_mpt(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + u32 mpt_key = inbuf->mpt_key; + struct roce_mpt_context *mpt_entry = &outbuf->mpt; + + memset(mpt_entry, 0, sizeof(struct roce_mpt_context)); + ret = roce3_dfx_cmd_query_mpt(rdev, mpt_key, mpt_entry); + if (ret != 0) { + roce3_dfx_print("Failed to query mpt from cache!"); + roce3_dfx_print("******************From Cache: mpt_key(%#x) ********************", mpt_key); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY MPT FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: mpt_key(%#x) ********************", mpt_key); + + return ret; + } + + return 0; +} + +static int roce3_dfx_query_host_mpt(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + u32 mpt_index = 0; + cqm_object_s *cqm_obj_mpt = NULL; + cqm_qpc_mpt_s *cqm_mpt = NULL; + struct rdma_mpt *rmpt = NULL; + u32 mpt_key = inbuf->mpt_key; + struct roce_mpt_context *mpt_entry = &outbuf->mpt; + + mpt_index = (mpt_key >> MR_KEY_2_INDEX_SHIFT) & 0xFFFFFF; + cqm_obj_mpt = cqm_object_get(rdev->hwdev, CQM_OBJECT_MPT, mpt_index, false); + if (cqm_obj_mpt == NULL) { + roce3_dfx_print("Failed to get cqm_obj_mpt."); + roce3_dfx_print("******************From Host: mpt_key(%#x) ********************", mpt_key); + roce3_dfx_print(">>>>>>>>>>> QUERY MPT FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: mpt_key(%#x) ********************", mpt_key); + + return -EINVAL; + } + + cqm_mpt = container_of(cqm_obj_mpt, cqm_qpc_mpt_s, object); + rmpt = (struct rdma_mpt *)cqm_mpt->priv; + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_mpt); + + memcpy(mpt_entry, rmpt->vaddr, sizeof(struct roce_mpt_context)); + + return 0; +} + +static int roce3_dfx_query_cache_gid(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + u32 gid_index = inbuf->gid_index; + struct rdma_gid_entry *gid_entry = &outbuf->gid_entry; + + memset(gid_entry, 0, sizeof(struct rdma_gid_entry)); + ret = roce3_dfx_cmd_query_gid(rdev, 0, gid_index, gid_entry); + if (ret != 0) { + roce3_dfx_print("***************port(1), gid_index(%d) *****************", gid_index); + roce3_dfx_print("Failed to query gid from cache!"); + roce3_dfx_print("***************port(1), gid_index(%d) *****************", gid_index); + + return -EINVAL; + } + + return 0; +} + +static void roce3_dfx_query_pi_ci_b32_to_cpu(struct roce_qp_context *qp_ctx) +{ + qp_ctx->chip_seg.sqc.dw0.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw0.value); + qp_ctx->chip_seg.sqc.dw2.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw2.value); + qp_ctx->chip_seg.sqc.dw3.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw3.value); + qp_ctx->chip_seg.sqc.dw7.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw7.value); + qp_ctx->chip_seg.sqc.dw14.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw14.value); + qp_ctx->chip_seg.rqc.dw0.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw0.value); + qp_ctx->chip_seg.rqc.dw3.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw3.value); + qp_ctx->chip_seg.rqc.dw7.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw7.value); + qp_ctx->chip_seg.rqc.dw14.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw14.value); + qp_ctx->chip_seg.sqac.dw3.value = be32_to_cpu(qp_ctx->chip_seg.sqac.dw3.value); + qp_ctx->chip_seg.sqac.dw7.value = be32_to_cpu(qp_ctx->chip_seg.sqac.dw7.value); + qp_ctx->chip_seg.rcc.dw5.value = be32_to_cpu(qp_ctx->chip_seg.rcc.dw5.value); + qp_ctx->chip_seg.rcc.dw6.value = be32_to_cpu(qp_ctx->chip_seg.rcc.dw6.value); + qp_ctx->chip_seg.rcc.dw7.value = be32_to_cpu(qp_ctx->chip_seg.rcc.dw7.value); + qp_ctx->chip_seg.qpcc.dw4.value = be32_to_cpu(qp_ctx->chip_seg.qpcc.dw4.value); +} + +static void roce3_dfx_query_pi_ci_set(struct roce_qp_context qp_ctx, struct roce3_dfx_pi_ci *pi_ci) +{ + pi_ci->qpc_sq_pi_on_chip = qp_ctx.chip_seg.sqc.dw0.bs.sq_pi_on_chip; + pi_ci->qpc_sq_pi = qp_ctx.chip_seg.sqc.dw2.bs.sq_pi; + pi_ci->qpc_sq_load_pi = qp_ctx.chip_seg.sqc.dw3.bs.sq_load_pi; + pi_ci->qpc_rq_pi_on_chip = qp_ctx.chip_seg.rqc.dw0.bs.rq_pi_on_chip; + pi_ci->qpc_rq_load_pi = qp_ctx.chip_seg.rqc.dw3.bs.rq_load_pi; + pi_ci->qpc_rq_pi = qp_ctx.chip_seg.rqc.dw7.bs.rq_pi; + pi_ci->qpc_rc_pi = qp_ctx.chip_seg.rcc.dw5.bs.rc_pi; + pi_ci->qpc_sq_ci = qp_ctx.chip_seg.sqc.dw3.bs.sq_ci; + pi_ci->qpc_sq_wqe_prefetch_ci = qp_ctx.chip_seg.sqc.dw7.bs.sq_wqe_prefetch_ci; + pi_ci->qpc_sq_mtt_prefetch_wqe_ci = qp_ctx.chip_seg.sqc.dw14.bs.sq_mtt_prefetch_wqe_ci; + pi_ci->qpc_sqa_ci = qp_ctx.chip_seg.sqac.dw3.bs.sqa_ci; + pi_ci->qpc_sqa_wqe_prefetch_ci = qp_ctx.chip_seg.sqac.dw7.bs.sqa_wqe_prefetch_ci; + pi_ci->qpc_rq_ci = qp_ctx.chip_seg.rqc.dw3.bs.rq_ci; + pi_ci->qpc_rq_wqe_prefetch_ci = qp_ctx.chip_seg.rqc.dw7.bs.rq_wqe_prefetch_ci; + pi_ci->qpc_rq_mtt_prefetch_wqe_ci = qp_ctx.chip_seg.rqc.dw14.bs.rq_mtt_prefetch_wqe_ci; + pi_ci->qpc_rq_base_ci = qp_ctx.chip_seg.qpcc.dw4.bs.rq_base_ci; + pi_ci->qpc_rc_ci = qp_ctx.chip_seg.rcc.dw6.bs.rc_ci; + pi_ci->qpc_rc_prefetch_ci = qp_ctx.chip_seg.rcc.dw7.bs.rc_prefetch_ci; +} + +static int roce3_dfx_query_pi_ci(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + struct roce_qp_context qp_ctx; + struct roce_cq_context cq_ctx; + u32 qpn = inbuf->query_pi_ci.qpn; + u32 cqn = inbuf->query_pi_ci.cqn; + struct roce3_dfx_pi_ci *pi_ci = &outbuf->pi_ci; + + memset(pi_ci, 0, sizeof(struct roce3_dfx_pi_ci)); + + memset(&qp_ctx, 0, sizeof(qp_ctx)); + ret = roce3_dfx_cmd_query_qp(rdev, qpn, &qp_ctx); + if (ret != 0) { + return ret; + } + + roce3_dfx_query_pi_ci_b32_to_cpu(&qp_ctx); + roce3_dfx_query_pi_ci_set(qp_ctx, pi_ci); + + memset(&cq_ctx, 0, sizeof(cq_ctx)); + ret = roce3_dfx_cmd_query_cq(rdev, cqn, &cq_ctx); + if (ret != 0) { + return ret; + } + + cq_ctx.dw0.value = be32_to_cpu(cq_ctx.dw0.value); + cq_ctx.dw1.value = be32_to_cpu(cq_ctx.dw1.value); + cq_ctx.dw2.value = be32_to_cpu(cq_ctx.dw2.value); + cq_ctx.dw3.value = be32_to_cpu(cq_ctx.dw3.value); + cq_ctx.dw9.value = be32_to_cpu(cq_ctx.dw9.value); + cq_ctx.ci_record_gpa_at_hop_num = be32_to_cpu(cq_ctx.ci_record_gpa_at_hop_num); + + pi_ci->cq_ci_on_chip = cq_ctx.dw0.bs.ci_on_chip; + pi_ci->cq_ci = cq_ctx.dw1.bs.ci; + pi_ci->cq_load_ci = cq_ctx.dw3.bs.load_ci; + pi_ci->cq_ci_record_gpa_at_hop_num = cq_ctx.ci_record_gpa_at_hop_num; + pi_ci->cq_last_solicited_pi = cq_ctx.dw0.bs.last_solicited_pi; + pi_ci->cq_pi = cq_ctx.dw2.bs.pi; + pi_ci->cq_last_notified_pi = cq_ctx.dw9.bs.last_notified_pi; + + return 0; +} + +typedef int (*roce3_adm_dfx_query_t)(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf); + +static roce3_adm_dfx_query_t roce3_adm_dfx_query_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [ROCE_CMD_GET_QPC_FROM_CACHE] = roce3_dfx_query_cache_qpc, + [ROCE_CMD_GET_QPC_FROM_HOST] = roce3_dfx_query_host_qpc, + [ROCE_CMD_GET_CQC_FROM_CACHE] = roce3_dfx_query_cache_cqc, + [ROCE_CMD_GET_CQC_FROM_HOST] = roce3_dfx_query_host_cqc, + [ROCE_CMD_GET_SRQC_FROM_CACHE] = roce3_dfx_query_cache_srqc, + [ROCE_CMD_GET_SRQC_FROM_HOST] = roce3_dfx_query_host_srqc, + [ROCE_CMD_GET_MPT_FROM_CACHE] = roce3_dfx_query_cache_mpt, + [ROCE_CMD_GET_MPT_FROM_HOST] = roce3_dfx_query_host_mpt, + [ROCE_CMD_GET_GID_FROM_CACHE] = roce3_dfx_query_cache_gid, + [ROCE_CMD_GET_QPC_CQC_PI_CI] = roce3_dfx_query_pi_ci, + [ROCE_CMD_GET_QP_COUNT] = roce3_dfx_get_qp_count, + [ROCE_CMD_GET_DEV_ALGO] = roce3_dfx_get_dev_algo, +}; + +int roce3_adm_dfx_query(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + const struct roce3_dfx_query_inbuf *inbuf = (struct roce3_dfx_query_inbuf *)buf_in; + union roce3_dfx_query_outbuf *outbuf = (union roce3_dfx_query_outbuf *)buf_out; + roce3_adm_dfx_query_t roce3_adm_dfx_query_func; + + memset(buf_out, 0, sizeof(union roce3_dfx_query_outbuf)); + *out_size = (u32)sizeof(union roce3_dfx_query_outbuf); + + if (inbuf->cmd_type >= COMMON_CMD_VM_COMPAT_TEST) { + roce3_dfx_print("Not support this type(%d)", inbuf->cmd_type); + return -EINVAL; + } + + roce3_adm_dfx_query_func = roce3_adm_dfx_query_funcs[inbuf->cmd_type]; + if (roce3_adm_dfx_query_func == NULL) { + roce3_dfx_print("Not support this type(%d)", inbuf->cmd_type); + return -EINVAL; + } + + return roce3_adm_dfx_query_func(inbuf, rdev, outbuf); +} + +#endif diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c new file mode 100644 index 000000000..d56e35bab --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cdev_extension.c + * Version : v2.0 + * Created : 2021/7/1 + * Last Modified : 2022/7/1 + * Description : The definition of RoCE Async Event realated functions in kernel space. + */ +#ifndef PANGEA_NOF + +#include "roce_cdev_extension.h" + +long ioctl_non_bonding_extend(unsigned int cmd, struct roce3_device *rdev, unsigned long arg) +{ + return NOT_SUPOORT_TYPE; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c new file mode 100644 index 000000000..803d059dd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_event_extension.c + * Version : v1.0 + * Created : 2022/1/27 + * Last Modified : 2022/1/27 + * Description : The definition of RoCE async event module standard callback functions. + */ + +#include "roce_event_extension.h" + +#ifndef PANGEA_NOF +void roce3_event_report_extend(const struct roce3_device *rdev, int event_str_index) +{ + /*lint -e160 -e522*/ + roce3_pr_err_once("[ROCE] %s: [non ofed event type] Invalid extend event type error. function id: %u\n", __func__, + rdev->glb_func_id); + /*lint +e160 +e522*/ +} + +int roce3_async_event_handle_extend(u8 event_type, u8 *val, struct roce3_device *rdev) +{ + int event_str_index = 0; + + event_str_index = to_unkown_event_str_index(event_type, val); + + return event_str_index; +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c new file mode 100644 index 000000000..9b6649ee4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_main_extension.c + * Version : v1.0 + * Created : 2021/10/18 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE MAIN extended functions. + */ + +#include "roce_main_extension.h" + +#ifndef PANGEA_NOF + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" + +static struct mutex g_rdev_mutex; +#endif + +void roce3_service_init_pre(void) +{ +#ifdef ROCE_BONDING_EN + mutex_init(&g_rdev_mutex); +#endif + + return; +} + +void roce3_service_init_ext(void) +{ + return; +} + +void roce3_lock_rdev(void) +{ +#ifdef ROCE_BONDING_EN + mutex_lock(&g_rdev_mutex); +#endif +} + +void roce3_unlock_rdev(void) +{ +#ifdef ROCE_BONDING_EN + mutex_unlock(&g_rdev_mutex); +#endif +} + +int roce3_get_rdev_by_uld(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev, + struct hinic3_event_info *event) +{ +#ifdef ROCE_BONDING_EN + int ret; + + ret = roce3_bond_event_cfg_rdev(lld_dev, uld_dev, rdev); + if (ret != 0) { + pr_err("[ROCE] %s: Cfg bond rdev failed(%d)\n", __func__, ret); + return ret; + } + ret = roce3_bonded_port_event_report(*rdev, event); + if (ret != 0) { + pr_err("[ROCE] %s: Report bond event failed(%d)\n", __func__, ret); + return ret; + } +#else + if ((lld_dev == NULL) || (uld_dev == NULL)) { + pr_err("[ROCE] %s: Input params is null\n", __func__); + return -ENODEV; + } + *rdev = (struct roce3_device *)uld_dev; +#endif + return 0; +} +#endif /* !PANGEA_NOF */ + +#ifdef ROCE_STANDARD +void roce3_init_dev_ext_handlers(struct roce3_device *rdev) +{ + return; +} +#endif /* ROCE_STANDARD */ + +#ifndef PANGEA_NOF +void roce3_remove_clean_res_ext(struct roce3_device *rdev) +{ +#ifdef __ROCE_DFX__ + roce3_dfx_clean_up(rdev); +#endif +} +#endif /* PANGEA_NOF */ + +#ifndef PANGEA_NOF +int roce3_board_cfg_check(struct roce3_device *rdev) +{ + int ret = 0; + int port_num = 0; + int port_speed = 0; + + port_num = rdev->board_info.port_num; + port_speed = rdev->board_info.port_speed; + if ((port_num == ROCE3_2_PORT_NUM) && (port_speed == ROCE3_100G_PORT_SPEED)) { + rdev->hw_info.hca_type = ROCE3_2_100G_HCA; + } else if ((port_num == ROCE3_4_PORT_NUM) && (port_speed == ROCE3_25G_PORT_SPEED)) { + rdev->hw_info.hca_type = ROCE3_4_25G_HCA; + } else if ((port_num == ROCE3_2_PORT_NUM) && (port_speed == ROCE3_25G_PORT_SPEED)) { + rdev->hw_info.hca_type = ROCE3_2_25G_HCA; + } else { + pr_err("[ROCE] %s: Invalid fw cfg\n", __func__); + ret = (-EINVAL); + } + + return ret; +} + +int roce3_mmap_ext(struct roce3_device *rdev, struct roce3_ucontext *ucontext, struct vm_area_struct *vma) +{ + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Not support, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; +} + +int roce3_dfx_mem_alloc(struct roce3_device *rdev) +{ + return 0; +} + +void roce3_dfx_mem_free(struct roce3_device *rdev) +{ + return; +} + +void *roce3_ucontext_alloc_ext(void) +{ + return kzalloc(sizeof(struct roce3_ucontext), GFP_KERNEL); +} + +void *roce3_resp_alloc_ext(void) +{ + return kzalloc(sizeof(struct roce3_alloc_ucontext_resp), GFP_KERNEL); +} + +void roce3_resp_set_ext(struct roce3_device *rdev, struct roce3_alloc_ucontext_resp *resp) +{ + return; +} + +void roce3_ucontext_set_ext(struct roce3_device *rdev, struct roce3_ucontext *context) +{ + return; +} + +void *roce3_rdev_alloc_ext(void) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) \ + || defined(OFED_MLNX_5_8) + return (void *)ib_alloc_device(roce3_device, ib_dev); +#else + return (void *)ib_alloc_device(sizeof(struct roce3_device)); +#endif +} + +void roce3_rdev_set_ext(struct roce3_device *rdev) +{ + return; +} + +int ib_copy_to_udata_ext(struct ib_udata *udata, struct roce3_alloc_ucontext_resp *resp) +{ + return ib_copy_to_udata(udata, resp, sizeof(struct roce3_alloc_ucontext_resp)); +} + +int roce3_set_comm_event(const struct roce3_device *rdev, const struct hinic3_event_info *event) +{ + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Comm event unsupported, func_id(%d), event(%d)\n", __func__, + rdev->glb_func_id, event->type); + return -1; +} + +bool roce3_hca_is_present(const struct roce3_device *rdev) +{ + return true; +} +#endif /* PANGEA_NOF */ + +#if !defined(NOF_AA) +int roce3_init_dev_ext(struct roce3_device *rdev) +{ + return 0; +} + +#if defined(EULER_2_10_OFED_4_19) || defined(KY10_OFED_4_19) +void roce3_rdma_cap_ext(struct rdma_service_cap *rdma_cap) +{ + rdma_cap->max_sq_desc_sz = RDMA_MAX_SQ_DESC_SZ_COMPUTE; + rdma_cap->dev_rdma_cap.roce_own_cap.max_wqes = ROCE_MAX_WQES_COMPUTE; + rdma_cap->dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz = ROCE_MAX_SQ_INLINE_DATA_SZ_COMPUTE; + + return; +} +#else +void roce3_rdma_cap_ext(struct rdma_service_cap *rdma_cap) +{ + return; +} +#endif + +#endif diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c new file mode 100644 index 000000000..d176e9033 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mr_standard.c + * Version : v1.1 + * Created : 2021/7/14 + * Last Modified : 2021/11/24 + * Description : The definition of RoCE MR module standard callback functions. + */ +#include "roce_mr.h" +#include "roce_main_extension.h" +#include "roce_mr_extension.h" + +#ifdef ROCE_STANDARD +int roce3_check_alloc_mr_type(enum ib_mr_type mr_type) +{ + int ret = 0; + + if (mr_type != IB_MR_TYPE_MEM_REG) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: mr_type is invalid. mr_type:%u\n", __func__, mr_type); + } + + return ret; +} + +enum rdma_mr_type roce3_get_mrtype(enum ib_mr_type ib_mr_type) +{ + switch (ib_mr_type) { + case IB_MR_TYPE_MEM_REG: + return RDMA_DMA_MR; + + default: + return RDMA_DMA_MR; + } +} +#endif + diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c new file mode 100644 index 000000000..fa700f226 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_netdev_extension.c + * Version : v1.1 + * Created : 2021/10/18 + * Last Modified : 2022/1/26 + * Description : The definition of RoCE net devices realated extended functions. + */ + +#include "roce_netdev_extension.h" +#include "roce_mpu_common.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#ifdef ROCE_VROCE_EN +static int roce3_get_vni_by_func_id(void *hwdev, u16 func_id, u32 *vni) +{ + int ret; + vroce_mac_cfg_vni_info_s mac_vni_info; + u16 out_size = (u16)sizeof(vroce_mac_cfg_vni_info_s); + + if (!hwdev || !vni) { + pr_err("[ROCE, ERR] %s: null pointer hwdev %p vni %p\n", __func__, hwdev, vni); + return -EINVAL; + } + + memset(&mac_vni_info, 0, sizeof(mac_vni_info)); + + mac_vni_info.func_id = func_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_GET_MAC_VNI, &mac_vni_info, sizeof(mac_vni_info), &mac_vni_info, + &out_size); + if ((ret != 0) || (out_size == 0) || (mac_vni_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to get mac vni, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + mac_vni_info.head.status, out_size); + return -EINVAL; + } + + *vni = (mac_vni_info.vni_en) ? mac_vni_info.vlan_vni : 0; + + return ret; +} +#endif + +#ifndef PANGEA_NOF +int roce3_add_real_device_mac(struct roce3_device *rdev, struct net_device *netdev) +{ + int ret; + u32 vlan_id = 0; + +#ifndef ROCE_VROCE_EN + /* no need to configure IPSURX vf table for vroce here, this action has been done in vroce driver */ + roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); +#else + /* vroce uses vni to filt invalid packets */ + ret = roce3_get_vni_by_func_id(rdev->hwdev, rdev->glb_func_id, &vlan_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: get roce3_get_vni_by_func_id failed, vlan_id(0x%x) ret(%d)\n", __func__, vlan_id, ret); + } + + ret = + roce3_add_mac_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, rdev->glb_func_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to add mac_vlan entry, ret(%d)\n", __func__, ret); + return ret; + } +#endif + +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + ret = roce3_add_bond_real_slave_mac(rdev, (u8 *)netdev->dev_addr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to add bond read device ipsu mac, func_id(%d)\n", __func__, + rdev->glb_func_id); + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, 0, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + return ret; + } + } +#endif + + memcpy(rdev->mac, netdev->dev_addr, sizeof(rdev->mac)); + + return 0; +} + +int roce3_add_vlan_device_mac(struct roce3_device *rdev, struct net_device *netdev) +{ + int ret = 0; + u32 vlan_id = 0; + + vlan_id = ROCE_GID_SET_VLAN_32BIT_VLAID(((u32)rdma_vlan_dev_vlan_id(netdev))); + dev_info(rdev->hwdev_hdl, "[ROCE] %s: enter roce3_add_vlan_device_mac, vlan_id(0x%x), func_id(%d)\n", __func__, + vlan_id, rdev->glb_func_id); + ret = + roce3_add_mac_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, rdev->glb_func_id); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set vlan device mac, vlan_id(0x%x), func_id(%d)\n", + __func__, vlan_id, rdev->glb_func_id); + return ret; + } + + roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + ret = roce3_add_bond_vlan_slave_mac(rdev, (u8 *)netdev->dev_addr, (u16)vlan_id); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set bond vlan slave mac, vlan_id(0x%x), func_id(%d)\n", + __func__, vlan_id, rdev->glb_func_id); + goto err_add_bond_vlan_slave_mac; + } + } +#endif + + return ret; + +#ifdef ROCE_BONDING_EN +err_add_bond_vlan_slave_mac: + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + + (void)hinic3_del_mac(rdev->hwdev, (u8 *)netdev->dev_addr, (u16)vlan_id, rdev->glb_func_id, HINIC3_CHANNEL_ROCE); + + return ret; +#endif +} + +void roce3_del_real_device_mac(struct roce3_device *rdev) +{ + u32 vlan_id = 0; +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + roce3_del_bond_real_slave_mac(rdev); + } +#endif + +#ifndef ROCE_VROCE_EN + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, rdev->mac, vlan_id, rdev->glb_func_id, hinic3_er_id(rdev->hwdev)); +#else + /* vroce uses vni to filt invalid packets */ + (void)roce3_get_vni_by_func_id(rdev->hwdev, rdev->glb_func_id, &vlan_id); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, rdev->mac, vlan_id, rdev->glb_func_id, rdev->glb_func_id); +#endif +} + +void roce3_del_vlan_device_mac(struct roce3_device *rdev, struct roce3_vlan_dev_list *old_list) +{ +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + roce3_del_bond_vlan_slave_mac(rdev, old_list->mac, (u16)old_list->vlan_id); + } +#endif + + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, old_list->mac, old_list->vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, old_list->mac, old_list->vlan_id, rdev->glb_func_id, + rdev->glb_func_id); +} + +void roce3_event_up_extend(struct roce3_device *rdev) +{ + if (test_and_set_bit(ROCE3_PORT_EVENT, &rdev->status) == 0) { + roce3_ifconfig_up_down_event_report(rdev, IB_EVENT_PORT_ACTIVE); + } +} + +#endif /* PANGEA_NOF */ diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c new file mode 100755 index 000000000..a101f7dcd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_extension.c + * Version : v1.1 + * Created : 2021/12/18 + * Last Modified : 2021/12/18 + * Description : Define standard kernel QP realted function prototype. + */ + +#include "roce_qp_extension.h" +#include "cfg_mgmt_mpu_cmd_defs.h" + +#ifdef ROCE_EXTEND +#include "roce_ctx_api.h" +#include "roce_pd.h" +#endif + +int to_roce3_qp_type(enum ib_qp_type qp_type) +{ + switch (qp_type) { + case IB_QPT_RC: + return ROCE_QP_ST_RC; + + case IB_QPT_UC: + return ROCE_QP_ST_UC; + + case IB_QPT_UD: + return ROCE_QP_ST_UD; + + case IB_QPT_XRC_INI: + case IB_QPT_XRC_TGT: + return ROCE_QP_ST_XRC; + + case IB_QPT_GSI: + return ROCE_QP_ST_UD; + + default: + return -1; + } +} + +bool roce3_check_qp_modify_ok(enum ib_qp_state cur_state, enum ib_qp_state next_state, enum ib_qp_type type, + enum ib_qp_attr_mask mask, enum rdma_link_layer ll) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) \ + || defined(OFED_MLNX_5_8) + return ib_modify_qp_is_ok(cur_state, next_state, type, mask); +#else + return ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll); +#endif +} + +#ifndef PANGEA_NOF +int roce3_create_qp_pre_ext(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr) +{ + return 0; +} + +int roce3_create_qp_user_pre_ext(struct ib_qp_init_attr *init_attr, struct roce3_qp *rqp, u32 *qpn) +{ + *qpn = ROCE_QP_INVLID_QP_NUM; + + return 0; +} + +int roce3_create_qp_user_post_ext(struct ib_pd *ibpd, struct roce3_device *rdev, struct roce3_qp *rqp, + struct ib_qp_init_attr *init_attr) +{ + return 0; +} + +int roce3_qp_modify_cmd_ext(cqm_cmd_buf_s *cqm_cmd_inbuf, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr, + u32 optpar) +{ + return 0; +} + +bool roce3_need_qpn_lb1_consistent_srqn(const struct roce3_qp *rqp, const struct roce3_device *rdev, + const struct ib_qp_init_attr *init_attr) +{ + if (init_attr->srq == NULL) { + return false; + } + + if ((rdev->cfg_info.scence_id == SCENES_ID_CLOUD) || + (rdev->cfg_info.scence_id == SCENES_ID_COMPUTE_ROCE) || + (rdev->cfg_info.scence_id == SCENES_ID_COMPUTE_STANDARD)) { + return true; + } + + return false; +} + +int roce3_is_qp_normal(struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr) +{ + return 1; +} + +#ifdef ROCE_EXTEND +static struct roce3_qp *roce3_cdev_lookup_and_check_rqp(struct roce3_device *rdev, u32 qpn) +{ + cqm_object_s *cqm_obj_qp = NULL; + struct roce3_qp *rqp = NULL; + + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, qpn, false); + if (cqm_obj_qp == NULL) { + pr_err("[ROCE, ERR] %s: Can't find rqp according to qpn(0x%x), func_id(%d)\n", __func__, qpn, + rdev->glb_func_id); + return NULL; + } + + rqp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + + if (rqp->qpn >= QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: qpn[%u] more than sqpc num offset(%d) for sqpc.\n", __func__, + rqp->qpn, QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC); + return NULL; + } + + return rqp; +} + +static int roce3_alloc_sqpc(struct roce3_device *rdev, struct roce3_qp *rqp, struct roce3_vbs_qp *vbs_rqp) +{ + cqm_qpc_mpt_s *qpc_info = NULL; + + /* Call the CQM interface to allocate QPNs and QPCs */ + /* For SQPC, do not need to allocate QPN, QPN is directly spcified in rsvd segment */ + qpc_info = cqm_object_qpc_mpt_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_SERVICE_CTX, + rdev->rdma_cap.dev_rdma_cap.roce_own_cap.qpc_entry_sz, NULL, rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC, + false); + if (qpc_info == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to create qpc by cqm object, func_id(%d), qpn(%u)\n", + __func__, rdev->glb_func_id, rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC); + return -ENOMEM; + } + + if (qpc_info->xid != (rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC)) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Create qpc error, func_id(%d), expect qpn(%d), actual qpn(%d)\n", + __func__, rdev->glb_func_id, rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC, qpc_info->xid); + hiudk_cqm_object_delete(rdev->hwdev, &(qpc_info->object)); + return -EFAULT; + } + + vbs_rqp->vbs_sqpc_info = qpc_info; + rqp->vbs_qp_ptr = (void *)vbs_rqp; + + return 0; +} + +long roce3_set_qp_ext_attr(struct roce3_device *rdev, void *buf) +{ + int ret; + struct roce3_qp *rqp = NULL; + struct roce3_set_qp_ext_attr_cmd cmd; + struct roce_qp_context *context = NULL; + + ret = (int)copy_from_user(&cmd, buf, sizeof(cmd)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return (long)ret; + } + + rqp = roce3_cdev_lookup_and_check_rqp(rdev, cmd.qpn); + if (rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return -EINVAL; + } + + context = (struct roce_qp_context *)((void *)rqp->qpc_info->vaddr); + if (((cmd.attr_mask) & ROCE_QP_VBS_FLAG) != 0) { /* IBV_QP_VBS_OSD_FLAG */ + context->sw_seg.ucode_seg.common.dw0.bs.ulp_type = ROCE_ULP_VBS; + } + + return (long)ret; +} + +long roce3_vbs_create_sqpc(struct roce3_device *rdev, void *buf) +{ + struct roce3_modify_qp_vbs_cmd cmd; + struct roce3_vbs_qp *vbs_rqp = NULL; + struct roce3_qp *rqp = NULL; + struct roce3_pd *pd = NULL; + int ret; + + ret = (int)copy_from_user(&cmd, buf, sizeof(cmd)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return (long)ret; + } + + rqp = roce3_cdev_lookup_and_check_rqp(rdev, cmd.qpn); + if (rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return -EINVAL; + } + + vbs_rqp = (struct roce3_vbs_qp *)kzalloc(sizeof(*vbs_rqp), GFP_KERNEL); + if (vbs_rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to alloc vbs_rqp, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + pd = roce3_get_pd(rqp); + ret = roce3_db_map_user(to_roce3_ucontext(pd->ibpd.uobject->context), cmd.ci_record_addr, &vbs_rqp->db); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to map db page to user, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto free_rqp; + } + + ret = roce3_alloc_sqpc(rdev, rqp, vbs_rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to alloc sqpc, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto free_rqp; + } + + return 0; + +free_rqp: + kfree(vbs_rqp); + + return (long)ret; +} +#endif + +#endif /* !PANGEA_NOF */ + +#ifndef ROCE_CHIP_TEST +void roce3_set_qp_dif_attr(struct roce3_qp *rqp, const struct ib_qp_init_attr *init_attr, + const struct roce3_device *rdev) +{ + if (((unsigned int)init_attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) != 0) { + rqp->signature_en = true; + dev_info(rdev->hwdev_hdl, "[ROCE] %s: func(%d) qp(%u) roce3_create_qp signature_en.\n", __func__, + rdev->glb_func_id, rqp->qpn); + } + return; +} +#endif + +#ifndef ROCE_VBS_EN +int roce3_qp_modify_pre_extend(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata) +{ + return 0; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c new file mode 100644 index 000000000..14005a04d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_post_send_standard.c + * Version : v1.2 + * Created : 2021/8/20 + * Last Modified : 2021/11/23 + * Description : Define standard kernel post_send realted function prototype. + */ + +#include "roce_qp_post_send_extension.h" +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +#else +int roce3_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, struct ib_send_wr **bad_wr) +#endif +{ + return roce3_post_send_standard(ibqp, (const struct ib_send_wr *)wr, (const struct ib_send_wr **)bad_wr); +} diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c new file mode 100644 index 000000000..a9736d10e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq_extension.c + * Version : v1.0 + * Created : 2021/12/7 + * Last Modified : 2021/12/24 + * Description : The definition of RoCE SRQ module standard callback functions. + */ + +#include "roce_srq_extension.h" + +#ifndef ROCE_CHIP_TEST +void roce3_srq_container_init(struct ib_srq_init_attr *init_attr, struct roce3_srq *rsrq, struct roce3_device *rdev) +{ + rsrq->xrc_en = (init_attr->srq_type == IB_SRQT_XRC); + + if (rsrq->xrc_en != 0) { + rsrq->container_flag = rdev->cfg_info.srq_container_en; + } + + rsrq->container_mode = + (rsrq->xrc_en != 0) ? rdev->cfg_info.xrc_srq_container_mode : rdev->cfg_info.srq_container_mode; + rsrq->container_warn_th = roce3_calculate_cont_th(init_attr->attr.srq_limit); + rsrq->rqe_cnt_th = rdev->cfg_info.warn_th; + rsrq->container_size = roce3_get_container_sz(rsrq->container_mode); +} +#endif + +#ifndef PANGEA_NOF +void roce3_create_user_srq_update_ext(u32 *cqn, u32 srqn) +{ + return; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c new file mode 100644 index 000000000..7f8229ece --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c @@ -0,0 +1,148 @@ +/* + * Huawei HiNIC PCI Express Linux driver + * Copyright(c) 2017 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": [NIC]" fmt + +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/etherdevice.h> +#include <linux/if_vlan.h> +#include <linux/ethtool.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/pci.h> +#include <linux/netdevice.h> +#include <linux/module.h> + +#include "ossl_knl.h" +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "hinic3_common.h" +#include "hinic3_nic.h" +#include "hisec_mpu_cmd.h" +#include "hisec_mpu_cmd_defs.h" +#include "hisec_cfg.h" + +static int hisec_send_msg_to_mpu_sync(void *hwdev, u8 cmd, void *buf_in, + u16 in_size, void *buf_out, + u16 *out_size) +{ + /* todo:: vf need to mpu com or not ? */ + return hinic3_msg_to_mgmt_sync(hwdev, HINIC3_MOD_CRYPT, cmd, buf_in, + in_size, buf_out, out_size, + 0, HINIC3_CHANNEL_CRYPT); +} + +int hisec_set_ipsec_offload_mode(void *hwdev, u8 offload_mode) +{ + struct hinic3_nic_io *nic_io = NULL; + struct hisec_cmd_ipsec_offload_mode ipsec_cfg; + u16 out_size = sizeof(ipsec_cfg); + int err; + + if (!hwdev) + return -EINVAL; + + nic_io = hinic3_get_service_adapter(hwdev, SERVICE_T_NIC); + if (!nic_io) + return -EINVAL; + + memset(&ipsec_cfg, 0, sizeof(ipsec_cfg)); + ipsec_cfg.func_id = hinic3_global_func_id(hwdev); + ipsec_cfg.offload_mode = offload_mode; + + err = hisec_send_msg_to_mpu_sync(hwdev, + HISEC_MPU_CMD_SET_IPSEC_OFFLOAD_MODE, + &ipsec_cfg, sizeof(ipsec_cfg), + &ipsec_cfg, &out_size); + if (err || !out_size || ipsec_cfg.msg_head.status) { + nic_err(nic_io->dev_hdl, "Failed to set ipsec offload mode, err: %d, status: 0x%x, out size: 0x%x\n", + err, ipsec_cfg.msg_head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int hisec_get_crypto_stats(void *hwdev, struct hisec_crypto_stats *stats) +{ + struct hisec_cmd_cryptodev_stats cdev_stats; + u16 out_size = sizeof(cdev_stats); + struct hinic3_nic_io *nic_io = NULL; + int err; + + if (!hwdev || !stats) + return -EINVAL; + + nic_io = hinic3_get_service_adapter(hwdev, SERVICE_T_NIC); + if (!nic_io) + return -EINVAL; + + memset(&cdev_stats, 0, sizeof(cdev_stats)); + + err = hisec_send_msg_to_mpu_sync(hwdev, HISEC_MPU_CMD_GET_CRYPTO_STATS, + &cdev_stats, sizeof(cdev_stats), + &cdev_stats, &out_size); + if (err || !out_size || cdev_stats.msg_head.status) { + nic_err(nic_io->dev_hdl, "Failed to get cryptodev statistics, err: %d, status: 0x%x, out size: 0x%x\n", + err, cdev_stats.msg_head.status, out_size); + return -EFAULT; + } + + memcpy(stats, &cdev_stats.stats, sizeof(*stats)); + + return 0; +} + +int hisec_flush_ipsec_resource(void *hwdev, u32 flush_flag) +{ + struct hinic3_nic_io *nic_io = NULL; + struct hinic3_cmd_buf *cmd_buf = NULL; + hisec_cmd_flush_ipsec_res_s *flush_buf = NULL; + int ret = 0; + u64 out_param = 0; + + if (!hwdev) + return -EINVAL; + + nic_io = hinic3_get_service_adapter(hwdev, SERVICE_T_NIC); + if (!nic_io) + return -EINVAL; + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + if (!cmd_buf) { + sdk_err(nic_io->dev_hdl, "Failed to alloc cmd buf\n"); + return -ENOMEM; + } + + cmd_buf->size = sizeof(*flush_buf); + flush_buf = (hisec_cmd_flush_ipsec_res_s *)cmd_buf->buf; + flush_buf->func_id = cpu_to_be16(hinic3_global_func_id(hwdev)); + flush_buf->flush_flag = cpu_to_be32(flush_flag); + flush_buf->cmdhdr.dw0.bs.cmd_type = HISEC_NPU_CMD_FLUSH_IPSEC_RES; + flush_buf->cmdhdr.dw0.value = cpu_to_be32(flush_buf->cmdhdr.dw0.value); + + ret = hinic3_cmdq_direct_resp(hwdev, HINIC3_MOD_CRYPT, + HISEC_NPU_CMD_FLUSH_IPSEC_RES, cmd_buf, + &out_param, 0, HINIC3_CHANNEL_CRYPT); + if (ret || out_param) { + sdk_err(nic_io->dev_hdl, "Failed to flush IPsec res, ret: %d, out_param: 0x%llx\n", + ret, out_param); + ret = -EFAULT; + } + + hinic3_free_cmd_buf(hwdev, cmd_buf); + + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h new file mode 100644 index 000000000..2d1e56d09 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h @@ -0,0 +1,26 @@ +/* + * Huawei HiNIC PCI Express Linux driver + * Copyright(c) 2017 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ + +#ifndef HISEC_CFG_H +#define HISEC_CFG_H + +#include "hinic3_cqm.h" +#include "hisec_mpu_cmd_defs.h" + +int hisec_flush_ipsec_resource(void *hwdev, u32 flush_flag); +int hisec_set_ipsec_offload_mode(void *hwdev, u8 offload_mode); +int hisec_get_crypto_stats(void *hwdev, struct hisec_crypto_stats *stats); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c new file mode 100644 index 000000000..2c450b69f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * Description: Source File, hisec hwrand + * Create: 2023/02/02 + */ +#include <linux/types.h> +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/kdebug.h> +#include <linux/rtnetlink.h> +#include <linux/proc_fs.h> +#include <linux/miscdevice.h> + +#include "hinic3_hw.h" + +#include "hisec_npu_cmd.h" +#include "hisec_npu_cmd_defs.h" +#include "hisec_hwrand.h" + +/* Register this as a misc driver */ +#define HW_RAND_PATH "/dev/hwrand" +#define HW_RAND_CLASS "hwrand_class" +#define HW_RAND_NAME "hwrand" + +#define HW_RAND_CMDQ_MAX_BYTES 128 +#define HW_RAND_CMDQ_MIN_BYTES 16 +#define HW_RAND_READ_MAX_BYTES 256 + +#define HISEC_CDEV_CLASS_MODE ((umode_t)(S_IRUGO|S_IWUSR)) + +static struct hinic3_hwdev *ppf_hwdev; +static atomic_t g_hwrand_ref_cnt; +static dev_t g_dev_id = {0}; +/*lint -save -e104 -e808*/ +static struct class *g_hwrand_class; +/*lint -restore*/ +static struct cdev g_hwrand_cdev; + +static int file_open(struct inode* node, struct file* file) +{ + return 0; +} + +static int file_close(struct inode* inode, struct file* file) +{ + return 0; +} + +static int hisec_get_trng_from_npu(struct hinic3_hwdev *hwdev, size_t count, char *random_data) +{ + int ret = 0; + size_t data_len; + struct hinic3_cmd_buf *cmd_buf = NULL; + hisec_cmd_trng_module_s *trng_cmd = NULL; + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + if (!cmd_buf) { + pr_err("Allocate cmd buf failed.\n"); + return -ENOMEM; + } + + cmd_buf->size = sizeof(hisec_cmd_trng_module_s); + trng_cmd = (hisec_cmd_trng_module_s *)cmd_buf->buf; + trng_cmd->cmdhdr.dw0.bs.cmd_type = HISEC_NPU_CMD_HW_RANDOM; + trng_cmd->cmdhdr.dw0.value = cpu_to_be32(trng_cmd->cmdhdr.dw0.value); + + do { + data_len = (count > HW_RAND_CMDQ_MAX_BYTES) ? HW_RAND_CMDQ_MAX_BYTES: count; + trng_cmd->length = (u32)ALIGN(data_len, HW_RAND_CMDQ_MIN_BYTES); + trng_cmd->length = cpu_to_be32(trng_cmd->length); + + ret = hinic3_cmdq_detail_resp(hwdev, HINIC3_MOD_CRYPT, HISEC_NPU_CMD_HW_RANDOM, cmd_buf, + cmd_buf, NULL, 0, HINIC3_CHANNEL_CRYPT); + if (ret != 0) { + break; + } + + memcpy(random_data, (trng_cmd->resp).data_out, data_len); + random_data += data_len; + + count -= data_len; + } while (count > 0); + + hinic3_free_cmd_buf(hwdev, cmd_buf); + return ret; +} + +static ssize_t file_read(struct file* file, char __user *buff, size_t count, loff_t *off) +{ + int err; + u32 *random_data = NULL; + + if (count > HW_RAND_READ_MAX_BYTES) { + pr_err("Invalid length"); + return 0; + } + + random_data = (u32 *)vmalloc(HW_RAND_READ_MAX_BYTES); + if (random_data == NULL) { + pr_err("Vmalloc failed."); + return 0; + } + err = hisec_get_trng_from_npu(ppf_hwdev, count, (char *)random_data); + if (err != 0) { + pr_err("get hw rand from npu failed, err 0x%x.\n", err); + vfree(random_data); + return 0; + } + + if (copy_to_user(buff, random_data, (u32)count) != 0) { + pr_err("hw rand copy to user failed!"); + vfree(random_data); + return 0; + } + + vfree(random_data); + return (ssize_t)count; +} + +/* Supported driver operations */ +static const struct file_operations hw_rand_fops = { + .open = file_open, + .release = file_close, + .read = file_read +}; + +static char *hisec_cdev_class_devnode(struct device *dev, umode_t *mode) +{ + if (mode != NULL) + *mode = HISEC_CDEV_CLASS_MODE; + return NULL; +} + +int hisec_trng_init(struct hinic3_hwdev *hwdev) +{ + struct device *pdevice = NULL; + int err; + + atomic_inc(&g_hwrand_ref_cnt); + if (g_hwrand_ref_cnt.counter != 1) { + /* already initialized */ + return 0; + } + ppf_hwdev = hwdev; + + err = alloc_chrdev_region(&g_dev_id, 0, 1, HW_RAND_NAME); + if (err) { + pr_err("Register hwrand failed(0x%x)\n", err); + goto alloc_chdev_fail; + } + + /* Create equipment */ + /*lint -save -e160*/ + g_hwrand_class = class_create(THIS_MODULE, HW_RAND_CLASS); + /*lint -restore*/ + if (IS_ERR(g_hwrand_class)) { + pr_err("Create hwrand_class fail\n"); + err = -EFAULT; + goto class_create_err; + } + + g_hwrand_class->devnode = hisec_cdev_class_devnode; //lint !e10 !e63 !e40 + + /* Initializing the character device */ + cdev_init(&g_hwrand_cdev, &hw_rand_fops); + + /* Add devices to the operating system */ + err = cdev_add(&g_hwrand_cdev, g_dev_id, 1); + if (err < 0) { + pr_err("Add hwrand to operating system fail(0x%x)\n", err); + goto cdev_add_err; + } + + /* Export device information to user space + * (/sys/class/class name/device name) + */ + pdevice = device_create(g_hwrand_class, NULL, + g_dev_id, NULL, HW_RAND_NAME); + if (IS_ERR(pdevice)) { + pr_err("Export hwrand device information to user space fail\n"); + err = -EFAULT; + goto device_create_err; + } + + pr_info("Register hwrand to system succeed\n"); + + return 0; + +device_create_err: + cdev_del(&g_hwrand_cdev); + +cdev_add_err: + class_destroy(g_hwrand_class); + +class_create_err: + g_hwrand_class = NULL; + unregister_chrdev_region(g_dev_id, 1); + +alloc_chdev_fail: + atomic_dec(&g_hwrand_ref_cnt); + + return err; +} + +void hisec_trng_deinit(void) +{ + if (!(g_hwrand_ref_cnt.counter)) { + return; + } + + if ((g_hwrand_ref_cnt.counter) != 1) { + atomic_dec(&g_hwrand_ref_cnt); + return; + } + + if (!g_hwrand_class || IS_ERR(g_hwrand_class)) { + pr_err("Hwrand class is NULL.\n"); + return; + } + + device_destroy(g_hwrand_class, g_dev_id); + cdev_del(&g_hwrand_cdev); + class_destroy(g_hwrand_class); + g_hwrand_class = NULL; + + unregister_chrdev_region(g_dev_id, 1); + + pr_info("Unregister hwrand succeed\n"); +} \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.h b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.h new file mode 100644 index 000000000..ae994ad36 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * Description: Header File, hisec hwrand + * Create: 2023/02/02 + */ +#ifndef HISEC_HWRAND_H +#define HISEC_HWRAND_H + +#include "../../hwsdk/crm/hinic3_hwdev.h" + +int hisec_trng_init(struct hinic3_hwdev *hwdev); +void hisec_trng_deinit(void); + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_dev.h b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_dev.h new file mode 100644 index 000000000..f1921737b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_dev.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : crypt.h + * Version : v3.0 + * Created : 2023/10/19 + * Last Modified : 2023/10/19 + * Description : The definition of CRYPT MAIN function prototype, macros etc,. in kernel space. + */ +#ifndef CRYPT_DEV_H +#define CRYPT_DEV_H + +#include "hinic3_hw.h" +#include "hinic3_crm.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_lld.h" + +struct crypt_device { + struct hinic3_lld_dev *lld_dev; + struct pci_dev *pdev; + void *hwdev; +}; + +#define HICRYPT_DRV_NAME "crypt_drv" +#define HICRYPT_DRV_AUTHOR "Huawei Technologies CO., Ltd" +#define HICRYPT_DRV_DESC "Huawei(R) Intelligent Network Interface Card, crypt Driver" +#define HICRYPT_DRV_VERSION GLOBAL_VERSION_STR + +#endif // CRYPT_DEV_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_main.c b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_main.c new file mode 100644 index 000000000..d99c13e08 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_main.c @@ -0,0 +1,123 @@ + +/** + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * Description: implementation of dtoe driver for hi1822 chip + * Create: 2023-10-19 + * Author: Huawei + */ +#ifdef _PCLINT_ +#include "toe_pclint.h" +#else +#include <linux/module.h> +#include <linux/version.h> +#include <linux/pm.h> +#include "hinic3_hw.h" +#include "hinic3_lld.h" +#endif + +#include "hisec_hwrand.h" +#include "hisec_crypt_dev.h" + +static struct crypt_device *crypt_cryptdev_alloc(struct hinic3_lld_dev *lld_dev) +{ + struct crypt_device *crypt_dev = NULL; + crypt_dev = (struct crypt_device *)kzalloc(sizeof(struct crypt_device), GFP_KERNEL); + crypt_dev->lld_dev = lld_dev; + crypt_dev->hwdev = lld_dev->hwdev; + crypt_dev->pdev = lld_dev->pdev; + + return crypt_dev; +} + +static void crypt_cryptdev_free(struct crypt_device *crypt_dev) +{ + if (crypt_dev != NULL) { + kfree(crypt_dev); + crypt_dev = NULL; + } +} + +static int crypt_cryptserv_init(struct crypt_device *crypt_dev) +{ + int ret = 0; + if (hinic3_func_type(crypt_dev->hwdev) == TYPE_PPF) { + ret = hisec_trng_init(crypt_dev->hwdev); + } + if (ret != 0) { + pr_err("Init trng failed, ret = %d\n", ret); + return ret; + } + return 0; +} + +static void crypt_cryptserv_deinit(struct crypt_device *crypt_dev) +{ + if (hinic3_func_type(crypt_dev->hwdev) == TYPE_PPF) { + hisec_trng_deinit(); + } +} + +static int crypt_probe(struct hinic3_lld_dev *lld_dev, void **uld_dev, char *uld_dev_name) +{ + struct crypt_device *crypt_dev = NULL; + int ret = 0; + crypt_dev = crypt_cryptdev_alloc(lld_dev); + if (crypt_dev == NULL) { + pr_err("Alloc cryptdev failed, crypt_dev = NULL\n"); + goto err_dev_alloc; + } + *uld_dev = (void *)crypt_dev; + ret = crypt_cryptserv_init(crypt_dev); + if (ret != 0) { + pr_err("Init cryptserv failed, ret = %d\n", ret); + goto err_serv_init; + } + return 0; + +err_serv_init: + crypt_cryptdev_free(crypt_dev); +err_dev_alloc: + return -EINVAL; +} + +static void crypt_remove(struct hinic3_lld_dev *lld_dev, void *uld_dev) +{ + struct crypt_device *crypt_dev = NULL; + crypt_dev = (struct crypt_device *)uld_dev; + crypt_cryptserv_deinit(crypt_dev); + crypt_cryptdev_free(crypt_dev); +} + +struct hinic3_uld_info g_crypt_uld_info = { + .probe = crypt_probe, + .remove = crypt_remove, + .suspend = NULL, + .resume = NULL, + .event = NULL, + .ioctl = NULL, +}; + +static int __init crypt_init(void) +{ + int ret = 0; + ret = hinic3_register_uld(SERVICE_T_CRYPT, &g_crypt_uld_info); + if (ret) { + pr_err("Register crypt hinic3 uld failed, ret = %d\n", ret); + return ret; + } + + return 0; +} + +static void __exit crypt_exit(void) +{ + hinic3_unregister_uld(SERVICE_T_CRYPT); +} + +module_init(crypt_init); +module_exit(crypt_exit); + +MODULE_AUTHOR(HICRYPT_DRV_AUTHOR); +MODULE_DESCRIPTION(HICRYPT_DRV_DESC); +MODULE_VERSION(HICRYPT_DRV_VERSION); +MODULE_LICENSE("GPL"); \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/readme.txt b/drivers/infiniband/hw/hiroce3/host/crypt/readme.txt new file mode 100644 index 000000000..3094243db --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/readme.txt @@ -0,0 +1 @@ +本目录是主机软件代码中加解密业务实现的代码目录 \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.c new file mode 100644 index 000000000..b1b2cead9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.c @@ -0,0 +1,170 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_buddy.c + Version : Initial Draft + Description : realize the management of buddy +***************************************************************************** */ + +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include "hinic3_hw.h" +#include "hmm_comp.h" +#include "hmm_buddy.h" + + +u32 hmm_buddy_alloc(struct hmm_buddy *buddy, u32 order) +{ + u32 first_index = 0; + u32 cur_order = 0; + u32 cur_bit_num = 0; + + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return HMM_INVALID_INDEX; + } + if (order > buddy->max_order) { + pr_err("%s: Order(%d) is bigger than max order(%d)\n", __FUNCTION__, order, buddy->max_order); + return HMM_INVALID_INDEX; + } + spin_lock(&buddy->lock); + + for (cur_order = order; cur_order <= buddy->max_order; ++cur_order) { + if (buddy->num_free[cur_order] != 0) { + cur_bit_num = 1U << (buddy->max_order - cur_order); + first_index = (u32)find_first_bit(buddy->bits[cur_order], (unsigned long)cur_bit_num); + if (first_index < cur_bit_num) { + goto found; + } + } + } + spin_unlock(&buddy->lock); + pr_err("%s: Get a invalid index\n", __FUNCTION__); + return HMM_INVALID_INDEX; + +found: + clear_bit((int)first_index, buddy->bits[cur_order]); + --buddy->num_free[cur_order]; + + while (cur_order > order) { + --cur_order; + first_index <<= 1; + set_bit(first_index ^ 1, buddy->bits[cur_order]); + ++buddy->num_free[cur_order]; + } + first_index <<= order; + spin_unlock(&buddy->lock); + return first_index; +} + +void hmm_buddy_free(struct hmm_buddy *buddy, u32 first_index, u32 order) +{ + u32 tmp_first_index = first_index; + u32 tmp_order = order; + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return; + } + if (tmp_order > buddy->max_order) { + pr_err("%s: Order(%d) is bigger than max order(%d)\n", __FUNCTION__, tmp_order, buddy->max_order); + return; + } + tmp_first_index >>= tmp_order; + spin_lock(&buddy->lock); + while (test_bit((int)(tmp_first_index ^ 1), buddy->bits[tmp_order]) != 0) { + clear_bit((int)(tmp_first_index ^ 1), buddy->bits[tmp_order]); + --buddy->num_free[tmp_order]; + tmp_first_index >>= 1; + ++tmp_order; + } + set_bit(tmp_first_index, buddy->bits[tmp_order]); + ++buddy->num_free[tmp_order]; + spin_unlock(&buddy->lock); + return; +} + +static void hmm_buddy_alloc_bitmap_fail(struct hmm_buddy *buddy, u32 i) +{ + u32 j = 0; + for (j = 0; j < i; j++) { + if (is_vmalloc_addr(buddy->bits[j])) { + vfree(buddy->bits[j]); + } else { + kfree(buddy->bits[j]); + } + buddy->bits[j] = NULL; + } + kfree(buddy->bits); + buddy->bits = NULL; + return; +} + +int hmm_buddy_init(struct hmm_buddy *buddy, u32 max_order) +{ + u32 i = 0; + u32 bit_num = 0; + + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return -EINVAL; + } + buddy->max_order = max_order; + /*lint -e708*/ + spin_lock_init(&buddy->lock); + /*lint +e708*/ + buddy->num_free = (unsigned int *)kcalloc((unsigned long)(buddy->max_order + 1UL), sizeof(int), GFP_KERNEL); + if (buddy->num_free == NULL) { + pr_err("%s: Alloc memory for buddy->num_free failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + buddy->bits = (unsigned long **)kcalloc((unsigned long)(buddy->max_order + 1UL), sizeof(long *), GFP_KERNEL); + if (buddy->bits == NULL) { + pr_err("%s: Alloc memory for buddy->bits failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + goto alloc_bits_fail; + } + + for (i = 0; i <= buddy->max_order; i++) { + bit_num = (u32)BITS_TO_LONGS(1UL << (buddy->max_order - i)); + buddy->bits[i] = (unsigned long *)kcalloc((unsigned long)bit_num, sizeof(long), GFP_KERNEL | __GFP_NOWARN); + if (buddy->bits[i] == NULL) { + pr_err("%s: Kcalloc memory for buddy->bits[%d] failed, ret(%d)\n", __FUNCTION__, i, -ENOMEM); + buddy->bits[i] = (unsigned long *)vzalloc((unsigned long)bit_num * sizeof(long)); + if (buddy->bits[i] == NULL) { + pr_err("%s: Vzalloc memory for buddy->bits[%d] failed, ret(%d)\n", __FUNCTION__, i, -ENOMEM); + goto alloc_bitmap_fail; + } + } + } + set_bit(0, buddy->bits[buddy->max_order]); + buddy->num_free[buddy->max_order] = 1; + return 0; + +alloc_bitmap_fail: + hmm_buddy_alloc_bitmap_fail(buddy, i); +alloc_bits_fail: + kfree(buddy->num_free); + buddy->num_free = NULL; + return -ENOMEM; +} + +void hmm_buddy_cleanup(struct hmm_buddy *buddy) +{ + u32 i; + + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return; + } + for (i = 0; i <= buddy->max_order; i++) { + if (is_vmalloc_addr(buddy->bits[i])) { + vfree(buddy->bits[i]); + } else { + kfree(buddy->bits[i]); + } + buddy->bits[i] = NULL; + } + kfree(buddy->bits); + buddy->bits = NULL; + kfree(buddy->num_free); + buddy->num_free = NULL; + return; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.h new file mode 100644 index 000000000..858ff780b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.h @@ -0,0 +1,36 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_buddy.h + Version : Initial Draft + Description : define buddy related macro and structure +***************************************************************************** */ + +#ifndef HMM_BUDDY_H +#define HMM_BUDDY_H + +#include <linux/spinlock.h> +#include <linux/mm.h> + +#if defined(__i386__) +#include <asm/highmem.h> +#endif + +#ifndef HMM_INVALID_INDEX +#define HMM_INVALID_INDEX 0xFFFFFFFF +#endif + +struct hmm_buddy { + unsigned long **bits; /* 指向多级bitmap的内存 */ + unsigned int *num_free; /* 指示各级bitmap中可用的索引个数 */ + u32 max_order; /* 指bitmap的级数 */ + spinlock_t lock; /* buddy的自旋锁 */ +}; + +u32 hmm_buddy_alloc(struct hmm_buddy *buddy, u32 order); +void hmm_buddy_free(struct hmm_buddy *buddy, u32 first_index, u32 order); + +int hmm_buddy_init(struct hmm_buddy *buddy, u32 max_order); +void hmm_buddy_cleanup(struct hmm_buddy *buddy); + + +#endif // HMM_BUDDY_H diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.c new file mode 100644 index 000000000..886788ba9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.c @@ -0,0 +1,165 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp.c + Version : Initial Draft + Last Modified : + Description : implement the management of PDID, XRCD, MPT, MTT, RDMARC, + GID and GUID +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> +#include "hinic3_hw.h" +#include "hmm_comp.h" + + +struct hmm_comp_priv *get_hmm_comp_priv(void *hwdev, u32 service_type) +{ + return (struct hmm_comp_priv *)hinic3_get_service_adapter(hwdev, (enum hinic3_service_type)service_type); +} + +static void assemble_mpt_hw2sw(struct rdma_mpt_hw2sw_inbuf **mpt_hw2sw_inbuf, struct hmm_comp_priv *comp_priv, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + *mpt_hw2sw_inbuf = (struct rdma_mpt_hw2sw_inbuf *)cqm_cmd_inbuf->buf; + memset(*mpt_hw2sw_inbuf, 0, sizeof(struct rdma_mpt_hw2sw_inbuf)); + + (*mpt_hw2sw_inbuf)->dmtt_flags = 0; /* 默认按VF踢除cache */ + (*mpt_hw2sw_inbuf)->dmtt_num = 0; + (*mpt_hw2sw_inbuf)->dmtt_cache_line_start = cpu_to_be32(comp_priv->rdma_cap.dmtt_cl_start); + (*mpt_hw2sw_inbuf)->dmtt_cache_line_end = cpu_to_be32(comp_priv->rdma_cap.dmtt_cl_end); + (*mpt_hw2sw_inbuf)->dmtt_cache_line_size = cpu_to_be32(comp_priv->rdma_cap.dmtt_cl_sz); + return; +} + +int hmm_enable_roce_mpt(void *hwdev, cqm_cmd_buf_s *cqm_cmd_inbuf, u16 channel) +{ + int ret; + + ret = cqm_send_cmd_box(hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_SW2HW_MPT, cqm_cmd_inbuf, NULL, NULL, + RDMA_CMD_TIME_OUT_A, channel); + if (ret != 0) { + if (hinic3_get_heartbeat_status(hwdev) != PCIE_LINK_DOWN) { + pr_err("%s: Send cmd rdma_roce_cmd_sw2hw_mpt failed, ret(%d)\n", __FUNCTION__, ret); + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + return -RDMA_CMDQ_TIMEOUT; + } + return -RDMA_CMDQ_ERR; + } + pr_err("%s: Card not present, return err\n", __FUNCTION__); + return -RDMA_CMDQ_ERR; + } + + return 0; +} + +static int hmm_mpt_read_back_test(struct hmm_comp_priv *comp_priv, struct rdma_mpt *mpt) +{ + int retry; + struct rdma_mpt_entry *mpt_entry = NULL; + struct rdma_mpt_entry check_mpt_entry; + + /* 获取Host MPT内容 */ + mpt_entry = (struct rdma_mpt_entry *)mpt->vaddr; + for (retry = 0; retry < RDMA_MAX_RETRY; retry++) { + if (hinic3_get_heartbeat_status(comp_priv->hwdev) == PCIE_LINK_DOWN) { + pr_err("%s: Card not present, return ok\n", __FUNCTION__); + return 0; + } + /* 通过比较MPT State字段,确认芯片操作完成 + * 回读状态正确则跳出,否则强制延迟后继续读取比较，直至循环结束 */ + check_mpt_entry.roce_mpt_ctx.dw2.value = be32_to_cpu(mpt_entry->roce_mpt_ctx.dw2.value); + if (check_mpt_entry.roce_mpt_ctx.dw2.bs.status == RDMA_MPT_STATUS_INVALID) { + return 0; + } +#ifndef _lint + /*lint -e160 -e506*/ + mdelay(RDMA_MS_DELAY); + /*lint +e160 +e506*/ +#endif + } + + pr_err("%s: RoCE mpt state read times(%d), mpt_index(0x%x), state_dw(0x%x)\n", __FUNCTION__, retry, + mpt->mpt_index, mpt_entry->roce_mpt_ctx.dw2.value); + return -RDMA_CMDQ_ERR; +} + +int hmm_disable_roce_mpt(struct hmm_comp_priv *comp_priv, struct rdma_mpt *mpt, u16 channel) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct rdma_mpt_hw2sw_inbuf *mpt_hw2sw_inbuf = NULL; + + cqm_cmd_inbuf = cqm_cmd_alloc(comp_priv->hwdev); + if (cqm_cmd_inbuf == NULL) { + pr_err("%s: RoCE alloc cmd_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + cqm_cmd_inbuf->size = (u16)sizeof(struct rdma_mpt_hw2sw_inbuf); + assemble_mpt_hw2sw(&mpt_hw2sw_inbuf, comp_priv, cqm_cmd_inbuf); + mpt_hw2sw_inbuf->com.index = cpu_to_be32(mpt->mpt_index); + mpt_hw2sw_inbuf->com.dw0.bs.cmd_bitmask = (u16)cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + ret = cqm_send_cmd_box(comp_priv->hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_HW2SW_MPT, cqm_cmd_inbuf, NULL, NULL, + RDMA_CMD_TIME_OUT_A, channel); + if (ret != 0) { + if (hinic3_get_heartbeat_status(comp_priv->hwdev) != PCIE_LINK_DOWN) { + pr_err("%s: Send cmd rdma_roce_cmd_hw2sw_mpt failed, ret(%d)\n", __FUNCTION__, ret); + cqm_cmd_free(comp_priv->hwdev, cqm_cmd_inbuf); + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + return -RDMA_CMDQ_TIMEOUT; + } + return -RDMA_CMDQ_ERR; + } + pr_err("%s: Card not present, return ok\n", __FUNCTION__); + cqm_cmd_free(comp_priv->hwdev, cqm_cmd_inbuf); + return 0; + } + cqm_cmd_free(comp_priv->hwdev, cqm_cmd_inbuf); + + ret = hmm_mpt_read_back_test(comp_priv, mpt); + return ret; +} + + +int hmm_modify_roce_mpt(void *hwdev, u32 mpt_index, u32 new_key, u64 length, u64 iova, u16 channel) +{ + cqm_cmd_buf_s *cqm_cmd_inbuf; + struct rdma_mpt_modify_inbuf *mpt_modify_inbuf = NULL; + int ret; + + cqm_cmd_inbuf = cqm_cmd_alloc(hwdev); + if (cqm_cmd_inbuf == NULL) { + pr_err("%s: RoCE alloc cmd_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + cqm_cmd_inbuf->size = (u16)sizeof(struct rdma_mpt_modify_inbuf); + mpt_modify_inbuf = (struct rdma_mpt_modify_inbuf *)cqm_cmd_inbuf->buf; + memset(mpt_modify_inbuf, 0, sizeof(*mpt_modify_inbuf)); + + mpt_modify_inbuf->com.dw0.bs.cmd_bitmask = (u16)cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + mpt_modify_inbuf->com.index = cpu_to_be32(mpt_index); + mpt_modify_inbuf->new_key = cpu_to_be32(new_key); + mpt_modify_inbuf->length = cpu_to_be64(length); + mpt_modify_inbuf->iova = cpu_to_be64(iova); + + ret = cqm_send_cmd_box(hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_MODIFY_MPT, cqm_cmd_inbuf, NULL, NULL, + RDMA_CMD_TIME_OUT_A, channel); + if (ret != 0) { + if (hinic3_get_heartbeat_status(hwdev) != PCIE_LINK_DOWN) { + pr_err("%s: Send cmd rdma_roce_cmd_modify_mpt failed, ret(%d)\n", __FUNCTION__, ret); + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + return -RDMA_CMDQ_TIMEOUT; + } + return -RDMA_CMDQ_ERR; + } + pr_err("%s: Card not present, return ok\n", __FUNCTION__); + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + return 0; + } + + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.h new file mode 100644 index 000000000..96293a677 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.h @@ -0,0 +1,225 @@ +/* Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp.h + Version : Initial Draft + Description : define rdma component related macro, structure and interface */ + +#ifndef HMM_COMP_H +#define HMM_COMP_H + +#ifndef ROCE_SERVICE +#include "ossl_knl.h" +#endif +#include <linux/delay.h> +#include <linux/types.h> +#include "roce_hmm_context.h" +#include "hinic3_crm.h" +#include "hinic3_cqm.h" +#include "hinic3_rdma.h" +#include "hmm_buddy.h" +#include "hmm_em.h" + +/* x86 */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +#define PCIE_LINK_DOWN 0xFFFFFFFF + +#define RDMA_MPT_STATUS_INVALID 0xf +#define RDMA_MPT_STATUS_FREE 0x3 +#define RDMA_MPT_STATUS_VALID 0x1 +#define RDMA_MPT_STATUS_MEM_INIT 0xa + +#define RDMA_MS_DELAY 5 +#define RDMA_MAX_RETRY 200 + +#define RDMA_MPT_DMA_ATTR_IDX 0 +#define RDMA_MPT_SO_RO 0x1 + +#define RDMA_PA_SIZE ((u32)sizeof(dma_addr_t)) + +#define PAGE_SIZE_4k 4096 /* page size is 4K */ +#define PAGE_SHIFT_4K 12 /* page size is 1 left shift 12 */ + +#define PAGE_SIZE_64k (64 * 4096) /* page size is 64K */ +#define PAGE_SHIFT_64K 16 /* page size is 1 left shift 16 */ + +#define PAGE_SIZE_2M (2 * 1024 * 1024) /* page size is 2M */ +#define PAGE_SHIFT_2M 21 /* page size is 1 left shift 21 */ + +#define RDMA_MTT_PA_VALID 0x1 + +#define HMM_MTT_NUM_PER_CACHELINE 32 /* 256B Cache line has 32 records */ + +#define BLOCK_SIZE_DEVIDE_SECTOR 8 /* Chip logic: 8 */ + + +#define MPT_GPA_SIG_LEN 3 + +#define RDMA_CMDQ_ERR 1 +#define RDMA_CMDQ_TIMEOUT 2 + +#ifndef VERBS_CMD_TYPE_MR_BITMASK +#define VERBS_CMD_TYPE_MR_BITMASK (1u << 12) /* verbs_mr_bitmask */ +#endif + +enum { + RDMA_MTT_PAGE_SIZE_4K = 0, + RDMA_MTT_PAGE_SIZE_64K = 1, + RDMA_MTT_PAGE_SIZE_2M = 2 +}; + +#ifdef __EMU_X86__ +enum { + RDMA_CMD_TIME_OUT_A = 30000000, + RDMA_CMD_TIME_OUT_B = 40000000, + RDMA_CMD_TIME_OUT_C = 50000000 +}; +#else +enum { + RDMA_CMD_TIME_OUT_A = 30000, + RDMA_CMD_TIME_OUT_B = 40000, + RDMA_CMD_TIME_OUT_C = 50000 +}; +#endif + +enum rdma_mr_mw { + RDMA_MPT_MW = 0, + RDMA_MPT_MR = 1 +}; + +enum rdma_roce_cmd { + RDMA_ROCE_CMD_SW2HW_MPT = 0x70, + RDMA_ROCE_CMD_HW2SW_MPT = 0x71, + RDMA_ROCE_CMD_MODIFY_MPT = 0x72, + RDMA_ROCE_CMD_QUERY_MPT = 0x73, + RDMA_ROCE_CMD_FLUSH_TPT = 0x74, + RDMA_ROCE_CMD_SYNC_TPT = 0x75 +}; + + +enum mtt_layer { + RDMA_MTT_NO_LAYER = -1, /* dma mr needs no mtt */ + RDMA_MTT_ZERO_LAYER = 0, /* 1 page mr has 0 level mtt */ + RDMA_MTT_ONE_LAYER = 1, + RDMA_MTT_TWO_LAYER = 2, + RDMA_MTT_THREE_LAYER = 3 +}; + +typedef struct rdma_verbs_cmd_com { + union { + __be32 value; + + struct { + __be32 version : 8; + __be32 rsvd : 8; + __be32 cmd_bitmask : 16; + } bs; + } dw0; + + __be32 index; +} rdma_verbs_cmd_com_s; + +struct hmm_service_cap { + struct dev_rdma_svc_cap dev_rdma_cap; + u8 log_mtt; /* 1. the number of MTT PA must be integer power of 2 + * 2. represented by logarithm. Each MTT table can + * contain 1, 2, 4, 8, and 16 PA) + */ + /* todo: need to check whether related to max_mtt_seg */ + u32 num_mtts; /* Number of MTT table (4M), + * is actually MTT seg number + */ + /* todo: max value needs to be confirmed */ + /* MTT table number of Each MTT seg(3) */ + u32 log_mtt_seg; + u32 mtt_entry_sz; /* MTT table size 8B, including 1 PA(64bits) */ + u32 mpt_entry_sz; /* MPT table size (64B) */ + + u32 dmtt_cl_start; + u32 dmtt_cl_end; + u32 dmtt_cl_sz; + u32 mtt_page_size; /* 4K, 8K, 16K, 32K */ + u32 mtt_page_shift; /* 12, 13, 14, 15 */ +}; + + +struct hmm_comp_priv { + struct rdma_comp_resource rdma_comp_res; /* gid & guid */ + struct hmm_buddy mtt_buddy; + struct hmm_em_table mtt_em_table; + void *hwdev; + struct pci_dev *pdev; + struct rdma_mr rsvd_lkey; + struct rdma_mr fixed_mr; + u32 mtt_page_size; /* 4K, 8K, 16K, 32K */ + u32 mtt_page_shift; /* 12, 13, 14, 15 */ + + struct hmm_service_cap rdma_cap; +}; + +typedef struct rdma_mpt_entry { + struct roce_mpt_context roce_mpt_ctx; +} rdma_mpt_entry_s; + +struct rdma_mpt_sw2hw_inbuf { + rdma_verbs_cmd_com_s com; + struct rdma_mpt_entry mpt_entry; +}; + +struct rdma_mpt_hw2sw_inbuf { + rdma_verbs_cmd_com_s com; + + __be32 dmtt_flags; + __be32 dmtt_num; + __be32 dmtt_cache_line_start; + __be32 dmtt_cache_line_end; + __be32 dmtt_cache_line_size; +}; + +struct rdma_mpt_modify_inbuf { + rdma_verbs_cmd_com_s com; + __be32 new_key; + __be64 length; + __be64 iova; +}; + + +/* for llt to set stub */ +int hmm_disable_roce_mpt(struct hmm_comp_priv *comp_priv, struct rdma_mpt *mpt, u16 channel); + +int hmm_modify_roce_mpt(void *hwdev, u32 mpt_index, u32 new_key, u64 length, u64 iova, u16 channel); + +struct hmm_comp_priv *get_hmm_comp_priv(void *hwdev, u32 service_type); + +int hmm_rdma_mpt_alloc(void *hwdev, struct rdma_mpt *mpt, u32 service_type); + +int hmm_enable_roce_mpt(void *hwdev, cqm_cmd_buf_s *cqm_cmd_inbuf, u16 channel); + +#ifdef RDMA_SIGN_MTT_EN +u64 hmm_gen_mtt_sign(u64 mtt_base_gpa, enum mtt_data_type_e type); + +#define RDMA_CMTT_SIGN_MASK 0x7ff +#define RDMA_CMTT_SIGN_SHIFT0 3 +#define RDMA_CMTT_SIGN_SHIFT1 14 +#define RDMA_CMTT_SIGN_SHIFT2 25 + +#define RDMA_DMTT_SIGN_MASK 0x3ff + +#define RDMA_DMTT_ADD_SHIFT0 7 +#define RDMA_DMTT_SIGN_SHIFT0 3 +#define RDMA_DMTT_SIGN_SHIFT1 6 +#define RDMA_DMTT_SIGN_SHIFT2 16 +#define RDMA_DMTT_SIGN_SHIFT3 26 + +#endif + +#endif // HMM_COMP_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_init.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_init.c new file mode 100644 index 000000000..85c342edd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_init.c @@ -0,0 +1,131 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp_init.c + Version : Initial Draft + Last Modified : + Description : implement the management of MPT, MTT +***************************************************************************** */ +#include <linux/module.h> +#include <linux/netdevice.h> +#include "hinic3_hw.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_crm.h" + +#include "hmm_comp.h" +#include "hinic3_hmm.h" + +#define ROCE_MAX_RDMA_RC_EXTEND 384 /* 扩展表为12K */ + +u32 g_mtt_page_size = 0U; +module_param(g_mtt_page_size, uint, S_IRUGO); +MODULE_PARM_DESC(g_mtt_page_size, "0:4K,1:64K,2:2M,default:4K"); + +static int hmm_init_table(void *hwdev, struct hmm_comp_priv *comp_priv, u32 srv_type) +{ + int ret; + + ret = hmm_init_mtt_table(comp_priv); + if (ret != 0) { + pr_err("%s: Initialize mtt's table failed, ret(%d)\n", __FUNCTION__, ret); + kfree(comp_priv); + return ret; + } + + ret = hinic3_register_service_adapter((void *)hwdev, (void *)comp_priv, (enum hinic3_service_type)srv_type); + if (ret != 0) { + pr_err("%s: put hmm_comp_res failed, ret(%d)\n", __FUNCTION__, ret); + goto err_init; + } + pr_info("%s: Hmm init resource successful\n", __FUNCTION__); + return 0; + +err_init: + hmm_cleanup_mtt_table(comp_priv); + kfree(comp_priv); + return ret; +} + +void hmm_cleanup_resource(void *hwdev, u32 service_type) +{ + struct rdma_service_cap rdma_cap; + struct hmm_comp_priv *comp_priv = NULL; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return; + } + + if (!hinic3_support_rdma(hwdev, &rdma_cap)) { + pr_err("%s: Not support rdma service\n", __FUNCTION__); + return; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + hmm_cleanup_mtt_table(comp_priv); + + kfree(comp_priv); + + hinic3_unregister_service_adapter((void *)hwdev, (enum hinic3_service_type)service_type); + + pr_info("%s: Rdma cleanup resource successful", __FUNCTION__); + + return; +} + +int hmm_init_resource(void *hwdev, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + struct rdma_service_cap rdma_cap; + int ret; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return -EINVAL; + } + if (!hinic3_support_rdma(hwdev, &rdma_cap)) { + pr_info("%s: Don't support hmm dev\n", __FUNCTION__); + return 0; + } + comp_priv = (struct hmm_comp_priv *)kzalloc(sizeof(struct hmm_comp_priv), GFP_KERNEL); + if (comp_priv == NULL) { + pr_err("%s: Alloc memory for comp_priv failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + comp_priv->hwdev = hwdev; + comp_priv->pdev = (struct pci_dev *)((struct hinic3_hwdev *)hwdev)->pcidev_hdl; + comp_priv->rdma_cap.log_mtt = rdma_cap.log_mtt; + comp_priv->rdma_cap.log_mtt_seg = rdma_cap.log_mtt_seg; + comp_priv->rdma_cap.mtt_entry_sz = rdma_cap.mtt_entry_sz; + comp_priv->rdma_cap.mpt_entry_sz = rdma_cap.mpt_entry_sz; + comp_priv->rdma_cap.num_mtts = rdma_cap.num_mtts; + + comp_priv->rdma_cap.dmtt_cl_start = rdma_cap.dev_rdma_cap.roce_own_cap.dmtt_cl_start; + comp_priv->rdma_cap.dmtt_cl_end = rdma_cap.dev_rdma_cap.roce_own_cap.dmtt_cl_end; + comp_priv->rdma_cap.dmtt_cl_sz = rdma_cap.dev_rdma_cap.roce_own_cap.dmtt_cl_sz; + + switch (g_mtt_page_size) { + case RDMA_MTT_PAGE_SIZE_4K: + comp_priv->mtt_page_size = PAGE_SIZE_4k; /* page size is 4K */ + comp_priv->mtt_page_shift = PAGE_SHIFT_4K; /* page size is 1 left shift 12 */ + break; + case RDMA_MTT_PAGE_SIZE_64K: + comp_priv->mtt_page_size = PAGE_SIZE_64k; /* page size is 64K */ + comp_priv->mtt_page_shift = PAGE_SHIFT_64K; /* page size is 1 left shift 16 */ + break; + case RDMA_MTT_PAGE_SIZE_2M: + comp_priv->mtt_page_size = PAGE_SIZE_2M; /* page size is 2M */ + comp_priv->mtt_page_shift = PAGE_SHIFT_2M; /* page size is 1 left shift 21 */ + break; + default: + comp_priv->mtt_page_size = PAGE_SIZE_4k; /* page size is 4K */ + comp_priv->mtt_page_shift = PAGE_SHIFT_4K; /* page size is 1 left shift 12 */ + break; + } + ret = hmm_init_table(hwdev, comp_priv, service_type); + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mtt.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mtt.c new file mode 100644 index 000000000..f9478e2c8 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mtt.c @@ -0,0 +1,497 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + + Description : implement the management of MPT, MTT +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "hinic3_rdma.h" +#include "hmm_comp.h" +#include "hmm_mr.h" + +static int hmm_set_mtt_layer(const struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 npages) +{ + u32 one_layer_flag = 0; + u64 two_layer_flag = 0; + u64 three_layer_flag = 0; + + one_layer_flag = comp_priv->mtt_page_size / RDMA_PA_SIZE; + two_layer_flag = ((u64)one_layer_flag) * ((u64)one_layer_flag); + three_layer_flag = (u64)one_layer_flag * two_layer_flag; + + if (npages <= 1) { + mtt->mtt_layers = RDMA_MTT_ZERO_LAYER; + return 0; + } else if (npages <= one_layer_flag) { + mtt->mtt_layers = RDMA_MTT_ONE_LAYER; + } else if (npages <= two_layer_flag) { + mtt->mtt_layers = RDMA_MTT_TWO_LAYER; + } else if ((u64)npages <= three_layer_flag) { + mtt->mtt_layers = RDMA_MTT_THREE_LAYER; + } else { + pr_err("%s: Npages(0x%x) over range, ret(%d)\n", __FUNCTION__, npages, -EINVAL); + return -EINVAL; + } + + return 0; +} + +#ifdef RDMA_SIGN_MTT_EN + +u16 hmm_gen_cmtt_sign(u64 mtt_base_gpa) +{ + u16 sign0 = (mtt_base_gpa >> RDMA_CMTT_SIGN_SHIFT0) & RDMA_CMTT_SIGN_MASK; + u16 sign1 = (mtt_base_gpa >> RDMA_CMTT_SIGN_SHIFT1) & RDMA_CMTT_SIGN_MASK; + u16 sign2 = (mtt_base_gpa >> RDMA_CMTT_SIGN_SHIFT2) & RDMA_CMTT_SIGN_MASK; + u16 cmtt_sign = ~(sign0 ^ sign1 ^ sign2); + cmtt_sign &= RDMA_CMTT_SIGN_MASK; + return cmtt_sign; +} + +u16 hmm_gen_dmtt_sign(u64 mtt_base_gpa) +{ + u16 sign0 = ((u16)(mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT0) << RDMA_DMTT_ADD_SHIFT0) & RDMA_DMTT_SIGN_MASK; + u16 sign1 = (mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT1) & RDMA_DMTT_SIGN_MASK; + u16 sign2 = (mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT2) & RDMA_DMTT_SIGN_MASK; + u16 sign3 = (mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT3) & RDMA_DMTT_SIGN_MASK; + u16 dmtt_sign = ~(sign0 ^ sign1 ^ sign2 ^ sign3); + dmtt_sign &= RDMA_DMTT_SIGN_MASK; + return dmtt_sign; +} + + +u64 hmm_gen_mtt_sign(u64 mtt_base_gpa, enum mtt_data_type_e type) +{ + if (type == MTT_CMTT_TYPE) { + return hmm_gen_cmtt_sign(mtt_base_gpa); + } + return (u64)hmm_gen_dmtt_sign(mtt_base_gpa) << 1; +} + +#endif + +static int hmm_find_mtt_page_list(struct hmm_comp_priv *comp_priv, struct rdma_mtt_seg *mtt_seg, u32 npages, + u64 *page_list) +{ + void *vaddr = NULL; + u32 i = 0; + u32 mtt_index = 0; + u32 mtts_per_page = 0; + + mtts_per_page = comp_priv->mtt_page_size / RDMA_PA_SIZE; + if ((mtt_seg->offset % mtts_per_page) != 0) { + pr_err("%s: First mtt isn't in the head of page, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + mtt_index = mtt_seg->offset; + for (i = 0; i < npages; i++) { + vaddr = hmm_em_table_find(&comp_priv->mtt_em_table, mtt_index, &page_list[i]); + if (vaddr == NULL) { + pr_err("%s: Can't find va and pa of mtt entry, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + mtt_index += comp_priv->mtt_page_size / RDMA_PA_SIZE; + } + + return 0; +} + +static int hmm_write_mtt_chunk(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 mtt_level_index, + u32 start_index, u32 npages, const u64 *page_list) +{ + u32 i = 0; + u16 sign_val = 0; + __be64 *mtts = NULL; + + mtts = (__be64 *)hmm_em_table_find(&comp_priv->mtt_em_table, mtt->mtt_seg[mtt_level_index]->offset + start_index, + NULL); + if (mtts == NULL) { + pr_err("%s: Can't find va and pa of mtt entry, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } +#ifdef RDMA_SIGN_MTT_EN + sign_val = hmm_gen_mtt_sign(mtt->mtt_paddr, mtt->mtt_type); +#endif + for (i = 0; i < npages; i++) { + mtts[i] = cpu_to_be64(page_list[i] | RDMA_MTT_PA_VALID | (sign_val << 1)); + } + + return 0; +} + +static int hmm_write_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 mtt_level_index, + u32 start_index, u32 npages, u64 *page_list) +{ + int ret = 0; + u32 chunk = 0; + u32 mtts_per_page = 0; + u32 max_mtts_first_page = 0; + u32 tmp_npages = npages; + u32 tmp_start_index = start_index; + u64 *tmp_page_list = page_list; + + /* caculate how may mtts fit in the first page */ + mtts_per_page = comp_priv->mtt_page_size / RDMA_PA_SIZE; + max_mtts_first_page = mtts_per_page - ((mtt->mtt_seg[mtt_level_index]->offset + tmp_start_index) % mtts_per_page); + + chunk = (tmp_npages < max_mtts_first_page) ? tmp_npages : max_mtts_first_page; + + while ((int)tmp_npages > 0) { + ret = hmm_write_mtt_chunk(comp_priv, mtt, mtt_level_index, tmp_start_index, chunk, tmp_page_list); + if (ret != 0) { + pr_err("%s: Write mtt chunk failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + tmp_npages -= chunk; + tmp_start_index += chunk; + tmp_page_list += chunk; + + chunk = (tmp_npages < mtts_per_page) ? tmp_npages : mtts_per_page; + } + + return 0; +} + +static int hmm_alloc_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt_seg *mtt_seg) +{ + int ret = 0; + u32 seg_offset = 0; + u32 seg_order = 0; + u32 log_mtts_per_seg = 0; + + log_mtts_per_seg = comp_priv->rdma_cap.log_mtt_seg; + + seg_order = (mtt_seg->order > log_mtts_per_seg) ? (mtt_seg->order - log_mtts_per_seg) : 0; + mtt_seg->order = seg_order + log_mtts_per_seg; + + seg_offset = hmm_buddy_alloc(&comp_priv->mtt_buddy, seg_order); + if (seg_offset == HMM_INVALID_INDEX) { + pr_err("%s: Alloc mtt index failed\n", __FUNCTION__); + return -ENOMEM; + } + + mtt_seg->offset = seg_offset << log_mtts_per_seg; + + ret = hmm_em_table_get_range(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_seg->offset, + mtt_seg->offset + (u32)(1U << mtt_seg->order) - 1); + if (ret != 0) { + pr_err("%s: Alloc mtt entry failed, ret(%d)\n", __FUNCTION__, ret); + goto err_get_entry; + } + + mtt_seg->vaddr = hmm_em_table_find(&comp_priv->mtt_em_table, mtt_seg->offset, &mtt_seg->paddr); + if (mtt_seg->vaddr == NULL) { + pr_err("%s: Can't find start address of mtt_seg\n", __FUNCTION__); + goto err_find_entry; + } + + return 0; + +err_find_entry: + hmm_em_table_put_range(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_seg->offset, + mtt_seg->offset + (u32)(1U << mtt_seg->order) - 1); + +err_get_entry: + hmm_buddy_free(&comp_priv->mtt_buddy, seg_offset, seg_order); + + return -ENOMEM; +} + +static void hmm_free_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt_seg *mtt_seg) +{ + u32 seg_offset = 0; + u32 seg_order = 0; + int log_mtts_per_seg = 0; + + hmm_em_table_put_range(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_seg->offset, + mtt_seg->offset + (1U << mtt_seg->order) - 1); + + log_mtts_per_seg = (int)comp_priv->rdma_cap.log_mtt_seg; + seg_order = mtt_seg->order - (u32)log_mtts_per_seg; + seg_offset = mtt_seg->offset >> (unsigned int)log_mtts_per_seg; + + hmm_buddy_free(&comp_priv->mtt_buddy, seg_offset, seg_order); +} + +static int hmm_init_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 npages) +{ + u32 i; + int ret; + + if ((comp_priv == NULL) || (mtt == NULL)) { + pr_err("%s: Comp_priv or mtt is null\n", __FUNCTION__); + return -EINVAL; + } + + if (npages >= comp_priv->rdma_cap.num_mtts) { + pr_err("%s: Npages(0x%x) over range, ret(%d)\n", __FUNCTION__, npages, -EINVAL); + return -EINVAL; + } + + ret = hmm_set_mtt_layer(comp_priv, mtt, npages); + if (ret != 0) { + return ret; + } + + mtt->mtt_seg = (struct rdma_mtt_seg **)kzalloc(mtt->mtt_layers * sizeof(struct rdma_mtt_seg *), GFP_KERNEL); + if (mtt->mtt_seg == NULL) { + pr_err("%s: Alloc memory for mtt->mtt_seg failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + for (i = 0; i < mtt->mtt_layers; i++) { + mtt->mtt_seg[i] = (struct rdma_mtt_seg *)kzalloc(sizeof(struct rdma_mtt_seg), GFP_KERNEL); + if (mtt->mtt_seg[i] == NULL) { + pr_err("%s: Alloc memory for mtt->mtt_seg[i] failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + goto err_out; + } + } + + return 0; + +err_out: + for (i = 0; i < mtt->mtt_layers; i++) { + if (mtt->mtt_seg[i]) { + kfree(mtt->mtt_seg[i]); + mtt->mtt_seg[i] = NULL; + } + } + + kfree(mtt->mtt_seg); + mtt->mtt_seg = NULL; + + return -ENOMEM; +} + +static int hmm_rdma_mtt_alloc_prepare(void *hwdev, u32 npages, struct rdma_mtt *mtt, struct hmm_comp_priv **comp_priv, + u32 service_type) +{ + int ret = 0; + if ((hwdev == NULL) || (mtt == NULL)) { + pr_err("%s: Hwdev or mtt is null\n", __FUNCTION__); + return -EINVAL; + } + + *comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (*comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + ret = hmm_init_mtt_seg(*comp_priv, mtt, npages); + if (ret != 0) { + pr_err("%s: Initialize mtt_seg failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return ret; +} + +static int hmm_enable_mtt_related(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 low_layer_index) +{ + u64 *page_list = NULL; + struct rdma_mtt_seg *low_mtt_seg = NULL; + u32 npages = 0; + int ret = 0; + + low_mtt_seg = mtt->mtt_seg[low_layer_index]; + npages = (u32)((1UL << low_mtt_seg->order) / (comp_priv->mtt_page_size / RDMA_PA_SIZE)); + page_list = (u64 *)kzalloc(npages * RDMA_PA_SIZE, GFP_KERNEL); + if (page_list == NULL) { + pr_err("%s: Alloc memory for page_list failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + ret = hmm_find_mtt_page_list(comp_priv, low_mtt_seg, npages, page_list); + if (ret != 0) { + pr_err("%s: Can't find page_list of mtt_seg, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + + ret = hmm_write_mtt_seg(comp_priv, mtt, low_layer_index + 1, 0, npages, page_list); + if (ret != 0) { + pr_err("%s: Write mtt_seg failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + +out: + kfree(page_list); + + return ret; +} + +static void hmm_cleanup_mtt_seg(struct rdma_mtt *mtt) +{ + u32 i = 0; + + for (i = 0; i < mtt->mtt_layers; i++) { + if (mtt->mtt_seg[i]) { + kfree(mtt->mtt_seg[i]); + mtt->mtt_seg[i] = NULL; + } + } + + kfree(mtt->mtt_seg); + mtt->mtt_seg = NULL; +} + +int hmm_rdma_mtt_alloc(void *hwdev, u32 npages, u32 page_shift, struct rdma_mtt *mtt, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + int ret = 0; + u32 i = 0; + u32 cur_layer = 0; + u32 order = 0; + u32 tmp_npages = npages; + ret = hmm_rdma_mtt_alloc_prepare(hwdev, npages, mtt, &comp_priv, service_type); + if (ret != 0) { + return ret; + } + + for (cur_layer = 1; cur_layer <= mtt->mtt_layers; cur_layer++) { + tmp_npages = (tmp_npages < HMM_MTT_NUM_PER_CACHELINE) ? HMM_MTT_NUM_PER_CACHELINE : tmp_npages; + for (i = 1; i < tmp_npages; i <<= 1) { + order++; + } + + mtt->mtt_seg[cur_layer - 1]->order = order; + ret = hmm_alloc_mtt_seg(comp_priv, mtt->mtt_seg[cur_layer - 1]); + if (ret != 0) { + pr_err("%s: Alloc mtt_seg failed, npages(%d), ret(%d)\n", __FUNCTION__, tmp_npages, ret); + goto err_out; + } + + tmp_npages = (u32)(1U << mtt->mtt_seg[cur_layer - 1]->order) / (comp_priv->mtt_page_size / RDMA_PA_SIZE); + order = 0; + } + if (mtt->mtt_layers > 0) { + mtt->mtt_vaddr = (__be64 *)mtt->mtt_seg[mtt->mtt_layers - 1]->vaddr; + mtt->mtt_paddr = mtt->mtt_seg[mtt->mtt_layers - 1]->paddr; + } + for (i = 1; i < mtt->mtt_layers; i++) { + ret = hmm_enable_mtt_related(comp_priv, mtt, i - 1); + if (ret != 0) { + pr_err("%s: Cant't get multi mtt_seg related, i(%d), ret(%d)\n", __FUNCTION__, i, ret); + goto err_out; + } + } + mtt->buf_page_shift = page_shift; + mtt->mtt_page_shift = comp_priv->mtt_page_shift; + return 0; +err_out: + for (i = cur_layer - 1; i > 0; i--) { + hmm_free_mtt_seg(comp_priv, mtt->mtt_seg[i - 1]); + } + hmm_cleanup_mtt_seg(mtt); + return -ENOMEM; +} + +void hmm_rdma_mtt_free(void *hwdev, struct rdma_mtt *mtt, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + u32 i = 0; + + if ((hwdev == NULL) || (mtt == NULL)) { + pr_err("%s: Hwdev or mtt is null\n", __FUNCTION__); + return; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + if (mtt->mtt_layers == 0) { + return; + } + + for (i = 0; i < mtt->mtt_layers; i++) { + hmm_free_mtt_seg(comp_priv, mtt->mtt_seg[i]); + } + + hmm_cleanup_mtt_seg(mtt); +} + +int hmm_rdma_write_mtt(void *hwdev, struct rdma_mtt *mtt, u32 start_index, u32 npages, u64 *page_list, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mtt == NULL)) { + pr_err("%s: Hwdev or mtt is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + if (mtt->mtt_layers == 0) { + mtt->mtt_paddr = page_list[0]; + return 0; + } + + ret = hmm_write_mtt_seg(comp_priv, mtt, 0, start_index, npages, page_list); + if (ret != 0) { + pr_err("%s: Write mtt seg failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +int hmm_init_mtt_table(struct hmm_comp_priv *comp_priv) +{ + int ret = 0; + u32 i = 0; + u32 max_order = 0; + u32 mtt_num = 0; + u32 mtt_size = 0; + u32 log_mtts_per_seg = 0; + + mtt_num = comp_priv->rdma_cap.num_mtts; + log_mtts_per_seg = comp_priv->rdma_cap.log_mtt_seg; + mtt_size = comp_priv->rdma_cap.mtt_entry_sz; + + for (i = 1; i < mtt_num; i <<= 1) { + max_order++; + } + + max_order = (max_order > log_mtts_per_seg) ? (max_order - log_mtts_per_seg) : 0; + + ret = hmm_buddy_init(&comp_priv->mtt_buddy, max_order); + if (ret != 0) { + pr_err("%s: Initialize mtt's buddy failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + ret = hmm_em_init_table(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_size, mtt_num, 0, + (int)(comp_priv->mtt_page_shift - PAGE_SHIFT_4K)); + if (ret != 0) { + pr_err("%s: Initialize mtt's em_table failed, ret(%d)\n", __FUNCTION__, ret); + goto err_out; + } + + return 0; + +err_out: + hmm_buddy_cleanup(&comp_priv->mtt_buddy); + + return ret; +} + +void hmm_cleanup_mtt_table(struct hmm_comp_priv *comp_priv) +{ + hmm_em_cleanup_table(comp_priv->pdev, &comp_priv->mtt_em_table); + + hmm_buddy_cleanup(&comp_priv->mtt_buddy); +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mw_mr.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mw_mr.c new file mode 100644 index 000000000..d21fb9dbc --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mw_mr.c @@ -0,0 +1,222 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : implement the management of MPT, MTT +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "hmm_comp.h" + +static void hmm_roce_mpt_to_big_endian(struct roce_mpt_context *mpt_ctx) +{ + mpt_ctx->dw0.value = cpu_to_be32(mpt_ctx->dw0.value); + mpt_ctx->dw1.value = cpu_to_be32(mpt_ctx->dw1.value); + mpt_ctx->dw2.value = cpu_to_be32(mpt_ctx->dw2.value); + mpt_ctx->dw3.value = cpu_to_be32(mpt_ctx->dw3.value); + mpt_ctx->iova = cpu_to_be64(mpt_ctx->iova); + mpt_ctx->length = cpu_to_be64(mpt_ctx->length); + mpt_ctx->mtt_base_addr = cpu_to_be64(mpt_ctx->mtt_base_addr); + mpt_ctx->mtt_sz = cpu_to_be32(mpt_ctx->mtt_sz); +} + +static void hmm_set_roce_mr_access(struct roce_mpt_context *mpt_ctx, const struct rdma_mr *mr) +{ + mpt_ctx->dw0.bs.access_lr = 1; /* Local access enabled by default */ + + if ((RDMA_IB_ACCESS_LOCAL_WRITE & mr->access) != 0) { + mpt_ctx->dw0.bs.access_lw = 1; + } + if ((RDMA_IB_ACCESS_REMOTE_READ & mr->access) != 0) { + mpt_ctx->dw0.bs.access_rr = 1; + } + if ((RDMA_IB_ACCESS_REMOTE_WRITE & mr->access) != 0) { + mpt_ctx->dw0.bs.access_rw = 1; + } + if ((RDMA_IB_ACCESS_REMOTE_ATOMIC & mr->access) != 0) { + mpt_ctx->dw0.bs.access_ra = 1; + } + if ((RDMA_IB_ACCESS_MW_BIND & mr->access) != 0) { + mpt_ctx->dw0.bs.access_bind = 1; + } +} + +static void hmm_set_mptc_type_above_phy_mr(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + switch (mr->mr_type) { + case RDMA_PHYS_MR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_RSVD_LKEY: + mpt_ctx->dw0.bs.rkey = 1; + mpt_ctx->dw0.bs.bpd = 0; + mpt_ctx->dw0.bs.invalid_en = 0; + mpt_ctx->dw0.bs.remote_invalid_en = 0; + mpt_ctx->dw0.bs.pa = 1; + mpt_ctx->mtt_base_addr = 0; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_SIG_MR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + break; + + case RDMA_INDIRECT_MR: + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + break; + default: + pr_err("%s: RoCE unsupport mr type(%d)\n", __FUNCTION__, mr->mr_type); + break; + } +} + +static void hmm_set_mptc_type_below_phy_mr(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + switch (mr->mr_type) { + case RDMA_DMA_MR: + mpt_ctx->dw0.bs.pa = 1; + mpt_ctx->mtt_base_addr = 0; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_USER_MR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_FRMR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw0.bs.fast_reg_en = 1; + mpt_ctx->dw0.bs.remote_access_en = 1; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + mpt_ctx->mtt_sz = (mr->mtt.mtt_layers > 0) ? 1U << mr->mtt.mtt_seg[mr->mtt.mtt_layers - 1]->order : 0; + break; + + case RDMA_FMR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + default: + pr_err("%s: RoCE unsupport mr type(%d)\n", __FUNCTION__, mr->mr_type); + break; + } +} + +static void hmm_set_mptc_according_to_mr_type(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + if (mr->mr_type < RDMA_PHYS_MR) { + hmm_set_mptc_type_below_phy_mr(mpt_ctx, mr); + } else { + hmm_set_mptc_type_above_phy_mr(mpt_ctx, mr); + } +} + +static void hmm_set_roce_mr_cmd_buf(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + hmm_set_roce_mr_access(mpt_ctx, mr); + + mpt_ctx->dw0.bs.invalid_en = 1; + mpt_ctx->dw0.bs.remote_invalid_en = 1; + mpt_ctx->dw0.bs.r_w = RDMA_MPT_MR; + mpt_ctx->dw0.bs.bpd = 1; + mpt_ctx->dw2.bs.pdn = mr->pdn & 0x3ffff; + + if (mr->mr_type != RDMA_INDIRECT_MR) { + mpt_ctx->dw0.bs.mtt_page_size = + (mr->mtt.mtt_page_shift > PAGE_SHIFT_4K) ? (mr->mtt.mtt_page_shift - PAGE_SHIFT_4K) : 0; + mpt_ctx->dw0.bs.mtt_layer_num = mr->mtt.mtt_layers; + mpt_ctx->dw0.bs.buf_page_size = + (mr->mtt.buf_page_shift > PAGE_SHIFT_4K) ? (mr->mtt.buf_page_shift - PAGE_SHIFT_4K) : 0; + mpt_ctx->dw1.bs.dma_attr_idx = RDMA_MPT_DMA_ATTR_IDX; + mpt_ctx->dw1.bs.so_ro = 0; + mpt_ctx->dw2.bs.block_size = (mr->block_size / BLOCK_SIZE_DEVIDE_SECTOR) & 0x3f; + if (mr->block_size > 0) { + mpt_ctx->dw3.bs.page_mode = 1; + } + + mpt_ctx->iova = mr->iova; + mpt_ctx->length = mr->size; + mpt_ctx->dw3.bs.fbo = 0; + if ((mr->access & RDMA_IB_ACCESS_ZERO_BASED) != 0) { + mpt_ctx->dw0.bs.zbva = 1; + mpt_ctx->dw3.bs.fbo = mr->iova & PAGE_MASK; + mpt_ctx->iova = 0; + } + } else { + mpt_ctx->dw2.bs.indirect_mr = 1; + } + + mpt_ctx->dw3.bs.mkey = mr->key & 0xFF; + + hmm_set_mptc_according_to_mr_type(mpt_ctx, mr); + hmm_roce_mpt_to_big_endian(mpt_ctx); +} + +int hmm_rdma_disable_mr_mpt(void *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel) +{ + struct hmm_comp_priv *comp_priv = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mr == NULL)) { + pr_err("%s: Hwdev or mr is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + if (mr->enabled == RDMA_MPT_EN_HW) { + ret = hmm_disable_roce_mpt(comp_priv, &mr->mpt, channel); + if (ret != 0) { + pr_err("%s: Disable mr's mpt failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + mr->enabled = RDMA_MPT_EN_SW; + } + return 0; +} + +int hmm_rdma_enable_mr_mpt(void *hwdev, struct rdma_mr *mr, u16 channel) +{ + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct rdma_mpt_entry *mpt_entry = NULL; + struct rdma_mpt_sw2hw_inbuf *mpt_sw2hw_inbuf = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mr == NULL)) { + pr_err("%s: Hwdev or mr is null\n", __FUNCTION__); + return -EINVAL; + } + + cqm_cmd_inbuf = cqm_cmd_alloc(hwdev); + if (cqm_cmd_inbuf == NULL) { + pr_err("%s: Alloc cmd_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + cqm_cmd_inbuf->size = (u16)sizeof(struct rdma_mpt_sw2hw_inbuf); + mpt_sw2hw_inbuf = (struct rdma_mpt_sw2hw_inbuf *)cqm_cmd_inbuf->buf; + memset(mpt_sw2hw_inbuf, 0, sizeof(*mpt_sw2hw_inbuf)); + mpt_sw2hw_inbuf->com.dw0.bs.cmd_bitmask = (u16)cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + mpt_sw2hw_inbuf->com.index = cpu_to_be32(mr->mpt.mpt_index); + mpt_entry = &mpt_sw2hw_inbuf->mpt_entry; + + hmm_set_roce_mr_cmd_buf(&mpt_entry->roce_mpt_ctx, mr); + ret = hmm_enable_roce_mpt(hwdev, cqm_cmd_inbuf, channel); + if (ret != 0) { + pr_err("%s: Enable mr's mpt failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + mr->enabled = RDMA_MPT_EN_HW; +out: + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_res.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_res.c new file mode 100644 index 000000000..e6e2d541f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_res.c @@ -0,0 +1,63 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp_res.c + Version : Initial Draft + Description : implement the management of MPT, MTT +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "hmm_comp.h" + +int hmm_rdma_mpt_alloc(void *hwdev, struct rdma_mpt *mpt, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + struct rdma_mpt_entry *mpt_entry = NULL; + u32 mpt_entry_size = 0; + + if ((hwdev == NULL) || (mpt == NULL)) { + pr_err("%s: Hwdev or mpt is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + mpt_entry_size = comp_priv->rdma_cap.mpt_entry_sz; + + mpt->mpt_object = + (void *)cqm_object_qpc_mpt_create(hwdev, service_type, CQM_OBJECT_MPT, mpt_entry_size, mpt, CQM_INDEX_INVALID, + false); + if (mpt->mpt_object == NULL) { + pr_err("%s: Alloc mpt_object failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + mpt->mpt_index = ((cqm_qpc_mpt_s *)mpt->mpt_object)->xid; + mpt->vaddr = (void *)((cqm_qpc_mpt_s *)mpt->mpt_object)->vaddr; + if (!cqm_need_secure_mem(hwdev)) { + memset(mpt->vaddr, 0, sizeof(struct rdma_mpt_entry)); + + mpt_entry = (struct rdma_mpt_entry *)mpt->vaddr; + mpt_entry->roce_mpt_ctx.dw2.bs.status = RDMA_MPT_STATUS_MEM_INIT; + mpt_entry->roce_mpt_ctx.dw2.value = cpu_to_be32(mpt_entry->roce_mpt_ctx.dw2.value); + } + return 0; +} + + +void hmm_rdma_mpt_free(void *hwdev, struct rdma_mpt *mpt) +{ + if ((hwdev == NULL) || (mpt == NULL)) { + pr_err("%s: Hwdev or mpt is null\n", __FUNCTION__); + return; + } + hiudk_cqm_object_delete(hwdev, &((cqm_qpc_mpt_s *)mpt->mpt_object)->object); + mpt->vaddr = NULL; + mpt->mpt_object = NULL; + return; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.c new file mode 100644 index 000000000..8d52724d1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.c @@ -0,0 +1,348 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : management of entry + ***************************************************************************** */ +#include <linux/mm.h> +#include <linux/scatterlist.h> +#include <linux/slab.h> + +#include "hmm_em.h" + +static void hmm_em_chunk_free(struct pci_dev *pdev, struct hmm_em_chunk *em_chunk) +{ + struct hmm_em_buf *cur_buf = NULL; + struct hmm_em_buf *next_buf = NULL; + + cur_buf = &em_chunk->em_buf_list; + next_buf = cur_buf->next_buf; + + while (next_buf != NULL) { + cur_buf = next_buf; + next_buf = cur_buf->next_buf; + + if ((cur_buf->buf != NULL) && (cur_buf->length > 0)) { + memset(cur_buf->buf, 0, cur_buf->length); + dma_free_coherent(&pdev->dev, (unsigned long)cur_buf->length, cur_buf->buf, cur_buf->dma_addr); + cur_buf->buf = NULL; + cur_buf->length = 0; + } + + kfree(cur_buf); + cur_buf = NULL; + } + + kfree(em_chunk); +} + +static int hmm_em_chunk_alloc_npages(struct pci_dev *pdev, struct hmm_em_chunk *em_chunk, int min_order) +{ + int cur_order = 0; + int npages = 0; + unsigned int chunk_size = HMM_EM_CHUNK_SIZE; + struct hmm_em_buf* cur_buf = &em_chunk->em_buf_list; + struct hmm_em_buf* next_buf = NULL; + + cur_buf->next_buf = NULL; + cur_buf->length = 0; + cur_order = get_order(chunk_size); //lint !e834 !e587 + npages = (int)(1U << (unsigned int)cur_order); + while (npages > 0) { + if (next_buf == NULL) { + next_buf = (struct hmm_em_buf *)kzalloc(sizeof(struct hmm_em_buf), GFP_KERNEL); + if (next_buf == NULL) { + dev_err(&pdev->dev, "[HMM] %s: Alloc memory for em_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return (-ENOMEM); + } + + next_buf->length = 0; + next_buf->next_buf = NULL; + } + cur_buf->next_buf = next_buf; + + next_buf->buf = dma_alloc_coherent(&pdev->dev, (size_t)HMM_EM_PAGE_SIZE << (unsigned int)cur_order, + &next_buf->dma_addr, GFP_KERNEL); + if (next_buf->buf == NULL) { + cur_order--; + if (cur_order < min_order) { + dev_err(&pdev->dev, "[HMM] %s:em_chunk alloc dma buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return (-ENOMEM); + } else { + dev_err(&pdev->dev, "[HMM, WARN] %s: em_chunk alloc %d o dma failed. cont alloc small mem.\n", + __FUNCTION__, cur_order); + continue; + } + } + + next_buf->length = (u32)HMM_EM_PAGE_SIZE << (unsigned int)cur_order; + em_chunk->buf_num++; + npages -= (int)(1U << (unsigned int)cur_order); + + cur_buf = next_buf; + next_buf = NULL; + } + + return 0; +} +static struct hmm_em_chunk *hmm_em_chunk_alloc(struct pci_dev *pdev, int min_order) +{ + struct hmm_em_chunk *em_chunk = NULL; + int ret; + + em_chunk = (struct hmm_em_chunk *)kzalloc(sizeof(struct hmm_em_chunk), GFP_KERNEL); + if (em_chunk == NULL) { + dev_err(&pdev->dev, "[HMM] %s: Alloc memory for em_chunk failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return (struct hmm_em_chunk *)ERR_PTR((long)-ENOMEM); + } + + em_chunk->buf_num = 0; + ret = hmm_em_chunk_alloc_npages(pdev, em_chunk, min_order); + if (ret != 0) { + hmm_em_chunk_free(pdev, em_chunk); + return (struct hmm_em_chunk *)ERR_PTR((long)ret); + } + + em_chunk->refcount = 0; + + return em_chunk; +} + +static void hmm_em_table_put(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj) +{ + u32 i = 0; + + if (obj >= em_table->obj_num) { + dev_err(&pdev->dev, "[HMM] %s: Obj over range, obj(0x%x), max(0x%x)\n", __FUNCTION__, obj, + em_table->obj_num - 1); + return; + } + + i = obj / (HMM_EM_CHUNK_SIZE / em_table->obj_size); + + mutex_lock(&em_table->mutex); + + if ((em_table->em_chunk[i] == NULL) || (IS_ERR(em_table->em_chunk[i]))) { + dev_err(&pdev->dev, "[HMM] %s: Em_table->em_chunk[%d] not alloced, obj(0x%x)\n", __FUNCTION__, i, obj); + mutex_unlock(&em_table->mutex); + return; + } + + if (em_table->em_chunk[i]->refcount == 1) { + em_table->em_chunk[i]->refcount = 0; + hmm_em_chunk_free(pdev, em_table->em_chunk[i]); + em_table->em_chunk[i] = NULL; + } else { + --em_table->em_chunk[i]->refcount; + } + + mutex_unlock(&em_table->mutex); +} + +static int hmm_em_table_get(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj) +{ + int ret = 0; + u32 i; + + if (obj >= em_table->obj_num) { + dev_err(&pdev->dev, "[HMM] %s: Obj over range, obj(0x%x), max(0x%x)\n", __FUNCTION__, obj, + em_table->obj_num - 1); + return -EINVAL; + } + + i = obj / (HMM_EM_CHUNK_SIZE / em_table->obj_size); + + mutex_lock(&em_table->mutex); + + if (em_table->em_chunk[i]) { + ++em_table->em_chunk[i]->refcount; + goto out; + } + + em_table->em_chunk[i] = hmm_em_chunk_alloc(pdev, em_table->min_order); + if (IS_ERR(em_table->em_chunk[i])) { + ret = (int)PTR_ERR(em_table->em_chunk[i]); + dev_err(&pdev->dev, "[HMM] %s: Alloc em_chunk failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + + ++em_table->em_chunk[i]->refcount; + +out: + mutex_unlock(&em_table->mutex); + + return ret; +} + +void *hmm_em_table_find(struct hmm_em_table *em_table, u32 obj, dma_addr_t *dma_handle) +{ + void *vaddr = NULL; + struct hmm_em_chunk *em_chunk = NULL; + struct hmm_em_buf *cur_buf = NULL; + struct hmm_em_buf *next_buf = NULL; + u64 table_offset; + u32 offset; + + if (em_table == NULL) { + pr_err("%s: Em_table is null, err(%d)\n", __FUNCTION__, -EINVAL); + return NULL; + } + + if (obj >= em_table->obj_num) { + pr_err("%s: Obj over range, obj(0x%x), max(0x%x)\n", __FUNCTION__, obj, em_table->obj_num - 1); + return NULL; + } + + mutex_lock(&em_table->mutex); + + table_offset = (u64)obj * em_table->obj_size; + em_chunk = em_table->em_chunk[table_offset / HMM_EM_CHUNK_SIZE]; + offset = table_offset % HMM_EM_CHUNK_SIZE; + + if (em_chunk == NULL) { + pr_err("%s: Em_chunk has not been alloced, err(%d)\n", __FUNCTION__, -EINVAL); + goto err_out; + } + + cur_buf = &em_chunk->em_buf_list; + next_buf = cur_buf->next_buf; + + while (next_buf != NULL) { + cur_buf = next_buf; + if (offset < cur_buf->length) { + if (dma_handle) { + *dma_handle = cur_buf->dma_addr + offset; + } + + vaddr = (void *)((char *)(cur_buf->buf) + offset); + mutex_unlock(&em_table->mutex); + return vaddr; + } + + offset -= cur_buf->length; + next_buf = cur_buf->next_buf; + } + +err_out: + mutex_unlock(&em_table->mutex); + + return NULL; +} + +void hmm_em_table_put_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end) +{ + int i = 0; + int inc = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null, err(%d)\n", __FUNCTION__, -EINVAL); + return; + } + + inc = (int)(HMM_EM_CHUNK_SIZE / em_table->obj_size); + for (i = (int)start; i <= (int)end; i += inc) { + hmm_em_table_put(pdev, em_table, (u32)i); + } + + return; +} + +int hmm_em_table_get_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end) +{ + int ret = 0; + int i = 0; + int inc = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null, err(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + inc = (int)(HMM_EM_CHUNK_SIZE / em_table->obj_size); + + for (i = (int)start; i <= (int)end; i += inc) { + ret = hmm_em_table_get(pdev, em_table, (u32)i); + if (ret != 0) { + dev_err(&pdev->dev, "[HMM] %s: Get entry failed, start(%d), end(%d), i(%d), ret(%d)\n", __FUNCTION__, start, + end, i, ret); + goto err_out; + } + } + + return 0; + +err_out: + while (i > (int)start) { + i -= inc; + hmm_em_table_put(pdev, em_table, (u32)i); + } + + return ret; +} + +int hmm_em_init_table(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj_size, u32 nobj, u32 reserved_bot, + int min_order) +{ + u32 obj_per_chunk = 0; + u32 chunk_num = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null\n", __FUNCTION__); + return -EINVAL; + } + + if (nobj == 0) { + dev_err(&pdev->dev, "[HMM] %s: Nobj is invalid\n", __FUNCTION__); + return -EINVAL; + } + + /*lint -e587 */ + if (nobj != HMM_EM_ROUNDUP_POW_OF_TWO(nobj)) { + dev_err(&pdev->dev, "[HMM] %s: Obj isn't pow of two, nobj(0x%x)\n", __FUNCTION__, nobj); + return -EINVAL; + } + + if (obj_size != HMM_EM_ROUNDUP_POW_OF_TWO(obj_size)) { + dev_err(&pdev->dev, "[HMM] %s: Obj_size isn't pow of two, obj_size(0x%x)\n", __FUNCTION__, obj_size); + return -EINVAL; + } + /*lint +e587 */ + + obj_per_chunk = HMM_EM_CHUNK_SIZE / obj_size; + chunk_num = (nobj + obj_per_chunk - 1) / obj_per_chunk; + + em_table->em_chunk = (struct hmm_em_chunk **)kcalloc((size_t)chunk_num, sizeof(struct hmm_em_chunk *), GFP_KERNEL); + if (em_table->em_chunk == NULL) { + dev_err(&pdev->dev, "[HMM] %s: Em_table->em_chunk create failed\n", __FUNCTION__); + return -ENOMEM; + } + + em_table->chunk_num = chunk_num; + em_table->obj_num = nobj; + em_table->obj_size = obj_size; + em_table->min_order = min_order; + + mutex_init(&em_table->mutex); + + return 0; +} + +void hmm_em_cleanup_table(struct pci_dev *pdev, struct hmm_em_table *em_table) +{ + u32 i = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null\n", __FUNCTION__); + return; + } + + for (i = 0; i < em_table->chunk_num; i++) { + if (em_table->em_chunk[i]) { + hmm_em_chunk_free(pdev, em_table->em_chunk[i]); + em_table->em_chunk[i] = NULL; + } + } + + kfree(em_table->em_chunk); + em_table->em_chunk = NULL; + + return; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.h new file mode 100644 index 000000000..4523ae863 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + * Description : structure and interface about management of entry + */ + +#ifndef HMM_EM_H +#define HMM_EM_H + +#include <linux/pci.h> +#include <linux/mutex.h> +#include "hmm_umem.h" + +#define HMM_EM_CHUNK_SIZE (1 << 21) +#define HMM_EM_PAGE_SIZE PAGE_SIZE // (4096UL) + +#define HMM_EM_ROUNDUP_POW_OF_TWO roundup_pow_of_two + +struct hmm_em_buf { + u32 length; + void *buf; + dma_addr_t dma_addr; + struct hmm_em_buf *next_buf; +}; + +struct hmm_em_chunk { + u32 buf_num; + u32 refcount; + struct hmm_em_buf em_buf_list; +}; + +struct hmm_em_table { + u32 chunk_num; + u32 obj_num; + u32 obj_size; + int min_order; + struct mutex mutex; + struct hmm_em_chunk **em_chunk; +}; + + +void *hmm_em_table_find(struct hmm_em_table *em_table, u32 obj, dma_addr_t *dma_handle); +void hmm_em_table_put_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end); +int hmm_em_table_get_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end); +int hmm_em_init_table(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj_size, u32 nobj, u32 reserved_bot, + int min_order); +void hmm_em_cleanup_table(struct pci_dev *pdev, struct hmm_em_table *em_table); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.c new file mode 100644 index 000000000..5cca85f14 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.c @@ -0,0 +1,403 @@ +/* ***************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : implement the verbs of momory region +***************************************************************************** */ +#include <linux/pci.h> +#include <linux/dma-mapping.h> +#include <linux/vmalloc.h> +#include <linux/semaphore.h> + +#include "hinic3_crm.h" +#include "hmm_umem.h" +#include "hmm_comp.h" +#include "hinic3_hmm.h" +#include "hmm_mr.h" + +/* **************************************************************************** + Prototype : get_key_from_index + Description : mr key的计算算法，通过index移位计算得到 + Input : u32 mpt_index + Output : None +**************************************************************************** */ +static u32 get_key_from_index(u32 mpt_index) +{ + return (mpt_index >> MR_KEY_RIGHT_SHIFT_OFS) | (mpt_index << MR_KEY_LEFT_SHIFT_OFS); +} + +/* **************************************************************************** + Prototype : hmm_alloc_tpt + Description : alloc mpt and mtt + Input : struct hinic3_hwdev *hwdev + struct rdma_mr *mr + u32 npages + u32 page_shift + Output : None +**************************************************************************** */ +static int hmm_alloc_tpt(struct hinic3_hwdev *hwdev, struct rdma_mr *mr, u32 npages, u32 page_shift, u32 service_type) +{ + int ret; + + ret = hmm_rdma_mpt_alloc(hwdev, &mr->mpt, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mpt, ret(%d), func_id(%d)\n", __func__, __LINE__, + ret, hinic3_global_func_id(hwdev)); + return ret; + } + mr->enabled = RDMA_MPT_EN_SW; + + /* npages = 0 or 1, means not need mtt */ + ret = hmm_rdma_mtt_alloc(hwdev, npages, page_shift, &mr->mtt, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mtt, ret(%d), func_id(%d)\n", __func__, __LINE__, + ret, hinic3_global_func_id(hwdev)); + goto err_alloc_mtt; + } + return 0; + +err_alloc_mtt: + hmm_rdma_mpt_free(hwdev, &mr->mpt); + mr->enabled = HMM_MPT_DISABLED; + + return ret; +} + +/* **************************************************************************** + Prototype : hmm_free_tpt + Description : free mpt and mtt + Input : struct hinic3_hwdev *hwdev + struct rdma_mr *mr +**************************************************************************** */ +void hmm_free_tpt(void *hwdev, struct rdma_mr *mr, u32 service_type) +{ + hmm_rdma_mtt_free(hwdev, &mr->mtt, service_type); + hmm_rdma_mpt_free(hwdev, &mr->mpt); + mr->enabled = HMM_MPT_DISABLED; +} + +/* **************************************************************************** + Prototype : hmm_set_rdma_mr + Description : set the member of rdma_mr + Input : struct rdma_mr *mr + enum rdma_mr_type mr_type + u32 pdn + u64 iova + u64 size + u32 access + Output : None +**************************************************************************** */ +static void hmm_set_rdma_mr(struct rdma_mr *mr, enum rdma_mr_type mr_type, u32 pdn, u64 iova, u64 size, u32 access) +{ + mr->iova = iova; + mr->size = size; + mr->pdn = pdn; + mr->access = access; + mr->key = get_key_from_index(mr->mpt.mpt_index); /* 由mpt index转换为key */ + mr->mr_type = mr_type; +} + +/* **************************************************************************** + Prototype : hmm_alloc_mr + Description : register DMA_MR + Input : struct hinic3_hwdev *hwdev + enum rdma_mr_type mr_type + u32 max_num_sg + u32 service_type + Output : None +**************************************************************************** */ +struct hmm_mr *hmm_alloc_mr(struct hinic3_hwdev *hwdev, u32 pdn, enum rdma_mr_type mr_type, u32 max_num_sg, + u32 service_type, u16 channel) +{ + u32 access_flag; + int ret = 0; + struct hmm_mr *mr = NULL; + + if (hwdev == NULL) { + ret = -EINVAL; + pr_err("[HMM, ERR] %s(%d): dev is null\n", __func__, __LINE__); + goto err_out; + } +#ifndef PANGEA_V6 + if (mr_type != RDMA_DMA_MR && mr_type != RDMA_INDIRECT_MR) { +#else + if (mr_type != RDMA_DMA_MR) { +#endif + ret = -EINVAL; + pr_err("[HMM, ERR] %s(%d): mr_type is invalid\n", __func__, __LINE__); + goto err_out; + } + + mr = (struct hmm_mr *)kzalloc(sizeof *mr, GFP_KERNEL); + if (mr == NULL) { + ret = -ENOMEM; + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc memory for dma mr, func_id(%d)\n", __func__, + __LINE__, hinic3_global_func_id(hwdev)); + goto err_out; + } + + ret = hmm_alloc_tpt(hwdev->dev_hdl, &mr->rdmamr, 0, 0, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mpt and mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_alloc_tpt; + } + + access_flag = (RDMA_IB_ACCESS_REMOTE_READ | RDMA_IB_ACCESS_REMOTE_WRITE | RDMA_IB_ACCESS_LOCAL_WRITE | + RDMA_IB_ACCESS_REMOTE_ATOMIC); + + hmm_set_rdma_mr(&mr->rdmamr, mr_type, pdn, 0ULL, ROCE_DMA_MR_SIZE, access_flag); + + ret = hmm_rdma_enable_mr_mpt(hwdev->dev_hdl, &(mr->rdmamr), channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to enable mpt of DMA mr, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_enable_mpt; + } + + return mr; + +err_enable_mpt: + hmm_free_tpt(hwdev->dev_hdl, &mr->rdmamr, service_type); + +err_alloc_tpt: + kfree(mr); + +err_out: + return (struct hmm_mr *)ERR_PTR((long)ret); +} + +static int hmm_umem_write_mtt_check(const void *hwdev, const struct rdma_mtt *mtt, const struct hmm_umem *umem) +{ + if ((hwdev == NULL) || (mtt == NULL) || (umem == NULL)) { + pr_err("[HMM, ERR] %s(%d): hwdev or mtt or umem is null\n", __func__, __LINE__); + return -EINVAL; + } + return 0; +} + +static int hmm_umem_write_mtt_update(struct hinic3_hwdev *hwdev, struct rdma_mtt *mtt, + struct hmm_umem *umem, u64 *page_list, u32 service_type) +{ + int ret = 0; + int i = 0; + u32 j = 0; + u32 pages_in_chunk = 0; /* umem_chunk中单个内存块的页个数 */ + u32 npages = 0; /* 已经记录的页个数 */ + u32 start_index = 0; /* 要写入mtt的页 */ + struct scatterlist *sg = NULL; + u64 page_size = 0; + + page_size = BIT((unsigned int)umem->page_shift); + for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) + { + /* cal page num in truck */ + pages_in_chunk = sg_dma_len(sg) >> mtt->buf_page_shift; + for (j = 0; j < pages_in_chunk; ++j) { + page_list[npages] = sg_dma_address(sg) + (page_size * j); + npages++; + + /* one page can hold (PAGE_SIZE / sizeof(u64)) addrs */ + if (npages == (PAGE_SIZE / sizeof(u64))) { + ret = hmm_rdma_write_mtt(hwdev, mtt, start_index, npages, page_list, service_type); + start_index += npages; + npages = 0; + } + if ((npages == (PAGE_SIZE / sizeof(u64))) && (ret != 0)) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to write mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto out; + } + } + } + + if (npages != 0) { + ret = hmm_rdma_write_mtt(hwdev, mtt, start_index, npages, page_list, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to write mtt, ret(%d), start_index(%d), func_id(%d)\n", + __func__, __LINE__, ret, start_index, hinic3_global_func_id(hwdev)); + goto out; + } + } + +out: + kfree(page_list); + + return ret; +} + +/* **************************************************************************** + Prototype : hmm_umem_write_mtt + Description : write mtt for umem(get from memory alloced by user) + Input : struct hinic3_hwdev *hwdev + struct rdma_mtt *mtt + struct hmm_umem *umem + Output : None +**************************************************************************** */ +int hmm_umem_write_mtt(struct hinic3_hwdev *hwdev, struct rdma_mtt *mtt, struct hmm_umem *umem, u32 service_type) +{ + int ret; + u64 *page_list = NULL; /* 要写入mtt的page_list */ + + ret = hmm_umem_write_mtt_check(hwdev, mtt, umem); + if (ret != 0) { + return ret; + } + page_list = (u64 *)kzalloc(PAGE_SIZE, GFP_KERNEL); + if (page_list == NULL) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc memory for page list, func_id(%d)\n", __func__, + __LINE__, hinic3_global_func_id(hwdev)); + return -ENOMEM; + } + ret = hmm_umem_write_mtt_update(hwdev, mtt, umem, page_list, service_type); + return ret; +} + +int hmm_reg_user_mr_update(struct hinic3_hwdev *hwdev, struct hmm_mr *mr, u32 pdn, u64 length, u64 virt_addr, + int access, u32 service_type, u16 channel) +{ + int ret = 0; + u32 npages = 0; + u32 page_shift = 0; + + if (hwdev == NULL) { + pr_err("[HMM, ERR] %s(%d): hwdev is null\n", __func__, __LINE__); + return 0; + } + mr->rdmamr.mtt.mtt_type = MTT_DMTT_TYPE; + npages = (u32)hmm_umem_page_count(mr->umem); + page_shift = (u32)(mr->umem->page_shift); + ret = hmm_alloc_tpt(hwdev, &mr->rdmamr, npages, page_shift, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mpt and mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_alloc_tpt; + } + + hmm_set_rdma_mr(&mr->rdmamr, RDMA_USER_MR, pdn, virt_addr, length, (u32)access); + + ret = hmm_umem_write_mtt(hwdev, &mr->rdmamr.mtt, mr->umem, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to write mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_write_mtt; + } + + ret = hmm_rdma_enable_mr_mpt(hwdev, &mr->rdmamr, channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to enable mpt of user mr, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_write_mtt; + } + + return 0; + +err_write_mtt: + hmm_free_tpt(hwdev, &mr->rdmamr, service_type); + +err_alloc_tpt: + return ret; +} + +int hmm_dereg_mr_update(struct hinic3_hwdev *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel) +{ + int ret = 0; + ret = hmm_rdma_disable_mr_mpt(hwdev, mr, service_type, channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to disable mpt of mr, ret(%d)\n", __func__, __LINE__, ret); + return ret; + } + + hmm_free_tpt(hwdev, mr, service_type); + return ret; +} + +#ifndef ROCE_SERVICE +/* **************************************************************************** + Prototype : hmm_reg_user_mr + Description : register MR for user + Input : struct hinic3_hwdev *hwdev + u64 start + u64 length + u64 virt_addr + int hmm_acess + Output : None +**************************************************************************** */ +struct hmm_mr *hmm_reg_user_mr(struct hinic3_hwdev *hwdev, u64 start, u32 pd, u64 length, u64 virt_addr, int hmm_acess, + u32 service_type, u16 channel) +{ + int ret = 0; + struct hmm_mr *mr = NULL; + + if (hwdev == NULL) { + pr_err("[HMM, ERR] %s(%d): hwdev is null\n", __func__, __LINE__); + goto err_out; + } + + mr = (struct hmm_mr *)kzalloc(sizeof(*mr), GFP_KERNEL); + if (mr == NULL) { + ret = -ENOMEM; + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc memory for roce mr, func_id(%d)\n", __func__, + __LINE__, hinic3_global_func_id(hwdev)); + goto err_out; + } + + mr->hwdev = hwdev; + mr->rdmamr.iova = virt_addr; + mr->umem = hmm_umem_get(hwdev->dev_hdl, start, (size_t)length, hmm_acess, 0); + if (IS_ERR(mr->umem)) { + ret = (int)PTR_ERR(mr->umem); + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to get ib umem, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_empty; + } + + rcu_read_lock(); + mr->umem->context->tgid = get_task_pid(current->group_leader, PIDTYPE_PID); + rcu_read_unlock(); + ret = hmm_reg_user_mr_update(hwdev, mr, pd, length, virt_addr, hmm_acess, service_type, channel); + if (ret != 0) { + goto err_get_umem; + } + return mr; + +err_get_umem: + hmm_umem_release(mr->umem); +err_empty: + kfree(mr); + +err_out: + return (struct hmm_mr *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : hmm_dereg_mr + Description : dereg DMA_MR, user_MR or FRMR + Input : struct hmm_mr *mr + Output : None + +**************************************************************************** */ +int hmm_dereg_mr(struct hmm_mr *mr, u32 service_type, u16 channel) +{ + int ret = 0; + struct hinic3_hwdev *hwdev = NULL; + + if (mr == NULL) { + pr_err("[HMM, ERR] %s(%d): Ibmr is null\n", __func__, __LINE__); + return -EINVAL; + } + + hwdev = (struct hinic3_hwdev *)mr->hwdev; + ret = hmm_dereg_mr_update(hwdev, &(mr->rdmamr), service_type, channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to de-reg mr update, ret(%d), func_id(%d)\n", __func__, __LINE__, + ret, hinic3_global_func_id(hwdev)); + return ret; + } + + if (mr->umem) { + hmm_umem_release(mr->umem); + } + kfree(mr); + return ret; +} +#endif + diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.h new file mode 100644 index 000000000..dfcae013c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + * Description : structure related to mr + */ + +#ifndef HMM_MR_H +#define HMM_MR_H + +#include "hmm_umem.h" +#include "hmm_comp.h" + + +#define ROCE_DMA_MR_SIZE (~0ULL) +#define ROCE_FRMR_MAX_PAGES 512 +#define MR_KEY_RIGHT_SHIFT_OFS 24 +#define MR_KEY_LEFT_SHIFT_OFS 8 + +struct hmm_mr { + struct hmm_umem *umem; + struct rdma_mr rdmamr; + void *hwdev; +}; + +int hmm_rdma_enable_mr_mpt(void *hwdev, struct rdma_mr *mr, u16 channel); + +int hmm_rdma_disable_mr_mpt(void *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel); + +void hmm_rdma_mpt_free(void *hwdev, struct rdma_mpt *mpt); + +int hmm_init_resource(void *hwdev, u32 service_type); + +void hmm_cleanup_resource(void *hwdev, u32 service_type); + +#endif // HMM_MR_H_ diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.c new file mode 100644 index 000000000..944a86203 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.c @@ -0,0 +1,322 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : get the dma sglist from virtal memory address +***************************************************************************** */ + +#include <linux/mm.h> +#include <linux/dma-mapping.h> +#include <linux/signal.h> +#include <linux/sched/mm.h> +#include <linux/sched/signal.h> +#include <linux/hugetlb.h> +#include <linux/slab.h> +#include <linux/version.h> +#include "hinic3_rdma.h" +#include "hmm_umem.h" + +#ifndef ROCE_SERVICE +static void hmm_umemsg_release(struct device *device, struct hmm_umem *hmm_umem, int dirty) +{ + struct scatterlist *sg = NULL; + struct page *page = NULL; + int i; + + if (hmm_umem->nmap > 0) + dma_unmap_sg(device, hmm_umem->sg_head.sgl, hmm_umem->npages, DMA_BIDIRECTIONAL); + + for_each_sg(hmm_umem->sg_head.sgl, sg, hmm_umem->npages, i) + { + page = sg_page(sg); + if (!PageDirty(page) && hmm_umem->writable && dirty) + set_page_dirty_lock(page); + put_page(page); + } + + sg_free_table(&hmm_umem->sg_head); + return; +} + +/** + * hmm_umem_get - Pin and DMA map userspace memory. + * + * If access flags indicate ODP memory, avoid pinning. Instead, stores + * the mm for future page fault handling in conjunction with MMU notifiers. + * + * @context: userspace context to pin memory for + * @addr: userspace virtual address to start at + * @size: length of region to pin + * @access: RDMA_IB_ACCESS_xxx flags for memory being pinned + * @dmasync: flush in-flight DMA when the memory region is written + */ +struct hmm_umem *hmm_umem_get(struct device *device, unsigned long addr, size_t size, int access, int dmasync) +{ + int ret; + int i; + struct hmm_umem *hmem = NULL; + struct page **page_list = NULL; + struct vm_area_struct **vma_list = NULL; + unsigned long locked_pages; + unsigned long lock_limit; + unsigned long current_base; + unsigned long npages; + +#ifdef HAVE_STRUCT_DMA_ATTRS + DEFINE_DMA_ATTRS(dma_attrs); +#else + unsigned long dma_attrs = 0; +#endif + struct scatterlist *sg = NULL, *sg_list_start = NULL; + int need_release = 0; +#ifdef HAVE_GET_USER_PAGES_GUP_FLAGS + unsigned int gup_flags = FOLL_WRITE; +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0) + if (dmasync) +#ifdef HAVE_STRUCT_DMA_ATTRS + dma_set_attr(DMA_ATTR_WRITE_BARRIER, &dma_attrs); +#else + dma_attrs |= DMA_ATTR_WRITE_BARRIER; +#endif +#endif + + /* + * If the combination of the addr and size requested for this memory + * region causes an integer overflow, return error. + */ + if (((addr + size) < addr) || PAGE_ALIGN(addr + size) < (addr + size)) { + return ERR_PTR(-EINVAL); + } + + if (can_do_mlock() == 0) { + return ERR_PTR(-EPERM); + } + + hmem = kzalloc(sizeof *hmem, GFP_KERNEL); + if (hmem == NULL) { + return ERR_PTR(-ENOMEM); + } + hmem->context = kzalloc(sizeof(*(hmem->context)), GFP_KERNEL); + if ((hmem->context) == NULL) { + kfree(hmem); + return ERR_PTR(-ENOMEM); + } + hmem->context->device = device; + hmem->length = size; + hmem->address = addr; + hmem->page_shift = PAGE_SHIFT; + /* + * We ask for writable memory if any of the following + * access flags are set. "Local write" and "remote write" + * obviously require write access. "Remote atomic" can do + * things like fetch and add, which will modify memory, and + * "MW bind" can change permissions by binding a window. + */ + hmem->writable = !!(access & (RDMA_IB_ACCESS_LOCAL_WRITE | RDMA_IB_ACCESS_REMOTE_WRITE | + RDMA_IB_ACCESS_REMOTE_ATOMIC | RDMA_IB_ACCESS_MW_BIND)); + + if ((access & RDMA_IB_ACCESS_ON_DEMAND) != 0) { + kfree(hmem->context); + kfree(hmem); + dev_err(device, "[HMM, ERR] %s(%d): don't support odp \n", __func__, __LINE__); + return ERR_PTR(-ENOMEM); + } + hmem->odp_data = NULL; + + /* We assume the memory is from hugetlb until proved otherwise */ + hmem->hugetlb = 1; + page_list = (struct page **)__get_free_page(GFP_KERNEL); + if (page_list == NULL) { + kfree(hmem->context); + kfree(hmem); + return ERR_PTR(-ENOMEM); + } + + /* + * if we can't alloc the vma_list, it's not so bad; + * just assume the memory is not hugetlb memory + */ + vma_list = (struct vm_area_struct **)__get_free_page(GFP_KERNEL); + if (vma_list == NULL) { + hmem->hugetlb = 0; + } + npages = hmm_umem_num_pages(hmem); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + down_write(¤t->mm->mmap_sem); +#else + mmap_write_lock(current->mm); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) + locked_pages = npages + current->mm->pinned_vm; +#else + locked_pages = npages + atomic64_read(¤t->mm->pinned_vm); +#endif + lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; + if ((locked_pages > lock_limit) && !capable(CAP_IPC_LOCK)) { + ret = -ENOMEM; + goto out; + } + current_base = addr & PAGE_MASK; + if (npages == 0 || npages > UINT_MAX) { + ret = -EINVAL; + goto out; + } + ret = sg_alloc_table(&hmem->sg_head, (unsigned int)npages, GFP_KERNEL); + if (ret != 0) { + goto out; + } + +#ifdef HAVE_GET_USER_PAGES_GUP_FLAGS + if (hmem->writable == 0) { + gup_flags |= FOLL_FORCE; + } +#endif + + need_release = 1; + sg_list_start = hmem->sg_head.sgl; + + while (npages != 0) { +#ifdef HAVE_GET_USER_PAGES_8_PARAMS + ret = get_user_pages(current, current->mm, current_base, + min_t(unsigned long, npages, PAGE_SIZE / sizeof(struct page *)), 1, !hmem->writable, page_list, vma_list); +#else +#ifdef HAVE_GET_USER_PAGES_LONGTERM +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ret = get_user_pages(current_base, +#else + ret = get_user_pages_longterm(current_base, +#endif +#else + ret = get_user_pages(current_base, +#endif + min_t(unsigned long, npages, PAGE_SIZE / sizeof(struct page *)), +#ifdef HAVE_GET_USER_PAGES_GUP_FLAGS + gup_flags, page_list, vma_list); +#else + 1, !hmem->writable, page_list, vma_list); +#endif +#endif + + if (ret < 0) { + goto out; + } + hmem->npages += ret; + current_base += ret * PAGE_SIZE; + npages = (unsigned long)(npages - ret); + + for_each_sg(sg_list_start, sg, ret, i) + { + if (vma_list != NULL && !is_vm_hugetlb_page(vma_list[i])) { + hmem->hugetlb = 0; + } + sg_set_page(sg, page_list[i], PAGE_SIZE, 0); + } + + /* preparing for next loop */ + sg_list_start = sg; + } + + hmem->nmap = dma_map_sg_attrs(device, hmem->sg_head.sgl, hmem->npages, DMA_BIDIRECTIONAL, +#ifdef HAVE_STRUCT_DMA_ATTRS + &dma_attrs); +#else + dma_attrs); +#endif + if (hmem->nmap <= 0) { + ret = -ENOMEM; + goto out; + } + ret = 0; + +out: + if (ret < 0) { + if (need_release != 0) { + hmm_umemsg_release(device, hmem, 0); + } + kfree(hmem->context); + kfree(hmem); + } else { +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) + current->mm->pinned_vm = locked_pages; +#else + atomic64_set(¤t->mm->pinned_vm, locked_pages); +#endif + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + up_write(¤t->mm->mmap_sem); +#else + mmap_write_unlock(current->mm); +#endif + if (vma_list != NULL) { + free_page((unsigned long)(uintptr_t)vma_list); + } + free_page((unsigned long)(uintptr_t)page_list); + return (ret < 0) ? ERR_PTR(ret) : hmem; +} + +/** + * hmm_umem_release - release memory pinned with ib_umem_get + * @hmem: umem struct to release + */ +void hmm_umem_release(struct hmm_umem *hmem) +{ + struct ib_ucontext *context = hmem->context; + struct mm_struct *mm = NULL; + struct task_struct *task = NULL; + unsigned long diff; + + if (hmem->odp_data) { + pr_err("[HMM, ERR] %s(%d): Don't support odp \n", __func__, __LINE__); + return; + } + + hmm_umemsg_release(context->device, hmem, 1); + task = get_pid_task(context->tgid, PIDTYPE_PID); + if (task == NULL) { + goto out; + } + mm = get_task_mm(task); + put_task_struct(task); + if (mm == NULL) { + goto out; + } + + diff = hmm_umem_num_pages(hmem); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + down_write(&mm->mmap_sem); +#else + mmap_write_lock(mm); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) + mm->pinned_vm -= diff; +#else + atomic64_sub(diff, &mm->pinned_vm); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + up_write(&mm->mmap_sem); +#else + mmap_write_unlock(mm); +#endif + mmput(mm); +out: + kfree(context); + kfree(hmem); +} +#endif + +u32 hmm_umem_page_count(struct hmm_umem *hmem) +{ + u32 i; + u32 n; + struct scatterlist *sg = NULL; + + if (hmem->odp_data) { + return (u32)(hmm_umem_num_pages(hmem)); + } + + n = 0; + for_each_sg(hmem->sg_head.sgl, sg, hmem->nmap, i) n += sg_dma_len(sg) >> ((u32)hmem->page_shift); + + return n; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.h new file mode 100644 index 000000000..8daebd9c7 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.h @@ -0,0 +1,124 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : structure and interface about umem +***************************************************************************** */ + +#ifndef HMM_UMEM_H +#define HMM_UMEM_H + +#include <linux/list.h> +#include <linux/scatterlist.h> +#include <linux/workqueue.h> +#include <linux/uaccess.h> +#include <linux/types.h> +#include <linux/mmu_notifier.h> +#include <linux/kernel.h> + +#ifdef ROCE_SERVICE +#include <rdma/ib_verbs.h> +#include <rdma/ib_umem.h> +#endif + + +#ifndef ROCE_SERVICE + +enum rdma_remove_reason { + /* Userspace requested uobject deletion. Call could fail */ + RDMA_REMOVE_DESTROY, + /* Context deletion. This call should delete the actual object itself */ + RDMA_REMOVE_CLOSE, + /* Driver is being hot-unplugged. This call should delete the actual object itself */ + RDMA_REMOVE_DRIVER_REMOVE, + /* Context is being cleaned-up, but commit was just completed */ + RDMA_REMOVE_DURING_CLEANUP, +}; + +struct ib_uverbs_file; +struct ib_rdmacg_object {}; +struct rb_root_cached_struct { + struct rb_node *rb_root; + struct rb_node *rb_leftmost; +}; + +struct ib_ucontext { + struct device *device; + struct ib_uverbs_file *ufile; + int closing; + + /* locking the uobjects_list */ + struct mutex uobjects_lock; + struct list_head uobjects; + /* protects cleanup process from other actions */ + struct rw_semaphore cleanup_rwsem; + enum rdma_remove_reason cleanup_reason; + + struct pid *tgid; + struct rb_root_cached_struct umem_tree; + /* + * Protects .umem_rbroot and tree, as well as odp_mrs_count and + * mmu notifiers registration. + */ + struct rw_semaphore umem_rwsem; + void (*invalidate_range)(void *umem, unsigned long start, unsigned long end); + + struct mmu_notifier mn; + atomic_t notifier_count; + /* A list of umems that don't have private mmu notifier counters yet. */ + struct list_head no_private_counters; + int odp_mrs_count; + + struct ib_rdmacg_object cg_obj; +}; + +struct ib_umem_odp; + +struct hmm_umem *hmm_umem_get(struct device *device, unsigned long addr, size_t size, int access, int dmasync); + +void hmm_umem_release(struct hmm_umem *hmem); + +#endif + +struct hmm_umem { + struct ib_ucontext *context; + size_t length; + unsigned long address; + int page_shift; + int writable; + int hugetlb; + struct work_struct work; + struct mm_struct *mm; + unsigned long diff; + struct ib_umem_odp *odp_data; + struct sg_table sg_head; + int nmap; + int npages; +}; + + +/* Returns the offset of the umem start relative to the first page. */ +static inline int hmm_umem_offset(const struct hmm_umem *umem) +{ + return umem->address & ~PAGE_MASK; +} + +/* Returns the first page of an ODP umem. */ +static inline unsigned long hmm_umem_start(struct hmm_umem *umem) +{ + return umem->address - hmm_umem_offset(umem); +} + +/* Returns the address of the page after the last one of an ODP umem. */ +static inline unsigned long hmm_umem_end(const struct hmm_umem *umem) +{ + return ALIGN(umem->address + umem->length, BIT((unsigned int)umem->page_shift)); +} + +static inline size_t hmm_umem_num_pages(struct hmm_umem *umem) +{ + return (size_t)(((unsigned long)(hmm_umem_end(umem) - hmm_umem_start(umem))) >> (unsigned long)umem->page_shift); +} + +u32 hmm_umem_page_count(struct hmm_umem *hmem); + + +#endif /* HMM_UMEM_H */ diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.c b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.c new file mode 100644 index 000000000..025c24efe --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": [COMM]" fmt + +#include <linux/netlink.h> +#include <linux/pci.h> +#include <linux/firmware.h> + +#include "hinic3_devlink.h" +#ifdef HAVE_DEVLINK_FLASH_UPDATE_PARAMS +#include "hinic3_common.h" +#include "hinic3_api_cmd.h" +#include "hinic3_mgmt.h" +#include "hinic3_hw.h" + +static bool check_image_valid(struct hinic3_hwdev *hwdev, const u8 *buf, + u32 size, struct host_image *host_image) +{ + struct firmware_image *fw_image = NULL; + u32 len = 0; + u32 i; + + fw_image = (struct firmware_image *)buf; + if (fw_image->fw_magic != FW_MAGIC_NUM) { + sdk_err(hwdev->dev_hdl, "Wrong fw magic read from file, fw_magic: 0x%x\n", + fw_image->fw_magic); + return false; + } + + if (fw_image->fw_info.section_cnt > FW_TYPE_MAX_NUM) { + sdk_err(hwdev->dev_hdl, "Wrong fw type number read from file, fw_type_num: 0x%x\n", + fw_image->fw_info.section_cnt); + return false; + } + + for (i = 0; i < fw_image->fw_info.section_cnt; i++) { + len += fw_image->section_info[i].section_len; + memcpy(&host_image->section_info[i], &fw_image->section_info[i], + sizeof(struct firmware_section)); + } + + if (len != fw_image->fw_len || + (u32)(fw_image->fw_len + FW_IMAGE_HEAD_SIZE) != size) { + sdk_err(hwdev->dev_hdl, "Wrong data size read from file\n"); + return false; + } + + host_image->image_info.total_len = fw_image->fw_len; + host_image->image_info.fw_version = fw_image->fw_version; + host_image->type_num = fw_image->fw_info.section_cnt; + host_image->device_id = fw_image->device_id; + + return true; +} + +static bool check_image_integrity(struct hinic3_hwdev *hwdev, struct host_image *host_image) +{ + u64 collect_section_type = 0; + u32 type, i; + + for (i = 0; i < host_image->type_num; i++) { + type = host_image->section_info[i].section_type; + if (collect_section_type & (1ULL << type)) { + sdk_err(hwdev->dev_hdl, "Duplicate section type: %u\n", type); + return false; + } + collect_section_type |= (1ULL << type); + } + + if ((collect_section_type & IMAGE_COLD_SUB_MODULES_MUST_IN) == + IMAGE_COLD_SUB_MODULES_MUST_IN && + (collect_section_type & IMAGE_CFG_SUB_MODULES_MUST_IN) != 0) + return true; + + sdk_err(hwdev->dev_hdl, "Failed to check file integrity, valid: 0x%llx, current: 0x%llx\n", + (IMAGE_COLD_SUB_MODULES_MUST_IN | IMAGE_CFG_SUB_MODULES_MUST_IN), + collect_section_type); + + return false; +} + +static bool check_image_device_type(struct hinic3_hwdev *hwdev, u32 device_type) +{ + struct comm_cmd_board_info board_info; + + memset(&board_info, 0, sizeof(board_info)); + if (hinic3_get_board_info(hwdev, &board_info.info, HINIC3_CHANNEL_COMM)) { + sdk_err(hwdev->dev_hdl, "Failed to get board info\n"); + return false; + } + + if (device_type == board_info.info.board_type) + return true; + + sdk_err(hwdev->dev_hdl, "The image device type: 0x%x doesn't match the firmware device type: 0x%x\n", + device_type, board_info.info.board_type); + + return false; +} + +static void encapsulate_update_cmd(struct hinic3_cmd_update_firmware *msg, + struct firmware_section *section_info, + const int *remain_len, u32 *send_len, u32 *send_pos) +{ + memset(msg->data, 0, sizeof(msg->data)); + msg->ctl_info.sf = (*remain_len == section_info->section_len) ? true : false; + msg->section_info.section_crc = section_info->section_crc; + msg->section_info.section_type = section_info->section_type; + msg->section_version = section_info->section_version; + msg->section_len = section_info->section_len; + msg->section_offset = *send_pos; + msg->ctl_info.bit_signed = section_info->section_flag & 0x1; + + if (*remain_len <= FW_FRAGMENT_MAX_LEN) { + msg->ctl_info.sl = true; + msg->ctl_info.fragment_len = (u32)(*remain_len); + *send_len += section_info->section_len; + } else { + msg->ctl_info.sl = false; + msg->ctl_info.fragment_len = FW_FRAGMENT_MAX_LEN; + *send_len += FW_FRAGMENT_MAX_LEN; + } +} + +static int hinic3_flash_firmware(struct hinic3_hwdev *hwdev, const u8 *data, + struct host_image *image) +{ + u32 send_pos, send_len, section_offset, i; + struct hinic3_cmd_update_firmware *update_msg = NULL; + u16 out_size = sizeof(*update_msg); + bool total_flag = false; + int remain_len, err; + + update_msg = kzalloc(sizeof(*update_msg), GFP_KERNEL); + if (!update_msg) { + sdk_err(hwdev->dev_hdl, "Failed to alloc update message\n"); + return -ENOMEM; + } + + for (i = 0; i < image->type_num; i++) { + section_offset = image->section_info[i].section_offset; + remain_len = (int)(image->section_info[i].section_len); + send_len = 0; + send_pos = 0; + + while (remain_len > 0) { + if (!total_flag) { + update_msg->total_len = image->image_info.total_len; + total_flag = true; + } else { + update_msg->total_len = 0; + } + + encapsulate_update_cmd(update_msg, &image->section_info[i], + &remain_len, &send_len, &send_pos); + + memcpy(update_msg->data, + ((data + FW_IMAGE_HEAD_SIZE) + section_offset) + send_pos, + update_msg->ctl_info.fragment_len); + + err = hinic3_pf_to_mgmt_sync(hwdev, HINIC3_MOD_COMM, COMM_MGMT_CMD_UPDATE_FW, + update_msg, sizeof(*update_msg), update_msg, &out_size, FW_UPDATE_MGMT_TIMEOUT); + if (err || !out_size || update_msg->msg_head.status) { + sdk_err(hwdev->dev_hdl, "Failed to update firmware, err: %d, status: 0x%x, out size: 0x%x\n", + err, update_msg->msg_head.status, out_size); + err = update_msg->msg_head.status ? + update_msg->msg_head.status : -EIO; + kfree(update_msg); + return err; + } + + send_pos = send_len; + remain_len = (int)(image->section_info[i].section_len - send_len); + } + } + + kfree(update_msg); + + return 0; +} + +static int hinic3_flash_update_notify(struct devlink *devlink, const struct firmware *fw, + struct host_image *image, struct netlink_ext_ack *extack) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + int err; + +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + devlink_flash_update_begin_notify(devlink); +#endif + devlink_flash_update_status_notify(devlink, "Flash firmware begin", NULL, 0, 0); + sdk_info(hwdev->dev_hdl, "Flash firmware begin\n"); + err = hinic3_flash_firmware(hwdev, fw->data, image); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to flash firmware, err: %d\n", err); + NL_SET_ERR_MSG_MOD(extack, "Flash firmware failed"); + devlink_flash_update_status_notify(devlink, "Flash firmware failed", NULL, 0, 0); + } else { + sdk_info(hwdev->dev_hdl, "Flash firmware end\n"); + devlink_flash_update_status_notify(devlink, "Flash firmware end", NULL, 0, 0); + } +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + devlink_flash_update_end_notify(devlink); +#endif + + return err; +} + +#ifdef HAVE_DEVLINK_FW_FILE_NAME_PARAM +static int hinic3_devlink_flash_update(struct devlink *devlink, const char *file_name, + const char *component, struct netlink_ext_ack *extack) +#else +static int hinic3_devlink_flash_update(struct devlink *devlink, + struct devlink_flash_update_params *params, + struct netlink_ext_ack *extack) +#endif +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + const struct firmware *fw = NULL; +#else + const struct firmware *fw = params->fw; +#endif + struct host_image *image = NULL; + int err; + + image = kzalloc(sizeof(*image), GFP_KERNEL); + if (!image) { + sdk_err(hwdev->dev_hdl, "Failed to alloc host image\n"); + err = -ENOMEM; + goto devlink_param_reset; + } + +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER +#ifdef HAVE_DEVLINK_FW_FILE_NAME_PARAM + err = request_firmware_direct(&fw, file_name, hwdev->dev_hdl); +#else + err = request_firmware_direct(&fw, params->file_name, hwdev->dev_hdl); +#endif + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to request firmware\n"); + goto devlink_request_fw_err; + } +#endif + + if (!check_image_valid(hwdev, fw->data, (u32)(fw->size), image) || + !check_image_integrity(hwdev, image) || + !check_image_device_type(hwdev, image->device_id)) { + sdk_err(hwdev->dev_hdl, "Failed to check image\n"); + NL_SET_ERR_MSG_MOD(extack, "Check image failed"); + err = -EINVAL; + goto devlink_update_out; + } + + err = hinic3_flash_update_notify(devlink, fw, image, extack); + +devlink_update_out: +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + release_firmware(fw); + +devlink_request_fw_err: +#endif + kfree(image); + +devlink_param_reset: + /* reset activate_fw and switch_cfg after flash update operation */ + devlink_dev->activate_fw = FW_CFG_DEFAULT_INDEX; + devlink_dev->switch_cfg = FW_CFG_DEFAULT_INDEX; + + return err; +} + +static const struct devlink_ops hinic3_devlink_ops = { + .flash_update = hinic3_devlink_flash_update, +}; + +static int hinic3_devlink_get_activate_firmware_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + + ctx->val.vu8 = devlink_dev->activate_fw; + + return 0; +} + +static int hinic3_devlink_set_activate_firmware_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + int err; + + devlink_dev->activate_fw = ctx->val.vu8; + sdk_info(hwdev->dev_hdl, "Activate firmware begin\n"); + + err = hinic3_activate_firmware(hwdev, devlink_dev->activate_fw); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to activate firmware, err: %d\n", err); + return err; + } + + sdk_info(hwdev->dev_hdl, "Activate firmware end\n"); + + return 0; +} + +static int hinic3_devlink_get_switch_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + + ctx->val.vu8 = devlink_dev->switch_cfg; + + return 0; +} + +static int hinic3_devlink_set_switch_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + int err; + + devlink_dev->switch_cfg = ctx->val.vu8; + sdk_info(hwdev->dev_hdl, "Switch cfg begin"); + + err = hinic3_switch_config(hwdev, devlink_dev->switch_cfg); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to switch cfg, err: %d\n", err); + return err; + } + + sdk_info(hwdev->dev_hdl, "Switch cfg end\n"); + + return 0; +} + +static int hinic3_devlink_firmware_config_validate(struct devlink *devlink, u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + u8 cfg_index = val.vu8; + + if (cfg_index > FW_CFG_MAX_INDEX) { + sdk_err(hwdev->dev_hdl, "Firmware cfg index out of range [0,7]\n"); + NL_SET_ERR_MSG_MOD(extack, "Firmware cfg index out of range [0,7]"); + return -ERANGE; + } + + return 0; +} + +static const struct devlink_param hinic3_devlink_params[] = { + DEVLINK_PARAM_DRIVER(HINIC3_DEVLINK_PARAM_ID_ACTIVATE_FW, + "activate_fw", DEVLINK_PARAM_TYPE_U8, + BIT(DEVLINK_PARAM_CMODE_PERMANENT), + hinic3_devlink_get_activate_firmware_config, + hinic3_devlink_set_activate_firmware_config, + hinic3_devlink_firmware_config_validate), + DEVLINK_PARAM_DRIVER(HINIC3_DEVLINK_PARAM_ID_SWITCH_CFG, + "switch_cfg", DEVLINK_PARAM_TYPE_U8, + BIT(DEVLINK_PARAM_CMODE_PERMANENT), + hinic3_devlink_get_switch_config, + hinic3_devlink_set_switch_config, + hinic3_devlink_firmware_config_validate), +}; + +int hinic3_init_devlink(struct hinic3_hwdev *hwdev) +{ + struct devlink *devlink = NULL; + struct pci_dev *pdev = NULL; + int err; + + devlink = devlink_alloc(&hinic3_devlink_ops, sizeof(struct hinic3_devlink)); + if (!devlink) { + sdk_err(hwdev->dev_hdl, "Failed to alloc devlink\n"); + return -ENOMEM; + } + + hwdev->devlink_dev = devlink_priv(devlink); + hwdev->devlink_dev->hwdev = hwdev; + hwdev->devlink_dev->activate_fw = FW_CFG_DEFAULT_INDEX; + hwdev->devlink_dev->switch_cfg = FW_CFG_DEFAULT_INDEX; + + pdev = hwdev->hwif->pdev; + err = devlink_register(devlink, &pdev->dev); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to register devlink\n"); + goto register_devlink_err; + } + + err = devlink_params_register(devlink, hinic3_devlink_params, + ARRAY_SIZE(hinic3_devlink_params)); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to register devlink params\n"); + goto register_devlink_params_err; + } + + devlink_params_publish(devlink); + + return 0; + +register_devlink_params_err: + devlink_unregister(devlink); + +register_devlink_err: + devlink_free(devlink); + + return -EFAULT; +} + +void hinic3_uninit_devlink(struct hinic3_hwdev *hwdev) +{ + struct devlink *devlink = priv_to_devlink(hwdev->devlink_dev); + + devlink_params_unpublish(devlink); + devlink_params_unregister(devlink, hinic3_devlink_params, + ARRAY_SIZE(hinic3_devlink_params)); + devlink_unregister(devlink); + devlink_free(devlink); +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.h b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.h new file mode 100644 index 000000000..a0c14ea17 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#ifndef HINIC3_DEVLINK_H +#define HINIC3_DEVLINK_H + +#include "ossl_knl.h" +#include "hinic3_hwdev.h" + +#define FW_MAGIC_NUM 0x5a5a1100 +#define FW_IMAGE_HEAD_SIZE 4096 +#define FW_FRAGMENT_MAX_LEN 1536 +#define FW_CFG_DEFAULT_INDEX 0xFF +#define FW_TYPE_MAX_NUM 0x40 +#define FW_CFG_MAX_INDEX 7 + +#ifdef HAVE_DEVLINK_FLASH_UPDATE_PARAMS +enum hinic3_devlink_param_id { + HINIC3_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + HINIC3_DEVLINK_PARAM_ID_ACTIVATE_FW, + HINIC3_DEVLINK_PARAM_ID_SWITCH_CFG, +}; +#endif + +enum hinic3_firmware_type { + UP_FW_UPDATE_MIN_TYPE1 = 0x0, + UP_FW_UPDATE_UP_TEXT = 0x0, + UP_FW_UPDATE_UP_DATA = 0x1, + UP_FW_UPDATE_UP_DICT = 0x2, + UP_FW_UPDATE_TILE_PCPTR = 0x3, + UP_FW_UPDATE_TILE_TEXT = 0x4, + UP_FW_UPDATE_TILE_DATA = 0x5, + UP_FW_UPDATE_TILE_DICT = 0x6, + UP_FW_UPDATE_PPE_STATE = 0x7, + UP_FW_UPDATE_PPE_BRANCH = 0x8, + UP_FW_UPDATE_PPE_EXTACT = 0x9, + UP_FW_UPDATE_MAX_TYPE1 = 0x9, + UP_FW_UPDATE_CFG0 = 0xa, + UP_FW_UPDATE_CFG1 = 0xb, + UP_FW_UPDATE_CFG2 = 0xc, + UP_FW_UPDATE_CFG3 = 0xd, + UP_FW_UPDATE_MAX_TYPE1_CFG = 0xd, + + UP_FW_UPDATE_MIN_TYPE2 = 0x14, + UP_FW_UPDATE_MAX_TYPE2 = 0x14, + + UP_FW_UPDATE_MIN_TYPE3 = 0x18, + UP_FW_UPDATE_PHY = 0x18, + UP_FW_UPDATE_BIOS = 0x19, + UP_FW_UPDATE_HLINK_ONE = 0x1a, + UP_FW_UPDATE_HLINK_TWO = 0x1b, + UP_FW_UPDATE_HLINK_THR = 0x1c, + UP_FW_UPDATE_MAX_TYPE3 = 0x1c, + + UP_FW_UPDATE_MIN_TYPE4 = 0x20, + UP_FW_UPDATE_L0FW = 0x20, + UP_FW_UPDATE_L1FW = 0x21, + UP_FW_UPDATE_BOOT = 0x22, + UP_FW_UPDATE_SEC_DICT = 0x23, + UP_FW_UPDATE_HOT_PATCH0 = 0x24, + UP_FW_UPDATE_HOT_PATCH1 = 0x25, + UP_FW_UPDATE_HOT_PATCH2 = 0x26, + UP_FW_UPDATE_HOT_PATCH3 = 0x27, + UP_FW_UPDATE_HOT_PATCH4 = 0x28, + UP_FW_UPDATE_HOT_PATCH5 = 0x29, + UP_FW_UPDATE_HOT_PATCH6 = 0x2a, + UP_FW_UPDATE_HOT_PATCH7 = 0x2b, + UP_FW_UPDATE_HOT_PATCH8 = 0x2c, + UP_FW_UPDATE_HOT_PATCH9 = 0x2d, + UP_FW_UPDATE_HOT_PATCH10 = 0x2e, + UP_FW_UPDATE_HOT_PATCH11 = 0x2f, + UP_FW_UPDATE_HOT_PATCH12 = 0x30, + UP_FW_UPDATE_HOT_PATCH13 = 0x31, + UP_FW_UPDATE_HOT_PATCH14 = 0x32, + UP_FW_UPDATE_HOT_PATCH15 = 0x33, + UP_FW_UPDATE_HOT_PATCH16 = 0x34, + UP_FW_UPDATE_HOT_PATCH17 = 0x35, + UP_FW_UPDATE_HOT_PATCH18 = 0x36, + UP_FW_UPDATE_HOT_PATCH19 = 0x37, + UP_FW_UPDATE_MAX_TYPE4 = 0x37, + + UP_FW_UPDATE_MIN_TYPE5 = 0x3a, + UP_FW_UPDATE_OPTION_ROM = 0x3a, + UP_FW_UPDATE_MAX_TYPE5 = 0x3a, + + UP_FW_UPDATE_MIN_TYPE6 = 0x3e, + UP_FW_UPDATE_MAX_TYPE6 = 0x3e, + + UP_FW_UPDATE_MIN_TYPE7 = 0x40, + UP_FW_UPDATE_MAX_TYPE7 = 0x40, +}; + +#define IMAGE_MPU_ALL_IN (BIT_ULL(UP_FW_UPDATE_UP_TEXT) | \ + BIT_ULL(UP_FW_UPDATE_UP_DATA) | \ + BIT_ULL(UP_FW_UPDATE_UP_DICT)) + +#define IMAGE_NPU_ALL_IN (BIT_ULL(UP_FW_UPDATE_TILE_PCPTR) | \ + BIT_ULL(UP_FW_UPDATE_TILE_TEXT) | \ + BIT_ULL(UP_FW_UPDATE_TILE_DATA) | \ + BIT_ULL(UP_FW_UPDATE_TILE_DICT) | \ + BIT_ULL(UP_FW_UPDATE_PPE_STATE) | \ + BIT_ULL(UP_FW_UPDATE_PPE_BRANCH) | \ + BIT_ULL(UP_FW_UPDATE_PPE_EXTACT)) + +#define IMAGE_COLD_SUB_MODULES_MUST_IN (IMAGE_MPU_ALL_IN | IMAGE_NPU_ALL_IN) + +#define IMAGE_CFG_SUB_MODULES_MUST_IN (BIT_ULL(UP_FW_UPDATE_CFG0) | \ + BIT_ULL(UP_FW_UPDATE_CFG1) | \ + BIT_ULL(UP_FW_UPDATE_CFG2) | \ + BIT_ULL(UP_FW_UPDATE_CFG3)) + +struct firmware_section { + u32 section_len; + u32 section_offset; + u32 section_version; + u32 section_type; + u32 section_crc; + u32 section_flag; +}; + +struct firmware_image { + u32 fw_version; + u32 fw_len; + u32 fw_magic; + struct { + u32 section_cnt : 16; + u32 rsvd : 16; + } fw_info; + struct firmware_section section_info[FW_TYPE_MAX_NUM]; + u32 device_id; /* cfg fw board_type value */ + u32 rsvd0[101]; /* device_id and rsvd0[101] is update_head_extend_info */ + u32 rsvd1[534]; /* big bin file total size 4096B */ + u32 bin_data; /* obtain the address for use */ +}; + +struct host_image { + struct firmware_section section_info[FW_TYPE_MAX_NUM]; + struct { + u32 total_len; + u32 fw_version; + } image_info; + u32 type_num; + u32 device_id; +}; + +struct hinic3_cmd_update_firmware { + struct mgmt_msg_head msg_head; + + struct { + u32 sl : 1; + u32 sf : 1; + u32 flag : 1; + u32 bit_signed : 1; + u32 reserved : 12; + u32 fragment_len : 16; + } ctl_info; + + struct { + u32 section_crc; + u32 section_type; + } section_info; + + u32 total_len; + u32 section_len; + u32 section_version; + u32 section_offset; + u32 data[384]; +}; + +int hinic3_init_devlink(struct hinic3_hwdev *hwdev); +void hinic3_uninit_devlink(struct hinic3_hwdev *hwdev); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.c b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.c new file mode 100644 index 000000000..8eaa332b8 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.c @@ -0,0 +1,605 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#include "ossl_knl.h" +#include "hinic3_mt.h" +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "mpu_inband_cmd.h" +#include "hinic3_hw_mt.h" + +#define HINIC3_CMDQ_BUF_MAX_SIZE 2048U +#define DW_WIDTH 4 + +#define MSG_MAX_IN_SIZE (2048 * 1024) +#define MSG_MAX_OUT_SIZE (2048 * 1024) + +#define API_CSR_MAX_RD_LEN (4 * 1024 * 1024) + +/* completion timeout interval, unit is millisecond */ +#define MGMT_MSG_UPDATE_TIMEOUT 200000U + +void free_buff_in(void *hwdev, const struct msg_module *nt_msg, void *buf_in) +{ + if (!buf_in) + return; + + if (nt_msg->module == SEND_TO_NPU) + hinic3_free_cmd_buf(hwdev, buf_in); + else + kfree(buf_in); +} + +void free_buff_out(void *hwdev, struct msg_module *nt_msg, + void *buf_out) +{ + if (!buf_out) + return; + + if (nt_msg->module == SEND_TO_NPU && + !nt_msg->npu_cmd.direct_resp) + hinic3_free_cmd_buf(hwdev, buf_out); + else + kfree(buf_out); +} + +int alloc_buff_in(void *hwdev, struct msg_module *nt_msg, + u32 in_size, void **buf_in) +{ + void *msg_buf = NULL; + + if (!in_size) + return 0; + + if (nt_msg->module == SEND_TO_NPU) { + struct hinic3_cmd_buf *cmd_buf = NULL; + + if (in_size > HINIC3_CMDQ_BUF_MAX_SIZE) { + pr_err("Cmdq in size(%u) more than 2KB\n", in_size); + return -ENOMEM; + } + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + if (!cmd_buf) { + pr_err("Alloc cmdq cmd buffer failed in %s\n", + __func__); + return -ENOMEM; + } + msg_buf = cmd_buf->buf; + *buf_in = (void *)cmd_buf; + cmd_buf->size = (u16)in_size; + } else { + if (in_size > MSG_MAX_IN_SIZE) { + pr_err("In size(%u) more than 2M\n", in_size); + return -ENOMEM; + } + msg_buf = kzalloc(in_size, GFP_KERNEL); + *buf_in = msg_buf; + } + if (!(*buf_in)) { + pr_err("Alloc buffer in failed\n"); + return -ENOMEM; + } + + if (copy_from_user(msg_buf, nt_msg->in_buf, in_size)) { + pr_err("%s:%d: Copy from user failed\n", + __func__, __LINE__); + free_buff_in(hwdev, nt_msg, *buf_in); + return -EFAULT; + } + + return 0; +} + +int alloc_buff_out(void *hwdev, struct msg_module *nt_msg, + u32 out_size, void **buf_out) +{ + if (!out_size) + return 0; + + if (nt_msg->module == SEND_TO_NPU && + !nt_msg->npu_cmd.direct_resp) { + struct hinic3_cmd_buf *cmd_buf = NULL; + + if (out_size > HINIC3_CMDQ_BUF_MAX_SIZE) { + pr_err("Cmdq out size(%u) more than 2KB\n", out_size); + return -ENOMEM; + } + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + *buf_out = (void *)cmd_buf; + } else { + if (out_size > MSG_MAX_OUT_SIZE) { + pr_err("out size(%u) more than 2M\n", out_size); + return -ENOMEM; + } + *buf_out = kzalloc(out_size, GFP_KERNEL); + } + if (!(*buf_out)) { + pr_err("Alloc buffer out failed\n"); + return -ENOMEM; + } + + return 0; +} + +int copy_buf_out_to_user(struct msg_module *nt_msg, + u32 out_size, void *buf_out) +{ + int ret = 0; + void *msg_out = NULL; + + if (out_size == 0 || !buf_out) + return 0; + + if (nt_msg->module == SEND_TO_NPU && + !nt_msg->npu_cmd.direct_resp) + msg_out = ((struct hinic3_cmd_buf *)buf_out)->buf; + else + msg_out = buf_out; + + if (copy_to_user(nt_msg->out_buf, msg_out, out_size)) + ret = -EFAULT; + + return ret; +} + +int get_func_type(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u16 func_type; + + if (*out_size != sizeof(u16) || !buf_out) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(u16)); + return -EFAULT; + } + + func_type = hinic3_func_type(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + + *(u16 *)buf_out = func_type; + return 0; +} + +int get_func_id(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u16 func_id; + + if (*out_size != sizeof(u16) || !buf_out) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(u16)); + return -EFAULT; + } + + func_id = hinic3_global_func_id(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + *(u16 *)buf_out = func_id; + + return 0; +} + +int get_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + return hinic3_dbg_get_hw_stats(hinic3_get_sdk_hwdev_by_lld(lld_dev), + buf_out, out_size); +} + +int clear_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u16 size; + + size = hinic3_dbg_clear_hw_stats(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + if (*out_size != size) { + pr_err("Unexpect out buf size from user :%u, expect: %u\n", + *out_size, size); + return -EFAULT; + } + + return 0; +} + +int get_self_test_result(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u32 result; + + if (*out_size != sizeof(u32) || !buf_out) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(u32)); + return -EFAULT; + } + + result = hinic3_get_self_test_result(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + *(u32 *)buf_out = result; + + return 0; +} + +int get_chip_faults_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u32 offset = 0; + struct nic_cmd_chip_fault_stats *fault_info = NULL; + + if (!buf_in || !buf_out || *out_size != sizeof(*fault_info) || + in_size != sizeof(*fault_info)) { + pr_err("Unexpect out buf size from user: %u, expect: %lu\n", + *out_size, sizeof(*fault_info)); + return -EFAULT; + } + fault_info = (struct nic_cmd_chip_fault_stats *)buf_in; + offset = fault_info->offset; + + fault_info = (struct nic_cmd_chip_fault_stats *)buf_out; + hinic3_get_chip_fault_stats(hinic3_get_sdk_hwdev_by_lld(lld_dev), + fault_info->chip_fault_stats, offset); + + return 0; +} + +static u32 get_up_timeout_val(enum hinic3_mod_type mod, u16 cmd) +{ + if (mod == HINIC3_MOD_COMM && + (cmd == COMM_MGMT_CMD_UPDATE_FW || + cmd == COMM_MGMT_CMD_UPDATE_BIOS || + cmd == COMM_MGMT_CMD_ACTIVE_FW || + cmd == COMM_MGMT_CMD_SWITCH_CFG || + cmd == COMM_MGMT_CMD_HOT_ACTIVE_FW)) + return MGMT_MSG_UPDATE_TIMEOUT; + + return 0; /* use default mbox/apichain timeout time */ +} + +static int api_csr_read(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct up_log_msg_st *up_log_msg = (struct up_log_msg_st *)buf_in; + u8 *buf_out_tmp = (u8 *)buf_out; + int ret = 0; + u32 rd_len; + u32 rd_addr; + u32 rd_cnt = 0; + u32 offset = 0; + u8 node_id; + u32 i; + + if (!buf_in || !buf_out || in_size != sizeof(*up_log_msg) || + *out_size != up_log_msg->rd_len || up_log_msg->rd_len % DW_WIDTH != 0) + return -EINVAL; + + rd_len = up_log_msg->rd_len; + rd_addr = up_log_msg->addr; + node_id = (u8)nt_msg->mpu_cmd.mod; + + rd_cnt = rd_len / DW_WIDTH; + + for (i = 0; i < rd_cnt; i++) { + ret = hinic3_api_csr_rd32(hwdev, node_id, + rd_addr + offset, + (u32 *)(buf_out_tmp + offset)); + if (ret) { + pr_err("Csr rd fail, err: %d, node_id: %u, csr addr: 0x%08x\n", + ret, node_id, rd_addr + offset); + return ret; + } + offset += DW_WIDTH; + } + *out_size = rd_len; + + return ret; +} + +static int api_csr_write(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, + u32 *out_size) +{ + struct csr_write_st *csr_write_msg = (struct csr_write_st *)buf_in; + int ret = 0; + u32 rd_len; + u32 rd_addr; + u32 rd_cnt = 0; + u32 offset = 0; + u8 node_id; + u32 i; + u8 *data = NULL; + + if (!buf_in || in_size != sizeof(*csr_write_msg) || csr_write_msg->rd_len == 0 || + csr_write_msg->rd_len > API_CSR_MAX_RD_LEN || csr_write_msg->rd_len % DW_WIDTH != 0) + return -EINVAL; + + rd_len = csr_write_msg->rd_len; + rd_addr = csr_write_msg->addr; + node_id = (u8)nt_msg->mpu_cmd.mod; + + rd_cnt = rd_len / DW_WIDTH; + + data = kzalloc(rd_len, GFP_KERNEL); + if (!data) { + pr_err("No more memory\n"); + return -EFAULT; + } + if (copy_from_user(data, (void *)csr_write_msg->data, rd_len)) { + pr_err("Copy information from user failed\n"); + kfree(data); + return -EFAULT; + } + + for (i = 0; i < rd_cnt; i++) { + ret = hinic3_api_csr_wr32(hwdev, node_id, + rd_addr + offset, + *((u32 *)(data + offset))); + if (ret) { + pr_err("Csr wr fail, ret: %d, node_id: %u, csr addr: 0x%08x\n", + ret, rd_addr + offset, node_id); + kfree(data); + return ret; + } + offset += DW_WIDTH; + } + + *out_size = 0; + kfree(data); + return ret; +} + +int send_to_mpu(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + enum hinic3_mod_type mod; + u32 timeout; + int ret = 0; + u16 cmd; + + mod = (enum hinic3_mod_type)nt_msg->mpu_cmd.mod; + cmd = nt_msg->mpu_cmd.cmd; + + if (nt_msg->mpu_cmd.api_type == API_TYPE_MBOX || nt_msg->mpu_cmd.api_type == API_TYPE_CLP) { + timeout = get_up_timeout_val(mod, cmd); + + if (nt_msg->mpu_cmd.api_type == API_TYPE_MBOX) + ret = hinic3_msg_to_mgmt_sync(hwdev, mod, cmd, buf_in, (u16)in_size, + buf_out, (u16 *)(u8 *)out_size, timeout, + HINIC3_CHANNEL_DEFAULT); + else + ret = hinic3_clp_to_mgmt(hwdev, mod, cmd, buf_in, (u16)in_size, + buf_out, (u16 *)out_size); + if (ret) { + pr_err("Message to mgmt cpu return fail, mod: %d, cmd: %u\n", mod, cmd); + return ret; + } + } else if (nt_msg->mpu_cmd.api_type == API_TYPE_API_CHAIN_BYPASS) { + if (nt_msg->mpu_cmd.cmd == API_CSR_WRITE) + return api_csr_write(hwdev, nt_msg, buf_in, in_size, buf_out, out_size); + + ret = api_csr_read(hwdev, nt_msg, buf_in, in_size, buf_out, out_size); + } else if (nt_msg->mpu_cmd.api_type == API_TYPE_API_CHAIN_TO_MPU) { + timeout = get_up_timeout_val(mod, cmd); + if (hinic3_pcie_itf_id(hwdev) != SPU_HOST_ID) + ret = hinic3_msg_to_mgmt_api_chain_sync(hwdev, mod, cmd, buf_in, + (u16)in_size, buf_out, + (u16 *)(u8 *)out_size, timeout); + else + ret = hinic3_msg_to_mgmt_sync(hwdev, mod, cmd, buf_in, (u16)in_size, + buf_out, (u16 *)(u8 *)out_size, timeout, + HINIC3_CHANNEL_DEFAULT); + if (ret) { + pr_err("Message to mgmt api chain cpu return fail, mod: %d, cmd: %u\n", + mod, cmd); + return ret; + } + } else { + pr_err("Unsupported api_type %u\n", nt_msg->mpu_cmd.api_type); + return -EINVAL; + } + + return ret; +} + +int send_to_npu(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int ret = 0; + u8 cmd; + enum hinic3_mod_type mod; + + mod = (enum hinic3_mod_type)nt_msg->npu_cmd.mod; + cmd = nt_msg->npu_cmd.cmd; + + if (nt_msg->npu_cmd.direct_resp) { + ret = hinic3_cmdq_direct_resp(hwdev, mod, cmd, + buf_in, buf_out, 0, + HINIC3_CHANNEL_DEFAULT); + if (ret) + pr_err("Send direct cmdq failed, err: %d\n", ret); + } else { + ret = hinic3_cmdq_detail_resp(hwdev, mod, cmd, buf_in, buf_out, + NULL, 0, HINIC3_CHANNEL_DEFAULT); + if (ret) + pr_err("Send detail cmdq failed, err: %d\n", ret); + } + + return ret; +} + +static int sm_rd16(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u16 val1; + int ret; + + ret = hinic3_sm_ctr_rd16(hwdev, node, instance, id, &val1); + if (ret != 0) { + pr_err("Get sm ctr information (16 bits)failed!\n"); + val1 = 0xffff; + } + + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd32(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u32 val1; + int ret; + + ret = hinic3_sm_ctr_rd32(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr information (32 bits)failed!\n"); + val1 = ~0; + } + + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd32_clear(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u32 val1; + int ret; + + ret = hinic3_sm_ctr_rd32_clear(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr clear information(32 bits) failed!\n"); + val1 = ~0; + } + + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd64_pair(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1 = 0, val2 = 0; + int ret; + + ret = hinic3_sm_ctr_rd64_pair(hwdev, node, instance, id, &val1, &val2); + if (ret) { + pr_err("Get sm ctr information (64 bits pair)failed!\n"); + val1 = ~0; + val2 = ~0; + } + + buf_out->val1 = val1; + buf_out->val2 = val2; + + return ret; +} + +static int sm_rd64_pair_clear(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1 = 0; + u64 val2 = 0; + int ret; + + ret = hinic3_sm_ctr_rd64_pair_clear(hwdev, node, instance, id, &val1, + &val2); + if (ret) { + pr_err("Get sm ctr clear information(64 bits pair) failed!\n"); + val1 = ~0; + val2 = ~0; + } + + buf_out->val1 = val1; + buf_out->val2 = val2; + + return ret; +} + +static int sm_rd64(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1; + int ret; + + ret = hinic3_sm_ctr_rd64(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr information (64 bits)failed!\n"); + val1 = ~0; + } + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd64_clear(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1; + int ret; + + ret = hinic3_sm_ctr_rd64_clear(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr clear information(64 bits) failed!\n"); + val1 = ~0; + } + buf_out->val1 = val1; + + return ret; +} + +typedef int (*sm_module)(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out); + +struct sm_module_handle { + enum sm_cmd_type sm_cmd_name; + sm_module sm_func; +}; + +const struct sm_module_handle sm_module_cmd_handle[] = { + {SM_CTR_RD16, sm_rd16}, + {SM_CTR_RD32, sm_rd32}, + {SM_CTR_RD64_PAIR, sm_rd64_pair}, + {SM_CTR_RD64, sm_rd64}, + {SM_CTR_RD32_CLEAR, sm_rd32_clear}, + {SM_CTR_RD64_PAIR_CLEAR, sm_rd64_pair_clear}, + {SM_CTR_RD64_CLEAR, sm_rd64_clear} +}; + +int send_to_sm(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct sm_in_st *sm_in = buf_in; + struct sm_out_st *sm_out = buf_out; + u32 msg_formate; + int index, num_cmds = ARRAY_LEN(sm_module_cmd_handle); + int ret = 0; + + if (!nt_msg || !buf_in || !buf_out || in_size != sizeof(*sm_in) || *out_size != sizeof(*sm_out)) { + pr_err("Unexpect out buf size :%u, in buf size: %u\n", + *out_size, in_size); + return -EINVAL; + } + msg_formate = nt_msg->msg_formate; + + for (index = 0; index < num_cmds; index++) { + if (msg_formate != sm_module_cmd_handle[index].sm_cmd_name) + continue; + + ret = sm_module_cmd_handle[index].sm_func(hwdev, (u32)sm_in->id, + (u8)sm_in->instance, + (u8)sm_in->node, sm_out); + break; + } + + if (index == num_cmds) { + pr_err("Can't find callback for %d\n", msg_formate); + return -EINVAL; + } + if (ret != 0) + pr_err("Get sm information fail, id:%d, instance:%d, node:%d\n", + sm_in->id, sm_in->instance, sm_in->node); + + *out_size = sizeof(struct sm_out_st); + + return ret; +} + diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.h b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.h new file mode 100644 index 000000000..933020082 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#ifndef HINIC3_HW_MT_H +#define HINIC3_HW_MT_H + +#include "hinic3_lld.h" + +struct sm_in_st { + int node; + int id; + int instance; +}; + +struct sm_out_st { + u64 val1; + u64 val2; +}; + +struct up_log_msg_st { + u32 rd_len; + u32 addr; +}; + +struct csr_write_st { + u32 rd_len; + u32 addr; + u8 *data; +}; + +int get_func_type(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_func_id(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int clear_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_self_test_result(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_chip_faults_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.c b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.c new file mode 100644 index 000000000..782f314c3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.c @@ -0,0 +1,982 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": [COMM]" fmt + +#include <net/sock.h> +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/pci.h> + +#include "ossl_knl.h" +#include "hinic3_mt.h" +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_dev_mgmt.h" +#include "hinic3_hwdev.h" +#include "hinic3_lld.h" +#include "hinic3_hw_mt.h" +#include "hinic3_nictool.h" + +static int g_nictool_ref_cnt; + +static dev_t g_dev_id = {0}; +static struct class *g_nictool_class; +static struct cdev g_nictool_cdev; + +#define HINIC3_MAX_BUF_SIZE (2048 * 1024) + +void *g_card_node_array[MAX_CARD_NUM] = {0}; +void *g_card_vir_addr[MAX_CARD_NUM] = {0}; +u64 g_card_phy_addr[MAX_CARD_NUM] = {0}; +int card_id; + +#define HIADM3_DEV_PATH "/dev/hinic3_nictool_dev" +#define HIADM3_DEV_CLASS "hinic3_nictool_class" +#define HIADM3_DEV_NAME "hinic3_nictool_dev" + +typedef int (*hw_driv_module)(struct hinic3_lld_dev *lld_dev, const void *buf_in, + u32 in_size, void *buf_out, u32 *out_size); +struct hw_drv_module_handle { + enum driver_cmd_type driv_cmd_name; + hw_driv_module driv_func; +}; + +static int get_single_card_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, + u32 in_size, void *buf_out, u32 *out_size) +{ + if (!buf_out || *out_size != sizeof(struct card_info)) { + pr_err("buf_out is NULL, or out_size != %lu\n", sizeof(struct card_info)); + return -EINVAL; + } + + hinic3_get_card_info(hinic3_get_sdk_hwdev_by_lld(lld_dev), buf_out); + + return 0; +} + +static int is_driver_in_vm(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + bool in_host = false; + + if (!buf_out || (*out_size != sizeof(u8))) { + pr_err("buf_out is NULL, or out_size != %lu\n", sizeof(u8)); + return -EINVAL; + } + + in_host = hinic3_is_in_host(); + if (in_host) + *((u8 *)buf_out) = 0; + else + *((u8 *)buf_out) = 1; + + return 0; +} + +static int get_all_chip_id_cmd(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + if (*out_size != sizeof(struct nic_card_id) || !buf_out) { + pr_err("Invalid parameter: out_buf_size %u, expect %lu\n", + *out_size, sizeof(struct nic_card_id)); + return -EFAULT; + } + + hinic3_get_all_chip_id(buf_out); + + return 0; +} + +static int get_card_usr_api_chain_mem(int card_idx) +{ + unsigned char *tmp = NULL; + int i; + + card_id = card_idx; + if (!g_card_vir_addr[card_idx]) { + g_card_vir_addr[card_idx] = + (void *)ossl_get_free_pages(GFP_KERNEL, + DBGTOOL_PAGE_ORDER); + if (!g_card_vir_addr[card_idx]) { + pr_err("Alloc api chain memory fail for card %d!\n", card_idx); + return -EFAULT; + } + + memset(g_card_vir_addr[card_idx], 0, + PAGE_SIZE * (1 << DBGTOOL_PAGE_ORDER)); + + g_card_phy_addr[card_idx] = + virt_to_phys(g_card_vir_addr[card_idx]); + if (!g_card_phy_addr[card_idx]) { + pr_err("phy addr for card %d is 0\n", card_idx); + free_pages((unsigned long)g_card_vir_addr[card_idx], DBGTOOL_PAGE_ORDER); + g_card_vir_addr[card_idx] = NULL; + return -EFAULT; + } + + tmp = g_card_vir_addr[card_idx]; + for (i = 0; i < (1 << DBGTOOL_PAGE_ORDER); i++) { + SetPageReserved(virt_to_page(tmp)); + tmp += PAGE_SIZE; + } + } + + return 0; +} + +static void chipif_get_all_pf_dev_info(struct pf_dev_info *dev_info, int card_idx, + void **g_func_handle_array) +{ + u32 func_idx; + void *hwdev = NULL; + struct pci_dev *pdev = NULL; + + for (func_idx = 0; func_idx < PF_DEV_INFO_NUM; func_idx++) { + hwdev = (void *)g_func_handle_array[func_idx]; + + dev_info[func_idx].phy_addr = g_card_phy_addr[card_idx]; + + if (!hwdev) { + dev_info[func_idx].bar0_size = 0; + dev_info[func_idx].bus = 0; + dev_info[func_idx].slot = 0; + dev_info[func_idx].func = 0; + } else { + pdev = (struct pci_dev *)hinic3_get_pcidev_hdl(hwdev); + dev_info[func_idx].bar0_size = + pci_resource_len(pdev, 0); + dev_info[func_idx].bus = pdev->bus->number; + dev_info[func_idx].slot = PCI_SLOT(pdev->devfn); + dev_info[func_idx].func = PCI_FUNC(pdev->devfn); + } + } +} + +static int get_pf_dev_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct pf_dev_info *dev_info = buf_out; + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + int id, err; + + if (!buf_out || *out_size != sizeof(struct pf_dev_info) * PF_DEV_INFO_NUM) { + pr_err("Invalid parameter: out_buf_size %u, expect %lu\n", + *out_size, sizeof(*dev_info) * PF_DEV_INFO_NUM); + return -EFAULT; + } + + err = sscanf(card_info->chip_name, HINIC3_CHIP_NAME "%d", &id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + return err; + } + + if (id >= MAX_CARD_NUM || id < 0) { + pr_err("chip id %d exceed limit[0-%d]\n", id, MAX_CARD_NUM - 1); + return -EINVAL; + } + + chipif_get_all_pf_dev_info(dev_info, id, card_info->func_handle_array); + + err = get_card_usr_api_chain_mem(id); + if (err) { + pr_err("Faile to get api chain memory for userspace %s\n", + card_info->chip_name); + return -EFAULT; + } + + return 0; +} + +static void dbgtool_knl_free_mem(int id) +{ + unsigned char *tmp = NULL; + int i; + + if (id < 0 || id >= MAX_CARD_NUM) { + pr_err("Invalid card id\n"); + return; + } + + if (!g_card_vir_addr[id]) + return; + + tmp = g_card_vir_addr[id]; + for (i = 0; i < (1 << DBGTOOL_PAGE_ORDER); i++) { + ClearPageReserved(virt_to_page(tmp)); + tmp += PAGE_SIZE; + } + + free_pages((unsigned long)g_card_vir_addr[id], DBGTOOL_PAGE_ORDER); + g_card_vir_addr[id] = NULL; + g_card_phy_addr[id] = 0; +} + +static int free_knl_mem(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + int id, err; + + err = sscanf(card_info->chip_name, HINIC3_CHIP_NAME "%d", &id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + return err; + } + + if (id >= MAX_CARD_NUM || id < 0) { + pr_err("chip id %d exceed limit[0-%d]\n", id, MAX_CARD_NUM - 1); + return -EINVAL; + } + + dbgtool_knl_free_mem(id); + + return 0; +} + +static int card_info_param_valid(const char *dev_name, const void *buf_out, + u32 buf_out_size, int *id) +{ + int err; + + if (!buf_out || buf_out_size != sizeof(struct hinic3_card_func_info)) { + pr_err("Invalid parameter: out_buf_size %u, expect %lu\n", + buf_out_size, sizeof(struct hinic3_card_func_info)); + return -EINVAL; + } + + err = memcmp(dev_name, HINIC3_CHIP_NAME, strlen(HINIC3_CHIP_NAME)); + if (err) { + pr_err("Invalid chip name %s\n", dev_name); + return err; + } + + err = sscanf(dev_name, HINIC3_CHIP_NAME "%d", id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + return err; + } + + if (*id >= MAX_CARD_NUM || *id < 0) { + pr_err("chip id %d exceed limit[0-%d]\n", + *id, MAX_CARD_NUM - 1); + return -EINVAL; + } + + return 0; +} + +static int get_card_func_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct hinic3_card_func_info *card_func_info = buf_out; + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + int err, id = 0; + + err = card_info_param_valid(card_info->chip_name, buf_out, *out_size, &id); + if (err) + return err; + + hinic3_get_card_func_info_by_card_name(card_info->chip_name, card_func_info); + + if (!card_func_info->num_pf) { + pr_err("None function found for %s\n", card_info->chip_name); + return -EFAULT; + } + + err = get_card_usr_api_chain_mem(id); + if (err) { + pr_err("Faile to get api chain memory for userspace %s\n", + card_info->chip_name); + return -EFAULT; + } + + card_func_info->usr_api_phy_addr = g_card_phy_addr[id]; + + return 0; +} + +static int get_pf_cap_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct service_cap *func_cap = NULL; + struct hinic3_hwdev *hwdev = NULL; + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + struct svc_cap_info *svc_cap_info_in = (struct svc_cap_info *)buf_in; + struct svc_cap_info *svc_cap_info_out = (struct svc_cap_info *)buf_out; + + if (*out_size != sizeof(struct svc_cap_info) || in_size != sizeof(struct svc_cap_info) || + !buf_in || !buf_out) { + pr_err("Invalid parameter: out_buf_size %u, in_size: %u, expect %lu\n", + *out_size, in_size, sizeof(struct svc_cap_info)); + return -EINVAL; + } + + if (svc_cap_info_in->func_idx >= MAX_FUNCTION_NUM) { + pr_err("func_idx is illegal. func_idx: %u, max_num: %u\n", + svc_cap_info_in->func_idx, MAX_FUNCTION_NUM); + return -EINVAL; + } + + lld_hold(); + hwdev = (struct hinic3_hwdev *)(card_info->func_handle_array)[svc_cap_info_in->func_idx]; + if (!hwdev) { + lld_put(); + return -EINVAL; + } + + func_cap = &hwdev->cfg_mgmt->svc_cap; + memcpy(&svc_cap_info_out->cap, func_cap, sizeof(struct service_cap)); + lld_put(); + + return 0; +} + +static int get_hw_drv_version(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct drv_version_info *ver_info = buf_out; + int err; + + if (!buf_out) { + pr_err("Buf_out is NULL.\n"); + return -EINVAL; + } + + if (*out_size != sizeof(*ver_info)) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(*ver_info)); + return -EINVAL; + } + + err = snprintf(ver_info->ver, sizeof(ver_info->ver), "%s %s", + HINIC3_DRV_VERSION, __TIME_STR__); + if (err < 0) + return -EINVAL; + + return 0; +} + +static int get_pf_id(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct hinic3_pf_info *pf_info = NULL; + struct card_node *chip_node = hinic3_get_chip_node_by_lld(lld_dev); + u32 port_id; + int err; + + if (!chip_node) + return -ENODEV; + + if (!buf_out || (*out_size != sizeof(*pf_info)) || !buf_in || in_size != sizeof(u32)) { + pr_err("Unexpect out buf size from user :%u, expect: %lu, in size:%u\n", + *out_size, sizeof(*pf_info), in_size); + return -EINVAL; + } + + port_id = *((u32 *)buf_in); + pf_info = (struct hinic3_pf_info *)buf_out; + err = hinic3_get_pf_id(chip_node, port_id, &pf_info->pf_id, &pf_info->isvalid); + if (err) + return err; + + *out_size = sizeof(*pf_info); + + return 0; +} + +struct hw_drv_module_handle hw_driv_module_cmd_handle[] = { + {FUNC_TYPE, get_func_type}, + {GET_FUNC_IDX, get_func_id}, + {GET_HW_STATS, (hw_driv_module)get_hw_driver_stats}, + {CLEAR_HW_STATS, clear_hw_driver_stats}, + {GET_SELF_TEST_RES, get_self_test_result}, + {GET_CHIP_FAULT_STATS, (hw_driv_module)get_chip_faults_stats}, + {GET_SINGLE_CARD_INFO, (hw_driv_module)get_single_card_info}, + {IS_DRV_IN_VM, is_driver_in_vm}, + {GET_CHIP_ID, get_all_chip_id_cmd}, + {GET_PF_DEV_INFO, get_pf_dev_info}, + {CMD_FREE_MEM, free_knl_mem}, + {GET_CHIP_INFO, get_card_func_info}, + {GET_FUNC_CAP, get_pf_cap_info}, + {GET_DRV_VERSION, get_hw_drv_version}, + {GET_PF_ID, get_pf_id}, +}; + +static int alloc_tmp_buf(void *hwdev, struct msg_module *nt_msg, u32 in_size, + void **buf_in, u32 out_size, void **buf_out) +{ + int ret; + + ret = alloc_buff_in(hwdev, nt_msg, in_size, buf_in); + if (ret) { + pr_err("Alloc tool cmd buff in failed\n"); + return ret; + } + + ret = alloc_buff_out(hwdev, nt_msg, out_size, buf_out); + if (ret) { + pr_err("Alloc tool cmd buff out failed\n"); + goto out_free_buf_in; + } + + return 0; + +out_free_buf_in: + free_buff_in(hwdev, nt_msg, *buf_in); + + return ret; +} + +static void free_tmp_buf(void *hwdev, struct msg_module *nt_msg, + void *buf_in, void *buf_out) +{ + free_buff_out(hwdev, nt_msg, buf_out); + free_buff_in(hwdev, nt_msg, buf_in); +} + +static int send_to_hw_driver(struct hinic3_lld_dev *lld_dev, struct msg_module *nt_msg, + const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int index, num_cmds = (int)(sizeof(hw_driv_module_cmd_handle) / + sizeof(hw_driv_module_cmd_handle[0])); + enum driver_cmd_type cmd_type = + (enum driver_cmd_type)(nt_msg->msg_formate); + int err = 0; + + for (index = 0; index < num_cmds; index++) { + if (cmd_type == + hw_driv_module_cmd_handle[index].driv_cmd_name) { + err = hw_driv_module_cmd_handle[index].driv_func + (lld_dev, buf_in, in_size, buf_out, out_size); + break; + } + } + + if (index == num_cmds) { + pr_err("Can't find callback for %d\n", cmd_type); + return -EINVAL; + } + + return err; +} + +static int send_to_service_driver(struct hinic3_lld_dev *lld_dev, struct msg_module *nt_msg, + const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + const char **service_name = NULL; + enum hinic3_service_type type; + void *uld_dev = NULL; + int ret = -EINVAL; + + service_name = hinic3_get_uld_names(); + type = nt_msg->module - SEND_TO_SRV_DRV_BASE; + if (type >= SERVICE_T_MAX) { + pr_err("Ioctl input module id: %u is incorrectly\n", nt_msg->module); + return -EINVAL; + } + + uld_dev = hinic3_get_uld_dev(lld_dev, type); + if (!uld_dev) { + if (nt_msg->msg_formate == GET_DRV_VERSION) + return 0; + + pr_err("Can not get the uld dev correctly: %s driver may be not register\n", + service_name[type]); + return -EINVAL; + } + + if (g_uld_info[type].ioctl) + ret = g_uld_info[type].ioctl(uld_dev, nt_msg->msg_formate, + buf_in, in_size, buf_out, out_size); + uld_dev_put(lld_dev, type); + + return ret; +} + +static int nictool_exec_cmd(struct hinic3_lld_dev *lld_dev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int ret = 0; + + switch (nt_msg->module) { + case SEND_TO_HW_DRIVER: + ret = send_to_hw_driver(lld_dev, nt_msg, buf_in, in_size, buf_out, out_size); + break; + case SEND_TO_MPU: + ret = send_to_mpu(hinic3_get_sdk_hwdev_by_lld(lld_dev), + nt_msg, buf_in, in_size, buf_out, out_size); + break; + case SEND_TO_SM: + ret = send_to_sm(hinic3_get_sdk_hwdev_by_lld(lld_dev), + nt_msg, buf_in, in_size, buf_out, out_size); + break; + case SEND_TO_NPU: + ret = send_to_npu(hinic3_get_sdk_hwdev_by_lld(lld_dev), + nt_msg, buf_in, in_size, buf_out, out_size); + break; + default: + ret = send_to_service_driver(lld_dev, nt_msg, buf_in, in_size, buf_out, out_size); + break; + } + + return ret; +} + +static int cmd_parameter_valid(struct msg_module *nt_msg, unsigned long arg, + u32 *out_size_expect, u32 *in_size) +{ + if (copy_from_user(nt_msg, (void *)arg, sizeof(*nt_msg))) { + pr_err("Copy information from user failed\n"); + return -EFAULT; + } + + *out_size_expect = nt_msg->buf_out_size; + *in_size = nt_msg->buf_in_size; + if (*out_size_expect > HINIC3_MAX_BUF_SIZE || + *in_size > HINIC3_MAX_BUF_SIZE) { + pr_err("Invalid in size: %u or out size: %u\n", + *in_size, *out_size_expect); + return -EFAULT; + } + + nt_msg->device_name[IFNAMSIZ - 1] = '\0'; + + return 0; +} + +static struct hinic3_lld_dev *get_lld_dev_by_nt_msg(struct msg_module *nt_msg) +{ + struct hinic3_lld_dev *lld_dev = NULL; + + if (nt_msg->module == SEND_TO_NIC_DRIVER && (nt_msg->msg_formate == GET_XSFP_INFO || + nt_msg->msg_formate == GET_XSFP_PRESENT)) { + lld_dev = hinic3_get_lld_dev_by_chip_and_port(nt_msg->device_name, nt_msg->port_id); + } else if (nt_msg->module == SEND_TO_CUSTOM_DRIVER && nt_msg->msg_formate == CMD_CUSTOM_BOND_GET_CHIP_NAME) { + lld_dev = hinic3_get_lld_dev_by_dev_name(nt_msg->device_name, SERVICE_T_MAX); + } else if (nt_msg->module == SEND_TO_VBS_DRIVER) { + lld_dev = hinic3_get_lld_dev_by_chip_name(nt_msg->device_name); + } else if (nt_msg->module >= SEND_TO_SRV_DRV_BASE && nt_msg->module < SEND_TO_DRIVER_MAX + && nt_msg->msg_formate != GET_DRV_VERSION) { + lld_dev = hinic3_get_lld_dev_by_dev_name(nt_msg->device_name, + nt_msg->module - SEND_TO_SRV_DRV_BASE); + } else { + lld_dev = hinic3_get_lld_dev_by_chip_name(nt_msg->device_name); + if (!lld_dev) + lld_dev = hinic3_get_lld_dev_by_dev_name(nt_msg->device_name, SERVICE_T_MAX); + } + + return lld_dev; +} + +static long hinicadm_k_unlocked_ioctl(struct file *pfile, unsigned long arg) +{ + struct hinic3_lld_dev *lld_dev = NULL; + struct msg_module nt_msg; + void *buf_out = NULL; + void *buf_in = NULL; + u32 out_size_expect = 0; + u32 out_size = 0; + u32 in_size = 0; + int ret = 0; + + memset(&nt_msg, 0, sizeof(nt_msg)); + if (cmd_parameter_valid(&nt_msg, arg, &out_size_expect, &in_size)) + return -EFAULT; + + lld_dev = get_lld_dev_by_nt_msg(&nt_msg); + if (!lld_dev) { + if (nt_msg.msg_formate != DEV_NAME_TEST) + pr_err("Can not find device %s for module %u\n", + nt_msg.device_name, nt_msg.module); + + return -ENODEV; + } + + if (nt_msg.msg_formate == DEV_NAME_TEST) { + lld_dev_put(lld_dev); + return 0; + } + + ret = alloc_tmp_buf(hinic3_get_sdk_hwdev_by_lld(lld_dev), &nt_msg, + in_size, &buf_in, out_size_expect, &buf_out); + if (ret) { + pr_err("Alloc tmp buff failed\n"); + goto out_free_lock; + } + + out_size = out_size_expect; + + ret = nictool_exec_cmd(lld_dev, &nt_msg, buf_in, in_size, buf_out, &out_size); + if (ret) { + pr_err("nictool_exec_cmd failed, module: %u, ret: %d.\n", nt_msg.module, ret); + goto out_free_buf; + } + + if (out_size > out_size_expect) { + ret = -EFAULT; + pr_err("Out size is greater than expected out size from user: %u, out size: %u\n", + out_size_expect, out_size); + goto out_free_buf; + } + + ret = copy_buf_out_to_user(&nt_msg, out_size, buf_out); + if (ret) + pr_err("Copy information to user failed\n"); + +out_free_buf: + free_tmp_buf(hinic3_get_sdk_hwdev_by_lld(lld_dev), &nt_msg, buf_in, buf_out); + +out_free_lock: + lld_dev_put(lld_dev); + return (long)ret; +} + +/** + * dbgtool_knl_ffm_info_rd - Read ffm information + * @para: the dbgtool parameter + * @dbgtool_info: the dbgtool info + **/ +static long dbgtool_knl_ffm_info_rd(struct dbgtool_param *para, + struct dbgtool_k_glb_info *dbgtool_info) +{ + if (!para->param.ffm_rd || !dbgtool_info->ffm) + return -EINVAL; + + /* Copy the ffm_info to user mode */ + if (copy_to_user(para->param.ffm_rd, dbgtool_info->ffm, + (unsigned int)sizeof(struct ffm_record_info))) { + pr_err("Copy ffm_info to user fail\n"); + return -EFAULT; + } + + return 0; +} + +static long dbgtool_k_unlocked_ioctl(struct file *pfile, + unsigned int real_cmd, + unsigned long arg) +{ + long ret; + struct dbgtool_param param; + struct dbgtool_k_glb_info *dbgtool_info = NULL; + struct card_node *card_info = NULL; + int i; + + memset(¶m, 0, sizeof(param)); + + if (copy_from_user(¶m, (void *)arg, sizeof(param))) { + pr_err("Copy param from user fail\n"); + return -EFAULT; + } + + lld_hold(); + for (i = 0; i < MAX_CARD_NUM; i++) { + card_info = (struct card_node *)g_card_node_array[i]; + if (!card_info) + continue; + if (memcmp(param.chip_name, card_info->chip_name, strlen(card_info->chip_name) + 1) == 0) + break; + } + + if (i == MAX_CARD_NUM || !card_info) { + lld_put(); + pr_err("Can't find this card.\n"); + return -EFAULT; + } + + card_id = i; + dbgtool_info = (struct dbgtool_k_glb_info *)card_info->dbgtool_info; + + down(&dbgtool_info->dbgtool_sem); + + switch (real_cmd) { + case DBGTOOL_CMD_FFM_RD: + ret = dbgtool_knl_ffm_info_rd(¶m, dbgtool_info); + break; + case DBGTOOL_CMD_MSG_2_UP: + pr_err("Not suppose to use this cmd(0x%x).\n", real_cmd); + ret = 0; + break; + default: + pr_err("Dbgtool cmd(0x%x) not support now\n", real_cmd); + ret = -EFAULT; + break; + } + + up(&dbgtool_info->dbgtool_sem); + + lld_put(); + + return ret; +} + +static int nictool_k_release(struct inode *pnode, struct file *pfile) +{ + return 0; +} + +static int nictool_k_open(struct inode *pnode, struct file *pfile) +{ + return 0; +} + +static ssize_t nictool_k_read(struct file *pfile, char __user *ubuf, + size_t size, loff_t *ppos) +{ + return 0; +} + +static ssize_t nictool_k_write(struct file *pfile, const char __user *ubuf, + size_t size, loff_t *ppos) +{ + return 0; +} + +static long nictool_k_unlocked_ioctl(struct file *pfile, + unsigned int cmd, unsigned long arg) +{ + unsigned int real_cmd; + + real_cmd = _IOC_NR(cmd); + + return (real_cmd == NICTOOL_CMD_TYPE) ? + hinicadm_k_unlocked_ioctl(pfile, arg) : + dbgtool_k_unlocked_ioctl(pfile, real_cmd, arg); +} + +static int hinic3_mem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + pgprot_t vm_page_prot; + unsigned long vmsize = vma->vm_end - vma->vm_start; + phys_addr_t offset = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT; + phys_addr_t phy_addr; + int err = 0; + + if (vmsize > (PAGE_SIZE * (1 << DBGTOOL_PAGE_ORDER))) { + pr_err("Map size = %lu is bigger than alloc\n", vmsize); + return -EAGAIN; + } + + /* old version of tool set vma->vm_pgoff to 0 */ + phy_addr = offset ? offset : g_card_phy_addr[card_id]; + /* check phy_addr valid */ + if (phy_addr != g_card_phy_addr[card_id]) { + err = hinic3_bar_mmap_param_valid(phy_addr, vmsize); + if (err != 0) { + pr_err("mmap param invalid, err: %d\n", err); + return err; + } + } + + /* Disable cache and write buffer in the mapping area */ + vm_page_prot = pgprot_noncached(vma->vm_page_prot); + vma->vm_page_prot = vm_page_prot; + if (remap_pfn_range(vma, vma->vm_start, (phy_addr >> PAGE_SHIFT), + vmsize, vma->vm_page_prot)) { + pr_err("Remap pfn range failed.\n"); + return -EAGAIN; + } + + return 0; +} + +static const struct file_operations fifo_operations = { + .owner = THIS_MODULE, + .release = nictool_k_release, + .open = nictool_k_open, + .read = nictool_k_read, + .write = nictool_k_write, + .unlocked_ioctl = nictool_k_unlocked_ioctl, + .mmap = hinic3_mem_mmap, +}; + +static void free_dbgtool_info(void *hwdev, struct card_node *chip_info) +{ + struct dbgtool_k_glb_info *dbgtool_info = NULL; + + if (hinic3_func_type(hwdev) != TYPE_VF) + chip_info->func_handle_array[hinic3_global_func_id(hwdev)] = NULL; + + if (--chip_info->func_num) + return; + + if (chip_info->chip_id >= 0 && chip_info->chip_id < MAX_CARD_NUM) + g_card_node_array[chip_info->chip_id] = NULL; + + dbgtool_info = chip_info->dbgtool_info; + /* FFM deinit */ + if (dbgtool_info && dbgtool_info->ffm) { + kfree(dbgtool_info->ffm); + dbgtool_info->ffm = NULL; + } + + if (dbgtool_info) + kfree(dbgtool_info); + + chip_info->dbgtool_info = NULL; + + if (chip_info->chip_id >= 0 && chip_info->chip_id < MAX_CARD_NUM) + dbgtool_knl_free_mem(chip_info->chip_id); +} + +static int alloc_dbgtool_info(void *hwdev, struct card_node *chip_info) +{ + struct dbgtool_k_glb_info *dbgtool_info = NULL; + int err, id = 0; + + if (hinic3_func_type(hwdev) != TYPE_VF) + chip_info->func_handle_array[hinic3_global_func_id(hwdev)] = hwdev; + + if (chip_info->func_num++) + return 0; + + dbgtool_info = (struct dbgtool_k_glb_info *) + kzalloc(sizeof(struct dbgtool_k_glb_info), GFP_KERNEL); + if (!dbgtool_info) { + pr_err("Failed to allocate dbgtool_info\n"); + goto dbgtool_info_fail; + } + + chip_info->dbgtool_info = dbgtool_info; + + /* FFM init */ + dbgtool_info->ffm = (struct ffm_record_info *) + kzalloc(sizeof(struct ffm_record_info), GFP_KERNEL); + if (!dbgtool_info->ffm) { + pr_err("Failed to allocate cell contexts for a chain\n"); + goto dbgtool_info_ffm_fail; + } + + sema_init(&dbgtool_info->dbgtool_sem, 1); + + err = sscanf(chip_info->chip_name, HINIC3_CHIP_NAME "%d", &id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + goto sscanf_chdev_fail; + } + + g_card_node_array[id] = chip_info; + + return 0; + +sscanf_chdev_fail: + kfree(dbgtool_info->ffm); + +dbgtool_info_ffm_fail: + kfree(dbgtool_info); + chip_info->dbgtool_info = NULL; + +dbgtool_info_fail: + if (hinic3_func_type(hwdev) != TYPE_VF) + chip_info->func_handle_array[hinic3_global_func_id(hwdev)] = NULL; + chip_info->func_num--; + return -ENOMEM; +} + +/** + * nictool_k_init - initialize the hw interface + **/ +/* temp for dbgtool_info */ + +int nictool_k_init(void *hwdev, void *chip_node) +{ + struct card_node *chip_info = (struct card_node *)chip_node; + struct device *pdevice = NULL; + int err; + + err = alloc_dbgtool_info(hwdev, chip_info); + if (err) + return err; + + if (g_nictool_ref_cnt++) { + /* already initialized */ + return 0; + } + + err = alloc_chrdev_region(&g_dev_id, 0, 1, HIADM3_DEV_NAME); + if (err) { + pr_err("Register nictool_dev failed(0x%x)\n", err); + goto alloc_chdev_fail; + } + + /* Create equipment */ + g_nictool_class = class_create(THIS_MODULE, HIADM3_DEV_CLASS); + if (IS_ERR(g_nictool_class)) { + pr_err("Create nictool_class fail\n"); + err = -EFAULT; + goto class_create_err; + } + + /* Initializing the character device */ + cdev_init(&g_nictool_cdev, &fifo_operations); + + /* Add devices to the operating system */ + err = cdev_add(&g_nictool_cdev, g_dev_id, 1); + if (err < 0) { + pr_err("Add nictool_dev to operating system fail(0x%x)\n", err); + goto cdev_add_err; + } + + /* Export device information to user space + * (/sys/class/class name/device name) + */ + pdevice = device_create(g_nictool_class, NULL, + g_dev_id, NULL, HIADM3_DEV_NAME); + if (IS_ERR(pdevice)) { + pr_err("Export nictool device information to user space fail\n"); + err = -EFAULT; + goto device_create_err; + } + + pr_info("Register nictool_dev to system succeed\n"); + + return 0; + +device_create_err: + cdev_del(&g_nictool_cdev); + +cdev_add_err: + class_destroy(g_nictool_class); + +class_create_err: + g_nictool_class = NULL; + unregister_chrdev_region(g_dev_id, 1); + +alloc_chdev_fail: + g_nictool_ref_cnt--; + free_dbgtool_info(hwdev, chip_info); + + return err; +} + +void nictool_k_uninit(void *hwdev, void *chip_node) +{ + struct card_node *chip_info = (struct card_node *)chip_node; + + free_dbgtool_info(hwdev, chip_info); + + if (!g_nictool_ref_cnt) + return; + + if (--g_nictool_ref_cnt) + return; + + if (IS_ERR(g_nictool_class)) { + pr_err("Nictool class is NULL.\n"); + return; + } + + device_destroy(g_nictool_class, g_dev_id); + cdev_del(&g_nictool_cdev); + class_destroy(g_nictool_class); + g_nictool_class = NULL; + + unregister_chrdev_region(g_dev_id, 1); + + pr_info("Unregister nictool_dev succeed\n"); +} + diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.h b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.h new file mode 100644 index 000000000..f368133e3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#ifndef HINIC3_NICTOOL_H +#define HINIC3_NICTOOL_H + +#include "hinic3_mt.h" +#include "hinic3_crm.h" + +#ifndef MAX_SIZE +#define MAX_SIZE (16) +#endif + +#define DBGTOOL_PAGE_ORDER (10) + +#define MAX_CARD_NUM (64) + +int nictool_k_init(void *hwdev, void *chip_node); +void nictool_k_uninit(void *hwdev, void *chip_node); + +void hinic3_get_all_chip_id(void *id_info); + +void hinic3_get_card_func_info_by_card_name + (const char *chip_name, struct hinic3_card_func_info *card_func); + +void hinic3_get_card_info(const void *hwdev, void *bufin); + +bool hinic3_is_in_host(void); + +int hinic3_get_pf_id(struct card_node *chip_node, u32 port_id, u32 *pf_id, u32 *isvalid); + +extern struct hinic3_uld_info g_uld_info[SERVICE_T_MAX]; + +#endif + diff --git a/drivers/infiniband/hw/hiroce3/host/mt/readme.txt b/drivers/infiniband/hw/hiroce3/host/mt/readme.txt new file mode 100644 index 000000000..08ab9134c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/readme.txt @@ -0,0 +1 @@ +本目录是诊断维护代码目录 \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/vram/vram_common.c b/drivers/infiniband/hw/hiroce3/host/vram/vram_common.c new file mode 100644 index 000000000..4a12a7c74 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/vram/vram_common.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * Description: Header File, vram common + * Create: 2023/7/19 + */ +#include <linux/kallsyms.h> +#include <linux/errno.h> +#include <linux/version.h> + +#include "ossl_knl.h" +#include "vram_common.h" + +static int g_use_vram = 0; +static int g_in_kexec = 0; + +static register_nvwa_notifier_t _register_nvwa_notifier = NULL; +static unregister_nvwa_notifier_t _unregister_nvwa_notifier = NULL; +static register_euleros_reboot_notifier_t _register_euleros_reboot_notifier = NULL; +static unregister_euleros_reboot_notifier_t _unregister_euleros_reboot_notifier = NULL; +static vram_kalloc_t _vram_kalloc = NULL; +static vram_kfree_t _vram_kfree = NULL; +static vram_get_gfp_vram _vram_get_gfp_vram = NULL; + +int hi_register_nvwa_notifier(int hook, struct notifier_block *nb) +{ + if (_register_nvwa_notifier) { + return _register_nvwa_notifier(hook, nb); + } + + return -EINVAL; +} +EXPORT_SYMBOL(hi_register_nvwa_notifier); + +int hi_unregister_nvwa_notifier(int hook, struct notifier_block *nb) +{ + if (_unregister_nvwa_notifier) { + return _unregister_nvwa_notifier(hook, nb); + } + + return -EINVAL; +} +EXPORT_SYMBOL(hi_unregister_nvwa_notifier); + +int hi_register_euleros_reboot_notifier(struct notifier_block *nb) +{ + if (_register_euleros_reboot_notifier) + return _register_euleros_reboot_notifier(nb); + + return -EINVAL; +} +EXPORT_SYMBOL(hi_register_euleros_reboot_notifier); + +int hi_unregister_euleros_reboot_notifier(struct notifier_block *nb) +{ + if (_unregister_euleros_reboot_notifier) + return _unregister_euleros_reboot_notifier(nb); + + return -EINVAL; +} +EXPORT_SYMBOL(hi_unregister_euleros_reboot_notifier); + +void __iomem *hi_vram_kalloc(char *name, u64 size) +{ + if (_vram_kalloc) { + return _vram_kalloc(name, size); + } + + return NULL; +} +EXPORT_SYMBOL(hi_vram_kalloc); + +void hi_vram_kfree(void __iomem *vaddr, char *name, u64 size) +{ + if (_vram_kfree && vaddr) { + _vram_kfree(vaddr, name, size); + } + + return; +} +EXPORT_SYMBOL(hi_vram_kfree); + +gfp_t hi_vram_get_gfp_vram(void) +{ + if (_vram_get_gfp_vram) { + return _vram_get_gfp_vram(); + } + return 0; +} +EXPORT_SYMBOL(hi_vram_get_gfp_vram); + +void lookup_vram_related_symbols(void) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + _register_nvwa_notifier = (register_nvwa_notifier_t) + kallsyms_lookup_name("register_nvwa_notifier"); + + _unregister_nvwa_notifier = (unregister_nvwa_notifier_t) + kallsyms_lookup_name("unregister_nvwa_notifier"); + + _register_euleros_reboot_notifier = (register_euleros_reboot_notifier_t) + kallsyms_lookup_name("register_euleros_reboot_notifier"); + + _unregister_euleros_reboot_notifier = (unregister_euleros_reboot_notifier_t) + kallsyms_lookup_name("unregister_euleros_reboot_notifier"); + + _vram_kalloc = (vram_kalloc_t) + kallsyms_lookup_name("vram_kalloc"); + + _vram_kfree = (vram_kfree_t) + kallsyms_lookup_name("vram_kfree"); + + _vram_get_gfp_vram = (vram_get_gfp_vram) + kallsyms_lookup_name("vram_get_vram_gfp_t"); +#else +// openEuler: the symbol table cannot be scanned in kernel versions later than 5.10. +#if (!defined(HIUDK_OPENEULER)) + _register_nvwa_notifier = (register_nvwa_notifier_t) + kallsyms_lookup_name_wrap("register_nvwa_notifier"); + + _unregister_nvwa_notifier = (unregister_nvwa_notifier_t) + kallsyms_lookup_name_wrap("unregister_nvwa_notifier"); + + _register_euleros_reboot_notifier = (register_euleros_reboot_notifier_t) + kallsyms_lookup_name_wrap("register_euleros_reboot_notifier"); + + _unregister_euleros_reboot_notifier = (unregister_euleros_reboot_notifier_t) + kallsyms_lookup_name_wrap("unregister_euleros_reboot_notifier"); + + _vram_kalloc = (vram_kalloc_t) + kallsyms_lookup_name_wrap("vram_kalloc"); + + _vram_kfree = (vram_kfree_t) + kallsyms_lookup_name_wrap("vram_kfree"); + + _vram_get_gfp_vram = (vram_get_gfp_vram) + kallsyms_lookup_name_wrap("vram_get_vram_gfp_t"); +#endif +#endif +} +EXPORT_SYMBOL(lookup_vram_related_symbols); + +int hi_set_kexec_status(int status) +{ + int *kexec_status_addr = NULL; + + kexec_status_addr = hi_vram_kalloc(KEXEC_SIGN, VRAM_BLOCK_SIZE_2M); + if (!kexec_status_addr) { + pr_err("set kexec status vram kalloc failed.\n"); + return -ENOMEM; + } + + *kexec_status_addr = status; + g_in_kexec = *kexec_status_addr; + + return 0; +} +EXPORT_SYMBOL(hi_set_kexec_status); + +int hi_get_kexec_status(void) +{ + int *kexec_status_addr = NULL; + + kexec_status_addr = hi_vram_kalloc(KEXEC_SIGN, VRAM_BLOCK_SIZE_2M); + if (!kexec_status_addr) { + pr_err("get kexec status vram kalloc failed.\n"); + return -ENOMEM; + } + + g_in_kexec = *kexec_status_addr; + hi_vram_kfree((void *)kexec_status_addr, KEXEC_SIGN, VRAM_BLOCK_SIZE_2M); + + return 0; +} +EXPORT_SYMBOL(hi_get_kexec_status); + +int get_use_vram_flag(void) +{ + return g_use_vram; +} +EXPORT_SYMBOL(get_use_vram_flag); + +void set_use_vram_flag(bool flag) +{ + g_use_vram = flag; +} +EXPORT_SYMBOL(set_use_vram_flag); + +int vram_get_kexec_flag(void) +{ + return g_in_kexec; +} +EXPORT_SYMBOL(vram_get_kexec_flag); diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd.h new file mode 100644 index 000000000..c146d17de --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd.h @@ -0,0 +1,38 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_mpu_cmd.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_MPU_CMD_H +#define HISEC_MPU_CMD_H + +/** + * @brief Crypto driver to MPU Commands + * + */ +typedef enum hisec_mpu_cmd { + HISEC_MPU_CMD_SET_IPSEC_OFFLOAD_MODE = 2, /**< MPU crypt set IPsec offload mode + @see struct hisec_cmd_ipsec_offload_mode */ + HISEC_MPU_CMD_GET_CRYPTO_STATS = 3, /**< MPU crypt get crypto states + @see struct hisec_cmd_cryptodev_stats */ + HISEC_MPU_CMD_GET_IPSEC_SAD = 4, /**< MPU crypt get IPsec SAD + @see struct hisec_cmd_sml_table */ + HISEC_MPU_CMD_GET_IPSEC_SPD = 5, /**< MPU crypt get IPsec SPD + @see struct hisec_cmd_sml_table */ + HISEC_MPU_CMD_GET_IPSEC_ITEM_CNT = 6, /**< MPU crypt get IPsec item count + @see struct hisec_cmd_ipsec_item_cnt */ + HISEC_MPU_CMD_SET_IPSEC_CTRL_HOST = 7, /**< MPU cpypt set IPsec ctrl host + @see struct hisec_cmd_ipsec_ctrl_host */ + + HISEC_MPU_CMD_MAX = 255 +} hisec_mpu_cmd_type_e; + +#endif /* HISEC_MPU_CMD_H */ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd_defs.h new file mode 100644 index 000000000..02ed077a2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd_defs.h @@ -0,0 +1,118 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_mpu_cmd_defs.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_MPU_CMD_DEFS_H +#define HISEC_MPU_CMD_DEFS_H + +#include "mpu_cmd_base_defs.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#define IPSEC_SML_TBL_BUF_MAX 768 + +/** + * @brief HISec set ipsec offload mode command struct defination + * @see HISEC_MPU_CMD_SET_IPSEC_OFFLOAD_MODE + * + */ +struct hisec_cmd_ipsec_offload_mode { + struct comm_info_head msg_head; /**< Common information head */ + u16 func_id; /**< Function id */ + u8 offload_mode; /**< Offload mode, 0: disable 1: xfrm offload 2:ipsec full offload */ + u8 rsvd1[5]; +}; + +/** + * @brief HISec set ipsec ctrl host command struct defination + * @see HISEC_MPU_CMD_SET_IPSEC_CTRL_HOST + * + */ +struct hisec_cmd_ipsec_ctrl_host { + struct comm_info_head msg_head; /**< Common information head */ + u16 func_id; /**< IPSec Function ID */ + u16 host_id; /**< IPSec owner controller host */ + u8 rsvd1[4]; +}; + +/** + * @brief HISec crypto state description + * + */ +struct hisec_crypto_stats { + u64 cryrx_auth_err; /**< Crypto rx authority error */ + u64 cryrx_tfc_pad_err; /**< Crypto rx tfc pad error */ + u64 cryrx_other_err; /**< Crypto rx other error */ + u64 crytx_bd_err; /**< Crypto tx bd error */ + u64 crytx_len_err; /**< Crypto tx length error */ +}; + +/** + * @brief HISec get crypto device states command struct defination + * @see HISEC_MPU_CMD_GET_CRYPTO_STATS + * + */ +struct hisec_cmd_cryptodev_stats { + struct comm_info_head msg_head; /**< Common information head */ + struct hisec_crypto_stats stats; /**< Crypto device states */ +}; + +/** + * @brief HISec get ipsec item count command struct defination + * @see HISEC_MPU_CMD_GET_IPSEC_ITEM_CNT + * + */ +struct hisec_cmd_ipsec_item_cnt { + struct comm_info_head msg_head; /**< Common information head */ + u32 sp_item_cnt; /**< SP item count */ + u32 sa_item_cnt; /**< SA item count */ + u16 func_id; /**< Function id */ + u16 pad; +}; + +/** + * @brief IPSec SML table arguments, used by struct hisec_cmd_sml_table + * + */ +typedef union { + struct { + u32 tbl_index; + u32 cnt; + u32 total_cnt; + u32 pad; + } tbl_arg; + + u32 args[4]; +} ipsec_sml_tbl_args; + +/** + * @brief HISec get ipsec sad or spd command struct defination + * @see HISEC_MPU_CMD_GET_IPSEC_SAD + * @see HISEC_MPU_CMD_GET_IPSEC_SPD + * + */ +struct hisec_cmd_sml_table { + struct comm_info_head msg_head; /**< Common information head */ + u16 func_id; /**< Function ID */ + u16 pad; + u32 tbl_type; /**< SML table type, unused */ + ipsec_sml_tbl_args args; /**< SML table arguments */ + u8 tbl_buf[IPSEC_SML_TBL_BUF_MAX]; /**< SML table data buffer */ +}; + +#endif /** HISEC_MPU_CMD_DEFS_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd.h new file mode 100644 index 000000000..6c229ae62 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd.h @@ -0,0 +1,30 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_npu_cmd.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_NPU_CMD_H +#define HISEC_NPU_CMD_H + +/** Crypto driver to NPU Commands */ +typedef enum hisec_npu_cmd_type { + HISEC_NPU_CMD_SET_IPSEC_SA, /**< IPsec SA child context 256B @see struct tag_hisec_cmd_set_ipsec_sa */ + HISEC_NPU_CMD_SET_IPSEC_SP, /**< IPsec Secure Policy @see struct tag_hisec_cmd_set_ipsec_sp */ + HISEC_NPU_CMD_CALC_DH, /**< IPsec Calculate DH @see struct tag_hisec_cmd_calc_dh */ + HISEC_NPU_CMD_FLUSH_IPSEC_RES, /**< IPsec flush resource @see struct tag_hisec_cmd_flush_ipsec_res */ + HISEC_NPU_CMD_INIT_SCQC, /**< IPsec init scqc @see struct tag_hisec_cmd_init_scqc */ + HISEC_NPU_CMD_DEINIT_SCQC, /**< IPsec uninit scqc @see struct tag_hisec_cmd_deinit_scqc */ + HISEC_NPU_CMD_HW_RANDOM, /**< IPsec hardware random @see struct hisec_cmd_trng_module */ + + HISEC_NPU_CMD_MAX = 255 +} hisec_npu_cmd_type_e; + +#endif /* HISEC_NPU_CMD_H */ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd_defs.h new file mode 100644 index 000000000..3f0826591 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd_defs.h @@ -0,0 +1,415 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_npu_cmd_defs.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_NPU_CMD_DEFS_H +#define HISEC_NPU_CMD_DEFS_H + +#include "mpu_cmd_base_defs.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#define RESP_DATA_LEN_MAX 32 + +/** + * @brief hisec command common header + * + */ +typedef struct tag_hisec_cmd_hdr { + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 rsvd0 : 16; + + /** Logical concurrency channel */ + u32 channel_id : 8; + + /** Command type, @see hisec_npu_cmd_type_e */ + u32 cmd_type : 8; +#else + /** Command type, @see hisec_npu_cmd_type_e */ + u32 cmd_type : 8; + + /** Logical concurrency channel */ + u32 channel_id : 8; + u32 rsvd0 : 16; +#endif + } bs; + u32 value; + } dw0; + + /** Command serial number */ + u32 cmd_sn; + u32 rsvd1[2]; +} hisec_cmd_hdr_s; + +/** + * @brief HiSec init scqc command struct defination + * @see HISEC_NPU_CMD_INIT_SCQC + * + */ +typedef struct tag_hisec_cmd_init_scqc { + hisec_cmd_hdr_s cmdhdr; + + u32 scqn; + u32 rsvd; + u32 scqc[10]; +} hisec_cmd_init_scqc_s; + +/** + * @brief Hisec deinit scqc command struct defination + * @see HISEC_NPU_CMD_DEINIT_SCQC + * + */ +typedef struct tag_hisec_cmd_deinit_scqc { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + + u32 scqn; + u32 resvd[11]; +} hisec_cmd_deinit_scqc_s; + +/** + * @brief HISec flush ipsec resource struct defination + * @see HISEC_NPU_CMD_FLUSH_IPSEC_RES + * + */ +typedef struct tag_hisec_cmd_flush_ipsec_res { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + + u16 func_id; + u16 rsvd0; + u32 flush_flag; + u32 rsvd1; +} hisec_cmd_flush_ipsec_res_s; + +/** + * @brief HISec SA encrypt information + * + */ +typedef struct tag_hisec_sa_enc_info { + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 proto : 8; /**< tcp/udp */ + u32 direction : 8; /**< out/in */ + u32 mode : 8; /**< 0 transport/ 1 tunnel */ + u32 flag : 8; /**< 1 -esn */ +#else + u32 flag : 8; + u32 mode : 8; + u32 direction : 8; + u32 proto : 8; +#endif + } bs; + u32 value; + } enc_dw0; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 replaywindow : 16; /**< 32-64 */ + u32 alg_type : 8; /**< 0- aead 1-enc 2-auth 3-enc & auth */ + u32 alg_standard : 8; /**< 0 - aes, 3 - SM4 */ +#else + u32 alg_standard : 8; + u32 alg_type : 8; + u32 replaywindow : 16; +#endif + } bs; + u32 value; + } enc_dw1; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 enc_type : 8; /**< hisec_crypto_alg_type */ + u32 auth_type : 8; /**< hisec_crypto_alg_type */ + u32 cipher_key_len : 16; /**< in bit */ +#else + u32 cipher_key_len : 16; + u32 auth_type : 8; + u32 enc_type : 8; +#endif + } bs; + u32 value; + } enc_dw2; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 auth_key_len : 16; /**< in bit */ + u32 auth_trunc_len : 16; /**< in bit */ +#else + u32 auth_trunc_len : 16; + u32 auth_key_len : 16; +#endif + } bs; + u32 value; + } enc_dw3; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 icv_mac_len : 16; /**< in bit */ + u32 rsvd1 : 16; +#else + u32 rsvd1 : 16; + u32 icv_mac_len : 16; + +#endif + } bs; + u32 value; + } enc_dw4; + + u32 salt; /**< 32bit */ + + u32 pad[2]; + + u32 cipher_key[8]; /**< 128bit 192bit 256bit */ + u32 auth_key[8]; /**< 256bit */ +} hisec_sa_enc_info_s; + +/** + * @brief HISec SA tuples + * + */ +typedef struct tag_hisec_sa_tuples { + u32 daddr[4]; /**< ipv4 in daddr[0] */ + u32 spi; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 ipsec_proto : 8; + u32 iptype : 8; /**< 0-ipv4 1-ipv6 */ + u32 rsvd : 16; +#else + u32 rsvd : 16; + u32 iptype : 8; + u32 ipsec_proto : 8; +#endif + } bs; + u32 value; + } tup_dw0; + + u32 pad[2]; +} hisec_sa_tuples_s; + +/** + * @brief IPsec SA msg 160B struct defination + * @see HISEC_NPU_CMD_SET_IPSEC_SA + * + */ +typedef struct tag_hisec_cmd_set_ipsec_sa { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header, 16B */ + + hisec_sa_tuples_s tuples; /**< 32B */ + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 opid : 8; /**< 0-add 1-del 2-update 3-flush */ + u32 rsvd0 : 24; +#else + u32 rsvd0 : 24; + u32 opid : 8; +#endif + } bs; + u32 value; + } sa_dw0; + + u32 scqn; /**< used for scqe sa aging update msg notify */ + + u32 pad[2]; + + hisec_sa_enc_info_s enc_info; +} hisec_cmd_set_ipsec_sa_s; + +/** + * @brief HISec SP tuples + * + */ +typedef struct tag_hisec_sp_tuples { + u32 saddr[4]; /**< ipv4 in saddr[0] */ + u32 daddr[4]; /**< ipv4 in daddr[0] */ + u32 sa_masklen; + u32 da_masklen; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 dport : 16; + u32 sport : 16; +#else + u32 sport : 16; + u32 dport : 16; +#endif + } bs; + u32 value; + } tup_dw0; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 dport_mask : 16; + u32 sport_mask : 16; +#else + u32 sport_mask : 16; + u32 dport_mask : 16; +#endif + } bs; + u32 value; + } tup_dw1; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 ulp_proto : 8; /**< tcp/udp */ + u32 iptype : 8; /**< 0-ipv4 1-ipv6 */ + u32 rsvd0 : 16; +#else + u16 rsvd0; + u8 iptype; + u8 ulp_proto; +#endif + } bs; + u32 value; + } tup_dw2; + + u32 pad[3]; +} hisec_sp_tuples_s; + +/** + * @brief HISec set ipsec SP command struct defination + * @see HISEC_NPU_CMD_SET_IPSEC_SP, IPsec SP msg 128B + * + */ +typedef struct tag_hisec_cmd_set_ipsec_sp { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + hisec_sp_tuples_s tuples; + u32 spi; + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 ipsec_proto : 8; /**< 50-esp 51-ah */ + u32 opid : 8; /**< 0-add 1-del 2-update */ + u32 action : 8; /**< 0-bypass 1-encrypted */ + u32 rsvd0 : 8; +#else + u32 rsvd0 : 8; + u32 action : 8; + u32 opid : 8; + u32 ipsec_proto : 8; +#endif + } bs; + u32 value; + } sp_dw0; + + u32 pad[10]; +} hisec_cmd_set_ipsec_sp_s; + +/** + * @brief HISec DH parameters, used by hisec_cmd_calc_dh_s + * + */ +typedef struct tag_hisec_cmd_dh_param { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u16 generator; + /** DH phase, 1:DH Phase1 2:DH Phase 2 */ + u8 dh_phase; + /** DH group id */ + u8 dh_groupid; +#else + /** DH group id */ + u8 dh_groupid; + /** DH phase, 1:DH Phase1 2:DH Phase 2 */ + u8 dh_phase; + u16 generator; +#endif + +#if (BYTE_ORDER == LITTLE_ENDIAN) + u16 privkey_len; + u16 modp_len; +#else + u16 modp_len; + u16 privkey_len; +#endif + +#if (BYTE_ORDER == LITTLE_ENDIAN) + u16 rsvd0; + u16 pubkey_len; +#else + u16 pubkey_len; + u16 rsvd0; +#endif + + u32 rsvd1[13]; + + u32 modprime[128]; /**< public prime number */ + u32 private_key[128]; /**< private Xa */ + u32 public_key[128]; /**< public Yb */ +} hisec_cmd_dh_param_s; + +/** + * @brief HISec calculate DH command struct defination + * @see HISEC_NPU_CMD_CALC_DH + * + */ +typedef struct tag_hisec_cmd_calc_dh { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + + /** writeback result PhyAddr */ + u32 buf_len; + u32 buf_gpah; + u32 buf_gpal; + + /** writeback result LogicalVirtualAddr */ + u32 buf_vah; + u32 buf_val; + + /** detect memory tramp */ + u32 magic_h; + u32 magic_l; + + u32 scqn; + u32 rsvd[4]; + + hisec_cmd_dh_param_s dh_param; +} hisec_cmd_calc_dh_s; + +/** + * @brief HISec hardware random calculation response data, used by hisec_cmd_trng_module_s + * + */ +typedef struct trng_data_resp { + u32 status; + u32 data_out[RESP_DATA_LEN_MAX]; +} trng_data_resp_s; + +/** + * @brief HISec hardware random command struct defination + * @see HISEC_NPU_CMD_HW_RANDOM + * + */ +typedef struct hisec_cmd_trng_module { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + u32 length; + trng_data_resp_s resp; +} hisec_cmd_trng_module_s; + +#endif /* HISEC_NPU_CMD_DEFS_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hinic3_hmm.h b/drivers/infiniband/hw/hiroce3/include/hinic3_hmm.h new file mode 100644 index 000000000..5a8f76e2d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hinic3_hmm.h @@ -0,0 +1,83 @@ +/* *************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2022. All rights reserved. + ******************************************************************************/ + +#ifndef HINIC_HMM_H__ +#define HINIC_HMM_H__ + +/* has no mpt entry */ +#define HMM_MPT_EN_SW 1 /* has mpt, state INVALID */ +#define HMM_MPT_EN_HW 2 /* has mpt, state FREE or VALID */ +#define HMM_MPT_DISABLED 0 /* has no mpt entry */ +#define HMM_MPT_FIX_BUG_LKEY 0 + +#include "hinic3_cqm.h" +#include "hinic3_hwdev.h" +#include "hmm_comp.h" +#include "hmm_mr.h" + +/* **************************************************************************** + Prototype : hmm_reg_user_mr_update + Description : MR注册生成和更新MPT和MTT表 + Input : struct hinic3_hwdev *hwdev + hmm_mr *mr MR结构，包含已经完成用户态内存的物理地址获取umem + u32 pdn PD号，如果不支持的pd的特性直接填0. + u64 length 需要注册的用户态地址长度 + u64 virt_addr 需要注册的IOV虚拟地址首地址 + int hmm_acess填入enum rdma_ib_access的值 + u32 service_type enum hinic3_service_type的值 + Output : None +**************************************************************************** */ +int hmm_reg_user_mr_update(struct hinic3_hwdev *hwdev, struct hmm_mr *mr, u32 pdn, u64 length, + u64 virt_addr, int access, u32 service_type, u16 channel); + + +/* **************************************************************************** + Prototype : hmm_reg_user_mr_update + Description : MR去注册删除MPT和MTT表 + Input : struct hinic3_hwdev *hwdev + rdma_mr *mr MR结构 + u32 service_type enum hinic3_service_type的值 + Output : None +**************************************************************************** */ +int hmm_dereg_mr_update(struct hinic3_hwdev *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel); + +#ifndef ROCE_SERVICE +/* **************************************************************************** + Prototype : hmm_reg_user_mr + Description : register MR for user + Input : struct hinic3_hwdev *hwdev + u32 pdn PD�� + u64 start ע��memory����ʼ��ַ + u64 length ע���ڴ�ij��� + u64 virt_addr io�������ַ + int hmm_acess ����enum rdma_ib_access��ֵ + u32 service_type enum hinic3_service_type��ֵ + Output : None +**************************************************************************** */ +struct hmm_mr *hmm_reg_user_mr(struct hinic3_hwdev *hwdev, u64 start, u32 pdn, u64 length, + u64 virt_addr, int hmm_acess, u32 service_type, u16 channel); + +/* **************************************************************************** + Prototype : hmm_dereg_mr + Description : dereg DMA_MR, user_MR or FRMR + Input : struct hmm_mr *mr + : u32 service_type enum hinic3_service_type的值 + Output : None + +**************************************************************************** */ +int hmm_dereg_mr(struct hmm_mr *mr, u32 service_type, u16 channel); +#endif + +int hmm_rdma_write_mtt(void *hwdev, struct rdma_mtt *mtt, u32 start_index, u32 npages, + u64 *page_list, u32 service_type); + +int hmm_rdma_mtt_alloc(void *hwdev, u32 npages, u32 page_shift, struct rdma_mtt *mtt, u32 service_type); + +void hmm_rdma_mtt_free(void *hwdev, struct rdma_mtt *mtt, u32 service_type); + +int hmm_init_mtt_table(struct hmm_comp_priv *comp_priv); + +void hmm_cleanup_mtt_table(struct hmm_comp_priv *comp_priv); + +#endif /* HINIC_RDMA_H__ */ diff --git a/drivers/infiniband/hw/hiroce3/include/hinic3_rdma.h b/drivers/infiniband/hw/hiroce3/include/hinic3_rdma.h new file mode 100644 index 000000000..3742c28fa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hinic3_rdma.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2022. All rights reserved. + ****************************************************************************** + History : + 1.Date : 2018/3/8 + Modification: Created file +***************************************************************************** */ + +#ifndef HINIC_RDMA_H__ +#define HINIC_RDMA_H__ + +#define RDMA_ROCE_ENABLE 1 +#define RDMA_IWARP_ENABLE 1 +#define RDMA_ROCE_DISABLE 0 +#define RDMA_IWARP_DISABLE 0 + +#define RDMA_MPT_DISABLED 0 /* has no mpt entry */ +#define RDMA_MPT_EN_SW 1 /* has mpt, state INVALID */ +#define RDMA_MPT_EN_HW 2 /* has mpt, state FREE or VALID */ + +#define RDMA_MPT_FIX_BUG_LKEY 0 + +struct mutex; +struct tag_cqm_qpc_mpt; +struct tag_cqm_object; +struct net_device; +struct rdma_gid_entry; + +#include "hinic3_cqm.h" + +enum mtt_check_type_e { + MTT_CHECK_TYPE_0 = 0, + MTT_CHECK_TYPE_1 +}; + +enum mtt_data_type_e { + MTT_DMTT_TYPE = 0, + MTT_CMTT_TYPE +}; + +enum rdma_ib_access { + RDMA_IB_ACCESS_LOCAL_WRITE = 1, + RDMA_IB_ACCESS_REMOTE_WRITE = (1 << 1), + RDMA_IB_ACCESS_REMOTE_READ = (1 << 2), + RDMA_IB_ACCESS_REMOTE_ATOMIC = (1 << 3), + RDMA_IB_ACCESS_MW_BIND = (1 << 4), + RDMA_IB_ACCESS_ZERO_BASED = (1 << 5), + RDMA_IB_ACCESS_ON_DEMAND = (1 << 6), +}; + +struct rdma_gid_entry { + union { + u8 raw[16]; + struct { + __be64 subnet_prefix; + __be64 interface_id; + } global; + }; + union { + struct { + u32 rsvd : 7; + u32 is_vroce : 1; + u32 cvlan : 12; /* 内层vlan customer vlan */ + u32 svlan : 12; /* 外层vlan */ + } bs; + u32 value; + } dw4; + + union { + u32 hdr_len_value; + }; + + union { + struct { + u16 tag : 2; /* 0:没有vlan； 1：一层vlan； 2: 2层vlan； 3：stag */ + u16 tunnel : 1; // rsvd for ppe, don't use. 'tunnel' + u16 gid_type : 2; + u16 ppe_rsvd1 : 1; + u16 outer_tag : 2; // rsvd for ppe, don't use. 'outer_tag' + u16 ppe_rsvd3 : 1; // rsvd for ppe, don't use. 'stag' + u16 gid_update : 1; + u16 rsvd : 6; + } bs; + u16 value; + } dw6_h; + + u8 smac[6]; +}; + +struct rdma_comp_resource { + struct mutex mutex; /* gid_entry使用的互斥量 */ + __be64 node_guid; /* 与ibdev中的node_guid一致 */ + struct rdma_gid_entry **gid_table; /* gid_entry在rdma组件初始化时分配内存 */ +}; + +struct rdma_mpt { + u32 mpt_index; /* 封装cqm提供的mpt_index */ + void *vaddr; /* 封装cqm提供的mpt_entry的虚拟地址 */ + void *mpt_object; /* 封装的cqm提供的指针 */ +}; + + +struct rdma_mtt_seg { + u32 offset; /* 分配连续索引的首个索引 */ + u32 order; /* mtt索引个数为1<<order，每个索引对应一个mtt entry */ + void *vaddr; /* mtt_seg第一个MTT的起始虚拟地址 */ + dma_addr_t paddr; /* mtt_seg第一个MTT的起始物理地址 */ +}; + +struct rdma_mtt { + u32 mtt_layers; /* mtt的级数,该值为0时表示不使用mtt做地址转换 */ + u32 mtt_page_shift; /* MTT的页大小 */ + u32 buf_page_shift; /* buffer页大小 */ + dma_addr_t mtt_paddr; /* 写入context中的物理地址 */ + __be64 *mtt_vaddr; /* 写入context中的虚拟地址 */ + struct rdma_mtt_seg **mtt_seg; /* 指向多级mtt */ + enum mtt_data_type_e mtt_type; +}; + +enum rdma_mr_type { + RDMA_DMA_MR = 0, + RDMA_USER_MR = 1, + RDMA_FRMR = 2, + RDMA_FMR = 3, + RDMA_PHYS_MR = 4, + RDMA_RSVD_LKEY = 5, + RDMA_SIG_MR = 6, + RDMA_INDIRECT_MR = 8, + RDMA_ODP_IMPLICIT_MR = 9, + RDMA_ODP_EXPLICIT_MR = 10, +}; + +struct rdma_mr { + struct rdma_mpt mpt; + struct rdma_mtt mtt; + u64 iova; /* mr指向内存的起始地址(虚拟地址,ZBVA时为0) */ + u64 size; /* mr指向内存的大小 */ + u32 key; /* mr对应的key */ + u32 pdn; /* mr绑定的pdn */ + u32 access; /* mr的访问权限 */ + int enabled; /* mr的状态,DISABLE、EN_SW、EN_HW */ + int mr_type; /* mr类型 */ + u32 block_size; +}; + +enum rdma_mw_type { + RDMA_MW_TYPE_1 = 1, + RDMA_MW_TYPE_2 = 2 +}; + +struct rdma_mw { + struct rdma_mpt mpt; + u32 key; /* mw对应的key */ + u32 pdn; /* mw绑定的pdn */ + enum rdma_mw_type type; /* mw的类型,type1,type2 */ + int enabled; /* mw的状态 */ +}; + +struct rdma_fmr { + struct rdma_mr mr; + u32 max_pages; /* fmr的最大映射页个数 */ + u32 max_maps; /* fmr的最大映射次数 */ + u32 maps; /* fmr的当前映射次数 */ + u32 page_shift; /* fmr指定的页偏移 */ +}; + +struct rdma_rdmarc { + u32 offset; /* 分配连续索引的首个索引 */ + u32 order; /* 分配的rdmarc的order,代表了个数 */ + u32 ext_order; /* 包含rc表和扩展表的个数 */ + dma_addr_t dma_addr; + void *vaddr; +}; + +int roce3_rdma_pd_alloc(void *hwdev, u32 *pdn); + +void roce3_rdma_pd_free(void *hwdev, u32 pdn); + +int roce3_rdma_enable_mw_mpt(void *hwdev, struct rdma_mw *mw, u32 service_type); + +int roce3_rdma_disable_mw_mpt(void *hwdev, struct rdma_mw *mw, u32 service_type); + +int roce3_rdma_map_phys_fmr(void *hwdev, struct rdma_fmr *fmr, u64 *page_list, int npages, u64 iova, u32 service_type); + +int roce3_rdma_unmap_fmr(void *hwdev, struct rdma_fmr *fmr, u32 service_type); + +int roce3_rdma_rdmarc_alloc(void *hwdev, u32 num, struct rdma_rdmarc *rdmarc); + +void roce3_rdma_rdmarc_free(void *hwdev, struct rdma_rdmarc *rdmarc); + +int roce3_rdma_update_gid_mac(void *hwdev, u32 port, struct rdma_gid_entry *gid_entry); +int roce3_rdma_update_gid(void *hwdev, u32 port, u32 update_index, struct rdma_gid_entry *gid_entry); +int roce3_rdma_reset_gid_table(void *hwdev, u32 port); + +int roce3_rdma_get_gid(void *hwdev, u32 port, u32 gid_index, struct rdma_gid_entry *gid); + +/* 该接口在pf初始化时调用 */ +int roce3_rdma_init_resource(void *hwdev); + +/* 该接口在pf卸载时调用 */ +void roce3_rdma_cleanup_resource(void *hwdev); + +#endif /* HINIC_RDMA_H__ */ diff --git a/drivers/infiniband/hw/hiroce3/include/hinic3_srv_nic.h b/drivers/infiniband/hw/hiroce3/include/hinic3_srv_nic.h new file mode 100644 index 000000000..245097b3a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hinic3_srv_nic.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2022. All rights reserved. + ****************************************************************************** + * @file hinic3_srv_nic.h + * @details nic service interface + History : + 1.Date : 2018/3/8 + Modification: Created file +***************************************************************************** */ + +#ifndef HINIC3_SRV_NIC_H +#define HINIC3_SRV_NIC_H + +#include "nic_mpu_cmd_defs.h" +#include "mag_mpu_cmd.h" +#include "mag_mpu_cmd_defs.h" +#include "hinic3_lld.h" + +enum hinic3_queue_type { + HINIC3_SQ, + HINIC3_RQ, + HINIC3_MAX_QUEUE_TYPE +}; + +struct hinic3_lld_dev *hinic3_get_lld_dev_by_netdev(struct net_device *netdev); +struct net_device *hinic3_get_netdev_by_lld(struct hinic3_lld_dev *lld_dev); + +struct hinic3_event_link_info { + u8 valid; + u8 port_type; + u8 autoneg_cap; + u8 autoneg_state; + u8 duplex; + u8 speed; +}; + +enum link_err_type { + LINK_ERR_MODULE_UNRECOGENIZED, + LINK_ERR_NUM, +}; + +enum port_module_event_type { + HINIC3_PORT_MODULE_CABLE_PLUGGED, + HINIC3_PORT_MODULE_CABLE_UNPLUGGED, + HINIC3_PORT_MODULE_LINK_ERR, + HINIC3_PORT_MODULE_MAX_EVENT, +}; + +struct hinic3_port_module_event { + enum port_module_event_type type; + enum link_err_type err_type; +}; + +struct hinic3_dcb_info { + u8 dcb_on; + u8 default_cos; + u8 up_cos[NIC_DCB_COS_MAX]; +}; + +enum hinic3_nic_event_type { + EVENT_NIC_LINK_DOWN, + EVENT_NIC_LINK_UP, + EVENT_NIC_PORT_MODULE_EVENT, + EVENT_NIC_DCB_STATE_CHANGE, + EVENT_NIC_BOND_DOWN, + EVENT_NIC_BOND_UP, +}; + +/* * + * @brief hinic3_set_mac - set mac address + * @param hwdev: device pointer to hwdev + * @param mac_addr: mac address from hardware + * @param vlan_id: vlan id + * @param func_id: function index + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_set_mac(void *hwdev, const u8 *mac_addr, u16 vlan_id, u16 func_id, u16 channel); + +/* * + * @brief hinic3_del_mac - delete mac address + * @param hwdev: device pointer to hwdev + * @param mac_addr: mac address from hardware + * @param vlan_id: vlan id + * @param func_id: function index + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_del_mac(void *hwdev, const u8 *mac_addr, u16 vlan_id, u16 func_id, u16 channel); + +/* * + * @brief hinic3_set_vport_enable - set function valid status + * @param hwdev: device pointer to hwdev + * @param func_id: global function index + * @param enable: 0-disable, 1-enable + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_set_vport_enable(void *hwdev, u16 func_id, bool enable, u16 channel); + +/* * + * @brief hinic3_set_port_enable - set port status + * @param hwdev: device pointer to hwdev + * @param enable: 0-disable, 1-enable + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_set_port_enable(void *hwdev, bool enable, u16 channel); + +/* * + * @brief hinic3_flush_qps_res - flush queue pairs resource in hardware + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_flush_qps_res(void *hwdev); + +/* * + * @brief hinic3_cache_out_qps_res - cache out queue pairs wqe resource in hardware + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_cache_out_qps_res(void *hwdev); + +/* * + * @brief hinic3_init_nic_hwdev - init nic hwdev + * @param hwdev: device pointer to hwdev + * @param pcidev_hdl: pointer to pcidev or handler + * @param dev_hdl: pointer to pcidev->dev or handler, for sdk_err() or + * dma_alloc() + * @param rx_buff_len: rx_buff_len is receive buffer length + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_init_nic_hwdev(void *hwdev, void *pcidev_hdl, void *dev_hdl, u16 rx_buff_len); + +/* * + * @brief hinic3_free_nic_hwdev - free nic hwdev + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +void hinic3_free_nic_hwdev(void *hwdev); + +/* * + * @brief hinic3_get_speed - set link speed + * @param hwdev: device pointer to hwdev + * @param port_info: link speed + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_get_speed(void *hwdev, enum mag_cmd_port_speed *speed, u16 channel); + +int hinic3_get_dcb_state(void *hwdev, struct hinic3_dcb_state *dcb_state); + +int hinic3_get_pf_dcb_state(void *hwdev, struct hinic3_dcb_state *dcb_state); + +int hinic3_get_cos_by_pri(void *hwdev, u8 pri, u8 *cos); + +/* * + * @brief hinic3_create_qps - create queue pairs + * @param hwdev: device pointer to hwdev + * @param num_qp: number of queue pairs + * @param sq_depth: sq depth + * @param rq_depth: rq depth + * @param qps_msix_arry: msix info + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_create_qps(void *hwdev, u16 num_qp, u32 sq_depth, u32 rq_depth, + struct irq_info *qps_msix_arry); + +/* * + * @brief hinic3_destroy_qps - destroy queue pairs + * @param hwdev: device pointer to hwdev + */ +void hinic3_destroy_qps(void *hwdev); + +/* * + * @brief hinic3_get_nic_queue - get nic queue + * @param hwdev: device pointer to hwdev + * @param q_id: queue index + * @param q_type: queue type + * @retval queue address + */ +void *hinic3_get_nic_queue(void *hwdev, u16 q_id, enum hinic3_queue_type q_type); + +/* * + * @brief hinic3_init_qp_ctxts - init queue pair context + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_init_qp_ctxts(void *hwdev); + +/* * + * @brief hinic3_free_qp_ctxts - free queue pairs + * @param hwdev: device pointer to hwdev + */ +void hinic3_free_qp_ctxts(void *hwdev); + +/* * + * @brief hinic3_pf_set_vf_link_state pf set vf link state + * @param hwdev: device pointer to hwdev + * @param vf_link_forced: set link forced + * @param link_state: Set link state, This parameter is valid only when vf_link_forced is true + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_pf_set_vf_link_state(void *hwdev, bool vf_link_forced, bool link_state); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/db_srv_type_pub.h b/drivers/infiniband/hw/hiroce3/include/hw/db_srv_type_pub.h new file mode 100644 index 000000000..85fd83f38 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/db_srv_type_pub.h @@ -0,0 +1,126 @@ +/* ***************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2015-2022. All rights reserved. + ****************************************************************************** + File name: Db_srv_type_pub.h + Version No.: Draft + Generated on May 28,: 2015 + Latest modification: + Function Description: Sml_table.h header file + Function list: + Modification history: + 1. Date: 2015 May 28 + Modify content: Create a file. + +***************************************************************************** */ + +#ifndef DB_SRV_TYPE_H +#define DB_SRV_TYPE_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +typedef enum { + DOORBELL_CMDQ_SRV_TYPE = 0, + DOORBELL_L2NIC_SRV_TYPE = 1, + DOORBELL_ROCE_SRV_TYPE = 2, + DOORBELL_ROCE_ARM_CQ_SRV_TYPE = 3, + DOORBELL_NOF1_SRV_TYPE = 4, + + DOORBELL_VIRTIO_SRV_TYPE = 5, + + DOORBELL_TOE_RQ1_SRV_TYPE = 6, + DOORBELL_TOE_RQ2_SRV_TYPE = 7, + DOORBELL_TOE_RQ4_SRV_TYPE = 8, + + DOORBELL_TOE_ISCSI_TGT_SRV_TYPE = 9, + DOORBELL_TOE_ISCSI_TGT_AA_HARD_SRV_TYPE = 10, + DOORBELL_TOE_ISCSI_TGT_AA_PROTOCOL_SRV_TYPE = 11, + + DOORBELL_FC_PARENT_RQ1_SRV_TYPE = 12, + DOORBELL_FC_PARENT_RQ2_SRV_TYPE = 13, + DOORBELL_FC_PARENT_RQ4_SRV_TYPE = 14, + + REMOTE_DB_ROCE_SRV_TYPE = 15, + DOORBELL_NOF2_SRV_TYPE = 16, + + DOORBELL_OVS_DPIF_TX_SRV_TYPE = 17, + DOORBELL_NVME_SQ_SRV_TYPE = 18, + DOORBELL_NVME_CQ_SRV_TYPE = 19, + DOORBELL_PCQ_SRV_TYPE = 20, /* dsw volq doorbell(producer and consumer) */ + + DOORBELL_ROCE_RQ_CNP_TYPE = 21, + DOORBELL_ROCE_SQA_CNP_TYPE = 22, + + DOORBELL_RSVD25 = 25, + DOORBELL_RSVD26 = 26, + DOORBELL_NOF3_SRV_TYPE = 27, + + DOORBELL_FC_CHILD0_SRV_TYPE = 28, + DOORBELL_FC_CHILD1_SRV_TYPE = 29, + DOORBELL_FC_CHILD2_SRV_TYPE = 30, + DOORBELL_RSV2 = 31, // For stateless timer +} doorbell_srv_type_e; + +/* * + * Enum name : armcq_type_e + * @brief xxxxxxxx + * Description: xxxxxxxxxxxxxxx + */ +typedef enum { + ARMCQ_RDMA = 0, + ARMCQ_TIFOE, + ARMCQ_IWARP +} armcq_type_e; + +typedef enum { + NO_QUEUE_Q_TYPE, + TOE_SQ_Q_TYPE, + TOE_RQ_Q_TYPE, + IOE_SQ_Q_TYPE, + IOE_RQ_Q_TYPE, + EMBEDED_CQ_Q_TYPE, + ROCE_SQ_Q_TYPE, + ROCE_RQ_Q_TYPE, + EXTERNAL_CQ_Q_TYPE, + SRQ_Q_TYPE +} doorbell_queue_type_e; + +typedef enum { + DB_CONTEXT_SIZE_256B, + DB_CONTEXT_SIZE_512B, + DB_CONTEXT_SIZE_RSVD, + DB_CONTEXT_SIZE_1024B +} doorbell_context_size_e; + +typedef enum { + DB_KEY_SIZE_RSVD, + DB_KEY_SIZE_10B, + DB_KEY_SIZE_26B, + DB_KEY_SIZE_42B +} doorbell_key_size_e; + + +/* * DB_SUBTYPE_E */ +enum DB_SUBTYPE_E { + DB_SUBTYPE_NONE = 0, + DB_SUBTYPE_RC_SEND = 1, + DB_SUBTYPE_RC_SEND_IMME = 2, + DB_SUBTYPE_RC_WRITE = 3, + DB_SUBTYPE_RC_WRITE_IMME = 4, + DB_SUBTYPE_RC_READ = 5, + DB_SUBTYPE_RC_ATOMIC_CMPSWP = 6, + DB_SUBTYPE_RC_ATOMIC_FETCHADD = 7 +}; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif /* DB_SRV_TYPE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/node_id.h b/drivers/infiniband/hw/hiroce3/include/hw/node_id.h new file mode 100644 index 000000000..7d30fb009 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/node_id.h @@ -0,0 +1,58 @@ +/****************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + ****************************************************************************** + * @file node_id.h + * @brief node_id.h header file + * @date 2022/4/27 + * History: +******************************************************************************/ +#ifndef NODE_ID_H +#define NODE_ID_H + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/** RING NODE ID */ +typedef enum { + NODE_ID_CPI = 0, + NODE_ID_MQM = 1, + NODE_ID_QUF = 2, + NODE_ID_Reserved0 = 3, + NODE_ID_SMF0 = 4, + NODE_ID_TILE_F0 = 5, + NODE_ID_TILE_F1 = 6, + NODE_ID_SMF1 = 7, + NODE_ID_DP_NETWORK = 8, + NODE_ID_CPB = 9, + NODE_ID_QUL = 10, + NODE_ID_TS = 11, + NODE_ID_TILE_L1 = 12, + NODE_ID_SML1 = 13, + NODE_ID_SML0 = 14, + NODE_ID_TILE_L0 = 15, + NODE_ID_SMF2 = 16, + NODE_ID_TILE_F2 = 17, + NODE_ID_TILE_F3 = 18, + NODE_ID_SMF3 = 19, + NODE_ID_TILE_L3 = 20, + NODE_ID_SML3 = 21, + NODE_ID_SML2 = 22, + NODE_ID_TILE_L2 = 23, + NODE_ID_CRYPTO = 24, + NODE_ID_LCAM = 25, + NODE_ID_MPU = 26, + NODE_ID_DP_HOST = 27, + NODE_ID_UP_HOST = 31 /* Used for API chain function in the CPI */ +} INTERNAL_RING_NODE_ID_E; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif /* NODE_ID_H */ + diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_c_union_define.h new file mode 100644 index 000000000..3c67c555f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_c_union_define.h @@ -0,0 +1,318 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cnb_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:25:21 Create file +// ****************************************************************************** + +#ifndef CNB_C_UNION_DEFINE_H +#define CNB_C_UNION_DEFINE_H + +/* Define the union csr_cnb_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_version_u; + +/* Define the union csr_cnb_tmout_cnt_thd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tmout_cnt_thd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_tmout_cnt_thd_u; + +/* Define the union csr_cnb_empty_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_err_addr : 26; /* [25:0] */ + u32 rsv_0 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_empty_addr_u; + +/* Define the union csr_cnb_api_err_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_err_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_err_flit_cnt_u; + +/* Define the union csr_cnb_api_crt_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_crt_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_crt_msge_cnt_u; + +/* Define the union csr_cnb_api_tx_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_tx_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_tx_msge_cnt_u; + +/* Define the union csr_cnb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_vector_u; + +/* Define the union csr_cnb_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_3 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_u; + +/* Define the union csr_cnb_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_4 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_en_u; + +/* Define the union csr_cnb_api_op_code_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opcode_err : 1; /* [0] */ + u32 opcode_err_insrt : 1; /* [1] */ + u32 opcode_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_op_code_err_u; + +/* Define the union csr_cnb_csr_cmd_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmdpar_err : 1; /* [0] */ + u32 cmdpar_err_insrt : 1; /* [1] */ + u32 cmdpar_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_cmd_parity_err_u; + +/* Define the union csr_cnb_csr_wr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrcmd_err : 1; /* [0] */ + u32 wrcmd_err_insrt : 1; /* [1] */ + u32 wrcmd_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_wr_err_u; + +/* Define the union csr_cnb_csr_rddat_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdatpar_err : 1; /* [0] */ + u32 rdatpar_err_insrt : 1; /* [1] */ + u32 rdatpar_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rddat_parity_err_u; + +/* Define the union csr_cnb_csr_rd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdcmd_err : 1; /* [0] */ + u32 rdcmd_err_insrt : 1; /* [1] */ + u32 rdcmd_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rd_err_u; + +/* Define the union csr_cnb_merr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmout_err : 1; /* [0] */ + u32 tmout_err_insrt : 1; /* [1] */ + u32 intpar_err : 1; /* [2] */ + u32 intpar_err_insrt : 1; /* [3] */ + u32 api_e1_err : 1; /* [4] */ + u32 api_e1_err_insrt : 1; /* [5] */ + u32 api_e0_err : 1; /* [6] */ + u32 api_e0_err_insrt : 1; /* [7] */ + u32 api_token_err : 1; /* [8] */ + u32 api_token_err_insrt : 1; /* [9] */ + u32 api_prot_err : 1; /* [10] */ + u32 api_prot_err_insrt : 1; /* [11] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_u; + +/* Define the union csr_cnb_merr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmout_err_en : 1; /* [0] */ + u32 intpar_err_en : 1; /* [1] */ + u32 api_e1_err_en : 1; /* [2] */ + u32 api_e0_err_en : 1; /* [3] */ + u32 api_token_err_en : 1; /* [4] */ + u32 api_prot_err_en : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_en_u; + +/* Define the union csr_rs_nd_pe_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crdt_sta : 10; /* [9:0] */ + u32 rsv_7 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rs_nd_pe_crdt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cnb_version_u cnb_version; /* 0 */ + volatile csr_cnb_tmout_cnt_thd_u cnb_tmout_cnt_thd; /* 4 */ + volatile csr_cnb_empty_addr_u cnb_empty_addr; /* 8 */ + volatile csr_cnb_api_err_flit_cnt_u cnb_api_err_flit_cnt; /* C */ + volatile csr_cnb_api_crt_msge_cnt_u cnb_api_crt_msge_cnt; /* 10 */ + volatile csr_cnb_api_tx_msge_cnt_u cnb_api_tx_msge_cnt; /* 14 */ + volatile csr_cnb_int_vector_u cnb_int_vector; /* 18 */ + volatile csr_cnb_int_u cnb_int; /* 1C */ + volatile csr_cnb_int_en_u cnb_int_en; /* 20 */ + volatile csr_cnb_api_op_code_err_u cnb_api_op_code_err; /* 24 */ + volatile csr_cnb_csr_cmd_parity_err_u cnb_csr_cmd_parity_err; /* 28 */ + volatile csr_cnb_csr_wr_err_u cnb_csr_wr_err; /* 2C */ + volatile csr_cnb_csr_rddat_parity_err_u cnb_csr_rddat_parity_err; /* 30 */ + volatile csr_cnb_csr_rd_err_u cnb_csr_rd_err; /* 34 */ + volatile csr_cnb_merr_u cnb_merr; /* 38 */ + volatile csr_cnb_merr_en_u cnb_merr_en; /* 3C */ + volatile csr_rs_nd_pe_crdt_u rs_nd_pe_crdt; /* 40 */ +} S_cnb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cnb_csr */ +extern volatile S_cnb_csr_REGS_TYPE *gopcnb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCNB_VERSION_cnb_version(unsigned int ucnb_version); +int iSetCNB_TMOUT_CNT_THD_rp_tmout_cnt_thd(unsigned int urp_tmout_cnt_thd); +int iSetCNB_EMPTY_ADDR_api_err_addr(unsigned int uapi_err_addr); +int iSetCNB_API_ERR_FLIT_CNT_cnb_api_err_flit_cnt(unsigned int ucnb_api_err_flit_cnt); +int iSetCNB_API_CRT_MSGE_CNT_cnb_api_crt_msge_cnt(unsigned int ucnb_api_crt_msge_cnt); +int iSetCNB_API_TX_MSGE_CNT_cnb_api_tx_msge_cnt(unsigned int ucnb_api_tx_msge_cnt); +int iSetCNB_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetCNB_INT_VECTOR_enable(unsigned int uenable); +int iSetCNB_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetCNB_INT_int_data(unsigned int uint_data); +int iSetCNB_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetCNB_INT_EN_int_en(unsigned int uint_en); +int iSetCNB_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetCNB_API_OP_CODE_ERR_opcode_err(unsigned int uopcode_err); +int iSetCNB_API_OP_CODE_ERR_opcode_err_insrt(unsigned int uopcode_err_insrt); +int iSetCNB_API_OP_CODE_ERR_opcode_err_info(unsigned int uopcode_err_info); +int iSetCNB_CSR_CMD_PARITY_ERR_cmdpar_err(unsigned int ucmdpar_err); +int iSetCNB_CSR_CMD_PARITY_ERR_cmdpar_err_insrt(unsigned int ucmdpar_err_insrt); +int iSetCNB_CSR_CMD_PARITY_ERR_cmdpar_err_info(unsigned int ucmdpar_err_info); +int iSetCNB_CSR_WR_ERR_wrcmd_err(unsigned int uwrcmd_err); +int iSetCNB_CSR_WR_ERR_wrcmd_err_insrt(unsigned int uwrcmd_err_insrt); +int iSetCNB_CSR_WR_ERR_wrcmd_err_info(unsigned int uwrcmd_err_info); +int iSetCNB_CSR_RDDAT_PARITY_ERR_rdatpar_err(unsigned int urdatpar_err); +int iSetCNB_CSR_RDDAT_PARITY_ERR_rdatpar_err_insrt(unsigned int urdatpar_err_insrt); +int iSetCNB_CSR_RDDAT_PARITY_ERR_rdatpar_err_info(unsigned int urdatpar_err_info); +int iSetCNB_CSR_RD_ERR_rdcmd_err(unsigned int urdcmd_err); +int iSetCNB_CSR_RD_ERR_rdcmd_err_insrt(unsigned int urdcmd_err_insrt); +int iSetCNB_CSR_RD_ERR_rdcmd_err_info(unsigned int urdcmd_err_info); +int iSetCNB_MERR_tmout_err(unsigned int utmout_err); +int iSetCNB_MERR_tmout_err_insrt(unsigned int utmout_err_insrt); +int iSetCNB_MERR_intpar_err(unsigned int uintpar_err); +int iSetCNB_MERR_intpar_err_insrt(unsigned int uintpar_err_insrt); +int iSetCNB_MERR_api_e1_err(unsigned int uapi_e1_err); +int iSetCNB_MERR_api_e1_err_insrt(unsigned int uapi_e1_err_insrt); +int iSetCNB_MERR_api_e0_err(unsigned int uapi_e0_err); +int iSetCNB_MERR_api_e0_err_insrt(unsigned int uapi_e0_err_insrt); +int iSetCNB_MERR_api_token_err(unsigned int uapi_token_err); +int iSetCNB_MERR_api_token_err_insrt(unsigned int uapi_token_err_insrt); +int iSetCNB_MERR_api_prot_err(unsigned int uapi_prot_err); +int iSetCNB_MERR_api_prot_err_insrt(unsigned int uapi_prot_err_insrt); +int iSetCNB_MERR_EN_tmout_err_en(unsigned int utmout_err_en); +int iSetCNB_MERR_EN_intpar_err_en(unsigned int uintpar_err_en); +int iSetCNB_MERR_EN_api_e1_err_en(unsigned int uapi_e1_err_en); +int iSetCNB_MERR_EN_api_e0_err_en(unsigned int uapi_e0_err_en); +int iSetCNB_MERR_EN_api_token_err_en(unsigned int uapi_token_err_en); +int iSetCNB_MERR_EN_api_prot_err_en(unsigned int uapi_prot_err_en); +int iSetRS_ND_PE_CRDT_crdt_sta(unsigned int ucrdt_sta); + + +#endif // CNB_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_reg_offset.h new file mode 100644 index 000000000..139d687f2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_reg_offset.h @@ -0,0 +1,42 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cnb_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:25:21 Create file +// ****************************************************************************** + +#ifndef CNB_REG_OFFSET_H +#define CNB_REG_OFFSET_H + +/* CNB_CSR Base address of Module's Register */ +#define CSR_CNB_CSR_BASE (0x0) + +/* **************************************************************************** */ +/* CNB_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CNB_CSR_CNB_VERSION_REG (CSR_CNB_CSR_BASE + 0x0) /* 版本寄存器和EC寄存器。 */ +#define CSR_CNB_CSR_CNB_TMOUT_CNT_THD_REG (CSR_CNB_CSR_BASE + 0x4) /* CNB超时配置寄存器。 */ +#define CSR_CNB_CSR_CNB_EMPTY_ADDR_REG (CSR_CNB_CSR_BASE + 0x8) /* 错误地址记录。 */ +#define CSR_CNB_CSR_CNB_API_ERR_FLIT_CNT_REG (CSR_CNB_CSR_BASE + 0xC) /* Flit错误统计。 */ +#define CSR_CNB_CSR_CNB_API_CRT_MSGE_CNT_REG (CSR_CNB_CSR_BASE + 0x10) /* 接收API统计。 */ +#define CSR_CNB_CSR_CNB_API_TX_MSGE_CNT_REG (CSR_CNB_CSR_BASE + 0x14) /* 发送API统计。 */ +#define CSR_CNB_CSR_CNB_INT_VECTOR_REG (CSR_CNB_CSR_BASE + 0x18) /* 中断向量 */ +#define CSR_CNB_CSR_CNB_INT_REG (CSR_CNB_CSR_BASE + 0x1C) /* 中断状态。 */ +#define CSR_CNB_CSR_CNB_INT_EN_REG (CSR_CNB_CSR_BASE + 0x20) /* 中断使能。 */ +#define CSR_CNB_CSR_CNB_API_OP_CODE_ERR_REG (CSR_CNB_CSR_BASE + 0x24) /* 非法OPCODE错误。 */ +#define CSR_CNB_CSR_CNB_CSR_CMD_PARITY_ERR_REG (CSR_CNB_CSR_BASE + 0x28) /* 奇偶校验错误。 */ +#define CSR_CNB_CSR_CNB_CSR_WR_ERR_REG (CSR_CNB_CSR_BASE + 0x2C) /* 写操作错误。 */ +#define CSR_CNB_CSR_CNB_CSR_RDDAT_PARITY_ERR_REG (CSR_CNB_CSR_BASE + 0x30) /* 读数据奇偶错误。 */ +#define CSR_CNB_CSR_CNB_CSR_RD_ERR_REG (CSR_CNB_CSR_BASE + 0x34) /* 读操作错误。 */ +#define CSR_CNB_CSR_CNB_MERR_REG (CSR_CNB_CSR_BASE + 0x38) /* CNB异常状态。 */ +#define CSR_CNB_CSR_CNB_MERR_EN_REG (CSR_CNB_CSR_BASE + 0x3C) /* CNB异常中断使能寄存器。 */ +#define CSR_CNB_CSR_RS_ND_PE_CRDT_REG (CSR_CNB_CSR_BASE + 0x40) /* 信用统计。 */ + +#endif // CNB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_c_union_define.h new file mode 100644 index 000000000..589025e74 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_c_union_define.h @@ -0,0 +1,8234 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpb_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/3 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2020/03/24 21:10:00 Create file +// ****************************************************************************** + +#ifndef CPB_C_UNION_DEFINE_H +#define CPB_C_UNION_DEFINE_H + +/* Define the union csr_cpb_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fpga_ver_u; + +/* Define the union csr_cpb_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_emu_ver_u; + +/* Define the union csr_cpb_bank_row_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bk_row_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bank_row_en_u; + +/* Define the union csr_cpb_dat_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_datmem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_dat_init_start_u; + +/* Define the union csr_cpb_cd_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cdmem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_cd_init_start_u; + +/* Define the union csr_cpb_nptr_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_nptrmem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_nptr_init_start_u; + +/* Define the union csr_cpb_ti_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_timem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ti_init_start_u; + +/* Define the union csr_cpb_dat_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_datmem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_dat_init_done_u; + +/* Define the union csr_cpb_cd_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cdmem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_cd_init_done_u; + +/* Define the union csr_cpb_nptr_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_nptrmem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_nptr_init_done_u; + +/* Define the union csr_cpb_ti_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_timem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ti_init_done_u; + +/* Define the union csr_cpb_bmp_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bmp_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bmp_init_start_u; + +/* Define the union csr_cpb_bmp_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bmp_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bmp_init_done_u; + +/* Define the union csr_cpb_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fpa_init_start : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 tso_ctxm_init_start : 1; /* [4] */ + u32 rsv_1 : 3; /* [7:5] */ + u32 tx_port_fp_init_start : 8; /* [15:8] */ + u32 rxlb_fp_init_start : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_init_start_u; + +/* Define the union csr_cpb_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_init_done : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 fpa_init_done : 1; /* [4] */ + u32 tso_ctxm_init_done : 1; /* [5] */ + u32 rsv_4 : 2; /* [7:6] */ + u32 tx_port_fp_init_done : 8; /* [15:8] */ + u32 rxlb_fp_init_done : 1; /* [16] */ + u32 rsv_5 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_init_done_u; + +/* Define the union csr_cpb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cpi_int_index : 24; /* [23:0] */ + u32 rsv_6 : 3; /* [26:24] */ + u32 cpb_int_enable : 1; /* [27] */ + u32 cpb_int_issue : 1; /* [28] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_int_vector_u; + +/* Define the union csr_cpb_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_int_data : 15; /* [14:0] */ + u32 rsv_8 : 1; /* [15] */ + u32 cpb_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_int_u; + +/* Define the union csr_cpb_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_int_en : 15; /* [14:0] */ + u32 rsv_9 : 1; /* [15] */ + u32 cpb_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_int_en_u; + +/* Define the union csr_cpb_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ucerr : 1; /* [0] */ + u32 cpb_ram_ucerr_inj : 1; /* [1] */ + u32 cpb_ram_ucerr_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ucerr_u; + +/* Define the union csr_cpb_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_cerr : 1; /* [0] */ + u32 cpb_ram_cerr_inj : 1; /* [1] */ + u32 cpb_ram_cerr_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_cerr_u; + +/* Define the union csr_cpb_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fifo_of_err : 1; /* [0] */ + u32 cpb_fifo_of_err_inj : 1; /* [1] */ + u32 cpb_fifo_of_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fifo_of_err_u; + +/* Define the union csr_cpb_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fifo_uf_err : 1; /* [0] */ + u32 cpb_fifo_uf_err_inj : 1; /* [1] */ + u32 cpb_fifo_uf_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fifo_uf_err_u; + +/* Define the union csr_cpb_rx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_crdt_of_err : 1; /* [0] */ + u32 cpb_rx_crdt_uf_err : 1; /* [1] */ + u32 sge_zero_err : 1; /* [2] */ + u32 cpb_rx_crdt_of_err_inj : 1; /* [3] */ + u32 cpb_rx_crdt_uf_err_inj : 1; /* [4] */ + u32 sge_zero_err_inj : 1; /* [5] */ + u32 cpb_rx_crdt_err_stickey : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_crdt_err_u; + +/* Define the union csr_cpb_tx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_tx_crdt_of_err : 1; /* [0] */ + u32 cpb_tx_crdt_uf_err : 1; /* [1] */ + u32 cpb_tx_crdt_of_err_inj : 1; /* [2] */ + u32 cpb_tx_crdt_uf_err_inj : 1; /* [3] */ + u32 cpb_tx_crdt_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_crdt_err_u; + +/* Define the union csr_tx_prealc_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_prealc_crdt_err : 1; /* [0] */ + u32 tx_prealc_crdt_err_inj : 1; /* [1] */ + u32 tx_prealc_crdt_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_prealc_crdt_err_u; + +/* Define the union csr_cpb_bp_drop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bp_drop_err : 1; /* [0] */ + u32 cpb_bp_drop_err_inj : 1; /* [1] */ + u32 cpb_bp_drop_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bp_drop_err_u; + +/* Define the union csr_cir_cit_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_abn_err : 1; /* [0] */ + u32 cit_abn_err : 1; /* [1] */ + u32 cir_abn_err_inj : 1; /* [2] */ + u32 cit_abn_err_inj : 1; /* [3] */ + u32 cir_cit_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_cit_abn_err_u; + +/* Define the union csr_cpr_cpt_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_abn_err : 1; /* [0] */ + u32 cpt_abn_err : 1; /* [1] */ + u32 cpr_abn_err_inj : 1; /* [2] */ + u32 cpt_abn_err_inj : 1; /* [3] */ + u32 cpr_cpt_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_cpt_abn_err_u; + +/* Define the union csr_ct_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cstl_abn_err : 1; /* [0] */ + u32 cstf_abn_err : 1; /* [1] */ + u32 cstl_abn_err_inj : 1; /* [2] */ + u32 cstf_abn_err_inj : 1; /* [3] */ + u32 ct_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_abn_err_u; + +/* Define the union csr_cq_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ciq_abn_err : 1; /* [0] */ + u32 coq_abn_err : 1; /* [1] */ + u32 ciq_abn_err_inj : 1; /* [2] */ + u32 coq_abn_err_inj : 1; /* [3] */ + u32 cq_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cq_abn_err_u; + +/* Define the union csr_rx_tx_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_abn_err : 1; /* [0] */ + u32 cpb_tx_abn_err : 1; /* [1] */ + u32 cpb_rx_abn_err_inj : 1; /* [2] */ + u32 cpb_tx_abn_err_inj : 1; /* [3] */ + u32 rx_tx_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tx_abn_err_u; + +/* Define the union csr_cpb_bmu_rsc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bmu_err : 1; /* [0] */ + u32 cpb_bmu_err_inj : 1; /* [1] */ + u32 cpb_bmu_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bmu_rsc_err_u; + +/* Define the union csr_cpb_aging_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_aging_err : 1; /* [0] */ + u32 cpb_aging_err_inj : 1; /* [1] */ + u32 cpb_aging_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_aging_err_u; + +/* Define the union csr_cpb_fatal_err_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ucerr_fatal_en : 1; /* [0] */ + u32 cpb_fifo_of_fatal_en : 1; /* [1] */ + u32 cpb_fifo_uf_fatal_en : 1; /* [2] */ + u32 cpb_rx_crdt_err_fatal_en : 1; /* [3] */ + u32 cpb_tx_crdt_err_fatal_en : 1; /* [4] */ + u32 cpb_ipsu_itf_err_fatal_en : 1; /* [5] */ + u32 cpb_pe_itf_err_fatal_en : 1; /* [6] */ + u32 cpb_tile_itf_err_fatal_en : 1; /* [7] */ + u32 cpb_qu_itf_err_fatal_en : 1; /* [8] */ + u32 cpb_rxtx_itf_err_fatal_en : 1; /* [9] */ + u32 cpb_bmp_err_fatal_en : 1; /* [10] */ + u32 rsv_10 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fatal_err_en_u; + +/* Define the union csr_cpb_fatal_err_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ucerr_fatal_sta : 1; /* [0] */ + u32 cpb_fifo_of_fatal_sta : 1; /* [1] */ + u32 cpb_fifo_uf_fatal_sta : 1; /* [2] */ + u32 cpb_rx_crdt_err_fatal_sta : 1; /* [3] */ + u32 cpb_tx_crdt_err_fatal_sta : 1; /* [4] */ + u32 cpb_ipsu_itf_err_fatal_sta : 1; /* [5] */ + u32 cpb_pe_itf_err_fatal_sta : 1; /* [6] */ + u32 cpb_tile_itf_err_fatal_sta : 1; /* [7] */ + u32 cpb_qu_itf_err_fatal_sta : 1; /* [8] */ + u32 cpb_rxtx_itf_err_fatal_sta : 1; /* [9] */ + u32 cpb_bmp_err_fatal_sta : 1; /* [10] */ + u32 rsv_11 : 5; /* [15:11] */ + u32 cpb_ram_ucerr_fatal_clr : 1; /* [16] */ + u32 cpb_fifo_of_fatal_clr : 1; /* [17] */ + u32 cpb_fifo_uf_fatal_clr : 1; /* [18] */ + u32 cpb_rx_crdt_err_fatal_clr : 1; /* [19] */ + u32 cpb_tx_crdt_err_fatal_clr : 1; /* [20] */ + u32 cpb_ipsu_itf_err_fatal_clr : 1; /* [21] */ + u32 cpb_pe_itf_err_fatal_clr : 1; /* [22] */ + u32 cpb_tile_itf_err_fatal_clr : 1; /* [23] */ + u32 cpb_qu_itf_err_fatal_clr : 1; /* [24] */ + u32 cpb_rxtx_itf_err_fatal_clr : 1; /* [25] */ + u32 cpb_bmp_err_fatal_clr : 1; /* [26] */ + u32 rsv_12 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fatal_err_sta_u; + +/* Define the union csr_cpb_itf_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ipsurx_bp_sta : 1; /* [0] */ + u32 cpb_ipsutx_bp_sta : 1; /* [1] */ + u32 iq_cpb_rx_bp_sta : 1; /* [2] */ + u32 iq_cpb_tx_bp_sta : 1; /* [3] */ + u32 cpb_stliq_req_bp_sta : 5; /* [8:4] */ + u32 cpb_stfiq_req_bp_sta : 4; /* [12:9] */ + u32 stlfq_cpb_ackstr_bp_sta : 1; /* [13] */ + u32 stffq_cpb_ackstr_bp_sta : 2; /* [15:14] */ + u32 prm_cpb_alloc_rx_bp_sta : 1; /* [16] */ + u32 prm_cpb_alloc_tx_bp_sta : 1; /* [17] */ + u32 prm_cpb_dealloc_rx_bp_sta : 1; /* [18] */ + u32 prm_cpb_dealloc_tx_bp_sta : 1; /* [19] */ + u32 prm_cpb_prls_bp_sta : 1; /* [20] */ + u32 cpb_oq_rx_bp_sta : 1; /* [21] */ + u32 cpb_oq_tx_bp_sta : 1; /* [22] */ + u32 cpb_oq_drp_bp_sta : 1; /* [23] */ + u32 cpb_pqm_host_bp_sta : 4; /* [27:24] */ + u32 rx_prm_bp_sta : 1; /* [28] */ + u32 tx_mag_bp_sta : 1; /* [29] */ + u32 rx_crdt_bp_sta : 1; /* [30] */ + u32 tx_crdt_bp_sta : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_itf_bp_sta_u; + +/* Define the union csr_cpb_itf_bp_his_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ipsurx_bp_his : 1; /* [0] */ + u32 cpb_ipsutx_bp_his : 1; /* [1] */ + u32 iq_cpb_rx_bp_his : 1; /* [2] */ + u32 iq_cpb_tx_bp_his : 1; /* [3] */ + u32 cpb_stliq_req_bp_his : 5; /* [8:4] */ + u32 cpb_stfiq_req_bp_his : 4; /* [12:9] */ + u32 stlfq_cpb_ackstr_bp_his : 1; /* [13] */ + u32 stffq_cpb_ackstr_bp_his : 2; /* [15:14] */ + u32 prm_cpb_alloc_rx_bp_his : 1; /* [16] */ + u32 prm_cpb_alloc_tx_bp_his : 1; /* [17] */ + u32 prm_cpb_dealloc_rx_bp_his : 1; /* [18] */ + u32 prm_cpb_dealloc_tx_bp_his : 1; /* [19] */ + u32 prm_cpb_prls_bp_his : 1; /* [20] */ + u32 cpb_oq_rx_bp_his : 1; /* [21] */ + u32 cpb_oq_tx_bp_his : 1; /* [22] */ + u32 cpb_oq_drp_bp_his : 1; /* [23] */ + u32 cpb_pqm_host_bp_his : 4; /* [27:24] */ + u32 rx_prm_bp_his : 1; /* [28] */ + u32 tx_mag_bp_his : 1; /* [29] */ + u32 rx_crdt_bp_his : 1; /* [30] */ + u32 tx_crdt_bp_his : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_itf_bp_his_u; + +/* Define the union csr_cpb_api_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_api_err : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_api_err_u; + +/* Define the union csr_cpb_fifo_err_col_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_fifo_uf_col : 1; /* [0] */ + u32 stl_fifo_uf_col : 1; /* [1] */ + u32 cpt_fifo_uf_col : 1; /* [2] */ + u32 cpr_fifo_uf_col : 1; /* [3] */ + u32 cit_fifo_uf_col : 1; /* [4] */ + u32 cir_fifo_uf_col : 1; /* [5] */ + u32 ct_ext_dealc_rx_fifo_uf : 1; /* [6] */ + u32 ct_ext_dealc_tx_fifo_uf : 1; /* [7] */ + u32 ciq_fifo_uf_col : 1; /* [8] */ + u32 coq_fifo_uf_col : 1; /* [9] */ + u32 crx_fifo_uf_col : 1; /* [10] */ + u32 ctx_fifo_uf_col : 1; /* [11] */ + u32 cdt_fifo_uf_col : 1; /* [12] */ + u32 rsv_14 : 3; /* [15:13] */ + u32 stf_fifo_ov_col : 1; /* [16] */ + u32 stl_fifo_ov_col : 1; /* [17] */ + u32 cpt_fifo_ov_col : 1; /* [18] */ + u32 cpr_fifo_ov_col : 1; /* [19] */ + u32 cit_fifo_ov_col : 1; /* [20] */ + u32 cir_fifo_ov_col : 1; /* [21] */ + u32 ct_ext_dealc_rx_fifo_ov : 1; /* [22] */ + u32 ct_ext_dealc_tx_fifo_ov : 1; /* [23] */ + u32 ciq_fifo_of_col : 1; /* [24] */ + u32 coq_fifo_of_col : 1; /* [25] */ + u32 crx_fifo_of_col : 1; /* [26] */ + u32 ctx_fifo_of_col : 1; /* [27] */ + u32 cdt_fifo_of_col : 1; /* [28] */ + u32 rsv_15 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fifo_err_col_u; + +/* Define the union csr_tl_req_invld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_iq_push_len_err : 4; /* [3:0] */ + u32 stf_iq_push_len_err : 4; /* [7:4] */ + u32 stl_cmd_crc_len_err : 4; /* [11:8] */ + u32 stf_cmd_crc_len_err : 4; /* [15:12] */ + u32 stl_cmd_rd_link_err : 4; /* [19:16] */ + u32 stf_cmd_rd_link_err : 4; /* [23:20] */ + u32 rsv_16 : 4; /* [27:24] */ + u32 stf_psh_len_lt_tp_lho : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_req_invld_u; + +/* Define the union csr_tl_str_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_pe_cmd_len_err : 4; /* [3:0] */ + u32 stf_str_pe_cmd_len_err : 4; /* [7:4] */ + u32 stl_str_cm_len_err : 4; /* [11:8] */ + u32 stf_str_cm_len_err : 4; /* [15:12] */ + u32 stl_str_ext_len_err : 4; /* [19:16] */ + u32 stf_str_ext_len_err : 4; /* [23:20] */ + u32 stl_str_ov_len_err : 4; /* [27:24] */ + u32 stf_str_ov_len_err : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_str_err_0_u; + +/* Define the union csr_tl_str_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_mio_len_err : 4; /* [3:0] */ + u32 stf_str_mio_len_err : 4; /* [7:4] */ + u32 stl_str_pld_len_err : 4; /* [11:8] */ + u32 stf_str_pld_len_err : 4; /* [15:12] */ + u32 stl_str_ext_omd_len_err : 4; /* [19:16] */ + u32 stf_str_ext_omd_len_err : 4; /* [23:20] */ + u32 stl_str_mc_cmd_num_err : 4; /* [27:24] */ + u32 stf_str_mc_cmd_num_err : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_str_err_1_u; + +/* Define the union csr_tl_str_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_cmd_len_err : 4; /* [3:0] */ + u32 stf_str_cmd_len_err : 4; /* [7:4] */ + u32 stl_str_para_cmd_cnum_err : 4; /* [11:8] */ + u32 stf_str_para_cmd_cnum_err : 4; /* [15:12] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_str_err_2_u; + +/* Define the union csr_cpb_ram_ctrl_bus_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_0_u; + +/* Define the union csr_cpb_ram_ctrl_bus_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_1_u; + +/* Define the union csr_cpb_ram_ctrl_bus_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_2_u; + +/* Define the union csr_cpb_ram_ctrl_bus_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_3_u; + +/* Define the union csr_cpb_ram_ctrl_bus_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_4_u; + +/* Define the union csr_cpb_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ecc_bypass : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ecc_bypass_u; + +/* Define the union csr_cpb_indir_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_indir_addr : 20; /* [19:0] */ + u32 rsv_20 : 4; /* [23:20] */ + u32 cpb_indir_tab : 4; /* [27:24] */ + u32 cpb_indir_state : 2; /* [29:28] */ + u32 cpb_indir_mode : 1; /* [30] */ + u32 cpb_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_indir_ctrl_u; + +/* Define the union csr_cpb_indir_to_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_indir_to_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_indir_to_th_u; + +/* Define the union csr_bank_weak_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_weak_en : 1; /* [0] */ + u32 rsv_21 : 3; /* [3:1] */ + u32 weak_diff_th : 9; /* [12:4] */ + u32 rsv_22 : 3; /* [15:13] */ + u32 weak_low_th : 12; /* [27:16] */ + u32 rsv_23 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bank_weak_cfg_u; + +/* Define the union csr_bmu_alt_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmu_alt_bp_on_th : 9; /* [8:0] */ + u32 rsv_24 : 7; /* [15:9] */ + u32 bmu_alt_bp_off_th : 10; /* [25:16] */ + u32 rsv_25 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_alt_bp_cfg_u; + +/* Define the union csr_bmu_fat_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmu_fatal_bp_on_th : 8; /* [7:0] */ + u32 bmu_fatal_bp_off_th : 8; /* [15:8] */ + u32 ct_fatal_bp_en : 1; /* [16] */ + u32 rsv_26 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_fat_bp_cfg_u; + +/* Define the union csr_bmu_ap_acc_wt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_acc_wt0 : 3; /* [2:0] */ + u32 rsv_27 : 1; /* [3] */ + u32 ap_acc_wt1 : 3; /* [6:4] */ + u32 rsv_28 : 1; /* [7] */ + u32 ap_acc_wt2 : 3; /* [10:8] */ + u32 rsv_29 : 1; /* [11] */ + u32 ap_acc_wt3 : 3; /* [14:12] */ + u32 rsv_30 : 1; /* [15] */ + u32 ap_acc_wt4 : 3; /* [18:16] */ + u32 rsv_31 : 1; /* [19] */ + u32 ap_acc_wt5 : 3; /* [22:20] */ + u32 rsv_32 : 1; /* [23] */ + u32 ap_acc_wt6 : 3; /* [26:24] */ + u32 rsv_33 : 1; /* [27] */ + u32 ap_acc_wt7 : 3; /* [30:28] */ + u32 rsv_34 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_ap_acc_wt0_u; + +/* Define the union csr_bmu_ap_acc_wt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_acc_wt8 : 3; /* [2:0] */ + u32 rsv_35 : 1; /* [3] */ + u32 ap_acc_wt9 : 3; /* [6:4] */ + u32 rsv_36 : 1; /* [7] */ + u32 ap_acc_wt10 : 3; /* [10:8] */ + u32 rsv_37 : 1; /* [11] */ + u32 ap_acc_wt11 : 3; /* [14:12] */ + u32 rsv_38 : 1; /* [15] */ + u32 ap_acc_wt12 : 3; /* [18:16] */ + u32 rsv_39 : 1; /* [19] */ + u32 ap_acc_wt13 : 3; /* [22:20] */ + u32 rsv_40 : 1; /* [23] */ + u32 ap_acc_wt14 : 3; /* [26:24] */ + u32 rsv_41 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_ap_acc_wt1_u; + +/* Define the union csr_ti_acc_to_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ti_nm_rreq_to_th0 : 5; /* [4:0] */ + u32 rsv_42 : 3; /* [7:5] */ + u32 ti_nm_rreq_to_th1 : 5; /* [12:8] */ + u32 rsv_43 : 3; /* [15:13] */ + u32 ti_nm_rreq_to_th2 : 5; /* [20:16] */ + u32 rsv_44 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ti_acc_to_th_u; + +/* Define the union csr_bmp_am_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmp_aempty_th : 6; /* [5:0] */ + u32 rsv_45 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmp_am_th_u; + +/* Define the union csr_bk_exht_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_exht_th : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_exht_th_u; + +/* Define the union csr_cell_rd_rls_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cell_rd_rls_en : 1; /* [0] */ + u32 rsv_47 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cell_rd_rls_en_u; + +/* Define the union csr_cpb_age_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_timer_unit_th : 19; /* [18:0] */ + u32 rsv_48 : 1; /* [19] */ + u32 age_auto_rls_en : 1; /* [20] */ + u32 rsv_49 : 3; /* [23:21] */ + u32 cpb_age_en : 1; /* [24] */ + u32 rsv_50 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_age_cfg_u; + +/* Define the union csr_cpb_age_to_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_age_to_th : 23; /* [22:0] */ + u32 rsv_51 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_age_to_th_u; + +/* Define the union csr_bk_age_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_bmp_addr : 8; /* [7:0] */ + u32 bk_age_addr_found : 1; /* [8] */ + u32 rsv_52 : 3; /* [11:9] */ + u32 bk_cur_age_st : 4; /* [15:12] */ + u32 bk_age_scan_busy : 1; /* [16] */ + u32 rsv_53 : 3; /* [19:17] */ + u32 bk_age_scan_req : 1; /* [20] */ + u32 rsv_54 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_cfg_u; + +/* Define the union csr_bk_age_bmp_line_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_bmp_line : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_bmp_line_u; + +/* Define the union csr_bk_age_rls_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_addr : 13; /* [12:0] */ + u32 rsv_55 : 3; /* [15:13] */ + u32 bk_age_rls_req : 1; /* [16] */ + u32 rsv_56 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_rls_cfg_u; + +/* Define the union csr_bk_age_find_nxt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_find_nxt : 1; /* [0] */ + u32 rsv_57 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_find_nxt_u; + +/* Define the union csr_bk_free_rsc_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk0_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_58 : 2; /* [15:14] */ + u32 bk1_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_59 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt0_u; + +/* Define the union csr_bk_free_rsc_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk2_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 bk3_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_61 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt1_u; + +/* Define the union csr_bk_free_rsc_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk4_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 bk5_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_63 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt2_u; + +/* Define the union csr_bk_free_rsc_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk6_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_64 : 2; /* [15:14] */ + u32 bk7_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_65 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt3_u; + +/* Define the union csr_bk_min_rsc_his_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk0_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_66 : 2; /* [15:14] */ + u32 bk1_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_67 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt0_u; + +/* Define the union csr_bk_min_rsc_his_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk2_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 bk3_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_69 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt1_u; + +/* Define the union csr_bk_min_rsc_his_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk4_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_70 : 2; /* [15:14] */ + u32 bk5_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_71 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt2_u; + +/* Define the union csr_bk_min_rsc_his_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk6_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_72 : 2; /* [15:14] */ + u32 bk7_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_73 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt3_u; + +/* Define the union csr_cpb_min_rsc_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_min_rsc_his_cnt : 17; /* [16:0] */ + u32 rsv_74 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_min_rsc_his_cnt_u; + +/* Define the union csr_bmu_rsc_his_cnt_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_min_rsc_his_cnt_clr : 8; /* [7:0] */ + u32 cpb_min_rsc_his_cnt_clr : 1; /* [8] */ + u32 rsv_75 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_rsc_his_cnt_clr_u; + +/* Define the union csr_bmu_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmu_alt_bp : 1; /* [0] */ + u32 rsv_76 : 3; /* [3:1] */ + u32 bmu_fatal_bp : 1; /* [4] */ + u32 rsv_77 : 3; /* [7:5] */ + u32 bk_weak_bp : 8; /* [15:8] */ + u32 bmu_alt_bp_his : 1; /* [16] */ + u32 rsv_78 : 3; /* [19:17] */ + u32 bmu_fatal_bp_his : 1; /* [20] */ + u32 rsv_79 : 3; /* [23:21] */ + u32 bk_weak_bp_his : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_bp_sta_u; + +/* Define the union csr_row_bmp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 row_bmp_free_rsc_cnt : 12; /* [11:0] */ + u32 row_bmp_aempty : 1; /* [12] */ + u32 row_bmp_empty : 1; /* [13] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 row_bmp_aempty_his : 1; /* [16] */ + u32 row_bmp_empty_his : 1; /* [17] */ + u32 rsv_81 : 2; /* [19:18] */ + u32 row_bmp_refrain_err_his : 1; /* [20] */ + u32 row_bmp_leak_err_his : 1; /* [21] */ + u32 rsv_82 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_row_bmp_sta_u; + +/* Define the union csr_age_rls_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt0 : 16; /* [15:0] */ + u32 bk_age_rls_cnt1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_0_u; + +/* Define the union csr_age_rls_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt2 : 16; /* [15:0] */ + u32 bk_age_rls_cnt3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_1_u; + +/* Define the union csr_age_rls_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt4 : 16; /* [15:0] */ + u32 bk_age_rls_cnt5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_2_u; + +/* Define the union csr_age_rls_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt6 : 16; /* [15:0] */ + u32 bk_age_rls_cnt7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_3_u; + +/* Define the union csr_stf_rsp_api_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_npt_fifo_crdt : 5; /* [4:0] */ + u32 rsv_83 : 3; /* [7:5] */ + u32 stf_rsp_dat_fifo_crdt : 6; /* [13:8] */ + u32 rsv_84 : 2; /* [15:14] */ + u32 stf_rsp_api_hdr_fifo_crdt : 4; /* [19:16] */ + u32 stf_rsp_crc_fifo_crdt : 4; /* [23:20] */ + u32 stf_rsp_api_fifo_crdt_init : 1; /* [24] */ + u32 rsv_85 : 3; /* [27:25] */ + u32 stf_str_rsp_hdr_crdt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_fifo_crdt_init_u; + +/* Define the union csr_stf_psh_cmd_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_req_wt : 4; /* [3:0] */ + u32 stf_psh_req_wt : 4; /* [7:4] */ + u32 rsv_86 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_psh_cmd_wt_u; + +/* Define the union csr_stf_col_del_md_hdr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_col_del_md_hdr_en : 1; /* [0] */ + u32 rsv_87 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_col_del_md_hdr_en_u; + +/* Define the union csr_stf_rd_req_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_req_fifo_af_th : 4; /* [3:0] */ + u32 rsv_88 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rd_req_fifo_af_th_u; + +/* Define the union csr_stf_rd_ctrl_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_ctrl_fifo_af_th : 4; /* [3:0] */ + u32 rsv_89 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rd_ctrl_fifo_af_th_u; + +/* Define the union csr_cpb_stf_api_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_stf_api_crdt : 5; /* [4:0] */ + u32 rsv_90 : 3; /* [7:5] */ + u32 cpb_stf_api_crdt_init : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_stf_api_crdt_init_u; + +/* Define the union csr_stf_str_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_str_di_fifo_af_th : 6; /* [5:0] */ + u32 rsv_92 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_di_fifo_af_th_u; + +/* Define the union csr_stf_str_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_str_api_fifo_af_th : 6; /* [5:0] */ + u32 rsv_93 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_api_fifo_af_th_u; + +/* Define the union csr_stf_cmd_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_api_fifo_af_th : 4; /* [3:0] */ + u32 rsv_94 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_cmd_api_fifo_af_th_u; + +/* Define the union csr_stf_ackstr_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_ackstr_fifo_af_th : 3; /* [2:0] */ + u32 rsv_95 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_ackstr_fifo_af_th_u; + +/* Define the union csr_stf_msg_vfid_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fake_vfid_start_bit : 4; /* [3:0] */ + u32 fake_vfid_end_bit : 4; /* [7:4] */ + u32 rsv_96 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_msg_vfid_ctl_u; + +/* Define the union csr_ct_dma_nret_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_nret_psh2pptr_en : 1; /* [0] */ + u32 rsv_97 : 3; /* [3:1] */ + u32 dma_nret_psh2pptr_fix : 1; /* [4] */ + u32 rsv_98 : 3; /* [7:5] */ + u32 psh_pptr_cmd_len : 4; /* [11:8] */ + u32 rsv_99 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_dma_nret_cfg_u; + +/* Define the union csr_ct_col_src_tag_h_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osd_id_i : 4; /* [3:0] */ + u32 osd_id_l : 4; /* [7:4] */ + u32 osd_id_m : 4; /* [11:8] */ + u32 rsv_100 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_col_src_tag_h_cfg_u; + +/* Define the union csr_ct_dealc_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ct_dealc_fifo_af_th : 7; /* [6:0] */ + u32 rsv_101 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_dealc_fifo_af_th_u; + +/* Define the union csr_stfiq_psh_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfpsh_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_102 : 2; /* [7:6] */ + u32 stfpsh_fifo_af_th : 6; /* [13:8] */ + u32 rsv_103 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_psh_fifo_cfg_u; + +/* Define the union csr_stfiq_link_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_104 : 2; /* [7:6] */ + u32 link_fifo_af_th : 6; /* [13:8] */ + u32 rsv_105 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_link_fifo_cfg_u; + +/* Define the union csr_link_wr_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkwr_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_106 : 2; /* [7:6] */ + u32 linkwr_fifo_af_th : 6; /* [13:8] */ + u32 rsv_107 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_wr_fifo_cfg_u; + +/* Define the union csr_stf_cmd_api_rd_req_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_108 : 5; /* [15:11] */ + u32 stf_rd_req_fifo_sta : 11; /* [26:16] */ + u32 rsv_109 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_cmd_api_rd_req_fifo_sta_u; + +/* Define the union csr_stf_str_api_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_str_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_110 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_api_fifo_sta_u; + +/* Define the union csr_stf_wr_rd_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_wr_di_fifo_sta : 11; /* [10:0] */ + u32 rsv_111 : 5; /* [15:11] */ + u32 stf_rd_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_112 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_wr_rd_dat_in_fifo_sta_u; + +/* Define the union csr_stf_rsp_api_hdr_dat_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_dat_fifo_sta : 11; /* [10:0] */ + u32 rsv_113 : 5; /* [15:11] */ + u32 stf_rsp_api_hdr_fifo_sta : 11; /* [26:16] */ + u32 rsv_114 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_hdr_dat_fifo_sta_u; + +/* Define the union csr_stf_rsp_api_cd_crc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_crc_fifo_sta : 11; /* [10:0] */ + u32 rsv_115 : 5; /* [15:11] */ + u32 stf_rsp_api_cd_fifo_sta : 11; /* [26:16] */ + u32 rsv_116 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_cd_crc_fifo_sta_u; + +/* Define the union csr_stf_rsp_api_cs_nptr_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_nptr_fifo_sta : 11; /* [10:0] */ + u32 rsv_117 : 5; /* [15:11] */ + u32 stf_rsp_api_cs_fifo_sta : 11; /* [26:16] */ + u32 rsv_118 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_cs_nptr_fifo_sta_u; + +/* Define the union csr_stf_str_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_cnt : 16; /* [15:0] */ + u32 stf_str_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_cmd_cnt_u; + +/* Define the union csr_stf_ack_rsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_cnt : 16; /* [15:0] */ + u32 stf_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_ack_rsp_cnt_u; + +/* Define the union csr_stf_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_psh_tl_cnt : 16; /* [15:0] */ + u32 stf_iq_psh_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_psh_cnt_u; + +/* Define the union csr_stf_cell_mdf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cell_mdf_cnt : 16; /* [15:0] */ + u32 stf_iq_psh_rm_scol_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_cell_mdf_cnt_u; + +/* Define the union csr_stf_wr_di_ctrl_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_wr_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_119 : 5; /* [15:11] */ + u32 stf_ackstr_fifo_sta : 11; /* [26:16] */ + u32 rsv_120 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_wr_di_ctrl_fifo_sta_u; + +/* Define the union csr_stf_fifo_ov_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_req_fifo_ov : 4; /* [3:0] */ + u32 stf_cmd_api_fifo_ov : 4; /* [7:4] */ + u32 stf_str_api_fifo_ov : 4; /* [11:8] */ + u32 stf_rd_di_fifo_ov : 2; /* [13:12] */ + u32 rsv_121 : 2; /* [15:14] */ + u32 stf_wr_di_fifo_ov : 2; /* [17:16] */ + u32 rsv_122 : 2; /* [19:18] */ + u32 stf_wr_di_ctrl_fifo_ov : 2; /* [21:20] */ + u32 rsv_123 : 2; /* [23:22] */ + u32 stf_ackstr_fifo_ov : 2; /* [25:24] */ + u32 rsv_124 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_ov_err_0_u; + +/* Define the union csr_stf_fifo_ov_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_hdr_fifo_ov : 4; /* [3:0] */ + u32 stf_rsp_api_dat_fifo_ov : 4; /* [7:4] */ + u32 stf_rsp_api_cd_fifo_ov : 4; /* [11:8] */ + u32 stf_rsp_api_crc_fifo_ov : 4; /* [15:12] */ + u32 stf_rsp_api_cs_fifo_ov : 4; /* [19:16] */ + u32 stf_rsp_api_nptr_fifo_ov : 4; /* [23:20] */ + u32 rsv_125 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_ov_err_1_u; + +/* Define the union csr_stf_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_req_fifo_uf : 4; /* [3:0] */ + u32 stf_cmd_api_fifo_uf : 4; /* [7:4] */ + u32 stf_str_api_fifo_uf : 4; /* [11:8] */ + u32 stf_rd_di_fifo_uf : 2; /* [13:12] */ + u32 rsv_126 : 2; /* [15:14] */ + u32 stf_wr_di_fifo_uf : 2; /* [17:16] */ + u32 rsv_127 : 2; /* [19:18] */ + u32 stf_wr_di_ctrl_fifo_uf : 2; /* [21:20] */ + u32 rsv_128 : 2; /* [23:22] */ + u32 stf_ackstr_fifo_uf : 2; /* [25:24] */ + u32 rsv_129 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_uf_err_0_u; + +/* Define the union csr_stf_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_hdr_fifo_uf : 4; /* [3:0] */ + u32 stf_rsp_api_dat_fifo_uf : 4; /* [7:4] */ + u32 stf_rsp_api_cd_fifo_uf : 4; /* [11:8] */ + u32 stf_rsp_api_crc_fifo_uf : 4; /* [15:12] */ + u32 stf_rsp_api_cs_fifo_uf : 4; /* [19:16] */ + u32 stf_rsp_api_nptr_fifo_uf : 4; /* [23:20] */ + u32 rsv_130 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_uf_err_1_u; + +/* Define the union csr_ct_ext_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ct_ext_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_131 : 5; /* [15:11] */ + u32 ct_ext_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_132 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_ext_dealc_fifo_sta_u; + +/* Define the union csr_stf_pcol_num_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_pcol_num_err : 4; /* [3:0] */ + u32 rsv_133 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_pcol_num_err_u; + +/* Define the union csr_stfwr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfwr_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_134 : 7; /* [11:5] */ + u32 stfwr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stfwr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_135 : 2; /* [15:14] */ + u32 stfwr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfwr_fifo_ram_err_u; + +/* Define the union csr_stfstr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfstr_fifo_mem_err_addr : 6; /* [5:0] */ + u32 rsv_136 : 6; /* [11:6] */ + u32 stfstr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stfstr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_137 : 2; /* [15:14] */ + u32 stfstr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfstr_fifo_ram_err_u; + +/* Define the union csr_stfrsp_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfrsp_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_138 : 7; /* [11:5] */ + u32 stfrsp_fifo_mem_err_cerr : 1; /* [12] */ + u32 stfrsp_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_139 : 2; /* [15:14] */ + u32 stfrsp_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfrsp_fifo_ram_err_u; + +/* Define the union csr_stfiq_pkt_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_pkt_psh_cnt : 16; /* [15:0] */ + u32 rsv_140 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_pkt_psh_cnt_u; + +/* Define the union csr_stfiq_msg_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_msg_psh_cnt : 16; /* [15:0] */ + u32 rsv_141 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_msg_psh_cnt_u; + +/* Define the union csr_stfiq_col_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_col_psh_cnt : 16; /* [15:0] */ + u32 rsv_142 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_col_psh_cnt_u; + +/* Define the union csr_stfiq_link_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_link_req_cnt : 16; /* [15:0] */ + u32 rsv_143 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_link_req_cnt_u; + +/* Define the union csr_stfiq_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_psh_fifo_sta : 10; /* [9:0] */ + u32 rsv_144 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_psh_fifo_sta_u; + +/* Define the union csr_stfiq_link_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_link_fifo_sta : 10; /* [9:0] */ + u32 rsv_145 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_link_fifo_sta_u; + +/* Define the union csr_link_wr_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_wr_fifo_sta : 10; /* [9:0] */ + u32 rsv_146 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_wr_fifo_sta_u; + +/* Define the union csr_ciq_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_psh_fifo_of_err : 4; /* [3:0] */ + u32 stfiq_psh_fifo_of_err : 4; /* [7:4] */ + u32 stfiq_link_fifo_of_err : 4; /* [11:8] */ + u32 link_wr_fifo_of_err : 1; /* [12] */ + u32 rob_psh_fifo_of_err : 1; /* [13] */ + u32 rsv_147 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_fifo_of_err_u; + +/* Define the union csr_ciq_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_psh_fifo_uf_err : 4; /* [3:0] */ + u32 stfiq_psh_fifo_uf_err : 4; /* [7:4] */ + u32 stfiq_link_fifo_uf_err : 4; /* [11:8] */ + u32 link_wr_fifo_uf_err : 1; /* [12] */ + u32 rob_psh_fifo_uf_err : 1; /* [13] */ + u32 rsv_148 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_fifo_uf_err_u; + +/* Define the union csr_ciq_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_psh_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_149 : 3; /* [7:5] */ + u32 stfiq_psh_fifo_mem_cerr : 1; /* [8] */ + u32 stfiq_psh_fifo_mem_ucerr : 1; /* [9] */ + u32 rsv_150 : 6; /* [15:10] */ + u32 stfiq_psh_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_ram_err_u; + +/* Define the union csr_ciq_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_col_psh_err : 1; /* [0] */ + u32 rsv_151 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_err_u; + +/* Define the union csr_dat_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_mem_err_addr : 13; /* [12:0] */ + u32 rsv_152 : 1; /* [13] */ + u32 dat_mem_err_cerr : 1; /* [14] */ + u32 dat_mem_err_ucerr : 1; /* [15] */ + u32 dat_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dat_ram_err_u; + +/* Define the union csr_cd_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cd_mem_err_addr : 13; /* [12:0] */ + u32 rsv_153 : 1; /* [13] */ + u32 cd_mem_err_cerr : 1; /* [14] */ + u32 cd_mem_err_ucerr : 1; /* [15] */ + u32 cd_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cd_ram_err_u; + +/* Define the union csr_nptr_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nptr_mem_err_addr : 13; /* [12:0] */ + u32 rsv_154 : 1; /* [13] */ + u32 nptr_mem_err_cerr : 1; /* [14] */ + u32 nptr_mem_err_ucerr : 1; /* [15] */ + u32 nptr_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nptr_ram_err_u; + +/* Define the union csr_ti_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ti_mem_err_addr : 13; /* [12:0] */ + u32 rsv_155 : 1; /* [13] */ + u32 ti_mem_err_cerr : 1; /* [14] */ + u32 ti_mem_err_ucerr : 1; /* [15] */ + u32 ti_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ti_ram_err_u; + +/* Define the union csr_bmp_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmp_mem_err_addr : 8; /* [7:0] */ + u32 bmp_mem_err_cerr : 1; /* [8] */ + u32 bmp_mem_err_ucerr : 1; /* [9] */ + u32 rsv_156 : 6; /* [15:10] */ + u32 bmp_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmp_ram_err_u; + +/* Define the union csr_age_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 age_mem_err_addr : 8; /* [7:0] */ + u32 age_mem_err_cerr : 1; /* [8] */ + u32 age_mem_err_ucerr : 1; /* [9] */ + u32 rsv_157 : 6; /* [15:10] */ + u32 age_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_ram_err_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cpb_fpga_ver_u cpb_fpga_ver; /* 0 */ + volatile csr_cpb_emu_ver_u cpb_emu_ver; /* 4 */ + volatile csr_cpb_bank_row_en_u cpb_bank_row_en; /* C */ + volatile csr_cpb_dat_init_start_u cpb_dat_init_start; /* 10 */ + volatile csr_cpb_cd_init_start_u cpb_cd_init_start; /* 14 */ + volatile csr_cpb_nptr_init_start_u cpb_nptr_init_start; /* 18 */ + volatile csr_cpb_ti_init_start_u cpb_ti_init_start; /* 1C */ + volatile csr_cpb_dat_init_done_u cpb_dat_init_done; /* 20 */ + volatile csr_cpb_cd_init_done_u cpb_cd_init_done; /* 24 */ + volatile csr_cpb_nptr_init_done_u cpb_nptr_init_done; /* 28 */ + volatile csr_cpb_ti_init_done_u cpb_ti_init_done; /* 2C */ + volatile csr_cpb_bmp_init_start_u cpb_bmp_init_start; /* 30 */ + volatile csr_cpb_bmp_init_done_u cpb_bmp_init_done; /* 34 */ + volatile csr_cpb_init_start_u cpb_init_start; /* 38 */ + volatile csr_cpb_init_done_u cpb_init_done; /* 3C */ + volatile csr_cpb_int_vector_u cpb_int_vector; /* 40 */ + volatile csr_cpb_int_u cpb_int; /* 44 */ + volatile csr_cpb_int_en_u cpb_int_en; /* 48 */ + volatile csr_cpb_ram_ucerr_u cpb_ram_ucerr; /* 4C */ + volatile csr_cpb_ram_cerr_u cpb_ram_cerr; /* 50 */ + volatile csr_cpb_fifo_of_err_u cpb_fifo_of_err; /* 54 */ + volatile csr_cpb_fifo_uf_err_u cpb_fifo_uf_err; /* 58 */ + volatile csr_cpb_rx_crdt_err_u cpb_rx_crdt_err; /* 5C */ + volatile csr_cpb_tx_crdt_err_u cpb_tx_crdt_err; /* 60 */ + volatile csr_tx_prealc_crdt_err_u tx_prealc_crdt_err; /* 64 */ + volatile csr_cpb_bp_drop_err_u cpb_bp_drop_err; /* 68 */ + volatile csr_cir_cit_abn_err_u cir_cit_abn_err; /* 6C */ + volatile csr_cpr_cpt_abn_err_u cpr_cpt_abn_err; /* 70 */ + volatile csr_ct_abn_err_u ct_abn_err; /* 74 */ + volatile csr_cq_abn_err_u cq_abn_err; /* 78 */ + volatile csr_rx_tx_abn_err_u rx_tx_abn_err; /* 7C */ + volatile csr_cpb_bmu_rsc_err_u cpb_bmu_rsc_err; /* 80 */ + volatile csr_cpb_aging_err_u cpb_aging_err; /* 84 */ + volatile csr_cpb_fatal_err_en_u cpb_fatal_err_en; /* 90 */ + volatile csr_cpb_fatal_err_sta_u cpb_fatal_err_sta; /* 94 */ + volatile csr_cpb_itf_bp_sta_u cpb_itf_bp_sta; /* A0 */ + volatile csr_cpb_itf_bp_his_u cpb_itf_bp_his; /* A4 */ + volatile csr_cpb_api_err_u cpb_api_err; /* D0 */ + volatile csr_cpb_fifo_err_col_u cpb_fifo_err_col; /* D4 */ + volatile csr_tl_req_invld_u tl_req_invld; /* D8 */ + volatile csr_tl_str_err_0_u tl_str_err_0; /* DC */ + volatile csr_tl_str_err_1_u tl_str_err_1; /* E0 */ + volatile csr_tl_str_err_2_u tl_str_err_2; /* E4 */ + volatile csr_cpb_ram_ctrl_bus_0_u cpb_ram_ctrl_bus_0; /* 100 */ + volatile csr_cpb_ram_ctrl_bus_1_u cpb_ram_ctrl_bus_1; /* 104 */ + volatile csr_cpb_ram_ctrl_bus_2_u cpb_ram_ctrl_bus_2; /* 108 */ + volatile csr_cpb_ram_ctrl_bus_3_u cpb_ram_ctrl_bus_3; /* 10C */ + volatile csr_cpb_ram_ctrl_bus_4_u cpb_ram_ctrl_bus_4; /* 110 */ + volatile csr_cpb_ram_ecc_bypass_u cpb_ram_ecc_bypass; /* 114 */ + volatile csr_cpb_indir_ctrl_u cpb_indir_ctrl; /* 170 */ + volatile csr_cpb_indir_to_th_u cpb_indir_to_th; /* 174 */ + volatile csr_bank_weak_cfg_u bank_weak_cfg; /* 200 */ + volatile csr_bmu_alt_bp_cfg_u bmu_alt_bp_cfg; /* 204 */ + volatile csr_bmu_fat_bp_cfg_u bmu_fat_bp_cfg; /* 208 */ + volatile csr_bmu_ap_acc_wt0_u bmu_ap_acc_wt0; /* 210 */ + volatile csr_bmu_ap_acc_wt1_u bmu_ap_acc_wt1; /* 214 */ + volatile csr_ti_acc_to_th_u ti_acc_to_th; /* 218 */ + volatile csr_bmp_am_th_u bmp_am_th; /* 220 */ + volatile csr_bk_exht_th_u bk_exht_th; /* 224 */ + volatile csr_cell_rd_rls_en_u cell_rd_rls_en; /* 228 */ + volatile csr_cpb_age_cfg_u cpb_age_cfg; /* 258 */ + volatile csr_cpb_age_to_th_u cpb_age_to_th; /* 25C */ + volatile csr_bk_age_cfg_u bk_age_cfg[8]; /* 260 */ + volatile csr_bk_age_bmp_line_u bk_age_bmp_line[8]; /* 280 */ + volatile csr_bk_age_rls_cfg_u bk_age_rls_cfg[8]; /* 2A0 */ + volatile csr_bk_age_find_nxt_u bk_age_find_nxt[8]; /* 2C0 */ + volatile csr_bk_free_rsc_cnt0_u bk_free_rsc_cnt0; /* 300 */ + volatile csr_bk_free_rsc_cnt1_u bk_free_rsc_cnt1; /* 304 */ + volatile csr_bk_free_rsc_cnt2_u bk_free_rsc_cnt2; /* 308 */ + volatile csr_bk_free_rsc_cnt3_u bk_free_rsc_cnt3; /* 30C */ + volatile csr_bk_min_rsc_his_cnt0_u bk_min_rsc_his_cnt0; /* 310 */ + volatile csr_bk_min_rsc_his_cnt1_u bk_min_rsc_his_cnt1; /* 314 */ + volatile csr_bk_min_rsc_his_cnt2_u bk_min_rsc_his_cnt2; /* 318 */ + volatile csr_bk_min_rsc_his_cnt3_u bk_min_rsc_his_cnt3; /* 31C */ + volatile csr_cpb_min_rsc_his_cnt_u cpb_min_rsc_his_cnt; /* 320 */ + volatile csr_bmu_rsc_his_cnt_clr_u bmu_rsc_his_cnt_clr; /* 324 */ + volatile csr_bmu_bp_sta_u bmu_bp_sta; /* 328 */ + volatile csr_row_bmp_sta_u row_bmp_sta[32]; /* 330 */ + volatile csr_age_rls_cnt_0_u age_rls_cnt_0; /* 3B0 */ + volatile csr_age_rls_cnt_1_u age_rls_cnt_1; /* 3B4 */ + volatile csr_age_rls_cnt_2_u age_rls_cnt_2; /* 3B8 */ + volatile csr_age_rls_cnt_3_u age_rls_cnt_3; /* 3BC */ + volatile csr_stf_rsp_api_fifo_crdt_init_u stf_rsp_api_fifo_crdt_init; /* 830 */ + volatile csr_stf_psh_cmd_wt_u stf_psh_cmd_wt; /* 834 */ + volatile csr_stf_col_del_md_hdr_en_u stf_col_del_md_hdr_en; /* 838 */ + volatile csr_stf_rd_req_fifo_af_th_u stf_rd_req_fifo_af_th; /* 83C */ + volatile csr_stf_rd_ctrl_fifo_af_th_u stf_rd_ctrl_fifo_af_th; /* 840 */ + volatile csr_cpb_stf_api_crdt_init_u cpb_stf_api_crdt_init; /* 844 */ + volatile csr_stf_str_di_fifo_af_th_u stf_str_di_fifo_af_th; /* 848 */ + volatile csr_stf_str_api_fifo_af_th_u stf_str_api_fifo_af_th; /* 84C */ + volatile csr_stf_cmd_api_fifo_af_th_u stf_cmd_api_fifo_af_th; /* 850 */ + volatile csr_stf_ackstr_fifo_af_th_u stf_ackstr_fifo_af_th; /* 854 */ + volatile csr_stf_msg_vfid_ctl_u stf_msg_vfid_ctl; /* 860 */ + volatile csr_ct_dma_nret_cfg_u ct_dma_nret_cfg; /* 864 */ + volatile csr_ct_col_src_tag_h_cfg_u ct_col_src_tag_h_cfg; /* 868 */ + volatile csr_ct_dealc_fifo_af_th_u ct_dealc_fifo_af_th; /* 870 */ + volatile csr_stfiq_psh_fifo_cfg_u stfiq_psh_fifo_cfg; /* 910 */ + volatile csr_stfiq_link_fifo_cfg_u stfiq_link_fifo_cfg; /* 920 */ + volatile csr_link_wr_fifo_cfg_u link_wr_fifo_cfg; /* 924 */ + volatile csr_stf_cmd_api_rd_req_fifo_sta_u stf_cmd_api_rd_req_fifo_sta[4]; /* 1500 */ + volatile csr_stf_str_api_fifo_sta_u stf_str_api_fifo_sta[4]; /* 1510 */ + volatile csr_stf_wr_rd_dat_in_fifo_sta_u stf_wr_rd_dat_in_fifo_sta[2]; /* 1520 */ + volatile csr_stf_rsp_api_hdr_dat_fifo_sta_u stf_rsp_api_hdr_dat_fifo_sta[4]; /* 1530 */ + volatile csr_stf_rsp_api_cd_crc_fifo_sta_u stf_rsp_api_cd_crc_fifo_sta[4]; /* 1540 */ + volatile csr_stf_rsp_api_cs_nptr_fifo_sta_u stf_rsp_api_cs_nptr_fifo_sta[4]; /* 1550 */ + volatile csr_stf_str_cmd_cnt_u stf_str_cmd_cnt[4]; /* 1560 */ + volatile csr_stf_ack_rsp_cnt_u stf_ack_rsp_cnt[4]; /* 1570 */ + volatile csr_stf_psh_cnt_u stf_psh_cnt[4]; /* 1580 */ + volatile csr_stf_cell_mdf_cnt_u stf_cell_mdf_cnt[4]; /* 1590 */ + volatile csr_stf_wr_di_ctrl_fifo_sta_u stf_wr_di_ctrl_fifo_sta[2]; /* 15A4 */ + volatile csr_stf_fifo_ov_err_0_u stf_fifo_ov_err_0; /* 15B0 */ + volatile csr_stf_fifo_ov_err_1_u stf_fifo_ov_err_1; /* 15B4 */ + volatile csr_stf_fifo_uf_err_0_u stf_fifo_uf_err_0; /* 15B8 */ + volatile csr_stf_fifo_uf_err_1_u stf_fifo_uf_err_1; /* 15BC */ + volatile csr_ct_ext_dealc_fifo_sta_u ct_ext_dealc_fifo_sta; /* 15C0 */ + volatile csr_stf_pcol_num_err_u stf_pcol_num_err; /* 15C4 */ + volatile csr_stfwr_fifo_ram_err_u stfwr_fifo_ram_err[2]; /* 15D8 */ + volatile csr_stfstr_fifo_ram_err_u stfstr_fifo_ram_err[4]; /* 15E0 */ + volatile csr_stfrsp_fifo_ram_err_u stfrsp_fifo_ram_err[4]; /* 15F0 */ + volatile csr_stfiq_pkt_psh_cnt_u stfiq_pkt_psh_cnt[4]; /* 1620 */ + volatile csr_stfiq_msg_psh_cnt_u stfiq_msg_psh_cnt[4]; /* 1630 */ + volatile csr_stfiq_col_psh_cnt_u stfiq_col_psh_cnt[4]; /* 1640 */ + volatile csr_stfiq_link_req_cnt_u stfiq_link_req_cnt[4]; /* 1650 */ + volatile csr_stfiq_psh_fifo_sta_u stfiq_psh_fifo_sta[4]; /* 1690 */ + volatile csr_stfiq_link_fifo_sta_u stfiq_link_fifo_sta[4]; /* 16A0 */ + volatile csr_link_wr_fifo_sta_u link_wr_fifo_sta; /* 16B0 */ + volatile csr_ciq_fifo_of_err_u ciq_fifo_of_err; /* 16C0 */ + volatile csr_ciq_fifo_uf_err_u ciq_fifo_uf_err; /* 16C4 */ + volatile csr_ciq_ram_err_u ciq_ram_err[4]; /* 16C8 */ + volatile csr_ciq_err_u ciq_err; /* 16E0 */ + volatile csr_dat_ram_err_u dat_ram_err[8]; /* 1BA0 */ + volatile csr_cd_ram_err_u cd_ram_err[8]; /* 1BC0 */ + volatile csr_nptr_ram_err_u nptr_ram_err[8]; /* 1BE0 */ + volatile csr_ti_ram_err_u ti_ram_err[8]; /* 1C00 */ + volatile csr_bmp_ram_err_u bmp_ram_err[8]; /* 1C20 */ + volatile csr_age_ram_err_u age_ram_err[8]; /* 1C40 */ +} S_cpb_csr_0_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_0 */ +extern volatile S_cpb_csr_0_REGS_TYPE *gopcpb_csr_0AllReg; + +/* Declare the functions that set the member value */ +int iSetCPB_FPGA_VER_cpb_fpga_ver(unsigned int ucpb_fpga_ver); +int iSetCPB_EMU_VER_cpb_emu_ver(unsigned int ucpb_emu_ver); +int iSetCPB_BANK_ROW_EN_cpb_bk_row_en(unsigned int ucpb_bk_row_en); +int iSetCPB_DAT_INIT_START_cpb_datmem_init_start(unsigned int ucpb_datmem_init_start); +int iSetCPB_CD_INIT_START_cpb_cdmem_init_start(unsigned int ucpb_cdmem_init_start); +int iSetCPB_NPTR_INIT_START_cpb_nptrmem_init_start(unsigned int ucpb_nptrmem_init_start); +int iSetCPB_TI_INIT_START_cpb_timem_init_start(unsigned int ucpb_timem_init_start); +int iSetCPB_DAT_INIT_DONE_cpb_datmem_init_done(unsigned int ucpb_datmem_init_done); +int iSetCPB_CD_INIT_DONE_cpb_cdmem_init_done(unsigned int ucpb_cdmem_init_done); +int iSetCPB_NPTR_INIT_DONE_cpb_nptrmem_init_done(unsigned int ucpb_nptrmem_init_done); +int iSetCPB_TI_INIT_DONE_cpb_timem_init_done(unsigned int ucpb_timem_init_done); +int iSetCPB_BMP_INIT_START_cpb_bmp_init_start(unsigned int ucpb_bmp_init_start); +int iSetCPB_BMP_INIT_DONE_cpb_bmp_init_done(unsigned int ucpb_bmp_init_done); +int iSetCPB_INIT_START_fpa_init_start(unsigned int ufpa_init_start); +int iSetCPB_INIT_START_tso_ctxm_init_start(unsigned int utso_ctxm_init_start); +int iSetCPB_INIT_START_tx_port_fp_init_start(unsigned int utx_port_fp_init_start); +int iSetCPB_INIT_START_rxlb_fp_init_start(unsigned int urxlb_fp_init_start); +int iSetCPB_INIT_DONE_cpb_init_done(unsigned int ucpb_init_done); +int iSetCPB_INIT_DONE_fpa_init_done(unsigned int ufpa_init_done); +int iSetCPB_INIT_DONE_tso_ctxm_init_done(unsigned int utso_ctxm_init_done); +int iSetCPB_INIT_DONE_tx_port_fp_init_done(unsigned int utx_port_fp_init_done); +int iSetCPB_INIT_DONE_rxlb_fp_init_done(unsigned int urxlb_fp_init_done); +int iSetCPB_INT_VECTOR_cpb_cpi_int_index(unsigned int ucpb_cpi_int_index); +int iSetCPB_INT_VECTOR_cpb_int_enable(unsigned int ucpb_int_enable); +int iSetCPB_INT_VECTOR_cpb_int_issue(unsigned int ucpb_int_issue); +int iSetCPB_INT_cpb_int_data(unsigned int ucpb_int_data); +int iSetCPB_INT_cpb_program_csr_id_ro(unsigned int ucpb_program_csr_id_ro); +int iSetCPB_INT_EN_cpb_int_en(unsigned int ucpb_int_en); +int iSetCPB_INT_EN_cpb_program_csr_id(unsigned int ucpb_program_csr_id); +int iSetCPB_RAM_UCERR_cpb_ram_ucerr(unsigned int ucpb_ram_ucerr); +int iSetCPB_RAM_UCERR_cpb_ram_ucerr_inj(unsigned int ucpb_ram_ucerr_inj); +int iSetCPB_RAM_UCERR_cpb_ram_ucerr_stickey(unsigned int ucpb_ram_ucerr_stickey); +int iSetCPB_RAM_CERR_cpb_ram_cerr(unsigned int ucpb_ram_cerr); +int iSetCPB_RAM_CERR_cpb_ram_cerr_inj(unsigned int ucpb_ram_cerr_inj); +int iSetCPB_RAM_CERR_cpb_ram_cerr_stickey(unsigned int ucpb_ram_cerr_stickey); +int iSetCPB_FIFO_OF_ERR_cpb_fifo_of_err(unsigned int ucpb_fifo_of_err); +int iSetCPB_FIFO_OF_ERR_cpb_fifo_of_err_inj(unsigned int ucpb_fifo_of_err_inj); +int iSetCPB_FIFO_OF_ERR_cpb_fifo_of_err_stickey(unsigned int ucpb_fifo_of_err_stickey); +int iSetCPB_FIFO_UF_ERR_cpb_fifo_uf_err(unsigned int ucpb_fifo_uf_err); +int iSetCPB_FIFO_UF_ERR_cpb_fifo_uf_err_inj(unsigned int ucpb_fifo_uf_err_inj); +int iSetCPB_FIFO_UF_ERR_cpb_fifo_uf_err_stickey(unsigned int ucpb_fifo_uf_err_stickey); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_of_err(unsigned int ucpb_rx_crdt_of_err); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_uf_err(unsigned int ucpb_rx_crdt_uf_err); +int iSetCPB_RX_CRDT_ERR_sge_zero_err(unsigned int usge_zero_err); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_of_err_inj(unsigned int ucpb_rx_crdt_of_err_inj); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_uf_err_inj(unsigned int ucpb_rx_crdt_uf_err_inj); +int iSetCPB_RX_CRDT_ERR_sge_zero_err_inj(unsigned int usge_zero_err_inj); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_err_stickey(unsigned int ucpb_rx_crdt_err_stickey); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_of_err(unsigned int ucpb_tx_crdt_of_err); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_uf_err(unsigned int ucpb_tx_crdt_uf_err); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_of_err_inj(unsigned int ucpb_tx_crdt_of_err_inj); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_uf_err_inj(unsigned int ucpb_tx_crdt_uf_err_inj); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_err_stickey(unsigned int ucpb_tx_crdt_err_stickey); +int iSetTX_PREALC_CRDT_ERR_tx_prealc_crdt_err(unsigned int utx_prealc_crdt_err); +int iSetTX_PREALC_CRDT_ERR_tx_prealc_crdt_err_inj(unsigned int utx_prealc_crdt_err_inj); +int iSetTX_PREALC_CRDT_ERR_tx_prealc_crdt_err_stickey(unsigned int utx_prealc_crdt_err_stickey); +int iSetCPB_BP_DROP_ERR_cpb_bp_drop_err(unsigned int ucpb_bp_drop_err); +int iSetCPB_BP_DROP_ERR_cpb_bp_drop_err_inj(unsigned int ucpb_bp_drop_err_inj); +int iSetCPB_BP_DROP_ERR_cpb_bp_drop_err_stickey(unsigned int ucpb_bp_drop_err_stickey); +int iSetCIR_CIT_ABN_ERR_cir_abn_err(unsigned int ucir_abn_err); +int iSetCIR_CIT_ABN_ERR_cit_abn_err(unsigned int ucit_abn_err); +int iSetCIR_CIT_ABN_ERR_cir_abn_err_inj(unsigned int ucir_abn_err_inj); +int iSetCIR_CIT_ABN_ERR_cit_abn_err_inj(unsigned int ucit_abn_err_inj); +int iSetCIR_CIT_ABN_ERR_cir_cit_abn_err_stickey(unsigned int ucir_cit_abn_err_stickey); +int iSetCPR_CPT_ABN_ERR_cpr_abn_err(unsigned int ucpr_abn_err); +int iSetCPR_CPT_ABN_ERR_cpt_abn_err(unsigned int ucpt_abn_err); +int iSetCPR_CPT_ABN_ERR_cpr_abn_err_inj(unsigned int ucpr_abn_err_inj); +int iSetCPR_CPT_ABN_ERR_cpt_abn_err_inj(unsigned int ucpt_abn_err_inj); +int iSetCPR_CPT_ABN_ERR_cpr_cpt_abn_err_stickey(unsigned int ucpr_cpt_abn_err_stickey); +int iSetCT_ABN_ERR_cstl_abn_err(unsigned int ucstl_abn_err); +int iSetCT_ABN_ERR_cstf_abn_err(unsigned int ucstf_abn_err); +int iSetCT_ABN_ERR_cstl_abn_err_inj(unsigned int ucstl_abn_err_inj); +int iSetCT_ABN_ERR_cstf_abn_err_inj(unsigned int ucstf_abn_err_inj); +int iSetCT_ABN_ERR_ct_abn_err_stickey(unsigned int uct_abn_err_stickey); +int iSetCQ_ABN_ERR_ciq_abn_err(unsigned int uciq_abn_err); +int iSetCQ_ABN_ERR_coq_abn_err(unsigned int ucoq_abn_err); +int iSetCQ_ABN_ERR_ciq_abn_err_inj(unsigned int uciq_abn_err_inj); +int iSetCQ_ABN_ERR_coq_abn_err_inj(unsigned int ucoq_abn_err_inj); +int iSetCQ_ABN_ERR_cq_abn_err_stickey(unsigned int ucq_abn_err_stickey); +int iSetRX_TX_ABN_ERR_cpb_rx_abn_err(unsigned int ucpb_rx_abn_err); +int iSetRX_TX_ABN_ERR_cpb_tx_abn_err(unsigned int ucpb_tx_abn_err); +int iSetRX_TX_ABN_ERR_cpb_rx_abn_err_inj(unsigned int ucpb_rx_abn_err_inj); +int iSetRX_TX_ABN_ERR_cpb_tx_abn_err_inj(unsigned int ucpb_tx_abn_err_inj); +int iSetRX_TX_ABN_ERR_rx_tx_abn_err_stickey(unsigned int urx_tx_abn_err_stickey); +int iSetCPB_BMU_RSC_ERR_cpb_bmu_err(unsigned int ucpb_bmu_err); +int iSetCPB_BMU_RSC_ERR_cpb_bmu_err_inj(unsigned int ucpb_bmu_err_inj); +int iSetCPB_BMU_RSC_ERR_cpb_bmu_err_stickey(unsigned int ucpb_bmu_err_stickey); +int iSetCPB_AGING_ERR_cpb_aging_err(unsigned int ucpb_aging_err); +int iSetCPB_AGING_ERR_cpb_aging_err_inj(unsigned int ucpb_aging_err_inj); +int iSetCPB_AGING_ERR_cpb_aging_err_stickey(unsigned int ucpb_aging_err_stickey); +int iSetCPB_FATAL_ERR_EN_cpb_ram_ucerr_fatal_en(unsigned int ucpb_ram_ucerr_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_fifo_of_fatal_en(unsigned int ucpb_fifo_of_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_fifo_uf_fatal_en(unsigned int ucpb_fifo_uf_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_rx_crdt_err_fatal_en(unsigned int ucpb_rx_crdt_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_tx_crdt_err_fatal_en(unsigned int ucpb_tx_crdt_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_ipsu_itf_err_fatal_en(unsigned int ucpb_ipsu_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_pe_itf_err_fatal_en(unsigned int ucpb_pe_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_tile_itf_err_fatal_en(unsigned int ucpb_tile_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_qu_itf_err_fatal_en(unsigned int ucpb_qu_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_rxtx_itf_err_fatal_en(unsigned int ucpb_rxtx_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_bmp_err_fatal_en(unsigned int ucpb_bmp_err_fatal_en); +int iSetCPB_FATAL_ERR_STA_cpb_ram_ucerr_fatal_sta(unsigned int ucpb_ram_ucerr_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_of_fatal_sta(unsigned int ucpb_fifo_of_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_uf_fatal_sta(unsigned int ucpb_fifo_uf_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_rx_crdt_err_fatal_sta(unsigned int ucpb_rx_crdt_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_tx_crdt_err_fatal_sta(unsigned int ucpb_tx_crdt_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_ipsu_itf_err_fatal_sta(unsigned int ucpb_ipsu_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_pe_itf_err_fatal_sta(unsigned int ucpb_pe_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_tile_itf_err_fatal_sta(unsigned int ucpb_tile_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_qu_itf_err_fatal_sta(unsigned int ucpb_qu_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_rxtx_itf_err_fatal_sta(unsigned int ucpb_rxtx_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_bmp_err_fatal_sta(unsigned int ucpb_bmp_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_ram_ucerr_fatal_clr(unsigned int ucpb_ram_ucerr_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_of_fatal_clr(unsigned int ucpb_fifo_of_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_uf_fatal_clr(unsigned int ucpb_fifo_uf_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_rx_crdt_err_fatal_clr(unsigned int ucpb_rx_crdt_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_tx_crdt_err_fatal_clr(unsigned int ucpb_tx_crdt_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_ipsu_itf_err_fatal_clr(unsigned int ucpb_ipsu_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_pe_itf_err_fatal_clr(unsigned int ucpb_pe_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_tile_itf_err_fatal_clr(unsigned int ucpb_tile_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_qu_itf_err_fatal_clr(unsigned int ucpb_qu_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_rxtx_itf_err_fatal_clr(unsigned int ucpb_rxtx_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_bmp_err_fatal_clr(unsigned int ucpb_bmp_err_fatal_clr); +int iSetCPB_ITF_BP_STA_cpb_ipsurx_bp_sta(unsigned int ucpb_ipsurx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_ipsutx_bp_sta(unsigned int ucpb_ipsutx_bp_sta); +int iSetCPB_ITF_BP_STA_iq_cpb_rx_bp_sta(unsigned int uiq_cpb_rx_bp_sta); +int iSetCPB_ITF_BP_STA_iq_cpb_tx_bp_sta(unsigned int uiq_cpb_tx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_stliq_req_bp_sta(unsigned int ucpb_stliq_req_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_stfiq_req_bp_sta(unsigned int ucpb_stfiq_req_bp_sta); +int iSetCPB_ITF_BP_STA_stlfq_cpb_ackstr_bp_sta(unsigned int ustlfq_cpb_ackstr_bp_sta); +int iSetCPB_ITF_BP_STA_stffq_cpb_ackstr_bp_sta(unsigned int ustffq_cpb_ackstr_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_alloc_rx_bp_sta(unsigned int uprm_cpb_alloc_rx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_alloc_tx_bp_sta(unsigned int uprm_cpb_alloc_tx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_dealloc_rx_bp_sta(unsigned int uprm_cpb_dealloc_rx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_dealloc_tx_bp_sta(unsigned int uprm_cpb_dealloc_tx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_prls_bp_sta(unsigned int uprm_cpb_prls_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_oq_rx_bp_sta(unsigned int ucpb_oq_rx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_oq_tx_bp_sta(unsigned int ucpb_oq_tx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_oq_drp_bp_sta(unsigned int ucpb_oq_drp_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_pqm_host_bp_sta(unsigned int ucpb_pqm_host_bp_sta); +int iSetCPB_ITF_BP_STA_rx_prm_bp_sta(unsigned int urx_prm_bp_sta); +int iSetCPB_ITF_BP_STA_tx_mag_bp_sta(unsigned int utx_mag_bp_sta); +int iSetCPB_ITF_BP_STA_rx_crdt_bp_sta(unsigned int urx_crdt_bp_sta); +int iSetCPB_ITF_BP_STA_tx_crdt_bp_sta(unsigned int utx_crdt_bp_sta); +int iSetCPB_ITF_BP_HIS_cpb_ipsurx_bp_his(unsigned int ucpb_ipsurx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_ipsutx_bp_his(unsigned int ucpb_ipsutx_bp_his); +int iSetCPB_ITF_BP_HIS_iq_cpb_rx_bp_his(unsigned int uiq_cpb_rx_bp_his); +int iSetCPB_ITF_BP_HIS_iq_cpb_tx_bp_his(unsigned int uiq_cpb_tx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_stliq_req_bp_his(unsigned int ucpb_stliq_req_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_stfiq_req_bp_his(unsigned int ucpb_stfiq_req_bp_his); +int iSetCPB_ITF_BP_HIS_stlfq_cpb_ackstr_bp_his(unsigned int ustlfq_cpb_ackstr_bp_his); +int iSetCPB_ITF_BP_HIS_stffq_cpb_ackstr_bp_his(unsigned int ustffq_cpb_ackstr_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_alloc_rx_bp_his(unsigned int uprm_cpb_alloc_rx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_alloc_tx_bp_his(unsigned int uprm_cpb_alloc_tx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_dealloc_rx_bp_his(unsigned int uprm_cpb_dealloc_rx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_dealloc_tx_bp_his(unsigned int uprm_cpb_dealloc_tx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_prls_bp_his(unsigned int uprm_cpb_prls_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_oq_rx_bp_his(unsigned int ucpb_oq_rx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_oq_tx_bp_his(unsigned int ucpb_oq_tx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_oq_drp_bp_his(unsigned int ucpb_oq_drp_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_pqm_host_bp_his(unsigned int ucpb_pqm_host_bp_his); +int iSetCPB_ITF_BP_HIS_rx_prm_bp_his(unsigned int urx_prm_bp_his); +int iSetCPB_ITF_BP_HIS_tx_mag_bp_his(unsigned int utx_mag_bp_his); +int iSetCPB_ITF_BP_HIS_rx_crdt_bp_his(unsigned int urx_crdt_bp_his); +int iSetCPB_ITF_BP_HIS_tx_crdt_bp_his(unsigned int utx_crdt_bp_his); +int iSetCPB_API_ERR_cpb_api_err(unsigned int ucpb_api_err); +int iSetCPB_FIFO_ERR_COL_stf_fifo_uf_col(unsigned int ustf_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_stl_fifo_uf_col(unsigned int ustl_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cpt_fifo_uf_col(unsigned int ucpt_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cpr_fifo_uf_col(unsigned int ucpr_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cit_fifo_uf_col(unsigned int ucit_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cir_fifo_uf_col(unsigned int ucir_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_rx_fifo_uf(unsigned int uct_ext_dealc_rx_fifo_uf); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_tx_fifo_uf(unsigned int uct_ext_dealc_tx_fifo_uf); +int iSetCPB_FIFO_ERR_COL_ciq_fifo_uf_col(unsigned int uciq_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_coq_fifo_uf_col(unsigned int ucoq_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_crx_fifo_uf_col(unsigned int ucrx_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_ctx_fifo_uf_col(unsigned int uctx_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cdt_fifo_uf_col(unsigned int ucdt_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_stf_fifo_ov_col(unsigned int ustf_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_stl_fifo_ov_col(unsigned int ustl_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cpt_fifo_ov_col(unsigned int ucpt_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cpr_fifo_ov_col(unsigned int ucpr_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cit_fifo_ov_col(unsigned int ucit_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cir_fifo_ov_col(unsigned int ucir_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_rx_fifo_ov(unsigned int uct_ext_dealc_rx_fifo_ov); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_tx_fifo_ov(unsigned int uct_ext_dealc_tx_fifo_ov); +int iSetCPB_FIFO_ERR_COL_ciq_fifo_of_col(unsigned int uciq_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_coq_fifo_of_col(unsigned int ucoq_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_crx_fifo_of_col(unsigned int ucrx_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_ctx_fifo_of_col(unsigned int uctx_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_cdt_fifo_of_col(unsigned int ucdt_fifo_of_col); +int iSetTL_REQ_INVLD_stl_iq_push_len_err(unsigned int ustl_iq_push_len_err); +int iSetTL_REQ_INVLD_stf_iq_push_len_err(unsigned int ustf_iq_push_len_err); +int iSetTL_REQ_INVLD_stl_cmd_crc_len_err(unsigned int ustl_cmd_crc_len_err); +int iSetTL_REQ_INVLD_stf_cmd_crc_len_err(unsigned int ustf_cmd_crc_len_err); +int iSetTL_REQ_INVLD_stl_cmd_rd_link_err(unsigned int ustl_cmd_rd_link_err); +int iSetTL_REQ_INVLD_stf_cmd_rd_link_err(unsigned int ustf_cmd_rd_link_err); +int iSetTL_REQ_INVLD_stf_psh_len_lt_tp_lho(unsigned int ustf_psh_len_lt_tp_lho); +int iSetTL_STR_ERR_0_stl_str_pe_cmd_len_err(unsigned int ustl_str_pe_cmd_len_err); +int iSetTL_STR_ERR_0_stf_str_pe_cmd_len_err(unsigned int ustf_str_pe_cmd_len_err); +int iSetTL_STR_ERR_0_stl_str_cm_len_err(unsigned int ustl_str_cm_len_err); +int iSetTL_STR_ERR_0_stf_str_cm_len_err(unsigned int ustf_str_cm_len_err); +int iSetTL_STR_ERR_0_stl_str_ext_len_err(unsigned int ustl_str_ext_len_err); +int iSetTL_STR_ERR_0_stf_str_ext_len_err(unsigned int ustf_str_ext_len_err); +int iSetTL_STR_ERR_0_stl_str_ov_len_err(unsigned int ustl_str_ov_len_err); +int iSetTL_STR_ERR_0_stf_str_ov_len_err(unsigned int ustf_str_ov_len_err); +int iSetTL_STR_ERR_1_stl_str_mio_len_err(unsigned int ustl_str_mio_len_err); +int iSetTL_STR_ERR_1_stf_str_mio_len_err(unsigned int ustf_str_mio_len_err); +int iSetTL_STR_ERR_1_stl_str_pld_len_err(unsigned int ustl_str_pld_len_err); +int iSetTL_STR_ERR_1_stf_str_pld_len_err(unsigned int ustf_str_pld_len_err); +int iSetTL_STR_ERR_1_stl_str_ext_omd_len_err(unsigned int ustl_str_ext_omd_len_err); +int iSetTL_STR_ERR_1_stf_str_ext_omd_len_err(unsigned int ustf_str_ext_omd_len_err); +int iSetTL_STR_ERR_1_stl_str_mc_cmd_num_err(unsigned int ustl_str_mc_cmd_num_err); +int iSetTL_STR_ERR_1_stf_str_mc_cmd_num_err(unsigned int ustf_str_mc_cmd_num_err); +int iSetTL_STR_ERR_2_stl_str_cmd_len_err(unsigned int ustl_str_cmd_len_err); +int iSetTL_STR_ERR_2_stf_str_cmd_len_err(unsigned int ustf_str_cmd_len_err); +int iSetTL_STR_ERR_2_stl_str_para_cmd_cnum_err(unsigned int ustl_str_para_cmd_cnum_err); +int iSetTL_STR_ERR_2_stf_str_para_cmd_cnum_err(unsigned int ustf_str_para_cmd_cnum_err); +int iSetCPB_RAM_CTRL_BUS_0_cpb_ram_ctrl_bus_0(unsigned int ucpb_ram_ctrl_bus_0); +int iSetCPB_RAM_CTRL_BUS_1_cpb_ram_ctrl_bus_1(unsigned int ucpb_ram_ctrl_bus_1); +int iSetCPB_RAM_CTRL_BUS_2_cpb_ram_ctrl_bus_2(unsigned int ucpb_ram_ctrl_bus_2); +int iSetCPB_RAM_CTRL_BUS_3_cpb_ram_ctrl_bus_3(unsigned int ucpb_ram_ctrl_bus_3); +int iSetCPB_RAM_CTRL_BUS_4_cpb_ram_ctrl_bus_4(unsigned int ucpb_ram_ctrl_bus_4); +int iSetCPB_RAM_ECC_BYPASS_cpb_ram_ecc_bypass(unsigned int ucpb_ram_ecc_bypass); +int iSetCPB_INDIR_CTRL_cpb_indir_addr(unsigned int ucpb_indir_addr); +int iSetCPB_INDIR_CTRL_cpb_indir_tab(unsigned int ucpb_indir_tab); +int iSetCPB_INDIR_CTRL_cpb_indir_state(unsigned int ucpb_indir_state); +int iSetCPB_INDIR_CTRL_cpb_indir_mode(unsigned int ucpb_indir_mode); +int iSetCPB_INDIR_CTRL_cpb_indir_vld(unsigned int ucpb_indir_vld); +int iSetCPB_INDIR_TO_TH_cpb_indir_to_th(unsigned int ucpb_indir_to_th); +int iSetBANK_WEAK_CFG_bk_weak_en(unsigned int ubk_weak_en); +int iSetBANK_WEAK_CFG_weak_diff_th(unsigned int uweak_diff_th); +int iSetBANK_WEAK_CFG_weak_low_th(unsigned int uweak_low_th); +int iSetBMU_ALT_BP_CFG_bmu_alt_bp_on_th(unsigned int ubmu_alt_bp_on_th); +int iSetBMU_ALT_BP_CFG_bmu_alt_bp_off_th(unsigned int ubmu_alt_bp_off_th); +int iSetBMU_FAT_BP_CFG_bmu_fatal_bp_on_th(unsigned int ubmu_fatal_bp_on_th); +int iSetBMU_FAT_BP_CFG_bmu_fatal_bp_off_th(unsigned int ubmu_fatal_bp_off_th); +int iSetBMU_FAT_BP_CFG_ct_fatal_bp_en(unsigned int uct_fatal_bp_en); +int iSetBMU_AP_ACC_WT0_ap_acc_wt0(unsigned int uap_acc_wt0); +int iSetBMU_AP_ACC_WT0_ap_acc_wt1(unsigned int uap_acc_wt1); +int iSetBMU_AP_ACC_WT0_ap_acc_wt2(unsigned int uap_acc_wt2); +int iSetBMU_AP_ACC_WT0_ap_acc_wt3(unsigned int uap_acc_wt3); +int iSetBMU_AP_ACC_WT0_ap_acc_wt4(unsigned int uap_acc_wt4); +int iSetBMU_AP_ACC_WT0_ap_acc_wt5(unsigned int uap_acc_wt5); +int iSetBMU_AP_ACC_WT0_ap_acc_wt6(unsigned int uap_acc_wt6); +int iSetBMU_AP_ACC_WT0_ap_acc_wt7(unsigned int uap_acc_wt7); +int iSetBMU_AP_ACC_WT1_ap_acc_wt8(unsigned int uap_acc_wt8); +int iSetBMU_AP_ACC_WT1_ap_acc_wt9(unsigned int uap_acc_wt9); +int iSetBMU_AP_ACC_WT1_ap_acc_wt10(unsigned int uap_acc_wt10); +int iSetBMU_AP_ACC_WT1_ap_acc_wt11(unsigned int uap_acc_wt11); +int iSetBMU_AP_ACC_WT1_ap_acc_wt12(unsigned int uap_acc_wt12); +int iSetBMU_AP_ACC_WT1_ap_acc_wt13(unsigned int uap_acc_wt13); +int iSetBMU_AP_ACC_WT1_ap_acc_wt14(unsigned int uap_acc_wt14); +int iSetTI_ACC_TO_TH_ti_nm_rreq_to_th0(unsigned int uti_nm_rreq_to_th0); +int iSetTI_ACC_TO_TH_ti_nm_rreq_to_th1(unsigned int uti_nm_rreq_to_th1); +int iSetTI_ACC_TO_TH_ti_nm_rreq_to_th2(unsigned int uti_nm_rreq_to_th2); +int iSetBMP_AM_TH_bmp_aempty_th(unsigned int ubmp_aempty_th); +int iSetBK_EXHT_TH_bk_exht_th(unsigned int ubk_exht_th); +int iSetCELL_RD_RLS_EN_cell_rd_rls_en(unsigned int ucell_rd_rls_en); +int iSetCPB_AGE_CFG_cpb_timer_unit_th(unsigned int ucpb_timer_unit_th); +int iSetCPB_AGE_CFG_age_auto_rls_en(unsigned int uage_auto_rls_en); +int iSetCPB_AGE_CFG_cpb_age_en(unsigned int ucpb_age_en); +int iSetCPB_AGE_TO_TH_cpb_age_to_th(unsigned int ucpb_age_to_th); +int iSetBK_AGE_CFG_bk_age_bmp_addr(unsigned int ubk_age_bmp_addr); +int iSetBK_AGE_CFG_bk_age_addr_found(unsigned int ubk_age_addr_found); +int iSetBK_AGE_CFG_bk_cur_age_st(unsigned int ubk_cur_age_st); +int iSetBK_AGE_CFG_bk_age_scan_busy(unsigned int ubk_age_scan_busy); +int iSetBK_AGE_CFG_bk_age_scan_req(unsigned int ubk_age_scan_req); +int iSetBK_AGE_BMP_LINE_bk_age_bmp_line(unsigned int ubk_age_bmp_line); +int iSetBK_AGE_RLS_CFG_bk_age_rls_addr(unsigned int ubk_age_rls_addr); +int iSetBK_AGE_RLS_CFG_bk_age_rls_req(unsigned int ubk_age_rls_req); +int iSetBK_AGE_FIND_NXT_bk_age_find_nxt(unsigned int ubk_age_find_nxt); +int iSetBK_FREE_RSC_CNT0_bk0_free_rsc_cnt(unsigned int ubk0_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT0_bk1_free_rsc_cnt(unsigned int ubk1_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT1_bk2_free_rsc_cnt(unsigned int ubk2_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT1_bk3_free_rsc_cnt(unsigned int ubk3_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT2_bk4_free_rsc_cnt(unsigned int ubk4_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT2_bk5_free_rsc_cnt(unsigned int ubk5_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT3_bk6_free_rsc_cnt(unsigned int ubk6_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT3_bk7_free_rsc_cnt(unsigned int ubk7_free_rsc_cnt); +int iSetBK_MIN_RSC_HIS_CNT0_bk0_min_rsc_his_cnt(unsigned int ubk0_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT0_bk1_min_rsc_his_cnt(unsigned int ubk1_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT1_bk2_min_rsc_his_cnt(unsigned int ubk2_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT1_bk3_min_rsc_his_cnt(unsigned int ubk3_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT2_bk4_min_rsc_his_cnt(unsigned int ubk4_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT2_bk5_min_rsc_his_cnt(unsigned int ubk5_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT3_bk6_min_rsc_his_cnt(unsigned int ubk6_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT3_bk7_min_rsc_his_cnt(unsigned int ubk7_min_rsc_his_cnt); +int iSetCPB_MIN_RSC_HIS_CNT_cpb_min_rsc_his_cnt(unsigned int ucpb_min_rsc_his_cnt); +int iSetBMU_RSC_HIS_CNT_CLR_bk_min_rsc_his_cnt_clr(unsigned int ubk_min_rsc_his_cnt_clr); +int iSetBMU_RSC_HIS_CNT_CLR_cpb_min_rsc_his_cnt_clr(unsigned int ucpb_min_rsc_his_cnt_clr); +int iSetBMU_BP_STA_bmu_alt_bp(unsigned int ubmu_alt_bp); +int iSetBMU_BP_STA_bmu_fatal_bp(unsigned int ubmu_fatal_bp); +int iSetBMU_BP_STA_bk_weak_bp(unsigned int ubk_weak_bp); +int iSetBMU_BP_STA_bmu_alt_bp_his(unsigned int ubmu_alt_bp_his); +int iSetBMU_BP_STA_bmu_fatal_bp_his(unsigned int ubmu_fatal_bp_his); +int iSetBMU_BP_STA_bk_weak_bp_his(unsigned int ubk_weak_bp_his); +int iSetROW_BMP_STA_row_bmp_free_rsc_cnt(unsigned int urow_bmp_free_rsc_cnt); +int iSetROW_BMP_STA_row_bmp_aempty(unsigned int urow_bmp_aempty); +int iSetROW_BMP_STA_row_bmp_empty(unsigned int urow_bmp_empty); +int iSetROW_BMP_STA_row_bmp_aempty_his(unsigned int urow_bmp_aempty_his); +int iSetROW_BMP_STA_row_bmp_empty_his(unsigned int urow_bmp_empty_his); +int iSetROW_BMP_STA_row_bmp_refrain_err_his(unsigned int urow_bmp_refrain_err_his); +int iSetROW_BMP_STA_row_bmp_leak_err_his(unsigned int urow_bmp_leak_err_his); +int iSetAGE_RLS_CNT_0_bk_age_rls_cnt0(unsigned int ubk_age_rls_cnt0); +int iSetAGE_RLS_CNT_0_bk_age_rls_cnt1(unsigned int ubk_age_rls_cnt1); +int iSetAGE_RLS_CNT_1_bk_age_rls_cnt2(unsigned int ubk_age_rls_cnt2); +int iSetAGE_RLS_CNT_1_bk_age_rls_cnt3(unsigned int ubk_age_rls_cnt3); +int iSetAGE_RLS_CNT_2_bk_age_rls_cnt4(unsigned int ubk_age_rls_cnt4); +int iSetAGE_RLS_CNT_2_bk_age_rls_cnt5(unsigned int ubk_age_rls_cnt5); +int iSetAGE_RLS_CNT_3_bk_age_rls_cnt6(unsigned int ubk_age_rls_cnt6); +int iSetAGE_RLS_CNT_3_bk_age_rls_cnt7(unsigned int ubk_age_rls_cnt7); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_npt_fifo_crdt(unsigned int ustf_rsp_npt_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_dat_fifo_crdt(unsigned int ustf_rsp_dat_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_api_hdr_fifo_crdt(unsigned int ustf_rsp_api_hdr_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_crc_fifo_crdt(unsigned int ustf_rsp_crc_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_api_fifo_crdt_init(unsigned int ustf_rsp_api_fifo_crdt_init); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_str_rsp_hdr_crdt(unsigned int ustf_str_rsp_hdr_crdt); +int iSetSTF_PSH_CMD_WT_stf_cmd_req_wt(unsigned int ustf_cmd_req_wt); +int iSetSTF_PSH_CMD_WT_stf_psh_req_wt(unsigned int ustf_psh_req_wt); +int iSetSTF_COL_DEL_MD_HDR_EN_stf_col_del_md_hdr_en(unsigned int ustf_col_del_md_hdr_en); +int iSetSTF_RD_REQ_FIFO_AF_TH_stf_rd_req_fifo_af_th(unsigned int ustf_rd_req_fifo_af_th); +int iSetSTF_RD_CTRL_FIFO_AF_TH_stf_rd_ctrl_fifo_af_th(unsigned int ustf_rd_ctrl_fifo_af_th); +int iSetCPB_STF_API_CRDT_INIT_cpb_stf_api_crdt(unsigned int ucpb_stf_api_crdt); +int iSetCPB_STF_API_CRDT_INIT_cpb_stf_api_crdt_init(unsigned int ucpb_stf_api_crdt_init); +int iSetSTF_STR_DI_FIFO_AF_TH_stf_str_di_fifo_af_th(unsigned int ustf_str_di_fifo_af_th); +int iSetSTF_STR_API_FIFO_AF_TH_stf_str_api_fifo_af_th(unsigned int ustf_str_api_fifo_af_th); +int iSetSTF_CMD_API_FIFO_AF_TH_stf_cmd_api_fifo_af_th(unsigned int ustf_cmd_api_fifo_af_th); +int iSetSTF_ACKSTR_FIFO_AF_TH_stf_ackstr_fifo_af_th(unsigned int ustf_ackstr_fifo_af_th); +int iSetSTF_MSG_VFID_CTL_fake_vfid_start_bit(unsigned int ufake_vfid_start_bit); +int iSetSTF_MSG_VFID_CTL_fake_vfid_end_bit(unsigned int ufake_vfid_end_bit); +int iSetCT_DMA_NRET_CFG_dma_nret_psh2pptr_en(unsigned int udma_nret_psh2pptr_en); +int iSetCT_DMA_NRET_CFG_dma_nret_psh2pptr_fix(unsigned int udma_nret_psh2pptr_fix); +int iSetCT_DMA_NRET_CFG_psh_pptr_cmd_len(unsigned int upsh_pptr_cmd_len); +int iSetCT_COL_SRC_TAG_H_CFG_osd_id_i(unsigned int uosd_id_i); +int iSetCT_COL_SRC_TAG_H_CFG_osd_id_l(unsigned int uosd_id_l); +int iSetCT_COL_SRC_TAG_H_CFG_osd_id_m(unsigned int uosd_id_m); +int iSetCT_DEALC_FIFO_AF_TH_ct_dealc_fifo_af_th(unsigned int uct_dealc_fifo_af_th); +int iSetSTFIQ_PSH_FIFO_CFG_stfpsh_fifo_ae_th(unsigned int ustfpsh_fifo_ae_th); +int iSetSTFIQ_PSH_FIFO_CFG_stfpsh_fifo_af_th(unsigned int ustfpsh_fifo_af_th); +int iSetSTFIQ_LINK_FIFO_CFG_link_fifo_ae_th(unsigned int ulink_fifo_ae_th); +int iSetSTFIQ_LINK_FIFO_CFG_link_fifo_af_th(unsigned int ulink_fifo_af_th); +int iSetLINK_WR_FIFO_CFG_linkwr_fifo_ae_th(unsigned int ulinkwr_fifo_ae_th); +int iSetLINK_WR_FIFO_CFG_linkwr_fifo_af_th(unsigned int ulinkwr_fifo_af_th); +int iSetSTF_CMD_API_RD_REQ_FIFO_STA_stf_cmd_api_fifo_sta(unsigned int ustf_cmd_api_fifo_sta); +int iSetSTF_CMD_API_RD_REQ_FIFO_STA_stf_rd_req_fifo_sta(unsigned int ustf_rd_req_fifo_sta); +int iSetSTF_STR_API_FIFO_STA_stf_str_api_fifo_sta(unsigned int ustf_str_api_fifo_sta); +int iSetSTF_WR_RD_DAT_IN_FIFO_STA_stf_wr_di_fifo_sta(unsigned int ustf_wr_di_fifo_sta); +int iSetSTF_WR_RD_DAT_IN_FIFO_STA_stf_rd_di_fifo_sta(unsigned int ustf_rd_di_fifo_sta); +int iSetSTF_RSP_API_HDR_DAT_FIFO_STA_stf_rsp_api_dat_fifo_sta(unsigned int ustf_rsp_api_dat_fifo_sta); +int iSetSTF_RSP_API_HDR_DAT_FIFO_STA_stf_rsp_api_hdr_fifo_sta(unsigned int ustf_rsp_api_hdr_fifo_sta); +int iSetSTF_RSP_API_CD_CRC_FIFO_STA_stf_rsp_api_crc_fifo_sta(unsigned int ustf_rsp_api_crc_fifo_sta); +int iSetSTF_RSP_API_CD_CRC_FIFO_STA_stf_rsp_api_cd_fifo_sta(unsigned int ustf_rsp_api_cd_fifo_sta); +int iSetSTF_RSP_API_CS_NPTR_FIFO_STA_stf_rsp_api_nptr_fifo_sta(unsigned int ustf_rsp_api_nptr_fifo_sta); +int iSetSTF_RSP_API_CS_NPTR_FIFO_STA_stf_rsp_api_cs_fifo_sta(unsigned int ustf_rsp_api_cs_fifo_sta); +int iSetSTF_STR_CMD_CNT_stf_cmd_cnt(unsigned int ustf_cmd_cnt); +int iSetSTF_STR_CMD_CNT_stf_str_cnt(unsigned int ustf_str_cnt); +int iSetSTF_ACK_RSP_CNT_stf_rsp_cnt(unsigned int ustf_rsp_cnt); +int iSetSTF_ACK_RSP_CNT_stf_ack_cnt(unsigned int ustf_ack_cnt); +int iSetSTF_PSH_CNT_stf_psh_tl_cnt(unsigned int ustf_psh_tl_cnt); +int iSetSTF_PSH_CNT_stf_iq_psh_cnt(unsigned int ustf_iq_psh_cnt); +int iSetSTF_CELL_MDF_CNT_stf_cell_mdf_cnt(unsigned int ustf_cell_mdf_cnt); +int iSetSTF_CELL_MDF_CNT_stf_iq_psh_rm_scol_cnt(unsigned int ustf_iq_psh_rm_scol_cnt); +int iSetSTF_WR_DI_CTRL_FIFO_STA_stf_wr_di_ctrl_fifo_sta(unsigned int ustf_wr_di_ctrl_fifo_sta); +int iSetSTF_WR_DI_CTRL_FIFO_STA_stf_ackstr_fifo_sta(unsigned int ustf_ackstr_fifo_sta); +int iSetSTF_FIFO_OV_ERR_0_stf_rd_req_fifo_ov(unsigned int ustf_rd_req_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_cmd_api_fifo_ov(unsigned int ustf_cmd_api_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_str_api_fifo_ov(unsigned int ustf_str_api_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_rd_di_fifo_ov(unsigned int ustf_rd_di_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_wr_di_fifo_ov(unsigned int ustf_wr_di_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_wr_di_ctrl_fifo_ov(unsigned int ustf_wr_di_ctrl_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_ackstr_fifo_ov(unsigned int ustf_ackstr_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_hdr_fifo_ov(unsigned int ustf_rsp_api_hdr_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_dat_fifo_ov(unsigned int ustf_rsp_api_dat_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_cd_fifo_ov(unsigned int ustf_rsp_api_cd_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_crc_fifo_ov(unsigned int ustf_rsp_api_crc_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_cs_fifo_ov(unsigned int ustf_rsp_api_cs_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_nptr_fifo_ov(unsigned int ustf_rsp_api_nptr_fifo_ov); +int iSetSTF_FIFO_UF_ERR_0_stf_rd_req_fifo_uf(unsigned int ustf_rd_req_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_cmd_api_fifo_uf(unsigned int ustf_cmd_api_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_str_api_fifo_uf(unsigned int ustf_str_api_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_rd_di_fifo_uf(unsigned int ustf_rd_di_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_wr_di_fifo_uf(unsigned int ustf_wr_di_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_wr_di_ctrl_fifo_uf(unsigned int ustf_wr_di_ctrl_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_ackstr_fifo_uf(unsigned int ustf_ackstr_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_hdr_fifo_uf(unsigned int ustf_rsp_api_hdr_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_dat_fifo_uf(unsigned int ustf_rsp_api_dat_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_cd_fifo_uf(unsigned int ustf_rsp_api_cd_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_crc_fifo_uf(unsigned int ustf_rsp_api_crc_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_cs_fifo_uf(unsigned int ustf_rsp_api_cs_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_nptr_fifo_uf(unsigned int ustf_rsp_api_nptr_fifo_uf); +int iSetCT_EXT_DEALC_FIFO_STA_ct_ext_dealc_rx_fifo_sta(unsigned int uct_ext_dealc_rx_fifo_sta); +int iSetCT_EXT_DEALC_FIFO_STA_ct_ext_dealc_tx_fifo_sta(unsigned int uct_ext_dealc_tx_fifo_sta); +int iSetSTF_PCOL_NUM_ERR_stf_pcol_num_err(unsigned int ustf_pcol_num_err); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_addr(unsigned int ustfwr_fifo_mem_err_addr); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_cerr(unsigned int ustfwr_fifo_mem_err_cerr); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_ucerr(unsigned int ustfwr_fifo_mem_err_ucerr); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_cnt(unsigned int ustfwr_fifo_mem_err_cnt); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_addr(unsigned int ustfstr_fifo_mem_err_addr); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_cerr(unsigned int ustfstr_fifo_mem_err_cerr); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_ucerr(unsigned int ustfstr_fifo_mem_err_ucerr); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_cnt(unsigned int ustfstr_fifo_mem_err_cnt); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_addr(unsigned int ustfrsp_fifo_mem_err_addr); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_cerr(unsigned int ustfrsp_fifo_mem_err_cerr); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_ucerr(unsigned int ustfrsp_fifo_mem_err_ucerr); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_cnt(unsigned int ustfrsp_fifo_mem_err_cnt); +int iSetSTFIQ_PKT_PSH_CNT_stfiq_pkt_psh_cnt(unsigned int ustfiq_pkt_psh_cnt); +int iSetSTFIQ_MSG_PSH_CNT_stfiq_msg_psh_cnt(unsigned int ustfiq_msg_psh_cnt); +int iSetSTFIQ_COL_PSH_CNT_stfiq_col_psh_cnt(unsigned int ustfiq_col_psh_cnt); +int iSetSTFIQ_LINK_REQ_CNT_stfiq_link_req_cnt(unsigned int ustfiq_link_req_cnt); +int iSetSTFIQ_PSH_FIFO_STA_stfiq_psh_fifo_sta(unsigned int ustfiq_psh_fifo_sta); +int iSetSTFIQ_LINK_FIFO_STA_stfiq_link_fifo_sta(unsigned int ustfiq_link_fifo_sta); +int iSetLINK_WR_FIFO_STA_link_wr_fifo_sta(unsigned int ulink_wr_fifo_sta); +int iSetCIQ_FIFO_OF_ERR_stliq_psh_fifo_of_err(unsigned int ustliq_psh_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_stfiq_psh_fifo_of_err(unsigned int ustfiq_psh_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_stfiq_link_fifo_of_err(unsigned int ustfiq_link_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_link_wr_fifo_of_err(unsigned int ulink_wr_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_rob_psh_fifo_of_err(unsigned int urob_psh_fifo_of_err); +int iSetCIQ_FIFO_UF_ERR_stliq_psh_fifo_uf_err(unsigned int ustliq_psh_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_stfiq_psh_fifo_uf_err(unsigned int ustfiq_psh_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_stfiq_link_fifo_uf_err(unsigned int ustfiq_link_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_link_wr_fifo_uf_err(unsigned int ulink_wr_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_rob_psh_fifo_uf_err(unsigned int urob_psh_fifo_uf_err); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_err_addr(unsigned int ustfiq_psh_fifo_mem_err_addr); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_cerr(unsigned int ustfiq_psh_fifo_mem_cerr); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_ucerr(unsigned int ustfiq_psh_fifo_mem_ucerr); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_err_cnt(unsigned int ustfiq_psh_fifo_mem_err_cnt); +int iSetCIQ_ERR_stfiq_col_psh_err(unsigned int ustfiq_col_psh_err); +int iSetDAT_RAM_ERR_dat_mem_err_addr(unsigned int udat_mem_err_addr); +int iSetDAT_RAM_ERR_dat_mem_err_cerr(unsigned int udat_mem_err_cerr); +int iSetDAT_RAM_ERR_dat_mem_err_ucerr(unsigned int udat_mem_err_ucerr); +int iSetDAT_RAM_ERR_dat_mem_err_cnt(unsigned int udat_mem_err_cnt); +int iSetCD_RAM_ERR_cd_mem_err_addr(unsigned int ucd_mem_err_addr); +int iSetCD_RAM_ERR_cd_mem_err_cerr(unsigned int ucd_mem_err_cerr); +int iSetCD_RAM_ERR_cd_mem_err_ucerr(unsigned int ucd_mem_err_ucerr); +int iSetCD_RAM_ERR_cd_mem_err_cnt(unsigned int ucd_mem_err_cnt); +int iSetNPTR_RAM_ERR_nptr_mem_err_addr(unsigned int unptr_mem_err_addr); +int iSetNPTR_RAM_ERR_nptr_mem_err_cerr(unsigned int unptr_mem_err_cerr); +int iSetNPTR_RAM_ERR_nptr_mem_err_ucerr(unsigned int unptr_mem_err_ucerr); +int iSetNPTR_RAM_ERR_nptr_mem_err_cnt(unsigned int unptr_mem_err_cnt); +int iSetTI_RAM_ERR_ti_mem_err_addr(unsigned int uti_mem_err_addr); +int iSetTI_RAM_ERR_ti_mem_err_cerr(unsigned int uti_mem_err_cerr); +int iSetTI_RAM_ERR_ti_mem_err_ucerr(unsigned int uti_mem_err_ucerr); +int iSetTI_RAM_ERR_ti_mem_err_cnt(unsigned int uti_mem_err_cnt); +int iSetBMP_RAM_ERR_bmp_mem_err_addr(unsigned int ubmp_mem_err_addr); +int iSetBMP_RAM_ERR_bmp_mem_err_cerr(unsigned int ubmp_mem_err_cerr); +int iSetBMP_RAM_ERR_bmp_mem_err_ucerr(unsigned int ubmp_mem_err_ucerr); +int iSetBMP_RAM_ERR_bmp_mem_err_cnt(unsigned int ubmp_mem_err_cnt); +int iSetAGE_RAM_ERR_age_mem_err_addr(unsigned int uage_mem_err_addr); +int iSetAGE_RAM_ERR_age_mem_err_cerr(unsigned int uage_mem_err_cerr); +int iSetAGE_RAM_ERR_age_mem_err_ucerr(unsigned int uage_mem_err_ucerr); +int iSetAGE_RAM_ERR_age_mem_err_cnt(unsigned int uage_mem_err_cnt); + +/* Define the union csr_cit_data_in_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_data_in_fifo_af_th : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_data_in_fifo_af_th_u; + +/* Define the union csr_cit_dealc_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_dealc_fifo_af_th : 5; /* [4:0] */ + u32 rsv_1 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_dealc_fifo_af_th_u; + +/* Define the union csr_cit_ec_ch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_ec_ch0 : 5; /* [4:0] */ + u32 rsv_2 : 2; /* [6:5] */ + u32 cit_ec_ch0_vld : 1; /* [7] */ + u32 cit_ec_ch1 : 5; /* [12:8] */ + u32 rsv_3 : 2; /* [14:13] */ + u32 cit_ec_ch1_vld : 1; /* [15] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_ec_ch_u; + +/* Define the union csr_cpr_pro_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_wt_0 : 4; /* [3:0] */ + u32 cpr_pro_wt_1 : 4; /* [7:4] */ + u32 cpr_pro_wt_2 : 4; /* [11:8] */ + u32 cpr_pro_wt_3 : 4; /* [15:12] */ + u32 cpr_pro_wt_4 : 4; /* [19:16] */ + u32 rsv_5 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_wt_u; + +/* Define the union csr_cpr_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_fifo_crdt_init_dat : 6; /* [5:0] */ + u32 rsv_6 : 2; /* [7:6] */ + u32 cpr_fifo_crdt_init : 1; /* [8] */ + u32 rsv_7 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_crdt_init_u; + +/* Define the union csr_cpr_dealc_tx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dealc_tx_af_th : 7; /* [6:0] */ + u32 rsv_8 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dealc_tx_af_th_u; + +/* Define the union csr_cpr_dealc_rx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dealc_rx_af_th : 7; /* [6:0] */ + u32 rsv_9 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dealc_rx_af_th_u; + +/* Define the union csr_cpr_prls_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_prls_af_th : 7; /* [6:0] */ + u32 rsv_10 : 1; /* [7] */ + u32 cpr_pro_prls_fifo_af_th : 5; /* [12:8] */ + u32 rsv_11 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_prls_af_th_u; + +/* Define the union csr_cpr_col_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_deast_col_th : 7; /* [6:0] */ + u32 rsv_12 : 1; /* [7] */ + u32 cpr_ast_col_th : 7; /* [14:8] */ + u32 rsv_13 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_col_th_u; + +/* Define the union csr_cpr_pro_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_di_fifo_af_th : 5; /* [4:0] */ + u32 rsv_14 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_di_fifo_af_th_u; + +/* Define the union csr_cpr_pro_dealc_tx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_tx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_15 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_tx_fifo_af_th_u; + +/* Define the union csr_cpr_pro_dealc_rx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_rx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_16 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_rx_fifo_af_th_u; + +/* Define the union csr_cpr_pro_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dat_fifo_crdt_init_dat : 5; /* [4:0] */ + u32 rsv_17 : 3; /* [7:5] */ + u32 cpr_pro_dat_fifo_crdt_init : 1; /* [8] */ + u32 rsv_18 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_fifo_crdt_init_u; + +/* Define the union csr_cpr_pro_dealc_rp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_rp_th : 7; /* [6:0] */ + u32 rsv_19 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_rp_th_u; + +/* Define the union csr_cpr_pro_rrdy_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_rrdy_fifo_af_th : 4; /* [3:0] */ + u32 rsv_20 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_rrdy_fifo_af_th_u; + +/* Define the union csr_cpr_out_err_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_perx_err_en : 1; /* [0] */ + u32 cpb_perx_ftso_err_en : 1; /* [1] */ + u32 rsv_21 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_err_en_u; + +/* Define the union csr_cit_dat_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_22 : 5; /* [15:11] */ + u32 cit_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_23 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_dat_fifo_sta_u; + +/* Define the union csr_cit_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_dealc_fifo_sta : 11; /* [10:0] */ + u32 rsv_24 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_dealc_fifo_sta_u; + +/* Define the union csr_cit_in_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_in_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_in_pkt_sop_cnt_u; + +/* Define the union csr_cit_in_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_in_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_in_pkt_eop_cnt_u; + +/* Define the union csr_cit_in_chnl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_in_chnl_pkt_cnt : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_in_chnl_pkt_cnt_u; + +/* Define the union csr_cit_rpt_iq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_rpt_iq_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_rpt_iq_cnt_u; + +/* Define the union csr_cit_iq_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_iq_bp_cnt : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_iq_bp_cnt_u; + +/* Define the union csr_cit_pal_less_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_pal_less_num : 16; /* [15:0] */ + u32 cit_pal_less_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_pal_less_sta_u; + +/* Define the union csr_cit_pal_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_pal_err : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_pal_err_u; + +/* Define the union csr_cit_schnl_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_schnl_err : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_schnl_err_u; + +/* Define the union csr_cit_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_di_fifo_uf : 1; /* [0] */ + u32 cit_di_ctrl_fifo_uf : 1; /* [1] */ + u32 cit_dealc_fifo_uf : 1; /* [2] */ + u32 rsv_32 : 13; /* [15:3] */ + u32 cit_di_fifo_ov : 1; /* [16] */ + u32 cit_di_ctrl_fifo_ov : 1; /* [17] */ + u32 cit_dealc_fifo_ov : 1; /* [18] */ + u32 rsv_33 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_fifo_err_u; + +/* Define the union csr_cit_ec_illegal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_ec_illegal : 1; /* [0] */ + u32 rsv_34 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_ec_illegal_u; + +/* Define the union csr_cit_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_35 : 7; /* [11:5] */ + u32 cit_fifo_mem_err_cerr : 1; /* [12] */ + u32 cit_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_36 : 2; /* [15:14] */ + u32 cit_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_fifo_ram_err_u; + +/* Define the union csr_cpr_pro_dat_in_rrdy_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_rrdy_fifo_sta : 11; /* [10:0] */ + u32 cpr_pro_di_fifo_sta : 11; /* [21:11] */ + u32 cpr_pro_prls_fifo_sta : 9; /* [30:22] */ + u32 rsv_37 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dat_in_rrdy_fifo_sta_u; + +/* Define the union csr_cpr_pro_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_38 : 5; /* [15:11] */ + u32 cpr_pro_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_39 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_fifo_sta_u; + +/* Define the union csr_cpr_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_40 : 5; /* [15:11] */ + u32 cpr_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_41 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dealc_fifo_sta_u; + +/* Define the union csr_cpr_dat_out_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dat_out_fifo_sta : 11; /* [10:0] */ + u32 rsv_42 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dat_out_fifo_sta_u; + +/* Define the union csr_cpr_prls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_prls_fifo_sta : 11; /* [10:0] */ + u32 rsv_43 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_prls_fifo_sta_u; + +/* Define the union csr_cpr_out_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_out_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_pkt_sop_cnt_u; + +/* Define the union csr_cpr_out_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_out_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_45 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_pkt_eop_cnt_u; + +/* Define the union csr_cpr_rrdy_side_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_rrdy_side_err : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_rrdy_side_err_u; + +/* Define the union csr_cpr_out_chnl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_out_chnl_pkt_cnt : 16; /* [15:0] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_chnl_pkt_cnt_u; + +/* Define the union csr_cpr_sof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_sof_msm_info : 28; /* [27:0] */ + u32 rsv_48 : 3; /* [30:28] */ + u32 cpr_sof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sof_msm_u; + +/* Define the union csr_cpr_eof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_eof_msm_info : 28; /* [27:0] */ + u32 rsv_49 : 3; /* [30:28] */ + u32 cpr_eof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_eof_msm_u; + +/* Define the union csr_cpr_fifo_ov_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_di_fifo_ov : 5; /* [4:0] */ + u32 cpr_pro_rrdy_fifo_ov : 5; /* [9:5] */ + u32 cpr_pro_dealc_tx_fifo_ov : 5; /* [14:10] */ + u32 cpr_pro_dealc_rx_fifo_ov : 5; /* [19:15] */ + u32 cpr_pro_prls_fifo_ov : 5; /* [24:20] */ + u32 rsv_50 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_ov_err_u; + +/* Define the union csr_cpr_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dat_out_fifo_uf : 5; /* [4:0] */ + u32 rsv_51 : 3; /* [7:5] */ + u32 cpr_dealc_tx_fifo_uf : 1; /* [8] */ + u32 cpr_dealc_rx_fifo_uf : 1; /* [9] */ + u32 cpr_prls_fifo_uf : 1; /* [10] */ + u32 rsv_52 : 5; /* [15:11] */ + u32 cpr_dat_out_fifo_ov : 5; /* [20:16] */ + u32 rsv_53 : 3; /* [23:21] */ + u32 cpr_dealc_tx_fifo_ov : 1; /* [24] */ + u32 cpr_dealc_rx_fifo_ov : 1; /* [25] */ + u32 cpr_prls_fifo_ov : 1; /* [26] */ + u32 rsv_54 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_err_u; + +/* Define the union csr_cpr_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_di_fifo_uf : 5; /* [4:0] */ + u32 cpr_pro_rrdy_fifo_uf : 5; /* [9:5] */ + u32 cpr_pro_dealc_tx_fifo_uf : 5; /* [14:10] */ + u32 cpr_pro_dealc_rx_fifo_uf : 5; /* [19:15] */ + u32 cpr_pro_prls_fifo_uf : 5; /* [24:20] */ + u32 rsv_55 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_uf_err_u; + +/* Define the union csr_cpr_sge_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_zero_clr : 1; /* [0] */ + u32 rsv_56 : 3; /* [3:1] */ + u32 sge_crdt_err_pro : 2; /* [5:4] */ + u32 rsv_57 : 2; /* [7:6] */ + u32 sge_crdt_err_chnl : 5; /* [12:8] */ + u32 rsv_58 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sge_crdt_err_u; + +/* Define the union csr_cpr_sge_crdt_err_dma_hed_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_err_crdt_err_dma_hed_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sge_crdt_err_dma_hed_l_u; + +/* Define the union csr_cpr_sge_crdt_err_dma_hed_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_err_crdt_err_dma_hed_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sge_crdt_err_dma_hed_h_u; + +/* Define the union csr_cpr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_fifo_mem_err_addr : 4; /* [3:0] */ + u32 rsv_59 : 8; /* [11:4] */ + u32 cpr_fifo_mem_err_cerr : 1; /* [12] */ + u32 cpr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 cpr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_ram_err_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cit_data_in_fifo_af_th_u cit_data_in_fifo_af_th; /* 500 */ + volatile csr_cit_dealc_fifo_af_th_u cit_dealc_fifo_af_th; /* 504 */ + volatile csr_cit_ec_ch_u cit_ec_ch; /* 508 */ + volatile csr_cpr_pro_wt_u cpr_pro_wt; /* 600 */ + volatile csr_cpr_fifo_crdt_init_u cpr_fifo_crdt_init; /* 604 */ + volatile csr_cpr_dealc_tx_af_th_u cpr_dealc_tx_af_th; /* 610 */ + volatile csr_cpr_dealc_rx_af_th_u cpr_dealc_rx_af_th; /* 614 */ + volatile csr_cpr_prls_af_th_u cpr_prls_af_th; /* 618 */ + volatile csr_cpr_col_th_u cpr_col_th; /* 61C */ + volatile csr_cpr_pro_di_fifo_af_th_u cpr_pro_di_fifo_af_th; /* 630 */ + volatile csr_cpr_pro_dealc_tx_fifo_af_th_u cpr_pro_dealc_tx_fifo_af_th; /* 634 */ + volatile csr_cpr_pro_dealc_rx_fifo_af_th_u cpr_pro_dealc_rx_fifo_af_th; /* 638 */ + volatile csr_cpr_pro_fifo_crdt_init_u cpr_pro_fifo_crdt_init; /* 63C */ + volatile csr_cpr_pro_dealc_rp_th_u cpr_pro_dealc_rp_th; /* 640 */ + volatile csr_cpr_pro_rrdy_fifo_af_th_u cpr_pro_rrdy_fifo_af_th; /* 644 */ + volatile csr_cpr_out_err_en_u cpr_out_err_en; /* 648 */ + volatile csr_cit_dat_fifo_sta_u cit_dat_fifo_sta; /* 1100 */ + volatile csr_cit_dealc_fifo_sta_u cit_dealc_fifo_sta; /* 1104 */ + volatile csr_cit_in_pkt_sop_cnt_u cit_in_pkt_sop_cnt; /* 1120 */ + volatile csr_cit_in_pkt_eop_cnt_u cit_in_pkt_eop_cnt; /* 1124 */ + volatile csr_cit_in_chnl_pkt_cnt_u cit_in_chnl_pkt_cnt[24]; /* 1130 */ + volatile csr_cit_rpt_iq_cnt_u cit_rpt_iq_cnt; /* 1190 */ + volatile csr_cit_iq_bp_cnt_u cit_iq_bp_cnt; /* 1194 */ + volatile csr_cit_pal_less_sta_u cit_pal_less_sta; /* 1198 */ + volatile csr_cit_pal_err_u cit_pal_err; /* 119C */ + volatile csr_cit_schnl_err_u cit_schnl_err; /* 11A0 */ + volatile csr_cit_fifo_err_u cit_fifo_err; /* 11A4 */ + volatile csr_cit_ec_illegal_u cit_ec_illegal; /* 11A8 */ + volatile csr_cit_fifo_ram_err_u cit_fifo_ram_err; /* 11B0 */ + volatile csr_cpr_pro_dat_in_rrdy_fifo_sta_u cpr_pro_dat_in_rrdy_fifo_sta[5]; /* 1200 */ + volatile csr_cpr_pro_dealc_fifo_sta_u cpr_pro_dealc_fifo_sta[5]; /* 1214 */ + volatile csr_cpr_dealc_fifo_sta_u cpr_dealc_fifo_sta; /* 1228 */ + volatile csr_cpr_dat_out_fifo_sta_u cpr_dat_out_fifo_sta[5]; /* 122C */ + volatile csr_cpr_prls_fifo_sta_u cpr_prls_fifo_sta; /* 1240 */ + volatile csr_cpr_out_pkt_sop_cnt_u cpr_out_pkt_sop_cnt; /* 1244 */ + volatile csr_cpr_out_pkt_eop_cnt_u cpr_out_pkt_eop_cnt; /* 1248 */ + volatile csr_cpr_rrdy_side_err_u cpr_rrdy_side_err; /* 124C */ + volatile csr_cpr_out_chnl_pkt_cnt_u cpr_out_chnl_pkt_cnt[23]; /* 1250 */ + volatile csr_cpr_sof_msm_u cpr_sof_msm[5]; /* 12AC */ + volatile csr_cpr_eof_msm_u cpr_eof_msm[5]; /* 12C0 */ + volatile csr_cpr_fifo_ov_err_u cpr_fifo_ov_err; /* 12D4 */ + volatile csr_cpr_fifo_err_u cpr_fifo_err; /* 12D8 */ + volatile csr_cpr_fifo_uf_err_u cpr_fifo_uf_err; /* 12DC */ + volatile csr_cpr_sge_crdt_err_u cpr_sge_crdt_err; /* 12E0 */ + volatile csr_cpr_sge_crdt_err_dma_hed_l_u cpr_sge_crdt_err_dma_hed_l; /* 12E4 */ + volatile csr_cpr_sge_crdt_err_dma_hed_h_u cpr_sge_crdt_err_dma_hed_h; /* 12E8 */ + volatile csr_cpr_fifo_ram_err_u cpr_fifo_ram_err[5]; /* 12EC */ +} S_cpb_csr_1_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_1 */ +extern volatile S_cpb_csr_1_REGS_TYPE *gopcpb_csr_1AllReg; + +/* Declare the functions that set the member value */ +int iSetCIT_DATA_IN_FIFO_AF_TH_cit_data_in_fifo_af_th(unsigned int ucit_data_in_fifo_af_th); +int iSetCIT_DEALC_FIFO_AF_TH_cit_dealc_fifo_af_th(unsigned int ucit_dealc_fifo_af_th); +int iSetCIT_EC_CH_cit_ec_ch0(unsigned int ucit_ec_ch0); +int iSetCIT_EC_CH_cit_ec_ch0_vld(unsigned int ucit_ec_ch0_vld); +int iSetCIT_EC_CH_cit_ec_ch1(unsigned int ucit_ec_ch1); +int iSetCIT_EC_CH_cit_ec_ch1_vld(unsigned int ucit_ec_ch1_vld); +int iSetCPR_PRO_WT_cpr_pro_wt_0(unsigned int ucpr_pro_wt_0); +int iSetCPR_PRO_WT_cpr_pro_wt_1(unsigned int ucpr_pro_wt_1); +int iSetCPR_PRO_WT_cpr_pro_wt_2(unsigned int ucpr_pro_wt_2); +int iSetCPR_PRO_WT_cpr_pro_wt_3(unsigned int ucpr_pro_wt_3); +int iSetCPR_PRO_WT_cpr_pro_wt_4(unsigned int ucpr_pro_wt_4); +int iSetCPR_FIFO_CRDT_INIT_cpr_fifo_crdt_init_dat(unsigned int ucpr_fifo_crdt_init_dat); +int iSetCPR_FIFO_CRDT_INIT_cpr_fifo_crdt_init(unsigned int ucpr_fifo_crdt_init); +int iSetCPR_DEALC_TX_AF_TH_cpr_dealc_tx_af_th(unsigned int ucpr_dealc_tx_af_th); +int iSetCPR_DEALC_RX_AF_TH_cpr_dealc_rx_af_th(unsigned int ucpr_dealc_rx_af_th); +int iSetCPR_PRLS_AF_TH_cpr_prls_af_th(unsigned int ucpr_prls_af_th); +int iSetCPR_PRLS_AF_TH_cpr_pro_prls_fifo_af_th(unsigned int ucpr_pro_prls_fifo_af_th); +int iSetCPR_COL_TH_cpr_deast_col_th(unsigned int ucpr_deast_col_th); +int iSetCPR_COL_TH_cpr_ast_col_th(unsigned int ucpr_ast_col_th); +int iSetCPR_PRO_DI_FIFO_AF_TH_cpr_pro_di_fifo_af_th(unsigned int ucpr_pro_di_fifo_af_th); +int iSetCPR_PRO_DEALC_TX_FIFO_AF_TH_cpr_pro_dealc_tx_fifo_af_th(unsigned int ucpr_pro_dealc_tx_fifo_af_th); +int iSetCPR_PRO_DEALC_RX_FIFO_AF_TH_cpr_pro_dealc_rx_fifo_af_th(unsigned int ucpr_pro_dealc_rx_fifo_af_th); +int iSetCPR_PRO_FIFO_CRDT_INIT_cpr_pro_dat_fifo_crdt_init_dat(unsigned int ucpr_pro_dat_fifo_crdt_init_dat); +int iSetCPR_PRO_FIFO_CRDT_INIT_cpr_pro_dat_fifo_crdt_init(unsigned int ucpr_pro_dat_fifo_crdt_init); +int iSetCPR_PRO_DEALC_RP_TH_cpr_pro_dealc_rp_th(unsigned int ucpr_pro_dealc_rp_th); +int iSetCPR_PRO_RRDY_FIFO_AF_TH_cpr_pro_rrdy_fifo_af_th(unsigned int ucpr_pro_rrdy_fifo_af_th); +int iSetCPR_OUT_ERR_EN_cpb_perx_err_en(unsigned int ucpb_perx_err_en); +int iSetCPR_OUT_ERR_EN_cpb_perx_ftso_err_en(unsigned int ucpb_perx_ftso_err_en); +int iSetCIT_DAT_FIFO_STA_cit_di_ctrl_fifo_sta(unsigned int ucit_di_ctrl_fifo_sta); +int iSetCIT_DAT_FIFO_STA_cit_di_fifo_sta(unsigned int ucit_di_fifo_sta); +int iSetCIT_DEALC_FIFO_STA_cit_dealc_fifo_sta(unsigned int ucit_dealc_fifo_sta); +int iSetCIT_IN_PKT_SOP_CNT_cit_in_pkt_sop_cnt(unsigned int ucit_in_pkt_sop_cnt); +int iSetCIT_IN_PKT_EOP_CNT_cit_in_pkt_eop_cnt(unsigned int ucit_in_pkt_eop_cnt); +int iSetCIT_IN_CHNL_PKT_CNT_cit_in_chnl_pkt_cnt(unsigned int ucit_in_chnl_pkt_cnt); +int iSetCIT_RPT_IQ_CNT_cit_rpt_iq_cnt(unsigned int ucit_rpt_iq_cnt); +int iSetCIT_IQ_BP_CNT_cit_iq_bp_cnt(unsigned int ucit_iq_bp_cnt); +int iSetCIT_PAL_LESS_STA_cit_pal_less_num(unsigned int ucit_pal_less_num); +int iSetCIT_PAL_LESS_STA_cit_pal_less_cnt(unsigned int ucit_pal_less_cnt); +int iSetCIT_PAL_ERR_cit_pal_err(unsigned int ucit_pal_err); +int iSetCIT_SCHNL_ERR_cit_schnl_err(unsigned int ucit_schnl_err); +int iSetCIT_FIFO_ERR_cit_di_fifo_uf(unsigned int ucit_di_fifo_uf); +int iSetCIT_FIFO_ERR_cit_di_ctrl_fifo_uf(unsigned int ucit_di_ctrl_fifo_uf); +int iSetCIT_FIFO_ERR_cit_dealc_fifo_uf(unsigned int ucit_dealc_fifo_uf); +int iSetCIT_FIFO_ERR_cit_di_fifo_ov(unsigned int ucit_di_fifo_ov); +int iSetCIT_FIFO_ERR_cit_di_ctrl_fifo_ov(unsigned int ucit_di_ctrl_fifo_ov); +int iSetCIT_FIFO_ERR_cit_dealc_fifo_ov(unsigned int ucit_dealc_fifo_ov); +int iSetCIT_EC_ILLEGAL_cit_ec_illegal(unsigned int ucit_ec_illegal); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_addr(unsigned int ucit_fifo_mem_err_addr); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_cerr(unsigned int ucit_fifo_mem_err_cerr); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_ucerr(unsigned int ucit_fifo_mem_err_ucerr); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_cnt(unsigned int ucit_fifo_mem_err_cnt); +int iSetCPR_PRO_DAT_IN_RRDY_FIFO_STA_cpr_pro_rrdy_fifo_sta(unsigned int ucpr_pro_rrdy_fifo_sta); +int iSetCPR_PRO_DAT_IN_RRDY_FIFO_STA_cpr_pro_di_fifo_sta(unsigned int ucpr_pro_di_fifo_sta); +int iSetCPR_PRO_DAT_IN_RRDY_FIFO_STA_cpr_pro_prls_fifo_sta(unsigned int ucpr_pro_prls_fifo_sta); +int iSetCPR_PRO_DEALC_FIFO_STA_cpr_pro_dealc_rx_fifo_sta(unsigned int ucpr_pro_dealc_rx_fifo_sta); +int iSetCPR_PRO_DEALC_FIFO_STA_cpr_pro_dealc_tx_fifo_sta(unsigned int ucpr_pro_dealc_tx_fifo_sta); +int iSetCPR_DEALC_FIFO_STA_cpr_dealc_rx_fifo_sta(unsigned int ucpr_dealc_rx_fifo_sta); +int iSetCPR_DEALC_FIFO_STA_cpr_dealc_tx_fifo_sta(unsigned int ucpr_dealc_tx_fifo_sta); +int iSetCPR_DAT_OUT_FIFO_STA_cpr_dat_out_fifo_sta(unsigned int ucpr_dat_out_fifo_sta); +int iSetCPR_PRLS_FIFO_STA_cpr_prls_fifo_sta(unsigned int ucpr_prls_fifo_sta); +int iSetCPR_OUT_PKT_SOP_CNT_cpr_out_pkt_sop_cnt(unsigned int ucpr_out_pkt_sop_cnt); +int iSetCPR_OUT_PKT_EOP_CNT_cpr_out_pkt_eop_cnt(unsigned int ucpr_out_pkt_eop_cnt); +int iSetCPR_RRDY_SIDE_ERR_cpr_rrdy_side_err(unsigned int ucpr_rrdy_side_err); +int iSetCPR_OUT_CHNL_PKT_CNT_cpr_out_chnl_pkt_cnt(unsigned int ucpr_out_chnl_pkt_cnt); +int iSetCPR_SOF_MSM_cpr_sof_msm_info(unsigned int ucpr_sof_msm_info); +int iSetCPR_SOF_MSM_cpr_sof_msm(unsigned int ucpr_sof_msm); +int iSetCPR_EOF_MSM_cpr_eof_msm_info(unsigned int ucpr_eof_msm_info); +int iSetCPR_EOF_MSM_cpr_eof_msm(unsigned int ucpr_eof_msm); +int iSetCPR_FIFO_OV_ERR_cpr_pro_di_fifo_ov(unsigned int ucpr_pro_di_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_rrdy_fifo_ov(unsigned int ucpr_pro_rrdy_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_dealc_tx_fifo_ov(unsigned int ucpr_pro_dealc_tx_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_dealc_rx_fifo_ov(unsigned int ucpr_pro_dealc_rx_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_prls_fifo_ov(unsigned int ucpr_pro_prls_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_dat_out_fifo_uf(unsigned int ucpr_dat_out_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_dealc_tx_fifo_uf(unsigned int ucpr_dealc_tx_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_dealc_rx_fifo_uf(unsigned int ucpr_dealc_rx_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_prls_fifo_uf(unsigned int ucpr_prls_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_dat_out_fifo_ov(unsigned int ucpr_dat_out_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_dealc_tx_fifo_ov(unsigned int ucpr_dealc_tx_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_dealc_rx_fifo_ov(unsigned int ucpr_dealc_rx_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_prls_fifo_ov(unsigned int ucpr_prls_fifo_ov); +int iSetCPR_FIFO_UF_ERR_cpr_pro_di_fifo_uf(unsigned int ucpr_pro_di_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_rrdy_fifo_uf(unsigned int ucpr_pro_rrdy_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_dealc_tx_fifo_uf(unsigned int ucpr_pro_dealc_tx_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_dealc_rx_fifo_uf(unsigned int ucpr_pro_dealc_rx_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_prls_fifo_uf(unsigned int ucpr_pro_prls_fifo_uf); +int iSetCPR_SGE_CRDT_ERR_sge_zero_clr(unsigned int usge_zero_clr); +int iSetCPR_SGE_CRDT_ERR_sge_crdt_err_pro(unsigned int usge_crdt_err_pro); +int iSetCPR_SGE_CRDT_ERR_sge_crdt_err_chnl(unsigned int usge_crdt_err_chnl); +int iSetCPR_SGE_CRDT_ERR_DMA_HED_L_sge_err_crdt_err_dma_hed_l(unsigned int usge_err_crdt_err_dma_hed_l); +int iSetCPR_SGE_CRDT_ERR_DMA_HED_H_sge_err_crdt_err_dma_hed_h(unsigned int usge_err_crdt_err_dma_hed_h); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_addr(unsigned int ucpr_fifo_mem_err_addr); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_cerr(unsigned int ucpr_fifo_mem_err_cerr); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_ucerr(unsigned int ucpr_fifo_mem_err_ucerr); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_cnt(unsigned int ucpr_fifo_mem_err_cnt); + +/* Define the union csr_stl_rsp_api_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_npt_fifo_crdt : 5; /* [4:0] */ + u32 rsv_0 : 3; /* [7:5] */ + u32 stl_rsp_dat_fifo_crdt : 6; /* [13:8] */ + u32 rsv_1 : 2; /* [15:14] */ + u32 stl_rsp_api_hdr_fifo_crdt : 4; /* [19:16] */ + u32 stl_rsp_crc_fifo_crdt : 4; /* [23:20] */ + u32 stl_rsp_api_fifo_crdt_init : 1; /* [24] */ + u32 rsv_2 : 3; /* [27:25] */ + u32 stl_str_rsp_hdr_crdt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_fifo_crdt_init_u; + +/* Define the union csr_stl_psh_cmd_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_req_wt : 4; /* [3:0] */ + u32 stl_psh_req_wt : 4; /* [7:4] */ + u32 rsv_3 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_psh_cmd_wt_u; + +/* Define the union csr_stl_rd_req_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_req_fifo_af_th : 4; /* [3:0] */ + u32 rsv_4 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rd_req_fifo_af_th_u; + +/* Define the union csr_stl_rd_ctrl_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_ctrl_fifo_af_th : 4; /* [3:0] */ + u32 rsv_5 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rd_ctrl_fifo_af_th_u; + +/* Define the union csr_cpb_stl_api_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_stl_api_crdt : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 cpb_stl_api_crdt_init : 1; /* [8] */ + u32 rsv_7 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_stl_api_crdt_init_u; + +/* Define the union csr_stl_str_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_di_fifo_af_th : 6; /* [5:0] */ + u32 rsv_8 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_di_fifo_af_th_u; + +/* Define the union csr_stl_str_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_api_fifo_af_th : 6; /* [5:0] */ + u32 rsv_9 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_api_fifo_af_th_u; + +/* Define the union csr_stl_cmd_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_api_fifo_af_th : 4; /* [3:0] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_cmd_api_fifo_af_th_u; + +/* Define the union csr_stl_ackstr_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_ackstr_fifo_af_th : 3; /* [2:0] */ + u32 rsv_11 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_ackstr_fifo_af_th_u; + +/* Define the union csr_cdt_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_crdt_cfg : 5; /* [4:0] */ + u32 rsv_12 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_crdt_cfg_u; + +/* Define the union csr_cdt_psh_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_psh_fifo_af_th : 5; /* [4:0] */ + u32 rsv_13 : 3; /* [7:5] */ + u32 cdt_psh_fifo_ae_th : 5; /* [12:8] */ + u32 rsv_14 : 3; /* [15:13] */ + u32 ct_para_ret_cell_num_err_en : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_psh_fifo_cfg_u; + +/* Define the union csr_stliq_psh_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlpsh_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_16 : 2; /* [7:6] */ + u32 stlpsh_fifo_af_th : 6; /* [13:8] */ + u32 rsv_17 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_psh_fifo_cfg_u; + +/* Define the union csr_inner_chn_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inner_cpi_chn_map_mode : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_inner_chn_map_u; + +/* Define the union csr_drp_ack_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_ack_th : 4; /* [3:0] */ + u32 rsv_19 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_ack_th_u; + +/* Define the union csr_oqrx_pd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oqrxpd_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_20 : 1; /* [7] */ + u32 oqrxpd_fifo_af_th : 7; /* [14:8] */ + u32 rsv_21 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oqrx_pd_fifo_cfg_u; + +/* Define the union csr_oqtx_pd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oqtxpd_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_22 : 1; /* [7] */ + u32 oqtxpd_fifo_af_th : 7; /* [14:8] */ + u32 rsv_23 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oqtx_pd_fifo_cfg_u; + +/* Define the union csr_drp_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_24 : 1; /* [7] */ + u32 drp_fifo_af_th : 7; /* [14:8] */ + u32 rsv_25 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_fifo_cfg_u; + +/* Define the union csr_drp_txrls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_txrls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_26 : 1; /* [7] */ + u32 drp_txrls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_27 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_txrls_fifo_cfg_u; + +/* Define the union csr_drp_rxrls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_rxrls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_28 : 1; /* [7] */ + u32 drp_rxrls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_29 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_rxrls_fifo_cfg_u; + +/* Define the union csr_fdrp_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fdrp_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 fdrp_fifo_af_th : 6; /* [13:8] */ + u32 rsv_31 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fdrp_fifo_cfg_u; + +/* Define the union csr_rx_nor_chn_wt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt00 : 3; /* [2:0] */ + u32 rsv_32 : 1; /* [3] */ + u32 perx_cell_req_wt01 : 3; /* [6:4] */ + u32 rsv_33 : 1; /* [7] */ + u32 perx_cell_req_wt02 : 3; /* [10:8] */ + u32 rsv_34 : 1; /* [11] */ + u32 perx_cell_req_wt03 : 3; /* [14:12] */ + u32 rsv_35 : 1; /* [15] */ + u32 perx_cell_req_wt04 : 3; /* [18:16] */ + u32 rsv_36 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt0_u; + +/* Define the union csr_rx_nor_chn_wt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt10 : 3; /* [2:0] */ + u32 rsv_37 : 1; /* [3] */ + u32 perx_cell_req_wt11 : 3; /* [6:4] */ + u32 rsv_38 : 1; /* [7] */ + u32 perx_cell_req_wt12 : 3; /* [10:8] */ + u32 rsv_39 : 1; /* [11] */ + u32 perx_cell_req_wt13 : 3; /* [14:12] */ + u32 rsv_40 : 1; /* [15] */ + u32 perx_cell_req_wt14 : 3; /* [18:16] */ + u32 rsv_41 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt1_u; + +/* Define the union csr_rx_nor_chn_wt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt20 : 3; /* [2:0] */ + u32 rsv_42 : 1; /* [3] */ + u32 perx_cell_req_wt21 : 3; /* [6:4] */ + u32 rsv_43 : 1; /* [7] */ + u32 perx_cell_req_wt22 : 3; /* [10:8] */ + u32 rsv_44 : 1; /* [11] */ + u32 perx_cell_req_wt23 : 3; /* [14:12] */ + u32 rsv_45 : 1; /* [15] */ + u32 perx_cell_req_wt24 : 3; /* [18:16] */ + u32 rsv_46 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt2_u; + +/* Define the union csr_rx_nor_chn_wt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt30 : 3; /* [2:0] */ + u32 rsv_47 : 1; /* [3] */ + u32 perx_cell_req_wt31 : 3; /* [6:4] */ + u32 rsv_48 : 1; /* [7] */ + u32 perx_cell_req_wt32 : 3; /* [10:8] */ + u32 rsv_49 : 1; /* [11] */ + u32 perx_cell_req_wt33 : 3; /* [14:12] */ + u32 rsv_50 : 1; /* [15] */ + u32 perx_cell_req_wt34 : 3; /* [18:16] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt3_u; + +/* Define the union csr_rx_lb_chn_wt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt40 : 3; /* [2:0] */ + u32 rsv_52 : 1; /* [3] */ + u32 perx_cell_req_wt41 : 3; /* [6:4] */ + u32 rsv_53 : 1; /* [7] */ + u32 perx_cell_req_wt42 : 3; /* [10:8] */ + u32 rsv_54 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lb_chn_wt3_u; + +/* Define the union csr_rxlb_port_wt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb0_port0_wt : 3; /* [2:0] */ + u32 rsv_55 : 1; /* [3] */ + u32 rxlb0_port1_wt : 3; /* [6:4] */ + u32 rsv_56 : 1; /* [7] */ + u32 rxlb0_port2_wt : 3; /* [10:8] */ + u32 rsv_57 : 1; /* [11] */ + u32 rxlb0_port3_wt : 3; /* [14:12] */ + u32 rsv_58 : 1; /* [15] */ + u32 rxlb0_port4_wt : 3; /* [18:16] */ + u32 rsv_59 : 1; /* [19] */ + u32 rxlb0_port5_wt : 3; /* [22:20] */ + u32 rsv_60 : 1; /* [23] */ + u32 rxlb0_port6_wt : 3; /* [26:24] */ + u32 rsv_61 : 1; /* [27] */ + u32 rxlb0_port7_wt : 3; /* [30:28] */ + u32 rsv_62 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_port_wt_0_u; + +/* Define the union csr_rxlb_port_wt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb1_port0_wt : 3; /* [2:0] */ + u32 rsv_63 : 1; /* [3] */ + u32 rxlb1_port1_wt : 3; /* [6:4] */ + u32 rsv_64 : 1; /* [7] */ + u32 rxlb1_port2_wt : 3; /* [10:8] */ + u32 rsv_65 : 1; /* [11] */ + u32 rxlb1_port3_wt : 3; /* [14:12] */ + u32 rsv_66 : 1; /* [15] */ + u32 rxlb1_port4_wt : 3; /* [18:16] */ + u32 rsv_67 : 1; /* [19] */ + u32 rxlb1_port5_wt : 3; /* [22:20] */ + u32 rsv_68 : 1; /* [23] */ + u32 rxlb1_port6_wt : 3; /* [26:24] */ + u32 rsv_69 : 1; /* [27] */ + u32 rxlb1_port7_wt : 3; /* [30:28] */ + u32 rsv_70 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_port_wt_1_u; + +/* Define the union csr_cos_chn_rxlb_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_chn_rxlb_cfg_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cos_chn_rxlb_cfg_0_u; + +/* Define the union csr_cos_chn_rxlb_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_chn_rxlb_cfg_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cos_chn_rxlb_cfg_1_u; + +/* Define the union csr_cpb_rx_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_prealc_crdt : 4; /* [3:0] */ + u32 rsv_71 : 4; /* [7:4] */ + u32 dat_prealc_crdt_w : 5; /* [12:8] */ + u32 rsv_72 : 3; /* [15:13] */ + u32 dat_prealc_crdt_o : 5; /* [20:16] */ + u32 rsv_73 : 3; /* [23:21] */ + u32 dat_prealc_crdt_lb : 3; /* [26:24] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_crdt_cfg_u; + +/* Define the union csr_cpb_rx_idx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_idx_crdt : 6; /* [5:0] */ + u32 rsv_75 : 2; /* [7:6] */ + u32 perx_idx_bp_gap : 4; /* [11:8] */ + u32 rsv_76 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_idx_cfg_u; + +/* Define the union csr_chn5_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th0 : 10; /* [9:0] */ + u32 rsv_77 : 2; /* [11:10] */ + u32 chn_sge_shr_th0 : 10; /* [21:12] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn5_sge_cfg_u; + +/* Define the union csr_chn6_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th1 : 10; /* [9:0] */ + u32 rsv_79 : 2; /* [11:10] */ + u32 chn_sge_shr_th1 : 10; /* [21:12] */ + u32 rsv_80 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn6_sge_cfg_u; + +/* Define the union csr_chn7_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th2 : 10; /* [9:0] */ + u32 rsv_81 : 2; /* [11:10] */ + u32 chn_sge_shr_th2 : 10; /* [21:12] */ + u32 rsv_82 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn7_sge_cfg_u; + +/* Define the union csr_chn8_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th3 : 10; /* [9:0] */ + u32 rsv_83 : 2; /* [11:10] */ + u32 chn_sge_shr_th3 : 10; /* [21:12] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn8_sge_cfg_u; + +/* Define the union csr_chn9_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th4 : 10; /* [9:0] */ + u32 rsv_85 : 2; /* [11:10] */ + u32 chn_sge_shr_th4 : 10; /* [21:12] */ + u32 rsv_86 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn9_sge_cfg_u; + +/* Define the union csr_chn10_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th5 : 10; /* [9:0] */ + u32 rsv_87 : 2; /* [11:10] */ + u32 chn_sge_shr_th5 : 10; /* [21:12] */ + u32 rsv_88 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn10_sge_cfg_u; + +/* Define the union csr_chn11_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th6 : 10; /* [9:0] */ + u32 rsv_89 : 2; /* [11:10] */ + u32 chn_sge_shr_th6 : 10; /* [21:12] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn11_sge_cfg_u; + +/* Define the union csr_chn12_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th7 : 10; /* [9:0] */ + u32 rsv_91 : 2; /* [11:10] */ + u32 chn_sge_shr_th7 : 10; /* [21:12] */ + u32 rsv_92 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn12_sge_cfg_u; + +/* Define the union csr_chn13_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th8 : 10; /* [9:0] */ + u32 rsv_93 : 2; /* [11:10] */ + u32 chn_sge_shr_th8 : 10; /* [21:12] */ + u32 rsv_94 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn13_sge_cfg_u; + +/* Define the union csr_chn14_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th9 : 10; /* [9:0] */ + u32 rsv_95 : 2; /* [11:10] */ + u32 chn_sge_shr_th9 : 10; /* [21:12] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn14_sge_cfg_u; + +/* Define the union csr_chn15_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th10 : 10; /* [9:0] */ + u32 rsv_97 : 2; /* [11:10] */ + u32 chn_sge_shr_th10 : 10; /* [21:12] */ + u32 rsv_98 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn15_sge_cfg_u; + +/* Define the union csr_chn16_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th11 : 10; /* [9:0] */ + u32 rsv_99 : 2; /* [11:10] */ + u32 chn_sge_shr_th11 : 10; /* [21:12] */ + u32 rsv_100 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn16_sge_cfg_u; + +/* Define the union csr_chn17_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th12 : 10; /* [9:0] */ + u32 rsv_101 : 2; /* [11:10] */ + u32 chn_sge_shr_th12 : 10; /* [21:12] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn17_sge_cfg_u; + +/* Define the union csr_chn18_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th13 : 10; /* [9:0] */ + u32 rsv_103 : 2; /* [11:10] */ + u32 chn_sge_shr_th13 : 10; /* [21:12] */ + u32 rsv_104 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn18_sge_cfg_u; + +/* Define the union csr_chn19_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th14 : 10; /* [9:0] */ + u32 rsv_105 : 2; /* [11:10] */ + u32 chn_sge_shr_th14 : 10; /* [21:12] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn19_sge_cfg_u; + +/* Define the union csr_chn20_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th15 : 10; /* [9:0] */ + u32 rsv_107 : 2; /* [11:10] */ + u32 chn_sge_shr_th15 : 10; /* [21:12] */ + u32 rsv_108 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn20_sge_cfg_u; + +/* Define the union csr_chn21_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th16 : 10; /* [9:0] */ + u32 rsv_109 : 2; /* [11:10] */ + u32 chn_sge_shr_th16 : 10; /* [21:12] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn21_sge_cfg_u; + +/* Define the union csr_chn22_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th17 : 10; /* [9:0] */ + u32 rsv_111 : 2; /* [11:10] */ + u32 chn_sge_shr_th17 : 10; /* [21:12] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn22_sge_cfg_u; + +/* Define the union csr_chn23_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th18 : 10; /* [9:0] */ + u32 rsv_113 : 2; /* [11:10] */ + u32 chn_sge_shr_th18 : 10; /* [21:12] */ + u32 rsv_114 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn23_sge_cfg_u; + +/* Define the union csr_chn24_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th19 : 10; /* [9:0] */ + u32 rsv_115 : 2; /* [11:10] */ + u32 chn_sge_shr_th19 : 10; /* [21:12] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn24_sge_cfg_u; + +/* Define the union csr_host0_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th0 : 10; /* [9:0] */ + u32 rsv_117 : 6; /* [15:10] */ + u32 host_sge_w_th0 : 10; /* [25:16] */ + u32 rsv_118 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host0_sge_th_u; + +/* Define the union csr_host1_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th1 : 10; /* [9:0] */ + u32 rsv_119 : 6; /* [15:10] */ + u32 host_sge_w_th1 : 10; /* [25:16] */ + u32 rsv_120 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host1_sge_th_u; + +/* Define the union csr_host2_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th2 : 10; /* [9:0] */ + u32 rsv_121 : 6; /* [15:10] */ + u32 host_sge_w_th2 : 10; /* [25:16] */ + u32 rsv_122 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host2_sge_th_u; + +/* Define the union csr_host3_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th3 : 10; /* [9:0] */ + u32 rsv_123 : 6; /* [15:10] */ + u32 host_sge_w_th3 : 10; /* [25:16] */ + u32 rsv_124 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host3_sge_th_u; + +/* Define the union csr_host4_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th4 : 10; /* [9:0] */ + u32 rsv_125 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host4_sge_th_u; + +/* Define the union csr_sge_shr_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_shr_bp_th : 10; /* [9:0] */ + u32 rsv_126 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sge_shr_bp_th_u; + +/* Define the union csr_sge_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_bp_gap : 5; /* [4:0] */ + u32 rsv_127 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sge_bp_gap_u; + +/* Define the union csr_chn5_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th0 : 10; /* [9:0] */ + u32 rsv_128 : 2; /* [11:10] */ + u32 chn_dat_shr_th0 : 10; /* [21:12] */ + u32 rsv_129 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn5_dat_cfg_u; + +/* Define the union csr_chn6_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th1 : 10; /* [9:0] */ + u32 rsv_130 : 2; /* [11:10] */ + u32 chn_dat_shr_th1 : 10; /* [21:12] */ + u32 rsv_131 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn6_dat_cfg_u; + +/* Define the union csr_chn7_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th2 : 10; /* [9:0] */ + u32 rsv_132 : 2; /* [11:10] */ + u32 chn_dat_shr_th2 : 10; /* [21:12] */ + u32 rsv_133 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn7_dat_cfg_u; + +/* Define the union csr_chn8_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th3 : 10; /* [9:0] */ + u32 rsv_134 : 2; /* [11:10] */ + u32 chn_dat_shr_th3 : 10; /* [21:12] */ + u32 rsv_135 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn8_dat_cfg_u; + +/* Define the union csr_chn9_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th4 : 10; /* [9:0] */ + u32 rsv_136 : 2; /* [11:10] */ + u32 chn_dat_shr_th4 : 10; /* [21:12] */ + u32 rsv_137 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn9_dat_cfg_u; + +/* Define the union csr_chn10_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th5 : 10; /* [9:0] */ + u32 rsv_138 : 2; /* [11:10] */ + u32 chn_dat_shr_th5 : 10; /* [21:12] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn10_dat_cfg_u; + +/* Define the union csr_chn11_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th6 : 10; /* [9:0] */ + u32 rsv_140 : 2; /* [11:10] */ + u32 chn_dat_shr_th6 : 10; /* [21:12] */ + u32 rsv_141 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn11_dat_cfg_u; + +/* Define the union csr_chn12_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th7 : 10; /* [9:0] */ + u32 rsv_142 : 2; /* [11:10] */ + u32 chn_dat_shr_th7 : 10; /* [21:12] */ + u32 rsv_143 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn12_dat_cfg_u; + +/* Define the union csr_chn13_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th8 : 10; /* [9:0] */ + u32 rsv_144 : 2; /* [11:10] */ + u32 chn_dat_shr_th8 : 10; /* [21:12] */ + u32 rsv_145 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn13_dat_cfg_u; + +/* Define the union csr_chn14_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th9 : 10; /* [9:0] */ + u32 rsv_146 : 2; /* [11:10] */ + u32 chn_dat_shr_th9 : 10; /* [21:12] */ + u32 rsv_147 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn14_dat_cfg_u; + +/* Define the union csr_chn15_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th10 : 10; /* [9:0] */ + u32 rsv_148 : 2; /* [11:10] */ + u32 chn_dat_shr_th10 : 10; /* [21:12] */ + u32 rsv_149 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn15_dat_cfg_u; + +/* Define the union csr_chn16_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th11 : 10; /* [9:0] */ + u32 rsv_150 : 2; /* [11:10] */ + u32 chn_dat_shr_th11 : 10; /* [21:12] */ + u32 rsv_151 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn16_dat_cfg_u; + +/* Define the union csr_chn17_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th12 : 10; /* [9:0] */ + u32 rsv_152 : 2; /* [11:10] */ + u32 chn_dat_shr_th12 : 10; /* [21:12] */ + u32 rsv_153 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn17_dat_cfg_u; + +/* Define the union csr_chn18_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th13 : 10; /* [9:0] */ + u32 rsv_154 : 2; /* [11:10] */ + u32 chn_dat_shr_th13 : 10; /* [21:12] */ + u32 rsv_155 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn18_dat_cfg_u; + +/* Define the union csr_chn19_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th14 : 10; /* [9:0] */ + u32 rsv_156 : 2; /* [11:10] */ + u32 chn_dat_shr_th14 : 10; /* [21:12] */ + u32 rsv_157 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn19_dat_cfg_u; + +/* Define the union csr_chn20_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th15 : 10; /* [9:0] */ + u32 rsv_158 : 2; /* [11:10] */ + u32 chn_dat_shr_th15 : 10; /* [21:12] */ + u32 rsv_159 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn20_dat_cfg_u; + +/* Define the union csr_chn21_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th16 : 10; /* [9:0] */ + u32 rsv_160 : 2; /* [11:10] */ + u32 chn_dat_shr_th16 : 10; /* [21:12] */ + u32 rsv_161 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn21_dat_cfg_u; + +/* Define the union csr_chn22_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th17 : 10; /* [9:0] */ + u32 rsv_162 : 2; /* [11:10] */ + u32 chn_dat_shr_th17 : 10; /* [21:12] */ + u32 rsv_163 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn22_dat_cfg_u; + +/* Define the union csr_chn23_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th18 : 10; /* [9:0] */ + u32 rsv_164 : 2; /* [11:10] */ + u32 chn_dat_shr_th18 : 10; /* [21:12] */ + u32 rsv_165 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn23_dat_cfg_u; + +/* Define the union csr_chn24_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th19 : 10; /* [9:0] */ + u32 rsv_166 : 2; /* [11:10] */ + u32 chn_dat_shr_th19 : 10; /* [21:12] */ + u32 rsv_167 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn24_dat_cfg_u; + +/* Define the union csr_host0_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th0 : 10; /* [9:0] */ + u32 rsv_168 : 6; /* [15:10] */ + u32 host_dat_w_th0 : 10; /* [25:16] */ + u32 rsv_169 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host0_dat_th_u; + +/* Define the union csr_host1_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th1 : 10; /* [9:0] */ + u32 rsv_170 : 6; /* [15:10] */ + u32 host_dat_w_th1 : 10; /* [25:16] */ + u32 rsv_171 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host1_dat_th_u; + +/* Define the union csr_host2_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th2 : 10; /* [9:0] */ + u32 rsv_172 : 6; /* [15:10] */ + u32 host_dat_w_th2 : 10; /* [25:16] */ + u32 rsv_173 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host2_dat_th_u; + +/* Define the union csr_host3_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th3 : 10; /* [9:0] */ + u32 rsv_174 : 6; /* [15:10] */ + u32 host_dat_w_th3 : 10; /* [25:16] */ + u32 rsv_175 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host3_dat_th_u; + +/* Define the union csr_host4_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th4 : 10; /* [9:0] */ + u32 rsv_176 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host4_dat_th_u; + +/* Define the union csr_dat_shr_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_shr_bp_th : 10; /* [9:0] */ + u32 rsv_177 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dat_shr_bp_th_u; + +/* Define the union csr_dat_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_bp_gap : 5; /* [4:0] */ + u32 rsv_178 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dat_bp_gap_u; + +/* Define the union csr_rx_mpu_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mpu_crdt_th : 7; /* [6:0] */ + u32 rsv_179 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_mpu_dat_cfg_u; + +/* Define the union csr_rx_lb0_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_lb_crdt_th0 : 7; /* [6:0] */ + u32 rsv_180 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lb0_dat_cfg_u; + +/* Define the union csr_rx_lb1_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_lb_crdt_th1 : 7; /* [6:0] */ + u32 rsv_181 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lb1_dat_cfg_u; + +/* Define the union csr_rxlb_dat_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_dat_bp_gap : 4; /* [3:0] */ + u32 rsv_182 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_dat_bp_gap_u; + +/* Define the union csr_rxpd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_183 : 2; /* [7:6] */ + u32 rxpd_fifo_af_th : 6; /* [13:8] */ + u32 rsv_184 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_cfg_u; + +/* Define the union csr_rxmpu_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmpu_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_185 : 2; /* [7:6] */ + u32 rxmpu_fifo_af_th : 6; /* [13:8] */ + u32 rsv_186 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxmpu_fifo_cfg_u; + +/* Define the union csr_rxlb_cos_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_cos_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_187 : 2; /* [7:6] */ + u32 rxlb_cos_fifo_af_th : 6; /* [13:8] */ + u32 rsv_188 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_cos_fifo_cfg_u; + +/* Define the union csr_rx_idx_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_idx_req_wt0 : 3; /* [2:0] */ + u32 rsv_189 : 1; /* [3] */ + u32 cpr_idx_req_wt1 : 3; /* [6:4] */ + u32 rsv_190 : 1; /* [7] */ + u32 cpr_idx_req_wt2 : 3; /* [10:8] */ + u32 rsv_191 : 1; /* [11] */ + u32 cpr_idx_req_wt3 : 3; /* [14:12] */ + u32 rsv_192 : 1; /* [15] */ + u32 cpr_idx_req_wt4 : 3; /* [18:16] */ + u32 rsv_193 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_idx_wt_u; + +/* Define the union csr_rx_host0_chn_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_chn_more_cfg : 1; /* [0] */ + u32 rsv_194 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_host0_chn_m_u; + +/* Define the union csr_rx_tso3_rls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tso3_rls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_195 : 1; /* [7] */ + u32 rx_tso3_rls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_196 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tso3_rls_fifo_cfg_u; + +/* Define the union csr_stl_cmd_api_rd_req_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_197 : 5; /* [15:11] */ + u32 stl_rd_req_fifo_sta : 11; /* [26:16] */ + u32 rsv_198 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_cmd_api_rd_req_fifo_sta_u; + +/* Define the union csr_stl_str_api_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_199 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_api_fifo_sta_u; + +/* Define the union csr_stl_wr_rd_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_wr_di_fifo_sta : 11; /* [10:0] */ + u32 rsv_200 : 5; /* [15:11] */ + u32 stl_rd_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_201 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_wr_rd_dat_in_fifo_sta_u; + +/* Define the union csr_stl_rsp_api_hdr_dat_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_dat_fifo_sta : 11; /* [10:0] */ + u32 rsv_202 : 5; /* [15:11] */ + u32 stl_rsp_api_hdr_fifo_sta : 11; /* [26:16] */ + u32 rsv_203 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_hdr_dat_fifo_sta_u; + +/* Define the union csr_stl_rsp_api_cd_crc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_crc_fifo_sta : 11; /* [10:0] */ + u32 rsv_204 : 5; /* [15:11] */ + u32 stl_rsp_api_cd_fifo_sta : 11; /* [26:16] */ + u32 rsv_205 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_cd_crc_fifo_sta_u; + +/* Define the union csr_stl_rsp_api_cs_nptr_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_nptr_fifo_sta : 11; /* [10:0] */ + u32 rsv_206 : 5; /* [15:11] */ + u32 stl_rsp_api_cs_fifo_sta : 11; /* [26:16] */ + u32 rsv_207 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_cs_nptr_fifo_sta_u; + +/* Define the union csr_stl_str_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_cnt : 16; /* [15:0] */ + u32 stl_str_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_cmd_cnt_u; + +/* Define the union csr_stl_ack_rsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_cnt : 16; /* [15:0] */ + u32 stl_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_ack_rsp_cnt_u; + +/* Define the union csr_stl_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_psh_tl_cnt : 16; /* [15:0] */ + u32 stl_iq_psh_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_psh_cnt_u; + +/* Define the union csr_stl_cell_mdf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cell_mdf_cnt : 16; /* [15:0] */ + u32 rsv_208 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_cell_mdf_cnt_u; + +/* Define the union csr_stl_wr_di_ctrl_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_wr_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_209 : 5; /* [15:11] */ + u32 stl_ackstr_fifo_sta : 11; /* [26:16] */ + u32 rsv_210 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_wr_di_ctrl_fifo_sta_u; + +/* Define the union csr_stl_fifo_ov_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_req_fifo_ov : 4; /* [3:0] */ + u32 stl_cmd_api_fifo_ov : 4; /* [7:4] */ + u32 stl_str_api_fifo_ov : 4; /* [11:8] */ + u32 stl_rd_di_fifo_ov : 2; /* [13:12] */ + u32 rsv_211 : 2; /* [15:14] */ + u32 stl_wr_di_fifo_ov : 2; /* [17:16] */ + u32 rsv_212 : 2; /* [19:18] */ + u32 stl_wr_di_ctrl_fifo_ov : 2; /* [21:20] */ + u32 rsv_213 : 2; /* [23:22] */ + u32 stl_ackstr_fifo_ov : 2; /* [25:24] */ + u32 rsv_214 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_ov_err_0_u; + +/* Define the union csr_stl_fifo_ov_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_hdr_fifo_ov : 4; /* [3:0] */ + u32 stl_rsp_api_dat_fifo_ov : 4; /* [7:4] */ + u32 stl_rsp_api_cd_fifo_ov : 4; /* [11:8] */ + u32 stl_rsp_api_crc_fifo_ov : 4; /* [15:12] */ + u32 stl_rsp_api_cs_fifo_ov : 4; /* [19:16] */ + u32 stl_rsp_api_nptr_fifo_ov : 4; /* [23:20] */ + u32 rsv_215 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_ov_err_1_u; + +/* Define the union csr_stl_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_req_fifo_uf : 4; /* [3:0] */ + u32 stl_cmd_api_fifo_uf : 4; /* [7:4] */ + u32 stl_str_api_fifo_uf : 4; /* [11:8] */ + u32 stl_rd_di_fifo_uf : 2; /* [13:12] */ + u32 rsv_216 : 2; /* [15:14] */ + u32 stl_wr_di_fifo_uf : 2; /* [17:16] */ + u32 rsv_217 : 2; /* [19:18] */ + u32 stl_wr_di_ctrl_fifo_uf : 2; /* [21:20] */ + u32 rsv_218 : 2; /* [23:22] */ + u32 stl_ackstr_fifo_uf : 2; /* [25:24] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_uf_err_0_u; + +/* Define the union csr_stl_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_hdr_fifo_uf : 4; /* [3:0] */ + u32 stl_rsp_api_dat_fifo_uf : 4; /* [7:4] */ + u32 stl_rsp_api_cd_fifo_uf : 4; /* [11:8] */ + u32 stl_rsp_api_crc_fifo_uf : 4; /* [15:12] */ + u32 stl_rsp_api_cs_fifo_uf : 4; /* [19:16] */ + u32 stl_rsp_api_nptr_fifo_uf : 4; /* [23:20] */ + u32 rsv_220 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_uf_err_1_u; + +/* Define the union csr_stlwr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlwr_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_221 : 7; /* [11:5] */ + u32 stlwr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stlwr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_222 : 2; /* [15:14] */ + u32 stlwr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stlwr_fifo_ram_err_u; + +/* Define the union csr_stlstr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlstr_fifo_mem_err_addr : 6; /* [5:0] */ + u32 rsv_223 : 6; /* [11:6] */ + u32 stlstr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stlstr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_224 : 2; /* [15:14] */ + u32 stlstr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stlstr_fifo_ram_err_u; + +/* Define the union csr_stlrsp_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlrsp_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_225 : 7; /* [11:5] */ + u32 stlrsp_fifo_mem_err_cerr : 1; /* [12] */ + u32 stlrsp_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_226 : 2; /* [15:14] */ + u32 stlrsp_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stlrsp_fifo_ram_err_u; + +/* Define the union csr_cdt_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_227 : 9; /* [8:0] */ + u32 psh_ctrl_fifo1_sta : 9; /* [17:9] */ + u32 psh_dat_fifo1_sta : 9; /* [26:18] */ + u32 rsv_228 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_psh_fifo_sta_u; + +/* Define the union csr_cdt_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_psh_fifo_of_err : 3; /* [2:0] */ + u32 cdt_psh_fifo_uf_err : 3; /* [5:3] */ + u32 rsv_229 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_fifo_err_u; + +/* Define the union csr_cdt_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_crdt_cnt : 5; /* [4:0] */ + u32 rsv_230 : 3; /* [7:5] */ + u32 cdt_crdt_of_err : 1; /* [8] */ + u32 cdt_crdt_uf_err : 1; /* [9] */ + u32 geneve_flowpac_ofs_err : 1; /* [10] */ + u32 rsv_231 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_crdt_sta_u; + +/* Define the union csr_stliq_pkt_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_pkt_psh_cnt : 16; /* [15:0] */ + u32 rsv_232 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_pkt_psh_cnt_u; + +/* Define the union csr_stliq_msg_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_msg_psh_cnt : 16; /* [15:0] */ + u32 rsv_233 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_msg_psh_cnt_u; + +/* Define the union csr_flowpac_psh_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flowpac_psh_req_cnt : 16; /* [15:0] */ + u32 rsv_234 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flowpac_psh_req_cnt_u; + +/* Define the union csr_nonflowpac_psh_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nonflowpac_psh_req_cnt : 16; /* [15:0] */ + u32 rsv_235 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nonflowpac_psh_req_cnt_u; + +/* Define the union csr_stliq_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_psh_fifo_sta : 10; /* [9:0] */ + u32 rsv_236 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_psh_fifo_sta_u; + +/* Define the union csr_rob_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rob_psh_fifo_sta : 10; /* [9:0] */ + u32 rsv_237 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rob_psh_fifo_sta_u; + +/* Define the union csr_rx_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_cnt : 16; /* [15:0] */ + u32 rsv_238 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_epd_cnt_u; + +/* Define the union csr_rx_chn_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_epd_cnt : 16; /* [15:0] */ + u32 rsv_239 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_chn_epd_cnt_u; + +/* Define the union csr_tx_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epd_cnt : 16; /* [15:0] */ + u32 rsv_240 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_epd_cnt_u; + +/* Define the union csr_tx_chn_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_epd_cnt : 16; /* [15:0] */ + u32 rsv_241 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_epd_cnt_u; + +/* Define the union csr_txmac_chn_tso12_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txmac_chn_tso12_epd_cnt : 16; /* [15:0] */ + u32 rsv_242 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txmac_chn_tso12_epd_cnt_u; + +/* Define the union csr_drp_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_req_cnt : 16; /* [15:0] */ + u32 rsv_243 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_req_cnt_u; + +/* Define the union csr_rx_tso3_drp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tso3_prls_cnt : 16; /* [15:0] */ + u32 rx_tso3_drp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tso3_drp_cnt_u; + +/* Define the union csr_tx_tso3_drp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tso3_prls_cnt : 16; /* [15:0] */ + u32 tx_tso3_drp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tso3_drp_cnt_u; + +/* Define the union csr_drp_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_eop_cnt : 16; /* [15:0] */ + u32 rsv_244 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_eop_cnt_u; + +/* Define the union csr_rx_epd_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_fifo_sta : 11; /* [10:0] */ + u32 rsv_245 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_epd_fifo_sta_u; + +/* Define the union csr_tx_epd_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epd_fifo_sta : 11; /* [10:0] */ + u32 rsv_246 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_epd_fifo_sta_u; + +/* Define the union csr_ndrp_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ndrp_fifo_sta : 11; /* [10:0] */ + u32 rsv_247 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ndrp_fifo_sta_u; + +/* Define the union csr_drp_rxrls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_rxrls_fifo_sta : 11; /* [10:0] */ + u32 rsv_248 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_rxrls_fifo_sta_u; + +/* Define the union csr_drp_txrls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_txrls_fifo_sta : 11; /* [10:0] */ + u32 rsv_249 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_txrls_fifo_sta_u; + +/* Define the union csr_fdrp_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fdrp_fifo_sta : 11; /* [10:0] */ + u32 rsv_250 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fdrp_fifo_sta_u; + +/* Define the union csr_ftso_drp_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ftso_drp_req_cnt : 16; /* [15:0] */ + u32 rsv_251 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ftso_drp_req_cnt_u; + +/* Define the union csr_coq_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_fifo_of_err : 1; /* [0] */ + u32 tx_epd_fifo_of_err : 1; /* [1] */ + u32 ndrp_fifo_of_err : 1; /* [2] */ + u32 drp_txrls_fifo_of_err : 1; /* [3] */ + u32 drp_rxrls_fifo_of_err : 1; /* [4] */ + u32 fdrp_fifo_of_err : 1; /* [5] */ + u32 rsv_252 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coq_fifo_of_err_u; + +/* Define the union csr_coq_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_fifo_uf_err : 1; /* [0] */ + u32 tx_epd_fifo_uf_err : 1; /* [1] */ + u32 ndrp_fifo_uf_err : 1; /* [2] */ + u32 drp_txrls_fifo_uf_err : 1; /* [3] */ + u32 drp_rxrls_fifo_uf_err : 1; /* [4] */ + u32 fdrp_fifo_uf_err : 1; /* [5] */ + u32 rsv_253 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coq_fifo_uf_err_u; + +/* Define the union csr_coq_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_cpi_chn_err : 1; /* [0] */ + u32 rx_pkt_mode_err : 1; /* [1] */ + u32 rx_pcnum_srch_err : 1; /* [2] */ + u32 tx_lb_chn_err : 1; /* [3] */ + u32 tx_pkt_mode_err : 1; /* [4] */ + u32 tx_pcnum_srch_err : 1; /* [5] */ + u32 rsv_254 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coq_err_u; + +/* Define the union csr_rx_cpi_chn_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_chnsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_255 : 2; /* [11:10] */ + u32 cpi_chnsge_crdt_af : 1; /* [12] */ + u32 rsv_256 : 3; /* [15:13] */ + u32 cpi_chndat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_257 : 2; /* [27:26] */ + u32 cpi_chndat_crdt_af : 1; /* [28] */ + u32 rsv_258 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_chn_crdt_sta_u; + +/* Define the union csr_rx_cpi_host_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_hostsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_259 : 2; /* [11:10] */ + u32 cpi_hostsge_crdt_af : 1; /* [12] */ + u32 rsv_260 : 3; /* [15:13] */ + u32 cpi_hostdat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_261 : 2; /* [27:26] */ + u32 cpi_hostdat_crdt_af : 1; /* [28] */ + u32 rsv_262 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_host_crdt_sta_u; + +/* Define the union csr_rx_cpi_shr_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_shrsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_263 : 2; /* [11:10] */ + u32 cpi_shrsge_crdt_af : 1; /* [12] */ + u32 rsv_264 : 3; /* [15:13] */ + u32 cpi_shrdat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_265 : 2; /* [27:26] */ + u32 cpi_shrdat_crdt_af : 1; /* [28] */ + u32 rsv_266 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_shr_crdt_sta_u; + +/* Define the union csr_rx_cpi_host_wcrdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_host_wsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_267 : 2; /* [11:10] */ + u32 cpb_pqm_hostsge_crdt_bp : 1; /* [12] */ + u32 rsv_268 : 3; /* [15:13] */ + u32 cpi_host_wdat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_269 : 2; /* [27:26] */ + u32 cpb_pqm_hostdat_crdt_bp : 1; /* [28] */ + u32 rsv_270 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_host_wcrdt_sta_u; + +/* Define the union csr_rxlb_chn_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_chn_crdt_cnt : 7; /* [6:0] */ + u32 rsv_271 : 1; /* [7] */ + u32 rxlb_chn_crdt_af : 1; /* [8] */ + u32 rsv_272 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_chn_crdt_sta_u; + +/* Define the union csr_rx_idx_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_idx_crdt_cnt : 6; /* [5:0] */ + u32 rsv_273 : 2; /* [7:6] */ + u32 rx_idx_crdt_af : 1; /* [8] */ + u32 rsv_274 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_idx_crdt_sta_u; + +/* Define the union csr_rxlb_fp_bmp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_fp_bmp_fill : 11; /* [10:0] */ + u32 rsv_275 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_fp_bmp_sta_u; + +/* Define the union csr_rxpd_fifo_empty_sta_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_empty_sta_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_empty_sta_0_u; + +/* Define the union csr_rxpd_fifo_empty_sta_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_empty_sta_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_empty_sta_1_u; + +/* Define the union csr_rxpd_fifo_empty_sta_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_empty_sta_2 : 21; /* [20:0] */ + u32 rsv_276 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_empty_sta_2_u; + +/* Define the union csr_rxpd_fifo_fill_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_fill_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_fill_sta_u; + +/* Define the union csr_rxpd_pro_fsm_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_pro_fsm_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_pro_fsm_sta_u; + +/* Define the union csr_rx_crdt_of_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_idx_crdt_of_err : 1; /* [0] */ + u32 rxlb_chn_crdt_of_err : 3; /* [3:1] */ + u32 cpi_chn_dat_crdt_of_err : 20; /* [23:4] */ + u32 rsv_277 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_of_err_0_u; + +/* Define the union csr_rx_crdt_of_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_chn_sge_crdt_of_err : 20; /* [19:0] */ + u32 rsv_278 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_of_err_1_u; + +/* Define the union csr_rx_crdt_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_idx_crdt_uf_err : 1; /* [0] */ + u32 rxlb_chn_crdt_uf_err : 3; /* [3:1] */ + u32 cpi_chn_dat_crdt_uf_err : 20; /* [23:4] */ + u32 rsv_279 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_uf_err_0_u; + +/* Define the union csr_rx_crdt_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_chn_sge_crdt_uf_err : 20; /* [19:0] */ + u32 rsv_280 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_uf_err_1_u; + +/* Define the union csr_rxpd_fifo_of_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_of_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_of_err_0_u; + +/* Define the union csr_rxpd_fifo_of_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_of_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_of_err_1_u; + +/* Define the union csr_rxpd_fifo_of_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_of_err_2 : 21; /* [20:0] */ + u32 rxlb_fp_fifo_of_err : 1; /* [21] */ + u32 rx_tso3_rls_fifo_of_err : 5; /* [26:22] */ + u32 rsv_281 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_of_err_2_u; + +/* Define the union csr_rxpd_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_uf_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_uf_err_0_u; + +/* Define the union csr_rxpd_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_uf_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_uf_err_1_u; + +/* Define the union csr_rxpd_fifo_uf_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_uf_err_2 : 21; /* [20:0] */ + u32 rxlb_fp_fifo_uf_err : 1; /* [21] */ + u32 rx_tso3_rls_fifo_uf_err : 5; /* [26:22] */ + u32 rsv_282 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_uf_err_2_u; + +/* Define the union csr_rxlb_pd_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_pd_mem_err_addr : 10; /* [9:0] */ + u32 rsv_283 : 2; /* [11:10] */ + u32 rxlb_pd_mem_err_cerr : 1; /* [12] */ + u32 rxlb_pd_mem_err_ucerr : 1; /* [13] */ + u32 rsv_284 : 2; /* [15:14] */ + u32 rxlb_pd_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_pd_ram_err_u; + +/* Define the union csr_cpb_rx_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_pd_pptr_err : 23; /* [22:0] */ + u32 rsv_285 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_0_u; + +/* Define the union csr_cpb_rx_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_pd_pktmod_err : 23; /* [22:0] */ + u32 rsv_286 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_1_u; + +/* Define the union csr_cpb_rx_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_ret_pcnum_err : 23; /* [22:0] */ + u32 rsv_287 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_2_u; + +/* Define the union csr_cpb_rx_err_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_tso2_err : 23; /* [22:0] */ + u32 rx_chn_tso2_num_err : 1; /* [23] */ + u32 rx_chn_tso2_cmd_cnum_err0 : 1; /* [24] */ + u32 rx_chn_tso2_cmd_cnum_err1 : 1; /* [25] */ + u32 rx_chn_tso2_cmd_cnum_err2 : 1; /* [26] */ + u32 rsv_288 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_3_u; + +/* Define the union csr_cpb_rx_err_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_lro1_err : 23; /* [22:0] */ + u32 rx_chn_lro1_num_err : 1; /* [23] */ + u32 rx_chn_lro1_cmd_cnum_err : 1; /* [24] */ + u32 rsv_289 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_4_u; + +/* Define the union csr_cpb_rx_err_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_lro2_err : 23; /* [22:0] */ + u32 rx_chn_lro2_num_err : 1; /* [23] */ + u32 rx_chn_lro2_cmd_cnum_err0 : 1; /* [24] */ + u32 rx_chn_lro2_cmd_cnum_err1 : 1; /* [25] */ + u32 rx_chn_lro2_cmd_cnum_err2 : 1; /* [26] */ + u32 rsv_290 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_5_u; + +/* Define the union csr_rx_tso3_rls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tso3_rls_fifo_sta : 11; /* [10:0] */ + u32 rsv_291 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tso3_rls_fifo_sta_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_stl_rsp_api_fifo_crdt_init_u stl_rsp_api_fifo_crdt_init; /* 800 */ + volatile csr_stl_psh_cmd_wt_u stl_psh_cmd_wt; /* 804 */ + volatile csr_stl_rd_req_fifo_af_th_u stl_rd_req_fifo_af_th; /* 80C */ + volatile csr_stl_rd_ctrl_fifo_af_th_u stl_rd_ctrl_fifo_af_th; /* 810 */ + volatile csr_cpb_stl_api_crdt_init_u cpb_stl_api_crdt_init; /* 814 */ + volatile csr_stl_str_di_fifo_af_th_u stl_str_di_fifo_af_th; /* 818 */ + volatile csr_stl_str_api_fifo_af_th_u stl_str_api_fifo_af_th; /* 81C */ + volatile csr_stl_cmd_api_fifo_af_th_u stl_cmd_api_fifo_af_th; /* 820 */ + volatile csr_stl_ackstr_fifo_af_th_u stl_ackstr_fifo_af_th; /* 824 */ + volatile csr_cdt_crdt_cfg_u cdt_crdt_cfg; /* 8A0 */ + volatile csr_cdt_psh_fifo_cfg_u cdt_psh_fifo_cfg; /* 8B0 */ + volatile csr_stliq_psh_fifo_cfg_u stliq_psh_fifo_cfg; /* 900 */ + volatile csr_inner_chn_map_u inner_chn_map; /* 980 */ + volatile csr_drp_ack_th_u drp_ack_th; /* 984 */ + volatile csr_oqrx_pd_fifo_cfg_u oqrx_pd_fifo_cfg; /* 990 */ + volatile csr_oqtx_pd_fifo_cfg_u oqtx_pd_fifo_cfg; /* 994 */ + volatile csr_drp_fifo_cfg_u drp_fifo_cfg; /* 998 */ + volatile csr_drp_txrls_fifo_cfg_u drp_txrls_fifo_cfg; /* 99C */ + volatile csr_drp_rxrls_fifo_cfg_u drp_rxrls_fifo_cfg; /* 9A0 */ + volatile csr_fdrp_fifo_cfg_u fdrp_fifo_cfg; /* 9A4 */ + volatile csr_rx_nor_chn_wt0_u rx_nor_chn_wt0; /* A00 */ + volatile csr_rx_nor_chn_wt1_u rx_nor_chn_wt1; /* A04 */ + volatile csr_rx_nor_chn_wt2_u rx_nor_chn_wt2; /* A08 */ + volatile csr_rx_nor_chn_wt3_u rx_nor_chn_wt3; /* A0C */ + volatile csr_rx_lb_chn_wt3_u rx_lb_chn_wt3; /* A10 */ + volatile csr_rxlb_port_wt_0_u rxlb_port_wt_0; /* A14 */ + volatile csr_rxlb_port_wt_1_u rxlb_port_wt_1; /* A18 */ + volatile csr_cos_chn_rxlb_cfg_0_u cos_chn_rxlb_cfg_0; /* A1C */ + volatile csr_cos_chn_rxlb_cfg_1_u cos_chn_rxlb_cfg_1; /* A20 */ + volatile csr_cpb_rx_crdt_cfg_u cpb_rx_crdt_cfg; /* A30 */ + volatile csr_cpb_rx_idx_cfg_u cpb_rx_idx_cfg; /* A34 */ + volatile csr_chn5_sge_cfg_u chn5_sge_cfg; /* A40 */ + volatile csr_chn6_sge_cfg_u chn6_sge_cfg; /* A44 */ + volatile csr_chn7_sge_cfg_u chn7_sge_cfg; /* A48 */ + volatile csr_chn8_sge_cfg_u chn8_sge_cfg; /* A4C */ + volatile csr_chn9_sge_cfg_u chn9_sge_cfg; /* A50 */ + volatile csr_chn10_sge_cfg_u chn10_sge_cfg; /* A54 */ + volatile csr_chn11_sge_cfg_u chn11_sge_cfg; /* A58 */ + volatile csr_chn12_sge_cfg_u chn12_sge_cfg; /* A5C */ + volatile csr_chn13_sge_cfg_u chn13_sge_cfg; /* A60 */ + volatile csr_chn14_sge_cfg_u chn14_sge_cfg; /* A64 */ + volatile csr_chn15_sge_cfg_u chn15_sge_cfg; /* A68 */ + volatile csr_chn16_sge_cfg_u chn16_sge_cfg; /* A6C */ + volatile csr_chn17_sge_cfg_u chn17_sge_cfg; /* A70 */ + volatile csr_chn18_sge_cfg_u chn18_sge_cfg; /* A74 */ + volatile csr_chn19_sge_cfg_u chn19_sge_cfg; /* A78 */ + volatile csr_chn20_sge_cfg_u chn20_sge_cfg; /* A7C */ + volatile csr_chn21_sge_cfg_u chn21_sge_cfg; /* A80 */ + volatile csr_chn22_sge_cfg_u chn22_sge_cfg; /* A84 */ + volatile csr_chn23_sge_cfg_u chn23_sge_cfg; /* A88 */ + volatile csr_chn24_sge_cfg_u chn24_sge_cfg; /* A8C */ + volatile csr_host0_sge_th_u host0_sge_th; /* A90 */ + volatile csr_host1_sge_th_u host1_sge_th; /* A94 */ + volatile csr_host2_sge_th_u host2_sge_th; /* A98 */ + volatile csr_host3_sge_th_u host3_sge_th; /* A9C */ + volatile csr_host4_sge_th_u host4_sge_th; /* AA0 */ + volatile csr_sge_shr_bp_th_u sge_shr_bp_th; /* AA4 */ + volatile csr_sge_bp_gap_u sge_bp_gap; /* AA8 */ + volatile csr_chn5_dat_cfg_u chn5_dat_cfg; /* AB0 */ + volatile csr_chn6_dat_cfg_u chn6_dat_cfg; /* AB4 */ + volatile csr_chn7_dat_cfg_u chn7_dat_cfg; /* AB8 */ + volatile csr_chn8_dat_cfg_u chn8_dat_cfg; /* ABC */ + volatile csr_chn9_dat_cfg_u chn9_dat_cfg; /* AC0 */ + volatile csr_chn10_dat_cfg_u chn10_dat_cfg; /* AC4 */ + volatile csr_chn11_dat_cfg_u chn11_dat_cfg; /* AC8 */ + volatile csr_chn12_dat_cfg_u chn12_dat_cfg; /* ACC */ + volatile csr_chn13_dat_cfg_u chn13_dat_cfg; /* AD0 */ + volatile csr_chn14_dat_cfg_u chn14_dat_cfg; /* AD4 */ + volatile csr_chn15_dat_cfg_u chn15_dat_cfg; /* AD8 */ + volatile csr_chn16_dat_cfg_u chn16_dat_cfg; /* ADC */ + volatile csr_chn17_dat_cfg_u chn17_dat_cfg; /* AE0 */ + volatile csr_chn18_dat_cfg_u chn18_dat_cfg; /* AE4 */ + volatile csr_chn19_dat_cfg_u chn19_dat_cfg; /* AE8 */ + volatile csr_chn20_dat_cfg_u chn20_dat_cfg; /* AEC */ + volatile csr_chn21_dat_cfg_u chn21_dat_cfg; /* AF0 */ + volatile csr_chn22_dat_cfg_u chn22_dat_cfg; /* AF4 */ + volatile csr_chn23_dat_cfg_u chn23_dat_cfg; /* AF8 */ + volatile csr_chn24_dat_cfg_u chn24_dat_cfg; /* AFC */ + volatile csr_host0_dat_th_u host0_dat_th; /* B00 */ + volatile csr_host1_dat_th_u host1_dat_th; /* B04 */ + volatile csr_host2_dat_th_u host2_dat_th; /* B08 */ + volatile csr_host3_dat_th_u host3_dat_th; /* B0C */ + volatile csr_host4_dat_th_u host4_dat_th; /* B10 */ + volatile csr_dat_shr_bp_th_u dat_shr_bp_th; /* B14 */ + volatile csr_dat_bp_gap_u dat_bp_gap; /* B18 */ + volatile csr_rx_mpu_dat_cfg_u rx_mpu_dat_cfg; /* B20 */ + volatile csr_rx_lb0_dat_cfg_u rx_lb0_dat_cfg; /* B24 */ + volatile csr_rx_lb1_dat_cfg_u rx_lb1_dat_cfg; /* B28 */ + volatile csr_rxlb_dat_bp_gap_u rxlb_dat_bp_gap; /* B30 */ + volatile csr_rxpd_fifo_cfg_u rxpd_fifo_cfg; /* B40 */ + volatile csr_rxmpu_fifo_cfg_u rxmpu_fifo_cfg; /* B44 */ + volatile csr_rxlb_cos_fifo_cfg_u rxlb_cos_fifo_cfg; /* B48 */ + volatile csr_rx_idx_wt_u rx_idx_wt; /* B54 */ + volatile csr_rx_host0_chn_m_u rx_host0_chn_m; /* B58 */ + volatile csr_rx_tso3_rls_fifo_cfg_u rx_tso3_rls_fifo_cfg; /* B60 */ + volatile csr_stl_cmd_api_rd_req_fifo_sta_u stl_cmd_api_rd_req_fifo_sta[4]; /* 1400 */ + volatile csr_stl_str_api_fifo_sta_u stl_str_api_fifo_sta[4]; /* 1410 */ + volatile csr_stl_wr_rd_dat_in_fifo_sta_u stl_wr_rd_dat_in_fifo_sta[2]; /* 1420 */ + volatile csr_stl_rsp_api_hdr_dat_fifo_sta_u stl_rsp_api_hdr_dat_fifo_sta[4]; /* 1430 */ + volatile csr_stl_rsp_api_cd_crc_fifo_sta_u stl_rsp_api_cd_crc_fifo_sta[4]; /* 1440 */ + volatile csr_stl_rsp_api_cs_nptr_fifo_sta_u stl_rsp_api_cs_nptr_fifo_sta[4]; /* 1450 */ + volatile csr_stl_str_cmd_cnt_u stl_str_cmd_cnt[4]; /* 1460 */ + volatile csr_stl_ack_rsp_cnt_u stl_ack_rsp_cnt[4]; /* 1470 */ + volatile csr_stl_psh_cnt_u stl_psh_cnt[4]; /* 1480 */ + volatile csr_stl_cell_mdf_cnt_u stl_cell_mdf_cnt[4]; /* 1490 */ + volatile csr_stl_wr_di_ctrl_fifo_sta_u stl_wr_di_ctrl_fifo_sta[2]; /* 14A4 */ + volatile csr_stl_fifo_ov_err_0_u stl_fifo_ov_err_0; /* 14B0 */ + volatile csr_stl_fifo_ov_err_1_u stl_fifo_ov_err_1; /* 14B4 */ + volatile csr_stl_fifo_uf_err_0_u stl_fifo_uf_err_0; /* 14B8 */ + volatile csr_stl_fifo_uf_err_1_u stl_fifo_uf_err_1; /* 14BC */ + volatile csr_stlwr_fifo_ram_err_u stlwr_fifo_ram_err[2]; /* 14C0 */ + volatile csr_stlstr_fifo_ram_err_u stlstr_fifo_ram_err[4]; /* 14D0 */ + volatile csr_stlrsp_fifo_ram_err_u stlrsp_fifo_ram_err[4]; /* 14E0 */ + volatile csr_cdt_psh_fifo_sta_u cdt_psh_fifo_sta; /* 15C8 */ + volatile csr_cdt_fifo_err_u cdt_fifo_err; /* 15CC */ + volatile csr_cdt_crdt_sta_u cdt_crdt_sta; /* 15D0 */ + volatile csr_stliq_pkt_psh_cnt_u stliq_pkt_psh_cnt[4]; /* 1600 */ + volatile csr_stliq_msg_psh_cnt_u stliq_msg_psh_cnt[4]; /* 1610 */ + volatile csr_flowpac_psh_req_cnt_u flowpac_psh_req_cnt; /* 1660 */ + volatile csr_nonflowpac_psh_req_cnt_u nonflowpac_psh_req_cnt; /* 1664 */ + volatile csr_stliq_psh_fifo_sta_u stliq_psh_fifo_sta[4]; /* 1680 */ + volatile csr_rob_psh_fifo_sta_u rob_psh_fifo_sta; /* 16B4 */ + volatile csr_rx_epd_cnt_u rx_epd_cnt; /* 1700 */ + volatile csr_rx_chn_epd_cnt_u rx_chn_epd_cnt[23]; /* 1704 */ + volatile csr_tx_epd_cnt_u tx_epd_cnt; /* 1760 */ + volatile csr_tx_chn_epd_cnt_u tx_chn_epd_cnt[11]; /* 1764 */ + volatile csr_txmac_chn_tso12_epd_cnt_u txmac_chn_tso12_epd_cnt[8]; /* 1790 */ + volatile csr_drp_req_cnt_u drp_req_cnt; /* 17B0 */ + volatile csr_rx_tso3_drp_cnt_u rx_tso3_drp_cnt; /* 17B4 */ + volatile csr_tx_tso3_drp_cnt_u tx_tso3_drp_cnt; /* 17B8 */ + volatile csr_drp_eop_cnt_u drp_eop_cnt; /* 17BC */ + volatile csr_rx_epd_fifo_sta_u rx_epd_fifo_sta; /* 17D0 */ + volatile csr_tx_epd_fifo_sta_u tx_epd_fifo_sta; /* 17D4 */ + volatile csr_ndrp_fifo_sta_u ndrp_fifo_sta; /* 17D8 */ + volatile csr_drp_rxrls_fifo_sta_u drp_rxrls_fifo_sta; /* 17DC */ + volatile csr_drp_txrls_fifo_sta_u drp_txrls_fifo_sta; /* 17E0 */ + volatile csr_fdrp_fifo_sta_u fdrp_fifo_sta; /* 17E4 */ + volatile csr_ftso_drp_req_cnt_u ftso_drp_req_cnt; /* 17E8 */ + volatile csr_coq_fifo_of_err_u coq_fifo_of_err; /* 17F0 */ + volatile csr_coq_fifo_uf_err_u coq_fifo_uf_err; /* 17F4 */ + volatile csr_coq_err_u coq_err; /* 17F8 */ + volatile csr_rx_cpi_chn_crdt_sta_u rx_cpi_chn_crdt_sta[20]; /* 1800 */ + volatile csr_rx_cpi_host_crdt_sta_u rx_cpi_host_crdt_sta[5]; /* 1850 */ + volatile csr_rx_cpi_shr_crdt_sta_u rx_cpi_shr_crdt_sta; /* 1864 */ + volatile csr_rx_cpi_host_wcrdt_sta_u rx_cpi_host_wcrdt_sta[4]; /* 1870 */ + volatile csr_rxlb_chn_crdt_sta_u rxlb_chn_crdt_sta[3]; /* 1880 */ + volatile csr_rx_idx_crdt_sta_u rx_idx_crdt_sta; /* 188C */ + volatile csr_rxlb_fp_bmp_sta_u rxlb_fp_bmp_sta; /* 1890 */ + volatile csr_rxpd_fifo_empty_sta_0_u rxpd_fifo_empty_sta_0; /* 1894 */ + volatile csr_rxpd_fifo_empty_sta_1_u rxpd_fifo_empty_sta_1; /* 1898 */ + volatile csr_rxpd_fifo_empty_sta_2_u rxpd_fifo_empty_sta_2; /* 189C */ + volatile csr_rxpd_fifo_fill_sta_u rxpd_fifo_fill_sta[11]; /* 18A0 */ + volatile csr_rxpd_pro_fsm_sta_u rxpd_pro_fsm_sta[23]; /* 1900 */ + volatile csr_rx_crdt_of_err_0_u rx_crdt_of_err_0; /* 1990 */ + volatile csr_rx_crdt_of_err_1_u rx_crdt_of_err_1; /* 1994 */ + volatile csr_rx_crdt_uf_err_0_u rx_crdt_uf_err_0; /* 1998 */ + volatile csr_rx_crdt_uf_err_1_u rx_crdt_uf_err_1; /* 199C */ + volatile csr_rxpd_fifo_of_err_0_u rxpd_fifo_of_err_0; /* 19A0 */ + volatile csr_rxpd_fifo_of_err_1_u rxpd_fifo_of_err_1; /* 19A4 */ + volatile csr_rxpd_fifo_of_err_2_u rxpd_fifo_of_err_2; /* 19A8 */ + volatile csr_rxpd_fifo_uf_err_0_u rxpd_fifo_uf_err_0; /* 19B0 */ + volatile csr_rxpd_fifo_uf_err_1_u rxpd_fifo_uf_err_1; /* 19B4 */ + volatile csr_rxpd_fifo_uf_err_2_u rxpd_fifo_uf_err_2; /* 19B8 */ + volatile csr_rxlb_pd_ram_err_u rxlb_pd_ram_err; /* 19BC */ + volatile csr_cpb_rx_err_0_u cpb_rx_err_0; /* 19C0 */ + volatile csr_cpb_rx_err_1_u cpb_rx_err_1; /* 19C4 */ + volatile csr_cpb_rx_err_2_u cpb_rx_err_2; /* 19C8 */ + volatile csr_cpb_rx_err_3_u cpb_rx_err_3; /* 19CC */ + volatile csr_cpb_rx_err_4_u cpb_rx_err_4; /* 19D0 */ + volatile csr_cpb_rx_err_5_u cpb_rx_err_5; /* 19D4 */ + volatile csr_rx_tso3_rls_fifo_sta_u rx_tso3_rls_fifo_sta[5]; /* 19E0 */ +} S_cpb_csr_2_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_2 */ +extern volatile S_cpb_csr_2_REGS_TYPE *gopcpb_csr_2AllReg; + +/* Declare the functions that set the member value */ +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_npt_fifo_crdt(unsigned int ustl_rsp_npt_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_dat_fifo_crdt(unsigned int ustl_rsp_dat_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_api_hdr_fifo_crdt(unsigned int ustl_rsp_api_hdr_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_crc_fifo_crdt(unsigned int ustl_rsp_crc_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_api_fifo_crdt_init(unsigned int ustl_rsp_api_fifo_crdt_init); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_str_rsp_hdr_crdt(unsigned int ustl_str_rsp_hdr_crdt); +int iSetSTL_PSH_CMD_WT_stl_cmd_req_wt(unsigned int ustl_cmd_req_wt); +int iSetSTL_PSH_CMD_WT_stl_psh_req_wt(unsigned int ustl_psh_req_wt); +int iSetSTL_RD_REQ_FIFO_AF_TH_stl_rd_req_fifo_af_th(unsigned int ustl_rd_req_fifo_af_th); +int iSetSTL_RD_CTRL_FIFO_AF_TH_stl_rd_ctrl_fifo_af_th(unsigned int ustl_rd_ctrl_fifo_af_th); +int iSetCPB_STL_API_CRDT_INIT_cpb_stl_api_crdt(unsigned int ucpb_stl_api_crdt); +int iSetCPB_STL_API_CRDT_INIT_cpb_stl_api_crdt_init(unsigned int ucpb_stl_api_crdt_init); +int iSetSTL_STR_DI_FIFO_AF_TH_stl_str_di_fifo_af_th(unsigned int ustl_str_di_fifo_af_th); +int iSetSTL_STR_API_FIFO_AF_TH_stl_str_api_fifo_af_th(unsigned int ustl_str_api_fifo_af_th); +int iSetSTL_CMD_API_FIFO_AF_TH_stl_cmd_api_fifo_af_th(unsigned int ustl_cmd_api_fifo_af_th); +int iSetSTL_ACKSTR_FIFO_AF_TH_stl_ackstr_fifo_af_th(unsigned int ustl_ackstr_fifo_af_th); +int iSetCDT_CRDT_CFG_cdt_crdt_cfg(unsigned int ucdt_crdt_cfg); +int iSetCDT_PSH_FIFO_CFG_cdt_psh_fifo_af_th(unsigned int ucdt_psh_fifo_af_th); +int iSetCDT_PSH_FIFO_CFG_cdt_psh_fifo_ae_th(unsigned int ucdt_psh_fifo_ae_th); +int iSetCDT_PSH_FIFO_CFG_ct_para_ret_cell_num_err_en(unsigned int uct_para_ret_cell_num_err_en); +int iSetSTLIQ_PSH_FIFO_CFG_stlpsh_fifo_ae_th(unsigned int ustlpsh_fifo_ae_th); +int iSetSTLIQ_PSH_FIFO_CFG_stlpsh_fifo_af_th(unsigned int ustlpsh_fifo_af_th); +int iSetINNER_CHN_MAP_inner_cpi_chn_map_mode(unsigned int uinner_cpi_chn_map_mode); +int iSetDRP_ACK_TH_drp_ack_th(unsigned int udrp_ack_th); +int iSetOQRX_PD_FIFO_CFG_oqrxpd_fifo_ae_th(unsigned int uoqrxpd_fifo_ae_th); +int iSetOQRX_PD_FIFO_CFG_oqrxpd_fifo_af_th(unsigned int uoqrxpd_fifo_af_th); +int iSetOQTX_PD_FIFO_CFG_oqtxpd_fifo_ae_th(unsigned int uoqtxpd_fifo_ae_th); +int iSetOQTX_PD_FIFO_CFG_oqtxpd_fifo_af_th(unsigned int uoqtxpd_fifo_af_th); +int iSetDRP_FIFO_CFG_drp_fifo_ae_th(unsigned int udrp_fifo_ae_th); +int iSetDRP_FIFO_CFG_drp_fifo_af_th(unsigned int udrp_fifo_af_th); +int iSetDRP_TXRLS_FIFO_CFG_drp_txrls_fifo_ae_th(unsigned int udrp_txrls_fifo_ae_th); +int iSetDRP_TXRLS_FIFO_CFG_drp_txrls_fifo_af_th(unsigned int udrp_txrls_fifo_af_th); +int iSetDRP_RXRLS_FIFO_CFG_drp_rxrls_fifo_ae_th(unsigned int udrp_rxrls_fifo_ae_th); +int iSetDRP_RXRLS_FIFO_CFG_drp_rxrls_fifo_af_th(unsigned int udrp_rxrls_fifo_af_th); +int iSetFDRP_FIFO_CFG_fdrp_fifo_ae_th(unsigned int ufdrp_fifo_ae_th); +int iSetFDRP_FIFO_CFG_fdrp_fifo_af_th(unsigned int ufdrp_fifo_af_th); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt00(unsigned int uperx_cell_req_wt00); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt01(unsigned int uperx_cell_req_wt01); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt02(unsigned int uperx_cell_req_wt02); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt03(unsigned int uperx_cell_req_wt03); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt04(unsigned int uperx_cell_req_wt04); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt10(unsigned int uperx_cell_req_wt10); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt11(unsigned int uperx_cell_req_wt11); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt12(unsigned int uperx_cell_req_wt12); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt13(unsigned int uperx_cell_req_wt13); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt14(unsigned int uperx_cell_req_wt14); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt20(unsigned int uperx_cell_req_wt20); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt21(unsigned int uperx_cell_req_wt21); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt22(unsigned int uperx_cell_req_wt22); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt23(unsigned int uperx_cell_req_wt23); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt24(unsigned int uperx_cell_req_wt24); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt30(unsigned int uperx_cell_req_wt30); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt31(unsigned int uperx_cell_req_wt31); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt32(unsigned int uperx_cell_req_wt32); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt33(unsigned int uperx_cell_req_wt33); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt34(unsigned int uperx_cell_req_wt34); +int iSetRX_LB_CHN_WT3_perx_cell_req_wt40(unsigned int uperx_cell_req_wt40); +int iSetRX_LB_CHN_WT3_perx_cell_req_wt41(unsigned int uperx_cell_req_wt41); +int iSetRX_LB_CHN_WT3_perx_cell_req_wt42(unsigned int uperx_cell_req_wt42); +int iSetRXLB_PORT_WT_0_rxlb0_port0_wt(unsigned int urxlb0_port0_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port1_wt(unsigned int urxlb0_port1_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port2_wt(unsigned int urxlb0_port2_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port3_wt(unsigned int urxlb0_port3_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port4_wt(unsigned int urxlb0_port4_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port5_wt(unsigned int urxlb0_port5_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port6_wt(unsigned int urxlb0_port6_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port7_wt(unsigned int urxlb0_port7_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port0_wt(unsigned int urxlb1_port0_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port1_wt(unsigned int urxlb1_port1_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port2_wt(unsigned int urxlb1_port2_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port3_wt(unsigned int urxlb1_port3_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port4_wt(unsigned int urxlb1_port4_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port5_wt(unsigned int urxlb1_port5_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port6_wt(unsigned int urxlb1_port6_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port7_wt(unsigned int urxlb1_port7_wt); +int iSetCOS_CHN_RXLB_CFG_0_cos_chn_rxlb_cfg_0(unsigned int ucos_chn_rxlb_cfg_0); +int iSetCOS_CHN_RXLB_CFG_1_cos_chn_rxlb_cfg_1(unsigned int ucos_chn_rxlb_cfg_1); +int iSetCPB_RX_CRDT_CFG_sge_prealc_crdt(unsigned int usge_prealc_crdt); +int iSetCPB_RX_CRDT_CFG_dat_prealc_crdt_w(unsigned int udat_prealc_crdt_w); +int iSetCPB_RX_CRDT_CFG_dat_prealc_crdt_o(unsigned int udat_prealc_crdt_o); +int iSetCPB_RX_CRDT_CFG_dat_prealc_crdt_lb(unsigned int udat_prealc_crdt_lb); +int iSetCPB_RX_IDX_CFG_perx_idx_crdt(unsigned int uperx_idx_crdt); +int iSetCPB_RX_IDX_CFG_perx_idx_bp_gap(unsigned int uperx_idx_bp_gap); +int iSetCHN5_SGE_CFG_chn_sge_rsv_th0(unsigned int uchn_sge_rsv_th0); +int iSetCHN5_SGE_CFG_chn_sge_shr_th0(unsigned int uchn_sge_shr_th0); +int iSetCHN6_SGE_CFG_chn_sge_rsv_th1(unsigned int uchn_sge_rsv_th1); +int iSetCHN6_SGE_CFG_chn_sge_shr_th1(unsigned int uchn_sge_shr_th1); +int iSetCHN7_SGE_CFG_chn_sge_rsv_th2(unsigned int uchn_sge_rsv_th2); +int iSetCHN7_SGE_CFG_chn_sge_shr_th2(unsigned int uchn_sge_shr_th2); +int iSetCHN8_SGE_CFG_chn_sge_rsv_th3(unsigned int uchn_sge_rsv_th3); +int iSetCHN8_SGE_CFG_chn_sge_shr_th3(unsigned int uchn_sge_shr_th3); +int iSetCHN9_SGE_CFG_chn_sge_rsv_th4(unsigned int uchn_sge_rsv_th4); +int iSetCHN9_SGE_CFG_chn_sge_shr_th4(unsigned int uchn_sge_shr_th4); +int iSetCHN10_SGE_CFG_chn_sge_rsv_th5(unsigned int uchn_sge_rsv_th5); +int iSetCHN10_SGE_CFG_chn_sge_shr_th5(unsigned int uchn_sge_shr_th5); +int iSetCHN11_SGE_CFG_chn_sge_rsv_th6(unsigned int uchn_sge_rsv_th6); +int iSetCHN11_SGE_CFG_chn_sge_shr_th6(unsigned int uchn_sge_shr_th6); +int iSetCHN12_SGE_CFG_chn_sge_rsv_th7(unsigned int uchn_sge_rsv_th7); +int iSetCHN12_SGE_CFG_chn_sge_shr_th7(unsigned int uchn_sge_shr_th7); +int iSetCHN13_SGE_CFG_chn_sge_rsv_th8(unsigned int uchn_sge_rsv_th8); +int iSetCHN13_SGE_CFG_chn_sge_shr_th8(unsigned int uchn_sge_shr_th8); +int iSetCHN14_SGE_CFG_chn_sge_rsv_th9(unsigned int uchn_sge_rsv_th9); +int iSetCHN14_SGE_CFG_chn_sge_shr_th9(unsigned int uchn_sge_shr_th9); +int iSetCHN15_SGE_CFG_chn_sge_rsv_th10(unsigned int uchn_sge_rsv_th10); +int iSetCHN15_SGE_CFG_chn_sge_shr_th10(unsigned int uchn_sge_shr_th10); +int iSetCHN16_SGE_CFG_chn_sge_rsv_th11(unsigned int uchn_sge_rsv_th11); +int iSetCHN16_SGE_CFG_chn_sge_shr_th11(unsigned int uchn_sge_shr_th11); +int iSetCHN17_SGE_CFG_chn_sge_rsv_th12(unsigned int uchn_sge_rsv_th12); +int iSetCHN17_SGE_CFG_chn_sge_shr_th12(unsigned int uchn_sge_shr_th12); +int iSetCHN18_SGE_CFG_chn_sge_rsv_th13(unsigned int uchn_sge_rsv_th13); +int iSetCHN18_SGE_CFG_chn_sge_shr_th13(unsigned int uchn_sge_shr_th13); +int iSetCHN19_SGE_CFG_chn_sge_rsv_th14(unsigned int uchn_sge_rsv_th14); +int iSetCHN19_SGE_CFG_chn_sge_shr_th14(unsigned int uchn_sge_shr_th14); +int iSetCHN20_SGE_CFG_chn_sge_rsv_th15(unsigned int uchn_sge_rsv_th15); +int iSetCHN20_SGE_CFG_chn_sge_shr_th15(unsigned int uchn_sge_shr_th15); +int iSetCHN21_SGE_CFG_chn_sge_rsv_th16(unsigned int uchn_sge_rsv_th16); +int iSetCHN21_SGE_CFG_chn_sge_shr_th16(unsigned int uchn_sge_shr_th16); +int iSetCHN22_SGE_CFG_chn_sge_rsv_th17(unsigned int uchn_sge_rsv_th17); +int iSetCHN22_SGE_CFG_chn_sge_shr_th17(unsigned int uchn_sge_shr_th17); +int iSetCHN23_SGE_CFG_chn_sge_rsv_th18(unsigned int uchn_sge_rsv_th18); +int iSetCHN23_SGE_CFG_chn_sge_shr_th18(unsigned int uchn_sge_shr_th18); +int iSetCHN24_SGE_CFG_chn_sge_rsv_th19(unsigned int uchn_sge_rsv_th19); +int iSetCHN24_SGE_CFG_chn_sge_shr_th19(unsigned int uchn_sge_shr_th19); +int iSetHOST0_SGE_TH_host_sge_th0(unsigned int uhost_sge_th0); +int iSetHOST0_SGE_TH_host_sge_w_th0(unsigned int uhost_sge_w_th0); +int iSetHOST1_SGE_TH_host_sge_th1(unsigned int uhost_sge_th1); +int iSetHOST1_SGE_TH_host_sge_w_th1(unsigned int uhost_sge_w_th1); +int iSetHOST2_SGE_TH_host_sge_th2(unsigned int uhost_sge_th2); +int iSetHOST2_SGE_TH_host_sge_w_th2(unsigned int uhost_sge_w_th2); +int iSetHOST3_SGE_TH_host_sge_th3(unsigned int uhost_sge_th3); +int iSetHOST3_SGE_TH_host_sge_w_th3(unsigned int uhost_sge_w_th3); +int iSetHOST4_SGE_TH_host_sge_th4(unsigned int uhost_sge_th4); +int iSetSGE_SHR_BP_TH_sge_shr_bp_th(unsigned int usge_shr_bp_th); +int iSetSGE_BP_GAP_sge_bp_gap(unsigned int usge_bp_gap); +int iSetCHN5_DAT_CFG_chn_dat_rsv_th0(unsigned int uchn_dat_rsv_th0); +int iSetCHN5_DAT_CFG_chn_dat_shr_th0(unsigned int uchn_dat_shr_th0); +int iSetCHN6_DAT_CFG_chn_dat_rsv_th1(unsigned int uchn_dat_rsv_th1); +int iSetCHN6_DAT_CFG_chn_dat_shr_th1(unsigned int uchn_dat_shr_th1); +int iSetCHN7_DAT_CFG_chn_dat_rsv_th2(unsigned int uchn_dat_rsv_th2); +int iSetCHN7_DAT_CFG_chn_dat_shr_th2(unsigned int uchn_dat_shr_th2); +int iSetCHN8_DAT_CFG_chn_dat_rsv_th3(unsigned int uchn_dat_rsv_th3); +int iSetCHN8_DAT_CFG_chn_dat_shr_th3(unsigned int uchn_dat_shr_th3); +int iSetCHN9_DAT_CFG_chn_dat_rsv_th4(unsigned int uchn_dat_rsv_th4); +int iSetCHN9_DAT_CFG_chn_dat_shr_th4(unsigned int uchn_dat_shr_th4); +int iSetCHN10_DAT_CFG_chn_dat_rsv_th5(unsigned int uchn_dat_rsv_th5); +int iSetCHN10_DAT_CFG_chn_dat_shr_th5(unsigned int uchn_dat_shr_th5); +int iSetCHN11_DAT_CFG_chn_dat_rsv_th6(unsigned int uchn_dat_rsv_th6); +int iSetCHN11_DAT_CFG_chn_dat_shr_th6(unsigned int uchn_dat_shr_th6); +int iSetCHN12_DAT_CFG_chn_dat_rsv_th7(unsigned int uchn_dat_rsv_th7); +int iSetCHN12_DAT_CFG_chn_dat_shr_th7(unsigned int uchn_dat_shr_th7); +int iSetCHN13_DAT_CFG_chn_dat_rsv_th8(unsigned int uchn_dat_rsv_th8); +int iSetCHN13_DAT_CFG_chn_dat_shr_th8(unsigned int uchn_dat_shr_th8); +int iSetCHN14_DAT_CFG_chn_dat_rsv_th9(unsigned int uchn_dat_rsv_th9); +int iSetCHN14_DAT_CFG_chn_dat_shr_th9(unsigned int uchn_dat_shr_th9); +int iSetCHN15_DAT_CFG_chn_dat_rsv_th10(unsigned int uchn_dat_rsv_th10); +int iSetCHN15_DAT_CFG_chn_dat_shr_th10(unsigned int uchn_dat_shr_th10); +int iSetCHN16_DAT_CFG_chn_dat_rsv_th11(unsigned int uchn_dat_rsv_th11); +int iSetCHN16_DAT_CFG_chn_dat_shr_th11(unsigned int uchn_dat_shr_th11); +int iSetCHN17_DAT_CFG_chn_dat_rsv_th12(unsigned int uchn_dat_rsv_th12); +int iSetCHN17_DAT_CFG_chn_dat_shr_th12(unsigned int uchn_dat_shr_th12); +int iSetCHN18_DAT_CFG_chn_dat_rsv_th13(unsigned int uchn_dat_rsv_th13); +int iSetCHN18_DAT_CFG_chn_dat_shr_th13(unsigned int uchn_dat_shr_th13); +int iSetCHN19_DAT_CFG_chn_dat_rsv_th14(unsigned int uchn_dat_rsv_th14); +int iSetCHN19_DAT_CFG_chn_dat_shr_th14(unsigned int uchn_dat_shr_th14); +int iSetCHN20_DAT_CFG_chn_dat_rsv_th15(unsigned int uchn_dat_rsv_th15); +int iSetCHN20_DAT_CFG_chn_dat_shr_th15(unsigned int uchn_dat_shr_th15); +int iSetCHN21_DAT_CFG_chn_dat_rsv_th16(unsigned int uchn_dat_rsv_th16); +int iSetCHN21_DAT_CFG_chn_dat_shr_th16(unsigned int uchn_dat_shr_th16); +int iSetCHN22_DAT_CFG_chn_dat_rsv_th17(unsigned int uchn_dat_rsv_th17); +int iSetCHN22_DAT_CFG_chn_dat_shr_th17(unsigned int uchn_dat_shr_th17); +int iSetCHN23_DAT_CFG_chn_dat_rsv_th18(unsigned int uchn_dat_rsv_th18); +int iSetCHN23_DAT_CFG_chn_dat_shr_th18(unsigned int uchn_dat_shr_th18); +int iSetCHN24_DAT_CFG_chn_dat_rsv_th19(unsigned int uchn_dat_rsv_th19); +int iSetCHN24_DAT_CFG_chn_dat_shr_th19(unsigned int uchn_dat_shr_th19); +int iSetHOST0_DAT_TH_host_dat_th0(unsigned int uhost_dat_th0); +int iSetHOST0_DAT_TH_host_dat_w_th0(unsigned int uhost_dat_w_th0); +int iSetHOST1_DAT_TH_host_dat_th1(unsigned int uhost_dat_th1); +int iSetHOST1_DAT_TH_host_dat_w_th1(unsigned int uhost_dat_w_th1); +int iSetHOST2_DAT_TH_host_dat_th2(unsigned int uhost_dat_th2); +int iSetHOST2_DAT_TH_host_dat_w_th2(unsigned int uhost_dat_w_th2); +int iSetHOST3_DAT_TH_host_dat_th3(unsigned int uhost_dat_th3); +int iSetHOST3_DAT_TH_host_dat_w_th3(unsigned int uhost_dat_w_th3); +int iSetHOST4_DAT_TH_host_dat_th4(unsigned int uhost_dat_th4); +int iSetDAT_SHR_BP_TH_dat_shr_bp_th(unsigned int udat_shr_bp_th); +int iSetDAT_BP_GAP_dat_bp_gap(unsigned int udat_bp_gap); +int iSetRX_MPU_DAT_CFG_rx_mpu_crdt_th(unsigned int urx_mpu_crdt_th); +int iSetRX_LB0_DAT_CFG_rx_lb_crdt_th0(unsigned int urx_lb_crdt_th0); +int iSetRX_LB1_DAT_CFG_rx_lb_crdt_th1(unsigned int urx_lb_crdt_th1); +int iSetRXLB_DAT_BP_GAP_rxlb_dat_bp_gap(unsigned int urxlb_dat_bp_gap); +int iSetRXPD_FIFO_CFG_rxpd_fifo_ae_th(unsigned int urxpd_fifo_ae_th); +int iSetRXPD_FIFO_CFG_rxpd_fifo_af_th(unsigned int urxpd_fifo_af_th); +int iSetRXMPU_FIFO_CFG_rxmpu_fifo_ae_th(unsigned int urxmpu_fifo_ae_th); +int iSetRXMPU_FIFO_CFG_rxmpu_fifo_af_th(unsigned int urxmpu_fifo_af_th); +int iSetRXLB_COS_FIFO_CFG_rxlb_cos_fifo_ae_th(unsigned int urxlb_cos_fifo_ae_th); +int iSetRXLB_COS_FIFO_CFG_rxlb_cos_fifo_af_th(unsigned int urxlb_cos_fifo_af_th); +int iSetRX_IDX_WT_cpr_idx_req_wt0(unsigned int ucpr_idx_req_wt0); +int iSetRX_IDX_WT_cpr_idx_req_wt1(unsigned int ucpr_idx_req_wt1); +int iSetRX_IDX_WT_cpr_idx_req_wt2(unsigned int ucpr_idx_req_wt2); +int iSetRX_IDX_WT_cpr_idx_req_wt3(unsigned int ucpr_idx_req_wt3); +int iSetRX_IDX_WT_cpr_idx_req_wt4(unsigned int ucpr_idx_req_wt4); +int iSetRX_HOST0_CHN_M_host0_chn_more_cfg(unsigned int uhost0_chn_more_cfg); +int iSetRX_TSO3_RLS_FIFO_CFG_rx_tso3_rls_fifo_ae_th(unsigned int urx_tso3_rls_fifo_ae_th); +int iSetRX_TSO3_RLS_FIFO_CFG_rx_tso3_rls_fifo_af_th(unsigned int urx_tso3_rls_fifo_af_th); +int iSetSTL_CMD_API_RD_REQ_FIFO_STA_stl_cmd_api_fifo_sta(unsigned int ustl_cmd_api_fifo_sta); +int iSetSTL_CMD_API_RD_REQ_FIFO_STA_stl_rd_req_fifo_sta(unsigned int ustl_rd_req_fifo_sta); +int iSetSTL_STR_API_FIFO_STA_stl_str_api_fifo_sta(unsigned int ustl_str_api_fifo_sta); +int iSetSTL_WR_RD_DAT_IN_FIFO_STA_stl_wr_di_fifo_sta(unsigned int ustl_wr_di_fifo_sta); +int iSetSTL_WR_RD_DAT_IN_FIFO_STA_stl_rd_di_fifo_sta(unsigned int ustl_rd_di_fifo_sta); +int iSetSTL_RSP_API_HDR_DAT_FIFO_STA_stl_rsp_api_dat_fifo_sta(unsigned int ustl_rsp_api_dat_fifo_sta); +int iSetSTL_RSP_API_HDR_DAT_FIFO_STA_stl_rsp_api_hdr_fifo_sta(unsigned int ustl_rsp_api_hdr_fifo_sta); +int iSetSTL_RSP_API_CD_CRC_FIFO_STA_stl_rsp_api_crc_fifo_sta(unsigned int ustl_rsp_api_crc_fifo_sta); +int iSetSTL_RSP_API_CD_CRC_FIFO_STA_stl_rsp_api_cd_fifo_sta(unsigned int ustl_rsp_api_cd_fifo_sta); +int iSetSTL_RSP_API_CS_NPTR_FIFO_STA_stl_rsp_api_nptr_fifo_sta(unsigned int ustl_rsp_api_nptr_fifo_sta); +int iSetSTL_RSP_API_CS_NPTR_FIFO_STA_stl_rsp_api_cs_fifo_sta(unsigned int ustl_rsp_api_cs_fifo_sta); +int iSetSTL_STR_CMD_CNT_stl_cmd_cnt(unsigned int ustl_cmd_cnt); +int iSetSTL_STR_CMD_CNT_stl_str_cnt(unsigned int ustl_str_cnt); +int iSetSTL_ACK_RSP_CNT_stl_rsp_cnt(unsigned int ustl_rsp_cnt); +int iSetSTL_ACK_RSP_CNT_stl_ack_cnt(unsigned int ustl_ack_cnt); +int iSetSTL_PSH_CNT_stl_psh_tl_cnt(unsigned int ustl_psh_tl_cnt); +int iSetSTL_PSH_CNT_stl_iq_psh_cnt(unsigned int ustl_iq_psh_cnt); +int iSetSTL_CELL_MDF_CNT_stl_cell_mdf_cnt(unsigned int ustl_cell_mdf_cnt); +int iSetSTL_WR_DI_CTRL_FIFO_STA_stl_wr_di_ctrl_fifo_sta(unsigned int ustl_wr_di_ctrl_fifo_sta); +int iSetSTL_WR_DI_CTRL_FIFO_STA_stl_ackstr_fifo_sta(unsigned int ustl_ackstr_fifo_sta); +int iSetSTL_FIFO_OV_ERR_0_stl_rd_req_fifo_ov(unsigned int ustl_rd_req_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_cmd_api_fifo_ov(unsigned int ustl_cmd_api_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_str_api_fifo_ov(unsigned int ustl_str_api_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_rd_di_fifo_ov(unsigned int ustl_rd_di_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_wr_di_fifo_ov(unsigned int ustl_wr_di_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_wr_di_ctrl_fifo_ov(unsigned int ustl_wr_di_ctrl_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_ackstr_fifo_ov(unsigned int ustl_ackstr_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_hdr_fifo_ov(unsigned int ustl_rsp_api_hdr_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_dat_fifo_ov(unsigned int ustl_rsp_api_dat_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_cd_fifo_ov(unsigned int ustl_rsp_api_cd_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_crc_fifo_ov(unsigned int ustl_rsp_api_crc_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_cs_fifo_ov(unsigned int ustl_rsp_api_cs_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_nptr_fifo_ov(unsigned int ustl_rsp_api_nptr_fifo_ov); +int iSetSTL_FIFO_UF_ERR_0_stl_rd_req_fifo_uf(unsigned int ustl_rd_req_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_cmd_api_fifo_uf(unsigned int ustl_cmd_api_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_str_api_fifo_uf(unsigned int ustl_str_api_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_rd_di_fifo_uf(unsigned int ustl_rd_di_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_wr_di_fifo_uf(unsigned int ustl_wr_di_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_wr_di_ctrl_fifo_uf(unsigned int ustl_wr_di_ctrl_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_ackstr_fifo_uf(unsigned int ustl_ackstr_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_hdr_fifo_uf(unsigned int ustl_rsp_api_hdr_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_dat_fifo_uf(unsigned int ustl_rsp_api_dat_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_cd_fifo_uf(unsigned int ustl_rsp_api_cd_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_crc_fifo_uf(unsigned int ustl_rsp_api_crc_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_cs_fifo_uf(unsigned int ustl_rsp_api_cs_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_nptr_fifo_uf(unsigned int ustl_rsp_api_nptr_fifo_uf); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_addr(unsigned int ustlwr_fifo_mem_err_addr); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_cerr(unsigned int ustlwr_fifo_mem_err_cerr); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_ucerr(unsigned int ustlwr_fifo_mem_err_ucerr); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_cnt(unsigned int ustlwr_fifo_mem_err_cnt); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_addr(unsigned int ustlstr_fifo_mem_err_addr); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_cerr(unsigned int ustlstr_fifo_mem_err_cerr); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_ucerr(unsigned int ustlstr_fifo_mem_err_ucerr); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_cnt(unsigned int ustlstr_fifo_mem_err_cnt); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_addr(unsigned int ustlrsp_fifo_mem_err_addr); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_cerr(unsigned int ustlrsp_fifo_mem_err_cerr); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_ucerr(unsigned int ustlrsp_fifo_mem_err_ucerr); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_cnt(unsigned int ustlrsp_fifo_mem_err_cnt); +int iSetCDT_PSH_FIFO_STA_psh_ctrl_fifo1_sta(unsigned int upsh_ctrl_fifo1_sta); +int iSetCDT_PSH_FIFO_STA_psh_dat_fifo1_sta(unsigned int upsh_dat_fifo1_sta); +int iSetCDT_FIFO_ERR_cdt_psh_fifo_of_err(unsigned int ucdt_psh_fifo_of_err); +int iSetCDT_FIFO_ERR_cdt_psh_fifo_uf_err(unsigned int ucdt_psh_fifo_uf_err); +int iSetCDT_CRDT_STA_cdt_crdt_cnt(unsigned int ucdt_crdt_cnt); +int iSetCDT_CRDT_STA_cdt_crdt_of_err(unsigned int ucdt_crdt_of_err); +int iSetCDT_CRDT_STA_cdt_crdt_uf_err(unsigned int ucdt_crdt_uf_err); +int iSetCDT_CRDT_STA_geneve_flowpac_ofs_err(unsigned int ugeneve_flowpac_ofs_err); +int iSetSTLIQ_PKT_PSH_CNT_stliq_pkt_psh_cnt(unsigned int ustliq_pkt_psh_cnt); +int iSetSTLIQ_MSG_PSH_CNT_stliq_msg_psh_cnt(unsigned int ustliq_msg_psh_cnt); +int iSetFLOWPAC_PSH_REQ_CNT_flowpac_psh_req_cnt(unsigned int uflowpac_psh_req_cnt); +int iSetNONFLOWPAC_PSH_REQ_CNT_nonflowpac_psh_req_cnt(unsigned int unonflowpac_psh_req_cnt); +int iSetSTLIQ_PSH_FIFO_STA_stliq_psh_fifo_sta(unsigned int ustliq_psh_fifo_sta); +int iSetROB_PSH_FIFO_STA_rob_psh_fifo_sta(unsigned int urob_psh_fifo_sta); +int iSetRX_EPD_CNT_rx_epd_cnt(unsigned int urx_epd_cnt); +int iSetRX_CHN_EPD_CNT_rx_chn_epd_cnt(unsigned int urx_chn_epd_cnt); +int iSetTX_EPD_CNT_tx_epd_cnt(unsigned int utx_epd_cnt); +int iSetTX_CHN_EPD_CNT_tx_chn_epd_cnt(unsigned int utx_chn_epd_cnt); +int iSetTXMAC_CHN_TSO12_EPD_CNT_txmac_chn_tso12_epd_cnt(unsigned int utxmac_chn_tso12_epd_cnt); +int iSetDRP_REQ_CNT_drp_req_cnt(unsigned int udrp_req_cnt); +int iSetRX_TSO3_DRP_CNT_rx_tso3_prls_cnt(unsigned int urx_tso3_prls_cnt); +int iSetRX_TSO3_DRP_CNT_rx_tso3_drp_cnt(unsigned int urx_tso3_drp_cnt); +int iSetTX_TSO3_DRP_CNT_tx_tso3_prls_cnt(unsigned int utx_tso3_prls_cnt); +int iSetTX_TSO3_DRP_CNT_tx_tso3_drp_cnt(unsigned int utx_tso3_drp_cnt); +int iSetDRP_EOP_CNT_drp_eop_cnt(unsigned int udrp_eop_cnt); +int iSetRX_EPD_FIFO_STA_rx_epd_fifo_sta(unsigned int urx_epd_fifo_sta); +int iSetTX_EPD_FIFO_STA_tx_epd_fifo_sta(unsigned int utx_epd_fifo_sta); +int iSetNDRP_FIFO_STA_ndrp_fifo_sta(unsigned int undrp_fifo_sta); +int iSetDRP_RXRLS_FIFO_STA_drp_rxrls_fifo_sta(unsigned int udrp_rxrls_fifo_sta); +int iSetDRP_TXRLS_FIFO_STA_drp_txrls_fifo_sta(unsigned int udrp_txrls_fifo_sta); +int iSetFDRP_FIFO_STA_fdrp_fifo_sta(unsigned int ufdrp_fifo_sta); +int iSetFTSO_DRP_REQ_CNT_ftso_drp_req_cnt(unsigned int uftso_drp_req_cnt); +int iSetCOQ_FIFO_OF_ERR_rx_epd_fifo_of_err(unsigned int urx_epd_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_tx_epd_fifo_of_err(unsigned int utx_epd_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_ndrp_fifo_of_err(unsigned int undrp_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_drp_txrls_fifo_of_err(unsigned int udrp_txrls_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_drp_rxrls_fifo_of_err(unsigned int udrp_rxrls_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_fdrp_fifo_of_err(unsigned int ufdrp_fifo_of_err); +int iSetCOQ_FIFO_UF_ERR_rx_epd_fifo_uf_err(unsigned int urx_epd_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_tx_epd_fifo_uf_err(unsigned int utx_epd_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_ndrp_fifo_uf_err(unsigned int undrp_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_drp_txrls_fifo_uf_err(unsigned int udrp_txrls_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_drp_rxrls_fifo_uf_err(unsigned int udrp_rxrls_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_fdrp_fifo_uf_err(unsigned int ufdrp_fifo_uf_err); +int iSetCOQ_ERR_rx_cpi_chn_err(unsigned int urx_cpi_chn_err); +int iSetCOQ_ERR_rx_pkt_mode_err(unsigned int urx_pkt_mode_err); +int iSetCOQ_ERR_rx_pcnum_srch_err(unsigned int urx_pcnum_srch_err); +int iSetCOQ_ERR_tx_lb_chn_err(unsigned int utx_lb_chn_err); +int iSetCOQ_ERR_tx_pkt_mode_err(unsigned int utx_pkt_mode_err); +int iSetCOQ_ERR_tx_pcnum_srch_err(unsigned int utx_pcnum_srch_err); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chnsge_crdt_cnt(unsigned int ucpi_chnsge_crdt_cnt); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chnsge_crdt_af(unsigned int ucpi_chnsge_crdt_af); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chndat_crdt_cnt(unsigned int ucpi_chndat_crdt_cnt); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chndat_crdt_af(unsigned int ucpi_chndat_crdt_af); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostsge_crdt_cnt(unsigned int ucpi_hostsge_crdt_cnt); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostsge_crdt_af(unsigned int ucpi_hostsge_crdt_af); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostdat_crdt_cnt(unsigned int ucpi_hostdat_crdt_cnt); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostdat_crdt_af(unsigned int ucpi_hostdat_crdt_af); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrsge_crdt_cnt(unsigned int ucpi_shrsge_crdt_cnt); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrsge_crdt_af(unsigned int ucpi_shrsge_crdt_af); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrdat_crdt_cnt(unsigned int ucpi_shrdat_crdt_cnt); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrdat_crdt_af(unsigned int ucpi_shrdat_crdt_af); +int iSetRX_CPI_HOST_WCRDT_STA_cpi_host_wsge_crdt_cnt(unsigned int ucpi_host_wsge_crdt_cnt); +int iSetRX_CPI_HOST_WCRDT_STA_cpb_pqm_hostsge_crdt_bp(unsigned int ucpb_pqm_hostsge_crdt_bp); +int iSetRX_CPI_HOST_WCRDT_STA_cpi_host_wdat_crdt_cnt(unsigned int ucpi_host_wdat_crdt_cnt); +int iSetRX_CPI_HOST_WCRDT_STA_cpb_pqm_hostdat_crdt_bp(unsigned int ucpb_pqm_hostdat_crdt_bp); +int iSetRXLB_CHN_CRDT_STA_rxlb_chn_crdt_cnt(unsigned int urxlb_chn_crdt_cnt); +int iSetRXLB_CHN_CRDT_STA_rxlb_chn_crdt_af(unsigned int urxlb_chn_crdt_af); +int iSetRX_IDX_CRDT_STA_rx_idx_crdt_cnt(unsigned int urx_idx_crdt_cnt); +int iSetRX_IDX_CRDT_STA_rx_idx_crdt_af(unsigned int urx_idx_crdt_af); +int iSetRXLB_FP_BMP_STA_rxlb_fp_bmp_fill(unsigned int urxlb_fp_bmp_fill); +int iSetRXPD_FIFO_EMPTY_STA_0_rxpd_fifo_empty_sta_0(unsigned int urxpd_fifo_empty_sta_0); +int iSetRXPD_FIFO_EMPTY_STA_1_rxpd_fifo_empty_sta_1(unsigned int urxpd_fifo_empty_sta_1); +int iSetRXPD_FIFO_EMPTY_STA_2_rxpd_fifo_empty_sta_2(unsigned int urxpd_fifo_empty_sta_2); +int iSetRXPD_FIFO_FILL_STA_rxpd_fifo_fill_sta(unsigned int urxpd_fifo_fill_sta); +int iSetRXPD_PRO_FSM_STA_rxpd_pro_fsm_sta(unsigned int urxpd_pro_fsm_sta); +int iSetRX_CRDT_OF_ERR_0_rx_idx_crdt_of_err(unsigned int urx_idx_crdt_of_err); +int iSetRX_CRDT_OF_ERR_0_rxlb_chn_crdt_of_err(unsigned int urxlb_chn_crdt_of_err); +int iSetRX_CRDT_OF_ERR_0_cpi_chn_dat_crdt_of_err(unsigned int ucpi_chn_dat_crdt_of_err); +int iSetRX_CRDT_OF_ERR_1_cpi_chn_sge_crdt_of_err(unsigned int ucpi_chn_sge_crdt_of_err); +int iSetRX_CRDT_UF_ERR_0_rx_idx_crdt_uf_err(unsigned int urx_idx_crdt_uf_err); +int iSetRX_CRDT_UF_ERR_0_rxlb_chn_crdt_uf_err(unsigned int urxlb_chn_crdt_uf_err); +int iSetRX_CRDT_UF_ERR_0_cpi_chn_dat_crdt_uf_err(unsigned int ucpi_chn_dat_crdt_uf_err); +int iSetRX_CRDT_UF_ERR_1_cpi_chn_sge_crdt_uf_err(unsigned int ucpi_chn_sge_crdt_uf_err); +int iSetRXPD_FIFO_OF_ERR_0_rxpd_fifo_of_err_0(unsigned int urxpd_fifo_of_err_0); +int iSetRXPD_FIFO_OF_ERR_1_rxpd_fifo_of_err_1(unsigned int urxpd_fifo_of_err_1); +int iSetRXPD_FIFO_OF_ERR_2_rxpd_fifo_of_err_2(unsigned int urxpd_fifo_of_err_2); +int iSetRXPD_FIFO_OF_ERR_2_rxlb_fp_fifo_of_err(unsigned int urxlb_fp_fifo_of_err); +int iSetRXPD_FIFO_OF_ERR_2_rx_tso3_rls_fifo_of_err(unsigned int urx_tso3_rls_fifo_of_err); +int iSetRXPD_FIFO_UF_ERR_0_rxpd_fifo_uf_err_0(unsigned int urxpd_fifo_uf_err_0); +int iSetRXPD_FIFO_UF_ERR_1_rxpd_fifo_uf_err_1(unsigned int urxpd_fifo_uf_err_1); +int iSetRXPD_FIFO_UF_ERR_2_rxpd_fifo_uf_err_2(unsigned int urxpd_fifo_uf_err_2); +int iSetRXPD_FIFO_UF_ERR_2_rxlb_fp_fifo_uf_err(unsigned int urxlb_fp_fifo_uf_err); +int iSetRXPD_FIFO_UF_ERR_2_rx_tso3_rls_fifo_uf_err(unsigned int urx_tso3_rls_fifo_uf_err); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_addr(unsigned int urxlb_pd_mem_err_addr); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_cerr(unsigned int urxlb_pd_mem_err_cerr); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_ucerr(unsigned int urxlb_pd_mem_err_ucerr); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_cnt(unsigned int urxlb_pd_mem_err_cnt); +int iSetCPB_RX_ERR_0_rx_chn_pd_pptr_err(unsigned int urx_chn_pd_pptr_err); +int iSetCPB_RX_ERR_1_rx_chn_pd_pktmod_err(unsigned int urx_chn_pd_pktmod_err); +int iSetCPB_RX_ERR_2_rx_chn_ret_pcnum_err(unsigned int urx_chn_ret_pcnum_err); +int iSetCPB_RX_ERR_3_rx_chn_tso2_err(unsigned int urx_chn_tso2_err); +int iSetCPB_RX_ERR_3_rx_chn_tso2_num_err(unsigned int urx_chn_tso2_num_err); +int iSetCPB_RX_ERR_3_rx_chn_tso2_cmd_cnum_err0(unsigned int urx_chn_tso2_cmd_cnum_err0); +int iSetCPB_RX_ERR_3_rx_chn_tso2_cmd_cnum_err1(unsigned int urx_chn_tso2_cmd_cnum_err1); +int iSetCPB_RX_ERR_3_rx_chn_tso2_cmd_cnum_err2(unsigned int urx_chn_tso2_cmd_cnum_err2); +int iSetCPB_RX_ERR_4_rx_chn_lro1_err(unsigned int urx_chn_lro1_err); +int iSetCPB_RX_ERR_4_rx_chn_lro1_num_err(unsigned int urx_chn_lro1_num_err); +int iSetCPB_RX_ERR_4_rx_chn_lro1_cmd_cnum_err(unsigned int urx_chn_lro1_cmd_cnum_err); +int iSetCPB_RX_ERR_5_rx_chn_lro2_err(unsigned int urx_chn_lro2_err); +int iSetCPB_RX_ERR_5_rx_chn_lro2_num_err(unsigned int urx_chn_lro2_num_err); +int iSetCPB_RX_ERR_5_rx_chn_lro2_cmd_cnum_err0(unsigned int urx_chn_lro2_cmd_cnum_err0); +int iSetCPB_RX_ERR_5_rx_chn_lro2_cmd_cnum_err1(unsigned int urx_chn_lro2_cmd_cnum_err1); +int iSetCPB_RX_ERR_5_rx_chn_lro2_cmd_cnum_err2(unsigned int urx_chn_lro2_cmd_cnum_err2); +int iSetRX_TSO3_RLS_FIFO_STA_rx_tso3_rls_fifo_sta(unsigned int urx_tso3_rls_fifo_sta); + +/* Define the union csr_cpb_indir_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_indir_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_indir_dat_u; + +/* Define the union csr_cir_alc_pro_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_pro_wt_0 : 4; /* [3:0] */ + u32 cir_alc_pro_wt_1 : 4; /* [7:4] */ + u32 cir_alc_pro_wt_2 : 4; /* [11:8] */ + u32 rsv_0 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_pro_wt_u; + +/* Define the union csr_cir_rpci_pro_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_rpci_pro_wt_0 : 4; /* [3:0] */ + u32 cir_rpci_pro_wt_1 : 4; /* [7:4] */ + u32 cir_rpci_pro_wt_2 : 4; /* [11:8] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpci_pro_wt_u; + +/* Define the union csr_cir_alc_mac_ncsi_port_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_mac_port_wt_4_0 : 4; /* [3:0] */ + u32 cir_alc_mac_port_wt_5_1 : 4; /* [7:4] */ + u32 cir_alc_mac_port_wt_6_2 : 4; /* [11:8] */ + u32 cir_alc_mac_port_wt_7_3 : 4; /* [15:12] */ + u32 cir_alc_ncsi_port_wt : 4; /* [19:16] */ + u32 rsv_2 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_mac_ncsi_port_wt_u; + +/* Define the union csr_cir_data_in_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_data_in_fifo_af_th_mac03 : 6; /* [5:0] */ + u32 rsv_3 : 2; /* [7:6] */ + u32 cir_data_in_fifo_af_th_mac47 : 6; /* [13:8] */ + u32 rsv_4 : 2; /* [15:14] */ + u32 cir_data_in_fifo_af_th_lprts : 6; /* [21:16] */ + u32 rsv_5 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_data_in_fifo_af_th_u; + +/* Define the union csr_cir_alc_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_fifo_af_th_mac03 : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 cir_alc_fifo_af_th_mac47 : 5; /* [12:8] */ + u32 rsv_7 : 3; /* [15:13] */ + u32 cir_alc_fifo_af_th_lprts : 5; /* [20:16] */ + u32 rsv_8 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_fifo_af_th_u; + +/* Define the union csr_cir_rpci_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_rpci_fifo_af_th_mac03 : 5; /* [4:0] */ + u32 rsv_9 : 3; /* [7:5] */ + u32 cir_rpci_fifo_af_th_mac47 : 5; /* [12:8] */ + u32 rsv_10 : 3; /* [15:13] */ + u32 cir_rpci_fifo_af_th_lprts : 5; /* [20:16] */ + u32 rsv_11 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpci_fifo_af_th_u; + +/* Define the union csr_cir_alc_rp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_rp_th_mac03 : 7; /* [6:0] */ + u32 rsv_12 : 1; /* [7] */ + u32 cir_alc_rp_th_mac47 : 7; /* [14:8] */ + u32 rsv_13 : 1; /* [15] */ + u32 cir_alc_rp_th_lprts : 7; /* [22:16] */ + u32 rsv_14 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_rp_th_u; + +/* Define the union csr_cir_data_in_fifo_drop_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_data_in_fifo_drop_th_mac03 : 6; /* [5:0] */ + u32 rsv_15 : 2; /* [7:6] */ + u32 cir_data_in_fifo_drop_th_mac47 : 6; /* [13:8] */ + u32 rsv_16 : 2; /* [15:14] */ + u32 cir_data_in_fifo_drop_th_lprts : 6; /* [21:16] */ + u32 rsv_17 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_data_in_fifo_drop_th_u; + +/* Define the union csr_cir_ipsurx_bp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_ipsurx_bp_en : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_ipsurx_bp_en_u; + +/* Define the union csr_cir_alc_shp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_shp_en : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_shp_en_u; + +/* Define the union csr_cpt_mac03_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_mac03_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_mac03_ts_u; + +/* Define the union csr_cpt_mac47_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_mac47_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_mac47_ts_u; + +/* Define the union csr_cpt_maclb_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_maclb_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_maclb_ts_u; + +/* Define the union csr_cpt_ts_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_ts_len : 5; /* [4:0] */ + u32 rsv_20 : 3; /* [7:5] */ + u32 cpt_ts_cfg_done : 1; /* [8] */ + u32 rsv_21 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_ts_cfg_u; + +/* Define the union csr_cpt_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_fifo_crdt_init_dat : 6; /* [5:0] */ + u32 rsv_22 : 2; /* [7:6] */ + u32 cpt_fifo_crdt_init : 1; /* [8] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_crdt_init_u; + +/* Define the union csr_cpt_dealc_tx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_tx_af_th : 7; /* [6:0] */ + u32 rsv_24 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_tx_af_th_u; + +/* Define the union csr_cpt_dealc_rx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_rx_af_th : 7; /* [6:0] */ + u32 rsv_25 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_rx_af_th_u; + +/* Define the union csr_cpt_prls_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_prls_af_th : 7; /* [6:0] */ + u32 rsv_26 : 1; /* [7] */ + u32 cpt_pro_prls_fifo_af_th : 5; /* [12:8] */ + u32 rsv_27 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_prls_af_th_u; + +/* Define the union csr_cpt_col_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_deast_col_th : 7; /* [6:0] */ + u32 rsv_28 : 1; /* [7] */ + u32 cpt_ast_col_th : 7; /* [14:8] */ + u32 rsv_29 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_col_th_u; + +/* Define the union csr_cpt_pro_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_af_th : 5; /* [4:0] */ + u32 rsv_30 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_di_fifo_af_th_u; + +/* Define the union csr_cpt_pro_dealc_tx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_tx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_31 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_tx_fifo_af_th_u; + +/* Define the union csr_cpt_pro_dealc_rx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_rx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_32 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_rx_fifo_af_th_u; + +/* Define the union csr_cpt_pro_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dat_fifo_crdt_init_dat : 5; /* [4:0] */ + u32 rsv_33 : 3; /* [7:5] */ + u32 cpt_pro_dat_fifo_crdt_init : 1; /* [8] */ + u32 rsv_34 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_fifo_crdt_init_u; + +/* Define the union csr_cpt_pro_dealc_rp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_rp_th : 7; /* [6:0] */ + u32 rsv_35 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_rp_th_u; + +/* Define the union csr_cpt_out_err_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_petx_err_en : 1; /* [0] */ + u32 cpb_petx_ftso_err_en : 1; /* [1] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_err_en_u; + +/* Define the union csr_cpt_txlb_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_txlb_en : 1; /* [0] */ + u32 rsv_37 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_txlb_en_u; + +/* Define the union csr_tx_crr0_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx0_crr_vld : 8; /* [7:0] */ + u32 cpbtx0_crr_len : 3; /* [10:8] */ + u32 rsv_38 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr0_en_u; + +/* Define the union csr_tx_crr0_pid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx0_crr_pid0 : 3; /* [2:0] */ + u32 rsv_39 : 1; /* [3] */ + u32 cpbtx0_crr_pid1 : 3; /* [6:4] */ + u32 rsv_40 : 1; /* [7] */ + u32 cpbtx0_crr_pid2 : 3; /* [10:8] */ + u32 rsv_41 : 1; /* [11] */ + u32 cpbtx0_crr_pid3 : 3; /* [14:12] */ + u32 rsv_42 : 1; /* [15] */ + u32 cpbtx0_crr_pid4 : 3; /* [18:16] */ + u32 rsv_43 : 1; /* [19] */ + u32 cpbtx0_crr_pid5 : 3; /* [22:20] */ + u32 rsv_44 : 1; /* [23] */ + u32 cpbtx0_crr_pid6 : 3; /* [26:24] */ + u32 rsv_45 : 1; /* [27] */ + u32 cpbtx0_crr_pid7 : 3; /* [30:28] */ + u32 rsv_46 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr0_pid_u; + +/* Define the union csr_tx_crr1_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx1_crr_vld : 8; /* [7:0] */ + u32 cpbtx1_crr_len : 3; /* [10:8] */ + u32 rsv_47 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr1_en_u; + +/* Define the union csr_tx_crr1_pid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx1_crr_pid0 : 3; /* [2:0] */ + u32 rsv_48 : 1; /* [3] */ + u32 cpbtx1_crr_pid1 : 3; /* [6:4] */ + u32 rsv_49 : 1; /* [7] */ + u32 cpbtx1_crr_pid2 : 3; /* [10:8] */ + u32 rsv_50 : 1; /* [11] */ + u32 cpbtx1_crr_pid3 : 3; /* [14:12] */ + u32 rsv_51 : 1; /* [15] */ + u32 cpbtx1_crr_pid4 : 3; /* [18:16] */ + u32 rsv_52 : 1; /* [19] */ + u32 cpbtx1_crr_pid5 : 3; /* [22:20] */ + u32 rsv_53 : 1; /* [23] */ + u32 cpbtx1_crr_pid6 : 3; /* [26:24] */ + u32 rsv_54 : 1; /* [27] */ + u32 cpbtx1_crr_pid7 : 3; /* [30:28] */ + u32 rsv_55 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr1_pid_u; + +/* Define the union csr_tx_crr2_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx2_crr_vld : 8; /* [7:0] */ + u32 cpbtx2_crr_len : 3; /* [10:8] */ + u32 rsv_56 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr2_en_u; + +/* Define the union csr_tx_crr2_pid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx2_crr_pid0 : 2; /* [1:0] */ + u32 rsv_57 : 2; /* [3:2] */ + u32 cpbtx2_crr_pid1 : 2; /* [5:4] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 cpbtx2_crr_pid2 : 2; /* [9:8] */ + u32 rsv_59 : 2; /* [11:10] */ + u32 cpbtx2_crr_pid3 : 2; /* [13:12] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 cpbtx2_crr_pid4 : 2; /* [17:16] */ + u32 rsv_61 : 2; /* [19:18] */ + u32 cpbtx2_crr_pid5 : 2; /* [21:20] */ + u32 rsv_62 : 2; /* [23:22] */ + u32 cpbtx2_crr_pid6 : 2; /* [25:24] */ + u32 rsv_63 : 2; /* [27:26] */ + u32 cpbtx2_crr_pid7 : 2; /* [29:28] */ + u32 rsv_64 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr2_pid_u; + +/* Define the union csr_tx_chn_crdt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_0 : 7; /* [6:0] */ + u32 rsv_65 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg0_u; + +/* Define the union csr_tx_chn_crdt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_1 : 7; /* [6:0] */ + u32 rsv_66 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg1_u; + +/* Define the union csr_tx_chn_crdt_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_2 : 7; /* [6:0] */ + u32 rsv_67 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg2_u; + +/* Define the union csr_tx_chn_crdt_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_3 : 7; /* [6:0] */ + u32 rsv_68 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg3_u; + +/* Define the union csr_tx_chn_crdt_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_4 : 7; /* [6:0] */ + u32 rsv_69 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg4_u; + +/* Define the union csr_tx_chn_crdt_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_5 : 7; /* [6:0] */ + u32 rsv_70 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg5_u; + +/* Define the union csr_tx_chn_crdt_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_6 : 7; /* [6:0] */ + u32 rsv_71 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg6_u; + +/* Define the union csr_tx_chn_crdt_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_7 : 7; /* [6:0] */ + u32 rsv_72 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg7_u; + +/* Define the union csr_tx_chn_crdt_cfg8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_8 : 7; /* [6:0] */ + u32 rsv_73 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg8_u; + +/* Define the union csr_tx_chn_crdt_cfg9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_9 : 7; /* [6:0] */ + u32 rsv_74 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg9_u; + +/* Define the union csr_tx_chn_crdt_cfg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_10 : 7; /* [6:0] */ + u32 rsv_75 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg10_u; + +/* Define the union csr_cpb_tx_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_idx_crdt : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 tx_dat_prealc_crdt : 3; /* [10:8] */ + u32 rsv_77 : 5; /* [15:11] */ + u32 tx_crdt_bp_gap : 4; /* [19:16] */ + u32 rsv_78 : 4; /* [23:20] */ + u32 petx_idx_bp_gap : 4; /* [27:24] */ + u32 rsv_79 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_crdt_cfg_u; + +/* Define the union csr_txlb_pd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txlp_pd_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_80 : 2; /* [7:6] */ + u32 txlp_pd_fifo_af_th : 6; /* [13:8] */ + u32 rsv_81 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txlb_pd_fifo_cfg_u; + +/* Define the union csr_tx_cos_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_cos_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 tx_cos_fifo_af_th : 6; /* [13:8] */ + u32 rsv_83 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_cos_fifo_cfg_u; + +/* Define the union csr_ftso_rls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ftso_rls_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_84 : 2; /* [7:6] */ + u32 ftso_rls_fifo_af_th : 6; /* [13:8] */ + u32 rsv_85 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ftso_rls_fifo_cfg_u; + +/* Define the union csr_tx_idx_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_idx_req_wt0 : 3; /* [2:0] */ + u32 rsv_86 : 1; /* [3] */ + u32 cpt_idx_req_wt1 : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 cpt_idx_req_wt2 : 3; /* [10:8] */ + u32 rsv_88 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_idx_wt_u; + +/* Define the union csr_mag_bp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpb_bp_en : 1; /* [0] */ + u32 rsv_89 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_bp_en_u; + +/* Define the union csr_tx_tso3_rls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tso3_rls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_90 : 1; /* [7] */ + u32 tx_tso3_rls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_91 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tso3_rls_fifo_cfg_u; + +/* Define the union csr_cir_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_92 : 5; /* [15:11] */ + u32 cir_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_93 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_dat_in_fifo_sta_u; + +/* Define the union csr_cir_rpt_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_fifo_sta : 11; /* [10:0] */ + u32 rsv_94 : 5; /* [15:11] */ + u32 cir_rpt_pci_sta : 11; /* [26:16] */ + u32 rsv_95 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpt_fifo_sta_u; + +/* Define the union csr_cir_in_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_in_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_in_pkt_sop_cnt_u; + +/* Define the union csr_cir_in_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_in_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_97 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_in_pkt_eop_cnt_u; + +/* Define the union csr_cir_in_port_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_in_port_pkt_cnt : 16; /* [15:0] */ + u32 rsv_98 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_in_port_pkt_cnt_u; + +/* Define the union csr_cir_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_drp_pkt_cnt : 16; /* [15:0] */ + u32 rsv_99 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_drp_pkt_cnt_u; + +/* Define the union csr_cir_fifo_af_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_fifo_af_drp_pkt_cnt : 16; /* [15:0] */ + u32 rsv_100 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_af_drp_pkt_cnt_u; + +/* Define the union csr_cir_bmu_af_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_bmu_af_drp_pkt_cnt : 16; /* [15:0] */ + u32 rsv_101 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_bmu_af_drp_pkt_cnt_u; + +/* Define the union csr_cir_fifo_af_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_fifo_af_cnt : 16; /* [15:0] */ + u32 rsv_102 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_af_cnt_u; + +/* Define the union csr_cir_cut_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_cut_pkt_cnt : 16; /* [15:0] */ + u32 rsv_103 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_cut_pkt_cnt_u; + +/* Define the union csr_cir_rpt_iq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_rpt_iq_cnt : 16; /* [15:0] */ + u32 rsv_104 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpt_iq_cnt_u; + +/* Define the union csr_cir_iq_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_iq_bp_cnt : 16; /* [15:0] */ + u32 rsv_105 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_iq_bp_cnt_u; + +/* Define the union csr_cir_sport_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_sport_err : 1; /* [0] */ + u32 rsv_106 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_sport_err_u; + +/* Define the union csr_cir_alc_prm_cnum_full_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_prm_cnum_full_err : 1; /* [0] */ + u32 rsv_107 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_prm_cnum_full_err_u; + +/* Define the union csr_cir_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_di_fifo_uf : 3; /* [2:0] */ + u32 rsv_108 : 1; /* [3] */ + u32 cir_di_ctrl_fifo_uf : 3; /* [6:4] */ + u32 rsv_109 : 1; /* [7] */ + u32 cir_rpt_pci_uf : 3; /* [10:8] */ + u32 rsv_110 : 1; /* [11] */ + u32 cir_alc_fifo_uf : 3; /* [14:12] */ + u32 rsv_111 : 1; /* [15] */ + u32 cir_di_fifo_ov : 3; /* [18:16] */ + u32 rsv_112 : 1; /* [19] */ + u32 cir_di_ctrl_fifo_ov : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 cir_rpt_pci_ov : 3; /* [26:24] */ + u32 rsv_114 : 1; /* [27] */ + u32 cir_alc_fifo_ov : 3; /* [30:28] */ + u32 rsv_115 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_err_u; + +/* Define the union csr_cir_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_fifo_mem_err_addr : 6; /* [5:0] */ + u32 rsv_116 : 6; /* [11:6] */ + u32 cir_fifo_mem_err_cerr : 1; /* [12] */ + u32 cir_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_117 : 2; /* [15:14] */ + u32 cir_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_ram_err_u; + +/* Define the union csr_cir_prm_bp_his_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_0_u; + +/* Define the union csr_cir_prm_bp_his_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_1_u; + +/* Define the union csr_cir_prm_bp_his_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_2_u; + +/* Define the union csr_cir_prm_bp_his_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_3_u; + +/* Define the union csr_cir_prm_bp_his_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_4 : 9; /* [8:0] */ + u32 rsv_118 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_4_u; + +/* Define the union csr_cpt_pro_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_sta : 11; /* [10:0] */ + u32 rsv_119 : 5; /* [15:11] */ + u32 cpt_pro_prls_fifo_sta : 9; /* [24:16] */ + u32 rsv_120 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dat_in_fifo_sta_u; + +/* Define the union csr_cpt_pro_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_121 : 5; /* [15:11] */ + u32 cpt_pro_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_122 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_fifo_sta_u; + +/* Define the union csr_cpt_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_123 : 5; /* [15:11] */ + u32 cpt_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_124 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_fifo_sta_u; + +/* Define the union csr_cpt_prls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_prls_fifo_sta : 11; /* [10:0] */ + u32 rsv_125 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_prls_fifo_sta_u; + +/* Define the union csr_cpt_dat_out_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dat_out_fifo_sta : 11; /* [10:0] */ + u32 rsv_126 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dat_out_fifo_sta_u; + +/* Define the union csr_cpt_out_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_out_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_pkt_sop_cnt_u; + +/* Define the union csr_cpt_out_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_out_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_128 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_pkt_eop_cnt_u; + +/* Define the union csr_cpt_out_chnl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_out_chnl_pkt_cnt : 16; /* [15:0] */ + u32 rsv_129 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_chnl_pkt_cnt_u; + +/* Define the union csr_cpt_sof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_sof_msm_info : 28; /* [27:0] */ + u32 rsv_130 : 3; /* [30:28] */ + u32 cpt_sof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_sof_msm_u; + +/* Define the union csr_cpt_eof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_eof_msm_info : 28; /* [27:0] */ + u32 rsv_131 : 3; /* [30:28] */ + u32 cpt_eof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_eof_msm_u; + +/* Define the union csr_cpt_dealc_tx_bp_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_tx_bp_tm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_tx_bp_tm_u; + +/* Define the union csr_cpt_dealc_rx_bp_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_rx_bp_tm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_rx_bp_tm_u; + +/* Define the union csr_cpt_ts_cfg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_ts_cfg_err : 1; /* [0] */ + u32 rsv_132 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_ts_cfg_err_u; + +/* Define the union csr_cpt_fifo_ov_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_ov : 3; /* [2:0] */ + u32 rsv_133 : 1; /* [3] */ + u32 cpt_pro_dealc_tx_fifo_ov : 3; /* [6:4] */ + u32 rsv_134 : 1; /* [7] */ + u32 cpt_pro_dealc_rx_fifo_ov : 3; /* [10:8] */ + u32 rsv_135 : 1; /* [11] */ + u32 cpt_dat_out_fifo_ov : 3; /* [14:12] */ + u32 rsv_136 : 1; /* [15] */ + u32 cpt_dealc_tx_fifo_ov : 1; /* [16] */ + u32 cpt_dealc_rx_fifo_ov : 1; /* [17] */ + u32 cpt_prls_fifo_ov : 1; /* [18] */ + u32 cpt_pro_prls_fifo_ov : 3; /* [21:19] */ + u32 rsv_137 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_fifo_ov_err_u; + +/* Define the union csr_cpt_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_uf : 3; /* [2:0] */ + u32 rsv_138 : 1; /* [3] */ + u32 cpt_pro_dealc_tx_fifo_uf : 3; /* [6:4] */ + u32 rsv_139 : 1; /* [7] */ + u32 cpt_pro_dealc_rx_fifo_uf : 3; /* [10:8] */ + u32 rsv_140 : 1; /* [11] */ + u32 cpt_dat_out_fifo_uf : 3; /* [14:12] */ + u32 rsv_141 : 1; /* [15] */ + u32 cpt_dealc_tx_fifo_uf : 1; /* [16] */ + u32 cpt_dealc_rx_fifo_uf : 1; /* [17] */ + u32 cpt_prls_fifo_uf : 1; /* [18] */ + u32 cpt_pro_prls_fifo_uf : 3; /* [21:19] */ + u32 rsv_142 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_fifo_uf_err_u; + +/* Define the union csr_cpt_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_fifo_mem_err_addr : 4; /* [3:0] */ + u32 rsv_143 : 8; /* [11:4] */ + u32 cpt_fifo_mem_err_cerr : 1; /* [12] */ + u32 cpt_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_144 : 2; /* [15:14] */ + u32 cpt_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_fifo_ram_err_u; + +/* Define the union csr_tx_chn_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_cnt : 7; /* [6:0] */ + u32 rsv_145 : 1; /* [7] */ + u32 tx_chn_crdt_af : 1; /* [8] */ + u32 rsv_146 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_sta_u; + +/* Define the union csr_tx_idx_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_idx_crdt_cnt : 6; /* [5:0] */ + u32 rsv_147 : 2; /* [7:6] */ + u32 tx_idx_crdt_af : 1; /* [8] */ + u32 rsv_148 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_idx_crdt_sta_u; + +/* Define the union csr_tx_fp_bmp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fp_bmp_fill : 8; /* [7:0] */ + u32 rsv_149 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_fp_bmp_sta_u; + +/* Define the union csr_txpd_fifo_empty_sta_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_empty_sta_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_empty_sta_0_u; + +/* Define the union csr_txpd_fifo_empty_sta_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_empty_sta_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_empty_sta_1_u; + +/* Define the union csr_txpd_fifo_empty_sta_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_empty_sta_2 : 3; /* [2:0] */ + u32 rsv_150 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_empty_sta_2_u; + +/* Define the union csr_txpd_fifo_fill_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_fill_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_fill_sta_u; + +/* Define the union csr_txpd_pro_fsm_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_pro_fsm_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_pro_fsm_sta_u; + +/* Define the union csr_mag_bp_sta_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpb_bp_sta_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_bp_sta_0_u; + +/* Define the union csr_mag_bp_sta_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpb_bp_sta_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_bp_sta_1_u; + +/* Define the union csr_tx_ftso_rls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ftsorls_fifo_sta_0 : 10; /* [9:0] */ + u32 rsv_151 : 6; /* [15:10] */ + u32 tx_ftsorls_fifo_sta_1 : 10; /* [25:16] */ + u32 rsv_152 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_ftso_rls_fifo_sta_u; + +/* Define the union csr_tx_tso3_rls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tso3_rls_fifo_sta : 11; /* [10:0] */ + u32 rsv_153 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tso3_rls_fifo_sta_u; + +/* Define the union csr_tx_crdt_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_idx_crdt_of_err : 1; /* [0] */ + u32 tx_chn_crdt_of_err : 11; /* [11:1] */ + u32 rsv_154 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crdt_of_err_u; + +/* Define the union csr_tx_crdt_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_idx_crdt_uf_err : 1; /* [0] */ + u32 tx_chn_crdt_uf_err : 11; /* [11:1] */ + u32 rsv_155 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crdt_uf_err_u; + +/* Define the union csr_txpd_fifo_of_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_of_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_of_err_0_u; + +/* Define the union csr_txpd_fifo_of_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_of_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_of_err_1_u; + +/* Define the union csr_txpd_fifo_of_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_of_err_2 : 3; /* [2:0] */ + u32 tx_fp_fifo_of_err : 8; /* [10:3] */ + u32 tx_tso3_rls_fifo_of_err : 3; /* [13:11] */ + u32 rsv_156 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_of_err_2_u; + +/* Define the union csr_txpd_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_uf_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_uf_err_0_u; + +/* Define the union csr_txpd_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_uf_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_uf_err_1_u; + +/* Define the union csr_txpd_fifo_uf_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_uf_err_2 : 3; /* [2:0] */ + u32 tx_fp_fifo_uf_err : 8; /* [10:3] */ + u32 tx_tso3_rls_fifo_uf_err : 3; /* [13:11] */ + u32 rsv_157 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_uf_err_2_u; + +/* Define the union csr_tx_ftso_rls_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ftso_rls_fifo_uf_err : 2; /* [1:0] */ + u32 tx_ftso_rls_fifo_of_err : 2; /* [3:2] */ + u32 rsv_158 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_ftso_rls_fifo_err_u; + +/* Define the union csr_tso_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tso_mem_err_addr : 12; /* [11:0] */ + u32 tso_mem_err_cerr : 1; /* [12] */ + u32 tso_mem_err_ucerr : 1; /* [13] */ + u32 rsv_159 : 2; /* [15:14] */ + u32 tso_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tso_ram_err_u; + +/* Define the union csr_tx_pd_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pd_mem_err_addr : 7; /* [6:0] */ + u32 rsv_160 : 5; /* [11:7] */ + u32 tx_pd_mem_err_cerr : 1; /* [12] */ + u32 tx_pd_mem_err_ucerr : 1; /* [13] */ + u32 rsv_161 : 2; /* [15:14] */ + u32 tx_pd_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pd_ram_err_u; + +/* Define the union csr_cpb_tx_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_pd_pptr_err : 11; /* [10:0] */ + u32 rsv_162 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_0_u; + +/* Define the union csr_cpb_tx_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_pd_pktmod_err : 11; /* [10:0] */ + u32 rsv_163 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_1_u; + +/* Define the union csr_cpb_tx_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_ret_pcnum_err : 11; /* [10:0] */ + u32 rsv_164 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_2_u; + +/* Define the union csr_cpb_tx_err_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_tso1_num_err : 11; /* [10:0] */ + u32 tx_chn_tso1_cmd_cnum_err : 11; /* [21:11] */ + u32 rsv_165 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_3_u; + +/* Define the union csr_cpb_tx_err_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_tso2_num_err : 11; /* [10:0] */ + u32 tx_chn_tso2_cmd_cnum_err : 11; /* [21:11] */ + u32 tx_chn_tso2_cmd_cnum_err0 : 1; /* [22] */ + u32 tx_chn_tso2_cmd_cnum_err1 : 1; /* [23] */ + u32 tx_chn_tso2_cmd_cnum_err2 : 1; /* [24] */ + u32 rsv_166 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_4_u; + +/* Define the union csr_cpb_tx_err_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_lro2_num_err : 11; /* [10:0] */ + u32 tx_chn_lro2_cmd_cnum_err : 11; /* [21:11] */ + u32 tx_chn_lro2_cmd_cnum_err0 : 1; /* [22] */ + u32 tx_chn_lro2_cmd_cnum_err1 : 1; /* [23] */ + u32 tx_chn_lro2_cmd_cnum_err2 : 1; /* [24] */ + u32 rsv_167 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_5_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cpb_indir_dat_u cpb_indir_dat[16]; /* 180 */ + volatile csr_cir_alc_pro_wt_u cir_alc_pro_wt; /* 400 */ + volatile csr_cir_rpci_pro_wt_u cir_rpci_pro_wt; /* 404 */ + volatile csr_cir_alc_mac_ncsi_port_wt_u cir_alc_mac_ncsi_port_wt; /* 408 */ + volatile csr_cir_data_in_fifo_af_th_u cir_data_in_fifo_af_th; /* 410 */ + volatile csr_cir_alc_fifo_af_th_u cir_alc_fifo_af_th; /* 414 */ + volatile csr_cir_rpci_fifo_af_th_u cir_rpci_fifo_af_th; /* 418 */ + volatile csr_cir_alc_rp_th_u cir_alc_rp_th; /* 41C */ + volatile csr_cir_data_in_fifo_drop_th_u cir_data_in_fifo_drop_th; /* 420 */ + volatile csr_cir_ipsurx_bp_en_u cir_ipsurx_bp_en; /* 424 */ + volatile csr_cir_alc_shp_en_u cir_alc_shp_en; /* 428 */ + volatile csr_cpt_mac03_ts_u cpt_mac03_ts; /* 700 */ + volatile csr_cpt_mac47_ts_u cpt_mac47_ts; /* 704 */ + volatile csr_cpt_maclb_ts_u cpt_maclb_ts; /* 708 */ + volatile csr_cpt_ts_cfg_u cpt_ts_cfg; /* 70C */ + volatile csr_cpt_crdt_init_u cpt_crdt_init; /* 710 */ + volatile csr_cpt_dealc_tx_af_th_u cpt_dealc_tx_af_th; /* 720 */ + volatile csr_cpt_dealc_rx_af_th_u cpt_dealc_rx_af_th; /* 724 */ + volatile csr_cpt_prls_af_th_u cpt_prls_af_th; /* 728 */ + volatile csr_cpt_col_th_u cpt_col_th; /* 72C */ + volatile csr_cpt_pro_di_fifo_af_th_u cpt_pro_di_fifo_af_th; /* 740 */ + volatile csr_cpt_pro_dealc_tx_fifo_af_th_u cpt_pro_dealc_tx_fifo_af_th; /* 744 */ + volatile csr_cpt_pro_dealc_rx_fifo_af_th_u cpt_pro_dealc_rx_fifo_af_th; /* 748 */ + volatile csr_cpt_pro_fifo_crdt_init_u cpt_pro_fifo_crdt_init; /* 74C */ + volatile csr_cpt_pro_dealc_rp_th_u cpt_pro_dealc_rp_th; /* 750 */ + volatile csr_cpt_out_err_en_u cpt_out_err_en; /* 754 */ + volatile csr_cpt_txlb_en_u cpt_txlb_en; /* 758 */ + volatile csr_tx_crr0_en_u tx_crr0_en; /* C00 */ + volatile csr_tx_crr0_pid_u tx_crr0_pid; /* C04 */ + volatile csr_tx_crr1_en_u tx_crr1_en; /* C08 */ + volatile csr_tx_crr1_pid_u tx_crr1_pid; /* C0C */ + volatile csr_tx_crr2_en_u tx_crr2_en; /* C10 */ + volatile csr_tx_crr2_pid_u tx_crr2_pid; /* C14 */ + volatile csr_tx_chn_crdt_cfg0_u tx_chn_crdt_cfg0; /* C20 */ + volatile csr_tx_chn_crdt_cfg1_u tx_chn_crdt_cfg1; /* C24 */ + volatile csr_tx_chn_crdt_cfg2_u tx_chn_crdt_cfg2; /* C28 */ + volatile csr_tx_chn_crdt_cfg3_u tx_chn_crdt_cfg3; /* C2C */ + volatile csr_tx_chn_crdt_cfg4_u tx_chn_crdt_cfg4; /* C30 */ + volatile csr_tx_chn_crdt_cfg5_u tx_chn_crdt_cfg5; /* C34 */ + volatile csr_tx_chn_crdt_cfg6_u tx_chn_crdt_cfg6; /* C38 */ + volatile csr_tx_chn_crdt_cfg7_u tx_chn_crdt_cfg7; /* C3C */ + volatile csr_tx_chn_crdt_cfg8_u tx_chn_crdt_cfg8; /* C40 */ + volatile csr_tx_chn_crdt_cfg9_u tx_chn_crdt_cfg9; /* C44 */ + volatile csr_tx_chn_crdt_cfg10_u tx_chn_crdt_cfg10; /* C48 */ + volatile csr_cpb_tx_crdt_cfg_u cpb_tx_crdt_cfg; /* C50 */ + volatile csr_txlb_pd_fifo_cfg_u txlb_pd_fifo_cfg; /* C60 */ + volatile csr_tx_cos_fifo_cfg_u tx_cos_fifo_cfg; /* C64 */ + volatile csr_ftso_rls_fifo_cfg_u ftso_rls_fifo_cfg; /* C68 */ + volatile csr_tx_idx_wt_u tx_idx_wt; /* C70 */ + volatile csr_mag_bp_en_u mag_bp_en; /* C74 */ + volatile csr_tx_tso3_rls_fifo_cfg_u tx_tso3_rls_fifo_cfg; /* C80 */ + volatile csr_cir_dat_in_fifo_sta_u cir_dat_in_fifo_sta[3]; /* 1000 */ + volatile csr_cir_rpt_fifo_sta_u cir_rpt_fifo_sta[3]; /* 1010 */ + volatile csr_cir_in_pkt_sop_cnt_u cir_in_pkt_sop_cnt; /* 1020 */ + volatile csr_cir_in_pkt_eop_cnt_u cir_in_pkt_eop_cnt; /* 1024 */ + volatile csr_cir_in_port_pkt_cnt_u cir_in_port_pkt_cnt[11]; /* 1030 */ + volatile csr_cir_drp_pkt_cnt_u cir_drp_pkt_cnt[3]; /* 1060 */ + volatile csr_cir_fifo_af_drp_pkt_cnt_u cir_fifo_af_drp_pkt_cnt[3]; /* 1070 */ + volatile csr_cir_bmu_af_drp_pkt_cnt_u cir_bmu_af_drp_pkt_cnt[3]; /* 1080 */ + volatile csr_cir_fifo_af_cnt_u cir_fifo_af_cnt[3]; /* 1090 */ + volatile csr_cir_cut_pkt_cnt_u cir_cut_pkt_cnt[3]; /* 10A0 */ + volatile csr_cir_rpt_iq_cnt_u cir_rpt_iq_cnt; /* 10B0 */ + volatile csr_cir_iq_bp_cnt_u cir_iq_bp_cnt; /* 10B4 */ + volatile csr_cir_sport_err_u cir_sport_err; /* 10B8 */ + volatile csr_cir_alc_prm_cnum_full_err_u cir_alc_prm_cnum_full_err; /* 10BC */ + volatile csr_cir_fifo_err_u cir_fifo_err; /* 10C0 */ + volatile csr_cir_fifo_ram_err_u cir_fifo_ram_err[3]; /* 10D0 */ + volatile csr_cir_prm_bp_his_0_u cir_prm_bp_his_0; /* 10E8 */ + volatile csr_cir_prm_bp_his_1_u cir_prm_bp_his_1; /* 10EC */ + volatile csr_cir_prm_bp_his_2_u cir_prm_bp_his_2; /* 10F0 */ + volatile csr_cir_prm_bp_his_3_u cir_prm_bp_his_3; /* 10F4 */ + volatile csr_cir_prm_bp_his_4_u cir_prm_bp_his_4; /* 10F8 */ + volatile csr_cpt_pro_dat_in_fifo_sta_u cpt_pro_dat_in_fifo_sta[3]; /* 1300 */ + volatile csr_cpt_pro_dealc_fifo_sta_u cpt_pro_dealc_fifo_sta[3]; /* 1310 */ + volatile csr_cpt_dealc_fifo_sta_u cpt_dealc_fifo_sta; /* 1320 */ + volatile csr_cpt_prls_fifo_sta_u cpt_prls_fifo_sta; /* 1324 */ + volatile csr_cpt_dat_out_fifo_sta_u cpt_dat_out_fifo_sta[3]; /* 1330 */ + volatile csr_cpt_out_pkt_sop_cnt_u cpt_out_pkt_sop_cnt; /* 1340 */ + volatile csr_cpt_out_pkt_eop_cnt_u cpt_out_pkt_eop_cnt; /* 1344 */ + volatile csr_cpt_out_chnl_pkt_cnt_u cpt_out_chnl_pkt_cnt[11]; /* 1350 */ + volatile csr_cpt_sof_msm_u cpt_sof_msm[3]; /* 1380 */ + volatile csr_cpt_eof_msm_u cpt_eof_msm[3]; /* 1390 */ + volatile csr_cpt_dealc_tx_bp_tm_u cpt_dealc_tx_bp_tm; /* 13A0 */ + volatile csr_cpt_dealc_rx_bp_tm_u cpt_dealc_rx_bp_tm; /* 13A4 */ + volatile csr_cpt_ts_cfg_err_u cpt_ts_cfg_err; /* 13A8 */ + volatile csr_cpt_fifo_ov_err_u cpt_fifo_ov_err; /* 13AC */ + volatile csr_cpt_fifo_uf_err_u cpt_fifo_uf_err; /* 13B0 */ + volatile csr_cpt_fifo_ram_err_u cpt_fifo_ram_err[3]; /* 13B4 */ + volatile csr_tx_chn_crdt_sta_u tx_chn_crdt_sta[11]; /* 1A00 */ + volatile csr_tx_idx_crdt_sta_u tx_idx_crdt_sta; /* 1A30 */ + volatile csr_tx_fp_bmp_sta_u tx_fp_bmp_sta[8]; /* 1A40 */ + volatile csr_txpd_fifo_empty_sta_0_u txpd_fifo_empty_sta_0; /* 1A60 */ + volatile csr_txpd_fifo_empty_sta_1_u txpd_fifo_empty_sta_1; /* 1A64 */ + volatile csr_txpd_fifo_empty_sta_2_u txpd_fifo_empty_sta_2; /* 1A68 */ + volatile csr_txpd_fifo_fill_sta_u txpd_fifo_fill_sta[9]; /* 1A70 */ + volatile csr_txpd_pro_fsm_sta_u txpd_pro_fsm_sta[11]; /* 1AA0 */ + volatile csr_mag_bp_sta_0_u mag_bp_sta_0; /* 1AD0 */ + volatile csr_mag_bp_sta_1_u mag_bp_sta_1; /* 1AD4 */ + volatile csr_tx_ftso_rls_fifo_sta_u tx_ftso_rls_fifo_sta; /* 1AE8 */ + volatile csr_tx_tso3_rls_fifo_sta_u tx_tso3_rls_fifo_sta[3]; /* 1AF0 */ + volatile csr_tx_crdt_of_err_u tx_crdt_of_err; /* 1B00 */ + volatile csr_tx_crdt_uf_err_u tx_crdt_uf_err; /* 1B04 */ + volatile csr_txpd_fifo_of_err_0_u txpd_fifo_of_err_0; /* 1B10 */ + volatile csr_txpd_fifo_of_err_1_u txpd_fifo_of_err_1; /* 1B14 */ + volatile csr_txpd_fifo_of_err_2_u txpd_fifo_of_err_2; /* 1B18 */ + volatile csr_txpd_fifo_uf_err_0_u txpd_fifo_uf_err_0; /* 1B20 */ + volatile csr_txpd_fifo_uf_err_1_u txpd_fifo_uf_err_1; /* 1B24 */ + volatile csr_txpd_fifo_uf_err_2_u txpd_fifo_uf_err_2; /* 1B28 */ + volatile csr_tx_ftso_rls_fifo_err_u tx_ftso_rls_fifo_err; /* 1B30 */ + volatile csr_tso_ram_err_u tso_ram_err; /* 1B34 */ + volatile csr_tx_pd_ram_err_u tx_pd_ram_err[8]; /* 1B40 */ + volatile csr_cpb_tx_err_0_u cpb_tx_err_0; /* 1B80 */ + volatile csr_cpb_tx_err_1_u cpb_tx_err_1; /* 1B84 */ + volatile csr_cpb_tx_err_2_u cpb_tx_err_2; /* 1B88 */ + volatile csr_cpb_tx_err_3_u cpb_tx_err_3; /* 1B8C */ + volatile csr_cpb_tx_err_4_u cpb_tx_err_4; /* 1B90 */ + volatile csr_cpb_tx_err_5_u cpb_tx_err_5; /* 1B94 */ +} S_cpb_csr_3_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_3 */ +extern volatile S_cpb_csr_3_REGS_TYPE *gopcpb_csr_3AllReg; + +/* Declare the functions that set the member value */ +int iSetCPB_INDIR_DAT_cpb_indir_dat(unsigned int ucpb_indir_dat); +int iSetCIR_ALC_PRO_WT_cir_alc_pro_wt_0(unsigned int ucir_alc_pro_wt_0); +int iSetCIR_ALC_PRO_WT_cir_alc_pro_wt_1(unsigned int ucir_alc_pro_wt_1); +int iSetCIR_ALC_PRO_WT_cir_alc_pro_wt_2(unsigned int ucir_alc_pro_wt_2); +int iSetCIR_RPCI_PRO_WT_cir_rpci_pro_wt_0(unsigned int ucir_rpci_pro_wt_0); +int iSetCIR_RPCI_PRO_WT_cir_rpci_pro_wt_1(unsigned int ucir_rpci_pro_wt_1); +int iSetCIR_RPCI_PRO_WT_cir_rpci_pro_wt_2(unsigned int ucir_rpci_pro_wt_2); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_4_0(unsigned int ucir_alc_mac_port_wt_4_0); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_5_1(unsigned int ucir_alc_mac_port_wt_5_1); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_6_2(unsigned int ucir_alc_mac_port_wt_6_2); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_7_3(unsigned int ucir_alc_mac_port_wt_7_3); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_ncsi_port_wt(unsigned int ucir_alc_ncsi_port_wt); +int iSetCIR_DATA_IN_FIFO_AF_TH_cir_data_in_fifo_af_th_mac03(unsigned int ucir_data_in_fifo_af_th_mac03); +int iSetCIR_DATA_IN_FIFO_AF_TH_cir_data_in_fifo_af_th_mac47(unsigned int ucir_data_in_fifo_af_th_mac47); +int iSetCIR_DATA_IN_FIFO_AF_TH_cir_data_in_fifo_af_th_lprts(unsigned int ucir_data_in_fifo_af_th_lprts); +int iSetCIR_ALC_FIFO_AF_TH_cir_alc_fifo_af_th_mac03(unsigned int ucir_alc_fifo_af_th_mac03); +int iSetCIR_ALC_FIFO_AF_TH_cir_alc_fifo_af_th_mac47(unsigned int ucir_alc_fifo_af_th_mac47); +int iSetCIR_ALC_FIFO_AF_TH_cir_alc_fifo_af_th_lprts(unsigned int ucir_alc_fifo_af_th_lprts); +int iSetCIR_RPCI_FIFO_AF_TH_cir_rpci_fifo_af_th_mac03(unsigned int ucir_rpci_fifo_af_th_mac03); +int iSetCIR_RPCI_FIFO_AF_TH_cir_rpci_fifo_af_th_mac47(unsigned int ucir_rpci_fifo_af_th_mac47); +int iSetCIR_RPCI_FIFO_AF_TH_cir_rpci_fifo_af_th_lprts(unsigned int ucir_rpci_fifo_af_th_lprts); +int iSetCIR_ALC_RP_TH_cir_alc_rp_th_mac03(unsigned int ucir_alc_rp_th_mac03); +int iSetCIR_ALC_RP_TH_cir_alc_rp_th_mac47(unsigned int ucir_alc_rp_th_mac47); +int iSetCIR_ALC_RP_TH_cir_alc_rp_th_lprts(unsigned int ucir_alc_rp_th_lprts); +int iSetCIR_DATA_IN_FIFO_DROP_TH_cir_data_in_fifo_drop_th_mac03(unsigned int ucir_data_in_fifo_drop_th_mac03); +int iSetCIR_DATA_IN_FIFO_DROP_TH_cir_data_in_fifo_drop_th_mac47(unsigned int ucir_data_in_fifo_drop_th_mac47); +int iSetCIR_DATA_IN_FIFO_DROP_TH_cir_data_in_fifo_drop_th_lprts(unsigned int ucir_data_in_fifo_drop_th_lprts); +int iSetCIR_IPSURX_BP_EN_cir_ipsurx_bp_en(unsigned int ucir_ipsurx_bp_en); +int iSetCIR_ALC_SHP_EN_cir_alc_shp_en(unsigned int ucir_alc_shp_en); +int iSetCPT_MAC03_TS_cpt_mac03_ts(unsigned int ucpt_mac03_ts); +int iSetCPT_MAC47_TS_cpt_mac47_ts(unsigned int ucpt_mac47_ts); +int iSetCPT_MACLB_TS_cpt_maclb_ts(unsigned int ucpt_maclb_ts); +int iSetCPT_TS_CFG_cpt_ts_len(unsigned int ucpt_ts_len); +int iSetCPT_TS_CFG_cpt_ts_cfg_done(unsigned int ucpt_ts_cfg_done); +int iSetCPT_CRDT_INIT_cpt_fifo_crdt_init_dat(unsigned int ucpt_fifo_crdt_init_dat); +int iSetCPT_CRDT_INIT_cpt_fifo_crdt_init(unsigned int ucpt_fifo_crdt_init); +int iSetCPT_DEALC_TX_AF_TH_cpt_dealc_tx_af_th(unsigned int ucpt_dealc_tx_af_th); +int iSetCPT_DEALC_RX_AF_TH_cpt_dealc_rx_af_th(unsigned int ucpt_dealc_rx_af_th); +int iSetCPT_PRLS_AF_TH_cpt_prls_af_th(unsigned int ucpt_prls_af_th); +int iSetCPT_PRLS_AF_TH_cpt_pro_prls_fifo_af_th(unsigned int ucpt_pro_prls_fifo_af_th); +int iSetCPT_COL_TH_cpt_deast_col_th(unsigned int ucpt_deast_col_th); +int iSetCPT_COL_TH_cpt_ast_col_th(unsigned int ucpt_ast_col_th); +int iSetCPT_PRO_DI_FIFO_AF_TH_cpt_pro_di_fifo_af_th(unsigned int ucpt_pro_di_fifo_af_th); +int iSetCPT_PRO_DEALC_TX_FIFO_AF_TH_cpt_pro_dealc_tx_fifo_af_th(unsigned int ucpt_pro_dealc_tx_fifo_af_th); +int iSetCPT_PRO_DEALC_RX_FIFO_AF_TH_cpt_pro_dealc_rx_fifo_af_th(unsigned int ucpt_pro_dealc_rx_fifo_af_th); +int iSetCPT_PRO_FIFO_CRDT_INIT_cpt_pro_dat_fifo_crdt_init_dat(unsigned int ucpt_pro_dat_fifo_crdt_init_dat); +int iSetCPT_PRO_FIFO_CRDT_INIT_cpt_pro_dat_fifo_crdt_init(unsigned int ucpt_pro_dat_fifo_crdt_init); +int iSetCPT_PRO_DEALC_RP_TH_cpt_pro_dealc_rp_th(unsigned int ucpt_pro_dealc_rp_th); +int iSetCPT_OUT_ERR_EN_cpb_petx_err_en(unsigned int ucpb_petx_err_en); +int iSetCPT_OUT_ERR_EN_cpb_petx_ftso_err_en(unsigned int ucpb_petx_ftso_err_en); +int iSetCPT_TXLB_EN_cpt_txlb_en(unsigned int ucpt_txlb_en); +int iSetTX_CRR0_EN_cpbtx0_crr_vld(unsigned int ucpbtx0_crr_vld); +int iSetTX_CRR0_EN_cpbtx0_crr_len(unsigned int ucpbtx0_crr_len); +int iSetTX_CRR0_PID_cpbtx0_crr_pid0(unsigned int ucpbtx0_crr_pid0); +int iSetTX_CRR0_PID_cpbtx0_crr_pid1(unsigned int ucpbtx0_crr_pid1); +int iSetTX_CRR0_PID_cpbtx0_crr_pid2(unsigned int ucpbtx0_crr_pid2); +int iSetTX_CRR0_PID_cpbtx0_crr_pid3(unsigned int ucpbtx0_crr_pid3); +int iSetTX_CRR0_PID_cpbtx0_crr_pid4(unsigned int ucpbtx0_crr_pid4); +int iSetTX_CRR0_PID_cpbtx0_crr_pid5(unsigned int ucpbtx0_crr_pid5); +int iSetTX_CRR0_PID_cpbtx0_crr_pid6(unsigned int ucpbtx0_crr_pid6); +int iSetTX_CRR0_PID_cpbtx0_crr_pid7(unsigned int ucpbtx0_crr_pid7); +int iSetTX_CRR1_EN_cpbtx1_crr_vld(unsigned int ucpbtx1_crr_vld); +int iSetTX_CRR1_EN_cpbtx1_crr_len(unsigned int ucpbtx1_crr_len); +int iSetTX_CRR1_PID_cpbtx1_crr_pid0(unsigned int ucpbtx1_crr_pid0); +int iSetTX_CRR1_PID_cpbtx1_crr_pid1(unsigned int ucpbtx1_crr_pid1); +int iSetTX_CRR1_PID_cpbtx1_crr_pid2(unsigned int ucpbtx1_crr_pid2); +int iSetTX_CRR1_PID_cpbtx1_crr_pid3(unsigned int ucpbtx1_crr_pid3); +int iSetTX_CRR1_PID_cpbtx1_crr_pid4(unsigned int ucpbtx1_crr_pid4); +int iSetTX_CRR1_PID_cpbtx1_crr_pid5(unsigned int ucpbtx1_crr_pid5); +int iSetTX_CRR1_PID_cpbtx1_crr_pid6(unsigned int ucpbtx1_crr_pid6); +int iSetTX_CRR1_PID_cpbtx1_crr_pid7(unsigned int ucpbtx1_crr_pid7); +int iSetTX_CRR2_EN_cpbtx2_crr_vld(unsigned int ucpbtx2_crr_vld); +int iSetTX_CRR2_EN_cpbtx2_crr_len(unsigned int ucpbtx2_crr_len); +int iSetTX_CRR2_PID_cpbtx2_crr_pid0(unsigned int ucpbtx2_crr_pid0); +int iSetTX_CRR2_PID_cpbtx2_crr_pid1(unsigned int ucpbtx2_crr_pid1); +int iSetTX_CRR2_PID_cpbtx2_crr_pid2(unsigned int ucpbtx2_crr_pid2); +int iSetTX_CRR2_PID_cpbtx2_crr_pid3(unsigned int ucpbtx2_crr_pid3); +int iSetTX_CRR2_PID_cpbtx2_crr_pid4(unsigned int ucpbtx2_crr_pid4); +int iSetTX_CRR2_PID_cpbtx2_crr_pid5(unsigned int ucpbtx2_crr_pid5); +int iSetTX_CRR2_PID_cpbtx2_crr_pid6(unsigned int ucpbtx2_crr_pid6); +int iSetTX_CRR2_PID_cpbtx2_crr_pid7(unsigned int ucpbtx2_crr_pid7); +int iSetTX_CHN_CRDT_CFG0_tx_chn_crdt_0(unsigned int utx_chn_crdt_0); +int iSetTX_CHN_CRDT_CFG1_tx_chn_crdt_1(unsigned int utx_chn_crdt_1); +int iSetTX_CHN_CRDT_CFG2_tx_chn_crdt_2(unsigned int utx_chn_crdt_2); +int iSetTX_CHN_CRDT_CFG3_tx_chn_crdt_3(unsigned int utx_chn_crdt_3); +int iSetTX_CHN_CRDT_CFG4_tx_chn_crdt_4(unsigned int utx_chn_crdt_4); +int iSetTX_CHN_CRDT_CFG5_tx_chn_crdt_5(unsigned int utx_chn_crdt_5); +int iSetTX_CHN_CRDT_CFG6_tx_chn_crdt_6(unsigned int utx_chn_crdt_6); +int iSetTX_CHN_CRDT_CFG7_tx_chn_crdt_7(unsigned int utx_chn_crdt_7); +int iSetTX_CHN_CRDT_CFG8_tx_chn_crdt_8(unsigned int utx_chn_crdt_8); +int iSetTX_CHN_CRDT_CFG9_tx_chn_crdt_9(unsigned int utx_chn_crdt_9); +int iSetTX_CHN_CRDT_CFG10_tx_chn_crdt_10(unsigned int utx_chn_crdt_10); +int iSetCPB_TX_CRDT_CFG_petx_idx_crdt(unsigned int upetx_idx_crdt); +int iSetCPB_TX_CRDT_CFG_tx_dat_prealc_crdt(unsigned int utx_dat_prealc_crdt); +int iSetCPB_TX_CRDT_CFG_tx_crdt_bp_gap(unsigned int utx_crdt_bp_gap); +int iSetCPB_TX_CRDT_CFG_petx_idx_bp_gap(unsigned int upetx_idx_bp_gap); +int iSetTXLB_PD_FIFO_CFG_txlp_pd_fifo_ae_th(unsigned int utxlp_pd_fifo_ae_th); +int iSetTXLB_PD_FIFO_CFG_txlp_pd_fifo_af_th(unsigned int utxlp_pd_fifo_af_th); +int iSetTX_COS_FIFO_CFG_tx_cos_fifo_ae_th(unsigned int utx_cos_fifo_ae_th); +int iSetTX_COS_FIFO_CFG_tx_cos_fifo_af_th(unsigned int utx_cos_fifo_af_th); +int iSetFTSO_RLS_FIFO_CFG_ftso_rls_fifo_ae_th(unsigned int uftso_rls_fifo_ae_th); +int iSetFTSO_RLS_FIFO_CFG_ftso_rls_fifo_af_th(unsigned int uftso_rls_fifo_af_th); +int iSetTX_IDX_WT_cpt_idx_req_wt0(unsigned int ucpt_idx_req_wt0); +int iSetTX_IDX_WT_cpt_idx_req_wt1(unsigned int ucpt_idx_req_wt1); +int iSetTX_IDX_WT_cpt_idx_req_wt2(unsigned int ucpt_idx_req_wt2); +int iSetMAG_BP_EN_mag_cpb_bp_en(unsigned int umag_cpb_bp_en); +int iSetTX_TSO3_RLS_FIFO_CFG_tx_tso3_rls_fifo_ae_th(unsigned int utx_tso3_rls_fifo_ae_th); +int iSetTX_TSO3_RLS_FIFO_CFG_tx_tso3_rls_fifo_af_th(unsigned int utx_tso3_rls_fifo_af_th); +int iSetCIR_DAT_IN_FIFO_STA_cir_di_ctrl_fifo_sta(unsigned int ucir_di_ctrl_fifo_sta); +int iSetCIR_DAT_IN_FIFO_STA_cir_di_fifo_sta(unsigned int ucir_di_fifo_sta); +int iSetCIR_RPT_FIFO_STA_cir_alc_fifo_sta(unsigned int ucir_alc_fifo_sta); +int iSetCIR_RPT_FIFO_STA_cir_rpt_pci_sta(unsigned int ucir_rpt_pci_sta); +int iSetCIR_IN_PKT_SOP_CNT_cir_in_pkt_sop_cnt(unsigned int ucir_in_pkt_sop_cnt); +int iSetCIR_IN_PKT_EOP_CNT_cir_in_pkt_eop_cnt(unsigned int ucir_in_pkt_eop_cnt); +int iSetCIR_IN_PORT_PKT_CNT_cir_in_port_pkt_cnt(unsigned int ucir_in_port_pkt_cnt); +int iSetCIR_DRP_PKT_CNT_cir_drp_pkt_cnt(unsigned int ucir_drp_pkt_cnt); +int iSetCIR_FIFO_AF_DRP_PKT_CNT_cir_fifo_af_drp_pkt_cnt(unsigned int ucir_fifo_af_drp_pkt_cnt); +int iSetCIR_BMU_AF_DRP_PKT_CNT_cir_bmu_af_drp_pkt_cnt(unsigned int ucir_bmu_af_drp_pkt_cnt); +int iSetCIR_FIFO_AF_CNT_cir_fifo_af_cnt(unsigned int ucir_fifo_af_cnt); +int iSetCIR_CUT_PKT_CNT_cir_cut_pkt_cnt(unsigned int ucir_cut_pkt_cnt); +int iSetCIR_RPT_IQ_CNT_cir_rpt_iq_cnt(unsigned int ucir_rpt_iq_cnt); +int iSetCIR_IQ_BP_CNT_cir_iq_bp_cnt(unsigned int ucir_iq_bp_cnt); +int iSetCIR_SPORT_ERR_cir_sport_err(unsigned int ucir_sport_err); +int iSetCIR_ALC_PRM_CNUM_FULL_ERR_cir_alc_prm_cnum_full_err(unsigned int ucir_alc_prm_cnum_full_err); +int iSetCIR_FIFO_ERR_cir_di_fifo_uf(unsigned int ucir_di_fifo_uf); +int iSetCIR_FIFO_ERR_cir_di_ctrl_fifo_uf(unsigned int ucir_di_ctrl_fifo_uf); +int iSetCIR_FIFO_ERR_cir_rpt_pci_uf(unsigned int ucir_rpt_pci_uf); +int iSetCIR_FIFO_ERR_cir_alc_fifo_uf(unsigned int ucir_alc_fifo_uf); +int iSetCIR_FIFO_ERR_cir_di_fifo_ov(unsigned int ucir_di_fifo_ov); +int iSetCIR_FIFO_ERR_cir_di_ctrl_fifo_ov(unsigned int ucir_di_ctrl_fifo_ov); +int iSetCIR_FIFO_ERR_cir_rpt_pci_ov(unsigned int ucir_rpt_pci_ov); +int iSetCIR_FIFO_ERR_cir_alc_fifo_ov(unsigned int ucir_alc_fifo_ov); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_addr(unsigned int ucir_fifo_mem_err_addr); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_cerr(unsigned int ucir_fifo_mem_err_cerr); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_ucerr(unsigned int ucir_fifo_mem_err_ucerr); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_cnt(unsigned int ucir_fifo_mem_err_cnt); +int iSetCIR_PRM_BP_HIS_0_cir_prm_bp_his_0(unsigned int ucir_prm_bp_his_0); +int iSetCIR_PRM_BP_HIS_1_cir_prm_bp_his_1(unsigned int ucir_prm_bp_his_1); +int iSetCIR_PRM_BP_HIS_2_cir_prm_bp_his_2(unsigned int ucir_prm_bp_his_2); +int iSetCIR_PRM_BP_HIS_3_cir_prm_bp_his_3(unsigned int ucir_prm_bp_his_3); +int iSetCIR_PRM_BP_HIS_4_cir_prm_bp_his_4(unsigned int ucir_prm_bp_his_4); +int iSetCPT_PRO_DAT_IN_FIFO_STA_cpt_pro_di_fifo_sta(unsigned int ucpt_pro_di_fifo_sta); +int iSetCPT_PRO_DAT_IN_FIFO_STA_cpt_pro_prls_fifo_sta(unsigned int ucpt_pro_prls_fifo_sta); +int iSetCPT_PRO_DEALC_FIFO_STA_cpt_pro_dealc_rx_fifo_sta(unsigned int ucpt_pro_dealc_rx_fifo_sta); +int iSetCPT_PRO_DEALC_FIFO_STA_cpt_pro_dealc_tx_fifo_sta(unsigned int ucpt_pro_dealc_tx_fifo_sta); +int iSetCPT_DEALC_FIFO_STA_cpt_dealc_rx_fifo_sta(unsigned int ucpt_dealc_rx_fifo_sta); +int iSetCPT_DEALC_FIFO_STA_cpt_dealc_tx_fifo_sta(unsigned int ucpt_dealc_tx_fifo_sta); +int iSetCPT_PRLS_FIFO_STA_cpt_prls_fifo_sta(unsigned int ucpt_prls_fifo_sta); +int iSetCPT_DAT_OUT_FIFO_STA_cpt_dat_out_fifo_sta(unsigned int ucpt_dat_out_fifo_sta); +int iSetCPT_OUT_PKT_SOP_CNT_cpt_out_pkt_sop_cnt(unsigned int ucpt_out_pkt_sop_cnt); +int iSetCPT_OUT_PKT_EOP_CNT_cpt_out_pkt_eop_cnt(unsigned int ucpt_out_pkt_eop_cnt); +int iSetCPT_OUT_CHNL_PKT_CNT_cpt_out_chnl_pkt_cnt(unsigned int ucpt_out_chnl_pkt_cnt); +int iSetCPT_SOF_MSM_cpt_sof_msm_info(unsigned int ucpt_sof_msm_info); +int iSetCPT_SOF_MSM_cpt_sof_msm(unsigned int ucpt_sof_msm); +int iSetCPT_EOF_MSM_cpt_eof_msm_info(unsigned int ucpt_eof_msm_info); +int iSetCPT_EOF_MSM_cpt_eof_msm(unsigned int ucpt_eof_msm); +int iSetCPT_DEALC_TX_BP_TM_cpt_dealc_tx_bp_tm(unsigned int ucpt_dealc_tx_bp_tm); +int iSetCPT_DEALC_RX_BP_TM_cpt_dealc_rx_bp_tm(unsigned int ucpt_dealc_rx_bp_tm); +int iSetCPT_TS_CFG_ERR_cpt_ts_cfg_err(unsigned int ucpt_ts_cfg_err); +int iSetCPT_FIFO_OV_ERR_cpt_pro_di_fifo_ov(unsigned int ucpt_pro_di_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_pro_dealc_tx_fifo_ov(unsigned int ucpt_pro_dealc_tx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_pro_dealc_rx_fifo_ov(unsigned int ucpt_pro_dealc_rx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_dat_out_fifo_ov(unsigned int ucpt_dat_out_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_dealc_tx_fifo_ov(unsigned int ucpt_dealc_tx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_dealc_rx_fifo_ov(unsigned int ucpt_dealc_rx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_prls_fifo_ov(unsigned int ucpt_prls_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_pro_prls_fifo_ov(unsigned int ucpt_pro_prls_fifo_ov); +int iSetCPT_FIFO_UF_ERR_cpt_pro_di_fifo_uf(unsigned int ucpt_pro_di_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_pro_dealc_tx_fifo_uf(unsigned int ucpt_pro_dealc_tx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_pro_dealc_rx_fifo_uf(unsigned int ucpt_pro_dealc_rx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_dat_out_fifo_uf(unsigned int ucpt_dat_out_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_dealc_tx_fifo_uf(unsigned int ucpt_dealc_tx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_dealc_rx_fifo_uf(unsigned int ucpt_dealc_rx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_prls_fifo_uf(unsigned int ucpt_prls_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_pro_prls_fifo_uf(unsigned int ucpt_pro_prls_fifo_uf); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_addr(unsigned int ucpt_fifo_mem_err_addr); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_cerr(unsigned int ucpt_fifo_mem_err_cerr); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_ucerr(unsigned int ucpt_fifo_mem_err_ucerr); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_cnt(unsigned int ucpt_fifo_mem_err_cnt); +int iSetTX_CHN_CRDT_STA_tx_chn_crdt_cnt(unsigned int utx_chn_crdt_cnt); +int iSetTX_CHN_CRDT_STA_tx_chn_crdt_af(unsigned int utx_chn_crdt_af); +int iSetTX_IDX_CRDT_STA_tx_idx_crdt_cnt(unsigned int utx_idx_crdt_cnt); +int iSetTX_IDX_CRDT_STA_tx_idx_crdt_af(unsigned int utx_idx_crdt_af); +int iSetTX_FP_BMP_STA_tx_fp_bmp_fill(unsigned int utx_fp_bmp_fill); +int iSetTXPD_FIFO_EMPTY_STA_0_txpd_fifo_empty_sta_0(unsigned int utxpd_fifo_empty_sta_0); +int iSetTXPD_FIFO_EMPTY_STA_1_txpd_fifo_empty_sta_1(unsigned int utxpd_fifo_empty_sta_1); +int iSetTXPD_FIFO_EMPTY_STA_2_txpd_fifo_empty_sta_2(unsigned int utxpd_fifo_empty_sta_2); +int iSetTXPD_FIFO_FILL_STA_txpd_fifo_fill_sta(unsigned int utxpd_fifo_fill_sta); +int iSetTXPD_PRO_FSM_STA_txpd_pro_fsm_sta(unsigned int utxpd_pro_fsm_sta); +int iSetMAG_BP_STA_0_mag_cpb_bp_sta_0(unsigned int umag_cpb_bp_sta_0); +int iSetMAG_BP_STA_1_mag_cpb_bp_sta_1(unsigned int umag_cpb_bp_sta_1); +int iSetTX_FTSO_RLS_FIFO_STA_tx_ftsorls_fifo_sta_0(unsigned int utx_ftsorls_fifo_sta_0); +int iSetTX_FTSO_RLS_FIFO_STA_tx_ftsorls_fifo_sta_1(unsigned int utx_ftsorls_fifo_sta_1); +int iSetTX_TSO3_RLS_FIFO_STA_tx_tso3_rls_fifo_sta(unsigned int utx_tso3_rls_fifo_sta); +int iSetTX_CRDT_OF_ERR_tx_idx_crdt_of_err(unsigned int utx_idx_crdt_of_err); +int iSetTX_CRDT_OF_ERR_tx_chn_crdt_of_err(unsigned int utx_chn_crdt_of_err); +int iSetTX_CRDT_UF_ERR_tx_idx_crdt_uf_err(unsigned int utx_idx_crdt_uf_err); +int iSetTX_CRDT_UF_ERR_tx_chn_crdt_uf_err(unsigned int utx_chn_crdt_uf_err); +int iSetTXPD_FIFO_OF_ERR_0_txpd_fifo_of_err_0(unsigned int utxpd_fifo_of_err_0); +int iSetTXPD_FIFO_OF_ERR_1_txpd_fifo_of_err_1(unsigned int utxpd_fifo_of_err_1); +int iSetTXPD_FIFO_OF_ERR_2_txpd_fifo_of_err_2(unsigned int utxpd_fifo_of_err_2); +int iSetTXPD_FIFO_OF_ERR_2_tx_fp_fifo_of_err(unsigned int utx_fp_fifo_of_err); +int iSetTXPD_FIFO_OF_ERR_2_tx_tso3_rls_fifo_of_err(unsigned int utx_tso3_rls_fifo_of_err); +int iSetTXPD_FIFO_UF_ERR_0_txpd_fifo_uf_err_0(unsigned int utxpd_fifo_uf_err_0); +int iSetTXPD_FIFO_UF_ERR_1_txpd_fifo_uf_err_1(unsigned int utxpd_fifo_uf_err_1); +int iSetTXPD_FIFO_UF_ERR_2_txpd_fifo_uf_err_2(unsigned int utxpd_fifo_uf_err_2); +int iSetTXPD_FIFO_UF_ERR_2_tx_fp_fifo_uf_err(unsigned int utx_fp_fifo_uf_err); +int iSetTXPD_FIFO_UF_ERR_2_tx_tso3_rls_fifo_uf_err(unsigned int utx_tso3_rls_fifo_uf_err); +int iSetTX_FTSO_RLS_FIFO_ERR_tx_ftso_rls_fifo_uf_err(unsigned int utx_ftso_rls_fifo_uf_err); +int iSetTX_FTSO_RLS_FIFO_ERR_tx_ftso_rls_fifo_of_err(unsigned int utx_ftso_rls_fifo_of_err); +int iSetTSO_RAM_ERR_tso_mem_err_addr(unsigned int utso_mem_err_addr); +int iSetTSO_RAM_ERR_tso_mem_err_cerr(unsigned int utso_mem_err_cerr); +int iSetTSO_RAM_ERR_tso_mem_err_ucerr(unsigned int utso_mem_err_ucerr); +int iSetTSO_RAM_ERR_tso_mem_err_cnt(unsigned int utso_mem_err_cnt); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_addr(unsigned int utx_pd_mem_err_addr); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_cerr(unsigned int utx_pd_mem_err_cerr); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_ucerr(unsigned int utx_pd_mem_err_ucerr); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_cnt(unsigned int utx_pd_mem_err_cnt); +int iSetCPB_TX_ERR_0_tx_chn_pd_pptr_err(unsigned int utx_chn_pd_pptr_err); +int iSetCPB_TX_ERR_1_tx_chn_pd_pktmod_err(unsigned int utx_chn_pd_pktmod_err); +int iSetCPB_TX_ERR_2_tx_chn_ret_pcnum_err(unsigned int utx_chn_ret_pcnum_err); +int iSetCPB_TX_ERR_3_tx_chn_tso1_num_err(unsigned int utx_chn_tso1_num_err); +int iSetCPB_TX_ERR_3_tx_chn_tso1_cmd_cnum_err(unsigned int utx_chn_tso1_cmd_cnum_err); +int iSetCPB_TX_ERR_4_tx_chn_tso2_num_err(unsigned int utx_chn_tso2_num_err); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err(unsigned int utx_chn_tso2_cmd_cnum_err); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err0(unsigned int utx_chn_tso2_cmd_cnum_err0); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err1(unsigned int utx_chn_tso2_cmd_cnum_err1); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err2(unsigned int utx_chn_tso2_cmd_cnum_err2); +int iSetCPB_TX_ERR_5_tx_chn_lro2_num_err(unsigned int utx_chn_lro2_num_err); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err(unsigned int utx_chn_lro2_cmd_cnum_err); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err0(unsigned int utx_chn_lro2_cmd_cnum_err0); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err1(unsigned int utx_chn_lro2_cmd_cnum_err1); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err2(unsigned int utx_chn_lro2_cmd_cnum_err2); + +#endif // CPB_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_reg_offset.h new file mode 100644 index 000000000..e45d6eb4e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_reg_offset.h @@ -0,0 +1,1157 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpb_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/3 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2020/03/24 21:10:00 Create file +// ****************************************************************************** + +#ifndef CPB_REG_OFFSET_H +#define CPB_REG_OFFSET_H + +/* CPB_CSR_0 Base address of Module's Register */ +#define CSR_CPB_CSR_0_BASE (0x2000) + +/* **************************************************************************** */ +/* CPB_CSR_0 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_CPB_FPGA_VER_REG (CSR_CPB_CSR_0_BASE + 0x0) /* CPB FPGA版本寄存器 */ +#define CSR_CPB_CSR_CPB_EMU_VER_REG (CSR_CPB_CSR_0_BASE + 0x4) /* CPB EMU版本寄存器 */ +#define CSR_CPB_CSR_CPB_BANK_ROW_EN_REG (CSR_CPB_CSR_0_BASE + 0xC) /* CPB BANK的各个ROW使能配置 */ +#define CSR_CPB_CSR_CPB_DAT_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x10) /* CPB DAT MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_CD_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x14) /* CPB CD MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_NPTR_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x18) /* CPB NPTR MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_TI_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x1C) /* CPB TI MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_DAT_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x20) /* CPB DAT MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_CD_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x24) /* CPB CD MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_NPTR_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x28) /* CPB NPTR MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_TI_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x2C) /* CPB TI MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_BMP_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x30) /* CPB Bitmap初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_BMP_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x34) /* CPB Bitmap初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x38) /* 配置表初始化使能寄存器 */ +#define CSR_CPB_CSR_CPB_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x3C) /* 配置表初始化状态寄存器 */ +#define CSR_CPB_CSR_CPB_INT_VECTOR_REG (CSR_CPB_CSR_0_BASE + 0x40) /* 中断向量寄存器 */ +#define CSR_CPB_CSR_CPB_INT_REG (CSR_CPB_CSR_0_BASE + 0x44) /* 中断状态寄存器 */ +#define CSR_CPB_CSR_CPB_INT_EN_REG (CSR_CPB_CSR_0_BASE + 0x48) /* 中断使能寄存器 */ +#define CSR_CPB_CSR_CPB_RAM_UCERR_REG (CSR_CPB_CSR_0_BASE + 0x4C) /* CPB RAM ECC不可纠错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_RAM_CERR_REG (CSR_CPB_CSR_0_BASE + 0x50) /* CPB RAM ECC可纠错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_FIFO_OF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x54) /* CPB FIFO出现Overflow错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_FIFO_UF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x58) /* CPB FIFO出现Underflow错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_RX_CRDT_ERR_REG (CSR_CPB_CSR_0_BASE + 0x5C) /* CPB RX方向Credit错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_TX_CRDT_ERR_REG (CSR_CPB_CSR_0_BASE + 0x60) /* CPB TX方向Credit错误中断寄存器 */ +#define CSR_CPB_CSR_TX_PREALC_CRDT_ERR_REG (CSR_CPB_CSR_0_BASE + 0x64) /* TX方向Cell预扣不足错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_BP_DROP_ERR_REG (CSR_CPB_CSR_0_BASE + 0x68) /* CPB因反压丢包错误中断寄存器 */ +#define CSR_CPB_CSR_CIR_CIT_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x6C) /* CPB IPSURX/IPSUTX接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_CPR_CPT_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x70) /* CPB PERX/PETX接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_CT_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x74) /* CPB STL/STF Tile接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_CQ_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x78) /* CPB QU IQ/OQ接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_RX_TX_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x7C) /* CPB RX/TX处理模块异常中断寄存器 */ +#define CSR_CPB_CSR_CPB_BMU_RSC_ERR_REG (CSR_CPB_CSR_0_BASE + 0x80) /* CPB BMU Cell资源异常中断寄存器 */ +#define CSR_CPB_CSR_CPB_AGING_ERR_REG (CSR_CPB_CSR_0_BASE + 0x84) /* CPB发现有Cell被老化的异常中断寄存器 */ +#define CSR_CPB_CSR_CPB_FATAL_ERR_EN_REG (CSR_CPB_CSR_0_BASE + 0x90) /* CPB产生Fatal Err指示的使能配置 */ +#define CSR_CPB_CSR_CPB_FATAL_ERR_STA_REG (CSR_CPB_CSR_0_BASE + 0x94) /* CPB的Fatal Err的状态指示及清除寄存器 */ +#define CSR_CPB_CSR_CPB_ITF_BP_STA_REG (CSR_CPB_CSR_0_BASE + 0xA0) /* CPB周边接口反压状态指示寄存器 */ +#define CSR_CPB_CSR_CPB_ITF_BP_HIS_REG (CSR_CPB_CSR_0_BASE + 0xA4) /* CPB周边接口反压历史状态寄存器 */ +#define CSR_CPB_CSR_CPB_API_ERR_REG (CSR_CPB_CSR_0_BASE + 0xD0) /* CPB中API异常的汇聚，包含TL_REQ_INVLD、TL_STR_ERR */ +#define CSR_CPB_CSR_CPB_FIFO_ERR_COL_REG (CSR_CPB_CSR_0_BASE + 0xD4) /* CPB中各模块FIFO溢出汇聚寄存器 */ +#define CSR_CPB_CSR_TL_REQ_INVLD_REG (CSR_CPB_CSR_0_BASE + 0xD8) /* Tile下发API或IQ的push请求非法 */ +#define CSR_CPB_CSR_TL_STR_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0xDC) /* Tile下发的streamout API填充错误 */ +#define CSR_CPB_CSR_TL_STR_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0xE0) /* Tile下发的streamout API填充错误 */ +#define CSR_CPB_CSR_TL_STR_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0xE4) /* Tile下发的streamout API填充错误 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_0_REG (CSR_CPB_CSR_0_BASE + 0x100) /* CPB RAM CTRL控制寄存器0 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_1_REG (CSR_CPB_CSR_0_BASE + 0x104) /* CPB RAM CTRL控制寄存器1 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_2_REG (CSR_CPB_CSR_0_BASE + 0x108) /* CPB RAM CTRL控制寄存器2 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_3_REG (CSR_CPB_CSR_0_BASE + 0x10C) /* CPB RAM CTRL控制寄存器3 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_4_REG (CSR_CPB_CSR_0_BASE + 0x110) /* CPB RAM CTRL控制寄存器4 */ +#define CSR_CPB_CSR_CPB_RAM_ECC_BYPASS_REG (CSR_CPB_CSR_0_BASE + 0x114) /* CPB RAM ECC单bit纠错Bypass配置寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_CTRL_REG (CSR_CPB_CSR_0_BASE + 0x170) /* 间接访问控制寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_TO_TH_REG (CSR_CPB_CSR_0_BASE + 0x174) /* 间接访问Timeout配置寄存器 */ +#define CSR_CPB_CSR_BANK_WEAK_CFG_REG (CSR_CPB_CSR_0_BASE + 0x200) /* BMU Bank Weak配置寄存器 */ +#define CSR_CPB_CSR_BMU_ALT_BP_CFG_REG (CSR_CPB_CSR_0_BASE + 0x204) /* BMU告警反压配置寄存器 */ +#define CSR_CPB_CSR_BMU_FAT_BP_CFG_REG (CSR_CPB_CSR_0_BASE + 0x208) /* BMU致命反压配置寄存器 */ +#define CSR_CPB_CSR_BMU_AP_ACC_WT0_REG (CSR_CPB_CSR_0_BASE + 0x210) /* BMU指定地址访问端口的权重配置 */ +#define CSR_CPB_CSR_BMU_AP_ACC_WT1_REG (CSR_CPB_CSR_0_BASE + 0x214) /* BMU指定地址访问端口的权重配置 */ +#define CSR_CPB_CSR_TI_ACC_TO_TH_REG (CSR_CPB_CSR_0_BASE + 0x218) /* TI Mem非主Mem访问超时时间配置 */ +#define CSR_CPB_CSR_BMP_AM_TH_REG (CSR_CPB_CSR_0_BASE + 0x220) /* 每个ROW的Bitmap 快空门限配置 */ +#define CSR_CPB_CSR_BK_EXHT_TH_REG (CSR_CPB_CSR_0_BASE + 0x224) /* 每个BANK的Cell地址快耗完的门限配置 */ +#define CSR_CPB_CSR_CELL_RD_RLS_EN_REG (CSR_CPB_CSR_0_BASE + 0x228) /* Cell读释放使能配置 */ +#define CSR_CPB_CSR_CPB_AGE_CFG_REG (CSR_CPB_CSR_0_BASE + 0x258) /* CPB Cell老化公共配置寄存器 */ +#define CSR_CPB_CSR_CPB_AGE_TO_TH_REG (CSR_CPB_CSR_0_BASE + 0x25C) /* CPB Cell老化时间配置 */ +#define CSR_CPB_CSR_BK_AGE_CFG_0_REG (CSR_CPB_CSR_0_BASE + 0x260) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_1_REG (CSR_CPB_CSR_0_BASE + 0x264) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_2_REG (CSR_CPB_CSR_0_BASE + 0x268) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_3_REG (CSR_CPB_CSR_0_BASE + 0x26C) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_4_REG (CSR_CPB_CSR_0_BASE + 0x270) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_5_REG (CSR_CPB_CSR_0_BASE + 0x274) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_6_REG (CSR_CPB_CSR_0_BASE + 0x278) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_7_REG (CSR_CPB_CSR_0_BASE + 0x27C) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_0_REG (CSR_CPB_CSR_0_BASE + 0x280) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_1_REG (CSR_CPB_CSR_0_BASE + 0x284) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_2_REG (CSR_CPB_CSR_0_BASE + 0x288) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_3_REG (CSR_CPB_CSR_0_BASE + 0x28C) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_4_REG (CSR_CPB_CSR_0_BASE + 0x290) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_5_REG (CSR_CPB_CSR_0_BASE + 0x294) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_6_REG (CSR_CPB_CSR_0_BASE + 0x298) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_7_REG (CSR_CPB_CSR_0_BASE + 0x29C) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_0_REG (CSR_CPB_CSR_0_BASE + 0x2A0) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_1_REG (CSR_CPB_CSR_0_BASE + 0x2A4) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_2_REG (CSR_CPB_CSR_0_BASE + 0x2A8) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_3_REG (CSR_CPB_CSR_0_BASE + 0x2AC) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_4_REG (CSR_CPB_CSR_0_BASE + 0x2B0) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_5_REG (CSR_CPB_CSR_0_BASE + 0x2B4) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_6_REG (CSR_CPB_CSR_0_BASE + 0x2B8) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_7_REG (CSR_CPB_CSR_0_BASE + 0x2BC) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_0_REG (CSR_CPB_CSR_0_BASE + 0x2C0) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_1_REG (CSR_CPB_CSR_0_BASE + 0x2C4) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_2_REG (CSR_CPB_CSR_0_BASE + 0x2C8) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_3_REG (CSR_CPB_CSR_0_BASE + 0x2CC) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_4_REG (CSR_CPB_CSR_0_BASE + 0x2D0) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_5_REG (CSR_CPB_CSR_0_BASE + 0x2D4) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_6_REG (CSR_CPB_CSR_0_BASE + 0x2D8) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_7_REG (CSR_CPB_CSR_0_BASE + 0x2DC) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT0_REG (CSR_CPB_CSR_0_BASE + 0x300) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT1_REG (CSR_CPB_CSR_0_BASE + 0x304) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT2_REG (CSR_CPB_CSR_0_BASE + 0x308) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT3_REG (CSR_CPB_CSR_0_BASE + 0x30C) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT0_REG (CSR_CPB_CSR_0_BASE + 0x310) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT1_REG (CSR_CPB_CSR_0_BASE + 0x314) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT2_REG (CSR_CPB_CSR_0_BASE + 0x318) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT3_REG (CSR_CPB_CSR_0_BASE + 0x31C) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_CPB_MIN_RSC_HIS_CNT_REG (CSR_CPB_CSR_0_BASE + 0x320) /* CPB剩余最小资源的历史记录 */ +#define CSR_CPB_CSR_BMU_RSC_HIS_CNT_CLR_REG (CSR_CPB_CSR_0_BASE + 0x324) /* CPB BMU的资源历史记录清除配置 */ +#define CSR_CPB_CSR_BMU_BP_STA_REG (CSR_CPB_CSR_0_BASE + 0x328) /* CPB BMU的反压状态指示寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_0_REG (CSR_CPB_CSR_0_BASE + 0x330) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_1_REG (CSR_CPB_CSR_0_BASE + 0x334) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_2_REG (CSR_CPB_CSR_0_BASE + 0x338) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_3_REG (CSR_CPB_CSR_0_BASE + 0x33C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_4_REG (CSR_CPB_CSR_0_BASE + 0x340) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_5_REG (CSR_CPB_CSR_0_BASE + 0x344) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_6_REG (CSR_CPB_CSR_0_BASE + 0x348) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_7_REG (CSR_CPB_CSR_0_BASE + 0x34C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_8_REG (CSR_CPB_CSR_0_BASE + 0x350) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_9_REG (CSR_CPB_CSR_0_BASE + 0x354) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_10_REG (CSR_CPB_CSR_0_BASE + 0x358) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_11_REG (CSR_CPB_CSR_0_BASE + 0x35C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_12_REG (CSR_CPB_CSR_0_BASE + 0x360) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_13_REG (CSR_CPB_CSR_0_BASE + 0x364) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_14_REG (CSR_CPB_CSR_0_BASE + 0x368) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_15_REG (CSR_CPB_CSR_0_BASE + 0x36C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_16_REG (CSR_CPB_CSR_0_BASE + 0x370) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_17_REG (CSR_CPB_CSR_0_BASE + 0x374) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_18_REG (CSR_CPB_CSR_0_BASE + 0x378) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_19_REG (CSR_CPB_CSR_0_BASE + 0x37C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_20_REG (CSR_CPB_CSR_0_BASE + 0x380) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_21_REG (CSR_CPB_CSR_0_BASE + 0x384) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_22_REG (CSR_CPB_CSR_0_BASE + 0x388) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_23_REG (CSR_CPB_CSR_0_BASE + 0x38C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_24_REG (CSR_CPB_CSR_0_BASE + 0x390) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_25_REG (CSR_CPB_CSR_0_BASE + 0x394) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_26_REG (CSR_CPB_CSR_0_BASE + 0x398) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_27_REG (CSR_CPB_CSR_0_BASE + 0x39C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_28_REG (CSR_CPB_CSR_0_BASE + 0x3A0) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_29_REG (CSR_CPB_CSR_0_BASE + 0x3A4) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_30_REG (CSR_CPB_CSR_0_BASE + 0x3A8) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_31_REG (CSR_CPB_CSR_0_BASE + 0x3AC) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x3B0) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x3B4) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x3B8) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x3BC) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_STF_RSP_API_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_0_BASE + 0x830) /* 内部存储reponse/push API实体的信用 \ + */ +#define CSR_CPB_CSR_STF_PSH_CMD_WT_REG (CSR_CPB_CSR_0_BASE + 0x834) +#define CSR_CPB_CSR_STF_COL_DEL_MD_HDR_EN_REG (CSR_CPB_CSR_0_BASE + 0x838) +#define CSR_CPB_CSR_STF_RD_REQ_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x83C) +#define CSR_CPB_CSR_STF_RD_CTRL_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x840) +#define CSR_CPB_CSR_CPB_STF_API_CRDT_INIT_REG (CSR_CPB_CSR_0_BASE + 0x844) +#define CSR_CPB_CSR_STF_STR_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x848) +#define CSR_CPB_CSR_STF_STR_API_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x84C) +#define CSR_CPB_CSR_STF_CMD_API_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x850) +#define CSR_CPB_CSR_STF_ACKSTR_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x854) /* streamout ACK FQ FIFO的将满阈值 */ +#define CSR_CPB_CSR_STF_MSG_VFID_CTL_REG (CSR_CPB_CSR_0_BASE + 0x860) +#define CSR_CPB_CSR_CT_DMA_NRET_CFG_REG (CSR_CPB_CSR_0_BASE + 0x864) /* DMA normal return配置寄存器 */ +#define CSR_CPB_CSR_CT_COL_SRC_TAG_H_CFG_REG (CSR_CPB_CSR_0_BASE + 0x868) /* 聚合时src_tag_h步进控制寄存器 */ +#define CSR_CPB_CSR_CT_DEALC_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x870) +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_CFG_REG (CSR_CPB_CSR_0_BASE + 0x910) /* STF IQ Push请求FIFO配置 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_CFG_REG (CSR_CPB_CSR_0_BASE + 0x920) /* STF IQ Link请求FIFO配置 */ +#define CSR_CPB_CSR_LINK_WR_FIFO_CFG_REG (CSR_CPB_CSR_0_BASE + 0x924) /* Link WR请求FIFO配置 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1500) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1504) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1508) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x150C) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1510) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1514) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1518) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x151C) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_WR_RD_DAT_IN_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1520) /* statefull tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_WR_RD_DAT_IN_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1524) /* statefull tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1530) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1534) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1538) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x153C) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1540) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1544) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1548) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x154C) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1550) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1554) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1558) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x155C) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1560) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1564) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1568) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x156C) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1570) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1574) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1578) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x157C) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1580) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1584) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1588) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x158C) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1590) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1594) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1598) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x159C) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_WR_DI_CTRL_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x15A4) /* stateful tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_WR_DI_CTRL_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x15A8) /* stateful tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_FIFO_OV_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15B0) +#define CSR_CPB_CSR_STF_FIFO_OV_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15B4) +#define CSR_CPB_CSR_STF_FIFO_UF_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15B8) +#define CSR_CPB_CSR_STF_FIFO_UF_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15BC) +#define CSR_CPB_CSR_CT_EXT_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_0_BASE + 0x15C0) /* extend mode push时，extend cell释放FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_PCOL_NUM_ERR_REG \ + (CSR_CPB_CSR_0_BASE + 0x15C4) /* 弱聚合包数过多，导致发送给tile的src_tag_h错误 */ +#define CSR_CPB_CSR_STFWR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15D8) /* STF WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFWR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15DC) /* STF WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15E0) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15E4) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x15E8) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x15EC) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15F0) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15F4) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x15F8) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x15FC) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1620) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1624) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1628) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x162C) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1630) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1634) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1638) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x163C) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1640) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1644) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1648) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x164C) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1650) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1654) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1658) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x165C) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_0_REG (CSR_CPB_CSR_0_BASE + 0x1690) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_1_REG (CSR_CPB_CSR_0_BASE + 0x1694) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_2_REG (CSR_CPB_CSR_0_BASE + 0x1698) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_3_REG (CSR_CPB_CSR_0_BASE + 0x169C) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_0_REG (CSR_CPB_CSR_0_BASE + 0x16A0) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_1_REG (CSR_CPB_CSR_0_BASE + 0x16A4) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_2_REG (CSR_CPB_CSR_0_BASE + 0x16A8) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_3_REG (CSR_CPB_CSR_0_BASE + 0x16AC) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_LINK_WR_FIFO_STA_REG (CSR_CPB_CSR_0_BASE + 0x16B0) /* LINK WR FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIQ_FIFO_OF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x16C0) /* CBP IQ接口模块FIFO Overflow状态记录 */ +#define CSR_CPB_CSR_CIQ_FIFO_UF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x16C4) /* CBP IQ接口模块FIFO Underflow状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x16C8) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x16CC) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x16D0) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x16D4) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_ERR_REG (CSR_CPB_CSR_0_BASE + 0x16E0) /* CBP IQ接口模块错误状态记录 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1BA0) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1BA4) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1BA8) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1BAC) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1BB0) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1BB4) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1BB8) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1BBC) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1BC0) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1BC4) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1BC8) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1BCC) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1BD0) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1BD4) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1BD8) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1BDC) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1BE0) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1BE4) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1BE8) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1BEC) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1BF0) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1BF4) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1BF8) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1BFC) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1C00) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1C04) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1C08) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1C0C) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1C10) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1C14) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1C18) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1C1C) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1C20) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1C24) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1C28) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1C2C) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1C30) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1C34) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1C38) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1C3C) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1C40) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1C44) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1C48) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1C4C) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1C50) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1C54) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1C58) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1C5C) /* BMP AGE Mem错误历史记录寄存器 */ + +/* CPB_CSR_1 Base address of Module's Register */ +#define CSR_CPB_CSR_1_BASE (0x4000) + +/* **************************************************************************** */ +/* CPB_CSR_1 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_CIT_DATA_IN_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x500) +#define CSR_CPB_CSR_CIT_DEALC_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x504) +#define CSR_CPB_CSR_CIT_EC_CH_REG (CSR_CPB_CSR_1_BASE + 0x508) /* EC通道配置 */ +#define CSR_CPB_CSR_CPR_PRO_WT_REG (CSR_CPB_CSR_1_BASE + 0x600) +#define CSR_CPB_CSR_CPR_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_1_BASE + 0x604) +#define CSR_CPB_CSR_CPR_DEALC_TX_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x610) +#define CSR_CPB_CSR_CPR_DEALC_RX_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x614) +#define CSR_CPB_CSR_CPR_PRLS_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x618) +#define CSR_CPB_CSR_CPR_COL_TH_REG (CSR_CPB_CSR_1_BASE + 0x61C) +#define CSR_CPB_CSR_CPR_PRO_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x630) +#define CSR_CPB_CSR_CPR_PRO_DEALC_TX_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x634) +#define CSR_CPB_CSR_CPR_PRO_DEALC_RX_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x638) +#define CSR_CPB_CSR_CPR_PRO_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_1_BASE + 0x63C) +#define CSR_CPB_CSR_CPR_PRO_DEALC_RP_TH_REG (CSR_CPB_CSR_1_BASE + 0x640) +#define CSR_CPB_CSR_CPR_PRO_RRDY_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x644) +#define CSR_CPB_CSR_CPR_OUT_ERR_EN_REG (CSR_CPB_CSR_1_BASE + 0x648) /* CPB输出给PERX的err bit有效使能 */ +#define CSR_CPB_CSR_CIT_DAT_FIFO_STA_REG (CSR_CPB_CSR_1_BASE + 0x1100) /* IPSUTX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIT_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_1_BASE + 0x1104) /* IPSUTX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIT_IN_PKT_SOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1120) /* CPB从IPSUTX接收到报文SOP数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_PKT_EOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1124) /* CPB从IPSUTX接收到报文EOP数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_0_REG (CSR_CPB_CSR_1_BASE + 0x1130) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_1_REG (CSR_CPB_CSR_1_BASE + 0x1134) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_2_REG (CSR_CPB_CSR_1_BASE + 0x1138) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_3_REG (CSR_CPB_CSR_1_BASE + 0x113C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_4_REG (CSR_CPB_CSR_1_BASE + 0x1140) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_5_REG (CSR_CPB_CSR_1_BASE + 0x1144) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_6_REG (CSR_CPB_CSR_1_BASE + 0x1148) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_7_REG (CSR_CPB_CSR_1_BASE + 0x114C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_8_REG (CSR_CPB_CSR_1_BASE + 0x1150) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_9_REG (CSR_CPB_CSR_1_BASE + 0x1154) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_10_REG (CSR_CPB_CSR_1_BASE + 0x1158) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_11_REG (CSR_CPB_CSR_1_BASE + 0x115C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_12_REG (CSR_CPB_CSR_1_BASE + 0x1160) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_13_REG (CSR_CPB_CSR_1_BASE + 0x1164) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_14_REG (CSR_CPB_CSR_1_BASE + 0x1168) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_15_REG (CSR_CPB_CSR_1_BASE + 0x116C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_16_REG (CSR_CPB_CSR_1_BASE + 0x1170) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_17_REG (CSR_CPB_CSR_1_BASE + 0x1174) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_18_REG (CSR_CPB_CSR_1_BASE + 0x1178) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_19_REG (CSR_CPB_CSR_1_BASE + 0x117C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_20_REG (CSR_CPB_CSR_1_BASE + 0x1180) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_21_REG (CSR_CPB_CSR_1_BASE + 0x1184) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_22_REG (CSR_CPB_CSR_1_BASE + 0x1188) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_23_REG (CSR_CPB_CSR_1_BASE + 0x118C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_RPT_IQ_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1190) /* CPB向IQ通告PCI次数的统计每个报文仅统计一次 */ +#define CSR_CPB_CSR_CIT_IQ_BP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1194) /* IQ反压CPB发送侧报文通告的次数 */ +#define CSR_CPB_CSR_CIT_PAL_LESS_STA_REG (CSR_CPB_CSR_1_BASE + 0x1198) /* 发送侧非UP（MCU）通道预扣状态寄存器 */ +#define CSR_CPB_CSR_CIT_PAL_ERR_REG (CSR_CPB_CSR_1_BASE + 0x119C) /* 发送侧非UP（MCU）通道预扣不足错误中断 */ +#define CSR_CPB_CSR_CIT_SCHNL_ERR_REG (CSR_CPB_CSR_1_BASE + 0x11A0) /* IPSUTX送给CPB报文对应的channel越界错误 */ +#define CSR_CPB_CSR_CIT_FIFO_ERR_REG (CSR_CPB_CSR_1_BASE + 0x11A4) /* IPSUTX_CPB接口FIFO溢出错误 */ +#define CSR_CPB_CSR_CIT_EC_ILLEGAL_REG (CSR_CPB_CSR_1_BASE + 0x11A8) /* IPSUTX送过来的EC channel配置非法 */ +#define CSR_CPB_CSR_CIT_FIFO_RAM_ERR_REG (CSR_CPB_CSR_1_BASE + 0x11B0) /* CIT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x1200) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x1204) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x1208) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x120C) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x1210) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x1214) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x1218) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x121C) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x1220) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x1224) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_1_BASE + 0x1228) /* CPB_PERX模块通告PRM cell释放FIFO的状态寄存器（经调度送出） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x122C) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x1230) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x1234) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x1238) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x123C) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_PRLS_FIFO_STA_REG (CSR_CPB_CSR_1_BASE + 0x1240) /* CPB_PERX接口PRLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_OUT_PKT_SOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1244) /* CPB输出给PERX报文SOP数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_PKT_EOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1248) /* CPB输出给PERX报文EOP数量的统计 */ +#define CSR_CPB_CSR_CPR_RRDY_SIDE_ERR_REG (CSR_CPB_CSR_1_BASE + 0x124C) /* FC业务释放报文对应的源错误 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_0_REG (CSR_CPB_CSR_1_BASE + 0x1250) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_1_REG (CSR_CPB_CSR_1_BASE + 0x1254) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_2_REG (CSR_CPB_CSR_1_BASE + 0x1258) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_3_REG (CSR_CPB_CSR_1_BASE + 0x125C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_4_REG (CSR_CPB_CSR_1_BASE + 0x1260) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_5_REG (CSR_CPB_CSR_1_BASE + 0x1264) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_6_REG (CSR_CPB_CSR_1_BASE + 0x1268) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_7_REG (CSR_CPB_CSR_1_BASE + 0x126C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_8_REG (CSR_CPB_CSR_1_BASE + 0x1270) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_9_REG (CSR_CPB_CSR_1_BASE + 0x1274) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_10_REG (CSR_CPB_CSR_1_BASE + 0x1278) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_11_REG (CSR_CPB_CSR_1_BASE + 0x127C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_12_REG (CSR_CPB_CSR_1_BASE + 0x1280) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_13_REG (CSR_CPB_CSR_1_BASE + 0x1284) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_14_REG (CSR_CPB_CSR_1_BASE + 0x1288) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_15_REG (CSR_CPB_CSR_1_BASE + 0x128C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_16_REG (CSR_CPB_CSR_1_BASE + 0x1290) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_17_REG (CSR_CPB_CSR_1_BASE + 0x1294) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_18_REG (CSR_CPB_CSR_1_BASE + 0x1298) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_19_REG (CSR_CPB_CSR_1_BASE + 0x129C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_20_REG (CSR_CPB_CSR_1_BASE + 0x12A0) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_21_REG (CSR_CPB_CSR_1_BASE + 0x12A4) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_22_REG (CSR_CPB_CSR_1_BASE + 0x12A8) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x12AC) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x12B0) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x12B4) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x12B8) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x12BC) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x12C0) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x12C4) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x12C8) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x12CC) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x12D0) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_FIFO_OV_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12D4) /* CPB_PERX_PRO中FIFO上溢错误 */ +#define CSR_CPB_CSR_CPR_FIFO_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12D8) /* CPB_PERX_MISC接口模块FIFO溢出错误 */ +#define CSR_CPB_CSR_CPR_FIFO_UF_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12DC) /* CPB_PERX_PRO模块FIFO下溢错误 */ +#define CSR_CPB_CSR_CPR_SGE_CRDT_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12E0) /* 发送往CPI的sge信用值微码填充错误 */ +#define CSR_CPB_CSR_CPR_SGE_CRDT_ERR_DMA_HED_L_REG (CSR_CPB_CSR_1_BASE + 0x12E4) /* sge预扣错误时微码填充的B8yte数据 \ + */ +#define CSR_CPB_CSR_CPR_SGE_CRDT_ERR_DMA_HED_H_REG (CSR_CPB_CSR_1_BASE + 0x12E8) /* sge预扣错误时微码填充的B8yte数据 \ + */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_1_BASE + 0x12EC) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_1_BASE + 0x12F0) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_1_BASE + 0x12F4) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_1_BASE + 0x12F8) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_4_REG (CSR_CPB_CSR_1_BASE + 0x12FC) /* CPR FIFO Mem错误历史记录寄存器 */ + +/* CPB_CSR_2 Base address of Module's Register */ +#define CSR_CPB_CSR_2_BASE (0x6000) + +/* **************************************************************************** */ +/* CPB_CSR_2 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_STL_RSP_API_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_2_BASE + 0x800) /* 内部存储reponse/push API实体的信用 \ + */ +#define CSR_CPB_CSR_STL_PSH_CMD_WT_REG (CSR_CPB_CSR_2_BASE + 0x804) +#define CSR_CPB_CSR_STL_RD_REQ_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x80C) +#define CSR_CPB_CSR_STL_RD_CTRL_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x810) +#define CSR_CPB_CSR_CPB_STL_API_CRDT_INIT_REG (CSR_CPB_CSR_2_BASE + 0x814) +#define CSR_CPB_CSR_STL_STR_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x818) +#define CSR_CPB_CSR_STL_STR_API_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x81C) +#define CSR_CPB_CSR_STL_CMD_API_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x820) +#define CSR_CPB_CSR_STL_ACKSTR_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x824) /* streamout ACK FQ FIFO的将满阈值 */ +#define CSR_CPB_CSR_CDT_CRDT_CFG_REG (CSR_CPB_CSR_2_BASE + 0x8A0) /* ROB与CPB间的入口FIFO的信用配置 */ +#define CSR_CPB_CSR_CDT_PSH_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x8B0) /* ROB Push FIFO的配置 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x900) /* STL IQ Push请求FIFO配置 */ +#define CSR_CPB_CSR_INNER_CHN_MAP_REG (CSR_CPB_CSR_2_BASE + 0x980) /* RX CPI Channel在CPB内部的散列分配模式配置 */ +#define CSR_CPB_CSR_DRP_ACK_TH_REG (CSR_CPB_CSR_2_BASE + 0x984) /* 报文Drop释放的Cell通告门限配置 */ +#define CSR_CPB_CSR_OQRX_PD_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x990) /* OQ调往RX方向的PD FIFO配置 */ +#define CSR_CPB_CSR_OQTX_PD_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x994) /* OQ调往TX方向的PD FIFO配置 */ +#define CSR_CPB_CSR_DRP_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x998) /* 报文Drop 请求FIFO配置 */ +#define CSR_CPB_CSR_DRP_TXRLS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x99C) /* TX方向报文Drop RRL FIFO配置 */ +#define CSR_CPB_CSR_DRP_RXRLS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x9A0) /* RX方向报文Drop RRL FIFO配置 */ +#define CSR_CPB_CSR_FDRP_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x9A4) /* FTSO报文Drop 请求FIFO配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT0_REG (CSR_CPB_CSR_2_BASE + 0xA00) /* CPB_RX_NOR_0内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT1_REG (CSR_CPB_CSR_2_BASE + 0xA04) /* CPB_RX_NOR_1内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT2_REG (CSR_CPB_CSR_2_BASE + 0xA08) /* CPB_RX_NOR_2内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT3_REG (CSR_CPB_CSR_2_BASE + 0xA0C) /* CPB_RX_NOR_3内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_LB_CHN_WT3_REG (CSR_CPB_CSR_2_BASE + 0xA10) /* CPB_RX_LB内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RXLB_PORT_WT_0_REG (CSR_CPB_CSR_2_BASE + 0xA14) /* RXLB0内部8个port的WRR权重配置 */ +#define CSR_CPB_CSR_RXLB_PORT_WT_1_REG (CSR_CPB_CSR_2_BASE + 0xA18) /* RXLB1内部8个port的WRR权重配置 */ +#define CSR_CPB_CSR_COS_CHN_RXLB_CFG_0_REG (CSR_CPB_CSR_2_BASE + 0xA1C) /* RXLB的64个Cos的划分配置0 */ +#define CSR_CPB_CSR_COS_CHN_RXLB_CFG_1_REG (CSR_CPB_CSR_2_BASE + 0xA20) /* RXLB的64个Cos的划分配置1 */ +#define CSR_CPB_CSR_CPB_RX_CRDT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA30) /* CPB_RX相关信用配置 */ +#define CSR_CPB_CSR_CPB_RX_IDX_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA34) /* CPB_RX IDX信用配置 */ +#define CSR_CPB_CSR_CHN5_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA40) /* CPI侧Chn5 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN6_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA44) /* CPI侧Chn6 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN7_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA48) /* CPI侧Chn7 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN8_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA4C) /* CPI侧Chn8 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN9_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA50) /* CPI侧Chn9 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN10_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA54) /* CPI侧Chn10 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN11_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA58) /* CPI侧Chn11 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN12_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA5C) /* CPI侧Chn12 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN13_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA60) /* CPI侧Chn13 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN14_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA64) /* CPI侧Chn14 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN15_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA68) /* CPI侧Chn15 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN16_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA6C) /* CPI侧Chn16 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN17_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA70) /* CPI侧Chn17 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN18_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA74) /* CPI侧Chn18 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN19_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA78) /* CPI侧Chn19 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN20_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA7C) /* CPI侧Chn20 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN21_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA80) /* CPI侧Chn21 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN22_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA84) /* CPI侧Chn22 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN23_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA88) /* CPI侧Chn23 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN24_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA8C) /* CPI侧Chn24 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_HOST0_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA90) /* CPI侧Host0所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST1_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA94) /* CPI侧Host1所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST2_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA98) /* CPI侧Host2所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST3_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA9C) /* CPI侧Host3所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST4_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xAA0) /* CPI侧Host4所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_SGE_SHR_BP_TH_REG (CSR_CPB_CSR_2_BASE + 0xAA4) /* CPI侧SGE Share空间反压门限配置 */ +#define CSR_CPB_CSR_SGE_BP_GAP_REG (CSR_CPB_CSR_2_BASE + 0xAA8) /* CPB内部的CPI侧每个Chn的SGE信用反压的Gap门限配置 */ +#define CSR_CPB_CSR_CHN5_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAB0) /* CPI侧Chn5 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN6_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAB4) /* CPI侧Chn6 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN7_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAB8) /* CPI侧Chn7 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN8_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xABC) /* CPI侧Chn8 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN9_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAC0) /* CPI侧Chn9 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN10_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAC4) /* CPI侧Chn10 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN11_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAC8) /* CPI侧Chn11 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN12_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xACC) /* CPI侧Chn12 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN13_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAD0) /* CPI侧Chn13 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN14_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAD4) /* CPI侧Chn14 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN15_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAD8) /* CPI侧Chn15 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN16_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xADC) /* CPI侧Chn16 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN17_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAE0) /* CPI侧Chn17 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN18_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAE4) /* CPI侧Chn18 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN19_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAE8) /* CPI侧Chn19 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN20_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAEC) /* CPI侧Chn20 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN21_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAF0) /* CPI侧Chn21 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN22_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAF4) /* CPI侧Chn22 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN23_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAF8) /* CPI侧Chn23 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN24_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAFC) /* CPI侧Chn24 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_HOST0_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB00) /* CPI侧Host0所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST1_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB04) /* CPI侧Host1所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST2_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB08) /* CPI侧Host2所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST3_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB0C) /* CPI侧Host3所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST4_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB10) /* CPI侧Host4所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_DAT_SHR_BP_TH_REG (CSR_CPB_CSR_2_BASE + 0xB14) /* CPI侧DAT Share空间反压门限配置 */ +#define CSR_CPB_CSR_DAT_BP_GAP_REG (CSR_CPB_CSR_2_BASE + 0xB18) /* CPB内部的CPI侧每个Chn的DAT信用反压的Gap门限配置 */ +#define CSR_CPB_CSR_RX_MPU_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB20) /* RX MPU通道DAT信用配置寄存器 */ +#define CSR_CPB_CSR_RX_LB0_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB24) /* RX Loopback0通道DAT信用配置寄存器 */ +#define CSR_CPB_CSR_RX_LB1_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB28) /* RX Loopback1通道DAT信用配置寄存器 */ +#define CSR_CPB_CSR_RXLB_DAT_BP_GAP_REG (CSR_CPB_CSR_2_BASE + 0xB30) /* CPB内部的RXLB Chn的DAT信用反压的Gap门限配置 */ +#define CSR_CPB_CSR_RXPD_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB40) /* CPB_RX的PD请求FIFO配置 */ +#define CSR_CPB_CSR_RXMPU_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB44) /* CPB_RX的to MPU的PD请求FIFO配置 */ +#define CSR_CPB_CSR_RXLB_COS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB48) /* RXLB COS PD请求FIFO配置 */ +#define CSR_CPB_CSR_RX_IDX_WT_REG (CSR_CPB_CSR_2_BASE + 0xB54) /* CPB_RX内部5个PRO间IDX信用申请权重配置 */ +#define CSR_CPB_CSR_RX_HOST0_CHN_M_REG (CSR_CPB_CSR_2_BASE + 0xB58) /* RX Host0 8 Chn的配置 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB60) /* RX TSO3 RLS请求FIFO配置 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1400) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1404) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1408) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x140C) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1410) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1414) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1418) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x141C) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_WR_RD_DAT_IN_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1420) /* stateless tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_WR_RD_DAT_IN_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1424) /* stateless tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1430) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1434) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1438) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x143C) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1440) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1444) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1448) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x144C) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1450) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1454) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1458) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x145C) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1460) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1464) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1468) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x146C) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1470) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1474) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1478) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x147C) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1480) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1484) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x1488) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x148C) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1490) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1494) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1498) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x149C) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_WR_DI_CTRL_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x14A4) /* stateless tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_WR_DI_CTRL_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x14A8) /* stateless tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_FIFO_OV_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14B0) +#define CSR_CPB_CSR_STL_FIFO_OV_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14B4) +#define CSR_CPB_CSR_STL_FIFO_UF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14B8) +#define CSR_CPB_CSR_STL_FIFO_UF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14BC) +#define CSR_CPB_CSR_STLWR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14C0) /* STL WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLWR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14C4) /* STL WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14D0) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14D4) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x14D8) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_2_BASE + 0x14DC) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14E0) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14E4) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x14E8) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_2_BASE + 0x14EC) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CDT_PSH_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x15C8) /* CDT PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_CDT_FIFO_ERR_REG (CSR_CPB_CSR_2_BASE + 0x15CC) /* CDT FIFO 溢出状态记录 */ +#define CSR_CPB_CSR_CDT_CRDT_STA_REG (CSR_CPB_CSR_2_BASE + 0x15D0) /* CDT Credit状态指示 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1600) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1604) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x1608) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x160C) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1610) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1614) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x1618) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x161C) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_FLOWPAC_PSH_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1660) /* STLIQ给ROB的Flowpac Push请求统计 */ +#define CSR_CPB_CSR_NONFLOWPAC_PSH_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1664) /* STLIQ给ROB的nonflowpac Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1680) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1684) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1688) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x168C) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_ROB_PSH_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x16B4) /* ROB PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_EPD_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1700) /* QU OQ调往RX方向总的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1704) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1708) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x170C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x1710) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_4_REG (CSR_CPB_CSR_2_BASE + 0x1714) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_5_REG (CSR_CPB_CSR_2_BASE + 0x1718) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_6_REG (CSR_CPB_CSR_2_BASE + 0x171C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_7_REG (CSR_CPB_CSR_2_BASE + 0x1720) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_8_REG (CSR_CPB_CSR_2_BASE + 0x1724) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_9_REG (CSR_CPB_CSR_2_BASE + 0x1728) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_10_REG (CSR_CPB_CSR_2_BASE + 0x172C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_11_REG (CSR_CPB_CSR_2_BASE + 0x1730) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_12_REG (CSR_CPB_CSR_2_BASE + 0x1734) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_13_REG (CSR_CPB_CSR_2_BASE + 0x1738) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_14_REG (CSR_CPB_CSR_2_BASE + 0x173C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_15_REG (CSR_CPB_CSR_2_BASE + 0x1740) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_16_REG (CSR_CPB_CSR_2_BASE + 0x1744) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_17_REG (CSR_CPB_CSR_2_BASE + 0x1748) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_18_REG (CSR_CPB_CSR_2_BASE + 0x174C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_19_REG (CSR_CPB_CSR_2_BASE + 0x1750) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_20_REG (CSR_CPB_CSR_2_BASE + 0x1754) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_21_REG (CSR_CPB_CSR_2_BASE + 0x1758) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_22_REG (CSR_CPB_CSR_2_BASE + 0x175C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_EPD_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1760) /* QU OQ调往TX方向总的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1764) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1768) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x176C) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x1770) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_4_REG (CSR_CPB_CSR_2_BASE + 0x1774) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_5_REG (CSR_CPB_CSR_2_BASE + 0x1778) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_6_REG (CSR_CPB_CSR_2_BASE + 0x177C) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_7_REG (CSR_CPB_CSR_2_BASE + 0x1780) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_8_REG (CSR_CPB_CSR_2_BASE + 0x1784) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_9_REG (CSR_CPB_CSR_2_BASE + 0x1788) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_10_REG (CSR_CPB_CSR_2_BASE + 0x178C) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1790) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1794) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1798) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x179C) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_4_REG \ + (CSR_CPB_CSR_2_BASE + 0x17A0) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_5_REG \ + (CSR_CPB_CSR_2_BASE + 0x17A4) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_6_REG \ + (CSR_CPB_CSR_2_BASE + 0x17A8) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_7_REG \ + (CSR_CPB_CSR_2_BASE + 0x17AC) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_DRP_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17B0) /* QU OQ报文Drop请求次数统计 */ +#define CSR_CPB_CSR_RX_TSO3_DRP_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17B4) /* RX方向TSO3报文丢弃数量统计 */ +#define CSR_CPB_CSR_TX_TSO3_DRP_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17B8) /* TX方向TSO3报文丢弃数量统计 */ +#define CSR_CPB_CSR_DRP_EOP_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17BC) /* CPB DROP接口丢弃报文量统计 */ +#define CSR_CPB_CSR_RX_EPD_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17D0) /* RX EPD FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_EPD_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17D4) /* TX EPD FIFO状态寄存器 */ +#define CSR_CPB_CSR_NDRP_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17D8) /* NDRP FIFO状态寄存器 */ +#define CSR_CPB_CSR_DRP_RXRLS_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17DC) /* DRP RXRLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_DRP_TXRLS_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17E0) /* DRP TXRLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_FDRP_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17E4) /* FDRP FIFO状态寄存器 */ +#define CSR_CPB_CSR_FTSO_DRP_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17E8) /* FAST TSO丢弃请求统计 */ +#define CSR_CPB_CSR_COQ_FIFO_OF_ERR_REG (CSR_CPB_CSR_2_BASE + 0x17F0) /* CBP OQ接口模块FIFO Overflow状态记录 */ +#define CSR_CPB_CSR_COQ_FIFO_UF_ERR_REG (CSR_CPB_CSR_2_BASE + 0x17F4) /* CBP OQ接口模块FIFO Uderflow状态记录 */ +#define CSR_CPB_CSR_COQ_ERR_REG (CSR_CPB_CSR_2_BASE + 0x17F8) /* CBP OQ接口模块错误状态记录 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1800) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1804) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1808) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x180C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x1810) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_5_REG (CSR_CPB_CSR_2_BASE + 0x1814) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_6_REG (CSR_CPB_CSR_2_BASE + 0x1818) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_7_REG (CSR_CPB_CSR_2_BASE + 0x181C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_8_REG (CSR_CPB_CSR_2_BASE + 0x1820) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_9_REG (CSR_CPB_CSR_2_BASE + 0x1824) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_10_REG (CSR_CPB_CSR_2_BASE + 0x1828) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_11_REG (CSR_CPB_CSR_2_BASE + 0x182C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_12_REG (CSR_CPB_CSR_2_BASE + 0x1830) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_13_REG (CSR_CPB_CSR_2_BASE + 0x1834) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_14_REG (CSR_CPB_CSR_2_BASE + 0x1838) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_15_REG (CSR_CPB_CSR_2_BASE + 0x183C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_16_REG (CSR_CPB_CSR_2_BASE + 0x1840) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_17_REG (CSR_CPB_CSR_2_BASE + 0x1844) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_18_REG (CSR_CPB_CSR_2_BASE + 0x1848) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_19_REG (CSR_CPB_CSR_2_BASE + 0x184C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1850) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1854) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1858) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x185C) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x1860) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_SHR_CRDT_STA_REG (CSR_CPB_CSR_2_BASE + 0x1864) /* RX方向CPI Share空间的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1870) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1874) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1878) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x187C) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_CHN_CRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1880) /* RX方向MPU及RXLB Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_CHN_CRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1884) /* RX方向MPU及RXLB Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_CHN_CRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1888) /* RX方向MPU及RXLB Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_IDX_CRDT_STA_REG (CSR_CPB_CSR_2_BASE + 0x188C) /* RX方向IDX的信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_FP_BMP_STA_REG (CSR_CPB_CSR_2_BASE + 0x1890) /* RXLB Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_EMPTY_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1894) /* RX方向PD FIFO empty状态寄存器0 */ +#define CSR_CPB_CSR_RXPD_FIFO_EMPTY_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1898) /* RX方向PD FIFO empty状态寄存器1 */ +#define CSR_CPB_CSR_RXPD_FIFO_EMPTY_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x189C) /* RX方向PD FIFO empty状态寄存器2 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x18A0) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x18A4) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x18A8) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x18AC) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x18B0) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_5_REG (CSR_CPB_CSR_2_BASE + 0x18B4) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_6_REG (CSR_CPB_CSR_2_BASE + 0x18B8) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_7_REG (CSR_CPB_CSR_2_BASE + 0x18BC) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_8_REG (CSR_CPB_CSR_2_BASE + 0x18C0) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_9_REG (CSR_CPB_CSR_2_BASE + 0x18C4) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_10_REG (CSR_CPB_CSR_2_BASE + 0x18C8) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1900) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1904) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1908) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x190C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x1910) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_5_REG (CSR_CPB_CSR_2_BASE + 0x1914) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_6_REG (CSR_CPB_CSR_2_BASE + 0x1918) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_7_REG (CSR_CPB_CSR_2_BASE + 0x191C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_8_REG (CSR_CPB_CSR_2_BASE + 0x1920) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_9_REG (CSR_CPB_CSR_2_BASE + 0x1924) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_10_REG (CSR_CPB_CSR_2_BASE + 0x1928) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_11_REG (CSR_CPB_CSR_2_BASE + 0x192C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_12_REG (CSR_CPB_CSR_2_BASE + 0x1930) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_13_REG (CSR_CPB_CSR_2_BASE + 0x1934) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_14_REG (CSR_CPB_CSR_2_BASE + 0x1938) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_15_REG (CSR_CPB_CSR_2_BASE + 0x193C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_16_REG (CSR_CPB_CSR_2_BASE + 0x1940) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_17_REG (CSR_CPB_CSR_2_BASE + 0x1944) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_18_REG (CSR_CPB_CSR_2_BASE + 0x1948) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_19_REG (CSR_CPB_CSR_2_BASE + 0x194C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_20_REG (CSR_CPB_CSR_2_BASE + 0x1950) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_21_REG (CSR_CPB_CSR_2_BASE + 0x1954) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_22_REG (CSR_CPB_CSR_2_BASE + 0x1958) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RX_CRDT_OF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x1990) /* RX方向Credit Overflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_RX_CRDT_OF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x1994) /* RX方向Credit Overflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_RX_CRDT_UF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x1998) /* RX方向Credit Underflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_RX_CRDT_UF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x199C) /* RX方向Credit Underflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_RXPD_FIFO_OF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x19A0) /* RX方向PD FIFO Overflow Err历史记录寄存器0 \ + */ +#define CSR_CPB_CSR_RXPD_FIFO_OF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x19A4) /* RX方向PD FIFO Overflow Err历史记录寄存器1 \ + */ +#define CSR_CPB_CSR_RXPD_FIFO_OF_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x19A8) /* RX方向PD FIFO Overflow Err历史记录寄存器2 \ + */ +#define CSR_CPB_CSR_RXPD_FIFO_UF_ERR_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x19B0) /* RX方向PD FIFO Underflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_RXPD_FIFO_UF_ERR_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x19B4) /* RX方向PD FIFO Underflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_RXPD_FIFO_UF_ERR_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x19B8) /* RX方向PD FIFO Underflow Err历史记录寄存器2 */ +#define CSR_CPB_CSR_RXLB_PD_RAM_ERR_REG (CSR_CPB_CSR_2_BASE + 0x19BC) /* RXLB PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPB_RX_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x19C0) /* CPB RX处理错误历史记录寄存器0 */ +#define CSR_CPB_CSR_CPB_RX_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x19C4) /* CPB RX处理错误历史记录寄存器1 */ +#define CSR_CPB_CSR_CPB_RX_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x19C8) /* CPB RX处理错误历史记录寄存器2 */ +#define CSR_CPB_CSR_CPB_RX_ERR_3_REG (CSR_CPB_CSR_2_BASE + 0x19CC) /* CPB RX处理错误历史记录寄存器3 */ +#define CSR_CPB_CSR_CPB_RX_ERR_4_REG (CSR_CPB_CSR_2_BASE + 0x19D0) /* CPB RX处理错误历史记录寄存器4 */ +#define CSR_CPB_CSR_CPB_RX_ERR_5_REG (CSR_CPB_CSR_2_BASE + 0x19D4) /* CPB RX处理错误历史记录寄存器5 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x19E0) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x19E4) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x19E8) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x19EC) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x19F0) /* RX TSO3 RLS FIFO状态寄存器 */ + +/* CPB_CSR_3 Base address of Module's Register */ +#define CSR_CPB_CSR_3_BASE (0x8000) + +/* **************************************************************************** */ +/* CPB_CSR_3 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_CPB_INDIR_DAT_0_REG (CSR_CPB_CSR_3_BASE + 0x180) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_1_REG (CSR_CPB_CSR_3_BASE + 0x184) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_2_REG (CSR_CPB_CSR_3_BASE + 0x188) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_3_REG (CSR_CPB_CSR_3_BASE + 0x18C) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_4_REG (CSR_CPB_CSR_3_BASE + 0x190) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_5_REG (CSR_CPB_CSR_3_BASE + 0x194) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_6_REG (CSR_CPB_CSR_3_BASE + 0x198) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_7_REG (CSR_CPB_CSR_3_BASE + 0x19C) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_8_REG (CSR_CPB_CSR_3_BASE + 0x1A0) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_9_REG (CSR_CPB_CSR_3_BASE + 0x1A4) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_10_REG (CSR_CPB_CSR_3_BASE + 0x1A8) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_11_REG (CSR_CPB_CSR_3_BASE + 0x1AC) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_12_REG (CSR_CPB_CSR_3_BASE + 0x1B0) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_13_REG (CSR_CPB_CSR_3_BASE + 0x1B4) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_14_REG (CSR_CPB_CSR_3_BASE + 0x1B8) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_15_REG (CSR_CPB_CSR_3_BASE + 0x1BC) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CIR_ALC_PRO_WT_REG (CSR_CPB_CSR_3_BASE + 0x400) +#define CSR_CPB_CSR_CIR_RPCI_PRO_WT_REG (CSR_CPB_CSR_3_BASE + 0x404) +#define CSR_CPB_CSR_CIR_ALC_MAC_NCSI_PORT_WT_REG (CSR_CPB_CSR_3_BASE + 0x408) +#define CSR_CPB_CSR_CIR_DATA_IN_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x410) +#define CSR_CPB_CSR_CIR_ALC_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x414) +#define CSR_CPB_CSR_CIR_RPCI_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x418) +#define CSR_CPB_CSR_CIR_ALC_RP_TH_REG (CSR_CPB_CSR_3_BASE + 0x41C) +#define CSR_CPB_CSR_CIR_DATA_IN_FIFO_DROP_TH_REG (CSR_CPB_CSR_3_BASE + 0x420) +#define CSR_CPB_CSR_CIR_IPSURX_BP_EN_REG (CSR_CPB_CSR_3_BASE + 0x424) +#define CSR_CPB_CSR_CIR_ALC_SHP_EN_REG (CSR_CPB_CSR_3_BASE + 0x428) /* CIR申请PRM限流300Mpps使能开关 */ +#define CSR_CPB_CSR_CPT_MAC03_TS_REG (CSR_CPB_CSR_3_BASE + 0x700) +#define CSR_CPB_CSR_CPT_MAC47_TS_REG (CSR_CPB_CSR_3_BASE + 0x704) +#define CSR_CPB_CSR_CPT_MACLB_TS_REG (CSR_CPB_CSR_3_BASE + 0x708) +#define CSR_CPB_CSR_CPT_TS_CFG_REG (CSR_CPB_CSR_3_BASE + 0x70C) +#define CSR_CPB_CSR_CPT_CRDT_INIT_REG (CSR_CPB_CSR_3_BASE + 0x710) +#define CSR_CPB_CSR_CPT_DEALC_TX_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x720) +#define CSR_CPB_CSR_CPT_DEALC_RX_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x724) +#define CSR_CPB_CSR_CPT_PRLS_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x728) +#define CSR_CPB_CSR_CPT_COL_TH_REG (CSR_CPB_CSR_3_BASE + 0x72C) +#define CSR_CPB_CSR_CPT_PRO_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x740) +#define CSR_CPB_CSR_CPT_PRO_DEALC_TX_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x744) +#define CSR_CPB_CSR_CPT_PRO_DEALC_RX_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x748) +#define CSR_CPB_CSR_CPT_PRO_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_3_BASE + 0x74C) +#define CSR_CPB_CSR_CPT_PRO_DEALC_RP_TH_REG (CSR_CPB_CSR_3_BASE + 0x750) +#define CSR_CPB_CSR_CPT_OUT_ERR_EN_REG (CSR_CPB_CSR_3_BASE + 0x754) /* CPB输出给PETX的err bit有效使能 */ +#define CSR_CPB_CSR_CPT_TXLB_EN_REG (CSR_CPB_CSR_3_BASE + 0x758) /* TXLB通道使能配置 */ +#define CSR_CPB_CSR_TX_CRR0_EN_REG (CSR_CPB_CSR_3_BASE + 0xC00) /* CPB_TX_NOR0的CRR使能配置 */ +#define CSR_CPB_CSR_TX_CRR0_PID_REG (CSR_CPB_CSR_3_BASE + 0xC04) /* CPB_TX_NOR0的CRR时隙的端口配置 */ +#define CSR_CPB_CSR_TX_CRR1_EN_REG (CSR_CPB_CSR_3_BASE + 0xC08) /* CPB_TX_NOR1的CRR使能配置 */ +#define CSR_CPB_CSR_TX_CRR1_PID_REG (CSR_CPB_CSR_3_BASE + 0xC0C) /* CPB_TX_NOR1的CRR时隙的端口配置 */ +#define CSR_CPB_CSR_TX_CRR2_EN_REG (CSR_CPB_CSR_3_BASE + 0xC10) /* TXLB的CRR使能配置 */ +#define CSR_CPB_CSR_TX_CRR2_PID_REG (CSR_CPB_CSR_3_BASE + 0xC14) /* TXLB的CRR时隙的端口配置 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG0_REG (CSR_CPB_CSR_3_BASE + 0xC20) /* TX方向Chn0 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG1_REG (CSR_CPB_CSR_3_BASE + 0xC24) /* TX方向Chn1 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG2_REG (CSR_CPB_CSR_3_BASE + 0xC28) /* TX方向Chn2 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG3_REG (CSR_CPB_CSR_3_BASE + 0xC2C) /* TX方向Chn3 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG4_REG (CSR_CPB_CSR_3_BASE + 0xC30) /* TX方向Chn4 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG5_REG (CSR_CPB_CSR_3_BASE + 0xC34) /* TX方向Chn5 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG6_REG (CSR_CPB_CSR_3_BASE + 0xC38) /* TX方向Chn6 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG7_REG (CSR_CPB_CSR_3_BASE + 0xC3C) /* TX方向Chn7 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG8_REG (CSR_CPB_CSR_3_BASE + 0xC40) /* TX方向Chn8 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG9_REG (CSR_CPB_CSR_3_BASE + 0xC44) /* TX方向Chn9 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG10_REG (CSR_CPB_CSR_3_BASE + 0xC48) /* TX方向Chn10 Credit配置寄存器 */ +#define CSR_CPB_CSR_CPB_TX_CRDT_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC50) /* CPB_TX相关信用配置 */ +#define CSR_CPB_CSR_TXLB_PD_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC60) /* TXLB的PD请求FIFO配置 */ +#define CSR_CPB_CSR_TX_COS_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC64) /* TX COS PD请求FIFO配置 */ +#define CSR_CPB_CSR_FTSO_RLS_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC68) /* Fast TSO Pptr Rls请求FIFO配置 */ +#define CSR_CPB_CSR_TX_IDX_WT_REG (CSR_CPB_CSR_3_BASE + 0xC70) /* CPB_TX内部3个PRO间IDX信用申请权重配置 */ +#define CSR_CPB_CSR_MAG_BP_EN_REG (CSR_CPB_CSR_3_BASE + 0xC74) /* MAG的反压使能配置 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC80) /* TX TSO3 RLS请求FIFO配置 */ +#define CSR_CPB_CSR_CIR_DAT_IN_FIFO_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1000) /* IPSURX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIR_DAT_IN_FIFO_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1004) /* IPSURX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIR_DAT_IN_FIFO_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1008) /* IPSURX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIR_RPT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1010) /* IPSURX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIR_RPT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1014) /* IPSURX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIR_RPT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1018) /* IPSURX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIR_IN_PKT_SOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1020) /* CPB从IPSURX接收到报文SOP数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PKT_EOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1024) /* CPB从IPSURX接收到报文SOP数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1030) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1034) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1038) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_3_REG (CSR_CPB_CSR_3_BASE + 0x103C) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_4_REG (CSR_CPB_CSR_3_BASE + 0x1040) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_5_REG (CSR_CPB_CSR_3_BASE + 0x1044) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_6_REG (CSR_CPB_CSR_3_BASE + 0x1048) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_7_REG (CSR_CPB_CSR_3_BASE + 0x104C) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_8_REG (CSR_CPB_CSR_3_BASE + 0x1050) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_9_REG (CSR_CPB_CSR_3_BASE + 0x1054) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_10_REG (CSR_CPB_CSR_3_BASE + 0x1058) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_DRP_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1060) /* CPB丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_DRP_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1064) /* CPB丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_DRP_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1068) /* CPB丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_DRP_PKT_CNT_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1070) /* CPB由于入口FIFO满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_DRP_PKT_CNT_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1074) /* CPB由于入口FIFO满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_DRP_PKT_CNT_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1078) /* CPB由于入口FIFO满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_BMU_AF_DRP_PKT_CNT_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1080) /* CPB由于BMU满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_BMU_AF_DRP_PKT_CNT_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1084) /* CPB由于BMU满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_BMU_AF_DRP_PKT_CNT_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1088) /* CPB由于BMU满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1090) /* IPSURX_CPB接口FIFO反压次数统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1094) /* IPSURX_CPB接口FIFO反压次数统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1098) /* IPSURX_CPB接口FIFO反压次数统计 */ +#define CSR_CPB_CSR_CIR_CUT_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x10A0) /* CPB丢包时截断报文数量的统计 */ +#define CSR_CPB_CSR_CIR_CUT_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x10A4) /* CPB丢包时截断报文数量的统计 */ +#define CSR_CPB_CSR_CIR_CUT_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x10A8) /* CPB丢包时截断报文数量的统计 */ +#define CSR_CPB_CSR_CIR_RPT_IQ_CNT_REG (CSR_CPB_CSR_3_BASE + 0x10B0) /* CPB向IQ通告PCI次数的统计每个报文仅统计一次 */ +#define CSR_CPB_CSR_CIR_IQ_BP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x10B4) /* IQ反压CPB接收侧报文通告的次数 */ +#define CSR_CPB_CSR_CIR_SPORT_ERR_REG (CSR_CPB_CSR_3_BASE + 0x10B8) /* IPSURX送给CPB的报文Sport超过有效范围 */ +#define CSR_CPB_CSR_CIR_ALC_PRM_CNUM_FULL_ERR_REG \ + (CSR_CPB_CSR_3_BASE + \ + 0x10BC) /* 由于受到PRM的反压，造成IPSURX_CPB内部申请PRM空间时根据COS汇聚，counter计满错误，counter最大值127 */ +#define CSR_CPB_CSR_CIR_FIFO_ERR_REG (CSR_CPB_CSR_3_BASE + 0x10C0) /* IPSURX_CPB模块FIFO溢出错误 */ +#define CSR_CPB_CSR_CIR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x10D0) /* CIR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CIR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x10D4) /* CIR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CIR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x10D8) /* CIR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_0_REG (CSR_CPB_CSR_3_BASE + 0x10E8) /* PRM反压丢弃历史记录0 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_1_REG (CSR_CPB_CSR_3_BASE + 0x10EC) /* PRM反压丢弃历史记录1 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_2_REG (CSR_CPB_CSR_3_BASE + 0x10F0) /* PRM反压丢弃历史记录2 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_3_REG (CSR_CPB_CSR_3_BASE + 0x10F4) /* PRM反压丢弃历史记录3 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_4_REG (CSR_CPB_CSR_3_BASE + 0x10F8) /* PRM反压丢弃历史记录4 */ +#define CSR_CPB_CSR_CPT_PRO_DAT_IN_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1300) /* CPB_TX送入的读取控制信息FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DAT_IN_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1304) /* CPB_TX送入的读取控制信息FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DAT_IN_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1308) /* CPB_TX送入的读取控制信息FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DEALC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1310) /* CPB_PETX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DEALC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1314) /* CPB_PETX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DEALC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1318) /* CPB_PETX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPT_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_3_BASE + 0x1320) /* CPB_PETX模块通告PRM cell释放FIFO的状态寄存器（经调度送出） */ +#define CSR_CPB_CSR_CPT_PRLS_FIFO_STA_REG \ + (CSR_CPB_CSR_3_BASE + 0x1324) /* CPB_PETX模块通告packet release FIFO的状态寄存器（经调度送出） */ +#define CSR_CPB_CSR_CPT_DAT_OUT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1330) /* CPB_PETX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPT_DAT_OUT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1334) /* CPB_PETX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPT_DAT_OUT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1338) /* CPB_PETX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPT_OUT_PKT_SOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1340) /* CPB输出给PETX报文SOP数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_PKT_EOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1344) /* CPB输出给PETX报文EOP数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1350) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1354) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1358) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_3_REG (CSR_CPB_CSR_3_BASE + 0x135C) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_4_REG (CSR_CPB_CSR_3_BASE + 0x1360) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_5_REG (CSR_CPB_CSR_3_BASE + 0x1364) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_6_REG (CSR_CPB_CSR_3_BASE + 0x1368) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_7_REG (CSR_CPB_CSR_3_BASE + 0x136C) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_8_REG (CSR_CPB_CSR_3_BASE + 0x1370) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_9_REG (CSR_CPB_CSR_3_BASE + 0x1374) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_10_REG (CSR_CPB_CSR_3_BASE + 0x1378) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_SOF_MSM_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1380) /* CPB输出报文给PETX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPT_SOF_MSM_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1384) /* CPB输出报文给PETX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPT_SOF_MSM_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1388) /* CPB输出报文给PETX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPT_EOF_MSM_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1390) /* CPB输出报文给PETX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPT_EOF_MSM_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1394) /* CPB输出报文给PETX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPT_EOF_MSM_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1398) /* CPB输出报文给PETX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPT_DEALC_TX_BP_TM_REG \ + (CSR_CPB_CSR_3_BASE + 0x13A0) /* CPB_PETX接口上PRM对DEALC_TX反压持续的最大时间 */ +#define CSR_CPB_CSR_CPT_DEALC_RX_BP_TM_REG \ + (CSR_CPB_CSR_3_BASE + 0x13A4) /* CPB_PETX接口上PRM对DEALC_RX反压持续的最大时间 */ +#define CSR_CPB_CSR_CPT_TS_CFG_ERR_REG (CSR_CPB_CSR_3_BASE + 0x13A8) /* CPB_PETX对应三个pro时隙配置错误 */ +#define CSR_CPB_CSR_CPT_FIFO_OV_ERR_REG (CSR_CPB_CSR_3_BASE + 0x13AC) /* CPB_PERX接口模块FIFO上溢错误 */ +#define CSR_CPB_CSR_CPT_FIFO_UF_ERR_REG (CSR_CPB_CSR_3_BASE + 0x13B0) /* CPB_PERX接口模块FIFO下溢错误 */ +#define CSR_CPB_CSR_CPT_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x13B4) /* CPT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPT_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x13B8) /* CPT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPT_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x13BC) /* CPT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A00) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A04) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A08) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1A0C) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1A10) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1A14) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1A18) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1A1C) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_8_REG (CSR_CPB_CSR_3_BASE + 0x1A20) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_9_REG (CSR_CPB_CSR_3_BASE + 0x1A24) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_10_REG (CSR_CPB_CSR_3_BASE + 0x1A28) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_IDX_CRDT_STA_REG (CSR_CPB_CSR_3_BASE + 0x1A30) /* TX方向IDX的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A40) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A44) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A48) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1A4C) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1A50) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1A54) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1A58) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1A5C) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_EMPTY_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A60) /* TX方向PD FIFO empty状态寄存器0 */ +#define CSR_CPB_CSR_TXPD_FIFO_EMPTY_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A64) /* TX方向PD FIFO empty状态寄存器1 */ +#define CSR_CPB_CSR_TXPD_FIFO_EMPTY_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A68) /* TX方向PD FIFO empty状态寄存器2 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A70) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A74) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A78) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1A7C) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1A80) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1A84) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1A88) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1A8C) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_8_REG (CSR_CPB_CSR_3_BASE + 0x1A90) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1AA0) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1AA4) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1AA8) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1AAC) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1AB0) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1AB4) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1AB8) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1ABC) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_8_REG (CSR_CPB_CSR_3_BASE + 0x1AC0) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_9_REG (CSR_CPB_CSR_3_BASE + 0x1AC4) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_10_REG (CSR_CPB_CSR_3_BASE + 0x1AC8) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_MAG_BP_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1AD0) /* MAG的反压状态指示0 */ +#define CSR_CPB_CSR_MAG_BP_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1AD4) /* MAG的反压状态指示1 */ +#define CSR_CPB_CSR_TX_FTSO_RLS_FIFO_STA_REG (CSR_CPB_CSR_3_BASE + 0x1AE8) /* TX FTSO Pptr Rls FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1AF0) /* TX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1AF4) /* TX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1AF8) /* TX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_CRDT_OF_ERR_REG (CSR_CPB_CSR_3_BASE + 0x1B00) /* TX方向Credit Overflow Err历史记录寄存器 */ +#define CSR_CPB_CSR_TX_CRDT_UF_ERR_REG (CSR_CPB_CSR_3_BASE + 0x1B04) /* TX方向Credit Underflow Err历史记录寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_OF_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x1B10) /* TX方向PD FIFO Overflow Err历史记录寄存器0 \ + */ +#define CSR_CPB_CSR_TXPD_FIFO_OF_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x1B14) /* TX方向PD FIFO Overflow Err历史记录寄存器1 \ + */ +#define CSR_CPB_CSR_TXPD_FIFO_OF_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x1B18) /* TX方向PD FIFO Overflow Err历史记录寄存器2 \ + */ +#define CSR_CPB_CSR_TXPD_FIFO_UF_ERR_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B20) /* TX方向PD FIFO Underflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_TXPD_FIFO_UF_ERR_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B24) /* TX方向PD FIFO Underflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_TXPD_FIFO_UF_ERR_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B28) /* TX方向PD FIFO Underflow Err历史记录寄存器2 */ +#define CSR_CPB_CSR_TX_FTSO_RLS_FIFO_ERR_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B30) /* TX FTSO Pptr Rls FIFO Underflow/Overflow Err历史记录寄存器 */ +#define CSR_CPB_CSR_TSO_RAM_ERR_REG (CSR_CPB_CSR_3_BASE + 0x1B34) /* TSO CTX Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x1B40) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x1B44) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x1B48) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_3_REG (CSR_CPB_CSR_3_BASE + 0x1B4C) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_4_REG (CSR_CPB_CSR_3_BASE + 0x1B50) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_5_REG (CSR_CPB_CSR_3_BASE + 0x1B54) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_6_REG (CSR_CPB_CSR_3_BASE + 0x1B58) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_7_REG (CSR_CPB_CSR_3_BASE + 0x1B5C) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPB_TX_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x1B80) /* CPB TX处理错误历史记录寄存器0 */ +#define CSR_CPB_CSR_CPB_TX_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x1B84) /* CPB TX处理错误历史记录寄存器1 */ +#define CSR_CPB_CSR_CPB_TX_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x1B88) /* CPB TX处理错误历史记录寄存器2 */ +#define CSR_CPB_CSR_CPB_TX_ERR_3_REG (CSR_CPB_CSR_3_BASE + 0x1B8C) /* CPB TX处理错误历史记录寄存器3 */ +#define CSR_CPB_CSR_CPB_TX_ERR_4_REG (CSR_CPB_CSR_3_BASE + 0x1B90) /* CPB TX处理错误历史记录寄存器4 */ +#define CSR_CPB_CSR_CPB_TX_ERR_5_REG (CSR_CPB_CSR_3_BASE + 0x1B94) /* CPB TX处理错误历史记录寄存器5 */ + +#endif // CPB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_c_union_define.h new file mode 100644 index 000000000..649f21cfa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_c_union_define.h @@ -0,0 +1,23677 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpi_c_union_define.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Author : xxx +// Version : V100 +// Date : +// Description : Hi 1823 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V5.1 History : xxx 2020/07/27 20:37:29 Create +// file +// ****************************************************************************** + +#ifndef CPI_C_UNION_DEFINE_H +#define CPI_C_UNION_DEFINE_H + +/* Define the union csr_msi_cap_csr_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_enable : 1; /* [0] */ + u32 msi_mutiple_message_enable : 3; /* [3:1] */ + u32 msi_x_function_mask : 1; /* [4] */ + u32 msi_x_enable : 1; /* [5] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_cap_csr_dw0_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msi_cap_csr_dw0_u msi_cap_csr_dw0[2]; /* 0 */ +} S_msi_cap_csr_REGS_TYPE; + +/* Declare the struct pointor of the module msi_cap_csr */ +extern volatile S_msi_cap_csr_REGS_TYPE *gopmsi_cap_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMSI_CAP_CSR_DW0_msi_enable(unsigned int umsi_enable); +int iSetMSI_CAP_CSR_DW0_msi_mutiple_message_enable(unsigned int umsi_mutiple_message_enable); +int iSetMSI_CAP_CSR_DW0_msi_x_function_mask(unsigned int umsi_x_function_mask); +int iSetMSI_CAP_CSR_DW0_msi_x_enable(unsigned int umsi_x_enable); + +/* Define the union csr_up_pcie_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_pcie_link : 5; /* [4:0] */ + u32 rsv_0 : 26; /* [30:5] */ + u32 ucpu_ini_sts : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_pcie_status_u; + +/* Define the union csr_up_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_int_sts : 1; /* [0] */ + u32 ucpu_rx_api_int_sts : 1; /* [1] */ + u32 ucpu_mb_int_sts : 1; /* [2] */ + u32 ucpu_mctprx_int_sts : 4; /* [6:3] */ + u32 ucpu_mctptx_int_sts : 4; /* [10:7] */ + u32 ucpu_tlprx_int_sts : 1; /* [11] */ + u32 ucpu_tlptx_int_sts : 1; /* [12] */ + u32 ucpu_clprx_int_sts : 4; /* [16:13] */ + u32 ucpu_crt_err : 1; /* [17] */ + u32 ucpu_uncrt_err : 1; /* [18] */ + u32 axi_bus_err : 1; /* [19] */ + u32 cpi_fatal_err : 1; /* [20] */ + u32 cpi_nonfatal_err : 1; /* [21] */ + u32 cpi_table_ecc_serr : 1; /* [22] */ + u32 host_mpu_notify_int_sts : 5; /* [27:23] */ + u32 rsv_1 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_status_u; + +/* Define the union csr_up_int_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_int_en : 1; /* [0] */ + u32 ucpu_rx_api_int_en : 1; /* [1] */ + u32 ucpu_mb_int_en : 1; /* [2] */ + u32 ucpu_mctprx_int_en : 4; /* [6:3] */ + u32 ucpu_mctptx_int_en : 4; /* [10:7] */ + u32 ucpu_tlprx_int_en : 1; /* [11] */ + u32 ucpu_tlptx_int_en : 1; /* [12] */ + u32 ucpu_clprx_int_en : 4; /* [16:13] */ + u32 ucpu_crt_int_en : 1; /* [17] */ + u32 ucpu_uncrt_int_en : 1; /* [18] */ + u32 axi_bus_err_int_en : 1; /* [19] */ + u32 cpi_fatal_err_en : 1; /* [20] */ + u32 cpi_nonfatal_err_en : 1; /* [21] */ + u32 cpi_table_ecc_serr_en : 1; /* [22] */ + u32 host_mpu_notify_int_en : 5; /* [27:23] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_ctl_u; + +/* Define the union csr_up_direct_access_lock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_dir_acc_lck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_direct_access_lock_u; + +/* Define the union csr_up_aeq_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_len : 21; /* [20:0] */ + u32 rsv_3 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_len_u; + +/* Define the union csr_up_aeq_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_ba : 26; /* [25:0] */ + u32 rsv_4 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_ba_u; + +/* Define the union csr_up_aeq_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_ci : 22; /* [21:0] */ + u32 rsv_5 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_ci_u; + +/* Define the union csr_up_aeq_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_pi : 22; /* [21:0] */ + u32 rsv_6 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_pi_u; + +/* Define the union csr_up_rx_api_buf_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_len : 21; /* [20:0] */ + u32 rsv_7 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_len_u; + +/* Define the union csr_up_rx_api_buf_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_ba : 26; /* [25:0] */ + u32 rsv_8 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_ba_u; + +/* Define the union csr_up_rx_api_buf_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_ci : 22; /* [21:0] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_ci_u; + +/* Define the union csr_up_rx_api_buf_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_pi : 22; /* [21:0] */ + u32 rsv_10 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_pi_u; + +/* Define the union csr_up_tx_api_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_tx_api_dest : 5; /* [4:0] */ + u32 ucpu_tx_api_code : 2; /* [6:5] */ + u32 op_type : 1; /* [7] */ + u32 ucpu_tx_api_len : 3; /* [10:8] */ + u32 rsv_11 : 1; /* [11] */ + u32 ucpu_api_rsp_len : 4; /* [15:12] */ + u32 src_tag_l : 12; /* [27:16] */ + u32 rsv_12 : 2; /* [29:28] */ + u32 status : 1; /* [30] */ + u32 ucpu_tx_api_issue : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tx_api_ctl_u; + +/* Define the union csr_up_tx_api_ctl_vio_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_tx_api_thread_id : 7; /* [6:0] */ + u32 up_tx_api_vio : 1; /* [7] */ + u32 up_tx_api_nvme : 1; /* [8] */ + u32 up_tx_rsvd_field : 6; /* [14:9] */ + u32 rsv_13 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tx_api_ctl_vio_u; + +/* Define the union csr_up_rb_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_aeq_timeout : 8; /* [7:0] */ + u32 rsv_14 : 8; /* [15:8] */ + u32 up_rb_timeout : 8; /* [23:16] */ + u32 up_mctp_timeout_off : 1; /* [24] */ + u32 up_mb_timeout_off : 1; /* [25] */ + u32 rsv_15 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_timeout_u; + +/* Define the union csr_up_xfer_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xcmd_otd : 4; /* [3:0] */ + u32 tlp_restart : 1; /* [4] */ + u32 apiram_init_start : 1; /* [5] */ + u32 apiram_init_done : 1; /* [6] */ + u32 rsv_16 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_xfer_ctrl_u; + +/* Define the union csr_up_tx_api_payload_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_tx_api_payload : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tx_api_payload_u; + +/* Define the union csr_up_int_coll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_int_coll : 3; /* [2:0] */ + u32 rsv_17 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_coll_u; + +/* Define the union csr_up_int_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 16; /* [15:0] */ + u32 ucpu_int_timeout : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_timeout_u; + +/* Define the union csr_up_tlp_rx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_len : 21; /* [20:0] */ + u32 rsv_19 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_len_u; + +/* Define the union csr_up_tlp_rx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_ba : 26; /* [25:0] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_ba_u; + +/* Define the union csr_up_tlp_rx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_ci : 22; /* [21:0] */ + u32 rsv_21 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_ci_u; + +/* Define the union csr_up_tlp_rx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_pi : 22; /* [21:0] */ + u32 rsv_22 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_pi_u; + +/* Define the union csr_up_tlp_tx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_len : 21; /* [20:0] */ + u32 rsv_23 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_len_u; + +/* Define the union csr_up_tlp_tx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_ba : 26; /* [25:0] */ + u32 rsv_24 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_ba_u; + +/* Define the union csr_up_tlp_tx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_ci : 22; /* [21:0] */ + u32 rsv_25 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_ci_u; + +/* Define the union csr_up_tlp_tx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_pi : 22; /* [21:0] */ + u32 rsv_26 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_pi_u; + +/* Define the union csr_up_mctprx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_len : 21; /* [20:0] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_len_u; + +/* Define the union csr_up_mctprx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_ba : 26; /* [25:0] */ + u32 rsv_28 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_ba_u; + +/* Define the union csr_up_mctprx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_ci : 22; /* [21:0] */ + u32 rsv_29 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_ci_u; + +/* Define the union csr_up_mctprx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_pi : 22; /* [21:0] */ + u32 rsv_30 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_pi_u; + +/* Define the union csr_up_mctptx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_len : 21; /* [20:0] */ + u32 rsv_31 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_len_u; + +/* Define the union csr_up_mctptx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_ba : 26; /* [25:0] */ + u32 rsv_32 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_ba_u; + +/* Define the union csr_up_mctptx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_ci : 22; /* [21:0] */ + u32 rsv_33 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_ci_u; + +/* Define the union csr_up_mctptx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_pi : 22; /* [21:0] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_pi_u; + +/* Define the union csr_up_csr_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_csr_node_addr : 27; /* [26:0] */ + u32 ucpu_acc_csr_status : 1; /* [27] */ + u32 ucpu_acc_csr_op_code : 2; /* [29:28] */ + u32 ucpu_acc_csr_size : 1; /* [30] */ + u32 ucpu_acc_csr_issue : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_csr_ctl_u; + +/* Define the union csr_up_csr_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_csr_wdat_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_csr_data0_u; + +/* Define the union csr_up_csr_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_csr_wdat_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_csr_data1_u; + +/* Define the union csr_up_api_rdat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_api_rdat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_api_rdat_u; + +/* Define the union csr_up_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 power_ctrl : 1; /* [0] */ + u32 spmem_tmod : 7; /* [7:1] */ + u32 tpmem_tmod : 8; /* [15:8] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_ctrl_u; + +/* Define the union csr_up_rb_dbgctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rb_dbg_sel : 5; /* [4:0] */ + u32 rsv_36 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_dbgctl_u; + +/* Define the union csr_up_rb_dbgdat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pi_ci_acc : 21; /* [20:0] */ + u32 rsv_37 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_dbgdat0_u; + +/* Define the union csr_up_rb_dbgdat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rb_cnt : 27; /* [26:0] */ + u32 rsv_38 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_dbgdat1_u; + +/* Define the union csr_up_fsm_dbg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxbuf_cur_st : 6; /* [5:0] */ + u32 aeq_cur_st : 6; /* [11:6] */ + u32 apirx_cur_st : 6; /* [17:12] */ + u32 apitx_cur_st : 3; /* [20:18] */ + u32 axi_bus_err : 2; /* [22:21] */ + u32 rsv_39 : 4; /* [26:23] */ + u32 tlp_xfer_err : 4; /* [30:27] */ + u32 rsv_40 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg0_u; + +/* Define the union csr_up_fsm_dbg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axixfer_cur_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg1_u; + +/* Define the union csr_up_fsm_dbg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbuf_cur_st : 20; /* [19:0] */ + u32 rsv_41 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg2_u; + +/* Define the union csr_up_fsm_dbg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clp_cur_st : 4; /* [3:0] */ + u32 vpd_cur_st : 4; /* [7:4] */ + u32 mctprx_cur_st : 7; /* [14:8] */ + u32 rsv_42 : 1; /* [15] */ + u32 rxtlp_cur_st : 6; /* [21:16] */ + u32 txtlp_cur_st : 9; /* [30:22] */ + u32 rsv_43 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg3_u; + +/* Define the union csr_up_mem_dbg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtlp_rama_errin : 2; /* [1:0] */ + u32 rxtlp_ramb_errin : 2; /* [3:2] */ + u32 upitf_rsp_ram_errin : 2; /* [5:4] */ + u32 prt0_rbdatfifo_ram_errin : 2; /* [7:6] */ + u32 prt1_rbdatfifo_ram_errin : 2; /* [9:8] */ + u32 prt2_rbdatfifo_ram_errin : 2; /* [11:10] */ + u32 prt3_rbdatfifo_ram_errin : 2; /* [13:12] */ + u32 prt0_txbuf_ram_errin : 2; /* [15:14] */ + u32 prt1_txbuf_ram_errin : 2; /* [17:16] */ + u32 prt2_txbuf_ram_errin : 2; /* [19:18] */ + u32 prt3_txbuf_ram_errin : 2; /* [21:20] */ + u32 axi_cnt_clr : 1; /* [22] */ + u32 rsv_44 : 1; /* [23] */ + u32 prt0_rxpctl_mb_ram_errin : 2; /* [25:24] */ + u32 prt1_rxpctl_mb_ram_errin : 2; /* [27:26] */ + u32 prt2_rxpctl_mb_ram_errin : 2; /* [29:28] */ + u32 prt3_rxpctl_mb_ram_errin : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg0_u; + +/* Define the union csr_up_mem_dbg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtlp_rama_erraddr : 6; /* [5:0] */ + u32 rsv_45 : 2; /* [7:6] */ + u32 rxtlp_rama_err : 2; /* [9:8] */ + u32 rxtlp_ramb_erraddr : 6; /* [15:10] */ + u32 rsv_46 : 2; /* [17:16] */ + u32 rxtlp_ramb_err : 2; /* [19:18] */ + u32 upitf_rsp_ram_erraddr : 4; /* [23:20] */ + u32 upitf_rsp_ram_err : 2; /* [25:24] */ + u32 rsv_47 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg1_u; + +/* Define the union csr_up_mem_dbg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_rbdatfifo_ram_erraddr : 5; /* [4:0] */ + u32 rsv_48 : 1; /* [5] */ + u32 prt0_rbdatfifo_ram_err : 2; /* [7:6] */ + u32 prt1_rbdatfifo_ram_erraddr : 5; /* [12:8] */ + u32 rsv_49 : 1; /* [13] */ + u32 prt1_rbdatfifo_ram_err : 2; /* [15:14] */ + u32 prt2_rbdatfifo_ram_erraddr : 5; /* [20:16] */ + u32 rsv_50 : 1; /* [21] */ + u32 prt2_rbdatfifo_ram_err : 2; /* [23:22] */ + u32 prt3_rbdatfifo_ram_erraddr : 5; /* [28:24] */ + u32 rsv_51 : 1; /* [29] */ + u32 prt3_rbdatfifo_ram_err : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg2_u; + +/* Define the union csr_up_mem_dbg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_txbuf_erraddr : 4; /* [3:0] */ + u32 prt0_txbuf_err : 2; /* [5:4] */ + u32 rsv_52 : 2; /* [7:6] */ + u32 prt1_txbuf_erraddr : 4; /* [11:8] */ + u32 prt1_txbuf_err : 2; /* [13:12] */ + u32 rsv_53 : 2; /* [15:14] */ + u32 prt2_txbuf_erraddr : 4; /* [19:16] */ + u32 prt2_txbuf_err : 2; /* [21:20] */ + u32 rsv_54 : 2; /* [23:22] */ + u32 prt3_txbuf_erraddr : 4; /* [27:24] */ + u32 prt3_txbuf_err : 2; /* [29:28] */ + u32 rsv_55 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg3_u; + +/* Define the union csr_up_dbg_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_fifo_st : 4; /* [3:0] */ + u32 prt1_fifo_st : 4; /* [7:4] */ + u32 prt2_fifo_st : 4; /* [11:8] */ + u32 prt3_fifo_st : 4; /* [15:12] */ + u32 wrcmd_otd : 4; /* [19:16] */ + u32 cnt_wr_acc : 4; /* [23:20] */ + u32 rdcmd_otd : 4; /* [27:24] */ + u32 cnt_rd_acc : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st0_u; + +/* Define the union csr_up_dbg_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_lat_avg : 8; /* [7:0] */ + u32 wr_lat_max : 8; /* [15:8] */ + u32 rd_lat_avg : 8; /* [23:16] */ + u32 rd_lat_max : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st1_u; + +/* Define the union csr_up_dbg_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_rxpctl_fifo_cnt : 6; /* [5:0] */ + u32 prt1_rxpctl_fifo_cnt : 6; /* [11:6] */ + u32 prt2_rxpctl_fifo_cnt : 6; /* [17:12] */ + u32 prt3_rxpctl_fifo_cnt : 6; /* [23:18] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st2_u; + +/* Define the union csr_up_dbg_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbuf_fifo_cnt : 20; /* [19:0] */ + u32 rxbuf_fifo_cnt : 7; /* [26:20] */ + u32 rsv_57 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st3_u; + +/* Define the union csr_up_mem_dbg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_rxpctl_mb_ram_erraddr : 4; /* [3:0] */ + u32 prt0_rxpctl_mb_ram_err : 2; /* [5:4] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 prt1_rxpctl_mb_ram_erraddr : 4; /* [11:8] */ + u32 prt1_rxpctl_mb_ram_err : 2; /* [13:12] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 prt2_rxpctl_mb_ram_erraddr : 4; /* [19:16] */ + u32 prt2_rxpctl_mb_ram_err : 2; /* [21:20] */ + u32 rsv_60 : 2; /* [23:22] */ + u32 prt3_rxpctl_mb_ram_erraddr : 4; /* [27:24] */ + u32 prt3_rxpctl_mb_ram_err : 2; /* [29:28] */ + u32 rsv_61 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg4_u; + +/* Define the union csr_up_dbg_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_mctprx_dropcnt : 8; /* [7:0] */ + u32 prt1_mctprx_dropcnt : 8; /* [15:8] */ + u32 prt2_mctprx_dropcnt : 8; /* [23:16] */ + u32 prt3_mctprx_dropcnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_cnt0_u; + +/* Define the union csr_up_dbg_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 upitf_all_apb_cnt : 16; /* [15:0] */ + u32 upitf_csr_apb_cnt : 8; /* [23:16] */ + u32 upitf_cpi_apb_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_cnt1_u; + +/* Define the union csr_up_rx_mb_buf_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_len : 21; /* [20:0] */ + u32 rsv_62 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_len_u; + +/* Define the union csr_up_rx_mb_buf_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_ba : 26; /* [25:0] */ + u32 rsv_63 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_ba_u; + +/* Define the union csr_up_rx_mb_buf_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_ci : 22; /* [21:0] */ + u32 rsv_64 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_ci_u; + +/* Define the union csr_up_rx_mb_buf_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_pi : 22; /* [21:0] */ + u32 rsv_65 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_pi_u; + +/* Define the union csr_up_bar_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bar_val : 3; /* [2:0] */ + u32 rsv_66 : 1; /* [3] */ + u32 msi_bar_val : 3; /* [6:4] */ + u32 rsv_67 : 1; /* [7] */ + u32 dbl_bar_val : 3; /* [10:8] */ + u32 rsv_68 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_bar_map_u; + +/* Define the union csr_up_acc_func_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_func_idx : 12; /* [11:0] */ + u32 rsv_69 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_acc_func_idx_u; + +/* Define the union csr_up_int_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_pcie_int_sts : 5; /* [4:0] */ + u32 ucpu_aeq_drop_int_sts : 1; /* [5] */ + u32 octl_ecc_err_int_sts : 1; /* [6] */ + u32 octl_ecc_merr_int_sts : 1; /* [7] */ + u32 octl_nonfatal_err_int_sts : 1; /* [8] */ + u32 octl_fatal_err_int_sts : 1; /* [9] */ + u32 dma_ecc_err_int_sts : 1; /* [10] */ + u32 dma_ecc_merr_int_sts : 1; /* [11] */ + u32 dma_nonfatal_err_int_sts : 1; /* [12] */ + u32 dma_fatal_err_int_sts : 1; /* [13] */ + u32 rsv_70 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_status2_u; + +/* Define the union csr_up_int_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_pcie_int_en : 5; /* [4:0] */ + u32 ucpu_aeq_drop_int_en : 1; /* [5] */ + u32 octl_ecc_err_int_en : 1; /* [6] */ + u32 octl_ecc_merr_int_en : 1; /* [7] */ + u32 octl_nonfatal_err_int_en : 1; /* [8] */ + u32 octl_fatal_err_int_en : 1; /* [9] */ + u32 dma_ecc_err_int_en : 1; /* [10] */ + u32 dma_ecc_merr_int_en : 1; /* [11] */ + u32 dma_nonfatal_err_int_en : 1; /* [12] */ + u32 dma_fatal_err_int_en : 1; /* [13] */ + u32 rsv_71 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_ctl2_u; + +/* Define the union csr_up_vioaeq_otd_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_otd_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_otd_th_u; + +/* Define the union csr_up_vioaeq_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_otd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_otd_cnt_u; + +/* Define the union csr_up_vioaeq_otd_rec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_otd_rec : 8; /* [7:0] */ + u32 rsv_72 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_otd_rec_u; + +/* Define the union csr_up_vioaeq_drop_rcd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop0_func : 12; /* [11:0] */ + u32 rsv_73 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop0_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd0_u; + +/* Define the union csr_up_vioaeq_drop_rcd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop1_func : 12; /* [11:0] */ + u32 rsv_74 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop1_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd1_u; + +/* Define the union csr_up_vioaeq_drop_rcd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop2_func : 12; /* [11:0] */ + u32 rsv_75 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop2_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd2_u; + +/* Define the union csr_up_vioaeq_drop_rcd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop3_func : 12; /* [11:0] */ + u32 rsv_76 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop3_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd3_u; + +/* Define the union csr_up_uncrt_err_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_uncrt_err_dis : 1; /* [0] */ + u32 rsv_77 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_uncrt_err_dis_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_up_pcie_status_u up_pcie_status; /* 0 */ + volatile csr_up_int_status_u up_int_status; /* 4 */ + volatile csr_up_int_ctl_u up_int_ctl; /* 8 */ + volatile csr_up_direct_access_lock_u up_direct_access_lock; /* C */ + volatile csr_up_aeq_len_u up_aeq_len; /* 10 */ + volatile csr_up_aeq_ba_u up_aeq_ba; /* 14 */ + volatile csr_up_aeq_ci_u up_aeq_ci; /* 18 */ + volatile csr_up_aeq_pi_u up_aeq_pi; /* 1C */ + volatile csr_up_rx_api_buf_len_u up_rx_api_buf_len; /* 20 */ + volatile csr_up_rx_api_buf_ba_u up_rx_api_buf_ba; /* 24 */ + volatile csr_up_rx_api_buf_ci_u up_rx_api_buf_ci; /* 28 */ + volatile csr_up_rx_api_buf_pi_u up_rx_api_buf_pi; /* 2C */ + volatile csr_up_tx_api_ctl_u up_tx_api_ctl; /* 30 */ + volatile csr_up_tx_api_ctl_vio_u up_tx_api_ctl_vio; /* 34 */ + volatile csr_up_rb_timeout_u up_rb_timeout; /* 38 */ + volatile csr_up_xfer_ctrl_u up_xfer_ctrl; /* 3C */ + volatile csr_up_tx_api_payload_u up_tx_api_payload[32]; /* 40 */ + volatile csr_up_int_coll_u up_int_coll; /* C8 */ + volatile csr_up_int_timeout_u up_int_timeout; /* CC */ + volatile csr_up_tlp_rx_len_u up_tlp_rx_len[4]; /* D0 */ + volatile csr_up_tlp_rx_ba_u up_tlp_rx_ba[4]; /* D4 */ + volatile csr_up_tlp_rx_ci_u up_tlp_rx_ci[4]; /* D8 */ + volatile csr_up_tlp_rx_pi_u up_tlp_rx_pi[4]; /* DC */ + volatile csr_up_tlp_tx_len_u up_tlp_tx_len[4]; /* E0 */ + volatile csr_up_tlp_tx_ba_u up_tlp_tx_ba[4]; /* E4 */ + volatile csr_up_tlp_tx_ci_u up_tlp_tx_ci[4]; /* E8 */ + volatile csr_up_tlp_tx_pi_u up_tlp_tx_pi[4]; /* EC */ + volatile csr_up_mctprx_len_u up_mctprx_len[4]; /* 150 */ + volatile csr_up_mctprx_ba_u up_mctprx_ba[4]; /* 154 */ + volatile csr_up_mctprx_ci_u up_mctprx_ci[4]; /* 158 */ + volatile csr_up_mctprx_pi_u up_mctprx_pi[4]; /* 15C */ + volatile csr_up_mctptx_len_u up_mctptx_len[4]; /* 160 */ + volatile csr_up_mctptx_ba_u up_mctptx_ba[4]; /* 164 */ + volatile csr_up_mctptx_ci_u up_mctptx_ci[4]; /* 168 */ + volatile csr_up_mctptx_pi_u up_mctptx_pi[4]; /* 16C */ + volatile csr_up_csr_ctl_u up_csr_ctl; /* 200 */ + volatile csr_up_csr_data0_u up_csr_data0; /* 204 */ + volatile csr_up_csr_data1_u up_csr_data1; /* 208 */ + volatile csr_up_api_rdat_u up_api_rdat[64]; /* 300 */ + volatile csr_up_mem_ctrl_u up_mem_ctrl; /* 400 */ + volatile csr_up_rb_dbgctl_u up_rb_dbgctl; /* 404 */ + volatile csr_up_rb_dbgdat0_u up_rb_dbgdat0; /* 408 */ + volatile csr_up_rb_dbgdat1_u up_rb_dbgdat1; /* 40C */ + volatile csr_up_fsm_dbg0_u up_fsm_dbg0; /* 410 */ + volatile csr_up_fsm_dbg1_u up_fsm_dbg1; /* 414 */ + volatile csr_up_fsm_dbg2_u up_fsm_dbg2; /* 418 */ + volatile csr_up_fsm_dbg3_u up_fsm_dbg3[4]; /* 420 */ + volatile csr_up_mem_dbg0_u up_mem_dbg0; /* 430 */ + volatile csr_up_mem_dbg1_u up_mem_dbg1; /* 434 */ + volatile csr_up_mem_dbg2_u up_mem_dbg2; /* 438 */ + volatile csr_up_mem_dbg3_u up_mem_dbg3; /* 43C */ + volatile csr_up_dbg_st0_u up_dbg_st0; /* 440 */ + volatile csr_up_dbg_st1_u up_dbg_st1; /* 444 */ + volatile csr_up_dbg_st2_u up_dbg_st2; /* 448 */ + volatile csr_up_dbg_st3_u up_dbg_st3; /* 44C */ + volatile csr_up_mem_dbg4_u up_mem_dbg4; /* 450 */ + volatile csr_up_dbg_cnt0_u up_dbg_cnt0; /* 460 */ + volatile csr_up_dbg_cnt1_u up_dbg_cnt1; /* 464 */ + volatile csr_up_rx_mb_buf_len_u up_rx_mb_buf_len; /* 470 */ + volatile csr_up_rx_mb_buf_ba_u up_rx_mb_buf_ba; /* 474 */ + volatile csr_up_rx_mb_buf_ci_u up_rx_mb_buf_ci; /* 478 */ + volatile csr_up_rx_mb_buf_pi_u up_rx_mb_buf_pi; /* 47C */ + volatile csr_up_bar_map_u up_bar_map; /* 480 */ + volatile csr_up_acc_func_idx_u up_acc_func_idx; /* 484 */ + volatile csr_up_int_status2_u up_int_status2; /* 490 */ + volatile csr_up_int_ctl2_u up_int_ctl2; /* 494 */ + volatile csr_up_vioaeq_otd_th_u up_vioaeq_otd_th; /* 4A0 */ + volatile csr_up_vioaeq_otd_cnt_u up_vioaeq_otd_cnt; /* 4A4 */ + volatile csr_up_vioaeq_otd_rec_u up_vioaeq_otd_rec; /* 4A8 */ + volatile csr_up_vioaeq_drop_rcd0_u up_vioaeq_drop_rcd0; /* 4B0 */ + volatile csr_up_vioaeq_drop_rcd1_u up_vioaeq_drop_rcd1; /* 4B4 */ + volatile csr_up_vioaeq_drop_rcd2_u up_vioaeq_drop_rcd2; /* 4B8 */ + volatile csr_up_vioaeq_drop_rcd3_u up_vioaeq_drop_rcd3; /* 4BC */ + volatile csr_up_uncrt_err_dis_u up_uncrt_err_dis; /* 4C0 */ +} S_up_itf_csr_REGS_TYPE; + +/* Declare the struct pointor of the module up_itf_csr */ +extern volatile S_up_itf_csr_REGS_TYPE *gopup_itf_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetUP_PCIE_STATUS_ucpu_pcie_link(unsigned int uucpu_pcie_link); +int iSetUP_PCIE_STATUS_ucpu_ini_sts(unsigned int uucpu_ini_sts); +int iSetUP_INT_STATUS_ucpu_aeq_int_sts(unsigned int uucpu_aeq_int_sts); +int iSetUP_INT_STATUS_ucpu_rx_api_int_sts(unsigned int uucpu_rx_api_int_sts); +int iSetUP_INT_STATUS_ucpu_mb_int_sts(unsigned int uucpu_mb_int_sts); +int iSetUP_INT_STATUS_ucpu_mctprx_int_sts(unsigned int uucpu_mctprx_int_sts); +int iSetUP_INT_STATUS_ucpu_mctptx_int_sts(unsigned int uucpu_mctptx_int_sts); +int iSetUP_INT_STATUS_ucpu_tlprx_int_sts(unsigned int uucpu_tlprx_int_sts); +int iSetUP_INT_STATUS_ucpu_tlptx_int_sts(unsigned int uucpu_tlptx_int_sts); +int iSetUP_INT_STATUS_ucpu_clprx_int_sts(unsigned int uucpu_clprx_int_sts); +int iSetUP_INT_STATUS_ucpu_crt_err(unsigned int uucpu_crt_err); +int iSetUP_INT_STATUS_ucpu_uncrt_err(unsigned int uucpu_uncrt_err); +int iSetUP_INT_STATUS_axi_bus_err(unsigned int uaxi_bus_err); +int iSetUP_INT_STATUS_cpi_fatal_err(unsigned int ucpi_fatal_err); +int iSetUP_INT_STATUS_cpi_nonfatal_err(unsigned int ucpi_nonfatal_err); +int iSetUP_INT_STATUS_cpi_table_ecc_serr(unsigned int ucpi_table_ecc_serr); +int iSetUP_INT_STATUS_host_mpu_notify_int_sts(unsigned int uhost_mpu_notify_int_sts); +int iSetUP_INT_CTL_ucpu_aeq_int_en(unsigned int uucpu_aeq_int_en); +int iSetUP_INT_CTL_ucpu_rx_api_int_en(unsigned int uucpu_rx_api_int_en); +int iSetUP_INT_CTL_ucpu_mb_int_en(unsigned int uucpu_mb_int_en); +int iSetUP_INT_CTL_ucpu_mctprx_int_en(unsigned int uucpu_mctprx_int_en); +int iSetUP_INT_CTL_ucpu_mctptx_int_en(unsigned int uucpu_mctptx_int_en); +int iSetUP_INT_CTL_ucpu_tlprx_int_en(unsigned int uucpu_tlprx_int_en); +int iSetUP_INT_CTL_ucpu_tlptx_int_en(unsigned int uucpu_tlptx_int_en); +int iSetUP_INT_CTL_ucpu_clprx_int_en(unsigned int uucpu_clprx_int_en); +int iSetUP_INT_CTL_ucpu_crt_int_en(unsigned int uucpu_crt_int_en); +int iSetUP_INT_CTL_ucpu_uncrt_int_en(unsigned int uucpu_uncrt_int_en); +int iSetUP_INT_CTL_axi_bus_err_int_en(unsigned int uaxi_bus_err_int_en); +int iSetUP_INT_CTL_cpi_fatal_err_en(unsigned int ucpi_fatal_err_en); +int iSetUP_INT_CTL_cpi_nonfatal_err_en(unsigned int ucpi_nonfatal_err_en); +int iSetUP_INT_CTL_cpi_table_ecc_serr_en(unsigned int ucpi_table_ecc_serr_en); +int iSetUP_INT_CTL_host_mpu_notify_int_en(unsigned int uhost_mpu_notify_int_en); +int iSetUP_DIRECT_ACCESS_LOCK_ucpu_dir_acc_lck(unsigned int uucpu_dir_acc_lck); +int iSetUP_AEQ_LEN_ucpu_aeq_len(unsigned int uucpu_aeq_len); +int iSetUP_AEQ_BA_ucpu_aeq_ba(unsigned int uucpu_aeq_ba); +int iSetUP_AEQ_CI_ucpu_aeq_ci(unsigned int uucpu_aeq_ci); +int iSetUP_AEQ_PI_ucpu_aeq_pi(unsigned int uucpu_aeq_pi); +int iSetUP_RX_API_BUF_LEN_ucpu_rx_api_buf_len(unsigned int uucpu_rx_api_buf_len); +int iSetUP_RX_API_BUF_BA_ucpu_rx_api_buf_ba(unsigned int uucpu_rx_api_buf_ba); +int iSetUP_RX_API_BUF_CI_ucpu_rx_api_buf_ci(unsigned int uucpu_rx_api_buf_ci); +int iSetUP_RX_API_BUF_PI_ucpu_rx_api_buf_pi(unsigned int uucpu_rx_api_buf_pi); +int iSetUP_TX_API_CTL_ucpu_tx_api_dest(unsigned int uucpu_tx_api_dest); +int iSetUP_TX_API_CTL_ucpu_tx_api_code(unsigned int uucpu_tx_api_code); +int iSetUP_TX_API_CTL_op_type(unsigned int uop_type); +int iSetUP_TX_API_CTL_ucpu_tx_api_len(unsigned int uucpu_tx_api_len); +int iSetUP_TX_API_CTL_ucpu_api_rsp_len(unsigned int uucpu_api_rsp_len); +int iSetUP_TX_API_CTL_src_tag_l(unsigned int usrc_tag_l); +int iSetUP_TX_API_CTL_status(unsigned int ustatus); +int iSetUP_TX_API_CTL_ucpu_tx_api_issue(unsigned int uucpu_tx_api_issue); +int iSetUP_TX_API_CTL_VIO_up_tx_api_thread_id(unsigned int uup_tx_api_thread_id); +int iSetUP_TX_API_CTL_VIO_up_tx_api_vio(unsigned int uup_tx_api_vio); +int iSetUP_TX_API_CTL_VIO_up_tx_api_nvme(unsigned int uup_tx_api_nvme); +int iSetUP_TX_API_CTL_VIO_up_tx_rsvd_field(unsigned int uup_tx_rsvd_field); +int iSetUP_RB_TIMEOUT_up_aeq_timeout(unsigned int uup_aeq_timeout); +int iSetUP_RB_TIMEOUT_up_rb_timeout(unsigned int uup_rb_timeout); +int iSetUP_RB_TIMEOUT_up_mctp_timeout_off(unsigned int uup_mctp_timeout_off); +int iSetUP_RB_TIMEOUT_up_mb_timeout_off(unsigned int uup_mb_timeout_off); +int iSetUP_XFER_CTRL_xcmd_otd(unsigned int uxcmd_otd); +int iSetUP_XFER_CTRL_tlp_restart(unsigned int utlp_restart); +int iSetUP_XFER_CTRL_apiram_init_start(unsigned int uapiram_init_start); +int iSetUP_XFER_CTRL_apiram_init_done(unsigned int uapiram_init_done); +int iSetUP_TX_API_PAYLOAD_ucpu_tx_api_payload(unsigned int uucpu_tx_api_payload); +int iSetUP_INT_COLL_ucpu_int_coll(unsigned int uucpu_int_coll); +int iSetUP_INT_TIMEOUT_ucpu_int_timeout(unsigned int uucpu_int_timeout); +int iSetUP_TLP_RX_LEN_ucpu_port_tlprx_len(unsigned int uucpu_port_tlprx_len); +int iSetUP_TLP_RX_BA_ucpu_port_tlprx_ba(unsigned int uucpu_port_tlprx_ba); +int iSetUP_TLP_RX_CI_ucpu_port_tlprx_ci(unsigned int uucpu_port_tlprx_ci); +int iSetUP_TLP_RX_PI_ucpu_port_tlprx_pi(unsigned int uucpu_port_tlprx_pi); +int iSetUP_TLP_TX_LEN_ucpu_port_tlptx_len(unsigned int uucpu_port_tlptx_len); +int iSetUP_TLP_TX_BA_ucpu_port_tlptx_ba(unsigned int uucpu_port_tlptx_ba); +int iSetUP_TLP_TX_CI_ucpu_port_tlptx_ci(unsigned int uucpu_port_tlptx_ci); +int iSetUP_TLP_TX_PI_ucpu_port_tlptx_pi(unsigned int uucpu_port_tlptx_pi); +int iSetUP_MCTPRX_LEN_ucpu_port_mctprx_len(unsigned int uucpu_port_mctprx_len); +int iSetUP_MCTPRX_BA_ucpu_port_mctprx_ba(unsigned int uucpu_port_mctprx_ba); +int iSetUP_MCTPRX_CI_ucpu_port_mctprx_ci(unsigned int uucpu_port_mctprx_ci); +int iSetUP_MCTPRX_PI_ucpu_port_mctprx_pi(unsigned int uucpu_port_mctprx_pi); +int iSetUP_MCTPTX_LEN_ucpu_port_mctptx_len(unsigned int uucpu_port_mctptx_len); +int iSetUP_MCTPTX_BA_ucpu_port_mctptx_ba(unsigned int uucpu_port_mctptx_ba); +int iSetUP_MCTPTX_CI_ucpu_port_mctptx_ci(unsigned int uucpu_port_mctptx_ci); +int iSetUP_MCTPTX_PI_ucpu_port_mctptx_pi(unsigned int uucpu_port_mctptx_pi); +int iSetUP_CSR_CTL_ucpu_acc_csr_node_addr(unsigned int uucpu_acc_csr_node_addr); +int iSetUP_CSR_CTL_ucpu_acc_csr_status(unsigned int uucpu_acc_csr_status); +int iSetUP_CSR_CTL_ucpu_acc_csr_op_code(unsigned int uucpu_acc_csr_op_code); +int iSetUP_CSR_CTL_ucpu_acc_csr_size(unsigned int uucpu_acc_csr_size); +int iSetUP_CSR_CTL_ucpu_acc_csr_issue(unsigned int uucpu_acc_csr_issue); +int iSetUP_CSR_DATA0_ucpu_acc_csr_wdat_h(unsigned int uucpu_acc_csr_wdat_h); +int iSetUP_CSR_DATA1_ucpu_acc_csr_wdat_l(unsigned int uucpu_acc_csr_wdat_l); +int iSetUP_API_RDAT_ucpu_api_rdat(unsigned int uucpu_api_rdat); +int iSetUP_MEM_CTRL_power_ctrl(unsigned int upower_ctrl); +int iSetUP_MEM_CTRL_spmem_tmod(unsigned int uspmem_tmod); +int iSetUP_MEM_CTRL_tpmem_tmod(unsigned int utpmem_tmod); +int iSetUP_RB_DBGCTL_rb_dbg_sel(unsigned int urb_dbg_sel); +int iSetUP_RB_DBGDAT0_pi_ci_acc(unsigned int upi_ci_acc); +int iSetUP_RB_DBGDAT1_rb_cnt(unsigned int urb_cnt); +int iSetUP_FSM_DBG0_rxbuf_cur_st(unsigned int urxbuf_cur_st); +int iSetUP_FSM_DBG0_aeq_cur_st(unsigned int uaeq_cur_st); +int iSetUP_FSM_DBG0_apirx_cur_st(unsigned int uapirx_cur_st); +int iSetUP_FSM_DBG0_apitx_cur_st(unsigned int uapitx_cur_st); +int iSetUP_FSM_DBG0_axi_bus_err(unsigned int uaxi_bus_err); +int iSetUP_FSM_DBG0_tlp_xfer_err(unsigned int utlp_xfer_err); +int iSetUP_FSM_DBG1_axixfer_cur_st(unsigned int uaxixfer_cur_st); +int iSetUP_FSM_DBG2_txbuf_cur_st(unsigned int utxbuf_cur_st); +int iSetUP_FSM_DBG3_clp_cur_st(unsigned int uclp_cur_st); +int iSetUP_FSM_DBG3_vpd_cur_st(unsigned int uvpd_cur_st); +int iSetUP_FSM_DBG3_mctprx_cur_st(unsigned int umctprx_cur_st); +int iSetUP_FSM_DBG3_rxtlp_cur_st(unsigned int urxtlp_cur_st); +int iSetUP_FSM_DBG3_txtlp_cur_st(unsigned int utxtlp_cur_st); +int iSetUP_MEM_DBG0_rxtlp_rama_errin(unsigned int urxtlp_rama_errin); +int iSetUP_MEM_DBG0_rxtlp_ramb_errin(unsigned int urxtlp_ramb_errin); +int iSetUP_MEM_DBG0_upitf_rsp_ram_errin(unsigned int uupitf_rsp_ram_errin); +int iSetUP_MEM_DBG0_prt0_rbdatfifo_ram_errin(unsigned int uprt0_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt1_rbdatfifo_ram_errin(unsigned int uprt1_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt2_rbdatfifo_ram_errin(unsigned int uprt2_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt3_rbdatfifo_ram_errin(unsigned int uprt3_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt0_txbuf_ram_errin(unsigned int uprt0_txbuf_ram_errin); +int iSetUP_MEM_DBG0_prt1_txbuf_ram_errin(unsigned int uprt1_txbuf_ram_errin); +int iSetUP_MEM_DBG0_prt2_txbuf_ram_errin(unsigned int uprt2_txbuf_ram_errin); +int iSetUP_MEM_DBG0_prt3_txbuf_ram_errin(unsigned int uprt3_txbuf_ram_errin); +int iSetUP_MEM_DBG0_axi_cnt_clr(unsigned int uaxi_cnt_clr); +int iSetUP_MEM_DBG0_prt0_rxpctl_mb_ram_errin(unsigned int uprt0_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG0_prt1_rxpctl_mb_ram_errin(unsigned int uprt1_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG0_prt2_rxpctl_mb_ram_errin(unsigned int uprt2_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG0_prt3_rxpctl_mb_ram_errin(unsigned int uprt3_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG1_rxtlp_rama_erraddr(unsigned int urxtlp_rama_erraddr); +int iSetUP_MEM_DBG1_rxtlp_rama_err(unsigned int urxtlp_rama_err); +int iSetUP_MEM_DBG1_rxtlp_ramb_erraddr(unsigned int urxtlp_ramb_erraddr); +int iSetUP_MEM_DBG1_rxtlp_ramb_err(unsigned int urxtlp_ramb_err); +int iSetUP_MEM_DBG1_upitf_rsp_ram_erraddr(unsigned int uupitf_rsp_ram_erraddr); +int iSetUP_MEM_DBG1_upitf_rsp_ram_err(unsigned int uupitf_rsp_ram_err); +int iSetUP_MEM_DBG2_prt0_rbdatfifo_ram_erraddr(unsigned int uprt0_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt0_rbdatfifo_ram_err(unsigned int uprt0_rbdatfifo_ram_err); +int iSetUP_MEM_DBG2_prt1_rbdatfifo_ram_erraddr(unsigned int uprt1_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt1_rbdatfifo_ram_err(unsigned int uprt1_rbdatfifo_ram_err); +int iSetUP_MEM_DBG2_prt2_rbdatfifo_ram_erraddr(unsigned int uprt2_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt2_rbdatfifo_ram_err(unsigned int uprt2_rbdatfifo_ram_err); +int iSetUP_MEM_DBG2_prt3_rbdatfifo_ram_erraddr(unsigned int uprt3_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt3_rbdatfifo_ram_err(unsigned int uprt3_rbdatfifo_ram_err); +int iSetUP_MEM_DBG3_prt0_txbuf_erraddr(unsigned int uprt0_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt0_txbuf_err(unsigned int uprt0_txbuf_err); +int iSetUP_MEM_DBG3_prt1_txbuf_erraddr(unsigned int uprt1_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt1_txbuf_err(unsigned int uprt1_txbuf_err); +int iSetUP_MEM_DBG3_prt2_txbuf_erraddr(unsigned int uprt2_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt2_txbuf_err(unsigned int uprt2_txbuf_err); +int iSetUP_MEM_DBG3_prt3_txbuf_erraddr(unsigned int uprt3_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt3_txbuf_err(unsigned int uprt3_txbuf_err); +int iSetUP_DBG_ST0_prt0_fifo_st(unsigned int uprt0_fifo_st); +int iSetUP_DBG_ST0_prt1_fifo_st(unsigned int uprt1_fifo_st); +int iSetUP_DBG_ST0_prt2_fifo_st(unsigned int uprt2_fifo_st); +int iSetUP_DBG_ST0_prt3_fifo_st(unsigned int uprt3_fifo_st); +int iSetUP_DBG_ST0_wrcmd_otd(unsigned int uwrcmd_otd); +int iSetUP_DBG_ST0_cnt_wr_acc(unsigned int ucnt_wr_acc); +int iSetUP_DBG_ST0_rdcmd_otd(unsigned int urdcmd_otd); +int iSetUP_DBG_ST0_cnt_rd_acc(unsigned int ucnt_rd_acc); +int iSetUP_DBG_ST1_wr_lat_avg(unsigned int uwr_lat_avg); +int iSetUP_DBG_ST1_wr_lat_max(unsigned int uwr_lat_max); +int iSetUP_DBG_ST1_rd_lat_avg(unsigned int urd_lat_avg); +int iSetUP_DBG_ST1_rd_lat_max(unsigned int urd_lat_max); +int iSetUP_DBG_ST2_prt0_rxpctl_fifo_cnt(unsigned int uprt0_rxpctl_fifo_cnt); +int iSetUP_DBG_ST2_prt1_rxpctl_fifo_cnt(unsigned int uprt1_rxpctl_fifo_cnt); +int iSetUP_DBG_ST2_prt2_rxpctl_fifo_cnt(unsigned int uprt2_rxpctl_fifo_cnt); +int iSetUP_DBG_ST2_prt3_rxpctl_fifo_cnt(unsigned int uprt3_rxpctl_fifo_cnt); +int iSetUP_DBG_ST3_txbuf_fifo_cnt(unsigned int utxbuf_fifo_cnt); +int iSetUP_DBG_ST3_rxbuf_fifo_cnt(unsigned int urxbuf_fifo_cnt); +int iSetUP_MEM_DBG4_prt0_rxpctl_mb_ram_erraddr(unsigned int uprt0_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt0_rxpctl_mb_ram_err(unsigned int uprt0_rxpctl_mb_ram_err); +int iSetUP_MEM_DBG4_prt1_rxpctl_mb_ram_erraddr(unsigned int uprt1_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt1_rxpctl_mb_ram_err(unsigned int uprt1_rxpctl_mb_ram_err); +int iSetUP_MEM_DBG4_prt2_rxpctl_mb_ram_erraddr(unsigned int uprt2_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt2_rxpctl_mb_ram_err(unsigned int uprt2_rxpctl_mb_ram_err); +int iSetUP_MEM_DBG4_prt3_rxpctl_mb_ram_erraddr(unsigned int uprt3_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt3_rxpctl_mb_ram_err(unsigned int uprt3_rxpctl_mb_ram_err); +int iSetUP_DBG_CNT0_prt0_mctprx_dropcnt(unsigned int uprt0_mctprx_dropcnt); +int iSetUP_DBG_CNT0_prt1_mctprx_dropcnt(unsigned int uprt1_mctprx_dropcnt); +int iSetUP_DBG_CNT0_prt2_mctprx_dropcnt(unsigned int uprt2_mctprx_dropcnt); +int iSetUP_DBG_CNT0_prt3_mctprx_dropcnt(unsigned int uprt3_mctprx_dropcnt); +int iSetUP_DBG_CNT1_upitf_all_apb_cnt(unsigned int uupitf_all_apb_cnt); +int iSetUP_DBG_CNT1_upitf_csr_apb_cnt(unsigned int uupitf_csr_apb_cnt); +int iSetUP_DBG_CNT1_upitf_cpi_apb_cnt(unsigned int uupitf_cpi_apb_cnt); +int iSetUP_RX_MB_BUF_LEN_ucpu_rx_mb_buf_len(unsigned int uucpu_rx_mb_buf_len); +int iSetUP_RX_MB_BUF_BA_ucpu_rx_mb_buf_ba(unsigned int uucpu_rx_mb_buf_ba); +int iSetUP_RX_MB_BUF_CI_ucpu_rx_mb_buf_ci(unsigned int uucpu_rx_mb_buf_ci); +int iSetUP_RX_MB_BUF_PI_ucpu_rx_mb_buf_pi(unsigned int uucpu_rx_mb_buf_pi); +int iSetUP_BAR_MAP_csr_bar_val(unsigned int ucsr_bar_val); +int iSetUP_BAR_MAP_msi_bar_val(unsigned int umsi_bar_val); +int iSetUP_BAR_MAP_dbl_bar_val(unsigned int udbl_bar_val); +int iSetUP_ACC_FUNC_IDX_ucpu_acc_func_idx(unsigned int uucpu_acc_func_idx); +int iSetUP_INT_STATUS2_ucpu_pcie_int_sts(unsigned int uucpu_pcie_int_sts); +int iSetUP_INT_STATUS2_ucpu_aeq_drop_int_sts(unsigned int uucpu_aeq_drop_int_sts); +int iSetUP_INT_STATUS2_octl_ecc_err_int_sts(unsigned int uoctl_ecc_err_int_sts); +int iSetUP_INT_STATUS2_octl_ecc_merr_int_sts(unsigned int uoctl_ecc_merr_int_sts); +int iSetUP_INT_STATUS2_octl_nonfatal_err_int_sts(unsigned int uoctl_nonfatal_err_int_sts); +int iSetUP_INT_STATUS2_octl_fatal_err_int_sts(unsigned int uoctl_fatal_err_int_sts); +int iSetUP_INT_STATUS2_dma_ecc_err_int_sts(unsigned int udma_ecc_err_int_sts); +int iSetUP_INT_STATUS2_dma_ecc_merr_int_sts(unsigned int udma_ecc_merr_int_sts); +int iSetUP_INT_STATUS2_dma_nonfatal_err_int_sts(unsigned int udma_nonfatal_err_int_sts); +int iSetUP_INT_STATUS2_dma_fatal_err_int_sts(unsigned int udma_fatal_err_int_sts); +int iSetUP_INT_CTL2_ucpu_pcie_int_en(unsigned int uucpu_pcie_int_en); +int iSetUP_INT_CTL2_ucpu_aeq_drop_int_en(unsigned int uucpu_aeq_drop_int_en); +int iSetUP_INT_CTL2_octl_ecc_err_int_en(unsigned int uoctl_ecc_err_int_en); +int iSetUP_INT_CTL2_octl_ecc_merr_int_en(unsigned int uoctl_ecc_merr_int_en); +int iSetUP_INT_CTL2_octl_nonfatal_err_int_en(unsigned int uoctl_nonfatal_err_int_en); +int iSetUP_INT_CTL2_octl_fatal_err_int_en(unsigned int uoctl_fatal_err_int_en); +int iSetUP_INT_CTL2_dma_ecc_err_int_en(unsigned int udma_ecc_err_int_en); +int iSetUP_INT_CTL2_dma_ecc_merr_int_en(unsigned int udma_ecc_merr_int_en); +int iSetUP_INT_CTL2_dma_nonfatal_err_int_en(unsigned int udma_nonfatal_err_int_en); +int iSetUP_INT_CTL2_dma_fatal_err_int_en(unsigned int udma_fatal_err_int_en); +int iSetUP_VIOAEQ_OTD_TH_ucpu_vioaeq_otd_th(unsigned int uucpu_vioaeq_otd_th); +int iSetUP_VIOAEQ_OTD_CNT_ucpu_vioaeq_otd_cnt(unsigned int uucpu_vioaeq_otd_cnt); +int iSetUP_VIOAEQ_OTD_REC_ucpu_vioaeq_otd_rec(unsigned int uucpu_vioaeq_otd_rec); +int iSetUP_VIOAEQ_DROP_RCD0_ucpu_vioaeq_drop0_func(unsigned int uucpu_vioaeq_drop0_func); +int iSetUP_VIOAEQ_DROP_RCD0_ucpu_vioaeq_drop0_vld(unsigned int uucpu_vioaeq_drop0_vld); +int iSetUP_VIOAEQ_DROP_RCD1_ucpu_vioaeq_drop1_func(unsigned int uucpu_vioaeq_drop1_func); +int iSetUP_VIOAEQ_DROP_RCD1_ucpu_vioaeq_drop1_vld(unsigned int uucpu_vioaeq_drop1_vld); +int iSetUP_VIOAEQ_DROP_RCD2_ucpu_vioaeq_drop2_func(unsigned int uucpu_vioaeq_drop2_func); +int iSetUP_VIOAEQ_DROP_RCD2_ucpu_vioaeq_drop2_vld(unsigned int uucpu_vioaeq_drop2_vld); +int iSetUP_VIOAEQ_DROP_RCD3_ucpu_vioaeq_drop3_func(unsigned int uucpu_vioaeq_drop3_func); +int iSetUP_VIOAEQ_DROP_RCD3_ucpu_vioaeq_drop3_vld(unsigned int uucpu_vioaeq_drop3_vld); +int iSetUP_UNCRT_ERR_DIS_ucpu_uncrt_err_dis(unsigned int uucpu_uncrt_err_dis); + +/* Define the union csr_function_attribute0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_glb_func_idx : 12; /* [11:0] */ + u32 af_assoc_pf_idx : 5; /* [16:12] */ + u32 af_itf_idx : 3; /* [19:17] */ + u32 af_vf_in_pf : 8; /* [27:20] */ + u32 af_pf_or_vf : 1; /* [28] */ + u32 rsv_0 : 2; /* [30:29] */ + u32 af_att_lrn : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute0_u; + +/* Define the union csr_function_attribute1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ppf_election : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 af_aeq_per_func : 2; /* [9:8] */ + u32 rsv_2 : 20; /* [29:10] */ + u32 af_up_ini_sts : 1; /* [30] */ + u32 af_pf_rst_sts : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute1_u; + +/* Define the union csr_function_attribute2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_per_func : 9; /* [8:0] */ + u32 af_dma_attr_per_func : 3; /* [11:9] */ + u32 rsv_3 : 4; /* [15:12] */ + u32 af_int_per_func : 11; /* [26:16] */ + u32 rsv_4 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute2_u; + +/* Define the union csr_function_attribute3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_vf_offset_for_nxt_pf : 12; /* [11:0] */ + u32 rsv_5 : 4; /* [15:12] */ + u32 af_vf_offset_for_cur_pf : 12; /* [27:16] */ + u32 rsv_6 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute3_u; + +/* Define the union csr_function_attribute4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_dbl_flush : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute4_u; + +/* Define the union csr_function_attribute5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_outbnd_flush : 1; /* [0] */ + u32 rsv_8 : 3; /* [3:1] */ + u32 ap_outbnd_flush : 5; /* [8:4] */ + u32 rsv_9 : 3; /* [11:9] */ + u32 af_round_bit : 1; /* [12] */ + u32 rsv_10 : 3; /* [15:13] */ + u32 cpi_rcv_chip_err : 1; /* [16] */ + u32 rsv_11 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute5_u; + +/* Define the union csr_function_attribute6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_status : 16; /* [15:0] */ + u32 rsvd : 6; /* [21:16] */ + u32 msix_flex_en : 1; /* [22] */ + u32 q_num : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute6_u; + +/* Define the union csr_function_tsk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk0_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk0_u; + +/* Define the union csr_function_tsk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk1_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk1_u; + +/* Define the union csr_function_tsk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk2_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk2_u; + +/* Define the union csr_function_tsk3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk3_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk3_u; + +/* Define the union csr_func_remap_table_entr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 20; /* [19:0] */ + u32 af_bme_bit : 1; /* [20] */ + u32 rsv_13 : 10; /* [30:21] */ + u32 af_vld_bit : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_remap_table_entr_u; + +/* Define the union csr_func_aeq_ci_indir_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_simple_indir_ci : 21; /* [20:0] */ + u32 aeq_simple_indir_armed : 1; /* [21] */ + u32 rsv_14 : 8; /* [29:22] */ + u32 aeq_simple_indir_idx : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_aeq_ci_indir_wr_u; + +/* Define the union csr_func_ceq_ci_indir_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_simple_indir_ci : 21; /* [20:0] */ + u32 ceq_simple_indir_armed : 1; /* [21] */ + u32 rsv_15 : 2; /* [23:22] */ + u32 ceq_simple_indir_idx : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ceq_ci_indir_wr_u; + +/* Define the union csr_func_msi_clr_indir_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_resend_timer_clr : 1; /* [0] */ + u32 msi_int_msk_set : 1; /* [1] */ + u32 msi_int_msk_clr : 1; /* [2] */ + u32 msi_auto_msk_set : 1; /* [3] */ + u32 msi_auto_msk_clr : 1; /* [4] */ + u32 rsv_16 : 17; /* [21:5] */ + u32 msi_simple_indir_idx : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_msi_clr_indir_wr_u; + +/* Define the union csr_func_ppf_elect_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_ppf_elect : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port0_u; + +/* Define the union csr_func_ppf_elect_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port1_ppf_elect : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port1_u; + +/* Define the union csr_func_ppf_elect_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port2_ppf_elect : 6; /* [5:0] */ + u32 rsv_19 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port2_u; + +/* Define the union csr_func_ppf_elect_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port3_ppf_elect : 6; /* [5:0] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port3_u; + +/* Define the union csr_func_ppf_elect_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port4_ppf_elect : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port4_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_function_attribute0_u function_attribute0[2]; /* 0 */ + volatile csr_function_attribute1_u function_attribute1[2]; /* 4 */ + volatile csr_function_attribute2_u function_attribute2[2]; /* 8 */ + volatile csr_function_attribute3_u function_attribute3[2]; /* C */ + volatile csr_function_attribute4_u function_attribute4[2]; /* 10 */ + volatile csr_function_attribute5_u function_attribute5[2]; /* 14 */ + volatile csr_function_attribute6_u function_attribute6[2]; /* 18 */ + volatile csr_function_tsk0_u function_tsk0[32]; /* 20 */ + volatile csr_function_tsk1_u function_tsk1[32]; /* 24 */ + volatile csr_function_tsk2_u function_tsk2[32]; /* 28 */ + volatile csr_function_tsk3_u function_tsk3[32]; /* 2C */ + volatile csr_func_remap_table_entr_u func_remap_table_entr[2]; /* 30 */ + volatile csr_func_aeq_ci_indir_wr_u func_aeq_ci_indir_wr; /* 50 */ + volatile csr_func_ceq_ci_indir_wr_u func_ceq_ci_indir_wr; /* 54 */ + volatile csr_func_msi_clr_indir_wr_u func_msi_clr_indir_wr; /* 58 */ + volatile csr_func_ppf_elect_port0_u func_ppf_elect_port0; /* 60 */ + volatile csr_func_ppf_elect_port1_u func_ppf_elect_port1; /* 64 */ + volatile csr_func_ppf_elect_port2_u func_ppf_elect_port2; /* 68 */ + volatile csr_func_ppf_elect_port3_u func_ppf_elect_port3; /* 6C */ + volatile csr_func_ppf_elect_port4_u func_ppf_elect_port4; /* 70 */ +} S_func_com_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_com_csr */ +extern volatile S_func_com_csr_REGS_TYPE *gopfunc_com_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetFUNCTION_ATTRIBUTE0_af_glb_func_idx(unsigned int uaf_glb_func_idx); +int iSetFUNCTION_ATTRIBUTE0_af_assoc_pf_idx(unsigned int uaf_assoc_pf_idx); +int iSetFUNCTION_ATTRIBUTE0_af_itf_idx(unsigned int uaf_itf_idx); +int iSetFUNCTION_ATTRIBUTE0_af_vf_in_pf(unsigned int uaf_vf_in_pf); +int iSetFUNCTION_ATTRIBUTE0_af_pf_or_vf(unsigned int uaf_pf_or_vf); +int iSetFUNCTION_ATTRIBUTE0_af_att_lrn(unsigned int uaf_att_lrn); +int iSetFUNCTION_ATTRIBUTE1_af_ppf_election(unsigned int uaf_ppf_election); +int iSetFUNCTION_ATTRIBUTE1_af_aeq_per_func(unsigned int uaf_aeq_per_func); +int iSetFUNCTION_ATTRIBUTE1_af_up_ini_sts(unsigned int uaf_up_ini_sts); +int iSetFUNCTION_ATTRIBUTE1_af_pf_rst_sts(unsigned int uaf_pf_rst_sts); +int iSetFUNCTION_ATTRIBUTE2_af_ceq_per_func(unsigned int uaf_ceq_per_func); +int iSetFUNCTION_ATTRIBUTE2_af_dma_attr_per_func(unsigned int uaf_dma_attr_per_func); +int iSetFUNCTION_ATTRIBUTE2_af_int_per_func(unsigned int uaf_int_per_func); +int iSetFUNCTION_ATTRIBUTE3_af_vf_offset_for_nxt_pf(unsigned int uaf_vf_offset_for_nxt_pf); +int iSetFUNCTION_ATTRIBUTE3_af_vf_offset_for_cur_pf(unsigned int uaf_vf_offset_for_cur_pf); +int iSetFUNCTION_ATTRIBUTE4_af_dbl_flush(unsigned int uaf_dbl_flush); +int iSetFUNCTION_ATTRIBUTE5_af_outbnd_flush(unsigned int uaf_outbnd_flush); +int iSetFUNCTION_ATTRIBUTE5_ap_outbnd_flush(unsigned int uap_outbnd_flush); +int iSetFUNCTION_ATTRIBUTE5_af_round_bit(unsigned int uaf_round_bit); +int iSetFUNCTION_ATTRIBUTE5_cpi_rcv_chip_err(unsigned int ucpi_rcv_chip_err); +int iSetFUNCTION_ATTRIBUTE6_af_simple_mb_tsk_csr(unsigned int uaf_simple_mb_tsk_csr); +int iSetFUNCTION_TSK0_pf_simple_mb_tsk0_csr(unsigned int upf_simple_mb_tsk0_csr); +int iSetFUNCTION_TSK1_pf_simple_mb_tsk1_csr(unsigned int upf_simple_mb_tsk1_csr); +int iSetFUNCTION_TSK2_pf_simple_mb_tsk2_csr(unsigned int upf_simple_mb_tsk2_csr); +int iSetFUNCTION_TSK3_pf_simple_mb_tsk3_csr(unsigned int upf_simple_mb_tsk3_csr); +int iSetFUNC_REMAP_TABLE_ENTR_af_bme_bit(unsigned int uaf_bme_bit); +int iSetFUNC_REMAP_TABLE_ENTR_af_vld_bit(unsigned int uaf_vld_bit); +int iSetFUNC_AEQ_CI_INDIR_WR_aeq_simple_indir_ci(unsigned int uaeq_simple_indir_ci); +int iSetFUNC_AEQ_CI_INDIR_WR_aeq_simple_indir_armed(unsigned int uaeq_simple_indir_armed); +int iSetFUNC_AEQ_CI_INDIR_WR_aeq_simple_indir_idx(unsigned int uaeq_simple_indir_idx); +int iSetFUNC_CEQ_CI_INDIR_WR_ceq_simple_indir_ci(unsigned int uceq_simple_indir_ci); +int iSetFUNC_CEQ_CI_INDIR_WR_ceq_simple_indir_armed(unsigned int uceq_simple_indir_armed); +int iSetFUNC_CEQ_CI_INDIR_WR_ceq_simple_indir_idx(unsigned int uceq_simple_indir_idx); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_resend_timer_clr(unsigned int umsi_resend_timer_clr); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_int_msk_set(unsigned int umsi_int_msk_set); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_int_msk_clr(unsigned int umsi_int_msk_clr); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_auto_msk_set(unsigned int umsi_auto_msk_set); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_auto_msk_clr(unsigned int umsi_auto_msk_clr); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_simple_indir_idx(unsigned int umsi_simple_indir_idx); +int iSetFUNC_PPF_ELECT_PORT0_port0_ppf_elect(unsigned int uport0_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT1_port1_ppf_elect(unsigned int uport1_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT2_port2_ppf_elect(unsigned int uport2_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT3_port3_ppf_elect(unsigned int uport3_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT4_port4_ppf_elect(unsigned int uport4_ppf_elect); + +/* Define the union csr_mailbox_dat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_0_u; + +/* Define the union csr_mailbox_dat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_1_u; + +/* Define the union csr_mailbox_dat_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_2_u; + +/* Define the union csr_mailbox_dat_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_3_u; + +/* Define the union csr_mailbox_dat_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_4_u; + +/* Define the union csr_mailbox_dat_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_5_u; + +/* Define the union csr_mailbox_dat_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_6_u; + +/* Define the union csr_mailbox_dat_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_7_u; + +/* Define the union csr_mailbox_dat_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_8_u; + +/* Define the union csr_mailbox_dat_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_9_u; + +/* Define the union csr_mailbox_dat_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_10_u; + +/* Define the union csr_mailbox_dat_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_11_u; + +/* Define the union csr_mailbox_dat_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_12_u; + +/* Define the union csr_mailbox_dat_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_13_u; + +/* Define the union csr_mailbox_dat_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_14_u; + +/* Define the union csr_mailbox_dat_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_15_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mailbox_dat_0_u mailbox_dat_0[2]; /* 0 */ + volatile csr_mailbox_dat_1_u mailbox_dat_1[2]; /* 4 */ + volatile csr_mailbox_dat_2_u mailbox_dat_2[2]; /* 8 */ + volatile csr_mailbox_dat_3_u mailbox_dat_3[2]; /* C */ + volatile csr_mailbox_dat_4_u mailbox_dat_4[2]; /* 10 */ + volatile csr_mailbox_dat_5_u mailbox_dat_5[2]; /* 14 */ + volatile csr_mailbox_dat_6_u mailbox_dat_6[2]; /* 18 */ + volatile csr_mailbox_dat_7_u mailbox_dat_7[2]; /* 1C */ + volatile csr_mailbox_dat_8_u mailbox_dat_8[2]; /* 20 */ + volatile csr_mailbox_dat_9_u mailbox_dat_9[2]; /* 24 */ + volatile csr_mailbox_dat_10_u mailbox_dat_10[2]; /* 28 */ + volatile csr_mailbox_dat_11_u mailbox_dat_11[2]; /* 2C */ + volatile csr_mailbox_dat_12_u mailbox_dat_12[2]; /* 30 */ + volatile csr_mailbox_dat_13_u mailbox_dat_13[2]; /* 34 */ + volatile csr_mailbox_dat_14_u mailbox_dat_14[2]; /* 38 */ + volatile csr_mailbox_dat_15_u mailbox_dat_15[2]; /* 3C */ +} S_func_mb_dat_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_mb_dat_csr */ +extern volatile S_func_mb_dat_csr_REGS_TYPE *gopfunc_mb_dat_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMAILBOX_DAT_0_af_mb_dat_0(unsigned int uaf_mb_dat_0); +int iSetMAILBOX_DAT_1_af_mb_dat_1(unsigned int uaf_mb_dat_1); +int iSetMAILBOX_DAT_2_af_mb_dat_2(unsigned int uaf_mb_dat_2); +int iSetMAILBOX_DAT_3_af_mb_dat_3(unsigned int uaf_mb_dat_3); +int iSetMAILBOX_DAT_4_af_mb_dat_4(unsigned int uaf_mb_dat_4); +int iSetMAILBOX_DAT_5_af_mb_dat_5(unsigned int uaf_mb_dat_5); +int iSetMAILBOX_DAT_6_af_mb_dat_6(unsigned int uaf_mb_dat_6); +int iSetMAILBOX_DAT_7_af_mb_dat_7(unsigned int uaf_mb_dat_7); +int iSetMAILBOX_DAT_8_af_mb_dat_8(unsigned int uaf_mb_dat_8); +int iSetMAILBOX_DAT_9_af_mb_dat_9(unsigned int uaf_mb_dat_9); +int iSetMAILBOX_DAT_10_af_mb_dat_10(unsigned int uaf_mb_dat_10); +int iSetMAILBOX_DAT_11_af_mb_dat_11(unsigned int uaf_mb_dat_11); +int iSetMAILBOX_DAT_12_af_mb_dat_12(unsigned int uaf_mb_dat_12); +int iSetMAILBOX_DAT_13_af_mb_dat_13(unsigned int uaf_mb_dat_13); +int iSetMAILBOX_DAT_14_af_mb_dat_14(unsigned int uaf_mb_dat_14); +int iSetMAILBOX_DAT_15_af_mb_dat_15(unsigned int uaf_mb_dat_15); + +/* Define the union csr_mailbox_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_trigger_aeqe : 1; /* [0] */ + u32 af_mb_tx_req : 1; /* [1] */ + u32 rsv_0 : 14; /* [15:2] */ + u32 af_mb_dest_func : 13; /* [28:16] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_control_u; + +/* Define the union csr_mailbox_int_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 10; /* [9:0] */ + u32 af_mb_dest_aeqn : 2; /* [11:10] */ + u32 af_mb_src_aeqn : 2; /* [13:12] */ + u32 af_mb_sts_dma_attr_offset : 6; /* [19:14] */ + u32 af_mb_tx_size : 5; /* [24:20] */ + u32 af_mb_sts_dma_so_ro : 2; /* [26:25] */ + u32 rsv_3 : 1; /* [27] */ + u32 af_mb_wr_sts_en : 1; /* [28] */ + u32 af_mb_tx_sts : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_int_offset_u; + +/* Define the union csr_mailbox_result_back_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_wr_sts_addrh : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_result_back_h_u; + +/* Define the union csr_mailbox_result_back_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_wr_sts_addrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_result_back_l_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mailbox_control_u mailbox_control[2]; /* 0 */ + volatile csr_mailbox_int_offset_u mailbox_int_offset[2]; /* 4 */ + volatile csr_mailbox_result_back_h_u mailbox_result_back_h[2]; /* 8 */ + volatile csr_mailbox_result_back_l_u mailbox_result_back_l[2]; /* C */ +} S_func_mb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_mb_csr */ +extern volatile S_func_mb_csr_REGS_TYPE *gopfunc_mb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMAILBOX_CONTROL_af_mb_trigger_aeqe(unsigned int uaf_mb_trigger_aeqe); +int iSetMAILBOX_CONTROL_af_mb_tx_req(unsigned int uaf_mb_tx_req); +int iSetMAILBOX_CONTROL_af_mb_dest_func(unsigned int uaf_mb_dest_func); +int iSetMAILBOX_INT_OFFSET_af_mb_dest_aeqn(unsigned int uaf_mb_dest_aeqn); +int iSetMAILBOX_INT_OFFSET_af_mb_src_aeqn(unsigned int uaf_mb_src_aeqn); +int iSetMAILBOX_INT_OFFSET_af_mb_sts_dma_attr_offset(unsigned int uaf_mb_sts_dma_attr_offset); +int iSetMAILBOX_INT_OFFSET_af_mb_tx_size(unsigned int uaf_mb_tx_size); +int iSetMAILBOX_INT_OFFSET_af_mb_sts_dma_so_ro(unsigned int uaf_mb_sts_dma_so_ro); +int iSetMAILBOX_INT_OFFSET_af_mb_wr_sts_en(unsigned int uaf_mb_wr_sts_en); +int iSetMAILBOX_INT_OFFSET_af_mb_tx_sts(unsigned int uaf_mb_tx_sts); +int iSetMAILBOX_RESULT_BACK_H_af_mb_wr_sts_addrh(unsigned int uaf_mb_wr_sts_addrh); +int iSetMAILBOX_RESULT_BACK_L_af_mb_wr_sts_addrl(unsigned int uaf_mb_wr_sts_addrl); + +/* Define the union csr_aeq_ctl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_int_offset : 10; /* [9:0] */ + u32 rsv_0 : 2; /* [11:10] */ + u32 af_aeq_dma_attr_offset : 6; /* [17:12] */ + u32 af_aeq_dma_so : 2; /* [19:18] */ + u32 af_aeq_port : 3; /* [22:20] */ + u32 rsv_1 : 8; /* [30:23] */ + u32 af_aeq_int_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ctl_0_u; + +/* Define the union csr_aeq_ctl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_length : 21; /* [20:0] */ + u32 rsv_2 : 3; /* [23:21] */ + u32 af_aeqe_size : 2; /* [25:24] */ + u32 rsv_3 : 2; /* [27:26] */ + u32 af_aeq_page : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ctl_1_u; + +/* Define the union csr_aeq_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_ci : 21; /* [20:0] */ + u32 rsv_4 : 10; /* [30:21] */ + u32 af_aeq_int_armed : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ci_u; + +/* Define the union csr_aeq_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_pi : 21; /* [20:0] */ + u32 rsv_5 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_pi_u; + +/* Define the union csr_aeq_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_indir_idx : 10; /* [9:0] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_indir_idx_u; + +/* Define the union csr_function_aeq_mtt0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt0_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt0_h_u; + +/* Define the union csr_function_aeq_mtt0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 12; /* [11:0] */ + u32 aeq_mtt0_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt0_l_u; + +/* Define the union csr_function_aeq_mtt1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt1_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt1_h_u; + +/* Define the union csr_function_aeq_mtt1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_8 : 12; /* [11:0] */ + u32 aeq_mtt1_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt1_l_u; + +/* Define the union csr_function_aeq_mtt2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt2_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt2_h_u; + +/* Define the union csr_function_aeq_mtt2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 12; /* [11:0] */ + u32 aeq_mtt2_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt2_l_u; + +/* Define the union csr_function_aeq_mtt3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt3_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt3_h_u; + +/* Define the union csr_function_aeq_mtt3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_10 : 12; /* [11:0] */ + u32 aeq_mtt3_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt3_l_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_aeq_ctl_0_u aeq_ctl_0[2]; /* 0 */ + volatile csr_aeq_ctl_1_u aeq_ctl_1[2]; /* 4 */ + volatile csr_aeq_ci_u aeq_ci[2]; /* 8 */ + volatile csr_aeq_pi_u aeq_pi[2]; /* C */ + volatile csr_aeq_indir_idx_u aeq_indir_idx[2]; /* 10 */ + volatile csr_function_aeq_mtt0_h_u function_aeq_mtt0_h[2]; /* 40 */ + volatile csr_function_aeq_mtt0_l_u function_aeq_mtt0_l[2]; /* 44 */ + volatile csr_function_aeq_mtt1_h_u function_aeq_mtt1_h[2]; /* 48 */ + volatile csr_function_aeq_mtt1_l_u function_aeq_mtt1_l[2]; /* 4C */ + volatile csr_function_aeq_mtt2_h_u function_aeq_mtt2_h[2]; /* 50 */ + volatile csr_function_aeq_mtt2_l_u function_aeq_mtt2_l[2]; /* 54 */ + volatile csr_function_aeq_mtt3_h_u function_aeq_mtt3_h[2]; /* 58 */ + volatile csr_function_aeq_mtt3_l_u function_aeq_mtt3_l[2]; /* 5C */ +} S_func_aeq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_aeq_csr */ +extern volatile S_func_aeq_csr_REGS_TYPE *gopfunc_aeq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAEQ_CTL_0_af_aeq_int_offset(unsigned int uaf_aeq_int_offset); +int iSetAEQ_CTL_0_af_aeq_dma_attr_offset(unsigned int uaf_aeq_dma_attr_offset); +int iSetAEQ_CTL_0_af_aeq_dma_so(unsigned int uaf_aeq_dma_so); +int iSetAEQ_CTL_0_af_aeq_port(unsigned int uaf_aeq_port); +int iSetAEQ_CTL_0_af_aeq_int_mode(unsigned int uaf_aeq_int_mode); +int iSetAEQ_CTL_1_af_aeq_length(unsigned int uaf_aeq_length); +int iSetAEQ_CTL_1_af_aeqe_size(unsigned int uaf_aeqe_size); +int iSetAEQ_CTL_1_af_aeq_page(unsigned int uaf_aeq_page); +int iSetAEQ_CI_af_aeq_ci(unsigned int uaf_aeq_ci); +int iSetAEQ_CI_af_aeq_int_armed(unsigned int uaf_aeq_int_armed); +int iSetAEQ_PI_af_aeq_pi(unsigned int uaf_aeq_pi); +int iSetAEQ_INDIR_IDX_aeq_indir_idx(unsigned int uaeq_indir_idx); +int iSetFUNCTION_AEQ_MTT0_H_aeq_mtt0_addr_h(unsigned int uaeq_mtt0_addr_h); +int iSetFUNCTION_AEQ_MTT0_L_aeq_mtt0_addr_l(unsigned int uaeq_mtt0_addr_l); +int iSetFUNCTION_AEQ_MTT1_H_aeq_mtt1_addr_h(unsigned int uaeq_mtt1_addr_h); +int iSetFUNCTION_AEQ_MTT1_L_aeq_mtt1_addr_l(unsigned int uaeq_mtt1_addr_l); +int iSetFUNCTION_AEQ_MTT2_H_aeq_mtt2_addr_h(unsigned int uaeq_mtt2_addr_h); +int iSetFUNCTION_AEQ_MTT2_L_aeq_mtt2_addr_l(unsigned int uaeq_mtt2_addr_l); +int iSetFUNCTION_AEQ_MTT3_H_aeq_mtt3_addr_h(unsigned int uaeq_mtt3_addr_h); +int iSetFUNCTION_AEQ_MTT3_L_aeq_mtt3_addr_l(unsigned int uaeq_mtt3_addr_l); + +/* Define the union csr_ceq_ctl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_int_offset : 10; /* [9:0] */ + u32 rsv_0 : 2; /* [11:10] */ + u32 af_ceq_dma_attr_offset : 6; /* [17:12] */ + u32 rsv_1 : 2; /* [19:18] */ + u32 af_ceqe_kickoff_lmt : 4; /* [23:20] */ + u32 af_ceq_pcie_port : 3; /* [26:24] */ + u32 af_ceq_page : 4; /* [30:27] */ + u32 af_ceq_int_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_ctl_0_u; + +/* Define the union csr_ceq_ctl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_length : 20; /* [19:0] */ + u32 af_ceq_glb_func_idx : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_ctl_1_u; + +/* Define the union csr_ceq_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_ci : 21; /* [20:0] */ + u32 rsv_2 : 10; /* [30:21] */ + u32 af_ceq_int_armed : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_ci_u; + +/* Define the union csr_ceq_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_pi : 21; /* [20:0] */ + u32 rsv_3 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_pi_u; + +/* Define the union csr_ceq_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_indir_idx : 10; /* [9:0] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_indir_idx_u; + +/* Define the union csr_function_ceq_mtt0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt0_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt0_h_u; + +/* Define the union csr_function_ceq_mtt0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt0_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt0_l_u; + +/* Define the union csr_function_ceq_mtt1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt1_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt1_h_u; + +/* Define the union csr_function_ceq_mtt1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt1_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt1_l_u; + +/* Define the union csr_function_ceq_mtt2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt2_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt2_h_u; + +/* Define the union csr_function_ceq_mtt2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt2_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt2_l_u; + +/* Define the union csr_function_ceq_mtt3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt3_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt3_h_u; + +/* Define the union csr_function_ceq_mtt3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt3_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt3_l_u; + +/* Define the union csr_function_ceq_mtt4_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt4_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt4_h_u; + +/* Define the union csr_function_ceq_mtt4_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt4_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt4_l_u; + +/* Define the union csr_function_ceq_mtt5_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt5_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt5_h_u; + +/* Define the union csr_function_ceq_mtt5_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt5_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt5_l_u; + +/* Define the union csr_function_ceq_mtt6_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt6_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt6_h_u; + +/* Define the union csr_function_ceq_mtt6_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt6_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt6_l_u; + +/* Define the union csr_function_ceq_mtt7_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt7_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt7_h_u; + +/* Define the union csr_function_ceq_mtt7_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt7_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt7_l_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ceq_ctl_0_u ceq_ctl_0[2]; /* 0 */ + volatile csr_ceq_ctl_1_u ceq_ctl_1[2]; /* 4 */ + volatile csr_ceq_ci_u ceq_ci[2]; /* 8 */ + volatile csr_ceq_pi_u ceq_pi[2]; /* C */ + volatile csr_ceq_indir_idx_u ceq_indir_idx[2]; /* 10 */ + volatile csr_function_ceq_mtt0_h_u function_ceq_mtt0_h[2]; /* 40 */ + volatile csr_function_ceq_mtt0_l_u function_ceq_mtt0_l[2]; /* 44 */ + volatile csr_function_ceq_mtt1_h_u function_ceq_mtt1_h[2]; /* 48 */ + volatile csr_function_ceq_mtt1_l_u function_ceq_mtt1_l[2]; /* 4C */ + volatile csr_function_ceq_mtt2_h_u function_ceq_mtt2_h[2]; /* 50 */ + volatile csr_function_ceq_mtt2_l_u function_ceq_mtt2_l[2]; /* 54 */ + volatile csr_function_ceq_mtt3_h_u function_ceq_mtt3_h[2]; /* 58 */ + volatile csr_function_ceq_mtt3_l_u function_ceq_mtt3_l[2]; /* 5C */ + volatile csr_function_ceq_mtt4_h_u function_ceq_mtt4_h[2]; /* 60 */ + volatile csr_function_ceq_mtt4_l_u function_ceq_mtt4_l[2]; /* 64 */ + volatile csr_function_ceq_mtt5_h_u function_ceq_mtt5_h[2]; /* 68 */ + volatile csr_function_ceq_mtt5_l_u function_ceq_mtt5_l[2]; /* 6C */ + volatile csr_function_ceq_mtt6_h_u function_ceq_mtt6_h[2]; /* 70 */ + volatile csr_function_ceq_mtt6_l_u function_ceq_mtt6_l[2]; /* 74 */ + volatile csr_function_ceq_mtt7_h_u function_ceq_mtt7_h[2]; /* 78 */ + volatile csr_function_ceq_mtt7_l_u function_ceq_mtt7_l[2]; /* 7C */ +} S_func_ceq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_ceq_csr */ +extern volatile S_func_ceq_csr_REGS_TYPE *gopfunc_ceq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCEQ_CTL_0_af_ceq_int_offset(unsigned int uaf_ceq_int_offset); +int iSetCEQ_CTL_0_af_ceq_dma_attr_offset(unsigned int uaf_ceq_dma_attr_offset); +int iSetCEQ_CTL_0_af_ceqe_kickoff_lmt(unsigned int uaf_ceqe_kickoff_lmt); +int iSetCEQ_CTL_0_af_ceq_pcie_port(unsigned int uaf_ceq_pcie_port); +int iSetCEQ_CTL_0_af_ceq_page(unsigned int uaf_ceq_page); +int iSetCEQ_CTL_0_af_ceq_int_mode(unsigned int uaf_ceq_int_mode); +int iSetCEQ_CTL_1_af_ceq_length(unsigned int uaf_ceq_length); +int iSetCEQ_CTL_1_af_ceq_glb_func_idx(unsigned int uaf_ceq_glb_func_idx); +int iSetCEQ_CI_af_ceq_ci(unsigned int uaf_ceq_ci); +int iSetCEQ_CI_af_ceq_int_armed(unsigned int uaf_ceq_int_armed); +int iSetCEQ_PI_af_ceq_pi(unsigned int uaf_ceq_pi); +int iSetCEQ_INDIR_IDX_ceq_indir_idx(unsigned int uceq_indir_idx); +int iSetFUNCTION_CEQ_MTT0_H_ceq_mtt0_addr_h(unsigned int uceq_mtt0_addr_h); +int iSetFUNCTION_CEQ_MTT0_L_ceq_mtt0_addr_l(unsigned int uceq_mtt0_addr_l); +int iSetFUNCTION_CEQ_MTT1_H_ceq_mtt1_addr_h(unsigned int uceq_mtt1_addr_h); +int iSetFUNCTION_CEQ_MTT1_L_ceq_mtt1_addr_l(unsigned int uceq_mtt1_addr_l); +int iSetFUNCTION_CEQ_MTT2_H_ceq_mtt2_addr_h(unsigned int uceq_mtt2_addr_h); +int iSetFUNCTION_CEQ_MTT2_L_ceq_mtt2_addr_l(unsigned int uceq_mtt2_addr_l); +int iSetFUNCTION_CEQ_MTT3_H_ceq_mtt3_addr_h(unsigned int uceq_mtt3_addr_h); +int iSetFUNCTION_CEQ_MTT3_L_ceq_mtt3_addr_l(unsigned int uceq_mtt3_addr_l); +int iSetFUNCTION_CEQ_MTT4_H_ceq_mtt4_addr_h(unsigned int uceq_mtt4_addr_h); +int iSetFUNCTION_CEQ_MTT4_L_ceq_mtt4_addr_l(unsigned int uceq_mtt4_addr_l); +int iSetFUNCTION_CEQ_MTT5_H_ceq_mtt5_addr_h(unsigned int uceq_mtt5_addr_h); +int iSetFUNCTION_CEQ_MTT5_L_ceq_mtt5_addr_l(unsigned int uceq_mtt5_addr_l); +int iSetFUNCTION_CEQ_MTT6_H_ceq_mtt6_addr_h(unsigned int uceq_mtt6_addr_h); +int iSetFUNCTION_CEQ_MTT6_L_ceq_mtt6_addr_l(unsigned int uceq_mtt6_addr_l); +int iSetFUNCTION_CEQ_MTT7_H_ceq_mtt7_addr_h(unsigned int uceq_mtt7_addr_h); +int iSetFUNCTION_CEQ_MTT7_L_ceq_mtt7_addr_l(unsigned int uceq_mtt7_addr_l); + +/* Define the union csr_msi_control_csr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending_limt : 8; /* [7:0] */ + u32 coalesc_timer_cfg : 8; /* [15:8] */ + u32 lli_timer_cfg : 8; /* [23:16] */ + u32 lli_credit_limit : 5; /* [28:24] */ + u32 resend_timer_cfg : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_0_u; + +/* Define the union csr_msi_control_csr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lli_tmier_cnt : 8; /* [7:0] */ + u32 lli_credit_cnt : 8; /* [15:8] */ + u32 coalesct_timer_cnt : 8; /* [23:16] */ + u32 pengding_cnt : 5; /* [28:24] */ + u32 resend_timer_cnt : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_1_u; + +/* Define the union csr_msi_control_csr_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 auto_msk_en : 1; /* [0] */ + u32 int_msk : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_2_u; + +/* Define the union csr_msi_control_csr_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_resend_timer_clr : 1; /* [0] */ + u32 msi_int_msk_set : 1; /* [1] */ + u32 msi_int_msk_clr : 1; /* [2] */ + u32 msi_auto_msk_set : 1; /* [3] */ + u32 msi_auto_msk_clr : 1; /* [4] */ + u32 rsv_1 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_3_u; + +/* Define the union csr_msi_control_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_ctl_indir_idx : 10; /* [9:0] */ + u32 rsv_2 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_indir_idx_u; + +/* Define the union csr_msi_control_csr_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_offset_in_func : 10; /* [9:0] */ + u32 rsv_3 : 6; /* [15:10] */ + u32 msi_glb_func_idx : 12; /* [27:16] */ + u32 rsv_4 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_4_u; + +/* Define the union csr_function_dma_attr_entr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_st : 8; /* [7:0] */ + u32 tlp_at : 2; /* [9:8] */ + u32 tlp_ph : 2; /* [11:10] */ + u32 tlp_no_snooping : 1; /* [12] */ + u32 tlp_en : 1; /* [13] */ + u32 rsv_5 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_dma_attr_entr_u; + +/* Define the union csr_dma_attr_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_attr_indir_idx : 10; /* [9:0] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_attr_indir_idx_u; + +/* Define the union csr_pf_intx_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask0_u; + +/* Define the union csr_pf_intx_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask1_u; + +/* Define the union csr_pf_intx_mask2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask2_u; + +/* Define the union csr_pf_intx_mask3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask3_u; + +/* Define the union csr_pf_intx_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status0_u; + +/* Define the union csr_pf_intx_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status1_u; + +/* Define the union csr_pf_intx_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status2_u; + +/* Define the union csr_pf_intx_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msi_control_csr_0_u msi_control_csr_0[2]; /* 0 */ + volatile csr_msi_control_csr_1_u msi_control_csr_1[2]; /* 4 */ + volatile csr_msi_control_csr_2_u msi_control_csr_2[2]; /* 8 */ + volatile csr_msi_control_csr_3_u msi_control_csr_3[2]; /* C */ + volatile csr_msi_control_indir_idx_u msi_control_indir_idx; /* 10 */ + volatile csr_msi_control_csr_4_u msi_control_csr_4[2]; /* 14 */ + volatile csr_function_dma_attr_entr_u function_dma_attr_entr[2]; /* 80000 */ + volatile csr_dma_attr_indir_idx_u dma_attr_indir_idx; /* 10 */ + volatile csr_pf_intx_mask0_u pf_intx_mask0[32]; /* A0000 */ + volatile csr_pf_intx_mask1_u pf_intx_mask1[32]; /* A0004 */ + volatile csr_pf_intx_mask2_u pf_intx_mask2[32]; /* A0008 */ + volatile csr_pf_intx_mask3_u pf_intx_mask3[32]; /* A000C */ + volatile csr_pf_intx_status0_u pf_intx_status0[32]; /* A0010 */ + volatile csr_pf_intx_status1_u pf_intx_status1[32]; /* A0014 */ + volatile csr_pf_intx_status2_u pf_intx_status2[32]; /* A0018 */ + volatile csr_pf_intx_status3_u pf_intx_status3[32]; /* A001C */ +} S_func_int_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_int_csr */ +extern volatile S_func_int_csr_REGS_TYPE *gopfunc_int_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMSI_CONTROL_CSR_0_pending_limt(unsigned int upending_limt); +int iSetMSI_CONTROL_CSR_0_coalesc_timer_cfg(unsigned int ucoalesc_timer_cfg); +int iSetMSI_CONTROL_CSR_0_lli_timer_cfg(unsigned int ulli_timer_cfg); +int iSetMSI_CONTROL_CSR_0_lli_credit_limit(unsigned int ulli_credit_limit); +int iSetMSI_CONTROL_CSR_0_resend_timer_cfg(unsigned int uresend_timer_cfg); +int iSetMSI_CONTROL_CSR_1_lli_tmier_cnt(unsigned int ulli_tmier_cnt); +int iSetMSI_CONTROL_CSR_1_lli_credit_cnt(unsigned int ulli_credit_cnt); +int iSetMSI_CONTROL_CSR_1_coalesct_timer_cnt(unsigned int ucoalesct_timer_cnt); +int iSetMSI_CONTROL_CSR_1_pengding_cnt(unsigned int upengding_cnt); +int iSetMSI_CONTROL_CSR_1_resend_timer_cnt(unsigned int uresend_timer_cnt); +int iSetMSI_CONTROL_CSR_2_auto_msk_en(unsigned int uauto_msk_en); +int iSetMSI_CONTROL_CSR_2_int_msk(unsigned int uint_msk); +int iSetMSI_CONTROL_CSR_3_msi_resend_timer_clr(unsigned int umsi_resend_timer_clr); +int iSetMSI_CONTROL_CSR_3_msi_int_msk_set(unsigned int umsi_int_msk_set); +int iSetMSI_CONTROL_CSR_3_msi_int_msk_clr(unsigned int umsi_int_msk_clr); +int iSetMSI_CONTROL_CSR_3_msi_auto_msk_set(unsigned int umsi_auto_msk_set); +int iSetMSI_CONTROL_CSR_3_msi_auto_msk_clr(unsigned int umsi_auto_msk_clr); +int iSetMSI_CONTROL_INDIR_IDX_msi_ctl_indir_idx(unsigned int umsi_ctl_indir_idx); +int iSetMSI_CONTROL_CSR_4_msi_offset_in_func(unsigned int umsi_offset_in_func); +int iSetMSI_CONTROL_CSR_4_msi_glb_func_idx(unsigned int umsi_glb_func_idx); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_st(unsigned int utlp_st); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_at(unsigned int utlp_at); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_ph(unsigned int utlp_ph); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_no_snooping(unsigned int utlp_no_snooping); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_en(unsigned int utlp_en); +int iSetDMA_ATTR_INDIR_IDX_dma_attr_indir_idx(unsigned int udma_attr_indir_idx); +int iSetPF_INTX_MASK0_pf_intx_mask_127_96(unsigned int upf_intx_mask_127_96); +int iSetPF_INTX_MASK1_pf_intx_mask_95_64(unsigned int upf_intx_mask_95_64); +int iSetPF_INTX_MASK2_pf_intx_mask_63_32(unsigned int upf_intx_mask_63_32); +int iSetPF_INTX_MASK3_pf_intx_mask_31_0(unsigned int upf_intx_mask_31_0); +int iSetPF_INTX_STATUS0_pf_intx_status_127_96(unsigned int upf_intx_status_127_96); +int iSetPF_INTX_STATUS1_pf_intx_status_95_64(unsigned int upf_intx_status_95_64); +int iSetPF_INTX_STATUS2_pf_intx_status_63_32(unsigned int upf_intx_status_63_32); +int iSetPF_INTX_STATUS3_pf_intx_status_31_0(unsigned int upf_intx_status_31_0); + +/* Define the union csr_ppf_election_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_ppf_elect : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppf_election_u; + +/* Define the union csr_mpf_election_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mpf_elect : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpf_election_u; + +/* Define the union csr_ucpu_clp_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_req_size : 11; /* [10:0] */ + u32 rsv_2 : 5; /* [15:11] */ + u32 port_clp_rsp_size : 11; /* [26:16] */ + u32 rsv_3 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_size_u; + +/* Define the union csr_ucpu_clp_reqbase_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_req_base : 27; /* [26:0] */ + u32 rsv_4 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_reqbase_u; + +/* Define the union csr_ucpu_clp_rspbase_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_rsp_base : 27; /* [26:0] */ + u32 rsv_5 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_rspbase_u; + +/* Define the union csr_ucpu_clp_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_req_len : 11; /* [10:0] */ + u32 rsv_6 : 20; /* [30:11] */ + u32 port_clp_req_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_req_u; + +/* Define the union csr_ucpu_clp_rsp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_rsp_len : 11; /* [10:0] */ + u32 rsv_7 : 20; /* [30:11] */ + u32 port_clp_rsp_rdy : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_rsp_u; + +/* Define the union csr_host_mpu_notify_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_mpu_pf_id : 5; /* [4:0] */ + u32 rsv_8 : 26; /* [30:5] */ + u32 host_mpu_notify : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_mpu_notify_ctl_u; + +/* Define the union csr_mpu_host_notify_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host_func_id : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 mpu_host_vct_id : 10; /* [25:16] */ + u32 rsv_10 : 4; /* [29:26] */ + u32 mpu_host_int_en : 1; /* [30] */ + u32 mpu_host_notify : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host_notify_ctl_u; + +/* Define the union csr_host0_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host0_mpu_notify_data_u; + +/* Define the union csr_mpu_host0_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host0_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host0_notify_data_u; + +/* Define the union csr_host1_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host1_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host1_mpu_notify_data_u; + +/* Define the union csr_mpu_host1_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host1_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host1_notify_data_u; + +/* Define the union csr_host2_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host2_mpu_notify_data_u; + +/* Define the union csr_mpu_host2_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host2_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host2_notify_data_u; + +/* Define the union csr_host3_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host3_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host3_mpu_notify_data_u; + +/* Define the union csr_mpu_host3_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host3_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host3_notify_data_u; + +/* Define the union csr_host4_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host4_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host4_mpu_notify_data_u; + +/* Define the union csr_mpu_host4_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host4_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host4_notify_data_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ppf_election_u ppf_election[5]; /* 0 */ + volatile csr_mpf_election_u mpf_election; /* 20 */ + volatile csr_ucpu_clp_size_u ucpu_clp_size[4]; /* 40 */ + volatile csr_ucpu_clp_reqbase_u ucpu_clp_reqbase[4]; /* 44 */ + volatile csr_ucpu_clp_rspbase_u ucpu_clp_rspbase[4]; /* 48 */ + volatile csr_ucpu_clp_req_u ucpu_clp_req[4]; /* 4C */ + volatile csr_ucpu_clp_rsp_u ucpu_clp_rsp[4]; /* 50 */ + volatile csr_host_mpu_notify_ctl_u host_mpu_notify_ctl[5]; /* C0 */ + volatile csr_mpu_host_notify_ctl_u mpu_host_notify_ctl[5]; /* C4 */ + volatile csr_host0_mpu_notify_data_u host0_mpu_notify_data[32]; /* 100 */ + volatile csr_mpu_host0_notify_data_u mpu_host0_notify_data[32]; /* 180 */ + volatile csr_host1_mpu_notify_data_u host1_mpu_notify_data[32]; /* 200 */ + volatile csr_mpu_host1_notify_data_u mpu_host1_notify_data[32]; /* 280 */ + volatile csr_host2_mpu_notify_data_u host2_mpu_notify_data[32]; /* 300 */ + volatile csr_mpu_host2_notify_data_u mpu_host2_notify_data[32]; /* 380 */ + volatile csr_host3_mpu_notify_data_u host3_mpu_notify_data[32]; /* 400 */ + volatile csr_mpu_host3_notify_data_u mpu_host3_notify_data[32]; /* 480 */ + volatile csr_host4_mpu_notify_data_u host4_mpu_notify_data[32]; /* 500 */ + volatile csr_mpu_host4_notify_data_u mpu_host4_notify_data[32]; /* 580 */ +} S_host_csr_REGS_TYPE; + +/* Declare the struct pointor of the module host_csr */ +extern volatile S_host_csr_REGS_TYPE *gophost_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPPF_ELECTION_port_ppf_elect(unsigned int uport_ppf_elect); +int iSetMPF_ELECTION_glb_mpf_elect(unsigned int uglb_mpf_elect); +int iSetUCPU_CLP_SIZE_port_clp_req_size(unsigned int uport_clp_req_size); +int iSetUCPU_CLP_SIZE_port_clp_rsp_size(unsigned int uport_clp_rsp_size); +int iSetUCPU_CLP_REQBASE_port_clp_req_base(unsigned int uport_clp_req_base); +int iSetUCPU_CLP_RSPBASE_port_clp_rsp_base(unsigned int uport_clp_rsp_base); +int iSetUCPU_CLP_REQ_port_clp_req_len(unsigned int uport_clp_req_len); +int iSetUCPU_CLP_REQ_port_clp_req_start(unsigned int uport_clp_req_start); +int iSetUCPU_CLP_RSP_port_clp_rsp_len(unsigned int uport_clp_rsp_len); +int iSetUCPU_CLP_RSP_port_clp_rsp_rdy(unsigned int uport_clp_rsp_rdy); +int iSetHOST_MPU_NOTIFY_CTL_host_mpu_pf_id(unsigned int uhost_mpu_pf_id); +int iSetHOST_MPU_NOTIFY_CTL_host_mpu_notify(unsigned int uhost_mpu_notify); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_func_id(unsigned int umpu_host_func_id); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_vct_id(unsigned int umpu_host_vct_id); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_int_en(unsigned int umpu_host_int_en); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_notify(unsigned int umpu_host_notify); +int iSetHOST0_MPU_NOTIFY_DATA_host0_mpu_notify_data(unsigned int uhost0_mpu_notify_data); +int iSetMPU_HOST0_NOTIFY_DATA_mpu_host0_notify_data(unsigned int umpu_host0_notify_data); +int iSetHOST1_MPU_NOTIFY_DATA_host1_mpu_notify_data(unsigned int uhost1_mpu_notify_data); +int iSetMPU_HOST1_NOTIFY_DATA_mpu_host1_notify_data(unsigned int umpu_host1_notify_data); +int iSetHOST2_MPU_NOTIFY_DATA_host2_mpu_notify_data(unsigned int uhost2_mpu_notify_data); +int iSetMPU_HOST2_NOTIFY_DATA_mpu_host2_notify_data(unsigned int umpu_host2_notify_data); +int iSetHOST3_MPU_NOTIFY_DATA_host3_mpu_notify_data(unsigned int uhost3_mpu_notify_data); +int iSetMPU_HOST3_NOTIFY_DATA_mpu_host3_notify_data(unsigned int umpu_host3_notify_data); +int iSetHOST4_MPU_NOTIFY_DATA_host4_mpu_notify_data(unsigned int uhost4_mpu_notify_data); +int iSetMPU_HOST4_NOTIFY_DATA_mpu_host4_notify_data(unsigned int umpu_host4_notify_data); + +/* Define the union csr_glb_cpi_version_csr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_version_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_version_csr_u; + +/* Define the union csr_glb_x86_req_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_x86_req_crd_flush_max : 5; /* [4:0] */ + u32 rsv_0 : 3; /* [7:5] */ + u32 glb_x86_req_crd_flush_en : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_x86_req_crd_flush_ctl_u; + +/* Define the union csr_glb_x86_cpl_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_x86_cpl_crd_flush_max : 5; /* [4:0] */ + u32 rsv_2 : 3; /* [7:5] */ + u32 glb_x86_cpl_crd_flush_en : 1; /* [8] */ + u32 rsv_3 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_x86_cpl_crd_flush_ctl_u; + +/* Define the union csr_glb_spu_x86_acc_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_req_acc_weight_port : 8; /* [7:0] */ + u32 glb_cpl_acc_weight_port : 8; /* [15:8] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_spu_x86_acc_weight_u; + +/* Define the union csr_glb_port_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_port_mode_cfg : 2; /* [1:0] */ + u32 rsv_5 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port_mode_u; + +/* Define the union csr_glb_spu_req_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_spu_req_crd_flush_max : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 glb_spu_req_crd_flush_en : 1; /* [8] */ + u32 rsv_7 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_spu_req_crd_flush_ctl_u; + +/* Define the union csr_glb_spu_cpl_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_spu_cpl_crd_flush_max : 5; /* [4:0] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 glb_spu_cpl_crd_flush_en : 1; /* [8] */ + u32 rsv_9 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_spu_cpl_crd_flush_ctl_u; + +/* Define the union csr_glb_res_per_func_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_aeq_per_pf : 2; /* [1:0] */ + u32 glb_aeq_per_vf : 2; /* [3:2] */ + u32 rsv_10 : 4; /* [7:4] */ + u32 glb_api_per_pf : 4; /* [11:8] */ + u32 rsv_11 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_res_per_func_u; + +/* Define the union csr_api_gap_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_gap : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_gap_ctl_u; + +/* Define the union csr_dir_wqe_gap_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_gap : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dir_wqe_gap_ctl_u; + +/* Define the union csr_dir_wqe_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_aging_period : 20; /* [19:0] */ + u32 rsv_14 : 4; /* [23:20] */ + u32 glb_dwqe_tx_req_fifo_threshold : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dir_wqe_timeout_u; + +/* Define the union csr_glb_sw_srch_tcam_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_sw_srch_tcam_key : 26; /* [25:0] */ + u32 rsv_15 : 5; /* [30:26] */ + u32 glb_sw_srch_tcam_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_sw_srch_tcam_ctl_u; + +/* Define the union csr_glb_sw_srch_tcam_rslt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_sw_srch_tcam_data : 13; /* [12:0] */ + u32 rsv_16 : 18; /* [30:13] */ + u32 glb_sw_srch_tcam_hit : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_sw_srch_tcam_rslt_u; + +/* Define the union csr_glb_apb_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_apb_timer_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_apb_timer_cfg_u; + +/* Define the union csr_glb_srv_type_for_ddb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_srv_type_for_ddb0 : 5; /* [4:0] */ + u32 rsv_17 : 3; /* [7:5] */ + u32 glb_srv_type_for_ddb1 : 5; /* [12:8] */ + u32 rsv_18 : 3; /* [15:13] */ + u32 glb_srv_type_for_ddb2 : 5; /* [20:16] */ + u32 rsv_19 : 3; /* [23:21] */ + u32 glb_srv_type_for_ddb3 : 5; /* [28:24] */ + u32 rsv_20 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_srv_type_for_ddb_u; + +/* Define the union csr_glb_nl2n_inline_otd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_otd : 5; /* [4:0] */ + u32 rsv_21 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_nl2n_inline_otd_u; + +/* Define the union csr_glb_nl2n_inline_num_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_num_th : 6; /* [5:0] */ + u32 rsv_22 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_nl2n_inline_num_th_u; + +/* Define the union csr_glb_tilep_poll_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_acc_poll_gap : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_tilep_poll_gap_u; + +/* Define the union csr_glb_mb_tx_legal_chk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_legal_chk : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_legal_chk_u; + +/* Define the union csr_glb_cpl_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_th_rsv : 1; /* [0] */ + u32 glb_cpl_data_rsv : 1; /* [1] */ + u32 glb_cpl_ur_st : 3; /* [4:2] */ + u32 rsv_25 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_ctrl_u; + +/* Define the union csr_ucpu_mb_tx_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_mb_dest_func : 13; /* [12:0] */ + u32 ucpu_mb_dest_port : 3; /* [15:13] */ + u32 ucpu_mb_dest_aeqn : 2; /* [17:16] */ + u32 ucpu_mb_tx_sts : 2; /* [19:18] */ + u32 ucpu_mb_tx_size : 5; /* [24:20] */ + u32 rsv_26 : 6; /* [30:25] */ + u32 ucpu_mb_tx_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_mb_tx_ctl_u; + +/* Define the union csr_ucpu_allow_vf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_allow_vf_cfg : 1; /* [0] */ + u32 af_mb_tsk_csr_wr_right : 1; /* [1] */ + u32 pf_mb_tsk_csr_wr_right : 1; /* [2] */ + u32 rsv_27 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_allow_vf_cfg_u; + +/* Define the union csr_ucpu_mb_tx_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_mb_tx_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_mb_tx_data_u; + +/* Define the union csr_pf_eprom_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_eprom_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_eprom_offset_u; + +/* Define the union csr_cpi_tbl_indir_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_tbl_indir_addr : 13; /* [12:0] */ + u32 rsv_28 : 11; /* [23:13] */ + u32 glb_tbl_indir_tab : 4; /* [27:24] */ + u32 glb_tbl_indir_stat : 2; /* [29:28] */ + u32 glb_tbl_indir_mode : 1; /* [30] */ + u32 glb_tbl_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tbl_indir_ctrl0_u; + +/* Define the union csr_cpi_tbl_indir_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_tbl_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tbl_indir_ctrl1_u; + +/* Define the union csr_cpi_tbl_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_tbl_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tbl_indir_data_u; + +/* Define the union csr_cpi_indir_path_ring_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_indir_path_addr : 27; /* [26:0] */ + u32 pcie_indir_path_sts : 1; /* [27] */ + u32 pcie_indir_path_op : 1; /* [28] */ + u32 rsv_29 : 1; /* [29] */ + u32 pcie_indir_path_size : 1; /* [30] */ + u32 pcie_indir_path_issue : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_indir_path_ring_ctrl_u; + +/* Define the union csr_cpi_indir_path_ring_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_indir_path_dat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_indir_path_ring_dat0_u; + +/* Define the union csr_cpi_indir_path_ring_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_indir_path_dat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_indir_path_ring_dat1_u; + +/* Define the union csr_cpi_ram_init_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ram_ini_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_init_req_u; + +/* Define the union csr_cpi_ram_init_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ram_ini_sts0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_init_sts0_u; + +/* Define the union csr_cpi_ram_init_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ram_ini_sts1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_init_sts1_u; + +/* Define the union csr_cpi_mb_tx_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_gap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_mb_tx_gap_u; + +/* Define the union csr_glb_cpi_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_30 : 31; /* [30:0] */ + u32 glb_cpi_ecc_bypass : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_ram_ecc_bypass_u; + +/* Define the union csr_glb_mb_shp_host0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host0 : 6; /* [5:0] */ + u32 rsv_31 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host0 : 6; /* [13:8] */ + u32 rsv_32 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host0 : 7; /* [22:16] */ + u32 rsv_33 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host0 : 7; /* [30:24] */ + u32 rsv_34 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host0_u; + +/* Define the union csr_glb_mb_shp_host1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host1 : 6; /* [5:0] */ + u32 rsv_35 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host1 : 6; /* [13:8] */ + u32 rsv_36 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host1 : 7; /* [22:16] */ + u32 rsv_37 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host1 : 7; /* [30:24] */ + u32 rsv_38 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host1_u; + +/* Define the union csr_glb_mb_shp_host2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host2 : 6; /* [5:0] */ + u32 rsv_39 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host2 : 6; /* [13:8] */ + u32 rsv_40 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host2 : 7; /* [22:16] */ + u32 rsv_41 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host2 : 7; /* [30:24] */ + u32 rsv_42 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host2_u; + +/* Define the union csr_glb_mb_shp_host3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host3 : 6; /* [5:0] */ + u32 rsv_43 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host3 : 6; /* [13:8] */ + u32 rsv_44 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host3 : 7; /* [22:16] */ + u32 rsv_45 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host3 : 7; /* [30:24] */ + u32 rsv_46 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host3_u; + +/* Define the union csr_glb_mb_shp_host4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host4 : 6; /* [5:0] */ + u32 rsv_47 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host4 : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host4 : 7; /* [22:16] */ + u32 rsv_49 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host4 : 7; /* [30:24] */ + u32 rsv_50 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host4_u; + +/* Define the union csr_glb_mb_shp_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_inc_unit : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_unit_u; + +/* Define the union csr_glb_mb_right_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_ppf_x86_to_spu_dis : 1; /* [0] */ + u32 mb_src_func_dis_mode : 1; /* [1] */ + u32 rsv_52 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_right_cfg_u; + +/* Define the union csr_glb_csr_acc_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_csr_acc_timeout : 16; /* [15:0] */ + u32 glb_dbl_acc_timeout : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_csr_acc_timeout_u; + +/* Define the union csr_glb_cpi_rs_nd_pe_crdit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_53 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_rs_nd_pe_crdit_u; + +/* Define the union csr_glb_np_ctx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_np_cpl_ur_st : 3; /* [2:0] */ + u32 rsv_54 : 5; /* [7:3] */ + u32 glb_np_cpl_data_rsv : 1; /* [8] */ + u32 rsv_55 : 7; /* [15:9] */ + u32 glb_np_ctx_aging_period : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_np_ctx_cfg_u; + +/* Define the union csr_glb_ipush_fifo_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_csr_fifo_bp_off : 7; /* [6:0] */ + u32 rsv_56 : 1; /* [7] */ + u32 glb_csr_fifo_bp_on : 7; /* [14:8] */ + u32 rsv_57 : 1; /* [15] */ + u32 glb_dbl_fifo_bp_off : 7; /* [22:16] */ + u32 rsv_58 : 1; /* [23] */ + u32 glb_dbl_fifo_bp_on : 7; /* [30:24] */ + u32 rsv_59 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ipush_fifo_bp_u; + +/* Define the union csr_glb_ipush_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ictl_ipush_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ipush_fifo_sts_u; + +/* Define the union csr_glb_cpath_int_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpath_int_bitmap : 16; /* [15:0] */ + u32 rsv_60 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpath_int_bitmap_u; + +/* Define the union csr_glb_dwqe_buf_vld_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_buf_vld_num : 7; /* [6:0] */ + u32 rsv_61 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_buf_vld_num_u; + +/* Define the union csr_dir_wqe_byte_order_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dirwqe_db_byte_order_switch_en : 1; /* [0] */ + u32 rsv_62 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dir_wqe_byte_order_en_u; + +/* Define the union csr_fake_vfid_cal_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fake_vfid_start_bit : 4; /* [3:0] */ + u32 fake_vfid_end_bit : 4; /* [7:4] */ + u32 fake_vfid_page_bit : 4; /* [11:8] */ + u32 rsv_63 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fake_vfid_cal_cfg_u; + +/* Define the union csr_fake_vfid_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fake_vfid_add_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fake_vfid_enable_u; + +/* Define the union csr_dbl_fake_vfid_cbit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbl_fake_vfid_cbit_en : 1; /* [0] */ + u32 rsv_64 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbl_fake_vfid_cbit_en_u; + +/* Define the union csr_dbl_srv_type_illegal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbl_srv_type_illegal : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbl_srv_type_illegal_u; + +/* Define the union csr_glb_dwqe_lb_hash_acc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_dst_cid : 20; /* [19:0] */ + u32 rsv_65 : 11; /* [30:20] */ + u32 glb_dwqe_hash_based_ctxt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_lb_hash_acc_u; + +/* Define the union csr_glb_dwqe_lb_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_lbf_mode : 2; /* [1:0] */ + u32 rsv_66 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_lb_mod_u; + +/* Define the union csr_glb_dwqe_smf_pg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_smf_pg_cfg : 4; /* [3:0] */ + u32 rsv_67 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_smf_pg_u; + +/* Define the union csr_virtio_byte_order_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_byte_order_disable : 1; /* [0] */ + u32 rsv_68 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_byte_order_dis_u; + +/* Define the union csr_nvme_rsv_addr_range_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_rsv_start_addr : 12; /* [11:0] */ + u32 nvme_rsv_range_en : 1; /* [12] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_rsv_addr_range_u; + +/* Define the union csr_virtio_lb_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_lbf_mode : 2; /* [1:0] */ + u32 rsv_70 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_lb_mod_u; + +/* Define the union csr_virtio_otd_max_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_otd_max_th : 7; /* [6:0] */ + u32 rsv_71 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_otd_max_th_u; + +/* Define the union csr_glb_flxq_map_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_flxq_map_en : 1; /* [0] */ + u32 rsv_72 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_flxq_map_en_u; + +/* Define the union csr_glb_aeq_idx_for_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_aeq_idx_for_vf : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_aeq_idx_for_vf_u; + +/* Define the union csr_ptp_ts_updt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_ns_delta : 30; /* [29:0] */ + u32 rsv_74 : 1; /* [30] */ + u32 glb_ptp_ns_delta_op : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_updt_cfg_u; + +/* Define the union csr_ptp_ts_inc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_inc_frac : 16; /* [15:0] */ + u32 glb_ptp_inc_intg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_inc_cfg_u; + +/* Define the union csr_ptp_ts_calibration_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_calb_value : 16; /* [15:0] */ + u32 rsv_75 : 15; /* [30:16] */ + u32 glb_ptp_calb_sign : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_calibration_u; + +/* Define the union csr_ptp_ts_wr_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_sec_h : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_wr_data0_u; + +/* Define the union csr_ptp_ts_wr_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_wr_data1_u; + +/* Define the union csr_ptp_ts_wr_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_ns : 30; /* [29:0] */ + u32 rsv_77 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_wr_data2_u; + +/* Define the union csr_ptp_ts_rd_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_rd_sec_h : 16; /* [15:0] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_rd_data0_u; + +/* Define the union csr_ptp_ts_rd_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_rd_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_rd_data1_u; + +/* Define the union csr_ptp_ts_rd_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_rd_ns : 30; /* [29:0] */ + u32 rsv_79 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_rd_data2_u; + +/* Define the union csr_ptp_ts_up_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_up_en : 1; /* [0] */ + u32 glb_ptp_rd_up_en : 1; /* [1] */ + u32 glb_ptp_cfg_up_en : 1; /* [2] */ + u32 glb_ptp_delta_up_en : 1; /* [3] */ + u32 rsv_80 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_up_en_u; + +/* Define the union csr_ptp_dstr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_dstr_gap : 16; /* [15:0] */ + u32 rsv_81 : 15; /* [30:16] */ + u32 glb_ptp_dstr_cmp_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_dstr_cfg_u; + +/* Define the union csr_non_ptp_ts_inc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_inc_frac : 16; /* [15:0] */ + u32 glb_non_ptp_inc_intg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_inc_cfg_u; + +/* Define the union csr_non_ptp_ts_calibration_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_calb_value : 16; /* [15:0] */ + u32 rsv_82 : 15; /* [30:16] */ + u32 glb_non_ptp_calb_sign : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_calibration_u; + +/* Define the union csr_non_ptp_ts_wr_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_sec_h : 16; /* [15:0] */ + u32 rsv_83 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_wr_data0_u; + +/* Define the union csr_non_ptp_ts_wr_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_wr_data1_u; + +/* Define the union csr_non_ptp_ts_wr_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_ns : 30; /* [29:0] */ + u32 rsv_84 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_wr_data2_u; + +/* Define the union csr_non_ptp_ts_rd_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_rd_sec_h : 16; /* [15:0] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_rd_data0_u; + +/* Define the union csr_non_ptp_ts_rd_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_rd_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_rd_data1_u; + +/* Define the union csr_non_ptp_ts_rd_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_rd_ns : 30; /* [29:0] */ + u32 rsv_86 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_rd_data2_u; + +/* Define the union csr_non_ptp_ts_up_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_up_en : 1; /* [0] */ + u32 glb_non_ptp_rd_up_en : 1; /* [1] */ + u32 glb_non_ptp_cfg_up_en : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_up_en_u; + +/* Define the union csr_non_ptp_dstr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_dstr_gap : 16; /* [15:0] */ + u32 rsv_88 : 15; /* [30:16] */ + u32 glb_non_ptp_dstr_cmp_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_dstr_cfg_u; + +/* Define the union csr_glb_vf_offset_for_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_vf_offset_for_pf : 12; /* [11:0] */ + u32 rsv_89 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_vf_offset_for_pf_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_glb_cpi_version_csr_u glb_cpi_version_csr; /* 0 */ + volatile csr_glb_x86_req_crd_flush_ctl_u glb_x86_req_crd_flush_ctl; /* 4 */ + volatile csr_glb_x86_cpl_crd_flush_ctl_u glb_x86_cpl_crd_flush_ctl; /* 8 */ + volatile csr_glb_spu_x86_acc_weight_u glb_spu_x86_acc_weight; /* C */ + volatile csr_glb_port_mode_u glb_port_mode; /* 10 */ + volatile csr_glb_spu_req_crd_flush_ctl_u glb_spu_req_crd_flush_ctl; /* 14 */ + volatile csr_glb_spu_cpl_crd_flush_ctl_u glb_spu_cpl_crd_flush_ctl; /* 18 */ + volatile csr_glb_res_per_func_u glb_res_per_func; /* 50 */ + volatile csr_api_gap_ctl_u api_gap_ctl; /* 54 */ + volatile csr_dir_wqe_gap_ctl_u dir_wqe_gap_ctl; /* 58 */ + volatile csr_dir_wqe_timeout_u dir_wqe_timeout; /* 5C */ + volatile csr_glb_sw_srch_tcam_ctl_u glb_sw_srch_tcam_ctl; /* 80 */ + volatile csr_glb_sw_srch_tcam_rslt_u glb_sw_srch_tcam_rslt; /* 84 */ + volatile csr_glb_apb_timer_cfg_u glb_apb_timer_cfg; /* 88 */ + volatile csr_glb_srv_type_for_ddb_u glb_srv_type_for_ddb; /* 8C */ + volatile csr_glb_nl2n_inline_otd_u glb_nl2n_inline_otd; /* 90 */ + volatile csr_glb_nl2n_inline_num_th_u glb_nl2n_inline_num_th; /* 94 */ + volatile csr_glb_tilep_poll_gap_u glb_tilep_poll_gap; /* 98 */ + volatile csr_glb_mb_tx_legal_chk_u glb_mb_tx_legal_chk; /* A0 */ + volatile csr_glb_cpl_ctrl_u glb_cpl_ctrl; /* A8 */ + volatile csr_ucpu_mb_tx_ctl_u ucpu_mb_tx_ctl; /* B0 */ + volatile csr_ucpu_allow_vf_cfg_u ucpu_allow_vf_cfg; /* BC */ + volatile csr_ucpu_mb_tx_data_u ucpu_mb_tx_data[16]; /* C0 */ + volatile csr_pf_eprom_offset_u pf_eprom_offset[32]; /* 100 */ + volatile csr_cpi_tbl_indir_ctrl0_u cpi_tbl_indir_ctrl0; /* 200 */ + volatile csr_cpi_tbl_indir_ctrl1_u cpi_tbl_indir_ctrl1; /* 204 */ + volatile csr_cpi_tbl_indir_data_u cpi_tbl_indir_data[8]; /* 210 */ + volatile csr_cpi_indir_path_ring_ctrl_u cpi_indir_path_ring_ctrl; /* 230 */ + volatile csr_cpi_indir_path_ring_dat0_u cpi_indir_path_ring_dat0; /* 234 */ + volatile csr_cpi_indir_path_ring_dat1_u cpi_indir_path_ring_dat1; /* 238 */ + volatile csr_cpi_ram_init_req_u cpi_ram_init_req; /* 240 */ + volatile csr_cpi_ram_init_sts0_u cpi_ram_init_sts0; /* 250 */ + volatile csr_cpi_ram_init_sts1_u cpi_ram_init_sts1; /* 254 */ + volatile csr_cpi_mb_tx_gap_u cpi_mb_tx_gap; /* 260 */ + volatile csr_glb_cpi_ram_ecc_bypass_u glb_cpi_ram_ecc_bypass; /* 280 */ + volatile csr_glb_mb_shp_host0_u glb_mb_shp_host0; /* 290 */ + volatile csr_glb_mb_shp_host1_u glb_mb_shp_host1; /* 294 */ + volatile csr_glb_mb_shp_host2_u glb_mb_shp_host2; /* 298 */ + volatile csr_glb_mb_shp_host3_u glb_mb_shp_host3; /* 29C */ + volatile csr_glb_mb_shp_host4_u glb_mb_shp_host4; /* 2A0 */ + volatile csr_glb_mb_shp_unit_u glb_mb_shp_unit; /* 2A4 */ + volatile csr_glb_mb_right_cfg_u glb_mb_right_cfg; /* 2A8 */ + volatile csr_glb_csr_acc_timeout_u glb_csr_acc_timeout; /* 2B0 */ + volatile csr_glb_cpi_rs_nd_pe_crdit_u glb_cpi_rs_nd_pe_crdit; /* 2B8 */ + volatile csr_glb_np_ctx_cfg_u glb_np_ctx_cfg; /* 2F0 */ + volatile csr_glb_ipush_fifo_bp_u glb_ipush_fifo_bp; /* 318 */ + volatile csr_glb_ipush_fifo_sts_u glb_ipush_fifo_sts; /* 31C */ + volatile csr_glb_cpath_int_bitmap_u glb_cpath_int_bitmap; /* 340 */ + volatile csr_glb_dwqe_buf_vld_num_u glb_dwqe_buf_vld_num; /* 344 */ + volatile csr_dir_wqe_byte_order_en_u dir_wqe_byte_order_en; /* 354 */ + volatile csr_fake_vfid_cal_cfg_u fake_vfid_cal_cfg; /* 360 */ + volatile csr_fake_vfid_enable_u fake_vfid_enable; /* 364 */ + volatile csr_dbl_fake_vfid_cbit_en_u dbl_fake_vfid_cbit_en; /* 368 */ + volatile csr_dbl_srv_type_illegal_u dbl_srv_type_illegal; /* 36C */ + volatile csr_glb_dwqe_lb_hash_acc_u glb_dwqe_lb_hash_acc; /* 370 */ + volatile csr_glb_dwqe_lb_mod_u glb_dwqe_lb_mod; /* 374 */ + volatile csr_glb_dwqe_smf_pg_u glb_dwqe_smf_pg; /* 378 */ + volatile csr_virtio_byte_order_dis_u virtio_byte_order_dis; /* 380 */ + volatile csr_nvme_rsv_addr_range_u nvme_rsv_addr_range; /* 384 */ + volatile csr_virtio_lb_mod_u virtio_lb_mod; /* 388 */ + volatile csr_virtio_otd_max_th_u virtio_otd_max_th; /* 38C */ + volatile csr_glb_flxq_map_en_u glb_flxq_map_en; /* 390 */ + volatile csr_glb_aeq_idx_for_vf_u glb_aeq_idx_for_vf; /* 3A0 */ + volatile csr_ptp_ts_updt_cfg_u ptp_ts_updt_cfg; /* 3AC */ + volatile csr_ptp_ts_inc_cfg_u ptp_ts_inc_cfg; /* 3B0 */ + volatile csr_ptp_ts_calibration_u ptp_ts_calibration; /* 3B4 */ + volatile csr_ptp_ts_wr_data0_u ptp_ts_wr_data0; /* 3B8 */ + volatile csr_ptp_ts_wr_data1_u ptp_ts_wr_data1; /* 3BC */ + volatile csr_ptp_ts_wr_data2_u ptp_ts_wr_data2; /* 3C0 */ + volatile csr_ptp_ts_rd_data0_u ptp_ts_rd_data0; /* 3C4 */ + volatile csr_ptp_ts_rd_data1_u ptp_ts_rd_data1; /* 3C8 */ + volatile csr_ptp_ts_rd_data2_u ptp_ts_rd_data2; /* 3CC */ + volatile csr_ptp_ts_up_en_u ptp_ts_up_en; /* 3D0 */ + volatile csr_ptp_dstr_cfg_u ptp_dstr_cfg; /* 3D4 */ + volatile csr_non_ptp_ts_inc_cfg_u non_ptp_ts_inc_cfg; /* 3D8 */ + volatile csr_non_ptp_ts_calibration_u non_ptp_ts_calibration; /* 3DC */ + volatile csr_non_ptp_ts_wr_data0_u non_ptp_ts_wr_data0; /* 3E0 */ + volatile csr_non_ptp_ts_wr_data1_u non_ptp_ts_wr_data1; /* 3E4 */ + volatile csr_non_ptp_ts_wr_data2_u non_ptp_ts_wr_data2; /* 3E8 */ + volatile csr_non_ptp_ts_rd_data0_u non_ptp_ts_rd_data0; /* 3EC */ + volatile csr_non_ptp_ts_rd_data1_u non_ptp_ts_rd_data1; /* 3F0 */ + volatile csr_non_ptp_ts_rd_data2_u non_ptp_ts_rd_data2; /* 3F4 */ + volatile csr_non_ptp_ts_up_en_u non_ptp_ts_up_en; /* 3F8 */ + volatile csr_non_ptp_dstr_cfg_u non_ptp_dstr_cfg; /* 3FC */ + volatile csr_glb_vf_offset_for_pf_u glb_vf_offset_for_pf[33]; /* 400 */ +} S_glb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module glb_csr */ +extern volatile S_glb_csr_REGS_TYPE *gopglb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetGLB_CPI_VERSION_CSR_glb_cpi_version_csr(unsigned int uglb_cpi_version_csr); +int iSetGLB_X86_REQ_CRD_FLUSH_CTL_glb_x86_req_crd_flush_max(unsigned int uglb_x86_req_crd_flush_max); +int iSetGLB_X86_REQ_CRD_FLUSH_CTL_glb_x86_req_crd_flush_en(unsigned int uglb_x86_req_crd_flush_en); +int iSetGLB_X86_CPL_CRD_FLUSH_CTL_glb_x86_cpl_crd_flush_max(unsigned int uglb_x86_cpl_crd_flush_max); +int iSetGLB_X86_CPL_CRD_FLUSH_CTL_glb_x86_cpl_crd_flush_en(unsigned int uglb_x86_cpl_crd_flush_en); +int iSetGLB_SPU_X86_ACC_WEIGHT_glb_req_acc_weight_port(unsigned int uglb_req_acc_weight_port); +int iSetGLB_SPU_X86_ACC_WEIGHT_glb_cpl_acc_weight_port(unsigned int uglb_cpl_acc_weight_port); +int iSetGLB_PORT_MODE_glb_port_mode_cfg(unsigned int uglb_port_mode_cfg); +int iSetGLB_SPU_REQ_CRD_FLUSH_CTL_glb_spu_req_crd_flush_max(unsigned int uglb_spu_req_crd_flush_max); +int iSetGLB_SPU_REQ_CRD_FLUSH_CTL_glb_spu_req_crd_flush_en(unsigned int uglb_spu_req_crd_flush_en); +int iSetGLB_SPU_CPL_CRD_FLUSH_CTL_glb_spu_cpl_crd_flush_max(unsigned int uglb_spu_cpl_crd_flush_max); +int iSetGLB_SPU_CPL_CRD_FLUSH_CTL_glb_spu_cpl_crd_flush_en(unsigned int uglb_spu_cpl_crd_flush_en); +int iSetGLB_RES_PER_FUNC_glb_aeq_per_pf(unsigned int uglb_aeq_per_pf); +int iSetGLB_RES_PER_FUNC_glb_aeq_per_vf(unsigned int uglb_aeq_per_vf); +int iSetGLB_RES_PER_FUNC_glb_api_per_pf(unsigned int uglb_api_per_pf); +int iSetAPI_GAP_CTL_glb_api_gap(unsigned int uglb_api_gap); +int iSetDIR_WQE_GAP_CTL_glb_dwqe_gap(unsigned int uglb_dwqe_gap); +int iSetDIR_WQE_TIMEOUT_glb_dwqe_aging_period(unsigned int uglb_dwqe_aging_period); +int iSetDIR_WQE_TIMEOUT_glb_dwqe_tx_req_fifo_threshold(unsigned int uglb_dwqe_tx_req_fifo_threshold); +int iSetGLB_SW_SRCH_TCAM_CTL_glb_sw_srch_tcam_key(unsigned int uglb_sw_srch_tcam_key); +int iSetGLB_SW_SRCH_TCAM_CTL_glb_sw_srch_tcam_vld(unsigned int uglb_sw_srch_tcam_vld); +int iSetGLB_SW_SRCH_TCAM_RSLT_glb_sw_srch_tcam_data(unsigned int uglb_sw_srch_tcam_data); +int iSetGLB_SW_SRCH_TCAM_RSLT_glb_sw_srch_tcam_hit(unsigned int uglb_sw_srch_tcam_hit); +int iSetGLB_APB_TIMER_CFG_glb_apb_timer_cfg(unsigned int uglb_apb_timer_cfg); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb0(unsigned int uglb_srv_type_for_ddb0); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb1(unsigned int uglb_srv_type_for_ddb1); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb2(unsigned int uglb_srv_type_for_ddb2); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb3(unsigned int uglb_srv_type_for_ddb3); +int iSetGLB_NL2N_INLINE_OTD_nl2_otd(unsigned int unl2_otd); +int iSetGLB_NL2N_INLINE_NUM_TH_nl2_cmd_num_th(unsigned int unl2_cmd_num_th); +int iSetGLB_TILEP_POLL_GAP_tilep_indir_acc_poll_gap(unsigned int utilep_indir_acc_poll_gap); +int iSetGLB_MB_TX_LEGAL_CHK_glb_mb_tx_legal_chk(unsigned int uglb_mb_tx_legal_chk); +int iSetGLB_CPL_CTRL_glb_cpl_th_rsv(unsigned int uglb_cpl_th_rsv); +int iSetGLB_CPL_CTRL_glb_cpl_data_rsv(unsigned int uglb_cpl_data_rsv); +int iSetGLB_CPL_CTRL_glb_cpl_ur_st(unsigned int uglb_cpl_ur_st); +int iSetUCPU_MB_TX_CTL_ucpu_mb_dest_func(unsigned int uucpu_mb_dest_func); +int iSetUCPU_MB_TX_CTL_ucpu_mb_dest_port(unsigned int uucpu_mb_dest_port); +int iSetUCPU_MB_TX_CTL_ucpu_mb_dest_aeqn(unsigned int uucpu_mb_dest_aeqn); +int iSetUCPU_MB_TX_CTL_ucpu_mb_tx_sts(unsigned int uucpu_mb_tx_sts); +int iSetUCPU_MB_TX_CTL_ucpu_mb_tx_size(unsigned int uucpu_mb_tx_size); +int iSetUCPU_MB_TX_CTL_ucpu_mb_tx_req(unsigned int uucpu_mb_tx_req); +int iSetUCPU_ALLOW_VF_CFG_ucpu_allow_vf_cfg(unsigned int uucpu_allow_vf_cfg); +int iSetUCPU_ALLOW_VF_CFG_af_mb_tsk_csr_wr_right(unsigned int uaf_mb_tsk_csr_wr_right); +int iSetUCPU_ALLOW_VF_CFG_pf_mb_tsk_csr_wr_right(unsigned int upf_mb_tsk_csr_wr_right); +int iSetUCPU_MB_TX_DATA_ucpu_mb_tx_data(unsigned int uucpu_mb_tx_data); +int iSetPF_EPROM_OFFSET_pf_eprom_offset(unsigned int upf_eprom_offset); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_addr(unsigned int uglb_tbl_indir_addr); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_tab(unsigned int uglb_tbl_indir_tab); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_stat(unsigned int uglb_tbl_indir_stat); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_mode(unsigned int uglb_tbl_indir_mode); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_vld(unsigned int uglb_tbl_indir_vld); +int iSetCPI_TBL_INDIR_CTRL1_glb_tbl_indir_timeout(unsigned int uglb_tbl_indir_timeout); +int iSetCPI_TBL_INDIR_DATA_glb_tbl_indir_data(unsigned int uglb_tbl_indir_data); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_addr(unsigned int upcie_indir_path_addr); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_sts(unsigned int upcie_indir_path_sts); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_op(unsigned int upcie_indir_path_op); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_size(unsigned int upcie_indir_path_size); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_issue(unsigned int upcie_indir_path_issue); +int iSetCPI_INDIR_PATH_RING_DAT0_pcie_indir_path_dat0(unsigned int upcie_indir_path_dat0); +int iSetCPI_INDIR_PATH_RING_DAT1_pcie_indir_path_dat1(unsigned int upcie_indir_path_dat1); +int iSetCPI_RAM_INIT_REQ_glb_cpi_ram_ini_req(unsigned int uglb_cpi_ram_ini_req); +int iSetCPI_RAM_INIT_STS0_glb_cpi_ram_ini_sts0(unsigned int uglb_cpi_ram_ini_sts0); +int iSetCPI_RAM_INIT_STS1_glb_cpi_ram_ini_sts1(unsigned int uglb_cpi_ram_ini_sts1); +int iSetCPI_MB_TX_GAP_glb_mb_tx_gap(unsigned int uglb_mb_tx_gap); +int iSetGLB_CPI_RAM_ECC_BYPASS_glb_cpi_ecc_bypass(unsigned int uglb_cpi_ecc_bypass); +int iSetGLB_MB_SHP_HOST0_mb_crdt_limit_for_pf_host0(unsigned int umb_crdt_limit_for_pf_host0); +int iSetGLB_MB_SHP_HOST0_mb_crdt_limit_for_vf_host0(unsigned int umb_crdt_limit_for_vf_host0); +int iSetGLB_MB_SHP_HOST0_mb_crdt_inc_timer_pf_host0(unsigned int umb_crdt_inc_timer_pf_host0); +int iSetGLB_MB_SHP_HOST0_mb_crdt_inc_timer_vf_host0(unsigned int umb_crdt_inc_timer_vf_host0); +int iSetGLB_MB_SHP_HOST1_mb_crdt_limit_for_pf_host1(unsigned int umb_crdt_limit_for_pf_host1); +int iSetGLB_MB_SHP_HOST1_mb_crdt_limit_for_vf_host1(unsigned int umb_crdt_limit_for_vf_host1); +int iSetGLB_MB_SHP_HOST1_mb_crdt_inc_timer_pf_host1(unsigned int umb_crdt_inc_timer_pf_host1); +int iSetGLB_MB_SHP_HOST1_mb_crdt_inc_timer_vf_host1(unsigned int umb_crdt_inc_timer_vf_host1); +int iSetGLB_MB_SHP_HOST2_mb_crdt_limit_for_pf_host2(unsigned int umb_crdt_limit_for_pf_host2); +int iSetGLB_MB_SHP_HOST2_mb_crdt_limit_for_vf_host2(unsigned int umb_crdt_limit_for_vf_host2); +int iSetGLB_MB_SHP_HOST2_mb_crdt_inc_timer_pf_host2(unsigned int umb_crdt_inc_timer_pf_host2); +int iSetGLB_MB_SHP_HOST2_mb_crdt_inc_timer_vf_host2(unsigned int umb_crdt_inc_timer_vf_host2); +int iSetGLB_MB_SHP_HOST3_mb_crdt_limit_for_pf_host3(unsigned int umb_crdt_limit_for_pf_host3); +int iSetGLB_MB_SHP_HOST3_mb_crdt_limit_for_vf_host3(unsigned int umb_crdt_limit_for_vf_host3); +int iSetGLB_MB_SHP_HOST3_mb_crdt_inc_timer_pf_host3(unsigned int umb_crdt_inc_timer_pf_host3); +int iSetGLB_MB_SHP_HOST3_mb_crdt_inc_timer_vf_host3(unsigned int umb_crdt_inc_timer_vf_host3); +int iSetGLB_MB_SHP_HOST4_mb_crdt_limit_for_pf_host4(unsigned int umb_crdt_limit_for_pf_host4); +int iSetGLB_MB_SHP_HOST4_mb_crdt_limit_for_vf_host4(unsigned int umb_crdt_limit_for_vf_host4); +int iSetGLB_MB_SHP_HOST4_mb_crdt_inc_timer_pf_host4(unsigned int umb_crdt_inc_timer_pf_host4); +int iSetGLB_MB_SHP_HOST4_mb_crdt_inc_timer_vf_host4(unsigned int umb_crdt_inc_timer_vf_host4); +int iSetGLB_MB_SHP_UNIT_mb_crdt_inc_unit(unsigned int umb_crdt_inc_unit); +int iSetGLB_MB_RIGHT_CFG_mb_ppf_x86_to_spu_dis(unsigned int umb_ppf_x86_to_spu_dis); +int iSetGLB_MB_RIGHT_CFG_mb_src_func_dis_mode(unsigned int umb_src_func_dis_mode); +int iSetGLB_CSR_ACC_TIMEOUT_glb_csr_acc_timeout(unsigned int uglb_csr_acc_timeout); +int iSetGLB_CSR_ACC_TIMEOUT_glb_dbl_acc_timeout(unsigned int uglb_dbl_acc_timeout); +int iSetGLB_CPI_RS_ND_PE_CRDIT_glb_cpi_rs_nd_pe_crdt_sta(unsigned int uglb_cpi_rs_nd_pe_crdt_sta); +int iSetGLB_NP_CTX_CFG_glb_np_cpl_ur_st(unsigned int uglb_np_cpl_ur_st); +int iSetGLB_NP_CTX_CFG_glb_np_cpl_data_rsv(unsigned int uglb_np_cpl_data_rsv); +int iSetGLB_NP_CTX_CFG_glb_np_ctx_aging_period(unsigned int uglb_np_ctx_aging_period); +int iSetGLB_IPUSH_FIFO_BP_glb_csr_fifo_bp_off(unsigned int uglb_csr_fifo_bp_off); +int iSetGLB_IPUSH_FIFO_BP_glb_csr_fifo_bp_on(unsigned int uglb_csr_fifo_bp_on); +int iSetGLB_IPUSH_FIFO_BP_glb_dbl_fifo_bp_off(unsigned int uglb_dbl_fifo_bp_off); +int iSetGLB_IPUSH_FIFO_BP_glb_dbl_fifo_bp_on(unsigned int uglb_dbl_fifo_bp_on); +int iSetGLB_IPUSH_FIFO_STS_glb_ictl_ipush_fifo_sts(unsigned int uglb_ictl_ipush_fifo_sts); +int iSetGLB_CPATH_INT_BITMAP_glb_cpath_int_bitmap(unsigned int uglb_cpath_int_bitmap); +int iSetGLB_DWQE_BUF_VLD_NUM_glb_dwqe_buf_vld_num(unsigned int uglb_dwqe_buf_vld_num); +int iSetDIR_WQE_BYTE_ORDER_EN_dirwqe_db_byte_order_switch_en(unsigned int udirwqe_db_byte_order_switch_en); +int iSetFAKE_VFID_CAL_CFG_fake_vfid_start_bit(unsigned int ufake_vfid_start_bit); +int iSetFAKE_VFID_CAL_CFG_fake_vfid_end_bit(unsigned int ufake_vfid_end_bit); +int iSetFAKE_VFID_CAL_CFG_fake_vfid_page_bit(unsigned int ufake_vfid_page_bit); +int iSetFAKE_VFID_ENABLE_fake_vfid_add_en(unsigned int ufake_vfid_add_en); +int iSetDBL_FAKE_VFID_CBIT_EN_dbl_fake_vfid_cbit_en(unsigned int udbl_fake_vfid_cbit_en); +int iSetDBL_SRV_TYPE_ILLEGAL_dbl_srv_type_illegal(unsigned int udbl_srv_type_illegal); +int iSetGLB_DWQE_LB_HASH_ACC_glb_dwqe_dst_cid(unsigned int uglb_dwqe_dst_cid); +int iSetGLB_DWQE_LB_HASH_ACC_glb_dwqe_hash_based_ctxt(unsigned int uglb_dwqe_hash_based_ctxt); +int iSetGLB_DWQE_LB_MOD_glb_dwqe_lbf_mode(unsigned int uglb_dwqe_lbf_mode); +int iSetGLB_DWQE_SMF_PG_glb_dwqe_smf_pg_cfg(unsigned int uglb_dwqe_smf_pg_cfg); +int iSetVIRTIO_BYTE_ORDER_DIS_virtio_byte_order_disable(unsigned int uvirtio_byte_order_disable); +int iSetNVME_RSV_ADDR_RANGE_nvme_rsv_start_addr(unsigned int unvme_rsv_start_addr); +int iSetNVME_RSV_ADDR_RANGE_nvme_rsv_range_en(unsigned int unvme_rsv_range_en); +int iSetVIRTIO_LB_MOD_virtio_lbf_mode(unsigned int uvirtio_lbf_mode); +int iSetVIRTIO_OTD_MAX_TH_virtio_otd_max_th(unsigned int uvirtio_otd_max_th); +int iSetGLB_FLXQ_MAP_EN_glb_flxq_map_en(unsigned int uglb_flxq_map_en); +int iSetGLB_AEQ_IDX_FOR_VF_glb_aeq_idx_for_vf(unsigned int uglb_aeq_idx_for_vf); +int iSetPTP_TS_UPDT_CFG_glb_ptp_ns_delta(unsigned int uglb_ptp_ns_delta); +int iSetPTP_TS_UPDT_CFG_glb_ptp_ns_delta_op(unsigned int uglb_ptp_ns_delta_op); +int iSetPTP_TS_INC_CFG_glb_ptp_inc_frac(unsigned int uglb_ptp_inc_frac); +int iSetPTP_TS_INC_CFG_glb_ptp_inc_intg(unsigned int uglb_ptp_inc_intg); +int iSetPTP_TS_CALIBRATION_glb_ptp_calb_value(unsigned int uglb_ptp_calb_value); +int iSetPTP_TS_CALIBRATION_glb_ptp_calb_sign(unsigned int uglb_ptp_calb_sign); +int iSetPTP_TS_WR_DATA0_glb_ptp_wr_sec_h(unsigned int uglb_ptp_wr_sec_h); +int iSetPTP_TS_WR_DATA1_glb_ptp_wr_sec_l(unsigned int uglb_ptp_wr_sec_l); +int iSetPTP_TS_WR_DATA2_glb_ptp_wr_ns(unsigned int uglb_ptp_wr_ns); +int iSetPTP_TS_RD_DATA0_glb_ptp_rd_sec_h(unsigned int uglb_ptp_rd_sec_h); +int iSetPTP_TS_RD_DATA1_glb_ptp_rd_sec_l(unsigned int uglb_ptp_rd_sec_l); +int iSetPTP_TS_RD_DATA2_glb_ptp_rd_ns(unsigned int uglb_ptp_rd_ns); +int iSetPTP_TS_UP_EN_glb_ptp_wr_up_en(unsigned int uglb_ptp_wr_up_en); +int iSetPTP_TS_UP_EN_glb_ptp_rd_up_en(unsigned int uglb_ptp_rd_up_en); +int iSetPTP_TS_UP_EN_glb_ptp_cfg_up_en(unsigned int uglb_ptp_cfg_up_en); +int iSetPTP_TS_UP_EN_glb_ptp_delta_up_en(unsigned int uglb_ptp_delta_up_en); +int iSetPTP_DSTR_CFG_glb_ptp_dstr_gap(unsigned int uglb_ptp_dstr_gap); +int iSetPTP_DSTR_CFG_glb_ptp_dstr_cmp_en(unsigned int uglb_ptp_dstr_cmp_en); +int iSetNON_PTP_TS_INC_CFG_glb_non_ptp_inc_frac(unsigned int uglb_non_ptp_inc_frac); +int iSetNON_PTP_TS_INC_CFG_glb_non_ptp_inc_intg(unsigned int uglb_non_ptp_inc_intg); +int iSetNON_PTP_TS_CALIBRATION_glb_non_ptp_calb_value(unsigned int uglb_non_ptp_calb_value); +int iSetNON_PTP_TS_CALIBRATION_glb_non_ptp_calb_sign(unsigned int uglb_non_ptp_calb_sign); +int iSetNON_PTP_TS_WR_DATA0_glb_non_ptp_wr_sec_h(unsigned int uglb_non_ptp_wr_sec_h); +int iSetNON_PTP_TS_WR_DATA1_glb_non_ptp_wr_sec_l(unsigned int uglb_non_ptp_wr_sec_l); +int iSetNON_PTP_TS_WR_DATA2_glb_non_ptp_wr_ns(unsigned int uglb_non_ptp_wr_ns); +int iSetNON_PTP_TS_RD_DATA0_glb_non_ptp_rd_sec_h(unsigned int uglb_non_ptp_rd_sec_h); +int iSetNON_PTP_TS_RD_DATA1_glb_non_ptp_rd_sec_l(unsigned int uglb_non_ptp_rd_sec_l); +int iSetNON_PTP_TS_RD_DATA2_glb_non_ptp_rd_ns(unsigned int uglb_non_ptp_rd_ns); +int iSetNON_PTP_TS_UP_EN_glb_non_ptp_wr_up_en(unsigned int uglb_non_ptp_wr_up_en); +int iSetNON_PTP_TS_UP_EN_glb_non_ptp_rd_up_en(unsigned int uglb_non_ptp_rd_up_en); +int iSetNON_PTP_TS_UP_EN_glb_non_ptp_cfg_up_en(unsigned int uglb_non_ptp_cfg_up_en); +int iSetNON_PTP_DSTR_CFG_glb_non_ptp_dstr_gap(unsigned int uglb_non_ptp_dstr_gap); +int iSetNON_PTP_DSTR_CFG_glb_non_ptp_dstr_cmp_en(unsigned int uglb_non_ptp_dstr_cmp_en); +int iSetGLB_VF_OFFSET_FOR_PF_glb_vf_offset_for_pf(unsigned int uglb_vf_offset_for_pf); + +/* Define the union csr_api_chain_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_addr_h_u; + +/* Define the union csr_api_chain_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_addr_l_u; + +/* Define the union csr_api_status_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_sts_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_addr_h_u; + +/* Define the union csr_api_status_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_sts_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_addr_l_u; + +/* Define the union csr_api_chain_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_len : 24; /* [23:0] */ + u32 rsv_0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_len_u; + +/* Define the union csr_api_chain_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_wb_after_susp : 1; /* [0] */ + u32 api_wb_after_restart : 1; /* [1] */ + u32 api_wb_after_xor_err : 1; /* [2] */ + u32 rsv_1 : 1; /* [3] */ + u32 api_wb_trigger_aeqe : 1; /* [4] */ + u32 ap_wb_after_cpld_err : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 api_wb_aeq_num : 2; /* [9:8] */ + u32 rsv_3 : 18; /* [27:10] */ + u32 api_xor_chk_en : 2; /* [29:28] */ + u32 api_cell_unit : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_ctl_u; + +/* Define the union csr_api_chain_dma_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_wb_dma_attr_offset : 6; /* [5:0] */ + u32 rsv_4 : 2; /* [7:6] */ + u32 api_chain_rd_dma_attr_offset : 6; /* [13:8] */ + u32 rsv_5 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_dma_attr_u; + +/* Define the union csr_api_chain_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_pi : 24; /* [23:0] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_pi_u; + +/* Define the union csr_api_chain_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_susp_req : 1; /* [0] */ + u32 api_chain_restart_req : 1; /* [1] */ + u32 api_sts_rd_req : 1; /* [2] */ + u32 rsv_7 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_req_u; + +/* Define the union csr_api_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_cur_ci : 24; /* [23:0] */ + u32 api_chain_cur_fsm : 4; /* [27:24] */ + u32 api_xor_chk_error : 2; /* [29:28] */ + u32 api_cpld_err : 1; /* [30] */ + u32 rsv_8 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_0_u; + +/* Define the union csr_api_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_cur_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_1_u; + +/* Define the union csr_api_status_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_cur_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_api_chain_addr_h_u api_chain_addr_h[2]; /* 0 */ + volatile csr_api_chain_addr_l_u api_chain_addr_l[2]; /* 4 */ + volatile csr_api_status_addr_h_u api_status_addr_h[2]; /* 8 */ + volatile csr_api_status_addr_l_u api_status_addr_l[2]; /* C */ + volatile csr_api_chain_len_u api_chain_len[2]; /* 10 */ + volatile csr_api_chain_ctl_u api_chain_ctl[2]; /* 14 */ + volatile csr_api_chain_dma_attr_u api_chain_dma_attr[2]; /* 18 */ + volatile csr_api_chain_pi_u api_chain_pi[2]; /* 1C */ + volatile csr_api_chain_req_u api_chain_req[2]; /* 20 */ + volatile csr_api_status_0_u api_status_0[2]; /* 30 */ + volatile csr_api_status_1_u api_status_1[2]; /* 34 */ + volatile csr_api_status_2_u api_status_2[2]; /* 38 */ +} S_api_chn_csr_REGS_TYPE; + +/* Declare the struct pointor of the module api_chn_csr */ +extern volatile S_api_chn_csr_REGS_TYPE *gopapi_chn_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAPI_CHAIN_ADDR_H_api_chain_addr_h(unsigned int uapi_chain_addr_h); +int iSetAPI_CHAIN_ADDR_L_api_chain_addr_l(unsigned int uapi_chain_addr_l); +int iSetAPI_STATUS_ADDR_H_api_sts_addr_h(unsigned int uapi_sts_addr_h); +int iSetAPI_STATUS_ADDR_L_api_sts_addr_l(unsigned int uapi_sts_addr_l); +int iSetAPI_CHAIN_LEN_api_chain_len(unsigned int uapi_chain_len); +int iSetAPI_CHAIN_CTL_api_wb_after_susp(unsigned int uapi_wb_after_susp); +int iSetAPI_CHAIN_CTL_api_wb_after_restart(unsigned int uapi_wb_after_restart); +int iSetAPI_CHAIN_CTL_api_wb_after_xor_err(unsigned int uapi_wb_after_xor_err); +int iSetAPI_CHAIN_CTL_api_wb_trigger_aeqe(unsigned int uapi_wb_trigger_aeqe); +int iSetAPI_CHAIN_CTL_ap_wb_after_cpld_err(unsigned int uap_wb_after_cpld_err); +int iSetAPI_CHAIN_CTL_api_wb_aeq_num(unsigned int uapi_wb_aeq_num); +int iSetAPI_CHAIN_CTL_api_xor_chk_en(unsigned int uapi_xor_chk_en); +int iSetAPI_CHAIN_CTL_api_cell_unit(unsigned int uapi_cell_unit); +int iSetAPI_CHAIN_DMA_ATTR_api_wb_dma_attr_offset(unsigned int uapi_wb_dma_attr_offset); +int iSetAPI_CHAIN_DMA_ATTR_api_chain_rd_dma_attr_offset(unsigned int uapi_chain_rd_dma_attr_offset); +int iSetAPI_CHAIN_PI_api_chain_pi(unsigned int uapi_chain_pi); +int iSetAPI_CHAIN_REQ_api_chain_susp_req(unsigned int uapi_chain_susp_req); +int iSetAPI_CHAIN_REQ_api_chain_restart_req(unsigned int uapi_chain_restart_req); +int iSetAPI_CHAIN_REQ_api_sts_rd_req(unsigned int uapi_sts_rd_req); +int iSetAPI_STATUS_0_api_chain_cur_ci(unsigned int uapi_chain_cur_ci); +int iSetAPI_STATUS_0_api_chain_cur_fsm(unsigned int uapi_chain_cur_fsm); +int iSetAPI_STATUS_0_api_xor_chk_error(unsigned int uapi_xor_chk_error); +int iSetAPI_STATUS_0_api_cpld_err(unsigned int uapi_cpld_err); +int iSetAPI_STATUS_1_api_chain_cur_addr_h(unsigned int uapi_chain_cur_addr_h); +int iSetAPI_STATUS_2_api_chain_cur_addr_l(unsigned int uapi_chain_cur_addr_l); + +/* Define the union csr_glb_debug_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_func_idx : 12; /* [11:0] */ + u32 rsv_0 : 4; /* [15:12] */ + u32 glb_dbg_bar_bitmap : 7; /* [22:16] */ + u32 rsv_1 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_cfg_u; + +/* Define the union csr_glb_debug_rx_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_rx_mwr_tlp_cnt : 16; /* [15:0] */ + u32 glb_dbg_rx_mrd_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_rx_tlp_cnt_u; + +/* Define the union csr_glb_debug_rx_dbl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_rx_dbl_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_rx_dbl_cnt_u; + +/* Define the union csr_glb_debug_rx_dwqe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_rx_dwqe_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_rx_dwqe_cnt_u; + +/* Define the union csr_glb_port0_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port0_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port0_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port0_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port1_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port1_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port1_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port1_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port2_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port2_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port2_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port2_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port3_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port3_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port3_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port3_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port4_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port4_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port4_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port4_npcpl_tlp_cnt_u; + +/* Define the union csr_dfx_ictl_rx_ok_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_sop_cnt : 16; /* [15:0] */ + u32 dfx_ictl_ok_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_ok_cnt_u; + +/* Define the union csr_dfx_ictl_rx_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_vld_cnt : 16; /* [15:0] */ + u32 dfx_ictl_eop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_eop_cnt_u; + +/* Define the union csr_dfx_ictl_sop_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_osch_tx_cpl_cnt : 16; /* [15:0] */ + u32 dfx_ictl_sop_eop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_sop_eop_cnt_u; + +/* Define the union csr_dfx_ictl_mpu_acc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_apb_rd_cnt : 16; /* [15:0] */ + u32 mpu_apb_wr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_mpu_acc_cnt_u; + +/* Define the union csr_dfx_ictl_ipush_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dwqe_tlp_cnt : 16; /* [15:0] */ + u32 ictl_ipush_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_ipush_tlp_cnt_u; + +/* Define the union csr_dfx_ictl_vio_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_rx_mem_cnt : 16; /* [15:0] */ + u32 ictl_vio_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_vio_tlp_cnt_u; + +/* Define the union csr_dfx_ictl_rx_io_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_rx_rom_cnt : 16; /* [15:0] */ + u32 dfx_ictl_rx_io_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_io_cnt_u; + +/* Define the union csr_dfx_ictl_rx_tlp_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_rx_uns_np_cnt : 16; /* [15:0] */ + u32 dfx_ictl_rx_tlp_drop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_tlp_drop_cnt_u; + +/* Define the union csr_glb_cpi_port_bp_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port_bp_en_cfg : 5; /* [4:0] */ + u32 rsv_2 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_port_bp_en_cfg_u; + +/* Define the union csr_dfx_ictl_fatal_msk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_fatal_msk95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_fatal_msk0_u; + +/* Define the union csr_dfx_ictl_fatal_msk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_fatal_msk63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_fatal_msk1_u; + +/* Define the union csr_dfx_ictl_fatal_msk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_fatal_msk31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_fatal_msk2_u; + +/* Define the union csr_dfx_ictl_nonfatal_msk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_nonfatal_msk95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_nonfatal_msk0_u; + +/* Define the union csr_dfx_ictl_nonfatal_msk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_nonfatal_msk63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_nonfatal_msk1_u; + +/* Define the union csr_dfx_ictl_nonfatal_msk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_nonfatal_msk31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_nonfatal_msk2_u; + +/* Define the union csr_dfx_ictl_err_pls0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_err_pls95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_err_pls0_u; + +/* Define the union csr_dfx_ictl_err_pls1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_err_pls63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_err_pls1_u; + +/* Define the union csr_dfx_ictl_err_pls2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_err_pls31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_err_pls2_u; + +/* Define the union csr_glb_cpi_bp_watch_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_sts_u; + +/* Define the union csr_glb_cpi_bp_watch_window_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_window : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_window_u; + +/* Define the union csr_glb_cpi_bp_watch_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_bitmap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_bitmap_u; + +/* Define the union csr_glb_cpi_bp_watch_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_start : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_start_u; + +/* Define the union csr_glb_cpi_bp_watch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_cnt_u; + +/* Define the union csr_glb_csr_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_csr_timeout_cnt : 8; /* [7:0] */ + u32 glb_non_csr_timeout_cnt : 8; /* [15:8] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_csr_timeout_cnt_u; + +/* Define the union csr_dwqe_api_no_enough_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_api_no_enough_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_api_no_enough_data_u; + +/* Define the union csr_dwqe_dbl_no_enough_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_no_enough_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_no_enough_data_u; + +/* Define the union csr_norm_dbl_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_illegal_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_drop_cnt_u; + +/* Define the union csr_norm_dbl_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_tx_cnt_u; + +/* Define the union csr_dwqe_dbl_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_tx_cnt_u; + +/* Define the union csr_dwqe_api_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_api_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_api_tx_cnt_u; + +/* Define the union csr_dwqe_buf_bp_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_bp_sts : 4; /* [3:0] */ + u32 rsv_5 : 27; /* [30:4] */ + u32 dwqe_buf_bp_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_bp_msk_u; + +/* Define the union csr_dwqe_buf_cnt_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_cnt_port3 : 8; /* [7:0] */ + u32 dwqe_buf_cnt_port2 : 8; /* [15:8] */ + u32 dwqe_buf_cnt_port1 : 8; /* [23:16] */ + u32 dwqe_buf_cnt_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_cnt_port_u; + +/* Define the union csr_dwqe_buf_bp_on_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_bp_on_port3 : 8; /* [7:0] */ + u32 dwqe_buf_bp_on_port2 : 8; /* [15:8] */ + u32 dwqe_buf_bp_on_port1 : 8; /* [23:16] */ + u32 dwqe_buf_bp_on_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_bp_on_port_u; + +/* Define the union csr_dwqe_buf_bp_off_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_bp_off_port3 : 8; /* [7:0] */ + u32 dwqe_buf_bp_off_port2 : 8; /* [15:8] */ + u32 dwqe_buf_bp_off_port1 : 8; /* [23:16] */ + u32 dwqe_buf_bp_off_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_bp_off_port_u; + +/* Define the union csr_dwqe_req_buf_bgn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_req_buf_bgn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_req_buf_bgn_u; + +/* Define the union csr_dwqe_dropping_in_tx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dropping_in_tx : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dropping_in_tx_u; + +/* Define the union csr_dwqe_dropping_no_buf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dropping_no_buf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dropping_no_buf_u; + +/* Define the union csr_dwqe_dbl_without_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_without_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_without_api_u; + +/* Define the union csr_dwqe_tx_dbl_after_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_dbl_after_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_dbl_after_api_u; + +/* Define the union csr_dwqe_no_dbl_after_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_no_dbl_after_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_no_dbl_after_api_u; + +/* Define the union csr_dwqe_buf_overwrite_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_overwrite_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_overwrite_drop_cnt_u; + +/* Define the union csr_dwqe_buf_aging_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_aging_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_aging_drop_cnt_u; + +/* Define the union csr_dwqe_tx_req_fifo_push_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_req_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_req_fifo_push_cnt_u; + +/* Define the union csr_dwqe_tx_req_fifo_pop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_req_fifo_pop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_req_fifo_pop_cnt_u; + +/* Define the union csr_dwqe_tx_req_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_req_fifo_sts : 3; /* [2:0] */ + u32 rsv_6 : 5; /* [7:3] */ + u32 dwqe_tx_req_fifo_overflow : 8; /* [15:8] */ + u32 dwqe_buf_alc_cnt : 8; /* [23:16] */ + u32 dwqe_tx_req_fifo_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_req_fifo_sts_u; + +/* Define the union csr_dwqe_dropping_invld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dropping_invld : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dropping_invld_u; + +/* Define the union csr_dwqe_sw_force_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_sw_force_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_sw_force_drop_u; + +/* Define the union csr_ictl_dbl_req_sop_null_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dbl_req_sop_null : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_dbl_req_sop_null_u; + +/* Define the union csr_cpi_pcie_mb_aeqe_to_mpu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_aeqe_to_mpu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_aeqe_to_mpu_cnt_u; + +/* Define the union csr_dfx_rx_dwqe_ddb_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dwqe_ddb1_cnt : 16; /* [15:0] */ + u32 dfx_rx_dwqe_ddb0_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dwqe_ddb_cnt0_u; + +/* Define the union csr_dfx_rx_dwqe_ddb_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dwqe_ddb3_cnt : 16; /* [15:0] */ + u32 dfx_rx_dwqe_ddb2_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dwqe_ddb_cnt1_u; + +/* Define the union csr_dfx_rx_dbl_srv_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dbl_srv1_cnt : 16; /* [15:0] */ + u32 dfx_rx_dbl_srv0_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dbl_srv_cnt0_u; + +/* Define the union csr_dfx_rx_dbl_srv_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dbl_srv3_cnt : 16; /* [15:0] */ + u32 dfx_rx_dbl_srv2_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dbl_srv_cnt1_u; + +/* Define the union csr_glb_dfx_cfg_srv_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dfx_cfg0_srv_type : 5; /* [4:0] */ + u32 rsv_7 : 3; /* [7:5] */ + u32 glb_dfx_cfg1_srv_type : 5; /* [12:8] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 glb_dfx_cfg2_srv_type : 5; /* [20:16] */ + u32 rsv_9 : 3; /* [23:21] */ + u32 glb_dfx_cfg3_srv_type : 5; /* [28:24] */ + u32 rsv_10 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dfx_cfg_srv_type_u; + +/* Define the union csr_aeq_ci_sw_wr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_ci_sw_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ci_sw_wr_cnt_u; + +/* Define the union csr_aeq_tx_int_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_tx_int_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_tx_int_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_wr_pcie_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_wr_pcie_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_wr_pcie_cnt_u; + +/* Define the union csr_cpi_ipush_csr_wr_ucpu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_wr_ucpu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_wr_ucpu_cnt_u; + +/* Define the union csr_cpi_ipush_csr_rd_pcie_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_rd_pcie_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_rd_pcie_cnt_u; + +/* Define the union csr_cpi_ipush_csr_rd_ucpu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_rd_ucpu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_rd_ucpu_cnt_u; + +/* Define the union csr_cpi_ipush_osch_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_osch_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_osch_cpl_cnt_u; + +/* Define the union csr_cpi_ipush_ictl_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_ictl_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_ictl_cpl_cnt_u; + +/* Define the union csr_cpi_ipush_apictl_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_apictl_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_apictl_req_cnt_u; + +/* Define the union csr_cpi_pcie_mb_aeqe_to_dst_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_aeqe_to_dst_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_aeqe_to_dst_cnt_u; + +/* Define the union csr_cpi_pcie_mb_aeqe_to_src_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_aeqe_to_src_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_aeqe_to_src_cnt_u; + +/* Define the union csr_cpi_pcie_mb_stat_to_src_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_stat_to_src_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_stat_to_src_cnt_u; + +/* Define the union csr_cpi_ucpu_mb_aeqe_to_dst_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ucpu_mb_aeqe_to_dst_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ucpu_mb_aeqe_to_dst_cnt_u; + +/* Define the union csr_cpi_ipush_csr_aeq_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_aeq_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_aeq_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_ceq_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_ceq_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_ceq_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_api_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_api_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_api_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_intctl_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_intctl_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_intctl_req_cnt_u; + +/* Define the union csr_cpi_ipush_upitf_clp_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_upitf_clp_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_upitf_clp_req_cnt_u; + +/* Define the union csr_cpi_ram_ecc_inj_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err0_u; + +/* Define the union csr_cpi_ram_ecc_inj_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err1_u; + +/* Define the union csr_cpi_ram_ecc_inj_err2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err2_u; + +/* Define the union csr_cpi_ram_ecc_inj_err3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err3_u; + +/* Define the union csr_cpi_ram_ecc_merr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_merr0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_merr0_u; + +/* Define the union csr_cpi_ram_ecc_merr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_merr1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_merr1_u; + +/* Define the union csr_cpi_ram_ecc_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err0_u; + +/* Define the union csr_cpi_ram_ecc_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err1_u; + +/* Define the union csr_cpi_ram_ecc_err_addr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr0_u; + +/* Define the union csr_cpi_ram_ecc_err_addr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr1_u; + +/* Define the union csr_cpi_ram_ecc_err_addr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr2_u; + +/* Define the union csr_cpi_ram_ecc_err_addr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr3_u; + +/* Define the union csr_ipush_reserved0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved0_u; + +/* Define the union csr_ipush_reserved1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved1_u; + +/* Define the union csr_ipush_reserved2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved2_u; + +/* Define the union csr_ipush_reserved3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved3_u; + +/* Define the union csr_glb_cpi_uncrt_err_code0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_cmisc_uncrt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_dma_uncrt_err_code : 4; /* [7:4] */ + u32 glb_cpi_dtif_uncrt_err_code : 4; /* [11:8] */ + u32 glb_cpi_ictl_uncrt_err_code : 4; /* [15:12] */ + u32 glb_cpi_qmap_uncrt_err_code : 4; /* [19:16] */ + u32 glb_cpi_apictl_uncrt_err_code : 4; /* [23:20] */ + u32 glb_cpi_dpath_i_uncrt_err_code : 4; /* [27:24] */ + u32 glb_cpi_dpath_o_uncrt_err_code : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_uncrt_err_code0_u; + +/* Define the union csr_glb_cpi_uncrt_err_code1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ipush_uncrt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_uncrt_err_code : 4; /* [7:4] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_uncrt_err_code1_u; + +/* Define the union csr_glb_cpi_crt_err_code0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_cmisc_crt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_dma_crt_err_code : 4; /* [7:4] */ + u32 glb_cpi_dtif_crt_err_code : 4; /* [11:8] */ + u32 glb_cpi_ictl_crt_err_code : 4; /* [15:12] */ + u32 glb_cpi_qmap_crt_err_code : 4; /* [19:16] */ + u32 glb_cpi_apictl_crt_err_code : 4; /* [23:20] */ + u32 glb_cpi_dpath_i_crt_err_code : 4; /* [27:24] */ + u32 glb_cpi_dpath_o_crt_err_code : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_crt_err_code0_u; + +/* Define the union csr_glb_cpi_crt_err_code1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ipush_crt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_crt_err_code : 4; /* [7:4] */ + u32 rsv_12 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_crt_err_code1_u; + +/* Define the union csr_dwqe_buf_dbg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_src_tag_l : 15; /* [14:0] */ + u32 rsv_13 : 1; /* [15] */ + u32 dwqe_buf_dbg_status : 2; /* [17:16] */ + u32 rsv_14 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_dbg0_u; + +/* Define the union csr_dwqe_buf_dbg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_exp_qw_num : 6; /* [5:0] */ + u32 rsv_15 : 2; /* [7:6] */ + u32 dwqe_buf_dbg_rx_qw_cnt : 6; /* [13:8] */ + u32 rsv_16 : 2; /* [15:14] */ + u32 dwqe_buf_dbg_no_dbl : 1; /* [16] */ + u32 dwqe_buf_dbg_aging_flag : 1; /* [17] */ + u32 rsv_17 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_dbg1_u; + +/* Define the union csr_dwqe_buf_dbg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_idx : 7; /* [6:0] */ + u32 rsv_18 : 1; /* [7] */ + u32 dwqe_buf_dbg_watch_en : 1; /* [8] */ + u32 dwqe_buf_dbg_force_ivld : 1; /* [9] */ + u32 rsv_19 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_dbg2_u; + +/* Define the union csr_dwqe_bug_dbg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_host_addr : 21; /* [20:0] */ + u32 rsv_20 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_bug_dbg3_u; + +/* Define the union csr_glb_mb_grp_tx_req_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_tx_req_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_tx_req_h_u; + +/* Define the union csr_glb_mb_grp_tx_req_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_tx_req_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_tx_req_l_u; + +/* Define the union csr_glb_mb_grp_grant_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_grant_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_grant_h_u; + +/* Define the union csr_glb_mb_grp_grant_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_grant_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_grant_l_u; + +/* Define the union csr_ictl_ipush_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_ipush_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_ipush_sop_cnt_u; + +/* Define the union csr_ictl_ipush_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_ipush_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_ipush_eop_cnt_u; + +/* Define the union csr_glb_mb_in_grp_tx_req_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_tx_req_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_tx_req_h_u; + +/* Define the union csr_glb_mb_in_grp_tx_req_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_tx_req_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_tx_req_l_u; + +/* Define the union csr_glb_mb_in_grp_grant_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_grant_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_grant_h_u; + +/* Define the union csr_glb_mb_in_grp_grant_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_grant_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_grant_l_u; + +/* Define the union csr_glb_mb_tx_start_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_start_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_start_cnt_u; + +/* Define the union csr_glb_mb_tx_illegal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_illegal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_illegal_cnt_u; + +/* Define the union csr_glb_mb_tx_illegal_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_illegal_code : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_illegal_code_u; + +/* Define the union csr_glb_mb_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_buf_fsm_state : 3; /* [2:0] */ + u32 rsv_22 : 1; /* [3] */ + u32 glb_mb_csr_ram_fsm_state : 4; /* [7:4] */ + u32 glb_mb_tx_fsm_state : 3; /* [10:8] */ + u32 rsv_23 : 1; /* [11] */ + u32 glb_mb_rr_fsm_state : 3; /* [14:12] */ + u32 rsv_24 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_fsm_state_u; + +/* Define the union csr_ictl_inbd_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_inbd_fifo_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_inbd_fifo_sts_u; + +/* Define the union csr_ictl_dbl_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dbl_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_dbl_sop_cnt_u; + +/* Define the union csr_ictl_dbl_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dbl_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_dbl_eop_cnt_u; + +/* Define the union csr_dwqe_drop_no_wr_buf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_drop_no_wr_buf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_drop_no_wr_buf_cnt_u; + +/* Define the union csr_dwqe_wr_buf_complete_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_wr_buf_complete_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_wr_buf_complete_cnt_u; + +/* Define the union csr_norm_dbl_rx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_rx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_rx_cnt_u; + +/* Define the union csr_norm_dbl_force_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_force_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_force_drop_u; + +/* Define the union csr_dwqe_rx_buf_bgn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_rx_buf_bgn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_rx_buf_bgn_u; + +/* Define the union csr_dwqe_illegal_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_illegal_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_illegal_drop_cnt_u; + +/* Define the union csr_dwqe_dbl_force_drop_no_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_force_drop_no_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_force_drop_no_api_u; + +/* Define the union csr_dwqe_dbl_force_drop_aft_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_force_drop_aft_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_force_drop_aft_api_u; + +/* Define the union csr_aeq_fsm_dbg_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_dbg_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_fsm_dbg_state_u; + +/* Define the union csr_glb_ucpu_msi_func_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ucpu_msi_func_idx : 10; /* [9:0] */ + u32 rsv_25 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ucpu_msi_func_idx_u; + +/* Define the union csr_glb_pcie_inbd_itf_wind_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_26 : 4; /* [3:0] */ + u32 pcie_inbd_itf_wind_16t : 16; /* [19:4] */ + u32 rsv_27 : 10; /* [29:20] */ + u32 pcie_inbd_itf_wind_mode : 1; /* [30] */ + u32 pcie_inbd_itf_wind_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_pcie_inbd_itf_wind_ctl_u; + +/* Define the union csr_glb_pcie_inbd_itf_wind_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_inbd_wind_detect_cnt : 20; /* [19:0] */ + u32 rsv_28 : 11; /* [30:20] */ + u32 pcie_inbd_wind_detect_done : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_pcie_inbd_itf_wind_cnt_u; + +/* Define the union csr_glb_pcie_inbd_itf_wind_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_inbd_wind_detect_tlp_cnt : 20; /* [19:0] */ + u32 rsv_29 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_pcie_inbd_itf_wind_tlp_cnt_u; + +/* Define the union csr_glb_dbg_cnt_dbl_grp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_cnt_dbl_grp_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cnt_dbl_grp_en_u; + +/* Define the union csr_glb_dbl_crd_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_timer_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_timer_cfg_u; + +/* Define the union csr_glb_dbl_crd_cfg_port01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cfg_port1 : 16; /* [15:0] */ + u32 glb_dbl_crd_cfg_port0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cfg_port01_u; + +/* Define the union csr_glb_dbl_crd_cfg_port23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cfg_port3 : 16; /* [15:0] */ + u32 glb_dbl_crd_cfg_port2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cfg_port23_u; + +/* Define the union csr_glb_dbl_crd_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port0 : 26; /* [25:0] */ + u32 rsv_30 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port0_u; + +/* Define the union csr_glb_dbl_crd_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port1 : 26; /* [25:0] */ + u32 rsv_31 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port1_u; + +/* Define the union csr_glb_dbl_crd_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port2 : 26; /* [25:0] */ + u32 rsv_32 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port2_u; + +/* Define the union csr_glb_dbl_crd_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port3 : 26; /* [25:0] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port3_u; + +/* Define the union csr_cpath_enj_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_enj_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_a_fatal_msk_u; + +/* Define the union csr_cpath_enj_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_enj_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_a_nonfatal_msk_u; + +/* Define the union csr_cpath_enj_fifo_aful_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_icpl_rdr_fifo_th : 4; /* [3:0] */ + u32 rsv_34 : 4; /* [7:4] */ + u32 oubd_pi_afifo_aful_gap_cpi : 5; /* [12:8] */ + u32 rsv_35 : 3; /* [15:13] */ + u32 oubd_pe_afifo_aful_gap_cpi : 5; /* [20:16] */ + u32 rsv_36 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_fifo_aful_th_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_tile_cnt : 16; /* [15:0] */ + u32 pure_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt0_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_cnt : 16; /* [15:0] */ + u32 cpath_rsv_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt1_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api10_cnt : 16; /* [15:0] */ + u32 cpath_octl_api11_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt2_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api08_cnt : 16; /* [15:0] */ + u32 cpath_octl_api09_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt3_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api06_cnt : 16; /* [15:0] */ + u32 cpath_octl_api07_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt4_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api04_cnt : 16; /* [15:0] */ + u32 cpath_octl_api05_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt5_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api02_cnt : 16; /* [15:0] */ + u32 cpath_octl_api03_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt6_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api00_cnt : 16; /* [15:0] */ + u32 cpath_octl_api01_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt7_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_afifo_pe : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo0_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_sfifo_pe : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo1_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_sfifo_pi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo2_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_sfifo_rsp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo3_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_0sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo4_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_1sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo5_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_2sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo6_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_3sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo7_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_tile : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo8_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_mqm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo9_u; + +/* Define the union csr_glb_dbg_cpath_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro0_u; + +/* Define the union csr_glb_dbg_cpath_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro1_u; + +/* Define the union csr_glb_dbg_cpath_ro2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro2_u; + +/* Define the union csr_glb_dbg_cpath_ro3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro3_u; + +/* Define the union csr_glb_dbg_cpath_ro4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro4_u; + +/* Define the union csr_glb_dbg_cpath_ro5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro5_u; + +/* Define the union csr_glb_dbg_cpath_ro6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro6_u; + +/* Define the union csr_glb_dbg_cpath_ro7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro7_u; + +/* Define the union csr_glb_dbg_cpath_ro8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_0sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro8_u; + +/* Define the union csr_glb_dbg_cpath_ro9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_1sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro9_u; + +/* Define the union csr_glb_dbg_cpath_ro10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_2sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro10_u; + +/* Define the union csr_glb_dbg_cpath_ro11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_3sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro11_u; + +/* Define the union csr_glb_dbg_cpath_ro12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_tile : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro12_u; + +/* Define the union csr_glb_dbg_cpath_ro13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_mqm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro13_u; + +/* Define the union csr_cpath_enj_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_enj_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_pls_u; + +/* Define the union csr_ctrl_mem_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus133_128 : 6; /* [5:0] */ + u32 rsv_37 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus0_u; + +/* Define the union csr_ctrl_mem_ctrl_bus1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus1_u; + +/* Define the union csr_ctrl_mem_ctrl_bus2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus2_u; + +/* Define the union csr_ctrl_mem_ctrl_bus3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus3_u; + +/* Define the union csr_ctrl_mem_ctrl_bus4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus4_u; + +/* Define the union csr_ctrl_tcam_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_tcam_ctrl_bus9_0 : 10; /* [9:0] */ + u32 rsv_38 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_tcam_ctrl_bus0_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_glb_debug_cfg_u glb_debug_cfg[16]; /* 0 */ + volatile csr_glb_debug_rx_tlp_cnt_u glb_debug_rx_tlp_cnt[16]; /* 4 */ + volatile csr_glb_debug_rx_dbl_cnt_u glb_debug_rx_dbl_cnt[16]; /* 8 */ + volatile csr_glb_debug_rx_dwqe_cnt_u glb_debug_rx_dwqe_cnt[16]; /* C */ + volatile csr_glb_port0_npcpl_tlp_cnt_u glb_port0_npcpl_tlp_cnt; /* 100 */ + volatile csr_glb_port1_npcpl_tlp_cnt_u glb_port1_npcpl_tlp_cnt; /* 104 */ + volatile csr_glb_port2_npcpl_tlp_cnt_u glb_port2_npcpl_tlp_cnt; /* 108 */ + volatile csr_glb_port3_npcpl_tlp_cnt_u glb_port3_npcpl_tlp_cnt; /* 10C */ + volatile csr_glb_port4_npcpl_tlp_cnt_u glb_port4_npcpl_tlp_cnt; /* 110 */ + volatile csr_dfx_ictl_rx_ok_cnt_u dfx_ictl_rx_ok_cnt; /* 114 */ + volatile csr_dfx_ictl_rx_eop_cnt_u dfx_ictl_rx_eop_cnt; /* 118 */ + volatile csr_dfx_ictl_sop_eop_cnt_u dfx_ictl_sop_eop_cnt; /* 11C */ + volatile csr_dfx_ictl_mpu_acc_cnt_u dfx_ictl_mpu_acc_cnt; /* 120 */ + volatile csr_dfx_ictl_ipush_tlp_cnt_u dfx_ictl_ipush_tlp_cnt; /* 124 */ + volatile csr_dfx_ictl_vio_tlp_cnt_u dfx_ictl_vio_tlp_cnt; /* 128 */ + volatile csr_dfx_ictl_rx_io_cnt_u dfx_ictl_rx_io_cnt; /* 12C */ + volatile csr_dfx_ictl_rx_tlp_drop_cnt_u dfx_ictl_rx_tlp_drop_cnt; /* 130 */ + volatile csr_glb_cpi_port_bp_en_cfg_u glb_cpi_port_bp_en_cfg; /* 134 */ + volatile csr_dfx_ictl_fatal_msk0_u dfx_ictl_fatal_msk0; /* 140 */ + volatile csr_dfx_ictl_fatal_msk1_u dfx_ictl_fatal_msk1; /* 144 */ + volatile csr_dfx_ictl_fatal_msk2_u dfx_ictl_fatal_msk2; /* 148 */ + volatile csr_dfx_ictl_nonfatal_msk0_u dfx_ictl_nonfatal_msk0; /* 150 */ + volatile csr_dfx_ictl_nonfatal_msk1_u dfx_ictl_nonfatal_msk1; /* 154 */ + volatile csr_dfx_ictl_nonfatal_msk2_u dfx_ictl_nonfatal_msk2; /* 158 */ + volatile csr_dfx_ictl_err_pls0_u dfx_ictl_err_pls0; /* 160 */ + volatile csr_dfx_ictl_err_pls1_u dfx_ictl_err_pls1; /* 164 */ + volatile csr_dfx_ictl_err_pls2_u dfx_ictl_err_pls2; /* 168 */ + volatile csr_glb_cpi_bp_watch_sts_u glb_cpi_bp_watch_sts; /* 400 */ + volatile csr_glb_cpi_bp_watch_window_u glb_cpi_bp_watch_window; /* 404 */ + volatile csr_glb_cpi_bp_watch_bitmap_u glb_cpi_bp_watch_bitmap; /* 408 */ + volatile csr_glb_cpi_bp_watch_start_u glb_cpi_bp_watch_start; /* 40C */ + volatile csr_glb_cpi_bp_watch_cnt_u glb_cpi_bp_watch_cnt; /* 410 */ + volatile csr_glb_csr_timeout_cnt_u glb_csr_timeout_cnt; /* 414 */ + volatile csr_dwqe_api_no_enough_data_u dwqe_api_no_enough_data; /* 418 */ + volatile csr_dwqe_dbl_no_enough_data_u dwqe_dbl_no_enough_data; /* 41C */ + volatile csr_norm_dbl_drop_cnt_u norm_dbl_drop_cnt; /* 420 */ + volatile csr_norm_dbl_tx_cnt_u norm_dbl_tx_cnt; /* 424 */ + volatile csr_dwqe_dbl_tx_cnt_u dwqe_dbl_tx_cnt; /* 428 */ + volatile csr_dwqe_api_tx_cnt_u dwqe_api_tx_cnt; /* 42C */ + volatile csr_dwqe_buf_bp_msk_u dwqe_buf_bp_msk; /* 430 */ + volatile csr_dwqe_buf_cnt_port_u dwqe_buf_cnt_port; /* 434 */ + volatile csr_dwqe_buf_bp_on_port_u dwqe_buf_bp_on_port; /* 438 */ + volatile csr_dwqe_buf_bp_off_port_u dwqe_buf_bp_off_port; /* 43C */ + volatile csr_dwqe_req_buf_bgn_u dwqe_req_buf_bgn; /* 440 */ + volatile csr_dwqe_dropping_in_tx_u dwqe_dropping_in_tx; /* 444 */ + volatile csr_dwqe_dropping_no_buf_u dwqe_dropping_no_buf; /* 448 */ + volatile csr_dwqe_dbl_without_api_u dwqe_dbl_without_api; /* 44C */ + volatile csr_dwqe_tx_dbl_after_api_u dwqe_tx_dbl_after_api; /* 450 */ + volatile csr_dwqe_no_dbl_after_api_u dwqe_no_dbl_after_api; /* 454 */ + volatile csr_dwqe_buf_overwrite_drop_cnt_u dwqe_buf_overwrite_drop_cnt; /* 458 */ + volatile csr_dwqe_buf_aging_drop_cnt_u dwqe_buf_aging_drop_cnt; /* 45C */ + volatile csr_dwqe_tx_req_fifo_push_cnt_u dwqe_tx_req_fifo_push_cnt; /* 460 */ + volatile csr_dwqe_tx_req_fifo_pop_cnt_u dwqe_tx_req_fifo_pop_cnt; /* 464 */ + volatile csr_dwqe_tx_req_fifo_sts_u dwqe_tx_req_fifo_sts; /* 468 */ + volatile csr_dwqe_dropping_invld_u dwqe_dropping_invld; /* 474 */ + volatile csr_dwqe_sw_force_drop_u dwqe_sw_force_drop; /* 478 */ + volatile csr_ictl_dbl_req_sop_null_u ictl_dbl_req_sop_null; /* 47C */ + volatile csr_cpi_pcie_mb_aeqe_to_mpu_cnt_u cpi_pcie_mb_aeqe_to_mpu_cnt; /* 480 */ + volatile csr_dfx_rx_dwqe_ddb_cnt0_u dfx_rx_dwqe_ddb_cnt0; /* 4A0 */ + volatile csr_dfx_rx_dwqe_ddb_cnt1_u dfx_rx_dwqe_ddb_cnt1; /* 4A4 */ + volatile csr_dfx_rx_dbl_srv_cnt0_u dfx_rx_dbl_srv_cnt0; /* 4A8 */ + volatile csr_dfx_rx_dbl_srv_cnt1_u dfx_rx_dbl_srv_cnt1; /* 4AC */ + volatile csr_glb_dfx_cfg_srv_type_u glb_dfx_cfg_srv_type; /* 4B0 */ + volatile csr_aeq_ci_sw_wr_cnt_u aeq_ci_sw_wr_cnt; /* 4B4 */ + volatile csr_aeq_tx_int_req_cnt_u aeq_tx_int_req_cnt; /* 4BC */ + volatile csr_cpi_ipush_csr_wr_pcie_cnt_u cpi_ipush_csr_wr_pcie_cnt; /* 4C0 */ + volatile csr_cpi_ipush_csr_wr_ucpu_cnt_u cpi_ipush_csr_wr_ucpu_cnt; /* 4C4 */ + volatile csr_cpi_ipush_csr_rd_pcie_cnt_u cpi_ipush_csr_rd_pcie_cnt; /* 4C8 */ + volatile csr_cpi_ipush_csr_rd_ucpu_cnt_u cpi_ipush_csr_rd_ucpu_cnt; /* 4CC */ + volatile csr_cpi_ipush_osch_cpl_cnt_u cpi_ipush_osch_cpl_cnt; /* 4D0 */ + volatile csr_cpi_ipush_ictl_cpl_cnt_u cpi_ipush_ictl_cpl_cnt; /* 4D4 */ + volatile csr_cpi_ipush_apictl_req_cnt_u cpi_ipush_apictl_req_cnt; /* 4D8 */ + volatile csr_cpi_pcie_mb_aeqe_to_dst_cnt_u cpi_pcie_mb_aeqe_to_dst_cnt; /* 4DC */ + volatile csr_cpi_pcie_mb_aeqe_to_src_cnt_u cpi_pcie_mb_aeqe_to_src_cnt; /* 4E0 */ + volatile csr_cpi_pcie_mb_stat_to_src_cnt_u cpi_pcie_mb_stat_to_src_cnt; /* 4E4 */ + volatile csr_cpi_ucpu_mb_aeqe_to_dst_cnt_u cpi_ucpu_mb_aeqe_to_dst_cnt; /* 4E8 */ + volatile csr_cpi_ipush_csr_aeq_req_cnt_u cpi_ipush_csr_aeq_req_cnt; /* 4EC */ + volatile csr_cpi_ipush_csr_ceq_req_cnt_u cpi_ipush_csr_ceq_req_cnt; /* 4F0 */ + volatile csr_cpi_ipush_csr_api_req_cnt_u cpi_ipush_csr_api_req_cnt; /* 4F4 */ + volatile csr_cpi_ipush_csr_intctl_req_cnt_u cpi_ipush_csr_intctl_req_cnt; /* 4F8 */ + volatile csr_cpi_ipush_upitf_clp_req_cnt_u cpi_ipush_upitf_clp_req_cnt; /* 4FC */ + volatile csr_cpi_ram_ecc_inj_err0_u cpi_ram_ecc_inj_err0; /* 500 */ + volatile csr_cpi_ram_ecc_inj_err1_u cpi_ram_ecc_inj_err1; /* 504 */ + volatile csr_cpi_ram_ecc_inj_err2_u cpi_ram_ecc_inj_err2; /* 508 */ + volatile csr_cpi_ram_ecc_inj_err3_u cpi_ram_ecc_inj_err3; /* 50C */ + volatile csr_cpi_ram_ecc_merr0_u cpi_ram_ecc_merr0; /* 520 */ + volatile csr_cpi_ram_ecc_merr1_u cpi_ram_ecc_merr1; /* 524 */ + volatile csr_cpi_ram_ecc_err0_u cpi_ram_ecc_err0; /* 540 */ + volatile csr_cpi_ram_ecc_err1_u cpi_ram_ecc_err1; /* 544 */ + volatile csr_cpi_ram_ecc_err_addr0_u cpi_ram_ecc_err_addr0; /* 560 */ + volatile csr_cpi_ram_ecc_err_addr1_u cpi_ram_ecc_err_addr1; /* 564 */ + volatile csr_cpi_ram_ecc_err_addr2_u cpi_ram_ecc_err_addr2; /* 568 */ + volatile csr_cpi_ram_ecc_err_addr3_u cpi_ram_ecc_err_addr3; /* 56C */ + volatile csr_ipush_reserved0_u ipush_reserved0; /* 5C0 */ + volatile csr_ipush_reserved1_u ipush_reserved1; /* 5C4 */ + volatile csr_ipush_reserved2_u ipush_reserved2; /* 5C8 */ + volatile csr_ipush_reserved3_u ipush_reserved3; /* 5CC */ + volatile csr_glb_cpi_uncrt_err_code0_u glb_cpi_uncrt_err_code0; /* 5D0 */ + volatile csr_glb_cpi_uncrt_err_code1_u glb_cpi_uncrt_err_code1; /* 5D4 */ + volatile csr_glb_cpi_crt_err_code0_u glb_cpi_crt_err_code0; /* 5D8 */ + volatile csr_glb_cpi_crt_err_code1_u glb_cpi_crt_err_code1; /* 5DC */ + volatile csr_dwqe_buf_dbg0_u dwqe_buf_dbg0; /* 5E0 */ + volatile csr_dwqe_buf_dbg1_u dwqe_buf_dbg1; /* 5E4 */ + volatile csr_dwqe_buf_dbg2_u dwqe_buf_dbg2; /* 5E8 */ + volatile csr_dwqe_bug_dbg3_u dwqe_bug_dbg3; /* 5EC */ + volatile csr_glb_mb_grp_tx_req_h_u glb_mb_grp_tx_req_h; /* 5F0 */ + volatile csr_glb_mb_grp_tx_req_l_u glb_mb_grp_tx_req_l; /* 5F4 */ + volatile csr_glb_mb_grp_grant_h_u glb_mb_grp_grant_h; /* 5F8 */ + volatile csr_glb_mb_grp_grant_l_u glb_mb_grp_grant_l; /* 5FC */ + volatile csr_ictl_ipush_sop_cnt_u ictl_ipush_sop_cnt; /* 608 */ + volatile csr_ictl_ipush_eop_cnt_u ictl_ipush_eop_cnt; /* 60C */ + volatile csr_glb_mb_in_grp_tx_req_h_u glb_mb_in_grp_tx_req_h; /* 610 */ + volatile csr_glb_mb_in_grp_tx_req_l_u glb_mb_in_grp_tx_req_l; /* 614 */ + volatile csr_glb_mb_in_grp_grant_h_u glb_mb_in_grp_grant_h; /* 618 */ + volatile csr_glb_mb_in_grp_grant_l_u glb_mb_in_grp_grant_l; /* 61C */ + volatile csr_glb_mb_tx_start_cnt_u glb_mb_tx_start_cnt; /* 620 */ + volatile csr_glb_mb_tx_illegal_cnt_u glb_mb_tx_illegal_cnt; /* 624 */ + volatile csr_glb_mb_tx_illegal_code_u glb_mb_tx_illegal_code; /* 628 */ + volatile csr_glb_mb_fsm_state_u glb_mb_fsm_state; /* 62C */ + volatile csr_ictl_inbd_fifo_sts_u ictl_inbd_fifo_sts; /* 638 */ + volatile csr_ictl_dbl_sop_cnt_u ictl_dbl_sop_cnt; /* 640 */ + volatile csr_ictl_dbl_eop_cnt_u ictl_dbl_eop_cnt; /* 644 */ + volatile csr_dwqe_drop_no_wr_buf_cnt_u dwqe_drop_no_wr_buf_cnt; /* 648 */ + volatile csr_dwqe_wr_buf_complete_cnt_u dwqe_wr_buf_complete_cnt; /* 64C */ + volatile csr_norm_dbl_rx_cnt_u norm_dbl_rx_cnt; /* 690 */ + volatile csr_norm_dbl_force_drop_u norm_dbl_force_drop; /* 694 */ + volatile csr_dwqe_rx_buf_bgn_u dwqe_rx_buf_bgn; /* 698 */ + volatile csr_dwqe_illegal_drop_cnt_u dwqe_illegal_drop_cnt; /* 69C */ + volatile csr_dwqe_dbl_force_drop_no_api_u dwqe_dbl_force_drop_no_api; /* 6A0 */ + volatile csr_dwqe_dbl_force_drop_aft_api_u dwqe_dbl_force_drop_aft_api; /* 6A4 */ + volatile csr_aeq_fsm_dbg_state_u aeq_fsm_dbg_state; /* 6A8 */ + volatile csr_glb_ucpu_msi_func_idx_u glb_ucpu_msi_func_idx; /* 6B0 */ + volatile csr_glb_pcie_inbd_itf_wind_ctl_u glb_pcie_inbd_itf_wind_ctl; /* 6B4 */ + volatile csr_glb_pcie_inbd_itf_wind_cnt_u glb_pcie_inbd_itf_wind_cnt; /* 6B8 */ + volatile csr_glb_pcie_inbd_itf_wind_tlp_cnt_u glb_pcie_inbd_itf_wind_tlp_cnt; /* 6BC */ + volatile csr_glb_dbg_cnt_dbl_grp_en_u glb_dbg_cnt_dbl_grp_en; /* 6C0 */ + volatile csr_glb_dbl_crd_timer_cfg_u glb_dbl_crd_timer_cfg; /* 6C4 */ + volatile csr_glb_dbl_crd_cfg_port01_u glb_dbl_crd_cfg_port01; /* 6C8 */ + volatile csr_glb_dbl_crd_cfg_port23_u glb_dbl_crd_cfg_port23; /* 6CC */ + volatile csr_glb_dbl_crd_cnt_port0_u glb_dbl_crd_cnt_port0; /* 6D0 */ + volatile csr_glb_dbl_crd_cnt_port1_u glb_dbl_crd_cnt_port1; /* 6D4 */ + volatile csr_glb_dbl_crd_cnt_port2_u glb_dbl_crd_cnt_port2; /* 6D8 */ + volatile csr_glb_dbl_crd_cnt_port3_u glb_dbl_crd_cnt_port3; /* 6DC */ + volatile csr_cpath_enj_a_fatal_msk_u cpath_enj_a_fatal_msk; /* 700 */ + volatile csr_cpath_enj_a_nonfatal_msk_u cpath_enj_a_nonfatal_msk; /* 704 */ + volatile csr_cpath_enj_fifo_aful_th_u cpath_enj_fifo_aful_th; /* 708 */ + volatile csr_glb_dbg_cpath_enj_cnt0_u glb_dbg_cpath_enj_cnt0; /* 710 */ + volatile csr_glb_dbg_cpath_enj_cnt1_u glb_dbg_cpath_enj_cnt1; /* 714 */ + volatile csr_glb_dbg_cpath_enj_cnt2_u glb_dbg_cpath_enj_cnt2; /* 718 */ + volatile csr_glb_dbg_cpath_enj_cnt3_u glb_dbg_cpath_enj_cnt3; /* 71C */ + volatile csr_glb_dbg_cpath_enj_cnt4_u glb_dbg_cpath_enj_cnt4; /* 720 */ + volatile csr_glb_dbg_cpath_enj_cnt5_u glb_dbg_cpath_enj_cnt5; /* 724 */ + volatile csr_glb_dbg_cpath_enj_cnt6_u glb_dbg_cpath_enj_cnt6; /* 728 */ + volatile csr_glb_dbg_cpath_enj_cnt7_u glb_dbg_cpath_enj_cnt7; /* 72C */ + volatile csr_glb_dbg_cpath_enj_fifo0_u glb_dbg_cpath_enj_fifo0; /* 730 */ + volatile csr_glb_dbg_cpath_enj_fifo1_u glb_dbg_cpath_enj_fifo1; /* 734 */ + volatile csr_glb_dbg_cpath_enj_fifo2_u glb_dbg_cpath_enj_fifo2; /* 738 */ + volatile csr_glb_dbg_cpath_enj_fifo3_u glb_dbg_cpath_enj_fifo3; /* 73C */ + volatile csr_glb_dbg_cpath_enj_fifo4_u glb_dbg_cpath_enj_fifo4; /* 740 */ + volatile csr_glb_dbg_cpath_enj_fifo5_u glb_dbg_cpath_enj_fifo5; /* 744 */ + volatile csr_glb_dbg_cpath_enj_fifo6_u glb_dbg_cpath_enj_fifo6; /* 748 */ + volatile csr_glb_dbg_cpath_enj_fifo7_u glb_dbg_cpath_enj_fifo7; /* 74C */ + volatile csr_glb_dbg_cpath_enj_fifo8_u glb_dbg_cpath_enj_fifo8; /* 750 */ + volatile csr_glb_dbg_cpath_enj_fifo9_u glb_dbg_cpath_enj_fifo9; /* 754 */ + volatile csr_glb_dbg_cpath_ro0_u glb_dbg_cpath_ro0; /* 758 */ + volatile csr_glb_dbg_cpath_ro1_u glb_dbg_cpath_ro1; /* 75C */ + volatile csr_glb_dbg_cpath_ro2_u glb_dbg_cpath_ro2; /* 760 */ + volatile csr_glb_dbg_cpath_ro3_u glb_dbg_cpath_ro3; /* 764 */ + volatile csr_glb_dbg_cpath_ro4_u glb_dbg_cpath_ro4; /* 768 */ + volatile csr_glb_dbg_cpath_ro5_u glb_dbg_cpath_ro5; /* 76C */ + volatile csr_glb_dbg_cpath_ro6_u glb_dbg_cpath_ro6; /* 770 */ + volatile csr_glb_dbg_cpath_ro7_u glb_dbg_cpath_ro7; /* 774 */ + volatile csr_glb_dbg_cpath_ro8_u glb_dbg_cpath_ro8; /* 778 */ + volatile csr_glb_dbg_cpath_ro9_u glb_dbg_cpath_ro9; /* 77C */ + volatile csr_glb_dbg_cpath_ro10_u glb_dbg_cpath_ro10; /* 780 */ + volatile csr_glb_dbg_cpath_ro11_u glb_dbg_cpath_ro11; /* 784 */ + volatile csr_glb_dbg_cpath_ro12_u glb_dbg_cpath_ro12; /* 788 */ + volatile csr_glb_dbg_cpath_ro13_u glb_dbg_cpath_ro13; /* 78C */ + volatile csr_cpath_enj_pls_u cpath_enj_pls; /* 7A0 */ + volatile csr_ctrl_mem_ctrl_bus0_u ctrl_mem_ctrl_bus0; /* 7B0 */ + volatile csr_ctrl_mem_ctrl_bus1_u ctrl_mem_ctrl_bus1; /* 7B4 */ + volatile csr_ctrl_mem_ctrl_bus2_u ctrl_mem_ctrl_bus2; /* 7B8 */ + volatile csr_ctrl_mem_ctrl_bus3_u ctrl_mem_ctrl_bus3; /* 7BC */ + volatile csr_ctrl_mem_ctrl_bus4_u ctrl_mem_ctrl_bus4; /* 7C0 */ + volatile csr_ctrl_tcam_ctrl_bus0_u ctrl_tcam_ctrl_bus0; /* 7C4 */ +} S_dfx_glb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_glb_csr */ +extern volatile S_dfx_glb_csr_REGS_TYPE *gopdfx_glb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetGLB_DEBUG_CFG_glb_dbg_func_idx(unsigned int uglb_dbg_func_idx); +int iSetGLB_DEBUG_CFG_glb_dbg_bar_bitmap(unsigned int uglb_dbg_bar_bitmap); +int iSetGLB_DEBUG_RX_TLP_CNT_glb_dbg_rx_mwr_tlp_cnt(unsigned int uglb_dbg_rx_mwr_tlp_cnt); +int iSetGLB_DEBUG_RX_TLP_CNT_glb_dbg_rx_mrd_tlp_cnt(unsigned int uglb_dbg_rx_mrd_tlp_cnt); +int iSetGLB_DEBUG_RX_DBL_CNT_glb_dbg_rx_dbl_tlp_cnt(unsigned int uglb_dbg_rx_dbl_tlp_cnt); +int iSetGLB_DEBUG_RX_DWQE_CNT_glb_dbg_rx_dwqe_tlp_cnt(unsigned int uglb_dbg_rx_dwqe_tlp_cnt); +int iSetGLB_PORT0_NPCPL_TLP_CNT_cpi_port0_tx_cpl_cnt(unsigned int ucpi_port0_tx_cpl_cnt); +int iSetGLB_PORT0_NPCPL_TLP_CNT_cpi_port0_rx_np_cnt(unsigned int ucpi_port0_rx_np_cnt); +int iSetGLB_PORT1_NPCPL_TLP_CNT_cpi_port1_tx_cpl_cnt(unsigned int ucpi_port1_tx_cpl_cnt); +int iSetGLB_PORT1_NPCPL_TLP_CNT_cpi_port1_rx_np_cnt(unsigned int ucpi_port1_rx_np_cnt); +int iSetGLB_PORT2_NPCPL_TLP_CNT_cpi_port2_tx_cpl_cnt(unsigned int ucpi_port2_tx_cpl_cnt); +int iSetGLB_PORT2_NPCPL_TLP_CNT_cpi_port2_rx_np_cnt(unsigned int ucpi_port2_rx_np_cnt); +int iSetGLB_PORT3_NPCPL_TLP_CNT_cpi_port3_tx_cpl_cnt(unsigned int ucpi_port3_tx_cpl_cnt); +int iSetGLB_PORT3_NPCPL_TLP_CNT_cpi_port3_rx_np_cnt(unsigned int ucpi_port3_rx_np_cnt); +int iSetGLB_PORT4_NPCPL_TLP_CNT_cpi_port4_tx_cpl_cnt(unsigned int ucpi_port4_tx_cpl_cnt); +int iSetGLB_PORT4_NPCPL_TLP_CNT_cpi_port4_rx_np_cnt(unsigned int ucpi_port4_rx_np_cnt); +int iSetDFX_ICTL_RX_OK_CNT_dfx_ictl_sop_cnt(unsigned int udfx_ictl_sop_cnt); +int iSetDFX_ICTL_RX_OK_CNT_dfx_ictl_ok_cnt(unsigned int udfx_ictl_ok_cnt); +int iSetDFX_ICTL_RX_EOP_CNT_dfx_ictl_vld_cnt(unsigned int udfx_ictl_vld_cnt); +int iSetDFX_ICTL_RX_EOP_CNT_dfx_ictl_eop_cnt(unsigned int udfx_ictl_eop_cnt); +int iSetDFX_ICTL_SOP_EOP_CNT_ictl_osch_tx_cpl_cnt(unsigned int uictl_osch_tx_cpl_cnt); +int iSetDFX_ICTL_SOP_EOP_CNT_dfx_ictl_sop_eop_cnt(unsigned int udfx_ictl_sop_eop_cnt); +int iSetDFX_ICTL_MPU_ACC_CNT_mpu_apb_rd_cnt(unsigned int umpu_apb_rd_cnt); +int iSetDFX_ICTL_MPU_ACC_CNT_mpu_apb_wr_cnt(unsigned int umpu_apb_wr_cnt); +int iSetDFX_ICTL_IPUSH_TLP_CNT_ictl_dwqe_tlp_cnt(unsigned int uictl_dwqe_tlp_cnt); +int iSetDFX_ICTL_IPUSH_TLP_CNT_ictl_ipush_tlp_cnt(unsigned int uictl_ipush_tlp_cnt); +int iSetDFX_ICTL_VIO_TLP_CNT_dfx_ictl_rx_mem_cnt(unsigned int udfx_ictl_rx_mem_cnt); +int iSetDFX_ICTL_VIO_TLP_CNT_ictl_vio_tlp_cnt(unsigned int uictl_vio_tlp_cnt); +int iSetDFX_ICTL_RX_IO_CNT_dfx_ictl_rx_rom_cnt(unsigned int udfx_ictl_rx_rom_cnt); +int iSetDFX_ICTL_RX_IO_CNT_dfx_ictl_rx_io_cnt(unsigned int udfx_ictl_rx_io_cnt); +int iSetDFX_ICTL_RX_TLP_DROP_CNT_dfx_ictl_rx_uns_np_cnt(unsigned int udfx_ictl_rx_uns_np_cnt); +int iSetDFX_ICTL_RX_TLP_DROP_CNT_dfx_ictl_rx_tlp_drop_cnt(unsigned int udfx_ictl_rx_tlp_drop_cnt); +int iSetGLB_CPI_PORT_BP_EN_CFG_cpi_port_bp_en_cfg(unsigned int ucpi_port_bp_en_cfg); +int iSetDFX_ICTL_FATAL_MSK0_dfx_ictl_fatal_msk95_64(unsigned int udfx_ictl_fatal_msk95_64); +int iSetDFX_ICTL_FATAL_MSK1_dfx_ictl_fatal_msk63_32(unsigned int udfx_ictl_fatal_msk63_32); +int iSetDFX_ICTL_FATAL_MSK2_dfx_ictl_fatal_msk31_0(unsigned int udfx_ictl_fatal_msk31_0); +int iSetDFX_ICTL_NONFATAL_MSK0_dfx_ictl_nonfatal_msk95_64(unsigned int udfx_ictl_nonfatal_msk95_64); +int iSetDFX_ICTL_NONFATAL_MSK1_dfx_ictl_nonfatal_msk63_32(unsigned int udfx_ictl_nonfatal_msk63_32); +int iSetDFX_ICTL_NONFATAL_MSK2_dfx_ictl_nonfatal_msk31_0(unsigned int udfx_ictl_nonfatal_msk31_0); +int iSetDFX_ICTL_ERR_PLS0_dfx_ictl_err_pls95_64(unsigned int udfx_ictl_err_pls95_64); +int iSetDFX_ICTL_ERR_PLS1_dfx_ictl_err_pls63_32(unsigned int udfx_ictl_err_pls63_32); +int iSetDFX_ICTL_ERR_PLS2_dfx_ictl_err_pls31_0(unsigned int udfx_ictl_err_pls31_0); +int iSetGLB_CPI_BP_WATCH_STS_glb_cpi_bp_watch_sts(unsigned int uglb_cpi_bp_watch_sts); +int iSetGLB_CPI_BP_WATCH_WINDOW_glb_cpi_bp_watch_window(unsigned int uglb_cpi_bp_watch_window); +int iSetGLB_CPI_BP_WATCH_BITMAP_glb_cpi_bp_watch_bitmap(unsigned int uglb_cpi_bp_watch_bitmap); +int iSetGLB_CPI_BP_WATCH_START_glb_cpi_bp_watch_start(unsigned int uglb_cpi_bp_watch_start); +int iSetGLB_CPI_BP_WATCH_CNT_glb_cpi_bp_watch_cnt(unsigned int uglb_cpi_bp_watch_cnt); +int iSetGLB_CSR_TIMEOUT_CNT_glb_csr_timeout_cnt(unsigned int uglb_csr_timeout_cnt); +int iSetGLB_CSR_TIMEOUT_CNT_glb_non_csr_timeout_cnt(unsigned int uglb_non_csr_timeout_cnt); +int iSetDWQE_API_NO_ENOUGH_DATA_dwqe_api_no_enough_data(unsigned int udwqe_api_no_enough_data); +int iSetDWQE_DBL_NO_ENOUGH_DATA_dwqe_dbl_no_enough_data(unsigned int udwqe_dbl_no_enough_data); +int iSetNORM_DBL_DROP_CNT_norm_dbl_illegal_drop_cnt(unsigned int unorm_dbl_illegal_drop_cnt); +int iSetNORM_DBL_TX_CNT_norm_dbl_tx_cnt(unsigned int unorm_dbl_tx_cnt); +int iSetDWQE_DBL_TX_CNT_dwqe_dbl_tx_cnt(unsigned int udwqe_dbl_tx_cnt); +int iSetDWQE_API_TX_CNT_dwqe_api_tx_cnt(unsigned int udwqe_api_tx_cnt); +int iSetDWQE_BUF_BP_MSK_dwqe_buf_bp_sts(unsigned int udwqe_buf_bp_sts); +int iSetDWQE_BUF_BP_MSK_dwqe_buf_bp_en(unsigned int udwqe_buf_bp_en); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port3(unsigned int udwqe_buf_cnt_port3); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port2(unsigned int udwqe_buf_cnt_port2); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port1(unsigned int udwqe_buf_cnt_port1); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port0(unsigned int udwqe_buf_cnt_port0); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port3(unsigned int udwqe_buf_bp_on_port3); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port2(unsigned int udwqe_buf_bp_on_port2); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port1(unsigned int udwqe_buf_bp_on_port1); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port0(unsigned int udwqe_buf_bp_on_port0); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port3(unsigned int udwqe_buf_bp_off_port3); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port2(unsigned int udwqe_buf_bp_off_port2); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port1(unsigned int udwqe_buf_bp_off_port1); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port0(unsigned int udwqe_buf_bp_off_port0); +int iSetDWQE_REQ_BUF_BGN_dwqe_req_buf_bgn(unsigned int udwqe_req_buf_bgn); +int iSetDWQE_DROPPING_IN_TX_dwqe_dropping_in_tx(unsigned int udwqe_dropping_in_tx); +int iSetDWQE_DROPPING_NO_BUF_dwqe_dropping_no_buf(unsigned int udwqe_dropping_no_buf); +int iSetDWQE_DBL_WITHOUT_API_dwqe_dbl_without_api(unsigned int udwqe_dbl_without_api); +int iSetDWQE_TX_DBL_AFTER_API_dwqe_tx_dbl_after_api(unsigned int udwqe_tx_dbl_after_api); +int iSetDWQE_NO_DBL_AFTER_API_dwqe_no_dbl_after_api(unsigned int udwqe_no_dbl_after_api); +int iSetDWQE_BUF_OVERWRITE_DROP_CNT_dwqe_buf_overwrite_drop_cnt(unsigned int udwqe_buf_overwrite_drop_cnt); +int iSetDWQE_BUF_AGING_DROP_CNT_dwqe_buf_aging_drop_cnt(unsigned int udwqe_buf_aging_drop_cnt); +int iSetDWQE_TX_REQ_FIFO_PUSH_CNT_dwqe_tx_req_fifo_push_cnt(unsigned int udwqe_tx_req_fifo_push_cnt); +int iSetDWQE_TX_REQ_FIFO_POP_CNT_dwqe_tx_req_fifo_pop_cnt(unsigned int udwqe_tx_req_fifo_pop_cnt); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_tx_req_fifo_sts(unsigned int udwqe_tx_req_fifo_sts); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_tx_req_fifo_overflow(unsigned int udwqe_tx_req_fifo_overflow); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_buf_alc_cnt(unsigned int udwqe_buf_alc_cnt); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_tx_req_fifo_cnt(unsigned int udwqe_tx_req_fifo_cnt); +int iSetDWQE_DROPPING_INVLD_dwqe_dropping_invld(unsigned int udwqe_dropping_invld); +int iSetDWQE_SW_FORCE_DROP_dwqe_sw_force_drop(unsigned int udwqe_sw_force_drop); +int iSetICTL_DBL_REQ_SOP_NULL_ictl_dbl_req_sop_null(unsigned int uictl_dbl_req_sop_null); +int iSetCPI_PCIE_MB_AEQE_TO_MPU_CNT_glb_pcie_mb_aeqe_to_mpu_cnt(unsigned int uglb_pcie_mb_aeqe_to_mpu_cnt); +int iSetDFX_RX_DWQE_DDB_CNT0_dfx_rx_dwqe_ddb1_cnt(unsigned int udfx_rx_dwqe_ddb1_cnt); +int iSetDFX_RX_DWQE_DDB_CNT0_dfx_rx_dwqe_ddb0_cnt(unsigned int udfx_rx_dwqe_ddb0_cnt); +int iSetDFX_RX_DWQE_DDB_CNT1_dfx_rx_dwqe_ddb3_cnt(unsigned int udfx_rx_dwqe_ddb3_cnt); +int iSetDFX_RX_DWQE_DDB_CNT1_dfx_rx_dwqe_ddb2_cnt(unsigned int udfx_rx_dwqe_ddb2_cnt); +int iSetDFX_RX_DBL_SRV_CNT0_dfx_rx_dbl_srv1_cnt(unsigned int udfx_rx_dbl_srv1_cnt); +int iSetDFX_RX_DBL_SRV_CNT0_dfx_rx_dbl_srv0_cnt(unsigned int udfx_rx_dbl_srv0_cnt); +int iSetDFX_RX_DBL_SRV_CNT1_dfx_rx_dbl_srv3_cnt(unsigned int udfx_rx_dbl_srv3_cnt); +int iSetDFX_RX_DBL_SRV_CNT1_dfx_rx_dbl_srv2_cnt(unsigned int udfx_rx_dbl_srv2_cnt); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg0_srv_type(unsigned int uglb_dfx_cfg0_srv_type); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg1_srv_type(unsigned int uglb_dfx_cfg1_srv_type); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg2_srv_type(unsigned int uglb_dfx_cfg2_srv_type); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg3_srv_type(unsigned int uglb_dfx_cfg3_srv_type); +int iSetAEQ_CI_SW_WR_CNT_aeq_ci_sw_wr_cnt(unsigned int uaeq_ci_sw_wr_cnt); +int iSetAEQ_TX_INT_REQ_CNT_aeq_tx_int_req_cnt(unsigned int uaeq_tx_int_req_cnt); +int iSetCPI_IPUSH_CSR_WR_PCIE_CNT_glb_ipush_csr_wr_pcie_cnt(unsigned int uglb_ipush_csr_wr_pcie_cnt); +int iSetCPI_IPUSH_CSR_WR_UCPU_CNT_glb_ipush_csr_wr_ucpu_cnt(unsigned int uglb_ipush_csr_wr_ucpu_cnt); +int iSetCPI_IPUSH_CSR_RD_PCIE_CNT_glb_ipush_csr_rd_pcie_cnt(unsigned int uglb_ipush_csr_rd_pcie_cnt); +int iSetCPI_IPUSH_CSR_RD_UCPU_CNT_glb_ipush_csr_rd_ucpu_cnt(unsigned int uglb_ipush_csr_rd_ucpu_cnt); +int iSetCPI_IPUSH_OSCH_CPL_CNT_glb_ipush_osch_cpl_cnt(unsigned int uglb_ipush_osch_cpl_cnt); +int iSetCPI_IPUSH_ICTL_CPL_CNT_glb_ipush_ictl_cpl_cnt(unsigned int uglb_ipush_ictl_cpl_cnt); +int iSetCPI_IPUSH_APICTL_REQ_CNT_glb_ipush_apictl_req_cnt(unsigned int uglb_ipush_apictl_req_cnt); +int iSetCPI_PCIE_MB_AEQE_TO_DST_CNT_glb_pcie_mb_aeqe_to_dst_cnt(unsigned int uglb_pcie_mb_aeqe_to_dst_cnt); +int iSetCPI_PCIE_MB_AEQE_TO_SRC_CNT_glb_pcie_mb_aeqe_to_src_cnt(unsigned int uglb_pcie_mb_aeqe_to_src_cnt); +int iSetCPI_PCIE_MB_STAT_TO_SRC_CNT_glb_pcie_mb_stat_to_src_cnt(unsigned int uglb_pcie_mb_stat_to_src_cnt); +int iSetCPI_UCPU_MB_AEQE_TO_DST_CNT_glb_ucpu_mb_aeqe_to_dst_cnt(unsigned int uglb_ucpu_mb_aeqe_to_dst_cnt); +int iSetCPI_IPUSH_CSR_AEQ_REQ_CNT_glb_ipush_csr_aeq_req_cnt(unsigned int uglb_ipush_csr_aeq_req_cnt); +int iSetCPI_IPUSH_CSR_CEQ_REQ_CNT_glb_ipush_csr_ceq_req_cnt(unsigned int uglb_ipush_csr_ceq_req_cnt); +int iSetCPI_IPUSH_CSR_API_REQ_CNT_glb_ipush_csr_api_req_cnt(unsigned int uglb_ipush_csr_api_req_cnt); +int iSetCPI_IPUSH_CSR_INTCTL_REQ_CNT_glb_ipush_csr_intctl_req_cnt(unsigned int uglb_ipush_csr_intctl_req_cnt); +int iSetCPI_IPUSH_UPITF_CLP_REQ_CNT_glb_ipush_upitf_clp_req_cnt(unsigned int uglb_ipush_upitf_clp_req_cnt); +int iSetCPI_RAM_ECC_INJ_ERR0_glb_cpi_ecc_inj_req0(unsigned int uglb_cpi_ecc_inj_req0); +int iSetCPI_RAM_ECC_INJ_ERR1_glb_cpi_ecc_inj_req1(unsigned int uglb_cpi_ecc_inj_req1); +int iSetCPI_RAM_ECC_INJ_ERR2_glb_cpi_ecc_inj_req2(unsigned int uglb_cpi_ecc_inj_req2); +int iSetCPI_RAM_ECC_INJ_ERR3_glb_cpi_ecc_inj_req3(unsigned int uglb_cpi_ecc_inj_req3); +int iSetCPI_RAM_ECC_MERR0_glb_cpi_ecc_merr0(unsigned int uglb_cpi_ecc_merr0); +int iSetCPI_RAM_ECC_MERR1_glb_cpi_ecc_merr1(unsigned int uglb_cpi_ecc_merr1); +int iSetCPI_RAM_ECC_ERR0_glb_cpi_ecc_err0(unsigned int uglb_cpi_ecc_err0); +int iSetCPI_RAM_ECC_ERR1_glb_cpi_ecc_err1(unsigned int uglb_cpi_ecc_err1); +int iSetCPI_RAM_ECC_ERR_ADDR0_glb_cpi_ecc_err_addr0(unsigned int uglb_cpi_ecc_err_addr0); +int iSetCPI_RAM_ECC_ERR_ADDR1_glb_cpi_ecc_err_addr1(unsigned int uglb_cpi_ecc_err_addr1); +int iSetCPI_RAM_ECC_ERR_ADDR2_glb_cpi_ecc_err_addr2(unsigned int uglb_cpi_ecc_err_addr2); +int iSetCPI_RAM_ECC_ERR_ADDR3_glb_cpi_ecc_err_addr3(unsigned int uglb_cpi_ecc_err_addr3); +int iSetIPUSH_RESERVED0_ipush_resved0(unsigned int uipush_resved0); +int iSetIPUSH_RESERVED1_ipush_resved1(unsigned int uipush_resved1); +int iSetIPUSH_RESERVED2_ipush_resved2(unsigned int uipush_resved2); +int iSetIPUSH_RESERVED3_ipush_resved3(unsigned int uipush_resved3); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_cmisc_uncrt_err_code(unsigned int uglb_cpi_cmisc_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_cpath_dma_uncrt_err_code(unsigned int uglb_cpi_cpath_dma_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_dtif_uncrt_err_code(unsigned int uglb_cpi_dtif_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_ictl_uncrt_err_code(unsigned int uglb_cpi_ictl_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_qmap_uncrt_err_code(unsigned int uglb_cpi_qmap_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_apictl_uncrt_err_code(unsigned int uglb_cpi_apictl_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_dpath_i_uncrt_err_code(unsigned int uglb_cpi_dpath_i_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_dpath_o_uncrt_err_code(unsigned int uglb_cpi_dpath_o_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE1_glb_cpi_ipush_uncrt_err_code(unsigned int uglb_cpi_ipush_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE1_glb_cpi_cpath_uncrt_err_code(unsigned int uglb_cpi_cpath_uncrt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_cmisc_crt_err_code(unsigned int uglb_cpi_cmisc_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_cpath_dma_crt_err_code(unsigned int uglb_cpi_cpath_dma_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_dtif_crt_err_code(unsigned int uglb_cpi_dtif_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_ictl_crt_err_code(unsigned int uglb_cpi_ictl_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_qmap_crt_err_code(unsigned int uglb_cpi_qmap_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_apictl_crt_err_code(unsigned int uglb_cpi_apictl_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_dpath_i_crt_err_code(unsigned int uglb_cpi_dpath_i_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_dpath_o_crt_err_code(unsigned int uglb_cpi_dpath_o_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE1_glb_cpi_ipush_crt_err_code(unsigned int uglb_cpi_ipush_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE1_glb_cpi_cpath_crt_err_code(unsigned int uglb_cpi_cpath_crt_err_code); +int iSetDWQE_BUF_DBG0_dwqe_buf_dbg_src_tag_l(unsigned int udwqe_buf_dbg_src_tag_l); +int iSetDWQE_BUF_DBG0_dwqe_buf_dbg_status(unsigned int udwqe_buf_dbg_status); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_exp_qw_num(unsigned int udwqe_buf_dbg_exp_qw_num); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_rx_qw_cnt(unsigned int udwqe_buf_dbg_rx_qw_cnt); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_no_dbl(unsigned int udwqe_buf_dbg_no_dbl); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_aging_flag(unsigned int udwqe_buf_dbg_aging_flag); +int iSetDWQE_BUF_DBG2_dwqe_buf_dbg_idx(unsigned int udwqe_buf_dbg_idx); +int iSetDWQE_BUF_DBG2_dwqe_buf_dbg_watch_en(unsigned int udwqe_buf_dbg_watch_en); +int iSetDWQE_BUF_DBG2_dwqe_buf_dbg_force_ivld(unsigned int udwqe_buf_dbg_force_ivld); +int iSetDWQE_BUG_DBG3_dwqe_buf_dbg_host_addr(unsigned int udwqe_buf_dbg_host_addr); +int iSetGLB_MB_GRP_TX_REQ_H_glb_mb_grp_tx_req_h(unsigned int uglb_mb_grp_tx_req_h); +int iSetGLB_MB_GRP_TX_REQ_L_glb_mb_grp_tx_req_l(unsigned int uglb_mb_grp_tx_req_l); +int iSetGLB_MB_GRP_GRANT_H_glb_mb_grp_grant_h(unsigned int uglb_mb_grp_grant_h); +int iSetGLB_MB_GRP_GRANT_L_glb_mb_grp_grant_l(unsigned int uglb_mb_grp_grant_l); +int iSetICTL_IPUSH_SOP_CNT_ictl_ipush_sop_cnt(unsigned int uictl_ipush_sop_cnt); +int iSetICTL_IPUSH_EOP_CNT_ictl_ipush_eop_cnt(unsigned int uictl_ipush_eop_cnt); +int iSetGLB_MB_IN_GRP_TX_REQ_H_glb_mb_in_grp_tx_req_h(unsigned int uglb_mb_in_grp_tx_req_h); +int iSetGLB_MB_IN_GRP_TX_REQ_L_glb_mb_in_grp_tx_req_l(unsigned int uglb_mb_in_grp_tx_req_l); +int iSetGLB_MB_IN_GRP_GRANT_H_glb_mb_in_grp_grant_h(unsigned int uglb_mb_in_grp_grant_h); +int iSetGLB_MB_IN_GRP_GRANT_L_glb_mb_in_grp_grant_l(unsigned int uglb_mb_in_grp_grant_l); +int iSetGLB_MB_TX_START_CNT_glb_mb_tx_start_cnt(unsigned int uglb_mb_tx_start_cnt); +int iSetGLB_MB_TX_ILLEGAL_CNT_glb_mb_tx_illegal_cnt(unsigned int uglb_mb_tx_illegal_cnt); +int iSetGLB_MB_TX_ILLEGAL_CODE_glb_mb_tx_illegal_code(unsigned int uglb_mb_tx_illegal_code); +int iSetGLB_MB_FSM_STATE_glb_mb_buf_fsm_state(unsigned int uglb_mb_buf_fsm_state); +int iSetGLB_MB_FSM_STATE_glb_mb_csr_ram_fsm_state(unsigned int uglb_mb_csr_ram_fsm_state); +int iSetGLB_MB_FSM_STATE_glb_mb_tx_fsm_state(unsigned int uglb_mb_tx_fsm_state); +int iSetGLB_MB_FSM_STATE_glb_mb_rr_fsm_state(unsigned int uglb_mb_rr_fsm_state); +int iSetICTL_INBD_FIFO_STS_ictl_inbd_fifo_st(unsigned int uictl_inbd_fifo_st); +int iSetICTL_DBL_SOP_CNT_ictl_dbl_sop_cnt(unsigned int uictl_dbl_sop_cnt); +int iSetICTL_DBL_EOP_CNT_ictl_dbl_eop_cnt(unsigned int uictl_dbl_eop_cnt); +int iSetDWQE_DROP_NO_WR_BUF_CNT_dwqe_drop_no_wr_buf_cnt(unsigned int udwqe_drop_no_wr_buf_cnt); +int iSetDWQE_WR_BUF_COMPLETE_CNT_dwqe_wr_buf_complete_cnt(unsigned int udwqe_wr_buf_complete_cnt); +int iSetNORM_DBL_RX_CNT_norm_dbl_rx_cnt(unsigned int unorm_dbl_rx_cnt); +int iSetNORM_DBL_FORCE_DROP_norm_dbl_force_drop(unsigned int unorm_dbl_force_drop); +int iSetDWQE_RX_BUF_BGN_dwqe_rx_buf_bgn(unsigned int udwqe_rx_buf_bgn); +int iSetDWQE_ILLEGAL_DROP_CNT_dwqe_illegal_drop(unsigned int udwqe_illegal_drop); +int iSetDWQE_DBL_FORCE_DROP_NO_API_dwqe_dbl_force_drop_no_api(unsigned int udwqe_dbl_force_drop_no_api); +int iSetDWQE_DBL_FORCE_DROP_AFT_API_dwqe_dbl_force_drop_aft_api(unsigned int udwqe_dbl_force_drop_aft_api); +int iSetAEQ_FSM_DBG_STATE_aeq_dbg_status(unsigned int uaeq_dbg_status); +int iSetGLB_UCPU_MSI_FUNC_IDX_glb_ucpu_msi_func_idx(unsigned int uglb_ucpu_msi_func_idx); +int iSetGLB_PCIE_INBD_ITF_WIND_CTL_pcie_inbd_itf_wind_16t(unsigned int upcie_inbd_itf_wind_16t); +int iSetGLB_PCIE_INBD_ITF_WIND_CTL_pcie_inbd_itf_wind_mode(unsigned int upcie_inbd_itf_wind_mode); +int iSetGLB_PCIE_INBD_ITF_WIND_CTL_pcie_inbd_itf_wind_start(unsigned int upcie_inbd_itf_wind_start); +int iSetGLB_PCIE_INBD_ITF_WIND_CNT_pcie_inbd_wind_detect_cnt(unsigned int upcie_inbd_wind_detect_cnt); +int iSetGLB_PCIE_INBD_ITF_WIND_CNT_pcie_inbd_wind_detect_done(unsigned int upcie_inbd_wind_detect_done); +int iSetGLB_PCIE_INBD_ITF_WIND_TLP_CNT_pcie_inbd_wind_detect_tlp_cnt(unsigned int upcie_inbd_wind_detect_tlp_cnt); +int iSetGLB_DBG_CNT_DBL_GRP_EN_glb_dbg_cnt_dbl_grp_en(unsigned int uglb_dbg_cnt_dbl_grp_en); +int iSetGLB_DBL_CRD_TIMER_CFG_glb_dbl_crd_timer_cfg(unsigned int uglb_dbl_crd_timer_cfg); +int iSetGLB_DBL_CRD_CFG_PORT01_glb_dbl_crd_cfg_port1(unsigned int uglb_dbl_crd_cfg_port1); +int iSetGLB_DBL_CRD_CFG_PORT01_glb_dbl_crd_cfg_port0(unsigned int uglb_dbl_crd_cfg_port0); +int iSetGLB_DBL_CRD_CFG_PORT23_glb_dbl_crd_cfg_port3(unsigned int uglb_dbl_crd_cfg_port3); +int iSetGLB_DBL_CRD_CFG_PORT23_glb_dbl_crd_cfg_port2(unsigned int uglb_dbl_crd_cfg_port2); +int iSetGLB_DBL_CRD_CNT_PORT0_glb_dbl_crd_cnt_port0(unsigned int uglb_dbl_crd_cnt_port0); +int iSetGLB_DBL_CRD_CNT_PORT1_glb_dbl_crd_cnt_port1(unsigned int uglb_dbl_crd_cnt_port1); +int iSetGLB_DBL_CRD_CNT_PORT2_glb_dbl_crd_cnt_port2(unsigned int uglb_dbl_crd_cnt_port2); +int iSetGLB_DBL_CRD_CNT_PORT3_glb_dbl_crd_cnt_port3(unsigned int uglb_dbl_crd_cnt_port3); +int iSetCPATH_ENJ_A_FATAL_MSK_cpath_enj_a_fatal_msk(unsigned int ucpath_enj_a_fatal_msk); +int iSetCPATH_ENJ_A_NONFATAL_MSK_cpath_enj_a_nonfatal_msk(unsigned int ucpath_enj_a_nonfatal_msk); +int iSetCPATH_ENJ_FIFO_AFUL_TH_cfg_icpl_rdr_fifo_th(unsigned int ucfg_icpl_rdr_fifo_th); +int iSetCPATH_ENJ_FIFO_AFUL_TH_oubd_pi_afifo_aful_gap_cpi(unsigned int uoubd_pi_afifo_aful_gap_cpi); +int iSetCPATH_ENJ_FIFO_AFUL_TH_oubd_pe_afifo_aful_gap_cpi(unsigned int uoubd_pe_afifo_aful_gap_cpi); +int iSetGLB_DBG_CPATH_ENJ_CNT0_cpath_tile_cnt(unsigned int ucpath_tile_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT0_pure_ack_cnt(unsigned int upure_ack_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT1_cpath_octl_cnt(unsigned int ucpath_octl_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT1_cpath_rsv_cnt(unsigned int ucpath_rsv_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT2_cpath_octl_api10_cnt(unsigned int ucpath_octl_api10_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT2_cpath_octl_api11_cnt(unsigned int ucpath_octl_api11_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT3_cpath_octl_api08_cnt(unsigned int ucpath_octl_api08_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT3_cpath_octl_api09_cnt(unsigned int ucpath_octl_api09_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT4_cpath_octl_api06_cnt(unsigned int ucpath_octl_api06_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT4_cpath_octl_api07_cnt(unsigned int ucpath_octl_api07_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT5_cpath_octl_api04_cnt(unsigned int ucpath_octl_api04_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT5_cpath_octl_api05_cnt(unsigned int ucpath_octl_api05_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT6_cpath_octl_api02_cnt(unsigned int ucpath_octl_api02_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT6_cpath_octl_api03_cnt(unsigned int ucpath_octl_api03_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT7_cpath_octl_api00_cnt(unsigned int ucpath_octl_api00_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT7_cpath_octl_api01_cnt(unsigned int ucpath_octl_api01_cnt); +int iSetGLB_DBG_CPATH_ENJ_FIFO0_cpath_oubd_afifo_pe(unsigned int ucpath_oubd_afifo_pe); +int iSetGLB_DBG_CPATH_ENJ_FIFO1_cpath_oubd_sfifo_pe(unsigned int ucpath_oubd_sfifo_pe); +int iSetGLB_DBG_CPATH_ENJ_FIFO2_cpath_oubd_sfifo_pi(unsigned int ucpath_oubd_sfifo_pi); +int iSetGLB_DBG_CPATH_ENJ_FIFO3_cpath_oubd_sfifo_rsp(unsigned int ucpath_oubd_sfifo_rsp); +int iSetGLB_DBG_CPATH_ENJ_FIFO4_cpath_sfifo_0sm(unsigned int ucpath_sfifo_0sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO5_cpath_sfifo_1sm(unsigned int ucpath_sfifo_1sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO6_cpath_sfifo_2sm(unsigned int ucpath_sfifo_2sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO7_cpath_sfifo_3sm(unsigned int ucpath_sfifo_3sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO8_cpath_sfifo_tile(unsigned int ucpath_sfifo_tile); +int iSetGLB_DBG_CPATH_ENJ_FIFO9_cpath_sfifo_mqm(unsigned int ucpath_sfifo_mqm); +int iSetGLB_DBG_CPATH_RO0_cpath_out_a(unsigned int ucpath_out_a); +int iSetGLB_DBG_CPATH_RO1_cpath_out_b(unsigned int ucpath_out_b); +int iSetGLB_DBG_CPATH_RO2_cpath_out_c(unsigned int ucpath_out_c); +int iSetGLB_DBG_CPATH_RO3_cpath_out_d(unsigned int ucpath_out_d); +int iSetGLB_DBG_CPATH_RO4_cpath_out_e(unsigned int ucpath_out_e); +int iSetGLB_DBG_CPATH_RO5_cpath_out_f(unsigned int ucpath_out_f); +int iSetGLB_DBG_CPATH_RO6_cpath_out_g(unsigned int ucpath_out_g); +int iSetGLB_DBG_CPATH_RO7_cpath_out_h(unsigned int ucpath_out_h); +int iSetGLB_DBG_CPATH_RO8_cpath_out_0sm(unsigned int ucpath_out_0sm); +int iSetGLB_DBG_CPATH_RO9_cpath_out_1sm(unsigned int ucpath_out_1sm); +int iSetGLB_DBG_CPATH_RO10_cpath_out_2sm(unsigned int ucpath_out_2sm); +int iSetGLB_DBG_CPATH_RO11_cpath_out_3sm(unsigned int ucpath_out_3sm); +int iSetGLB_DBG_CPATH_RO12_cpath_out_tile(unsigned int ucpath_out_tile); +int iSetGLB_DBG_CPATH_RO13_cpath_out_mqm(unsigned int ucpath_out_mqm); +int iSetCPATH_ENJ_PLS_cpath_enj_pls(unsigned int ucpath_enj_pls); +int iSetCTRL_MEM_CTRL_BUS0_ctrl_mem_ctrl_bus133_128(unsigned int uctrl_mem_ctrl_bus133_128); +int iSetCTRL_MEM_CTRL_BUS1_ctrl_mem_ctrl_bus127_96(unsigned int uctrl_mem_ctrl_bus127_96); +int iSetCTRL_MEM_CTRL_BUS2_ctrl_mem_ctrl_bus95_64(unsigned int uctrl_mem_ctrl_bus95_64); +int iSetCTRL_MEM_CTRL_BUS3_ctrl_mem_ctrl_bus63_32(unsigned int uctrl_mem_ctrl_bus63_32); +int iSetCTRL_MEM_CTRL_BUS4_ctrl_mem_ctrl_bus31_0(unsigned int uctrl_mem_ctrl_bus31_0); +int iSetCTRL_TCAM_CTRL_BUS0_ctrl_tcam_ctrl_bus9_0(unsigned int uctrl_tcam_ctrl_bus9_0); + +/* Define the union csr_dtif_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_csr_acc_af_th : 4; /* [3:0] */ + u32 dtif_tx_tlp_af_th : 4; /* [7:4] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo_af_th_u; + +/* Define the union csr_dtif_dfx_arb_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_gnt_ff : 14; /* [13:0] */ + u32 dtif_tx_gnt_vld : 1; /* [14] */ + u32 dtif_tx_is_busy : 1; /* [15] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_arb_ro_u; + +/* Define the union csr_dtif_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_csr_acc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_0_u; + +/* Define the union csr_dtif_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_arb_sel_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_1_u; + +/* Define the union csr_dtif_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_2_u; + +/* Define the union csr_dtif_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_3_u; + +/* Define the union csr_dtif_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_4_u; + +/* Define the union csr_dtif_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_5_u; + +/* Define the union csr_dtif_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_6_u; + +/* Define the union csr_dtif_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_7_u; + +/* Define the union csr_dtif_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_8_u; + +/* Define the union csr_dtif_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_9_u; + +/* Define the union csr_dtif_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_10_u; + +/* Define the union csr_dtif_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_11_u; + +/* Define the union csr_dtif_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_12_u; + +/* Define the union csr_dtif_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_13_u; + +/* Define the union csr_dtif_dfx_cnt_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_dtif2ctif_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_14_u; + +/* Define the union csr_dtif_dfx_cnt_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_dtif2ctif_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_15_u; + +/* Define the union csr_dtif_dfx_cnt_16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_16_u; + +/* Define the union csr_dtif_dfx_cnt_17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_17_u; + +/* Define the union csr_dtif_dfx_cnt_18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_18_u; + +/* Define the union csr_dtif_dfx_cnt_19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_19_u; + +/* Define the union csr_dtif_dfx_cnt_20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_20_u; + +/* Define the union csr_dtif_dfx_cnt_21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_21_u; + +/* Define the union csr_dtif_dfx_cnt_22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_22_u; + +/* Define the union csr_dtif_dfx_cnt_23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_23_u; + +/* Define the union csr_dtif_dfx_cnt_24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_24_u; + +/* Define the union csr_dtif_dfx_cnt_25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_25_u; + +/* Define the union csr_dtif_dfx_cnt_26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_wr_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_26_u; + +/* Define the union csr_dtif_dfx_cnt_27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_wr_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_27_u; + +/* Define the union csr_dtif_dfx_cnt_28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_nl2_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_28_u; + +/* Define the union csr_dtif_dfx_cnt_29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_nl2_rsp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_29_u; + +/* Define the union csr_dtif_dfx_cnt_30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mpu_tlp_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_30_u; + +/* Define the union csr_dtif_dfx_cnt_31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_api_chn_tlp_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_31_u; + +/* Define the union csr_dtif_dfx_cnt_32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nl2_cmd_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_32_u; + +/* Define the union csr_dtif_dfx_cnt_33_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mpu_csr_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_33_u; + +/* Define the union csr_dtif_dfx_cnt_34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_api_chn_tlp_abrt_cnt : 16; /* [15:0] */ + u32 rx_mpu_tlp_abrt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_34_u; + +/* Define the union csr_dfx_dtif_err_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_err_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dtif_err_pls_u; + +/* Define the union csr_dfx_dtif_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dtif_fatal_msk_u; + +/* Define the union csr_dfx_dtif_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dtif_nonfatal_msk_u; + +/* Define the union csr_dtif_fifo0_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_cpld_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo0_sts_u; + +/* Define the union csr_dtif_fifo1_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_csr_rsp_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo1_sts_u; + +/* Define the union csr_dtif_fifo2_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_nl2_cmd_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo2_sts_u; + +/* Define the union csr_dtif_fifo3_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_csr_acc_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo3_sts_u; + +/* Define the union csr_dtif_fifo4_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p0_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo4_sts_u; + +/* Define the union csr_dtif_fifo5_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p1_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo5_sts_u; + +/* Define the union csr_dtif_fifo6_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p2_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo6_sts_u; + +/* Define the union csr_dtif_fifo7_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p3_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo7_sts_u; + +/* Define the union csr_db_arb_qmap_fifo_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_fifo_cnt : 5; /* [4:0] */ + u32 arb_dwqe_db_bp : 1; /* [5] */ + u32 dwqe_db_fifo_ept : 1; /* [6] */ + u32 rsv_2 : 1; /* [7] */ + u32 virtio_db_fifo_cnt : 5; /* [12:8] */ + u32 arb_virtio_db_bp : 1; /* [13] */ + u32 virtio_db_fifo_ept : 1; /* [14] */ + u32 rsv_3 : 1; /* [15] */ + u32 osch_db_fifo_cnt : 5; /* [20:16] */ + u32 arb_osch_db_bp : 1; /* [21] */ + u32 osch_db_fifo_ept : 1; /* [22] */ + u32 rsv_4 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_fifo_ro_u; + +/* Define the union csr_db_arb_qmap_arb_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_arb_schedule_en : 1; /* [0] */ + u32 tcam_srch_schedule_en : 1; /* [1] */ + u32 db_buf_empty : 1; /* [2] */ + u32 rsv_5 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_arb_ro_u; + +/* Define the union csr_db_arb_qmap_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_0_u; + +/* Define the union csr_db_arb_qmap_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_db_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_1_u; + +/* Define the union csr_db_arb_qmap_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_db_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_2_u; + +/* Define the union csr_db_arb_qmap_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_arb_gnt_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_3_u; + +/* Define the union csr_db_arb_qmap_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_mqm_tx_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_4_u; + +/* Define the union csr_db_arb_qmap_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_db_tx_req_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_5_u; + +/* Define the union csr_db_arb_qmap_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_tcam_srch_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_6_u; + +/* Define the union csr_db_arb_qmap_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_tcam_srch_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_7_u; + +/* Define the union csr_db_arb_qmap_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_tcam_srch_miss_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_8_u; + +/* Define the union csr_db_arb_qmap_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcam_srch_gnt_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_9_u; + +/* Define the union csr_db_arb_qmap_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_tcam_srch_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_10_u; + +/* Define the union csr_db_arb_qmap_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_tcam_srch_miss_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_11_u; + +/* Define the union csr_dfx_db_arb_qmap_err_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmap_err_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_db_arb_qmap_err_pls_u; + +/* Define the union csr_dfx_db_arb_qmap_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmap_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_db_arb_qmap_fatal_msk_u; + +/* Define the union csr_dfx_db_arb_qmap_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmap_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_db_arb_qmap_nonfatal_msk_u; + +/* Define the union csr_ib_misc_dfx_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x86_req_fifo_cnt : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 spu_req_fifo_cnt : 5; /* [12:8] */ + u32 rsv_7 : 3; /* [15:13] */ + u32 mctp_rx_fifo_cnt : 7; /* [22:16] */ + u32 rsv_8 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_ro_0_u; + +/* Define the union csr_ib_misc_dfx_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_buf_dat_cnt : 2; /* [1:0] */ + u32 req_buf_reg_empty : 1; /* [2] */ + u32 rsv_9 : 1; /* [3] */ + u32 req_arb_gnted : 2; /* [5:4] */ + u32 req_arb_schedule_en : 1; /* [6] */ + u32 rsv_10 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_ro_1_u; + +/* Define the union csr_ib_misc_dfx_cnt_20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aer_uc_rpt_cnt : 16; /* [15:0] */ + u32 aer_ur_rpt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_20_u; + +/* Define the union csr_ib_misc_dfx_cnt_21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aer_all_rpt_cnt : 16; /* [15:0] */ + u32 aer_tout_rpt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_21_u; + +/* Define the union csr_ib_misc_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x86_req_fifo_overflow_cnt : 16; /* [15:0] */ + u32 spu_req_fifo_overflow_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_0_u; + +/* Define the union csr_ib_misc_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 abnormal_tlp_cnt : 16; /* [15:0] */ + u32 memio_tlp_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_1_u; + +/* Define the union csr_ib_misc_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_2_u; + +/* Define the union csr_ib_misc_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdm1_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_3_u; + +/* Define the union csr_ib_misc_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memio_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_4_u; + +/* Define the union csr_ib_misc_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spu_req_fifo_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_5_u; + +/* Define the union csr_ib_misc_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_req_crd_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_6_u; + +/* Define the union csr_ib_misc_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x86_req_fifo_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_7_u; + +/* Define the union csr_ib_misc_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_req_crd_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_8_u; + +/* Define the union csr_ib_misc_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_9_u; + +/* Define the union csr_ib_misc_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_10_u; + +/* Define the union csr_ib_misc_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_11_u; + +/* Define the union csr_ib_misc_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_12_u; + +/* Define the union csr_ib_misc_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_sop_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_13_u; + +/* Define the union csr_ib_misc_dfx_cnt_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_14_u; + +/* Define the union csr_ib_misc_dfx_cnt_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_15_u; + +/* Define the union csr_ib_misc_dfx_cnt_16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_16_u; + +/* Define the union csr_ib_misc_dfx_cnt_17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_17_u; + +/* Define the union csr_ib_misc_dfx_cnt_18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_sop_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_18_u; + +/* Define the union csr_ib_misc_dfx_cnt_19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_seop_err_cnt : 16; /* [15:0] */ + u32 req_x86_seop_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_19_u; + +/* Define the union csr_dfx_ctl_misc_err_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ctl_misc_err_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ctl_misc_err_pls_u; + +/* Define the union csr_dfx_ctl_misc_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ctl_misc_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ctl_misc_fatal_msk_u; + +/* Define the union csr_dfx_ctl_misc_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ctl_misc_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ctl_misc_nonfatal_msk_u; + +/* Define the union csr_virtio_itf_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_tlp_receive_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_0_u; + +/* Define the union csr_virtio_itf_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_msix_receive_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_1_u; + +/* Define the union csr_virtio_itf_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_2_u; + +/* Define the union csr_virtio_itf_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_tlp_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_3_u; + +/* Define the union csr_virtio_itf_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_msix_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_4_u; + +/* Define the union csr_virtio_itf_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_direct_cpld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_5_u; + +/* Define the union csr_virtio_itf_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_discard_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_6_u; + +/* Define the union csr_virtio_itf_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_api_cpld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_7_u; + +/* Define the union csr_virtio_itf_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_send_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_8_u; + +/* Define the union csr_virtio_itf_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_api_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_9_u; + +/* Define the union csr_virtio_itf_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_send_cpld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_10_u; + +/* Define the union csr_virtio_itf_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_noapi_2dw_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_11_u; + +/* Define the union csr_cpl_ctl_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_ctl_fifo_ae_th_cfg : 6; /* [5:0] */ + u32 rsv_11 : 2; /* [7:6] */ + u32 cpl_ctl_fifo_af_th_cfg : 6; /* [13:8] */ + u32 rsv_12 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_fifo_cfg_u; + +/* Define the union csr_cpl_ctl_fifo_sts_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_ctl_fifo_cnt : 5; /* [4:0] */ + u32 rsv_13 : 11; /* [15:5] */ + u32 cpl_ctl_fifo_empty : 1; /* [16] */ + u32 cpl_ctl_fifo_pfull : 1; /* [17] */ + u32 rsv_14 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_fifo_sts_ro_u; + +/* Define the union csr_cpl_ctl_sts_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_ctl_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_sts_ro_u; + +/* Define the union csr_cpl_ctl_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_ictl_cnt : 16; /* [15:0] */ + u32 dfx_cpl_vio_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_dfx_cnt_0_u; + +/* Define the union csr_cpl_ctl_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_aeqcsr_cnt : 16; /* [15:0] */ + u32 dfx_cpl_ipush_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_dfx_cnt_1_u; + +/* Define the union csr_cpl_ctl_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_total_cnt : 16; /* [15:0] */ + u32 dfx_cpl_apictl_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_dfx_cnt_2_u; + +/* Define the union csr_db_arb_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_arb_weight : 4; /* [3:0] */ + u32 virtio_db_arb_weight : 4; /* [7:4] */ + u32 osch_db_arb_weight : 4; /* [11:8] */ + u32 rsv_15 : 4; /* [15:12] */ + u32 db_srch_tcam_arb_weight : 4; /* [19:16] */ + u32 vio_srch_tcam_arb_weight : 4; /* [23:20] */ + u32 sw_srch_tcam_arb_weight : 4; /* [27:24] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_weight_cfg_u; + +/* Define the union csr_osch_db_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_db_fifo_af_th : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_db_fifo_af_th_u; + +/* Define the union csr_virtio_db_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_db_fifo_af_th : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_db_fifo_af_th_u; + +/* Define the union csr_dwqe_db_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_fifo_af_th : 6; /* [5:0] */ + u32 rsv_19 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_db_fifo_af_th_u; + +/* Define the union csr_qmap_tcam_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcam_top_msk_cfg : 26; /* [25:0] */ + u32 rsv_20 : 5; /* [30:26] */ + u32 tcam_top_valid_bit_mask_cfg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qmap_tcam_rsvd_cfg_u; + +/* Define the union csr_nvme_db_cos_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_db_cos_0 : 3; /* [2:0] */ + u32 rsv_21 : 1; /* [3] */ + u32 nvme_db_cos_1 : 3; /* [6:4] */ + u32 rsv_22 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_db_cos_cfg_u; + +/* Define the union csr_virtio_db_cos_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_db_cos_rq : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 virtio_db_cos_sq : 3; /* [6:4] */ + u32 rsv_24 : 1; /* [7] */ + u32 virtio_db_cos_ctrlq : 3; /* [10:8] */ + u32 rsv_25 : 1; /* [11] */ + u32 virtio_db_cos_eventq : 3; /* [14:12] */ + u32 rsv_26 : 1; /* [15] */ + u32 virtio_db_cos_rqstq : 3; /* [18:16] */ + u32 rsv_27 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_db_cos_cfg_u; + +/* Define the union csr_virtio_itf_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_lb_only_smf0_en : 1; /* [0] */ + u32 virtio_err_rtn_cpl_en : 1; /* [1] */ + u32 rsv_28 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cfg_u; + +/* Define the union csr_virtio_itf_dfx_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_tlp_af_th : 10; /* [9:0] */ + u32 rsv_29 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cfg_1_u; + +/* Define the union csr_virtio_itf_dfx_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bitmap_exhauste : 1; /* [0] */ + u32 virtio_use_tag_cnt : 7; /* [7:1] */ + u32 o_free_addr_cnt : 7; /* [14:8] */ + u32 send_location_flag : 4; /* [18:15] */ + u32 sfifo_tlp_full : 1; /* [19] */ + u32 sfifo_msix_full : 1; /* [20] */ + u32 api_sfifo_full : 1; /* [21] */ + u32 direct_sfifo_full : 1; /* [22] */ + u32 sfifo_tlp_empty : 1; /* [23] */ + u32 sfifo_msix_empty : 1; /* [24] */ + u32 api_sfifo_empty : 1; /* [25] */ + u32 direct_sfifo_empty : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_sts0_u; + +/* Define the union csr_vio_flr_dly_timer_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_flr_dly_timer_th : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vio_flr_dly_timer_th_u; + +/* Define the union csr_vio_flr_dly_timer_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_flr_dly_timer_unit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vio_flr_dly_timer_unit_u; + +/* Define the union csr_vio_flr_enable_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_flr_enable_dly : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vio_flr_enable_dly_u; + +/* Define the union csr_ib_misc_mctp_rx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_non_mctp_drop_en : 1; /* [0] */ + u32 mctp_rx_hed_byte_order_en : 1; /* [1] */ + u32 rsv_33 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_mctp_rx_cfg_u; + +/* Define the union csr_ib_misc_pcie_itf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_pcie_rx_cpl_data_crd_vld : 1; /* [0] */ + u32 cpi_pcie_rx_req_data_crd_vld : 1; /* [1] */ + u32 cpi_pcie_rx_cpl_crd_active_en : 1; /* [2] */ + u32 cpi_pcie_rx_req_crd_active_en : 1; /* [3] */ + u32 pcie_cpi_rx_cpl_crd_active_en : 1; /* [4] */ + u32 pcie_cpi_rx_req_crd_active_en : 1; /* [5] */ + u32 rsv_34 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_pcie_itf_cfg_u; + +/* Define the union csr_virtio_rsvd_q_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_rsvd0_q_index : 13; /* [12:0] */ + u32 virtio_rsvd0_q_type : 1; /* [13] */ + u32 rsv_35 : 2; /* [15:14] */ + u32 virtio_rsvd1_q_index : 13; /* [28:16] */ + u32 virtio_rsvd1_q_type : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_rsvd_q_cfg_u; + +/* Define the union csr_virtio_cos_sq_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cos_sq_cfg_typ0 : 3; /* [2:0] */ + u32 virtio_cos_sq_cfg_typ1 : 3; /* [5:3] */ + u32 virtio_cos_sq_cfg_typ2 : 3; /* [8:6] */ + u32 virtio_cos_sq_cfg_typ3 : 3; /* [11:9] */ + u32 virtio_cos_sq_cfg_typ4 : 3; /* [14:12] */ + u32 virtio_cos_sq_cfg_typ5 : 3; /* [17:15] */ + u32 virtio_cos_sq_cfg_typ6 : 3; /* [20:18] */ + u32 virtio_cos_sq_cfg_typ7 : 3; /* [23:21] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cos_sq_cfg0_u; + +/* Define the union csr_virtio_cos_sq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cos_sq_cfg_typ8 : 3; /* [2:0] */ + u32 virtio_cos_sq_cfg_typ9 : 3; /* [5:3] */ + u32 virtio_cos_sq_cfg_typ10 : 3; /* [8:6] */ + u32 virtio_cos_sq_cfg_typ11 : 3; /* [11:9] */ + u32 virtio_cos_sq_cfg_typ12 : 3; /* [14:12] */ + u32 virtio_cos_sq_cfg_typ13 : 3; /* [17:15] */ + u32 virtio_cos_sq_cfg_typ14 : 3; /* [20:18] */ + u32 virtio_cos_sq_cfg_typ15 : 3; /* [23:21] */ + u32 rsv_38 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cos_sq_cfg1_u; + +/* Define the union csr_virtio_cos_sq_rp_en_all_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cos_rp_en : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cos_sq_rp_en_all_u; + +/* Define the union csr_virtio_direct_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 direct_fifo_af_th : 4; /* [3:0] */ + u32 rsv_40 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_direct_fifo_af_th_u; + +/* Define the union csr_virtio_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_fifo_af_th : 6; /* [5:0] */ + u32 rsv_41 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_api_fifo_af_th_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_dtif_fifo_af_th_u dtif_fifo_af_th; /* 0 */ + volatile csr_dtif_dfx_arb_ro_u dtif_dfx_arb_ro; /* 8 */ + volatile csr_dtif_dfx_cnt_0_u dtif_dfx_cnt_0; /* C */ + volatile csr_dtif_dfx_cnt_1_u dtif_dfx_cnt_1; /* 10 */ + volatile csr_dtif_dfx_cnt_2_u dtif_dfx_cnt_2; /* 14 */ + volatile csr_dtif_dfx_cnt_3_u dtif_dfx_cnt_3; /* 18 */ + volatile csr_dtif_dfx_cnt_4_u dtif_dfx_cnt_4; /* 1C */ + volatile csr_dtif_dfx_cnt_5_u dtif_dfx_cnt_5; /* 20 */ + volatile csr_dtif_dfx_cnt_6_u dtif_dfx_cnt_6; /* 24 */ + volatile csr_dtif_dfx_cnt_7_u dtif_dfx_cnt_7; /* 28 */ + volatile csr_dtif_dfx_cnt_8_u dtif_dfx_cnt_8; /* 2C */ + volatile csr_dtif_dfx_cnt_9_u dtif_dfx_cnt_9; /* 30 */ + volatile csr_dtif_dfx_cnt_10_u dtif_dfx_cnt_10; /* 34 */ + volatile csr_dtif_dfx_cnt_11_u dtif_dfx_cnt_11; /* 38 */ + volatile csr_dtif_dfx_cnt_12_u dtif_dfx_cnt_12; /* 3C */ + volatile csr_dtif_dfx_cnt_13_u dtif_dfx_cnt_13; /* 40 */ + volatile csr_dtif_dfx_cnt_14_u dtif_dfx_cnt_14; /* 44 */ + volatile csr_dtif_dfx_cnt_15_u dtif_dfx_cnt_15; /* 48 */ + volatile csr_dtif_dfx_cnt_16_u dtif_dfx_cnt_16; /* 4C */ + volatile csr_dtif_dfx_cnt_17_u dtif_dfx_cnt_17; /* 50 */ + volatile csr_dtif_dfx_cnt_18_u dtif_dfx_cnt_18; /* 54 */ + volatile csr_dtif_dfx_cnt_19_u dtif_dfx_cnt_19; /* 58 */ + volatile csr_dtif_dfx_cnt_20_u dtif_dfx_cnt_20; /* 5C */ + volatile csr_dtif_dfx_cnt_21_u dtif_dfx_cnt_21; /* 60 */ + volatile csr_dtif_dfx_cnt_22_u dtif_dfx_cnt_22; /* 64 */ + volatile csr_dtif_dfx_cnt_23_u dtif_dfx_cnt_23; /* 68 */ + volatile csr_dtif_dfx_cnt_24_u dtif_dfx_cnt_24; /* 6C */ + volatile csr_dtif_dfx_cnt_25_u dtif_dfx_cnt_25; /* 70 */ + volatile csr_dtif_dfx_cnt_26_u dtif_dfx_cnt_26; /* 74 */ + volatile csr_dtif_dfx_cnt_27_u dtif_dfx_cnt_27; /* 78 */ + volatile csr_dtif_dfx_cnt_28_u dtif_dfx_cnt_28; /* 7C */ + volatile csr_dtif_dfx_cnt_29_u dtif_dfx_cnt_29; /* 80 */ + volatile csr_dtif_dfx_cnt_30_u dtif_dfx_cnt_30; /* 84 */ + volatile csr_dtif_dfx_cnt_31_u dtif_dfx_cnt_31; /* 88 */ + volatile csr_dtif_dfx_cnt_32_u dtif_dfx_cnt_32; /* 8C */ + volatile csr_dtif_dfx_cnt_33_u dtif_dfx_cnt_33; /* 90 */ + volatile csr_dtif_dfx_cnt_34_u dtif_dfx_cnt_34; /* 94 */ + volatile csr_dfx_dtif_err_pls_u dfx_dtif_err_pls; /* A0 */ + volatile csr_dfx_dtif_fatal_msk_u dfx_dtif_fatal_msk; /* A4 */ + volatile csr_dfx_dtif_nonfatal_msk_u dfx_dtif_nonfatal_msk; /* A8 */ + volatile csr_dtif_fifo0_sts_u dtif_fifo0_sts; /* B0 */ + volatile csr_dtif_fifo1_sts_u dtif_fifo1_sts; /* B4 */ + volatile csr_dtif_fifo2_sts_u dtif_fifo2_sts; /* B8 */ + volatile csr_dtif_fifo3_sts_u dtif_fifo3_sts; /* BC */ + volatile csr_dtif_fifo4_sts_u dtif_fifo4_sts; /* C0 */ + volatile csr_dtif_fifo5_sts_u dtif_fifo5_sts; /* C4 */ + volatile csr_dtif_fifo6_sts_u dtif_fifo6_sts; /* C8 */ + volatile csr_dtif_fifo7_sts_u dtif_fifo7_sts; /* CC */ + volatile csr_db_arb_qmap_fifo_ro_u db_arb_qmap_fifo_ro; /* 100 */ + volatile csr_db_arb_qmap_arb_ro_u db_arb_qmap_arb_ro; /* 108 */ + volatile csr_db_arb_qmap_cnt_0_u db_arb_qmap_cnt_0; /* 110 */ + volatile csr_db_arb_qmap_cnt_1_u db_arb_qmap_cnt_1; /* 114 */ + volatile csr_db_arb_qmap_cnt_2_u db_arb_qmap_cnt_2; /* 118 */ + volatile csr_db_arb_qmap_cnt_3_u db_arb_qmap_cnt_3; /* 11C */ + volatile csr_db_arb_qmap_cnt_4_u db_arb_qmap_cnt_4; /* 120 */ + volatile csr_db_arb_qmap_cnt_5_u db_arb_qmap_cnt_5; /* 124 */ + volatile csr_db_arb_qmap_cnt_6_u db_arb_qmap_cnt_6; /* 128 */ + volatile csr_db_arb_qmap_cnt_7_u db_arb_qmap_cnt_7; /* 12C */ + volatile csr_db_arb_qmap_cnt_8_u db_arb_qmap_cnt_8; /* 130 */ + volatile csr_db_arb_qmap_cnt_9_u db_arb_qmap_cnt_9; /* 134 */ + volatile csr_db_arb_qmap_cnt_10_u db_arb_qmap_cnt_10; /* 138 */ + volatile csr_db_arb_qmap_cnt_11_u db_arb_qmap_cnt_11; /* 13C */ + volatile csr_dfx_db_arb_qmap_err_pls_u dfx_db_arb_qmap_err_pls; /* 150 */ + volatile csr_dfx_db_arb_qmap_fatal_msk_u dfx_db_arb_qmap_fatal_msk; /* 154 */ + volatile csr_dfx_db_arb_qmap_nonfatal_msk_u dfx_db_arb_qmap_nonfatal_msk; /* 158 */ + volatile csr_ib_misc_dfx_ro_0_u ib_misc_dfx_ro_0; /* 180 */ + volatile csr_ib_misc_dfx_ro_1_u ib_misc_dfx_ro_1; /* 184 */ + volatile csr_ib_misc_dfx_cnt_20_u ib_misc_dfx_cnt_20; /* 198 */ + volatile csr_ib_misc_dfx_cnt_21_u ib_misc_dfx_cnt_21; /* 19C */ + volatile csr_ib_misc_dfx_cnt_0_u ib_misc_dfx_cnt_0; /* 1A0 */ + volatile csr_ib_misc_dfx_cnt_1_u ib_misc_dfx_cnt_1; /* 1A4 */ + volatile csr_ib_misc_dfx_cnt_2_u ib_misc_dfx_cnt_2; /* 1A8 */ + volatile csr_ib_misc_dfx_cnt_3_u ib_misc_dfx_cnt_3; /* 1AC */ + volatile csr_ib_misc_dfx_cnt_4_u ib_misc_dfx_cnt_4; /* 1B0 */ + volatile csr_ib_misc_dfx_cnt_5_u ib_misc_dfx_cnt_5; /* 1B4 */ + volatile csr_ib_misc_dfx_cnt_6_u ib_misc_dfx_cnt_6; /* 1B8 */ + volatile csr_ib_misc_dfx_cnt_7_u ib_misc_dfx_cnt_7; /* 1BC */ + volatile csr_ib_misc_dfx_cnt_8_u ib_misc_dfx_cnt_8; /* 1C0 */ + volatile csr_ib_misc_dfx_cnt_9_u ib_misc_dfx_cnt_9; /* 1C4 */ + volatile csr_ib_misc_dfx_cnt_10_u ib_misc_dfx_cnt_10; /* 1C8 */ + volatile csr_ib_misc_dfx_cnt_11_u ib_misc_dfx_cnt_11; /* 1CC */ + volatile csr_ib_misc_dfx_cnt_12_u ib_misc_dfx_cnt_12; /* 1D0 */ + volatile csr_ib_misc_dfx_cnt_13_u ib_misc_dfx_cnt_13; /* 1D4 */ + volatile csr_ib_misc_dfx_cnt_14_u ib_misc_dfx_cnt_14; /* 1D8 */ + volatile csr_ib_misc_dfx_cnt_15_u ib_misc_dfx_cnt_15; /* 1DC */ + volatile csr_ib_misc_dfx_cnt_16_u ib_misc_dfx_cnt_16; /* 1E0 */ + volatile csr_ib_misc_dfx_cnt_17_u ib_misc_dfx_cnt_17; /* 1E4 */ + volatile csr_ib_misc_dfx_cnt_18_u ib_misc_dfx_cnt_18; /* 1E8 */ + volatile csr_ib_misc_dfx_cnt_19_u ib_misc_dfx_cnt_19; /* 1EC */ + volatile csr_dfx_ctl_misc_err_pls_u dfx_ctl_misc_err_pls; /* 1F0 */ + volatile csr_dfx_ctl_misc_fatal_msk_u dfx_ctl_misc_fatal_msk; /* 1F4 */ + volatile csr_dfx_ctl_misc_nonfatal_msk_u dfx_ctl_misc_nonfatal_msk; /* 1F8 */ + volatile csr_virtio_itf_dfx_cnt_0_u virtio_itf_dfx_cnt_0; /* 200 */ + volatile csr_virtio_itf_dfx_cnt_1_u virtio_itf_dfx_cnt_1; /* 204 */ + volatile csr_virtio_itf_dfx_cnt_2_u virtio_itf_dfx_cnt_2; /* 208 */ + volatile csr_virtio_itf_dfx_cnt_3_u virtio_itf_dfx_cnt_3; /* 20C */ + volatile csr_virtio_itf_dfx_cnt_4_u virtio_itf_dfx_cnt_4; /* 210 */ + volatile csr_virtio_itf_dfx_cnt_5_u virtio_itf_dfx_cnt_5; /* 214 */ + volatile csr_virtio_itf_dfx_cnt_6_u virtio_itf_dfx_cnt_6; /* 218 */ + volatile csr_virtio_itf_dfx_cnt_7_u virtio_itf_dfx_cnt_7; /* 21C */ + volatile csr_virtio_itf_dfx_cnt_8_u virtio_itf_dfx_cnt_8; /* 220 */ + volatile csr_virtio_itf_dfx_cnt_9_u virtio_itf_dfx_cnt_9; /* 224 */ + volatile csr_virtio_itf_dfx_cnt_10_u virtio_itf_dfx_cnt_10; /* 228 */ + volatile csr_virtio_itf_dfx_cnt_11_u virtio_itf_dfx_cnt_11; /* 22C */ + volatile csr_cpl_ctl_fifo_cfg_u cpl_ctl_fifo_cfg; /* 280 */ + volatile csr_cpl_ctl_fifo_sts_ro_u cpl_ctl_fifo_sts_ro; /* 290 */ + volatile csr_cpl_ctl_sts_ro_u cpl_ctl_sts_ro; /* 294 */ + volatile csr_cpl_ctl_dfx_cnt_0_u cpl_ctl_dfx_cnt_0; /* 2A0 */ + volatile csr_cpl_ctl_dfx_cnt_1_u cpl_ctl_dfx_cnt_1; /* 2A4 */ + volatile csr_cpl_ctl_dfx_cnt_2_u cpl_ctl_dfx_cnt_2; /* 2A8 */ + volatile csr_db_arb_weight_cfg_u db_arb_weight_cfg; /* 400 */ + volatile csr_osch_db_fifo_af_th_u osch_db_fifo_af_th; /* 404 */ + volatile csr_virtio_db_fifo_af_th_u virtio_db_fifo_af_th; /* 408 */ + volatile csr_dwqe_db_fifo_af_th_u dwqe_db_fifo_af_th; /* 40C */ + volatile csr_qmap_tcam_rsvd_cfg_u qmap_tcam_rsvd_cfg; /* 410 */ + volatile csr_nvme_db_cos_cfg_u nvme_db_cos_cfg; /* 440 */ + volatile csr_virtio_db_cos_cfg_u virtio_db_cos_cfg; /* 444 */ + volatile csr_virtio_itf_dfx_cfg_u virtio_itf_dfx_cfg; /* 448 */ + volatile csr_virtio_itf_dfx_cfg_1_u virtio_itf_dfx_cfg_1; /* 44C */ + volatile csr_virtio_itf_dfx_sts0_u virtio_itf_dfx_sts0; /* 490 */ + volatile csr_vio_flr_dly_timer_th_u vio_flr_dly_timer_th; /* 498 */ + volatile csr_vio_flr_dly_timer_unit_u vio_flr_dly_timer_unit; /* 49C */ + volatile csr_vio_flr_enable_dly_u vio_flr_enable_dly; /* 4A0 */ + volatile csr_ib_misc_mctp_rx_cfg_u ib_misc_mctp_rx_cfg; /* 4B0 */ + volatile csr_ib_misc_pcie_itf_cfg_u ib_misc_pcie_itf_cfg; /* 4B4 */ + volatile csr_virtio_rsvd_q_cfg_u virtio_rsvd_q_cfg[2]; /* 500 */ + volatile csr_virtio_cos_sq_cfg0_u virtio_cos_sq_cfg0; /* 6A0 */ + volatile csr_virtio_cos_sq_cfg1_u virtio_cos_sq_cfg1; /* 6A4 */ + volatile csr_virtio_cos_sq_rp_en_all_u virtio_cos_sq_rp_en_all; /* 6A8 */ + volatile csr_virtio_direct_fifo_af_th_u virtio_direct_fifo_af_th; /* 6AC */ + volatile csr_virtio_api_fifo_af_th_u virtio_api_fifo_af_th; /* 6B0 */ +} S_dfx_ctrl_top_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_ctrl_top_csr */ +extern volatile S_dfx_ctrl_top_csr_REGS_TYPE *gopdfx_ctrl_top_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetDTIF_FIFO_AF_TH_dtif_csr_acc_af_th(unsigned int udtif_csr_acc_af_th); +int iSetDTIF_FIFO_AF_TH_dtif_tx_tlp_af_th(unsigned int udtif_tx_tlp_af_th); +int iSetDTIF_DFX_ARB_RO_dtif_tx_gnt_ff(unsigned int udtif_tx_gnt_ff); +int iSetDTIF_DFX_ARB_RO_dtif_tx_gnt_vld(unsigned int udtif_tx_gnt_vld); +int iSetDTIF_DFX_ARB_RO_dtif_tx_is_busy(unsigned int udtif_tx_is_busy); +int iSetDTIF_DFX_CNT_0_tx_csr_acc_cnt(unsigned int utx_csr_acc_cnt); +int iSetDTIF_DFX_CNT_1_tx_tlp_arb_sel_cnt(unsigned int utx_tlp_arb_sel_cnt); +int iSetDTIF_DFX_CNT_2_tx_tlp_crdt_prt0_cnt(unsigned int utx_tlp_crdt_prt0_cnt); +int iSetDTIF_DFX_CNT_3_tx_tlp_crdt_prt1_cnt(unsigned int utx_tlp_crdt_prt1_cnt); +int iSetDTIF_DFX_CNT_4_tx_tlp_crdt_prt2_cnt(unsigned int utx_tlp_crdt_prt2_cnt); +int iSetDTIF_DFX_CNT_5_tx_tlp_crdt_prt3_cnt(unsigned int utx_tlp_crdt_prt3_cnt); +int iSetDTIF_DFX_CNT_6_tx_tlp_mpu2dtif_pkt_prt0_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt0_cnt); +int iSetDTIF_DFX_CNT_7_tx_tlp_mpu2dtif_pkt_prt1_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt1_cnt); +int iSetDTIF_DFX_CNT_8_tx_tlp_mpu2dtif_pkt_prt2_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt2_cnt); +int iSetDTIF_DFX_CNT_9_tx_tlp_mpu2dtif_pkt_prt3_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt3_cnt); +int iSetDTIF_DFX_CNT_10_tx_tlp_mpu2dtif_vld_prt0_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt0_cnt); +int iSetDTIF_DFX_CNT_11_tx_tlp_mpu2dtif_vld_prt1_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt1_cnt); +int iSetDTIF_DFX_CNT_12_tx_tlp_mpu2dtif_vld_prt2_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt2_cnt); +int iSetDTIF_DFX_CNT_13_tx_tlp_mpu2dtif_vld_prt3_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt3_cnt); +int iSetDTIF_DFX_CNT_14_tx_tlp_dtif2ctif_pkt_cnt(unsigned int utx_tlp_dtif2ctif_pkt_cnt); +int iSetDTIF_DFX_CNT_15_tx_tlp_dtif2ctif_vld_cnt(unsigned int utx_tlp_dtif2ctif_vld_cnt); +int iSetDTIF_DFX_CNT_16_tx_epath_rd_cmd_prt0_cnt(unsigned int utx_epath_rd_cmd_prt0_cnt); +int iSetDTIF_DFX_CNT_17_tx_epath_rd_cmd_prt1_cnt(unsigned int utx_epath_rd_cmd_prt1_cnt); +int iSetDTIF_DFX_CNT_18_tx_epath_rd_cmd_prt2_cnt(unsigned int utx_epath_rd_cmd_prt2_cnt); +int iSetDTIF_DFX_CNT_19_tx_epath_rd_cmd_prt3_cnt(unsigned int utx_epath_rd_cmd_prt3_cnt); +int iSetDTIF_DFX_CNT_20_tx_epath_rd_cmd_prt4_cnt(unsigned int utx_epath_rd_cmd_prt4_cnt); +int iSetDTIF_DFX_CNT_21_tx_wr_epath_cmd_prt0_cnt(unsigned int utx_wr_epath_cmd_prt0_cnt); +int iSetDTIF_DFX_CNT_22_tx_wr_epath_cmd_prt1_cnt(unsigned int utx_wr_epath_cmd_prt1_cnt); +int iSetDTIF_DFX_CNT_23_tx_wr_epath_cmd_prt2_cnt(unsigned int utx_wr_epath_cmd_prt2_cnt); +int iSetDTIF_DFX_CNT_24_tx_wr_epath_cmd_prt3_cnt(unsigned int utx_wr_epath_cmd_prt3_cnt); +int iSetDTIF_DFX_CNT_25_tx_wr_epath_cmd_prt4_cnt(unsigned int utx_wr_epath_cmd_prt4_cnt); +int iSetDTIF_DFX_CNT_26_tx_epath_wr_pkt_cnt(unsigned int utx_epath_wr_pkt_cnt); +int iSetDTIF_DFX_CNT_27_tx_epath_wr_vld_cnt(unsigned int utx_epath_wr_vld_cnt); +int iSetDTIF_DFX_CNT_28_tx_nl2_rsp_cnt(unsigned int utx_nl2_rsp_cnt); +int iSetDTIF_DFX_CNT_29_tx_nl2_rsp_crdt_cnt(unsigned int utx_nl2_rsp_crdt_cnt); +int iSetDTIF_DFX_CNT_30_rx_mpu_tlp_eop_cnt(unsigned int urx_mpu_tlp_eop_cnt); +int iSetDTIF_DFX_CNT_31_rx_api_chn_tlp_eop_cnt(unsigned int urx_api_chn_tlp_eop_cnt); +int iSetDTIF_DFX_CNT_32_rx_nl2_cmd_req_cnt(unsigned int urx_nl2_cmd_req_cnt); +int iSetDTIF_DFX_CNT_33_rx_mpu_csr_rsp_cnt(unsigned int urx_mpu_csr_rsp_cnt); +int iSetDTIF_DFX_CNT_34_rx_api_chn_tlp_abrt_cnt(unsigned int urx_api_chn_tlp_abrt_cnt); +int iSetDTIF_DFX_CNT_34_rx_mpu_tlp_abrt_cnt(unsigned int urx_mpu_tlp_abrt_cnt); +int iSetDFX_DTIF_ERR_PLS_dtif_err_pls(unsigned int udtif_err_pls); +int iSetDFX_DTIF_FATAL_MSK_dtif_fatal_msk(unsigned int udtif_fatal_msk); +int iSetDFX_DTIF_NONFATAL_MSK_dtif_nonfatal_msk(unsigned int udtif_nonfatal_msk); +int iSetDTIF_FIFO0_STS_dtif_cpld_fifo_sts(unsigned int udtif_cpld_fifo_sts); +int iSetDTIF_FIFO1_STS_dtif_csr_rsp_fifo_sts(unsigned int udtif_csr_rsp_fifo_sts); +int iSetDTIF_FIFO2_STS_dtif_nl2_cmd_fifo_sts(unsigned int udtif_nl2_cmd_fifo_sts); +int iSetDTIF_FIFO3_STS_dtif_csr_acc_fifo_sts(unsigned int udtif_csr_acc_fifo_sts); +int iSetDTIF_FIFO4_STS_dtif_tx_tlp_p0_fifo_sts(unsigned int udtif_tx_tlp_p0_fifo_sts); +int iSetDTIF_FIFO5_STS_dtif_tx_tlp_p1_fifo_sts(unsigned int udtif_tx_tlp_p1_fifo_sts); +int iSetDTIF_FIFO6_STS_dtif_tx_tlp_p2_fifo_sts(unsigned int udtif_tx_tlp_p2_fifo_sts); +int iSetDTIF_FIFO7_STS_dtif_tx_tlp_p3_fifo_sts(unsigned int udtif_tx_tlp_p3_fifo_sts); +int iSetDB_ARB_QMAP_FIFO_RO_dwqe_db_fifo_cnt(unsigned int udwqe_db_fifo_cnt); +int iSetDB_ARB_QMAP_FIFO_RO_arb_dwqe_db_bp(unsigned int uarb_dwqe_db_bp); +int iSetDB_ARB_QMAP_FIFO_RO_dwqe_db_fifo_ept(unsigned int udwqe_db_fifo_ept); +int iSetDB_ARB_QMAP_FIFO_RO_virtio_db_fifo_cnt(unsigned int uvirtio_db_fifo_cnt); +int iSetDB_ARB_QMAP_FIFO_RO_arb_virtio_db_bp(unsigned int uarb_virtio_db_bp); +int iSetDB_ARB_QMAP_FIFO_RO_virtio_db_fifo_ept(unsigned int uvirtio_db_fifo_ept); +int iSetDB_ARB_QMAP_FIFO_RO_osch_db_fifo_cnt(unsigned int uosch_db_fifo_cnt); +int iSetDB_ARB_QMAP_FIFO_RO_arb_osch_db_bp(unsigned int uarb_osch_db_bp); +int iSetDB_ARB_QMAP_FIFO_RO_osch_db_fifo_ept(unsigned int uosch_db_fifo_ept); +int iSetDB_ARB_QMAP_ARB_RO_db_arb_schedule_en(unsigned int udb_arb_schedule_en); +int iSetDB_ARB_QMAP_ARB_RO_tcam_srch_schedule_en(unsigned int utcam_srch_schedule_en); +int iSetDB_ARB_QMAP_ARB_RO_db_buf_empty(unsigned int udb_buf_empty); +int iSetDB_ARB_QMAP_CNT_0_dwqe_db_fifo_push_cnt(unsigned int udwqe_db_fifo_push_cnt); +int iSetDB_ARB_QMAP_CNT_1_virtio_db_fifo_push_cnt(unsigned int uvirtio_db_fifo_push_cnt); +int iSetDB_ARB_QMAP_CNT_2_osch_db_fifo_push_cnt(unsigned int uosch_db_fifo_push_cnt); +int iSetDB_ARB_QMAP_CNT_3_db_arb_gnt_total_cnt(unsigned int udb_arb_gnt_total_cnt); +int iSetDB_ARB_QMAP_CNT_4_cpi_mqm_tx_db_cnt(unsigned int ucpi_mqm_tx_db_cnt); +int iSetDB_ARB_QMAP_CNT_5_cpi_db_tx_req_total_cnt(unsigned int ucpi_db_tx_req_total_cnt); +int iSetDB_ARB_QMAP_CNT_6_flxq_tcam_srch_total_cnt(unsigned int uflxq_tcam_srch_total_cnt); +int iSetDB_ARB_QMAP_CNT_7_flxq_tcam_srch_hit_cnt(unsigned int uflxq_tcam_srch_hit_cnt); +int iSetDB_ARB_QMAP_CNT_8_flxq_tcam_srch_miss_cnt(unsigned int uflxq_tcam_srch_miss_cnt); +int iSetDB_ARB_QMAP_CNT_9_tcam_srch_gnt_total_cnt(unsigned int utcam_srch_gnt_total_cnt); +int iSetDB_ARB_QMAP_CNT_10_vio_tcam_srch_hit_cnt(unsigned int uvio_tcam_srch_hit_cnt); +int iSetDB_ARB_QMAP_CNT_11_vio_tcam_srch_miss_cnt(unsigned int uvio_tcam_srch_miss_cnt); +int iSetDFX_DB_ARB_QMAP_ERR_PLS_qmap_err_pls(unsigned int uqmap_err_pls); +int iSetDFX_DB_ARB_QMAP_FATAL_MSK_qmap_fatal_msk(unsigned int uqmap_fatal_msk); +int iSetDFX_DB_ARB_QMAP_NONFATAL_MSK_qmap_nonfatal_msk(unsigned int uqmap_nonfatal_msk); +int iSetIB_MISC_DFX_RO_0_x86_req_fifo_cnt(unsigned int ux86_req_fifo_cnt); +int iSetIB_MISC_DFX_RO_0_spu_req_fifo_cnt(unsigned int uspu_req_fifo_cnt); +int iSetIB_MISC_DFX_RO_0_mctp_rx_fifo_cnt(unsigned int umctp_rx_fifo_cnt); +int iSetIB_MISC_DFX_RO_1_req_buf_dat_cnt(unsigned int ureq_buf_dat_cnt); +int iSetIB_MISC_DFX_RO_1_req_buf_reg_empty(unsigned int ureq_buf_reg_empty); +int iSetIB_MISC_DFX_RO_1_req_arb_gnted(unsigned int ureq_arb_gnted); +int iSetIB_MISC_DFX_RO_1_req_arb_schedule_en(unsigned int ureq_arb_schedule_en); +int iSetIB_MISC_DFX_CNT_20_aer_uc_rpt_cnt(unsigned int uaer_uc_rpt_cnt); +int iSetIB_MISC_DFX_CNT_20_aer_ur_rpt_cnt(unsigned int uaer_ur_rpt_cnt); +int iSetIB_MISC_DFX_CNT_21_aer_all_rpt_cnt(unsigned int uaer_all_rpt_cnt); +int iSetIB_MISC_DFX_CNT_21_aer_tout_rpt_cnt(unsigned int uaer_tout_rpt_cnt); +int iSetIB_MISC_DFX_CNT_0_x86_req_fifo_overflow_cnt(unsigned int ux86_req_fifo_overflow_cnt); +int iSetIB_MISC_DFX_CNT_0_spu_req_fifo_overflow_cnt(unsigned int uspu_req_fifo_overflow_cnt); +int iSetIB_MISC_DFX_CNT_1_abnormal_tlp_cnt(unsigned int uabnormal_tlp_cnt); +int iSetIB_MISC_DFX_CNT_1_memio_tlp_err_cnt(unsigned int umemio_tlp_err_cnt); +int iSetIB_MISC_DFX_CNT_2_mctp_tlp_cnt(unsigned int umctp_tlp_cnt); +int iSetIB_MISC_DFX_CNT_3_vdm1_tlp_cnt(unsigned int uvdm1_tlp_cnt); +int iSetIB_MISC_DFX_CNT_4_memio_tlp_cnt(unsigned int umemio_tlp_cnt); +int iSetIB_MISC_DFX_CNT_5_spu_req_fifo_wr_cnt(unsigned int uspu_req_fifo_wr_cnt); +int iSetIB_MISC_DFX_CNT_6_hva_req_crd_vld_cnt(unsigned int uhva_req_crd_vld_cnt); +int iSetIB_MISC_DFX_CNT_7_x86_req_fifo_wr_cnt(unsigned int ux86_req_fifo_wr_cnt); +int iSetIB_MISC_DFX_CNT_8_pcie_req_crd_vld_cnt(unsigned int upcie_req_crd_vld_cnt); +int iSetIB_MISC_DFX_CNT_9_req_spu_pkt_ok_cnt(unsigned int ureq_spu_pkt_ok_cnt); +int iSetIB_MISC_DFX_CNT_10_req_spu_pkt_sop_cnt(unsigned int ureq_spu_pkt_sop_cnt); +int iSetIB_MISC_DFX_CNT_11_req_spu_pkt_eop_cnt(unsigned int ureq_spu_pkt_eop_cnt); +int iSetIB_MISC_DFX_CNT_12_req_spu_pkt_vld_cnt(unsigned int ureq_spu_pkt_vld_cnt); +int iSetIB_MISC_DFX_CNT_13_req_spu_pkt_sop_eop_cnt(unsigned int ureq_spu_pkt_sop_eop_cnt); +int iSetIB_MISC_DFX_CNT_14_req_x86_pkt_ok_cnt(unsigned int ureq_x86_pkt_ok_cnt); +int iSetIB_MISC_DFX_CNT_15_req_x86_pkt_sop_cnt(unsigned int ureq_x86_pkt_sop_cnt); +int iSetIB_MISC_DFX_CNT_16_req_x86_pkt_eop_cnt(unsigned int ureq_x86_pkt_eop_cnt); +int iSetIB_MISC_DFX_CNT_17_req_x86_pkt_vld_cnt(unsigned int ureq_x86_pkt_vld_cnt); +int iSetIB_MISC_DFX_CNT_18_req_x86_pkt_sop_eop_cnt(unsigned int ureq_x86_pkt_sop_eop_cnt); +int iSetIB_MISC_DFX_CNT_19_req_spu_seop_err_cnt(unsigned int ureq_spu_seop_err_cnt); +int iSetIB_MISC_DFX_CNT_19_req_x86_seop_err_cnt(unsigned int ureq_x86_seop_err_cnt); +int iSetDFX_CTL_MISC_ERR_PLS_dfx_ctl_misc_err_pls(unsigned int udfx_ctl_misc_err_pls); +int iSetDFX_CTL_MISC_FATAL_MSK_dfx_ctl_misc_fatal_msk(unsigned int udfx_ctl_misc_fatal_msk); +int iSetDFX_CTL_MISC_NONFATAL_MSK_dfx_ctl_misc_nonfatal_msk(unsigned int udfx_ctl_misc_nonfatal_msk); +int iSetVIRTIO_ITF_DFX_CNT_0_virtio_tlp_receive_cnt(unsigned int uvirtio_tlp_receive_cnt); +int iSetVIRTIO_ITF_DFX_CNT_1_virtio_msix_receive_cnt(unsigned int uvirtio_msix_receive_cnt); +int iSetVIRTIO_ITF_DFX_CNT_2_virtio_itf_db_cnt(unsigned int uvirtio_itf_db_cnt); +int iSetVIRTIO_ITF_DFX_CNT_3_virtio_itf_tlp_api_cnt(unsigned int uvirtio_itf_tlp_api_cnt); +int iSetVIRTIO_ITF_DFX_CNT_4_virtio_itf_msix_api_cnt(unsigned int uvirtio_itf_msix_api_cnt); +int iSetVIRTIO_ITF_DFX_CNT_5_virtio_itf_direct_cpld_cnt(unsigned int uvirtio_itf_direct_cpld_cnt); +int iSetVIRTIO_ITF_DFX_CNT_6_virtio_itf_discard_tlp_cnt(unsigned int uvirtio_itf_discard_tlp_cnt); +int iSetVIRTIO_ITF_DFX_CNT_7_virtio_itf_api_cpld_cnt(unsigned int uvirtio_itf_api_cpld_cnt); +int iSetVIRTIO_ITF_DFX_CNT_8_virtio_itf_send_api_cnt(unsigned int uvirtio_itf_send_api_cnt); +int iSetVIRTIO_ITF_DFX_CNT_9_virtio_itf_api_rsp_cnt(unsigned int uvirtio_itf_api_rsp_cnt); +int iSetVIRTIO_ITF_DFX_CNT_10_virtio_itf_send_cpld_cnt(unsigned int uvirtio_itf_send_cpld_cnt); +int iSetVIRTIO_ITF_DFX_CNT_11_virtio_itf_noapi_2dw_cnt(unsigned int uvirtio_itf_noapi_2dw_cnt); +int iSetCPL_CTL_FIFO_CFG_cpl_ctl_fifo_ae_th_cfg(unsigned int ucpl_ctl_fifo_ae_th_cfg); +int iSetCPL_CTL_FIFO_CFG_cpl_ctl_fifo_af_th_cfg(unsigned int ucpl_ctl_fifo_af_th_cfg); +int iSetCPL_CTL_FIFO_STS_RO_cpl_ctl_fifo_cnt(unsigned int ucpl_ctl_fifo_cnt); +int iSetCPL_CTL_FIFO_STS_RO_cpl_ctl_fifo_empty(unsigned int ucpl_ctl_fifo_empty); +int iSetCPL_CTL_FIFO_STS_RO_cpl_ctl_fifo_pfull(unsigned int ucpl_ctl_fifo_pfull); +int iSetCPL_CTL_STS_RO_dfx_cpl_ctl_sts(unsigned int udfx_cpl_ctl_sts); +int iSetCPL_CTL_DFX_CNT_0_dfx_cpl_ictl_cnt(unsigned int udfx_cpl_ictl_cnt); +int iSetCPL_CTL_DFX_CNT_0_dfx_cpl_vio_cnt(unsigned int udfx_cpl_vio_cnt); +int iSetCPL_CTL_DFX_CNT_1_dfx_cpl_aeqcsr_cnt(unsigned int udfx_cpl_aeqcsr_cnt); +int iSetCPL_CTL_DFX_CNT_1_dfx_cpl_ipush_cnt(unsigned int udfx_cpl_ipush_cnt); +int iSetCPL_CTL_DFX_CNT_2_dfx_cpl_total_cnt(unsigned int udfx_cpl_total_cnt); +int iSetCPL_CTL_DFX_CNT_2_dfx_cpl_apictl_cnt(unsigned int udfx_cpl_apictl_cnt); +int iSetDB_ARB_WEIGHT_CFG_dwqe_db_arb_weight(unsigned int udwqe_db_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_virtio_db_arb_weight(unsigned int uvirtio_db_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_osch_db_arb_weight(unsigned int uosch_db_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_db_srch_tcam_arb_weight(unsigned int udb_srch_tcam_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_vio_srch_tcam_arb_weight(unsigned int uvio_srch_tcam_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_sw_srch_tcam_arb_weight(unsigned int usw_srch_tcam_arb_weight); +int iSetOSCH_DB_FIFO_AF_TH_osch_db_fifo_af_th(unsigned int uosch_db_fifo_af_th); +int iSetVIRTIO_DB_FIFO_AF_TH_virtio_db_fifo_af_th(unsigned int uvirtio_db_fifo_af_th); +int iSetDWQE_DB_FIFO_AF_TH_dwqe_db_fifo_af_th(unsigned int udwqe_db_fifo_af_th); +int iSetQMAP_TCAM_RSVD_CFG_tcam_top_msk_cfg(unsigned int utcam_top_msk_cfg); +int iSetQMAP_TCAM_RSVD_CFG_tcam_top_valid_bit_mask_cfg(unsigned int utcam_top_valid_bit_mask_cfg); +int iSetNVME_DB_COS_CFG_nvme_db_cos_0(unsigned int unvme_db_cos_0); +int iSetNVME_DB_COS_CFG_nvme_db_cos_1(unsigned int unvme_db_cos_1); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_rq(unsigned int uvirtio_db_cos_rq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_sq(unsigned int uvirtio_db_cos_sq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_ctrlq(unsigned int uvirtio_db_cos_ctrlq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_eventq(unsigned int uvirtio_db_cos_eventq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_rqstq(unsigned int uvirtio_db_cos_rqstq); +int iSetVIRTIO_ITF_DFX_CFG_virtio_lb_only_smf0_en(unsigned int uvirtio_lb_only_smf0_en); +int iSetVIRTIO_ITF_DFX_CFG_virtio_err_rtn_cpl_en(unsigned int uvirtio_err_rtn_cpl_en); +int iSetVIRTIO_ITF_DFX_CFG_1_sfifo_tlp_af_th(unsigned int usfifo_tlp_af_th); +int iSetVIRTIO_ITF_DFX_STS0_bitmap_exhauste(unsigned int ubitmap_exhauste); +int iSetVIRTIO_ITF_DFX_STS0_virtio_use_tag_cnt(unsigned int uvirtio_use_tag_cnt); +int iSetVIRTIO_ITF_DFX_STS0_o_free_addr_cnt(unsigned int uo_free_addr_cnt); +int iSetVIRTIO_ITF_DFX_STS0_send_location_flag(unsigned int usend_location_flag); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_tlp_full(unsigned int usfifo_tlp_full); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_msix_full(unsigned int usfifo_msix_full); +int iSetVIRTIO_ITF_DFX_STS0_api_sfifo_full(unsigned int uapi_sfifo_full); +int iSetVIRTIO_ITF_DFX_STS0_direct_sfifo_full(unsigned int udirect_sfifo_full); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_tlp_empty(unsigned int usfifo_tlp_empty); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_msix_empty(unsigned int usfifo_msix_empty); +int iSetVIRTIO_ITF_DFX_STS0_api_sfifo_empty(unsigned int uapi_sfifo_empty); +int iSetVIRTIO_ITF_DFX_STS0_direct_sfifo_empty(unsigned int udirect_sfifo_empty); +int iSetVIO_FLR_DLY_TIMER_TH_vio_flr_dly_timer_th(unsigned int uvio_flr_dly_timer_th); +int iSetVIO_FLR_DLY_TIMER_UNIT_vio_flr_dly_timer_unit(unsigned int uvio_flr_dly_timer_unit); +int iSetVIO_FLR_ENABLE_DLY_vio_flr_enable_dly(unsigned int uvio_flr_enable_dly); +int iSetIB_MISC_MCTP_RX_CFG_mctp_rx_non_mctp_drop_en(unsigned int umctp_rx_non_mctp_drop_en); +int iSetIB_MISC_MCTP_RX_CFG_mctp_rx_hed_byte_order_en(unsigned int umctp_rx_hed_byte_order_en); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_cpl_data_crd_vld(unsigned int ucpi_pcie_rx_cpl_data_crd_vld); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_req_data_crd_vld(unsigned int ucpi_pcie_rx_req_data_crd_vld); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_cpl_crd_active_en(unsigned int ucpi_pcie_rx_cpl_crd_active_en); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_req_crd_active_en(unsigned int ucpi_pcie_rx_req_crd_active_en); +int iSetIB_MISC_PCIE_ITF_CFG_pcie_cpi_rx_cpl_crd_active_en(unsigned int upcie_cpi_rx_cpl_crd_active_en); +int iSetIB_MISC_PCIE_ITF_CFG_pcie_cpi_rx_req_crd_active_en(unsigned int upcie_cpi_rx_req_crd_active_en); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd0_q_index(unsigned int uvirtio_rsvd0_q_index); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd0_q_type(unsigned int uvirtio_rsvd0_q_type); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd1_q_index(unsigned int uvirtio_rsvd1_q_index); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd1_q_type(unsigned int uvirtio_rsvd1_q_type); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ0(unsigned int uvirtio_cos_sq_cfg_typ0); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ1(unsigned int uvirtio_cos_sq_cfg_typ1); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ2(unsigned int uvirtio_cos_sq_cfg_typ2); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ3(unsigned int uvirtio_cos_sq_cfg_typ3); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ4(unsigned int uvirtio_cos_sq_cfg_typ4); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ5(unsigned int uvirtio_cos_sq_cfg_typ5); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ6(unsigned int uvirtio_cos_sq_cfg_typ6); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ7(unsigned int uvirtio_cos_sq_cfg_typ7); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ8(unsigned int uvirtio_cos_sq_cfg_typ8); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ9(unsigned int uvirtio_cos_sq_cfg_typ9); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ10(unsigned int uvirtio_cos_sq_cfg_typ10); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ11(unsigned int uvirtio_cos_sq_cfg_typ11); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ12(unsigned int uvirtio_cos_sq_cfg_typ12); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ13(unsigned int uvirtio_cos_sq_cfg_typ13); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ14(unsigned int uvirtio_cos_sq_cfg_typ14); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ15(unsigned int uvirtio_cos_sq_cfg_typ15); +int iSetVIRTIO_COS_SQ_RP_EN_ALL_virtio_cos_rp_en(unsigned int uvirtio_cos_rp_en); +int iSetVIRTIO_DIRECT_FIFO_AF_TH_direct_fifo_af_th(unsigned int udirect_fifo_af_th); +int iSetVIRTIO_API_FIFO_AF_TH_api_fifo_af_th(unsigned int uapi_fifo_af_th); + +/* Define the union csr_cpath_csr_inj_enj_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_enj_cnt : 16; /* [15:0] */ + u32 cpath_csr_inj_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_inj_enj_cnt_u; + +/* Define the union csr_cpath_inbd_inj_enj_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_enj_cnt : 16; /* [15:0] */ + u32 cpath_inbd_inj_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_inj_enj_cnt_u; + +/* Define the union csr_cpath_non_cpi_int_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_non_cpi_int_cnt_sf : 16; /* [15:0] */ + u32 cpath_non_cpi_int_cnt_hw : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_non_cpi_int_cnt_u; + +/* Define the union csr_cpath_enj_rsvd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_enj_rsvd_cnt : 16; /* [15:0] */ + u32 cpath_csr_enj_rsvd_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_rsvd_cnt_u; + +/* Define the union csr_cpath_enj_nml_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_enj_nml_cnt : 16; /* [15:0] */ + u32 cpath_csr_enj_nml_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_nml_cnt_u; + +/* Define the union csr_cpath_inbd_oubd_cnt_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 2; /* [1:0] */ + u32 cpath_inbd_enj_cnt_type : 1; /* [2] */ + u32 cpath_inbd_inj_cnt_type : 1; /* [3] */ + u32 rsv_1 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_oubd_cnt_type_u; + +/* Define the union csr_cpath_fifo_aful_gap_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_pe_fifo_aful_gap_cpi : 5; /* [4:0] */ + u32 rsv_2 : 3; /* [7:5] */ + u32 cpath_csr_pi_fifo_aful_gap_cpi : 5; /* [12:8] */ + u32 rsv_3 : 3; /* [15:13] */ + u32 cpath_inbd_pe_fifo_aful_gap_cpi : 6; /* [21:16] */ + u32 rsv_4 : 2; /* [23:22] */ + u32 cpath_inbd_pi_fifo_aful_gap_cpi : 5; /* [28:24] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_fifo_aful_gap_0_u; + +/* Define the union csr_cpath_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsvd : 8; /* [7:0] */ + u32 smu_lastword : 1; /* [8] */ + u32 npu_lastwoed : 1; /* [9] */ + u32 mpu_wdog : 1; /* [10] */ + u32 mpu_lastword : 1; /* [11] */ + u32 wr_phy_timeout : 1; /* [12] */ + u32 wr_mem_timeout : 1; /* [13] */ + u32 wr_reg_timeout : 1; /* [14] */ + u32 sfp_high_temperature_port3 : 1; /* [15] */ + u32 sfp_high_temperature_port2 : 1; /* [16] */ + u32 sfp_high_temperature_port1 : 1; /* [17] */ + u32 sfp_high_temperature_port0 : 1; /* [18] */ + u32 chip_low_temperature : 1; /* [19] */ + u32 chip_high_temperature : 1; /* [20] */ + u32 logic_except : 1; /* [21] */ + u32 host0_heart : 1; /* [22] */ + u32 host1_heart : 1; /* [23] */ + u32 host2_heart : 1; /* [24] */ + u32 host3_heart : 1; /* [25] */ + u32 host4_heart : 1; /* [26] */ + u32 mpu_init_done : 2; /* [28:27] */ + u32 mpu_boot_cause : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_reservd_u; + +/* Define the union csr_cpath_itf_sts_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_itf_sts_out : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_itf_sts_out_u; + +/* Define the union csr_cpath_csr_sfifo_pe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_sfifo_pe1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_sfifo_pe1_u; + +/* Define the union csr_cpath_csr_sfifo_pe0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_sfifo_pe0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_sfifo_pe0_u; + +/* Define the union csr_cpath_csr_sfifo_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_sfifo_pi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_sfifo_pi_u; + +/* Define the union csr_cpath_inbd_sfifo_pe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_sfifo_pe1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_sfifo_pe1_u; + +/* Define the union csr_cpath_inbd_sfifo_pe0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_sfifo_pe0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_sfifo_pe0_u; + +/* Define the union csr_cpath_inbd_sfifo_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_sfifo_pi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_sfifo_pi_u; + +/* Define the union csr_cpath_out_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_out_pls_u; + +/* Define the union csr_glb_ijt_node_id_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ijt_ring_node_id_bitmap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ijt_node_id_bitmap_u; + +/* Define the union csr_glb_ejt_node_id_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ejt_ring_node_id_bitmap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ejt_node_id_bitmap_u; + +/* Define the union csr_cpath_out_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_out_a_fatal_msk_u; + +/* Define the union csr_cpath_out_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_out_a_nonfatal_msk_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck0_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck1_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck2_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck3_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck4_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck5_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck6_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck7_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck8_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck9_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cpath_csr_inj_enj_cnt_u cpath_csr_inj_enj_cnt; /* 10 */ + volatile csr_cpath_inbd_inj_enj_cnt_u cpath_inbd_inj_enj_cnt; /* 14 */ + volatile csr_cpath_non_cpi_int_cnt_u cpath_non_cpi_int_cnt; /* 1C */ + volatile csr_cpath_enj_rsvd_cnt_u cpath_enj_rsvd_cnt; /* 20 */ + volatile csr_cpath_enj_nml_cnt_u cpath_enj_nml_cnt; /* 24 */ + volatile csr_cpath_inbd_oubd_cnt_type_u cpath_inbd_oubd_cnt_type; /* 2C */ + volatile csr_cpath_fifo_aful_gap_0_u cpath_fifo_aful_gap_0; /* 30 */ + volatile csr_cpath_reservd_u cpath_reservd; /* 3C */ + volatile csr_cpath_itf_sts_out_u cpath_itf_sts_out; /* 44 */ + volatile csr_cpath_csr_sfifo_pe1_u cpath_csr_sfifo_pe1; /* 4C */ + volatile csr_cpath_csr_sfifo_pe0_u cpath_csr_sfifo_pe0; /* 50 */ + volatile csr_cpath_csr_sfifo_pi_u cpath_csr_sfifo_pi; /* 54 */ + volatile csr_cpath_inbd_sfifo_pe1_u cpath_inbd_sfifo_pe1; /* 58 */ + volatile csr_cpath_inbd_sfifo_pe0_u cpath_inbd_sfifo_pe0; /* 5C */ + volatile csr_cpath_inbd_sfifo_pi_u cpath_inbd_sfifo_pi; /* 60 */ + volatile csr_cpath_out_pls_u cpath_out_pls; /* 70 */ + volatile csr_glb_ijt_node_id_bitmap_u glb_ijt_node_id_bitmap; /* 80 */ + volatile csr_glb_ejt_node_id_bitmap_u glb_ejt_node_id_bitmap; /* 84 */ + volatile csr_cpath_out_a_fatal_msk_u cpath_out_a_fatal_msk; /* 100 */ + volatile csr_cpath_out_a_nonfatal_msk_u cpath_out_a_nonfatal_msk; /* 104 */ + volatile csr_dfx_cpath_pe_rsp_lck0_u dfx_cpath_pe_rsp_lck0; /* 110 */ + volatile csr_dfx_cpath_pe_rsp_lck1_u dfx_cpath_pe_rsp_lck1; /* 114 */ + volatile csr_dfx_cpath_pe_rsp_lck2_u dfx_cpath_pe_rsp_lck2; /* 118 */ + volatile csr_dfx_cpath_pe_rsp_lck3_u dfx_cpath_pe_rsp_lck3; /* 11C */ + volatile csr_dfx_cpath_pe_rsp_lck4_u dfx_cpath_pe_rsp_lck4; /* 120 */ + volatile csr_dfx_cpath_pe_rsp_lck5_u dfx_cpath_pe_rsp_lck5; /* 124 */ + volatile csr_dfx_cpath_pe_rsp_lck6_u dfx_cpath_pe_rsp_lck6; /* 128 */ + volatile csr_dfx_cpath_pe_rsp_lck7_u dfx_cpath_pe_rsp_lck7; /* 12C */ + volatile csr_dfx_cpath_pe_rsp_lck8_u dfx_cpath_pe_rsp_lck8; /* 130 */ + volatile csr_dfx_cpath_pe_rsp_lck9_u dfx_cpath_pe_rsp_lck9; /* 134 */ +} S_dfx_cpath_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_cpath_csr */ +extern volatile S_dfx_cpath_csr_REGS_TYPE *gopdfx_cpath_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCPATH_CSR_INJ_ENJ_CNT_cpath_csr_enj_cnt(unsigned int ucpath_csr_enj_cnt); +int iSetCPATH_CSR_INJ_ENJ_CNT_cpath_csr_inj_cnt(unsigned int ucpath_csr_inj_cnt); +int iSetCPATH_INBD_INJ_ENJ_CNT_cpath_inbd_enj_cnt(unsigned int ucpath_inbd_enj_cnt); +int iSetCPATH_INBD_INJ_ENJ_CNT_cpath_inbd_inj_cnt(unsigned int ucpath_inbd_inj_cnt); +int iSetCPATH_NON_CPI_INT_CNT_cpath_non_cpi_int_cnt_sf(unsigned int ucpath_non_cpi_int_cnt_sf); +int iSetCPATH_NON_CPI_INT_CNT_cpath_non_cpi_int_cnt_hw(unsigned int ucpath_non_cpi_int_cnt_hw); +int iSetCPATH_ENJ_RSVD_CNT_cpath_inbd_enj_rsvd_cnt(unsigned int ucpath_inbd_enj_rsvd_cnt); +int iSetCPATH_ENJ_RSVD_CNT_cpath_csr_enj_rsvd_cnt(unsigned int ucpath_csr_enj_rsvd_cnt); +int iSetCPATH_ENJ_NML_CNT_cpath_inbd_enj_nml_cnt(unsigned int ucpath_inbd_enj_nml_cnt); +int iSetCPATH_ENJ_NML_CNT_cpath_csr_enj_nml_cnt(unsigned int ucpath_csr_enj_nml_cnt); +int iSetCPATH_INBD_OUBD_CNT_TYPE_cpath_inbd_enj_cnt_type(unsigned int ucpath_inbd_enj_cnt_type); +int iSetCPATH_INBD_OUBD_CNT_TYPE_cpath_inbd_inj_cnt_type(unsigned int ucpath_inbd_inj_cnt_type); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_csr_pe_fifo_aful_gap_cpi(unsigned int ucpath_csr_pe_fifo_aful_gap_cpi); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_csr_pi_fifo_aful_gap_cpi(unsigned int ucpath_csr_pi_fifo_aful_gap_cpi); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_inbd_pe_fifo_aful_gap_cpi(unsigned int ucpath_inbd_pe_fifo_aful_gap_cpi); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_inbd_pi_fifo_aful_gap_cpi(unsigned int ucpath_inbd_pi_fifo_aful_gap_cpi); +int iSetCPATH_RESERVD_cpath_reserved(unsigned int ucpath_reserved); +int iSetCPATH_ITF_STS_OUT_cpath_itf_sts_out(unsigned int ucpath_itf_sts_out); +int iSetCPATH_CSR_SFIFO_PE1_cpath_csr_sfifo_pe1(unsigned int ucpath_csr_sfifo_pe1); +int iSetCPATH_CSR_SFIFO_PE0_cpath_csr_sfifo_pe0(unsigned int ucpath_csr_sfifo_pe0); +int iSetCPATH_CSR_SFIFO_PI_cpath_csr_sfifo_pi(unsigned int ucpath_csr_sfifo_pi); +int iSetCPATH_INBD_SFIFO_PE1_cpath_inbd_sfifo_pe1(unsigned int ucpath_inbd_sfifo_pe1); +int iSetCPATH_INBD_SFIFO_PE0_cpath_inbd_sfifo_pe0(unsigned int ucpath_inbd_sfifo_pe0); +int iSetCPATH_INBD_SFIFO_PI_cpath_inbd_sfifo_pi(unsigned int ucpath_inbd_sfifo_pi); +int iSetCPATH_OUT_PLS_cpath_out_pls(unsigned int ucpath_out_pls); +int iSetGLB_IJT_NODE_ID_BITMAP_glb_ijt_ring_node_id_bitmap(unsigned int uglb_ijt_ring_node_id_bitmap); +int iSetGLB_EJT_NODE_ID_BITMAP_glb_ejt_ring_node_id_bitmap(unsigned int uglb_ejt_ring_node_id_bitmap); +int iSetCPATH_OUT_A_FATAL_MSK_cpath_out_a_fatal_msk(unsigned int ucpath_out_a_fatal_msk); +int iSetCPATH_OUT_A_NONFATAL_MSK_cpath_out_a_nonfatal_msk(unsigned int ucpath_out_a_nonfatal_msk); +int iSetDFX_CPATH_PE_RSP_LCK0_dfx_cpath_pe_rsp_lck0(unsigned int udfx_cpath_pe_rsp_lck0); +int iSetDFX_CPATH_PE_RSP_LCK1_dfx_cpath_pe_rsp_lck1(unsigned int udfx_cpath_pe_rsp_lck1); +int iSetDFX_CPATH_PE_RSP_LCK2_dfx_cpath_pe_rsp_lck2(unsigned int udfx_cpath_pe_rsp_lck2); +int iSetDFX_CPATH_PE_RSP_LCK3_dfx_cpath_pe_rsp_lck3(unsigned int udfx_cpath_pe_rsp_lck3); +int iSetDFX_CPATH_PE_RSP_LCK4_dfx_cpath_pe_rsp_lck4(unsigned int udfx_cpath_pe_rsp_lck4); +int iSetDFX_CPATH_PE_RSP_LCK5_dfx_cpath_pe_rsp_lck5(unsigned int udfx_cpath_pe_rsp_lck5); +int iSetDFX_CPATH_PE_RSP_LCK6_dfx_cpath_pe_rsp_lck6(unsigned int udfx_cpath_pe_rsp_lck6); +int iSetDFX_CPATH_PE_RSP_LCK7_dfx_cpath_pe_rsp_lck7(unsigned int udfx_cpath_pe_rsp_lck7); +int iSetDFX_CPATH_PE_RSP_LCK8_dfx_cpath_pe_rsp_lck8(unsigned int udfx_cpath_pe_rsp_lck8); +int iSetDFX_CPATH_PE_RSP_LCK9_dfx_cpath_pe_rsp_lck9(unsigned int udfx_cpath_pe_rsp_lck9); + +/* Define the union csr_apictl_dbg_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_aeqe_drop_dis : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 api_ctl_dbg_sel : 3; /* [6:4] */ + u32 rsv_1 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_sel_u; + +/* Define the union csr_apictl_af_th0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 16; /* [15:0] */ + u32 apiitf_dir_acc_af_th : 8; /* [23:16] */ + u32 apiitf_inbd_af_th : 5; /* [28:24] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th0_u; + +/* Define the union csr_apictl_af_th1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apiitf_inline_wqe_af_th : 4; /* [3:0] */ + u32 rsv_4 : 4; /* [7:4] */ + u32 apiitf_resp_af_th : 5; /* [12:8] */ + u32 rsv_5 : 3; /* [15:13] */ + u32 api_ctl_upitf_af_th : 6; /* [21:16] */ + u32 rsv_6 : 2; /* [23:22] */ + u32 api_ctl_aeqe_data_af_th : 4; /* [27:24] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th1_u; + +/* Define the union csr_apictl_af_th2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_non_cpi_int_af_th : 9; /* [8:0] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 apiitf_virtio_acc_af_th : 8; /* [23:16] */ + u32 rsv_9 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th2_u; + +/* Define the union csr_apictl_af_th3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apichn_cpld_fifo_af_th : 5; /* [4:0] */ + u32 rsv_10 : 3; /* [7:5] */ + u32 apichn_rsp_fifo_af_th : 4; /* [11:8] */ + u32 api_ctl_nl2_fifo_af_th : 2; /* [13:12] */ + u32 rsv_11 : 2; /* [15:14] */ + u32 api_ctl_tile_acc_fifo_af_th : 10; /* [25:16] */ + u32 rsv_12 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th3_u; + +/* Define the union csr_apictl_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_inbd_noncsr_cnt : 16; /* [15:0] */ + u32 api_ctl_inbd_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt2_u; + +/* Define the union csr_apictl_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_inbd_csr_cnt : 16; /* [15:0] */ + u32 api_ctl_inbd_up_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt3_u; + +/* Define the union csr_apictl_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dir_acc_cnt : 16; /* [15:0] */ + u32 api_ctl_inline_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt4_u; + +/* Define the union csr_apictl_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_up_tx_cnt : 16; /* [15:0] */ + u32 api_ctl_resp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt5_u; + +/* Define the union csr_apictl_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_noncsr_tag : 16; /* [15:0] */ + u32 api_ctl_csr_tag : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt6_u; + +/* Define the union csr_apictl_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chip_type : 2; /* [1:0] */ + u32 chip_ver : 2; /* [3:2] */ + u32 spu_en : 1; /* [4] */ + u32 host_num : 3; /* [7:5] */ + u32 cfg_template_id : 4; /* [11:8] */ + u32 board_type : 8; /* [19:12] */ + u32 board_id : 4; /* [23:20] */ + u32 mpu_ver : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_reservd_u; + +/* Define the union csr_apictl_out_a_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_out_a_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_a_pls_u; + +/* Define the union csr_apictl_out_b_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_out_b_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_b_pls_u; + +/* Define the union csr_apictl_non_csr_timer_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_noncsr_timer_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_non_csr_timer_th_u; + +/* Define the union csr_apictl_csr_timer_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_csr_timer_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_csr_timer_th_u; + +/* Define the union csr_apictl_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_a_u; + +/* Define the union csr_apictl_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_b_u; + +/* Define the union csr_apictl_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_c_u; + +/* Define the union csr_apictl_dbg_out_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_d_u; + +/* Define the union csr_apictl_dbg_out_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_e_u; + +/* Define the union csr_apictl_dbg_out_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_f_u; + +/* Define the union csr_apictl_dbg_out_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_g_u; + +/* Define the union csr_apictl_dbg_out_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_h_u; + +/* Define the union csr_apictl_dbg_out_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_i_u; + +/* Define the union csr_apictl_dbg_out_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_j_u; + +/* Define the union csr_apictl_dbg_out_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_k_u; + +/* Define the union csr_apictl_dbg_out_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_l_u; + +/* Define the union csr_apictl_dbg_out_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_m_u; + +/* Define the union csr_apictl_dbg_out_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_n_u; + +/* Define the union csr_apictl_dbg_out_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_o_u; + +/* Define the union csr_apictl_dbg_out_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_p_u; + +/* Define the union csr_apictl_dbg_out_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_q_u; + +/* Define the union csr_apictl_dbg_out_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_r_u; + +/* Define the union csr_apictl_dbg_out_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_s_u; + +/* Define the union csr_apictl_dbg_out_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_t_u; + +/* Define the union csr_apictl_dbg_out_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_u_u; + +/* Define the union csr_apictl_dbg_out_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_v_u; + +/* Define the union csr_apictl_dbg_out_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_w_u; + +/* Define the union csr_apictl_dbg_out_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_x_u; + +/* Define the union csr_apictl_dbg_out_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_y_u; + +/* Define the union csr_apictl_dbg_out_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_z : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_z_u; + +/* Define the union csr_apictl_dbg_fifo_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_a_u; + +/* Define the union csr_apictl_dbg_fifo_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_b_u; + +/* Define the union csr_apictl_dbg_fifo_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_c_u; + +/* Define the union csr_apictl_dbg_fifo_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_d_u; + +/* Define the union csr_apictl_dbg_fifo_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_e_u; + +/* Define the union csr_apictl_dbg_fifo_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_f_u; + +/* Define the union csr_apictl_dbg_fifo_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_g_u; + +/* Define the union csr_apictl_dbg_fifo_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_h_u; + +/* Define the union csr_apictl_dbg_fifo_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_i_u; + +/* Define the union csr_apictl_dbg_fifo_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_j_u; + +/* Define the union csr_apictl_dbg_fifo_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_k_u; + +/* Define the union csr_apictl_dbg_fifo_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_l_u; + +/* Define the union csr_apictl_dbg_fifo_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_m_u; + +/* Define the union csr_apictl_dbg_fifo_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_n_u; + +/* Define the union csr_apictl_dbg_fifo_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_o_u; + +/* Define the union csr_apictl_dbg_fifo_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_p_u; + +/* Define the union csr_apictl_dbg_fifo_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_q_u; + +/* Define the union csr_apictl_dbg_fifo_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_r_u; + +/* Define the union csr_apictl_dbg_fifo_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_s_u; + +/* Define the union csr_inbd_ring_buf_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_inbd_ring_buf_crdt : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_inbd_ring_buf_crdt_u; + +/* Define the union csr_inbd_cmd_rd_so_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_inbd_cmd_rd_so_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_inbd_cmd_rd_so_ro_u; + +/* Define the union csr_tilep_dfx_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cur_st : 8; /* [7:0] */ + u32 tilep_fifo_cmd_cnt : 8; /* [15:8] */ + u32 tilep_indir_sts : 1; /* [16] */ + u32 apictl_tile_rsp_err_lock : 1; /* [17] */ + u32 tilep_e0_err : 1; /* [18] */ + u32 rsv_14 : 5; /* [23:19] */ + u32 tilep_err_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_ro_0_u; + +/* Define the union csr_tilep_dfx_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_wr_dat_cnt : 5; /* [4:0] */ + u32 rsv_15 : 3; /* [7:5] */ + u32 tilep_indir_rd_tx_rsp_cnt : 5; /* [12:8] */ + u32 rsv_16 : 3; /* [15:13] */ + u32 tilep_rd_dat_cnt : 5; /* [20:16] */ + u32 rsv_17 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_ro_1_u; + +/* Define the union csr_tilep_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cmd_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_0_u; + +/* Define the union csr_tilep_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cmd_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_1_u; + +/* Define the union csr_tilep_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cmd_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_2_u; + +/* Define the union csr_tilep_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_csr_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_3_u; + +/* Define the union csr_tilep_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_rd_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_4_u; + +/* Define the union csr_tilep_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_wr_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_5_u; + +/* Define the union csr_tilep_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_tx_api_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_6_u; + +/* Define the union csr_tilep_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_tx_api_np_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_7_u; + +/* Define the union csr_tilep_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rx_api_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_8_u; + +/* Define the union csr_tilep_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rx_api_rsp_e0_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_9_u; + +/* Define the union csr_tilep_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rx_api_rsp_sts_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_10_u; + +/* Define the union csr_tilep_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_poll_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_11_u; + +/* Define the union csr_tilep_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rtn_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_12_u; + +/* Define the union csr_tilep_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_csr_no_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_13_u; + +/* Define the union csr_tilep_dfx_cnt_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_no_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_14_u; + +/* Define the union csr_nl2_dfx_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_acc_cur_st : 3; /* [2:0] */ + u32 rsv_18 : 1; /* [3] */ + u32 nl2_finish_cur_st : 4; /* [7:4] */ + u32 nl2_acc_crdt_cnt : 5; /* [12:8] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 first_available_ctx_idx : 4; /* [19:16] */ + u32 cur_rsp_ctx_idx : 4; /* [23:20] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_ro_0_u; + +/* Define the union csr_nl2_dfx_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_ctx_sm_miss : 16; /* [15:0] */ + u32 nl2_ctx_vld : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_ro_1_u; + +/* Define the union csr_nl2_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_0_u; + +/* Define the union csr_nl2_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_1_u; + +/* Define the union csr_nl2_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_2_u; + +/* Define the union csr_nl2_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_3_u; + +/* Define the union csr_nl2_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_4_u; + +/* Define the union csr_nl2_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_5_u; + +/* Define the union csr_nl2_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_cmd_tx_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_6_u; + +/* Define the union csr_nl2_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_rsp_rx_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_7_u; + +/* Define the union csr_nl2_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_rsp_rx_miss_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_8_u; + +/* Define the union csr_nl2_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_rsp_rx_abort_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_9_u; + +/* Define the union csr_nl2_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_done_success_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_10_u; + +/* Define the union csr_nl2_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_done_fail_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_11_u; + +/* Define the union csr_nl2_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_set_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_12_u; + +/* Define the union csr_nl2_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_set_rej_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_13_u; + +/* Define the union csr_apictl_out_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_a_fatal_msk_u; + +/* Define the union csr_apictl_out_b_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_b_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_b_fatal_msk_u; + +/* Define the union csr_apictl_out_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_a_nonfatal_msk_u; + +/* Define the union csr_apictl_out_b_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_b_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_b_nonfatal_msk_u; + +/* Define the union csr_glb_api_chn_right_ctl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_chn_root_right : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_api_chn_right_ctl0_u; + +/* Define the union csr_glb_api_chn_right_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_chn_non_bypass_right : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_api_chn_right_ctl1_u; + +/* Define the union csr_glb_api_chn_right_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_chn_other_right : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_api_chn_right_ctl2_u; + +/* Define the union csr_apictl_tag_cmp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_csr_tag_cmp_th : 6; /* [5:0] */ + u32 rsv_21 : 2; /* [7:6] */ + u32 apictl_noncsr_tag_cmp_th : 6; /* [13:8] */ + u32 rsv_22 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_tag_cmp_th_u; + +/* Define the union csr_apiitf_dfx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_virtio_cnt : 16; /* [15:0] */ + u32 api_ctl_tile_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_dfx_cnt0_u; + +/* Define the union csr_apiitf_dfx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_csr_wr_dest_illg_cnt : 16; /* [15:0] */ + u32 api_ctl_csr_rd_dest_illg_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_dfx_cnt1_u; + +/* Define the union csr_apiitf_dfx_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_noncsr_wr_dest_illg_cnt : 16; /* [15:0] */ + u32 api_ctl_noncsr_rd_dest_illg_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_dfx_cnt2_u; + +/* Define the union csr_apiitf_ring_dest_illg_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apiitf_ring_dest_illg_src : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_ring_dest_illg_src_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_apictl_dbg_sel_u apictl_dbg_sel; /* 0 */ + volatile csr_apictl_af_th0_u apictl_af_th0; /* 4 */ + volatile csr_apictl_af_th1_u apictl_af_th1; /* 8 */ + volatile csr_apictl_af_th2_u apictl_af_th2; /* C */ + volatile csr_apictl_af_th3_u apictl_af_th3; /* 10 */ + volatile csr_apictl_cnt2_u apictl_cnt2; /* 18 */ + volatile csr_apictl_cnt3_u apictl_cnt3; /* 1C */ + volatile csr_apictl_cnt4_u apictl_cnt4; /* 20 */ + volatile csr_apictl_cnt5_u apictl_cnt5; /* 24 */ + volatile csr_apictl_cnt6_u apictl_cnt6; /* 28 */ + volatile csr_apictl_reservd_u apictl_reservd; /* 2C */ + volatile csr_apictl_out_a_pls_u apictl_out_a_pls; /* 30 */ + volatile csr_apictl_out_b_pls_u apictl_out_b_pls; /* 34 */ + volatile csr_apictl_non_csr_timer_th_u apictl_non_csr_timer_th; /* 38 */ + volatile csr_apictl_csr_timer_th_u apictl_csr_timer_th; /* 3C */ + volatile csr_apictl_dbg_out_a_u apictl_dbg_out_a; /* 40 */ + volatile csr_apictl_dbg_out_b_u apictl_dbg_out_b; /* 44 */ + volatile csr_apictl_dbg_out_c_u apictl_dbg_out_c; /* 48 */ + volatile csr_apictl_dbg_out_d_u apictl_dbg_out_d; /* 4C */ + volatile csr_apictl_dbg_out_e_u apictl_dbg_out_e; /* 50 */ + volatile csr_apictl_dbg_out_f_u apictl_dbg_out_f; /* 54 */ + volatile csr_apictl_dbg_out_g_u apictl_dbg_out_g; /* 58 */ + volatile csr_apictl_dbg_out_h_u apictl_dbg_out_h; /* 5C */ + volatile csr_apictl_dbg_out_i_u apictl_dbg_out_i; /* 60 */ + volatile csr_apictl_dbg_out_j_u apictl_dbg_out_j; /* 64 */ + volatile csr_apictl_dbg_out_k_u apictl_dbg_out_k; /* 68 */ + volatile csr_apictl_dbg_out_l_u apictl_dbg_out_l; /* 6C */ + volatile csr_apictl_dbg_out_m_u apictl_dbg_out_m; /* 70 */ + volatile csr_apictl_dbg_out_n_u apictl_dbg_out_n; /* 74 */ + volatile csr_apictl_dbg_out_o_u apictl_dbg_out_o; /* 78 */ + volatile csr_apictl_dbg_out_p_u apictl_dbg_out_p; /* 7C */ + volatile csr_apictl_dbg_out_q_u apictl_dbg_out_q; /* 80 */ + volatile csr_apictl_dbg_out_r_u apictl_dbg_out_r; /* 84 */ + volatile csr_apictl_dbg_out_s_u apictl_dbg_out_s; /* 88 */ + volatile csr_apictl_dbg_out_t_u apictl_dbg_out_t; /* 8C */ + volatile csr_apictl_dbg_out_u_u apictl_dbg_out_u; /* 90 */ + volatile csr_apictl_dbg_out_v_u apictl_dbg_out_v; /* 94 */ + volatile csr_apictl_dbg_out_w_u apictl_dbg_out_w; /* 98 */ + volatile csr_apictl_dbg_out_x_u apictl_dbg_out_x; /* 9C */ + volatile csr_apictl_dbg_out_y_u apictl_dbg_out_y; /* A0 */ + volatile csr_apictl_dbg_out_z_u apictl_dbg_out_z; /* A4 */ + volatile csr_apictl_dbg_fifo_a_u apictl_dbg_fifo_a; /* B0 */ + volatile csr_apictl_dbg_fifo_b_u apictl_dbg_fifo_b; /* B4 */ + volatile csr_apictl_dbg_fifo_c_u apictl_dbg_fifo_c; /* B8 */ + volatile csr_apictl_dbg_fifo_d_u apictl_dbg_fifo_d; /* BC */ + volatile csr_apictl_dbg_fifo_e_u apictl_dbg_fifo_e; /* C0 */ + volatile csr_apictl_dbg_fifo_f_u apictl_dbg_fifo_f; /* C4 */ + volatile csr_apictl_dbg_fifo_g_u apictl_dbg_fifo_g; /* C8 */ + volatile csr_apictl_dbg_fifo_h_u apictl_dbg_fifo_h; /* CC */ + volatile csr_apictl_dbg_fifo_i_u apictl_dbg_fifo_i; /* D0 */ + volatile csr_apictl_dbg_fifo_j_u apictl_dbg_fifo_j; /* D4 */ + volatile csr_apictl_dbg_fifo_k_u apictl_dbg_fifo_k; /* D8 */ + volatile csr_apictl_dbg_fifo_l_u apictl_dbg_fifo_l; /* DC */ + volatile csr_apictl_dbg_fifo_m_u apictl_dbg_fifo_m; /* E0 */ + volatile csr_apictl_dbg_fifo_n_u apictl_dbg_fifo_n; /* E4 */ + volatile csr_apictl_dbg_fifo_o_u apictl_dbg_fifo_o; /* E8 */ + volatile csr_apictl_dbg_fifo_p_u apictl_dbg_fifo_p; /* EC */ + volatile csr_apictl_dbg_fifo_q_u apictl_dbg_fifo_q; /* F0 */ + volatile csr_apictl_dbg_fifo_r_u apictl_dbg_fifo_r; /* F4 */ + volatile csr_apictl_dbg_fifo_s_u apictl_dbg_fifo_s; /* F8 */ + volatile csr_inbd_ring_buf_crdt_u inbd_ring_buf_crdt; /* 108 */ + volatile csr_inbd_cmd_rd_so_ro_u inbd_cmd_rd_so_ro; /* 10C */ + volatile csr_tilep_dfx_ro_0_u tilep_dfx_ro_0; /* 110 */ + volatile csr_tilep_dfx_ro_1_u tilep_dfx_ro_1; /* 114 */ + volatile csr_tilep_dfx_cnt_0_u tilep_dfx_cnt_0; /* 118 */ + volatile csr_tilep_dfx_cnt_1_u tilep_dfx_cnt_1; /* 11C */ + volatile csr_tilep_dfx_cnt_2_u tilep_dfx_cnt_2; /* 120 */ + volatile csr_tilep_dfx_cnt_3_u tilep_dfx_cnt_3; /* 124 */ + volatile csr_tilep_dfx_cnt_4_u tilep_dfx_cnt_4; /* 128 */ + volatile csr_tilep_dfx_cnt_5_u tilep_dfx_cnt_5; /* 12C */ + volatile csr_tilep_dfx_cnt_6_u tilep_dfx_cnt_6; /* 130 */ + volatile csr_tilep_dfx_cnt_7_u tilep_dfx_cnt_7; /* 134 */ + volatile csr_tilep_dfx_cnt_8_u tilep_dfx_cnt_8; /* 138 */ + volatile csr_tilep_dfx_cnt_9_u tilep_dfx_cnt_9; /* 13C */ + volatile csr_tilep_dfx_cnt_10_u tilep_dfx_cnt_10; /* 140 */ + volatile csr_tilep_dfx_cnt_11_u tilep_dfx_cnt_11; /* 144 */ + volatile csr_tilep_dfx_cnt_12_u tilep_dfx_cnt_12; /* 148 */ + volatile csr_tilep_dfx_cnt_13_u tilep_dfx_cnt_13; /* 14C */ + volatile csr_tilep_dfx_cnt_14_u tilep_dfx_cnt_14; /* 150 */ + volatile csr_nl2_dfx_ro_0_u nl2_dfx_ro_0; /* 180 */ + volatile csr_nl2_dfx_ro_1_u nl2_dfx_ro_1; /* 184 */ + volatile csr_nl2_dfx_cnt_0_u nl2_dfx_cnt_0; /* 188 */ + volatile csr_nl2_dfx_cnt_1_u nl2_dfx_cnt_1; /* 18C */ + volatile csr_nl2_dfx_cnt_2_u nl2_dfx_cnt_2; /* 190 */ + volatile csr_nl2_dfx_cnt_3_u nl2_dfx_cnt_3; /* 194 */ + volatile csr_nl2_dfx_cnt_4_u nl2_dfx_cnt_4; /* 198 */ + volatile csr_nl2_dfx_cnt_5_u nl2_dfx_cnt_5; /* 19C */ + volatile csr_nl2_dfx_cnt_6_u nl2_dfx_cnt_6; /* 1A0 */ + volatile csr_nl2_dfx_cnt_7_u nl2_dfx_cnt_7; /* 1A4 */ + volatile csr_nl2_dfx_cnt_8_u nl2_dfx_cnt_8; /* 1A8 */ + volatile csr_nl2_dfx_cnt_9_u nl2_dfx_cnt_9; /* 1AC */ + volatile csr_nl2_dfx_cnt_10_u nl2_dfx_cnt_10; /* 1B0 */ + volatile csr_nl2_dfx_cnt_11_u nl2_dfx_cnt_11; /* 1B4 */ + volatile csr_nl2_dfx_cnt_12_u nl2_dfx_cnt_12; /* 1B8 */ + volatile csr_nl2_dfx_cnt_13_u nl2_dfx_cnt_13; /* 1BC */ + volatile csr_apictl_out_a_fatal_msk_u apictl_out_a_fatal_msk; /* 200 */ + volatile csr_apictl_out_b_fatal_msk_u apictl_out_b_fatal_msk; /* 204 */ + volatile csr_apictl_out_a_nonfatal_msk_u apictl_out_a_nonfatal_msk; /* 210 */ + volatile csr_apictl_out_b_nonfatal_msk_u apictl_out_b_nonfatal_msk; /* 214 */ + volatile csr_glb_api_chn_right_ctl0_u glb_api_chn_right_ctl0; /* 220 */ + volatile csr_glb_api_chn_right_ctl1_u glb_api_chn_right_ctl1; /* 224 */ + volatile csr_glb_api_chn_right_ctl2_u glb_api_chn_right_ctl2; /* 228 */ + volatile csr_apictl_tag_cmp_th_u apictl_tag_cmp_th; /* 230 */ + volatile csr_apiitf_dfx_cnt0_u apiitf_dfx_cnt0; /* 240 */ + volatile csr_apiitf_dfx_cnt1_u apiitf_dfx_cnt1; /* 244 */ + volatile csr_apiitf_dfx_cnt2_u apiitf_dfx_cnt2; /* 248 */ + volatile csr_apiitf_ring_dest_illg_src_u apiitf_ring_dest_illg_src; /* 24C */ +} S_dfx_apictl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_apictl_csr */ +extern volatile S_dfx_apictl_csr_REGS_TYPE *gopdfx_apictl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAPICTL_DBG_SEL_api_ctl_aeqe_drop_dis(unsigned int uapi_ctl_aeqe_drop_dis); +int iSetAPICTL_DBG_SEL_api_ctl_dbg_sel(unsigned int uapi_ctl_dbg_sel); +int iSetAPICTL_AF_TH0_apiitf_dir_acc_af_th(unsigned int uapiitf_dir_acc_af_th); +int iSetAPICTL_AF_TH0_apiitf_inbd_af_th(unsigned int uapiitf_inbd_af_th); +int iSetAPICTL_AF_TH1_apiitf_inline_wqe_af_th(unsigned int uapiitf_inline_wqe_af_th); +int iSetAPICTL_AF_TH1_apiitf_resp_af_th(unsigned int uapiitf_resp_af_th); +int iSetAPICTL_AF_TH1_api_ctl_upitf_af_th(unsigned int uapi_ctl_upitf_af_th); +int iSetAPICTL_AF_TH1_api_ctl_aeqe_data_af_th(unsigned int uapi_ctl_aeqe_data_af_th); +int iSetAPICTL_AF_TH2_api_ctl_non_cpi_int_af_th(unsigned int uapi_ctl_non_cpi_int_af_th); +int iSetAPICTL_AF_TH2_apiitf_virtio_acc_af_th(unsigned int uapiitf_virtio_acc_af_th); +int iSetAPICTL_AF_TH3_apichn_cpld_fifo_af_th(unsigned int uapichn_cpld_fifo_af_th); +int iSetAPICTL_AF_TH3_apichn_rsp_fifo_af_th(unsigned int uapichn_rsp_fifo_af_th); +int iSetAPICTL_AF_TH3_api_ctl_nl2_fifo_af_th(unsigned int uapi_ctl_nl2_fifo_af_th); +int iSetAPICTL_AF_TH3_api_ctl_tile_acc_fifo_af_th(unsigned int uapi_ctl_tile_acc_fifo_af_th); +int iSetAPICTL_CNT2_api_ctl_inbd_noncsr_cnt(unsigned int uapi_ctl_inbd_noncsr_cnt); +int iSetAPICTL_CNT2_api_ctl_inbd_cnt(unsigned int uapi_ctl_inbd_cnt); +int iSetAPICTL_CNT3_api_ctl_inbd_csr_cnt(unsigned int uapi_ctl_inbd_csr_cnt); +int iSetAPICTL_CNT3_api_ctl_inbd_up_cnt(unsigned int uapi_ctl_inbd_up_cnt); +int iSetAPICTL_CNT4_api_ctl_dir_acc_cnt(unsigned int uapi_ctl_dir_acc_cnt); +int iSetAPICTL_CNT4_api_ctl_inline_cnt(unsigned int uapi_ctl_inline_cnt); +int iSetAPICTL_CNT5_api_ctl_up_tx_cnt(unsigned int uapi_ctl_up_tx_cnt); +int iSetAPICTL_CNT5_api_ctl_resp_cnt(unsigned int uapi_ctl_resp_cnt); +int iSetAPICTL_CNT6_api_ctl_noncsr_tag(unsigned int uapi_ctl_noncsr_tag); +int iSetAPICTL_CNT6_api_ctl_csr_tag(unsigned int uapi_ctl_csr_tag); +int iSetAPICTL_RESERVD_apictl_reserved(unsigned int uapictl_reserved); +int iSetAPICTL_OUT_A_PLS_api_ctl_out_a_pls(unsigned int uapi_ctl_out_a_pls); +int iSetAPICTL_OUT_B_PLS_api_ctl_out_b_pls(unsigned int uapi_ctl_out_b_pls); +int iSetAPICTL_NON_CSR_TIMER_TH_api_ctl_noncsr_timer_th(unsigned int uapi_ctl_noncsr_timer_th); +int iSetAPICTL_CSR_TIMER_TH_api_ctl_csr_timer_th(unsigned int uapi_ctl_csr_timer_th); +int iSetAPICTL_DBG_OUT_A_api_ctl_dbg_out_a(unsigned int uapi_ctl_dbg_out_a); +int iSetAPICTL_DBG_OUT_B_api_ctl_dbg_out_b(unsigned int uapi_ctl_dbg_out_b); +int iSetAPICTL_DBG_OUT_C_api_ctl_dbg_out_c(unsigned int uapi_ctl_dbg_out_c); +int iSetAPICTL_DBG_OUT_D_api_ctl_dbg_out_d(unsigned int uapi_ctl_dbg_out_d); +int iSetAPICTL_DBG_OUT_E_api_ctl_dbg_out_e(unsigned int uapi_ctl_dbg_out_e); +int iSetAPICTL_DBG_OUT_F_api_ctl_dbg_out_f(unsigned int uapi_ctl_dbg_out_f); +int iSetAPICTL_DBG_OUT_G_api_ctl_dbg_out_g(unsigned int uapi_ctl_dbg_out_g); +int iSetAPICTL_DBG_OUT_H_api_ctl_dbg_out_h(unsigned int uapi_ctl_dbg_out_h); +int iSetAPICTL_DBG_OUT_I_api_ctl_dbg_out_i(unsigned int uapi_ctl_dbg_out_i); +int iSetAPICTL_DBG_OUT_J_api_ctl_dbg_out_j(unsigned int uapi_ctl_dbg_out_j); +int iSetAPICTL_DBG_OUT_K_api_ctl_dbg_out_k(unsigned int uapi_ctl_dbg_out_k); +int iSetAPICTL_DBG_OUT_L_api_ctl_dbg_out_l(unsigned int uapi_ctl_dbg_out_l); +int iSetAPICTL_DBG_OUT_M_api_ctl_dbg_out_m(unsigned int uapi_ctl_dbg_out_m); +int iSetAPICTL_DBG_OUT_N_api_ctl_dbg_out_n(unsigned int uapi_ctl_dbg_out_n); +int iSetAPICTL_DBG_OUT_O_api_ctl_dbg_out_o(unsigned int uapi_ctl_dbg_out_o); +int iSetAPICTL_DBG_OUT_P_api_ctl_dbg_out_p(unsigned int uapi_ctl_dbg_out_p); +int iSetAPICTL_DBG_OUT_Q_api_ctl_dbg_out_q(unsigned int uapi_ctl_dbg_out_q); +int iSetAPICTL_DBG_OUT_R_api_ctl_dbg_out_r(unsigned int uapi_ctl_dbg_out_r); +int iSetAPICTL_DBG_OUT_S_api_ctl_dbg_out_s(unsigned int uapi_ctl_dbg_out_s); +int iSetAPICTL_DBG_OUT_T_api_ctl_dbg_out_t(unsigned int uapi_ctl_dbg_out_t); +int iSetAPICTL_DBG_OUT_U_api_ctl_dbg_out_u(unsigned int uapi_ctl_dbg_out_u); +int iSetAPICTL_DBG_OUT_V_api_ctl_dbg_out_v(unsigned int uapi_ctl_dbg_out_v); +int iSetAPICTL_DBG_OUT_W_api_ctl_dbg_out_w(unsigned int uapi_ctl_dbg_out_w); +int iSetAPICTL_DBG_OUT_X_api_ctl_dbg_out_x(unsigned int uapi_ctl_dbg_out_x); +int iSetAPICTL_DBG_OUT_Y_api_ctl_dbg_out_y(unsigned int uapi_ctl_dbg_out_y); +int iSetAPICTL_DBG_OUT_Z_api_ctl_dbg_out_z(unsigned int uapi_ctl_dbg_out_z); +int iSetAPICTL_DBG_FIFO_A_api_ctl_dbg_fifo_a(unsigned int uapi_ctl_dbg_fifo_a); +int iSetAPICTL_DBG_FIFO_B_api_ctl_dbg_fifo_b(unsigned int uapi_ctl_dbg_fifo_b); +int iSetAPICTL_DBG_FIFO_C_api_ctl_dbg_fifo_c(unsigned int uapi_ctl_dbg_fifo_c); +int iSetAPICTL_DBG_FIFO_D_api_ctl_dbg_fifo_d(unsigned int uapi_ctl_dbg_fifo_d); +int iSetAPICTL_DBG_FIFO_E_api_ctl_dbg_fifo_e(unsigned int uapi_ctl_dbg_fifo_e); +int iSetAPICTL_DBG_FIFO_F_api_ctl_dbg_fifo_f(unsigned int uapi_ctl_dbg_fifo_f); +int iSetAPICTL_DBG_FIFO_G_api_ctl_dbg_fifo_g(unsigned int uapi_ctl_dbg_fifo_g); +int iSetAPICTL_DBG_FIFO_H_api_ctl_dbg_fifo_h(unsigned int uapi_ctl_dbg_fifo_h); +int iSetAPICTL_DBG_FIFO_I_api_ctl_dbg_fifo_i(unsigned int uapi_ctl_dbg_fifo_i); +int iSetAPICTL_DBG_FIFO_J_api_ctl_dbg_fifo_j(unsigned int uapi_ctl_dbg_fifo_j); +int iSetAPICTL_DBG_FIFO_K_api_ctl_dbg_fifo_k(unsigned int uapi_ctl_dbg_fifo_k); +int iSetAPICTL_DBG_FIFO_L_api_ctl_dbg_fifo_l(unsigned int uapi_ctl_dbg_fifo_l); +int iSetAPICTL_DBG_FIFO_M_api_ctl_dbg_fifo_m(unsigned int uapi_ctl_dbg_fifo_m); +int iSetAPICTL_DBG_FIFO_N_api_ctl_dbg_fifo_n(unsigned int uapi_ctl_dbg_fifo_n); +int iSetAPICTL_DBG_FIFO_O_api_ctl_dbg_fifo_o(unsigned int uapi_ctl_dbg_fifo_o); +int iSetAPICTL_DBG_FIFO_P_api_ctl_dbg_fifo_p(unsigned int uapi_ctl_dbg_fifo_p); +int iSetAPICTL_DBG_FIFO_Q_api_ctl_dbg_fifo_q(unsigned int uapi_ctl_dbg_fifo_q); +int iSetAPICTL_DBG_FIFO_R_api_ctl_dbg_fifo_r(unsigned int uapi_ctl_dbg_fifo_r); +int iSetAPICTL_DBG_FIFO_S_api_ctl_dbg_fifo_s(unsigned int uapi_ctl_dbg_fifo_s); +int iSetINBD_RING_BUF_CRDT_api_inbd_ring_buf_crdt(unsigned int uapi_inbd_ring_buf_crdt); +int iSetINBD_CMD_RD_SO_RO_api_inbd_cmd_rd_so_ro(unsigned int uapi_inbd_cmd_rd_so_ro); +int iSetTILEP_DFX_RO_0_tilep_cur_st(unsigned int utilep_cur_st); +int iSetTILEP_DFX_RO_0_tilep_fifo_cmd_cnt(unsigned int utilep_fifo_cmd_cnt); +int iSetTILEP_DFX_RO_0_tilep_indir_sts(unsigned int utilep_indir_sts); +int iSetTILEP_DFX_RO_0_apictl_tile_rsp_err_lock(unsigned int uapictl_tile_rsp_err_lock); +int iSetTILEP_DFX_RO_0_tilep_e0_err(unsigned int utilep_e0_err); +int iSetTILEP_DFX_RO_0_tilep_err_code(unsigned int utilep_err_code); +int iSetTILEP_DFX_RO_1_tilep_wr_dat_cnt(unsigned int utilep_wr_dat_cnt); +int iSetTILEP_DFX_RO_1_tilep_indir_rd_tx_rsp_cnt(unsigned int utilep_indir_rd_tx_rsp_cnt); +int iSetTILEP_DFX_RO_1_tilep_rd_dat_cnt(unsigned int utilep_rd_dat_cnt); +int iSetTILEP_DFX_CNT_0_tilep_cmd_total_cnt(unsigned int utilep_cmd_total_cnt); +int iSetTILEP_DFX_CNT_1_tilep_cmd_err_cnt(unsigned int utilep_cmd_err_cnt); +int iSetTILEP_DFX_CNT_2_tilep_cmd_ok_cnt(unsigned int utilep_cmd_ok_cnt); +int iSetTILEP_DFX_CNT_3_tilep_csr_cmd_cnt(unsigned int utilep_csr_cmd_cnt); +int iSetTILEP_DFX_CNT_4_tilep_indir_rd_cmd_cnt(unsigned int utilep_indir_rd_cmd_cnt); +int iSetTILEP_DFX_CNT_5_tilep_indir_wr_cmd_cnt(unsigned int utilep_indir_wr_cmd_cnt); +int iSetTILEP_DFX_CNT_6_tilep_tx_api_req_cnt(unsigned int utilep_tx_api_req_cnt); +int iSetTILEP_DFX_CNT_7_tilep_tx_api_np_req_cnt(unsigned int utilep_tx_api_np_req_cnt); +int iSetTILEP_DFX_CNT_8_tilep_rx_api_rsp_cnt(unsigned int utilep_rx_api_rsp_cnt); +int iSetTILEP_DFX_CNT_9_tilep_rx_api_rsp_e0_err_cnt(unsigned int utilep_rx_api_rsp_e0_err_cnt); +int iSetTILEP_DFX_CNT_10_tilep_rx_api_rsp_sts_err_cnt(unsigned int utilep_rx_api_rsp_sts_err_cnt); +int iSetTILEP_DFX_CNT_11_tilep_poll_req_cnt(unsigned int utilep_poll_req_cnt); +int iSetTILEP_DFX_CNT_12_tilep_rtn_rsp_cnt(unsigned int utilep_rtn_rsp_cnt); +int iSetTILEP_DFX_CNT_13_tilep_csr_no_ack_cnt(unsigned int utilep_csr_no_ack_cnt); +int iSetTILEP_DFX_CNT_14_tilep_indir_no_ack_cnt(unsigned int utilep_indir_no_ack_cnt); +int iSetNL2_DFX_RO_0_nl2_acc_cur_st(unsigned int unl2_acc_cur_st); +int iSetNL2_DFX_RO_0_nl2_finish_cur_st(unsigned int unl2_finish_cur_st); +int iSetNL2_DFX_RO_0_nl2_acc_crdt_cnt(unsigned int unl2_acc_crdt_cnt); +int iSetNL2_DFX_RO_0_first_available_ctx_idx(unsigned int ufirst_available_ctx_idx); +int iSetNL2_DFX_RO_0_cur_rsp_ctx_idx(unsigned int ucur_rsp_ctx_idx); +int iSetNL2_DFX_RO_1_nl2_ctx_sm_miss(unsigned int unl2_ctx_sm_miss); +int iSetNL2_DFX_RO_1_nl2_ctx_vld(unsigned int unl2_ctx_vld); +int iSetNL2_DFX_CNT_0_nl2_cmd_rev_total_cnt(unsigned int unl2_cmd_rev_total_cnt); +int iSetNL2_DFX_CNT_1_nl2_cmd_rev_prt0_cnt(unsigned int unl2_cmd_rev_prt0_cnt); +int iSetNL2_DFX_CNT_2_nl2_cmd_rev_prt1_cnt(unsigned int unl2_cmd_rev_prt1_cnt); +int iSetNL2_DFX_CNT_3_nl2_cmd_rev_prt2_cnt(unsigned int unl2_cmd_rev_prt2_cnt); +int iSetNL2_DFX_CNT_4_nl2_cmd_rev_prt3_cnt(unsigned int unl2_cmd_rev_prt3_cnt); +int iSetNL2_DFX_CNT_5_nl2_cmd_rev_prt4_cnt(unsigned int unl2_cmd_rev_prt4_cnt); +int iSetNL2_DFX_CNT_6_nl2_sub_cmd_tx_total_cnt(unsigned int unl2_sub_cmd_tx_total_cnt); +int iSetNL2_DFX_CNT_7_nl2_sub_rsp_rx_total_cnt(unsigned int unl2_sub_rsp_rx_total_cnt); +int iSetNL2_DFX_CNT_8_nl2_sub_rsp_rx_miss_cnt(unsigned int unl2_sub_rsp_rx_miss_cnt); +int iSetNL2_DFX_CNT_9_nl2_sub_rsp_rx_abort_cnt(unsigned int unl2_sub_rsp_rx_abort_cnt); +int iSetNL2_DFX_CNT_10_nl2_rtn_icpl_done_success_cnt(unsigned int unl2_rtn_icpl_done_success_cnt); +int iSetNL2_DFX_CNT_11_nl2_rtn_icpl_done_fail_cnt(unsigned int unl2_rtn_icpl_done_fail_cnt); +int iSetNL2_DFX_CNT_12_nl2_rtn_icpl_set_vld_cnt(unsigned int unl2_rtn_icpl_set_vld_cnt); +int iSetNL2_DFX_CNT_13_nl2_rtn_icpl_set_rej_cnt(unsigned int unl2_rtn_icpl_set_rej_cnt); +int iSetAPICTL_OUT_A_FATAL_MSK_apictl_out_a_fatal_msk(unsigned int uapictl_out_a_fatal_msk); +int iSetAPICTL_OUT_B_FATAL_MSK_apictl_out_b_fatal_msk(unsigned int uapictl_out_b_fatal_msk); +int iSetAPICTL_OUT_A_NONFATAL_MSK_apictl_out_a_nonfatal_msk(unsigned int uapictl_out_a_nonfatal_msk); +int iSetAPICTL_OUT_B_NONFATAL_MSK_apictl_out_b_nonfatal_msk(unsigned int uapictl_out_b_nonfatal_msk); +int iSetGLB_API_CHN_RIGHT_CTL0_glb_api_chn_root_right(unsigned int uglb_api_chn_root_right); +int iSetGLB_API_CHN_RIGHT_CTL1_glb_api_chn_non_bypass_right(unsigned int uglb_api_chn_non_bypass_right); +int iSetGLB_API_CHN_RIGHT_CTL2_glb_api_chn_other_right(unsigned int uglb_api_chn_other_right); +int iSetAPICTL_TAG_CMP_TH_apictl_csr_tag_cmp_th(unsigned int uapictl_csr_tag_cmp_th); +int iSetAPICTL_TAG_CMP_TH_apictl_noncsr_tag_cmp_th(unsigned int uapictl_noncsr_tag_cmp_th); +int iSetAPIITF_DFX_CNT0_api_ctl_virtio_cnt(unsigned int uapi_ctl_virtio_cnt); +int iSetAPIITF_DFX_CNT0_api_ctl_tile_cnt(unsigned int uapi_ctl_tile_cnt); +int iSetAPIITF_DFX_CNT1_api_ctl_csr_wr_dest_illg_cnt(unsigned int uapi_ctl_csr_wr_dest_illg_cnt); +int iSetAPIITF_DFX_CNT1_api_ctl_csr_rd_dest_illg_cnt(unsigned int uapi_ctl_csr_rd_dest_illg_cnt); +int iSetAPIITF_DFX_CNT2_api_ctl_noncsr_wr_dest_illg_cnt(unsigned int uapi_ctl_noncsr_wr_dest_illg_cnt); +int iSetAPIITF_DFX_CNT2_api_ctl_noncsr_rd_dest_illg_cnt(unsigned int uapi_ctl_noncsr_rd_dest_illg_cnt); +int iSetAPIITF_RING_DEST_ILLG_SRC_apiitf_ring_dest_illg_src(unsigned int uapiitf_ring_dest_illg_src); + +/* Define the union csr_dma_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_indrect_addr : 16; /* [15:0] */ + u32 rsv_0 : 8; /* [23:16] */ + u32 dma_indrect_tab : 4; /* [27:24] */ + u32 dma_indrect_status : 2; /* [29:28] */ + u32 dma_indrect_mode : 1; /* [30] */ + u32 dma_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_indrect_ctrl_u; + +/* Define the union csr_dma_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_indrect_timeout_u; + +/* Define the union csr_dma_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_indrect_data_u; + +/* Define the union csr_cpi_dma_ram_tmode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_tp_ram_tmode : 8; /* [7:0] */ + u32 glb_cpi_sp_ram_tmode : 7; /* [14:8] */ + u32 rsv_1 : 1; /* [15] */ + u32 glb_cpi_mem_power_mode : 6; /* [21:16] */ + u32 rsv_2 : 9; /* [30:22] */ + u32 glb_cpi_ecc_bypass : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_dma_ram_tmode_u; + +/* Define the union csr_msi_bar_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pba_offset : 15; /* [14:0] */ + u32 rsv_3 : 1; /* [15] */ + u32 glb_cpl_data_rsv : 1; /* [16] */ + u32 rsv_4 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_bar_offset_u; + +/* Define the union csr_pf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_func_idx_l : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 pf_func_idx_h : 5; /* [20:16] */ + u32 rsv_6 : 10; /* [30:21] */ + u32 pf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_range_port_u; + +/* Define the union csr_vf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_func_idx_l : 12; /* [11:0] */ + u32 rsv_7 : 4; /* [15:12] */ + u32 vf_func_idx_h : 12; /* [27:16] */ + u32 rsv_8 : 3; /* [30:28] */ + u32 vf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_range_port_u; + +/* Define the union csr_lvf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lvf_func_idx_l : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 lvf_func_idx_h : 12; /* [27:16] */ + u32 rsv_10 : 3; /* [30:28] */ + u32 lvf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lvf_range_port_u; + +/* Define the union csr_ceq_num_acc_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_num_acc_weight : 12; /* [11:0] */ + u32 rsv_11 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_num_acc_weight_u; + +/* Define the union csr_copy_ep_2_cos_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 copy_ep2cos_4_spu_en : 1; /* [0] */ + u32 modify_src_4_spu_en : 1; /* [1] */ + u32 rsv_12 : 2; /* [3:2] */ + u32 modify_src_idx : 3; /* [6:4] */ + u32 rsv_13 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_copy_ep_2_cos_en_u; + +/* Define the union csr_dma_attr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dma_attr_per_func : 3; /* [2:0] */ + u32 rsv_14 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_attr_num_u; + +/* Define the union csr_dma_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_mode_en : 1; /* [0] */ + u32 pcie_cpi_tag_modify_chk_en : 1; /* [1] */ + u32 rdr_buf_cfg_chk_en : 1; /* [2] */ + u32 cfg_bme_clr_no_flush : 1; /* [3] */ + u32 cfg_osch_drp_no_flush : 1; /* [4] */ + u32 cfg_bme_int_mode : 1; /* [5] */ + u32 rsv_15 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_0_u; + +/* Define the union csr_dma_ram_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_csr_ceq_ram_ini : 1; /* [0] */ + u32 ceq_num_init_start : 1; /* [1] */ + u32 dma_attr_ram_ini_req : 1; /* [2] */ + u32 func_idx_remap_ram_ini_req : 1; /* [3] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ram_init_u; + +/* Define the union csr_dma_ram_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt_tab_ram_ini_sts : 1; /* [0] */ + u32 ceq_attr_csr_ram_ini_sts : 1; /* [1] */ + u32 ceq_num_init_done : 1; /* [2] */ + u32 dma_attr_ram_ini_sts : 1; /* [3] */ + u32 func_idx_remap_ram_ini_sts : 1; /* [4] */ + u32 rsv_17 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ram_status_u; + +/* Define the union csr_pcie_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_time_out_treshold : 10; /* [9:0] */ + u32 rsv_18 : 6; /* [15:10] */ + u32 oubd_tag_time_out_unit_16us : 8; /* [23:16] */ + u32 rsv_19 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_timeout_u; + +/* Define the union csr_pcie_tag_force_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_force_clr_func : 12; /* [11:0] */ + u32 rsv_20 : 4; /* [15:12] */ + u32 mpu_force_clr : 1; /* [16] */ + u32 rsv_21 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_tag_force_u; + +/* Define the union csr_pcie_tag_force_itf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_port_force_clr_idx : 3; /* [2:0] */ + u32 rsv_22 : 13; /* [15:3] */ + u32 mpu_port_force_clr : 1; /* [16] */ + u32 rsv_23 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_tag_force_itf_u; + +/* Define the union csr_timeout_dly_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timeout_itf_dly_th : 16; /* [15:0] */ + u32 timeout_itf_unit : 8; /* [23:16] */ + u32 rsv_24 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timeout_dly_cfg_u; + +/* Define the union csr_pcie_cfg_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mrrs_used_mode : 1; /* [0] */ + u32 rsv_25 : 3; /* [3:1] */ + u32 timeout_set_used_mode : 1; /* [4] */ + u32 rsv_26 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cfg_mod_u; + +/* Define the union csr_pcie_cfg_loc_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_local_mrrs : 12; /* [11:0] */ + u32 cfg_local_timeout_val : 16; /* [27:12] */ + u32 cfg_local_timeout_dis : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cfg_loc_set_u; + +/* Define the union csr_spu_cfg_loc_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_spu_local_mrrs : 3; /* [2:0] */ + u32 rsv_27 : 9; /* [11:3] */ + u32 cfg_spu_local_timeout_val : 4; /* [15:12] */ + u32 rsv_28 : 12; /* [27:16] */ + u32 cfg_spu_local_timeout_dis : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spu_cfg_loc_set_u; + +/* Define the union csr_dma_top_eco0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_uncrt_err : 1; /* [0] */ + u32 pqm_uncrt_err : 1; /* [1] */ + u32 mqm_uncrt_err : 1; /* [2] */ + u32 stlqu_uncrt_err : 1; /* [3] */ + u32 smf0_uncrt_err : 1; /* [4] */ + u32 smf1_uncrt_err : 1; /* [5] */ + u32 smf2_uncrt_err : 1; /* [6] */ + u32 smf3_uncrt_err : 1; /* [7] */ + u32 sml0_uncrt_err : 1; /* [8] */ + u32 sml1_uncrt_err : 1; /* [9] */ + u32 sml2_uncrt_err : 1; /* [10] */ + u32 sml3_uncrt_err : 1; /* [11] */ + u32 stftile0_uncrt_err : 1; /* [12] */ + u32 stftile1_uncrt_err : 1; /* [13] */ + u32 stftile2_uncrt_err : 1; /* [14] */ + u32 stftile3_uncrt_err : 1; /* [15] */ + u32 stltile0_uncrt_err : 1; /* [16] */ + u32 stltile1_uncrt_err : 1; /* [17] */ + u32 stltile2_uncrt_err : 1; /* [18] */ + u32 stltile3_uncrt_err : 1; /* [19] */ + u32 mpu_uncrt_err : 1; /* [20] */ + u32 cpi_uncrt_err : 1; /* [21] */ + u32 lcam_uncrt_err : 1; /* [22] */ + u32 ipsutx_uncrt_err : 1; /* [23] */ + u32 perx_uncrt_err : 1; /* [24] */ + u32 ipsurx_uncrt_err : 1; /* [25] */ + u32 petx_uncrt_err : 1; /* [26] */ + u32 cpb_uncrt_err : 1; /* [27] */ + u32 ckd_err_int0 : 1; /* [28] */ + u32 ckd_err_int1 : 1; /* [29] */ + u32 pcie_uncrt_err : 1; /* [30] */ + u32 cryptorx_uncrt_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco0_u; + +/* Define the union csr_dma_top_eco1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_uncrt_err : 1; /* [0] */ + u32 ts_uncrt_err : 1; /* [1] */ + u32 mag_uncrt_err : 1; /* [2] */ + u32 fc_uncrt_err : 1; /* [3] */ + u32 hva_uncrt_err : 1; /* [4] */ + u32 rsvd : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco1_u; + +/* Define the union csr_dma_top_eco2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_top_eco2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco2_u; + +/* Define the union csr_dma_top_eco3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_top_eco3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco3_u; + +/* Define the union csr_dma_top_eco4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_top_eco4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco4_u; + +/* Define the union csr_cpl_timeout_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_0set : 10; /* [9:0] */ + u32 rsv_30 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_0set : 8; /* [23:16] */ + u32 rsv_31 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value0_u; + +/* Define the union csr_cpl_timeout_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_1set : 10; /* [9:0] */ + u32 rsv_32 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_1set : 8; /* [23:16] */ + u32 rsv_33 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value1_u; + +/* Define the union csr_cpl_timeout_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_2set : 10; /* [9:0] */ + u32 rsv_34 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_2set : 8; /* [23:16] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value2_u; + +/* Define the union csr_cpl_timeout_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_5set : 10; /* [9:0] */ + u32 rsv_36 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_5set : 8; /* [23:16] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value5_u; + +/* Define the union csr_cpl_timeout_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_6set : 10; /* [9:0] */ + u32 rsv_38 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_6set : 8; /* [23:16] */ + u32 rsv_39 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value6_u; + +/* Define the union csr_cpl_timeout_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_9set : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_9set : 8; /* [23:16] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value9_u; + +/* Define the union csr_cpl_timeout_valuea_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_aset : 10; /* [9:0] */ + u32 rsv_42 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_aset : 8; /* [23:16] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_valuea_u; + +/* Define the union csr_cpl_timeout_value_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_dis_set : 10; /* [9:0] */ + u32 rsv_44 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_dis_set : 8; /* [23:16] */ + u32 rsv_45 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value_dis_u; + +/* Define the union csr_pdi_tag_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_pcie_ur_cpl_req_cnt : 16; /* [15:0] */ + u32 dbg_pending_tag_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt0_u; + +/* Define the union csr_pdi_tag_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_timeout_req_cnt : 16; /* [15:0] */ + u32 dbg_osch_quick_back_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt1_u; + +/* Define the union csr_pdi_tag_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_aer_uc_cnt : 16; /* [15:0] */ + u32 dbg_mpu_force_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt2_u; + +/* Define the union csr_pdi_tag_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_pcie_ictl_sop_cnt : 16; /* [15:0] */ + u32 dbg_10bit_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt3_u; + +/* Define the union csr_pdi_tag_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_icpl_ep_cnt : 16; /* [15:0] */ + u32 dbg_pcie_ictl_eop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt4_u; + +/* Define the union csr_pdi_tag_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_icpl_unsucc_cnt : 16; /* [15:0] */ + u32 dbg_icpl_null_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt5_u; + +/* Define the union csr_pdi_tag_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_46 : 16; /* [15:0] */ + u32 dbg_osch_spu_quick_back_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt6_u; + +/* Define the union csr_pdi_tag_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_timeout3_req_cnt : 16; /* [15:0] */ + u32 dbg_timeout4_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt7_u; + +/* Define the union csr_pdi_tag_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_timeout1_req_cnt : 16; /* [15:0] */ + u32 dbg_timeout2_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt8_u; + +/* Define the union csr_pdi_tag_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_47 : 16; /* [15:0] */ + u32 dbg_mpu_port_force_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt9_u; + +/* Define the union csr_pdi_tag_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_cpld_spu_pkt_cnt : 16; /* [15:0] */ + u32 cpi_cpld_x86_pkt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt10_u; + +/* Define the union csr_ceq_blk_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_ceq_tx_int_req_cnt : 16; /* [15:0] */ + u32 dbg_ceq_ci_sw_wr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_blk_cnt_u; + +/* Define the union csr_ceq_csr_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_ceq_state : 12; /* [11:0] */ + u32 rsv_48 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_csr_st_u; + +/* Define the union csr_flr_rcv_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_rcv_pcie1_flr_cnt : 16; /* [15:0] */ + u32 cpi_rcv_pcie0_flr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_rcv_cnt0_u; + +/* Define the union csr_flr_rcv_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_rcv_pcie3_flr_cnt : 16; /* [15:0] */ + u32 cpi_rcv_pcie2_flr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_rcv_cnt1_u; + +/* Define the union csr_flr_rcv_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_49 : 16; /* [15:0] */ + u32 cpi_rcv_pcie4_flr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_rcv_cnt2_u; + +/* Define the union csr_dma_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus4 : 6; /* [5:0] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus0_u; + +/* Define the union csr_dma_ctrl_bus1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus1_u; + +/* Define the union csr_dma_ctrl_bus2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus2_u; + +/* Define the union csr_dma_ctrl_bus3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus3_u; + +/* Define the union csr_dma_ctrl_bus4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus4_u; + +/* Define the union csr_dma_pcie_inbd_itf_wind_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_51 : 4; /* [3:0] */ + u32 itf_wind_16t : 16; /* [19:4] */ + u32 rsv_52 : 10; /* [29:20] */ + u32 itf_wind_mode : 1; /* [30] */ + u32 itf_wind_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pcie_inbd_itf_wind_ctl_u; + +/* Define the union csr_dma_pcie_inbd_itf_wind_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 itf_wind_detect_mode_cnt : 20; /* [19:0] */ + u32 rsv_53 : 11; /* [30:20] */ + u32 itf_wind_detect_done : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pcie_inbd_itf_wind_cnt_u; + +/* Define the union csr_dma_pcie_inbd_itf_wind_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 itf_wind_detect_tlp_cnt : 20; /* [19:0] */ + u32 rsv_54 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pcie_inbd_itf_wind_tlp_cnt_u; + +/* Define the union csr_cpi_rcv_bme_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_rcv_bme_clear_func_idx : 12; /* [11:0] */ + u32 cpi_rcv_bme_clear_lat_en : 1; /* [12] */ + u32 rsv_55 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_rcv_bme_sts_u; + +/* Define the union csr_cpi_tag_timeout_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_sel : 7; /* [6:0] */ + u32 rsv_56 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_sel_u; + +/* Define the union csr_cpi_tag_timeout_clear_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_clr_pulse : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_clear_u; + +/* Define the union csr_cpi_tag_timeout_st_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_func_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_st_out_u; + +/* Define the union csr_cpi_tag_timeout_group_st_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_func_group_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_group_st_out_u; + +/* Define the union csr_cpi_pdi_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_a_fatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_a_fatal_msk_u; + +/* Define the union csr_cpi_pdi_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_a_nonfatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_a_nonfatal_msk_u; + +/* Define the union csr_cpi_pdi_a_int_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_a_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_a_int_pls_u; + +/* Define the union csr_cpi_pdi_b_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_b_fatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_b_fatal_msk_u; + +/* Define the union csr_cpi_pdi_b_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_b_nonfatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_b_nonfatal_msk_u; + +/* Define the union csr_cpi_pdi_b_int_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_b_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_b_int_pls_u; + +/* Define the union csr_cpi_virtio_cap_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_en_u; + +/* Define the union csr_cpi_virtio_cap_00value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_00value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_00value_pf_u; + +/* Define the union csr_cpi_virtio_cap_01value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_01value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_01value_pf_u; + +/* Define the union csr_cpi_virtio_cap_02value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_02value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_02value_pf_u; + +/* Define the union csr_cpi_virtio_cap_03value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_03value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_03value_pf_u; + +/* Define the union csr_cpi_virtio_cap_04value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_04value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_04value_pf_u; + +/* Define the union csr_cpi_virtio_cap_05value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_05value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_05value_pf_u; + +/* Define the union csr_cpi_virtio_cap_06value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_06value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_06value_pf_u; + +/* Define the union csr_cpi_virtio_cap_07value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_07value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_07value_pf_u; + +/* Define the union csr_cpi_virtio_cap_08value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_08value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_08value_pf_u; + +/* Define the union csr_cpi_virtio_cap_09value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_09value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_09value_pf_u; + +/* Define the union csr_cpi_virtio_cap_10value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_10value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_10value_pf_u; + +/* Define the union csr_cpi_virtio_cap_11value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_11value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_11value_pf_u; + +/* Define the union csr_cpi_virtio_cap_12value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_12value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_12value_pf_u; + +/* Define the union csr_cpi_virtio_cap_13value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_13value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_13value_pf_u; + +/* Define the union csr_cpi_virtio_cap_14value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_14value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_14value_pf_u; + +/* Define the union csr_cpi_virtio_cap_15value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_15value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_15value_pf_u; + +/* Define the union csr_cpi_virtio_cap_16value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_16value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_16value_pf_u; + +/* Define the union csr_cpi_virtio_cap_00value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_00value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_00value_vf_u; + +/* Define the union csr_cpi_virtio_cap_01value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_01value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_01value_vf_u; + +/* Define the union csr_cpi_virtio_cap_02value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_02value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_02value_vf_u; + +/* Define the union csr_cpi_virtio_cap_03value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_03value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_03value_vf_u; + +/* Define the union csr_cpi_virtio_cap_04value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_04value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_04value_vf_u; + +/* Define the union csr_cpi_virtio_cap_05value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_05value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_05value_vf_u; + +/* Define the union csr_cpi_virtio_cap_06value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_06value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_06value_vf_u; + +/* Define the union csr_cpi_virtio_cap_07value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_07value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_07value_vf_u; + +/* Define the union csr_cpi_virtio_cap_08value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_08value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_08value_vf_u; + +/* Define the union csr_cpi_virtio_cap_09value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_09value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_09value_vf_u; + +/* Define the union csr_cpi_virtio_cap_10value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_10value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_10value_vf_u; + +/* Define the union csr_cpi_virtio_cap_11value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_11value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_11value_vf_u; + +/* Define the union csr_cpi_virtio_cap_12value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_12value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_12value_vf_u; + +/* Define the union csr_cpi_virtio_cap_13value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_13value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_13value_vf_u; + +/* Define the union csr_cpi_virtio_cap_14value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_14value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_14value_vf_u; + +/* Define the union csr_cpi_virtio_cap_15value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_15value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_15value_vf_u; + +/* Define the union csr_cpi_virtio_cap_16value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_16value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_16value_vf_u; + +/* Define the union csr_dfx_dmatop_ram_ecc_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_cerr : 11; /* [10:0] */ + u32 rsv_57 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dmatop_ram_ecc_cerr_u; + +/* Define the union csr_dfx_dmatop_ram_ecc_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_ucerr : 11; /* [10:0] */ + u32 rsv_58 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dmatop_ram_ecc_ucerr_u; + +/* Define the union csr_dfx_dmatop_ram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_err_addr : 24; /* [23:0] */ + u32 rsv_59 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dmatop_ram_err_addr_u; + +/* Define the union csr_dmatop_ecc_inj_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_inj_req : 22; /* [21:0] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_ecc_inj_req_u; + +/* Define the union csr_dmatop_dbg_fifo_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_a_u; + +/* Define the union csr_dmatop_dbg_fifo_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_b_u; + +/* Define the union csr_dmatop_dbg_fifo_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_c_u; + +/* Define the union csr_dmatop_dbg_fifo_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_d_u; + +/* Define the union csr_dmatop_dbg_fifo_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_e_u; + +/* Define the union csr_dmatop_dbg_fifo_st_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_f_u; + +/* Define the union csr_dmatop_dbg_fifo_st_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_g_u; + +/* Define the union csr_dmatop_dbg_fifo_st_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_h_u; + +/* Define the union csr_dmatop_dbg_fifo_st_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_i_u; + +/* Define the union csr_dmatop_dbg_fifo_st_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_j_u; + +/* Define the union csr_dmatop_dbg_fifo_st_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_k_u; + +/* Define the union csr_dmatop_dbg_fifo_st_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_l_u; + +/* Define the union csr_dmatop_dbg_fifo_st_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_m_u; + +/* Define the union csr_dmatop_dbg_fifo_st_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_n_u; + +/* Define the union csr_dmatop_dbg_fifo_st_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_o_u; + +/* Define the union csr_dmatop_dbg_fifo_st_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_p_u; + +/* Define the union csr_dmatop_dbg_fifo_st_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_q_u; + +/* Define the union csr_dmatop_dbg_fifo_st_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_r_u; + +/* Define the union csr_dmatop_dbg_fifo_st_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_s_u; + +/* Define the union csr_dmatop_dbg_fifo_st_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_t_u; + +/* Define the union csr_dmatop_dbg_fifo_st_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_u_u; + +/* Define the union csr_dmatop_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_out_a_u; + +/* Define the union csr_dmatop_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_out_b_u; + +/* Define the union csr_dmatop_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_out_c_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_dma_indrect_ctrl_u dma_indrect_ctrl; /* 0 */ + volatile csr_dma_indrect_timeout_u dma_indrect_timeout; /* 4 */ + volatile csr_dma_indrect_data_u dma_indrect_data[8]; /* 8 */ + volatile csr_cpi_dma_ram_tmode_u cpi_dma_ram_tmode; /* 40 */ + volatile csr_msi_bar_offset_u msi_bar_offset; /* 44 */ + volatile csr_pf_range_port_u pf_range_port[5]; /* 50 */ + volatile csr_vf_range_port_u vf_range_port[5]; /* 54 */ + volatile csr_lvf_range_port_u lvf_range_port[5]; /* 58 */ + volatile csr_ceq_num_acc_weight_u ceq_num_acc_weight; /* B0 */ + volatile csr_copy_ep_2_cos_en_u copy_ep_2_cos_en; /* B4 */ + volatile csr_dma_attr_num_u dma_attr_num; /* B8 */ + volatile csr_dma_ctrl_0_u dma_ctrl_0; /* BC */ + volatile csr_dma_ram_init_u dma_ram_init; /* C0 */ + volatile csr_dma_ram_status_u dma_ram_status; /* C4 */ + volatile csr_pcie_timeout_u pcie_timeout; /* D0 */ + volatile csr_pcie_tag_force_u pcie_tag_force; /* D4 */ + volatile csr_pcie_tag_force_itf_u pcie_tag_force_itf; /* D8 */ + volatile csr_timeout_dly_cfg_u timeout_dly_cfg; /* DC */ + volatile csr_pcie_cfg_mod_u pcie_cfg_mod; /* E0 */ + volatile csr_pcie_cfg_loc_set_u pcie_cfg_loc_set; /* E4 */ + volatile csr_spu_cfg_loc_set_u spu_cfg_loc_set; /* E8 */ + volatile csr_dma_top_eco0_u dma_top_eco0; /* EC */ + volatile csr_dma_top_eco1_u dma_top_eco1; /* F0 */ + volatile csr_dma_top_eco2_u dma_top_eco2; /* F4 */ + volatile csr_dma_top_eco3_u dma_top_eco3; /* F8 */ + volatile csr_dma_top_eco4_u dma_top_eco4; /* FC */ + volatile csr_cpl_timeout_value0_u cpl_timeout_value0[5]; /* 100 */ + volatile csr_cpl_timeout_value1_u cpl_timeout_value1[5]; /* 104 */ + volatile csr_cpl_timeout_value2_u cpl_timeout_value2[5]; /* 108 */ + volatile csr_cpl_timeout_value5_u cpl_timeout_value5[5]; /* 10C */ + volatile csr_cpl_timeout_value6_u cpl_timeout_value6[5]; /* 110 */ + volatile csr_cpl_timeout_value9_u cpl_timeout_value9[5]; /* 114 */ + volatile csr_cpl_timeout_valuea_u cpl_timeout_valuea[5]; /* 118 */ + volatile csr_cpl_timeout_value_dis_u cpl_timeout_value_dis[5]; /* 11C */ + volatile csr_pdi_tag_cnt0_u pdi_tag_cnt0; /* 240 */ + volatile csr_pdi_tag_cnt1_u pdi_tag_cnt1; /* 244 */ + volatile csr_pdi_tag_cnt2_u pdi_tag_cnt2; /* 248 */ + volatile csr_pdi_tag_cnt3_u pdi_tag_cnt3; /* 24C */ + volatile csr_pdi_tag_cnt4_u pdi_tag_cnt4; /* 250 */ + volatile csr_pdi_tag_cnt5_u pdi_tag_cnt5; /* 254 */ + volatile csr_pdi_tag_cnt6_u pdi_tag_cnt6; /* 258 */ + volatile csr_pdi_tag_cnt7_u pdi_tag_cnt7; /* 25C */ + volatile csr_pdi_tag_cnt8_u pdi_tag_cnt8; /* 260 */ + volatile csr_pdi_tag_cnt9_u pdi_tag_cnt9; /* 264 */ + volatile csr_pdi_tag_cnt10_u pdi_tag_cnt10; /* 268 */ + volatile csr_ceq_blk_cnt_u ceq_blk_cnt; /* 2A0 */ + volatile csr_ceq_csr_st_u ceq_csr_st; /* 2A4 */ + volatile csr_flr_rcv_cnt0_u flr_rcv_cnt0; /* 2B0 */ + volatile csr_flr_rcv_cnt1_u flr_rcv_cnt1; /* 2B4 */ + volatile csr_flr_rcv_cnt2_u flr_rcv_cnt2; /* 2B8 */ + volatile csr_dma_ctrl_bus0_u dma_ctrl_bus0; /* 2E0 */ + volatile csr_dma_ctrl_bus1_u dma_ctrl_bus1; /* 2E4 */ + volatile csr_dma_ctrl_bus2_u dma_ctrl_bus2; /* 2E8 */ + volatile csr_dma_ctrl_bus3_u dma_ctrl_bus3; /* 2EC */ + volatile csr_dma_ctrl_bus4_u dma_ctrl_bus4; /* 2F0 */ + volatile csr_dma_pcie_inbd_itf_wind_ctl_u dma_pcie_inbd_itf_wind_ctl; /* 300 */ + volatile csr_dma_pcie_inbd_itf_wind_cnt_u dma_pcie_inbd_itf_wind_cnt; /* 304 */ + volatile csr_dma_pcie_inbd_itf_wind_tlp_cnt_u dma_pcie_inbd_itf_wind_tlp_cnt; /* 308 */ + volatile csr_cpi_rcv_bme_sts_u cpi_rcv_bme_sts[16]; /* 340 */ + volatile csr_cpi_tag_timeout_sel_u cpi_tag_timeout_sel; /* 380 */ + volatile csr_cpi_tag_timeout_clear_u cpi_tag_timeout_clear; /* 384 */ + volatile csr_cpi_tag_timeout_st_out_u cpi_tag_timeout_st_out; /* 388 */ + volatile csr_cpi_tag_timeout_group_st_out_u cpi_tag_timeout_group_st_out; /* 38C */ + volatile csr_cpi_pdi_a_fatal_msk_u cpi_pdi_a_fatal_msk; /* 3E0 */ + volatile csr_cpi_pdi_a_nonfatal_msk_u cpi_pdi_a_nonfatal_msk; /* 3E4 */ + volatile csr_cpi_pdi_a_int_pls_u cpi_pdi_a_int_pls; /* 3E8 */ + volatile csr_cpi_pdi_b_fatal_msk_u cpi_pdi_b_fatal_msk; /* 3F0 */ + volatile csr_cpi_pdi_b_nonfatal_msk_u cpi_pdi_b_nonfatal_msk; /* 3F4 */ + volatile csr_cpi_pdi_b_int_pls_u cpi_pdi_b_int_pls; /* 3F8 */ + volatile csr_cpi_virtio_cap_en_u cpi_virtio_cap_en[2]; /* 400 */ + volatile csr_cpi_virtio_cap_00value_pf_u cpi_virtio_cap_00value_pf; /* 600 */ + volatile csr_cpi_virtio_cap_01value_pf_u cpi_virtio_cap_01value_pf; /* 604 */ + volatile csr_cpi_virtio_cap_02value_pf_u cpi_virtio_cap_02value_pf; /* 608 */ + volatile csr_cpi_virtio_cap_03value_pf_u cpi_virtio_cap_03value_pf; /* 60C */ + volatile csr_cpi_virtio_cap_04value_pf_u cpi_virtio_cap_04value_pf; /* 610 */ + volatile csr_cpi_virtio_cap_05value_pf_u cpi_virtio_cap_05value_pf; /* 614 */ + volatile csr_cpi_virtio_cap_06value_pf_u cpi_virtio_cap_06value_pf; /* 618 */ + volatile csr_cpi_virtio_cap_07value_pf_u cpi_virtio_cap_07value_pf; /* 61C */ + volatile csr_cpi_virtio_cap_08value_pf_u cpi_virtio_cap_08value_pf; /* 620 */ + volatile csr_cpi_virtio_cap_09value_pf_u cpi_virtio_cap_09value_pf; /* 630 */ + volatile csr_cpi_virtio_cap_10value_pf_u cpi_virtio_cap_10value_pf; /* 634 */ + volatile csr_cpi_virtio_cap_11value_pf_u cpi_virtio_cap_11value_pf; /* 638 */ + volatile csr_cpi_virtio_cap_12value_pf_u cpi_virtio_cap_12value_pf; /* 63C */ + volatile csr_cpi_virtio_cap_13value_pf_u cpi_virtio_cap_13value_pf; /* 640 */ + volatile csr_cpi_virtio_cap_14value_pf_u cpi_virtio_cap_14value_pf; /* 644 */ + volatile csr_cpi_virtio_cap_15value_pf_u cpi_virtio_cap_15value_pf; /* 648 */ + volatile csr_cpi_virtio_cap_16value_pf_u cpi_virtio_cap_16value_pf; /* 64C */ + volatile csr_cpi_virtio_cap_00value_vf_u cpi_virtio_cap_00value_vf; /* 680 */ + volatile csr_cpi_virtio_cap_01value_vf_u cpi_virtio_cap_01value_vf; /* 684 */ + volatile csr_cpi_virtio_cap_02value_vf_u cpi_virtio_cap_02value_vf; /* 688 */ + volatile csr_cpi_virtio_cap_03value_vf_u cpi_virtio_cap_03value_vf; /* 68C */ + volatile csr_cpi_virtio_cap_04value_vf_u cpi_virtio_cap_04value_vf; /* 690 */ + volatile csr_cpi_virtio_cap_05value_vf_u cpi_virtio_cap_05value_vf; /* 694 */ + volatile csr_cpi_virtio_cap_06value_vf_u cpi_virtio_cap_06value_vf; /* 698 */ + volatile csr_cpi_virtio_cap_07value_vf_u cpi_virtio_cap_07value_vf; /* 69C */ + volatile csr_cpi_virtio_cap_08value_vf_u cpi_virtio_cap_08value_vf; /* 6A0 */ + volatile csr_cpi_virtio_cap_09value_vf_u cpi_virtio_cap_09value_vf; /* 6B0 */ + volatile csr_cpi_virtio_cap_10value_vf_u cpi_virtio_cap_10value_vf; /* 6B4 */ + volatile csr_cpi_virtio_cap_11value_vf_u cpi_virtio_cap_11value_vf; /* 6B8 */ + volatile csr_cpi_virtio_cap_12value_vf_u cpi_virtio_cap_12value_vf; /* 6BC */ + volatile csr_cpi_virtio_cap_13value_vf_u cpi_virtio_cap_13value_vf; /* 6C0 */ + volatile csr_cpi_virtio_cap_14value_vf_u cpi_virtio_cap_14value_vf; /* 6C4 */ + volatile csr_cpi_virtio_cap_15value_vf_u cpi_virtio_cap_15value_vf; /* 6C8 */ + volatile csr_cpi_virtio_cap_16value_vf_u cpi_virtio_cap_16value_vf; /* 6CC */ + volatile csr_dfx_dmatop_ram_ecc_cerr_u dfx_dmatop_ram_ecc_cerr; /* 700 */ + volatile csr_dfx_dmatop_ram_ecc_ucerr_u dfx_dmatop_ram_ecc_ucerr; /* 704 */ + volatile csr_dfx_dmatop_ram_err_addr_u dfx_dmatop_ram_err_addr; /* 708 */ + volatile csr_dmatop_ecc_inj_req_u dmatop_ecc_inj_req; /* 710 */ + volatile csr_dmatop_dbg_fifo_st_a_u dmatop_dbg_fifo_st_a; /* 720 */ + volatile csr_dmatop_dbg_fifo_st_b_u dmatop_dbg_fifo_st_b; /* 724 */ + volatile csr_dmatop_dbg_fifo_st_c_u dmatop_dbg_fifo_st_c; /* 728 */ + volatile csr_dmatop_dbg_fifo_st_d_u dmatop_dbg_fifo_st_d; /* 72C */ + volatile csr_dmatop_dbg_fifo_st_e_u dmatop_dbg_fifo_st_e; /* 730 */ + volatile csr_dmatop_dbg_fifo_st_f_u dmatop_dbg_fifo_st_f; /* 734 */ + volatile csr_dmatop_dbg_fifo_st_g_u dmatop_dbg_fifo_st_g; /* 738 */ + volatile csr_dmatop_dbg_fifo_st_h_u dmatop_dbg_fifo_st_h; /* 73C */ + volatile csr_dmatop_dbg_fifo_st_i_u dmatop_dbg_fifo_st_i; /* 740 */ + volatile csr_dmatop_dbg_fifo_st_j_u dmatop_dbg_fifo_st_j; /* 744 */ + volatile csr_dmatop_dbg_fifo_st_k_u dmatop_dbg_fifo_st_k; /* 748 */ + volatile csr_dmatop_dbg_fifo_st_l_u dmatop_dbg_fifo_st_l; /* 74C */ + volatile csr_dmatop_dbg_fifo_st_m_u dmatop_dbg_fifo_st_m; /* 750 */ + volatile csr_dmatop_dbg_fifo_st_n_u dmatop_dbg_fifo_st_n; /* 754 */ + volatile csr_dmatop_dbg_fifo_st_o_u dmatop_dbg_fifo_st_o; /* 758 */ + volatile csr_dmatop_dbg_fifo_st_p_u dmatop_dbg_fifo_st_p; /* 75C */ + volatile csr_dmatop_dbg_fifo_st_q_u dmatop_dbg_fifo_st_q; /* 760 */ + volatile csr_dmatop_dbg_fifo_st_r_u dmatop_dbg_fifo_st_r; /* 764 */ + volatile csr_dmatop_dbg_fifo_st_s_u dmatop_dbg_fifo_st_s; /* 768 */ + volatile csr_dmatop_dbg_fifo_st_t_u dmatop_dbg_fifo_st_t; /* 76C */ + volatile csr_dmatop_dbg_fifo_st_u_u dmatop_dbg_fifo_st_u; /* 770 */ + volatile csr_dmatop_dbg_out_a_u dmatop_dbg_out_a; /* 780 */ + volatile csr_dmatop_dbg_out_b_u dmatop_dbg_out_b; /* 784 */ + volatile csr_dmatop_dbg_out_c_u dmatop_dbg_out_c; /* 788 */ +} S_cpi_dma_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_dma_csr */ +extern volatile S_cpi_dma_csr_REGS_TYPE *gopcpi_dma_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetDMA_INDRECT_CTRL_dma_indrect_addr(unsigned int udma_indrect_addr); +int iSetDMA_INDRECT_CTRL_dma_indrect_tab(unsigned int udma_indrect_tab); +int iSetDMA_INDRECT_CTRL_dma_indrect_status(unsigned int udma_indrect_status); +int iSetDMA_INDRECT_CTRL_dma_indrect_mode(unsigned int udma_indrect_mode); +int iSetDMA_INDRECT_CTRL_dma_indrect_vld(unsigned int udma_indrect_vld); +int iSetDMA_INDRECT_TIMEOUT_dma_indrect_timeout(unsigned int udma_indrect_timeout); +int iSetDMA_INDRECT_DATA_dma_indrect_data(unsigned int udma_indrect_data); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_tp_ram_tmode(unsigned int uglb_cpi_tp_ram_tmode); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_sp_ram_tmode(unsigned int uglb_cpi_sp_ram_tmode); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_mem_power_mode(unsigned int uglb_cpi_mem_power_mode); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_ecc_bypass(unsigned int uglb_cpi_ecc_bypass); +int iSetMSI_BAR_OFFSET_glb_pba_offset(unsigned int uglb_pba_offset); +int iSetMSI_BAR_OFFSET_glb_cpl_data_rsv(unsigned int uglb_cpl_data_rsv); +int iSetPF_RANGE_PORT_pf_func_idx_l(unsigned int upf_func_idx_l); +int iSetPF_RANGE_PORT_pf_func_idx_h(unsigned int upf_func_idx_h); +int iSetPF_RANGE_PORT_pf_func_idx_v(unsigned int upf_func_idx_v); +int iSetVF_RANGE_PORT_vf_func_idx_l(unsigned int uvf_func_idx_l); +int iSetVF_RANGE_PORT_vf_func_idx_h(unsigned int uvf_func_idx_h); +int iSetVF_RANGE_PORT_vf_func_idx_v(unsigned int uvf_func_idx_v); +int iSetLVF_RANGE_PORT_lvf_func_idx_l(unsigned int ulvf_func_idx_l); +int iSetLVF_RANGE_PORT_lvf_func_idx_h(unsigned int ulvf_func_idx_h); +int iSetLVF_RANGE_PORT_lvf_func_idx_v(unsigned int ulvf_func_idx_v); +int iSetCEQ_NUM_ACC_WEIGHT_ceq_num_acc_weight(unsigned int uceq_num_acc_weight); +int iSetCOPY_EP_2_COS_EN_copy_ep2cos_4_spu_en(unsigned int ucopy_ep2cos_4_spu_en); +int iSetCOPY_EP_2_COS_EN_modify_src_4_spu_en(unsigned int umodify_src_4_spu_en); +int iSetCOPY_EP_2_COS_EN_modify_src_idx(unsigned int umodify_src_idx); +int iSetDMA_ATTR_NUM_glb_dma_attr_per_func(unsigned int uglb_dma_attr_per_func); +int iSetDMA_CTRL_0_flxq_mode_en(unsigned int uflxq_mode_en); +int iSetDMA_CTRL_0_pcie_cpi_tag_modify_chk_en(unsigned int upcie_cpi_tag_modify_chk_en); +int iSetDMA_CTRL_0_rdr_buf_cfg_chk_en(unsigned int urdr_buf_cfg_chk_en); +int iSetDMA_CTRL_0_cfg_bme_clr_no_flush(unsigned int ucfg_bme_clr_no_flush); +int iSetDMA_CTRL_0_cfg_osch_drp_no_flush(unsigned int ucfg_osch_drp_no_flush); +int iSetDMA_CTRL_0_cfg_bme_int_mode(unsigned int ucfg_bme_int_mode); +int iSetDMA_RAM_INIT_ipush_csr_ceq_ram_ini(unsigned int uipush_csr_ceq_ram_ini); +int iSetDMA_RAM_INIT_ceq_num_init_start(unsigned int uceq_num_init_start); +int iSetDMA_RAM_INIT_dma_attr_ram_ini_req(unsigned int udma_attr_ram_ini_req); +int iSetDMA_RAM_INIT_func_idx_remap_ram_ini_req(unsigned int ufunc_idx_remap_ram_ini_req); +int iSetDMA_RAM_STATUS_ceq_mtt_tab_ram_ini_sts(unsigned int uceq_mtt_tab_ram_ini_sts); +int iSetDMA_RAM_STATUS_ceq_attr_csr_ram_ini_sts(unsigned int uceq_attr_csr_ram_ini_sts); +int iSetDMA_RAM_STATUS_ceq_num_init_done(unsigned int uceq_num_init_done); +int iSetDMA_RAM_STATUS_dma_attr_ram_ini_sts(unsigned int udma_attr_ram_ini_sts); +int iSetDMA_RAM_STATUS_func_idx_remap_ram_ini_sts(unsigned int ufunc_idx_remap_ram_ini_sts); +int iSetPCIE_TIMEOUT_oubd_tag_time_out_treshold(unsigned int uoubd_tag_time_out_treshold); +int iSetPCIE_TIMEOUT_oubd_tag_time_out_unit_16us(unsigned int uoubd_tag_time_out_unit_16us); +int iSetPCIE_TAG_FORCE_mpu_force_clr_func(unsigned int umpu_force_clr_func); +int iSetPCIE_TAG_FORCE_mpu_force_clr(unsigned int umpu_force_clr); +int iSetPCIE_TAG_FORCE_ITF_mpu_port_force_clr_idx(unsigned int umpu_port_force_clr_idx); +int iSetPCIE_TAG_FORCE_ITF_mpu_port_force_clr(unsigned int umpu_port_force_clr); +int iSetTIMEOUT_DLY_CFG_timeout_itf_dly_th(unsigned int utimeout_itf_dly_th); +int iSetTIMEOUT_DLY_CFG_timeout_itf_unit(unsigned int utimeout_itf_unit); +int iSetPCIE_CFG_MOD_mrrs_used_mode(unsigned int umrrs_used_mode); +int iSetPCIE_CFG_MOD_timeout_set_used_mode(unsigned int utimeout_set_used_mode); +int iSetPCIE_CFG_LOC_SET_cfg_local_mrrs(unsigned int ucfg_local_mrrs); +int iSetPCIE_CFG_LOC_SET_cfg_local_timeout_val(unsigned int ucfg_local_timeout_val); +int iSetPCIE_CFG_LOC_SET_cfg_local_timeout_dis(unsigned int ucfg_local_timeout_dis); +int iSetSPU_CFG_LOC_SET_cfg_spu_local_mrrs(unsigned int ucfg_spu_local_mrrs); +int iSetSPU_CFG_LOC_SET_cfg_spu_local_timeout_val(unsigned int ucfg_spu_local_timeout_val); +int iSetSPU_CFG_LOC_SET_cfg_spu_local_timeout_dis(unsigned int ucfg_spu_local_timeout_dis); +int iSetDMA_TOP_ECO0_dma_top_eco0(unsigned int udma_top_eco0); +int iSetDMA_TOP_ECO1_dma_top_eco1(unsigned int udma_top_eco1); +int iSetDMA_TOP_ECO2_dma_top_eco2(unsigned int udma_top_eco2); +int iSetDMA_TOP_ECO3_dma_top_eco3(unsigned int udma_top_eco3); +int iSetDMA_TOP_ECO4_dma_top_eco4(unsigned int udma_top_eco4); +int iSetCPL_TIMEOUT_VALUE0_oubd_tag_treshold_0set(unsigned int uoubd_tag_treshold_0set); +int iSetCPL_TIMEOUT_VALUE0_oubd_tag_unit_16us_0set(unsigned int uoubd_tag_unit_16us_0set); +int iSetCPL_TIMEOUT_VALUE1_oubd_tag_treshold_1set(unsigned int uoubd_tag_treshold_1set); +int iSetCPL_TIMEOUT_VALUE1_oubd_tag_unit_16us_1set(unsigned int uoubd_tag_unit_16us_1set); +int iSetCPL_TIMEOUT_VALUE2_oubd_tag_treshold_2set(unsigned int uoubd_tag_treshold_2set); +int iSetCPL_TIMEOUT_VALUE2_oubd_tag_unit_16us_2set(unsigned int uoubd_tag_unit_16us_2set); +int iSetCPL_TIMEOUT_VALUE5_oubd_tag_treshold_5set(unsigned int uoubd_tag_treshold_5set); +int iSetCPL_TIMEOUT_VALUE5_oubd_tag_unit_16us_5set(unsigned int uoubd_tag_unit_16us_5set); +int iSetCPL_TIMEOUT_VALUE6_oubd_tag_treshold_6set(unsigned int uoubd_tag_treshold_6set); +int iSetCPL_TIMEOUT_VALUE6_oubd_tag_unit_16us_6set(unsigned int uoubd_tag_unit_16us_6set); +int iSetCPL_TIMEOUT_VALUE9_oubd_tag_treshold_9set(unsigned int uoubd_tag_treshold_9set); +int iSetCPL_TIMEOUT_VALUE9_oubd_tag_unit_16us_9set(unsigned int uoubd_tag_unit_16us_9set); +int iSetCPL_TIMEOUT_VALUEA_oubd_tag_treshold_aset(unsigned int uoubd_tag_treshold_aset); +int iSetCPL_TIMEOUT_VALUEA_oubd_tag_unit_16us_aset(unsigned int uoubd_tag_unit_16us_aset); +int iSetCPL_TIMEOUT_VALUE_DIS_oubd_tag_treshold_dis_set(unsigned int uoubd_tag_treshold_dis_set); +int iSetCPL_TIMEOUT_VALUE_DIS_oubd_tag_unit_16us_dis_set(unsigned int uoubd_tag_unit_16us_dis_set); +int iSetPDI_TAG_CNT0_dbg_pcie_ur_cpl_req_cnt(unsigned int udbg_pcie_ur_cpl_req_cnt); +int iSetPDI_TAG_CNT0_dbg_pending_tag_req_cnt(unsigned int udbg_pending_tag_req_cnt); +int iSetPDI_TAG_CNT1_dbg_timeout_req_cnt(unsigned int udbg_timeout_req_cnt); +int iSetPDI_TAG_CNT1_dbg_osch_quick_back_cnt(unsigned int udbg_osch_quick_back_cnt); +int iSetPDI_TAG_CNT2_dbg_aer_uc_cnt(unsigned int udbg_aer_uc_cnt); +int iSetPDI_TAG_CNT2_dbg_mpu_force_cnt(unsigned int udbg_mpu_force_cnt); +int iSetPDI_TAG_CNT3_dbg_pcie_ictl_sop_cnt(unsigned int udbg_pcie_ictl_sop_cnt); +int iSetPDI_TAG_CNT3_dbg_10bit_err_cnt(unsigned int udbg_10bit_err_cnt); +int iSetPDI_TAG_CNT4_dbg_icpl_ep_cnt(unsigned int udbg_icpl_ep_cnt); +int iSetPDI_TAG_CNT4_dbg_pcie_ictl_eop_cnt(unsigned int udbg_pcie_ictl_eop_cnt); +int iSetPDI_TAG_CNT5_dbg_icpl_unsucc_cnt(unsigned int udbg_icpl_unsucc_cnt); +int iSetPDI_TAG_CNT5_dbg_icpl_null_cnt(unsigned int udbg_icpl_null_cnt); +int iSetPDI_TAG_CNT6_dbg_osch_spu_quick_back_cnt(unsigned int udbg_osch_spu_quick_back_cnt); +int iSetPDI_TAG_CNT7_dbg_timeout3_req_cnt(unsigned int udbg_timeout3_req_cnt); +int iSetPDI_TAG_CNT7_dbg_timeout4_req_cnt(unsigned int udbg_timeout4_req_cnt); +int iSetPDI_TAG_CNT8_dbg_timeout1_req_cnt(unsigned int udbg_timeout1_req_cnt); +int iSetPDI_TAG_CNT8_dbg_timeout2_req_cnt(unsigned int udbg_timeout2_req_cnt); +int iSetPDI_TAG_CNT9_dbg_mpu_port_force_cnt(unsigned int udbg_mpu_port_force_cnt); +int iSetPDI_TAG_CNT10_cpi_cpld_spu_pkt_cnt(unsigned int ucpi_cpld_spu_pkt_cnt); +int iSetPDI_TAG_CNT10_cpi_cpld_x86_pkt_cnt(unsigned int ucpi_cpld_x86_pkt_cnt); +int iSetCEQ_BLK_CNT_dbg_ceq_tx_int_req_cnt(unsigned int udbg_ceq_tx_int_req_cnt); +int iSetCEQ_BLK_CNT_dbg_ceq_ci_sw_wr_cnt(unsigned int udbg_ceq_ci_sw_wr_cnt); +int iSetCEQ_CSR_ST_dbg_ceq_state(unsigned int udbg_ceq_state); +int iSetFLR_RCV_CNT0_cpi_rcv_pcie1_flr_cnt(unsigned int ucpi_rcv_pcie1_flr_cnt); +int iSetFLR_RCV_CNT0_cpi_rcv_pcie0_flr_cnt(unsigned int ucpi_rcv_pcie0_flr_cnt); +int iSetFLR_RCV_CNT1_cpi_rcv_pcie3_flr_cnt(unsigned int ucpi_rcv_pcie3_flr_cnt); +int iSetFLR_RCV_CNT1_cpi_rcv_pcie2_flr_cnt(unsigned int ucpi_rcv_pcie2_flr_cnt); +int iSetFLR_RCV_CNT2_cpi_rcv_pcie4_flr_cnt(unsigned int ucpi_rcv_pcie4_flr_cnt); +int iSetDMA_CTRL_BUS0_dma_ctrl_bus4(unsigned int udma_ctrl_bus4); +int iSetDMA_CTRL_BUS1_dma_ctrl_bus3(unsigned int udma_ctrl_bus3); +int iSetDMA_CTRL_BUS2_dma_ctrl_bus2(unsigned int udma_ctrl_bus2); +int iSetDMA_CTRL_BUS3_dma_ctrl_bus1(unsigned int udma_ctrl_bus1); +int iSetDMA_CTRL_BUS4_dma_ctrl_bus0(unsigned int udma_ctrl_bus0); +int iSetDMA_PCIE_INBD_ITF_WIND_CTL_itf_wind_16t(unsigned int uitf_wind_16t); +int iSetDMA_PCIE_INBD_ITF_WIND_CTL_itf_wind_mode(unsigned int uitf_wind_mode); +int iSetDMA_PCIE_INBD_ITF_WIND_CTL_itf_wind_start(unsigned int uitf_wind_start); +int iSetDMA_PCIE_INBD_ITF_WIND_CNT_itf_wind_detect_mode_cnt(unsigned int uitf_wind_detect_mode_cnt); +int iSetDMA_PCIE_INBD_ITF_WIND_CNT_itf_wind_detect_done(unsigned int uitf_wind_detect_done); +int iSetDMA_PCIE_INBD_ITF_WIND_TLP_CNT_itf_wind_detect_tlp_cnt(unsigned int uitf_wind_detect_tlp_cnt); +int iSetCPI_RCV_BME_STS_cpi_rcv_bme_clear_func_idx(unsigned int ucpi_rcv_bme_clear_func_idx); +int iSetCPI_RCV_BME_STS_cpi_rcv_bme_clear_lat_en(unsigned int ucpi_rcv_bme_clear_lat_en); +int iSetCPI_TAG_TIMEOUT_SEL_cpi_tag_timeout_sel(unsigned int ucpi_tag_timeout_sel); +int iSetCPI_TAG_TIMEOUT_CLEAR_cpi_tag_timeout_clr_pulse(unsigned int ucpi_tag_timeout_clr_pulse); +int iSetCPI_TAG_TIMEOUT_ST_OUT_cpi_tag_timeout_func_ro(unsigned int ucpi_tag_timeout_func_ro); +int iSetCPI_TAG_TIMEOUT_GROUP_ST_OUT_cpi_tag_timeout_func_group_ro(unsigned int ucpi_tag_timeout_func_group_ro); +int iSetCPI_PDI_A_FATAL_MSK_pdi_dfx_a_fatal_mask(unsigned int updi_dfx_a_fatal_mask); +int iSetCPI_PDI_A_NONFATAL_MSK_pdi_dfx_a_nonfatal_mask(unsigned int updi_dfx_a_nonfatal_mask); +int iSetCPI_PDI_A_INT_PLS_pdi_dfx_a_pls(unsigned int updi_dfx_a_pls); +int iSetCPI_PDI_B_FATAL_MSK_pdi_dfx_b_fatal_mask(unsigned int updi_dfx_b_fatal_mask); +int iSetCPI_PDI_B_NONFATAL_MSK_pdi_dfx_b_nonfatal_mask(unsigned int updi_dfx_b_nonfatal_mask); +int iSetCPI_PDI_B_INT_PLS_pdi_dfx_b_pls(unsigned int updi_dfx_b_pls); +int iSetCPI_VIRTIO_CAP_EN_virtio_cap_en(unsigned int uvirtio_cap_en); +int iSetCPI_VIRTIO_CAP_00VALUE_PF_virtio_cap_00value_pf(unsigned int uvirtio_cap_00value_pf); +int iSetCPI_VIRTIO_CAP_01VALUE_PF_virtio_cap_01value_pf(unsigned int uvirtio_cap_01value_pf); +int iSetCPI_VIRTIO_CAP_02VALUE_PF_virtio_cap_02value_pf(unsigned int uvirtio_cap_02value_pf); +int iSetCPI_VIRTIO_CAP_03VALUE_PF_virtio_cap_03value_pf(unsigned int uvirtio_cap_03value_pf); +int iSetCPI_VIRTIO_CAP_04VALUE_PF_virtio_cap_04value_pf(unsigned int uvirtio_cap_04value_pf); +int iSetCPI_VIRTIO_CAP_05VALUE_PF_virtio_cap_05value_pf(unsigned int uvirtio_cap_05value_pf); +int iSetCPI_VIRTIO_CAP_06VALUE_PF_virtio_cap_06value_pf(unsigned int uvirtio_cap_06value_pf); +int iSetCPI_VIRTIO_CAP_07VALUE_PF_virtio_cap_07value_pf(unsigned int uvirtio_cap_07value_pf); +int iSetCPI_VIRTIO_CAP_08VALUE_PF_virtio_cap_08value_pf(unsigned int uvirtio_cap_08value_pf); +int iSetCPI_VIRTIO_CAP_09VALUE_PF_virtio_cap_09value_pf(unsigned int uvirtio_cap_09value_pf); +int iSetCPI_VIRTIO_CAP_10VALUE_PF_virtio_cap_10value_pf(unsigned int uvirtio_cap_10value_pf); +int iSetCPI_VIRTIO_CAP_11VALUE_PF_virtio_cap_11value_pf(unsigned int uvirtio_cap_11value_pf); +int iSetCPI_VIRTIO_CAP_12VALUE_PF_virtio_cap_12value_pf(unsigned int uvirtio_cap_12value_pf); +int iSetCPI_VIRTIO_CAP_13VALUE_PF_virtio_cap_13value_pf(unsigned int uvirtio_cap_13value_pf); +int iSetCPI_VIRTIO_CAP_14VALUE_PF_virtio_cap_14value_pf(unsigned int uvirtio_cap_14value_pf); +int iSetCPI_VIRTIO_CAP_15VALUE_PF_virtio_cap_15value_pf(unsigned int uvirtio_cap_15value_pf); +int iSetCPI_VIRTIO_CAP_16VALUE_PF_virtio_cap_16value_pf(unsigned int uvirtio_cap_16value_pf); +int iSetCPI_VIRTIO_CAP_00VALUE_VF_virtio_cap_00value_vf(unsigned int uvirtio_cap_00value_vf); +int iSetCPI_VIRTIO_CAP_01VALUE_VF_virtio_cap_01value_vf(unsigned int uvirtio_cap_01value_vf); +int iSetCPI_VIRTIO_CAP_02VALUE_VF_virtio_cap_02value_vf(unsigned int uvirtio_cap_02value_vf); +int iSetCPI_VIRTIO_CAP_03VALUE_VF_virtio_cap_03value_vf(unsigned int uvirtio_cap_03value_vf); +int iSetCPI_VIRTIO_CAP_04VALUE_VF_virtio_cap_04value_vf(unsigned int uvirtio_cap_04value_vf); +int iSetCPI_VIRTIO_CAP_05VALUE_VF_virtio_cap_05value_vf(unsigned int uvirtio_cap_05value_vf); +int iSetCPI_VIRTIO_CAP_06VALUE_VF_virtio_cap_06value_vf(unsigned int uvirtio_cap_06value_vf); +int iSetCPI_VIRTIO_CAP_07VALUE_VF_virtio_cap_07value_vf(unsigned int uvirtio_cap_07value_vf); +int iSetCPI_VIRTIO_CAP_08VALUE_VF_virtio_cap_08value_vf(unsigned int uvirtio_cap_08value_vf); +int iSetCPI_VIRTIO_CAP_09VALUE_VF_virtio_cap_09value_vf(unsigned int uvirtio_cap_09value_vf); +int iSetCPI_VIRTIO_CAP_10VALUE_VF_virtio_cap_10value_vf(unsigned int uvirtio_cap_10value_vf); +int iSetCPI_VIRTIO_CAP_11VALUE_VF_virtio_cap_11value_vf(unsigned int uvirtio_cap_11value_vf); +int iSetCPI_VIRTIO_CAP_12VALUE_VF_virtio_cap_12value_vf(unsigned int uvirtio_cap_12value_vf); +int iSetCPI_VIRTIO_CAP_13VALUE_VF_virtio_cap_13value_vf(unsigned int uvirtio_cap_13value_vf); +int iSetCPI_VIRTIO_CAP_14VALUE_VF_virtio_cap_14value_vf(unsigned int uvirtio_cap_14value_vf); +int iSetCPI_VIRTIO_CAP_15VALUE_VF_virtio_cap_15value_vf(unsigned int uvirtio_cap_15value_vf); +int iSetCPI_VIRTIO_CAP_16VALUE_VF_virtio_cap_16value_vf(unsigned int uvirtio_cap_16value_vf); +int iSetDFX_DMATOP_RAM_ECC_CERR_dmatop_ecc_cerr(unsigned int udmatop_ecc_cerr); +int iSetDFX_DMATOP_RAM_ECC_UCERR_dmatop_ecc_ucerr(unsigned int udmatop_ecc_ucerr); +int iSetDFX_DMATOP_RAM_ERR_ADDR_dmatop_ecc_err_addr(unsigned int udmatop_ecc_err_addr); +int iSetDMATOP_ECC_INJ_REQ_dmatop_ecc_inj_req(unsigned int udmatop_ecc_inj_req); +int iSetDMATOP_DBG_FIFO_ST_A_pdi_fifo_a(unsigned int updi_fifo_a); +int iSetDMATOP_DBG_FIFO_ST_B_pdi_fifo_b(unsigned int updi_fifo_b); +int iSetDMATOP_DBG_FIFO_ST_C_pdi_fifo_c(unsigned int updi_fifo_c); +int iSetDMATOP_DBG_FIFO_ST_D_pdi_fifo_d(unsigned int updi_fifo_d); +int iSetDMATOP_DBG_FIFO_ST_E_pdi_fifo_e(unsigned int updi_fifo_e); +int iSetDMATOP_DBG_FIFO_ST_F_pdi_fifo_f(unsigned int updi_fifo_f); +int iSetDMATOP_DBG_FIFO_ST_G_pdi_fifo_g(unsigned int updi_fifo_g); +int iSetDMATOP_DBG_FIFO_ST_H_pdi_fifo_h(unsigned int updi_fifo_h); +int iSetDMATOP_DBG_FIFO_ST_I_pdi_fifo_i(unsigned int updi_fifo_i); +int iSetDMATOP_DBG_FIFO_ST_J_pdi_fifo_j(unsigned int updi_fifo_j); +int iSetDMATOP_DBG_FIFO_ST_K_pdi_fifo_k(unsigned int updi_fifo_k); +int iSetDMATOP_DBG_FIFO_ST_L_pdi_fifo_l(unsigned int updi_fifo_l); +int iSetDMATOP_DBG_FIFO_ST_M_pdi_fifo_m(unsigned int updi_fifo_m); +int iSetDMATOP_DBG_FIFO_ST_N_pdi_fifo_n(unsigned int updi_fifo_n); +int iSetDMATOP_DBG_FIFO_ST_O_pdi_fifo_o(unsigned int updi_fifo_o); +int iSetDMATOP_DBG_FIFO_ST_P_pdi_fifo_p(unsigned int updi_fifo_p); +int iSetDMATOP_DBG_FIFO_ST_Q_pdi_fifo_q(unsigned int updi_fifo_q); +int iSetDMATOP_DBG_FIFO_ST_R_pdi_fifo_r(unsigned int updi_fifo_r); +int iSetDMATOP_DBG_FIFO_ST_S_pdi_fifo_s(unsigned int updi_fifo_s); +int iSetDMATOP_DBG_FIFO_ST_T_pdi_fifo_t(unsigned int updi_fifo_t); +int iSetDMATOP_DBG_FIFO_ST_U_pdi_fifo_u(unsigned int updi_fifo_u); +int iSetDMATOP_DBG_OUT_A_pdi_out_a(unsigned int updi_out_a); +int iSetDMATOP_DBG_OUT_B_pdi_out_b(unsigned int updi_out_b); +int iSetDMATOP_DBG_OUT_C_pdi_out_c(unsigned int updi_out_c); + +/* Define the union csr_dp_normal_chl_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pipe_chl_act_en : 20; /* [19:0] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dp_normal_chl_en_u; + +/* Define the union csr_icpl_ram_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reorder_buf_init_start : 1; /* [0] */ + u32 icpl_bitmap_init_start : 5; /* [5:1] */ + u32 pre_fifo_cfg : 1; /* [6] */ + u32 icpl_cmd_info_init_start : 1; /* [7] */ + u32 icpl_res_init_start : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ram_init_u; + +/* Define the union csr_icpl_ram_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reorder_buf_init_done : 1; /* [0] */ + u32 icpl_tag_bitmap_init_done : 5; /* [5:1] */ + u32 icpl_cmd_bitmap_init_done : 5; /* [10:6] */ + u32 icpl_cmd_info_init_done : 1; /* [11] */ + u32 rsv_2 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ram_status_u; + +/* Define the union csr_icpl_fifo_aful_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cpld_fifo_af_cmd_th : 4; /* [3:0] */ + u32 cfg_cpld_fifo_af_dat_th : 4; /* [7:4] */ + u32 cfg_cpld_rdr_af_th : 3; /* [10:8] */ + u32 rsv_3 : 1; /* [11] */ + u32 cfg_cpld_tag_rls_af_th : 2; /* [13:12] */ + u32 rsv_4 : 2; /* [15:14] */ + u32 cfg_rdr_buf_pre_fifo_af_th : 3; /* [18:16] */ + u32 rsv_5 : 1; /* [19] */ + u32 cfg_rdr_buf_nonl2_af_th : 3; /* [22:20] */ + u32 rsv_6 : 1; /* [23] */ + u32 out_fifo_crdt_emp_gap : 4; /* [27:24] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_fifo_aful_ctl_u; + +/* Define the union csr_icpl_fifo_aful_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 out_fifo_af_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_fifo_aful_ctl1_u; + +/* Define the union csr_icpl_res_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bp_dpath_tag_div4 : 8; /* [7:0] */ + u32 bp_cpath_tag_div4 : 8; /* [15:8] */ + u32 bp_tag_num_div4 : 8; /* [23:16] */ + u32 pcie_tag_type : 1; /* [24] */ + u32 rsv_8 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_res_cfg_u; + +/* Define the union csr_icpl_tag_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_tag_cnt : 10; /* [9:0] */ + u32 rsv_9 : 6; /* [15:10] */ + u32 dpath_tag_cnt : 10; /* [25:16] */ + u32 rsv_10 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_tag_cnt_u; + +/* Define the union csr_icpl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_pkt_cnt : 10; /* [9:0] */ + u32 rsv_11 : 6; /* [15:10] */ + u32 dpath_pkt_cnt : 10; /* [25:16] */ + u32 rsv_12 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_pkt_cnt_u; + +/* Define the union csr_icpl_tag_base_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_tag_num_div4 : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_tag_base_u; + +/* Define the union csr_icpl_rdr_buf0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 non_pkt_buf_num : 11; /* [10:0] */ + u32 rsv_14 : 5; /* [15:11] */ + u32 pkt_buf_num : 11; /* [26:16] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rdr_buf0_u; + +/* Define the union csr_icpl_rdr_buf1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type1_buf_num : 11; /* [10:0] */ + u32 rsv_16 : 5; /* [15:11] */ + u32 type0_buf_num : 11; /* [26:16] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rdr_buf1_u; + +/* Define the union csr_icpl_arb_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_reodr_acc_weight_port : 12; /* [11:0] */ + u32 rsv_18 : 4; /* [15:12] */ + u32 icpl_reodr_pre_weight_port : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_arb_weight0_u; + +/* Define the union csr_icpl_arb_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 16; /* [15:0] */ + u32 icpl_pre_fifo_weight_port : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_arb_weight1_u; + +/* Define the union csr_icpl_arb_weight2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_20 : 8; /* [7:0] */ + u32 info_wrr_weight : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_arb_weight2_u; + +/* Define the union csr_icpl_ctrl_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_tag_use_mode : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ctrl_mod_u; + +/* Define the union csr_icpl_dbg_out_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_dbg_out_sel : 2; /* [1:0] */ + u32 rsv_22 : 2; /* [3:2] */ + u32 icpl_reodr_buf_vld_sel : 6; /* [9:4] */ + u32 icpl_dfx_cnt_en : 1; /* [10] */ + u32 rsv_23 : 1; /* [11] */ + u32 icpl_reodr_buf_rd_st_sel : 5; /* [16:12] */ + u32 rsv_24 : 7; /* [23:17] */ + u32 dfx_icpl_tag_round_trip_en : 1; /* [24] */ + u32 icpl_pkt_err_send_ceq_en : 1; /* [25] */ + u32 icpl_tag_round_type : 1; /* [26] */ + u32 icpl_atomic_soro_cfg : 2; /* [28:27] */ + u32 icpl_atomic_endian : 1; /* [29] */ + u32 icpl_atomic_64b_swap_mode : 1; /* [30] */ + u32 rsv_25 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_sel_u; + +/* Define the union csr_icpl_rtt_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_rtt_unit : 8; /* [7:0] */ + u32 rsv_26 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_ctl_u; + +/* Define the union csr_icpl_rtt_tag_idx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_idx_b : 10; /* [9:0] */ + u32 rsv_27 : 6; /* [15:10] */ + u32 dfx_icpl_tag_idx_a : 10; /* [25:16] */ + u32 rsv_28 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_tag_idx0_u; + +/* Define the union csr_icpl_rtt_tag_idx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_idx_d : 10; /* [9:0] */ + u32 rsv_29 : 6; /* [15:10] */ + u32 dfx_icpl_tag_idx_c : 10; /* [25:16] */ + u32 rsv_30 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_tag_idx1_u; + +/* Define the union csr_icpl_rtt_tag_idx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_idx_e : 10; /* [9:0] */ + u32 rsv_31 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_tag_idx2_u; + +/* Define the union csr_icpl_rtt_rang_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_snap : 1; /* [0] */ + u32 rsv_32 : 27; /* [27:1] */ + u32 dfx_icpl_tag_range_port : 3; /* [30:28] */ + u32 rsv_33 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang_ctl_u; + +/* Define the union csr_icpl_rtt_rang1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_a : 24; /* [23:0] */ + u32 rsv_34 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang1_u; + +/* Define the union csr_icpl_rtt_rang2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_b : 24; /* [23:0] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang2_u; + +/* Define the union csr_icpl_rtt_rang3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_c : 24; /* [23:0] */ + u32 rsv_36 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang3_u; + +/* Define the union csr_icpl_rtt_rang4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_d : 24; /* [23:0] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang4_u; + +/* Define the union csr_icpl_rtt_cur_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_rtt_cur : 24; /* [23:0] */ + u32 rsv_38 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_cur_u; + +/* Define the union csr_icpl_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_a_u; + +/* Define the union csr_icpl_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_b_u; + +/* Define the union csr_icpl_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_c_u; + +/* Define the union csr_icpl_dbg_out_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_d_u; + +/* Define the union csr_icpl_dbg_out_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_e_u; + +/* Define the union csr_icpl_dbg_out_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_f_u; + +/* Define the union csr_icpl_dbg_out_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_g_u; + +/* Define the union csr_icpl_dbg_out_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_h_u; + +/* Define the union csr_icpl_dbg_out_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_i_u; + +/* Define the union csr_icpl_dbg_out_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_j_u; + +/* Define the union csr_icpl_dbg_out_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_k_u; + +/* Define the union csr_icpl_dbg_out_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_l_u; + +/* Define the union csr_icpl_dbg_out_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_m_u; + +/* Define the union csr_icpl_dbg_out_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_n_u; + +/* Define the union csr_icpl_dbg_out_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_o_u; + +/* Define the union csr_icpl_dbg_out_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_p_u; + +/* Define the union csr_icpl_dbg_out_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_q_u; + +/* Define the union csr_icpl_dbg_out_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_r_u; + +/* Define the union csr_icpl_dbg_out_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_s_u; + +/* Define the union csr_icpl_dbg_out_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_t_u; + +/* Define the union csr_icpl_dbg_out_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_u_u; + +/* Define the union csr_icpl_dbg_out_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_v_u; + +/* Define the union csr_icpl_dbg_out_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_w_u; + +/* Define the union csr_icpl_dbg_out_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_x_u; + +/* Define the union csr_icpl_dbg_out_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_y_u; + +/* Define the union csr_icpl_dbg_out_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_z : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_z_u; + +/* Define the union csr_icpl_db_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_idx_sel : 5; /* [4:0] */ + u32 rsv_39 : 2; /* [6:5] */ + u32 icpl_chl_idx_sel_for_cdpath : 1; /* [7] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_db_sel_u; + +/* Define the union csr_icpl_dbg_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_eop_cnt : 16; /* [15:0] */ + u32 icpl_chl_sop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt0_u; + +/* Define the union csr_icpl_dbg_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_eor_cnt : 16; /* [15:0] */ + u32 icpl_chl_sor_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt1_u; + +/* Define the union csr_icpl_dbg_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_inl_bak_miss_cnt : 16; /* [15:0] */ + u32 icpl_inl_bak_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt2_u; + +/* Define the union csr_icpl_dbg_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_inl_2osch_cnt : 16; /* [15:0] */ + u32 icpl_inl_2osch_miss_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt3_u; + +/* Define the union csr_icpl_dbg_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_aad_bak_cnt : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt4_u; + +/* Define the union csr_icpl_dbg_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_aad_bak_eop_cnt : 16; /* [15:0] */ + u32 icpl_aad_bak_sop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt5_u; + +/* Define the union csr_icpl_chl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_pkt_eop_cnt : 16; /* [15:0] */ + u32 icpl_chl_pkt_sop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_chl_cnt_u; + +/* Define the union csr_icpl_dbg_fifo_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_a_u; + +/* Define the union csr_icpl_dbg_fifo_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_b_u; + +/* Define the union csr_icpl_dbg_fifo_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_c_u; + +/* Define the union csr_icpl_dbg_fifo_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_d_u; + +/* Define the union csr_icpl_dbg_fifo_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_e_u; + +/* Define the union csr_icpl_dbg_fifo_st_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_f_u; + +/* Define the union csr_icpl_dbg_fifo_st_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_g_u; + +/* Define the union csr_icpl_dbg_fifo_st_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_h_u; + +/* Define the union csr_icpl_dbg_fifo_st_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_i_u; + +/* Define the union csr_icpl_dbg_fifo_st_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_j_u; + +/* Define the union csr_icpl_dbg_fifo_st_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_k_u; + +/* Define the union csr_icpl_dbg_fifo_st_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_l_u; + +/* Define the union csr_icpl_dbg_fifo_st_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_m_u; + +/* Define the union csr_icpl_dbg_fifo_st_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_n_u; + +/* Define the union csr_icpl_dbg_fifo_st_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_o_u; + +/* Define the union csr_icpl_dbg_fifo_st_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_p_u; + +/* Define the union csr_icpl_dbg_fifo_st_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_q_u; + +/* Define the union csr_icpl_dbg_fifo_st_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_r_u; + +/* Define the union csr_icpl_dbg_fifo_st_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_s_u; + +/* Define the union csr_icpl_dbg_fifo_st_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_t_u; + +/* Define the union csr_icpl_dbg_fifo_st_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_u_u; + +/* Define the union csr_icpl_dbg_fifo_st_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_v_u; + +/* Define the union csr_icpl_dbg_fifo_st_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_w_u; + +/* Define the union csr_icpl_dbg_fifo_st_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_x_u; + +/* Define the union csr_icpl_dbg_fifo_st_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_y_u; + +/* Define the union csr_icpl_plsa_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsa_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsa_fatal_msk_u; + +/* Define the union csr_icpl_plsa_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsa_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsa_nonfatal_msk_u; + +/* Define the union csr_icpl_plsa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsa : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsa_u; + +/* Define the union csr_icpl_plsb_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsb_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsb_fatal_msk_u; + +/* Define the union csr_icpl_plsb_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsb_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsb_nonfatal_msk_u; + +/* Define the union csr_icpl_plsb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsb_u; + +/* Define the union csr_dfx_icpl_ram_ecc_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_cerr : 13; /* [12:0] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_icpl_ram_ecc_cerr_u; + +/* Define the union csr_dfx_icpl_ram_ecc_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_ucerr : 13; /* [12:0] */ + u32 rsv_43 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_icpl_ram_ecc_ucerr_u; + +/* Define the union csr_dfx_icpl_ram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_err_addr : 24; /* [23:0] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_icpl_ram_err_addr_u; + +/* Define the union csr_icpl_ecc_inj_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_inj_req : 26; /* [25:0] */ + u32 rsv_45 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ecc_inj_req_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_dp_normal_chl_en_u dp_normal_chl_en; /* 0 */ + volatile csr_icpl_ram_init_u icpl_ram_init; /* 44 */ + volatile csr_icpl_ram_status_u icpl_ram_status; /* 48 */ + volatile csr_icpl_fifo_aful_ctl_u icpl_fifo_aful_ctl; /* 50 */ + volatile csr_icpl_fifo_aful_ctl1_u icpl_fifo_aful_ctl1; /* 54 */ + volatile csr_icpl_res_cfg_u icpl_res_cfg[5]; /* 100 */ + volatile csr_icpl_tag_cnt_u icpl_tag_cnt[5]; /* 104 */ + volatile csr_icpl_pkt_cnt_u icpl_pkt_cnt[5]; /* 108 */ + volatile csr_icpl_tag_base_u icpl_tag_base[5]; /* 10C */ + volatile csr_icpl_rdr_buf0_u icpl_rdr_buf0[5]; /* 110 */ + volatile csr_icpl_rdr_buf1_u icpl_rdr_buf1[5]; /* 114 */ + volatile csr_icpl_arb_weight0_u icpl_arb_weight0; /* 1A0 */ + volatile csr_icpl_arb_weight1_u icpl_arb_weight1; /* 1A4 */ + volatile csr_icpl_arb_weight2_u icpl_arb_weight2; /* 1A8 */ + volatile csr_icpl_ctrl_mod_u icpl_ctrl_mod; /* 1AC */ + volatile csr_icpl_dbg_out_sel_u icpl_dbg_out_sel; /* 300 */ + volatile csr_icpl_rtt_ctl_u icpl_rtt_ctl; /* 304 */ + volatile csr_icpl_rtt_tag_idx0_u icpl_rtt_tag_idx0; /* 308 */ + volatile csr_icpl_rtt_tag_idx1_u icpl_rtt_tag_idx1; /* 30C */ + volatile csr_icpl_rtt_tag_idx2_u icpl_rtt_tag_idx2; /* 310 */ + volatile csr_icpl_rtt_rang_ctl_u icpl_rtt_rang_ctl; /* 314 */ + volatile csr_icpl_rtt_rang1_u icpl_rtt_rang1; /* 318 */ + volatile csr_icpl_rtt_rang2_u icpl_rtt_rang2; /* 31C */ + volatile csr_icpl_rtt_rang3_u icpl_rtt_rang3; /* 320 */ + volatile csr_icpl_rtt_rang4_u icpl_rtt_rang4; /* 324 */ + volatile csr_icpl_rtt_cur_u icpl_rtt_cur; /* 328 */ + volatile csr_icpl_dbg_out_a_u icpl_dbg_out_a; /* 360 */ + volatile csr_icpl_dbg_out_b_u icpl_dbg_out_b; /* 364 */ + volatile csr_icpl_dbg_out_c_u icpl_dbg_out_c; /* 368 */ + volatile csr_icpl_dbg_out_d_u icpl_dbg_out_d; /* 36C */ + volatile csr_icpl_dbg_out_e_u icpl_dbg_out_e; /* 370 */ + volatile csr_icpl_dbg_out_f_u icpl_dbg_out_f; /* 374 */ + volatile csr_icpl_dbg_out_g_u icpl_dbg_out_g; /* 378 */ + volatile csr_icpl_dbg_out_h_u icpl_dbg_out_h; /* 37C */ + volatile csr_icpl_dbg_out_i_u icpl_dbg_out_i; /* 380 */ + volatile csr_icpl_dbg_out_j_u icpl_dbg_out_j; /* 384 */ + volatile csr_icpl_dbg_out_k_u icpl_dbg_out_k; /* 388 */ + volatile csr_icpl_dbg_out_l_u icpl_dbg_out_l; /* 38C */ + volatile csr_icpl_dbg_out_m_u icpl_dbg_out_m; /* 390 */ + volatile csr_icpl_dbg_out_n_u icpl_dbg_out_n; /* 394 */ + volatile csr_icpl_dbg_out_o_u icpl_dbg_out_o; /* 398 */ + volatile csr_icpl_dbg_out_p_u icpl_dbg_out_p; /* 39C */ + volatile csr_icpl_dbg_out_q_u icpl_dbg_out_q; /* 3A0 */ + volatile csr_icpl_dbg_out_r_u icpl_dbg_out_r; /* 3A4 */ + volatile csr_icpl_dbg_out_s_u icpl_dbg_out_s; /* 3A8 */ + volatile csr_icpl_dbg_out_t_u icpl_dbg_out_t; /* 3AC */ + volatile csr_icpl_dbg_out_u_u icpl_dbg_out_u; /* 3B0 */ + volatile csr_icpl_dbg_out_v_u icpl_dbg_out_v; /* 3B4 */ + volatile csr_icpl_dbg_out_w_u icpl_dbg_out_w; /* 3B8 */ + volatile csr_icpl_dbg_out_x_u icpl_dbg_out_x; /* 3BC */ + volatile csr_icpl_dbg_out_y_u icpl_dbg_out_y; /* 3C0 */ + volatile csr_icpl_dbg_out_z_u icpl_dbg_out_z; /* 3C4 */ + volatile csr_icpl_db_sel_u icpl_db_sel[8]; /* 400 */ + volatile csr_icpl_dbg_cnt0_u icpl_dbg_cnt0[8]; /* 408 */ + volatile csr_icpl_dbg_cnt1_u icpl_dbg_cnt1[8]; /* 40C */ + volatile csr_icpl_dbg_cnt2_u icpl_dbg_cnt2; /* 480 */ + volatile csr_icpl_dbg_cnt3_u icpl_dbg_cnt3; /* 484 */ + volatile csr_icpl_dbg_cnt4_u icpl_dbg_cnt4; /* 488 */ + volatile csr_icpl_dbg_cnt5_u icpl_dbg_cnt5; /* 48C */ + volatile csr_icpl_chl_cnt_u icpl_chl_cnt[20]; /* 490 */ + volatile csr_icpl_dbg_fifo_st_a_u icpl_dbg_fifo_st_a; /* 500 */ + volatile csr_icpl_dbg_fifo_st_b_u icpl_dbg_fifo_st_b; /* 504 */ + volatile csr_icpl_dbg_fifo_st_c_u icpl_dbg_fifo_st_c; /* 508 */ + volatile csr_icpl_dbg_fifo_st_d_u icpl_dbg_fifo_st_d; /* 50C */ + volatile csr_icpl_dbg_fifo_st_e_u icpl_dbg_fifo_st_e; /* 510 */ + volatile csr_icpl_dbg_fifo_st_f_u icpl_dbg_fifo_st_f; /* 514 */ + volatile csr_icpl_dbg_fifo_st_g_u icpl_dbg_fifo_st_g; /* 518 */ + volatile csr_icpl_dbg_fifo_st_h_u icpl_dbg_fifo_st_h; /* 51C */ + volatile csr_icpl_dbg_fifo_st_i_u icpl_dbg_fifo_st_i; /* 520 */ + volatile csr_icpl_dbg_fifo_st_j_u icpl_dbg_fifo_st_j; /* 524 */ + volatile csr_icpl_dbg_fifo_st_k_u icpl_dbg_fifo_st_k; /* 528 */ + volatile csr_icpl_dbg_fifo_st_l_u icpl_dbg_fifo_st_l; /* 52C */ + volatile csr_icpl_dbg_fifo_st_m_u icpl_dbg_fifo_st_m; /* 530 */ + volatile csr_icpl_dbg_fifo_st_n_u icpl_dbg_fifo_st_n; /* 534 */ + volatile csr_icpl_dbg_fifo_st_o_u icpl_dbg_fifo_st_o; /* 538 */ + volatile csr_icpl_dbg_fifo_st_p_u icpl_dbg_fifo_st_p; /* 53C */ + volatile csr_icpl_dbg_fifo_st_q_u icpl_dbg_fifo_st_q; /* 540 */ + volatile csr_icpl_dbg_fifo_st_r_u icpl_dbg_fifo_st_r; /* 544 */ + volatile csr_icpl_dbg_fifo_st_s_u icpl_dbg_fifo_st_s; /* 548 */ + volatile csr_icpl_dbg_fifo_st_t_u icpl_dbg_fifo_st_t; /* 54C */ + volatile csr_icpl_dbg_fifo_st_u_u icpl_dbg_fifo_st_u; /* 550 */ + volatile csr_icpl_dbg_fifo_st_v_u icpl_dbg_fifo_st_v; /* 554 */ + volatile csr_icpl_dbg_fifo_st_w_u icpl_dbg_fifo_st_w; /* 558 */ + volatile csr_icpl_dbg_fifo_st_x_u icpl_dbg_fifo_st_x; /* 55C */ + volatile csr_icpl_dbg_fifo_st_y_u icpl_dbg_fifo_st_y; /* 560 */ + volatile csr_icpl_plsa_fatal_msk_u icpl_plsa_fatal_msk; /* 5E0 */ + volatile csr_icpl_plsa_nonfatal_msk_u icpl_plsa_nonfatal_msk; /* 5E4 */ + volatile csr_icpl_plsa_u icpl_plsa; /* 5E8 */ + volatile csr_icpl_plsb_fatal_msk_u icpl_plsb_fatal_msk; /* 5F0 */ + volatile csr_icpl_plsb_nonfatal_msk_u icpl_plsb_nonfatal_msk; /* 5F4 */ + volatile csr_icpl_plsb_u icpl_plsb; /* 5F8 */ + volatile csr_dfx_icpl_ram_ecc_cerr_u dfx_icpl_ram_ecc_cerr; /* 600 */ + volatile csr_dfx_icpl_ram_ecc_ucerr_u dfx_icpl_ram_ecc_ucerr; /* 604 */ + volatile csr_dfx_icpl_ram_err_addr_u dfx_icpl_ram_err_addr; /* 608 */ + volatile csr_icpl_ecc_inj_req_u icpl_ecc_inj_req; /* 610 */ +} S_cpi_icpl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_icpl_csr */ +extern volatile S_cpi_icpl_csr_REGS_TYPE *gopcpi_icpl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetDP_NORMAL_CHL_EN_pipe_chl_act_en(unsigned int upipe_chl_act_en); +int iSetICPL_RAM_INIT_reorder_buf_init_start(unsigned int ureorder_buf_init_start); +int iSetICPL_RAM_INIT_icpl_bitmap_init_start(unsigned int uicpl_bitmap_init_start); +int iSetICPL_RAM_INIT_pre_fifo_cfg(unsigned int upre_fifo_cfg); +int iSetICPL_RAM_INIT_icpl_cmd_info_init_start(unsigned int uicpl_cmd_info_init_start); +int iSetICPL_RAM_INIT_icpl_res_init_start(unsigned int uicpl_res_init_start); +int iSetICPL_RAM_STATUS_reorder_buf_init_done(unsigned int ureorder_buf_init_done); +int iSetICPL_RAM_STATUS_icpl_tag_bitmap_init_done(unsigned int uicpl_tag_bitmap_init_done); +int iSetICPL_RAM_STATUS_icpl_cmd_bitmap_init_done(unsigned int uicpl_cmd_bitmap_init_done); +int iSetICPL_RAM_STATUS_icpl_cmd_info_init_done(unsigned int uicpl_cmd_info_init_done); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_fifo_af_cmd_th(unsigned int ucfg_cpld_fifo_af_cmd_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_fifo_af_dat_th(unsigned int ucfg_cpld_fifo_af_dat_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_rdr_af_th(unsigned int ucfg_cpld_rdr_af_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_tag_rls_af_th(unsigned int ucfg_cpld_tag_rls_af_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_rdr_buf_pre_fifo_af_th(unsigned int ucfg_rdr_buf_pre_fifo_af_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_rdr_buf_nonl2_af_th(unsigned int ucfg_rdr_buf_nonl2_af_th); +int iSetICPL_FIFO_AFUL_CTL_out_fifo_crdt_emp_gap(unsigned int uout_fifo_crdt_emp_gap); +int iSetICPL_FIFO_AFUL_CTL1_out_fifo_af_th(unsigned int uout_fifo_af_th); +int iSetICPL_RES_CFG_bp_dpath_tag_div4(unsigned int ubp_dpath_tag_div4); +int iSetICPL_RES_CFG_bp_cpath_tag_div4(unsigned int ubp_cpath_tag_div4); +int iSetICPL_RES_CFG_bp_tag_num_div4(unsigned int ubp_tag_num_div4); +int iSetICPL_RES_CFG_pcie_tag_type(unsigned int upcie_tag_type); +int iSetICPL_TAG_CNT_cpath_tag_cnt(unsigned int ucpath_tag_cnt); +int iSetICPL_TAG_CNT_dpath_tag_cnt(unsigned int udpath_tag_cnt); +int iSetICPL_PKT_CNT_cpath_pkt_cnt(unsigned int ucpath_pkt_cnt); +int iSetICPL_PKT_CNT_dpath_pkt_cnt(unsigned int udpath_pkt_cnt); +int iSetICPL_TAG_BASE_max_tag_num_div4(unsigned int umax_tag_num_div4); +int iSetICPL_RDR_BUF0_non_pkt_buf_num(unsigned int unon_pkt_buf_num); +int iSetICPL_RDR_BUF0_pkt_buf_num(unsigned int upkt_buf_num); +int iSetICPL_RDR_BUF1_type1_buf_num(unsigned int utype1_buf_num); +int iSetICPL_RDR_BUF1_type0_buf_num(unsigned int utype0_buf_num); +int iSetICPL_ARB_WEIGHT0_icpl_reodr_acc_weight_port(unsigned int uicpl_reodr_acc_weight_port); +int iSetICPL_ARB_WEIGHT0_icpl_reodr_pre_weight_port(unsigned int uicpl_reodr_pre_weight_port); +int iSetICPL_ARB_WEIGHT1_icpl_pre_fifo_weight_port(unsigned int uicpl_pre_fifo_weight_port); +int iSetICPL_ARB_WEIGHT2_info_wrr_weight(unsigned int uinfo_wrr_weight); +int iSetICPL_CTRL_MOD_icpl_tag_use_mode(unsigned int uicpl_tag_use_mode); +int iSetICPL_DBG_OUT_SEL_icpl_dbg_out_sel(unsigned int uicpl_dbg_out_sel); +int iSetICPL_DBG_OUT_SEL_icpl_reodr_buf_vld_sel(unsigned int uicpl_reodr_buf_vld_sel); +int iSetICPL_DBG_OUT_SEL_icpl_dfx_cnt_en(unsigned int uicpl_dfx_cnt_en); +int iSetICPL_DBG_OUT_SEL_icpl_reodr_buf_rd_st_sel(unsigned int uicpl_reodr_buf_rd_st_sel); +int iSetICPL_DBG_OUT_SEL_dfx_icpl_tag_round_trip_en(unsigned int udfx_icpl_tag_round_trip_en); +int iSetICPL_DBG_OUT_SEL_icpl_pkt_err_send_ceq_en(unsigned int uicpl_pkt_err_send_ceq_en); +int iSetICPL_DBG_OUT_SEL_icpl_tag_round_type(unsigned int uicpl_tag_round_type); +int iSetICPL_DBG_OUT_SEL_icpl_atomic_soro_cfg(unsigned int uicpl_atomic_soro_cfg); +int iSetICPL_DBG_OUT_SEL_icpl_atomic_endian(unsigned int uicpl_atomic_endian); +int iSetICPL_DBG_OUT_SEL_icpl_atomic_64b_swap_mode(unsigned int uicpl_atomic_64b_swap_mode); +int iSetICPL_RTT_CTL_dfx_icpl_tag_rtt_unit(unsigned int udfx_icpl_tag_rtt_unit); +int iSetICPL_RTT_TAG_IDX0_dfx_icpl_tag_idx_b(unsigned int udfx_icpl_tag_idx_b); +int iSetICPL_RTT_TAG_IDX0_dfx_icpl_tag_idx_a(unsigned int udfx_icpl_tag_idx_a); +int iSetICPL_RTT_TAG_IDX1_dfx_icpl_tag_idx_d(unsigned int udfx_icpl_tag_idx_d); +int iSetICPL_RTT_TAG_IDX1_dfx_icpl_tag_idx_c(unsigned int udfx_icpl_tag_idx_c); +int iSetICPL_RTT_TAG_IDX2_dfx_icpl_tag_idx_e(unsigned int udfx_icpl_tag_idx_e); +int iSetICPL_RTT_RANG_CTL_dfx_icpl_tag_snap(unsigned int udfx_icpl_tag_snap); +int iSetICPL_RTT_RANG_CTL_dfx_icpl_tag_range_port(unsigned int udfx_icpl_tag_range_port); +int iSetICPL_RTT_RANG1_dfx_icpl_tag_range_a(unsigned int udfx_icpl_tag_range_a); +int iSetICPL_RTT_RANG2_dfx_icpl_tag_range_b(unsigned int udfx_icpl_tag_range_b); +int iSetICPL_RTT_RANG3_dfx_icpl_tag_range_c(unsigned int udfx_icpl_tag_range_c); +int iSetICPL_RTT_RANG4_dfx_icpl_tag_range_d(unsigned int udfx_icpl_tag_range_d); +int iSetICPL_RTT_CUR_dfx_icpl_tag_rtt_cur(unsigned int udfx_icpl_tag_rtt_cur); +int iSetICPL_DBG_OUT_A_dfx_icpl_out_a(unsigned int udfx_icpl_out_a); +int iSetICPL_DBG_OUT_B_dfx_icpl_out_b(unsigned int udfx_icpl_out_b); +int iSetICPL_DBG_OUT_C_dfx_icpl_out_c(unsigned int udfx_icpl_out_c); +int iSetICPL_DBG_OUT_D_dfx_icpl_out_d(unsigned int udfx_icpl_out_d); +int iSetICPL_DBG_OUT_E_dfx_icpl_out_e(unsigned int udfx_icpl_out_e); +int iSetICPL_DBG_OUT_F_dfx_icpl_out_f(unsigned int udfx_icpl_out_f); +int iSetICPL_DBG_OUT_G_dfx_icpl_out_g(unsigned int udfx_icpl_out_g); +int iSetICPL_DBG_OUT_H_dfx_icpl_out_h(unsigned int udfx_icpl_out_h); +int iSetICPL_DBG_OUT_I_dfx_icpl_out_i(unsigned int udfx_icpl_out_i); +int iSetICPL_DBG_OUT_J_dfx_icpl_out_j(unsigned int udfx_icpl_out_j); +int iSetICPL_DBG_OUT_K_dfx_icpl_out_k(unsigned int udfx_icpl_out_k); +int iSetICPL_DBG_OUT_L_dfx_icpl_out_l(unsigned int udfx_icpl_out_l); +int iSetICPL_DBG_OUT_M_dfx_icpl_out_m(unsigned int udfx_icpl_out_m); +int iSetICPL_DBG_OUT_N_dfx_icpl_out_n(unsigned int udfx_icpl_out_n); +int iSetICPL_DBG_OUT_O_dfx_icpl_out_o(unsigned int udfx_icpl_out_o); +int iSetICPL_DBG_OUT_P_dfx_icpl_out_p(unsigned int udfx_icpl_out_p); +int iSetICPL_DBG_OUT_Q_dfx_icpl_out_q(unsigned int udfx_icpl_out_q); +int iSetICPL_DBG_OUT_R_dfx_icpl_out_r(unsigned int udfx_icpl_out_r); +int iSetICPL_DBG_OUT_S_dfx_icpl_out_s(unsigned int udfx_icpl_out_s); +int iSetICPL_DBG_OUT_T_dfx_icpl_out_t(unsigned int udfx_icpl_out_t); +int iSetICPL_DBG_OUT_U_dfx_icpl_out_u(unsigned int udfx_icpl_out_u); +int iSetICPL_DBG_OUT_V_dfx_icpl_out_v(unsigned int udfx_icpl_out_v); +int iSetICPL_DBG_OUT_W_dfx_icpl_out_w(unsigned int udfx_icpl_out_w); +int iSetICPL_DBG_OUT_X_dfx_icpl_out_x(unsigned int udfx_icpl_out_x); +int iSetICPL_DBG_OUT_Y_dfx_icpl_out_y(unsigned int udfx_icpl_out_y); +int iSetICPL_DBG_OUT_Z_dfx_icpl_out_z(unsigned int udfx_icpl_out_z); +int iSetICPL_DB_SEL_icpl_chl_idx_sel(unsigned int uicpl_chl_idx_sel); +int iSetICPL_DB_SEL_icpl_chl_idx_sel_for_cdpath(unsigned int uicpl_chl_idx_sel_for_cdpath); +int iSetICPL_DBG_CNT0_icpl_chl_eop_cnt(unsigned int uicpl_chl_eop_cnt); +int iSetICPL_DBG_CNT0_icpl_chl_sop_cnt(unsigned int uicpl_chl_sop_cnt); +int iSetICPL_DBG_CNT1_icpl_chl_eor_cnt(unsigned int uicpl_chl_eor_cnt); +int iSetICPL_DBG_CNT1_icpl_chl_sor_cnt(unsigned int uicpl_chl_sor_cnt); +int iSetICPL_DBG_CNT2_icpl_inl_bak_miss_cnt(unsigned int uicpl_inl_bak_miss_cnt); +int iSetICPL_DBG_CNT2_icpl_inl_bak_cnt(unsigned int uicpl_inl_bak_cnt); +int iSetICPL_DBG_CNT3_icpl_inl_2osch_cnt(unsigned int uicpl_inl_2osch_cnt); +int iSetICPL_DBG_CNT3_icpl_inl_2osch_miss_cnt(unsigned int uicpl_inl_2osch_miss_cnt); +int iSetICPL_DBG_CNT4_icpl_aad_bak_cnt(unsigned int uicpl_aad_bak_cnt); +int iSetICPL_DBG_CNT5_icpl_aad_bak_eop_cnt(unsigned int uicpl_aad_bak_eop_cnt); +int iSetICPL_DBG_CNT5_icpl_aad_bak_sop_cnt(unsigned int uicpl_aad_bak_sop_cnt); +int iSetICPL_CHL_CNT_icpl_chl_pkt_eop_cnt(unsigned int uicpl_chl_pkt_eop_cnt); +int iSetICPL_CHL_CNT_icpl_chl_pkt_sop_cnt(unsigned int uicpl_chl_pkt_sop_cnt); +int iSetICPL_DBG_FIFO_ST_A_dfx_icpl_fifo_a(unsigned int udfx_icpl_fifo_a); +int iSetICPL_DBG_FIFO_ST_B_dfx_icpl_fifo_b(unsigned int udfx_icpl_fifo_b); +int iSetICPL_DBG_FIFO_ST_C_dfx_icpl_fifo_c(unsigned int udfx_icpl_fifo_c); +int iSetICPL_DBG_FIFO_ST_D_dfx_icpl_fifo_d(unsigned int udfx_icpl_fifo_d); +int iSetICPL_DBG_FIFO_ST_E_dfx_icpl_fifo_e(unsigned int udfx_icpl_fifo_e); +int iSetICPL_DBG_FIFO_ST_F_dfx_icpl_fifo_f(unsigned int udfx_icpl_fifo_f); +int iSetICPL_DBG_FIFO_ST_G_dfx_icpl_fifo_g(unsigned int udfx_icpl_fifo_g); +int iSetICPL_DBG_FIFO_ST_H_dfx_icpl_fifo_h(unsigned int udfx_icpl_fifo_h); +int iSetICPL_DBG_FIFO_ST_I_dfx_icpl_fifo_i(unsigned int udfx_icpl_fifo_i); +int iSetICPL_DBG_FIFO_ST_J_dfx_icpl_fifo_j(unsigned int udfx_icpl_fifo_j); +int iSetICPL_DBG_FIFO_ST_K_dfx_icpl_fifo_k(unsigned int udfx_icpl_fifo_k); +int iSetICPL_DBG_FIFO_ST_L_dfx_icpl_fifo_l(unsigned int udfx_icpl_fifo_l); +int iSetICPL_DBG_FIFO_ST_M_dfx_icpl_fifo_m(unsigned int udfx_icpl_fifo_m); +int iSetICPL_DBG_FIFO_ST_N_dfx_icpl_fifo_n(unsigned int udfx_icpl_fifo_n); +int iSetICPL_DBG_FIFO_ST_O_dfx_icpl_fifo_o(unsigned int udfx_icpl_fifo_o); +int iSetICPL_DBG_FIFO_ST_P_dfx_icpl_fifo_p(unsigned int udfx_icpl_fifo_p); +int iSetICPL_DBG_FIFO_ST_Q_dfx_icpl_fifo_q(unsigned int udfx_icpl_fifo_q); +int iSetICPL_DBG_FIFO_ST_R_dfx_icpl_fifo_r(unsigned int udfx_icpl_fifo_r); +int iSetICPL_DBG_FIFO_ST_S_dfx_icpl_fifo_s(unsigned int udfx_icpl_fifo_s); +int iSetICPL_DBG_FIFO_ST_T_dfx_icpl_fifo_t(unsigned int udfx_icpl_fifo_t); +int iSetICPL_DBG_FIFO_ST_U_dfx_icpl_fifo_u(unsigned int udfx_icpl_fifo_u); +int iSetICPL_DBG_FIFO_ST_V_dfx_icpl_fifo_v(unsigned int udfx_icpl_fifo_v); +int iSetICPL_DBG_FIFO_ST_W_dfx_icpl_fifo_w(unsigned int udfx_icpl_fifo_w); +int iSetICPL_DBG_FIFO_ST_X_dfx_icpl_fifo_x(unsigned int udfx_icpl_fifo_x); +int iSetICPL_DBG_FIFO_ST_Y_dfx_icpl_fifo_y(unsigned int udfx_icpl_fifo_y); +int iSetICPL_PLSA_FATAL_MSK_dfx_icpl_plsa_fatal_msk(unsigned int udfx_icpl_plsa_fatal_msk); +int iSetICPL_PLSA_NONFATAL_MSK_dfx_icpl_plsa_nonfatal_msk(unsigned int udfx_icpl_plsa_nonfatal_msk); +int iSetICPL_PLSA_dfx_icpl_plsa(unsigned int udfx_icpl_plsa); +int iSetICPL_PLSB_FATAL_MSK_dfx_icpl_plsb_fatal_msk(unsigned int udfx_icpl_plsb_fatal_msk); +int iSetICPL_PLSB_NONFATAL_MSK_dfx_icpl_plsb_nonfatal_msk(unsigned int udfx_icpl_plsb_nonfatal_msk); +int iSetICPL_PLSB_dfx_icpl_plsb(unsigned int udfx_icpl_plsb); +int iSetDFX_ICPL_RAM_ECC_CERR_icpl_ecc_cerr(unsigned int uicpl_ecc_cerr); +int iSetDFX_ICPL_RAM_ECC_UCERR_icpl_ecc_ucerr(unsigned int uicpl_ecc_ucerr); +int iSetDFX_ICPL_RAM_ERR_ADDR_icpl_ecc_err_addr(unsigned int uicpl_ecc_err_addr); +int iSetICPL_ECC_INJ_REQ_icpl_ecc_inj_req(unsigned int uicpl_ecc_inj_req); + +/* Define the union csr_intctl_int_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intctl_int_msk_af_th : 8; /* [7:0] */ + u32 intctl_int_trig_af_th : 8; /* [15:8] */ + u32 dfx_intctl_flr_vct_sel : 7; /* [22:16] */ + u32 rsv_0 : 1; /* [23] */ + u32 intctl_dbg_sel : 1; /* [24] */ + u32 rsv_1 : 3; /* [27:25] */ + u32 cfg_for_bp_set : 1; /* [28] */ + u32 cfg_msi_data_add : 1; /* [29] */ + u32 cfg_acc_mme_notchk : 1; /* [30] */ + u32 rsv_2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_int_ctl_u; + +/* Define the union csr_intctl_dbg_func_idx_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_bitmap__b : 8; /* [7:0] */ + u32 dfx_func_idx_bitmap__a : 8; /* [15:8] */ + u32 rsv_3 : 15; /* [30:16] */ + u32 dfx_func_idx_bitmap_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_bitmap_u; + +/* Define the union csr_intctl_dbg_func_idx_bitmap_wndw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_bitmap__win : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_bitmap_wndw_u; + +/* Define the union csr_intctl_dbg_func_idx_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_b : 12; /* [11:0] */ + u32 rsv_4 : 4; /* [15:12] */ + u32 dfx_func_idx_a : 12; /* [27:16] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ab_u; + +/* Define the union csr_intctl_dbg_func_idx_cd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_d : 12; /* [11:0] */ + u32 rsv_6 : 4; /* [15:12] */ + u32 dfx_func_idx_c : 12; /* [27:16] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_cd_u; + +/* Define the union csr_intctl_dbg_func_idx_ef_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_f : 12; /* [11:0] */ + u32 rsv_8 : 4; /* [15:12] */ + u32 dfx_func_idx_e : 12; /* [27:16] */ + u32 rsv_9 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ef_u; + +/* Define the union csr_intctl_dbg_func_idx_gh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_h : 12; /* [11:0] */ + u32 rsv_10 : 4; /* [15:12] */ + u32 dfx_func_idx_g : 12; /* [27:16] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_gh_u; + +/* Define the union csr_intctl_dbg_func_idx_ab_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_b_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_a_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ab_cnt_u; + +/* Define the union csr_intctl_dbg_func_idx_cd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_d_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_c_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_cd_cnt_u; + +/* Define the union csr_intctl_dbg_func_idx_ef_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_f_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_e_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ef_cnt_u; + +/* Define the union csr_intctl_dbg_func_idx_gh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_h_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_g_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_gh_cnt_u; + +/* Define the union csr_intctl_dbg_ipush_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ipush_cpl_cnt : 16; /* [15:0] */ + u32 dfx_intctl_ipush_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_ipush_cnt_u; + +/* Define the union csr_intctl_dbg_cfg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cfg_ack_rw_cnt : 16; /* [15:0] */ + u32 dfx_cfg_req_rw_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_cfg_cnt_u; + +/* Define the union csr_intctl_dbg_msk_trig_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_fun_msk_trig_cnt : 16; /* [15:0] */ + u32 dfx_per_msk_trig_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_msk_trig_cnt_u; + +/* Define the union csr_intctl_dbg_coal_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_coal_lli_in_cnt : 16; /* [15:0] */ + u32 dfx_coal_num_int_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_coal_cnt0_u; + +/* Define the union csr_intctl_dbg_coal_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_coal_time_int_cnt : 16; /* [15:0] */ + u32 dfx_coal_normal_in_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_coal_cnt1_u; + +/* Define the union csr_intctl_dbg_msi_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_msi_int_cnt : 16; /* [15:0] */ + u32 dfx_coal_num_drop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_msi_cnt_u; + +/* Define the union csr_intctl_dbg_msix_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pba_int_cnt : 16; /* [15:0] */ + u32 dfx_msix_int_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_msix_cnt_u; + +/* Define the union csr_intctl_dbg_vct_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trig_vct_cnt : 16; /* [15:0] */ + u32 dfx_normal_vct_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_vct_cnt_u; + +/* Define the union csr_intctl_dbg_intx_assert_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_ab_cnt : 16; /* [15:0] */ + u32 dfx_intx_aa_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_assert_cnt0_u; + +/* Define the union csr_intctl_dbg_intx_assert_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_ad_cnt : 16; /* [15:0] */ + u32 dfx_intx_ac_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_assert_cnt1_u; + +/* Define the union csr_intctl_dbg_intx_deassert_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_db_cnt : 16; /* [15:0] */ + u32 dfx_intx_da_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_deassert_cnt0_u; + +/* Define the union csr_intctl_dbg_intx_deassert_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_dd_cnt : 16; /* [15:0] */ + u32 dfx_intx_dc_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_deassert_cnt1_u; + +/* Define the union csr_intctl_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_a_u; + +/* Define the union csr_intctl_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_b_u; + +/* Define the union csr_intctl_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_c_u; + +/* Define the union csr_intctl_dbg_out_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_d_u; + +/* Define the union csr_intctl_dbg_out_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_e_u; + +/* Define the union csr_intctl_dbg_out_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_f_u; + +/* Define the union csr_intctl_dbg_out_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_g_u; + +/* Define the union csr_intctl_dbg_out_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_h_u; + +/* Define the union csr_intctl_dbg_out_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_i_u; + +/* Define the union csr_intctl_dbg_out_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_j_u; + +/* Define the union csr_intctl_dbg_out_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_k_u; + +/* Define the union csr_intctl_dbg_out_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_l_u; + +/* Define the union csr_intctl_dbg_out_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_m_u; + +/* Define the union csr_intctl_dbg_out_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_n_u; + +/* Define the union csr_intctl_dbg_out_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_o_u; + +/* Define the union csr_intctl_dbg_out_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_p_u; + +/* Define the union csr_intctl_dbg_out_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_q_u; + +/* Define the union csr_intctl_dbg_out_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_r_u; + +/* Define the union csr_intctl_dbg_out_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_s_u; + +/* Define the union csr_intctl_dbg_out_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_t_u; + +/* Define the union csr_intctl_dbg_out_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_u_u; + +/* Define the union csr_intctl_dbg_out_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_v_u; + +/* Define the union csr_intctl_dbg_out_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_w_u; + +/* Define the union csr_intctl_dbg_out_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_x_u; + +/* Define the union csr_intctl_dbg_out_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_y_u; + +/* Define the union csr_intctl_dbg_out_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_z : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_z_u; + +/* Define the union csr_intctl_dbg_fifo_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_a_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_a_u; + +/* Define the union csr_intctl_dbg_fifo_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_b_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_b_u; + +/* Define the union csr_intctl_dbg_fifo_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_c_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_c_u; + +/* Define the union csr_intctl_dbg_fifo_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_d_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_d_u; + +/* Define the union csr_intctl_dbg_fifo_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_e_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_e_u; + +/* Define the union csr_intctl_dbg_fifo_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_f_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_f_u; + +/* Define the union csr_intctl_dbg_fifo_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_g_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_g_u; + +/* Define the union csr_intctl_dbg_fifo_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_h_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_h_u; + +/* Define the union csr_intctl_dbg_fifo_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_i_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_i_u; + +/* Define the union csr_intctl_dbg_fifo_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_j_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_j_u; + +/* Define the union csr_intctl_dbg_fifo_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_k_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_k_u; + +/* Define the union csr_intctl_dbg_fifo_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_l_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_l_u; + +/* Define the union csr_intctl_dbg_fifo_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_m_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_m_u; + +/* Define the union csr_intctl_dbg_fifo_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_n_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_n_u; + +/* Define the union csr_intctl_dbg_fifo_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_o_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_o_u; + +/* Define the union csr_intctl_dbg_fifo_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_p_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_p_u; + +/* Define the union csr_intctl_dbg_fifo_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_q_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_q_u; + +/* Define the union csr_intctl_dbg_fifo_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_r_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_r_u; + +/* Define the union csr_intctl_dbg_drop_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_per_msk_drop_cnt : 16; /* [15:0] */ + u32 dfx_fm_msk_drop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_drop_msk_u; + +/* Define the union csr_intctl_msi_bp_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_msi_bp_timeout_1st : 16; /* [15:0] */ + u32 dfx_intctl_msi_bp_timeout4_2nd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_msi_bp_timeout_u; + +/* Define the union csr_intctl_msi_bp_timeout_2nd_01p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_msi_bp_timeout1_2nd : 16; /* [15:0] */ + u32 dfx_intctl_msi_bp_timeout0_2nd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_msi_bp_timeout_2nd_01p_u; + +/* Define the union csr_intctl_msi_bp_timeout_2nd_23p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_msi_bp_timeout3_2nd : 16; /* [15:0] */ + u32 dfx_intctl_msi_bp_timeout2_2nd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_msi_bp_timeout_2nd_23p_u; + +/* Define the union csr_intctl_flr_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_int_flr_limit : 10; /* [9:0] */ + u32 rsv_12 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_flr_limit_u; + +/* Define the union csr_intctl_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsvd : 29; /* [28:0] */ + u32 mpu_write_log_to_flash : 1; /* [29] */ + u32 npu_hot_update_active : 1; /* [30] */ + u32 mpu_hot_update_active : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_reservd_u; + +/* Define the union csr_intctl_out_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_a_fatal_msk_u; + +/* Define the union csr_intctl_out_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_a_nonfatal_msk_u; + +/* Define the union csr_intctl_dbg_out_a_plus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_a_plus_u; + +/* Define the union csr_intctl_out_b_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_b_fatal_msk_u; + +/* Define the union csr_intctl_out_b_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_b_nonfatal_msk_u; + +/* Define the union csr_intctl_dbg_out_b_plus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_b_plus_u; + +/* Define the union csr_intctl_ram_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcnt_ram_init_start : 1; /* [0] */ + u32 attr_ram_init_start : 1; /* [1] */ + u32 cap_ram_ini_start : 1; /* [2] */ + u32 pba_ram_init_start : 1; /* [3] */ + u32 msk_ram_init_start : 1; /* [4] */ + u32 tb_ram_init_start : 1; /* [5] */ + u32 int_num_init_start : 1; /* [6] */ + u32 msi_ram_ini_start : 1; /* [7] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ram_init_u; + +/* Define the union csr_intctl_ram_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcnt_ram_init_done : 1; /* [0] */ + u32 attr_ram_init_done : 1; /* [1] */ + u32 cap_ram_ini_done : 1; /* [2] */ + u32 pba_ram_init_done : 1; /* [3] */ + u32 msk_ram_init_done : 1; /* [4] */ + u32 tb_ram_init_done : 1; /* [5] */ + u32 int_num_init_done : 1; /* [6] */ + u32 msi_ram_ini_done : 1; /* [7] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ram_status_u; + +/* Define the union csr_intctl_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_intctl_allow_vf_cfg : 1; /* [0] */ + u32 cfg_msk_without_trig : 1; /* [1] */ + u32 rsv_15 : 1; /* [2] */ + u32 int_flr_no_clr_tab : 1; /* [3] */ + u32 intctl_coal_dbg_sel : 4; /* [7:4] */ + u32 cfg_msi_data_4byte_en : 5; /* [12:8] */ + u32 rsv_16 : 3; /* [15:13] */ + u32 cfg_msi_tlp_soro_nosnoop : 15; /* [30:16] */ + u32 rsv_17 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ctl_u; + +/* Define the union csr_intctl_res_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_per_pf : 4; /* [3:0] */ + u32 int_per_vf : 4; /* [7:4] */ + u32 rsv_18 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_res_u; + +/* Define the union csr_intctl_csr_acc_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intctl_csr_acc_weight_port : 8; /* [7:0] */ + u32 int_num_acc_weight : 12; /* [19:8] */ + u32 rsv_19 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_csr_acc_weight_u; + +/* Define the union csr_intctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_nxt_ptr : 8; /* [7:0] */ + u32 msix_nxt_ptr_pf : 8; /* [15:8] */ + u32 msix_nxt_ptr_vf : 8; /* [23:16] */ + u32 ipush_intctl_allow_pf_cfg : 1; /* [24] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl1_u; + +/* Define the union csr_intctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msien_crdt_gap : 6; /* [5:0] */ + u32 rsv_21 : 2; /* [7:6] */ + u32 msien_snap_2_virtio_en : 1; /* [8] */ + u32 rsv_22 : 3; /* [11:9] */ + u32 cfg_int_msk_aful_th : 3; /* [14:12] */ + u32 rsv_23 : 1; /* [15] */ + u32 cfg_intctl_csr_in_th : 2; /* [17:16] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl2_u; + +/* Define the union csr_intctl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_nxt_ptr_vf_with_vio : 8; /* [7:0] */ + u32 msix_at_cfg : 10; /* [17:8] */ + u32 rsv_25 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl3_u; + +/* Define the union csr_dfx_intctl_ram_ecc_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_ecc_cerr : 12; /* [11:0] */ + u32 rsv_26 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_ecc_cerr_u; + +/* Define the union csr_dfx_intctl_ram_ecc_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_ecc_ucerr : 12; /* [11:0] */ + u32 rsv_27 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_ecc_ucerr_u; + +/* Define the union csr_dfx_intctl_ram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_err_addr : 24; /* [23:0] */ + u32 rsv_28 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_err_addr_u; + +/* Define the union csr_dfx_intctl_ram_multi_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_multi_err_addr : 24; /* [23:0] */ + u32 rsv_29 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_multi_err_addr_u; + +/* Define the union csr_intctl_ecc_inj_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intctl_ecc_inj_req : 24; /* [23:0] */ + u32 rsv_30 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ecc_inj_req_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_intctl_int_ctl_u intctl_int_ctl; /* 0 */ + volatile csr_intctl_dbg_func_idx_bitmap_u intctl_dbg_func_idx_bitmap; /* 8 */ + volatile csr_intctl_dbg_func_idx_bitmap_wndw_u intctl_dbg_func_idx_bitmap_wndw; /* C */ + volatile csr_intctl_dbg_func_idx_ab_u intctl_dbg_func_idx_ab; /* 10 */ + volatile csr_intctl_dbg_func_idx_cd_u intctl_dbg_func_idx_cd; /* 14 */ + volatile csr_intctl_dbg_func_idx_ef_u intctl_dbg_func_idx_ef; /* 18 */ + volatile csr_intctl_dbg_func_idx_gh_u intctl_dbg_func_idx_gh; /* 1C */ + volatile csr_intctl_dbg_func_idx_ab_cnt_u intctl_dbg_func_idx_ab_cnt; /* 20 */ + volatile csr_intctl_dbg_func_idx_cd_cnt_u intctl_dbg_func_idx_cd_cnt; /* 24 */ + volatile csr_intctl_dbg_func_idx_ef_cnt_u intctl_dbg_func_idx_ef_cnt; /* 28 */ + volatile csr_intctl_dbg_func_idx_gh_cnt_u intctl_dbg_func_idx_gh_cnt; /* 2C */ + volatile csr_intctl_dbg_ipush_cnt_u intctl_dbg_ipush_cnt; /* 30 */ + volatile csr_intctl_dbg_cfg_cnt_u intctl_dbg_cfg_cnt; /* 34 */ + volatile csr_intctl_dbg_msk_trig_cnt_u intctl_dbg_msk_trig_cnt; /* 38 */ + volatile csr_intctl_dbg_coal_cnt0_u intctl_dbg_coal_cnt0; /* 3C */ + volatile csr_intctl_dbg_coal_cnt1_u intctl_dbg_coal_cnt1; /* 40 */ + volatile csr_intctl_dbg_msi_cnt_u intctl_dbg_msi_cnt; /* 44 */ + volatile csr_intctl_dbg_msix_cnt_u intctl_dbg_msix_cnt; /* 48 */ + volatile csr_intctl_dbg_vct_cnt_u intctl_dbg_vct_cnt; /* 4C */ + volatile csr_intctl_dbg_intx_assert_cnt0_u intctl_dbg_intx_assert_cnt0; /* 50 */ + volatile csr_intctl_dbg_intx_assert_cnt1_u intctl_dbg_intx_assert_cnt1; /* 54 */ + volatile csr_intctl_dbg_intx_deassert_cnt0_u intctl_dbg_intx_deassert_cnt0; /* 58 */ + volatile csr_intctl_dbg_intx_deassert_cnt1_u intctl_dbg_intx_deassert_cnt1; /* 5C */ + volatile csr_intctl_dbg_out_a_u intctl_dbg_out_a; /* 60 */ + volatile csr_intctl_dbg_out_b_u intctl_dbg_out_b; /* 64 */ + volatile csr_intctl_dbg_out_c_u intctl_dbg_out_c; /* 68 */ + volatile csr_intctl_dbg_out_d_u intctl_dbg_out_d; /* 6C */ + volatile csr_intctl_dbg_out_e_u intctl_dbg_out_e; /* 70 */ + volatile csr_intctl_dbg_out_f_u intctl_dbg_out_f; /* 74 */ + volatile csr_intctl_dbg_out_g_u intctl_dbg_out_g; /* 78 */ + volatile csr_intctl_dbg_out_h_u intctl_dbg_out_h; /* 7C */ + volatile csr_intctl_dbg_out_i_u intctl_dbg_out_i; /* 80 */ + volatile csr_intctl_dbg_out_j_u intctl_dbg_out_j; /* 84 */ + volatile csr_intctl_dbg_out_k_u intctl_dbg_out_k; /* 88 */ + volatile csr_intctl_dbg_out_l_u intctl_dbg_out_l; /* 8C */ + volatile csr_intctl_dbg_out_m_u intctl_dbg_out_m; /* 90 */ + volatile csr_intctl_dbg_out_n_u intctl_dbg_out_n; /* 94 */ + volatile csr_intctl_dbg_out_o_u intctl_dbg_out_o; /* 98 */ + volatile csr_intctl_dbg_out_p_u intctl_dbg_out_p; /* 9C */ + volatile csr_intctl_dbg_out_q_u intctl_dbg_out_q; /* A0 */ + volatile csr_intctl_dbg_out_r_u intctl_dbg_out_r; /* A4 */ + volatile csr_intctl_dbg_out_s_u intctl_dbg_out_s; /* A8 */ + volatile csr_intctl_dbg_out_t_u intctl_dbg_out_t; /* AC */ + volatile csr_intctl_dbg_out_u_u intctl_dbg_out_u; /* B0 */ + volatile csr_intctl_dbg_out_v_u intctl_dbg_out_v; /* B4 */ + volatile csr_intctl_dbg_out_w_u intctl_dbg_out_w; /* B8 */ + volatile csr_intctl_dbg_out_x_u intctl_dbg_out_x; /* BC */ + volatile csr_intctl_dbg_out_y_u intctl_dbg_out_y; /* C0 */ + volatile csr_intctl_dbg_out_z_u intctl_dbg_out_z; /* C4 */ + volatile csr_intctl_dbg_fifo_a_u intctl_dbg_fifo_a; /* D0 */ + volatile csr_intctl_dbg_fifo_b_u intctl_dbg_fifo_b; /* D4 */ + volatile csr_intctl_dbg_fifo_c_u intctl_dbg_fifo_c; /* D8 */ + volatile csr_intctl_dbg_fifo_d_u intctl_dbg_fifo_d; /* DC */ + volatile csr_intctl_dbg_fifo_e_u intctl_dbg_fifo_e; /* E0 */ + volatile csr_intctl_dbg_fifo_f_u intctl_dbg_fifo_f; /* E4 */ + volatile csr_intctl_dbg_fifo_g_u intctl_dbg_fifo_g; /* E8 */ + volatile csr_intctl_dbg_fifo_h_u intctl_dbg_fifo_h; /* EC */ + volatile csr_intctl_dbg_fifo_i_u intctl_dbg_fifo_i; /* F0 */ + volatile csr_intctl_dbg_fifo_j_u intctl_dbg_fifo_j; /* F4 */ + volatile csr_intctl_dbg_fifo_k_u intctl_dbg_fifo_k; /* F8 */ + volatile csr_intctl_dbg_fifo_l_u intctl_dbg_fifo_l; /* FC */ + volatile csr_intctl_dbg_fifo_m_u intctl_dbg_fifo_m; /* 100 */ + volatile csr_intctl_dbg_fifo_n_u intctl_dbg_fifo_n; /* 104 */ + volatile csr_intctl_dbg_fifo_o_u intctl_dbg_fifo_o; /* 108 */ + volatile csr_intctl_dbg_fifo_p_u intctl_dbg_fifo_p; /* 10C */ + volatile csr_intctl_dbg_fifo_q_u intctl_dbg_fifo_q; /* 110 */ + volatile csr_intctl_dbg_fifo_r_u intctl_dbg_fifo_r; /* 114 */ + volatile csr_intctl_dbg_drop_msk_u intctl_dbg_drop_msk; /* 120 */ + volatile csr_intctl_msi_bp_timeout_u intctl_msi_bp_timeout; /* 200 */ + volatile csr_intctl_msi_bp_timeout_2nd_01p_u intctl_msi_bp_timeout_2nd_01p; /* 204 */ + volatile csr_intctl_msi_bp_timeout_2nd_23p_u intctl_msi_bp_timeout_2nd_23p; /* 208 */ + volatile csr_intctl_flr_limit_u intctl_flr_limit; /* 220 */ + volatile csr_intctl_reservd_u intctl_reservd; /* 230 */ + volatile csr_intctl_out_a_fatal_msk_u intctl_out_a_fatal_msk; /* 2E0 */ + volatile csr_intctl_out_a_nonfatal_msk_u intctl_out_a_nonfatal_msk; /* 2E4 */ + volatile csr_intctl_dbg_out_a_plus_u intctl_dbg_out_a_plus; /* 2E8 */ + volatile csr_intctl_out_b_fatal_msk_u intctl_out_b_fatal_msk; /* 2F0 */ + volatile csr_intctl_out_b_nonfatal_msk_u intctl_out_b_nonfatal_msk; /* 2F4 */ + volatile csr_intctl_dbg_out_b_plus_u intctl_dbg_out_b_plus; /* 2F8 */ + volatile csr_intctl_ram_init_u intctl_ram_init; /* 310 */ + volatile csr_intctl_ram_status_u intctl_ram_status; /* 314 */ + volatile csr_intctl_ctl_u intctl_ctl; /* 318 */ + volatile csr_intctl_res_u intctl_res; /* 31C */ + volatile csr_intctl_csr_acc_weight_u intctl_csr_acc_weight; /* 320 */ + volatile csr_intctl1_u intctl1; /* 324 */ + volatile csr_intctl2_u intctl2; /* 328 */ + volatile csr_intctl3_u intctl3; /* 32C */ + volatile csr_dfx_intctl_ram_ecc_cerr_u dfx_intctl_ram_ecc_cerr; /* 400 */ + volatile csr_dfx_intctl_ram_ecc_ucerr_u dfx_intctl_ram_ecc_ucerr; /* 404 */ + volatile csr_dfx_intctl_ram_err_addr_u dfx_intctl_ram_err_addr; /* 408 */ + volatile csr_dfx_intctl_ram_multi_err_addr_u dfx_intctl_ram_multi_err_addr; /* 40C */ + volatile csr_intctl_ecc_inj_req_u intctl_ecc_inj_req; /* 410 */ +} S_cpi_intctl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_intctl_csr */ +extern volatile S_cpi_intctl_csr_REGS_TYPE *gopcpi_intctl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetINTCTL_INT_CTL_intctl_int_msk_af_th(unsigned int uintctl_int_msk_af_th); +int iSetINTCTL_INT_CTL_intctl_int_trig_af_th(unsigned int uintctl_int_trig_af_th); +int iSetINTCTL_INT_CTL_dfx_intctl_flr_vct_sel(unsigned int udfx_intctl_flr_vct_sel); +int iSetINTCTL_INT_CTL_intctl_dbg_sel(unsigned int uintctl_dbg_sel); +int iSetINTCTL_INT_CTL_cfg_for_bp_set(unsigned int ucfg_for_bp_set); +int iSetINTCTL_INT_CTL_cfg_msi_data_add(unsigned int ucfg_msi_data_add); +int iSetINTCTL_INT_CTL_cfg_acc_mme_notchk(unsigned int ucfg_acc_mme_notchk); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_dfx_func_idx_bitmap__b(unsigned int udfx_func_idx_bitmap__b); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_dfx_func_idx_bitmap__a(unsigned int udfx_func_idx_bitmap__a); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_dfx_func_idx_bitmap_start(unsigned int udfx_func_idx_bitmap_start); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_WNDW_dfx_func_idx_bitmap__win(unsigned int udfx_func_idx_bitmap__win); +int iSetINTCTL_DBG_FUNC_IDX_AB_dfx_func_idx_b(unsigned int udfx_func_idx_b); +int iSetINTCTL_DBG_FUNC_IDX_AB_dfx_func_idx_a(unsigned int udfx_func_idx_a); +int iSetINTCTL_DBG_FUNC_IDX_CD_dfx_func_idx_d(unsigned int udfx_func_idx_d); +int iSetINTCTL_DBG_FUNC_IDX_CD_dfx_func_idx_c(unsigned int udfx_func_idx_c); +int iSetINTCTL_DBG_FUNC_IDX_EF_dfx_func_idx_f(unsigned int udfx_func_idx_f); +int iSetINTCTL_DBG_FUNC_IDX_EF_dfx_func_idx_e(unsigned int udfx_func_idx_e); +int iSetINTCTL_DBG_FUNC_IDX_GH_dfx_func_idx_h(unsigned int udfx_func_idx_h); +int iSetINTCTL_DBG_FUNC_IDX_GH_dfx_func_idx_g(unsigned int udfx_func_idx_g); +int iSetINTCTL_DBG_FUNC_IDX_AB_CNT_dfx_func_idx_b_cnt(unsigned int udfx_func_idx_b_cnt); +int iSetINTCTL_DBG_FUNC_IDX_AB_CNT_dfx_func_idx_a_cnt(unsigned int udfx_func_idx_a_cnt); +int iSetINTCTL_DBG_FUNC_IDX_CD_CNT_dfx_func_idx_d_cnt(unsigned int udfx_func_idx_d_cnt); +int iSetINTCTL_DBG_FUNC_IDX_CD_CNT_dfx_func_idx_c_cnt(unsigned int udfx_func_idx_c_cnt); +int iSetINTCTL_DBG_FUNC_IDX_EF_CNT_dfx_func_idx_f_cnt(unsigned int udfx_func_idx_f_cnt); +int iSetINTCTL_DBG_FUNC_IDX_EF_CNT_dfx_func_idx_e_cnt(unsigned int udfx_func_idx_e_cnt); +int iSetINTCTL_DBG_FUNC_IDX_GH_CNT_dfx_func_idx_h_cnt(unsigned int udfx_func_idx_h_cnt); +int iSetINTCTL_DBG_FUNC_IDX_GH_CNT_dfx_func_idx_g_cnt(unsigned int udfx_func_idx_g_cnt); +int iSetINTCTL_DBG_IPUSH_CNT_dfx_intctl_ipush_cpl_cnt(unsigned int udfx_intctl_ipush_cpl_cnt); +int iSetINTCTL_DBG_IPUSH_CNT_dfx_intctl_ipush_req_cnt(unsigned int udfx_intctl_ipush_req_cnt); +int iSetINTCTL_DBG_CFG_CNT_dfx_cfg_ack_rw_cnt(unsigned int udfx_cfg_ack_rw_cnt); +int iSetINTCTL_DBG_CFG_CNT_dfx_cfg_req_rw_cnt(unsigned int udfx_cfg_req_rw_cnt); +int iSetINTCTL_DBG_MSK_TRIG_CNT_dfx_fun_msk_trig_cnt(unsigned int udfx_fun_msk_trig_cnt); +int iSetINTCTL_DBG_MSK_TRIG_CNT_dfx_per_msk_trig_cnt(unsigned int udfx_per_msk_trig_cnt); +int iSetINTCTL_DBG_COAL_CNT0_dfx_coal_lli_in_cnt(unsigned int udfx_coal_lli_in_cnt); +int iSetINTCTL_DBG_COAL_CNT0_dfx_coal_num_int_cnt(unsigned int udfx_coal_num_int_cnt); +int iSetINTCTL_DBG_COAL_CNT1_dfx_coal_time_int_cnt(unsigned int udfx_coal_time_int_cnt); +int iSetINTCTL_DBG_COAL_CNT1_dfx_coal_normal_in_cnt(unsigned int udfx_coal_normal_in_cnt); +int iSetINTCTL_DBG_MSI_CNT_dfx_msi_int_cnt(unsigned int udfx_msi_int_cnt); +int iSetINTCTL_DBG_MSI_CNT_dfx_coal_num_drop_cnt(unsigned int udfx_coal_num_drop_cnt); +int iSetINTCTL_DBG_MSIX_CNT_dfx_pba_int_cnt(unsigned int udfx_pba_int_cnt); +int iSetINTCTL_DBG_MSIX_CNT_dfx_msix_int_cnt(unsigned int udfx_msix_int_cnt); +int iSetINTCTL_DBG_VCT_CNT_dfx_trig_vct_cnt(unsigned int udfx_trig_vct_cnt); +int iSetINTCTL_DBG_VCT_CNT_dfx_normal_vct_cnt(unsigned int udfx_normal_vct_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT0_dfx_intx_ab_cnt(unsigned int udfx_intx_ab_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT0_dfx_intx_aa_cnt(unsigned int udfx_intx_aa_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT1_dfx_intx_ad_cnt(unsigned int udfx_intx_ad_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT1_dfx_intx_ac_cnt(unsigned int udfx_intx_ac_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT0_dfx_intx_db_cnt(unsigned int udfx_intx_db_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT0_dfx_intx_da_cnt(unsigned int udfx_intx_da_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT1_dfx_intx_dd_cnt(unsigned int udfx_intx_dd_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT1_dfx_intx_dc_cnt(unsigned int udfx_intx_dc_cnt); +int iSetINTCTL_DBG_OUT_A_dfx_intctl_out_a(unsigned int udfx_intctl_out_a); +int iSetINTCTL_DBG_OUT_B_dfx_intctl_out_b(unsigned int udfx_intctl_out_b); +int iSetINTCTL_DBG_OUT_C_dfx_intctl_out_c(unsigned int udfx_intctl_out_c); +int iSetINTCTL_DBG_OUT_D_dfx_intctl_out_d(unsigned int udfx_intctl_out_d); +int iSetINTCTL_DBG_OUT_E_dfx_intctl_out_e(unsigned int udfx_intctl_out_e); +int iSetINTCTL_DBG_OUT_F_dfx_intctl_out_f(unsigned int udfx_intctl_out_f); +int iSetINTCTL_DBG_OUT_G_dfx_intctl_out_g(unsigned int udfx_intctl_out_g); +int iSetINTCTL_DBG_OUT_H_dfx_intctl_out_h(unsigned int udfx_intctl_out_h); +int iSetINTCTL_DBG_OUT_I_dfx_intctl_out_i(unsigned int udfx_intctl_out_i); +int iSetINTCTL_DBG_OUT_J_dfx_intctl_out_j(unsigned int udfx_intctl_out_j); +int iSetINTCTL_DBG_OUT_K_dfx_intctl_out_k(unsigned int udfx_intctl_out_k); +int iSetINTCTL_DBG_OUT_L_dfx_intctl_out_l(unsigned int udfx_intctl_out_l); +int iSetINTCTL_DBG_OUT_M_dfx_intctl_out_m(unsigned int udfx_intctl_out_m); +int iSetINTCTL_DBG_OUT_N_dfx_intctl_out_n(unsigned int udfx_intctl_out_n); +int iSetINTCTL_DBG_OUT_O_dfx_intctl_out_o(unsigned int udfx_intctl_out_o); +int iSetINTCTL_DBG_OUT_P_dfx_intctl_out_p(unsigned int udfx_intctl_out_p); +int iSetINTCTL_DBG_OUT_Q_dfx_intctl_out_q(unsigned int udfx_intctl_out_q); +int iSetINTCTL_DBG_OUT_R_dfx_intctl_out_r(unsigned int udfx_intctl_out_r); +int iSetINTCTL_DBG_OUT_S_dfx_intctl_out_s(unsigned int udfx_intctl_out_s); +int iSetINTCTL_DBG_OUT_T_dfx_intctl_out_t(unsigned int udfx_intctl_out_t); +int iSetINTCTL_DBG_OUT_U_dfx_intctl_out_u(unsigned int udfx_intctl_out_u); +int iSetINTCTL_DBG_OUT_V_dfx_intctl_out_v(unsigned int udfx_intctl_out_v); +int iSetINTCTL_DBG_OUT_W_dfx_intctl_out_w(unsigned int udfx_intctl_out_w); +int iSetINTCTL_DBG_OUT_X_dfx_intctl_out_x(unsigned int udfx_intctl_out_x); +int iSetINTCTL_DBG_OUT_Y_dfx_intctl_out_y(unsigned int udfx_intctl_out_y); +int iSetINTCTL_DBG_OUT_Z_dfx_intctl_out_z(unsigned int udfx_intctl_out_z); +int iSetINTCTL_DBG_FIFO_A_dfx_intctl_fifo_a_ro(unsigned int udfx_intctl_fifo_a_ro); +int iSetINTCTL_DBG_FIFO_B_dfx_intctl_fifo_b_ro(unsigned int udfx_intctl_fifo_b_ro); +int iSetINTCTL_DBG_FIFO_C_dfx_intctl_fifo_c_ro(unsigned int udfx_intctl_fifo_c_ro); +int iSetINTCTL_DBG_FIFO_D_dfx_intctl_fifo_d_ro(unsigned int udfx_intctl_fifo_d_ro); +int iSetINTCTL_DBG_FIFO_E_dfx_intctl_fifo_e_ro(unsigned int udfx_intctl_fifo_e_ro); +int iSetINTCTL_DBG_FIFO_F_dfx_intctl_fifo_f_ro(unsigned int udfx_intctl_fifo_f_ro); +int iSetINTCTL_DBG_FIFO_G_dfx_intctl_fifo_g_ro(unsigned int udfx_intctl_fifo_g_ro); +int iSetINTCTL_DBG_FIFO_H_dfx_intctl_fifo_h_ro(unsigned int udfx_intctl_fifo_h_ro); +int iSetINTCTL_DBG_FIFO_I_dfx_intctl_fifo_i_ro(unsigned int udfx_intctl_fifo_i_ro); +int iSetINTCTL_DBG_FIFO_J_dfx_intctl_fifo_j_ro(unsigned int udfx_intctl_fifo_j_ro); +int iSetINTCTL_DBG_FIFO_K_dfx_intctl_fifo_k_ro(unsigned int udfx_intctl_fifo_k_ro); +int iSetINTCTL_DBG_FIFO_L_dfx_intctl_fifo_l_ro(unsigned int udfx_intctl_fifo_l_ro); +int iSetINTCTL_DBG_FIFO_M_dfx_intctl_fifo_m_ro(unsigned int udfx_intctl_fifo_m_ro); +int iSetINTCTL_DBG_FIFO_N_dfx_intctl_fifo_n_ro(unsigned int udfx_intctl_fifo_n_ro); +int iSetINTCTL_DBG_FIFO_O_dfx_intctl_fifo_o_ro(unsigned int udfx_intctl_fifo_o_ro); +int iSetINTCTL_DBG_FIFO_P_dfx_intctl_fifo_p_ro(unsigned int udfx_intctl_fifo_p_ro); +int iSetINTCTL_DBG_FIFO_Q_dfx_intctl_fifo_q_ro(unsigned int udfx_intctl_fifo_q_ro); +int iSetINTCTL_DBG_FIFO_R_dfx_intctl_fifo_r_ro(unsigned int udfx_intctl_fifo_r_ro); +int iSetINTCTL_DBG_DROP_MSK_dfx_per_msk_drop_cnt(unsigned int udfx_per_msk_drop_cnt); +int iSetINTCTL_DBG_DROP_MSK_dfx_fm_msk_drop_cnt(unsigned int udfx_fm_msk_drop_cnt); +int iSetINTCTL_MSI_BP_TIMEOUT_dfx_intctl_msi_bp_timeout_1st(unsigned int udfx_intctl_msi_bp_timeout_1st); +int iSetINTCTL_MSI_BP_TIMEOUT_dfx_intctl_msi_bp_timeout4_2nd(unsigned int udfx_intctl_msi_bp_timeout4_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_01P_dfx_intctl_msi_bp_timeout1_2nd(unsigned int udfx_intctl_msi_bp_timeout1_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_01P_dfx_intctl_msi_bp_timeout0_2nd(unsigned int udfx_intctl_msi_bp_timeout0_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_23P_dfx_intctl_msi_bp_timeout3_2nd(unsigned int udfx_intctl_msi_bp_timeout3_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_23P_dfx_intctl_msi_bp_timeout2_2nd(unsigned int udfx_intctl_msi_bp_timeout2_2nd); +int iSetINTCTL_FLR_LIMIT_glb_int_flr_limit(unsigned int uglb_int_flr_limit); +int iSetINTCTL_RESERVD_intctl_reserved(unsigned int uintctl_reserved); +int iSetINTCTL_OUT_A_FATAL_MSK_dfx_intctl_out_a_fatal_msk(unsigned int udfx_intctl_out_a_fatal_msk); +int iSetINTCTL_OUT_A_NONFATAL_MSK_dfx_intctl_out_a_nonfatal_msk(unsigned int udfx_intctl_out_a_nonfatal_msk); +int iSetINTCTL_DBG_OUT_A_PLUS_dfx_intctl_out_a_pls(unsigned int udfx_intctl_out_a_pls); +int iSetINTCTL_OUT_B_FATAL_MSK_dfx_intctl_out_b_fatal_msk(unsigned int udfx_intctl_out_b_fatal_msk); +int iSetINTCTL_OUT_B_NONFATAL_MSK_dfx_intctl_out_b_nonfatal_msk(unsigned int udfx_intctl_out_b_nonfatal_msk); +int iSetINTCTL_DBG_OUT_B_PLUS_dfx_intctl_out_b_pls(unsigned int udfx_intctl_out_b_pls); +int iSetINTCTL_RAM_INIT_pcnt_ram_init_start(unsigned int upcnt_ram_init_start); +int iSetINTCTL_RAM_INIT_attr_ram_init_start(unsigned int uattr_ram_init_start); +int iSetINTCTL_RAM_INIT_cap_ram_ini_start(unsigned int ucap_ram_ini_start); +int iSetINTCTL_RAM_INIT_pba_ram_init_start(unsigned int upba_ram_init_start); +int iSetINTCTL_RAM_INIT_msk_ram_init_start(unsigned int umsk_ram_init_start); +int iSetINTCTL_RAM_INIT_tb_ram_init_start(unsigned int utb_ram_init_start); +int iSetINTCTL_RAM_INIT_int_num_init_start(unsigned int uint_num_init_start); +int iSetINTCTL_RAM_INIT_msi_ram_ini_start(unsigned int umsi_ram_ini_start); +int iSetINTCTL_RAM_STATUS_pcnt_ram_init_done(unsigned int upcnt_ram_init_done); +int iSetINTCTL_RAM_STATUS_attr_ram_init_done(unsigned int uattr_ram_init_done); +int iSetINTCTL_RAM_STATUS_cap_ram_ini_done(unsigned int ucap_ram_ini_done); +int iSetINTCTL_RAM_STATUS_pba_ram_init_done(unsigned int upba_ram_init_done); +int iSetINTCTL_RAM_STATUS_msk_ram_init_done(unsigned int umsk_ram_init_done); +int iSetINTCTL_RAM_STATUS_tb_ram_init_done(unsigned int utb_ram_init_done); +int iSetINTCTL_RAM_STATUS_int_num_init_done(unsigned int uint_num_init_done); +int iSetINTCTL_RAM_STATUS_msi_ram_ini_done(unsigned int umsi_ram_ini_done); +int iSetINTCTL_CTL_ipush_intctl_allow_vf_cfg(unsigned int uipush_intctl_allow_vf_cfg); +int iSetINTCTL_CTL_cfg_msk_without_trig(unsigned int ucfg_msk_without_trig); +int iSetINTCTL_CTL_int_flr_no_clr_tab(unsigned int uint_flr_no_clr_tab); +int iSetINTCTL_CTL_intctl_coal_dbg_sel(unsigned int uintctl_coal_dbg_sel); +int iSetINTCTL_CTL_cfg_msi_data_4byte_en(unsigned int ucfg_msi_data_4byte_en); +int iSetINTCTL_CTL_cfg_msi_tlp_soro_nosnoop(unsigned int ucfg_msi_tlp_soro_nosnoop); +int iSetINTCTL_RES_int_per_pf(unsigned int uint_per_pf); +int iSetINTCTL_RES_int_per_vf(unsigned int uint_per_vf); +int iSetINTCTL_CSR_ACC_WEIGHT_intctl_csr_acc_weight_port(unsigned int uintctl_csr_acc_weight_port); +int iSetINTCTL_CSR_ACC_WEIGHT_int_num_acc_weight(unsigned int uint_num_acc_weight); +int iSetINTCTL1_msi_nxt_ptr(unsigned int umsi_nxt_ptr); +int iSetINTCTL1_msix_nxt_ptr_pf(unsigned int umsix_nxt_ptr_pf); +int iSetINTCTL1_msix_nxt_ptr_vf(unsigned int umsix_nxt_ptr_vf); +int iSetINTCTL1_ipush_intctl_allow_pf_cfg(unsigned int uipush_intctl_allow_pf_cfg); +int iSetINTCTL2_msien_crdt_gap(unsigned int umsien_crdt_gap); +int iSetINTCTL2_msien_snap_2_virtio_en(unsigned int umsien_snap_2_virtio_en); +int iSetINTCTL2_cfg_int_msk_aful_th(unsigned int ucfg_int_msk_aful_th); +int iSetINTCTL2_cfg_intctl_csr_in_th(unsigned int ucfg_intctl_csr_in_th); +int iSetINTCTL3_msix_nxt_ptr_vf_with_vio(unsigned int umsix_nxt_ptr_vf_with_vio); +int iSetINTCTL3_msix_at_cfg(unsigned int umsix_at_cfg); +int iSetDFX_INTCTL_RAM_ECC_CERR_dfx_intctl_ram_ecc_cerr(unsigned int udfx_intctl_ram_ecc_cerr); +int iSetDFX_INTCTL_RAM_ECC_UCERR_dfx_intctl_ram_ecc_ucerr(unsigned int udfx_intctl_ram_ecc_ucerr); +int iSetDFX_INTCTL_RAM_ERR_ADDR_dfx_intctl_ram_err_addr(unsigned int udfx_intctl_ram_err_addr); +int iSetDFX_INTCTL_RAM_MULTI_ERR_ADDR_dfx_intctl_ram_multi_err_addr(unsigned int udfx_intctl_ram_multi_err_addr); +int iSetINTCTL_ECC_INJ_REQ_intctl_ecc_inj_req(unsigned int uintctl_ecc_inj_req); + +/* Define the union csr_octl_tbl_indir_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_tbl_indir_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 octl_tbl_indir_tab : 4; /* [27:24] */ + u32 octl_tbl_indir_stat : 2; /* [29:28] */ + u32 octl_tbl_indir_mode : 1; /* [30] */ + u32 octl_tbl_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_tbl_indir_ctrl0_u; + +/* Define the union csr_octl_tbl_indir_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_tbl_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_tbl_indir_ctrl1_u; + +/* Define the union csr_octl_tbl_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_tbl_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_tbl_indir_data_u; + +/* Define the union csr_octl_ram_init_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ram_ini_req : 13; /* [12:0] */ + u32 rsv_1 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_init_req_u; + +/* Define the union csr_octl_ram_init_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ram_ini_sts : 13; /* [12:0] */ + u32 rsv_2 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_init_sts_u; + +/* Define the union csr_pre_sub_dat_crd_cpb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_presub_data_crdt : 8; /* [7:0] */ + u32 rsv_3 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pre_sub_dat_crd_cpb_u; + +/* Define the union csr_l2nic_ci_wr_chl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2nic_ci_wr_chl_port0 : 5; /* [4:0] */ + u32 l2nic_ci_wr_chl_port1 : 5; /* [9:5] */ + u32 l2nic_ci_wr_chl_port2 : 5; /* [14:10] */ + u32 l2nic_ci_wr_chl_port3 : 5; /* [19:15] */ + u32 l2nic_ci_wr_chl_port4 : 5; /* [24:20] */ + u32 rsv_4 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_l2nic_ci_wr_chl_cfg_u; + +/* Define the union csr_cqe_wr_chl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqe_wr_chl_port0 : 5; /* [4:0] */ + u32 cqe_wr_chl_port1 : 5; /* [9:5] */ + u32 cqe_wr_chl_port2 : 5; /* [14:10] */ + u32 cqe_wr_chl_port3 : 5; /* [19:15] */ + u32 cqe_wr_chl_port4 : 5; /* [24:20] */ + u32 rsv_5 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cqe_wr_chl_cfg_u; + +/* Define the union csr_pcie_port_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_cfg : 5; /* [4:0] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_port_cfg_u; + +/* Define the union csr_dma_pe_yyy_fifo_depth_port012_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_dma_pe_yyy_fifo_depth_cfg : 10; /* [9:0] */ + u32 port1_dma_pe_yyy_fifo_depth_cfg : 10; /* [19:10] */ + u32 port2_dma_pe_yyy_fifo_depth_cfg : 10; /* [29:20] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pe_yyy_fifo_depth_port012_u; + +/* Define the union csr_dma_pe_yyy_fifo_depth_port34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port3_dma_pe_yyy_fifo_depth_cfg : 10; /* [9:0] */ + u32 port4_dma_pe_yyy_fifo_depth_cfg : 10; /* [19:10] */ + u32 rsv_8 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pe_yyy_fifo_depth_port34_u; + +/* Define the union csr_cpi_prealloc_cpb_buf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cell_prealloc_cfg : 10; /* [9:0] */ + u32 rsv_9 : 2; /* [11:10] */ + u32 cpb_cell_prealloc_adj : 4; /* [15:12] */ + u32 cpb_cell_prealloc_thd : 10; /* [25:16] */ + u32 rsv_10 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_prealloc_cpb_buf_u; + +/* Define the union csr_cpi_sm_chl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_sm_chl_cfg0 : 5; /* [4:0] */ + u32 rsv_11 : 3; /* [7:5] */ + u32 cpi_sm_chl_cfg1 : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 cpi_sm_chl_cfg2 : 5; /* [20:16] */ + u32 rsv_13 : 3; /* [23:21] */ + u32 cpi_sm_chl_cfg3 : 5; /* [28:24] */ + u32 rsv_14 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_sm_chl_cfg_u; + +/* Define the union csr_octl_cut_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_pe_wdat_cut_through : 4; /* [3:0] */ + u32 cpath_wdat_cut_through : 4; /* [7:4] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cut_thr_cfg_u; + +/* Define the union csr_octl_in_cmd_chnl_src_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mem_err_addr_sel : 6; /* [5:0] */ + u32 perx_cmd_cnt_chnl_sel : 5; /* [10:6] */ + u32 perx_cmd_cnt_out_grain_cfg : 1; /* [11] */ + u32 perx_cmd_cnt_in_or_out_cfg : 1; /* [12] */ + u32 l2nic_cmd_cnt_chnl_sel : 6; /* [18:13] */ + u32 l2nic_cmd_cnt_out_grain_cfg : 1; /* [19] */ + u32 l2nic_cmd_cnt_in_or_out_cfg : 1; /* [20] */ + u32 sm_cp_cmd_src_sel : 5; /* [25:21] */ + u32 cpath_cmd_cnt_in_or_out_cfg : 1; /* [26] */ + u32 sm_cp_proc_cmd_src_sel : 3; /* [29:27] */ + u32 rsv_16 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_cmd_chnl_src_sel_u; + +/* Define the union csr_octl_err_detect_reg_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_octl_fatal_err : 1; /* [0] */ + u32 cpi_octl_nonfatal_err : 1; /* [1] */ + u32 octl_mem_ecc_merr_all : 1; /* [2] */ + u32 octl_mem_ecc_err_all : 1; /* [3] */ + u32 proc_cpath_data_err : 1; /* [4] */ + u32 sm_cpath_data_err : 1; /* [5] */ + u32 sm_l2nic_data_err : 1; /* [6] */ + u32 rde_octl_data_err : 1; /* [7] */ + u32 octl_mul_dif_cfg_chnl_err : 1; /* [8] */ + u32 octl_mul_dif_cfg_en_err : 1; /* [9] */ + u32 octl_ec_chnl_cfg_chnl_err_1 : 1; /* [10] */ + u32 octl_ec_chnl_cfg_chnl_err_0 : 1; /* [11] */ + u32 octl_ec_chnl_cfg_en_err : 1; /* [12] */ + u32 octl_cpb_num_deficit_err : 1; /* [13] */ + u32 octl_sge0_len_err_less : 1; /* [14] */ + u32 octl_sge0_len_err_more : 1; /* [15] */ + u32 octl_sge0_len_err : 1; /* [16] */ + u32 perx_unknown_cmd_err : 1; /* [17] */ + u32 perxin_unknown_cmd_err : 1; /* [18] */ + u32 cpi_dpath_rel_non_vld_err_all : 1; /* [19] */ + u32 cpi_dpath_rel_loss_eop_err_all : 1; /* [20] */ + u32 cpi_dpath_rel_loss_sop_err_all : 1; /* [21] */ + u32 cpi_dpath_o_non_vld_err_all : 1; /* [22] */ + u32 cpi_dpath_o_loss_eop_err_all : 1; /* [23] */ + u32 cpi_dpath_o_loss_sop_err_all : 1; /* [24] */ + u32 octl_fifo_underflow_all : 1; /* [25] */ + u32 octl_fifo_overflow_all : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_reg_a_u; + +/* Define the union csr_octl_err_detect_reg_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 proc_cpath_non_vld_err_all : 1; /* [0] */ + u32 proc_cpath_loss_eop_err_all : 1; /* [1] */ + u32 proc_cpath_loss_sop_err_all : 1; /* [2] */ + u32 sm_cpath_non_vld_err_all : 1; /* [3] */ + u32 sm_cpath_loss_eop_err_all : 1; /* [4] */ + u32 sm_cpath_loss_sop_err_all : 1; /* [5] */ + u32 sm_l2nic_non_vld_err_all : 1; /* [6] */ + u32 sm_l2nic_loss_eop_err_all : 1; /* [7] */ + u32 sm_l2nic_loss_sop_err_all : 1; /* [8] */ + u32 octl_sm_parser_data_err : 1; /* [9] */ + u32 octl_perx_hd_dif_err : 1; /* [10] */ + u32 octl_perx_hd_wdat_err : 1; /* [11] */ + u32 octl_dpath_o_sop_err : 1; /* [12] */ + u32 rsv_18 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_reg_b_u; + +/* Define the union csr_octl_err_detect_ro_reg_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cpi_bp_all : 1; /* [0] */ + u32 osch_octl_cpath_bp_all : 1; /* [1] */ + u32 osch_octl_dpath_sm_bp_all : 1; /* [2] */ + u32 osch_octl_dpath_pe_bp_all : 1; /* [3] */ + u32 prm_cpi_src_bp_all : 1; /* [4] */ + u32 prm_cpi_bp_all : 1; /* [5] */ + u32 octl_all_fifo_no_empty : 1; /* [6] */ + u32 octl_cpath_loop_swallow_packet : 1; /* [7] */ + u32 octl_l2nic_loop_swallow_packet : 1; /* [8] */ + u32 octl_pe_loop_swallow_packet : 1; /* [9] */ + u32 dma_pre_alc_num_cur : 10; /* [19:10] */ + u32 glb_cpb_cell_num_cnt : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_a_u; + +/* Define the union csr_octl_err_detect_ro_reg_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cp_proc_osch_host_crd_cnt_0 : 8; /* [7:0] */ + u32 cp_proc_icpl_sm_crd_cnt : 9; /* [16:8] */ + u32 cp_proc_icpl_vio_crd_cnt : 10; /* [26:17] */ + u32 rsv_19 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_b_u; + +/* Define the union csr_octl_err_detect_ro_reg_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cp_proc_osch_host_crd_cnt_4 : 8; /* [7:0] */ + u32 cp_proc_osch_host_crd_cnt_3 : 8; /* [15:8] */ + u32 cp_proc_osch_host_crd_cnt_2 : 8; /* [23:16] */ + u32 cp_proc_osch_host_crd_cnt_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_c_u; + +/* Define the union csr_octl_err_detect_ro_reg_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mem_err_addr : 15; /* [14:0] */ + u32 rsv_20 : 1; /* [15] */ + u32 ci_cqe_tbl_indir_op_done : 1; /* [16] */ + u32 rsv_21 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_d_u; + +/* Define the union csr_octl_cmd_cnt_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_a_u; + +/* Define the union csr_octl_cmd_cnt_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_b_u; + +/* Define the union csr_octl_cmd_cnt_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_c_u; + +/* Define the union csr_octl_cmd_cnt_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_d_u; + +/* Define the union csr_octl_cmd_cnt_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_in_chnl_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_e_u; + +/* Define the union csr_octl_cmd_cnt_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_in_chnl_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_f_u; + +/* Define the union csr_octl_cmd_cnt_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_chnl_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_g_u; + +/* Define the union csr_octl_cmd_cnt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_chnl_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_h_u; + +/* Define the union csr_octl_cmd_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_i_u; + +/* Define the union csr_octl_cmd_cnt_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_rd_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_j_u; + +/* Define the union csr_octl_cmd_cnt_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_atomic_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_k_u; + +/* Define the union csr_octl_cmd_cnt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_non_l2nic_il_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_l_u; + +/* Define the union csr_octl_cmd_cnt_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_non_l2nic_il_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_m_u; + +/* Define the union csr_octl_cmd_cnt_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_n_u; + +/* Define the union csr_octl_cmd_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_wr_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_o_u; + +/* Define the union csr_octl_cmd_cnt_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cqe_only_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_p_u; + +/* Define the union csr_octl_cmd_cnt_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ceqe_only : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_q_u; + +/* Define the union csr_octl_cmd_cnt_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_db_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_r_u; + +/* Define the union csr_octl_cmd_cnt_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mul_dif_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_s_u; + +/* Define the union csr_octl_cmd_cnt_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_rd_1st_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_t_u; + +/* Define the union csr_octl_cmd_cnt_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_rd_2nd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_u_u; + +/* Define the union csr_octl_cmd_cnt_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_cqe_rd_1st_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_v_u; + +/* Define the union csr_octl_cmd_cnt_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_cqe_rd_2nd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_w_u; + +/* Define the union csr_octl_cmd_cnt_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_rd_by_aad_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_x_u; + +/* Define the union csr_octl_cmd_cnt_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_y_u; + +/* Define the union csr_octl_cmd_cnt_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ci_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_z_u; + +/* Define the union csr_octl_cmd_cnt_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_cqe_only_ceqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aa_u; + +/* Define the union csr_octl_cmd_cnt_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_0_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ab_u; + +/* Define the union csr_octl_cmd_cnt_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_1_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ac_u; + +/* Define the union csr_octl_cmd_cnt_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_2_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ad_u; + +/* Define the union csr_octl_cmd_cnt_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_3_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ae_u; + +/* Define the union csr_octl_cmd_cnt_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_4_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_af_u; + +/* Define the union csr_octl_cmd_cnt_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ag_u; + +/* Define the union csr_octl_cmd_cnt_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ah_u; + +/* Define the union csr_octl_cmd_cnt_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ai_u; + +/* Define the union csr_octl_cmd_cnt_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aj_u; + +/* Define the union csr_octl_cmd_cnt_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_chnl_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ak_u; + +/* Define the union csr_octl_cmd_cnt_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_chnl_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_al_u; + +/* Define the union csr_octl_cmd_cnt_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_read_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_am_u; + +/* Define the union csr_octl_cmd_cnt_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_ceqe_only_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_an_u; + +/* Define the union csr_octl_cmd_cnt_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_il_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ao_u; + +/* Define the union csr_octl_cmd_cnt_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_read_ci_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ap_u; + +/* Define the union csr_octl_cmd_cnt_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_il_ci_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aq_u; + +/* Define the union csr_octl_cmd_cnt_ar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ar_u; + +/* Define the union csr_octl_cmd_cnt_as_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_as_u; + +/* Define the union csr_octl_cmd_cnt_at_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_at_u; + +/* Define the union csr_octl_cmd_cnt_au_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_au_u; + +/* Define the union csr_octl_cmd_cnt_av_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_in_src_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_av_u; + +/* Define the union csr_octl_cmd_cnt_aw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_in_src_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aw_u; + +/* Define the union csr_octl_cmd_cnt_ax_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_src_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ax_u; + +/* Define the union csr_octl_cmd_cnt_ay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_src_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ay_u; + +/* Define the union csr_octl_cmd_cnt_az_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_az_u; + +/* Define the union csr_octl_cmd_cnt_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ba_u; + +/* Define the union csr_octl_cmd_cnt_bb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_osch_cp_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bb_u; + +/* Define the union csr_octl_cmd_cnt_bc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_osch_cp_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bc_u; + +/* Define the union csr_octl_cmd_port_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_rd_cqe_inc : 16; /* [15:0] */ + u32 port_octl_rd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_aa_u; + +/* Define the union csr_octl_cmd_port_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_non_l2nic_il_inc : 16; /* [15:0] */ + u32 port_octl_atomic_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ab_u; + +/* Define the union csr_octl_cmd_port_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_wr_inc : 16; /* [15:0] */ + u32 port_octl_non_l2nic_il_cqe_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ac_u; + +/* Define the union csr_octl_cmd_port_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_cqe_only_inc : 16; /* [15:0] */ + u32 port_octl_wr_cqe_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ad_u; + +/* Define the union csr_octl_cmd_port_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_db_wr_inc : 16; /* [15:0] */ + u32 port_octl_ceqe_only_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ae_u; + +/* Define the union csr_octl_cmd_port_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_ec_rd_1st_inc : 16; /* [15:0] */ + u32 port_octl_mul_dif_rd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_af_u; + +/* Define the union csr_octl_cmd_port_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_ec_cqe_rd_1st_inc : 16; /* [15:0] */ + u32 port_octl_ec_rd_2nd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ag_u; + +/* Define the union csr_octl_cmd_port_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_rd_by_aad_inc : 16; /* [15:0] */ + u32 port_octl_ec_cqe_rd_2nd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ah_u; + +/* Define the union csr_octl_cmd_port_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_icpl_cqe_only_ceqe_inc : 16; /* [15:0] */ + u32 port_icpl_cqe_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ai_u; + +/* Define the union csr_octl_cmd_port_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_pe_cmd_port_inc : 16; /* [15:0] */ + u32 port_icpl_ci_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_aj_u; + +/* Define the union csr_octl_cmd_port_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sm_l2nic_ceqe_only_inc : 16; /* [15:0] */ + u32 port_sm_l2nic_read_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ak_u; + +/* Define the union csr_octl_cmd_port_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sm_l2nic_read_ci_inc : 16; /* [15:0] */ + u32 port_sm_l2nic_il_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_al_u; + +/* Define the union csr_octl_cmd_port_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_port_cp_inc : 16; /* [15:0] */ + u32 port_sm_l2nic_il_ci_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_am_u; + +/* Define the union csr_octl_cmd_port_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_port_cp_wr_inc : 16; /* [15:0] */ + u32 octl_port_cp_rd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_an_u; + +/* Define the union csr_octl_cmd_cnt_bd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_cpath_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bd_u; + +/* Define the union csr_octl_cmd_cnt_be_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_l2nic_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_be_u; + +/* Define the union csr_octl_cmd_cnt_bf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_ceqe_only_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bf_u; + +/* Define the union csr_octl_cmd_cnt_bg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 proc_cpath_eop_inc : 16; /* [15:0] */ + u32 proc_cpath_sop_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bg_u; + +/* Define the union csr_octl_cmd_cnt_bh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_drop_zero_sge_len_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bh_u; + +/* Define the union csr_octl_dpath_o_err_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_chnl_sop_err : 20; /* [19:0] */ + u32 rsv_22 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_dpath_o_err_dfx_u; + +/* Define the union csr_octl_sub_err_cfg_bk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_18 : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bk_u; + +/* Define the union csr_octl_sub_err_cfg_bl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_18 : 20; /* [19:0] */ + u32 rsv_24 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bl_u; + +/* Define the union csr_octl_sub_err_cfg_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_0 : 22; /* [21:0] */ + u32 rsv_25 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aa_u; + +/* Define the union csr_octl_sub_err_cfg_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_0 : 22; /* [21:0] */ + u32 rsv_26 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ab_u; + +/* Define the union csr_octl_sub_err_cfg_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_1 : 22; /* [21:0] */ + u32 rsv_27 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ac_u; + +/* Define the union csr_octl_sub_err_cfg_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_1 : 22; /* [21:0] */ + u32 rsv_28 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ad_u; + +/* Define the union csr_octl_sub_err_cfg_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_2 : 20; /* [19:0] */ + u32 rsv_29 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ae_u; + +/* Define the union csr_octl_sub_err_cfg_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_2 : 20; /* [19:0] */ + u32 rsv_30 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_af_u; + +/* Define the union csr_octl_sub_err_cfg_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_3 : 20; /* [19:0] */ + u32 rsv_31 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ag_u; + +/* Define the union csr_octl_sub_err_cfg_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_3 : 20; /* [19:0] */ + u32 rsv_32 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ah_u; + +/* Define the union csr_octl_sub_err_cfg_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_4 : 20; /* [19:0] */ + u32 rsv_33 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ai_u; + +/* Define the union csr_octl_sub_err_cfg_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_4 : 20; /* [19:0] */ + u32 rsv_34 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aj_u; + +/* Define the union csr_octl_sub_err_cfg_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_5 : 20; /* [19:0] */ + u32 rsv_35 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ak_u; + +/* Define the union csr_octl_sub_err_cfg_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_5 : 20; /* [19:0] */ + u32 rsv_36 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_al_u; + +/* Define the union csr_octl_sub_err_cfg_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_6 : 20; /* [19:0] */ + u32 rsv_37 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_am_u; + +/* Define the union csr_octl_sub_err_cfg_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_6 : 20; /* [19:0] */ + u32 rsv_38 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_an_u; + +/* Define the union csr_octl_sub_err_cfg_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_7 : 20; /* [19:0] */ + u32 rsv_39 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ao_u; + +/* Define the union csr_octl_sub_err_cfg_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_7 : 20; /* [19:0] */ + u32 rsv_40 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ap_u; + +/* Define the union csr_octl_sub_err_cfg_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aq_u; + +/* Define the union csr_octl_sub_err_cfg_ar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ar_u; + +/* Define the union csr_octl_sub_err_cfg_as_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_9 : 24; /* [23:0] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_as_u; + +/* Define the union csr_octl_sub_err_cfg_at_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_9 : 24; /* [23:0] */ + u32 rsv_42 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_at_u; + +/* Define the union csr_octl_sub_err_cfg_au_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_au_u; + +/* Define the union csr_octl_sub_err_cfg_av_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_av_u; + +/* Define the union csr_octl_sub_err_cfg_aw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_11 : 24; /* [23:0] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aw_u; + +/* Define the union csr_octl_sub_err_cfg_ax_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_11 : 24; /* [23:0] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ax_u; + +/* Define the union csr_octl_sub_err_cfg_ay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ay_u; + +/* Define the union csr_octl_sub_err_cfg_az_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_az_u; + +/* Define the union csr_octl_sub_err_cfg_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_13 : 24; /* [23:0] */ + u32 rsv_45 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ba_u; + +/* Define the union csr_octl_sub_err_cfg_bb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_13 : 24; /* [23:0] */ + u32 rsv_46 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bb_u; + +/* Define the union csr_octl_sub_err_cfg_bc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bc_u; + +/* Define the union csr_octl_sub_err_cfg_bd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bd_u; + +/* Define the union csr_octl_sub_err_cfg_be_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_be_u; + +/* Define the union csr_octl_sub_err_cfg_bf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bf_u; + +/* Define the union csr_octl_sub_err_cfg_bg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bg_u; + +/* Define the union csr_octl_sub_err_cfg_bh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bh_u; + +/* Define the union csr_octl_sub_err_cfg_bi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_17 : 18; /* [17:0] */ + u32 rsv_47 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bi_u; + +/* Define the union csr_octl_sub_err_cfg_bj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_17 : 18; /* [17:0] */ + u32 rsv_48 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bj_u; + +/* Define the union csr_octl_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_bypass : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_bypass_u; + +/* Define the union csr_octl_ram_ecc_inj_req_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_inj_req_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_inj_req_a_u; + +/* Define the union csr_octl_ram_ecc_inj_req_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_inj_req_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_inj_req_b_u; + +/* Define the union csr_octl_ram_ecc_inj_req_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_inj_req_2 : 2; /* [1:0] */ + u32 rsv_50 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_inj_req_c_u; + +/* Define the union csr_octl_ram_ecc_err_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_err_a_u; + +/* Define the union csr_octl_ram_ecc_err_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_err_b_u; + +/* Define the union csr_octl_ram_ecc_err_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_err_2 : 2; /* [1:0] */ + u32 rsv_51 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_err_c_u; + +/* Define the union csr_octl_ram_link_list_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_head_empty : 20; /* [19:0] */ + u32 rsv_52 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_aa_u; + +/* Define the union csr_octl_ram_link_list_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_sge_empty : 20; /* [19:0] */ + u32 rsv_53 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ab_u; + +/* Define the union csr_octl_ram_link_list_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_app0_empty : 20; /* [19:0] */ + u32 rsv_54 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ac_u; + +/* Define the union csr_octl_ram_link_list_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_app1_empty : 20; /* [19:0] */ + u32 rsv_55 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ad_u; + +/* Define the union csr_octl_ram_link_list_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_head_empty_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ae_u; + +/* Define the union csr_octl_ram_link_list_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_head_empty_1 : 24; /* [23:0] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_af_u; + +/* Define the union csr_octl_ram_link_list_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_sge_empty_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ag_u; + +/* Define the union csr_octl_ram_link_list_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_sge_empty_1 : 24; /* [23:0] */ + u32 rsv_57 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ah_u; + +/* Define the union csr_octl_ram_link_list_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_app0_empty_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ai_u; + +/* Define the union csr_octl_ram_link_list_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_app0_empty_1 : 24; /* [23:0] */ + u32 rsv_58 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_aj_u; + +/* Define the union csr_octl_ram_link_list_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_2nd_app0_empty : 5; /* [4:0] */ + u32 rsv_59 : 3; /* [7:5] */ + u32 sm_cbuf_ram_2nd_sge_empty : 5; /* [12:8] */ + u32 rsv_60 : 3; /* [15:13] */ + u32 sm_cbuf_ram_2nd_head_empty : 5; /* [20:16] */ + u32 rsv_61 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ak_u; + +/* Define the union csr_octl_ram_link_list_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_2nd_ec_ram_empty : 15; /* [14:0] */ + u32 pe_cmd_1st_ec_ram_empty : 15; /* [29:15] */ + u32 rsv_62 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_al_u; + +/* Define the union csr_octl_ram_link_list_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_proc_ram_empty : 10; /* [9:0] */ + u32 rsv_63 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_am_u; + +/* Define the union csr_octl_ram_link_list_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_app0_free_cell_cnt : 10; /* [9:0] */ + u32 pe_cbuf_ram_sge_free_cell_cnt : 10; /* [19:10] */ + u32 pe_cbuf_ram_head_free_cell_cnt : 10; /* [29:20] */ + u32 rsv_64 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_an_u; + +/* Define the union csr_octl_ram_link_list_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_dbuf_ram_bk1_free_cell_cnt : 10; /* [9:0] */ + u32 pe_dbuf_ram_bk0_free_cell_cnt : 10; /* [19:10] */ + u32 pe_cbuf_ram_app1_free_cell_cnt : 10; /* [29:20] */ + u32 rsv_65 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ao_u; + +/* Define the union csr_octl_ram_link_list_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_sge_free_cell_cnt : 11; /* [10:0] */ + u32 sm_cbuf_ram_head_free_cell_cnt : 11; /* [21:11] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ap_u; + +/* Define the union csr_octl_ram_link_list_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_dbuf_ram_bk1_free_cell_cnt : 10; /* [9:0] */ + u32 sm_dbuf_ram_bk0_free_cell_cnt : 10; /* [19:10] */ + u32 sm_cbuf_ram_app0_free_cell_cnt : 11; /* [30:20] */ + u32 rsv_67 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_aq_u; + +/* Define the union csr_octl_ram_link_list_ar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_proc_free_cell_cnt : 11; /* [10:0] */ + u32 pe_cmd_2nd_ec_free_cell_cnt : 7; /* [17:11] */ + u32 pe_cmd_1st_ec_free_cell_cnt : 7; /* [24:18] */ + u32 rsv_68 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ar_u; + +/* Define the union csr_octl_in_bp_sig_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_a_u; + +/* Define the union csr_octl_in_bp_sig_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_b_u; + +/* Define the union csr_octl_in_bp_sig_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp_2 : 24; /* [23:0] */ + u32 rsv_69 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_c_u; + +/* Define the union csr_octl_in_bp_sig_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_octl_dpath_pe_bp : 20; /* [19:0] */ + u32 rsv_70 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_d_u; + +/* Define the union csr_octl_in_bp_sig_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_octl_cpath_bp : 5; /* [4:0] */ + u32 osch_octl_dpath_sm_bp : 5; /* [9:5] */ + u32 rsv_71 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_e_u; + +/* Define the union csr_octl_in_bp_sig_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cpi_dat_inc_bp : 1; /* [0] */ + u32 mqm_cpi_host_sge_inc_bp : 1; /* [1] */ + u32 mqm_cpi_ep_sge_inc_bp : 1; /* [2] */ + u32 prm_cpi_bp : 1; /* [3] */ + u32 octl_rde_sm_parser_bp : 1; /* [4] */ + u32 octl_cpi_perx_bp : 1; /* [5] */ + u32 rsv_72 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_f_u; + +/* Define the union csr_octl_fifo_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_overflow : 22; /* [21:0] */ + u32 rsv_73 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_a_u; + +/* Define the union csr_octl_fifo_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_underflow : 22; /* [21:0] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_b_u; + +/* Define the union csr_octl_fifo_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_empty : 25; /* [24:0] */ + u32 rsv_75 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_c_u; + +/* Define the union csr_octl_fifo_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_full : 25; /* [24:0] */ + u32 rsv_76 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_d_u; + +/* Define the union csr_octl_fifo_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqe_cmd_fifo_done_port : 5; /* [4:0] */ + u32 cp_l2nic_cqe_en_cmd_pful : 1; /* [5] */ + u32 rsv_77 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_e_u; + +/* Define the union csr_octl_fifo_afon_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbuf_pe_app1_afon_th : 4; /* [3:0] */ + u32 dbuf_pe_app0_afon_th : 4; /* [7:4] */ + u32 cp_l2nic_cqe_en_cmd_afon_th : 5; /* [12:8] */ + u32 smvio_fifo_afon_th : 3; /* [15:13] */ + u32 dpath_o_sfifo_afon_th : 7; /* [22:16] */ + u32 rsv_78 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_afon_a_u; + +/* Define the union csr_octl_fifo_afon_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbuf_sm_app0_afon_th : 4; /* [3:0] */ + u32 cpb_bk1_fifo_afon_th : 6; /* [9:4] */ + u32 cpb_bk0_fifo_afon_th : 6; /* [15:10] */ + u32 cpb_adj_fifo_afon_th : 5; /* [20:16] */ + u32 pe_parser_dbuf_fifo_afon_th : 3; /* [23:21] */ + u32 pe_parser_sge_fifo_afon_th : 3; /* [26:24] */ + u32 pe_parser_head_fifo_afon_th : 3; /* [29:27] */ + u32 rsv_79 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_afon_b_u; + +/* Define the union csr_octl_fifo_afon_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_crdt_fifo_afon_th : 6; /* [5:0] */ + u32 aad_rd_fifo_afon_th : 4; /* [9:6] */ + u32 tlp_rd_fifo_afon_th : 3; /* [12:10] */ + u32 rde_octl_fifo_afon_th : 5; /* [17:13] */ + u32 sm_parser_dbuf_fifo_afon_th : 3; /* [20:18] */ + u32 sm_parser_sge_fifo_afon_th : 3; /* [23:21] */ + u32 sm_parser_head_fifo_afon_th : 3; /* [26:24] */ + u32 dbuf_sm_app1_afon_th : 4; /* [30:27] */ + u32 rsv_80 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_afon_c_u; + +/* Define the union csr_octl_err_sig_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_perx_data_err : 1; /* [0] */ + u32 rsv_81 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_aa_u; + +/* Define the union csr_octl_err_sig_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_loss_sop_err : 20; /* [19:0] */ + u32 rsv_82 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ab_u; + +/* Define the union csr_octl_err_sig_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_loss_eop_err : 20; /* [19:0] */ + u32 rsv_83 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ac_u; + +/* Define the union csr_octl_err_sig_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_non_vld_err : 20; /* [19:0] */ + u32 rsv_84 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ad_u; + +/* Define the union csr_octl_err_sig_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_rel_loss_sop_err : 20; /* [19:0] */ + u32 rsv_85 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ae_u; + +/* Define the union csr_octl_err_sig_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_rel_loss_eop_err : 20; /* [19:0] */ + u32 rsv_86 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_af_u; + +/* Define the union csr_octl_err_sig_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_rel_non_vld_err : 20; /* [19:0] */ + u32 rsv_87 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ag_u; + +/* Define the union csr_octl_err_sig_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_sop_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ah_u; + +/* Define the union csr_octl_err_sig_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_sop_err_1 : 24; /* [23:0] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ai_u; + +/* Define the union csr_octl_err_sig_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_eop_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_aj_u; + +/* Define the union csr_octl_err_sig_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_eop_err_1 : 24; /* [23:0] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ak_u; + +/* Define the union csr_octl_err_sig_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_non_vld_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_al_u; + +/* Define the union csr_octl_err_sig_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_non_vld_err_1 : 24; /* [23:0] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_am_u; + +/* Define the union csr_octl_ec_soro_attr_tbl_first_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_vf_so_ro_0_first : 2; /* [1:0] */ + u32 octl_vf_dma_attr_offset_0_first : 6; /* [7:2] */ + u32 rsv_91 : 2; /* [9:8] */ + u32 octl_vf_so_ro_1_first : 2; /* [11:10] */ + u32 octl_vf_dma_attr_offset_1_first : 6; /* [17:12] */ + u32 rsv_92 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ec_soro_attr_tbl_first_u; + +/* Define the union csr_octl_ec_soro_attr_tbl_second_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_vf_so_ro_0_second : 2; /* [1:0] */ + u32 octl_vf_dma_attr_offset_0_second : 6; /* [7:2] */ + u32 rsv_93 : 2; /* [9:8] */ + u32 octl_vf_so_ro_1_second : 2; /* [11:10] */ + u32 octl_vf_dma_attr_offset_1_second : 6; /* [17:12] */ + u32 rsv_94 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ec_soro_attr_tbl_second_u; + +/* Define the union csr_octl_ec_channel_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_octl_ec_chnl_first : 5; /* [4:0] */ + u32 cpi_octl_ec_chnl_first_en : 1; /* [5] */ + u32 rsv_95 : 4; /* [9:6] */ + u32 cpi_octl_ec_chnl_second : 5; /* [14:10] */ + u32 cpi_octl_ec_chnl_second_en : 1; /* [15] */ + u32 rsv_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ec_channel_enable_u; + +/* Define the union csr_octl_sm_cbuf_i_ready_chnl_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_i_ready_chnl_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sm_cbuf_i_ready_chnl_a_u; + +/* Define the union csr_octl_sm_cbuf_i_ready_chnl_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_i_ready_chnl_b : 24; /* [23:0] */ + u32 rsv_97 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sm_cbuf_i_ready_chnl_b_u; + +/* Define the union csr_octl_mul_host_dif_rd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mul_dif_dma_attr_offset_1 : 6; /* [5:0] */ + u32 octl_mul_dif_so_ro_1 : 2; /* [7:6] */ + u32 rsv_98 : 2; /* [9:8] */ + u32 octl_mul_dif_dma_attr_offset_0 : 6; /* [15:10] */ + u32 octl_mul_dif_so_ro_0 : 2; /* [17:16] */ + u32 cpi_octl_mul_dif_rd_chnl : 5; /* [22:18] */ + u32 cpi_octl_mul_dif_rd_chnl_en : 1; /* [23] */ + u32 rsv_99 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_mul_host_dif_rd_cfg_u; + +/* Define the union csr_octl_db_wr_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_db_wr_sge_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_db_wr_addr_l_u; + +/* Define the union csr_octl_db_wr_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_db_wr_sge_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_db_wr_addr_h_u; + +/* Define the union csr_octl_endian_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_octl_ci_endian_cfg : 1; /* [0] */ + u32 cpi_octl_cqe_endian_cfg : 1; /* [1] */ + u32 rsv_100 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_endian_cfg_u; + +/* Define the union csr_octl_fsm_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_a_u; + +/* Define the union csr_octl_fsm_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_b_u; + +/* Define the union csr_octl_fsm_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_c_u; + +/* Define the union csr_octl_fsm_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_d_u; + +/* Define the union csr_octl_fsm_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_e_u; + +/* Define the union csr_octl_fsm_st_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_ci_data_tbl_st : 12; /* [11:0] */ + u32 cur_ci_attr_tbl_st : 12; /* [23:12] */ + u32 rsv_101 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_f_u; + +/* Define the union csr_octl_head_storage_dfx_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_a_u; + +/* Define the union csr_octl_head_storage_dfx_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_b_u; + +/* Define the union csr_octl_head_storage_dfx_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_c_u; + +/* Define the union csr_octl_head_storage_dfx_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_d_u; + +/* Define the union csr_octl_head_storage_dfx_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_num_deficit_err_head_0 : 30; /* [29:0] */ + u32 rsv_102 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_e_u; + +/* Define the union csr_octl_head_storage_dfx_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_num_deficit_err_head_1 : 13; /* [12:0] */ + u32 rsv_103 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_f_u; + +/* Define the union csr_octl_head_storage_dfx_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge0_len_err_head_0 : 30; /* [29:0] */ + u32 rsv_104 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_g_u; + +/* Define the union csr_octl_head_storage_dfx_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge0_len_err_head_1 : 13; /* [12:0] */ + u32 rsv_105 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_h_u; + +/* Define the union csr_octl_err_sig_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cpath_loss_sop_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_an_u; + +/* Define the union csr_octl_err_sig_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cpath_loss_eop_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ao_u; + +/* Define the union csr_octl_err_sig_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cpath_non_vld_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ap_u; + +/* Define the union csr_octl_err_sig_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_proc_non_vld_err : 6; /* [5:0] */ + u32 octl_proc_cpath_loss_eop_err : 6; /* [11:6] */ + u32 octl_proc_cpath_loss_sop_err : 6; /* [17:12] */ + u32 rsv_106 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_aq_u; + +/* Define the union csr_octl_head_storage_dfx_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_i_u; + +/* Define the union csr_octl_head_storage_dfx_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_j_u; + +/* Define the union csr_octl_head_storage_dfx_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_k_u; + +/* Define the union csr_octl_head_storage_dfx_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_l_u; + +/* Define the union csr_octl_pe_parser_cfg_1st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_num_deficit_err_en : 1; /* [0] */ + u32 sge0_len_err_en : 1; /* [1] */ + u32 pe_unknown_cmd_err_en : 1; /* [2] */ + u32 sge_len_null_en : 1; /* [3] */ + u32 cpi_octl_cqe_ci_cmd_drop_en : 1; /* [4] */ + u32 rsv_107 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_pe_parser_cfg_1st_u; + +/* Define the union csr_octl_loop_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_loop_has_packet : 1; /* [0] */ + u32 sm_l2nic_loop_has_packet : 1; /* [1] */ + u32 cpath_loop_has_packet : 1; /* [2] */ + u32 rsv_108 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_loop_st_a_u; + +/* Define the union csr_octl_loop_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_proc_has_packet : 1; /* [0] */ + u32 cpath_has_packet : 1; /* [1] */ + u32 sm_cmd_ctl_has_packet : 1; /* [2] */ + u32 sm_dbuf_has_packet : 1; /* [3] */ + u32 sm_cbuf_has_packet : 1; /* [4] */ + u32 sm_parser_has_packet : 1; /* [5] */ + u32 pe_cmd_ctl_has_packet : 1; /* [6] */ + u32 pe_cqe_ctl_has_packet : 1; /* [7] */ + u32 pe_dbuf_has_packet : 1; /* [8] */ + u32 pe_cbuf_has_packet : 1; /* [9] */ + u32 pe_parser_has_cpb_crdt : 1; /* [10] */ + u32 pe_parser_has_packet : 1; /* [11] */ + u32 octl_tlp_ctl_has_packet : 1; /* [12] */ + u32 octl_aad_ctl_has_packet : 1; /* [13] */ + u32 octl_dpath_o_has_packet : 1; /* [14] */ + u32 rsv_109 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_loop_st_b_u; + +/* Define the union csr_octl_dfx_sig_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_perx_max_bp_cnt : 12; /* [11:0] */ + u32 rsv_110 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_dfx_sig_a_u; + +/* Define the union csr_octl_pf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_func_idx_l : 5; /* [4:0] */ + u32 rsv_111 : 11; /* [15:5] */ + u32 pf_func_idx_h : 5; /* [20:16] */ + u32 rsv_112 : 10; /* [30:21] */ + u32 pf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_pf_range_port_u; + +/* Define the union csr_octl_vf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_func_idx_l : 12; /* [11:0] */ + u32 rsv_113 : 4; /* [15:12] */ + u32 vf_func_idx_h : 12; /* [27:16] */ + u32 rsv_114 : 3; /* [30:28] */ + u32 vf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vf_range_port_u; + +/* Define the union csr_octl_lvf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lvf_func_idx_l : 12; /* [11:0] */ + u32 rsv_115 : 4; /* [15:12] */ + u32 lvf_func_idx_h : 12; /* [27:16] */ + u32 rsv_116 : 3; /* [30:28] */ + u32 lvf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_lvf_range_port_u; + +/* Define the union csr_octl_vld_sig_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_aa_u; + +/* Define the union csr_octl_vld_sig_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ab_u; + +/* Define the union csr_octl_vld_sig_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ac_u; + +/* Define the union csr_octl_vld_sig_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ad_u; + +/* Define the union csr_octl_vld_sig_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ae_u; + +/* Define the union csr_octl_vld_sig_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_af_u; + +/* Define the union csr_octl_vld_sig_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ag_u; + +/* Define the union csr_octl_vld_sig_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ah_u; + +/* Define the union csr_cpi_octl_cpath_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_sm_crdt_num : 9; /* [8:0] */ + u32 rsv_117 : 1; /* [9] */ + u32 icpl_vio_crdt_num : 10; /* [19:10] */ + u32 osch_host_crdt_num : 8; /* [27:20] */ + u32 cpi_cpath_proc_bypass : 1; /* [28] */ + u32 rsv_118 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_octl_cpath_crdt_u; + +/* Define the union csr_ctrl_bus_cfg_one_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_one : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_one_u; + +/* Define the union csr_ctrl_bus_cfg_two_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_two : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_two_u; + +/* Define the union csr_ctrl_bus_cfg_three_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_three : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_three_u; + +/* Define the union csr_ctrl_bus_cfg_four_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_four : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_four_u; + +/* Define the union csr_ctrl_bus_cfg_five_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_five : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_five_u; + +/* Define the union csr_bak_for_eco_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_b : 16; /* [15:0] */ + u32 bak_for_eco_a : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_aa_u; + +/* Define the union csr_bak_for_eco_bb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_d : 16; /* [15:0] */ + u32 bak_for_eco_c : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_bb_u; + +/* Define the union csr_octl_head_storage_dfx_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_m_u; + +/* Define the union csr_octl_head_storage_dfx_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_n_u; + +/* Define the union csr_octl_head_storage_dfx_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_o_u; + +/* Define the union csr_octl_head_storage_dfx_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_p_u; + +/* Define the union csr_bak_for_eco_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_f : 16; /* [15:0] */ + u32 bak_for_eco_e : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_cc_u; + +/* Define the union csr_bak_for_eco_dd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_h : 16; /* [15:0] */ + u32 bak_for_eco_g : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_dd_u; + +/* Define the union csr_bak_for_eco_ee_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_j : 16; /* [15:0] */ + u32 bak_for_eco_i : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_ee_u; + +/* Define the union csr_cpi_sm_chl_cfg_en_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_sm_chl_cfg_en_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_sm_chl_cfg_en_a_u; + +/* Define the union csr_cpi_sm_chl_cfg_en_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_sm_chl_cfg_en_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_sm_chl_cfg_en_b_u; + +/* Define the union csr_cpi_octl_mul_wr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mul_wr_dma_attr_offset : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 octl_mul_wr_so_ro : 2; /* [9:8] */ + u32 rsv_120 : 2; /* [11:10] */ + u32 octl_mul_wr_soro_attr_en : 1; /* [12] */ + u32 rsv_121 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_octl_mul_wr_cfg_u; + +/* Define the union csr_cpi_octl_cqe_ctl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqe_cmd_fifo_alfull_gap : 11; /* [10:0] */ + u32 rsv_122 : 1; /* [11] */ + u32 l2nic_ci_force_update : 1; /* [12] */ + u32 rsv_123 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_octl_cqe_ctl_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_octl_tbl_indir_ctrl0_u octl_tbl_indir_ctrl0; /* 0 */ + volatile csr_octl_tbl_indir_ctrl1_u octl_tbl_indir_ctrl1; /* 4 */ + volatile csr_octl_tbl_indir_data_u octl_tbl_indir_data[8]; /* 8 */ + volatile csr_octl_ram_init_req_u octl_ram_init_req; /* 28 */ + volatile csr_octl_ram_init_sts_u octl_ram_init_sts; /* 2C */ + volatile csr_pre_sub_dat_crd_cpb_u pre_sub_dat_crd_cpb; /* 30 */ + volatile csr_l2nic_ci_wr_chl_cfg_u l2nic_ci_wr_chl_cfg; /* 34 */ + volatile csr_cqe_wr_chl_cfg_u cqe_wr_chl_cfg; /* 38 */ + volatile csr_pcie_port_cfg_u pcie_port_cfg; /* 3C */ + volatile csr_dma_pe_yyy_fifo_depth_port012_u dma_pe_yyy_fifo_depth_port012; /* 40 */ + volatile csr_dma_pe_yyy_fifo_depth_port34_u dma_pe_yyy_fifo_depth_port34; /* 44 */ + volatile csr_cpi_prealloc_cpb_buf_u cpi_prealloc_cpb_buf; /* 48 */ + volatile csr_cpi_sm_chl_cfg_u cpi_sm_chl_cfg[16]; /* 4C */ + volatile csr_octl_cut_thr_cfg_u octl_cut_thr_cfg; /* 8C */ + volatile csr_octl_in_cmd_chnl_src_sel_u octl_in_cmd_chnl_src_sel; /* 94 */ + volatile csr_octl_err_detect_reg_a_u octl_err_detect_reg_a; /* 98 */ + volatile csr_octl_err_detect_reg_b_u octl_err_detect_reg_b; /* 9C */ + volatile csr_octl_err_detect_ro_reg_a_u octl_err_detect_ro_reg_a; /* A0 */ + volatile csr_octl_err_detect_ro_reg_b_u octl_err_detect_ro_reg_b; /* A4 */ + volatile csr_octl_err_detect_ro_reg_c_u octl_err_detect_ro_reg_c; /* A8 */ + volatile csr_octl_err_detect_ro_reg_d_u octl_err_detect_ro_reg_d; /* AC */ + volatile csr_octl_cmd_cnt_a_u octl_cmd_cnt_a; /* B0 */ + volatile csr_octl_cmd_cnt_b_u octl_cmd_cnt_b; /* B4 */ + volatile csr_octl_cmd_cnt_c_u octl_cmd_cnt_c; /* B8 */ + volatile csr_octl_cmd_cnt_d_u octl_cmd_cnt_d; /* BC */ + volatile csr_octl_cmd_cnt_e_u octl_cmd_cnt_e; /* C0 */ + volatile csr_octl_cmd_cnt_f_u octl_cmd_cnt_f; /* C4 */ + volatile csr_octl_cmd_cnt_g_u octl_cmd_cnt_g; /* C8 */ + volatile csr_octl_cmd_cnt_h_u octl_cmd_cnt_h; /* CC */ + volatile csr_octl_cmd_cnt_i_u octl_cmd_cnt_i; /* D0 */ + volatile csr_octl_cmd_cnt_j_u octl_cmd_cnt_j; /* D4 */ + volatile csr_octl_cmd_cnt_k_u octl_cmd_cnt_k; /* D8 */ + volatile csr_octl_cmd_cnt_l_u octl_cmd_cnt_l; /* DC */ + volatile csr_octl_cmd_cnt_m_u octl_cmd_cnt_m; /* E0 */ + volatile csr_octl_cmd_cnt_n_u octl_cmd_cnt_n; /* E4 */ + volatile csr_octl_cmd_cnt_o_u octl_cmd_cnt_o; /* E8 */ + volatile csr_octl_cmd_cnt_p_u octl_cmd_cnt_p; /* EC */ + volatile csr_octl_cmd_cnt_q_u octl_cmd_cnt_q; /* F0 */ + volatile csr_octl_cmd_cnt_r_u octl_cmd_cnt_r; /* F4 */ + volatile csr_octl_cmd_cnt_s_u octl_cmd_cnt_s; /* F8 */ + volatile csr_octl_cmd_cnt_t_u octl_cmd_cnt_t; /* FC */ + volatile csr_octl_cmd_cnt_u_u octl_cmd_cnt_u; /* 100 */ + volatile csr_octl_cmd_cnt_v_u octl_cmd_cnt_v; /* 104 */ + volatile csr_octl_cmd_cnt_w_u octl_cmd_cnt_w; /* 108 */ + volatile csr_octl_cmd_cnt_x_u octl_cmd_cnt_x; /* 10C */ + volatile csr_octl_cmd_cnt_y_u octl_cmd_cnt_y; /* 110 */ + volatile csr_octl_cmd_cnt_z_u octl_cmd_cnt_z; /* 114 */ + volatile csr_octl_cmd_cnt_aa_u octl_cmd_cnt_aa; /* 118 */ + volatile csr_octl_cmd_cnt_ab_u octl_cmd_cnt_ab; /* 11C */ + volatile csr_octl_cmd_cnt_ac_u octl_cmd_cnt_ac; /* 120 */ + volatile csr_octl_cmd_cnt_ad_u octl_cmd_cnt_ad; /* 124 */ + volatile csr_octl_cmd_cnt_ae_u octl_cmd_cnt_ae; /* 128 */ + volatile csr_octl_cmd_cnt_af_u octl_cmd_cnt_af; /* 12C */ + volatile csr_octl_cmd_cnt_ag_u octl_cmd_cnt_ag; /* 130 */ + volatile csr_octl_cmd_cnt_ah_u octl_cmd_cnt_ah; /* 134 */ + volatile csr_octl_cmd_cnt_ai_u octl_cmd_cnt_ai; /* 138 */ + volatile csr_octl_cmd_cnt_aj_u octl_cmd_cnt_aj; /* 13C */ + volatile csr_octl_cmd_cnt_ak_u octl_cmd_cnt_ak; /* 140 */ + volatile csr_octl_cmd_cnt_al_u octl_cmd_cnt_al; /* 144 */ + volatile csr_octl_cmd_cnt_am_u octl_cmd_cnt_am; /* 148 */ + volatile csr_octl_cmd_cnt_an_u octl_cmd_cnt_an; /* 14C */ + volatile csr_octl_cmd_cnt_ao_u octl_cmd_cnt_ao; /* 150 */ + volatile csr_octl_cmd_cnt_ap_u octl_cmd_cnt_ap; /* 154 */ + volatile csr_octl_cmd_cnt_aq_u octl_cmd_cnt_aq; /* 158 */ + volatile csr_octl_cmd_cnt_ar_u octl_cmd_cnt_ar; /* 15C */ + volatile csr_octl_cmd_cnt_as_u octl_cmd_cnt_as; /* 160 */ + volatile csr_octl_cmd_cnt_at_u octl_cmd_cnt_at; /* 164 */ + volatile csr_octl_cmd_cnt_au_u octl_cmd_cnt_au; /* 168 */ + volatile csr_octl_cmd_cnt_av_u octl_cmd_cnt_av; /* 16C */ + volatile csr_octl_cmd_cnt_aw_u octl_cmd_cnt_aw; /* 170 */ + volatile csr_octl_cmd_cnt_ax_u octl_cmd_cnt_ax; /* 174 */ + volatile csr_octl_cmd_cnt_ay_u octl_cmd_cnt_ay; /* 178 */ + volatile csr_octl_cmd_cnt_az_u octl_cmd_cnt_az; /* 17C */ + volatile csr_octl_cmd_cnt_ba_u octl_cmd_cnt_ba; /* 180 */ + volatile csr_octl_cmd_cnt_bb_u octl_cmd_cnt_bb; /* 184 */ + volatile csr_octl_cmd_cnt_bc_u octl_cmd_cnt_bc; /* 188 */ + volatile csr_octl_cmd_port_aa_u octl_cmd_port_aa[5]; /* 1A0 */ + volatile csr_octl_cmd_port_ab_u octl_cmd_port_ab[5]; /* 1A4 */ + volatile csr_octl_cmd_port_ac_u octl_cmd_port_ac[5]; /* 1A8 */ + volatile csr_octl_cmd_port_ad_u octl_cmd_port_ad[5]; /* 1AC */ + volatile csr_octl_cmd_port_ae_u octl_cmd_port_ae[5]; /* 1B0 */ + volatile csr_octl_cmd_port_af_u octl_cmd_port_af[5]; /* 1B4 */ + volatile csr_octl_cmd_port_ag_u octl_cmd_port_ag[5]; /* 1B8 */ + volatile csr_octl_cmd_port_ah_u octl_cmd_port_ah[5]; /* 1BC */ + volatile csr_octl_cmd_port_ai_u octl_cmd_port_ai[5]; /* 1C0 */ + volatile csr_octl_cmd_port_aj_u octl_cmd_port_aj[5]; /* 1C4 */ + volatile csr_octl_cmd_port_ak_u octl_cmd_port_ak[5]; /* 1C8 */ + volatile csr_octl_cmd_port_al_u octl_cmd_port_al[5]; /* 1CC */ + volatile csr_octl_cmd_port_am_u octl_cmd_port_am[5]; /* 1D0 */ + volatile csr_octl_cmd_port_an_u octl_cmd_port_an[5]; /* 1D4 */ + volatile csr_octl_cmd_cnt_bd_u octl_cmd_cnt_bd; /* 300 */ + volatile csr_octl_cmd_cnt_be_u octl_cmd_cnt_be; /* 304 */ + volatile csr_octl_cmd_cnt_bf_u octl_cmd_cnt_bf; /* 308 */ + volatile csr_octl_cmd_cnt_bg_u octl_cmd_cnt_bg; /* 30C */ + volatile csr_octl_cmd_cnt_bh_u octl_cmd_cnt_bh; /* 310 */ + volatile csr_octl_dpath_o_err_dfx_u octl_dpath_o_err_dfx; /* 340 */ + volatile csr_octl_sub_err_cfg_bk_u octl_sub_err_cfg_bk; /* 350 */ + volatile csr_octl_sub_err_cfg_bl_u octl_sub_err_cfg_bl; /* 354 */ + volatile csr_octl_sub_err_cfg_aa_u octl_sub_err_cfg_aa; /* 358 */ + volatile csr_octl_sub_err_cfg_ab_u octl_sub_err_cfg_ab; /* 35C */ + volatile csr_octl_sub_err_cfg_ac_u octl_sub_err_cfg_ac; /* 360 */ + volatile csr_octl_sub_err_cfg_ad_u octl_sub_err_cfg_ad; /* 364 */ + volatile csr_octl_sub_err_cfg_ae_u octl_sub_err_cfg_ae; /* 368 */ + volatile csr_octl_sub_err_cfg_af_u octl_sub_err_cfg_af; /* 36C */ + volatile csr_octl_sub_err_cfg_ag_u octl_sub_err_cfg_ag; /* 370 */ + volatile csr_octl_sub_err_cfg_ah_u octl_sub_err_cfg_ah; /* 374 */ + volatile csr_octl_sub_err_cfg_ai_u octl_sub_err_cfg_ai; /* 378 */ + volatile csr_octl_sub_err_cfg_aj_u octl_sub_err_cfg_aj; /* 37C */ + volatile csr_octl_sub_err_cfg_ak_u octl_sub_err_cfg_ak; /* 380 */ + volatile csr_octl_sub_err_cfg_al_u octl_sub_err_cfg_al; /* 384 */ + volatile csr_octl_sub_err_cfg_am_u octl_sub_err_cfg_am; /* 388 */ + volatile csr_octl_sub_err_cfg_an_u octl_sub_err_cfg_an; /* 38C */ + volatile csr_octl_sub_err_cfg_ao_u octl_sub_err_cfg_ao; /* 390 */ + volatile csr_octl_sub_err_cfg_ap_u octl_sub_err_cfg_ap; /* 394 */ + volatile csr_octl_sub_err_cfg_aq_u octl_sub_err_cfg_aq; /* 398 */ + volatile csr_octl_sub_err_cfg_ar_u octl_sub_err_cfg_ar; /* 39C */ + volatile csr_octl_sub_err_cfg_as_u octl_sub_err_cfg_as; /* 3A0 */ + volatile csr_octl_sub_err_cfg_at_u octl_sub_err_cfg_at; /* 3A4 */ + volatile csr_octl_sub_err_cfg_au_u octl_sub_err_cfg_au; /* 3A8 */ + volatile csr_octl_sub_err_cfg_av_u octl_sub_err_cfg_av; /* 3AC */ + volatile csr_octl_sub_err_cfg_aw_u octl_sub_err_cfg_aw; /* 3B0 */ + volatile csr_octl_sub_err_cfg_ax_u octl_sub_err_cfg_ax; /* 3B4 */ + volatile csr_octl_sub_err_cfg_ay_u octl_sub_err_cfg_ay; /* 3B8 */ + volatile csr_octl_sub_err_cfg_az_u octl_sub_err_cfg_az; /* 3BC */ + volatile csr_octl_sub_err_cfg_ba_u octl_sub_err_cfg_ba; /* 3C0 */ + volatile csr_octl_sub_err_cfg_bb_u octl_sub_err_cfg_bb; /* 3C4 */ + volatile csr_octl_sub_err_cfg_bc_u octl_sub_err_cfg_bc; /* 3C8 */ + volatile csr_octl_sub_err_cfg_bd_u octl_sub_err_cfg_bd; /* 3CC */ + volatile csr_octl_sub_err_cfg_be_u octl_sub_err_cfg_be; /* 3D0 */ + volatile csr_octl_sub_err_cfg_bf_u octl_sub_err_cfg_bf; /* 3D4 */ + volatile csr_octl_sub_err_cfg_bg_u octl_sub_err_cfg_bg; /* 3D8 */ + volatile csr_octl_sub_err_cfg_bh_u octl_sub_err_cfg_bh; /* 3DC */ + volatile csr_octl_sub_err_cfg_bi_u octl_sub_err_cfg_bi; /* 3E0 */ + volatile csr_octl_sub_err_cfg_bj_u octl_sub_err_cfg_bj; /* 3E4 */ + volatile csr_octl_ram_ecc_bypass_u octl_ram_ecc_bypass; /* 3F8 */ + volatile csr_octl_ram_ecc_inj_req_a_u octl_ram_ecc_inj_req_a; /* 3FC */ + volatile csr_octl_ram_ecc_inj_req_b_u octl_ram_ecc_inj_req_b; /* 400 */ + volatile csr_octl_ram_ecc_inj_req_c_u octl_ram_ecc_inj_req_c; /* 404 */ + volatile csr_octl_ram_ecc_err_a_u octl_ram_ecc_err_a; /* 408 */ + volatile csr_octl_ram_ecc_err_b_u octl_ram_ecc_err_b; /* 40C */ + volatile csr_octl_ram_ecc_err_c_u octl_ram_ecc_err_c; /* 410 */ + volatile csr_octl_ram_link_list_aa_u octl_ram_link_list_aa; /* 414 */ + volatile csr_octl_ram_link_list_ab_u octl_ram_link_list_ab; /* 418 */ + volatile csr_octl_ram_link_list_ac_u octl_ram_link_list_ac; /* 41C */ + volatile csr_octl_ram_link_list_ad_u octl_ram_link_list_ad; /* 420 */ + volatile csr_octl_ram_link_list_ae_u octl_ram_link_list_ae; /* 424 */ + volatile csr_octl_ram_link_list_af_u octl_ram_link_list_af; /* 428 */ + volatile csr_octl_ram_link_list_ag_u octl_ram_link_list_ag; /* 42C */ + volatile csr_octl_ram_link_list_ah_u octl_ram_link_list_ah; /* 430 */ + volatile csr_octl_ram_link_list_ai_u octl_ram_link_list_ai; /* 434 */ + volatile csr_octl_ram_link_list_aj_u octl_ram_link_list_aj; /* 438 */ + volatile csr_octl_ram_link_list_ak_u octl_ram_link_list_ak; /* 43C */ + volatile csr_octl_ram_link_list_al_u octl_ram_link_list_al; /* 440 */ + volatile csr_octl_ram_link_list_am_u octl_ram_link_list_am; /* 444 */ + volatile csr_octl_ram_link_list_an_u octl_ram_link_list_an; /* 448 */ + volatile csr_octl_ram_link_list_ao_u octl_ram_link_list_ao; /* 44C */ + volatile csr_octl_ram_link_list_ap_u octl_ram_link_list_ap; /* 450 */ + volatile csr_octl_ram_link_list_aq_u octl_ram_link_list_aq; /* 454 */ + volatile csr_octl_ram_link_list_ar_u octl_ram_link_list_ar; /* 458 */ + volatile csr_octl_in_bp_sig_a_u octl_in_bp_sig_a; /* 45C */ + volatile csr_octl_in_bp_sig_b_u octl_in_bp_sig_b; /* 460 */ + volatile csr_octl_in_bp_sig_c_u octl_in_bp_sig_c; /* 464 */ + volatile csr_octl_in_bp_sig_d_u octl_in_bp_sig_d; /* 468 */ + volatile csr_octl_in_bp_sig_e_u octl_in_bp_sig_e; /* 46C */ + volatile csr_octl_in_bp_sig_f_u octl_in_bp_sig_f; /* 470 */ + volatile csr_octl_fifo_st_a_u octl_fifo_st_a; /* 474 */ + volatile csr_octl_fifo_st_b_u octl_fifo_st_b; /* 478 */ + volatile csr_octl_fifo_st_c_u octl_fifo_st_c; /* 47C */ + volatile csr_octl_fifo_st_d_u octl_fifo_st_d; /* 480 */ + volatile csr_octl_fifo_st_e_u octl_fifo_st_e; /* 484 */ + volatile csr_octl_fifo_afon_a_u octl_fifo_afon_a; /* 488 */ + volatile csr_octl_fifo_afon_b_u octl_fifo_afon_b; /* 48C */ + volatile csr_octl_fifo_afon_c_u octl_fifo_afon_c; /* 490 */ + volatile csr_octl_err_sig_aa_u octl_err_sig_aa; /* 4A0 */ + volatile csr_octl_err_sig_ab_u octl_err_sig_ab; /* 4A4 */ + volatile csr_octl_err_sig_ac_u octl_err_sig_ac; /* 4A8 */ + volatile csr_octl_err_sig_ad_u octl_err_sig_ad; /* 4AC */ + volatile csr_octl_err_sig_ae_u octl_err_sig_ae; /* 4B0 */ + volatile csr_octl_err_sig_af_u octl_err_sig_af; /* 4B4 */ + volatile csr_octl_err_sig_ag_u octl_err_sig_ag; /* 4B8 */ + volatile csr_octl_err_sig_ah_u octl_err_sig_ah; /* 4BC */ + volatile csr_octl_err_sig_ai_u octl_err_sig_ai; /* 4C0 */ + volatile csr_octl_err_sig_aj_u octl_err_sig_aj; /* 4C4 */ + volatile csr_octl_err_sig_ak_u octl_err_sig_ak; /* 4C8 */ + volatile csr_octl_err_sig_al_u octl_err_sig_al; /* 4CC */ + volatile csr_octl_err_sig_am_u octl_err_sig_am; /* 4D0 */ + volatile csr_octl_ec_soro_attr_tbl_first_u octl_ec_soro_attr_tbl_first; /* 4E4 */ + volatile csr_octl_ec_soro_attr_tbl_second_u octl_ec_soro_attr_tbl_second; /* 4E8 */ + volatile csr_octl_ec_channel_enable_u octl_ec_channel_enable; /* 4EC */ + volatile csr_octl_sm_cbuf_i_ready_chnl_a_u octl_sm_cbuf_i_ready_chnl_a; /* 4F0 */ + volatile csr_octl_sm_cbuf_i_ready_chnl_b_u octl_sm_cbuf_i_ready_chnl_b; /* 4F4 */ + volatile csr_octl_mul_host_dif_rd_cfg_u octl_mul_host_dif_rd_cfg; /* 4F8 */ + volatile csr_octl_db_wr_addr_l_u octl_db_wr_addr_l; /* 4FC */ + volatile csr_octl_db_wr_addr_h_u octl_db_wr_addr_h; /* 500 */ + volatile csr_octl_endian_cfg_u octl_endian_cfg; /* 504 */ + volatile csr_octl_fsm_st_a_u octl_fsm_st_a; /* 560 */ + volatile csr_octl_fsm_st_b_u octl_fsm_st_b; /* 564 */ + volatile csr_octl_fsm_st_c_u octl_fsm_st_c; /* 568 */ + volatile csr_octl_fsm_st_d_u octl_fsm_st_d; /* 56C */ + volatile csr_octl_fsm_st_e_u octl_fsm_st_e; /* 570 */ + volatile csr_octl_fsm_st_f_u octl_fsm_st_f; /* 574 */ + volatile csr_octl_head_storage_dfx_a_u octl_head_storage_dfx_a; /* 578 */ + volatile csr_octl_head_storage_dfx_b_u octl_head_storage_dfx_b; /* 57C */ + volatile csr_octl_head_storage_dfx_c_u octl_head_storage_dfx_c; /* 580 */ + volatile csr_octl_head_storage_dfx_d_u octl_head_storage_dfx_d; /* 584 */ + volatile csr_octl_head_storage_dfx_e_u octl_head_storage_dfx_e; /* 588 */ + volatile csr_octl_head_storage_dfx_f_u octl_head_storage_dfx_f; /* 58C */ + volatile csr_octl_head_storage_dfx_g_u octl_head_storage_dfx_g; /* 590 */ + volatile csr_octl_head_storage_dfx_h_u octl_head_storage_dfx_h; /* 594 */ + volatile csr_octl_err_sig_an_u octl_err_sig_an; /* 598 */ + volatile csr_octl_err_sig_ao_u octl_err_sig_ao; /* 59C */ + volatile csr_octl_err_sig_ap_u octl_err_sig_ap; /* 5A0 */ + volatile csr_octl_err_sig_aq_u octl_err_sig_aq; /* 5A4 */ + volatile csr_octl_head_storage_dfx_i_u octl_head_storage_dfx_i; /* 5A8 */ + volatile csr_octl_head_storage_dfx_j_u octl_head_storage_dfx_j; /* 5AC */ + volatile csr_octl_head_storage_dfx_k_u octl_head_storage_dfx_k; /* 5B0 */ + volatile csr_octl_head_storage_dfx_l_u octl_head_storage_dfx_l; /* 5B4 */ + volatile csr_octl_pe_parser_cfg_1st_u octl_pe_parser_cfg_1st; /* 650 */ + volatile csr_octl_loop_st_a_u octl_loop_st_a; /* 654 */ + volatile csr_octl_loop_st_b_u octl_loop_st_b; /* 658 */ + volatile csr_octl_dfx_sig_a_u octl_dfx_sig_a; /* 65C */ + volatile csr_octl_pf_range_port_u octl_pf_range_port[5]; /* 674 */ + volatile csr_octl_vf_range_port_u octl_vf_range_port[5]; /* 678 */ + volatile csr_octl_lvf_range_port_u octl_lvf_range_port[5]; /* 67C */ + volatile csr_octl_vld_sig_aa_u octl_vld_sig_aa; /* 6C0 */ + volatile csr_octl_vld_sig_ab_u octl_vld_sig_ab; /* 6C4 */ + volatile csr_octl_vld_sig_ac_u octl_vld_sig_ac; /* 6C8 */ + volatile csr_octl_vld_sig_ad_u octl_vld_sig_ad; /* 6CC */ + volatile csr_octl_vld_sig_ae_u octl_vld_sig_ae; /* 6D0 */ + volatile csr_octl_vld_sig_af_u octl_vld_sig_af; /* 6D4 */ + volatile csr_octl_vld_sig_ag_u octl_vld_sig_ag; /* 6D8 */ + volatile csr_octl_vld_sig_ah_u octl_vld_sig_ah; /* 6DC */ + volatile csr_cpi_octl_cpath_crdt_u cpi_octl_cpath_crdt; /* 718 */ + volatile csr_ctrl_bus_cfg_one_u ctrl_bus_cfg_one; /* 71C */ + volatile csr_ctrl_bus_cfg_two_u ctrl_bus_cfg_two; /* 720 */ + volatile csr_ctrl_bus_cfg_three_u ctrl_bus_cfg_three; /* 724 */ + volatile csr_ctrl_bus_cfg_four_u ctrl_bus_cfg_four; /* 728 */ + volatile csr_ctrl_bus_cfg_five_u ctrl_bus_cfg_five; /* 72C */ + volatile csr_bak_for_eco_aa_u bak_for_eco_aa; /* 730 */ + volatile csr_bak_for_eco_bb_u bak_for_eco_bb; /* 734 */ + volatile csr_octl_head_storage_dfx_m_u octl_head_storage_dfx_m; /* 738 */ + volatile csr_octl_head_storage_dfx_n_u octl_head_storage_dfx_n; /* 73C */ + volatile csr_octl_head_storage_dfx_o_u octl_head_storage_dfx_o; /* 740 */ + volatile csr_octl_head_storage_dfx_p_u octl_head_storage_dfx_p; /* 744 */ + volatile csr_bak_for_eco_cc_u bak_for_eco_cc; /* 748 */ + volatile csr_bak_for_eco_dd_u bak_for_eco_dd; /* 74C */ + volatile csr_bak_for_eco_ee_u bak_for_eco_ee; /* 750 */ + volatile csr_cpi_sm_chl_cfg_en_a_u cpi_sm_chl_cfg_en_a; /* 754 */ + volatile csr_cpi_sm_chl_cfg_en_b_u cpi_sm_chl_cfg_en_b; /* 758 */ + volatile csr_cpi_octl_mul_wr_cfg_u cpi_octl_mul_wr_cfg; /* 75C */ + volatile csr_cpi_octl_cqe_ctl_cfg_u cpi_octl_cqe_ctl_cfg; /* 760 */ +} S_cpi_octl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_octl_csr */ +extern volatile S_cpi_octl_csr_REGS_TYPE *gopcpi_octl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_addr(unsigned int uoctl_tbl_indir_addr); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_tab(unsigned int uoctl_tbl_indir_tab); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_stat(unsigned int uoctl_tbl_indir_stat); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_mode(unsigned int uoctl_tbl_indir_mode); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_vld(unsigned int uoctl_tbl_indir_vld); +int iSetOCTL_TBL_INDIR_CTRL1_octl_tbl_indir_timeout(unsigned int uoctl_tbl_indir_timeout); +int iSetOCTL_TBL_INDIR_DATA_octl_tbl_indir_data(unsigned int uoctl_tbl_indir_data); +int iSetOCTL_RAM_INIT_REQ_octl_ram_ini_req(unsigned int uoctl_ram_ini_req); +int iSetOCTL_RAM_INIT_STS_octl_ram_ini_sts(unsigned int uoctl_ram_ini_sts); +int iSetPRE_SUB_DAT_CRD_CPB_cpb_presub_data_crdt(unsigned int ucpb_presub_data_crdt); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port0(unsigned int ul2nic_ci_wr_chl_port0); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port1(unsigned int ul2nic_ci_wr_chl_port1); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port2(unsigned int ul2nic_ci_wr_chl_port2); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port3(unsigned int ul2nic_ci_wr_chl_port3); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port4(unsigned int ul2nic_ci_wr_chl_port4); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port0(unsigned int ucqe_wr_chl_port0); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port1(unsigned int ucqe_wr_chl_port1); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port2(unsigned int ucqe_wr_chl_port2); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port3(unsigned int ucqe_wr_chl_port3); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port4(unsigned int ucqe_wr_chl_port4); +int iSetPCIE_PORT_CFG_pcie_port_cfg(unsigned int upcie_port_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT012_port0_dma_pe_yyy_fifo_depth_cfg(unsigned int uport0_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT012_port1_dma_pe_yyy_fifo_depth_cfg(unsigned int uport1_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT012_port2_dma_pe_yyy_fifo_depth_cfg(unsigned int uport2_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT34_port3_dma_pe_yyy_fifo_depth_cfg(unsigned int uport3_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT34_port4_dma_pe_yyy_fifo_depth_cfg(unsigned int uport4_dma_pe_yyy_fifo_depth_cfg); +int iSetCPI_PREALLOC_CPB_BUF_cpb_cell_prealloc_cfg(unsigned int ucpb_cell_prealloc_cfg); +int iSetCPI_PREALLOC_CPB_BUF_cpb_cell_prealloc_adj(unsigned int ucpb_cell_prealloc_adj); +int iSetCPI_PREALLOC_CPB_BUF_cpb_cell_prealloc_thd(unsigned int ucpb_cell_prealloc_thd); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg0(unsigned int ucpi_sm_chl_cfg0); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg1(unsigned int ucpi_sm_chl_cfg1); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg2(unsigned int ucpi_sm_chl_cfg2); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg3(unsigned int ucpi_sm_chl_cfg3); +int iSetOCTL_CUT_THR_CFG_dma_pe_wdat_cut_through(unsigned int udma_pe_wdat_cut_through); +int iSetOCTL_CUT_THR_CFG_cpath_wdat_cut_through(unsigned int ucpath_wdat_cut_through); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_octl_mem_err_addr_sel(unsigned int uoctl_mem_err_addr_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_perx_cmd_cnt_chnl_sel(unsigned int uperx_cmd_cnt_chnl_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_perx_cmd_cnt_out_grain_cfg(unsigned int uperx_cmd_cnt_out_grain_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_perx_cmd_cnt_in_or_out_cfg(unsigned int uperx_cmd_cnt_in_or_out_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_l2nic_cmd_cnt_chnl_sel(unsigned int ul2nic_cmd_cnt_chnl_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_l2nic_cmd_cnt_out_grain_cfg(unsigned int ul2nic_cmd_cnt_out_grain_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_l2nic_cmd_cnt_in_or_out_cfg(unsigned int ul2nic_cmd_cnt_in_or_out_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_sm_cp_cmd_src_sel(unsigned int usm_cp_cmd_src_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_cpath_cmd_cnt_in_or_out_cfg(unsigned int ucpath_cmd_cnt_in_or_out_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_sm_cp_proc_cmd_src_sel(unsigned int usm_cp_proc_cmd_src_sel); +int iSetOCTL_ERR_DETECT_REG_A_cpi_octl_fatal_err(unsigned int ucpi_octl_fatal_err); +int iSetOCTL_ERR_DETECT_REG_A_cpi_octl_nonfatal_err(unsigned int ucpi_octl_nonfatal_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_mem_ecc_merr_all(unsigned int uoctl_mem_ecc_merr_all); +int iSetOCTL_ERR_DETECT_REG_A_octl_mem_ecc_err_all(unsigned int uoctl_mem_ecc_err_all); +int iSetOCTL_ERR_DETECT_REG_A_proc_cpath_data_err(unsigned int uproc_cpath_data_err); +int iSetOCTL_ERR_DETECT_REG_A_sm_cpath_data_err(unsigned int usm_cpath_data_err); +int iSetOCTL_ERR_DETECT_REG_A_sm_l2nic_data_err(unsigned int usm_l2nic_data_err); +int iSetOCTL_ERR_DETECT_REG_A_rde_octl_data_err(unsigned int urde_octl_data_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_mul_dif_cfg_chnl_err(unsigned int uoctl_mul_dif_cfg_chnl_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_mul_dif_cfg_en_err(unsigned int uoctl_mul_dif_cfg_en_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_ec_chnl_cfg_chnl_err_1(unsigned int uoctl_ec_chnl_cfg_chnl_err_1); +int iSetOCTL_ERR_DETECT_REG_A_octl_ec_chnl_cfg_chnl_err_0(unsigned int uoctl_ec_chnl_cfg_chnl_err_0); +int iSetOCTL_ERR_DETECT_REG_A_octl_ec_chnl_cfg_en_err(unsigned int uoctl_ec_chnl_cfg_en_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_cpb_num_deficit_err(unsigned int uoctl_cpb_num_deficit_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_sge0_len_err_less(unsigned int uoctl_sge0_len_err_less); +int iSetOCTL_ERR_DETECT_REG_A_octl_sge0_len_err_more(unsigned int uoctl_sge0_len_err_more); +int iSetOCTL_ERR_DETECT_REG_A_octl_sge0_len_err(unsigned int uoctl_sge0_len_err); +int iSetOCTL_ERR_DETECT_REG_A_perx_unknown_cmd_err(unsigned int uperx_unknown_cmd_err); +int iSetOCTL_ERR_DETECT_REG_A_perxin_unknown_cmd_err(unsigned int uperxin_unknown_cmd_err); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_rel_non_vld_err_all(unsigned int ucpi_dpath_rel_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_rel_loss_eop_err_all(unsigned int ucpi_dpath_rel_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_rel_loss_sop_err_all(unsigned int ucpi_dpath_rel_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_o_non_vld_err_all(unsigned int ucpi_dpath_o_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_o_loss_eop_err_all(unsigned int ucpi_dpath_o_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_o_loss_sop_err_all(unsigned int ucpi_dpath_o_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_octl_fifo_underflow_all(unsigned int uoctl_fifo_underflow_all); +int iSetOCTL_ERR_DETECT_REG_A_octl_fifo_overflow_all(unsigned int uoctl_fifo_overflow_all); +int iSetOCTL_ERR_DETECT_REG_B_proc_cpath_non_vld_err_all(unsigned int uproc_cpath_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_B_proc_cpath_loss_eop_err_all(unsigned int uproc_cpath_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_proc_cpath_loss_sop_err_all(unsigned int uproc_cpath_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_cpath_non_vld_err_all(unsigned int usm_cpath_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_cpath_loss_eop_err_all(unsigned int usm_cpath_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_cpath_loss_sop_err_all(unsigned int usm_cpath_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_l2nic_non_vld_err_all(unsigned int usm_l2nic_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_l2nic_loss_eop_err_all(unsigned int usm_l2nic_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_l2nic_loss_sop_err_all(unsigned int usm_l2nic_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_octl_sm_parser_data_err(unsigned int uoctl_sm_parser_data_err); +int iSetOCTL_ERR_DETECT_REG_B_octl_perx_hd_dif_err(unsigned int uoctl_perx_hd_dif_err); +int iSetOCTL_ERR_DETECT_REG_B_octl_perx_hd_wdat_err(unsigned int uoctl_perx_hd_wdat_err); +int iSetOCTL_ERR_DETECT_REG_B_octl_dpath_o_sop_err(unsigned int uoctl_dpath_o_sop_err); +int iSetOCTL_ERR_DETECT_RO_REG_A_mqm_cpi_bp_all(unsigned int umqm_cpi_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_osch_octl_cpath_bp_all(unsigned int uosch_octl_cpath_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_osch_octl_dpath_sm_bp_all(unsigned int uosch_octl_dpath_sm_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_osch_octl_dpath_pe_bp_all(unsigned int uosch_octl_dpath_pe_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_prm_cpi_src_bp_all(unsigned int uprm_cpi_src_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_prm_cpi_bp_all(unsigned int uprm_cpi_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_all_fifo_no_empty(unsigned int uoctl_all_fifo_no_empty); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_cpath_loop_swallow_packet(unsigned int uoctl_cpath_loop_swallow_packet); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_l2nic_loop_swallow_packet(unsigned int uoctl_l2nic_loop_swallow_packet); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_pe_loop_swallow_packet(unsigned int uoctl_pe_loop_swallow_packet); +int iSetOCTL_ERR_DETECT_RO_REG_A_dma_pre_alc_num_cur(unsigned int udma_pre_alc_num_cur); +int iSetOCTL_ERR_DETECT_RO_REG_A_glb_cpb_cell_num_cnt(unsigned int uglb_cpb_cell_num_cnt); +int iSetOCTL_ERR_DETECT_RO_REG_B_cp_proc_osch_host_crd_cnt_0(unsigned int ucp_proc_osch_host_crd_cnt_0); +int iSetOCTL_ERR_DETECT_RO_REG_B_cp_proc_icpl_sm_crd_cnt(unsigned int ucp_proc_icpl_sm_crd_cnt); +int iSetOCTL_ERR_DETECT_RO_REG_B_cp_proc_icpl_vio_crd_cnt(unsigned int ucp_proc_icpl_vio_crd_cnt); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_4(unsigned int ucp_proc_osch_host_crd_cnt_4); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_3(unsigned int ucp_proc_osch_host_crd_cnt_3); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_2(unsigned int ucp_proc_osch_host_crd_cnt_2); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_1(unsigned int ucp_proc_osch_host_crd_cnt_1); +int iSetOCTL_ERR_DETECT_RO_REG_D_octl_mem_err_addr(unsigned int uoctl_mem_err_addr); +int iSetOCTL_ERR_DETECT_RO_REG_D_ci_cqe_tbl_indir_op_done(unsigned int uci_cqe_tbl_indir_op_done); +int iSetOCTL_CMD_CNT_A_cpi_dpath_o_sop_inc(unsigned int ucpi_dpath_o_sop_inc); +int iSetOCTL_CMD_CNT_B_cpi_dpath_o_eop_inc(unsigned int ucpi_dpath_o_eop_inc); +int iSetOCTL_CMD_CNT_C_cpi_dpath_rel_sop_inc(unsigned int ucpi_dpath_rel_sop_inc); +int iSetOCTL_CMD_CNT_D_cpi_dpath_rel_eop_inc(unsigned int ucpi_dpath_rel_eop_inc); +int iSetOCTL_CMD_CNT_E_cpi_dpath_in_chnl_sop_inc(unsigned int ucpi_dpath_in_chnl_sop_inc); +int iSetOCTL_CMD_CNT_F_cpi_dpath_in_chnl_eop_inc(unsigned int ucpi_dpath_in_chnl_eop_inc); +int iSetOCTL_CMD_CNT_G_cpi_dpath_rel_chnl_sop_inc(unsigned int ucpi_dpath_rel_chnl_sop_inc); +int iSetOCTL_CMD_CNT_H_cpi_dpath_rel_chnl_eop_inc(unsigned int ucpi_dpath_rel_chnl_eop_inc); +int iSetOCTL_CMD_CNT_I_octl_rd_inc(unsigned int uoctl_rd_inc); +int iSetOCTL_CMD_CNT_J_octl_rd_cqe_inc(unsigned int uoctl_rd_cqe_inc); +int iSetOCTL_CMD_CNT_K_octl_atomic_inc(unsigned int uoctl_atomic_inc); +int iSetOCTL_CMD_CNT_L_octl_non_l2nic_il_inc(unsigned int uoctl_non_l2nic_il_inc); +int iSetOCTL_CMD_CNT_M_octl_non_l2nic_il_cqe_inc(unsigned int uoctl_non_l2nic_il_cqe_inc); +int iSetOCTL_CMD_CNT_N_octl_wr_inc(unsigned int uoctl_wr_inc); +int iSetOCTL_CMD_CNT_O_octl_wr_cqe_inc(unsigned int uoctl_wr_cqe_inc); +int iSetOCTL_CMD_CNT_P_octl_cqe_only_inc(unsigned int uoctl_cqe_only_inc); +int iSetOCTL_CMD_CNT_Q_octl_ceqe_only(unsigned int uoctl_ceqe_only); +int iSetOCTL_CMD_CNT_R_octl_db_wr_inc(unsigned int uoctl_db_wr_inc); +int iSetOCTL_CMD_CNT_S_octl_mul_dif_rd_inc(unsigned int uoctl_mul_dif_rd_inc); +int iSetOCTL_CMD_CNT_T_octl_ec_rd_1st_inc(unsigned int uoctl_ec_rd_1st_inc); +int iSetOCTL_CMD_CNT_U_octl_ec_rd_2nd_inc(unsigned int uoctl_ec_rd_2nd_inc); +int iSetOCTL_CMD_CNT_V_octl_ec_cqe_rd_1st_inc(unsigned int uoctl_ec_cqe_rd_1st_inc); +int iSetOCTL_CMD_CNT_W_octl_ec_cqe_rd_2nd_inc(unsigned int uoctl_ec_cqe_rd_2nd_inc); +int iSetOCTL_CMD_CNT_X_octl_rd_by_aad_inc(unsigned int uoctl_rd_by_aad_inc); +int iSetOCTL_CMD_CNT_Y_icpl_cqe_inc(unsigned int uicpl_cqe_inc); +int iSetOCTL_CMD_CNT_Z_icpl_ci_inc(unsigned int uicpl_ci_inc); +int iSetOCTL_CMD_CNT_AA_icpl_cqe_only_ceqe_inc(unsigned int uicpl_cqe_only_ceqe_inc); +int iSetOCTL_CMD_CNT_AB_sm_cbuf_head_obd_0_inc(unsigned int usm_cbuf_head_obd_0_inc); +int iSetOCTL_CMD_CNT_AC_sm_cbuf_head_obd_1_inc(unsigned int usm_cbuf_head_obd_1_inc); +int iSetOCTL_CMD_CNT_AD_sm_cbuf_head_obd_2_inc(unsigned int usm_cbuf_head_obd_2_inc); +int iSetOCTL_CMD_CNT_AE_sm_cbuf_head_obd_3_inc(unsigned int usm_cbuf_head_obd_3_inc); +int iSetOCTL_CMD_CNT_AF_sm_cbuf_head_obd_4_inc(unsigned int usm_cbuf_head_obd_4_inc); +int iSetOCTL_CMD_CNT_AG_sm_parser_sop_inc(unsigned int usm_parser_sop_inc); +int iSetOCTL_CMD_CNT_AH_sm_parser_eop_inc(unsigned int usm_parser_eop_inc); +int iSetOCTL_CMD_CNT_AI_sm_l2nic_sop_inc(unsigned int usm_l2nic_sop_inc); +int iSetOCTL_CMD_CNT_AJ_sm_l2nic_eop_inc(unsigned int usm_l2nic_eop_inc); +int iSetOCTL_CMD_CNT_AK_sm_l2nic_chnl_sop_inc(unsigned int usm_l2nic_chnl_sop_inc); +int iSetOCTL_CMD_CNT_AL_sm_l2nic_chnl_eop_inc(unsigned int usm_l2nic_chnl_eop_inc); +int iSetOCTL_CMD_CNT_AM_sm_l2nic_read_inc(unsigned int usm_l2nic_read_inc); +int iSetOCTL_CMD_CNT_AN_sm_l2nic_ceqe_only_inc(unsigned int usm_l2nic_ceqe_only_inc); +int iSetOCTL_CMD_CNT_AO_sm_l2nic_il_inc(unsigned int usm_l2nic_il_inc); +int iSetOCTL_CMD_CNT_AP_sm_l2nic_read_ci_inc(unsigned int usm_l2nic_read_ci_inc); +int iSetOCTL_CMD_CNT_AQ_sm_l2nic_il_ci_inc(unsigned int usm_l2nic_il_ci_inc); +int iSetOCTL_CMD_CNT_AR_sm_cpath_sop_inc(unsigned int usm_cpath_sop_inc); +int iSetOCTL_CMD_CNT_AS_sm_cpath_eop_inc(unsigned int usm_cpath_eop_inc); +int iSetOCTL_CMD_CNT_AT_sm_cpath_rd_inc(unsigned int usm_cpath_rd_inc); +int iSetOCTL_CMD_CNT_AU_sm_cpath_wr_inc(unsigned int usm_cpath_wr_inc); +int iSetOCTL_CMD_CNT_AV_sm_cp_in_src_sop_inc(unsigned int usm_cp_in_src_sop_inc); +int iSetOCTL_CMD_CNT_AW_sm_cp_in_src_eop_inc(unsigned int usm_cp_in_src_eop_inc); +int iSetOCTL_CMD_CNT_AX_sm_cp_proc_src_sop_inc(unsigned int usm_cp_proc_src_sop_inc); +int iSetOCTL_CMD_CNT_AY_sm_cp_proc_src_eop_inc(unsigned int usm_cp_proc_src_eop_inc); +int iSetOCTL_CMD_CNT_AZ_sm_cp_proc_rd_inc(unsigned int usm_cp_proc_rd_inc); +int iSetOCTL_CMD_CNT_BA_sm_cp_proc_wr_inc(unsigned int usm_cp_proc_wr_inc); +int iSetOCTL_CMD_CNT_BB_octl_osch_cp_rd_inc(unsigned int uoctl_osch_cp_rd_inc); +int iSetOCTL_CMD_CNT_BC_octl_osch_cp_wr_inc(unsigned int uoctl_osch_cp_wr_inc); +int iSetOCTL_CMD_PORT_AA_port_octl_rd_cqe_inc(unsigned int uport_octl_rd_cqe_inc); +int iSetOCTL_CMD_PORT_AA_port_octl_rd_inc(unsigned int uport_octl_rd_inc); +int iSetOCTL_CMD_PORT_AB_port_octl_non_l2nic_il_inc(unsigned int uport_octl_non_l2nic_il_inc); +int iSetOCTL_CMD_PORT_AB_port_octl_atomic_inc(unsigned int uport_octl_atomic_inc); +int iSetOCTL_CMD_PORT_AC_port_octl_wr_inc(unsigned int uport_octl_wr_inc); +int iSetOCTL_CMD_PORT_AC_port_octl_non_l2nic_il_cqe_inc(unsigned int uport_octl_non_l2nic_il_cqe_inc); +int iSetOCTL_CMD_PORT_AD_port_octl_cqe_only_inc(unsigned int uport_octl_cqe_only_inc); +int iSetOCTL_CMD_PORT_AD_port_octl_wr_cqe_inc(unsigned int uport_octl_wr_cqe_inc); +int iSetOCTL_CMD_PORT_AE_port_octl_db_wr_inc(unsigned int uport_octl_db_wr_inc); +int iSetOCTL_CMD_PORT_AE_port_octl_ceqe_only_inc(unsigned int uport_octl_ceqe_only_inc); +int iSetOCTL_CMD_PORT_AF_port_octl_ec_rd_1st_inc(unsigned int uport_octl_ec_rd_1st_inc); +int iSetOCTL_CMD_PORT_AF_port_octl_mul_dif_rd_inc(unsigned int uport_octl_mul_dif_rd_inc); +int iSetOCTL_CMD_PORT_AG_port_octl_ec_cqe_rd_1st_inc(unsigned int uport_octl_ec_cqe_rd_1st_inc); +int iSetOCTL_CMD_PORT_AG_port_octl_ec_rd_2nd_inc(unsigned int uport_octl_ec_rd_2nd_inc); +int iSetOCTL_CMD_PORT_AH_port_octl_rd_by_aad_inc(unsigned int uport_octl_rd_by_aad_inc); +int iSetOCTL_CMD_PORT_AH_port_octl_ec_cqe_rd_2nd_inc(unsigned int uport_octl_ec_cqe_rd_2nd_inc); +int iSetOCTL_CMD_PORT_AI_port_icpl_cqe_only_ceqe_inc(unsigned int uport_icpl_cqe_only_ceqe_inc); +int iSetOCTL_CMD_PORT_AI_port_icpl_cqe_inc(unsigned int uport_icpl_cqe_inc); +int iSetOCTL_CMD_PORT_AJ_octl_pe_cmd_port_inc(unsigned int uoctl_pe_cmd_port_inc); +int iSetOCTL_CMD_PORT_AJ_port_icpl_ci_inc(unsigned int uport_icpl_ci_inc); +int iSetOCTL_CMD_PORT_AK_port_sm_l2nic_ceqe_only_inc(unsigned int uport_sm_l2nic_ceqe_only_inc); +int iSetOCTL_CMD_PORT_AK_port_sm_l2nic_read_inc(unsigned int uport_sm_l2nic_read_inc); +int iSetOCTL_CMD_PORT_AL_port_sm_l2nic_read_ci_inc(unsigned int uport_sm_l2nic_read_ci_inc); +int iSetOCTL_CMD_PORT_AL_port_sm_l2nic_il_inc(unsigned int uport_sm_l2nic_il_inc); +int iSetOCTL_CMD_PORT_AM_octl_port_cp_inc(unsigned int uoctl_port_cp_inc); +int iSetOCTL_CMD_PORT_AM_port_sm_l2nic_il_ci_inc(unsigned int uport_sm_l2nic_il_ci_inc); +int iSetOCTL_CMD_PORT_AN_octl_port_cp_wr_inc(unsigned int uoctl_port_cp_wr_inc); +int iSetOCTL_CMD_PORT_AN_octl_port_cp_rd_inc(unsigned int uoctl_port_cp_rd_inc); +int iSetOCTL_CMD_CNT_BD_sm_parser_cpath_inc(unsigned int usm_parser_cpath_inc); +int iSetOCTL_CMD_CNT_BE_sm_parser_l2nic_inc(unsigned int usm_parser_l2nic_inc); +int iSetOCTL_CMD_CNT_BF_sm_parser_ceqe_only_inc(unsigned int usm_parser_ceqe_only_inc); +int iSetOCTL_CMD_CNT_BG_proc_cpath_eop_inc(unsigned int uproc_cpath_eop_inc); +int iSetOCTL_CMD_CNT_BG_proc_cpath_sop_inc(unsigned int uproc_cpath_sop_inc); +int iSetOCTL_CMD_CNT_BH_octl_drop_zero_sge_len_inc(unsigned int uoctl_drop_zero_sge_len_inc); +int iSetOCTL_DPATH_O_ERR_DFX_octl_dpath_o_chnl_sop_err(unsigned int uoctl_dpath_o_chnl_sop_err); +int iSetOCTL_SUB_ERR_CFG_BK_octl_err_fatal_mask_18(unsigned int uoctl_err_fatal_mask_18); +int iSetOCTL_SUB_ERR_CFG_BL_octl_err_nonfatal_mask_18(unsigned int uoctl_err_nonfatal_mask_18); +int iSetOCTL_SUB_ERR_CFG_AA_octl_err_fatal_mask_0(unsigned int uoctl_err_fatal_mask_0); +int iSetOCTL_SUB_ERR_CFG_AB_octl_err_nonfatal_mask_0(unsigned int uoctl_err_nonfatal_mask_0); +int iSetOCTL_SUB_ERR_CFG_AC_octl_err_fatal_mask_1(unsigned int uoctl_err_fatal_mask_1); +int iSetOCTL_SUB_ERR_CFG_AD_octl_err_nonfatal_mask_1(unsigned int uoctl_err_nonfatal_mask_1); +int iSetOCTL_SUB_ERR_CFG_AE_octl_err_fatal_mask_2(unsigned int uoctl_err_fatal_mask_2); +int iSetOCTL_SUB_ERR_CFG_AF_octl_err_nonfatal_mask_2(unsigned int uoctl_err_nonfatal_mask_2); +int iSetOCTL_SUB_ERR_CFG_AG_octl_err_fatal_mask_3(unsigned int uoctl_err_fatal_mask_3); +int iSetOCTL_SUB_ERR_CFG_AH_octl_err_nonfatal_mask_3(unsigned int uoctl_err_nonfatal_mask_3); +int iSetOCTL_SUB_ERR_CFG_AI_octl_err_fatal_mask_4(unsigned int uoctl_err_fatal_mask_4); +int iSetOCTL_SUB_ERR_CFG_AJ_octl_err_nonfatal_mask_4(unsigned int uoctl_err_nonfatal_mask_4); +int iSetOCTL_SUB_ERR_CFG_AK_octl_err_fatal_mask_5(unsigned int uoctl_err_fatal_mask_5); +int iSetOCTL_SUB_ERR_CFG_AL_octl_err_nonfatal_mask_5(unsigned int uoctl_err_nonfatal_mask_5); +int iSetOCTL_SUB_ERR_CFG_AM_octl_err_fatal_mask_6(unsigned int uoctl_err_fatal_mask_6); +int iSetOCTL_SUB_ERR_CFG_AN_octl_err_nonfatal_mask_6(unsigned int uoctl_err_nonfatal_mask_6); +int iSetOCTL_SUB_ERR_CFG_AO_octl_err_fatal_mask_7(unsigned int uoctl_err_fatal_mask_7); +int iSetOCTL_SUB_ERR_CFG_AP_octl_err_nonfatal_mask_7(unsigned int uoctl_err_nonfatal_mask_7); +int iSetOCTL_SUB_ERR_CFG_AQ_octl_err_fatal_mask_8(unsigned int uoctl_err_fatal_mask_8); +int iSetOCTL_SUB_ERR_CFG_AR_octl_err_nonfatal_mask_8(unsigned int uoctl_err_nonfatal_mask_8); +int iSetOCTL_SUB_ERR_CFG_AS_octl_err_fatal_mask_9(unsigned int uoctl_err_fatal_mask_9); +int iSetOCTL_SUB_ERR_CFG_AT_octl_err_nonfatal_mask_9(unsigned int uoctl_err_nonfatal_mask_9); +int iSetOCTL_SUB_ERR_CFG_AU_octl_err_fatal_mask_10(unsigned int uoctl_err_fatal_mask_10); +int iSetOCTL_SUB_ERR_CFG_AV_octl_err_nonfatal_mask_10(unsigned int uoctl_err_nonfatal_mask_10); +int iSetOCTL_SUB_ERR_CFG_AW_octl_err_fatal_mask_11(unsigned int uoctl_err_fatal_mask_11); +int iSetOCTL_SUB_ERR_CFG_AX_octl_err_nonfatal_mask_11(unsigned int uoctl_err_nonfatal_mask_11); +int iSetOCTL_SUB_ERR_CFG_AY_octl_err_fatal_mask_12(unsigned int uoctl_err_fatal_mask_12); +int iSetOCTL_SUB_ERR_CFG_AZ_octl_err_nonfatal_mask_12(unsigned int uoctl_err_nonfatal_mask_12); +int iSetOCTL_SUB_ERR_CFG_BA_octl_err_fatal_mask_13(unsigned int uoctl_err_fatal_mask_13); +int iSetOCTL_SUB_ERR_CFG_BB_octl_err_nonfatal_mask_13(unsigned int uoctl_err_nonfatal_mask_13); +int iSetOCTL_SUB_ERR_CFG_BC_octl_err_fatal_mask_14(unsigned int uoctl_err_fatal_mask_14); +int iSetOCTL_SUB_ERR_CFG_BD_octl_err_nonfatal_mask_14(unsigned int uoctl_err_nonfatal_mask_14); +int iSetOCTL_SUB_ERR_CFG_BE_octl_err_fatal_mask_15(unsigned int uoctl_err_fatal_mask_15); +int iSetOCTL_SUB_ERR_CFG_BF_octl_err_nonfatal_mask_15(unsigned int uoctl_err_nonfatal_mask_15); +int iSetOCTL_SUB_ERR_CFG_BG_octl_err_fatal_mask_16(unsigned int uoctl_err_fatal_mask_16); +int iSetOCTL_SUB_ERR_CFG_BH_octl_err_nonfatal_mask_16(unsigned int uoctl_err_nonfatal_mask_16); +int iSetOCTL_SUB_ERR_CFG_BI_octl_err_fatal_mask_17(unsigned int uoctl_err_fatal_mask_17); +int iSetOCTL_SUB_ERR_CFG_BJ_octl_err_nonfatal_mask_17(unsigned int uoctl_err_nonfatal_mask_17); +int iSetOCTL_RAM_ECC_BYPASS_mem_ecc_bypass(unsigned int umem_ecc_bypass); +int iSetOCTL_RAM_ECC_INJ_REQ_A_mem_ecc_inj_req_0(unsigned int umem_ecc_inj_req_0); +int iSetOCTL_RAM_ECC_INJ_REQ_B_mem_ecc_inj_req_1(unsigned int umem_ecc_inj_req_1); +int iSetOCTL_RAM_ECC_INJ_REQ_C_mem_ecc_inj_req_2(unsigned int umem_ecc_inj_req_2); +int iSetOCTL_RAM_ECC_ERR_A_mem_ecc_err_0(unsigned int umem_ecc_err_0); +int iSetOCTL_RAM_ECC_ERR_B_mem_ecc_err_1(unsigned int umem_ecc_err_1); +int iSetOCTL_RAM_ECC_ERR_C_mem_ecc_err_2(unsigned int umem_ecc_err_2); +int iSetOCTL_RAM_LINK_LIST_AA_pe_cbuf_ram_head_empty(unsigned int upe_cbuf_ram_head_empty); +int iSetOCTL_RAM_LINK_LIST_AB_pe_cbuf_ram_sge_empty(unsigned int upe_cbuf_ram_sge_empty); +int iSetOCTL_RAM_LINK_LIST_AC_pe_cbuf_ram_app0_empty(unsigned int upe_cbuf_ram_app0_empty); +int iSetOCTL_RAM_LINK_LIST_AD_pe_cbuf_ram_app1_empty(unsigned int upe_cbuf_ram_app1_empty); +int iSetOCTL_RAM_LINK_LIST_AE_sm_cbuf_ram_1st_head_empty_0(unsigned int usm_cbuf_ram_1st_head_empty_0); +int iSetOCTL_RAM_LINK_LIST_AF_sm_cbuf_ram_1st_head_empty_1(unsigned int usm_cbuf_ram_1st_head_empty_1); +int iSetOCTL_RAM_LINK_LIST_AG_sm_cbuf_ram_1st_sge_empty_0(unsigned int usm_cbuf_ram_1st_sge_empty_0); +int iSetOCTL_RAM_LINK_LIST_AH_sm_cbuf_ram_1st_sge_empty_1(unsigned int usm_cbuf_ram_1st_sge_empty_1); +int iSetOCTL_RAM_LINK_LIST_AI_sm_cbuf_ram_1st_app0_empty_0(unsigned int usm_cbuf_ram_1st_app0_empty_0); +int iSetOCTL_RAM_LINK_LIST_AJ_sm_cbuf_ram_1st_app0_empty_1(unsigned int usm_cbuf_ram_1st_app0_empty_1); +int iSetOCTL_RAM_LINK_LIST_AK_sm_cbuf_ram_2nd_app0_empty(unsigned int usm_cbuf_ram_2nd_app0_empty); +int iSetOCTL_RAM_LINK_LIST_AK_sm_cbuf_ram_2nd_sge_empty(unsigned int usm_cbuf_ram_2nd_sge_empty); +int iSetOCTL_RAM_LINK_LIST_AK_sm_cbuf_ram_2nd_head_empty(unsigned int usm_cbuf_ram_2nd_head_empty); +int iSetOCTL_RAM_LINK_LIST_AL_pe_cmd_2nd_ec_ram_empty(unsigned int upe_cmd_2nd_ec_ram_empty); +int iSetOCTL_RAM_LINK_LIST_AL_pe_cmd_1st_ec_ram_empty(unsigned int upe_cmd_1st_ec_ram_empty); +int iSetOCTL_RAM_LINK_LIST_AM_cpath_proc_ram_empty(unsigned int ucpath_proc_ram_empty); +int iSetOCTL_RAM_LINK_LIST_AN_pe_cbuf_ram_app0_free_cell_cnt(unsigned int upe_cbuf_ram_app0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AN_pe_cbuf_ram_sge_free_cell_cnt(unsigned int upe_cbuf_ram_sge_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AN_pe_cbuf_ram_head_free_cell_cnt(unsigned int upe_cbuf_ram_head_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AO_pe_dbuf_ram_bk1_free_cell_cnt(unsigned int upe_dbuf_ram_bk1_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AO_pe_dbuf_ram_bk0_free_cell_cnt(unsigned int upe_dbuf_ram_bk0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AO_pe_cbuf_ram_app1_free_cell_cnt(unsigned int upe_cbuf_ram_app1_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AP_sm_cbuf_ram_sge_free_cell_cnt(unsigned int usm_cbuf_ram_sge_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AP_sm_cbuf_ram_head_free_cell_cnt(unsigned int usm_cbuf_ram_head_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AQ_sm_dbuf_ram_bk1_free_cell_cnt(unsigned int usm_dbuf_ram_bk1_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AQ_sm_dbuf_ram_bk0_free_cell_cnt(unsigned int usm_dbuf_ram_bk0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AQ_sm_cbuf_ram_app0_free_cell_cnt(unsigned int usm_cbuf_ram_app0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AR_cpath_proc_free_cell_cnt(unsigned int ucpath_proc_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AR_pe_cmd_2nd_ec_free_cell_cnt(unsigned int upe_cmd_2nd_ec_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AR_pe_cmd_1st_ec_free_cell_cnt(unsigned int upe_cmd_1st_ec_free_cell_cnt); +int iSetOCTL_IN_BP_SIG_A_prm_cpi_src_bp_0(unsigned int uprm_cpi_src_bp_0); +int iSetOCTL_IN_BP_SIG_B_prm_cpi_src_bp_1(unsigned int uprm_cpi_src_bp_1); +int iSetOCTL_IN_BP_SIG_C_prm_cpi_src_bp_2(unsigned int uprm_cpi_src_bp_2); +int iSetOCTL_IN_BP_SIG_D_osch_octl_dpath_pe_bp(unsigned int uosch_octl_dpath_pe_bp); +int iSetOCTL_IN_BP_SIG_E_osch_octl_cpath_bp(unsigned int uosch_octl_cpath_bp); +int iSetOCTL_IN_BP_SIG_E_osch_octl_dpath_sm_bp(unsigned int uosch_octl_dpath_sm_bp); +int iSetOCTL_IN_BP_SIG_F_mqm_cpi_dat_inc_bp(unsigned int umqm_cpi_dat_inc_bp); +int iSetOCTL_IN_BP_SIG_F_mqm_cpi_host_sge_inc_bp(unsigned int umqm_cpi_host_sge_inc_bp); +int iSetOCTL_IN_BP_SIG_F_mqm_cpi_ep_sge_inc_bp(unsigned int umqm_cpi_ep_sge_inc_bp); +int iSetOCTL_IN_BP_SIG_F_prm_cpi_bp(unsigned int uprm_cpi_bp); +int iSetOCTL_IN_BP_SIG_F_octl_rde_sm_parser_bp(unsigned int uoctl_rde_sm_parser_bp); +int iSetOCTL_IN_BP_SIG_F_octl_cpi_perx_bp(unsigned int uoctl_cpi_perx_bp); +int iSetOCTL_FIFO_ST_A_octl_fifo_overflow(unsigned int uoctl_fifo_overflow); +int iSetOCTL_FIFO_ST_B_octl_fifo_underflow(unsigned int uoctl_fifo_underflow); +int iSetOCTL_FIFO_ST_C_octl_fifo_empty(unsigned int uoctl_fifo_empty); +int iSetOCTL_FIFO_ST_D_octl_fifo_full(unsigned int uoctl_fifo_full); +int iSetOCTL_FIFO_ST_E_cqe_cmd_fifo_done_port(unsigned int ucqe_cmd_fifo_done_port); +int iSetOCTL_FIFO_ST_E_cp_l2nic_cqe_en_cmd_pful(unsigned int ucp_l2nic_cqe_en_cmd_pful); +int iSetOCTL_FIFO_AFON_A_dbuf_pe_app1_afon_th(unsigned int udbuf_pe_app1_afon_th); +int iSetOCTL_FIFO_AFON_A_dbuf_pe_app0_afon_th(unsigned int udbuf_pe_app0_afon_th); +int iSetOCTL_FIFO_AFON_A_cp_l2nic_cqe_en_cmd_afon_th(unsigned int ucp_l2nic_cqe_en_cmd_afon_th); +int iSetOCTL_FIFO_AFON_A_smvio_fifo_afon_th(unsigned int usmvio_fifo_afon_th); +int iSetOCTL_FIFO_AFON_A_dpath_o_sfifo_afon_th(unsigned int udpath_o_sfifo_afon_th); +int iSetOCTL_FIFO_AFON_B_dbuf_sm_app0_afon_th(unsigned int udbuf_sm_app0_afon_th); +int iSetOCTL_FIFO_AFON_B_cpb_bk1_fifo_afon_th(unsigned int ucpb_bk1_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_cpb_bk0_fifo_afon_th(unsigned int ucpb_bk0_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_cpb_adj_fifo_afon_th(unsigned int ucpb_adj_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_pe_parser_dbuf_fifo_afon_th(unsigned int upe_parser_dbuf_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_pe_parser_sge_fifo_afon_th(unsigned int upe_parser_sge_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_pe_parser_head_fifo_afon_th(unsigned int upe_parser_head_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sge_crdt_fifo_afon_th(unsigned int usge_crdt_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_aad_rd_fifo_afon_th(unsigned int uaad_rd_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_tlp_rd_fifo_afon_th(unsigned int utlp_rd_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_rde_octl_fifo_afon_th(unsigned int urde_octl_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sm_parser_dbuf_fifo_afon_th(unsigned int usm_parser_dbuf_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sm_parser_sge_fifo_afon_th(unsigned int usm_parser_sge_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sm_parser_head_fifo_afon_th(unsigned int usm_parser_head_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_dbuf_sm_app1_afon_th(unsigned int udbuf_sm_app1_afon_th); +int iSetOCTL_ERR_SIG_AA_octl_perx_data_err(unsigned int uoctl_perx_data_err); +int iSetOCTL_ERR_SIG_AB_octl_dpath_o_loss_sop_err(unsigned int uoctl_dpath_o_loss_sop_err); +int iSetOCTL_ERR_SIG_AC_octl_dpath_o_loss_eop_err(unsigned int uoctl_dpath_o_loss_eop_err); +int iSetOCTL_ERR_SIG_AD_octl_dpath_o_non_vld_err(unsigned int uoctl_dpath_o_non_vld_err); +int iSetOCTL_ERR_SIG_AE_octl_dpath_rel_loss_sop_err(unsigned int uoctl_dpath_rel_loss_sop_err); +int iSetOCTL_ERR_SIG_AF_octl_dpath_rel_loss_eop_err(unsigned int uoctl_dpath_rel_loss_eop_err); +int iSetOCTL_ERR_SIG_AG_octl_dpath_rel_non_vld_err(unsigned int uoctl_dpath_rel_non_vld_err); +int iSetOCTL_ERR_SIG_AH_octl_l2nic_loss_sop_err_0(unsigned int uoctl_l2nic_loss_sop_err_0); +int iSetOCTL_ERR_SIG_AI_octl_l2nic_loss_sop_err_1(unsigned int uoctl_l2nic_loss_sop_err_1); +int iSetOCTL_ERR_SIG_AJ_octl_l2nic_loss_eop_err_0(unsigned int uoctl_l2nic_loss_eop_err_0); +int iSetOCTL_ERR_SIG_AK_octl_l2nic_loss_eop_err_1(unsigned int uoctl_l2nic_loss_eop_err_1); +int iSetOCTL_ERR_SIG_AL_octl_l2nic_non_vld_err_0(unsigned int uoctl_l2nic_non_vld_err_0); +int iSetOCTL_ERR_SIG_AM_octl_l2nic_non_vld_err_1(unsigned int uoctl_l2nic_non_vld_err_1); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_so_ro_0_first(unsigned int uoctl_vf_so_ro_0_first); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_dma_attr_offset_0_first(unsigned int uoctl_vf_dma_attr_offset_0_first); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_so_ro_1_first(unsigned int uoctl_vf_so_ro_1_first); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_dma_attr_offset_1_first(unsigned int uoctl_vf_dma_attr_offset_1_first); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_so_ro_0_second(unsigned int uoctl_vf_so_ro_0_second); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_dma_attr_offset_0_second(unsigned int uoctl_vf_dma_attr_offset_0_second); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_so_ro_1_second(unsigned int uoctl_vf_so_ro_1_second); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_dma_attr_offset_1_second(unsigned int uoctl_vf_dma_attr_offset_1_second); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_first(unsigned int ucpi_octl_ec_chnl_first); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_first_en(unsigned int ucpi_octl_ec_chnl_first_en); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_second(unsigned int ucpi_octl_ec_chnl_second); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_second_en(unsigned int ucpi_octl_ec_chnl_second_en); +int iSetOCTL_SM_CBUF_I_READY_CHNL_A_sm_cbuf_i_ready_chnl_a(unsigned int usm_cbuf_i_ready_chnl_a); +int iSetOCTL_SM_CBUF_I_READY_CHNL_B_sm_cbuf_i_ready_chnl_b(unsigned int usm_cbuf_i_ready_chnl_b); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_dma_attr_offset_1(unsigned int uoctl_mul_dif_dma_attr_offset_1); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_so_ro_1(unsigned int uoctl_mul_dif_so_ro_1); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_dma_attr_offset_0(unsigned int uoctl_mul_dif_dma_attr_offset_0); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_so_ro_0(unsigned int uoctl_mul_dif_so_ro_0); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_cpi_octl_mul_dif_rd_chnl(unsigned int ucpi_octl_mul_dif_rd_chnl); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_cpi_octl_mul_dif_rd_chnl_en(unsigned int ucpi_octl_mul_dif_rd_chnl_en); +int iSetOCTL_DB_WR_ADDR_L_octl_db_wr_sge_addr_l(unsigned int uoctl_db_wr_sge_addr_l); +int iSetOCTL_DB_WR_ADDR_H_octl_db_wr_sge_addr_h(unsigned int uoctl_db_wr_sge_addr_h); +int iSetOCTL_ENDIAN_CFG_cpi_octl_ci_endian_cfg(unsigned int ucpi_octl_ci_endian_cfg); +int iSetOCTL_ENDIAN_CFG_cpi_octl_cqe_endian_cfg(unsigned int ucpi_octl_cqe_endian_cfg); +int iSetOCTL_FSM_ST_A_cpi_dpath_o_cur_st_a(unsigned int ucpi_dpath_o_cur_st_a); +int iSetOCTL_FSM_ST_B_cpi_dpath_o_cur_st_b(unsigned int ucpi_dpath_o_cur_st_b); +int iSetOCTL_FSM_ST_C_cpi_dpath_o_cur_st_c(unsigned int ucpi_dpath_o_cur_st_c); +int iSetOCTL_FSM_ST_D_cpi_dpath_o_cur_st_d(unsigned int ucpi_dpath_o_cur_st_d); +int iSetOCTL_FSM_ST_E_cpi_dpath_o_cur_st_e(unsigned int ucpi_dpath_o_cur_st_e); +int iSetOCTL_FSM_ST_F_cur_ci_data_tbl_st(unsigned int ucur_ci_data_tbl_st); +int iSetOCTL_FSM_ST_F_cur_ci_attr_tbl_st(unsigned int ucur_ci_attr_tbl_st); +int iSetOCTL_HEAD_STORAGE_DFX_A_pe_unknown_cmd_head_0(unsigned int upe_unknown_cmd_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_B_pe_unknown_cmd_head_1(unsigned int upe_unknown_cmd_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_C_pe_unknown_cmd_head_2(unsigned int upe_unknown_cmd_head_2); +int iSetOCTL_HEAD_STORAGE_DFX_D_pe_unknown_cmd_head_3(unsigned int upe_unknown_cmd_head_3); +int iSetOCTL_HEAD_STORAGE_DFX_E_cpb_num_deficit_err_head_0(unsigned int ucpb_num_deficit_err_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_F_cpb_num_deficit_err_head_1(unsigned int ucpb_num_deficit_err_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_G_sge0_len_err_head_0(unsigned int usge0_len_err_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_H_sge0_len_err_head_1(unsigned int usge0_len_err_head_1); +int iSetOCTL_ERR_SIG_AN_octl_cpath_loss_sop_err(unsigned int uoctl_cpath_loss_sop_err); +int iSetOCTL_ERR_SIG_AO_octl_cpath_loss_eop_err(unsigned int uoctl_cpath_loss_eop_err); +int iSetOCTL_ERR_SIG_AP_octl_cpath_non_vld_err(unsigned int uoctl_cpath_non_vld_err); +int iSetOCTL_ERR_SIG_AQ_octl_proc_non_vld_err(unsigned int uoctl_proc_non_vld_err); +int iSetOCTL_ERR_SIG_AQ_octl_proc_cpath_loss_eop_err(unsigned int uoctl_proc_cpath_loss_eop_err); +int iSetOCTL_ERR_SIG_AQ_octl_proc_cpath_loss_sop_err(unsigned int uoctl_proc_cpath_loss_sop_err); +int iSetOCTL_HEAD_STORAGE_DFX_I_pe_cmd_last_known_head_0(unsigned int upe_cmd_last_known_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_J_pe_cmd_last_known_head_1(unsigned int upe_cmd_last_known_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_K_pe_cmd_last_known_head_2(unsigned int upe_cmd_last_known_head_2); +int iSetOCTL_HEAD_STORAGE_DFX_L_pe_cmd_last_known_head_3(unsigned int upe_cmd_last_known_head_3); +int iSetOCTL_PE_PARSER_CFG_1ST_cpb_num_deficit_err_en(unsigned int ucpb_num_deficit_err_en); +int iSetOCTL_PE_PARSER_CFG_1ST_sge0_len_err_en(unsigned int usge0_len_err_en); +int iSetOCTL_PE_PARSER_CFG_1ST_pe_unknown_cmd_err_en(unsigned int upe_unknown_cmd_err_en); +int iSetOCTL_PE_PARSER_CFG_1ST_sge_len_null_en(unsigned int usge_len_null_en); +int iSetOCTL_PE_PARSER_CFG_1ST_cpi_octl_cqe_ci_cmd_drop_en(unsigned int ucpi_octl_cqe_ci_cmd_drop_en); +int iSetOCTL_LOOP_ST_A_pe_loop_has_packet(unsigned int upe_loop_has_packet); +int iSetOCTL_LOOP_ST_A_sm_l2nic_loop_has_packet(unsigned int usm_l2nic_loop_has_packet); +int iSetOCTL_LOOP_ST_A_cpath_loop_has_packet(unsigned int ucpath_loop_has_packet); +int iSetOCTL_LOOP_ST_B_cpath_proc_has_packet(unsigned int ucpath_proc_has_packet); +int iSetOCTL_LOOP_ST_B_cpath_has_packet(unsigned int ucpath_has_packet); +int iSetOCTL_LOOP_ST_B_sm_cmd_ctl_has_packet(unsigned int usm_cmd_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_sm_dbuf_has_packet(unsigned int usm_dbuf_has_packet); +int iSetOCTL_LOOP_ST_B_sm_cbuf_has_packet(unsigned int usm_cbuf_has_packet); +int iSetOCTL_LOOP_ST_B_sm_parser_has_packet(unsigned int usm_parser_has_packet); +int iSetOCTL_LOOP_ST_B_pe_cmd_ctl_has_packet(unsigned int upe_cmd_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_pe_cqe_ctl_has_packet(unsigned int upe_cqe_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_pe_dbuf_has_packet(unsigned int upe_dbuf_has_packet); +int iSetOCTL_LOOP_ST_B_pe_cbuf_has_packet(unsigned int upe_cbuf_has_packet); +int iSetOCTL_LOOP_ST_B_pe_parser_has_cpb_crdt(unsigned int upe_parser_has_cpb_crdt); +int iSetOCTL_LOOP_ST_B_pe_parser_has_packet(unsigned int upe_parser_has_packet); +int iSetOCTL_LOOP_ST_B_octl_tlp_ctl_has_packet(unsigned int uoctl_tlp_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_octl_aad_ctl_has_packet(unsigned int uoctl_aad_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_octl_dpath_o_has_packet(unsigned int uoctl_dpath_o_has_packet); +int iSetOCTL_DFX_SIG_A_cpi_perx_max_bp_cnt(unsigned int ucpi_perx_max_bp_cnt); +int iSetOCTL_PF_RANGE_PORT_pf_func_idx_l(unsigned int upf_func_idx_l); +int iSetOCTL_PF_RANGE_PORT_pf_func_idx_h(unsigned int upf_func_idx_h); +int iSetOCTL_PF_RANGE_PORT_pf_func_idx_v(unsigned int upf_func_idx_v); +int iSetOCTL_VF_RANGE_PORT_vf_func_idx_l(unsigned int uvf_func_idx_l); +int iSetOCTL_VF_RANGE_PORT_vf_func_idx_h(unsigned int uvf_func_idx_h); +int iSetOCTL_VF_RANGE_PORT_vf_func_idx_v(unsigned int uvf_func_idx_v); +int iSetOCTL_LVF_RANGE_PORT_lvf_func_idx_l(unsigned int ulvf_func_idx_l); +int iSetOCTL_LVF_RANGE_PORT_lvf_func_idx_h(unsigned int ulvf_func_idx_h); +int iSetOCTL_LVF_RANGE_PORT_lvf_func_idx_v(unsigned int ulvf_func_idx_v); +int iSetOCTL_VLD_SIG_AA_octl_inside_data_vld_0(unsigned int uoctl_inside_data_vld_0); +int iSetOCTL_VLD_SIG_AB_octl_inside_data_vld_1(unsigned int uoctl_inside_data_vld_1); +int iSetOCTL_VLD_SIG_AC_octl_inside_data_vld_2(unsigned int uoctl_inside_data_vld_2); +int iSetOCTL_VLD_SIG_AD_octl_inside_data_vld_3(unsigned int uoctl_inside_data_vld_3); +int iSetOCTL_VLD_SIG_AE_octl_inside_data_vld_4(unsigned int uoctl_inside_data_vld_4); +int iSetOCTL_VLD_SIG_AF_octl_inside_data_vld_5(unsigned int uoctl_inside_data_vld_5); +int iSetOCTL_VLD_SIG_AG_octl_inside_data_vld_6(unsigned int uoctl_inside_data_vld_6); +int iSetOCTL_VLD_SIG_AH_octl_inside_data_vld_7(unsigned int uoctl_inside_data_vld_7); +int iSetCPI_OCTL_CPATH_CRDT_icpl_sm_crdt_num(unsigned int uicpl_sm_crdt_num); +int iSetCPI_OCTL_CPATH_CRDT_icpl_vio_crdt_num(unsigned int uicpl_vio_crdt_num); +int iSetCPI_OCTL_CPATH_CRDT_osch_host_crdt_num(unsigned int uosch_host_crdt_num); +int iSetCPI_OCTL_CPATH_CRDT_cpi_cpath_proc_bypass(unsigned int ucpi_cpath_proc_bypass); +int iSetCTRL_BUS_CFG_ONE_ctrl_bus_one(unsigned int uctrl_bus_one); +int iSetCTRL_BUS_CFG_TWO_ctrl_bus_two(unsigned int uctrl_bus_two); +int iSetCTRL_BUS_CFG_THREE_ctrl_bus_three(unsigned int uctrl_bus_three); +int iSetCTRL_BUS_CFG_FOUR_ctrl_bus_four(unsigned int uctrl_bus_four); +int iSetCTRL_BUS_CFG_FIVE_ctrl_bus_five(unsigned int uctrl_bus_five); +int iSetBAK_FOR_ECO_AA_bak_for_eco_b(unsigned int ubak_for_eco_b); +int iSetBAK_FOR_ECO_AA_bak_for_eco_a(unsigned int ubak_for_eco_a); +int iSetBAK_FOR_ECO_BB_bak_for_eco_d(unsigned int ubak_for_eco_d); +int iSetBAK_FOR_ECO_BB_bak_for_eco_c(unsigned int ubak_for_eco_c); +int iSetOCTL_HEAD_STORAGE_DFX_M_perxin_unknown_cmd_head_0(unsigned int uperxin_unknown_cmd_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_N_perxin_unknown_cmd_head_1(unsigned int uperxin_unknown_cmd_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_O_perxin_unknown_cmd_head_2(unsigned int uperxin_unknown_cmd_head_2); +int iSetOCTL_HEAD_STORAGE_DFX_P_perxin_unknown_cmd_head_3(unsigned int uperxin_unknown_cmd_head_3); +int iSetBAK_FOR_ECO_CC_bak_for_eco_f(unsigned int ubak_for_eco_f); +int iSetBAK_FOR_ECO_CC_bak_for_eco_e(unsigned int ubak_for_eco_e); +int iSetBAK_FOR_ECO_DD_bak_for_eco_h(unsigned int ubak_for_eco_h); +int iSetBAK_FOR_ECO_DD_bak_for_eco_g(unsigned int ubak_for_eco_g); +int iSetBAK_FOR_ECO_EE_bak_for_eco_j(unsigned int ubak_for_eco_j); +int iSetBAK_FOR_ECO_EE_bak_for_eco_i(unsigned int ubak_for_eco_i); +int iSetCPI_SM_CHL_CFG_EN_A_cpi_sm_chl_cfg_en_a(unsigned int ucpi_sm_chl_cfg_en_a); +int iSetCPI_SM_CHL_CFG_EN_B_cpi_sm_chl_cfg_en_b(unsigned int ucpi_sm_chl_cfg_en_b); +int iSetCPI_OCTL_MUL_WR_CFG_octl_mul_wr_dma_attr_offset(unsigned int uoctl_mul_wr_dma_attr_offset); +int iSetCPI_OCTL_MUL_WR_CFG_octl_mul_wr_so_ro(unsigned int uoctl_mul_wr_so_ro); +int iSetCPI_OCTL_MUL_WR_CFG_octl_mul_wr_soro_attr_en(unsigned int uoctl_mul_wr_soro_attr_en); +int iSetCPI_OCTL_CQE_CTL_CFG_cqe_cmd_fifo_alfull_gap(unsigned int ucqe_cmd_fifo_alfull_gap); +int iSetCPI_OCTL_CQE_CTL_CFG_l2nic_ci_force_update(unsigned int ul2nic_ci_force_update); + +/* Define the union csr_osch_tlp_drop_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port0_u; + +/* Define the union csr_osch_tlp_drop_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port1_u; + +/* Define the union csr_osch_tlp_drop_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port2_u; + +/* Define the union csr_osch_tlp_drop_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port3_u; + +/* Define the union csr_osch_tlp_drop_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port4_u; + +/* Define the union csr_osch_tlp_error_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_err_count_port3 : 8; /* [7:0] */ + u32 osch_tlp_err_count_port2 : 8; /* [15:8] */ + u32 osch_tlp_err_count_port1 : 8; /* [23:16] */ + u32 osch_tlp_err_count_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_error_cnt0_u; + +/* Define the union csr_osch_tlp_error_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_err_count_port4 : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_error_cnt1_u; + +/* Define the union csr_osch_tlp_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt0_u; + +/* Define the union csr_osch_tlp_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt1_u; + +/* Define the union csr_osch_tlp_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt2_u; + +/* Define the union csr_osch_tlp_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt3_u; + +/* Define the union csr_osch_tlp_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt4_u; + +/* Define the union csr_osch_tlp_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt5_u; + +/* Define the union csr_osch_tlp_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt6_u; + +/* Define the union csr_osch_tlp_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt7_u; + +/* Define the union csr_osch_tlp_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt8_u; + +/* Define the union csr_osch_tlp_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt9_u; + +/* Define the union csr_osch_tlp_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt10_u; + +/* Define the union csr_osch_tlp_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt11_u; + +/* Define the union csr_osch_tlp_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt12_u; + +/* Define the union csr_osch_tlp_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt13_u; + +/* Define the union csr_osch_tlp_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt14_u; + +/* Define the union csr_osch_tlp_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt15_u; + +/* Define the union csr_osch_tlp_drop_func01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func1 : 12; /* [11:0] */ + u32 rsv_1 : 4; /* [15:12] */ + u32 osch_tlp_drop_func0 : 12; /* [27:16] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func01_u; + +/* Define the union csr_osch_tlp_drop_func23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func3 : 12; /* [11:0] */ + u32 rsv_3 : 4; /* [15:12] */ + u32 osch_tlp_drop_func2 : 12; /* [27:16] */ + u32 rsv_4 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func23_u; + +/* Define the union csr_osch_tlp_drop_func45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func5 : 12; /* [11:0] */ + u32 rsv_5 : 4; /* [15:12] */ + u32 osch_tlp_drop_func4 : 12; /* [27:16] */ + u32 rsv_6 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func45_u; + +/* Define the union csr_osch_tlp_drop_func67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func7 : 12; /* [11:0] */ + u32 rsv_7 : 4; /* [15:12] */ + u32 osch_tlp_drop_func6 : 12; /* [27:16] */ + u32 rsv_8 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func67_u; + +/* Define the union csr_osch_tlp_drop_func89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func9 : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 osch_tlp_drop_func8 : 12; /* [27:16] */ + u32 rsv_10 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func89_u; + +/* Define the union csr_osch_tlp_drop_func1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func11 : 12; /* [11:0] */ + u32 rsv_11 : 4; /* [15:12] */ + u32 osch_tlp_drop_func10 : 12; /* [27:16] */ + u32 rsv_12 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func1011_u; + +/* Define the union csr_osch_tlp_drop_func1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func13 : 12; /* [11:0] */ + u32 rsv_13 : 4; /* [15:12] */ + u32 osch_tlp_drop_func12 : 12; /* [27:16] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func1213_u; + +/* Define the union csr_osch_tlp_drop_func1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func15 : 12; /* [11:0] */ + u32 rsv_15 : 4; /* [15:12] */ + u32 osch_tlp_drop_func14 : 12; /* [27:16] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func1415_u; + +/* Define the union csr_osch_ceqe_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_drop_cnt : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_drop_cnt_u; + +/* Define the union csr_osch_ceqe_pi_overflow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_pi_overfl_qid : 12; /* [11:0] */ + u32 rsv_18 : 19; /* [30:12] */ + u32 osch_ceqe_pi_overfl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_pi_overflow_u; + +/* Define the union csr_osch_fifo_overflow_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_overflow_id : 6; /* [5:0] */ + u32 rsv_19 : 25; /* [30:6] */ + u32 osch_fifo_overflow : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_overflow_low_u; + +/* Define the union csr_osch_req_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_port_busy_src : 30; /* [29:0] */ + u32 rsv_20 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_req_timeout_u; + +/* Define the union csr_osch_fifo_empt_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_empty_high : 28; /* [27:0] */ + u32 rsv_21 : 3; /* [30:28] */ + u32 osch_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_empt_high_u; + +/* Define the union csr_osch_fifo_empt_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_empty_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_empt_low_u; + +/* Define the union csr_osch_fifo_afull_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_afull_high : 28; /* [27:0] */ + u32 rsv_22 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_afull_high_u; + +/* Define the union csr_osch_fifo_afull_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_afull_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_afull_low_u; + +/* Define the union csr_osch_payload_fifo_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_ctrl_all_port : 7; /* [6:0] */ + u32 rsv_23 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_payload_fifo_ctrl_u; + +/* Define the union csr_osch_msi_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ctrl_port3 : 7; /* [6:0] */ + u32 rsv_24 : 1; /* [7] */ + u32 osch_msi_tx_fifo_ctrl_port2 : 7; /* [14:8] */ + u32 rsv_25 : 1; /* [15] */ + u32 osch_msi_tx_fifo_ctrl_port1 : 7; /* [22:16] */ + u32 rsv_26 : 1; /* [23] */ + u32 osch_msi_tx_fifo_ctrl_port0 : 7; /* [30:24] */ + u32 rsv_27 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_msi_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_msi_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ctrl_port4 : 7; /* [6:0] */ + u32 rsv_28 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_msi_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_atomic_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_atomic_tx_fifo_ctrl_port3 : 7; /* [6:0] */ + u32 rsv_29 : 1; /* [7] */ + u32 osch_atomic_tx_fifo_ctrl_port2 : 7; /* [14:8] */ + u32 rsv_30 : 1; /* [15] */ + u32 osch_atomic_tx_fifo_ctrl_port1 : 7; /* [22:16] */ + u32 rsv_31 : 1; /* [23] */ + u32 osch_atomic_tx_fifo_ctrl_port0 : 7; /* [30:24] */ + u32 rsv_32 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_atomic_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_atomic_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_atomic_tx_fifo_ctrl_port4 : 7; /* [6:0] */ + u32 rsv_33 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_atomic_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_ceqe_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_tx_fifo_ctrl_port3 : 7; /* [6:0] */ + u32 rsv_34 : 1; /* [7] */ + u32 osch_ceqe_tx_fifo_ctrl_port2 : 7; /* [14:8] */ + u32 rsv_35 : 1; /* [15] */ + u32 osch_ceqe_tx_fifo_ctrl_port1 : 7; /* [22:16] */ + u32 rsv_36 : 1; /* [23] */ + u32 osch_ceqe_tx_fifo_ctrl_port0 : 7; /* [30:24] */ + u32 rsv_37 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_ceqe_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_tx_fifo_ctrl_port4 : 7; /* [6:0] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_cpld_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_tx_fifo_ctrl_port3 : 6; /* [5:0] */ + u32 rsv_39 : 2; /* [7:6] */ + u32 osch_cpld_tx_fifo_ctrl_port2 : 6; /* [13:8] */ + u32 rsv_40 : 2; /* [15:14] */ + u32 osch_cpld_tx_fifo_ctrl_port1 : 6; /* [21:16] */ + u32 rsv_41 : 2; /* [23:22] */ + u32 osch_cpld_tx_fifo_ctrl_port0 : 6; /* [29:24] */ + u32 rsv_42 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpld_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_cpld_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_tx_fifo_ctrl_port4 : 6; /* [5:0] */ + u32 rsv_43 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpld_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_fifo_empt_tophigh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_empty_tophigh : 14; /* [13:0] */ + u32 rsv_44 : 2; /* [15:14] */ + u32 osch_port_pipe_empty : 5; /* [20:16] */ + u32 osch_port_sch_pipe_empty : 2; /* [22:21] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_empt_tophigh_u; + +/* Define the union csr_osch_fifo_afull_tophigh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_afull_tophigh : 14; /* [13:0] */ + u32 rsv_46 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_afull_tophigh_u; + +/* Define the union csr_osch_cpath_q0_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_cpath_q0_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_cpath_q0_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_cpath_q0_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q0_fifo_ctrl0_u; + +/* Define the union csr_osch_cpath_q0_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q0_fifo_ctrl1_u; + +/* Define the union csr_osch_cpath_q1_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q1_fifo_ctrl_port2 : 9; /* [8:0] */ + u32 osch_cpath_q1_fifo_ctrl_port1 : 9; /* [17:9] */ + u32 osch_cpath_q1_fifo_ctrl_port0 : 9; /* [26:18] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q1_fifo_ctrl0_u; + +/* Define the union csr_osch_cpath_q1_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q1_fifo_ctrl_port4 : 9; /* [8:0] */ + u32 osch_cpath_q1_fifo_ctrl_port3 : 9; /* [17:9] */ + u32 rsv_49 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q1_fifo_ctrl1_u; + +/* Define the union csr_osch_cpath_q2_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q2_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_cpath_q2_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_cpath_q2_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_cpath_q2_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q2_fifo_ctrl0_u; + +/* Define the union csr_osch_cpath_q2_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q2_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_50 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q2_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q0_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q0_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q0_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q0_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q0_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q0_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q0_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q1_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q1_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q1_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q1_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q1_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q1_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q1_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q1_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_52 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q1_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q2_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q2_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q2_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q2_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q2_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q2_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q2_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q2_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_53 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q2_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q3_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q3_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q3_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q3_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q3_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q3_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_54 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q3_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q4_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q4_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q4_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q4_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q4_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q4_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q4_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q4_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q4_fifo_ctrl1_u; + +/* Define the union csr_osch_reserved0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_resved0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_reserved0_u; + +/* Define the union csr_osch_reserved1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_resved1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_reserved1_u; + +/* Define the union csr_osch_reserved2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_resved2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_reserved2_u; + +/* Define the union csr_glb_post_head_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_post_head_credit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_post_head_credit_u; + +/* Define the union csr_glb_post_payload_credit_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_post_payload_credit_h : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_post_payload_credit_h_u; + +/* Define the union csr_glb_post_payload_credit_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_post_payload_credit_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_post_payload_credit_l_u; + +/* Define the union csr_glb_non_post_head_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_post_head_credit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_non_post_head_credit_u; + +/* Define the union csr_glb_non_post_payload_credit_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_post_payload_credit_h : 16; /* [15:0] */ + u32 rsv_57 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_non_post_payload_credit_h_u; + +/* Define the union csr_glb_non_post_payload_credit_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_post_payload_credit_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_non_post_payload_credit_l_u; + +/* Define the union csr_glb_cpl_head_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_head_credit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_head_credit_u; + +/* Define the union csr_glb_cpl_payload_credit_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_payload_credit_h : 16; /* [15:0] */ + u32 rsv_58 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_payload_credit_h_u; + +/* Define the union csr_glb_cpl_payload_credit_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_payload_credit_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_payload_credit_l_u; + +/* Define the union csr_glb_osch_ceqe_in_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_ceqe_in_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_ceqe_in_cnt_u; + +/* Define the union csr_glb_osch_ceqe_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_ceqe_out_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_ceqe_out_cnt_u; + +/* Define the union csr_glb_ceqe_drop_tail_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ceqe_drop_tail : 5; /* [4:0] */ + u32 ceqe_cls_glb_offs_drop_en : 1; /* [5] */ + u32 rsv_59 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ceqe_drop_tail_u; + +/* Define the union csr_osch_tlp_post_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port0_u; + +/* Define the union csr_osch_tlp_post_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port1_u; + +/* Define the union csr_osch_tlp_post_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port2_u; + +/* Define the union csr_osch_tlp_post_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port3_u; + +/* Define the union csr_osch_tlp_post_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port4_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port0_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port1_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port2_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port3_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port4_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port0_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port1_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port2_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port3_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port4_u; + +/* Define the union csr_osch_int_ceq_credit_port01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_int_ceq_credit_port1 : 9; /* [8:0] */ + u32 rsv_60 : 7; /* [15:9] */ + u32 osch_int_ceq_credit_port0 : 9; /* [24:16] */ + u32 rsv_61 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_int_ceq_credit_port01_u; + +/* Define the union csr_osch_int_ceq_credit_port23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_int_ceq_credit_port3 : 9; /* [8:0] */ + u32 rsv_62 : 7; /* [15:9] */ + u32 osch_int_ceq_credit_port2 : 9; /* [24:16] */ + u32 rsv_63 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_int_ceq_credit_port23_u; + +/* Define the union csr_osch_int_ceq_credit_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_int_ceq_credit_port4 : 9; /* [8:0] */ + u32 rsv_64 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_int_ceq_credit_port4_u; + +/* Define the union csr_osch_esch_dpath_bp_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_bp_q4 : 5; /* [4:0] */ + u32 osch_esch_dpath_bp_q3 : 5; /* [9:5] */ + u32 osch_esch_dpath_bp_q2 : 5; /* [14:10] */ + u32 osch_esch_dpath_bp_q1 : 5; /* [19:15] */ + u32 osch_esch_dpath_bp_q0 : 5; /* [24:20] */ + u32 rsv_65 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_bp_sts_u; + +/* Define the union csr_osch_esch_dpath_q0_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q0_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_66 : 2; /* [7:6] */ + u32 osch_esch_dpath_q0_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_67 : 2; /* [15:14] */ + u32 osch_esch_dpath_q0_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_68 : 2; /* [23:22] */ + u32 osch_esch_dpath_q0_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_69 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q0_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q0_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q0_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_70 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q0_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q1_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q1_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_71 : 2; /* [7:6] */ + u32 osch_esch_dpath_q1_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_72 : 2; /* [15:14] */ + u32 osch_esch_dpath_q1_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_73 : 2; /* [23:22] */ + u32 osch_esch_dpath_q1_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_74 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q1_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q1_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q1_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_75 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q1_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q2_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q2_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 osch_esch_dpath_q2_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 osch_esch_dpath_q2_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_78 : 2; /* [23:22] */ + u32 osch_esch_dpath_q2_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_79 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q2_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q2_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q2_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_80 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q2_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q3_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q3_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_81 : 2; /* [7:6] */ + u32 osch_esch_dpath_q3_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_82 : 2; /* [15:14] */ + u32 osch_esch_dpath_q3_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_83 : 2; /* [23:22] */ + u32 osch_esch_dpath_q3_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_84 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q3_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q3_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q3_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_85 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q3_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q4_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q4_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_86 : 2; /* [7:6] */ + u32 osch_esch_dpath_q4_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_87 : 2; /* [15:14] */ + u32 osch_esch_dpath_q4_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_88 : 2; /* [23:22] */ + u32 osch_esch_dpath_q4_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_89 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q4_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q4_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q4_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_90 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q4_bp_thd1_u; + +/* Define the union csr_osch_perf_watch_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_en : 1; /* [0] */ + u32 rsv_91 : 3; /* [3:1] */ + u32 osch_perf_watch_port_idx : 3; /* [6:4] */ + u32 rsv_92 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_en_u; + +/* Define the union csr_osch_perf_watch_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_period : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_period_u; + +/* Define the union csr_osch_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_byte_u; + +/* Define the union csr_osch_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_tlp_u; + +/* Define the union csr_port_out_sch_dwrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sch_dwrr_weight : 13; /* [12:0] */ + u32 rsv_93 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_out_sch_dwrr_weight_u; + +/* Define the union csr_port_rd_src_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_src_dwrr_weight2 : 16; /* [15:0] */ + u32 rsv_94 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_src_weight1_u; + +/* Define the union csr_port_rd_src_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_src_dwrr_weight0 : 16; /* [15:0] */ + u32 port_rd_src_dwrr_weight1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_src_weight0_u; + +/* Define the union csr_port_rd_dpath_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_dpath_wrr_weight4 : 6; /* [5:0] */ + u32 rsv_95 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_dpath_wrr_weight1_u; + +/* Define the union csr_port_rd_dpath_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_dpath_wrr_weight0 : 6; /* [5:0] */ + u32 rsv_96 : 2; /* [7:6] */ + u32 port_rd_dpath_wrr_weight1 : 6; /* [13:8] */ + u32 rsv_97 : 2; /* [15:14] */ + u32 port_rd_dpath_wrr_weight2 : 6; /* [21:16] */ + u32 rsv_98 : 2; /* [23:22] */ + u32 port_rd_dpath_wrr_weight3 : 6; /* [29:24] */ + u32 rsv_99 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_dpath_wrr_weight0_u; + +/* Define the union csr_port_rd_non_dpath_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_ndpath_wrr_weight4 : 6; /* [5:0] */ + u32 rsv_100 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_non_dpath_wrr_weight1_u; + +/* Define the union csr_port_rd_non_dpath_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_ndpath_wrr_weight0 : 6; /* [5:0] */ + u32 rsv_101 : 2; /* [7:6] */ + u32 port_rd_ndpath_wrr_weight1 : 6; /* [13:8] */ + u32 rsv_102 : 2; /* [15:14] */ + u32 port_rd_ndpath_wrr_weight2 : 6; /* [21:16] */ + u32 rsv_103 : 2; /* [23:22] */ + u32 port_rd_ndpath_wrr_weight3 : 6; /* [29:24] */ + u32 rsv_104 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_non_dpath_wrr_weight0_u; + +/* Define the union csr_port_wr_wrr_weight2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_wr_wrr_weight8 : 6; /* [5:0] */ + u32 rsv_105 : 2; /* [7:6] */ + u32 port_wr_wrr_weight9 : 6; /* [13:8] */ + u32 rsv_106 : 2; /* [15:14] */ + u32 port_wr_wrr_weight10 : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_wr_wrr_weight2_u; + +/* Define the union csr_port_wr_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_wr_wrr_weight4 : 6; /* [5:0] */ + u32 rsv_108 : 2; /* [7:6] */ + u32 port_wr_wrr_weight5 : 6; /* [13:8] */ + u32 rsv_109 : 2; /* [15:14] */ + u32 port_wr_wrr_weight6 : 6; /* [21:16] */ + u32 rsv_110 : 2; /* [23:22] */ + u32 port_wr_wrr_weight7 : 6; /* [29:24] */ + u32 rsv_111 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_wr_wrr_weight1_u; + +/* Define the union csr_port_wr_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_wr_wrr_weight0 : 6; /* [5:0] */ + u32 rsv_112 : 2; /* [7:6] */ + u32 port_wr_wrr_weight1 : 6; /* [13:8] */ + u32 rsv_113 : 2; /* [15:14] */ + u32 port_wr_wrr_weight2 : 6; /* [21:16] */ + u32 rsv_114 : 2; /* [23:22] */ + u32 port_wr_wrr_weight3 : 6; /* [29:24] */ + u32 rsv_115 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_wr_wrr_weight0_u; + +/* Define the union csr_cfg_doorbell_crdt_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_doorbell_crdt_bp_th : 6; /* [5:0] */ + u32 rsv_116 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_doorbell_crdt_bp_th_u; + +/* Define the union csr_doorbell_wr_cmd_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doorbell_wr_cmd_crdt_err : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_doorbell_wr_cmd_crdt_err_u; + +/* Define the union csr_osch_ctrl_doorbell_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ctrl_doorbell_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ctrl_doorbell_cnt_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt0 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt0 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy0 : 1; /* [28] */ + u32 pcie_wr_head_busy0 : 1; /* [29] */ + u32 rsv_118 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt0_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt0 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt0 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy0 : 1; /* [28] */ + u32 pcie_rd_head_busy0 : 1; /* [29] */ + u32 rsv_119 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt0_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt0 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt0 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy0 : 1; /* [28] */ + u32 pcie_cpl_head_busy0 : 1; /* [29] */ + u32 rsv_120 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt0_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt1 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt1 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy1 : 1; /* [28] */ + u32 pcie_wr_head_busy1 : 1; /* [29] */ + u32 rsv_121 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt1_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt1 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt1 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy1 : 1; /* [28] */ + u32 pcie_rd_head_busy1 : 1; /* [29] */ + u32 rsv_122 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt1_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt1 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt1 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy1 : 1; /* [28] */ + u32 pcie_cpl_head_busy1 : 1; /* [29] */ + u32 rsv_123 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt1_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt2 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt2 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy2 : 1; /* [28] */ + u32 pcie_wr_head_busy2 : 1; /* [29] */ + u32 rsv_124 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt2_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt2 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt2 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy2 : 1; /* [28] */ + u32 pcie_rd_head_busy2 : 1; /* [29] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt2_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt2 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt2 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy2 : 1; /* [28] */ + u32 pcie_cpl_head_busy2 : 1; /* [29] */ + u32 rsv_126 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt2_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt3 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt3 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy3 : 1; /* [28] */ + u32 pcie_wr_head_busy3 : 1; /* [29] */ + u32 rsv_127 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt3_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt3 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt3 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy3 : 1; /* [28] */ + u32 pcie_rd_head_busy3 : 1; /* [29] */ + u32 rsv_128 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt3_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt3 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt3 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy3 : 1; /* [28] */ + u32 pcie_cpl_head_busy3 : 1; /* [29] */ + u32 rsv_129 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt3_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt4 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt4 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy4 : 1; /* [28] */ + u32 pcie_wr_head_busy4 : 1; /* [29] */ + u32 rsv_130 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt4_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt4 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt4 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy4 : 1; /* [28] */ + u32 pcie_rd_head_busy4 : 1; /* [29] */ + u32 rsv_131 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt4_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt4 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt4 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy4 : 1; /* [28] */ + u32 pcie_cpl_head_busy4 : 1; /* [29] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt4_u; + +/* Define the union csr_osch_ecc_inj_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_cpld_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_nl2nic_req_mem_inj : 10; /* [19:10] */ + u32 cpi_osch_ceqe_tx_fifo_inj : 10; /* [29:20] */ + u32 rsv_133 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_0_u; + +/* Define the union csr_osch_ecc_inj_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_dpath_q0_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_dpath_q1_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_dpath_q2_fifo_inj : 10; /* [29:20] */ + u32 rsv_134 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_1_u; + +/* Define the union csr_osch_ecc_inj_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_dpath_q3_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_dpath_q4_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_atomic_tx_fifo_inj : 10; /* [29:20] */ + u32 rsv_135 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_2_u; + +/* Define the union csr_osch_ecc_inj_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_cpath_q0_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_cpath_q1_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_cpath_q2_fifo_inj : 10; /* [29:20] */ + u32 rsv_136 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_3_u; + +/* Define the union csr_osch_ecc_inj_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_msi_tx_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_atomic64_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_ceqe_buf_fifo_inj : 2; /* [21:20] */ + u32 cpi_osch_payload_fifo_inj : 2; /* [23:22] */ + u32 cpi_osch_payload_fifo1_inj : 2; /* [25:24] */ + u32 cpi_osch_payload_fifo_hva_inj : 2; /* [27:26] */ + u32 cpi_osch_payload_fifo1_hva_inj : 2; /* [29:28] */ + u32 cpi_osch_doorbell_fifo_inj : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_4_u; + +/* Define the union csr_osch_ecc_inj_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_payload_fifo_np_inj : 2; /* [1:0] */ + u32 cpi_osch_payload_fifo1_np_inj : 2; /* [3:2] */ + u32 cpi_osch_payload_fifo_hva_np_inj : 2; /* [5:4] */ + u32 cpi_osch_payload_fifo1_hva_np_inj : 2; /* [7:6] */ + u32 rsv_137 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_5_u; + +/* Define the union csr_osch_ecc_int_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_nl2nic_req_mem_ecc_err : 10; /* [19:10] */ + u32 osch_ceqe_tx_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_138 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_0_u; + +/* Define the union csr_osch_ecc_int_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_dpath_q1_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_dpath_q2_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_139 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_1_u; + +/* Define the union csr_osch_ecc_int_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_dpath_q4_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_atomic_tx_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_140 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_2_u; + +/* Define the union csr_osch_ecc_int_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_cpath_q1_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_cpath_q2_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_141 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_3_u; + +/* Define the union csr_osch_ecc_int_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_atomic64_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_ceqe_buf_fifo_ecc_err : 2; /* [21:20] */ + u32 osch_payload_fifo_ecc_err : 2; /* [23:22] */ + u32 osch_payload_fifo1_ecc_err : 2; /* [25:24] */ + u32 osch_payload_fifo_hva_ecc_err : 2; /* [27:26] */ + u32 osch_payload_fifo1_hva_ecc_err : 2; /* [29:28] */ + u32 osch_doorbell_fifo_ecc_err : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_4_u; + +/* Define the union csr_osch_ecc_int_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_np_ecc_err : 2; /* [1:0] */ + u32 osch_payload_fifo1_np_ecc_err : 2; /* [3:2] */ + u32 osch_payload_fifo_hva_np_ecc_err : 2; /* [5:4] */ + u32 osch_payload_fifo1_hva_np_ecc_err : 2; /* [7:6] */ + u32 rsv_142 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_5_u; + +/* Define the union csr_osch_ecc_int_en_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_nl2nic_req_mem_ecc_int_en : 10; /* [19:10] */ + u32 osch_ceqe_tx_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_143 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_0_u; + +/* Define the union csr_osch_ecc_int_en_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_dpath_q1_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_dpath_q2_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_144 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_1_u; + +/* Define the union csr_osch_ecc_int_en_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_dpath_q4_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_atomic_tx_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_145 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_2_u; + +/* Define the union csr_osch_ecc_int_en_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_cpath_q1_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_cpath_q2_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_146 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_3_u; + +/* Define the union csr_osch_ecc_int_en_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_atomic64_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_ceqe_buf_fifo_ecc_int_en : 2; /* [21:20] */ + u32 osch_payload_fifo_ecc_int_en : 2; /* [23:22] */ + u32 osch_payload_fifo1_ecc_int_en : 2; /* [25:24] */ + u32 osch_payload_fifo_hva_ecc_int_en : 2; /* [27:26] */ + u32 osch_payload_fifo1_hva_ecc_int_en : 2; /* [29:28] */ + u32 osch_doorbell_fifo_ecc_int_en : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_4_u; + +/* Define the union csr_osch_ecc_int_en_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_np_ecc_int_en : 2; /* [1:0] */ + u32 osch_payload_fifo1_np_ecc_int_en : 2; /* [3:2] */ + u32 osch_payload_fifo_hva_np_ecc_int_en : 2; /* [5:4] */ + u32 osch_payload_fifo1_hva_np_ecc_int_en : 2; /* [7:6] */ + u32 rsv_147 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_5_u; + +/* Define the union csr_osch_ecc_err_addr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo1_ecc_erraddr : 10; /* [9:0] */ + u32 osch_payload_fifo_hva_ecc_erraddr : 10; /* [19:10] */ + u32 osch_payload_fifo1_hva_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_148 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_0_u; + +/* Define the union csr_osch_ecc_err_addr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_port0_ecc_erraddr : 10; /* [9:0] */ + u32 osch_ceqe_buf_ecc_erraddr : 12; /* [21:10] */ + u32 osch_payload_fifo_ecc_erraddr : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_1_u; + +/* Define the union csr_osch_ecc_err_addr_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_port1_ecc_erraddr : 10; /* [9:0] */ + u32 osch_port2_ecc_erraddr : 10; /* [19:10] */ + u32 osch_port3_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_149 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_2_u; + +/* Define the union csr_osch_ecc_err_addr_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_port4_ecc_erraddr : 10; /* [9:0] */ + u32 osch_payload_fifo1_hva_np_ecc_erraddr : 10; /* [19:10] */ + u32 osch_doorbell_fifo_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_150 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_3_u; + +/* Define the union csr_osch_ecc_err_addr_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_np_ecc_erraddr : 10; /* [9:0] */ + u32 osch_payload_fifo1_np_ecc_erraddr : 10; /* [19:10] */ + u32 osch_payload_fifo_hva_np_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_151 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_4_u; + +/* Define the union csr_osch_ecc_err_addr_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ecc_err_addr_port0_sel : 4; /* [3:0] */ + u32 osch_ecc_err_addr_port1_sel : 4; /* [7:4] */ + u32 osch_ecc_err_addr_port2_sel : 4; /* [11:8] */ + u32 osch_ecc_err_addr_port3_sel : 4; /* [15:12] */ + u32 osch_ecc_err_addr_port4_sel : 4; /* [19:16] */ + u32 rsv_152 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_sel_u; + +/* Define the union csr_osch_overflow_int_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic64_tx_fifo_overf : 5; /* [4:0] */ + u32 payload_fifo_hva_overf_np : 1; /* [5] */ + u32 payload_fifo1_hva_overf_np : 1; /* [6] */ + u32 payload_fifo1_overf_np : 1; /* [7] */ + u32 payload_fifo_overf_np : 1; /* [8] */ + u32 payload_fifo_hva_overf : 1; /* [9] */ + u32 payload_fifo1_hva_overf : 1; /* [10] */ + u32 payload_fifo1_overf : 1; /* [11] */ + u32 dbell_fifo_overf : 1; /* [12] */ + u32 payload_fifo_overf : 1; /* [13] */ + u32 rsv_153 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_0_u; + +/* Define the union csr_osch_overflow_int_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_q2_fifo_overf : 5; /* [4:0] */ + u32 cpath_q1_fifo_overf : 5; /* [9:5] */ + u32 cpath_q0_fifo_overf : 5; /* [14:10] */ + u32 ceqe_tx_fifo_overf : 5; /* [19:15] */ + u32 atomic_tx_fifo_overf : 5; /* [24:20] */ + u32 msi_tx_fifo_overf : 5; /* [29:25] */ + u32 rsv_154 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_1_u; + +/* Define the union csr_osch_overflow_int_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpld_fifo_overf : 5; /* [4:0] */ + u32 dpath_q4_fifo_overf : 5; /* [9:5] */ + u32 dpath_q3_fifo_overf : 5; /* [14:10] */ + u32 dpath_q2_fifo_overf : 5; /* [19:15] */ + u32 dpath_q1_fifo_overf : 5; /* [24:20] */ + u32 dpath_q0_fifo_overf : 5; /* [29:25] */ + u32 rsv_155 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_2_u; + +/* Define the union csr_osch_overflow_int_en_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic64_tx_fifo_overf_int_en : 5; /* [4:0] */ + u32 payload_fifo_hva_overf_np_int_en : 1; /* [5] */ + u32 payload_fifo1_hva_overf_np_int_en : 1; /* [6] */ + u32 payload_fifo1_overf_np_int_en : 1; /* [7] */ + u32 payload_fifo_overf_np_int_en : 1; /* [8] */ + u32 payload_fifo_hva_overf_int_en : 1; /* [9] */ + u32 payload_fifo1_hva_overf_int_en : 1; /* [10] */ + u32 payload_fifo1_overf_int_en : 1; /* [11] */ + u32 dbell_fifo_overf_int_en : 1; /* [12] */ + u32 payload_fifo_overf_int_en : 1; /* [13] */ + u32 rsv_156 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_en_0_u; + +/* Define the union csr_osch_overflow_int_en_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_q2_fifo_overf_int_en : 5; /* [4:0] */ + u32 cpath_q1_fifo_overf_int_en : 5; /* [9:5] */ + u32 cpath_q0_fifo_overf_int_en : 5; /* [14:10] */ + u32 ceqe_tx_fifo_overf_int_en : 5; /* [19:15] */ + u32 atomic_tx_fifo_overf_int_en : 5; /* [24:20] */ + u32 msi_tx_fifo_overf_int_en : 5; /* [29:25] */ + u32 rsv_157 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_en_1_u; + +/* Define the union csr_osch_overflow_int_en_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpld_fifo_overf_int_en : 5; /* [4:0] */ + u32 dpath_q4_fifo_overf_int_en : 5; /* [9:5] */ + u32 dpath_q3_fifo_overf_int_en : 5; /* [14:10] */ + u32 dpath_q2_fifo_overf_int_en : 5; /* [19:15] */ + u32 dpath_q1_fifo_overf_int_en : 5; /* [24:20] */ + u32 dpath_q0_fifo_overf_int_en : 5; /* [29:25] */ + u32 rsv_158 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_en_2_u; + +/* Define the union csr_osch_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_port_timeout : 5; /* [4:0] */ + u32 port_sch_tlp_err : 1; /* [5] */ + u32 port_sch_tlp_err_hva : 1; /* [6] */ + u32 port_sch_tlp_err_npcpl : 1; /* [7] */ + u32 port_sch_tlp_err_hva_npcpl : 1; /* [8] */ + u32 cpi_osch_ceqe_drop_req : 1; /* [9] */ + u32 port_sch_phy_addr_err : 1; /* [10] */ + u32 port_sch_phy_addr_err_npcpl : 1; /* [11] */ + u32 rsv_159 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_crt_err_u; + +/* Define the union csr_osch_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dpath_req_drop_p : 5; /* [4:0] */ + u32 cpi_osch_int_ceq_credit_err_p : 5; /* [9:5] */ + u32 osch_loss_sopeop_err : 10; /* [19:10] */ + u32 rsv_160 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_uncrt_err_u; + +/* Define the union csr_osch_crt_err_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_port_timeout_int_en : 5; /* [4:0] */ + u32 port_sch_tlp_err_int_en : 1; /* [5] */ + u32 port_sch_tlp_err_hva_int_en : 1; /* [6] */ + u32 port_sch_tlp_err_npcpl_int_en : 1; /* [7] */ + u32 port_sch_tlp_err_hva_npcpl_int_en : 1; /* [8] */ + u32 cpi_osch_ceqe_drop_req_int_en : 1; /* [9] */ + u32 port_sch_phy_addr_err_int_en : 1; /* [10] */ + u32 port_sch_phy_addr_err_npcpl_int_en : 1; /* [11] */ + u32 rsv_161 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_crt_err_int_en_u; + +/* Define the union csr_osch_uncrt_err_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dpath_req_drop_p_int_en : 5; /* [4:0] */ + u32 cpi_osch_int_ceq_credit_err_p_int_en : 5; /* [9:5] */ + u32 osch_loss_sopeop_err_int_en : 10; /* [19:10] */ + u32 rsv_162 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_uncrt_err_int_en_u; + +/* Define the union csr_osch_active_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 active_en_cfg_value : 5; /* [4:0] */ + u32 active_en_cfg_enable : 5; /* [9:5] */ + u32 rsv_163 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_active_en_cfg_u; + +/* Define the union csr_osch_nl2nic_outstanding_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_non_l2nic_outstanding_bp_th : 15; /* [14:0] */ + u32 rsv_164 : 1; /* [15] */ + u32 cfg_non_l2nic_outstanding_bp_en : 5; /* [20:16] */ + u32 rsv_165 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_nl2nic_outstanding_bp_cfg_u; + +/* Define the union csr_ceq_cls_fifo_st_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_cls_fifo_st_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_cls_fifo_st_err_u; + +/* Define the union csr_glb_cqe_ci_d_chl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ceqe_sch_period : 8; /* [7:0] */ + u32 glb_osch_non_l2nic_outstanding_cfg : 2; /* [9:8] */ + u32 rsv_166 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cqe_ci_d_chl_u; + +/* Define the union csr_glb_dma_so_ro_replace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dma_so_ro_cfg : 2; /* [1:0] */ + u32 rsv_167 : 2; /* [3:2] */ + u32 glb_dma_so_ro_replace_mode : 1; /* [4] */ + u32 rsv_168 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dma_so_ro_replace_u; + +/* Define the union csr_glb_osch_rls_tag_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_rls_tag_en : 1; /* [0] */ + u32 rsv_169 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_rls_tag_en_u; + +/* Define the union csr_glb_osch_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_timeout_cfg : 15; /* [14:0] */ + u32 rsv_170 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_timeout_u; + +/* Define the union csr_glb_cp_cqe_credit_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port4_cqe_credit_cfg : 2; /* [1:0] */ + u32 rsv_171 : 2; /* [3:2] */ + u32 port3_cqe_credit_cfg : 2; /* [5:4] */ + u32 rsv_172 : 2; /* [7:6] */ + u32 port2_cqe_credit_cfg : 2; /* [9:8] */ + u32 rsv_173 : 2; /* [11:10] */ + u32 port1_cqe_credit_cfg : 2; /* [13:12] */ + u32 rsv_174 : 2; /* [15:14] */ + u32 port0_cqe_credit_cfg : 2; /* [17:16] */ + u32 rsv_175 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cp_cqe_credit_port_u; + +/* Define the union csr_glb_osch_addr_hi_lmt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_hi_lmt_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_hi_lmt_h_u; + +/* Define the union csr_glb_osch_addr_hi_lmt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_hi_lmt_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_hi_lmt_l_u; + +/* Define the union csr_glb_osch_addr_lo_lmt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_lo_lmt_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_lo_lmt_h_u; + +/* Define the union csr_glb_osch_addr_lo_lmt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_lo_lmt_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_lo_lmt_l_u; + +/* Define the union csr_glb_osch_addr_out_range_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_out_range_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_out_range_h_u; + +/* Define the union csr_glb_osch_addr_out_range_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_out_range_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_out_range_l_u; + +/* Define the union csr_osch_payload_fifo1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo1_ctrl_all_port : 7; /* [6:0] */ + u32 rsv_176 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_payload_fifo1_ctrl_u; + +/* Define the union csr_osch_dbell_fifo_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dbell_fifo_ctrl_all_port : 7; /* [6:0] */ + u32 rsv_177 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dbell_fifo_ctrl_u; + +/* Define the union csr_cfg_doorbell_wr_cmd_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_doorbell_wr_cmd_en : 5; /* [4:0] */ + u32 rsv_178 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_doorbell_wr_cmd_en_u; + +/* Define the union csr_cfg_doorbell_crdt_initial_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_doorbell_crdt_initial : 5; /* [4:0] */ + u32 rsv_179 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_doorbell_crdt_initial_u; + +/* Define the union csr_cfg_dpath_xts_rd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dpath_xts_rd_chl : 5; /* [4:0] */ + u32 cfg_dpath_xts_rd_en : 1; /* [5] */ + u32 rsv_180 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_dpath_xts_rd_u; + +/* Define the union csr_cfg_round_bit_check_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_round_bit_check_mod : 1; /* [0] */ + u32 rsv_181 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_round_bit_check_mod_u; + +/* Define the union csr_cfg_port1_to_port0_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port1_to_port0_mode : 1; /* [0] */ + u32 rsv_182 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_port1_to_port0_mode_u; + +/* Define the union csr_cfg_non_l2nic_loop2_edge_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_non_l2nic_loop2_edge_en : 1; /* [0] */ + u32 rsv_183 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_non_l2nic_loop2_edge_en_u; + +/* Define the union csr_cfg_cur_cpl_timeout_drop_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cur_cpl_timeout_drop_max : 20; /* [19:0] */ + u32 rsv_184 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_cur_cpl_timeout_drop_max_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port0_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port1_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port2_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port3_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port4_u; + +/* Define the union csr_osch_tlp_npcpl_error_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_err_count_port3 : 8; /* [7:0] */ + u32 osch_tlp_npcpl_err_count_port2 : 8; /* [15:8] */ + u32 osch_tlp_npcpl_err_count_port1 : 8; /* [23:16] */ + u32 osch_tlp_npcpl_err_count_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_error_cnt0_u; + +/* Define the union csr_osch_tlp_npcpl_error_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_err_count_port4 : 8; /* [7:0] */ + u32 rsv_185 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_error_cnt1_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt0_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt1_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt2_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt3_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt4_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt5_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt6_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt7_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt8_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt9_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt10_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt11_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt12_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt13_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt14_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt15_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt0_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt1_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt2_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt3_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt4_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt5_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt6_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt7_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt8_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt9_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt10_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt11_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt12_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt13_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt14_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt15_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt0_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt1_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt2_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt3_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt4_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt5_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt6_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt7_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt8_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt9_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt10_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt11_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt12_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt13_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt14_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt15_u; + +/* Define the union csr_osch_tlp_drop_count_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_mode : 16; /* [15:0] */ + u32 rsv_186 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_count_mode_u; + +/* Define the union csr_osch_npcpl_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_npcpl_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_npcpl_perf_watch_byte_u; + +/* Define the union csr_osch_npcpl_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_npcpl_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_npcpl_perf_watch_tlp_u; + +/* Define the union csr_osch_hva_p_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_p_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_p_perf_watch_byte_u; + +/* Define the union csr_osch_hva_p_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_p_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_p_perf_watch_tlp_u; + +/* Define the union csr_osch_hva_npcpl_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_npcpl_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_npcpl_perf_watch_byte_u; + +/* Define the union csr_osch_hva_npcpl_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_npcpl_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_npcpl_perf_watch_tlp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_osch_tlp_drop_cnt_port0_u osch_tlp_drop_cnt_port0; /* 0 */ + volatile csr_osch_tlp_drop_cnt_port1_u osch_tlp_drop_cnt_port1; /* 4 */ + volatile csr_osch_tlp_drop_cnt_port2_u osch_tlp_drop_cnt_port2; /* 8 */ + volatile csr_osch_tlp_drop_cnt_port3_u osch_tlp_drop_cnt_port3; /* C */ + volatile csr_osch_tlp_drop_cnt_port4_u osch_tlp_drop_cnt_port4; /* 10 */ + volatile csr_osch_tlp_error_cnt0_u osch_tlp_error_cnt0; /* 14 */ + volatile csr_osch_tlp_error_cnt1_u osch_tlp_error_cnt1; /* 18 */ + volatile csr_osch_tlp_drop_cnt0_u osch_tlp_drop_cnt0; /* 20 */ + volatile csr_osch_tlp_drop_cnt1_u osch_tlp_drop_cnt1; /* 24 */ + volatile csr_osch_tlp_drop_cnt2_u osch_tlp_drop_cnt2; /* 28 */ + volatile csr_osch_tlp_drop_cnt3_u osch_tlp_drop_cnt3; /* 2C */ + volatile csr_osch_tlp_drop_cnt4_u osch_tlp_drop_cnt4; /* 30 */ + volatile csr_osch_tlp_drop_cnt5_u osch_tlp_drop_cnt5; /* 34 */ + volatile csr_osch_tlp_drop_cnt6_u osch_tlp_drop_cnt6; /* 38 */ + volatile csr_osch_tlp_drop_cnt7_u osch_tlp_drop_cnt7; /* 3C */ + volatile csr_osch_tlp_drop_cnt8_u osch_tlp_drop_cnt8; /* 40 */ + volatile csr_osch_tlp_drop_cnt9_u osch_tlp_drop_cnt9; /* 44 */ + volatile csr_osch_tlp_drop_cnt10_u osch_tlp_drop_cnt10; /* 48 */ + volatile csr_osch_tlp_drop_cnt11_u osch_tlp_drop_cnt11; /* 4C */ + volatile csr_osch_tlp_drop_cnt12_u osch_tlp_drop_cnt12; /* 50 */ + volatile csr_osch_tlp_drop_cnt13_u osch_tlp_drop_cnt13; /* 54 */ + volatile csr_osch_tlp_drop_cnt14_u osch_tlp_drop_cnt14; /* 58 */ + volatile csr_osch_tlp_drop_cnt15_u osch_tlp_drop_cnt15; /* 5C */ + volatile csr_osch_tlp_drop_func01_u osch_tlp_drop_func01; /* 60 */ + volatile csr_osch_tlp_drop_func23_u osch_tlp_drop_func23; /* 64 */ + volatile csr_osch_tlp_drop_func45_u osch_tlp_drop_func45; /* 68 */ + volatile csr_osch_tlp_drop_func67_u osch_tlp_drop_func67; /* 6C */ + volatile csr_osch_tlp_drop_func89_u osch_tlp_drop_func89; /* 70 */ + volatile csr_osch_tlp_drop_func1011_u osch_tlp_drop_func1011; /* 74 */ + volatile csr_osch_tlp_drop_func1213_u osch_tlp_drop_func1213; /* 78 */ + volatile csr_osch_tlp_drop_func1415_u osch_tlp_drop_func1415; /* 7C */ + volatile csr_osch_ceqe_drop_cnt_u osch_ceqe_drop_cnt; /* 90 */ + volatile csr_osch_ceqe_pi_overflow_u osch_ceqe_pi_overflow; /* 94 */ + volatile csr_osch_fifo_overflow_low_u osch_fifo_overflow_low; /* 98 */ + volatile csr_osch_req_timeout_u osch_req_timeout; /* 9C */ + volatile csr_osch_fifo_empt_high_u osch_fifo_empt_high; /* A0 */ + volatile csr_osch_fifo_empt_low_u osch_fifo_empt_low; /* A4 */ + volatile csr_osch_fifo_afull_high_u osch_fifo_afull_high; /* A8 */ + volatile csr_osch_fifo_afull_low_u osch_fifo_afull_low; /* AC */ + volatile csr_osch_payload_fifo_ctrl_u osch_payload_fifo_ctrl; /* B0 */ + volatile csr_osch_msi_tx_fifo_ctrl0_u osch_msi_tx_fifo_ctrl0; /* B4 */ + volatile csr_osch_msi_tx_fifo_ctrl1_u osch_msi_tx_fifo_ctrl1; /* B8 */ + volatile csr_osch_atomic_tx_fifo_ctrl0_u osch_atomic_tx_fifo_ctrl0; /* BC */ + volatile csr_osch_atomic_tx_fifo_ctrl1_u osch_atomic_tx_fifo_ctrl1; /* C0 */ + volatile csr_osch_ceqe_tx_fifo_ctrl0_u osch_ceqe_tx_fifo_ctrl0; /* C4 */ + volatile csr_osch_ceqe_tx_fifo_ctrl1_u osch_ceqe_tx_fifo_ctrl1; /* C8 */ + volatile csr_osch_cpld_tx_fifo_ctrl0_u osch_cpld_tx_fifo_ctrl0; /* D0 */ + volatile csr_osch_cpld_tx_fifo_ctrl1_u osch_cpld_tx_fifo_ctrl1; /* D4 */ + volatile csr_osch_fifo_empt_tophigh_u osch_fifo_empt_tophigh; /* D8 */ + volatile csr_osch_fifo_afull_tophigh_u osch_fifo_afull_tophigh; /* DC */ + volatile csr_osch_cpath_q0_fifo_ctrl0_u osch_cpath_q0_fifo_ctrl0; /* F0 */ + volatile csr_osch_cpath_q0_fifo_ctrl1_u osch_cpath_q0_fifo_ctrl1; /* F4 */ + volatile csr_osch_cpath_q1_fifo_ctrl0_u osch_cpath_q1_fifo_ctrl0; /* 100 */ + volatile csr_osch_cpath_q1_fifo_ctrl1_u osch_cpath_q1_fifo_ctrl1; /* 104 */ + volatile csr_osch_cpath_q2_fifo_ctrl0_u osch_cpath_q2_fifo_ctrl0; /* 110 */ + volatile csr_osch_cpath_q2_fifo_ctrl1_u osch_cpath_q2_fifo_ctrl1; /* 114 */ + volatile csr_osch_dpath_q0_fifo_ctrl0_u osch_dpath_q0_fifo_ctrl0; /* 120 */ + volatile csr_osch_dpath_q0_fifo_ctrl1_u osch_dpath_q0_fifo_ctrl1; /* 124 */ + volatile csr_osch_dpath_q1_fifo_ctrl0_u osch_dpath_q1_fifo_ctrl0; /* 130 */ + volatile csr_osch_dpath_q1_fifo_ctrl1_u osch_dpath_q1_fifo_ctrl1; /* 134 */ + volatile csr_osch_dpath_q2_fifo_ctrl0_u osch_dpath_q2_fifo_ctrl0; /* 140 */ + volatile csr_osch_dpath_q2_fifo_ctrl1_u osch_dpath_q2_fifo_ctrl1; /* 144 */ + volatile csr_osch_dpath_q3_fifo_ctrl0_u osch_dpath_q3_fifo_ctrl0; /* 150 */ + volatile csr_osch_dpath_q3_fifo_ctrl1_u osch_dpath_q3_fifo_ctrl1; /* 154 */ + volatile csr_osch_dpath_q4_fifo_ctrl0_u osch_dpath_q4_fifo_ctrl0; /* 160 */ + volatile csr_osch_dpath_q4_fifo_ctrl1_u osch_dpath_q4_fifo_ctrl1; /* 164 */ + volatile csr_osch_reserved0_u osch_reserved0; /* 170 */ + volatile csr_osch_reserved1_u osch_reserved1; /* 174 */ + volatile csr_osch_reserved2_u osch_reserved2; /* 178 */ + volatile csr_glb_post_head_credit_u glb_post_head_credit; /* 180 */ + volatile csr_glb_post_payload_credit_h_u glb_post_payload_credit_h; /* 184 */ + volatile csr_glb_post_payload_credit_l_u glb_post_payload_credit_l; /* 188 */ + volatile csr_glb_non_post_head_credit_u glb_non_post_head_credit; /* 190 */ + volatile csr_glb_non_post_payload_credit_h_u glb_non_post_payload_credit_h; /* 194 */ + volatile csr_glb_non_post_payload_credit_l_u glb_non_post_payload_credit_l; /* 198 */ + volatile csr_glb_cpl_head_credit_u glb_cpl_head_credit; /* 1A0 */ + volatile csr_glb_cpl_payload_credit_h_u glb_cpl_payload_credit_h; /* 1A4 */ + volatile csr_glb_cpl_payload_credit_l_u glb_cpl_payload_credit_l; /* 1A8 */ + volatile csr_glb_osch_ceqe_in_cnt_u glb_osch_ceqe_in_cnt; /* 1B0 */ + volatile csr_glb_osch_ceqe_out_cnt_u glb_osch_ceqe_out_cnt; /* 1B4 */ + volatile csr_glb_ceqe_drop_tail_u glb_ceqe_drop_tail; /* 1C0 */ + volatile csr_osch_tlp_post_cnt_port0_u osch_tlp_post_cnt_port0; /* 1D0 */ + volatile csr_osch_tlp_post_cnt_port1_u osch_tlp_post_cnt_port1; /* 1D4 */ + volatile csr_osch_tlp_post_cnt_port2_u osch_tlp_post_cnt_port2; /* 1D8 */ + volatile csr_osch_tlp_post_cnt_port3_u osch_tlp_post_cnt_port3; /* 1DC */ + volatile csr_osch_tlp_post_cnt_port4_u osch_tlp_post_cnt_port4; /* 1E0 */ + volatile csr_osch_tlp_non_post_cnt_port0_u osch_tlp_non_post_cnt_port0; /* 1F0 */ + volatile csr_osch_tlp_non_post_cnt_port1_u osch_tlp_non_post_cnt_port1; /* 1F4 */ + volatile csr_osch_tlp_non_post_cnt_port2_u osch_tlp_non_post_cnt_port2; /* 1F8 */ + volatile csr_osch_tlp_non_post_cnt_port3_u osch_tlp_non_post_cnt_port3; /* 1FC */ + volatile csr_osch_tlp_non_post_cnt_port4_u osch_tlp_non_post_cnt_port4; /* 200 */ + volatile csr_osch_tlp_cpl_cnt_port0_u osch_tlp_cpl_cnt_port0; /* 210 */ + volatile csr_osch_tlp_cpl_cnt_port1_u osch_tlp_cpl_cnt_port1; /* 214 */ + volatile csr_osch_tlp_cpl_cnt_port2_u osch_tlp_cpl_cnt_port2; /* 218 */ + volatile csr_osch_tlp_cpl_cnt_port3_u osch_tlp_cpl_cnt_port3; /* 21C */ + volatile csr_osch_tlp_cpl_cnt_port4_u osch_tlp_cpl_cnt_port4; /* 220 */ + volatile csr_osch_int_ceq_credit_port01_u osch_int_ceq_credit_port01; /* 230 */ + volatile csr_osch_int_ceq_credit_port23_u osch_int_ceq_credit_port23; /* 234 */ + volatile csr_osch_int_ceq_credit_port4_u osch_int_ceq_credit_port4; /* 238 */ + volatile csr_osch_esch_dpath_bp_sts_u osch_esch_dpath_bp_sts; /* 240 */ + volatile csr_osch_esch_dpath_q0_bp_thd0_u osch_esch_dpath_q0_bp_thd0; /* 250 */ + volatile csr_osch_esch_dpath_q0_bp_thd1_u osch_esch_dpath_q0_bp_thd1; /* 254 */ + volatile csr_osch_esch_dpath_q1_bp_thd0_u osch_esch_dpath_q1_bp_thd0; /* 260 */ + volatile csr_osch_esch_dpath_q1_bp_thd1_u osch_esch_dpath_q1_bp_thd1; /* 264 */ + volatile csr_osch_esch_dpath_q2_bp_thd0_u osch_esch_dpath_q2_bp_thd0; /* 270 */ + volatile csr_osch_esch_dpath_q2_bp_thd1_u osch_esch_dpath_q2_bp_thd1; /* 274 */ + volatile csr_osch_esch_dpath_q3_bp_thd0_u osch_esch_dpath_q3_bp_thd0; /* 280 */ + volatile csr_osch_esch_dpath_q3_bp_thd1_u osch_esch_dpath_q3_bp_thd1; /* 284 */ + volatile csr_osch_esch_dpath_q4_bp_thd0_u osch_esch_dpath_q4_bp_thd0; /* 290 */ + volatile csr_osch_esch_dpath_q4_bp_thd1_u osch_esch_dpath_q4_bp_thd1; /* 294 */ + volatile csr_osch_perf_watch_en_u osch_perf_watch_en; /* 298 */ + volatile csr_osch_perf_watch_period_u osch_perf_watch_period; /* 2A0 */ + volatile csr_osch_perf_watch_byte_u osch_perf_watch_byte; /* 2A4 */ + volatile csr_osch_perf_watch_tlp_u osch_perf_watch_tlp; /* 2A8 */ + volatile csr_port_out_sch_dwrr_weight_u port_out_sch_dwrr_weight[5]; /* 300 */ + volatile csr_port_rd_src_weight1_u port_rd_src_weight1[5]; /* 304 */ + volatile csr_port_rd_src_weight0_u port_rd_src_weight0[5]; /* 308 */ + volatile csr_port_rd_dpath_wrr_weight1_u port_rd_dpath_wrr_weight1[5]; /* 30C */ + volatile csr_port_rd_dpath_wrr_weight0_u port_rd_dpath_wrr_weight0[5]; /* 310 */ + volatile csr_port_rd_non_dpath_wrr_weight1_u port_rd_non_dpath_wrr_weight1[5]; /* 314 */ + volatile csr_port_rd_non_dpath_wrr_weight0_u port_rd_non_dpath_wrr_weight0[5]; /* 318 */ + volatile csr_port_wr_wrr_weight2_u port_wr_wrr_weight2[5]; /* 320 */ + volatile csr_port_wr_wrr_weight1_u port_wr_wrr_weight1[5]; /* 324 */ + volatile csr_port_wr_wrr_weight0_u port_wr_wrr_weight0[5]; /* 328 */ + volatile csr_cfg_doorbell_crdt_bp_th_u cfg_doorbell_crdt_bp_th[5]; /* 32C */ + volatile csr_doorbell_wr_cmd_crdt_err_u doorbell_wr_cmd_crdt_err[5]; /* 330 */ + volatile csr_osch_ctrl_doorbell_cnt_u osch_ctrl_doorbell_cnt; /* 500 */ + volatile csr_pcie_wr_payload_crdt_cnt0_u pcie_wr_payload_crdt_cnt0; /* 504 */ + volatile csr_pcie_rd_payload_crdt_cnt0_u pcie_rd_payload_crdt_cnt0; /* 508 */ + volatile csr_pcie_cpl_payload_crdt_cnt0_u pcie_cpl_payload_crdt_cnt0; /* 50C */ + volatile csr_pcie_wr_payload_crdt_cnt1_u pcie_wr_payload_crdt_cnt1; /* 510 */ + volatile csr_pcie_rd_payload_crdt_cnt1_u pcie_rd_payload_crdt_cnt1; /* 514 */ + volatile csr_pcie_cpl_payload_crdt_cnt1_u pcie_cpl_payload_crdt_cnt1; /* 518 */ + volatile csr_pcie_wr_payload_crdt_cnt2_u pcie_wr_payload_crdt_cnt2; /* 51C */ + volatile csr_pcie_rd_payload_crdt_cnt2_u pcie_rd_payload_crdt_cnt2; /* 520 */ + volatile csr_pcie_cpl_payload_crdt_cnt2_u pcie_cpl_payload_crdt_cnt2; /* 524 */ + volatile csr_pcie_wr_payload_crdt_cnt3_u pcie_wr_payload_crdt_cnt3; /* 528 */ + volatile csr_pcie_rd_payload_crdt_cnt3_u pcie_rd_payload_crdt_cnt3; /* 52C */ + volatile csr_pcie_cpl_payload_crdt_cnt3_u pcie_cpl_payload_crdt_cnt3; /* 530 */ + volatile csr_pcie_wr_payload_crdt_cnt4_u pcie_wr_payload_crdt_cnt4; /* 534 */ + volatile csr_pcie_rd_payload_crdt_cnt4_u pcie_rd_payload_crdt_cnt4; /* 538 */ + volatile csr_pcie_cpl_payload_crdt_cnt4_u pcie_cpl_payload_crdt_cnt4; /* 53C */ + volatile csr_osch_ecc_inj_0_u osch_ecc_inj_0; /* 540 */ + volatile csr_osch_ecc_inj_1_u osch_ecc_inj_1; /* 544 */ + volatile csr_osch_ecc_inj_2_u osch_ecc_inj_2; /* 548 */ + volatile csr_osch_ecc_inj_3_u osch_ecc_inj_3; /* 54C */ + volatile csr_osch_ecc_inj_4_u osch_ecc_inj_4; /* 550 */ + volatile csr_osch_ecc_inj_5_u osch_ecc_inj_5; /* 554 */ + volatile csr_osch_ecc_int_0_u osch_ecc_int_0; /* 558 */ + volatile csr_osch_ecc_int_1_u osch_ecc_int_1; /* 55C */ + volatile csr_osch_ecc_int_2_u osch_ecc_int_2; /* 560 */ + volatile csr_osch_ecc_int_3_u osch_ecc_int_3; /* 564 */ + volatile csr_osch_ecc_int_4_u osch_ecc_int_4; /* 568 */ + volatile csr_osch_ecc_int_5_u osch_ecc_int_5; /* 56C */ + volatile csr_osch_ecc_int_en_0_u osch_ecc_int_en_0; /* 570 */ + volatile csr_osch_ecc_int_en_1_u osch_ecc_int_en_1; /* 574 */ + volatile csr_osch_ecc_int_en_2_u osch_ecc_int_en_2; /* 578 */ + volatile csr_osch_ecc_int_en_3_u osch_ecc_int_en_3; /* 57C */ + volatile csr_osch_ecc_int_en_4_u osch_ecc_int_en_4; /* 580 */ + volatile csr_osch_ecc_int_en_5_u osch_ecc_int_en_5; /* 584 */ + volatile csr_osch_ecc_err_addr_0_u osch_ecc_err_addr_0; /* 588 */ + volatile csr_osch_ecc_err_addr_1_u osch_ecc_err_addr_1; /* 58C */ + volatile csr_osch_ecc_err_addr_2_u osch_ecc_err_addr_2; /* 590 */ + volatile csr_osch_ecc_err_addr_3_u osch_ecc_err_addr_3; /* 594 */ + volatile csr_osch_ecc_err_addr_4_u osch_ecc_err_addr_4; /* 598 */ + volatile csr_osch_ecc_err_addr_sel_u osch_ecc_err_addr_sel; /* 59C */ + volatile csr_osch_overflow_int_0_u osch_overflow_int_0; /* 5A0 */ + volatile csr_osch_overflow_int_1_u osch_overflow_int_1; /* 5A4 */ + volatile csr_osch_overflow_int_2_u osch_overflow_int_2; /* 5A8 */ + volatile csr_osch_overflow_int_en_0_u osch_overflow_int_en_0; /* 5AC */ + volatile csr_osch_overflow_int_en_1_u osch_overflow_int_en_1; /* 5B0 */ + volatile csr_osch_overflow_int_en_2_u osch_overflow_int_en_2; /* 5B4 */ + volatile csr_osch_crt_err_u osch_crt_err; /* 5B8 */ + volatile csr_osch_uncrt_err_u osch_uncrt_err; /* 5BC */ + volatile csr_osch_crt_err_int_en_u osch_crt_err_int_en; /* 5C0 */ + volatile csr_osch_uncrt_err_int_en_u osch_uncrt_err_int_en; /* 5C4 */ + volatile csr_osch_active_en_cfg_u osch_active_en_cfg; /* 5C8 */ + volatile csr_osch_nl2nic_outstanding_bp_cfg_u osch_nl2nic_outstanding_bp_cfg; /* 5CC */ + volatile csr_ceq_cls_fifo_st_err_u ceq_cls_fifo_st_err; /* 600 */ + volatile csr_glb_cqe_ci_d_chl_u glb_cqe_ci_d_chl; /* 604 */ + volatile csr_glb_dma_so_ro_replace_u glb_dma_so_ro_replace; /* 608 */ + volatile csr_glb_osch_rls_tag_en_u glb_osch_rls_tag_en; /* 60C */ + volatile csr_glb_osch_timeout_u glb_osch_timeout; /* 610 */ + volatile csr_glb_cp_cqe_credit_port_u glb_cp_cqe_credit_port; /* 614 */ + volatile csr_glb_osch_addr_hi_lmt_h_u glb_osch_addr_hi_lmt_h; /* 618 */ + volatile csr_glb_osch_addr_hi_lmt_l_u glb_osch_addr_hi_lmt_l; /* 61C */ + volatile csr_glb_osch_addr_lo_lmt_h_u glb_osch_addr_lo_lmt_h; /* 620 */ + volatile csr_glb_osch_addr_lo_lmt_l_u glb_osch_addr_lo_lmt_l; /* 624 */ + volatile csr_glb_osch_addr_out_range_h_u glb_osch_addr_out_range_h; /* 628 */ + volatile csr_glb_osch_addr_out_range_l_u glb_osch_addr_out_range_l; /* 62C */ + volatile csr_osch_payload_fifo1_ctrl_u osch_payload_fifo1_ctrl; /* 630 */ + volatile csr_osch_dbell_fifo_ctrl_u osch_dbell_fifo_ctrl; /* 634 */ + volatile csr_cfg_doorbell_wr_cmd_en_u cfg_doorbell_wr_cmd_en; /* 638 */ + volatile csr_cfg_doorbell_crdt_initial_u cfg_doorbell_crdt_initial; /* 63C */ + volatile csr_cfg_dpath_xts_rd_u cfg_dpath_xts_rd; /* 640 */ + volatile csr_cfg_round_bit_check_mod_u cfg_round_bit_check_mod; /* 650 */ + volatile csr_cfg_port1_to_port0_mode_u cfg_port1_to_port0_mode; /* 660 */ + volatile csr_cfg_non_l2nic_loop2_edge_en_u cfg_non_l2nic_loop2_edge_en; /* 670 */ + volatile csr_cfg_cur_cpl_timeout_drop_max_u cfg_cur_cpl_timeout_drop_max; /* 674 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port0_u osch_tlp_npcpl_drop_cnt_port0; /* 700 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port1_u osch_tlp_npcpl_drop_cnt_port1; /* 704 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port2_u osch_tlp_npcpl_drop_cnt_port2; /* 708 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port3_u osch_tlp_npcpl_drop_cnt_port3; /* 70C */ + volatile csr_osch_tlp_npcpl_drop_cnt_port4_u osch_tlp_npcpl_drop_cnt_port4; /* 710 */ + volatile csr_osch_tlp_npcpl_error_cnt0_u osch_tlp_npcpl_error_cnt0; /* 714 */ + volatile csr_osch_tlp_npcpl_error_cnt1_u osch_tlp_npcpl_error_cnt1; /* 718 */ + volatile csr_osch_tlp_npcpl_drop_cnt0_u osch_tlp_npcpl_drop_cnt0; /* 720 */ + volatile csr_osch_tlp_npcpl_drop_cnt1_u osch_tlp_npcpl_drop_cnt1; /* 724 */ + volatile csr_osch_tlp_npcpl_drop_cnt2_u osch_tlp_npcpl_drop_cnt2; /* 728 */ + volatile csr_osch_tlp_npcpl_drop_cnt3_u osch_tlp_npcpl_drop_cnt3; /* 72C */ + volatile csr_osch_tlp_npcpl_drop_cnt4_u osch_tlp_npcpl_drop_cnt4; /* 730 */ + volatile csr_osch_tlp_npcpl_drop_cnt5_u osch_tlp_npcpl_drop_cnt5; /* 734 */ + volatile csr_osch_tlp_npcpl_drop_cnt6_u osch_tlp_npcpl_drop_cnt6; /* 738 */ + volatile csr_osch_tlp_npcpl_drop_cnt7_u osch_tlp_npcpl_drop_cnt7; /* 73C */ + volatile csr_osch_tlp_npcpl_drop_cnt8_u osch_tlp_npcpl_drop_cnt8; /* 740 */ + volatile csr_osch_tlp_npcpl_drop_cnt9_u osch_tlp_npcpl_drop_cnt9; /* 744 */ + volatile csr_osch_tlp_npcpl_drop_cnt10_u osch_tlp_npcpl_drop_cnt10; /* 748 */ + volatile csr_osch_tlp_npcpl_drop_cnt11_u osch_tlp_npcpl_drop_cnt11; /* 74C */ + volatile csr_osch_tlp_npcpl_drop_cnt12_u osch_tlp_npcpl_drop_cnt12; /* 750 */ + volatile csr_osch_tlp_npcpl_drop_cnt13_u osch_tlp_npcpl_drop_cnt13; /* 754 */ + volatile csr_osch_tlp_npcpl_drop_cnt14_u osch_tlp_npcpl_drop_cnt14; /* 758 */ + volatile csr_osch_tlp_npcpl_drop_cnt15_u osch_tlp_npcpl_drop_cnt15; /* 75C */ + volatile csr_osch_tlp_hva_p_drop_cnt0_u osch_tlp_hva_p_drop_cnt0; /* 760 */ + volatile csr_osch_tlp_hva_p_drop_cnt1_u osch_tlp_hva_p_drop_cnt1; /* 764 */ + volatile csr_osch_tlp_hva_p_drop_cnt2_u osch_tlp_hva_p_drop_cnt2; /* 768 */ + volatile csr_osch_tlp_hva_p_drop_cnt3_u osch_tlp_hva_p_drop_cnt3; /* 76C */ + volatile csr_osch_tlp_hva_p_drop_cnt4_u osch_tlp_hva_p_drop_cnt4; /* 770 */ + volatile csr_osch_tlp_hva_p_drop_cnt5_u osch_tlp_hva_p_drop_cnt5; /* 774 */ + volatile csr_osch_tlp_hva_p_drop_cnt6_u osch_tlp_hva_p_drop_cnt6; /* 778 */ + volatile csr_osch_tlp_hva_p_drop_cnt7_u osch_tlp_hva_p_drop_cnt7; /* 77C */ + volatile csr_osch_tlp_hva_p_drop_cnt8_u osch_tlp_hva_p_drop_cnt8; /* 780 */ + volatile csr_osch_tlp_hva_p_drop_cnt9_u osch_tlp_hva_p_drop_cnt9; /* 784 */ + volatile csr_osch_tlp_hva_p_drop_cnt10_u osch_tlp_hva_p_drop_cnt10; /* 788 */ + volatile csr_osch_tlp_hva_p_drop_cnt11_u osch_tlp_hva_p_drop_cnt11; /* 78C */ + volatile csr_osch_tlp_hva_p_drop_cnt12_u osch_tlp_hva_p_drop_cnt12; /* 790 */ + volatile csr_osch_tlp_hva_p_drop_cnt13_u osch_tlp_hva_p_drop_cnt13; /* 794 */ + volatile csr_osch_tlp_hva_p_drop_cnt14_u osch_tlp_hva_p_drop_cnt14; /* 798 */ + volatile csr_osch_tlp_hva_p_drop_cnt15_u osch_tlp_hva_p_drop_cnt15; /* 79C */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt0_u osch_tlp_hva_npcpl_drop_cnt0; /* 7A0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt1_u osch_tlp_hva_npcpl_drop_cnt1; /* 7A4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt2_u osch_tlp_hva_npcpl_drop_cnt2; /* 7A8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt3_u osch_tlp_hva_npcpl_drop_cnt3; /* 7AC */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt4_u osch_tlp_hva_npcpl_drop_cnt4; /* 7B0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt5_u osch_tlp_hva_npcpl_drop_cnt5; /* 7B4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt6_u osch_tlp_hva_npcpl_drop_cnt6; /* 7B8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt7_u osch_tlp_hva_npcpl_drop_cnt7; /* 7BC */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt8_u osch_tlp_hva_npcpl_drop_cnt8; /* 7C0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt9_u osch_tlp_hva_npcpl_drop_cnt9; /* 7C4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt10_u osch_tlp_hva_npcpl_drop_cnt10; /* 7C8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt11_u osch_tlp_hva_npcpl_drop_cnt11; /* 7CC */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt12_u osch_tlp_hva_npcpl_drop_cnt12; /* 7D0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt13_u osch_tlp_hva_npcpl_drop_cnt13; /* 7D4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt14_u osch_tlp_hva_npcpl_drop_cnt14; /* 7D8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt15_u osch_tlp_hva_npcpl_drop_cnt15; /* 7DC */ + volatile csr_osch_tlp_drop_count_mode_u osch_tlp_drop_count_mode; /* 7E0 */ + volatile csr_osch_npcpl_perf_watch_byte_u osch_npcpl_perf_watch_byte; /* 7E8 */ + volatile csr_osch_npcpl_perf_watch_tlp_u osch_npcpl_perf_watch_tlp; /* 7EC */ + volatile csr_osch_hva_p_perf_watch_byte_u osch_hva_p_perf_watch_byte; /* 7F0 */ + volatile csr_osch_hva_p_perf_watch_tlp_u osch_hva_p_perf_watch_tlp; /* 7F4 */ + volatile csr_osch_hva_npcpl_perf_watch_byte_u osch_hva_npcpl_perf_watch_byte; /* 7F8 */ + volatile csr_osch_hva_npcpl_perf_watch_tlp_u osch_hva_npcpl_perf_watch_tlp; /* 7FC */ +} S_cpi_osch_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_osch_csr */ +extern volatile S_cpi_osch_csr_REGS_TYPE *gopcpi_osch_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetOSCH_TLP_DROP_CNT_PORT0_osch_tlp_drop_count_port0(unsigned int uosch_tlp_drop_count_port0); +int iSetOSCH_TLP_DROP_CNT_PORT1_osch_tlp_drop_count_port1(unsigned int uosch_tlp_drop_count_port1); +int iSetOSCH_TLP_DROP_CNT_PORT2_osch_tlp_drop_count_port2(unsigned int uosch_tlp_drop_count_port2); +int iSetOSCH_TLP_DROP_CNT_PORT3_osch_tlp_drop_count_port3(unsigned int uosch_tlp_drop_count_port3); +int iSetOSCH_TLP_DROP_CNT_PORT4_osch_tlp_drop_count_port4(unsigned int uosch_tlp_drop_count_port4); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port3(unsigned int uosch_tlp_err_count_port3); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port2(unsigned int uosch_tlp_err_count_port2); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port1(unsigned int uosch_tlp_err_count_port1); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port0(unsigned int uosch_tlp_err_count_port0); +int iSetOSCH_TLP_ERROR_CNT1_osch_tlp_err_count_port4(unsigned int uosch_tlp_err_count_port4); +int iSetOSCH_TLP_DROP_CNT0_osch_tlp_drop_count0(unsigned int uosch_tlp_drop_count0); +int iSetOSCH_TLP_DROP_CNT1_osch_tlp_drop_count1(unsigned int uosch_tlp_drop_count1); +int iSetOSCH_TLP_DROP_CNT2_osch_tlp_drop_count2(unsigned int uosch_tlp_drop_count2); +int iSetOSCH_TLP_DROP_CNT3_osch_tlp_drop_count3(unsigned int uosch_tlp_drop_count3); +int iSetOSCH_TLP_DROP_CNT4_osch_tlp_drop_count4(unsigned int uosch_tlp_drop_count4); +int iSetOSCH_TLP_DROP_CNT5_osch_tlp_drop_count5(unsigned int uosch_tlp_drop_count5); +int iSetOSCH_TLP_DROP_CNT6_osch_tlp_drop_count6(unsigned int uosch_tlp_drop_count6); +int iSetOSCH_TLP_DROP_CNT7_osch_tlp_drop_count7(unsigned int uosch_tlp_drop_count7); +int iSetOSCH_TLP_DROP_CNT8_osch_tlp_drop_count8(unsigned int uosch_tlp_drop_count8); +int iSetOSCH_TLP_DROP_CNT9_osch_tlp_drop_count9(unsigned int uosch_tlp_drop_count9); +int iSetOSCH_TLP_DROP_CNT10_osch_tlp_drop_count10(unsigned int uosch_tlp_drop_count10); +int iSetOSCH_TLP_DROP_CNT11_osch_tlp_drop_count11(unsigned int uosch_tlp_drop_count11); +int iSetOSCH_TLP_DROP_CNT12_osch_tlp_drop_count12(unsigned int uosch_tlp_drop_count12); +int iSetOSCH_TLP_DROP_CNT13_osch_tlp_drop_count13(unsigned int uosch_tlp_drop_count13); +int iSetOSCH_TLP_DROP_CNT14_osch_tlp_drop_count14(unsigned int uosch_tlp_drop_count14); +int iSetOSCH_TLP_DROP_CNT15_osch_tlp_drop_count15(unsigned int uosch_tlp_drop_count15); +int iSetOSCH_TLP_DROP_FUNC01_osch_tlp_drop_func1(unsigned int uosch_tlp_drop_func1); +int iSetOSCH_TLP_DROP_FUNC01_osch_tlp_drop_func0(unsigned int uosch_tlp_drop_func0); +int iSetOSCH_TLP_DROP_FUNC23_osch_tlp_drop_func3(unsigned int uosch_tlp_drop_func3); +int iSetOSCH_TLP_DROP_FUNC23_osch_tlp_drop_func2(unsigned int uosch_tlp_drop_func2); +int iSetOSCH_TLP_DROP_FUNC45_osch_tlp_drop_func5(unsigned int uosch_tlp_drop_func5); +int iSetOSCH_TLP_DROP_FUNC45_osch_tlp_drop_func4(unsigned int uosch_tlp_drop_func4); +int iSetOSCH_TLP_DROP_FUNC67_osch_tlp_drop_func7(unsigned int uosch_tlp_drop_func7); +int iSetOSCH_TLP_DROP_FUNC67_osch_tlp_drop_func6(unsigned int uosch_tlp_drop_func6); +int iSetOSCH_TLP_DROP_FUNC89_osch_tlp_drop_func9(unsigned int uosch_tlp_drop_func9); +int iSetOSCH_TLP_DROP_FUNC89_osch_tlp_drop_func8(unsigned int uosch_tlp_drop_func8); +int iSetOSCH_TLP_DROP_FUNC1011_osch_tlp_drop_func11(unsigned int uosch_tlp_drop_func11); +int iSetOSCH_TLP_DROP_FUNC1011_osch_tlp_drop_func10(unsigned int uosch_tlp_drop_func10); +int iSetOSCH_TLP_DROP_FUNC1213_osch_tlp_drop_func13(unsigned int uosch_tlp_drop_func13); +int iSetOSCH_TLP_DROP_FUNC1213_osch_tlp_drop_func12(unsigned int uosch_tlp_drop_func12); +int iSetOSCH_TLP_DROP_FUNC1415_osch_tlp_drop_func15(unsigned int uosch_tlp_drop_func15); +int iSetOSCH_TLP_DROP_FUNC1415_osch_tlp_drop_func14(unsigned int uosch_tlp_drop_func14); +int iSetOSCH_CEQE_DROP_CNT_osch_ceqe_drop_cnt(unsigned int uosch_ceqe_drop_cnt); +int iSetOSCH_CEQE_PI_OVERFLOW_osch_ceqe_pi_overfl_qid(unsigned int uosch_ceqe_pi_overfl_qid); +int iSetOSCH_CEQE_PI_OVERFLOW_osch_ceqe_pi_overfl(unsigned int uosch_ceqe_pi_overfl); +int iSetOSCH_FIFO_OVERFLOW_LOW_osch_fifo_overflow_id(unsigned int uosch_fifo_overflow_id); +int iSetOSCH_FIFO_OVERFLOW_LOW_osch_fifo_overflow(unsigned int uosch_fifo_overflow); +int iSetOSCH_REQ_TIMEOUT_cur_port_busy_src(unsigned int ucur_port_busy_src); +int iSetOSCH_FIFO_EMPT_HIGH_osch_fifo_empty_high(unsigned int uosch_fifo_empty_high); +int iSetOSCH_FIFO_EMPT_HIGH_osch_empty(unsigned int uosch_empty); +int iSetOSCH_FIFO_EMPT_LOW_osch_fifo_empty_low(unsigned int uosch_fifo_empty_low); +int iSetOSCH_FIFO_AFULL_HIGH_osch_fifo_afull_high(unsigned int uosch_fifo_afull_high); +int iSetOSCH_FIFO_AFULL_LOW_osch_fifo_afull_low(unsigned int uosch_fifo_afull_low); +int iSetOSCH_PAYLOAD_FIFO_CTRL_osch_payload_fifo_ctrl_all_port(unsigned int uosch_payload_fifo_ctrl_all_port); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port3(unsigned int uosch_msi_tx_fifo_ctrl_port3); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port2(unsigned int uosch_msi_tx_fifo_ctrl_port2); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port1(unsigned int uosch_msi_tx_fifo_ctrl_port1); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port0(unsigned int uosch_msi_tx_fifo_ctrl_port0); +int iSetOSCH_MSI_TX_FIFO_CTRL1_osch_msi_tx_fifo_ctrl_port4(unsigned int uosch_msi_tx_fifo_ctrl_port4); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port3(unsigned int uosch_atomic_tx_fifo_ctrl_port3); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port2(unsigned int uosch_atomic_tx_fifo_ctrl_port2); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port1(unsigned int uosch_atomic_tx_fifo_ctrl_port1); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port0(unsigned int uosch_atomic_tx_fifo_ctrl_port0); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL1_osch_atomic_tx_fifo_ctrl_port4(unsigned int uosch_atomic_tx_fifo_ctrl_port4); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port3(unsigned int uosch_ceqe_tx_fifo_ctrl_port3); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port2(unsigned int uosch_ceqe_tx_fifo_ctrl_port2); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port1(unsigned int uosch_ceqe_tx_fifo_ctrl_port1); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port0(unsigned int uosch_ceqe_tx_fifo_ctrl_port0); +int iSetOSCH_CEQE_TX_FIFO_CTRL1_osch_ceqe_tx_fifo_ctrl_port4(unsigned int uosch_ceqe_tx_fifo_ctrl_port4); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port3(unsigned int uosch_cpld_tx_fifo_ctrl_port3); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port2(unsigned int uosch_cpld_tx_fifo_ctrl_port2); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port1(unsigned int uosch_cpld_tx_fifo_ctrl_port1); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port0(unsigned int uosch_cpld_tx_fifo_ctrl_port0); +int iSetOSCH_CPLD_TX_FIFO_CTRL1_osch_cpld_tx_fifo_ctrl_port4(unsigned int uosch_cpld_tx_fifo_ctrl_port4); +int iSetOSCH_FIFO_EMPT_TOPHIGH_osch_fifo_empty_tophigh(unsigned int uosch_fifo_empty_tophigh); +int iSetOSCH_FIFO_EMPT_TOPHIGH_osch_port_pipe_empty(unsigned int uosch_port_pipe_empty); +int iSetOSCH_FIFO_EMPT_TOPHIGH_osch_port_sch_pipe_empty(unsigned int uosch_port_sch_pipe_empty); +int iSetOSCH_FIFO_AFULL_TOPHIGH_osch_fifo_afull_tophigh(unsigned int uosch_fifo_afull_tophigh); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port3(unsigned int uosch_cpath_q0_fifo_ctrl_port3); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port2(unsigned int uosch_cpath_q0_fifo_ctrl_port2); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port1(unsigned int uosch_cpath_q0_fifo_ctrl_port1); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port0(unsigned int uosch_cpath_q0_fifo_ctrl_port0); +int iSetOSCH_CPATH_Q0_FIFO_CTRL1_osch_cpath_q0_fifo_ctrl_port4(unsigned int uosch_cpath_q0_fifo_ctrl_port4); +int iSetOSCH_CPATH_Q1_FIFO_CTRL0_osch_cpath_q1_fifo_ctrl_port2(unsigned int uosch_cpath_q1_fifo_ctrl_port2); +int iSetOSCH_CPATH_Q1_FIFO_CTRL0_osch_cpath_q1_fifo_ctrl_port1(unsigned int uosch_cpath_q1_fifo_ctrl_port1); +int iSetOSCH_CPATH_Q1_FIFO_CTRL0_osch_cpath_q1_fifo_ctrl_port0(unsigned int uosch_cpath_q1_fifo_ctrl_port0); +int iSetOSCH_CPATH_Q1_FIFO_CTRL1_osch_cpath_q1_fifo_ctrl_port4(unsigned int uosch_cpath_q1_fifo_ctrl_port4); +int iSetOSCH_CPATH_Q1_FIFO_CTRL1_osch_cpath_q1_fifo_ctrl_port3(unsigned int uosch_cpath_q1_fifo_ctrl_port3); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port3(unsigned int uosch_cpath_q2_fifo_ctrl_port3); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port2(unsigned int uosch_cpath_q2_fifo_ctrl_port2); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port1(unsigned int uosch_cpath_q2_fifo_ctrl_port1); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port0(unsigned int uosch_cpath_q2_fifo_ctrl_port0); +int iSetOSCH_CPATH_Q2_FIFO_CTRL1_osch_cpath_q2_fifo_ctrl_port4(unsigned int uosch_cpath_q2_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port3(unsigned int uosch_dpath_q0_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port2(unsigned int uosch_dpath_q0_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port1(unsigned int uosch_dpath_q0_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port0(unsigned int uosch_dpath_q0_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q0_FIFO_CTRL1_osch_dpath_q0_fifo_ctrl_port4(unsigned int uosch_dpath_q0_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port3(unsigned int uosch_dpath_q1_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port2(unsigned int uosch_dpath_q1_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port1(unsigned int uosch_dpath_q1_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port0(unsigned int uosch_dpath_q1_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q1_FIFO_CTRL1_osch_dpath_q1_fifo_ctrl_port4(unsigned int uosch_dpath_q1_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port3(unsigned int uosch_dpath_q2_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port2(unsigned int uosch_dpath_q2_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port1(unsigned int uosch_dpath_q2_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port0(unsigned int uosch_dpath_q2_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q2_FIFO_CTRL1_osch_dpath_q2_fifo_ctrl_port4(unsigned int uosch_dpath_q2_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port3(unsigned int uosch_dpath_q3_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port2(unsigned int uosch_dpath_q3_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port1(unsigned int uosch_dpath_q3_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port0(unsigned int uosch_dpath_q3_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q3_FIFO_CTRL1_osch_dpath_q3_fifo_ctrl_port4(unsigned int uosch_dpath_q3_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port3(unsigned int uosch_dpath_q4_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port2(unsigned int uosch_dpath_q4_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port1(unsigned int uosch_dpath_q4_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port0(unsigned int uosch_dpath_q4_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q4_FIFO_CTRL1_osch_dpath_q4_fifo_ctrl_port4(unsigned int uosch_dpath_q4_fifo_ctrl_port4); +int iSetOSCH_RESERVED0_osch_resved0(unsigned int uosch_resved0); +int iSetOSCH_RESERVED1_osch_resved1(unsigned int uosch_resved1); +int iSetOSCH_RESERVED2_osch_resved2(unsigned int uosch_resved2); +int iSetGLB_POST_HEAD_CREDIT_glb_post_head_credit(unsigned int uglb_post_head_credit); +int iSetGLB_POST_PAYLOAD_CREDIT_H_glb_post_payload_credit_h(unsigned int uglb_post_payload_credit_h); +int iSetGLB_POST_PAYLOAD_CREDIT_L_glb_post_payload_credit_l(unsigned int uglb_post_payload_credit_l); +int iSetGLB_NON_POST_HEAD_CREDIT_glb_non_post_head_credit(unsigned int uglb_non_post_head_credit); +int iSetGLB_NON_POST_PAYLOAD_CREDIT_H_glb_non_post_payload_credit_h(unsigned int uglb_non_post_payload_credit_h); +int iSetGLB_NON_POST_PAYLOAD_CREDIT_L_glb_non_post_payload_credit_l(unsigned int uglb_non_post_payload_credit_l); +int iSetGLB_CPL_HEAD_CREDIT_glb_cpl_head_credit(unsigned int uglb_cpl_head_credit); +int iSetGLB_CPL_PAYLOAD_CREDIT_H_glb_cpl_payload_credit_h(unsigned int uglb_cpl_payload_credit_h); +int iSetGLB_CPL_PAYLOAD_CREDIT_L_glb_cpl_payload_credit_l(unsigned int uglb_cpl_payload_credit_l); +int iSetGLB_OSCH_CEQE_IN_CNT_glb_osch_ceqe_in_cnt(unsigned int uglb_osch_ceqe_in_cnt); +int iSetGLB_OSCH_CEQE_OUT_CNT_glb_osch_ceqe_out_cnt(unsigned int uglb_osch_ceqe_out_cnt); +int iSetGLB_CEQE_DROP_TAIL_glb_ceqe_drop_tail(unsigned int uglb_ceqe_drop_tail); +int iSetGLB_CEQE_DROP_TAIL_ceqe_cls_glb_offs_drop_en(unsigned int uceqe_cls_glb_offs_drop_en); +int iSetOSCH_TLP_POST_CNT_PORT0_osch_tlp_post_count_port0(unsigned int uosch_tlp_post_count_port0); +int iSetOSCH_TLP_POST_CNT_PORT1_osch_tlp_post_count_port1(unsigned int uosch_tlp_post_count_port1); +int iSetOSCH_TLP_POST_CNT_PORT2_osch_tlp_post_count_port2(unsigned int uosch_tlp_post_count_port2); +int iSetOSCH_TLP_POST_CNT_PORT3_osch_tlp_post_count_port3(unsigned int uosch_tlp_post_count_port3); +int iSetOSCH_TLP_POST_CNT_PORT4_osch_tlp_post_count_port4(unsigned int uosch_tlp_post_count_port4); +int iSetOSCH_TLP_NON_POST_CNT_PORT0_osch_tlp_non_post_count_port0(unsigned int uosch_tlp_non_post_count_port0); +int iSetOSCH_TLP_NON_POST_CNT_PORT1_osch_tlp_non_post_count_port1(unsigned int uosch_tlp_non_post_count_port1); +int iSetOSCH_TLP_NON_POST_CNT_PORT2_osch_tlp_non_post_count_port2(unsigned int uosch_tlp_non_post_count_port2); +int iSetOSCH_TLP_NON_POST_CNT_PORT3_osch_tlp_non_post_count_port3(unsigned int uosch_tlp_non_post_count_port3); +int iSetOSCH_TLP_NON_POST_CNT_PORT4_osch_tlp_non_post_count_port4(unsigned int uosch_tlp_non_post_count_port4); +int iSetOSCH_TLP_CPL_CNT_PORT0_osch_tlp_cpl_count_port0(unsigned int uosch_tlp_cpl_count_port0); +int iSetOSCH_TLP_CPL_CNT_PORT1_osch_tlp_cpl_count_port1(unsigned int uosch_tlp_cpl_count_port1); +int iSetOSCH_TLP_CPL_CNT_PORT2_osch_tlp_cpl_count_port2(unsigned int uosch_tlp_cpl_count_port2); +int iSetOSCH_TLP_CPL_CNT_PORT3_osch_tlp_cpl_count_port3(unsigned int uosch_tlp_cpl_count_port3); +int iSetOSCH_TLP_CPL_CNT_PORT4_osch_tlp_cpl_count_port4(unsigned int uosch_tlp_cpl_count_port4); +int iSetOSCH_INT_CEQ_CREDIT_PORT01_osch_int_ceq_credit_port1(unsigned int uosch_int_ceq_credit_port1); +int iSetOSCH_INT_CEQ_CREDIT_PORT01_osch_int_ceq_credit_port0(unsigned int uosch_int_ceq_credit_port0); +int iSetOSCH_INT_CEQ_CREDIT_PORT23_osch_int_ceq_credit_port3(unsigned int uosch_int_ceq_credit_port3); +int iSetOSCH_INT_CEQ_CREDIT_PORT23_osch_int_ceq_credit_port2(unsigned int uosch_int_ceq_credit_port2); +int iSetOSCH_INT_CEQ_CREDIT_PORT4_osch_int_ceq_credit_port4(unsigned int uosch_int_ceq_credit_port4); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q4(unsigned int uosch_esch_dpath_bp_q4); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q3(unsigned int uosch_esch_dpath_bp_q3); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q2(unsigned int uosch_esch_dpath_bp_q2); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q1(unsigned int uosch_esch_dpath_bp_q1); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q0(unsigned int uosch_esch_dpath_bp_q0); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port3(unsigned int uosch_esch_dpath_q0_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port2(unsigned int uosch_esch_dpath_q0_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port1(unsigned int uosch_esch_dpath_q0_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port0(unsigned int uosch_esch_dpath_q0_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD1_osch_esch_dpath_q0_bp_thd_port4(unsigned int uosch_esch_dpath_q0_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port3(unsigned int uosch_esch_dpath_q1_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port2(unsigned int uosch_esch_dpath_q1_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port1(unsigned int uosch_esch_dpath_q1_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port0(unsigned int uosch_esch_dpath_q1_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD1_osch_esch_dpath_q1_bp_thd_port4(unsigned int uosch_esch_dpath_q1_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port3(unsigned int uosch_esch_dpath_q2_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port2(unsigned int uosch_esch_dpath_q2_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port1(unsigned int uosch_esch_dpath_q2_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port0(unsigned int uosch_esch_dpath_q2_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD1_osch_esch_dpath_q2_bp_thd_port4(unsigned int uosch_esch_dpath_q2_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port3(unsigned int uosch_esch_dpath_q3_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port2(unsigned int uosch_esch_dpath_q3_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port1(unsigned int uosch_esch_dpath_q3_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port0(unsigned int uosch_esch_dpath_q3_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD1_osch_esch_dpath_q3_bp_thd_port4(unsigned int uosch_esch_dpath_q3_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port3(unsigned int uosch_esch_dpath_q4_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port2(unsigned int uosch_esch_dpath_q4_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port1(unsigned int uosch_esch_dpath_q4_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port0(unsigned int uosch_esch_dpath_q4_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD1_osch_esch_dpath_q4_bp_thd_port4(unsigned int uosch_esch_dpath_q4_bp_thd_port4); +int iSetOSCH_PERF_WATCH_EN_osch_perf_watch_en(unsigned int uosch_perf_watch_en); +int iSetOSCH_PERF_WATCH_EN_osch_perf_watch_port_idx(unsigned int uosch_perf_watch_port_idx); +int iSetOSCH_PERF_WATCH_PERIOD_osch_perf_watch_period(unsigned int uosch_perf_watch_period); +int iSetOSCH_PERF_WATCH_BYTE_osch_perf_watch_byte(unsigned int uosch_perf_watch_byte); +int iSetOSCH_PERF_WATCH_TLP_osch_perf_watch_tlp(unsigned int uosch_perf_watch_tlp); +int iSetPORT_OUT_SCH_DWRR_WEIGHT_port_sch_dwrr_weight(unsigned int uport_sch_dwrr_weight); +int iSetPORT_RD_SRC_WEIGHT1_port_rd_src_dwrr_weight2(unsigned int uport_rd_src_dwrr_weight2); +int iSetPORT_RD_SRC_WEIGHT0_port_rd_src_dwrr_weight0(unsigned int uport_rd_src_dwrr_weight0); +int iSetPORT_RD_SRC_WEIGHT0_port_rd_src_dwrr_weight1(unsigned int uport_rd_src_dwrr_weight1); +int iSetPORT_RD_DPATH_WRR_WEIGHT1_port_rd_dpath_wrr_weight4(unsigned int uport_rd_dpath_wrr_weight4); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight0(unsigned int uport_rd_dpath_wrr_weight0); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight1(unsigned int uport_rd_dpath_wrr_weight1); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight2(unsigned int uport_rd_dpath_wrr_weight2); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight3(unsigned int uport_rd_dpath_wrr_weight3); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT1_port_rd_ndpath_wrr_weight4(unsigned int uport_rd_ndpath_wrr_weight4); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight0(unsigned int uport_rd_ndpath_wrr_weight0); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight1(unsigned int uport_rd_ndpath_wrr_weight1); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight2(unsigned int uport_rd_ndpath_wrr_weight2); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight3(unsigned int uport_rd_ndpath_wrr_weight3); +int iSetPORT_WR_WRR_WEIGHT2_port_wr_wrr_weight8(unsigned int uport_wr_wrr_weight8); +int iSetPORT_WR_WRR_WEIGHT2_port_wr_wrr_weight9(unsigned int uport_wr_wrr_weight9); +int iSetPORT_WR_WRR_WEIGHT2_port_wr_wrr_weight10(unsigned int uport_wr_wrr_weight10); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight4(unsigned int uport_wr_wrr_weight4); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight5(unsigned int uport_wr_wrr_weight5); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight6(unsigned int uport_wr_wrr_weight6); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight7(unsigned int uport_wr_wrr_weight7); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight0(unsigned int uport_wr_wrr_weight0); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight1(unsigned int uport_wr_wrr_weight1); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight2(unsigned int uport_wr_wrr_weight2); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight3(unsigned int uport_wr_wrr_weight3); +int iSetCFG_DOORBELL_CRDT_BP_TH_cfg_doorbell_crdt_bp_th(unsigned int ucfg_doorbell_crdt_bp_th); +int iSetDOORBELL_WR_CMD_CRDT_ERR_doorbell_wr_cmd_crdt_err(unsigned int udoorbell_wr_cmd_crdt_err); +int iSetOSCH_CTRL_DOORBELL_CNT_osch_ctrl_doorbell_cnt(unsigned int uosch_ctrl_doorbell_cnt); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_payload_crdt_cnt0(unsigned int upcie_wr_payload_crdt_cnt0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_head_crdt_cnt0(unsigned int upcie_wr_head_crdt_cnt0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_payload_busy0(unsigned int upcie_wr_payload_busy0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_head_busy0(unsigned int upcie_wr_head_busy0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_payload_crdt_cnt0(unsigned int upcie_rd_payload_crdt_cnt0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_head_crdt_cnt0(unsigned int upcie_rd_head_crdt_cnt0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_payload_busy0(unsigned int upcie_rd_payload_busy0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_head_busy0(unsigned int upcie_rd_head_busy0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_payload_crdt_cnt0(unsigned int upcie_cpl_payload_crdt_cnt0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_head_crdt_cnt0(unsigned int upcie_cpl_head_crdt_cnt0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_payload_busy0(unsigned int upcie_cpl_payload_busy0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_head_busy0(unsigned int upcie_cpl_head_busy0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_payload_crdt_cnt1(unsigned int upcie_wr_payload_crdt_cnt1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_head_crdt_cnt1(unsigned int upcie_wr_head_crdt_cnt1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_payload_busy1(unsigned int upcie_wr_payload_busy1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_head_busy1(unsigned int upcie_wr_head_busy1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_payload_crdt_cnt1(unsigned int upcie_rd_payload_crdt_cnt1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_head_crdt_cnt1(unsigned int upcie_rd_head_crdt_cnt1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_payload_busy1(unsigned int upcie_rd_payload_busy1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_head_busy1(unsigned int upcie_rd_head_busy1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_payload_crdt_cnt1(unsigned int upcie_cpl_payload_crdt_cnt1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_head_crdt_cnt1(unsigned int upcie_cpl_head_crdt_cnt1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_payload_busy1(unsigned int upcie_cpl_payload_busy1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_head_busy1(unsigned int upcie_cpl_head_busy1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_payload_crdt_cnt2(unsigned int upcie_wr_payload_crdt_cnt2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_head_crdt_cnt2(unsigned int upcie_wr_head_crdt_cnt2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_payload_busy2(unsigned int upcie_wr_payload_busy2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_head_busy2(unsigned int upcie_wr_head_busy2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_payload_crdt_cnt2(unsigned int upcie_rd_payload_crdt_cnt2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_head_crdt_cnt2(unsigned int upcie_rd_head_crdt_cnt2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_payload_busy2(unsigned int upcie_rd_payload_busy2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_head_busy2(unsigned int upcie_rd_head_busy2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_payload_crdt_cnt2(unsigned int upcie_cpl_payload_crdt_cnt2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_head_crdt_cnt2(unsigned int upcie_cpl_head_crdt_cnt2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_payload_busy2(unsigned int upcie_cpl_payload_busy2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_head_busy2(unsigned int upcie_cpl_head_busy2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_payload_crdt_cnt3(unsigned int upcie_wr_payload_crdt_cnt3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_head_crdt_cnt3(unsigned int upcie_wr_head_crdt_cnt3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_payload_busy3(unsigned int upcie_wr_payload_busy3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_head_busy3(unsigned int upcie_wr_head_busy3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_payload_crdt_cnt3(unsigned int upcie_rd_payload_crdt_cnt3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_head_crdt_cnt3(unsigned int upcie_rd_head_crdt_cnt3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_payload_busy3(unsigned int upcie_rd_payload_busy3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_head_busy3(unsigned int upcie_rd_head_busy3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_payload_crdt_cnt3(unsigned int upcie_cpl_payload_crdt_cnt3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_head_crdt_cnt3(unsigned int upcie_cpl_head_crdt_cnt3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_payload_busy3(unsigned int upcie_cpl_payload_busy3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_head_busy3(unsigned int upcie_cpl_head_busy3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_payload_crdt_cnt4(unsigned int upcie_wr_payload_crdt_cnt4); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_head_crdt_cnt4(unsigned int upcie_wr_head_crdt_cnt4); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_payload_busy4(unsigned int upcie_wr_payload_busy4); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_head_busy4(unsigned int upcie_wr_head_busy4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_payload_crdt_cnt4(unsigned int upcie_rd_payload_crdt_cnt4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_head_crdt_cnt4(unsigned int upcie_rd_head_crdt_cnt4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_payload_busy4(unsigned int upcie_rd_payload_busy4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_head_busy4(unsigned int upcie_rd_head_busy4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_payload_crdt_cnt4(unsigned int upcie_cpl_payload_crdt_cnt4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_head_crdt_cnt4(unsigned int upcie_cpl_head_crdt_cnt4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_payload_busy4(unsigned int upcie_cpl_payload_busy4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_head_busy4(unsigned int upcie_cpl_head_busy4); +int iSetOSCH_ECC_INJ_0_cpi_osch_cpld_fifo_inj(unsigned int ucpi_osch_cpld_fifo_inj); +int iSetOSCH_ECC_INJ_0_cpi_osch_nl2nic_req_mem_inj(unsigned int ucpi_osch_nl2nic_req_mem_inj); +int iSetOSCH_ECC_INJ_0_cpi_osch_ceqe_tx_fifo_inj(unsigned int ucpi_osch_ceqe_tx_fifo_inj); +int iSetOSCH_ECC_INJ_1_cpi_osch_dpath_q0_fifo_inj(unsigned int ucpi_osch_dpath_q0_fifo_inj); +int iSetOSCH_ECC_INJ_1_cpi_osch_dpath_q1_fifo_inj(unsigned int ucpi_osch_dpath_q1_fifo_inj); +int iSetOSCH_ECC_INJ_1_cpi_osch_dpath_q2_fifo_inj(unsigned int ucpi_osch_dpath_q2_fifo_inj); +int iSetOSCH_ECC_INJ_2_cpi_osch_dpath_q3_fifo_inj(unsigned int ucpi_osch_dpath_q3_fifo_inj); +int iSetOSCH_ECC_INJ_2_cpi_osch_dpath_q4_fifo_inj(unsigned int ucpi_osch_dpath_q4_fifo_inj); +int iSetOSCH_ECC_INJ_2_cpi_osch_atomic_tx_fifo_inj(unsigned int ucpi_osch_atomic_tx_fifo_inj); +int iSetOSCH_ECC_INJ_3_cpi_osch_cpath_q0_fifo_inj(unsigned int ucpi_osch_cpath_q0_fifo_inj); +int iSetOSCH_ECC_INJ_3_cpi_osch_cpath_q1_fifo_inj(unsigned int ucpi_osch_cpath_q1_fifo_inj); +int iSetOSCH_ECC_INJ_3_cpi_osch_cpath_q2_fifo_inj(unsigned int ucpi_osch_cpath_q2_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_msi_tx_fifo_inj(unsigned int ucpi_osch_msi_tx_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_atomic64_fifo_inj(unsigned int ucpi_osch_atomic64_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_ceqe_buf_fifo_inj(unsigned int ucpi_osch_ceqe_buf_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo_inj(unsigned int ucpi_osch_payload_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo1_inj(unsigned int ucpi_osch_payload_fifo1_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo_hva_inj(unsigned int ucpi_osch_payload_fifo_hva_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo1_hva_inj(unsigned int ucpi_osch_payload_fifo1_hva_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_doorbell_fifo_inj(unsigned int ucpi_osch_doorbell_fifo_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo_np_inj(unsigned int ucpi_osch_payload_fifo_np_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo1_np_inj(unsigned int ucpi_osch_payload_fifo1_np_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo_hva_np_inj(unsigned int ucpi_osch_payload_fifo_hva_np_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo1_hva_np_inj(unsigned int ucpi_osch_payload_fifo1_hva_np_inj); +int iSetOSCH_ECC_INT_0_osch_cpld_fifo_ecc_err(unsigned int uosch_cpld_fifo_ecc_err); +int iSetOSCH_ECC_INT_0_osch_nl2nic_req_mem_ecc_err(unsigned int uosch_nl2nic_req_mem_ecc_err); +int iSetOSCH_ECC_INT_0_osch_ceqe_tx_fifo_ecc_err(unsigned int uosch_ceqe_tx_fifo_ecc_err); +int iSetOSCH_ECC_INT_1_osch_dpath_q0_fifo_ecc_err(unsigned int uosch_dpath_q0_fifo_ecc_err); +int iSetOSCH_ECC_INT_1_osch_dpath_q1_fifo_ecc_err(unsigned int uosch_dpath_q1_fifo_ecc_err); +int iSetOSCH_ECC_INT_1_osch_dpath_q2_fifo_ecc_err(unsigned int uosch_dpath_q2_fifo_ecc_err); +int iSetOSCH_ECC_INT_2_osch_dpath_q3_fifo_ecc_err(unsigned int uosch_dpath_q3_fifo_ecc_err); +int iSetOSCH_ECC_INT_2_osch_dpath_q4_fifo_ecc_err(unsigned int uosch_dpath_q4_fifo_ecc_err); +int iSetOSCH_ECC_INT_2_osch_atomic_tx_fifo_ecc_err(unsigned int uosch_atomic_tx_fifo_ecc_err); +int iSetOSCH_ECC_INT_3_osch_cpath_q0_fifo_ecc_err(unsigned int uosch_cpath_q0_fifo_ecc_err); +int iSetOSCH_ECC_INT_3_osch_cpath_q1_fifo_ecc_err(unsigned int uosch_cpath_q1_fifo_ecc_err); +int iSetOSCH_ECC_INT_3_osch_cpath_q2_fifo_ecc_err(unsigned int uosch_cpath_q2_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_msi_tx_fifo_ecc_err(unsigned int uosch_msi_tx_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_atomic64_fifo_ecc_err(unsigned int uosch_atomic64_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_ceqe_buf_fifo_ecc_err(unsigned int uosch_ceqe_buf_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo_ecc_err(unsigned int uosch_payload_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo1_ecc_err(unsigned int uosch_payload_fifo1_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo_hva_ecc_err(unsigned int uosch_payload_fifo_hva_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo1_hva_ecc_err(unsigned int uosch_payload_fifo1_hva_ecc_err); +int iSetOSCH_ECC_INT_4_osch_doorbell_fifo_ecc_err(unsigned int uosch_doorbell_fifo_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo_np_ecc_err(unsigned int uosch_payload_fifo_np_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo1_np_ecc_err(unsigned int uosch_payload_fifo1_np_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo_hva_np_ecc_err(unsigned int uosch_payload_fifo_hva_np_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo1_hva_np_ecc_err(unsigned int uosch_payload_fifo1_hva_np_ecc_err); +int iSetOSCH_ECC_INT_EN_0_osch_cpld_fifo_ecc_int_en(unsigned int uosch_cpld_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_0_osch_nl2nic_req_mem_ecc_int_en(unsigned int uosch_nl2nic_req_mem_ecc_int_en); +int iSetOSCH_ECC_INT_EN_0_osch_ceqe_tx_fifo_ecc_int_en(unsigned int uosch_ceqe_tx_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_1_osch_dpath_q0_fifo_ecc_int_en(unsigned int uosch_dpath_q0_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_1_osch_dpath_q1_fifo_ecc_int_en(unsigned int uosch_dpath_q1_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_1_osch_dpath_q2_fifo_ecc_int_en(unsigned int uosch_dpath_q2_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_2_osch_dpath_q3_fifo_ecc_int_en(unsigned int uosch_dpath_q3_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_2_osch_dpath_q4_fifo_ecc_int_en(unsigned int uosch_dpath_q4_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_2_osch_atomic_tx_fifo_ecc_int_en(unsigned int uosch_atomic_tx_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_3_osch_cpath_q0_fifo_ecc_int_en(unsigned int uosch_cpath_q0_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_3_osch_cpath_q1_fifo_ecc_int_en(unsigned int uosch_cpath_q1_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_3_osch_cpath_q2_fifo_ecc_int_en(unsigned int uosch_cpath_q2_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_msi_tx_fifo_ecc_int_en(unsigned int uosch_msi_tx_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_atomic64_fifo_ecc_int_en(unsigned int uosch_atomic64_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_ceqe_buf_fifo_ecc_int_en(unsigned int uosch_ceqe_buf_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo_ecc_int_en(unsigned int uosch_payload_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo1_ecc_int_en(unsigned int uosch_payload_fifo1_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo_hva_ecc_int_en(unsigned int uosch_payload_fifo_hva_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo1_hva_ecc_int_en(unsigned int uosch_payload_fifo1_hva_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_doorbell_fifo_ecc_int_en(unsigned int uosch_doorbell_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo_np_ecc_int_en(unsigned int uosch_payload_fifo_np_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo1_np_ecc_int_en(unsigned int uosch_payload_fifo1_np_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo_hva_np_ecc_int_en(unsigned int uosch_payload_fifo_hva_np_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo1_hva_np_ecc_int_en(unsigned int uosch_payload_fifo1_hva_np_ecc_int_en); +int iSetOSCH_ECC_ERR_ADDR_0_osch_payload_fifo1_ecc_erraddr(unsigned int uosch_payload_fifo1_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_0_osch_payload_fifo_hva_ecc_erraddr(unsigned int uosch_payload_fifo_hva_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_0_osch_payload_fifo1_hva_ecc_erraddr(unsigned int uosch_payload_fifo1_hva_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_1_osch_port0_ecc_erraddr(unsigned int uosch_port0_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_1_osch_ceqe_buf_ecc_erraddr(unsigned int uosch_ceqe_buf_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_1_osch_payload_fifo_ecc_erraddr(unsigned int uosch_payload_fifo_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_2_osch_port1_ecc_erraddr(unsigned int uosch_port1_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_2_osch_port2_ecc_erraddr(unsigned int uosch_port2_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_2_osch_port3_ecc_erraddr(unsigned int uosch_port3_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_3_osch_port4_ecc_erraddr(unsigned int uosch_port4_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_3_osch_payload_fifo1_hva_np_ecc_erraddr(unsigned int uosch_payload_fifo1_hva_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_3_osch_doorbell_fifo_ecc_erraddr(unsigned int uosch_doorbell_fifo_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_4_osch_payload_fifo_np_ecc_erraddr(unsigned int uosch_payload_fifo_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_4_osch_payload_fifo1_np_ecc_erraddr(unsigned int uosch_payload_fifo1_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_4_osch_payload_fifo_hva_np_ecc_erraddr(unsigned int uosch_payload_fifo_hva_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port0_sel(unsigned int uosch_ecc_err_addr_port0_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port1_sel(unsigned int uosch_ecc_err_addr_port1_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port2_sel(unsigned int uosch_ecc_err_addr_port2_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port3_sel(unsigned int uosch_ecc_err_addr_port3_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port4_sel(unsigned int uosch_ecc_err_addr_port4_sel); +int iSetOSCH_OVERFLOW_INT_0_atomic64_tx_fifo_overf(unsigned int uatomic64_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_hva_overf_np(unsigned int upayload_fifo_hva_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_hva_overf_np(unsigned int upayload_fifo1_hva_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_overf_np(unsigned int upayload_fifo1_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_overf_np(unsigned int upayload_fifo_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_hva_overf(unsigned int upayload_fifo_hva_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_hva_overf(unsigned int upayload_fifo1_hva_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_overf(unsigned int upayload_fifo1_overf); +int iSetOSCH_OVERFLOW_INT_0_dbell_fifo_overf(unsigned int udbell_fifo_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_overf(unsigned int upayload_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_cpath_q2_fifo_overf(unsigned int ucpath_q2_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_cpath_q1_fifo_overf(unsigned int ucpath_q1_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_cpath_q0_fifo_overf(unsigned int ucpath_q0_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_ceqe_tx_fifo_overf(unsigned int uceqe_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_atomic_tx_fifo_overf(unsigned int uatomic_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_msi_tx_fifo_overf(unsigned int umsi_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_cpld_fifo_overf(unsigned int ucpld_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q4_fifo_overf(unsigned int udpath_q4_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q3_fifo_overf(unsigned int udpath_q3_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q2_fifo_overf(unsigned int udpath_q2_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q1_fifo_overf(unsigned int udpath_q1_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q0_fifo_overf(unsigned int udpath_q0_fifo_overf); +int iSetOSCH_OVERFLOW_INT_EN_0_atomic64_tx_fifo_overf_int_en(unsigned int uatomic64_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_hva_overf_np_int_en(unsigned int upayload_fifo_hva_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_hva_overf_np_int_en(unsigned int upayload_fifo1_hva_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_overf_np_int_en(unsigned int upayload_fifo1_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_overf_np_int_en(unsigned int upayload_fifo_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_hva_overf_int_en(unsigned int upayload_fifo_hva_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_hva_overf_int_en(unsigned int upayload_fifo1_hva_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_overf_int_en(unsigned int upayload_fifo1_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_dbell_fifo_overf_int_en(unsigned int udbell_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_overf_int_en(unsigned int upayload_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_cpath_q2_fifo_overf_int_en(unsigned int ucpath_q2_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_cpath_q1_fifo_overf_int_en(unsigned int ucpath_q1_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_cpath_q0_fifo_overf_int_en(unsigned int ucpath_q0_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_ceqe_tx_fifo_overf_int_en(unsigned int uceqe_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_atomic_tx_fifo_overf_int_en(unsigned int uatomic_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_msi_tx_fifo_overf_int_en(unsigned int umsi_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_cpld_fifo_overf_int_en(unsigned int ucpld_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q4_fifo_overf_int_en(unsigned int udpath_q4_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q3_fifo_overf_int_en(unsigned int udpath_q3_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q2_fifo_overf_int_en(unsigned int udpath_q2_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q1_fifo_overf_int_en(unsigned int udpath_q1_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q0_fifo_overf_int_en(unsigned int udpath_q0_fifo_overf_int_en); +int iSetOSCH_CRT_ERR_cur_port_timeout(unsigned int ucur_port_timeout); +int iSetOSCH_CRT_ERR_port_sch_tlp_err(unsigned int uport_sch_tlp_err); +int iSetOSCH_CRT_ERR_port_sch_tlp_err_hva(unsigned int uport_sch_tlp_err_hva); +int iSetOSCH_CRT_ERR_port_sch_tlp_err_npcpl(unsigned int uport_sch_tlp_err_npcpl); +int iSetOSCH_CRT_ERR_port_sch_tlp_err_hva_npcpl(unsigned int uport_sch_tlp_err_hva_npcpl); +int iSetOSCH_CRT_ERR_cpi_osch_ceqe_drop_req(unsigned int ucpi_osch_ceqe_drop_req); +int iSetOSCH_CRT_ERR_port_sch_phy_addr_err(unsigned int uport_sch_phy_addr_err); +int iSetOSCH_CRT_ERR_port_sch_phy_addr_err_npcpl(unsigned int uport_sch_phy_addr_err_npcpl); +int iSetOSCH_UNCRT_ERR_dpath_req_drop_p(unsigned int udpath_req_drop_p); +int iSetOSCH_UNCRT_ERR_cpi_osch_int_ceq_credit_err_p(unsigned int ucpi_osch_int_ceq_credit_err_p); +int iSetOSCH_UNCRT_ERR_osch_loss_sopeop_err(unsigned int uosch_loss_sopeop_err); +int iSetOSCH_CRT_ERR_INT_EN_cur_port_timeout_int_en(unsigned int ucur_port_timeout_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_int_en(unsigned int uport_sch_tlp_err_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_hva_int_en(unsigned int uport_sch_tlp_err_hva_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_npcpl_int_en(unsigned int uport_sch_tlp_err_npcpl_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_hva_npcpl_int_en(unsigned int uport_sch_tlp_err_hva_npcpl_int_en); +int iSetOSCH_CRT_ERR_INT_EN_cpi_osch_ceqe_drop_req_int_en(unsigned int ucpi_osch_ceqe_drop_req_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_phy_addr_err_int_en(unsigned int uport_sch_phy_addr_err_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_phy_addr_err_npcpl_int_en(unsigned int uport_sch_phy_addr_err_npcpl_int_en); +int iSetOSCH_UNCRT_ERR_INT_EN_dpath_req_drop_p_int_en(unsigned int udpath_req_drop_p_int_en); +int iSetOSCH_UNCRT_ERR_INT_EN_cpi_osch_int_ceq_credit_err_p_int_en(unsigned int ucpi_osch_int_ceq_credit_err_p_int_en); +int iSetOSCH_UNCRT_ERR_INT_EN_osch_loss_sopeop_err_int_en(unsigned int uosch_loss_sopeop_err_int_en); +int iSetOSCH_ACTIVE_EN_CFG_active_en_cfg_value(unsigned int uactive_en_cfg_value); +int iSetOSCH_ACTIVE_EN_CFG_active_en_cfg_enable(unsigned int uactive_en_cfg_enable); +int iSetOSCH_NL2NIC_OUTSTANDING_BP_CFG_cfg_non_l2nic_outstanding_bp_th(unsigned int ucfg_non_l2nic_outstanding_bp_th); +int iSetOSCH_NL2NIC_OUTSTANDING_BP_CFG_cfg_non_l2nic_outstanding_bp_en(unsigned int ucfg_non_l2nic_outstanding_bp_en); +int iSetCEQ_CLS_FIFO_ST_ERR_ceq_cls_fifo_st_err(unsigned int uceq_cls_fifo_st_err); +int iSetGLB_CQE_CI_D_CHL_glb_ceqe_sch_period(unsigned int uglb_ceqe_sch_period); +int iSetGLB_CQE_CI_D_CHL_glb_osch_non_l2nic_outstanding_cfg(unsigned int uglb_osch_non_l2nic_outstanding_cfg); +int iSetGLB_DMA_SO_RO_REPLACE_glb_dma_so_ro_cfg(unsigned int uglb_dma_so_ro_cfg); +int iSetGLB_DMA_SO_RO_REPLACE_glb_dma_so_ro_replace_mode(unsigned int uglb_dma_so_ro_replace_mode); +int iSetGLB_OSCH_RLS_TAG_EN_glb_osch_rls_tag_en(unsigned int uglb_osch_rls_tag_en); +int iSetGLB_OSCH_TIMEOUT_glb_osch_timeout_cfg(unsigned int uglb_osch_timeout_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port4_cqe_credit_cfg(unsigned int uport4_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port3_cqe_credit_cfg(unsigned int uport3_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port2_cqe_credit_cfg(unsigned int uport2_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port1_cqe_credit_cfg(unsigned int uport1_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port0_cqe_credit_cfg(unsigned int uport0_cqe_credit_cfg); +int iSetGLB_OSCH_ADDR_HI_LMT_H_glb_osch_addr_hi_lmt_h(unsigned int uglb_osch_addr_hi_lmt_h); +int iSetGLB_OSCH_ADDR_HI_LMT_L_glb_osch_addr_hi_lmt_l(unsigned int uglb_osch_addr_hi_lmt_l); +int iSetGLB_OSCH_ADDR_LO_LMT_H_glb_osch_addr_lo_lmt_h(unsigned int uglb_osch_addr_lo_lmt_h); +int iSetGLB_OSCH_ADDR_LO_LMT_L_glb_osch_addr_lo_lmt_l(unsigned int uglb_osch_addr_lo_lmt_l); +int iSetGLB_OSCH_ADDR_OUT_RANGE_H_glb_osch_addr_out_range_h(unsigned int uglb_osch_addr_out_range_h); +int iSetGLB_OSCH_ADDR_OUT_RANGE_L_glb_osch_addr_out_range_l(unsigned int uglb_osch_addr_out_range_l); +int iSetOSCH_PAYLOAD_FIFO1_CTRL_osch_payload_fifo1_ctrl_all_port(unsigned int uosch_payload_fifo1_ctrl_all_port); +int iSetOSCH_DBELL_FIFO_CTRL_osch_dbell_fifo_ctrl_all_port(unsigned int uosch_dbell_fifo_ctrl_all_port); +int iSetCFG_DOORBELL_WR_CMD_EN_cfg_doorbell_wr_cmd_en(unsigned int ucfg_doorbell_wr_cmd_en); +int iSetCFG_DOORBELL_CRDT_INITIAL_cfg_doorbell_crdt_initial(unsigned int ucfg_doorbell_crdt_initial); +int iSetCFG_DPATH_XTS_RD_cfg_dpath_xts_rd_chl(unsigned int ucfg_dpath_xts_rd_chl); +int iSetCFG_DPATH_XTS_RD_cfg_dpath_xts_rd_en(unsigned int ucfg_dpath_xts_rd_en); +int iSetCFG_ROUND_BIT_CHECK_MOD_cfg_round_bit_check_mod(unsigned int ucfg_round_bit_check_mod); +int iSetCFG_PORT1_TO_PORT0_MODE_cfg_port1_to_port0_mode(unsigned int ucfg_port1_to_port0_mode); +int iSetCFG_NON_L2NIC_LOOP2_EDGE_EN_cfg_non_l2nic_loop2_edge_en(unsigned int ucfg_non_l2nic_loop2_edge_en); +int iSetCFG_CUR_CPL_TIMEOUT_DROP_MAX_cfg_cur_cpl_timeout_drop_max(unsigned int ucfg_cur_cpl_timeout_drop_max); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT0_osch_tlp_npcpl_drop_count_port0(unsigned int uosch_tlp_npcpl_drop_count_port0); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT1_osch_tlp_npcpl_drop_count_port1(unsigned int uosch_tlp_npcpl_drop_count_port1); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT2_osch_tlp_npcpl_drop_count_port2(unsigned int uosch_tlp_npcpl_drop_count_port2); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT3_osch_tlp_npcpl_drop_count_port3(unsigned int uosch_tlp_npcpl_drop_count_port3); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT4_osch_tlp_npcpl_drop_count_port4(unsigned int uosch_tlp_npcpl_drop_count_port4); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port3(unsigned int uosch_tlp_npcpl_err_count_port3); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port2(unsigned int uosch_tlp_npcpl_err_count_port2); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port1(unsigned int uosch_tlp_npcpl_err_count_port1); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port0(unsigned int uosch_tlp_npcpl_err_count_port0); +int iSetOSCH_TLP_NPCPL_ERROR_CNT1_osch_tlp_npcpl_err_count_port4(unsigned int uosch_tlp_npcpl_err_count_port4); +int iSetOSCH_TLP_NPCPL_DROP_CNT0_osch_tlp_npcpl_drop_count0(unsigned int uosch_tlp_npcpl_drop_count0); +int iSetOSCH_TLP_NPCPL_DROP_CNT1_osch_tlp_npcpl_drop_count1(unsigned int uosch_tlp_npcpl_drop_count1); +int iSetOSCH_TLP_NPCPL_DROP_CNT2_osch_tlp_npcpl_drop_count2(unsigned int uosch_tlp_npcpl_drop_count2); +int iSetOSCH_TLP_NPCPL_DROP_CNT3_osch_tlp_npcpl_drop_count3(unsigned int uosch_tlp_npcpl_drop_count3); +int iSetOSCH_TLP_NPCPL_DROP_CNT4_osch_tlp_npcpl_drop_count4(unsigned int uosch_tlp_npcpl_drop_count4); +int iSetOSCH_TLP_NPCPL_DROP_CNT5_osch_tlp_npcpl_drop_count5(unsigned int uosch_tlp_npcpl_drop_count5); +int iSetOSCH_TLP_NPCPL_DROP_CNT6_osch_tlp_npcpl_drop_count6(unsigned int uosch_tlp_npcpl_drop_count6); +int iSetOSCH_TLP_NPCPL_DROP_CNT7_osch_tlp_npcpl_drop_count7(unsigned int uosch_tlp_npcpl_drop_count7); +int iSetOSCH_TLP_NPCPL_DROP_CNT8_osch_tlp_npcpl_drop_count8(unsigned int uosch_tlp_npcpl_drop_count8); +int iSetOSCH_TLP_NPCPL_DROP_CNT9_osch_tlp_npcpl_drop_count9(unsigned int uosch_tlp_npcpl_drop_count9); +int iSetOSCH_TLP_NPCPL_DROP_CNT10_osch_tlp_npcpl_drop_count10(unsigned int uosch_tlp_npcpl_drop_count10); +int iSetOSCH_TLP_NPCPL_DROP_CNT11_osch_tlp_npcpl_drop_count11(unsigned int uosch_tlp_npcpl_drop_count11); +int iSetOSCH_TLP_NPCPL_DROP_CNT12_osch_tlp_npcpl_drop_count12(unsigned int uosch_tlp_npcpl_drop_count12); +int iSetOSCH_TLP_NPCPL_DROP_CNT13_osch_tlp_npcpl_drop_count13(unsigned int uosch_tlp_npcpl_drop_count13); +int iSetOSCH_TLP_NPCPL_DROP_CNT14_osch_tlp_npcpl_drop_count14(unsigned int uosch_tlp_npcpl_drop_count14); +int iSetOSCH_TLP_NPCPL_DROP_CNT15_osch_tlp_npcpl_drop_count15(unsigned int uosch_tlp_npcpl_drop_count15); +int iSetOSCH_TLP_HVA_P_DROP_CNT0_osch_tlp_hva_p_drop_count0(unsigned int uosch_tlp_hva_p_drop_count0); +int iSetOSCH_TLP_HVA_P_DROP_CNT1_osch_tlp_hva_p_drop_count1(unsigned int uosch_tlp_hva_p_drop_count1); +int iSetOSCH_TLP_HVA_P_DROP_CNT2_osch_tlp_hva_p_drop_count2(unsigned int uosch_tlp_hva_p_drop_count2); +int iSetOSCH_TLP_HVA_P_DROP_CNT3_osch_tlp_hva_p_drop_count3(unsigned int uosch_tlp_hva_p_drop_count3); +int iSetOSCH_TLP_HVA_P_DROP_CNT4_osch_tlp_hva_p_drop_count4(unsigned int uosch_tlp_hva_p_drop_count4); +int iSetOSCH_TLP_HVA_P_DROP_CNT5_osch_tlp_hva_p_drop_count5(unsigned int uosch_tlp_hva_p_drop_count5); +int iSetOSCH_TLP_HVA_P_DROP_CNT6_osch_tlp_hva_p_drop_count6(unsigned int uosch_tlp_hva_p_drop_count6); +int iSetOSCH_TLP_HVA_P_DROP_CNT7_osch_tlp_hva_p_drop_count7(unsigned int uosch_tlp_hva_p_drop_count7); +int iSetOSCH_TLP_HVA_P_DROP_CNT8_osch_tlp_hva_p_drop_count8(unsigned int uosch_tlp_hva_p_drop_count8); +int iSetOSCH_TLP_HVA_P_DROP_CNT9_osch_tlp_hva_p_drop_count9(unsigned int uosch_tlp_hva_p_drop_count9); +int iSetOSCH_TLP_HVA_P_DROP_CNT10_osch_tlp_hva_p_drop_count10(unsigned int uosch_tlp_hva_p_drop_count10); +int iSetOSCH_TLP_HVA_P_DROP_CNT11_osch_tlp_hva_p_drop_count11(unsigned int uosch_tlp_hva_p_drop_count11); +int iSetOSCH_TLP_HVA_P_DROP_CNT12_osch_tlp_hva_p_drop_count12(unsigned int uosch_tlp_hva_p_drop_count12); +int iSetOSCH_TLP_HVA_P_DROP_CNT13_osch_tlp_hva_p_drop_count13(unsigned int uosch_tlp_hva_p_drop_count13); +int iSetOSCH_TLP_HVA_P_DROP_CNT14_osch_tlp_hva_p_drop_count14(unsigned int uosch_tlp_hva_p_drop_count14); +int iSetOSCH_TLP_HVA_P_DROP_CNT15_osch_tlp_hva_p_drop_count15(unsigned int uosch_tlp_hva_p_drop_count15); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT0_osch_tlp_hva_npcpl_drop_count0(unsigned int uosch_tlp_hva_npcpl_drop_count0); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT1_osch_tlp_hva_npcpl_drop_count1(unsigned int uosch_tlp_hva_npcpl_drop_count1); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT2_osch_tlp_hva_npcpl_drop_count2(unsigned int uosch_tlp_hva_npcpl_drop_count2); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT3_osch_tlp_hva_npcpl_drop_count3(unsigned int uosch_tlp_hva_npcpl_drop_count3); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT4_osch_tlp_hva_npcpl_drop_count4(unsigned int uosch_tlp_hva_npcpl_drop_count4); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT5_osch_tlp_hva_npcpl_drop_count5(unsigned int uosch_tlp_hva_npcpl_drop_count5); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT6_osch_tlp_hva_npcpl_drop_count6(unsigned int uosch_tlp_hva_npcpl_drop_count6); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT7_osch_tlp_hva_npcpl_drop_count7(unsigned int uosch_tlp_hva_npcpl_drop_count7); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT8_osch_tlp_hva_npcpl_drop_count8(unsigned int uosch_tlp_hva_npcpl_drop_count8); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT9_osch_tlp_hva_npcpl_drop_count9(unsigned int uosch_tlp_hva_npcpl_drop_count9); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT10_osch_tlp_hva_npcpl_drop_count10(unsigned int uosch_tlp_hva_npcpl_drop_count10); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT11_osch_tlp_hva_npcpl_drop_count11(unsigned int uosch_tlp_hva_npcpl_drop_count11); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT12_osch_tlp_hva_npcpl_drop_count12(unsigned int uosch_tlp_hva_npcpl_drop_count12); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT13_osch_tlp_hva_npcpl_drop_count13(unsigned int uosch_tlp_hva_npcpl_drop_count13); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT14_osch_tlp_hva_npcpl_drop_count14(unsigned int uosch_tlp_hva_npcpl_drop_count14); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT15_osch_tlp_hva_npcpl_drop_count15(unsigned int uosch_tlp_hva_npcpl_drop_count15); +int iSetOSCH_TLP_DROP_COUNT_MODE_osch_tlp_drop_count_mode(unsigned int uosch_tlp_drop_count_mode); +int iSetOSCH_NPCPL_PERF_WATCH_BYTE_osch_npcpl_perf_watch_byte(unsigned int uosch_npcpl_perf_watch_byte); +int iSetOSCH_NPCPL_PERF_WATCH_TLP_osch_npcpl_perf_watch_tlp(unsigned int uosch_npcpl_perf_watch_tlp); +int iSetOSCH_HVA_P_PERF_WATCH_BYTE_osch_hva_p_perf_watch_byte(unsigned int uosch_hva_p_perf_watch_byte); +int iSetOSCH_HVA_P_PERF_WATCH_TLP_osch_hva_p_perf_watch_tlp(unsigned int uosch_hva_p_perf_watch_tlp); +int iSetOSCH_HVA_NPCPL_PERF_WATCH_BYTE_osch_hva_npcpl_perf_watch_byte(unsigned int uosch_hva_npcpl_perf_watch_byte); +int iSetOSCH_HVA_NPCPL_PERF_WATCH_TLP_osch_hva_npcpl_perf_watch_tlp(unsigned int uosch_hva_npcpl_perf_watch_tlp); + + +#endif // CPI_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_dfx_glb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_dfx_glb_reg_offset.h new file mode 100644 index 000000000..9b0618cf7 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_dfx_glb_reg_offset.h @@ -0,0 +1,236 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2016, Hisilicon Technologies Co. Ltd. +// File name : cpi_dfx_glb_reg_offset.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Author : xxx +// Version : V100 +// Date : 2014/5/8 +// Description : Hi 1822 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V4.0.2.5 History : xxx 2016/10/25 15:05:13 +// Create file +// ****************************************************************************** + +#ifndef CPI_DFX_GLB_REG_OFFSET_H +#define CPI_DFX_GLB_REG_OFFSET_H + +/* CPI_DFX_GLB Base address of Module's Register */ +#define HI1822_CPI_DFX_GLB_BASE (0x41af000) +#define CPI_DFX_TYPE_GLB (0x0) + +/* **************************************************************************** */ +/* HI1822 CPI_DFX_GLB Registers' Definitions */ +/* **************************************************************************** */ + +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_CFG_REG (HI1822_CPI_DFX_GLB_BASE + 0x0) /* CPI debug control */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_MRD_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x4) /* CPI debug Rx Mrd TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_MWR_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x8) /* CPI debug Rx Mwr TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_CPL_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0xC) /* CPI debug Rx CPL/CPLD TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_DBL_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x10) /* CPI debug Rx UR Mrd TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_DWQE_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x14) /* CPI debug Rx UR Mrd TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_ESL__TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x18) /* CPI debug Rx others TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_BAR_HIT6_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x1C) /* CPI debug Rx BAR hit == 6 TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x400) /* CPI BP WATCH Status */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_WINDOW_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x404) /* CPI backpressure watch window */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_BITMAP_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x408) /* CPI backpressure watch bitmap */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_START_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x40C) /* CPI backpressure watch start */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x410) /* CPI backpressure watch counter */ +#define HI1822_CPI_DFX_GLB_GLB_CSR_TIMEOUT_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x414) +#define HI1822_CPI_DFX_GLB_DWQE_API_NO_ENOUGH_DATA_REG (HI1822_CPI_DFX_GLB_BASE + 0x418) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_NO_ENOUGH_DATA_REG (HI1822_CPI_DFX_GLB_BASE + 0x41C) +#define HI1822_CPI_DFX_GLB_NORM_DBL_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x420) +#define HI1822_CPI_DFX_GLB_NORM_DBL_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x424) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x428) +#define HI1822_CPI_DFX_GLB_DWQE_API_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x42C) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_MSK_REG (HI1822_CPI_DFX_GLB_BASE + 0x430) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_CNT_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x434) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_ON_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x438) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_OFF_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x43C) +#define HI1822_CPI_DFX_GLB_DWQE_REQ_BUF_BGN_REG (HI1822_CPI_DFX_GLB_BASE + 0x440) +#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_IN_TX_REG (HI1822_CPI_DFX_GLB_BASE + 0x444) +#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_NO_BUF_REG (HI1822_CPI_DFX_GLB_BASE + 0x448) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_WITHOUT_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x44C) +#define HI1822_CPI_DFX_GLB_DWQE_TX_DBL_AFTER_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x450) +#define HI1822_CPI_DFX_GLB_DWQE_NO_DBL_AFTER_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x454) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_OVERWRITE_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x458) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_AGING_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x45C) +#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_PUSH_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x460) +#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_POP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x464) +#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x468) +#define HI1822_CPI_DFX_GLB_CPI_DPATH_O_FSM_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x46C) +#define HI1822_CPI_DFX_GLB_CPI_DPATH_O_CNT_TYPE_REG (HI1822_CPI_DFX_GLB_BASE + 0x470) +#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_INVLD_REG (HI1822_CPI_DFX_GLB_BASE + 0x474) +#define HI1822_CPI_DFX_GLB_DWQE_SW_FORCE_DROP_REG (HI1822_CPI_DFX_GLB_BASE + 0x478) +#define HI1822_CPI_DFX_GLB_ICTL_DBL_REQ_SOP_NULL_REG (HI1822_CPI_DFX_GLB_BASE + 0x47C) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x480) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x484) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x488) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x48C) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x490) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x494) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x498) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x49C) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A0) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A4) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A8) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x4AC) +#define HI1822_CPI_DFX_GLB_CEQ_CI_SW_WR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B0) +#define HI1822_CPI_DFX_GLB_AEQ_CI_SW_WR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B4) +#define HI1822_CPI_DFX_GLB_CEQ_TX_INT_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B8) +#define HI1822_CPI_DFX_GLB_AEQ_TX_INT_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4BC) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_WR_PCIE_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C0) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_WR_UCPU_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C4) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_RD_PCIE_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C8) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_RD_UCPU_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4CC) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_OSCH_CPL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D0) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_ICTL_CPL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D4) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_APICTL_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D8) +#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_AEQE_TO_DST_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4DC) +#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_AEQE_TO_SRC_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E0) +#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_STAT_TO_SRC_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E4) +#define HI1822_CPI_DFX_GLB_CPI_UCPU_MB_AEQE_TO_DST_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E8) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_AEQ_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4EC) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_CEQ_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F0) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_API_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F4) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_INTCTL_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F8) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_UPITF_CLP_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4FC) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR0_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x500) /* CPI internal RAM ECC error injection */ +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x504) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x508) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x50C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x510) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x514) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x518) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x51C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x520) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x524) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x528) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x52C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x530) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x534) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x538) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x53C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x540) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x544) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x548) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x54C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x550) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x554) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x558) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x55C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x560) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x564) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x568) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x56C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x570) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x574) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x578) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x57C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR8_REG (HI1822_CPI_DFX_GLB_BASE + 0x580) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x590) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x594) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x598) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x59C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A0) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A4) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A8) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x5AC) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR8_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B0) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR9_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B4) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR10_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B8) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C0) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C4) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED2_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C8) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED3_REG (HI1822_CPI_DFX_GLB_BASE + 0x5CC) +#define HI1822_CPI_DFX_GLB_GLB_CPI_UNCRT_ERR_CODE0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D0) +#define HI1822_CPI_DFX_GLB_GLB_CPI_UNCRT_ERR_CODE1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D4) +#define HI1822_CPI_DFX_GLB_GLB_CPI_CRT_ERR_CODE0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D8) +#define HI1822_CPI_DFX_GLB_GLB_CPI_CRT_ERR_CODE1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5DC) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E0) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E4) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG2_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E8) +#define HI1822_CPI_DFX_GLB_ICTL_RX_MWR_TLP_PASS_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F0) +#define HI1822_CPI_DFX_GLB_ICTL_RX_MWR_TLP_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F4) +#define HI1822_CPI_DFX_GLB_ICTL_RX_MRD_TLP_PASS_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F8) +#define HI1822_CPI_DFX_GLB_ICTL_RX_UNS_NP_TLP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5FC) +#define HI1822_CPI_DFX_GLB_PCIE_ICTL_SOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x600) +#define HI1822_CPI_DFX_GLB_PCIE_ICTL_EOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x604) +#define HI1822_CPI_DFX_GLB_ICTL_IPUSH_SOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x608) +#define HI1822_CPI_DFX_GLB_ICTL_IPUSH_EOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x60C) +#define HI1822_CPI_DFX_GLB_GLB_MB_GRP_TX_REQ_REG (HI1822_CPI_DFX_GLB_BASE + 0x610) +#define HI1822_CPI_DFX_GLB_GLB_MB_IN_GRP_TX_REQ_REG (HI1822_CPI_DFX_GLB_BASE + 0x614) +#define HI1822_CPI_DFX_GLB_GLB_MB_GRP_GRANT_REG (HI1822_CPI_DFX_GLB_BASE + 0x618) +#define HI1822_CPI_DFX_GLB_GLB_MB_IN_GRP_GRANT_REG (HI1822_CPI_DFX_GLB_BASE + 0x61C) +#define HI1822_CPI_DFX_GLB_GLB_MB_TX_START_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x620) +#define HI1822_CPI_DFX_GLB_GLB_MB_TX_ILLEGAL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x624) +#define HI1822_CPI_DFX_GLB_GLB_MB_TX_ILLEGAL_CODE_REG (HI1822_CPI_DFX_GLB_BASE + 0x628) +#define HI1822_CPI_DFX_GLB_GLB_MB_FSM_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x62C) +#define HI1822_CPI_DFX_GLB_DFX_DPATH_O_HISTORY_REG (HI1822_CPI_DFX_GLB_BASE + 0x630) +#define HI1822_CPI_DFX_GLB_DFX_DPATH_O_STATUS_REG (HI1822_CPI_DFX_GLB_BASE + 0x634) +#define HI1822_CPI_DFX_GLB_ICTL_INBD_FIFO_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x638) +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_INC_CFG_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x640) /* non-MAC Timestamp timer configuration */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_CALIBRATION_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x644) /* non-MAC Timestamp timer calibration */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA0_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x648) /* non-MAC Timestamp timer write data 0 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA1_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x64C) /* non-MAC Timestamp timer write data 1 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA2_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x650) /* non-MAC Timestamp timer write data 2 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA0_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x654) /* non-MAC Timestamp timer read data 0 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA1_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x658) /* non-MAC Timestamp timer read data 1 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA2_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x65C) /* non-MAC Timestamp timer read data 2 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_UP_EN_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x660) /* non-MAC Timestamp timer update enable */ +#define HI1822_CPI_DFX_GLB_NON_PTP_DSTR_CFG_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x664) /* non-MAC Timestamp distribute configuration */ +#define HI1822_CPI_DFX_GLB_PCIE_PENDING_TAG_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x670) /* 接收来自PCIe的数目 */ +#define HI1822_CPI_DFX_GLB_ICTL_SND_ERR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x674) /* 发送给PCIe AER的数目 */ +#define HI1822_CPI_DFX_GLB_ICTL_RX_CPLD_TLP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x678) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x680) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x684) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x688) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x68C) +#define HI1822_CPI_DFX_GLB_NORM_DBL_RX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x690) +#define HI1822_CPI_DFX_GLB_NORM_DBL_FORCE_DROP_REG (HI1822_CPI_DFX_GLB_BASE + 0x694) +#define HI1822_CPI_DFX_GLB_DWQE_RX_BUF_BGN_REG (HI1822_CPI_DFX_GLB_BASE + 0x698) +#define HI1822_CPI_DFX_GLB_DWQE_ILLEGAL_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x69C) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_FORCE_DROP_NO_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A0) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_FORCE_DROP_AFT_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A4) +#define HI1822_CPI_DFX_GLB_AEQ_FSM_DBG_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A8) +#define HI1822_CPI_DFX_GLB_CEQ_FSM_DBG_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x6AC) +#define HI1822_CPI_DFX_GLB_GLB_UCPU_MSI_FUNC_IDX_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6B0) /* the function index when ucpu access CSRs in the INT_CTL */ +#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_CTL_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6B4) /* the control register to measure the inbound itf */ +#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6B8) /* the result for the window detect for the mode */ +#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6BC) /* the result for the window detect for the TLP */ +#define HI1822_CPI_DFX_GLB_GLB_DBG_CNT_DBL_GRP_EN_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C0) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_TIMER_CFG_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C4) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CFG_PORT01_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C8) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CFG_PORT23_REG (HI1822_CPI_DFX_GLB_BASE + 0x6CC) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D0) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D4) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D8) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x6DC) + +#endif // CPI_DFX_GLB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_reg_offset.h new file mode 100644 index 000000000..78829c792 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_reg_offset.h @@ -0,0 +1,4698 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpi_reg_offset.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Author : xxx +// Version : V100 +// Date : +// Description : Hi 1823 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V5.1 History : xxx 2020/07/27 20:37:29 Create +// file +// ****************************************************************************** + +#ifndef CPI_REG_OFFSET_H +#define CPI_REG_OFFSET_H + +/* msi_cap_csr Base address of Module's Register */ +#define CSR_MSI_CAP_CSR_BASE (0x43F9000) + +/* **************************************************************************** */ +/* msi_cap_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MSI_CAP_CSR_MSI_CAP_CSR_DW0_0_REG (CSR_MSI_CAP_CSR_BASE + 0x0) +#define CSR_MSI_CAP_CSR_MSI_CAP_CSR_DW0_1_REG (CSR_MSI_CAP_CSR_BASE + 0x4) + +/* up_itf_csr Base address of Module's Register */ +#define CSR_UP_ITF_CSR_BASE (0x43AE000) + +/* **************************************************************************** */ +/* up_itf_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_UP_ITF_CSR_UP_PCIE_STATUS_REG (CSR_UP_ITF_CSR_BASE + 0x0) /* PCIe端口link实时状态。 */ +#define CSR_UP_ITF_CSR_UP_INT_STATUS_REG (CSR_UP_ITF_CSR_BASE + 0x4) /* 中断状态寄存器；写1清除对应比特中断。 */ +#define CSR_UP_ITF_CSR_UP_INT_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x8) /* uP interrupt control */ +#define CSR_UP_ITF_CSR_UP_DIRECT_ACCESS_LOCK_REG (CSR_UP_ITF_CSR_BASE + 0xC) /* direct access lock */ +#define CSR_UP_ITF_CSR_UP_AEQ_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x10) /* uP AEQ length and AEQE size */ +#define CSR_UP_ITF_CSR_UP_AEQ_BA_REG (CSR_UP_ITF_CSR_BASE + 0x14) /* uP AEQ ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_AEQ_CI_REG (CSR_UP_ITF_CSR_BASE + 0x18) /* uP AEQ ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_AEQ_PI_REG (CSR_UP_ITF_CSR_BASE + 0x1C) /* uP AEQ ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x20) /* uP API Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_BA_REG (CSR_UP_ITF_CSR_BASE + 0x24) /* uP API Rx ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_CI_REG (CSR_UP_ITF_CSR_BASE + 0x28) /* uP API Rx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_PI_REG (CSR_UP_ITF_CSR_BASE + 0x2C) /* uP API Rx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TX_API_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x30) /* uP API Tx control register */ +#define CSR_UP_ITF_CSR_UP_TX_API_CTL_VIO_REG (CSR_UP_ITF_CSR_BASE + 0x34) /* mpu tx api ctrl register for VirtIO/NVMe \ + */ +#define CSR_UP_ITF_CSR_UP_RB_TIMEOUT_REG (CSR_UP_ITF_CSR_BASE + 0x38) /* UP RINGBuffer申请时间约束。 */ +#define CSR_UP_ITF_CSR_UP_XFER_CTRL_REG (CSR_UP_ITF_CSR_BASE + 0x3C) /* UP AXI接口控制寄存器 */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_0_REG (CSR_UP_ITF_CSR_BASE + 0x40) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_1_REG (CSR_UP_ITF_CSR_BASE + 0x44) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_2_REG (CSR_UP_ITF_CSR_BASE + 0x48) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_3_REG (CSR_UP_ITF_CSR_BASE + 0x4C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_4_REG (CSR_UP_ITF_CSR_BASE + 0x50) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_5_REG (CSR_UP_ITF_CSR_BASE + 0x54) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_6_REG (CSR_UP_ITF_CSR_BASE + 0x58) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_7_REG (CSR_UP_ITF_CSR_BASE + 0x5C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_8_REG (CSR_UP_ITF_CSR_BASE + 0x60) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_9_REG (CSR_UP_ITF_CSR_BASE + 0x64) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_10_REG (CSR_UP_ITF_CSR_BASE + 0x68) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_11_REG (CSR_UP_ITF_CSR_BASE + 0x6C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_12_REG (CSR_UP_ITF_CSR_BASE + 0x70) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_13_REG (CSR_UP_ITF_CSR_BASE + 0x74) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_14_REG (CSR_UP_ITF_CSR_BASE + 0x78) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_15_REG (CSR_UP_ITF_CSR_BASE + 0x7C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_16_REG (CSR_UP_ITF_CSR_BASE + 0x80) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_17_REG (CSR_UP_ITF_CSR_BASE + 0x84) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_18_REG (CSR_UP_ITF_CSR_BASE + 0x88) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_19_REG (CSR_UP_ITF_CSR_BASE + 0x8C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_20_REG (CSR_UP_ITF_CSR_BASE + 0x90) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_21_REG (CSR_UP_ITF_CSR_BASE + 0x94) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_22_REG (CSR_UP_ITF_CSR_BASE + 0x98) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_23_REG (CSR_UP_ITF_CSR_BASE + 0x9C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_24_REG (CSR_UP_ITF_CSR_BASE + 0xA0) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_25_REG (CSR_UP_ITF_CSR_BASE + 0xA4) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_26_REG (CSR_UP_ITF_CSR_BASE + 0xA8) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_27_REG (CSR_UP_ITF_CSR_BASE + 0xAC) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_28_REG (CSR_UP_ITF_CSR_BASE + 0xB0) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_29_REG (CSR_UP_ITF_CSR_BASE + 0xB4) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_30_REG (CSR_UP_ITF_CSR_BASE + 0xB8) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_31_REG (CSR_UP_ITF_CSR_BASE + 0xBC) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_INT_COLL_REG (CSR_UP_ITF_CSR_BASE + 0xC8) /* uP interrupt collection. */ +#define CSR_UP_ITF_CSR_UP_INT_TIMEOUT_REG (CSR_UP_ITF_CSR_BASE + 0xCC) /* uP interrupt collection timeout. */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_0_REG (CSR_UP_ITF_CSR_BASE + 0xD0) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_1_REG (CSR_UP_ITF_CSR_BASE + 0xF0) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_2_REG (CSR_UP_ITF_CSR_BASE + 0x110) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_3_REG (CSR_UP_ITF_CSR_BASE + 0x130) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_0_REG (CSR_UP_ITF_CSR_BASE + 0xD4) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_1_REG (CSR_UP_ITF_CSR_BASE + 0xF4) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_2_REG (CSR_UP_ITF_CSR_BASE + 0x114) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_3_REG (CSR_UP_ITF_CSR_BASE + 0x134) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_0_REG (CSR_UP_ITF_CSR_BASE + 0xD8) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_1_REG (CSR_UP_ITF_CSR_BASE + 0xF8) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_2_REG (CSR_UP_ITF_CSR_BASE + 0x118) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_3_REG (CSR_UP_ITF_CSR_BASE + 0x138) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_0_REG (CSR_UP_ITF_CSR_BASE + 0xDC) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_1_REG (CSR_UP_ITF_CSR_BASE + 0xFC) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_2_REG (CSR_UP_ITF_CSR_BASE + 0x11C) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_3_REG (CSR_UP_ITF_CSR_BASE + 0x13C) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_0_REG (CSR_UP_ITF_CSR_BASE + 0xE0) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_1_REG (CSR_UP_ITF_CSR_BASE + 0x100) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_2_REG (CSR_UP_ITF_CSR_BASE + 0x120) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_3_REG (CSR_UP_ITF_CSR_BASE + 0x140) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_0_REG (CSR_UP_ITF_CSR_BASE + 0xE4) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_1_REG (CSR_UP_ITF_CSR_BASE + 0x104) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_2_REG (CSR_UP_ITF_CSR_BASE + 0x124) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_3_REG (CSR_UP_ITF_CSR_BASE + 0x144) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_0_REG (CSR_UP_ITF_CSR_BASE + 0xE8) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_1_REG (CSR_UP_ITF_CSR_BASE + 0x108) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_2_REG (CSR_UP_ITF_CSR_BASE + 0x128) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_3_REG (CSR_UP_ITF_CSR_BASE + 0x148) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_0_REG (CSR_UP_ITF_CSR_BASE + 0xEC) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_1_REG (CSR_UP_ITF_CSR_BASE + 0x10C) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_2_REG (CSR_UP_ITF_CSR_BASE + 0x12C) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_3_REG (CSR_UP_ITF_CSR_BASE + 0x14C) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x150) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x170) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x190) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1B0) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x154) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x174) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x194) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1B4) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x158) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x178) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x198) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1B8) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x15C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x17C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x19C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1BC) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x160) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x180) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1A0) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1C0) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x164) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x184) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1A4) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1C4) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x168) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x188) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1A8) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1C8) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x16C) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x18C) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1AC) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1CC) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_CSR_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x200) /* UP访问系统CSR寄存器的控制寄存器 */ +#define CSR_UP_ITF_CSR_UP_CSR_DATA0_REG (CSR_UP_ITF_CSR_BASE + 0x204) /* UP访问CSR的数据寄存器0 */ +#define CSR_UP_ITF_CSR_UP_CSR_DATA1_REG (CSR_UP_ITF_CSR_BASE + 0x208) /* UP访问CSR的数据寄存器1 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_0_REG (CSR_UP_ITF_CSR_BASE + 0x300) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_1_REG (CSR_UP_ITF_CSR_BASE + 0x304) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_2_REG (CSR_UP_ITF_CSR_BASE + 0x308) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_3_REG (CSR_UP_ITF_CSR_BASE + 0x30C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_4_REG (CSR_UP_ITF_CSR_BASE + 0x310) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_5_REG (CSR_UP_ITF_CSR_BASE + 0x314) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_6_REG (CSR_UP_ITF_CSR_BASE + 0x318) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_7_REG (CSR_UP_ITF_CSR_BASE + 0x31C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_8_REG (CSR_UP_ITF_CSR_BASE + 0x320) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_9_REG (CSR_UP_ITF_CSR_BASE + 0x324) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_10_REG (CSR_UP_ITF_CSR_BASE + 0x328) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_11_REG (CSR_UP_ITF_CSR_BASE + 0x32C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_12_REG (CSR_UP_ITF_CSR_BASE + 0x330) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_13_REG (CSR_UP_ITF_CSR_BASE + 0x334) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_14_REG (CSR_UP_ITF_CSR_BASE + 0x338) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_15_REG (CSR_UP_ITF_CSR_BASE + 0x33C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_16_REG (CSR_UP_ITF_CSR_BASE + 0x340) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_17_REG (CSR_UP_ITF_CSR_BASE + 0x344) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_18_REG (CSR_UP_ITF_CSR_BASE + 0x348) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_19_REG (CSR_UP_ITF_CSR_BASE + 0x34C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_20_REG (CSR_UP_ITF_CSR_BASE + 0x350) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_21_REG (CSR_UP_ITF_CSR_BASE + 0x354) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_22_REG (CSR_UP_ITF_CSR_BASE + 0x358) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_23_REG (CSR_UP_ITF_CSR_BASE + 0x35C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_24_REG (CSR_UP_ITF_CSR_BASE + 0x360) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_25_REG (CSR_UP_ITF_CSR_BASE + 0x364) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_26_REG (CSR_UP_ITF_CSR_BASE + 0x368) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_27_REG (CSR_UP_ITF_CSR_BASE + 0x36C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_28_REG (CSR_UP_ITF_CSR_BASE + 0x370) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_29_REG (CSR_UP_ITF_CSR_BASE + 0x374) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_30_REG (CSR_UP_ITF_CSR_BASE + 0x378) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_31_REG (CSR_UP_ITF_CSR_BASE + 0x37C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_32_REG (CSR_UP_ITF_CSR_BASE + 0x380) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_33_REG (CSR_UP_ITF_CSR_BASE + 0x384) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_34_REG (CSR_UP_ITF_CSR_BASE + 0x388) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_35_REG (CSR_UP_ITF_CSR_BASE + 0x38C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_36_REG (CSR_UP_ITF_CSR_BASE + 0x390) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_37_REG (CSR_UP_ITF_CSR_BASE + 0x394) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_38_REG (CSR_UP_ITF_CSR_BASE + 0x398) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_39_REG (CSR_UP_ITF_CSR_BASE + 0x39C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_40_REG (CSR_UP_ITF_CSR_BASE + 0x3A0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_41_REG (CSR_UP_ITF_CSR_BASE + 0x3A4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_42_REG (CSR_UP_ITF_CSR_BASE + 0x3A8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_43_REG (CSR_UP_ITF_CSR_BASE + 0x3AC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_44_REG (CSR_UP_ITF_CSR_BASE + 0x3B0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_45_REG (CSR_UP_ITF_CSR_BASE + 0x3B4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_46_REG (CSR_UP_ITF_CSR_BASE + 0x3B8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_47_REG (CSR_UP_ITF_CSR_BASE + 0x3BC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_48_REG (CSR_UP_ITF_CSR_BASE + 0x3C0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_49_REG (CSR_UP_ITF_CSR_BASE + 0x3C4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_50_REG (CSR_UP_ITF_CSR_BASE + 0x3C8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_51_REG (CSR_UP_ITF_CSR_BASE + 0x3CC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_52_REG (CSR_UP_ITF_CSR_BASE + 0x3D0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_53_REG (CSR_UP_ITF_CSR_BASE + 0x3D4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_54_REG (CSR_UP_ITF_CSR_BASE + 0x3D8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_55_REG (CSR_UP_ITF_CSR_BASE + 0x3DC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_56_REG (CSR_UP_ITF_CSR_BASE + 0x3E0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_57_REG (CSR_UP_ITF_CSR_BASE + 0x3E4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_58_REG (CSR_UP_ITF_CSR_BASE + 0x3E8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_59_REG (CSR_UP_ITF_CSR_BASE + 0x3EC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_60_REG (CSR_UP_ITF_CSR_BASE + 0x3F0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_61_REG (CSR_UP_ITF_CSR_BASE + 0x3F4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_62_REG (CSR_UP_ITF_CSR_BASE + 0x3F8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_63_REG (CSR_UP_ITF_CSR_BASE + 0x3FC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_MEM_CTRL_REG (CSR_UP_ITF_CSR_BASE + 0x400) /* 接口Memory属性配置寄存器。保持为默认值。 */ +#define CSR_UP_ITF_CSR_UP_RB_DBGCTL_REG (CSR_UP_ITF_CSR_BASE + 0x404) /* UP RingBuffer Debug控制寄存器 */ +#define CSR_UP_ITF_CSR_UP_RB_DBGDAT0_REG (CSR_UP_ITF_CSR_BASE + 0x408) /* RingBuffer指针状态。 */ +#define CSR_UP_ITF_CSR_UP_RB_DBGDAT1_REG (CSR_UP_ITF_CSR_BASE + 0x40C) /* RingBuffer数据个数状态。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG0_REG (CSR_UP_ITF_CSR_BASE + 0x410) /* 内部状态0。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG1_REG (CSR_UP_ITF_CSR_BASE + 0x414) /* 内部状态1。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG2_REG (CSR_UP_ITF_CSR_BASE + 0x418) /* 内部状态2。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_0_REG (CSR_UP_ITF_CSR_BASE + 0x420) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_1_REG (CSR_UP_ITF_CSR_BASE + 0x424) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_2_REG (CSR_UP_ITF_CSR_BASE + 0x428) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_3_REG (CSR_UP_ITF_CSR_BASE + 0x42C) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG0_REG (CSR_UP_ITF_CSR_BASE + 0x430) /* Memory错误注入寄存器 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG1_REG (CSR_UP_ITF_CSR_BASE + 0x434) /* MEM错误状态寄存器1 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG2_REG (CSR_UP_ITF_CSR_BASE + 0x438) /* MEM错误状态寄存器2 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG3_REG (CSR_UP_ITF_CSR_BASE + 0x43C) /* MEM错误状态寄存器3 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST0_REG (CSR_UP_ITF_CSR_BASE + 0x440) /* DFX状态寄存器0 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST1_REG (CSR_UP_ITF_CSR_BASE + 0x444) /* DFX状态寄存器1 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST2_REG (CSR_UP_ITF_CSR_BASE + 0x448) /* DFX状态寄存器2 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST3_REG (CSR_UP_ITF_CSR_BASE + 0x44C) /* DFX状态寄存器3 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG4_REG (CSR_UP_ITF_CSR_BASE + 0x450) /* MEM错误状态寄存器4 */ +#define CSR_UP_ITF_CSR_UP_DBG_CNT0_REG (CSR_UP_ITF_CSR_BASE + 0x460) /* DFX统计寄存器0 */ +#define CSR_UP_ITF_CSR_UP_DBG_CNT1_REG (CSR_UP_ITF_CSR_BASE + 0x464) +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x470) /* uP MB Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_BA_REG (CSR_UP_ITF_CSR_BASE + 0x474) /* uP MB Rx ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_CI_REG (CSR_UP_ITF_CSR_BASE + 0x478) /* uP MB Rx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_PI_REG (CSR_UP_ITF_CSR_BASE + 0x47C) /* uP MB Rx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_BAR_MAP_REG (CSR_UP_ITF_CSR_BASE + 0x480) /* CPI BAR空间映射 */ +#define CSR_UP_ITF_CSR_UP_ACC_FUNC_IDX_REG (CSR_UP_ITF_CSR_BASE + 0x484) +#define CSR_UP_ITF_CSR_UP_INT_STATUS2_REG (CSR_UP_ITF_CSR_BASE + 0x490) /* 中断状态寄存器；写1清除对应比特中断。 */ +#define CSR_UP_ITF_CSR_UP_INT_CTL2_REG (CSR_UP_ITF_CSR_BASE + 0x494) /* uP interrupt control */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_TH_REG (CSR_UP_ITF_CSR_BASE + 0x4A0) /* 并发度门限 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_CNT_REG (CSR_UP_ITF_CSR_BASE + 0x4A4) /* 并发数统计 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_REC_REG (CSR_UP_ITF_CSR_BASE + 0x4A8) /* 并发数恢复 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD0_REG (CSR_UP_ITF_CSR_BASE + 0x4B0) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD1_REG (CSR_UP_ITF_CSR_BASE + 0x4B4) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD2_REG (CSR_UP_ITF_CSR_BASE + 0x4B8) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD3_REG (CSR_UP_ITF_CSR_BASE + 0x4BC) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_UNCRT_ERR_DIS_REG (CSR_UP_ITF_CSR_BASE + 0x4C0) + +/* func_com_csr Base address of Module's Register */ +#define CSR_FUNC_COM_CSR_BASE (0x4000000) + +/* **************************************************************************** */ +/* func_com_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE0_0_REG (CSR_FUNC_COM_CSR_BASE + 0x0) /* Function attribute0 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE0_1_REG (CSR_FUNC_COM_CSR_BASE + 0x80) /* Function attribute0 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE1_0_REG (CSR_FUNC_COM_CSR_BASE + 0x4) /* Function attribute1 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE1_1_REG (CSR_FUNC_COM_CSR_BASE + 0x84) /* Function attribute1 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE2_0_REG (CSR_FUNC_COM_CSR_BASE + 0x8) /* function attribute2 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE2_1_REG (CSR_FUNC_COM_CSR_BASE + 0x88) /* function attribute2 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE3_0_REG (CSR_FUNC_COM_CSR_BASE + 0xC) /* Function attribute3 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE3_1_REG (CSR_FUNC_COM_CSR_BASE + 0x8C) /* Function attribute3 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE4_0_REG (CSR_FUNC_COM_CSR_BASE + 0x10) /* Function attribute4 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE4_1_REG (CSR_FUNC_COM_CSR_BASE + 0x90) /* Function attribute4 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE5_0_REG (CSR_FUNC_COM_CSR_BASE + 0x14) /* Function attribute5 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE5_1_REG (CSR_FUNC_COM_CSR_BASE + 0x94) /* Function attribute5 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE6_0_REG (CSR_FUNC_COM_CSR_BASE + 0x18) /* Function attribute6 */ + +#define CSR_FUNC_COM_CSR_FUNCTION_TSK0_0_REG (CSR_FUNC_COM_CSR_BASE + 0x20) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_0_REG (CSR_FUNC_COM_CSR_BASE + 0x24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_1_REG (CSR_FUNC_COM_CSR_BASE + 0xA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_2_REG (CSR_FUNC_COM_CSR_BASE + 0x124) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_4_REG (CSR_FUNC_COM_CSR_BASE + 0x224) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_6_REG (CSR_FUNC_COM_CSR_BASE + 0x324) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_8_REG (CSR_FUNC_COM_CSR_BASE + 0x424) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_10_REG (CSR_FUNC_COM_CSR_BASE + 0x524) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_12_REG (CSR_FUNC_COM_CSR_BASE + 0x624) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_14_REG (CSR_FUNC_COM_CSR_BASE + 0x724) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_16_REG (CSR_FUNC_COM_CSR_BASE + 0x824) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_18_REG (CSR_FUNC_COM_CSR_BASE + 0x924) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_0_REG (CSR_FUNC_COM_CSR_BASE + 0x28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_1_REG (CSR_FUNC_COM_CSR_BASE + 0xA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_2_REG (CSR_FUNC_COM_CSR_BASE + 0x128) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_4_REG (CSR_FUNC_COM_CSR_BASE + 0x228) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_6_REG (CSR_FUNC_COM_CSR_BASE + 0x328) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_8_REG (CSR_FUNC_COM_CSR_BASE + 0x428) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_10_REG (CSR_FUNC_COM_CSR_BASE + 0x528) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_12_REG (CSR_FUNC_COM_CSR_BASE + 0x628) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_14_REG (CSR_FUNC_COM_CSR_BASE + 0x728) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_16_REG (CSR_FUNC_COM_CSR_BASE + 0x828) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_18_REG (CSR_FUNC_COM_CSR_BASE + 0x928) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_0_REG (CSR_FUNC_COM_CSR_BASE + 0x2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_1_REG (CSR_FUNC_COM_CSR_BASE + 0xAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_2_REG (CSR_FUNC_COM_CSR_BASE + 0x12C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_4_REG (CSR_FUNC_COM_CSR_BASE + 0x22C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_6_REG (CSR_FUNC_COM_CSR_BASE + 0x32C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_8_REG (CSR_FUNC_COM_CSR_BASE + 0x42C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_10_REG (CSR_FUNC_COM_CSR_BASE + 0x52C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_12_REG (CSR_FUNC_COM_CSR_BASE + 0x62C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_14_REG (CSR_FUNC_COM_CSR_BASE + 0x72C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_16_REG (CSR_FUNC_COM_CSR_BASE + 0x82C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_18_REG (CSR_FUNC_COM_CSR_BASE + 0x92C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFAC) +#define CSR_FUNC_COM_CSR_FUNC_REMAP_TABLE_ENTR_0_REG (CSR_FUNC_COM_CSR_BASE + 0x30) /* function remap table entry */ +#define CSR_FUNC_COM_CSR_FUNC_REMAP_TABLE_ENTR_1_REG (CSR_FUNC_COM_CSR_BASE + 0xB0) /* function remap table entry */ +#define CSR_FUNC_COM_CSR_FUNC_AEQ_CI_INDIR_WR_REG \ + (CSR_FUNC_COM_CSR_BASE + 0x50) /* AEQ CI simple indirect access path */ +#define CSR_FUNC_COM_CSR_FUNC_CEQ_CI_INDIR_WR_REG \ + (CSR_FUNC_COM_CSR_BASE + 0x54) /* CEQ CI simple indirect access path */ +#define CSR_FUNC_COM_CSR_FUNC_MSI_CLR_INDIR_WR_REG \ + (CSR_FUNC_COM_CSR_BASE + 0x58) /* MSI_CTL CLR simple indirect access path */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT0_REG (CSR_FUNC_COM_CSR_BASE + 0x60) /* ppf election results in port0 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT1_REG (CSR_FUNC_COM_CSR_BASE + 0x64) /* ppf election results in port1 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT2_REG (CSR_FUNC_COM_CSR_BASE + 0x68) /* ppf election results in port2 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT3_REG (CSR_FUNC_COM_CSR_BASE + 0x6C) /* ppf election results in port3 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT4_REG (CSR_FUNC_COM_CSR_BASE + 0x70) /* ppf election results in port4 */ + +/* func_mb_dat_csr Base address of Module's Register */ +#define CSR_FUNC_MB_DAT_CSR_BASE (0x4080000) + +/* **************************************************************************** */ +/* func_mb_dat_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_0_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x0) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_0_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x80) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_1_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x4) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_1_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x84) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_2_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x8) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_2_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x88) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_3_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xC) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_3_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x8C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_4_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x10) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_4_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x90) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_5_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x14) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_5_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x94) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_6_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x18) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_6_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x98) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_7_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x1C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_7_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x9C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_8_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x20) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_8_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA0) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_9_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x24) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_9_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA4) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_10_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x28) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_10_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA8) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_11_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x2C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_11_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xAC) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_12_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x30) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_12_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB0) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_13_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x34) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_13_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB4) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_14_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x38) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_14_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB8) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_15_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x3C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_15_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xBC) /* mailbox data */ + +/* func_mb_csr Base address of Module's Register */ +#define CSR_FUNC_MB_CSR_BASE (0x4100000) + +/* **************************************************************************** */ +/* func_mb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_MB_CSR_MAILBOX_CONTROL_0_REG (CSR_FUNC_MB_CSR_BASE + 0x0) /* Maibox control */ +#define CSR_FUNC_MB_CSR_MAILBOX_CONTROL_1_REG (CSR_FUNC_MB_CSR_BASE + 0x80) /* Maibox control */ +#define CSR_FUNC_MB_CSR_MAILBOX_INT_OFFSET_0_REG (CSR_FUNC_MB_CSR_BASE + 0x4) /* Mailbox interrupt offset */ +#define CSR_FUNC_MB_CSR_MAILBOX_INT_OFFSET_1_REG (CSR_FUNC_MB_CSR_BASE + 0x84) /* Mailbox interrupt offset */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_H_0_REG \ + (CSR_FUNC_MB_CSR_BASE + 0x8) /* Maibox data sending result back address high 32 bits */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_H_1_REG \ + (CSR_FUNC_MB_CSR_BASE + 0x88) /* Maibox data sending result back address high 32 bits */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_L_0_REG \ + (CSR_FUNC_MB_CSR_BASE + 0xC) /* Maibox data sending result back address low 32 bits */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_L_1_REG \ + (CSR_FUNC_MB_CSR_BASE + 0x8C) /* Maibox data sending result back address low 32 bits */ + +/* func_aeq_csr Base address of Module's Register */ +#define CSR_FUNC_AEQ_CSR_BASE (0x4181000) + +/* **************************************************************************** */ +/* func_aeq_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_0_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x0) /* Each PF use offset = 0x200 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2200. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_0_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x80) /* Each PF use offset = 0x200 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2200. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_1_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x4) /* Each PF use offset = 0x204 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2204. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_1_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x84) /* Each PF use offset = 0x204 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2204. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CI_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x8) /* Each PF use offset = 0x208 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2208. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CI_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x88) /* Each PF use offset = 0x208 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2208. */ +#define CSR_FUNC_AEQ_CSR_AEQ_PI_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC) /* Each PF use offset = 0x20C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x220C. */ +#define CSR_FUNC_AEQ_CSR_AEQ_PI_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x8C) /* Each PF use offset = 0x20C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x220C. */ +#define CSR_FUNC_AEQ_CSR_AEQ_INDIR_IDX_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x210 to access this csr. VF offset = 0x2210.MPU cann't access this CSR. */ +#define CSR_FUNC_AEQ_CSR_AEQ_INDIR_IDX_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + \ + 0x90) /* Each PF use offset = 0x210 to access this csr. VF offset = 0x2210.MPU cann't access this CSR. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x40) /* Each PF use offset = 0x240 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2240. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC0) /* Each PF use offset = 0x240 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2240. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x44) /* Each PF use offset = 0x244 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2244. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC4) /* Each PF use offset = 0x244 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2244. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x48) /* Each PF use offset = 0x248 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2248. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC8) /* Each PF use offset = 0x248 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2248. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x4C) /* Each PF use offset = 0x24C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x224C. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xCC) /* Each PF use offset = 0x24C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x224C. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x50) /* Each PF use offset = 0x250 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2250. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xD0) /* Each PF use offset = 0x250 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2250. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x54) /* Each PF use offset = 0x254 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2254. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xD4) /* Each PF use offset = 0x254 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2254. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x58) /* Each PF use offset = 0x258 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2258. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xD8) /* Each PF use offset = 0x258 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2258. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x5C) /* Each PF use offset = 0x25C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x225C. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xDC) /* Each PF use offset = 0x25C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x225C. */ + +/* func_ceq_csr Base address of Module's Register */ +#define CSR_FUNC_CEQ_CSR_BASE (0x4281000) + +/* **************************************************************************** */ +/* func_ceq_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_0_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x0) /* Each PF use offset = 0x280 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2280. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_0_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x80) /* Each PF use offset = 0x280 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2280. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_1_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x4) /* Each PF use offset = 0x284 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2284. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_1_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x84) /* Each PF use offset = 0x284 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2284. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CI_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x8) /* Each PF use offset = 0x288 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2288. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CI_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x88) /* Each PF use offset = 0x288 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2288. */ +#define CSR_FUNC_CEQ_CSR_CEQ_PI_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC) /* Each PF use offset = 0x28C to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x228C. */ +#define CSR_FUNC_CEQ_CSR_CEQ_PI_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x8C) /* Each PF use offset = 0x28C to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x228C. */ +#define CSR_FUNC_CEQ_CSR_CEQ_INDIR_IDX_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x290 to access this csr. VF offset = 0x2290.MPU can't access this CSR. */ +#define CSR_FUNC_CEQ_CSR_CEQ_INDIR_IDX_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + \ + 0x90) /* Each PF use offset = 0x290 to access this csr. VF offset = 0x2290.MPU can't access this CSR. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x40) /* Each PF use offset = 0x2C0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC0) /* Each PF use offset = 0x2C0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x44) /* Each PF use offset = 0x2C4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC4) /* Each PF use offset = 0x2C4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x48) /* Each PF use offset = 0x2C8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC8) /* Each PF use offset = 0x2C8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x4C) /* Each PF use offset = 0x2CC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22CC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xCC) /* Each PF use offset = 0x2CC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22CC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x50) /* Each PF use offset = 0x2D0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xD0) /* Each PF use offset = 0x2D0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x54) /* Each PF use offset = 0x2D4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xD4) /* Each PF use offset = 0x2D4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x58) /* Each PF use offset = 0x2D8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xD8) /* Each PF use offset = 0x2D8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x5C) /* Each PF use offset = 0x2DC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22DC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xDC) /* Each PF use offset = 0x2DC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22DC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x60) /* Each PF use offset = 0x2E0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xE0) /* Each PF use offset = 0x2E0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x64) /* Each PF use offset = 0x2E4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xE4) /* Each PF use offset = 0x2E4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x68) /* Each PF use offset = 0x2E8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xE8) /* Each PF use offset = 0x2E8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x6C) /* Each PF use offset = 0x2EC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22EC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xEC) /* Each PF use offset = 0x2EC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22EC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x70) /* Each PF use offset = 0x2F0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xF0) /* Each PF use offset = 0x2F0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x74) /* Each PF use offset = 0x2F4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xF4) /* Each PF use offset = 0x2F4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x78) /* Each PF use offset = 0x2F8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xF8) /* Each PF use offset = 0x2F8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x7C) /* Each PF use offset = 0x2FC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22FC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xFC) /* Each PF use offset = 0x2FC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22FC. */ + +/* func_int_csr Base address of Module's Register */ +#define CSR_FUNC_INT_CSR_BASE (0x4301000) + +/* **************************************************************************** */ +/* func_int_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_0_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x0) /* Each PF use offset = 0x300 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2300. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_0_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x20) /* Each PF use offset = 0x300 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2300. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_1_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x4) /* Each PF use offset = 0x304 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2304. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_1_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x24) /* Each PF use offset = 0x304 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2304. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_2_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x8) /* Each PF use offset = 0x308 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2308. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_2_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x28) /* Each PF use offset = 0x308 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2308. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_3_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0xC) /* Each PF use offset = 0x30C to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x230C. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_3_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x2C) /* Each PF use offset = 0x30C to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x230C. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_INDIR_IDX_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x310 to access this csr. VF offset = 0x2310.MPU can't access this CSR. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_4_0_REG (CSR_FUNC_INT_CSR_BASE + 0x14) /* It is only access by MPU. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_4_1_REG (CSR_FUNC_INT_CSR_BASE + 0x34) /* It is only access by MPU. */ +#define CSR_FUNC_INT_CSR_FUNCTION_DMA_ATTR_ENTR_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x80000) /* Each PF use offset = 0x380 to access this csr after correct configuration of \ + DMA_ATTR_INDIR_IDX.VF offset = 0x2380. */ +#define CSR_FUNC_INT_CSR_FUNCTION_DMA_ATTR_ENTR_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x80004) /* Each PF use offset = 0x380 to access this csr after correct configuration of \ + DMA_ATTR_INDIR_IDX.VF offset = 0x2380. */ +#define CSR_FUNC_INT_CSR_DMA_ATTR_INDIR_IDX_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x390 to access this csr. VF offset = 0x2390.MPU can't access this CSR. */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0000) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0080) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0100) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0180) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0200) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0280) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0300) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0380) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0400) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0480) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0500) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0580) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0600) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0680) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0700) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0780) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0800) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0880) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0900) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0980) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0004) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0084) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0104) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0184) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0204) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0284) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0304) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0384) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0404) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0484) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0504) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0584) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0604) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0684) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0704) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0784) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0804) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0884) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0904) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0984) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0008) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0088) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0108) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0188) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0208) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0288) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0308) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0388) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0408) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0488) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0508) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0588) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0608) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0688) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0708) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0788) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0808) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0888) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0908) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0988) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA000C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA008C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA010C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA018C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA020C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA028C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA030C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA038C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA040C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA048C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA050C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA058C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA060C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA068C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA070C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA078C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA080C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA088C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA090C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA098C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0010) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0090) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0110) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0190) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0210) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0290) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0310) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0390) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0410) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0490) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0510) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0590) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0610) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0690) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0710) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0790) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0810) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0890) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0910) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0990) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0014) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0094) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0114) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0194) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0214) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0294) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0314) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0394) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0414) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0494) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0514) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0594) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0614) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0694) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0714) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0794) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0814) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0894) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0914) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0994) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0018) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0098) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0118) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0198) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0218) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0298) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0318) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0398) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0418) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0498) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0518) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0598) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0618) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0698) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0718) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0798) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0818) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0898) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0918) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0998) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA001C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA009C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA011C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA019C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA021C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA029C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA031C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA039C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA041C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA049C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA051C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA059C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA061C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA069C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA071C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA079C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA081C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA089C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA091C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA099C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ + +/* host_csr Base address of Module's Register */ +#define CSR_HOST_CSR_BASE (0x43AC000) + +/* **************************************************************************** */ +/* host_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HOST_CSR_PPF_ELECTION_0_REG \ + (CSR_HOST_CSR_BASE + \ + 0x0) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_1_REG \ + (CSR_HOST_CSR_BASE + \ + 0x4) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_2_REG \ + (CSR_HOST_CSR_BASE + \ + 0x8) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_3_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_4_REG \ + (CSR_HOST_CSR_BASE + \ + 0x10) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_MPF_ELECTION_REG \ + (CSR_HOST_CSR_BASE + \ + 0x20) /* MPF election.(each PF will use offset=0x020 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_0_REG \ + (CSR_HOST_CSR_BASE + 0x40) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_1_REG \ + (CSR_HOST_CSR_BASE + 0x60) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_2_REG \ + (CSR_HOST_CSR_BASE + 0x80) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_3_REG \ + (CSR_HOST_CSR_BASE + 0xA0) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_0_REG \ + (CSR_HOST_CSR_BASE + 0x44) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_1_REG \ + (CSR_HOST_CSR_BASE + 0x64) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_2_REG \ + (CSR_HOST_CSR_BASE + 0x84) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_3_REG \ + (CSR_HOST_CSR_BASE + 0xA4) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_0_REG \ + (CSR_HOST_CSR_BASE + 0x48) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_1_REG \ + (CSR_HOST_CSR_BASE + 0x68) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_2_REG \ + (CSR_HOST_CSR_BASE + 0x88) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_3_REG \ + (CSR_HOST_CSR_BASE + 0xA8) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_0_REG \ + (CSR_HOST_CSR_BASE + 0x4C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_1_REG \ + (CSR_HOST_CSR_BASE + 0x6C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_2_REG \ + (CSR_HOST_CSR_BASE + 0x8C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_3_REG \ + (CSR_HOST_CSR_BASE + 0xAC) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_0_REG \ + (CSR_HOST_CSR_BASE + 0x50) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_1_REG \ + (CSR_HOST_CSR_BASE + 0x70) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_2_REG \ + (CSR_HOST_CSR_BASE + 0x90) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_3_REG \ + (CSR_HOST_CSR_BASE + 0xB0) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_0_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_1_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC8) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_2_REG \ + (CSR_HOST_CSR_BASE + \ + 0xD0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_3_REG \ + (CSR_HOST_CSR_BASE + \ + 0xD8) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_4_REG \ + (CSR_HOST_CSR_BASE + \ + 0xE0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_0_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_1_REG \ + (CSR_HOST_CSR_BASE + \ + 0xCC) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_2_REG \ + (CSR_HOST_CSR_BASE + \ + 0xD4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_3_REG \ + (CSR_HOST_CSR_BASE + \ + 0xDC) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_4_REG \ + (CSR_HOST_CSR_BASE + \ + 0xE4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x100) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x104) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x108) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x10C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x110) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x114) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x118) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x11C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x120) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x124) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x128) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x12C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x130) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x134) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x138) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x13C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x140) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x144) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x148) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x14C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x150) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x154) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x158) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x15C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x160) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x164) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x168) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x16C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x170) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x174) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x178) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x17C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x180) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x184) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x188) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x18C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x190) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x194) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x198) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x19C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x1A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x1A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x1A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x1AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x1B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x1B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x1B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x1BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x1C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x1C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x1C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x1CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x1D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x1D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x1D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x1DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x1E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x1E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x1E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x1EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x1F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x1F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x1F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x1FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x200) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x204) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x208) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x20C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x210) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x214) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x218) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x21C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x220) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x224) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x228) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x22C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x230) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x234) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x238) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x23C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x240) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x244) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x248) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x24C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x250) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x254) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x258) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x25C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x260) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x264) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x268) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x26C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x270) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x274) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x278) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x27C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x280) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x284) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x288) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x28C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x290) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x294) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x298) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x29C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x2A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x2A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x2A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x2AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x2B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x2B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x2B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x2BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x2C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x2C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x2C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x2CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x2D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x2D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x2D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x2DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x2E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x2E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x2E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x2EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x2F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x2F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x2F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x2FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x300) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x304) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x308) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x30C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x310) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x314) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x318) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x31C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x320) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x324) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x328) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x32C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x330) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x334) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x338) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x33C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x340) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x344) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x348) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x34C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x350) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x354) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x358) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x35C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x360) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x364) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x368) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x36C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x370) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x374) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x378) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x37C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x380) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x384) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x388) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x38C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x390) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x394) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x398) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x39C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x3A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x3A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x3A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x3AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x3B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x3B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x3B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x3BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x3C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x3C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x3C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x3CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x3D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x3D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x3D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x3DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x3E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x3E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x3E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x3EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x3F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x3F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x3F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x3FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x400) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x404) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x408) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x40C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x410) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x414) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x418) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x41C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x420) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x424) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x428) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x42C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x430) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x434) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x438) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x43C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x440) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x444) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x448) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x44C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x450) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x454) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x458) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x45C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x460) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x464) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x468) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x46C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x470) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x474) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x478) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x47C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x480) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x484) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x488) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x48C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x490) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x494) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x498) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x49C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x4A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x4A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x4A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x4AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x4B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x4B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x4B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x4BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x4C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x4C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x4C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x4CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x4D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x4D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x4D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x4DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x4E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x4E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x4E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x4EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x4F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x4F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x4F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x4FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x500) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x504) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x508) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x50C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x510) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x514) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x518) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x51C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x520) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x524) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x528) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x52C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x530) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x534) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x538) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x53C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x540) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x544) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x548) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x54C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x550) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x554) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x558) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x55C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x560) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x564) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x568) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x56C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x570) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x574) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x578) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x57C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x580) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x584) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x588) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x58C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x590) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x594) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x598) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x59C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x5A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x5A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x5A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x5AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x5B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x5B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x5B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x5BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x5C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x5C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x5C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x5CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x5D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x5D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x5D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x5DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x5E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x5E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x5E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x5EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x5F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x5F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x5F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x5FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ + +/* glb_csr Base address of Module's Register */ +#define CSR_GLB_CSR_BASE (0x43AD000) + +/* **************************************************************************** */ +/* glb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_GLB_CSR_GLB_CPI_VERSION_CSR_REG (CSR_GLB_CSR_BASE + 0x0) +#define CSR_GLB_CSR_GLB_X86_REQ_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x4) +#define CSR_GLB_CSR_GLB_X86_CPL_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x8) +#define CSR_GLB_CSR_GLB_SPU_X86_ACC_WEIGHT_REG (CSR_GLB_CSR_BASE + 0xC) +#define CSR_GLB_CSR_GLB_PORT_MODE_REG (CSR_GLB_CSR_BASE + 0x10) +#define CSR_GLB_CSR_GLB_SPU_REQ_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x14) +#define CSR_GLB_CSR_GLB_SPU_CPL_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x18) +#define CSR_GLB_CSR_GLB_RES_PER_FUNC_REG (CSR_GLB_CSR_BASE + 0x50) /* The global resources for each function */ +#define CSR_GLB_CSR_API_GAP_CTL_REG (CSR_GLB_CSR_BASE + 0x54) /* API sending gap configuration */ +#define CSR_GLB_CSR_DIR_WQE_GAP_CTL_REG (CSR_GLB_CSR_BASE + 0x58) /* Direct WQE sending gap configuration */ +#define CSR_GLB_CSR_DIR_WQE_TIMEOUT_REG (CSR_GLB_CSR_BASE + 0x5C) /* Direct WQE timeout configuration */ +#define CSR_GLB_CSR_GLB_SW_SRCH_TCAM_CTL_REG (CSR_GLB_CSR_BASE + 0x80) +#define CSR_GLB_CSR_GLB_SW_SRCH_TCAM_RSLT_REG (CSR_GLB_CSR_BASE + 0x84) +#define CSR_GLB_CSR_GLB_APB_TIMER_CFG_REG (CSR_GLB_CSR_BASE + 0x88) /* The threshold for wait timer in the I_CTL */ +#define CSR_GLB_CSR_GLB_SRV_TYPE_FOR_DDB_REG \ + (CSR_GLB_CSR_BASE + 0x8C) /* The Srv_Type in the doorbell API generated by direct WQE */ +#define CSR_GLB_CSR_GLB_NL2N_INLINE_OTD_REG (CSR_GLB_CSR_BASE + 0x90) /* Outstanding of NL2N sub-command */ +#define CSR_GLB_CSR_GLB_NL2N_INLINE_NUM_TH_REG \ + (CSR_GLB_CSR_BASE + 0x94) /* Upper threshold of local NL2N sub-command. */ +#define CSR_GLB_CSR_GLB_TILEP_POLL_GAP_REG (CSR_GLB_CSR_BASE + 0x98) /* Poll gap of tile proxy */ +#define CSR_GLB_CSR_GLB_MB_TX_LEGAL_CHK_REG \ + (CSR_GLB_CSR_BASE + 0xA0) /* check the mailbox sendor and receiver whether legal */ +#define CSR_GLB_CSR_GLB_CPL_CTRL_REG (CSR_GLB_CSR_BASE + 0xA8) /* CPL Control */ +#define CSR_GLB_CSR_UCPU_MB_TX_CTL_REG (CSR_GLB_CSR_BASE + 0xB0) /* the UCPU MB send control */ +#define CSR_GLB_CSR_UCPU_ALLOW_VF_CFG_REG (CSR_GLB_CSR_BASE + 0xBC) /* the UCPU alow VF have configure right */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_0_REG (CSR_GLB_CSR_BASE + 0xC0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_1_REG (CSR_GLB_CSR_BASE + 0xC4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_2_REG (CSR_GLB_CSR_BASE + 0xC8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_3_REG (CSR_GLB_CSR_BASE + 0xCC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_4_REG (CSR_GLB_CSR_BASE + 0xD0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_5_REG (CSR_GLB_CSR_BASE + 0xD4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_6_REG (CSR_GLB_CSR_BASE + 0xD8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_7_REG (CSR_GLB_CSR_BASE + 0xDC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_8_REG (CSR_GLB_CSR_BASE + 0xE0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_9_REG (CSR_GLB_CSR_BASE + 0xE4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_10_REG (CSR_GLB_CSR_BASE + 0xE8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_11_REG (CSR_GLB_CSR_BASE + 0xEC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_12_REG (CSR_GLB_CSR_BASE + 0xF0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_13_REG (CSR_GLB_CSR_BASE + 0xF4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_14_REG (CSR_GLB_CSR_BASE + 0xF8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_15_REG (CSR_GLB_CSR_BASE + 0xFC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_PF_EPROM_OFFSET_BASE_REG (CSR_GLB_CSR_BASE + 0x100) /* The Expansion ROM offset configuration */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_CTRL0_REG \ + (CSR_GLB_CSR_BASE + 0x200) /* CPI internal table indirect access ctrl registers */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_CTRL1_REG \ + (CSR_GLB_CSR_BASE + 0x204) /* CPI internal table indirect access ctrl registers */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_0_REG (CSR_GLB_CSR_BASE + 0x210) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_1_REG (CSR_GLB_CSR_BASE + 0x214) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_2_REG (CSR_GLB_CSR_BASE + 0x218) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_3_REG (CSR_GLB_CSR_BASE + 0x21C) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_4_REG (CSR_GLB_CSR_BASE + 0x220) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_5_REG (CSR_GLB_CSR_BASE + 0x224) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_6_REG (CSR_GLB_CSR_BASE + 0x228) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_7_REG (CSR_GLB_CSR_BASE + 0x22C) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_CTRL_REG (CSR_GLB_CSR_BASE + 0x230) /* pcie indir to ring path control */ +#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_DAT0_REG (CSR_GLB_CSR_BASE + 0x234) /* pcie indir to ring path data0 */ +#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_DAT1_REG (CSR_GLB_CSR_BASE + 0x238) /* pcie indir to ring path data0 */ +#define CSR_GLB_CSR_CPI_RAM_INIT_REQ_REG (CSR_GLB_CSR_BASE + 0x240) /* CPI internal RAM initial request */ +#define CSR_GLB_CSR_CPI_RAM_INIT_STS0_REG (CSR_GLB_CSR_BASE + 0x250) /* CPI internal RAM initial status 0 */ +#define CSR_GLB_CSR_CPI_RAM_INIT_STS1_REG (CSR_GLB_CSR_BASE + 0x254) /* CPI internal RAM initial status 1 */ +#define CSR_GLB_CSR_CPI_MB_TX_GAP_REG (CSR_GLB_CSR_BASE + 0x260) /* CPI control the mailobx sending gap */ +#define CSR_GLB_CSR_GLB_CPI_RAM_ECC_BYPASS_REG (CSR_GLB_CSR_BASE + 0x280) /* CPI internal RAM test mode */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST0_REG (CSR_GLB_CSR_BASE + 0x290) /* mailbox shaper control csr for host0 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST1_REG (CSR_GLB_CSR_BASE + 0x294) /* mailbox shaper control csr for host1 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST2_REG (CSR_GLB_CSR_BASE + 0x298) /* mailbox shaper control csr for host2 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST3_REG (CSR_GLB_CSR_BASE + 0x29C) /* mailbox shaper control csr for host3 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST4_REG (CSR_GLB_CSR_BASE + 0x2A0) /* mailbox shaper control csr for host4 */ +#define CSR_GLB_CSR_GLB_MB_SHP_UNIT_REG (CSR_GLB_CSR_BASE + 0x2A4) /* mailbox shaper time unit */ +#define CSR_GLB_CSR_GLB_MB_RIGHT_CFG_REG (CSR_GLB_CSR_BASE + 0x2A8) +#define CSR_GLB_CSR_GLB_CSR_ACC_TIMEOUT_REG (CSR_GLB_CSR_BASE + 0x2B0) +#define CSR_GLB_CSR_GLB_CPI_RS_ND_PE_CRDIT_REG (CSR_GLB_CSR_BASE + 0x2B8) +#define CSR_GLB_CSR_GLB_NP_CTX_CFG_REG (CSR_GLB_CSR_BASE + 0x2F0) +#define CSR_GLB_CSR_GLB_IPUSH_FIFO_BP_REG (CSR_GLB_CSR_BASE + 0x318) +#define CSR_GLB_CSR_GLB_IPUSH_FIFO_STS_REG (CSR_GLB_CSR_BASE + 0x31C) +#define CSR_GLB_CSR_GLB_CPATH_INT_BITMAP_REG (CSR_GLB_CSR_BASE + 0x340) /* non-cpi INT的中断屏蔽寄存器 */ +#define CSR_GLB_CSR_GLB_DWQE_BUF_VLD_NUM_REG (CSR_GLB_CSR_BASE + 0x344) /* Direct WQE Buffer的可用参数 */ +#define CSR_GLB_CSR_DIR_WQE_BYTE_ORDER_EN_REG (CSR_GLB_CSR_BASE + 0x354) /* Direct WQE字节序转换使能 */ +#define CSR_GLB_CSR_FAKE_VFID_CAL_CFG_REG (CSR_GLB_CSR_BASE + 0x360) /* fake VFID此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_FAKE_VFID_ENABLE_REG (CSR_GLB_CSR_BASE + 0x364) /* fake VFID此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_DBL_FAKE_VFID_CBIT_EN_REG (CSR_GLB_CSR_BASE + 0x368) +#define CSR_GLB_CSR_DBL_SRV_TYPE_ILLEGAL_REG (CSR_GLB_CSR_BASE + 0x36C) +#define CSR_GLB_CSR_GLB_DWQE_LB_HASH_ACC_REG (CSR_GLB_CSR_BASE + 0x370) /* load balance此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_GLB_DWQE_LB_MOD_REG (CSR_GLB_CSR_BASE + 0x374) /* load balance此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_GLB_DWQE_SMF_PG_REG (CSR_GLB_CSR_BASE + 0x378) /* load balance此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_VIRTIO_BYTE_ORDER_DIS_REG (CSR_GLB_CSR_BASE + 0x380) /* VIRTIO_ITF字节序转换disable */ +#define CSR_GLB_CSR_NVME_RSV_ADDR_RANGE_REG (CSR_GLB_CSR_BASE + 0x384) +#define CSR_GLB_CSR_VIRTIO_LB_MOD_REG (CSR_GLB_CSR_BASE + 0x388) +#define CSR_GLB_CSR_VIRTIO_OTD_MAX_TH_REG (CSR_GLB_CSR_BASE + 0x38C) +#define CSR_GLB_CSR_GLB_FLXQ_MAP_EN_REG (CSR_GLB_CSR_BASE + 0x390) +#define CSR_GLB_CSR_GLB_AEQ_IDX_FOR_VF_REG (CSR_GLB_CSR_BASE + 0x3A0) /* 第一个VF所对应物理资源AEQ的起始编号。 */ +#define CSR_GLB_CSR_PTP_TS_UPDT_CFG_REG (CSR_GLB_CSR_BASE + 0x3AC) /* Timestamp timer update */ +#define CSR_GLB_CSR_PTP_TS_INC_CFG_REG (CSR_GLB_CSR_BASE + 0x3B0) /* Timestamp timer configuration */ +#define CSR_GLB_CSR_PTP_TS_CALIBRATION_REG (CSR_GLB_CSR_BASE + 0x3B4) /* Timestamp timer calibration */ +#define CSR_GLB_CSR_PTP_TS_WR_DATA0_REG (CSR_GLB_CSR_BASE + 0x3B8) /* Timestamp timer write data 0 */ +#define CSR_GLB_CSR_PTP_TS_WR_DATA1_REG (CSR_GLB_CSR_BASE + 0x3BC) /* Timestamp timer write data 1 */ +#define CSR_GLB_CSR_PTP_TS_WR_DATA2_REG (CSR_GLB_CSR_BASE + 0x3C0) /* Timestamp timer write data 2 */ +#define CSR_GLB_CSR_PTP_TS_RD_DATA0_REG (CSR_GLB_CSR_BASE + 0x3C4) /* Timestamp timer read data 0 */ +#define CSR_GLB_CSR_PTP_TS_RD_DATA1_REG (CSR_GLB_CSR_BASE + 0x3C8) /* Timestamp timer read data 1 */ +#define CSR_GLB_CSR_PTP_TS_RD_DATA2_REG (CSR_GLB_CSR_BASE + 0x3CC) /* Timestamp timer read data 2 */ +#define CSR_GLB_CSR_PTP_TS_UP_EN_REG \ + (CSR_GLB_CSR_BASE + \ + 0x3D0) /* Timestamp timer update enableAttention, bit[3:0] should be configured in onehot mode. */ +#define CSR_GLB_CSR_PTP_DSTR_CFG_REG (CSR_GLB_CSR_BASE + 0x3D4) /* Timestamp distribute configuration */ +#define CSR_GLB_CSR_NON_PTP_TS_INC_CFG_REG (CSR_GLB_CSR_BASE + 0x3D8) /* non-MAC Timestamp timer configuration */ +#define CSR_GLB_CSR_NON_PTP_TS_CALIBRATION_REG (CSR_GLB_CSR_BASE + 0x3DC) /* non-MAC Timestamp timer calibration */ +#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA0_REG (CSR_GLB_CSR_BASE + 0x3E0) /* non-MAC Timestamp timer write data 0 */ +#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA1_REG (CSR_GLB_CSR_BASE + 0x3E4) /* non-MAC Timestamp timer write data 1 */ +#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA2_REG (CSR_GLB_CSR_BASE + 0x3E8) /* non-MAC Timestamp timer write data 2 */ +#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA0_REG (CSR_GLB_CSR_BASE + 0x3EC) /* non-MAC Timestamp timer read data 0 */ +#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA1_REG (CSR_GLB_CSR_BASE + 0x3F0) /* non-MAC Timestamp timer read data 1 */ +#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA2_REG (CSR_GLB_CSR_BASE + 0x3F4) /* non-MAC Timestamp timer read data 2 */ +#define CSR_GLB_CSR_NON_PTP_TS_UP_EN_REG \ + (CSR_GLB_CSR_BASE + \ + 0x3F8) /* non-MAC Timestamp timer update enable.Attention, bit[2:0] should be configured in onehot mode. */ +#define CSR_GLB_CSR_NON_PTP_DSTR_CFG_REG (CSR_GLB_CSR_BASE + 0x3FC) /* non-MAC Timestamp distribute configuration */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_0_REG (CSR_GLB_CSR_BASE + 0x400) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_1_REG (CSR_GLB_CSR_BASE + 0x404) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_2_REG (CSR_GLB_CSR_BASE + 0x408) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_3_REG (CSR_GLB_CSR_BASE + 0x40C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_4_REG (CSR_GLB_CSR_BASE + 0x410) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_5_REG (CSR_GLB_CSR_BASE + 0x414) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_6_REG (CSR_GLB_CSR_BASE + 0x418) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_7_REG (CSR_GLB_CSR_BASE + 0x41C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_8_REG (CSR_GLB_CSR_BASE + 0x420) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_9_REG (CSR_GLB_CSR_BASE + 0x424) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_10_REG (CSR_GLB_CSR_BASE + 0x428) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_11_REG (CSR_GLB_CSR_BASE + 0x42C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_12_REG (CSR_GLB_CSR_BASE + 0x430) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_13_REG (CSR_GLB_CSR_BASE + 0x434) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_14_REG (CSR_GLB_CSR_BASE + 0x438) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_15_REG (CSR_GLB_CSR_BASE + 0x43C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_16_REG (CSR_GLB_CSR_BASE + 0x440) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_17_REG (CSR_GLB_CSR_BASE + 0x444) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_18_REG (CSR_GLB_CSR_BASE + 0x448) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_19_REG (CSR_GLB_CSR_BASE + 0x44C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_20_REG (CSR_GLB_CSR_BASE + 0x450) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_21_REG (CSR_GLB_CSR_BASE + 0x454) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_22_REG (CSR_GLB_CSR_BASE + 0x458) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_23_REG (CSR_GLB_CSR_BASE + 0x45C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_24_REG (CSR_GLB_CSR_BASE + 0x460) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_25_REG (CSR_GLB_CSR_BASE + 0x464) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_26_REG (CSR_GLB_CSR_BASE + 0x468) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_27_REG (CSR_GLB_CSR_BASE + 0x46C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_28_REG (CSR_GLB_CSR_BASE + 0x470) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_29_REG (CSR_GLB_CSR_BASE + 0x474) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_30_REG (CSR_GLB_CSR_BASE + 0x478) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_31_REG (CSR_GLB_CSR_BASE + 0x47C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_32_REG (CSR_GLB_CSR_BASE + 0x480) /* vf offset for the PF */ + +/* api_chn_csr Base address of Module's Register */ +#define CSR_API_CHN_CSR_BASE (0x43A4000) + +/* **************************************************************************** */ +/* api_chn_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_H_0_REG \ + (CSR_API_CHN_CSR_BASE + \ + 0x0) /* high 32 bits address of an API chain一个PF最多分配128份api chain资源。全局共有256份api chain资源。 */ +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_H_1_REG \ + (CSR_API_CHN_CSR_BASE + \ + 0x80) /* high 32 bits address of an API chain一个PF最多分配128份api chain资源。全局共有256份api chain资源。 */ +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_L_0_REG (CSR_API_CHN_CSR_BASE + 0x4) /* low 32 bits address of an API chain */ +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_L_1_REG (CSR_API_CHN_CSR_BASE + 0x84) /* low 32 bits address of an API chain */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_H_0_REG \ + (CSR_API_CHN_CSR_BASE + 0x8) /* High 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_H_1_REG \ + (CSR_API_CHN_CSR_BASE + 0x88) /* High 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_L_0_REG \ + (CSR_API_CHN_CSR_BASE + 0xC) /* Low 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_L_1_REG \ + (CSR_API_CHN_CSR_BASE + 0x8C) /* Low 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_CHAIN_LEN_0_REG (CSR_API_CHN_CSR_BASE + 0x10) /* The API chain length */ +#define CSR_API_CHN_CSR_API_CHAIN_LEN_1_REG (CSR_API_CHN_CSR_BASE + 0x90) /* The API chain length */ +#define CSR_API_CHN_CSR_API_CHAIN_CTL_0_REG (CSR_API_CHN_CSR_BASE + 0x14) /* API chain attribute */ +#define CSR_API_CHN_CSR_API_CHAIN_CTL_1_REG (CSR_API_CHN_CSR_BASE + 0x94) /* API chain attribute */ +#define CSR_API_CHN_CSR_API_CHAIN_DMA_ATTR_0_REG (CSR_API_CHN_CSR_BASE + 0x18) /* API TPH control filed */ +#define CSR_API_CHN_CSR_API_CHAIN_DMA_ATTR_1_REG (CSR_API_CHN_CSR_BASE + 0x98) /* API TPH control filed */ +#define CSR_API_CHN_CSR_API_CHAIN_PI_0_REG (CSR_API_CHN_CSR_BASE + 0x1C) /* The PI value of an API chain */ +#define CSR_API_CHN_CSR_API_CHAIN_PI_1_REG (CSR_API_CHN_CSR_BASE + 0x9C) /* The PI value of an API chain */ +#define CSR_API_CHN_CSR_API_CHAIN_REQ_0_REG (CSR_API_CHN_CSR_BASE + 0x20) /* API chain control */ +#define CSR_API_CHN_CSR_API_CHAIN_REQ_1_REG (CSR_API_CHN_CSR_BASE + 0xA0) /* API chain control */ +#define CSR_API_CHN_CSR_API_STATUS_0_0_REG (CSR_API_CHN_CSR_BASE + 0x30) /* API Chain Status */ +#define CSR_API_CHN_CSR_API_STATUS_0_1_REG (CSR_API_CHN_CSR_BASE + 0xB0) /* API Chain Status */ +#define CSR_API_CHN_CSR_API_STATUS_1_0_REG (CSR_API_CHN_CSR_BASE + 0x34) /* API Chain Current Address H */ +#define CSR_API_CHN_CSR_API_STATUS_1_1_REG (CSR_API_CHN_CSR_BASE + 0xB4) /* API Chain Current Address H */ +#define CSR_API_CHN_CSR_API_STATUS_2_0_REG (CSR_API_CHN_CSR_BASE + 0x38) /* API Chain Current Address L */ +#define CSR_API_CHN_CSR_API_STATUS_2_1_REG (CSR_API_CHN_CSR_BASE + 0xB8) /* API Chain Current Address L */ + +/* dfx_glb_csr Base address of Module's Register */ +#define CSR_DFX_GLB_CSR_BASE (0x43AF000) + +/* **************************************************************************** */ +/* dfx_glb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_0_REG (CSR_DFX_GLB_CSR_BASE + 0x0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_1_REG (CSR_DFX_GLB_CSR_BASE + 0x10) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_2_REG (CSR_DFX_GLB_CSR_BASE + 0x20) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_3_REG (CSR_DFX_GLB_CSR_BASE + 0x30) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_4_REG (CSR_DFX_GLB_CSR_BASE + 0x40) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_5_REG (CSR_DFX_GLB_CSR_BASE + 0x50) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_6_REG (CSR_DFX_GLB_CSR_BASE + 0x60) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_7_REG (CSR_DFX_GLB_CSR_BASE + 0x70) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_8_REG (CSR_DFX_GLB_CSR_BASE + 0x80) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_9_REG (CSR_DFX_GLB_CSR_BASE + 0x90) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0x4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x14) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x24) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x34) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x44) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x54) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x64) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x74) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x84) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x94) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0x8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x18) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x28) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x38) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x48) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x58) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x68) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x78) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x88) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x98) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0xC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x1C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x2C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x3C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x4C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x5C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x6C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x7C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x8C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x9C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xAC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xBC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xCC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xDC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xEC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xFC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_PORT0_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x100) +#define CSR_DFX_GLB_CSR_GLB_PORT1_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x104) +#define CSR_DFX_GLB_CSR_GLB_PORT2_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x108) +#define CSR_DFX_GLB_CSR_GLB_PORT3_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x10C) +#define CSR_DFX_GLB_CSR_GLB_PORT4_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x110) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_OK_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x114) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x118) +#define CSR_DFX_GLB_CSR_DFX_ICTL_SOP_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x11C) +#define CSR_DFX_GLB_CSR_DFX_ICTL_MPU_ACC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x120) +#define CSR_DFX_GLB_CSR_DFX_ICTL_IPUSH_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x124) +#define CSR_DFX_GLB_CSR_DFX_ICTL_VIO_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x128) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_IO_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x12C) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_TLP_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x130) +#define CSR_DFX_GLB_CSR_GLB_CPI_PORT_BP_EN_CFG_REG (CSR_DFX_GLB_CSR_BASE + 0x134) +#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK0_REG (CSR_DFX_GLB_CSR_BASE + 0x140) +#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK1_REG (CSR_DFX_GLB_CSR_BASE + 0x144) +#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK2_REG (CSR_DFX_GLB_CSR_BASE + 0x148) +#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK0_REG (CSR_DFX_GLB_CSR_BASE + 0x150) +#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK1_REG (CSR_DFX_GLB_CSR_BASE + 0x154) +#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK2_REG (CSR_DFX_GLB_CSR_BASE + 0x158) +#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS0_REG (CSR_DFX_GLB_CSR_BASE + 0x160) +#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS1_REG (CSR_DFX_GLB_CSR_BASE + 0x164) +#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS2_REG (CSR_DFX_GLB_CSR_BASE + 0x168) +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x400) /* CPI BP WATCH Status */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_WINDOW_REG (CSR_DFX_GLB_CSR_BASE + 0x404) /* CPI backpressure watch window */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_BITMAP_REG (CSR_DFX_GLB_CSR_BASE + 0x408) /* CPI backpressure watch bitmap */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_START_REG (CSR_DFX_GLB_CSR_BASE + 0x40C) /* CPI backpressure watch start */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x410) /* CPI backpressure watch counter */ +#define CSR_DFX_GLB_CSR_GLB_CSR_TIMEOUT_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x414) +#define CSR_DFX_GLB_CSR_DWQE_API_NO_ENOUGH_DATA_REG (CSR_DFX_GLB_CSR_BASE + 0x418) +#define CSR_DFX_GLB_CSR_DWQE_DBL_NO_ENOUGH_DATA_REG (CSR_DFX_GLB_CSR_BASE + 0x41C) +#define CSR_DFX_GLB_CSR_NORM_DBL_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x420) +#define CSR_DFX_GLB_CSR_NORM_DBL_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x424) +#define CSR_DFX_GLB_CSR_DWQE_DBL_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x428) +#define CSR_DFX_GLB_CSR_DWQE_API_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x42C) +#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x430) +#define CSR_DFX_GLB_CSR_DWQE_BUF_CNT_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x434) +#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_ON_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x438) +#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_OFF_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x43C) +#define CSR_DFX_GLB_CSR_DWQE_REQ_BUF_BGN_REG (CSR_DFX_GLB_CSR_BASE + 0x440) +#define CSR_DFX_GLB_CSR_DWQE_DROPPING_IN_TX_REG (CSR_DFX_GLB_CSR_BASE + 0x444) +#define CSR_DFX_GLB_CSR_DWQE_DROPPING_NO_BUF_REG (CSR_DFX_GLB_CSR_BASE + 0x448) +#define CSR_DFX_GLB_CSR_DWQE_DBL_WITHOUT_API_REG (CSR_DFX_GLB_CSR_BASE + 0x44C) +#define CSR_DFX_GLB_CSR_DWQE_TX_DBL_AFTER_API_REG (CSR_DFX_GLB_CSR_BASE + 0x450) +#define CSR_DFX_GLB_CSR_DWQE_NO_DBL_AFTER_API_REG (CSR_DFX_GLB_CSR_BASE + 0x454) +#define CSR_DFX_GLB_CSR_DWQE_BUF_OVERWRITE_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x458) +#define CSR_DFX_GLB_CSR_DWQE_BUF_AGING_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x45C) +#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_PUSH_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x460) +#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_POP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x464) +#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x468) +#define CSR_DFX_GLB_CSR_DWQE_DROPPING_INVLD_REG (CSR_DFX_GLB_CSR_BASE + 0x474) +#define CSR_DFX_GLB_CSR_DWQE_SW_FORCE_DROP_REG (CSR_DFX_GLB_CSR_BASE + 0x478) +#define CSR_DFX_GLB_CSR_ICTL_DBL_REQ_SOP_NULL_REG (CSR_DFX_GLB_CSR_BASE + 0x47C) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_MPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x480) +#define CSR_DFX_GLB_CSR_DFX_RX_DWQE_DDB_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x4A0) +#define CSR_DFX_GLB_CSR_DFX_RX_DWQE_DDB_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x4A4) +#define CSR_DFX_GLB_CSR_DFX_RX_DBL_SRV_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x4A8) +#define CSR_DFX_GLB_CSR_DFX_RX_DBL_SRV_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x4AC) +#define CSR_DFX_GLB_CSR_GLB_DFX_CFG_SRV_TYPE_REG (CSR_DFX_GLB_CSR_BASE + 0x4B0) +#define CSR_DFX_GLB_CSR_AEQ_CI_SW_WR_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4B4) +#define CSR_DFX_GLB_CSR_AEQ_TX_INT_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4BC) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_WR_PCIE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C0) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_WR_UCPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C4) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_RD_PCIE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C8) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_RD_UCPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4CC) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_OSCH_CPL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D0) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_ICTL_CPL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D4) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_APICTL_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D8) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_DST_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4DC) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_SRC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E0) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_STAT_TO_SRC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E4) +#define CSR_DFX_GLB_CSR_CPI_UCPU_MB_AEQE_TO_DST_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E8) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_AEQ_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4EC) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_CEQ_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F0) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_API_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F4) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_INTCTL_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F8) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_UPITF_CLP_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4FC) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR0_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x500) /* CPI internal RAM ECC error injection */ +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x504) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR2_REG (CSR_DFX_GLB_CSR_BASE + 0x508) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR3_REG (CSR_DFX_GLB_CSR_BASE + 0x50C) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_MERR0_REG (CSR_DFX_GLB_CSR_BASE + 0x520) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_MERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x524) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR0_REG (CSR_DFX_GLB_CSR_BASE + 0x540) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x544) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR0_REG (CSR_DFX_GLB_CSR_BASE + 0x560) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR1_REG (CSR_DFX_GLB_CSR_BASE + 0x564) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR2_REG (CSR_DFX_GLB_CSR_BASE + 0x568) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR3_REG (CSR_DFX_GLB_CSR_BASE + 0x56C) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED0_REG (CSR_DFX_GLB_CSR_BASE + 0x5C0) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED1_REG (CSR_DFX_GLB_CSR_BASE + 0x5C4) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED2_REG (CSR_DFX_GLB_CSR_BASE + 0x5C8) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED3_REG (CSR_DFX_GLB_CSR_BASE + 0x5CC) +#define CSR_DFX_GLB_CSR_GLB_CPI_UNCRT_ERR_CODE0_REG (CSR_DFX_GLB_CSR_BASE + 0x5D0) +#define CSR_DFX_GLB_CSR_GLB_CPI_UNCRT_ERR_CODE1_REG (CSR_DFX_GLB_CSR_BASE + 0x5D4) +#define CSR_DFX_GLB_CSR_GLB_CPI_CRT_ERR_CODE0_REG (CSR_DFX_GLB_CSR_BASE + 0x5D8) +#define CSR_DFX_GLB_CSR_GLB_CPI_CRT_ERR_CODE1_REG (CSR_DFX_GLB_CSR_BASE + 0x5DC) +#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG0_REG (CSR_DFX_GLB_CSR_BASE + 0x5E0) +#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG1_REG (CSR_DFX_GLB_CSR_BASE + 0x5E4) +#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG2_REG (CSR_DFX_GLB_CSR_BASE + 0x5E8) +#define CSR_DFX_GLB_CSR_DWQE_BUG_DBG3_REG (CSR_DFX_GLB_CSR_BASE + 0x5EC) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_TX_REQ_H_REG (CSR_DFX_GLB_CSR_BASE + 0x5F0) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_TX_REQ_L_REG (CSR_DFX_GLB_CSR_BASE + 0x5F4) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_GRANT_H_REG (CSR_DFX_GLB_CSR_BASE + 0x5F8) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_GRANT_L_REG (CSR_DFX_GLB_CSR_BASE + 0x5FC) +#define CSR_DFX_GLB_CSR_ICTL_IPUSH_SOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x608) +#define CSR_DFX_GLB_CSR_ICTL_IPUSH_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x60C) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_TX_REQ_H_REG (CSR_DFX_GLB_CSR_BASE + 0x610) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_TX_REQ_L_REG (CSR_DFX_GLB_CSR_BASE + 0x614) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_GRANT_H_REG (CSR_DFX_GLB_CSR_BASE + 0x618) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_GRANT_L_REG (CSR_DFX_GLB_CSR_BASE + 0x61C) +#define CSR_DFX_GLB_CSR_GLB_MB_TX_START_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x620) +#define CSR_DFX_GLB_CSR_GLB_MB_TX_ILLEGAL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x624) +#define CSR_DFX_GLB_CSR_GLB_MB_TX_ILLEGAL_CODE_REG (CSR_DFX_GLB_CSR_BASE + 0x628) +#define CSR_DFX_GLB_CSR_GLB_MB_FSM_STATE_REG (CSR_DFX_GLB_CSR_BASE + 0x62C) +#define CSR_DFX_GLB_CSR_ICTL_INBD_FIFO_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x638) +#define CSR_DFX_GLB_CSR_ICTL_DBL_SOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x640) +#define CSR_DFX_GLB_CSR_ICTL_DBL_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x644) +#define CSR_DFX_GLB_CSR_DWQE_DROP_NO_WR_BUF_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x648) +#define CSR_DFX_GLB_CSR_DWQE_WR_BUF_COMPLETE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x64C) +#define CSR_DFX_GLB_CSR_NORM_DBL_RX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x690) +#define CSR_DFX_GLB_CSR_NORM_DBL_FORCE_DROP_REG (CSR_DFX_GLB_CSR_BASE + 0x694) +#define CSR_DFX_GLB_CSR_DWQE_RX_BUF_BGN_REG (CSR_DFX_GLB_CSR_BASE + 0x698) +#define CSR_DFX_GLB_CSR_DWQE_ILLEGAL_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x69C) +#define CSR_DFX_GLB_CSR_DWQE_DBL_FORCE_DROP_NO_API_REG (CSR_DFX_GLB_CSR_BASE + 0x6A0) +#define CSR_DFX_GLB_CSR_DWQE_DBL_FORCE_DROP_AFT_API_REG (CSR_DFX_GLB_CSR_BASE + 0x6A4) +#define CSR_DFX_GLB_CSR_AEQ_FSM_DBG_STATE_REG (CSR_DFX_GLB_CSR_BASE + 0x6A8) +#define CSR_DFX_GLB_CSR_GLB_UCPU_MSI_FUNC_IDX_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6B0) /* the function index when ucpu access CSRs in the INT_CTL */ +#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_CTL_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6B4) /* the control register to measure the inbound itf */ +#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_CNT_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6B8) /* the result for the window detect for the mode */ +#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_TLP_CNT_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6BC) /* the result for the window detect for the TLP */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CNT_DBL_GRP_EN_REG (CSR_DFX_GLB_CSR_BASE + 0x6C0) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_TIMER_CFG_REG (CSR_DFX_GLB_CSR_BASE + 0x6C4) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CFG_PORT01_REG (CSR_DFX_GLB_CSR_BASE + 0x6C8) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CFG_PORT23_REG (CSR_DFX_GLB_CSR_BASE + 0x6CC) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT0_REG (CSR_DFX_GLB_CSR_BASE + 0x6D0) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT1_REG (CSR_DFX_GLB_CSR_BASE + 0x6D4) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT2_REG (CSR_DFX_GLB_CSR_BASE + 0x6D8) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT3_REG (CSR_DFX_GLB_CSR_BASE + 0x6DC) +#define CSR_DFX_GLB_CSR_CPATH_ENJ_A_FATAL_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x700) +#define CSR_DFX_GLB_CSR_CPATH_ENJ_A_NONFATAL_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x704) +#define CSR_DFX_GLB_CSR_CPATH_ENJ_FIFO_AFUL_TH_REG (CSR_DFX_GLB_CSR_BASE + 0x708) +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x710) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x714) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT2_REG (CSR_DFX_GLB_CSR_BASE + 0x718) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT3_REG (CSR_DFX_GLB_CSR_BASE + 0x71C) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT4_REG (CSR_DFX_GLB_CSR_BASE + 0x720) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT5_REG (CSR_DFX_GLB_CSR_BASE + 0x724) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT6_REG (CSR_DFX_GLB_CSR_BASE + 0x728) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT7_REG (CSR_DFX_GLB_CSR_BASE + 0x72C) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO0_REG (CSR_DFX_GLB_CSR_BASE + 0x730) /* CPATH内下RING FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO1_REG (CSR_DFX_GLB_CSR_BASE + 0x734) /* CPATH内下RING FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO2_REG (CSR_DFX_GLB_CSR_BASE + 0x738) /* CPATH内上RING FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO3_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x73C) /* CPATH内ICPL返回完成包接口FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO4_REG (CSR_DFX_GLB_CSR_BASE + 0x740) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO5_REG (CSR_DFX_GLB_CSR_BASE + 0x744) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO6_REG (CSR_DFX_GLB_CSR_BASE + 0x748) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO7_REG (CSR_DFX_GLB_CSR_BASE + 0x74C) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO8_REG (CSR_DFX_GLB_CSR_BASE + 0x750) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO9_REG (CSR_DFX_GLB_CSR_BASE + 0x754) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO0_REG (CSR_DFX_GLB_CSR_BASE + 0x758) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO1_REG (CSR_DFX_GLB_CSR_BASE + 0x75C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO2_REG (CSR_DFX_GLB_CSR_BASE + 0x760) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO3_REG (CSR_DFX_GLB_CSR_BASE + 0x764) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO4_REG (CSR_DFX_GLB_CSR_BASE + 0x768) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO5_REG (CSR_DFX_GLB_CSR_BASE + 0x76C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO6_REG (CSR_DFX_GLB_CSR_BASE + 0x770) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO7_REG (CSR_DFX_GLB_CSR_BASE + 0x774) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO8_REG (CSR_DFX_GLB_CSR_BASE + 0x778) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO9_REG (CSR_DFX_GLB_CSR_BASE + 0x77C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO10_REG (CSR_DFX_GLB_CSR_BASE + 0x780) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO11_REG (CSR_DFX_GLB_CSR_BASE + 0x784) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO12_REG (CSR_DFX_GLB_CSR_BASE + 0x788) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO13_REG (CSR_DFX_GLB_CSR_BASE + 0x78C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_CPATH_ENJ_PLS_REG (CSR_DFX_GLB_CSR_BASE + 0x7A0) +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS0_REG (CSR_DFX_GLB_CSR_BASE + 0x7B0) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS1_REG (CSR_DFX_GLB_CSR_BASE + 0x7B4) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS2_REG (CSR_DFX_GLB_CSR_BASE + 0x7B8) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS3_REG (CSR_DFX_GLB_CSR_BASE + 0x7BC) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS4_REG (CSR_DFX_GLB_CSR_BASE + 0x7C0) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_TCAM_CTRL_BUS0_REG (CSR_DFX_GLB_CSR_BASE + 0x7C4) /* ctrl_bus配置值，软件不要改。 */ + +/* dfx_ctrl_top_csr Base address of Module's Register */ +#define CSR_DFX_CTRL_TOP_CSR_BASE (0x43AF800) + +/* **************************************************************************** */ +/* dfx_ctrl_top_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x0) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_ARB_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x10) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x14) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x18) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x20) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x24) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x28) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x30) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x34) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x38) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_12_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x3C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_13_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x40) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_14_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x44) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_15_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x48) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_16_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_17_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x50) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_18_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x54) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_19_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x58) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_20_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x5C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_21_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x60) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_22_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x64) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_23_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x68) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_24_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_25_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x70) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_26_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x74) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_27_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x78) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_28_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x7C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_29_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x80) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_30_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x84) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_31_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x88) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_32_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x8C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_33_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x90) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_34_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x94) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA0) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA4) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO0_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB0) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO1_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB4) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO2_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO3_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xBC) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO4_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC0) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO5_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC4) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO6_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO7_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xCC) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_FIFO_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x100) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_ARB_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x108) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x110) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x114) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x118) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x11C) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x120) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x124) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x128) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x12C) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x130) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x134) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x138) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x13C) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x150) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x154) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x158) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_RO_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x180) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_RO_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x184) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_20_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x198) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_21_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x19C) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1AC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1BC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1CC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_12_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_13_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_14_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_15_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1DC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_16_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_17_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_18_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_19_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1EC) +#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F0) +#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F4) +#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F8) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x200) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x204) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x208) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x20C) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x210) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x214) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x218) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x21C) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x220) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x224) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x228) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x22C) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_FIFO_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x280) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_FIFO_STS_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x290) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_STS_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x294) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A0) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A4) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A8) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_WEIGHT_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x400) +#define CSR_DFX_CTRL_TOP_CSR_OSCH_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x404) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x408) +#define CSR_DFX_CTRL_TOP_CSR_DWQE_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x40C) +#define CSR_DFX_CTRL_TOP_CSR_QMAP_TCAM_RSVD_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x410) +#define CSR_DFX_CTRL_TOP_CSR_NVME_DB_COS_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x440) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DB_COS_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x444) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x448) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CFG_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x44C) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_STS0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x490) +#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_DLY_TIMER_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x498) +#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_DLY_TIMER_UNIT_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x49C) +#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_ENABLE_DLY_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4A0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_MCTP_RX_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4B0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_PCIE_ITF_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4B4) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_RSVD_Q_CFG_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x500) /* VIRTIO缺省队列配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_RSVD_Q_CFG_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x504) /* VIRTIO缺省队列配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_CFG0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A0) /* 三网合一功能的cos配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_CFG1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A4) /* 三网合一功能的cos配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_RP_EN_ALL_REG \ + (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A8) /* 三网合一时替换使能cos功能 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DIRECT_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6AC) /* 将满水线DFX */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_API_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6B0) /* 将满水线DFX */ + +/* dfx_cpath_csr Base address of Module's Register */ +#define CSR_DFX_CPATH_CSR_BASE (0x43B0800) + +/* **************************************************************************** */ +/* dfx_cpath_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_CPATH_CSR_CPATH_CSR_INJ_ENJ_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x10) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_INJ_ENJ_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x14) +#define CSR_DFX_CPATH_CSR_CPATH_NON_CPI_INT_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x1C) +#define CSR_DFX_CPATH_CSR_CPATH_ENJ_RSVD_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x20) +#define CSR_DFX_CPATH_CSR_CPATH_ENJ_NML_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x24) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_OUBD_CNT_TYPE_REG (CSR_DFX_CPATH_CSR_BASE + 0x2C) +#define CSR_DFX_CPATH_CSR_CPATH_FIFO_AFUL_GAP_0_REG (CSR_DFX_CPATH_CSR_BASE + 0x30) +#define CSR_DFX_CPATH_CSR_CPATH_RESERVD_REG (CSR_DFX_CPATH_CSR_BASE + 0x3C) /* ECO保留 */ +#define CSR_DFX_CPATH_CSR_CPATH_ITF_STS_OUT_REG (CSR_DFX_CPATH_CSR_BASE + 0x44) +#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PE1_REG (CSR_DFX_CPATH_CSR_BASE + 0x4C) +#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PE0_REG (CSR_DFX_CPATH_CSR_BASE + 0x50) +#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PI_REG (CSR_DFX_CPATH_CSR_BASE + 0x54) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PE1_REG (CSR_DFX_CPATH_CSR_BASE + 0x58) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PE0_REG (CSR_DFX_CPATH_CSR_BASE + 0x5C) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PI_REG (CSR_DFX_CPATH_CSR_BASE + 0x60) +#define CSR_DFX_CPATH_CSR_CPATH_OUT_PLS_REG (CSR_DFX_CPATH_CSR_BASE + 0x70) +#define CSR_DFX_CPATH_CSR_GLB_IJT_NODE_ID_BITMAP_REG (CSR_DFX_CPATH_CSR_BASE + 0x80) +#define CSR_DFX_CPATH_CSR_GLB_EJT_NODE_ID_BITMAP_REG (CSR_DFX_CPATH_CSR_BASE + 0x84) +#define CSR_DFX_CPATH_CSR_CPATH_OUT_A_FATAL_MSK_REG (CSR_DFX_CPATH_CSR_BASE + 0x100) +#define CSR_DFX_CPATH_CSR_CPATH_OUT_A_NONFATAL_MSK_REG (CSR_DFX_CPATH_CSR_BASE + 0x104) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK0_REG (CSR_DFX_CPATH_CSR_BASE + 0x110) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK1_REG (CSR_DFX_CPATH_CSR_BASE + 0x114) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK2_REG (CSR_DFX_CPATH_CSR_BASE + 0x118) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK3_REG (CSR_DFX_CPATH_CSR_BASE + 0x11C) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK4_REG (CSR_DFX_CPATH_CSR_BASE + 0x120) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK5_REG (CSR_DFX_CPATH_CSR_BASE + 0x124) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK6_REG (CSR_DFX_CPATH_CSR_BASE + 0x128) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK7_REG (CSR_DFX_CPATH_CSR_BASE + 0x12C) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK8_REG (CSR_DFX_CPATH_CSR_BASE + 0x130) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK9_REG (CSR_DFX_CPATH_CSR_BASE + 0x134) + +/* dfx_apictl_csr Base address of Module's Register */ +#define CSR_DFX_APICTL_CSR_BASE (0x43B2000) + +/* **************************************************************************** */ +/* dfx_apictl_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_APICTL_CSR_APICTL_DBG_SEL_REG (CSR_DFX_APICTL_CSR_BASE + 0x0) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH0_REG (CSR_DFX_APICTL_CSR_BASE + 0x4) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH1_REG (CSR_DFX_APICTL_CSR_BASE + 0x8) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH2_REG (CSR_DFX_APICTL_CSR_BASE + 0xC) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH3_REG (CSR_DFX_APICTL_CSR_BASE + 0x10) +#define CSR_DFX_APICTL_CSR_APICTL_CNT2_REG (CSR_DFX_APICTL_CSR_BASE + 0x18) +#define CSR_DFX_APICTL_CSR_APICTL_CNT3_REG (CSR_DFX_APICTL_CSR_BASE + 0x1C) +#define CSR_DFX_APICTL_CSR_APICTL_CNT4_REG (CSR_DFX_APICTL_CSR_BASE + 0x20) +#define CSR_DFX_APICTL_CSR_APICTL_CNT5_REG (CSR_DFX_APICTL_CSR_BASE + 0x24) +#define CSR_DFX_APICTL_CSR_APICTL_CNT6_REG (CSR_DFX_APICTL_CSR_BASE + 0x28) +#define CSR_DFX_APICTL_CSR_APICTL_RESERVD_REG (CSR_DFX_APICTL_CSR_BASE + 0x2C) /* ECO保留 */ +#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_PLS_REG (CSR_DFX_APICTL_CSR_BASE + 0x30) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_PLS_REG (CSR_DFX_APICTL_CSR_BASE + 0x34) +#define CSR_DFX_APICTL_CSR_APICTL_NON_CSR_TIMER_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x38) +#define CSR_DFX_APICTL_CSR_APICTL_CSR_TIMER_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x3C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_A_REG (CSR_DFX_APICTL_CSR_BASE + 0x40) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_B_REG (CSR_DFX_APICTL_CSR_BASE + 0x44) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_C_REG (CSR_DFX_APICTL_CSR_BASE + 0x48) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_D_REG (CSR_DFX_APICTL_CSR_BASE + 0x4C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_E_REG (CSR_DFX_APICTL_CSR_BASE + 0x50) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_F_REG (CSR_DFX_APICTL_CSR_BASE + 0x54) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_G_REG (CSR_DFX_APICTL_CSR_BASE + 0x58) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_H_REG (CSR_DFX_APICTL_CSR_BASE + 0x5C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_I_REG (CSR_DFX_APICTL_CSR_BASE + 0x60) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_J_REG (CSR_DFX_APICTL_CSR_BASE + 0x64) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_K_REG (CSR_DFX_APICTL_CSR_BASE + 0x68) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_L_REG (CSR_DFX_APICTL_CSR_BASE + 0x6C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_M_REG (CSR_DFX_APICTL_CSR_BASE + 0x70) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_N_REG (CSR_DFX_APICTL_CSR_BASE + 0x74) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_O_REG (CSR_DFX_APICTL_CSR_BASE + 0x78) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_P_REG (CSR_DFX_APICTL_CSR_BASE + 0x7C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Q_REG (CSR_DFX_APICTL_CSR_BASE + 0x80) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_R_REG (CSR_DFX_APICTL_CSR_BASE + 0x84) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_S_REG (CSR_DFX_APICTL_CSR_BASE + 0x88) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_T_REG (CSR_DFX_APICTL_CSR_BASE + 0x8C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_U_REG (CSR_DFX_APICTL_CSR_BASE + 0x90) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_V_REG (CSR_DFX_APICTL_CSR_BASE + 0x94) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_W_REG (CSR_DFX_APICTL_CSR_BASE + 0x98) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_X_REG (CSR_DFX_APICTL_CSR_BASE + 0x9C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Y_REG (CSR_DFX_APICTL_CSR_BASE + 0xA0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Z_REG (CSR_DFX_APICTL_CSR_BASE + 0xA4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_A_REG (CSR_DFX_APICTL_CSR_BASE + 0xB0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_B_REG (CSR_DFX_APICTL_CSR_BASE + 0xB4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_C_REG (CSR_DFX_APICTL_CSR_BASE + 0xB8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_D_REG (CSR_DFX_APICTL_CSR_BASE + 0xBC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_E_REG (CSR_DFX_APICTL_CSR_BASE + 0xC0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_F_REG (CSR_DFX_APICTL_CSR_BASE + 0xC4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_G_REG (CSR_DFX_APICTL_CSR_BASE + 0xC8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_H_REG (CSR_DFX_APICTL_CSR_BASE + 0xCC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_I_REG (CSR_DFX_APICTL_CSR_BASE + 0xD0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_J_REG (CSR_DFX_APICTL_CSR_BASE + 0xD4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_K_REG (CSR_DFX_APICTL_CSR_BASE + 0xD8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_L_REG (CSR_DFX_APICTL_CSR_BASE + 0xDC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_M_REG (CSR_DFX_APICTL_CSR_BASE + 0xE0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_N_REG (CSR_DFX_APICTL_CSR_BASE + 0xE4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_O_REG (CSR_DFX_APICTL_CSR_BASE + 0xE8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_P_REG (CSR_DFX_APICTL_CSR_BASE + 0xEC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_Q_REG (CSR_DFX_APICTL_CSR_BASE + 0xF0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_R_REG (CSR_DFX_APICTL_CSR_BASE + 0xF4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_S_REG (CSR_DFX_APICTL_CSR_BASE + 0xF8) +#define CSR_DFX_APICTL_CSR_INBD_RING_BUF_CRDT_REG \ + (CSR_DFX_APICTL_CSR_BASE + 0x108) /* inbound API到uP侧的非bypass ring buffer 信用控制寄存器 */ +#define CSR_DFX_APICTL_CSR_INBD_CMD_RD_SO_RO_REG \ + (CSR_DFX_APICTL_CSR_BASE + 0x10C) /* API chain发送到host侧的读写命令SO/RO控制寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_RO_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x110) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_RO_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x114) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x118) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x11C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_2_REG (CSR_DFX_APICTL_CSR_BASE + 0x120) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_3_REG (CSR_DFX_APICTL_CSR_BASE + 0x124) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_4_REG (CSR_DFX_APICTL_CSR_BASE + 0x128) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_5_REG (CSR_DFX_APICTL_CSR_BASE + 0x12C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_6_REG (CSR_DFX_APICTL_CSR_BASE + 0x130) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_7_REG (CSR_DFX_APICTL_CSR_BASE + 0x134) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_8_REG (CSR_DFX_APICTL_CSR_BASE + 0x138) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_9_REG (CSR_DFX_APICTL_CSR_BASE + 0x13C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_10_REG (CSR_DFX_APICTL_CSR_BASE + 0x140) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_11_REG (CSR_DFX_APICTL_CSR_BASE + 0x144) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_12_REG (CSR_DFX_APICTL_CSR_BASE + 0x148) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_13_REG (CSR_DFX_APICTL_CSR_BASE + 0x14C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_14_REG (CSR_DFX_APICTL_CSR_BASE + 0x150) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_RO_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x180) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_RO_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x184) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x188) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x18C) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_2_REG (CSR_DFX_APICTL_CSR_BASE + 0x190) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_3_REG (CSR_DFX_APICTL_CSR_BASE + 0x194) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_4_REG (CSR_DFX_APICTL_CSR_BASE + 0x198) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_5_REG (CSR_DFX_APICTL_CSR_BASE + 0x19C) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_6_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A0) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_7_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A4) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_8_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A8) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_9_REG (CSR_DFX_APICTL_CSR_BASE + 0x1AC) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_10_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B0) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_11_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B4) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_12_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B8) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_13_REG (CSR_DFX_APICTL_CSR_BASE + 0x1BC) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_FATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x200) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_FATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x204) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_NONFATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x210) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_NONFATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x214) +#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL0_REG (CSR_DFX_APICTL_CSR_BASE + 0x220) /* api chain权限控制 */ +#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL1_REG (CSR_DFX_APICTL_CSR_BASE + 0x224) /* api chain权限控制 */ +#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL2_REG (CSR_DFX_APICTL_CSR_BASE + 0x228) /* api chain权限控制 */ +#define CSR_DFX_APICTL_CSR_APICTL_TAG_CMP_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x230) +#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT0_REG (CSR_DFX_APICTL_CSR_BASE + 0x240) +#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT1_REG (CSR_DFX_APICTL_CSR_BASE + 0x244) +#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT2_REG (CSR_DFX_APICTL_CSR_BASE + 0x248) +#define CSR_DFX_APICTL_CSR_APIITF_RING_DEST_ILLG_SRC_REG (CSR_DFX_APICTL_CSR_BASE + 0x24C) + +/* CPI_DMA_CSR Base address of Module's Register */ +#define CSR_CPI_DMA_CSR_BASE (0x43B3000) + +/* **************************************************************************** */ +/* CPI_DMA_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_DMA_CSR_DMA_INDRECT_CTRL_REG (CSR_CPI_DMA_CSR_BASE + 0x0) /* CPI DMA 中间接访控制寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_TIMEOUT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x4) /* dma Indirect Access Timeout Register。 */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_0_REG (CSR_CPI_DMA_CSR_BASE + 0x8) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_1_REG (CSR_CPI_DMA_CSR_BASE + 0xC) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_2_REG (CSR_CPI_DMA_CSR_BASE + 0x10) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_3_REG (CSR_CPI_DMA_CSR_BASE + 0x14) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_4_REG (CSR_CPI_DMA_CSR_BASE + 0x18) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_5_REG (CSR_CPI_DMA_CSR_BASE + 0x1C) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_6_REG (CSR_CPI_DMA_CSR_BASE + 0x20) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_7_REG (CSR_CPI_DMA_CSR_BASE + 0x24) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_CPI_DMA_RAM_TMODE_REG (CSR_CPI_DMA_CSR_BASE + 0x40) /* CPI internal RAM test mode */ +#define CSR_CPI_DMA_CSR_MSI_BAR_OFFSET_REG (CSR_CPI_DMA_CSR_BASE + 0x44) /* 表示配置MSI bar的偏移。 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x50) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x60) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x70) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x80) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x90) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x54) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x64) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x74) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x84) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x94) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x58) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x68) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x78) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x88) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x98) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_CEQ_NUM_ACC_WEIGHT_REG (CSR_CPI_DMA_CSR_BASE + 0xB0) /* CEQ 分配RAM访问权重寄存器 */ +#define CSR_CPI_DMA_CSR_COPY_EP_2_COS_EN_REG (CSR_CPI_DMA_CSR_BASE + 0xB4) /* 第五host copyEP到COS 使能寄存器。 */ +#define CSR_CPI_DMA_CSR_DMA_ATTR_NUM_REG (CSR_CPI_DMA_CSR_BASE + 0xB8) /* CPI内DMA属性配置寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_0_REG (CSR_CPI_DMA_CSR_BASE + 0xBC) /* DMA控制寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_RAM_INIT_REG (CSR_CPI_DMA_CSR_BASE + 0xC0) /* DMA侧ram初始化寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_RAM_STATUS_REG (CSR_CPI_DMA_CSR_BASE + 0xC4) /* DMA侧ram初始化状态寄存器 */ +#define CSR_CPI_DMA_CSR_PCIE_TIMEOUT_REG (CSR_CPI_DMA_CSR_BASE + 0xD0) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_PCIE_TAG_FORCE_REG (CSR_CPI_DMA_CSR_BASE + 0xD4) /* 强制回收某PF/VF的读命令 */ +#define CSR_CPI_DMA_CSR_PCIE_TAG_FORCE_ITF_REG (CSR_CPI_DMA_CSR_BASE + 0xD8) /* 强制回收某PCIe端口的读命令 */ +#define CSR_CPI_DMA_CSR_TIMEOUT_DLY_CFG_REG (CSR_CPI_DMA_CSR_BASE + 0xDC) /* 配置超时tag重复利用的静默时间 */ +#define CSR_CPI_DMA_CSR_PCIE_CFG_MOD_REG (CSR_CPI_DMA_CSR_BASE + 0xE0) /* 表示CPI使用pcie 配置空间的模式 */ +#define CSR_CPI_DMA_CSR_PCIE_CFG_LOC_SET_REG (CSR_CPI_DMA_CSR_BASE + 0xE4) /* 表示CPI使用pcie 配置空间的模式 */ +#define CSR_CPI_DMA_CSR_SPU_CFG_LOC_SET_REG (CSR_CPI_DMA_CSR_BASE + 0xE8) /* 表示CPI使用SPU侧pcie 配置空间的模式 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO0_REG (CSR_CPI_DMA_CSR_BASE + 0xEC) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO1_REG (CSR_CPI_DMA_CSR_BASE + 0xF0) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO2_REG (CSR_CPI_DMA_CSR_BASE + 0xF4) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO3_REG (CSR_CPI_DMA_CSR_BASE + 0xF8) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO4_REG (CSR_CPI_DMA_CSR_BASE + 0xFC) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_0_REG (CSR_CPI_DMA_CSR_BASE + 0x100) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_1_REG (CSR_CPI_DMA_CSR_BASE + 0x120) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_2_REG (CSR_CPI_DMA_CSR_BASE + 0x140) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_3_REG (CSR_CPI_DMA_CSR_BASE + 0x160) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_4_REG (CSR_CPI_DMA_CSR_BASE + 0x180) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_0_REG (CSR_CPI_DMA_CSR_BASE + 0x104) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_1_REG (CSR_CPI_DMA_CSR_BASE + 0x124) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_2_REG (CSR_CPI_DMA_CSR_BASE + 0x144) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_3_REG (CSR_CPI_DMA_CSR_BASE + 0x164) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_4_REG (CSR_CPI_DMA_CSR_BASE + 0x184) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_0_REG (CSR_CPI_DMA_CSR_BASE + 0x108) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_1_REG (CSR_CPI_DMA_CSR_BASE + 0x128) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_2_REG (CSR_CPI_DMA_CSR_BASE + 0x148) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_3_REG (CSR_CPI_DMA_CSR_BASE + 0x168) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_4_REG (CSR_CPI_DMA_CSR_BASE + 0x188) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_0_REG (CSR_CPI_DMA_CSR_BASE + 0x10C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_1_REG (CSR_CPI_DMA_CSR_BASE + 0x12C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_2_REG (CSR_CPI_DMA_CSR_BASE + 0x14C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_3_REG (CSR_CPI_DMA_CSR_BASE + 0x16C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_4_REG (CSR_CPI_DMA_CSR_BASE + 0x18C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_0_REG (CSR_CPI_DMA_CSR_BASE + 0x110) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_1_REG (CSR_CPI_DMA_CSR_BASE + 0x130) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_2_REG (CSR_CPI_DMA_CSR_BASE + 0x150) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_3_REG (CSR_CPI_DMA_CSR_BASE + 0x170) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_4_REG (CSR_CPI_DMA_CSR_BASE + 0x190) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_0_REG (CSR_CPI_DMA_CSR_BASE + 0x114) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_1_REG (CSR_CPI_DMA_CSR_BASE + 0x134) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_2_REG (CSR_CPI_DMA_CSR_BASE + 0x154) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_3_REG (CSR_CPI_DMA_CSR_BASE + 0x174) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_4_REG (CSR_CPI_DMA_CSR_BASE + 0x194) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_0_REG (CSR_CPI_DMA_CSR_BASE + 0x118) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_1_REG (CSR_CPI_DMA_CSR_BASE + 0x138) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_2_REG (CSR_CPI_DMA_CSR_BASE + 0x158) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_3_REG (CSR_CPI_DMA_CSR_BASE + 0x178) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_4_REG (CSR_CPI_DMA_CSR_BASE + 0x198) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_0_REG (CSR_CPI_DMA_CSR_BASE + 0x11C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_1_REG (CSR_CPI_DMA_CSR_BASE + 0x13C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_2_REG (CSR_CPI_DMA_CSR_BASE + 0x15C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_3_REG (CSR_CPI_DMA_CSR_BASE + 0x17C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_4_REG (CSR_CPI_DMA_CSR_BASE + 0x19C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT0_REG (CSR_CPI_DMA_CSR_BASE + 0x240) /* PDI 模块统计计数器0 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT1_REG (CSR_CPI_DMA_CSR_BASE + 0x244) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT2_REG (CSR_CPI_DMA_CSR_BASE + 0x248) /* PDI 模块统计计数器2 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT3_REG (CSR_CPI_DMA_CSR_BASE + 0x24C) /* PDI 模块统计计数器3 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT4_REG (CSR_CPI_DMA_CSR_BASE + 0x250) /* PDI 模块统计计数器4 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT5_REG (CSR_CPI_DMA_CSR_BASE + 0x254) /* PDI 模块统计计数器5 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT6_REG (CSR_CPI_DMA_CSR_BASE + 0x258) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT7_REG (CSR_CPI_DMA_CSR_BASE + 0x25C) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT8_REG (CSR_CPI_DMA_CSR_BASE + 0x260) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT9_REG (CSR_CPI_DMA_CSR_BASE + 0x264) /* PDI 模块统计计数器2 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT10_REG (CSR_CPI_DMA_CSR_BASE + 0x268) /* PDI 模块统计计数器2 */ +#define CSR_CPI_DMA_CSR_CEQ_BLK_CNT_REG (CSR_CPI_DMA_CSR_BASE + 0x2A0) /* CEQ 模块统计计数器 */ +#define CSR_CPI_DMA_CSR_CEQ_CSR_ST_REG (CSR_CPI_DMA_CSR_BASE + 0x2A4) /* CEQ 模块各状态寄存器 */ +#define CSR_CPI_DMA_CSR_FLR_RCV_CNT0_REG (CSR_CPI_DMA_CSR_BASE + 0x2B0) /* CPI接收FLR统计计数器 */ +#define CSR_CPI_DMA_CSR_FLR_RCV_CNT1_REG (CSR_CPI_DMA_CSR_BASE + 0x2B4) /* CPI接收FLR统计计数器 */ +#define CSR_CPI_DMA_CSR_FLR_RCV_CNT2_REG (CSR_CPI_DMA_CSR_BASE + 0x2B8) /* CPI接收FLR统计计数器 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS0_REG (CSR_CPI_DMA_CSR_BASE + 0x2E0) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS1_REG (CSR_CPI_DMA_CSR_BASE + 0x2E4) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS2_REG (CSR_CPI_DMA_CSR_BASE + 0x2E8) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS3_REG (CSR_CPI_DMA_CSR_BASE + 0x2EC) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS4_REG (CSR_CPI_DMA_CSR_BASE + 0x2F0) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_CTL_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x300) /* the control register to measure the inbound itf */ +#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_CNT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x304) /* the result for the window detect for the mode */ +#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_TLP_CNT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x308) /* the result for the window detect for the TLP */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_0_REG (CSR_CPI_DMA_CSR_BASE + 0x340) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_1_REG (CSR_CPI_DMA_CSR_BASE + 0x344) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_2_REG (CSR_CPI_DMA_CSR_BASE + 0x348) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_3_REG (CSR_CPI_DMA_CSR_BASE + 0x34C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_4_REG (CSR_CPI_DMA_CSR_BASE + 0x350) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_5_REG (CSR_CPI_DMA_CSR_BASE + 0x354) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_6_REG (CSR_CPI_DMA_CSR_BASE + 0x358) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_7_REG (CSR_CPI_DMA_CSR_BASE + 0x35C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_8_REG (CSR_CPI_DMA_CSR_BASE + 0x360) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_9_REG (CSR_CPI_DMA_CSR_BASE + 0x364) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_10_REG (CSR_CPI_DMA_CSR_BASE + 0x368) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_11_REG (CSR_CPI_DMA_CSR_BASE + 0x36C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_12_REG (CSR_CPI_DMA_CSR_BASE + 0x370) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_13_REG (CSR_CPI_DMA_CSR_BASE + 0x374) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_14_REG (CSR_CPI_DMA_CSR_BASE + 0x378) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_15_REG (CSR_CPI_DMA_CSR_BASE + 0x37C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_SEL_REG (CSR_CPI_DMA_CSR_BASE + 0x380) /* select the tag timeout funciton */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_CLEAR_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x384) /* clear the selected funciton tag timeout */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_ST_OUT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x388) /* read the selected funciton tag timeout */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_GROUP_ST_OUT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x38C) /* read the selected funciton tag timeout */ +#define CSR_CPI_DMA_CSR_CPI_PDI_A_FATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3E0) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_A_NONFATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3E4) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_A_INT_PLS_REG (CSR_CPI_DMA_CSR_BASE + 0x3E8) /* PDI模块中断状态寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_B_FATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3F0) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_B_NONFATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3F4) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_B_INT_PLS_REG (CSR_CPI_DMA_CSR_BASE + 0x3F8) /* PDI模块中断状态寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_0_REG (CSR_CPI_DMA_CSR_BASE + 0x400) /* the enable for virtio capability */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_1_REG (CSR_CPI_DMA_CSR_BASE + 0x404) /* the enable for virtio capability */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_127_REG (CSR_CPI_DMA_CSR_BASE + 0x5FC) /* the enable for virtio capability \ + */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_00VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x600) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_01VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x604) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_02VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x608) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_03VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x60C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_04VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x610) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_05VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x614) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_06VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x618) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_07VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x61C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_08VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x620) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_09VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x630) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_10VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x634) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_11VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x638) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_12VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x63C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_13VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x640) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_14VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x644) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_15VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x648) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_16VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x64C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_00VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x680) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_01VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x684) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_02VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x688) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_03VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x68C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_04VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x690) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_05VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x694) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_06VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x698) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_07VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x69C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_08VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6A0) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_09VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6B0) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_10VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6B4) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_11VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6B8) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_12VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6BC) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_13VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6C0) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_14VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6C4) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_15VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6C8) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_16VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6CC) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ECC_CERR_REG (CSR_CPI_DMA_CSR_BASE + 0x700) +#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ECC_UCERR_REG (CSR_CPI_DMA_CSR_BASE + 0x704) +#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ERR_ADDR_REG (CSR_CPI_DMA_CSR_BASE + 0x708) +#define CSR_CPI_DMA_CSR_DMATOP_ECC_INJ_REQ_REG (CSR_CPI_DMA_CSR_BASE + 0x710) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_A_REG (CSR_CPI_DMA_CSR_BASE + 0x720) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_B_REG (CSR_CPI_DMA_CSR_BASE + 0x724) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_C_REG (CSR_CPI_DMA_CSR_BASE + 0x728) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_D_REG (CSR_CPI_DMA_CSR_BASE + 0x72C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_E_REG (CSR_CPI_DMA_CSR_BASE + 0x730) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_F_REG (CSR_CPI_DMA_CSR_BASE + 0x734) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_G_REG (CSR_CPI_DMA_CSR_BASE + 0x738) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_H_REG (CSR_CPI_DMA_CSR_BASE + 0x73C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_I_REG (CSR_CPI_DMA_CSR_BASE + 0x740) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_J_REG (CSR_CPI_DMA_CSR_BASE + 0x744) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_K_REG (CSR_CPI_DMA_CSR_BASE + 0x748) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_L_REG (CSR_CPI_DMA_CSR_BASE + 0x74C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_M_REG (CSR_CPI_DMA_CSR_BASE + 0x750) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_N_REG (CSR_CPI_DMA_CSR_BASE + 0x754) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_O_REG (CSR_CPI_DMA_CSR_BASE + 0x758) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_P_REG (CSR_CPI_DMA_CSR_BASE + 0x75C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_Q_REG (CSR_CPI_DMA_CSR_BASE + 0x760) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_R_REG (CSR_CPI_DMA_CSR_BASE + 0x764) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_S_REG (CSR_CPI_DMA_CSR_BASE + 0x768) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_T_REG (CSR_CPI_DMA_CSR_BASE + 0x76C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_U_REG (CSR_CPI_DMA_CSR_BASE + 0x770) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_A_REG (CSR_CPI_DMA_CSR_BASE + 0x780) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_B_REG (CSR_CPI_DMA_CSR_BASE + 0x784) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_C_REG (CSR_CPI_DMA_CSR_BASE + 0x788) + +/* CPI_ICPL_CSR Base address of Module's Register */ +#define CSR_CPI_ICPL_CSR_BASE (0x43B3800) + +/* **************************************************************************** */ +/* CPI_ICPL_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_ICPL_CSR_DP_NORMAL_CHL_EN_REG (CSR_CPI_ICPL_CSR_BASE + 0x0) /* 表示dpath普通channel使能寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_RAM_INIT_REG (CSR_CPI_ICPL_CSR_BASE + 0x44) /* DMA侧ram初始化寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_RAM_STATUS_REG (CSR_CPI_ICPL_CSR_BASE + 0x48) /* DMA侧ram初始化状态寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_FIFO_AFUL_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x50) +#define CSR_CPI_ICPL_CSR_ICPL_FIFO_AFUL_CTL1_REG (CSR_CPI_ICPL_CSR_BASE + 0x54) +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x100) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x120) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x140) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x160) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x180) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x104) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x124) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x144) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x164) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x184) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x108) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x128) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x148) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x168) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x188) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x10C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x12C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x14C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x16C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x18C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_0_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x110) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_1_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x130) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_2_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x150) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_3_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x170) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_4_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x190) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_0_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x114) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_1_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x134) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_2_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x154) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_3_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x174) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_4_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x194) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT0_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A0) /* ICPL内仲裁权重寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT1_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A4) /* ICPL内仲裁权重寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT2_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A8) /* ICPL内仲裁权重寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_CTRL_MOD_REG (CSR_CPI_ICPL_CSR_BASE + 0x1AC) /* ICPL内模式配置就存起 */ +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_SEL_REG (CSR_CPI_ICPL_CSR_BASE + 0x300) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x304) /* ICPL控制测量RTT的控制寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX0_REG (CSR_CPI_ICPL_CSR_BASE + 0x308) /* ICPL用于配置待测量的TAG 编号0。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX1_REG (CSR_CPI_ICPL_CSR_BASE + 0x30C) /* ICPL用于配置待测量的TAG 编号1。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX2_REG (CSR_CPI_ICPL_CSR_BASE + 0x310) /* ICPL用于配置待测量的TAG 编号2。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x314) /* ICPL用于测量RTT范围的控制寄存器。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG1_REG (CSR_CPI_ICPL_CSR_BASE + 0x318) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG2_REG (CSR_CPI_ICPL_CSR_BASE + 0x31C) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG3_REG (CSR_CPI_ICPL_CSR_BASE + 0x320) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG4_REG (CSR_CPI_ICPL_CSR_BASE + 0x324) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_CUR_REG (CSR_CPI_ICPL_CSR_BASE + 0x328) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_A_REG (CSR_CPI_ICPL_CSR_BASE + 0x360) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_B_REG (CSR_CPI_ICPL_CSR_BASE + 0x364) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_C_REG (CSR_CPI_ICPL_CSR_BASE + 0x368) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_D_REG (CSR_CPI_ICPL_CSR_BASE + 0x36C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_E_REG (CSR_CPI_ICPL_CSR_BASE + 0x370) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_F_REG (CSR_CPI_ICPL_CSR_BASE + 0x374) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_G_REG (CSR_CPI_ICPL_CSR_BASE + 0x378) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_H_REG (CSR_CPI_ICPL_CSR_BASE + 0x37C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_I_REG (CSR_CPI_ICPL_CSR_BASE + 0x380) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_J_REG (CSR_CPI_ICPL_CSR_BASE + 0x384) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_K_REG (CSR_CPI_ICPL_CSR_BASE + 0x388) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_L_REG (CSR_CPI_ICPL_CSR_BASE + 0x38C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_M_REG (CSR_CPI_ICPL_CSR_BASE + 0x390) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_N_REG (CSR_CPI_ICPL_CSR_BASE + 0x394) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_O_REG (CSR_CPI_ICPL_CSR_BASE + 0x398) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_P_REG (CSR_CPI_ICPL_CSR_BASE + 0x39C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Q_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A0) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_R_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A4) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_S_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A8) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_T_REG (CSR_CPI_ICPL_CSR_BASE + 0x3AC) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_U_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B0) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_V_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B4) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_W_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B8) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_X_REG (CSR_CPI_ICPL_CSR_BASE + 0x3BC) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Y_REG (CSR_CPI_ICPL_CSR_BASE + 0x3C0) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Z_REG (CSR_CPI_ICPL_CSR_BASE + 0x3C4) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x400) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x410) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x420) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x430) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x440) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x450) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x460) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x470) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x408) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x418) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x428) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x438) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x448) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x458) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x468) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x478) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x40C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x41C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x42C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x43C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x44C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x45C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x46C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x47C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT2_REG (CSR_CPI_ICPL_CSR_BASE + 0x480) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT3_REG (CSR_CPI_ICPL_CSR_BASE + 0x484) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT4_REG (CSR_CPI_ICPL_CSR_BASE + 0x488) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT5_REG (CSR_CPI_ICPL_CSR_BASE + 0x48C) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x490) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x494) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x498) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x49C) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x4AC) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_8_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_9_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_10_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_11_REG (CSR_CPI_ICPL_CSR_BASE + 0x4BC) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_12_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_13_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_14_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_15_REG (CSR_CPI_ICPL_CSR_BASE + 0x4CC) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_16_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_17_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_18_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_19_REG (CSR_CPI_ICPL_CSR_BASE + 0x4DC) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_A_REG (CSR_CPI_ICPL_CSR_BASE + 0x500) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_B_REG (CSR_CPI_ICPL_CSR_BASE + 0x504) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_C_REG (CSR_CPI_ICPL_CSR_BASE + 0x508) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_D_REG (CSR_CPI_ICPL_CSR_BASE + 0x50C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_E_REG (CSR_CPI_ICPL_CSR_BASE + 0x510) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_F_REG (CSR_CPI_ICPL_CSR_BASE + 0x514) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_G_REG (CSR_CPI_ICPL_CSR_BASE + 0x518) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_H_REG (CSR_CPI_ICPL_CSR_BASE + 0x51C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_I_REG (CSR_CPI_ICPL_CSR_BASE + 0x520) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_J_REG (CSR_CPI_ICPL_CSR_BASE + 0x524) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_K_REG (CSR_CPI_ICPL_CSR_BASE + 0x528) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_L_REG (CSR_CPI_ICPL_CSR_BASE + 0x52C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_M_REG (CSR_CPI_ICPL_CSR_BASE + 0x530) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_N_REG (CSR_CPI_ICPL_CSR_BASE + 0x534) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_O_REG (CSR_CPI_ICPL_CSR_BASE + 0x538) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_P_REG (CSR_CPI_ICPL_CSR_BASE + 0x53C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_Q_REG (CSR_CPI_ICPL_CSR_BASE + 0x540) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_R_REG (CSR_CPI_ICPL_CSR_BASE + 0x544) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_S_REG (CSR_CPI_ICPL_CSR_BASE + 0x548) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_T_REG (CSR_CPI_ICPL_CSR_BASE + 0x54C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_U_REG (CSR_CPI_ICPL_CSR_BASE + 0x550) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_V_REG (CSR_CPI_ICPL_CSR_BASE + 0x554) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_W_REG (CSR_CPI_ICPL_CSR_BASE + 0x558) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_X_REG (CSR_CPI_ICPL_CSR_BASE + 0x55C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_Y_REG (CSR_CPI_ICPL_CSR_BASE + 0x560) +#define CSR_CPI_ICPL_CSR_ICPL_PLSA_FATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E0) +#define CSR_CPI_ICPL_CSR_ICPL_PLSA_NONFATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E4) +#define CSR_CPI_ICPL_CSR_ICPL_PLSA_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E8) +#define CSR_CPI_ICPL_CSR_ICPL_PLSB_FATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F0) +#define CSR_CPI_ICPL_CSR_ICPL_PLSB_NONFATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F4) +#define CSR_CPI_ICPL_CSR_ICPL_PLSB_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F8) +#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ECC_CERR_REG (CSR_CPI_ICPL_CSR_BASE + 0x600) +#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ECC_UCERR_REG (CSR_CPI_ICPL_CSR_BASE + 0x604) +#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ERR_ADDR_REG (CSR_CPI_ICPL_CSR_BASE + 0x608) +#define CSR_CPI_ICPL_CSR_ICPL_ECC_INJ_REQ_REG (CSR_CPI_ICPL_CSR_BASE + 0x610) + +/* CPI_INTCTL_CSR Base address of Module's Register */ +#define CSR_CPI_INTCTL_CSR_BASE (0x43B4000) + +/* **************************************************************************** */ +/* CPI_INTCTL_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_INTCTL_CSR_INTCTL_INT_CTL_REG (CSR_CPI_INTCTL_CSR_BASE + 0x0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_BITMAP_REG (CSR_CPI_INTCTL_CSR_BASE + 0x8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_BITMAP_WNDW_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_AB_REG (CSR_CPI_INTCTL_CSR_BASE + 0x10) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_CD_REG (CSR_CPI_INTCTL_CSR_BASE + 0x14) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_EF_REG (CSR_CPI_INTCTL_CSR_BASE + 0x18) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_GH_REG (CSR_CPI_INTCTL_CSR_BASE + 0x1C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_AB_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x20) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_CD_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x24) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_EF_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x28) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_GH_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_IPUSH_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x30) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_CFG_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x34) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSK_TRIG_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x38) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_COAL_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x3C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_COAL_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x40) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSI_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x44) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSIX_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x48) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_VCT_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x4C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_ASSERT_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x50) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_ASSERT_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x54) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_DEASSERT_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x58) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_DEASSERT_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x5C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_A_REG (CSR_CPI_INTCTL_CSR_BASE + 0x60) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_B_REG (CSR_CPI_INTCTL_CSR_BASE + 0x64) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_C_REG (CSR_CPI_INTCTL_CSR_BASE + 0x68) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_D_REG (CSR_CPI_INTCTL_CSR_BASE + 0x6C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_E_REG (CSR_CPI_INTCTL_CSR_BASE + 0x70) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_F_REG (CSR_CPI_INTCTL_CSR_BASE + 0x74) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_G_REG (CSR_CPI_INTCTL_CSR_BASE + 0x78) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_H_REG (CSR_CPI_INTCTL_CSR_BASE + 0x7C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_I_REG (CSR_CPI_INTCTL_CSR_BASE + 0x80) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_J_REG (CSR_CPI_INTCTL_CSR_BASE + 0x84) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_K_REG (CSR_CPI_INTCTL_CSR_BASE + 0x88) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_L_REG (CSR_CPI_INTCTL_CSR_BASE + 0x8C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_M_REG (CSR_CPI_INTCTL_CSR_BASE + 0x90) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_N_REG (CSR_CPI_INTCTL_CSR_BASE + 0x94) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_O_REG (CSR_CPI_INTCTL_CSR_BASE + 0x98) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x9C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Q_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_R_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_S_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_T_REG (CSR_CPI_INTCTL_CSR_BASE + 0xAC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_U_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_V_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_W_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_X_REG (CSR_CPI_INTCTL_CSR_BASE + 0xBC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Y_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Z_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_A_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_B_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_C_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_D_REG (CSR_CPI_INTCTL_CSR_BASE + 0xDC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_E_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_F_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_G_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_H_REG (CSR_CPI_INTCTL_CSR_BASE + 0xEC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_I_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_J_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_K_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_L_REG (CSR_CPI_INTCTL_CSR_BASE + 0xFC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_M_REG (CSR_CPI_INTCTL_CSR_BASE + 0x100) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_N_REG (CSR_CPI_INTCTL_CSR_BASE + 0x104) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_O_REG (CSR_CPI_INTCTL_CSR_BASE + 0x108) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x10C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_Q_REG (CSR_CPI_INTCTL_CSR_BASE + 0x110) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_R_REG (CSR_CPI_INTCTL_CSR_BASE + 0x114) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_DROP_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x120) +#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x200) +#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_2ND_01P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x204) +#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_2ND_23P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x208) +#define CSR_CPI_INTCTL_CSR_INTCTL_FLR_LIMIT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x220) +#define CSR_CPI_INTCTL_CSR_INTCTL_RESERVD_REG (CSR_CPI_INTCTL_CSR_BASE + 0x230) /* ECO保留 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_A_FATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E0) +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_A_NONFATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_A_PLUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E8) +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_B_FATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F0) +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_B_NONFATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_B_PLUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F8) +#define CSR_CPI_INTCTL_CSR_INTCTL_RAM_INIT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x310) /* DMA侧ram初始化寄存器 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_RAM_STATUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x314) /* DMA侧ram初始化状态寄存器 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_CTL_REG (CSR_CPI_INTCTL_CSR_BASE + 0x318) /* intctl模块控制寄存器 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_RES_REG (CSR_CPI_INTCTL_CSR_BASE + 0x31C) /* int ctl 资源配置 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_CSR_ACC_WEIGHT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x320) /* 中断模块访问权重控制寄存器 \ + */ +#define CSR_CPI_INTCTL_CSR_INTCTL1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x324) +#define CSR_CPI_INTCTL_CSR_INTCTL2_REG (CSR_CPI_INTCTL_CSR_BASE + 0x328) +#define CSR_CPI_INTCTL_CSR_INTCTL3_REG (CSR_CPI_INTCTL_CSR_BASE + 0x32C) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ECC_CERR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x400) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ECC_UCERR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x404) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ERR_ADDR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x408) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_MULTI_ERR_ADDR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x40C) +#define CSR_CPI_INTCTL_CSR_INTCTL_ECC_INJ_REQ_REG (CSR_CPI_INTCTL_CSR_BASE + 0x410) + +/* CPI_OCTL_CSR Base address of Module's Register */ +#define CSR_CPI_OCTL_CSR_BASE (0x43B4800) + +/* **************************************************************************** */ +/* CPI_OCTL_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_CTRL0_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x0) /* CPI_OCTL internal table indirect access ctrl registers */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_CTRL1_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x4) /* CPI_OCTL internal table indirect access ctrl registers */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_0_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x8) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_1_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0xC) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_2_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x10) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_3_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x14) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_4_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x18) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_5_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x1C) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_6_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x20) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_7_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x24) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_RAM_INIT_REQ_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x28) /* CPI_OCTL internal RAM initial request */ +#define CSR_CPI_OCTL_CSR_OCTL_RAM_INIT_STS_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C) /* CPI_OCTL internal RAM initial status \ + */ +#define CSR_CPI_OCTL_CSR_PRE_SUB_DAT_CRD_CPB_REG (CSR_CPI_OCTL_CSR_BASE + 0x30) /* Data Credit presub value from CPB \ + */ +#define CSR_CPI_OCTL_CSR_L2NIC_CI_WR_CHL_CFG_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x34) /* specifies the D-Path channel for the CI write. */ +#define CSR_CPI_OCTL_CSR_CQE_WR_CHL_CFG_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x38) /* specifies the D-Path channel for the CQE write. */ +#define CSR_CPI_OCTL_CSR_PCIE_PORT_CFG_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x3C) /* specifies which PCIe port's FIFO configuration */ +#define CSR_CPI_OCTL_CSR_DMA_PE_YYY_FIFO_DEPTH_PORT012_REG (CSR_CPI_OCTL_CSR_BASE + 0x40) +#define CSR_CPI_OCTL_CSR_DMA_PE_YYY_FIFO_DEPTH_PORT34_REG (CSR_CPI_OCTL_CSR_BASE + 0x44) +#define CSR_CPI_OCTL_CSR_CPI_PREALLOC_CPB_BUF_REG (CSR_CPI_OCTL_CSR_BASE + 0x48) /* the pre-alloc CPB buffers */ +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x50) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x54) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x58) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x5C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_5_REG (CSR_CPI_OCTL_CSR_BASE + 0x60) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_6_REG (CSR_CPI_OCTL_CSR_BASE + 0x64) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_7_REG (CSR_CPI_OCTL_CSR_BASE + 0x68) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_8_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_9_REG (CSR_CPI_OCTL_CSR_BASE + 0x70) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_10_REG (CSR_CPI_OCTL_CSR_BASE + 0x74) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_11_REG (CSR_CPI_OCTL_CSR_BASE + 0x78) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_12_REG (CSR_CPI_OCTL_CSR_BASE + 0x7C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_13_REG (CSR_CPI_OCTL_CSR_BASE + 0x80) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_14_REG (CSR_CPI_OCTL_CSR_BASE + 0x84) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_15_REG (CSR_CPI_OCTL_CSR_BASE + 0x88) +#define CSR_CPI_OCTL_CSR_OCTL_CUT_THR_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x8C) +#define CSR_CPI_OCTL_CSR_OCTL_IN_CMD_CHNL_SRC_SEL_REG (CSR_CPI_OCTL_CSR_BASE + 0x94) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_REG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x98) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_REG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x9C) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0xA0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0xA4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_C_REG (CSR_CPI_OCTL_CSR_BASE + 0xA8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_D_REG (CSR_CPI_OCTL_CSR_BASE + 0xAC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_A_REG (CSR_CPI_OCTL_CSR_BASE + 0xB0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_B_REG (CSR_CPI_OCTL_CSR_BASE + 0xB4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_C_REG (CSR_CPI_OCTL_CSR_BASE + 0xB8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_D_REG (CSR_CPI_OCTL_CSR_BASE + 0xBC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_E_REG (CSR_CPI_OCTL_CSR_BASE + 0xC0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_F_REG (CSR_CPI_OCTL_CSR_BASE + 0xC4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_G_REG (CSR_CPI_OCTL_CSR_BASE + 0xC8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_H_REG (CSR_CPI_OCTL_CSR_BASE + 0xCC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_I_REG (CSR_CPI_OCTL_CSR_BASE + 0xD0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_J_REG (CSR_CPI_OCTL_CSR_BASE + 0xD4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_K_REG (CSR_CPI_OCTL_CSR_BASE + 0xD8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_L_REG (CSR_CPI_OCTL_CSR_BASE + 0xDC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_M_REG (CSR_CPI_OCTL_CSR_BASE + 0xE0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_N_REG (CSR_CPI_OCTL_CSR_BASE + 0xE4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_O_REG (CSR_CPI_OCTL_CSR_BASE + 0xE8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_P_REG (CSR_CPI_OCTL_CSR_BASE + 0xEC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Q_REG (CSR_CPI_OCTL_CSR_BASE + 0xF0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_R_REG (CSR_CPI_OCTL_CSR_BASE + 0xF4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_S_REG (CSR_CPI_OCTL_CSR_BASE + 0xF8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_T_REG (CSR_CPI_OCTL_CSR_BASE + 0xFC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_U_REG (CSR_CPI_OCTL_CSR_BASE + 0x100) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_V_REG (CSR_CPI_OCTL_CSR_BASE + 0x104) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_W_REG (CSR_CPI_OCTL_CSR_BASE + 0x108) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_X_REG (CSR_CPI_OCTL_CSR_BASE + 0x10C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Y_REG (CSR_CPI_OCTL_CSR_BASE + 0x110) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Z_REG (CSR_CPI_OCTL_CSR_BASE + 0x114) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x118) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x11C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x120) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x124) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x128) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x12C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x130) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x134) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x138) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x13C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x140) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x144) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x148) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x14C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x150) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x154) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x158) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x15C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AS_REG (CSR_CPI_OCTL_CSR_BASE + 0x160) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AT_REG (CSR_CPI_OCTL_CSR_BASE + 0x164) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AU_REG (CSR_CPI_OCTL_CSR_BASE + 0x168) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AV_REG (CSR_CPI_OCTL_CSR_BASE + 0x16C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AW_REG (CSR_CPI_OCTL_CSR_BASE + 0x170) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AX_REG (CSR_CPI_OCTL_CSR_BASE + 0x174) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AY_REG (CSR_CPI_OCTL_CSR_BASE + 0x178) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AZ_REG (CSR_CPI_OCTL_CSR_BASE + 0x17C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BA_REG (CSR_CPI_OCTL_CSR_BASE + 0x180) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x184) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BC_REG (CSR_CPI_OCTL_CSR_BASE + 0x188) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x220) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x260) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x224) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x264) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x228) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x268) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1AC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1EC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x22C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x26C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2AC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x230) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x270) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x234) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x274) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x238) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x278) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1BC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1FC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x23C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x27C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2BC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x200) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x240) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x280) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x204) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x244) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x284) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x208) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x248) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x288) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1CC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x20C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x24C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x28C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2CC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1D0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x210) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x250) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x290) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2D0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1D4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x214) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x254) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x294) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2D4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BD_REG (CSR_CPI_OCTL_CSR_BASE + 0x300) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BE_REG (CSR_CPI_OCTL_CSR_BASE + 0x304) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BF_REG (CSR_CPI_OCTL_CSR_BASE + 0x308) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BG_REG (CSR_CPI_OCTL_CSR_BASE + 0x30C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BH_REG (CSR_CPI_OCTL_CSR_BASE + 0x310) +#define CSR_CPI_OCTL_CSR_OCTL_DPATH_O_ERR_DFX_REG (CSR_CPI_OCTL_CSR_BASE + 0x340) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BK_REG (CSR_CPI_OCTL_CSR_BASE + 0x350) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BL_REG (CSR_CPI_OCTL_CSR_BASE + 0x354) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x358) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x35C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x360) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x364) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x368) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x36C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x370) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x374) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x378) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x37C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x380) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x384) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x388) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x38C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x390) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x394) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x398) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x39C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AS_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AT_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AU_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AV_REG (CSR_CPI_OCTL_CSR_BASE + 0x3AC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AW_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AX_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AY_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AZ_REG (CSR_CPI_OCTL_CSR_BASE + 0x3BC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BA_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BC_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BD_REG (CSR_CPI_OCTL_CSR_BASE + 0x3CC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BE_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BF_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BG_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BH_REG (CSR_CPI_OCTL_CSR_BASE + 0x3DC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BI_REG (CSR_CPI_OCTL_CSR_BASE + 0x3E0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x3E4) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_BYPASS_REG (CSR_CPI_OCTL_CSR_BASE + 0x3F8) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x3FC) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x400) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x404) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x408) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x40C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x410) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x414) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x418) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x41C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x420) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x424) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x428) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x42C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x430) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x434) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x438) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x43C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x440) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x444) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x448) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x44C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x450) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x454) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x458) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x45C) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x460) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x464) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x468) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x46C) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x470) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x474) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x478) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x47C) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x480) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x484) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x488) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x48C) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x490) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x4AC) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x4BC) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x4CC) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x4D0) +#define CSR_CPI_OCTL_CSR_OCTL_EC_SORO_ATTR_TBL_FIRST_REG (CSR_CPI_OCTL_CSR_BASE + 0x4E4) +#define CSR_CPI_OCTL_CSR_OCTL_EC_SORO_ATTR_TBL_SECOND_REG (CSR_CPI_OCTL_CSR_BASE + 0x4E8) +#define CSR_CPI_OCTL_CSR_OCTL_EC_CHANNEL_ENABLE_REG (CSR_CPI_OCTL_CSR_BASE + 0x4EC) +#define CSR_CPI_OCTL_CSR_OCTL_SM_CBUF_I_READY_CHNL_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F0) +#define CSR_CPI_OCTL_CSR_OCTL_SM_CBUF_I_READY_CHNL_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F4) +#define CSR_CPI_OCTL_CSR_OCTL_MUL_HOST_DIF_RD_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F8) +#define CSR_CPI_OCTL_CSR_OCTL_DB_WR_ADDR_L_REG (CSR_CPI_OCTL_CSR_BASE + 0x4FC) +#define CSR_CPI_OCTL_CSR_OCTL_DB_WR_ADDR_H_REG (CSR_CPI_OCTL_CSR_BASE + 0x500) +#define CSR_CPI_OCTL_CSR_OCTL_ENDIAN_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x504) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x560) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x564) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x568) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x56C) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x570) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x574) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x578) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x57C) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x580) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x584) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x588) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x58C) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_G_REG (CSR_CPI_OCTL_CSR_BASE + 0x590) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_H_REG (CSR_CPI_OCTL_CSR_BASE + 0x594) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x598) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x59C) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A4) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_I_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A8) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_J_REG (CSR_CPI_OCTL_CSR_BASE + 0x5AC) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_K_REG (CSR_CPI_OCTL_CSR_BASE + 0x5B0) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_L_REG (CSR_CPI_OCTL_CSR_BASE + 0x5B4) +#define CSR_CPI_OCTL_CSR_OCTL_PE_PARSER_CFG_1ST_REG (CSR_CPI_OCTL_CSR_BASE + 0x650) +#define CSR_CPI_OCTL_CSR_OCTL_LOOP_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x654) +#define CSR_CPI_OCTL_CSR_OCTL_LOOP_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x658) +#define CSR_CPI_OCTL_CSR_OCTL_DFX_SIG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x65C) +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x674) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x684) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x694) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6A4) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6B4) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x678) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x688) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x698) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6A8) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6B8) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x67C) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x68C) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x69C) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6AC) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6BC) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C0) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C4) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C8) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x6CC) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D0) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D4) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D8) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x6DC) +#define CSR_CPI_OCTL_CSR_CPI_OCTL_CPATH_CRDT_REG (CSR_CPI_OCTL_CSR_BASE + 0x718) /* CPATH信用配置寄存器 */ +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_ONE_REG (CSR_CPI_OCTL_CSR_BASE + 0x71C) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_TWO_REG (CSR_CPI_OCTL_CSR_BASE + 0x720) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_THREE_REG (CSR_CPI_OCTL_CSR_BASE + 0x724) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_FOUR_REG (CSR_CPI_OCTL_CSR_BASE + 0x728) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_FIVE_REG (CSR_CPI_OCTL_CSR_BASE + 0x72C) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x730) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x734) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_M_REG (CSR_CPI_OCTL_CSR_BASE + 0x738) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_N_REG (CSR_CPI_OCTL_CSR_BASE + 0x73C) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_O_REG (CSR_CPI_OCTL_CSR_BASE + 0x740) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_P_REG (CSR_CPI_OCTL_CSR_BASE + 0x744) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_CC_REG (CSR_CPI_OCTL_CSR_BASE + 0x748) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_DD_REG (CSR_CPI_OCTL_CSR_BASE + 0x74C) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_EE_REG (CSR_CPI_OCTL_CSR_BASE + 0x750) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_EN_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x754) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_EN_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x758) +#define CSR_CPI_OCTL_CSR_CPI_OCTL_MUL_WR_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x75C) +#define CSR_CPI_OCTL_CSR_CPI_OCTL_CQE_CTL_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x760) + +/* CPI_OSCH_CSR Base address of Module's Register */ +#define CSR_CPI_OSCH_CSR_BASE (0x43B5000) + +/* **************************************************************************** */ +/* CPI_OSCH_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x0) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x4) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x8) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xC) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x10) /* 单纯 的基于port统计drop数量。对应HVA P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_ERROR_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x14) /* 单纯的基于port统计err数量。对应P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_ERROR_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x18) /* 单纯的基于port统计err数量。对应P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x20) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是PCIe的P报文。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x24) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x28) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x2C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x30) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x34) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x38) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x3C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x40) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x44) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x48) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x4C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x50) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x54) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x58) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC01_REG (CSR_CPI_OSCH_CSR_BASE + 0x60) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC23_REG (CSR_CPI_OSCH_CSR_BASE + 0x64) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC45_REG (CSR_CPI_OSCH_CSR_BASE + 0x68) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC67_REG (CSR_CPI_OSCH_CSR_BASE + 0x6C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC89_REG (CSR_CPI_OSCH_CSR_BASE + 0x70) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1011_REG (CSR_CPI_OSCH_CSR_BASE + 0x74) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1213_REG (CSR_CPI_OSCH_CSR_BASE + 0x78) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1415_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C) +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_DROP_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x90) /* ceqe drop counter统计。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_PI_OVERFLOW_REG (CSR_CPI_OSCH_CSR_BASE + 0x94) /* 有统计信号 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_OVERFLOW_LOW_REG \ + (CSR_CPI_OSCH_CSR_BASE + \ + 0x98) /* osch所有的fifo overflow统计信号这个地方使用OR的方式操作overflow告警，不对，需要展开。 */ +#define CSR_CPI_OSCH_CSR_OSCH_REQ_TIMEOUT_REG (CSR_CPI_OSCH_CSR_BASE + 0x9C) /* 检测oschoutbound request 超时状态 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_HIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xA0) /* osch 所有fifo的empty告警信号，中域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_LOW_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xA4) /* osch 所有fifo的empty告警信号，低域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_HIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xA8) /* osch 所有fifo的AFULL告警信号，中域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_LOW_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xAC) /* osch 所有fifo的AFULL告警信号，低域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_PAYLOAD_FIFO_CTRL_REG (CSR_CPI_OSCH_CSR_BASE + 0xB0) /* payload fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_MSI_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xB4) /* msi_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_MSI_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xB8) /* msi_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ATOMIC_TX_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xBC) /* atomic_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ATOMIC_TX_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xC0) /* atomic_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xC4) /* ceqe_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xC8) /* ceqe_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPLD_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xD0) /* cpld_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPLD_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xD4) /* cpld_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_TOPHIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xD8) /* osch 所有fifo的empty告警信号，最高域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_TOPHIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xDC) /* osch 所有fifo的AFULL告警信号，高域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q0_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xF0) /* CPATH Q0FIFO的afull反压门限， \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q0_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xF4) /* CPATH Q0FIFO的afull反压门限， \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q1_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x100) /* CPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q1_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x104) /* CPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q2_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x110) /* CPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q2_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x114) /* CPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q0_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x120) /* DPATH Q0FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q0_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x124) /* DPATH Q0FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q1_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x130) /* DPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q1_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x134) /* DPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q2_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x140) /* DPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q2_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x144) /* DPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q3_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x150) /* DPATH Q3FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q3_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x154) /* DPATH Q3FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q4_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x160) /* DPATH Q4FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q4_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x164) /* DPATH Q4FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_RESERVED0_REG (CSR_CPI_OSCH_CSR_BASE + 0x170) +#define CSR_CPI_OSCH_CSR_OSCH_RESERVED1_REG (CSR_CPI_OSCH_CSR_BASE + 0x174) +#define CSR_CPI_OSCH_CSR_OSCH_RESERVED2_REG (CSR_CPI_OSCH_CSR_BASE + 0x178) +#define CSR_CPI_OSCH_CSR_GLB_POST_HEAD_CREDIT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x180) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_POST_PAYLOAD_CREDIT_H_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x184) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_POST_PAYLOAD_CREDIT_L_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x188) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_NON_POST_HEAD_CREDIT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x190) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_NON_POST_PAYLOAD_CREDIT_H_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x194) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_NON_POST_PAYLOAD_CREDIT_L_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x198) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_CPL_HEAD_CREDIT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x1A0) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_CPL_PAYLOAD_CREDIT_H_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x1A4) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_CPL_PAYLOAD_CREDIT_L_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x1A8) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_OSCH_CEQE_IN_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x1B0) /* 内部capture信号 */ +#define CSR_CPI_OSCH_CSR_GLB_OSCH_CEQE_OUT_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x1B4) +#define CSR_CPI_OSCH_CSR_GLB_CEQE_DROP_TAIL_REG (CSR_CPI_OSCH_CSR_BASE + 0x1C0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x1DC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x1E0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x1FC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x200) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x210) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x214) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x218) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x21C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x220) +#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT01_REG (CSR_CPI_OSCH_CSR_BASE + 0x230) +#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT23_REG (CSR_CPI_OSCH_CSR_BASE + 0x234) +#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x238) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_BP_STS_REG (CSR_CPI_OSCH_CSR_BASE + 0x240) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q0_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x250) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q0_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x254) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q1_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x260) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q1_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x264) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q2_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x270) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q2_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x274) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q3_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x280) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q3_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x284) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q4_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x290) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q4_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x294) +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x298) +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_PERIOD_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A0) +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A4) /* PCIE的P类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A8) /* PCIE的P类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x300) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x340) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x380) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3C0) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x400) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x304) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x344) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x384) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3C4) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x404) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x308) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x348) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x388) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3C8) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x408) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x30C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x34C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x38C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3CC) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x40C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x310) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x350) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x390) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3D0) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x410) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x314) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x354) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x394) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3D4) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x414) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x318) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x358) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x398) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3D8) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x418) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x320) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x360) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A0) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E0) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x420) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x324) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x364) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A4) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E4) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x424) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x328) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x368) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A8) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E8) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x428) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x32C) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x36C) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3AC) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3EC) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x42C) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x330) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x370) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3B0) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3F0) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x430) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CTRL_DOORBELL_CNT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x500) /* 伪装成DMA 写命令发送给CPI_CTRL的doorbell，对齐的统计计数。 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x504) /* 通道0 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x508) /* 通道0 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x50C) /* 通道0 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x510) /* 通道1 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x514) /* 通道1 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x518) /* 通道1 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x51C) /* 通道2 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x520) /* 通道2 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x524) /* 通道2 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x528) /* 通道3 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x52C) /* 通道3 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x530) /* 通道3 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x534) /* 通道4 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x538) /* 通道4 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x53C) /* 通道4 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x540) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x544) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x548) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x54C) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x550) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_5_REG (CSR_CPI_OSCH_CSR_BASE + 0x554) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x558) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x55C) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x560) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x564) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x568) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_5_REG (CSR_CPI_OSCH_CSR_BASE + 0x56C) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x570) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x574) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x578) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x57C) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x580) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_5_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x584) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x588) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x58C) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x590) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x594) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x598) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_SEL_REG (CSR_CPI_OSCH_CSR_BASE + 0x59C) /* PORT0~4内ECC 错误地址上报选择 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5A0) /* OSCH内FIFO的overflow告警中断上报。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5A4) /* OSCH内FIFO的overflow告警中断上报。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5A8) /* OSCH内FIFO的overflow告警中断上报。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5AC) /* OSCH内FIFO的overflow告警中断开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5B0) /* OSCH内FIFO的overflow告警中断开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5B4) /* OSCH内FIFO的overflow告警中断开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CRT_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x5B8) /* OSCH内的可纠错误中断上报 */ +#define CSR_CPI_OSCH_CSR_OSCH_UNCRT_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x5BC) /* OSCH内的不可纠错误中断上报 */ +#define CSR_CPI_OSCH_CSR_OSCH_CRT_ERR_INT_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C0) /* OSCH内的可纠错误中断上报开关 */ +#define CSR_CPI_OSCH_CSR_OSCH_UNCRT_ERR_INT_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C4) /* OSCH内的不可纠错误中断上报开关 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ACTIVE_EN_CFG_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C8) /* OSCH内的tx_crd_active_en自定义输出 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_NL2NIC_OUTSTANDING_BP_CFG_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5CC) /* OSCH内各port的AAD FIFO的non l2nic outstanding的bp门限 */ +#define CSR_CPI_OSCH_CSR_CEQ_CLS_FIFO_ST_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x600) /* cqe cls fifo status_err */ +#define CSR_CPI_OSCH_CSR_GLB_CQE_CI_D_CHL_REG (CSR_CPI_OSCH_CSR_BASE + 0x604) /* CQE_CI_DP_CHL */ +#define CSR_CPI_OSCH_CSR_GLB_DMA_SO_RO_REPLACE_REG (CSR_CPI_OSCH_CSR_BASE + 0x608) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_RLS_TAG_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x60C) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_TIMEOUT_REG (CSR_CPI_OSCH_CSR_BASE + 0x610) +#define CSR_CPI_OSCH_CSR_GLB_CP_CQE_CREDIT_PORT_REG (CSR_CPI_OSCH_CSR_BASE + 0x614) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_HI_LMT_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x618) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_HI_LMT_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x61C) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_LO_LMT_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x620) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_LO_LMT_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x624) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_OUT_RANGE_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x628) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_OUT_RANGE_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x62C) +#define CSR_CPI_OSCH_CSR_OSCH_PAYLOAD_FIFO1_CTRL_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x630) /* payload fifo1的afull反压门限。(位宽转换FIFO) */ +#define CSR_CPI_OSCH_CSR_OSCH_DBELL_FIFO_CTRL_REG (CSR_CPI_OSCH_CSR_BASE + 0x634) /* doorbell fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_WR_CMD_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x638) /* wr cmd 转DOORBELL的使能信号。 \ + */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_INITIAL_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x63C) /* wr cmd 转DOORBELL的信用的置位信号 */ +#define CSR_CPI_OSCH_CSR_CFG_DPATH_XTS_RD_REG (CSR_CPI_OSCH_CSR_BASE + 0x640) /* 针对XTS对应通道的配置使能 */ +#define CSR_CPI_OSCH_CSR_CFG_ROUND_BIT_CHECK_MOD_REG (CSR_CPI_OSCH_CSR_BASE + 0x650) /* ROUND BIT 检查开关。 */ +#define CSR_CPI_OSCH_CSR_CFG_PORT1_TO_PORT0_MODE_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x660) /* PORT1 channel到PORT0资源的路由开关。 */ +#define CSR_CPI_OSCH_CSR_CFG_NON_L2NIC_LOOP2_EDGE_EN_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x670) /* 在non l2nic inline 数据在第二轮进入Dpath_rd通路时。是否判定F_L边界。 */ +#define CSR_CPI_OSCH_CSR_CFG_CUR_CPL_TIMEOUT_DROP_MAX_REG (CSR_CPI_OSCH_CSR_BASE + 0x674) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x700) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x704) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x708) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x70C) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x710) /* 单纯 的基于port统计drop数量。对应HVA NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_ERROR_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x714) /* 单纯的基于port统计err数量。对应NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_ERROR_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x718) /* 单纯的基于port统计err数量。对应NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x720) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是PCIE的NP/CPL报文 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x724) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x728) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x72C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x730) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x734) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x738) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x73C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x740) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x744) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x748) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x74C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x750) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x754) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x758) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x75C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x760) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是HVA端口的的P报文 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x764) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x768) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x76C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x770) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x774) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x778) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x77C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x780) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x784) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x788) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x78C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x790) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x794) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x798) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x79C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x7A0) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是HVA端口的的NP/CPL报文 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x7A4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x7A8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x7AC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x7BC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x7CC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x7DC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_COUNT_MODE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7E0) +#define CSR_CPI_OSCH_CSR_OSCH_NPCPL_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7E8) /* PCIE的NPCPL类型TLP长度统计 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_NPCPL_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x7EC) /* PCIE的NPCPL类型TLP长度统计 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_P_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F0) /* HVA的P类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_P_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F4) /* HVA的NPCPL类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_NPCPL_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F8) /* HVA的P类型TLP长度统计 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_NPCPL_PERF_WATCH_TLP_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x7FC) /* HVA的NPCPL类型TLP长度统计 */ + +#endif // CPI_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_c_union_define.h new file mode 100644 index 000000000..71faa9bfd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_c_union_define.h @@ -0,0 +1,6226 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : crypto_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/7/25 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/25 10:01:08 Create file +// ****************************************************************************** + +#ifndef CRYPTO_C_UNION_DEFINE_H +#define CRYPTO_C_UNION_DEFINE_H +/* Define the union csr_am_ctrl_global_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_shutdown_req : 1; /* [0] */ + u32 ctrl_lat_stat_rd_en : 1; /* [1] */ + u32 ctrl_lat_stat_wr_en : 1; /* [2] */ + u32 rsv_0 : 1; /* [3] */ + u32 rd_rate_limit : 4; /* [7:4] */ + u32 wr_rate_limit : 4; /* [11:8] */ + u32 rsv_1 : 4; /* [15:12] */ + u32 ctrl_en_rd_256byte_global : 1; /* [16] */ + u32 ctrl_en_wr_256byte_global : 1; /* [17] */ + u32 ctrl_clkgt_en : 1; /* [18] */ + u32 rsv_2 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_ctrl_global_u; + +/* Define the union csr_am_ctrl_latency_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_lat_rd_port_sel : 4; /* [3:0] */ + u32 rsv_3 : 4; /* [7:4] */ + u32 ctrl_lat_wr_port_sel : 4; /* [11:8] */ + u32 rsv_4 : 4; /* [15:12] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_ctrl_latency_sel_u; + +/* Define the union csr_am_ctrl_ptl_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_ptl_wr_64byte : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_ctrl_ptl_wr_u; + +/* Define the union csr_am_cfg_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_rd_trans : 8; /* [7:0] */ + u32 cfg_max_wr_trans : 8; /* [15:8] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_max_trans_u; + +/* Define the union csr_am_cfg_single_port_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_sgl_port_rd_trans : 8; /* [7:0] */ + u32 cfg_max_sgl_port_wr_trans : 8; /* [15:8] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_single_port_max_trans_u; + +/* Define the union csr_am_cfg_port_rd_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_rd_en : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_port_rd_en_u; + +/* Define the union csr_am_cfg_port_wr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_wr_en : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_port_wr_en_u; + +/* Define the union csr_am_curr_aw_w_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_w_tx_port : 16; /* [15:0] */ + u32 curr_w_tx_stock : 2; /* [17:16] */ + u32 curr_w_tx_idle : 1; /* [18] */ + u32 rsv_11 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_aw_w_fifo_sts_u; + +/* Define the union csr_am_curr_port_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_port_sts : 16; /* [15:0] */ + u32 curr_wr_port_sts : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_port_sts_u; + +/* Define the union csr_am_rob_ecc_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rob_ecc_err_onebit : 1; /* [0] */ + u32 rob_ecc_err_multpl : 1; /* [1] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_rob_ecc_int_sts_u; + +/* Define the union csr_am_rob_ecc_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ecc_err_detect_int_msk : 1; /* [0] */ + u32 cfg_ecc_err_multpl_int_msk : 1; /* [1] */ + u32 rsv_13 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_rob_ecc_int_mask_u; + +/* Define the union csr_am_rob_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rob_ecc_onebit_err_addr : 12; /* [11:0] */ + u32 rob_ecc_multpl_err_addr : 12; /* [23:12] */ + u32 rsv_14 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_rob_ecc_err_addr_u; + +/* Define the union csr_am_curr_max_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_max_rd_latency : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_max_rd_latency_u; + +/* Define the union csr_am_curr_ava_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_ava_rd_latency : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_ava_rd_latency_u; + +/* Define the union csr_am_curr_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_latency : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_latency_u; + +/* Define the union csr_am_curr_max_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_max_wr_latency : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_max_wr_latency_u; + +/* Define the union csr_am_curr_ava_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_ava_wr_latency : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_ava_wr_latency_u; + +/* Define the union csr_am_curr_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_latency : 16; /* [15:0] */ + u32 rsv_20 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_latency_u; + +/* Define the union csr_am_curr_trans_return_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_all_rd_returned : 1; /* [0] */ + u32 curr_all_wr_returned : 1; /* [1] */ + u32 rsv_21 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_trans_return_u; + +/* Define the union csr_am_curr_rd_max_txid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_max_txid : 7; /* [6:0] */ + u32 rsv_22 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_max_txid_u; + +/* Define the union csr_am_curr_wr_max_txid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_max_txid : 7; /* [6:0] */ + u32 rsv_23 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_max_txid_u; + +/* Define the union csr_am_curr_rd_txid_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_txid_sts_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_txid_sts_0_u; + +/* Define the union csr_am_curr_rd_txid_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_txid_sts_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_txid_sts_1_u; + +/* Define the union csr_am_curr_rd_txid_sts_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_txid_sts_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_txid_sts_2_u; + +/* Define the union csr_am_curr_wr_txid_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_txid_sts_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_txid_sts_0_u; + +/* Define the union csr_am_curr_wr_txid_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_txid_sts_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_txid_sts_1_u; + +/* Define the union csr_am_curr_wr_txid_sts_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_txid_sts_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_txid_sts_2_u; + +/* Define the union csr_am_alarm_rresp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alarm_rresp_0 : 1; /* [0] */ + u32 alarm_rresp_1 : 1; /* [1] */ + u32 alarm_rresp_2 : 1; /* [2] */ + u32 alarm_rresp_3 : 1; /* [3] */ + u32 rsv_24 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_alarm_rresp_u; + +/* Define the union csr_am_alarm_bresp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alarm_bresp_0 : 1; /* [0] */ + u32 alarm_bresp_1 : 1; /* [1] */ + u32 alarm_bresp_2 : 1; /* [2] */ + u32 alarm_bresp_3 : 1; /* [3] */ + u32 rsv_25 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_alarm_bresp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_am_ctrl_global_u am_ctrl_global; /* 0 */ + volatile csr_am_ctrl_latency_sel_u am_ctrl_latency_sel; /* 4 */ + volatile csr_am_ctrl_ptl_wr_u am_ctrl_ptl_wr; /* 8 */ + volatile csr_am_cfg_max_trans_u am_cfg_max_trans; /* 10 */ + volatile csr_am_cfg_single_port_max_trans_u am_cfg_single_port_max_trans; /* 14 */ + volatile csr_am_cfg_port_rd_en_u am_cfg_port_rd_en; /* 18 */ + volatile csr_am_cfg_port_wr_en_u am_cfg_port_wr_en; /* 1C */ + volatile csr_am_curr_aw_w_fifo_sts_u am_curr_aw_w_fifo_sts; /* 20 */ + volatile csr_am_curr_port_sts_u am_curr_port_sts; /* 100 */ + volatile csr_am_rob_ecc_int_sts_u am_rob_ecc_int_sts; /* 104 */ + volatile csr_am_rob_ecc_int_mask_u am_rob_ecc_int_mask; /* 108 */ + volatile csr_am_rob_ecc_err_addr_u am_rob_ecc_err_addr; /* 10C */ + volatile csr_am_curr_max_rd_latency_u am_curr_max_rd_latency; /* 110 */ + volatile csr_am_curr_ava_rd_latency_u am_curr_ava_rd_latency; /* 114 */ + volatile csr_am_curr_rd_latency_u am_curr_rd_latency; /* 118 */ + volatile csr_am_curr_max_wr_latency_u am_curr_max_wr_latency; /* 130 */ + volatile csr_am_curr_ava_wr_latency_u am_curr_ava_wr_latency; /* 134 */ + volatile csr_am_curr_wr_latency_u am_curr_wr_latency; /* 138 */ + volatile csr_am_curr_trans_return_u am_curr_trans_return; /* 150 */ + volatile csr_am_curr_rd_max_txid_u am_curr_rd_max_txid; /* 154 */ + volatile csr_am_curr_wr_max_txid_u am_curr_wr_max_txid; /* 158 */ + volatile csr_am_curr_rd_txid_sts_0_u am_curr_rd_txid_sts_0; /* 160 */ + volatile csr_am_curr_rd_txid_sts_1_u am_curr_rd_txid_sts_1; /* 164 */ + volatile csr_am_curr_rd_txid_sts_2_u am_curr_rd_txid_sts_2; /* 168 */ + volatile csr_am_curr_wr_txid_sts_0_u am_curr_wr_txid_sts_0; /* 170 */ + volatile csr_am_curr_wr_txid_sts_1_u am_curr_wr_txid_sts_1; /* 174 */ + volatile csr_am_curr_wr_txid_sts_2_u am_curr_wr_txid_sts_2; /* 178 */ + volatile csr_am_alarm_rresp_u am_alarm_rresp; /* 180 */ + volatile csr_am_alarm_bresp_u am_alarm_bresp; /* 184 */ +} S_am_ooo_cfg_REGS_TYPE; + +/* Declare the struct pointor of the module am_ooo_cfg */ +extern volatile S_am_ooo_cfg_REGS_TYPE *gopam_ooo_cfgAllReg; + +/* Declare the functions that set the member value */ +int iSetAM_CTRL_GLOBAL_ctrl_shutdown_req(unsigned int uctrl_shutdown_req); +int iSetAM_CTRL_GLOBAL_ctrl_lat_stat_rd_en(unsigned int uctrl_lat_stat_rd_en); +int iSetAM_CTRL_GLOBAL_ctrl_lat_stat_wr_en(unsigned int uctrl_lat_stat_wr_en); +int iSetAM_CTRL_GLOBAL_rd_rate_limit(unsigned int urd_rate_limit); +int iSetAM_CTRL_GLOBAL_wr_rate_limit(unsigned int uwr_rate_limit); +int iSetAM_CTRL_GLOBAL_ctrl_en_rd_256byte_global(unsigned int uctrl_en_rd_256byte_global); +int iSetAM_CTRL_GLOBAL_ctrl_en_wr_256byte_global(unsigned int uctrl_en_wr_256byte_global); +int iSetAM_CTRL_GLOBAL_ctrl_clkgt_en(unsigned int uctrl_clkgt_en); +int iSetAM_CTRL_LATENCY_SEL_ctrl_lat_rd_port_sel(unsigned int uctrl_lat_rd_port_sel); +int iSetAM_CTRL_LATENCY_SEL_ctrl_lat_wr_port_sel(unsigned int uctrl_lat_wr_port_sel); +int iSetAM_CTRL_PTL_WR_ctrl_ptl_wr_64byte(unsigned int uctrl_ptl_wr_64byte); +int iSetAM_CFG_MAX_TRANS_cfg_max_rd_trans(unsigned int ucfg_max_rd_trans); +int iSetAM_CFG_MAX_TRANS_cfg_max_wr_trans(unsigned int ucfg_max_wr_trans); +int iSetAM_CFG_SINGLE_PORT_MAX_TRANS_cfg_max_sgl_port_rd_trans(unsigned int ucfg_max_sgl_port_rd_trans); +int iSetAM_CFG_SINGLE_PORT_MAX_TRANS_cfg_max_sgl_port_wr_trans(unsigned int ucfg_max_sgl_port_wr_trans); +int iSetAM_CFG_PORT_RD_EN_cfg_port_rd_en(unsigned int ucfg_port_rd_en); +int iSetAM_CFG_PORT_WR_EN_cfg_port_wr_en(unsigned int ucfg_port_wr_en); +int iSetAM_CURR_AW_W_FIFO_STS_curr_w_tx_port(unsigned int ucurr_w_tx_port); +int iSetAM_CURR_AW_W_FIFO_STS_curr_w_tx_stock(unsigned int ucurr_w_tx_stock); +int iSetAM_CURR_AW_W_FIFO_STS_curr_w_tx_idle(unsigned int ucurr_w_tx_idle); +int iSetAM_CURR_PORT_STS_curr_rd_port_sts(unsigned int ucurr_rd_port_sts); +int iSetAM_CURR_PORT_STS_curr_wr_port_sts(unsigned int ucurr_wr_port_sts); +int iSetAM_ROB_ECC_INT_STS_rob_ecc_err_onebit(unsigned int urob_ecc_err_onebit); +int iSetAM_ROB_ECC_INT_STS_rob_ecc_err_multpl(unsigned int urob_ecc_err_multpl); +int iSetAM_ROB_ECC_INT_MASK_cfg_ecc_err_detect_int_msk(unsigned int ucfg_ecc_err_detect_int_msk); +int iSetAM_ROB_ECC_INT_MASK_cfg_ecc_err_multpl_int_msk(unsigned int ucfg_ecc_err_multpl_int_msk); +int iSetAM_ROB_ECC_ERR_ADDR_rob_ecc_onebit_err_addr(unsigned int urob_ecc_onebit_err_addr); +int iSetAM_ROB_ECC_ERR_ADDR_rob_ecc_multpl_err_addr(unsigned int urob_ecc_multpl_err_addr); +int iSetAM_CURR_MAX_RD_LATENCY_curr_max_rd_latency(unsigned int ucurr_max_rd_latency); +int iSetAM_CURR_AVA_RD_LATENCY_curr_ava_rd_latency(unsigned int ucurr_ava_rd_latency); +int iSetAM_CURR_RD_LATENCY_curr_rd_latency(unsigned int ucurr_rd_latency); +int iSetAM_CURR_MAX_WR_LATENCY_curr_max_wr_latency(unsigned int ucurr_max_wr_latency); +int iSetAM_CURR_AVA_WR_LATENCY_curr_ava_wr_latency(unsigned int ucurr_ava_wr_latency); +int iSetAM_CURR_WR_LATENCY_curr_wr_latency(unsigned int ucurr_wr_latency); +int iSetAM_CURR_TRANS_RETURN_curr_all_rd_returned(unsigned int ucurr_all_rd_returned); +int iSetAM_CURR_TRANS_RETURN_curr_all_wr_returned(unsigned int ucurr_all_wr_returned); +int iSetAM_CURR_RD_MAX_TXID_curr_rd_max_txid(unsigned int ucurr_rd_max_txid); +int iSetAM_CURR_WR_MAX_TXID_curr_wr_max_txid(unsigned int ucurr_wr_max_txid); +int iSetAM_CURR_RD_TXID_STS_0_curr_rd_txid_sts_0(unsigned int ucurr_rd_txid_sts_0); +int iSetAM_CURR_RD_TXID_STS_1_curr_rd_txid_sts_1(unsigned int ucurr_rd_txid_sts_1); +int iSetAM_CURR_RD_TXID_STS_2_curr_rd_txid_sts_2(unsigned int ucurr_rd_txid_sts_2); +int iSetAM_CURR_WR_TXID_STS_0_curr_wr_txid_sts_0(unsigned int ucurr_wr_txid_sts_0); +int iSetAM_CURR_WR_TXID_STS_1_curr_wr_txid_sts_1(unsigned int ucurr_wr_txid_sts_1); +int iSetAM_CURR_WR_TXID_STS_2_curr_wr_txid_sts_2(unsigned int ucurr_wr_txid_sts_2); +int iSetAM_ALARM_RRESP_alarm_rresp_0(unsigned int ualarm_rresp_0); +int iSetAM_ALARM_RRESP_alarm_rresp_1(unsigned int ualarm_rresp_1); +int iSetAM_ALARM_RRESP_alarm_rresp_2(unsigned int ualarm_rresp_2); +int iSetAM_ALARM_RRESP_alarm_rresp_3(unsigned int ualarm_rresp_3); +int iSetAM_ALARM_BRESP_alarm_bresp_0(unsigned int ualarm_bresp_0); +int iSetAM_ALARM_BRESP_alarm_bresp_1(unsigned int ualarm_bresp_1); +int iSetAM_ALARM_BRESP_alarm_bresp_2(unsigned int ualarm_bresp_2); +int iSetAM_ALARM_BRESP_alarm_bresp_3(unsigned int ualarm_bresp_3); + +/* Define the union csr_cryptorx_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptorx_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_version_u; + +/* Define the union csr_cryptorx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 crx_enable : 1; /* [27] */ + u32 crx_int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_int_vector_u; + +/* Define the union csr_cryptorx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_int_data : 4; /* [3:0] */ + u32 rsv_2 : 12; /* [15:4] */ + u32 crx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_int_u; + +/* Define the union csr_cryptorx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_int_en : 4; /* [3:0] */ + u32 rsv_3 : 12; /* [15:4] */ + u32 crx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_int_en_u; + +/* Define the union csr_crx_lp_top_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lp_top_err : 1; /* [0] */ + u32 crx_lp_top_err_inj : 1; /* [1] */ + u32 crx_lp_top_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_lp_top_err_u; + +/* Define the union csr_crx_lp_gcm_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lp_gcm_err : 1; /* [0] */ + u32 crx_lp_gcm_err_inj : 1; /* [1] */ + u32 crx_lp_gcm_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_lp_gcm_err_u; + +/* Define the union csr_crx_lp_cbc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lp_cbc_err : 1; /* [0] */ + u32 crx_lp_cbc_err_inj : 1; /* [1] */ + u32 crx_lp_cbc_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_lp_cbc_err_u; + +/* Define the union csr_crx_xts_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_xts_err : 1; /* [0] */ + u32 crx_xts_err_inj : 1; /* [1] */ + u32 crx_xts_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_xts_err_u; + +/* Define the union csr_crx_tmout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_tmout_cfg : 24; /* [23:0] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_tmout_cfg_u; + +/* Define the union csr_ipsec_rx_crg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ipsec_rx : 1; /* [0] */ + u32 icg_en_ipsec_csr_rx : 1; /* [1] */ + u32 icg_en_cbc_rx : 1; /* [2] */ + u32 icg_en_gcm_rx : 1; /* [3] */ + u32 rsv_5 : 4; /* [7:4] */ + u32 srst_req_ipsec_rx : 1; /* [8] */ + u32 srst_req_ipsec_csr_rx : 1; /* [9] */ + u32 srst_req_cbc_rx : 1; /* [10] */ + u32 srst_req_gcm_rx : 1; /* [11] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_rx_crg_cfg_u; + +/* Define the union csr_crx_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_mem_init : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_mem_init_u; + +/* Define the union csr_crx_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_mem_init_done : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_mem_init_done_u; + +/* Define the union csr_crx_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_mem_power_mode : 6; /* [5:0] */ + u32 crx_tp_ram_tmod : 8; /* [13:6] */ + u32 crx_sp_ram_tmod : 7; /* [20:14] */ + u32 crx_ecc_bypass : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_mem_ctrl_u; + +/* Define the union csr_crx_reg_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 snap_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_reg_cnt_clr_ce_u; + +/* Define the union csr_crx_chx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_gcm_ch_cfg : 5; /* [4:0] */ + u32 rsv_11 : 3; /* [7:5] */ + u32 crx_cbc_ch_cfg : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 crx_xts_ch_cfg : 5; /* [20:16] */ + u32 rsv_13 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_chx_cfg_u; + +/* Define the union csr_crx_credit_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_credit_o_cfg : 6; /* [5:0] */ + u32 rsv_14 : 2; /* [7:6] */ + u32 crx_lpch_cmd_credit_o_cfg : 5; /* [12:8] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_credit_o_cfg_u; + +/* Define the union csr_crx_credit2_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lpch_credit2_o_sum : 7; /* [6:0] */ + u32 rsv_16 : 1; /* [7] */ + u32 crx_gcm_credit2_o_cfg : 7; /* [14:8] */ + u32 rsv_17 : 1; /* [15] */ + u32 crx_cbc_credit2_o_cfg : 7; /* [22:16] */ + u32 rsv_18 : 1; /* [23] */ + u32 crx_prealc_pkt_credit2 : 4; /* [27:24] */ + u32 rsv_19 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_credit2_o_cfg_u; + +/* Define the union csr_crx_ctrl_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ctrl_rsv : 24; /* [23:0] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_ctrl_rsv_u; + +/* Define the union csr_crx_stat_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_stat_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_stat_rsv_u; + +/* Define the union csr_crx_ept_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ept : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_ept_u; + +/* Define the union csr_crx_full_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_full : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_full_u; + +/* Define the union csr_crx_dft_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_0_u; + +/* Define the union csr_crx_dft_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_1_u; + +/* Define the union csr_crx_dft_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_2_u; + +/* Define the union csr_crx_dft_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_3_u; + +/* Define the union csr_crx_dft_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_4 : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_4_u; + +/* Define the union csr_crx_err1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ecc_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_err1_cnt_u; + +/* Define the union csr_crx_ecc_err2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ecc_err2_addr : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_ecc_err2_addr_u; + +/* Define the union csr_crx_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_top_int_en : 8; /* [7:0] */ + u32 rsv_23 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_top_int_en_u; + +/* Define the union csr_crx_top_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_top_alm : 8; /* [7:0] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_top_alm_u; + +/* Define the union csr_crx_credit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_gcm_credit_i_err : 1; /* [0] */ + u32 crx_cbc_credit_i_err : 1; /* [1] */ + u32 crx_xts_credit_i_err : 1; /* [2] */ + u32 rsv_25 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_credit_err_u; + +/* Define the union csr_crx_inn_credit_i_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_gcm_inn_credit_i_err : 1; /* [0] */ + u32 crx_cbc_inn_credit_i_err : 1; /* [1] */ + u32 crx_xts_inn_credit_i_err : 1; /* [2] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_inn_credit_i_err_u; + +/* Define the union csr_crx_pkt_cnt_i_pre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cnt_i_pre : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cnt_i_pre_u; + +/* Define the union csr_crx_chk_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_chk_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_chk_err_cnt_u; + +/* Define the union csr_crx_tfc_pad_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_tfc_pad_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_tfc_pad_err_cnt_u; + +/* Define the union csr_crx_other_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_other_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_other_err_cnt_u; + +/* Define the union csr_crx_pkt_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cnt_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cnt_i_u; + +/* Define the union csr_crx_pkt_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cnt_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cnt_o_u; + +/* Define the union csr_cryptorx_if_i_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptorx_if_i_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_if_i_cnt_u; + +/* Define the union csr_crx_bdsplit_len_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_bdsplit_len_i : 12; /* [11:0] */ + u32 rsv_29 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_bdsplit_len_i_u; + +/* Define the union csr_crx_bdsplit_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_bdsplit_len_o : 12; /* [11:0] */ + u32 rsv_30 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_bdsplit_len_o_u; + +/* Define the union csr_crx_pkt_cmb_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cmb_len_o : 12; /* [11:0] */ + u32 rsv_31 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cmb_len_o_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cryptorx_version_u cryptorx_version; /* 0 */ + volatile csr_cryptorx_int_vector_u cryptorx_int_vector; /* 60 */ + volatile csr_cryptorx_int_u cryptorx_int; /* 64 */ + volatile csr_cryptorx_int_en_u cryptorx_int_en; /* 68 */ + volatile csr_crx_lp_top_err_u crx_lp_top_err; /* 6C */ + volatile csr_crx_lp_gcm_err_u crx_lp_gcm_err; /* 70 */ + volatile csr_crx_lp_cbc_err_u crx_lp_cbc_err; /* 74 */ + volatile csr_crx_xts_err_u crx_xts_err; /* 78 */ + volatile csr_crx_tmout_cfg_u crx_tmout_cfg; /* 80 */ + volatile csr_ipsec_rx_crg_cfg_u ipsec_rx_crg_cfg; /* 84 */ + volatile csr_crx_mem_init_u crx_mem_init; /* 100 */ + volatile csr_crx_mem_init_done_u crx_mem_init_done; /* 104 */ + volatile csr_crx_mem_ctrl_u crx_mem_ctrl; /* 108 */ + volatile csr_crx_reg_cnt_clr_ce_u crx_reg_cnt_clr_ce; /* 10C */ + volatile csr_crx_chx_cfg_u crx_chx_cfg; /* 120 */ + volatile csr_crx_credit_o_cfg_u crx_credit_o_cfg; /* 128 */ + volatile csr_crx_credit2_o_cfg_u crx_credit2_o_cfg; /* 12C */ + volatile csr_crx_ctrl_rsv_u crx_ctrl_rsv; /* 130 */ + volatile csr_crx_stat_rsv_u crx_stat_rsv; /* 134 */ + volatile csr_crx_ept_u crx_ept; /* 138 */ + volatile csr_crx_full_u crx_full; /* 13C */ + volatile csr_crx_dft_mem_ctrl_0_u crx_dft_mem_ctrl_0; /* 150 */ + volatile csr_crx_dft_mem_ctrl_1_u crx_dft_mem_ctrl_1; /* 154 */ + volatile csr_crx_dft_mem_ctrl_2_u crx_dft_mem_ctrl_2; /* 158 */ + volatile csr_crx_dft_mem_ctrl_3_u crx_dft_mem_ctrl_3; /* 15C */ + volatile csr_crx_dft_mem_ctrl_4_u crx_dft_mem_ctrl_4; /* 160 */ + volatile csr_crx_err1_cnt_u crx_err1_cnt; /* 170 */ + volatile csr_crx_ecc_err2_addr_u crx_ecc_err2_addr; /* 174 */ + volatile csr_crx_top_int_en_u crx_top_int_en; /* 178 */ + volatile csr_crx_top_alm_u crx_top_alm; /* 17C */ + volatile csr_crx_credit_err_u crx_credit_err; /* 200 */ + volatile csr_crx_inn_credit_i_err_u crx_inn_credit_i_err; /* 204 */ + volatile csr_crx_pkt_cnt_i_pre_u crx_pkt_cnt_i_pre[3]; /* 310 */ + volatile csr_crx_chk_err_cnt_u crx_chk_err_cnt; /* 320 */ + volatile csr_crx_tfc_pad_err_cnt_u crx_tfc_pad_err_cnt; /* 324 */ + volatile csr_crx_other_err_cnt_u crx_other_err_cnt; /* 328 */ + volatile csr_crx_pkt_cnt_i_u crx_pkt_cnt_i[3]; /* 210 */ + volatile csr_crx_pkt_cnt_o_u crx_pkt_cnt_o[3]; /* 220 */ + volatile csr_cryptorx_if_i_cnt_u cryptorx_if_i_cnt[3]; /* 280 */ + volatile csr_crx_bdsplit_len_i_u crx_bdsplit_len_i[3]; /* 2A0 */ + volatile csr_crx_bdsplit_len_o_u crx_bdsplit_len_o[3]; /* 2C0 */ + volatile csr_crx_pkt_cmb_len_o_u crx_pkt_cmb_len_o[3]; /* 2E0 */ +} S_cryptorx_inout_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cryptorx_inout_csr */ +extern volatile S_cryptorx_inout_csr_REGS_TYPE *gopcryptorx_inout_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCRYPTORX_VERSION_cryptorx_version(unsigned int ucryptorx_version); +int iSetCRYPTORX_INT_VECTOR_crx_cpi_int_index(unsigned int ucrx_cpi_int_index); +int iSetCRYPTORX_INT_VECTOR_crx_enable(unsigned int ucrx_enable); +int iSetCRYPTORX_INT_VECTOR_crx_int_issue(unsigned int ucrx_int_issue); +int iSetCRYPTORX_INT_crx_int_data(unsigned int ucrx_int_data); +int iSetCRYPTORX_INT_crx_program_csr_id_ro(unsigned int ucrx_program_csr_id_ro); +int iSetCRYPTORX_INT_EN_crx_int_en(unsigned int ucrx_int_en); +int iSetCRYPTORX_INT_EN_crx_program_csr_id(unsigned int ucrx_program_csr_id); +int iSetCRX_LP_TOP_ERR_crx_lp_top_err(unsigned int ucrx_lp_top_err); +int iSetCRX_LP_TOP_ERR_crx_lp_top_err_inj(unsigned int ucrx_lp_top_err_inj); +int iSetCRX_LP_TOP_ERR_crx_lp_top_err_sticky(unsigned int ucrx_lp_top_err_sticky); +int iSetCRX_LP_GCM_ERR_crx_lp_gcm_err(unsigned int ucrx_lp_gcm_err); +int iSetCRX_LP_GCM_ERR_crx_lp_gcm_err_inj(unsigned int ucrx_lp_gcm_err_inj); +int iSetCRX_LP_GCM_ERR_crx_lp_gcm_err_sticky(unsigned int ucrx_lp_gcm_err_sticky); +int iSetCRX_LP_CBC_ERR_crx_lp_cbc_err(unsigned int ucrx_lp_cbc_err); +int iSetCRX_LP_CBC_ERR_crx_lp_cbc_err_inj(unsigned int ucrx_lp_cbc_err_inj); +int iSetCRX_LP_CBC_ERR_crx_lp_cbc_err_sticky(unsigned int ucrx_lp_cbc_err_sticky); +int iSetCRX_XTS_ERR_crx_xts_err(unsigned int ucrx_xts_err); +int iSetCRX_XTS_ERR_crx_xts_err_inj(unsigned int ucrx_xts_err_inj); +int iSetCRX_XTS_ERR_crx_xts_err_sticky(unsigned int ucrx_xts_err_sticky); +int iSetCRX_TMOUT_CFG_crx_tmout_cfg(unsigned int ucrx_tmout_cfg); +int iSetIPSEC_RX_CRG_CFG_icg_en_ipsec_rx(unsigned int uicg_en_ipsec_rx); +int iSetIPSEC_RX_CRG_CFG_icg_en_ipsec_csr_rx(unsigned int uicg_en_ipsec_csr_rx); +int iSetIPSEC_RX_CRG_CFG_icg_en_cbc_rx(unsigned int uicg_en_cbc_rx); +int iSetIPSEC_RX_CRG_CFG_icg_en_gcm_rx(unsigned int uicg_en_gcm_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_ipsec_rx(unsigned int usrst_req_ipsec_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_ipsec_csr_rx(unsigned int usrst_req_ipsec_csr_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_cbc_rx(unsigned int usrst_req_cbc_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_gcm_rx(unsigned int usrst_req_gcm_rx); +int iSetCRX_MEM_INIT_crx_mem_init(unsigned int ucrx_mem_init); +int iSetCRX_MEM_INIT_DONE_crx_mem_init_done(unsigned int ucrx_mem_init_done); +int iSetCRX_MEM_CTRL_crx_mem_power_mode(unsigned int ucrx_mem_power_mode); +int iSetCRX_MEM_CTRL_crx_tp_ram_tmod(unsigned int ucrx_tp_ram_tmod); +int iSetCRX_MEM_CTRL_crx_sp_ram_tmod(unsigned int ucrx_sp_ram_tmod); +int iSetCRX_MEM_CTRL_crx_ecc_bypass(unsigned int ucrx_ecc_bypass); +int iSetCRX_REG_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce); +int iSetCRX_REG_CNT_CLR_CE_snap_en(unsigned int usnap_en); +int iSetCRX_CHX_CFG_crx_gcm_ch_cfg(unsigned int ucrx_gcm_ch_cfg); +int iSetCRX_CHX_CFG_crx_cbc_ch_cfg(unsigned int ucrx_cbc_ch_cfg); +int iSetCRX_CHX_CFG_crx_xts_ch_cfg(unsigned int ucrx_xts_ch_cfg); +int iSetCRX_CREDIT_O_CFG_crx_pkt_credit_o_cfg(unsigned int ucrx_pkt_credit_o_cfg); +int iSetCRX_CREDIT_O_CFG_crx_lpch_cmd_credit_o_cfg(unsigned int ucrx_lpch_cmd_credit_o_cfg); +int iSetCRX_CREDIT2_O_CFG_crx_lpch_credit2_o_sum(unsigned int ucrx_lpch_credit2_o_sum); +int iSetCRX_CREDIT2_O_CFG_crx_gcm_credit2_o_cfg(unsigned int ucrx_gcm_credit2_o_cfg); +int iSetCRX_CREDIT2_O_CFG_crx_cbc_credit2_o_cfg(unsigned int ucrx_cbc_credit2_o_cfg); +int iSetCRX_CREDIT2_O_CFG_crx_prealc_pkt_credit2(unsigned int ucrx_prealc_pkt_credit2); +int iSetCRX_CTRL_RSV_crx_ctrl_rsv(unsigned int ucrx_ctrl_rsv); +int iSetCRX_STAT_RSV_crx_stat_rsv(unsigned int ucrx_stat_rsv); +int iSetCRX_EPT_crx_ept(unsigned int ucrx_ept); +int iSetCRX_FULL_crx_full(unsigned int ucrx_full); +int iSetCRX_DFT_MEM_CTRL_0_crx_dft_mem_ctrl_0(unsigned int ucrx_dft_mem_ctrl_0); +int iSetCRX_DFT_MEM_CTRL_1_crx_dft_mem_ctrl_1(unsigned int ucrx_dft_mem_ctrl_1); +int iSetCRX_DFT_MEM_CTRL_2_crx_dft_mem_ctrl_2(unsigned int ucrx_dft_mem_ctrl_2); +int iSetCRX_DFT_MEM_CTRL_3_crx_dft_mem_ctrl_3(unsigned int ucrx_dft_mem_ctrl_3); +int iSetCRX_DFT_MEM_CTRL_4_crx_dft_mem_ctrl_4(unsigned int ucrx_dft_mem_ctrl_4); +int iSetCRX_ERR1_CNT_crx_ecc_err1_cnt(unsigned int ucrx_ecc_err1_cnt); +int iSetCRX_ECC_ERR2_ADDR_crx_ecc_err2_addr(unsigned int ucrx_ecc_err2_addr); +int iSetCRX_TOP_INT_EN_crx_top_int_en(unsigned int ucrx_top_int_en); +int iSetCRX_TOP_ALM_crx_top_alm(unsigned int ucrx_top_alm); +int iSetCRX_CREDIT_ERR_crx_gcm_credit_i_err(unsigned int ucrx_gcm_credit_i_err); +int iSetCRX_CREDIT_ERR_crx_cbc_credit_i_err(unsigned int ucrx_cbc_credit_i_err); +int iSetCRX_CREDIT_ERR_crx_xts_credit_i_err(unsigned int ucrx_xts_credit_i_err); +int iSetCRX_INN_CREDIT_I_ERR_crx_gcm_inn_credit_i_err(unsigned int ucrx_gcm_inn_credit_i_err); +int iSetCRX_INN_CREDIT_I_ERR_crx_cbc_inn_credit_i_err(unsigned int ucrx_cbc_inn_credit_i_err); +int iSetCRX_INN_CREDIT_I_ERR_crx_xts_inn_credit_i_err(unsigned int ucrx_xts_inn_credit_i_err); +int iSetCRX_PKT_CNT_I_PRE_crx_pkt_cnt_i_pre(unsigned int ucrx_pkt_cnt_i_pre); +int iSetCRX_CHK_ERR_CNT_crx_chk_err_cnt(unsigned int ucrx_chk_err_cnt); +int iSetCRX_TFC_PAD_ERR_CNT_crx_tfc_pad_err_cnt(unsigned int ucrx_tfc_pad_err_cnt); +int iSetCRX_OTHER_ERR_CNT_crx_other_err_cnt(unsigned int ucrx_other_err_cnt); +int iSetCRX_PKT_CNT_I_crx_pkt_cnt_i(unsigned int ucrx_pkt_cnt_i); +int iSetCRX_PKT_CNT_O_crx_pkt_cnt_o(unsigned int ucrx_pkt_cnt_o); +int iSetCRYPTORX_IF_I_CNT_cryptorx_if_i_cnt(unsigned int ucryptorx_if_i_cnt); +int iSetCRX_BDSPLIT_LEN_I_crx_bdsplit_len_i(unsigned int ucrx_bdsplit_len_i); +int iSetCRX_BDSPLIT_LEN_O_crx_bdsplit_len_o(unsigned int ucrx_bdsplit_len_o); +int iSetCRX_PKT_CMB_LEN_O_crx_pkt_cmb_len_o(unsigned int ucrx_pkt_cmb_len_o); + +/* Define the union csr_ctx_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_version_u; + +/* Define the union csr_ctx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 ctx_enable : 1; /* [27] */ + u32 ctx_int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_int_vector_u; + +/* Define the union csr_ctx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_int_data : 5; /* [4:0] */ + u32 rsv_2 : 11; /* [15:5] */ + u32 ctx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_int_u; + +/* Define the union csr_ctx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_int_en : 5; /* [4:0] */ + u32 rsv_3 : 11; /* [15:5] */ + u32 ctx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_int_en_u; + +/* Define the union csr_ctx_top_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_top_err : 1; /* [0] */ + u32 ctx_top_err_inj : 1; /* [1] */ + u32 ctx_top_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_top_err_u; + +/* Define the union csr_ctx_lp_gcm_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_gcm_err : 1; /* [0] */ + u32 ctx_lp_gcm_err_inj : 1; /* [1] */ + u32 ctx_lp_gcm_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_gcm_err_u; + +/* Define the union csr_ctx_lp_cbc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_cbc_err : 1; /* [0] */ + u32 ctx_lp_cbc_err_inj : 1; /* [1] */ + u32 ctx_lp_cbc_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_cbc_err_u; + +/* Define the union csr_ctx_ec_xts_ec_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_xts_ec_err : 1; /* [0] */ + u32 ctx_ec_xts_ec_err_inj : 1; /* [1] */ + u32 ctx_ec_xts_ec_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_xts_ec_err_u; + +/* Define the union csr_ctx_ec_xts_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_xts_err : 1; /* [0] */ + u32 ctx_ec_xts_err_inj : 1; /* [1] */ + u32 ctx_ec_xts_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_xts_err_u; + +/* Define the union csr_ctx_tmout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_tmout_cfg : 24; /* [23:0] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_tmout_cfg_u; + +/* Define the union csr_ipsec_tx_crg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ipsec_tx : 1; /* [0] */ + u32 icg_en_ipsec_csr_tx : 1; /* [1] */ + u32 icg_en_cbc_tx : 1; /* [2] */ + u32 icg_en_gcm_tx : 1; /* [3] */ + u32 rsv_5 : 4; /* [7:4] */ + u32 srst_req_ipsec_tx : 1; /* [8] */ + u32 srst_req_ipsec_csr_tx : 1; /* [9] */ + u32 srst_req_cbc_tx : 1; /* [10] */ + u32 srst_req_gcm_tx : 1; /* [11] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_tx_crg_cfg_u; + +/* Define the union csr_ctx_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_mem_init : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_mem_init_u; + +/* Define the union csr_ctx_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_mem_init_done : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_mem_init_done_u; + +/* Define the union csr_ctx_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_mem_power_mode : 6; /* [5:0] */ + u32 ctx_tp_ram_tmod : 8; /* [13:6] */ + u32 ctx_sp_ram_tmod : 7; /* [20:14] */ + u32 ctx_ecc_bypass : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_mem_ctrl_u; + +/* Define the union csr_ctx_reg_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 snap_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_reg_cnt_clr_ce_u; + +/* Define the union csr_ctx_lp_chx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_gcm_ch_cfg : 5; /* [4:0] */ + u32 rsv_11 : 3; /* [7:5] */ + u32 ctx_cbc_ch_cfg : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 ctx_rsa_ch_cfg : 5; /* [20:16] */ + u32 rsv_13 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_chx_cfg_u; + +/* Define the union csr_ctx_ec_chx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_xts_ec_ch_cfg : 5; /* [4:0] */ + u32 rsv_14 : 3; /* [7:5] */ + u32 ctx_xts_ch_cfg : 5; /* [12:8] */ + u32 rsv_15 : 3; /* [15:13] */ + u32 ctx_ec_ch_cfg : 5; /* [20:16] */ + u32 rsv_16 : 3; /* [23:21] */ + u32 ctx_mhd_ch_cfg : 5; /* [28:24] */ + u32 rsv_17 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_chx_cfg_u; + +/* Define the union csr_ctx_necch_credit_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_necch_credit_o_cfg : 5; /* [4:0] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_necch_credit_o_cfg_u; + +/* Define the union csr_ctx_ecch_credit_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ecch_credit_o_cfg : 5; /* [4:0] */ + u32 rsv_19 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ecch_credit_o_cfg_u; + +/* Define the union csr_ctx_ctrl_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ctrl_rsv : 24; /* [23:0] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ctrl_rsv_u; + +/* Define the union csr_ctx_stat_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_stat_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_stat_rsv_u; + +/* Define the union csr_ctx_lp_ept_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_ept : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_ept_u; + +/* Define the union csr_ctx_lp_full_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_full : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_full_u; + +/* Define the union csr_ctx_ec_ept_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_ept : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_ept_u; + +/* Define the union csr_ctx_ec_full_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_full : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_full_u; + +/* Define the union csr_ctx_dft_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_0_u; + +/* Define the union csr_ctx_dft_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_1_u; + +/* Define the union csr_ctx_dft_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_2_u; + +/* Define the union csr_ctx_dft_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_3_u; + +/* Define the union csr_ctx_dft_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_4 : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_4_u; + +/* Define the union csr_ctx_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_top_int_en : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_top_int_en_u; + +/* Define the union csr_ctx_top_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_top_alm : 8; /* [7:0] */ + u32 rsv_23 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_top_alm_u; + +/* Define the union csr_ctx_credit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_gcm_credit_i_err : 1; /* [0] */ + u32 ctx_cbc_credit_i_err : 1; /* [1] */ + u32 ctx_rsa_credit_i_err : 1; /* [2] */ + u32 ctx_xts_ec_credit_i_err : 1; /* [3] */ + u32 ctx_xts_credit_i_err : 1; /* [4] */ + u32 ctx_ec_credit_i_err : 1; /* [5] */ + u32 ctx_mhd_credit_i_err : 1; /* [6] */ + u32 ctx_byp_credit_i_err : 1; /* [7] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_credit_err_u; + +/* Define the union csr_ctx_inn_credit_i_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_gcm_inn_credit_i_err : 1; /* [0] */ + u32 ctx_cbc_inn_credit_i_err : 1; /* [1] */ + u32 ctx_rsa_inn_credit_i_err : 1; /* [2] */ + u32 ctx_xts_ec_inn_credit_i_err : 1; /* [3] */ + u32 ctx_xts_inn_credit_i_err : 1; /* [4] */ + u32 rsv_25 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_inn_credit_i_err_u; + +/* Define the union csr_ctx_lp_pkt_cnt_i_pre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_pkt_cnt_i_pre : 8; /* [7:0] */ + u32 rsv_26 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_pkt_cnt_i_pre_u; + +/* Define the union csr_ctx_ec_pkt_cnt_i_pre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_pkt_cnt_i_pre : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_pkt_cnt_i_pre_u; + +/* Define the union csr_ctx_bd_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_bd_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_bd_err_cnt_u; + +/* Define the union csr_ctx_len_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_len_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_len_err_cnt_u; + +/* Define the union csr_ctx_lp_pkt_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_pkt_cnt_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_pkt_cnt_i_u; + +/* Define the union csr_ctx_ec_pkt_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_pkt_cnt_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_pkt_cnt_i_u; + +/* Define the union csr_ctx_lp_pkt_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_pkt_cnt_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_pkt_cnt_o_u; + +/* Define the union csr_ctx_ec_pkt_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_pkt_cnt_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_pkt_cnt_o_u; + +/* Define the union csr_cryptotx_if_i_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_if_i_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptotx_if_i_cnt_u; + +/* Define the union csr_ctx_bdsplit_len_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_bdsplit_len_i : 12; /* [11:0] */ + u32 rsv_29 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_bdsplit_len_i_u; + +/* Define the union csr_ctx_bdsplit_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_bdsplit_len_o : 12; /* [11:0] */ + u32 rsv_30 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_bdsplit_len_o_u; + +/* Define the union csr_ctx_pkt_cmb_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_pkt_cmb_len_o : 12; /* [11:0] */ + u32 rsv_31 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_pkt_cmb_len_o_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ctx_version_u ctx_version; /* 0 */ + volatile csr_ctx_int_vector_u ctx_int_vector; /* 60 */ + volatile csr_ctx_int_u ctx_int; /* 64 */ + volatile csr_ctx_int_en_u ctx_int_en; /* 68 */ + volatile csr_ctx_top_err_u ctx_top_err; /* 6C */ + volatile csr_ctx_lp_gcm_err_u ctx_lp_gcm_err; /* 70 */ + volatile csr_ctx_lp_cbc_err_u ctx_lp_cbc_err; /* 74 */ + volatile csr_ctx_ec_xts_ec_err_u ctx_ec_xts_ec_err; /* 78 */ + volatile csr_ctx_ec_xts_err_u ctx_ec_xts_err; /* 7C */ + volatile csr_ctx_tmout_cfg_u ctx_tmout_cfg; /* 80 */ + volatile csr_ipsec_tx_crg_cfg_u ipsec_tx_crg_cfg; /* 84 */ + volatile csr_ctx_mem_init_u ctx_mem_init; /* 100 */ + volatile csr_ctx_mem_init_done_u ctx_mem_init_done; /* 104 */ + volatile csr_ctx_mem_ctrl_u ctx_mem_ctrl; /* 108 */ + volatile csr_ctx_reg_cnt_clr_ce_u ctx_reg_cnt_clr_ce; /* 10C */ + volatile csr_ctx_lp_chx_cfg_u ctx_lp_chx_cfg; /* 120 */ + volatile csr_ctx_ec_chx_cfg_u ctx_ec_chx_cfg; /* 124 */ + volatile csr_ctx_necch_credit_o_cfg_u ctx_necch_credit_o_cfg; /* 128 */ + volatile csr_ctx_ecch_credit_o_cfg_u ctx_ecch_credit_o_cfg; /* 12C */ + volatile csr_ctx_ctrl_rsv_u ctx_ctrl_rsv; /* 130 */ + volatile csr_ctx_stat_rsv_u ctx_stat_rsv; /* 134 */ + volatile csr_ctx_lp_ept_u ctx_lp_ept; /* 140 */ + volatile csr_ctx_lp_full_u ctx_lp_full; /* 144 */ + volatile csr_ctx_ec_ept_u ctx_ec_ept; /* 148 */ + volatile csr_ctx_ec_full_u ctx_ec_full; /* 14C */ + volatile csr_ctx_dft_mem_ctrl_0_u ctx_dft_mem_ctrl_0; /* 150 */ + volatile csr_ctx_dft_mem_ctrl_1_u ctx_dft_mem_ctrl_1; /* 154 */ + volatile csr_ctx_dft_mem_ctrl_2_u ctx_dft_mem_ctrl_2; /* 158 */ + volatile csr_ctx_dft_mem_ctrl_3_u ctx_dft_mem_ctrl_3; /* 15C */ + volatile csr_ctx_dft_mem_ctrl_4_u ctx_dft_mem_ctrl_4; /* 160 */ + volatile csr_ctx_top_int_en_u ctx_top_int_en; /* 178 */ + volatile csr_ctx_top_alm_u ctx_top_alm; /* 17C */ + volatile csr_ctx_credit_err_u ctx_credit_err; /* 200 */ + volatile csr_ctx_inn_credit_i_err_u ctx_inn_credit_i_err; /* 204 */ + volatile csr_ctx_lp_pkt_cnt_i_pre_u ctx_lp_pkt_cnt_i_pre[3]; /* 310 */ + volatile csr_ctx_ec_pkt_cnt_i_pre_u ctx_ec_pkt_cnt_i_pre[5]; /* 320 */ + volatile csr_ctx_bd_err_cnt_u ctx_bd_err_cnt; /* 340 */ + volatile csr_ctx_len_err_cnt_u ctx_len_err_cnt; /* 344 */ + volatile csr_ctx_lp_pkt_cnt_i_u ctx_lp_pkt_cnt_i[3]; /* 210 */ + volatile csr_ctx_ec_pkt_cnt_i_u ctx_ec_pkt_cnt_i[5]; /* 220 */ + volatile csr_ctx_lp_pkt_cnt_o_u ctx_lp_pkt_cnt_o[3]; /* 240 */ + volatile csr_ctx_ec_pkt_cnt_o_u ctx_ec_pkt_cnt_o[5]; /* 260 */ + volatile csr_cryptotx_if_i_cnt_u cryptotx_if_i_cnt[5]; /* 280 */ + volatile csr_ctx_bdsplit_len_i_u ctx_bdsplit_len_i[5]; /* 2A0 */ + volatile csr_ctx_bdsplit_len_o_u ctx_bdsplit_len_o[5]; /* 2C0 */ + volatile csr_ctx_pkt_cmb_len_o_u ctx_pkt_cmb_len_o[5]; /* 2E0 */ +} S_cryptotx_inout_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cryptotx_inout_csr */ +extern volatile S_cryptotx_inout_csr_REGS_TYPE *gopcryptotx_inout_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCTX_VERSION_cryptotx_version(unsigned int ucryptotx_version); +int iSetCTX_INT_VECTOR_ctx_cpi_int_index(unsigned int uctx_cpi_int_index); +int iSetCTX_INT_VECTOR_ctx_enable(unsigned int uctx_enable); +int iSetCTX_INT_VECTOR_ctx_int_issue(unsigned int uctx_int_issue); +int iSetCTX_INT_ctx_int_data(unsigned int uctx_int_data); +int iSetCTX_INT_ctx_program_csr_id_ro(unsigned int uctx_program_csr_id_ro); +int iSetCTX_INT_EN_ctx_int_en(unsigned int uctx_int_en); +int iSetCTX_INT_EN_ctx_program_csr_id(unsigned int uctx_program_csr_id); +int iSetCTX_TOP_ERR_ctx_top_err(unsigned int uctx_top_err); +int iSetCTX_TOP_ERR_ctx_top_err_inj(unsigned int uctx_top_err_inj); +int iSetCTX_TOP_ERR_ctx_top_err_sticky(unsigned int uctx_top_err_sticky); +int iSetCTX_LP_GCM_ERR_ctx_lp_gcm_err(unsigned int uctx_lp_gcm_err); +int iSetCTX_LP_GCM_ERR_ctx_lp_gcm_err_inj(unsigned int uctx_lp_gcm_err_inj); +int iSetCTX_LP_GCM_ERR_ctx_lp_gcm_err_sticky(unsigned int uctx_lp_gcm_err_sticky); +int iSetCTX_LP_CBC_ERR_ctx_lp_cbc_err(unsigned int uctx_lp_cbc_err); +int iSetCTX_LP_CBC_ERR_ctx_lp_cbc_err_inj(unsigned int uctx_lp_cbc_err_inj); +int iSetCTX_LP_CBC_ERR_ctx_lp_cbc_err_sticky(unsigned int uctx_lp_cbc_err_sticky); +int iSetCTX_EC_XTS_EC_ERR_ctx_ec_xts_ec_err(unsigned int uctx_ec_xts_ec_err); +int iSetCTX_EC_XTS_EC_ERR_ctx_ec_xts_ec_err_inj(unsigned int uctx_ec_xts_ec_err_inj); +int iSetCTX_EC_XTS_EC_ERR_ctx_ec_xts_ec_err_sticky(unsigned int uctx_ec_xts_ec_err_sticky); +int iSetCTX_EC_XTS_ERR_ctx_ec_xts_err(unsigned int uctx_ec_xts_err); +int iSetCTX_EC_XTS_ERR_ctx_ec_xts_err_inj(unsigned int uctx_ec_xts_err_inj); +int iSetCTX_EC_XTS_ERR_ctx_ec_xts_err_sticky(unsigned int uctx_ec_xts_err_sticky); +int iSetCTX_TMOUT_CFG_ctx_tmout_cfg(unsigned int uctx_tmout_cfg); +int iSetIPSEC_TX_CRG_CFG_icg_en_ipsec_tx(unsigned int uicg_en_ipsec_tx); +int iSetIPSEC_TX_CRG_CFG_icg_en_ipsec_csr_tx(unsigned int uicg_en_ipsec_csr_tx); +int iSetIPSEC_TX_CRG_CFG_icg_en_cbc_tx(unsigned int uicg_en_cbc_tx); +int iSetIPSEC_TX_CRG_CFG_icg_en_gcm_tx(unsigned int uicg_en_gcm_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_ipsec_tx(unsigned int usrst_req_ipsec_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_ipsec_csr_tx(unsigned int usrst_req_ipsec_csr_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_cbc_tx(unsigned int usrst_req_cbc_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_gcm_tx(unsigned int usrst_req_gcm_tx); +int iSetCTX_MEM_INIT_ctx_mem_init(unsigned int uctx_mem_init); +int iSetCTX_MEM_INIT_DONE_ctx_mem_init_done(unsigned int uctx_mem_init_done); +int iSetCTX_MEM_CTRL_ctx_mem_power_mode(unsigned int uctx_mem_power_mode); +int iSetCTX_MEM_CTRL_ctx_tp_ram_tmod(unsigned int uctx_tp_ram_tmod); +int iSetCTX_MEM_CTRL_ctx_sp_ram_tmod(unsigned int uctx_sp_ram_tmod); +int iSetCTX_MEM_CTRL_ctx_ecc_bypass(unsigned int uctx_ecc_bypass); +int iSetCTX_REG_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce); +int iSetCTX_REG_CNT_CLR_CE_snap_en(unsigned int usnap_en); +int iSetCTX_LP_CHX_CFG_ctx_gcm_ch_cfg(unsigned int uctx_gcm_ch_cfg); +int iSetCTX_LP_CHX_CFG_ctx_cbc_ch_cfg(unsigned int uctx_cbc_ch_cfg); +int iSetCTX_LP_CHX_CFG_ctx_rsa_ch_cfg(unsigned int uctx_rsa_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_xts_ec_ch_cfg(unsigned int uctx_xts_ec_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_xts_ch_cfg(unsigned int uctx_xts_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_ec_ch_cfg(unsigned int uctx_ec_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_mhd_ch_cfg(unsigned int uctx_mhd_ch_cfg); +int iSetCTX_NECCH_CREDIT_O_CFG_ctx_necch_credit_o_cfg(unsigned int uctx_necch_credit_o_cfg); +int iSetCTX_ECCH_CREDIT_O_CFG_ctx_ecch_credit_o_cfg(unsigned int uctx_ecch_credit_o_cfg); +int iSetCTX_CTRL_RSV_ctx_ctrl_rsv(unsigned int uctx_ctrl_rsv); +int iSetCTX_STAT_RSV_ctx_stat_rsv(unsigned int uctx_stat_rsv); +int iSetCTX_LP_EPT_ctx_lp_ept(unsigned int uctx_lp_ept); +int iSetCTX_LP_FULL_ctx_lp_full(unsigned int uctx_lp_full); +int iSetCTX_EC_EPT_ctx_ec_ept(unsigned int uctx_ec_ept); +int iSetCTX_EC_FULL_ctx_ec_full(unsigned int uctx_ec_full); +int iSetCTX_DFT_MEM_CTRL_0_ctx_dft_mem_ctrl_0(unsigned int uctx_dft_mem_ctrl_0); +int iSetCTX_DFT_MEM_CTRL_1_ctx_dft_mem_ctrl_1(unsigned int uctx_dft_mem_ctrl_1); +int iSetCTX_DFT_MEM_CTRL_2_ctx_dft_mem_ctrl_2(unsigned int uctx_dft_mem_ctrl_2); +int iSetCTX_DFT_MEM_CTRL_3_ctx_dft_mem_ctrl_3(unsigned int uctx_dft_mem_ctrl_3); +int iSetCTX_DFT_MEM_CTRL_4_ctx_dft_mem_ctrl_4(unsigned int uctx_dft_mem_ctrl_4); +int iSetCTX_TOP_INT_EN_ctx_top_int_en(unsigned int uctx_top_int_en); +int iSetCTX_TOP_ALM_ctx_top_alm(unsigned int uctx_top_alm); +int iSetCTX_CREDIT_ERR_ctx_gcm_credit_i_err(unsigned int uctx_gcm_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_cbc_credit_i_err(unsigned int uctx_cbc_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_rsa_credit_i_err(unsigned int uctx_rsa_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_xts_ec_credit_i_err(unsigned int uctx_xts_ec_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_xts_credit_i_err(unsigned int uctx_xts_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_ec_credit_i_err(unsigned int uctx_ec_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_mhd_credit_i_err(unsigned int uctx_mhd_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_byp_credit_i_err(unsigned int uctx_byp_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_gcm_inn_credit_i_err(unsigned int uctx_gcm_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_cbc_inn_credit_i_err(unsigned int uctx_cbc_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_rsa_inn_credit_i_err(unsigned int uctx_rsa_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_xts_ec_inn_credit_i_err(unsigned int uctx_xts_ec_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_xts_inn_credit_i_err(unsigned int uctx_xts_inn_credit_i_err); +int iSetCTX_LP_PKT_CNT_I_PRE_ctx_lp_pkt_cnt_i_pre(unsigned int uctx_lp_pkt_cnt_i_pre); +int iSetCTX_EC_PKT_CNT_I_PRE_ctx_ec_pkt_cnt_i_pre(unsigned int uctx_ec_pkt_cnt_i_pre); +int iSetCTX_BD_ERR_CNT_ctx_bd_err_cnt(unsigned int uctx_bd_err_cnt); +int iSetCTX_LEN_ERR_CNT_ctx_len_err_cnt(unsigned int uctx_len_err_cnt); +int iSetCTX_LP_PKT_CNT_I_ctx_lp_pkt_cnt_i(unsigned int uctx_lp_pkt_cnt_i); +int iSetCTX_EC_PKT_CNT_I_ctx_ec_pkt_cnt_i(unsigned int uctx_ec_pkt_cnt_i); +int iSetCTX_LP_PKT_CNT_O_ctx_lp_pkt_cnt_o(unsigned int uctx_lp_pkt_cnt_o); +int iSetCTX_EC_PKT_CNT_O_ctx_ec_pkt_cnt_o(unsigned int uctx_ec_pkt_cnt_o); +int iSetCRYPTOTX_IF_I_CNT_cryptotx_if_i_cnt(unsigned int ucryptotx_if_i_cnt); +int iSetCTX_BDSPLIT_LEN_I_ctx_bdsplit_len_i(unsigned int uctx_bdsplit_len_i); +int iSetCTX_BDSPLIT_LEN_O_ctx_bdsplit_len_o(unsigned int uctx_bdsplit_len_o); +int iSetCTX_PKT_CMB_LEN_O_ctx_pkt_cmb_len_o(unsigned int uctx_pkt_cmb_len_o); + +/* Define the union csr_hpre_core_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_enb0 : 1; /* [0] */ + u32 hpre_core_enb1 : 1; /* [1] */ + u32 hpre_core_enb2 : 1; /* [2] */ + u32 hpre_core_enb3 : 1; /* [3] */ + u32 rsv_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_enb_u; + +/* Define the union csr_hpre_cluster_dyn_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_cluster_dyn_enb : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cluster_dyn_enb_u; + +/* Define the union csr_hpre_core_ini_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_ini_cfg : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_ini_cfg_u; + +/* Define the union csr_hpre_core_ini_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_status0 : 1; /* [0] */ + u32 hpre_core_status1 : 1; /* [1] */ + u32 hpre_core_status2 : 1; /* [2] */ + u32 hpre_core_status3 : 1; /* [3] */ + u32 rsv_3 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_ini_status_u; + +/* Define the union csr_hpre_err_bit_inject_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_bit_inject_en : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_err_bit_inject_en_u; + +/* Define the union csr_hpre_core_shb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shb_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_shb_cfg_u; + +/* Define the union csr_hpre_core_shb_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shb_warning : 4; /* [3:0] */ + u32 rsv_5 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_shb_st_u; + +/* Define the union csr_hpre_core_idle_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_arb_st : 4; /* [3:0] */ + u32 rsv_6 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_idle_st_u; + +/* Define the union csr_hpre_core_status_inquire_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_status_inquire_req : 1; /* [0] */ + u32 hpre_core_status_inquire_content : 11; /* [11:1] */ + u32 core_idx : 2; /* [13:12] */ + u32 rsv_7 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_status_inquire_u; + +/* Define the union csr_hpre_core_status_result_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_status_result : 18; /* [17:0] */ + u32 result_core_idx : 2; /* [19:18] */ + u32 latest_inquire_content : 11; /* [30:20] */ + u32 hpre_core_status_result_rdy : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_status_result_u; + +/* Define the union csr_hpre_core_err_bit_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ej_core_idx : 2; /* [1:0] */ + u32 ej_cmd : 4; /* [5:2] */ + u32 ram_bit0_inject : 13; /* [18:6] */ + u32 ram_bit1_inject : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_err_bit_inject_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hpre_core_enb_u hpre_core_enb; /* 4 */ + volatile csr_hpre_cluster_dyn_enb_u hpre_cluster_dyn_enb; /* 10 */ + volatile csr_hpre_core_ini_cfg_u hpre_core_ini_cfg; /* 20 */ + volatile csr_hpre_core_ini_status_u hpre_core_ini_status; /* 80 */ + volatile csr_hpre_err_bit_inject_en_u hpre_err_bit_inject_en; /* 84 */ + volatile csr_hpre_core_shb_cfg_u hpre_core_shb_cfg; /* 88 */ + volatile csr_hpre_core_shb_st_u hpre_core_shb_st; /* 8C */ + volatile csr_hpre_core_idle_st_u hpre_core_idle_st; /* 90 */ + volatile csr_hpre_core_status_inquire_u hpre_core_status_inquire; /* 100 */ + volatile csr_hpre_core_status_result_u hpre_core_status_result; /* 104 */ + volatile csr_hpre_core_err_bit_inject_u hpre_core_err_bit_inject; /* 108 */ +} S_hpre_cluster_REGS_TYPE; + +/* Declare the struct pointor of the module hpre_cluster */ +extern volatile S_hpre_cluster_REGS_TYPE *gophpre_clusterAllReg; + +/* Declare the functions that set the member value */ +int iSetHPRE_CORE_ENB_hpre_core_enb0(unsigned int uhpre_core_enb0); +int iSetHPRE_CORE_ENB_hpre_core_enb1(unsigned int uhpre_core_enb1); +int iSetHPRE_CORE_ENB_hpre_core_enb2(unsigned int uhpre_core_enb2); +int iSetHPRE_CORE_ENB_hpre_core_enb3(unsigned int uhpre_core_enb3); +int iSetHPRE_CLUSTER_DYN_ENB_hpre_cluster_dyn_enb(unsigned int uhpre_cluster_dyn_enb); +int iSetHPRE_CORE_INI_CFG_hpre_core_ini_cfg(unsigned int uhpre_core_ini_cfg); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status0(unsigned int uhpre_core_status0); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status1(unsigned int uhpre_core_status1); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status2(unsigned int uhpre_core_status2); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status3(unsigned int uhpre_core_status3); +int iSetHPRE_ERR_BIT_INJECT_EN_err_bit_inject_en(unsigned int uerr_bit_inject_en); +int iSetHPRE_CORE_SHB_CFG_shb_num(unsigned int ushb_num); +int iSetHPRE_CORE_SHB_ST_shb_warning(unsigned int ushb_warning); +int iSetHPRE_CORE_IDLE_ST_core_arb_st(unsigned int ucore_arb_st); +int iSetHPRE_CORE_STATUS_INQUIRE_hpre_core_status_inquire_req(unsigned int uhpre_core_status_inquire_req); +int iSetHPRE_CORE_STATUS_INQUIRE_hpre_core_status_inquire_content(unsigned int uhpre_core_status_inquire_content); +int iSetHPRE_CORE_STATUS_INQUIRE_core_idx(unsigned int ucore_idx); +int iSetHPRE_CORE_STATUS_RESULT_hpre_core_status_result(unsigned int uhpre_core_status_result); +int iSetHPRE_CORE_STATUS_RESULT_result_core_idx(unsigned int uresult_core_idx); +int iSetHPRE_CORE_STATUS_RESULT_latest_inquire_content(unsigned int ulatest_inquire_content); +int iSetHPRE_CORE_STATUS_RESULT_hpre_core_status_result_rdy(unsigned int uhpre_core_status_result_rdy); +int iSetHPRE_CORE_ERR_BIT_INJECT_ej_core_idx(unsigned int uej_core_idx); +int iSetHPRE_CORE_ERR_BIT_INJECT_ej_cmd(unsigned int uej_cmd); +int iSetHPRE_CORE_ERR_BIT_INJECT_ram_bit0_inject(unsigned int uram_bit0_inject); +int iSetHPRE_CORE_ERR_BIT_INJECT_ram_bit1_inject(unsigned int uram_bit1_inject); + +/* Define the union csr_hpre_common_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_common_cnt_clr_ce_u; + +/* Define the union csr_hpre_cfg_axqos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 awqos : 4; /* [3:0] */ + u32 arqos : 4; /* [7:4] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_axqos_u; + +/* Define the union csr_hpre_cfg_axcache_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 awcache : 4; /* [3:0] */ + u32 arcache : 4; /* [7:4] */ + u32 rsv_1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_axcache_u; + +/* Define the union csr_hpre_cfg_rdchn_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdchn_ini : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_rdchn_ini_u; + +/* Define the union csr_hpre_cfg_awuser_fp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aw_fp1_enb : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_awuser_fp_cfg_u; + +/* Define the union csr_hpre_cfg_bd_endian_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_endian : 2; /* [1:0] */ + u32 rsv_4 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_bd_endian_u; + +/* Define the union csr_hpre_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_bypass : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ecc_bypass_u; + +/* Define the union csr_hpre_ras_int_width_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ras_int_width : 10; /* [9:0] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ras_int_width_cfg_u; + +/* Define the union csr_hpre_poison_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_poison_bypass : 1; /* [0] */ + u32 wr_poison_bypass : 1; /* [1] */ + u32 rsv_7 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_poison_bypass_u; + +/* Define the union csr_hpre_bd_aruser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_aruser_snpattr : 1; /* [0] */ + u32 bd_aruser_cmd_type : 3; /* [3:1] */ + u32 bd_aruser_type : 2; /* [5:4] */ + u32 bd_aruser_cleaninvalid : 1; /* [6] */ + u32 bd_aruser_fna : 1; /* [7] */ + u32 bd_aruser_fa : 1; /* [8] */ + u32 bd_aruser_ssv : 1; /* [9] */ + u32 rsv_8 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_bd_aruser_cfg_u; + +/* Define the union csr_hpre_bd_awuser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_awuser_snpattr : 1; /* [0] */ + u32 bd_awuser_cmd_type : 3; /* [3:1] */ + u32 bd_awuser_type : 2; /* [5:4] */ + u32 bd_awuser_fp1_enb : 1; /* [6] */ + u32 bd_awuser_fna : 1; /* [7] */ + u32 bd_awuser_fa : 1; /* [8] */ + u32 bd_awuser_ssv : 1; /* [9] */ + u32 rsv_9 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_bd_awuser_cfg_u; + +/* Define the union csr_hpre_types_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 task_type_enb : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_types_enb_u; + +/* Define the union csr_hpre_data_aruser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_aruser_snpattr : 1; /* [0] */ + u32 data_aruser_cmd_type : 3; /* [3:1] */ + u32 data_aruser_type : 2; /* [5:4] */ + u32 data_aruser_cleaninvalid : 1; /* [6] */ + u32 data_aruser_fna : 1; /* [7] */ + u32 data_aruser_fa : 1; /* [8] */ + u32 data_aruser_ssv : 1; /* [9] */ + u32 rsv_11 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_data_aruser_cfg_u; + +/* Define the union csr_hpre_data_awuser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_awuser_snpattr : 1; /* [0] */ + u32 data_awuser_cmd_type : 3; /* [3:1] */ + u32 data_awuser_type : 2; /* [5:4] */ + u32 data_awuser_fp1_enb : 1; /* [6] */ + u32 data_awuser_fna : 1; /* [7] */ + u32 data_awuser_fa : 1; /* [8] */ + u32 data_awuser_ssv : 1; /* [9] */ + u32 rsv_12 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_data_awuser_cfg_u; + +/* Define the union csr_hpre_am_ooo_shutdown_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 am_ooo_shutdown_enb : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_am_ooo_shutdown_enb_u; + +/* Define the union csr_hpre_hac_int_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_msk : 1; /* [0] */ + u32 core_ecc_2bit_err_msk : 1; /* [1] */ + u32 dat_wb_poison_msk : 1; /* [2] */ + u32 dat_rd_poison_msk : 1; /* [3] */ + u32 bd_rd_poison_msk : 1; /* [4] */ + u32 ooo_ecc_2bit_err_msk : 1; /* [5] */ + u32 cluster1_shb_timeout_msk : 1; /* [6] */ + u32 cluster2_shb_timeout_msk : 1; /* [7] */ + u32 cluster3_shb_timeout_msk : 1; /* [8] */ + u32 cluster4_shb_timeout_msk : 1; /* [9] */ + u32 ooo_rdrsp_err_msk : 6; /* [15:10] */ + u32 ooo_wrrsp_err_msk : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_msk : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_msk : 1; /* [23] */ + u32 datrd_ecc_1bit_err_msk : 1; /* [24] */ + u32 datrd_ecc_2bit_err_msk : 1; /* [25] */ + u32 rsv_14 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_int_msk_u; + +/* Define the union csr_hpre_ras_ecc1bit_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_ras_ecc1bit_th : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ras_ecc1bit_th_u; + +/* Define the union csr_hpre_hac_ras_ce_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hac_ras_ce_enb : 26; /* [25:0] */ + u32 rsv_16 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_ce_enb_u; + +/* Define the union csr_hpre_hac_ras_nfe_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hac_ras_nfe_enb : 26; /* [25:0] */ + u32 rsv_17 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_nfe_enb_u; + +/* Define the union csr_hpre_hac_ras_fe_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hac_ras_fe_enb : 26; /* [25:0] */ + u32 rsv_18 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_fe_enb_u; + +/* Define the union csr_hpre_hac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_int_set : 1; /* [0] */ + u32 core_ecc_2bit_err_int_set : 1; /* [1] */ + u32 dat_wb_poison_int_set : 1; /* [2] */ + u32 dat_rd_poison_int_set : 1; /* [3] */ + u32 bd_rd_poison_int_set : 1; /* [4] */ + u32 ooo_ecc_2bit_err_int_set : 1; /* [5] */ + u32 cluster1_shb_timeout_int_set : 1; /* [6] */ + u32 cluster2_shb_timeout_int_set : 1; /* [7] */ + u32 cluster3_shb_timeout_int_set : 1; /* [8] */ + u32 cluster4_shb_timeout_int_set : 1; /* [9] */ + u32 ooo_rdrsp_err_int_set : 6; /* [15:10] */ + u32 ooo_wrrsp_err_int_set : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_int_set : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_int_set : 1; /* [23] */ + u32 datrd_ecc_1bit_err_int_set : 1; /* [24] */ + u32 datrd_ecc_2bit_err_int_set : 1; /* [25] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_int_set_u; + +/* Define the union csr_hpre_hac_rint_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_rint : 1; /* [0] */ + u32 core_ecc_2bit_err_rint : 1; /* [1] */ + u32 dat_wb_poison_rint : 1; /* [2] */ + u32 dat_rd_poison_rint : 1; /* [3] */ + u32 bd_rd_poison_rint : 1; /* [4] */ + u32 ooo_ecc_2bit_err_rint : 1; /* [5] */ + u32 cluster1_shb_timeout_rint : 1; /* [6] */ + u32 cluster2_shb_timeout_rint : 1; /* [7] */ + u32 cluster3_shb_timeout_rint : 1; /* [8] */ + u32 cluster4_shb_timeout_rint : 1; /* [9] */ + u32 ooo_rdrsp_err_rint : 6; /* [15:10] */ + u32 ooo_wrrsp_err_rint : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_rint : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_rint : 1; /* [23] */ + u32 datrd_ecc_1bit_err_rint : 1; /* [24] */ + u32 datrd_ecc_2bit_err_rint : 1; /* [25] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_rint_u; + +/* Define the union csr_hpre_hac_int_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_int_st : 1; /* [0] */ + u32 core_ecc_2bit_err_int_st : 1; /* [1] */ + u32 dat_wb_poison_int_st : 1; /* [2] */ + u32 dat_rd_poison_int_st : 1; /* [3] */ + u32 bd_rd_poison_int_st : 1; /* [4] */ + u32 ooo_ecc_2bit_err_int_st : 1; /* [5] */ + u32 cluster1_shb_timeout_int_st : 1; /* [6] */ + u32 cluster2_shb_timeout_int_st : 1; /* [7] */ + u32 cluster3_shb_timeout_int_st : 1; /* [8] */ + u32 cluster4_shb_timeout_int_st : 1; /* [9] */ + u32 ooo_rdrsp_err_int_st : 6; /* [15:10] */ + u32 ooo_wrrsp_err_int_st : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_int_st : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_int_st : 1; /* [23] */ + u32 datrd_ecc_1bit_err_int_st : 1; /* [24] */ + u32 datrd_ecc_2bit_err_int_st : 1; /* [25] */ + u32 rsv_21 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_int_st_u; + +/* Define the union csr_hpre_fifo_afull_his1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_rd_chn_fifo_afull_his : 4; /* [3:0] */ + u32 rsv_22 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_afull_his1_u; + +/* Define the union csr_hpre_fifo_afull_his2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_wb_chn_fifo_afull_his : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_afull_his2_u; + +/* Define the union csr_hpre_fifo_afull_his3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdtn_fifo_afull_his : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_afull_his3_u; + +/* Define the union csr_hpre_fifo_full_his1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_rd_chn_fifo_full_his : 4; /* [3:0] */ + u32 rsv_24 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_full_his1_u; + +/* Define the union csr_hpre_fifo_full_his2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_wb_chn_fifo_full_his : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_full_his2_u; + +/* Define the union csr_hpre_fifo_full_his3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdtn_fifo_full_his : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_full_his3_u; + +/* Define the union csr_hpre_fifo_empty_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_rd_chn_fifo_empty : 4; /* [3:0] */ + u32 rsv_26 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_empty_st1_u; + +/* Define the union csr_hpre_fifo_empty_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_wb_chn_fifo_empty : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_empty_st2_u; + +/* Define the union csr_hpre_fifo_empty_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdtn_fifo_empty : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_empty_st3_u; + +/* Define the union csr_hpre_mem_ebit_inj_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iobuf_err_bit_inject_en : 1; /* [0] */ + u32 qmv2_err_bit_inject_en : 1; /* [1] */ + u32 rsv_28 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ebit_inj_en_u; + +/* Define the union csr_hpre_mem_ebit_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iobuf_ram0_err_bit_inj : 2; /* [1:0] */ + u32 iobuf_ram1_err_bit_inj : 2; /* [3:2] */ + u32 iobuf_ram2_err_bit_inj : 2; /* [5:4] */ + u32 iobuf_ram3_err_bit_inj : 2; /* [7:6] */ + u32 qmv2_storem_errbit_inj : 2; /* [9:8] */ + u32 qmv2_store_comp_m_errbit_inj : 2; /* [11:10] */ + u32 rsv_29 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ebit_inj_u; + +/* Define the union csr_hpre_qmv2_mem_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmv2_storem_err_addr : 8; /* [7:0] */ + u32 qmv2_store_comp_m_err_addr : 8; /* [15:8] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_qmv2_mem_err_addr_u; + +/* Define the union csr_hpre_clkgate_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clk_gate_enable : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_clkgate_enb_u; + +/* Define the union csr_hpre_crypt_do_crt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_do_credit : 4; /* [3:0] */ + u32 rsv_32 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_crypt_do_crt_u; + +/* Define the union csr_hpre_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_cpi_int_index : 24; /* [23:0] */ + u32 rsv_33 : 3; /* [26:24] */ + u32 hpre_enable : 1; /* [27] */ + u32 hpre_int_issue : 1; /* [28] */ + u32 rsv_34 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_int_vector_u; + +/* Define the union csr_hpre_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_int_data : 6; /* [5:0] */ + u32 rsv_35 : 10; /* [15:6] */ + u32 hpre_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_int_u; + +/* Define the union csr_hpre_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_int_en : 6; /* [5:0] */ + u32 rsv_36 : 10; /* [15:6] */ + u32 hpre_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_int_en_u; + +/* Define the union csr_hpre_hac_ras_ce_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_hac_ras_ce_err : 1; /* [0] */ + u32 hpre_hac_ras_ce_err_inj : 1; /* [1] */ + u32 hpre_hac_ras_ce_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_ce_err_u; + +/* Define the union csr_hpre_hac_ras_fe_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_hac_ras_fe_err : 1; /* [0] */ + u32 hpre_hac_ras_fe_err_inj : 1; /* [1] */ + u32 hpre_hac_ras_fe_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_fe_err_u; + +/* Define the union csr_hpre_hac_ras_nfe_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_hac_ras_nfe_err : 1; /* [0] */ + u32 hpre_hac_ras_nfe_err_inj : 1; /* [1] */ + u32 hpre_hac_ras_nfe_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_nfe_err_u; + +/* Define the union csr_int_sram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_sram_err : 1; /* [0] */ + u32 int_sram_err_inj : 1; /* [1] */ + u32 int_sram_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_sram_err_u; + +/* Define the union csr_hpre_di_fsm_timeout_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_di_fsm_timeout_err : 1; /* [0] */ + u32 hpre_di_fsm_timeout_err_inj : 1; /* [1] */ + u32 hpre_di_fsm_timeout_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_di_fsm_timeout_err_u; + +/* Define the union csr_hpre_do_fsm_timeout_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_do_fsm_timeout_err : 1; /* [0] */ + u32 hpre_do_fsm_timeout_err_inj : 1; /* [1] */ + u32 hpre_do_fsm_timeout_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_do_fsm_timeout_err_u; + +/* Define the union csr_hpre_dido_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 di_sop_overlapped_err : 1; /* [0] */ + u32 di_eop_len_nomatch_err : 1; /* [1] */ + u32 di_alg_err : 1; /* [2] */ + u32 di_len_err : 1; /* [3] */ + u32 di_strb_err : 1; /* [4] */ + u32 di_fifo_err : 1; /* [5] */ + u32 di_axi_wr_err : 1; /* [6] */ + u32 di_credit_err : 1; /* [7] */ + u32 do_credit_err : 1; /* [8] */ + u32 do_fifo_err : 1; /* [9] */ + u32 do_axi_rd_err : 1; /* [10] */ + u32 rsv_37 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_dido_err_info_u; + +/* Define the union csr_hpre_fsm_shb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fsm_shb_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fsm_shb_cfg_u; + +/* Define the union csr_hpre_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_0_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_0_u; + +/* Define the union csr_hpre_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_1_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_1_u; + +/* Define the union csr_hpre_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_2_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_2_u; + +/* Define the union csr_hpre_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_3_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_3_u; + +/* Define the union csr_hpre_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_4_bus : 6; /* [5:0] */ + u32 rsv_38 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_4_u; + +/* Define the union csr_hpre_rdchn_ini_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdchn_ini_st : 1; /* [0] */ + u32 rsv_39 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_rdchn_ini_st_u; + +/* Define the union csr_hpre_ecc1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_ecc1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ecc1bit_err_cnt_u; + +/* Define the union csr_hpre_ecc2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_ecc2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ecc2bit_err_cnt_u; + +/* Define the union csr_hpre_peh_eco1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco1_u; + +/* Define the union csr_hpre_peh_eco2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco2_u; + +/* Define the union csr_hpre_peh_eco3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco3_u; + +/* Define the union csr_hpre_peh_eco4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco4_u; + +/* Define the union csr_hpre_peh_eco5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco5_u; + +/* Define the union csr_hpre_eco1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco1_u; + +/* Define the union csr_hpre_eco2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco2_u; + +/* Define the union csr_hpre_eco3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco3_u; + +/* Define the union csr_hpre_eco4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco4_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hpre_cfg_axqos_u hpre_cfg_axqos; /* C */ + volatile csr_hpre_cfg_axcache_u hpre_cfg_axcache; /* 10 */ + volatile csr_hpre_cfg_rdchn_ini_u hpre_cfg_rdchn_ini; /* 14 */ + volatile csr_hpre_cfg_awuser_fp_cfg_u hpre_cfg_awuser_fp_cfg; /* 18 */ + volatile csr_hpre_cfg_bd_endian_u hpre_cfg_bd_endian; /* 20 */ + volatile csr_hpre_ecc_bypass_u hpre_ecc_bypass; /* 24 */ + volatile csr_hpre_ras_int_width_cfg_u hpre_ras_int_width_cfg; /* 28 */ + volatile csr_hpre_poison_bypass_u hpre_poison_bypass; /* 2C */ + volatile csr_hpre_bd_aruser_cfg_u hpre_bd_aruser_cfg; /* 30 */ + volatile csr_hpre_bd_awuser_cfg_u hpre_bd_awuser_cfg; /* 34 */ + volatile csr_hpre_types_enb_u hpre_types_enb; /* 38 */ + volatile csr_hpre_data_aruser_cfg_u hpre_data_aruser_cfg; /* 3C */ + volatile csr_hpre_data_awuser_cfg_u hpre_data_awuser_cfg; /* 40 */ + volatile csr_hpre_am_ooo_shutdown_enb_u hpre_am_ooo_shutdown_enb; /* 44 */ + volatile csr_hpre_hac_int_msk_u hpre_hac_int_msk; /* 400 */ + volatile csr_hpre_ras_ecc1bit_th_u hpre_ras_ecc1bit_th; /* 40C */ + volatile csr_hpre_hac_ras_ce_enb_u hpre_hac_ras_ce_enb; /* 410 */ + volatile csr_hpre_hac_ras_nfe_enb_u hpre_hac_ras_nfe_enb; /* 414 */ + volatile csr_hpre_hac_ras_fe_enb_u hpre_hac_ras_fe_enb; /* 418 */ + volatile csr_hpre_hac_int_set_u hpre_hac_int_set; /* 500 */ + volatile csr_hpre_hac_rint_u hpre_hac_rint; /* 600 */ + volatile csr_hpre_hac_int_st_u hpre_hac_int_st; /* 800 */ + volatile csr_hpre_fifo_afull_his1_u hpre_fifo_afull_his1; /* 810 */ + volatile csr_hpre_fifo_afull_his2_u hpre_fifo_afull_his2; /* 814 */ + volatile csr_hpre_fifo_afull_his3_u hpre_fifo_afull_his3; /* 818 */ + volatile csr_hpre_fifo_full_his1_u hpre_fifo_full_his1; /* 840 */ + volatile csr_hpre_fifo_full_his2_u hpre_fifo_full_his2; /* 844 */ + volatile csr_hpre_fifo_full_his3_u hpre_fifo_full_his3; /* 848 */ + volatile csr_hpre_fifo_empty_st1_u hpre_fifo_empty_st1; /* 880 */ + volatile csr_hpre_fifo_empty_st2_u hpre_fifo_empty_st2; /* 884 */ + volatile csr_hpre_fifo_empty_st3_u hpre_fifo_empty_st3; /* 888 */ + volatile csr_hpre_mem_ebit_inj_en_u hpre_mem_ebit_inj_en; /* 900 */ + volatile csr_hpre_mem_ebit_inj_u hpre_mem_ebit_inj; /* 904 */ + volatile csr_hpre_qmv2_mem_err_addr_u hpre_qmv2_mem_err_addr; /* 908 */ + volatile csr_hpre_clkgate_enb_u hpre_clkgate_enb; /* 90C */ + volatile csr_hpre_crypt_do_crt_u hpre_crypt_do_crt; /* 910 */ + volatile csr_hpre_int_vector_u hpre_int_vector; /* 914 */ + volatile csr_hpre_int_u hpre_int; /* 918 */ + volatile csr_hpre_int_en_u hpre_int_en; /* 91C */ + volatile csr_hpre_hac_ras_ce_err_u hpre_hac_ras_ce_err; /* 920 */ + volatile csr_hpre_hac_ras_fe_err_u hpre_hac_ras_fe_err; /* 924 */ + volatile csr_hpre_hac_ras_nfe_err_u hpre_hac_ras_nfe_err; /* 928 */ + volatile csr_int_sram_err_u int_sram_err; /* 92C */ + volatile csr_hpre_di_fsm_timeout_err_u hpre_di_fsm_timeout_err; /* 930 */ + volatile csr_hpre_do_fsm_timeout_err_u hpre_do_fsm_timeout_err; /* 934 */ + volatile csr_hpre_dido_err_info_u hpre_dido_err_info; /* 938 */ + volatile csr_hpre_fsm_shb_cfg_u hpre_fsm_shb_cfg; /* 93C */ + volatile csr_hpre_mem_ctrl_0_u hpre_mem_ctrl_0; /* 940 */ + volatile csr_hpre_mem_ctrl_1_u hpre_mem_ctrl_1; /* 944 */ + volatile csr_hpre_mem_ctrl_2_u hpre_mem_ctrl_2; /* 948 */ + volatile csr_hpre_mem_ctrl_3_u hpre_mem_ctrl_3; /* 94C */ + volatile csr_hpre_mem_ctrl_4_u hpre_mem_ctrl_4; /* 950 */ + volatile csr_hpre_rdchn_ini_st_u hpre_rdchn_ini_st; /* A00 */ + volatile csr_hpre_ecc1bit_err_cnt_u hpre_ecc1bit_err_cnt; /* A04 */ + volatile csr_hpre_ecc2bit_err_cnt_u hpre_ecc2bit_err_cnt; /* A08 */ + volatile csr_hpre_peh_eco1_u hpre_peh_eco1; /* A10 */ + volatile csr_hpre_peh_eco2_u hpre_peh_eco2; /* A14 */ + volatile csr_hpre_peh_eco3_u hpre_peh_eco3; /* A18 */ + volatile csr_hpre_peh_eco4_u hpre_peh_eco4; /* A1C */ + volatile csr_hpre_peh_eco5_u hpre_peh_eco5; /* A20 */ + volatile csr_hpre_eco1_u hpre_eco1; /* A24 */ + volatile csr_hpre_eco2_u hpre_eco2; /* A28 */ + volatile csr_hpre_eco3_u hpre_eco3; /* A2C */ + volatile csr_hpre_eco4_u hpre_eco4; /* A30 */ +} S_hpre_common_REGS_TYPE; + +/* Declare the struct pointor of the module hpre_common */ +extern volatile S_hpre_common_REGS_TYPE *gophpre_commonAllReg; + +/* Declare the functions that set the member value */ +int iSetHPRE_CFG_AXQOS_awqos(unsigned int uawqos); +int iSetHPRE_CFG_AXQOS_arqos(unsigned int uarqos); +int iSetHPRE_CFG_AXCACHE_awcache(unsigned int uawcache); +int iSetHPRE_CFG_AXCACHE_arcache(unsigned int uarcache); +int iSetHPRE_CFG_RDCHN_INI_rdchn_ini(unsigned int urdchn_ini); +int iSetHPRE_CFG_AWUSER_FP_CFG_aw_fp1_enb(unsigned int uaw_fp1_enb); +int iSetHPRE_CFG_BD_ENDIAN_bd_endian(unsigned int ubd_endian); +int iSetHPRE_ECC_BYPASS_ecc_bypass(unsigned int uecc_bypass); +int iSetHPRE_RAS_INT_WIDTH_CFG_ras_int_width(unsigned int uras_int_width); +int iSetHPRE_POISON_BYPASS_rd_poison_bypass(unsigned int urd_poison_bypass); +int iSetHPRE_POISON_BYPASS_wr_poison_bypass(unsigned int uwr_poison_bypass); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_snpattr(unsigned int ubd_aruser_snpattr); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_cmd_type(unsigned int ubd_aruser_cmd_type); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_type(unsigned int ubd_aruser_type); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_cleaninvalid(unsigned int ubd_aruser_cleaninvalid); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_fna(unsigned int ubd_aruser_fna); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_fa(unsigned int ubd_aruser_fa); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_ssv(unsigned int ubd_aruser_ssv); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_snpattr(unsigned int ubd_awuser_snpattr); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_cmd_type(unsigned int ubd_awuser_cmd_type); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_type(unsigned int ubd_awuser_type); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_fp1_enb(unsigned int ubd_awuser_fp1_enb); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_fna(unsigned int ubd_awuser_fna); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_fa(unsigned int ubd_awuser_fa); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_ssv(unsigned int ubd_awuser_ssv); +int iSetHPRE_TYPES_ENB_task_type_enb(unsigned int utask_type_enb); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_snpattr(unsigned int udata_aruser_snpattr); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_cmd_type(unsigned int udata_aruser_cmd_type); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_type(unsigned int udata_aruser_type); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_cleaninvalid(unsigned int udata_aruser_cleaninvalid); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_fna(unsigned int udata_aruser_fna); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_fa(unsigned int udata_aruser_fa); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_ssv(unsigned int udata_aruser_ssv); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_snpattr(unsigned int udata_awuser_snpattr); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_cmd_type(unsigned int udata_awuser_cmd_type); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_type(unsigned int udata_awuser_type); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_fp1_enb(unsigned int udata_awuser_fp1_enb); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_fna(unsigned int udata_awuser_fna); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_fa(unsigned int udata_awuser_fa); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_ssv(unsigned int udata_awuser_ssv); +int iSetHPRE_AM_OOO_SHUTDOWN_ENB_am_ooo_shutdown_enb(unsigned int uam_ooo_shutdown_enb); +int iSetHPRE_HAC_INT_MSK_core_ecc_1bit_err_msk(unsigned int ucore_ecc_1bit_err_msk); +int iSetHPRE_HAC_INT_MSK_core_ecc_2bit_err_msk(unsigned int ucore_ecc_2bit_err_msk); +int iSetHPRE_HAC_INT_MSK_dat_wb_poison_msk(unsigned int udat_wb_poison_msk); +int iSetHPRE_HAC_INT_MSK_dat_rd_poison_msk(unsigned int udat_rd_poison_msk); +int iSetHPRE_HAC_INT_MSK_bd_rd_poison_msk(unsigned int ubd_rd_poison_msk); +int iSetHPRE_HAC_INT_MSK_ooo_ecc_2bit_err_msk(unsigned int uooo_ecc_2bit_err_msk); +int iSetHPRE_HAC_INT_MSK_cluster1_shb_timeout_msk(unsigned int ucluster1_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_cluster2_shb_timeout_msk(unsigned int ucluster2_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_cluster3_shb_timeout_msk(unsigned int ucluster3_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_cluster4_shb_timeout_msk(unsigned int ucluster4_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_ooo_rdrsp_err_msk(unsigned int uooo_rdrsp_err_msk); +int iSetHPRE_HAC_INT_MSK_ooo_wrrsp_err_msk(unsigned int uooo_wrrsp_err_msk); +int iSetHPRE_HAC_INT_MSK_qmv2_ecc_1bit_err_msk(unsigned int uqmv2_ecc_1bit_err_msk); +int iSetHPRE_HAC_INT_MSK_qmv2_ecc_2bit_err_msk(unsigned int uqmv2_ecc_2bit_err_msk); +int iSetHPRE_HAC_INT_MSK_datrd_ecc_1bit_err_msk(unsigned int udatrd_ecc_1bit_err_msk); +int iSetHPRE_HAC_INT_MSK_datrd_ecc_2bit_err_msk(unsigned int udatrd_ecc_2bit_err_msk); +int iSetHPRE_RAS_ECC1BIT_TH_hpre_ras_ecc1bit_th(unsigned int uhpre_ras_ecc1bit_th); +int iSetHPRE_HAC_RAS_CE_ENB_hac_ras_ce_enb(unsigned int uhac_ras_ce_enb); +int iSetHPRE_HAC_RAS_NFE_ENB_hac_ras_nfe_enb(unsigned int uhac_ras_nfe_enb); +int iSetHPRE_HAC_RAS_FE_ENB_hac_ras_fe_enb(unsigned int uhac_ras_fe_enb); +int iSetHPRE_HAC_INT_SET_core_ecc_1bit_err_int_set(unsigned int ucore_ecc_1bit_err_int_set); +int iSetHPRE_HAC_INT_SET_core_ecc_2bit_err_int_set(unsigned int ucore_ecc_2bit_err_int_set); +int iSetHPRE_HAC_INT_SET_dat_wb_poison_int_set(unsigned int udat_wb_poison_int_set); +int iSetHPRE_HAC_INT_SET_dat_rd_poison_int_set(unsigned int udat_rd_poison_int_set); +int iSetHPRE_HAC_INT_SET_bd_rd_poison_int_set(unsigned int ubd_rd_poison_int_set); +int iSetHPRE_HAC_INT_SET_ooo_ecc_2bit_err_int_set(unsigned int uooo_ecc_2bit_err_int_set); +int iSetHPRE_HAC_INT_SET_cluster1_shb_timeout_int_set(unsigned int ucluster1_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_cluster2_shb_timeout_int_set(unsigned int ucluster2_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_cluster3_shb_timeout_int_set(unsigned int ucluster3_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_cluster4_shb_timeout_int_set(unsigned int ucluster4_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_ooo_rdrsp_err_int_set(unsigned int uooo_rdrsp_err_int_set); +int iSetHPRE_HAC_INT_SET_ooo_wrrsp_err_int_set(unsigned int uooo_wrrsp_err_int_set); +int iSetHPRE_HAC_INT_SET_qmv2_ecc_1bit_err_int_set(unsigned int uqmv2_ecc_1bit_err_int_set); +int iSetHPRE_HAC_INT_SET_qmv2_ecc_2bit_err_int_set(unsigned int uqmv2_ecc_2bit_err_int_set); +int iSetHPRE_HAC_INT_SET_datrd_ecc_1bit_err_int_set(unsigned int udatrd_ecc_1bit_err_int_set); +int iSetHPRE_HAC_INT_SET_datrd_ecc_2bit_err_int_set(unsigned int udatrd_ecc_2bit_err_int_set); +int iSetHPRE_HAC_RINT_core_ecc_1bit_err_rint(unsigned int ucore_ecc_1bit_err_rint); +int iSetHPRE_HAC_RINT_core_ecc_2bit_err_rint(unsigned int ucore_ecc_2bit_err_rint); +int iSetHPRE_HAC_RINT_dat_wb_poison_rint(unsigned int udat_wb_poison_rint); +int iSetHPRE_HAC_RINT_dat_rd_poison_rint(unsigned int udat_rd_poison_rint); +int iSetHPRE_HAC_RINT_bd_rd_poison_rint(unsigned int ubd_rd_poison_rint); +int iSetHPRE_HAC_RINT_ooo_ecc_2bit_err_rint(unsigned int uooo_ecc_2bit_err_rint); +int iSetHPRE_HAC_RINT_cluster1_shb_timeout_rint(unsigned int ucluster1_shb_timeout_rint); +int iSetHPRE_HAC_RINT_cluster2_shb_timeout_rint(unsigned int ucluster2_shb_timeout_rint); +int iSetHPRE_HAC_RINT_cluster3_shb_timeout_rint(unsigned int ucluster3_shb_timeout_rint); +int iSetHPRE_HAC_RINT_cluster4_shb_timeout_rint(unsigned int ucluster4_shb_timeout_rint); +int iSetHPRE_HAC_RINT_ooo_rdrsp_err_rint(unsigned int uooo_rdrsp_err_rint); +int iSetHPRE_HAC_RINT_ooo_wrrsp_err_rint(unsigned int uooo_wrrsp_err_rint); +int iSetHPRE_HAC_RINT_qmv2_ecc_1bit_err_rint(unsigned int uqmv2_ecc_1bit_err_rint); +int iSetHPRE_HAC_RINT_qmv2_ecc_2bit_err_rint(unsigned int uqmv2_ecc_2bit_err_rint); +int iSetHPRE_HAC_RINT_datrd_ecc_1bit_err_rint(unsigned int udatrd_ecc_1bit_err_rint); +int iSetHPRE_HAC_RINT_datrd_ecc_2bit_err_rint(unsigned int udatrd_ecc_2bit_err_rint); +int iSetHPRE_HAC_INT_ST_core_ecc_1bit_err_int_st(unsigned int ucore_ecc_1bit_err_int_st); +int iSetHPRE_HAC_INT_ST_core_ecc_2bit_err_int_st(unsigned int ucore_ecc_2bit_err_int_st); +int iSetHPRE_HAC_INT_ST_dat_wb_poison_int_st(unsigned int udat_wb_poison_int_st); +int iSetHPRE_HAC_INT_ST_dat_rd_poison_int_st(unsigned int udat_rd_poison_int_st); +int iSetHPRE_HAC_INT_ST_bd_rd_poison_int_st(unsigned int ubd_rd_poison_int_st); +int iSetHPRE_HAC_INT_ST_ooo_ecc_2bit_err_int_st(unsigned int uooo_ecc_2bit_err_int_st); +int iSetHPRE_HAC_INT_ST_cluster1_shb_timeout_int_st(unsigned int ucluster1_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_cluster2_shb_timeout_int_st(unsigned int ucluster2_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_cluster3_shb_timeout_int_st(unsigned int ucluster3_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_cluster4_shb_timeout_int_st(unsigned int ucluster4_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_ooo_rdrsp_err_int_st(unsigned int uooo_rdrsp_err_int_st); +int iSetHPRE_HAC_INT_ST_ooo_wrrsp_err_int_st(unsigned int uooo_wrrsp_err_int_st); +int iSetHPRE_HAC_INT_ST_qmv2_ecc_1bit_err_int_st(unsigned int uqmv2_ecc_1bit_err_int_st); +int iSetHPRE_HAC_INT_ST_qmv2_ecc_2bit_err_int_st(unsigned int uqmv2_ecc_2bit_err_int_st); +int iSetHPRE_HAC_INT_ST_datrd_ecc_1bit_err_int_st(unsigned int udatrd_ecc_1bit_err_int_st); +int iSetHPRE_HAC_INT_ST_datrd_ecc_2bit_err_int_st(unsigned int udatrd_ecc_2bit_err_int_st); +int iSetHPRE_FIFO_AFULL_HIS1_dat_rd_chn_fifo_afull_his(unsigned int udat_rd_chn_fifo_afull_his); +int iSetHPRE_FIFO_AFULL_HIS2_dat_wb_chn_fifo_afull_his(unsigned int udat_wb_chn_fifo_afull_his); +int iSetHPRE_FIFO_AFULL_HIS3_rdtn_fifo_afull_his(unsigned int urdtn_fifo_afull_his); +int iSetHPRE_FIFO_FULL_HIS1_data_rd_chn_fifo_full_his(unsigned int udata_rd_chn_fifo_full_his); +int iSetHPRE_FIFO_FULL_HIS2_dat_wb_chn_fifo_full_his(unsigned int udat_wb_chn_fifo_full_his); +int iSetHPRE_FIFO_FULL_HIS3_rdtn_fifo_full_his(unsigned int urdtn_fifo_full_his); +int iSetHPRE_FIFO_EMPTY_ST1_dat_rd_chn_fifo_empty(unsigned int udat_rd_chn_fifo_empty); +int iSetHPRE_FIFO_EMPTY_ST2_dat_wb_chn_fifo_empty(unsigned int udat_wb_chn_fifo_empty); +int iSetHPRE_FIFO_EMPTY_ST3_rdtn_fifo_empty(unsigned int urdtn_fifo_empty); +int iSetHPRE_MEM_EBIT_INJ_EN_iobuf_err_bit_inject_en(unsigned int uiobuf_err_bit_inject_en); +int iSetHPRE_MEM_EBIT_INJ_EN_qmv2_err_bit_inject_en(unsigned int uqmv2_err_bit_inject_en); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram0_err_bit_inj(unsigned int uiobuf_ram0_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram1_err_bit_inj(unsigned int uiobuf_ram1_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram2_err_bit_inj(unsigned int uiobuf_ram2_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram3_err_bit_inj(unsigned int uiobuf_ram3_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_qmv2_storem_errbit_inj(unsigned int uqmv2_storem_errbit_inj); +int iSetHPRE_MEM_EBIT_INJ_qmv2_store_comp_m_errbit_inj(unsigned int uqmv2_store_comp_m_errbit_inj); +int iSetHPRE_QMV2_MEM_ERR_ADDR_qmv2_storem_err_addr(unsigned int uqmv2_storem_err_addr); +int iSetHPRE_QMV2_MEM_ERR_ADDR_qmv2_store_comp_m_err_addr(unsigned int uqmv2_store_comp_m_err_addr); +int iSetHPRE_CLKGATE_ENB_clk_gate_enable(unsigned int uclk_gate_enable); +int iSetHPRE_CRYPT_DO_CRT_hpre_do_credit(unsigned int uhpre_do_credit); +int iSetHPRE_INT_VECTOR_hpre_cpi_int_index(unsigned int uhpre_cpi_int_index); +int iSetHPRE_INT_VECTOR_hpre_enable(unsigned int uhpre_enable); +int iSetHPRE_INT_VECTOR_hpre_int_issue(unsigned int uhpre_int_issue); +int iSetHPRE_INT_hpre_int_data(unsigned int uhpre_int_data); +int iSetHPRE_INT_hpre_program_csr_id_ro(unsigned int uhpre_program_csr_id_ro); +int iSetHPRE_INT_EN_hpre_int_en(unsigned int uhpre_int_en); +int iSetHPRE_INT_EN_hpre_program_csr_id(unsigned int uhpre_program_csr_id); +int iSetHPRE_HAC_RAS_CE_ERR_hpre_hac_ras_ce_err(unsigned int uhpre_hac_ras_ce_err); +int iSetHPRE_HAC_RAS_CE_ERR_hpre_hac_ras_ce_err_inj(unsigned int uhpre_hac_ras_ce_err_inj); +int iSetHPRE_HAC_RAS_CE_ERR_hpre_hac_ras_ce_err_sticky(unsigned int uhpre_hac_ras_ce_err_sticky); +int iSetHPRE_HAC_RAS_FE_ERR_hpre_hac_ras_fe_err(unsigned int uhpre_hac_ras_fe_err); +int iSetHPRE_HAC_RAS_FE_ERR_hpre_hac_ras_fe_err_inj(unsigned int uhpre_hac_ras_fe_err_inj); +int iSetHPRE_HAC_RAS_FE_ERR_hpre_hac_ras_fe_err_sticky(unsigned int uhpre_hac_ras_fe_err_sticky); +int iSetHPRE_HAC_RAS_NFE_ERR_hpre_hac_ras_nfe_err(unsigned int uhpre_hac_ras_nfe_err); +int iSetHPRE_HAC_RAS_NFE_ERR_hpre_hac_ras_nfe_err_inj(unsigned int uhpre_hac_ras_nfe_err_inj); +int iSetHPRE_HAC_RAS_NFE_ERR_hpre_hac_ras_nfe_err_sticky(unsigned int uhpre_hac_ras_nfe_err_sticky); +int iSetINT_SRAM_ERR_int_sram_err(unsigned int uint_sram_err); +int iSetINT_SRAM_ERR_int_sram_err_inj(unsigned int uint_sram_err_inj); +int iSetINT_SRAM_ERR_int_sram_err_sticky(unsigned int uint_sram_err_sticky); +int iSetHPRE_DI_FSM_TIMEOUT_ERR_hpre_di_fsm_timeout_err(unsigned int uhpre_di_fsm_timeout_err); +int iSetHPRE_DI_FSM_TIMEOUT_ERR_hpre_di_fsm_timeout_err_inj(unsigned int uhpre_di_fsm_timeout_err_inj); +int iSetHPRE_DI_FSM_TIMEOUT_ERR_hpre_di_fsm_timeout_err_sticky(unsigned int uhpre_di_fsm_timeout_err_sticky); +int iSetHPRE_DO_FSM_TIMEOUT_ERR_hpre_do_fsm_timeout_err(unsigned int uhpre_do_fsm_timeout_err); +int iSetHPRE_DO_FSM_TIMEOUT_ERR_hpre_do_fsm_timeout_err_inj(unsigned int uhpre_do_fsm_timeout_err_inj); +int iSetHPRE_DO_FSM_TIMEOUT_ERR_hpre_do_fsm_timeout_err_sticky(unsigned int uhpre_do_fsm_timeout_err_sticky); +int iSetHPRE_DIDO_ERR_INFO_di_sop_overlapped_err(unsigned int udi_sop_overlapped_err); +int iSetHPRE_DIDO_ERR_INFO_di_eop_len_nomatch_err(unsigned int udi_eop_len_nomatch_err); +int iSetHPRE_DIDO_ERR_INFO_di_alg_err(unsigned int udi_alg_err); +int iSetHPRE_DIDO_ERR_INFO_di_len_err(unsigned int udi_len_err); +int iSetHPRE_DIDO_ERR_INFO_di_strb_err(unsigned int udi_strb_err); +int iSetHPRE_DIDO_ERR_INFO_di_fifo_err(unsigned int udi_fifo_err); +int iSetHPRE_DIDO_ERR_INFO_di_axi_wr_err(unsigned int udi_axi_wr_err); +int iSetHPRE_DIDO_ERR_INFO_di_credit_err(unsigned int udi_credit_err); +int iSetHPRE_DIDO_ERR_INFO_do_credit_err(unsigned int udo_credit_err); +int iSetHPRE_DIDO_ERR_INFO_do_fifo_err(unsigned int udo_fifo_err); +int iSetHPRE_DIDO_ERR_INFO_do_axi_rd_err(unsigned int udo_axi_rd_err); +int iSetHPRE_FSM_SHB_CFG_fsm_shb_num(unsigned int ufsm_shb_num); +int iSetHPRE_MEM_CTRL_0_hpre_mem_ctrl_0_bus(unsigned int uhpre_mem_ctrl_0_bus); +int iSetHPRE_MEM_CTRL_1_hpre_mem_ctrl_1_bus(unsigned int uhpre_mem_ctrl_1_bus); +int iSetHPRE_MEM_CTRL_2_hpre_mem_ctrl_2_bus(unsigned int uhpre_mem_ctrl_2_bus); +int iSetHPRE_MEM_CTRL_3_hpre_mem_ctrl_3_bus(unsigned int uhpre_mem_ctrl_3_bus); +int iSetHPRE_MEM_CTRL_4_hpre_mem_ctrl_4_bus(unsigned int uhpre_mem_ctrl_4_bus); +int iSetHPRE_RDCHN_INI_ST_rdchn_ini_st(unsigned int urdchn_ini_st); +int iSetHPRE_ECC1BIT_ERR_CNT_hpre_ecc1bit_err_cnt(unsigned int uhpre_ecc1bit_err_cnt); +int iSetHPRE_ECC2BIT_ERR_CNT_hpre_ecc2bit_err_cnt(unsigned int uhpre_ecc2bit_err_cnt); +int iSetHPRE_PEH_ECO1_hpre_peh_eco1(unsigned int uhpre_peh_eco1); +int iSetHPRE_PEH_ECO2_hpre_peh_eco2(unsigned int uhpre_peh_eco2); +int iSetHPRE_PEH_ECO3_hpre_peh_eco3(unsigned int uhpre_peh_eco3); +int iSetHPRE_PEH_ECO4_hpre_peh_eco4(unsigned int uhpre_peh_eco4); +int iSetHPRE_PEH_ECO5_hpre_peh_eco5(unsigned int uhpre_peh_eco5); +int iSetHPRE_ECO1_hpre_eco1(unsigned int uhpre_eco1); +int iSetHPRE_ECO2_hpre_eco2(unsigned int uhpre_eco2); +int iSetHPRE_ECO3_hpre_eco3(unsigned int uhpre_eco3); +int iSetHPRE_ECO4_hpre_eco4(unsigned int uhpre_eco4); + +/* Define the union csr_cbc_fifo_16k_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_fifo_16k_th : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_16k_th_u; + +/* Define the union csr_saa_ch_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saa_ch_en : 14; /* [13:0] */ + u32 rsv_1 : 2; /* [15:14] */ + u32 cbc_clk_gate_en : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_saa_ch_en_u; + +/* Define the union csr_cbc_core_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_core_rsv : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_core_rsv_u; + +/* Define the union csr_sec_cluster_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_cluster_rsv : 24; /* [23:0] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_cluster_rsv_u; + +/* Define the union csr_sec_alu_addr_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alu_addr_i : 10; /* [9:0] */ + u32 rsv_5 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_alu_addr_i_u; + +/* Define the union csr_sec_alu_rdata_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alu_rdata_o : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_alu_rdata_o_u; + +/* Define the union csr_sec_cluster_saa_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_cluster_saa_cnt : 12; /* [11:0] */ + u32 rsv_7 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_cluster_saa_cnt_u; + +/* Define the union csr_cbc_probe_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_probe_addr : 16; /* [15:0] */ + u32 cbc_probe_cs : 4; /* [19:16] */ + u32 cbc_probe_req : 1; /* [20] */ + u32 rsv_8 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_probe_i_u; + +/* Define the union csr_cbc_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_probe_rdata_u; + +/* Define the union csr_cbc_fifo_probe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dfx_credit_dis_if : 1; /* [0] */ + u32 cbc_dfx_credit_dis_of : 1; /* [1] */ + u32 cbc_probe_bd_dis : 1; /* [2] */ + u32 rsv_9 : 1; /* [3] */ + u32 cbc_probe_ipsec_re : 1; /* [4] */ + u32 cbc_probe_fifo_sel : 1; /* [5] */ + u32 rsv_10 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_probe_ctrl_u; + +/* Define the union csr_cbc_fifo_probe_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_fifo_probe_stat : 16; /* [15:0] */ + u32 cbc_probe_ipsec_if_ept : 1; /* [16] */ + u32 cbc_probe_ipsec_of_ept : 1; /* [17] */ + u32 rsv_11 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_probe_stat_u; + +/* Define the union csr_cbc_bd_err_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_code : 7; /* [6:0] */ + u32 rsv_12 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_code_u; + +/* Define the union csr_cbc_bd_err_code_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_code_clr : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_code_clr_u; + +/* Define the union csr_cbc_bd_err_msk_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_msk_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_msk_l_u; + +/* Define the union csr_cbc_bd_err_msk_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_msk_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_msk_h_u; + +/* Define the union csr_cbc_fifo_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_fifo_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_probe_rdata_u; + +/* Define the union csr_cbc_ecc_err1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_ecc_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_ecc_err1_cnt_u; + +/* Define the union csr_cbc_ecc_err2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_ecc_err2_addr : 11; /* [10:0] */ + u32 rsv_14 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_ecc_err2_addr_u; + +/* Define the union csr_ipsec_cbc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_int_en : 24; /* [23:0] */ + u32 rsv_15 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_int_en_u; + +/* Define the union csr_ipsec_cbc_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_alm : 24; /* [23:0] */ + u32 rsv_16 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_alm_u; + +/* Define the union csr_ipsec_cbc_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta1_u; + +/* Define the union csr_ipsec_cbc_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta2_u; + +/* Define the union csr_ipsec_cbc_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta3_u; + +/* Define the union csr_ipsec_cbc_sta4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta4_u; + +/* Define the union csr_cbc_core_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_core_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_core_cnt_u; + +/* Define the union csr_cbc_dft_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_0_u; + +/* Define the union csr_cbc_dft_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_1_u; + +/* Define the union csr_cbc_dft_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_2_u; + +/* Define the union csr_cbc_dft_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_3_u; + +/* Define the union csr_cbc_dft_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_4 : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_4_u; + +/* Define the union csr_trng_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_tmout_th : 24; /* [23:0] */ + u32 trng_en : 1; /* [24] */ + u32 drop_random_cfg : 1; /* [25] */ + u32 rsv_18 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cbc_fifo_16k_th_u cbc_fifo_16k_th; /* 0 */ + volatile csr_saa_ch_en_u saa_ch_en; /* 4 */ + volatile csr_cbc_core_rsv_u cbc_core_rsv; /* 8 */ + volatile csr_sec_cluster_rsv_u sec_cluster_rsv; /* 10 */ + volatile csr_sec_alu_addr_i_u sec_alu_addr_i; /* 14 */ + volatile csr_sec_alu_rdata_o_u sec_alu_rdata_o; /* 18 */ + volatile csr_sec_cluster_saa_cnt_u sec_cluster_saa_cnt[14]; /* 20 */ + volatile csr_cbc_probe_i_u cbc_probe_i; /* 60 */ + volatile csr_cbc_probe_rdata_u cbc_probe_rdata; /* 64 */ + volatile csr_cbc_fifo_probe_ctrl_u cbc_fifo_probe_ctrl; /* 68 */ + volatile csr_cbc_fifo_probe_stat_u cbc_fifo_probe_stat; /* 6C */ + volatile csr_cbc_bd_err_code_u cbc_bd_err_code; /* A0 */ + volatile csr_cbc_bd_err_code_clr_u cbc_bd_err_code_clr; /* A4 */ + volatile csr_cbc_bd_err_msk_l_u cbc_bd_err_msk_l; /* A8 */ + volatile csr_cbc_bd_err_msk_h_u cbc_bd_err_msk_h; /* AC */ + volatile csr_cbc_fifo_probe_rdata_u cbc_fifo_probe_rdata[8]; /* 70 */ + volatile csr_cbc_ecc_err1_cnt_u cbc_ecc_err1_cnt; /* B0 */ + volatile csr_cbc_ecc_err2_addr_u cbc_ecc_err2_addr; /* B4 */ + volatile csr_ipsec_cbc_int_en_u ipsec_cbc_int_en; /* FC */ + volatile csr_ipsec_cbc_alm_u ipsec_cbc_alm; /* 100 */ + volatile csr_ipsec_cbc_sta1_u ipsec_cbc_sta1; /* 104 */ + volatile csr_ipsec_cbc_sta2_u ipsec_cbc_sta2; /* 108 */ + volatile csr_ipsec_cbc_sta3_u ipsec_cbc_sta3; /* 10C */ + volatile csr_ipsec_cbc_sta4_u ipsec_cbc_sta4; /* 110 */ + volatile csr_cbc_core_cnt_u cbc_core_cnt; /* 114 */ + volatile csr_cbc_dft_mem_ctrl_0_u cbc_dft_mem_ctrl_0; /* 150 */ + volatile csr_cbc_dft_mem_ctrl_1_u cbc_dft_mem_ctrl_1; /* 154 */ + volatile csr_cbc_dft_mem_ctrl_2_u cbc_dft_mem_ctrl_2; /* 158 */ + volatile csr_cbc_dft_mem_ctrl_3_u cbc_dft_mem_ctrl_3; /* 15C */ + volatile csr_cbc_dft_mem_ctrl_4_u cbc_dft_mem_ctrl_4; /* 160 */ + volatile csr_trng_cfg_u trng_cfg; /* 170 */ +} S_ipsec_cbc_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ipsec_cbc_csr */ +extern volatile S_ipsec_cbc_csr_REGS_TYPE *gopipsec_cbc_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCBC_FIFO_16K_TH_cbc_fifo_16k_th(unsigned int ucbc_fifo_16k_th); +int iSetSAA_CH_EN_saa_ch_en(unsigned int usaa_ch_en); +int iSetSAA_CH_EN_cbc_clk_gate_en(unsigned int ucbc_clk_gate_en); +int iSetCBC_CORE_RSV_cbc_core_rsv(unsigned int ucbc_core_rsv); +int iSetSEC_CLUSTER_RSV_sec_cluster_rsv(unsigned int usec_cluster_rsv); +int iSetSEC_ALU_ADDR_I_alu_addr_i(unsigned int ualu_addr_i); +int iSetSEC_ALU_RDATA_O_alu_rdata_o(unsigned int ualu_rdata_o); +int iSetSEC_CLUSTER_SAA_CNT_sec_cluster_saa_cnt(unsigned int usec_cluster_saa_cnt); +int iSetCBC_PROBE_I_cbc_probe_addr(unsigned int ucbc_probe_addr); +int iSetCBC_PROBE_I_cbc_probe_cs(unsigned int ucbc_probe_cs); +int iSetCBC_PROBE_I_cbc_probe_req(unsigned int ucbc_probe_req); +int iSetCBC_PROBE_RDATA_cbc_probe_rdata(unsigned int ucbc_probe_rdata); +int iSetCBC_FIFO_PROBE_CTRL_cbc_dfx_credit_dis_if(unsigned int ucbc_dfx_credit_dis_if); +int iSetCBC_FIFO_PROBE_CTRL_cbc_dfx_credit_dis_of(unsigned int ucbc_dfx_credit_dis_of); +int iSetCBC_FIFO_PROBE_CTRL_cbc_probe_bd_dis(unsigned int ucbc_probe_bd_dis); +int iSetCBC_FIFO_PROBE_CTRL_cbc_probe_ipsec_re(unsigned int ucbc_probe_ipsec_re); +int iSetCBC_FIFO_PROBE_CTRL_cbc_probe_fifo_sel(unsigned int ucbc_probe_fifo_sel); +int iSetCBC_FIFO_PROBE_STAT_cbc_fifo_probe_stat(unsigned int ucbc_fifo_probe_stat); +int iSetCBC_FIFO_PROBE_STAT_cbc_probe_ipsec_if_ept(unsigned int ucbc_probe_ipsec_if_ept); +int iSetCBC_FIFO_PROBE_STAT_cbc_probe_ipsec_of_ept(unsigned int ucbc_probe_ipsec_of_ept); +int iSetCBC_BD_ERR_CODE_cbc_bd_err_code(unsigned int ucbc_bd_err_code); +int iSetCBC_BD_ERR_CODE_CLR_cbc_bd_err_code_clr(unsigned int ucbc_bd_err_code_clr); +int iSetCBC_BD_ERR_MSK_L_cbc_bd_err_msk_l(unsigned int ucbc_bd_err_msk_l); +int iSetCBC_BD_ERR_MSK_H_cbc_bd_err_msk_h(unsigned int ucbc_bd_err_msk_h); +int iSetCBC_FIFO_PROBE_RDATA_cbc_fifo_probe_rdata(unsigned int ucbc_fifo_probe_rdata); +int iSetCBC_ECC_ERR1_CNT_cbc_ecc_err1_cnt(unsigned int ucbc_ecc_err1_cnt); +int iSetCBC_ECC_ERR2_ADDR_cbc_ecc_err2_addr(unsigned int ucbc_ecc_err2_addr); +int iSetIPSEC_CBC_INT_EN_ipsec_cbc_int_en(unsigned int uipsec_cbc_int_en); +int iSetIPSEC_CBC_ALM_ipsec_cbc_alm(unsigned int uipsec_cbc_alm); +int iSetIPSEC_CBC_STA1_ipsec_cbc_sta1(unsigned int uipsec_cbc_sta1); +int iSetIPSEC_CBC_STA2_ipsec_cbc_sta2(unsigned int uipsec_cbc_sta2); +int iSetIPSEC_CBC_STA3_ipsec_cbc_sta3(unsigned int uipsec_cbc_sta3); +int iSetIPSEC_CBC_STA4_ipsec_cbc_sta4(unsigned int uipsec_cbc_sta4); +int iSetCBC_CORE_CNT_cbc_core_cnt(unsigned int ucbc_core_cnt); +int iSetCBC_DFT_MEM_CTRL_0_cbc_dft_mem_ctrl_0(unsigned int ucbc_dft_mem_ctrl_0); +int iSetCBC_DFT_MEM_CTRL_1_cbc_dft_mem_ctrl_1(unsigned int ucbc_dft_mem_ctrl_1); +int iSetCBC_DFT_MEM_CTRL_2_cbc_dft_mem_ctrl_2(unsigned int ucbc_dft_mem_ctrl_2); +int iSetCBC_DFT_MEM_CTRL_3_cbc_dft_mem_ctrl_3(unsigned int ucbc_dft_mem_ctrl_3); +int iSetCBC_DFT_MEM_CTRL_4_cbc_dft_mem_ctrl_4(unsigned int ucbc_dft_mem_ctrl_4); +int iSetTRNG_CFG_trng_tmout_th(unsigned int utrng_tmout_th); +int iSetTRNG_CFG_trng_en(unsigned int utrng_en); +int iSetTRNG_CFG_drop_random_cfg(unsigned int udrop_random_cfg); + +/* Define the union csr_gcm_fifo_16k_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_fifo_16k_th : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_16k_th_u; + +/* Define the union csr_gcm_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_clk_gate_en : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_ctrl_u; + +/* Define the union csr_gcm_core_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_core_rsv : 16; /* [15:0] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_core_rsv_u; + +/* Define the union csr_gcm_cluster_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_cluster_rsv : 24; /* [23:0] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_cluster_rsv_u; + +/* Define the union csr_gcm_probe_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_probe_addr : 16; /* [15:0] */ + u32 gcm_probe_cs : 4; /* [19:16] */ + u32 gcm_probe_req : 1; /* [20] */ + u32 rsv_4 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_probe_i_u; + +/* Define the union csr_gcm_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_probe_rdata_u; + +/* Define the union csr_gcm_fifo_probe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_dfx_credit_dis_if : 1; /* [0] */ + u32 gcm_dfx_credit_dis_of : 1; /* [1] */ + u32 gcm_probe_bd_dis : 1; /* [2] */ + u32 rsv_5 : 1; /* [3] */ + u32 gcm_probe_ipsec_re : 1; /* [4] */ + u32 gcm_probe_fifo_sel : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_probe_ctrl_u; + +/* Define the union csr_gcm_fifo_probe_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_fifo_probe_stat : 16; /* [15:0] */ + u32 gcm_probe_ipsec_if_ept : 1; /* [16] */ + u32 gcm_probe_ipsec_of_ept : 1; /* [17] */ + u32 rsv_7 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_probe_stat_u; + +/* Define the union csr_gcm_fifo_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_fifo_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_probe_rdata_u; + +/* Define the union csr_gcm_bd_err_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_code : 7; /* [6:0] */ + u32 rsv_8 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_code_u; + +/* Define the union csr_gcm_bd_err_code_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_code_clr : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_code_clr_u; + +/* Define the union csr_gcm_bd_err_msk_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_msk_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_msk_l_u; + +/* Define the union csr_gcm_bd_err_msk_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_msk_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_msk_h_u; + +/* Define the union csr_gcm_ecc_err1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_ecc_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_ecc_err1_cnt_u; + +/* Define the union csr_gcm_ecc_err2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_ecc_err2_addr : 12; /* [11:0] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_ecc_err2_addr_u; + +/* Define the union csr_ipsec_gcm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_int_en : 24; /* [23:0] */ + u32 rsv_11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_int_en_u; + +/* Define the union csr_ipsec_gcm_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_alm : 24; /* [23:0] */ + u32 rsv_12 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_alm_u; + +/* Define the union csr_ipsec_gcm_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta1_u; + +/* Define the union csr_ipsec_gcm_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta2_u; + +/* Define the union csr_ipsec_gcm_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta3_u; + +/* Define the union csr_ipsec_gcm_sta4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta4_u; + +/* Define the union csr_ipsec_gcm_sta5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta5_u; + +/* Define the union csr_ipsec_gcm_sta6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta6_u; + +/* Define the union csr_ipsec_gcm_sta7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta7_u; + +/* Define the union csr_ipsec_gcm_sta8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta8_u; + +/* Define the union csr_ipsec_gcm_sta9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta9_u; + +/* Define the union csr_ipsec_gcm_sta10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta10_u; + +/* Define the union csr_ipsec_gcm_sta11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta11_u; + +/* Define the union csr_ipsec_gcm_sta12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta12_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_gcm_fifo_16k_th_u gcm_fifo_16k_th; /* 0 */ + volatile csr_gcm_ctrl_u gcm_ctrl; /* 4 */ + volatile csr_gcm_core_rsv_u gcm_core_rsv; /* 8 */ + volatile csr_gcm_cluster_rsv_u gcm_cluster_rsv; /* 10 */ + volatile csr_gcm_probe_i_u gcm_probe_i; /* 20 */ + volatile csr_gcm_probe_rdata_u gcm_probe_rdata; /* 24 */ + volatile csr_gcm_fifo_probe_ctrl_u gcm_fifo_probe_ctrl; /* 28 */ + volatile csr_gcm_fifo_probe_stat_u gcm_fifo_probe_stat; /* 2C */ + volatile csr_gcm_fifo_probe_rdata_u gcm_fifo_probe_rdata[8]; /* 30 */ + volatile csr_gcm_bd_err_code_u gcm_bd_err_code; /* A0 */ + volatile csr_gcm_bd_err_code_clr_u gcm_bd_err_code_clr; /* A4 */ + volatile csr_gcm_bd_err_msk_l_u gcm_bd_err_msk_l; /* A8 */ + volatile csr_gcm_bd_err_msk_h_u gcm_bd_err_msk_h; /* AC */ + volatile csr_gcm_ecc_err1_cnt_u gcm_ecc_err1_cnt; /* B0 */ + volatile csr_gcm_ecc_err2_addr_u gcm_ecc_err2_addr; /* B4 */ + volatile csr_ipsec_gcm_int_en_u ipsec_gcm_int_en; /* FC */ + volatile csr_ipsec_gcm_alm_u ipsec_gcm_alm; /* 100 */ + volatile csr_ipsec_gcm_sta1_u ipsec_gcm_sta1; /* 104 */ + volatile csr_ipsec_gcm_sta2_u ipsec_gcm_sta2; /* 108 */ + volatile csr_ipsec_gcm_sta3_u ipsec_gcm_sta3; /* 10C */ + volatile csr_ipsec_gcm_sta4_u ipsec_gcm_sta4; /* 110 */ + volatile csr_ipsec_gcm_sta5_u ipsec_gcm_sta5; /* 114 */ + volatile csr_ipsec_gcm_sta6_u ipsec_gcm_sta6; /* 118 */ + volatile csr_ipsec_gcm_sta7_u ipsec_gcm_sta7; /* 11C */ + volatile csr_ipsec_gcm_sta8_u ipsec_gcm_sta8; /* 120 */ + volatile csr_ipsec_gcm_sta9_u ipsec_gcm_sta9; /* 124 */ + volatile csr_ipsec_gcm_sta10_u ipsec_gcm_sta10; /* 128 */ + volatile csr_ipsec_gcm_sta11_u ipsec_gcm_sta11; /* 12C */ + volatile csr_ipsec_gcm_sta12_u ipsec_gcm_sta12; /* 130 */ +} S_ipsec_gcm_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ipsec_gcm_csr */ +extern volatile S_ipsec_gcm_csr_REGS_TYPE *gopipsec_gcm_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetGCM_FIFO_16K_TH_gcm_fifo_16k_th(unsigned int ugcm_fifo_16k_th); +int iSetGCM_CTRL_gcm_clk_gate_en(unsigned int ugcm_clk_gate_en); +int iSetGCM_CORE_RSV_gcm_core_rsv(unsigned int ugcm_core_rsv); +int iSetGCM_CLUSTER_RSV_gcm_cluster_rsv(unsigned int ugcm_cluster_rsv); +int iSetGCM_PROBE_I_gcm_probe_addr(unsigned int ugcm_probe_addr); +int iSetGCM_PROBE_I_gcm_probe_cs(unsigned int ugcm_probe_cs); +int iSetGCM_PROBE_I_gcm_probe_req(unsigned int ugcm_probe_req); +int iSetGCM_PROBE_RDATA_gcm_probe_rdata(unsigned int ugcm_probe_rdata); +int iSetGCM_FIFO_PROBE_CTRL_gcm_dfx_credit_dis_if(unsigned int ugcm_dfx_credit_dis_if); +int iSetGCM_FIFO_PROBE_CTRL_gcm_dfx_credit_dis_of(unsigned int ugcm_dfx_credit_dis_of); +int iSetGCM_FIFO_PROBE_CTRL_gcm_probe_bd_dis(unsigned int ugcm_probe_bd_dis); +int iSetGCM_FIFO_PROBE_CTRL_gcm_probe_ipsec_re(unsigned int ugcm_probe_ipsec_re); +int iSetGCM_FIFO_PROBE_CTRL_gcm_probe_fifo_sel(unsigned int ugcm_probe_fifo_sel); +int iSetGCM_FIFO_PROBE_STAT_gcm_fifo_probe_stat(unsigned int ugcm_fifo_probe_stat); +int iSetGCM_FIFO_PROBE_STAT_gcm_probe_ipsec_if_ept(unsigned int ugcm_probe_ipsec_if_ept); +int iSetGCM_FIFO_PROBE_STAT_gcm_probe_ipsec_of_ept(unsigned int ugcm_probe_ipsec_of_ept); +int iSetGCM_FIFO_PROBE_RDATA_gcm_fifo_probe_rdata(unsigned int ugcm_fifo_probe_rdata); +int iSetGCM_BD_ERR_CODE_gcm_bd_err_code(unsigned int ugcm_bd_err_code); +int iSetGCM_BD_ERR_CODE_CLR_gcm_bd_err_code_clr(unsigned int ugcm_bd_err_code_clr); +int iSetGCM_BD_ERR_MSK_L_gcm_bd_err_msk_l(unsigned int ugcm_bd_err_msk_l); +int iSetGCM_BD_ERR_MSK_H_gcm_bd_err_msk_h(unsigned int ugcm_bd_err_msk_h); +int iSetGCM_ECC_ERR1_CNT_gcm_ecc_err1_cnt(unsigned int ugcm_ecc_err1_cnt); +int iSetGCM_ECC_ERR2_ADDR_gcm_ecc_err2_addr(unsigned int ugcm_ecc_err2_addr); +int iSetIPSEC_GCM_INT_EN_ipsec_gcm_int_en(unsigned int uipsec_gcm_int_en); +int iSetIPSEC_GCM_ALM_ipsec_gcm_alm(unsigned int uipsec_gcm_alm); +int iSetIPSEC_GCM_STA1_ipsec_gcm_sta1(unsigned int uipsec_gcm_sta1); +int iSetIPSEC_GCM_STA2_ipsec_gcm_sta2(unsigned int uipsec_gcm_sta2); +int iSetIPSEC_GCM_STA3_ipsec_gcm_sta3(unsigned int uipsec_gcm_sta3); +int iSetIPSEC_GCM_STA4_ipsec_gcm_sta4(unsigned int uipsec_gcm_sta4); +int iSetIPSEC_GCM_STA5_ipsec_gcm_sta5(unsigned int uipsec_gcm_sta5); +int iSetIPSEC_GCM_STA6_ipsec_gcm_sta6(unsigned int uipsec_gcm_sta6); +int iSetIPSEC_GCM_STA7_ipsec_gcm_sta7(unsigned int uipsec_gcm_sta7); +int iSetIPSEC_GCM_STA8_ipsec_gcm_sta8(unsigned int uipsec_gcm_sta8); +int iSetIPSEC_GCM_STA9_ipsec_gcm_sta9(unsigned int uipsec_gcm_sta9); +int iSetIPSEC_GCM_STA10_ipsec_gcm_sta10(unsigned int uipsec_gcm_sta10); +int iSetIPSEC_GCM_STA11_ipsec_gcm_sta11(unsigned int uipsec_gcm_sta11); +int iSetIPSEC_GCM_STA12_ipsec_gcm_sta12(unsigned int uipsec_gcm_sta12); + +/* Define the union csr_xts_key1_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg7_u; + +/* Define the union csr_xts_key1_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg6_u; + +/* Define the union csr_xts_key1_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg5_u; + +/* Define the union csr_xts_key1_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg4_u; + +/* Define the union csr_xts_key1_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg3_u; + +/* Define the union csr_xts_key1_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg2_u; + +/* Define the union csr_xts_key1_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg1_u; + +/* Define the union csr_xts_key1_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg0_u; + +/* Define the union csr_xts_key2_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg7_u; + +/* Define the union csr_xts_key2_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg6_u; + +/* Define the union csr_xts_key2_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg5_u; + +/* Define the union csr_xts_key2_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg4_u; + +/* Define the union csr_xts_key2_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg3_u; + +/* Define the union csr_xts_key2_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg2_u; + +/* Define the union csr_xts_key2_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg1_u; + +/* Define the union csr_xts_key2_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg0_u; + +/* Define the union csr_xts_key_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key_idx : 9; /* [8:0] */ + u32 rsv_0 : 7; /* [15:9] */ + u32 xts_key12_sel : 2; /* [17:16] */ + u32 xts_key256_sel : 2; /* [19:18] */ + u32 xts_key_opr : 2; /* [21:20] */ + u32 rsv_1 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key_ctrl_u; + +/* Define the union csr_xts_key_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key_crc : 16; /* [15:0] */ + u32 xts_key_opr_busy : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key_stat_u; + +/* Define the union csr_xtx_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_mem_init : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xtx_mem_init_u; + +/* Define the union csr_xts_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_mem_init_done : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_mem_init_done_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_xts_key1_cfg7_u xts_key1_cfg7; /* 0 */ + volatile csr_xts_key1_cfg6_u xts_key1_cfg6; /* 4 */ + volatile csr_xts_key1_cfg5_u xts_key1_cfg5; /* 8 */ + volatile csr_xts_key1_cfg4_u xts_key1_cfg4; /* C */ + volatile csr_xts_key1_cfg3_u xts_key1_cfg3; /* 10 */ + volatile csr_xts_key1_cfg2_u xts_key1_cfg2; /* 14 */ + volatile csr_xts_key1_cfg1_u xts_key1_cfg1; /* 18 */ + volatile csr_xts_key1_cfg0_u xts_key1_cfg0; /* 1C */ + volatile csr_xts_key2_cfg7_u xts_key2_cfg7; /* 20 */ + volatile csr_xts_key2_cfg6_u xts_key2_cfg6; /* 24 */ + volatile csr_xts_key2_cfg5_u xts_key2_cfg5; /* 28 */ + volatile csr_xts_key2_cfg4_u xts_key2_cfg4; /* 2C */ + volatile csr_xts_key2_cfg3_u xts_key2_cfg3; /* 30 */ + volatile csr_xts_key2_cfg2_u xts_key2_cfg2; /* 34 */ + volatile csr_xts_key2_cfg1_u xts_key2_cfg1; /* 38 */ + volatile csr_xts_key2_cfg0_u xts_key2_cfg0; /* 3C */ + volatile csr_xts_key_ctrl_u xts_key_ctrl; /* 40 */ + volatile csr_xts_key_stat_u xts_key_stat; /* 44 */ + volatile csr_xtx_mem_init_u xtx_mem_init; /* 48 */ + volatile csr_xts_mem_init_done_u xts_mem_init_done; /* 4C */ +} S_ipsec_key_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ipsec_key_csr */ +extern volatile S_ipsec_key_csr_REGS_TYPE *gopipsec_key_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetXTS_KEY1_CFG7_xts_key1_cfg7(unsigned int uxts_key1_cfg7); +int iSetXTS_KEY1_CFG6_xts_key1_cfg6(unsigned int uxts_key1_cfg6); +int iSetXTS_KEY1_CFG5_xts_key1_cfg5(unsigned int uxts_key1_cfg5); +int iSetXTS_KEY1_CFG4_xts_key1_cfg4(unsigned int uxts_key1_cfg4); +int iSetXTS_KEY1_CFG3_xts_key1_cfg3(unsigned int uxts_key1_cfg3); +int iSetXTS_KEY1_CFG2_xts_key1_cfg2(unsigned int uxts_key1_cfg2); +int iSetXTS_KEY1_CFG1_xts_key1_cfg1(unsigned int uxts_key1_cfg1); +int iSetXTS_KEY1_CFG0_xts_key1_cfg0(unsigned int uxts_key1_cfg0); +int iSetXTS_KEY2_CFG7_xts_key2_cfg7(unsigned int uxts_key2_cfg7); +int iSetXTS_KEY2_CFG6_xts_key2_cfg6(unsigned int uxts_key2_cfg6); +int iSetXTS_KEY2_CFG5_xts_key2_cfg5(unsigned int uxts_key2_cfg5); +int iSetXTS_KEY2_CFG4_xts_key2_cfg4(unsigned int uxts_key2_cfg4); +int iSetXTS_KEY2_CFG3_xts_key2_cfg3(unsigned int uxts_key2_cfg3); +int iSetXTS_KEY2_CFG2_xts_key2_cfg2(unsigned int uxts_key2_cfg2); +int iSetXTS_KEY2_CFG1_xts_key2_cfg1(unsigned int uxts_key2_cfg1); +int iSetXTS_KEY2_CFG0_xts_key2_cfg0(unsigned int uxts_key2_cfg0); +int iSetXTS_KEY_CTRL_xts_key_idx(unsigned int uxts_key_idx); +int iSetXTS_KEY_CTRL_xts_key12_sel(unsigned int uxts_key12_sel); +int iSetXTS_KEY_CTRL_xts_key256_sel(unsigned int uxts_key256_sel); +int iSetXTS_KEY_CTRL_xts_key_opr(unsigned int uxts_key_opr); +int iSetXTS_KEY_STAT_xts_key_crc(unsigned int uxts_key_crc); +int iSetXTS_KEY_STAT_xts_key_opr_busy(unsigned int uxts_key_opr_busy); +int iSetXTX_MEM_INIT_xts_mem_init(unsigned int uxts_mem_init); +int iSetXTS_MEM_INIT_DONE_xts_mem_init_done(unsigned int uxts_mem_init_done); + +/* Define the union csr_sram_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init : 1; /* [0] */ + u32 reg_lowpower : 1; /* [1] */ + u32 ecc_en : 1; /* [2] */ + u32 multi_ecc_report : 1; /* [3] */ + u32 excl_endian : 1; /* [4] */ + u32 cnt_en : 1; /* [5] */ + u32 decerr_report : 1; /* [6] */ + u32 rsv_0 : 1; /* [7] */ + u32 base_addr_en : 1; /* [8] */ + u32 exinc_en : 1; /* [9] */ + u32 exdec_en : 1; /* [10] */ + u32 mbist_en : 1; /* [11] */ + u32 rdwrap_dis : 1; /* [12] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ctrl_u; + +/* Define the union csr_sram_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_over : 1; /* [0] */ + u32 wrfifo_empty : 1; /* [1] */ + u32 rdfifo_empty : 1; /* [2] */ + u32 wdatfifo_empty : 1; /* [3] */ + u32 pipe_empty : 1; /* [4] */ + u32 resp_empty : 1; /* [5] */ + u32 rsv_3 : 2; /* [7:6] */ + u32 decode_error : 1; /* [8] */ + u32 slave_error : 1; /* [9] */ + u32 ns_error : 1; /* [10] */ + u32 single_ecc : 1; /* [11] */ + u32 multi_ecc : 1; /* [12] */ + u32 buscfg_rderr : 1; /* [13] */ + u32 buscfg_wrerr : 1; /* [14] */ + u32 buscfg_wrcft : 1; /* [15] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_state_u; + +/* Define the union csr_sram_sec_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sec_en : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_sec_ctrl_u; + +/* Define the union csr_sram_sec_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sec_addr : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_sec_addr_u; + +/* Define the union csr_sram_sec_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sec_size : 5; /* [4:0] */ + u32 rsv_7 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_sec_size_u; + +/* Define the union csr_sram_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_base_addr : 13; /* [12:0] */ + u32 rsv_8 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_base_addr_u; + +/* Define the union csr_sram_intmask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_intmsk : 1; /* [0] */ + u32 slverr_intmsk : 1; /* [1] */ + u32 nserr_intmsk : 1; /* [2] */ + u32 ecc_intmsk : 1; /* [3] */ + u32 cnt0_intmsk : 1; /* [4] */ + u32 cnt1_intmsk : 1; /* [5] */ + u32 cnt2_intmsk : 1; /* [6] */ + u32 cnt3_intmsk : 1; /* [7] */ + u32 buserr_intmsk : 1; /* [8] */ + u32 rsv_9 : 3; /* [11:9] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_intmask_u; + +/* Define the union csr_sram_rawint_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_rawint : 1; /* [0] */ + u32 slverr_rawint : 1; /* [1] */ + u32 nserr_rawint : 1; /* [2] */ + u32 ecc_rawint : 1; /* [3] */ + u32 cnt0_rawint : 1; /* [4] */ + u32 cnt1_rawint : 1; /* [5] */ + u32 cnt2_rawint : 1; /* [6] */ + u32 cnt3_rawint : 1; /* [7] */ + u32 buserr_rawint : 1; /* [8] */ + u32 rsv_11 : 3; /* [11:9] */ + u32 rsv_12 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_rawint_u; + +/* Define the union csr_sram_intsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_intst : 1; /* [0] */ + u32 slverr_intst : 1; /* [1] */ + u32 nserr_intst : 1; /* [2] */ + u32 ecc_intst : 1; /* [3] */ + u32 cnt0_intst : 1; /* [4] */ + u32 cnt1_intst : 1; /* [5] */ + u32 cnt2_intst : 1; /* [6] */ + u32 cnt3_intst : 1; /* [7] */ + u32 buserr_intst : 1; /* [8] */ + u32 rsv_13 : 3; /* [11:9] */ + u32 rsv_14 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_intsts_u; + +/* Define the union csr_sram_intclr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_intclr : 1; /* [0] */ + u32 slverr_intclr : 1; /* [1] */ + u32 nserr_intclr : 1; /* [2] */ + u32 ecc_intclr : 1; /* [3] */ + u32 cnt0_intclr : 1; /* [4] */ + u32 cnt1_intclr : 1; /* [5] */ + u32 cnt2_intclr : 1; /* [6] */ + u32 cnt3_intclr : 1; /* [7] */ + u32 buserr_intclr : 1; /* [8] */ + u32 rsv_15 : 3; /* [11:9] */ + u32 rsv_16 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_intclr_u; + +/* Define the union csr_sram_ecc_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bit1_sel : 7; /* [6:0] */ + u32 bit1_en : 1; /* [7] */ + u32 bit2_sel : 7; /* [14:8] */ + u32 bit2_en : 1; /* [15] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ecc_inject_u; + +/* Define the union csr_sram_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinfo_id : 16; /* [15:0] */ + u32 errinfo_len : 6; /* [21:16] */ + u32 errinfo_size : 3; /* [24:22] */ + u32 errinfo_burst : 2; /* [26:25] */ + u32 errinfo_lock : 1; /* [27] */ + u32 errinfo_prot : 3; /* [30:28] */ + u32 errinfo_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_err_info_u; + +/* Define the union csr_sram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_err_addr_u; + +/* Define the union csr_sram_ecc_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eccinfo_vec : 2; /* [1:0] */ + u32 rsv_18 : 2; /* [3:2] */ + u32 eccinfo_addr : 13; /* [16:4] */ + u32 rsv_19 : 7; /* [23:17] */ + u32 eccinfo_single : 1; /* [24] */ + u32 eccinfo_multi : 1; /* [25] */ + u32 rsv_20 : 2; /* [27:26] */ + u32 rsv_21 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ecc_info_u; + +/* Define the union csr_sram_clr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_state : 1; /* [0] */ + u32 clr_ecc1_cnt : 1; /* [1] */ + u32 clr_ecc2_cnt : 1; /* [2] */ + u32 clr_err_info : 1; /* [3] */ + u32 clr_ecc_info : 1; /* [4] */ + u32 clr_cnt0 : 1; /* [5] */ + u32 clr_cnt1 : 1; /* [6] */ + u32 clr_cnt2 : 1; /* [7] */ + u32 clr_cnt3 : 1; /* [8] */ + u32 rsv_22 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_clr_stat_u; + +/* Define the union csr_sram_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 single_ecc_cnt : 16; /* [15:0] */ + u32 multi_ecc_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ecc_cnt_u; + +/* Define the union csr_sram_cnt_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_type : 4; /* [3:0] */ + u32 cnt1_type : 4; /* [7:4] */ + u32 cnt2_type : 4; /* [11:8] */ + u32 cnt3_type : 4; /* [15:12] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt_type_u; + +/* Define the union csr_sram_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt0_u; + +/* Define the union csr_sram_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt1_u; + +/* Define the union csr_sram_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt2_u; + +/* Define the union csr_sram_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt3_u; + +/* Define the union csr_sram_magic_word_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_magic_word_u; + +/* Define the union csr_sram_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hisilicon_version : 12; /* [11:0] */ + u32 sub_version : 4; /* [15:12] */ + u32 main_version : 4; /* [19:16] */ + u32 rsv_25 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_version_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_sram_ctrl_u sram_ctrl; /* 0 */ + volatile csr_sram_state_u sram_state; /* 4 */ + volatile csr_sram_sec_ctrl_u sram_sec_ctrl; /* 10 */ + volatile csr_sram_sec_addr_u sram_sec_addr; /* 14 */ + volatile csr_sram_sec_size_u sram_sec_size; /* 18 */ + volatile csr_sram_base_addr_u sram_base_addr; /* 20 */ + volatile csr_sram_intmask_u sram_intmask; /* 40 */ + volatile csr_sram_rawint_u sram_rawint; /* 44 */ + volatile csr_sram_intsts_u sram_intsts; /* 48 */ + volatile csr_sram_intclr_u sram_intclr; /* 4C */ + volatile csr_sram_ecc_inject_u sram_ecc_inject; /* 60 */ + volatile csr_sram_err_info_u sram_err_info; /* 64 */ + volatile csr_sram_err_addr_u sram_err_addr; /* 68 */ + volatile csr_sram_ecc_info_u sram_ecc_info; /* 6C */ + volatile csr_sram_clr_stat_u sram_clr_stat; /* 70 */ + volatile csr_sram_ecc_cnt_u sram_ecc_cnt; /* 80 */ + volatile csr_sram_cnt_type_u sram_cnt_type; /* 84 */ + volatile csr_sram_cnt0_u sram_cnt0; /* 88 */ + volatile csr_sram_cnt1_u sram_cnt1; /* 8C */ + volatile csr_sram_cnt2_u sram_cnt2; /* 90 */ + volatile csr_sram_cnt3_u sram_cnt3; /* 94 */ + volatile csr_sram_magic_word_u sram_magic_word; /* 7F0 */ + volatile csr_sram_version_u sram_version; /* C10 */ +} S_sram_REGS_TYPE; + +/* Declare the struct pointor of the module sram */ +extern volatile S_sram_REGS_TYPE *gopsramAllReg; + +/* Declare the functions that set the member value */ +int iSetSRAM_CTRL_init(unsigned int uinit); +int iSetSRAM_CTRL_reg_lowpower(unsigned int ureg_lowpower); +int iSetSRAM_CTRL_ecc_en(unsigned int uecc_en); +int iSetSRAM_CTRL_multi_ecc_report(unsigned int umulti_ecc_report); +int iSetSRAM_CTRL_excl_endian(unsigned int uexcl_endian); +int iSetSRAM_CTRL_cnt_en(unsigned int ucnt_en); +int iSetSRAM_CTRL_decerr_report(unsigned int udecerr_report); +int iSetSRAM_CTRL_base_addr_en(unsigned int ubase_addr_en); +int iSetSRAM_CTRL_exinc_en(unsigned int uexinc_en); +int iSetSRAM_CTRL_exdec_en(unsigned int uexdec_en); +int iSetSRAM_CTRL_mbist_en(unsigned int umbist_en); +int iSetSRAM_CTRL_rdwrap_dis(unsigned int urdwrap_dis); +int iSetSRAM_STATE_init_over(unsigned int uinit_over); +int iSetSRAM_STATE_wrfifo_empty(unsigned int uwrfifo_empty); +int iSetSRAM_STATE_rdfifo_empty(unsigned int urdfifo_empty); +int iSetSRAM_STATE_wdatfifo_empty(unsigned int uwdatfifo_empty); +int iSetSRAM_STATE_pipe_empty(unsigned int upipe_empty); +int iSetSRAM_STATE_resp_empty(unsigned int uresp_empty); +int iSetSRAM_STATE_decode_error(unsigned int udecode_error); +int iSetSRAM_STATE_slave_error(unsigned int uslave_error); +int iSetSRAM_STATE_ns_error(unsigned int uns_error); +int iSetSRAM_STATE_single_ecc(unsigned int usingle_ecc); +int iSetSRAM_STATE_multi_ecc(unsigned int umulti_ecc); +int iSetSRAM_STATE_buscfg_rderr(unsigned int ubuscfg_rderr); +int iSetSRAM_STATE_buscfg_wrerr(unsigned int ubuscfg_wrerr); +int iSetSRAM_STATE_buscfg_wrcft(unsigned int ubuscfg_wrcft); +int iSetSRAM_SEC_CTRL_reg_sec_en(unsigned int ureg_sec_en); +int iSetSRAM_SEC_ADDR_reg_sec_addr(unsigned int ureg_sec_addr); +int iSetSRAM_SEC_SIZE_reg_sec_size(unsigned int ureg_sec_size); +int iSetSRAM_BASE_ADDR_reg_base_addr(unsigned int ureg_base_addr); +int iSetSRAM_INTMASK_decerr_intmsk(unsigned int udecerr_intmsk); +int iSetSRAM_INTMASK_slverr_intmsk(unsigned int uslverr_intmsk); +int iSetSRAM_INTMASK_nserr_intmsk(unsigned int unserr_intmsk); +int iSetSRAM_INTMASK_ecc_intmsk(unsigned int uecc_intmsk); +int iSetSRAM_INTMASK_cnt0_intmsk(unsigned int ucnt0_intmsk); +int iSetSRAM_INTMASK_cnt1_intmsk(unsigned int ucnt1_intmsk); +int iSetSRAM_INTMASK_cnt2_intmsk(unsigned int ucnt2_intmsk); +int iSetSRAM_INTMASK_cnt3_intmsk(unsigned int ucnt3_intmsk); +int iSetSRAM_INTMASK_buserr_intmsk(unsigned int ubuserr_intmsk); +int iSetSRAM_RAWINT_decerr_rawint(unsigned int udecerr_rawint); +int iSetSRAM_RAWINT_slverr_rawint(unsigned int uslverr_rawint); +int iSetSRAM_RAWINT_nserr_rawint(unsigned int unserr_rawint); +int iSetSRAM_RAWINT_ecc_rawint(unsigned int uecc_rawint); +int iSetSRAM_RAWINT_cnt0_rawint(unsigned int ucnt0_rawint); +int iSetSRAM_RAWINT_cnt1_rawint(unsigned int ucnt1_rawint); +int iSetSRAM_RAWINT_cnt2_rawint(unsigned int ucnt2_rawint); +int iSetSRAM_RAWINT_cnt3_rawint(unsigned int ucnt3_rawint); +int iSetSRAM_RAWINT_buserr_rawint(unsigned int ubuserr_rawint); +int iSetSRAM_INTSTS_decerr_intst(unsigned int udecerr_intst); +int iSetSRAM_INTSTS_slverr_intst(unsigned int uslverr_intst); +int iSetSRAM_INTSTS_nserr_intst(unsigned int unserr_intst); +int iSetSRAM_INTSTS_ecc_intst(unsigned int uecc_intst); +int iSetSRAM_INTSTS_cnt0_intst(unsigned int ucnt0_intst); +int iSetSRAM_INTSTS_cnt1_intst(unsigned int ucnt1_intst); +int iSetSRAM_INTSTS_cnt2_intst(unsigned int ucnt2_intst); +int iSetSRAM_INTSTS_cnt3_intst(unsigned int ucnt3_intst); +int iSetSRAM_INTSTS_buserr_intst(unsigned int ubuserr_intst); +int iSetSRAM_INTCLR_decerr_intclr(unsigned int udecerr_intclr); +int iSetSRAM_INTCLR_slverr_intclr(unsigned int uslverr_intclr); +int iSetSRAM_INTCLR_nserr_intclr(unsigned int unserr_intclr); +int iSetSRAM_INTCLR_ecc_intclr(unsigned int uecc_intclr); +int iSetSRAM_INTCLR_cnt0_intclr(unsigned int ucnt0_intclr); +int iSetSRAM_INTCLR_cnt1_intclr(unsigned int ucnt1_intclr); +int iSetSRAM_INTCLR_cnt2_intclr(unsigned int ucnt2_intclr); +int iSetSRAM_INTCLR_cnt3_intclr(unsigned int ucnt3_intclr); +int iSetSRAM_INTCLR_buserr_intclr(unsigned int ubuserr_intclr); +int iSetSRAM_ECC_INJECT_bit1_sel(unsigned int ubit1_sel); +int iSetSRAM_ECC_INJECT_bit1_en(unsigned int ubit1_en); +int iSetSRAM_ECC_INJECT_bit2_sel(unsigned int ubit2_sel); +int iSetSRAM_ECC_INJECT_bit2_en(unsigned int ubit2_en); +int iSetSRAM_ERR_INFO_errinfo_id(unsigned int uerrinfo_id); +int iSetSRAM_ERR_INFO_errinfo_len(unsigned int uerrinfo_len); +int iSetSRAM_ERR_INFO_errinfo_size(unsigned int uerrinfo_size); +int iSetSRAM_ERR_INFO_errinfo_burst(unsigned int uerrinfo_burst); +int iSetSRAM_ERR_INFO_errinfo_lock(unsigned int uerrinfo_lock); +int iSetSRAM_ERR_INFO_errinfo_prot(unsigned int uerrinfo_prot); +int iSetSRAM_ERR_INFO_errinfo_en(unsigned int uerrinfo_en); +int iSetSRAM_ERR_ADDR_ecc_addr(unsigned int uecc_addr); +int iSetSRAM_ECC_INFO_eccinfo_vec(unsigned int ueccinfo_vec); +int iSetSRAM_ECC_INFO_eccinfo_addr(unsigned int ueccinfo_addr); +int iSetSRAM_ECC_INFO_eccinfo_single(unsigned int ueccinfo_single); +int iSetSRAM_ECC_INFO_eccinfo_multi(unsigned int ueccinfo_multi); +int iSetSRAM_CLR_STAT_clr_state(unsigned int uclr_state); +int iSetSRAM_CLR_STAT_clr_ecc1_cnt(unsigned int uclr_ecc1_cnt); +int iSetSRAM_CLR_STAT_clr_ecc2_cnt(unsigned int uclr_ecc2_cnt); +int iSetSRAM_CLR_STAT_clr_err_info(unsigned int uclr_err_info); +int iSetSRAM_CLR_STAT_clr_ecc_info(unsigned int uclr_ecc_info); +int iSetSRAM_CLR_STAT_clr_cnt0(unsigned int uclr_cnt0); +int iSetSRAM_CLR_STAT_clr_cnt1(unsigned int uclr_cnt1); +int iSetSRAM_CLR_STAT_clr_cnt2(unsigned int uclr_cnt2); +int iSetSRAM_CLR_STAT_clr_cnt3(unsigned int uclr_cnt3); +int iSetSRAM_ECC_CNT_single_ecc_cnt(unsigned int usingle_ecc_cnt); +int iSetSRAM_ECC_CNT_multi_ecc_cnt(unsigned int umulti_ecc_cnt); +int iSetSRAM_CNT_TYPE_cnt0_type(unsigned int ucnt0_type); +int iSetSRAM_CNT_TYPE_cnt1_type(unsigned int ucnt1_type); +int iSetSRAM_CNT_TYPE_cnt2_type(unsigned int ucnt2_type); +int iSetSRAM_CNT_TYPE_cnt3_type(unsigned int ucnt3_type); +int iSetSRAM_CNT0_dfx_cnt0(unsigned int udfx_cnt0); +int iSetSRAM_CNT1_dfx_cnt1(unsigned int udfx_cnt1); +int iSetSRAM_CNT2_dfx_cnt2(unsigned int udfx_cnt2); +int iSetSRAM_CNT3_dfx_cnt3(unsigned int udfx_cnt3); + +int iSetSRAM_VERSION_hisilicon_version(unsigned int uhisilicon_version); +int iSetSRAM_VERSION_sub_version(unsigned int usub_version); +int iSetSRAM_VERSION_main_version(unsigned int umain_version); + +/* Define the union csr_trng_output_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_0_u; + +/* Define the union csr_trng_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_1_u; + +/* Define the union csr_trng_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_2_u; + +/* Define the union csr_trng_output_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_3_u; + +/* Define the union csr_trng_input_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_0_u; + +/* Define the union csr_trng_input_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_1_u; + +/* Define the union csr_trng_input_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_2_u; + +/* Define the union csr_trng_input_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_3_u; + +/* Define the union csr_trng_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 shutdown_oflo : 1; /* [1] */ + u32 stuck_out : 1; /* [2] */ + u32 noise_fail : 1; /* [3] */ + u32 run_fail : 1; /* [4] */ + u32 long_run_fail : 1; /* [5] */ + u32 poker_fail : 1; /* [6] */ + u32 monobit_fail : 1; /* [7] */ + u32 test_ready : 1; /* [8] */ + u32 stuck_nrbg : 1; /* [9] */ + u32 reseed_ai : 1; /* [10] */ + u32 rsv_0 : 2; /* [12:11] */ + u32 repcnt_fail : 1; /* [13] */ + u32 aprop_fail : 1; /* [14] */ + u32 test_stuck_out : 1; /* [15] */ + u32 blocks_available : 8; /* [23:16] */ + u32 blocks_thresh : 7; /* [30:24] */ + u32 need_clock : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_status_u; + +/* Define the union csr_trng_intack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready_ack : 1; /* [0] */ + u32 shutdown_oflo_ack : 1; /* [1] */ + u32 stuck_out_ack : 1; /* [2] */ + u32 noise_fail_ack : 1; /* [3] */ + u32 run_fail_ack : 1; /* [4] */ + u32 long_run_fail_ack : 1; /* [5] */ + u32 poker_fail_ack : 1; /* [6] */ + u32 monobit_fail_ack : 1; /* [7] */ + u32 test_ready_ack : 1; /* [8] */ + u32 stuck_nrbg_ack : 1; /* [9] */ + u32 open_read_gate : 3; /* [12:10] */ + u32 repcnt_fail_ack : 1; /* [13] */ + u32 aprop_fail_ack : 1; /* [14] */ + u32 test_stuck_out : 1; /* [15] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_intack_u; + +/* Define the union csr_trng_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready_mask : 1; /* [0] */ + u32 shutdown_oflo_mask : 1; /* [1] */ + u32 stuck_out_mask : 1; /* [2] */ + u32 noise_fail_mask : 1; /* [3] */ + u32 run_fail_mask : 1; /* [4] */ + u32 long_run_fail_mask : 1; /* [5] */ + u32 poker_fail_mask : 1; /* [6] */ + u32 monobit_fail_mask : 1; /* [7] */ + u32 test_mode : 1; /* [8] */ + u32 stuck_nrbg_mask : 1; /* [9] */ + u32 enable_trng : 1; /* [10] */ + u32 no_whitening : 1; /* [11] */ + u32 drbg_en : 1; /* [12] */ + u32 repcnt_fail_mask : 1; /* [13] */ + u32 aprop_fail_mask : 1; /* [14] */ + u32 re_seed : 1; /* [15] */ + u32 request_data : 1; /* [16] */ + u32 request_hold : 1; /* [17] */ + u32 rsv_2 : 2; /* [19:18] */ + u32 data_blocks : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_control_u; + +/* Define the union csr_trng_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 noise_blocks : 5; /* [4:0] */ + u32 use_startup_bits : 1; /* [5] */ + u32 scale : 2; /* [7:6] */ + u32 sample_div : 4; /* [11:8] */ + u32 read_timeout : 4; /* [15:12] */ + u32 sample_cycles : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_config_u; + +/* Define the union csr_trng_alarmcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alarm_threshold : 8; /* [7:0] */ + u32 rsv_3 : 7; /* [14:8] */ + u32 stall_run_poker : 1; /* [15] */ + u32 shutdown_threshold : 5; /* [20:16] */ + u32 rsv_4 : 2; /* [22:21] */ + u32 shutdown_fatal : 1; /* [23] */ + u32 shutdown_count : 6; /* [29:24] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_alarmcnt_u; + +/* Define the union csr_trng_froenable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_enables : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_froenable_u; + +/* Define the union csr_trng_frodetune_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_detunes : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_frodetune_u; + +/* Define the union csr_trng_alarmmask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_alarmmasks : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_alarmmask_u; + +/* Define the union csr_trng_alarmstop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_alarmstops : 8; /* [7:0] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_alarmstop_u; + +/* Define the union csr_trng_raw_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shift_reg_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_raw_l_u; + +/* Define the union csr_trng_raw_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shift_reg_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_raw_h_u; + +/* Define the union csr_trng_spb_tests_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 repcnt : 6; /* [5:0] */ + u32 repcnt_value_h : 2; /* [7:6] */ + u32 aprop_64 : 6; /* [13:8] */ + u32 aprop_64_value_h : 2; /* [15:14] */ + u32 aprop_512 : 8; /* [23:16] */ + u32 aprop_512_h : 4; /* [27:24] */ + u32 show_counters : 1; /* [28] */ + u32 show_values : 1; /* [29] */ + u32 aprop_64_fail : 1; /* [30] */ + u32 aprop_512_fail : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_spb_tests_u; + +/* Define the union csr_trng_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sample_cyc_cnt : 16; /* [15:0] */ + u32 noise_blk_cnt : 5; /* [20:16] */ + u32 rsv_10 : 3; /* [23:21] */ + u32 sample_cyc_ext : 6; /* [29:24] */ + u32 rsv_11 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_count_u; + +/* Define the union csr_trng_cond_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_0_u; + +/* Define the union csr_trng_cond_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_1_u; + +/* Define the union csr_trng_cond_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_2_u; + +/* Define the union csr_trng_cond_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_3_u; + +/* Define the union csr_trng_cond_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_4_u; + +/* Define the union csr_trng_cond_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_5_u; + +/* Define the union csr_trng_cond_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_6_u; + +/* Define the union csr_trng_cond_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_7_u; + +/* Define the union csr_trng_key_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_0_u; + +/* Define the union csr_trng_key_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_1_u; + +/* Define the union csr_trng_key_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_2_u; + +/* Define the union csr_trng_key_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_3_u; + +/* Define the union csr_trng_key_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_4_u; + +/* Define the union csr_trng_key_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_5_u; + +/* Define the union csr_trng_key_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_6_u; + +/* Define the union csr_trng_key_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_7_u; + +/* Define the union csr_trng_ps_ai_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_0_u; + +/* Define the union csr_trng_ps_ai_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_1_u; + +/* Define the union csr_trng_ps_ai_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_2_u; + +/* Define the union csr_trng_ps_ai_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_3_u; + +/* Define the union csr_trng_ps_ai_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_4_u; + +/* Define the union csr_trng_ps_ai_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_5_u; + +/* Define the union csr_trng_ps_ai_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_6_u; + +/* Define the union csr_trng_ps_ai_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_7_u; + +/* Define the union csr_trng_ps_ai_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_287_256 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_8_u; + +/* Define the union csr_trng_ps_ai_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_319_288 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_9_u; + +/* Define the union csr_trng_ps_ai_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_351_320 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_10_u; + +/* Define the union csr_trng_ps_ai_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_383_352 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_11_u; + +/* Define the union csr_trng_run_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_test_count : 15; /* [14:0] */ + u32 run_state : 1; /* [15] */ + u32 run_length_count : 6; /* [21:16] */ + u32 rsv_12 : 2; /* [23:22] */ + u32 run_length_max : 6; /* [29:24] */ + u32 rsv_13 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_cnt_u; + +/* Define the union csr_trng_run_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_1_count_zeroes : 12; /* [11:0] */ + u32 rsv_14 : 4; /* [15:12] */ + u32 run_1_count_ones : 12; /* [27:16] */ + u32 rsv_15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_1_u; + +/* Define the union csr_trng_run_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_2_count_zeroes : 12; /* [11:0] */ + u32 rsv_16 : 4; /* [15:12] */ + u32 run_2_count_ones : 12; /* [27:16] */ + u32 rsv_17 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_2_u; + +/* Define the union csr_trng_run_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_3_count_zeroes : 10; /* [9:0] */ + u32 rsv_18 : 6; /* [15:10] */ + u32 run_3_count_ones : 10; /* [25:16] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_3_u; + +/* Define the union csr_trng_run_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_4_count_zeroes : 9; /* [8:0] */ + u32 rsv_20 : 7; /* [15:9] */ + u32 run_4_count_ones : 9; /* [24:16] */ + u32 rsv_21 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_4_u; + +/* Define the union csr_trng_run_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_5_count_zeroes : 8; /* [7:0] */ + u32 rsv_22 : 8; /* [15:8] */ + u32 run_5_count_ones : 8; /* [23:16] */ + u32 rsv_23 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_5_u; + +/* Define the union csr_trng_run_6_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_6_up_count_zeroes : 8; /* [7:0] */ + u32 rsv_24 : 8; /* [15:8] */ + u32 run_6_up_count_ones : 8; /* [23:16] */ + u32 rsv_25 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_6_up_u; + +/* Define the union csr_trng_monobitcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 monobit_count_l : 17; /* [16:0] */ + u32 monobit_count_h : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_monobitcnt_u; + +/* Define the union csr_trng_poker_3_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_0 : 8; /* [7:0] */ + u32 poker_count_1 : 8; /* [15:8] */ + u32 poker_count_2 : 8; /* [23:16] */ + u32 poker_count_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_3_0_u; + +/* Define the union csr_trng_poker_7_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_4 : 8; /* [7:0] */ + u32 poker_count_5 : 8; /* [15:8] */ + u32 poker_count_6 : 8; /* [23:16] */ + u32 poker_count_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_7_4_u; + +/* Define the union csr_trng_poker_b_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_8 : 8; /* [7:0] */ + u32 poker_count_9 : 8; /* [15:8] */ + u32 poker_count_a : 8; /* [23:16] */ + u32 poker_count_b : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_b_8_u; + +/* Define the union csr_trng_poker_f_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_c : 8; /* [7:0] */ + u32 poker_count_d : 8; /* [15:8] */ + u32 poker_count_e : 8; /* [23:16] */ + u32 poker_count_f : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_f_c_u; + +/* Define the union csr_trng_test_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 test_en_out : 1; /* [0] */ + u32 test_patt_fro : 1; /* [1] */ + u32 test_patt_det : 1; /* [2] */ + u32 test_shiftreg : 1; /* [3] */ + u32 cont_poker : 1; /* [4] */ + u32 test_known_noise : 1; /* [5] */ + u32 test_aes_256 : 1; /* [6] */ + u32 test_sp_800_90 : 1; /* [7] */ + u32 test_select : 5; /* [12:8] */ + u32 test_noise : 1; /* [13] */ + u32 test_spb : 1; /* [14] */ + u32 test_cond_func : 1; /* [15] */ + u32 test_pattern : 12; /* [27:16] */ + u32 fro_testin2_not : 1; /* [28] */ + u32 fro_testin3 : 1; /* [29] */ + u32 fro_testin4 : 1; /* [30] */ + u32 test_irq : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_test_u; + +/* Define the union csr_trng_blockcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_26 : 4; /* [3:0] */ + u32 block_count : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_blockcnt_u; + +/* Define the union csr_trng_options_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 post_processor_option : 3; /* [2:0] */ + u32 rsv_27 : 3; /* [5:3] */ + u32 nr_of_fros : 6; /* [11:6] */ + u32 buffer_size : 3; /* [14:12] */ + u32 rsv_28 : 1; /* [15] */ + u32 pr_test : 1; /* [16] */ + u32 conditioner_option : 2; /* [18:17] */ + u32 detuning_option : 2; /* [20:19] */ + u32 aprop_512 : 1; /* [21] */ + u32 rsv_29 : 1; /* [22] */ + u32 auto_detune : 1; /* [23] */ + u32 detune_counter : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_options_u; + +/* Define the union csr_trng_eip_rev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 basic_eip_number : 8; /* [7:0] */ + u32 complement_of_basic_eip_number : 8; /* [15:8] */ + u32 hw_patch_level : 4; /* [19:16] */ + u32 minor_hw_revision : 4; /* [23:20] */ + u32 major_hw_revision : 4; /* [27:24] */ + u32 rsv_30 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_eip_rev_u; + +/* Define the union csr_trng_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_mode : 1; /* [0] */ + u32 sec_interface_disable : 1; /* [1] */ + u32 km_interface_disable : 1; /* [2] */ + u32 jtagauth_interface_disable : 1; /* [3] */ + u32 user_interface_disable : 1; /* [4] */ + u32 auto_reseed_enable : 1; /* [5] */ + u32 hpre_interface_disable : 1; /* [6] */ + u32 rsv_31 : 1; /* [7] */ + u32 mem_ctrl : 8; /* [15:8] */ + u32 block_cnt : 12; /* [27:16] */ + u32 rsv_32 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ctrl0_u; + +/* Define the union csr_trng_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 check_reseed_time_gap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ctrl1_u; + +/* Define the union csr_trng_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_cpi_int_index : 24; /* [23:0] */ + u32 rsv_33 : 3; /* [26:24] */ + u32 trng_issue_enable : 1; /* [27] */ + u32 trng_int_issue : 1; /* [28] */ + u32 rsv_34 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_vector_u; + +/* Define the union csr_rng_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_en : 1; /* [0] */ + u32 rng_seed_sel : 1; /* [1] */ + u32 rng_ring_en : 1; /* [2] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_ctrl_u; + +/* Define the union csr_rng_seed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_seed : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_seed_u; + +/* Define the union csr_trng_fsm_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pproc_state : 7; /* [6:0] */ + u32 rsv_36 : 1; /* [7] */ + u32 fsm_state : 3; /* [10:8] */ + u32 rsv_37 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_fsm_st_u; + +/* Define the union csr_rng_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_num_u; + +/* Define the union csr_rng_phy_seed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_phy_seed : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_phy_seed_u; + +/* Define the union csr_rng_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_reload_err : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_err_u; + +/* Define the union csr_trng_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_39 : 1; /* [0] */ + u32 shut_down_oflo_intset : 1; /* [1] */ + u32 stuck_out_intset : 1; /* [2] */ + u32 noise_fail_intset : 1; /* [3] */ + u32 run_fail_intset : 1; /* [4] */ + u32 long_run_fail_intset : 1; /* [5] */ + u32 poker_fail_intset : 1; /* [6] */ + u32 monobit_fail_intset : 1; /* [7] */ + u32 rsv_40 : 1; /* [8] */ + u32 stuck_nrbg_intset : 1; /* [9] */ + u32 rsv_41 : 3; /* [12:10] */ + u32 repcnt_fail_intset : 1; /* [13] */ + u32 aprop_fail_intset : 1; /* [14] */ + u32 rsv_42 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_set_u; + +/* Define the union csr_trng_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_int_en : 2; /* [1:0] */ + u32 rsv_43 : 14; /* [15:2] */ + u32 trng_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_en_u; + +/* Define the union csr_trng_int_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_int_data : 2; /* [1:0] */ + u32 rsv_44 : 14; /* [15:2] */ + u32 trng_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_st_u; + +/* Define the union csr_trng_ran_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data0_u; + +/* Define the union csr_trng_ran_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data1_u; + +/* Define the union csr_trng_ran_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data2_u; + +/* Define the union csr_trng_ran_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_trng_output_0_u trng_output_0; /* 0 */ + volatile csr_trng_output_1_u trng_output_1; /* 4 */ + volatile csr_trng_output_2_u trng_output_2; /* 8 */ + volatile csr_trng_output_3_u trng_output_3; /* C */ + volatile csr_trng_input_0_u trng_input_0; /* 0 */ + volatile csr_trng_input_1_u trng_input_1; /* 4 */ + volatile csr_trng_input_2_u trng_input_2; /* 8 */ + volatile csr_trng_input_3_u trng_input_3; /* C */ + volatile csr_trng_status_u trng_status; /* 10 */ + volatile csr_trng_intack_u trng_intack; /* 10 */ + volatile csr_trng_control_u trng_control; /* 14 */ + volatile csr_trng_config_u trng_config; /* 18 */ + volatile csr_trng_alarmcnt_u trng_alarmcnt; /* 1C */ + volatile csr_trng_froenable_u trng_froenable; /* 20 */ + volatile csr_trng_frodetune_u trng_frodetune; /* 24 */ + volatile csr_trng_alarmmask_u trng_alarmmask; /* 28 */ + volatile csr_trng_alarmstop_u trng_alarmstop; /* 2C */ + volatile csr_trng_raw_l_u trng_raw_l; /* 30 */ + volatile csr_trng_raw_h_u trng_raw_h; /* 34 */ + volatile csr_trng_spb_tests_u trng_spb_tests; /* 38 */ + volatile csr_trng_count_u trng_count; /* 3C */ + volatile csr_trng_cond_0_u trng_cond_0; /* 40 */ + volatile csr_trng_cond_1_u trng_cond_1; /* 44 */ + volatile csr_trng_cond_2_u trng_cond_2; /* 48 */ + volatile csr_trng_cond_3_u trng_cond_3; /* 4C */ + volatile csr_trng_cond_4_u trng_cond_4; /* 50 */ + volatile csr_trng_cond_5_u trng_cond_5; /* 54 */ + volatile csr_trng_cond_6_u trng_cond_6; /* 58 */ + volatile csr_trng_cond_7_u trng_cond_7; /* 5C */ + volatile csr_trng_key_0_u trng_key_0; /* 40 */ + volatile csr_trng_key_1_u trng_key_1; /* 44 */ + volatile csr_trng_key_2_u trng_key_2; /* 48 */ + volatile csr_trng_key_3_u trng_key_3; /* 4C */ + volatile csr_trng_key_4_u trng_key_4; /* 50 */ + volatile csr_trng_key_5_u trng_key_5; /* 54 */ + volatile csr_trng_key_6_u trng_key_6; /* 58 */ + volatile csr_trng_key_7_u trng_key_7; /* 5C */ + volatile csr_trng_ps_ai_0_u trng_ps_ai_0; /* 40 */ + volatile csr_trng_ps_ai_1_u trng_ps_ai_1; /* 44 */ + volatile csr_trng_ps_ai_2_u trng_ps_ai_2; /* 48 */ + volatile csr_trng_ps_ai_3_u trng_ps_ai_3; /* 4C */ + volatile csr_trng_ps_ai_4_u trng_ps_ai_4; /* 50 */ + volatile csr_trng_ps_ai_5_u trng_ps_ai_5; /* 54 */ + volatile csr_trng_ps_ai_6_u trng_ps_ai_6; /* 58 */ + volatile csr_trng_ps_ai_7_u trng_ps_ai_7; /* 5C */ + volatile csr_trng_ps_ai_8_u trng_ps_ai_8; /* 60 */ + volatile csr_trng_ps_ai_9_u trng_ps_ai_9; /* 64 */ + volatile csr_trng_ps_ai_10_u trng_ps_ai_10; /* 68 */ + volatile csr_trng_ps_ai_11_u trng_ps_ai_11; /* 6C */ + volatile csr_trng_run_cnt_u trng_run_cnt; /* 40 */ + volatile csr_trng_run_1_u trng_run_1; /* 44 */ + volatile csr_trng_run_2_u trng_run_2; /* 48 */ + volatile csr_trng_run_3_u trng_run_3; /* 4C */ + volatile csr_trng_run_4_u trng_run_4; /* 50 */ + volatile csr_trng_run_5_u trng_run_5; /* 54 */ + volatile csr_trng_run_6_up_u trng_run_6_up; /* 58 */ + volatile csr_trng_monobitcnt_u trng_monobitcnt; /* 5C */ + volatile csr_trng_poker_3_0_u trng_poker_3_0; /* 60 */ + volatile csr_trng_poker_7_4_u trng_poker_7_4; /* 64 */ + volatile csr_trng_poker_b_8_u trng_poker_b_8; /* 68 */ + volatile csr_trng_poker_f_c_u trng_poker_f_c; /* 6C */ + volatile csr_trng_test_u trng_test; /* 70 */ + volatile csr_trng_blockcnt_u trng_blockcnt; /* 74 */ + volatile csr_trng_options_u trng_options; /* 78 */ + volatile csr_trng_eip_rev_u trng_eip_rev; /* 7C */ + volatile csr_trng_ctrl0_u trng_ctrl0; /* C0 */ + volatile csr_trng_ctrl1_u trng_ctrl1; /* C4 */ + volatile csr_trng_int_vector_u trng_int_vector; /* C8 */ + volatile csr_rng_ctrl_u rng_ctrl; /* CC */ + volatile csr_rng_seed_u rng_seed; /* D0 */ + volatile csr_trng_fsm_st_u trng_fsm_st; /* D4 */ + volatile csr_rng_num_u rng_num; /* D8 */ + volatile csr_rng_phy_seed_u rng_phy_seed; /* DC */ + volatile csr_rng_err_u rng_err; /* E0 */ + volatile csr_trng_int_set_u trng_int_set; /* E4 */ + volatile csr_trng_int_en_u trng_int_en; /* E8 */ + volatile csr_trng_int_st_u trng_int_st; /* EC */ + volatile csr_trng_ran_data0_u trng_ran_data0; /* F0 */ + volatile csr_trng_ran_data1_u trng_ran_data1; /* F4 */ + volatile csr_trng_ran_data2_u trng_ran_data2; /* F8 */ + volatile csr_trng_ran_data3_u trng_ran_data3; /* FC */ +} S_trng_csr_REGS_TYPE; + +/* Declare the struct pointor of the module trng_csr */ +extern volatile S_trng_csr_REGS_TYPE *goptrng_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetTRNG_OUTPUT_0_trng_output_31_0(unsigned int utrng_output_31_0); +int iSetTRNG_OUTPUT_1_trng_output_63_32(unsigned int utrng_output_63_32); +int iSetTRNG_OUTPUT_2_trng_output_95_64(unsigned int utrng_output_95_64); +int iSetTRNG_OUTPUT_3_trng_output_127_96(unsigned int utrng_output_127_96); +int iSetTRNG_INPUT_0_trng_input_31_0(unsigned int utrng_input_31_0); +int iSetTRNG_INPUT_1_trng_input_63_32(unsigned int utrng_input_63_32); +int iSetTRNG_INPUT_2_trng_input_95_64(unsigned int utrng_input_95_64); +int iSetTRNG_INPUT_3_trng_input_127_96(unsigned int utrng_input_127_96); +int iSetTRNG_STATUS_ready(unsigned int uready); +int iSetTRNG_STATUS_shutdown_oflo(unsigned int ushutdown_oflo); +int iSetTRNG_STATUS_stuck_out(unsigned int ustuck_out); +int iSetTRNG_STATUS_noise_fail(unsigned int unoise_fail); +int iSetTRNG_STATUS_run_fail(unsigned int urun_fail); +int iSetTRNG_STATUS_long_run_fail(unsigned int ulong_run_fail); +int iSetTRNG_STATUS_poker_fail(unsigned int upoker_fail); +int iSetTRNG_STATUS_monobit_fail(unsigned int umonobit_fail); +int iSetTRNG_STATUS_test_ready(unsigned int utest_ready); +int iSetTRNG_STATUS_stuck_nrbg(unsigned int ustuck_nrbg); +int iSetTRNG_STATUS_reseed_ai(unsigned int ureseed_ai); +int iSetTRNG_STATUS_repcnt_fail(unsigned int urepcnt_fail); +int iSetTRNG_STATUS_aprop_fail(unsigned int uaprop_fail); +int iSetTRNG_STATUS_test_stuck_out(unsigned int utest_stuck_out); +int iSetTRNG_STATUS_blocks_available(unsigned int ublocks_available); +int iSetTRNG_STATUS_blocks_thresh(unsigned int ublocks_thresh); +int iSetTRNG_STATUS_need_clock(unsigned int uneed_clock); +int iSetTRNG_INTACK_ready_ack(unsigned int uready_ack); +int iSetTRNG_INTACK_shutdown_oflo_ack(unsigned int ushutdown_oflo_ack); +int iSetTRNG_INTACK_stuck_out_ack(unsigned int ustuck_out_ack); +int iSetTRNG_INTACK_noise_fail_ack(unsigned int unoise_fail_ack); +int iSetTRNG_INTACK_run_fail_ack(unsigned int urun_fail_ack); +int iSetTRNG_INTACK_long_run_fail_ack(unsigned int ulong_run_fail_ack); +int iSetTRNG_INTACK_poker_fail_ack(unsigned int upoker_fail_ack); +int iSetTRNG_INTACK_monobit_fail_ack(unsigned int umonobit_fail_ack); +int iSetTRNG_INTACK_test_ready_ack(unsigned int utest_ready_ack); +int iSetTRNG_INTACK_stuck_nrbg_ack(unsigned int ustuck_nrbg_ack); +int iSetTRNG_INTACK_open_read_gate(unsigned int uopen_read_gate); +int iSetTRNG_INTACK_repcnt_fail_ack(unsigned int urepcnt_fail_ack); +int iSetTRNG_INTACK_aprop_fail_ack(unsigned int uaprop_fail_ack); +int iSetTRNG_INTACK_test_stuck_out(unsigned int utest_stuck_out); +int iSetTRNG_CONTROL_ready_mask(unsigned int uready_mask); +int iSetTRNG_CONTROL_shutdown_oflo_mask(unsigned int ushutdown_oflo_mask); +int iSetTRNG_CONTROL_stuck_out_mask(unsigned int ustuck_out_mask); +int iSetTRNG_CONTROL_noise_fail_mask(unsigned int unoise_fail_mask); +int iSetTRNG_CONTROL_run_fail_mask(unsigned int urun_fail_mask); +int iSetTRNG_CONTROL_long_run_fail_mask(unsigned int ulong_run_fail_mask); +int iSetTRNG_CONTROL_poker_fail_mask(unsigned int upoker_fail_mask); +int iSetTRNG_CONTROL_monobit_fail_mask(unsigned int umonobit_fail_mask); +int iSetTRNG_CONTROL_test_mode(unsigned int utest_mode); +int iSetTRNG_CONTROL_stuck_nrbg_mask(unsigned int ustuck_nrbg_mask); +int iSetTRNG_CONTROL_enable_trng(unsigned int uenable_trng); +int iSetTRNG_CONTROL_no_whitening(unsigned int uno_whitening); +int iSetTRNG_CONTROL_drbg_en(unsigned int udrbg_en); +int iSetTRNG_CONTROL_repcnt_fail_mask(unsigned int urepcnt_fail_mask); +int iSetTRNG_CONTROL_aprop_fail_mask(unsigned int uaprop_fail_mask); +int iSetTRNG_CONTROL_re_seed(unsigned int ure_seed); +int iSetTRNG_CONTROL_request_data(unsigned int urequest_data); +int iSetTRNG_CONTROL_request_hold(unsigned int urequest_hold); +int iSetTRNG_CONTROL_data_blocks(unsigned int udata_blocks); +int iSetTRNG_CONFIG_noise_blocks(unsigned int unoise_blocks); +int iSetTRNG_CONFIG_use_startup_bits(unsigned int uuse_startup_bits); +int iSetTRNG_CONFIG_scale(unsigned int uscale); +int iSetTRNG_CONFIG_sample_div(unsigned int usample_div); +int iSetTRNG_CONFIG_read_timeout(unsigned int uread_timeout); +int iSetTRNG_CONFIG_sample_cycles(unsigned int usample_cycles); +int iSetTRNG_ALARMCNT_alarm_threshold(unsigned int ualarm_threshold); +int iSetTRNG_ALARMCNT_stall_run_poker(unsigned int ustall_run_poker); +int iSetTRNG_ALARMCNT_shutdown_threshold(unsigned int ushutdown_threshold); +int iSetTRNG_ALARMCNT_shutdown_fatal(unsigned int ushutdown_fatal); +int iSetTRNG_ALARMCNT_shutdown_count(unsigned int ushutdown_count); +int iSetTRNG_FROENABLE_fro_enables(unsigned int ufro_enables); +int iSetTRNG_FRODETUNE_fro_detunes(unsigned int ufro_detunes); +int iSetTRNG_ALARMMASK_fro_alarmmasks(unsigned int ufro_alarmmasks); +int iSetTRNG_ALARMSTOP_fro_alarmstops(unsigned int ufro_alarmstops); +int iSetTRNG_RAW_L_shift_reg_31_0(unsigned int ushift_reg_31_0); +int iSetTRNG_RAW_H_shift_reg_63_32(unsigned int ushift_reg_63_32); +int iSetTRNG_SPB_TESTS_repcnt(unsigned int urepcnt); +int iSetTRNG_SPB_TESTS_repcnt_value_h(unsigned int urepcnt_value_h); +int iSetTRNG_SPB_TESTS_aprop_64(unsigned int uaprop_64); +int iSetTRNG_SPB_TESTS_aprop_64_value_h(unsigned int uaprop_64_value_h); +int iSetTRNG_SPB_TESTS_aprop_512(unsigned int uaprop_512); +int iSetTRNG_SPB_TESTS_aprop_512_h(unsigned int uaprop_512_h); +int iSetTRNG_SPB_TESTS_show_counters(unsigned int ushow_counters); +int iSetTRNG_SPB_TESTS_show_values(unsigned int ushow_values); +int iSetTRNG_SPB_TESTS_aprop_64_fail(unsigned int uaprop_64_fail); +int iSetTRNG_SPB_TESTS_aprop_512_fail(unsigned int uaprop_512_fail); +int iSetTRNG_COUNT_sample_cyc_cnt(unsigned int usample_cyc_cnt); +int iSetTRNG_COUNT_noise_blk_cnt(unsigned int unoise_blk_cnt); +int iSetTRNG_COUNT_sample_cyc_ext(unsigned int usample_cyc_ext); +int iSetTRNG_COND_0_cf_output_31_0(unsigned int ucf_output_31_0); +int iSetTRNG_COND_1_cf_output_63_32(unsigned int ucf_output_63_32); +int iSetTRNG_COND_2_cf_output_95_64(unsigned int ucf_output_95_64); +int iSetTRNG_COND_3_cf_output_127_96(unsigned int ucf_output_127_96); +int iSetTRNG_COND_4_cf_output_159_128(unsigned int ucf_output_159_128); +int iSetTRNG_COND_5_cf_output_191_160(unsigned int ucf_output_191_160); +int iSetTRNG_COND_6_cf_output_223_192(unsigned int ucf_output_223_192); +int iSetTRNG_COND_7_cf_output_255_224(unsigned int ucf_output_255_224); +int iSetTRNG_KEY_0_key_31_0(unsigned int ukey_31_0); +int iSetTRNG_KEY_1_key_63_32(unsigned int ukey_63_32); +int iSetTRNG_KEY_2_key_95_64(unsigned int ukey_95_64); +int iSetTRNG_KEY_3_key_127_96(unsigned int ukey_127_96); +int iSetTRNG_KEY_4_key_159_128(unsigned int ukey_159_128); +int iSetTRNG_KEY_5_key_191_160(unsigned int ukey_191_160); +int iSetTRNG_KEY_6_key_223_192(unsigned int ukey_223_192); +int iSetTRNG_KEY_7_key_255_224(unsigned int ukey_255_224); +int iSetTRNG_PS_AI_0_vector_31_0(unsigned int uvector_31_0); +int iSetTRNG_PS_AI_1_vector_63_32(unsigned int uvector_63_32); +int iSetTRNG_PS_AI_2_vector_95_64(unsigned int uvector_95_64); +int iSetTRNG_PS_AI_3_vector_127_96(unsigned int uvector_127_96); +int iSetTRNG_PS_AI_4_vector_159_128(unsigned int uvector_159_128); +int iSetTRNG_PS_AI_5_vector_191_160(unsigned int uvector_191_160); +int iSetTRNG_PS_AI_6_vector_223_192(unsigned int uvector_223_192); +int iSetTRNG_PS_AI_7_vector_255_224(unsigned int uvector_255_224); +int iSetTRNG_PS_AI_8_vector_287_256(unsigned int uvector_287_256); +int iSetTRNG_PS_AI_9_vector_319_288(unsigned int uvector_319_288); +int iSetTRNG_PS_AI_10_vector_351_320(unsigned int uvector_351_320); +int iSetTRNG_PS_AI_11_vector_383_352(unsigned int uvector_383_352); +int iSetTRNG_RUN_CNT_run_test_count(unsigned int urun_test_count); +int iSetTRNG_RUN_CNT_run_state(unsigned int urun_state); +int iSetTRNG_RUN_CNT_run_length_count(unsigned int urun_length_count); +int iSetTRNG_RUN_CNT_run_length_max(unsigned int urun_length_max); +int iSetTRNG_RUN_1_run_1_count_zeroes(unsigned int urun_1_count_zeroes); +int iSetTRNG_RUN_1_run_1_count_ones(unsigned int urun_1_count_ones); +int iSetTRNG_RUN_2_run_2_count_zeroes(unsigned int urun_2_count_zeroes); +int iSetTRNG_RUN_2_run_2_count_ones(unsigned int urun_2_count_ones); +int iSetTRNG_RUN_3_run_3_count_zeroes(unsigned int urun_3_count_zeroes); +int iSetTRNG_RUN_3_run_3_count_ones(unsigned int urun_3_count_ones); +int iSetTRNG_RUN_4_run_4_count_zeroes(unsigned int urun_4_count_zeroes); +int iSetTRNG_RUN_4_run_4_count_ones(unsigned int urun_4_count_ones); +int iSetTRNG_RUN_5_run_5_count_zeroes(unsigned int urun_5_count_zeroes); +int iSetTRNG_RUN_5_run_5_count_ones(unsigned int urun_5_count_ones); +int iSetTRNG_RUN_6_UP_run_6_up_count_zeroes(unsigned int urun_6_up_count_zeroes); +int iSetTRNG_RUN_6_UP_run_6_up_count_ones(unsigned int urun_6_up_count_ones); +int iSetTRNG_MONOBITCNT_monobit_count_l(unsigned int umonobit_count_l); +int iSetTRNG_MONOBITCNT_monobit_count_h(unsigned int umonobit_count_h); +int iSetTRNG_POKER_3_0_poker_count_0(unsigned int upoker_count_0); +int iSetTRNG_POKER_3_0_poker_count_1(unsigned int upoker_count_1); +int iSetTRNG_POKER_3_0_poker_count_2(unsigned int upoker_count_2); +int iSetTRNG_POKER_3_0_poker_count_3(unsigned int upoker_count_3); +int iSetTRNG_POKER_7_4_poker_count_4(unsigned int upoker_count_4); +int iSetTRNG_POKER_7_4_poker_count_5(unsigned int upoker_count_5); +int iSetTRNG_POKER_7_4_poker_count_6(unsigned int upoker_count_6); +int iSetTRNG_POKER_7_4_poker_count_7(unsigned int upoker_count_7); +int iSetTRNG_POKER_B_8_poker_count_8(unsigned int upoker_count_8); +int iSetTRNG_POKER_B_8_poker_count_9(unsigned int upoker_count_9); +int iSetTRNG_POKER_B_8_poker_count_a(unsigned int upoker_count_a); +int iSetTRNG_POKER_B_8_poker_count_b(unsigned int upoker_count_b); +int iSetTRNG_POKER_F_C_poker_count_c(unsigned int upoker_count_c); +int iSetTRNG_POKER_F_C_poker_count_d(unsigned int upoker_count_d); +int iSetTRNG_POKER_F_C_poker_count_e(unsigned int upoker_count_e); +int iSetTRNG_POKER_F_C_poker_count_f(unsigned int upoker_count_f); +int iSetTRNG_TEST_test_en_out(unsigned int utest_en_out); +int iSetTRNG_TEST_test_patt_fro(unsigned int utest_patt_fro); +int iSetTRNG_TEST_test_patt_det(unsigned int utest_patt_det); +int iSetTRNG_TEST_test_shiftreg(unsigned int utest_shiftreg); +int iSetTRNG_TEST_cont_poker(unsigned int ucont_poker); +int iSetTRNG_TEST_test_known_noise(unsigned int utest_known_noise); +int iSetTRNG_TEST_test_aes_256(unsigned int utest_aes_256); +int iSetTRNG_TEST_test_sp_800_90(unsigned int utest_sp_800_90); +int iSetTRNG_TEST_test_select(unsigned int utest_select); +int iSetTRNG_TEST_test_noise(unsigned int utest_noise); +int iSetTRNG_TEST_test_spb(unsigned int utest_spb); +int iSetTRNG_TEST_test_cond_func(unsigned int utest_cond_func); +int iSetTRNG_TEST_test_pattern(unsigned int utest_pattern); +int iSetTRNG_TEST_fro_testin2_not(unsigned int ufro_testin2_not); +int iSetTRNG_TEST_fro_testin3(unsigned int ufro_testin3); +int iSetTRNG_TEST_fro_testin4(unsigned int ufro_testin4); +int iSetTRNG_TEST_test_irq(unsigned int utest_irq); +int iSetTRNG_BLOCKCNT_block_count(unsigned int ublock_count); +int iSetTRNG_OPTIONS_post_processor_option(unsigned int upost_processor_option); +int iSetTRNG_OPTIONS_nr_of_fros(unsigned int unr_of_fros); +int iSetTRNG_OPTIONS_buffer_size(unsigned int ubuffer_size); +int iSetTRNG_OPTIONS_pr_test(unsigned int upr_test); +int iSetTRNG_OPTIONS_conditioner_option(unsigned int uconditioner_option); +int iSetTRNG_OPTIONS_detuning_option(unsigned int udetuning_option); +int iSetTRNG_OPTIONS_aprop_512(unsigned int uaprop_512); +int iSetTRNG_OPTIONS_auto_detune(unsigned int uauto_detune); +int iSetTRNG_OPTIONS_detune_counter(unsigned int udetune_counter); +int iSetTRNG_EIP_REV_basic_eip_number(unsigned int ubasic_eip_number); +int iSetTRNG_EIP_REV_complement_of_basic_eip_number(unsigned int ucomplement_of_basic_eip_number); +int iSetTRNG_EIP_REV_hw_patch_level(unsigned int uhw_patch_level); +int iSetTRNG_EIP_REV_minor_hw_revision(unsigned int uminor_hw_revision); +int iSetTRNG_EIP_REV_major_hw_revision(unsigned int umajor_hw_revision); +int iSetTRNG_CTRL0_trng_mode(unsigned int utrng_mode); +int iSetTRNG_CTRL0_sec_interface_disable(unsigned int usec_interface_disable); +int iSetTRNG_CTRL0_km_interface_disable(unsigned int ukm_interface_disable); +int iSetTRNG_CTRL0_jtagauth_interface_disable(unsigned int ujtagauth_interface_disable); +int iSetTRNG_CTRL0_user_interface_disable(unsigned int uuser_interface_disable); +int iSetTRNG_CTRL0_auto_reseed_enable(unsigned int uauto_reseed_enable); +int iSetTRNG_CTRL0_hpre_interface_disable(unsigned int uhpre_interface_disable); +int iSetTRNG_CTRL0_mem_ctrl(unsigned int umem_ctrl); +int iSetTRNG_CTRL0_block_cnt(unsigned int ublock_cnt); +int iSetTRNG_CTRL1_check_reseed_time_gap(unsigned int ucheck_reseed_time_gap); +int iSetTRNG_INT_VECTOR_trng_cpi_int_index(unsigned int utrng_cpi_int_index); +int iSetTRNG_INT_VECTOR_trng_issue_enable(unsigned int utrng_issue_enable); +int iSetTRNG_INT_VECTOR_trng_int_issue(unsigned int utrng_int_issue); +int iSetRNG_CTRL_rng_en(unsigned int urng_en); +int iSetRNG_CTRL_rng_seed_sel(unsigned int urng_seed_sel); +int iSetRNG_CTRL_rng_ring_en(unsigned int urng_ring_en); +int iSetRNG_SEED_rng_seed(unsigned int urng_seed); +int iSetTRNG_FSM_ST_pproc_state(unsigned int upproc_state); +int iSetTRNG_FSM_ST_fsm_state(unsigned int ufsm_state); +int iSetRNG_NUM_rng_num(unsigned int urng_num); +int iSetRNG_PHY_SEED_rng_phy_seed(unsigned int urng_phy_seed); +int iSetRNG_ERR_rng_reload_err(unsigned int urng_reload_err); +int iSetTRNG_INT_SET_shut_down_oflo_intset(unsigned int ushut_down_oflo_intset); +int iSetTRNG_INT_SET_stuck_out_intset(unsigned int ustuck_out_intset); +int iSetTRNG_INT_SET_noise_fail_intset(unsigned int unoise_fail_intset); +int iSetTRNG_INT_SET_run_fail_intset(unsigned int urun_fail_intset); +int iSetTRNG_INT_SET_long_run_fail_intset(unsigned int ulong_run_fail_intset); +int iSetTRNG_INT_SET_poker_fail_intset(unsigned int upoker_fail_intset); +int iSetTRNG_INT_SET_monobit_fail_intset(unsigned int umonobit_fail_intset); +int iSetTRNG_INT_SET_stuck_nrbg_intset(unsigned int ustuck_nrbg_intset); +int iSetTRNG_INT_SET_repcnt_fail_intset(unsigned int urepcnt_fail_intset); +int iSetTRNG_INT_SET_aprop_fail_intset(unsigned int uaprop_fail_intset); +int iSetTRNG_INT_EN_trng_int_en(unsigned int utrng_int_en); +int iSetTRNG_INT_EN_trng_program_csr_id(unsigned int utrng_program_csr_id); +int iSetTRNG_INT_ST_trng_int_data(unsigned int utrng_int_data); +int iSetTRNG_INT_ST_trng_program_csr_id_ro(unsigned int utrng_program_csr_id_ro); +int iSetTRNG_RAN_DATA0_trng_random_data0(unsigned int utrng_random_data0); +int iSetTRNG_RAN_DATA1_trng_random_data1(unsigned int utrng_random_data1); +int iSetTRNG_RAN_DATA2_trng_random_data2(unsigned int utrng_random_data2); +int iSetTRNG_RAN_DATA3_trng_random_data3(unsigned int utrng_random_data3); + + +#endif // XXX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_reg_offset.h new file mode 100644 index 000000000..2050cdd14 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_reg_offset.h @@ -0,0 +1,1181 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : crypto_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/5/26 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/26 16:19:41 Create file +// ****************************************************************************** + +#ifndef CRYPTO_REG_OFFSET_H +#define CRYPTO_REG_OFFSET_H + +/* CRYPTORX_INOUT_CSR Base address of Module's Register */ +#define CSR_CRYPTORX_INOUT_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* CRYPTORX_INOUT_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_VERSION_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_INT_VECTOR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x60) /* 中断向量 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_INT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x64) /* 中断状态 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_INT_EN_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x68) /* 中断屏蔽 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_LP_TOP_ERR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x6C) /* CRX环回顶层错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_LP_GCM_ERR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x70) /* CRX环回GCM通道错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_LP_CBC_ERR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x74) /* CRX环回CBC通道错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_XTS_ERR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x78) /* CRX XTS通道错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TMOUT_CFG_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x80) /* CRX通道超时阈值 */ +#define CSR_CRYPTORX_INOUT_CSR_IPSEC_RX_CRG_CFG_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x84) /* IPSEC_RX时钟复位配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_MEM_INIT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x100) /* CRYPTORX MEM初始化使能寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_MEM_INIT_DONE_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x104) /* CRYPTORX MEM初始化状态寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_MEM_CTRL_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x108) /* CRYPTORX MEM配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_REG_CNT_CLR_CE_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x10C) /* CRYPTORX 中CNT_CYC读清控制信号配置寄存器。 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CHX_CFG_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x120) /* CRX通道SAA配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CREDIT_O_CFG_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x128) /* CRX出口CREDIT配置寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CREDIT2_O_CFG_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x12C) /* CRX出口CREDIT2配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CTRL_RSV_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x130) /* 控制保留寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_STAT_RSV_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x134) /* 状态保留寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_EPT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x138) /* CRYPTORX顶层空状态寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_FULL_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x13C) /* CRYPTOTX顶层满状态寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x150) /* CRYPTORX DFT_MEM_CTRL寄存器0 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x154) /* CRYPTORX DFT_MEM_CTRL寄存器1 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x158) /* CRYPTORX DFT_MEM_CTRL寄存器2 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_3_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x15C) /* CRYPTORX DFT_MEM_CTRL寄存器3 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_4_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x160) /* CRYPTORX DFT_MEM_CTRL寄存器4 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_ERR1_CNT_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x170) /* CRYPTORX顶层ECC1比特错误计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_ECC_ERR2_ADDR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x174) /* CRYPTORX顶层ECC2比特错误地址寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TOP_INT_EN_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x178) /* CRYPTORX顶层中断使能寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TOP_ALM_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x17C) /* CRYPTORX顶层告警寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CREDIT_ERR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x200) /* CRYPTO入口CREDIT ERR寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_INN_CREDIT_I_ERR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x204) /* CRYPTO入口INN CREDIT ERR寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_PRE_0_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x310) /* 入口SOF流量统计寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_PRE_1_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x314) /* 入口SOF流量统计寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_PRE_2_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x318) /* 入口SOF流量统计寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CHK_ERR_CNT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x320) /* 校验错误统计计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TFC_PAD_ERR_CNT_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x324) /* TFC_PAD删除失败统计计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_OTHER_ERR_CNT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x328) /* CRX其余错误统计计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_0_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x210) /* 入口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_1_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x214) /* 入口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_2_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x218) /* 入口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_O_0_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x220) /* 出口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_O_1_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x224) /* 出口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_O_2_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x228) /* 出口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_IF_I_CNT_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x280) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_IF_I_CNT_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x284) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_IF_I_CNT_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x288) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_I_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2A0) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_I_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2A4) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_I_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2A8) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_O_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2C0) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_O_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2C4) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_O_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2C8) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CMB_LEN_O_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2E0) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CMB_LEN_O_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2E4) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CMB_LEN_O_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2E8) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ + +/* CRYPTOTX_INOUT_CSR Base address of Module's Register */ +#define CSR_CRYPTOTX_INOUT_CSR_BASE (0x4000) + +/* **************************************************************************** */ +/* CRYPTOTX_INOUT_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRYPTOTX_INOUT_CSR_CTX_VERSION_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INT_VECTOR_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x60) /* 中断向量 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x64) /* 中断状态 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INT_EN_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x68) /* 中断屏蔽 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TOP_ERR_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x6C) /* CTX环回顶层错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_GCM_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x70) /* CTX环回GCM通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_CBC_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x74) /* CTX环回CBC通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_XTS_EC_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x78) /* CTX直通XTS_EC通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_XTS_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x7C) /* CTX直通XTS通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TMOUT_CFG_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x80) /* CTX通道超时阈值 */ +#define CSR_CRYPTOTX_INOUT_CSR_IPSEC_TX_CRG_CFG_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x84) /* IPSEC_TX时钟复位配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_MEM_INIT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x100) /* CRYPTOTX MEM初始化使能寄存器 \ + */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_MEM_INIT_DONE_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x104) /* CRYPTOTX MEM初始化状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_MEM_CTRL_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x108) /* CRYPTOTX MEM配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_REG_CNT_CLR_CE_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x10C) /* CRYPTOTX 中CNT_CYC读清控制信号配置寄存器。 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_CHX_CFG_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x120) /* 环回通道SAA配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_CHX_CFG_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x124) /* 直通通道SAA映射寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_NECCH_CREDIT_O_CFG_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x128) /* 非EC通道出口CREDIT配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_ECCH_CREDIT_O_CFG_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x12C) /* EC通道出口CREDIT配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_CTRL_RSV_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x130) /* 控制保留寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_STAT_RSV_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x134) /* 状态保留寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_EPT_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x140) /* CRYPTOTX环回通道顶层空状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_FULL_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x144) /* CRYPTOTX环回通道顶层满状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_EPT_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x148) /* CRYPTOTX直通通道顶层空状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_FULL_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x14C) /* CRYPTOTX直通通道顶层满状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x150) /* CRYPTOTX DFT_MEM_CTRL寄存器0 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x154) /* CRYPTOTX DFT_MEM_CTRL寄存器1 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x158) /* CRYPTOTX DFT_MEM_CTRL寄存器2 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x15C) /* CRYPTOTX DFT_MEM_CTRL寄存器3 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x160) /* CRYPTOTX DFT_MEM_CTRL寄存器4 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TOP_INT_EN_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x178) /* CRYPTOTX顶层中断使能寄存器 \ + */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TOP_ALM_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x17C) /* CRYPTOTX顶层告警寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_CREDIT_ERR_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x200) /* CRYPTO入口CREDIT ERR寄存器 \ + */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INN_CREDIT_I_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x204) /* CRYPTO入口INN CREDIT ERR寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_PRE_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x310) /* 环回通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_PRE_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x314) /* 环回通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_PRE_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x318) /* 环回通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x320) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x324) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x328) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x32C) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x330) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BD_ERR_CNT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x340) /* BD错误统计计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LEN_ERR_CNT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x344) /* 报文长度错误统计计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x210) /* 环回通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x214) /* 环回通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x218) /* 环回通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x220) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x224) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x228) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x22C) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x230) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x240) /* 环回通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x244) /* 环回通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x248) /* 环回通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x260) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x264) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x268) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x26C) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x270) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x280) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x284) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x288) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x28C) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x290) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2A0) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2A4) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2A8) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2AC) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2B0) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2C0) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2C4) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2C8) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2CC) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2D0) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2E0) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2E4) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2E8) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2EC) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2F0) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ + +/* CRX_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CRX_IPSEC_GCM_CSR_BASE (0x3000) + +/* **************************************************************************** */ +/* CRX_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 */ + +/* CTX_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CTX_IPSEC_GCM_CSR_BASE (0x6000) + +/* **************************************************************************** */ +/* CTX_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 */ + +/* CRX_IPSEC_CBC_CSR Base address of Module's Register */ +#define CSR_CRX_IPSEC_CBC_CSR_BASE (0x3400) + +/* **************************************************************************** */ +/* CRX_IPSEC_CBC_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_16K_TH_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x0) /* CBC通道出口整包缓存FIFO将满阈值 */ +#define CSR_CRX_IPSEC_CBC_CSR_SAA_CH_EN_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x4) /* CBC通道内部子通道使能 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_CORE_RSV_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x8) /* CBC_CORE保留寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_RSV_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x10) /* SEC_CLUSTER模块保留寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_ALU_ADDR_I_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x14) /* CLUSTER DFX地址输入寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_ALU_RDATA_O_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x18) /* CLUSTER DFX数据输出寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_0_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x20) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_1_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x24) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_2_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x28) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_3_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x2C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_4_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x30) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_5_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x34) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_6_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x38) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_7_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x3C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_8_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x40) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_9_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x44) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_10_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x48) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_11_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x4C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_12_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x50) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_13_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x54) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_PROBE_I_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x60) /* CBC内部MEMPROBE输入信号 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_PROBE_RDATA_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x64) /* CBC内部MEM PROBE输出信号 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_CTRL_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x68) /* CBC通道FIFO PROBE控制寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_STAT_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x6C) /* CBC通道FIFO PROBE状态寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xA0) /* CBC通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_CLR_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xA4) /* CBC通道BD_ERR历史状态清除寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_L_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xA8) /* CBC通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_H_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xAC) /* CBC通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_0_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x70) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_1_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x74) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_2_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x78) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_3_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x7C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_4_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x80) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_5_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x84) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_6_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x88) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_7_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x8C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_ECC_ERR1_CNT_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xB0) /* CBC通道ECC1比特错误计数器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_ECC_ERR2_ADDR_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xB4) /* CBC通道ECC2比特错误地址寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_INT_EN_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xFC) /* CBC通道中断使能寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_ALM_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x100) /* CBC通道告警寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA1_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x104) /* CBC通道状态寄存器1 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA2_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x108) /* CBC通道状态寄存器2 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA3_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x10C) /* CBC通道状态寄存器3 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA4_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x110) /* CBC通道状态寄存器4 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_CORE_CNT_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x114) /* CBC通道尾数统计计数器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_0_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x150) /* CRYPTOBC DFT_MEM_CTRL寄存器0 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_1_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x154) /* CRYPTOBC DFT_MEM_CTRL寄存器1 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_2_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x158) /* CRYPTOBC DFT_MEM_CTRL寄存器2 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_3_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x15C) /* CRYPTOBC DFT_MEM_CTRL寄存器3 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_4_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x160) /* CRYPTOBC DFT_MEM_CTRL寄存器4 */ +#define CSR_CRX_IPSEC_CBC_CSR_TRNG_CFG_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x170) /* 随机数配置寄存器 */ + +/* CTX_IPSEC_CBC_CSR Base address of Module's Register */ +#define CSR_CTX_IPSEC_CBC_CSR_BASE (0x6400) + +/* **************************************************************************** */ +/* CTX_IPSEC_CBC_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_16K_TH_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x0) /* CBC通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_IPSEC_CBC_CSR_SAA_CH_EN_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x4) /* CBC通道内部子通道使能 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_CORE_RSV_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x8) /* CBC_CORE保留寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_RSV_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x10) /* SEC_CLUSTER模块保留寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_ALU_ADDR_I_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x14) /* CLUSTER DFX地址输入寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_ALU_RDATA_O_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x18) /* CLUSTER DFX数据输出寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_0_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x20) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_1_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x24) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_2_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x28) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_3_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x2C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_4_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x30) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_5_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x34) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_6_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x38) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_7_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x3C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_8_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x40) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_9_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x44) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_10_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x48) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_11_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x4C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_12_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x50) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_13_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x54) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_PROBE_I_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x60) /* CBC内部MEMPROBE输入信号 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_PROBE_RDATA_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x64) /* CBC内部MEM PROBE输出信号 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x68) /* CBC通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_STAT_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x6C) /* CBC通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xA0) /* CBC通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xA4) /* CBC通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_L_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xA8) /* CBC通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_H_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xAC) /* CBC通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x70) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x74) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x78) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x7C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x80) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x84) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x88) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x8C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_ECC_ERR1_CNT_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xB0) /* CBC通道ECC1比特错误计数器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_ECC_ERR2_ADDR_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xB4) /* CBC通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_INT_EN_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xFC) /* CBC通道中断使能寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_ALM_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x100) /* CBC通道告警寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA1_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x104) /* CBC通道状态寄存器1 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA2_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x108) /* CBC通道状态寄存器2 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA3_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x10C) /* CBC通道状态寄存器3 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA4_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x110) /* CBC通道状态寄存器4 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_CORE_CNT_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x114) /* CBC通道尾数统计计数器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_0_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x150) /* CRYPTOBC DFT_MEM_CTRL寄存器0 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_1_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x154) /* CRYPTOBC DFT_MEM_CTRL寄存器1 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_2_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x158) /* CRYPTOBC DFT_MEM_CTRL寄存器2 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_3_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x15C) /* CRYPTOBC DFT_MEM_CTRL寄存器3 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_4_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x160) /* CRYPTOBC DFT_MEM_CTRL寄存器4 */ +#define CSR_CTX_IPSEC_CBC_CSR_TRNG_CFG_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x170) /* 随机数配置寄存器 */ + +/* CRX_XTS_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_BASE (0x3800) + +/* **************************************************************************** */ +/* CRX_XTS_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 \ + */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 \ + */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 \ + */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 \ + */ + +/* CTX_XTS_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_BASE (0x6C00) + +/* **************************************************************************** */ +/* CTX_XTS_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 \ + */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 \ + */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 \ + */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 \ + */ + +/* CTX_XTS_EC_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE (0x6800) + +/* **************************************************************************** */ +/* CTX_XTS_EC_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 \ + */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_PROBE_I_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 */ + +/* CRX_XTS_IPSEC_KEY_CSR Base address of Module's Register */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_BASE (0x3A00) + +/* **************************************************************************** */ +/* CRX_XTS_IPSEC_KEY_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG7_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x0) /* XTS_KEY1配置寄存器7 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG6_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x4) /* XTS_KEY1配置寄存器6 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG5_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x8) /* XTS_KEY1配置寄存器5 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG4_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0xC) /* XTS_KEY1配置寄存器4 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG3_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x10) /* XTS_KEY1配置寄存器3 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG2_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x14) /* XTS_KEY1配置寄存器2 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG1_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x18) /* XTS_KEY1配置寄存器1 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG0_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x1C) /* XTS_KEY1配置寄存器0 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG7_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x20) /* XTS_KEY2配置寄存器7 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG6_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x24) /* XTS_KEY2配置寄存器6 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG5_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x28) /* XTS_KEY2配置寄存器5 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG4_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x2C) /* XTS_KEY2配置寄存器4 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG3_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x30) /* XTS_KEY2配置寄存器3 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG2_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x34) /* XTS_KEY2配置寄存器2 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG1_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x38) /* XTS_KEY2配置寄存器1 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG0_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x3C) /* XTS_KEY2配置寄存器0 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY_CTRL_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x40) /* XTS_KEY控制寄存器 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY_STAT_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x44) /* XTS_KEY状态寄存器 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTX_MEM_INIT_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x48) /* XTS MEM初始化使能寄存器 \ + */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_MEM_INIT_DONE_REG \ + (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x4C) /* XTS MEM初始化状态寄存器 */ + +/* CTX_XTS_IPSEC_KEY_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_BASE (0x6E00) + +/* **************************************************************************** */ +/* CTX_XTS_IPSEC_KEY_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG7_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x0) /* XTS_KEY1配置寄存器7 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG6_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x4) /* XTS_KEY1配置寄存器6 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG5_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x8) /* XTS_KEY1配置寄存器5 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG4_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0xC) /* XTS_KEY1配置寄存器4 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG3_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x10) /* XTS_KEY1配置寄存器3 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG2_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x14) /* XTS_KEY1配置寄存器2 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG1_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x18) /* XTS_KEY1配置寄存器1 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG0_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x1C) /* XTS_KEY1配置寄存器0 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG7_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x20) /* XTS_KEY2配置寄存器7 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG6_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x24) /* XTS_KEY2配置寄存器6 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG5_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x28) /* XTS_KEY2配置寄存器5 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG4_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x2C) /* XTS_KEY2配置寄存器4 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG3_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x30) /* XTS_KEY2配置寄存器3 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG2_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x34) /* XTS_KEY2配置寄存器2 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG1_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x38) /* XTS_KEY2配置寄存器1 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG0_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x3C) /* XTS_KEY2配置寄存器0 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY_CTRL_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x40) /* XTS_KEY控制寄存器 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY_STAT_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x44) /* XTS_KEY状态寄存器 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTX_MEM_INIT_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x48) /* XTS MEM初始化使能寄存器 \ + */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_MEM_INIT_DONE_REG \ + (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x4C) /* XTS MEM初始化状态寄存器 */ + +/* CTX_XTS_EC_IPSEC_KEY_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE (0x6A00) + +/* **************************************************************************** */ +/* CTX_XTS_EC_IPSEC_KEY_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG7_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x0) /* XTS_KEY1配置寄存器7 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG6_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x4) /* XTS_KEY1配置寄存器6 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG5_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x8) /* XTS_KEY1配置寄存器5 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG4_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0xC) /* XTS_KEY1配置寄存器4 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG3_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x10) /* XTS_KEY1配置寄存器3 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG2_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x14) /* XTS_KEY1配置寄存器2 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG1_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x18) /* XTS_KEY1配置寄存器1 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG0_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x1C) /* XTS_KEY1配置寄存器0 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG7_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x20) /* XTS_KEY2配置寄存器7 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG6_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x24) /* XTS_KEY2配置寄存器6 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG5_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x28) /* XTS_KEY2配置寄存器5 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG4_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x2C) /* XTS_KEY2配置寄存器4 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG3_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x30) /* XTS_KEY2配置寄存器3 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG2_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x34) /* XTS_KEY2配置寄存器2 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG1_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x38) /* XTS_KEY2配置寄存器1 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG0_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x3C) /* XTS_KEY2配置寄存器0 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY_CTRL_REG (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x40) /* XTS_KEY控制寄存器 \ + */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY_STAT_REG (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x44) /* XTS_KEY状态寄存器 \ + */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTX_MEM_INIT_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x48) /* XTS MEM初始化使能寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_MEM_INIT_DONE_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x4C) /* XTS MEM初始化状态寄存器 */ + +/* TRNG_CSR Base address of Module's Register */ +#define CSR_TRNG_CSR_BASE (0xF000) + +/* **************************************************************************** */ +/* TRNG_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TRNG_CSR_TRNG_OUTPUT_0_REG (CSR_TRNG_CSR_BASE + 0x0) /* 随机数输出寄存器0 */ +#define CSR_TRNG_CSR_TRNG_OUTPUT_1_REG (CSR_TRNG_CSR_BASE + 0x4) /* 随机数输出寄存器1 */ +#define CSR_TRNG_CSR_TRNG_OUTPUT_2_REG (CSR_TRNG_CSR_BASE + 0x8) /* 随机数输出寄存器2 */ +#define CSR_TRNG_CSR_TRNG_OUTPUT_3_REG (CSR_TRNG_CSR_BASE + 0xC) /* 随机数输出寄存器3 */ +#define CSR_TRNG_CSR_TRNG_INPUT_0_REG (CSR_TRNG_CSR_BASE + 0x0) /* 数据输入寄存器0 */ +#define CSR_TRNG_CSR_TRNG_INPUT_1_REG (CSR_TRNG_CSR_BASE + 0x4) /* 数据输入寄存器1 */ +#define CSR_TRNG_CSR_TRNG_INPUT_2_REG (CSR_TRNG_CSR_BASE + 0x8) /* 数据输入寄存器2 */ +#define CSR_TRNG_CSR_TRNG_INPUT_3_REG (CSR_TRNG_CSR_BASE + 0xC) /* 数据输入寄存器3 */ +#define CSR_TRNG_CSR_TRNG_STATUS_REG (CSR_TRNG_CSR_BASE + 0x10) /* 状态寄存器 */ +#define CSR_TRNG_CSR_TRNG_INTACK_REG (CSR_TRNG_CSR_BASE + 0x10) /* 中断清除寄存器 */ +#define CSR_TRNG_CSR_TRNG_CONTROL_REG (CSR_TRNG_CSR_BASE + 0x14) /* 控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_CONFIG_REG (CSR_TRNG_CSR_BASE + 0x18) /* 配置寄存器 */ +#define CSR_TRNG_CSR_TRNG_ALARMCNT_REG (CSR_TRNG_CSR_BASE + 0x1C) /* 关断中断控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_FROENABLE_REG (CSR_TRNG_CSR_BASE + 0x20) /* FRO使能寄存器 */ +#define CSR_TRNG_CSR_TRNG_FRODETUNE_REG (CSR_TRNG_CSR_BASE + 0x24) /* FRO调节寄存器 */ +#define CSR_TRNG_CSR_TRNG_ALARMMASK_REG (CSR_TRNG_CSR_BASE + 0x28) /* 告警事件log寄存器 */ +#define CSR_TRNG_CSR_TRNG_ALARMSTOP_REG (CSR_TRNG_CSR_BASE + 0x2C) /* 告警关断寄存器 */ +#define CSR_TRNG_CSR_TRNG_RAW_L_REG (CSR_TRNG_CSR_BASE + 0x30) /* 原始噪声bit低位寄存器 */ +#define CSR_TRNG_CSR_TRNG_RAW_H_REG (CSR_TRNG_CSR_BASE + 0x34) /* 原始噪声bit高位寄存器 */ +#define CSR_TRNG_CSR_TRNG_SPB_TESTS_REG (CSR_TRNG_CSR_BASE + 0x38) /* SP 800-90B测试控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_COUNT_REG (CSR_TRNG_CSR_BASE + 0x3C) /* 主时间计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_COND_0_REG (CSR_TRNG_CSR_BASE + 0x40) /* 加工功能输出寄存器0 */ +#define CSR_TRNG_CSR_TRNG_COND_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* 加工功能输出寄存器1 */ +#define CSR_TRNG_CSR_TRNG_COND_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* 加工功能输出寄存器2 */ +#define CSR_TRNG_CSR_TRNG_COND_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* 加工功能输出寄存器3 */ +#define CSR_TRNG_CSR_TRNG_COND_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* 加工功能输出寄存器4 */ +#define CSR_TRNG_CSR_TRNG_COND_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* 加工功能输出寄存器5 */ +#define CSR_TRNG_CSR_TRNG_COND_6_REG (CSR_TRNG_CSR_BASE + 0x58) /* 加工功能输出寄存器6 */ +#define CSR_TRNG_CSR_TRNG_COND_7_REG (CSR_TRNG_CSR_BASE + 0x5C) /* 加工功能输出寄存器7 */ +#define CSR_TRNG_CSR_TRNG_KEY_0_REG (CSR_TRNG_CSR_BASE + 0x40) /* DRBG AES-256 key寄存器0 */ +#define CSR_TRNG_CSR_TRNG_KEY_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* DRBG AES-256 key寄存器1 */ +#define CSR_TRNG_CSR_TRNG_KEY_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* DRBG AES-256 key寄存器2 */ +#define CSR_TRNG_CSR_TRNG_KEY_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* DRBG AES-256 key寄存器3 */ +#define CSR_TRNG_CSR_TRNG_KEY_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* DRBG AES-256 key寄存器4 */ +#define CSR_TRNG_CSR_TRNG_KEY_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* DRBG AES-256 key寄存器5 */ +#define CSR_TRNG_CSR_TRNG_KEY_6_REG (CSR_TRNG_CSR_BASE + 0x58) /* DRBG AES-256 key寄存器6 */ +#define CSR_TRNG_CSR_TRNG_KEY_7_REG (CSR_TRNG_CSR_BASE + 0x5C) /* DRBG AES-256 key寄存器7 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_0_REG (CSR_TRNG_CSR_BASE + 0x40) /* DRBG输入寄存器0 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* DRBG输入寄存器1 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* DRBG输入寄存器2 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* DRBG输入寄存器3 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* DRBG输入寄存器4 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* DRBG输入寄存器5 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_6_REG (CSR_TRNG_CSR_BASE + 0x58) /* DRBG输入寄存器6 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_7_REG (CSR_TRNG_CSR_BASE + 0x5C) /* DRBG输入寄存器7 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_8_REG (CSR_TRNG_CSR_BASE + 0x60) /* DRBG输入寄存器8 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_9_REG (CSR_TRNG_CSR_BASE + 0x64) /* DRBG输入寄存器9 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_10_REG (CSR_TRNG_CSR_BASE + 0x68) /* DRBG输入寄存器10 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_11_REG (CSR_TRNG_CSR_BASE + 0x6C) /* DRBG输入寄存器11 */ +#define CSR_TRNG_CSR_TRNG_RUN_CNT_REG (CSR_TRNG_CSR_BASE + 0x40) /* bits和runs 计数器状态寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* 1bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* 2bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* 3bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* 4bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* 5bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_6_UP_REG (CSR_TRNG_CSR_BASE + 0x58) /* 大于等于6bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_MONOBITCNT_REG (CSR_TRNG_CSR_BASE + 0x5C) /* “Monobit”测试计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_3_0_REG (CSR_TRNG_CSR_BASE + 0x60) /* “Poker”测试计数器0-3寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_7_4_REG (CSR_TRNG_CSR_BASE + 0x64) /* “Poker”测试计数器4-7寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_B_8_REG (CSR_TRNG_CSR_BASE + 0x68) /* “Poker”测试计数器8-B寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_F_C_REG (CSR_TRNG_CSR_BASE + 0x6C) /* “Poker”测试计数器C-F寄存器 */ +#define CSR_TRNG_CSR_TRNG_TEST_REG (CSR_TRNG_CSR_BASE + 0x70) /* 测试控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_BLOCKCNT_REG (CSR_TRNG_CSR_BASE + 0x74) /* 输出block计数器 */ +#define CSR_TRNG_CSR_TRNG_OPTIONS_REG (CSR_TRNG_CSR_BASE + 0x78) /* 引擎可选信息 */ +#define CSR_TRNG_CSR_TRNG_EIP_REV_REG (CSR_TRNG_CSR_BASE + 0x7C) /* EIP 数字和core版本信息 */ +#define CSR_TRNG_CSR_TRNG_CTRL0_REG (CSR_TRNG_CSR_BASE + 0xC0) /* TRNG全局控制寄存器0 */ +#define CSR_TRNG_CSR_TRNG_CTRL1_REG (CSR_TRNG_CSR_BASE + 0xC4) /* TRNG全局控制寄存器1 */ +#define CSR_TRNG_CSR_TRNG_INT_VECTOR_REG (CSR_TRNG_CSR_BASE + 0xC8) /* 中断向量 */ +#define CSR_TRNG_CSR_RNG_CTRL_REG (CSR_TRNG_CSR_BASE + 0xCC) /* RNG控制寄存器 */ +#define CSR_TRNG_CSR_RNG_SEED_REG (CSR_TRNG_CSR_BASE + 0xD0) /* RNG随机种子配置寄存器 */ +#define CSR_TRNG_CSR_TRNG_FSM_ST_REG (CSR_TRNG_CSR_BASE + 0xD4) /* TRNG core内部状态机实时状态 */ +#define CSR_TRNG_CSR_RNG_NUM_REG (CSR_TRNG_CSR_BASE + 0xD8) /* RNG产生的32bit随机数 */ +#define CSR_TRNG_CSR_RNG_PHY_SEED_REG (CSR_TRNG_CSR_BASE + 0xDC) /* RNG的物理环产生的随机种子 */ +#define CSR_TRNG_CSR_RNG_ERR_REG (CSR_TRNG_CSR_BASE + 0xE0) /* RNG错误状态 */ +#define CSR_TRNG_CSR_TRNG_INT_SET_REG (CSR_TRNG_CSR_BASE + 0xE4) /* 中断置位寄存器 */ +#define CSR_TRNG_CSR_TRNG_INT_EN_REG (CSR_TRNG_CSR_BASE + 0xE8) /* 中断使能 */ +#define CSR_TRNG_CSR_TRNG_INT_ST_REG (CSR_TRNG_CSR_BASE + 0xEC) /* 中断状态 */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA0_REG (CSR_TRNG_CSR_BASE + 0xF0) /* TRNG真随机数生成寄存器（非安全可读） */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA1_REG (CSR_TRNG_CSR_BASE + 0xF4) /* TRNG真随机数生成寄存器（非安全可读） */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA2_REG (CSR_TRNG_CSR_BASE + 0xF8) /* TRNG真随机数生成寄存器（非安全可读） */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA3_REG (CSR_TRNG_CSR_BASE + 0xFC) /* TRNG真随机数生成寄存器（非安全可读） */ + +/* SRAM Base address of Module's Register */ +#define CSR_SRAM_BASE (0x8000) + +/* **************************************************************************** */ +/* SRAM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SRAM_SRAM_CTRL_REG (CSR_SRAM_BASE + 0x0) /* SRAM控制寄存器 */ +#define CSR_SRAM_SRAM_STATE_REG (CSR_SRAM_BASE + 0x4) /* SRAM状态寄存器 */ +#define CSR_SRAM_SRAM_SEC_CTRL_REG (CSR_SRAM_BASE + 0x10) /* SRAM安全空间控制寄存器 */ +#define CSR_SRAM_SRAM_SEC_ADDR_REG (CSR_SRAM_BASE + 0x14) /* SRAM安全空间地址寄存器 */ +#define CSR_SRAM_SRAM_SEC_SIZE_REG (CSR_SRAM_BASE + 0x18) /* SRAM安全空间Size寄存器 */ +#define CSR_SRAM_SRAM_BASE_ADDR_REG (CSR_SRAM_BASE + 0x20) /* SRAM 基地址地址寄存器 */ +#define CSR_SRAM_SRAM_INTMASK_REG (CSR_SRAM_BASE + 0x40) /* SRAM中断屏蔽寄存器 */ +#define CSR_SRAM_SRAM_RAWINT_REG (CSR_SRAM_BASE + 0x44) /* SRAM原始中断状态寄存器 */ +#define CSR_SRAM_SRAM_INTSTS_REG (CSR_SRAM_BASE + 0x48) /* SRAM中断状态寄存器 */ +#define CSR_SRAM_SRAM_INTCLR_REG (CSR_SRAM_BASE + 0x4C) /* SRAM中断清除寄存器 */ +#define CSR_SRAM_SRAM_ECC_INJECT_REG (CSR_SRAM_BASE + 0x60) /* SRAM ECC注入寄存器 */ +#define CSR_SRAM_SRAM_ERR_INFO_REG (CSR_SRAM_BASE + 0x64) /* SRAM错误操作信息寄存器 */ +#define CSR_SRAM_SRAM_ERR_ADDR_REG (CSR_SRAM_BASE + 0x68) /* SRAM错误操作地址寄存器 */ +#define CSR_SRAM_SRAM_ECC_INFO_REG (CSR_SRAM_BASE + 0x6C) /* SRAM ECC错误寄存器 */ +#define CSR_SRAM_SRAM_CLR_STAT_REG (CSR_SRAM_BASE + 0x70) /* SRAM状态清除寄存器 */ +#define CSR_SRAM_SRAM_ECC_CNT_REG (CSR_SRAM_BASE + 0x80) /* SRAM ECC错误计数器 */ +#define CSR_SRAM_SRAM_CNT_TYPE_REG (CSR_SRAM_BASE + 0x84) /* SRAM DFX计数器类型控制寄存器 */ +#define CSR_SRAM_SRAM_CNT0_REG (CSR_SRAM_BASE + 0x88) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_CNT1_REG (CSR_SRAM_BASE + 0x8C) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_CNT2_REG (CSR_SRAM_BASE + 0x90) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_CNT3_REG (CSR_SRAM_BASE + 0x94) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_MAGIC_WORD_REG (CSR_SRAM_BASE + 0x7F0) /* SRAM版本修改寄存器 */ +#define CSR_SRAM_SRAM_VERSION_REG (CSR_SRAM_BASE + 0xC10) /* SRAM版本寄存器 */ + +/* AM_OOO_CFG Base address of Module's Register */ +#define CSR_AM_OOO_CFG_BASE (0x9000) + +/* **************************************************************************** */ +/* AM_OOO_CFG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_AM_OOO_CFG_AM_CTRL_GLOBAL_REG (CSR_AM_OOO_CFG_BASE + 0x0) /* 全局控制 */ +#define CSR_AM_OOO_CFG_AM_CTRL_LATENCY_SEL_REG (CSR_AM_OOO_CFG_BASE + 0x4) /* 选择对某个通道进行总线访问延迟统计。 */ +#define CSR_AM_OOO_CFG_AM_CTRL_PTL_WR_REG (CSR_AM_OOO_CFG_BASE + 0x8) /* 控制使能PARTIAL WR操作 */ +#define CSR_AM_OOO_CFG_AM_CFG_MAX_TRANS_REG (CSR_AM_OOO_CFG_BASE + 0x10) /* 配置全局允许的最大outstanding数量 */ +#define CSR_AM_OOO_CFG_AM_CFG_SINGLE_PORT_MAX_TRANS_REG \ + (CSR_AM_OOO_CFG_BASE + 0x14) /* 配置全局允许的最大outstanding数量 */ +#define CSR_AM_OOO_CFG_AM_CFG_PORT_RD_EN_REG (CSR_AM_OOO_CFG_BASE + 0x18) /* 配置允许打开的内部读端口 */ +#define CSR_AM_OOO_CFG_AM_CFG_PORT_WR_EN_REG (CSR_AM_OOO_CFG_BASE + 0x1C) /* 配置允许打开的内部写端口 */ +#define CSR_AM_OOO_CFG_AM_CURR_AW_W_FIFO_STS_REG (CSR_AM_OOO_CFG_BASE + 0x20) /* AW与W之间FIFO的当前状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_PORT_STS_REG (CSR_AM_OOO_CFG_BASE + 0x100) /* 内部读写端口的当前工作状态 */ +#define CSR_AM_OOO_CFG_AM_ROB_ECC_INT_STS_REG \ + (CSR_AM_OOO_CFG_BASE + 0x104) /* Reorder Buffer所用Memory发生ECC错误中断状态 */ +#define CSR_AM_OOO_CFG_AM_ROB_ECC_INT_MASK_REG \ + (CSR_AM_OOO_CFG_BASE + 0x108) /* Reorder Buffer所用Memory发生ECC错误中断使能信号 */ +#define CSR_AM_OOO_CFG_AM_ROB_ECC_ERR_ADDR_REG \ + (CSR_AM_OOO_CFG_BASE + 0x10C) /* Reorder Buffer所用Memory发生ECC错误对应的地址 */ +#define CSR_AM_OOO_CFG_AM_CURR_MAX_RD_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x110) /* 指定内部端口读访问操作最大延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_AVA_RD_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x114) /* 指定内部端口读访问操作平均延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x118) /* 读延迟实时状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_MAX_WR_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x130) /* 指定内部端口写访问操作最大延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_AVA_WR_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x134) /* 指定内部端口写访问操作平均延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x138) /* 写完成延迟实时状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_TRANS_RETURN_REG \ + (CSR_AM_OOO_CFG_BASE + 0x150) /* 读写通道发出的续写outstnading操作完成状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_MAX_TXID_REG (CSR_AM_OOO_CFG_BASE + 0x154) /* 读通道transaction ID的最大使用量 */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_MAX_TXID_REG (CSR_AM_OOO_CFG_BASE + 0x158) /* 写通道transaction ID的最大使用量 */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_TXID_STS_0_REG (CSR_AM_OOO_CFG_BASE + 0x160) /* 读方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_TXID_STS_1_REG (CSR_AM_OOO_CFG_BASE + 0x164) /* 读方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_TXID_STS_2_REG (CSR_AM_OOO_CFG_BASE + 0x168) /* 读方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_TXID_STS_0_REG (CSR_AM_OOO_CFG_BASE + 0x170) /* 写方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_TXID_STS_1_REG (CSR_AM_OOO_CFG_BASE + 0x174) /* 写方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_TXID_STS_2_REG (CSR_AM_OOO_CFG_BASE + 0x178) /* 写方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_ALARM_RRESP_REG (CSR_AM_OOO_CFG_BASE + 0x180) /* 读方向RESP出错告警信号 */ +#define CSR_AM_OOO_CFG_AM_ALARM_BRESP_REG (CSR_AM_OOO_CFG_BASE + 0x184) /* 写方向BRESP出错告警信号 */ + +/* HPRE_COMMON Base address of Module's Register */ +#define CSR_HPRE_COMMON_BASE (0xA000) + +/* **************************************************************************** */ +/* HPRE_COMMON Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HPRE_COMMON_HPRE_CNT_CLR_CE (CSR_HPRE_COMMON_BASE + 0x0) /* HPRE CNT CLR CE配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_AXQOS_REG (CSR_HPRE_COMMON_BASE + 0xC) /* HPRE AXI MASTER的AXQOS配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_AXCACHE_REG (CSR_HPRE_COMMON_BASE + 0x10) /* HPRE AXI MASTER的AXCACHE配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_RDCHN_INI_REG (CSR_HPRE_COMMON_BASE + 0x14) /* HPRE读通道SRAM初始化配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_AWUSER_FP_CFG_REG (CSR_HPRE_COMMON_BASE + 0x18) /* AW USER FP域段配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_BD_ENDIAN_REG (CSR_HPRE_COMMON_BASE + 0x20) /* 输入/输出BD的大小端配置 */ +#define CSR_HPRE_COMMON_HPRE_ECC_BYPASS_REG (CSR_HPRE_COMMON_BASE + 0x24) /* SRAM ECC校验旁路控制寄存器 */ +#define CSR_HPRE_COMMON_HPRE_RAS_INT_WIDTH_CFG_REG (CSR_HPRE_COMMON_BASE + 0x28) /* RAS中断脉冲宽度配置寄存器 */ +#define CSR_HPRE_COMMON_HPRE_POISON_BYPASS_REG (CSR_HPRE_COMMON_BASE + 0x2C) /* AXI MASTER读写污染域屏蔽配置寄存器 */ +#define CSR_HPRE_COMMON_HPRE_BD_ARUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x30) /* 模块读BD的AR USER属性配置寄存器。 */ +#define CSR_HPRE_COMMON_HPRE_BD_AWUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x34) /* 模块写BD的AW USER属性配置寄存器。 */ +#define CSR_HPRE_COMMON_HPRE_TYPES_ENB_REG (CSR_HPRE_COMMON_BASE + 0x38) /* 任务类型使能 */ +#define CSR_HPRE_COMMON_HPRE_DATA_ARUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x3C) /* 模块读数据的AR USER属性配置寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_DATA_AWUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x40) /* 模块写数据的AW USER属性配置寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_AM_OOO_SHUTDOWN_ENB_REG (CSR_HPRE_COMMON_BASE + 0x44) /* HPRE的AM OOO关闭使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_INT_MSK_REG \ + (CSR_HPRE_COMMON_BASE + 0x400) /* HPRE HAC中断的屏蔽寄存器(不包含QM的中断) */ +#define CSR_HPRE_COMMON_HPRE_RAS_ECC1BIT_TH_REG (CSR_HPRE_COMMON_BASE + 0x40C) /* ECC1bit错误上报阈值配置 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_CE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x410) /* HPRE HAC中断上报RAS CE中断使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_NFE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x414) /* HPRE HAC中断上报RAS NFE中断使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_FE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x418) /* HPRE HAC中断上报RAS FE中断使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_INT_SET_REG (CSR_HPRE_COMMON_BASE + 0x500) /* HPRE_HAC_RINT置位寄存器 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RINT_REG (CSR_HPRE_COMMON_BASE + 0x600) /* HPRE HAC原始中断 */ +#define CSR_HPRE_COMMON_HPRE_HAC_INT_ST_REG (CSR_HPRE_COMMON_BASE + 0x800) /* HPRE HAC中断状态 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_AFULL_HIS1_REG \ + (CSR_HPRE_COMMON_BASE + 0x810) /* FIFO曾经出现将满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_AFULL_HIS2_REG \ + (CSR_HPRE_COMMON_BASE + 0x814) /* FIFO曾经出现将满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_AFULL_HIS3_REG \ + (CSR_HPRE_COMMON_BASE + 0x818) /* FIFO曾经出现将满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_FULL_HIS1_REG \ + (CSR_HPRE_COMMON_BASE + 0x840) /* FIFO曾经出现满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_FULL_HIS2_REG \ + (CSR_HPRE_COMMON_BASE + 0x844) /* FIFO曾经出现满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_FULL_HIS3_REG \ + (CSR_HPRE_COMMON_BASE + 0x848) /* FIFO曾经出现满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_EMPTY_ST1_REG \ + (CSR_HPRE_COMMON_BASE + 0x880) /* FIFO空状态记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_EMPTY_ST2_REG \ + (CSR_HPRE_COMMON_BASE + 0x884) /* FIFO空状态记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_EMPTY_ST3_REG \ + (CSR_HPRE_COMMON_BASE + 0x888) /* FIFO空状态记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_MEM_EBIT_INJ_EN_REG \ + (CSR_HPRE_COMMON_BASE + 0x900) /* HPRE读通道和QMV2内部 MEM故障注入使能 */ +#define CSR_HPRE_COMMON_HPRE_MEM_EBIT_INJ_REG (CSR_HPRE_COMMON_BASE + 0x904) /* HPRE读通道和QMV2内部 MEM故障注入 */ +#define CSR_HPRE_COMMON_HPRE_QMV2_MEM_ERR_ADDR_REG (CSR_HPRE_COMMON_BASE + 0x908) /* HPRE的QMV2内部MEM出错地址记录 */ +#define CSR_HPRE_COMMON_HPRE_CLKGATE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x90C) /* HPRE算法核动态门控使能 */ +#define CSR_HPRE_COMMON_HPRE_CRYPT_DO_CRT_REG (CSR_HPRE_COMMON_BASE + 0x910) /* HPRE输出端口信用值 */ +#define CSR_HPRE_COMMON_HPRE_INT_VECTOR_REG (CSR_HPRE_COMMON_BASE + 0x914) /* HPRE中断向量 */ +#define CSR_HPRE_COMMON_HPRE_INT_REG (CSR_HPRE_COMMON_BASE + 0x918) /* HPRE中断状态 */ +#define CSR_HPRE_COMMON_HPRE_INT_EN_REG (CSR_HPRE_COMMON_BASE + 0x91C) /* HPRE中断屏蔽 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_CE_ERR_REG (CSR_HPRE_COMMON_BASE + 0x920) /* HPRE加速器CE中断 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_FE_ERR_REG (CSR_HPRE_COMMON_BASE + 0x924) /* HPRE加速器FE中断 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_NFE_ERR_REG (CSR_HPRE_COMMON_BASE + 0x928) /* HPRE加速器NFE中断 */ +#define CSR_HPRE_COMMON_INT_SRAM_ERR_REG (CSR_HPRE_COMMON_BASE + 0x92C) /* SRAM中断 */ +#define CSR_HPRE_COMMON_HPRE_DI_FSM_TIMEOUT_ERR_REG (CSR_HPRE_COMMON_BASE + 0x930) /* DI状态机超时 */ +#define CSR_HPRE_COMMON_HPRE_DO_FSM_TIMEOUT_ERR_REG (CSR_HPRE_COMMON_BASE + 0x934) /* DO状态机超时 */ +#define CSR_HPRE_COMMON_HPRE_DIDO_ERR_INFO_REG (CSR_HPRE_COMMON_BASE + 0x938) /* di/do曾出现异常信息 */ +#define CSR_HPRE_COMMON_HPRE_FSM_SHB_CFG_REG (CSR_HPRE_COMMON_BASE + 0x93C) /* 智能心跳上限配置 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_0_REG (CSR_HPRE_COMMON_BASE + 0x940) /* HPRE中MEM_CTRL寄存器0 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_1_REG (CSR_HPRE_COMMON_BASE + 0x944) /* HPRE中MEM_CTRL寄存器1 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_2_REG (CSR_HPRE_COMMON_BASE + 0x948) /* HPRE中MEM_CTRL寄存器2 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_3_REG (CSR_HPRE_COMMON_BASE + 0x94C) /* HPRE中MEM_CTRL寄存器3 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_4_REG (CSR_HPRE_COMMON_BASE + 0x950) /* HPRE中MEM_CTRL寄存器4 */ +#define CSR_HPRE_COMMON_HPRE_RDCHN_INI_ST_REG (CSR_HPRE_COMMON_BASE + 0xA00) /* HPRE 读数据通道 SRAM初始化状态 */ +#define CSR_HPRE_COMMON_HPRE_ECC1BIT_ERR_CNT_REG (CSR_HPRE_COMMON_BASE + 0xA04) /* Memory出现ECC1bit错误统计寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_ECC2BIT_ERR_CNT_REG (CSR_HPRE_COMMON_BASE + 0xA08) /* Memory出现ECC2bit错误统计寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO1_REG (CSR_HPRE_COMMON_BASE + 0xA10) /* PEH ECO寄存器组1 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO2_REG (CSR_HPRE_COMMON_BASE + 0xA14) /* PEH ECO寄存器组2 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO3_REG (CSR_HPRE_COMMON_BASE + 0xA18) /* PEH ECO寄存器组3 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO4_REG (CSR_HPRE_COMMON_BASE + 0xA1C) /* PEH ECO寄存器组4 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO5_REG (CSR_HPRE_COMMON_BASE + 0xA20) /* PEH ECO寄存器组5 */ +#define CSR_HPRE_COMMON_HPRE_ECO1_REG (CSR_HPRE_COMMON_BASE + 0xA24) /* ECO寄存器1 */ +#define CSR_HPRE_COMMON_HPRE_ECO2_REG (CSR_HPRE_COMMON_BASE + 0xA28) /* ECO寄存器2 */ +#define CSR_HPRE_COMMON_HPRE_ECO3_REG (CSR_HPRE_COMMON_BASE + 0xA2C) /* ECO寄存器3 */ +#define CSR_HPRE_COMMON_HPRE_ECO4_REG (CSR_HPRE_COMMON_BASE + 0xA30) /* ECO寄存器4 */ + +/* HPRE_CLUSTER1 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER1_BASE (0xB000) +/* HPRE_CLUSTER2 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER2_BASE (0xC000) +/* HPRE_CLUSTER3 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER3_BASE (0xD000) +/* HPRE_CLUSTER4 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER4_BASE (0xE000) + +/* **************************************************************************** */ +/* HPRE_CLUSTER Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HPRE_CLUSTER_HPRE_CORE_ENB_REG(base_addr) ((base_addr) + 0x4) /* HPRE算法核使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CLUSTER_DYN_ENB_REG(base_addr) ((base_addr) + 0x10) /* HPRE CLUSTER动态时钟门控使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_INI_CFG_REG(base_addr) ((base_addr) + 0x20) /* HPRE算法核初始化配置使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_INI_STATUS_REG(base_addr) ((base_addr) + 0x80) /* HPRE算法核memory初始化状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_ERR_BIT_INJECT_EN_REG(base_addr) ((base_addr) + 0x84) /* SRAM故障注入使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_SHB_CFG_REG(base_addr) ((base_addr) + 0x88) /* 智能心跳上限配置 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_SHB_ST_REG(base_addr) ((base_addr) + 0x8C) /* 算法核智能心跳状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_IDLE_ST_REG(base_addr) ((base_addr) + 0x90) /* CLUSTER算法核空闲状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_STATUS_INQUIRE_REG(base_addr) ((base_addr) + 0x100) /* HPRE算法核状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_STATUS_RESULT_REG(base_addr) \ + ((base_addr) + 0x104) /* HPRE算法核状态数据返回（考虑到数据返回有延迟，配置完HPRE_CORE_STATUS_INQUIRE后，需要等待若干HPRE周期后(10个HPRE周期，约10ns)，再去查询本寄存器的值） \ + */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_ERR_BIT_INJECT_REG(base_addr) ((base_addr) + 0x108) + +#endif // CRYPTO_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_c_union_define.h new file mode 100644 index 000000000..ccc021ecf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_c_union_define.h @@ -0,0 +1,1340 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : esch_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/11 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/12/11 20:09:30 Create file +// ****************************************************************************** + +#ifndef ESCH_C_UNION_DEFINE_H +#define ESCH_C_UNION_DEFINE_H + +/* Define the union csr_esch_cos_ch_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_ch_map_link : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_cos_ch_map_u; + +/* Define the union csr_esch_mem_cfg_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ok : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_cfg_ok_u; + +/* Define the union csr_esch_ppop_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_bp_mask : 1; /* [0] */ + u32 rsv_2 : 3; /* [3:1] */ + u32 eps_q_grp_csr_cfg : 7; /* [10:4] */ + u32 rsv_3 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_ppop_bp_cfg_u; + +/* Define the union csr_esch_ppop_bp_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_grp_bp_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_ppop_bp_st_u; + +/* Define the union csr_esch_lb_prm_bp_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_lb_cos_map : 6; /* [5:0] */ + u32 rsv_4 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_lb_prm_bp_map_u; + +/* Define the union csr_esch_host_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_host_fifo_th : 5; /* [4:0] */ + u32 rsv_5 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_host_fifo_th_u; + +/* Define the union csr_esch_hostlb_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_host_lb_fifo_th : 5; /* [4:0] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hostlb_fifo_th_u; + +/* Define the union csr_esch_net_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_net_fifo_th : 5; /* [4:0] */ + u32 rsv_7 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_net_fifo_th_u; + +/* Define the union csr_esch_netlb_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_net_lb_fifo_th : 5; /* [4:0] */ + u32 rsv_8 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_netlb_fifo_th_u; + +/* Define the union csr_esch_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_start : 1; /* [0] */ + u32 mem_power_ctrl : 3; /* [3:1] */ + u32 mem_timing_ctrl : 7; /* [10:4] */ + u32 mem_ecc_enable : 1; /* [11] */ + u32 mem_init_done : 1; /* [12] */ + u32 rsv_9 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_ctrl_u; + +/* Define the union csr_esch_mem_err_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_ram_err_req0 : 16; /* [15:0] */ + u32 eps_ram_err_req1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_err_req0_u; + +/* Define the union csr_esch_mem_err_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_ram_err_req4 : 2; /* [1:0] */ + u32 eps_ram_err_req3 : 2; /* [3:2] */ + u32 eps_ram_err_req2 : 2; /* [5:4] */ + u32 hps_ram_err_req2 : 2; /* [7:6] */ + u32 hps_ram_err_req1 : 2; /* [9:8] */ + u32 hps_ram_err_req0 : 2; /* [11:10] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_err_req1_u; + +/* Define the union csr_esch_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_11 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int_vector_u; + +/* Define the union csr_esch_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_13 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int_u; + +/* Define the union csr_esch_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_14 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int_en_u; + +/* Define the union csr_esch_int0_sticky0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esch_mem_err0 : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 esch_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int0_sticky0_u; + +/* Define the union csr_esch_int0_sticky1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esch_mem_err1 : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 esch_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int0_sticky1_u; + +/* Define the union csr_esch_int0_sticky2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esch_fifo_err : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 esch_int2_sticky : 4; /* [5:2] */ + u32 rsv_15 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int0_sticky2_u; + +/* Define the union csr_esch_fcnp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcnp_ref_size_cfg : 10; /* [9:0] */ + u32 rsv_16 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_fcnp_cfg_u; + +/* Define the union csr_esch_cpb_ch_cdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_chan_credit : 5; /* [4:0] */ + u32 cpb_chan_id : 6; /* [10:5] */ + u32 cpb_chan_type : 3; /* [13:11] */ + u32 rsv_17 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_cpb_ch_cdt_cfg_u; + +/* Define the union csr_esch_hps_nml_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_normal_cos_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_nml_cos_bp_u; + +/* Define the union csr_esch_hps_up_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_mpu_bp : 1; /* [0] */ + u32 hps_spu_cos_bp : 8; /* [8:1] */ + u32 rsv_18 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_up_bp_u; + +/* Define the union csr_esch_hps_lb_cos_high_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_cos_high_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_cos_high_bp_u; + +/* Define the union csr_esch_hps_lb_cos_low_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_cos_low_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_cos_low_bp_u; + +/* Define the union csr_esch_eps_cos_high_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_high_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_eps_cos_high_bp_u; + +/* Define the union csr_esch_eps_cos_low_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_low_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_eps_cos_low_bp_u; + +/* Define the union csr_esch_eps_lb_type_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_type_bp : 3; /* [2:0] */ + u32 rsv_19 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_eps_lb_type_bp_u; + +/* Define the union csr_esch_mag_high_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_esch_chan_bp_high32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mag_high_cos_bp_u; + +/* Define the union csr_esch_mag_low_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_esch_chan_bp_low32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mag_low_cos_bp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_esch_cos_ch_map_u esch_cos_ch_map[40]; /* 0 */ + volatile csr_esch_mem_cfg_ok_u esch_mem_cfg_ok; /* A0 */ + volatile csr_esch_ppop_bp_cfg_u esch_ppop_bp_cfg; /* A4 */ + volatile csr_esch_ppop_bp_st_u esch_ppop_bp_st; /* A8 */ + volatile csr_esch_lb_prm_bp_map_u esch_lb_prm_bp_map[192]; /* 100 */ + volatile csr_esch_host_fifo_th_u esch_host_fifo_th[33]; /* 400 */ + volatile csr_esch_hostlb_fifo_th_u esch_hostlb_fifo_th[64]; /* 500 */ + volatile csr_esch_net_fifo_th_u esch_net_fifo_th[64]; /* 600 */ + volatile csr_esch_netlb_fifo_th_u esch_netlb_fifo_th[3]; /* 700 */ + volatile csr_esch_mem_ctrl_u esch_mem_ctrl; /* 750 */ + volatile csr_esch_mem_err_req0_u esch_mem_err_req0; /* 754 */ + volatile csr_esch_mem_err_req1_u esch_mem_err_req1; /* 758 */ + volatile csr_esch_int_vector_u esch_int_vector; /* 760 */ + volatile csr_esch_int_u esch_int; /* 764 */ + volatile csr_esch_int_en_u esch_int_en; /* 768 */ + volatile csr_esch_int0_sticky0_u esch_int0_sticky0; /* 76C */ + volatile csr_esch_int0_sticky1_u esch_int0_sticky1; /* 770 */ + volatile csr_esch_int0_sticky2_u esch_int0_sticky2; /* 774 */ + volatile csr_esch_fcnp_cfg_u esch_fcnp_cfg; /* 778 */ + volatile csr_esch_cpb_ch_cdt_cfg_u esch_cpb_ch_cdt_cfg; /* 77C */ + volatile csr_esch_hps_nml_cos_bp_u esch_hps_nml_cos_bp; /* 780 */ + volatile csr_esch_hps_up_bp_u esch_hps_up_bp; /* 784 */ + volatile csr_esch_hps_lb_cos_high_bp_u esch_hps_lb_cos_high_bp; /* 788 */ + volatile csr_esch_hps_lb_cos_low_bp_u esch_hps_lb_cos_low_bp; /* 78C */ + volatile csr_esch_eps_cos_high_bp_u esch_eps_cos_high_bp; /* 790 */ + volatile csr_esch_eps_cos_low_bp_u esch_eps_cos_low_bp; /* 794 */ + volatile csr_esch_eps_lb_type_bp_u esch_eps_lb_type_bp; /* 79C */ + volatile csr_esch_mag_high_cos_bp_u esch_mag_high_cos_bp; /* 7A0 */ + volatile csr_esch_mag_low_cos_bp_u esch_mag_low_cos_bp; /* 7A4 */ +} S_esch_top_csr_REGS_TYPE; + +/* Declare the struct pointor of the module esch_top_csr */ +extern volatile S_esch_top_csr_REGS_TYPE *gopesch_top_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetESCH_COS_CH_MAP_cos_ch_map_link(unsigned int ucos_ch_map_link); +int iSetESCH_MEM_CFG_OK_cfg_ok(unsigned int ucfg_ok); +int iSetESCH_PPOP_BP_CFG_eps_q_bp_mask(unsigned int ueps_q_bp_mask); +int iSetESCH_PPOP_BP_CFG_eps_q_grp_csr_cfg(unsigned int ueps_q_grp_csr_cfg); +int iSetESCH_PPOP_BP_ST_eps_q_grp_bp_st(unsigned int ueps_q_grp_bp_st); +int iSetESCH_LB_PRM_BP_MAP_prm_lb_cos_map(unsigned int uprm_lb_cos_map); +int iSetESCH_HOST_FIFO_TH_cpb_host_fifo_th(unsigned int ucpb_host_fifo_th); +int iSetESCH_HOSTLB_FIFO_TH_cpb_host_lb_fifo_th(unsigned int ucpb_host_lb_fifo_th); +int iSetESCH_NET_FIFO_TH_cpb_net_fifo_th(unsigned int ucpb_net_fifo_th); +int iSetESCH_NETLB_FIFO_TH_cpb_net_lb_fifo_th(unsigned int ucpb_net_lb_fifo_th); +int iSetESCH_MEM_CTRL_mem_init_start(unsigned int umem_init_start); +int iSetESCH_MEM_CTRL_mem_power_ctrl(unsigned int umem_power_ctrl); +int iSetESCH_MEM_CTRL_mem_timing_ctrl(unsigned int umem_timing_ctrl); +int iSetESCH_MEM_CTRL_mem_ecc_enable(unsigned int umem_ecc_enable); +int iSetESCH_MEM_CTRL_mem_init_done(unsigned int umem_init_done); +int iSetESCH_MEM_ERR_REQ0_eps_ram_err_req0(unsigned int ueps_ram_err_req0); +int iSetESCH_MEM_ERR_REQ0_eps_ram_err_req1(unsigned int ueps_ram_err_req1); +int iSetESCH_MEM_ERR_REQ1_eps_ram_err_req4(unsigned int ueps_ram_err_req4); +int iSetESCH_MEM_ERR_REQ1_eps_ram_err_req3(unsigned int ueps_ram_err_req3); +int iSetESCH_MEM_ERR_REQ1_eps_ram_err_req2(unsigned int ueps_ram_err_req2); +int iSetESCH_MEM_ERR_REQ1_hps_ram_err_req2(unsigned int uhps_ram_err_req2); +int iSetESCH_MEM_ERR_REQ1_hps_ram_err_req1(unsigned int uhps_ram_err_req1); +int iSetESCH_MEM_ERR_REQ1_hps_ram_err_req0(unsigned int uhps_ram_err_req0); +int iSetESCH_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetESCH_INT_VECTOR_enable(unsigned int uenable); +int iSetESCH_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetESCH_INT_int_data(unsigned int uint_data); +int iSetESCH_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetESCH_INT_EN_int_en(unsigned int uint_en); +int iSetESCH_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetESCH_INT0_STICKY0_esch_mem_err0(unsigned int uesch_mem_err0); +int iSetESCH_INT0_STICKY0_int_insrt0(unsigned int uint_insrt0); +int iSetESCH_INT0_STICKY0_esch_int0_sticky(unsigned int uesch_int0_sticky); +int iSetESCH_INT0_STICKY1_esch_mem_err1(unsigned int uesch_mem_err1); +int iSetESCH_INT0_STICKY1_int_insrt1(unsigned int uint_insrt1); +int iSetESCH_INT0_STICKY1_esch_int1_sticky(unsigned int uesch_int1_sticky); +int iSetESCH_INT0_STICKY2_esch_fifo_err(unsigned int uesch_fifo_err); +int iSetESCH_INT0_STICKY2_int_insrt2(unsigned int uint_insrt2); +int iSetESCH_INT0_STICKY2_esch_int2_sticky(unsigned int uesch_int2_sticky); +int iSetESCH_FCNP_CFG_fcnp_ref_size_cfg(unsigned int ufcnp_ref_size_cfg); +int iSetESCH_CPB_CH_CDT_CFG_cpb_chan_credit(unsigned int ucpb_chan_credit); +int iSetESCH_CPB_CH_CDT_CFG_cpb_chan_id(unsigned int ucpb_chan_id); +int iSetESCH_CPB_CH_CDT_CFG_cpb_chan_type(unsigned int ucpb_chan_type); +int iSetESCH_HPS_NML_COS_BP_hps_normal_cos_bp(unsigned int uhps_normal_cos_bp); +int iSetESCH_HPS_UP_BP_hps_mpu_bp(unsigned int uhps_mpu_bp); +int iSetESCH_HPS_UP_BP_hps_spu_cos_bp(unsigned int uhps_spu_cos_bp); +int iSetESCH_HPS_LB_COS_HIGH_BP_hps_lb_cos_high_bp(unsigned int uhps_lb_cos_high_bp); +int iSetESCH_HPS_LB_COS_LOW_BP_hps_lb_cos_low_bp(unsigned int uhps_lb_cos_low_bp); +int iSetESCH_EPS_COS_HIGH_BP_eps_cos_high_bp(unsigned int ueps_cos_high_bp); +int iSetESCH_EPS_COS_LOW_BP_eps_cos_low_bp(unsigned int ueps_cos_low_bp); +int iSetESCH_EPS_LB_TYPE_BP_eps_lb_type_bp(unsigned int ueps_lb_type_bp); +int iSetESCH_MAG_HIGH_COS_BP_mag_esch_chan_bp_high32(unsigned int umag_esch_chan_bp_high32); +int iSetESCH_MAG_LOW_COS_BP_mag_esch_chan_bp_low32(unsigned int umag_esch_chan_bp_low32); + +/* Define the union csr_eps_q_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_indrect_addr : 24; /* [23:0] */ + u32 eps_q_indrect_tab : 4; /* [27:24] */ + u32 eps_q_indrect_stat : 2; /* [29:28] */ + u32 eps_q_indrect_mode : 1; /* [30] */ + u32 eps_q_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_q_indrect_ctrl_u; + +/* Define the union csr_eps_q_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_q_indrect_timeout_u; + +/* Define the union csr_eps_q_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_q_indrect_data_u; + +/* Define the union csr_eps_cos_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_indrect_addr : 24; /* [23:0] */ + u32 eps_cos_indrect_tab : 4; /* [27:24] */ + u32 eps_cos_indrect_stat : 2; /* [29:28] */ + u32 eps_cos_indrect_mode : 1; /* [30] */ + u32 eps_cos_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_indrect_ctrl_u; + +/* Define the union csr_eps_cos_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_indrect_timeout_u; + +/* Define the union csr_eps_cos_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_indrect_data_u; + +/* Define the union csr_eps_tc_p_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_tc_p_indrect_addr : 24; /* [23:0] */ + u32 eps_tc_p_indrect_tab : 4; /* [27:24] */ + u32 eps_tc_p_indrect_stat : 2; /* [29:28] */ + u32 eps_tc_p_indrect_mode : 1; /* [30] */ + u32 eps_tc_p_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_tc_p_indrect_ctrl_u; + +/* Define the union csr_eps_tc_p_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_tc_p_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_tc_p_indrect_timeout_u; + +/* Define the union csr_eps_tc_p_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_tc_p_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_tc_p_indrect_data_u; + +/* Define the union csr_eps_lb_q_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_q_indrect_addr : 24; /* [23:0] */ + u32 eps_lb_q_indrect_tab : 4; /* [27:24] */ + u32 eps_lb_q_indrect_stat : 2; /* [29:28] */ + u32 eps_lb_q_indrect_mode : 1; /* [30] */ + u32 eps_lb_q_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_q_indrect_ctrl_u; + +/* Define the union csr_eps_lb_q_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_q_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_q_indrect_timeout_u; + +/* Define the union csr_eps_lb_q_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_q_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_q_indrect_data_u; + +/* Define the union csr_eps_lb_p_t_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_p_t_indrect_addr : 24; /* [23:0] */ + u32 eps_lb_p_t_indrect_tab : 4; /* [27:24] */ + u32 eps_lb_p_t_indrect_stat : 2; /* [29:28] */ + u32 eps_lb_p_t_indrect_mode : 1; /* [30] */ + u32 eps_lb_p_t_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_p_t_indrect_ctrl_u; + +/* Define the union csr_eps_lb_p_t_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_p_t_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_p_t_indrect_timeout_u; + +/* Define the union csr_eps_lb_p_t_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_p_t_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_p_t_indrect_data_u; + +/* Define the union csr_eps_p_soft_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_port_soft_bp_cfg : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_p_soft_bp_cfg_u; + +/* Define the union csr_eps_cos_bp_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_bp_en_p0 : 8; /* [7:0] */ + u32 eps_cos_bp_en_p1 : 8; /* [15:8] */ + u32 eps_cos_bp_en_p2 : 8; /* [23:16] */ + u32 eps_cos_bp_en_p3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_bp_en0_u; + +/* Define the union csr_eps_cos_bp_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_bp_en_p4 : 8; /* [7:0] */ + u32 eps_cos_bp_en_p5 : 8; /* [15:8] */ + u32 eps_cos_bp_en_p6 : 8; /* [23:16] */ + u32 eps_cos_bp_en_p7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_bp_en1_u; + +/* Define the union csr_eps_bp_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_bp_mode : 8; /* [7:0] */ + u32 eps_rw_rsv0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_bp_mode_u; + +/* Define the union csr_eps_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_port_grp_cir_cfg : 25; /* [24:0] */ + u32 rsv_1 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_root_cir_cfg_u; + +/* Define the union csr_eps_lb_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_cir_cfg : 25; /* [24:0] */ + u32 rsv_2 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_root_cir_cfg_u; + +/* Define the union csr_eps_all_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_all_cir_cfg : 25; /* [24:0] */ + u32 rsv_3 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_all_cir_cfg_u; + +/* Define the union csr_eps_root_cir_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_root_cir_cnt : 26; /* [25:0] */ + u32 rsv_4 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_root_cir_cnt_u; + +/* Define the union csr_eps_lb_root_cir_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_root_cir_cnt : 26; /* [25:0] */ + u32 rsv_5 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_root_cir_cnt_u; + +/* Define the union csr_eps_root_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_root_wgt_cfg : 24; /* [23:0] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_root_wgt_cfg_u; + +/* Define the union csr_eps_nml_root_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_nml_root_wgt_cnt : 25; /* [24:0] */ + u32 rsv_7 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_nml_root_wgt_cnt_u; + +/* Define the union csr_eps_lb_root_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_root_wgt_cnt : 25; /* [24:0] */ + u32 rsv_8 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_root_wgt_cnt_u; + +/* Define the union csr_eps_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_mem_ecc_err0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_ecc_1bit_err_cnt_u; + +/* Define the union csr_eps_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_mem_ecc_err1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_ecc_2bit_err_cnt_u; + +/* Define the union csr_eps_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_dqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_dqs_cnt_u; + +/* Define the union csr_eps_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_eqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_eqs_cnt_u; + +/* Define the union csr_eps_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_fifo_cnt : 4; /* [3:0] */ + u32 rsv_9 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_fifo_cnt_u; + +/* Define the union csr_eps_inner_err_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sel_queue_err : 1; /* [0] */ + u32 dqs_qid_err : 1; /* [1] */ + u32 dqs_over_err : 1; /* [2] */ + u32 dqs_late_err : 1; /* [3] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_inner_err_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_eps_q_indrect_ctrl_u eps_q_indrect_ctrl; /* 0 */ + volatile csr_eps_q_indrect_timeout_u eps_q_indrect_timeout; /* 4 */ + volatile csr_eps_q_indrect_data_u eps_q_indrect_data; /* 8 */ + volatile csr_eps_cos_indrect_ctrl_u eps_cos_indrect_ctrl; /* 10 */ + volatile csr_eps_cos_indrect_timeout_u eps_cos_indrect_timeout; /* 14 */ + volatile csr_eps_cos_indrect_data_u eps_cos_indrect_data; /* 18 */ + volatile csr_eps_tc_p_indrect_ctrl_u eps_tc_p_indrect_ctrl; /* 20 */ + volatile csr_eps_tc_p_indrect_timeout_u eps_tc_p_indrect_timeout; /* 24 */ + volatile csr_eps_tc_p_indrect_data_u eps_tc_p_indrect_data; /* 28 */ + volatile csr_eps_lb_q_indrect_ctrl_u eps_lb_q_indrect_ctrl; /* 30 */ + volatile csr_eps_lb_q_indrect_timeout_u eps_lb_q_indrect_timeout; /* 34 */ + volatile csr_eps_lb_q_indrect_data_u eps_lb_q_indrect_data; /* 38 */ + volatile csr_eps_lb_p_t_indrect_ctrl_u eps_lb_p_t_indrect_ctrl; /* 40 */ + volatile csr_eps_lb_p_t_indrect_timeout_u eps_lb_p_t_indrect_timeout; /* 44 */ + volatile csr_eps_lb_p_t_indrect_data_u eps_lb_p_t_indrect_data; /* 48 */ + volatile csr_eps_p_soft_bp_cfg_u eps_p_soft_bp_cfg; /* 50 */ + volatile csr_eps_cos_bp_en0_u eps_cos_bp_en0; /* 54 */ + volatile csr_eps_cos_bp_en1_u eps_cos_bp_en1; /* 58 */ + volatile csr_eps_bp_mode_u eps_bp_mode; /* 5C */ + volatile csr_eps_root_cir_cfg_u eps_root_cir_cfg; /* 60 */ + volatile csr_eps_lb_root_cir_cfg_u eps_lb_root_cir_cfg; /* 64 */ + volatile csr_eps_all_cir_cfg_u eps_all_cir_cfg; /* 68 */ + volatile csr_eps_root_cir_cnt_u eps_root_cir_cnt; /* 6C */ + volatile csr_eps_lb_root_cir_cnt_u eps_lb_root_cir_cnt; /* 70 */ + volatile csr_eps_root_wgt_cfg_u eps_root_wgt_cfg; /* 78 */ + volatile csr_eps_nml_root_wgt_cnt_u eps_nml_root_wgt_cnt; /* 80 */ + volatile csr_eps_lb_root_wgt_cnt_u eps_lb_root_wgt_cnt; /* 84 */ + volatile csr_eps_ecc_1bit_err_cnt_u eps_ecc_1bit_err_cnt; /* 100 */ + volatile csr_eps_ecc_2bit_err_cnt_u eps_ecc_2bit_err_cnt; /* 104 */ + volatile csr_eps_dqs_cnt_u eps_dqs_cnt; /* 108 */ + volatile csr_eps_eqs_cnt_u eps_eqs_cnt; /* 10C */ + volatile csr_eps_fifo_cnt_u eps_fifo_cnt; /* 110 */ + volatile csr_eps_inner_err_st_u eps_inner_err_st; /* 114 */ +} S_esch_eps_csr_REGS_TYPE; + +/* Declare the struct pointor of the module esch_eps_csr */ +extern volatile S_esch_eps_csr_REGS_TYPE *gopesch_eps_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_addr(unsigned int ueps_q_indrect_addr); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_tab(unsigned int ueps_q_indrect_tab); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_stat(unsigned int ueps_q_indrect_stat); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_mode(unsigned int ueps_q_indrect_mode); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_vld(unsigned int ueps_q_indrect_vld); +int iSetEPS_Q_INDRECT_TIMEOUT_eps_q_indrect_timeout(unsigned int ueps_q_indrect_timeout); +int iSetEPS_Q_INDRECT_DATA_eps_q_indrect_data(unsigned int ueps_q_indrect_data); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_addr(unsigned int ueps_cos_indrect_addr); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_tab(unsigned int ueps_cos_indrect_tab); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_stat(unsigned int ueps_cos_indrect_stat); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_mode(unsigned int ueps_cos_indrect_mode); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_vld(unsigned int ueps_cos_indrect_vld); +int iSetEPS_COS_INDRECT_TIMEOUT_eps_cos_indrect_timeout(unsigned int ueps_cos_indrect_timeout); +int iSetEPS_COS_INDRECT_DATA_eps_cos_indrect_data(unsigned int ueps_cos_indrect_data); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_addr(unsigned int ueps_tc_p_indrect_addr); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_tab(unsigned int ueps_tc_p_indrect_tab); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_stat(unsigned int ueps_tc_p_indrect_stat); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_mode(unsigned int ueps_tc_p_indrect_mode); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_vld(unsigned int ueps_tc_p_indrect_vld); +int iSetEPS_TC_P_INDRECT_TIMEOUT_eps_tc_p_indrect_timeout(unsigned int ueps_tc_p_indrect_timeout); +int iSetEPS_TC_P_INDRECT_DATA_eps_tc_p_indrect_data(unsigned int ueps_tc_p_indrect_data); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_addr(unsigned int ueps_lb_q_indrect_addr); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_tab(unsigned int ueps_lb_q_indrect_tab); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_stat(unsigned int ueps_lb_q_indrect_stat); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_mode(unsigned int ueps_lb_q_indrect_mode); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_vld(unsigned int ueps_lb_q_indrect_vld); +int iSetEPS_LB_Q_INDRECT_TIMEOUT_eps_lb_q_indrect_timeout(unsigned int ueps_lb_q_indrect_timeout); +int iSetEPS_LB_Q_INDRECT_DATA_eps_lb_q_indrect_data(unsigned int ueps_lb_q_indrect_data); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_addr(unsigned int ueps_lb_p_t_indrect_addr); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_tab(unsigned int ueps_lb_p_t_indrect_tab); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_stat(unsigned int ueps_lb_p_t_indrect_stat); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_mode(unsigned int ueps_lb_p_t_indrect_mode); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_vld(unsigned int ueps_lb_p_t_indrect_vld); +int iSetEPS_LB_P_T_INDRECT_TIMEOUT_eps_lb_p_t_indrect_timeout(unsigned int ueps_lb_p_t_indrect_timeout); +int iSetEPS_LB_P_T_INDRECT_DATA_eps_lb_p_t_indrect_data(unsigned int ueps_lb_p_t_indrect_data); +int iSetEPS_P_SOFT_BP_CFG_eps_port_soft_bp_cfg(unsigned int ueps_port_soft_bp_cfg); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p0(unsigned int ueps_cos_bp_en_p0); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p1(unsigned int ueps_cos_bp_en_p1); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p2(unsigned int ueps_cos_bp_en_p2); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p3(unsigned int ueps_cos_bp_en_p3); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p4(unsigned int ueps_cos_bp_en_p4); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p5(unsigned int ueps_cos_bp_en_p5); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p6(unsigned int ueps_cos_bp_en_p6); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p7(unsigned int ueps_cos_bp_en_p7); +int iSetEPS_BP_MODE_eps_bp_mode(unsigned int ueps_bp_mode); +int iSetEPS_BP_MODE_eps_rw_rsv0(unsigned int ueps_rw_rsv0); +int iSetEPS_ROOT_CIR_CFG_eps_port_grp_cir_cfg(unsigned int ueps_port_grp_cir_cfg); +int iSetEPS_LB_ROOT_CIR_CFG_eps_lb_cir_cfg(unsigned int ueps_lb_cir_cfg); +int iSetEPS_ALL_CIR_CFG_eps_all_cir_cfg(unsigned int ueps_all_cir_cfg); +int iSetEPS_ROOT_CIR_CNT_eps_root_cir_cnt(unsigned int ueps_root_cir_cnt); +int iSetEPS_LB_ROOT_CIR_CNT_eps_lb_root_cir_cnt(unsigned int ueps_lb_root_cir_cnt); +int iSetEPS_ROOT_WGT_CFG_eps_root_wgt_cfg(unsigned int ueps_root_wgt_cfg); +int iSetEPS_NML_ROOT_WGT_CNT_eps_nml_root_wgt_cnt(unsigned int ueps_nml_root_wgt_cnt); +int iSetEPS_LB_ROOT_WGT_CNT_eps_lb_root_wgt_cnt(unsigned int ueps_lb_root_wgt_cnt); +int iSetEPS_ECC_1BIT_ERR_CNT_eps_mem_ecc_err0(unsigned int ueps_mem_ecc_err0); +int iSetEPS_ECC_2BIT_ERR_CNT_eps_mem_ecc_err1(unsigned int ueps_mem_ecc_err1); +int iSetEPS_DQS_CNT_eps_dqs_rec(unsigned int ueps_dqs_rec); +int iSetEPS_EQS_CNT_eps_eqs_rec(unsigned int ueps_eqs_rec); +int iSetEPS_FIFO_CNT_eps_fifo_cnt(unsigned int ueps_fifo_cnt); +int iSetEPS_INNER_ERR_ST_sel_queue_err(unsigned int usel_queue_err); +int iSetEPS_INNER_ERR_ST_dqs_qid_err(unsigned int udqs_qid_err); +int iSetEPS_INNER_ERR_ST_dqs_over_err(unsigned int udqs_over_err); +int iSetEPS_INNER_ERR_ST_dqs_late_err(unsigned int udqs_late_err); + +/* Define the union csr_hps_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_indrect_addr : 24; /* [23:0] */ + u32 hps_indrect_tab : 4; /* [27:24] */ + u32 hps_indrect_stat : 2; /* [29:28] */ + u32 hps_indrect_mode : 1; /* [30] */ + u32 hps_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hps_indrect_ctrl_u; + +/* Define the union csr_hps_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hps_indrect_timeout_u; + +/* Define the union csr_hps_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hps_indrect_data_u; + +/* Define the union csr_esch_hps_cppi_shap_type_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hp_shaper_pkt_len : 18; /* [17:0] */ + u32 rsv_0 : 2; /* [19:18] */ + u32 hps_up_shaper_type_cfg : 1; /* [20] */ + u32 rsv_1 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_cppi_shap_type_cfg_u; + +/* Define the union csr_esch_hps_soft_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_port_soft_bp_cfg : 6; /* [5:0] */ + u32 rsv_2 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_soft_bp_cfg_u; + +/* Define the union csr_esch_hps_root_shap_type_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hp_root_shaper_pkt_len : 18; /* [17:0] */ + u32 rsv_3 : 2; /* [19:18] */ + u32 hps_root_shaper_type_cfg : 1; /* [20] */ + u32 rsv_4 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_shap_type_cfg_u; + +/* Define the union csr_esch_hps_upq_shap_type_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_upq_shaper_type_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_upq_shap_type_cfg_u; + +/* Define the union csr_esch_hps_all_root_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_root_wgt_cfg : 12; /* [11:0] */ + u32 hps_root_wgt_cfg : 12; /* [23:12] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_all_root_wgt_cfg_u; + +/* Define the union csr_esch_hps_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_root_cir_cfg : 25; /* [24:0] */ + u32 rsv_6 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_cir_cfg_u; + +/* Define the union csr_esch_hps_lb_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_root_cir_cfg : 25; /* [24:0] */ + u32 rsv_7 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_root_cir_cfg_u; + +/* Define the union csr_esch_hps_lb_p_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_port_wgt_cfg : 12; /* [11:0] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_wgt_cfg_u; + +/* Define the union csr_esch_hps_lb_p_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_port_cir_cfg : 25; /* [24:0] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_cir_cfg_u; + +/* Define the union csr_esch_hps_lb_q_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_wgt_cfg : 12; /* [11:0] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_wgt_cfg_u; + +/* Define the union csr_esch_hps_lb_q_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_cir_cfg : 25; /* [24:0] */ + u32 rsv_11 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_cir_cfg_u; + +/* Define the union csr_esch_hps_root_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_root_wgtcnt : 25; /* [24:0] */ + u32 rsv_12 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_wgt_cnt_u; + +/* Define the union csr_esch_hps_lb_p_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_port_wgtcnt : 25; /* [24:0] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_wgt_cnt_u; + +/* Define the union csr_esch_hps_lb_q_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_wgtcnt : 25; /* [24:0] */ + u32 rsv_14 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_wgt_cnt_u; + +/* Define the union csr_esch_hps_root_cir_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_r_cir_token : 26; /* [25:0] */ + u32 rsv_15 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_cir_token_u; + +/* Define the union csr_esch_hps_lb_p_cir_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_p_cir_token : 26; /* [25:0] */ + u32 rsv_16 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_cir_token_u; + +/* Define the union csr_esch_hps_lb_q_cir_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_cir_token : 26; /* [25:0] */ + u32 rsv_17 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_cir_token_u; + +/* Define the union csr_esch_hps_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_mem_ecc_err0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_ecc_1bit_err_cnt_u; + +/* Define the union csr_esch_hps_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_mem_ecc_err1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_ecc_2bit_err_cnt_u; + +/* Define the union csr_esch_hps_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_dqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_dqs_cnt_u; + +/* Define the union csr_esch_hps_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_eqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_eqs_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hps_indrect_ctrl_u hps_indrect_ctrl; /* 0 */ + volatile csr_hps_indrect_timeout_u hps_indrect_timeout; /* 4 */ + volatile csr_hps_indrect_data_u hps_indrect_data; /* 8 */ + volatile csr_esch_hps_cppi_shap_type_cfg_u esch_hps_cppi_shap_type_cfg; /* 14 */ + volatile csr_esch_hps_soft_bp_cfg_u esch_hps_soft_bp_cfg; /* 18 */ + volatile csr_esch_hps_root_shap_type_cfg_u esch_hps_root_shap_type_cfg; /* 1C */ + volatile csr_esch_hps_upq_shap_type_cfg_u esch_hps_upq_shap_type_cfg; /* 60 */ + volatile csr_esch_hps_all_root_wgt_cfg_u esch_hps_all_root_wgt_cfg; /* 100 */ + volatile csr_esch_hps_root_cir_cfg_u esch_hps_root_cir_cfg; /* 104 */ + volatile csr_esch_hps_lb_root_cir_cfg_u esch_hps_lb_root_cir_cfg; /* 108 */ + volatile csr_esch_hps_lb_p_wgt_cfg_u esch_hps_lb_p_wgt_cfg[8]; /* 110 */ + volatile csr_esch_hps_lb_p_cir_cfg_u esch_hps_lb_p_cir_cfg[8]; /* 130 */ + volatile csr_esch_hps_lb_q_wgt_cfg_u esch_hps_lb_q_wgt_cfg[64]; /* 150 */ + volatile csr_esch_hps_lb_q_cir_cfg_u esch_hps_lb_q_cir_cfg[64]; /* 250 */ + volatile csr_esch_hps_root_wgt_cnt_u esch_hps_root_wgt_cnt[2]; /* 400 */ + volatile csr_esch_hps_lb_p_wgt_cnt_u esch_hps_lb_p_wgt_cnt[8]; /* 410 */ + volatile csr_esch_hps_lb_q_wgt_cnt_u esch_hps_lb_q_wgt_cnt[64]; /* 430 */ + volatile csr_esch_hps_root_cir_token_u esch_hps_root_cir_token[2]; /* 530 */ + volatile csr_esch_hps_lb_p_cir_token_u esch_hps_lb_p_cir_token[8]; /* 540 */ + volatile csr_esch_hps_lb_q_cir_token_u esch_hps_lb_q_cir_token[64]; /* 560 */ + volatile csr_esch_hps_ecc_1bit_err_cnt_u esch_hps_ecc_1bit_err_cnt; /* 660 */ + volatile csr_esch_hps_ecc_2bit_err_cnt_u esch_hps_ecc_2bit_err_cnt; /* 664 */ + volatile csr_esch_hps_dqs_cnt_u esch_hps_dqs_cnt; /* 668 */ + volatile csr_esch_hps_eqs_cnt_u esch_hps_eqs_cnt; /* 66C */ +} S_esch_hps_csr_REGS_TYPE; + +/* Declare the struct pointor of the module esch_hps_csr */ +extern volatile S_esch_hps_csr_REGS_TYPE *gopesch_hps_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetHPS_INDRECT_CTRL_hps_indrect_addr(unsigned int uhps_indrect_addr); +int iSetHPS_INDRECT_CTRL_hps_indrect_tab(unsigned int uhps_indrect_tab); +int iSetHPS_INDRECT_CTRL_hps_indrect_stat(unsigned int uhps_indrect_stat); +int iSetHPS_INDRECT_CTRL_hps_indrect_mode(unsigned int uhps_indrect_mode); +int iSetHPS_INDRECT_CTRL_hps_indrect_vld(unsigned int uhps_indrect_vld); +int iSetHPS_INDRECT_TIMEOUT_hps_indrect_timeout(unsigned int uhps_indrect_timeout); +int iSetHPS_INDRECT_DATA_hps_indrect_data(unsigned int uhps_indrect_data); +int iSetESCH_HPS_CPPI_SHAP_TYPE_CFG_hp_shaper_pkt_len(unsigned int uhp_shaper_pkt_len); +int iSetESCH_HPS_CPPI_SHAP_TYPE_CFG_hps_up_shaper_type_cfg(unsigned int uhps_up_shaper_type_cfg); +int iSetESCH_HPS_SOFT_BP_CFG_hps_port_soft_bp_cfg(unsigned int uhps_port_soft_bp_cfg); +int iSetESCH_HPS_ROOT_SHAP_TYPE_CFG_hp_root_shaper_pkt_len(unsigned int uhp_root_shaper_pkt_len); +int iSetESCH_HPS_ROOT_SHAP_TYPE_CFG_hps_root_shaper_type_cfg(unsigned int uhps_root_shaper_type_cfg); +int iSetESCH_HPS_UPQ_SHAP_TYPE_CFG_hps_upq_shaper_type_cfg(unsigned int uhps_upq_shaper_type_cfg); +int iSetESCH_HPS_ALL_ROOT_WGT_CFG_hps_lb_root_wgt_cfg(unsigned int uhps_lb_root_wgt_cfg); +int iSetESCH_HPS_ALL_ROOT_WGT_CFG_hps_root_wgt_cfg(unsigned int uhps_root_wgt_cfg); +int iSetESCH_HPS_ROOT_CIR_CFG_hps_root_cir_cfg(unsigned int uhps_root_cir_cfg); +int iSetESCH_HPS_LB_ROOT_CIR_CFG_hps_lb_root_cir_cfg(unsigned int uhps_lb_root_cir_cfg); +int iSetESCH_HPS_LB_P_WGT_CFG_hps_lb_port_wgt_cfg(unsigned int uhps_lb_port_wgt_cfg); +int iSetESCH_HPS_LB_P_CIR_CFG_hps_lb_port_cir_cfg(unsigned int uhps_lb_port_cir_cfg); +int iSetESCH_HPS_LB_Q_WGT_CFG_hps_lb_q_wgt_cfg(unsigned int uhps_lb_q_wgt_cfg); +int iSetESCH_HPS_LB_Q_CIR_CFG_hps_lb_q_cir_cfg(unsigned int uhps_lb_q_cir_cfg); +int iSetESCH_HPS_ROOT_WGT_CNT_hps_root_wgtcnt(unsigned int uhps_root_wgtcnt); +int iSetESCH_HPS_LB_P_WGT_CNT_hps_lb_port_wgtcnt(unsigned int uhps_lb_port_wgtcnt); +int iSetESCH_HPS_LB_Q_WGT_CNT_hps_lb_q_wgtcnt(unsigned int uhps_lb_q_wgtcnt); +int iSetESCH_HPS_ROOT_CIR_TOKEN_hps_lb_r_cir_token(unsigned int uhps_lb_r_cir_token); +int iSetESCH_HPS_LB_P_CIR_TOKEN_hps_lb_p_cir_token(unsigned int uhps_lb_p_cir_token); +int iSetESCH_HPS_LB_Q_CIR_TOKEN_hps_lb_q_cir_token(unsigned int uhps_lb_q_cir_token); +int iSetESCH_HPS_ECC_1BIT_ERR_CNT_hps_mem_ecc_err0(unsigned int uhps_mem_ecc_err0); +int iSetESCH_HPS_ECC_2BIT_ERR_CNT_hps_mem_ecc_err1(unsigned int uhps_mem_ecc_err1); +int iSetESCH_HPS_DQS_CNT_hps_dqs_rec(unsigned int uhps_dqs_rec); +int iSetESCH_HPS_EQS_CNT_hps_eqs_rec(unsigned int uhps_eqs_rec); + + +#endif // ESCH_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_reg_offset.h new file mode 100644 index 000000000..52f6a1cd0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_reg_offset.h @@ -0,0 +1,802 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : esch_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/11 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/12/11 20:09:31 Create file +// ****************************************************************************** + +#ifndef ESCH_REG_OFFSET_H +#define ESCH_REG_OFFSET_H + +/* ESCH_TOP_CSR Base address of Module's Register */ +#define CSR_ESCH_TOP_CSR_BASE (0xB000) + +/* **************************************************************************** */ +/* ESCH_TOP_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x0) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x4) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x8) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_3_REG (CSR_ESCH_TOP_CSR_BASE + 0xC) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x10) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x14) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x18) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x20) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x24) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x28) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x30) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x34) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x38) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x40) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x44) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x48) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x4C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x50) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x54) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x58) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x60) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x64) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x68) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x70) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x74) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x78) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x7C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x80) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x84) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x88) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x8C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x90) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x94) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x98) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x9C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_CFG_OK_REG (CSR_ESCH_TOP_CSR_BASE + 0xA0) /* ESCH使能配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_PPOP_BP_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0xA4) /* DFX CFG */ +#define CSR_ESCH_TOP_CSR_ESCH_PPOP_BP_ST_REG (CSR_ESCH_TOP_CSR_BASE + 0xA8) +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x100) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x104) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x108) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x10C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x110) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x114) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x118) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x11C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x120) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x124) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x128) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x12C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x130) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x134) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x138) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x13C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x140) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x144) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x148) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x14C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x150) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x154) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x158) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x15C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x160) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x164) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x168) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x16C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x170) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x174) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x178) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x17C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x180) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x184) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x188) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x18C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x190) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x194) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x198) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x19C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x1AC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x1BC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x1CC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x1DC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x1EC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x1FC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_64_REG (CSR_ESCH_TOP_CSR_BASE + 0x200) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_65_REG (CSR_ESCH_TOP_CSR_BASE + 0x204) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_66_REG (CSR_ESCH_TOP_CSR_BASE + 0x208) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_67_REG (CSR_ESCH_TOP_CSR_BASE + 0x20C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_68_REG (CSR_ESCH_TOP_CSR_BASE + 0x210) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_69_REG (CSR_ESCH_TOP_CSR_BASE + 0x214) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_70_REG (CSR_ESCH_TOP_CSR_BASE + 0x218) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_71_REG (CSR_ESCH_TOP_CSR_BASE + 0x21C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_72_REG (CSR_ESCH_TOP_CSR_BASE + 0x220) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_73_REG (CSR_ESCH_TOP_CSR_BASE + 0x224) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_74_REG (CSR_ESCH_TOP_CSR_BASE + 0x228) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_75_REG (CSR_ESCH_TOP_CSR_BASE + 0x22C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_76_REG (CSR_ESCH_TOP_CSR_BASE + 0x230) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_77_REG (CSR_ESCH_TOP_CSR_BASE + 0x234) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_78_REG (CSR_ESCH_TOP_CSR_BASE + 0x238) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_79_REG (CSR_ESCH_TOP_CSR_BASE + 0x23C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_80_REG (CSR_ESCH_TOP_CSR_BASE + 0x240) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_81_REG (CSR_ESCH_TOP_CSR_BASE + 0x244) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_82_REG (CSR_ESCH_TOP_CSR_BASE + 0x248) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_83_REG (CSR_ESCH_TOP_CSR_BASE + 0x24C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_84_REG (CSR_ESCH_TOP_CSR_BASE + 0x250) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_85_REG (CSR_ESCH_TOP_CSR_BASE + 0x254) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_86_REG (CSR_ESCH_TOP_CSR_BASE + 0x258) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_87_REG (CSR_ESCH_TOP_CSR_BASE + 0x25C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_88_REG (CSR_ESCH_TOP_CSR_BASE + 0x260) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_89_REG (CSR_ESCH_TOP_CSR_BASE + 0x264) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_90_REG (CSR_ESCH_TOP_CSR_BASE + 0x268) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_91_REG (CSR_ESCH_TOP_CSR_BASE + 0x26C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_92_REG (CSR_ESCH_TOP_CSR_BASE + 0x270) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_93_REG (CSR_ESCH_TOP_CSR_BASE + 0x274) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_94_REG (CSR_ESCH_TOP_CSR_BASE + 0x278) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_95_REG (CSR_ESCH_TOP_CSR_BASE + 0x27C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_96_REG (CSR_ESCH_TOP_CSR_BASE + 0x280) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_97_REG (CSR_ESCH_TOP_CSR_BASE + 0x284) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_98_REG (CSR_ESCH_TOP_CSR_BASE + 0x288) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_99_REG (CSR_ESCH_TOP_CSR_BASE + 0x28C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_100_REG (CSR_ESCH_TOP_CSR_BASE + 0x290) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_101_REG (CSR_ESCH_TOP_CSR_BASE + 0x294) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_102_REG (CSR_ESCH_TOP_CSR_BASE + 0x298) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_103_REG (CSR_ESCH_TOP_CSR_BASE + 0x29C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_104_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_105_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_106_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_107_REG (CSR_ESCH_TOP_CSR_BASE + 0x2AC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_108_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_109_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_110_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_111_REG (CSR_ESCH_TOP_CSR_BASE + 0x2BC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_112_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_113_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_114_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_115_REG (CSR_ESCH_TOP_CSR_BASE + 0x2CC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_116_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_117_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_118_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_119_REG (CSR_ESCH_TOP_CSR_BASE + 0x2DC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_120_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_121_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_122_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_123_REG (CSR_ESCH_TOP_CSR_BASE + 0x2EC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_124_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_125_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_126_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_127_REG (CSR_ESCH_TOP_CSR_BASE + 0x2FC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_128_REG (CSR_ESCH_TOP_CSR_BASE + 0x300) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_129_REG (CSR_ESCH_TOP_CSR_BASE + 0x304) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_130_REG (CSR_ESCH_TOP_CSR_BASE + 0x308) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_131_REG (CSR_ESCH_TOP_CSR_BASE + 0x30C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_132_REG (CSR_ESCH_TOP_CSR_BASE + 0x310) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_133_REG (CSR_ESCH_TOP_CSR_BASE + 0x314) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_134_REG (CSR_ESCH_TOP_CSR_BASE + 0x318) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_135_REG (CSR_ESCH_TOP_CSR_BASE + 0x31C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_136_REG (CSR_ESCH_TOP_CSR_BASE + 0x320) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_137_REG (CSR_ESCH_TOP_CSR_BASE + 0x324) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_138_REG (CSR_ESCH_TOP_CSR_BASE + 0x328) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_139_REG (CSR_ESCH_TOP_CSR_BASE + 0x32C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_140_REG (CSR_ESCH_TOP_CSR_BASE + 0x330) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_141_REG (CSR_ESCH_TOP_CSR_BASE + 0x334) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_142_REG (CSR_ESCH_TOP_CSR_BASE + 0x338) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_143_REG (CSR_ESCH_TOP_CSR_BASE + 0x33C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_144_REG (CSR_ESCH_TOP_CSR_BASE + 0x340) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_145_REG (CSR_ESCH_TOP_CSR_BASE + 0x344) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_146_REG (CSR_ESCH_TOP_CSR_BASE + 0x348) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_147_REG (CSR_ESCH_TOP_CSR_BASE + 0x34C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_148_REG (CSR_ESCH_TOP_CSR_BASE + 0x350) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_149_REG (CSR_ESCH_TOP_CSR_BASE + 0x354) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_150_REG (CSR_ESCH_TOP_CSR_BASE + 0x358) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_151_REG (CSR_ESCH_TOP_CSR_BASE + 0x35C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_152_REG (CSR_ESCH_TOP_CSR_BASE + 0x360) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_153_REG (CSR_ESCH_TOP_CSR_BASE + 0x364) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_154_REG (CSR_ESCH_TOP_CSR_BASE + 0x368) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_155_REG (CSR_ESCH_TOP_CSR_BASE + 0x36C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_156_REG (CSR_ESCH_TOP_CSR_BASE + 0x370) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_157_REG (CSR_ESCH_TOP_CSR_BASE + 0x374) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_158_REG (CSR_ESCH_TOP_CSR_BASE + 0x378) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_159_REG (CSR_ESCH_TOP_CSR_BASE + 0x37C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_160_REG (CSR_ESCH_TOP_CSR_BASE + 0x380) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_161_REG (CSR_ESCH_TOP_CSR_BASE + 0x384) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_162_REG (CSR_ESCH_TOP_CSR_BASE + 0x388) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_163_REG (CSR_ESCH_TOP_CSR_BASE + 0x38C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_164_REG (CSR_ESCH_TOP_CSR_BASE + 0x390) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_165_REG (CSR_ESCH_TOP_CSR_BASE + 0x394) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_166_REG (CSR_ESCH_TOP_CSR_BASE + 0x398) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_167_REG (CSR_ESCH_TOP_CSR_BASE + 0x39C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_168_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_169_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_170_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_171_REG (CSR_ESCH_TOP_CSR_BASE + 0x3AC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_172_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_173_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_174_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_175_REG (CSR_ESCH_TOP_CSR_BASE + 0x3BC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_176_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_177_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_178_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_179_REG (CSR_ESCH_TOP_CSR_BASE + 0x3CC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_180_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_181_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_182_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_183_REG (CSR_ESCH_TOP_CSR_BASE + 0x3DC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_184_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_185_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_186_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_187_REG (CSR_ESCH_TOP_CSR_BASE + 0x3EC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_188_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_189_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_190_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_191_REG (CSR_ESCH_TOP_CSR_BASE + 0x3FC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x400) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x404) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x408) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x40C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x410) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x414) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x418) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x41C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x420) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x424) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x428) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x42C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x430) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x434) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x438) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x43C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x440) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x444) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x448) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x44C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x450) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x454) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x458) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x45C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x460) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x464) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x468) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x46C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x470) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x474) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x478) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x47C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x480) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x500) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x504) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x508) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x50C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x510) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x514) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x518) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x51C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x520) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x524) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x528) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x52C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x530) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x534) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x538) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x53C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x540) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x544) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x548) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x54C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x550) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x554) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x558) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x55C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x560) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x564) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x568) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x56C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x570) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x574) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x578) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x57C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x580) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x584) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x588) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x58C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x590) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x594) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x598) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x59C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x5AC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x5BC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x5CC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x5DC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x5EC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x5FC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x600) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x604) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x608) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x60C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x610) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x614) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x618) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x61C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x620) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x624) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x628) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x62C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x630) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x634) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x638) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x63C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x640) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x644) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x648) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x64C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x650) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x654) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x658) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x65C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x660) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x664) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x668) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x66C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x670) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x674) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x678) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x67C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x680) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x684) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x688) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x68C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x690) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x694) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x698) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x69C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x6AC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x6BC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x6CC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x6DC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x6EC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x6FC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x700) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x704) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x708) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_CTRL_REG (CSR_ESCH_TOP_CSR_BASE + 0x750) /* MEM 配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_ERR_REQ0_REG (CSR_ESCH_TOP_CSR_BASE + 0x754) /* MEM 配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_ERR_REQ1_REG (CSR_ESCH_TOP_CSR_BASE + 0x758) /* MEM 配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT_VECTOR_REG (CSR_ESCH_TOP_CSR_BASE + 0x760) /* 中断向量 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT_REG (CSR_ESCH_TOP_CSR_BASE + 0x764) /* 中断状态 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT_EN_REG (CSR_ESCH_TOP_CSR_BASE + 0x768) /* 中断屏蔽 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY0_REG (CSR_ESCH_TOP_CSR_BASE + 0x76C) /* 中断0的sticky信息 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY1_REG (CSR_ESCH_TOP_CSR_BASE + 0x770) /* 中断1的sticky信息 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY2_REG (CSR_ESCH_TOP_CSR_BASE + 0x774) /* 中断2的sticky信息 */ +#define CSR_ESCH_TOP_CSR_ESCH_FCNP_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0x778) /* FCNPshaper固定桶深配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_CPB_CH_CDT_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0x77C) /* 信用深度统计 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_NML_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x780) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_UP_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x784) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_LB_COS_HIGH_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x788) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_LB_COS_LOW_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x78C) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_EPS_COS_HIGH_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x790) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_EPS_COS_LOW_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x794) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_EPS_LB_TYPE_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x79C) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_MAG_HIGH_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x7A0) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_MAG_LOW_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x7A4) /* 信用反压 */ + +/* ESCH_EPS_CSR Base address of Module's Register */ +#define CSR_ESCH_EPS_CSR_BASE (0xA800) + +/* **************************************************************************** */ +/* ESCH_EPS_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x0) /* EPS 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x4) /* EPS 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x8) /* EPS 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x10) /* EPS COS间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x14) /* EPS COS间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x18) /* EPS COS间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x20) /* EPS TC和Port间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x24) /* EPS TC和Port间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x28) /* EPS TC和Port间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x30) /* EPS LB 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x34) /* EPS LB 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x38) /* EPS LB 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x40) /* EPS LB Port和Type间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x44) /* EPS LB Port和Type间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x48) /* EPS LB Port和Type间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_P_SOFT_BP_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x50) /* EPS PORT节点软反压配置 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_BP_EN0_REG (CSR_ESCH_EPS_CSR_BASE + 0x54) /* ETH端口队列反压响应使能寄存器0 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_BP_EN1_REG (CSR_ESCH_EPS_CSR_BASE + 0x58) /* ETH端口队列反压响应使能寄存器1 */ +#define CSR_ESCH_EPS_CSR_EPS_BP_MODE_REG (CSR_ESCH_EPS_CSR_BASE + 0x5C) /* EPS BP 模式配置 register. */ +#define CSR_ESCH_EPS_CSR_EPS_ROOT_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x60) /* EPS PORT GRP CIR shaper配置 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x64) /* EPS LB PORT GRP CIR shaper配置 */ +#define CSR_ESCH_EPS_CSR_EPS_ALL_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x68) /* EPS ALL CIR shaper配置 */ +#define CSR_ESCH_EPS_CSR_EPS_ROOT_CIR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x6C) /* EPS_ROOT_CIR_CNT */ +#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_CIR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x70) /* EPS_LB_ROOT_CIR_CNT */ +#define CSR_ESCH_EPS_CSR_EPS_ROOT_WGT_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x78) /* EPS_ROOT_WGT_CNT */ +#define CSR_ESCH_EPS_CSR_EPS_NML_ROOT_WGT_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x80) /* NML ROOT_WGT */ +#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_WGT_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x84) /* LB_ROOT_WGT */ +#define CSR_ESCH_EPS_CSR_EPS_ECC_1BIT_ERR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x100) /* EPS 1bit ECC错误计数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_ECC_2BIT_ERR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x104) /* EPS 2bit ECC错误计数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_DQS_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x108) /* 出队次数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_EQS_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x10C) /* 入队次数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_FIFO_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x110) /* EPS FIFO当前深度 */ +#define CSR_ESCH_EPS_CSR_EPS_INNER_ERR_ST_REG (CSR_ESCH_EPS_CSR_BASE + 0x114) /* EPS 内部错误状态 */ + +/* ESCH_HPS_CSR Base address of Module's Register */ +#define CSR_ESCH_HPS_CSR_BASE (0xA000) + +/* **************************************************************************** */ +/* ESCH_HPS_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_ESCH_HPS_CSR_HPS_INDRECT_CTRL_REG (CSR_ESCH_HPS_CSR_BASE + 0x0) /* 间接访问寄存器 */ +#define CSR_ESCH_HPS_CSR_HPS_INDRECT_TIMEOUT_REG (CSR_ESCH_HPS_CSR_BASE + 0x4) /* 间接访问寄存器 */ +#define CSR_ESCH_HPS_CSR_HPS_INDRECT_DATA_REG (CSR_ESCH_HPS_CSR_BASE + 0x8) /* 间接访问寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_CPPI_SHAP_TYPE_CFG_REG \ + (CSR_ESCH_HPS_CSR_BASE + 0x14) /* HPS CPPI PORT SHAPER整形类型配置寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_SOFT_BP_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x18) /* HPS PORT节点软反压配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_SHAP_TYPE_CFG_REG \ + (CSR_ESCH_HPS_CSR_BASE + 0x1C) /* HPS CPPI PORT SHAPER整形类型配置寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_UPQ_SHAP_TYPE_CFG_REG \ + (CSR_ESCH_HPS_CSR_BASE + 0x60) /* HPS UP QUEUE SHAPER整形类型配置寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ALL_ROOT_WGT_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x100) /* ROOT DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x104) /* Normal RootCIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_ROOT_CIR_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x108) /* loopback RootCIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x110) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x114) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x118) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x11C) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x120) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x124) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x128) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x12C) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x130) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x134) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x138) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x13C) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x140) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x144) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x148) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x14C) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x150) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x154) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x158) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x15C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x160) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x164) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x168) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x16C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x170) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x174) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x178) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x17C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x180) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x184) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x188) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x18C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x190) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x194) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x198) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x19C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x1AC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x1BC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x1CC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x1DC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x1EC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x1FC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x200) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x204) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x208) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x20C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x210) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x214) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x218) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x21C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x220) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x224) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x228) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x22C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x230) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x234) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x238) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x23C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x240) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x244) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x248) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x24C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x250) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x254) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x258) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x25C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x260) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x264) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x268) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x26C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x270) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x274) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x278) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x27C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x280) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x284) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x288) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x28C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x290) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x294) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x298) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x29C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x2AC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x2BC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x2CC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x2DC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x2EC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x2FC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x300) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x304) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x308) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x30C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x310) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x314) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x318) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x31C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x320) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x324) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x328) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x32C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x330) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x334) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x338) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x33C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x340) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x344) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x348) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x34C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x400) /* ROOT级 DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x404) /* ROOT级 DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x410) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x414) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x418) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x41C) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x420) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x424) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x428) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x42C) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x430) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x434) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x438) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x43C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x440) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x444) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x448) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x44C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x450) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x454) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x458) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x45C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x460) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x464) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x468) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x46C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x470) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x474) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x478) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x47C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x480) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x484) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x488) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x48C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x490) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x494) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x498) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x49C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x4AC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x4BC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x4CC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x4DC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x4EC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x4FC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x500) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x504) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x508) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x50C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x510) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x514) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x518) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x51C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x520) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x524) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x528) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x52C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x530) /* ROOT CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x534) /* ROOT CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x540) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x544) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x548) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x54C) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x550) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x554) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x558) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x55C) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x560) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x564) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x568) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x56C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x570) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x574) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x578) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x57C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x580) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x584) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x588) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x58C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x590) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x594) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x598) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x59C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x5AC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x5BC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x5CC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x5DC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x5EC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x5FC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x600) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x604) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x608) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x60C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x610) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x614) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x618) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x61C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x620) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x624) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x628) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x62C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x630) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x634) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x638) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x63C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x640) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x644) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x648) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x64C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x650) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x654) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x658) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x65C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ECC_1BIT_ERR_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x660) /* HPS 1bit ECC错误计数统计 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ECC_2BIT_ERR_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x664) /* HPS 2bit ECC错误计数统计 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_DQS_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x668) /* 出队次数统计 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_EQS_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x66C) /* 入队次数统计 */ + +#endif // ESCH_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_addr_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_addr_define.h new file mode 100644 index 000000000..3461ea022 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_addr_define.h @@ -0,0 +1,384 @@ +#ifndef HI1823_CSR_SM_ADDR_DEFINE_H +#define HI1823_CSR_SM_ADDR_DEFINE_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* * __cplusplus */ + +/* * smrt_csr base address */ +#define CSR_SMRT_CSR_BASE_ADDR 0xa00 + +/* * SMRT_CSR address */ +#define CSR_SMRT_VERSION_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x0) +#define CSR_SMXR_CFG1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x4) +#define CSR_SMXR_CFG0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x8) +#define CSR_SMXT_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0xC) +#define CSR_SMXR_TM_GRT01_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x10) +#define CSR_SMXR_TM_GRT23_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x14) +#define CSR_SMRT_INT_VECTOR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x18) +#define CSR_SMRT_INT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x1C) +#define CSR_SMRT_INT_MASK_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x20) +#define CSR_SMXR_REQ_MEM_CRT_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x24) +#define CSR_SMXR_REQ_MEM_UNCRT_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x28) +#define CSR_SMXR_MISS_SOP_EOP_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x2C) +#define CSR_SMXR_INDRECT_CTRL_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x30) +#define CSR_SMXR_INDRECT_TIMEOUT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x34) +#define CSR_SMXR_INDRECT_DATA_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x38) +#define CSR_SMXT_CAP_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x3C) +#define CSR_SMXT_CAP_FIELD_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x40) +#define CSR_SMXT_CNT_CFG0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x44) +#define CSR_SMXT_CNT_CFG1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x48) +#define CSR_SMXT_CNT0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x4C) +#define CSR_SMXT_CNT1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x50) +#define CSR_SMXT_CNT2_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x54) +#define CSR_SMXT_CNT3_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x58) +#define CSR_SMXT_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x5C) +#define CSR_SMXT_FIFO_DEPTH0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x60) +#define CSR_SMXT_FIFO_DEPTH1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x68) +#define CSR_TL0_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x6C) +#define CSR_TL1_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x70) +#define CSR_RQST_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x74) +#define CSR_RSP_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x78) +#define CSR_RQST_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x7C) +#define CSR_RESP_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x80) +#define CSR_SMXR_CNT0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x84) +#define CSR_SMXR_CNT1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x88) +#define CSR_SMXR_CNT2_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x8C) +#define CSR_SMXR_CNT3_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x90) +#define CSR_SMXT_CTP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x94) +/* * smir_csr base address */ +#define CSR_SMIR_CSR_BASE_ADDR 0x100 + +/* * SMIR_CSR address */ +#define CSR_SMIR_VERSION_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x0) +#define CSR_SMIR_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x4) +#define CSR_SMIR_HASH_SEED0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x8) +#define CSR_SMIR_HASH_SEED1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC) +#define CSR_SMIR_INT_VECTOR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x10) +#define CSR_SMIR_INT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x14) +#define CSR_SMIR_INT_MASK_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x18) +#define CSR_SMIR_ERR_SPEC_TH_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x1C) +#define CSR_SMIR_REQ_MSG_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x20) +#define CSR_SMIR_RESP_MSG_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x24) +#define CSR_SMIR_MEM_ECC_CRT_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x28) +#define CSR_SMIR_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x2C) +#define CSR_SMIR_INDRECT_CTRL_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x30) +#define CSR_SMIR_INDRECT_TIMEOUT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x34) +#define CSR_SMIR_INDRECT_DATA_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x38) +#define CSR_SMIR_CAP0_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x3C) +#define CSR_SMIR_CAP1_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x40) +#define CSR_SMIR_CAP2_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x44) +#define CSR_SMIR_CAP3_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x48) +#define CSR_SMIR_CAP4_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x4C) +#define CSR_SMIR_CAP6_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x50) +#define CSR_SMIR_EN_CNT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x54) +#define CSR_SMIR_CNT0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x58) +#define CSR_SMIR_CNT1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x5C) +#define CSR_SMIR_CNT2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x60) +#define CSR_SMIR_CRDT_CNT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x64) +#define CSR_SMIR_CAP_FLIT0_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x68) +#define CSR_SMIR_CAP_FLIT0_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x70) +#define CSR_SMIR_CAP_FLIT1_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x78) +#define CSR_SMIR_CAP_FLIT1_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x80) +#define CSR_SMIR_CAP_FLIT2_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x88) +#define CSR_SMIR_CAP_FLIT2_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x90) +#define CSR_SMIR_CAP_FLIT3_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x98) +#define CSR_SMIR_CAP_FLIT3_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xA0) +#define CSR_SMIR_CAP_FLIT4_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xA8) +#define CSR_SMIR_CAP_FLIT4_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xB0) +#define CSR_SMIR_CAP_FLIT5_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xB8) +#define CSR_SMIR_CAP_FLIT5_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC0) +#define CSR_SMIR_CAP_FLIT0_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC8) +#define CSR_SMIR_CAP_FLIT1_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xCC) +#define CSR_SMIR_CAP_FLIT2_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD0) +#define CSR_SMIR_CAP_FLIT3_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD4) +#define CSR_SMIR_CAP_FLIT4_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD8) +#define CSR_SMIR_CAP_FLIT5_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xDC) +/* * smeg0_abuf0_csr base address */ +#define CSR_SMEG0_ABUF0_CSR_BASE_ADDR 0x200 + +/* * SMEG0_ABUF0_CSR address */ +#define CSR_SMEG0_ABUF0_VERSION_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x0) +#define CSR_SM_ABUF_TH_GRW_WM_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x4) +#define CSR_SM_ABUF_TH_GRW_WM_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x8) +#define CSR_SM_ABUF_TH_GRW_WM_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC) +#define CSR_SM_ABUF_TH_GRW_WM_3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x10) +#define CSR_SM_ABUF_TH_GRW_WM_4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x14) +#define CSR_SM_ABUF_TH_GRW_WM_5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x18) +#define CSR_SM_ABUF_TH_GRW_WM_6_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x1C) +#define CSR_SM_ABUF_TH_SHK_WM_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x20) +#define CSR_SM_ABUF_TH_SHK_WM_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x24) +#define CSR_SM_ABUF_TH_SHK_WM_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x28) +#define CSR_SM_ABUF_TH_SHK_WM_3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x2C) +#define CSR_SM_ABUF_TH_SHK_WM_4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x30) +#define CSR_SM_ABUF_TH_SHK_WM_5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x34) +#define CSR_SM_ABUF_TH_SHK_WM_6_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x38) +#define CSR_SM_ABUF_FLRC_ATTR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x3C) +#define CSR_SM_ABUF_FLRC_NUM_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x40) +#define CSR_SM_ABUF_FLRC_BOUND_U_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x44) +#define CSR_SM_ABUF_FLRC_BOUND_L_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x48) +#define CSR_SM_ABUF_PF_LIFO_CLR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x4C) +#define CSR_SM_ABUF_MEM_CFG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x50) +#define CSR_SM_ABUF_INT_VECTOR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x54) +#define CSR_SM_ABUF_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x58) +#define CSR_SM_ABUF_INT_MASK_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x5C) +#define CSR_SM_ABUF_PBERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x60) +#define CSR_SM_ABUF_FL_UFLOW_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x64) +#define CSR_SM_ABUF_FL_OFLOW_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x68) +#define CSR_SM_ABUF_FL_TAIL_MISS_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x6C) +#define CSR_SMEG0_ABUF_INDRECT_CTRL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x70) +#define CSR_SMEG0_ABUF_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x74) +#define CSR_SMEG0_ABUF_INDRECT_DATA_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x78) +#define CSR_SM_ABUF_DIS_ALLOC_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x7C) +#define CSR_SM_ABUF_DIS_DE_ALLOC_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x80) +#define CSR_SM_ABUF_FLRC_ST_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x84) +#define CSR_SM_ABUF_EMPTY_FL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x88) +#define CSR_SM_ABUF_FULL_FL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x8C) +#define CSR_SM_ABUF_ST_WM_GROW_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x90) +#define CSR_SM_ABUF_ST_WM_SHRINK_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x94) +#define CSR_SM_ABUF_CNT_SEL0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x98) +#define CSR_SM_ABUF_CNT_SEL1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x9C) +#define CSR_SM_ABUF_COUNTER0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA0) +#define CSR_SM_ABUF_COUNTER1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA4) +#define CSR_SM_ABUF_COUNTER2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA8) +#define CSR_SM_ABUF_COUNTER3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xAC) +#define CSR_SM_ABUF_COUNTER4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB0) +#define CSR_SM_ABUF_COUNTER5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB4) +#define CSR_SM_ABUF_PFETCH_FLAG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB8) +#define CSR_SM_ABUF_IREQ_LIST_STA_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xBC) +#define CSR_SM_ABUF_TAIL_MISS0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC0) +#define CSR_SM_ABUF_TAIL_MISS1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC8) +#define CSR_SM_ABUF_CNT_LIFO_PFETCH_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xD0) +#define CSR_SM_ABUF_CNT_LIFO_PFETCH_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xD8) +#define CSR_SM_ABUF_CNT_LIFO_PFETCH_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE0) +#define CSR_SM_ABUF_ECC_CFG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE4) +#define CSR_SM_ABUF_ECC_1B_ERR_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE8) +#define CSR_SM_ABUF_ECC_2B_ERR_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xEC) +/* * smeg0_aget_csr base address */ +#define CSR_SMEG0_AGET_CSR_BASE_ADDR 0x300 + +/* * SMEG0_AGET_CSR address */ +#define CSR_SMEG0_AGET_VERSION_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x0) +#define CSR_SMEG0_AGET_CFG_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x4) +#define CSR_SMEG0_AGET_INT_VECTOR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x8) +#define CSR_SMEG0_AGET_INT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0xC) +#define CSR_SMEG0_AGET_INT_MASK_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x10) +#define CSR_SMEG0_AGET_MEM_PRTY_ERR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x14) +#define CSR_SMEG0_AGET_BOUNDARY_ERR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x18) +#define CSR_SMEG0_AGET_INDRECT_CTRL_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x1C) +#define CSR_SMEG0_AGET_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x20) +#define CSR_SMEG0_AGET_INDRECT_DATA_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x24) +#define CSR_SMEG_CORE_MEM_INIT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x28) +#define CSR_SMEG0_CNT0_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x2C) +#define CSR_SMEG0_CNT1_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x30) +/* * smeg0_lu_csr base address */ +#define CSR_SMEG0_LU_CSR_BASE_ADDR 0x400 + +/* * SMEG0_LU_CSR address */ +#define CSR_SMEG0_LU_VERSION_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x0) +#define CSR_SMEG0_LU_CHK_ENABLE_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x4) +#define CSR_SMEG0_LU_INT_VECTOR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x8) +#define CSR_SMEG0_LU_INT_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0xC) +#define CSR_SMEG0_LU_INT_MASK_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x10) +#define CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x14) +#define CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x18) +#define CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x1C) +#define CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x20) +#define CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x24) +#define CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x28) +#define CSR_SMEG0_LU_SW_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x2C) +#define CSR_SMEG0_LU_INDRECT_CTRL_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x30) +#define CSR_SMEG0_LU_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x34) +#define CSR_SMEG0_LU_INDRECT_DATA_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x38) +#define CSR_SMEG0_LU_ERR_INJ_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x3C) +#define CSR_SMEG0_LU_CNT_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x40) +#define CSR_SMEG0_LU_CNT0_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x44) +#define CSR_SMEG0_LU_CNT1_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x48) +#define CSR_SMEG0_LU_CNT2_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x4C) +#define CSR_SMEG0_LU_CNT3_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x50) +#define CSR_SMEG0_LU_CTP_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x54) +/* * smeg1_csr base address */ +#define CSR_SMEG1_CSR_BASE_ADDR 0x500 + +/* * SMEG1_CSR address */ +#define CSR_SMEG1_VERSION_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x0) +#define CSR_SMEG1_CFG0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x4) +#define CSR_SMEG1_CFG1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x8) +#define CSR_SMEG1_RUNAWAY_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC) +#define CSR_SMEG1_THREAD_ENABLE_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x10) +#define CSR_SMEG1_TM_TS_FAST2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x14) +#define CSR_SMEG1_TM_TS_FAST3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x18) +#define CSR_SMEG1_TM_TS_SLOW0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x1C) +#define CSR_SMEG1_TM_TS_SLOW1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x20) +#define CSR_SMEG1_TM_TMT_CFG7_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x24) +#define CSR_SMEG1_TM_TMT_CFG6_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x28) +#define CSR_SMEG1_TM_TMT_CFG5_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x2C) +#define CSR_SMEG1_TM_TMT_CFG4_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x30) +#define CSR_SMEG1_TM_TMT_CFG3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x34) +#define CSR_SMEG1_TM_TMT_CFG2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x38) +#define CSR_SMEG1_TM_TMT_CFG1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x3C) +#define CSR_SMEG1_TM_TMT_CFG0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x40) +#define CSR_SMEG1_INT_VECTOR_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x44) +#define CSR_SMEG1_INT_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x48) +#define CSR_SMEG1_INT_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x4C) +#define CSR_SMEG1_ENGINE_SW_ERR_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x50) +#define CSR_SMEG1_ERR0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x54) +#define CSR_SMEG1_ERR0_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x58) +#define CSR_SMEG1_ERR1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x5C) +#define CSR_SMEG1_ERR1_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x60) +#define CSR_SMEG1_INDRECT_CTRL_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x64) +#define CSR_SMEG1_INDRECT_TIMEOUT_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x68) +#define CSR_SMEG1_INDRECT_DATA_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x6C) +#define CSR_SMEG1_CNT_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x70) +#define CSR_SMEG1_CNT_MATCH_ID_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x74) +#define CSR_SMEG1_CNT0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x78) +#define CSR_SMEG1_CNT1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x80) +#define CSR_SMEG1_CNT2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x88) +#define CSR_SMEG1_CNT3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x90) +#define CSR_SMEG1_TCD_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x98) +#define CSR_SMEG1_RUNAWAY_THD_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x9C) +#define CSR_SMEG1_CTP0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xA0) +#define CSR_SMEG1_CTP1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xA8) +#define CSR_SMEG1_CTP2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB0) +#define CSR_SMEG1_TMT_EXT_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB4) +#define CSR_SMEG1_MEM_ECC_ERR_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB8) +#define CSR_SMMC_CACHE_RESOURCE_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xBC) +#define CSR_SMEG1_SYNC_API_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC0) +#define CSR_SMEG1_CUR_TIMESTAMP_US_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC8) +/* * smit_csr base address */ +#define CSR_SMIT_CSR_BASE_ADDR 0x600 + +/* * SMIT_CSR address */ +#define CSR_SMIT_VERSION_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x0) +#define CSR_SMIT_CFG_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x4) +#define CSR_SMIT_INT_VECTOR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x8) +#define CSR_SMIT_INT_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0xC) +#define CSR_SMIT_INT_MASK_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x10) +#define CSR_SMIT_ERR_PRTY_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x14) +#define CSR_SMIT_MEM_ECC_CRT_ERR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x18) +#define CSR_SMIT_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x1C) +#define CSR_SMIT_INDRECT_CTRL_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x20) +#define CSR_SMIT_INDRECT_TIMEOUT_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x24) +#define CSR_SMIT_INDRECT_DATA_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x28) +/* * smlc_csr base address */ +#define CSR_SMLC_CSR_BASE_ADDR 0x700 + +/* * SMLC_CSR address */ +#define CSR_SMLC_VERSION_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x0) +#define CSR_SMLC_CFG0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x4) +#define CSR_SMLC_CFG1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x8) +#define CSR_SMLC_CFG2_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0xC) +#define CSR_SMLC_INT_VECTOR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x10) +#define CSR_SMLC_INT_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x14) +#define CSR_SMLC_INT_MASK_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x18) +#define CSR_SMLC_SRF_OV_ERR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x1C) +#define CSR_SMLC_ECC_ERR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x24) +#define CSR_SMLC_ECC_ERRPR_MASK_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x28) +#define CSR_SMLC_INDRECT_CTRL_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x2C) +#define CSR_SMLC_INDRECT_TIMEOUT_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x30) +#define CSR_SMLC_INDRECT_DATA_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x34) +#define CSR_SMLC_CNT0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x38) +#define CSR_SMLC_CNT1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x40) +#define CSR_SMLC_CNT2_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x48) +#define CSR_SMLC_CNT3_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x50) +#define CSR_SMLC_CNT_CFG0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x58) +#define CSR_SMLC_CNT_CFG1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x5C) +#define CSR_SMLC_CREDIT_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x60) +#define CSR_SMLC_FIFO_DEPTH_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x64) +#define CSR_SMLC_ECC_ERR_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x68) +/* * smmc_f_csr base address */ +#define CSR_SMMC_F_CSR_BASE_ADDR 0x800 + +/* * SMMC_F_CSR address */ +#define CSR_SMMC_F_VERSION_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x0) +#define CSR_SMMC_F_MC_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x4) +#define CSR_SMMC_F_MC_CFG1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x8) +#define CSR_SMMC_HASH_SEED0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC) +#define CSR_SMMC_HASH_SEED1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x10) +#define CSR_SMMC_F_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x14) +#define CSR_SMMC_F_MC_INIT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x18) +#define CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x1C) +#define CSR_SMMC_F_INT_VECTOR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x20) +#define CSR_SMMC_F_INT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x24) +#define CSR_SMMC_F_INT_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x28) +#define CSR_SMMC_F_MC_CACHE_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x2C) +#define CSR_SMMC_F_MC_CACHE_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x30) +#define CSR_SMMC_F_MC_CACHE_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x34) +#define CSR_SMMC_F_BUFFER_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x38) +#define CSR_SMMC_F_BUFFER_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x3C) +#define CSR_SMMC_F_BUFFER_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x40) +#define CSR_SMMC_F_MC_RF_RTN_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x44) +#define CSR_SMMC_F_MC_RF_TIMEOUT_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x48) +#define CSR_SMMC_F_MC_MULTI_HIT_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x4C) +#define CSR_SMMC_F_VC_CACHE_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x50) +#define CSR_SMMC_F_VC_CACHE_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x54) +#define CSR_SMMC_F_VC_CACHE_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x58) +#define CSR_SMMC_F_INDRECT_CTRL_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x5C) +#define CSR_SMMC_F_INDRECT_TIMEOUT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x60) +#define CSR_SMMC_F_INDRECT_DATA_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x64) +#define CSR_SMMC_F_MC_CNT_ENB_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x68) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x6C) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x70) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x74) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x78) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x7C) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL3_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x80) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL4_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x84) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL5_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x88) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL6_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x8C) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL7_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x90) +#define CSR_SMMC_F_MC_STATUS_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x94) +#define CSR_SMMC_F_MC_CNT0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x98) +#define CSR_SMMC_F_MC_CNT1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xA0) +#define CSR_SMMC_F_MC_CNT2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xA8) +#define CSR_SMMC_F_MC_CNT3_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xB0) +#define CSR_SMMC_F_MC_CNT4_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xB8) +#define CSR_SMMC_F_MC_CNT5_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC0) +#define CSR_SMMC_F_MC_CNT6_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC8) +#define CSR_SMMC_F_MC_CNT7_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xD0) +#define CSR_SMMC_F_VC_FIFO_DEPTH0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xD8) +#define CSR_SMMC_F_VC_FIFO_DEPTH1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xDC) +#define CSR_SMMC_F_MC_FIFO1_DEPTH_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE0) +#define CSR_SMMC_F_MC_FIFO2_DEPTH_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE4) +#define CSR_SMMC_F_ERR_INJ_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE8) +#define CSR_SMMC_F_GPA_TRANS_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xEC) +#define CSR_SMMC_F_QU_INTF_CNT_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF0) +#define CSR_SMMC_F_QU_INTF_RX_CNT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF4) +#define CSR_SMMC_F_QU_INTF_TX_CNT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF8) +#define CSR_SMMC_F_MC_CFG2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xFC) +/* * smmc_l_csr base address */ +#define CSR_SMMC_L_CSR_BASE_ADDR 0x900 + +/* * SMMC_L_CSR address */ +#define CSR_SMMC_L_VERSION_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x0) +#define CSR_SMMC_L_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x4) +#define CSR_SMMC_L_STAT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x8) +#define CSR_SMMC_L_INT_VECTOR_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0xC) +#define CSR_SMMC_L_INT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x10) +#define CSR_SMMC_L_INT_MASK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x14) +#define CSR_SMMC_L_MEM_ERR_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x18) +#define CSR_SMMC_L_MEM_ERR_MASK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x1C) +#define CSR_SMMC_L_MEM_ERR_INFO_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x20) +#define CSR_SMMC_L_INDRECT_CTRL_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x24) +#define CSR_SMMC_L_INDRECT_TIMEOUT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x28) +#define CSR_SMMC_L_INDRECT_DATA_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x2C) +#define CSR_SMMC_L_CNT_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x30) +#define CSR_SMMC_L_CNT_MATCH_BANK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x34) +#define CSR_SMMC_L_CNT_MATCH_INSTANCE_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x38) +#define CSR_SMMC_L_CNT0_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x3C) +#define CSR_SMMC_L_CNT1_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x40) +#define CSR_SMMC_L_CNT2_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x44) +#define CSR_SMMC_L_CNT3_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x48) +#define CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x4C) +#define CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x50) +#define CSR_SMMC_L_ECC_INJ_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x54) +#define CSR_SMMC_L_PG_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x58) +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* * __cplusplus */ + +#endif /* * HI1823_CSR_SM_ADDR_DEFINE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_typedef.h new file mode 100644 index 000000000..8fe38dabe --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_typedef.h @@ -0,0 +1,12259 @@ +#ifndef HI1823_CSR_SM_TYPEDEF_H +#define HI1823_CSR_SM_TYPEDEF_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* * __cplusplus */ + +/* ** + * Union name : SMRT_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmrtVersion { + struct tagStSmrtVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smrtVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smrtVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_VERSION_U; + +/* ** + * Union name : SMXR_CFG1 + * @brief SMXR cofigure registers + * Description: + */ +typedef union tagUnSmxrCfg1 { + struct tagStSmxrCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int rpUncrtErrInjReq : 1; /* * [31:31]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory.Enable memory check, when use this err + inection function. */ + unsigned int rpCrtErrInjReq : 1; /* * [30:30]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpSmUncrtErrMask : 7; /* * [29:23]Fatal Error Mask.For SMLbit[0]：smxt fatal error + mask;bit[1]：smmc_l fatal error maskbit[2]：smeg_core fatal error + maskbit[3~6]：Reserved.For SMFbit[0]：smxr fatal e rror mask;bit[1]：smxt fatal + error mask;bit[2]：smmc_f fatal error maskbit[3]：smeg_core 3 fatal error + maskbit[4]：smeg_core 2 fatal error maskbit[5]：smeg_core 1 fa tal error + maskbit[6]：smeg_core 0 fatal error mask7 fatal error source for SMF and 3 fatal + error source for SML, SW can mask the fatal error of each source respe + ctively.1'b0: Mask the fatal error;1'b1: Unmask the fatal error */ + unsigned int rpSmUncrtErrClr : 1; /* * [22:22]Clr the Fatal error of SML/SMF.SW can write 0 then 1 to generate a + * rising edge to clear the fatal error + */ + unsigned int tifoePftchWqeNum : 2; /* * [21:20]TIFOE pre-fetch API pre-fetch WQE number */ + unsigned int tifoePftchCtl : 2; /* * [19:18]TIFOE pre-fetch API control bit2:1;For details, please refer to + * description of TIFOE prefetch API in Hi1822V100 FS SMF API.docx + */ + unsigned int reserved0 : 1; /* * [17:17]reserved */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int iwarpPiCopyEnb : 1; /* * [7:7]IWARP PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int rocePiCopyEnb : 1; /* * [6:6]ROCE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int tifoePiCopyEnb : 1; /* * [5:5]TIFOE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int reserved1 : 2; /* * [4:3]reserved */ + unsigned int smxrCntSel : 2; /* * [2:1]smxr cnt source select:2'b00: Count disable2'b01: Count number of API + segment smxr received;2'b10: Count number of messages smxr received2'b11: Count number + of flitssmxr received */ + unsigned int memChkEn : 1; /* * [0:0]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ +#else + unsigned int memChkEn : 1; /* * [0:0]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ + unsigned int smxrCntSel : 2; /* * [2:1]smxr cnt source select:2'b00: Count disable2'b01: Count number of API + segment smxr received;2'b10: Count number of messages smxr received2'b11: Count number + of flitssmxr received */ + unsigned int reserved1 : 2; /* * [4:3]reserved */ + unsigned int tifoePiCopyEnb : 1; /* * [5:5]TIFOE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int rocePiCopyEnb : 1; /* * [6:6]ROCE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int iwarpPiCopyEnb : 1; /* * [7:7]IWARP PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int reserved0 : 1; /* * [17:17]reserved */ + unsigned int tifoePftchCtl : 2; /* * [19:18]TIFOE pre-fetch API control bit2:1;For details, please refer to + * description of TIFOE prefetch API in Hi1822V100 FS SMF API.docx + */ + unsigned int tifoePftchWqeNum : 2; /* * [21:20]TIFOE pre-fetch API pre-fetch WQE number */ + unsigned int rpSmUncrtErrClr : 1; /* * [22:22]Clr the Fatal error of SML/SMF.SW can write 0 then 1 to generate a + * rising edge to clear the fatal error + */ + unsigned int rpSmUncrtErrMask : 7; /* * [29:23]Fatal Error Mask.For SMLbit[0]：smxt fatal error + mask;bit[1]：smmc_l fatal error maskbit[2]：smeg_core fatal error + maskbit[3~6]：Reserved.For SMFbit[0]：smxr fatal e rror mask;bit[1]：smxt fatal + error mask;bit[2]：smmc_f fatal error maskbit[3]：smeg_core 3 fatal error + maskbit[4]：smeg_core 2 fatal error maskbit[5]：smeg_core 1 fa tal error + maskbit[6]：smeg_core 0 fatal error mask7 fatal error source for SMF and 3 fatal + error source for SML, SW can mask the fatal error of each source respe + ctively.1'b0: Mask the fatal error;1'b1: Unmask the fatal error */ + unsigned int rpCrtErrInjReq : 1; /* * [30:30]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [31:31]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory.Enable memory check, when use this err + inection function. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CFG1_U; + +/* ** + * Union name : SMXR_CFG0 + * @brief SMXR cofigure registers + * Description: + */ +typedef union tagUnSmxrCfg0 { + struct tagStSmxrCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int rpFairnessNum : 16; /* * [31:16]This is the flit numbers to the same smeg_core before fairness + * scheme is execute + */ + unsigned int rpFairnessEn : 1; /* * [15:15]1: turn on XR arbiter fairness0: do not use XR arbiter fairness */ + unsigned int reserved : 1; /* * [14:14] */ + unsigned int rpLbQuLdWqe : 2; /* * [13:12]load balance for ROCE load WQE API from QU:2'b00 - to infra + * pipeline02'b01 - to infra pipeline12'b10 - to infra pipeline22'b11 - to infra + * pipeline3 + */ + unsigned int rpInstIdQuLdWqe : 5; /* * [11:7]instance id for ROCE load WQE API from QU */ + unsigned int rpLbMqm : 2; /* * [6:5]load balance for API from MQM:2'b00 - to infra pipeline02'b01 - to infra + * pipeline12'b10 - to infra pipeline22'b11 - to infra pipeline3 + */ + unsigned int rpInstIdMqm : 5; /* * [4:0]instance id for API from MQM */ +#else + unsigned int rpInstIdMqm : 5; /* * [4:0]instance id for API from MQM */ + unsigned int rpLbMqm : 2; /* * [6:5]load balance for API from MQM:2'b00 - to infra pipeline02'b01 - to infra + * pipeline12'b10 - to infra pipeline22'b11 - to infra pipeline3 + */ + unsigned int rpInstIdQuLdWqe : 5; /* * [11:7]instance id for ROCE load WQE API from QU */ + unsigned int rpLbQuLdWqe : 2; /* * [13:12]load balance for ROCE load WQE API from QU:2'b00 - to infra + * pipeline02'b01 - to infra pipeline12'b10 - to infra pipeline22'b11 - to infra + * pipeline3 + */ + unsigned int reserved : 1; /* * [14:14] */ + unsigned int rpFairnessEn : 1; /* * [15:15]1: turn on XR arbiter fairness0: do not use XR arbiter fairness */ + unsigned int rpFairnessNum : 16; /* * [31:16]This is the flit numbers to the same smeg_core before fairness + * scheme is execute + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CFG0_U; + +/* ** +* Union name : SMXT_CFG +* @brief This is the Smart Memory Infra Cross Transmission (SMXT) module configuration register. The +software use this register for debug. + +* Description: +*/ +typedef union tagUnSmxtCfg { + struct tagStSmxtCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved */ + unsigned int capStart : 1; /* * [6:6]capture api data start; a posedge of this signal triggle a capture action; + * start capture after all capture mode/match fields are configure + */ + unsigned int regCapChSel : 2; /* * [5:4]Capture data source selection.0: send captured message data from ring + request channel to capture data.1: send captured message data from ring response + channel t o capture data.2: RSV in SML; SMF: send captured message data from to_tile0 + channel to capture data.3: RSV in SML; SMF: send captured message data from to_tile1 + channel to capture data. */ + unsigned int disTxEgTl1 : 1; /* * [3:3]disable service for feature engine message transmission to tile1 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int disTxEgTl0 : 1; /* * [2:2]disable service for feature engine message transmission to tile0 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int disTxMc : 1; /* * [1:1]disable service for smmc message transmission . This is for debug .1: + disable.0: enable.Note:only used for debug,users should know the api counts before con + fig this bit. */ + unsigned int disTxEg : 1; /* * [0:0]disable service for feature engine message transmission to ting. This is for + debug .1: disable.0: enable. Note:only used for debug,users should know the api + counts before config this bit. */ +#else + unsigned int disTxEg : 1; /* * [0:0]disable service for feature engine message transmission to ting. This is for + debug .1: disable.0: enable. Note:only used for debug,users should know the api + counts before config this bit. */ + unsigned int disTxMc : 1; /* * [1:1]disable service for smmc message transmission . This is for debug .1: + disable.0: enable.Note:only used for debug,users should know the api counts before con + fig this bit. */ + unsigned int disTxEgTl0 : 1; /* * [2:2]disable service for feature engine message transmission to tile0 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int disTxEgTl1 : 1; /* * [3:3]disable service for feature engine message transmission to tile1 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int regCapChSel : 2; /* * [5:4]Capture data source selection.0: send captured message data from ring + request channel to capture data.1: send captured message data from ring response + channel t o capture data.2: RSV in SML; SMF: send captured message data from to_tile0 + channel to capture data.3: RSV in SML; SMF: send captured message data from to_tile1 + channel to capture data. */ + unsigned int capStart : 1; /* * [6:6]capture api data start; a posedge of this signal triggle a capture action; + * start capture after all capture mode/match fields are configure + */ + unsigned int reserved : 25; /* * [31:7]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CFG_U; + +/* ** + * Union name : SMXR_TM_GRT01 + * @brief Timer Group Routing table element 0 and 1 + * Description: + */ +typedef union tagUnSmxrTmGrt01 { + struct tagStSmxrTmGrt01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int rpTmGrt1 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt0 : 13; /* * [12:0]Timer routing table configure for group0:bit12:11 - Load balance factor + indicates which engine core this timer group is instanced to. 00: send to core 0 0 + 1: send to core 1 10: send to core 2 11: send to core 3bit10:9 - This timer group + belong to which hostbit8:5 - Indicates which PF this timer group is m apped into. + Default 0~15 is used as global PPF for up to 4 hostsbit4:0 - Indicates which instance + ID is for timer engine in target engine core. + */ +#else + unsigned int rpTmGrt0 : 13; /* * [12:0]Timer routing table configure for group0:bit12:11 - Load balance factor + indicates which engine core this timer group is instanced to. 00: send to core 0 0 + 1: send to core 1 10: send to core 2 11: send to core 3bit10:9 - This timer group + belong to which hostbit8:5 - Indicates which PF this timer group is m apped into. + Default 0~15 is used as global PPF for up to 4 hostsbit4:0 - Indicates which instance + ID is for timer engine in target engine core. + */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt1 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_TM_GRT01_U; + +/* ** + * Union name : SMXR_TM_GRT23 + * @brief Timer Group Routing table element 2 and 3 + * Description: + */ +typedef union tagUnSmxrTmGrt23 { + struct tagStSmxrTmGrt23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int rpTmGrt3 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt2 : 13; /* * [12:0]As same as configure for group0 */ +#else + unsigned int rpTmGrt2 : 13; /* * [12:0]As same as configure for group0 */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt3 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_TM_GRT23_U; + +/* ** + * Union name : SMRT_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnSmrtIntVector { + struct tagStSmrtIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_INT_VECTOR_U; + +/* ** + * Union name : SMRT_INT + * @brief SMRT interrupt data + * Description: + */ +typedef union tagUnSmrtInt { + struct tagStSmrtInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_INT_U; + +/* ** + * Union name : SMRT_INT_MASK + * @brief SMIR interrupt mask configuration + * Description: + */ +typedef union tagUnSmrtIntMask { + struct tagStSmrtIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_INT_MASK_U; + +/* ** + * Union name : SMXR_REQ_MEM_CRT_ERR + * @brief ECC correctable memory detected on SMXR request memory + * Description: + */ +typedef union tagUnSmxrReqMemCrtErr { + struct tagStSmxrReqMemCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_REQ_MEM_CRT_ERR_U; + +/* ** + * Union name : SMXR_REQ_MEM_UNCRT_ERR + * @brief ECC un-correctable memory detected on SMXR request memory + * Description: + */ +typedef union tagUnSmxrReqMemUncrtErr { + struct tagStSmxrReqMemUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_REQ_MEM_UNCRT_ERR_U; + +/* ** + * Union name : SMXR_MISS_SOP_EOP_ERR + * @brief SMXR received miss EOP API + * Description: + */ +typedef union tagUnSmxrMissSopEopErr { + struct tagStSmxrMissSopEopErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.31:25 + - thread id;24:19 - src_tag_h;18:14 - src;13:8 - rsv ;7 - tile16 - tile05 + - ring resp4 - ring rqst3 - miss eop2 - miss sop */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.31:25 + - thread id;24:19 - src_tag_h;18:14 - src;13:8 - rsv ;7 - tile16 - tile05 + - ring resp4 - ring rqst3 - miss eop2 - miss sop */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_MISS_SOP_EOP_ERR_U; + +/* ** + * Union name : SMXR_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmxrIndrectCtrl { + struct tagStSmxrIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smxrIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smxrIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smxrIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: DBLB(Doorbeel + * loadbalance table), only in SMF4'b0001: API_CAP: SMXT capture API data （read + * only）others:reserved + */ + unsigned int smxrIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[5:0] memory address DBLB: only + bit 4:0 is v alidAPI_CAP: bit[5:2] flit number, bit[1:0] API DW: 00-flit[127:96], + 01-flit[95:64], 10-flit[63:32], 11-flit[31:0] + */ +#else + unsigned int smxrIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[5:0] memory address DBLB: only + bit 4:0 is v alidAPI_CAP: bit[5:2] flit number, bit[1:0] API DW: 00-flit[127:96], + 01-flit[95:64], 10-flit[63:32], 11-flit[31:0] + */ + unsigned int smxrIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: DBLB(Doorbeel + * loadbalance table), only in SMF4'b0001: API_CAP: SMXT capture API data （read + * only）others:reserved + */ + unsigned int smxrIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smxrIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smxrIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_INDRECT_CTRL_U; + +/* ** + * Union name : SMXR_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmxrIndrectTimeout { + struct tagStSmxrIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smxrIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMXR_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmxrIndrectData { + struct tagStSmxrIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smxrIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_INDRECT_DATA_U; + +/* ** +* Union name : SMXT_CAP_CFG +* @brief smxt capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per field via <cap_sel _en> +in <smxr_en_cnt> ) +* Description: +*/ +typedef union tagUnSmxtCapCfg { + struct tagStSmxtCapCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured. */ + unsigned int reserved : 17; /* * [30:14] */ + unsigned int flit0127123Msk : 5; /* * [13:9]flit0 bit127~bit123 capture mask. 1:corresponding bit must match + * when capture.0:don't care whether corresponding bit match when capture. + */ + unsigned int flit0127123 : 5; /* * [8:4]flit0 bit127~bit123 field to capture . */ + unsigned int capDnidEn : 1; /* * [3:3]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_node_id> field match according field in message. 0 ,No need to match this field + .This field's capture valid.. + */ + unsigned int capThdIdEn : 1; /* * [2:2]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_thd_id> field in message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capTagHEn : 1; /* * [1:1]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_h> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capTagLEn : 1; /* * [0:0]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_l> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ +#else + unsigned int capTagLEn : 1; /* * [0:0]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_l> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capTagHEn : 1; /* * [1:1]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_h> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capThdIdEn : 1; /* * [2:2]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_thd_id> field in message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capDnidEn : 1; /* * [3:3]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_node_id> field match according field in message. 0 ,No need to match this field + .This field's capture valid.. + */ + unsigned int flit0127123 : 5; /* * [8:4]flit0 bit127~bit123 field to capture . */ + unsigned int flit0127123Msk : 5; /* * [13:9]flit0 bit127~bit123 capture mask. 1:corresponding bit must match + * when capture.0:don't care whether corresponding bit match when capture. + */ + unsigned int reserved : 17; /* * [30:14] */ + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CAP_CFG_U; + +/* ** +* Union name : SMXT_CAP_FIELD_CFG +* @brief SMXT capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per field via <cap_sel _en> +in <smxr_en_cnt> ) +* Description: +*/ +typedef union tagUnSmxtCapFieldCfg { + struct tagStSmxtCapFieldCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 1; /* * [31:31]reserved */ + unsigned int dstNdId : 6; /* * [30:25]<dst_node_id> field to be matchedbit30 is RSV in 1822 */ + unsigned int dstThdId : 7; /* * [24:18]<dst_thd_id> field to be matched */ + unsigned int dstTagH : 6; /* * [17:12]<dst_tag_h> field to be matched. */ + unsigned int dstTagL : 12; /* * [11:0]<dst_tag_l> field to be matched.For response API, only match low 5 bit, + * which is src field for response API + */ +#else + unsigned int dstTagL : 12; /* * [11:0]<dst_tag_l> field to be matched.For response API, only match low 5 bit, + * which is src field for response API + */ + unsigned int dstTagH : 6; /* * [17:12]<dst_tag_h> field to be matched. */ + unsigned int dstThdId : 7; /* * [24:18]<dst_thd_id> field to be matched */ + unsigned int dstNdId : 6; /* * [30:25]<dst_node_id> field to be matchedbit30 is RSV in 1822 */ + unsigned int reserved : 1; /* * [31:31]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CAP_FIELD_CFG_U; + +/* ** +* Union name : SMXT_CNT_CFG0 +* @brief SMXT mappable event counter controal . The software use this control to configure expected +counter mapping . + +* Description: +*/ +typedef union tagUnSmxtCntCfg0 { + struct tagStSmxtCntCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 7; /* * [31:25]reserved */ + unsigned int + smxtEnCnt1 : 9; /* * [24:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_8: counter + enable1'b0:disable counting.1'b1:enable counting.bit[7:6]: channel selection1'b0:this counter + will only count the request channel to ring.1'b1:this cou nter will only count the response + channel to ring.1'b2:this counter will only count the to_tile0 channel.1'b3:this counter will + only count the to_tile1 channel. bit_5:capture Conditional count enable . This is used for + debug .When Software enable this field, then only messages matched with capture condition + inside regiser < SMXT_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for + all kinds of messages . 1 : count only when message match capture trigge r condition.0 : count + for all messages.bit[4:0]:counter input selection,config one value to choose which type you + want count:5'h0:flits send out from smeg1 of i nfra 05'h1:messages send out from smeg1 of infra + 05'h2: flits send out from smeg1 of infra 15'h3: messages send out from smeg1 of infra + 15'h4:flits send out fro m smeg1 of infra 25'h5:messages send out from smeg1 of infra 25'h6: + flits send out from smeg1 of infra 35'h7: messages send out from smeg1 of infra 35'h8: flits + send out from smmc5'h9: messages send out from smmc 5'ha:the summation of flits from smeg1 + + smmc5'hb:the summation of messages from smeg1 + smmc5'hc:flits wit h E0 from smeg1 of infra + 0.5'hd:messages with E0 from smeg1 of infra 0. （counter when message EOP with E0）5'he:flits + with E0 from smeg1 of infra 1.5'hf:messages with E0 from smeg1 of infra 1. （counter when + message EOP with E0）5'h10:flits with E0 from smeg1 of infra 2.5'h11:messages with E0 from + smeg1 of infra 2.（counte r when message EOP with E0）5'h12:flits with E0 from smeg1 of + infra 3.5'h13:messages with E0 from smeg1 of infra 3.（counter when message EOP with + E0）5'h14:the su mmation of sop from smeg1+smmc out5'h15:the summation of eop from smeg1+smmc + out5'h16:sop send out from smeg1 infra 0.5'h17:eop send out from smeg1 infra 0.5'h1 8:sop send + out from smeg1 infra 1.5'h19:eop send out from smeg1 infra 1.5'h1a:sop send out from smeg1 + infra 2.5'h1b:eop send out from smeg1 infra 2.5'h1c:sop se nd out from smeg1 infra 3.5'h1d:eop + send out from smeg1 infra 3.5'h1e:sop send out from smmc5'h1f:eop send out from smmc + */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int smxtEnCnt0 : 9; /* * [8:0]as same as SMXT_en_cnt_1 */ +#else + unsigned int smxtEnCnt0 : 9; /* * [8:0]as same as SMXT_en_cnt_1 */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int + smxtEnCnt1 : 9; /* * [24:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_8: counter + enable1'b0:disable counting.1'b1:enable counting.bit[7:6]: channel selection1'b0:this counter + will only count the request channel to ring.1'b1:this cou nter will only count the response + channel to ring.1'b2:this counter will only count the to_tile0 channel.1'b3:this counter will + only count the to_tile1 channel. bit_5:capture Conditional count enable . This is used for + debug .When Software enable this field, then only messages matched with capture condition + inside regiser < SMXT_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for + all kinds of messages . 1 : count only when message match capture trigge r condition.0 : count + for all messages.bit[4:0]:counter input selection,config one value to choose which type you + want count:5'h0:flits send out from smeg1 of i nfra 05'h1:messages send out from smeg1 of infra + 05'h2: flits send out from smeg1 of infra 15'h3: messages send out from smeg1 of infra + 15'h4:flits send out fro m smeg1 of infra 25'h5:messages send out from smeg1 of infra 25'h6: + flits send out from smeg1 of infra 35'h7: messages send out from smeg1 of infra 35'h8: flits + send out from smmc5'h9: messages send out from smmc 5'ha:the summation of flits from smeg1 + + smmc5'hb:the summation of messages from smeg1 + smmc5'hc:flits wit h E0 from smeg1 of infra + 0.5'hd:messages with E0 from smeg1 of infra 0. （counter when message EOP with E0）5'he:flits + with E0 from smeg1 of infra 1.5'hf:messages with E0 from smeg1 of infra 1. （counter when + message EOP with E0）5'h10:flits with E0 from smeg1 of infra 2.5'h11:messages with E0 from + smeg1 of infra 2.（counte r when message EOP with E0）5'h12:flits with E0 from smeg1 of + infra 3.5'h13:messages with E0 from smeg1 of infra 3.（counter when message EOP with + E0）5'h14:the su mmation of sop from smeg1+smmc out5'h15:the summation of eop from smeg1+smmc + out5'h16:sop send out from smeg1 infra 0.5'h17:eop send out from smeg1 infra 0.5'h1 8:sop send + out from smeg1 infra 1.5'h19:eop send out from smeg1 infra 1.5'h1a:sop send out from smeg1 + infra 2.5'h1b:eop send out from smeg1 infra 2.5'h1c:sop se nd out from smeg1 infra 3.5'h1d:eop + send out from smeg1 infra 3.5'h1e:sop send out from smmc5'h1f:eop send out from smmc + */ + unsigned int reserved0 : 7; /* * [31:25]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT_CFG0_U; + +/* ** +* Union name : SMXT_CNT_CFG1 +* @brief SMXT mappable event counter controal . The software use this control to configure expected +counter mapping . + +* Description: +*/ +typedef union tagUnSmxtCntCfg1 { + struct tagStSmxtCntCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 7; /* * [31:25]reserved */ + unsigned int smxtEnCnt3 : 9; /* * [24:16]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int smxtEnCnt2 : 9; /* * [8:0]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ +#else + unsigned int smxtEnCnt2 : 9; /* * [8:0]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int smxtEnCnt3 : 9; /* * [24:16]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ + unsigned int reserved0 : 7; /* * [31:25]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT_CFG1_U; + +/* ** +* Union name : SMXT_CNT0 +* @brief SMXT physical counter 0.software can enable which events to be counted into it via field +<SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . + +* Description: +*/ +typedef union tagUnSmxtCnt0 { + struct tagStSmxtCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt0 : 32; /* * [31:0]SMXT physical counter 0.software can enable which events to be counted + * into it via field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . + */ +#else + unsigned int smxtCnt0 : 32; /* * [31:0]SMXT physical counter 0.software can enable which events to be counted + * into it via field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT0_U; + +/* ** +* Union name : SMXT_CNT1 +* @brief SMXT physical counter 1.software can enable which events to be counted into it via field +<SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . + +* Description: +*/ +typedef union tagUnSmxtCnt1 { + struct tagStSmxtCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt1 : 32; /* * [31:0]SMXT physical counter 1.software can enable which events to be counted + * into it via field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . + */ +#else + unsigned int smxtCnt1 : 32; /* * [31:0]SMXT physical counter 1.software can enable which events to be counted + * into it via field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT1_U; + +/* ** +* Union name : SMXT_CNT2 +* @brief SMXT physical counter 2.software can enable which events to be counted into it via field +<SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . + +* Description: +*/ +typedef union tagUnSmxtCnt2 { + struct tagStSmxtCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt2 : 32; /* * [31:0]SMXT physical counter 2.software can enable which events to be counted + * into it via field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . + */ +#else + unsigned int smxtCnt2 : 32; /* * [31:0]SMXT physical counter 2.software can enable which events to be counted + * into it via field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT2_U; + +/* ** +* Union name : SMXT_CNT3 +* @brief SMXT physical counter 3.software can enable which events to be counted into it via field +<SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . + +* Description: +*/ +typedef union tagUnSmxtCnt3 { + struct tagStSmxtCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt3 : 32; /* * [31:0]SMXT physical counter 3.software can enable which events to be counted + * into it via field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . + */ +#else + unsigned int smxtCnt3 : 32; /* * [31:0]SMXT physical counter 3.software can enable which events to be counted + * into it via field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT3_U; + +/* ** + * Union name : SMXT_CRDT_CNT + * @brief smxt credit counter CTP registers + * Description: + */ +typedef union tagUnSmxtCrdtCnt { + struct tagStSmxtCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int ringRqstCtp : 3; /* * [15:13]SMXT credit counter CTP registers for ring request channel*NOTE: the + * default value is 0 in SML + */ + unsigned int ringRespCtp : 3; /* * [12:10]SMXT credit counter CTP registers for ring response channel*NOTE: the + * default value is 0 in SML + */ + unsigned int tl0Ctp : 5; /* * [9:5]SMXT credit counter CTP registers for tile0*NOTE: the default value is 0 in + SML */ + unsigned int tl1Ctp : 5; /* * [4:0]SMXT credit counter CTP registers for tile1*NOTE: the default value is 0 in + SML */ +#else + unsigned int tl1Ctp : 5; /* * [4:0]SMXT credit counter CTP registers for tile1*NOTE: the default value is 0 in + SML */ + unsigned int tl0Ctp : 5; /* * [9:5]SMXT credit counter CTP registers for tile0*NOTE: the default value is 0 in + SML */ + unsigned int ringRespCtp : 3; /* * [12:10]SMXT credit counter CTP registers for ring response channel*NOTE: the + * default value is 0 in SML + */ + unsigned int ringRqstCtp : 3; /* * [15:13]SMXT credit counter CTP registers for ring request channel*NOTE: the + * default value is 0 in SML + */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CRDT_CNT_U; + +/* ** + * Union name : SMXT_FIFO_DEPTH0 + * @brief FIFO depth CTP registers for SMXT FIFOs for SMF infra1 and infra0 + * Description: + */ +typedef union tagUnSmxtFifoDepth0 { + struct tagStSmxtFifoDepth0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 29; /* * [63:35]reserved. */ + unsigned long long mcCtp : 3; /* * [34:32]SMXT FIFO depth CTP registers for SMMC */ + unsigned long long if1RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long if1RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if1Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if1Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned long long if0RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long if0RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if0Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if0Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ +#else + unsigned long long if0Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ + unsigned long long if0Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if0RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if0RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long if1Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned long long if1Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if1RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if1RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long mcCtp : 3; /* * [34:32]SMXT FIFO depth CTP registers for SMMC */ + unsigned long long reserved : 29; /* * [63:35]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMXT_FIFO_DEPTH0_U; + +/* ** + * Union name : SMXT_FIFO_DEPTH1 + * @brief FIFO depth CTP registers for SMXT FIFOs for SMF infra3 and Infra2 + * Description: + */ +typedef union tagUnSmxtFifoDepth1 { + struct tagStSmxtFifoDepth1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int if3RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ + unsigned int if3RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if3Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if3Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned int if2RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned int if2RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if2Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if2Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ +#else + unsigned int if2Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ + unsigned int if2Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if2RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if2RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned int if3Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned int if3Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if3RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if3RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_FIFO_DEPTH1_U; + +/* ** + * Union name : TL0_Q_DEP + * @brief queue depth for API from TILE0 in SMXR + * Description: + */ +typedef union tagUnTl0QDep { + struct tagStTl0QDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved0 : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_TL0_Q_DEP_U; + +/* ** + * Union name : TL1_Q_DEP + * @brief queue depth for API from TILE1 in SMXR + * Description: + */ +typedef union tagUnTl1QDep { + struct tagStTl1QDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved0 : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_TL1_Q_DEP_U; + +/* ** + * Union name : RQST_Q_DEP + * @brief queue depth for API from RING request channel in SMXR + * Description: + */ +typedef union tagUnRqstQDep { + struct tagStRqstQDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int reserved : 16; /* * [31:16]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RQST_Q_DEP_U; + +/* ** + * Union name : RSP_Q_DEP + * @brief queue depth for API from RING request channel in SMXR + * Description: + */ +typedef union tagUnRspQDep { + struct tagStRspQDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]reserved */ + unsigned int l4Ctp : 4; /* * [19:16]flit number in queue to SMMC */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int l4Ctp : 4; /* * [19:16]flit number in queue to SMMC */ + unsigned int reserved : 12; /* * [31:20]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RSP_Q_DEP_U; + +/* ** + * Union name : RQST_CRDT_CNT + * @brief rqst channel credit counter in SMXR + * Description: + */ +typedef union tagUnRqstCrdtCnt { + struct tagStRqstCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]reserved */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ +#else + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int reserved : 12; /* * [31:20]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RQST_CRDT_CNT_U; + +/* ** + * Union name : RESP_CRDT_CNT + * @brief rsponse channel credit counter in SMXR + * Description: + */ +typedef union tagUnRespCrdtCnt { + struct tagStRespCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 7; /* * [31:25]reserved */ + unsigned int smmcCtp : 5; /* * [24:20]credit counter of smmcbinary format *NOTE: the default value is 0 in SML + */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ +#else + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int smmcCtp : 5; /* * [24:20]credit counter of smmcbinary format *NOTE: the default value is 0 in SML + */ + unsigned int reserved : 7; /* * [31:25]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RESP_CRDT_CNT_U; + +/* ** + * Union name : SMXR_CNT0 + * @brief Cnt for tile0 direct channel + * Description: + */ +typedef union tagUnSmxrCnt0 { + struct tagStSmxrCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt0 : 32; /* * [31:0]Cnt for tile0 direct channel */ +#else + unsigned int smxrCnt0 : 32; /* * [31:0]Cnt for tile0 direct channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT0_U; + +/* ** + * Union name : SMXR_CNT1 + * @brief Cnt for tile1 direct channel + * Description: + */ +typedef union tagUnSmxrCnt1 { + struct tagStSmxrCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt1 : 32; /* * [31:0]Cnt for tile1 direct channel */ +#else + unsigned int smxrCnt1 : 32; /* * [31:0]Cnt for tile1 direct channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT1_U; + +/* ** + * Union name : SMXR_CNT2 + * @brief Cnt for ring request channel + * Description: + */ +typedef union tagUnSmxrCnt2 { + struct tagStSmxrCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt2 : 32; /* * [31:0]Cnt for ring request channel */ +#else + unsigned int smxrCnt2 : 32; /* * [31:0]Cnt for ring request channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT2_U; + +/* ** + * Union name : SMXR_CNT3 + * @brief Cnt for ring rsponse channel + * Description: + */ +typedef union tagUnSmxrCnt3 { + struct tagStSmxrCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt3 : 32; /* * [31:0]Cnt for ring rsponse channel */ +#else + unsigned int smxrCnt3 : 32; /* * [31:0]Cnt for ring rsponse channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT3_U; + +/* ** + * Union name : SMXT_CTP + * @brief SMXT CTP registers + * Description: + */ +typedef union tagUnSmxtCtp { + struct tagStSmxtCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved */ + unsigned int apiCapDone : 1; /* * [0:0]0: API capture not success1: API capture successed */ +#else + unsigned int apiCapDone : 1; /* * [0:0]0: API capture not success1: API capture successed */ + unsigned int reserved : 31; /* * [31:1]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CTP_U; + + +/* ** + * Union name : SMIR_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmirVersion { + struct tagStSmirVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smirVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_VERSION_U; + +/* ** +* Union name : SMIR_CFG +* @brief This is the Smart Memory Infra Receive (SMIR) module configuration register. Use this register +for debug. + +* Description: +*/ +typedef union tagUnSmirCfg { + struct tagStSmirCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 6; /* * [31:26]reserved */ + unsigned int rpUncrtErrInjReq : 1; /* * [25:25]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int rpCrtErrInjReq : 1; /* * [24:24]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved1 : 9; /* * [15:7]reserved */ + unsigned int rpL2nicDbPseudoApiEn : 1; /* * [6:6]L2NIC DB pseudo API enable:1'b1: judge the API TYPE (pseudo or + * not) according to the "pseudo" bit in API;1'b0: All L2NIC DB API is + * regarded as non-pseudo API. + */ + unsigned int memChkEn : 1; /* * [5:5]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ + unsigned int msbThreadCfg : 1; /* * [4:4]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smeg 1.smeg1_cfg0.msb_thread_cfg should be configure the same value */ + unsigned int regCapChSel : 1; /* * [3:3]capture data selection,used to choose a channel data into + SMIR_CAP_DATA.0: put the caputured data from request channel into SMIR_CAP_DATA. 1: + put the caputured data from response channel into SMIR_CAP_DATA. Note:both request + channel and response channel have capture logic,they can capture message at same + time. The chan + nel selection is used to decide which channel to be displayed to uers. */ + unsigned int simpleHash : 1; /* * [2:2]simple hash computaion select.This bit is used for vefication Verfication + can simulate hash collsion easily via this mode .0: default hardware hash computation. + 1 : select lower 64bits of hash key as hash result instead of standard hardware hash + computation.FHT Engine: select first 32bit of hash key (sop[63:32] as hash result; + Stateless Hash:If key size is 10B: select first 64bit of hash key (sop[103:40] as hash + result;if key size is 4B：select all 32bit key：sop [95:64], then u se { key[23:16], + key[31:24], key[7:0], key[15:8], key[31:0]} as hash result;else, select first 64bit of + hash key (sop[95:32] as hash result;Statefull Hash:If ke y size is 42B/26B/10B, select + first 64bit of hash key (sop[79:16] as hash result;If key size is 9B，select first + 64bit of hash key (sop[95:32] as hash result; + */ + unsigned int disRxResp : 1; /* * [1:1]disable receive message from response channel . This bit is used for + debug. Software can stop to receive message from response channel via set this + bit.1: d isable receive message from response channel.0: enable. */ + unsigned int disRxRqst : 1; /* * [0:0]disable request message from request channel . This bit is used for + debug. Software can stop to receive message from request channel via set this + bit.1: dis able receive message from request channel.0: enable.Note: This bit should + not be config to 1 as csr message cannot be delivered to cnb after request channel is + disabled. */ +#else + unsigned int disRxRqst : 1; /* * [0:0]disable request message from request channel . This bit is used for + debug. Software can stop to receive message from request channel via set this + bit.1: dis able receive message from request channel.0: enable.Note: This bit should + not be config to 1 as csr message cannot be delivered to cnb after request channel is + disabled. */ + unsigned int disRxResp : 1; /* * [1:1]disable receive message from response channel . This bit is used for + debug. Software can stop to receive message from response channel via set this + bit.1: d isable receive message from response channel.0: enable. */ + unsigned int simpleHash : 1; /* * [2:2]simple hash computaion select.This bit is used for vefication Verfication + can simulate hash collsion easily via this mode .0: default hardware hash computation. + 1 : select lower 64bits of hash key as hash result instead of standard hardware hash + computation.FHT Engine: select first 32bit of hash key (sop[63:32] as hash result; + Stateless Hash:If key size is 10B: select first 64bit of hash key (sop[103:40] as hash + result;if key size is 4B：select all 32bit key：sop [95:64], then u se { key[23:16], + key[31:24], key[7:0], key[15:8], key[31:0]} as hash result;else, select first 64bit of + hash key (sop[95:32] as hash result;Statefull Hash:If ke y size is 42B/26B/10B, select + first 64bit of hash key (sop[79:16] as hash result;If key size is 9B，select first + 64bit of hash key (sop[95:32] as hash result; + */ + unsigned int regCapChSel : 1; /* * [3:3]capture data selection,used to choose a channel data into + SMIR_CAP_DATA.0: put the caputured data from request channel into SMIR_CAP_DATA. 1: + put the caputured data from response channel into SMIR_CAP_DATA. Note:both request + channel and response channel have capture logic,they can capture message at same + time. The chan + nel selection is used to decide which channel to be displayed to uers. */ + unsigned int msbThreadCfg : 1; /* * [4:4]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smeg 1.smeg1_cfg0.msb_thread_cfg should be configure the same value */ + unsigned int memChkEn : 1; /* * [5:5]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ + unsigned int rpL2nicDbPseudoApiEn : 1; /* * [6:6]L2NIC DB pseudo API enable:1'b1: judge the API TYPE (pseudo or + * not) according to the "pseudo" bit in API;1'b0: All L2NIC DB API is + * regarded as non-pseudo API. + */ + unsigned int reserved1 : 9; /* * [15:7]reserved */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int rpCrtErrInjReq : 1; /* * [24:24]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [25:25]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int reserved0 : 6; /* * [31:26]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CFG_U; + +/* ** +* Union name : SMIR_HASH_SEED0 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmirHashSeed0 { + struct tagStSmirHashSeed0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg0 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[31:0] of hash function. + */ +#else + unsigned int hashSeedCfg0 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[31:0] of hash function. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_HASH_SEED0_U; + +/* ** +* Union name : SMIR_HASH_SEED1 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmirHashSeed1 { + struct tagStSmirHashSeed1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg1 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[63:32] of hash function. + */ +#else + unsigned int hashSeedCfg1 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[63:32] of hash function. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_HASH_SEED1_U; + +/* ** + * Union name : SMIR_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnSmirIntVector { + struct tagStSmirIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INT_VECTOR_U; + +/* ** + * Union name : SMIR_INT + * @brief SMIR interrupt data + * Description: + */ +typedef union tagUnSmirInt { + struct tagStSmirInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int intData : 5; /* * [4:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 5; /* * [4:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INT_U; + +/* ** + * Union name : SMIR_INT_MASK + * @brief SMIR interrupt mask configuration + * Description: + */ +typedef union tagUnSmirIntMask { + struct tagStSmirIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int errMask : 5; /* * [4:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 5; /* * [4:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INT_MASK_U; + +/* ** + * Union name : SMIR_ERR_SPEC_TH + * @brief Int[0] :specital thread drop for busy. + * Description: + */ +typedef union tagUnSmirErrSpecTh { + struct tagStSmirErrSpecTh { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.Capture data format as following:31:25 - thread id;24:19 - src_tag_h;18:14 - src;13:8 + - in stance ID;7:2 - OP-CODE （include ACK bit） */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.Capture data format as following:31:25 - thread id;24:19 - src_tag_h;18:14 - src;13:8 + - in stance ID;7:2 - OP-CODE （include ACK bit） */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_ERR_SPEC_TH_U; + +/* ** + * Union name : SMIR_REQ_MSG_ERR + * @brief SMIR request channel message error register. + * Description: + */ +typedef union tagUnSmirReqMsgErr { + struct tagStSmirReqMsgErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:mmessage with E1-bitbit2:message over length + bit3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_id （include ACK bit）bit[ 21:16] : + instancebit[26:22] : srcBit27~29 RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:mmessage with E1-bitbit2:message over length + bit3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_id （include ACK bit）bit[ 21:16] : + instancebit[26:22] : srcBit27~29 RSV */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_REQ_MSG_ERR_U; + +/* ** + * Union name : SMIR_RESP_MSG_ERR + * @brief SMIR response channel message error register. + * Description: + */ +typedef union tagUnSmirRespMsgErr { + struct tagStSmirRespMsgErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:message with E1-bitbit2:message over lengthb + it3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_idbit[21:16] : instancebit [26:22] : + srcBit27~29 RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:message with E1-bitbit2:message over lengthb + it3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_idbit[21:16] : instancebit [26:22] : + srcBit27~29 RSV */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_RESP_MSG_ERR_U; + +/* ** + * Union name : SMIR_MEM_ECC_CRT_ERR + * @brief smir memory ecc correctable error + * Description: + */ +typedef union tagUnSmirMemEccCrtErr { + struct tagStSmirMemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMIR_MEM_ECC_UNCRT_ERR + * @brief smir memory ecc uncorrectable error + * Description: + */ +typedef union tagUnSmirMemEccUncrtErr { + struct tagStSmirMemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMIR_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmirIndrectCtrl { + struct tagStSmirIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smirIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smirIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smirIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: FIPR;4’b0001: RSS hash + memory4' b0010: VAT memory, only in SMF4' b0011: TPT(timer position table), only in + SMFother s:reserved */ + unsigned int smirIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[13:5] memory address in SMF: + FIPR; only bi t8:4 is valid; RSS_Hash:only bit 7:4 is valid; VAT: bit 13:4 is + valid TPT: only bit 8:4 is valid in SML mode: FIPR; only bit9:4 is valid; + RSS_Hash:only bit 7:4 is valid;bit[3:0] word select for RSS MEM: 0~3 reserved, + 4:mem_dat[352:321] // ECC Code, read only for CSR 5:{31bit RSV, + mem_dat[320]} 6: mem_dat[319:288] 7:mem_dat[287:256] 8:mem_dat[255:224] + 9:mem_dat[223:192] 10:mem_dat[191:160] 11:mem_dat[159:128] 12:mem_dat[127:96] + 13:mem_dat[95 :64] 14:mem_dat[63:32] 15:mem_dat[31:0]bit[3:0] word select for + VAT MEM: 0~11 reserved, 12:{24Bit RSV, mem_data[84:77]} // ECC Code, read + only for CSR 13:{19Bit RSV, mem_dat[76:64]} 14:mem_dat[63:32] + 15:mem_dat[31:0]Note: for accessing FIPR/TPT,bit[3:0] should be 4'hf. + */ +#else + unsigned int smirIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[13:5] memory address in SMF: + FIPR; only bi t8:4 is valid; RSS_Hash:only bit 7:4 is valid; VAT: bit 13:4 is + valid TPT: only bit 8:4 is valid in SML mode: FIPR; only bit9:4 is valid; + RSS_Hash:only bit 7:4 is valid;bit[3:0] word select for RSS MEM: 0~3 reserved, + 4:mem_dat[352:321] // ECC Code, read only for CSR 5:{31bit RSV, + mem_dat[320]} 6: mem_dat[319:288] 7:mem_dat[287:256] 8:mem_dat[255:224] + 9:mem_dat[223:192] 10:mem_dat[191:160] 11:mem_dat[159:128] 12:mem_dat[127:96] + 13:mem_dat[95 :64] 14:mem_dat[63:32] 15:mem_dat[31:0]bit[3:0] word select for + VAT MEM: 0~11 reserved, 12:{24Bit RSV, mem_data[84:77]} // ECC Code, read + only for CSR 13:{19Bit RSV, mem_dat[76:64]} 14:mem_dat[63:32] + 15:mem_dat[31:0]Note: for accessing FIPR/TPT,bit[3:0] should be 4'hf. + */ + unsigned int smirIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: FIPR;4’b0001: RSS hash + memory4' b0010: VAT memory, only in SMF4' b0011: TPT(timer position table), only in + SMFother s:reserved */ + unsigned int smirIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smirIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smirIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INDRECT_CTRL_U; + +/* ** + * Union name : SMIR_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmirIndrectTimeout { + struct tagStSmirIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smirIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMIR_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmirIndrectData { + struct tagStSmirIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smirIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INDRECT_DATA_U; + +/* ** +* Union name : SMIR_CAP0_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per field via <cap_sel _en> +in <smir_en_cnt> ) +* Description: +*/ +typedef union tagUnSmirCap0Cfg { + struct tagStSmirCap0Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured.Note：field match enable + config can be found in SMIR_EN_CNT register. + */ + unsigned int sE1Bit : 1; /* * [30:30]E1 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int sE0Bit : 1; /* * [29:29]E0 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int sCode : 2; /* * [28:27]code field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int sOpId : 6; /* * [26:21]opcode field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int sInstId : 6; /* * [20:15]inst_id field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int src : 5; /* * [14:10]src field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int reserved : 4; /* * [9:6]reserved */ + unsigned int stagH : 6; /* * [5:0]src_tag_h field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ +#else + unsigned int stagH : 6; /* * [5:0]src_tag_h field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int reserved : 4; /* * [9:6]reserved */ + unsigned int src : 5; /* * [14:10]src field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int sInstId : 6; /* * [20:15]inst_id field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int sOpId : 6; /* * [26:21]opcode field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int sCode : 2; /* * [28:27]code field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int sE0Bit : 1; /* * [29:29]E0 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int sE1Bit : 1; /* * [30:30]E1 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured.Note：field match enable + config can be found in SMIR_EN_CNT register. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP0_CFG_U; + +/* ** +* Union name : SMIR_CAP1_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap1Cfg { + struct tagStSmirCap1Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit011196 : 16; /* * [31:16]flit0 bit111~bit96 field to capture . */ + unsigned int flit011196Msk : 16; /* * [15:0]flit0 bit111~bit96 capture mask. 1:corresponding bit must match when + * capture.0:don't care whether corresponding bit match when capture. + */ +#else + unsigned int flit011196Msk : 16; /* * [15:0]flit0 bit111~bit96 capture mask. 1:corresponding bit must match when + * capture.0:don't care whether corresponding bit match when capture. + */ + unsigned int flit011196 : 16; /* * [31:16]flit0 bit111~bit96 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP1_CFG_U; + +/* ** +* Union name : SMIR_CAP2_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap2Cfg { + struct tagStSmirCap2Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit09564 : 32; /* * [31:0]flit0 bit95~bit64 field to capture . */ +#else + unsigned int flit09564 : 32; /* * [31:0]flit0 bit95~bit64 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP2_CFG_U; + +/* ** +* Union name : SMIR_CAP3_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap3Cfg { + struct tagStSmirCap3Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit06332 : 32; /* * [31:0]flit0 bit63~bit32 field to capture . */ +#else + unsigned int flit06332 : 32; /* * [31:0]flit0 bit63~bit32 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP3_CFG_U; + +/* ** +* Union name : SMIR_CAP4_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap4Cfg { + struct tagStSmirCap4Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit0310 : 32; /* * [31:0]flit0 bit31~bit0 field to capture . */ +#else + unsigned int flit0310 : 32; /* * [31:0]flit0 bit31~bit0 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP4_CFG_U; + +/* ** +* Union name : SMIR_CAP6_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap6Cfg { + struct tagStSmirCap6Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 6; /* * [31:26]reserved */ + unsigned int flit0950Msk : 6; /* * [25:20]flit0 bit95~bit0 capture mask.1 mask bit is corresponding 16bit data. + 1:corresponding bit must match when capture.0:don't care whether corresponding bit + match w hen capture. . */ + unsigned int capThreadIdEn : 1; /* * [19:19]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + outband E bit field in message match according field in message. 0 ,No need to + match this field .This field's capture valid. + */ + unsigned int threadId : 7; /* * [18:12]thread_id field to capture . It can be enable via cap_thread_id_en . */ + unsigned int stagL : 12; /* * [11:0]src_tag_l field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ +#else + unsigned int stagL : 12; /* * [11:0]src_tag_l field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int threadId : 7; /* * [18:12]thread_id field to capture . It can be enable via cap_thread_id_en . */ + unsigned int capThreadIdEn : 1; /* * [19:19]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + outband E bit field in message match according field in message. 0 ,No need to + match this field .This field's capture valid. + */ + unsigned int flit0950Msk : 6; /* * [25:20]flit0 bit95~bit0 capture mask.1 mask bit is corresponding 16bit data. + 1:corresponding bit must match when capture.0:don't care whether corresponding bit + match w hen capture. . */ + unsigned int reserved : 6; /* * [31:26]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP6_CFG_U; + +/* ** +* Union name : SMIR_EN_CNT +* @brief SMIR mappable event counter controal . The software use this control to configure expected +counter mapping . + +* Description: +*/ +typedef union tagUnSmirEnCnt { + struct tagStSmirEnCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int capStagLEn : 1; /* * [31:31]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + src_tag_l field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capErr1En : 1; /* * [30:30]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capErr0En : 1; /* * [29:29]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capCodeEn : 1; /* * [28:28]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + code field in message match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capOpEn : 1; /* * [27:27]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when opcode + field in mes sage match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capInstEn : 1; /* * [26:26]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when inst_id + field in me ssage match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capSrcEn : 1; /* * [25:25]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when src field + in messag e match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capStagHEn : 1; /* * [24:24]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when stag + field in messa ge match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int + smirEnCnt2 : 8; /* * [23:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_7: counter + enable1'b0:disable counting.1'b1:enable counting.bit_6: channel selection1'b0:this counter will + only count the request channel.1'b1:this counter will o nly count the response + channel.bit_5:capture Conditional count enable . This is used for debug .When Software + enable this field, then only messages matched with capture condition inside regiser < + smir_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for all kinds of + messages . 1 : count only wh en message match capture trigger condition.0 : count for all + messages.bit_4:reserved.bit[3:0]:counter input selection,config one value to choose which type + you want count:4'h0:received flits number4'h1:received messages number4'h2:received sop + number4'h3:received eop number4'h4:flits sent to smeg14'h5:messages sent to smeg14'h6:flits + sent to smeg04'h7:messages sent to smeg04'h8:RSV4'h9:RSV4'ha:RSV4'hb:RSV4'hc:flits dropped by + smir4'hd:messages dropped by smir4'he~4'hf:reserve d. */ + unsigned int smirEnCnt1 : 8; /* * [15:8]Counter configure register for SMIR_CNT1; Function is as same as + smir_en_cnt_2 */ + unsigned int smirEnCnt0 : 8; /* * [7:0]Counter configure register for SMIR_CNT0; Function is as same as + smir_en_cnt_2 */ +#else + unsigned int smirEnCnt0 : 8; /* * [7:0]Counter configure register for SMIR_CNT0; Function is as same as + smir_en_cnt_2 */ + unsigned int smirEnCnt1 : 8; /* * [15:8]Counter configure register for SMIR_CNT1; Function is as same as + smir_en_cnt_2 */ + unsigned int + smirEnCnt2 : 8; /* * [23:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_7: counter + enable1'b0:disable counting.1'b1:enable counting.bit_6: channel selection1'b0:this counter will + only count the request channel.1'b1:this counter will o nly count the response + channel.bit_5:capture Conditional count enable . This is used for debug .When Software + enable this field, then only messages matched with capture condition inside regiser < + smir_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for all kinds of + messages . 1 : count only wh en message match capture trigger condition.0 : count for all + messages.bit_4:reserved.bit[3:0]:counter input selection,config one value to choose which type + you want count:4'h0:received flits number4'h1:received messages number4'h2:received sop + number4'h3:received eop number4'h4:flits sent to smeg14'h5:messages sent to smeg14'h6:flits + sent to smeg04'h7:messages sent to smeg04'h8:RSV4'h9:RSV4'ha:RSV4'hb:RSV4'hc:flits dropped by + smir4'hd:messages dropped by smir4'he~4'hf:reserve d. */ + unsigned int capStagHEn : 1; /* * [24:24]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when stag + field in messa ge match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capSrcEn : 1; /* * [25:25]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when src field + in messag e match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capInstEn : 1; /* * [26:26]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when inst_id + field in me ssage match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capOpEn : 1; /* * [27:27]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when opcode + field in mes sage match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capCodeEn : 1; /* * [28:28]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + code field in message match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capErr0En : 1; /* * [29:29]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capErr1En : 1; /* * [30:30]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capStagLEn : 1; /* * [31:31]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + src_tag_l field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_EN_CNT_U; + +/* ** +* Union name : SMIR_CNT0 +* @brief SMIR physical counter 0.software can enable which events to be counted into it via field +<smir_en_cnt_0> in register <SMIR_EN_CNT> . + +* Description: +*/ +typedef union tagUnSmirCnt0 { + struct tagStSmirCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirCnt0 : 32; /* * [31:0] */ +#else + unsigned int smirCnt0 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CNT0_U; + +/* ** +* Union name : SMIR_CNT1 +* @brief SMIR physical counter 1.software can enable which events to be counted into it via field +<smir_en_cnt_1> in register <SMIR_EN_CNT> . + +* Description: +*/ +typedef union tagUnSmirCnt1 { + struct tagStSmirCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirCnt1 : 32; /* * [31:0] */ +#else + unsigned int smirCnt1 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CNT1_U; + +/* ** +* Union name : SMIR_CNT2 +* @brief SMIR physical counter 2.software can enable which events to be counted into it via field +<smir_en_cnt_2> in register <SMIR_EN_CNT> . + +* Description: +*/ +typedef union tagUnSmirCnt2 { + struct tagStSmirCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirCnt2 : 32; /* * [31:0] */ +#else + unsigned int smirCnt2 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CNT2_U; + +/* ** + * Union name : SMIR_CRDT_CNT + * @brief SMIR credit counter CTP register + * Description: + */ +typedef union tagUnSmirCrdtCnt { + struct tagStSmirCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 18; /* * [31:14]reserved. */ + unsigned int smmcCtp : 5; /* * [13:9]RSV */ + unsigned int rqstCtp : 3; /* * [8:6]credit counter CTP registers for EG1 request channel; */ + unsigned int respCtp : 3; /* * [5:3]credit counter CTP registers for EG1 response channel; */ + unsigned int eg0Ctp : 3; /* * [2:0]smeg0 credit counter CTP registers for EG0; */ +#else + unsigned int eg0Ctp : 3; /* * [2:0]smeg0 credit counter CTP registers for EG0; */ + unsigned int respCtp : 3; /* * [5:3]credit counter CTP registers for EG1 response channel; */ + unsigned int rqstCtp : 3; /* * [8:6]credit counter CTP registers for EG1 request channel; */ + unsigned int smmcCtp : 5; /* * [13:9]RSV */ + unsigned int reserved : 18; /* * [31:14]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CRDT_CNT_U; + +/* ** +* Union name : SMIR_CAP_FLIT0_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit0Data0 { + struct tagStSmirCapFlit0Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT0_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT0_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit0Data1 { + struct tagStSmirCapFlit0Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT0_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT1_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit1Data0 { + struct tagStSmirCapFlit1Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT1_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT1_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit1Data1 { + struct tagStSmirCapFlit1Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT1_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT2_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit2Data0 { + struct tagStSmirCapFlit2Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT2_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT2_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit2Data1 { + struct tagStSmirCapFlit2Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT2_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT3_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit3Data0 { + struct tagStSmirCapFlit3Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT3_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT3_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit3Data1 { + struct tagStSmirCapFlit3Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT3_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT4_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit4Data0 { + struct tagStSmirCapFlit4Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT4_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT4_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit4Data1 { + struct tagStSmirCapFlit4Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT4_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT5_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit5Data0 { + struct tagStSmirCapFlit5Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT5_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT5_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit5Data1 { + struct tagStSmirCapFlit5Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT5_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT0_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit0Data2 { + struct tagStSmirCapFlit0Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT0_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT1_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit1Data2 { + struct tagStSmirCapFlit1Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT1_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT2_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit2Data2 { + struct tagStSmirCapFlit2Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT2_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT3_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit3Data2 { + struct tagStSmirCapFlit3Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT3_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT4_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit4Data2 { + struct tagStSmirCapFlit4Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT4_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT5_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit5Data2 { + struct tagStSmirCapFlit5Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT5_DATA2_U; + + +/* ** + * Union name : SMEG0_ABUF0_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg0Abuf0Version { + struct tagStSmeg0Abuf0Version { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0Abuf0Version : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg0Abuf0Version : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF0_VERSION_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_0 + * @brief This is the Sm Abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm0 { + struct tagStSmAbufThGrwWm0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow0 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFO.Bit[5:0] list0,Bit[11:6] list1,...Bit[29 :24] list4,<The + following statement can be changed for clarity.>Eg:For list0, th_grow_0[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow f lag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less than 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ +#else + unsigned int thGrow0 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFO.Bit[5:0] list0,Bit[11:6] list1,...Bit[29 :24] list4,<The + following statement can be changed for clarity.>Eg:For list0, th_grow_0[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow f lag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less than 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_0_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_1 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm1 { + struct tagStSmAbufThGrwWm1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow1 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29: 24] list9,<The + following statement can be changed for clarity.>Eg:For list5, th_grow_1[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow fl ag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less t han 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ +#else + unsigned int thGrow1 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29: 24] list9,<The + following statement can be changed for clarity.>Eg:For list5, th_grow_1[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow fl ag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less t han 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_1_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_2 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm2 { + struct tagStSmAbufThGrwWm2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow2 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[2 9:24] + list14,<The following statement can be changed for clarity.>Eg:For list10, th_grow_2[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow2 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[2 9:24] + list14,<The following statement can be changed for clarity.>Eg:For list10, th_grow_2[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_2_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_3 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm3 { + struct tagStSmAbufThGrwWm3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow3 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[2 9:24] + list19,<The following statement can be changed for clarity.>Eg:For list15, th_grow_3[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow3 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[2 9:24] + list19,<The following statement can be changed for clarity.>Eg:For list15, th_grow_3[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_3_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_4 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm4 { + struct tagStSmAbufThGrwWm4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow4 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[2 9:24] + list24,<The following statement can be changed for clarity.>Eg:For list20, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow4 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[2 9:24] + list24,<The following statement can be changed for clarity.>Eg:For list20, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_4_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_5 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm5 { + struct tagStSmAbufThGrwWm5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow5 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[2 9:24] + list29,<The following statement can be changed for clarity.>Eg:For list25, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow5 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[2 9:24] + list29,<The following statement can be changed for clarity.>Eg:For list25, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_5_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_6 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm6 { + struct tagStSmAbufThGrwWm6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved */ + unsigned int thGrow6 : 12; /* * [11:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list30,Bit[11:6] list31<The foll owing statement + can be changed for clarity.>Eg:For list30, th_grow_5[5:0] can indicate 64 grow water-mark + thresholds:6'd0: which means grow flag will never gene rate.you can say Disable grow + water-mark generate.6'd1: 1/64*total_num,which means that if the current free node number + in free list is less than 1/64 of total free node number,abuf0 will set grow flag and + sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ +#else + unsigned int thGrow6 : 12; /* * [11:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list30,Bit[11:6] list31<The foll owing statement + can be changed for clarity.>Eg:For list30, th_grow_5[5:0] can indicate 64 grow water-mark + thresholds:6'd0: which means grow flag will never gene rate.you can say Disable grow + water-mark generate.6'd1: 1/64*total_num,which means that if the current free node number + in free list is less than 1/64 of total free node number,abuf0 will set grow flag and + sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ + unsigned int reserved : 20; /* * [31:12]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_6_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_0 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm0 { + struct tagStSmAbufThShkWm0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thShrink0 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list0,Bit[11:6] list1,...Bit[29:24] list4,Eg:Fo r list0, + th_shrink_0[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink0 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list0,Bit[11:6] list1,...Bit[29:24] list4,Eg:Fo r list0, + th_shrink_0[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_0_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_1 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm1 { + struct tagStSmAbufThShkWm1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thShrink1 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29:24] list9,Eg:Fo r list5, + th_shrink_1[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink1 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29:24] list9,Eg:Fo r list5, + th_shrink_1[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_1_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_2 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm2 { + struct tagStSmAbufThShkWm2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thShrink2 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[29:24] list14,Eg :For list10, + th_shrink_2[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink2 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[29:24] list14,Eg :For list10, + th_shrink_2[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_2_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_3 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm3 { + struct tagStSmAbufThShkWm3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]Reserved */ + unsigned int thShrink3 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[29:24] list19,Eg :For list15, + th_shrink_3[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink3 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[29:24] list19,Eg :For list15, + th_shrink_3[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_3_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_4 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm4 { + struct tagStSmAbufThShkWm4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]Reserved */ + unsigned int thShrink4 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[29:24] list24,Eg :For list20, + th_shrink_4[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink4 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[29:24] list24,Eg :For list20, + th_shrink_4[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_4_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_5 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm5 { + struct tagStSmAbufThShkWm5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]Reserved */ + unsigned int thShrink5 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[29:24] list29,Eg :For list25, + th_shrink_5[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink5 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[29:24] list29,Eg :For list25, + th_shrink_5[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_5_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_6 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm6 { + struct tagStSmAbufThShkWm6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]Reserved */ + unsigned int thShrink6 : 12; /* * [11:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list30,Bit[11:6] list31Eg:For list30, th_shrink _6[5:0] can + indicate 64 shrink water-mark thresholds:6'd0: which means shrink flag will never + generate.you can say Disable shrink water-mark generate.6'd1: 1/64 *total_num,which + means that if the current free node number in free list is larger than 1/64 of total + free node number,abuf0 will set shrink flag and sent it to smeg1. 6'd2: + 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink6 : 12; /* * [11:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list30,Bit[11:6] list31Eg:For list30, th_shrink _6[5:0] can + indicate 64 shrink water-mark thresholds:6'd0: which means shrink flag will never + generate.you can say Disable shrink water-mark generate.6'd1: 1/64 *total_num,which + means that if the current free node number in free list is larger than 1/64 of total + free node number,abuf0 will set shrink flag and sent it to smeg1. 6'd2: + 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 20; /* * [31:12]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_6_U; + +/* ** +* Union name : SM_ABUF_FLRC_ATTR +* @brief This is the free list reclaim attribute config register.This is used to set up the reclaim +operation on one free list. + +* Description: +*/ +typedef union tagUnSmAbufFlrcAttr { + struct tagStSmAbufFlrcAttr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 22; /* * [31:10]reserved */ + unsigned int stopRclm : 1; /* * [9:9]If sw wants pause or stop reclaim operation while reclaim is running,setup + * this bit.1'b0:cancel stop reclaim.1'b1:stop reclaim. + */ + unsigned int enRclm : 1; /* * [8:8]reclaim start control bit.Sw can setup this bit after configuring upper + boundary,lower boundary,free list id to be reclaim and reclaim fn number.1'b0: reclaim d + isable;1'b1: reclaim enable. */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int flidTorc : 5; /* * [4:0]Free list to be reclaimed (free list 1~31). */ +#else + unsigned int flidTorc : 5; /* * [4:0]Free list to be reclaimed (free list 1~31). */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int enRclm : 1; /* * [8:8]reclaim start control bit.Sw can setup this bit after configuring upper + boundary,lower boundary,free list id to be reclaim and reclaim fn number.1'b0: reclaim d + isable;1'b1: reclaim enable. */ + unsigned int stopRclm : 1; /* * [9:9]If sw wants pause or stop reclaim operation while reclaim is running,setup + * this bit.1'b0:cancel stop reclaim.1'b1:stop reclaim. + */ + unsigned int reserved0 : 22; /* * [31:10]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_ATTR_U; + +/* ** +* Union name : SM_ABUF_FLRC_NUM +* @brief This is the Sm abuf0 free list reclaim number config register.This is used to set the total +number of free nodes that the software wants to get from the particu lar free list.This register must be set before the +reclaim operation is set up. +* Description: +*/ +typedef union tagUnSmAbufFlrcNum { + struct tagStSmAbufFlrcNum { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 4; /* * [31:28]Reserved */ + unsigned int numRclm : 28; /* * [27:0]Total number of free nodes to be reclaimed. */ +#else + unsigned int numRclm : 28; /* * [27:0]Total number of free nodes to be reclaimed. */ + unsigned int reserved : 4; /* * [31:28]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_NUM_U; + +/* ** +* Union name : SM_ABUF_FLRC_BOUND_U +* @brief This is the Sm abuf0 reclaim upper boundary config register.This is used to set the upper +boundary of the reclaim region. + +* Description: +*/ +typedef union tagUnSmAbufFlrcBoundU { + struct tagStSmAbufFlrcBoundU { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufFlrcBoundU : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#else + unsigned int smAbufFlrcBoundU : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_BOUND_U_U; + +/* ** +* Union name : SM_ABUF_FLRC_BOUND_L +* @brief Sm abuf0 reclaim lower boundary config register. This register is used to set the lower boundary +of the reclaim region. + +* Description: +*/ +typedef union tagUnSmAbufFlrcBoundL { + struct tagStSmAbufFlrcBoundL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufFlrcBoundL : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#else + unsigned int smAbufFlrcBoundL : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_BOUND_L_U; + +/* ** +* Union name : SM_ABUF_PF_LIFO_CLR +* @brief This is the Sm abuf0 pre-fetch lifo clear register.This is used to clear any pfetch lifos if +software wants.(here lifo means Last in first out) + +* Description: +*/ +typedef union tagUnSmAbufPfLifoClr { + struct tagStSmAbufPfLifoClr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufPfLifoClr : 32; /* * [31:0]Pre-fetch lifo clear register.Bit[0]:pre-fetch lifo of list + 0,Bit[1]:pre-fetch lifo of list 1,….Bit[31]:pre-fetch lifo of list 31,Single bit + description:1'b0:no rmal status,not clear the lifo.1'b1:clear status,clear the + lifo.Note: User must config the register to normal status if he wants regarding + list work as normal. */ +#else + unsigned int smAbufPfLifoClr : 32; /* * [31:0]Pre-fetch lifo clear register.Bit[0]:pre-fetch lifo of list + 0,Bit[1]:pre-fetch lifo of list 1,….Bit[31]:pre-fetch lifo of list 31,Single bit + description:1'b0:no rmal status,not clear the lifo.1'b1:clear status,clear the + lifo.Note: User must config the register to normal status if he wants regarding + list work as normal. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_PF_LIFO_CLR_U; + +/* ** + * Union name : SM_ABUF_MEM_CFG + * @brief This is the Sm abuf0 parity bit check enable config register. + * Description: + */ +typedef union tagUnSmAbufMemCfg { + struct tagStSmAbufMemCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 8; /* * [31:24]reserved */ + unsigned int tpRamTmod : 8; /* * [23:16]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int pbChkEn : 1; /* * [4:4]reserved */ + unsigned int ireqPberrGen : 1; /* * [3:3]reserved */ + unsigned int ibufPberrGen : 1; /* * [2:2]reserved */ + unsigned int infoPberrGen : 1; /* * [1:1]reserved */ + unsigned int lifoPberrGen : 1; /* * [0:0]reserved */ +#else + unsigned int lifoPberrGen : 1; /* * [0:0]reserved */ + unsigned int infoPberrGen : 1; /* * [1:1]reserved */ + unsigned int ibufPberrGen : 1; /* * [2:2]reserved */ + unsigned int ireqPberrGen : 1; /* * [3:3]reserved */ + unsigned int pbChkEn : 1; /* * [4:4]reserved */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int tpRamTmod : 8; /* * [23:16]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved0 : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_MEM_CFG_U; + +/* ** +* Union name : SM_ABUF_INT_VECTOR +* @brief This is the Smart Memory (SM) abuf0 interrupt vector register.This is used to determine the CP +interrupt address, disable and enable an interrupt report,and pr ovide the total status of an abuf0 interrupt. +* Description: +*/ +typedef union tagUnSmAbufIntVector { + struct tagStSmAbufIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0: No interrupt issued;1: Interrupt issued; CP + * needs to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag that enables all interrupts reported through this + * register. 0: Interrupt disable1: Interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag that enables all interrupts reported through this + * register. 0: Interrupt disable1: Interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0: No interrupt issued;1: Interrupt issued; CP + * needs to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_INT_VECTOR_U; + +/* ** +* Union name : SM_ABUF_INT +* @brief This is the SM abuf0 interrupt data register.This is used to record the history of the interrupt +status since the last clear operation. Software can use this re gister to let the CP know, which CSR module, or group of +CSR modules, requested the interrupt. + +* Description: +*/ +typedef union tagUnSmAbufInt { + struct tagStSmAbufInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID that indicates to the CP, which CSR module, or + group of CSR modules, asked for the interrupt.Eg:Config program_csr_id=8h3,if sw + access the c sr_node whose csr_id=8'h3,the csr_node is in abuf0.it is the member + description,so it is not neccessary to move it. + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int intData : 6; /* * [5:0]Interrupt masked field. It is a collection of the error bits from the + * corresponding error registers on the sheet. + */ +#else + unsigned int intData : 6; /* * [5:0]Interrupt masked field. It is a collection of the error bits from the + * corresponding error registers on the sheet. + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID that indicates to the CP, which CSR module, or + group of CSR modules, asked for the interrupt.Eg:Config program_csr_id=8h3,if sw + access the c sr_node whose csr_id=8'h3,the csr_node is in abuf0.it is the member + description,so it is not neccessary to move it. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_INT_U; + +/* ** +* Union name : SM_ABUF_INT_MASK +* @brief This is the SM abuf0 interrupt mask register.This is used to mask the bits of the interrupt +register that should not be reported to an upper level.Software can use this register to mask corresponding bits if they +do not want those bits reporting to an upper level. + +* Description: +*/ +typedef union tagUnSmAbufIntMask { + struct tagStSmAbufIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int errMask : 6; /* * [5:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 6; /* * [5:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_INT_MASK_U; + +/* ** +* Union name : SM_ABUF_PBERR +* @brief This is the ireq_list's output data Parity Bit Error interrupt register.Software can get related +ireq_list information from this register. This register is used for debug. +* Description: +*/ +typedef union tagUnSmAbufPberr { + struct tagStSmAbufPberr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures ireq_list parity error state of the first error capture + even if the mask is off.Sticky[0]:ireq_list parity bit error;Sticky[1]:ireq_buf parit y + bit error;Sticky[3:2]:ReservedSticky[9:4]: address of ireq_list has parity + error.Sticky[15:10]: which address of ireq_buf has parity error.Sticky[29:16]: Res erved + When error_bit or multi_error_bit is set,software can use this register's member to record + the address that has the parity error. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures ireq_list parity error state of the first error capture + even if the mask is off.Sticky[0]:ireq_list parity bit error;Sticky[1]:ireq_buf parit y + bit error;Sticky[3:2]:ReservedSticky[9:4]: address of ireq_list has parity + error.Sticky[15:10]: which address of ireq_buf has parity error.Sticky[29:16]: Res erved + When error_bit or multi_error_bit is set,software can use this register's member to record + the address that has the parity error. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_PBERR_U; + +/* ** +* Union name : SM_ABUF_FL_UFLOW_ERR +* @brief This is the free list underflow error interrupt register.This register is used to record the +underflow status of 32 free lists.Any free lists are in underflow s tatus,this register will trigger.This register is +used for debug. Software can use this register to scan the status of 32 free lists. + +* Description: +*/ +typedef union tagUnSmAbufFlUflowErr { + struct tagStSmAbufFlUflowErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error, capture even if mask + is off. Sticky[4:0]: The list ID that was in an underflow state.Stick[29]:0-underflo w + because get from uneable dis-allocate list 1-underflow because get from empty + list;Sticky[28:5]: Reserved.When the error_bit or even the multi_error _bit is + set,software can use this member of the register to record the list ID. For example, when + list 0 is empty, an allocate request will load list0 to be un derflow. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error, capture even if mask + is off. Sticky[4:0]: The list ID that was in an underflow state.Stick[29]:0-underflo w + because get from uneable dis-allocate list 1-underflow because get from empty + list;Sticky[28:5]: Reserved.When the error_bit or even the multi_error _bit is + set,software can use this member of the register to record the list ID. For example, when + list 0 is empty, an allocate request will load list0 to be un derflow. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FL_UFLOW_ERR_U; + +/* ** +* Union name : SM_ABUF_FL_OFLOW_ERR +* @brief This is the free list overflow error interrupt register.This register is used to record the +overflow status of 32 free lists.If any free lists are in an overfl ow state,this register will trigger.This register +is used for debug. Software can use this register to scan the status of the 32 free lists. + +* Description: +*/ +typedef union tagUnSmAbufFlOflowErr { + struct tagStSmAbufFlOflowErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error. It captures this + even if the mask is off.Sticky[4:0]: The list ID that was in an overflow state.Stick[2 + 9]:0-overflow because put into unenable allocate list 1-overflow because put into + a full list;Sticky[28:5]: Reserved.While the error_bit or even the m ulti_error_bit is + set,software can use this member of the register to record corresponding list ID. For + example, when list0 is full,an de-allocate request will load list0 to be overflow. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error. It captures this + even if the mask is off.Sticky[4:0]: The list ID that was in an overflow state.Stick[2 + 9]:0-overflow because put into unenable allocate list 1-overflow because put into + a full list;Sticky[28:5]: Reserved.While the error_bit or even the m ulti_error_bit is + set,software can use this member of the register to record corresponding list ID. For + example, when list0 is full,an de-allocate request will load list0 to be overflow. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FL_OFLOW_ERR_U; + +/* ** +* Union name : SM_ABUF_FL_TAIL_MISS_ERR +* @brief This is the tail missed error interrupt register.This is used to capture information of regarding +list whose tail pointer is not equal to the last pointer of th e link list,when the free node group(including the last +pointer) is load from outside DDR.This register is used for debug. + +* Description: +*/ +typedef union tagUnSmAbufFlTailMissErr { + struct tagStSmAbufFlTailMissErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures error state of the first error, capture even if mask is + off.Sticky[4:0]:the list id that was tail missed.Sticky[29:5] reserve.While error_bit or + even multi_error_bit was set,software can use this member of the register to record + corresponding list id. If error_bit or multi_error_bit is set,that means the free + list(sticy[4:0]) has been destroyed. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures error state of the first error, capture even if mask is + off.Sticky[4:0]:the list id that was tail missed.Sticky[29:5] reserve.While error_bit or + even multi_error_bit was set,software can use this member of the register to record + corresponding list id. If error_bit or multi_error_bit is set,that means the free + list(sticy[4:0]) has been destroyed. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FL_TAIL_MISS_ERR_U; + +/* ** + * Union name : SMEG0_ABUF_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg0AbufIndrectCtrl { + struct tagStSmeg0AbufIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AbufIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ + unsigned int smeg0AbufIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AbufIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AbufIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:ireq list0x1:ireq + * buffer0x2:list info0x3:pfetch lifoothers:reserved + */ + unsigned int + smeg0AbufIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in + one group or internal address of the table.Bit[9:2]memory block read/write + address.differe nt memory block has different address depth and data width. User should + operate on valid address.For SML:Mem_sel Mem_addr 2'b00 0~15 2'b01 0~152'b10 + 0~31 (DATA) 32~63 (ECC)2'b11 0~127 (DATA) 128~255(ECC)For SMF:Mem_sel + Mem_addr 2'b00 0~31 2'b01 0~312'b10 0~31 (DATA, Read a nd Write) 32~63 (ECC, + read only)2'b11 0~127 (DATA, read and write) 128~255(ECC read + only)-----------------------------bit[1:0]Memory entry Index.Access order:big endian + which LSB accessed by higher address.For ireq list access,0x0~0x2:reserved.0x3: + data[31:0]For ireq_buf access,the memory data widt h of ireq_buf is 38 bit.each entry + index can only access 32bit data. so user should access ireq_buf twice to get 38bit + data.the entry index should be:0x0~0x1:re served.0x2: data[37:32]0x3: data[31:0]For + list info and prefetch lifo,the memory width is 128 bits.each entry index can only + access 32bit data.so user should ac cess list info a four times to get 128 bit + data.0x0:data[127:96]0x1:data[95:64]0x2:data[63:32]0x3:data[31:0] 0x0: {25'd0,ECC[6:0]} + for data[127:96]0x1: {25'd0,E CC[6:0]} for data[95:64]0x2: {25'd0,ECC[6:0]} for + data[63:32]0x3: {25'd0,ECC[6:0]} for data[31:0]BTW: prefetch does not support dynamic + write and if S/W want to + write continous 128 bit, its write address[1:0] must guarantee from 0x3 to 0x0. */ +#else + unsigned int + smeg0AbufIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in + one group or internal address of the table.Bit[9:2]memory block read/write + address.differe nt memory block has different address depth and data width. User should + operate on valid address.For SML:Mem_sel Mem_addr 2'b00 0~15 2'b01 0~152'b10 + 0~31 (DATA) 32~63 (ECC)2'b11 0~127 (DATA) 128~255(ECC)For SMF:Mem_sel + Mem_addr 2'b00 0~31 2'b01 0~312'b10 0~31 (DATA, Read a nd Write) 32~63 (ECC, + read only)2'b11 0~127 (DATA, read and write) 128~255(ECC read + only)-----------------------------bit[1:0]Memory entry Index.Access order:big endian + which LSB accessed by higher address.For ireq list access,0x0~0x2:reserved.0x3: + data[31:0]For ireq_buf access,the memory data widt h of ireq_buf is 38 bit.each entry + index can only access 32bit data. so user should access ireq_buf twice to get 38bit + data.the entry index should be:0x0~0x1:re served.0x2: data[37:32]0x3: data[31:0]For + list info and prefetch lifo,the memory width is 128 bits.each entry index can only + access 32bit data.so user should ac cess list info a four times to get 128 bit + data.0x0:data[127:96]0x1:data[95:64]0x2:data[63:32]0x3:data[31:0] 0x0: {25'd0,ECC[6:0]} + for data[127:96]0x1: {25'd0,E CC[6:0]} for data[95:64]0x2: {25'd0,ECC[6:0]} for + data[63:32]0x3: {25'd0,ECC[6:0]} for data[31:0]BTW: prefetch does not support dynamic + write and if S/W want to + write continous 128 bit, its write address[1:0] must guarantee from 0x3 to 0x0. */ + unsigned int smeg0AbufIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:ireq list0x1:ireq + * buffer0x2:list info0x3:pfetch lifoothers:reserved + */ + unsigned int smeg0AbufIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AbufIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AbufIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG0_ABUF_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg0AbufIndrectTimeout { + struct tagStSmeg0AbufIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AbufIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg0AbufIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG0_ABUF_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg0AbufIndrectData { + struct tagStSmeg0AbufIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + smeg0AbufIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send these + data to target.When operation read: Logic write data to these registers and refresh + xxx_indir_stat, software will get these data from target.ireq list:bit[7] :even pa rity + check bit of bit[6:0]bit[6:0]: dataireq buffer:bit[37]:even parity check bit of + bit[36:32]bit[31]:even parity check bit of bit[31:0]bit[36:32],bit[30:0]: d atalist + info:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bit[126:96 + ] : data.pfetch lifo:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bi + t[126:96] : data. */ +#else + unsigned int + smeg0AbufIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send these + data to target.When operation read: Logic write data to these registers and refresh + xxx_indir_stat, software will get these data from target.ireq list:bit[7] :even pa rity + check bit of bit[6:0]bit[6:0]: dataireq buffer:bit[37]:even parity check bit of + bit[36:32]bit[31]:even parity check bit of bit[31:0]bit[36:32],bit[30:0]: d atalist + info:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bit[126:96 + ] : data.pfetch lifo:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bi + t[126:96] : data. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF_INDRECT_DATA_U; + +/* ** +* Union name : SM_ABUF_DIS_ALLOC +* @brief This is the SM Abuf0 disable allocation config register.This is used by software to disable the +allocate operation if you do not want to release any free nodes from the particular list. +* Description: +*/ +typedef union tagUnSmAbufDisAlloc { + struct tagStSmAbufDisAlloc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufDisAlloc : 32; /* * [31:0]SM Application Buffer's disable allocation.1'b0: Enable,1'b1: + * Disable.Bit[0] free list 0,Bit[1] free list 1,Bit[2] free list 2,...Bit[31] + * free list 31. + */ +#else + unsigned int smAbufDisAlloc : 32; /* * [31:0]SM Application Buffer's disable allocation.1'b0: Enable,1'b1: + * Disable.Bit[0] free list 0,Bit[1] free list 1,Bit[2] free list 2,...Bit[31] + * free list 31. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_DIS_ALLOC_U; + +/* ** +* Union name : SM_ABUF_DIS_DE_ALLOC +* @brief This is the SM Abuf0 de_allocate disable config register.This is used by software to disable the +de-allocate operation if you do not want to put any free nodes to the particular list. +* Description: +*/ +typedef union tagUnSmAbufDisDeAlloc { + struct tagStSmAbufDisDeAlloc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufDisDeAlloc : 32; /* * [31:0]SM Application Buffer's disable + * de-allocation.1'b0:enable,1'b1:disable.Bit[0] free list 0,Bit[1] free + * list 1,Bit[2] free list 2,...Bit[31] free list 31. + */ +#else + unsigned int smAbufDisDeAlloc : 32; /* * [31:0]SM Application Buffer's disable + * de-allocation.1'b0:enable,1'b1:disable.Bit[0] free list 0,Bit[1] free + * list 1,Bit[2] free list 2,...Bit[31] free list 31. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_DIS_DE_ALLOC_U; + +/* ** +* Union name : SM_ABUF_FLRC_ST +* @brief This is the Sm abuf0 free list reclaim status register.This is used by the software to scan the +reclaimed working state. + +* Description: +*/ +typedef union tagUnSmAbufFlrcSt { + struct tagStSmAbufFlrcSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 28; /* * [31:4]This register is for reboundary function. It will be accessed by the software + during the re-boundary operation.bit[31:4] rclm_cnt:reclaim counter,this counter + compare with rclm_num, rclm_cnt=rclm_num means relcaim will be finished. */ + unsigned int reserved : 1; /* * [3:3]reserved */ + unsigned int wlistCleaning : 1; /* * [2:2]wlist clean status register.1'b0:wlist is not being clean.1'b1:wlist + * is being clean. + */ + unsigned int rlistCleaning : 1; /* * [1:1]reclaim list clean status register.1'b0: The reclaim list is not + * being clean.1'b1: The reclaim list is being clean. + */ + unsigned int doneRclm : 1; /* * [0:0]free list reclaim states.1'b0: Reclaim not done;1'b1: Reclaim done. */ +#else + unsigned int doneRclm : 1; /* * [0:0]free list reclaim states.1'b0: Reclaim not done;1'b1: Reclaim done. */ + unsigned int rlistCleaning : 1; /* * [1:1]reclaim list clean status register.1'b0: The reclaim list is not + * being clean.1'b1: The reclaim list is being clean. + */ + unsigned int wlistCleaning : 1; /* * [2:2]wlist clean status register.1'b0:wlist is not being clean.1'b1:wlist + * is being clean. + */ + unsigned int reserved : 1; /* * [3:3]reserved */ + unsigned int ctp : 28; /* * [31:4]This register is for reboundary function. It will be accessed by the software + during the re-boundary operation.bit[31:4] rclm_cnt:reclaim counter,this counter + compare with rclm_num, rclm_cnt=rclm_num means relcaim will be finished. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_ST_U; + +/* ** +* Union name : SM_ABUF_EMPTY_FL +* @brief This is the Sm abuf0 free list empty status register.This is used by software to scan whether +regarding list is empty or not. + +* Description: +*/ +typedef union tagUnSmAbufEmptyFl { + struct tagStSmAbufEmptyFl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list empty bitmap,index with free list id: 1'b0: Not empty;1'b1: both + * pre-fetch lifo and external DDR is Empty. + */ +#else + unsigned int ctp : 32; /* * [31:0]Free list empty bitmap,index with free list id: 1'b0: Not empty;1'b1: both + * pre-fetch lifo and external DDR is Empty. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_EMPTY_FL_U; + +/* ** +* Union name : SM_ABUF_FULL_FL +* @brief This is the Sm abuf0 free list full/almost full status register.This is used by the software to +scan whether the list is full, almost full, or none of the above + . +* Description: +*/ +typedef union tagUnSmAbufFullFl { + struct tagStSmAbufFullFl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list full status bitmap. Index with free list id: 1'b0: Not full;1'b1: + Full.Full means the total free nodes number in both pre-fetch lifo and external DD + R is equal or larger than the Total number configured in list info. */ +#else + unsigned int ctp : 32; /* * [31:0]Free list full status bitmap. Index with free list id: 1'b0: Not full;1'b1: + Full.Full means the total free nodes number in both pre-fetch lifo and external DD + R is equal or larger than the Total number configured in list info. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FULL_FL_U; + +/* ** +* Union name : SM_ABUF_ST_WM_GROW +* @brief This is the Sm abuf0 free list grow watermark status register.This is used by the softeware to +scan whether the free list is in status that need to grow. + +* Description: +*/ +typedef union tagUnSmAbufStWmGrow { + struct tagStSmAbufStWmGrow { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for growth. Index with free list ID. 1'b0: Used + watermark is lower than the growth threshold;1'b1: Used watermark is more than the growth + threshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#else + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for growth. Index with free list ID. 1'b0: Used + watermark is lower than the growth threshold;1'b1: Used watermark is more than the growth + threshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ST_WM_GROW_U; + +/* ** +* Union name : SM_ABUF_ST_WM_SHRINK +* @brief This is the Sm abuf0 free list shrink watermark status register.This is used by the softeware to +scan whether the free list is in a shrink status. + +* Description: +*/ +typedef union tagUnSmAbufStWmShrink { + struct tagStSmAbufStWmShrink { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for shrink. Index with free list ID. 1'b0: + Watermark is lower than the shrink threshold;1'b1: Watermark is more than the shrink thr + eshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#else + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for shrink. Index with free list ID. 1'b0: + Watermark is lower than the shrink threshold;1'b1: Watermark is more than the shrink thr + eshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ST_WM_SHRINK_U; + +/* ** +* Union name : SM_ABUF_CNT_SEL0 +* @brief This is the Sm abuf0 csr counter select config register.This is used to select which free list +must be counted. + +* Description: +*/ +typedef union tagUnSmAbufCntSel0 { + struct tagStSmAbufCntSel0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int cnt3EventSel : 3; /* * [31:29]counter 3 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt3SrcSel : 5; /* * [28:24]counter 3 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt2EventSel : 3; /* * [23:21]counter 2 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt2SrcSel : 5; /* * [20:16]counter 2 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt1EventSel : 3; /* * [15:13]counter 1 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt1SrcSel : 5; /* * [12:8]counter 1 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt0EventSel : 3; /* * [7:5]counter 0 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt0SrcSel : 5; /* * [4:0]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ +#else + unsigned int cnt0SrcSel : 5; /* * [4:0]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt0EventSel : 3; /* * [7:5]counter 0 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt1SrcSel : 5; /* * [12:8]counter 1 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt1EventSel : 3; /* * [15:13]counter 1 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt2SrcSel : 5; /* * [20:16]counter 2 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt2EventSel : 3; /* * [23:21]counter 2 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt3SrcSel : 5; /* * [28:24]counter 3 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt3EventSel : 3; /* * [31:29]counter 3 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_CNT_SEL0_U; + +/* ** +* Union name : SM_ABUF_CNT_SEL1 +* @brief Sm abuf ireq list status register.Sw can use this register to judge if the request queue is empty +or not. + +* Description: +*/ +typedef union tagUnSmAbufCntSel1 { + struct tagStSmAbufCntSel1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved */ + unsigned int cntEnable : 6; /* * [21:16]counter enable/disable register.User can config this member to enable or + diable any counter.Cnt_en[0] counter 0 enable/disabale cfg bit.Cnt_en[1] counter 0 enab + le/disabale cfg bit.Cnt_en[2] counter 0 enable/disabale cfg bit.Cnt_en[3] counter 0 + enable/disabale cfg bit.Cnt_en[4] counter 0 enable/disabale cfg bit.Cnt_en[5 + ] counter 0 enable/disabale cfg bit. */ + unsigned int cnt5EventSel : 3; /* * [15:13]counter 5 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt5SrcSel : 5; /* * [12:8]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt4EventSel : 3; /* * [7:5]counter 4 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt4SrcSel : 5; /* * [4:0]counter 4 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ +#else + unsigned int cnt4SrcSel : 5; /* * [4:0]counter 4 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt4EventSel : 3; /* * [7:5]counter 4 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt5SrcSel : 5; /* * [12:8]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt5EventSel : 3; /* * [15:13]counter 5 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cntEnable : 6; /* * [21:16]counter enable/disable register.User can config this member to enable or + diable any counter.Cnt_en[0] counter 0 enable/disabale cfg bit.Cnt_en[1] counter 0 enab + le/disabale cfg bit.Cnt_en[2] counter 0 enable/disabale cfg bit.Cnt_en[3] counter 0 + enable/disabale cfg bit.Cnt_en[4] counter 0 enable/disabale cfg bit.Cnt_en[5 + ] counter 0 enable/disabale cfg bit. */ + unsigned int reserved : 10; /* * [31:22]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_CNT_SEL1_U; + +/* ** +* Union name : SM_ABUF_COUNTER0 +* @brief This is the Sm abuf0 allocate free node count register.This is used to count the free nodes that +have been allocated successfully by abuf0. + +* Description: +*/ +typedef union tagUnSmAbufCounter0 { + struct tagStSmAbufCounter0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter0 : 32; /* * [31:0]Counter 0 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter0 : 32; /* * [31:0]Counter 0 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER0_U; + +/* ** +* Union name : SM_ABUF_COUNTER1 +* @brief This is the Sm abuf0 de-allocate free node count register.This is used to count the free nodes +that have been de-allocated successfully by abuf0. + +* Description: +*/ +typedef union tagUnSmAbufCounter1 { + struct tagStSmAbufCounter1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter1 : 32; /* * [31:0]Counter 1 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter1 : 32; /* * [31:0]Counter 1 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER1_U; + +/* ** +* Union name : SM_ABUF_COUNTER2 +* @brief This is the allocate failed operation count register.This is used to count the total number of +failed allocate operation attempts. + +* Description: +*/ +typedef union tagUnSmAbufCounter2 { + struct tagStSmAbufCounter2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter2 : 32; /* * [31:0]Counter 2 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter2 : 32; /* * [31:0]Counter 2 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER2_U; + +/* ** +* Union name : SM_ABUF_COUNTER3 +* @brief This is the Sm abuf0 de-allocate failed operation count register.This is used to count the total +number of failed de-allocate operation attempts. + +* Description: +*/ +typedef union tagUnSmAbufCounter3 { + struct tagStSmAbufCounter3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter3 : 32; /* * [31:0]Counter 3 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter3 : 32; /* * [31:0]Counter 3 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER3_U; + +/* ** +* Union name : SM_ABUF_COUNTER4 +* @brief This is the Sm abuf0 total pre-fetch load operation count register.This is used to count the +total number of pre-fetched load operations. + +* Description: +*/ +typedef union tagUnSmAbufCounter4 { + struct tagStSmAbufCounter4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter4 : 32; /* * [31:0]Counter 4 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter4 : 32; /* * [31:0]Counter 4 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER4_U; + +/* ** +* Union name : SM_ABUF_COUNTER5 +* @brief This is the Sm abuf0 total pre-fetch store operation count register.This is used to count the +total pre-fetched store operations. + +* Description: +*/ +typedef union tagUnSmAbufCounter5 { + struct tagStSmAbufCounter5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter5 : 32; /* * [31:0]Counter 5 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter5 : 32; /* * [31:0]Counter 5 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER5_U; + +/* ** +* Union name : SM_ABUF_PFETCH_FLAG +* @brief Sm abuf pre-fetch load/store setup flag.This is used to record which free list has initiated +pre-fetch load/store operation. + +* Description: +*/ +typedef union tagUnSmAbufPfetchFlag { + struct tagStSmAbufPfetchFlag { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]record the pfe-fetch load/store status of 32 free lists.Bit[0]:list 0 + pre-fetch ld/st flag.Bit[1]:list 0 pre-fetch ld/st flag....Bit[31]:list 0 pre-fetch ld/st + flag.Corresponding bit will be set when one list has initiated pre-fetch load or store + operation to smmc.Corresponding bit will be clear when one list has recei ve pre-fetch load + reture or store grant from smmc. */ +#else + unsigned int ctp : 32; /* * [31:0]record the pfe-fetch load/store status of 32 free lists.Bit[0]:list 0 + pre-fetch ld/st flag.Bit[1]:list 0 pre-fetch ld/st flag....Bit[31]:list 0 pre-fetch ld/st + flag.Corresponding bit will be set when one list has initiated pre-fetch load or store + operation to smmc.Corresponding bit will be clear when one list has recei ve pre-fetch load + reture or store grant from smmc. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_PFETCH_FLAG_U; + +/* ** +* Union name : SM_ABUF_IREQ_LIST_STA +* @brief Sm abuf ireq list status register.Sw can use this register to judge if the request queue is empty +or not. + +* Description: +*/ +typedef union tagUnSmAbufIreqListSta { + struct tagStSmAbufIreqListSta { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]ctp[0]:request queue status of free list0,ctp[1]:request queue status of free + list1,...ctp[31]:request queue status of free list31.1'b0:request queue is empty,1 + 'b1:request queue is not empty. */ +#else + unsigned int ctp : 32; /* * [31:0]ctp[0]:request queue status of free list0,ctp[1]:request queue status of free + list1,...ctp[31]:request queue status of free list31.1'b0:request queue is empty,1 + 'b1:request queue is not empty. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_IREQ_LIST_STA_U; + +/* ** +* Union name : SM_ABUF_TAIL_MISS0 +* @brief This is the SM abuf0 tail miss capture register. This is used to capture the information of the +tail-missed free list. + +* Description: +*/ +typedef union tagUnSmAbufTailMiss0 { + struct tagStSmAbufTailMiss0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed. capture low 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ +#else + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed. capture low 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_TAIL_MISS0_U; + +/* ** +* Union name : SM_ABUF_TAIL_MISS1 +* @brief This is the SM abuf0 tail miss capture register. This is used to capture the information of the +tail-missed free list. + +* Description: +*/ +typedef union tagUnSmAbufTailMiss1 { + struct tagStSmAbufTailMiss1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed.capture high 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ +#else + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed.capture high 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_TAIL_MISS1_U; + +/* ** +* Union name : SM_ABUF_CNT_LIFO_PFETCH_0 +* @brief This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number +in each pfetch lifo. + +* Description: +*/ +typedef union tagUnSmAbufCntLifoPfetch0 { + struct tagStSmAbufCntLifoPfetch0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#else + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_CNT_LIFO_PFETCH_0_U; + +/* ** +* Union name : SM_ABUF_CNT_LIFO_PFETCH_1 +* @brief This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number +in each pfetch lifo. + +* Description: +*/ +typedef union tagUnSmAbufCntLifoPfetch1 { + struct tagStSmAbufCntLifoPfetch1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#else + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_CNT_LIFO_PFETCH_1_U; + +/* ** +* Union name : SM_ABUF_CNT_LIFO_PFETCH_2 +* @brief This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number +in each pfetch lifo. + +* Description: +*/ +typedef union tagUnSmAbufCntLifoPfetch2 { + struct tagStSmAbufCntLifoPfetch2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int ctp : 4; /* * [3:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to free list + 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre -fetch lifo + has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of Rebounding free list. + */ +#else + unsigned int ctp : 4; /* * [3:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to free list + 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre -fetch lifo + has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of Rebounding free list. + */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_CNT_LIFO_PFETCH_2_U; + +/* ** + * Union name : SM_ABUF_ECC_CFG + * @brief SMEG0_ABUF ECC function configration register + * Description: + */ +typedef union tagUnSmAbufEccCfg { + struct tagStSmAbufEccCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 24; /* * [31:8]Reserved */ + unsigned int reserved1 : 1; /* * [7:7]Reserved */ + unsigned int lifoEccEn : 1; /* * [6:6]Bypass ECC function of lifo info memory1: enable ecc function0: bypass ecc + * function + */ + unsigned int lifo2bEccInjEn : 1; /* * [5:5]Enable to inject Dual ECC Error when read lifo memory0: disable1: + enable */ + unsigned int lifo1bEccInjEn : 1; /* * [4:4]Enable to inject Single ECC Error when read lifo memory0: disable1: + enable */ + unsigned int reserved2 : 1; /* * [3:3]Reserved */ + unsigned int listInfoEccEn : 1; /* * [2:2]Enable ECC function of list info memory1: enable ecc function0: bypass + * ecc function + */ + unsigned int listInfo2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read list info memory0: + disable1: enable */ + unsigned int listInfo1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read list info memory0: + disable1: enable */ +#else + unsigned int listInfo1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read list info memory0: + disable1: enable */ + unsigned int listInfo2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read list info memory0: + disable1: enable */ + unsigned int listInfoEccEn : 1; /* * [2:2]Enable ECC function of list info memory1: enable ecc function0: bypass + * ecc function + */ + unsigned int reserved2 : 1; /* * [3:3]Reserved */ + unsigned int lifo1bEccInjEn : 1; /* * [4:4]Enable to inject Single ECC Error when read lifo memory0: disable1: + enable */ + unsigned int lifo2bEccInjEn : 1; /* * [5:5]Enable to inject Dual ECC Error when read lifo memory0: disable1: + enable */ + unsigned int lifoEccEn : 1; /* * [6:6]Bypass ECC function of lifo info memory1: enable ecc function0: bypass ecc + * function + */ + unsigned int reserved1 : 1; /* * [7:7]Reserved */ + unsigned int reserved0 : 24; /* * [31:8]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ECC_CFG_U; + +/* ** + * Union name : SM_ABUF_ECC_1B_ERR_INT + * @brief 1 bit error sticky register + * Description: + */ +typedef union tagUnSmAbufEcc1bErrInt { + struct tagStSmAbufEcc1bErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 1 bit ECC error;Sticky[1]:pfetch lifo 1 bit ECC + error;Sticky[6:2]: which address of list info has 1 bit error.Sticky[13:7] which address + of pfetch lifo has 1bit error.Sticky[29:14]: reserved */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 1 bit ECC error;Sticky[1]:pfetch lifo 1 bit ECC + error;Sticky[6:2]: which address of list info has 1 bit error.Sticky[13:7] which address + of pfetch lifo has 1bit error.Sticky[29:14]: reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ECC_1B_ERR_INT_U; + +/* ** + * Union name : SM_ABUF_ECC_2B_ERR_INT + * @brief 2 bit error sticky register + * Description: + */ +typedef union tagUnSmAbufEcc2bErrInt { + struct tagStSmAbufEcc2bErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 2 bit ECC error;Sticky[1]:pfetch lifo 2 bit ECC + error;Sticky[6:2]: which address of list info has 2 bit error.Sticky[13:7] which address + of pfetch lifo has 2 bit error.Sticky[29:14]: reserved */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 2 bit ECC error;Sticky[1]:pfetch lifo 2 bit ECC + error;Sticky[6:2]: which address of list info has 2 bit error.Sticky[13:7] which address + of pfetch lifo has 2 bit error.Sticky[29:14]: reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ECC_2B_ERR_INT_U; + + +/* ** + * Union name : SMEG0_AGET_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg0AgetVersion { + struct tagStSmeg0AgetVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg0AgetVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_VERSION_U; + +/* ** + * Union name : SMEG0_AGET_CFG + * @brief age table configure registers + * Description: + */ +typedef union tagUnSmeg0AgetCfg { + struct tagStSmeg0AgetCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21]reserved */ + unsigned int smeg0Cnt1Cfg : 2; /* * [20:19]smeg0_cnt1 configure:bit0:enable, 1-enable, 0-disable;bit1:source + * select, 1-counter for smeg0_ALU 0-counter for smeg0_AGET + */ + unsigned int smeg0Cnt0Cfg : 2; /* * [18:17]smeg0_cnt0 configure:as same as the Comments of smeg0_cnt1_cfg */ + unsigned int smegCoreMemInitStart : 1; /* * [16:16]A posedge of this bit will triggle memory in smeg_core init + start. */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved1 : 7; /* * [7:1]reserved */ + unsigned int memChkEn : 1; /* * [0:0]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ +#else + unsigned int memChkEn : 1; /* * [0:0]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ + unsigned int reserved1 : 7; /* * [7:1]reserved */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int smegCoreMemInitStart : 1; /* * [16:16]A posedge of this bit will triggle memory in smeg_core init + start. */ + unsigned int smeg0Cnt0Cfg : 2; /* * [18:17]smeg0_cnt0 configure:as same as the Comments of smeg0_cnt1_cfg */ + unsigned int smeg0Cnt1Cfg : 2; /* * [20:19]smeg0_cnt1 configure:bit0:enable, 1-enable, 0-disable;bit1:source + * select, 1-counter for smeg0_ALU 0-counter for smeg0_AGET + */ + unsigned int reserved0 : 11; /* * [31:21]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_CFG_U; + +/* ** + * Union name : SMEG0_AGET_INT_VECTOR + * @brief interrupt vector + * Description: + */ +typedef union tagUnSmeg0AgetIntVector { + struct tagStSmeg0AgetIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INT_VECTOR_U; + +/* ** + * Union name : SMEG0_AGET_INT + * @brief interrupt data + * Description: + */ +typedef union tagUnSmeg0AgetInt { + struct tagStSmeg0AgetInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INT_U; + +/* ** + * Union name : SMEG0_AGET_INT_MASK + * @brief interrupt mask + * Description: + */ +typedef union tagUnSmeg0AgetIntMask { + struct tagStSmeg0AgetIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INT_MASK_U; + +/* ** + * Union name : SMEG0_AGET_MEM_PRTY_ERR + * @brief SMEG0_AGET age flag memory parity error + * Description: + */ +typedef union tagUnSmeg0AgetMemPrtyErr { + struct tagStSmeg0AgetMemPrtyErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:8]: reserved[7:0] memory index of parity error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:8]: reserved[7:0] memory index of parity error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_MEM_PRTY_ERR_U; + +/* ** + * Union name : SMEG0_AGET_BOUNDARY_ERR + * @brief SMEG0_AGET operation is out of the table boundary + * Description: + */ +typedef union tagUnSmeg0AgetBoundaryErr { + struct tagStSmeg0AgetBoundaryErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + others: reserved[13:8]:instance ID[7:0]: operation index of error (the original index rece + ived from SMEG1) */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + others: reserved[13:8]:instance ID[7:0]: operation index of error (the original index rece + ived from SMEG1) */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_BOUNDARY_ERR_U; + +/* ** + * Union name : SMEG0_AGET_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg0AgetIndrectCtrl { + struct tagStSmeg0AgetIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ + unsigned int smeg0AgetIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AgetIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AgetIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: base address + * table;4’b0001: age flag memory;others:reserved + */ + unsigned int smeg0AgetIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.Base address table: + bit7:2: instance ID; bit7 is RSV in SMF Age flag MEM: bit9:2: memory + indexbit[1:0] word select: 0:reserved, 1:mem_dat[95:64] 2:mem_dat[63:32] + 3:mem_dat[31:0]Note: for accessing + base address table,bit[1:0] should be 2'h3. */ +#else + unsigned int smeg0AgetIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.Base address table: + bit7:2: instance ID; bit7 is RSV in SMF Age flag MEM: bit9:2: memory + indexbit[1:0] word select: 0:reserved, 1:mem_dat[95:64] 2:mem_dat[63:32] + 3:mem_dat[31:0]Note: for accessing + base address table,bit[1:0] should be 2'h3. */ + unsigned int smeg0AgetIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: base address + * table;4’b0001: age flag memory;others:reserved + */ + unsigned int smeg0AgetIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AgetIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AgetIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG0_AGET_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg0AgetIndrectTimeout { + struct tagStSmeg0AgetIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg0AgetIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG0_AGET_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg0AgetIndrectData { + struct tagStSmeg0AgetIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to + these registers and refresh xxx_indir_stat, software will get these data from + target. + */ +#else + unsigned int smeg0AgetIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to + these registers and refresh xxx_indir_stat, software will get these data from + target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INDRECT_DATA_U; + +/* ** + * Union name : SMEG_CORE_MEM_INIT + * @brief smeg core memory init done flag + * Description: + */ +typedef union tagUnSmegCoreMemInit { + struct tagStSmegCoreMemInit { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int done : 1; /* * [0:0]1'b1: indicate memory init done;1'b0: memory init not done */ +#else + unsigned int done : 1; /* * [0:0]1'b1: indicate memory init done;1'b0: memory init not done */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG_CORE_MEM_INIT_U; + +/* ** + * Union name : SMEG0_CNT0 + * @brief SMEG0 Counter 0 + * Description: + */ +typedef union tagUnSmeg0Cnt0 { + struct tagStSmeg0Cnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0Cnt0 : 32; /* * [31:0]SMEG0 received request numbers;Used to Counter the numbers of received + * request numbers of smeg0 age table or smeg0 ALU module + */ +#else + unsigned int smeg0Cnt0 : 32; /* * [31:0]SMEG0 received request numbers;Used to Counter the numbers of received + * request numbers of smeg0 age table or smeg0 ALU module + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_CNT0_U; + +/* ** + * Union name : SMEG0_CNT1 + * @brief SMEG0 Counter 1 + * Description: + */ +typedef union tagUnSmeg0Cnt1 { + struct tagStSmeg0Cnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0Cnt1 : 32; /* * [31:0]SMEG0 returned grant numbers;Used to Counter the numbers of grant + * numbers of smeg0 age table or smeg0 ALU module + */ +#else + unsigned int smeg0Cnt1 : 32; /* * [31:0]SMEG0 returned grant numbers;Used to Counter the numbers of grant + * numbers of smeg0 age table or smeg0 ALU module + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_CNT1_U; + + +/* ** + * Union name : SMEG0_LU_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg0LuVersion { + struct tagStSmeg0LuVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg0LuVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_VERSION_U; + +/* ** + * Union name : SMEG0_LU_CHK_ENABLE_CFG + * @brief configuration register for memory check enbale + * Description: + */ +typedef union tagUnSmeg0LuChkEnableCfg { + struct tagStSmeg0LuChkEnableCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 8; /* * [31:24]reserved */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved1 : 4; /* * [7:4]reserved */ + unsigned int pipe0MemChkEnable : 1; /* * [3:3]0:disable1:enable */ + unsigned int pipe1MemChkEnable : 1; /* * [2:2]0:disable1:enable */ + unsigned int flitFifoChkEnable : 1; /* * [1:1]0:disable1:enable */ + unsigned int reserved2 : 1; /* * [0:0]reserved */ +#else + unsigned int reserved2 : 1; /* * [0:0]reserved */ + unsigned int flitFifoChkEnable : 1; /* * [1:1]0:disable1:enable */ + unsigned int pipe1MemChkEnable : 1; /* * [2:2]0:disable1:enable */ + unsigned int pipe0MemChkEnable : 1; /* * [3:3]0:disable1:enable */ + unsigned int reserved1 : 4; /* * [7:4]reserved */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int reserved0 : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CHK_ENABLE_CFG_U; + +/* ** + * Union name : SMEG0_LU_INT_VECTOR + * @brief interrupt vector + * Description: + */ +typedef union tagUnSmeg0LuIntVector { + struct tagStSmeg0LuIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INT_VECTOR_U; + +/* ** + * Union name : SMEG0_LU_INT + * @brief interrupt data + * Description: + */ +typedef union tagUnSmeg0LuInt { + struct tagStSmeg0LuInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INT_U; + +/* ** + * Union name : SMEG0_LU_INT_MASK + * @brief interrupt mask + * Description: + */ +typedef union tagUnSmeg0LuIntMask { + struct tagStSmeg0LuIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INT_MASK_U; + +/* ** + * Union name : SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR + * @brief SMEG0_LOOKUP_PIPE0MEM ECC 1bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe0MemEccCrtErr { + struct tagStSmeg0LuPipe0MemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR + * @brief SMEG0_LOOKUP_PIPE0MEM ECC multi-bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe0MemEccUncrtErr { + struct tagStSmeg0LuPipe0MemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR + * @brief SMEG0_LOOKUP_PIPE1MEM ECC 1bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe1MemEccCrtErr { + struct tagStSmeg0LuPipe1MemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR + * @brief SMEG0_LOOKUP_PIPE1MEM ECC multi-bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe1MemEccUncrtErr { + struct tagStSmeg0LuPipe1MemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR + * @brief SMEG0_LU_FLITFIFO 1bit error + * Description: + */ +typedef union tagUnSmeg0LuFlitfifoMemEccCrtErr { + struct tagStSmeg0LuFlitfifoMemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + ctrl_fifo mem check error flagIn flit,each 32bit generates a even parity error bit,i f + anyone happen parity error,will be triggered a flit error flag.15 bit ctrl_info generate a + even parity error flag. Any error flag will be triggered this inter rupt. */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + ctrl_fifo mem check error flagIn flit,each 32bit generates a even parity error bit,i f + anyone happen parity error,will be triggered a flit error flag.15 bit ctrl_info generate a + even parity error flag. Any error flag will be triggered this inter rupt. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR + * @brief SMEG0_LU_FLITFIFO multi-bit error + * Description: + */ +typedef union tagUnSmeg0LuFlitfifoMemEccUncrtErr { + struct tagStSmeg0LuFlitfifoMemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + reservedIn flit,each 32bit generates a even parity error bit,if anyone happen parity + error,will be triggered a flit error flag.15 bit ctrl_info generate a even parity error + flag. Any error flag will be triggered this interrupt. + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + reservedIn flit,each 32bit generates a even parity error bit,if anyone happen parity + error,will be triggered a flit error flag.15 bit ctrl_info generate a even parity error + flag. Any error flag will be triggered this interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_SW_ERR + * @brief BTREE engine detected software fatal error + * Description: + */ +typedef union tagUnSmeg0LuSwErr { + struct tagStSmeg0LuSwErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + [31:8]:engine result 29:6 bits.[7]: API length error;[6]: SW err[5:2]: SW error cause(Plea + se refer to SEMG0_lookup uArch spec) */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + [31:8]:engine result 29:6 bits.[7]: API length error;[6]: SW err[5:2]: SW error cause(Plea + se refer to SEMG0_lookup uArch spec) */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_SW_ERR_U; + +/* ** + * Union name : SMEG0_LU_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg0LuIndrectCtrl { + struct tagStSmeg0LuIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ + unsigned int smeg0LuIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0LuIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0LuIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:pipe0 memory 0x1:pipe1 + * memory others:reserved + */ + unsigned int smeg0LuIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.index [12:4]: pipe1_mem + index for 390 entriesin dex [10:4]: pipe0_mem index for 118 entriesindex [3:0]: + offset of one entry0x0-0x6: reserved, no mapping0x7: data[287:256]0x8: + data[255:224]0x9: data[223:192]0x a: data[191:160]0xb: data[159:128]0xc: + data[127:96]0xd: data[95:64]0xe: data[63:32]0xf: data[31:0] + */ +#else + unsigned int smeg0LuIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.index [12:4]: pipe1_mem + index for 390 entriesin dex [10:4]: pipe0_mem index for 118 entriesindex [3:0]: + offset of one entry0x0-0x6: reserved, no mapping0x7: data[287:256]0x8: + data[255:224]0x9: data[223:192]0x a: data[191:160]0xb: data[159:128]0xc: + data[127:96]0xd: data[95:64]0xe: data[63:32]0xf: data[31:0] + */ + unsigned int smeg0LuIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:pipe0 memory 0x1:pipe1 + * memory others:reserved + */ + unsigned int smeg0LuIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0LuIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0LuIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG0_LU_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg0LuIndrectTimeout { + struct tagStSmeg0LuIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg0LuIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG0_LU_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg0LuIndrectData { + struct tagStSmeg0LuIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smeg0LuIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INDRECT_DATA_U; + +/* ** +* Union name : SMEG0_LU_ERR_INJ_CFG +* @brief configuration register for error injection of FIFO memories. FIFO doesn't support CSR access. +Software can set error inject enable bit to test error handling. + +* Description: +*/ +typedef union tagUnSmeg0LuErrInjCfg { + struct tagStSmeg0LuErrInjCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved */ + unsigned int flitfUncrtErrInjReq : 1; /* * [5:5]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int flitfCrtErrInjReq : 1; /* * [4:4]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe1UncrtErrInjReq : 1; /* * [3:3]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int pipe1CrtErrInjReq : 1; /* * [2:2]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe0UncrtErrInjReq : 1; /* * [1:1]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int pipe0CrtErrInjReq : 1; /* * [0:0]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ +#else + unsigned int pipe0CrtErrInjReq : 1; /* * [0:0]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe0UncrtErrInjReq : 1; /* * [1:1]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int pipe1CrtErrInjReq : 1; /* * [2:2]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe1UncrtErrInjReq : 1; /* * [3:3]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int flitfCrtErrInjReq : 1; /* * [4:4]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int flitfUncrtErrInjReq : 1; /* * [5:5]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int reserved : 26; /* * [31:6]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_ERR_INJ_CFG_U; + +/* ** + * Union name : SMEG0_LU_CNT_CFG + * @brief counter related configuration register + * Description: + */ +typedef union tagUnSmeg0LuCntCfg { + struct tagStSmeg0LuCntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11]reserved */ + unsigned int engEventGrp : 3; /* * [10:8]engine enent group select;3'h0 : sel group 0 event to count;3'h1 : sel + group 1 event to count;3'h2 : sel group 2 event to count;3'h3 : sel group 3 event to + coun t;3'h4 : sel all group event to count;others: reserved */ + unsigned int cnt3EventSel : 1; /* * [7:7]0: engine_event[3];1: outgoing_msg */ + unsigned int cnt2EventSel : 1; /* * [6:6]0: engine_event[2]; 1: outgoing_flit */ + unsigned int cnt1EventSel : 1; /* * [5:5]0: engine_event[1];1: incoming msg */ + unsigned int cnt0EventSel : 1; /* * [4:4]0: engine_event[0];1: incoming flit. */ + unsigned int cntEnable : 4; /* * [3:0]each bit is mapping to one counter.setting 1 means enable, seeting 0 means + disable4'bxxx1: SMEG0_LU_CNT0_ENABLE4'bxx1x: SMEG0_LU_CNT1_ENABLE4'bx1xx: SMEG0_LU_CN + T2_ENABLE4'b1xxx: SMEG0_LU_CNT3_ENABLE */ +#else + unsigned int cntEnable : 4; /* * [3:0]each bit is mapping to one counter.setting 1 means enable, seeting 0 means + disable4'bxxx1: SMEG0_LU_CNT0_ENABLE4'bxx1x: SMEG0_LU_CNT1_ENABLE4'bx1xx: SMEG0_LU_CN + T2_ENABLE4'b1xxx: SMEG0_LU_CNT3_ENABLE */ + unsigned int cnt0EventSel : 1; /* * [4:4]0: engine_event[0];1: incoming flit. */ + unsigned int cnt1EventSel : 1; /* * [5:5]0: engine_event[1];1: incoming msg */ + unsigned int cnt2EventSel : 1; /* * [6:6]0: engine_event[2]; 1: outgoing_flit */ + unsigned int cnt3EventSel : 1; /* * [7:7]0: engine_event[3];1: outgoing_msg */ + unsigned int engEventGrp : 3; /* * [10:8]engine enent group select;3'h0 : sel group 0 event to count;3'h1 : sel + group 1 event to count;3'h2 : sel group 2 event to count;3'h3 : sel group 3 event to + coun t;3'h4 : sel all group event to count;others: reserved */ + unsigned int reserved : 21; /* * [31:11]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT_CFG_U; + +/* ** + * Union name : SMEG0_LU_CNT0 + * @brief counter0 + * Description: + */ +typedef union tagUnSmeg0LuCnt0 { + struct tagStSmeg0LuCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt0 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt0 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT0_U; + +/* ** + * Union name : SMEG0_LU_CNT1 + * @brief counter1 + * Description: + */ +typedef union tagUnSmeg0LuCnt1 { + struct tagStSmeg0LuCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt1 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt1 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT1_U; + +/* ** + * Union name : SMEG0_LU_CNT2 + * @brief counter2 + * Description: + */ +typedef union tagUnSmeg0LuCnt2 { + struct tagStSmeg0LuCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt2 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt2 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT2_U; + +/* ** + * Union name : SMEG0_LU_CNT3 + * @brief counter3 + * Description: + */ +typedef union tagUnSmeg0LuCnt3 { + struct tagStSmeg0LuCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt3 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt3 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT3_U; + +/* ** + * Union name : SMEG0_LU_CTP + * @brief SMEG0 Profile Register for performance monitor. + * Description: + */ +typedef union tagUnSmeg0LuCtp { + struct tagStSmeg0LuCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved */ + unsigned int numInOriginalFifo : 5; /* * [9:5]number of APIs in original_fifo. */ + unsigned int numInResultFifo : 5; /* * [4:0]number of commands in result_fifo. Those commands are completed in + * smeg0, and waits for forwarding to smeg1 + */ +#else + unsigned int numInResultFifo : 5; /* * [4:0]number of commands in result_fifo. Those commands are completed in + * smeg0, and waits for forwarding to smeg1 + */ + unsigned int numInOriginalFifo : 5; /* * [9:5]number of APIs in original_fifo. */ + unsigned int reserved : 22; /* * [31:10]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CTP_U; + + +/* ** + * Union name : SMEG1_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg1Version { + struct tagStSmeg1Version { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1Version : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg1Version : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_VERSION_U; + +/* ** +* Union name : SMEG1_CFG0 +* @brief Smart Memory Infra Engine Group1 (SMEG1) configuration register . This is used to configure +additional features, and for debug. + +* Description: +*/ +typedef union tagUnSmeg1Cfg0 { + struct tagStSmeg1Cfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int rpHaltThreadMaxNum : 6; /* * [31:26]maximus halted threads number, 0 - halt 1 thread at most;1 - + halt 2 thread at most;……;N - halt N+1 thread at most;Notes: Make sure N < 16 + in SML and N < 32 in S MF; */ + unsigned int btInstId : 6; /* * [25:20]Btree instance ID, all btree API use the same instance ID to access + memory, including Btree node/LT/AGE table; The base address of these table should be + configu re use this instance ID, not instance ID from API */ + unsigned int rpInlldLlIvldEn : 1; /* * [19:19]Configure for MISC_F engine RDMA inline load API. last cache line + cache invalid enable control:1'b1 - send cache invalid command for the last cache + line access by the current API;1'b0 - only when all the data of the last cache + line is load to cpi, send cache invalid command for the cache line, else dont + send cache inva lid command for the last cache line */ + unsigned int memChkEn : 1; /* * [18:18]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ + unsigned int msbThreadCfg : 1; /* * [17:17]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smir .smir_cfg.msb_thread_cfg should be configure the same value */ + unsigned int tcdThdId : 6; /* * [16:11]which thread's tcd map to tcd ctp */ + unsigned int haltOnRunawayErr : 1; /* * [10:10]halt thread on runaway error 1: halt the thread in smeg1 0: + no halt */ + unsigned int ctpActiveBits : 1; /* * [9:9]1: runaway ctp transmits thread active bits 0: runaway ctp transmits + * runaway threads + */ + unsigned int haltSwErr1 : 1; /* * [8:8]halt thread on software error1. 1: halt the thread in smeg1 when + engine detected sw_err1;Send message for the thread and SR if LL is issued ever. 0: no + h alt, no SEND/SR operation; */ + unsigned int haltOnEbit : 1; /* * [7:7]halt thread on ebit with load return, store return,get put return or + * wakeup. 1: halt the thread in smeg1 0: no halt + */ + unsigned int haltSwErr : 1; /* * [6:6]halt thread on software error. 1: halt the thread in smeg1 0: + * no halt + */ + unsigned int prememCount : 4; /* * [5:2]This is the number of allowed preload or prestore operations before + * issuing a thread from the install issue queue + */ + unsigned int preloadFairness : 1; /* * [1:1]1: turn on preload fairness0: do not use preload fairness */ + unsigned int detectRunawayThread : 1; /* * [0:0]1: detect runaway thread 0: do not detect any runaway + * thread.Attention:before turn on this bit, should configure + * smeg1_runaway_cfg first. + */ +#else + unsigned int detectRunawayThread : 1; /* * [0:0]1: detect runaway thread 0: do not detect any runaway + * thread.Attention:before turn on this bit, should configure + * smeg1_runaway_cfg first. + */ + unsigned int preloadFairness : 1; /* * [1:1]1: turn on preload fairness0: do not use preload fairness */ + unsigned int prememCount : 4; /* * [5:2]This is the number of allowed preload or prestore operations before + * issuing a thread from the install issue queue + */ + unsigned int haltSwErr : 1; /* * [6:6]halt thread on software error. 1: halt the thread in smeg1 0: + * no halt + */ + unsigned int haltOnEbit : 1; /* * [7:7]halt thread on ebit with load return, store return,get put return or + * wakeup. 1: halt the thread in smeg1 0: no halt + */ + unsigned int haltSwErr1 : 1; /* * [8:8]halt thread on software error1. 1: halt the thread in smeg1 when + engine detected sw_err1;Send message for the thread and SR if LL is issued ever. 0: no + h alt, no SEND/SR operation; */ + unsigned int ctpActiveBits : 1; /* * [9:9]1: runaway ctp transmits thread active bits 0: runaway ctp transmits + * runaway threads + */ + unsigned int haltOnRunawayErr : 1; /* * [10:10]halt thread on runaway error 1: halt the thread in smeg1 0: + no halt */ + unsigned int tcdThdId : 6; /* * [16:11]which thread's tcd map to tcd ctp */ + unsigned int msbThreadCfg : 1; /* * [17:17]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smir .smir_cfg.msb_thread_cfg should be configure the same value */ + unsigned int memChkEn : 1; /* * [18:18]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ + unsigned int rpInlldLlIvldEn : 1; /* * [19:19]Configure for MISC_F engine RDMA inline load API. last cache line + cache invalid enable control:1'b1 - send cache invalid command for the last cache + line access by the current API;1'b0 - only when all the data of the last cache + line is load to cpi, send cache invalid command for the cache line, else dont + send cache inva lid command for the last cache line */ + unsigned int btInstId : 6; /* * [25:20]Btree instance ID, all btree API use the same instance ID to access + memory, including Btree node/LT/AGE table; The base address of these table should be + configu re use this instance ID, not instance ID from API */ + unsigned int rpHaltThreadMaxNum : 6; /* * [31:26]maximus halted threads number, 0 - halt 1 thread at most;1 - + halt 2 thread at most;……;N - halt N+1 thread at most;Notes: Make sure N < 16 + in SML and N < 32 in S MF; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CFG0_U; + +/* ** + * Union name : SMEG1_CFG1 + * @brief Smart Memory Infra Engine Group1 (SMEG1) configuration register . + * Description: + */ +typedef union tagUnSmeg1Cfg1 { + struct tagStSmeg1Cfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]Software can use this register to do memory power and timing configure; + */ + unsigned int fidrUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int fidrCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [17:17]as same as fidr_uncrt_err_inj_req; only for the ECC protected + * memory in SMEG1 excepted FIDR + */ + unsigned int rpCrtErrInjReq : 1; /* * [16:16]as same as fidr_crt_err_inj_req; only for the ECC protected memory + * in SMEG1 excepted FIDR + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ +#else + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int rpCrtErrInjReq : 1; /* * [16:16]as same as fidr_crt_err_inj_req; only for the ECC protected memory + * in SMEG1 excepted FIDR + */ + unsigned int rpUncrtErrInjReq : 1; /* * [17:17]as same as fidr_uncrt_err_inj_req; only for the ECC protected + * memory in SMEG1 excepted FIDR + */ + unsigned int fidrCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int fidrUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int reserved : 12; /* * [31:20]Software can use this register to do memory power and timing configure; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CFG1_U; + +/* ** +* Union name : SMEG1_RUNAWAY_CFG +* @brief Smart Memory Infra Engine Group1 (SMEG1) Runaway sampling count configuration register. In the +normal operation, this can be used as a watch dog timer for 16 or 64 threads in a smart memory tile. +* Description: +*/ +typedef union tagUnSmeg1RunawayCfg { + struct tagStSmeg1RunawayCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1RunawayCfg : 32; /* * [31:0]The value programmed in this register is used to measure the life + span of an active thread. The maximum value of this watch dog timer is 4s. Once a + thread is ca ught as a runaway, the kill pending bit in the scoreboard is + asserted and the thread is prohibited from reissuing until software clears the + bit.*NOTE: 1. If you want to change the default runaway time, please close the + runaway detect function, update the ruaway time, then re-open the runaway + detected operation.2. the D efault value is 200ms @1GHz clock */ +#else + unsigned int smeg1RunawayCfg : 32; /* * [31:0]The value programmed in this register is used to measure the life + span of an active thread. The maximum value of this watch dog timer is 4s. Once a + thread is ca ught as a runaway, the kill pending bit in the scoreboard is + asserted and the thread is prohibited from reissuing until software clears the + bit.*NOTE: 1. If you want to change the default runaway time, please close the + runaway detect function, update the ruaway time, then re-open the runaway + detected operation.2. the D efault value is 200ms @1GHz clock */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_RUNAWAY_CFG_U; + +/* ** + * Union name : SMEG1_THREAD_ENABLE_CFG + * @brief Thread enable configure; bitmap for 16/32 thread in smeg1 + * Description: + */ +typedef union tagUnSmeg1ThreadEnableCfg { + struct tagStSmeg1ThreadEnableCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1ThreadEnableCfg : 32; /* * [31:0]thread disable configure; bitmap for 16/32 thread in smeg1; + bit0 is for thread0, bit1 is for thread 1, and so on; (bit31:16 is reserved + in SML)1'b1: thread is e nable1'b0: thread is disable, this thread will be + not allocated;*NOTE: if msb_thread_cfg is configured to allocate the MSB + thread to response channel, then the MSB (bit15 in SML/bit31 in SMF) of this + field should be enable*NOTE: not configure all 0's to this field.(when MSB + is allocated to response channel, not configu + re all 0's to the other valid fields) */ +#else + unsigned int smeg1ThreadEnableCfg : 32; /* * [31:0]thread disable configure; bitmap for 16/32 thread in smeg1; + bit0 is for thread0, bit1 is for thread 1, and so on; (bit31:16 is reserved + in SML)1'b1: thread is e nable1'b0: thread is disable, this thread will be + not allocated;*NOTE: if msb_thread_cfg is configured to allocate the MSB + thread to response channel, then the MSB (bit15 in SML/bit31 in SMF) of this + field should be enable*NOTE: not configure all 0's to this field.(when MSB + is allocated to response channel, not configu + re all 0's to the other valid fields) */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_THREAD_ENABLE_CFG_U; + +/* ** + * Union name : SMEG1_TM_TS_FAST2 + * @brief timer wheel control info + * Description: + */ +typedef union tagUnSmeg1TmTsFast2 { + struct tagStSmeg1TmTsFast2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsFast2 : 32; /* * [31:0]This register Includes fast timer wheel 0~3, {Timer wheel 0, Timer + wheel 1,Timer wheel 2, Timer wheel 3}One timer wheel's info:bit[7] :Valid, + Indicate this timi ng wheel is validbit[6:5] Spoke Mode, 00: 256 spokes 01: + 512 spokes 10: 1024 spokes 11: 2048 spokes bit[4:0] Spoke Tick Scale, + Indicate s how many ticks this timing wheel’s spoke takes, one tick time is equal + to based unit tick time, 1us.one spoke tick = 2^spoke tick scale + */ +#else + unsigned int smeg1TmTsFast2 : 32; /* * [31:0]This register Includes fast timer wheel 0~3, {Timer wheel 0, Timer + wheel 1,Timer wheel 2, Timer wheel 3}One timer wheel's info:bit[7] :Valid, + Indicate this timi ng wheel is validbit[6:5] Spoke Mode, 00: 256 spokes 01: + 512 spokes 10: 1024 spokes 11: 2048 spokes bit[4:0] Spoke Tick Scale, + Indicate s how many ticks this timing wheel’s spoke takes, one tick time is equal + to based unit tick time, 1us.one spoke tick = 2^spoke tick scale + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_FAST2_U; + +/* ** + * Union name : SMEG1_TM_TS_FAST3 + * @brief TIMER engine wheel control info + * Description: + */ +typedef union tagUnSmeg1TmTsFast3 { + struct tagStSmeg1TmTsFast3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsFast3 : 32; /* * [31:0]This register Includes slow timer wheel 4~5, {Timer wheel 4, Timer + * wheel 5,Reserved 16 bit}timer wheel info data structure is same with fast + * timer wheel info. + */ +#else + unsigned int smeg1TmTsFast3 : 32; /* * [31:0]This register Includes slow timer wheel 4~5, {Timer wheel 4, Timer + * wheel 5,Reserved 16 bit}timer wheel info data structure is same with fast + * timer wheel info. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_FAST3_U; + +/* ** + * Union name : SMEG1_TM_TS_SLOW0 + * @brief TIMER engine control info + * Description: + */ +typedef union tagUnSmeg1TmTsSlow0 { + struct tagStSmeg1TmTsSlow0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsSlow0 : 32; /* * [31:0][31:2]: reserved[1]: indicate core clock's frequency0: 900MHz1: + 600MHz[0]: CAR engine use type of timestamp. If chip support DFS, select global + timestamp.0: use local timestamp1: use global timestamp */ +#else + unsigned int smeg1TmTsSlow0 : 32; /* * [31:0][31:2]: reserved[1]: indicate core clock's frequency0: 900MHz1: + 600MHz[0]: CAR engine use type of timestamp. If chip support DFS, select global + timestamp.0: use local timestamp1: use global timestamp */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_SLOW0_U; + +/* ** + * Union name : SMEG1_TM_TS_SLOW1 + * @brief TIMER engine control info + * Description: + */ +typedef union tagUnSmeg1TmTsSlow1 { + struct tagStSmeg1TmTsSlow1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsSlow1 : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 15Bit [29:28]: entry + 14Bit [27: 26]: entry 13Bit [25:24]: entry 12Bit [23:22]: entry 11Bit [21:20]: + entry 10Bit [19:18]: entry 9Bit [17:16]: entry 8Bit [15:14]: entry 7Bit [13:12]: + entry 6Bit [11:10]: entry 5Bit [9:8] : entry 4Bit [7:6] : entry 3Bit [5:4] : + entry 2Bit [3:2] : entry 1Bit [1:0] : entry 0 + */ +#else + unsigned int smeg1TmTsSlow1 : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 15Bit [29:28]: entry + 14Bit [27: 26]: entry 13Bit [25:24]: entry 12Bit [23:22]: entry 11Bit [21:20]: + entry 10Bit [19:18]: entry 9Bit [17:16]: entry 8Bit [15:14]: entry 7Bit [13:12]: + entry 6Bit [11:10]: entry 5Bit [9:8] : entry 4Bit [7:6] : entry 3Bit [5:4] : + entry 2Bit [3:2] : entry 1Bit [1:0] : entry 0 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_SLOW1_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG7 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg7 { + struct tagStSmeg1TmTmtCfg7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt31 : 8; /* * [31:24]timer engine memory type config for APIs whose service type is + 31:bit[7]: valid flag, 1: valid; 0: invalid;bit[6:4] Vcache index: + Virtual cache Ind ex for context in FIARbit[3:0] Tag_type,Memory Tag Type, which is + used to access context, and definitions are referred in stateful SM FS. + */ + unsigned int smeg1TmTmt30 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 30 + */ + unsigned int smeg1TmTmt29 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 29 + */ + unsigned int smeg1TmTmt28 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 28 + */ +#else + unsigned int smeg1TmTmt28 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 28 + */ + unsigned int smeg1TmTmt29 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 29 + */ + unsigned int smeg1TmTmt30 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 30 + */ + unsigned int smeg1TmTmt31 : 8; /* * [31:24]timer engine memory type config for APIs whose service type is + 31:bit[7]: valid flag, 1: valid; 0: invalid;bit[6:4] Vcache index: + Virtual cache Ind ex for context in FIARbit[3:0] Tag_type,Memory Tag Type, which is + used to access context, and definitions are referred in stateful SM FS. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG7_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG6 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg6 { + struct tagStSmeg1TmTmtCfg6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt27 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 27 + */ + unsigned int smeg1TmTmt26 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 26 + */ + unsigned int smeg1TmTmt25 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 25 + */ + unsigned int smeg1TmTmt24 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 24 + */ +#else + unsigned int smeg1TmTmt24 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 24 + */ + unsigned int smeg1TmTmt25 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 25 + */ + unsigned int smeg1TmTmt26 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 26 + */ + unsigned int smeg1TmTmt27 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 27 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG6_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG5 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg5 { + struct tagStSmeg1TmTmtCfg5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt23 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 23 + */ + unsigned int smeg1TmTmt22 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 22 + */ + unsigned int smeg1TmTmt21 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 21 + */ + unsigned int smeg1TmTmt20 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 20 + */ +#else + unsigned int smeg1TmTmt20 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 20 + */ + unsigned int smeg1TmTmt21 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 21 + */ + unsigned int smeg1TmTmt22 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 22 + */ + unsigned int smeg1TmTmt23 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 23 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG5_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG4 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg4 { + struct tagStSmeg1TmTmtCfg4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt19 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 19 + */ + unsigned int smeg1TmTmt18 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 18 + */ + unsigned int smeg1TmTmt17 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 17 + */ + unsigned int smeg1TmTmt16 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 16 + */ +#else + unsigned int smeg1TmTmt16 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 16 + */ + unsigned int smeg1TmTmt17 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 17 + */ + unsigned int smeg1TmTmt18 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 18 + */ + unsigned int smeg1TmTmt19 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 19 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG4_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG3 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg3 { + struct tagStSmeg1TmTmtCfg3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt15 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 15 + */ + unsigned int smeg1TmTmt14 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 14 + */ + unsigned int smeg1TmTmt13 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 13 + */ + unsigned int smeg1TmTmt12 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 12 + */ +#else + unsigned int smeg1TmTmt12 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 12 + */ + unsigned int smeg1TmTmt13 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 13 + */ + unsigned int smeg1TmTmt14 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 14 + */ + unsigned int smeg1TmTmt15 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 15 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG3_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG2 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg2 { + struct tagStSmeg1TmTmtCfg2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt11 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 11 + */ + unsigned int smeg1TmTmt10 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 10 + */ + unsigned int smeg1TmTmt9 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 9 + */ + unsigned int smeg1TmTmt8 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 8 + */ +#else + unsigned int smeg1TmTmt8 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 8 + */ + unsigned int smeg1TmTmt9 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 9 + */ + unsigned int smeg1TmTmt10 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 10 + */ + unsigned int smeg1TmTmt11 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 11 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG2_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG1 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg1 { + struct tagStSmeg1TmTmtCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt7 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 7 + */ + unsigned int smeg1TmTmt6 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 6 + */ + unsigned int smeg1TmTmt5 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 5 + */ + unsigned int smeg1TmTmt4 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 4 + */ +#else + unsigned int smeg1TmTmt4 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 4 + */ + unsigned int smeg1TmTmt5 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 5 + */ + unsigned int smeg1TmTmt6 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 6 + */ + unsigned int smeg1TmTmt7 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 7 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG1_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG0 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg0 { + struct tagStSmeg1TmTmtCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt3 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 3 + */ + unsigned int smeg1TmTmt2 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 2 + */ + unsigned int smeg1TmTmt1 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 1 + */ + unsigned int smeg1TmTmt0 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 0 + */ +#else + unsigned int smeg1TmTmt0 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 0 + */ + unsigned int smeg1TmTmt1 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 1 + */ + unsigned int smeg1TmTmt2 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 2 + */ + unsigned int smeg1TmTmt3 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 3 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG0_U; + +/* ** + * Union name : SMEG1_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnSmeg1IntVector { + struct tagStSmeg1IntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INT_VECTOR_U; + +/* ** + * Union name : SMEG1_INT + * @brief + * Description: + */ +typedef union tagUnSmeg1Int { + struct tagStSmeg1Int { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INT_U; + +/* ** + * Union name : SMEG1_INT_MASK + * @brief + * Description: + */ +typedef union tagUnSmeg1IntMask { + struct tagStSmeg1IntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INT_MASK_U; + +/* ** +* Union name : SMEG1_ENGINE_SW_ERR +* @brief This is Smart Memory Infra Engine Group1 (SMEG1) engine software error log register. + +* Description: +*/ +typedef union tagUnSmeg1EngineSwErr { + struct tagStSmeg1EngineSwErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off It + logs thread id, opcode of the failed API and instance id.Bi t[31]:sw_err1 is + detectedBit[30]:sw_err0 is detectedBit[29:26]:sw error codeBit[25:20]:RSVBit[19:14]:thread + id.Bit[13:8]:opcode.Bit[7:2]:instance id. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off It + logs thread id, opcode of the failed API and instance id.Bi t[31]:sw_err1 is + detectedBit[30]:sw_err0 is detectedBit[29:26]:sw error codeBit[25:20]:RSVBit[19:14]:thread + id.Bit[13:8]:opcode.Bit[7:2]:instance id. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ENGINE_SW_ERR_U; + +/* ** + * Union name : SMEG1_ERR0 + * @brief error register 0 + * Description: + */ +typedef union tagUnSmeg1Err0 { + struct tagStSmeg1Err0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 14; /* * [31:18]reserved. */ + unsigned int runawayMerr : 1; /* * [17:17] */ + unsigned int runawayErr : 1; /* * [16:16]runaway error */ + unsigned int eccCrtMerr7 : 1; /* * [15:15] */ + unsigned int eccCrtErr7 : 1; /* * [14:14]ecc correctable error is detected on memory ARR */ + unsigned int eccCrtMerr6 : 1; /* * [13:13] */ + unsigned int eccCrtErr6 : 1; /* * [12:12]ecc correctable error is detected on memory tdr */ + unsigned int eccCrtMerr5 : 1; /* * [11:11] */ + unsigned int eccCrtErr5 : 1; /* * [10:10]ecc correctable error is detected on memory etr1 */ + unsigned int eccCrtMerr4 : 1; /* * [9:9] */ + unsigned int eccCrtErr4 : 1; /* * [8:8]ecc correctable error is detected on memory etr0 */ + unsigned int eccCrtMerr3 : 1; /* * [7:7] */ + unsigned int eccCrtErr3 : 1; /* * [6:6]ecc correctable error is detected on memory esr */ + unsigned int eccCrtMerr2 : 1; /* * [5:5] */ + unsigned int eccCrtErr2 : 1; /* * [4:4]ecc correctable error is detected on memory fidr */ + unsigned int eccCrtMerr1 : 1; /* * [3:3] */ + unsigned int eccCrtErr1 : 1; /* * [2:2]ecc correctable error is detected on memory gpr1 */ + unsigned int eccCrtMerr0 : 1; /* * [1:1] */ + unsigned int eccCrtErr0 : 1; /* * [0:0]ecc correctable error is detected on memory gpr0 */ +#else + unsigned int eccCrtErr0 : 1; /* * [0:0]ecc correctable error is detected on memory gpr0 */ + unsigned int eccCrtMerr0 : 1; /* * [1:1] */ + unsigned int eccCrtErr1 : 1; /* * [2:2]ecc correctable error is detected on memory gpr1 */ + unsigned int eccCrtMerr1 : 1; /* * [3:3] */ + unsigned int eccCrtErr2 : 1; /* * [4:4]ecc correctable error is detected on memory fidr */ + unsigned int eccCrtMerr2 : 1; /* * [5:5] */ + unsigned int eccCrtErr3 : 1; /* * [6:6]ecc correctable error is detected on memory esr */ + unsigned int eccCrtMerr3 : 1; /* * [7:7] */ + unsigned int eccCrtErr4 : 1; /* * [8:8]ecc correctable error is detected on memory etr0 */ + unsigned int eccCrtMerr4 : 1; /* * [9:9] */ + unsigned int eccCrtErr5 : 1; /* * [10:10]ecc correctable error is detected on memory etr1 */ + unsigned int eccCrtMerr5 : 1; /* * [11:11] */ + unsigned int eccCrtErr6 : 1; /* * [12:12]ecc correctable error is detected on memory tdr */ + unsigned int eccCrtMerr6 : 1; /* * [13:13] */ + unsigned int eccCrtErr7 : 1; /* * [14:14]ecc correctable error is detected on memory ARR */ + unsigned int eccCrtMerr7 : 1; /* * [15:15] */ + unsigned int runawayErr : 1; /* * [16:16]runaway error */ + unsigned int runawayMerr : 1; /* * [17:17] */ + unsigned int reserved : 14; /* * [31:18]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR0_U; + +/* ** + * Union name : SMEG1_ERR0_MASK + * @brief error register 1 + * Description: + */ +typedef union tagUnSmeg1Err0Mask { + struct tagStSmeg1Err0Mask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9]reserved. */ + unsigned int runawayErrMask : 1; /* * [8:8]err mask of runaway error */ + unsigned int eccCrtErrMask7 : 1; /* * [7:7]err mask of ECC correctable error 7 */ + unsigned int eccCrtErrMask6 : 1; /* * [6:6]err mask of ECC correctable error 6 */ + unsigned int eccCrtErrMask5 : 1; /* * [5:5]err mask of ECC correctable error 5 */ + unsigned int eccCrtErrMask4 : 1; /* * [4:4]err mask of ECC correctable error 4 */ + unsigned int eccCrtErrMask3 : 1; /* * [3:3]err mask of ECC correctable error 3 */ + unsigned int eccCrtErrMask2 : 1; /* * [2:2]err mask of ECC correctable error 2 */ + unsigned int eccCrtErrMask1 : 1; /* * [1:1]err mask of ECC correctable error 1 */ + unsigned int eccCrtErrMask0 : 1; /* * [0:0]err mask of ECC correctable error 0 */ +#else + unsigned int eccCrtErrMask0 : 1; /* * [0:0]err mask of ECC correctable error 0 */ + unsigned int eccCrtErrMask1 : 1; /* * [1:1]err mask of ECC correctable error 1 */ + unsigned int eccCrtErrMask2 : 1; /* * [2:2]err mask of ECC correctable error 2 */ + unsigned int eccCrtErrMask3 : 1; /* * [3:3]err mask of ECC correctable error 3 */ + unsigned int eccCrtErrMask4 : 1; /* * [4:4]err mask of ECC correctable error 4 */ + unsigned int eccCrtErrMask5 : 1; /* * [5:5]err mask of ECC correctable error 5 */ + unsigned int eccCrtErrMask6 : 1; /* * [6:6]err mask of ECC correctable error 6 */ + unsigned int eccCrtErrMask7 : 1; /* * [7:7]err mask of ECC correctable error 7 */ + unsigned int runawayErrMask : 1; /* * [8:8]err mask of runaway error */ + unsigned int reserved : 23; /* * [31:9]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR0_MASK_U; + +/* ** + * Union name : SMEG1_ERR1 + * @brief + * Description: + */ +typedef union tagUnSmeg1Err1 { + struct tagStSmeg1Err1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int eccUncrtMerr7 : 1; /* * [15:15] */ + unsigned int eccUncrtErr7 : 1; /* * [14:14]ECC uncorrectable error is detected on memory ARR */ + unsigned int eccUncrtMerr6 : 1; /* * [13:13] */ + unsigned int eccUncrtErr6 : 1; /* * [12:12]ECC uncorrectable error is detected on memory tdr */ + unsigned int eccUncrtMerr5 : 1; /* * [11:11] */ + unsigned int eccUncrtErr5 : 1; /* * [10:10]ECC uncorrectable error is detected on memory etr1 */ + unsigned int eccUncrtMerr4 : 1; /* * [9:9] */ + unsigned int eccUncrtErr4 : 1; /* * [8:8]ECC uncorrectable error is detected on memory etr0 */ + unsigned int eccUncrtMerr3 : 1; /* * [7:7] */ + unsigned int eccUncrtErr3 : 1; /* * [6:6]ECC uncorrectable error is detected on memory esr */ + unsigned int eccUncrtMerr2 : 1; /* * [5:5] */ + unsigned int eccUncrtErr2 : 1; /* * [4:4]ECC uncorrectable error is detected on memory fidr */ + unsigned int eccUncrtMerr1 : 1; /* * [3:3] */ + unsigned int eccUncrtErr1 : 1; /* * [2:2]ECC uncorrectable error is detected on memory gpr1 */ + unsigned int eccUncrtMerr0 : 1; /* * [1:1] */ + unsigned int eccUncrtErr0 : 1; /* * [0:0]ECC uncorrectable error is detected on memory gpr0 */ +#else + unsigned int eccUncrtErr0 : 1; /* * [0:0]ECC uncorrectable error is detected on memory gpr0 */ + unsigned int eccUncrtMerr0 : 1; /* * [1:1] */ + unsigned int eccUncrtErr1 : 1; /* * [2:2]ECC uncorrectable error is detected on memory gpr1 */ + unsigned int eccUncrtMerr1 : 1; /* * [3:3] */ + unsigned int eccUncrtErr2 : 1; /* * [4:4]ECC uncorrectable error is detected on memory fidr */ + unsigned int eccUncrtMerr2 : 1; /* * [5:5] */ + unsigned int eccUncrtErr3 : 1; /* * [6:6]ECC uncorrectable error is detected on memory esr */ + unsigned int eccUncrtMerr3 : 1; /* * [7:7] */ + unsigned int eccUncrtErr4 : 1; /* * [8:8]ECC uncorrectable error is detected on memory etr0 */ + unsigned int eccUncrtMerr4 : 1; /* * [9:9] */ + unsigned int eccUncrtErr5 : 1; /* * [10:10]ECC uncorrectable error is detected on memory etr1 */ + unsigned int eccUncrtMerr5 : 1; /* * [11:11] */ + unsigned int eccUncrtErr6 : 1; /* * [12:12]ECC uncorrectable error is detected on memory tdr */ + unsigned int eccUncrtMerr6 : 1; /* * [13:13] */ + unsigned int eccUncrtErr7 : 1; /* * [14:14]ECC uncorrectable error is detected on memory ARR */ + unsigned int eccUncrtMerr7 : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR1_U; + +/* ** + * Union name : SMEG1_ERR1_MASK + * @brief + * Description: + */ +typedef union tagUnSmeg1Err1Mask { + struct tagStSmeg1Err1Mask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 24; /* * [31:8]reserved. */ + unsigned int eccUncrtErrMask7 : 1; /* * [7:7]err mask of ECC uncorrectable error 7 */ + unsigned int eccUncrtErrMask6 : 1; /* * [6:6]err mask of ECC uncorrectable error 6 */ + unsigned int eccUncrtErrMask5 : 1; /* * [5:5]err mask of ECC uncorrectable error 5 */ + unsigned int eccUncrtErrMask4 : 1; /* * [4:4]err mask of ECC uncorrectable error 4 */ + unsigned int eccUncrtErrMask3 : 1; /* * [3:3]err mask of ECC uncorrectable error 3 */ + unsigned int eccUncrtErrMask2 : 1; /* * [2:2]err mask of ECC uncorrectable error 2 */ + unsigned int eccUncrtErrMask1 : 1; /* * [1:1]err mask of ECC uncorrectable error 1 */ + unsigned int eccUncrtErrMask0 : 1; /* * [0:0]err mask of ECC uncorrectable error 0 */ +#else + unsigned int eccUncrtErrMask0 : 1; /* * [0:0]err mask of ECC uncorrectable error 0 */ + unsigned int eccUncrtErrMask1 : 1; /* * [1:1]err mask of ECC uncorrectable error 1 */ + unsigned int eccUncrtErrMask2 : 1; /* * [2:2]err mask of ECC uncorrectable error 2 */ + unsigned int eccUncrtErrMask3 : 1; /* * [3:3]err mask of ECC uncorrectable error 3 */ + unsigned int eccUncrtErrMask4 : 1; /* * [4:4]err mask of ECC uncorrectable error 4 */ + unsigned int eccUncrtErrMask5 : 1; /* * [5:5]err mask of ECC uncorrectable error 5 */ + unsigned int eccUncrtErrMask6 : 1; /* * [6:6]err mask of ECC uncorrectable error 6 */ + unsigned int eccUncrtErrMask7 : 1; /* * [7:7]err mask of ECC uncorrectable error 7 */ + unsigned int reserved : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR1_MASK_U; + +/* ** + * Union name : SMEG1_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg1IndrectCtrl { + struct tagStSmeg1IndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1IndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smeg1IndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smeg1IndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg1IndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:GPR0 0x1:GPR1 0x2:ESR + 0x3:FIDR 0x4:FICR 0x5:Scoreboard （read to get data for debug,and write to + clear halt thread) 0x6:TDR (only in SMF) 0x7:ETR0(only in SMF) 0x8:ETR1(only + in SMF) 0x9:ARR (only in SMF) others:reservedNOTE：memory not support CSR write + oper ation when the thread is running */ + unsigned int + smeg1IndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.****** Comments for bit 9:3 - memory index **** + **For FICR: 8:3 instance ID, bit8 is RSV in SMFFor ScoreBoard: 7:3 thread ID, bit7 is + RSV in SMLFor fidr, 8:3 is instance id., bit8 is RSV in SMFFor gpr0/ gpr1,in SML: 9:8 + reserved, 7:4 is thread id; in SMF, 9 reserved, 8:4 is thread id. Bit3 is logic + flit id. For read gpr0, if bit3 is 0, read Flit0 ; if bit3 is 1, read flit2. For + read gpr1, if bit3 is 0, read flit1; if bit3 is 1, read flit3.For ETR0/ETR1, 9 + reserved, 8:4 is thread id. Bit3 is ETR id. For read ETR0, if bit3 is 0, read ID0 of + ETR0; if bit3 is 1, read ID1 of ETR0. For read ETR1, if bit3 is 0, read ID0 of + ETR1; if bit 3 is 1, read ID1 of ETR1.For esr, in SMF, 9 reserved, if bit8 is + 0,access normal esr0, if bit8 is 1,access esr1. (RSV in 1822) 7:3 is thread id.in SML + , bit9:7 reserved, 6:3 is thread id. For TDR: (only in SMF)bit7:3 is thread ID****** + Comments for bit 2:0 - word sel ******1. refer to FS AS for the detail data structure, and + ECC bit is read only2. DO NOT read write the word out of the MSB of the corresponding MEM + 0x0:0x2 + - reserved 0x3: data[159:128] 0x4: data[127:96] 0x5: + data[95:64] 0x6: data[63:32] 0x7: data[31:0] + */ +#else + unsigned int + smeg1IndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.****** Comments for bit 9:3 - memory index **** + **For FICR: 8:3 instance ID, bit8 is RSV in SMFFor ScoreBoard: 7:3 thread ID, bit7 is + RSV in SMLFor fidr, 8:3 is instance id., bit8 is RSV in SMFFor gpr0/ gpr1,in SML: 9:8 + reserved, 7:4 is thread id; in SMF, 9 reserved, 8:4 is thread id. Bit3 is logic + flit id. For read gpr0, if bit3 is 0, read Flit0 ; if bit3 is 1, read flit2. For + read gpr1, if bit3 is 0, read flit1; if bit3 is 1, read flit3.For ETR0/ETR1, 9 + reserved, 8:4 is thread id. Bit3 is ETR id. For read ETR0, if bit3 is 0, read ID0 of + ETR0; if bit3 is 1, read ID1 of ETR0. For read ETR1, if bit3 is 0, read ID0 of + ETR1; if bit 3 is 1, read ID1 of ETR1.For esr, in SMF, 9 reserved, if bit8 is + 0,access normal esr0, if bit8 is 1,access esr1. (RSV in 1822) 7:3 is thread id.in SML + , bit9:7 reserved, 6:3 is thread id. For TDR: (only in SMF)bit7:3 is thread ID****** + Comments for bit 2:0 - word sel ******1. refer to FS AS for the detail data structure, and + ECC bit is read only2. DO NOT read write the word out of the MSB of the corresponding MEM + 0x0:0x2 + - reserved 0x3: data[159:128] 0x4: data[127:96] 0x5: + data[95:64] 0x6: data[63:32] 0x7: data[31:0] + */ + unsigned int smeg1IndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:GPR0 0x1:GPR1 0x2:ESR + 0x3:FIDR 0x4:FICR 0x5:Scoreboard （read to get data for debug,and write to + clear halt thread) 0x6:TDR (only in SMF) 0x7:ETR0(only in SMF) 0x8:ETR1(only + in SMF) 0x9:ARR (only in SMF) others:reservedNOTE：memory not support CSR write + oper ation when the thread is running */ + unsigned int smeg1IndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg1IndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smeg1IndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG1_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg1IndrectTimeout { + struct tagStSmeg1IndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1IndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg1IndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG1_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg1IndrectData { + struct tagStSmeg1IndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1IndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smeg1IndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INDRECT_DATA_U; + +/* ** +* Union name : SMEG1_CNT_CFG +* @brief SMEG1 counter configuration register. This register is used for debug or for statistics +collection + +* Description: +*/ +typedef union tagUnSmeg1CntCfg { + struct tagStSmeg1CntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]SMEG1 has four counters to count various events generated in the + infrastructure or in the engines. For the engines, the events can also be counted for a + specif ic instance, as programmed in the smeg1_cnt_match_id register. */ + unsigned int cnt3Sel : 1; /* * [12:12]0: SEND1:ENGINE_EVENT[3] */ + unsigned int cnt2Sel : 1; /* * [11:11]0:FINISH1:ENGINE_EVENT[2] */ + unsigned int cnt1Sel : 2; /* * [10:9]00:WAKEUP01:SLEEP10:ENGINE_LD_ST11:ENGINE_EVENT[1] */ + unsigned int cnt0Sel : 1; /* * [8:8]0:INSTALL1:ENGINE_EVENT[0] */ + unsigned int cnt3MatchEn : 1; /* * [7:7]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt2MatchEn : 1; /* * [6:6]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt1MatchEn : 1; /* * [5:5]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt0MatchEn : 1; /* * [4:4]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ +#else + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt0MatchEn : 1; /* * [4:4]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt1MatchEn : 1; /* * [5:5]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt2MatchEn : 1; /* * [6:6]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt3MatchEn : 1; /* * [7:7]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt0Sel : 1; /* * [8:8]0:INSTALL1:ENGINE_EVENT[0] */ + unsigned int cnt1Sel : 2; /* * [10:9]00:WAKEUP01:SLEEP10:ENGINE_LD_ST11:ENGINE_EVENT[1] */ + unsigned int cnt2Sel : 1; /* * [11:11]0:FINISH1:ENGINE_EVENT[2] */ + unsigned int cnt3Sel : 1; /* * [12:12]0: SEND1:ENGINE_EVENT[3] */ + unsigned int reserved : 19; /* * [31:13]SMEG1 has four counters to count various events generated in the + infrastructure or in the engines. For the engines, the events can also be counted for a + specif ic instance, as programmed in the smeg1_cnt_match_id register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CNT_CFG_U; + +/* ** +* Union name : SMEG1_CNT_MATCH_ID +* @brief This register is used to configure Instance IDs for all four counters. This can be used for +debug or for performance analysis. + +* Description: +*/ +typedef union tagUnSmeg1CntMatchId { + struct tagStSmeg1CntMatchId { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 8; /* * [31:24]reserved */ + unsigned int cnt3MatchId : 6; /* * [23:18]Instance ID for counter 3 */ + unsigned int cnt2MatchId : 6; /* * [17:12]Instance ID for counter 2 */ + unsigned int cnt1MatchId : 6; /* * [11:6]Instance ID for counter 1 */ + unsigned int cnt0MatchId : 6; /* * [5:0]Instance ID for counter 0 */ +#else + unsigned int cnt0MatchId : 6; /* * [5:0]Instance ID for counter 0 */ + unsigned int cnt1MatchId : 6; /* * [11:6]Instance ID for counter 1 */ + unsigned int cnt2MatchId : 6; /* * [17:12]Instance ID for counter 2 */ + unsigned int cnt3MatchId : 6; /* * [23:18]Instance ID for counter 3 */ + unsigned int reserved : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CNT_MATCH_ID_U; + +/* ** +* Union name : SMEG1_CNT0 +* @brief This smmeg1 counter0 register is a statistics counter that counts API install and engine event0 + +* Description: +*/ +typedef union tagUnSmeg1Cnt0 { + struct tagStSmeg1Cnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt0 : 48; /* * [47:0]depending on the configuration this counter counts command + * install, or engine event 0. This can also be programmed to count only for + * a specific instance + */ +#else + unsigned long long smeg1Cnt0 : 48; /* * [47:0]depending on the configuration this counter counts command + * install, or engine event 0. This can also be programmed to count only for + * a specific instance + */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT0_U; + +/* ** +* Union name : SMEG1_CNT1 +* @brief This smeg1 counter1 register is a statistics counter that counts load, store, sleep, wakeup, and +engine event 1 + +* Description: +*/ +typedef union tagUnSmeg1Cnt1 { + struct tagStSmeg1Cnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt1 : 48; /* * [47:0]depending on the configuration this counter counts thread + prel-oadstore, sleep, wakeup, or engine event 1. This can also be programmed to count + only for a spec ific instance */ +#else + unsigned long long smeg1Cnt1 : 48; /* * [47:0]depending on the configuration this counter counts thread + prel-oadstore, sleep, wakeup, or engine event 1. This can also be programmed to count + only for a spec ific instance */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT1_U; + +/* ** +* Union name : SMEG1_CNT2 +* @brief This smeg1 counter1 register is a statistics counter that counts 'finish' or engine event 2 + +* Description: +*/ +typedef union tagUnSmeg1Cnt2 { + struct tagStSmeg1Cnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt2 : 48; /* * [47:0]depending on the configuration this counter counts thread + * terminate, or engine event 2. This can also be programmed to count only + * for a specific instance + */ +#else + unsigned long long smeg1Cnt2 : 48; /* * [47:0]depending on the configuration this counter counts thread + * terminate, or engine event 2. This can also be programmed to count only + * for a specific instance + */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT2_U; + +/* ** +* Union name : SMEG1_CNT3 +* @brief This smeg1 counter3 register is a statistics counter that counts 'send' and engine event 3 + +* Description: +*/ +typedef union tagUnSmeg1Cnt3 { + struct tagStSmeg1Cnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt3 : 48; /* * [47:0]depending on the configuration this counter counts message send to + * smit , or engine event 3. This can also be programmed to count only for a + * specific instance + */ +#else + unsigned long long smeg1Cnt3 : 48; /* * [47:0]depending on the configuration this counter counts message send to + * smit , or engine event 3. This can also be programmed to count only for a + * specific instance + */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT3_U; + +/* ** +* Union name : SMEG1_TCD_CTP +* @brief This is the SMEG1 thread TCD register. This register contains the read data that comes from +the TCD. + +* Description: +*/ +typedef union tagUnSmeg1TcdCtp { + struct tagStSmeg1TcdCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 8; /* * [31:24]reserved. */ + unsigned int ctp : 24; /* * [23:0][23:18] : instance id [17:15]: error response type[14] : rd2_etr1_id[13] : + rd2_etr0_id[12] : rd1_etr1_id[11] : rd1_etr0_id [10] : o-bit [9:5] : engine id[4] : gpr1 id + in second issue[3] : gpr0 id in second issue[2] : dual issue [1] : gpr1 id in first issue [0] + : gpr0 id in first issue + */ +#else + unsigned int ctp : 24; /* * [23:0][23:18] : instance id [17:15]: error response type[14] : rd2_etr1_id[13] : + rd2_etr0_id[12] : rd1_etr1_id[11] : rd1_etr0_id [10] : o-bit [9:5] : engine id[4] : gpr1 id + in second issue[3] : gpr0 id in second issue[2] : dual issue [1] : gpr1 id in first issue [0] + : gpr0 id in first issue + */ + unsigned int reserved : 8; /* * [31:24]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TCD_CTP_U; + +/* ** +* Union name : SMEG1_RUNAWAY_THD_CTP +* @brief Each bit represents a runaway thread. When a thread runs for more than a sampling time, it is +considered a runaway thread. Bit63 logs runaway errors for the t hread 63, and bit0 logs the error for the thread 0 +respectively. +* Description: +*/ +typedef union tagUnSmeg1RunawayThdCtp { + struct tagStSmeg1RunawayThdCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]1: This thread is active for a very long time (>sample period). No new issue + for this thread. 0: nor mal + operation If configured, this register also can be + used for active thread ctp. + */ +#else + unsigned int ctp : 32; /* * [31:0]1: This thread is active for a very long time (>sample period). No new issue + for this thread. 0: nor mal + operation If configured, this register also can be + used for active thread ctp. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_RUNAWAY_THD_CTP_U; + +/* ** + * Union name : SMEG1_CTP0 + * @brief This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. + * Description: + */ +typedef union tagUnSmeg1Ctp0 { + struct tagStSmeg1Ctp0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 8; /* * [63:56]reserved. */ + unsigned long long tcd : 24; /* * [55:32]TCD ctp registers */ + unsigned long long activeRunawayThd : 32; /* * [31:0]32thread scoreboard active */ +#else + unsigned long long activeRunawayThd : 32; /* * [31:0]32thread scoreboard active */ + unsigned long long tcd : 24; /* * [55:32]TCD ctp registers */ + unsigned long long reserved : 8; /* * [63:56]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CTP0_U; + +/* ** + * Union name : SMEG1_CTP1 + * @brief This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. + * Description: + */ +typedef union tagUnSmeg1Ctp1 { + struct tagStSmeg1Ctp1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 20; /* * [63:44]reserved */ + unsigned long long smeg1Internal : 44; /* * [43:0][43:41] fifoD_ctl_credit(6), [40:38] fifoD_data_credit(6) + [37] fifo a_sop(0) [36] fifob_sop(0) + [35] fifoc_sop(0) [34] fifoa_eop(0) [33] fifob_eop(0) [32] + fifoc_eop(0) [31] + riq_valid(0), [30] iiq_valid(0), [29] + fifoa_allocated(0), [28] fifob_allocated(0), [27] + fifoc_allocated(0), [26] abuf_afifo_valid(0), + [25] fifob_prestore(0), [24] fifoc_prestore(0), + [23:20] fairness_count(0), [19:17] reserved (0)[16] fifoe_empty(1)[15] + fifoe_full (0) [14] fifoa_empty(1) + [13] fifoa_full (0) [12] fifob_empty(1) + [11] fifob_full(0) [10] fifoC_empty(1), [9] + fifoc_full(0) [8:2] + available_thd_id The default value of availble_thd_id in SML and SMF is dif + ferent, SML is 14 in Dec; SMF is 30 in Dec. [1] allocate_available(1) [0] + resp_thd_free (0)The default value of smeg1_internal in SMF is 0x0d800001547a; in + SML is :0x0d800001543a; + */ +#else + unsigned long long smeg1Internal : 44; /* * [43:0][43:41] fifoD_ctl_credit(6), [40:38] fifoD_data_credit(6) + [37] fifo a_sop(0) [36] fifob_sop(0) + [35] fifoc_sop(0) [34] fifoa_eop(0) [33] fifob_eop(0) [32] + fifoc_eop(0) [31] + riq_valid(0), [30] iiq_valid(0), [29] + fifoa_allocated(0), [28] fifob_allocated(0), [27] + fifoc_allocated(0), [26] abuf_afifo_valid(0), + [25] fifob_prestore(0), [24] fifoc_prestore(0), + [23:20] fairness_count(0), [19:17] reserved (0)[16] fifoe_empty(1)[15] + fifoe_full (0) [14] fifoa_empty(1) + [13] fifoa_full (0) [12] fifob_empty(1) + [11] fifob_full(0) [10] fifoC_empty(1), [9] + fifoc_full(0) [8:2] + available_thd_id The default value of availble_thd_id in SML and SMF is dif + ferent, SML is 14 in Dec; SMF is 30 in Dec. [1] allocate_available(1) [0] + resp_thd_free (0)The default value of smeg1_internal in SMF is 0x0d800001547a; in + SML is :0x0d800001543a; + */ + unsigned long long reserved : 20; /* * [63:44]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CTP1_U; + +/* ** + * Union name : SMEG1_CTP2 + * @brief This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. + * Description: + */ +typedef union tagUnSmeg1Ctp2 { + struct tagStSmeg1Ctp2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int wtRunaway : 32; /* * [31:0]thread runaway counter has overflow, and thread is in the status of + * waiting new issued of this thread or terminate of this thread; + */ +#else + unsigned int wtRunaway : 32; /* * [31:0]thread runaway counter has overflow, and thread is in the status of + * waiting new issued of this thread or terminate of this thread; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CTP2_U; + +/* ** + * Union name : SMEG1_TMT_EXT_CFG + * @brief TIMER engine control info + * Description: + */ +typedef union tagUnSmeg1TmtExtCfg { + struct tagStSmeg1TmtExtCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmtExtCfg : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 31Bit [29:28]: entry + 30Bit [27: 26]: entry 29Bit [25:24]: entry 28Bit [23:22]: entry 27Bit [21:20]: + entry 26Bit [19:18]: entry 25Bit [17:16]: entry 24Bit [15:14]: entry 23Bit + [13:12]: entry 22 Bit [11:10]: entry 21Bit [9:8] : entry 20Bit [7:6] : entry + 19Bit [5:4] : entry 18Bit [3:2] : entry 17Bit [1:0] : entry 16 + */ +#else + unsigned int smeg1TmtExtCfg : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 31Bit [29:28]: entry + 30Bit [27: 26]: entry 29Bit [25:24]: entry 28Bit [23:22]: entry 27Bit [21:20]: + entry 26Bit [19:18]: entry 25Bit [17:16]: entry 24Bit [15:14]: entry 23Bit + [13:12]: entry 22 Bit [11:10]: entry 21Bit [9:8] : entry 20Bit [7:6] : entry + 19Bit [5:4] : entry 18Bit [3:2] : entry 17Bit [1:0] : entry 16 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TMT_EXT_CFG_U; + +/* ** +* Union name : SMEG1_MEM_ECC_ERR_CTP +* @brief ecc ERR ADDR; CAPTURE the last err addr;only valid when the ECC interrupt is reported; + +* Description: +*/ +typedef union tagUnSmeg1MemEccErrCtp { + struct tagStSmeg1MemEccErrCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 18; /* * [31:14]reserved */ + unsigned int addr : 6; /* * [13:8]err_addr:for fidr: err instance ID;for other mem: [13:9]-error thread ID, + * bit[8]-err mem ID; + */ + unsigned int flag : 8; /* * [7:0]flag to indicate which memory the err_addr is:7 - fidr6 - gpr05 - gpr14 - etr03 + * - etr12 - esr1 - tdr0 - arr + */ +#else + unsigned int flag : 8; /* * [7:0]flag to indicate which memory the err_addr is:7 - fidr6 - gpr05 - gpr14 - etr03 + * - etr12 - esr1 - tdr0 - arr + */ + unsigned int addr : 6; /* * [13:8]err_addr:for fidr: err instance ID;for other mem: [13:9]-error thread ID, + * bit[8]-err mem ID; + */ + unsigned int reserved : 18; /* * [31:14]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_MEM_ECC_ERR_CTP_U; + +/* ** + * Union name : SMMC_CACHE_RESOURCE_CTP + * @brief SMMC WQE Cache resource counter + * Description: + */ +typedef union tagUnSmmcCacheResourceCtp { + struct tagStSmmcCacheResourceCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved */ + unsigned int rqCnt : 14; /* * [29:16]SMMC RQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ + unsigned int reserved1 : 2; /* * [15:14]reserved */ + unsigned int sqCnt : 14; /* * [13:0]SMMC SQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ +#else + unsigned int sqCnt : 14; /* * [13:0]SMMC SQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ + unsigned int reserved1 : 2; /* * [15:14]reserved */ + unsigned int rqCnt : 14; /* * [29:16]SMMC RQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ + unsigned int reserved0 : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_CACHE_RESOURCE_CTP_U; + +/* ** + * Union name : SMEG1_SYNC_API_CFG + * @brief SYNC_API configuration register + * Description: + */ +typedef union tagUnSmeg1SyncApiCfg { + struct tagStSmeg1SyncApiCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 22; /* * [31:10]reserved */ + unsigned int syncCntThreshold : 2; /* * [9:8]The number of sync API allowed to waiting for getting lock must be + * equal or less than this threshold.0: max number is 4;1~3: max number; + */ + unsigned int reserved1 : 2; /* * [7:6]reserved */ + unsigned int snapshotEngEn : 1; /* * [5:5]enable snapshot based engine ID0: disable1: enable */ + unsigned int snapshotEngId : 5; /* * [4:0]SYNC_API snapshot engine IDdefault to timer engine ID. */ +#else + unsigned int snapshotEngId : 5; /* * [4:0]SYNC_API snapshot engine IDdefault to timer engine ID. */ + unsigned int snapshotEngEn : 1; /* * [5:5]enable snapshot based engine ID0: disable1: enable */ + unsigned int reserved1 : 2; /* * [7:6]reserved */ + unsigned int syncCntThreshold : 2; /* * [9:8]The number of sync API allowed to waiting for getting lock must be + * equal or less than this threshold.0: max number is 4;1~3: max number; + */ + unsigned int reserved0 : 22; /* * [31:10]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_SYNC_API_CFG_U; + +/* ** + * Union name : SMEG1_CUR_TIMESTAMP_US + * @brief Current timestamp (us) + * Description: + */ +typedef union tagUnSmeg1CurTimestampUs { + struct tagStSmeg1CurTimestampUs { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 15; /* * [63:49]reserved. */ + unsigned long long ctp : 49; /* * [48:0]Current timestamp (us) */ +#else + unsigned long long ctp : 49; /* * [48:0]Current timestamp (us) */ + unsigned long long reserved : 15; /* * [63:49]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CUR_TIMESTAMP_US_U; + + +/* ** + * Union name : SMIT_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmitVersion { + struct tagStSmitVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smitVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_VERSION_U; + +/* ** +* Union name : SMIT_CFG +* @brief This is the Smart Memory Infra Transmission (SMIT) module configuration register. The software +use this register for debug. + +* Description: +*/ +typedef union tagUnSmitCfg { + struct tagStSmitCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 12; /* * [31:20]reserved */ + unsigned int rpUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int rpCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int memPbChkEn : 1; /* * [17:17]memory check enable.1'b0:disable all memories check.1'b1:enable all + * memories check. + */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved1 : 7; /* * [7:1] */ + unsigned int disOder : 1; /* * [0:0]Ordering queue enable configuration.this is for debug . Software can + disable SMIT ordering queue function via this field . Hw will ignore O-bit inside API w + hen software set this field. 1 : disable ordering transmission .0: enable ordering + transmission.Note:only used for debug,users should know the api counts before + config this bit. */ +#else + unsigned int disOder : 1; /* * [0:0]Ordering queue enable configuration.this is for debug . Software can + disable SMIT ordering queue function via this field . Hw will ignore O-bit inside API w + hen software set this field. 1 : disable ordering transmission .0: enable ordering + transmission.Note:only used for debug,users should know the api counts before + config this bit. */ + unsigned int reserved1 : 7; /* * [7:1] */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int memPbChkEn : 1; /* * [17:17]memory check enable.1'b0:disable all memories check.1'b1:enable all + * memories check. + */ + unsigned int rpCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int reserved0 : 12; /* * [31:20]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_CFG_U; + +/* ** + * Union name : SMIT_INT_VECTOR + * @brief SMIT interrupt vector + * Description: + */ +typedef union tagUnSmitIntVector { + struct tagStSmitIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INT_VECTOR_U; + +/* ** + * Union name : SMIT_INT + * @brief SMIT interrupt status vector + * Description: + */ +typedef union tagUnSmitInt { + struct tagStSmitInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + corresponding error registers on the sheet1 : SMIT memory (TMDR/TMHR/TMNHR) parity error + deteced . 0 : No SMIT memory parity error deteced. */ +#else + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + corresponding error registers on the sheet1 : SMIT memory (TMDR/TMHR/TMNHR) parity error + deteced . 0 : No SMIT memory parity error deteced. */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INT_U; + +/* ** + * Union name : SMIT_INT_MASK + * @brief SMIT interrupt mask vector + * Description: + */ +typedef union tagUnSmitIntMask { + struct tagStSmitIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INT_MASK_U; + +/* ** + * Union name : SMIT_ERR_PRTY + * @brief RSV + * Description: + */ +typedef union tagUnSmitErrPrty { + struct tagStSmitErrPrty { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]RSV */ + unsigned int errorBit : 1; /* * [0:0]RSV */ +#else + unsigned int errorBit : 1; /* * [0:0]RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]RSV */ + unsigned int sticky : 30; /* * [31:2]RSV */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_ERR_PRTY_U; + +/* ** + * Union name : SMIT_MEM_ECC_CRT_ERR + * @brief tmdr ecc correctable err + * Description: + */ +typedef union tagUnSmitMemEccCrtErr { + struct tagStSmitMemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMIT_MEM_ECC_UNCRT_ERR + * @brief tmdr ecc uncorrectable err + * Description: + */ +typedef union tagUnSmitMemEccUncrtErr { + struct tagStSmitMemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMIT_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmitIndrectCtrl { + struct tagStSmitIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smitIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smitIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smitIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:TMHR 0x1:TMNHR + 0x2:TMLIST (only support read op) 0x3:TMCD (only support read op) 0x4:TMDR0 + 0x5:TMDR1 0x6: TMDR2 0x7:TMDR3 others:reserved */ + unsigned int smitIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.1.bit[11:3] memory address in SML: + TMDR bit[10:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid in SMF: TMDR + bit[11:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid2.bit[2:0] word select: + 0~3: reserved, 0x4:mem_dat[127:96] 0x5:mem_dat[95:64] 0x6:mem_dat[63:32] + 0x7:mem_dat[31:0]Note 1: for accessing tmhr/ tmnhr/ tmlist/ tmcd,bit[2:0] shoul d + be 0x7.; */ +#else + unsigned int smitIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.1.bit[11:3] memory address in SML: + TMDR bit[10:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid in SMF: TMDR + bit[11:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid2.bit[2:0] word select: + 0~3: reserved, 0x4:mem_dat[127:96] 0x5:mem_dat[95:64] 0x6:mem_dat[63:32] + 0x7:mem_dat[31:0]Note 1: for accessing tmhr/ tmnhr/ tmlist/ tmcd,bit[2:0] shoul d + be 0x7.; */ + unsigned int smitIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:TMHR 0x1:TMNHR + 0x2:TMLIST (only support read op) 0x3:TMCD (only support read op) 0x4:TMDR0 + 0x5:TMDR1 0x6: TMDR2 0x7:TMDR3 others:reserved */ + unsigned int smitIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smitIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smitIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INDRECT_CTRL_U; + +/* ** + * Union name : SMIT_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmitIndrectTimeout { + struct tagStSmitIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smitIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMIT_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmitIndrectData { + struct tagStSmitIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smitIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INDRECT_DATA_U; + + +/* ** + * Union name : SMLC_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmlcVersion { + struct tagStSmlcVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smlcVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_VERSION_U; + +/* ** + * Union name : SMLC_CFG0 + * @brief Smart Memory Lock Cache Controller (SMLC) configuration 0. + * Description: + */ +typedef union tagUnSmlcCfg0 { + struct tagStSmlcCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 8; /* * [31:24]reserved */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved1 : 5; /* * [7:3]reserved */ + unsigned int smlcUncrtErrInj : 1; /* * [2:2]smlc ECC un-corrected err injection requestion;err injection start + when posedge of this bit is detected; After Err injection start, err is injected + when a memor y read is issued to the memory. */ + unsigned int smlcCrtErrInj : 1; /* * [1:1]smlc ECC corrected err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when a + memory r ead is issued to the memory. */ + unsigned int smlcEccChkEn : 1; /* * [0:0]whether enable ECC check.0:disable;1:enable. */ +#else + unsigned int smlcEccChkEn : 1; /* * [0:0]whether enable ECC check.0:disable;1:enable. */ + unsigned int smlcCrtErrInj : 1; /* * [1:1]smlc ECC corrected err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when a + memory r ead is issued to the memory. */ + unsigned int smlcUncrtErrInj : 1; /* * [2:2]smlc ECC un-corrected err injection requestion;err injection start + when posedge of this bit is detected; After Err injection start, err is injected + when a memor y read is issued to the memory. */ + unsigned int reserved1 : 5; /* * [7:3]reserved */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int reserved0 : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CFG0_U; + +/* ** + * Union name : SMLC_CFG1 + * @brief Smart Memory Lock Cache Controller (SMLC) configuration 1. + * Description: + */ +typedef union tagUnSmlcCfg1 { + struct tagStSmlcCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int bypassCd310 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data31~cache data0.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#else + unsigned int bypassCd310 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data31~cache data0.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CFG1_U; + +/* ** + * Union name : SMLC_CFG2 + * @brief Smart Memory Lock Cache Controller (SMLC) configuration 2. + * Description: + */ +typedef union tagUnSmlcCfg2 { + struct tagStSmlcCfg2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int bypassCd6332 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data63~cache data32.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#else + unsigned int bypassCd6332 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data63~cache data32.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CFG2_U; + +/* ** + * Union name : SMLC_INT_VECTOR + * @brief Smart Memory Lock Cache Controller (SMLC) interrupt vector register + * Description: + */ +typedef union tagUnSmlcIntVector { + struct tagStSmlcIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INT_VECTOR_U; + +/* ** + * Union name : SMLC_INT + * @brief Smart Memory Lock Cache Controller (SMLC) interrupt data register + * Description: + */ +typedef union tagUnSmlcInt { + struct tagStSmlcInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 14; /* * [15:2]reserved */ + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 14; /* * [15:2]reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INT_U; + +/* ** + * Union name : SMLC_INT_MASK + * @brief Smart Memory Lock Cache Controller (SMLC) interrupt mask register. + * Description: + */ +typedef union tagUnSmlcIntMask { + struct tagStSmlcIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INT_MASK_U; + +/* ** + * Union name : SMLC_SRF_OV_ERR + * @brief srf fifo overflow error. + * Description: + */ +typedef union tagUnSmlcSrfOvErr { + struct tagStSmlcSrfOvErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]This field is fixed to be 0. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 1; /* * [2:2]This field is fixed to be 0. */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_SRF_OV_ERR_U; + +/* ** + * Union name : SMLC_ECC_ERR + * @brief memory ecc error. + * Description: + */ +typedef union tagUnSmlcEccErr { + struct tagStSmlcEccErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 8; /* * [31:24]reserved. */ + unsigned int pab2bEccMerr : 1; /* * [23:23]pab memory 2bit ECC multi error; */ + unsigned int pab2bEccErr : 1; /* * [22:22]pab memory 2bit ECC error; */ + unsigned int pab1bEccMerr : 1; /* * [21:21]pab memory 1bit ECC multi error; */ + unsigned int pab1bEccErr : 1; /* * [20:20]pab memory 1bit ECC error; */ + unsigned int cdb12bEccMerr : 1; /* * [19:19]cdb1 memory 2bit ECC multi error; */ + unsigned int cdb12bEccErr : 1; /* * [18:18]cdb1 memory 2bit ECC error; */ + unsigned int cdb11bEccMerr : 1; /* * [17:17]cdb1 memory 1bit ECC multi error; */ + unsigned int cdb11bEccErr : 1; /* * [16:16]cdb1 memory 1bit ECC error; */ + unsigned int cdb02bEccMerr : 1; /* * [15:15]cdb0 memory 2bit ECC multi error; */ + unsigned int cdb02bEccErr : 1; /* * [14:14]cdb0 memory 2bit ECC error; */ + unsigned int cdb01bEccMerr : 1; /* * [13:13]cdb0 memory 1bit ECC multi error; */ + unsigned int cdb01bEccErr : 1; /* * [12:12]cdb0 memory 1bit ECC error; */ + unsigned int stb2bEccMerr : 1; /* * [11:11]stb memory 2bit ECC multi error; */ + unsigned int stb2bEccErr : 1; /* * [10:10]stb memory 2bit ECC error; */ + unsigned int stb1bEccMerr : 1; /* * [9:9]stb memory 1bit ECC multi error; */ + unsigned int stb1bEccErr : 1; /* * [8:8]stb memory 1bit ECC error; */ + unsigned int bat2bEccMerr : 1; /* * [7:7]bat memory 2bit ECC multi error; */ + unsigned int bat2bEccErr : 1; /* * [6:6]bat memory 2bit ECC error; */ + unsigned int bat1bEccMerr : 1; /* * [5:5]bat memory 1bit ECC multi error; */ + unsigned int bat1bEccErr : 1; /* * [4:4]bat memory 1bit ECC error; */ + unsigned int fiar2bEccMerr : 1; /* * [3:3]fiar memory 2bit ECC multi error; */ + unsigned int fiar2bEccErr : 1; /* * [2:2]fiar memory 2bit ECC error; */ + unsigned int fiar1bEccMerr : 1; /* * [1:1]fiar memory 1bit ECC multi error; */ + unsigned int fiar1bEccErr : 1; /* * [0:0]fiar memory 1bit ECC error; */ +#else + unsigned int fiar1bEccErr : 1; /* * [0:0]fiar memory 1bit ECC error; */ + unsigned int fiar1bEccMerr : 1; /* * [1:1]fiar memory 1bit ECC multi error; */ + unsigned int fiar2bEccErr : 1; /* * [2:2]fiar memory 2bit ECC error; */ + unsigned int fiar2bEccMerr : 1; /* * [3:3]fiar memory 2bit ECC multi error; */ + unsigned int bat1bEccErr : 1; /* * [4:4]bat memory 1bit ECC error; */ + unsigned int bat1bEccMerr : 1; /* * [5:5]bat memory 1bit ECC multi error; */ + unsigned int bat2bEccErr : 1; /* * [6:6]bat memory 2bit ECC error; */ + unsigned int bat2bEccMerr : 1; /* * [7:7]bat memory 2bit ECC multi error; */ + unsigned int stb1bEccErr : 1; /* * [8:8]stb memory 1bit ECC error; */ + unsigned int stb1bEccMerr : 1; /* * [9:9]stb memory 1bit ECC multi error; */ + unsigned int stb2bEccErr : 1; /* * [10:10]stb memory 2bit ECC error; */ + unsigned int stb2bEccMerr : 1; /* * [11:11]stb memory 2bit ECC multi error; */ + unsigned int cdb01bEccErr : 1; /* * [12:12]cdb0 memory 1bit ECC error; */ + unsigned int cdb01bEccMerr : 1; /* * [13:13]cdb0 memory 1bit ECC multi error; */ + unsigned int cdb02bEccErr : 1; /* * [14:14]cdb0 memory 2bit ECC error; */ + unsigned int cdb02bEccMerr : 1; /* * [15:15]cdb0 memory 2bit ECC multi error; */ + unsigned int cdb11bEccErr : 1; /* * [16:16]cdb1 memory 1bit ECC error; */ + unsigned int cdb11bEccMerr : 1; /* * [17:17]cdb1 memory 1bit ECC multi error; */ + unsigned int cdb12bEccErr : 1; /* * [18:18]cdb1 memory 2bit ECC error; */ + unsigned int cdb12bEccMerr : 1; /* * [19:19]cdb1 memory 2bit ECC multi error; */ + unsigned int pab1bEccErr : 1; /* * [20:20]pab memory 1bit ECC error; */ + unsigned int pab1bEccMerr : 1; /* * [21:21]pab memory 1bit ECC multi error; */ + unsigned int pab2bEccErr : 1; /* * [22:22]pab memory 2bit ECC error; */ + unsigned int pab2bEccMerr : 1; /* * [23:23]pab memory 2bit ECC multi error; */ + unsigned int reserved : 8; /* * [31:24]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_ECC_ERR_U; + +/* ** + * Union name : SMLC_ECC_ERRPR_MASK + * @brief + * Description: + */ +typedef union tagUnSmlcEccErrprMask { + struct tagStSmlcEccErrprMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved. */ + unsigned int pab2bEccErrMask : 1; /* * [11:11] */ + unsigned int pab1bEccErrMask : 1; /* * [10:10] */ + unsigned int cdb12bEccErrMask : 1; /* * [9:9] */ + unsigned int cdb11bEccErrMask : 1; /* * [8:8] */ + unsigned int cdb02bEccErrMask : 1; /* * [7:7] */ + unsigned int cdb01bEccErrMask : 1; /* * [6:6] */ + unsigned int stb2bEccErrMask : 1; /* * [5:5] */ + unsigned int stb1bEccErrMask : 1; /* * [4:4] */ + unsigned int bat2bEccErrMask : 1; /* * [3:3] */ + unsigned int bat1bEccErrMask : 1; /* * [2:2] */ + unsigned int fiar2bEccErrMask : 1; /* * [1:1] */ + unsigned int fiar1bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int fiar1bEccErrMask : 1; /* * [0:0] */ + unsigned int fiar2bEccErrMask : 1; /* * [1:1] */ + unsigned int bat1bEccErrMask : 1; /* * [2:2] */ + unsigned int bat2bEccErrMask : 1; /* * [3:3] */ + unsigned int stb1bEccErrMask : 1; /* * [4:4] */ + unsigned int stb2bEccErrMask : 1; /* * [5:5] */ + unsigned int cdb01bEccErrMask : 1; /* * [6:6] */ + unsigned int cdb02bEccErrMask : 1; /* * [7:7] */ + unsigned int cdb11bEccErrMask : 1; /* * [8:8] */ + unsigned int cdb12bEccErrMask : 1; /* * [9:9] */ + unsigned int pab1bEccErrMask : 1; /* * [10:10] */ + unsigned int pab2bEccErrMask : 1; /* * [11:11] */ + unsigned int reserved : 20; /* * [31:12]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_ECC_ERRPR_MASK_U; + +/* ** + * Union name : SMLC_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmlcIndrectCtrl { + struct tagStSmlcIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smlcIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smlcIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int + smlcIndirTab : 7; /* * [27:21]It specifies memory group or table. 0:fiar;1:pab; SML:mem_index(18). + SMF:stateless and memory mode: bankid(2),mem_index(19),reserved(88). statefull mode + : bankid(2), + cid0(10),cid1(10),base_addr(56),pcie_template(6),host_id(2),base_addr_type(1),refill_len(6),refill_len_valid(1),o_bit(1),csize(2),vcache_base(10),b + size(2).2:stb;3:cdb0; 4:cdb1;5:rsv;6:rsv;7:rsv.8:req_list_info_0; SML: + thread_id(4),base_sel(1),instance(6),mem_index(18),valid_cache_data(1),valid_list(1),hol + ding(1),sa_req(1),lha_req(1),28'b0. + SMF:thread_id(5),mem_index(56),valid_cache_data(1),valid_list(1),holding(1),sa_req(1),lha_req(1).mode(1),misc(1),mem(1),bat + _type(2),bpc(1),index_type(4),index_subtype(2),vf(10),ofst(6).9:req_list_info_1;…… + SML时，只有 req_list_info_0~31有效。71:req_list_info_63;72:BAT pointer table.other value: + reserved. */ + unsigned int + smlcIndirAddr : 21; /* * [20:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.14:5 - memory indexFor FIAR: 14:13 reserved, In + SMF: 12:8 is instance id; 7:5 is entry number in instance. In SML: 12:7 is + instance id; bit6 is entry number in instance.bit5 is RSV.For pab:(o nly support for CSR + read) 14:11 reserved, 10:6 thread ID, bit10 is RSV in SML. 5:3 reserved. 1个pab + entry的109bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个109bit，后续读此1 + 09bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先读地址bit[2:0]=7。 [2:0] word + select field.0x0:0x3 - reserved 0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data [31:0] For stb,(only support for CSR read) 14:11 reserved, 10:6 thread ID, bit10 is + RSV in SML. [5:3] 16Byte data entry index in an entry; When 0x0, indi cate to read byte + enable. [2:0] word select field.0x0:0x2 - reserved 0x3: data[159:128]0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]F or cdb0,(only support for + CSR read) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. [5:3] 16Byte data entry + index in an entry; [2:0] word select f ield.0x0:0x2 - reserved0x3: data[159:128](ECC + bit of 16B)0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For + cdb1,(only support for CSR re ad) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. + [5:3] 16Byte data entry index in an entry; When 0x0, indicate to read byte enable. [2:0] + word s elect field.0x0: - reserved0x1: data[223:192] 0x2: data[191:160] 0x3: + data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For r + eq_list_info,(only support for CSR read) 14:3 reserved, 1个req_list_info + 的94bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个94bit，后续读此94bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先 + 读地址bit[2:0]=7。 [2:0] word select field.0x0:0x4 - reserved 0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0]For BAT pointer table, 14:5 vf index. + */ +#else + unsigned int + smlcIndirAddr : 21; /* * [20:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.14:5 - memory indexFor FIAR: 14:13 reserved, In + SMF: 12:8 is instance id; 7:5 is entry number in instance. In SML: 12:7 is + instance id; bit6 is entry number in instance.bit5 is RSV.For pab:(o nly support for CSR + read) 14:11 reserved, 10:6 thread ID, bit10 is RSV in SML. 5:3 reserved. 1个pab + entry的109bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个109bit，后续读此1 + 09bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先读地址bit[2:0]=7。 [2:0] word + select field.0x0:0x3 - reserved 0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data [31:0] For stb,(only support for CSR read) 14:11 reserved, 10:6 thread ID, bit10 is + RSV in SML. [5:3] 16Byte data entry index in an entry; When 0x0, indi cate to read byte + enable. [2:0] word select field.0x0:0x2 - reserved 0x3: data[159:128]0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]F or cdb0,(only support for + CSR read) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. [5:3] 16Byte data entry + index in an entry; [2:0] word select f ield.0x0:0x2 - reserved0x3: data[159:128](ECC + bit of 16B)0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For + cdb1,(only support for CSR re ad) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. + [5:3] 16Byte data entry index in an entry; When 0x0, indicate to read byte enable. [2:0] + word s elect field.0x0: - reserved0x1: data[223:192] 0x2: data[191:160] 0x3: + data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For r + eq_list_info,(only support for CSR read) 14:3 reserved, 1个req_list_info + 的94bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个94bit，后续读此94bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先 + 读地址bit[2:0]=7。 [2:0] word select field.0x0:0x4 - reserved 0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0]For BAT pointer table, 14:5 vf index. + */ + unsigned int + smlcIndirTab : 7; /* * [27:21]It specifies memory group or table. 0:fiar;1:pab; SML:mem_index(18). + SMF:stateless and memory mode: bankid(2),mem_index(19),reserved(88). statefull mode + : bankid(2), + cid0(10),cid1(10),base_addr(56),pcie_template(6),host_id(2),base_addr_type(1),refill_len(6),refill_len_valid(1),o_bit(1),csize(2),vcache_base(10),b + size(2).2:stb;3:cdb0; 4:cdb1;5:rsv;6:rsv;7:rsv.8:req_list_info_0; SML: + thread_id(4),base_sel(1),instance(6),mem_index(18),valid_cache_data(1),valid_list(1),hol + ding(1),sa_req(1),lha_req(1),28'b0. + SMF:thread_id(5),mem_index(56),valid_cache_data(1),valid_list(1),holding(1),sa_req(1),lha_req(1).mode(1),misc(1),mem(1),bat + _type(2),bpc(1),index_type(4),index_subtype(2),vf(10),ofst(6).9:req_list_info_1;…… + SML时，只有 req_list_info_0~31有效。71:req_list_info_63;72:BAT pointer table.other value: + reserved. */ + unsigned int smlcIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smlcIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smlcIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INDRECT_CTRL_U; + +/* ** + * Union name : SMLC_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmlcIndrectTimeout { + struct tagStSmlcIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smlcIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMLC_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmlcIndrectData { + struct tagStSmlcIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smlcIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INDRECT_DATA_U; + +/* ** + * Union name : SMLC_CNT0 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter0 + * Description: + */ +typedef union tagUnSmlcCnt0 { + struct tagStSmlcCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt0 : 48; /* * [47:0]Event counter 0, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt0 : 48; /* * [47:0]Event counter 0, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT0_U; + +/* ** + * Union name : SMLC_CNT1 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter1 + * Description: + */ +typedef union tagUnSmlcCnt1 { + struct tagStSmlcCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt1 : 48; /* * [47:0]Event counter 1, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt1 : 48; /* * [47:0]Event counter 1, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT1_U; + +/* ** + * Union name : SMLC_CNT2 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter2 + * Description: + */ +typedef union tagUnSmlcCnt2 { + struct tagStSmlcCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt2 : 48; /* * [47:0]Event counter 2, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt2 : 48; /* * [47:0]Event counter 2, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT2_U; + +/* ** + * Union name : SMLC_CNT3 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter3 + * Description: + */ +typedef union tagUnSmlcCnt3 { + struct tagStSmlcCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt3 : 48; /* * [47:0]Event counter 3, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt3 : 48; /* * [47:0]Event counter 3, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT3_U; + +/* ** + * Union name : SMLC_CNT_CFG0 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter configuration 0 + * Description: + */ +typedef union tagUnSmlcCntCfg0 { + struct tagStSmlcCntCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int cnt3MatchInstId : 6; /* * [31:26]Counter 3 match instance ID */ + unsigned int cnt2MatchInstId : 6; /* * [25:20]Counter 2 match instance ID */ + unsigned int cnt1MatchInstId : 6; /* * [19:14]Counter 1 match instance ID */ + unsigned int cnt0MatchInstId : 6; /* * [13:8]Counter 0 match instance ID */ + unsigned int cnt3InstMatchEnable : 1; /* * [7:7]Counter 3 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt3_match_inst_id + */ + unsigned int cnt2InstMatchEnable : 1; /* * [6:6]Counter 2 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt2_match_inst_id + */ + unsigned int cnt1InstMatchEnable : 1; /* * [5:5]Counter 1 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt1_match_inst_id + */ + unsigned int cnt0InstMatchEnable : 1; /* * [4:4]Counter 0 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt0_match_inst_id + */ + unsigned int cntEnable : 4; /* * [3:0]Event counter enable for each counter */ +#else + unsigned int cntEnable : 4; /* * [3:0]Event counter enable for each counter */ + unsigned int cnt0InstMatchEnable : 1; /* * [4:4]Counter 0 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt0_match_inst_id + */ + unsigned int cnt1InstMatchEnable : 1; /* * [5:5]Counter 1 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt1_match_inst_id + */ + unsigned int cnt2InstMatchEnable : 1; /* * [6:6]Counter 2 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt2_match_inst_id + */ + unsigned int cnt3InstMatchEnable : 1; /* * [7:7]Counter 3 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt3_match_inst_id + */ + unsigned int cnt0MatchInstId : 6; /* * [13:8]Counter 0 match instance ID */ + unsigned int cnt1MatchInstId : 6; /* * [19:14]Counter 1 match instance ID */ + unsigned int cnt2MatchInstId : 6; /* * [25:20]Counter 2 match instance ID */ + unsigned int cnt3MatchInstId : 6; /* * [31:26]Counter 3 match instance ID */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CNT_CFG0_U; + +/* ** + * Union name : SMLC_CNT_CFG1 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter configuration 1 + * Description: + */ +typedef union tagUnSmlcCntCfg1 { + struct tagStSmlcCntCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int cnt3EventSel : 4; /* * [15:12]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt2EventSel : 4; /* * [11:8]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt1EventSel : 4; /* * [7:4]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt0EventSel : 4; /* * [3:0]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ +#else + unsigned int cnt0EventSel : 4; /* * [3:0]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt1EventSel : 4; /* * [7:4]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt2EventSel : 4; /* * [11:8]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt3EventSel : 4; /* * [15:12]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CNT_CFG1_U; + +/* ** + * Union name : SMLC_CREDIT_CTP + * @brief Smart Memory Lock Cache Controller (SMLC)credit snapshot register. + * Description: + */ +typedef union tagUnSmlcCreditCtp { + struct tagStSmlcCreditCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int vcCredit : 2; /* * [6:5]bpc data credit value from Victim Cache.In SMF, the initial value is 0x1. + */ + unsigned int smmcCredit : 5; /* * [4:0]credit value from SMMC.In SMF, the initial value is 0x4. In SML, the + * initial value is 0x10. + */ +#else + unsigned int smmcCredit : 5; /* * [4:0]credit value from SMMC.In SMF, the initial value is 0x4. In SML, the + * initial value is 0x10. + */ + unsigned int vcCredit : 2; /* * [6:5]bpc data credit value from Victim Cache.In SMF, the initial value is 0x1. + */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CREDIT_CTP_U; + +/* ** + * Union name : SMLC_FIFO_DEPTH_CTP + * @brief Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register. + * Description: + */ +typedef union tagUnSmlcFifoDepthCtp { + struct tagStSmlcFifoDepthCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 22; /* * [31:10]reserved. */ + unsigned int reserved1 : 5; /* * [9:5]reserved */ + unsigned int srfFifoDepth : 5; /* * [4:0]srf fifo real depth. */ +#else + unsigned int srfFifoDepth : 5; /* * [4:0]srf fifo real depth. */ + unsigned int reserved1 : 5; /* * [9:5]reserved */ + unsigned int reserved0 : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_FIFO_DEPTH_CTP_U; + +/* ** + * Union name : SMLC_ECC_ERR_CTP + * @brief Smart Memory Lock Cache Controller (SMLC)parity error snapshot register. + * Description: + */ +typedef union tagUnSmlcEccErrCtp { + struct tagStSmlcEccErrCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int eccErrorInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur.Note: this field only capture the onformation of the last error.[31:16] + reserved.[15:13] : information type. indicate which memory has ECC error. 0:fiar; + 1:pab; 2:stb; 3:cdb0; 4:cdb1; 5:bat; other value:reserved.For fiar memory + error:[12:8] reserved.[7:0] memory index;For pab memory error:[12:5] reserved.[4:0] + memory index;For stb memory error:[12:8] reserved.[7:3] memory index;[2:0] index + number o f error occured 16byte in a entry of data memory;For cdb0 memory + error:[12:9] reserved.[8:3] memory index;[2:0] index number of error occured 16byte + in a entry of data memory;For cdb1 memory error:[12:7] memory index;[6:0] index + number of error occured byte in a entry of data memory;For bat memory error:[12:10] + reserve d.[9:0] memory index; */ +#else + unsigned int eccErrorInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur.Note: this field only capture the onformation of the last error.[31:16] + reserved.[15:13] : information type. indicate which memory has ECC error. 0:fiar; + 1:pab; 2:stb; 3:cdb0; 4:cdb1; 5:bat; other value:reserved.For fiar memory + error:[12:8] reserved.[7:0] memory index;For pab memory error:[12:5] reserved.[4:0] + memory index;For stb memory error:[12:8] reserved.[7:3] memory index;[2:0] index + number o f error occured 16byte in a entry of data memory;For cdb0 memory + error:[12:9] reserved.[8:3] memory index;[2:0] index number of error occured 16byte + in a entry of data memory;For cdb1 memory error:[12:7] memory index;[6:0] index + number of error occured byte in a entry of data memory;For bat memory error:[12:10] + reserve d.[9:0] memory index; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_ECC_ERR_CTP_U; + + +/* ** + * Union name : SMMC_F_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmmcFVersion { + struct tagStSmmcFVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smmcFVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VERSION_U; + +/* ** + * Union name : SMMC_F_MC_CFG + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCfg { + struct tagStSmmcFMcCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30] */ + unsigned int readSoRo : 2; /* * [29:28]so_ro configure for read operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering; 2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int writeSoRo : 2; /* * [27:26]so_ro configure for write operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering ;2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int memBankIdPst : 2; /* * [25:24]Bank id position in mem_index in memory mode, or stateless + mode.0:bank_id = mem_index[3:2];1:bank_id = mem_index[4:3];2:bank_id = + mem_index[5:4];3:bank_id = mem _index[6:5]; */ + unsigned int smmcQuStoreBpThd : 8; /* * [23:16]Qu store buffer backpressure threshold, in unit of 64Byte. If + * available space in qu store buffer is less than this value,qu store API + * will be blocked. + */ + unsigned int smmcQuReturnFifoBp0ffThd : 6; /* * [15:10]Qu return fifo release backpressure threshold. If used + * space in qu return fifo is less than this value, the backpressure + * will be released. + */ + unsigned int smmcQuReturnFifoBponThd : 6; /* * [9:4]Qu return fifo backpressure threshold. If used space in qu + return fifo is no less than this value, the backpressure will be set, and + qu load API will be blocked + . */ + unsigned int smmcMcEccParityEnable : 1; /* * [3:3]1'b1:enable ecc/parity check with memory read + * data;1'b0:disable ecc/parity check with memory read data; + */ + unsigned int smmcMcClaChkEnb : 1; /* * [2:2]1'b1:enable to check validation of CLA GPA.GPA[0] =1 means this GPA + * is valid, GPA[0]=0 means this GPA is invalid.1'b0:disable to check + * validation of CLA GPA. + */ + unsigned int + smmcFQuRxCtpEnb : 1; /* * [1:1]when this signal is enable, SMMC will capture first flit that received from + QU side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后从QU侧过来的第一个flit，抓住后保持不变；如果要重新抓新的fli + t，需要先把该信号拉低再拉高。 */ + unsigned int + smmcFQuTxCtpEnb : 1; /* * [0:0]when this signal is enable, SMMC will capture first flit that sent to QU + side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后SMMC发给QU的第一个flit，抓住后保持不变；如果要重新抓新的flit，需要 + 先把该信号拉低再拉高。 */ +#else + unsigned int + smmcFQuTxCtpEnb : 1; /* * [0:0]when this signal is enable, SMMC will capture first flit that sent to QU + side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后SMMC发给QU的第一个flit，抓住后保持不变；如果要重新抓新的flit，需要 + 先把该信号拉低再拉高。 */ + unsigned int + smmcFQuRxCtpEnb : 1; /* * [1:1]when this signal is enable, SMMC will capture first flit that received from + QU side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后从QU侧过来的第一个flit，抓住后保持不变；如果要重新抓新的fli + t，需要先把该信号拉低再拉高。 */ + unsigned int smmcMcClaChkEnb : 1; /* * [2:2]1'b1:enable to check validation of CLA GPA.GPA[0] =1 means this GPA + * is valid, GPA[0]=0 means this GPA is invalid.1'b0:disable to check + * validation of CLA GPA. + */ + unsigned int smmcMcEccParityEnable : 1; /* * [3:3]1'b1:enable ecc/parity check with memory read + * data;1'b0:disable ecc/parity check with memory read data; + */ + unsigned int smmcQuReturnFifoBponThd : 6; /* * [9:4]Qu return fifo backpressure threshold. If used space in qu + return fifo is no less than this value, the backpressure will be set, and + qu load API will be blocked + . */ + unsigned int smmcQuReturnFifoBp0ffThd : 6; /* * [15:10]Qu return fifo release backpressure threshold. If used + * space in qu return fifo is less than this value, the backpressure + * will be released. + */ + unsigned int smmcQuStoreBpThd : 8; /* * [23:16]Qu store buffer backpressure threshold, in unit of 64Byte. If + * available space in qu store buffer is less than this value,qu store API + * will be blocked. + */ + unsigned int memBankIdPst : 2; /* * [25:24]Bank id position in mem_index in memory mode, or stateless + mode.0:bank_id = mem_index[3:2];1:bank_id = mem_index[4:3];2:bank_id = + mem_index[5:4];3:bank_id = mem _index[6:5]; */ + unsigned int writeSoRo : 2; /* * [27:26]so_ro configure for write operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering ;2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int readSoRo : 2; /* * [29:28]so_ro configure for read operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering; 2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int reserved : 2; /* * [31:30] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CFG_U; + +/* ** + * Union name : SMMC_F_MC_CFG1 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCfg1 { + struct tagStSmmcFMcCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30] */ + unsigned int bankidSrc : 15; /* * [29:15]For cache mode, where bankid come from.0:bank id = hash + value[4:3].1:bank id = smeg1_smlc_mem_index[4:3].Each bit is corresponding to each type + configuration.Ba nkid_src[0] is corresponding to type1=p_cxt2.…Bankid_src[14] is + corresponding to type15=others(GPA). + */ + unsigned int cidSrc : 15; /* * [14:0]For cache mode, where CID0/CID1 come from.0: CID0=hash value[22:14], + CID1=hash value[13:5].1: CID0=CID1=smeg1_smlc_mem_index[13:5].Each bit is corresponding to + each type configuration.cid_src[0] is corresponding to type1=p_cxt2.…cid_src[14] is + corresponding to type15=others(GPA). + */ +#else + unsigned int cidSrc : 15; /* * [14:0]For cache mode, where CID0/CID1 come from.0: CID0=hash value[22:14], + CID1=hash value[13:5].1: CID0=CID1=smeg1_smlc_mem_index[13:5].Each bit is corresponding to + each type configuration.cid_src[0] is corresponding to type1=p_cxt2.…cid_src[14] is + corresponding to type15=others(GPA). + */ + unsigned int bankidSrc : 15; /* * [29:15]For cache mode, where bankid come from.0:bank id = hash + value[4:3].1:bank id = smeg1_smlc_mem_index[4:3].Each bit is corresponding to each type + configuration.Ba nkid_src[0] is corresponding to type1=p_cxt2.…Bankid_src[14] is + corresponding to type15=others(GPA). + */ + unsigned int reserved : 2; /* * [31:30] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CFG1_U; + +/* ** +* Union name : SMMC_HASH_SEED0 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmmcHashSeed0 { + struct tagStSmmcHashSeed0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg0 : 32; /* * [31:0] */ +#else + unsigned int hashSeedCfg0 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_HASH_SEED0_U; + +/* ** +* Union name : SMMC_HASH_SEED1 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmmcHashSeed1 { + struct tagStSmmcHashSeed1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg1 : 32; /* * [31:0] */ +#else + unsigned int hashSeedCfg1 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_HASH_SEED1_U; + +/* ** + * Union name : SMMC_F_CFG + * @brief SMMF_F configuration register . + * Description: + */ +typedef union tagUnSmmcFCfg { + struct tagStSmmcFCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved : 2; /* * [23:22]reserved */ + unsigned int smmcFBankVldId : 4; /* * [21:18]indicate which bank is + valid,1'b1:valid;1'b0:invalid.Bit[0]:correspond to bank0;Bit[1]:correspond to + bank1;Bit[2]:correspond to bank2;Bit[3]:correspond to bank3 + ; */ + unsigned int smmcFBankVldNum : 2; /* * [17:16]indicate how many banks are valid:2'b00: 4 banks are valid;2'b01: + 1 bank is valid;2'b10: 2 banks are valid;2'b11: reserved;Note: this signal only + configure how many banks are valid, which bank is valid is cofigured by + smmc_f_bank_vld_id. */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ +#else + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int smmcFBankVldNum : 2; /* * [17:16]indicate how many banks are valid:2'b00: 4 banks are valid;2'b01: + 1 bank is valid;2'b10: 2 banks are valid;2'b11: reserved;Note: this signal only + configure how many banks are valid, which bank is valid is cofigured by + smmc_f_bank_vld_id. */ + unsigned int smmcFBankVldId : 4; /* * [21:18]indicate which bank is + valid,1'b1:valid;1'b0:invalid.Bit[0]:correspond to bank0;Bit[1]:correspond to + bank1;Bit[2]:correspond to bank2;Bit[3]:correspond to bank3 + ; */ + unsigned int reserved : 2; /* * [23:22]reserved */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_CFG_U; + +/* ** + * Union name : SMMC_F_MC_INIT + * @brief SMMC_F main cache initialization + * Description: + */ +typedef union tagUnSmmcFMcInit { + struct tagStSmmcFMcInit { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 3; /* * [31:29] */ + unsigned int smmcMcInitEndAddr : 14; /* * [28:15]The end address in data memory to stop processing + initialization. */ + unsigned int smmcMcInitStartAddr : 14; /* * [14:1]The start address in data memory to begin processing + initialization. The initialization only process in the region from the start + address to the end address in four banks.Basically, only the memory mode + region in data memory needs to initializing. + */ + unsigned int smmcMcInit : 1; /* * [0:0]Write 1 to register will trigger one cycle pulse to start harware inital + * invalidate all cache line entries(include tag memory and data memory) in main + * cache. + */ +#else + unsigned int smmcMcInit : 1; /* * [0:0]Write 1 to register will trigger one cycle pulse to start harware inital + * invalidate all cache line entries(include tag memory and data memory) in main + * cache. + */ + unsigned int smmcMcInitStartAddr : 14; /* * [14:1]The start address in data memory to begin processing + initialization. The initialization only process in the region from the start + address to the end address in four banks.Basically, only the memory mode + region in data memory needs to initializing. + */ + unsigned int smmcMcInitEndAddr : 14; /* * [28:15]The end address in data memory to stop processing + initialization. */ + unsigned int reserved : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_INIT_U; + +/* ** + * Union name : SMMC_F_MC_RF_TIMEOUT_INTERVAL + * @brief + * Description: + */ +typedef union tagUnSmmcFMcRfTimeoutInterval { + struct tagStSmmcFMcRfTimeoutInterval { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcRefillTimeoutInterval : 32; /* * [31:0]the max interval for SMMC to refill data from host. if a + * refill operation interval exceed the configured interval, SMMC + * will report a timeout error to SW. + */ +#else + unsigned int mcRefillTimeoutInterval : 32; /* * [31:0]the max interval for SMMC to refill data from host. if a + * refill operation interval exceed the configured interval, SMMC + * will report a timeout error to SW. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_U; + +/* ** + * Union name : SMMC_F_INT_VECTOR + * @brief Statefull Smart Memory Memory Controller (SMMC_F) interrupt vector register + * Description: + */ +typedef union tagUnSmmcFIntVector { + struct tagStSmmcFIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INT_VECTOR_U; + +/* ** + * Union name : SMMC_F_INT + * @brief Smart Memory Memory Controller (SMMC) interrupt data register + * Description: + */ +typedef union tagUnSmmcFInt { + struct tagStSmmcFInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 9; /* * [15:7]reserved */ + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 9; /* * [15:7]reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INT_U; + +/* ** + * Union name : SMMC_F_INT_MASK + * @brief Statefull Smart Memory Memory Controller (SMMC_F) interrupt mask register. + * Description: + */ +typedef union tagUnSmmcFIntMask { + struct tagStSmmcFIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INT_MASK_U; + +/* ** + * Union name : SMMC_F_MC_CACHE_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCacheErr { + struct tagStSmmcFMcCacheErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcData32bEccMerr : 1; /* * [31:31]main cache bank3 data memory 2bit ECC multi error; */ + unsigned int mcData32bEccErr : 1; /* * [30:30]main cache bank3 data memory 2bit ECC error; */ + unsigned int mcData31bEccMerr : 1; /* * [29:29]main cache bank3 data memory 1bit ECC multi error; */ + unsigned int mcData31bEccErr : 1; /* * [28:28]main cache bank3 data memory 1bit ECC error; */ + unsigned int mcData22bEccMerr : 1; /* * [27:27]main cache bank2 data memory 2bit ECC multi error; */ + unsigned int mcData22bEccErr : 1; /* * [26:26]main cache bank2 data memory 2bit ECC error; */ + unsigned int mcData21bEccMerr : 1; /* * [25:25]main cache bank2 data memory 1bit ECC multi error; */ + unsigned int mcData21bEccErr : 1; /* * [24:24]main cache bank2 data memory 1bit ECC error; */ + unsigned int mcData12bEccMerr : 1; /* * [23:23]main cache bank1 data memory 2bit ECC multi error; */ + unsigned int mcData12bEccErr : 1; /* * [22:22]main cache bank1 data memory 2bit ECC error; */ + unsigned int mcData11bEccMerr : 1; /* * [21:21]main cache bank1 data memory 1bit ECC multi error; */ + unsigned int mcData11bEccErr : 1; /* * [20:20]main cache bank1 data memory 1bit ECC error; */ + unsigned int mcData02bEccMerr : 1; /* * [19:19]main cache bank0 data memory 2bit ECC multi error; */ + unsigned int mcData02bEccErr : 1; /* * [18:18]main cache bank0 data memory 2bit ECC error; */ + unsigned int mcData01bEccMerr : 1; /* * [17:17]main cache bank0 data memory 1bit ECC multi error; */ + unsigned int mcData01bEccErr : 1; /* * [16:16]main cache bank0 data memory 1bit ECC error; */ + unsigned int mcTag32bEccMerr : 1; /* * [15:15]main cache bank3 tag memory 2bit ECC multi error; */ + unsigned int mcTag32bEccErr : 1; /* * [14:14]main cache bank3 tag memory 2bit ECC error; */ + unsigned int mcTag31bEccMerr : 1; /* * [13:13]main cache bank3 tag memory 1bit ECC multi error; */ + unsigned int mcTag31bEccErr : 1; /* * [12:12]main cache bank3 tag memory 1bit ECC error; */ + unsigned int mcTag22bEccMerr : 1; /* * [11:11]main cache bank2 tag memory 2bit ECC multi error; */ + unsigned int mcTag22bEccErr : 1; /* * [10:10]main cache bank2 tag memory 2bit ECC error; */ + unsigned int mcTag21bEccMerr : 1; /* * [9:9]main cache bank2 tag memory 1bit ECC multi error; */ + unsigned int mcTag21bEccErr : 1; /* * [8:8]main cache bank2 tag memory 1bit ECC error; */ + unsigned int mcTag12bEccMerr : 1; /* * [7:7]main cache bank1 tag memory 2bit ECC multi error; */ + unsigned int mcTag12bEccErr : 1; /* * [6:6]main cache bank1 tag memory 2bit ECC error; */ + unsigned int mcTag11bEccMerr : 1; /* * [5:5]main cache bank1 tag memory 1bit ECC multi error; */ + unsigned int mcTag11bEccErr : 1; /* * [4:4]main cache bank1 tag memory 1bit ECC error; */ + unsigned int mcTag02bEccMerr : 1; /* * [3:3]main cache bank0 tag memory 2bit ECC multi error; */ + unsigned int mcTag02bEccErr : 1; /* * [2:2]main cache bank0 tag memory 2bit ECC error; */ + unsigned int mcTag01bEccMerr : 1; /* * [1:1]main cache bank0 tag memory 1bit ECC multi error; */ + unsigned int mcTag01bEccErr : 1; /* * [0:0]main cache bank0 tag memory 1bit ECC error; */ +#else + unsigned int mcTag01bEccErr : 1; /* * [0:0]main cache bank0 tag memory 1bit ECC error; */ + unsigned int mcTag01bEccMerr : 1; /* * [1:1]main cache bank0 tag memory 1bit ECC multi error; */ + unsigned int mcTag02bEccErr : 1; /* * [2:2]main cache bank0 tag memory 2bit ECC error; */ + unsigned int mcTag02bEccMerr : 1; /* * [3:3]main cache bank0 tag memory 2bit ECC multi error; */ + unsigned int mcTag11bEccErr : 1; /* * [4:4]main cache bank1 tag memory 1bit ECC error; */ + unsigned int mcTag11bEccMerr : 1; /* * [5:5]main cache bank1 tag memory 1bit ECC multi error; */ + unsigned int mcTag12bEccErr : 1; /* * [6:6]main cache bank1 tag memory 2bit ECC error; */ + unsigned int mcTag12bEccMerr : 1; /* * [7:7]main cache bank1 tag memory 2bit ECC multi error; */ + unsigned int mcTag21bEccErr : 1; /* * [8:8]main cache bank2 tag memory 1bit ECC error; */ + unsigned int mcTag21bEccMerr : 1; /* * [9:9]main cache bank2 tag memory 1bit ECC multi error; */ + unsigned int mcTag22bEccErr : 1; /* * [10:10]main cache bank2 tag memory 2bit ECC error; */ + unsigned int mcTag22bEccMerr : 1; /* * [11:11]main cache bank2 tag memory 2bit ECC multi error; */ + unsigned int mcTag31bEccErr : 1; /* * [12:12]main cache bank3 tag memory 1bit ECC error; */ + unsigned int mcTag31bEccMerr : 1; /* * [13:13]main cache bank3 tag memory 1bit ECC multi error; */ + unsigned int mcTag32bEccErr : 1; /* * [14:14]main cache bank3 tag memory 2bit ECC error; */ + unsigned int mcTag32bEccMerr : 1; /* * [15:15]main cache bank3 tag memory 2bit ECC multi error; */ + unsigned int mcData01bEccErr : 1; /* * [16:16]main cache bank0 data memory 1bit ECC error; */ + unsigned int mcData01bEccMerr : 1; /* * [17:17]main cache bank0 data memory 1bit ECC multi error; */ + unsigned int mcData02bEccErr : 1; /* * [18:18]main cache bank0 data memory 2bit ECC error; */ + unsigned int mcData02bEccMerr : 1; /* * [19:19]main cache bank0 data memory 2bit ECC multi error; */ + unsigned int mcData11bEccErr : 1; /* * [20:20]main cache bank1 data memory 1bit ECC error; */ + unsigned int mcData11bEccMerr : 1; /* * [21:21]main cache bank1 data memory 1bit ECC multi error; */ + unsigned int mcData12bEccErr : 1; /* * [22:22]main cache bank1 data memory 2bit ECC error; */ + unsigned int mcData12bEccMerr : 1; /* * [23:23]main cache bank1 data memory 2bit ECC multi error; */ + unsigned int mcData21bEccErr : 1; /* * [24:24]main cache bank2 data memory 1bit ECC error; */ + unsigned int mcData21bEccMerr : 1; /* * [25:25]main cache bank2 data memory 1bit ECC multi error; */ + unsigned int mcData22bEccErr : 1; /* * [26:26]main cache bank2 data memory 2bit ECC error; */ + unsigned int mcData22bEccMerr : 1; /* * [27:27]main cache bank2 data memory 2bit ECC multi error; */ + unsigned int mcData31bEccErr : 1; /* * [28:28]main cache bank3 data memory 1bit ECC error; */ + unsigned int mcData31bEccMerr : 1; /* * [29:29]main cache bank3 data memory 1bit ECC multi error; */ + unsigned int mcData32bEccErr : 1; /* * [30:30]main cache bank3 data memory 2bit ECC error; */ + unsigned int mcData32bEccMerr : 1; /* * [31:31]main cache bank3 data memory 2bit ECC multi error; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CACHE_ERR_U; + +/* ** + * Union name : SMMC_F_MC_CACHE_MASK + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCacheMask { + struct tagStSmmcFMcCacheMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int mcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int mcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int mcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int mcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int mcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int mcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int mcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int mcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int mcTag32bEccErrMask : 1; /* * [7:7] */ + unsigned int mcTag31bEccErrMask : 1; /* * [6:6] */ + unsigned int mcTag22bEccErrMask : 1; /* * [5:5] */ + unsigned int mcTag21bEccErrMask : 1; /* * [4:4] */ + unsigned int mcTag12bEccErrMask : 1; /* * [3:3] */ + unsigned int mcTag11bEccErrMask : 1; /* * [2:2] */ + unsigned int mcTag02bEccErrMask : 1; /* * [1:1] */ + unsigned int mcTag01bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int mcTag01bEccErrMask : 1; /* * [0:0] */ + unsigned int mcTag02bEccErrMask : 1; /* * [1:1] */ + unsigned int mcTag11bEccErrMask : 1; /* * [2:2] */ + unsigned int mcTag12bEccErrMask : 1; /* * [3:3] */ + unsigned int mcTag21bEccErrMask : 1; /* * [4:4] */ + unsigned int mcTag22bEccErrMask : 1; /* * [5:5] */ + unsigned int mcTag31bEccErrMask : 1; /* * [6:6] */ + unsigned int mcTag32bEccErrMask : 1; /* * [7:7] */ + unsigned int mcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int mcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int mcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int mcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int mcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int mcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int mcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int mcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CACHE_MASK_U; + +/* ** + * Union name : SMMC_F_MC_CACHE_ERR_INFO + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCacheErrInfo { + struct tagStSmmcFMcCacheErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + mcCacheErrInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur(corresponding to "SMMC_F_MC_CACHE_ERR").Note: this field only capture the onformation + of the last error.[31]: information valid flag. once there is ECC error occurs to any main + cache memory(tag memory or data memory),the bit will set valid.[30:28]: information type. + indicate which memory has ECC error. 3'b000: tag memory in bank0; 3'b001: tag memory in + bank1; 3'b010: tag memory in bank2; 3'b011: tag m emory in bank3; 3'b100: data memory in + bank0; 3'b101: data memory in bank1; 3'b110: data memory in bank2; 3'b111: data memory + in bank3;For main cache tag me mory error:[27:14] reserved.[13] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error.[12] tag memory way number in a bank(corresponding to + CID0 or CID1);[11:2] memory address;[1:0] indicate which 16Byte has ECC error;For main + cache data memory error:[27:18] reserved.[17] error type: 1'b0: 1-bit ECC err or. 1'b1: + 2-bit ECC error.[16:2] memory address;[1:0] indicate which 16Byte has ECC error; + */ +#else + unsigned int + mcCacheErrInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur(corresponding to "SMMC_F_MC_CACHE_ERR").Note: this field only capture the onformation + of the last error.[31]: information valid flag. once there is ECC error occurs to any main + cache memory(tag memory or data memory),the bit will set valid.[30:28]: information type. + indicate which memory has ECC error. 3'b000: tag memory in bank0; 3'b001: tag memory in + bank1; 3'b010: tag memory in bank2; 3'b011: tag m emory in bank3; 3'b100: data memory in + bank0; 3'b101: data memory in bank1; 3'b110: data memory in bank2; 3'b111: data memory + in bank3;For main cache tag me mory error:[27:14] reserved.[13] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error.[12] tag memory way number in a bank(corresponding to + CID0 or CID1);[11:2] memory address;[1:0] indicate which 16Byte has ECC error;For main + cache data memory error:[27:18] reserved.[17] error type: 1'b0: 1-bit ECC err or. 1'b1: + 2-bit ECC error.[16:2] memory address;[1:0] indicate which 16Byte has ECC error; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CACHE_ERR_INFO_U; + +/* ** + * Union name : SMMC_F_BUFFER_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFBufferErr { + struct tagStSmmcFBufferErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int fifoOvfMerr : 1; /* * [31:31]fifo overflow multi error in main cache or victim cache. */ + unsigned int fifoOvfErr : 1; /* * [30:30]fifo overflow error in main cache or victim cache. */ + unsigned int directwqeMerr : 1; /* * [29:29]direct WQE e0/e1 multi error. */ + unsigned int directwqeErr : 1; /* * [28:28]direct WQE e0/e1 error. */ + unsigned int vcSmxtfBuf2bEccMerr : 1; /* * [27:27]victim cache smxt interface output fifo 2bit ECC multi error. + */ + unsigned int vcSmxtfBuf2bEccErr : 1; /* * [26:26]victim cache smxt interface output fifo 2bit ECC error. */ + unsigned int vcSmxtfBuf1bEccMerr : 1; /* * [25:25]victim cache smxt interface output fifo 1bit ECC multi error. + */ + unsigned int vcSmxtfBuf1bEccErr : 1; /* * [24:24]victim cache smxt interface output fifo 1bit ECC error. */ + unsigned int mcRfbuf2bEccMerr : 1; /* * [23:23]main cache refill data buffer 2bit ECC multi error. */ + unsigned int mcRfbuf2bEccErr : 1; /* * [22:22]main cache refill data buffer 2bit ECC error. */ + unsigned int mcRfbuf1bEccMerr : 1; /* * [21:21]main cache refill data buffer 1bit ECC multi error. */ + unsigned int mcRfbuf1bEccErr : 1; /* * [20:20]main cache refill data buffer 1bit ECC error. */ + unsigned int mcQuDatafifo2bEccMerr : 1; /* * [19:19]main cache qu data fifo 2bit ECC multi error. */ + unsigned int mcQuDatafifo2bEccErr : 1; /* * [18:18]main cache qu data fifo 2bit ECC error. */ + unsigned int mcQuDatafifo1bEccMerr : 1; /* * [17:17]main cache qu data fifo 1bit ECC multi error. */ + unsigned int mcQuDatafifo1bEccErr : 1; /* * [16:16]main cache qu data fifo 1bit ECC error. */ + unsigned int mcQuLrn2bEccMerr : 1; /* * [15:15]main cache qu lrn data buffer 2bit ECC multi error. */ + unsigned int mcQuLrn2bEccErr : 1; /* * [14:14]main cache qu lrn data buffer 2bit ECC error. */ + unsigned int mcQuLrn1bEccMerr : 1; /* * [13:13]main cache qu lrn data buffer 1bit ECC multi error. */ + unsigned int mcQuLrn1bEccErr : 1; /* * [12:12]main cache qu lrn data buffer 1bit ECC error. */ + unsigned int mcQuStbuf2bEccMerr : 1; /* * [11:11]main cache qu store data buffer 2bit ECC multi error. */ + unsigned int mcQuStbuf2bEccErr : 1; /* * [10:10]main cache qu store data buffer 2bit ECC error. */ + unsigned int mcQuStbuf1bEccMerr : 1; /* * [9:9]main cache qu store data buffer 1bit ECC multi error. */ + unsigned int mcQuStbuf1bEccErr : 1; /* * [8:8]main cache qu store data buffer 1bit ECC error. */ + unsigned int mcEngStbuf2bEccMerr : 1; /* * [7:7]main cache engine store data buffer 2bit ECC multi error. */ + unsigned int mcEngStbuf2bEccErr : 1; /* * [6:6]main cache engine store data buffer 2bit ECC error. */ + unsigned int mcEngStbuf1bEccMerr : 1; /* * [5:5]main cache engine store data buffer 1bit ECC multi error. */ + unsigned int mcEngStbuf1bEccErr : 1; /* * [4:4]main cache engine store data buffer 1bit ECC error. */ + unsigned int mcQuVfa2bEccMerr : 1; /* * [3:3]main cache VFA table 2bit ECC multi error. */ + unsigned int mcQuVfa2bEccErr : 1; /* * [2:2]main cache VFA table 2bit ECC error. */ + unsigned int mcQuVfa1bEccMerr : 1; /* * [1:1]main cache VFA table 1bit ECC multi error. */ + unsigned int mcQuVfa1bEccErr : 1; /* * [0:0]main cache VFA table 1bit ECC error. */ +#else + unsigned int mcQuVfa1bEccErr : 1; /* * [0:0]main cache VFA table 1bit ECC error. */ + unsigned int mcQuVfa1bEccMerr : 1; /* * [1:1]main cache VFA table 1bit ECC multi error. */ + unsigned int mcQuVfa2bEccErr : 1; /* * [2:2]main cache VFA table 2bit ECC error. */ + unsigned int mcQuVfa2bEccMerr : 1; /* * [3:3]main cache VFA table 2bit ECC multi error. */ + unsigned int mcEngStbuf1bEccErr : 1; /* * [4:4]main cache engine store data buffer 1bit ECC error. */ + unsigned int mcEngStbuf1bEccMerr : 1; /* * [5:5]main cache engine store data buffer 1bit ECC multi error. */ + unsigned int mcEngStbuf2bEccErr : 1; /* * [6:6]main cache engine store data buffer 2bit ECC error. */ + unsigned int mcEngStbuf2bEccMerr : 1; /* * [7:7]main cache engine store data buffer 2bit ECC multi error. */ + unsigned int mcQuStbuf1bEccErr : 1; /* * [8:8]main cache qu store data buffer 1bit ECC error. */ + unsigned int mcQuStbuf1bEccMerr : 1; /* * [9:9]main cache qu store data buffer 1bit ECC multi error. */ + unsigned int mcQuStbuf2bEccErr : 1; /* * [10:10]main cache qu store data buffer 2bit ECC error. */ + unsigned int mcQuStbuf2bEccMerr : 1; /* * [11:11]main cache qu store data buffer 2bit ECC multi error. */ + unsigned int mcQuLrn1bEccErr : 1; /* * [12:12]main cache qu lrn data buffer 1bit ECC error. */ + unsigned int mcQuLrn1bEccMerr : 1; /* * [13:13]main cache qu lrn data buffer 1bit ECC multi error. */ + unsigned int mcQuLrn2bEccErr : 1; /* * [14:14]main cache qu lrn data buffer 2bit ECC error. */ + unsigned int mcQuLrn2bEccMerr : 1; /* * [15:15]main cache qu lrn data buffer 2bit ECC multi error. */ + unsigned int mcQuDatafifo1bEccErr : 1; /* * [16:16]main cache qu data fifo 1bit ECC error. */ + unsigned int mcQuDatafifo1bEccMerr : 1; /* * [17:17]main cache qu data fifo 1bit ECC multi error. */ + unsigned int mcQuDatafifo2bEccErr : 1; /* * [18:18]main cache qu data fifo 2bit ECC error. */ + unsigned int mcQuDatafifo2bEccMerr : 1; /* * [19:19]main cache qu data fifo 2bit ECC multi error. */ + unsigned int mcRfbuf1bEccErr : 1; /* * [20:20]main cache refill data buffer 1bit ECC error. */ + unsigned int mcRfbuf1bEccMerr : 1; /* * [21:21]main cache refill data buffer 1bit ECC multi error. */ + unsigned int mcRfbuf2bEccErr : 1; /* * [22:22]main cache refill data buffer 2bit ECC error. */ + unsigned int mcRfbuf2bEccMerr : 1; /* * [23:23]main cache refill data buffer 2bit ECC multi error. */ + unsigned int vcSmxtfBuf1bEccErr : 1; /* * [24:24]victim cache smxt interface output fifo 1bit ECC error. */ + unsigned int vcSmxtfBuf1bEccMerr : 1; /* * [25:25]victim cache smxt interface output fifo 1bit ECC multi error. + */ + unsigned int vcSmxtfBuf2bEccErr : 1; /* * [26:26]victim cache smxt interface output fifo 2bit ECC error. */ + unsigned int vcSmxtfBuf2bEccMerr : 1; /* * [27:27]victim cache smxt interface output fifo 2bit ECC multi error. + */ + unsigned int directwqeErr : 1; /* * [28:28]direct WQE e0/e1 error. */ + unsigned int directwqeMerr : 1; /* * [29:29]direct WQE e0/e1 multi error. */ + unsigned int fifoOvfErr : 1; /* * [30:30]fifo overflow error in main cache or victim cache. */ + unsigned int fifoOvfMerr : 1; /* * [31:31]fifo overflow multi error in main cache or victim cache. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_BUFFER_ERR_U; + +/* ** + * Union name : SMMC_F_BUFFER_MASK + * @brief + * Description: + */ +typedef union tagUnSmmcFBufferMask { + struct tagStSmmcFBufferMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int fifoOvfErrMask : 1; /* * [15:15] */ + unsigned int directwqeErrMask : 1; /* * [14:14] */ + unsigned int vcSmxtfBuf2bEccErrMask : 1; /* * [13:13] */ + unsigned int vcSmxtfBuf1bEccErrMask : 1; /* * [12:12] */ + unsigned int mcRfbuf2bEccErrMask : 1; /* * [11:11] */ + unsigned int mcRfbuf1bEccErrMask : 1; /* * [10:10] */ + unsigned int mcQuDatafifo2bEccErrMask : 1; /* * [9:9] */ + unsigned int mcQuDatafifo1bEccErrMask : 1; /* * [8:8] */ + unsigned int mcQuLrn2bEccErrMask : 1; /* * [7:7] */ + unsigned int mcQuLrn1bEccErrMask : 1; /* * [6:6] */ + unsigned int mcQuStbuf2bEccErrMask : 1; /* * [5:5] */ + unsigned int mcQuStbuf1bEccErrMask : 1; /* * [4:4] */ + unsigned int mcEngStbuf2bEccErrMask : 1; /* * [3:3] */ + unsigned int mcEngStbuf1bEccErrMask : 1; /* * [2:2] */ + unsigned int mcQuVfa2bEccErrMask : 1; /* * [1:1] */ + unsigned int mcQuVfa1bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int mcQuVfa1bEccErrMask : 1; /* * [0:0] */ + unsigned int mcQuVfa2bEccErrMask : 1; /* * [1:1] */ + unsigned int mcEngStbuf1bEccErrMask : 1; /* * [2:2] */ + unsigned int mcEngStbuf2bEccErrMask : 1; /* * [3:3] */ + unsigned int mcQuStbuf1bEccErrMask : 1; /* * [4:4] */ + unsigned int mcQuStbuf2bEccErrMask : 1; /* * [5:5] */ + unsigned int mcQuLrn1bEccErrMask : 1; /* * [6:6] */ + unsigned int mcQuLrn2bEccErrMask : 1; /* * [7:7] */ + unsigned int mcQuDatafifo1bEccErrMask : 1; /* * [8:8] */ + unsigned int mcQuDatafifo2bEccErrMask : 1; /* * [9:9] */ + unsigned int mcRfbuf1bEccErrMask : 1; /* * [10:10] */ + unsigned int mcRfbuf2bEccErrMask : 1; /* * [11:11] */ + unsigned int vcSmxtfBuf1bEccErrMask : 1; /* * [12:12] */ + unsigned int vcSmxtfBuf2bEccErrMask : 1; /* * [13:13] */ + unsigned int directwqeErrMask : 1; /* * [14:14] */ + unsigned int fifoOvfErrMask : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_BUFFER_MASK_U; + +/* ** + * Union name : SMMC_F_BUFFER_ERR_INFO + * @brief + * Description: + */ +typedef union tagUnSmmcFBufferErrInfo { + struct tagStSmmcFBufferErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + mcBufferErrInfo : 32; /* * [31:0]This field will capture the information when other buffer memory ECC error + occur(corresponding to "SMMC_F_BUFFER_ERR").Note: this field only capture the informa tion + of the last error.[31]: information valid flag. once there is ECC error occurs to any + buffer memory,this bit will set valid.[30:28]: information type. indi cate which buffer + memory has ECC error. 3'b000: VFA table; 3'b001: engine store data buffer; 3'b010: qu + store data buffer; 3'b011: qu lrn data buffer; 3'b1 00: qu data fifo; 3'b101: refill + data buffer; 3'b110: vc smxtf buffer; 3'b111: fifo overflow;For VFA table:[27:11] + reserved.[10] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[9:0] + memory address. For engine store data buffer:[27:11] reserved.[10] error type: 1'b0: + 1-bit ECC error. 1'b1: 2 -bit ECC error.[9] buffer number: 1'b0: buffer0; 1'b1: + buffer1;[8:3] memory access index (SMMC outstanding tag).[2:0] The error 16B position in + 64B. For qu store data buffer:[27:9] reserved.[8] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[7:0] memory access address.For qu lrn data buffer:[27 :7] + reserved.[6] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[5:0] memory + access address.For qu data fifo:[27:6] reserved.[5] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[4:0] memory access address.For refill data buffer:[27:9] + reserved.[8] error type: 1'b0: 1-bit ECC error . 1'b1: 2-bit ECC error.[7:0] + memory access address. For VC smxtf buffer:[27:6] reserved[5] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error + .[4:0] memory access address.For fifo overflow, indicate which fifo is overflow:[15]:qu + command bimap error;[14]:qu command csize error;[13]:qu command tag type error;[12]:victim + cache3 write back fifo overflow;[11]:victim cache2 write back fifo overflow;[10]:victim + cache1 write back fifo overflow;[9]:victim cache0 wri te back fifo overflow;[8]:bank3 rcb + refill response fifo overflow;[7]:bank2 rcb refill response fifo overflow;[6]:bank1 rcb + refill response fifo overflow;[5]:ba nk0 rcb refill response fifo overflow;[4]:smxr refill + response fifo overflow;[3]:qu store ack fifo overflow;[2]:qu lrn fifo overflow;[1]:qu data + fifo overflow;[ 0]:qu command fifo overflow; */ +#else + unsigned int + mcBufferErrInfo : 32; /* * [31:0]This field will capture the information when other buffer memory ECC error + occur(corresponding to "SMMC_F_BUFFER_ERR").Note: this field only capture the informa tion + of the last error.[31]: information valid flag. once there is ECC error occurs to any + buffer memory,this bit will set valid.[30:28]: information type. indi cate which buffer + memory has ECC error. 3'b000: VFA table; 3'b001: engine store data buffer; 3'b010: qu + store data buffer; 3'b011: qu lrn data buffer; 3'b1 00: qu data fifo; 3'b101: refill + data buffer; 3'b110: vc smxtf buffer; 3'b111: fifo overflow;For VFA table:[27:11] + reserved.[10] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[9:0] + memory address. For engine store data buffer:[27:11] reserved.[10] error type: 1'b0: + 1-bit ECC error. 1'b1: 2 -bit ECC error.[9] buffer number: 1'b0: buffer0; 1'b1: + buffer1;[8:3] memory access index (SMMC outstanding tag).[2:0] The error 16B position in + 64B. For qu store data buffer:[27:9] reserved.[8] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[7:0] memory access address.For qu lrn data buffer:[27 :7] + reserved.[6] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[5:0] memory + access address.For qu data fifo:[27:6] reserved.[5] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[4:0] memory access address.For refill data buffer:[27:9] + reserved.[8] error type: 1'b0: 1-bit ECC error . 1'b1: 2-bit ECC error.[7:0] + memory access address. For VC smxtf buffer:[27:6] reserved[5] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error + .[4:0] memory access address.For fifo overflow, indicate which fifo is overflow:[15]:qu + command bimap error;[14]:qu command csize error;[13]:qu command tag type error;[12]:victim + cache3 write back fifo overflow;[11]:victim cache2 write back fifo overflow;[10]:victim + cache1 write back fifo overflow;[9]:victim cache0 wri te back fifo overflow;[8]:bank3 rcb + refill response fifo overflow;[7]:bank2 rcb refill response fifo overflow;[6]:bank1 rcb + refill response fifo overflow;[5]:ba nk0 rcb refill response fifo overflow;[4]:smxr refill + response fifo overflow;[3]:qu store ack fifo overflow;[2]:qu lrn fifo overflow;[1]:qu data + fifo overflow;[ 0]:qu command fifo overflow; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_BUFFER_ERR_INFO_U; + +/* ** + * Union name : SMMC_F_MC_RF_RTN_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcRfRtnErr { + struct tagStSmmcFMcRfRtnErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2][31:2]:reserved;Note：the error information is captured in a proprietary + register, which could be read via indirect CSR access(via indirect memory/register group + "4'd14: qu interface capture data flit AND smf refill error captured information"). + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2][31:2]:reserved;Note：the error information is captured in a proprietary + register, which could be read via indirect CSR access(via indirect memory/register group + "4'd14: qu interface capture data flit AND smf refill error captured information"). + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_RF_RTN_ERR_U; + +/* ** + * Union name : SMMC_F_MC_RF_TIMEOUT_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcRfTimeoutErr { + struct tagStSmmcFMcRfTimeoutErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2][31:2]:reserved; */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2][31:2]:reserved; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_RF_TIMEOUT_ERR_U; + +/* ** + * Union name : SMMC_F_MC_MULTI_HIT_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcMultiHitErr { + struct tagStSmmcFMcMultiHitErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2][31:30]: reserved;[29]: multiple hit both in main cache and victim + cache;[28]: multiple hit in main cache;[27:24]: tag type;[23:22]: BANK-ID;[21:12]: + CID1;[11:2 + ]: CID0; */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2][31:30]: reserved;[29]: multiple hit both in main cache and victim + cache;[28]: multiple hit in main cache;[27:24]: tag type;[23:22]: BANK-ID;[21:12]: + CID1;[11:2 + ]: CID0; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_MULTI_HIT_ERR_U; + +/* ** + * Union name : SMMC_F_VC_CACHE_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFVcCacheErr { + struct tagStSmmcFVcCacheErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int vcData32bEccMerr : 1; /* * [31:31]victim cache bank3 data memory 2bit ECC multi error; */ + unsigned int vcData32bEccErr : 1; /* * [30:30]victim cache bank3 data memory 2bit ECC error; */ + unsigned int vcData31bEccMerr : 1; /* * [29:29]victim cache bank3 data memory 1bit ECC multi error; */ + unsigned int vcData31bEccErr : 1; /* * [28:28]victim cache bank3 data memory 1bit ECC error; */ + unsigned int vcData22bEccMerr : 1; /* * [27:27]victim cache bank2 data memory 2bit ECC multi error; */ + unsigned int vcData22bEccErr : 1; /* * [26:26]victim cache bank2 data memory 2bit ECC error; */ + unsigned int vcData21bEccMerr : 1; /* * [25:25]victim cache bank2 data memory 1bit ECC multi error; */ + unsigned int vcData21bEccErr : 1; /* * [24:24]victim cache bank2 data memory 1bit ECC error; */ + unsigned int vcData12bEccMerr : 1; /* * [23:23]victim cache bank1 data memory 2bit ECC multi error; */ + unsigned int vcData12bEccErr : 1; /* * [22:22]victim cache bank1 data memory 2bit ECC error; */ + unsigned int vcData11bEccMerr : 1; /* * [21:21]victim cache bank1 data memory 1bit ECC multi error; */ + unsigned int vcData11bEccErr : 1; /* * [20:20]victim cache bank1 data memory 1bit ECC error; */ + unsigned int vcData02bEccMerr : 1; /* * [19:19]victim cache bank0 data memory 2bit ECC multi error; */ + unsigned int vcData02bEccErr : 1; /* * [18:18]victim cache bank0 data memory 2bit ECC error; */ + unsigned int vcData01bEccMerr : 1; /* * [17:17]victim cache bank0 data memory 1bit ECC multi error; */ + unsigned int vcData01bEccErr : 1; /* * [16:16]victim cache bank0 data memory 1bit ECC error; */ + unsigned int vcWb32bEccMerr : 1; /* * [15:15]victim cache bank3 write back memory 2bit ECC multi error; */ + unsigned int vcWb32bEccErr : 1; /* * [14:14]victim cache bank3 write back memory 2bit ECC error; */ + unsigned int vcWb31bEccMerr : 1; /* * [13:13]victim cache bank3 write back memory 1bit ECC multi error; */ + unsigned int vcWb31bEccErr : 1; /* * [12:12]victim cache bank3 write back memory 1bit ECC error; */ + unsigned int vcWb22bEccMerr : 1; /* * [11:11]victim cache bank2 write back memory 2bit ECC multi error; */ + unsigned int vcWb22bEccErr : 1; /* * [10:10]victim cache bank2 write back memory 2bit ECC error; */ + unsigned int vcWb21bEccMerr : 1; /* * [9:9]victim cache bank2 write back memory 1bit ECC multi error; */ + unsigned int vcWb21bEccErr : 1; /* * [8:8]victim cache bank2 write back memory 1bit ECC error; */ + unsigned int vcWb12bEccMerr : 1; /* * [7:7]victim cache bank1 write back memory 2bit ECC multi error; */ + unsigned int vcWb12bEccErr : 1; /* * [6:6]victim cache bank1 write back memory 2bit ECC error; */ + unsigned int vcWb11bEccMerr : 1; /* * [5:5]victim cache bank1 write back memory 1bit ECC multi error; */ + unsigned int vcWb11bEccErr : 1; /* * [4:4]victim cache bank1 write back memory 1bit ECC error; */ + unsigned int vcWb02bEccMerr : 1; /* * [3:3]victim cache bank0 write back memory 2bit ECC multi error; */ + unsigned int vcWb02bEccErr : 1; /* * [2:2]victim cache bank0 write back memory 2bit ECC error; */ + unsigned int vcWb01bEccMerr : 1; /* * [1:1]victim cache bank0 write back memory 1bit ECC multi error; */ + unsigned int vcWb01bEccErr : 1; /* * [0:0]victim cache bank0 write back memory 1bit ECC error; */ +#else + unsigned int vcWb01bEccErr : 1; /* * [0:0]victim cache bank0 write back memory 1bit ECC error; */ + unsigned int vcWb01bEccMerr : 1; /* * [1:1]victim cache bank0 write back memory 1bit ECC multi error; */ + unsigned int vcWb02bEccErr : 1; /* * [2:2]victim cache bank0 write back memory 2bit ECC error; */ + unsigned int vcWb02bEccMerr : 1; /* * [3:3]victim cache bank0 write back memory 2bit ECC multi error; */ + unsigned int vcWb11bEccErr : 1; /* * [4:4]victim cache bank1 write back memory 1bit ECC error; */ + unsigned int vcWb11bEccMerr : 1; /* * [5:5]victim cache bank1 write back memory 1bit ECC multi error; */ + unsigned int vcWb12bEccErr : 1; /* * [6:6]victim cache bank1 write back memory 2bit ECC error; */ + unsigned int vcWb12bEccMerr : 1; /* * [7:7]victim cache bank1 write back memory 2bit ECC multi error; */ + unsigned int vcWb21bEccErr : 1; /* * [8:8]victim cache bank2 write back memory 1bit ECC error; */ + unsigned int vcWb21bEccMerr : 1; /* * [9:9]victim cache bank2 write back memory 1bit ECC multi error; */ + unsigned int vcWb22bEccErr : 1; /* * [10:10]victim cache bank2 write back memory 2bit ECC error; */ + unsigned int vcWb22bEccMerr : 1; /* * [11:11]victim cache bank2 write back memory 2bit ECC multi error; */ + unsigned int vcWb31bEccErr : 1; /* * [12:12]victim cache bank3 write back memory 1bit ECC error; */ + unsigned int vcWb31bEccMerr : 1; /* * [13:13]victim cache bank3 write back memory 1bit ECC multi error; */ + unsigned int vcWb32bEccErr : 1; /* * [14:14]victim cache bank3 write back memory 2bit ECC error; */ + unsigned int vcWb32bEccMerr : 1; /* * [15:15]victim cache bank3 write back memory 2bit ECC multi error; */ + unsigned int vcData01bEccErr : 1; /* * [16:16]victim cache bank0 data memory 1bit ECC error; */ + unsigned int vcData01bEccMerr : 1; /* * [17:17]victim cache bank0 data memory 1bit ECC multi error; */ + unsigned int vcData02bEccErr : 1; /* * [18:18]victim cache bank0 data memory 2bit ECC error; */ + unsigned int vcData02bEccMerr : 1; /* * [19:19]victim cache bank0 data memory 2bit ECC multi error; */ + unsigned int vcData11bEccErr : 1; /* * [20:20]victim cache bank1 data memory 1bit ECC error; */ + unsigned int vcData11bEccMerr : 1; /* * [21:21]victim cache bank1 data memory 1bit ECC multi error; */ + unsigned int vcData12bEccErr : 1; /* * [22:22]victim cache bank1 data memory 2bit ECC error; */ + unsigned int vcData12bEccMerr : 1; /* * [23:23]victim cache bank1 data memory 2bit ECC multi error; */ + unsigned int vcData21bEccErr : 1; /* * [24:24]victim cache bank2 data memory 1bit ECC error; */ + unsigned int vcData21bEccMerr : 1; /* * [25:25]victim cache bank2 data memory 1bit ECC multi error; */ + unsigned int vcData22bEccErr : 1; /* * [26:26]victim cache bank2 data memory 2bit ECC error; */ + unsigned int vcData22bEccMerr : 1; /* * [27:27]victim cache bank2 data memory 2bit ECC multi error; */ + unsigned int vcData31bEccErr : 1; /* * [28:28]victim cache bank3 data memory 1bit ECC error; */ + unsigned int vcData31bEccMerr : 1; /* * [29:29]victim cache bank3 data memory 1bit ECC multi error; */ + unsigned int vcData32bEccErr : 1; /* * [30:30]victim cache bank3 data memory 2bit ECC error; */ + unsigned int vcData32bEccMerr : 1; /* * [31:31]victim cache bank3 data memory 2bit ECC multi error; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_CACHE_ERR_U; + +/* ** + * Union name : SMMC_F_VC_CACHE_MASK + * @brief + * Description: + */ +typedef union tagUnSmmcFVcCacheMask { + struct tagStSmmcFVcCacheMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int vcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int vcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int vcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int vcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int vcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int vcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int vcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int vcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int vcWb32bEccErrMask : 1; /* * [7:7] */ + unsigned int vcWb31bEccErrMask : 1; /* * [6:6] */ + unsigned int vcWb22bEccErrMask : 1; /* * [5:5] */ + unsigned int vcWb21bEccErrMask : 1; /* * [4:4] */ + unsigned int vcWb12bEccErrMask : 1; /* * [3:3] */ + unsigned int vcWb11bEccErrMask : 1; /* * [2:2] */ + unsigned int vcWb02bEccErrMask : 1; /* * [1:1] */ + unsigned int vcWb01bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int vcWb01bEccErrMask : 1; /* * [0:0] */ + unsigned int vcWb02bEccErrMask : 1; /* * [1:1] */ + unsigned int vcWb11bEccErrMask : 1; /* * [2:2] */ + unsigned int vcWb12bEccErrMask : 1; /* * [3:3] */ + unsigned int vcWb21bEccErrMask : 1; /* * [4:4] */ + unsigned int vcWb22bEccErrMask : 1; /* * [5:5] */ + unsigned int vcWb31bEccErrMask : 1; /* * [6:6] */ + unsigned int vcWb32bEccErrMask : 1; /* * [7:7] */ + unsigned int vcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int vcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int vcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int vcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int vcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int vcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int vcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int vcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_CACHE_MASK_U; + +/* ** + * Union name : SMMC_F_VC_CACHE_ERR_INFO + * @brief + * Description: + */ +typedef union tagUnSmmcFVcCacheErrInfo { + struct tagStSmmcFVcCacheErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int vcCacheErrInfo : 32; /* * [31:0][31:14]:reserved.If write back memory and data memory ECC error at + the same time, here capture write back memory.If multi bank memory ECC error, here + capture th e lowest bank.[13:12]: bank id. 2'b00: bank 0, 2'b01: bank 1, 2'b10: + bank 2, 2'b11: bank 3. [11]: information type. indicate which buffer memory has + ECC err or. 1'b0: write back memory; 1'b1: vc data memory; For victim cache wb + memory error:[10:8] reserved.[7] error type: 1'b0: 1-bit ECC error. 1'b1: + 2-bit ECC error.[6:2] memory access index;[1:0] The error 16B position in 64B. For + victim cache data memory error:[10] error type: 1'b0: 1-bit ECC error. 1' + b1: 2-bit ECC error.[9:2] memory access index;[1:0] The error 16B position in 64B. + */ +#else + unsigned int vcCacheErrInfo : 32; /* * [31:0][31:14]:reserved.If write back memory and data memory ECC error at + the same time, here capture write back memory.If multi bank memory ECC error, here + capture th e lowest bank.[13:12]: bank id. 2'b00: bank 0, 2'b01: bank 1, 2'b10: + bank 2, 2'b11: bank 3. [11]: information type. indicate which buffer memory has + ECC err or. 1'b0: write back memory; 1'b1: vc data memory; For victim cache wb + memory error:[10:8] reserved.[7] error type: 1'b0: 1-bit ECC error. 1'b1: + 2-bit ECC error.[6:2] memory access index;[1:0] The error 16B position in 64B. For + victim cache data memory error:[10] error type: 1'b0: 1-bit ECC error. 1' + b1: 2-bit ECC error.[9:2] memory access index;[1:0] The error 16B position in 64B. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_CACHE_ERR_INFO_U; + +/* ** + * Union name : SMMC_F_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmmcFIndrectCtrl { + struct tagStSmmcFIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smmcFIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcFIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int + smmcFIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'd0: main cache tag memory;data + structure:{ecc_bit(9bit),occupy(1bit),valid_bit(8bit),dirty_bit(4bit),stick_bit(1bit),host_ + id(2bit),vf_id(10bit),gpa (56bit),o_bit(1bit),csize(2bit),tag_type(4bit),xid(40bit)}4'd1: + main cache data cache memory;4'd2: main cache VFA table;data structure + :{ecc_bit(7bit),pf_id(4bit),ft_enb(1bit),ft_pf_enb(1bit),rdma_enb(1bit),rdma_pf_enb(1bit),bat_ptr(18bit)}4'd3: + main cache recycle buffer;recycle buffer data str + ucture:{valid(1bit),head(1bit),tail(1bit),nxt_ptr(6),ready(1bit),early_retire(1bit),rf_done(1bit),cout_done(1bit),cla_bpc_flag(1bit),cla_entry_size(2bit),cla_xy + z(15bit),gpa_trans_flag(1bit),gpa_trans_lev(2bit),action_type(4),gpa_entry_idx(3),offset(6),tag_type(4bit),mem_idx_type(2bit),mem_idx(56bit),bank_id(2bit),cid0( + 10bit),cid1(10bit),acc_size(5bit),error_flag(1bit),cache_line_size(2bit),base_cache_line_size(2bit),original_offset(6bit),api_src(3bit),opcode(4bit),api_token(3 + 8bit),cache_base_addr(10bit),qu_st_ack(1bit)}4'd4: main cache miss cam;miss cam data + structure: {occp_cid_idx(1bit),occp_way_idx(4bit),evt_way_idx(4bit),mem_idx + _type(2bit),mem_idx(56bit),offset(6bit),tag_type(4bit),original_tag_type(4bit),host_id(2bit),vf_id(10bit),xid(40bit),original_bank_id(2bit),original_cid0(10bit) + ,original_cid1(10bit),cla_lev(2bit),tail(1bit)};4'd5: main cache engine store data + buffer;4'd6: main cache QU store data buffer;4'd7: main cache QU store data b uffer free + list; data structure:{tag_head_address, tag_tail_address,tag_used_addr_num}.4'd8: main cache + refill data buffer; data structure:{control information( 3bit),refill data(128)}.4'd9: + victim cache request information;data + structure:{req_vld(1),req_otstag(6),pcie_template(6),req_type(3),req_size(6),host_id(2),vf_i + d(10),gpa_ofst(64),lcid(2),rsv(2)}4'd10: victim cache tag memory;data + structure:{tag_vld(1),dirty(4),host_id(2),vf_id(10),gpa(56),xid(40),type(4),csize(2)}4'd11 + : victim cache data cache memory;4'd12: RTT latency counter;4'd13: virtual cache + configuration entries;4'd14: qu interface capture data flit AND smf refill erro r captured + information;refill error captured information data structure(83 bits in + total):{api_src(3),vf_id(10),api_opcode(4),api_tag_type(4),api_tag_sub_type(2 + bit，如果是qu的请求，不需要看sub_type),gpa_translation_flag(1), + gpa_translation_lev(2),api_mem_index(56),captured_info_valid(1)};4'd15:direct wqe service + type mapping table AND refill timeout otstanding tag index.data structure:1)the mapping + table are total 64bits. each 2bit are a group, bit[1:0] is corresponding to service type 0 + ,......bit[63:62] is corresponding to service type 31.bit[n+1 : n] = 2'b00, the service type + is L2NIC.bit[n+1 : n] = 2'b01, the service type is ROCE.bit[n+1 : n ] = 2'b10, the service + type is IWARP.2)refill timeout otstanding tag index:64bit, one bit corresponding to an + outstanding tag(bit0 corresponding to tag0; bit63 corresponding to tag63). when a tag is + timeout, the corresponding tag will be set, to inform SW which tag has encountered refill + timeout. The timeout tag will b e hanged up until the refill response return from host. */ + unsigned int + smmcFIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote + 0;以下软件间接访问的数据entry有些是大于32bit。软件写这些数据entry的时候需要发多次写操作，拼成一个完整的entry，然后由硬件一次写入memory中。硬件默认由entry的LSB开始写起（对应地址[2:0]=7）。软件读大于32b + it的entry时，对于一些较重要的控制信息在软件读地址[2:0]=7时，硬件锁存整个entry，后续读该entry时，从锁存寄存器中取。所以，综上所述，要求软件读/写以下数据时，地址[2:0]应该统一从7开始，由高到低依次操作。以下列出的memory的数据格式包含了ECC + bit，对于ECC bit，只可通过CSR间 接读；不可通过CSR间接写。It specifies memory address in one + group or internal address of the table.[20:3] memory access index field0) for main cache + tag memory[17:16] bank -ID[15] CID0/CID1 index type:1'b0:CID0;1'b1:CID1;[14:5] TAG memory + access index. In SMF mode,[14:5] is tag group (include 4 tags) index in a memory + way.[4 :3] tag num in a tag group0x0:0x2 - reserved 0x3: + data[159:128]([159:138]:reserved,[137:129]:ECC bit;[128]:tag data)0x4: data[127:96]0x5: + data[95:64]0x6: d ata[63:32]0x7: data[31:0] 1) for main cache data cache memory:[21:20] + bank-ID[19] data memory coreesponding to CID0/CID1:1'b0:corresponding to CID0;1'b1:corres + ponding to CID1;[18:7] memory access index. In SMF mode,[18:7] is 256Byte basic cache + line.[6:3] 16Byte data entry.0x0:0x2 - reserved 0x3: data[159:128] + ([159:137]:reserved,[136:128]:ECC bit)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 2) for main cache VFA table memory[12:3] memory index [2:0] + word select field0x0:0x6 - reserved 0x7: data[31:0] ([31:26]:ECC bit;[25:0]:vfa data)3) + for main cache recycle buffer(only support for CSR read)[8:3] me mory access index.In SMF + mode, it's corresponding to 64 outstandings;[2:0] word select field0x0: reserved 0x1: + data[223:192]0x2: data[191:160]0x3: data[159 :128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 4) for main cache miss cam(only support for CSR read)[8:3] + memory access index.In SMF mode, it's corresponding to 64 outstandings;[2:0] word select + field0x0:0x2 - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x 7: data[31:0] 5) for main cache engine store data buffer(only support for + CSR read)[12] memory id: 0:stb0; 1:stb1;[11:6] memory access index.In SMF mod e, + it's in the unit of 64Byte, and corresponding to 64 outstandings;[5:3] 16Byte data entry + index in a 64Byte store data; When 0x4, indicate to access 1bit dir ty and 64bit byte + enable.[2:0] word select field0x0:0x2 - reserved0x3: data[159:128] 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 6) f or main cache QU store data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4: 3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]([159:137]:reserved,[136:128]:ECC + bit)0x4: data[127: 96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]7) for mainc cache + QU store data buffer list(only support for CSR read)[8:3] memory access index.[2:0] wor d + select field0x0:0x6 - reserved 0x7: data[31:0] 8) for main cache refill data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4:3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]( [159:140]:reserved,[139:131]:ECC + bit,[130:129]:refill buffer entry control data)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 9) victim c ache request information (only support for CSR + read)[4:3] victim cache bank ID;[2:0] word select field0x0:0x3 - reserved 0x4: + data[127:96]0x5: data[95:64]0x6 : data[63:32]0x7: data[31:0] 10) victim cache tag + memory(only support for CSR read,and CSR write + clear.注意CSR写清时，要没有writeback流量，否则可能造成错误。例如1KB的cacheline占4个256B + ，当逻辑写了2个256B时，CSR发起清操作，前面2个256B会被清掉，但后面2个256B不清。)[10:9] + victim cache bank ID.[8:3] memory access index.In SMF mode, there are 32 tags in each + victim cache.[2:0] word select field0x0:0x3 - reserved 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 11) victim cache data cache memory(only + support for C SR read)[14:13] victim cache bank ID.[12:7] the memory access index. In SMF + mode, the victim cache is 256Byte in width.[6:3] the index number of eache 16Byte in + 256Byte of cache line.[2:0] word select field0x0:0x2 - reserved 0x3: data[159:128] 0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] 12) R TT latency + counter(only support for CSR read)[3] select which counter to read:1'b1: longest letency + counter. 1'b0: shortest letency counter. [2:0] word select field0x0~5: reserved.0x6: + counter[47:32].0x7: counter[31:0].13) virtual cache configuration entries[5:3] virtual + cache configuration entry number:3'd0: QU virtu al configure entry 0(RDMA parent + context).3'd1: QU virtual configure entry 1(flow based parent context).3'd2: QU virtual + configure entry 2(child context).3'd3: Direct WQE virtual configure entry 0(L2 NIC direct + WQE).3'd4: Direct WQE virtual configure entry 1(ROCE direct WQE).3'd5: Direct WQE virtual + configure entry 2(I WARP direct WQE).3'd6: CLA virtual configure entry.3'd7: MBaseAddr + configure [2:0] word select field0x0~6: reserved.0x7: entry data[31:0].14) qu interface + capt ure data flit[4:3]: qu interface capture data entry number 2'b00: first captured + data flit sent from QU to SMMC_F; 2'b01: first captured data flit sent from SMMC_F to + QU; 2'b10: refill error captured information;[2:0] word select field(Note:for refill + error captured information, word select field ONLY use 0x5~0x7,0x0~0x4 is reserved)0x0:0x2 + - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data[31:0] 15) service type mapping table AND refill timeout outstanding tag index.[3]: + register entry select field1'b0: service type mapping table;1'b1: refill timeout + outstanding tag index (only support for CSR read).[2:0] word select field0x0:0x5 - + reserved 0x6: data[63:32]0x7: data[31:0] + */ +#else + unsigned int + smmcFIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote + 0;以下软件间接访问的数据entry有些是大于32bit。软件写这些数据entry的时候需要发多次写操作，拼成一个完整的entry，然后由硬件一次写入memory中。硬件默认由entry的LSB开始写起（对应地址[2:0]=7）。软件读大于32b + it的entry时，对于一些较重要的控制信息在软件读地址[2:0]=7时，硬件锁存整个entry，后续读该entry时，从锁存寄存器中取。所以，综上所述，要求软件读/写以下数据时，地址[2:0]应该统一从7开始，由高到低依次操作。以下列出的memory的数据格式包含了ECC + bit，对于ECC bit，只可通过CSR间 接读；不可通过CSR间接写。It specifies memory address in one + group or internal address of the table.[20:3] memory access index field0) for main cache + tag memory[17:16] bank -ID[15] CID0/CID1 index type:1'b0:CID0;1'b1:CID1;[14:5] TAG memory + access index. In SMF mode,[14:5] is tag group (include 4 tags) index in a memory + way.[4 :3] tag num in a tag group0x0:0x2 - reserved 0x3: + data[159:128]([159:138]:reserved,[137:129]:ECC bit;[128]:tag data)0x4: data[127:96]0x5: + data[95:64]0x6: d ata[63:32]0x7: data[31:0] 1) for main cache data cache memory:[21:20] + bank-ID[19] data memory coreesponding to CID0/CID1:1'b0:corresponding to CID0;1'b1:corres + ponding to CID1;[18:7] memory access index. In SMF mode,[18:7] is 256Byte basic cache + line.[6:3] 16Byte data entry.0x0:0x2 - reserved 0x3: data[159:128] + ([159:137]:reserved,[136:128]:ECC bit)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 2) for main cache VFA table memory[12:3] memory index [2:0] + word select field0x0:0x6 - reserved 0x7: data[31:0] ([31:26]:ECC bit;[25:0]:vfa data)3) + for main cache recycle buffer(only support for CSR read)[8:3] me mory access index.In SMF + mode, it's corresponding to 64 outstandings;[2:0] word select field0x0: reserved 0x1: + data[223:192]0x2: data[191:160]0x3: data[159 :128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 4) for main cache miss cam(only support for CSR read)[8:3] + memory access index.In SMF mode, it's corresponding to 64 outstandings;[2:0] word select + field0x0:0x2 - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x 7: data[31:0] 5) for main cache engine store data buffer(only support for + CSR read)[12] memory id: 0:stb0; 1:stb1;[11:6] memory access index.In SMF mod e, + it's in the unit of 64Byte, and corresponding to 64 outstandings;[5:3] 16Byte data entry + index in a 64Byte store data; When 0x4, indicate to access 1bit dir ty and 64bit byte + enable.[2:0] word select field0x0:0x2 - reserved0x3: data[159:128] 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 6) f or main cache QU store data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4: 3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]([159:137]:reserved,[136:128]:ECC + bit)0x4: data[127: 96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]7) for mainc cache + QU store data buffer list(only support for CSR read)[8:3] memory access index.[2:0] wor d + select field0x0:0x6 - reserved 0x7: data[31:0] 8) for main cache refill data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4:3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]( [159:140]:reserved,[139:131]:ECC + bit,[130:129]:refill buffer entry control data)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 9) victim c ache request information (only support for CSR + read)[4:3] victim cache bank ID;[2:0] word select field0x0:0x3 - reserved 0x4: + data[127:96]0x5: data[95:64]0x6 : data[63:32]0x7: data[31:0] 10) victim cache tag + memory(only support for CSR read,and CSR write + clear.注意CSR写清时，要没有writeback流量，否则可能造成错误。例如1KB的cacheline占4个256B + ，当逻辑写了2个256B时，CSR发起清操作，前面2个256B会被清掉，但后面2个256B不清。)[10:9] + victim cache bank ID.[8:3] memory access index.In SMF mode, there are 32 tags in each + victim cache.[2:0] word select field0x0:0x3 - reserved 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 11) victim cache data cache memory(only + support for C SR read)[14:13] victim cache bank ID.[12:7] the memory access index. In SMF + mode, the victim cache is 256Byte in width.[6:3] the index number of eache 16Byte in + 256Byte of cache line.[2:0] word select field0x0:0x2 - reserved 0x3: data[159:128] 0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] 12) R TT latency + counter(only support for CSR read)[3] select which counter to read:1'b1: longest letency + counter. 1'b0: shortest letency counter. [2:0] word select field0x0~5: reserved.0x6: + counter[47:32].0x7: counter[31:0].13) virtual cache configuration entries[5:3] virtual + cache configuration entry number:3'd0: QU virtu al configure entry 0(RDMA parent + context).3'd1: QU virtual configure entry 1(flow based parent context).3'd2: QU virtual + configure entry 2(child context).3'd3: Direct WQE virtual configure entry 0(L2 NIC direct + WQE).3'd4: Direct WQE virtual configure entry 1(ROCE direct WQE).3'd5: Direct WQE virtual + configure entry 2(I WARP direct WQE).3'd6: CLA virtual configure entry.3'd7: MBaseAddr + configure [2:0] word select field0x0~6: reserved.0x7: entry data[31:0].14) qu interface + capt ure data flit[4:3]: qu interface capture data entry number 2'b00: first captured + data flit sent from QU to SMMC_F; 2'b01: first captured data flit sent from SMMC_F to + QU; 2'b10: refill error captured information;[2:0] word select field(Note:for refill + error captured information, word select field ONLY use 0x5~0x7,0x0~0x4 is reserved)0x0:0x2 + - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data[31:0] 15) service type mapping table AND refill timeout outstanding tag index.[3]: + register entry select field1'b0: service type mapping table;1'b1: refill timeout + outstanding tag index (only support for CSR read).[2:0] word select field0x0:0x5 - + reserved 0x6: data[63:32]0x7: data[31:0] + */ + unsigned int + smmcFIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'd0: main cache tag memory;data + structure:{ecc_bit(9bit),occupy(1bit),valid_bit(8bit),dirty_bit(4bit),stick_bit(1bit),host_ + id(2bit),vf_id(10bit),gpa (56bit),o_bit(1bit),csize(2bit),tag_type(4bit),xid(40bit)}4'd1: + main cache data cache memory;4'd2: main cache VFA table;data structure + :{ecc_bit(7bit),pf_id(4bit),ft_enb(1bit),ft_pf_enb(1bit),rdma_enb(1bit),rdma_pf_enb(1bit),bat_ptr(18bit)}4'd3: + main cache recycle buffer;recycle buffer data str + ucture:{valid(1bit),head(1bit),tail(1bit),nxt_ptr(6),ready(1bit),early_retire(1bit),rf_done(1bit),cout_done(1bit),cla_bpc_flag(1bit),cla_entry_size(2bit),cla_xy + z(15bit),gpa_trans_flag(1bit),gpa_trans_lev(2bit),action_type(4),gpa_entry_idx(3),offset(6),tag_type(4bit),mem_idx_type(2bit),mem_idx(56bit),bank_id(2bit),cid0( + 10bit),cid1(10bit),acc_size(5bit),error_flag(1bit),cache_line_size(2bit),base_cache_line_size(2bit),original_offset(6bit),api_src(3bit),opcode(4bit),api_token(3 + 8bit),cache_base_addr(10bit),qu_st_ack(1bit)}4'd4: main cache miss cam;miss cam data + structure: {occp_cid_idx(1bit),occp_way_idx(4bit),evt_way_idx(4bit),mem_idx + _type(2bit),mem_idx(56bit),offset(6bit),tag_type(4bit),original_tag_type(4bit),host_id(2bit),vf_id(10bit),xid(40bit),original_bank_id(2bit),original_cid0(10bit) + ,original_cid1(10bit),cla_lev(2bit),tail(1bit)};4'd5: main cache engine store data + buffer;4'd6: main cache QU store data buffer;4'd7: main cache QU store data b uffer free + list; data structure:{tag_head_address, tag_tail_address,tag_used_addr_num}.4'd8: main cache + refill data buffer; data structure:{control information( 3bit),refill data(128)}.4'd9: + victim cache request information;data + structure:{req_vld(1),req_otstag(6),pcie_template(6),req_type(3),req_size(6),host_id(2),vf_i + d(10),gpa_ofst(64),lcid(2),rsv(2)}4'd10: victim cache tag memory;data + structure:{tag_vld(1),dirty(4),host_id(2),vf_id(10),gpa(56),xid(40),type(4),csize(2)}4'd11 + : victim cache data cache memory;4'd12: RTT latency counter;4'd13: virtual cache + configuration entries;4'd14: qu interface capture data flit AND smf refill erro r captured + information;refill error captured information data structure(83 bits in + total):{api_src(3),vf_id(10),api_opcode(4),api_tag_type(4),api_tag_sub_type(2 + bit，如果是qu的请求，不需要看sub_type),gpa_translation_flag(1), + gpa_translation_lev(2),api_mem_index(56),captured_info_valid(1)};4'd15:direct wqe service + type mapping table AND refill timeout otstanding tag index.data structure:1)the mapping + table are total 64bits. each 2bit are a group, bit[1:0] is corresponding to service type 0 + ,......bit[63:62] is corresponding to service type 31.bit[n+1 : n] = 2'b00, the service type + is L2NIC.bit[n+1 : n] = 2'b01, the service type is ROCE.bit[n+1 : n ] = 2'b10, the service + type is IWARP.2)refill timeout otstanding tag index:64bit, one bit corresponding to an + outstanding tag(bit0 corresponding to tag0; bit63 corresponding to tag63). when a tag is + timeout, the corresponding tag will be set, to inform SW which tag has encountered refill + timeout. The timeout tag will b e hanged up until the refill response return from host. */ + unsigned int smmcFIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smmcFIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcFIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INDRECT_CTRL_U; + +/* ** + * Union name : SMMC_F_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmmcFIndrectTimeout { + struct tagStSmmcFIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smmcFIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMMC_F_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmmcFIndrectData { + struct tagStSmmcFIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INDRECT_DATA_U; + +/* ** + * Union name : SMMC_F_MC_CNT_ENB + * @brief counter enable + * Description: + */ +typedef union tagUnSmmcFMcCntEnb { + struct tagStSmmcFMcCntEnb { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 24; /* * [31:8]reserved. */ + unsigned int smmcFMcCntEnb : 8; /* * [7:0]SMMC main cache counter enable.1'b0: disable SMMC counter.1'b1: enable + * SMMC counter. + */ +#else + unsigned int smmcFMcCntEnb : 8; /* * [7:0]SMMC main cache counter enable.1'b0: disable SMMC counter.1'b1: enable + * SMMC counter. + */ + unsigned int reserved : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_ENB_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0 + * @brief counter event selection enable + * Description: + */ +typedef union tagUnSmmcFMcCntEventSelEnbGrp0 { + struct tagStSmmcFMcCntEventSelEnbGrp0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFMcCntEventSelEnb3 : 8; /* * [31:24]SMMC counter3 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb2 : 8; /* * [23:16]SMMC counter2 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb1 : 8; /* * [15:8]SMMC counter1 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb0 : 8; /* * [7:0]SMMC counter0 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#else + unsigned int smmcFMcCntEventSelEnb0 : 8; /* * [7:0]SMMC counter0 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb1 : 8; /* * [15:8]SMMC counter1 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb2 : 8; /* * [23:16]SMMC counter2 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb3 : 8; /* * [31:24]SMMC counter3 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1 + * @brief counter event selection enable + * Description: + */ +typedef union tagUnSmmcFMcCntEventSelEnbGrp1 { + struct tagStSmmcFMcCntEventSelEnbGrp1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFMcCntEventSelEnb7 : 8; /* * [31:24]SMMC counter7 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb6 : 8; /* * [23:16]SMMC counter6 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb5 : 8; /* * [15:8]SMMC counter5 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb4 : 8; /* * [7:0]SMMC counter4 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#else + unsigned int smmcFMcCntEventSelEnb4 : 8; /* * [7:0]SMMC counter4 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb5 : 8; /* * [15:8]SMMC counter5 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb6 : 8; /* * [23:16]SMMC counter6 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb7 : 8; /* * [31:24]SMMC counter7 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL0 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel0 { + struct tagStSmmcFMcCntEventSel0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel0UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel0EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel0ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel0ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel0BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel0TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel0VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel0VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel0TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel0BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel0ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel0ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel0EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel0UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL0_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL1 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel1 { + struct tagStSmmcFMcCntEventSel1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel1UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel1EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel1ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel1ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel1BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel1TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel1VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel1VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel1TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel1BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel1ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel1ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel1EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel1UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL1_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL2 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel2 { + struct tagStSmmcFMcCntEventSel2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel2UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel2EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel2ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel2ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel2BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel2TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel2VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel2VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel2TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel2BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel2ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel2ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel2EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel2UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL2_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL3 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel3 { + struct tagStSmmcFMcCntEventSel3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel3UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel3EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel3ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel3ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel3BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel3TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel3VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel3VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel3TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel3BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel3ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel3ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel3EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel3UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL3_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL4 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel4 { + struct tagStSmmcFMcCntEventSel4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel4UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel4EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel4ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel4ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel4BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel4TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel4VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel4VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel4TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel4BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel4ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel4ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel4EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel4UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL4_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL5 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel5 { + struct tagStSmmcFMcCntEventSel5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel5UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel5EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel5ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel5ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel5BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel5TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel5VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel5VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel5TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel5BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel5ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel5ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel5EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel5UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL5_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL6 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel6 { + struct tagStSmmcFMcCntEventSel6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel6UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel6EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel6ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel6ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel6BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel6TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel6VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel6VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel6TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel6BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel6ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel6ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel6EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel6UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL6_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL7 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel7 { + struct tagStSmmcFMcCntEventSel7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel7UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel7EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel7ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel7ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel7BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel7TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel7VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel7VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel7TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel7BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel7ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel7ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel7EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel7UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL7_U; + +/* ** + * Union name : SMMC_F_MC_STATUS + * @brief + * Description: + */ +typedef union tagUnSmmcFMcStatus { + struct tagStSmmcFMcStatus { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11] */ + unsigned int smmcRfTimeout : 1; /* * [10:10]indicate there is outstanding tag timeout in SMMC, when refill data + from CPI. This signal could not tell which outstanding tag is timeout in SMMC. SW + should rea d RCB of each outstanding tag to check out which outstanding tag is + timeout. */ + unsigned int quTxFlitCtpDone : 1; /* * [9:9]QU transmit data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int quRxFlitCtpDone : 1; /* * [8:8]QU received data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int mcFreeTagNum : 7; /* * [7:1]the free outstanding tag number in SMMC */ + unsigned int mcInitDone : 1; /* * [0:0]smmc initial done signal.1: initial done;0: in initial processing or have + * not started initial processing. + */ +#else + unsigned int mcInitDone : 1; /* * [0:0]smmc initial done signal.1: initial done;0: in initial processing or have + * not started initial processing. + */ + unsigned int mcFreeTagNum : 7; /* * [7:1]the free outstanding tag number in SMMC */ + unsigned int quRxFlitCtpDone : 1; /* * [8:8]QU received data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int quTxFlitCtpDone : 1; /* * [9:9]QU transmit data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int smmcRfTimeout : 1; /* * [10:10]indicate there is outstanding tag timeout in SMMC, when refill data + from CPI. This signal could not tell which outstanding tag is timeout in SMMC. SW + should rea d RCB of each outstanding tag to check out which outstanding tag is + timeout. */ + unsigned int reserved : 21; /* * [31:11] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_STATUS_U; + +/* ** +* Union name : SMMC_F_MC_CNT0 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB0 and SMMC_F_MC_CNT_EVENT_SEL0. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt0 { + struct tagStSmmcFMcCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt0 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt0 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT0_U; + +/* ** +* Union name : SMMC_F_MC_CNT1 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB1 and SMMC_F_MC_CNT_EVENT_SEL1. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt1 { + struct tagStSmmcFMcCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt1 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt1 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT1_U; + +/* ** +* Union name : SMMC_F_MC_CNT2 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB2 and SMMC_F_MC_CNT_EVENT_SEL2. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt2 { + struct tagStSmmcFMcCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt2 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt2 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT2_U; + +/* ** +* Union name : SMMC_F_MC_CNT3 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB3 and SMMC_F_MC_CNT_EVENT_SEL3. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt3 { + struct tagStSmmcFMcCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt3 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt3 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT3_U; + +/* ** +* Union name : SMMC_F_MC_CNT4 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB4 and SMMC_F_MC_CNT_EVENT_SEL4. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt4 { + struct tagStSmmcFMcCnt4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt4 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt4 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT4_U; + +/* ** +* Union name : SMMC_F_MC_CNT5 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB5 and SMMC_F_MC_CNT_EVENT_SEL5. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt5 { + struct tagStSmmcFMcCnt5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt5 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt5 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT5_U; + +/* ** +* Union name : SMMC_F_MC_CNT6 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB6 and SMMC_F_MC_CNT_EVENT_SEL6. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt6 { + struct tagStSmmcFMcCnt6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt6 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt6 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT6_U; + +/* ** +* Union name : SMMC_F_MC_CNT7 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB7 and SMMC_F_MC_CNT_EVENT_SEL7. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt7 { + struct tagStSmmcFMcCnt7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt7 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt7 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT7_U; + +/* ** + * Union name : SMMC_F_VC_FIFO_DEPTH0 + * @brief SMMC_F victim cache FIFO depth or credit + * Description: + */ +typedef union tagUnSmmcFVcFifoDepth0 { + struct tagStSmmcFVcFifoDepth0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int vc3WbCtrlFifoDepth : 3; /* * [31:29]Bank3 victim cache write back control fifo real depth. */ + unsigned int vc2WbCtrlFifoDepth : 3; /* * [28:26]Bank2 victim cache write back control fifo real depth. */ + unsigned int vc1WbCtrlFifoDepth : 3; /* * [25:23]Bank1 victim cache write back control fifo real depth. */ + unsigned int vc0WbCtrlFifoDepth : 3; /* * [22:20]Bank0 victim cache write back control fifo real depth.The write + * back control fifo is between MC and VC, the total depth is 6. + */ + unsigned int vc3WbDataFifoDepth : 5; /* * [19:15]Bank3 victim cache write back data fifo real depth. */ + unsigned int vc2WbDataFifoDepth : 5; /* * [14:10]Bank2 victim cache write back data fifo real depth. */ + unsigned int vc1WbDataFifoDepth : 5; /* * [9:5]Bank1 victim cache write back data fifo real depth. */ + unsigned int vc0WbDataFifoDepth : 5; /* * [4:0]Bank0 victim cache write back data fifo real depth.The write back + * data fifo is between MC and VC, the total depth is 24. The data fifo + * contain 24 x64B. + */ +#else + unsigned int vc0WbDataFifoDepth : 5; /* * [4:0]Bank0 victim cache write back data fifo real depth.The write back + * data fifo is between MC and VC, the total depth is 24. The data fifo + * contain 24 x64B. + */ + unsigned int vc1WbDataFifoDepth : 5; /* * [9:5]Bank1 victim cache write back data fifo real depth. */ + unsigned int vc2WbDataFifoDepth : 5; /* * [14:10]Bank2 victim cache write back data fifo real depth. */ + unsigned int vc3WbDataFifoDepth : 5; /* * [19:15]Bank3 victim cache write back data fifo real depth. */ + unsigned int vc0WbCtrlFifoDepth : 3; /* * [22:20]Bank0 victim cache write back control fifo real depth.The write + * back control fifo is between MC and VC, the total depth is 6. + */ + unsigned int vc1WbCtrlFifoDepth : 3; /* * [25:23]Bank1 victim cache write back control fifo real depth. */ + unsigned int vc2WbCtrlFifoDepth : 3; /* * [28:26]Bank2 victim cache write back control fifo real depth. */ + unsigned int vc3WbCtrlFifoDepth : 3; /* * [31:29]Bank3 victim cache write back control fifo real depth. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_FIFO_DEPTH0_U; + +/* ** + * Union name : SMMC_F_VC_FIFO_DEPTH1 + * @brief SMMC_F victim cache FIFO depth or credit + * Description: + */ +typedef union tagUnSmmcFVcFifoDepth1 { + struct tagStSmmcFVcFifoDepth1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 7; /* * [31:25] */ + unsigned int vcCrdtFromSmit : 3; /* * [24:22]credit counter from SMIT.The initial value is 6. */ + unsigned int smxtfFifoDepth : 6; /* * [21:16]smxt interface fifo.The fifo total depth is 32. */ + unsigned int vc3DataFifoDepth : 2; /* * [15:14]Bank3 victim cache data fifo real depth. */ + unsigned int vc2DataFifoDepth : 2; /* * [13:12]Bank2 victim cache data fifo real depth. */ + unsigned int vc1DataFifoDepth : 2; /* * [11:10]Bank1 victim cache data fifo real depth. */ + unsigned int vc0DataFifoDepth : 2; /* * [9:8]Bank0 victim cache data fifo real depth.This fifo is between each + vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 input i nto smxt_intf. */ + unsigned int vc3CtrlFifoDepth : 2; /* * [7:6]Bank3 victim cache control fifo real depth. */ + unsigned int vc2CtrlFifoDepth : 2; /* * [5:4]Bank2 victim cache control fifo real depth. */ + unsigned int vc1CtrlFifoDepth : 2; /* * [3:2]Bank1 victim cache control fifo real depth. */ + unsigned int vc0CtrlFifoDepth : 2; /* * [1:0]Bank0 victim cache control fifo real depth.This fifo is between + each vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 inpu t into smxt_intf. */ +#else + unsigned int vc0CtrlFifoDepth : 2; /* * [1:0]Bank0 victim cache control fifo real depth.This fifo is between + each vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 inpu t into smxt_intf. */ + unsigned int vc1CtrlFifoDepth : 2; /* * [3:2]Bank1 victim cache control fifo real depth. */ + unsigned int vc2CtrlFifoDepth : 2; /* * [5:4]Bank2 victim cache control fifo real depth. */ + unsigned int vc3CtrlFifoDepth : 2; /* * [7:6]Bank3 victim cache control fifo real depth. */ + unsigned int vc0DataFifoDepth : 2; /* * [9:8]Bank0 victim cache data fifo real depth.This fifo is between each + vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 input i nto smxt_intf. */ + unsigned int vc1DataFifoDepth : 2; /* * [11:10]Bank1 victim cache data fifo real depth. */ + unsigned int vc2DataFifoDepth : 2; /* * [13:12]Bank2 victim cache data fifo real depth. */ + unsigned int vc3DataFifoDepth : 2; /* * [15:14]Bank3 victim cache data fifo real depth. */ + unsigned int smxtfFifoDepth : 6; /* * [21:16]smxt interface fifo.The fifo total depth is 32. */ + unsigned int vcCrdtFromSmit : 3; /* * [24:22]credit counter from SMIT.The initial value is 6. */ + unsigned int reserved : 7; /* * [31:25] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_FIFO_DEPTH1_U; + +/* ** + * Union name : SMMC_F_MC_FIFO1_DEPTH + * @brief SMMC_F main cache FIFO depth or credit + * Description: + */ +typedef union tagUnSmmcFMcFifo1Depth { + struct tagStSmmcFMcFifo1Depth { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 3; /* * [31:29] */ + unsigned int lrb2FifoDepth : 5; /* * [28:24]lrb2 fifo real depth. */ + unsigned int lrb1FifoDepth : 5; /* * [23:19]lrb1 fifo real depth. */ + unsigned int lrb0FifoDepth : 5; /* * [18:14]lrb0 fifo real depth. */ + unsigned int quDataFifoDepth : 6; /* * [13:8]QU data fifo real depth. */ + unsigned int quCmdFifoDepth : 4; /* * [7:4]QU command fifo real depth. */ + unsigned int dataCreditFromQu : 4; /* * [3:0]data credit from QU. */ +#else + unsigned int dataCreditFromQu : 4; /* * [3:0]data credit from QU. */ + unsigned int quCmdFifoDepth : 4; /* * [7:4]QU command fifo real depth. */ + unsigned int quDataFifoDepth : 6; /* * [13:8]QU data fifo real depth. */ + unsigned int lrb0FifoDepth : 5; /* * [18:14]lrb0 fifo real depth. */ + unsigned int lrb1FifoDepth : 5; /* * [23:19]lrb1 fifo real depth. */ + unsigned int lrb2FifoDepth : 5; /* * [28:24]lrb2 fifo real depth. */ + unsigned int reserved : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_FIFO1_DEPTH_U; + +/* ** + * Union name : SMMC_F_MC_FIFO2_DEPTH + * @brief SMMC_F main cache FIFO depth + * Description: + */ +typedef union tagUnSmmcFMcFifo2Depth { + struct tagStSmmcFMcFifo2Depth { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 1; /* * [31:31] */ + unsigned int quStoreBufferDepth : 9; /* * [30:22]QU store buffer real depth. */ + unsigned int rfbufCredit : 9; /* * [21:13]refill buffer credit.The initial value is 0x100, indicate 256 64B + credit. */ + unsigned int lrb3FifoDepth : 5; /* * [12:8]lrb3 fifo real depth. */ + unsigned int quStoreBufferBp : 1; /* * [7:7]QU store buffer backpressure. */ + unsigned int quReturnFifoBp : 1; /* * [6:6]QU return fifo backpressure. */ + unsigned int quReturnFifoDepth : 6; /* * [5:0]QU return fifo real depth. */ +#else + unsigned int quReturnFifoDepth : 6; /* * [5:0]QU return fifo real depth. */ + unsigned int quReturnFifoBp : 1; /* * [6:6]QU return fifo backpressure. */ + unsigned int quStoreBufferBp : 1; /* * [7:7]QU store buffer backpressure. */ + unsigned int lrb3FifoDepth : 5; /* * [12:8]lrb3 fifo real depth. */ + unsigned int rfbufCredit : 9; /* * [21:13]refill buffer credit.The initial value is 0x100, indicate 256 64B + credit. */ + unsigned int quStoreBufferDepth : 9; /* * [30:22]QU store buffer real depth. */ + unsigned int reserved : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_FIFO2_DEPTH_U; + +/* ** + * Union name : SMMC_F_ERR_INJ + * @brief + * Description: + */ +typedef union tagUnSmmcFErrInj { + struct tagStSmmcFErrInj { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 6; /* * [31:26]reserved */ + unsigned int smmcSmxtfbUncrtErrInj : 1; /* * [25:25]smxt interface buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is inje cted when a memory read is issued to the + memory. */ + unsigned int smmcSmxtfbCrtErrInj : 1; /* * [24:24]smxt interface buffer ECC corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is injecte d when a memory read is issued to the + memory. */ + unsigned int smmcStbUncrtErrInj : 1; /* * [23:23]engine store buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After Err + injection start, err is inject + ed when a memory read is issued to the memory. */ + unsigned int smmcStbCrtErrInj : 1; /* * [22:22]Engine store buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection start, + err is injected when a memory read is issued to the memory. */ + unsigned int smmcVfaUncrtErrInj : 1; /* * [21:21]VFA table ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcVfaCrtErrInj : 1; /* * [20:20]VFA table ECC corrected err injection requestion;err injection + start when posedge of this bit is detected; After Err injection start, err is + injected when a mem ory read is issued to the memory. */ + unsigned int smmcRfBufUncrtErrInj : 1; /* * [19:19]refill buffer ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected whe n a memory read is issued to the memory. */ + unsigned int smmcRfBufCrtErrInj : 1; /* * [18:18]refill buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcQuIntfUncrtErrInj : 1; /* * [17:17]QU interface buffer(include qu_data buffer, qu_lrn buffer + and qu_store_data buffer) ECC un-corrected err injection requestion;err + injection start when posedge o f this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. + */ + unsigned int smmcQuIntfCrtErrInj : 1; /* * [16:16]QU interface buffer(include qu_data buffer, qu_lrn buffer and + qu_store_data buffer) ECC corrected err injection requestion;err injection + start when posedge of t his bit is detected; After Err injection start, err + is injected when a memory read is issued to the memory. + */ + unsigned int smmcMc3UncrtErrInj : 1; /* * [15:15]main cache bank3 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc3CrtErrInj : 1; /* * [14:14]main cache bank3 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc2UncrtErrInj : 1; /* * [13:13]main cache bank2 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc2CrtErrInj : 1; /* * [12:12]main cache bank2 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc1UncrtErrInj : 1; /* * [11:11]main cache bank1 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc1CrtErrInj : 1; /* * [10:10]main cache bank1 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc0UncrtErrInj : 1; /* * [9:9]main cache bank0 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc0CrtErrInj : 1; /* * [8:8]main cache bank0 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcVc3UncrtErrInj : 1; /* * [7:7]victim cache bank3 memory(include all memory in victim cache + bank3) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc3CrtErrInj : 1; /* * [6:6]victim cache bank3 memory(include all memory in victim cache bank3) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc2UncrtErrInj : 1; /* * [5:5]victim cache bank2 memory(include all memory in victim cache + bank2) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc2CrtErrInj : 1; /* * [4:4]victim cache bank2 memory(include all memory in victim cache bank2) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc1UncrtErrInj : 1; /* * [3:3]victim cache bank1 memory(include all memory in victim cache + bank1) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc1CrtErrInj : 1; /* * [2:2]victim cache bank1 memory(include all memory in victim cache bank1) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc0UncrtErrInj : 1; /* * [1:1]victim cache bank0 memory(include all memory in victim cache + bank0) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc0CrtErrInj : 1; /* * [0:0]victim cache bank0 memory(include all memory in victim cache bank0) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ +#else + unsigned int smmcVc0CrtErrInj : 1; /* * [0:0]victim cache bank0 memory(include all memory in victim cache bank0) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc0UncrtErrInj : 1; /* * [1:1]victim cache bank0 memory(include all memory in victim cache + bank0) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc1CrtErrInj : 1; /* * [2:2]victim cache bank1 memory(include all memory in victim cache bank1) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc1UncrtErrInj : 1; /* * [3:3]victim cache bank1 memory(include all memory in victim cache + bank1) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc2CrtErrInj : 1; /* * [4:4]victim cache bank2 memory(include all memory in victim cache bank2) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc2UncrtErrInj : 1; /* * [5:5]victim cache bank2 memory(include all memory in victim cache + bank2) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc3CrtErrInj : 1; /* * [6:6]victim cache bank3 memory(include all memory in victim cache bank3) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc3UncrtErrInj : 1; /* * [7:7]victim cache bank3 memory(include all memory in victim cache + bank3) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcMc0CrtErrInj : 1; /* * [8:8]main cache bank0 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc0UncrtErrInj : 1; /* * [9:9]main cache bank0 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc1CrtErrInj : 1; /* * [10:10]main cache bank1 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc1UncrtErrInj : 1; /* * [11:11]main cache bank1 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc2CrtErrInj : 1; /* * [12:12]main cache bank2 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc2UncrtErrInj : 1; /* * [13:13]main cache bank2 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc3CrtErrInj : 1; /* * [14:14]main cache bank3 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc3UncrtErrInj : 1; /* * [15:15]main cache bank3 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcQuIntfCrtErrInj : 1; /* * [16:16]QU interface buffer(include qu_data buffer, qu_lrn buffer and + qu_store_data buffer) ECC corrected err injection requestion;err injection + start when posedge of t his bit is detected; After Err injection start, err + is injected when a memory read is issued to the memory. + */ + unsigned int smmcQuIntfUncrtErrInj : 1; /* * [17:17]QU interface buffer(include qu_data buffer, qu_lrn buffer + and qu_store_data buffer) ECC un-corrected err injection requestion;err + injection start when posedge o f this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. + */ + unsigned int smmcRfBufCrtErrInj : 1; /* * [18:18]refill buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcRfBufUncrtErrInj : 1; /* * [19:19]refill buffer ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected whe n a memory read is issued to the memory. */ + unsigned int smmcVfaCrtErrInj : 1; /* * [20:20]VFA table ECC corrected err injection requestion;err injection + start when posedge of this bit is detected; After Err injection start, err is + injected when a mem ory read is issued to the memory. */ + unsigned int smmcVfaUncrtErrInj : 1; /* * [21:21]VFA table ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcStbCrtErrInj : 1; /* * [22:22]Engine store buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection start, + err is injected when a memory read is issued to the memory. */ + unsigned int smmcStbUncrtErrInj : 1; /* * [23:23]engine store buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After Err + injection start, err is inject + ed when a memory read is issued to the memory. */ + unsigned int smmcSmxtfbCrtErrInj : 1; /* * [24:24]smxt interface buffer ECC corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is injecte d when a memory read is issued to the + memory. */ + unsigned int smmcSmxtfbUncrtErrInj : 1; /* * [25:25]smxt interface buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is inje cted when a memory read is issued to the + memory. */ + unsigned int reserved : 6; /* * [31:26]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_ERR_INJ_U; + +/* ** + * Union name : SMMC_F_GPA_TRANS_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFGpaTransErr { + struct tagStSmmcFGpaTransErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of BAT or CLA GPA.[31:21]:reserved;[20]:error type. + 1:memory index error; 0:GPA is invalid;[19:10]:VF-ID;[9:6]:tag_type;[5:4]:current CLA l + ev: 2'b00:0 level CLA; 2'b01:1 level CLA; 2'B10:2 level CLA;[3:2]:total CLA + lev: 2'b00:0 level; 2'b01:1 level; 2'b10:2 level; + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of BAT or CLA GPA.[31:21]:reserved;[20]:error type. + 1:memory index error; 0:GPA is invalid;[19:10]:VF-ID;[9:6]:tag_type;[5:4]:current CLA l + ev: 2'b00:0 level CLA; 2'b01:1 level CLA; 2'B10:2 level CLA;[3:2]:total CLA + lev: 2'b00:0 level; 2'b01:1 level; 2'b10:2 level; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_GPA_TRANS_ERR_U; + +/* ** + * Union name : SMMC_F_QU_INTF_CNT_CFG + * @brief + * Description: + */ +typedef union tagUnSmmcFQuIntfCntCfg { + struct tagStSmmcFQuIntfCntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + smmcFQuIntfRxCntCfg : 16; /* * [31:16]qu_interface API received counter configuration, API received counter + is used to count for API request that sent from QU to + SMMC_F:qu_intf_rx_cnt和qu_rx_flit_ctp + 共用该寄存器的配置参数。qu_intf_rx_cnt要计数的API类型，qu_rx_flit_ctp要抓的数据类型，都由该寄存器的bit【30:16】决定。[31]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[30]:VF_ ID configuration + enable. If this bit is valid, counter will count for API by the VF_ID configured by + CSR.[29]:TAG_TYPE configuration enable. If this bit is vali d, counter will count for + API by the tag_type configured by CSR.[28]:OPCODE configuration enable. If this bit is + valid, counter will count for API by the opcode configured by CSR.[27:19]:VF_ID. If + bit[30] is valid, counter will count for API by this + field.(NOTE:当该参数用来配置qu_intf_rx_cnt时，配的是映射后的VF_ID.当该参数用来配置qu_rx_flit_ct + p时，配的是映射之前的VF_ID.)[18:17]:TAG_TYPE. If bit[29] is valid, counter will count + for API by this field. 2'b00: flow table parent context; 2'b01: RDMA parent cont + ext; 2'b10: child context; 2'b11: reserved;[16]:OPCODE. If bit[28] is valid, + counter will count for API by this field. 1'b0: load; 1'b1: store;Note:bit[ 30:28] + could be configured to enable or disable independently. If bit[30:28] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the s ame time. If none + of bit[30:28] is valid, counter will count for any API received. + */ + unsigned int + smmcFQuIntfTxCntCfg : 16; /* * [15:0]qu_interface API transmited counter configuration, API transmit + counter is used to count for API response that sent from SMMC_F to + QU:qu_intf_tx_cnt和qu_tx_flit_ + ctp共用该寄存器的配置参数。qu_intf_tx_cnt要计数的API类型，qu_tx_flit_ctp要抓的数据类型，都由该寄存器的bit【14:0】决定。[15]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[14]:V F_ID + configuration enable. If this bit is valid, counter will count for API by the + VF_ID configured by CSR.[13]:TAG_TYPE configuration enable. If this bit is va + lid, counter will count for API by the tag_type configured by CSR.[12]:OPCODE + configuration enable. If this bit is valid, counter will count for API by the + opco de configured by CSR.[11:3]:VF_ID. If bit[14] is valid, counter will + count for API by this field.(NOTE:该参数配的是映射后的VF_ID.)[2:1]:TAG_TYPE. + If bit[13] is valid, cou nter will count for API by this field. 2'b00: flow + table parent context; 2'b01: RDMA parent context; 2'b10: child context; + 2'b11: reserved;[0]:OPCODE. I f bit[12] is valid, counter will count for API + by this field. 1'b0: load; 1'b1: store;Note:bit[14:12] could be + configured to enable or disable independently . If bit[14:12] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the same time. + If none of bit[14:12] is valid, counter will count for any API sent. */ +#else + unsigned int + smmcFQuIntfTxCntCfg : 16; /* * [15:0]qu_interface API transmited counter configuration, API transmit + counter is used to count for API response that sent from SMMC_F to + QU:qu_intf_tx_cnt和qu_tx_flit_ + ctp共用该寄存器的配置参数。qu_intf_tx_cnt要计数的API类型，qu_tx_flit_ctp要抓的数据类型，都由该寄存器的bit【14:0】决定。[15]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[14]:V F_ID + configuration enable. If this bit is valid, counter will count for API by the + VF_ID configured by CSR.[13]:TAG_TYPE configuration enable. If this bit is va + lid, counter will count for API by the tag_type configured by CSR.[12]:OPCODE + configuration enable. If this bit is valid, counter will count for API by the + opco de configured by CSR.[11:3]:VF_ID. If bit[14] is valid, counter will + count for API by this field.(NOTE:该参数配的是映射后的VF_ID.)[2:1]:TAG_TYPE. + If bit[13] is valid, cou nter will count for API by this field. 2'b00: flow + table parent context; 2'b01: RDMA parent context; 2'b10: child context; + 2'b11: reserved;[0]:OPCODE. I f bit[12] is valid, counter will count for API + by this field. 1'b0: load; 1'b1: store;Note:bit[14:12] could be + configured to enable or disable independently . If bit[14:12] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the same time. + If none of bit[14:12] is valid, counter will count for any API sent. */ + unsigned int + smmcFQuIntfRxCntCfg : 16; /* * [31:16]qu_interface API received counter configuration, API received counter + is used to count for API request that sent from QU to + SMMC_F:qu_intf_rx_cnt和qu_rx_flit_ctp + 共用该寄存器的配置参数。qu_intf_rx_cnt要计数的API类型，qu_rx_flit_ctp要抓的数据类型，都由该寄存器的bit【30:16】决定。[31]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[30]:VF_ ID configuration + enable. If this bit is valid, counter will count for API by the VF_ID configured by + CSR.[29]:TAG_TYPE configuration enable. If this bit is vali d, counter will count for + API by the tag_type configured by CSR.[28]:OPCODE configuration enable. If this bit is + valid, counter will count for API by the opcode configured by CSR.[27:19]:VF_ID. If + bit[30] is valid, counter will count for API by this + field.(NOTE:当该参数用来配置qu_intf_rx_cnt时，配的是映射后的VF_ID.当该参数用来配置qu_rx_flit_ct + p时，配的是映射之前的VF_ID.)[18:17]:TAG_TYPE. If bit[29] is valid, counter will count + for API by this field. 2'b00: flow table parent context; 2'b01: RDMA parent cont + ext; 2'b10: child context; 2'b11: reserved;[16]:OPCODE. If bit[28] is valid, + counter will count for API by this field. 1'b0: load; 1'b1: store;Note:bit[ 30:28] + could be configured to enable or disable independently. If bit[30:28] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the s ame time. If none + of bit[30:28] is valid, counter will count for any API received. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_QU_INTF_CNT_CFG_U; + +/* ** + * Union name : SMMC_F_QU_INTF_RX_CNT + * @brief + * Description: + */ +typedef union tagUnSmmcFQuIntfRxCnt { + struct tagStSmmcFQuIntfRxCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFQuIntfRxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#else + unsigned int smmcFQuIntfRxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_QU_INTF_RX_CNT_U; + +/* ** + * Union name : SMMC_F_QU_INTF_TX_CNT + * @brief + * Description: + */ +typedef union tagUnSmmcFQuIntfTxCnt { + struct tagStSmmcFQuIntfTxCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFQuIntfTxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#else + unsigned int smmcFQuIntfTxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_QU_INTF_TX_CNT_U; + +/* ** + * Union name : SMMC_F_MC_CFG2 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCfg2 { + struct tagStSmmcFMcCfg2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11] */ + unsigned int mcRefillTimeoutEnb : 1; /* * [10:10]enable SMMC to monitor and check if a refill request to CPI is + timeout. */ + unsigned int smfCommonMemPowerMode : 6; /* * [9:4]memory power mode control, this signal is used to control + * memory in SMXR,and SMMC(except tag memory and data memory in main + * cache and victim cache) + */ + unsigned int + smmcFRfErrCtpClr : 1; /* * [3:3]clear the refill error information and restart to capture next refill error + information. The refill error information could be read via CSR indirect access.Note + :该信号是用来清除refill error捕抓的信息,并且重新开始捕抓下一个refill + error的信息的。正常的流程应该是，refill + error报中断后，软件通过CSR间接读写接口去读取捕抓的错误信息（捕抓信息的bit0等于时表示捕抓的信息有效），读取分析完后再通过该信号去清除捕抓的信息。该信号是上升沿触发清零 + 操作，如果多次清零，需要先把该信号写成零，再写成一，这样SMMC会产生一个上升沿脉冲信号，并用该脉冲信号清零。 + */ + unsigned int smmcFRttCntEnb : 1; /* * [2:2]SMMC_F support to record the longest/shortest latency of refilling + from CPI, or record the longest/shortest operating latency in SMMC_F.If this + signal is enable , SMMC_F issue a counter to record the latency, and capture the + latency in two register:rtt_ctp_short and rtt_ctp_long. these two register can be + read by SW via CSR indirect access. */ + unsigned int smmcFRttCntType : 1; /* * [1:1]SW can configure this signal to indicate SMMC_F which type of + * latency to record:0:record API operating latency in SMMC_F.1:record refill + * latency from CPI. + */ + unsigned int smmcFRscCntMixEn : 1; /* * [0:0]If rsc_cnt_mix_en=1, SQ WQE and RQ WQE and other data structures + share the same virtual cache.SMMC doesn't differentiate WQE type (SQ WQE and RQ + WQE) in this ca se, SMMC just maintains one resource counter.If + rsc_cnt_mix_en=0, SQ WQE uses a separate virtual cache (only SQ WQE in this + virtual cache). RQ WQE uses another separate virtual cache (only RQ WQE in this + virtual cache).SQ resource counter and RQ resource counter are counted + independently. + */ +#else + unsigned int smmcFRscCntMixEn : 1; /* * [0:0]If rsc_cnt_mix_en=1, SQ WQE and RQ WQE and other data structures + share the same virtual cache.SMMC doesn't differentiate WQE type (SQ WQE and RQ + WQE) in this ca se, SMMC just maintains one resource counter.If + rsc_cnt_mix_en=0, SQ WQE uses a separate virtual cache (only SQ WQE in this + virtual cache). RQ WQE uses another separate virtual cache (only RQ WQE in this + virtual cache).SQ resource counter and RQ resource counter are counted + independently. + */ + unsigned int smmcFRttCntType : 1; /* * [1:1]SW can configure this signal to indicate SMMC_F which type of + * latency to record:0:record API operating latency in SMMC_F.1:record refill + * latency from CPI. + */ + unsigned int smmcFRttCntEnb : 1; /* * [2:2]SMMC_F support to record the longest/shortest latency of refilling + from CPI, or record the longest/shortest operating latency in SMMC_F.If this + signal is enable , SMMC_F issue a counter to record the latency, and capture the + latency in two register:rtt_ctp_short and rtt_ctp_long. these two register can be + read by SW via CSR indirect access. */ + unsigned int + smmcFRfErrCtpClr : 1; /* * [3:3]clear the refill error information and restart to capture next refill error + information. The refill error information could be read via CSR indirect access.Note + :该信号是用来清除refill error捕抓的信息,并且重新开始捕抓下一个refill + error的信息的。正常的流程应该是，refill + error报中断后，软件通过CSR间接读写接口去读取捕抓的错误信息（捕抓信息的bit0等于时表示捕抓的信息有效），读取分析完后再通过该信号去清除捕抓的信息。该信号是上升沿触发清零 + 操作，如果多次清零，需要先把该信号写成零，再写成一，这样SMMC会产生一个上升沿脉冲信号，并用该脉冲信号清零。 + */ + unsigned int smfCommonMemPowerMode : 6; /* * [9:4]memory power mode control, this signal is used to control + * memory in SMXR,and SMMC(except tag memory and data memory in main + * cache and victim cache) + */ + unsigned int mcRefillTimeoutEnb : 1; /* * [10:10]enable SMMC to monitor and check if a refill request to CPI is + timeout. */ + unsigned int reserved : 21; /* * [31:11] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CFG2_U; + + +/* ** + * Union name : SMMC_L_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmmcLVersion { + struct tagStSmmcLVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smmcLVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_VERSION_U; + +/* ** + * Union name : SMMC_L_CFG + * @brief SMMC_L configure register + * Description: + */ +typedef union tagUnSmmcLCfg { + struct tagStSmmcLCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int memIniEn : 1; /* * [2:2]Enable to initialize internal memory1: enable;0: disable */ + unsigned int smmcLEccChk : 1; /* * [1:1]ECC error check enable */ + unsigned int smmcLParityChk : 1; /* * [0:0]reserved */ +#else + unsigned int smmcLParityChk : 1; /* * [0:0]reserved */ + unsigned int smmcLEccChk : 1; /* * [1:1]ECC error check enable */ + unsigned int memIniEn : 1; /* * [2:2]Enable to initialize internal memory1: enable;0: disable */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CFG_U; + +/* ** + * Union name : SMMC_L_STAT + * @brief SMMC_L status register + * Description: + */ +typedef union tagUnSmmcLStat { + struct tagStSmmcLStat { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1] */ + unsigned int memIniDone : 1; /* * [0:0]Indicate whether memory initialization done or not1: Done0: not complete + */ +#else + unsigned int memIniDone : 1; /* * [0:0]Indicate whether memory initialization done or not1: Done0: not complete + */ + unsigned int reserved : 31; /* * [31:1] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_STAT_U; + +/* ** + * Union name : SMMC_L_INT_VECTOR + * @brief SMMC_L interrupt vector register + * Description: + */ +typedef union tagUnSmmcLIntVector { + struct tagStSmmcLIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INT_VECTOR_U; + +/* ** + * Union name : SMMC_L_INT + * @brief SMMC_L interrupt register + * Description: + */ +typedef union tagUnSmmcLInt { + struct tagStSmmcLInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int intData : 1; /* * [0:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 1; /* * [0:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INT_U; + +/* ** + * Union name : SMMC_L_INT_MASK + * @brief SMMC_L interrupt mask register + * Description: + */ +typedef union tagUnSmmcLIntMask { + struct tagStSmmcLIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int errMask : 1; /* * [0:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 1; /* * [0:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INT_MASK_U; + +/* ** + * Union name : SMMC_L_MEM_ERR + * @brief SMMC_L MEM error register + * Description: + */ +typedef union tagUnSmmcLMemErr { + struct tagStSmmcLMemErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int mainMem1bEccMerr : 1; /* * [3:3] */ + unsigned int mainMem1bEccErr : 1; /* * [2:2]main memory 1 bit ECC error */ + unsigned int mainMem2bEccMerr : 1; /* * [1:1]multi times of main memory 2 bit ECC error */ + unsigned int mainMem2bEccErr : 1; /* * [0:0]main memory 2 bit ECC error */ +#else + unsigned int mainMem2bEccErr : 1; /* * [0:0]main memory 2 bit ECC error */ + unsigned int mainMem2bEccMerr : 1; /* * [1:1]multi times of main memory 2 bit ECC error */ + unsigned int mainMem1bEccErr : 1; /* * [2:2]main memory 1 bit ECC error */ + unsigned int mainMem1bEccMerr : 1; /* * [3:3] */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_MEM_ERR_U; + +/* ** + * Union name : SMMC_L_MEM_ERR_MASK + * @brief SMMC_L MEM error mask register + * Description: + */ +typedef union tagUnSmmcLMemErrMask { + struct tagStSmmcLMemErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]reserved. */ + unsigned int mainMem1bEccErrMask : 1; /* * [1:1]main memory 1 bit ECC error mask */ + unsigned int mainMem2bEccErrMask : 1; /* * [0:0]main memory 2 bit ECC error mask */ +#else + unsigned int mainMem2bEccErrMask : 1; /* * [0:0]main memory 2 bit ECC error mask */ + unsigned int mainMem1bEccErrMask : 1; /* * [1:1]main memory 1 bit ECC error mask */ + unsigned int reserved : 30; /* * [31:2]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_MEM_ERR_MASK_U; + +/* ** + * Union name : SMMC_L_MEM_ERR_INFO + * @brief SMMC_L MEM error info register + * Description: + */ +typedef union tagUnSmmcLMemErrInfo { + struct tagStSmmcLMemErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 14; /* * [31:18]reserved. */ + unsigned int memErrInfoType : 2; /* * [17:16]Indicate which error's info is captured:00: main memory has 1 bit + * ECC error;01: main memory has 2 bit ECC error;10~11: reserved + */ + unsigned int reserved1 : 1; /* * [15:15]reserved bit */ + unsigned int memErrIndex : 15; /* * [14:0]Indicate the address of entry meeting error.For main memory, + * index[14:0] is usage for 32 K entries of 32 byte. + */ +#else + unsigned int memErrIndex : 15; /* * [14:0]Indicate the address of entry meeting error.For main memory, + * index[14:0] is usage for 32 K entries of 32 byte. + */ + unsigned int reserved1 : 1; /* * [15:15]reserved bit */ + unsigned int memErrInfoType : 2; /* * [17:16]Indicate which error's info is captured:00: main memory has 1 bit + * ECC error;01: main memory has 2 bit ECC error;10~11: reserved + */ + unsigned int reserved0 : 14; /* * [31:18]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_MEM_ERR_INFO_U; + +/* ** + * Union name : SMMC_L_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmmcLIndrectCtrl { + struct tagStSmmcLIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smmcLIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcLIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smmcLIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'h0: main memory;4'h1: ECC + memory.ECC memory only can rightly read or write in debug mode without normal + datapath stream.4' h2: loopback CAM request info and link info.It only support to + read and not to write;4'h3: slot ring.It only support to read and not to + write;4'h4: bank queue i nfo.It only support to read and not to write;4'h5: + reserved;4'h6: reserved4'h7~4'hf: reserved + */ + unsigned int + smmcLIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.(1) Main memory:Total size is 1M byte and one e ntry + is 32 byte.Index[17:0] is usage for access main memory.Index[17:3] address to one entry, + and index[2:0] address to one 4 byte in one entry.index[2:0]000: e ntry[255:224];001: + entry[223:192];010: entry[191:160];011: entry[159:128];100: entry[127:96];101: + entry[95:64];110: entry[63:32];111: entry[31:0];(2) ECC memory One 10 bit ECC protects one + entry of main memory.16 ECC of 10 bits is grouped as one entry of ECC memory and total + number of entries is 2 K. Index[14:0] address one entry of 10 bit ECC. One entry + is{22'd0,EEC[9:0]};(3) Loopback CAM and Request info and Link infoThese are addressed by + request ID.Total number of request ID is 16. Index[3:0] address one entry of one request + ID. One entry's datastructre:entry[31:24]: loopback CAM[7:0];entry[23:21]: reserved 3 + bit;entry[20:4]: req uest info[16:0];entry[3:0]: link info[3:0]; (4) Slot ringSlot ring + only has 8 bits, index is unused.(5) Bank queue list info;Bank queue list info is addressed + b y bank ID, and total number of bank in SMMC_L is 16 banks. Once CSR can access 2 bank + queue list infos as an entry. Its datastructure isEntry[31:26]: reserved 6 + bits;Entry[25:16]: bank queue list info[9:0]Entry[15:10]: reserved 6 bits;Entry[9:0]: bank + queue list info[9:0]Index[2:0] address one entry;000: bank 0 and ban k 1's list info001: + bank 2 and bank 3's list info010: bank 4 and bank 5's list info011: bank 6 and bank 7's + list info100: bank 8 and bank 9's list info101: bank 10 and bank 11's list info110: bank 12 + and bank 13's list info111: bank 14 and bank 15's list info(6) reserved + */ +#else + unsigned int + smmcLIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.(1) Main memory:Total size is 1M byte and one e ntry + is 32 byte.Index[17:0] is usage for access main memory.Index[17:3] address to one entry, + and index[2:0] address to one 4 byte in one entry.index[2:0]000: e ntry[255:224];001: + entry[223:192];010: entry[191:160];011: entry[159:128];100: entry[127:96];101: + entry[95:64];110: entry[63:32];111: entry[31:0];(2) ECC memory One 10 bit ECC protects one + entry of main memory.16 ECC of 10 bits is grouped as one entry of ECC memory and total + number of entries is 2 K. Index[14:0] address one entry of 10 bit ECC. One entry + is{22'd0,EEC[9:0]};(3) Loopback CAM and Request info and Link infoThese are addressed by + request ID.Total number of request ID is 16. Index[3:0] address one entry of one request + ID. One entry's datastructre:entry[31:24]: loopback CAM[7:0];entry[23:21]: reserved 3 + bit;entry[20:4]: req uest info[16:0];entry[3:0]: link info[3:0]; (4) Slot ringSlot ring + only has 8 bits, index is unused.(5) Bank queue list info;Bank queue list info is addressed + b y bank ID, and total number of bank in SMMC_L is 16 banks. Once CSR can access 2 bank + queue list infos as an entry. Its datastructure isEntry[31:26]: reserved 6 + bits;Entry[25:16]: bank queue list info[9:0]Entry[15:10]: reserved 6 bits;Entry[9:0]: bank + queue list info[9:0]Index[2:0] address one entry;000: bank 0 and ban k 1's list info001: + bank 2 and bank 3's list info010: bank 4 and bank 5's list info011: bank 6 and bank 7's + list info100: bank 8 and bank 9's list info101: bank 10 and bank 11's list info110: bank 12 + and bank 13's list info111: bank 14 and bank 15's list info(6) reserved + */ + unsigned int smmcLIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'h0: main memory;4'h1: ECC + memory.ECC memory only can rightly read or write in debug mode without normal + datapath stream.4' h2: loopback CAM request info and link info.It only support to + read and not to write;4'h3: slot ring.It only support to read and not to + write;4'h4: bank queue i nfo.It only support to read and not to write;4'h5: + reserved;4'h6: reserved4'h7~4'hf: reserved + */ + unsigned int smmcLIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smmcLIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcLIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INDRECT_CTRL_U; + +/* ** + * Union name : SMMC_L_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmmcLIndrectTimeout { + struct tagStSmmcLIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smmcLIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMMC_L_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmmcLIndrectData { + struct tagStSmmcLIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INDRECT_DATA_U; + +/* ** + * Union name : SMMC_L_CNT_CFG + * @brief SMMC_L counter configure register + * Description: + */ +typedef union tagUnSmmcLCntCfg { + struct tagStSmmcLCntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20] */ + unsigned int cnt3Sel : 2; /* * [19:18]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt2Sel : 2; /* * [17:16]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt1Sel : 2; /* * [15:14]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt0Sel : 2; /* * [13:12]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt3MatchEn : 2; /* * [11:10]00: count for all types01: reserved 10: counter for matched bank + * ID;11: reserved; + */ + unsigned int cnt2MatchEn : 2; /* * [9:8]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt1MatchEn : 2; /* * [7:6]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt0MatchEn : 2; /* * [5:4]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ +#else + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt0MatchEn : 2; /* * [5:4]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt1MatchEn : 2; /* * [7:6]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt2MatchEn : 2; /* * [9:8]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt3MatchEn : 2; /* * [11:10]00: count for all types01: reserved 10: counter for matched bank + * ID;11: reserved; + */ + unsigned int cnt0Sel : 2; /* * [13:12]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt1Sel : 2; /* * [15:14]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt2Sel : 2; /* * [17:16]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt3Sel : 2; /* * [19:18]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int reserved : 12; /* * [31:20] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT_CFG_U; + +/* ** + * Union name : SMMC_L_CNT_MATCH_BANK + * @brief SMMC_L counter configure register for matching instance ID + * Description: + */ +typedef union tagUnSmmcLCntMatchBank { + struct tagStSmmcLCntMatchBank { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int cnt3MatchBank : 4; /* * [15:12]Bank ID for counter 3 */ + unsigned int cnt2MatchBank : 4; /* * [11:8]Bank ID for counter 2 */ + unsigned int cnt1MatchBank : 4; /* * [7:4]Bank ID for counter 1 */ + unsigned int cnt0MatchBank : 4; /* * [3:0]Bank ID for counter 0 */ +#else + unsigned int cnt0MatchBank : 4; /* * [3:0]Bank ID for counter 0 */ + unsigned int cnt1MatchBank : 4; /* * [7:4]Bank ID for counter 1 */ + unsigned int cnt2MatchBank : 4; /* * [11:8]Bank ID for counter 2 */ + unsigned int cnt3MatchBank : 4; /* * [15:12]Bank ID for counter 3 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT_MATCH_BANK_U; + +/* ** + * Union name : SMMC_L_CNT_MATCH_INSTANCE + * @brief SMMC_L counter configure register for matching instance ID + * Description: + */ +typedef union tagUnSmmcLCntMatchInstance { + struct tagStSmmcLCntMatchInstance { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]SMMC_L does not see instance ID, so that this configuration is not used + */ + unsigned int cnt3MatchInst : 5; /* * [19:15]Reserved */ + unsigned int cnt2MatchInst : 5; /* * [14:10]Reserved */ + unsigned int cnt1MatchInst : 5; /* * [9:5]Reserved */ + unsigned int cnt0MatchInst : 5; /* * [4:0]Reserved */ +#else + unsigned int cnt0MatchInst : 5; /* * [4:0]Reserved */ + unsigned int cnt1MatchInst : 5; /* * [9:5]Reserved */ + unsigned int cnt2MatchInst : 5; /* * [14:10]Reserved */ + unsigned int cnt3MatchInst : 5; /* * [19:15]Reserved */ + unsigned int reserved : 12; /* * [31:20]SMMC_L does not see instance ID, so that this configuration is not used + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT_MATCH_INSTANCE_U; + +/* ** + * Union name : SMMC_L_CNT0 + * @brief SMMC_L counter 0 register + * Description: + */ +typedef union tagUnSmmcLCnt0 { + struct tagStSmmcLCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt0 : 32; /* * [31:0]Couner 0 accroding to counter configure register. */ +#else + unsigned int smmcLCnt0 : 32; /* * [31:0]Couner 0 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT0_U; + +/* ** + * Union name : SMMC_L_CNT1 + * @brief SMMC_L counter 1 register + * Description: + */ +typedef union tagUnSmmcLCnt1 { + struct tagStSmmcLCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt1 : 32; /* * [31:0]Couner 1 accroding to counter configure register. */ +#else + unsigned int smmcLCnt1 : 32; /* * [31:0]Couner 1 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT1_U; + +/* ** + * Union name : SMMC_L_CNT2 + * @brief SMMC_L counter 2 register + * Description: + */ +typedef union tagUnSmmcLCnt2 { + struct tagStSmmcLCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt2 : 32; /* * [31:0]Couner 2 accroding to counter configure register. */ +#else + unsigned int smmcLCnt2 : 32; /* * [31:0]Couner 2 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT2_U; + +/* ** + * Union name : SMMC_L_CNT3 + * @brief SMMC_L counter 3 register + * Description: + */ +typedef union tagUnSmmcLCnt3 { + struct tagStSmmcLCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt3 : 32; /* * [31:0]Couner 3 accroding to counter configure register. */ +#else + unsigned int smmcLCnt3 : 32; /* * [31:0]Couner 3 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT3_U; + +/* ** + * Union name : SMMC_L_BANK_QUEUE_DEPTH_CTP0 + * @brief SMMC_L bank queue's depth register 0 + * Description: + */ +typedef union tagUnSmmcLBankQueueDepthCtp0 { + struct tagStSmmcLBankQueueDepthCtp0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int curDepthBank7 : 4; /* * [31:28]Current depth of bank 7 queue.Notice that depth of bank is up to 15, + because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for de bug mode. */ + unsigned int curDepthBank6 : 4; /* * [27:24]Current depth of bank 6 queue. */ + unsigned int curDepthBank5 : 4; /* * [23:20]Current depth of bank 5 queue. */ + unsigned int curDepthBank4 : 4; /* * [19:16]Current depth of bank 4 queue. */ + unsigned int curDepthBank3 : 4; /* * [15:12]Current depth of bank 3 queue. */ + unsigned int curDepthBank2 : 4; /* * [11:8]Current depth of bank 2 queue. */ + unsigned int curDepthBank1 : 4; /* * [7:4]Current depth of bank 1 queue. */ + unsigned int curDepthBank0 : 4; /* * [3:0]Current depth of bank 0 queue. */ +#else + unsigned int curDepthBank0 : 4; /* * [3:0]Current depth of bank 0 queue. */ + unsigned int curDepthBank1 : 4; /* * [7:4]Current depth of bank 1 queue. */ + unsigned int curDepthBank2 : 4; /* * [11:8]Current depth of bank 2 queue. */ + unsigned int curDepthBank3 : 4; /* * [15:12]Current depth of bank 3 queue. */ + unsigned int curDepthBank4 : 4; /* * [19:16]Current depth of bank 4 queue. */ + unsigned int curDepthBank5 : 4; /* * [23:20]Current depth of bank 5 queue. */ + unsigned int curDepthBank6 : 4; /* * [27:24]Current depth of bank 6 queue. */ + unsigned int curDepthBank7 : 4; /* * [31:28]Current depth of bank 7 queue.Notice that depth of bank is up to 15, + because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for de bug mode. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_U; + +/* ** + * Union name : SMMC_L_BANK_QUEUE_DEPTH_CTP1 + * @brief SMMC_L bank queue's depth register 1 + * Description: + */ +typedef union tagUnSmmcLBankQueueDepthCtp1 { + struct tagStSmmcLBankQueueDepthCtp1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int curDepthBank15 : 4; /* * [31:28]Current depth of bank 15 queue.Notice that depth of bank is up to + 15, because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for d ebug mode. */ + unsigned int curDepthBank14 : 4; /* * [27:24]Current depth of bank 14 queue. */ + unsigned int curDepthBank13 : 4; /* * [23:20]Current depth of bank 13 queue. */ + unsigned int curDepthBank12 : 4; /* * [19:16]Current depth of bank 12 queue. */ + unsigned int curDepthBank11 : 4; /* * [15:12]Current depth of bank 11 queue. */ + unsigned int curDepthBank10 : 4; /* * [11:8]Current depth of bank 10 queue. */ + unsigned int curDepthBank9 : 4; /* * [7:4]Current depth of bank 9 queue. */ + unsigned int curDepthBank8 : 4; /* * [3:0]Current depth of bank 8 queue. */ +#else + unsigned int curDepthBank8 : 4; /* * [3:0]Current depth of bank 8 queue. */ + unsigned int curDepthBank9 : 4; /* * [7:4]Current depth of bank 9 queue. */ + unsigned int curDepthBank10 : 4; /* * [11:8]Current depth of bank 10 queue. */ + unsigned int curDepthBank11 : 4; /* * [15:12]Current depth of bank 11 queue. */ + unsigned int curDepthBank12 : 4; /* * [19:16]Current depth of bank 12 queue. */ + unsigned int curDepthBank13 : 4; /* * [23:20]Current depth of bank 13 queue. */ + unsigned int curDepthBank14 : 4; /* * [27:24]Current depth of bank 14 queue. */ + unsigned int curDepthBank15 : 4; /* * [31:28]Current depth of bank 15 queue.Notice that depth of bank is up to + 15, because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for d ebug mode. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_U; + +/* ** + * Union name : SMMC_L_ECC_INJ_CFG + * @brief SMMC_L ECC inject register + * Description: + */ +typedef union tagUnSmmcLEccInjCfg { + struct tagStSmmcLEccInjCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]Reserved */ + unsigned int smmcL2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read Data memory0: disable1: + enable */ + unsigned int smmcL1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read Data memory0: disable1: + enable */ +#else + unsigned int smmcL1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read Data memory0: disable1: + enable */ + unsigned int smmcL2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read Data memory0: disable1: + enable */ + unsigned int reserved : 30; /* * [31:2]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_ECC_INJ_CFG_U; + +/* ** + * Union name : SMMC_L_PG_CFG + * @brief SMMC_L Partial Good register + * Description: + */ +typedef union tagUnSmmcLPgCfg { + struct tagStSmmcLPgCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]Reserved */ + unsigned int smmcLPgGrpNum : 1; /* * [4:4]If any group has uncorrected error, SMMC_L can support 2 groups in + paritial good mode.The number of bank group in paritial good mode:0: 4 groups/16 + banks is ena ble;1: 2 groups/8 banks is enable */ + unsigned int smmcLPgGrp0Id : 2; /* * [3:2]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 1st group ID of PG.Group 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: bank 12~15.For example, if only support group 1 and group 2, + pg_grp0_id must set to 1 and pg_grp1_id must set to 2. + */ + unsigned int smmcLPgGrp1Id : 2; /* * [1:0]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 2nd group ID of PGGroup 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: b ank 12~15 */ +#else + unsigned int smmcLPgGrp1Id : 2; /* * [1:0]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 2nd group ID of PGGroup 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: b ank 12~15 */ + unsigned int smmcLPgGrp0Id : 2; /* * [3:2]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 1st group ID of PG.Group 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: bank 12~15.For example, if only support group 1 and group 2, + pg_grp0_id must set to 1 and pg_grp1_id must set to 2. + */ + unsigned int smmcLPgGrpNum : 1; /* * [4:4]If any group has uncorrected error, SMMC_L can support 2 groups in + paritial good mode.The number of bank group in paritial good mode:0: 4 groups/16 + banks is ena ble;1: 2 groups/8 banks is enable */ + unsigned int reserved : 27; /* * [31:5]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_PG_CFG_U; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* * __cplusplus */ + +#endif /* * HI1823_CSR_SM_TYPEDEF_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hinic3_csr_addr_common.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hinic3_csr_addr_common.h new file mode 100644 index 000000000..d9ccef586 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hinic3_csr_addr_common.h @@ -0,0 +1,254 @@ +#ifndef HINIC3_CSR_ADDR_COMMON_H +#define HINIC3_CSR_ADDR_COMMON_H + + +#include "infra_pub.h" +#include "node_id.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +#define CSR_PHY_ADDR_GEN_CPB(addr) CSR_PHY_ADDR_GEN(NODE_ID_CPB, addr) +#define CSR_PHY_ADDR_GEN_QUL(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUL, addr) +#define CSR_PHY_ADDR_GEN_QUF(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUF, addr) +#define CSR_PHY_ADDR_GEN_ISCH(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUL, addr) /* iSCH use QU's Node id */ +#define CSR_PHY_ADDR_GEN_ESCH(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUL, addr) +#define CSR_PHY_ADDR_GEN_MQM(addr) CSR_PHY_ADDR_GEN(NODE_ID_MQM, addr) +#define CSR_PHY_ADDR_GEN_LCAM(addr) CSR_PHY_ADDR_GEN(NODE_ID_LCAM, addr) + +#define CSR_PHY_ADDR_GEN_TILE_L0(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L0, addr) +#define CSR_PHY_ADDR_GEN_TILE_L1(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L1, addr) +#define CSR_PHY_ADDR_GEN_TILE_L2(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L2, addr) +#define CSR_PHY_ADDR_GEN_TILE_L3(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L3, addr) + +#define CSR_PHY_ADDR_GEN_TILE_F0(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F0, addr) +#define CSR_PHY_ADDR_GEN_TILE_F1(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F1, addr) +#define CSR_PHY_ADDR_GEN_TILE_F2(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F2, addr) +#define CSR_PHY_ADDR_GEN_TILE_F3(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F3, addr) + +#define CSR_PHY_ADDR_GEN_PETX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_NETWORK, addr) +#define CSR_PHY_ADDR_GEN_PERX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_HOST, addr) + +#define CSR_PHY_ADDR_GEN_IPSUTX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_HOST, addr) +#define CSR_PHY_ADDR_GEN_IPSURX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_NETWORK, addr) + +#define CSR_PHY_ADDR_GEN_SML0(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML0, addr) +#define CSR_PHY_ADDR_GEN_SML1(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML1, addr) +#define CSR_PHY_ADDR_GEN_SML2(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML2, addr) +#define CSR_PHY_ADDR_GEN_SML3(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML3, addr) + +#define CSR_PHY_ADDR_GEN_SMF0(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF0, addr) +#define CSR_PHY_ADDR_GEN_SMF1(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF1, addr) +#define CSR_PHY_ADDR_GEN_SMF2(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF2, addr) +#define CSR_PHY_ADDR_GEN_SMF3(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF3, addr) + +#define CSR_PHY_ADDR_GEN_CRYPT(addr) CSR_PHY_ADDR_GEN(NODE_ID_CRYPTO, addr) + +#define CSR_PHY_ADDR_GEN_ROB(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) +#define CSR_PHY_ADDR_GEN_ISC(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) +#define CSR_PHY_ADDR_GEN_ESC(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) +#define CSR_PHY_ADDR_GEN_TS_TOP(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) + +#define CSR_PHY_ADDR_GEN_SM(sm_id, addr) CSR_PHY_ADDR_GEN(tool_sm_get_nodeid(sm_id), (addr)) + +/* STLIQ */ +#define IND_STLIQ_MEM_PREALLOC (6) +#define IND_STLIQ_MEM_OQID (7) +#define IND_STLIQ_MEM_PRO_TYPE (9) +#define IND_STLIQ_MEM_ICHANNEL (10) +#define IND_STLIQ_MEM_PCPTR (11) +#define IND_STLIQ_MEM_STL_EVT_ICHNL (14) +#define IND_STLIQ_MEM_STF_EVT_ICHNL (15) + +/* STFIQ */ +#define IND_STFIQ_MEM_MSG_SRV (1) +#define IND_STFIQ_MEM_ICHANNEL (3) +#define IND_STFIQ_MEM_PREALLOC (15) +#define IND_STFIQ_MEM_PCPTR (16) +#define IND_STFIQ_MEM_PCOFFSET (17) + +/* PRMTX & PRMRX */ +#define IND_PRM_G_COS_TH (0) +#define IND_PRM_G_P_TH (1) +#define IND_PRM_G_SRV_TH (2) +#define IND_PRM_Y_STF_P_TH (3) +#define IND_PRM_Y_STF_SRV_TH (4) +#define IND_PRM_R_STF_P_TH (5) +#define IND_PRM_R_STF_SRV_TH (6) +#define IND_PRM_Y_STL_P_TH (7) +#define IND_PRM_Y_STL_SRV_TH (8) +#define IND_PRM_R_STL_P_TH (9) +#define IND_PRM_R_STL_SRV_TH (10) + +/* +(Configurations) +0x0: port group threshold configure table. +0x1:red zone port configure threshold table. +0x2:yellow zone port configure threshold table. +0x3:network side port configure threshold table. +0x4:network side cos configure threshold table. +0x5 : host side EP group configure threshold table. +0x6 : host side srv group (per service) configure threshold table. +0x7 : host side port group(per host per service) configure threshold table. +0x8 : host side pri group (per cos per host per service) configure threshold table. +0x9 : host side queue group (per cos per ep for normal queues) configure threshold table. +*/ +#define IND_MEM_QU_PDM_PORT_GRP_THD_CFG_TBL (0x0) +#define IND_MEM_QU_PDM_RED_ZONE_PORT_CFG_THD_TBL (0x1) +#define IND_MEM_QU_PDM_YELLOW_ZONE_PORT_CFG_THD_TBL (0x2) +#define IND_MEM_QU_PDM_NETWORK_SIDE_PORT_CFG_THD_TBL (0x3) +#define IND_MEM_QU_PDM_NETWORK_SIDE_COS_CFG_THD_TBL (0x4) +#define IND_MEM_QU_PDM_HOST_SIDE_EP_GRP_CFG_THD_TBL (0x5) +#define IND_MEM_QU_PDM_HOST_SIDE_SRV_GRP_CFG_THD_TBL (0x6) +#define IND_MEM_QU_PDM_HOST_SIDE_PORT_GRP_CFG_THD_TBL (0x7) +#define IND_MEM_QU_PDM_HOST_SIDE_PRI_GRP_CFG_THD_TBL (0x8) +#define IND_MEM_QU_PDM_HOST_SIDE_QUE_GRP_CFG_THD_TBL (0x9) + +typedef union { + struct { + unsigned long long pg_fc_th_dif2 : 8; // [71:64] + unsigned long long pg_rsvd_th : 16; // [87:72] + unsigned long long pg_drp_th_on : 16; // [103:88] + unsigned long long pg_drp_th_dif : 8; // [111:104] + unsigned long long pg_max_sh_th : 15; // [126:112] + unsigned long long pg_sh_fc_dyn : 1; // [127] + + unsigned long long pg_fc_th_on0 : 16; // [15:0] + unsigned long long pg_fc_th_on1 : 16; // [31:16] + unsigned long long pg_fc_th_on2 : 16; // [47:32] + unsigned long long pg_fc_th_dif0 : 8; // [55:48] + unsigned long long pg_fc_th_dif1 : 8; // [63:56] + } bs; + + unsigned long long val64[2]; +} u_qu_pdm_port_grp_thd_cfg; + +/* +Red cell occupied threshold table +Yellow cell occupied threshold table +*/ +typedef union { + struct { + unsigned long long port_rsvd_th : 16; // [15:0] + unsigned long long port_bp_th_dif : 8; // [23:16] + unsigned long long port_bp_th : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_color_zone_cfg; + +/* + Network Port cell occupied threshold table Fields Definition + This table was indexed with : +" TP/Mac : {1'b0,port [3:0]}. +" Mc : 16. + +*/ +typedef union { + struct { + unsigned long long port_fc_th_dif2 : 8; // [71:64] + unsigned long long port_rsvd_th : 16; // [87:72] + unsigned long long port_drp_th_on : 16; // [103:88] + unsigned long long port_drp_th_dif : 8; // [111:104] + unsigned long long port_max_sh : 15; // [126:112] + unsigned long long port_sh_fc_dyn : 1; // [127] + + unsigned long long port_fc_th_on0 : 16; // [15:0] + unsigned long long port_fc_th_on1 : 16; // [31:16] + unsigned long long port_fc_th_on2 : 16; // [47:32] + unsigned long long port_fc_th_dif0 : 8; // [55:48] + unsigned long long port_fc_th_dif1 : 8; // [63:56] + } bs; + unsigned long long val64[2]; +} u_qu_pdm_nw_port_thd_cfg; + + +/* + Network Cos cell occupied threshold table Fields Definition + Total number : 128+2 . +" Unicast : {1'b0, port/tp[3:0], cos[2:0]} . +" Multicast(FIC): {5'h10, cos[0]}. +*/ +typedef union { + struct { + unsigned long long cos_rsvd_th : 16; // [15:0] + unsigned long long cos_sh_fc_th_dif : 8; // [23:16] + unsigned long long cos_sh_fc_th_on : 16; // [39:24] + unsigned long long cos_drp_th_dif : 8; // [47:40] + unsigned long long cos_drp_th_on : 16; // [63:48] + } bs; + unsigned long long val64; +} u_qu_pdm_nw_cos_thd_cfg; + + +/* + */ +typedef union { + struct { + unsigned long long cos_rsvd_th : 16; // [15:0] + unsigned long long cos_sh_fc_th_dif : 8; // [23:16] + unsigned long long cos_sh_fc_th_on : 16; // [39:24] + unsigned long long cos_sh_bp_th_dif : 8; // [47:40] + unsigned long long cos_sh_bp_th_on : 16; // [63:48] + } bs; + unsigned long long val64; +} u_qu_pdm_host_que_thd_cfg; + + +/* + */ +typedef union { + struct { + unsigned long long sp_rsvd_th : 16; // [15:0] + unsigned long long sp_fc_th_dif : 8; // [23:16] + unsigned long long sp_fc_th_on : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_host_pri_thd_cfg; + + +/* + */ +typedef union { + struct { + unsigned long long port_rsvd_th : 16; // [15:0] + unsigned long long port_fc_th_dif : 8; // [23:16] + unsigned long long port_fc_th_on : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_host_port_thd_cfg; + +/* + */ +typedef union { + struct { + unsigned long long sg_rsvd_th : 16; // [15:0] + unsigned long long sg_fc_th_dif : 8; // [23:16] + unsigned long long sg_fc_th_on : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_host_srv_grp_thd_cfg; + +typedef union { + struct { + unsigned int ep_bp_th_dif : 8; // [7:0] + unsigned int ep_bp_th_on : 16; // [23:8] + unsigned int rsv : 8; // [31:24] + } bs; + + unsigned int val32; +} u_qu_pdm_host_ep_grp_thd_cfg; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif /* HINIC3_CSR_ADDR_COMMON_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_c_union_define.h new file mode 100644 index 000000000..c07c6d582 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_c_union_define.h @@ -0,0 +1,1062 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : icdq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:06:21 Create file +// ****************************************************************************** + +#ifndef ICDQ_C_UNION_DEFINE_H +#define ICDQ_C_UNION_DEFINE_H + +/* Define the union csr_icdq_mode0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 8; /* [7:0] */ + u32 rsv_1 : 8; /* [15:8] */ + u32 rsv_2 : 3; /* [18:16] */ + u32 rsv_3 : 3; /* [21:19] */ + u32 csr_icdq_mem_init_start : 1; /* [22] */ + u32 csr_icdq_pru_alter_time : 1; /* [23] */ + u32 csr_icdq_mem_ecc_bypass : 1; /* [24] */ + u32 csr_icdq_ram_uncrt_err2itf_en : 1; /* [25] */ + u32 csr_icdq_other_uncrt_err2itf_en : 1; /* [26] */ + u32 csr_icdq_mem_ecc_req : 2; /* [28:27] */ + u32 csr_icdq_fqid_vf : 1; /* [29] */ + u32 csr_icdq_partial_col_max_num : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mode0_u; + +/* Define the union csr_icdq_mode1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_strong_col_max_num : 4; /* [3:0] */ + u32 csr_icdq_real_dpl_pcnum_ctrl : 1; /* [4] */ + u32 csr_icdq_fqid_0 : 1; /* [5] */ + u32 csr_icdq_lbf_mode_sel : 2; /* [7:6] */ + u32 csr_icdq_quf_pg_cfg : 2; /* [9:8] */ + u32 csr_icdq_2k_vf_mode : 1; /* [10] */ + u32 csr_icdq_wred_pps_mode : 1; /* [11] */ + u32 csr_icdq_wred_plen : 16; /* [27:12] */ + u32 rsv_4 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mode1_u; + +/* Define the union csr_icdq_wrr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_dsp_weight : 8; /* [7:0] */ + u32 csr_icdq_rxf_weight : 8; /* [15:8] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_wrr_u; + +/* Define the union csr_icdq_cfp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_cfp_num : 12; /* [11:0] */ + u32 csr_icdq_nreal_dpl_pcnum : 4; /* [15:12] */ + u32 csr_icdq_nreal_dpl_plen : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_cfp_num_u; + +/* Define the union csr_icdq_pqm_ep_bitmap0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port0_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port1_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port2_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port3_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap0_u; + +/* Define the union csr_icdq_pqm_ep_bitmap1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port4_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port5_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port6_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port7_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap1_u; + +/* Define the union csr_icdq_pqm_ep_bitmap2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port8_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port9_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port10_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port11_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap2_u; + +/* Define the union csr_icdq_pqm_ep_bitmap3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port12_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port13_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port14_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port15_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap3_u; + +/* Define the union csr_icdq_pqm_ep_bitmap4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep0_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep1_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep2_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep3_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap4_u; + +/* Define the union csr_icdq_pqm_ep_bitmap5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep4_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep5_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep6_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep7_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap5_u; + +/* Define the union csr_icdq_pqm_ep_bitmap6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep8_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep9_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep10_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep11_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap6_u; + +/* Define the union csr_icdq_pqm_ep_bitmap7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep12_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep13_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep14_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep15_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap7_u; + +/* Define the union csr_icdq_fc_pro_typ_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_fc_pro_typ : 7; /* [6:0] */ + u32 rsv_6 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_fc_pro_typ_u; + +/* Define the union csr_icdq_sfifo_af0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_stffq0_opn_af_th : 8; /* [7:0] */ + u32 sfifo_stffq1_opn_af_th : 8; /* [15:8] */ + u32 sfifo_stffq0_rls_af_th : 8; /* [23:16] */ + u32 sfifo_stffq1_rls_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_af0_u; + +/* Define the union csr_icdq_sfifo_af1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_pru_af_th : 8; /* [7:0] */ + u32 sfifo_icq_af_th : 8; /* [15:8] */ + u32 sfifo_idq_af_th : 8; /* [23:16] */ + u32 sfifo_dsp_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_af1_u; + +/* Define the union csr_icdq_sfifo_af2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_rxf_af_th : 8; /* [7:0] */ + u32 sfifo_rul_mem_cflict_af_th : 8; /* [15:8] */ + u32 sfifo_drp_af_th : 8; /* [23:16] */ + u32 sfifo_cpd_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_af2_u; + +/* Define the union csr_icdq_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_done : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mem_init_done_u; + +/* Define the union csr_icdq_wred_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_wred_drp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_wred_drop_cnt_u; + +/* Define the union csr_icdq_dsp_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_dsp_drp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_dsp_drop_cnt_u; + +/* Define the union csr_icdq_dsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_dsp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_dsp_cnt_u; + +/* Define the union csr_icdq_rxf_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_rxf_sop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_rxf_sop_cnt_u; + +/* Define the union csr_icdq_rxf_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_rxf_eop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_rxf_eop_cnt_u; + +/* Define the union csr_icdq_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pthru : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pthru_cnt_u; + +/* Define the union csr_icdq_mem_ecc_1bit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_mem_1bit_ecc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mem_ecc_1bit_cnt_u; + +/* Define the union csr_icdq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_8 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_9 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int_vector_u; + +/* Define the union csr_icdq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_10 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int_u; + +/* Define the union csr_icdq_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_11 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int_en_u; + +/* Define the union csr_icdq_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_deq_abnml : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 icdq_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int0_sticky_u; + +/* Define the union csr_icdq_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_fifo_overflow : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 icdq_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int1_sticky_u; + +/* Define the union csr_icdq_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_fifo_underflow : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 icdq_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int2_sticky_u; + +/* Define the union csr_icdq_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_2bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 icdq_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int3_sticky_u; + +/* Define the union csr_icdq_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 icdq_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int4_sticky_u; + +/* Define the union csr_icdq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_ctrl_u; + +/* Define the union csr_icdq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_timeout_u; + +/* Define the union csr_icdq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat0_u; + +/* Define the union csr_icdq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat1_u; + +/* Define the union csr_icdq_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat2_u; + +/* Define the union csr_icdq_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat3_u; + +/* Define the union csr_icdq_indrect_dat4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat4_u; + +/* Define the union csr_icdq_indrect_dat5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat5_u; + +/* Define the union csr_icdq_indrect_dat6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat6_u; + +/* Define the union csr_icdq_indrect_dat7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat7_u; + +/* Define the union csr_icdq_indrect_dat8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat8_u; + +/* Define the union csr_icdq_indrect_dat9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat9_u; + +/* Define the union csr_icdq_indrect_dat10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat10_u; + +/* Define the union csr_icdq_indrect_dat11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat11_u; + +/* Define the union csr_icdq_indrect_dat12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat12_u; + +/* Define the union csr_icdq_indrect_dat13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat13_u; + +/* Define the union csr_icdq_indrect_dat14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat14_u; + +/* Define the union csr_icdq_indrect_dat15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat15_u; + +/* Define the union csr_icdq_sfifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_stffq0_opn_fill : 8; /* [7:0] */ + u32 sfifo_stffq1_opn_fill : 8; /* [15:8] */ + u32 sfifo_stffq0_rls_fill : 8; /* [23:16] */ + u32 sfifo_stffq1_rls_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_fill0_u; + +/* Define the union csr_icdq_sfifo_fill1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_pru_fill : 8; /* [7:0] */ + u32 sfifo_icq_fill : 8; /* [15:8] */ + u32 sfifo_idq_fill : 8; /* [23:16] */ + u32 sfifo_dsp_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_fill1_u; + +/* Define the union csr_icdq_sfifo_fill2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_rxf_fill : 8; /* [7:0] */ + u32 sfifo_rul_mem_cflict_fill : 8; /* [15:8] */ + u32 sfifo_drp_fill : 8; /* [23:16] */ + u32 sfifo_cpd_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_fill2_u; + +/* Define the union csr_icdq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_sample_mode : 1; /* [0] */ + u32 csr_icdq_spec_port_en : 1; /* [1] */ + u32 csr_icdq_done_clr : 1; /* [2] */ + u32 rsv_12 : 1; /* [3] */ + u32 csr_icdq_spec_port_num : 4; /* [7:4] */ + u32 csr_icdq_spec_pptr_typ : 8; /* [15:8] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_latency_cfg_u; + +/* Define the union csr_icdq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_sample_done : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_latency_sta_u; + +/* Define the union csr_icdq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sample_tmr_u; + +/* Define the union csr_icdq_bp0_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_stlfq_dsp_bp : 1; /* [0] */ + u32 icdq_stffq0_opn_bp : 1; /* [1] */ + u32 icdq_stffq1_opn_bp : 1; /* [2] */ + u32 icdq_stffq0_rls_bp : 1; /* [3] */ + u32 icdq_stffq1_rls_bp : 1; /* [4] */ + u32 stfiq_icdq_sqr_bp : 1; /* [5] */ + u32 icdq_csr_opn_icq_bp : 1; /* [6] */ + u32 icdq_csr_opn_idq_bp : 1; /* [7] */ + u32 icdq_csr_ele_icq_bp : 1; /* [8] */ + u32 rsv_15 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_bp0_sta_u; + +/* Define the union csr_icdq_bp1_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_sqd_ep_bp : 16; /* [15:0] */ + u32 icdq_csr_sqd_port_bp : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_bp1_sta_u; + +/* Define the union csr_icdq_pqm_eqs_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_eqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_eqs_num_u; + +/* Define the union csr_icdq_pqm_dqr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_dqr_num_u; + +/* Define the union csr_icdq_pqm_dqs_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_dqs_num_u; + +/* Define the union csr_icdq_pqm_dpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_dpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_dpl_num_u; + +/* Define the union csr_icdq_stfiq_enqx_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_stfiq_enqx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_stfiq_enqx_num_u; + +/* Define the union csr_icdq_stfiq_enqy_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_stfiq_enqy_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_stfiq_enqy_num_u; + +/* Define the union csr_icdq_cfp_dqr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_cfp_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_cfp_dqr_num_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_icdq_mode0_u icdq_mode0; /* 0 */ + volatile csr_icdq_mode1_u icdq_mode1; /* 4 */ + volatile csr_icdq_wrr_u icdq_wrr; /* 8 */ + volatile csr_icdq_cfp_num_u icdq_cfp_num; /* C */ + volatile csr_icdq_pqm_ep_bitmap0_u icdq_pqm_ep_bitmap0; /* 10 */ + volatile csr_icdq_pqm_ep_bitmap1_u icdq_pqm_ep_bitmap1; /* 14 */ + volatile csr_icdq_pqm_ep_bitmap2_u icdq_pqm_ep_bitmap2; /* 18 */ + volatile csr_icdq_pqm_ep_bitmap3_u icdq_pqm_ep_bitmap3; /* 1C */ + volatile csr_icdq_pqm_ep_bitmap4_u icdq_pqm_ep_bitmap4; /* 20 */ + volatile csr_icdq_pqm_ep_bitmap5_u icdq_pqm_ep_bitmap5; /* 24 */ + volatile csr_icdq_pqm_ep_bitmap6_u icdq_pqm_ep_bitmap6; /* 28 */ + volatile csr_icdq_pqm_ep_bitmap7_u icdq_pqm_ep_bitmap7; /* 2C */ + volatile csr_icdq_fc_pro_typ_u icdq_fc_pro_typ; /* 30 */ + volatile csr_icdq_sfifo_af0_u icdq_sfifo_af0; /* 34 */ + volatile csr_icdq_sfifo_af1_u icdq_sfifo_af1; /* 38 */ + volatile csr_icdq_sfifo_af2_u icdq_sfifo_af2; /* 3C */ + volatile csr_icdq_mem_init_done_u icdq_mem_init_done; /* 40 */ + volatile csr_icdq_wred_drop_cnt_u icdq_wred_drop_cnt; /* 44 */ + volatile csr_icdq_dsp_drop_cnt_u icdq_dsp_drop_cnt; /* 48 */ + volatile csr_icdq_dsp_cnt_u icdq_dsp_cnt; /* 4C */ + volatile csr_icdq_rxf_sop_cnt_u icdq_rxf_sop_cnt; /* 50 */ + volatile csr_icdq_rxf_eop_cnt_u icdq_rxf_eop_cnt; /* 54 */ + volatile csr_icdq_pthru_cnt_u icdq_pthru_cnt; /* 58 */ + volatile csr_icdq_mem_ecc_1bit_cnt_u icdq_mem_ecc_1bit_cnt; /* 5C */ + volatile csr_icdq_int_vector_u icdq_int_vector; /* 60 */ + volatile csr_icdq_int_u icdq_int; /* 64 */ + volatile csr_icdq_int_en_u icdq_int_en; /* 68 */ + volatile csr_icdq_int0_sticky_u icdq_int0_sticky; /* 6C */ + volatile csr_icdq_int1_sticky_u icdq_int1_sticky; /* 70 */ + volatile csr_icdq_int2_sticky_u icdq_int2_sticky; /* 74 */ + volatile csr_icdq_int3_sticky_u icdq_int3_sticky; /* 78 */ + volatile csr_icdq_int4_sticky_u icdq_int4_sticky; /* 7C */ + volatile csr_icdq_indrect_ctrl_u icdq_indrect_ctrl; /* 80 */ + volatile csr_icdq_indrect_timeout_u icdq_indrect_timeout; /* 84 */ + volatile csr_icdq_indrect_dat0_u icdq_indrect_dat0; /* 88 */ + volatile csr_icdq_indrect_dat1_u icdq_indrect_dat1; /* 8C */ + volatile csr_icdq_indrect_dat2_u icdq_indrect_dat2; /* 90 */ + volatile csr_icdq_indrect_dat3_u icdq_indrect_dat3; /* 94 */ + volatile csr_icdq_indrect_dat4_u icdq_indrect_dat4; /* 98 */ + volatile csr_icdq_indrect_dat5_u icdq_indrect_dat5; /* 9C */ + volatile csr_icdq_indrect_dat6_u icdq_indrect_dat6; /* A0 */ + volatile csr_icdq_indrect_dat7_u icdq_indrect_dat7; /* A4 */ + volatile csr_icdq_indrect_dat8_u icdq_indrect_dat8; /* A8 */ + volatile csr_icdq_indrect_dat9_u icdq_indrect_dat9; /* AC */ + volatile csr_icdq_indrect_dat10_u icdq_indrect_dat10; /* B0 */ + volatile csr_icdq_indrect_dat11_u icdq_indrect_dat11; /* B4 */ + volatile csr_icdq_indrect_dat12_u icdq_indrect_dat12; /* B8 */ + volatile csr_icdq_indrect_dat13_u icdq_indrect_dat13; /* BC */ + volatile csr_icdq_indrect_dat14_u icdq_indrect_dat14; /* C0 */ + volatile csr_icdq_indrect_dat15_u icdq_indrect_dat15; /* C4 */ + volatile csr_icdq_sfifo_fill0_u icdq_sfifo_fill0; /* C8 */ + volatile csr_icdq_sfifo_fill1_u icdq_sfifo_fill1; /* CC */ + volatile csr_icdq_sfifo_fill2_u icdq_sfifo_fill2; /* D0 */ + volatile csr_icdq_latency_cfg_u icdq_latency_cfg; /* D4 */ + volatile csr_icdq_latency_sta_u icdq_latency_sta; /* D8 */ + volatile csr_icdq_sample_tmr_u icdq_sample_tmr; /* DC */ + volatile csr_icdq_bp0_sta_u icdq_bp0_sta; /* E0 */ + volatile csr_icdq_bp1_sta_u icdq_bp1_sta; /* E4 */ + volatile csr_icdq_pqm_eqs_num_u icdq_pqm_eqs_num; /* E8 */ + volatile csr_icdq_pqm_dqr_num_u icdq_pqm_dqr_num; /* EC */ + volatile csr_icdq_pqm_dqs_num_u icdq_pqm_dqs_num; /* F0 */ + volatile csr_icdq_pqm_dpl_num_u icdq_pqm_dpl_num; /* F4 */ + volatile csr_icdq_stfiq_enqx_num_u icdq_stfiq_enqx_num; /* F8 */ + volatile csr_icdq_stfiq_enqy_num_u icdq_stfiq_enqy_num; /* FC */ + volatile csr_icdq_cfp_dqr_num_u icdq_cfp_dqr_num; /* 100 */ +} S_qu_icdq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_icdq_csr */ +extern volatile S_qu_icdq_csr_REGS_TYPE *gopqu_icdq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetICDQ_MODE0_csr_icdq_mem_init_start(unsigned int ucsr_icdq_mem_init_start); +int iSetICDQ_MODE0_csr_icdq_pru_alter_time(unsigned int ucsr_icdq_pru_alter_time); +int iSetICDQ_MODE0_csr_icdq_mem_ecc_bypass(unsigned int ucsr_icdq_mem_ecc_bypass); +int iSetICDQ_MODE0_csr_icdq_ram_uncrt_err2itf_en(unsigned int ucsr_icdq_ram_uncrt_err2itf_en); +int iSetICDQ_MODE0_csr_icdq_other_uncrt_err2itf_en(unsigned int ucsr_icdq_other_uncrt_err2itf_en); +int iSetICDQ_MODE0_csr_icdq_mem_ecc_req(unsigned int ucsr_icdq_mem_ecc_req); +int iSetICDQ_MODE0_csr_icdq_fqid_vf(unsigned int ucsr_icdq_fqid_vf); +int iSetICDQ_MODE0_csr_icdq_partial_col_max_num(unsigned int ucsr_icdq_partial_col_max_num); +int iSetICDQ_MODE1_csr_icdq_strong_col_max_num(unsigned int ucsr_icdq_strong_col_max_num); +int iSetICDQ_MODE1_csr_icdq_real_dpl_pcnum_ctrl(unsigned int ucsr_icdq_real_dpl_pcnum_ctrl); +int iSetICDQ_MODE1_csr_icdq_fqid_0(unsigned int ucsr_icdq_fqid_0); +int iSetICDQ_MODE1_csr_icdq_lbf_mode_sel(unsigned int ucsr_icdq_lbf_mode_sel); +int iSetICDQ_MODE1_csr_icdq_quf_pg_cfg(unsigned int ucsr_icdq_quf_pg_cfg); +int iSetICDQ_MODE1_csr_icdq_2k_vf_mode(unsigned int ucsr_icdq_2k_vf_mode); +int iSetICDQ_MODE1_csr_icdq_wred_pps_mode(unsigned int ucsr_icdq_wred_pps_mode); +int iSetICDQ_MODE1_csr_icdq_wred_plen(unsigned int ucsr_icdq_wred_plen); +int iSetICDQ_WRR_csr_icdq_dsp_weight(unsigned int ucsr_icdq_dsp_weight); +int iSetICDQ_WRR_csr_icdq_rxf_weight(unsigned int ucsr_icdq_rxf_weight); +int iSetICDQ_CFP_NUM_csr_icdq_cfp_num(unsigned int ucsr_icdq_cfp_num); +int iSetICDQ_CFP_NUM_csr_icdq_nreal_dpl_pcnum(unsigned int ucsr_icdq_nreal_dpl_pcnum); +int iSetICDQ_CFP_NUM_csr_icdq_nreal_dpl_plen(unsigned int ucsr_icdq_nreal_dpl_plen); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port0_2_ep_bm(unsigned int ucsr_icdq_port0_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port1_2_ep_bm(unsigned int ucsr_icdq_port1_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port2_2_ep_bm(unsigned int ucsr_icdq_port2_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port3_2_ep_bm(unsigned int ucsr_icdq_port3_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port4_2_ep_bm(unsigned int ucsr_icdq_port4_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port5_2_ep_bm(unsigned int ucsr_icdq_port5_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port6_2_ep_bm(unsigned int ucsr_icdq_port6_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port7_2_ep_bm(unsigned int ucsr_icdq_port7_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port8_2_ep_bm(unsigned int ucsr_icdq_port8_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port9_2_ep_bm(unsigned int ucsr_icdq_port9_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port10_2_ep_bm(unsigned int ucsr_icdq_port10_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port11_2_ep_bm(unsigned int ucsr_icdq_port11_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port12_2_ep_bm(unsigned int ucsr_icdq_port12_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port13_2_ep_bm(unsigned int ucsr_icdq_port13_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port14_2_ep_bm(unsigned int ucsr_icdq_port14_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port15_2_ep_bm(unsigned int ucsr_icdq_port15_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep0_2_ep_bm(unsigned int ucsr_icdq_ep0_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep1_2_ep_bm(unsigned int ucsr_icdq_ep1_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep2_2_ep_bm(unsigned int ucsr_icdq_ep2_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep3_2_ep_bm(unsigned int ucsr_icdq_ep3_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep4_2_ep_bm(unsigned int ucsr_icdq_ep4_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep5_2_ep_bm(unsigned int ucsr_icdq_ep5_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep6_2_ep_bm(unsigned int ucsr_icdq_ep6_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep7_2_ep_bm(unsigned int ucsr_icdq_ep7_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep8_2_ep_bm(unsigned int ucsr_icdq_ep8_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep9_2_ep_bm(unsigned int ucsr_icdq_ep9_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep10_2_ep_bm(unsigned int ucsr_icdq_ep10_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep11_2_ep_bm(unsigned int ucsr_icdq_ep11_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep12_2_ep_bm(unsigned int ucsr_icdq_ep12_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep13_2_ep_bm(unsigned int ucsr_icdq_ep13_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep14_2_ep_bm(unsigned int ucsr_icdq_ep14_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep15_2_ep_bm(unsigned int ucsr_icdq_ep15_2_ep_bm); +int iSetICDQ_FC_PRO_TYP_csr_icdq_fc_pro_typ(unsigned int ucsr_icdq_fc_pro_typ); +int iSetICDQ_SFIFO_AF0_sfifo_stffq0_opn_af_th(unsigned int usfifo_stffq0_opn_af_th); +int iSetICDQ_SFIFO_AF0_sfifo_stffq1_opn_af_th(unsigned int usfifo_stffq1_opn_af_th); +int iSetICDQ_SFIFO_AF0_sfifo_stffq0_rls_af_th(unsigned int usfifo_stffq0_rls_af_th); +int iSetICDQ_SFIFO_AF0_sfifo_stffq1_rls_af_th(unsigned int usfifo_stffq1_rls_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_pru_af_th(unsigned int usfifo_pru_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_icq_af_th(unsigned int usfifo_icq_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_idq_af_th(unsigned int usfifo_idq_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_dsp_af_th(unsigned int usfifo_dsp_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_rxf_af_th(unsigned int usfifo_rxf_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_rul_mem_cflict_af_th(unsigned int usfifo_rul_mem_cflict_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_drp_af_th(unsigned int usfifo_drp_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_cpd_af_th(unsigned int usfifo_cpd_af_th); +int iSetICDQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done); +int iSetICDQ_WRED_DROP_CNT_icdq_csr_wred_drp(unsigned int uicdq_csr_wred_drp); +int iSetICDQ_DSP_DROP_CNT_icdq_csr_dsp_drp(unsigned int uicdq_csr_dsp_drp); +int iSetICDQ_DSP_CNT_icdq_csr_dsp(unsigned int uicdq_csr_dsp); +int iSetICDQ_RXF_SOP_CNT_icdq_csr_rxf_sop(unsigned int uicdq_csr_rxf_sop); +int iSetICDQ_RXF_EOP_CNT_icdq_csr_rxf_eop(unsigned int uicdq_csr_rxf_eop); +int iSetICDQ_PTHRU_CNT_icdq_csr_pthru(unsigned int uicdq_csr_pthru); +int iSetICDQ_MEM_ECC_1BIT_CNT_icdq_csr_mem_1bit_ecc(unsigned int uicdq_csr_mem_1bit_ecc); +int iSetICDQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetICDQ_INT_VECTOR_enable(unsigned int uenable); +int iSetICDQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetICDQ_INT_int_data(unsigned int uint_data); +int iSetICDQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetICDQ_INT_EN_int_en(unsigned int uint_en); +int iSetICDQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetICDQ_INT0_STICKY_icdq_deq_abnml(unsigned int uicdq_deq_abnml); +int iSetICDQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetICDQ_INT0_STICKY_icdq_int0_sticky(unsigned int uicdq_int0_sticky); +int iSetICDQ_INT1_STICKY_icdq_fifo_overflow(unsigned int uicdq_fifo_overflow); +int iSetICDQ_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetICDQ_INT1_STICKY_icdq_int1_sticky(unsigned int uicdq_int1_sticky); +int iSetICDQ_INT2_STICKY_icdq_fifo_underflow(unsigned int uicdq_fifo_underflow); +int iSetICDQ_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetICDQ_INT2_STICKY_icdq_int2_sticky(unsigned int uicdq_int2_sticky); +int iSetICDQ_INT3_STICKY_mem_ecc_2bit(unsigned int umem_ecc_2bit); +int iSetICDQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetICDQ_INT3_STICKY_icdq_int3_sticky(unsigned int uicdq_int3_sticky); +int iSetICDQ_INT4_STICKY_mem_ecc_1bit(unsigned int umem_ecc_1bit); +int iSetICDQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4); +int iSetICDQ_INT4_STICKY_icdq_int4_sticky(unsigned int uicdq_int4_sticky); +int iSetICDQ_INDRECT_CTRL_csr_icdq_indrect_ctrl(unsigned int ucsr_icdq_indrect_ctrl); +int iSetICDQ_INDRECT_TIMEOUT_csr_icdq_indrect_timeout(unsigned int ucsr_icdq_indrect_timeout); +int iSetICDQ_INDRECT_DAT0_csr_icdq_indrect_data0(unsigned int ucsr_icdq_indrect_data0); +int iSetICDQ_INDRECT_DAT1_csr_icdq_indrect_data1(unsigned int ucsr_icdq_indrect_data1); +int iSetICDQ_INDRECT_DAT2_csr_icdq_indrect_data2(unsigned int ucsr_icdq_indrect_data2); +int iSetICDQ_INDRECT_DAT3_csr_icdq_indrect_data3(unsigned int ucsr_icdq_indrect_data3); +int iSetICDQ_INDRECT_DAT4_csr_icdq_indrect_data4(unsigned int ucsr_icdq_indrect_data4); +int iSetICDQ_INDRECT_DAT5_csr_icdq_indrect_data5(unsigned int ucsr_icdq_indrect_data5); +int iSetICDQ_INDRECT_DAT6_csr_icdq_indrect_data6(unsigned int ucsr_icdq_indrect_data6); +int iSetICDQ_INDRECT_DAT7_csr_icdq_indrect_data7(unsigned int ucsr_icdq_indrect_data7); +int iSetICDQ_INDRECT_DAT8_csr_icdq_indrect_data8(unsigned int ucsr_icdq_indrect_data8); +int iSetICDQ_INDRECT_DAT9_csr_icdq_indrect_data9(unsigned int ucsr_icdq_indrect_data9); +int iSetICDQ_INDRECT_DAT10_csr_icdq_indrect_data10(unsigned int ucsr_icdq_indrect_data10); +int iSetICDQ_INDRECT_DAT11_csr_icdq_indrect_data11(unsigned int ucsr_icdq_indrect_data11); +int iSetICDQ_INDRECT_DAT12_csr_icdq_indrect_data12(unsigned int ucsr_icdq_indrect_data12); +int iSetICDQ_INDRECT_DAT13_csr_icdq_indrect_data13(unsigned int ucsr_icdq_indrect_data13); +int iSetICDQ_INDRECT_DAT14_csr_icdq_indrect_data14(unsigned int ucsr_icdq_indrect_data14); +int iSetICDQ_INDRECT_DAT15_csr_icdq_indrect_data15(unsigned int ucsr_icdq_indrect_data15); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq0_opn_fill(unsigned int usfifo_stffq0_opn_fill); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq1_opn_fill(unsigned int usfifo_stffq1_opn_fill); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq0_rls_fill(unsigned int usfifo_stffq0_rls_fill); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq1_rls_fill(unsigned int usfifo_stffq1_rls_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_pru_fill(unsigned int usfifo_pru_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_icq_fill(unsigned int usfifo_icq_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_idq_fill(unsigned int usfifo_idq_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_dsp_fill(unsigned int usfifo_dsp_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_rxf_fill(unsigned int usfifo_rxf_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_rul_mem_cflict_fill(unsigned int usfifo_rul_mem_cflict_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_drp_fill(unsigned int usfifo_drp_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_cpd_fill(unsigned int usfifo_cpd_fill); +int iSetICDQ_LATENCY_CFG_csr_icdq_sample_mode(unsigned int ucsr_icdq_sample_mode); +int iSetICDQ_LATENCY_CFG_csr_icdq_spec_port_en(unsigned int ucsr_icdq_spec_port_en); +int iSetICDQ_LATENCY_CFG_csr_icdq_done_clr(unsigned int ucsr_icdq_done_clr); +int iSetICDQ_LATENCY_CFG_csr_icdq_spec_port_num(unsigned int ucsr_icdq_spec_port_num); +int iSetICDQ_LATENCY_CFG_csr_icdq_spec_pptr_typ(unsigned int ucsr_icdq_spec_pptr_typ); +int iSetICDQ_LATENCY_STA_icdq_csr_sample_done(unsigned int uicdq_csr_sample_done); +int iSetICDQ_SAMPLE_TMR_icdq_csr_sample_tmr(unsigned int uicdq_csr_sample_tmr); +int iSetICDQ_BP0_STA_icdq_stlfq_dsp_bp(unsigned int uicdq_stlfq_dsp_bp); +int iSetICDQ_BP0_STA_icdq_stffq0_opn_bp(unsigned int uicdq_stffq0_opn_bp); +int iSetICDQ_BP0_STA_icdq_stffq1_opn_bp(unsigned int uicdq_stffq1_opn_bp); +int iSetICDQ_BP0_STA_icdq_stffq0_rls_bp(unsigned int uicdq_stffq0_rls_bp); +int iSetICDQ_BP0_STA_icdq_stffq1_rls_bp(unsigned int uicdq_stffq1_rls_bp); +int iSetICDQ_BP0_STA_stfiq_icdq_sqr_bp(unsigned int ustfiq_icdq_sqr_bp); +int iSetICDQ_BP0_STA_icdq_csr_opn_icq_bp(unsigned int uicdq_csr_opn_icq_bp); +int iSetICDQ_BP0_STA_icdq_csr_opn_idq_bp(unsigned int uicdq_csr_opn_idq_bp); +int iSetICDQ_BP0_STA_icdq_csr_ele_icq_bp(unsigned int uicdq_csr_ele_icq_bp); +int iSetICDQ_BP1_STA_icdq_csr_sqd_ep_bp(unsigned int uicdq_csr_sqd_ep_bp); +int iSetICDQ_BP1_STA_icdq_csr_sqd_port_bp(unsigned int uicdq_csr_sqd_port_bp); +int iSetICDQ_PQM_EQS_NUM_icdq_csr_pqm_eqs_cnt(unsigned int uicdq_csr_pqm_eqs_cnt); +int iSetICDQ_PQM_DQR_NUM_icdq_csr_pqm_dqr_cnt(unsigned int uicdq_csr_pqm_dqr_cnt); +int iSetICDQ_PQM_DQS_NUM_icdq_csr_pqm_dqs_cnt(unsigned int uicdq_csr_pqm_dqs_cnt); +int iSetICDQ_PQM_DPL_NUM_icdq_csr_pqm_dpl_cnt(unsigned int uicdq_csr_pqm_dpl_cnt); +int iSetICDQ_STFIQ_ENQX_NUM_icdq_csr_stfiq_enqx_cnt(unsigned int uicdq_csr_stfiq_enqx_cnt); +int iSetICDQ_STFIQ_ENQY_NUM_icdq_csr_stfiq_enqy_cnt(unsigned int uicdq_csr_stfiq_enqy_cnt); +int iSetICDQ_CFP_DQR_NUM_icdq_csr_cfp_dqr_cnt(unsigned int uicdq_csr_cfp_dqr_cnt); + + +#endif // ICDQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_reg_offset.h new file mode 100644 index 000000000..cf46fb517 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_reg_offset.h @@ -0,0 +1,114 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : icdq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:06:21 Create file +// ****************************************************************************** + +#ifndef ICDQ_REG_OFFSET_H +#define ICDQ_REG_OFFSET_H + +/* QU_ICDQ_CSR Base address of Module's Register */ +#define CSR_QU_ICDQ_CSR_BASE (0xA000) + +/* **************************************************************************** */ +/* QU_ICDQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_ICDQ_CSR_ICDQ_MODE0_REG (CSR_QU_ICDQ_CSR_BASE + 0x0) /* 模式配置寄存器 */ +#define CSR_QU_ICDQ_CSR_ICDQ_MODE1_REG (CSR_QU_ICDQ_CSR_BASE + 0x4) /* 模式配置寄存器 */ +#define CSR_QU_ICDQ_CSR_ICDQ_WRR_REG (CSR_QU_ICDQ_CSR_BASE + 0x8) /* rx fastpath与stl tile normalpath的权重配置 */ +#define CSR_QU_ICDQ_CSR_ICDQ_CFP_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xC) /* 发往网络侧或不需要PQM调度的ICQ的个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP0_REG (CSR_QU_ICDQ_CSR_BASE + 0x10) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP1_REG (CSR_QU_ICDQ_CSR_BASE + 0x14) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP2_REG (CSR_QU_ICDQ_CSR_BASE + 0x18) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP3_REG (CSR_QU_ICDQ_CSR_BASE + 0x1C) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP4_REG (CSR_QU_ICDQ_CSR_BASE + 0x20) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP5_REG (CSR_QU_ICDQ_CSR_BASE + 0x24) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP6_REG (CSR_QU_ICDQ_CSR_BASE + 0x28) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP7_REG (CSR_QU_ICDQ_CSR_BASE + 0x2C) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_FC_PRO_TYP_REG (CSR_QU_ICDQ_CSR_BASE + 0x30) /* fc协议的Pro_typ值 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_AF0_REG (CSR_QU_ICDQ_CSR_BASE + 0x34) /* FIFO几乎满配置。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_AF1_REG (CSR_QU_ICDQ_CSR_BASE + 0x38) /* FIFO几乎满配置。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_AF2_REG (CSR_QU_ICDQ_CSR_BASE + 0x3C) /* FIFO几乎满配置。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_MEM_INIT_DONE_REG (CSR_QU_ICDQ_CSR_BASE + 0x40) /* 表项初始化完成。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_WRED_DROP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x44) /* 源网络侧报文WRED丢弃次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_DSP_DROP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x48) /* 微码DSP时丢弃报文次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_DSP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x4C) /* 微码DSP报文次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_RXF_SOP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x50) /* 源网络侧报文SOP次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_RXF_EOP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x54) /* 源网络侧报文EOP次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PTHRU_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x58) /* 被ICDQ PTHRU的报文个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_MEM_ECC_1BIT_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x5C) /* ICDQ内部RAM发生1BIT ECC的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT_VECTOR_REG (CSR_QU_ICDQ_CSR_BASE + 0x60) /* 中断向量 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT_REG (CSR_QU_ICDQ_CSR_BASE + 0x64) /* 中断状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT_EN_REG (CSR_QU_ICDQ_CSR_BASE + 0x68) /* 中断屏蔽 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT0_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x6C) /* 中断0的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT1_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x70) /* 中断1的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT2_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x74) /* 中断2的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT3_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x78) /* 中断3的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT4_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x7C) /* 中断4的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_CTRL_REG (CSR_QU_ICDQ_CSR_BASE + 0x80) /* ICDQ间接寻址控制寄存器 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_TIMEOUT_REG (CSR_QU_ICDQ_CSR_BASE + 0x84) /* IQ间接寻址Timeout水线配置 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT0_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x88) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT1_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x8C) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT2_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x90) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT3_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x94) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT4_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x98) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT5_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x9C) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT6_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xA0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT7_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xA4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT8_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xA8) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT9_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xAC) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT10_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xB0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT11_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xB4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT12_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xB8) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT13_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xBC) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT14_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xC0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT15_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xC4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_FILL0_REG (CSR_QU_ICDQ_CSR_BASE + 0xC8) /* FIFO内数据个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_FILL1_REG (CSR_QU_ICDQ_CSR_BASE + 0xCC) /* FIFO内数据个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_FILL2_REG (CSR_QU_ICDQ_CSR_BASE + 0xD0) /* FIFO内数据个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_LATENCY_CFG_REG (CSR_QU_ICDQ_CSR_BASE + 0xD4) /* ICDQ的时延采样DFX配置 */ +#define CSR_QU_ICDQ_CSR_ICDQ_LATENCY_STA_REG (CSR_QU_ICDQ_CSR_BASE + 0xD8) /* icdq的时延采样DFX状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SAMPLE_TMR_REG (CSR_QU_ICDQ_CSR_BASE + 0xDC) /* icdq的时延采样DFX时间 */ +#define CSR_QU_ICDQ_CSR_ICDQ_BP0_STA_REG (CSR_QU_ICDQ_CSR_BASE + 0xE0) /* icdq外围接口反压状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_BP1_STA_REG (CSR_QU_ICDQ_CSR_BASE + 0xE4) /* icdq外围接口反压状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EQS_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xE8) /* icdq向PQM提调度请求的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_DQR_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xEC) /* PQM向icdq发起调度的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_DQS_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xF0) /* icdq向PQM返回队列状态的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_DPL_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xF4) /* icdq向PQM返回队列状态的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_STFIQ_ENQX_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xF8) /* icdq向STFIQ入队X链的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_STFIQ_ENQY_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xFC) /* icdq向STFIQ入队Y链的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_CFP_DQR_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0x100) /* CFP调度器(非PQM)向icdq发起调度的次数 */ + +#endif // ICDQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_c_union_define.h new file mode 100644 index 000000000..af82b16ce --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_c_union_define.h @@ -0,0 +1,4805 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_typedef.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2020/01/20 11:20:16 Create file +// ****************************************************************************** + +#ifndef IPSURX_C_UNION_DEFINE_H +#define IPSURX_C_UNION_DEFINE_H + +/* Define the union csr_ipsurx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fpga_ver_u; + +/* Define the union csr_ipsurx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_emu_ver_u; + +/* Define the union csr_ipsurx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_init_start : 1; /* [0] */ + u32 rsv_0 : 2; /* [2:1] */ + u32 ipsurx_roceop_init_start : 1; /* [3] */ + u32 rsv_1 : 2; /* [5:4] */ + u32 ipsurx_vfidx_init_start : 1; /* [6] */ + u32 ipsurx_vftb_init_start : 1; /* [7] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_initctab_start_u; + +/* Define the union csr_ipsurx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_init_done : 1; /* [0] */ + u32 rsv_3 : 2; /* [2:1] */ + u32 ipsurx_roceop_init_done : 1; /* [3] */ + u32 rsv_4 : 2; /* [5:4] */ + u32 ipsurx_vfidx_init_done : 1; /* [6] */ + u32 ipsurx_vftb_init_done : 1; /* [7] */ + u32 rsv_5 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_initctab_done_u; + +/* Define the union csr_ipsurx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_6 : 3; /* [26:24] */ + u32 ipsurx_int_enable : 1; /* [27] */ + u32 ipsurx_int_issue : 1; /* [28] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_vector_u; + +/* Define the union csr_ipsurx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_int_data : 6; /* [5:0] */ + u32 rsv_8 : 10; /* [15:6] */ + u32 ipsurx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_u; + +/* Define the union csr_ipsurx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_int_en : 6; /* [5:0] */ + u32 rsv_9 : 10; /* [15:6] */ + u32 ipsurx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_en_u; + +/* Define the union csr_ipsurx_ch_invld_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_invld_err : 1; /* [0] */ + u32 ipsurx_ch_invld_err_insrt : 1; /* [1] */ + u32 ipsurx_ch_invld_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ch_invld_err_u; + +/* Define the union csr_ipsurx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ucerr : 1; /* [0] */ + u32 ipsurx_ram_ucerr_insrt : 1; /* [1] */ + u32 ipsurx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ucerr_u; + +/* Define the union csr_ipsurx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_cerr : 1; /* [0] */ + u32 ipsurx_ram_cerr_insrt : 1; /* [1] */ + u32 ipsurx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_cerr_u; + +/* Define the union csr_ipsurx_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fifo_of_err : 1; /* [0] */ + u32 ipsurx_fifo_of_err_insrt : 1; /* [1] */ + u32 ipsurx_fifo_of_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_of_err_u; + +/* Define the union csr_ipsurx_sop_eop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sop_eop_err : 1; /* [0] */ + u32 ipsurx_sop_eop_err_insrt : 1; /* [1] */ + u32 ipsurx_sop_eop_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sop_eop_err_u; + +/* Define the union csr_ipsurx_parse_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_parse_err : 1; /* [0] */ + u32 ipsurx_parse_err_insrt : 1; /* [1] */ + u32 ipsurx_parse_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_parse_err_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw3_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw2_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw1_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw0_u; + +/* Define the union csr_ipsurx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_indrect_addr : 24; /* [23:0] */ + u32 ipsurx_indrect_tab : 4; /* [27:24] */ + u32 ipsurx_indrect_stat : 2; /* [29:28] */ + u32 ipsurx_indrect_mode : 1; /* [30] */ + u32 ipsurx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_indrect_ctrl_u; + +/* Define the union csr_ipsurx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_indrect_timeout_u; + +/* Define the union csr_ipsurx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_indrect_data_u; + +/* Define the union csr_ipsurx_cat_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_cvlan_tpid_sel : 5; /* [4:0] */ + u32 ipsurx_ch_cvlan : 1; /* [5] */ + u32 rsv_10 : 1; /* [6] */ + u32 ipsurx_ch_svlan_tpid_sel : 5; /* [11:7] */ + u32 ipsurx_ch_svlan : 1; /* [12] */ + u32 ipsurx_ch_dflt_vlan_ins : 1; /* [13] */ + u32 rsv_11 : 1; /* [14] */ + u32 ipsurx_ch_dsatag : 1; /* [15] */ + u32 ipsurx_ch_evtag_tpid_sel : 4; /* [19:16] */ + u32 ipsurx_ch_evtag : 2; /* [21:20] */ + u32 rsv_12 : 2; /* [23:22] */ + u32 ipsurx_ch_cpt_port_ctrl : 1; /* [24] */ + u32 ipsurx_ch_unknown_tag_en : 1; /* [25] */ + u32 ipsurx_ch_telemetry_en : 1; /* [26] */ + u32 ipsurx_ch_hcap_en : 1; /* [27] */ + u32 ipsurx_ch_1588v2_en : 1; /* [28] */ + u32 ipsurx_ch_type : 2; /* [30:29] */ + u32 ipsurx_ch_valid : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw0_u; + +/* Define the union csr_ipsurx_cat_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_ipv4_blindcs_en : 1; /* [0] */ + u32 ipsurx_ch_ipv4_nvme_rocev2_verify_en : 1; /* [1] */ + u32 ipsurx_ch_ipv4_nvme_rocev2_en : 1; /* [2] */ + u32 ipsurx_ch_nvme_sector_size : 1; /* [3] */ + u32 ipsurx_ch_ipv4_udp_len_chk_en : 1; /* [4] */ + u32 ipsurx_ch_ipv4_tcp_cs_chk_en : 1; /* [5] */ + u32 ipsurx_ch_ipv4_tcp_syn_chk_en : 1; /* [6] */ + u32 ipsurx_ch_ipv4_sctp_cs_chk_en : 1; /* [7] */ + u32 ipsurx_ch_ipv4_icmp_cs_chk_en : 1; /* [8] */ + u32 ipsurx_ch_ipv4_igmp_cs_chk_en : 1; /* [9] */ + u32 ipsurx_ch_rocev2_ipv4_udp_cs_chk_en : 1; /* [10] */ + u32 ipsurx_ch_rocev2_ipv4_fra_chk_en : 1; /* [11] */ + u32 ipsurx_ch_ipv4_udp_cs_chk_en : 1; /* [12] */ + u32 ipsurx_ch_natt_ipv4_udpcs_zero_chk_en : 1; /* [13] */ + u32 ipsurx_ch_ipv4_ip_cs_chk_en : 1; /* [14] */ + u32 ipsurx_ch_ipv4_dip_rsv_addr_chk_en : 1; /* [15] */ + u32 ipsurx_ch_ipv4_dip_zero_chk_en : 1; /* [16] */ + u32 ipsurx_ch_ipv4_dip_lb_chk_en : 1; /* [17] */ + u32 ipsurx_ch_ipv4_sip_lb_chk_en : 1; /* [18] */ + u32 ipsurx_ch_ipv4_sip_mc_chk_en : 1; /* [19] */ + u32 ipsurx_ch_ipv4_sip_dip_chk_en : 1; /* [20] */ + u32 ipsurx_ch_ipv4_ihl_chk_en : 1; /* [21] */ + u32 ipsurx_ch_ipv4_ver_chk_en : 1; /* [22] */ + u32 ipsurx_ch_ipv4_len_chk_en : 1; /* [23] */ + u32 rsv_13 : 4; /* [27:24] */ + u32 ipsurx_ch_8023_len_chk_en : 1; /* [28] */ + u32 ipsurx_ch_da_sa_equal_chk_en : 1; /* [29] */ + u32 ipsurx_ch_smac_chk_en : 1; /* [30] */ + u32 ipsurx_ch_dmac_zero_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw1_u; + +/* Define the union csr_ipsurx_cat_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_fc_crc_chk_en : 1; /* [0] */ + u32 ipsurx_ch_roce_pkey_chk_en : 1; /* [1] */ + u32 ipsurx_ch_roce_tver_chk_en : 1; /* [2] */ + u32 ipsurx_ch_roce_icrc_chk_en : 1; /* [3] */ + u32 ipsurx_ch_roce_dqp_chk_en : 1; /* [4] */ + u32 ipsurx_ch_rocev1_len_chk_en : 1; /* [5] */ + u32 ipsurx_ch_rocev1_sgid_chk_en : 1; /* [6] */ + u32 ipsurx_ch_rocev1_dgid_chk_en : 1; /* [7] */ + u32 ipsurx_ch_rocev1_nxhdr_chk_en : 1; /* [8] */ + u32 ipsurx_ch_rocev1_ipver_chk_en : 1; /* [9] */ + u32 ipsurx_ch_roce_ext_len_exc_chk_en : 1; /* [10] */ + u32 ipsurx_ch_tcp_ack_rst_syn_chk_en : 1; /* [11] */ + u32 ipsurx_ch_tcp_fin_ack_chk_en : 1; /* [12] */ + u32 ipsurx_ch_tcp_no_flag_chk_en : 1; /* [13] */ + u32 ipsurx_ch_tcp_syn_fin_chk_en : 1; /* [14] */ + u32 ipsurx_ch_tcp_do_chk_en : 1; /* [15] */ + u32 ipsurx_ch_ipv6_blindcs_en : 1; /* [16] */ + u32 ipsurx_ch_ipv6_nvme_rocev2_verify_en : 1; /* [17] */ + u32 ipsurx_ch_ipv6_nvme_rocev2_en : 1; /* [18] */ + u32 ipsurx_ch_nvme_rocev1_verify_en : 1; /* [19] */ + u32 ipsurx_ch_nvme_rocev1_en : 1; /* [20] */ + u32 ipsurx_ch_ipv6_tcp_cs_chk_en : 1; /* [21] */ + u32 ipsurx_ch_ipv6_tcp_syn_chk_en : 1; /* [22] */ + u32 ipsurx_ch_ipv6_sctp_cs_chk_en : 1; /* [23] */ + u32 ipsurx_ch_ipv6_icmp_cs_chk_en : 1; /* [24] */ + u32 ipsurx_ch_rocev2_ipv6_udp_cs_chk_en : 1; /* [25] */ + u32 ipsurx_ch_ipv6_udp_cs_chk_en : 1; /* [26] */ + u32 ipsurx_ch_ipv6_udpcs_zero_chk_en : 1; /* [27] */ + u32 ipsurx_ch_ipv6_dip_chk_en : 1; /* [28] */ + u32 ipsurx_ch_ipv6_sip_chk_en : 1; /* [29] */ + u32 ipsurx_ch_ipv6_ver_chk_en : 1; /* [30] */ + u32 ipsurx_ch_ipv6_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw2_u; + +/* Define the union csr_ipsurx_cat_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_pkt_len_chk_en : 1; /* [0] */ + u32 ipsurx_ch_min_pkt_len : 7; /* [7:1] */ + u32 ipsurx_ch_max_pkt_len : 14; /* [21:8] */ + u32 rsv_14 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw3_u; + +/* Define the union csr_ipsurx_cat_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_tunnel_da_sa_equal_chk_en : 1; /* [0] */ + u32 ipsurx_ch_tunnel_smac_chk_en : 1; /* [1] */ + u32 ipsurx_ch_tunnel_dmac_zero_chk_en : 1; /* [2] */ + u32 ipsurx_ch_tunnel_nvgre_cvlan_chk_en : 1; /* [3] */ + u32 rsv_15 : 4; /* [7:4] */ + u32 ipsurx_ch_tunnel_cvlan_tpid_sel : 5; /* [12:8] */ + u32 ipsurx_ch_tunnel_cvlan : 1; /* [13] */ + u32 ipsurx_ch_tunnel_svlan_tpid_sel : 5; /* [18:14] */ + u32 ipsurx_ch_tunnel_svlan : 1; /* [19] */ + u32 ipsurx_ch_tunnel_vni_chk_en : 1; /* [20] */ + u32 ipsurx_ch_nvgre_crks_chk_en : 1; /* [21] */ + u32 rsv_16 : 2; /* [23:22] */ + u32 ipsurx_ch_dflt_fwd_act : 3; /* [26:24] */ + u32 rsv_17 : 1; /* [27] */ + u32 ipsurx_ch_dflt_pkt_pri : 3; /* [30:28] */ + u32 rsv_18 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw4_u; + +/* Define the union csr_ipsurx_cat_dw5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_vf_key_sel : 1; /* [0] */ + u32 ipsurx_ch_tcam_key_sel : 1; /* [1] */ + u32 ipsurx_ch_pri_dflt_sel : 1; /* [2] */ + u32 ipsurx_ch_ncsi_key_sel : 1; /* [3] */ + u32 ipsurx_ch_pri_sel : 4; /* [7:4] */ + u32 ipsurx_ch_pri_key_sel : 1; /* [8] */ + u32 ipsurx_ch_pri_sel_en : 1; /* [9] */ + u32 ipsurx_ch_tunnel_ipv6_blindcs_en : 1; /* [10] */ + u32 ipsurx_ch_tunnel_ipv6_udp_cs_chk_en : 1; /* [11] */ + u32 ipsurx_ch_tunnel_ipv6_udpcs_zero_chk_en : 1; /* [12] */ + u32 ipsurx_ch_tunnel_ipv6_dip_chk_en : 1; /* [13] */ + u32 ipsurx_ch_tunnel_ipv6_sip_chk_en : 1; /* [14] */ + u32 ipsurx_ch_tunnel_ipv6_ver_chk_en : 1; /* [15] */ + u32 ipsurx_ch_tunnel_ipv6_len_chk_en : 1; /* [16] */ + u32 ipsurx_ch_cn_pri_sel : 1; /* [17] */ + u32 ipsurx_ch_tunnel_ipv4_udp_len_chk_en : 1; /* [18] */ + u32 ipsurx_ch_tunnel_ipv4_blindcs_en : 1; /* [19] */ + u32 ipsurx_ch_tunnel_ipv4_udp_cs_chk_en : 1; /* [20] */ + u32 ipsurx_ch_tunnel_ipv4_ip_cs_chk_en : 1; /* [21] */ + u32 ipsurx_ch_tunnel_ipv4_dip_rsv_addr_chk_en : 1; /* [22] */ + u32 ipsurx_ch_tunnel_ipv4_dip_zero_chk_en : 1; /* [23] */ + u32 ipsurx_ch_tunnel_ipv4_dip_lb_chk_en : 1; /* [24] */ + u32 ipsurx_ch_tunnel_ipv4_sip_lb_chk_en : 1; /* [25] */ + u32 ipsurx_ch_tunnel_ipv4_sip_mc_chk_en : 1; /* [26] */ + u32 ipsurx_ch_tunnel_ipv4_sip_dip_chk_en : 1; /* [27] */ + u32 ipsurx_ch_tunnel_ipv4_ihl_chk_en : 1; /* [28] */ + u32 ipsurx_ch_tunnel_ipv4_ver_chk_en : 1; /* [29] */ + u32 ipsurx_ch_tunnel_ipv4_len_chk_en : 1; /* [30] */ + u32 ipsurx_ch_tunnel_8023_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw5_u; + +/* Define the union csr_ipsurx_ch_invld_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_invld_sts : 9; /* [8:0] */ + u32 rsv_19 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ch_invld_sts_u; + +/* Define the union csr_ipsurx_sop_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sop_eop_st : 11; /* [10:0] */ + u32 rsv_20 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sop_eop_st_u; + +/* Define the union csr_ipsurx_mfs_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_sop_with_err_cnt_u; + +/* Define the union csr_ipsurx_mfs_abort_bf_ipsurx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_abort_bf_ipsurx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_abort_bf_ipsurx_cnt_u; + +/* Define the union csr_ipsurx_mfs_cut_by_ipsurx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_cut_by_ipsurx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_cut_by_ipsurx_cnt_u; + +/* Define the union csr_ipsurx_mfs_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_sop_sop_err_cnt_u; + +/* Define the union csr_ipsurx_perx_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_perx_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_perx_sop_with_err_cnt_u; + +/* Define the union csr_ipsurx_perx_abort_bf_ipsurx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_perx_abort_bf_ipsurx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_perx_abort_bf_ipsurx_cnt_u; + +/* Define the union csr_ipsurx_perx_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_perx_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_perx_sop_sop_err_cnt_u; + +/* Define the union csr_ipsurx_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_hg2hdr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hg2hdr_ehv_loc : 7; /* [6:0] */ + u32 rsv_21 : 1; /* [7] */ + u32 ipsurx_hg2hdr_ehv_0_hlen : 5; /* [12:8] */ + u32 rsv_22 : 3; /* [15:13] */ + u32 ipsurx_hg2hdr_ehv_1_hlen : 5; /* [20:16] */ + u32 rsv_23 : 3; /* [23:21] */ + u32 ipsurx_hg2hdr_vld : 1; /* [24] */ + u32 rsv_24 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hg2hdr_cfg_u; + +/* Define the union csr_ipsurx_unknown_tag_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_unknown_tag_ofs : 6; /* [5:0] */ + u32 rsv_25 : 2; /* [7:6] */ + u32 ipsurx_unknown_tag_len : 5; /* [12:8] */ + u32 rsv_26 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_unknown_tag_cfg_u; + +/* Define the union csr_ipsurx_evtag_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_evtag_tpid2 : 16; /* [15:0] */ + u32 ipsurx_evtag_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_evtag_tpid1_u; + +/* Define the union csr_ipsurx_evtag_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_evtag_tpid0 : 16; /* [15:0] */ + u32 ipsurx_evtag_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_evtag_tpid0_u; + +/* Define the union csr_ipsurx_svlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_svlan_tpid4 : 16; /* [15:0] */ + u32 ipsurx_svlan_private0 : 1; /* [16] */ + u32 ipsurx_svlan_private1 : 1; /* [17] */ + u32 ipsurx_svlan_private2 : 1; /* [18] */ + u32 ipsurx_svlan_private3 : 1; /* [19] */ + u32 ipsurx_svlan_private4 : 1; /* [20] */ + u32 ipsurx_hcap_svlan0 : 1; /* [21] */ + u32 ipsurx_hcap_svlan1 : 1; /* [22] */ + u32 ipsurx_hcap_svlan2 : 1; /* [23] */ + u32 ipsurx_hcap_svlan3 : 1; /* [24] */ + u32 ipsurx_hcap_svlan4 : 1; /* [25] */ + u32 rsv_27 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_svlan_tpid2_u; + +/* Define the union csr_ipsurx_svlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_svlan_tpid2 : 16; /* [15:0] */ + u32 ipsurx_svlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_svlan_tpid1_u; + +/* Define the union csr_ipsurx_svlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_svlan_tpid0 : 16; /* [15:0] */ + u32 ipsurx_svlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_svlan_tpid0_u; + +/* Define the union csr_ipsurx_cvlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cvlan_tpid4 : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cvlan_tpid2_u; + +/* Define the union csr_ipsurx_cvlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cvlan_tpid2 : 16; /* [15:0] */ + u32 ipsurx_cvlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cvlan_tpid1_u; + +/* Define the union csr_ipsurx_cvlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cvlan_tpid0 : 16; /* [15:0] */ + u32 ipsurx_cvlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cvlan_tpid0_u; + +/* Define the union csr_ipsurx_p8021_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_p8021_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_p8021_pri_u; + +/* Define the union csr_ipsurx_8023_max_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_8023_max_len : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_8023_max_len_u; + +/* Define the union csr_ipsurx_8023_jumbo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_8023_jumbo_tpid : 16; /* [15:0] */ + u32 ipsurx_8023_jumbo_chk_en : 1; /* [16] */ + u32 rsv_30 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_8023_jumbo_cfg_u; + +/* Define the union csr_ipsurx_l2_dmac_eth_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lldp_dmac_chk_en : 1; /* [0] */ + u32 ipsurx_lacp_dmac_chk_en : 1; /* [1] */ + u32 ipsurx_pfc_dmac_chk_en : 1; /* [2] */ + u32 ipsurx_pause_dmac_chk_en : 1; /* [3] */ + u32 ipsurx_tunnel_lldp_dmac_chk_en : 1; /* [4] */ + u32 ipsurx_tunnel_lacp_dmac_chk_en : 1; /* [5] */ + u32 ipsurx_tunnel_pfc_dmac_chk_en : 1; /* [6] */ + u32 ipsurx_tunnel_pause_dmac_chk_en : 1; /* [7] */ + u32 rsv_31 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_l2_dmac_eth_chk_en_u; + +/* Define the union csr_ipsurx_rtn_ts_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rtn_ts_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rtn_ts_en_u; + +/* Define the union csr_ipsurx_rtn_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rtn_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rtn_ts_u; + +/* Define the union csr_ipsurx_ipv4_dscp_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dscp_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dscp_pri_u; + +/* Define the union csr_ipsurx_igmpv4_dip_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_igmpv4_dip_chk_en : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_igmpv4_dip_chk_en_u; + +/* Define the union csr_ipsurx_ipv6_dscp_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_dscp_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_dscp_pri_u; + +/* Define the union csr_ipsurx_fc_csctl_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_csctl_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_csctl_pri_u; + +/* Define the union csr_ipsurx_fc_priority_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_priority_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_priority_pri_u; + +/* Define the union csr_ipsurx_ipv6_spec_mc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_spec_mcast : 16; /* [15:0] */ + u32 ipsurx_ipv6_spec_mcast_mask : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_spec_mc_u; + +/* Define the union csr_ipsurx_roce_bth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_pkey : 16; /* [15:0] */ + u32 ipsurx_roce_tver : 4; /* [19:16] */ + u32 rsv_34 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_bth_u; + +/* Define the union csr_ipsurx_rocev2_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_dport : 16; /* [15:0] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_dport_u; + +/* Define the union csr_ipsurx_natt_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_natt_dport : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_natt_dport_u; + +/* Define the union csr_ipsurx_vxlan_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vxlan_dport : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vxlan_dport_u; + +/* Define the union csr_ipsurx_vxlan_gpe_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vxlan_gpe_dport : 16; /* [15:0] */ + u32 rsv_38 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vxlan_gpe_dport_u; + +/* Define the union csr_ipsurx_geneve_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_geneve_dport : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_geneve_dport_u; + +/* Define the union csr_ipsurx_ipv4_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_np : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_np_u; + +/* Define the union csr_ipsurx_ipv6_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_np : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_np_u; + +/* Define the union csr_ipsurx_ethernet_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ethernet_np : 8; /* [7:0] */ + u32 rsv_42 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ethernet_np_u; + +/* Define the union csr_ipsurx_ioam_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ioam_np : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ioam_np_u; + +/* Define the union csr_ipsurx_int_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_int_np : 8; /* [7:0] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_np_u; + +/* Define the union csr_ipsurx_nsh_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nsh_np : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nsh_np_u; + +/* Define the union csr_ipsurx_ah_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ah_np : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ah_np_u; + +/* Define the union csr_ipsurx_esp_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_esp_np : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_esp_np_u; + +/* Define the union csr_ipsurx_rob_opt_class_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rob_opt_class : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rob_opt_class_u; + +/* Define the union csr_ipsurx_ppop_opt_class_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ppop_opt_class : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ppop_opt_class_u; + +/* Define the union csr_ipsurx_telemetry_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tele_geneve_en : 1; /* [0] */ + u32 ipsurx_tele_tcp_en : 1; /* [1] */ + u32 ipsurx_tele_udp_en : 1; /* [2] */ + u32 rsv_50 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_telemetry_en_u; + +/* Define the union csr_ipsurx_tcp_coco_with_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_with_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_coco_with_ts_dw0_u; + +/* Define the union csr_ipsurx_tcp_coco_without_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_without_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_coco_without_ts_dw0_u; + +/* Define the union csr_ipsurx_tcp_coco_dw0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_dw0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_coco_dw0_mask_u; + +/* Define the union csr_ipsurx_coalesce_pkt_fwd_act_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_fwd_act_ctrl : 1; /* [0] */ + u32 ipsurx_rocev2_fwd_act_ctrl : 1; /* [1] */ + u32 ipsurx_fc_fwd_act_ctrl : 1; /* [2] */ + u32 ipsurx_cn_rocev2_fwd_act_ctrl : 1; /* [3] */ + u32 ipsurx_lb_tcp_coco_fwd_act_ctrl : 1; /* [4] */ + u32 ipsurx_lb_rocev2_fwd_act_ctrl : 1; /* [5] */ + u32 ipsurx_lb_cn_rocev2_fwd_act_ctrl : 1; /* [6] */ + u32 rsv_51 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_coalesce_pkt_fwd_act_ctrl_u; + +/* Define the union csr_ipsurx_hcap_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hcap_val1 : 16; /* [15:0] */ + u32 ipsurx_hcap_val2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hcap_val_u; + +/* Define the union csr_ipsurx_hcap_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hcap_pri : 3; /* [2:0] */ + u32 rsv_52 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hcap_pri_u; + +/* Define the union csr_ipsurx_ctrl_pkt_dmac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_dmac_h : 16; /* [15:0] */ + u32 ipsurx_ctrl_pkt_dmac_en : 1; /* [16] */ + u32 rsv_53 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_dmac_h_u; + +/* Define the union csr_ipsurx_ctrl_pkt_dmac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_dmac_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_dmac_l_u; + +/* Define the union csr_ipsurx_ipv6_ext_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_ext_nh : 8; /* [7:0] */ + u32 ipsurx_ipv6_ext_vld : 1; /* [8] */ + u32 rsv_54 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_ext_ctrl_u; + +/* Define the union csr_ipsurx_bgp_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_bgp_dport : 16; /* [15:0] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_bgp_dport_u; + +/* Define the union csr_ipsurx_tcp_opt_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_opt_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_opt_dw0_u; + +/* Define the union csr_ipsurx_esp_prtl_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_esp_prtl_type : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_esp_prtl_type_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw0_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw1_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw2_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw3_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw0_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw1_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw2_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw3_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw0_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw1_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw2_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw3_u; + +/* Define the union csr_ipsurx_crc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_difx_crc_dat_bit_rev : 1; /* [0] */ + u32 ipsurx_difx_crc_rslt_bit_rev : 1; /* [1] */ + u32 ipsurx_difx_crc_rslt_inv : 1; /* [2] */ + u32 rsv_57 : 1; /* [3] */ + u32 ipsurx_fc_crc_dat_bit_rev : 1; /* [4] */ + u32 ipsurx_fc_crc_rslt_bit_rev : 1; /* [5] */ + u32 ipsurx_fc_crc_rslt_inv : 1; /* [6] */ + u32 rsv_58 : 1; /* [7] */ + u32 ipsurx_sctp_crc_dat_bit_rev : 1; /* [8] */ + u32 ipsurx_sctp_crc_rslt_bit_rev : 1; /* [9] */ + u32 ipsurx_sctp_crc_rslt_inv : 1; /* [10] */ + u32 rsv_59 : 5; /* [15:11] */ + u32 ipsurx_roce_icrc_dat_bit_rev : 1; /* [16] */ + u32 ipsurx_roce_icrc_rslt_bit_rev : 1; /* [17] */ + u32 ipsurx_roce_icrc_rslt_inv : 1; /* [18] */ + u32 rsv_60 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_crc_ctrl_u; + +/* Define the union csr_ipsurx_roce_icrc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_icrc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_icrc_ini_u; + +/* Define the union csr_ipsurx_roce_icrc_mn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_icrc_mn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_icrc_mn_u; + +/* Define the union csr_ipsurx_fc_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_crc_ini_u; + +/* Define the union csr_ipsurx_fc_crc_mn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_crc_mn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_crc_mn_u; + +/* Define the union csr_ipsurx_sctp_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sctp_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sctp_crc_ini_u; + +/* Define the union csr_ipsurx_difx_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_difx_crc_ini : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_difx_crc_ini_u; + +/* Define the union csr_ipsurx_mag_drop_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mag_drop_ctrl : 2; /* [1:0] */ + u32 rsv_61 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mag_drop_ctrl_u; + +/* Define the union csr_ipsurx_rob_ppop_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ppop_en : 1; /* [0] */ + u32 ipsurx_rob_en : 1; /* [1] */ + u32 ipsurx_ppop_ctrl_en : 1; /* [2] */ + u32 rsv_62 : 1; /* [3] */ + u32 ipsurx_fwd_to_rob_en : 1; /* [4] */ + u32 rsv_63 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rob_ppop_en_u; + +/* Define the union csr_ipsurx_ctrl_pkt_port_map_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_port_map_en : 1; /* [0] */ + u32 rsv_64 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_port_map_en_u; + +/* Define the union csr_ipsurx_ctrl_pkt_port_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_port_map : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_port_map_u; + +/* Define the union csr_ipsurx_push_len_l2f_oth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_l2f_none : 4; /* [3:0] */ + u32 ipsurx_push_len_l2f_hcap : 4; /* [7:4] */ + u32 ipsurx_push_len_err : 4; /* [11:8] */ + u32 ipsurx_push_len_l2f_ppop : 4; /* [15:12] */ + u32 ipsurx_push_len_max : 4; /* [19:16] */ + u32 rsv_65 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_l2f_oth_u; + +/* Define the union csr_ipsurx_push_len_l3f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_l3f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_l3f_u; + +/* Define the union csr_ipsurx_push_len_l45f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_l45f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_l45f_u; + +/* Define the union csr_ipsurx_push_len_fc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_fc : 4; /* [3:0] */ + u32 rsv_66 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_fc_u; + +/* Define the union csr_ipsurx_roce_ext_sumop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_ext_sumop : 6; /* [5:0] */ + u32 rsv_67 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_ext_sumop_u; + +/* Define the union csr_ipsurx_sr_sumop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_reroute_sumop : 6; /* [5:0] */ + u32 rsv_68 : 2; /* [7:6] */ + u32 ipsurx_other_reroute_sumop : 6; /* [13:8] */ + u32 rsv_69 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sr_sumop_u; + +/* Define the union csr_ipsurx_ctrl_pkt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_en_arp : 1; /* [0] */ + u32 ipsurx_ctrl_pkt_en_rarp : 1; /* [1] */ + u32 ipsurx_ctrl_pkt_en_pause : 1; /* [2] */ + u32 ipsurx_ctrl_pkt_en_pfc : 1; /* [3] */ + u32 ipsurx_ctrl_pkt_en_lacp : 1; /* [4] */ + u32 ipsurx_ctrl_pkt_en_marker : 1; /* [5] */ + u32 ipsurx_ctrl_pkt_en_oam : 1; /* [6] */ + u32 ipsurx_ctrl_pkt_en_slow_prtl : 1; /* [7] */ + u32 ipsurx_ctrl_pkt_en_lldp : 1; /* [8] */ + u32 ipsurx_ctrl_pkt_en_cdcp : 1; /* [9] */ + u32 ipsurx_ctrl_pkt_en_cnm : 1; /* [10] */ + u32 ipsurx_ctrl_pkt_en_ecp : 1; /* [11] */ + u32 ipsurx_ctrl_pkt_en_vdp : 1; /* [12] */ + u32 ipsurx_ctrl_pkt_en_mpls : 1; /* [13] */ + u32 ipsurx_ctrl_pkt_en_vrrp : 1; /* [14] */ + u32 ipsurx_ctrl_pkt_en_ospf : 1; /* [15] */ + u32 ipsurx_ctrl_pkt_en_bgp : 1; /* [16] */ + u32 rsv_70 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_en_u; + +/* Define the union csr_ipsurx_roce_ext_len_exc_sumop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_ext_len_exc_sumop : 6; /* [5:0] */ + u32 rsv_71 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_ext_len_exc_sumop_u; + +/* Define the union csr_ipsurx_roce_drc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_drc_op : 3; /* [2:0] */ + u32 ipsurx_roce_dqp_allf_chk_en : 1; /* [3] */ + u32 rsv_72 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_drc_ctrl_u; + +/* Define the union csr_ipsurx_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_dmac_zero_cnt_u; + +/* Define the union csr_ipsurx_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_smac_ilgl_cnt_u; + +/* Define the union csr_ipsurx_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_da_sa_equal_cnt_u; + +/* Define the union csr_ipsurx_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_dmac_zero_cnt_u; + +/* Define the union csr_ipsurx_tunnel_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_smac_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_da_sa_equal_cnt_u; + +/* Define the union csr_ipsurx_tunnel_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_land_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_land_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_land_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_do_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_do_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_do_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_syn_fin_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_syn_fin_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_syn_fin_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_no_flag_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_no_flag_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_no_flag_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_fin_ack_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_fin_ack_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_fin_ack_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_ack_rst_syn_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_ack_rst_syn_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_ack_rst_syn_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_udp_cs_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_udp_cs_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_udp_cs_zero_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_udp_cs_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_udp_cs_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_udp_cs_zero_cnt_u; + +/* Define the union csr_ipsurx_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_igmp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_igmp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_igmp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_icmpv4_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_icmpv4_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_icmpv4_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_icmpv6_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_icmpv6_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_icmpv6_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_sctp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sctp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sctp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_dgid_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_dgid_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_dgid_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_sgid_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_sgid_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_sgid_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_ipver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_ipver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_ipver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_nxhdr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_nxhdr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_nxhdr_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_paylen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_paylen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_paylen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_frag_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_frag_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_frag_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_tver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_tver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_tver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_pkey_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_pkey_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_pkey_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_dqp_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_dqp_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_dqp_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_padcnt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_padcnt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_padcnt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_va_8b_align_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_va_8b_align_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_va_8b_align_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_dmalen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_dmalen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_dmalen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_opcode_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_opcode_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_opcode_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ib_icrc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ib_icrc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ib_icrc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_fc_crc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_crc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_crc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_to_up_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_to_up_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_to_up_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_to_bmc_only_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_to_bmc_only_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_to_bmc_only_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_llc_snap_enc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_llc_snap_enc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_llc_snap_enc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_eth_type_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_eth_type_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_eth_type_ilgl_cnt_u; + +/* Define the union csr_ipsurx_vxlan_gpe_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vxlan_gpe_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vxlan_gpe_other_ver_cnt_u; + +/* Define the union csr_ipsurx_geneve_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_geneve_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_geneve_other_ver_cnt_u; + +/* Define the union csr_ipsurx_nsh_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nsh_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nsh_other_ver_cnt_u; + +/* Define the union csr_ipsurx_nsh_len_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nsh_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nsh_len_cnt_u; + +/* Define the union csr_ipsurx_tunnel_nvgre_cvlan_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_nvgre_cvlan_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_nvgre_cvlan_ilgl_cnt_u; + +/* Define the union csr_ipsurx_hcap_md_size_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hcap_md_size_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hcap_md_size_ilgl_cnt_u; + +/* Define the union csr_ipsurx_drop_mfs_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_drop_mfs_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_drop_mfs_pkt_cnt_u; + +/* Define the union csr_ipsurx_len_4b_align_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_len_4b_align_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_len_4b_align_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_nvgre_crks_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nvgre_crks_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nvgre_crks_ilgl_cnt_u; + +/* Define the union csr_ipsurx_hdr_len_min_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hdr_len_min_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hdr_len_min_ilgl_cnt_u; + +/* Define the union csr_ipsurx_pause_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pause_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pause_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_pfc_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pfc_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pfc_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_ext_len_exc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_ext_len_exc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_ext_len_exc_cnt_u; + +/* Define the union csr_ipsurx_ipsec_auth_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipsec_auth_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipsec_auth_ilgl_cnt_u; + +/* Define the union csr_ipsurx_natt_ipv4_udp_cs_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_natt_ipv4_udp_cs_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_natt_ipv4_udp_cs_zero_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tx_cpt_pkt_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tx_cpt_pkt_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tx_cpt_pkt_drop_cnt_u; + +/* Define the union csr_ipsurx_ncsi_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_pkt_pri : 3; /* [2:0] */ + u32 ipsurx_ncsi_ctrl_pkt_en : 1; /* [3] */ + u32 ipsurx_mac_ncsi_en : 1; /* [4] */ + u32 ipsurx_hg2_ncsi_en : 1; /* [5] */ + u32 rsv_73 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_filter_mng_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_rule0_en : 1; /* [0] */ + u32 ipsurx_ncsi_flt_rule0_fwd_act : 1; /* [1] */ + u32 rsv_74 : 2; /* [3:2] */ + u32 ipsurx_ncsi_flt_rule0_mac_port : 4; /* [7:4] */ + u32 ipsurx_ncsi_flt_rule1_en : 1; /* [8] */ + u32 ipsurx_ncsi_flt_rule1_fwd_act : 1; /* [9] */ + u32 rsv_75 : 2; /* [11:10] */ + u32 ipsurx_ncsi_flt_rule1_mac_port : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_rule2_en : 1; /* [16] */ + u32 ipsurx_ncsi_flt_rule2_fwd_act : 1; /* [17] */ + u32 rsv_76 : 2; /* [19:18] */ + u32 ipsurx_ncsi_flt_rule2_mac_port : 4; /* [23:20] */ + u32 ipsurx_ncsi_flt_rule3_en : 1; /* [24] */ + u32 ipsurx_ncsi_flt_rule3_fwd_act : 1; /* [25] */ + u32 rsv_77 : 2; /* [27:26] */ + u32 ipsurx_ncsi_flt_rule3_mac_port : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_filter_mng_u; + +/* Define the union csr_ipsurx_ncsi_mac3_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac3_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac3_vld : 1; /* [16] */ + u32 rsv_78 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac3_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac3_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac3_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac3_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac2_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac2_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac2_vld : 1; /* [16] */ + u32 rsv_79 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac2_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac2_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac2_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac2_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac1_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac1_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac1_vld : 1; /* [16] */ + u32 rsv_80 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac1_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac1_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac1_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac1_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac0_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac0_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac0_vld : 1; /* [16] */ + u32 rsv_81 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac0_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac0_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac0_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac0_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_vlan_en : 4; /* [3:0] */ + u32 rsv_82 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan_en_u; + +/* Define the union csr_ipsurx_ncsi_vlan7_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan7_id : 12; /* [11:0] */ + u32 rsv_83 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan7_id_vld : 1; /* [16] */ + u32 rsv_84 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan7_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan6_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan6_id : 12; /* [11:0] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan6_id_vld : 1; /* [16] */ + u32 rsv_86 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan6_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan5_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan5_id : 12; /* [11:0] */ + u32 rsv_87 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan5_id_vld : 1; /* [16] */ + u32 rsv_88 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan5_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan4_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan4_id : 12; /* [11:0] */ + u32 rsv_89 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan4_id_vld : 1; /* [16] */ + u32 rsv_90 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan4_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan3_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan3_id : 12; /* [11:0] */ + u32 rsv_91 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan3_id_vld : 1; /* [16] */ + u32 rsv_92 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan3_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan2_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan2_id : 12; /* [11:0] */ + u32 rsv_93 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan2_id_vld : 1; /* [16] */ + u32 rsv_94 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan2_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan1_id : 12; /* [11:0] */ + u32 rsv_95 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan1_id_vld : 1; /* [16] */ + u32 rsv_96 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan1_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan0_id : 12; /* [11:0] */ + u32 rsv_97 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan0_id_vld : 1; /* [16] */ + u32 rsv_98 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan0_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_bc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_dmac_en : 1; /* [0] */ + u32 ipsurx_ncsi_flt_bc_arp_en : 1; /* [1] */ + u32 ipsurx_ncsi_flt_bc_ipv4_en : 1; /* [2] */ + u32 ipsurx_ncsi_flt_bc_ip_udp_en : 1; /* [3] */ + u32 ipsurx_ncsi_flt_bc_udp_prt68_en : 1; /* [4] */ + u32 ipsurx_ncsi_flt_bc_udp_prt67_en : 1; /* [5] */ + u32 ipsurx_ncsi_flt_bc_udp_prt137_en : 1; /* [6] */ + u32 ipsurx_ncsi_flt_bc_udp_prt138_en : 1; /* [7] */ + u32 ipsurx_ncsi_flt_bc_arp_tipv4_addr_en : 1; /* [8] */ + u32 ipsurx_ncsi_flt_bc_dhcpv4_cmac_en : 1; /* [9] */ + u32 rsv_99 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_bc_arp_tipv4_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_arp_tipv4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_arp_tipv4_addr_u; + +/* Define the union csr_ipsurx_ncsi_bc_dhcpv4_cmac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_dhcpv4_cmac_h : 16; /* [15:0] */ + u32 rsv_100 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_dhcpv4_cmac_h_u; + +/* Define the union csr_ipsurx_ncsi_bc_dhcpv4_cmac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_dhcpv4_cmac_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_dhcpv4_cmac_l_u; + +/* Define the union csr_ipsurx_ncsi_mc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_mc_dmac0_en : 1; /* [0] */ + u32 ipsurx_ncsi_flt_mc_dmac1_en : 1; /* [1] */ + u32 ipsurx_ncsi_flt_mc_dmac2_en : 1; /* [2] */ + u32 ipsurx_ncsi_flt_mc_dmac3_en : 1; /* [3] */ + u32 ipsurx_ncsi_flt_mc_ipv6_en : 1; /* [4] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_en : 1; /* [5] */ + u32 ipsurx_ncsi_flt_mc_udp_en : 1; /* [6] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt136_en : 1; /* [7] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt135_en : 1; /* [8] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt134_en : 1; /* [9] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt132_en : 1; /* [10] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt131_en : 1; /* [11] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt130_en : 1; /* [12] */ + u32 ipsurx_ncsi_flt_mc_udp_prt547_en : 1; /* [13] */ + u32 ipsurx_ncsi_flt_mc_udp_prt546_en : 1; /* [14] */ + u32 rsv_101 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mc_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_rule_vxlan_en : 4; /* [3:0] */ + u32 rsv_102 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_en_u; + +/* Define the union csr_ipsurx_ncsi_vxlan1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan1_vni : 24; /* [23:0] */ + u32 ipsurx_ncsi_flt_vxlan1_vld : 1; /* [24] */ + u32 rsv_103 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan1_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vxlan0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan0_vni : 24; /* [23:0] */ + u32 ipsurx_ncsi_flt_vxlan0_vld : 1; /* [24] */ + u32 rsv_104 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan0_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv4_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw3_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw2_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw1_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw0_u; + +/* Define the union csr_ipsurx_ncsi_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_hit_cnt_u; + +/* Define the union csr_ipsurx_lli_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lli_type : 16; /* [15:0] */ + u32 ipsurx_lli_type_vld : 1; /* [16] */ + u32 rsv_105 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lli_type_u; + +/* Define the union csr_ipsurx_tcam_key_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_key_sel : 1; /* [0] */ + u32 rsv_106 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_key_sel_u; + +/* Define the union csr_ipsurx_tcam_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_bk_scan_period : 8; /* [7:0] */ + u32 ipsurx_tcam_bk_scan_interval_unit : 8; /* [15:8] */ + u32 ipsurx_tcam_lkup_en : 1; /* [16] */ + u32 rsv_107 : 10; /* [26:17] */ + u32 ipsurx_tcam_mbist_en : 1; /* [27] */ + u32 ipsurx_tcam_mbist_test : 2; /* [29:28] */ + u32 ipsurx_tcam_mbist_t_sel : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_ctrl_u; + +/* Define the union csr_ipsurx_tcam_mbist_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_mbist_done : 1; /* [0] */ + u32 rsv_108 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_mbist_done_u; + +/* Define the union csr_ipsurx_vf_tb_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vf_tb_vlanid_mask : 1; /* [0] */ + u32 ipsurx_vf_tb_dmac_mask : 1; /* [1] */ + u32 ipsurx_vf_tb_erid_mask : 1; /* [2] */ + u32 ipsurx_vf_tb_lb_vlanid_mask : 1; /* [3] */ + u32 ipsurx_vf_tb_lb_dmac_mask : 1; /* [4] */ + u32 ipsurx_vf_tb_lb_erid_mask : 1; /* [5] */ + u32 rsv_109 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_tb_mask_u; + +/* Define the union csr_ipsurx_vf_tb_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mac_vf_tb_en : 1; /* [0] */ + u32 ipsurx_hg2_vf_tb_en : 1; /* [1] */ + u32 rsv_110 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_tb_ctrl_u; + +/* Define the union csr_ipsurx_port_erid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port_erid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port_erid_u; + +/* Define the union csr_ipsurx_tcp_opcd_tb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_opcd0 : 8; /* [7:0] */ + u32 ipsurx_tcp_opcd0_hdr_len : 5; /* [12:8] */ + u32 rsv_111 : 3; /* [15:13] */ + u32 ipsurx_tcp_opcd1 : 8; /* [23:16] */ + u32 ipsurx_tcp_opcd1_hdr_len : 5; /* [28:24] */ + u32 rsv_112 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_opcd_tb_u; + +/* Define the union csr_ipsurx_tcam_mbist_mem_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_mbist_mem_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_mbist_mem_err_cnt_u; + +/* Define the union csr_ipsurx_tcam_mbist_cmp_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_mbist_cmp_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_mbist_cmp_err_cnt_u; + +/* Define the union csr_ipsurx_lb_port_erid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lb_port_erid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lb_port_erid_u; + +/* Define the union csr_ipsurx_tcam_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_hit_cnt_u; + +/* Define the union csr_ipsurx_fwd_act_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fwd_act_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fwd_act_cnt_u; + +/* Define the union csr_ipsurx_ctrl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_cnt_u; + +/* Define the union csr_ipsurx_vf_hit_sel_vf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vf_hit_sel_vf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_hit_sel_vf_cnt_u; + +/* Define the union csr_ipsurx_vf_hit_sel_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vf_hit_sel_out_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_hit_sel_out_cnt_u; + +/* Define the union csr_ipsurx_wol_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol_wkup_ctrl : 4; /* [3:0] */ + u32 ipsurx_mac_wol_en : 1; /* [4] */ + u32 ipsurx_hg2_wol_en : 1; /* [5] */ + u32 ipsurx_wol_mod_en : 1; /* [6] */ + u32 rsv_113 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol_ctrl_u; + +/* Define the union csr_ipsurx_wol1_chk_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_rule4_wk_host : 2; /* [1:0] */ + u32 rsv_114 : 2; /* [3:2] */ + u32 ipsurx_wol1_chk_rule4_opcode : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 ipsurx_wol1_rule5_wk_host : 2; /* [9:8] */ + u32 rsv_116 : 2; /* [11:10] */ + u32 ipsurx_wol1_chk_rule5_opcode : 3; /* [14:12] */ + u32 rsv_117 : 1; /* [15] */ + u32 ipsurx_wol1_rule6_wk_host : 2; /* [17:16] */ + u32 rsv_118 : 2; /* [19:18] */ + u32 ipsurx_wol1_chk_rule6_opcode : 3; /* [22:20] */ + u32 rsv_119 : 1; /* [23] */ + u32 ipsurx_wol1_rule7_wk_host : 2; /* [25:24] */ + u32 rsv_120 : 2; /* [27:26] */ + u32 ipsurx_wol1_chk_rule7_opcode : 3; /* [30:28] */ + u32 rsv_121 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ctrl1_u; + +/* Define the union csr_ipsurx_wol1_chk_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_rule0_wk_host : 2; /* [1:0] */ + u32 rsv_122 : 2; /* [3:2] */ + u32 ipsurx_wol1_chk_rule0_opcode : 3; /* [6:4] */ + u32 rsv_123 : 1; /* [7] */ + u32 ipsurx_wol1_rule1_wk_host : 2; /* [9:8] */ + u32 rsv_124 : 2; /* [11:10] */ + u32 ipsurx_wol1_chk_rule1_opcode : 3; /* [14:12] */ + u32 rsv_125 : 1; /* [15] */ + u32 ipsurx_wol1_rule2_wk_host : 2; /* [17:16] */ + u32 rsv_126 : 2; /* [19:18] */ + u32 ipsurx_wol1_chk_rule2_opcode : 3; /* [22:20] */ + u32 rsv_127 : 1; /* [23] */ + u32 ipsurx_wol1_rule3_wk_host : 2; /* [25:24] */ + u32 rsv_128 : 2; /* [27:26] */ + u32 ipsurx_wol1_chk_rule3_opcode : 3; /* [30:28] */ + u32 rsv_129 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ctrl0_u; + +/* Define the union csr_ipsurx_wol1_chk_mac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_macaddr_h : 16; /* [15:0] */ + u32 rsv_130 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_mac_h_u; + +/* Define the union csr_ipsurx_wol1_chk_mac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_macaddr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_mac_l_u; + +/* Define the union csr_ipsurx_wol1_chk_vlanid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_vlanid : 12; /* [11:0] */ + u32 ipsurx_wol1_chk_vlanen : 1; /* [12] */ + u32 rsv_131 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_vlanid_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw0_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw1_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw2_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw3_u; + +/* Define the union csr_ipsurx_wol1_chk_node_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_node_addr_h : 16; /* [15:0] */ + u32 rsv_132 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_node_addr_h_u; + +/* Define the union csr_ipsurx_wol1_chk_node_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_node_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_node_addr_l_u; + +/* Define the union csr_ipsurx_wol2_chk_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_rule0_wk_host : 2; /* [1:0] */ + u32 ipsurx_wol2_chk_rule0_valid : 1; /* [2] */ + u32 rsv_133 : 1; /* [3] */ + u32 ipsurx_wol2_chk_rule1_wk_host : 2; /* [5:4] */ + u32 ipsurx_wol2_chk_rule1_valid : 1; /* [6] */ + u32 rsv_134 : 1; /* [7] */ + u32 ipsurx_wol2_chk_rule2_wk_host : 2; /* [9:8] */ + u32 ipsurx_wol2_chk_rule2_valid : 1; /* [10] */ + u32 rsv_135 : 1; /* [11] */ + u32 ipsurx_wol2_chk_rule3_wk_host : 2; /* [13:12] */ + u32 ipsurx_wol2_chk_rule3_valid : 1; /* [14] */ + u32 rsv_136 : 1; /* [15] */ + u32 ipsurx_wol2_chk_rule4_wk_host : 2; /* [17:16] */ + u32 ipsurx_wol2_chk_rule4_valid : 1; /* [18] */ + u32 rsv_137 : 1; /* [19] */ + u32 ipsurx_wol2_chk_rule5_wk_host : 2; /* [21:20] */ + u32 ipsurx_wol2_chk_rule5_valid : 1; /* [22] */ + u32 rsv_138 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_ctrl_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw0_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw1_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw2_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw3_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw00 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw00_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw01 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw01_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw02_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw02 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw02_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw03_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw03_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw04 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw04_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw05_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw05 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw05_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw06_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw06 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw06_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw07_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw07 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw07_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw08 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw08_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw09_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw09 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw09_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw10_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw11_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw12_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw13_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw14_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw15_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw16_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw17_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw18_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw19_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw20_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw21_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw22_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw23_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw24_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw25_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw26_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw27_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw28_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw29_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw30_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw31_u; + +/* Define the union csr_ipsurx_wol_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol_hit_cnt_u; + +/* Define the union csr_ipsurx_cpt_ofs_ctrl_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ofs : 6; /* [5:0] */ + u32 rsv_139 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ofs_ctrl_dw0_u; + +/* Define the union csr_ipsurx_cpt_ofs_ctrl_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ofs_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ofs_ctrl_dw1_u; + +/* Define the union csr_ipsurx_cpt_com_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_mac_port : 3; /* [2:0] */ + u32 ipsurx_cpt_sel : 1; /* [3] */ + u32 ipsurx_cpt_ofs_vld : 1; /* [4] */ + u32 ipsurx_cpt_en : 1; /* [5] */ + u32 rsv_140 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_com_ctrl_u; + +/* Define the union csr_ipsurx_cpt_mac_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_mac_etype : 16; /* [15:0] */ + u32 ipsurx_cpt_mac_etype_vld : 1; /* [16] */ + u32 ipsurx_cpt_smac_vld : 1; /* [17] */ + u32 ipsurx_cpt_dmac_vld : 1; /* [18] */ + u32 rsv_141 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw0_u; + +/* Define the union csr_ipsurx_cpt_mac_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_dmac_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw1_u; + +/* Define the union csr_ipsurx_cpt_mac_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_smac_h16 : 16; /* [15:0] */ + u32 ipsurx_cpt_dmac_h16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw2_u; + +/* Define the union csr_ipsurx_cpt_mac_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_smac_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw3_u; + +/* Define the union csr_ipsurx_cpt_vlan_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_vlanid : 12; /* [11:0] */ + u32 ipsurx_cpt_vlanid_vld : 1; /* [12] */ + u32 rsv_142 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_vlan_ctrl_u; + +/* Define the union csr_ipsurx_cpt_ip_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_prtl : 8; /* [7:0] */ + u32 ipsurx_cpt_ip_prtl_vld : 1; /* [8] */ + u32 ipsurx_cpt_ip_hip_vld : 1; /* [9] */ + u32 ipsurx_cpt_ip_sip_vld : 1; /* [10] */ + u32 ipsurx_cpt_ip_dip_vld : 1; /* [11] */ + u32 rsv_143 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw0_u; + +/* Define the union csr_ipsurx_cpt_ip_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw1_u; + +/* Define the union csr_ipsurx_cpt_ip_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw2_u; + +/* Define the union csr_ipsurx_cpt_ip_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw3_u; + +/* Define the union csr_ipsurx_cpt_ip_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw4_u; + +/* Define the union csr_ipsurx_cpt_ip_dw5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw5_u; + +/* Define the union csr_ipsurx_cpt_ip_dw6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw6_u; + +/* Define the union csr_ipsurx_cpt_ip_dw7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw7_u; + +/* Define the union csr_ipsurx_cpt_ip_dw8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw8_u; + +/* Define the union csr_ipsurx_cpt_ip_dw9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw9_u; + +/* Define the union csr_ipsurx_cpt_ip_dw10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw10_u; + +/* Define the union csr_ipsurx_cpt_ip_dw11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw11_u; + +/* Define the union csr_ipsurx_cpt_ip_dw12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw12_u; + +/* Define the union csr_ipsurx_cpt_ip_dw13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw13_u; + +/* Define the union csr_ipsurx_cpt_ip_dw14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw14_u; + +/* Define the union csr_ipsurx_cpt_ip_dw15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw15_u; + +/* Define the union csr_ipsurx_cpt_ip_dw16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw16_u; + +/* Define the union csr_ipsurx_cpt_l4_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_l4_hport_vld : 1; /* [0] */ + u32 ipsurx_cpt_l4_sport_vld : 1; /* [1] */ + u32 ipsurx_cpt_l4_dport_vld : 1; /* [2] */ + u32 rsv_144 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_l4_dw0_u; + +/* Define the union csr_ipsurx_cpt_l4_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_l4_sport : 16; /* [15:0] */ + u32 ipsurx_cpt_l4_dport : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_l4_dw1_u; + +/* Define the union csr_ipsurx_cpt_vxlan_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_vxlan_vni : 24; /* [23:0] */ + u32 ipsurx_cpt_vxlan_vni_vld : 1; /* [24] */ + u32 rsv_145 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_vxlan_ctrl_u; + +/* Define the union csr_ipsurx_cpt_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_tx_sumop : 8; /* [7:0] */ + u32 ipsurx_cpt_tx_push_len : 4; /* [11:8] */ + u32 rsv_146 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_tx_ctrl_u; + +/* Define the union csr_ipsurx_cpt_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_hit_cnt_u; + +/* Define the union csr_ipsurx_uncrt_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pif_ovfl_ctrl : 1; /* [0] */ + u32 ipsurx_hdrf_ovfl_ctrl : 1; /* [1] */ + u32 ipsurx_datf_ovfl_ctrl : 1; /* [2] */ + u32 ipsurx_emdf0_ovfl_ctrl : 1; /* [3] */ + u32 ipsurx_emdf1_ovfl_ctrl : 1; /* [4] */ + u32 ipsurx_renqf_ovfl_ctrl : 1; /* [5] */ + u32 ipsurx_rof_ovfl_ctrl : 1; /* [6] */ + u32 ipsurx_lb_crdtf_ovfl_ctrl : 1; /* [7] */ + u32 rsv_147 : 1; /* [8] */ + u32 ipsurx_hdrf_ram_uncrt_ctrl : 1; /* [9] */ + u32 ipsurx_datf_ram_uncrt_ctrl : 1; /* [10] */ + u32 ipsurx_renqf_uncrt_ctrl : 1; /* [11] */ + u32 ipsurx_renqof_uncrt_ctrl : 1; /* [12] */ + u32 ipsurx_vf_idx_ram_uncrt_ctrl : 1; /* [13] */ + u32 ipsurx_vf_ram_uncrt_ctrl : 1; /* [14] */ + u32 ipsurx_emd_ram_uncrt_ctrl : 1; /* [15] */ + u32 ipsurx_roce_opcd_uncrt_ctrl : 1; /* [16] */ + u32 ipsurx_tcam_art_uncrt_ctrl : 1; /* [17] */ + u32 ipsurx_tcam_uncrt_ctrl : 1; /* [18] */ + u32 ipsurx_mag_cut_by_ipsurx_err_ctrl : 1; /* [19] */ + u32 ipsurx_mag_sop_with_err_ctrl : 1; /* [20] */ + u32 ipsurx_mag_sop_sop_err_ctrl : 1; /* [21] */ + u32 ipsurx_perx_sop_with_err_ctrl : 1; /* [22] */ + u32 ipsurx_perx_sop_sop_err_ctrl : 1; /* [23] */ + u32 ipsurx_fatal_err_ctrl : 1; /* [24] */ + u32 rsv_148 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_uncrt_err_ctrl_u; + +/* Define the union csr_ipsurx_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_renqf_af_th : 7; /* [6:0] */ + u32 rsv_149 : 1; /* [7] */ + u32 ipsurx_emdf0_af_th : 4; /* [11:8] */ + u32 ipsurx_emdf1_af_th : 4; /* [15:12] */ + u32 ipsurx_rof_af_th : 6; /* [21:16] */ + u32 rsv_150 : 2; /* [23:22] */ + u32 ipsurx_hdrf_af_th : 7; /* [30:24] */ + u32 rsv_151 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_th_u; + +/* Define the union csr_ipsurx_rammod_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tp_ram_tmod_ctrl : 8; /* [7:0] */ + u32 ipsurx_sp_ram_tmod_ctrl : 7; /* [14:8] */ + u32 ipsurx_mem_power_mode_ctrl : 6; /* [20:15] */ + u32 rsv_152 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rammod_ctrl_u; + +/* Define the union csr_ipsurx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_err_chk_bypass : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_err_chk_bypass_u; + +/* Define the union csr_ipsurx_ram_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_crt_err_inj : 1; /* [0] */ + u32 ipsurx_tcam_uncrt_err_inj : 1; /* [1] */ + u32 ipsurx_tcam_art_crt_err_inj : 1; /* [2] */ + u32 ipsurx_tcam_art_uncrt_err_inj : 1; /* [3] */ + u32 rsv_154 : 4; /* [7:4] */ + u32 ipsurx_roce_opcd_crt_err_inj : 1; /* [8] */ + u32 ipsurx_roce_opcd_uncrt_err_inj : 1; /* [9] */ + u32 rsv_155 : 2; /* [11:10] */ + u32 ipsurx_vf_ram_crt_err_inj : 1; /* [12] */ + u32 ipsurx_vf_ram_uncrt_err_inj : 1; /* [13] */ + u32 ipsurx_vf_idx_ram_crt_err_inj : 1; /* [14] */ + u32 ipsurx_vf_idx_ram_uncrt_err_inj : 1; /* [15] */ + u32 ipsurx_hdrf_ram_crt_err_inj : 1; /* [16] */ + u32 ipsurx_hdrf_ram_uncrt_err_inj : 1; /* [17] */ + u32 ipsurx_datf_ram_crt_err_inj : 1; /* [18] */ + u32 ipsurx_datf_ram_uncrt_err_inj : 1; /* [19] */ + u32 ipsurx_emd_ram_crt_err_inj : 1; /* [20] */ + u32 ipsurx_emd_ram_uncrt_err_inj : 1; /* [21] */ + u32 ipsurx_renqf_ram_crt_err_inj : 1; /* [22] */ + u32 ipsurx_renqf_ram_uncrt_err_inj : 1; /* [23] */ + u32 ipsurx_rof_ram_crt_err_inj : 1; /* [24] */ + u32 ipsurx_rof_ram_uncrt_err_inj : 1; /* [25] */ + u32 rsv_156 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_err_inj_u; + +/* Define the union csr_ipsurx_fifo_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rof_cnt : 6; /* [5:0] */ + u32 ipsurx_rof_empty : 1; /* [6] */ + u32 ipsurx_rof_full : 1; /* [7] */ + u32 ipsurx_rof_af : 1; /* [8] */ + u32 ipsurx_rof_of : 1; /* [9] */ + u32 rsv_157 : 2; /* [11:10] */ + u32 ipsurx_lb_crdtf_cnt : 5; /* [16:12] */ + u32 ipsurx_lb_crdtf_empty : 1; /* [17] */ + u32 ipsurx_lb_crdtf_full : 1; /* [18] */ + u32 ipsurx_lb_crdtf_af : 1; /* [19] */ + u32 ipsurx_lb_crdtf_uf : 1; /* [20] */ + u32 ipsurx_lb_crdtf_of : 1; /* [21] */ + u32 rsv_158 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_sts2_u; + +/* Define the union csr_ipsurx_fifo_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_renqf_cnt : 7; /* [6:0] */ + u32 ipsurx_renqf_empty : 1; /* [7] */ + u32 ipsurx_renqf_full : 1; /* [8] */ + u32 ipsurx_renqf_af : 1; /* [9] */ + u32 ipsurx_renqf_of : 1; /* [10] */ + u32 rsv_159 : 1; /* [11] */ + u32 ipsurx_emdf0_cnt : 5; /* [16:12] */ + u32 ipsurx_emdf0_empty : 1; /* [17] */ + u32 ipsurx_emdf0_full : 1; /* [18] */ + u32 ipsurx_emdf0_af : 1; /* [19] */ + u32 ipsurx_emdf0_uf : 1; /* [20] */ + u32 ipsurx_emdf0_of : 1; /* [21] */ + u32 ipsurx_emdf1_cnt : 5; /* [26:22] */ + u32 ipsurx_emdf1_empty : 1; /* [27] */ + u32 ipsurx_emdf1_full : 1; /* [28] */ + u32 ipsurx_emdf1_af : 1; /* [29] */ + u32 ipsurx_emdf1_uf : 1; /* [30] */ + u32 ipsurx_emdf1_of : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_sts1_u; + +/* Define the union csr_ipsurx_fifo_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pif_cnt : 4; /* [3:0] */ + u32 ipsurx_pif_empty : 1; /* [4] */ + u32 ipsurx_pif_full : 1; /* [5] */ + u32 ipsurx_pif_uf : 1; /* [6] */ + u32 ipsurx_pif_of : 1; /* [7] */ + u32 ipsurx_hdrf_cnt : 7; /* [14:8] */ + u32 ipsurx_hdrf_empty : 1; /* [15] */ + u32 ipsurx_hdrf_full : 1; /* [16] */ + u32 ipsurx_hdrf_af : 1; /* [17] */ + u32 ipsurx_hdrf_of : 1; /* [18] */ + u32 rsv_160 : 1; /* [19] */ + u32 ipsurx_datf_cnt : 6; /* [25:20] */ + u32 ipsurx_datf_empty : 1; /* [26] */ + u32 ipsurx_datf_full : 1; /* [27] */ + u32 ipsurx_datf_of : 1; /* [28] */ + u32 rsv_161 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_sts0_u; + +/* Define the union csr_ipsurx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ucerr_cnt_u; + +/* Define the union csr_ipsurx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_cerr_cnt_u; + +/* Define the union csr_ipsurx_rcv_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rcv_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rcv_bp_cnt_u; + +/* Define the union csr_ipsurx_mfs_gen_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_gen_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_gen_bp_cnt_u; + +/* Define the union csr_ipsurx_renqf_mfs_perx_th_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_renqf_mfs_perx_th_gap : 7; /* [6:0] */ + u32 rsv_162 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_renqf_mfs_perx_th_gap_u; + +/* Define the union csr_ipsurx_lb_rts_crdt_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lb_crdt_sts : 6; /* [5:0] */ + u32 rsv_163 : 2; /* [7:6] */ + u32 ipsurx_rts_crdt_sts : 4; /* [11:8] */ + u32 rsv_164 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lb_rts_crdt_sts_u; + +/* Define the union csr_ipsurx_prm_bp_rand_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_prm_bp_rand_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_prm_bp_rand_cnt_u; + +/* Define the union csr_ipsurx_prm_bp_all_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_prm_bp_all_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_prm_bp_all_cnt_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw0 : 6; /* [5:0] */ + u32 rsv_165 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw0_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw1_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw2_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw3_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw4_u; + +/* Define the union csr_ipsurx_tcam_ctrl_bus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_ctrl_bus : 10; /* [9:0] */ + u32 rsv_166 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_ctrl_bus_u; + +/* Define the union csr_ipsurx_lb_crdtf_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lb_crdtf_af_th : 4; /* [3:0] */ + u32 rsv_167 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lb_crdtf_th_u; + +/* Define the union csr_ipsurx_rx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rx_pkt_cnt_u; + +/* Define the union csr_ipsurx_tx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tx_pkt_cnt_u; + +/* Define the union csr_ipsurx_cnp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cnp_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cnp_pkt_cnt_u; + +/* Define the union csr_ipsurx_ecn_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ecn_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ecn_pkt_cnt_u; + +/* Define the union csr_ipsurx_port_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port_cnt_port0 : 3; /* [2:0] */ + u32 rsv_168 : 1; /* [3] */ + u32 ipsurx_port_cnt_port1 : 3; /* [6:4] */ + u32 rsv_169 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port_cnt_cfg_u; + +/* Define the union csr_ipsurx_port1_cos_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port1_cos_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port1_cos_cnt_u; + +/* Define the union csr_ipsurx_port0_cos_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port0_cos_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port0_cos_cnt_u; + +/* Define the union csr_ipsurx_vtep_ip_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw0_u; + +/* Define the union csr_ipsurx_vtep_ip_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw1_u; + +/* Define the union csr_ipsurx_vtep_ip_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw2_u; + +/* Define the union csr_ipsurx_vtep_ip_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw3_u; + +/* Define the union csr_ipsurx_vtep_ip_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip0_port : 4; /* [3:0] */ + u32 ipsurx_vtep_ip1_port : 4; /* [7:4] */ + u32 ipsurx_vtep_ip2_port : 4; /* [11:8] */ + u32 ipsurx_vtep_ip3_port : 4; /* [15:12] */ + u32 ipsurx_vtep_ip4_port : 4; /* [19:16] */ + u32 ipsurx_vtep_ip5_port : 4; /* [23:20] */ + u32 ipsurx_vtep_ip6_port : 4; /* [27:24] */ + u32 ipsurx_vtep_ip7_port : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_port_u; + +/* Define the union csr_ipsurx_vtep_ip_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip0_vld : 1; /* [0] */ + u32 ipsurx_vtep_ip1_vld : 1; /* [1] */ + u32 ipsurx_vtep_ip2_vld : 1; /* [2] */ + u32 ipsurx_vtep_ip3_vld : 1; /* [3] */ + u32 ipsurx_vtep_ip4_vld : 1; /* [4] */ + u32 ipsurx_vtep_ip5_vld : 1; /* [5] */ + u32 ipsurx_vtep_ip6_vld : 1; /* [6] */ + u32 ipsurx_vtep_ip7_vld : 1; /* [7] */ + u32 ipsurx_vtep_ip0_port_en : 1; /* [8] */ + u32 ipsurx_vtep_ip1_port_en : 1; /* [9] */ + u32 ipsurx_vtep_ip2_port_en : 1; /* [10] */ + u32 ipsurx_vtep_ip3_port_en : 1; /* [11] */ + u32 ipsurx_vtep_ip4_port_en : 1; /* [12] */ + u32 ipsurx_vtep_ip5_port_en : 1; /* [13] */ + u32 ipsurx_vtep_ip6_port_en : 1; /* [14] */ + u32 ipsurx_vtep_ip7_port_en : 1; /* [15] */ + u32 ipsurx_vtep_ip0_tp : 1; /* [16] */ + u32 ipsurx_vtep_ip1_tp : 1; /* [17] */ + u32 ipsurx_vtep_ip2_tp : 1; /* [18] */ + u32 ipsurx_vtep_ip3_tp : 1; /* [19] */ + u32 ipsurx_vtep_ip4_tp : 1; /* [20] */ + u32 ipsurx_vtep_ip5_tp : 1; /* [21] */ + u32 ipsurx_vtep_ip6_tp : 1; /* [22] */ + u32 ipsurx_vtep_ip7_tp : 1; /* [23] */ + u32 rsv_170 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_ctrl_u; + +/* Define the union csr_ipsurx_patn_id_ext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_patn_id_ext : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_patn_id_ext_u; + +/* Define the union csr_ipsurx_patn_id_ofs_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_patn_id_ofs_idx : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_patn_id_ofs_idx_u; + +/* Define the union csr_ipsurx_patn_id_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_patn_id_int : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_patn_id_int_u; + +/* Define the union csr_ipsurx_err_patn_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_patn_id : 4; /* [3:0] */ + u32 rsv_171 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_patn_id_u; + + +#endif // IPSURX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_reg_offset.h new file mode 100644 index 000000000..74df5ca5c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_reg_offset.h @@ -0,0 +1,1469 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_addr_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/09/06 10:44:42 Create file +// ****************************************************************************** + +#ifndef IPSURX_REG_OFFSET_H +#define IPSURX_REG_OFFSET_H + +/* IPSURX_CSR Base address of Module's Register */ +#define CSR_IPSURX_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* IPSURX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_IPSURX_CSR_IPSURX_FPGA_VER_REG (CSR_IPSURX_CSR_BASE + 0x0) /* �汾�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_EMU_VER_REG (CSR_IPSURX_CSR_BASE + 0x4) /* �汾�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_INITCTAB_START_REG (CSR_IPSURX_CSR_BASE + 0x8) /* ���ñ���ʼ��ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INITCTAB_DONE_REG (CSR_IPSURX_CSR_BASE + 0xC) /* ���ñ���ʼ��״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_INT_VECTOR_REG (CSR_IPSURX_CSR_BASE + 0x10) /* Interrupt Vector Register */ +#define CSR_IPSURX_CSR_IPSURX_INT_REG (CSR_IPSURX_CSR_BASE + 0x14) /* Interrupt Data Register */ +#define CSR_IPSURX_CSR_IPSURX_INT_EN_REG (CSR_IPSURX_CSR_BASE + 0x18) /* Interrupt Mask Register */ +#define CSR_IPSURX_CSR_IPSURX_CH_INVLD_ERR_REG (CSR_IPSURX_CSR_BASE + 0x1C) /* ͨ��δʹ�ܵ��յ����ݴ����жϴ���Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_RAM_UCERR_REG (CSR_IPSURX_CSR_BASE + 0x20) /* RAM���ɾ������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CERR_REG (CSR_IPSURX_CSR_BASE + 0x24) /* RAM�ɾ������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_OF_ERR_REG (CSR_IPSURX_CSR_BASE + 0x28) /* FIFO��������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_SOP_EOP_ERR_REG (CSR_IPSURX_CSR_BASE + 0x2C) /* SOP/EOP�������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_PARSE_ERR_REG (CSR_IPSURX_CSR_BASE + 0x30) /* ���Ľ����������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW3_REG (CSR_IPSURX_CSR_BASE + 0x50) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW2_REG (CSR_IPSURX_CSR_BASE + 0x54) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW1_REG (CSR_IPSURX_CSR_BASE + 0x58) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW0_REG (CSR_IPSURX_CSR_BASE + 0x5C) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x80) /* ���Ѱַ���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_TIMEOUT_REG (CSR_IPSURX_CSR_BASE + 0x84) /* ���ѰַTIMEOUT���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_0_REG (CSR_IPSURX_CSR_BASE + 0x88) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_1_REG (CSR_IPSURX_CSR_BASE + 0x8C) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_2_REG (CSR_IPSURX_CSR_BASE + 0x90) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_3_REG (CSR_IPSURX_CSR_BASE + 0x94) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_4_REG (CSR_IPSURX_CSR_BASE + 0x98) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_5_REG (CSR_IPSURX_CSR_BASE + 0x9C) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_6_REG (CSR_IPSURX_CSR_BASE + 0xA0) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_7_REG (CSR_IPSURX_CSR_BASE + 0xA4) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_8_REG (CSR_IPSURX_CSR_BASE + 0xA8) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_9_REG (CSR_IPSURX_CSR_BASE + 0xAC) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_10_REG (CSR_IPSURX_CSR_BASE + 0xB0) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_11_REG (CSR_IPSURX_CSR_BASE + 0xB4) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_12_REG (CSR_IPSURX_CSR_BASE + 0xB8) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_13_REG (CSR_IPSURX_CSR_BASE + 0xBC) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_14_REG (CSR_IPSURX_CSR_BASE + 0xC0) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_15_REG (CSR_IPSURX_CSR_BASE + 0xC4) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x100) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x104) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x108) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x10C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x110) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x114) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x118) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x11C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_8_REG (CSR_IPSURX_CSR_BASE + 0x120) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_9_REG (CSR_IPSURX_CSR_BASE + 0x124) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_10_REG (CSR_IPSURX_CSR_BASE + 0x128) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x12C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x130) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x134) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x138) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x13C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x140) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x144) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x148) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_8_REG (CSR_IPSURX_CSR_BASE + 0x14C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_9_REG (CSR_IPSURX_CSR_BASE + 0x150) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_10_REG (CSR_IPSURX_CSR_BASE + 0x154) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x158) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x15C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x160) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x164) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x168) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x16C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x170) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x174) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_8_REG (CSR_IPSURX_CSR_BASE + 0x178) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_9_REG (CSR_IPSURX_CSR_BASE + 0x17C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_10_REG (CSR_IPSURX_CSR_BASE + 0x180) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x184) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x188) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x18C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x190) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x194) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x198) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x19C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x1A0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_8_REG (CSR_IPSURX_CSR_BASE + 0x1A4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_9_REG (CSR_IPSURX_CSR_BASE + 0x1A8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_10_REG (CSR_IPSURX_CSR_BASE + 0x1AC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_0_REG (CSR_IPSURX_CSR_BASE + 0x1B0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_1_REG (CSR_IPSURX_CSR_BASE + 0x1B4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_2_REG (CSR_IPSURX_CSR_BASE + 0x1B8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_3_REG (CSR_IPSURX_CSR_BASE + 0x1BC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_4_REG (CSR_IPSURX_CSR_BASE + 0x1C0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_5_REG (CSR_IPSURX_CSR_BASE + 0x1C4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_6_REG (CSR_IPSURX_CSR_BASE + 0x1C8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_7_REG (CSR_IPSURX_CSR_BASE + 0x1CC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_8_REG (CSR_IPSURX_CSR_BASE + 0x1D0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_9_REG (CSR_IPSURX_CSR_BASE + 0x1D4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_10_REG (CSR_IPSURX_CSR_BASE + 0x1D8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_0_REG (CSR_IPSURX_CSR_BASE + 0x1DC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_1_REG (CSR_IPSURX_CSR_BASE + 0x1E0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_2_REG (CSR_IPSURX_CSR_BASE + 0x1E4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_3_REG (CSR_IPSURX_CSR_BASE + 0x1E8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_4_REG (CSR_IPSURX_CSR_BASE + 0x1EC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_5_REG (CSR_IPSURX_CSR_BASE + 0x1F0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_6_REG (CSR_IPSURX_CSR_BASE + 0x1F4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_7_REG (CSR_IPSURX_CSR_BASE + 0x1F8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_8_REG (CSR_IPSURX_CSR_BASE + 0x1FC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_9_REG (CSR_IPSURX_CSR_BASE + 0x200) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_10_REG (CSR_IPSURX_CSR_BASE + 0x204) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CH_INVLD_STS_REG (CSR_IPSURX_CSR_BASE + 0x280) /* ͨ����Ч״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_SOP_EOP_ST_REG (CSR_IPSURX_CSR_BASE + 0x284) /* SOP/EOP���״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_SOP_WITH_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x288) /* SOP_WITH_ERR��������� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_ABORT_BF_IPSURX_CNT_REG (CSR_IPSURX_CSR_BASE + 0x28C) /* ABORT_BF_IPSURX��������� \ + */ +#define CSR_IPSURX_CSR_IPSURX_MFS_CUT_BY_IPSURX_CNT_REG (CSR_IPSURX_CSR_BASE + 0x290) /* CUT_BY_IPSURX��������� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_SOP_SOP_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x294) /* SOP_SOP��������� */ +#define CSR_IPSURX_CSR_IPSURX_PERX_SOP_WITH_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x298) /* SOP_WITH_ERR��������� */ +#define CSR_IPSURX_CSR_IPSURX_PERX_ABORT_BF_IPSURX_CNT_REG (CSR_IPSURX_CSR_BASE + 0x29C) /* ABORT_BF_IPSURX��������� \ + */ +#define CSR_IPSURX_CSR_IPSURX_PERX_SOP_SOP_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x2A0) /* SOP_SOP��������� */ +#define CSR_IPSURX_CSR_IPSURX_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x2A4) /* ���ճ��̱������������� */ +#define CSR_IPSURX_CSR_IPSURX_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x2A8) /* ���ճ����������������� */ +#define CSR_IPSURX_CSR_IPSURX_HG2HDR_CFG_REG (CSR_IPSURX_CSR_BASE + 0x300) /* HG2 header���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_0_REG (CSR_IPSURX_CSR_BASE + 0x304) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_1_REG (CSR_IPSURX_CSR_BASE + 0x308) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_2_REG (CSR_IPSURX_CSR_BASE + 0x30C) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_3_REG (CSR_IPSURX_CSR_BASE + 0x310) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_4_REG (CSR_IPSURX_CSR_BASE + 0x314) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_5_REG (CSR_IPSURX_CSR_BASE + 0x318) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_6_REG (CSR_IPSURX_CSR_BASE + 0x31C) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_7_REG (CSR_IPSURX_CSR_BASE + 0x320) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_EVTAG_TPID1_REG (CSR_IPSURX_CSR_BASE + 0x324) /* ETAG/VNTAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_EVTAG_TPID0_REG (CSR_IPSURX_CSR_BASE + 0x328) /* ETAG/VNTAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SVLAN_TPID2_REG (CSR_IPSURX_CSR_BASE + 0x32C) /* SVLAN TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SVLAN_TPID1_REG (CSR_IPSURX_CSR_BASE + 0x330) /* SVLAN TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SVLAN_TPID0_REG (CSR_IPSURX_CSR_BASE + 0x334) /* SVLAN TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CVLAN_TPID2_REG (CSR_IPSURX_CSR_BASE + 0x338) /* CVLAN-TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CVLAN_TPID1_REG (CSR_IPSURX_CSR_BASE + 0x33C) /* CVLAN-TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CVLAN_TPID0_REG (CSR_IPSURX_CSR_BASE + 0x340) /* CVLAN-TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_P8021_PRI_REG (CSR_IPSURX_CSR_BASE + 0x344) /* 802.1���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_0_REG (CSR_IPSURX_CSR_BASE + 0x348) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_1_REG (CSR_IPSURX_CSR_BASE + 0x34C) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_2_REG (CSR_IPSURX_CSR_BASE + 0x350) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_3_REG (CSR_IPSURX_CSR_BASE + 0x354) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_4_REG (CSR_IPSURX_CSR_BASE + 0x358) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_5_REG (CSR_IPSURX_CSR_BASE + 0x35C) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_6_REG (CSR_IPSURX_CSR_BASE + 0x360) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_7_REG (CSR_IPSURX_CSR_BASE + 0x364) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_8_REG (CSR_IPSURX_CSR_BASE + 0x368) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_9_REG (CSR_IPSURX_CSR_BASE + 0x36C) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_10_REG (CSR_IPSURX_CSR_BASE + 0x370) /* 802.3��󳤶����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_JUMBO_CFG_REG (CSR_IPSURX_CSR_BASE + 0x374) /* 802.3Jumbo֡���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_L2_DMAC_ETH_CHK_EN_REG \ + (CSR_IPSURX_CSR_BASE + 0x378) /* L2����DMAC/ETH���ʹ�����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RTN_TS_EN_REG (CSR_IPSURX_CSR_BASE + 0x37C) /* �ش�ʱ�����ļĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RTN_TS_REG (CSR_IPSURX_CSR_BASE + 0x380) /* �ش�ʱ�����ļĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x384) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x388) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x38C) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x390) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x394) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x398) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x39C) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x3A0) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IGMPV4_DIP_CHK_EN_REG (CSR_IPSURX_CSR_BASE + 0x3A4) /* IGMPv4 DIP�����ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x3A8) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x3AC) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x3B0) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x3B4) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x3B8) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x3BC) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x3C0) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x3C4) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x3C8) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x3CC) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x3D0) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x3D4) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x3D8) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x3DC) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x3E0) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x3E4) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x3E8) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x3EC) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x3F0) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x3F4) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x3F8) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x3FC) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x400) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x404) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_8_REG (CSR_IPSURX_CSR_BASE + 0x408) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_9_REG (CSR_IPSURX_CSR_BASE + 0x40C) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_10_REG (CSR_IPSURX_CSR_BASE + 0x410) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_11_REG (CSR_IPSURX_CSR_BASE + 0x414) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_12_REG (CSR_IPSURX_CSR_BASE + 0x418) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_13_REG (CSR_IPSURX_CSR_BASE + 0x41C) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_14_REG (CSR_IPSURX_CSR_BASE + 0x420) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_15_REG (CSR_IPSURX_CSR_BASE + 0x424) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_SPEC_MC_REG (CSR_IPSURX_CSR_BASE + 0x428) /* IPv6ָ���ಥ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_BTH_REG (CSR_IPSURX_CSR_BASE + 0x42C) /* RoCE����BTHͷ���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x430) /* RoCEV2Ŀ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_NATT_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x434) /* NATTĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_VXLAN_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x438) /* VXLANĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_VXLAN_GPE_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x43C) /* VXLAN GPEĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_GENEVE_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x440) /* GENEVEĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_NP_REG (CSR_IPSURX_CSR_BASE + 0x444) /* IPv4 Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_NP_REG (CSR_IPSURX_CSR_BASE + 0x448) /* IPv6 Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_ETHERNET_NP_REG (CSR_IPSURX_CSR_BASE + 0x44C) /* Ethernet Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_IOAM_NP_REG (CSR_IPSURX_CSR_BASE + 0x450) /* IOAM Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_INT_NP_REG (CSR_IPSURX_CSR_BASE + 0x454) /* INT Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_NSH_NP_REG (CSR_IPSURX_CSR_BASE + 0x458) /* NSH Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_AH_NP_REG (CSR_IPSURX_CSR_BASE + 0x45C) /* AH Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_ESP_NP_REG (CSR_IPSURX_CSR_BASE + 0x460) /* ESP Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_ROB_OPT_CLASS_REG (CSR_IPSURX_CSR_BASE + 0x464) /* ROB���������ĵ�Option Class */ +#define CSR_IPSURX_CSR_IPSURX_PPOP_OPT_CLASS_REG (CSR_IPSURX_CSR_BASE + 0x468) /* PPOP���ĵ�Option Class */ +#define CSR_IPSURX_CSR_IPSURX_TELEMETRY_EN_REG (CSR_IPSURX_CSR_BASE + 0x470) /* Telemetry����ʹ�� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_COCO_WITH_TS_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x474) /* ��ʱ����TCP COCO DW0���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_COCO_WITHOUT_TS_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x478) /* ����ʱ����TCP COCO DW0���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_COCO_DW0_MASK_REG (CSR_IPSURX_CSR_BASE + 0x47C) /* TCP COCO DW0�������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_COALESCE_PKT_FWD_ACT_CTRL_REG \ + (CSR_IPSURX_CSR_BASE + 0x480) /* �ۺϱ���ת����Ϊ���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_HCAP_VAL_REG (CSR_IPSURX_CSR_BASE + 0x484) /* HCAP����VAL���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_HCAP_PRI_REG (CSR_IPSURX_CSR_BASE + 0x488) /* HCAP�������ȼ����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_0_REG (CSR_IPSURX_CSR_BASE + 0x48C) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_1_REG (CSR_IPSURX_CSR_BASE + 0x490) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_2_REG (CSR_IPSURX_CSR_BASE + 0x494) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_3_REG (CSR_IPSURX_CSR_BASE + 0x498) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_4_REG (CSR_IPSURX_CSR_BASE + 0x49C) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_5_REG (CSR_IPSURX_CSR_BASE + 0x4A0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_6_REG (CSR_IPSURX_CSR_BASE + 0x4A4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_7_REG (CSR_IPSURX_CSR_BASE + 0x4A8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_8_REG (CSR_IPSURX_CSR_BASE + 0x4AC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_9_REG (CSR_IPSURX_CSR_BASE + 0x4B0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_10_REG (CSR_IPSURX_CSR_BASE + 0x4B4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_0_REG (CSR_IPSURX_CSR_BASE + 0x4B8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_1_REG (CSR_IPSURX_CSR_BASE + 0x4BC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_2_REG (CSR_IPSURX_CSR_BASE + 0x4C0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_3_REG (CSR_IPSURX_CSR_BASE + 0x4C4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_4_REG (CSR_IPSURX_CSR_BASE + 0x4C8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_5_REG (CSR_IPSURX_CSR_BASE + 0x4CC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_6_REG (CSR_IPSURX_CSR_BASE + 0x4D0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_7_REG (CSR_IPSURX_CSR_BASE + 0x4D4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_8_REG (CSR_IPSURX_CSR_BASE + 0x4D8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_9_REG (CSR_IPSURX_CSR_BASE + 0x4DC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_10_REG (CSR_IPSURX_CSR_BASE + 0x4E0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_EXT_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x4E4) /* IPv6��չͷ���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_BGP_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x4E8) /* BGPĿ��TCP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_OPT_DW0_REG (CSR_IPSURX_CSR_BASE + 0x4EC) /* TCP����option��һ��DW�ȶ�����ֵ */ +#define CSR_IPSURX_CSR_IPSURX_ESP_PRTL_TYPE_REG (CSR_IPSURX_CSR_BASE + 0x4F0) /* ESP Protocol Type�� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW0_REG (CSR_IPSURX_CSR_BASE + 0x500) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW1_REG (CSR_IPSURX_CSR_BASE + 0x504) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW2_REG (CSR_IPSURX_CSR_BASE + 0x508) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW3_REG (CSR_IPSURX_CSR_BASE + 0x50C) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x510) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW1_REG \ + (CSR_IPSURX_CSR_BASE + 0x514) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW2_REG \ + (CSR_IPSURX_CSR_BASE + 0x518) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW3_REG \ + (CSR_IPSURX_CSR_BASE + 0x51C) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x520) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW1_REG \ + (CSR_IPSURX_CSR_BASE + 0x524) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW2_REG \ + (CSR_IPSURX_CSR_BASE + 0x528) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW3_REG \ + (CSR_IPSURX_CSR_BASE + 0x52C) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_CRC_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x530) /* IPSURX CRC���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_ICRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x534) /* RoCE ICRC��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_ICRC_MN_REG (CSR_IPSURX_CSR_BASE + 0x538) /* RoCE����ICRC Magic Numberֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x53C) /* FCoE����CRC ��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CRC_MN_REG (CSR_IPSURX_CSR_BASE + 0x540) /* FCoE����CRC Magic Numberֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_SCTP_CRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x544) /* SCTP����CRC ��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_DIFX_CRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x548) /* DIF/DIX CRC16 ��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_MAG_DROP_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x54C) /* MAG������������������ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROB_PPOP_EN_REG (CSR_IPSURX_CSR_BASE + 0x550) /* ROB/PPOP����ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_PORT_MAP_EN_REG (CSR_IPSURX_CSR_BASE + 0x554) /* ���Ķ˿�ӳ��ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_PORT_MAP_REG (CSR_IPSURX_CSR_BASE + 0x558) /* ���Ķ˿�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L2F_OTH_REG \ + (CSR_IPSURX_CSR_BASE + 0x55C) /* L2 Final�������������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_0_REG (CSR_IPSURX_CSR_BASE + 0x560) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_1_REG (CSR_IPSURX_CSR_BASE + 0x564) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_2_REG (CSR_IPSURX_CSR_BASE + 0x568) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_3_REG (CSR_IPSURX_CSR_BASE + 0x56C) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_0_REG (CSR_IPSURX_CSR_BASE + 0x570) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_1_REG (CSR_IPSURX_CSR_BASE + 0x574) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_2_REG (CSR_IPSURX_CSR_BASE + 0x578) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_3_REG (CSR_IPSURX_CSR_BASE + 0x57C) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_FC_REG (CSR_IPSURX_CSR_BASE + 0x580) /* FC�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_EXT_SUMOP_REG (CSR_IPSURX_CSR_BASE + 0x584) /* ROCE��չЭ��SUMOP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SR_SUMOP_REG (CSR_IPSURX_CSR_BASE + 0x588) /* Դ·�ɹ�����·��SUMOP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_EN_REG (CSR_IPSURX_CSR_BASE + 0x58C) /* ���Ʊ���ʶ��ʹ�����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_EXT_LEN_EXC_SUMOP_REG \ + (CSR_IPSURX_CSR_BASE + 0x590) /* ROCE��չЭ�鳬�������SUMOP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_DRC_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x594) /* ROCE DRC������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_DMAC_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x600) /* Ŀ��MACΪ0�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_SMAC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x604) /* ԴMAC�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_DA_SA_EQUAL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x608) /* ԴĿ��MAC��ȱ��ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_ETH_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x60C) /* ETH_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_DMAC_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x610) /* Ŀ��MACΪ0�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_SMAC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x614) /* ԴMAC�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_DA_SA_EQUAL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x618) /* ԴĿ��MAC��ȱ��ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_ETH_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x61C) /* ETH_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x620) /* IPV4_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_IHL_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x624) /* IPV4_IHL_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_SIP_DIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x628) /* IPV4_SIP_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x62C) /* IPV4_SIP_MC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x630) /* IPV4_SIP_LB_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x634) /* IPV4_DIP_LB_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DIP_ZERO_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x638) /* IPV4_DIP_ZERO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x63C) /* IPV4_DIP_RSV_ADDR_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x640) /* IPV4_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_UDP_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x644) /* IPV4_UDP_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x648) /* IPV4_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x64C) /* IPV6_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_SIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x650) /* IPV6_SIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x654) /* IPV6_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x658) /* IPV6_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x65C) /* IPV4_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_IHL_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x660) /* IPV4_IHL_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_SIP_DIP_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x664) /* IPV4_SIP_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x668) /* IPV4_SIP_MC_ILGL������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x66C) /* IPV4_SIP_LB_ILGL������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x670) /* IPV4_DIP_LB_ILGL������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_DIP_ZERO_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x674) /* IPV4_DIP_ZERO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x678) /* IPV4_DIP_RSV_ADDR_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x67C) /* IPV4_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_UDP_LEN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x680) /* IPV4_UDP_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x684) /* IPV4_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x688) /* IPV6_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_SIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x68C) /* IPV6_SIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_DIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x690) /* IPV6_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x694) /* IPV6_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_LAND_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x698) /* TCP_LAND_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_DO_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x69C) /* TCP_DO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_SYN_FIN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6A0) /* TCP_SYN_FIN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_NO_FLAG_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6A4) /* TCP_NO_FLAG_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_FIN_ACK_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6A8) /* TCP_FIN_ACK_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_ACK_RST_SYN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6AC) /* TCP_ACK_RST_SYN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6B0) /* TCP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_UDP_CS_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6B4) /* IPv6 UDP_CS_ZERO������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_UDP_CS_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6B8) /* IPv6 UDP_CS_ZERO������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_UDP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6BC) /* UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IGMP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6C0) /* IGMP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ICMPV4_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6C4) /* ICMPV4_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ICMPV6_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6C8) /* ICMPV6_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_SCTP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6CC) /* SCTP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_DGID_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6D0) /* ROCEV1_DGID_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_SGID_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6D4) /* ROCEV1_SGID_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_IPVER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6D8) /* ROCEV1_IPVER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_NXHDR_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6DC) /* ROCEV1_NXHDR_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_PAYLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6E0) /* ROCEV1_PAYLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_FRAG_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6E4) /* ROCEV2_IPV4_FRAG_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_UDP_CS_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6E8) /* ROCEV2_IPV4_UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_UDP_CS_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6EC) /* ROCEV2_IPV6_UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_TVER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6F0) /* ROCE_TVER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_PKEY_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6F4) /* ROCE_PKEY_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_DQP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6F8) /* ROCE_DQP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_PADCNT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6FC) /* ROCE_PADCNT_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_VA_8B_ALIGN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x700) /* ROCE_VA_8B_ALIGN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_DMALEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x704) /* ROCE_DMALEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_OPCODE_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x708) /* ROCE_OPCODE_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IB_ICRC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x70C) /* IB_ICRC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_FC_CRC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x710) /* FC_CRC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TO_UP_PKT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x714) /* TO UP����У���������� */ +#define CSR_IPSURX_CSR_IPSURX_TO_BMC_ONLY_PKT_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x718) /* TO BMC ONLY����У���������� */ +#define CSR_IPSURX_CSR_IPSURX_LLC_SNAP_ENC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x71C) /* LLC_SNAP_ENC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ETH_TYPE_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x720) /* ETH_TYPE_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_VXLAN_GPE_OTHER_VER_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x724) /* VXLAN_GPE_OTHER_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_GENEVE_OTHER_VER_CNT_REG (CSR_IPSURX_CSR_BASE + 0x728) /* GENEVE_OTHER_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NSH_OTHER_VER_CNT_REG (CSR_IPSURX_CSR_BASE + 0x72C) /* NSH_OTHER_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NSH_LEN_CNT_REG (CSR_IPSURX_CSR_BASE + 0x730) /* NSH_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_NVGRE_CVLAN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x734) /* nvGRE�����ڲ�CVLAN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_HCAP_MD_SIZE_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x738) /* HCAP����MD_SIZE_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_DROP_MFS_PKT_CNT_REG (CSR_IPSURX_CSR_BASE + 0x73C) /* IPSURX��ڶ���MFS���ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_LEN_4B_ALIGN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x740) /* ROCE/FC/SCTP����payload���ȷ�4B��������� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_UDP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x744) /* UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NVGRE_CRKS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x748) /* NVGRE_CRKS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_HDR_LEN_MIN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x74C) /* PKT_HDR_LEN_MIN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_PAUSE_PKT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x750) /* PAUSE_PKT_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_PFC_PKT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x754) /* PFC_PKT_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_EXT_LEN_EXC_CNT_REG (CSR_IPSURX_CSR_BASE + 0x758) /* ROCE_EXT_LEN_EXC������ */ +#define CSR_IPSURX_CSR_IPSURX_IPSEC_AUTH_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x75C) /* IPSEC_AUTH_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NATT_IPV4_UDP_CS_ZERO_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x760) /* NATT_IPV4_UDP_CS_ZERO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TX_CPT_PKT_DROP_CNT_REG (CSR_IPSURX_CSR_BASE + 0x764) /* TX_CPT_PKT_DROP������ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x800) /* NCSI���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_FILTER_MNG_REG (CSR_IPSURX_CSR_BASE + 0x804) /* NCSI FILTER�����Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x808) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x80C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x810) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x814) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x818) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x81C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x820) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x824) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x828) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x82C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x830) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x834) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x838) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x83C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x840) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x844) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x848) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x84C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x850) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x854) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x858) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x85C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x860) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x864) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x868) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x86C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x870) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x874) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x878) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x87C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x880) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x884) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN_EN_REG (CSR_IPSURX_CSR_BASE + 0x888) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x88C) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x890) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x894) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x898) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x89C) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8A0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8A4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8A8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8AC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8B0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8B4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8B8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8BC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8C0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8C4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8C8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8CC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8D0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8D4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8D8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8DC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8E0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8E4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8E8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8EC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8F0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8F4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8F8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8FC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x900) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x904) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x908) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x90C) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x910) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x914) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x918) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x91C) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x920) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x924) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x928) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x92C) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x930) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x934) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x938) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x93C) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x940) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x944) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x948) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x94C) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x950) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x954) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x958) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_EN_REG (CSR_IPSURX_CSR_BASE + 0x95C) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x960) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x964) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x968) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x96C) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x970) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x974) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x978) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x97C) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x980) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x984) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x988) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x98C) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x990) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x994) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x998) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x99C) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x9A0) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x9A4) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x9A8) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x9AC) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x9B0) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x9B4) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x9B8) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x9BC) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x9C0) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x9C4) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x9C8) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x9CC) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_0_REG (CSR_IPSURX_CSR_BASE + 0xA00) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_1_REG (CSR_IPSURX_CSR_BASE + 0xA04) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_2_REG (CSR_IPSURX_CSR_BASE + 0xA08) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_3_REG (CSR_IPSURX_CSR_BASE + 0xA0C) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_4_REG (CSR_IPSURX_CSR_BASE + 0xA10) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_5_REG (CSR_IPSURX_CSR_BASE + 0xA14) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_6_REG (CSR_IPSURX_CSR_BASE + 0xA18) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_7_REG (CSR_IPSURX_CSR_BASE + 0xA1C) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_KEY_SEL_REG (CSR_IPSURX_CSR_BASE + 0xA20) /* TCAM KEYѡ�����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xA24) /* TCAM���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_MBIST_DONE_REG (CSR_IPSURX_CSR_BASE + 0xA28) /* TCAM MBIST���״̬�ź� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_0_REG (CSR_IPSURX_CSR_BASE + 0xA2C) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_1_REG (CSR_IPSURX_CSR_BASE + 0xA30) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_2_REG (CSR_IPSURX_CSR_BASE + 0xA34) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_3_REG (CSR_IPSURX_CSR_BASE + 0xA38) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_4_REG (CSR_IPSURX_CSR_BASE + 0xA3C) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_5_REG (CSR_IPSURX_CSR_BASE + 0xA40) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_6_REG (CSR_IPSURX_CSR_BASE + 0xA44) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_7_REG (CSR_IPSURX_CSR_BASE + 0xA48) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xA4C) /* VF Table���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PORT_ERID_REG (CSR_IPSURX_CSR_BASE + 0xA50) /* PORT->ERID����Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_OPCD_TB_REG (CSR_IPSURX_CSR_BASE + 0xA54) /* TCP OPCODE�������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_MBIST_MEM_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0xA58) /* TCAM MBIST MEM��������� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_MBIST_CMP_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0xA5C) /* TCAM MBISTƥ���������� */ +#define CSR_IPSURX_CSR_IPSURX_LB_PORT_ERID_REG (CSR_IPSURX_CSR_BASE + 0xA60) /* ��������PORT->ERID����Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_HIT_CNT_REG (CSR_IPSURX_CSR_BASE + 0xA64) /* Ӳ��TCAM�������м����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xA68) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xA6C) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xA70) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xA74) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xA78) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xA7C) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xA80) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xA84) /* ���͸�CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xA88) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xA8C) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xA90) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xA94) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xA98) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xA9C) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xAA0) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xAA4) /* ���͸�CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_VF_HIT_SEL_VF_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0xAA8) /* Ӳ��VF������к�SELΪVF�Ĵ��������� */ +#define CSR_IPSURX_CSR_IPSURX_VF_HIT_SEL_OUT_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0xAAC) /* Ӳ��VF������к�SELΪOUTPUT PORT�Ĵ��������� */ +#define CSR_IPSURX_CSR_IPSURX_WOL_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xB00) /* WOL���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_CTRL1_REG (CSR_IPSURX_CSR_BASE + 0xB04) /* WOL TYPE1���ļ��RULE���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_CTRL0_REG (CSR_IPSURX_CSR_BASE + 0xB08) /* WOL TYPE1���ļ��RULE���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB0C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB10) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB14) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB18) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB1C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB20) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB24) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB28) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB2C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB30) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB34) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB38) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB3C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB40) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB44) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB48) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB4C) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB50) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB54) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB58) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB5C) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB60) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB64) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB68) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB6C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB70) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB74) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB78) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB7C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB80) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB84) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB88) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB8C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB90) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB94) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB98) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB9C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xBA0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xBA4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xBA8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xBAC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xBB0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xBB4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xBB8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xBBC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xBC0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xBC4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xBC8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xBCC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xBD0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xBD4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xBD8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xBDC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xBE0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xBE4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xBE8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xBEC) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xBF0) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xBF4) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xBF8) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xBFC) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC00) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xC04) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xC08) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC0C) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC10) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC14) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC18) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC1C) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC20) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xC24) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xC28) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xC2C) /* WOL TYPE2���ļ����ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC30) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC34) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC38) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC3C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC40) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC44) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC48) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC4C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC50) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC54) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC58) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC5C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC60) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC64) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC68) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC6C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC70) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC74) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC78) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC7C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC80) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC84) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC88) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC8C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_0_REG (CSR_IPSURX_CSR_BASE + 0xC90) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_1_REG (CSR_IPSURX_CSR_BASE + 0xC94) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_2_REG (CSR_IPSURX_CSR_BASE + 0xC98) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_3_REG (CSR_IPSURX_CSR_BASE + 0xC9C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_4_REG (CSR_IPSURX_CSR_BASE + 0xCA0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_5_REG (CSR_IPSURX_CSR_BASE + 0xCA4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_0_REG (CSR_IPSURX_CSR_BASE + 0xCA8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_1_REG (CSR_IPSURX_CSR_BASE + 0xCAC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_2_REG (CSR_IPSURX_CSR_BASE + 0xCB0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_3_REG (CSR_IPSURX_CSR_BASE + 0xCB4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_4_REG (CSR_IPSURX_CSR_BASE + 0xCB8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_5_REG (CSR_IPSURX_CSR_BASE + 0xCBC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_0_REG (CSR_IPSURX_CSR_BASE + 0xCC0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_1_REG (CSR_IPSURX_CSR_BASE + 0xCC4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_2_REG (CSR_IPSURX_CSR_BASE + 0xCC8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_3_REG (CSR_IPSURX_CSR_BASE + 0xCCC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_4_REG (CSR_IPSURX_CSR_BASE + 0xCD0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_5_REG (CSR_IPSURX_CSR_BASE + 0xCD4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_0_REG (CSR_IPSURX_CSR_BASE + 0xCD8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_1_REG (CSR_IPSURX_CSR_BASE + 0xCDC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_2_REG (CSR_IPSURX_CSR_BASE + 0xCE0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_3_REG (CSR_IPSURX_CSR_BASE + 0xCE4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_4_REG (CSR_IPSURX_CSR_BASE + 0xCE8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_5_REG (CSR_IPSURX_CSR_BASE + 0xCEC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_0_REG (CSR_IPSURX_CSR_BASE + 0xCF0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_1_REG (CSR_IPSURX_CSR_BASE + 0xCF4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_2_REG (CSR_IPSURX_CSR_BASE + 0xCF8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_3_REG (CSR_IPSURX_CSR_BASE + 0xCFC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_4_REG (CSR_IPSURX_CSR_BASE + 0xD00) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_5_REG (CSR_IPSURX_CSR_BASE + 0xD04) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_0_REG (CSR_IPSURX_CSR_BASE + 0xD08) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_1_REG (CSR_IPSURX_CSR_BASE + 0xD0C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_2_REG (CSR_IPSURX_CSR_BASE + 0xD10) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_3_REG (CSR_IPSURX_CSR_BASE + 0xD14) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_4_REG (CSR_IPSURX_CSR_BASE + 0xD18) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_5_REG (CSR_IPSURX_CSR_BASE + 0xD1C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_0_REG (CSR_IPSURX_CSR_BASE + 0xD20) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_1_REG (CSR_IPSURX_CSR_BASE + 0xD24) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_2_REG (CSR_IPSURX_CSR_BASE + 0xD28) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_3_REG (CSR_IPSURX_CSR_BASE + 0xD2C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_4_REG (CSR_IPSURX_CSR_BASE + 0xD30) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_5_REG (CSR_IPSURX_CSR_BASE + 0xD34) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_0_REG (CSR_IPSURX_CSR_BASE + 0xD38) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_1_REG (CSR_IPSURX_CSR_BASE + 0xD3C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_2_REG (CSR_IPSURX_CSR_BASE + 0xD40) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_3_REG (CSR_IPSURX_CSR_BASE + 0xD44) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_4_REG (CSR_IPSURX_CSR_BASE + 0xD48) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_5_REG (CSR_IPSURX_CSR_BASE + 0xD4C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_0_REG (CSR_IPSURX_CSR_BASE + 0xD50) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_1_REG (CSR_IPSURX_CSR_BASE + 0xD54) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_2_REG (CSR_IPSURX_CSR_BASE + 0xD58) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_3_REG (CSR_IPSURX_CSR_BASE + 0xD5C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_4_REG (CSR_IPSURX_CSR_BASE + 0xD60) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_5_REG (CSR_IPSURX_CSR_BASE + 0xD64) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_0_REG (CSR_IPSURX_CSR_BASE + 0xD68) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_1_REG (CSR_IPSURX_CSR_BASE + 0xD6C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_2_REG (CSR_IPSURX_CSR_BASE + 0xD70) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_3_REG (CSR_IPSURX_CSR_BASE + 0xD74) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_4_REG (CSR_IPSURX_CSR_BASE + 0xD78) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_5_REG (CSR_IPSURX_CSR_BASE + 0xD7C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_0_REG (CSR_IPSURX_CSR_BASE + 0xD80) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_1_REG (CSR_IPSURX_CSR_BASE + 0xD84) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_2_REG (CSR_IPSURX_CSR_BASE + 0xD88) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_3_REG (CSR_IPSURX_CSR_BASE + 0xD8C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_4_REG (CSR_IPSURX_CSR_BASE + 0xD90) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_5_REG (CSR_IPSURX_CSR_BASE + 0xD94) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_0_REG (CSR_IPSURX_CSR_BASE + 0xD98) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_1_REG (CSR_IPSURX_CSR_BASE + 0xD9C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_2_REG (CSR_IPSURX_CSR_BASE + 0xDA0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_3_REG (CSR_IPSURX_CSR_BASE + 0xDA4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_4_REG (CSR_IPSURX_CSR_BASE + 0xDA8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_5_REG (CSR_IPSURX_CSR_BASE + 0xDAC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_0_REG (CSR_IPSURX_CSR_BASE + 0xDB0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_1_REG (CSR_IPSURX_CSR_BASE + 0xDB4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_2_REG (CSR_IPSURX_CSR_BASE + 0xDB8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_3_REG (CSR_IPSURX_CSR_BASE + 0xDBC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_4_REG (CSR_IPSURX_CSR_BASE + 0xDC0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_5_REG (CSR_IPSURX_CSR_BASE + 0xDC4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_0_REG (CSR_IPSURX_CSR_BASE + 0xDC8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_1_REG (CSR_IPSURX_CSR_BASE + 0xDCC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_2_REG (CSR_IPSURX_CSR_BASE + 0xDD0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_3_REG (CSR_IPSURX_CSR_BASE + 0xDD4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_4_REG (CSR_IPSURX_CSR_BASE + 0xDD8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_5_REG (CSR_IPSURX_CSR_BASE + 0xDDC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_0_REG (CSR_IPSURX_CSR_BASE + 0xDE0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_1_REG (CSR_IPSURX_CSR_BASE + 0xDE4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_2_REG (CSR_IPSURX_CSR_BASE + 0xDE8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_3_REG (CSR_IPSURX_CSR_BASE + 0xDEC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_4_REG (CSR_IPSURX_CSR_BASE + 0xDF0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_5_REG (CSR_IPSURX_CSR_BASE + 0xDF4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_0_REG (CSR_IPSURX_CSR_BASE + 0xDF8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_1_REG (CSR_IPSURX_CSR_BASE + 0xDFC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_2_REG (CSR_IPSURX_CSR_BASE + 0xE00) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_3_REG (CSR_IPSURX_CSR_BASE + 0xE04) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_4_REG (CSR_IPSURX_CSR_BASE + 0xE08) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_5_REG (CSR_IPSURX_CSR_BASE + 0xE0C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_0_REG (CSR_IPSURX_CSR_BASE + 0xE10) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_1_REG (CSR_IPSURX_CSR_BASE + 0xE14) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_2_REG (CSR_IPSURX_CSR_BASE + 0xE18) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_3_REG (CSR_IPSURX_CSR_BASE + 0xE1C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_4_REG (CSR_IPSURX_CSR_BASE + 0xE20) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_5_REG (CSR_IPSURX_CSR_BASE + 0xE24) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_0_REG (CSR_IPSURX_CSR_BASE + 0xE28) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_1_REG (CSR_IPSURX_CSR_BASE + 0xE2C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_2_REG (CSR_IPSURX_CSR_BASE + 0xE30) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_3_REG (CSR_IPSURX_CSR_BASE + 0xE34) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_4_REG (CSR_IPSURX_CSR_BASE + 0xE38) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_5_REG (CSR_IPSURX_CSR_BASE + 0xE3C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_0_REG (CSR_IPSURX_CSR_BASE + 0xE40) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_1_REG (CSR_IPSURX_CSR_BASE + 0xE44) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_2_REG (CSR_IPSURX_CSR_BASE + 0xE48) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_3_REG (CSR_IPSURX_CSR_BASE + 0xE4C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_4_REG (CSR_IPSURX_CSR_BASE + 0xE50) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_5_REG (CSR_IPSURX_CSR_BASE + 0xE54) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_0_REG (CSR_IPSURX_CSR_BASE + 0xE58) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_1_REG (CSR_IPSURX_CSR_BASE + 0xE5C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_2_REG (CSR_IPSURX_CSR_BASE + 0xE60) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_3_REG (CSR_IPSURX_CSR_BASE + 0xE64) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_4_REG (CSR_IPSURX_CSR_BASE + 0xE68) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_5_REG (CSR_IPSURX_CSR_BASE + 0xE6C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_0_REG (CSR_IPSURX_CSR_BASE + 0xE70) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_1_REG (CSR_IPSURX_CSR_BASE + 0xE74) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_2_REG (CSR_IPSURX_CSR_BASE + 0xE78) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_3_REG (CSR_IPSURX_CSR_BASE + 0xE7C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_4_REG (CSR_IPSURX_CSR_BASE + 0xE80) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_5_REG (CSR_IPSURX_CSR_BASE + 0xE84) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_0_REG (CSR_IPSURX_CSR_BASE + 0xE88) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_1_REG (CSR_IPSURX_CSR_BASE + 0xE8C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_2_REG (CSR_IPSURX_CSR_BASE + 0xE90) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_3_REG (CSR_IPSURX_CSR_BASE + 0xE94) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_4_REG (CSR_IPSURX_CSR_BASE + 0xE98) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_5_REG (CSR_IPSURX_CSR_BASE + 0xE9C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_0_REG (CSR_IPSURX_CSR_BASE + 0xEA0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_1_REG (CSR_IPSURX_CSR_BASE + 0xEA4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_2_REG (CSR_IPSURX_CSR_BASE + 0xEA8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_3_REG (CSR_IPSURX_CSR_BASE + 0xEAC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_4_REG (CSR_IPSURX_CSR_BASE + 0xEB0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_5_REG (CSR_IPSURX_CSR_BASE + 0xEB4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_0_REG (CSR_IPSURX_CSR_BASE + 0xEB8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_1_REG (CSR_IPSURX_CSR_BASE + 0xEBC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_2_REG (CSR_IPSURX_CSR_BASE + 0xEC0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_3_REG (CSR_IPSURX_CSR_BASE + 0xEC4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_4_REG (CSR_IPSURX_CSR_BASE + 0xEC8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_5_REG (CSR_IPSURX_CSR_BASE + 0xECC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_0_REG (CSR_IPSURX_CSR_BASE + 0xED0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_1_REG (CSR_IPSURX_CSR_BASE + 0xED4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_2_REG (CSR_IPSURX_CSR_BASE + 0xED8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_3_REG (CSR_IPSURX_CSR_BASE + 0xEDC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_4_REG (CSR_IPSURX_CSR_BASE + 0xEE0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_5_REG (CSR_IPSURX_CSR_BASE + 0xEE4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_0_REG (CSR_IPSURX_CSR_BASE + 0xEE8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_1_REG (CSR_IPSURX_CSR_BASE + 0xEEC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_2_REG (CSR_IPSURX_CSR_BASE + 0xEF0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_3_REG (CSR_IPSURX_CSR_BASE + 0xEF4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_4_REG (CSR_IPSURX_CSR_BASE + 0xEF8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_5_REG (CSR_IPSURX_CSR_BASE + 0xEFC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_0_REG (CSR_IPSURX_CSR_BASE + 0xF00) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_1_REG (CSR_IPSURX_CSR_BASE + 0xF04) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_2_REG (CSR_IPSURX_CSR_BASE + 0xF08) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_3_REG (CSR_IPSURX_CSR_BASE + 0xF0C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_4_REG (CSR_IPSURX_CSR_BASE + 0xF10) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_5_REG (CSR_IPSURX_CSR_BASE + 0xF14) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_0_REG (CSR_IPSURX_CSR_BASE + 0xF18) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_1_REG (CSR_IPSURX_CSR_BASE + 0xF1C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_2_REG (CSR_IPSURX_CSR_BASE + 0xF20) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_3_REG (CSR_IPSURX_CSR_BASE + 0xF24) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_4_REG (CSR_IPSURX_CSR_BASE + 0xF28) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_5_REG (CSR_IPSURX_CSR_BASE + 0xF2C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_0_REG (CSR_IPSURX_CSR_BASE + 0xF30) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_1_REG (CSR_IPSURX_CSR_BASE + 0xF34) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_2_REG (CSR_IPSURX_CSR_BASE + 0xF38) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_3_REG (CSR_IPSURX_CSR_BASE + 0xF3C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_4_REG (CSR_IPSURX_CSR_BASE + 0xF40) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_5_REG (CSR_IPSURX_CSR_BASE + 0xF44) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_0_REG (CSR_IPSURX_CSR_BASE + 0xF48) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_1_REG (CSR_IPSURX_CSR_BASE + 0xF4C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_2_REG (CSR_IPSURX_CSR_BASE + 0xF50) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_3_REG (CSR_IPSURX_CSR_BASE + 0xF54) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_4_REG (CSR_IPSURX_CSR_BASE + 0xF58) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_5_REG (CSR_IPSURX_CSR_BASE + 0xF5C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_0_REG (CSR_IPSURX_CSR_BASE + 0xF60) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_1_REG (CSR_IPSURX_CSR_BASE + 0xF64) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_2_REG (CSR_IPSURX_CSR_BASE + 0xF68) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_3_REG (CSR_IPSURX_CSR_BASE + 0xF6C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_4_REG (CSR_IPSURX_CSR_BASE + 0xF70) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_5_REG (CSR_IPSURX_CSR_BASE + 0xF74) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_0_REG (CSR_IPSURX_CSR_BASE + 0xF78) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_1_REG (CSR_IPSURX_CSR_BASE + 0xF7C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_2_REG (CSR_IPSURX_CSR_BASE + 0xF80) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_3_REG (CSR_IPSURX_CSR_BASE + 0xF84) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_4_REG (CSR_IPSURX_CSR_BASE + 0xF88) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_5_REG (CSR_IPSURX_CSR_BASE + 0xF8C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL_HIT_CNT_REG (CSR_IPSURX_CSR_BASE + 0xF90) /* WOL�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_OFS_CTRL_DW0_REG (CSR_IPSURX_CSR_BASE + 0x1000) /* ����ƥ��DFXƫ������ */ +#define CSR_IPSURX_CSR_IPSURX_CPT_OFS_CTRL_DW1_REG (CSR_IPSURX_CSR_BASE + 0x1004) /* ����ƥ��DFXƫ������ */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x1008) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x100C) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x1010) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x1014) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_4_REG (CSR_IPSURX_CSR_BASE + 0x1018) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_5_REG (CSR_IPSURX_CSR_BASE + 0x101C) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_6_REG (CSR_IPSURX_CSR_BASE + 0x1020) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_7_REG (CSR_IPSURX_CSR_BASE + 0x1024) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x1028) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x102C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x1030) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x1034) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x1038) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x103C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x1040) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x1044) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x1048) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x104C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x1050) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x1054) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x1058) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x105C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1060) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x1064) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x1068) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x106C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x1070) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x1074) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x1078) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x107C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x1080) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x1084) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x1088) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x108C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x1090) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x1094) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x1098) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x109C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x10A0) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x10A4) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x10A8) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x10AC) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x10B0) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x10B4) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_4_REG (CSR_IPSURX_CSR_BASE + 0x10B8) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_5_REG (CSR_IPSURX_CSR_BASE + 0x10BC) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_6_REG (CSR_IPSURX_CSR_BASE + 0x10C0) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_7_REG (CSR_IPSURX_CSR_BASE + 0x10C4) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x10C8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x10CC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x10D0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x10D4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x10D8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x10DC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x10E0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x10E4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x10E8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x10EC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x10F0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x10F4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x10F8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x10FC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1100) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x1104) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x1108) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x110C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x1110) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x1114) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x1118) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x111C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x1120) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x1124) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x1128) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x112C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x1130) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x1134) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x1138) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x113C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x1140) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x1144) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_0_REG (CSR_IPSURX_CSR_BASE + 0x1148) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_1_REG (CSR_IPSURX_CSR_BASE + 0x114C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_2_REG (CSR_IPSURX_CSR_BASE + 0x1150) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_3_REG (CSR_IPSURX_CSR_BASE + 0x1154) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_4_REG (CSR_IPSURX_CSR_BASE + 0x1158) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_5_REG (CSR_IPSURX_CSR_BASE + 0x115C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_6_REG (CSR_IPSURX_CSR_BASE + 0x1160) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_7_REG (CSR_IPSURX_CSR_BASE + 0x1164) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_0_REG (CSR_IPSURX_CSR_BASE + 0x1168) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_1_REG (CSR_IPSURX_CSR_BASE + 0x116C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_2_REG (CSR_IPSURX_CSR_BASE + 0x1170) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_3_REG (CSR_IPSURX_CSR_BASE + 0x1174) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_4_REG (CSR_IPSURX_CSR_BASE + 0x1178) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_5_REG (CSR_IPSURX_CSR_BASE + 0x117C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_6_REG (CSR_IPSURX_CSR_BASE + 0x1180) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_7_REG (CSR_IPSURX_CSR_BASE + 0x1184) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_0_REG (CSR_IPSURX_CSR_BASE + 0x1188) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_1_REG (CSR_IPSURX_CSR_BASE + 0x118C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_2_REG (CSR_IPSURX_CSR_BASE + 0x1190) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_3_REG (CSR_IPSURX_CSR_BASE + 0x1194) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_4_REG (CSR_IPSURX_CSR_BASE + 0x1198) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_5_REG (CSR_IPSURX_CSR_BASE + 0x119C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_6_REG (CSR_IPSURX_CSR_BASE + 0x11A0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_7_REG (CSR_IPSURX_CSR_BASE + 0x11A4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_0_REG (CSR_IPSURX_CSR_BASE + 0x11A8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_1_REG (CSR_IPSURX_CSR_BASE + 0x11AC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_2_REG (CSR_IPSURX_CSR_BASE + 0x11B0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_3_REG (CSR_IPSURX_CSR_BASE + 0x11B4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_4_REG (CSR_IPSURX_CSR_BASE + 0x11B8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_5_REG (CSR_IPSURX_CSR_BASE + 0x11BC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_6_REG (CSR_IPSURX_CSR_BASE + 0x11C0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_7_REG (CSR_IPSURX_CSR_BASE + 0x11C4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_0_REG (CSR_IPSURX_CSR_BASE + 0x11C8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_1_REG (CSR_IPSURX_CSR_BASE + 0x11CC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_2_REG (CSR_IPSURX_CSR_BASE + 0x11D0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_3_REG (CSR_IPSURX_CSR_BASE + 0x11D4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_4_REG (CSR_IPSURX_CSR_BASE + 0x11D8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_5_REG (CSR_IPSURX_CSR_BASE + 0x11DC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_6_REG (CSR_IPSURX_CSR_BASE + 0x11E0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_7_REG (CSR_IPSURX_CSR_BASE + 0x11E4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_0_REG (CSR_IPSURX_CSR_BASE + 0x11E8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_1_REG (CSR_IPSURX_CSR_BASE + 0x11EC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_2_REG (CSR_IPSURX_CSR_BASE + 0x11F0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_3_REG (CSR_IPSURX_CSR_BASE + 0x11F4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_4_REG (CSR_IPSURX_CSR_BASE + 0x11F8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_5_REG (CSR_IPSURX_CSR_BASE + 0x11FC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_6_REG (CSR_IPSURX_CSR_BASE + 0x1200) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_7_REG (CSR_IPSURX_CSR_BASE + 0x1204) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_0_REG (CSR_IPSURX_CSR_BASE + 0x1208) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_1_REG (CSR_IPSURX_CSR_BASE + 0x120C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_2_REG (CSR_IPSURX_CSR_BASE + 0x1210) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_3_REG (CSR_IPSURX_CSR_BASE + 0x1214) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_4_REG (CSR_IPSURX_CSR_BASE + 0x1218) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_5_REG (CSR_IPSURX_CSR_BASE + 0x121C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_6_REG (CSR_IPSURX_CSR_BASE + 0x1220) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_7_REG (CSR_IPSURX_CSR_BASE + 0x1224) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_0_REG (CSR_IPSURX_CSR_BASE + 0x1228) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_1_REG (CSR_IPSURX_CSR_BASE + 0x122C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_2_REG (CSR_IPSURX_CSR_BASE + 0x1230) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_3_REG (CSR_IPSURX_CSR_BASE + 0x1234) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_4_REG (CSR_IPSURX_CSR_BASE + 0x1238) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_5_REG (CSR_IPSURX_CSR_BASE + 0x123C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_6_REG (CSR_IPSURX_CSR_BASE + 0x1240) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_7_REG (CSR_IPSURX_CSR_BASE + 0x1244) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_0_REG (CSR_IPSURX_CSR_BASE + 0x1248) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_1_REG (CSR_IPSURX_CSR_BASE + 0x124C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_2_REG (CSR_IPSURX_CSR_BASE + 0x1250) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_3_REG (CSR_IPSURX_CSR_BASE + 0x1254) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_4_REG (CSR_IPSURX_CSR_BASE + 0x1258) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_5_REG (CSR_IPSURX_CSR_BASE + 0x125C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_6_REG (CSR_IPSURX_CSR_BASE + 0x1260) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_7_REG (CSR_IPSURX_CSR_BASE + 0x1264) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_0_REG (CSR_IPSURX_CSR_BASE + 0x1268) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_1_REG (CSR_IPSURX_CSR_BASE + 0x126C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_2_REG (CSR_IPSURX_CSR_BASE + 0x1270) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_3_REG (CSR_IPSURX_CSR_BASE + 0x1274) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_4_REG (CSR_IPSURX_CSR_BASE + 0x1278) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_5_REG (CSR_IPSURX_CSR_BASE + 0x127C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_6_REG (CSR_IPSURX_CSR_BASE + 0x1280) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_7_REG (CSR_IPSURX_CSR_BASE + 0x1284) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_0_REG (CSR_IPSURX_CSR_BASE + 0x1288) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_1_REG (CSR_IPSURX_CSR_BASE + 0x128C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_2_REG (CSR_IPSURX_CSR_BASE + 0x1290) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_3_REG (CSR_IPSURX_CSR_BASE + 0x1294) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_4_REG (CSR_IPSURX_CSR_BASE + 0x1298) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_5_REG (CSR_IPSURX_CSR_BASE + 0x129C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_6_REG (CSR_IPSURX_CSR_BASE + 0x12A0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_7_REG (CSR_IPSURX_CSR_BASE + 0x12A4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_0_REG (CSR_IPSURX_CSR_BASE + 0x12A8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_1_REG (CSR_IPSURX_CSR_BASE + 0x12AC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_2_REG (CSR_IPSURX_CSR_BASE + 0x12B0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_3_REG (CSR_IPSURX_CSR_BASE + 0x12B4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_4_REG (CSR_IPSURX_CSR_BASE + 0x12B8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_5_REG (CSR_IPSURX_CSR_BASE + 0x12BC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_6_REG (CSR_IPSURX_CSR_BASE + 0x12C0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_7_REG (CSR_IPSURX_CSR_BASE + 0x12C4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_0_REG (CSR_IPSURX_CSR_BASE + 0x12C8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_1_REG (CSR_IPSURX_CSR_BASE + 0x12CC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_2_REG (CSR_IPSURX_CSR_BASE + 0x12D0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_3_REG (CSR_IPSURX_CSR_BASE + 0x12D4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_4_REG (CSR_IPSURX_CSR_BASE + 0x12D8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_5_REG (CSR_IPSURX_CSR_BASE + 0x12DC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_6_REG (CSR_IPSURX_CSR_BASE + 0x12E0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_7_REG (CSR_IPSURX_CSR_BASE + 0x12E4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x12E8) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x12EC) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x12F0) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x12F4) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x12F8) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x12FC) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x1300) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x1304) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x1308) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x130C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x1310) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x1314) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x1318) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x131C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1320) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x1324) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x1328) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x132C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x1330) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x1334) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_4_REG (CSR_IPSURX_CSR_BASE + 0x1338) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_5_REG (CSR_IPSURX_CSR_BASE + 0x133C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_6_REG (CSR_IPSURX_CSR_BASE + 0x1340) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_7_REG (CSR_IPSURX_CSR_BASE + 0x1344) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_TX_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1348) /* TX����ƥ��DFX���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x134C) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1350) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1354) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1358) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x135C) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1360) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1364) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x1368) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_UNCRT_ERR_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1400) /* IPSURX����������ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_TH_REG (CSR_IPSURX_CSR_BASE + 0x1404) /* IPSURX FIFO���޼Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAMMOD_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1408) /* IPSURXģ��RAM MOD���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_ERR_CHK_BYPASS_REG \ + (CSR_IPSURX_CSR_BASE + 0x140C) /* IPSURXģ��RAM������BYPASS�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_ERR_INJ_REG (CSR_IPSURX_CSR_BASE + 0x1410) /* IPSURXģ��RAM����ע��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_STS2_REG (CSR_IPSURX_CSR_BASE + 0x1414) /* IPSURX FIFO��ǰ״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_STS1_REG (CSR_IPSURX_CSR_BASE + 0x1418) /* IPSURX FIFO��ǰ״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_STS0_REG (CSR_IPSURX_CSR_BASE + 0x141C) /* IPSURX FIFO��ǰ״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_UCERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1420) /* IPSURX RAM���ɾ���������� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1424) /* IPSURX RAM�ɾ���������� */ +#define CSR_IPSURX_CSR_IPSURX_RCV_BP_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1428) /* IPSURX���շ�ѹ���������� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_GEN_BP_CNT_REG (CSR_IPSURX_CSR_BASE + 0x142C) /* IPSURX������ѹ���������� */ +#define CSR_IPSURX_CSR_IPSURX_RENQF_MFS_PERX_TH_GAP_REG \ + (CSR_IPSURX_CSR_BASE + 0x1430) /* IPSURX RENQ FIFO��MFS��PERX���ĵ�ˮ��GAP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_LB_RTS_CRDT_STS_REG (CSR_IPSURX_CSR_BASE + 0x1434) /* ���ؼ��ش�ʱ��ͨ������״̬ */ +#define CSR_IPSURX_CSR_IPSURX_PRM_BP_RAND_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1438) /* PRM�������������������������� */ +#define CSR_IPSURX_CSR_IPSURX_PRM_BP_ALL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x143C) /* PRM���������ȫ���������������� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW0_REG (CSR_IPSURX_CSR_BASE + 0x1440) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW1_REG (CSR_IPSURX_CSR_BASE + 0x1444) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW2_REG (CSR_IPSURX_CSR_BASE + 0x1448) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW3_REG (CSR_IPSURX_CSR_BASE + 0x144C) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW4_REG (CSR_IPSURX_CSR_BASE + 0x1450) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_CTRL_BUS_REG (CSR_IPSURX_CSR_BASE + 0x1454) /* IPSURX TCAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_LB_CRDTF_TH_REG (CSR_IPSURX_CSR_BASE + 0x1458) /* IPSURX LB CRDT FIFO���޼Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x1500) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1504) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1508) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x150C) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x1510) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1514) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1518) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x151C) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x1520) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x1524) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x1528) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x152C) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1530) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1534) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1538) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x153C) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1540) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1544) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x1548) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x154C) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x1550) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x1554) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x1558) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x155C) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1560) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1564) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x1568) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x156C) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1570) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x1574) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x1578) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x157C) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x1580) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x1584) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1588) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x158C) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1590) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x1594) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1598) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x159C) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x15A0) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x15A4) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x15A8) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x15AC) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT_CNT_CFG_REG \ + (CSR_IPSURX_CSR_BASE + 0x15B0) /* ����COS�ı���������������Ӧ��PORT���� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x15B4) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x15B8) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x15BC) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x15C0) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0x15C4) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0x15C8) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0x15CC) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0x15D0) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x15D4) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x15D8) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x15DC) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x15E0) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0x15E4) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0x15E8) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0x15EC) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0x15F0) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x1600) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x1604) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x1608) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x160C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x1610) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x1614) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x1618) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x161C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x1620) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x1624) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x1628) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x162C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x1630) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x1634) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1638) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x163C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x1640) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x1644) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x1648) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x164C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x1650) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x1654) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x1658) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x165C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x1660) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x1664) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x1668) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x166C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x1670) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x1674) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x1678) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x167C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_PORT_REG (CSR_IPSURX_CSR_BASE + 0x1680) /* VTEP IPƥ��˿����� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1684) /* VTEP IPƥ����ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_0_REG (CSR_IPSURX_CSR_BASE + 0x1700) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_1_REG (CSR_IPSURX_CSR_BASE + 0x1704) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_2_REG (CSR_IPSURX_CSR_BASE + 0x1708) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_3_REG (CSR_IPSURX_CSR_BASE + 0x170C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_4_REG (CSR_IPSURX_CSR_BASE + 0x1710) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_5_REG (CSR_IPSURX_CSR_BASE + 0x1714) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_6_REG (CSR_IPSURX_CSR_BASE + 0x1718) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_7_REG (CSR_IPSURX_CSR_BASE + 0x171C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_8_REG (CSR_IPSURX_CSR_BASE + 0x1720) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_9_REG (CSR_IPSURX_CSR_BASE + 0x1724) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_10_REG (CSR_IPSURX_CSR_BASE + 0x1728) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_11_REG (CSR_IPSURX_CSR_BASE + 0x172C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_12_REG (CSR_IPSURX_CSR_BASE + 0x1730) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_13_REG (CSR_IPSURX_CSR_BASE + 0x1734) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_14_REG (CSR_IPSURX_CSR_BASE + 0x1738) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_15_REG (CSR_IPSURX_CSR_BASE + 0x173C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x1740) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x1744) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x1748) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x174C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_4_REG \ + (CSR_IPSURX_CSR_BASE + 0x1750) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_5_REG \ + (CSR_IPSURX_CSR_BASE + 0x1754) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_6_REG \ + (CSR_IPSURX_CSR_BASE + 0x1758) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_7_REG \ + (CSR_IPSURX_CSR_BASE + 0x175C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_8_REG \ + (CSR_IPSURX_CSR_BASE + 0x1760) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_9_REG \ + (CSR_IPSURX_CSR_BASE + 0x1764) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_10_REG \ + (CSR_IPSURX_CSR_BASE + 0x1768) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_11_REG \ + (CSR_IPSURX_CSR_BASE + 0x176C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_12_REG \ + (CSR_IPSURX_CSR_BASE + 0x1770) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_13_REG \ + (CSR_IPSURX_CSR_BASE + 0x1774) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_14_REG \ + (CSR_IPSURX_CSR_BASE + 0x1778) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_15_REG \ + (CSR_IPSURX_CSR_BASE + 0x177C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_0_REG (CSR_IPSURX_CSR_BASE + 0x1780) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_1_REG (CSR_IPSURX_CSR_BASE + 0x1784) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_2_REG (CSR_IPSURX_CSR_BASE + 0x1788) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_3_REG (CSR_IPSURX_CSR_BASE + 0x178C) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_ERR_PATN_ID_REG (CSR_IPSURX_CSR_BASE + 0x1790) /* ���Ľ�������ʱ�����PATTERN ID */ + + +#endif // IPSURX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_typedef.h new file mode 100644 index 000000000..e4b24c217 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_typedef.h @@ -0,0 +1,30688 @@ +/* ** + * @file hi1823_csr_ipsurx_typedef.h + * @brief struct of ipsurx module defination + * + * Copyright (c) 2011 + * Huawei Tech.Co.,Ltd + * + * @author Huawei + * @date 2016-08-17 + * @version + * @nManager version:2015-06-12 + * + * + */ + +#ifndef HI1822_CSR_IPSURX_TYPEDEF_H +#define HI1822_CSR_IPSURX_TYPEDEF_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* * __cplusplus */ + +/* ** + * Union name : IPSURX_FPGA_VER + * @brief + * Description: + */ +typedef union tagUnIpsurxFpgaVer { + struct tagStIpsurxFpgaVer { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFpgaVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#else + unsigned int ipsurxFpgaVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FPGA_VER_U; + +/* ** + * Union name : IPSURX_EMU_VER + * @brief + * Description: + */ +typedef union tagUnIpsurxEmuVer { + struct tagStIpsurxEmuVer { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxEmuVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#else + unsigned int ipsurxEmuVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EMU_VER_U; + +/* ** + * Union name : IPSURX_INITCTAB_START + * @brief 配置表初始化使能寄存器 + * Description: + */ +typedef union tagUnIpsurxInitctabStart { + struct tagStIpsurxInitctabStart { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]保留。 */ + unsigned int + ipsurxTptInitStart : 1; /* * [1:1]TPT(TCP PORT + TABLE)初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ + unsigned int ipsurxTcamInitStart : 1; /* * + [0:0]TCAM配置表初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ +#else + unsigned int ipsurxTcamInitStart : 1; /* * + [0:0]TCAM配置表初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ + unsigned int + ipsurxTptInitStart : 1; /* * [1:1]TPT(TCP PORT + TABLE)初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ + unsigned int reserved : 30; /* * [31:2]保留。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INITCTAB_START_U; + +/* ** + * Union name : IPSURX_INITCTAB_DONE + * @brief 配置表初始化状态寄存器 + * Description: + */ +typedef union tagUnIpsurxInitctabDone { + struct tagStIpsurxInitctabDone { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]保留。 */ + unsigned int ipsurxTptInitDone : 1; /* * [1:1]TCP Port + Table初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ + unsigned int ipsurxTcamInitDone : 1; /* * [0:0]TCAM初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ +#else + unsigned int ipsurxTcamInitDone : 1; /* * [0:0]TCAM初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ + unsigned int ipsurxTptInitDone : 1; /* * [1:1]TCP Port + Table初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ + unsigned int reserved : 30; /* * [31:2]保留。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INITCTAB_DONE_U; + +/* ** + * Union name : IPSURX_ERR_INT_VECTOR + * @brief Interrupt Vector Register + * Description: + */ +typedef union tagUnIpsurxErrIntVector { + struct tagStIpsurxErrIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ERR_INT_VECTOR_U; + +/* ** + * Union name : IPSURX_ERR_INT + * @brief Interrupt Data Register + * Description: + */ +typedef union tagUnIpsurxErrInt { + struct tagStIpsurxErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_ERR_INT_MASK. + */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int intData : 13; /* * [12:0]These 13 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ +#else + unsigned int intData : 13; /* * [12:0]These 13 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_ERR_INT_MASK. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ERR_INT_U; + +/* ** + * Union name : IPSURX_ERR_INT_MASK + * @brief Interrupt Mask Register + * Description: + */ +typedef union tagUnIpsurxErrIntMask { + struct tagStIpsurxErrIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int + errMask : 13; /* * + [12:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[12:6]和bit[1]对应IPSURX数据路径上的FIFO溢出事件或者RAM的多比特不可纠错误。作为致命中断，建议芯片初始化完成后打开该比特。其余比特对应非致命中断，用户可以根据自 + 己需要处理。 */ +#else + unsigned int + errMask : 13; /* * + [12:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[12:6]和bit[1]对应IPSURX数据路径上的FIFO溢出事件或者RAM的多比特不可纠错误。作为致命中断，建议芯片初始化完成后打开该比特。其余比特对应非致命中断，用户可以根据自 + 己需要处理。 */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ERR_INT_MASK_U; + +/* ** + * Union name : IPSURX_CH_INVLD_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxChInvldErr { + struct tagStIpsurxChInvldErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 13; /* * [31:19]reserved. */ + unsigned int sticky : 17; /* * [18:2]Bit vector to indicate received data from disabled channel.Bit + * i(i=0~16)为高表示通道i未使能但收到数据。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 17; /* * [18:2]Bit vector to indicate received data from disabled channel.Bit + * i(i=0~16)为高表示通道i未使能但收到数据。 + */ + unsigned int reserved : 13; /* * [31:19]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH_INVLD_ERR_U; + +/* ** + * Union name : IPSURX_PPC_DRAM_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxPpcDramUncrtErr { + struct tagStIpsurxPpcDramUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int sticky : 4; /* * [5:2]Data RAM address in IPSURX PPC module. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 4; /* * [5:2]Data RAM address in IPSURX PPC module. */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PPC_DRAM_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_TCAM_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxTcamUncrtErr { + struct tagStIpsurxTcamUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved. */ + unsigned int sticky : 10; /* * [11:2]TCAM ENTRY address when uncorrectable error + * occurs.Sticky[9:1]表示TCAM地址。Sticky[0]=0表示Y ENTRY；为1表示X ENTRY。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 10; /* * [11:2]TCAM ENTRY address when uncorrectable error + * occurs.Sticky[9:1]表示TCAM地址。Sticky[0]=0表示Y ENTRY；为1表示X ENTRY。 + */ + unsigned int reserved : 20; /* * [31:12]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_TCAM_ART_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxTcamArtUncrtErr { + struct tagStIpsurxTcamArtUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11]reserved. */ + unsigned int sticky : 9; /* * [10:2]TCAM ART ENTRY address when uncorrectable error occurs. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 9; /* * [10:2]TCAM ART ENTRY address when uncorrectable error occurs. */ + unsigned int reserved : 21; /* * [31:11]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_ART_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_SFT_TCAM_LOOK_RSLT + * @brief + * Description: + */ +typedef union tagUnIpsurxSftTcamLookRslt { + struct tagStIpsurxSftTcamLookRslt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]When ipsurx_tcam_cfg_search_ctrl = 1'b0, Sticky[29:0] return hitted TCAM + entry index.sticky[29:10] Reserved.sticky[9:1] TCAM key address.sticky[0] VALID, high a + ctive.when ipsurx_tcam_cfg_search_ctrl = 1'b1, Sticky[29:0] return hitted ART + results.sticky[29:21] Packet Type.sticky[20:18] Reserved.sticky[17:12] ERR Type. s + ticky[11:8] Priority.sticky[7:4] PUSH_LEN.sticky[3:1] Forwarding Action.sticky[0] VALID, + high active. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 30; /* * [31:2]When ipsurx_tcam_cfg_search_ctrl = 1'b0, Sticky[29:0] return hitted TCAM + entry index.sticky[29:10] Reserved.sticky[9:1] TCAM key address.sticky[0] VALID, high a + ctive.when ipsurx_tcam_cfg_search_ctrl = 1'b1, Sticky[29:0] return hitted ART + results.sticky[29:21] Packet Type.sticky[20:18] Reserved.sticky[17:12] ERR Type. s + ticky[11:8] Priority.sticky[7:4] PUSH_LEN.sticky[3:1] Forwarding Action.sticky[0] VALID, + high active. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SFT_TCAM_LOOK_RSLT_U; + +/* ** + * Union name : IPSURX_TPT_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxTptUncrtErr { + struct tagStIpsurxTptUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int sticky : 11; /* * [12:2]TCP port table entry address when uncorrectable error occurs. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 11; /* * [12:2]TCP port table entry address when uncorrectable error occurs. */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_LCVPP_CONTEXT_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxLcvppContextUncrtErr { + struct tagStIpsurxLcvppContextUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int sticky : 3; /* * [4:2]Context RAM address when uncorrectable error occurs in IPSURX LCVPP module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 3; /* * [4:2]Context RAM address when uncorrectable error occurs in IPSURX LCVPP module. + */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCVPP_CONTEXT_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_LCV_FIFO_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxLcvFifoUncrtErr { + struct tagStIpsurxLcvFifoUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9]reserved. */ + unsigned int sticky : 7; /* * [8:2]FIFO address when uncorrectable error occurs in LCVPP module. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 7; /* * [8:2]FIFO address when uncorrectable error occurs in LCVPP module. */ + unsigned int reserved : 23; /* * [31:9]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_FIFO_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_IF_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqIfUncrtErr { + struct tagStIpsurxRenqIfUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]Input FIFO RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]Input FIFO RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_IF_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT0_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqContext0UncrtErr { + struct tagStIpsurxRenqContext0UncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int sticky : 3; /* * [4:2]Context0 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 3; /* * [4:2]Context0 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT0_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT1_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqContext1UncrtErr { + struct tagStIpsurxRenqContext1UncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int sticky : 3; /* * [4:2]Context1 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 3; /* * [4:2]Context1 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT1_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_OF_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqOfUncrtErr { + struct tagStIpsurxRenqOfUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]Output FIFO RAM address when uncorrectable error occurs in IPSURX RENQ + * module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]Output FIFO RAM address when uncorrectable error occurs in IPSURX RENQ + * module. + */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_OF_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_FIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxFifoOvfl { + struct tagStIpsurxFifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int sticky : 2; /* * [3:2]溢出FIFO编号。2'b00: LCV FIFO overflow;2'b01: RENQ input FIFO overflow;2'b10: + * RENQ output FIFO overflow;2'b11: Reserved. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 2; /* * [3:2]溢出FIFO编号。2'b00: LCV FIFO overflow;2'b01: RENQ input FIFO overflow;2'b10: + * RENQ output FIFO overflow;2'b11: Reserved. + */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_OVFL_U; + +/* ** + * Union name : IPSURX_MERR_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnIpsurxMerrIntVector { + struct tagStIpsurxMerrIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MERR_INT_VECTOR_U; + +/* ** + * Union name : IPSURX_MERR_INT + * @brief + * Description: + */ +typedef union tagUnIpsurxMerrInt { + struct tagStIpsurxMerrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_MERR_INT_MASK register. + */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int intData : 5; /* * [4:0]These 5 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ +#else + unsigned int intData : 5; /* * [4:0]These 5 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_MERR_INT_MASK register. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MERR_INT_U; + +/* ** + * Union name : IPSURX_MERR_INT_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxMerrIntMask { + struct tagStIpsurxMerrIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int + errMask : 5; /* * + [4:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[4]对应CSR路径上，IPSUTX时钟域到IPSURX时钟域的异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[3:0]对应非致命中断，用户可以根据自己需要 + 处理。 */ +#else + unsigned int + errMask : 5; /* * + [4:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[4]对应CSR路径上，IPSUTX时钟域到IPSURX时钟域的异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[3:0]对应非致命中断，用户可以根据自己需要 + 处理。 */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MERR_INT_MASK_U; + +/* ** + * Union name : IPSURX_SOP_EOP_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxSopEopErr { + struct tagStIpsurxSopEopErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int sopSopMerr : 1; /* * [5:5]1'b1: 发生多次SOP_SOP错误。1'b0：未发生多次SOP_SOP错误。 */ + unsigned int sopSopErr : 1; /* * [4:4]1'b1: 发生SOP_SOP错误。1'b0：未发生SOP_SOP错误。 */ + unsigned int abortBfIpsurxMerr : 1; /* * [3:3]1'b1: 发生多次ABORT_BF_IPSURX + 错误。1'b0：未发生多次ABORT_BF_IPSURX 错误。 */ + unsigned int abortBfIpsurxErr : 1; /* * [2:2]1'b1: 发生ABORT_BF_IPSURX 错误。1'b0：未发生ABORT_BF_IPSURX 错误。 + */ + unsigned int sopWithMerr : 1; /* * [1:1]1'b1: 发生多次SOP_WITH_ERR 错误。1'b0：未发生多次SOP_WITH_ERR 错误。 */ + unsigned int sopWithErr : 1; /* * [0:0]1'b1: 发生SOP_WITH_ERR 错误。1'b0：未发生SOP_WITH_ERR 错误。 */ +#else + unsigned int sopWithErr : 1; /* * [0:0]1'b1: 发生SOP_WITH_ERR 错误。1'b0：未发生SOP_WITH_ERR 错误。 */ + unsigned int sopWithMerr : 1; /* * [1:1]1'b1: 发生多次SOP_WITH_ERR 错误。1'b0：未发生多次SOP_WITH_ERR 错误。 */ + unsigned int abortBfIpsurxErr : 1; /* * [2:2]1'b1: 发生ABORT_BF_IPSURX 错误。1'b0：未发生ABORT_BF_IPSURX 错误。 + */ + unsigned int abortBfIpsurxMerr : 1; /* * [3:3]1'b1: 发生多次ABORT_BF_IPSURX + 错误。1'b0：未发生多次ABORT_BF_IPSURX 错误。 */ + unsigned int sopSopErr : 1; /* * [4:4]1'b1: 发生SOP_SOP错误。1'b0：未发生SOP_SOP错误。 */ + unsigned int sopSopMerr : 1; /* * [5:5]1'b1: 发生多次SOP_SOP错误。1'b0：未发生多次SOP_SOP错误。 */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_EOP_ERR_U; + +/* ** + * Union name : IPSURX_SOP_EOP_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxSopEopErrMask { + struct tagStIpsurxSopEopErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sopSopErrMask : 1; /* * [2:2]1'b1：允许上报SOP_SOP错误中断；1'b0：不允许上报SOP_SOP错误中断。 */ + unsigned int abortBfIpsurxMask : 1; /* * [1:1]1'b1：允许上报ABORT_BF_IPSURX + 中断；1'b0：不允许上报ABORT_BF_IPSURX 中断。 */ + unsigned int sopWithErrMask : 1; /* * [0:0]1'b1：允许上报SOP_WITH_ERR 中断；1'b0：不允许上报SOP_WITH_ERR 中断。 + */ +#else + unsigned int sopWithErrMask : 1; /* * [0:0]1'b1：允许上报SOP_WITH_ERR 中断；1'b0：不允许上报SOP_WITH_ERR 中断。 + */ + unsigned int abortBfIpsurxMask : 1; /* * [1:1]1'b1：允许上报ABORT_BF_IPSURX + 中断；1'b0：不允许上报ABORT_BF_IPSURX 中断。 */ + unsigned int sopSopErrMask : 1; /* * [2:2]1'b1：允许上报SOP_SOP错误中断；1'b0：不允许上报SOP_SOP错误中断。 */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_EOP_ERR_MASK_U; + +/* ** + * Union name : IPSURX_IP_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxIpErr { + struct tagStIpsurxIpErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipv4VerMerr : 1; /* * [31:31]1'b1: 发生多次IPv4 Version错误。1'b0：未发生多次IPv4 Version错误。 */ + unsigned int ipv4VerErr : 1; /* * [30:30]1'b1: 发生IPv4 Version错误。1'b0：未发生IPv4 Version错误。 */ + unsigned int ipv4IhlMerr : 1; /* * [29:29]1'b1: 发生多次IPv4头部长度错误。1'b0：未发生多次IPv4头部长度错误。 */ + unsigned int ipv4IhlErr : 1; /* * [28:28]1'b1: 发生IPv4头部长度错误。1'b0：未发生IPv4头部长度错误。 */ + unsigned int ipv4SipMerr : 1; /* * [27:27]1'b1: 发生多次IPv4源IP地址错误。1'b0：未发生多次IPv4源IP地址错误。 */ + unsigned int ipv4SipErr : 1; /* * [26:26]1'b1: 发生IPv4源IP地址错误。1'b0：未发生IPv4源IP地址错误。 */ + unsigned int ipv4DipMerr : 1; /* * [25:25]1'b1: 发生多次IPv4目的IP地址错误。1'b0：未发生多次IPv4目的IP地址错误。 + */ + unsigned int ipv4DipErr : 1; /* * [24:24]1'b1: 发生IPv4目的IP地址错误。1'b0：未发生IPv4目的IP地址错误。 */ + unsigned int ipv4CsMerr : 1; /* * [23:23]1'b1: + * 发生多次IPv4头部CS校验错误。1'b0：未发生多次IPv4头部CS校校验错误。 + */ + unsigned int ipv4CsErr : 1; /* * [22:22]1'b1: 发生IPv4头部CS校验错误。1'b0：未发生IPv4头部CS校验错误。 */ + unsigned int ipv6VerMerr : 1; /* * [21:21]1'b1: 发生多次IPv6 Version错误。1'b0：未发生多次IPv6 Version错误。 */ + unsigned int ipv6VerErr : 1; /* * [20:20]1'b1: 发生IPv6 Version 错误。1'b0：未发生IPv6 Version 错误。 */ + unsigned int ipv6SipMerr : 1; /* * [19:19]1'b1: 发生多次IPv6源IP地址错误。1'b0：未发生多次IPv6源IP地址错误。 */ + unsigned int ipv6SipErr : 1; /* * [18:18]1'b1: 发生IPv6源IP地址错误。1'b0：未发生IPv6源IP地址错误。 */ + unsigned int ipv6DipMerr : 1; /* * [17:17]1'b1: 发生多次IPv6目的IP地址错误。1'b0：未发生多次IPv6目的IP地址错误。 + */ + unsigned int ipv6DipErr : 1; /* * [16:16]1'b1: 发生IPv6目的IP地址错误。1'b0：未发生IPv6目的IP地址错误。 */ + unsigned int tcpLandMerr : 1; /* * [15:15]1'b1: 发生多次TCP LAND错误。1'b0：未发生多次TCP LAND错误。 */ + unsigned int tcpLandErr : 1; /* * [14:14]1'b1: 发生TCP LAND错误。1'b0：未发生TCP LAND错误。 */ + unsigned int tcpCsMerr : 1; /* * [13:13]1'b1: 发生多次TCP CS校验错误。1'b0：未发生多次TCP CS校验错误。 */ + unsigned int tcpCsErr : 1; /* * [12:12]1'b1: 发生TCP CS校验错误。1'b0：未发生TCP CS校验错误。 */ + unsigned int ipv6UdpCsZeroMerr : 1; /* * [11:11]1'b1: 发生多次IPv6 UDP CS为0校验错误。1'b0：未发生多次IPv6 UDP + CS为0校验错误。 */ + unsigned int ipv6UdpCsZeroErr : 1; /* * [10:10]1'b1: 发生IPv6 UDP CS为0校验错误。1'b0：未发生IPv6 UDP + CS为0校验错误。 */ + unsigned int udpCsMerr : 1; /* * [9:9]1'b1: 发生多次UDP CS校验错误。1'b0：未发生多次UDP CS校验错误。 */ + unsigned int udpCsErr : 1; /* * [8:8]1'b1: 发生UDP CS校验错误。1'b0：未发生UDP CS校验错误。 */ + unsigned int igmpCsMerr : 1; /* * [7:7]1'b1: 发生多次IGMP CS校验错误。1'b0：未发生多次IGMP CS校验错误。 */ + unsigned int igmpCsErr : 1; /* * [6:6]1'b1: 发生IGMP CS校验错误。1'b0：未发生IGMP CS校验错误。 */ + unsigned int icmpv4CsMerr : 1; /* * [5:5]1'b1: 发生多次ICMPv4 CS校验错误。1'b0：未发生多次ICMPv4 CS校验错误。 */ + unsigned int icmpv4CsErr : 1; /* * [4:4]1'b1: 发生ICMPv4 CS校验错误。1'b0：未发生ICMPv4 CS校验错误。 */ + unsigned int icmpv6CsMerr : 1; /* * [3:3]1'b1: 发生多次ICMPv6 CS校验错误。1'b0：未发生多次ICMPv6 CS校验错误。 */ + unsigned int icmpv6CsErr : 1; /* * [2:2]1'b1: 发生ICMPv6 CS校验错误。1'b0：未发生ICMPv6 CS校验错误。 */ + unsigned int sctpCsMerr : 1; /* * [1:1]1'b1: 发生多次SCTP CS校验错误。1'b0：未发生多次SCTP CS校验错误。 */ + unsigned int sctpCsErr : 1; /* * [0:0]1'b1: 发生SCTP CS校验错误。1'b0：未发生SCTP CS校验错误。 */ +#else + unsigned int sctpCsErr : 1; /* * [0:0]1'b1: 发生SCTP CS校验错误。1'b0：未发生SCTP CS校验错误。 */ + unsigned int sctpCsMerr : 1; /* * [1:1]1'b1: 发生多次SCTP CS校验错误。1'b0：未发生多次SCTP CS校验错误。 */ + unsigned int icmpv6CsErr : 1; /* * [2:2]1'b1: 发生ICMPv6 CS校验错误。1'b0：未发生ICMPv6 CS校验错误。 */ + unsigned int icmpv6CsMerr : 1; /* * [3:3]1'b1: 发生多次ICMPv6 CS校验错误。1'b0：未发生多次ICMPv6 CS校验错误。 */ + unsigned int icmpv4CsErr : 1; /* * [4:4]1'b1: 发生ICMPv4 CS校验错误。1'b0：未发生ICMPv4 CS校验错误。 */ + unsigned int icmpv4CsMerr : 1; /* * [5:5]1'b1: 发生多次ICMPv4 CS校验错误。1'b0：未发生多次ICMPv4 CS校验错误。 */ + unsigned int igmpCsErr : 1; /* * [6:6]1'b1: 发生IGMP CS校验错误。1'b0：未发生IGMP CS校验错误。 */ + unsigned int igmpCsMerr : 1; /* * [7:7]1'b1: 发生多次IGMP CS校验错误。1'b0：未发生多次IGMP CS校验错误。 */ + unsigned int udpCsErr : 1; /* * [8:8]1'b1: 发生UDP CS校验错误。1'b0：未发生UDP CS校验错误。 */ + unsigned int udpCsMerr : 1; /* * [9:9]1'b1: 发生多次UDP CS校验错误。1'b0：未发生多次UDP CS校验错误。 */ + unsigned int ipv6UdpCsZeroErr : 1; /* * [10:10]1'b1: 发生IPv6 UDP CS为0校验错误。1'b0：未发生IPv6 UDP + CS为0校验错误。 */ + unsigned int ipv6UdpCsZeroMerr : 1; /* * [11:11]1'b1: 发生多次IPv6 UDP CS为0校验错误。1'b0：未发生多次IPv6 UDP + CS为0校验错误。 */ + unsigned int tcpCsErr : 1; /* * [12:12]1'b1: 发生TCP CS校验错误。1'b0：未发生TCP CS校验错误。 */ + unsigned int tcpCsMerr : 1; /* * [13:13]1'b1: 发生多次TCP CS校验错误。1'b0：未发生多次TCP CS校验错误。 */ + unsigned int tcpLandErr : 1; /* * [14:14]1'b1: 发生TCP LAND错误。1'b0：未发生TCP LAND错误。 */ + unsigned int tcpLandMerr : 1; /* * [15:15]1'b1: 发生多次TCP LAND错误。1'b0：未发生多次TCP LAND错误。 */ + unsigned int ipv6DipErr : 1; /* * [16:16]1'b1: 发生IPv6目的IP地址错误。1'b0：未发生IPv6目的IP地址错误。 */ + unsigned int ipv6DipMerr : 1; /* * [17:17]1'b1: 发生多次IPv6目的IP地址错误。1'b0：未发生多次IPv6目的IP地址错误。 + */ + unsigned int ipv6SipErr : 1; /* * [18:18]1'b1: 发生IPv6源IP地址错误。1'b0：未发生IPv6源IP地址错误。 */ + unsigned int ipv6SipMerr : 1; /* * [19:19]1'b1: 发生多次IPv6源IP地址错误。1'b0：未发生多次IPv6源IP地址错误。 */ + unsigned int ipv6VerErr : 1; /* * [20:20]1'b1: 发生IPv6 Version 错误。1'b0：未发生IPv6 Version 错误。 */ + unsigned int ipv6VerMerr : 1; /* * [21:21]1'b1: 发生多次IPv6 Version错误。1'b0：未发生多次IPv6 Version错误。 */ + unsigned int ipv4CsErr : 1; /* * [22:22]1'b1: 发生IPv4头部CS校验错误。1'b0：未发生IPv4头部CS校验错误。 */ + unsigned int ipv4CsMerr : 1; /* * [23:23]1'b1: + * 发生多次IPv4头部CS校验错误。1'b0：未发生多次IPv4头部CS校校验错误。 + */ + unsigned int ipv4DipErr : 1; /* * [24:24]1'b1: 发生IPv4目的IP地址错误。1'b0：未发生IPv4目的IP地址错误。 */ + unsigned int ipv4DipMerr : 1; /* * [25:25]1'b1: 发生多次IPv4目的IP地址错误。1'b0：未发生多次IPv4目的IP地址错误。 + */ + unsigned int ipv4SipErr : 1; /* * [26:26]1'b1: 发生IPv4源IP地址错误。1'b0：未发生IPv4源IP地址错误。 */ + unsigned int ipv4SipMerr : 1; /* * [27:27]1'b1: 发生多次IPv4源IP地址错误。1'b0：未发生多次IPv4源IP地址错误。 */ + unsigned int ipv4IhlErr : 1; /* * [28:28]1'b1: 发生IPv4头部长度错误。1'b0：未发生IPv4头部长度错误。 */ + unsigned int ipv4IhlMerr : 1; /* * [29:29]1'b1: 发生多次IPv4头部长度错误。1'b0：未发生多次IPv4头部长度错误。 */ + unsigned int ipv4VerErr : 1; /* * [30:30]1'b1: 发生IPv4 Version错误。1'b0：未发生IPv4 Version错误。 */ + unsigned int ipv4VerMerr : 1; /* * [31:31]1'b1: 发生多次IPv4 Version错误。1'b0：未发生多次IPv4 Version错误。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IP_ERR_U; + +/* ** + * Union name : IPSURX_IP_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxIpErrMask { + struct tagStIpsurxIpErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int ipv4VerErrMask : 1; /* * [15:15]1'b1：允许上报IPv4 Version错误中断；1'b0：不允许上报IPv4 + Version错误中断。 */ + unsigned int ipv4IhlErrMask : 1; /* * [14:14]1'b1：允许上报IPv4 头部长度错误中断；1'b0：不允许上报IPv4 + 头部长度错误中断。 */ + unsigned int ipv4SipErrMask : 1; /* * [13:13]1'b1：允许上报IPv4 源IP错误中断；1'b0：不允许上报IPv4 + * 源IP错误中断。 + */ + unsigned int ipv4DipErrMask : 1; /* * [12:12]1'b1：允许上报IPv4 目的IP错误中断；1'b0：不允许上报IPv4 + 目的IP错误中断。 */ + unsigned int ipv4CsErrMask : 1; /* * [11:11]1'b1：允许上报IPv4 头部CS校验错误中断；1'b0：不允许上报IPv4 + 头部CS校验错误中断。 */ + unsigned int ipv6VerErrMask : 1; /* * [10:10]1'b1：允许上报IPv6 Version错误中断；1'b0：不允许上报IPv6 + Version错误中断。 */ + unsigned int ipv6SipErrMask : 1; /* * [9:9]1'b1：允许上报IPv6 源IP错误中断；1'b0：不允许上报IPv6 源IP错误中断。 + */ + unsigned int ipv6DipErrMask : 1; /* * [8:8]1'b1：允许上报IPv6 目的IP错误中断；1'b0：不允许上报IPv6 + 目的IP错误中断。 */ + unsigned int tcpLandErrMask : 1; /* * [7:7]1'b1：允许上报TCP LADN错误中断；1'b0：不允许上报TCP LADN错误中断。 */ + unsigned int tcpCsErrMask : 1; /* * [6:6]1'b1：允许上报TCP CS校验错误中断；1'b0：不允许上报TCP CS校验错误中断。 + */ + unsigned int ipv6UdpCsZeroErrMask : 1; /* * [5:5]1'b1：允许上报IPv6 UDP CS为0校验错误中断；1'b0：不允许上报IPv6 + UDP CS为0校验错误中断。 */ + unsigned int udpCsErrMask : 1; /* * [4:4]1'b1：允许上报UDP CS校验错误中断；1'b0：不允许上报UDP CS校验错误中断。 + */ + unsigned int igmpCsErrMask : 1; /* * [3:3]1'b1：允许上报IGMP CS校验错误中断；1'b0：不允许上报IGMP + CS校验错误中断。 */ + unsigned int icmpv4CsErrMask : 1; /* * [2:2]1'b1：允许上报ICMPv4 CS校验错误中断；1'b0：不允许上报ICMPv4 + CS校验错误中断。 */ + unsigned int icmpv6CsErrMask : 1; /* * [1:1]1'b1：允许上报ICMPv6 CS校验错误中断；1'b0：不允许上报ICMPv6 + CS校验错误中断。 */ + unsigned int sctpCsErrMask : 1; /* * [0:0]1'b1：允许上报SCTP CS校验错误中断；1'b0：不允许上报SCTP + CS校验错误中断。 */ +#else + unsigned int sctpCsErrMask : 1; /* * [0:0]1'b1：允许上报SCTP CS校验错误中断；1'b0：不允许上报SCTP + CS校验错误中断。 */ + unsigned int icmpv6CsErrMask : 1; /* * [1:1]1'b1：允许上报ICMPv6 CS校验错误中断；1'b0：不允许上报ICMPv6 + CS校验错误中断。 */ + unsigned int icmpv4CsErrMask : 1; /* * [2:2]1'b1：允许上报ICMPv4 CS校验错误中断；1'b0：不允许上报ICMPv4 + CS校验错误中断。 */ + unsigned int igmpCsErrMask : 1; /* * [3:3]1'b1：允许上报IGMP CS校验错误中断；1'b0：不允许上报IGMP + CS校验错误中断。 */ + unsigned int udpCsErrMask : 1; /* * [4:4]1'b1：允许上报UDP CS校验错误中断；1'b0：不允许上报UDP CS校验错误中断。 + */ + unsigned int ipv6UdpCsZeroErrMask : 1; /* * [5:5]1'b1：允许上报IPv6 UDP CS为0校验错误中断；1'b0：不允许上报IPv6 + UDP CS为0校验错误中断。 */ + unsigned int tcpCsErrMask : 1; /* * [6:6]1'b1：允许上报TCP CS校验错误中断；1'b0：不允许上报TCP CS校验错误中断。 + */ + unsigned int tcpLandErrMask : 1; /* * [7:7]1'b1：允许上报TCP LADN错误中断；1'b0：不允许上报TCP LADN错误中断。 */ + unsigned int ipv6DipErrMask : 1; /* * [8:8]1'b1：允许上报IPv6 目的IP错误中断；1'b0：不允许上报IPv6 + 目的IP错误中断。 */ + unsigned int ipv6SipErrMask : 1; /* * [9:9]1'b1：允许上报IPv6 源IP错误中断；1'b0：不允许上报IPv6 源IP错误中断。 + */ + unsigned int ipv6VerErrMask : 1; /* * [10:10]1'b1：允许上报IPv6 Version错误中断；1'b0：不允许上报IPv6 + Version错误中断。 */ + unsigned int ipv4CsErrMask : 1; /* * [11:11]1'b1：允许上报IPv4 头部CS校验错误中断；1'b0：不允许上报IPv4 + 头部CS校验错误中断。 */ + unsigned int ipv4DipErrMask : 1; /* * [12:12]1'b1：允许上报IPv4 目的IP错误中断；1'b0：不允许上报IPv4 + 目的IP错误中断。 */ + unsigned int ipv4SipErrMask : 1; /* * [13:13]1'b1：允许上报IPv4 源IP错误中断；1'b0：不允许上报IPv4 + * 源IP错误中断。 + */ + unsigned int ipv4IhlErrMask : 1; /* * [14:14]1'b1：允许上报IPv4 头部长度错误中断；1'b0：不允许上报IPv4 + 头部长度错误中断。 */ + unsigned int ipv4VerErrMask : 1; /* * [15:15]1'b1：允许上报IPv4 Version错误中断；1'b0：不允许上报IPv4 + Version错误中断。 */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IP_ERR_MASK_U; + +/* ** + * Union name : IPSURX_ROCE_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRoceErr { + struct tagStIpsurxRoceErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]reserved. */ + unsigned int rocev1DgidMerr : 1; /* * [19:19]1'b1: 发生多次RoCEv1 DGID错误。1'b0：未发生多次RoCEv1 DGID错误。 */ + unsigned int rocev1DgidErr : 1; /* * [18:18]1'b1: 发生RoCEv1 DGID错误。1'b0：未发生RoCEv1 DGID错误。 */ + unsigned int rocev1SgidMerr : 1; /* * [17:17]1'b1: 发生多次RoCEv1 SGID错误。1'b0：未发生多次RoCEv1 SGID错误。 */ + unsigned int rocev1SgidErr : 1; /* * [16:16]1'b1: 发生RoCEv1 SGID错误。1'b0：未发生RoCEv1 SGID错误。 */ + unsigned int rocev1IpverMerr : 1; /* * [15:15]1'b1: 发生多次RoCEv1 IPVer错误。1'b0：未发生多次RoCEv1 IPVer错误。 + */ + unsigned int rocev1IpverErr : 1; /* * [14:14]1'b1: 发生RoCEv1 IPVer错误。1'b0：未发生RoCEv1 IPVer错误。 */ + unsigned int rocev1NxhdrMerr : 1; /* * [13:13]1'b1: 发生多次RoCEv1 NXHDR错误。1'b0：未发生多次RoCEv1 NXHDR错误。 + */ + unsigned int rocev1NxhdrErr : 1; /* * [12:12]1'b1: 发生RoCEv1 NXHDR错误。1'b0：未发生RoCEv1 NXHDR错误。 */ + unsigned int rocev1PlenMerr : 1; /* * [11:11]1'b1: 发生多次RoCEv1 PayLen错误。1'b0：未发生多次RoCEv1 + * PayLen错误。 + */ + unsigned int rocev1PlenErr : 1; /* * [10:10]1'b1: 发生RoCEv1 PayLen错误。1'b0：未发生RoCEv1 PayLen错误。 */ + unsigned int rocev2Ipv4FragMerr : 1; /* * [9:9]1'b1: 发生多次RoCEv2 IPv4分片错误。1'b0：未发生多次RoCEv2 + IPv4分片错误。 */ + unsigned int rocev2Ipv4FragErr : 1; /* * [8:8]1'b1: 发生RoCEv2 IPv4分片错误。1'b0：未发生RoCEv2 IPv4分片错误。 + */ + unsigned int rocev2Ipv4UdpCsMerr : 1; /* * [7:7]1'b1: 发生多次RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv4 UDP CS校验错误。 */ + unsigned int rocev2Ipv4UdpCsErr : 1; /* * [6:6]1'b1: 发生RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生RoCEv2 IPv4 UDP + CS校验错误。 */ + unsigned int rocev2Ipv6UdpCsMerr : 1; /* * [5:5]1'b1: 发生多次RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv6 UDP CS校验错误。 */ + unsigned int rocev2Ipv6UdpCsErr : 1; /* * [4:4]1'b1: 发生RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生RoCEv2 IPv6 UDP + CS校验错误。 */ + unsigned int roceDqpMerr : 1; /* * [3:3]1'b1: 发生多次RoCE DQP错误。1'b0：未发生多次RoCE DQP错误。 */ + unsigned int roceDqpErr : 1; /* * [2:2]1'b1: 发生RoCE DQP错误。1'b0：未发生RoCE DQP错误。 */ + unsigned int ibIcrcMerr : 1; /* * [1:1]1'b1: 发生多次RoCE ICRC校验错误。1'b0：未发生多次RoCE ICRC校验错误。 */ + unsigned int ibIcrcErr : 1; /* * [0:0]1'b1: 发生RoCE ICRC校验错误。1'b0：未发生RoCE ICRC校验错误。 */ +#else + unsigned int ibIcrcErr : 1; /* * [0:0]1'b1: 发生RoCE ICRC校验错误。1'b0：未发生RoCE ICRC校验错误。 */ + unsigned int ibIcrcMerr : 1; /* * [1:1]1'b1: 发生多次RoCE ICRC校验错误。1'b0：未发生多次RoCE ICRC校验错误。 */ + unsigned int roceDqpErr : 1; /* * [2:2]1'b1: 发生RoCE DQP错误。1'b0：未发生RoCE DQP错误。 */ + unsigned int roceDqpMerr : 1; /* * [3:3]1'b1: 发生多次RoCE DQP错误。1'b0：未发生多次RoCE DQP错误。 */ + unsigned int rocev2Ipv6UdpCsErr : 1; /* * [4:4]1'b1: 发生RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生RoCEv2 IPv6 UDP + CS校验错误。 */ + unsigned int rocev2Ipv6UdpCsMerr : 1; /* * [5:5]1'b1: 发生多次RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv6 UDP CS校验错误。 */ + unsigned int rocev2Ipv4UdpCsErr : 1; /* * [6:6]1'b1: 发生RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生RoCEv2 IPv4 UDP + CS校验错误。 */ + unsigned int rocev2Ipv4UdpCsMerr : 1; /* * [7:7]1'b1: 发生多次RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv4 UDP CS校验错误。 */ + unsigned int rocev2Ipv4FragErr : 1; /* * [8:8]1'b1: 发生RoCEv2 IPv4分片错误。1'b0：未发生RoCEv2 IPv4分片错误。 + */ + unsigned int rocev2Ipv4FragMerr : 1; /* * [9:9]1'b1: 发生多次RoCEv2 IPv4分片错误。1'b0：未发生多次RoCEv2 + IPv4分片错误。 */ + unsigned int rocev1PlenErr : 1; /* * [10:10]1'b1: 发生RoCEv1 PayLen错误。1'b0：未发生RoCEv1 PayLen错误。 */ + unsigned int rocev1PlenMerr : 1; /* * [11:11]1'b1: 发生多次RoCEv1 PayLen错误。1'b0：未发生多次RoCEv1 + * PayLen错误。 + */ + unsigned int rocev1NxhdrErr : 1; /* * [12:12]1'b1: 发生RoCEv1 NXHDR错误。1'b0：未发生RoCEv1 NXHDR错误。 */ + unsigned int rocev1NxhdrMerr : 1; /* * [13:13]1'b1: 发生多次RoCEv1 NXHDR错误。1'b0：未发生多次RoCEv1 NXHDR错误。 + */ + unsigned int rocev1IpverErr : 1; /* * [14:14]1'b1: 发生RoCEv1 IPVer错误。1'b0：未发生RoCEv1 IPVer错误。 */ + unsigned int rocev1IpverMerr : 1; /* * [15:15]1'b1: 发生多次RoCEv1 IPVer错误。1'b0：未发生多次RoCEv1 IPVer错误。 + */ + unsigned int rocev1SgidErr : 1; /* * [16:16]1'b1: 发生RoCEv1 SGID错误。1'b0：未发生RoCEv1 SGID错误。 */ + unsigned int rocev1SgidMerr : 1; /* * [17:17]1'b1: 发生多次RoCEv1 SGID错误。1'b0：未发生多次RoCEv1 SGID错误。 */ + unsigned int rocev1DgidErr : 1; /* * [18:18]1'b1: 发生RoCEv1 DGID错误。1'b0：未发生RoCEv1 DGID错误。 */ + unsigned int rocev1DgidMerr : 1; /* * [19:19]1'b1: 发生多次RoCEv1 DGID错误。1'b0：未发生多次RoCEv1 DGID错误。 */ + unsigned int reserved : 12; /* * [31:20]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ERR_U; + +/* ** + * Union name : IPSURX_ROCE_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxRoceErrMask { + struct tagStIpsurxRoceErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved. */ + unsigned int rocev1DgidErrMask : 1; /* * [9:9]1'b1：允许上报RoCEv1 DGID错误中断；1'b0：不允许上报RoCEv1 + DGID错误中断。 */ + unsigned int rocev1SgidErrMask : 1; /* * [8:8]1'b1：允许上报RoCEv1 SGID错误中断；1'b0：不允许上报RoCEv1 + SGID错误中断。 */ + unsigned int rocev1IpverErrMask : 1; /* * [7:7]1'b1：允许上报RoCEv1 IPVer错误中断；1'b0：不允许上报RoCEv1 + IPVer错误中断。 */ + unsigned int rocev1NxhdrErrMask : 1; /* * [6:6]1'b1：允许上报RoCEv1 NXHDR错误中断；1'b0：不允许上报RoCEv1 + NXHDR错误中断。 */ + unsigned int rocev1PlenErrMask : 1; /* * [5:5]1'b1：允许上报RoCEv1 PayLen错误中断；1'b0：不允许上报RoCEv1 + PayLen错误中断。 */ + unsigned int rocev2Ipv4FragErrMask : 1; /* * [4:4]1'b1：允许上报RoCEv2 IPv4分片错误中断；1'b0：不允许上报RoCEv2 + IPv4分片错误中断。 */ + unsigned int rocev2Ipv4UdpCsErrMask : 1; /* * [3:3]1'b1：允许上报RoCEv2 IPv4 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv4 UDP CS校验错误中断。 */ + unsigned int rocev2Ipv6UdpCsErrMask : 1; /* * [2:2]1'b1：允许上报RoCEv2 IPv6 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv6 UDP CS校验错误中断。 */ + unsigned int roceDqpErrMask : 1; /* * [1:1]1'b1：允许上报RoCE DQP错误中断；1'b0：不允许上报RoCE DQP错误中断。 */ + unsigned int ibIcrcErrMask : 1; /* * [0:0]1'b1：允许上报RoCE ICRC校验错误中断；1'b0：不允许上报RoCE + ICRC校验错误中断。 */ +#else + unsigned int ibIcrcErrMask : 1; /* * [0:0]1'b1：允许上报RoCE ICRC校验错误中断；1'b0：不允许上报RoCE + ICRC校验错误中断。 */ + unsigned int roceDqpErrMask : 1; /* * [1:1]1'b1：允许上报RoCE DQP错误中断；1'b0：不允许上报RoCE DQP错误中断。 */ + unsigned int rocev2Ipv6UdpCsErrMask : 1; /* * [2:2]1'b1：允许上报RoCEv2 IPv6 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv6 UDP CS校验错误中断。 */ + unsigned int rocev2Ipv4UdpCsErrMask : 1; /* * [3:3]1'b1：允许上报RoCEv2 IPv4 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv4 UDP CS校验错误中断。 */ + unsigned int rocev2Ipv4FragErrMask : 1; /* * [4:4]1'b1：允许上报RoCEv2 IPv4分片错误中断；1'b0：不允许上报RoCEv2 + IPv4分片错误中断。 */ + unsigned int rocev1PlenErrMask : 1; /* * [5:5]1'b1：允许上报RoCEv1 PayLen错误中断；1'b0：不允许上报RoCEv1 + PayLen错误中断。 */ + unsigned int rocev1NxhdrErrMask : 1; /* * [6:6]1'b1：允许上报RoCEv1 NXHDR错误中断；1'b0：不允许上报RoCEv1 + NXHDR错误中断。 */ + unsigned int rocev1IpverErrMask : 1; /* * [7:7]1'b1：允许上报RoCEv1 IPVer错误中断；1'b0：不允许上报RoCEv1 + IPVer错误中断。 */ + unsigned int rocev1SgidErrMask : 1; /* * [8:8]1'b1：允许上报RoCEv1 SGID错误中断；1'b0：不允许上报RoCEv1 + SGID错误中断。 */ + unsigned int rocev1DgidErrMask : 1; /* * [9:9]1'b1：允许上报RoCEv1 DGID错误中断；1'b0：不允许上报RoCEv1 + DGID错误中断。 */ + unsigned int reserved : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ERR_MASK_U; + +/* ** + * Union name : IPSURX_OTH_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxOthErr { + struct tagStIpsurxOthErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int dropByTcamMerr : 1; /* * [21:21]1'b1: + 发生多次TCAM查找结果指示丢弃报文。1'b0：未发生多次TCAM查找结果指示丢弃报文。 + */ + unsigned int dropByTcamErr : 1; /* * [20:20]1'b1: + 发生TCAM查找结果指示丢弃报文。1'b0：未发生TCAM查找结果指示丢弃报文。 */ + unsigned int + directToUpPktMerr : 1; /* * [19:19]1'b1: + 发生多次直接转发到UP的报文校验错误。1'b0：未发生多次直接转发到UP的报文校验错误。 + */ + unsigned int directToUpPktErr : 1; /* * [18:18]1'b1: + 发生直接转发到UP的报文校验错误。1'b0：未发生直接转发到UP的报文校验错误。 + */ + unsigned int dmacZeroMerr : 1; /* * [17:17]1'b1: 发生多次目的MAC为0错误。1'b0：未发生多次目的MAC为0错误。 */ + unsigned int dmacZeroErr : 1; /* * [16:16]1'b1: 发生目的MAC为0错误。1'b0：未发生目的MAC为0错误。 */ + unsigned int smacMerr : 1; /* * [15:15]1'b1: 发生多次源MAC错误。1'b0：未发生多次源MAC错误。 */ + unsigned int smacErr : 1; /* * [14:14]1'b1: 发生源MAC错误。1'b0：未发生源MAC错误。 */ + unsigned int dmacSmacEqualMerr : 1; /* * [13:13]1'b1: + 发生多次目的MAC等于源MAC错误。1'b0：未发生多次目的MAC等于源MAC错误。 */ + unsigned int dmacSmacEqualErr : 1; /* * [12:12]1'b1: + * 发生目的MAC等于源MAC错误。1'b0：未发生目的MAC等于源MAC错误。 + */ + unsigned int arpPosiMerr : 1; /* * [11:11]1'b1: 发生多次ARP DMAC为单播错误。1'b0：未发生多次ARP DMAC为单播错误。 + */ + unsigned int arpPosiErr : 1; /* * [10:10]1'b1: 发生ARP DMAC为单播错误。1'b0：未发生ARP DMAC为单播错误。 */ + unsigned int ethLlcLenMerr : 1; /* * [9:9]1'b1: 发生多次LLC/SNAP Length校验错误。1'b0：未发生多次LLC/SNAP + Length校验错误。 */ + unsigned int ethLlcLenErr : 1; /* * [8:8]1'b1: 发生LLC/SNAP Length校验错误。1'b0：未发生LLC/SNAP + * Length校验错误。 + */ + unsigned int pktLenMinMerr : 1; /* * [7:7]1'b1: 发生多次最小包长错误。1'b0：未发生多次最小包长错误。 */ + unsigned int pktLenMinErr : 1; /* * [6:6]1'b1: 发生最小包长错误。1'b0：未发生最小包长错误。 */ + unsigned int pktLenMaxMerr : 1; /* * [5:5]1'b1: 发生多次最长包长错误。1'b0：未发生多次最长包长错误。 */ + unsigned int pktLenMaxErr : 1; /* * [4:4]1'b1: 发生最长包长错误。1'b0：未发生最长包长错误。 */ + unsigned int fcCrcMerr : 1; /* * [3:3]1'b1: 发生多次FC CRC校验错误。1'b0：未发生多次FC CRC校验错误。 */ + unsigned int fcCrcErr : 1; /* * [2:2]1'b1: 发生FC CRC校验错误。1'b0：未发生FC CRC校验错误。 */ + unsigned int toBmcOnlyPktMerr : 1; /* * [1:1]1'b1: 发生多次TO BMC ONLY错误。1'b0：未发生多次TO BMC ONLY错误。 */ + unsigned int toBmcOnlyPktErr : 1; /* * [0:0]1'b1: 发生TO BMC ONLY校验错误。1'b0：未发生TO BMC ONLY校验错误。 */ +#else + unsigned int toBmcOnlyPktErr : 1; /* * [0:0]1'b1: 发生TO BMC ONLY校验错误。1'b0：未发生TO BMC ONLY校验错误。 */ + unsigned int toBmcOnlyPktMerr : 1; /* * [1:1]1'b1: 发生多次TO BMC ONLY错误。1'b0：未发生多次TO BMC ONLY错误。 */ + unsigned int fcCrcErr : 1; /* * [2:2]1'b1: 发生FC CRC校验错误。1'b0：未发生FC CRC校验错误。 */ + unsigned int fcCrcMerr : 1; /* * [3:3]1'b1: 发生多次FC CRC校验错误。1'b0：未发生多次FC CRC校验错误。 */ + unsigned int pktLenMaxErr : 1; /* * [4:4]1'b1: 发生最长包长错误。1'b0：未发生最长包长错误。 */ + unsigned int pktLenMaxMerr : 1; /* * [5:5]1'b1: 发生多次最长包长错误。1'b0：未发生多次最长包长错误。 */ + unsigned int pktLenMinErr : 1; /* * [6:6]1'b1: 发生最小包长错误。1'b0：未发生最小包长错误。 */ + unsigned int pktLenMinMerr : 1; /* * [7:7]1'b1: 发生多次最小包长错误。1'b0：未发生多次最小包长错误。 */ + unsigned int ethLlcLenErr : 1; /* * [8:8]1'b1: 发生LLC/SNAP Length校验错误。1'b0：未发生LLC/SNAP + * Length校验错误。 + */ + unsigned int ethLlcLenMerr : 1; /* * [9:9]1'b1: 发生多次LLC/SNAP Length校验错误。1'b0：未发生多次LLC/SNAP + Length校验错误。 */ + unsigned int arpPosiErr : 1; /* * [10:10]1'b1: 发生ARP DMAC为单播错误。1'b0：未发生ARP DMAC为单播错误。 */ + unsigned int arpPosiMerr : 1; /* * [11:11]1'b1: 发生多次ARP DMAC为单播错误。1'b0：未发生多次ARP DMAC为单播错误。 + */ + unsigned int dmacSmacEqualErr : 1; /* * [12:12]1'b1: + * 发生目的MAC等于源MAC错误。1'b0：未发生目的MAC等于源MAC错误。 + */ + unsigned int dmacSmacEqualMerr : 1; /* * [13:13]1'b1: + 发生多次目的MAC等于源MAC错误。1'b0：未发生多次目的MAC等于源MAC错误。 */ + unsigned int smacErr : 1; /* * [14:14]1'b1: 发生源MAC错误。1'b0：未发生源MAC错误。 */ + unsigned int smacMerr : 1; /* * [15:15]1'b1: 发生多次源MAC错误。1'b0：未发生多次源MAC错误。 */ + unsigned int dmacZeroErr : 1; /* * [16:16]1'b1: 发生目的MAC为0错误。1'b0：未发生目的MAC为0错误。 */ + unsigned int dmacZeroMerr : 1; /* * [17:17]1'b1: 发生多次目的MAC为0错误。1'b0：未发生多次目的MAC为0错误。 */ + unsigned int directToUpPktErr : 1; /* * [18:18]1'b1: + 发生直接转发到UP的报文校验错误。1'b0：未发生直接转发到UP的报文校验错误。 + */ + unsigned int + directToUpPktMerr : 1; /* * [19:19]1'b1: + 发生多次直接转发到UP的报文校验错误。1'b0：未发生多次直接转发到UP的报文校验错误。 + */ + unsigned int dropByTcamErr : 1; /* * [20:20]1'b1: + 发生TCAM查找结果指示丢弃报文。1'b0：未发生TCAM查找结果指示丢弃报文。 */ + unsigned int dropByTcamMerr : 1; /* * [21:21]1'b1: + 发生多次TCAM查找结果指示丢弃报文。1'b0：未发生多次TCAM查找结果指示丢弃报文。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_OTH_ERR_U; + +/* ** + * Union name : IPSURX_OTH_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxOthErrMask { + struct tagStIpsurxOthErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11]reserved. */ + unsigned int + dropByTcamErrMask : 1; /* * [10:10]1'b1: + 允许上报TCAM查找结果指示丢弃报文。1'b0：不允许上报TCAM查找结果指示丢弃报文。 + */ + unsigned int + directToUpPktErrMask : 1; /* * [9:9]1'b1: + 允许上报直接转发到UP的报文校验错误。1'b0：不允许上报直接转发到UP的报文校验错误。 + */ + unsigned int + dmacZeroErrMask : 1; /* * [8:8]1'b1：允许上报目的MAC为0错误中断；1'b0：不允许上报目的MAC为0错误中断。 */ + unsigned int smacErrMask : 1; /* * [7:7]1'b1：允许上报源MAC错误中断；1'b0：不允许上报源MAC错误中断。 */ + unsigned int dmacSmacEqualErrMask : 1; /* * + [6:6]1'b1：允许上报源MAC等于目的MAC错误中断；1'b0：不允许上报MAC等于目的MAC错误中断。 + */ + unsigned int arpPosiErrMask : 1; /* * + [5:5]1'b1：允许上报ARP目的MAC为单播地址错误中断；1'b0：不允许上报ARP目的MAC为单播地址错误中断。 + */ + unsigned int ethLlcLenErrMask : 1; /* * [4:4]1'b1：允许上报LLC/SNAP Length校验错误中断；1'b0：不允许上报LLC/SNAP + Length校验错误中断。 */ + unsigned int pktLenMinErrMask : 1; /* * [3:3]1'b1：允许上报最小长度错误中断；1'b0：不允许上报最小长度错误中断。 + */ + unsigned int pktLenMaxErrMask : 1; /* * [2:2]1'b1：允许上报最大长度错误中断；1'b0：不允许上报最大长度错误中断。 + */ + unsigned int fcCrcErrMask : 1; /* * [1:1]1'b1：允许上报FC CRC校验错误中断；1'b0：不允许上报FC CRC校验错误中断。 + */ + unsigned int toBmcOnlyPktErrMask : 1; /* * [0:0]1'b1：允许上报TO BMC ONLY错误中断；1'b0：不允许上报TO BMC + ONLY错误中断。 */ +#else + unsigned int toBmcOnlyPktErrMask : 1; /* * [0:0]1'b1：允许上报TO BMC ONLY错误中断；1'b0：不允许上报TO BMC + ONLY错误中断。 */ + unsigned int fcCrcErrMask : 1; /* * [1:1]1'b1：允许上报FC CRC校验错误中断；1'b0：不允许上报FC CRC校验错误中断。 + */ + unsigned int pktLenMaxErrMask : 1; /* * [2:2]1'b1：允许上报最大长度错误中断；1'b0：不允许上报最大长度错误中断。 + */ + unsigned int pktLenMinErrMask : 1; /* * [3:3]1'b1：允许上报最小长度错误中断；1'b0：不允许上报最小长度错误中断。 + */ + unsigned int ethLlcLenErrMask : 1; /* * [4:4]1'b1：允许上报LLC/SNAP Length校验错误中断；1'b0：不允许上报LLC/SNAP + Length校验错误中断。 */ + unsigned int arpPosiErrMask : 1; /* * + [5:5]1'b1：允许上报ARP目的MAC为单播地址错误中断；1'b0：不允许上报ARP目的MAC为单播地址错误中断。 + */ + unsigned int dmacSmacEqualErrMask : 1; /* * + [6:6]1'b1：允许上报源MAC等于目的MAC错误中断；1'b0：不允许上报MAC等于目的MAC错误中断。 + */ + unsigned int smacErrMask : 1; /* * [7:7]1'b1：允许上报源MAC错误中断；1'b0：不允许上报源MAC错误中断。 */ + unsigned int + dmacZeroErrMask : 1; /* * [8:8]1'b1：允许上报目的MAC为0错误中断；1'b0：不允许上报目的MAC为0错误中断。 */ + unsigned int + directToUpPktErrMask : 1; /* * [9:9]1'b1: + 允许上报直接转发到UP的报文校验错误。1'b0：不允许上报直接转发到UP的报文校验错误。 + */ + unsigned int + dropByTcamErrMask : 1; /* * [10:10]1'b1: + 允许上报TCAM查找结果指示丢弃报文。1'b0：不允许上报TCAM查找结果指示丢弃报文。 + */ + unsigned int reserved : 21; /* * [31:11]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_OTH_ERR_MASK_U; + +/* ** + * Union name : IPSURX_IPSUTX_AFIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxIpsutxAfifoOvfl { + struct tagStIpsurxIpsutxAfifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]IPSUTX时钟域到IPSURX时钟域溢出异步FIFO编号。1'b0: IPSUTX到IPSURX + * CSR异步FIFO溢出；1'b1: IPSUTX到IPSURX 中断CSR异步FIFO溢出。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 1; /* * [2:2]IPSUTX时钟域到IPSURX时钟域溢出异步FIFO编号。1'b0: IPSUTX到IPSURX + * CSR异步FIFO溢出；1'b1: IPSUTX到IPSURX 中断CSR异步FIFO溢出。 + */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPSUTX_AFIFO_OVFL_U; + + +/* ** + * Union name : IPSURX_INDRECT_CTRL + * @brief 间接寻址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectCtrl { + struct tagStIpsurxIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxIndrectVld : 1; /* * + * [31:31]VALID：CPU发起读、写操作时将VALID域置1，内部一次操作完成后将VALID清零。具体为：内部成功写/读操作之后，将VALID清零，读操作TIMEOUT后也将VALID清零。 + */ + unsigned int ipsurxIndrectMode : 1; /* * [30:30]OPERATION_MODE.1'b1 : Read;1'b0 : Write. */ + unsigned int ipsurxIndrectStat : 2; /* * [29:28]STATUS :2'b00: OK;2'b01: Time out;Others: Reserved. */ + unsigned int ipsurxIndrectTab : 4; /* * [27:24]bit[3:2]保留未用，bit[1:0]表示间接寻址表编号： + 0x0：TCAM/ART表；0x1：TPT表；Others: 保留未用。 */ + unsigned int ipsurxIndrectAddr : 24; /* * [23:0]模块间接寻址MEM地址。TCAM + * TABLE：寻址范围为0~511，仅bit[8:0]有效；TPT + * TABLE：寻址范围为0~2047，仅bit[10:0]有效。 + */ +#else + unsigned int ipsurxIndrectAddr : 24; /* * [23:0]模块间接寻址MEM地址。TCAM + * TABLE：寻址范围为0~511，仅bit[8:0]有效；TPT + * TABLE：寻址范围为0~2047，仅bit[10:0]有效。 + */ + unsigned int ipsurxIndrectTab : 4; /* * [27:24]bit[3:2]保留未用，bit[1:0]表示间接寻址表编号： + 0x0：TCAM/ART表；0x1：TPT表；Others: 保留未用。 */ + unsigned int ipsurxIndrectStat : 2; /* * [29:28]STATUS :2'b00: OK;2'b01: Time out;Others: Reserved. */ + unsigned int ipsurxIndrectMode : 1; /* * [30:30]OPERATION_MODE.1'b1 : Read;1'b0 : Write. */ + unsigned int + ipsurxIndrectVld : 1; /* * + * [31:31]VALID：CPU发起读、写操作时将VALID域置1，内部一次操作完成后将VALID清零。具体为：内部成功写/读操作之后，将VALID清零，读操作TIMEOUT后也将VALID清零。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_CTRL_U; + +/* ** + * Union name : IPSURX_INDRECT_TIMEOUT + * @brief 间接寻址TIMEOUT配置寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectTimeout { + struct tagStIpsurxIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectTimeout : 32; /* * + [31:0]间接寻址TIMEOUT配置寄存器。发起的间接读/写没有返回时，不能改变该值。 + */ +#else + unsigned int ipsurxIndrectTimeout : 32; /* * + [31:0]间接寻址TIMEOUT配置寄存器。发起的间接读/写没有返回时，不能改变该值。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_TIMEOUT_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA0 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData0 { + struct tagStIpsurxIndrectData0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData0 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData0 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA0_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA1 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData1 { + struct tagStIpsurxIndrectData1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData1 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData1 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA1_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA2 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData2 { + struct tagStIpsurxIndrectData2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData2 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData2 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA2_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA3 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData3 { + struct tagStIpsurxIndrectData3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData3 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData3 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA3_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA4 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData4 { + struct tagStIpsurxIndrectData4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData4 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData4 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA4_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA5 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData5 { + struct tagStIpsurxIndrectData5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData5 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData5 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA5_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA6 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData6 { + struct tagStIpsurxIndrectData6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData6 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData6 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA6_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA7 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData7 { + struct tagStIpsurxIndrectData7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData7 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData7 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA7_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA8 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData8 { + struct tagStIpsurxIndrectData8 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData8 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData8 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA8_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA9 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData9 { + struct tagStIpsurxIndrectData9 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData9 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData9 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA9_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA10 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData10 { + struct tagStIpsurxIndrectData10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData10 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData10 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA10_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA11 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData11 { + struct tagStIpsurxIndrectData11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData11 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData11 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA11_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA12 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData12 { + struct tagStIpsurxIndrectData12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData12 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData12 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA12_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA13 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData13 { + struct tagStIpsurxIndrectData13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData13 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData13 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA13_U; + + +/* ** + * Union name : IPSURX_CH16_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw0 { + struct tagStIpsurxCh16AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh16Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh16Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh161588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh16Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh16Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh16CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh16SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh161588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh16Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh16Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw1 { + struct tagStIpsurxCh16AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh16DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh168023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh16Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh16Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh16Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh16Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh16ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh168023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw2 { + struct tagStIpsurxCh16AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh16Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh16Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh16FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh16FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh16RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh16Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw3 { + struct tagStIpsurxCh16AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh16MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh16MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh16PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh16PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh16MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh16MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw4 { + struct tagStIpsurxCh16AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh16DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh16DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh16DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh16DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh16DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh16DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh16DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh16DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw0 { + struct tagStIpsurxCh15AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh15Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh15Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh151588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh15Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh15Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh15CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh15SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh151588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh15Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh15Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw1 { + struct tagStIpsurxCh15AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh15DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh158023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh15Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh15Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh15Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh15Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh15ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh158023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw2 { + struct tagStIpsurxCh15AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh15Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh15Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh15FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh15FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh15RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh15Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw3 { + struct tagStIpsurxCh15AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh15MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh15MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh15PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh15PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh15MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh15MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw4 { + struct tagStIpsurxCh15AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh15DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh15DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh15DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh15DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh15DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh15DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh15DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh15DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw0 { + struct tagStIpsurxCh14AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh14Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh14Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh141588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh14Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh14Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh14CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh14SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh141588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh14Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh14Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw1 { + struct tagStIpsurxCh14AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh14DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh148023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh14Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh14Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh14Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh14Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh14ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh148023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw2 { + struct tagStIpsurxCh14AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh14Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh14Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh14FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh14FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh14RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh14Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw3 { + struct tagStIpsurxCh14AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh14MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh14MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh14PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh14PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh14MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh14MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw4 { + struct tagStIpsurxCh14AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh14DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh14DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh14DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh14DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh14DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh14DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh14DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh14DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw0 { + struct tagStIpsurxCh13AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh13Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh13Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh131588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh13Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh13Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh13CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh13SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh131588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh13Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh13Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw1 { + struct tagStIpsurxCh13AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh13DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh138023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh13Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh13Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh13Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh13Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh13ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh138023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw2 { + struct tagStIpsurxCh13AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh13Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh13Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh13FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh13FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh13RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh13Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw3 { + struct tagStIpsurxCh13AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh13MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh13MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh13PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh13PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh13MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh13MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw4 { + struct tagStIpsurxCh13AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh13DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh13DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh13DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh13DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh13DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh13DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh13DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh13DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw0 { + struct tagStIpsurxCh12AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh12Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh12Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh121588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh12Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh12Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh12CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh12SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh121588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh12Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh12Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw1 { + struct tagStIpsurxCh12AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh12DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh128023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh12Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh12Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh12Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh12Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh12ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh128023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw2 { + struct tagStIpsurxCh12AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh12Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh12Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh12FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh12FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh12RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh12Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw3 { + struct tagStIpsurxCh12AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh12MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh12MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh12PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh12PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh12MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh12MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw4 { + struct tagStIpsurxCh12AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh12DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh12DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh12DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh12DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh12DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh12DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh12DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh12DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw0 { + struct tagStIpsurxCh11AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh11Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh11Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh111588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh11Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh11Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh11CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh11SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh111588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh11Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh11Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw1 { + struct tagStIpsurxCh11AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh11DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh118023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh11Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh11Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh11Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh11Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh11ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh118023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw2 { + struct tagStIpsurxCh11AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh11Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh11Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh11FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh11FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh11RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh11Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw3 { + struct tagStIpsurxCh11AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh11MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh11MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh11PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh11PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh11MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh11MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw4 { + struct tagStIpsurxCh11AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh11DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh11DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh11DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh11DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh11DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh11DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh11DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh11DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw0 { + struct tagStIpsurxCh10AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh10Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh10Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh101588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh10Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh10Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh10CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh10SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh101588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh10Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh10Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw1 { + struct tagStIpsurxCh10AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh10DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh108023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh10Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh10Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh10Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh10Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh10ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh108023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw2 { + struct tagStIpsurxCh10AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh10Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh10Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh10FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh10FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh10RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh10Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw3 { + struct tagStIpsurxCh10AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh10MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh10MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh10PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh10PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh10MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh10MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw4 { + struct tagStIpsurxCh10AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh10DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh10DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh10DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh10DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh10DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh10DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh10DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh10DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw0 { + struct tagStIpsurxCh09AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh09Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh09Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh091588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh09Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh09Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh09CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh09SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh091588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh09Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh09Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw1 { + struct tagStIpsurxCh09AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh09DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh098023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh09Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh09Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh09Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh09Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh09ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh098023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw2 { + struct tagStIpsurxCh09AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh09Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh09Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh09FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh09FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh09RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh09Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw3 { + struct tagStIpsurxCh09AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh09MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh09MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh09PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh09PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh09MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh09MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw4 { + struct tagStIpsurxCh09AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh09DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh09DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh09DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh09DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh09DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh09DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh09DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh09DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw0 { + struct tagStIpsurxCh08AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh08Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh08Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh081588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh08Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh08Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh08CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh08SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh081588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh08Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh08Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw1 { + struct tagStIpsurxCh08AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh08DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh088023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh08Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh08Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh08Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh08Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh08ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh088023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw2 { + struct tagStIpsurxCh08AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh08Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh08Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh08FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh08FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh08RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh08Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw3 { + struct tagStIpsurxCh08AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh08MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh08MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh08PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh08PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh08MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh08MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw4 { + struct tagStIpsurxCh08AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh08DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh08DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh08DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh08DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh08DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh08DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh08DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh08DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW4_U; + + +/* ** + * Union name : IPSURX_CH07_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw0 { + struct tagStIpsurxCh07AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh07Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh07Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh071588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh07Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh07Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh07CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh07SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh071588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh07Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh07Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw1 { + struct tagStIpsurxCh07AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh07DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh078023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh07Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh07Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh07Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh07Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh07ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh078023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw2 { + struct tagStIpsurxCh07AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh07Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh07Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh07FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh07FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh07RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh07Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw3 { + struct tagStIpsurxCh07AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh07MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh07MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh07PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh07PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh07MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh07MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw4 { + struct tagStIpsurxCh07AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh07DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh07DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh07DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh07DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh07DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh07DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh07DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh07DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw0 { + struct tagStIpsurxCh06AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh06Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh06Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh061588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh06Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh06Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh06CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh06SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh061588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh06Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh06Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw1 { + struct tagStIpsurxCh06AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh06DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh068023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh06Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh06Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh06Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh06Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh06ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh068023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw2 { + struct tagStIpsurxCh06AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh06Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh06Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh06FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh06FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh06RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh06Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw3 { + struct tagStIpsurxCh06AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh06MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh06MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh06PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh06PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh06MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh06MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw4 { + struct tagStIpsurxCh06AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh06DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh06DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh06DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh06DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh06DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh06DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh06DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh06DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw0 { + struct tagStIpsurxCh05AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh05Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh05Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh051588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh05Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh05Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh05CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh05SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh051588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh05Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh05Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw1 { + struct tagStIpsurxCh05AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh05DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh058023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh05Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh05Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh05Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh05Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh05ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh058023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw2 { + struct tagStIpsurxCh05AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh05Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh05Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh05FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh05FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh05RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh05Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw3 { + struct tagStIpsurxCh05AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh05MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh05MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh05PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh05PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh05MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh05MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw4 { + struct tagStIpsurxCh05AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh05DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh05DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh05DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh05DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh05DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh05DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh05DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh05DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw0 { + struct tagStIpsurxCh04AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh04Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh04Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh041588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh04Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh04Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh04CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh04SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh041588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh04Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh04Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw1 { + struct tagStIpsurxCh04AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh04DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh048023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh04Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh04Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh04Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh04Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh04ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh048023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw2 { + struct tagStIpsurxCh04AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh04Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh04Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh04FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh04FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh04RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh04Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw3 { + struct tagStIpsurxCh04AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh04MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh04MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh04PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh04PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh04MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh04MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw4 { + struct tagStIpsurxCh04AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh04DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh04DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh04DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh04DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh04DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh04DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh04DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh04DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw0 { + struct tagStIpsurxCh03AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh03Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh03Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh031588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh03Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh03Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh03CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh03SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh031588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh03Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh03Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw1 { + struct tagStIpsurxCh03AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh03DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh038023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh03Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh03Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh03Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh03Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh03ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh038023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw2 { + struct tagStIpsurxCh03AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh03Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh03Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh03FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh03FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh03RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh03Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw3 { + struct tagStIpsurxCh03AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh03MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh03MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh03PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh03PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh03MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh03MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw4 { + struct tagStIpsurxCh03AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh03DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh03DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh03DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh03DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh03DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh03DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh03DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh03DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw0 { + struct tagStIpsurxCh02AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh02Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh02Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh021588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh02Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh02Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh02CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh02SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh021588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh02Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh02Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw1 { + struct tagStIpsurxCh02AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh02DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh028023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh02Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh02Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh02Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh02Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh02ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh028023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw2 { + struct tagStIpsurxCh02AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh02Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh02Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh02FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh02FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh02RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh02Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw3 { + struct tagStIpsurxCh02AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh02MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh02MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh02PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh02PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh02MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh02MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw4 { + struct tagStIpsurxCh02AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh02DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh02DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh02DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh02DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh02DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh02DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh02DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh02DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw0 { + struct tagStIpsurxCh01AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh01Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh01Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh011588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh01Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh01Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh01CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh01SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh011588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh01Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh01Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw1 { + struct tagStIpsurxCh01AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh01DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh018023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh01Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh01Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh01Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh01Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh01ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh018023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw2 { + struct tagStIpsurxCh01AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh01Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh01Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh01FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh01FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh01RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh01Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw3 { + struct tagStIpsurxCh01AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh01MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh01MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh01PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh01PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh01MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh01MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw4 { + struct tagStIpsurxCh01AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh01DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh01DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh01DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh01DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh01DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh01DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh01DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh01DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw0 { + struct tagStIpsurxCh00AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh00Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh00Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh001588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh00Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh00Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh00CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh00SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh001588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh00Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh00Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw1 { + struct tagStIpsurxCh00AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh00DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh008023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh00Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh00Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh00Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh00Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh00ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh008023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw2 { + struct tagStIpsurxCh00AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh00Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh00Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh00FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh00FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh00RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh00Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw3 { + struct tagStIpsurxCh00AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh00MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh00MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh00PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh00PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh00MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh00MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw4 { + struct tagStIpsurxCh00AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh00DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh00DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh00DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh00DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh00DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh00DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh00DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh00DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH_INVLD_HST + * @brief 通道无效状态寄存器 + * Description: + */ +typedef union tagUnIpsurxChInvldHst { + struct tagStIpsurxChInvldHst { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17]reserved. */ + unsigned int + ipsurxCh16InvldHst : 1; /* * [16:16]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh15InvldHst : 1; /* * [15:15]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh14InvldHst : 1; /* * [14:14]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b1：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh13InvldHst : 1; /* * [13:13]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b2：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh12InvldHst : 1; /* * [12:12]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b3：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh11InvldHst : 1; /* * [11:11]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b4：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh10InvldHst : 1; /* * [10:10]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b5：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh9InvldHst : 1; /* * [9:9]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b6：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh8InvldHst : 1; /* * [8:8]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b7：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh7InvldHst : 1; /* * [7:7]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b8：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh6InvldHst : 1; /* * [6:6]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b9：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh5InvldHst : 1; /* * [5:5]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b10：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh4InvldHst : 1; /* * [4:4]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b11：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh3InvldHst : 1; /* * [3:3]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b12：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh2InvldHst : 1; /* * [2:2]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b13：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh1InvldHst : 1; /* * [1:1]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b14：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh0InvldHst : 1; /* * [0:0]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b15：未在通道未使能情况下收到数据。 + */ +#else + unsigned int + ipsurxCh0InvldHst : 1; /* * [0:0]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b15：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh1InvldHst : 1; /* * [1:1]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b14：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh2InvldHst : 1; /* * [2:2]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b13：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh3InvldHst : 1; /* * [3:3]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b12：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh4InvldHst : 1; /* * [4:4]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b11：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh5InvldHst : 1; /* * [5:5]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b10：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh6InvldHst : 1; /* * [6:6]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b9：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh7InvldHst : 1; /* * [7:7]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b8：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh8InvldHst : 1; /* * [8:8]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b7：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh9InvldHst : 1; /* * [9:9]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b6：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh10InvldHst : 1; /* * [10:10]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b5：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh11InvldHst : 1; /* * [11:11]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b4：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh12InvldHst : 1; /* * [12:12]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b3：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh13InvldHst : 1; /* * [13:13]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b2：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh14InvldHst : 1; /* * [14:14]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b1：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh15InvldHst : 1; /* * [15:15]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh16InvldHst : 1; /* * [16:16]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int reserved : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH_INVLD_HST_U; + +/* ** + * Union name : IPSURX_SOP_EOP_ST + * @brief SOP/EOP检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxSopEopSt { + struct tagStIpsurxSopEopSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved. */ + unsigned int ipsurxFicSopEopSt : 1; /* * [9:9]FIC端口输入报文的SOP/EOP检测状态1'b0：等待SOP1'b1：等待EOP */ + unsigned int ipsurxMagSopEopSt : 9; /* * [8:0]bit[0]：对应 MAG PORT0 输入数据的SOP/EOP状态。bit[1]：对应 MAG + PORT1 输入数据的SOP/EOP状态。……bit[7]：对应 MAG PORT7 + 输入数据的SOP/EOP状态。bit[8]：对应 MAG PORT16（回传时戳) + 输入数据的SOP/EOP状态。1'b0：等待SOP； 1'b1：等待EOP。 */ +#else + unsigned int ipsurxMagSopEopSt : 9; /* * [8:0]bit[0]：对应 MAG PORT0 输入数据的SOP/EOP状态。bit[1]：对应 MAG + PORT1 输入数据的SOP/EOP状态。……bit[7]：对应 MAG PORT7 + 输入数据的SOP/EOP状态。bit[8]：对应 MAG PORT16（回传时戳) + 输入数据的SOP/EOP状态。1'b0：等待SOP； 1'b1：等待EOP。 */ + unsigned int ipsurxFicSopEopSt : 1; /* * [9:9]FIC端口输入报文的SOP/EOP检测状态1'b0：等待SOP1'b1：等待EOP */ + unsigned int reserved : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_EOP_ST_U; + +/* ** + * Union name : IPSURX_SOP_WITH_ERR_CNT + * @brief SOP_WITH_ERR错误计数器 + * Description: + */ +typedef union tagUnIpsurxSopWithErrCnt { + struct tagStIpsurxSopWithErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSopWithErrCnt : 32; /* * [31:0]统计当处于WSOP时，输入数据有效，但SOP无效的数据的拍数。 */ +#else + unsigned int ipsurxSopWithErrCnt : 32; /* * [31:0]统计当处于WSOP时，输入数据有效，但SOP无效的数据的拍数。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_WITH_ERR_CNT_U; + +/* ** + * Union name : IPSURX_ABORT_BF_IPSURX_CNT + * @brief ABORT_BF_IPSURX错误计数器 + * Description: + */ +typedef union tagUnIpsurxAbortBfIpsurxCnt { + struct tagStIpsurxAbortBfIpsurxCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxAbortBfIpsurxCnt : 32; /* * [31:0]统计输入数据有效，前一级模块指示abort的数据。 */ +#else + unsigned int ipsurxAbortBfIpsurxCnt : 32; /* * [31:0]统计输入数据有效，前一级模块指示abort的数据。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ABORT_BF_IPSURX_CNT_U; + +/* ** + * Union name : IPSURX_SOP_SOP_ERR_CNT + * @brief SOP_SOP错误计数器 + * Description: + */ +typedef union tagUnIpsurxSopSopErrCnt { + struct tagStIpsurxSopSopErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSopSopErrCnt : 32; /* * [31:0]统计当处于WEOP时，输入数据有效，SOP连续出现的错误。 */ +#else + unsigned int ipsurxSopSopErrCnt : 32; /* * [31:0]统计当处于WEOP时，输入数据有效，SOP连续出现的错误。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_SOP_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PKT_MIN_LEN_ILGL_CNT + * @brief 接收超短报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxPktMinLenIlglCnt { + struct tagStIpsurxPktMinLenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPktMinLenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPktMinLenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PKT_MIN_LEN_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_PKT_MAX_LEN_ILGL_CNT + * @brief 接收超长报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxPktMaxLenIlglCnt { + struct tagStIpsurxPktMaxLenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPktMaxLenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPktMaxLenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PKT_MAX_LEN_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_NP2NP_FIELD_LOC + * @brief NP2NP头字段位置配置寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npFieldLoc { + struct tagStIpsurxNp2npFieldLoc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved. */ + unsigned int ipsurxNp2npSbLoc : 6; /* * [29:24]NP2NP头SB字段的起始位置。建议不修改默认值。 */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxNp2npColorLoc : 6; /* * [21:16]NP2NP头COLOR字段的起始位置。建议不修改默认值。 */ + unsigned int reserved2 : 2; /* * [15:14] */ + unsigned int ipsurxNp2npQindexLoc : 6; /* * [13:8]NP2NP头QINDEX字段的起始位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npFhlLoc : 4; /* * [7:4]NP2NP头FHL字段的起始位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npUcLoc : 4; /* * [3:0]NP2NP头UC比特位置。建议不修改默认值。 */ +#else + unsigned int ipsurxNp2npUcLoc : 4; /* * [3:0]NP2NP头UC比特位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npFhlLoc : 4; /* * [7:4]NP2NP头FHL字段的起始位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npQindexLoc : 6; /* * [13:8]NP2NP头QINDEX字段的起始位置。建议不修改默认值。 */ + unsigned int reserved2 : 2; /* * [15:14] */ + unsigned int ipsurxNp2npColorLoc : 6; /* * [21:16]NP2NP头COLOR字段的起始位置。建议不修改默认值。 */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxNp2npSbLoc : 6; /* * [29:24]NP2NP头SB字段的起始位置。建议不修改默认值。 */ + unsigned int reserved0 : 2; /* * [31:30]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_FIELD_LOC_U; + +/* ** + * Union name : IPSURX_NP2NP_TP_LOC + * @brief NP2NP头TP字段位置配置寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npTpLoc { + struct tagStIpsurxNp2npTpLoc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int ipsurxNp2npTpLoc : 6; /* * [5:0]NP2NP头TP字段的起始位置。建议不修改默认值。 */ +#else + unsigned int ipsurxNp2npTpLoc : 6; /* * [5:0]NP2NP头TP字段的起始位置。建议不修改默认值。 */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_TP_LOC_U; + +/* ** + * Union name : IPSURX_NP2NP_MCTP_SEL + * @brief NP2NP报文，多播TP映射选择寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npMctpSel { + struct tagStIpsurxNp2npMctpSel { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1] */ + unsigned int ipsurxNp2npMctpSel : 1; /* * [0:0]NP2NP报文，多播TP映射选择。1'b0：根据FIC模块的输入UC/MC + * FLAG来映射多播报文TP。1'b1：根据NP2NP头里的UC/MC + * FLAG来映射多播报文TP。建议不修改默认值。 + */ +#else + unsigned int ipsurxNp2npMctpSel : 1; /* * [0:0]NP2NP报文，多播TP映射选择。1'b0：根据FIC模块的输入UC/MC + * FLAG来映射多播报文TP。1'b1：根据NP2NP头里的UC/MC + * FLAG来映射多播报文TP。建议不修改默认值。 + */ + unsigned int reserved : 31; /* * [31:1] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_MCTP_SEL_U; + +/* ** + * Union name : IPSURX_NP2NP_HLEN + * @brief NP2NP头长度配置寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npHlen { + struct tagStIpsurxNp2npHlen { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int ipsurxNp2npFhl3Hlen : 5; /* * [28:24]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxNp2npFhl2Hlen : 5; /* * [20:16]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved2 : 3; /* * [15:13] */ + unsigned int ipsurxNp2npFhl1Hlen : 5; /* * [12:8]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxNp2npFhl0Hlen : 5; /* * [4:0]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ +#else + unsigned int ipsurxNp2npFhl0Hlen : 5; /* * [4:0]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxNp2npFhl1Hlen : 5; /* * [12:8]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved2 : 3; /* * [15:13] */ + unsigned int ipsurxNp2npFhl2Hlen : 5; /* * [20:16]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxNp2npFhl3Hlen : 5; /* * [28:24]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_HLEN_U; + +/* ** + * Union name : IPSURX_NP2NP_QIDX_PRI1 + * @brief NP2NP头QINDEX优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npQidxPri1 { + struct tagStIpsurxNp2npQidxPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxQidxV15Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值15对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxQidxV14Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值14对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxQidxV13Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值13对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxQidxV12Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值12对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxQidxV11Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值11对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxQidxV10Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值10对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxQidxV9Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值9对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV8Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值8对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ +#else + unsigned int ipsurxQidxV8Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值8对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV9Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值9对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxQidxV10Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值10对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxQidxV11Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值11对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxQidxV12Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值12对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxQidxV13Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值13对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxQidxV14Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值14对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxQidxV15Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值15对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_QIDX_PRI1_U; + +/* ** + * Union name : IPSURX_NP2NP_QIDX_PRI0 + * @brief NP2NP头QINDEX优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npQidxPri0 { + struct tagStIpsurxNp2npQidxPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxQidxV7Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值7对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxQidxV6Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值6对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxQidxV5Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值5对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxQidxV4Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值4对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxQidxV3Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值3对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxQidxV2Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值2对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxQidxV1Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值1对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV0Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值0对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ +#else + unsigned int ipsurxQidxV0Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值0对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV1Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值1对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxQidxV2Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值2对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxQidxV3Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值3对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxQidxV4Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值4对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxQidxV5Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值5对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxQidxV6Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值6对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxQidxV7Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值7对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_QIDX_PRI0_U; + +/* ** + * Union name : IPSURX_HG2HDR_CFG + * @brief HG2 header配置寄存器 + * Description: + */ +typedef union tagUnIpsurxHg2hdrCfg { + struct tagStIpsurxHg2hdrCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21]reserved. */ + unsigned int ipsurxHg2hdrEhv1Hlen : 5; /* * [20:16]EHV比特值为1时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [15:13] */ + unsigned int ipsurxHg2hdrEhv0Hlen : 5; /* * [12:8]EHV比特值为0时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxHg2hdrEhvLoc : 7; /* * [6:0]EHV比特的位置。建议不修改默认值。有效值范围:0x30 - 0x4F。 */ +#else + unsigned int ipsurxHg2hdrEhvLoc : 7; /* * [6:0]EHV比特的位置。建议不修改默认值。有效值范围:0x30 - 0x4F。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxHg2hdrEhv0Hlen : 5; /* * [12:8]EHV比特值为0时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [15:13] */ + unsigned int ipsurxHg2hdrEhv1Hlen : 5; /* * [20:16]EHV比特值为1时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved0 : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_HG2HDR_CFG_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID3 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid3 { + struct tagStIpsurxEvtagTpid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid3 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid3 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID3_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID2 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid2 { + struct tagStIpsurxEvtagTpid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid2 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid2 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID2_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID1 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid1 { + struct tagStIpsurxEvtagTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid1 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid1 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID1_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID0 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid0 { + struct tagStIpsurxEvtagTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid0 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid0 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID0_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID4 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid4 { + struct tagStIpsurxSvlanTpid4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid4 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid4 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID4_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID3 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid3 { + struct tagStIpsurxSvlanTpid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid3 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid3 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID3_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID2 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid2 { + struct tagStIpsurxSvlanTpid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid2 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid2 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID2_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID1 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid1 { + struct tagStIpsurxSvlanTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid1 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid1 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID1_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID0 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid0 { + struct tagStIpsurxSvlanTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid0 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid0 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID0_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID4 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid4 { + struct tagStIpsurxCvlanTpid4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid4 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid4 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID4_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID3 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid3 { + struct tagStIpsurxCvlanTpid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid3 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid3 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID3_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID2 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid2 { + struct tagStIpsurxCvlanTpid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid2 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid2 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID2_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID1 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid1 { + struct tagStIpsurxCvlanTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid1 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid1 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID1_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID0 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid0 { + struct tagStIpsurxCvlanTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid0 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid0 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID0_U; + +/* ** + * Union name : IPSURX_P8021_PRI + * @brief 802.1优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxP8021Pri { + struct tagStIpsurxP8021Pri { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxP8021V7Pri : 3; /* * [30:28]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为7的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxP8021V6Pri : 3; /* * [26:24]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为6的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxP8021V5Pri : 3; /* * [22:20]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为5的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxP8021V4Pri : 3; /* * [18:16]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为4的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxP8021V3Pri : 3; /* * [14:12]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为3的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxP8021V2Pri : 3; /* * [10:8]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为2的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxP8021V1Pri : 3; /* * [6:4]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为1的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxP8021V0Pri : 3; /* * [2:0]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为0的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxP8021V0Pri : 3; /* * [2:0]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为0的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxP8021V1Pri : 3; /* * [6:4]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为1的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxP8021V2Pri : 3; /* * [10:8]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为2的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxP8021V3Pri : 3; /* * [14:12]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为3的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxP8021V4Pri : 3; /* * [18:16]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为4的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxP8021V5Pri : 3; /* * [22:20]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为5的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxP8021V6Pri : 3; /* * [26:24]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为6的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxP8021V7Pri : 3; /* * [30:28]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为7的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_P8021_PRI_U; + +/* ** + * Union name : IPSURX_CNTAG_TPID1 + * @brief CN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCntagTpid1 { + struct tagStIpsurxCntagTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCntagTpid1 : 16; /* * [15:0]软件配置CN TAG TPID。 */ +#else + unsigned int ipsurxCntagTpid1 : 16; /* * [15:0]软件配置CN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CNTAG_TPID1_U; + +/* ** + * Union name : IPSURX_CNTAG_TPID0 + * @brief CN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCntagTpid0 { + struct tagStIpsurxCntagTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCntagTpid0 : 16; /* * [15:0]软件配置CN TAG TPID。 */ +#else + unsigned int ipsurxCntagTpid0 : 16; /* * [15:0]软件配置CN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CNTAG_TPID0_U; + +/* ** + * Union name : IPSURX_8023_MAX_LEN + * @brief 802.3最大长度配置寄存器 + * Description: + */ +typedef union tagUnIpsurx8023MaxLen { + struct tagStIpsurx8023MaxLen { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11] */ + unsigned int ipsurx8023MaxLen : 11; /* * [10:0]802.3封装的以太网帧，LENGTH域最大值。建议不修改默认值。 */ +#else + unsigned int ipsurx8023MaxLen : 11; /* * [10:0]802.3封装的以太网帧，LENGTH域最大值。建议不修改默认值。 */ + unsigned int reserved : 21; /* * [31:11] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_8023_MAX_LEN_U; + +/* ** + * Union name : IPSURX_8023_JUMBO_CFG + * @brief 802.3Jumbo帧配置寄存器 + * Description: + */ +typedef union tagUnIpsurx8023JumboCfg { + struct tagStIpsurx8023JumboCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17]reserved. */ + unsigned int ipsurx8023JumboChkEn : 1; /* * [16:16]1'b1：使能802.3 JUMBO帧检测；1'b0：不使能802.3 JUMBO帧检测。 + */ + unsigned int ipsurx8023JumboTpid : 16; /* * [15:0]802.3封装的JUMBO帧TPID。建议不修改默认值。 */ +#else + unsigned int ipsurx8023JumboTpid : 16; /* * [15:0]802.3封装的JUMBO帧TPID。建议不修改默认值。 */ + unsigned int ipsurx8023JumboChkEn : 1; /* * [16:16]1'b1：使能802.3 JUMBO帧检测；1'b0：不使能802.3 JUMBO帧检测。 + */ + unsigned int reserved : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_8023_JUMBO_CFG_U; + +/* ** + * Union name : IPSURX_L2_DMAC_CHK_EN + * @brief L2报文DMAC检测使能配置寄存器 + * Description: + */ +typedef union tagUnIpsurxL2DmacChkEn { + struct tagStIpsurxL2DmacChkEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int + ipsurxPauseDmacChkEn : 1; /* * + * [3:3]Pause帧DMAC检测使能：1'b1：PAUSE报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PAUSE报文识别不检测DMAC地址。 + */ + unsigned int ipsurxPfcDmacChkEn : 1; /* * + [2:2]PFC帧DMAC检测使能：1'b1：PFC报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PFC报文识别不检测DMAC地址。 + */ + unsigned int ipsurxLacpDmacChkEn : 1; /* * + [1:1]LACP帧DMAC检测使能：1'b1：LACP报文识别需要检测DMAC地址01-80-C2-00-00-02；1'b0：LACP报文识别不检测DMAC地址。 + */ + unsigned int + ipsurxLldpDmacChkEn : 1; /* * + * [0:0]LLDP/CDCP报文DMAC检测使能：1'b1：LLDP/CDCP报文识别需要检测DMAC地址，DMAC地址为01-80-C2-00-00-{00,03,0E}之一；1'b0：LLDP/CDCP报文识别不检测DMAC地址。 + */ +#else + unsigned int + ipsurxLldpDmacChkEn : 1; /* * + * [0:0]LLDP/CDCP报文DMAC检测使能：1'b1：LLDP/CDCP报文识别需要检测DMAC地址，DMAC地址为01-80-C2-00-00-{00,03,0E}之一；1'b0：LLDP/CDCP报文识别不检测DMAC地址。 + */ + unsigned int ipsurxLacpDmacChkEn : 1; /* * + [1:1]LACP帧DMAC检测使能：1'b1：LACP报文识别需要检测DMAC地址01-80-C2-00-00-02；1'b0：LACP报文识别不检测DMAC地址。 + */ + unsigned int ipsurxPfcDmacChkEn : 1; /* * + [2:2]PFC帧DMAC检测使能：1'b1：PFC报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PFC报文识别不检测DMAC地址。 + */ + unsigned int + ipsurxPauseDmacChkEn : 1; /* * + * [3:3]Pause帧DMAC检测使能：1'b1：PAUSE报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PAUSE报文识别不检测DMAC地址。 + */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_L2_DMAC_CHK_EN_U; + +/* ** + * Union name : IPSURX_FIP_TO_UP_EN + * @brief IPSURX FIP控制寄存器 + * Description: + */ +typedef union tagUnIpsurxFipToUpEn { + struct tagStIpsurxFipToUpEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxFipToUpEn : 1; /* * [0:0]1'b0：FIP报文转发到TILE；1'b1：FIP Protocol + Code不等于0x2的报文转发到UP。 */ +#else + unsigned int ipsurxFipToUpEn : 1; /* * [0:0]1'b0：FIP报文转发到TILE；1'b1：FIP Protocol + Code不等于0x2的报文转发到UP。 */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIP_TO_UP_EN_U; + +/* ** + * Union name : IPSURX_RTN_TS + * @brief 回传时戳报文寄存器 + * Description: + */ +typedef union tagUnIpsurxRtnTs { + struct tagStIpsurxRtnTs { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17]reserved. */ + unsigned int + ipsurxRtnTsEn : 1; /* * [16:16]1'b1：用户定义回传时戳报文类型有效。1'b0：用户定义回传时戳报文类型无效。 */ + unsigned int ipsurxRtnTs : 16; /* * + * [15:0]用户定义回传时戳报文类型。该寄存器的值必需与MAG的寄存器MAG_RXDP_RTS_TYPE的高16比特的值保持一致。其值要求大于0x600，并且不和知名的Ethernet + * TYPE类型值冲突。 + */ +#else + unsigned int ipsurxRtnTs : 16; /* * + * [15:0]用户定义回传时戳报文类型。该寄存器的值必需与MAG的寄存器MAG_RXDP_RTS_TYPE的高16比特的值保持一致。其值要求大于0x600，并且不和知名的Ethernet + * TYPE类型值冲突。 + */ + unsigned int + ipsurxRtnTsEn : 1; /* * [16:16]1'b1：用户定义回传时戳报文类型有效。1'b0：用户定义回传时戳报文类型无效。 */ + unsigned int reserved : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RTN_TS_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI7 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri7 { + struct tagStIpsurxIpv4DscpPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV63Pri : 3; /* * [30:28]IPv4 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV62Pri : 3; /* * [26:24]IPv4 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV61Pri : 3; /* * [22:20]IPv4 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV60Pri : 3; /* * [18:16]IPv4 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV59Pri : 3; /* * [14:12]IPv4 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV58Pri : 3; /* * [10:8]IPv4 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV57Pri : 3; /* * [6:4]IPv4 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV56Pri : 3; /* * [2:0]IPv4 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV56Pri : 3; /* * [2:0]IPv4 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV57Pri : 3; /* * [6:4]IPv4 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV58Pri : 3; /* * [10:8]IPv4 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV59Pri : 3; /* * [14:12]IPv4 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV60Pri : 3; /* * [18:16]IPv4 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV61Pri : 3; /* * [22:20]IPv4 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV62Pri : 3; /* * [26:24]IPv4 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV63Pri : 3; /* * [30:28]IPv4 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI7_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI6 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri6 { + struct tagStIpsurxIpv4DscpPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV55Pri : 3; /* * [30:28]IPv4 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV54Pri : 3; /* * [26:24]IPv4 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV53Pri : 3; /* * [22:20]IPv4 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV52Pri : 3; /* * [18:16]IPv4 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV51Pri : 3; /* * [14:12]IPv4 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV50Pri : 3; /* * [10:8]IPv4 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV49Pri : 3; /* * [6:4]IPv4 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV48Pri : 3; /* * [2:0]IPv4 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV48Pri : 3; /* * [2:0]IPv4 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV49Pri : 3; /* * [6:4]IPv4 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV50Pri : 3; /* * [10:8]IPv4 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV51Pri : 3; /* * [14:12]IPv4 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV52Pri : 3; /* * [18:16]IPv4 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV53Pri : 3; /* * [22:20]IPv4 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV54Pri : 3; /* * [26:24]IPv4 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV55Pri : 3; /* * [30:28]IPv4 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI6_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI5 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri5 { + struct tagStIpsurxIpv4DscpPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV47Pri : 3; /* * [30:28]IPv4 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV46Pri : 3; /* * [26:24]IPv4 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV45Pri : 3; /* * [22:20]IPv4 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV44Pri : 3; /* * [18:16]IPv4 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV43Pri : 3; /* * [14:12]IPv4 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV42Pri : 3; /* * [10:8]IPv4 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV41Pri : 3; /* * [6:4]IPv4 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV40Pri : 3; /* * [2:0]IPv4 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV40Pri : 3; /* * [2:0]IPv4 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV41Pri : 3; /* * [6:4]IPv4 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV42Pri : 3; /* * [10:8]IPv4 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV43Pri : 3; /* * [14:12]IPv4 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV44Pri : 3; /* * [18:16]IPv4 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV45Pri : 3; /* * [22:20]IPv4 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV46Pri : 3; /* * [26:24]IPv4 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV47Pri : 3; /* * [30:28]IPv4 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI5_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI4 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri4 { + struct tagStIpsurxIpv4DscpPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV39Pri : 3; /* * [30:28]IPv4 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV38Pri : 3; /* * [26:24]IPv4 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV37Pri : 3; /* * [22:20]IPv4 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV36Pri : 3; /* * [18:16]IPv4 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV35Pri : 3; /* * [14:12]IPv4 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV34Pri : 3; /* * [10:8]IPv4 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV33Pri : 3; /* * [6:4]IPv4 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV32Pri : 3; /* * [2:0]IPv4 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV32Pri : 3; /* * [2:0]IPv4 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV33Pri : 3; /* * [6:4]IPv4 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV34Pri : 3; /* * [10:8]IPv4 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV35Pri : 3; /* * [14:12]IPv4 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV36Pri : 3; /* * [18:16]IPv4 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV37Pri : 3; /* * [22:20]IPv4 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV38Pri : 3; /* * [26:24]IPv4 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV39Pri : 3; /* * [30:28]IPv4 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI4_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI3 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri3 { + struct tagStIpsurxIpv4DscpPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV31Pri : 3; /* * [30:28]IPv4 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV30Pri : 3; /* * [26:24]IPv4 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV29Pri : 3; /* * [22:20]IPv4 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV28Pri : 3; /* * [18:16]IPv4 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV27Pri : 3; /* * [14:12]IPv4 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV26Pri : 3; /* * [10:8]IPv4 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV25Pri : 3; /* * [6:4]IPv4 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV24Pri : 3; /* * [2:0]IPv4 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV24Pri : 3; /* * [2:0]IPv4 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV25Pri : 3; /* * [6:4]IPv4 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV26Pri : 3; /* * [10:8]IPv4 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV27Pri : 3; /* * [14:12]IPv4 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV28Pri : 3; /* * [18:16]IPv4 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV29Pri : 3; /* * [22:20]IPv4 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV30Pri : 3; /* * [26:24]IPv4 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV31Pri : 3; /* * [30:28]IPv4 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI3_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI2 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri2 { + struct tagStIpsurxIpv4DscpPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV23Pri : 3; /* * [30:28]IPv4 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV22Pri : 3; /* * [26:24]IPv4 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV21Pri : 3; /* * [22:20]IPv4 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV20Pri : 3; /* * [18:16]IPv4 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV19Pri : 3; /* * [14:12]IPv4 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV18Pri : 3; /* * [10:8]IPv4 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV17Pri : 3; /* * [6:4]IPv4 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV16Pri : 3; /* * [2:0]IPv4 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV16Pri : 3; /* * [2:0]IPv4 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV17Pri : 3; /* * [6:4]IPv4 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV18Pri : 3; /* * [10:8]IPv4 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV19Pri : 3; /* * [14:12]IPv4 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV20Pri : 3; /* * [18:16]IPv4 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV21Pri : 3; /* * [22:20]IPv4 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV22Pri : 3; /* * [26:24]IPv4 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV23Pri : 3; /* * [30:28]IPv4 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI2_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI1 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri1 { + struct tagStIpsurxIpv4DscpPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV15Pri : 3; /* * [30:28]IPv4 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV14Pri : 3; /* * [26:24]IPv4 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV13Pri : 3; /* * [22:20]IPv4 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV12Pri : 3; /* * [18:16]IPv4 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV11Pri : 3; /* * [14:12]IPv4 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV10Pri : 3; /* * [10:8]IPv4 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv4DscpV9Pri : 3; /* * [6:4]IPv4 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV8Pri : 3; /* * [2:0]IPv4 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv4DscpV8Pri : 3; /* * [2:0]IPv4 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV9Pri : 3; /* * [6:4]IPv4 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV10Pri : 3; /* * [10:8]IPv4 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV11Pri : 3; /* * [14:12]IPv4 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV12Pri : 3; /* * [18:16]IPv4 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV13Pri : 3; /* * [22:20]IPv4 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV14Pri : 3; /* * [26:24]IPv4 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV15Pri : 3; /* * [30:28]IPv4 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI1_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI0 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri0 { + struct tagStIpsurxIpv4DscpPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxIpv4DscpV7Pri : 3; /* * [30:28]IPv4 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv4DscpV6Pri : 3; /* * [26:24]IPv4 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv4DscpV5Pri : 3; /* * [22:20]IPv4 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv4DscpV4Pri : 3; /* * [18:16]IPv4 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv4DscpV3Pri : 3; /* * [14:12]IPv4 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv4DscpV2Pri : 3; /* * [10:8]IPv4 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv4DscpV1Pri : 3; /* * [6:4]IPv4 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV0Pri : 3; /* * [2:0]IPv4 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv4DscpV0Pri : 3; /* * [2:0]IPv4 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV1Pri : 3; /* * [6:4]IPv4 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv4DscpV2Pri : 3; /* * [10:8]IPv4 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv4DscpV3Pri : 3; /* * [14:12]IPv4 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv4DscpV4Pri : 3; /* * [18:16]IPv4 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv4DscpV5Pri : 3; /* * [22:20]IPv4 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv4DscpV6Pri : 3; /* * [26:24]IPv4 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv4DscpV7Pri : 3; /* * [30:28]IPv4 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI0_U; + +/* ** + * Union name : IPSURX_IGMPV4_DIP_CHK_EN + * @brief IGMPv4 DIP检测控制寄存器 + * Description: + */ +typedef union tagUnIpsurxIgmpv4DipChkEn { + struct tagStIpsurxIgmpv4DipChkEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxIgmpv4DipChkEn : 1; /* * + * [0:0]1'b0：不检测IGMPv4报文的DIP范围；1'b1：检测IGMPv4报文的DIP范围。 + */ +#else + unsigned int ipsurxIgmpv4DipChkEn : 1; /* * + * [0:0]1'b0：不检测IGMPv4报文的DIP范围；1'b1：检测IGMPv4报文的DIP范围。 + */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IGMPV4_DIP_CHK_EN_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI7 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri7 { + struct tagStIpsurxIpv6DscpPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV63Pri : 3; /* * [30:28]IPv6 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV62Pri : 3; /* * [26:24]IPv6 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV61Pri : 3; /* * [22:20]IPv6 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV60Pri : 3; /* * [18:16]IPv6 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV59Pri : 3; /* * [14:12]IPv6 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV58Pri : 3; /* * [10:8]IPv6 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV57Pri : 3; /* * [6:4]IPv6 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV56Pri : 3; /* * [2:0]IPv6 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV56Pri : 3; /* * [2:0]IPv6 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV57Pri : 3; /* * [6:4]IPv6 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV58Pri : 3; /* * [10:8]IPv6 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV59Pri : 3; /* * [14:12]IPv6 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV60Pri : 3; /* * [18:16]IPv6 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV61Pri : 3; /* * [22:20]IPv6 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV62Pri : 3; /* * [26:24]IPv6 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV63Pri : 3; /* * [30:28]IPv6 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI7_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI6 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri6 { + struct tagStIpsurxIpv6DscpPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV55Pri : 3; /* * [30:28]IPv6 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV54Pri : 3; /* * [26:24]IPv6 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV53Pri : 3; /* * [22:20]IPv6 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV52Pri : 3; /* * [18:16]IPv6 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV51Pri : 3; /* * [14:12]IPv6 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV50Pri : 3; /* * [10:8]IPv6 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV49Pri : 3; /* * [6:4]IPv6 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV48Pri : 3; /* * [2:0]IPv6 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV48Pri : 3; /* * [2:0]IPv6 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV49Pri : 3; /* * [6:4]IPv6 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV50Pri : 3; /* * [10:8]IPv6 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV51Pri : 3; /* * [14:12]IPv6 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV52Pri : 3; /* * [18:16]IPv6 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV53Pri : 3; /* * [22:20]IPv6 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV54Pri : 3; /* * [26:24]IPv6 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV55Pri : 3; /* * [30:28]IPv6 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI6_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI5 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri5 { + struct tagStIpsurxIpv6DscpPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV47Pri : 3; /* * [30:28]IPv6 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV46Pri : 3; /* * [26:24]IPv6 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV45Pri : 3; /* * [22:20]IPv6 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV44Pri : 3; /* * [18:16]IPv6 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV43Pri : 3; /* * [14:12]IPv6 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV42Pri : 3; /* * [10:8]IPv6 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV41Pri : 3; /* * [6:4]IPv6 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV40Pri : 3; /* * [2:0]IPv6 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV40Pri : 3; /* * [2:0]IPv6 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV41Pri : 3; /* * [6:4]IPv6 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV42Pri : 3; /* * [10:8]IPv6 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV43Pri : 3; /* * [14:12]IPv6 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV44Pri : 3; /* * [18:16]IPv6 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV45Pri : 3; /* * [22:20]IPv6 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV46Pri : 3; /* * [26:24]IPv6 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV47Pri : 3; /* * [30:28]IPv6 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI5_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI4 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri4 { + struct tagStIpsurxIpv6DscpPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV39Pri : 3; /* * [30:28]IPv6 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV38Pri : 3; /* * [26:24]IPv6 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV37Pri : 3; /* * [22:20]IPv6 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV36Pri : 3; /* * [18:16]IPv6 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV35Pri : 3; /* * [14:12]IPv6 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV34Pri : 3; /* * [10:8]IPv6 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV33Pri : 3; /* * [6:4]IPv6 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV32Pri : 3; /* * [2:0]IPv6 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV32Pri : 3; /* * [2:0]IPv6 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV33Pri : 3; /* * [6:4]IPv6 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV34Pri : 3; /* * [10:8]IPv6 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV35Pri : 3; /* * [14:12]IPv6 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV36Pri : 3; /* * [18:16]IPv6 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV37Pri : 3; /* * [22:20]IPv6 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV38Pri : 3; /* * [26:24]IPv6 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV39Pri : 3; /* * [30:28]IPv6 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI4_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI3 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri3 { + struct tagStIpsurxIpv6DscpPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV31Pri : 3; /* * [30:28]IPv6 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV30Pri : 3; /* * [26:24]IPv6 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV29Pri : 3; /* * [22:20]IPv6 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV28Pri : 3; /* * [18:16]IPv6 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV27Pri : 3; /* * [14:12]IPv6 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV26Pri : 3; /* * [10:8]IPv6 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV25Pri : 3; /* * [6:4]IPv6 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV24Pri : 3; /* * [2:0]IPv6 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV24Pri : 3; /* * [2:0]IPv6 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV25Pri : 3; /* * [6:4]IPv6 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV26Pri : 3; /* * [10:8]IPv6 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV27Pri : 3; /* * [14:12]IPv6 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV28Pri : 3; /* * [18:16]IPv6 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV29Pri : 3; /* * [22:20]IPv6 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV30Pri : 3; /* * [26:24]IPv6 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV31Pri : 3; /* * [30:28]IPv6 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI3_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI2 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri2 { + struct tagStIpsurxIpv6DscpPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV23Pri : 3; /* * [30:28]IPv6 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV22Pri : 3; /* * [26:24]IPv6 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV21Pri : 3; /* * [22:20]IPv6 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV20Pri : 3; /* * [18:16]IPv6 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV19Pri : 3; /* * [14:12]IPv6 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV18Pri : 3; /* * [10:8]IPv6 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV17Pri : 3; /* * [6:4]IPv6 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV16Pri : 3; /* * [2:0]IPv6 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV16Pri : 3; /* * [2:0]IPv6 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV17Pri : 3; /* * [6:4]IPv6 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV18Pri : 3; /* * [10:8]IPv6 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV19Pri : 3; /* * [14:12]IPv6 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV20Pri : 3; /* * [18:16]IPv6 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV21Pri : 3; /* * [22:20]IPv6 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV22Pri : 3; /* * [26:24]IPv6 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV23Pri : 3; /* * [30:28]IPv6 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI2_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI1 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri1 { + struct tagStIpsurxIpv6DscpPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV15Pri : 3; /* * [30:28]IPv6 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV14Pri : 3; /* * [26:24]IPv6 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV13Pri : 3; /* * [22:20]IPv6 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV12Pri : 3; /* * [18:16]IPv6 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV11Pri : 3; /* * [14:12]IPv6 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV10Pri : 3; /* * [10:8]IPv6 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv6DscpV9Pri : 3; /* * [6:4]IPv6 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV8Pri : 3; /* * [2:0]IPv6 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv6DscpV8Pri : 3; /* * [2:0]IPv6 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV9Pri : 3; /* * [6:4]IPv6 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV10Pri : 3; /* * [10:8]IPv6 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV11Pri : 3; /* * [14:12]IPv6 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV12Pri : 3; /* * [18:16]IPv6 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV13Pri : 3; /* * [22:20]IPv6 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV14Pri : 3; /* * [26:24]IPv6 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV15Pri : 3; /* * [30:28]IPv6 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI1_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI0 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri0 { + struct tagStIpsurxIpv6DscpPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxIpv6DscpV7Pri : 3; /* * [30:28]IPv6 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv6DscpV6Pri : 3; /* * [26:24]IPv6 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv6DscpV5Pri : 3; /* * [22:20]IPv6 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv6DscpV4Pri : 3; /* * [18:16]IPv6 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv6DscpV3Pri : 3; /* * [14:12]IPv6 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv6DscpV2Pri : 3; /* * [10:8]IPv6 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv6DscpV1Pri : 3; /* * [6:4]IPv6 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV0Pri : 3; /* * [2:0]IPv6 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv6DscpV0Pri : 3; /* * [2:0]IPv6 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV1Pri : 3; /* * [6:4]IPv6 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv6DscpV2Pri : 3; /* * [10:8]IPv6 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv6DscpV3Pri : 3; /* * [14:12]IPv6 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv6DscpV4Pri : 3; /* * [18:16]IPv6 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv6DscpV5Pri : 3; /* * [22:20]IPv6 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv6DscpV6Pri : 3; /* * [26:24]IPv6 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv6DscpV7Pri : 3; /* * [30:28]IPv6 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI0_U; + +/* ** + * Union name : IPSURX_IPV6_SPEC_MC + * @brief IPv6指定多播寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6SpecMc { + struct tagStIpsurxIpv6SpecMc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6SpecMcastMask : 16; /* * [31:16]IPv6指定多播掩码。 */ + unsigned int ipsurxIpv6SpecMcast : 16; /* * [15:0]IPv6指定多播。 */ +#else + unsigned int ipsurxIpv6SpecMcast : 16; /* * [15:0]IPv6指定多播。 */ + unsigned int ipsurxIpv6SpecMcastMask : 16; /* * [31:16]IPv6指定多播掩码。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_SPEC_MC_U; + +/* ** + * Union name : IPSURX_VXLAN_DPORT + * @brief VXLAN目的UDP PORT号 + * Description: + */ +typedef union tagUnIpsurxVxlanDport { + struct tagStIpsurxVxlanDport { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxVxlanDport : 16; /* * [15:0]VXLAN目的UDP端口号 */ +#else + unsigned int ipsurxVxlanDport : 16; /* * [15:0]VXLAN目的UDP端口号 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_VXLAN_DPORT_U; + +/* ** + * Union name : IPSURX_ROCEV2_DPORT + * @brief RoCEV2目的UDP PORT号 + * Description: + */ +typedef union tagUnIpsurxRocev2Dport { + struct tagStIpsurxRocev2Dport { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxRocev2Dport : 16; /* * [15:0]RoCEV2目的UDP端口号 */ +#else + unsigned int ipsurxRocev2Dport : 16; /* * [15:0]RoCEV2目的UDP端口号 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_DPORT_U; + +/* ** + * Union name : IPSURX_TPT_CTRL + * @brief TCP PORT表控制寄存器 + * Description: + */ +typedef union tagUnIpsurxTptCtrl { + struct tagStIpsurxTptCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]保留 */ + unsigned int ipsurxTcpPortLkEn : 1; /* * [6:6]TCP DPORT表查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxTcpSampIterval : 6; /* * [5:0]控制TCP报文采样间隔，实际采样间隔为该值乘以64。可配值范围：6'd1 + - 6'd63。 */ +#else + unsigned int ipsurxTcpSampIterval : 6; /* * [5:0]控制TCP报文采样间隔，实际采样间隔为该值乘以64。可配值范围：6'd1 + - 6'd63。 */ + unsigned int ipsurxTcpPortLkEn : 1; /* * [6:6]TCP DPORT表查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved : 25; /* * [31:7]保留 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_CTRL_U; + +/* ** + * Union name : IPSURX_TPT_DROP_FOR_BUSY_CNT + * @brief TPT表项忙，丢弃反标TCP端口号计数器 + * Description: + */ +typedef union tagUnIpsurxTptDropForBusyCnt { + struct tagStIpsurxTptDropForBusyCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTptDropForBusyCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTptDropForBusyCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_DROP_FOR_BUSY_CNT_U; + +/* ** + * Union name : IPSURX_DMAC_ZERO_CNT + * @brief 目的MAC为0错误报文计数器 + * Description: + */ +typedef union tagUnIpsurxDmacZeroCnt { + struct tagStIpsurxDmacZeroCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxDmacZeroCnt : 32; /* * [31:0]目的MAC为0的报文数量。 */ +#else + unsigned int ipsurxDmacZeroCnt : 32; /* * [31:0]目的MAC为0的报文数量。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_DMAC_ZERO_CNT_U; + +/* ** + * Union name : IPSURX_SMAC_ILGL_CNT + * @brief 源MAC错误报文计数器 + * Description: + */ +typedef union tagUnIpsurxSmacIlglCnt { + struct tagStIpsurxSmacIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSmacIlglCnt : 32; /* * [31:0]源MAC错误的报文数量。 */ +#else + unsigned int ipsurxSmacIlglCnt : 32; /* * [31:0]源MAC错误的报文数量。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SMAC_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_DA_SA_EQUAL_CNT + * @brief 源目的MAC相等报文计数器 + * Description: + */ +typedef union tagUnIpsurxDaSaEqualCnt { + struct tagStIpsurxDaSaEqualCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxDaSaEqualCnt : 32; /* * [31:0]源目的MAC相等报文计数器。 */ +#else + unsigned int ipsurxDaSaEqualCnt : 32; /* * [31:0]源目的MAC相等报文计数器。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_DA_SA_EQUAL_CNT_U; + +/* ** + * Union name : IPSURX_ETH_LEN_ILGL_CNT + * @brief ETH_LEN_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxEthLenIlglCnt { + struct tagStIpsurxEthLenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxEthLenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxEthLenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ETH_LEN_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ARP_POSI_ILGL_CNT + * @brief ARP_POSI_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxArpPosiIlglCnt { + struct tagStIpsurxArpPosiIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxArpPosiIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxArpPosiIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ARP_POSI_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI7 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri7 { + struct tagStIpsurxFcCsctlPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV63Pri : 3; /* * [30:28]FC + CSCTL字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV62Pri : 3; /* * [26:24]FC + CSCTL字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV61Pri : 3; /* * [22:20]FC + CSCTL字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV60Pri : 3; /* * [18:16]FC + CSCTL字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV59Pri : 3; /* * [14:12]FC + CSCTL字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV58Pri : 3; /* * [10:8]FC + CSCTL字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV57Pri : 3; /* * [6:4]FC + CSCTL字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV56Pri : 3; /* * [2:0]FC + CSCTL字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV56Pri : 3; /* * [2:0]FC + CSCTL字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV57Pri : 3; /* * [6:4]FC + CSCTL字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV58Pri : 3; /* * [10:8]FC + CSCTL字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV59Pri : 3; /* * [14:12]FC + CSCTL字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV60Pri : 3; /* * [18:16]FC + CSCTL字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV61Pri : 3; /* * [22:20]FC + CSCTL字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV62Pri : 3; /* * [26:24]FC + CSCTL字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV63Pri : 3; /* * [30:28]FC + CSCTL字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI7_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI6 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri6 { + struct tagStIpsurxFcCsctlPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV55Pri : 3; /* * [30:28]FC + CSCTL字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV54Pri : 3; /* * [26:24]FC + CSCTL字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV53Pri : 3; /* * [22:20]FC + CSCTL字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV52Pri : 3; /* * [18:16]FC + CSCTL字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV51Pri : 3; /* * [14:12]FC + CSCTL字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV50Pri : 3; /* * [10:8]FC + CSCTL字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV49Pri : 3; /* * [6:4]FC + CSCTL字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV48Pri : 3; /* * [2:0]FC + CSCTL字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV48Pri : 3; /* * [2:0]FC + CSCTL字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV49Pri : 3; /* * [6:4]FC + CSCTL字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV50Pri : 3; /* * [10:8]FC + CSCTL字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV51Pri : 3; /* * [14:12]FC + CSCTL字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV52Pri : 3; /* * [18:16]FC + CSCTL字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV53Pri : 3; /* * [22:20]FC + CSCTL字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV54Pri : 3; /* * [26:24]FC + CSCTL字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV55Pri : 3; /* * [30:28]FC + CSCTL字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI6_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI5 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri5 { + struct tagStIpsurxFcCsctlPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV47Pri : 3; /* * [30:28]FC + CSCTL字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV46Pri : 3; /* * [26:24]FC + CSCTL字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV45Pri : 3; /* * [22:20]FC + CSCTL字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV44Pri : 3; /* * [18:16]FC + CSCTL字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV43Pri : 3; /* * [14:12]FC + CSCTL字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV42Pri : 3; /* * [10:8]FC + CSCTL字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV41Pri : 3; /* * [6:4]FC + CSCTL字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV40Pri : 3; /* * [2:0]FC + CSCTL字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV40Pri : 3; /* * [2:0]FC + CSCTL字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV41Pri : 3; /* * [6:4]FC + CSCTL字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV42Pri : 3; /* * [10:8]FC + CSCTL字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV43Pri : 3; /* * [14:12]FC + CSCTL字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV44Pri : 3; /* * [18:16]FC + CSCTL字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV45Pri : 3; /* * [22:20]FC + CSCTL字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV46Pri : 3; /* * [26:24]FC + CSCTL字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV47Pri : 3; /* * [30:28]FC + CSCTL字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI5_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI4 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri4 { + struct tagStIpsurxFcCsctlPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV39Pri : 3; /* * [30:28]FC + CSCTL字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV38Pri : 3; /* * [26:24]FC + CSCTL字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV37Pri : 3; /* * [22:20]FC + CSCTL字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV36Pri : 3; /* * [18:16]FC + CSCTL字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV35Pri : 3; /* * [14:12]FC + CSCTL字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV34Pri : 3; /* * [10:8]FC + CSCTL字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV33Pri : 3; /* * [6:4]FC + CSCTL字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV32Pri : 3; /* * [2:0]FC + CSCTL字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV32Pri : 3; /* * [2:0]FC + CSCTL字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV33Pri : 3; /* * [6:4]FC + CSCTL字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV34Pri : 3; /* * [10:8]FC + CSCTL字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV35Pri : 3; /* * [14:12]FC + CSCTL字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV36Pri : 3; /* * [18:16]FC + CSCTL字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV37Pri : 3; /* * [22:20]FC + CSCTL字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV38Pri : 3; /* * [26:24]FC + CSCTL字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV39Pri : 3; /* * [30:28]FC + CSCTL字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI4_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI3 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri3 { + struct tagStIpsurxFcCsctlPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV31Pri : 3; /* * [30:28]FC + CSCTL字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV30Pri : 3; /* * [26:24]FC + CSCTL字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV29Pri : 3; /* * [22:20]FC + CSCTL字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV28Pri : 3; /* * [18:16]FC + CSCTL字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV27Pri : 3; /* * [14:12]FC + CSCTL字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV26Pri : 3; /* * [10:8]FC + CSCTL字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV25Pri : 3; /* * [6:4]FC + CSCTL字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV24Pri : 3; /* * [2:0]FC + CSCTL字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV24Pri : 3; /* * [2:0]FC + CSCTL字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV25Pri : 3; /* * [6:4]FC + CSCTL字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV26Pri : 3; /* * [10:8]FC + CSCTL字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV27Pri : 3; /* * [14:12]FC + CSCTL字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV28Pri : 3; /* * [18:16]FC + CSCTL字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV29Pri : 3; /* * [22:20]FC + CSCTL字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV30Pri : 3; /* * [26:24]FC + CSCTL字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV31Pri : 3; /* * [30:28]FC + CSCTL字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI3_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI2 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri2 { + struct tagStIpsurxFcCsctlPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV23Pri : 3; /* * [30:28]FC + CSCTL字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV22Pri : 3; /* * [26:24]FC + CSCTL字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV21Pri : 3; /* * [22:20]FC + CSCTL字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV20Pri : 3; /* * [18:16]FC + CSCTL字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV19Pri : 3; /* * [14:12]FC + CSCTL字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV18Pri : 3; /* * [10:8]FC + CSCTL字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV17Pri : 3; /* * [6:4]FC + CSCTL字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV16Pri : 3; /* * [2:0]FC + CSCTL字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV16Pri : 3; /* * [2:0]FC + CSCTL字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV17Pri : 3; /* * [6:4]FC + CSCTL字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV18Pri : 3; /* * [10:8]FC + CSCTL字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV19Pri : 3; /* * [14:12]FC + CSCTL字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV20Pri : 3; /* * [18:16]FC + CSCTL字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV21Pri : 3; /* * [22:20]FC + CSCTL字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV22Pri : 3; /* * [26:24]FC + CSCTL字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV23Pri : 3; /* * [30:28]FC + CSCTL字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI2_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI1 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri1 { + struct tagStIpsurxFcCsctlPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV15Pri : 3; /* * [30:28]FC + CSCTL字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV14Pri : 3; /* * [26:24]FC + CSCTL字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV13Pri : 3; /* * [22:20]FC + CSCTL字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV12Pri : 3; /* * [18:16]FC + CSCTL字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV11Pri : 3; /* * [14:12]FC + CSCTL字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV10Pri : 3; /* * [10:8]FC + CSCTL字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxFcCsctlV9Pri : 3; /* * [6:4]FC + CSCTL字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV8Pri : 3; /* * [2:0]FC + CSCTL字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxFcCsctlV8Pri : 3; /* * [2:0]FC + CSCTL字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV9Pri : 3; /* * [6:4]FC + CSCTL字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV10Pri : 3; /* * [10:8]FC + CSCTL字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV11Pri : 3; /* * [14:12]FC + CSCTL字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV12Pri : 3; /* * [18:16]FC + CSCTL字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV13Pri : 3; /* * [22:20]FC + CSCTL字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV14Pri : 3; /* * [26:24]FC + CSCTL字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV15Pri : 3; /* * [30:28]FC + CSCTL字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI1_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI0 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri0 { + struct tagStIpsurxFcCsctlPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxFcCsctlV7Pri : 3; /* * [30:28]FC + CSCTL字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxFcCsctlV6Pri : 3; /* * [26:24]FC + CSCTL字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxFcCsctlV5Pri : 3; /* * [22:20]FC + CSCTL字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxFcCsctlV4Pri : 3; /* * [18:16]FC + CSCTL字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxFcCsctlV3Pri : 3; /* * [14:12]FC + CSCTL字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxFcCsctlV2Pri : 3; /* * [10:8]FC + CSCTL字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxFcCsctlV1Pri : 3; /* * [6:4]FC + CSCTL字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV0Pri : 3; /* * [2:0]FC + CSCTL字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxFcCsctlV0Pri : 3; /* * [2:0]FC + CSCTL字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV1Pri : 3; /* * [6:4]FC + CSCTL字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxFcCsctlV2Pri : 3; /* * [10:8]FC + CSCTL字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxFcCsctlV3Pri : 3; /* * [14:12]FC + CSCTL字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxFcCsctlV4Pri : 3; /* * [18:16]FC + CSCTL字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxFcCsctlV5Pri : 3; /* * [22:20]FC + CSCTL字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxFcCsctlV6Pri : 3; /* * [26:24]FC + CSCTL字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxFcCsctlV7Pri : 3; /* * [30:28]FC + CSCTL字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI0_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI15 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri15 { + struct tagStIpsurxFcPriorityPri15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV127Pri : 3; /* * [30:28]FC + PRIORITY字段值127优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV126Pri : 3; /* * [26:24]FC + PRIORITY字段值126优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV125Pri : 3; /* * [22:20]FC + PRIORITY字段值125优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV124Pri : 3; /* * [18:16]FC + PRIORITY字段值124优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV123Pri : 3; /* * [14:12]FC + PRIORITY字段值123优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV122Pri : 3; /* * [10:8]FC + PRIORITY字段值122优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV121Pri : 3; /* * [6:4]FC + PRIORITY字段值121优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV120Pri : 3; /* * [2:0]FC + PRIORITY字段值120优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV120Pri : 3; /* * [2:0]FC + PRIORITY字段值120优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV121Pri : 3; /* * [6:4]FC + PRIORITY字段值121优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV122Pri : 3; /* * [10:8]FC + PRIORITY字段值122优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV123Pri : 3; /* * [14:12]FC + PRIORITY字段值123优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV124Pri : 3; /* * [18:16]FC + PRIORITY字段值124优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV125Pri : 3; /* * [22:20]FC + PRIORITY字段值125优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV126Pri : 3; /* * [26:24]FC + PRIORITY字段值126优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV127Pri : 3; /* * [30:28]FC + PRIORITY字段值127优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI15_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI14 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri14 { + struct tagStIpsurxFcPriorityPri14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV119Pri : 3; /* * [30:28]FC + PRIORITY字段值119优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV118Pri : 3; /* * [26:24]FC + PRIORITY字段值118优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV117Pri : 3; /* * [22:20]FC + PRIORITY字段值117优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV116Pri : 3; /* * [18:16]FC + PRIORITY字段值116优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV115Pri : 3; /* * [14:12]FC + PRIORITY字段值115优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV114Pri : 3; /* * [10:8]FC + PRIORITY字段值114优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV113Pri : 3; /* * [6:4]FC + PRIORITY字段值113优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV112Pri : 3; /* * [2:0]FC + PRIORITY字段值112优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV112Pri : 3; /* * [2:0]FC + PRIORITY字段值112优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV113Pri : 3; /* * [6:4]FC + PRIORITY字段值113优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV114Pri : 3; /* * [10:8]FC + PRIORITY字段值114优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV115Pri : 3; /* * [14:12]FC + PRIORITY字段值115优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV116Pri : 3; /* * [18:16]FC + PRIORITY字段值116优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV117Pri : 3; /* * [22:20]FC + PRIORITY字段值117优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV118Pri : 3; /* * [26:24]FC + PRIORITY字段值118优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV119Pri : 3; /* * [30:28]FC + PRIORITY字段值119优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI14_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI13 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri13 { + struct tagStIpsurxFcPriorityPri13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV111Pri : 3; /* * [30:28]FC + PRIORITY字段值111优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV110Pri : 3; /* * [26:24]FC + PRIORITY字段值110优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV109Pri : 3; /* * [22:20]FC + PRIORITY字段值109优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV108Pri : 3; /* * [18:16]FC + PRIORITY字段值108优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV107Pri : 3; /* * [14:12]FC + PRIORITY字段值107优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV106Pri : 3; /* * [10:8]FC + PRIORITY字段值106优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV105Pri : 3; /* * [6:4]FC + PRIORITY字段值105优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV104Pri : 3; /* * [2:0]FC + PRIORITY字段值104优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV104Pri : 3; /* * [2:0]FC + PRIORITY字段值104优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV105Pri : 3; /* * [6:4]FC + PRIORITY字段值105优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV106Pri : 3; /* * [10:8]FC + PRIORITY字段值106优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV107Pri : 3; /* * [14:12]FC + PRIORITY字段值107优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV108Pri : 3; /* * [18:16]FC + PRIORITY字段值108优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV109Pri : 3; /* * [22:20]FC + PRIORITY字段值109优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV110Pri : 3; /* * [26:24]FC + PRIORITY字段值110优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV111Pri : 3; /* * [30:28]FC + PRIORITY字段值111优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI13_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI12 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri12 { + struct tagStIpsurxFcPriorityPri12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV103Pri : 3; /* * [30:28]FC + PRIORITY字段值103优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV102Pri : 3; /* * [26:24]FC + PRIORITY字段值102优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV101Pri : 3; /* * [22:20]FC + PRIORITY字段值101优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV100Pri : 3; /* * [18:16]FC + PRIORITY字段值100优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV99Pri : 3; /* * [14:12]FC + PRIORITY字段值99优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV98Pri : 3; /* * [10:8]FC + PRIORITY字段值98优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV97Pri : 3; /* * [6:4]FC + PRIORITY字段值97优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV96Pri : 3; /* * [2:0]FC + PRIORITY字段值96优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV96Pri : 3; /* * [2:0]FC + PRIORITY字段值96优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV97Pri : 3; /* * [6:4]FC + PRIORITY字段值97优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV98Pri : 3; /* * [10:8]FC + PRIORITY字段值98优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV99Pri : 3; /* * [14:12]FC + PRIORITY字段值99优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV100Pri : 3; /* * [18:16]FC + PRIORITY字段值100优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV101Pri : 3; /* * [22:20]FC + PRIORITY字段值101优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV102Pri : 3; /* * [26:24]FC + PRIORITY字段值102优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV103Pri : 3; /* * [30:28]FC + PRIORITY字段值103优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI12_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI11 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri11 { + struct tagStIpsurxFcPriorityPri11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV95Pri : 3; /* * [30:28]FC + PRIORITY字段值95优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV94Pri : 3; /* * [26:24]FC + PRIORITY字段值94优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV93Pri : 3; /* * [22:20]FC + PRIORITY字段值93优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV92Pri : 3; /* * [18:16]FC + PRIORITY字段值92优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV91Pri : 3; /* * [14:12]FC + PRIORITY字段值91优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV90Pri : 3; /* * [10:8]FC + PRIORITY字段值90优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV89Pri : 3; /* * [6:4]FC + PRIORITY字段值89优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV88Pri : 3; /* * [2:0]FC + PRIORITY字段值88优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV88Pri : 3; /* * [2:0]FC + PRIORITY字段值88优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV89Pri : 3; /* * [6:4]FC + PRIORITY字段值89优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV90Pri : 3; /* * [10:8]FC + PRIORITY字段值90优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV91Pri : 3; /* * [14:12]FC + PRIORITY字段值91优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV92Pri : 3; /* * [18:16]FC + PRIORITY字段值92优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV93Pri : 3; /* * [22:20]FC + PRIORITY字段值93优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV94Pri : 3; /* * [26:24]FC + PRIORITY字段值94优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV95Pri : 3; /* * [30:28]FC + PRIORITY字段值95优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI11_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI10 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri10 { + struct tagStIpsurxFcPriorityPri10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV87Pri : 3; /* * [30:28]FC + PRIORITY字段值87优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV86Pri : 3; /* * [26:24]FC + PRIORITY字段值86优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV85Pri : 3; /* * [22:20]FC + PRIORITY字段值85优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV84Pri : 3; /* * [18:16]FC + PRIORITY字段值84优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV83Pri : 3; /* * [14:12]FC + PRIORITY字段值83优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV82Pri : 3; /* * [10:8]FC + PRIORITY字段值82优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV81Pri : 3; /* * [6:4]FC + PRIORITY字段值81优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV80Pri : 3; /* * [2:0]FC + PRIORITY字段值80优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV80Pri : 3; /* * [2:0]FC + PRIORITY字段值80优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV81Pri : 3; /* * [6:4]FC + PRIORITY字段值81优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV82Pri : 3; /* * [10:8]FC + PRIORITY字段值82优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV83Pri : 3; /* * [14:12]FC + PRIORITY字段值83优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV84Pri : 3; /* * [18:16]FC + PRIORITY字段值84优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV85Pri : 3; /* * [22:20]FC + PRIORITY字段值85优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV86Pri : 3; /* * [26:24]FC + PRIORITY字段值86优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV87Pri : 3; /* * [30:28]FC + PRIORITY字段值87优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI10_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI9 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri9 { + struct tagStIpsurxFcPriorityPri9 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV79Pri : 3; /* * [30:28]FC + PRIORITY字段值79优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV78Pri : 3; /* * [26:24]FC + PRIORITY字段值78优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV77Pri : 3; /* * [22:20]FC + PRIORITY字段值77优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV76Pri : 3; /* * [18:16]FC + PRIORITY字段值76优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV75Pri : 3; /* * [14:12]FC + PRIORITY字段值75优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV74Pri : 3; /* * [10:8]FC + PRIORITY字段值74优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV73Pri : 3; /* * [6:4]FC + PRIORITY字段值73优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV72Pri : 3; /* * [2:0]FC + PRIORITY字段值72优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV72Pri : 3; /* * [2:0]FC + PRIORITY字段值72优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV73Pri : 3; /* * [6:4]FC + PRIORITY字段值73优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV74Pri : 3; /* * [10:8]FC + PRIORITY字段值74优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV75Pri : 3; /* * [14:12]FC + PRIORITY字段值75优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV76Pri : 3; /* * [18:16]FC + PRIORITY字段值76优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV77Pri : 3; /* * [22:20]FC + PRIORITY字段值77优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV78Pri : 3; /* * [26:24]FC + PRIORITY字段值78优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV79Pri : 3; /* * [30:28]FC + PRIORITY字段值79优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI9_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI8 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri8 { + struct tagStIpsurxFcPriorityPri8 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV71Pri : 3; /* * [30:28]FC + PRIORITY字段值71优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV70Pri : 3; /* * [26:24]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV69Pri : 3; /* * [22:20]FC + PRIORITY字段值69优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV68Pri : 3; /* * [18:16]FC + PRIORITY字段值68优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV67Pri : 3; /* * [14:12]FC + PRIORITY字段值67优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV66Pri : 3; /* * [10:8]FC + PRIORITY字段值66优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV65Pri : 3; /* * [6:4]FC + PRIORITY字段值65优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV64Pri : 3; /* * [2:0]FC + PRIORITY字段值64优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV64Pri : 3; /* * [2:0]FC + PRIORITY字段值64优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV65Pri : 3; /* * [6:4]FC + PRIORITY字段值65优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV66Pri : 3; /* * [10:8]FC + PRIORITY字段值66优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV67Pri : 3; /* * [14:12]FC + PRIORITY字段值67优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV68Pri : 3; /* * [18:16]FC + PRIORITY字段值68优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV69Pri : 3; /* * [22:20]FC + PRIORITY字段值69优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV70Pri : 3; /* * [26:24]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV71Pri : 3; /* * [30:28]FC + PRIORITY字段值71优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI8_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI7 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri7 { + struct tagStIpsurxFcPriorityPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV63Pri : 3; /* * [30:28]FC + PRIORITY字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV62Pri : 3; /* * [26:24]FC + PRIORITY字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV61Pri : 3; /* * [22:20]FC + PRIORITY字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV60Pri : 3; /* * [18:16]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV59Pri : 3; /* * [14:12]FC + PRIORITY字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV58Pri : 3; /* * [10:8]FC + PRIORITY字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV57Pri : 3; /* * [6:4]FC + PRIORITY字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV56Pri : 3; /* * [2:0]FC + PRIORITY字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV56Pri : 3; /* * [2:0]FC + PRIORITY字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV57Pri : 3; /* * [6:4]FC + PRIORITY字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV58Pri : 3; /* * [10:8]FC + PRIORITY字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV59Pri : 3; /* * [14:12]FC + PRIORITY字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV60Pri : 3; /* * [18:16]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV61Pri : 3; /* * [22:20]FC + PRIORITY字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV62Pri : 3; /* * [26:24]FC + PRIORITY字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV63Pri : 3; /* * [30:28]FC + PRIORITY字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI7_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI6 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri6 { + struct tagStIpsurxFcPriorityPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV55Pri : 3; /* * [30:28]FC + PRIORITY字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV54Pri : 3; /* * [26:24]FC + PRIORITY字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV53Pri : 3; /* * [22:20]FC + PRIORITY字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV52Pri : 3; /* * [18:16]FC + PRIORITY字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV51Pri : 3; /* * [14:12]FC + PRIORITY字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV50Pri : 3; /* * [10:8]FC + PRIORITY字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV49Pri : 3; /* * [6:4]FC + PRIORITY字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV48Pri : 3; /* * [2:0]FC + PRIORITY字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV48Pri : 3; /* * [2:0]FC + PRIORITY字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV49Pri : 3; /* * [6:4]FC + PRIORITY字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV50Pri : 3; /* * [10:8]FC + PRIORITY字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV51Pri : 3; /* * [14:12]FC + PRIORITY字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV52Pri : 3; /* * [18:16]FC + PRIORITY字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV53Pri : 3; /* * [22:20]FC + PRIORITY字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV54Pri : 3; /* * [26:24]FC + PRIORITY字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV55Pri : 3; /* * [30:28]FC + PRIORITY字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI6_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI5 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri5 { + struct tagStIpsurxFcPriorityPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV47Pri : 3; /* * [30:28]FC + PRIORITY字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV46Pri : 3; /* * [26:24]FC + PRIORITY字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV45Pri : 3; /* * [22:20]FC + PRIORITY字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV44Pri : 3; /* * [18:16]FC + PRIORITY字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV43Pri : 3; /* * [14:12]FC + PRIORITY字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV42Pri : 3; /* * [10:8]FC + PRIORITY字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV41Pri : 3; /* * [6:4]FC + PRIORITY字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV40Pri : 3; /* * [2:0]FC + PRIORITY字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV40Pri : 3; /* * [2:0]FC + PRIORITY字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV41Pri : 3; /* * [6:4]FC + PRIORITY字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV42Pri : 3; /* * [10:8]FC + PRIORITY字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV43Pri : 3; /* * [14:12]FC + PRIORITY字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV44Pri : 3; /* * [18:16]FC + PRIORITY字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV45Pri : 3; /* * [22:20]FC + PRIORITY字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV46Pri : 3; /* * [26:24]FC + PRIORITY字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV47Pri : 3; /* * [30:28]FC + PRIORITY字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI5_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI4 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri4 { + struct tagStIpsurxFcPriorityPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV39Pri : 3; /* * [30:28]FC + PRIORITY字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV38Pri : 3; /* * [26:24]FC + PRIORITY字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV37Pri : 3; /* * [22:20]FC + PRIORITY字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV36Pri : 3; /* * [18:16]FC + PRIORITY字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV35Pri : 3; /* * [14:12]FC + PRIORITY字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV34Pri : 3; /* * [10:8]FC + PRIORITY字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV33Pri : 3; /* * [6:4]FC + PRIORITY字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV32Pri : 3; /* * [2:0]FC + PRIORITY字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV32Pri : 3; /* * [2:0]FC + PRIORITY字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV33Pri : 3; /* * [6:4]FC + PRIORITY字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV34Pri : 3; /* * [10:8]FC + PRIORITY字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV35Pri : 3; /* * [14:12]FC + PRIORITY字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV36Pri : 3; /* * [18:16]FC + PRIORITY字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV37Pri : 3; /* * [22:20]FC + PRIORITY字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV38Pri : 3; /* * [26:24]FC + PRIORITY字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV39Pri : 3; /* * [30:28]FC + PRIORITY字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI4_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI3 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri3 { + struct tagStIpsurxFcPriorityPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV31Pri : 3; /* * [30:28]FC + PRIORITY字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV30Pri : 3; /* * [26:24]FC + PRIORITY字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV29Pri : 3; /* * [22:20]FC + PRIORITY字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV28Pri : 3; /* * [18:16]FC + PRIORITY字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV27Pri : 3; /* * [14:12]FC + PRIORITY字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV26Pri : 3; /* * [10:8]FC + PRIORITY字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV25Pri : 3; /* * [6:4]FC + PRIORITY字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV24Pri : 3; /* * [2:0]FC + PRIORITY字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV24Pri : 3; /* * [2:0]FC + PRIORITY字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV25Pri : 3; /* * [6:4]FC + PRIORITY字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV26Pri : 3; /* * [10:8]FC + PRIORITY字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV27Pri : 3; /* * [14:12]FC + PRIORITY字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV28Pri : 3; /* * [18:16]FC + PRIORITY字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV29Pri : 3; /* * [22:20]FC + PRIORITY字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV30Pri : 3; /* * [26:24]FC + PRIORITY字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV31Pri : 3; /* * [30:28]FC + PRIORITY字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI3_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI2 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri2 { + struct tagStIpsurxFcPriorityPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV23Pri : 3; /* * [30:28]FC + PRIORITY字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV22Pri : 3; /* * [26:24]FC + PRIORITY字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV21Pri : 3; /* * [22:20]FC + PRIORITY字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV20Pri : 3; /* * [18:16]FC + PRIORITY字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV19Pri : 3; /* * [14:12]FC + PRIORITY字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV18Pri : 3; /* * [10:8]FC + PRIORITY字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV17Pri : 3; /* * [6:4]FC + PRIORITY字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV16Pri : 3; /* * [2:0]FC + PRIORITY字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV16Pri : 3; /* * [2:0]FC + PRIORITY字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV17Pri : 3; /* * [6:4]FC + PRIORITY字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV18Pri : 3; /* * [10:8]FC + PRIORITY字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV19Pri : 3; /* * [14:12]FC + PRIORITY字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV20Pri : 3; /* * [18:16]FC + PRIORITY字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV21Pri : 3; /* * [22:20]FC + PRIORITY字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV22Pri : 3; /* * [26:24]FC + PRIORITY字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV23Pri : 3; /* * [30:28]FC + PRIORITY字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI2_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI1 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri1 { + struct tagStIpsurxFcPriorityPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV15Pri : 3; /* * [30:28]FC + PRIORITY字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV14Pri : 3; /* * [26:24]FC + PRIORITY字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV13Pri : 3; /* * [22:20]FC + PRIORITY字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV12Pri : 3; /* * [18:16]FC + PRIORITY字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV11Pri : 3; /* * [14:12]FC + PRIORITY字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV10Pri : 3; /* * [10:8]FC + PRIORITY字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV9Pri : 3; /* * [6:4]FC + PRIORITY字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV8Pri : 3; /* * [2:0]FC + PRIORITY字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV8Pri : 3; /* * [2:0]FC + PRIORITY字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV9Pri : 3; /* * [6:4]FC + PRIORITY字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV10Pri : 3; /* * [10:8]FC + PRIORITY字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV11Pri : 3; /* * [14:12]FC + PRIORITY字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV12Pri : 3; /* * [18:16]FC + PRIORITY字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV13Pri : 3; /* * [22:20]FC + PRIORITY字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV14Pri : 3; /* * [26:24]FC + PRIORITY字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV15Pri : 3; /* * [30:28]FC + PRIORITY字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI1_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI0 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri0 { + struct tagStIpsurxFcPriorityPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV7Pri : 3; /* * [30:28]FC + PRIORITY字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV6Pri : 3; /* * [26:24]FC + PRIORITY字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV5Pri : 3; /* * [22:20]FC + PRIORITY字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV4Pri : 3; /* * [18:16]FC + PRIORITY字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV3Pri : 3; /* * [14:12]FC + PRIORITY字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV2Pri : 3; /* * [10:8]FC + PRIORITY字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV1Pri : 3; /* * [6:4]FC + PRIORITY字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV0Pri : 3; /* * [2:0]FC + PRIORITY字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV0Pri : 3; /* * [2:0]FC + PRIORITY字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV1Pri : 3; /* * [6:4]FC + PRIORITY字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV2Pri : 3; /* * [10:8]FC + PRIORITY字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV3Pri : 3; /* * [14:12]FC + PRIORITY字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV4Pri : 3; /* * [18:16]FC + PRIORITY字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV5Pri : 3; /* * [22:20]FC + PRIORITY字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV6Pri : 3; /* * [26:24]FC + PRIORITY字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV7Pri : 3; /* * [30:28]FC + PRIORITY字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI0_U; + +/* ** + * Union name : IPSURX_CRC_CTRL + * @brief IPSURX CRC控制寄存器 + * Description: + */ +typedef union tagUnIpsurxCrcCtrl { + struct tagStIpsurxCrcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 13; /* * [31:19]建议不要修改bit[18:0]的默认值。 */ + unsigned int ipsurxRoceIcrcRsltInv : 1; /* * [18:18]RoCE ICRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxRoceIcrcRsltBitRev : 1; /* * [17:17]RoCE + ICRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxRoceIcrcDatBitRev : 1; /* * [16:16]RoCE + ICRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved1 : 1; /* * [15:15] */ + unsigned int ipsurxIwarpCrcRsltInv : 1; /* * [14:14]IWARP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxIwarpCrcRsltBitRev : 1; /* * [13:13]IWARP + CRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxIwarpCrcDatBitRev : 1; /* * [12:12]IWARP + CRC输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved2 : 1; /* * [11:11] */ + unsigned int ipsurxSctpCrcRsltInv : 1; /* * [10:10]SCTP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxSctpCrcRsltBitRev : 1; /* * [9:9]SCTP + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxSctpCrcDatBitRev : 1; /* * [8:8]SCTP + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved3 : 1; /* * [7:7] */ + unsigned int ipsurxFcCrcRsltInv : 1; /* * [6:6]FC CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxFcCrcRsltBitRev : 1; /* * [5:5]FC CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 + */ + unsigned int ipsurxFcCrcDatBitRev : 1; /* * [4:4]FC CRC校验输入数据Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved4 : 1; /* * [3:3]保留。 */ + unsigned int ipsurxDifxCrcRsltInv : 1; /* * [2:2]DIFX CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxDifxCrcRsltBitRev : 1; /* * [1:1]DIFX + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxDifxCrcDatBitRev : 1; /* * [0:0]DIFX + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ +#else + unsigned int ipsurxDifxCrcDatBitRev : 1; /* * [0:0]DIFX + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxDifxCrcRsltBitRev : 1; /* * [1:1]DIFX + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxDifxCrcRsltInv : 1; /* * [2:2]DIFX CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved4 : 1; /* * [3:3]保留。 */ + unsigned int ipsurxFcCrcDatBitRev : 1; /* * [4:4]FC CRC校验输入数据Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxFcCrcRsltBitRev : 1; /* * [5:5]FC CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 + */ + unsigned int ipsurxFcCrcRsltInv : 1; /* * [6:6]FC CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved3 : 1; /* * [7:7] */ + unsigned int ipsurxSctpCrcDatBitRev : 1; /* * [8:8]SCTP + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxSctpCrcRsltBitRev : 1; /* * [9:9]SCTP + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxSctpCrcRsltInv : 1; /* * [10:10]SCTP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved2 : 1; /* * [11:11] */ + unsigned int ipsurxIwarpCrcDatBitRev : 1; /* * [12:12]IWARP + CRC输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxIwarpCrcRsltBitRev : 1; /* * [13:13]IWARP + CRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxIwarpCrcRsltInv : 1; /* * [14:14]IWARP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved1 : 1; /* * [15:15] */ + unsigned int ipsurxRoceIcrcDatBitRev : 1; /* * [16:16]RoCE + ICRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxRoceIcrcRsltBitRev : 1; /* * [17:17]RoCE + ICRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxRoceIcrcRsltInv : 1; /* * [18:18]RoCE ICRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved0 : 13; /* * [31:19]建议不要修改bit[18:0]的默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CRC_CTRL_U; + +/* ** + * Union name : IPSURX_ROCE_ICRC_INI + * @brief RoCE ICRC初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxRoceIcrcIni { + struct tagStIpsurxRoceIcrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxRoceIcrcIni : 32; /* * [31:0]RoCE + * ICRC校验时加载的ICRC计算初值。默认值：按照标准算法得到的0xC704DD7B。【注】：该默认值为算法本身初始值0xFFFFFFFF，计算8字节固定全1数据后的CRC值。建议不要修改默认值。 + */ +#else + unsigned int + ipsurxRoceIcrcIni : 32; /* * [31:0]RoCE + * ICRC校验时加载的ICRC计算初值。默认值：按照标准算法得到的0xC704DD7B。【注】：该默认值为算法本身初始值0xFFFFFFFF，计算8字节固定全1数据后的CRC值。建议不要修改默认值。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ICRC_INI_U; + +/* ** + * Union name : IPSURX_ROCE_ICRC_MN + * @brief RoCE报文ICRC Magic Number值寄存器 + * Description: + */ +typedef union tagUnIpsurxRoceIcrcMn { + struct tagStIpsurxRoceIcrcMn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxRoceIcrcMn : 32; /* * [31:0]RoCE ICRC校验Magic + * Number配置值。默认值：按照标准算法得到的0x1CDF4421。【注】：该值与CRC算法的相关配置有关，需与之匹配。建议不要修改默认值。 + */ +#else + unsigned int + ipsurxRoceIcrcMn : 32; /* * [31:0]RoCE ICRC校验Magic + * Number配置值。默认值：按照标准算法得到的0x1CDF4421。【注】：该值与CRC算法的相关配置有关，需与之匹配。建议不要修改默认值。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ICRC_MN_U; + +/* ** + * Union name : IPSURX_IWARP_CRC_INI + * @brief IWARP报文CRC 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxIwarpCrcIni { + struct tagStIpsurxIwarpCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIwarpCrcIni : 32; /* * [31:0]计算TCP报文的IWARP CRC初始值。建议不要修改默认值。 */ +#else + unsigned int ipsurxIwarpCrcIni : 32; /* * [31:0]计算TCP报文的IWARP CRC初始值。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IWARP_CRC_INI_U; + +/* ** + * Union name : IPSURX_FC_CRC_INI + * @brief FCoE报文CRC 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCrcIni { + struct tagStIpsurxFcCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFcCrcIni : 32; /* * [31:0]FC CRC初始值。建议不要修改默认值。 */ +#else + unsigned int ipsurxFcCrcIni : 32; /* * [31:0]FC CRC初始值。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CRC_INI_U; + +/* ** + * Union name : IPSURX_FC_CRC_MN + * @brief FCoE报文CRC Magic Number值寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCrcMn { + struct tagStIpsurxFcCrcMn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFcCrcMn : 32; /* * [31:0]FC CRC校验Magic + Number配置值。默认值：0x1CDF4421。建议不要修改默认值。 */ +#else + unsigned int ipsurxFcCrcMn : 32; /* * [31:0]FC CRC校验Magic + Number配置值。默认值：0x1CDF4421。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CRC_MN_U; + +/* ** + * Union name : IPSURX_SCTP_CRC_INI + * @brief SCTP报文CRC 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxSctpCrcIni { + struct tagStIpsurxSctpCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSctpCrcIni : 32; /* * [31:0]SCTP CRC初始值。建议不要修改默认值。 */ +#else + unsigned int ipsurxSctpCrcIni : 32; /* * [31:0]SCTP CRC初始值。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SCTP_CRC_INI_U; + +/* ** + * Union name : IPSURX_DIFX_CRC_INI + * @brief DIF/DIX CRC16 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxDifxCrcIni { + struct tagStIpsurxDifxCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int ipsurxDifxCrcIni : 16; /* * [15:0]DIF/DIX CRC16 初始值建议不要修改默认值。 */ +#else + unsigned int ipsurxDifxCrcIni : 16; /* * [15:0]DIF/DIX CRC16 初始值建议不要修改默认值。 */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_DIFX_CRC_INI_U; + +/* ** + * Union name : IPSURX_IPV4_VER_ILGL_CNT + * @brief IPV4_VER_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4VerIlglCnt { + struct tagStIpsurxIpv4VerIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4VerIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4VerIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_VER_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_IHL_ILGL_CNT + * @brief IPV4_IHL_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4IhlIlglCnt { + struct tagStIpsurxIpv4IhlIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4IhlIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4IhlIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_IHL_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_SIP_ILGL_CNT + * @brief IPV4_SIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4SipIlglCnt { + struct tagStIpsurxIpv4SipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4SipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4SipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_SIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_DIP_ILGL_CNT + * @brief IPV4_DIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4DipIlglCnt { + struct tagStIpsurxIpv4DipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4DipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4DipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_CS_ILGL_CNT + * @brief IPV4_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4CsIlglCnt { + struct tagStIpsurxIpv4CsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4CsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4CsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_VER_ILGL_CNT + * @brief IPV6_VER_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6VerIlglCnt { + struct tagStIpsurxIpv6VerIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6VerIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6VerIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_VER_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_SIP_ILGL_CNT + * @brief IPV6_SIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6SipIlglCnt { + struct tagStIpsurxIpv6SipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6SipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6SipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_SIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_DIP_ILGL_CNT + * @brief IPV6_DIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6DipIlglCnt { + struct tagStIpsurxIpv6DipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6DipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6DipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_TCP_LAND_ILGL_CNT + * @brief TCP_LAND_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxTcpLandIlglCnt { + struct tagStIpsurxTcpLandIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcpLandIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcpLandIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCP_LAND_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_TCP_CS_ILGL_CNT + * @brief TCP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxTcpCsIlglCnt { + struct tagStIpsurxTcpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_UDP_CS_ZERO_CNT + * @brief IPv6 UDP_CS_ZERO计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6UdpCsZeroCnt { + struct tagStIpsurxIpv6UdpCsZeroCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6UdpCsZeroCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6UdpCsZeroCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_UDP_CS_ZERO_CNT_U; + +/* ** + * Union name : IPSURX_UDP_CS_ILGL_CNT + * @brief UDP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxUdpCsIlglCnt { + struct tagStIpsurxUdpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxUdpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxUdpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_UDP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IGMP_CS_ILGL_CNT + * @brief IGMP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIgmpCsIlglCnt { + struct tagStIpsurxIgmpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIgmpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIgmpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IGMP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ICMPV4_CS_ILGL_CNT + * @brief ICMPV4_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIcmpv4CsIlglCnt { + struct tagStIpsurxIcmpv4CsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIcmpv4CsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIcmpv4CsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ICMPV4_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ICMPV6_CS_ILGL_CNT + * @brief ICMPV6_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIcmpv6CsIlglCnt { + struct tagStIpsurxIcmpv6CsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIcmpv6CsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIcmpv6CsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ICMPV6_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_SCTP_CS_ILGL_CNT + * @brief SCTP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxSctpCsIlglCnt { + struct tagStIpsurxSctpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSctpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxSctpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SCTP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV2_IPV4_FRAG_ILGL_CNT + * @brief ROCEV2_IPV4_FRAG_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev2Ipv4FragIlglCnt { + struct tagStIpsurxRocev2Ipv4FragIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev2Ipv4FragIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev2Ipv4FragIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_IPV4_FRAG_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV2_IPV4_UDP_CS_ILGL_CNT + * @brief ROCEV2_IPV4_UDP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev2Ipv4UdpCsIlglCnt { + struct tagStIpsurxRocev2Ipv4UdpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev2Ipv4UdpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev2Ipv4UdpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_IPV4_UDP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV2_IPV6_UDP_CS_ILGL_CNT + * @brief ROCEV2_IPV6_UDP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev2Ipv6UdpCsIlglCnt { + struct tagStIpsurxRocev2Ipv6UdpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev2Ipv6UdpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev2Ipv6UdpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_IPV6_UDP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_DGID_ILGL_CNT + * @brief ROCEV1_DGID_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1DgidIlglCnt { + struct tagStIpsurxRocev1DgidIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1DgidIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1DgidIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_DGID_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_SGID_ILGL_CNT + * @brief ROCEV1_SGID_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1SgidIlglCnt { + struct tagStIpsurxRocev1SgidIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1SgidIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1SgidIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_SGID_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_IPVER_ILGL_CNT + * @brief ROCEV1_IPVER_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1IpverIlglCnt { + struct tagStIpsurxRocev1IpverIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1IpverIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1IpverIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_IPVER_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_NXHDR_ILGL_CNT + * @brief ROCEV1_NXHDR_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1NxhdrIlglCnt { + struct tagStIpsurxRocev1NxhdrIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1NxhdrIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1NxhdrIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_NXHDR_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_PLEN_ILGL_CNT + * @brief ROCEV1_PLEN_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1PlenIlglCnt { + struct tagStIpsurxRocev1PlenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1PlenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1PlenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_PLEN_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCE_DQP_ILGL_CNT + * @brief ROCE_DQP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRoceDqpIlglCnt { + struct tagStIpsurxRoceDqpIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRoceDqpIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRoceDqpIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_DQP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IB_ICRC_ILGL_CNT + * @brief IB_ICRC_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIbIcrcIlglCnt { + struct tagStIpsurxIbIcrcIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIbIcrcIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIbIcrcIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IB_ICRC_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_FC_CRC_ILGL_CNT + * @brief FC_CRC_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxFcCrcIlglCnt { + struct tagStIpsurxFcCrcIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFcCrcIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxFcCrcIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CRC_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_TO_UP_PKT_ILGL_CNT + * @brief TO UP报文校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxToUpPktIlglCnt { + struct tagStIpsurxToUpPktIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxToUpPktIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxToUpPktIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TO_UP_PKT_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_NCSI_CTRL + * @brief NCSI控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiCtrl { + struct tagStIpsurxNcsiCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 25; /* * [31:7] */ + unsigned int ipsurxFicNcsiEn : 1; /* * + [6:6]预留通道属性为FIC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxHg2NcsiEn : 1; /* * + [5:5]预留通道属性为HG2，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxMacNcsiEn : 1; /* * [4:4]通道属性为MAC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int reserved1 : 1; /* * [3:3] */ + unsigned int ipsurxNcsiPktPri : 3; /* * [2:0]NCSI报文优先级。3'b000，最高优先级；...3'b111，最低优先级。 */ +#else + unsigned int ipsurxNcsiPktPri : 3; /* * [2:0]NCSI报文优先级。3'b000，最高优先级；...3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [3:3] */ + unsigned int ipsurxMacNcsiEn : 1; /* * [4:4]通道属性为MAC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2NcsiEn : 1; /* * + [5:5]预留通道属性为HG2，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxFicNcsiEn : 1; /* * + [6:6]预留通道属性为FIC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int reserved0 : 25; /* * [31:7] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_FILTER_MNG + * @brief NCSI FILTER管理寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiFilterMng { + struct tagStIpsurxNcsiFilterMng { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3MacPort : 4; /* * [31:28]0x0~0xF：rule 3对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved0 : 2; /* * [27:26] */ + unsigned int ipsurxNcsiFltRule3FwdAct : 1; /* * [25:25]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule3En : 1; /* * [24:24]rule3 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule2MacPort : 4; /* * [23:20]0x0~0xF：rule 2 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved1 : 2; /* * [19:18] */ + unsigned int ipsurxNcsiFltRule2FwdAct : 1; /* * [17:17]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule2En : 1; /* * [16:16]rule2 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule1MacPort : 4; /* * [15:12]0x0~0xF：rule 1 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved2 : 2; /* * [11:10] */ + unsigned int ipsurxNcsiFltRule1FwdAct : 1; /* * [9:9]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule1En : 1; /* * [8:8]rule1 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule0MacPort : 4; /* * [7:4]0x0~0xF：rule 0 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved3 : 2; /* * [3:2] */ + unsigned int ipsurxNcsiFltRule0FwdAct : 1; /* * [1:1]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule0En : 1; /* * [0:0]rule0 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ +#else + unsigned int + ipsurxNcsiFltRule0En : 1; /* * [0:0]rule0 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule0FwdAct : 1; /* * [1:1]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved3 : 2; /* * [3:2] */ + unsigned int ipsurxNcsiFltRule0MacPort : 4; /* * [7:4]0x0~0xF：rule 0 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int + ipsurxNcsiFltRule1En : 1; /* * [8:8]rule1 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule1FwdAct : 1; /* * [9:9]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved2 : 2; /* * [11:10] */ + unsigned int ipsurxNcsiFltRule1MacPort : 4; /* * [15:12]0x0~0xF：rule 1 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int + ipsurxNcsiFltRule2En : 1; /* * [16:16]rule2 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule2FwdAct : 1; /* * [17:17]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved1 : 2; /* * [19:18] */ + unsigned int ipsurxNcsiFltRule2MacPort : 4; /* * [23:20]0x0~0xF：rule 2 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int + ipsurxNcsiFltRule3En : 1; /* * [24:24]rule3 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule3FwdAct : 1; /* * [25:25]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved0 : 2; /* * [27:26] */ + unsigned int ipsurxNcsiFltRule3MacPort : 4; /* * [31:28]0x0~0xF：rule 3对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_FILTER_MNG_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac3HCtrl { + struct tagStIpsurxNcsiRule3Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac3LCtrl { + struct tagStIpsurxNcsiRule3Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac2HCtrl { + struct tagStIpsurxNcsiRule3Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac2LCtrl { + struct tagStIpsurxNcsiRule3Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac1HCtrl { + struct tagStIpsurxNcsiRule3Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac1LCtrl { + struct tagStIpsurxNcsiRule3Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac0HCtrl { + struct tagStIpsurxNcsiRule3Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac0LCtrl { + struct tagStIpsurxNcsiRule3Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC0_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac3HCtrl { + struct tagStIpsurxNcsiRule2Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac3LCtrl { + struct tagStIpsurxNcsiRule2Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac2HCtrl { + struct tagStIpsurxNcsiRule2Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac2LCtrl { + struct tagStIpsurxNcsiRule2Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac1HCtrl { + struct tagStIpsurxNcsiRule2Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac1LCtrl { + struct tagStIpsurxNcsiRule2Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac0HCtrl { + struct tagStIpsurxNcsiRule2Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac0LCtrl { + struct tagStIpsurxNcsiRule2Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC0_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac3HCtrl { + struct tagStIpsurxNcsiRule1Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac3LCtrl { + struct tagStIpsurxNcsiRule1Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac2HCtrl { + struct tagStIpsurxNcsiRule1Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac2LCtrl { + struct tagStIpsurxNcsiRule1Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac1HCtrl { + struct tagStIpsurxNcsiRule1Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac1LCtrl { + struct tagStIpsurxNcsiRule1Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac0HCtrl { + struct tagStIpsurxNcsiRule1Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac0LCtrl { + struct tagStIpsurxNcsiRule1Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC0_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac3HCtrl { + struct tagStIpsurxNcsiRule0Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac3LCtrl { + struct tagStIpsurxNcsiRule0Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac2HCtrl { + struct tagStIpsurxNcsiRule0Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac2LCtrl { + struct tagStIpsurxNcsiRule0Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac1HCtrl { + struct tagStIpsurxNcsiRule0Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac1LCtrl { + struct tagStIpsurxNcsiRule0Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac0HCtrl { + struct tagStIpsurxNcsiRule0Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac0LCtrl { + struct tagStIpsurxNcsiRule0Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC0_L_CTRL_U; + + +/* ** + * Union name : IPSURX_NCSI_RULE_VLAN_EN + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRuleVlanEn { + struct tagStIpsurxNcsiRuleVlanEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int + ipsurxNcsiRuleVlanEn : 4; /* * [3:0]NCSI FILTER VLAN使能寄存器。1'b0：所有携带VLAN + TAG的报文不能通过该规则检测，不含VLAN + TAG的报文通过该规则检测；1'b1：根据该条规则的8个VLAN控制寄存器的配置进行NCSI报文VLAN的检测。BIT[3]：NCSI + RULE3 VLAN EN；BIT[2]：NCSI RULE2 V LAN EN；BIT[1]：NCSI RULE1 VLAN + EN；BIT[0]：NCSI RULE0 VLAN EN。 */ +#else + unsigned int + ipsurxNcsiRuleVlanEn : 4; /* * [3:0]NCSI FILTER VLAN使能寄存器。1'b0：所有携带VLAN + TAG的报文不能通过该规则检测，不含VLAN + TAG的报文通过该规则检测；1'b1：根据该条规则的8个VLAN控制寄存器的配置进行NCSI报文VLAN的检测。BIT[3]：NCSI + RULE3 VLAN EN；BIT[2]：NCSI RULE2 V LAN EN；BIT[1]：NCSI RULE1 VLAN + EN；BIT[0]：NCSI RULE0 VLAN EN。 */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE_VLAN_EN_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan7Ctrl { + struct tagStIpsurxNcsiRule3Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan6Ctrl { + struct tagStIpsurxNcsiRule3Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan5Ctrl { + struct tagStIpsurxNcsiRule3Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan4Ctrl { + struct tagStIpsurxNcsiRule3Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan3Ctrl { + struct tagStIpsurxNcsiRule3Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan2Ctrl { + struct tagStIpsurxNcsiRule3Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan1Ctrl { + struct tagStIpsurxNcsiRule3Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan0Ctrl { + struct tagStIpsurxNcsiRule3Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan7Ctrl { + struct tagStIpsurxNcsiRule2Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan6Ctrl { + struct tagStIpsurxNcsiRule2Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan5Ctrl { + struct tagStIpsurxNcsiRule2Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan4Ctrl { + struct tagStIpsurxNcsiRule2Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan3Ctrl { + struct tagStIpsurxNcsiRule2Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan2Ctrl { + struct tagStIpsurxNcsiRule2Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan1Ctrl { + struct tagStIpsurxNcsiRule2Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan0Ctrl { + struct tagStIpsurxNcsiRule2Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan7Ctrl { + struct tagStIpsurxNcsiRule1Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan6Ctrl { + struct tagStIpsurxNcsiRule1Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan5Ctrl { + struct tagStIpsurxNcsiRule1Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan4Ctrl { + struct tagStIpsurxNcsiRule1Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan3Ctrl { + struct tagStIpsurxNcsiRule1Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan2Ctrl { + struct tagStIpsurxNcsiRule1Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan1Ctrl { + struct tagStIpsurxNcsiRule1Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan0Ctrl { + struct tagStIpsurxNcsiRule1Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan7Ctrl { + struct tagStIpsurxNcsiRule0Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan6Ctrl { + struct tagStIpsurxNcsiRule0Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan5Ctrl { + struct tagStIpsurxNcsiRule0Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan4Ctrl { + struct tagStIpsurxNcsiRule0Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan3Ctrl { + struct tagStIpsurxNcsiRule0Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan2Ctrl { + struct tagStIpsurxNcsiRule0Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan1Ctrl { + struct tagStIpsurxNcsiRule0Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan0Ctrl { + struct tagStIpsurxNcsiRule0Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcCtrl { + struct tagStIpsurxNcsiRule3BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule3BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcCtrl { + struct tagStIpsurxNcsiRule2BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule2BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcCtrl { + struct tagStIpsurxNcsiRule1BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule1BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcCtrl { + struct tagStIpsurxNcsiRule0BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule0BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcArpTipv4Addr { + struct tagStIpsurxNcsiRule3BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule3BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcArpTipv4Addr { + struct tagStIpsurxNcsiRule2BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule2BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcArpTipv4Addr { + struct tagStIpsurxNcsiRule1BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule1BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcArpTipv4Addr { + struct tagStIpsurxNcsiRule0BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule0BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule3BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule3BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule2BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule2BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule1BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule1BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule0BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule0BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3McCtrl { + struct tagStIpsurxNcsiRule3McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule3McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule3McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule3McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2McCtrl { + struct tagStIpsurxNcsiRule2McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule2McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule2McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule2McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1McCtrl { + struct tagStIpsurxNcsiRule1McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule1McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule1McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule1McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0McCtrl { + struct tagStIpsurxNcsiRule0McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule0McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule0McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule0McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MC_CTRL_U; + +/* ** + * Union name : IPSURX_TO_BMC_ONLY_PKT_ILGL_CNT + * @brief TO BMC ONLY报文校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxToBmcOnlyPktIlglCnt { + struct tagStIpsurxToBmcOnlyPktIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxToBmcOnlyPktIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxToBmcOnlyPktIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TO_BMC_ONLY_PKT_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_WOL_CTRL + * @brief WOL控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWolCtrl { + struct tagStIpsurxWolCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 24; /* * [31:8]reserved. */ + unsigned int ipsurxWolModEn : 1; /* * + [7:7]WOL工作模式使能。1'b0：不使能WOL工作模式；1'b1：使能WOL工作模式。该寄存器只控制报文的转发，不影响WOL报文的检测。 + */ + unsigned int ipsurxFicWolEn : 1; /* * + [6:6]预留通道属性为FIC，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxHg2WolEn : 1; /* * + [5:5]预留通道属性为HG2，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxMacWolEn : 1; /* * [4:4]通道属性为MAC，WOL报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxWolWkupCtrl : 4; /* * + [3:0]Bit[i]（i=0~3)控制IPSURX模块产生的唤醒host[i](i=0~3)的请求。1'b0：清除唤醒请求；1'b1：不清除唤醒请求。 + */ +#else + unsigned int ipsurxWolWkupCtrl : 4; /* * + [3:0]Bit[i]（i=0~3)控制IPSURX模块产生的唤醒host[i](i=0~3)的请求。1'b0：清除唤醒请求；1'b1：不清除唤醒请求。 + */ + unsigned int ipsurxMacWolEn : 1; /* * [4:4]通道属性为MAC，WOL报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2WolEn : 1; /* * + [5:5]预留通道属性为HG2，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxFicWolEn : 1; /* * + [6:6]预留通道属性为FIC，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxWolModEn : 1; /* * + [7:7]WOL工作模式使能。1'b0：不使能WOL工作模式；1'b1：使能WOL工作模式。该寄存器只控制报文的转发，不影响WOL报文的检测。 + */ + unsigned int reserved : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL_CTRL_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_CTRL1 + * @brief WOL TYPE1报文检测RULE控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkCtrl1 { + struct tagStIpsurxWol1ChkCtrl1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxWol1ChkRule7Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int ipsurxWol1Rule7WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxWol1ChkRule6Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int ipsurxWol1Rule6WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxWol1ChkRule5Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int ipsurxWol1Rule5WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxWol1ChkRule4Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int ipsurxWol1Rule4WkHost : 2; /* * [1:0]唤醒主机编号。 */ +#else + unsigned int ipsurxWol1Rule4WkHost : 2; /* * [1:0]唤醒主机编号。 */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int + ipsurxWol1ChkRule4Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxWol1Rule5WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int + ipsurxWol1ChkRule5Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxWol1Rule6WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int + ipsurxWol1ChkRule6Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxWol1Rule7WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int + ipsurxWol1ChkRule7Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_CTRL1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_CTRL0 + * @brief WOL TYPE1报文检测RULE控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkCtrl0 { + struct tagStIpsurxWol1ChkCtrl0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxWol1ChkRule3Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int ipsurxWol1Rule3WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxWol1ChkRule2Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int ipsurxWol1Rule2WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxWol1ChkRule1Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int ipsurxWol1Rule1WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxWol1ChkRule0Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int ipsurxWol1Rule0WkHost : 2; /* * [1:0]唤醒主机编号。 */ +#else + unsigned int ipsurxWol1Rule0WkHost : 2; /* * [1:0]唤醒主机编号。 */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int + ipsurxWol1ChkRule0Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxWol1Rule1WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int + ipsurxWol1ChkRule1Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxWol1Rule2WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int + ipsurxWol1ChkRule2Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxWol1Rule3WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int + ipsurxWol1ChkRule3Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_CTRL0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7MacH { + struct tagStIpsurxWol1ChkRule7MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule7MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule7MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7MacL { + struct tagStIpsurxWol1ChkRule7MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule7MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6MacH { + struct tagStIpsurxWol1ChkRule6MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule6MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule6MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6MacL { + struct tagStIpsurxWol1ChkRule6MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule6MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5MacH { + struct tagStIpsurxWol1ChkRule5MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule5MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule5MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5MacL { + struct tagStIpsurxWol1ChkRule5MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule5MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4MacH { + struct tagStIpsurxWol1ChkRule4MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule4MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule4MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4MacL { + struct tagStIpsurxWol1ChkRule4MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule4MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3MacH { + struct tagStIpsurxWol1ChkRule3MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule3MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule3MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3MacL { + struct tagStIpsurxWol1ChkRule3MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule3MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2MacH { + struct tagStIpsurxWol1ChkRule2MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule2MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule2MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2MacL { + struct tagStIpsurxWol1ChkRule2MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule2MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1MacH { + struct tagStIpsurxWol1ChkRule1MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule1MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule1MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1MacL { + struct tagStIpsurxWol1ChkRule1MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule1MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0MacH { + struct tagStIpsurxWol1ChkRule0MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule0MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule0MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0MacL { + struct tagStIpsurxWol1ChkRule0MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule0MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7Vlanid { + struct tagStIpsurxWol1ChkRule7Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule7Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule7Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule7Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule7Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6Vlanid { + struct tagStIpsurxWol1ChkRule6Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule6Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule6Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule6Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule6Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5Vlanid { + struct tagStIpsurxWol1ChkRule5Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule5Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule5Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule5Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule5Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4Vlanid { + struct tagStIpsurxWol1ChkRule4Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule4Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule4Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule4Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule4Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3Vlanid { + struct tagStIpsurxWol1ChkRule3Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule3Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule3Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule3Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule3Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2Vlanid { + struct tagStIpsurxWol1ChkRule2Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule2Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule2Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule2Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule2Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1Vlanid { + struct tagStIpsurxWol1ChkRule1Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule1Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule1Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule1Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule1Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0Vlanid { + struct tagStIpsurxWol1ChkRule0Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule0Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule0Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule0Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule0Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw0 { + struct tagStIpsurxWol1ChkRule7IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw1 { + struct tagStIpsurxWol1ChkRule7IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw2 { + struct tagStIpsurxWol1ChkRule7IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw3 { + struct tagStIpsurxWol1ChkRule7IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw0 { + struct tagStIpsurxWol1ChkRule6IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw1 { + struct tagStIpsurxWol1ChkRule6IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw2 { + struct tagStIpsurxWol1ChkRule6IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw3 { + struct tagStIpsurxWol1ChkRule6IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw0 { + struct tagStIpsurxWol1ChkRule5IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw1 { + struct tagStIpsurxWol1ChkRule5IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw2 { + struct tagStIpsurxWol1ChkRule5IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw3 { + struct tagStIpsurxWol1ChkRule5IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw0 { + struct tagStIpsurxWol1ChkRule4IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw1 { + struct tagStIpsurxWol1ChkRule4IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw2 { + struct tagStIpsurxWol1ChkRule4IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw3 { + struct tagStIpsurxWol1ChkRule4IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw0 { + struct tagStIpsurxWol1ChkRule3IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw1 { + struct tagStIpsurxWol1ChkRule3IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw2 { + struct tagStIpsurxWol1ChkRule3IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw3 { + struct tagStIpsurxWol1ChkRule3IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw0 { + struct tagStIpsurxWol1ChkRule2IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw1 { + struct tagStIpsurxWol1ChkRule2IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw2 { + struct tagStIpsurxWol1ChkRule2IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw3 { + struct tagStIpsurxWol1ChkRule2IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw0 { + struct tagStIpsurxWol1ChkRule1IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw1 { + struct tagStIpsurxWol1ChkRule1IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw2 { + struct tagStIpsurxWol1ChkRule1IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw3 { + struct tagStIpsurxWol1ChkRule1IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw0 { + struct tagStIpsurxWol1ChkRule0IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw1 { + struct tagStIpsurxWol1ChkRule0IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw2 { + struct tagStIpsurxWol1ChkRule0IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw3 { + struct tagStIpsurxWol1ChkRule0IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW3_U; + + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7NodeAddrH { + struct tagStIpsurxWol1ChkRule7NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule7NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule7NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7NodeAddrL { + struct tagStIpsurxWol1ChkRule7NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule7NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6NodeAddrH { + struct tagStIpsurxWol1ChkRule6NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule6NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule6NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6NodeAddrL { + struct tagStIpsurxWol1ChkRule6NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule6NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5NodeAddrH { + struct tagStIpsurxWol1ChkRule5NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule5NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule5NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5NodeAddrL { + struct tagStIpsurxWol1ChkRule5NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule5NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4NodeAddrH { + struct tagStIpsurxWol1ChkRule4NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule4NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule4NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4NodeAddrL { + struct tagStIpsurxWol1ChkRule4NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule4NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3NodeAddrH { + struct tagStIpsurxWol1ChkRule3NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule3NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule3NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3NodeAddrL { + struct tagStIpsurxWol1ChkRule3NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule3NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2NodeAddrH { + struct tagStIpsurxWol1ChkRule2NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule2NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule2NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2NodeAddrL { + struct tagStIpsurxWol1ChkRule2NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule2NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1NodeAddrH { + struct tagStIpsurxWol1ChkRule1NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule1NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule1NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1NodeAddrL { + struct tagStIpsurxWol1ChkRule1NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule1NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0NodeAddrH { + struct tagStIpsurxWol1ChkRule0NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule0NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule0NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0NodeAddrL { + struct tagStIpsurxWol1ChkRule0NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule0NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW0 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw0 { + struct tagStIpsurxWol1MagicChkStatusDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P7rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P6rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW1 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw1 { + struct tagStIpsurxWol1MagicChkStatusDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P5rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P4rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW2 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw2 { + struct tagStIpsurxWol1MagicChkStatusDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P3rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P2rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW3 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw3 { + struct tagStIpsurxWol1MagicChkStatusDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P1rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P0rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_CTRL + * @brief WOL TYPE2报文检测控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkCtrl { + struct tagStIpsurxWol2ChkCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 9; /* * [31:23] */ + unsigned int ipsurxWol2ChkRule5Valid : 1; /* * + [22:22]rule5用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule5WkHost : 2; /* * [21:20]rule5唤醒主机编号。 */ + unsigned int reserved1 : 1; /* * [19:19] */ + unsigned int ipsurxWol2ChkRule4Valid : 1; /* * + [18:18]rule4用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule4WkHost : 2; /* * [17:16]rule4唤醒主机编号。 */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxWol2ChkRule3Valid : 1; /* * + [14:14]rule3用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule3WkHost : 2; /* * [13:12]rule3唤醒主机编号。 */ + unsigned int reserved3 : 1; /* * [11:11] */ + unsigned int ipsurxWol2ChkRule2Valid : 1; /* * + [10:10]rule2用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule2WkHost : 2; /* * [9:8]rule2唤醒主机编号。 */ + unsigned int reserved4 : 1; /* * [7:7] */ + unsigned int ipsurxWol2ChkRule1Valid : 1; /* * + [6:6]rule1用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule1WkHost : 2; /* * [5:4]rule1唤醒主机编号。 */ + unsigned int reserved5 : 1; /* * [3:3] */ + unsigned int ipsurxWol2ChkRule0Valid : 1; /* * + [2:2]rule0用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule0WkHost : 2; /* * [1:0]rule0唤醒主机编号。 */ +#else + unsigned int ipsurxWol2ChkRule0WkHost : 2; /* * [1:0]rule0唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule0Valid : 1; /* * + [2:2]rule0用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved5 : 1; /* * [3:3] */ + unsigned int ipsurxWol2ChkRule1WkHost : 2; /* * [5:4]rule1唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule1Valid : 1; /* * + [6:6]rule1用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved4 : 1; /* * [7:7] */ + unsigned int ipsurxWol2ChkRule2WkHost : 2; /* * [9:8]rule2唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule2Valid : 1; /* * + [10:10]rule2用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved3 : 1; /* * [11:11] */ + unsigned int ipsurxWol2ChkRule3WkHost : 2; /* * [13:12]rule3唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule3Valid : 1; /* * + [14:14]rule3用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxWol2ChkRule4WkHost : 2; /* * [17:16]rule4唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule4Valid : 1; /* * + [18:18]rule4用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved1 : 1; /* * [19:19] */ + unsigned int ipsurxWol2ChkRule5WkHost : 2; /* * [21:20]rule5唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule5Valid : 1; /* * + [22:22]rule5用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved0 : 9; /* * [31:23] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_CTRL_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw0 { + struct tagStIpsurxWol2ChkRule5MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw1 { + struct tagStIpsurxWol2ChkRule5MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw2 { + struct tagStIpsurxWol2ChkRule5MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw3 { + struct tagStIpsurxWol2ChkRule5MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw0 { + struct tagStIpsurxWol2ChkRule4MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw1 { + struct tagStIpsurxWol2ChkRule4MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw2 { + struct tagStIpsurxWol2ChkRule4MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw3 { + struct tagStIpsurxWol2ChkRule4MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw0 { + struct tagStIpsurxWol2ChkRule3MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw1 { + struct tagStIpsurxWol2ChkRule3MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw2 { + struct tagStIpsurxWol2ChkRule3MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw3 { + struct tagStIpsurxWol2ChkRule3MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw0 { + struct tagStIpsurxWol2ChkRule2MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw1 { + struct tagStIpsurxWol2ChkRule2MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw2 { + struct tagStIpsurxWol2ChkRule2MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw3 { + struct tagStIpsurxWol2ChkRule2MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw0 { + struct tagStIpsurxWol2ChkRule1MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw1 { + struct tagStIpsurxWol2ChkRule1MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw2 { + struct tagStIpsurxWol2ChkRule1MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw3 { + struct tagStIpsurxWol2ChkRule1MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw0 { + struct tagStIpsurxWol2ChkRule0MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw1 { + struct tagStIpsurxWol2ChkRule0MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw2 { + struct tagStIpsurxWol2ChkRule0MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw3 { + struct tagStIpsurxWol2ChkRule0MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW3_U; + + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw00 { + struct tagStIpsurxWol2Rule5PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule5PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw01 { + struct tagStIpsurxWol2Rule5PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule5PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw02 { + struct tagStIpsurxWol2Rule5PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule5PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw03 { + struct tagStIpsurxWol2Rule5PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule5PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw04 { + struct tagStIpsurxWol2Rule5PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule5PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw05 { + struct tagStIpsurxWol2Rule5PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule5PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw06 { + struct tagStIpsurxWol2Rule5PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule5PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw07 { + struct tagStIpsurxWol2Rule5PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule5PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw08 { + struct tagStIpsurxWol2Rule5PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule5PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw09 { + struct tagStIpsurxWol2Rule5PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule5PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw10 { + struct tagStIpsurxWol2Rule5PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule5PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw11 { + struct tagStIpsurxWol2Rule5PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule5PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw12 { + struct tagStIpsurxWol2Rule5PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule5PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw13 { + struct tagStIpsurxWol2Rule5PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule5PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw14 { + struct tagStIpsurxWol2Rule5PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule5PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw15 { + struct tagStIpsurxWol2Rule5PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule5PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw16 { + struct tagStIpsurxWol2Rule5PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule5PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw17 { + struct tagStIpsurxWol2Rule5PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule5PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw18 { + struct tagStIpsurxWol2Rule5PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule5PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw19 { + struct tagStIpsurxWol2Rule5PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule5PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw20 { + struct tagStIpsurxWol2Rule5PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule5PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw21 { + struct tagStIpsurxWol2Rule5PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule5PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw22 { + struct tagStIpsurxWol2Rule5PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule5PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw23 { + struct tagStIpsurxWol2Rule5PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule5PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw24 { + struct tagStIpsurxWol2Rule5PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule5PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw25 { + struct tagStIpsurxWol2Rule5PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule5PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw26 { + struct tagStIpsurxWol2Rule5PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule5PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw27 { + struct tagStIpsurxWol2Rule5PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule5PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw28 { + struct tagStIpsurxWol2Rule5PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule5PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw29 { + struct tagStIpsurxWol2Rule5PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule5PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw30 { + struct tagStIpsurxWol2Rule5PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule5PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw31 { + struct tagStIpsurxWol2Rule5PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule5PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW31_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw00 { + struct tagStIpsurxWol2Rule4PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule4PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw01 { + struct tagStIpsurxWol2Rule4PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule4PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw02 { + struct tagStIpsurxWol2Rule4PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule4PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw03 { + struct tagStIpsurxWol2Rule4PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule4PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw04 { + struct tagStIpsurxWol2Rule4PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule4PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw05 { + struct tagStIpsurxWol2Rule4PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule4PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw06 { + struct tagStIpsurxWol2Rule4PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule4PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw07 { + struct tagStIpsurxWol2Rule4PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule4PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw08 { + struct tagStIpsurxWol2Rule4PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule4PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw09 { + struct tagStIpsurxWol2Rule4PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule4PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw10 { + struct tagStIpsurxWol2Rule4PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule4PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw11 { + struct tagStIpsurxWol2Rule4PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule4PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw12 { + struct tagStIpsurxWol2Rule4PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule4PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw13 { + struct tagStIpsurxWol2Rule4PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule4PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw14 { + struct tagStIpsurxWol2Rule4PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule4PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw15 { + struct tagStIpsurxWol2Rule4PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule4PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw16 { + struct tagStIpsurxWol2Rule4PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule4PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw17 { + struct tagStIpsurxWol2Rule4PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule4PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw18 { + struct tagStIpsurxWol2Rule4PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule4PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw19 { + struct tagStIpsurxWol2Rule4PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule4PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw20 { + struct tagStIpsurxWol2Rule4PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule4PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw21 { + struct tagStIpsurxWol2Rule4PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule4PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw22 { + struct tagStIpsurxWol2Rule4PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule4PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw23 { + struct tagStIpsurxWol2Rule4PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule4PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw24 { + struct tagStIpsurxWol2Rule4PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule4PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw25 { + struct tagStIpsurxWol2Rule4PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule4PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw26 { + struct tagStIpsurxWol2Rule4PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule4PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw27 { + struct tagStIpsurxWol2Rule4PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule4PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw28 { + struct tagStIpsurxWol2Rule4PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule4PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw29 { + struct tagStIpsurxWol2Rule4PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule4PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw30 { + struct tagStIpsurxWol2Rule4PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule4PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw31 { + struct tagStIpsurxWol2Rule4PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule4PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW31_U; + + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw00 { + struct tagStIpsurxWol2Rule3PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule3PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw01 { + struct tagStIpsurxWol2Rule3PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule3PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw02 { + struct tagStIpsurxWol2Rule3PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule3PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw03 { + struct tagStIpsurxWol2Rule3PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule3PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw04 { + struct tagStIpsurxWol2Rule3PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule3PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw05 { + struct tagStIpsurxWol2Rule3PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule3PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw06 { + struct tagStIpsurxWol2Rule3PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule3PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw07 { + struct tagStIpsurxWol2Rule3PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule3PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw08 { + struct tagStIpsurxWol2Rule3PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule3PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw09 { + struct tagStIpsurxWol2Rule3PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule3PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw10 { + struct tagStIpsurxWol2Rule3PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule3PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw11 { + struct tagStIpsurxWol2Rule3PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule3PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw12 { + struct tagStIpsurxWol2Rule3PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule3PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw13 { + struct tagStIpsurxWol2Rule3PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule3PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw14 { + struct tagStIpsurxWol2Rule3PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule3PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw15 { + struct tagStIpsurxWol2Rule3PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule3PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw16 { + struct tagStIpsurxWol2Rule3PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule3PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw17 { + struct tagStIpsurxWol2Rule3PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule3PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw18 { + struct tagStIpsurxWol2Rule3PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule3PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw19 { + struct tagStIpsurxWol2Rule3PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule3PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw20 { + struct tagStIpsurxWol2Rule3PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule3PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw21 { + struct tagStIpsurxWol2Rule3PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule3PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw22 { + struct tagStIpsurxWol2Rule3PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule3PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw23 { + struct tagStIpsurxWol2Rule3PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule3PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw24 { + struct tagStIpsurxWol2Rule3PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule3PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw25 { + struct tagStIpsurxWol2Rule3PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule3PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw26 { + struct tagStIpsurxWol2Rule3PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule3PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw27 { + struct tagStIpsurxWol2Rule3PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule3PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw28 { + struct tagStIpsurxWol2Rule3PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule3PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw29 { + struct tagStIpsurxWol2Rule3PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule3PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw30 { + struct tagStIpsurxWol2Rule3PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule3PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw31 { + struct tagStIpsurxWol2Rule3PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule3PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW31_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw00 { + struct tagStIpsurxWol2Rule2PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule2PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw01 { + struct tagStIpsurxWol2Rule2PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule2PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw02 { + struct tagStIpsurxWol2Rule2PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule2PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw03 { + struct tagStIpsurxWol2Rule2PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule2PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw04 { + struct tagStIpsurxWol2Rule2PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule2PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw05 { + struct tagStIpsurxWol2Rule2PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule2PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw06 { + struct tagStIpsurxWol2Rule2PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule2PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw07 { + struct tagStIpsurxWol2Rule2PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule2PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw08 { + struct tagStIpsurxWol2Rule2PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule2PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw09 { + struct tagStIpsurxWol2Rule2PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule2PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw10 { + struct tagStIpsurxWol2Rule2PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule2PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw11 { + struct tagStIpsurxWol2Rule2PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule2PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw12 { + struct tagStIpsurxWol2Rule2PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule2PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw13 { + struct tagStIpsurxWol2Rule2PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule2PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw14 { + struct tagStIpsurxWol2Rule2PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule2PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw15 { + struct tagStIpsurxWol2Rule2PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule2PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw16 { + struct tagStIpsurxWol2Rule2PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule2PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw17 { + struct tagStIpsurxWol2Rule2PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule2PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw18 { + struct tagStIpsurxWol2Rule2PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule2PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw19 { + struct tagStIpsurxWol2Rule2PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule2PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw20 { + struct tagStIpsurxWol2Rule2PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule2PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw21 { + struct tagStIpsurxWol2Rule2PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule2PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw22 { + struct tagStIpsurxWol2Rule2PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule2PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw23 { + struct tagStIpsurxWol2Rule2PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule2PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw24 { + struct tagStIpsurxWol2Rule2PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule2PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw25 { + struct tagStIpsurxWol2Rule2PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule2PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw26 { + struct tagStIpsurxWol2Rule2PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule2PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw27 { + struct tagStIpsurxWol2Rule2PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule2PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw28 { + struct tagStIpsurxWol2Rule2PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule2PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw29 { + struct tagStIpsurxWol2Rule2PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule2PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw30 { + struct tagStIpsurxWol2Rule2PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule2PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw31 { + struct tagStIpsurxWol2Rule2PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule2PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW31_U; + + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw00 { + struct tagStIpsurxWol2Rule1PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule1PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw01 { + struct tagStIpsurxWol2Rule1PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule1PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw02 { + struct tagStIpsurxWol2Rule1PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule1PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw03 { + struct tagStIpsurxWol2Rule1PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule1PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw04 { + struct tagStIpsurxWol2Rule1PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule1PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw05 { + struct tagStIpsurxWol2Rule1PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule1PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw06 { + struct tagStIpsurxWol2Rule1PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule1PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw07 { + struct tagStIpsurxWol2Rule1PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule1PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw08 { + struct tagStIpsurxWol2Rule1PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule1PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw09 { + struct tagStIpsurxWol2Rule1PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule1PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw10 { + struct tagStIpsurxWol2Rule1PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule1PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw11 { + struct tagStIpsurxWol2Rule1PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule1PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw12 { + struct tagStIpsurxWol2Rule1PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule1PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw13 { + struct tagStIpsurxWol2Rule1PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule1PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw14 { + struct tagStIpsurxWol2Rule1PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule1PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw15 { + struct tagStIpsurxWol2Rule1PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule1PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw16 { + struct tagStIpsurxWol2Rule1PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule1PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw17 { + struct tagStIpsurxWol2Rule1PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule1PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw18 { + struct tagStIpsurxWol2Rule1PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule1PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw19 { + struct tagStIpsurxWol2Rule1PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule1PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw20 { + struct tagStIpsurxWol2Rule1PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule1PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw21 { + struct tagStIpsurxWol2Rule1PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule1PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw22 { + struct tagStIpsurxWol2Rule1PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule1PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw23 { + struct tagStIpsurxWol2Rule1PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule1PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw24 { + struct tagStIpsurxWol2Rule1PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule1PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw25 { + struct tagStIpsurxWol2Rule1PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule1PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw26 { + struct tagStIpsurxWol2Rule1PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule1PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw27 { + struct tagStIpsurxWol2Rule1PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule1PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw28 { + struct tagStIpsurxWol2Rule1PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule1PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw29 { + struct tagStIpsurxWol2Rule1PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule1PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw30 { + struct tagStIpsurxWol2Rule1PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule1PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw31 { + struct tagStIpsurxWol2Rule1PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule1PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW31_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw00 { + struct tagStIpsurxWol2Rule0PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule0PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw01 { + struct tagStIpsurxWol2Rule0PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule0PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw02 { + struct tagStIpsurxWol2Rule0PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule0PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw03 { + struct tagStIpsurxWol2Rule0PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule0PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw04 { + struct tagStIpsurxWol2Rule0PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule0PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw05 { + struct tagStIpsurxWol2Rule0PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule0PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw06 { + struct tagStIpsurxWol2Rule0PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule0PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw07 { + struct tagStIpsurxWol2Rule0PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule0PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw08 { + struct tagStIpsurxWol2Rule0PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule0PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw09 { + struct tagStIpsurxWol2Rule0PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule0PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw10 { + struct tagStIpsurxWol2Rule0PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule0PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw11 { + struct tagStIpsurxWol2Rule0PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule0PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw12 { + struct tagStIpsurxWol2Rule0PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule0PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw13 { + struct tagStIpsurxWol2Rule0PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule0PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw14 { + struct tagStIpsurxWol2Rule0PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule0PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw15 { + struct tagStIpsurxWol2Rule0PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule0PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw16 { + struct tagStIpsurxWol2Rule0PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule0PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw17 { + struct tagStIpsurxWol2Rule0PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule0PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw18 { + struct tagStIpsurxWol2Rule0PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule0PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw19 { + struct tagStIpsurxWol2Rule0PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule0PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw20 { + struct tagStIpsurxWol2Rule0PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule0PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw21 { + struct tagStIpsurxWol2Rule0PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule0PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw22 { + struct tagStIpsurxWol2Rule0PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule0PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw23 { + struct tagStIpsurxWol2Rule0PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule0PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw24 { + struct tagStIpsurxWol2Rule0PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule0PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw25 { + struct tagStIpsurxWol2Rule0PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule0PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw26 { + struct tagStIpsurxWol2Rule0PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule0PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw27 { + struct tagStIpsurxWol2Rule0PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule0PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw28 { + struct tagStIpsurxWol2Rule0PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule0PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw29 { + struct tagStIpsurxWol2Rule0PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule0PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw30 { + struct tagStIpsurxWol2Rule0PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule0PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw31 { + struct tagStIpsurxWol2Rule0PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule0PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW31_U; + + +/* ** + * Union name : IPSURX_LLI_TYPE7 + * @brief LLI报文TYPE7寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType7 { + struct tagStIpsurxLliType7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType7Vld : 1; /* * [16:16]LLI报文TYPE7 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType7 : 16; /* * [15:0]LLI报文Ethernet TYPE7。 */ +#else + unsigned int ipsurxLliType7 : 16; /* * [15:0]LLI报文Ethernet TYPE7。 */ + unsigned int ipsurxLliType7Vld : 1; /* * [16:16]LLI报文TYPE7 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE7_U; + +/* ** + * Union name : IPSURX_LLI_TYPE6 + * @brief LLI报文TYPE6寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType6 { + struct tagStIpsurxLliType6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType6Vld : 1; /* * [16:16]LLI报文TYPE6 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType6 : 16; /* * [15:0]LLI报文Ethernet TYPE6。 */ +#else + unsigned int ipsurxLliType6 : 16; /* * [15:0]LLI报文Ethernet TYPE6。 */ + unsigned int ipsurxLliType6Vld : 1; /* * [16:16]LLI报文TYPE6 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE6_U; + +/* ** + * Union name : IPSURX_LLI_TYPE5 + * @brief LLI报文TYPE5寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType5 { + struct tagStIpsurxLliType5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType5Vld : 1; /* * [16:16]LLI报文TYPE5 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType5 : 16; /* * [15:0]LLI报文Ethernet TYPE5。 */ +#else + unsigned int ipsurxLliType5 : 16; /* * [15:0]LLI报文Ethernet TYPE5。 */ + unsigned int ipsurxLliType5Vld : 1; /* * [16:16]LLI报文TYPE5 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE5_U; + +/* ** + * Union name : IPSURX_LLI_TYPE4 + * @brief LLI报文TYPE4寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType4 { + struct tagStIpsurxLliType4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType4Vld : 1; /* * [16:16]LLI报文TYPE4 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType4 : 16; /* * [15:0]LLI报文Ethernet TYPE4。 */ +#else + unsigned int ipsurxLliType4 : 16; /* * [15:0]LLI报文Ethernet TYPE4。 */ + unsigned int ipsurxLliType4Vld : 1; /* * [16:16]LLI报文TYPE4 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE4_U; + +/* ** + * Union name : IPSURX_LLI_TYPE3 + * @brief LLI报文TYPE3寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType3 { + struct tagStIpsurxLliType3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType3Vld : 1; /* * [16:16]LLI报文TYPE3 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType3 : 16; /* * [15:0]LLI报文Ethernet TYPE3。 */ +#else + unsigned int ipsurxLliType3 : 16; /* * [15:0]LLI报文Ethernet TYPE3。 */ + unsigned int ipsurxLliType3Vld : 1; /* * [16:16]LLI报文TYPE3 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE3_U; + +/* ** + * Union name : IPSURX_LLI_TYPE2 + * @brief LLI报文TYPE2寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType2 { + struct tagStIpsurxLliType2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType2Vld : 1; /* * [16:16]LLI报文TYPE2 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType2 : 16; /* * [15:0]LLI报文Ethernet TYPE2。 */ +#else + unsigned int ipsurxLliType2 : 16; /* * [15:0]LLI报文Ethernet TYPE2。 */ + unsigned int ipsurxLliType2Vld : 1; /* * [16:16]LLI报文TYPE2 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE2_U; + +/* ** + * Union name : IPSURX_LLI_TYPE1 + * @brief LLI报文TYPE1寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType1 { + struct tagStIpsurxLliType1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType1Vld : 1; /* * [16:16]LLI报文TYPE1 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType1 : 16; /* * [15:0]LLI报文Ethernet TYPE1。 */ +#else + unsigned int ipsurxLliType1 : 16; /* * [15:0]LLI报文Ethernet TYPE1。 */ + unsigned int ipsurxLliType1Vld : 1; /* * [16:16]LLI报文TYPE1 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE1_U; + +/* ** + * Union name : IPSURX_LLI_TYPE0 + * @brief LLI报文TYPE0寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType0 { + struct tagStIpsurxLliType0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType0Vld : 1; /* * [16:16]LLI报文TYPE0 VALID信号。1'b1：VALID；1'b0: INVALID。 */ + unsigned int ipsurxLliType0 : 16; /* * [15:0]LLI报文Ethernet TYPE0。 */ +#else + unsigned int ipsurxLliType0 : 16; /* * [15:0]LLI报文Ethernet TYPE0。 */ + unsigned int ipsurxLliType0Vld : 1; /* * [16:16]LLI报文TYPE0 VALID信号。1'b1：VALID；1'b0: INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE0_U; + +/* ** + * Union name : IPSURX_MAC_TB_CTRL + * @brief MAC Table控制寄存器 + * Description: + */ +typedef union tagUnIpsurxMacTbCtrl { + struct tagStIpsurxMacTbCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 24; /* * [31:8]reserved. */ + unsigned int reserved1 : 5; /* * [7:3] */ + unsigned int ipsurxFicMacTbEn : 1; /* * [2:2]通道属性为FIC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2MacTbEn : 1; /* * [1:1]通道属性为HG2，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxMacMacTbEn : 1; /* * [0:0]通道属性为MAC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ +#else + unsigned int ipsurxMacMacTbEn : 1; /* * [0:0]通道属性为MAC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2MacTbEn : 1; /* * [1:1]通道属性为HG2，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxFicMacTbEn : 1; /* * [2:2]通道属性为FIC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int reserved1 : 5; /* * [7:3] */ + unsigned int reserved0 : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_CTRL_U; + +/* ** + * Union name : IPSURX_PORT_ERID7 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid7 { + struct tagStIpsurxPortErid7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry15Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry15Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry14Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry14Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry14Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry14Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry15Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry15Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID7_U; + +/* ** + * Union name : IPSURX_PORT_ERID6 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid6 { + struct tagStIpsurxPortErid6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry13Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry13Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry12Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry12Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry12Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry12Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry13Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry13Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID6_U; + +/* ** + * Union name : IPSURX_PORT_ERID5 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid5 { + struct tagStIpsurxPortErid5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry11Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry11Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry10Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry10Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry10Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry10Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry11Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry11Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID5_U; + +/* ** + * Union name : IPSURX_PORT_ERID4 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid4 { + struct tagStIpsurxPortErid4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry9Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry9Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry8Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry8Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry8Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry8Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry9Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry9Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID4_U; + +/* ** + * Union name : IPSURX_PORT_ERID3 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid3 { + struct tagStIpsurxPortErid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry7Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry7Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry6Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry6Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry6Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry6Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry7Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry7Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID3_U; + +/* ** + * Union name : IPSURX_PORT_ERID2 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid2 { + struct tagStIpsurxPortErid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry5Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry5Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry4Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry4Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry4Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry4Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry5Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry5Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID2_U; + +/* ** + * Union name : IPSURX_PORT_ERID1 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid1 { + struct tagStIpsurxPortErid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry3Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry3Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry2Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry2Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry2Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry2Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry3Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry3Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID1_U; + +/* ** + * Union name : IPSURX_PORT_ERID0 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid0 { + struct tagStIpsurxPortErid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry1Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry1Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry0Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry0Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry0Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry0Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry1Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry1Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID0_U; + + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY63_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry63H { + struct tagStIpsurxMacTbEntry63H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry63Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry63MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry63MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry63Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY63_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY63_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry63M { + struct tagStIpsurxMacTbEntry63M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry63MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry63MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY63_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY63_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry63L { + struct tagStIpsurxMacTbEntry63L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry63VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry63Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry63Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry63Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry63Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry63VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY63_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY62_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry62H { + struct tagStIpsurxMacTbEntry62H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry62Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry62MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry62MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry62Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY62_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY62_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry62M { + struct tagStIpsurxMacTbEntry62M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry62MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry62MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY62_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY62_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry62L { + struct tagStIpsurxMacTbEntry62L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry62VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry62Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry62Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry62Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry62Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry62VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY62_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY61_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry61H { + struct tagStIpsurxMacTbEntry61H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry61Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry61MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry61MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry61Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY61_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY61_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry61M { + struct tagStIpsurxMacTbEntry61M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry61MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry61MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY61_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY61_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry61L { + struct tagStIpsurxMacTbEntry61L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry61VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry61Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry61Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry61Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry61Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry61VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY61_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY60_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry60H { + struct tagStIpsurxMacTbEntry60H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry60Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry60MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry60MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry60Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY60_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY60_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry60M { + struct tagStIpsurxMacTbEntry60M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry60MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry60MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY60_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY60_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry60L { + struct tagStIpsurxMacTbEntry60L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry60VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry60Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry60Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry60Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry60Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry60VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY60_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY59_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry59H { + struct tagStIpsurxMacTbEntry59H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry59Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry59MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry59MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry59Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY59_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY59_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry59M { + struct tagStIpsurxMacTbEntry59M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry59MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry59MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY59_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY59_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry59L { + struct tagStIpsurxMacTbEntry59L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry59VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry59Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry59Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry59Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry59Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry59VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY59_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY58_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry58H { + struct tagStIpsurxMacTbEntry58H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry58Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry58MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry58MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry58Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY58_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY58_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry58M { + struct tagStIpsurxMacTbEntry58M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry58MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry58MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY58_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY58_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry58L { + struct tagStIpsurxMacTbEntry58L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry58VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry58Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry58Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry58Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry58Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry58VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY58_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY57_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry57H { + struct tagStIpsurxMacTbEntry57H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry57Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry57MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry57MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry57Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY57_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY57_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry57M { + struct tagStIpsurxMacTbEntry57M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry57MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry57MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY57_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY57_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry57L { + struct tagStIpsurxMacTbEntry57L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry57VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry57Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry57Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry57Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry57Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry57VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY57_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY56_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry56H { + struct tagStIpsurxMacTbEntry56H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry56Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry56MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry56MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry56Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY56_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY56_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry56M { + struct tagStIpsurxMacTbEntry56M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry56MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry56MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY56_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY56_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry56L { + struct tagStIpsurxMacTbEntry56L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry56VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry56Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry56Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry56Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry56Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry56VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY56_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY55_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry55H { + struct tagStIpsurxMacTbEntry55H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry55Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry55MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry55MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry55Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY55_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY55_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry55M { + struct tagStIpsurxMacTbEntry55M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry55MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry55MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY55_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY55_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry55L { + struct tagStIpsurxMacTbEntry55L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry55VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry55Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry55Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry55Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry55Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry55VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY55_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY54_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry54H { + struct tagStIpsurxMacTbEntry54H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry54Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry54MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry54MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry54Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY54_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY54_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry54M { + struct tagStIpsurxMacTbEntry54M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry54MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry54MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY54_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY54_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry54L { + struct tagStIpsurxMacTbEntry54L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry54VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry54Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry54Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry54Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry54Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry54VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY54_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY53_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry53H { + struct tagStIpsurxMacTbEntry53H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry53Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry53MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry53MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry53Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY53_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY53_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry53M { + struct tagStIpsurxMacTbEntry53M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry53MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry53MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY53_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY53_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry53L { + struct tagStIpsurxMacTbEntry53L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry53VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry53Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry53Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry53Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry53Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry53VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY53_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY52_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry52H { + struct tagStIpsurxMacTbEntry52H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry52Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry52MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry52MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry52Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY52_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY52_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry52M { + struct tagStIpsurxMacTbEntry52M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry52MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry52MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY52_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY52_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry52L { + struct tagStIpsurxMacTbEntry52L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry52VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry52Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry52Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry52Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry52Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry52VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY52_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY51_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry51H { + struct tagStIpsurxMacTbEntry51H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry51Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry51MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry51MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry51Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY51_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY51_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry51M { + struct tagStIpsurxMacTbEntry51M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry51MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry51MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY51_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY51_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry51L { + struct tagStIpsurxMacTbEntry51L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry51VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry51Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry51Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry51Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry51Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry51VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY51_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY50_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry50H { + struct tagStIpsurxMacTbEntry50H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry50Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry50MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry50MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry50Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY50_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY50_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry50M { + struct tagStIpsurxMacTbEntry50M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry50MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry50MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY50_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY50_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry50L { + struct tagStIpsurxMacTbEntry50L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry50VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry50Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry50Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry50Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry50Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry50VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY50_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY49_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry49H { + struct tagStIpsurxMacTbEntry49H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry49Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry49MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry49MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry49Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY49_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY49_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry49M { + struct tagStIpsurxMacTbEntry49M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry49MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry49MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY49_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY49_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry49L { + struct tagStIpsurxMacTbEntry49L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry49VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry49Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry49Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry49Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry49Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry49VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY49_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY48_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry48H { + struct tagStIpsurxMacTbEntry48H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry48Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry48MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry48MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry48Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY48_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY48_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry48M { + struct tagStIpsurxMacTbEntry48M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry48MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry48MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY48_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY48_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry48L { + struct tagStIpsurxMacTbEntry48L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry48VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry48Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry48Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry48Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry48Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry48VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY48_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY47_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry47H { + struct tagStIpsurxMacTbEntry47H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry47Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry47MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry47MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry47Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY47_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY47_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry47M { + struct tagStIpsurxMacTbEntry47M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry47MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry47MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY47_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY47_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry47L { + struct tagStIpsurxMacTbEntry47L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry47VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry47Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry47Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry47Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry47Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry47VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY47_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY46_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry46H { + struct tagStIpsurxMacTbEntry46H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry46Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry46MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry46MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry46Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY46_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY46_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry46M { + struct tagStIpsurxMacTbEntry46M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry46MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry46MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY46_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY46_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry46L { + struct tagStIpsurxMacTbEntry46L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry46VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry46Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry46Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry46Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry46Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry46VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY46_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY45_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry45H { + struct tagStIpsurxMacTbEntry45H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry45Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry45MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry45MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry45Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY45_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY45_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry45M { + struct tagStIpsurxMacTbEntry45M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry45MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry45MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY45_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY45_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry45L { + struct tagStIpsurxMacTbEntry45L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry45VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry45Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry45Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry45Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry45Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry45VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY45_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY44_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry44H { + struct tagStIpsurxMacTbEntry44H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry44Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry44MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry44MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry44Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY44_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY44_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry44M { + struct tagStIpsurxMacTbEntry44M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry44MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry44MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY44_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY44_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry44L { + struct tagStIpsurxMacTbEntry44L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry44VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry44Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry44Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry44Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry44Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry44VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY44_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY43_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry43H { + struct tagStIpsurxMacTbEntry43H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry43Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry43MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry43MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry43Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY43_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY43_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry43M { + struct tagStIpsurxMacTbEntry43M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry43MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry43MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY43_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY43_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry43L { + struct tagStIpsurxMacTbEntry43L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry43VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry43Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry43Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry43Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry43Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry43VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY43_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY42_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry42H { + struct tagStIpsurxMacTbEntry42H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry42Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry42MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry42MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry42Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY42_H_U; + + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY42_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry42M { + struct tagStIpsurxMacTbEntry42M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry42MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry42MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY42_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY42_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry42L { + struct tagStIpsurxMacTbEntry42L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry42VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry42Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry42Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry42Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry42Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry42VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY42_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY41_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry41H { + struct tagStIpsurxMacTbEntry41H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry41Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry41MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry41MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry41Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY41_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY41_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry41M { + struct tagStIpsurxMacTbEntry41M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry41MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry41MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY41_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY41_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry41L { + struct tagStIpsurxMacTbEntry41L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry41VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry41Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry41Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry41Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry41Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry41VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY41_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY40_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry40H { + struct tagStIpsurxMacTbEntry40H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry40Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry40MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry40MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry40Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY40_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY40_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry40M { + struct tagStIpsurxMacTbEntry40M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry40MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry40MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY40_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY40_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry40L { + struct tagStIpsurxMacTbEntry40L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry40VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry40Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry40Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry40Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry40Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry40VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY40_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY39_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry39H { + struct tagStIpsurxMacTbEntry39H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry39Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry39MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry39MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry39Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY39_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY39_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry39M { + struct tagStIpsurxMacTbEntry39M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry39MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry39MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY39_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY39_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry39L { + struct tagStIpsurxMacTbEntry39L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry39VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry39Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry39Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry39Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry39Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry39VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY39_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY38_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry38H { + struct tagStIpsurxMacTbEntry38H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry38Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry38MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry38MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry38Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY38_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY38_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry38M { + struct tagStIpsurxMacTbEntry38M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry38MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry38MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY38_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY38_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry38L { + struct tagStIpsurxMacTbEntry38L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry38VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry38Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry38Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry38Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry38Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry38VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY38_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY37_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry37H { + struct tagStIpsurxMacTbEntry37H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry37Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry37MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry37MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry37Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY37_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY37_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry37M { + struct tagStIpsurxMacTbEntry37M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry37MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry37MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY37_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY37_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry37L { + struct tagStIpsurxMacTbEntry37L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry37VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry37Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry37Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry37Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry37Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry37VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY37_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY36_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry36H { + struct tagStIpsurxMacTbEntry36H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry36Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry36MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry36MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry36Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY36_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY36_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry36M { + struct tagStIpsurxMacTbEntry36M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry36MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry36MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY36_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY36_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry36L { + struct tagStIpsurxMacTbEntry36L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry36VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry36Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry36Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry36Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry36Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry36VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY36_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY35_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry35H { + struct tagStIpsurxMacTbEntry35H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry35Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry35MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry35MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry35Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY35_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY35_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry35M { + struct tagStIpsurxMacTbEntry35M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry35MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry35MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY35_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY35_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry35L { + struct tagStIpsurxMacTbEntry35L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry35VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry35Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry35Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry35Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry35Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry35VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY35_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY34_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry34H { + struct tagStIpsurxMacTbEntry34H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry34Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry34MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry34MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry34Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY34_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY34_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry34M { + struct tagStIpsurxMacTbEntry34M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry34MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry34MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY34_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY34_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry34L { + struct tagStIpsurxMacTbEntry34L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry34VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry34Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry34Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry34Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry34Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry34VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY34_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY33_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry33H { + struct tagStIpsurxMacTbEntry33H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry33Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry33MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry33MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry33Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY33_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY33_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry33M { + struct tagStIpsurxMacTbEntry33M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry33MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry33MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY33_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY33_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry33L { + struct tagStIpsurxMacTbEntry33L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry33VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry33Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry33Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry33Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry33Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry33VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY33_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY32_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry32H { + struct tagStIpsurxMacTbEntry32H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry32Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry32MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry32MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry32Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY32_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY32_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry32M { + struct tagStIpsurxMacTbEntry32M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry32MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry32MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY32_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY32_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry32L { + struct tagStIpsurxMacTbEntry32L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry32VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry32Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry32Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry32Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry32Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry32VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY32_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY31_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry31H { + struct tagStIpsurxMacTbEntry31H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry31Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry31MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry31MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry31Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY31_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY31_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry31M { + struct tagStIpsurxMacTbEntry31M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry31MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry31MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY31_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY31_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry31L { + struct tagStIpsurxMacTbEntry31L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry31VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry31Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry31Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry31Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry31Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry31VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY31_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY30_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry30H { + struct tagStIpsurxMacTbEntry30H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry30Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry30MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry30MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry30Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY30_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY30_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry30M { + struct tagStIpsurxMacTbEntry30M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry30MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry30MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY30_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY30_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry30L { + struct tagStIpsurxMacTbEntry30L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry30VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry30Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry30Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry30Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry30Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry30VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY30_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY29_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry29H { + struct tagStIpsurxMacTbEntry29H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry29Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry29MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry29MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry29Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY29_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY29_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry29M { + struct tagStIpsurxMacTbEntry29M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry29MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry29MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY29_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY29_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry29L { + struct tagStIpsurxMacTbEntry29L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry29VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry29Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry29Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry29Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry29Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry29VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY29_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY28_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry28H { + struct tagStIpsurxMacTbEntry28H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry28Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry28MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry28MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry28Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY28_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY28_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry28M { + struct tagStIpsurxMacTbEntry28M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry28MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry28MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY28_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY28_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry28L { + struct tagStIpsurxMacTbEntry28L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry28VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry28Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry28Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry28Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry28Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry28VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY28_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY27_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry27H { + struct tagStIpsurxMacTbEntry27H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry27Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry27MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry27MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry27Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY27_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY27_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry27M { + struct tagStIpsurxMacTbEntry27M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry27MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry27MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY27_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY27_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry27L { + struct tagStIpsurxMacTbEntry27L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry27VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry27Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry27Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry27Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry27Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry27VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY27_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY26_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry26H { + struct tagStIpsurxMacTbEntry26H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry26Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry26MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry26MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry26Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY26_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY26_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry26M { + struct tagStIpsurxMacTbEntry26M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry26MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry26MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY26_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY26_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry26L { + struct tagStIpsurxMacTbEntry26L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry26VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry26Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry26Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry26Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry26Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry26VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY26_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY25_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry25H { + struct tagStIpsurxMacTbEntry25H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry25Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry25MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry25MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry25Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY25_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY25_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry25M { + struct tagStIpsurxMacTbEntry25M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry25MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry25MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY25_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY25_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry25L { + struct tagStIpsurxMacTbEntry25L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry25VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry25Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry25Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry25Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry25Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry25VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY25_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY24_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry24H { + struct tagStIpsurxMacTbEntry24H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry24Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry24MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry24MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry24Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY24_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY24_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry24M { + struct tagStIpsurxMacTbEntry24M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry24MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry24MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY24_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY24_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry24L { + struct tagStIpsurxMacTbEntry24L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry24VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry24Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry24Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry24Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry24Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry24VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY24_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY23_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry23H { + struct tagStIpsurxMacTbEntry23H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry23Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry23MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry23MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry23Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY23_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY23_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry23M { + struct tagStIpsurxMacTbEntry23M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry23MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry23MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY23_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY23_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry23L { + struct tagStIpsurxMacTbEntry23L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry23VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry23Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry23Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry23Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry23Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry23VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY23_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY22_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry22H { + struct tagStIpsurxMacTbEntry22H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry22Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry22MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry22MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry22Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY22_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY22_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry22M { + struct tagStIpsurxMacTbEntry22M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry22MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry22MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY22_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY22_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry22L { + struct tagStIpsurxMacTbEntry22L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry22VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry22Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry22Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry22Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry22Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry22VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY22_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY21_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry21H { + struct tagStIpsurxMacTbEntry21H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry21Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry21MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry21MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry21Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY21_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY21_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry21M { + struct tagStIpsurxMacTbEntry21M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry21MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry21MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY21_M_U; + + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY21_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry21L { + struct tagStIpsurxMacTbEntry21L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry21VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry21Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry21Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry21Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry21Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry21VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY21_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY20_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry20H { + struct tagStIpsurxMacTbEntry20H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry20Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry20MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry20MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry20Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY20_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY20_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry20M { + struct tagStIpsurxMacTbEntry20M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry20MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry20MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY20_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY20_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry20L { + struct tagStIpsurxMacTbEntry20L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry20VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry20Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry20Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry20Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry20Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry20VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY20_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY19_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry19H { + struct tagStIpsurxMacTbEntry19H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry19Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry19MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry19MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry19Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY19_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY19_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry19M { + struct tagStIpsurxMacTbEntry19M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry19MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry19MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY19_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY19_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry19L { + struct tagStIpsurxMacTbEntry19L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry19VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry19Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry19Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry19Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry19Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry19VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY19_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY18_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry18H { + struct tagStIpsurxMacTbEntry18H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry18Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry18MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry18MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry18Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY18_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY18_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry18M { + struct tagStIpsurxMacTbEntry18M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry18MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry18MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY18_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY18_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry18L { + struct tagStIpsurxMacTbEntry18L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry18VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry18Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry18Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry18Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry18Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry18VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY18_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY17_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry17H { + struct tagStIpsurxMacTbEntry17H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry17Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry17MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry17MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry17Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY17_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY17_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry17M { + struct tagStIpsurxMacTbEntry17M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry17MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry17MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY17_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY17_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry17L { + struct tagStIpsurxMacTbEntry17L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry17VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry17Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry17Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry17Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry17Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry17VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY17_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY16_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry16H { + struct tagStIpsurxMacTbEntry16H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry16Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry16MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry16MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry16Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY16_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY16_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry16M { + struct tagStIpsurxMacTbEntry16M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry16MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry16MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY16_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY16_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry16L { + struct tagStIpsurxMacTbEntry16L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry16VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry16Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry16Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry16Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry16Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry16VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY16_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY15_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry15H { + struct tagStIpsurxMacTbEntry15H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry15Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry15MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry15MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry15Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY15_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY15_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry15M { + struct tagStIpsurxMacTbEntry15M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry15MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry15MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY15_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY15_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry15L { + struct tagStIpsurxMacTbEntry15L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry15VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry15Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry15Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry15Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry15Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry15VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY15_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY14_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry14H { + struct tagStIpsurxMacTbEntry14H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry14Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry14MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry14MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry14Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY14_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY14_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry14M { + struct tagStIpsurxMacTbEntry14M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry14MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry14MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY14_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY14_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry14L { + struct tagStIpsurxMacTbEntry14L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry14VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry14Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry14Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry14Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry14Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry14VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY14_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY13_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry13H { + struct tagStIpsurxMacTbEntry13H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry13Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry13MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry13MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry13Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY13_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY13_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry13M { + struct tagStIpsurxMacTbEntry13M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry13MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry13MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY13_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY13_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry13L { + struct tagStIpsurxMacTbEntry13L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry13VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry13Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry13Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry13Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry13Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry13VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY13_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY12_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry12H { + struct tagStIpsurxMacTbEntry12H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry12Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry12MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry12MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry12Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY12_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY12_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry12M { + struct tagStIpsurxMacTbEntry12M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry12MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry12MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY12_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY12_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry12L { + struct tagStIpsurxMacTbEntry12L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry12VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry12Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry12Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry12Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry12Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry12VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY12_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY11_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry11H { + struct tagStIpsurxMacTbEntry11H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry11Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry11MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry11MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry11Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY11_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY11_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry11M { + struct tagStIpsurxMacTbEntry11M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry11MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry11MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY11_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY11_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry11L { + struct tagStIpsurxMacTbEntry11L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry11VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry11Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry11Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry11Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry11Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry11VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY11_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY10_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry10H { + struct tagStIpsurxMacTbEntry10H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry10Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry10MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry10MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry10Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY10_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY10_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry10M { + struct tagStIpsurxMacTbEntry10M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry10MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry10MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY10_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY10_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry10L { + struct tagStIpsurxMacTbEntry10L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry10VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry10Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry10Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry10Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry10Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry10VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY10_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY9_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry9H { + struct tagStIpsurxMacTbEntry9H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry9Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry9MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry9MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry9Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY9_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY9_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry9M { + struct tagStIpsurxMacTbEntry9M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry9MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry9MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY9_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY9_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry9L { + struct tagStIpsurxMacTbEntry9L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry9VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry9Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry9Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry9Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry9Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry9VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY9_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY8_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry8H { + struct tagStIpsurxMacTbEntry8H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry8Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry8MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry8MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry8Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY8_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY8_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry8M { + struct tagStIpsurxMacTbEntry8M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry8MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry8MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY8_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY8_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry8L { + struct tagStIpsurxMacTbEntry8L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry8VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry8Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry8Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry8Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry8Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry8VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY8_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY7_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry7H { + struct tagStIpsurxMacTbEntry7H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry7Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry7MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry7MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry7Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY7_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY7_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry7M { + struct tagStIpsurxMacTbEntry7M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry7MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry7MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY7_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY7_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry7L { + struct tagStIpsurxMacTbEntry7L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry7VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry7Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry7Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry7Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry7Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry7VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY7_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY6_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry6H { + struct tagStIpsurxMacTbEntry6H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry6Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry6MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry6MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry6Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY6_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY6_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry6M { + struct tagStIpsurxMacTbEntry6M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry6MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry6MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY6_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY6_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry6L { + struct tagStIpsurxMacTbEntry6L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry6VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry6Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry6Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry6Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry6Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry6VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY6_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY5_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry5H { + struct tagStIpsurxMacTbEntry5H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry5Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry5MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry5MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry5Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY5_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY5_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry5M { + struct tagStIpsurxMacTbEntry5M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry5MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry5MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY5_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY5_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry5L { + struct tagStIpsurxMacTbEntry5L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry5VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry5Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry5Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry5Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry5Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry5VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY5_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY4_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry4H { + struct tagStIpsurxMacTbEntry4H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry4Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry4MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry4MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry4Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY4_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY4_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry4M { + struct tagStIpsurxMacTbEntry4M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry4MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry4MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY4_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY4_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry4L { + struct tagStIpsurxMacTbEntry4L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry4VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry4Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry4Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry4Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry4Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry4VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY4_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY3_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry3H { + struct tagStIpsurxMacTbEntry3H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry3Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry3MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry3MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry3Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY3_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY3_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry3M { + struct tagStIpsurxMacTbEntry3M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry3MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry3MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY3_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY3_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry3L { + struct tagStIpsurxMacTbEntry3L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry3VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry3Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry3Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry3Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry3Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry3VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY3_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY2_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry2H { + struct tagStIpsurxMacTbEntry2H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry2Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry2MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry2MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry2Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY2_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY2_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry2M { + struct tagStIpsurxMacTbEntry2M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry2MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry2MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY2_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY2_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry2L { + struct tagStIpsurxMacTbEntry2L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry2VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry2Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry2Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry2Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry2Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry2VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY2_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY1_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry1H { + struct tagStIpsurxMacTbEntry1H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry1Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry1MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry1MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry1Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY1_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY1_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry1M { + struct tagStIpsurxMacTbEntry1M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry1MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry1MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY1_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY1_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry1L { + struct tagStIpsurxMacTbEntry1L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry1VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry1Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry1Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry1Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry1Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry1VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY1_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY0_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry0H { + struct tagStIpsurxMacTbEntry0H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry0Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry0MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry0MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry0Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY0_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY0_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry0M { + struct tagStIpsurxMacTbEntry0M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry0MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry0MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY0_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY0_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry0L { + struct tagStIpsurxMacTbEntry0L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry0VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry0Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry0Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry0Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry0Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry0VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY0_L_U; + + +/* ** + * Union name : IPSURX_UNCRT_ERR_CTRL + * @brief IPSURX致命错误控制寄存器 + * Description: + */ +typedef union tagUnIpsurxUncrtErrCtrl { + struct tagStIpsurxUncrtErrCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17]reserved. */ + unsigned int ipsurxUncrtErrCtrl : 1; /* * + [16:16]1'b1：允许IPSURX模块产生致命错误；1'b0：不允许IPSURX模块产生致命错误。 + */ + unsigned int ipsurxTcamUncrtErrCtrl : 1; /* * [15:15]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTcamArtUncrtErrCtrl : 1; /* * [14:14]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTptUncrtErrCtrl : 1; /* * [13:13]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqContext0UncrtErrCtrl : 1; /* * [12:12]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int ipsurxRenqContext1UncrtErrCtrl : 1; /* * [11:11]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int reserved1 : 1; /* * [10:10] */ + unsigned int ipsurxRenqOfUncrtErrCtrl : 1; /* * [9:9]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqIfUncrtErrCtrl : 1; /* * [8:8]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int reserved3 : 1; /* * [6:6] */ + unsigned int ipsurxLcvFifoUncrtErrCtrl : 1; /* * [5:5]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvppContextUncrtErrCtrl : 1; /* * [4:4]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxPpcRamUncrtCtrl : 1; /* * [3:3]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqOfifoOvflCtrl : 1; /* * [2:2]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqIfifoOvflCtrl : 1; /* * [1:1]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvFifoOvflCtrl : 1; /* * [0:0]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ +#else + unsigned int ipsurxLcvFifoOvflCtrl : 1; /* * [0:0]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqIfifoOvflCtrl : 1; /* * [1:1]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqOfifoOvflCtrl : 1; /* * [2:2]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxPpcRamUncrtCtrl : 1; /* * [3:3]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvppContextUncrtErrCtrl : 1; /* * [4:4]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvFifoUncrtErrCtrl : 1; /* * [5:5]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int reserved3 : 1; /* * [6:6] */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxRenqIfUncrtErrCtrl : 1; /* * [8:8]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqOfUncrtErrCtrl : 1; /* * [9:9]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int reserved1 : 1; /* * [10:10] */ + unsigned int ipsurxRenqContext1UncrtErrCtrl : 1; /* * [11:11]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int ipsurxRenqContext0UncrtErrCtrl : 1; /* * [12:12]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int ipsurxTptUncrtErrCtrl : 1; /* * [13:13]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTcamArtUncrtErrCtrl : 1; /* * [14:14]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTcamUncrtErrCtrl : 1; /* * [15:15]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxUncrtErrCtrl : 1; /* * + [16:16]1'b1：允许IPSURX模块产生致命错误；1'b0：不允许IPSURX模块产生致命错误。 + */ + unsigned int reserved0 : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_UNCRT_ERR_CTRL_U; + +/* ** + * Union name : IPSURX_FIFO_TH + * @brief IPSURX FIFO门限寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoTh { + struct tagStIpsurxFifoTh { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int ipsurxRenqOfBpTh : 5; /* * [28:24]RENQ模块输出FIFO的反压门限。建议不要修改。可配置范围：5'd18 -- + 5'd24. */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxRenqIfBpTh : 6; /* * [21:16]RENQ模块输入FIFO反压门限。建议不要修改。可配置范围:6'd18 -- + * 6'd22. + */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxLcvFifoBpTh : 7; /* * [14:8]LCV模块输入FIFO反压门限。建议不要修改。可配置范围: 7'd30 -- + * 7'd44. + */ + unsigned int reserved3 : 2; /* * [7:6] */ + unsigned int ipsurxRenqOfAemptyTh : 2; /* * [5:4]RENQ模块输出FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxRenqIfAemptyTh : 2; /* * [3:2]RENQ模块输入FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxLcvFifoAemptyTh : 2; /* * [1:0]LCV模块输入FIFO几乎空门限。建议不要修改。 */ +#else + unsigned int ipsurxLcvFifoAemptyTh : 2; /* * [1:0]LCV模块输入FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxRenqIfAemptyTh : 2; /* * [3:2]RENQ模块输入FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxRenqOfAemptyTh : 2; /* * [5:4]RENQ模块输出FIFO几乎空门限。建议不要修改。 */ + unsigned int reserved3 : 2; /* * [7:6] */ + unsigned int ipsurxLcvFifoBpTh : 7; /* * [14:8]LCV模块输入FIFO反压门限。建议不要修改。可配置范围: 7'd30 -- + * 7'd44. + */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxRenqIfBpTh : 6; /* * [21:16]RENQ模块输入FIFO反压门限。建议不要修改。可配置范围:6'd18 -- + * 6'd22. + */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxRenqOfBpTh : 5; /* * [28:24]RENQ模块输出FIFO的反压门限。建议不要修改。可配置范围：5'd18 -- + 5'd24. */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_TH_U; + +/* ** + * Union name : IPSURX_RAMMOD_CTRL + * @brief IPSURX模块RAM MOD控制寄存器 + * Description: + */ +typedef union tagUnIpsurxRammodCtrl { + struct tagStIpsurxRammodCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21] */ + unsigned int ipsurxMemPowerModeCtrl : 6; /* * [20:15]建议不要修改。 */ + unsigned int ipsurxSpRamTmodCtrl : 7; /* * [14:8]建议不要修改。 */ + unsigned int ipsurxTpRamTmodCtrl : 8; /* * [7:0]建议不要修改。 */ +#else + unsigned int ipsurxTpRamTmodCtrl : 8; /* * [7:0]建议不要修改。 */ + unsigned int ipsurxSpRamTmodCtrl : 7; /* * [14:8]建议不要修改。 */ + unsigned int ipsurxMemPowerModeCtrl : 6; /* * [20:15]建议不要修改。 */ + unsigned int reserved : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RAMMOD_CTRL_U; + +/* ** + * Union name : IPSURX_RAM_ERR_CHK_BYPASS + * @brief IPSURX模块RAM错误检查BYPASS寄存器 + * Description: + */ +typedef union tagUnIpsurxRamErrChkBypass { + struct tagStIpsurxRamErrChkBypass { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxRamErrChkBypass : 1; /* * [0:0]1'b0：使能RAM ECC校验；1'b1：不使能RAM ECC校验。 */ +#else + unsigned int ipsurxRamErrChkBypass : 1; /* * [0:0]1'b0：使能RAM ECC校验；1'b1：不使能RAM ECC校验。 */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RAM_ERR_CHK_BYPASS_U; + +/* ** + * Union name : IPSURX_RAM_ERR_INJ + * @brief IPSURX模块RAM错误注入寄存器 + * Description: + */ +typedef union tagUnIpsurxRamErrInj { + struct tagStIpsurxRamErrInj { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]保留 */ + unsigned int ipsurxRenqOfRamUncrtErrInj : 1; /* * [27:27]RENQ Output FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqOfRamCrtErrInj : 1; /* * [26:26]RENQ Output FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamUncrtErrInj : 1; /* * [25:25]RENQ CONTEXT1 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamCrtErrInj : 1; /* * [24:24]RENQ CONTEXT1 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamUncrtErrInj : 1; /* * [23:23]RENQ CONTEXT0 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamCrtErrInj : 1; /* * [22:22]RENQ CONTEXT0 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqIfRamUncrtErrInj : 1; /* * [21:21]RENQ Input FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqIfRamCrtErrInj : 1; /* * [20:20]RENQ Input FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int reserved1 : 8; /* * [19:12] */ + unsigned int ipsurxLcvContextRamUncrtErrInj : 1; /* * [11:11]LCV CONTEXT + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvContextRamCrtErrInj : 1; /* * [10:10]LCV CONTEXT + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvFifoRamUncrtErrInj : 1; /* * [9:9]LCV FIFO RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 + */ + unsigned int ipsurxLcvFifoRamCrtErrInj : 1; /* * [8:8]LCV FIFO RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramUncrtErrInj : 1; /* * [7:7]PPC DATA RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramCrtErrInj : 1; /* * [6:6]PPC DATA RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptUncrtErrInj : 1; /* * [5:5]TCP Port Table RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptCrtErrInj : 1; /* * [4:4]TCP Port Table RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtUncrtErrInj : 1; /* * [3:3]TCAM ART不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtCrtErrInj : 1; /* * [2:2]TCAM ART可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamUncrtErrInj : 1; /* * [1:1]TCAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamCrtErrInj : 1; /* * [0:0]TCAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ +#else + unsigned int ipsurxTcamCrtErrInj : 1; /* * [0:0]TCAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamUncrtErrInj : 1; /* * [1:1]TCAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtCrtErrInj : 1; /* * [2:2]TCAM ART可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtUncrtErrInj : 1; /* * [3:3]TCAM ART不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptCrtErrInj : 1; /* * [4:4]TCP Port Table RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptUncrtErrInj : 1; /* * [5:5]TCP Port Table RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramCrtErrInj : 1; /* * [6:6]PPC DATA RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramUncrtErrInj : 1; /* * [7:7]PPC DATA RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvFifoRamCrtErrInj : 1; /* * [8:8]LCV FIFO RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvFifoRamUncrtErrInj : 1; /* * [9:9]LCV FIFO RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 + */ + unsigned int ipsurxLcvContextRamCrtErrInj : 1; /* * [10:10]LCV CONTEXT + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvContextRamUncrtErrInj : 1; /* * [11:11]LCV CONTEXT + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int reserved1 : 8; /* * [19:12] */ + unsigned int ipsurxRenqIfRamCrtErrInj : 1; /* * [20:20]RENQ Input FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqIfRamUncrtErrInj : 1; /* * [21:21]RENQ Input FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamCrtErrInj : 1; /* * [22:22]RENQ CONTEXT0 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamUncrtErrInj : 1; /* * [23:23]RENQ CONTEXT0 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamCrtErrInj : 1; /* * [24:24]RENQ CONTEXT1 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamUncrtErrInj : 1; /* * [25:25]RENQ CONTEXT1 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqOfRamCrtErrInj : 1; /* * [26:26]RENQ Output FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqOfRamUncrtErrInj : 1; /* * [27:27]RENQ Output FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int reserved0 : 4; /* * [31:28]保留 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RAM_ERR_INJ_U; + +/* ** + * Union name : IPSURX_TCAM_CTRL + * @brief TCAM控制寄存器 + * Description: + */ +typedef union tagUnIpsurxTcamCtrl { + struct tagStIpsurxTcamCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxTcamMbistTSel : 2; /* * [31:30]用于调节TCAM IP里面的read电路的时序， + * 默认值是2'b10。ATE筛片的时候，测试有read问题或者良率不行的时候，可以调大T_SEL改善；或者良率可以，并提高TCAM读速度的时候，可以调小T_SEL。 + */ + unsigned int ipsurxTcamMbistTest : 2; /* * + [29:28]2'b00：不进行筛片；2'b01：筛除弱pmos；2'b10：筛除弱nmos；2'b11：筛除弱pmos/nmos。 + */ + unsigned int ipsurxTcamMbistEn : 1; /* * [27:27]Function MBIST测试使能1'b0：不使能；1'b1：使能。 */ + unsigned int reserved : 9; /* * [26:18] */ + unsigned int + ipsurxTcamCfgSearchCtrl : 1; /* * [17:17]1'b0：返回命中TCAM KEY + 的地址；1'b1：返回TCAM查找的ART表项结果。在一次查找返回结果之前不能修改该值。 + */ + unsigned int ipsurxTcamLkupEn : 1; /* * [16:16]TCAM逻辑查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxTcamBkScanIntervalUnit : 8; /* * + [15:8]TCAM背景扫描间隔计数单位，最小值为16。当配置值小于16时，硬件会自动将配置值修改为16。 + */ + unsigned int + ipsurxTcamBkScanPeriod : 8; /* * + * [7:0]TCAM背景扫描间隔周期。实际的TCAM扫描启动间隔：当前背景扫描完成后ipsurx_tcam_bk_scan_interval_unit + * * ipsurx_tcam_bk_scan_period个CYCLE。注意：当两个参数的乘积为0时，表示不使能TCAM背景扫描。 + */ +#else + unsigned int + ipsurxTcamBkScanPeriod : 8; /* * + * [7:0]TCAM背景扫描间隔周期。实际的TCAM扫描启动间隔：当前背景扫描完成后ipsurx_tcam_bk_scan_interval_unit + * * ipsurx_tcam_bk_scan_period个CYCLE。注意：当两个参数的乘积为0时，表示不使能TCAM背景扫描。 + */ + unsigned int ipsurxTcamBkScanIntervalUnit : 8; /* * + [15:8]TCAM背景扫描间隔计数单位，最小值为16。当配置值小于16时，硬件会自动将配置值修改为16。 + */ + unsigned int ipsurxTcamLkupEn : 1; /* * [16:16]TCAM逻辑查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxTcamCfgSearchCtrl : 1; /* * [17:17]1'b0：返回命中TCAM KEY + 的地址；1'b1：返回TCAM查找的ART表项结果。在一次查找返回结果之前不能修改该值。 + */ + unsigned int reserved : 9; /* * [26:18] */ + unsigned int ipsurxTcamMbistEn : 1; /* * [27:27]Function MBIST测试使能1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxTcamMbistTest : 2; /* * + [29:28]2'b00：不进行筛片；2'b01：筛除弱pmos；2'b10：筛除弱nmos；2'b11：筛除弱pmos/nmos。 + */ + unsigned int + ipsurxTcamMbistTSel : 2; /* * [31:30]用于调节TCAM IP里面的read电路的时序， + * 默认值是2'b10。ATE筛片的时候，测试有read问题或者良率不行的时候，可以调大T_SEL改善；或者良率可以，并提高TCAM读速度的时候，可以调小T_SEL。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_CTRL_U; + +/* ** + * Union name : IPSURX_TCAM_MBIST_DONE + * @brief TCAM MBIST完成状态信号 + * Description: + */ +typedef union tagUnIpsurxTcamMbistDone { + struct tagStIpsurxTcamMbistDone { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxTcamMbistDone : 1; /* * [0:0]1'b0：未完成。1'b1：MBIST完成。 */ +#else + unsigned int ipsurxTcamMbistDone : 1; /* * [0:0]1'b0：未完成。1'b1：MBIST完成。 */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_MBIST_DONE_U; + +/* ** + * Union name : IPSURX_FIFO_CNT + * @brief IPSURX FIFO当前深度计数寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoCnt { + struct tagStIpsurxFifoCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 10; /* * [31:22]reserved. */ + unsigned int ipsurxRenqOfCnt : 6; /* * [21:16]RENQ 输出FIFO当前深度。 */ + unsigned int reserved1 : 2; /* * [15:14] */ + unsigned int ipsurxRenqIfCnt : 6; /* * [13:8]RENQ 输入FIFO当前深度。 */ + unsigned int ipsurxLcvFifoCnt : 8; /* * [7:0]LCV模块输入FIFO当前深度。 */ +#else + unsigned int ipsurxLcvFifoCnt : 8; /* * [7:0]LCV模块输入FIFO当前深度。 */ + unsigned int ipsurxRenqIfCnt : 6; /* * [13:8]RENQ 输入FIFO当前深度。 */ + unsigned int reserved1 : 2; /* * [15:14] */ + unsigned int ipsurxRenqOfCnt : 6; /* * [21:16]RENQ 输出FIFO当前深度。 */ + unsigned int reserved0 : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_CNT_U; + +/* ** + * Union name : IPSURX_FIFO_CURR_ST + * @brief IPSURX FIFO当前状态寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoCurrSt { + struct tagStIpsurxFifoCurrSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 17; /* * [31:15]reserved. */ + unsigned int ipsurxRenqOfOverflowCurr : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfFullCurr : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfAfullCurr : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfEmptyCurr : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAemptyCurr : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfOverflowCurr : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfFullCurr : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfAfullCurr : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAemptyCurr : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoOverflowCurr : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxLcvFifoFullCurr : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoAfullCurr : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoEmptyCurr : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAemptyCurr : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ +#else + unsigned int ipsurxLcvFifoAemptyCurr : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoEmptyCurr : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAfullCurr : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoFullCurr : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoOverflowCurr : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfAemptyCurr : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAfullCurr : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfFullCurr : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfOverflowCurr : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfAemptyCurr : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqOfEmptyCurr : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAfullCurr : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfFullCurr : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfOverflowCurr : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 17; /* * [31:15]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_CURR_ST_U; + +/* ** + * Union name : IPSUTX_IPSURX_CSR_AFIFO_CURR_ST + * @brief IPSURX CSR异步FIFO当前状态寄存器 + * Description: + */ +typedef union tagUnIpsutxIpsurxCsrAfifoCurrSt { + struct tagStIpsutxIpsurxCsrAfifoCurrSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6] */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsutxIpsurxCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 26; /* * [31:6] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSUTX_IPSURX_CSR_AFIFO_CURR_ST_U; + +/* ** + * Union name : IPSURX_FIFO_HIS_ST + * @brief IPSURX FIFO历史状态寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoHisSt { + struct tagStIpsurxFifoHisSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 17; /* * [31:15]reserved. */ + unsigned int ipsurxRenqOfOverflowHst : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfFullHst : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfAfullHst : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfEmptyHst : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAemptyHst : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfOverflowHst : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfFullHst : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfAfullHst : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAemptyHst : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoOverflowHst : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxLcvFifoFullHst : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoAfullHst : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoEmptyHst : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAemptyHst : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ +#else + unsigned int ipsurxLcvFifoAemptyHst : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoEmptyHst : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAfullHst : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoFullHst : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoOverflowHst : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfAemptyHst : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAfullHst : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfFullHst : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfOverflowHst : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfAemptyHst : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqOfEmptyHst : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAfullHst : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfFullHst : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfOverflowHst : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 17; /* * [31:15]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_HIS_ST_U; + +/* ** + * Union name : IPSUTX_IPSURX_CSR_AFIFO_HIS_ST + * @brief IPSURX CSR异步FIFO历史状态寄存器 + * Description: + */ +typedef union tagUnIpsutxIpsurxCsrAfifoHisSt { + struct tagStIpsutxIpsurxCsrAfifoHisSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsutxIpsurxCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSUTX_IPSURX_CSR_AFIFO_HIS_ST_U; + +/* ** + * Union name : IPSURX_REC_BP_CNT + * @brief IPSURX接收反压次数计数器 + * Description: + */ +typedef union tagUnIpsurxRecBpCnt { + struct tagStIpsurxRecBpCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRecBpCnt : 32; /* * [31:0]IPSURX收到反压次数计数器 */ +#else + unsigned int ipsurxRecBpCnt : 32; /* * [31:0]IPSURX收到反压次数计数器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_REC_BP_CNT_U; + +/* ** + * Union name : IPSURX_GEN_BP_CNT + * @brief IPSURX产生反压次数计数器 + * Description: + */ +typedef union tagUnIpsurxGenBpCnt { + struct tagStIpsurxGenBpCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxGenBpCnt : 32; /* * [31:0]IPSURX产生反压次数计数器 */ +#else + unsigned int ipsurxGenBpCnt : 32; /* * [31:0]IPSURX产生反压次数计数器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_GEN_BP_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_MBIST_MEM_ERR_CNT + * @brief TCAM MBIST MEM错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamMbistMemErrCnt { + struct tagStIpsurxTcamMbistMemErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamMbistMemErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamMbistMemErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_MBIST_MEM_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_MBIST_CMP_ERR_CNT + * @brief TCAM MBIST 匹配错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamMbistCmpErrCnt { + struct tagStIpsurxTcamMbistCmpErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamMbistCmpErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamMbistCmpErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_MBIST_CMP_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_CRT_ERR_CNT + * @brief TCAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamCrtErrCnt { + struct tagStIpsurxTcamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_UNCRT_ERR_CNT + * @brief TCAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamUncrtErrCnt { + struct tagStIpsurxTcamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_ART_CRT_ERR_CNT + * @brief TCAM/ART 可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamArtCrtErrCnt { + struct tagStIpsurxTcamArtCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamArtCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamArtCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_ART_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_ART_UNCRT_ERR_CNT + * @brief TCAM/ART 不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamArtUncrtErrCnt { + struct tagStIpsurxTcamArtUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamArtUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamArtUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_ART_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PKT_DROP_BY_TCAM_CNT + * @brief TCAM指定丢弃报文计数器 + * Description: + */ +typedef union tagUnIpsurxPktDropByTcamCnt { + struct tagStIpsurxPktDropByTcamCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPktDropByTcamCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPktDropByTcamCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PKT_DROP_BY_TCAM_CNT_U; + +/* ** + * Union name : IPSURX_TPT_CRT_ERR_CNT + * @brief TPT 可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTptCrtErrCnt { + struct tagStIpsurxTptCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTptCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTptCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TPT_UNCRT_ERR_CNT + * @brief TPT 不可纠ECC校验错计数器 + * Description: + */ +typedef union tagUnIpsurxTptUncrtErrCnt { + struct tagStIpsurxTptUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTptUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTptUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PPC_DRAM_CRT_ERR_CNT + * @brief PPC模块数据RAM可纠ECC校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxPpcDramCrtErrCnt { + struct tagStIpsurxPpcDramCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPpcDramCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPpcDramCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PPC_DRAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PPC_DRAM_UNCRT_ERR_CNT + * @brief PPC模块数据RAM不可纠校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxPpcDramUncrtErrCnt { + struct tagStIpsurxPpcDramUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPpcDramUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPpcDramUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PPC_DRAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_FIFO_RAM_CRT_ERR_CNT + * @brief LCV 输入FIFO RAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvFifoRamCrtErrCnt { + struct tagStIpsurxLcvFifoRamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvFifoRamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvFifoRamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_FIFO_RAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_FIFO_RAM_UNCRT_ERR_CNT + * @brief LCV 输入FIFO RAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvFifoRamUncrtErrCnt { + struct tagStIpsurxLcvFifoRamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvFifoRamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvFifoRamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_FIFO_RAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_CONTEXT_CRT_ERR_CNT + * @brief LCV模块Context可纠ECC校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvContextCrtErrCnt { + struct tagStIpsurxLcvContextCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvContextCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvContextCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_CONTEXT_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_CONTEXT_UNCRT_ERR_CNT + * @brief LCV模块Context不可纠校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvContextUncrtErrCnt { + struct tagStIpsurxLcvContextUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvContextUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvContextUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_CONTEXT_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_IF_RAM_CRT_ERR_CNT + * @brief RENQ 输入FIFO RAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqIfRamCrtErrCnt { + struct tagStIpsurxRenqIfRamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqIfRamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqIfRamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_IF_RAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_IF_RAM_UNCRT_ERR_CNT + * @brief RENQ 输入FIFO RAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqIfRamUncrtErrCnt { + struct tagStIpsurxRenqIfRamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqIfRamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqIfRamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_IF_RAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT0_CRT_ERR_CNT + * @brief RENQ CONTEXT RAM可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext0CrtErrCnt { + struct tagStIpsurxRenqContext0CrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext0CrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext0CrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT0_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT0_UNCRT_ERR_CNT + * @brief RENQ CONTEXT RAM不可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext0UncrtErrCnt { + struct tagStIpsurxRenqContext0UncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext0UncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext0UncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT0_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT1_CRT_ERR_CNT + * @brief RENQ CONTEXT RAM可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext1CrtErrCnt { + struct tagStIpsurxRenqContext1CrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext1CrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext1CrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT1_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT1_UNCRT_ERR_CNT + * @brief RENQ CONTEXT RAM不可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext1UncrtErrCnt { + struct tagStIpsurxRenqContext1UncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext1UncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext1UncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT1_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_OF_RAM_CRT_ERR_CNT + * @brief RENQ 输出FIFO RAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqOfRamCrtErrCnt { + struct tagStIpsurxRenqOfRamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqOfRamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqOfRamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_OF_RAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_OF_RAM_UNCRT_ERR_CNT + * @brief RENQ 输出FIFO RAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqOfRamUncrtErrCnt { + struct tagStIpsurxRenqOfRamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqOfRamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqOfRamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_OF_RAM_UNCRT_ERR_CNT_U; + + +/* ** + * Union name : IPSURX_CH16_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh16RxPktCnt { + struct tagStIpsurxCh16RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh16RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh16RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH16_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH16_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh16TxPktCnt { + struct tagStIpsurxCh16TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh16TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh16TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH16_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH15_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh15RxPktCnt { + struct tagStIpsurxCh15RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh15RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh15RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH15_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH15_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh15TxPktCnt { + struct tagStIpsurxCh15TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh15TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh15TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH15_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH14_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh14RxPktCnt { + struct tagStIpsurxCh14RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh14RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh14RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH14_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH14_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh14TxPktCnt { + struct tagStIpsurxCh14TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh14TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh14TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH14_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH13_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh13RxPktCnt { + struct tagStIpsurxCh13RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh13RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh13RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH13_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH13_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh13TxPktCnt { + struct tagStIpsurxCh13TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh13TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh13TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH13_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH12_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh12RxPktCnt { + struct tagStIpsurxCh12RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh12RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh12RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH12_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH12_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh12TxPktCnt { + struct tagStIpsurxCh12TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh12TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh12TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH12_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH11_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh11RxPktCnt { + struct tagStIpsurxCh11RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh11RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh11RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH11_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH11_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh11TxPktCnt { + struct tagStIpsurxCh11TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh11TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh11TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH11_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH10_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh10RxPktCnt { + struct tagStIpsurxCh10RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh10RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh10RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH10_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH10_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh10TxPktCnt { + struct tagStIpsurxCh10TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh10TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh10TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH10_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH09_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh09RxPktCnt { + struct tagStIpsurxCh09RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh09RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh09RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH09_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH09_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh09TxPktCnt { + struct tagStIpsurxCh09TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh09TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh09TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH09_TX_PKT_CNT_U; + + +/* ** + * Union name : IPSURX_CH08_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh08RxPktCnt { + struct tagStIpsurxCh08RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh08RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh08RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH08_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH08_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh08TxPktCnt { + struct tagStIpsurxCh08TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh08TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh08TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH08_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH07_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh07RxPktCnt { + struct tagStIpsurxCh07RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh07RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh07RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH07_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH07_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh07TxPktCnt { + struct tagStIpsurxCh07TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh07TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh07TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH07_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH06_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh06RxPktCnt { + struct tagStIpsurxCh06RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh06RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh06RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH06_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH06_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh06TxPktCnt { + struct tagStIpsurxCh06TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh06TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh06TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH06_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH05_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh05RxPktCnt { + struct tagStIpsurxCh05RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh05RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh05RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH05_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH05_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh05TxPktCnt { + struct tagStIpsurxCh05TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh05TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh05TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH05_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH04_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh04RxPktCnt { + struct tagStIpsurxCh04RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh04RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh04RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH04_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH04_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh04TxPktCnt { + struct tagStIpsurxCh04TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh04TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh04TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH04_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH03_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh03RxPktCnt { + struct tagStIpsurxCh03RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh03RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh03RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH03_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH03_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh03TxPktCnt { + struct tagStIpsurxCh03TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh03TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh03TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH03_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH02_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh02RxPktCnt { + struct tagStIpsurxCh02RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh02RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh02RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH02_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH02_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh02TxPktCnt { + struct tagStIpsurxCh02TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh02TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh02TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH02_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH01_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh01RxPktCnt { + struct tagStIpsurxCh01RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh01RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh01RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH01_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH01_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh01TxPktCnt { + struct tagStIpsurxCh01TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh01TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh01TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH01_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH00_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh00RxPktCnt { + struct tagStIpsurxCh00RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh00RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh00RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH00_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH00_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh00TxPktCnt { + struct tagStIpsurxCh00TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh00TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh00TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH00_TX_PKT_CNT_U; + + +/* ** + * Union name : IPSURX_API_CSR_FIFO_CURR_ST + * @brief IPSURX CSR FIFO当前状态寄存器 + * Description: + */ +typedef union tagUnIpsurxApiCsrFifoCurrSt { + struct tagStIpsurxApiCsrFifoCurrSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12] */ + unsigned int ipsurxApiSfifoOverflowCurr : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoFullCurr : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoEmptyCurr : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoOverflowCurr : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoFullCurr : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsurxCnbCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoFullCurr : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoOverflowCurr : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoEmptyCurr : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiSfifoFullCurr : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoOverflowCurr : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 20; /* * [31:12] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CSR_FIFO_CURR_ST_U; + +/* ** + * Union name : IPSURX_API_CSR_FIFO_HIS_ST + * @brief IPSURX CSR FIFO历史状态寄存器 + * Description: + */ +typedef union tagUnIpsurxApiCsrFifoHisSt { + struct tagStIpsurxApiCsrFifoHisSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved. */ + unsigned int ipsurxApiSfifoOverflowHst : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoFullHst : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoEmptyHst : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoOverflowHst : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoFullHst : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsurxCnbCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoFullHst : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoOverflowHst : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoEmptyHst : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiSfifoFullHst : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoOverflowHst : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 20; /* * [31:12]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CSR_FIFO_HIS_ST_U; + +/* ** + * Union name : IPSURX_API_ERR_FLIT_CNT + * @brief IPSURX错误API FLIT计数器 + * Description: + */ +typedef union tagUnIpsurxApiErrFlitCnt { + struct tagStIpsurxApiErrFlitCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxApiErrFlitCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxApiErrFlitCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_FLIT_CNT_U; + +/* ** + * Union name : IPSURX_API_CRT_FLIT_CNT + * @brief IPSURX正确API FLIT计数器 + * Description: + */ +typedef union tagUnIpsurxApiCrtFlitCnt { + struct tagStIpsurxApiCrtFlitCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxApiCrtFlitCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxApiCrtFlitCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CRT_FLIT_CNT_U; + +/* ** + * Union name : IPSURX_API_DROP_FOR_FULL_CNT + * @brief IPSURX丢弃正确API计数器 + * Description: + */ +typedef union tagUnIpsurxApiDropForFullCnt { + struct tagStIpsurxApiDropForFullCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxApiDropForFullCnt : 32; /* * + [31:0]由于API在RING时钟域，可能大量突发给IPSURX，IPSURX可能来不及处理。这种情况下，会直接丢弃已经通过合法性检查的API，并进行计数。 + */ +#else + unsigned int ipsurxApiDropForFullCnt : 32; /* * + [31:0]由于API在RING时钟域，可能大量突发给IPSURX，IPSURX可能来不及处理。这种情况下，会直接丢弃已经通过合法性检查的API，并进行计数。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_DROP_FOR_FULL_CNT_U; + +/* ** + * Union name : IPSURX_API_ERR_INT_VECTOR + * @brief IPSURX API错误中断向量寄存器 + * Description: + */ +typedef union tagUnIpsurxApiErrIntVector { + struct tagStIpsurxApiErrIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported thru this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + * and MSI-X table index. The detail of the 24-bit register is defined by CPI in + * Hi1822V100 FS + */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + * and MSI-X table index. The detail of the 24-bit register is defined by CPI in + * Hi1822V100 FS + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported thru this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_INT_VECTOR_U; + +/* ** + * Union name : IPSURX_API_ERR_INT + * @brief IPSURX API错误中断寄存器 + * Description: + */ +typedef union tagUnIpsurxApiErrInt { + struct tagStIpsurxApiErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_API_ERR_INT_MASK register. + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int intData : 7; /* * [6:0]These 7 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ +#else + unsigned int intData : 7; /* * [6:0]These 7 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_API_ERR_INT_MASK register. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_INT_U; + +/* ** + * Union name : IPSURX_API_ERR_INT_MASK + * @brief IPSURX API错误中断MASK寄存器 + * Description: + */ +typedef union tagUnIpsurxApiErrIntMask { + struct tagStIpsurxApiErrIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int + errMask : 7; /* * + [6:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[6]对应TILE写给IPSURX的反标API路径上的FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。bit[5]对应CSR路径上，IPSURX时钟域到RING时钟域的 + 异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[4:0]对应非致命中断，用户可以根据自己需要处理。 + */ +#else + unsigned int + errMask : 7; /* * + [6:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[6]对应TILE写给IPSURX的反标API路径上的FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。bit[5]对应CSR路径上，IPSURX时钟域到RING时钟域的 + 异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[4:0]对应非致命中断，用户可以根据自己需要处理。 + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_INT_MASK_U; + +/* ** + * Union name : IPSURX_API_FLIT_TYPE_ERR + * @brief FLIT TYPE错误中断 + * Description: + */ +typedef union tagUnIpsurxApiFlitTypeErr { + struct tagStIpsurxApiFlitTypeErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received flit type. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received flit type. */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_FLIT_TYPE_ERR_U; + +/* ** + * Union name : IPSURX_API_CODE_ERR + * @brief API CODE错误中断 + * Description: + */ +typedef union tagUnIpsurxApiCodeErr { + struct tagStIpsurxApiCodeErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received API code field. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received API code field. */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CODE_ERR_U; + +/* ** + * Union name : IPSURX_API_SRC_ERR + * @brief API SRC 错误中断 + * Description: + */ +typedef union tagUnIpsurxApiSrcErr { + struct tagStIpsurxApiSrcErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API SRC field. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API SRC field. */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_SRC_ERR_U; + +/* ** + * Union name : IPSURX_API_OPCODE_ERR + * @brief API OPCODE 错误中断 + * Description: + */ +typedef union tagUnIpsurxApiOpcodeErr { + struct tagStIpsurxApiOpcodeErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API OPCODE field. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API OPCODE field. */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_OPCODE_ERR_U; + +/* ** + * Union name : IPSURX_API_MERR + * @brief API错误中断寄存器 + * Description: + */ +typedef union tagUnIpsurxApiMerr { + struct tagStIpsurxApiMerr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved. */ + unsigned int apiAMerr : 1; /* * [9:9]API A-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiAErr : 1; /* * [8:8]API A-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiMMerr : 1; /* * [7:7]API M-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiMErr : 1; /* * [6:6]API M-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiE0Merr : 1; /* * [5:5]API E0-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE0Err : 1; /* * [4:4]API E0-bit error1'b0: no error found;1'b1: error found. */ + unsigned int apiE1Merr : 1; /* * [3:3]API E1-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE1Err : 1; /* * [2:2]API E1-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiSMerr : 1; /* * [1:1]API S-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiSErr : 1; /* * [0:0]API S-bit error.1'b0: no error found;1'b1: error found. */ +#else + unsigned int apiSErr : 1; /* * [0:0]API S-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiSMerr : 1; /* * [1:1]API S-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE1Err : 1; /* * [2:2]API E1-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiE1Merr : 1; /* * [3:3]API E1-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE0Err : 1; /* * [4:4]API E0-bit error1'b0: no error found;1'b1: error found. */ + unsigned int apiE0Merr : 1; /* * [5:5]API E0-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiMErr : 1; /* * [6:6]API M-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiMMerr : 1; /* * [7:7]API M-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiAErr : 1; /* * [8:8]API A-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiAMerr : 1; /* * [9:9]API A-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int reserved : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_MERR_U; + +/* ** + * Union name : IPSURX_API_MERR_MASK + * @brief API错误中断MASK寄存器 + * Description: + */ +typedef union tagUnIpsurxApiMerrMask { + struct tagStIpsurxApiMerrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int apiAErrMask : 1; /* * [4:4]1'b1：允许上报API A比特错误中断；1'b0：不允许上报API A比特错误中断。 */ + unsigned int apiMErrMask : 1; /* * [3:3]1'b1：允许上报API M比特错误中断；1'b0：不允许上报API M比特错误中断。 */ + unsigned int apiE0ErrMask : 1; /* * [2:2]1'b1：允许上报API E0比特错误中断；1'b0：不允许上报API E0比特错误中断。 + */ + unsigned int apiE1ErrMask : 1; /* * [1:1]1'b1：允许上报API E1比特错误中断；1'b0：不允许上报API E1比特错误中断。 + */ + unsigned int apiSErrMask : 1; /* * [0:0]1'b1：允许上报API S比特错误中断；1'b0：不允许上报API S比特错误中断。 */ +#else + unsigned int apiSErrMask : 1; /* * [0:0]1'b1：允许上报API S比特错误中断；1'b0：不允许上报API S比特错误中断。 */ + unsigned int apiE1ErrMask : 1; /* * [1:1]1'b1：允许上报API E1比特错误中断；1'b0：不允许上报API E1比特错误中断。 + */ + unsigned int apiE0ErrMask : 1; /* * [2:2]1'b1：允许上报API E0比特错误中断；1'b0：不允许上报API E0比特错误中断。 + */ + unsigned int apiMErrMask : 1; /* * [3:3]1'b1：允许上报API M比特错误中断；1'b0：不允许上报API M比特错误中断。 */ + unsigned int apiAErrMask : 1; /* * [4:4]1'b1：允许上报API A比特错误中断；1'b0：不允许上报API A比特错误中断。 */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_MERR_MASK_U; + +/* ** + * Union name : IPSURX_RING_AFIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxRingAfifoOvfl { + struct tagStIpsurxRingAfifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]IPSURX时钟域到RING时钟域溢出异步FIFO编号。1'b0: IPSURX到RING + * CSR异步FIFO溢出；1'b1: IPSURX到RING 中断CSR异步FIFO溢出。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 1; /* * [2:2]IPSURX时钟域到RING时钟域溢出异步FIFO编号。1'b0: IPSURX到RING + * CSR异步FIFO溢出；1'b1: IPSURX到RING 中断CSR异步FIFO溢出。 + */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RING_AFIFO_OVFL_U; + +/* ** + * Union name : IPSURX_API_FIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxApiFifoOvfl { + struct tagStIpsurxApiFifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]TILE写给IPSURX的反标API路径上的溢出FIFO编号。1'b0: 同步FIFO溢出；1'b1: + 异步FIFO溢出。 */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 1; /* * [2:2]TILE写给IPSURX的反标API路径上的溢出FIFO编号。1'b0: 同步FIFO溢出；1'b1: + 异步FIFO溢出。 */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_FIFO_OVFL_U; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* * __cplusplus */ + +#endif /* * HI1822_CSR_IPSURX_TYPEDEF_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_c_union_define.h new file mode 100644 index 000000000..7b545a081 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_c_union_define.h @@ -0,0 +1,2872 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_typedef.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/09/06 10:44:42 Create file +// ****************************************************************************** + +#ifndef IPSUTX_C_UNION_DEFINE_H +#define IPSUTX_C_UNION_DEFINE_H + +/* Define the union csr_ipsutx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fpga_ver_u; + +/* Define the union csr_ipsutx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_emu_ver_u; + +/* Define the union csr_ipsutx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_crc_cs_init_start : 1; /* [0] */ + u32 ipsutx_tcam_init_start : 1; /* [1] */ + u32 ipsutx_difx_rslt_init_start : 1; /* [2] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_initctab_start_u; + +/* Define the union csr_ipsutx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_crc_cs_init_done : 1; /* [0] */ + u32 ipsutx_tcam_init_done : 1; /* [1] */ + u32 ipsutx_difx_rslt_init_done : 1; /* [2] */ + u32 rsv_1 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_initctab_done_u; + +/* Define the union csr_ipsutx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 ipsutx_int_enable : 1; /* [27] */ + u32 ipsutx_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_vector_u; + +/* Define the union csr_ipsutx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_int_data : 7; /* [6:0] */ + u32 rsv_4 : 9; /* [15:7] */ + u32 ipsutx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_u; + +/* Define the union csr_ipsutx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_int_en : 7; /* [6:0] */ + u32 rsv_5 : 9; /* [15:7] */ + u32 ipsutx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_en_u; + +/* Define the union csr_ipsutx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ucerr : 1; /* [0] */ + u32 ipsutx_ram_ucerr_insrt : 1; /* [1] */ + u32 ipsutx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ucerr_u; + +/* Define the union csr_ipsutx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_cerr : 1; /* [0] */ + u32 ipsutx_ram_cerr_insrt : 1; /* [1] */ + u32 ipsutx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_cerr_u; + +/* Define the union csr_ipsutx_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_fifo_of_err : 1; /* [0] */ + u32 ipsutx_fifo_of_err_insrt : 1; /* [1] */ + u32 ipsutx_fifo_of_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_of_err_u; + +/* Define the union csr_ipsutx_sop_eop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_sop_eop_err : 1; /* [0] */ + u32 ipsutx_sop_eop_err_insrt : 1; /* [1] */ + u32 ipsutx_sop_eop_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sop_eop_err_u; + +/* Define the union csr_ipsutx_difx_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_err : 1; /* [0] */ + u32 ipsutx_difx_err_insrt : 1; /* [1] */ + u32 ipsutx_difx_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_u; + +/* Define the union csr_ipsutx_parse_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_parse_err : 1; /* [0] */ + u32 ipsutx_parse_err_insrt : 1; /* [1] */ + u32 ipsutx_parse_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_parse_err_u; + +/* Define the union csr_ipsutx_schnl_cfg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_schnl_cfg_err : 1; /* [0] */ + u32 ipsutx_schnl_cfg_err_insrt : 1; /* [1] */ + u32 ipsutx_schnl_cfg_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_schnl_cfg_err_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw3_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw2_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw1_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw0_u; + +/* Define the union csr_ipsutx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_indrect_addr : 24; /* [23:0] */ + u32 ipsutx_indrect_tab : 4; /* [27:24] */ + u32 ipsutx_indrect_stat : 2; /* [29:28] */ + u32 ipsutx_indrect_mode : 1; /* [30] */ + u32 ipsutx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_indrect_ctrl_u; + +/* Define the union csr_ipsutx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_indrect_timeout_u; + +/* Define the union csr_ipsutx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_indrect_data_u; + +/* Define the union csr_ipsutx_cat_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 2; /* [1:0] */ + u32 ipsutx_ch_cvlan_tpid_sel : 5; /* [6:2] */ + u32 ipsutx_ch_cvlan : 1; /* [7] */ + u32 rsv_7 : 2; /* [9:8] */ + u32 ipsutx_ch_svlan_tpid_sel : 5; /* [14:10] */ + u32 ipsutx_ch_svlan : 1; /* [15] */ + u32 rsv_8 : 2; /* [17:16] */ + u32 ipsutx_ch_dsatag : 1; /* [18] */ + u32 rsv_9 : 1; /* [19] */ + u32 ipsutx_ch_evtag_tpid_sel : 4; /* [23:20] */ + u32 ipsutx_ch_evtag : 2; /* [25:24] */ + u32 rsv_10 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw0_u; + +/* Define the union csr_ipsutx_cat_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 4; /* [3:0] */ + u32 ipsutx_ch_ipv4_tcp_syn_chk_en : 1; /* [4] */ + u32 rsv_12 : 7; /* [11:5] */ + u32 ipsutx_ch_ipv4_udp_len_chk_en : 1; /* [12] */ + u32 ipsutx_ch_ipv4_dip_rsv_addr_chk_en : 1; /* [13] */ + u32 ipsutx_ch_ipv4_dip_zero_chk_en : 1; /* [14] */ + u32 ipsutx_ch_ipv4_dip_lb_chk_en : 1; /* [15] */ + u32 ipsutx_ch_ipv4_sip_lb_chk_en : 1; /* [16] */ + u32 ipsutx_ch_ipv4_sip_mc_chk_en : 1; /* [17] */ + u32 ipsutx_ch_ipv4_sip_dip_chk_en : 1; /* [18] */ + u32 ipsutx_ch_ipv4_ihl_chk_en : 1; /* [19] */ + u32 ipsutx_ch_ipv4_ver_chk_en : 1; /* [20] */ + u32 ipsutx_ch_ipv4_len_chk_en : 1; /* [21] */ + u32 rsv_13 : 6; /* [27:22] */ + u32 ipsutx_ch_8023_len_chk_en : 1; /* [28] */ + u32 ipsutx_ch_da_sa_equal_chk_en : 1; /* [29] */ + u32 ipsutx_ch_smac_chk_en : 1; /* [30] */ + u32 ipsutx_ch_dmac_zero_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw1_u; + +/* Define the union csr_ipsutx_cat_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ch_tunnel_da_sa_equal_chk_en : 1; /* [0] */ + u32 ipsutx_ch_tunnel_smac_chk_en : 1; /* [1] */ + u32 ipsutx_ch_tunnel_dmac_zero_chk_en : 1; /* [2] */ + u32 ipsutx_ch_tunnel_nvgre_cvlan_chk_en : 1; /* [3] */ + u32 rsv_14 : 4; /* [7:4] */ + u32 ipsutx_ch_tunnel_cvlan_tpid_sel : 5; /* [12:8] */ + u32 ipsutx_ch_tunnel_cvlan : 1; /* [13] */ + u32 ipsutx_ch_tunnel_svlan_tpid_sel : 5; /* [18:14] */ + u32 ipsutx_ch_tunnel_svlan : 1; /* [19] */ + u32 ipsutx_ch_tunnel_vni_chk_en : 1; /* [20] */ + u32 ipsutx_ch_nvgre_crks_chk_en : 1; /* [21] */ + u32 ipsutx_ch_ipv6_tcp_syn_chk_en : 1; /* [22] */ + u32 rsv_15 : 5; /* [27:23] */ + u32 ipsutx_ch_ipv6_dip_chk_en : 1; /* [28] */ + u32 ipsutx_ch_ipv6_sip_chk_en : 1; /* [29] */ + u32 ipsutx_ch_ipv6_ver_chk_en : 1; /* [30] */ + u32 ipsutx_ch_ipv6_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw2_u; + +/* Define the union csr_ipsutx_cat_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 1; /* [0] */ + u32 ipsutx_ch_tcam_key_sel : 1; /* [1] */ + u32 rsv_17 : 11; /* [12:2] */ + u32 ipsutx_ch_tunnel_ipv6_dip_chk_en : 1; /* [13] */ + u32 ipsutx_ch_tunnel_ipv6_sip_chk_en : 1; /* [14] */ + u32 ipsutx_ch_tunnel_ipv6_ver_chk_en : 1; /* [15] */ + u32 ipsutx_ch_tunnel_ipv6_len_chk_en : 1; /* [16] */ + u32 rsv_18 : 4; /* [20:17] */ + u32 ipsutx_ch_tunnel_ipv4_udp_len_chk_en : 1; /* [21] */ + u32 ipsutx_ch_tunnel_ipv4_dip_rsv_addr_chk_en : 1; /* [22] */ + u32 ipsutx_ch_tunnel_ipv4_dip_zero_chk_en : 1; /* [23] */ + u32 ipsutx_ch_tunnel_ipv4_dip_lb_chk_en : 1; /* [24] */ + u32 ipsutx_ch_tunnel_ipv4_sip_lb_chk_en : 1; /* [25] */ + u32 ipsutx_ch_tunnel_ipv4_sip_mc_chk_en : 1; /* [26] */ + u32 ipsutx_ch_tunnel_ipv4_sip_dip_chk_en : 1; /* [27] */ + u32 ipsutx_ch_tunnel_ipv4_ihl_chk_en : 1; /* [28] */ + u32 ipsutx_ch_tunnel_ipv4_ver_chk_en : 1; /* [29] */ + u32 ipsutx_ch_tunnel_ipv4_len_chk_en : 1; /* [30] */ + u32 ipsutx_ch_tunnel_8023_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw3_u; + +/* Define the union csr_ipsutx_cpi_ec_ch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_ec_ch0 : 5; /* [4:0] */ + u32 rsv_19 : 2; /* [6:5] */ + u32 ipsutx_cpi_ec_ch0_vld : 1; /* [7] */ + u32 ipsutx_cpi_ec_ch1 : 5; /* [12:8] */ + u32 rsv_20 : 2; /* [14:13] */ + u32 ipsutx_cpi_ec_ch1_vld : 1; /* [15] */ + u32 rsv_21 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_ec_ch_u; + +/* Define the union csr_ipsutx_cpi_virtio_ch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_virtio_ch0 : 5; /* [4:0] */ + u32 rsv_22 : 2; /* [6:5] */ + u32 ipsutx_cpi_virtio_ch0_vld : 1; /* [7] */ + u32 ipsutx_cpi_virtio_ch1 : 5; /* [12:8] */ + u32 rsv_23 : 2; /* [14:13] */ + u32 ipsutx_cpi_virtio_ch1_vld : 1; /* [15] */ + u32 ipsutx_cpi_virtio_ch2 : 5; /* [20:16] */ + u32 rsv_24 : 2; /* [22:21] */ + u32 ipsutx_cpi_virtio_ch2_vld : 1; /* [23] */ + u32 ipsutx_cpi_virtio_ch3 : 5; /* [28:24] */ + u32 rsv_25 : 2; /* [30:29] */ + u32 ipsutx_cpi_virtio_ch3_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_virtio_ch_u; + +/* Define the union csr_ipsutx_bandwidth_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_bw : 7; /* [6:0] */ + u32 rsv_26 : 1; /* [7] */ + u32 ipsutx_petx_bw : 7; /* [14:8] */ + u32 rsv_27 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_bandwidth_cfg_u; + +/* Define the union csr_ipsutx_ppop_mpu_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_mpu_timer : 20; /* [19:0] */ + u32 rsv_28 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_mpu_timer_u; + +/* Define the union csr_ipsutx_cpi_difx_ch_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_29 : 5; /* [4:0] */ + u32 ipsutx_cpi_difx_ch_en : 15; /* [19:5] */ + u32 rsv_30 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_difx_ch_en_u; + +/* Define the union csr_ipsutx_sop_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sop_eop_st : 20; /* [19:0] */ + u32 ipsutx_petx_sop_eop_st : 3; /* [22:20] */ + u32 ipsutx_mpu_sop_eop_st : 1; /* [23] */ + u32 ipsutx_ppop_sop_eop_st : 1; /* [24] */ + u32 ipsutx_petx_pdu_st : 3; /* [27:25] */ + u32 rsv_31 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sop_eop_st_u; + +/* Define the union csr_ipsutx_cpi_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_cpi_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_cpi_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_mag_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_mag_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_mag_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_mag_1stpdu_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_1stpdu_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_1stpdu_with_err_cnt_u; + +/* Define the union csr_ipsutx_mag_1stpdu_1stpdu_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_1stpdu_1stpdu_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_1stpdu_1stpdu_err_cnt_u; + +/* Define the union csr_ipsutx_mpu_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_mpu_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_mpu_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_ppop_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_ppop_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_ppop_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_mpu_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_mpu_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ppop_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ppop_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ppop_mpu_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_mpu_timeout_cnt : 16; /* [15:0] */ + u32 ipsutx_ppop_timeout_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_mpu_timeout_cnt_u; + +/* Define the union csr_ipsutx_sor_eor_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sor_eor_st : 2; /* [1:0] */ + u32 rsv_32 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sor_eor_st_u; + +/* Define the union csr_ipsutx_cpi_sor_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sor_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sor_with_err_cnt_u; + +/* Define the union csr_ipsutx_cpi_sor_sor_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sor_sor_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sor_sor_err_cnt_u; + +/* Define the union csr_ipsutx_evtag_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_evtag_tpid2 : 16; /* [15:0] */ + u32 ipsutx_evtag_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_evtag_tpid1_u; + +/* Define the union csr_ipsutx_evtag_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_evtag_tpid0 : 16; /* [15:0] */ + u32 ipsutx_evtag_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_evtag_tpid0_u; + +/* Define the union csr_ipsutx_svlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_svlan_tpid4 : 16; /* [15:0] */ + u32 rsv_33 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_svlan_tpid2_u; + +/* Define the union csr_ipsutx_svlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_svlan_tpid2 : 16; /* [15:0] */ + u32 ipsutx_svlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_svlan_tpid1_u; + +/* Define the union csr_ipsutx_svlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_svlan_tpid0 : 16; /* [15:0] */ + u32 ipsutx_svlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_svlan_tpid0_u; + +/* Define the union csr_ipsutx_cvlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cvlan_tpid4 : 16; /* [15:0] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cvlan_tpid2_u; + +/* Define the union csr_ipsutx_cvlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cvlan_tpid2 : 16; /* [15:0] */ + u32 ipsutx_cvlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cvlan_tpid1_u; + +/* Define the union csr_ipsutx_cvlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cvlan_tpid0 : 16; /* [15:0] */ + u32 ipsutx_cvlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cvlan_tpid0_u; + +/* Define the union csr_ipsutx_8023_max_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_8023_max_len : 11; /* [10:0] */ + u32 rsv_35 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_8023_max_len_u; + +/* Define the union csr_ipsutx_8023_jumbo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_8023_jumbo_tpid : 16; /* [15:0] */ + u32 ipsutx_8023_jumbo_chk_en : 1; /* [16] */ + u32 rsv_36 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_8023_jumbo_cfg_u; + +/* Define the union csr_ipsutx_l2_dmac_eth_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_lldp_dmac_chk_en : 1; /* [0] */ + u32 ipsutx_lacp_dmac_chk_en : 1; /* [1] */ + u32 ipsutx_pfc_dmac_chk_en : 1; /* [2] */ + u32 ipsutx_pause_dmac_chk_en : 1; /* [3] */ + u32 ipsutx_tunnel_lldp_dmac_chk_en : 1; /* [4] */ + u32 ipsutx_tunnel_lacp_dmac_chk_en : 1; /* [5] */ + u32 ipsutx_tunnel_pfc_dmac_chk_en : 1; /* [6] */ + u32 ipsutx_tunnel_pause_dmac_chk_en : 1; /* [7] */ + u32 rsv_37 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2_dmac_eth_chk_en_u; + +/* Define the union csr_ipsutx_igmpv4_dip_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_igmpv4_dip_chk_en : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_igmpv4_dip_chk_en_u; + +/* Define the union csr_ipsutx_ipv6_spec_mc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_spec_mcast : 16; /* [15:0] */ + u32 ipsutx_ipv6_spec_mcast_mask : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_spec_mc_u; + +/* Define the union csr_ipsutx_rocev2_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_rocev2_dport : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rocev2_dport_u; + +/* Define the union csr_ipsutx_natt_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_natt_dport : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_natt_dport_u; + +/* Define the union csr_ipsutx_vxlan_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_vxlan_dport : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_vxlan_dport_u; + +/* Define the union csr_ipsutx_vxlan_gpe_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_vxlan_gpe_dport : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_vxlan_gpe_dport_u; + +/* Define the union csr_ipsutx_geneve_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_geneve_dport : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_geneve_dport_u; + +/* Define the union csr_ipsutx_ipv4_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_np : 8; /* [7:0] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_np_u; + +/* Define the union csr_ipsutx_ipv6_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_np : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_np_u; + +/* Define the union csr_ipsutx_ethernet_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ethernet_np : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ethernet_np_u; + +/* Define the union csr_ipsutx_ioam_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ioam_np : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ioam_np_u; + +/* Define the union csr_ipsutx_int_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_int_np : 8; /* [7:0] */ + u32 rsv_48 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_np_u; + +/* Define the union csr_ipsutx_nsh_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nsh_np : 8; /* [7:0] */ + u32 rsv_49 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nsh_np_u; + +/* Define the union csr_ipsutx_ah_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ah_np : 8; /* [7:0] */ + u32 rsv_50 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ah_np_u; + +/* Define the union csr_ipsutx_esp_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_esp_np : 8; /* [7:0] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_esp_np_u; + +/* Define the union csr_ipsutx_tcp_coco_with_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_coco_with_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_coco_with_ts_dw0_u; + +/* Define the union csr_ipsutx_tcp_coco_without_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_coco_without_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_coco_without_ts_dw0_u; + +/* Define the union csr_ipsutx_tcp_coco_dw0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_coco_dw0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_coco_dw0_mask_u; + +/* Define the union csr_ipsutx_ipv6_ext_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_ext_nh : 8; /* [7:0] */ + u32 ipsutx_ipv6_ext_vld : 1; /* [8] */ + u32 rsv_52 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_ext_ctrl_u; + +/* Define the union csr_ipsutx_bgp_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_bgp_dport : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_bgp_dport_u; + +/* Define the union csr_ipsutx_esp_prtl_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_esp_prtl_type : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_esp_prtl_type_u; + +/* Define the union csr_ipsutx_crc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_crc_dat_bit_rev : 1; /* [0] */ + u32 ipsutx_difx_crc_rslt_bit_rev : 1; /* [1] */ + u32 ipsutx_difx_crc_rslt_inv : 1; /* [2] */ + u32 rsv_55 : 1; /* [3] */ + u32 ipsutx_difx_crc2_dat_bit_rev : 1; /* [4] */ + u32 ipsutx_difx_crc2_rslt_bit_rev : 1; /* [5] */ + u32 ipsutx_difx_crc2_rslt_inv : 1; /* [6] */ + u32 rsv_56 : 1; /* [7] */ + u32 ipsutx_iscsi_crc_dat_bit_rev : 1; /* [8] */ + u32 ipsutx_iscsi_crc_rslt_bit_rev : 1; /* [9] */ + u32 ipsutx_iscsi_crc_rslt_inv : 1; /* [10] */ + u32 rsv_57 : 1; /* [11] */ + u32 ipsutx_sctp_crc_dat_bit_rev : 1; /* [12] */ + u32 ipsutx_sctp_crc_rslt_bit_rev : 1; /* [13] */ + u32 ipsutx_sctp_crc_rslt_inv : 1; /* [14] */ + u32 rsv_58 : 4; /* [18:15] */ + u32 ipsutx_difx_cs_rslt_bit_inv : 1; /* [19] */ + u32 ipsutx_difx_cs_rslt_1s_inv : 1; /* [20] */ + u32 ipsutx_difx_cs_rslt_0s_inv : 1; /* [21] */ + u32 rsv_59 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_crc_ctrl_u; + +/* Define the union csr_ipsutx_sctp_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_sctp_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sctp_crc_ini_u; + +/* Define the union csr_ipsutx_iscsi_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_iscsi_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_iscsi_crc_ini_u; + +/* Define the union csr_ipsutx_difx_agm_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_cs_ini : 16; /* [15:0] */ + u32 ipsutx_difx_crc_ini : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_agm_ini_u; + +/* Define the union csr_ipsutx_difx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_verify_special_case_en : 1; /* [0] */ + u32 rsv_60 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_ctrl_u; + +/* Define the union csr_ipsutx_l2nic_fwd_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_pkt_len_max : 19; /* [18:0] */ + u32 rsv_61 : 5; /* [23:19] */ + u32 ipsutx_l2nic_fwd_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_pkt_len_u; + +/* Define the union csr_ipsutx_l2nic_parse_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_parse_pkt_len_max : 19; /* [18:0] */ + u32 rsv_62 : 5; /* [23:19] */ + u32 ipsutx_l2nic_parse_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_parse_pkt_len_u; + +/* Define the union csr_ipsutx_l2nic_gso_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_gso_pkt_len_max : 19; /* [18:0] */ + u32 rsv_63 : 5; /* [23:19] */ + u32 ipsutx_l2nic_gso_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_gso_pkt_len_u; + +/* Define the union csr_ipsutx_ec_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_pkt_len_max : 19; /* [18:0] */ + u32 rsv_64 : 5; /* [23:19] */ + u32 ipsutx_ec_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_pkt_len_u; + +/* Define the union csr_ipsutx_non_l2nic_fwd_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_non_l2nic_fwd_pkt_len_max : 19; /* [18:0] */ + u32 rsv_65 : 5; /* [23:19] */ + u32 ipsutx_non_l2nic_fwd_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_non_l2nic_fwd_pkt_len_u; + +/* Define the union csr_ipsutx_toe_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_toe_pkt_len_max : 19; /* [18:0] */ + u32 rsv_66 : 5; /* [23:19] */ + u32 ipsutx_toe_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_toe_pkt_len_u; + +/* Define the union csr_ipsutx_non_tcp_difx_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_non_tcp_difx_pkt_len_max : 19; /* [18:0] */ + u32 rsv_67 : 5; /* [23:19] */ + u32 ipsutx_non_tcp_difx_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_non_tcp_difx_pkt_len_u; + +/* Define the union csr_ipsutx_ioe_difx_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ioe_difx_pkt_len_max : 19; /* [18:0] */ + u32 rsv_68 : 5; /* [23:19] */ + u32 ipsutx_ioe_difx_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ioe_difx_pkt_len_u; + +/* Define the union csr_ipsutx_ipsec_lb_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipsec_lb_pkt_len_max : 19; /* [18:0] */ + u32 rsv_69 : 5; /* [23:19] */ + u32 ipsutx_ipsec_lb_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipsec_lb_pkt_len_u; + +/* Define the union csr_ipsutx_pkt_lb_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_lb_pkt_len_max : 19; /* [18:0] */ + u32 rsv_70 : 5; /* [23:19] */ + u32 ipsutx_pkt_lb_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_lb_pkt_len_u; + +/* Define the union csr_ipsutx_mpu_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_pkt_len_max : 16; /* [15:0] */ + u32 ipsutx_up_pkt_len_min : 8; /* [23:16] */ + u32 rsv_71 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_pkt_len_u; + +/* Define the union csr_ipsutx_ppop_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_pkt_len_max : 16; /* [15:0] */ + u32 ipsutx_ppop_pkt_len_min : 8; /* [23:16] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_pkt_len_u; + +/* Define the union csr_ipsutx_mpu_push_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_push_len : 4; /* [3:0] */ + u32 rsv_73 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_push_len_u; + +/* Define the union csr_ipsutx_ppop_push_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_push_len : 4; /* [3:0] */ + u32 rsv_74 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_push_len_u; + +/* Define the union csr_ipsutx_push_len_l2f_oth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_push_len_l2f_none : 4; /* [3:0] */ + u32 rsv_75 : 4; /* [7:4] */ + u32 ipsutx_push_len_err : 4; /* [11:8] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 ipsutx_push_len_max : 4; /* [19:16] */ + u32 ipsutx_push_len_gso_no_hdr : 4; /* [23:20] */ + u32 ipsutx_push_len_pldofs_non_zero : 4; /* [27:24] */ + u32 rsv_77 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_push_len_l2f_oth_u; + +/* Define the union csr_ipsutx_push_len_l3f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_push_len_l3f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_push_len_l3f_u; + +/* Define the union csr_ipsutx_push_len_l45f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_push_len_l45f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_push_len_l45f_u; + +/* Define the union csr_ipsutx_l2nic_fwd_dir_push_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_dir_push_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_dir_push_len_u; + +/* Define the union csr_ipsutx_l2nic_fwd_dir_sumop1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_dir_sumop1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_dir_sumop1_u; + +/* Define the union csr_ipsutx_l2nic_fwd_dir_sumop0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_dir_sumop0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_dir_sumop0_u; + +/* Define the union csr_ipsutx_mpu_sum_op_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_totile_sumop : 8; /* [7:0] */ + u32 ipsutx_up_tooq_sumop : 8; /* [15:8] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_sum_op_u; + +/* Define the union csr_ipsutx_ppop_sum_op_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_totile_sumop : 8; /* [7:0] */ + u32 rsv_79 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_sum_op_u; + +/* Define the union csr_ipsutx_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_dmac_zero_cnt_u; + +/* Define the union csr_ipsutx_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_smac_ilgl_cnt_u; + +/* Define the union csr_ipsutx_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_da_sa_equal_cnt_u; + +/* Define the union csr_ipsutx_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_dmac_zero_cnt_u; + +/* Define the union csr_ipsutx_tunnel_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_smac_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_da_sa_equal_cnt_u; + +/* Define the union csr_ipsutx_tunnel_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tcp_land_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_land_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_land_ilgl_cnt_u; + +/* Define the union csr_ipsutx_llc_snap_enc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_llc_snap_enc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_llc_snap_enc_ilgl_cnt_u; + +/* Define the union csr_ipsutx_eth_type_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_eth_type_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_eth_type_ilgl_cnt_u; + +/* Define the union csr_ipsutx_vxlan_gpe_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_vxlan_gpe_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_vxlan_gpe_other_ver_cnt_u; + +/* Define the union csr_ipsutx_geneve_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_geneve_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_geneve_other_ver_cnt_u; + +/* Define the union csr_ipsutx_nsh_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nsh_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nsh_other_ver_cnt_u; + +/* Define the union csr_ipsutx_nsh_len_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nsh_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nsh_len_cnt_u; + +/* Define the union csr_ipsutx_tunnel_nvgre_cvlan_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_nvgre_cvlan_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_nvgre_cvlan_ilgl_cnt_u; + +/* Define the union csr_ipsutx_nvgre_crks_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nvgre_crks_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nvgre_crks_ilgl_cnt_u; + +/* Define the union csr_ipsutx_hdr_len_min_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdr_len_min_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_hdr_len_min_ilgl_cnt_u; + +/* Define the union csr_ipsutx_sctp_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_sctp_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sctp_ilgl_cnt_u; + +/* Define the union csr_ipsutx_gso_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_gso_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_gso_ilgl_cnt_u; + +/* Define the union csr_ipsutx_lli_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_lli_type : 16; /* [15:0] */ + u32 ipsutx_lli_type_vld : 1; /* [16] */ + u32 rsv_80 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_lli_type_u; + +/* Define the union csr_ipsutx_tcam_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_bk_scan_period : 8; /* [7:0] */ + u32 ipsutx_tcam_bk_scan_interval_unit : 8; /* [15:8] */ + u32 ipsutx_tcam_lkup_en : 1; /* [16] */ + u32 rsv_81 : 10; /* [26:17] */ + u32 ipsutx_tcam_mbist_en : 1; /* [27] */ + u32 ipsutx_tcam_mbist_test : 2; /* [29:28] */ + u32 ipsutx_tcam_mbist_t_sel : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_ctrl_u; + +/* Define the union csr_ipsutx_tcam_mbist_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_mbist_done : 1; /* [0] */ + u32 rsv_82 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_mbist_done_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw0_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw1_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw2_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw3_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw0_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw1_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw2_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw3_u; + +/* Define the union csr_ipsutx_tcam_mbist_mem_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_mbist_mem_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_mbist_mem_err_cnt_u; + +/* Define the union csr_ipsutx_tcam_mbist_cmp_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_mbist_cmp_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_mbist_cmp_err_cnt_u; + +/* Define the union csr_ipsutx_uncrt_err_ctrl_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ovfl_ctrl : 1; /* [0] */ + u32 ipsutx_datf_ovfl_ctrl : 1; /* [1] */ + u32 ipsutx_cincf_ovfl_ctrl : 1; /* [2] */ + u32 ipsutx_ciec0f_ovfl_ctrl : 1; /* [3] */ + u32 ipsutx_ciec1f_ovfl_ctrl : 1; /* [4] */ + u32 rsv_83 : 4; /* [8:5] */ + u32 ipsutx_pktlbf_ovfl_ctrl : 1; /* [9] */ + u32 ipsutx_difxf_ovfl_ctrl : 1; /* [10] */ + u32 ipsutx_haf_ovfl_ctrl : 1; /* [11] */ + u32 ipsutx_ecf_ovfl_ctrl : 1; /* [12] */ + u32 ipsutx_ulef_ovfl_ctrl : 1; /* [13] */ + u32 rsv_84 : 1; /* [14] */ + u32 ipsutx_tenqf_ovfl_ctrl : 1; /* [15] */ + u32 rsv_85 : 4; /* [19:16] */ + u32 ipsutx_fatal_err_ctrl : 1; /* [20] */ + u32 rsv_86 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_uncrt_err_ctrl_dw0_u; + +/* Define the union csr_ipsutx_uncrt_err_ctrl_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ram_uncrt_ctrl : 1; /* [0] */ + u32 ipsutx_datf_ram_uncrt_ctrl : 1; /* [1] */ + u32 ipsutx_tcam_uncrt_ctrl : 1; /* [2] */ + u32 ipsutx_tcam_art_uncrt_ctrl : 1; /* [3] */ + u32 ipsutx_cif_ram_uncrt_ctrl : 1; /* [4] */ + u32 ipsutx_difxcalc_ctx6_uncrt_ctrl : 1; /* [5] */ + u32 ipsutx_difxf_ram_uncrt_ctrl : 1; /* [6] */ + u32 ipsutx_haf_ram_uncrt_ctrl : 1; /* [7] */ + u32 ipsutx_ulef_ram_uncrt_ctrl : 1; /* [8] */ + u32 rsv_87 : 1; /* [9] */ + u32 ipsutx_tenqf_ram_uncrt_ctrl : 1; /* [10] */ + u32 ipsutx_difxram_uncrt_ctrl : 1; /* [11] */ + u32 ipsutx_difx_rslt_ctx_uncrt_ctrl : 1; /* [12] */ + u32 ipsutx_segspl_ctx1_uncrt_ctrl : 1; /* [13] */ + u32 ipsutx_tenq_ctx3_uncrt_ctrl : 1; /* [14] */ + u32 rsv_88 : 1; /* [15] */ + u32 ipsutx_cpi_sop_sop_err_ctrl : 1; /* [16] */ + u32 ipsutx_cpi_sop_with_err_ctrl : 1; /* [17] */ + u32 ipsutx_petx_sop_sop_err_ctrl : 1; /* [18] */ + u32 ipsutx_petx_sop_with_err_ctrl : 1; /* [19] */ + u32 ipsutx_petx_1stpdu_1stpdu_err_ctrl : 1; /* [20] */ + u32 ipsutx_petx_1stpdu_with_err_ctrl : 1; /* [21] */ + u32 ipsutx_mpu_sop_sop_err_ctrl : 1; /* [22] */ + u32 ipsutx_mpu_sop_with_err_ctrl : 1; /* [23] */ + u32 ipsutx_mpu_timeout_ctrl : 1; /* [24] */ + u32 ipsutx_ppop_sop_sop_err_ctrl : 1; /* [25] */ + u32 ipsutx_ppop_sop_with_err_ctrl : 1; /* [26] */ + u32 ipsutx_ppop_timeout_ctrl : 1; /* [27] */ + u32 ipsutx_cpi_sor_sor_err_crtl : 1; /* [28] */ + u32 ipsutx_cpi_sor_with_err_ctrl : 1; /* [29] */ + u32 rsv_89 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_uncrt_err_ctrl_dw1_u; + +/* Define the union csr_ipsutx_rammod_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tp_ram_tmod_ctrl : 8; /* [7:0] */ + u32 ipsutx_sp_ram_tmod_ctrl : 7; /* [14:8] */ + u32 ipsutx_mem_power_mode_ctrl : 6; /* [20:15] */ + u32 rsv_90 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rammod_ctrl_u; + +/* Define the union csr_ipsutx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_err_chk_bypass : 1; /* [0] */ + u32 rsv_91 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_err_chk_bypass_u; + +/* Define the union csr_ipsutx_ram_err_inj_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ram_uncrt_err_inj : 1; /* [0] */ + u32 ipsutx_datf_ram_uncrt_err_inj : 1; /* [1] */ + u32 ipsutx_tcam_uncrt_err_inj : 1; /* [2] */ + u32 ipsutx_tcam_art_uncrt_err_inj : 1; /* [3] */ + u32 ipsutx_cif_ram_uncrt_err_inj : 1; /* [4] */ + u32 ipsutx_difxcalc_ctx6_uncrt_err_inj : 1; /* [5] */ + u32 ipsutx_difxf_ram_uncrt_err_inj : 1; /* [6] */ + u32 ipsutx_haf_ram_uncrt_err_inj : 1; /* [7] */ + u32 ipsutx_ulef_ram_uncrt_err_inj : 1; /* [8] */ + u32 rsv_92 : 1; /* [9] */ + u32 ipsutx_tenqf_ram_uncrt_err_inj : 1; /* [10] */ + u32 ipsutx_difxram_uncrt_err_inj : 1; /* [11] */ + u32 ipsutx_difx_rslt_ctx_uncrt_err_inj : 1; /* [12] */ + u32 ipsutx_segspl_ctx1_uncrt_err_inj : 1; /* [13] */ + u32 ipsutx_tenq_ctx3_uncrt_err_inj : 1; /* [14] */ + u32 rsv_93 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_err_inj_dw0_u; + +/* Define the union csr_ipsutx_ram_err_inj_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ram_crt_err_inj : 1; /* [0] */ + u32 ipsutx_datf_ram_crt_err_inj : 1; /* [1] */ + u32 ipsutx_tcam_crt_err_inj : 1; /* [2] */ + u32 ipsutx_tcam_art_crt_err_inj : 1; /* [3] */ + u32 ipsutx_cif_ram_crt_err_inj : 1; /* [4] */ + u32 ipsutx_difxcalc_ctx6_crt_err_inj : 1; /* [5] */ + u32 ipsutx_difxf_ram_crt_err_inj : 1; /* [6] */ + u32 ipsutx_haf_ram_crt_err_inj : 1; /* [7] */ + u32 ipsutx_ulef_ram_crt_err_inj : 1; /* [8] */ + u32 rsv_94 : 1; /* [9] */ + u32 ipsutx_tenqf_ram_crt_err_inj : 1; /* [10] */ + u32 ipsutx_difxram_crt_err_inj : 1; /* [11] */ + u32 ipsutx_difx_rslt_ctx_crt_err_inj : 1; /* [12] */ + u32 ipsutx_segspl_ctx1_crt_err_inj : 1; /* [13] */ + u32 ipsutx_tenq_ctx3_crt_err_inj : 1; /* [14] */ + u32 rsv_95 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_err_inj_dw1_u; + +/* Define the union csr_ipsutx_fifo_th1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_af_th : 7; /* [6:0] */ + u32 rsv_96 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_th1_u; + +/* Define the union csr_ipsutx_fifo_th0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tenqof_af_th : 7; /* [6:0] */ + u32 rsv_97 : 9; /* [15:7] */ + u32 ipsutx_ulef_af_th : 7; /* [22:16] */ + u32 rsv_98 : 1; /* [23] */ + u32 ipsutx_difxf_af_th : 6; /* [29:24] */ + u32 rsv_99 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_th0_u; + +/* Define the union csr_ipsutx_fifo_sts5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 12; /* [11:0] */ + u32 ipsutx_tenqof_cnt : 7; /* [18:12] */ + u32 ipsutx_tenqof_empty : 1; /* [19] */ + u32 ipsutx_tenqof_full : 1; /* [20] */ + u32 ipsutx_tenqof_of : 1; /* [21] */ + u32 ipsutx_tenqof_af : 1; /* [22] */ + u32 rsv_101 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts5_u; + +/* Define the union csr_ipsutx_fifo_sts4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ecf_cnt : 5; /* [4:0] */ + u32 ipsutx_ecf_empty : 1; /* [5] */ + u32 ipsutx_ecf_full : 1; /* [6] */ + u32 ipsutx_ecf_of : 1; /* [7] */ + u32 rsv_102 : 8; /* [15:8] */ + u32 ipsutx_ulef_cnt : 7; /* [22:16] */ + u32 ipsutx_ulef_empty : 1; /* [23] */ + u32 ipsutx_ulef_full : 1; /* [24] */ + u32 ipsutx_ulef_of : 1; /* [25] */ + u32 ipsutx_ulef_af : 1; /* [26] */ + u32 rsv_103 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts4_u; + +/* Define the union csr_ipsutx_fifo_sts3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difxf_cnt : 6; /* [5:0] */ + u32 ipsutx_difxf_empty : 1; /* [6] */ + u32 ipsutx_difxf_full : 1; /* [7] */ + u32 ipsutx_difxf_of : 1; /* [8] */ + u32 ipsutx_difxf_af : 1; /* [9] */ + u32 rsv_104 : 2; /* [11:10] */ + u32 ipsutx_haf_cnt : 7; /* [18:12] */ + u32 ipsutx_haf_empty : 1; /* [19] */ + u32 ipsutx_haf_full : 1; /* [20] */ + u32 ipsutx_haf_of : 1; /* [21] */ + u32 ipsutx_datf_cnt : 6; /* [27:22] */ + u32 ipsutx_datf_empty : 1; /* [28] */ + u32 ipsutx_datf_full : 1; /* [29] */ + u32 ipsutx_datf_of : 1; /* [30] */ + u32 rsv_105 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts3_u; + +/* Define the union csr_ipsutx_fifo_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_cnt : 7; /* [6:0] */ + u32 ipsutx_hdrf_empty : 1; /* [7] */ + u32 ipsutx_hdrf_full : 1; /* [8] */ + u32 ipsutx_hdrf_of : 1; /* [9] */ + u32 ipsutx_hdrf_af : 1; /* [10] */ + u32 rsv_106 : 9; /* [19:11] */ + u32 ipsutx_pktlbf_cnt : 5; /* [24:20] */ + u32 ipsutx_pktlbf_empty : 1; /* [25] */ + u32 ipsutx_pktlbf_full : 1; /* [26] */ + u32 ipsutx_pktlbf_of : 1; /* [27] */ + u32 rsv_107 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts2_u; + +/* Define the union csr_ipsutx_fifo_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cincf_cnt : 6; /* [5:0] */ + u32 ipsutx_cincf_empty : 1; /* [6] */ + u32 ipsutx_cincf_full : 1; /* [7] */ + u32 ipsutx_cincf_of : 1; /* [8] */ + u32 ipsutx_ciec0f_cnt : 6; /* [14:9] */ + u32 ipsutx_ciec0f_empty : 1; /* [15] */ + u32 ipsutx_ciec0f_full : 1; /* [16] */ + u32 ipsutx_ciec0f_of : 1; /* [17] */ + u32 rsv_108 : 2; /* [19:18] */ + u32 ipsutx_ciec1f_cnt : 6; /* [25:20] */ + u32 ipsutx_ciec1f_empty : 1; /* [26] */ + u32 ipsutx_ciec1f_full : 1; /* [27] */ + u32 ipsutx_ciec1f_of : 1; /* [28] */ + u32 rsv_109 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts1_u; + +/* Define the union csr_ipsutx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ucerr_cnt_u; + +/* Define the union csr_ipsutx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_cerr_cnt_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw0 : 6; /* [5:0] */ + u32 rsv_110 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw0_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw1_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw2_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw3_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw4_u; + +/* Define the union csr_ipsutx_tcam_ctrl_bus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_ctrl_bus : 10; /* [9:0] */ + u32 rsv_111 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_ctrl_bus_u; + +/* Define the union csr_ipsutx_rcv_cpb_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_rcv_cpb_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rcv_cpb_bp_cnt_u; + +/* Define the union csr_ipsutx_mpu_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_mpu_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_bp_cnt_u; + +/* Define the union csr_ipsutx_ppop_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_bp_cnt_u; + +/* Define the union csr_ipsutx_difx_grd_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_grd_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_grd_ilgl_cnt_u; + +/* Define the union csr_ipsutx_difx_ref_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_ref_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_ref_ilgl_cnt_u; + +/* Define the union csr_ipsutx_difx_app_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_app_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_app_ilgl_cnt_u; + +/* Define the union csr_ipsutx_gso_sctp_plofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_gso_sctp_plofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_gso_sctp_plofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tcp_sd_ofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_sd_ofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_sd_ofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_l2nic_plofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_plofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_plofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ioe_rsp_hdr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ioe_rsp_hdr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ioe_rsp_hdr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_pkt_lb_md_hdr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_lb_md_hdr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_lb_md_hdr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_pdu_sd_ofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pdu_sd_ofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pdu_sd_ofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_cry_err1_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cry_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cry_err1_ilgl_cnt_u; + +/* Define the union csr_ipsutx_cry_err2_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cry_err2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cry_err2_ilgl_cnt_u; + +/* Define the union csr_ipsutx_cry_bd_ilgl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cry_bd_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cry_bd_ilgl_ilgl_cnt_u; + +/* Define the union csr_ipsutx_rx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_rx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rx_pkt_cnt_u; + +/* Define the union csr_ipsutx_tx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tx_pkt_cnt_u; + +/* Define the union csr_ipsutx_edit_type_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_edit_type_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_edit_type_pkt_cnt_u; + +/* Define the union csr_ipsutx_edit_type_cry_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_edit_type_cry_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_edit_type_cry_pkt_cnt_u; + +/* Define the union csr_ipsutx_patn_id_ext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_patn_id_ext : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_patn_id_ext_u; + +/* Define the union csr_ipsutx_patn_id_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_patn_id_int : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_patn_id_int_u; + +/* Define the union csr_ipsutx_err_patn_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_patn_id : 4; /* [3:0] */ + u32 rsv_112 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_patn_id_u; + +/* Define the union csr_ipsutx_virtio_patn_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_virtio_patn_id : 4; /* [3:0] */ + u32 rsv_113 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_virtio_patn_id_u; + +/* Define the union csr_ipsutx_difx_err_dfx_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_err_dfx_clr : 1; /* [0] */ + u32 rsv_114 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_dfx_clr_u; + +/* Define the union csr_ipsutx_difx_err_info_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_guard_err : 1; /* [0] */ + u32 ipsutx_difx_app_err : 1; /* [1] */ + u32 ipsutx_difx_ref_err : 1; /* [2] */ + u32 rsv_115 : 1; /* [3] */ + u32 ipsutx_difx_vrf_type : 2; /* [5:4] */ + u32 rsv_116 : 2; /* [7:6] */ + u32 ipsutx_difx_err_schnl : 5; /* [12:8] */ + u32 rsv_117 : 3; /* [15:13] */ + u32 ipsutx_difx_task_tag : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw0_u; + +/* Define the union csr_ipsutx_difx_err_info_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_rcv_guard : 16; /* [15:0] */ + u32 ipsutx_difx_rcv_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw1_u; + +/* Define the union csr_ipsutx_difx_err_info_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_rcv_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw2_u; + +/* Define the union csr_ipsutx_difx_err_info_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_exp_guard : 16; /* [15:0] */ + u32 ipsutx_difx_exp_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw3_u; + +/* Define the union csr_ipsutx_difx_err_info_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_exp_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw4_u; + +#endif // IPSUTX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_reg_offset.h new file mode 100644 index 000000000..6e99fe2bf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_reg_offset.h @@ -0,0 +1,429 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_addr_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/09/06 10:44:42 Create file +// ****************************************************************************** + +#ifndef IPSUTX_REG_OFFSET_H +#define IPSUTX_REG_OFFSET_H + +/* IPSUTX_CSR Base address of Module's Register */ +#define CSR_IPSUTX_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* IPSUTX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_IPSUTX_CSR_IPSUTX_FPGA_VER_REG (CSR_IPSUTX_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EMU_VER_REG (CSR_IPSUTX_CSR_BASE + 0x4) /* 版本寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INITCTAB_START_REG (CSR_IPSUTX_CSR_BASE + 0x8) /* 配置表初始化使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INITCTAB_DONE_REG (CSR_IPSUTX_CSR_BASE + 0xC) /* 配置表初始化状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_VECTOR_REG (CSR_IPSUTX_CSR_BASE + 0x10) /* Interrupt Vector Register */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_REG (CSR_IPSUTX_CSR_BASE + 0x14) /* Interrupt Data Register */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_EN_REG (CSR_IPSUTX_CSR_BASE + 0x18) /* Interrupt Mask Register */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_UCERR_REG (CSR_IPSUTX_CSR_BASE + 0x1C) /* RAM不可纠错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CERR_REG (CSR_IPSUTX_CSR_BASE + 0x20) /* RAM可纠错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_OF_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x24) /* FIFO溢出错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SOP_EOP_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x28) /* SOP/EOP检查错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x2C) /* DIF/DIX校验错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PARSE_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x30) /* 报文解析检查错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SCHNL_CFG_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x34) /* 报文通道配置错误中断寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x50) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x54) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x58) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x5C) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x80) /* 间接寻址控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_TIMEOUT_REG (CSR_IPSUTX_CSR_BASE + 0x84) /* 间接寻址TIMEOUT配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_0_REG (CSR_IPSUTX_CSR_BASE + 0x88) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_1_REG (CSR_IPSUTX_CSR_BASE + 0x8C) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_2_REG (CSR_IPSUTX_CSR_BASE + 0x90) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_3_REG (CSR_IPSUTX_CSR_BASE + 0x94) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_4_REG (CSR_IPSUTX_CSR_BASE + 0x98) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_5_REG (CSR_IPSUTX_CSR_BASE + 0x9C) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_6_REG (CSR_IPSUTX_CSR_BASE + 0xA0) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_7_REG (CSR_IPSUTX_CSR_BASE + 0xA4) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_8_REG (CSR_IPSUTX_CSR_BASE + 0xA8) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_9_REG (CSR_IPSUTX_CSR_BASE + 0xAC) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_10_REG (CSR_IPSUTX_CSR_BASE + 0xB0) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_11_REG (CSR_IPSUTX_CSR_BASE + 0xB4) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_12_REG (CSR_IPSUTX_CSR_BASE + 0xB8) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_13_REG (CSR_IPSUTX_CSR_BASE + 0xBC) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_14_REG (CSR_IPSUTX_CSR_BASE + 0xC0) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_15_REG (CSR_IPSUTX_CSR_BASE + 0xC4) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x100) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x104) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x108) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x10C) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_EC_CH_REG (CSR_IPSUTX_CSR_BASE + 0x110) /* EC通道配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_VIRTIO_CH_REG (CSR_IPSUTX_CSR_BASE + 0x114) /* VirtIO-net通道配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_BANDWIDTH_CFG_REG (CSR_IPSUTX_CSR_BASE + 0x118) /* 带宽配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_MPU_TIMER_REG (CSR_IPSUTX_CSR_BASE + 0x11C) /* PPOP/MPU接口计时器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_DIFX_CH_EN_REG (CSR_IPSUTX_CSR_BASE + 0x120) /* DIFX通道配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_SOP_EOP_ST_REG (CSR_IPSUTX_CSR_BASE + 0x200) /* SOP/EOP检测状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x204) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x208) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x20C) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x210) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x214) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x218) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_1STPDU_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x21C) /* 1STPDU_WITH_ERR错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_1STPDU_1STPDU_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x220) /* 1STPDU_1STPDU错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x224) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x228) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x22C) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x230) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x234) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x238) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x23C) /* 接收超短报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x240) /* 接收超长报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x244) /* 接收超短报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x248) /* 接收超长报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x24C) /* 接收超短报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x250) /* 接收超长报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_MPU_TIMEOUT_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x254) /* PPOP/MPU报文超时错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SOR_EOR_ST_REG (CSR_IPSUTX_CSR_BASE + 0x258) /* SOR/EOR检测状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOR_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x25C) /* SOR_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOR_SOR_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x260) /* SOR_SOR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EVTAG_TPID1_REG (CSR_IPSUTX_CSR_BASE + 0x300) /* ETAG/VNTAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EVTAG_TPID0_REG (CSR_IPSUTX_CSR_BASE + 0x304) /* ETAG/VNTAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SVLAN_TPID2_REG (CSR_IPSUTX_CSR_BASE + 0x308) /* SVLAN TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SVLAN_TPID1_REG (CSR_IPSUTX_CSR_BASE + 0x30C) /* SVLAN TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SVLAN_TPID0_REG (CSR_IPSUTX_CSR_BASE + 0x310) /* SVLAN TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CVLAN_TPID2_REG (CSR_IPSUTX_CSR_BASE + 0x314) /* CVLAN-TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CVLAN_TPID1_REG (CSR_IPSUTX_CSR_BASE + 0x318) /* CVLAN-TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CVLAN_TPID0_REG (CSR_IPSUTX_CSR_BASE + 0x31C) /* CVLAN-TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_8023_MAX_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x320) /* 802.3最大长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_8023_JUMBO_CFG_REG (CSR_IPSUTX_CSR_BASE + 0x324) /* 802.3Jumbo帧配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2_DMAC_ETH_CHK_EN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x328) /* L2报文DMAC/ETH检测使能配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IGMPV4_DIP_CHK_EN_REG (CSR_IPSUTX_CSR_BASE + 0x32C) /* IGMPv4 DIP检测控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_SPEC_MC_REG (CSR_IPSUTX_CSR_BASE + 0x330) /* IPv6指定多播寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ROCEV2_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x334) /* RoCEV2目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_NATT_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x338) /* NATT目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_VXLAN_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x33C) /* VXLAN目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_VXLAN_GPE_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x340) /* VXLAN GPE目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_GENEVE_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x344) /* GENEVE目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_NP_REG (CSR_IPSUTX_CSR_BASE + 0x348) /* IPv4 Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_NP_REG (CSR_IPSUTX_CSR_BASE + 0x34C) /* IPv6 Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_ETHERNET_NP_REG (CSR_IPSUTX_CSR_BASE + 0x350) /* Ethernet Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_IOAM_NP_REG (CSR_IPSUTX_CSR_BASE + 0x354) /* IOAM Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_NP_REG (CSR_IPSUTX_CSR_BASE + 0x358) /* INT Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_NSH_NP_REG (CSR_IPSUTX_CSR_BASE + 0x35C) /* NSH Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_AH_NP_REG (CSR_IPSUTX_CSR_BASE + 0x360) /* AH Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_ESP_NP_REG (CSR_IPSUTX_CSR_BASE + 0x364) /* ESP Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_COCO_WITH_TS_DW0_REG \ + (CSR_IPSUTX_CSR_BASE + 0x368) /* 带时戳的TCP COCO DW0配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_COCO_WITHOUT_TS_DW0_REG \ + (CSR_IPSUTX_CSR_BASE + 0x36C) /* 不带时戳的TCP COCO DW0配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_COCO_DW0_MASK_REG (CSR_IPSUTX_CSR_BASE + 0x370) /* TCP COCO DW0掩码配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_EXT_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x374) /* IPv6扩展头配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_BGP_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x378) /* BGP目的TCP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_ESP_PRTL_TYPE_REG (CSR_IPSUTX_CSR_BASE + 0x37C) /* ESP Protocol Type号 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRC_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x400) /* IPSUTX CRC控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SCTP_CRC_INI_REG (CSR_IPSUTX_CSR_BASE + 0x404) /* SCTP报文CRC 初始值寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ISCSI_CRC_INI_REG (CSR_IPSUTX_CSR_BASE + 0x408) /* iscsi报文头CRC 初始值寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_AGM_INI_REG (CSR_IPSUTX_CSR_BASE + 0x454) /* DIX/DIF算法初始值配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x458) /* DIF/DIX控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x45C) /* L2NIC_FWD_DIRECT报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_PARSE_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x460) /* L2NIC_PARSE_ONLY报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_GSO_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x464) /* L2NIC_GSO报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x468) /* EC报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NON_L2NIC_FWD_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x46C) /* NON-L2NIC_FWD_DIRECT报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TOE_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x470) /* TOE报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NON_TCP_DIFX_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x474) /* NON-TCP_PKT_DIFX报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IOE_DIFX_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x478) /* IOE_DIFX报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPSEC_LB_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x47C) /* IPSEC_LB报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_LB_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x480) /* PKT_LB报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x484) /* UP报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x488) /* PPOP报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PUSH_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x48C) /* UP报文的推送长度 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PUSH_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x490) /* PPOP报文的推送长度 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L2F_OTH_REG \ + (CSR_IPSUTX_CSR_BASE + 0x494) /* L2 Final和其他报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_0_REG (CSR_IPSUTX_CSR_BASE + 0x498) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_1_REG (CSR_IPSUTX_CSR_BASE + 0x49C) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_2_REG (CSR_IPSUTX_CSR_BASE + 0x4A0) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_3_REG (CSR_IPSUTX_CSR_BASE + 0x4A4) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_0_REG (CSR_IPSUTX_CSR_BASE + 0x4A8) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_1_REG (CSR_IPSUTX_CSR_BASE + 0x4AC) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_2_REG (CSR_IPSUTX_CSR_BASE + 0x4B0) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_3_REG (CSR_IPSUTX_CSR_BASE + 0x4B4) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_DIR_PUSH_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x4B8) /* L2NIC_FWD_DIRECT报文的推送长度 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_DIR_SUMOP1_REG (CSR_IPSUTX_CSR_BASE + 0x4BC) /* L2NIC_FWD_DIRECT报文的SUMOP */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_DIR_SUMOP0_REG (CSR_IPSUTX_CSR_BASE + 0x4C0) /* L2NIC_FWD_DIRECT报文的SUMOP */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_SUM_OP_REG (CSR_IPSUTX_CSR_BASE + 0x4D0) /* MPU报文SUM_OP配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_SUM_OP_REG (CSR_IPSUTX_CSR_BASE + 0x4D4) /* PPOP报文SUM_OP配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DMAC_ZERO_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x500) /* 目的MAC为0错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SMAC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x504) /* 源MAC错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DA_SA_EQUAL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x508) /* 源目的MAC相等报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ETH_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x50C) /* ETH_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_DMAC_ZERO_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x510) /* 目的MAC为0错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_SMAC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x514) /* 源MAC错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_DA_SA_EQUAL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x518) /* 源目的MAC相等报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_ETH_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x51C) /* ETH_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x520) /* IPV4_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_IHL_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x524) /* IPV4_IHL_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_SIP_DIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x528) /* IPV4_SIP_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x52C) /* IPV4_SIP_MC_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x530) /* IPV4_SIP_LB_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x534) /* IPV4_DIP_LB_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_DIP_ZERO_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x538) /* IPV4_DIP_ZERO_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x53C) /* IPV4_DIP_RSV_ADDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_UDP_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x540) /* IPV4_UDP_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x544) /* IPV4_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x548) /* IPV6_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_SIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x54C) /* IPV6_SIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_DIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x550) /* IPV6_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x554) /* IPV6_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x558) /* IPV4_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_IHL_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x55C) /* IPV4_IHL_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_SIP_DIP_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x560) /* IPV4_SIP_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x564) /* IPV4_SIP_MC_ILGL计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x568) /* IPV4_SIP_LB_ILGL计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x56C) /* IPV4_DIP_LB_ILGL计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_DIP_ZERO_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x570) /* IPV4_DIP_ZERO_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x574) /* IPV4_DIP_RSV_ADDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_UDP_LEN_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x578) /* IPV4_UDP_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x57C) /* IPV4_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x580) /* IPV6_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_SIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x584) /* IPV6_SIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_DIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x588) /* IPV6_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x58C) /* IPV6_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_LAND_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x590) /* TCP_LAND_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLC_SNAP_ENC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x594) /* LLC_SNAP_ENC_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ETH_TYPE_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x598) /* ETH_TYPE_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_VXLAN_GPE_OTHER_VER_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x59C) /* VXLAN_GPE_OTHER_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_GENEVE_OTHER_VER_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5A0) /* GENEVE_OTHER_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NSH_OTHER_VER_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5A4) /* NSH_OTHER_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NSH_LEN_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5A8) /* NSH_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_NVGRE_CVLAN_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x5AC) /* nvGRE报文内层CVLAN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NVGRE_CRKS_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5B0) /* NVGRE_CRKS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_HDR_LEN_MIN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5B4) /* PKT_HDR_LEN_MIN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SCTP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5B8) /* SCTP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_GSO_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5BC) /* GSO_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_0_REG (CSR_IPSUTX_CSR_BASE + 0x600) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_1_REG (CSR_IPSUTX_CSR_BASE + 0x604) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_2_REG (CSR_IPSUTX_CSR_BASE + 0x608) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_3_REG (CSR_IPSUTX_CSR_BASE + 0x60C) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_4_REG (CSR_IPSUTX_CSR_BASE + 0x610) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_5_REG (CSR_IPSUTX_CSR_BASE + 0x614) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_6_REG (CSR_IPSUTX_CSR_BASE + 0x618) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_7_REG (CSR_IPSUTX_CSR_BASE + 0x61C) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x620) /* TCAM控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_MBIST_DONE_REG (CSR_IPSUTX_CSR_BASE + 0x624) /* TCAM MBIST完成状态信号 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x628) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x62C) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x630) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x634) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x638) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x63C) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x640) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x644) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_MBIST_MEM_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x648) /* TCAM MBIST MEM错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_MBIST_CMP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x64C) /* TCAM MBIST匹配错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_UNCRT_ERR_CTRL_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x700) /* IPSUTX致命错误控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_UNCRT_ERR_CTRL_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x704) /* IPSUTX致命错误控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAMMOD_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x708) /* IPSUTX模块RAM MOD控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_ERR_CHK_BYPASS_REG \ + (CSR_IPSUTX_CSR_BASE + 0x70C) /* IPSUTX模块RAM错误检查BYPASS寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_ERR_INJ_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x710) /* IPSUTX模块RAM错误注入寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_ERR_INJ_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x714) /* IPSUTX模块RAM错误注入寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_TH1_REG (CSR_IPSUTX_CSR_BASE + 0x718) /* IPSUTX FIFO门限寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_TH0_REG (CSR_IPSUTX_CSR_BASE + 0x71C) /* IPSUTX FIFO门限寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS5_REG (CSR_IPSUTX_CSR_BASE + 0x720) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS4_REG (CSR_IPSUTX_CSR_BASE + 0x724) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS3_REG (CSR_IPSUTX_CSR_BASE + 0x728) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS2_REG (CSR_IPSUTX_CSR_BASE + 0x72C) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS1_REG (CSR_IPSUTX_CSR_BASE + 0x730) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_UCERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x738) /* IPSUTX RAM不可纠错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x73C) /* IPSUTX RAM可纠错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x740) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x744) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x748) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x74C) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW4_REG (CSR_IPSUTX_CSR_BASE + 0x750) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_CTRL_BUS_REG (CSR_IPSUTX_CSR_BASE + 0x754) /* IPSUTX TCAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RCV_CPB_BP_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x800) /* IPSUTX接收CPB反压次数计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_BP_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x804) /* 发送至MPU的反压计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_BP_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x808) /* 发送至PPOP的反压计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_GRD_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x80C) /* DIFX_GRD_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_REF_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x810) /* DIFX_REF_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_APP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x814) /* DIFX_APP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_GSO_SCTP_PLOFS_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x818) /* GSO/SCTP报文PLOFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_SD_OFS_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x81C) /* IOE/PKT_LB报文TCP_SD_OFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_PLOFS_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x820) /* L2NIC报文PLOFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IOE_RSP_HDR_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x824) /* IOE报文的RSP_HDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_LB_MD_HDR_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x828) /* PKT_LB报文和IPSEC报文的MD_HDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PDU_SD_OFS_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x82C) /* IOE/NTCP报文PDU_SD_OFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRY_ERR1_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x830) /* IPSUTX入口的加密模块的错误CRYPTOTX_ERR1个数计数器，基于包统计。 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRY_ERR2_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x834) /* IPSUTX入口的加密模块的错误CRYPTOTX_ERR2个数计数器，基于包统计。 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRY_BD_ILGL_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x838) /* IPSUTX入口的加密模块的错误CRYPTOTX_BD_ILGL个数计数器，基于包统计。 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_0_REG (CSR_IPSUTX_CSR_BASE + 0x900) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_1_REG (CSR_IPSUTX_CSR_BASE + 0x904) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_2_REG (CSR_IPSUTX_CSR_BASE + 0x908) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_3_REG (CSR_IPSUTX_CSR_BASE + 0x90C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_4_REG (CSR_IPSUTX_CSR_BASE + 0x910) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_5_REG (CSR_IPSUTX_CSR_BASE + 0x914) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_6_REG (CSR_IPSUTX_CSR_BASE + 0x918) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_7_REG (CSR_IPSUTX_CSR_BASE + 0x91C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_8_REG (CSR_IPSUTX_CSR_BASE + 0x920) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_9_REG (CSR_IPSUTX_CSR_BASE + 0x924) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_10_REG (CSR_IPSUTX_CSR_BASE + 0x928) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_11_REG (CSR_IPSUTX_CSR_BASE + 0x92C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_12_REG (CSR_IPSUTX_CSR_BASE + 0x930) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_13_REG (CSR_IPSUTX_CSR_BASE + 0x934) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_14_REG (CSR_IPSUTX_CSR_BASE + 0x938) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_15_REG (CSR_IPSUTX_CSR_BASE + 0x93C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_16_REG (CSR_IPSUTX_CSR_BASE + 0x940) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_17_REG (CSR_IPSUTX_CSR_BASE + 0x944) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_18_REG (CSR_IPSUTX_CSR_BASE + 0x948) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_19_REG (CSR_IPSUTX_CSR_BASE + 0x94C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_20_REG (CSR_IPSUTX_CSR_BASE + 0x950) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_21_REG (CSR_IPSUTX_CSR_BASE + 0x954) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_22_REG (CSR_IPSUTX_CSR_BASE + 0x958) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_23_REG (CSR_IPSUTX_CSR_BASE + 0x95C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_0_REG (CSR_IPSUTX_CSR_BASE + 0x964) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_1_REG (CSR_IPSUTX_CSR_BASE + 0x968) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_2_REG (CSR_IPSUTX_CSR_BASE + 0x96C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_3_REG (CSR_IPSUTX_CSR_BASE + 0x970) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_4_REG (CSR_IPSUTX_CSR_BASE + 0x974) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_5_REG (CSR_IPSUTX_CSR_BASE + 0x978) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_6_REG (CSR_IPSUTX_CSR_BASE + 0x97C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_7_REG (CSR_IPSUTX_CSR_BASE + 0x980) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_8_REG (CSR_IPSUTX_CSR_BASE + 0x984) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_9_REG (CSR_IPSUTX_CSR_BASE + 0x988) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_10_REG (CSR_IPSUTX_CSR_BASE + 0x98C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_11_REG (CSR_IPSUTX_CSR_BASE + 0x990) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_12_REG (CSR_IPSUTX_CSR_BASE + 0x994) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_13_REG (CSR_IPSUTX_CSR_BASE + 0x998) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_14_REG (CSR_IPSUTX_CSR_BASE + 0x99C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_15_REG (CSR_IPSUTX_CSR_BASE + 0x9A0) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_16_REG (CSR_IPSUTX_CSR_BASE + 0x9A4) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_17_REG (CSR_IPSUTX_CSR_BASE + 0x9A8) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_18_REG (CSR_IPSUTX_CSR_BASE + 0x9AC) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_19_REG (CSR_IPSUTX_CSR_BASE + 0x9B0) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_20_REG (CSR_IPSUTX_CSR_BASE + 0x9B4) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_21_REG (CSR_IPSUTX_CSR_BASE + 0x9B8) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_22_REG (CSR_IPSUTX_CSR_BASE + 0x9BC) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_23_REG (CSR_IPSUTX_CSR_BASE + 0x9C0) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_0_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9C8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_1_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9CC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_2_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9D0) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_3_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9D4) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_4_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9D8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_5_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9DC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_6_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9E0) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_7_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9E4) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_8_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9E8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_9_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9EC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_10_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9F0) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_11_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9F4) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_12_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9F8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_13_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9FC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_14_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA00) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_15_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA04) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_0_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA08) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_1_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA0C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_2_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA10) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_3_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA14) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_4_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA18) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_5_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA1C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_6_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA20) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_7_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA24) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_8_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA28) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_9_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA2C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_10_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA30) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_11_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA34) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_12_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA38) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_13_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA3C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_14_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA40) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_15_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA44) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_0_REG (CSR_IPSUTX_CSR_BASE + 0xB00) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_1_REG (CSR_IPSUTX_CSR_BASE + 0xB04) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_2_REG (CSR_IPSUTX_CSR_BASE + 0xB08) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_3_REG (CSR_IPSUTX_CSR_BASE + 0xB0C) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_4_REG (CSR_IPSUTX_CSR_BASE + 0xB10) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_5_REG (CSR_IPSUTX_CSR_BASE + 0xB14) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_6_REG (CSR_IPSUTX_CSR_BASE + 0xB18) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_7_REG (CSR_IPSUTX_CSR_BASE + 0xB1C) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_0_REG (CSR_IPSUTX_CSR_BASE + 0xB20) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_1_REG (CSR_IPSUTX_CSR_BASE + 0xB24) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_2_REG (CSR_IPSUTX_CSR_BASE + 0xB28) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_3_REG (CSR_IPSUTX_CSR_BASE + 0xB2C) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_PATN_ID_REG (CSR_IPSUTX_CSR_BASE + 0xB30) /* 报文解析出错时的外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_VIRTIO_PATN_ID_REG \ + (CSR_IPSUTX_CSR_BASE + 0xB34) /* 报文存在VirtIO-net时的外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_DFX_CLR_REG (CSR_IPSUTX_CSR_BASE + 0xC00) /* IPSUTX DIF/DIX错误DFX清除寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW0_REG (CSR_IPSUTX_CSR_BASE + 0xC04) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW1_REG (CSR_IPSUTX_CSR_BASE + 0xC08) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW2_REG (CSR_IPSUTX_CSR_BASE + 0xC0C) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW3_REG (CSR_IPSUTX_CSR_BASE + 0xC10) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW4_REG (CSR_IPSUTX_CSR_BASE + 0xC14) /* IPSUTX DIF/DIX错误信息 */ + +#endif // IPSUTX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_c_union_define.h new file mode 100644 index 000000000..1a9b59da5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_c_union_define.h @@ -0,0 +1,741 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : lcam_c_union_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/14 16:55:24 Create file +// ****************************************************************************** + +#ifndef LCAM_C_UNION_DEFINE_H +#define LCAM_C_UNION_DEFINE_H + +/* Define the union csr_lcam_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_version_u; + +/* Define the union csr_lcam_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_addr : 5; /* [4:0] */ + u32 rsv_0 : 19; /* [23:5] */ + u32 lcam_indrect_tab : 1; /* [24] */ + u32 rsv_1 : 3; /* [27:25] */ + u32 lcam_indrect_status : 2; /* [29:28] */ + u32 lcam_indrect_mode : 1; /* [30] */ + u32 lcam_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_ctrl_u; + +/* Define the union csr_lcam_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_timeout_u; + +/* Define the union csr_lcam_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_data_0_u; + +/* Define the union csr_lcam_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_data_1_u; + +/* Define the union csr_lcam_indrect_data_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_data_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_data_2_u; + +/* Define the union csr_lcam_scan_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_scan_period : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_scan_period_u; + +/* Define the union csr_lcam_scan_period_gra_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_scan_period_gra : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_scan_period_gra_u; + +/* Define the union csr_lcam_scan_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_scan_en : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_scan_en_u; + +/* Define the union csr_lcam_common_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_block_gating : 5; /* [4:0] */ + u32 rp_lcam_tcam_init_en : 1; /* [5] */ + u32 rp_lcam_ag_init_en : 1; /* [6] */ + u32 rp_check_en : 1; /* [7] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 sp_ret1n : 1; /* [15] */ + u32 rp_lcam_cnt_src_sel : 1; /* [16] */ + u32 rp_lcam_cnt_en : 1; /* [17] */ + u32 rp_lcam_resp_e0_en : 1; /* [18] */ + u32 rp_tcam_search_low_power_en : 1; /* [19] */ + u32 rp_rx_async_fifo_wr_bp_thrd : 4; /* [23:20] */ + u32 rp_tx_async_fifo_wr_bp_thrd : 4; /* [27:24] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_common_cfg_u; + +/* Define the union csr_lcam_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_uncrt_err_clr : 1; /* [0] */ + u32 rp_lcam_api_drop_err_mask : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_uncrt_err_u; + +/* Define the union csr_lcam_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_tcam_wrr_weight : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_wrr_weight_u; + +/* Define the union csr_lcam_ring_rx_rqst_correct_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_rx_rqst_correct_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_rx_rqst_correct_cnt_u; + +/* Define the union csr_lcam_ring_rx_rqst_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_rx_rqst_err_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_rx_rqst_err_cnt_u; + +/* Define the union csr_lcam_ring_rx_rqst_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_rx_rqst_drop_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_rx_rqst_drop_cnt_u; + +/* Define the union csr_lcam_ring_tx_rqst_correct_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_tx_rqst_correct_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_tx_rqst_correct_cnt_u; + +/* Define the union csr_lcam_ring_tx_rqst_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_tx_rqst_err_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_tx_rqst_err_cnt_u; + +/* Define the union csr_lcam_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_int_vector_u; + +/* Define the union csr_lcam_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 7; /* [6:0] */ + u32 rsv_6 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_int_u; + +/* Define the union csr_lcam_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 7; /* [6:0] */ + u32 rsv_7 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_int_mask_u; + +/* Define the union csr_lcam_ring_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_drop_err : 1; /* [0] */ + u32 api_drop_merr : 1; /* [1] */ + u32 miss_sop_err : 1; /* [2] */ + u32 miss_sop_merr : 1; /* [3] */ + u32 miss_eop_err : 1; /* [4] */ + u32 miss_eop_merr : 1; /* [5] */ + u32 illegal_op_id_err : 1; /* [6] */ + u32 illegal_op_id_merr : 1; /* [7] */ + u32 api_overlong_err : 1; /* [8] */ + u32 api_overlong_merr : 1; /* [9] */ + u32 api_tooshort_err : 1; /* [10] */ + u32 api_tooshort_merr : 1; /* [11] */ + u32 req_asyn_overflow_err : 1; /* [12] */ + u32 req_asyn_overflow_merr : 1; /* [13] */ + u32 rsp_asyn_overflow_err : 1; /* [14] */ + u32 rsp_asyn_overflow_merr : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_itf_err_u; + +/* Define the union csr_lcam_ring_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_drop_err_mask : 1; /* [0] */ + u32 miss_sop_err_mask : 1; /* [1] */ + u32 miss_eop_err_mask : 1; /* [2] */ + u32 illegal_op_id_err_mask : 1; /* [3] */ + u32 api_overlong_err_mask : 1; /* [4] */ + u32 api_tooshort_err_mask : 1; /* [5] */ + u32 req_asyn_overflow_err_mask : 1; /* [6] */ + u32 rsp_asyn_overflow_err_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_itf_err_mask_u; + +/* Define the union csr_lcam_ad_ecc_one_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 17; /* [18:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ad_ecc_one_bit_err_u; + +/* Define the union csr_lcam_ad_ecc_two_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 17; /* [18:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ad_ecc_two_bit_err_u; + +/* Define the union csr_lcam_tcam_ecc_one_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 22; /* [23:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_tcam_ecc_one_bit_err_u; + +/* Define the union csr_lcam_tcam_ecc_two_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 22; /* [23:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_tcam_ecc_two_bit_err_u; + +/* Define the union csr_lcam_cmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ag_addr_outof_range_err : 1; /* [0] */ + u32 ag_addr_outof_range_merr : 1; /* [1] */ + u32 tcam_op_addr_cmd_err : 1; /* [2] */ + u32 tcam_op_addr_cmd_merr : 1; /* [3] */ + u32 move_new_eq_old_err : 1; /* [4] */ + u32 move_new_eq_old_merr : 1; /* [5] */ + u32 move_len_outof_err : 1; /* [6] */ + u32 move_len_outof_merr : 1; /* [7] */ + u32 move_old_outof_err : 1; /* [8] */ + u32 move_old_outof_merr : 1; /* [9] */ + u32 move_new_outof_err : 1; /* [10] */ + u32 move_new_outof_merr : 1; /* [11] */ + u32 move_len_zero_err : 1; /* [12] */ + u32 move_len_zero_merr : 1; /* [13] */ + u32 target_blk_gating_err : 1; /* [14] */ + u32 target_blk_gating_merr : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_cmd_err_u; + +/* Define the union csr_lcam_cmd_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ag_addr_outof_range_err_mask : 1; /* [0] */ + u32 tcam_op_addr_cmd_err_mask : 1; /* [1] */ + u32 move_new_eq_old_err_mask : 1; /* [2] */ + u32 move_len_outof_err_mask : 1; /* [3] */ + u32 move_old_outof_err_mask : 1; /* [4] */ + u32 move_new_outof_err_mask : 1; /* [5] */ + u32 move_len_zero_err_mask : 1; /* [6] */ + u32 target_blk_gating_err_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_cmd_err_mask_u; + +/* Define the union csr_lcam_init_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_tcam_init_done : 1; /* [0] */ + u32 lcam_ag_init_done : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_init_status_u; + +/* Define the union csr_lcam_ecc_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_ad_one_bit_err_inj_req : 1; /* [0] */ + u32 rp_lcam_ad_two_bit_err_inj_req : 1; /* [1] */ + u32 rp_lcam_tcam_one_bit_err_inj_req : 1; /* [2] */ + u32 rp_lcam_tcam_two_bit_err_inj_req : 1; /* [3] */ + u32 rsv_8 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ecc_err_inj_u; + +/* Define the union csr_lcam_src_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_chk_err : 1; /* [0] */ + u32 src_chk_merr : 1; /* [1] */ + u32 sticky : 5; /* [6:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_err_u; + +/* Define the union csr_lcam_src_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_err_mask : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_err_mask_u; + +/* Define the union csr_lcam_src_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_cfg : 9; /* [8:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_cfg_u; + +/* Define the union csr_lcam_src_cfg_node_id0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 node_id_tile0 : 5; /* [4:0] */ + u32 node_id_tile1 : 5; /* [9:5] */ + u32 node_id_tile2 : 5; /* [14:10] */ + u32 node_id_tile3 : 5; /* [19:15] */ + u32 node_id_tile4 : 5; /* [24:20] */ + u32 node_id_tile5 : 5; /* [29:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_cfg_node_id0_u; + +/* Define the union csr_lcam_src_cfg_node_id1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 node_id_tile6 : 5; /* [4:0] */ + u32 node_id_tile7 : 5; /* [9:5] */ + u32 node_id_mpu : 5; /* [14:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_cfg_node_id1_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg4 : 6; /* [5:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_lcam_tcam_ctrl_bus_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_tcam_ctrl_bus_cfg : 10; /* [9:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_tcam_ctrl_bus_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_lcam_version_u lcam_version; /* 0 */ + volatile csr_lcam_indrect_ctrl_u lcam_indrect_ctrl; /* 4 */ + volatile csr_lcam_indrect_timeout_u lcam_indrect_timeout; /* 8 */ + volatile csr_lcam_indrect_data_0_u lcam_indrect_data_0; /* C */ + volatile csr_lcam_indrect_data_1_u lcam_indrect_data_1; /* 10 */ + volatile csr_lcam_indrect_data_2_u lcam_indrect_data_2; /* 14 */ + volatile csr_lcam_scan_period_u lcam_scan_period; /* 18 */ + volatile csr_lcam_scan_period_gra_u lcam_scan_period_gra; /* 1C */ + volatile csr_lcam_scan_en_u lcam_scan_en; /* 20 */ + volatile csr_lcam_common_cfg_u lcam_common_cfg; /* 24 */ + volatile csr_lcam_uncrt_err_u lcam_uncrt_err; /* 28 */ + volatile csr_lcam_wrr_weight_u lcam_wrr_weight; /* 2C */ + volatile csr_lcam_ring_rx_rqst_correct_cnt_u lcam_ring_rx_rqst_correct_cnt; /* 30 */ + volatile csr_lcam_ring_rx_rqst_err_cnt_u lcam_ring_rx_rqst_err_cnt; /* 34 */ + volatile csr_lcam_ring_rx_rqst_drop_cnt_u lcam_ring_rx_rqst_drop_cnt; /* 38 */ + volatile csr_lcam_ring_tx_rqst_correct_cnt_u lcam_ring_tx_rqst_correct_cnt; /* 3C */ + volatile csr_lcam_ring_tx_rqst_err_cnt_u lcam_ring_tx_rqst_err_cnt; /* 40 */ + volatile csr_lcam_int_vector_u lcam_int_vector; /* 44 */ + volatile csr_lcam_int_u lcam_int; /* 48 */ + volatile csr_lcam_int_mask_u lcam_int_mask; /* 4C */ + volatile csr_lcam_ring_itf_err_u lcam_ring_itf_err; /* 50 */ + volatile csr_lcam_ring_itf_err_mask_u lcam_ring_itf_err_mask; /* 54 */ + volatile csr_lcam_ad_ecc_one_bit_err_u lcam_ad_ecc_one_bit_err; /* 58 */ + volatile csr_lcam_ad_ecc_two_bit_err_u lcam_ad_ecc_two_bit_err; /* 5C */ + volatile csr_lcam_tcam_ecc_one_bit_err_u lcam_tcam_ecc_one_bit_err; /* 60 */ + volatile csr_lcam_tcam_ecc_two_bit_err_u lcam_tcam_ecc_two_bit_err; /* 64 */ + volatile csr_lcam_cmd_err_u lcam_cmd_err; /* 68 */ + volatile csr_lcam_cmd_err_mask_u lcam_cmd_err_mask; /* 6C */ + volatile csr_lcam_init_status_u lcam_init_status; /* 70 */ + volatile csr_lcam_ecc_err_inj_u lcam_ecc_err_inj; /* 74 */ + volatile csr_lcam_src_err_u lcam_src_err; /* 80 */ + volatile csr_lcam_src_err_mask_u lcam_src_err_mask; /* 84 */ + volatile csr_lcam_src_cfg_u lcam_src_cfg; /* 88 */ + volatile csr_lcam_src_cfg_node_id0_u lcam_src_cfg_node_id0; /* 8C */ + volatile csr_lcam_src_cfg_node_id1_u lcam_src_cfg_node_id1; /* 90 */ + volatile csr_lcam_mem_ctrl_bus_cfg0_u lcam_mem_ctrl_bus_cfg0; /* 94 */ + volatile csr_lcam_mem_ctrl_bus_cfg1_u lcam_mem_ctrl_bus_cfg1; /* 98 */ + volatile csr_lcam_mem_ctrl_bus_cfg2_u lcam_mem_ctrl_bus_cfg2; /* 9C */ + volatile csr_lcam_mem_ctrl_bus_cfg3_u lcam_mem_ctrl_bus_cfg3; /* A0 */ + volatile csr_lcam_mem_ctrl_bus_cfg4_u lcam_mem_ctrl_bus_cfg4; /* A4 */ + volatile csr_lcam_tcam_ctrl_bus_cfg_u lcam_tcam_ctrl_bus_cfg; /* A8 */ +} S_lcam_csr_REGS_TYPE; + +/* Declare the struct pointor of the module lcam_csr */ +extern volatile S_lcam_csr_REGS_TYPE *goplcam_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetLCAM_VERSION_lcam_version(unsigned int ulcam_version); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_addr(unsigned int ulcam_indrect_addr); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_tab(unsigned int ulcam_indrect_tab); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_status(unsigned int ulcam_indrect_status); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_mode(unsigned int ulcam_indrect_mode); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_vld(unsigned int ulcam_indrect_vld); +int iSetLCAM_INDRECT_TIMEOUT_lcam_indrect_timeout(unsigned int ulcam_indrect_timeout); +int iSetLCAM_INDRECT_DATA_0_lcam_indrect_data_0(unsigned int ulcam_indrect_data_0); +int iSetLCAM_INDRECT_DATA_1_lcam_indrect_data_1(unsigned int ulcam_indrect_data_1); +int iSetLCAM_INDRECT_DATA_2_lcam_indrect_data_2(unsigned int ulcam_indrect_data_2); +int iSetLCAM_SCAN_PERIOD_rp_lcam_scan_period(unsigned int urp_lcam_scan_period); +int iSetLCAM_SCAN_PERIOD_GRA_rp_lcam_scan_period_gra(unsigned int urp_lcam_scan_period_gra); +int iSetLCAM_SCAN_EN_rp_lcam_scan_en(unsigned int urp_lcam_scan_en); +int iSetLCAM_COMMON_CFG_rp_block_gating(unsigned int urp_block_gating); +int iSetLCAM_COMMON_CFG_rp_lcam_tcam_init_en(unsigned int urp_lcam_tcam_init_en); +int iSetLCAM_COMMON_CFG_rp_lcam_ag_init_en(unsigned int urp_lcam_ag_init_en); +int iSetLCAM_COMMON_CFG_rp_check_en(unsigned int urp_check_en); +int iSetLCAM_COMMON_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetLCAM_COMMON_CFG_sp_ret1n(unsigned int usp_ret1n); +int iSetLCAM_COMMON_CFG_rp_lcam_cnt_src_sel(unsigned int urp_lcam_cnt_src_sel); +int iSetLCAM_COMMON_CFG_rp_lcam_cnt_en(unsigned int urp_lcam_cnt_en); +int iSetLCAM_COMMON_CFG_rp_lcam_resp_e0_en(unsigned int urp_lcam_resp_e0_en); +int iSetLCAM_COMMON_CFG_rp_tcam_search_low_power_en(unsigned int urp_tcam_search_low_power_en); +int iSetLCAM_COMMON_CFG_rp_rx_async_fifo_wr_bp_thrd(unsigned int urp_rx_async_fifo_wr_bp_thrd); +int iSetLCAM_COMMON_CFG_rp_tx_async_fifo_wr_bp_thrd(unsigned int urp_tx_async_fifo_wr_bp_thrd); +int iSetLCAM_UNCRT_ERR_rp_lcam_uncrt_err_clr(unsigned int urp_lcam_uncrt_err_clr); +int iSetLCAM_UNCRT_ERR_rp_lcam_api_drop_err_mask(unsigned int urp_lcam_api_drop_err_mask); +int iSetLCAM_WRR_WEIGHT_rp_lcam_tcam_wrr_weight(unsigned int urp_lcam_tcam_wrr_weight); +int iSetLCAM_RING_RX_RQST_CORRECT_CNT_lcam_ring_rx_rqst_correct_cnt(unsigned int ulcam_ring_rx_rqst_correct_cnt); +int iSetLCAM_RING_RX_RQST_ERR_CNT_lcam_ring_rx_rqst_err_cnt(unsigned int ulcam_ring_rx_rqst_err_cnt); +int iSetLCAM_RING_RX_RQST_DROP_CNT_lcam_ring_rx_rqst_drop_cnt(unsigned int ulcam_ring_rx_rqst_drop_cnt); +int iSetLCAM_RING_TX_RQST_CORRECT_CNT_lcam_ring_tx_rqst_correct_cnt(unsigned int ulcam_ring_tx_rqst_correct_cnt); +int iSetLCAM_RING_TX_RQST_ERR_CNT_lcam_ring_tx_rqst_err_cnt(unsigned int ulcam_ring_tx_rqst_err_cnt); +int iSetLCAM_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetLCAM_INT_VECTOR_enable(unsigned int uenable); +int iSetLCAM_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetLCAM_INT_int_data(unsigned int uint_data); +int iSetLCAM_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetLCAM_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetLCAM_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetLCAM_RING_ITF_ERR_api_drop_err(unsigned int uapi_drop_err); +int iSetLCAM_RING_ITF_ERR_api_drop_merr(unsigned int uapi_drop_merr); +int iSetLCAM_RING_ITF_ERR_miss_sop_err(unsigned int umiss_sop_err); +int iSetLCAM_RING_ITF_ERR_miss_sop_merr(unsigned int umiss_sop_merr); +int iSetLCAM_RING_ITF_ERR_miss_eop_err(unsigned int umiss_eop_err); +int iSetLCAM_RING_ITF_ERR_miss_eop_merr(unsigned int umiss_eop_merr); +int iSetLCAM_RING_ITF_ERR_illegal_op_id_err(unsigned int uillegal_op_id_err); +int iSetLCAM_RING_ITF_ERR_illegal_op_id_merr(unsigned int uillegal_op_id_merr); +int iSetLCAM_RING_ITF_ERR_api_overlong_err(unsigned int uapi_overlong_err); +int iSetLCAM_RING_ITF_ERR_api_overlong_merr(unsigned int uapi_overlong_merr); +int iSetLCAM_RING_ITF_ERR_api_tooshort_err(unsigned int uapi_tooshort_err); +int iSetLCAM_RING_ITF_ERR_api_tooshort_merr(unsigned int uapi_tooshort_merr); +int iSetLCAM_RING_ITF_ERR_req_asyn_overflow_err(unsigned int ureq_asyn_overflow_err); +int iSetLCAM_RING_ITF_ERR_req_asyn_overflow_merr(unsigned int ureq_asyn_overflow_merr); +int iSetLCAM_RING_ITF_ERR_rsp_asyn_overflow_err(unsigned int ursp_asyn_overflow_err); +int iSetLCAM_RING_ITF_ERR_rsp_asyn_overflow_merr(unsigned int ursp_asyn_overflow_merr); +int iSetLCAM_RING_ITF_ERR_MASK_api_drop_err_mask(unsigned int uapi_drop_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_miss_sop_err_mask(unsigned int umiss_sop_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_miss_eop_err_mask(unsigned int umiss_eop_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_illegal_op_id_err_mask(unsigned int uillegal_op_id_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_api_overlong_err_mask(unsigned int uapi_overlong_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_api_tooshort_err_mask(unsigned int uapi_tooshort_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_req_asyn_overflow_err_mask(unsigned int ureq_asyn_overflow_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_rsp_asyn_overflow_err_mask(unsigned int ursp_asyn_overflow_err_mask); +int iSetLCAM_AD_ECC_ONE_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_AD_ECC_ONE_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_AD_ECC_ONE_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_AD_ECC_TWO_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_AD_ECC_TWO_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_AD_ECC_TWO_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_TCAM_ECC_ONE_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_TCAM_ECC_ONE_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_TCAM_ECC_ONE_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_TCAM_ECC_TWO_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_TCAM_ECC_TWO_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_TCAM_ECC_TWO_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_CMD_ERR_ag_addr_outof_range_err(unsigned int uag_addr_outof_range_err); +int iSetLCAM_CMD_ERR_ag_addr_outof_range_merr(unsigned int uag_addr_outof_range_merr); +int iSetLCAM_CMD_ERR_tcam_op_addr_cmd_err(unsigned int utcam_op_addr_cmd_err); +int iSetLCAM_CMD_ERR_tcam_op_addr_cmd_merr(unsigned int utcam_op_addr_cmd_merr); +int iSetLCAM_CMD_ERR_move_new_eq_old_err(unsigned int umove_new_eq_old_err); +int iSetLCAM_CMD_ERR_move_new_eq_old_merr(unsigned int umove_new_eq_old_merr); +int iSetLCAM_CMD_ERR_move_len_outof_err(unsigned int umove_len_outof_err); +int iSetLCAM_CMD_ERR_move_len_outof_merr(unsigned int umove_len_outof_merr); +int iSetLCAM_CMD_ERR_move_old_outof_err(unsigned int umove_old_outof_err); +int iSetLCAM_CMD_ERR_move_old_outof_merr(unsigned int umove_old_outof_merr); +int iSetLCAM_CMD_ERR_move_new_outof_err(unsigned int umove_new_outof_err); +int iSetLCAM_CMD_ERR_move_new_outof_merr(unsigned int umove_new_outof_merr); +int iSetLCAM_CMD_ERR_move_len_zero_err(unsigned int umove_len_zero_err); +int iSetLCAM_CMD_ERR_move_len_zero_merr(unsigned int umove_len_zero_merr); +int iSetLCAM_CMD_ERR_target_blk_gating_err(unsigned int utarget_blk_gating_err); +int iSetLCAM_CMD_ERR_target_blk_gating_merr(unsigned int utarget_blk_gating_merr); +int iSetLCAM_CMD_ERR_MASK_ag_addr_outof_range_err_mask(unsigned int uag_addr_outof_range_err_mask); +int iSetLCAM_CMD_ERR_MASK_tcam_op_addr_cmd_err_mask(unsigned int utcam_op_addr_cmd_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_new_eq_old_err_mask(unsigned int umove_new_eq_old_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_len_outof_err_mask(unsigned int umove_len_outof_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_old_outof_err_mask(unsigned int umove_old_outof_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_new_outof_err_mask(unsigned int umove_new_outof_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_len_zero_err_mask(unsigned int umove_len_zero_err_mask); +int iSetLCAM_CMD_ERR_MASK_target_blk_gating_err_mask(unsigned int utarget_blk_gating_err_mask); +int iSetLCAM_INIT_STATUS_lcam_tcam_init_done(unsigned int ulcam_tcam_init_done); +int iSetLCAM_INIT_STATUS_lcam_ag_init_done(unsigned int ulcam_ag_init_done); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_ad_one_bit_err_inj_req(unsigned int urp_lcam_ad_one_bit_err_inj_req); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_ad_two_bit_err_inj_req(unsigned int urp_lcam_ad_two_bit_err_inj_req); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_tcam_one_bit_err_inj_req(unsigned int urp_lcam_tcam_one_bit_err_inj_req); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_tcam_two_bit_err_inj_req(unsigned int urp_lcam_tcam_two_bit_err_inj_req); +int iSetLCAM_SRC_ERR_src_chk_err(unsigned int usrc_chk_err); +int iSetLCAM_SRC_ERR_src_chk_merr(unsigned int usrc_chk_merr); +int iSetLCAM_SRC_ERR_sticky(unsigned int usticky); +int iSetLCAM_SRC_ERR_MASK_src_err_mask(unsigned int usrc_err_mask); +int iSetLCAM_SRC_CFG_src_cfg(unsigned int usrc_cfg); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile0(unsigned int unode_id_tile0); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile1(unsigned int unode_id_tile1); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile2(unsigned int unode_id_tile2); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile3(unsigned int unode_id_tile3); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile4(unsigned int unode_id_tile4); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile5(unsigned int unode_id_tile5); +int iSetLCAM_SRC_CFG_NODE_ID1_node_id_tile6(unsigned int unode_id_tile6); +int iSetLCAM_SRC_CFG_NODE_ID1_node_id_tile7(unsigned int unode_id_tile7); +int iSetLCAM_SRC_CFG_NODE_ID1_node_id_mpu(unsigned int unode_id_mpu); +int iSetLCAM_MEM_CTRL_BUS_CFG0_lcam_mem_ctrl_bus_cfg0(unsigned int ulcam_mem_ctrl_bus_cfg0); +int iSetLCAM_MEM_CTRL_BUS_CFG1_lcam_mem_ctrl_bus_cfg1(unsigned int ulcam_mem_ctrl_bus_cfg1); +int iSetLCAM_MEM_CTRL_BUS_CFG2_lcam_mem_ctrl_bus_cfg2(unsigned int ulcam_mem_ctrl_bus_cfg2); +int iSetLCAM_MEM_CTRL_BUS_CFG3_lcam_mem_ctrl_bus_cfg3(unsigned int ulcam_mem_ctrl_bus_cfg3); +int iSetLCAM_MEM_CTRL_BUS_CFG4_lcam_mem_ctrl_bus_cfg4(unsigned int ulcam_mem_ctrl_bus_cfg4); +int iSetLCAM_TCAM_CTRL_BUS_CFG_lcam_tcam_ctrl_bus_cfg(unsigned int ulcam_tcam_ctrl_bus_cfg); + + +#endif // LCAM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_reg_offset.h new file mode 100644 index 000000000..d886511cd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_reg_offset.h @@ -0,0 +1,72 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : lcam_reg_offset.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/14 16:55:24 Create file +// ****************************************************************************** + +#ifndef LCAM_REG_OFFSET_H +#define LCAM_REG_OFFSET_H + +/* lcam_csr Base address of Module's Register */ +#define CSR_LCAM_CSR_BASE (0x0) + +/* **************************************************************************** */ +/* lcam_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_LCAM_CSR_LCAM_VERSION_REG (CSR_LCAM_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_LCAM_CSR_LCAM_INDRECT_CTRL_REG (CSR_LCAM_CSR_BASE + 0x4) /* LCAM间接寻址控制寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_TIMEOUT_REG (CSR_LCAM_CSR_BASE + 0x8) /* LCAM间接寻址TIMEOUT配置寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_0_REG (CSR_LCAM_CSR_BASE + 0xC) /* LCAM间接寻址数据寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_1_REG (CSR_LCAM_CSR_BASE + 0x10) /* LCAM间接寻址数据寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_2_REG (CSR_LCAM_CSR_BASE + 0x14) /* LCAM间接寻址数据寄存器 */ +#define CSR_LCAM_CSR_LCAM_SCAN_PERIOD_REG (CSR_LCAM_CSR_BASE + 0x18) /* LCAM背景周期 */ +#define CSR_LCAM_CSR_LCAM_SCAN_PERIOD_GRA_REG (CSR_LCAM_CSR_BASE + 0x1C) /* LCAM背景周期计数粒度 */ +#define CSR_LCAM_CSR_LCAM_SCAN_EN_REG (CSR_LCAM_CSR_BASE + 0x20) /* LCAM背景周期使能 */ +#define CSR_LCAM_CSR_LCAM_COMMON_CFG_REG (CSR_LCAM_CSR_BASE + 0x24) /* LCAM 其它的配置 */ +#define CSR_LCAM_CSR_LCAM_UNCRT_ERR_REG \ + (CSR_LCAM_CSR_BASE + 0x28) /* LCAM 致命中断标记配置入口发生丢弃API错误时，中断信号都会输出到顶层 */ +#define CSR_LCAM_CSR_LCAM_WRR_WEIGHT_REG (CSR_LCAM_CSR_BASE + 0x2C) /* LCAM TCAM 仲裁器权重 */ +#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_CORRECT_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x30) /* The number of correct api /flit received in RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_ERR_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x34) /* The number of error api /flit received in RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_DROP_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x38) /* The number of dropped api/flit received in RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_TX_RQST_CORRECT_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x3C) /* The number of correct api/flit send to RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_TX_RQST_ERR_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x40) /* The number of error api/flit send to RING interfaces */ +#define CSR_LCAM_CSR_LCAM_INT_VECTOR_REG (CSR_LCAM_CSR_BASE + 0x44) +#define CSR_LCAM_CSR_LCAM_INT_REG (CSR_LCAM_CSR_BASE + 0x48) /* SMIR interrupt data */ +#define CSR_LCAM_CSR_LCAM_INT_MASK_REG (CSR_LCAM_CSR_BASE + 0x4C) /* SMIR interrupt mask configuration */ +#define CSR_LCAM_CSR_LCAM_RING_ITF_ERR_REG (CSR_LCAM_CSR_BASE + 0x50) /* RING request channel 入口和出口发生的错误 */ +#define CSR_LCAM_CSR_LCAM_RING_ITF_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x54) +#define CSR_LCAM_CSR_LCAM_AD_ECC_ONE_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x58) /* LCAM AD memory发生ECC校验1比特错误 */ +#define CSR_LCAM_CSR_LCAM_AD_ECC_TWO_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x5C) /* LCAM AD memory发生ECC校验2比特错误 */ +#define CSR_LCAM_CSR_LCAM_TCAM_ECC_ONE_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x60) /* LCAM TCAM IP发生ECC校验1比特错误 */ +#define CSR_LCAM_CSR_LCAM_TCAM_ECC_TWO_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x64) /* LCAM TCAM IP发生ECC校验2比特错误 */ +#define CSR_LCAM_CSR_LCAM_CMD_ERR_REG (CSR_LCAM_CSR_BASE + 0x68) /* 软件配置错误 */ +#define CSR_LCAM_CSR_LCAM_CMD_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x6C) +#define CSR_LCAM_CSR_LCAM_INIT_STATUS_REG (CSR_LCAM_CSR_BASE + 0x70) +#define CSR_LCAM_CSR_LCAM_ECC_ERR_INJ_REG (CSR_LCAM_CSR_BASE + 0x74) /* LCAM ECC memory error injection */ +#define CSR_LCAM_CSR_LCAM_SRC_ERR_REG (CSR_LCAM_CSR_BASE + 0x80) +#define CSR_LCAM_CSR_LCAM_SRC_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x84) +#define CSR_LCAM_CSR_LCAM_SRC_CFG_REG (CSR_LCAM_CSR_BASE + 0x88) +#define CSR_LCAM_CSR_LCAM_SRC_CFG_NODE_ID0_REG (CSR_LCAM_CSR_BASE + 0x8C) +#define CSR_LCAM_CSR_LCAM_SRC_CFG_NODE_ID1_REG (CSR_LCAM_CSR_BASE + 0x90) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG0_REG (CSR_LCAM_CSR_BASE + 0x94) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG1_REG (CSR_LCAM_CSR_BASE + 0x98) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG2_REG (CSR_LCAM_CSR_BASE + 0x9C) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG3_REG (CSR_LCAM_CSR_BASE + 0xA0) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG4_REG (CSR_LCAM_CSR_BASE + 0xA4) +#define CSR_LCAM_CSR_LCAM_TCAM_CTRL_BUS_CFG_REG (CSR_LCAM_CSR_BASE + 0xA8) + +#endif // LCAM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_c_union_define.h new file mode 100644 index 000000000..7d81af8b6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_c_union_define.h @@ -0,0 +1,11885 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : mqm_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:55:24 Create file +// ****************************************************************************** + +#ifndef MQM_C_UNION_DEFINE_H +#define MQM_C_UNION_DEFINE_H + +/* Define the union csr_mqm_edition_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_edition_u; + +/* Define the union csr_mqm_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_initctab_start : 1; /* [0] */ + u32 brm_initctab_start : 1; /* [1] */ + u32 iqm_initctab_start : 1; /* [2] */ + u32 msc_initctab_start : 1; /* [3] */ + u32 eqm_initctab_start : 1; /* [4] */ + u32 deqc_initctab_start : 1; /* [5] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_initctab_start_u; + +/* Define the union csr_mqm_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_initctab_done : 1; /* [0] */ + u32 rsv_1 : 15; /* [15:1] */ + u32 enqc_mqm_init_done : 1; /* [16] */ + u32 brm_mqm_init_done : 1; /* [17] */ + u32 iqm_mqm_init_done : 1; /* [18] */ + u32 msc_mqm_init_done : 1; /* [19] */ + u32 eqm_mqm_init_done : 1; /* [20] */ + u32 deqc_mqm_init_done : 1; /* [21] */ + u32 rsv_2 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_initctab_done_u; + +/* Define the union csr_mqm_cfg_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cfg_ok : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_cfg_ok_u; + +/* Define the union csr_mqm_initlogic_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_initlogic_done : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_initlogic_done_u; + +/* Define the union csr_mqm_top_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_cpi_int_index : 24; /* [23:0] */ + u32 rsv_5 : 3; /* [26:24] */ + u32 mqm_top_enable : 1; /* [27] */ + u32 mqm_top_int_issue : 1; /* [28] */ + u32 rsv_6 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_int_vector_u; + +/* Define the union csr_mqm_top_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_int_data : 4; /* [3:0] */ + u32 rsv_7 : 12; /* [15:4] */ + u32 mqm_top_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_int_u; + +/* Define the union csr_mqm_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_int_en : 4; /* [3:0] */ + u32 rsv_8 : 12; /* [15:4] */ + u32 mqm_top_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_int_en_u; + +/* Define the union csr_vf_flush_done_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_done_err : 1; /* [0] */ + u32 vf_flush_done_err_insrt : 1; /* [1] */ + u32 vf_flush_done_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_done_int_u; + +/* Define the union csr_mqm_rx_cnp_e0_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cnp_api_e0_err : 1; /* [0] */ + u32 mqm_cnp_api_e0_err_insert : 1; /* [1] */ + u32 mqm_cnp_api_e0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rx_cnp_e0_err_int_u; + +/* Define the union csr_mqm_rx_cnp_e1_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cnp_api_e1_err : 1; /* [0] */ + u32 mqm_cnp_api_e1_err_insert : 1; /* [1] */ + u32 mqm_cnp_api_e1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rx_cnp_e1_err_int_u; + +/* Define the union csr_mqm_top_fifo_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_fifo_int_err0 : 1; /* [0] */ + u32 mqm_top_fifo_int_err0_insrt : 1; /* [1] */ + u32 mqm_top_fifo_int_err1 : 1; /* [2] */ + u32 mqm_top_fifo_int_err1_insrt : 1; /* [3] */ + u32 mqm_top_fifo_int_err2 : 1; /* [4] */ + u32 mqm_top_fifo_int_err2_insrt : 1; /* [5] */ + u32 mqm_top_fifo_int_err3 : 1; /* [6] */ + u32 mqm_top_fifo_int_err3_insrt : 1; /* [7] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_fifo_int_u; + +/* Define the union csr_mqm_top_fifo_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_fifo_int_err0_en : 1; /* [0] */ + u32 mqm_top_fifo_int_err1_en : 1; /* [1] */ + u32 mqm_top_fifo_int_err2_en : 1; /* [2] */ + u32 mqm_top_fifo_int_err3_en : 1; /* [3] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_fifo_int_mask_u; + +/* Define the union csr_use_host_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 use_host_bmp : 4; /* [3:0] */ + u32 rsv_11 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_use_host_bitmap_u; + +/* Define the union csr_db_type_maping_tab0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type0_map_id : 3; /* [2:0] */ + u32 type0_map_en : 1; /* [3] */ + u32 type1_map_id : 3; /* [6:4] */ + u32 type1_map_en : 1; /* [7] */ + u32 type2_map_id : 3; /* [10:8] */ + u32 type2_map_en : 1; /* [11] */ + u32 rsv_12 : 4; /* [15:12] */ + u32 type4_map_id : 3; /* [18:16] */ + u32 type4_map_en : 1; /* [19] */ + u32 rsv_13 : 4; /* [23:20] */ + u32 type6_map_id : 3; /* [26:24] */ + u32 type6_map_en : 1; /* [27] */ + u32 type7_map_id : 3; /* [30:28] */ + u32 type7_map_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab0_u; + +/* Define the union csr_db_type_maping_tab1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type8_map_id : 3; /* [2:0] */ + u32 type8_map_en : 1; /* [3] */ + u32 type9_map_id : 3; /* [6:4] */ + u32 type9_map_en : 1; /* [7] */ + u32 type10_map_id : 3; /* [10:8] */ + u32 type10_map_en : 1; /* [11] */ + u32 type11_map_id : 3; /* [14:12] */ + u32 type11_map_en : 1; /* [15] */ + u32 type12_map_id : 3; /* [18:16] */ + u32 type12_map_en : 1; /* [19] */ + u32 type13_map_id : 3; /* [22:20] */ + u32 type13_map_en : 1; /* [23] */ + u32 type14_map_id : 3; /* [26:24] */ + u32 type14_map_en : 1; /* [27] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab1_u; + +/* Define the union csr_db_type_maping_tab2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_15 : 4; /* [3:0] */ + u32 type17_map_id : 3; /* [6:4] */ + u32 type17_map_en : 1; /* [7] */ + u32 rsv_16 : 8; /* [15:8] */ + u32 type20_map_id : 3; /* [18:16] */ + u32 type20_map_en : 1; /* [19] */ + u32 type21_map_id : 3; /* [22:20] */ + u32 type21_map_en : 1; /* [23] */ + u32 type22_map_id : 3; /* [26:24] */ + u32 type22_map_en : 1; /* [27] */ + u32 type23_map_id : 3; /* [30:28] */ + u32 type23_map_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab2_u; + +/* Define the union csr_db_type_maping_tab3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type24_map_id : 3; /* [2:0] */ + u32 type24_map_en : 1; /* [3] */ + u32 rsv_17 : 24; /* [27:4] */ + u32 type31_map_id : 3; /* [30:28] */ + u32 type31_map_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab3_u; + +/* Define the union csr_mqm_cmq_enq_mode_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cmq_enq_mode_cfg : 2; /* [1:0] */ + u32 rsv_18 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_cmq_enq_mode_cfg_u; + +/* Define the union csr_mqm_max_dma_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_max_dma_credit_sge_cfg : 8; /* [7:0] */ + u32 mqm_max_dma_credit_data_cfg : 8; /* [15:8] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_max_dma_crdt_cfg_u; + +/* Define the union csr_mqm_soc_use_pf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_soc_use_pf_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_soc_use_pf_cfg_u; + +/* Define the union csr_mqm_pf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_pf_offset_cfg : 4; /* [3:0] */ + u32 mqm_pf_use_mode_cfg : 3; /* [6:4] */ + u32 rsv_20 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_pf_cfg_u; + +/* Define the union csr_mqm_vf_flush_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_id : 13; /* [12:0] */ + u32 rsv_21 : 3; /* [15:13] */ + u32 vf_flush_host_id : 3; /* [18:16] */ + u32 rsv_22 : 1; /* [19] */ + u32 vf_flush_ep_id : 3; /* [22:20] */ + u32 rsv_23 : 1; /* [23] */ + u32 vf_flush_vld : 1; /* [24] */ + u32 rsv_24 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_cfg_u; + +/* Define the union csr_mqm_vf_flush_nmq_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_nmqid : 13; /* [12:0] */ + u32 rsv_25 : 3; /* [15:13] */ + u32 vf_flush_nmq_cos_id : 3; /* [18:16] */ + u32 rsv_26 : 5; /* [23:19] */ + u32 vf_flush_nmq_vld : 1; /* [24] */ + u32 rsv_27 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_nmq_id_cfg_u; + +/* Define the union csr_mqm_vf_flush_nfmq_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_nfmqid : 12; /* [11:0] */ + u32 rsv_28 : 4; /* [15:12] */ + u32 vf_flush_nfmq_cos_id : 3; /* [18:16] */ + u32 rsv_29 : 5; /* [23:19] */ + u32 vf_flush_nfmq_vld : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_nfmq_id_cfg_u; + +/* Define the union csr_vf_flush_r_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_r_txq_num : 21; /* [20:0] */ + u32 rsv_31 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_r_txq_num_u; + +/* Define the union csr_vf_flush_r_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_r_txq_baddr : 20; /* [19:0] */ + u32 rsv_32 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_r_txq_baddr_u; + +/* Define the union csr_vf_flush_s_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_s_txq_num : 21; /* [20:0] */ + u32 rsv_33 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_s_txq_num_u; + +/* Define the union csr_vf_flush_s_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_s_txq_baddr : 20; /* [19:0] */ + u32 rsv_34 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_s_txq_baddr_u; + +/* Define the union csr_vf_flush_f_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_f_txq_num : 21; /* [20:0] */ + u32 rsv_35 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_f_txq_num_u; + +/* Define the union csr_vf_flush_f_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_f_txq_baddr : 20; /* [19:0] */ + u32 rsv_36 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_f_txq_baddr_u; + +/* Define the union csr_vf_flush_u_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_u_txq_num : 21; /* [20:0] */ + u32 rsv_37 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_u_txq_num_u; + +/* Define the union csr_vf_flush_u_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_u_txq_baddr : 20; /* [19:0] */ + u32 rsv_38 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_u_txq_baddr_u; + +/* Define the union csr_vf_flush_lnic_sq_txq_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_ls_txq_num : 14; /* [13:0] */ + u32 rsv_39 : 2; /* [15:14] */ + u32 vf_flush_ls_txq_baddr : 13; /* [28:16] */ + u32 rsv_40 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_lnic_sq_txq_info_u; + +/* Define the union csr_vf_flush_lnic_rq_txq_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_lr_txq_num : 14; /* [13:0] */ + u32 rsv_41 : 2; /* [15:14] */ + u32 vf_flush_lr_txq_baddr : 13; /* [28:16] */ + u32 rsv_42 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_lnic_rq_txq_info_u; + +/* Define the union csr_mqm_vf_flush_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_vf_flush_done : 1; /* [0] */ + u32 rsv_43 : 3; /* [3:1] */ + u32 deqc_vf_flush_done : 1; /* [4] */ + u32 eqm_vf_flush_done : 1; /* [5] */ + u32 msc_vf_flush_done : 1; /* [6] */ + u32 iqm_vf_flush_done : 1; /* [7] */ + u32 enqc_vf_flush_done : 1; /* [8] */ + u32 rsv_44 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_done_u; + +/* Define the union csr_mqm_uncrt_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_mask : 1; /* [0] */ + u32 other_uncrt_err_mask : 1; /* [1] */ + u32 rsv_45 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_uncrt_err_mask_u; + +/* Define the union csr_mqm_uncrt_err_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_clr : 1; /* [0] */ + u32 other_uncrt_err_clr : 1; /* [1] */ + u32 rsv_46 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_uncrt_err_clr_u; + +/* Define the union csr_mqm_vf_count_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_count_designate_vfid : 13; /* [12:0] */ + u32 rsv_47 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_count_cfg_u; + +/* Define the union csr_mqm_rx_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rx_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rx_designate_vfid_cnt_u; + +/* Define the union csr_mqm_filt_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_filt_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_filt_designate_vfid_cnt_u; + +/* Define the union csr_mqm_tx_sm_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_tx_sm_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_tx_sm_designate_vfid_cnt_u; + +/* Define the union csr_mqm_tx_qu_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_tx_qu_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_tx_qu_designate_vfid_cnt_u; + +/* Define the union csr_mqm_rcv_tile_api_op_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rcv_tile_opid_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rcv_tile_api_op_err_cnt_u; + +/* Define the union csr_mqm_rcv_tile_fast_cnp_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rcv_tile_fast_cnp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rcv_tile_fast_cnp_api_cnt_u; + +/* Define the union csr_mqm_rcv_tile_cnp_api_e0e1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rcv_tile_fast_cnp_e0e1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rcv_tile_cnp_api_e0e1_cnt_u; + +/* Define the union csr_mqm_nd_rs_rqst_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_nd_rs_rqst_credit : 3; /* [2:0] */ + u32 rsv_48 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_nd_rs_rqst_credit_u; + +/* Define the union csr_mqm_top_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_fifo0_st : 2; /* [1:0] */ + u32 mqm_top_fifo1_st : 2; /* [3:2] */ + u32 rsv_49 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_fifo_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mqm_edition_u mqm_edition; /* 0 */ + volatile csr_mqm_initctab_start_u mqm_initctab_start; /* 4 */ + volatile csr_mqm_initctab_done_u mqm_initctab_done; /* 8 */ + volatile csr_mqm_cfg_ok_u mqm_cfg_ok; /* C */ + volatile csr_mqm_initlogic_done_u mqm_initlogic_done; /* 10 */ + volatile csr_mqm_top_int_vector_u mqm_top_int_vector; /* 30 */ + volatile csr_mqm_top_int_u mqm_top_int; /* 34 */ + volatile csr_mqm_top_int_en_u mqm_top_int_en; /* 38 */ + volatile csr_vf_flush_done_int_u vf_flush_done_int; /* 3C */ + volatile csr_mqm_rx_cnp_e0_err_int_u mqm_rx_cnp_e0_err_int; /* 40 */ + volatile csr_mqm_rx_cnp_e1_err_int_u mqm_rx_cnp_e1_err_int; /* 44 */ + volatile csr_mqm_top_fifo_int_u mqm_top_fifo_int; /* 48 */ + volatile csr_mqm_top_fifo_int_mask_u mqm_top_fifo_int_mask; /* 4C */ + volatile csr_use_host_bitmap_u use_host_bitmap; /* 80 */ + volatile csr_db_type_maping_tab0_u db_type_maping_tab0; /* 84 */ + volatile csr_db_type_maping_tab1_u db_type_maping_tab1; /* 88 */ + volatile csr_db_type_maping_tab2_u db_type_maping_tab2; /* 8C */ + volatile csr_db_type_maping_tab3_u db_type_maping_tab3; /* 90 */ + volatile csr_mqm_cmq_enq_mode_cfg_u mqm_cmq_enq_mode_cfg; /* 94 */ + volatile csr_mqm_max_dma_crdt_cfg_u mqm_max_dma_crdt_cfg; /* 98 */ + volatile csr_mqm_soc_use_pf_cfg_u mqm_soc_use_pf_cfg[4]; /* 9C */ + volatile csr_mqm_pf_cfg_u mqm_pf_cfg; /* AC */ + volatile csr_mqm_vf_flush_cfg_u mqm_vf_flush_cfg; /* 100 */ + volatile csr_mqm_vf_flush_nmq_id_cfg_u mqm_vf_flush_nmq_id_cfg[8]; /* 104 */ + volatile csr_mqm_vf_flush_nfmq_id_cfg_u mqm_vf_flush_nfmq_id_cfg[8]; /* 124 */ + volatile csr_vf_flush_r_txq_num_u vf_flush_r_txq_num; /* 144 */ + volatile csr_vf_flush_r_txq_baddr_u vf_flush_r_txq_baddr; /* 148 */ + volatile csr_vf_flush_s_txq_num_u vf_flush_s_txq_num; /* 14C */ + volatile csr_vf_flush_s_txq_baddr_u vf_flush_s_txq_baddr; /* 150 */ + volatile csr_vf_flush_f_txq_num_u vf_flush_f_txq_num; /* 154 */ + volatile csr_vf_flush_f_txq_baddr_u vf_flush_f_txq_baddr; /* 158 */ + volatile csr_vf_flush_u_txq_num_u vf_flush_u_txq_num; /* 15C */ + volatile csr_vf_flush_u_txq_baddr_u vf_flush_u_txq_baddr; /* 160 */ + volatile csr_vf_flush_lnic_sq_txq_info_u vf_flush_lnic_sq_txq_info; /* 164 */ + volatile csr_vf_flush_lnic_rq_txq_info_u vf_flush_lnic_rq_txq_info; /* 168 */ + volatile csr_mqm_vf_flush_done_u mqm_vf_flush_done; /* 174 */ + volatile csr_mqm_uncrt_err_mask_u mqm_uncrt_err_mask; /* 200 */ + volatile csr_mqm_uncrt_err_clr_u mqm_uncrt_err_clr; /* 204 */ + volatile csr_mqm_vf_count_cfg_u mqm_vf_count_cfg; /* 304 */ + volatile csr_mqm_rx_designate_vfid_cnt_u mqm_rx_designate_vfid_cnt; /* 308 */ + volatile csr_mqm_filt_designate_vfid_cnt_u mqm_filt_designate_vfid_cnt; /* 30C */ + volatile csr_mqm_tx_sm_designate_vfid_cnt_u mqm_tx_sm_designate_vfid_cnt; /* 310 */ + volatile csr_mqm_tx_qu_designate_vfid_cnt_u mqm_tx_qu_designate_vfid_cnt; /* 314 */ + volatile csr_mqm_rcv_tile_api_op_err_cnt_u mqm_rcv_tile_api_op_err_cnt; /* 318 */ + volatile csr_mqm_rcv_tile_fast_cnp_api_cnt_u mqm_rcv_tile_fast_cnp_api_cnt; /* 31C */ + volatile csr_mqm_rcv_tile_cnp_api_e0e1_cnt_u mqm_rcv_tile_cnp_api_e0e1_cnt; /* 320 */ + volatile csr_mqm_nd_rs_rqst_credit_u mqm_nd_rs_rqst_credit; /* 324 */ + volatile csr_mqm_top_fifo_st_u mqm_top_fifo_st; /* 328 */ +} S_mqm_top_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_top */ +extern volatile S_mqm_top_REGS_TYPE *gopmqm_topAllReg; + +/* Declare the functions that set the member value */ +int iSetMQM_EDITION_mqm_version(unsigned int umqm_version); +int iSetMQM_INITCTAB_START_enqc_initctab_start(unsigned int uenqc_initctab_start); +int iSetMQM_INITCTAB_START_brm_initctab_start(unsigned int ubrm_initctab_start); +int iSetMQM_INITCTAB_START_iqm_initctab_start(unsigned int uiqm_initctab_start); +int iSetMQM_INITCTAB_START_msc_initctab_start(unsigned int umsc_initctab_start); +int iSetMQM_INITCTAB_START_eqm_initctab_start(unsigned int ueqm_initctab_start); +int iSetMQM_INITCTAB_START_deqc_initctab_start(unsigned int udeqc_initctab_start); +int iSetMQM_INITCTAB_DONE_mqm_initctab_done(unsigned int umqm_initctab_done); +int iSetMQM_INITCTAB_DONE_enqc_mqm_init_done(unsigned int uenqc_mqm_init_done); +int iSetMQM_INITCTAB_DONE_brm_mqm_init_done(unsigned int ubrm_mqm_init_done); +int iSetMQM_INITCTAB_DONE_iqm_mqm_init_done(unsigned int uiqm_mqm_init_done); +int iSetMQM_INITCTAB_DONE_msc_mqm_init_done(unsigned int umsc_mqm_init_done); +int iSetMQM_INITCTAB_DONE_eqm_mqm_init_done(unsigned int ueqm_mqm_init_done); +int iSetMQM_INITCTAB_DONE_deqc_mqm_init_done(unsigned int udeqc_mqm_init_done); +int iSetMQM_CFG_OK_mqm_cfg_ok(unsigned int umqm_cfg_ok); +int iSetMQM_INITLOGIC_DONE_mqm_initlogic_done(unsigned int umqm_initlogic_done); +int iSetMQM_TOP_INT_VECTOR_mqm_top_cpi_int_index(unsigned int umqm_top_cpi_int_index); +int iSetMQM_TOP_INT_VECTOR_mqm_top_enable(unsigned int umqm_top_enable); +int iSetMQM_TOP_INT_VECTOR_mqm_top_int_issue(unsigned int umqm_top_int_issue); +int iSetMQM_TOP_INT_mqm_top_int_data(unsigned int umqm_top_int_data); +int iSetMQM_TOP_INT_mqm_top_program_csr_id_ro(unsigned int umqm_top_program_csr_id_ro); +int iSetMQM_TOP_INT_EN_mqm_top_int_en(unsigned int umqm_top_int_en); +int iSetMQM_TOP_INT_EN_mqm_top_program_csr_id(unsigned int umqm_top_program_csr_id); +int iSetVF_FLUSH_DONE_INT_vf_flush_done_err(unsigned int uvf_flush_done_err); +int iSetVF_FLUSH_DONE_INT_vf_flush_done_err_insrt(unsigned int uvf_flush_done_err_insrt); +int iSetVF_FLUSH_DONE_INT_vf_flush_done_err_info(unsigned int uvf_flush_done_err_info); +int iSetMQM_RX_CNP_E0_ERR_INT_mqm_cnp_api_e0_err(unsigned int umqm_cnp_api_e0_err); +int iSetMQM_RX_CNP_E0_ERR_INT_mqm_cnp_api_e0_err_insert(unsigned int umqm_cnp_api_e0_err_insert); +int iSetMQM_RX_CNP_E0_ERR_INT_mqm_cnp_api_e0_err_info(unsigned int umqm_cnp_api_e0_err_info); +int iSetMQM_RX_CNP_E1_ERR_INT_mqm_cnp_api_e1_err(unsigned int umqm_cnp_api_e1_err); +int iSetMQM_RX_CNP_E1_ERR_INT_mqm_cnp_api_e1_err_insert(unsigned int umqm_cnp_api_e1_err_insert); +int iSetMQM_RX_CNP_E1_ERR_INT_mqm_cnp_api_e1_err_info(unsigned int umqm_cnp_api_e1_err_info); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err0(unsigned int umqm_top_fifo_int_err0); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err0_insrt(unsigned int umqm_top_fifo_int_err0_insrt); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err1(unsigned int umqm_top_fifo_int_err1); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err1_insrt(unsigned int umqm_top_fifo_int_err1_insrt); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err2(unsigned int umqm_top_fifo_int_err2); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err2_insrt(unsigned int umqm_top_fifo_int_err2_insrt); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err3(unsigned int umqm_top_fifo_int_err3); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err3_insrt(unsigned int umqm_top_fifo_int_err3_insrt); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err0_en(unsigned int umqm_top_fifo_int_err0_en); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err1_en(unsigned int umqm_top_fifo_int_err1_en); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err2_en(unsigned int umqm_top_fifo_int_err2_en); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err3_en(unsigned int umqm_top_fifo_int_err3_en); +int iSetUSE_HOST_BITMAP_use_host_bmp(unsigned int uuse_host_bmp); +int iSetDB_TYPE_MAPING_TAB0_type0_map_id(unsigned int utype0_map_id); +int iSetDB_TYPE_MAPING_TAB0_type0_map_en(unsigned int utype0_map_en); +int iSetDB_TYPE_MAPING_TAB0_type1_map_id(unsigned int utype1_map_id); +int iSetDB_TYPE_MAPING_TAB0_type1_map_en(unsigned int utype1_map_en); +int iSetDB_TYPE_MAPING_TAB0_type2_map_id(unsigned int utype2_map_id); +int iSetDB_TYPE_MAPING_TAB0_type2_map_en(unsigned int utype2_map_en); +int iSetDB_TYPE_MAPING_TAB0_type4_map_id(unsigned int utype4_map_id); +int iSetDB_TYPE_MAPING_TAB0_type4_map_en(unsigned int utype4_map_en); +int iSetDB_TYPE_MAPING_TAB0_type6_map_id(unsigned int utype6_map_id); +int iSetDB_TYPE_MAPING_TAB0_type6_map_en(unsigned int utype6_map_en); +int iSetDB_TYPE_MAPING_TAB0_type7_map_id(unsigned int utype7_map_id); +int iSetDB_TYPE_MAPING_TAB0_type7_map_en(unsigned int utype7_map_en); +int iSetDB_TYPE_MAPING_TAB1_type8_map_id(unsigned int utype8_map_id); +int iSetDB_TYPE_MAPING_TAB1_type8_map_en(unsigned int utype8_map_en); +int iSetDB_TYPE_MAPING_TAB1_type9_map_id(unsigned int utype9_map_id); +int iSetDB_TYPE_MAPING_TAB1_type9_map_en(unsigned int utype9_map_en); +int iSetDB_TYPE_MAPING_TAB1_type10_map_id(unsigned int utype10_map_id); +int iSetDB_TYPE_MAPING_TAB1_type10_map_en(unsigned int utype10_map_en); +int iSetDB_TYPE_MAPING_TAB1_type11_map_id(unsigned int utype11_map_id); +int iSetDB_TYPE_MAPING_TAB1_type11_map_en(unsigned int utype11_map_en); +int iSetDB_TYPE_MAPING_TAB1_type12_map_id(unsigned int utype12_map_id); +int iSetDB_TYPE_MAPING_TAB1_type12_map_en(unsigned int utype12_map_en); +int iSetDB_TYPE_MAPING_TAB1_type13_map_id(unsigned int utype13_map_id); +int iSetDB_TYPE_MAPING_TAB1_type13_map_en(unsigned int utype13_map_en); +int iSetDB_TYPE_MAPING_TAB1_type14_map_id(unsigned int utype14_map_id); +int iSetDB_TYPE_MAPING_TAB1_type14_map_en(unsigned int utype14_map_en); +int iSetDB_TYPE_MAPING_TAB2_type17_map_id(unsigned int utype17_map_id); +int iSetDB_TYPE_MAPING_TAB2_type17_map_en(unsigned int utype17_map_en); +int iSetDB_TYPE_MAPING_TAB2_type20_map_id(unsigned int utype20_map_id); +int iSetDB_TYPE_MAPING_TAB2_type20_map_en(unsigned int utype20_map_en); +int iSetDB_TYPE_MAPING_TAB2_type21_map_id(unsigned int utype21_map_id); +int iSetDB_TYPE_MAPING_TAB2_type21_map_en(unsigned int utype21_map_en); +int iSetDB_TYPE_MAPING_TAB2_type22_map_id(unsigned int utype22_map_id); +int iSetDB_TYPE_MAPING_TAB2_type22_map_en(unsigned int utype22_map_en); +int iSetDB_TYPE_MAPING_TAB2_type23_map_id(unsigned int utype23_map_id); +int iSetDB_TYPE_MAPING_TAB2_type23_map_en(unsigned int utype23_map_en); +int iSetDB_TYPE_MAPING_TAB3_type24_map_id(unsigned int utype24_map_id); +int iSetDB_TYPE_MAPING_TAB3_type24_map_en(unsigned int utype24_map_en); +int iSetDB_TYPE_MAPING_TAB3_type31_map_id(unsigned int utype31_map_id); +int iSetDB_TYPE_MAPING_TAB3_type31_map_en(unsigned int utype31_map_en); +int iSetMQM_CMQ_ENQ_MODE_CFG_mqm_cmq_enq_mode_cfg(unsigned int umqm_cmq_enq_mode_cfg); +int iSetMQM_MAX_DMA_CRDT_CFG_mqm_max_dma_credit_sge_cfg(unsigned int umqm_max_dma_credit_sge_cfg); +int iSetMQM_MAX_DMA_CRDT_CFG_mqm_max_dma_credit_data_cfg(unsigned int umqm_max_dma_credit_data_cfg); +int iSetMQM_SOC_USE_PF_CFG_mqm_soc_use_pf_cfg(unsigned int umqm_soc_use_pf_cfg); +int iSetMQM_PF_CFG_mqm_pf_offset_cfg(unsigned int umqm_pf_offset_cfg); +int iSetMQM_PF_CFG_mqm_pf_use_mode_cfg(unsigned int umqm_pf_use_mode_cfg); +int iSetMQM_VF_FLUSH_CFG_vf_flush_id(unsigned int uvf_flush_id); +int iSetMQM_VF_FLUSH_CFG_vf_flush_host_id(unsigned int uvf_flush_host_id); +int iSetMQM_VF_FLUSH_CFG_vf_flush_ep_id(unsigned int uvf_flush_ep_id); +int iSetMQM_VF_FLUSH_CFG_vf_flush_vld(unsigned int uvf_flush_vld); +int iSetMQM_VF_FLUSH_NMQ_ID_CFG_vf_flush_nmqid(unsigned int uvf_flush_nmqid); +int iSetMQM_VF_FLUSH_NMQ_ID_CFG_vf_flush_nmq_cos_id(unsigned int uvf_flush_nmq_cos_id); +int iSetMQM_VF_FLUSH_NMQ_ID_CFG_vf_flush_nmq_vld(unsigned int uvf_flush_nmq_vld); +int iSetMQM_VF_FLUSH_NFMQ_ID_CFG_vf_flush_nfmqid(unsigned int uvf_flush_nfmqid); +int iSetMQM_VF_FLUSH_NFMQ_ID_CFG_vf_flush_nfmq_cos_id(unsigned int uvf_flush_nfmq_cos_id); +int iSetMQM_VF_FLUSH_NFMQ_ID_CFG_vf_flush_nfmq_vld(unsigned int uvf_flush_nfmq_vld); +int iSetVF_FLUSH_R_TXQ_NUM_vf_flush_r_txq_num(unsigned int uvf_flush_r_txq_num); +int iSetVF_FLUSH_R_TXQ_BADDR_vf_flush_r_txq_baddr(unsigned int uvf_flush_r_txq_baddr); +int iSetVF_FLUSH_S_TXQ_NUM_vf_flush_s_txq_num(unsigned int uvf_flush_s_txq_num); +int iSetVF_FLUSH_S_TXQ_BADDR_vf_flush_s_txq_baddr(unsigned int uvf_flush_s_txq_baddr); +int iSetVF_FLUSH_F_TXQ_NUM_vf_flush_f_txq_num(unsigned int uvf_flush_f_txq_num); +int iSetVF_FLUSH_F_TXQ_BADDR_vf_flush_f_txq_baddr(unsigned int uvf_flush_f_txq_baddr); +int iSetVF_FLUSH_U_TXQ_NUM_vf_flush_u_txq_num(unsigned int uvf_flush_u_txq_num); +int iSetVF_FLUSH_U_TXQ_BADDR_vf_flush_u_txq_baddr(unsigned int uvf_flush_u_txq_baddr); +int iSetVF_FLUSH_LNIC_SQ_TXQ_INFO_vf_flush_ls_txq_num(unsigned int uvf_flush_ls_txq_num); +int iSetVF_FLUSH_LNIC_SQ_TXQ_INFO_vf_flush_ls_txq_baddr(unsigned int uvf_flush_ls_txq_baddr); +int iSetVF_FLUSH_LNIC_RQ_TXQ_INFO_vf_flush_lr_txq_num(unsigned int uvf_flush_lr_txq_num); +int iSetVF_FLUSH_LNIC_RQ_TXQ_INFO_vf_flush_lr_txq_baddr(unsigned int uvf_flush_lr_txq_baddr); +int iSetMQM_VF_FLUSH_DONE_mqm_vf_flush_done(unsigned int umqm_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_deqc_vf_flush_done(unsigned int udeqc_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_eqm_vf_flush_done(unsigned int ueqm_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_msc_vf_flush_done(unsigned int umsc_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_iqm_vf_flush_done(unsigned int uiqm_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_enqc_vf_flush_done(unsigned int uenqc_vf_flush_done); +int iSetMQM_UNCRT_ERR_MASK_ram_uncrt_err_mask(unsigned int uram_uncrt_err_mask); +int iSetMQM_UNCRT_ERR_MASK_other_uncrt_err_mask(unsigned int uother_uncrt_err_mask); +int iSetMQM_UNCRT_ERR_CLR_ram_uncrt_err_clr(unsigned int uram_uncrt_err_clr); +int iSetMQM_UNCRT_ERR_CLR_other_uncrt_err_clr(unsigned int uother_uncrt_err_clr); +int iSetMQM_VF_COUNT_CFG_mqm_count_designate_vfid(unsigned int umqm_count_designate_vfid); +int iSetMQM_RX_DESIGNATE_VFID_CNT_mqm_rx_designate_vfid_cnt(unsigned int umqm_rx_designate_vfid_cnt); +int iSetMQM_FILT_DESIGNATE_VFID_CNT_mqm_filt_designate_vfid_cnt(unsigned int umqm_filt_designate_vfid_cnt); +int iSetMQM_TX_SM_DESIGNATE_VFID_CNT_mqm_tx_sm_designate_vfid_cnt(unsigned int umqm_tx_sm_designate_vfid_cnt); +int iSetMQM_TX_QU_DESIGNATE_VFID_CNT_mqm_tx_qu_designate_vfid_cnt(unsigned int umqm_tx_qu_designate_vfid_cnt); +int iSetMQM_RCV_TILE_API_OP_ERR_CNT_mqm_rcv_tile_opid_err_cnt(unsigned int umqm_rcv_tile_opid_err_cnt); +int iSetMQM_RCV_TILE_FAST_CNP_API_CNT_mqm_rcv_tile_fast_cnp_cnt(unsigned int umqm_rcv_tile_fast_cnp_cnt); +int iSetMQM_RCV_TILE_CNP_API_E0E1_CNT_mqm_rcv_tile_fast_cnp_e0e1_cnt(unsigned int umqm_rcv_tile_fast_cnp_e0e1_cnt); +int iSetMQM_ND_RS_RQST_CREDIT_mqm_nd_rs_rqst_credit(unsigned int umqm_nd_rs_rqst_credit); +int iSetMQM_TOP_FIFO_ST_mqm_top_fifo0_st(unsigned int umqm_top_fifo0_st); +int iSetMQM_TOP_FIFO_ST_mqm_top_fifo1_st(unsigned int umqm_top_fifo1_st); + +/* Define the union csr_enqc_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv0_u; + +/* Define the union csr_enqc_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv1_u; + +/* Define the union csr_enqc_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv2_u; + +/* Define the union csr_enqc_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv3_u; + +/* Define the union csr_enqc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 enqc_indrect_tab : 4; /* [27:24] */ + u32 enqc_indrect_status : 2; /* [29:28] */ + u32 enqc_indrect_mode : 1; /* [30] */ + u32 enqc_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_ctrl_u; + +/* Define the union csr_enqc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_timeout_u; + +/* Define the union csr_enqc_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_data_0_u; + +/* Define the union csr_enqc_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_data_1_u; + +/* Define the union csr_enqc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 enqc_enable : 1; /* [27] */ + u32 enqc_int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_int_vector_u; + +/* Define the union csr_enqc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_int_data : 13; /* [12:0] */ + u32 rsv_3 : 3; /* [15:13] */ + u32 enqc_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_int_u; + +/* Define the union csr_enqc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_int_en : 13; /* [12:0] */ + u32 rsv_4 : 3; /* [15:13] */ + u32 enqc_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_int_en_u; + +/* Define the union csr_enqc_mem_ecc_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc0_err : 1; /* [0] */ + u32 enqc_ecc0_err_insert : 1; /* [1] */ + u32 enqc_ecc0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_err0_u; + +/* Define the union csr_enqc_mem_ecc_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc1_err : 1; /* [0] */ + u32 enqc_ecc1_err_insert : 1; /* [1] */ + u32 enqc_ecc1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_err1_u; + +/* Define the union csr_table_rd_invld_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 table_rd_err : 1; /* [0] */ + u32 table_rd_err_insert : 1; /* [1] */ + u32 table_rd_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_table_rd_invld_int_u; + +/* Define the union csr_vfpf_to_host_id_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfpf_hid_err : 1; /* [0] */ + u32 vfpf_hid_err_insert : 1; /* [1] */ + u32 vfpf_hid_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vfpf_to_host_id_int_u; + +/* Define the union csr_qu_enqc_db_if_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_enqc_db_interface_err : 1; /* [0] */ + u32 qu_enqc_db_interface_err_insert : 1; /* [1] */ + u32 qu_enqc_db_interface_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_enqc_db_if_int_u; + +/* Define the union csr_cpi_discard_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_discard_int_err : 1; /* [0] */ + u32 cpi_discard_int_err_insert : 1; /* [1] */ + u32 cpi_discard_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_discard_int_u; + +/* Define the union csr_enqc_fifo_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_fifo_wr_ovfl_int_err : 1; /* [0] */ + u32 cpi_fifo_wr_ovfl_int_err_insert : 1; /* [1] */ + u32 tile_fifo_wr_ovfl_int_err : 1; /* [2] */ + u32 tile_fifo_wr_ovfl_int_err_insert : 1; /* [3] */ + u32 sm_fifo_wr_ovfl_int_err : 1; /* [4] */ + u32 sm_fifo_wr_ovfl_int_err_insert : 1; /* [5] */ + u32 mrf_fifo_wr_ovfl_int_err : 1; /* [6] */ + u32 mrf_fifo_wr_ovfl_int_err_insert : 1; /* [7] */ + u32 dul_fifo_wr_ovfl_int_err : 1; /* [8] */ + u32 dul_fifo_wr_ovfl_int_err_insert : 1; /* [9] */ + u32 emq_enq_fifo_wr_ovfl_int_err : 1; /* [10] */ + u32 emq_enq_fifo_wr_ovfl_int_err_insert : 1; /* [11] */ + u32 cpi_fifo_rd_udfl_int_err : 1; /* [12] */ + u32 cpi_fifo_rd_udfl_int_err_insert : 1; /* [13] */ + u32 emq_enq_fifo_rd_udfl_int_err : 1; /* [14] */ + u32 emq_enq_fifo_rd_udfl_int_err_insert : 1; /* [15] */ + u32 passthru_fifo_rd_udfl_int_err : 1; /* [16] */ + u32 passthru_fifo_rd_udfl_int_err_insert : 1; /* [17] */ + u32 passthru_fifo_wr_ovfl_int_err : 1; /* [18] */ + u32 passthru_fifo_wr_ovfl_int_err_insert : 1; /* [19] */ + u32 qu_fifo_wr_ovfl_int_err : 1; /* [20] */ + u32 qu_fifo_wr_ovfl_int_err_insert : 1; /* [21] */ + u32 qu_fifo_rd_udfl_int_err : 1; /* [22] */ + u32 qu_fifo_rd_udfl_int_err_insert : 1; /* [23] */ + u32 tile_fifo_rd_udfl_int_err : 1; /* [24] */ + u32 tile_fifo_rd_udfl_int_err_insert : 1; /* [25] */ + u32 sm_fifo_rd_udfl_int_err : 1; /* [26] */ + u32 sm_fifo_rd_udfl_int_err_insert : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_fifo_int_u; + +/* Define the union csr_enqc_fifo_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_fifo_wr_ovfl_int_err_en : 1; /* [0] */ + u32 tile_fifo_wr_ovfl_int_err_en : 1; /* [1] */ + u32 sm_fifo_wr_ovfl_int_err_en : 1; /* [2] */ + u32 mrf_fifo_wr_ovfl_int_err_en : 1; /* [3] */ + u32 dul_fifo_wr_ovfl_int_err_en : 1; /* [4] */ + u32 emq_enq_fifo_wr_ovfl_int_err_en : 1; /* [5] */ + u32 cpi_fifo_rd_udfl_int_err_en : 1; /* [6] */ + u32 emq_enq_fifo_rd_udfl_int_err_en : 1; /* [7] */ + u32 passthru_fifo_rd_udfl_int_err_en : 1; /* [8] */ + u32 passthru_fifo_wr_ovfl_int_err_en : 1; /* [9] */ + u32 qu_fifo_rd_udfl_int_err_en : 1; /* [10] */ + u32 qu_fifo_wr_ovfl_int_err_en : 1; /* [11] */ + u32 tile_fifo_rd_udfl_int_err_en : 1; /* [12] */ + u32 sm_fifo_rd_udfl_int_err_en : 1; /* [13] */ + u32 rsv_6 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_fifo_int_en_u; + +/* Define the union csr_enqc_qf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_qf_int_err : 1; /* [0] */ + u32 enqc_qf_int_err_insert : 1; /* [1] */ + u32 enqc_qf_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_qf_int_u; + +/* Define the union csr_rx_ring_e0_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_e0_err : 1; /* [0] */ + u32 ring_e0_err_insert : 1; /* [1] */ + u32 ring_e0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_ring_e0_err_int_u; + +/* Define the union csr_rx_ring_e1_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_e1_err : 1; /* [0] */ + u32 ring_e1_err_insert : 1; /* [1] */ + u32 ring_e1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_ring_e1_err_int_u; + +/* Define the union csr_enqc_txqid_ovfl_vf_range_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txqid_ovfl_vf_range_int_err : 1; /* [0] */ + u32 txqid_ovfl_vf_range_int_err_insert : 1; /* [1] */ + u32 txqid_ovfl_vf_range_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_txqid_ovfl_vf_range_int_u; + +/* Define the union csr_enqc_nonf_num_ovfl_thr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nonf_num_ovfl_err : 1; /* [0] */ + u32 nonf_num_ovfl_err_insert : 1; /* [1] */ + u32 nonf_num_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_nonf_num_ovfl_thr_int_u; + +/* Define the union csr_enqc_err_typ_db_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_type_err : 1; /* [0] */ + u32 db_type_err_insert : 1; /* [1] */ + u32 db_type_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_err_typ_db_int_u; + +/* Define the union csr_enqc_mem_ecc_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfp1_mem_ecc_req : 2; /* [1:0] */ + u32 vfp2_mem_ecc_req : 2; /* [3:2] */ + u32 vfp3_mem_ecc_req : 2; /* [5:4] */ + u32 vfr_mem_ecc_req : 2; /* [7:6] */ + u32 vf2nmq_mem_ecc_req : 2; /* [9:8] */ + u32 vf2nfmq_mem_ecc_req : 2; /* [11:10] */ + u32 emq_cnt_mem_ecc_req : 2; /* [13:12] */ + u32 durf_fifo_a_mem_err_req : 2; /* [15:14] */ + u32 durf_fifo_b_mem_err_req : 2; /* [17:16] */ + u32 mrf_fifo_a_mem_err_req : 2; /* [19:18] */ + u32 mrf_fifo_b_mem_err_req : 2; /* [21:20] */ + u32 vf_pi_baddr_lim_mem_err_req : 2; /* [23:22] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_req0_u; + +/* Define the union csr_enqc_mem_ecc_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf2ep_mem_err_req : 2; /* [1:0] */ + u32 vf_range1_mem_err_req : 2; /* [3:2] */ + u32 vf_range2_mem_err_req : 2; /* [5:4] */ + u32 vf_range3_mem_err_req : 2; /* [7:6] */ + u32 vf_nonflt_thr_mem_err_req : 2; /* [9:8] */ + u32 vf_nonflt_cnt_mem_err_req : 2; /* [11:10] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_req1_u; + +/* Define the union csr_enqc_qu_db_if_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_enqc_db_if_err_en : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_qu_db_if_uncrt_int_en_u; + +/* Define the union csr_enqc_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qf_clr_err_uncrt_int_en : 1; /* [0] */ + u32 rx_ring_e1_uncrt_int_en : 1; /* [1] */ + u32 rx_ring_e0_uncrt_int_en : 1; /* [2] */ + u32 rsv_10 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_uncrt_int_en_u; + +/* Define the union csr_enqc_sendq_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_stxq_baddr : 21; /* [20:0] */ + u32 rsv_11 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sendq_base_addr_u; + +/* Define the union csr_enqc_sendq_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_stxq_lim : 21; /* [20:0] */ + u32 rsv_12 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sendq_scope_u; + +/* Define the union csr_enqc_taskio_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ttxq_baddr : 21; /* [20:0] */ + u32 rsv_13 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_taskio_base_addr_u; + +/* Define the union csr_enqc_taskio_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ttxq_lim : 21; /* [20:0] */ + u32 rsv_14 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_taskio_scope_u; + +/* Define the union csr_enqc_rdma_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_rtxq_baddr : 21; /* [20:0] */ + u32 rsv_15 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rdma_base_addr_u; + +/* Define the union csr_enqc_rdma_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_rtxq_lim : 21; /* [20:0] */ + u32 rsv_16 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rdma_scope_u; + +/* Define the union csr_enqc_ftxqid_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ftxq_baddr : 21; /* [20:0] */ + u32 rsv_17 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ftxqid_base_addr_u; + +/* Define the union csr_enqc_ftxqid_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ftxq_lim : 21; /* [20:0] */ + u32 rsv_18 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ftxqid_scope_u; + +/* Define the union csr_enqc_utxqid_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_utxq_baddr : 21; /* [20:0] */ + u32 rsv_19 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_utxqid_base_addr_u; + +/* Define the union csr_enqc_utxqid_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_utxq_lim : 21; /* [20:0] */ + u32 rsv_20 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_utxqid_scope_u; + +/* Define the union csr_soc_pf_base_lnic_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_base_lnic_sq_soc : 9; /* [8:0] */ + u32 rsv_21 : 3; /* [11:9] */ + u32 pf_base_lnic_rq_soc : 12; /* [23:12] */ + u32 rsv_22 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_pf_base_lnic_u; + +/* Define the union csr_soc_pf_range_lnic_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_range_dat_lnic_sq_soc : 8; /* [7:0] */ + u32 rsv_23 : 4; /* [11:8] */ + u32 pf_range_dat_lnic_rq_soc : 11; /* [22:12] */ + u32 rsv_24 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_pf_range_lnic_u; + +/* Define the union csr_enqc_host_lnic_sq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_sq_baddr : 17; /* [16:0] */ + u32 rsv_25 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_sq_cnt_baddr_u; + +/* Define the union csr_enqc_host_lnic_sq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_sq_lim : 17; /* [16:0] */ + u32 rsv_26 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_sq_cnt_limit_u; + +/* Define the union csr_enqc_host_lnic_rq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_rq_baddr : 17; /* [16:0] */ + u32 rsv_27 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_rq_cnt_baddr_u; + +/* Define the union csr_enqc_host_lnic_rq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_rq_lim : 17; /* [16:0] */ + u32 rsv_28 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_rq_cnt_limit_u; + +/* Define the union csr_enqc_sq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_send_baddr : 17; /* [16:0] */ + u32 rsv_29 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sq_cnt_baddr_u; + +/* Define the union csr_enqc_sq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_send_lim : 17; /* [16:0] */ + u32 rsv_30 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sq_cnt_limit_u; + +/* Define the union csr_enqc_host_cmq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_cmq_lim : 17; /* [16:0] */ + u32 rsv_31 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_cmq_cnt_limit_u; + +/* Define the union csr_enqc_pf_range_portx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_pf_func_idx_l : 5; /* [4:0] */ + u32 rsv_32 : 11; /* [15:5] */ + u32 portx_pf_func_idx_h : 5; /* [20:16] */ + u32 rsv_33 : 10; /* [30:21] */ + u32 portx_pf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_pf_range_portx_u; + +/* Define the union csr_enqc_vf_range_portx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_vf_func_idx_l : 12; /* [11:0] */ + u32 rsv_34 : 4; /* [15:12] */ + u32 portx_vf_func_idx_h : 12; /* [27:16] */ + u32 rsv_35 : 3; /* [30:28] */ + u32 portx_vf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_vf_range_portx_u; + +/* Define the union csr_enqc_lvf_range_portx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_lvf_func_idx_l : 12; /* [11:0] */ + u32 rsv_36 : 4; /* [15:12] */ + u32 portx_lvf_func_idx_h : 12; /* [27:16] */ + u32 rsv_37 : 3; /* [30:28] */ + u32 portx_lvf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_lvf_range_portx_u; + +/* Define the union csr_enqc_enqc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq2emq_cfg : 1; /* [0] */ + u32 rsv_38 : 3; /* [3:1] */ + u32 enqc_qf_rdma_half_cfg : 1; /* [4] */ + u32 rsv_39 : 7; /* [11:5] */ + u32 cpi_discard_en : 1; /* [12] */ + u32 rsv_40 : 3; /* [15:13] */ + u32 rx_du_length_unit : 5; /* [20:16] */ + u32 rsv_41 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_enqc_cfg_u; + +/* Define the union csr_soc_stateful_db_map_hid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_stateful_db_map_hid : 2; /* [1:0] */ + u32 soc_stateful_db_map_vld : 1; /* [2] */ + u32 rsv_42 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_stateful_db_map_hid_u; + +/* Define the union csr_enqc_in_fifo_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_aful_gap : 4; /* [3:0] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 tile_aful_gap : 3; /* [10:8] */ + u32 rsv_44 : 5; /* [15:11] */ + u32 qu_aful_gap : 4; /* [19:16] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 sm_aful_gap : 3; /* [26:24] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_in_fifo_gap_u; + +/* Define the union csr_enqc_eqm_pt_fifo_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_fifo_aful_gap : 4; /* [3:0] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 emq_enq_fifo_afull_gap : 4; /* [11:8] */ + u32 rsv_48 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_eqm_pt_fifo_gap_u; + +/* Define the union csr_enqc_mrf_fifo_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mrf_afull_th : 9; /* [8:0] */ + u32 rsv_49 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mrf_fifo_bp_th_u; + +/* Define the union csr_enqc_durf_fifo_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 durf_afull_th : 9; /* [8:0] */ + u32 rsv_50 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_durf_fifo_bp_th_u; + +/* Define the union csr_enqc_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_weight : 8; /* [7:0] */ + u32 tile_weight : 8; /* [15:8] */ + u32 sm_weight : 8; /* [23:16] */ + u32 rsv_51 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_wrr_weight0_u; + +/* Define the union csr_enqc_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_weight : 8; /* [7:0] */ + u32 rsv_52 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_wrr_weight1_u; + +/* Define the union csr_enqc_rx_du_len_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_du_len_clr : 1; /* [0] */ + u32 rsv_53 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_du_len_clr_u; + +/* Define the union csr_enqc_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_54 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_bypass_en_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_55 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_enqc_host_cmq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_cmq_baddr : 17; /* [16:0] */ + u32 rsv_56 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_cmq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_lnic_sq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_lnic_sq_baddr : 17; /* [16:0] */ + u32 rsv_57 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_lnic_sq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_lnic_rq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_lnic_rq_baddr : 17; /* [16:0] */ + u32 rsv_58 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_lnic_rq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_cmq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_cmq_baddr : 17; /* [16:0] */ + u32 rsv_59 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_cmq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_db_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_lnic_sq_lim : 9; /* [8:0] */ + u32 rsv_60 : 3; /* [11:9] */ + u32 cnt_soc_lnic_rq_lim : 11; /* [22:12] */ + u32 rsv_61 : 1; /* [23] */ + u32 cnt_soc_cmq_lim : 7; /* [30:24] */ + u32 rsv_62 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_db_cnt_limit_u; + +/* Define the union csr_pass_through_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_enable : 1; /* [0] */ + u32 rsv_63 : 7; /* [7:1] */ + u32 passthrou_timeout_value : 4; /* [11:8] */ + u32 rsv_64 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pass_through_cfg_u; + +/* Define the union csr_enqc_root_host_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_xon_inmq : 4; /* [3:0] */ + u32 host_xon_infmq : 4; /* [7:4] */ + u32 root_xon_inmq : 1; /* [8] */ + u32 rsv_65 : 3; /* [11:9] */ + u32 root_xon_infmq : 1; /* [12] */ + u32 rsv_66 : 3; /* [15:13] */ + u32 root_xon_total : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_root_host_xon_sta_u; + +/* Define the union csr_enqc_hostep_inmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_xon_inmq_h0 : 8; /* [7:0] */ + u32 ep_xon_inmq_h1 : 8; /* [15:8] */ + u32 ep_xon_inmq_h2 : 8; /* [23:16] */ + u32 ep_xon_inmq_h3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hostep_inmq_xon_sta_u; + +/* Define the union csr_enqc_hostep_infmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_xon_infmq_h0 : 8; /* [7:0] */ + u32 ep_xon_infmq_h1 : 8; /* [15:8] */ + u32 ep_xon_infmq_h2 : 8; /* [23:16] */ + u32 ep_xon_infmq_h3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hostep_infmq_xon_sta_u; + +/* Define the union csr_enqc_hec_inmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hec_xon_inmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hec_inmq_xon_sta_u; + +/* Define the union csr_enqc_hec_infmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hec_xon_infmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hec_infmq_xon_sta_u; + +/* Define the union csr_enqc_que_inmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 que_xon_inmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_que_inmq_xon_sta_u; + +/* Define the union csr_enqc_que_infmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 que_xon_infmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_que_infmq_xon_sta_u; + +/* Define the union csr_enqc_flush_qf_emqcnt_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flush_soc_cmd_qf_done : 1; /* [0] */ + u32 flush_host_cmd_qf_done : 1; /* [1] */ + u32 flush_soc_ls_qf_done : 1; /* [2] */ + u32 flush_soc_lr_qf_done : 1; /* [3] */ + u32 flush_host_ls_qf_done : 1; /* [4] */ + u32 flush_host_lr_qf_done : 1; /* [5] */ + u32 flush_sq_qf_done : 1; /* [6] */ + u32 flush_rq_qf_done : 1; /* [7] */ + u32 flush_ucode_qf_done : 1; /* [8] */ + u32 flush_rdma_qf_done : 1; /* [9] */ + u32 flush_emqcnt_done : 1; /* [10] */ + u32 flush_pt_fifo_done : 1; /* [11] */ + u32 rsv_68 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_flush_qf_emqcnt_done_u; + +/* Define the union csr_enqc_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ecc_1bit_err_cnt_u; + +/* Define the union csr_enqc_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ecc_2bit_err_cnt_u; + +/* Define the union csr_enqc_rx_du_packet_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_du_pkt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_du_packet_u; + +/* Define the union csr_enqc_rx_du_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_du_length : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_du_length_u; + +/* Define the union csr_cpi_in_emqcnt_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_cnt : 5; /* [4:0] */ + u32 rsv_69 : 3; /* [7:5] */ + u32 cpi_full : 1; /* [8] */ + u32 rsv_70 : 3; /* [11:9] */ + u32 cpi_empt : 1; /* [12] */ + u32 rsv_71 : 3; /* [15:13] */ + u32 emqenq_fifo_cnt : 5; /* [20:16] */ + u32 rsv_72 : 3; /* [23:21] */ + u32 emqenq_fifo_full : 1; /* [24] */ + u32 rsv_73 : 3; /* [27:25] */ + u32 emqenq_fifo_empt : 1; /* [28] */ + u32 rsv_74 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_in_emqcnt_fifo_status_u; + +/* Define the union csr_sm_in_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_wfifo_cnt : 4; /* [3:0] */ + u32 rsv_75 : 4; /* [7:4] */ + u32 sm_full : 1; /* [8] */ + u32 rsv_76 : 3; /* [11:9] */ + u32 sm_aful : 1; /* [12] */ + u32 rsv_77 : 3; /* [15:13] */ + u32 sm_empt : 1; /* [16] */ + u32 rsv_78 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_in_fifo_status_u; + +/* Define the union csr_tile_qu_in_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_wfifo_cnt : 4; /* [3:0] */ + u32 rsv_79 : 4; /* [7:4] */ + u32 tile_full : 1; /* [8] */ + u32 rsv_80 : 3; /* [11:9] */ + u32 tile_empt : 1; /* [12] */ + u32 rsv_81 : 3; /* [15:13] */ + u32 qu_wfifo_cnt : 5; /* [20:16] */ + u32 rsv_82 : 3; /* [23:21] */ + u32 qu_full : 1; /* [24] */ + u32 rsv_83 : 3; /* [27:25] */ + u32 qu_empt : 1; /* [28] */ + u32 rsv_84 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qu_in_fifo_status_u; + +/* Define the union csr_enqc_mrf_du_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mrf_fifo_cnt : 9; /* [8:0] */ + u32 rsv_85 : 3; /* [11:9] */ + u32 mrf_fifo_full : 1; /* [12] */ + u32 mrf_fifo_empt : 1; /* [13] */ + u32 mrf_fifo_aful : 1; /* [14] */ + u32 rsv_86 : 1; /* [15] */ + u32 durf_fifo_cnt : 9; /* [24:16] */ + u32 rsv_87 : 3; /* [27:25] */ + u32 durf_fifo_full : 1; /* [28] */ + u32 durf_fifo_empt : 1; /* [29] */ + u32 durf_fifo_aful : 1; /* [30] */ + u32 rsv_88 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mrf_du_fifo_status_u; + +/* Define the union csr_enqc_passthru_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_fifo_cnt : 5; /* [4:0] */ + u32 rsv_89 : 3; /* [7:5] */ + u32 passthru_fifo_dfx : 2; /* [9:8] */ + u32 rsv_90 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_passthru_fifo_status_u; + +/* Define the union csr_enqc_input_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cpi_db_bp : 1; /* [0] */ + u32 rsv_91 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_input_bp_u; + +/* Define the union csr_enqc_eqm_qd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_eqm_qd_cnt : 23; /* [22:0] */ + u32 rsv_92 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_eqm_qd_cnt_u; + +/* Define the union csr_enqc_rx_cpi_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_cpi_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_cpi_pkt_cnt_u; + +/* Define the union csr_enqc_rx_sm_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_sm_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_pkt_cnt_u; + +/* Define the union csr_enqc_rx_tile_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_tile_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_tile_pkt_cnt_u; + +/* Define the union csr_enqc_rx_qu_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_qu_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_qu_pkt_cnt_u; + +/* Define the union csr_enqc_dis_cpi_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_dis_cpi_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_dis_cpi_cnt_u; + +/* Define the union csr_enqc_rx_ring_err_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_ring_err_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_ring_err_db_cnt_u; + +/* Define the union csr_enqc_enq_iqm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_iqm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_enq_iqm_cnt_u; + +/* Define the union csr_enqc_enq_eqm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_eqm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_enq_eqm_cnt_u; + +/* Define the union csr_enqc_filterd_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_filterd_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_filterd_db_cnt_u; + +/* Define the union csr_enqc_rx_sm_cp_sge_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_cp_sge_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_cp_sge_crdt_u; + +/* Define the union csr_enqc_rx_sm_dp_sge_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_dp_sge_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_dp_sge_crdt_u; + +/* Define the union csr_enqc_rx_sm_cp_data_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_cp_data_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_cp_data_crdt_u; + +/* Define the union csr_enqc_rx_sm_dp_data_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_dp_data_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_dp_data_crdt_u; + +/* Define the union csr_enqc_rx_dp_nofl_db_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_dp_nofl_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_dp_nofl_db_u; + +/* Define the union csr_db_ovfl_vf_range_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_ovfl_vf_range_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_ovfl_vf_range_cnt_u; + +/* Define the union csr_nonf_db_num_ovfl_thr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nonf_db_num_ovfl_thr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nonf_db_num_ovfl_thr_cnt_u; + +/* Define the union csr_mqm_err_typ_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_err_typ_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_err_typ_db_cnt_u; + +/* Define the union csr_pass_through_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_fsm : 2; /* [1:0] */ + u32 rsv_93 : 2; /* [3:2] */ + u32 passthru_fifo_status : 2; /* [5:4] */ + u32 rsv_94 : 10; /* [15:6] */ + u32 iqm_enqc_inner_empt : 1; /* [16] */ + u32 eqm_enqc_outer_empt : 1; /* [17] */ + u32 enqc_passthru_pipe_empt : 1; /* [18] */ + u32 rsv_95 : 1; /* [19] */ + u32 iqm_enqc_inner_bp : 1; /* [20] */ + u32 qu_mqm_underload : 1; /* [21] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pass_through_sta_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_enqc_rw_rsv0_u enqc_rw_rsv0; /* 0 */ + volatile csr_enqc_rw_rsv1_u enqc_rw_rsv1; /* 4 */ + volatile csr_enqc_rw_rsv2_u enqc_rw_rsv2; /* 8 */ + volatile csr_enqc_rw_rsv3_u enqc_rw_rsv3; /* C */ + volatile csr_enqc_indrect_ctrl_u enqc_indrect_ctrl; /* 10 */ + volatile csr_enqc_indrect_timeout_u enqc_indrect_timeout; /* 14 */ + volatile csr_enqc_indrect_data_0_u enqc_indrect_data_0; /* 18 */ + volatile csr_enqc_indrect_data_1_u enqc_indrect_data_1; /* 1C */ + volatile csr_enqc_int_vector_u enqc_int_vector; /* 20 */ + volatile csr_enqc_int_u enqc_int; /* 24 */ + volatile csr_enqc_int_en_u enqc_int_en; /* 28 */ + volatile csr_enqc_mem_ecc_err0_u enqc_mem_ecc_err0; /* 2C */ + volatile csr_enqc_mem_ecc_err1_u enqc_mem_ecc_err1; /* 30 */ + volatile csr_table_rd_invld_int_u table_rd_invld_int; /* 34 */ + volatile csr_vfpf_to_host_id_int_u vfpf_to_host_id_int; /* 38 */ + volatile csr_qu_enqc_db_if_int_u qu_enqc_db_if_int; /* 3C */ + volatile csr_cpi_discard_int_u cpi_discard_int; /* 40 */ + volatile csr_enqc_fifo_int_u enqc_fifo_int; /* 44 */ + volatile csr_enqc_fifo_int_en_u enqc_fifo_int_en; /* 48 */ + volatile csr_enqc_qf_int_u enqc_qf_int; /* 4C */ + volatile csr_rx_ring_e0_err_int_u rx_ring_e0_err_int; /* 50 */ + volatile csr_rx_ring_e1_err_int_u rx_ring_e1_err_int; /* 54 */ + volatile csr_enqc_txqid_ovfl_vf_range_int_u enqc_txqid_ovfl_vf_range_int; /* 58 */ + volatile csr_enqc_nonf_num_ovfl_thr_int_u enqc_nonf_num_ovfl_thr_int; /* 5C */ + volatile csr_enqc_err_typ_db_int_u enqc_err_typ_db_int; /* 60 */ + volatile csr_enqc_mem_ecc_req0_u enqc_mem_ecc_req0; /* 80 */ + volatile csr_enqc_mem_ecc_req1_u enqc_mem_ecc_req1; /* 84 */ + volatile csr_enqc_qu_db_if_uncrt_int_en_u enqc_qu_db_if_uncrt_int_en; /* 88 */ + volatile csr_enqc_uncrt_int_en_u enqc_uncrt_int_en; /* 8C */ + volatile csr_enqc_sendq_base_addr_u enqc_sendq_base_addr; /* B0 */ + volatile csr_enqc_sendq_scope_u enqc_sendq_scope; /* B4 */ + volatile csr_enqc_taskio_base_addr_u enqc_taskio_base_addr; /* B8 */ + volatile csr_enqc_taskio_scope_u enqc_taskio_scope; /* BC */ + volatile csr_enqc_rdma_base_addr_u enqc_rdma_base_addr; /* C0 */ + volatile csr_enqc_rdma_scope_u enqc_rdma_scope; /* C4 */ + volatile csr_enqc_ftxqid_base_addr_u enqc_ftxqid_base_addr; /* C8 */ + volatile csr_enqc_ftxqid_scope_u enqc_ftxqid_scope; /* CC */ + volatile csr_enqc_utxqid_base_addr_u enqc_utxqid_base_addr; /* D0 */ + volatile csr_enqc_utxqid_scope_u enqc_utxqid_scope; /* D4 */ + volatile csr_soc_pf_base_lnic_u soc_pf_base_lnic[8]; /* D8 */ + volatile csr_soc_pf_range_lnic_u soc_pf_range_lnic[8]; /* F8 */ + volatile csr_enqc_host_lnic_sq_cnt_baddr_u enqc_host_lnic_sq_cnt_baddr; /* 118 */ + volatile csr_enqc_host_lnic_sq_cnt_limit_u enqc_host_lnic_sq_cnt_limit; /* 11C */ + volatile csr_enqc_host_lnic_rq_cnt_baddr_u enqc_host_lnic_rq_cnt_baddr; /* 120 */ + volatile csr_enqc_host_lnic_rq_cnt_limit_u enqc_host_lnic_rq_cnt_limit; /* 124 */ + volatile csr_enqc_sq_cnt_baddr_u enqc_sq_cnt_baddr; /* 128 */ + volatile csr_enqc_sq_cnt_limit_u enqc_sq_cnt_limit; /* 12C */ + volatile csr_enqc_host_cmq_cnt_limit_u enqc_host_cmq_cnt_limit; /* 130 */ + volatile csr_enqc_pf_range_portx_u enqc_pf_range_portx[5]; /* 134 */ + volatile csr_enqc_vf_range_portx_u enqc_vf_range_portx[4]; /* 148 */ + volatile csr_enqc_lvf_range_portx_u enqc_lvf_range_portx[4]; /* 158 */ + volatile csr_enqc_enqc_cfg_u enqc_enqc_cfg; /* 168 */ + volatile csr_soc_stateful_db_map_hid_u soc_stateful_db_map_hid; /* 16C */ + volatile csr_enqc_in_fifo_gap_u enqc_in_fifo_gap; /* 170 */ + volatile csr_enqc_eqm_pt_fifo_gap_u enqc_eqm_pt_fifo_gap; /* 174 */ + volatile csr_enqc_mrf_fifo_bp_th_u enqc_mrf_fifo_bp_th; /* 178 */ + volatile csr_enqc_durf_fifo_bp_th_u enqc_durf_fifo_bp_th; /* 17C */ + volatile csr_enqc_wrr_weight0_u enqc_wrr_weight0; /* 180 */ + volatile csr_enqc_wrr_weight1_u enqc_wrr_weight1; /* 184 */ + volatile csr_enqc_rx_du_len_clr_u enqc_rx_du_len_clr; /* 188 */ + volatile csr_enqc_mem_ecc_bypass_en_u enqc_mem_ecc_bypass_en; /* 18C */ + volatile csr_enqc_mem_ctrl_bus_cfg0_u enqc_mem_ctrl_bus_cfg0; /* 190 */ + volatile csr_enqc_mem_ctrl_bus_cfg1_u enqc_mem_ctrl_bus_cfg1; /* 194 */ + volatile csr_enqc_mem_ctrl_bus_cfg2_u enqc_mem_ctrl_bus_cfg2; /* 198 */ + volatile csr_enqc_mem_ctrl_bus_cfg3_u enqc_mem_ctrl_bus_cfg3; /* 19C */ + volatile csr_enqc_mem_ctrl_bus_cfg4_u enqc_mem_ctrl_bus_cfg4; /* 1A0 */ + volatile csr_enqc_host_cmq_cnt_baddr_u enqc_host_cmq_cnt_baddr; /* 1A4 */ + volatile csr_enqc_soc_lnic_sq_cnt_baddr_u enqc_soc_lnic_sq_cnt_baddr; /* 1A8 */ + volatile csr_enqc_soc_lnic_rq_cnt_baddr_u enqc_soc_lnic_rq_cnt_baddr; /* 1AC */ + volatile csr_enqc_soc_cmq_cnt_baddr_u enqc_soc_cmq_cnt_baddr; /* 1B0 */ + volatile csr_enqc_soc_db_cnt_limit_u enqc_soc_db_cnt_limit; /* 1B4 */ + volatile csr_pass_through_cfg_u pass_through_cfg; /* 1B8 */ + volatile csr_enqc_root_host_xon_sta_u enqc_root_host_xon_sta; /* 1C0 */ + volatile csr_enqc_hostep_inmq_xon_sta_u enqc_hostep_inmq_xon_sta; /* 1C4 */ + volatile csr_enqc_hostep_infmq_xon_sta_u enqc_hostep_infmq_xon_sta; /* 1C8 */ + volatile csr_enqc_hec_inmq_xon_sta_u enqc_hec_inmq_xon_sta[8]; /* 1CC */ + volatile csr_enqc_hec_infmq_xon_sta_u enqc_hec_infmq_xon_sta[8]; /* 1EC */ + volatile csr_enqc_que_inmq_xon_sta_u enqc_que_inmq_xon_sta[256]; /* 20C */ + volatile csr_enqc_que_infmq_xon_sta_u enqc_que_infmq_xon_sta[128]; /* 60C */ + volatile csr_enqc_flush_qf_emqcnt_done_u enqc_flush_qf_emqcnt_done; /* 80C */ + volatile csr_enqc_ecc_1bit_err_cnt_u enqc_ecc_1bit_err_cnt; /* 810 */ + volatile csr_enqc_ecc_2bit_err_cnt_u enqc_ecc_2bit_err_cnt; /* 814 */ + volatile csr_enqc_rx_du_packet_u enqc_rx_du_packet; /* 830 */ + volatile csr_enqc_rx_du_length_u enqc_rx_du_length; /* 834 */ + volatile csr_cpi_in_emqcnt_fifo_status_u cpi_in_emqcnt_fifo_status; /* 838 */ + volatile csr_sm_in_fifo_status_u sm_in_fifo_status; /* 83C */ + volatile csr_tile_qu_in_fifo_status_u tile_qu_in_fifo_status; /* 840 */ + volatile csr_enqc_mrf_du_fifo_status_u enqc_mrf_du_fifo_status; /* 844 */ + volatile csr_enqc_passthru_fifo_status_u enqc_passthru_fifo_status; /* 848 */ + volatile csr_enqc_input_bp_u enqc_input_bp; /* 84C */ + volatile csr_enqc_eqm_qd_cnt_u enqc_eqm_qd_cnt; /* 850 */ + volatile csr_enqc_rx_cpi_pkt_cnt_u enqc_rx_cpi_pkt_cnt; /* 854 */ + volatile csr_enqc_rx_sm_pkt_cnt_u enqc_rx_sm_pkt_cnt; /* 858 */ + volatile csr_enqc_rx_tile_pkt_cnt_u enqc_rx_tile_pkt_cnt; /* 85C */ + volatile csr_enqc_rx_qu_pkt_cnt_u enqc_rx_qu_pkt_cnt; /* 860 */ + volatile csr_enqc_dis_cpi_cnt_u enqc_dis_cpi_cnt; /* 864 */ + volatile csr_enqc_rx_ring_err_db_cnt_u enqc_rx_ring_err_db_cnt; /* 868 */ + volatile csr_enqc_enq_iqm_cnt_u enqc_enq_iqm_cnt; /* 86C */ + volatile csr_enqc_enq_eqm_cnt_u enqc_enq_eqm_cnt; /* 870 */ + volatile csr_enqc_filterd_db_cnt_u enqc_filterd_db_cnt; /* 874 */ + volatile csr_enqc_rx_sm_cp_sge_crdt_u enqc_rx_sm_cp_sge_crdt; /* 878 */ + volatile csr_enqc_rx_sm_dp_sge_crdt_u enqc_rx_sm_dp_sge_crdt; /* 87C */ + volatile csr_enqc_rx_sm_cp_data_crdt_u enqc_rx_sm_cp_data_crdt; /* 880 */ + volatile csr_enqc_rx_sm_dp_data_crdt_u enqc_rx_sm_dp_data_crdt; /* 884 */ + volatile csr_enqc_rx_dp_nofl_db_u enqc_rx_dp_nofl_db; /* 888 */ + volatile csr_db_ovfl_vf_range_cnt_u db_ovfl_vf_range_cnt; /* 88C */ + volatile csr_nonf_db_num_ovfl_thr_cnt_u nonf_db_num_ovfl_thr_cnt; /* 890 */ + volatile csr_mqm_err_typ_db_cnt_u mqm_err_typ_db_cnt; /* 894 */ + volatile csr_pass_through_sta_u pass_through_sta; /* 898 */ +} S_mqm_enqc_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_enqc */ +extern volatile S_mqm_enqc_REGS_TYPE *gopmqm_enqcAllReg; + +/* Declare the functions that set the member value */ +int iSetENQC_RW_RSV0_enqc_rw_rsv0(unsigned int uenqc_rw_rsv0); +int iSetENQC_RW_RSV1_enqc_rw_rsv1(unsigned int uenqc_rw_rsv1); +int iSetENQC_RW_RSV2_enqc_rw_rsv2(unsigned int uenqc_rw_rsv2); +int iSetENQC_RW_RSV3_enqc_rw_rsv3(unsigned int uenqc_rw_rsv3); +int iSetENQC_INDRECT_CTRL_enqc_indrect_addr(unsigned int uenqc_indrect_addr); +int iSetENQC_INDRECT_CTRL_enqc_indrect_tab(unsigned int uenqc_indrect_tab); +int iSetENQC_INDRECT_CTRL_enqc_indrect_status(unsigned int uenqc_indrect_status); +int iSetENQC_INDRECT_CTRL_enqc_indrect_mode(unsigned int uenqc_indrect_mode); +int iSetENQC_INDRECT_CTRL_enqc_indrect_vld(unsigned int uenqc_indrect_vld); +int iSetENQC_INDRECT_TIMEOUT_enqc_indrect_timeout(unsigned int uenqc_indrect_timeout); +int iSetENQC_INDRECT_DATA_0_enqc_indrect_data_0(unsigned int uenqc_indrect_data_0); +int iSetENQC_INDRECT_DATA_1_enqc_indrect_data_1(unsigned int uenqc_indrect_data_1); +int iSetENQC_INT_VECTOR_enqc_cpi_int_index(unsigned int uenqc_cpi_int_index); +int iSetENQC_INT_VECTOR_enqc_enable(unsigned int uenqc_enable); +int iSetENQC_INT_VECTOR_enqc_int_issue(unsigned int uenqc_int_issue); +int iSetENQC_INT_enqc_int_data(unsigned int uenqc_int_data); +int iSetENQC_INT_enqc_program_csr_id_ro(unsigned int uenqc_program_csr_id_ro); +int iSetENQC_INT_EN_enqc_int_en(unsigned int uenqc_int_en); +int iSetENQC_INT_EN_enqc_program_csr_id(unsigned int uenqc_program_csr_id); +int iSetENQC_MEM_ECC_ERR0_enqc_ecc0_err(unsigned int uenqc_ecc0_err); +int iSetENQC_MEM_ECC_ERR0_enqc_ecc0_err_insert(unsigned int uenqc_ecc0_err_insert); +int iSetENQC_MEM_ECC_ERR0_enqc_ecc0_err_info(unsigned int uenqc_ecc0_err_info); +int iSetENQC_MEM_ECC_ERR1_enqc_ecc1_err(unsigned int uenqc_ecc1_err); +int iSetENQC_MEM_ECC_ERR1_enqc_ecc1_err_insert(unsigned int uenqc_ecc1_err_insert); +int iSetENQC_MEM_ECC_ERR1_enqc_ecc1_err_info(unsigned int uenqc_ecc1_err_info); +int iSetTABLE_RD_INVLD_INT_table_rd_err(unsigned int utable_rd_err); +int iSetTABLE_RD_INVLD_INT_table_rd_err_insert(unsigned int utable_rd_err_insert); +int iSetTABLE_RD_INVLD_INT_table_rd_err_info(unsigned int utable_rd_err_info); +int iSetVFPF_TO_HOST_ID_INT_vfpf_hid_err(unsigned int uvfpf_hid_err); +int iSetVFPF_TO_HOST_ID_INT_vfpf_hid_err_insert(unsigned int uvfpf_hid_err_insert); +int iSetVFPF_TO_HOST_ID_INT_vfpf_hid_err_info(unsigned int uvfpf_hid_err_info); +int iSetQU_ENQC_DB_IF_INT_qu_enqc_db_interface_err(unsigned int uqu_enqc_db_interface_err); +int iSetQU_ENQC_DB_IF_INT_qu_enqc_db_interface_err_insert(unsigned int uqu_enqc_db_interface_err_insert); +int iSetQU_ENQC_DB_IF_INT_qu_enqc_db_interface_err_info(unsigned int uqu_enqc_db_interface_err_info); +int iSetCPI_DISCARD_INT_cpi_discard_int_err(unsigned int ucpi_discard_int_err); +int iSetCPI_DISCARD_INT_cpi_discard_int_err_insert(unsigned int ucpi_discard_int_err_insert); +int iSetCPI_DISCARD_INT_cpi_discard_int_err_info(unsigned int ucpi_discard_int_err_info); +int iSetENQC_FIFO_INT_cpi_fifo_wr_ovfl_int_err(unsigned int ucpi_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_cpi_fifo_wr_ovfl_int_err_insert(unsigned int ucpi_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_tile_fifo_wr_ovfl_int_err(unsigned int utile_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_tile_fifo_wr_ovfl_int_err_insert(unsigned int utile_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_sm_fifo_wr_ovfl_int_err(unsigned int usm_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_sm_fifo_wr_ovfl_int_err_insert(unsigned int usm_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_mrf_fifo_wr_ovfl_int_err(unsigned int umrf_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_mrf_fifo_wr_ovfl_int_err_insert(unsigned int umrf_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_dul_fifo_wr_ovfl_int_err(unsigned int udul_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_dul_fifo_wr_ovfl_int_err_insert(unsigned int udul_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_emq_enq_fifo_wr_ovfl_int_err(unsigned int uemq_enq_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_emq_enq_fifo_wr_ovfl_int_err_insert(unsigned int uemq_enq_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_cpi_fifo_rd_udfl_int_err(unsigned int ucpi_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_cpi_fifo_rd_udfl_int_err_insert(unsigned int ucpi_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_emq_enq_fifo_rd_udfl_int_err(unsigned int uemq_enq_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_emq_enq_fifo_rd_udfl_int_err_insert(unsigned int uemq_enq_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_passthru_fifo_rd_udfl_int_err(unsigned int upassthru_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_passthru_fifo_rd_udfl_int_err_insert(unsigned int upassthru_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_passthru_fifo_wr_ovfl_int_err(unsigned int upassthru_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_passthru_fifo_wr_ovfl_int_err_insert(unsigned int upassthru_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_qu_fifo_wr_ovfl_int_err(unsigned int uqu_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_qu_fifo_wr_ovfl_int_err_insert(unsigned int uqu_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_qu_fifo_rd_udfl_int_err(unsigned int uqu_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_qu_fifo_rd_udfl_int_err_insert(unsigned int uqu_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_tile_fifo_rd_udfl_int_err(unsigned int utile_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_tile_fifo_rd_udfl_int_err_insert(unsigned int utile_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_sm_fifo_rd_udfl_int_err(unsigned int usm_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_sm_fifo_rd_udfl_int_err_insert(unsigned int usm_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_EN_cpi_fifo_wr_ovfl_int_err_en(unsigned int ucpi_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_tile_fifo_wr_ovfl_int_err_en(unsigned int utile_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_sm_fifo_wr_ovfl_int_err_en(unsigned int usm_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_mrf_fifo_wr_ovfl_int_err_en(unsigned int umrf_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_dul_fifo_wr_ovfl_int_err_en(unsigned int udul_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_emq_enq_fifo_wr_ovfl_int_err_en(unsigned int uemq_enq_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_cpi_fifo_rd_udfl_int_err_en(unsigned int ucpi_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_emq_enq_fifo_rd_udfl_int_err_en(unsigned int uemq_enq_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_passthru_fifo_rd_udfl_int_err_en(unsigned int upassthru_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_passthru_fifo_wr_ovfl_int_err_en(unsigned int upassthru_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_qu_fifo_rd_udfl_int_err_en(unsigned int uqu_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_qu_fifo_wr_ovfl_int_err_en(unsigned int uqu_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_tile_fifo_rd_udfl_int_err_en(unsigned int utile_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_sm_fifo_rd_udfl_int_err_en(unsigned int usm_fifo_rd_udfl_int_err_en); +int iSetENQC_QF_INT_enqc_qf_int_err(unsigned int uenqc_qf_int_err); +int iSetENQC_QF_INT_enqc_qf_int_err_insert(unsigned int uenqc_qf_int_err_insert); +int iSetENQC_QF_INT_enqc_qf_int_err_info(unsigned int uenqc_qf_int_err_info); +int iSetRX_RING_E0_ERR_INT_ring_e0_err(unsigned int uring_e0_err); +int iSetRX_RING_E0_ERR_INT_ring_e0_err_insert(unsigned int uring_e0_err_insert); +int iSetRX_RING_E0_ERR_INT_ring_e0_err_info(unsigned int uring_e0_err_info); +int iSetRX_RING_E1_ERR_INT_ring_e1_err(unsigned int uring_e1_err); +int iSetRX_RING_E1_ERR_INT_ring_e1_err_insert(unsigned int uring_e1_err_insert); +int iSetRX_RING_E1_ERR_INT_ring_e1_err_info(unsigned int uring_e1_err_info); +int iSetENQC_TXQID_OVFL_VF_RANGE_INT_txqid_ovfl_vf_range_int_err(unsigned int utxqid_ovfl_vf_range_int_err); +int iSetENQC_TXQID_OVFL_VF_RANGE_INT_txqid_ovfl_vf_range_int_err_insert( + unsigned int utxqid_ovfl_vf_range_int_err_insert); +int iSetENQC_TXQID_OVFL_VF_RANGE_INT_txqid_ovfl_vf_range_int_err_info(unsigned int utxqid_ovfl_vf_range_int_err_info); +int iSetENQC_NONF_NUM_OVFL_THR_INT_nonf_num_ovfl_err(unsigned int unonf_num_ovfl_err); +int iSetENQC_NONF_NUM_OVFL_THR_INT_nonf_num_ovfl_err_insert(unsigned int unonf_num_ovfl_err_insert); +int iSetENQC_NONF_NUM_OVFL_THR_INT_nonf_num_ovfl_err_info(unsigned int unonf_num_ovfl_err_info); +int iSetENQC_ERR_TYP_DB_INT_db_type_err(unsigned int udb_type_err); +int iSetENQC_ERR_TYP_DB_INT_db_type_err_insert(unsigned int udb_type_err_insert); +int iSetENQC_ERR_TYP_DB_INT_db_type_err_info(unsigned int udb_type_err_info); +int iSetENQC_MEM_ECC_REQ0_vfp1_mem_ecc_req(unsigned int uvfp1_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vfp2_mem_ecc_req(unsigned int uvfp2_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vfp3_mem_ecc_req(unsigned int uvfp3_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vfr_mem_ecc_req(unsigned int uvfr_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vf2nmq_mem_ecc_req(unsigned int uvf2nmq_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vf2nfmq_mem_ecc_req(unsigned int uvf2nfmq_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_emq_cnt_mem_ecc_req(unsigned int uemq_cnt_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_durf_fifo_a_mem_err_req(unsigned int udurf_fifo_a_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_durf_fifo_b_mem_err_req(unsigned int udurf_fifo_b_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_mrf_fifo_a_mem_err_req(unsigned int umrf_fifo_a_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_mrf_fifo_b_mem_err_req(unsigned int umrf_fifo_b_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_vf_pi_baddr_lim_mem_err_req(unsigned int uvf_pi_baddr_lim_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf2ep_mem_err_req(unsigned int uvf2ep_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_range1_mem_err_req(unsigned int uvf_range1_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_range2_mem_err_req(unsigned int uvf_range2_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_range3_mem_err_req(unsigned int uvf_range3_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_nonflt_thr_mem_err_req(unsigned int uvf_nonflt_thr_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_nonflt_cnt_mem_err_req(unsigned int uvf_nonflt_cnt_mem_err_req); +int iSetENQC_QU_DB_IF_UNCRT_INT_EN_qu_enqc_db_if_err_en(unsigned int uqu_enqc_db_if_err_en); +int iSetENQC_UNCRT_INT_EN_qf_clr_err_uncrt_int_en(unsigned int uqf_clr_err_uncrt_int_en); +int iSetENQC_UNCRT_INT_EN_rx_ring_e1_uncrt_int_en(unsigned int urx_ring_e1_uncrt_int_en); +int iSetENQC_UNCRT_INT_EN_rx_ring_e0_uncrt_int_en(unsigned int urx_ring_e0_uncrt_int_en); +int iSetENQC_SENDQ_BASE_ADDR_flt_stxq_baddr(unsigned int uflt_stxq_baddr); +int iSetENQC_SENDQ_SCOPE_flt_stxq_lim(unsigned int uflt_stxq_lim); +int iSetENQC_TASKIO_BASE_ADDR_flt_ttxq_baddr(unsigned int uflt_ttxq_baddr); +int iSetENQC_TASKIO_SCOPE_flt_ttxq_lim(unsigned int uflt_ttxq_lim); +int iSetENQC_RDMA_BASE_ADDR_flt_rtxq_baddr(unsigned int uflt_rtxq_baddr); +int iSetENQC_RDMA_SCOPE_flt_rtxq_lim(unsigned int uflt_rtxq_lim); +int iSetENQC_FTXQID_BASE_ADDR_flt_ftxq_baddr(unsigned int uflt_ftxq_baddr); +int iSetENQC_FTXQID_SCOPE_flt_ftxq_lim(unsigned int uflt_ftxq_lim); +int iSetENQC_UTXQID_BASE_ADDR_flt_utxq_baddr(unsigned int uflt_utxq_baddr); +int iSetENQC_UTXQID_SCOPE_flt_utxq_lim(unsigned int uflt_utxq_lim); +int iSetSOC_PF_BASE_LNIC_pf_base_lnic_sq_soc(unsigned int upf_base_lnic_sq_soc); +int iSetSOC_PF_BASE_LNIC_pf_base_lnic_rq_soc(unsigned int upf_base_lnic_rq_soc); +int iSetSOC_PF_RANGE_LNIC_pf_range_dat_lnic_sq_soc(unsigned int upf_range_dat_lnic_sq_soc); +int iSetSOC_PF_RANGE_LNIC_pf_range_dat_lnic_rq_soc(unsigned int upf_range_dat_lnic_rq_soc); +int iSetENQC_HOST_LNIC_SQ_CNT_BADDR_cnt_host_lnic_sq_baddr(unsigned int ucnt_host_lnic_sq_baddr); +int iSetENQC_HOST_LNIC_SQ_CNT_LIMIT_cnt_host_lnic_sq_lim(unsigned int ucnt_host_lnic_sq_lim); +int iSetENQC_HOST_LNIC_RQ_CNT_BADDR_cnt_host_lnic_rq_baddr(unsigned int ucnt_host_lnic_rq_baddr); +int iSetENQC_HOST_LNIC_RQ_CNT_LIMIT_cnt_host_lnic_rq_lim(unsigned int ucnt_host_lnic_rq_lim); +int iSetENQC_SQ_CNT_BADDR_cnt_send_baddr(unsigned int ucnt_send_baddr); +int iSetENQC_SQ_CNT_LIMIT_cnt_send_lim(unsigned int ucnt_send_lim); +int iSetENQC_HOST_CMQ_CNT_LIMIT_cnt_host_cmq_lim(unsigned int ucnt_host_cmq_lim); +int iSetENQC_PF_RANGE_PORTX_portx_pf_func_idx_l(unsigned int uportx_pf_func_idx_l); +int iSetENQC_PF_RANGE_PORTX_portx_pf_func_idx_h(unsigned int uportx_pf_func_idx_h); +int iSetENQC_PF_RANGE_PORTX_portx_pf_func_idx_v(unsigned int uportx_pf_func_idx_v); +int iSetENQC_VF_RANGE_PORTX_portx_vf_func_idx_l(unsigned int uportx_vf_func_idx_l); +int iSetENQC_VF_RANGE_PORTX_portx_vf_func_idx_h(unsigned int uportx_vf_func_idx_h); +int iSetENQC_VF_RANGE_PORTX_portx_vf_func_idx_v(unsigned int uportx_vf_func_idx_v); +int iSetENQC_LVF_RANGE_PORTX_portx_lvf_func_idx_l(unsigned int uportx_lvf_func_idx_l); +int iSetENQC_LVF_RANGE_PORTX_portx_lvf_func_idx_h(unsigned int uportx_lvf_func_idx_h); +int iSetENQC_LVF_RANGE_PORTX_portx_lvf_func_idx_v(unsigned int uportx_lvf_func_idx_v); +int iSetENQC_ENQC_CFG_enqc_enq2emq_cfg(unsigned int uenqc_enq2emq_cfg); +int iSetENQC_ENQC_CFG_enqc_qf_rdma_half_cfg(unsigned int uenqc_qf_rdma_half_cfg); +int iSetENQC_ENQC_CFG_cpi_discard_en(unsigned int ucpi_discard_en); +int iSetENQC_ENQC_CFG_rx_du_length_unit(unsigned int urx_du_length_unit); +int iSetSOC_STATEFUL_DB_MAP_HID_soc_stateful_db_map_hid(unsigned int usoc_stateful_db_map_hid); +int iSetSOC_STATEFUL_DB_MAP_HID_soc_stateful_db_map_vld(unsigned int usoc_stateful_db_map_vld); +int iSetENQC_IN_FIFO_GAP_cpi_aful_gap(unsigned int ucpi_aful_gap); +int iSetENQC_IN_FIFO_GAP_tile_aful_gap(unsigned int utile_aful_gap); +int iSetENQC_IN_FIFO_GAP_qu_aful_gap(unsigned int uqu_aful_gap); +int iSetENQC_IN_FIFO_GAP_sm_aful_gap(unsigned int usm_aful_gap); +int iSetENQC_EQM_PT_FIFO_GAP_passthru_fifo_aful_gap(unsigned int upassthru_fifo_aful_gap); +int iSetENQC_EQM_PT_FIFO_GAP_emq_enq_fifo_afull_gap(unsigned int uemq_enq_fifo_afull_gap); +int iSetENQC_MRF_FIFO_BP_TH_mrf_afull_th(unsigned int umrf_afull_th); +int iSetENQC_DURF_FIFO_BP_TH_durf_afull_th(unsigned int udurf_afull_th); +int iSetENQC_WRR_WEIGHT0_cpi_weight(unsigned int ucpi_weight); +int iSetENQC_WRR_WEIGHT0_tile_weight(unsigned int utile_weight); +int iSetENQC_WRR_WEIGHT0_sm_weight(unsigned int usm_weight); +int iSetENQC_WRR_WEIGHT1_qu_weight(unsigned int uqu_weight); +int iSetENQC_RX_DU_LEN_CLR_enqc_rx_du_len_clr(unsigned int uenqc_rx_du_len_clr); +int iSetENQC_MEM_ECC_BYPASS_EN_enqc_mem_ecc_bypass(unsigned int uenqc_mem_ecc_bypass); +int iSetENQC_MEM_CTRL_BUS_CFG0_enqc_mem_ctrl_bus_0(unsigned int uenqc_mem_ctrl_bus_0); +int iSetENQC_MEM_CTRL_BUS_CFG1_enqc_mem_ctrl_bus_1(unsigned int uenqc_mem_ctrl_bus_1); +int iSetENQC_MEM_CTRL_BUS_CFG2_enqc_mem_ctrl_bus_2(unsigned int uenqc_mem_ctrl_bus_2); +int iSetENQC_MEM_CTRL_BUS_CFG3_enqc_mem_ctrl_bus_3(unsigned int uenqc_mem_ctrl_bus_3); +int iSetENQC_MEM_CTRL_BUS_CFG4_enqc_mem_ctrl_bus_4(unsigned int uenqc_mem_ctrl_bus_4); +int iSetENQC_HOST_CMQ_CNT_BADDR_cnt_host_cmq_baddr(unsigned int ucnt_host_cmq_baddr); +int iSetENQC_SOC_LNIC_SQ_CNT_BADDR_cnt_soc_lnic_sq_baddr(unsigned int ucnt_soc_lnic_sq_baddr); +int iSetENQC_SOC_LNIC_RQ_CNT_BADDR_cnt_soc_lnic_rq_baddr(unsigned int ucnt_soc_lnic_rq_baddr); +int iSetENQC_SOC_CMQ_CNT_BADDR_cnt_soc_cmq_baddr(unsigned int ucnt_soc_cmq_baddr); +int iSetENQC_SOC_DB_CNT_LIMIT_cnt_soc_lnic_sq_lim(unsigned int ucnt_soc_lnic_sq_lim); +int iSetENQC_SOC_DB_CNT_LIMIT_cnt_soc_lnic_rq_lim(unsigned int ucnt_soc_lnic_rq_lim); +int iSetENQC_SOC_DB_CNT_LIMIT_cnt_soc_cmq_lim(unsigned int ucnt_soc_cmq_lim); +int iSetPASS_THROUGH_CFG_passthru_enable(unsigned int upassthru_enable); +int iSetPASS_THROUGH_CFG_passthrou_timeout_value(unsigned int upassthrou_timeout_value); +int iSetENQC_ROOT_HOST_XON_STA_host_xon_inmq(unsigned int uhost_xon_inmq); +int iSetENQC_ROOT_HOST_XON_STA_host_xon_infmq(unsigned int uhost_xon_infmq); +int iSetENQC_ROOT_HOST_XON_STA_root_xon_inmq(unsigned int uroot_xon_inmq); +int iSetENQC_ROOT_HOST_XON_STA_root_xon_infmq(unsigned int uroot_xon_infmq); +int iSetENQC_ROOT_HOST_XON_STA_root_xon_total(unsigned int uroot_xon_total); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h0(unsigned int uep_xon_inmq_h0); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h1(unsigned int uep_xon_inmq_h1); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h2(unsigned int uep_xon_inmq_h2); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h3(unsigned int uep_xon_inmq_h3); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h0(unsigned int uep_xon_infmq_h0); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h1(unsigned int uep_xon_infmq_h1); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h2(unsigned int uep_xon_infmq_h2); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h3(unsigned int uep_xon_infmq_h3); +int iSetENQC_HEC_INMQ_XON_STA_hec_xon_inmq(unsigned int uhec_xon_inmq); +int iSetENQC_HEC_INFMQ_XON_STA_hec_xon_infmq(unsigned int uhec_xon_infmq); +int iSetENQC_QUE_INMQ_XON_STA_que_xon_inmq(unsigned int uque_xon_inmq); +int iSetENQC_QUE_INFMQ_XON_STA_que_xon_infmq(unsigned int uque_xon_infmq); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_soc_cmd_qf_done(unsigned int uflush_soc_cmd_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_host_cmd_qf_done(unsigned int uflush_host_cmd_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_soc_ls_qf_done(unsigned int uflush_soc_ls_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_soc_lr_qf_done(unsigned int uflush_soc_lr_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_host_ls_qf_done(unsigned int uflush_host_ls_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_host_lr_qf_done(unsigned int uflush_host_lr_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_sq_qf_done(unsigned int uflush_sq_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_rq_qf_done(unsigned int uflush_rq_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_ucode_qf_done(unsigned int uflush_ucode_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_rdma_qf_done(unsigned int uflush_rdma_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_emqcnt_done(unsigned int uflush_emqcnt_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_pt_fifo_done(unsigned int uflush_pt_fifo_done); +int iSetENQC_ECC_1BIT_ERR_CNT_enqc_ecc_1bit_err_cnt(unsigned int uenqc_ecc_1bit_err_cnt); +int iSetENQC_ECC_2BIT_ERR_CNT_enqc_ecc_2bit_err_cnt(unsigned int uenqc_ecc_2bit_err_cnt); +int iSetENQC_RX_DU_PACKET_enqc_rx_du_pkt(unsigned int uenqc_rx_du_pkt); +int iSetENQC_RX_DU_LENGTH_enqc_rx_du_length(unsigned int uenqc_rx_du_length); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_cpi_cnt(unsigned int ucpi_cnt); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_cpi_full(unsigned int ucpi_full); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_cpi_empt(unsigned int ucpi_empt); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_emqenq_fifo_cnt(unsigned int uemqenq_fifo_cnt); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_emqenq_fifo_full(unsigned int uemqenq_fifo_full); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_emqenq_fifo_empt(unsigned int uemqenq_fifo_empt); +int iSetSM_IN_FIFO_STATUS_sm_wfifo_cnt(unsigned int usm_wfifo_cnt); +int iSetSM_IN_FIFO_STATUS_sm_full(unsigned int usm_full); +int iSetSM_IN_FIFO_STATUS_sm_aful(unsigned int usm_aful); +int iSetSM_IN_FIFO_STATUS_sm_empt(unsigned int usm_empt); +int iSetTILE_QU_IN_FIFO_STATUS_tile_wfifo_cnt(unsigned int utile_wfifo_cnt); +int iSetTILE_QU_IN_FIFO_STATUS_tile_full(unsigned int utile_full); +int iSetTILE_QU_IN_FIFO_STATUS_tile_empt(unsigned int utile_empt); +int iSetTILE_QU_IN_FIFO_STATUS_qu_wfifo_cnt(unsigned int uqu_wfifo_cnt); +int iSetTILE_QU_IN_FIFO_STATUS_qu_full(unsigned int uqu_full); +int iSetTILE_QU_IN_FIFO_STATUS_qu_empt(unsigned int uqu_empt); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_cnt(unsigned int umrf_fifo_cnt); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_full(unsigned int umrf_fifo_full); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_empt(unsigned int umrf_fifo_empt); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_aful(unsigned int umrf_fifo_aful); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_cnt(unsigned int udurf_fifo_cnt); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_full(unsigned int udurf_fifo_full); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_empt(unsigned int udurf_fifo_empt); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_aful(unsigned int udurf_fifo_aful); +int iSetENQC_PASSTHRU_FIFO_STATUS_passthru_fifo_cnt(unsigned int upassthru_fifo_cnt); +int iSetENQC_PASSTHRU_FIFO_STATUS_passthru_fifo_dfx(unsigned int upassthru_fifo_dfx); +int iSetENQC_INPUT_BP_mqm_cpi_db_bp(unsigned int umqm_cpi_db_bp); +int iSetENQC_EQM_QD_CNT_enqc_eqm_qd_cnt(unsigned int uenqc_eqm_qd_cnt); +int iSetENQC_RX_CPI_PKT_CNT_enqc_rx_cpi_pkt_cnt(unsigned int uenqc_rx_cpi_pkt_cnt); +int iSetENQC_RX_SM_PKT_CNT_enqc_rx_sm_pkt_cnt(unsigned int uenqc_rx_sm_pkt_cnt); +int iSetENQC_RX_TILE_PKT_CNT_enqc_rx_tile_pkt_cnt(unsigned int uenqc_rx_tile_pkt_cnt); +int iSetENQC_RX_QU_PKT_CNT_enqc_rx_qu_pkt_cnt(unsigned int uenqc_rx_qu_pkt_cnt); +int iSetENQC_DIS_CPI_CNT_enqc_dis_cpi_cnt(unsigned int uenqc_dis_cpi_cnt); +int iSetENQC_RX_RING_ERR_DB_CNT_enqc_rx_ring_err_db_cnt(unsigned int uenqc_rx_ring_err_db_cnt); +int iSetENQC_ENQ_IQM_CNT_enqc_enq_iqm_cnt(unsigned int uenqc_enq_iqm_cnt); +int iSetENQC_ENQ_EQM_CNT_enqc_enq_eqm_cnt(unsigned int uenqc_enq_eqm_cnt); +int iSetENQC_FILTERD_DB_CNT_enqc_filterd_db_cnt(unsigned int uenqc_filterd_db_cnt); +int iSetENQC_RX_SM_CP_SGE_CRDT_enqc_rx_cp_sge_crdt(unsigned int uenqc_rx_cp_sge_crdt); +int iSetENQC_RX_SM_DP_SGE_CRDT_enqc_rx_dp_sge_crdt(unsigned int uenqc_rx_dp_sge_crdt); +int iSetENQC_RX_SM_CP_DATA_CRDT_enqc_rx_cp_data_crdt(unsigned int uenqc_rx_cp_data_crdt); +int iSetENQC_RX_SM_DP_DATA_CRDT_enqc_rx_dp_data_crdt(unsigned int uenqc_rx_dp_data_crdt); +int iSetENQC_RX_DP_NOFL_DB_enqc_rx_dp_nofl_db_cnt(unsigned int uenqc_rx_dp_nofl_db_cnt); +int iSetDB_OVFL_VF_RANGE_CNT_db_ovfl_vf_range_cnt(unsigned int udb_ovfl_vf_range_cnt); +int iSetNONF_DB_NUM_OVFL_THR_CNT_nonf_db_num_ovfl_thr_cnt(unsigned int unonf_db_num_ovfl_thr_cnt); +int iSetMQM_ERR_TYP_DB_CNT_mqm_err_typ_db_cnt(unsigned int umqm_err_typ_db_cnt); +int iSetPASS_THROUGH_STA_passthru_fsm(unsigned int upassthru_fsm); +int iSetPASS_THROUGH_STA_passthru_fifo_status(unsigned int upassthru_fifo_status); +int iSetPASS_THROUGH_STA_iqm_enqc_inner_empt(unsigned int uiqm_enqc_inner_empt); +int iSetPASS_THROUGH_STA_eqm_enqc_outer_empt(unsigned int ueqm_enqc_outer_empt); +int iSetPASS_THROUGH_STA_enqc_passthru_pipe_empt(unsigned int uenqc_passthru_pipe_empt); +int iSetPASS_THROUGH_STA_iqm_enqc_inner_bp(unsigned int uiqm_enqc_inner_bp); +int iSetPASS_THROUGH_STA_qu_mqm_underload(unsigned int uqu_mqm_underload); + +/* Define the union csr_brm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv0_u; + +/* Define the union csr_brm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv1_u; + +/* Define the union csr_brm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv2_u; + +/* Define the union csr_brm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv3_u; + +/* Define the union csr_brm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_addr : 13; /* [12:0] */ + u32 rsv_0 : 11; /* [23:13] */ + u32 brm_indrect_tab : 4; /* [27:24] */ + u32 brm_indrect_status : 2; /* [29:28] */ + u32 brm_indrect_mode : 1; /* [30] */ + u32 brm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_ctrl_u; + +/* Define the union csr_brm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_timeout_u; + +/* Define the union csr_brm_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_data_0_u; + +/* Define the union csr_brm_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_data_1_u; + +/* Define the union csr_brm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 brm_enable : 1; /* [27] */ + u32 brm_int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_int_vector_u; + +/* Define the union csr_brm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_int_data : 4; /* [3:0] */ + u32 rsv_3 : 12; /* [15:4] */ + u32 brm_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_int_u; + +/* Define the union csr_brm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_int_en : 4; /* [3:0] */ + u32 rsv_4 : 12; /* [15:4] */ + u32 brm_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_int_en_u; + +/* Define the union csr_brm_mem_ecc0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc0_err : 1; /* [0] */ + u32 brm_ecc0_err_insert : 1; /* [1] */ + u32 brm_ecc0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ecc0_u; + +/* Define the union csr_brm_mem_ecc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc1_err : 1; /* [0] */ + u32 brm_ecc1_err_insert : 1; /* [1] */ + u32 brm_ecc1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ecc1_u; + +/* Define the union csr_brm_db_flt_addr_ovfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_qf_ovfl_err : 1; /* [0] */ + u32 brm_qf_ovfl_err_insert : 1; /* [1] */ + u32 brm_qf_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_db_flt_addr_ovfl_int_u; + +/* Define the union csr_brm_cnt_addr_ovfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_cnt_ovfl_err : 1; /* [0] */ + u32 brm_cnt_ovfl_err_insert : 1; /* [1] */ + u32 brm_cnt_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_cnt_addr_ovfl_int_u; + +/* Define the union csr_brm_att_cnt_mem_ecc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slc7_err_req : 2; /* [1:0] */ + u32 slc8_err_req : 2; /* [3:2] */ + u32 slc9_err_req : 2; /* [5:4] */ + u32 slc10_err_req : 2; /* [7:6] */ + u32 slc11_err_req : 2; /* [9:8] */ + u32 slc12_err_req : 2; /* [11:10] */ + u32 slc13_err_req : 2; /* [13:12] */ + u32 slc14_err_req : 2; /* [15:14] */ + u32 slc15_err_req : 2; /* [17:16] */ + u32 slc16_err_req : 2; /* [19:18] */ + u32 slc17_err_req : 2; /* [21:20] */ + u32 dwq_err_req : 2; /* [23:22] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_att_cnt_mem_ecc_req_u; + +/* Define the union csr_brm_qf_qd_mem_ecc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slc0_lc_err_req : 2; /* [1:0] */ + u32 slc0_err_req : 2; /* [3:2] */ + u32 slc1_err_req : 2; /* [5:4] */ + u32 slc2_err_req : 2; /* [7:6] */ + u32 slc3_err_req : 2; /* [9:8] */ + u32 slc4_err_req : 2; /* [11:10] */ + u32 slc5_err_req : 2; /* [13:12] */ + u32 slc6_err_req : 2; /* [15:14] */ + u32 slc18_err_req : 2; /* [17:16] */ + u32 slc19_err_req : 2; /* [19:18] */ + u32 rsv_6 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_qf_qd_mem_ecc_req_u; + +/* Define the union csr_brm_que_filt_spa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 que_filt_spa : 3; /* [2:0] */ + u32 rsv_7 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_que_filt_spa_u; + +/* Define the union csr_brm_att_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_att_size : 4; /* [3:0] */ + u32 rsv_8 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_att_size_u; + +/* Define the union csr_brm_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ecc_bypass_en_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_10 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_brm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_ecc_1bit_err_cnt_u; + +/* Define the union csr_brm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_ecc_2bit_err_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_brm_rw_rsv0_u brm_rw_rsv0; /* 0 */ + volatile csr_brm_rw_rsv1_u brm_rw_rsv1; /* 4 */ + volatile csr_brm_rw_rsv2_u brm_rw_rsv2; /* 8 */ + volatile csr_brm_rw_rsv3_u brm_rw_rsv3; /* C */ + volatile csr_brm_indrect_ctrl_u brm_indrect_ctrl; /* 10 */ + volatile csr_brm_indrect_timeout_u brm_indrect_timeout; /* 14 */ + volatile csr_brm_indrect_data_0_u brm_indrect_data_0; /* 18 */ + volatile csr_brm_indrect_data_1_u brm_indrect_data_1; /* 1C */ + volatile csr_brm_int_vector_u brm_int_vector; /* 20 */ + volatile csr_brm_int_u brm_int; /* 24 */ + volatile csr_brm_int_en_u brm_int_en; /* 28 */ + volatile csr_brm_mem_ecc0_u brm_mem_ecc0; /* 2C */ + volatile csr_brm_mem_ecc1_u brm_mem_ecc1; /* 30 */ + volatile csr_brm_db_flt_addr_ovfl_int_u brm_db_flt_addr_ovfl_int; /* 34 */ + volatile csr_brm_cnt_addr_ovfl_int_u brm_cnt_addr_ovfl_int; /* 38 */ + volatile csr_brm_att_cnt_mem_ecc_req_u brm_att_cnt_mem_ecc_req; /* 50 */ + volatile csr_brm_qf_qd_mem_ecc_req_u brm_qf_qd_mem_ecc_req; /* 54 */ + volatile csr_brm_que_filt_spa_u brm_que_filt_spa; /* 80 */ + volatile csr_brm_att_size_u brm_att_size; /* 84 */ + volatile csr_brm_mem_ecc_bypass_en_u brm_mem_ecc_bypass_en; /* 88 */ + volatile csr_brm_mem_ctrl_bus_cfg0_u brm_mem_ctrl_bus_cfg0; /* 8C */ + volatile csr_brm_mem_ctrl_bus_cfg1_u brm_mem_ctrl_bus_cfg1; /* 90 */ + volatile csr_brm_mem_ctrl_bus_cfg2_u brm_mem_ctrl_bus_cfg2; /* 94 */ + volatile csr_brm_mem_ctrl_bus_cfg3_u brm_mem_ctrl_bus_cfg3; /* 98 */ + volatile csr_brm_mem_ctrl_bus_cfg4_u brm_mem_ctrl_bus_cfg4; /* 9C */ + volatile csr_brm_ecc_1bit_err_cnt_u brm_ecc_1bit_err_cnt; /* B0 */ + volatile csr_brm_ecc_2bit_err_cnt_u brm_ecc_2bit_err_cnt; /* B4 */ +} S_mqm_brm_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_brm */ +extern volatile S_mqm_brm_REGS_TYPE *gopmqm_brmAllReg; + +/* Declare the functions that set the member value */ +int iSetBRM_RW_RSV0_brm_rw_rsv0(unsigned int ubrm_rw_rsv0); +int iSetBRM_RW_RSV1_brm_rw_rsv1(unsigned int ubrm_rw_rsv1); +int iSetBRM_RW_RSV2_brm_rw_rsv2(unsigned int ubrm_rw_rsv2); +int iSetBRM_RW_RSV3_brm_rw_rsv3(unsigned int ubrm_rw_rsv3); +int iSetBRM_INDRECT_CTRL_brm_indrect_addr(unsigned int ubrm_indrect_addr); +int iSetBRM_INDRECT_CTRL_brm_indrect_tab(unsigned int ubrm_indrect_tab); +int iSetBRM_INDRECT_CTRL_brm_indrect_status(unsigned int ubrm_indrect_status); +int iSetBRM_INDRECT_CTRL_brm_indrect_mode(unsigned int ubrm_indrect_mode); +int iSetBRM_INDRECT_CTRL_brm_indrect_vld(unsigned int ubrm_indrect_vld); +int iSetBRM_INDRECT_TIMEOUT_brm_indrect_timeout(unsigned int ubrm_indrect_timeout); +int iSetBRM_INDRECT_DATA_0_brm_indrect_data_0(unsigned int ubrm_indrect_data_0); +int iSetBRM_INDRECT_DATA_1_brm_indrect_data_1(unsigned int ubrm_indrect_data_1); +int iSetBRM_INT_VECTOR_brm_cpi_int_index(unsigned int ubrm_cpi_int_index); +int iSetBRM_INT_VECTOR_brm_enable(unsigned int ubrm_enable); +int iSetBRM_INT_VECTOR_brm_int_issue(unsigned int ubrm_int_issue); +int iSetBRM_INT_brm_int_data(unsigned int ubrm_int_data); +int iSetBRM_INT_brm_program_csr_id_ro(unsigned int ubrm_program_csr_id_ro); +int iSetBRM_INT_EN_brm_int_en(unsigned int ubrm_int_en); +int iSetBRM_INT_EN_brm_program_csr_id(unsigned int ubrm_program_csr_id); +int iSetBRM_MEM_ECC0_brm_ecc0_err(unsigned int ubrm_ecc0_err); +int iSetBRM_MEM_ECC0_brm_ecc0_err_insert(unsigned int ubrm_ecc0_err_insert); +int iSetBRM_MEM_ECC0_brm_ecc0_err_info(unsigned int ubrm_ecc0_err_info); +int iSetBRM_MEM_ECC1_brm_ecc1_err(unsigned int ubrm_ecc1_err); +int iSetBRM_MEM_ECC1_brm_ecc1_err_insert(unsigned int ubrm_ecc1_err_insert); +int iSetBRM_MEM_ECC1_brm_ecc1_err_info(unsigned int ubrm_ecc1_err_info); +int iSetBRM_DB_FLT_ADDR_OVFL_INT_brm_qf_ovfl_err(unsigned int ubrm_qf_ovfl_err); +int iSetBRM_DB_FLT_ADDR_OVFL_INT_brm_qf_ovfl_err_insert(unsigned int ubrm_qf_ovfl_err_insert); +int iSetBRM_DB_FLT_ADDR_OVFL_INT_brm_qf_ovfl_err_info(unsigned int ubrm_qf_ovfl_err_info); +int iSetBRM_CNT_ADDR_OVFL_INT_brm_cnt_ovfl_err(unsigned int ubrm_cnt_ovfl_err); +int iSetBRM_CNT_ADDR_OVFL_INT_brm_cnt_ovfl_err_insert(unsigned int ubrm_cnt_ovfl_err_insert); +int iSetBRM_CNT_ADDR_OVFL_INT_brm_cnt_ovfl_err_info(unsigned int ubrm_cnt_ovfl_err_info); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc7_err_req(unsigned int uslc7_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc8_err_req(unsigned int uslc8_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc9_err_req(unsigned int uslc9_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc10_err_req(unsigned int uslc10_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc11_err_req(unsigned int uslc11_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc12_err_req(unsigned int uslc12_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc13_err_req(unsigned int uslc13_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc14_err_req(unsigned int uslc14_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc15_err_req(unsigned int uslc15_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc16_err_req(unsigned int uslc16_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc17_err_req(unsigned int uslc17_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_dwq_err_req(unsigned int udwq_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc0_lc_err_req(unsigned int uslc0_lc_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc0_err_req(unsigned int uslc0_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc1_err_req(unsigned int uslc1_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc2_err_req(unsigned int uslc2_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc3_err_req(unsigned int uslc3_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc4_err_req(unsigned int uslc4_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc5_err_req(unsigned int uslc5_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc6_err_req(unsigned int uslc6_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc18_err_req(unsigned int uslc18_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc19_err_req(unsigned int uslc19_err_req); +int iSetBRM_QUE_FILT_SPA_que_filt_spa(unsigned int uque_filt_spa); +int iSetBRM_ATT_SIZE_brm_att_size(unsigned int ubrm_att_size); +int iSetBRM_MEM_ECC_BYPASS_EN_brm_mem_ecc_bypass(unsigned int ubrm_mem_ecc_bypass); +int iSetBRM_MEM_CTRL_BUS_CFG0_brm_mem_ctrl_bus_0(unsigned int ubrm_mem_ctrl_bus_0); +int iSetBRM_MEM_CTRL_BUS_CFG1_brm_mem_ctrl_bus_1(unsigned int ubrm_mem_ctrl_bus_1); +int iSetBRM_MEM_CTRL_BUS_CFG2_brm_mem_ctrl_bus_2(unsigned int ubrm_mem_ctrl_bus_2); +int iSetBRM_MEM_CTRL_BUS_CFG3_brm_mem_ctrl_bus_3(unsigned int ubrm_mem_ctrl_bus_3); +int iSetBRM_MEM_CTRL_BUS_CFG4_brm_mem_ctrl_bus_4(unsigned int ubrm_mem_ctrl_bus_4); +int iSetBRM_ECC_1BIT_ERR_CNT_brm_ecc_1bit_err_cnt(unsigned int ubrm_ecc_1bit_err_cnt); +int iSetBRM_ECC_2BIT_ERR_CNT_brm_ecc_2bit_err_cnt(unsigned int ubrm_ecc_2bit_err_cnt); + +/* Define the union csr_iqm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv0_u; + +/* Define the union csr_iqm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv1_u; + +/* Define the union csr_iqm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv2_u; + +/* Define the union csr_iqm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv3_u; + +/* Define the union csr_iqm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 iqm_indrect_tab : 4; /* [27:24] */ + u32 iqm_indrect_status : 2; /* [29:28] */ + u32 iqm_indrect_mode : 1; /* [30] */ + u32 iqm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_ctrl_u; + +/* Define the union csr_iqm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_timeout_u; + +/* Define the union csr_iqm_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_data_0_u; + +/* Define the union csr_iqm_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_data_1_u; + +/* Define the union csr_iqm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 iqm_enable : 1; /* [27] */ + u32 iqm_int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_int_vector_u; + +/* Define the union csr_iqm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_int_data : 9; /* [8:0] */ + u32 rsv_3 : 7; /* [15:9] */ + u32 iqm_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_int_u; + +/* Define the union csr_iqm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_int_en : 9; /* [8:0] */ + u32 rsv_4 : 7; /* [15:9] */ + u32 iqm_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_int_en_u; + +/* Define the union csr_iqm_mem_ecc0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc0_err : 1; /* [0] */ + u32 iqm_ecc0_err_insert : 1; /* [1] */ + u32 iqm_ecc0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc0_u; + +/* Define the union csr_iqm_mem_ecc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc1_err : 1; /* [0] */ + u32 iqm_ecc1_err_insert : 1; /* [1] */ + u32 iqm_ecc1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc1_u; + +/* Define the union csr_iqm_aging_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_int_err : 1; /* [0] */ + u32 iqm_aging_int_err_insert : 1; /* [1] */ + u32 iqm_aging_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_int_u; + +/* Define the union csr_iqm_cmq_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_deq_empty_err : 1; /* [0] */ + u32 iqm_cmq_deq_empty_err_insert : 1; /* [1] */ + u32 iqm_cmq_deq_empty_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_deq_empty_int_u; + +/* Define the union csr_iqm_fifo_wr_ovfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_fifo_wr_ovfl_err : 1; /* [0] */ + u32 iqm_fifo_wr_ovfl_err_insert : 1; /* [1] */ + u32 iqm_fifo_wr_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_wr_ovfl_int_u; + +/* Define the union csr_iqm_fifo_rd_udfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_fifo_rd_udfl_err : 1; /* [0] */ + u32 iqm_fifo_rd_udfl_err_insert : 1; /* [1] */ + u32 iqm_fifo_rd_udfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_rd_udfl_int_u; + +/* Define the union csr_iqm_free_rsc_bmp_overflow_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_free_rsc_bmp_ovfl_err : 1; /* [0] */ + u32 iqm_free_rsc_bmp_ovfl_err_insert : 1; /* [1] */ + u32 iqm_free_rsc_bmp_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_free_rsc_bmp_overflow_int_u; + +/* Define the union csr_iqm_cll_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmqnfmq_deq_empty_err : 1; /* [0] */ + u32 iqm_nmqnfmq_deq_empty_err_insert : 1; /* [1] */ + u32 iqm_nmqnfmq_deq_empty_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cll_deq_empty_int_u; + +/* Define the union csr_iqm_uxmq_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_uxmq_deq_empty_err : 1; /* [0] */ + u32 iqm_uxmq_deq_empty_err_insert : 1; /* [1] */ + u32 iqm_uxmq_deq_empty_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uxmq_deq_empty_int_u; + +/* Define the union csr_iqm_fifo_int_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_shallow_fifo_rd_udfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req1_u; + +/* Define the union csr_iqm_fifo_int_req2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_rd_udfl_insert2 : 8; /* [7:0] */ + u32 sm_shallow_fifo_rd_udfl_insert1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req2_u; + +/* Define the union csr_iqm_fifo_int_req3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_rd_udfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req3_u; + +/* Define the union csr_iqm_fifo_int_req4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_rd_udfl_insert1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req4_u; + +/* Define the union csr_iqm_mem_ecc_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cll_head_mem_err_req : 2; /* [1:0] */ + u32 cll_tail_mem_err_req : 2; /* [3:2] */ + u32 cll_mqle_mem_err_req : 2; /* [5:4] */ + u32 cll_ckll_mem_err_req : 2; /* [7:6] */ + u32 mq2vf_mem_err_req : 2; /* [9:8] */ + u32 cll_faptab_mem_err_req : 2; /* [11:10] */ + u32 pre_enq_qlen_mem_err_req : 2; /* [13:12] */ + u32 que_pro_map_mem_err_req : 2; /* [15:14] */ + u32 pre_enq_hec_len_mem_err_req : 2; /* [17:16] */ + u32 cmq_ll_head_mem_err_req : 2; /* [19:18] */ + u32 cmq_ll_tail_mem_err_req : 2; /* [21:20] */ + u32 cmq_queue_len_mem_err_req : 2; /* [23:22] */ + u32 cmq_ll_mem_err_req : 2; /* [25:24] */ + u32 cmq_hec_len_mem_err_req : 2; /* [27:26] */ + u32 ill_soc_ll_err_req : 2; /* [29:28] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc_req0_u; + +/* Define the union csr_iqm_mem_ecc_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_qd_err_req : 2; /* [1:0] */ + u32 deq_sm_fifo_mem_err_req : 2; /* [3:2] */ + u32 deq_qu_fifo_mem_err_req : 2; /* [5:4] */ + u32 iqm_agcnt_err_req : 2; /* [7:6] */ + u32 iqm_agvld_err_req : 2; /* [9:8] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc_req1_u; + +/* Define the union csr_iqm_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cll_rsc_overflow_uncrt_int_en : 1; /* [0] */ + u32 cll_deq_empty_uncrt_int_en : 1; /* [1] */ + u32 cmq_deq_empty_uncrt_int_en : 1; /* [2] */ + u32 uxmq_deq_empty_uncrt_int_en : 1; /* [3] */ + u32 rsv_7 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uncrt_int_en_u; + +/* Define the union csr_iqm_fifo_int_req5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_shallow_fifo_wr_ovfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req5_u; + +/* Define the union csr_iqm_fifo_int_req6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_wr_ovfl_insert2 : 8; /* [7:0] */ + u32 sm_shallow_fifo_wr_ovfl_insert1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req6_u; + +/* Define the union csr_iqm_fifo_int_req7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_wr_ovfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req7_u; + +/* Define the union csr_iqm_fifo_int_req8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_wr_ovfl_insert1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req8_u; + +/* Define the union csr_iqm_fifo_int_req9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_fifo_wr_ovfl_insert : 1; /* [0] */ + u32 enqc_enq_fifo_rd_udfl_insert : 1; /* [1] */ + u32 eqm_enq_fifo_wr_ovfl_insert : 1; /* [2] */ + u32 eqm_enq_fifo_rd_udfl_insert : 1; /* [3] */ + u32 deqc_enq_fifo_wr_ovfl_insert : 1; /* [4] */ + u32 deqc_enq_fifo_rd_udfl_insert : 1; /* [5] */ + u32 enqc_enq_soc_fifo_wr_ovfl_insert : 1; /* [6] */ + u32 enqc_enq_soc_fifo_rd_udfl_insert : 1; /* [7] */ + u32 sm_dp_out_fifo_wr_ovfl_insert : 1; /* [8] */ + u32 sm_dp_out_fifo_rd_udfl_insert : 1; /* [9] */ + u32 sm_cp_out_fifo_wr_ovfl_insert : 1; /* [10] */ + u32 sm_cp_out_fifo_rd_udfl_insert : 1; /* [11] */ + u32 cpi_ep_sge_fifo_wr_ovfl_insert : 1; /* [12] */ + u32 cpi_ep_sge_fifo_rd_udfl_insert : 1; /* [13] */ + u32 cpi_host_sge_fifo_wr_ovfl_insert : 1; /* [14] */ + u32 cpi_host_sge_fifo_rd_udfl_insert : 1; /* [15] */ + u32 cpi_data_fifo_wr_ovfl_insert : 1; /* [16] */ + u32 cpi_data_fifo_rd_udfl_insert : 1; /* [17] */ + u32 sm_data_fifo_wr_ovfl_insert : 1; /* [18] */ + u32 sm_data_fifo_rd_udfl_insert : 1; /* [19] */ + u32 sm_sge_fifo_wr_ovfl_insert : 1; /* [20] */ + u32 sm_sge_fifo_rd_udfl_insert : 1; /* [21] */ + u32 qu_ep_fifo_wr_ovfl_insert : 1; /* [22] */ + u32 qu_ep_fifo_rd_udfl_insert : 1; /* [23] */ + u32 rsv_8 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req9_u; + +/* Define the union csr_iqm_chunk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chunk_size : 2; /* [1:0] */ + u32 rsv_9 : 2; /* [3:2] */ + u32 icll_bitmap_critical_depth : 11; /* [14:4] */ + u32 rsv_10 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_chunk_u; + +/* Define the union csr_iqm_out_fifo_th_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_deq_sm_ctrl_plane_aful_gap : 4; /* [3:0] */ + u32 rsv_11 : 4; /* [7:4] */ + u32 iqm_deq_sm_data_plane_aful_gap : 4; /* [11:8] */ + u32 rsv_12 : 4; /* [15:12] */ + u32 iqm_qu_shallow_fifo_gap : 4; /* [19:16] */ + u32 rsv_13 : 4; /* [23:20] */ + u32 iqm_sm_shallow_fifo_gap : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_out_fifo_th_gap_u; + +/* Define the union csr_iqm_enq_fifo_aful_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_fifo_afull_gap : 2; /* [1:0] */ + u32 rsv_15 : 2; /* [3:2] */ + u32 eqm_enq_fifo_afull_gap : 3; /* [6:4] */ + u32 rsv_16 : 1; /* [7] */ + u32 deqc_enq_fifo_afull_gap : 3; /* [10:8] */ + u32 rsv_17 : 1; /* [11] */ + u32 enqc_enq_soc_fifo_afull_gap : 2; /* [13:12] */ + u32 rsv_18 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_enq_fifo_aful_gap_u; + +/* Define the union csr_iqm_crdt_comp_fifo_gap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_data_aful_gap : 3; /* [2:0] */ + u32 rsv_19 : 1; /* [3] */ + u32 sm_sge_aful_gap : 3; /* [6:4] */ + u32 rsv_20 : 1; /* [7] */ + u32 cpi_data_aful_gap : 6; /* [13:8] */ + u32 rsv_21 : 2; /* [15:14] */ + u32 cpi_host_sge_aful_gap : 6; /* [21:16] */ + u32 rsv_22 : 2; /* [23:22] */ + u32 cpi_ep_sge_aful_gap : 6; /* [29:24] */ + u32 rsv_23 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_crdt_comp_fifo_gap_cfg_u; + +/* Define the union csr_iqm_aging_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_aging_en : 1; /* [0] */ + u32 rsv_24 : 3; /* [3:1] */ + u32 nfmq_aging_en : 1; /* [4] */ + u32 rsv_25 : 3; /* [7:5] */ + u32 aging_intval : 16; /* [23:8] */ + u32 aging_dest : 1; /* [24] */ + u32 rsv_26 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_cfg_u; + +/* Define the union csr_iqm_des_que_deq_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_que_deq_mqid : 13; /* [12:0] */ + u32 rsv_27 : 3; /* [15:13] */ + u32 des_que_deq_qa : 1; /* [16] */ + u32 des_que_deq_src : 1; /* [17] */ + u32 rsv_28 : 2; /* [19:18] */ + u32 des_que_deq_hid : 2; /* [21:20] */ + u32 rsv_29 : 2; /* [23:22] */ + u32 des_que_deq_cos : 3; /* [26:24] */ + u32 rsv_30 : 1; /* [27] */ + u32 des_que_deq_ep : 3; /* [30:28] */ + u32 rsv_31 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_des_que_deq_cfg0_u; + +/* Define the union csr_iqm_des_que_deq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_des_que_deq_vld : 1; /* [0] */ + u32 rsv_32 : 3; /* [3:1] */ + u32 des_que_deq_vfid : 13; /* [16:4] */ + u32 rsv_33 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_des_que_deq_cfg1_u; + +/* Define the union csr_iqm_root_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_total_fl_static_th : 16; /* [15:0] */ + u32 root_total_sl_static_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_root_thr_cfg_u; + +/* Define the union csr_iqm_root_hthr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_hth_parm_nmq : 6; /* [5:0] */ + u32 rsv_34 : 2; /* [7:6] */ + u32 root_hth_parm_nfmq : 6; /* [13:8] */ + u32 rsv_35 : 2; /* [15:14] */ + u32 root_total_hth_parm : 6; /* [21:16] */ + u32 rsv_36 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_root_hthr_cfg_u; + +/* Define the union csr_iqm_nmq_root_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_fl_static_th_nmq : 16; /* [15:0] */ + u32 root_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_root_thr_cfg_u; + +/* Define the union csr_iqm_nfmq_root_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_fl_static_th_nfmq : 16; /* [15:0] */ + u32 root_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_root_thr_cfg_u; + +/* Define the union csr_iqm_nmq_host0_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid0_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host0_th_u; + +/* Define the union csr_iqm_nmq_host1_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid1_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid1_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host1_th_u; + +/* Define the union csr_iqm_nmq_host2_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid2_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid2_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host2_th_u; + +/* Define the union csr_iqm_nmq_host3_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid3_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid3_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host3_th_u; + +/* Define the union csr_iqm_nmq_host_hth_pa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_hth_parm_nmq : 6; /* [5:0] */ + u32 rsv_37 : 2; /* [7:6] */ + u32 hid1_hth_parm_nmq : 6; /* [13:8] */ + u32 rsv_38 : 2; /* [15:14] */ + u32 hid2_hth_parm_nmq : 6; /* [21:16] */ + u32 rsv_39 : 2; /* [23:22] */ + u32 hid3_hth_parm_nmq : 6; /* [29:24] */ + u32 rsv_40 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host_hth_pa_u; + +/* Define the union csr_iqm_nfmq_host0_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid0_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host0_th_u; + +/* Define the union csr_iqm_nfmq_host1_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid1_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid1_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host1_th_u; + +/* Define the union csr_iqm_nfmq_host2_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid2_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid2_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host2_th_u; + +/* Define the union csr_iqm_nfmq_host3_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid3_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid3_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host3_th_u; + +/* Define the union csr_iqm_nfmq_host_hth_pa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_hth_parm_nfmq : 6; /* [5:0] */ + u32 rsv_41 : 2; /* [7:6] */ + u32 hid1_hth_parm_nfmq : 6; /* [13:8] */ + u32 rsv_42 : 2; /* [15:14] */ + u32 hid2_hth_parm_nfmq : 6; /* [21:16] */ + u32 rsv_43 : 2; /* [23:22] */ + u32 hid3_hth_parm_nfmq : 6; /* [29:24] */ + u32 rsv_44 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host_hth_pa_u; + +/* Define the union csr_iqm_nmq_hex_pro_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_pro_map_nmq_0 : 4; /* [3:0] */ + u32 he_pro_map_nmq_1 : 4; /* [7:4] */ + u32 he_pro_map_nmq_2 : 4; /* [11:8] */ + u32 he_pro_map_nmq_3 : 4; /* [15:12] */ + u32 he_pro_map_nmq_4 : 4; /* [19:16] */ + u32 he_pro_map_nmq_5 : 4; /* [23:20] */ + u32 he_pro_map_nmq_6 : 4; /* [27:24] */ + u32 he_pro_map_nmq_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_hex_pro_map_u; + +/* Define the union csr_iqm_nfmq_hex_pro_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_pro_map_nfmq_0 : 4; /* [3:0] */ + u32 he_pro_map_nfmq_1 : 4; /* [7:4] */ + u32 he_pro_map_nfmq_2 : 4; /* [11:8] */ + u32 he_pro_map_nfmq_3 : 4; /* [15:12] */ + u32 he_pro_map_nfmq_4 : 4; /* [19:16] */ + u32 he_pro_map_nfmq_5 : 4; /* [23:20] */ + u32 he_pro_map_nfmq_6 : 4; /* [27:24] */ + u32 he_pro_map_nfmq_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_hex_pro_map_u; + +/* Define the union csr_iqm_he_th_pro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_fl_static_th_pro : 16; /* [15:0] */ + u32 he_sl_static_th_pro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_he_th_pro_u; + +/* Define the union csr_iqm_he_fac_pro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_ep_fl_a_fact_pro : 7; /* [6:0] */ + u32 rsv_45 : 1; /* [7] */ + u32 host_ep_sl_a_fact_pro : 7; /* [14:8] */ + u32 rsv_46 : 1; /* [15] */ + u32 host_ep_hth_parm_pro : 6; /* [21:16] */ + u32 rsv_47 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_he_fac_pro_u; + +/* Define the union csr_iqm_qtss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qtsc_fl : 16; /* [15:0] */ + u32 qtsc_sl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qtss_cfg_u; + +/* Define the union csr_iqm_hetss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_tsc_fl : 16; /* [15:0] */ + u32 he_tsc_sl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_hetss_cfg_u; + +/* Define the union csr_iqm_hectss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hec_tsc_fl : 16; /* [15:0] */ + u32 hec_tsc_sl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_hectss_cfg_u; + +/* Define the union csr_iqm_sm_host_credit_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_host_credit_data_th : 10; /* [9:0] */ + u32 rsv_48 : 6; /* [15:10] */ + u32 iqm_sm_host_credit_sge_th : 10; /* [25:16] */ + u32 rsv_49 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_host_credit_th_u; + +/* Define the union csr_iqm_sm_credit_tss_cfg_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_cp_credit_tss_data : 10; /* [9:0] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 iqm_sm_ep_dp_credit_tss_data : 10; /* [25:16] */ + u32 rsv_51 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_credit_tss_cfg_data_u; + +/* Define the union csr_iqm_sm_credit_tss_cfg_sge_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_cp_credit_tss_sge : 10; /* [9:0] */ + u32 rsv_52 : 6; /* [15:10] */ + u32 iqm_sm_ep_dp_credit_tss_sge : 10; /* [25:16] */ + u32 rsv_53 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_credit_tss_cfg_sge_u; + +/* Define the union csr_iqm_qu_credit_tss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_cp_credit_tss : 10; /* [9:0] */ + u32 rsv_54 : 6; /* [15:10] */ + u32 iqm_qu_ep_dp_credit_tss : 10; /* [25:16] */ + u32 rsv_55 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_credit_tss_cfg_u; + +/* Define the union csr_iqm_crr_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_dp_crr_wgt : 3; /* [2:0] */ + u32 rsv_56 : 5; /* [7:3] */ + u32 iqm_sm_cp_crr_wgt : 3; /* [10:8] */ + u32 rsv_57 : 5; /* [15:11] */ + u32 iqm_qu_dp_crr_wgt : 3; /* [18:16] */ + u32 rsv_58 : 5; /* [23:19] */ + u32 iqm_qu_cp_crr_wgt : 3; /* [26:24] */ + u32 rsv_59 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_crr_wgt_cfg_u; + +/* Define the union csr_iqm_db_merger_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_db_merger_en : 1; /* [0] */ + u32 rsv_60 : 3; /* [3:1] */ + u32 iqm_db_merger_num : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 iqm_db_merger_num_sum : 7; /* [14:8] */ + u32 rsv_62 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_db_merger_cfg_u; + +/* Define the union csr_smf_dst_hash_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_pg_cfg : 4; /* [3:0] */ + u32 rsv_63 : 12; /* [15:4] */ + u32 lbf_mode_sel_cfg : 2; /* [17:16] */ + u32 rsv_64 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_dst_hash_cfg_u; + +/* Define the union csr_iqm_aging_clr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mq_ag_clr_mqid : 13; /* [12:0] */ + u32 rsv_65 : 3; /* [15:13] */ + u32 mq_ag_clr_qa : 1; /* [16] */ + u32 rsv_66 : 7; /* [23:17] */ + u32 mq_ag_clr_vld : 1; /* [24] */ + u32 rsv_67 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_clr_cfg_u; + +/* Define the union csr_iqm_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_68 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc_bypass_en_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_69 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_iqm_sm_shallow_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_shallow_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_shallow_fifo_status_u; + +/* Define the union csr_iqm_qu_shallow_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_shallow_fifo_status_u; + +/* Define the union csr_iqm_cmq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_root_cnt : 15; /* [14:0] */ + u32 rsv_70 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_cnt_u; + +/* Define the union csr_iqm_cmq_host_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_host0_cnt : 15; /* [14:0] */ + u32 rsv_71 : 1; /* [15] */ + u32 iqm_cmq_host1_cnt : 15; /* [30:16] */ + u32 rsv_72 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_host_cnt0_u; + +/* Define the union csr_iqm_cmq_host_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_host2_cnt : 15; /* [14:0] */ + u32 rsv_73 : 1; /* [15] */ + u32 iqm_cmq_host3_cnt : 15; /* [30:16] */ + u32 rsv_74 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_host_cnt1_u; + +/* Define the union csr_iqm_cmq_hostepx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_hostep_cnt : 15; /* [14:0] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_hostepx_cnt_u; + +/* Define the union csr_iqm_rootx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rootx_cnt_u; + +/* Define the union csr_iqm_nmq_hostx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_host0_cnt : 16; /* [15:0] */ + u32 iqm_nmq_host1_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_hostx_cnt0_u; + +/* Define the union csr_iqm_nmq_hostx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_host2_cnt : 16; /* [15:0] */ + u32 iqm_nmq_host3_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_hostx_cnt1_u; + +/* Define the union csr_iqm_nfmq_hostx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nfmq_host0_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_host1_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_hostx_cnt0_u; + +/* Define the union csr_iqm_nfmq_hostx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nfmq_host2_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_host3_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_hostx_cnt1_u; + +/* Define the union csr_iqm_mq_hex_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_he_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_he_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mq_hex_cnt_u; + +/* Define the union csr_iqm_ucmq_root_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ucmq_root_cnt : 11; /* [10:0] */ + u32 rsv_76 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ucmq_root_cnt_u; + +/* Define the union csr_iqm_unmq_root_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmq_root_cnt : 9; /* [8:0] */ + u32 rsv_77 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_unmq_root_cnt_u; + +/* Define the union csr_iqm_uxmq_ep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 unmq_qlen_ep : 9; /* [8:0] */ + u32 rsv_78 : 3; /* [11:9] */ + u32 ucmq_qlen_ep : 11; /* [22:12] */ + u32 rsv_79 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uxmq_ep_cnt_u; + +/* Define the union csr_iqm_uxmq_queue_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmqid_cnt : 11; /* [10:0] */ + u32 rsv_80 : 5; /* [15:11] */ + u32 iqm_ucmqid_cnt : 11; /* [26:16] */ + u32 rsv_81 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uxmq_queue_cnt_u; + +/* Define the union csr_eqm_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_enq_fifo_cnt : 4; /* [3:0] */ + u32 rsv_82 : 12; /* [15:4] */ + u32 eqm_enq_fifo_full : 1; /* [16] */ + u32 rsv_83 : 3; /* [19:17] */ + u32 eqm_enq_fifo_aful : 1; /* [20] */ + u32 rsv_84 : 3; /* [23:21] */ + u32 eqm_enq_fifo_empt : 1; /* [24] */ + u32 rsv_85 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_enq_fifo_status_u; + +/* Define the union csr_deqc_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_enq_fifo_cnt : 4; /* [3:0] */ + u32 rsv_86 : 4; /* [7:4] */ + u32 deqc_enq_fifo_full : 1; /* [8] */ + u32 rsv_87 : 3; /* [11:9] */ + u32 deqc_enq_fifo_empt : 1; /* [12] */ + u32 rsv_88 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_enq_fifo_status_u; + +/* Define the union csr_iqm_enqc_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_fifo_cnt : 3; /* [2:0] */ + u32 rsv_89 : 5; /* [7:3] */ + u32 enqc_enq_fifo_full : 1; /* [8] */ + u32 rsv_90 : 3; /* [11:9] */ + u32 enqc_enq_fifo_empt : 1; /* [12] */ + u32 rsv_91 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_enqc_enq_fifo_status_u; + +/* Define the union csr_iqm_enqc_soc_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_soc_enq_fifo_cnt : 3; /* [2:0] */ + u32 rsv_92 : 5; /* [7:3] */ + u32 enqc_soc_enq_fifo_full : 1; /* [8] */ + u32 rsv_93 : 3; /* [11:9] */ + u32 enqc_soc_enq_fifo_empt : 1; /* [12] */ + u32 rsv_94 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_enqc_soc_enq_fifo_status_u; + +/* Define the union csr_iqm_cpi_sge_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_host_sge_fifo_cnt : 7; /* [6:0] */ + u32 rsv_95 : 1; /* [7] */ + u32 cpi_host_sge_empt : 1; /* [8] */ + u32 cpi_host_sge_full : 1; /* [9] */ + u32 rsv_96 : 2; /* [11:10] */ + u32 cpi_ep_sge_fifo_cnt : 7; /* [18:12] */ + u32 rsv_97 : 1; /* [19] */ + u32 cpi_ep_sge_empt : 1; /* [20] */ + u32 cpi_ep_sge_full : 1; /* [21] */ + u32 rsv_98 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cpi_sge_crdt_comp_fifo_status_u; + +/* Define the union csr_iqm_cpi_data_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_data_fifo_cnt : 7; /* [6:0] */ + u32 rsv_99 : 1; /* [7] */ + u32 cpi_data_empt : 1; /* [8] */ + u32 cpi_data_full : 1; /* [9] */ + u32 rsv_100 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cpi_data_crdt_comp_fifo_status_u; + +/* Define the union csr_iqm_sm_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_data_fifo_cnt : 4; /* [3:0] */ + u32 rsv_101 : 4; /* [7:4] */ + u32 sm_data_empt : 1; /* [8] */ + u32 sm_data_full : 1; /* [9] */ + u32 rsv_102 : 2; /* [11:10] */ + u32 sm_sge_fifo_cnt : 4; /* [15:12] */ + u32 rsv_103 : 4; /* [19:16] */ + u32 sm_sge_empt : 1; /* [20] */ + u32 sm_sge_full : 1; /* [21] */ + u32 rsv_104 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_crdt_comp_fifo_status_u; + +/* Define the union csr_iqm_sm_out_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_out_fifo_cnt : 5; /* [4:0] */ + u32 rsv_105 : 3; /* [7:5] */ + u32 sm_cp_out_fifo_empt : 1; /* [8] */ + u32 sm_cp_out_fifo_full : 1; /* [9] */ + u32 rsv_106 : 2; /* [11:10] */ + u32 sm_dp_out_fifo_cnt : 5; /* [16:12] */ + u32 rsv_107 : 3; /* [19:17] */ + u32 sm_dp_out_fifo_empt : 1; /* [20] */ + u32 sm_dp_out_fifo_full : 1; /* [21] */ + u32 rsv_108 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_out_fifo_status_u; + +/* Define the union csr_iqm_qu_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_ep_crdt_fifo_cnt : 4; /* [3:0] */ + u32 rsv_109 : 4; /* [7:4] */ + u32 qu_ep_crdt_fifo_empt : 1; /* [8] */ + u32 qu_ep_crdt_fifo_full : 1; /* [9] */ + u32 rsv_110 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_crdt_comp_fifo_status_u; + +/* Define the union csr_icll_free_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icll_free_rsc_cnt : 16; /* [15:0] */ + u32 rsv_111 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icll_free_cnt_u; + +/* Define the union csr_iqm_sm_total_cam_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_total_thread_cnt : 7; /* [6:0] */ + u32 rsv_112 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_total_cam_cnt_u; + +/* Define the union csr_iqm_sm_host_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_host_sge_crdt_bp : 5; /* [4:0] */ + u32 rsv_113 : 3; /* [7:5] */ + u32 iqm_sm_host_dat_crdt_bp : 5; /* [12:8] */ + u32 rsv_114 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_host_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_rr_sge_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_rr_sge_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_rr_sge_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_rr_dat_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_rr_dat_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_rr_dat_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_sge_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_sge_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_sge_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_dat_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_data_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_dat_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_cp_rr_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_cp_rr_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_host_cp_rr_dat_crdt_bp : 8; /* [15:8] */ + u32 rsv_115 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_cp_rr_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_soc_rr_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_soc_dp_rr_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_soc_cp_rr_sge_crdt_bp : 8; /* [15:8] */ + u32 iqm_sm_ep_soc_dp_rr_dat_crdt_bp : 8; /* [23:16] */ + u32 iqm_sm_ep_soc_cp_rr_dat_crdt_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_soc_rr_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_cp_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_cp_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_host_cp_dat_crdt_bp : 8; /* [15:8] */ + u32 rsv_116 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_cp_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_soc_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_soc_dp_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_soc_cp_sge_crdt_bp : 8; /* [15:8] */ + u32 iqm_sm_ep_soc_dp_dat_crdt_bp : 8; /* [23:16] */ + u32 iqm_sm_ep_soc_cp_dat_crdt_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_soc_crdt_bp_u; + +/* Define the union csr_iqm_qu_ep_dp_crdt_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_crdt_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_crdt_bp0_u; + +/* Define the union csr_iqm_qu_ep_dp_crdt_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_crdt_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_crdt_bp1_u; + +/* Define the union csr_iqm_qu_ep_cp_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_cp_crdt_bp : 8; /* [7:0] */ + u32 rsv_117 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_cp_crdt_bp_u; + +/* Define the union csr_iqm_qu_ep_dp_rr_crdt_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_rr_crdt_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_rr_crdt_bp0_u; + +/* Define the union csr_iqm_qu_ep_dp_rr_crdt_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_rr_crdt_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_rr_crdt_bp1_u; + +/* Define the union csr_iqm_qu_ep_cp_rr_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_cp_rr_crdt_bp : 8; /* [7:0] */ + u32 rsv_118 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_cp_rr_crdt_bp_u; + +/* Define the union csr_iqm_flush_icll_cam_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_nmq_cll_flush_done : 1; /* [0] */ + u32 host_nfmq_cll_flush_done : 1; /* [1] */ + u32 host_cmq_ll_flush_done : 1; /* [2] */ + u32 soc_mq_ll_flush_done : 1; /* [3] */ + u32 sm_cam_flush_done : 1; /* [4] */ + u32 iqm_qu_sl_fifo_flush_done : 1; /* [5] */ + u32 iqm_sm_sl_fifo_flush_done : 1; /* [6] */ + u32 iqm_sm_cp_crr_fifo_flush_done : 1; /* [7] */ + u32 iqm_sm_dp_crr_fifo_flush_done : 1; /* [8] */ + u32 rsv_119 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_flush_icll_cam_done_u; + +/* Define the union csr_iqm_aging_nmq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_nmq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_nmq_cnt_u; + +/* Define the union csr_iqm_aging_nfmq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_nfmq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_nfmq_cnt_u; + +/* Define the union csr_iqm_aging_discard_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_discard_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_discard_cnt_u; + +/* Define the union csr_iqm_to_eqm_qd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_to_eqm_qd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_to_eqm_qd_cnt_u; + +/* Define the union csr_iqm_deq_sm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_deq_to_sm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_deq_sm_cnt_u; + +/* Define the union csr_iqm_deq_qu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_deq_to_qu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_deq_qu_cnt_u; + +/* Define the union csr_msc_iqm_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_iqm_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_iqm_deq_cnt_u; + +/* Define the union csr_iqm_nmqnfmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmqnfmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmqnfmq_enq_cnt_u; + +/* Define the union csr_iqm_nmqnfmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmqnfmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmqnfmq_deq_cnt_u; + +/* Define the union csr_iqm_cmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_enq_cnt_u; + +/* Define the union csr_iqm_cmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_deq_cnt_u; + +/* Define the union csr_soc_msc_iqm_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_msc_iqm_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_msc_iqm_deq_cnt_u; + +/* Define the union csr_iqm_unmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_unmq_enq_cnt_u; + +/* Define the union csr_iqm_unmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_unmq_deq_cnt_u; + +/* Define the union csr_iqm_ucmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ucmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ucmq_enq_cnt_u; + +/* Define the union csr_iqm_ucmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ucmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ucmq_deq_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_host_sge_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_host_sge_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_host_sge_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_host_dat_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_host_dat_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_host_dat_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_dp_sge_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_cp_sge_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_dp_dat_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_cp_dat_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt_u; + +/* Define the union csr_iqm_rx_qu_comp_ep_dp_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_qu_ep_dp_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_qu_comp_ep_dp_crdt_cnt_u; + +/* Define the union csr_iqm_rx_qu_comp_ep_cp_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_qu_ep_cp_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_qu_comp_ep_cp_crdt_cnt_u; + +/* Define the union csr_iqm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ecc_1bit_err_cnt_u; + +/* Define the union csr_iqm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ecc_2bit_err_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_iqm_rw_rsv0_u iqm_rw_rsv0; /* 0 */ + volatile csr_iqm_rw_rsv1_u iqm_rw_rsv1; /* 4 */ + volatile csr_iqm_rw_rsv2_u iqm_rw_rsv2; /* 8 */ + volatile csr_iqm_rw_rsv3_u iqm_rw_rsv3; /* C */ + volatile csr_iqm_indrect_ctrl_u iqm_indrect_ctrl; /* 10 */ + volatile csr_iqm_indrect_timeout_u iqm_indrect_timeout; /* 14 */ + volatile csr_iqm_indrect_data_0_u iqm_indrect_data_0; /* 18 */ + volatile csr_iqm_indrect_data_1_u iqm_indrect_data_1; /* 1C */ + volatile csr_iqm_int_vector_u iqm_int_vector; /* 20 */ + volatile csr_iqm_int_u iqm_int; /* 24 */ + volatile csr_iqm_int_en_u iqm_int_en; /* 28 */ + volatile csr_iqm_mem_ecc0_u iqm_mem_ecc0; /* 2C */ + volatile csr_iqm_mem_ecc1_u iqm_mem_ecc1; /* 30 */ + volatile csr_iqm_aging_int_u iqm_aging_int; /* 34 */ + volatile csr_iqm_cmq_deq_empty_int_u iqm_cmq_deq_empty_int; /* 38 */ + volatile csr_iqm_fifo_wr_ovfl_int_u iqm_fifo_wr_ovfl_int; /* 3C */ + volatile csr_iqm_fifo_rd_udfl_int_u iqm_fifo_rd_udfl_int; /* 40 */ + volatile csr_iqm_free_rsc_bmp_overflow_int_u iqm_free_rsc_bmp_overflow_int; /* 44 */ + volatile csr_iqm_cll_deq_empty_int_u iqm_cll_deq_empty_int; /* 48 */ + volatile csr_iqm_uxmq_deq_empty_int_u iqm_uxmq_deq_empty_int; /* 4C */ + volatile csr_iqm_fifo_int_req1_u iqm_fifo_int_req1; /* 50 */ + volatile csr_iqm_fifo_int_req2_u iqm_fifo_int_req2; /* 54 */ + volatile csr_iqm_fifo_int_req3_u iqm_fifo_int_req3; /* 58 */ + volatile csr_iqm_fifo_int_req4_u iqm_fifo_int_req4; /* 5C */ + volatile csr_iqm_mem_ecc_req0_u iqm_mem_ecc_req0; /* 60 */ + volatile csr_iqm_mem_ecc_req1_u iqm_mem_ecc_req1; /* 64 */ + volatile csr_iqm_uncrt_int_en_u iqm_uncrt_int_en; /* 68 */ + volatile csr_iqm_fifo_int_req5_u iqm_fifo_int_req5; /* 6C */ + volatile csr_iqm_fifo_int_req6_u iqm_fifo_int_req6; /* 70 */ + volatile csr_iqm_fifo_int_req7_u iqm_fifo_int_req7; /* 74 */ + volatile csr_iqm_fifo_int_req8_u iqm_fifo_int_req8; /* 78 */ + volatile csr_iqm_fifo_int_req9_u iqm_fifo_int_req9; /* 7C */ + volatile csr_iqm_chunk_u iqm_chunk; /* 80 */ + volatile csr_iqm_out_fifo_th_gap_u iqm_out_fifo_th_gap; /* 84 */ + volatile csr_iqm_enq_fifo_aful_gap_u iqm_enq_fifo_aful_gap; /* 88 */ + volatile csr_iqm_crdt_comp_fifo_gap_cfg_u iqm_crdt_comp_fifo_gap_cfg; /* 8C */ + volatile csr_iqm_aging_cfg_u iqm_aging_cfg; /* 90 */ + volatile csr_iqm_des_que_deq_cfg0_u iqm_des_que_deq_cfg0; /* 94 */ + volatile csr_iqm_des_que_deq_cfg1_u iqm_des_que_deq_cfg1; /* 98 */ + volatile csr_iqm_root_thr_cfg_u iqm_root_thr_cfg; /* 9C */ + volatile csr_iqm_root_hthr_cfg_u iqm_root_hthr_cfg; /* A0 */ + volatile csr_iqm_nmq_root_thr_cfg_u iqm_nmq_root_thr_cfg; /* A4 */ + volatile csr_iqm_nfmq_root_thr_cfg_u iqm_nfmq_root_thr_cfg; /* A8 */ + volatile csr_iqm_nmq_host0_th_u iqm_nmq_host0_th; /* AC */ + volatile csr_iqm_nmq_host1_th_u iqm_nmq_host1_th; /* B0 */ + volatile csr_iqm_nmq_host2_th_u iqm_nmq_host2_th; /* B4 */ + volatile csr_iqm_nmq_host3_th_u iqm_nmq_host3_th; /* B8 */ + volatile csr_iqm_nmq_host_hth_pa_u iqm_nmq_host_hth_pa; /* BC */ + volatile csr_iqm_nfmq_host0_th_u iqm_nfmq_host0_th; /* C0 */ + volatile csr_iqm_nfmq_host1_th_u iqm_nfmq_host1_th; /* C4 */ + volatile csr_iqm_nfmq_host2_th_u iqm_nfmq_host2_th; /* C8 */ + volatile csr_iqm_nfmq_host3_th_u iqm_nfmq_host3_th; /* CC */ + volatile csr_iqm_nfmq_host_hth_pa_u iqm_nfmq_host_hth_pa; /* D0 */ + volatile csr_iqm_nmq_hex_pro_map_u iqm_nmq_hex_pro_map[4]; /* D4 */ + volatile csr_iqm_nfmq_hex_pro_map_u iqm_nfmq_hex_pro_map[4]; /* E4 */ + volatile csr_iqm_he_th_pro_u iqm_he_th_pro[16]; /* F4 */ + volatile csr_iqm_he_fac_pro_u iqm_he_fac_pro[16]; /* 134 */ + volatile csr_iqm_qtss_cfg_u iqm_qtss_cfg; /* 174 */ + volatile csr_iqm_hetss_cfg_u iqm_hetss_cfg; /* 178 */ + volatile csr_iqm_hectss_cfg_u iqm_hectss_cfg; /* 17C */ + volatile csr_iqm_sm_host_credit_th_u iqm_sm_host_credit_th[5]; /* 180 */ + volatile csr_iqm_sm_credit_tss_cfg_data_u iqm_sm_credit_tss_cfg_data; /* 194 */ + volatile csr_iqm_sm_credit_tss_cfg_sge_u iqm_sm_credit_tss_cfg_sge; /* 198 */ + volatile csr_iqm_qu_credit_tss_cfg_u iqm_qu_credit_tss_cfg; /* 19C */ + volatile csr_iqm_crr_wgt_cfg_u iqm_crr_wgt_cfg; /* 1A0 */ + volatile csr_iqm_db_merger_cfg_u iqm_db_merger_cfg; /* 1A4 */ + volatile csr_smf_dst_hash_cfg_u smf_dst_hash_cfg; /* 1A8 */ + volatile csr_iqm_aging_clr_cfg_u iqm_aging_clr_cfg; /* 1AC */ + volatile csr_iqm_mem_ecc_bypass_en_u iqm_mem_ecc_bypass_en; /* 1B0 */ + volatile csr_iqm_mem_ctrl_bus_cfg0_u iqm_mem_ctrl_bus_cfg0; /* 1B4 */ + volatile csr_iqm_mem_ctrl_bus_cfg1_u iqm_mem_ctrl_bus_cfg1; /* 1B8 */ + volatile csr_iqm_mem_ctrl_bus_cfg2_u iqm_mem_ctrl_bus_cfg2; /* 1BC */ + volatile csr_iqm_mem_ctrl_bus_cfg3_u iqm_mem_ctrl_bus_cfg3; /* 1C0 */ + volatile csr_iqm_mem_ctrl_bus_cfg4_u iqm_mem_ctrl_bus_cfg4; /* 1C4 */ + volatile csr_iqm_sm_shallow_fifo_status_u iqm_sm_shallow_fifo_status[14]; /* 1E0 */ + volatile csr_iqm_qu_shallow_fifo_status_u iqm_qu_shallow_fifo_status[18]; /* 218 */ + volatile csr_iqm_cmq_cnt_u iqm_cmq_cnt; /* 260 */ + volatile csr_iqm_cmq_host_cnt0_u iqm_cmq_host_cnt0; /* 264 */ + volatile csr_iqm_cmq_host_cnt1_u iqm_cmq_host_cnt1; /* 268 */ + volatile csr_iqm_cmq_hostepx_cnt_u iqm_cmq_hostepx_cnt[32]; /* 26C */ + volatile csr_iqm_rootx_cnt_u iqm_rootx_cnt; /* 2EC */ + volatile csr_iqm_nmq_hostx_cnt0_u iqm_nmq_hostx_cnt0; /* 2F0 */ + volatile csr_iqm_nmq_hostx_cnt1_u iqm_nmq_hostx_cnt1; /* 2F4 */ + volatile csr_iqm_nfmq_hostx_cnt0_u iqm_nfmq_hostx_cnt0; /* 2F8 */ + volatile csr_iqm_nfmq_hostx_cnt1_u iqm_nfmq_hostx_cnt1; /* 2FC */ + volatile csr_iqm_mq_hex_cnt_u iqm_mq_hex_cnt[32]; /* 300 */ + volatile csr_iqm_ucmq_root_cnt_u iqm_ucmq_root_cnt; /* 380 */ + volatile csr_iqm_unmq_root_cnt_u iqm_unmq_root_cnt; /* 384 */ + volatile csr_iqm_uxmq_ep_cnt_u iqm_uxmq_ep_cnt[8]; /* 388 */ + volatile csr_iqm_uxmq_queue_cnt_u iqm_uxmq_queue_cnt[64]; /* 3A8 */ + volatile csr_eqm_enq_fifo_status_u eqm_enq_fifo_status; /* 4A8 */ + volatile csr_deqc_enq_fifo_status_u deqc_enq_fifo_status; /* 4AC */ + volatile csr_iqm_enqc_enq_fifo_status_u iqm_enqc_enq_fifo_status; /* 4B0 */ + volatile csr_iqm_enqc_soc_enq_fifo_status_u iqm_enqc_soc_enq_fifo_status; /* 4B4 */ + volatile csr_iqm_cpi_sge_crdt_comp_fifo_status_u iqm_cpi_sge_crdt_comp_fifo_status; /* 4B8 */ + volatile csr_iqm_cpi_data_crdt_comp_fifo_status_u iqm_cpi_data_crdt_comp_fifo_status; /* 4BC */ + volatile csr_iqm_sm_crdt_comp_fifo_status_u iqm_sm_crdt_comp_fifo_status; /* 4C0 */ + volatile csr_iqm_sm_out_fifo_status_u iqm_sm_out_fifo_status; /* 4C4 */ + volatile csr_iqm_qu_crdt_comp_fifo_status_u iqm_qu_crdt_comp_fifo_status; /* 4C8 */ + volatile csr_icll_free_cnt_u icll_free_cnt; /* 4CC */ + volatile csr_iqm_sm_total_cam_cnt_u iqm_sm_total_cam_cnt; /* 4D0 */ + volatile csr_iqm_sm_host_crdt_bp_u iqm_sm_host_crdt_bp; /* 4D4 */ + volatile csr_iqm_sm_ep_host_dp_rr_sge_crdt_bp_u iqm_sm_ep_host_dp_rr_sge_crdt_bp; /* 4D8 */ + volatile csr_iqm_sm_ep_host_dp_rr_dat_crdt_bp_u iqm_sm_ep_host_dp_rr_dat_crdt_bp; /* 4DC */ + volatile csr_iqm_sm_ep_host_dp_sge_crdt_bp_u iqm_sm_ep_host_dp_sge_crdt_bp; /* 4E0 */ + volatile csr_iqm_sm_ep_host_dp_dat_crdt_bp_u iqm_sm_ep_host_dp_dat_crdt_bp; /* 4E4 */ + volatile csr_iqm_sm_ep_host_cp_rr_crdt_bp_u iqm_sm_ep_host_cp_rr_crdt_bp; /* 4E8 */ + volatile csr_iqm_sm_ep_soc_rr_crdt_bp_u iqm_sm_ep_soc_rr_crdt_bp; /* 4EC */ + volatile csr_iqm_sm_ep_host_cp_crdt_bp_u iqm_sm_ep_host_cp_crdt_bp; /* 4F0 */ + volatile csr_iqm_sm_ep_soc_crdt_bp_u iqm_sm_ep_soc_crdt_bp; /* 4F4 */ + volatile csr_iqm_qu_ep_dp_crdt_bp0_u iqm_qu_ep_dp_crdt_bp0; /* 4F8 */ + volatile csr_iqm_qu_ep_dp_crdt_bp1_u iqm_qu_ep_dp_crdt_bp1; /* 4FC */ + volatile csr_iqm_qu_ep_cp_crdt_bp_u iqm_qu_ep_cp_crdt_bp; /* 500 */ + volatile csr_iqm_qu_ep_dp_rr_crdt_bp0_u iqm_qu_ep_dp_rr_crdt_bp0; /* 504 */ + volatile csr_iqm_qu_ep_dp_rr_crdt_bp1_u iqm_qu_ep_dp_rr_crdt_bp1; /* 508 */ + volatile csr_iqm_qu_ep_cp_rr_crdt_bp_u iqm_qu_ep_cp_rr_crdt_bp; /* 50C */ + volatile csr_iqm_flush_icll_cam_done_u iqm_flush_icll_cam_done; /* 510 */ + volatile csr_iqm_aging_nmq_cnt_u iqm_aging_nmq_cnt; /* B38 */ + volatile csr_iqm_aging_nfmq_cnt_u iqm_aging_nfmq_cnt; /* B3C */ + volatile csr_iqm_aging_discard_cnt_u iqm_aging_discard_cnt; /* B40 */ + volatile csr_iqm_to_eqm_qd_cnt_u iqm_to_eqm_qd_cnt; /* B44 */ + volatile csr_iqm_deq_sm_cnt_u iqm_deq_sm_cnt; /* B48 */ + volatile csr_iqm_deq_qu_cnt_u iqm_deq_qu_cnt; /* B4C */ + volatile csr_msc_iqm_deq_cnt_u msc_iqm_deq_cnt; /* B50 */ + volatile csr_iqm_nmqnfmq_enq_cnt_u iqm_nmqnfmq_enq_cnt; /* B54 */ + volatile csr_iqm_nmqnfmq_deq_cnt_u iqm_nmqnfmq_deq_cnt; /* B58 */ + volatile csr_iqm_cmq_enq_cnt_u iqm_cmq_enq_cnt; /* B5C */ + volatile csr_iqm_cmq_deq_cnt_u iqm_cmq_deq_cnt; /* B60 */ + volatile csr_soc_msc_iqm_deq_cnt_u soc_msc_iqm_deq_cnt; /* B64 */ + volatile csr_iqm_unmq_enq_cnt_u iqm_unmq_enq_cnt; /* B68 */ + volatile csr_iqm_unmq_deq_cnt_u iqm_unmq_deq_cnt; /* B6C */ + volatile csr_iqm_ucmq_enq_cnt_u iqm_ucmq_enq_cnt; /* B70 */ + volatile csr_iqm_ucmq_deq_cnt_u iqm_ucmq_deq_cnt; /* B74 */ + volatile csr_iqm_rx_cpi_comp_host_sge_crdt_cnt_u iqm_rx_cpi_comp_host_sge_crdt_cnt; /* B78 */ + volatile csr_iqm_rx_cpi_comp_host_dat_crdt_cnt_u iqm_rx_cpi_comp_host_dat_crdt_cnt; /* B7C */ + volatile csr_iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt_u iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt; /* B80 */ + volatile csr_iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt_u iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt; /* B84 */ + volatile csr_iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt_u iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt; /* B88 */ + volatile csr_iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt_u iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt; /* B8C */ + volatile csr_iqm_rx_qu_comp_ep_dp_crdt_cnt_u iqm_rx_qu_comp_ep_dp_crdt_cnt; /* B90 */ + volatile csr_iqm_rx_qu_comp_ep_cp_crdt_cnt_u iqm_rx_qu_comp_ep_cp_crdt_cnt; /* B94 */ + volatile csr_iqm_ecc_1bit_err_cnt_u iqm_ecc_1bit_err_cnt; /* B98 */ + volatile csr_iqm_ecc_2bit_err_cnt_u iqm_ecc_2bit_err_cnt; /* B9C */ +} S_mqm_iqm_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_iqm */ +extern volatile S_mqm_iqm_REGS_TYPE *gopmqm_iqmAllReg; + +/* Declare the functions that set the member value */ +int iSetIQM_RW_RSV0_iqm_rw_rsv0(unsigned int uiqm_rw_rsv0); +int iSetIQM_RW_RSV1_iqm_rw_rsv1(unsigned int uiqm_rw_rsv1); +int iSetIQM_RW_RSV2_iqm_rw_rsv2(unsigned int uiqm_rw_rsv2); +int iSetIQM_RW_RSV3_iqm_rw_rsv3(unsigned int uiqm_rw_rsv3); +int iSetIQM_INDRECT_CTRL_iqm_indrect_addr(unsigned int uiqm_indrect_addr); +int iSetIQM_INDRECT_CTRL_iqm_indrect_tab(unsigned int uiqm_indrect_tab); +int iSetIQM_INDRECT_CTRL_iqm_indrect_status(unsigned int uiqm_indrect_status); +int iSetIQM_INDRECT_CTRL_iqm_indrect_mode(unsigned int uiqm_indrect_mode); +int iSetIQM_INDRECT_CTRL_iqm_indrect_vld(unsigned int uiqm_indrect_vld); +int iSetIQM_INDRECT_TIMEOUT_iqm_indrect_timeout(unsigned int uiqm_indrect_timeout); +int iSetIQM_INDRECT_DATA_0_iqm_indrect_data_0(unsigned int uiqm_indrect_data_0); +int iSetIQM_INDRECT_DATA_1_iqm_indrect_data_1(unsigned int uiqm_indrect_data_1); +int iSetIQM_INT_VECTOR_iqm_cpi_int_index(unsigned int uiqm_cpi_int_index); +int iSetIQM_INT_VECTOR_iqm_enable(unsigned int uiqm_enable); +int iSetIQM_INT_VECTOR_iqm_int_issue(unsigned int uiqm_int_issue); +int iSetIQM_INT_iqm_int_data(unsigned int uiqm_int_data); +int iSetIQM_INT_iqm_program_csr_id_ro(unsigned int uiqm_program_csr_id_ro); +int iSetIQM_INT_EN_iqm_int_en(unsigned int uiqm_int_en); +int iSetIQM_INT_EN_iqm_program_csr_id(unsigned int uiqm_program_csr_id); +int iSetIQM_MEM_ECC0_iqm_ecc0_err(unsigned int uiqm_ecc0_err); +int iSetIQM_MEM_ECC0_iqm_ecc0_err_insert(unsigned int uiqm_ecc0_err_insert); +int iSetIQM_MEM_ECC0_iqm_ecc0_err_info(unsigned int uiqm_ecc0_err_info); +int iSetIQM_MEM_ECC1_iqm_ecc1_err(unsigned int uiqm_ecc1_err); +int iSetIQM_MEM_ECC1_iqm_ecc1_err_insert(unsigned int uiqm_ecc1_err_insert); +int iSetIQM_MEM_ECC1_iqm_ecc1_err_info(unsigned int uiqm_ecc1_err_info); +int iSetIQM_AGING_INT_iqm_aging_int_err(unsigned int uiqm_aging_int_err); +int iSetIQM_AGING_INT_iqm_aging_int_err_insert(unsigned int uiqm_aging_int_err_insert); +int iSetIQM_AGING_INT_iqm_aging_int_err_info(unsigned int uiqm_aging_int_err_info); +int iSetIQM_CMQ_DEQ_EMPTY_INT_iqm_cmq_deq_empty_err(unsigned int uiqm_cmq_deq_empty_err); +int iSetIQM_CMQ_DEQ_EMPTY_INT_iqm_cmq_deq_empty_err_insert(unsigned int uiqm_cmq_deq_empty_err_insert); +int iSetIQM_CMQ_DEQ_EMPTY_INT_iqm_cmq_deq_empty_err_info(unsigned int uiqm_cmq_deq_empty_err_info); +int iSetIQM_FIFO_WR_OVFL_INT_iqm_fifo_wr_ovfl_err(unsigned int uiqm_fifo_wr_ovfl_err); +int iSetIQM_FIFO_WR_OVFL_INT_iqm_fifo_wr_ovfl_err_insert(unsigned int uiqm_fifo_wr_ovfl_err_insert); +int iSetIQM_FIFO_WR_OVFL_INT_iqm_fifo_wr_ovfl_err_info(unsigned int uiqm_fifo_wr_ovfl_err_info); +int iSetIQM_FIFO_RD_UDFL_INT_iqm_fifo_rd_udfl_err(unsigned int uiqm_fifo_rd_udfl_err); +int iSetIQM_FIFO_RD_UDFL_INT_iqm_fifo_rd_udfl_err_insert(unsigned int uiqm_fifo_rd_udfl_err_insert); +int iSetIQM_FIFO_RD_UDFL_INT_iqm_fifo_rd_udfl_err_info(unsigned int uiqm_fifo_rd_udfl_err_info); +int iSetIQM_FREE_RSC_BMP_OVERFLOW_INT_iqm_free_rsc_bmp_ovfl_err(unsigned int uiqm_free_rsc_bmp_ovfl_err); +int iSetIQM_FREE_RSC_BMP_OVERFLOW_INT_iqm_free_rsc_bmp_ovfl_err_insert(unsigned int uiqm_free_rsc_bmp_ovfl_err_insert); +int iSetIQM_FREE_RSC_BMP_OVERFLOW_INT_iqm_free_rsc_bmp_ovfl_err_info(unsigned int uiqm_free_rsc_bmp_ovfl_err_info); +int iSetIQM_CLL_DEQ_EMPTY_INT_iqm_nmqnfmq_deq_empty_err(unsigned int uiqm_nmqnfmq_deq_empty_err); +int iSetIQM_CLL_DEQ_EMPTY_INT_iqm_nmqnfmq_deq_empty_err_insert(unsigned int uiqm_nmqnfmq_deq_empty_err_insert); +int iSetIQM_CLL_DEQ_EMPTY_INT_iqm_nmqnfmq_deq_empty_err_info(unsigned int uiqm_nmqnfmq_deq_empty_err_info); +int iSetIQM_UXMQ_DEQ_EMPTY_INT_iqm_uxmq_deq_empty_err(unsigned int uiqm_uxmq_deq_empty_err); +int iSetIQM_UXMQ_DEQ_EMPTY_INT_iqm_uxmq_deq_empty_err_insert(unsigned int uiqm_uxmq_deq_empty_err_insert); +int iSetIQM_UXMQ_DEQ_EMPTY_INT_iqm_uxmq_deq_empty_err_info(unsigned int uiqm_uxmq_deq_empty_err_info); +int iSetIQM_FIFO_INT_REQ1_sm_shallow_fifo_rd_udfl_insert0(unsigned int usm_shallow_fifo_rd_udfl_insert0); +int iSetIQM_FIFO_INT_REQ2_qu_shallow_fifo_rd_udfl_insert2(unsigned int uqu_shallow_fifo_rd_udfl_insert2); +int iSetIQM_FIFO_INT_REQ2_sm_shallow_fifo_rd_udfl_insert1(unsigned int usm_shallow_fifo_rd_udfl_insert1); +int iSetIQM_FIFO_INT_REQ3_qu_shallow_fifo_rd_udfl_insert0(unsigned int uqu_shallow_fifo_rd_udfl_insert0); +int iSetIQM_FIFO_INT_REQ4_qu_shallow_fifo_rd_udfl_insert1(unsigned int uqu_shallow_fifo_rd_udfl_insert1); +int iSetIQM_MEM_ECC_REQ0_cll_head_mem_err_req(unsigned int ucll_head_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_tail_mem_err_req(unsigned int ucll_tail_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_mqle_mem_err_req(unsigned int ucll_mqle_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_ckll_mem_err_req(unsigned int ucll_ckll_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_mq2vf_mem_err_req(unsigned int umq2vf_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_faptab_mem_err_req(unsigned int ucll_faptab_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_pre_enq_qlen_mem_err_req(unsigned int upre_enq_qlen_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_que_pro_map_mem_err_req(unsigned int uque_pro_map_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_pre_enq_hec_len_mem_err_req(unsigned int upre_enq_hec_len_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_ll_head_mem_err_req(unsigned int ucmq_ll_head_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_ll_tail_mem_err_req(unsigned int ucmq_ll_tail_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_queue_len_mem_err_req(unsigned int ucmq_queue_len_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_ll_mem_err_req(unsigned int ucmq_ll_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_hec_len_mem_err_req(unsigned int ucmq_hec_len_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_ill_soc_ll_err_req(unsigned int uill_soc_ll_err_req); +int iSetIQM_MEM_ECC_REQ1_soc_qd_err_req(unsigned int usoc_qd_err_req); +int iSetIQM_MEM_ECC_REQ1_deq_sm_fifo_mem_err_req(unsigned int udeq_sm_fifo_mem_err_req); +int iSetIQM_MEM_ECC_REQ1_deq_qu_fifo_mem_err_req(unsigned int udeq_qu_fifo_mem_err_req); +int iSetIQM_MEM_ECC_REQ1_iqm_agcnt_err_req(unsigned int uiqm_agcnt_err_req); +int iSetIQM_MEM_ECC_REQ1_iqm_agvld_err_req(unsigned int uiqm_agvld_err_req); +int iSetIQM_UNCRT_INT_EN_cll_rsc_overflow_uncrt_int_en(unsigned int ucll_rsc_overflow_uncrt_int_en); +int iSetIQM_UNCRT_INT_EN_cll_deq_empty_uncrt_int_en(unsigned int ucll_deq_empty_uncrt_int_en); +int iSetIQM_UNCRT_INT_EN_cmq_deq_empty_uncrt_int_en(unsigned int ucmq_deq_empty_uncrt_int_en); +int iSetIQM_UNCRT_INT_EN_uxmq_deq_empty_uncrt_int_en(unsigned int uuxmq_deq_empty_uncrt_int_en); +int iSetIQM_FIFO_INT_REQ5_sm_shallow_fifo_wr_ovfl_insert0(unsigned int usm_shallow_fifo_wr_ovfl_insert0); +int iSetIQM_FIFO_INT_REQ6_qu_shallow_fifo_wr_ovfl_insert2(unsigned int uqu_shallow_fifo_wr_ovfl_insert2); +int iSetIQM_FIFO_INT_REQ6_sm_shallow_fifo_wr_ovfl_insert1(unsigned int usm_shallow_fifo_wr_ovfl_insert1); +int iSetIQM_FIFO_INT_REQ7_qu_shallow_fifo_wr_ovfl_insert0(unsigned int uqu_shallow_fifo_wr_ovfl_insert0); +int iSetIQM_FIFO_INT_REQ8_qu_shallow_fifo_wr_ovfl_insert1(unsigned int uqu_shallow_fifo_wr_ovfl_insert1); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_fifo_wr_ovfl_insert(unsigned int uenqc_enq_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_fifo_rd_udfl_insert(unsigned int uenqc_enq_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_eqm_enq_fifo_wr_ovfl_insert(unsigned int ueqm_enq_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_eqm_enq_fifo_rd_udfl_insert(unsigned int ueqm_enq_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_deqc_enq_fifo_wr_ovfl_insert(unsigned int udeqc_enq_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_deqc_enq_fifo_rd_udfl_insert(unsigned int udeqc_enq_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_soc_fifo_wr_ovfl_insert(unsigned int uenqc_enq_soc_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_soc_fifo_rd_udfl_insert(unsigned int uenqc_enq_soc_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_dp_out_fifo_wr_ovfl_insert(unsigned int usm_dp_out_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_dp_out_fifo_rd_udfl_insert(unsigned int usm_dp_out_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_cp_out_fifo_wr_ovfl_insert(unsigned int usm_cp_out_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_cp_out_fifo_rd_udfl_insert(unsigned int usm_cp_out_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_ep_sge_fifo_wr_ovfl_insert(unsigned int ucpi_ep_sge_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_ep_sge_fifo_rd_udfl_insert(unsigned int ucpi_ep_sge_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_host_sge_fifo_wr_ovfl_insert(unsigned int ucpi_host_sge_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_host_sge_fifo_rd_udfl_insert(unsigned int ucpi_host_sge_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_data_fifo_wr_ovfl_insert(unsigned int ucpi_data_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_data_fifo_rd_udfl_insert(unsigned int ucpi_data_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_data_fifo_wr_ovfl_insert(unsigned int usm_data_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_data_fifo_rd_udfl_insert(unsigned int usm_data_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_sge_fifo_wr_ovfl_insert(unsigned int usm_sge_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_sge_fifo_rd_udfl_insert(unsigned int usm_sge_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_qu_ep_fifo_wr_ovfl_insert(unsigned int uqu_ep_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_qu_ep_fifo_rd_udfl_insert(unsigned int uqu_ep_fifo_rd_udfl_insert); +int iSetIQM_CHUNK_chunk_size(unsigned int uchunk_size); +int iSetIQM_CHUNK_icll_bitmap_critical_depth(unsigned int uicll_bitmap_critical_depth); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_deq_sm_ctrl_plane_aful_gap(unsigned int uiqm_deq_sm_ctrl_plane_aful_gap); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_deq_sm_data_plane_aful_gap(unsigned int uiqm_deq_sm_data_plane_aful_gap); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_qu_shallow_fifo_gap(unsigned int uiqm_qu_shallow_fifo_gap); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_sm_shallow_fifo_gap(unsigned int uiqm_sm_shallow_fifo_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_enqc_enq_fifo_afull_gap(unsigned int uenqc_enq_fifo_afull_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_eqm_enq_fifo_afull_gap(unsigned int ueqm_enq_fifo_afull_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_deqc_enq_fifo_afull_gap(unsigned int udeqc_enq_fifo_afull_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_enqc_enq_soc_fifo_afull_gap(unsigned int uenqc_enq_soc_fifo_afull_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_sm_data_aful_gap(unsigned int usm_data_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_sm_sge_aful_gap(unsigned int usm_sge_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_cpi_data_aful_gap(unsigned int ucpi_data_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_cpi_host_sge_aful_gap(unsigned int ucpi_host_sge_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_cpi_ep_sge_aful_gap(unsigned int ucpi_ep_sge_aful_gap); +int iSetIQM_AGING_CFG_nmq_aging_en(unsigned int unmq_aging_en); +int iSetIQM_AGING_CFG_nfmq_aging_en(unsigned int unfmq_aging_en); +int iSetIQM_AGING_CFG_aging_intval(unsigned int uaging_intval); +int iSetIQM_AGING_CFG_aging_dest(unsigned int uaging_dest); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_mqid(unsigned int udes_que_deq_mqid); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_qa(unsigned int udes_que_deq_qa); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_src(unsigned int udes_que_deq_src); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_hid(unsigned int udes_que_deq_hid); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_cos(unsigned int udes_que_deq_cos); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_ep(unsigned int udes_que_deq_ep); +int iSetIQM_DES_QUE_DEQ_CFG1_iqm_des_que_deq_vld(unsigned int uiqm_des_que_deq_vld); +int iSetIQM_DES_QUE_DEQ_CFG1_des_que_deq_vfid(unsigned int udes_que_deq_vfid); +int iSetIQM_ROOT_THR_CFG_root_total_fl_static_th(unsigned int uroot_total_fl_static_th); +int iSetIQM_ROOT_THR_CFG_root_total_sl_static_th(unsigned int uroot_total_sl_static_th); +int iSetIQM_ROOT_HTHR_CFG_root_hth_parm_nmq(unsigned int uroot_hth_parm_nmq); +int iSetIQM_ROOT_HTHR_CFG_root_hth_parm_nfmq(unsigned int uroot_hth_parm_nfmq); +int iSetIQM_ROOT_HTHR_CFG_root_total_hth_parm(unsigned int uroot_total_hth_parm); +int iSetIQM_NMQ_ROOT_THR_CFG_root_fl_static_th_nmq(unsigned int uroot_fl_static_th_nmq); +int iSetIQM_NMQ_ROOT_THR_CFG_root_sl_static_th_nmq(unsigned int uroot_sl_static_th_nmq); +int iSetIQM_NFMQ_ROOT_THR_CFG_root_fl_static_th_nfmq(unsigned int uroot_fl_static_th_nfmq); +int iSetIQM_NFMQ_ROOT_THR_CFG_root_sl_static_th_nfmq(unsigned int uroot_sl_static_th_nfmq); +int iSetIQM_NMQ_HOST0_TH_hid0_fl_static_th_nmq(unsigned int uhid0_fl_static_th_nmq); +int iSetIQM_NMQ_HOST0_TH_hid0_sl_static_th_nmq(unsigned int uhid0_sl_static_th_nmq); +int iSetIQM_NMQ_HOST1_TH_hid1_fl_static_th_nmq(unsigned int uhid1_fl_static_th_nmq); +int iSetIQM_NMQ_HOST1_TH_hid1_sl_static_th_nmq(unsigned int uhid1_sl_static_th_nmq); +int iSetIQM_NMQ_HOST2_TH_hid2_fl_static_th_nmq(unsigned int uhid2_fl_static_th_nmq); +int iSetIQM_NMQ_HOST2_TH_hid2_sl_static_th_nmq(unsigned int uhid2_sl_static_th_nmq); +int iSetIQM_NMQ_HOST3_TH_hid3_fl_static_th_nmq(unsigned int uhid3_fl_static_th_nmq); +int iSetIQM_NMQ_HOST3_TH_hid3_sl_static_th_nmq(unsigned int uhid3_sl_static_th_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid0_hth_parm_nmq(unsigned int uhid0_hth_parm_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid1_hth_parm_nmq(unsigned int uhid1_hth_parm_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid2_hth_parm_nmq(unsigned int uhid2_hth_parm_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid3_hth_parm_nmq(unsigned int uhid3_hth_parm_nmq); +int iSetIQM_NFMQ_HOST0_TH_hid0_fl_static_th_nfmq(unsigned int uhid0_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST0_TH_hid0_sl_static_th_nfmq(unsigned int uhid0_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST1_TH_hid1_fl_static_th_nfmq(unsigned int uhid1_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST1_TH_hid1_sl_static_th_nfmq(unsigned int uhid1_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST2_TH_hid2_fl_static_th_nfmq(unsigned int uhid2_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST2_TH_hid2_sl_static_th_nfmq(unsigned int uhid2_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST3_TH_hid3_fl_static_th_nfmq(unsigned int uhid3_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST3_TH_hid3_sl_static_th_nfmq(unsigned int uhid3_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid0_hth_parm_nfmq(unsigned int uhid0_hth_parm_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid1_hth_parm_nfmq(unsigned int uhid1_hth_parm_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid2_hth_parm_nfmq(unsigned int uhid2_hth_parm_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid3_hth_parm_nfmq(unsigned int uhid3_hth_parm_nfmq); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_0(unsigned int uhe_pro_map_nmq_0); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_1(unsigned int uhe_pro_map_nmq_1); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_2(unsigned int uhe_pro_map_nmq_2); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_3(unsigned int uhe_pro_map_nmq_3); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_4(unsigned int uhe_pro_map_nmq_4); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_5(unsigned int uhe_pro_map_nmq_5); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_6(unsigned int uhe_pro_map_nmq_6); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_7(unsigned int uhe_pro_map_nmq_7); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_0(unsigned int uhe_pro_map_nfmq_0); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_1(unsigned int uhe_pro_map_nfmq_1); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_2(unsigned int uhe_pro_map_nfmq_2); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_3(unsigned int uhe_pro_map_nfmq_3); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_4(unsigned int uhe_pro_map_nfmq_4); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_5(unsigned int uhe_pro_map_nfmq_5); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_6(unsigned int uhe_pro_map_nfmq_6); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_7(unsigned int uhe_pro_map_nfmq_7); +int iSetIQM_HE_TH_PRO_he_fl_static_th_pro(unsigned int uhe_fl_static_th_pro); +int iSetIQM_HE_TH_PRO_he_sl_static_th_pro(unsigned int uhe_sl_static_th_pro); +int iSetIQM_HE_FAC_PRO_host_ep_fl_a_fact_pro(unsigned int uhost_ep_fl_a_fact_pro); +int iSetIQM_HE_FAC_PRO_host_ep_sl_a_fact_pro(unsigned int uhost_ep_sl_a_fact_pro); +int iSetIQM_HE_FAC_PRO_host_ep_hth_parm_pro(unsigned int uhost_ep_hth_parm_pro); +int iSetIQM_QTSS_CFG_qtsc_fl(unsigned int uqtsc_fl); +int iSetIQM_QTSS_CFG_qtsc_sl(unsigned int uqtsc_sl); +int iSetIQM_HETSS_CFG_he_tsc_fl(unsigned int uhe_tsc_fl); +int iSetIQM_HETSS_CFG_he_tsc_sl(unsigned int uhe_tsc_sl); +int iSetIQM_HECTSS_CFG_hec_tsc_fl(unsigned int uhec_tsc_fl); +int iSetIQM_HECTSS_CFG_hec_tsc_sl(unsigned int uhec_tsc_sl); +int iSetIQM_SM_HOST_CREDIT_TH_iqm_sm_host_credit_data_th(unsigned int uiqm_sm_host_credit_data_th); +int iSetIQM_SM_HOST_CREDIT_TH_iqm_sm_host_credit_sge_th(unsigned int uiqm_sm_host_credit_sge_th); +int iSetIQM_SM_CREDIT_TSS_CFG_DATA_iqm_sm_ep_cp_credit_tss_data(unsigned int uiqm_sm_ep_cp_credit_tss_data); +int iSetIQM_SM_CREDIT_TSS_CFG_DATA_iqm_sm_ep_dp_credit_tss_data(unsigned int uiqm_sm_ep_dp_credit_tss_data); +int iSetIQM_SM_CREDIT_TSS_CFG_SGE_iqm_sm_ep_cp_credit_tss_sge(unsigned int uiqm_sm_ep_cp_credit_tss_sge); +int iSetIQM_SM_CREDIT_TSS_CFG_SGE_iqm_sm_ep_dp_credit_tss_sge(unsigned int uiqm_sm_ep_dp_credit_tss_sge); +int iSetIQM_QU_CREDIT_TSS_CFG_iqm_qu_ep_cp_credit_tss(unsigned int uiqm_qu_ep_cp_credit_tss); +int iSetIQM_QU_CREDIT_TSS_CFG_iqm_qu_ep_dp_credit_tss(unsigned int uiqm_qu_ep_dp_credit_tss); +int iSetIQM_CRR_WGT_CFG_iqm_sm_dp_crr_wgt(unsigned int uiqm_sm_dp_crr_wgt); +int iSetIQM_CRR_WGT_CFG_iqm_sm_cp_crr_wgt(unsigned int uiqm_sm_cp_crr_wgt); +int iSetIQM_CRR_WGT_CFG_iqm_qu_dp_crr_wgt(unsigned int uiqm_qu_dp_crr_wgt); +int iSetIQM_CRR_WGT_CFG_iqm_qu_cp_crr_wgt(unsigned int uiqm_qu_cp_crr_wgt); +int iSetIQM_DB_MERGER_CFG_iqm_db_merger_en(unsigned int uiqm_db_merger_en); +int iSetIQM_DB_MERGER_CFG_iqm_db_merger_num(unsigned int uiqm_db_merger_num); +int iSetIQM_DB_MERGER_CFG_iqm_db_merger_num_sum(unsigned int uiqm_db_merger_num_sum); +int iSetSMF_DST_HASH_CFG_smf_pg_cfg(unsigned int usmf_pg_cfg); +int iSetSMF_DST_HASH_CFG_lbf_mode_sel_cfg(unsigned int ulbf_mode_sel_cfg); +int iSetIQM_AGING_CLR_CFG_mq_ag_clr_mqid(unsigned int umq_ag_clr_mqid); +int iSetIQM_AGING_CLR_CFG_mq_ag_clr_qa(unsigned int umq_ag_clr_qa); +int iSetIQM_AGING_CLR_CFG_mq_ag_clr_vld(unsigned int umq_ag_clr_vld); +int iSetIQM_MEM_ECC_BYPASS_EN_iqm_mem_ecc_bypass(unsigned int uiqm_mem_ecc_bypass); +int iSetIQM_MEM_CTRL_BUS_CFG0_iqm_mem_ctrl_bus_0(unsigned int uiqm_mem_ctrl_bus_0); +int iSetIQM_MEM_CTRL_BUS_CFG1_iqm_mem_ctrl_bus_1(unsigned int uiqm_mem_ctrl_bus_1); +int iSetIQM_MEM_CTRL_BUS_CFG2_iqm_mem_ctrl_bus_2(unsigned int uiqm_mem_ctrl_bus_2); +int iSetIQM_MEM_CTRL_BUS_CFG3_iqm_mem_ctrl_bus_3(unsigned int uiqm_mem_ctrl_bus_3); +int iSetIQM_MEM_CTRL_BUS_CFG4_iqm_mem_ctrl_bus_4(unsigned int uiqm_mem_ctrl_bus_4); +int iSetIQM_SM_SHALLOW_FIFO_STATUS_sm_shallow_fifo_status(unsigned int usm_shallow_fifo_status); +int iSetIQM_QU_SHALLOW_FIFO_STATUS_qu_shallow_fifo_status(unsigned int uqu_shallow_fifo_status); +int iSetIQM_CMQ_CNT_iqm_cmq_root_cnt(unsigned int uiqm_cmq_root_cnt); +int iSetIQM_CMQ_HOST_CNT0_iqm_cmq_host0_cnt(unsigned int uiqm_cmq_host0_cnt); +int iSetIQM_CMQ_HOST_CNT0_iqm_cmq_host1_cnt(unsigned int uiqm_cmq_host1_cnt); +int iSetIQM_CMQ_HOST_CNT1_iqm_cmq_host2_cnt(unsigned int uiqm_cmq_host2_cnt); +int iSetIQM_CMQ_HOST_CNT1_iqm_cmq_host3_cnt(unsigned int uiqm_cmq_host3_cnt); +int iSetIQM_CMQ_HOSTEPX_CNT_iqm_cmq_hostep_cnt(unsigned int uiqm_cmq_hostep_cnt); +int iSetIQM_ROOTX_CNT_iqm_nmq_cnt(unsigned int uiqm_nmq_cnt); +int iSetIQM_ROOTX_CNT_iqm_nfmq_cnt(unsigned int uiqm_nfmq_cnt); +int iSetIQM_NMQ_HOSTX_CNT0_iqm_nmq_host0_cnt(unsigned int uiqm_nmq_host0_cnt); +int iSetIQM_NMQ_HOSTX_CNT0_iqm_nmq_host1_cnt(unsigned int uiqm_nmq_host1_cnt); +int iSetIQM_NMQ_HOSTX_CNT1_iqm_nmq_host2_cnt(unsigned int uiqm_nmq_host2_cnt); +int iSetIQM_NMQ_HOSTX_CNT1_iqm_nmq_host3_cnt(unsigned int uiqm_nmq_host3_cnt); +int iSetIQM_NFMQ_HOSTX_CNT0_iqm_nfmq_host0_cnt(unsigned int uiqm_nfmq_host0_cnt); +int iSetIQM_NFMQ_HOSTX_CNT0_iqm_nfmq_host1_cnt(unsigned int uiqm_nfmq_host1_cnt); +int iSetIQM_NFMQ_HOSTX_CNT1_iqm_nfmq_host2_cnt(unsigned int uiqm_nfmq_host2_cnt); +int iSetIQM_NFMQ_HOSTX_CNT1_iqm_nfmq_host3_cnt(unsigned int uiqm_nfmq_host3_cnt); +int iSetIQM_MQ_HEX_CNT_iqm_nmq_he_cnt(unsigned int uiqm_nmq_he_cnt); +int iSetIQM_MQ_HEX_CNT_iqm_nfmq_he_cnt(unsigned int uiqm_nfmq_he_cnt); +int iSetIQM_UCMQ_ROOT_CNT_iqm_ucmq_root_cnt(unsigned int uiqm_ucmq_root_cnt); +int iSetIQM_UNMQ_ROOT_CNT_iqm_unmq_root_cnt(unsigned int uiqm_unmq_root_cnt); +int iSetIQM_UXMQ_EP_CNT_unmq_qlen_ep(unsigned int uunmq_qlen_ep); +int iSetIQM_UXMQ_EP_CNT_ucmq_qlen_ep(unsigned int uucmq_qlen_ep); +int iSetIQM_UXMQ_QUEUE_CNT_iqm_unmqid_cnt(unsigned int uiqm_unmqid_cnt); +int iSetIQM_UXMQ_QUEUE_CNT_iqm_ucmqid_cnt(unsigned int uiqm_ucmqid_cnt); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_cnt(unsigned int ueqm_enq_fifo_cnt); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_full(unsigned int ueqm_enq_fifo_full); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_aful(unsigned int ueqm_enq_fifo_aful); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_empt(unsigned int ueqm_enq_fifo_empt); +int iSetDEQC_ENQ_FIFO_STATUS_deqc_enq_fifo_cnt(unsigned int udeqc_enq_fifo_cnt); +int iSetDEQC_ENQ_FIFO_STATUS_deqc_enq_fifo_full(unsigned int udeqc_enq_fifo_full); +int iSetDEQC_ENQ_FIFO_STATUS_deqc_enq_fifo_empt(unsigned int udeqc_enq_fifo_empt); +int iSetIQM_ENQC_ENQ_FIFO_STATUS_enqc_enq_fifo_cnt(unsigned int uenqc_enq_fifo_cnt); +int iSetIQM_ENQC_ENQ_FIFO_STATUS_enqc_enq_fifo_full(unsigned int uenqc_enq_fifo_full); +int iSetIQM_ENQC_ENQ_FIFO_STATUS_enqc_enq_fifo_empt(unsigned int uenqc_enq_fifo_empt); +int iSetIQM_ENQC_SOC_ENQ_FIFO_STATUS_enqc_soc_enq_fifo_cnt(unsigned int uenqc_soc_enq_fifo_cnt); +int iSetIQM_ENQC_SOC_ENQ_FIFO_STATUS_enqc_soc_enq_fifo_full(unsigned int uenqc_soc_enq_fifo_full); +int iSetIQM_ENQC_SOC_ENQ_FIFO_STATUS_enqc_soc_enq_fifo_empt(unsigned int uenqc_soc_enq_fifo_empt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_host_sge_fifo_cnt(unsigned int ucpi_host_sge_fifo_cnt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_host_sge_empt(unsigned int ucpi_host_sge_empt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_host_sge_full(unsigned int ucpi_host_sge_full); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_ep_sge_fifo_cnt(unsigned int ucpi_ep_sge_fifo_cnt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_ep_sge_empt(unsigned int ucpi_ep_sge_empt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_ep_sge_full(unsigned int ucpi_ep_sge_full); +int iSetIQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_cpi_data_fifo_cnt(unsigned int ucpi_data_fifo_cnt); +int iSetIQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_cpi_data_empt(unsigned int ucpi_data_empt); +int iSetIQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_cpi_data_full(unsigned int ucpi_data_full); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_data_fifo_cnt(unsigned int usm_data_fifo_cnt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_data_empt(unsigned int usm_data_empt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_data_full(unsigned int usm_data_full); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_sge_fifo_cnt(unsigned int usm_sge_fifo_cnt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_sge_empt(unsigned int usm_sge_empt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_sge_full(unsigned int usm_sge_full); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_cp_out_fifo_cnt(unsigned int usm_cp_out_fifo_cnt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_cp_out_fifo_empt(unsigned int usm_cp_out_fifo_empt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_cp_out_fifo_full(unsigned int usm_cp_out_fifo_full); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_dp_out_fifo_cnt(unsigned int usm_dp_out_fifo_cnt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_dp_out_fifo_empt(unsigned int usm_dp_out_fifo_empt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_dp_out_fifo_full(unsigned int usm_dp_out_fifo_full); +int iSetIQM_QU_CRDT_COMP_FIFO_STATUS_qu_ep_crdt_fifo_cnt(unsigned int uqu_ep_crdt_fifo_cnt); +int iSetIQM_QU_CRDT_COMP_FIFO_STATUS_qu_ep_crdt_fifo_empt(unsigned int uqu_ep_crdt_fifo_empt); +int iSetIQM_QU_CRDT_COMP_FIFO_STATUS_qu_ep_crdt_fifo_full(unsigned int uqu_ep_crdt_fifo_full); +int iSetICLL_FREE_CNT_icll_free_rsc_cnt(unsigned int uicll_free_rsc_cnt); +int iSetIQM_SM_TOTAL_CAM_CNT_iqm_sm_total_thread_cnt(unsigned int uiqm_sm_total_thread_cnt); +int iSetIQM_SM_HOST_CRDT_BP_iqm_sm_host_sge_crdt_bp(unsigned int uiqm_sm_host_sge_crdt_bp); +int iSetIQM_SM_HOST_CRDT_BP_iqm_sm_host_dat_crdt_bp(unsigned int uiqm_sm_host_dat_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_RR_SGE_CRDT_BP_iqm_sm_ep_host_dp_rr_sge_crdt_bp( + unsigned int uiqm_sm_ep_host_dp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_RR_DAT_CRDT_BP_iqm_sm_ep_host_dp_rr_dat_crdt_bp( + unsigned int uiqm_sm_ep_host_dp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_SGE_CRDT_BP_iqm_sm_ep_host_dp_sge_crdt_bp(unsigned int uiqm_sm_ep_host_dp_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_DAT_CRDT_BP_iqm_sm_ep_host_dp_data_crdt_bp(unsigned int uiqm_sm_ep_host_dp_data_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_RR_CRDT_BP_iqm_sm_ep_host_cp_rr_sge_crdt_bp(unsigned int uiqm_sm_ep_host_cp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_RR_CRDT_BP_iqm_sm_ep_host_cp_rr_dat_crdt_bp(unsigned int uiqm_sm_ep_host_cp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_dp_rr_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_cp_rr_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_dp_rr_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_cp_rr_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_CRDT_BP_iqm_sm_ep_host_cp_sge_crdt_bp(unsigned int uiqm_sm_ep_host_cp_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_CRDT_BP_iqm_sm_ep_host_cp_dat_crdt_bp(unsigned int uiqm_sm_ep_host_cp_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_dp_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_cp_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_dp_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_cp_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_dat_crdt_bp); +int iSetIQM_QU_EP_DP_CRDT_BP0_iqm_qu_ep_dp_crdt_bp0(unsigned int uiqm_qu_ep_dp_crdt_bp0); +int iSetIQM_QU_EP_DP_CRDT_BP1_iqm_qu_ep_dp_crdt_bp1(unsigned int uiqm_qu_ep_dp_crdt_bp1); +int iSetIQM_QU_EP_CP_CRDT_BP_iqm_qu_ep_cp_crdt_bp(unsigned int uiqm_qu_ep_cp_crdt_bp); +int iSetIQM_QU_EP_DP_RR_CRDT_BP0_iqm_qu_ep_dp_rr_crdt_bp0(unsigned int uiqm_qu_ep_dp_rr_crdt_bp0); +int iSetIQM_QU_EP_DP_RR_CRDT_BP1_iqm_qu_ep_dp_rr_crdt_bp1(unsigned int uiqm_qu_ep_dp_rr_crdt_bp1); +int iSetIQM_QU_EP_CP_RR_CRDT_BP_iqm_qu_ep_cp_rr_crdt_bp(unsigned int uiqm_qu_ep_cp_rr_crdt_bp); +int iSetIQM_FLUSH_ICLL_CAM_DONE_host_nmq_cll_flush_done(unsigned int uhost_nmq_cll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_host_nfmq_cll_flush_done(unsigned int uhost_nfmq_cll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_host_cmq_ll_flush_done(unsigned int uhost_cmq_ll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_soc_mq_ll_flush_done(unsigned int usoc_mq_ll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_sm_cam_flush_done(unsigned int usm_cam_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_qu_sl_fifo_flush_done(unsigned int uiqm_qu_sl_fifo_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_sm_sl_fifo_flush_done(unsigned int uiqm_sm_sl_fifo_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_sm_cp_crr_fifo_flush_done(unsigned int uiqm_sm_cp_crr_fifo_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_sm_dp_crr_fifo_flush_done(unsigned int uiqm_sm_dp_crr_fifo_flush_done); +int iSetIQM_AGING_NMQ_CNT_iqm_aging_nmq_cnt(unsigned int uiqm_aging_nmq_cnt); +int iSetIQM_AGING_NFMQ_CNT_iqm_aging_nfmq_cnt(unsigned int uiqm_aging_nfmq_cnt); +int iSetIQM_AGING_DISCARD_CNT_iqm_aging_discard_cnt(unsigned int uiqm_aging_discard_cnt); +int iSetIQM_TO_EQM_QD_CNT_iqm_to_eqm_qd_cnt(unsigned int uiqm_to_eqm_qd_cnt); +int iSetIQM_DEQ_SM_CNT_iqm_deq_to_sm_cnt(unsigned int uiqm_deq_to_sm_cnt); +int iSetIQM_DEQ_QU_CNT_iqm_deq_to_qu_cnt(unsigned int uiqm_deq_to_qu_cnt); +int iSetMSC_IQM_DEQ_CNT_msc_iqm_deq_cnt(unsigned int umsc_iqm_deq_cnt); +int iSetIQM_NMQNFMQ_ENQ_CNT_iqm_nmqnfmq_enq_cnt(unsigned int uiqm_nmqnfmq_enq_cnt); +int iSetIQM_NMQNFMQ_DEQ_CNT_iqm_nmqnfmq_deq_cnt(unsigned int uiqm_nmqnfmq_deq_cnt); +int iSetIQM_CMQ_ENQ_CNT_iqm_cmq_enq_cnt(unsigned int uiqm_cmq_enq_cnt); +int iSetIQM_CMQ_DEQ_CNT_iqm_cmq_deq_cnt(unsigned int uiqm_cmq_deq_cnt); +int iSetSOC_MSC_IQM_DEQ_CNT_soc_msc_iqm_deq_cnt(unsigned int usoc_msc_iqm_deq_cnt); +int iSetIQM_UNMQ_ENQ_CNT_iqm_unmq_enq_cnt(unsigned int uiqm_unmq_enq_cnt); +int iSetIQM_UNMQ_DEQ_CNT_iqm_unmq_deq_cnt(unsigned int uiqm_unmq_deq_cnt); +int iSetIQM_UCMQ_ENQ_CNT_iqm_ucmq_enq_cnt(unsigned int uiqm_ucmq_enq_cnt); +int iSetIQM_UCMQ_DEQ_CNT_iqm_ucmq_deq_cnt(unsigned int uiqm_ucmq_deq_cnt); +int iSetIQM_RX_CPI_COMP_HOST_SGE_CRDT_CNT_iqm_rx_cpi_host_sge_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_host_sge_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_HOST_DAT_CRDT_CNT_iqm_rx_cpi_host_dat_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_host_dat_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_DP_SGE_CRDT_CNT_iqm_rx_cpi_ep_dp_sge_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_dp_sge_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_CP_SGE_CRDT_CNT_iqm_rx_cpi_ep_cp_sge_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_cp_sge_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_DP_DAT_CRDT_CNT_iqm_rx_cpi_ep_dp_dat_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_dp_dat_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_CP_DAT_CRDT_CNT_iqm_rx_cpi_ep_cp_dat_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_cp_dat_comp_crdt_cnt); +int iSetIQM_RX_QU_COMP_EP_DP_CRDT_CNT_iqm_rx_qu_ep_dp_comp_crdt_cnt(unsigned int uiqm_rx_qu_ep_dp_comp_crdt_cnt); +int iSetIQM_RX_QU_COMP_EP_CP_CRDT_CNT_iqm_rx_qu_ep_cp_comp_crdt_cnt(unsigned int uiqm_rx_qu_ep_cp_comp_crdt_cnt); +int iSetIQM_ECC_1BIT_ERR_CNT_iqm_ecc_1bit_err_cnt(unsigned int uiqm_ecc_1bit_err_cnt); +int iSetIQM_ECC_2BIT_ERR_CNT_iqm_ecc_2bit_err_cnt(unsigned int uiqm_ecc_2bit_err_cnt); + +/* Define the union csr_eqm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv0_u; + +/* Define the union csr_eqm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv1_u; + +/* Define the union csr_eqm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv2_u; + +/* Define the union csr_eqm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv3_u; + +/* Define the union csr_eqm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_indrect_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 eqm_indrect_tab : 4; /* [27:24] */ + u32 eqm_indrect_status : 2; /* [29:28] */ + u32 eqm_indrect_mode : 1; /* [30] */ + u32 eqm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_indrect_ctrl_u; + +/* Define the union csr_eqm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_indrect_timeout_u; + +/* Define the union csr_eqm_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_indrect_data_u; + +/* Define the union csr_eqm_ecqm_bp_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hfifo_bp_bypass : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_bp_bypass_u; + +/* Define the union csr_eqm_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ecc_bypass_en : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ecc_bypass_en_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_eqm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 eqm_enable : 1; /* [27] */ + u32 eqm_int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_int_vector_u; + +/* Define the union csr_eqm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 10; /* [9:0] */ + u32 rsv_6 : 6; /* [15:10] */ + u32 eqm_int_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_int_u; + +/* Define the union csr_eqm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_int_err_en : 10; /* [9:0] */ + u32 rsv_7 : 6; /* [15:10] */ + u32 eqm_int_en_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_int_en_u; + +/* Define the union csr_eqm_mem_ecc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_dwq_free_rsc_err_req : 2; /* [1:0] */ + u32 host_link_err_req : 2; /* [3:2] */ + u32 hfifo_mem_err_req : 2; /* [5:4] */ + u32 host0_ecll_mem_err_req : 2; /* [7:6] */ + u32 host1_ecll_mem_err_req : 2; /* [9:8] */ + u32 host2_ecll_mem_err_req : 2; /* [11:10] */ + u32 host3_ecll_mem_err_req : 2; /* [13:12] */ + u32 head_mem_err_req : 2; /* [15:14] */ + u32 tail_mem_err_req : 2; /* [17:16] */ + u32 link_list_mem_err_req : 2; /* [19:18] */ + u32 ecll_mqlen_err_req : 2; /* [21:20] */ + u32 dmacmd_mem_err_req : 2; /* [23:22] */ + u32 dmard_mem_err_req : 2; /* [25:24] */ + u32 dmawr_mem_err_req : 2; /* [27:26] */ + u32 rsv_8 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ecc_req_u; + +/* Define the union csr_eqm_mem_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_1bit_err : 1; /* [0] */ + u32 eqm_mem_1bit_err_insrt : 1; /* [1] */ + u32 eqm_mem_1bit_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_1bit_err_u; + +/* Define the union csr_eqm_mem_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_2bit_err : 1; /* [0] */ + u32 eqm_mem_2bit_err_insrt : 1; /* [1] */ + u32 eqm_mem_2bit_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_2bit_err_u; + +/* Define the union csr_eqm_ql_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_ql_deq_empty_err : 1; /* [0] */ + u32 eqm_ql_deq_empty_err_insrt : 1; /* [1] */ + u32 eqm_ql_deq_empty_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ql_deq_empty_int_u; + +/* Define the union csr_eqm_cll_fap_exhausted_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_cll_fap_exhuasted_err : 1; /* [0] */ + u32 eqm_cll_fap_exhuasted_err_insrt : 1; /* [1] */ + u32 eqm_cll_fap_exhuasted_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_cll_fap_exhausted_int_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err0 : 1; /* [0] */ + u32 fifo_ovfl_err_insrt0 : 1; /* [1] */ + u32 fifo_ovfl_err1 : 1; /* [2] */ + u32 fifo_ovfl_err_insrt1 : 1; /* [3] */ + u32 fifo_ovfl_err2 : 1; /* [4] */ + u32 fifo_ovfl_err_insrt2 : 1; /* [5] */ + u32 fifo_ovfl_err3 : 1; /* [6] */ + u32 fifo_ovfl_err_insrt3 : 1; /* [7] */ + u32 fifo_ovfl_err4 : 1; /* [8] */ + u32 fifo_ovfl_err_insrt4 : 1; /* [9] */ + u32 fifo_ovfl_err5 : 1; /* [10] */ + u32 fifo_ovfl_err_insrt5 : 1; /* [11] */ + u32 fifo_ovfl_err6 : 1; /* [12] */ + u32 fifo_ovfl_err_insrt6 : 1; /* [13] */ + u32 fifo_ovfl_err7 : 1; /* [14] */ + u32 fifo_ovfl_err_insrt7 : 1; /* [15] */ + u32 fifo_ovfl_err8 : 1; /* [16] */ + u32 fifo_ovfl_err_insrt8 : 1; /* [17] */ + u32 fifo_ovfl_err9 : 1; /* [18] */ + u32 fifo_ovfl_err_insrt9 : 1; /* [19] */ + u32 fifo_ovfl_err10 : 1; /* [20] */ + u32 fifo_ovfl_err_insrt10 : 1; /* [21] */ + u32 fifo_ovfl_err11 : 1; /* [22] */ + u32 fifo_ovfl_err_insrt11 : 1; /* [23] */ + u32 fifo_ovfl_err12 : 1; /* [24] */ + u32 fifo_ovfl_err_insrt12 : 1; /* [25] */ + u32 fifo_ovfl_err13 : 1; /* [26] */ + u32 fifo_ovfl_err_insrt13 : 1; /* [27] */ + u32 fifo_ovfl_err14 : 1; /* [28] */ + u32 fifo_ovfl_err_insrt14 : 1; /* [29] */ + u32 fifo_ovfl_err15 : 1; /* [30] */ + u32 fifo_ovfl_err_insrt15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int0_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int0_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err0_en : 1; /* [0] */ + u32 fifo_ovfl_err1_en : 1; /* [1] */ + u32 fifo_ovfl_err2_en : 1; /* [2] */ + u32 fifo_ovfl_err3_en : 1; /* [3] */ + u32 fifo_ovfl_err4_en : 1; /* [4] */ + u32 fifo_ovfl_err5_en : 1; /* [5] */ + u32 fifo_ovfl_err6_en : 1; /* [6] */ + u32 fifo_ovfl_err7_en : 1; /* [7] */ + u32 fifo_ovfl_err8_en : 1; /* [8] */ + u32 fifo_ovfl_err9_en : 1; /* [9] */ + u32 fifo_ovfl_err10_en : 1; /* [10] */ + u32 fifo_ovfl_err11_en : 1; /* [11] */ + u32 fifo_ovfl_err12_en : 1; /* [12] */ + u32 fifo_ovfl_err13_en : 1; /* [13] */ + u32 fifo_ovfl_err14_en : 1; /* [14] */ + u32 fifo_ovfl_err15_en : 1; /* [15] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int0_en_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err16 : 1; /* [0] */ + u32 fifo_ovfl_err_insrt16 : 1; /* [1] */ + u32 fifo_ovfl_err17 : 1; /* [2] */ + u32 fifo_ovfl_err_insrt17 : 1; /* [3] */ + u32 fifo_ovfl_err18 : 1; /* [4] */ + u32 fifo_ovfl_err_insrt18 : 1; /* [5] */ + u32 fifo_ovfl_err19 : 1; /* [6] */ + u32 fifo_ovfl_err_insrt19 : 1; /* [7] */ + u32 fifo_ovfl_err20 : 1; /* [8] */ + u32 fifo_ovfl_err_insrt20 : 1; /* [9] */ + u32 fifo_ovfl_err21 : 1; /* [10] */ + u32 fifo_ovfl_err_insrt21 : 1; /* [11] */ + u32 fifo_ovfl_err22 : 1; /* [12] */ + u32 fifo_ovfl_err_insrt22 : 1; /* [13] */ + u32 fifo_ovfl_err23 : 1; /* [14] */ + u32 fifo_ovfl_err_insrt23 : 1; /* [15] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int1_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int1_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err16_en : 1; /* [0] */ + u32 fifo_ovfl_err17_en : 1; /* [1] */ + u32 fifo_ovfl_err18_en : 1; /* [2] */ + u32 fifo_ovfl_err19_en : 1; /* [3] */ + u32 fifo_ovfl_err20_en : 1; /* [4] */ + u32 fifo_ovfl_err21_en : 1; /* [5] */ + u32 fifo_ovfl_err22_en : 1; /* [6] */ + u32 fifo_ovfl_err23_en : 1; /* [7] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int1_en_u; + +/* Define the union csr_eqm_fifo_rd_undel_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_underfl_err0 : 1; /* [0] */ + u32 fifo_underfl_err_insrt0 : 1; /* [1] */ + u32 fifo_underfl_err1 : 1; /* [2] */ + u32 fifo_underfl_err_insrt1 : 1; /* [3] */ + u32 fifo_underfl_err2 : 1; /* [4] */ + u32 fifo_underfl_err_insrt2 : 1; /* [5] */ + u32 fifo_underfl_err3 : 1; /* [6] */ + u32 fifo_underfl_err_insrt3 : 1; /* [7] */ + u32 fifo_underfl_err4 : 1; /* [8] */ + u32 fifo_underfl_err_insrt4 : 1; /* [9] */ + u32 fifo_underfl_err5 : 1; /* [10] */ + u32 fifo_underfl_err_insrt5 : 1; /* [11] */ + u32 fifo_underfl_err6 : 1; /* [12] */ + u32 fifo_underfl_err_insrt6 : 1; /* [13] */ + u32 fifo_underfl_err7 : 1; /* [14] */ + u32 fifo_underfl_err_insrt7 : 1; /* [15] */ + u32 fifo_underfl_err8 : 1; /* [16] */ + u32 fifo_underfl_err_insrt8 : 1; /* [17] */ + u32 fifo_underfl_err9 : 1; /* [18] */ + u32 fifo_underfl_err_insrt9 : 1; /* [19] */ + u32 fifo_underfl_err10 : 1; /* [20] */ + u32 fifo_underfl_err_insrt10 : 1; /* [21] */ + u32 fifo_underfl_err11 : 1; /* [22] */ + u32 fifo_underfl_err_insrt11 : 1; /* [23] */ + u32 fifo_underfl_err12 : 1; /* [24] */ + u32 fifo_underfl_err_insrt12 : 1; /* [25] */ + u32 fifo_underfl_err13 : 1; /* [26] */ + u32 fifo_underfl_err_insrt13 : 1; /* [27] */ + u32 fifo_underfl_err14 : 1; /* [28] */ + u32 fifo_underfl_err_insrt14 : 1; /* [29] */ + u32 fifo_underfl_err15 : 1; /* [30] */ + u32 fifo_underfl_err_insrt15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_rd_undel_int_u; + +/* Define the union csr_eqm_fifo_rd_undel_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_underfl_err0_en : 1; /* [0] */ + u32 fifo_underfl_err1_en : 1; /* [1] */ + u32 fifo_underfl_err2_en : 1; /* [2] */ + u32 fifo_underfl_err3_en : 1; /* [3] */ + u32 fifo_underfl_err4_en : 1; /* [4] */ + u32 fifo_underfl_err5_en : 1; /* [5] */ + u32 fifo_underfl_err6_en : 1; /* [6] */ + u32 fifo_underfl_err7_en : 1; /* [7] */ + u32 fifo_underfl_err8_en : 1; /* [8] */ + u32 fifo_underfl_err9_en : 1; /* [9] */ + u32 fifo_underfl_err10_en : 1; /* [10] */ + u32 fifo_underfl_err11_en : 1; /* [11] */ + u32 fifo_underfl_err12_en : 1; /* [12] */ + u32 fifo_underfl_err13_en : 1; /* [13] */ + u32 fifo_underfl_err14_en : 1; /* [14] */ + u32 fifo_underfl_err15_en : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_rd_undel_int_en_u; + +/* Define the union csr_eqm_ring_dfx_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_ring_dfx_err : 1; /* [0] */ + u32 eqm_ring_dfx_err_insrt : 1; /* [1] */ + u32 eqm_ring_dfx_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_dfx_err_int_u; + +/* Define the union csr_eqm_brmatt_rd_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_brmatt_rd_err : 1; /* [0] */ + u32 eqm_brmatt_rd_err_insrt : 1; /* [1] */ + u32 eqm_brmatt_rd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_brmatt_rd_int_u; + +/* Define the union csr_eqm_ring_dfx_err_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_ring_dfx_err1 : 1; /* [0] */ + u32 eqm_ring_dfx_err1_insrt : 1; /* [1] */ + u32 eqm_ring_dfx_err1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_dfx_err_int1_u; + +/* Define the union csr_eqm_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addrtran_rd_uncrt_int_en : 1; /* [0] */ + u32 rsc_exhausted_uncrt_int_en : 1; /* [1] */ + u32 ql_deq_empty_uncrt_int_en : 1; /* [2] */ + u32 rsv_13 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_uncrt_int_en_u; + +/* Define the union csr_eqm_dwq_rsc_dep_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_free_rsc_depth : 9; /* [8:0] */ + u32 rsv_14 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_rsc_dep_cfg_u; + +/* Define the union csr_eqm_pack_channel_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 packing_en : 1; /* [0] */ + u32 packing_num : 3; /* [3:1] */ + u32 packing_pri_en : 8; /* [11:4] */ + u32 packing_aging_time : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_pack_channel_cfg_u; + +/* Define the union csr_eqm_db_store_space_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_overflow_mode : 1; /* [0] */ + u32 rsv_15 : 3; /* [3:1] */ + u32 usr_appoint_host_id : 2; /* [5:4] */ + u32 rsv_16 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_db_store_space_sel_u; + +/* Define the union csr_eqm_host_chunk_num_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_chunk_num : 16; /* [15:0] */ + u32 host1_chunk_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_chunk_num_cfg0_u; + +/* Define the union csr_eqm_host_chunk_num_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_chunk_num : 16; /* [15:0] */ + u32 host3_chunk_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_chunk_num_cfg1_u; + +/* Define the union csr_eqm_page_size_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_page_size : 2; /* [1:0] */ + u32 host1_page_size : 2; /* [3:2] */ + u32 host2_page_size : 2; /* [5:4] */ + u32 host3_page_size : 2; /* [7:6] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_page_size_cfg_u; + +/* Define the union csr_eqm_hostx_dma_channel_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dmard_so_ro : 2; /* [1:0] */ + u32 hostx_dmawr_so_ro : 2; /* [3:2] */ + u32 hostx_dmard_attr_offset : 6; /* [9:4] */ + u32 hostx_dmawr_attr_offset : 6; /* [15:10] */ + u32 hostx_pf_id : 5; /* [20:16] */ + u32 rsv_18 : 3; /* [23:21] */ + u32 hostx_dmard_c_chl : 2; /* [25:24] */ + u32 hostx_dmawr_c_chl : 2; /* [27:26] */ + u32 rsv_19 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_dma_channel_cfg_u; + +/* Define the union csr_eqm_host_search_gpa_baddr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_search_gpa_baddr : 15; /* [14:0] */ + u32 rsv_20 : 1; /* [15] */ + u32 host1_search_gpa_baddr : 15; /* [30:16] */ + u32 rsv_21 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_search_gpa_baddr_cfg0_u; + +/* Define the union csr_eqm_host_search_gpa_baddr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_search_gpa_baddr : 15; /* [14:0] */ + u32 rsv_22 : 1; /* [15] */ + u32 host3_search_gpa_baddr : 15; /* [30:16] */ + u32 rsv_23 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_search_gpa_baddr_cfg1_u; + +/* Define the union csr_eqm_dma_outstd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_outstd_num : 7; /* [6:0] */ + u32 rsv_24 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dma_outstd_num_u; + +/* Define the union csr_eqm_host_dma_outstd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_outstd_num : 7; /* [6:0] */ + u32 rsv_25 : 1; /* [7] */ + u32 host1_outstd_num : 7; /* [14:8] */ + u32 rsv_26 : 1; /* [15] */ + u32 host2_outstd_num : 7; /* [22:16] */ + u32 rsv_27 : 1; /* [23] */ + u32 host3_outstd_num : 7; /* [30:24] */ + u32 rsv_28 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_dma_outstd_num_u; + +/* Define the union csr_eqm_fifo_gap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_enq_aful_gap : 3; /* [2:0] */ + u32 rsv_29 : 1; /* [3] */ + u32 enqc_enq_aful_gap : 3; /* [6:4] */ + u32 rsv_30 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_gap_cfg_u; + +/* Define the union csr_eqm_dwq_inf_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_smm_bp_th : 14; /* [13:0] */ + u32 rsv_31 : 2; /* [15:14] */ + u32 dwq_til_bp_th : 14; /* [29:16] */ + u32 rsv_32 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_inf_th_cfg0_u; + +/* Define the union csr_eqm_dwq_inf_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_cpi_bp_th : 14; /* [13:0] */ + u32 rsv_33 : 2; /* [15:14] */ + u32 dwq_qu_bp_th : 14; /* [29:16] */ + u32 rsv_34 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_inf_th_cfg1_u; + +/* Define the union csr_eqm_dwq_inf_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_sch_bp_th : 14; /* [13:0] */ + u32 rsv_35 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_inf_th_cfg2_u; + +/* Define the union csr_eqm_hostx_cpi_halt_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_cpi_halt_lth : 14; /* [13:0] */ + u32 rsv_36 : 2; /* [15:14] */ + u32 hostx_cpi_halt_hth : 14; /* [29:16] */ + u32 rsv_37 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_cpi_halt_th_cfg_u; + +/* Define the union csr_eqm_host_fifo_depth_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_hfifo_depth : 8; /* [7:0] */ + u32 host1_hfifo_depth : 8; /* [15:8] */ + u32 host2_hfifo_depth : 8; /* [23:16] */ + u32 host3_hfifo_depth : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_fifo_depth_cfg_u; + +/* Define the union csr_eqm_dmard_fifo_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmard_fifo_bp_th : 8; /* [7:0] */ + u32 host1_dmard_fifo_bp_th : 8; /* [15:8] */ + u32 host2_dmard_fifo_bp_th : 8; /* [23:16] */ + u32 host3_dmard_fifo_bp_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmard_fifo_bp_th_u; + +/* Define the union csr_eqm_dmard_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmard_fifo_depth : 9; /* [8:0] */ + u32 rsv_38 : 7; /* [15:9] */ + u32 host1_dmard_fifo_depth : 9; /* [24:16] */ + u32 rsv_39 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmard_fifo_depth0_u; + +/* Define the union csr_eqm_dmard_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmard_fifo_depth : 9; /* [8:0] */ + u32 rsv_40 : 7; /* [15:9] */ + u32 host3_dmard_fifo_depth : 9; /* [24:16] */ + u32 rsv_41 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmard_fifo_depth1_u; + +/* Define the union csr_eqm_dmawr_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmawr_fifo_depth : 9; /* [8:0] */ + u32 rsv_42 : 7; /* [15:9] */ + u32 host1_dmawr_fifo_depth : 9; /* [24:16] */ + u32 rsv_43 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmawr_fifo_depth0_u; + +/* Define the union csr_eqm_dmawr_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmawr_fifo_depth : 9; /* [8:0] */ + u32 rsv_44 : 7; /* [15:9] */ + u32 host3_dmawr_fifo_depth : 9; /* [24:16] */ + u32 rsv_45 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmawr_fifo_depth1_u; + +/* Define the union csr_eqm_dmacmd_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmacmd_fifo_depth : 10; /* [9:0] */ + u32 rsv_46 : 6; /* [15:10] */ + u32 host1_dmacmd_fifo_depth : 10; /* [25:16] */ + u32 rsv_47 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_depth0_u; + +/* Define the union csr_eqm_dmacmd_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmacmd_fifo_depth : 10; /* [9:0] */ + u32 rsv_48 : 6; /* [15:10] */ + u32 host3_dmacmd_fifo_depth : 10; /* [25:16] */ + u32 rsv_49 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_depth1_u; + +/* Define the union csr_eqm_dmacmd_rdfifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmardcmd_fifo_th : 7; /* [6:0] */ + u32 rsv_50 : 1; /* [7] */ + u32 host1_dmardcmd_fifo_th : 7; /* [14:8] */ + u32 rsv_51 : 1; /* [15] */ + u32 host2_dmardcmd_fifo_th : 7; /* [22:16] */ + u32 rsv_52 : 1; /* [23] */ + u32 host3_dmardcmd_fifo_th : 7; /* [30:24] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_rdfifo_th_u; + +/* Define the union csr_eqm_dmacmd_wrfifo_th0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmawrcmd_fifo_aful_th : 9; /* [8:0] */ + u32 rsv_54 : 7; /* [15:9] */ + u32 host1_dmawrcmd_fifo_aful_th : 9; /* [24:16] */ + u32 rsv_55 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_wrfifo_th0_u; + +/* Define the union csr_eqm_dmacmd_wrfifo_th1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmawrcmd_fifo_aful_th : 9; /* [8:0] */ + u32 rsv_56 : 7; /* [15:9] */ + u32 host3_dmawrcmd_fifo_aful_th : 9; /* [24:16] */ + u32 rsv_57 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_wrfifo_th1_u; + +/* Define the union csr_eqm_outstd_fifo_alempty_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 outstd_fifo_ampt_th : 7; /* [6:0] */ + u32 rsv_58 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_outstd_fifo_alempty_th_u; + +/* Define the union csr_eqm_dmacmd_fifo_af_gap0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmacmd_fifo_af_gap : 10; /* [9:0] */ + u32 rsv_59 : 6; /* [15:10] */ + u32 host1_dmacmd_fifo_af_gap : 10; /* [25:16] */ + u32 rsv_60 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_af_gap0_u; + +/* Define the union csr_eqm_dmacmd_fifo_af_gap1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmacmd_fifo_af_gap : 10; /* [9:0] */ + u32 rsv_61 : 6; /* [15:10] */ + u32 host3_dmacmd_fifo_af_gap : 10; /* [25:16] */ + u32 rsv_62 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_af_gap1_u; + +/* Define the union csr_eqm_dmawr_fifo_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmawr_fifo_bp_gap : 8; /* [7:0] */ + u32 host1_dmawr_fifo_bp_gap : 8; /* [15:8] */ + u32 host2_dmawr_fifo_bp_gap : 8; /* [23:16] */ + u32 host3_dmawr_fifo_bp_gap : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmawr_fifo_bp_gap_u; + +/* Define the union csr_eqm_inner_bp_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_enqc_cpi_bp : 1; /* [0] */ + u32 eqm_enqc_tile_bp : 1; /* [1] */ + u32 eqm_enqc_qu_bp : 1; /* [2] */ + u32 rsv_63 : 1; /* [3] */ + u32 mqm_cpi_halt_port : 4; /* [7:4] */ + u32 hfifo_dwqm_bp : 4; /* [11:8] */ + u32 dmacmd_fifo_aful : 4; /* [15:12] */ + u32 host_rdcmd_cnt_aful : 4; /* [19:16] */ + u32 host_wrcmd_cnt_aful : 4; /* [23:20] */ + u32 dmard_fifo_bp : 4; /* [27:24] */ + u32 dmawd_fifo_aful : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_inner_bp_status0_u; + +/* Define the union csr_eqm_inner_bp_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_deqc_root_bp : 1; /* [0] */ + u32 rsv_64 : 3; /* [3:1] */ + u32 eqm_deqc_host_bp : 4; /* [7:4] */ + u32 host_dmard_outstand_bp : 4; /* [11:8] */ + u32 eqm_ring_fifo_aful : 1; /* [12] */ + u32 ring_eqm_fifo_aful : 1; /* [13] */ + u32 eqm_iqm_enq_xoff : 1; /* [14] */ + u32 host_chunk_aempty : 4; /* [18:15] */ + u32 rsv_65 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_inner_bp_status1_u; + +/* Define the union csr_eqm_fifo_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_enq_fifo_dfx : 2; /* [1:0] */ + u32 enqc_enq_fifo_dfx : 2; /* [3:2] */ + u32 dwq_deq_fifo_dfx : 2; /* [5:4] */ + u32 pack_enq_fifo_dfx : 2; /* [7:6] */ + u32 host0_fifo_dfx : 2; /* [9:8] */ + u32 host1_fifo_dfx : 2; /* [11:10] */ + u32 host2_fifo_dfx : 2; /* [13:12] */ + u32 host3_fifo_dfx : 2; /* [15:14] */ + u32 ring_eqm_fifo_dfx : 2; /* [17:16] */ + u32 eqm_ring_fifo_dfx : 2; /* [19:18] */ + u32 dmacmd_infifo_dfx : 2; /* [21:20] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_status0_u; + +/* Define the union csr_eqm_fifo_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dma_wdfifo_dfx : 2; /* [1:0] */ + u32 host1_dma_wdfifo_dfx : 2; /* [3:2] */ + u32 host2_dma_wdfifo_dfx : 2; /* [5:4] */ + u32 host3_dma_wdfifo_dfx : 2; /* [7:6] */ + u32 host0_dma_rdfifo_dfx : 2; /* [9:8] */ + u32 host1_dma_rdfifo_dfx : 2; /* [11:10] */ + u32 host2_dma_rdfifo_dfx : 2; /* [13:12] */ + u32 host3_dma_rdfifo_dfx : 2; /* [15:14] */ + u32 host0_dma_cmdfifo_dfx : 2; /* [17:16] */ + u32 host1_dma_cmdfifo_dfx : 2; /* [19:18] */ + u32 host2_dma_cmdfifo_dfx : 2; /* [21:20] */ + u32 host3_dma_cmdfifo_dfx : 2; /* [23:22] */ + u32 outstd_fifo_dfx : 2; /* [25:24] */ + u32 rsv_67 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_status1_u; + +/* Define the union csr_eqm_ring_dfx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_dfx_err_cnt : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_dfx_err_cnt_u; + +/* Define the union csr_eqm_sm_ovfl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_ovfl_cnt : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_sm_ovfl_cnt_u; + +/* Define the union csr_eqm_dwq_free_addr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_free_addr_cnt : 14; /* [13:0] */ + u32 rsv_70 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_free_addr_cnt_u; + +/* Define the union csr_eqm_dwq_list_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_list_db_cnt : 14; /* [13:0] */ + u32 rsv_71 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_list_db_cnt_u; + +/* Define the union csr_eqm_dwq_hostx_list_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_hostx_list_len : 14; /* [13:0] */ + u32 rsv_72 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_hostx_list_len_u; + +/* Define the union csr_eqm_brmfap_hostx_db_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brmfap_hostx_wr_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_brmfap_hostx_db_eop_cnt_u; + +/* Define the union csr_eqm_nmq_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_db_cnt : 23; /* [22:0] */ + u32 rsv_73 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nmq_db_cnt_u; + +/* Define the union csr_eqm_nmq_hostx_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_hostx_db_cnt : 23; /* [22:0] */ + u32 rsv_74 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nmq_hostx_db_cnt_u; + +/* Define the union csr_eqm_nfmq_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_db_cnt : 23; /* [22:0] */ + u32 rsv_75 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nfmq_db_cnt_u; + +/* Define the union csr_eqm_nfmq_hostx_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_hostx_db_cnt : 23; /* [22:0] */ + u32 rsv_76 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nfmq_hostx_db_cnt_u; + +/* Define the union csr_eqm_hostx_dma_free_addr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_free_rsc_cnt : 16; /* [15:0] */ + u32 rsv_77 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_dma_free_addr_cnt_u; + +/* Define the union csr_eqm_dwq_tile_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_tile_cnt : 14; /* [13:0] */ + u32 rsv_78 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_tile_cnt_u; + +/* Define the union csr_eqm_dwq_sm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_sm_cnt : 14; /* [13:0] */ + u32 rsv_79 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_sm_cnt_u; + +/* Define the union csr_eqm_dwq_qu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_qu_cnt : 14; /* [13:0] */ + u32 rsv_80 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_qu_cnt_u; + +/* Define the union csr_eqm_dwq_cpi_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_cpi_cnt : 14; /* [13:0] */ + u32 rsv_81 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_cpi_cnt_u; + +/* Define the union csr_eqm_dwq_cpi_hostx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dwq_cpi_cnt : 14; /* [13:0] */ + u32 rsv_82 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_cpi_hostx_cnt_u; + +/* Define the union csr_eqm_ecqm_hostx_enq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hostx_enq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_hostx_enq_cmd_cnt_u; + +/* Define the union csr_eqm_ecqm_hostx_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hostx_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_hostx_deq_cmd_cnt_u; + +/* Define the union csr_eqm_ecqm_hostx_sec_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hostx_sec_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_hostx_sec_deq_cmd_cnt_u; + +/* Define the union csr_eqm_dmagen_hostx_wr_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmagen_hostx_enq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmagen_hostx_wr_cmd_cnt_u; + +/* Define the union csr_eqm_dmagen_hostx_rd_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmagen_hostx_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmagen_hostx_rd_cmd_cnt_u; + +/* Define the union csr_eqm_ring_hostx_wr_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_wr_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_hostx_wr_db_cnt_u; + +/* Define the union csr_eqm_ring_hostx_rd_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_rd_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_hostx_rd_db_cnt_u; + +/* Define the union csr_eqm_hostx_enq_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_hostx_enq_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_enq_db_cnt_u; + +/* Define the union csr_eqm_iqm_send_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_iqm_send_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_iqm_send_db_cnt_u; + +/* Define the union csr_eqm_ring_hostx_pre_rd_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_pre_rd_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_hostx_pre_rd_db_cnt_u; + +/* Define the union csr_eqm_dma_outstand_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_outstand_fifo_cnt : 7; /* [6:0] */ + u32 rsv_83 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dma_outstand_dfx0_u; + +/* Define the union csr_eqm_dma_outstand_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dma_outstand_fifo_cnt : 8; /* [7:0] */ + u32 host1_dma_outstand_fifo_cnt : 8; /* [15:8] */ + u32 host2_dma_outstand_fifo_cnt : 8; /* [23:16] */ + u32 host3_dma_outstand_fifo_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dma_outstand_dfx1_u; + +/* Define the union csr_eqm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecc_1bit_err_cnt_u; + +/* Define the union csr_eqm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecc_2bit_err_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_eqm_rw_rsv0_u eqm_rw_rsv0; /* 0 */ + volatile csr_eqm_rw_rsv1_u eqm_rw_rsv1; /* 4 */ + volatile csr_eqm_rw_rsv2_u eqm_rw_rsv2; /* 8 */ + volatile csr_eqm_rw_rsv3_u eqm_rw_rsv3; /* C */ + volatile csr_eqm_indrect_ctrl_u eqm_indrect_ctrl; /* 10 */ + volatile csr_eqm_indrect_timeout_u eqm_indrect_timeout; /* 14 */ + volatile csr_eqm_indrect_data_u eqm_indrect_data; /* 18 */ + volatile csr_eqm_ecqm_bp_bypass_u eqm_ecqm_bp_bypass; /* 1C */ + volatile csr_eqm_mem_ecc_bypass_en_u eqm_mem_ecc_bypass_en; /* 20 */ + volatile csr_eqm_mem_ctrl_bus_cfg0_u eqm_mem_ctrl_bus_cfg0; /* 24 */ + volatile csr_eqm_mem_ctrl_bus_cfg1_u eqm_mem_ctrl_bus_cfg1; /* 28 */ + volatile csr_eqm_mem_ctrl_bus_cfg2_u eqm_mem_ctrl_bus_cfg2; /* 2C */ + volatile csr_eqm_mem_ctrl_bus_cfg3_u eqm_mem_ctrl_bus_cfg3; /* 30 */ + volatile csr_eqm_mem_ctrl_bus_cfg4_u eqm_mem_ctrl_bus_cfg4; /* 34 */ + volatile csr_eqm_int_vector_u eqm_int_vector; /* 40 */ + volatile csr_eqm_int_u eqm_int; /* 44 */ + volatile csr_eqm_int_en_u eqm_int_en; /* 48 */ + volatile csr_eqm_mem_ecc_req_u eqm_mem_ecc_req; /* 4C */ + volatile csr_eqm_mem_1bit_err_u eqm_mem_1bit_err; /* 50 */ + volatile csr_eqm_mem_2bit_err_u eqm_mem_2bit_err; /* 54 */ + volatile csr_eqm_ql_deq_empty_int_u eqm_ql_deq_empty_int; /* 58 */ + volatile csr_eqm_cll_fap_exhausted_int_u eqm_cll_fap_exhausted_int; /* 5C */ + volatile csr_eqm_fifo_wr_ovfl_int0_u eqm_fifo_wr_ovfl_int0; /* 60 */ + volatile csr_eqm_fifo_wr_ovfl_int0_en_u eqm_fifo_wr_ovfl_int0_en; /* 64 */ + volatile csr_eqm_fifo_wr_ovfl_int1_u eqm_fifo_wr_ovfl_int1; /* 68 */ + volatile csr_eqm_fifo_wr_ovfl_int1_en_u eqm_fifo_wr_ovfl_int1_en; /* 6C */ + volatile csr_eqm_fifo_rd_undel_int_u eqm_fifo_rd_undel_int; /* 70 */ + volatile csr_eqm_fifo_rd_undel_int_en_u eqm_fifo_rd_undel_int_en; /* 74 */ + volatile csr_eqm_ring_dfx_err_int_u eqm_ring_dfx_err_int; /* 78 */ + volatile csr_eqm_brmatt_rd_int_u eqm_brmatt_rd_int; /* 7C */ + volatile csr_eqm_ring_dfx_err_int1_u eqm_ring_dfx_err_int1; /* 80 */ + volatile csr_eqm_uncrt_int_en_u eqm_uncrt_int_en; /* 84 */ + volatile csr_eqm_dwq_rsc_dep_cfg_u eqm_dwq_rsc_dep_cfg; /* 800 */ + volatile csr_eqm_pack_channel_cfg_u eqm_pack_channel_cfg; /* 804 */ + volatile csr_eqm_db_store_space_sel_u eqm_db_store_space_sel; /* 808 */ + volatile csr_eqm_host_chunk_num_cfg0_u eqm_host_chunk_num_cfg0; /* 80C */ + volatile csr_eqm_host_chunk_num_cfg1_u eqm_host_chunk_num_cfg1; /* 810 */ + volatile csr_eqm_page_size_cfg_u eqm_page_size_cfg; /* 814 */ + volatile csr_eqm_hostx_dma_channel_cfg_u eqm_hostx_dma_channel_cfg[4]; /* 820 */ + volatile csr_eqm_host_search_gpa_baddr_cfg0_u eqm_host_search_gpa_baddr_cfg0; /* 830 */ + volatile csr_eqm_host_search_gpa_baddr_cfg1_u eqm_host_search_gpa_baddr_cfg1; /* 834 */ + volatile csr_eqm_dma_outstd_num_u eqm_dma_outstd_num; /* 838 */ + volatile csr_eqm_host_dma_outstd_num_u eqm_host_dma_outstd_num; /* 83C */ + volatile csr_eqm_fifo_gap_cfg_u eqm_fifo_gap_cfg; /* 840 */ + volatile csr_eqm_dwq_inf_th_cfg0_u eqm_dwq_inf_th_cfg0; /* 844 */ + volatile csr_eqm_dwq_inf_th_cfg1_u eqm_dwq_inf_th_cfg1; /* 848 */ + volatile csr_eqm_dwq_inf_th_cfg2_u eqm_dwq_inf_th_cfg2; /* 84C */ + volatile csr_eqm_hostx_cpi_halt_th_cfg_u eqm_hostx_cpi_halt_th_cfg[4]; /* 850 */ + volatile csr_eqm_host_fifo_depth_cfg_u eqm_host_fifo_depth_cfg; /* 860 */ + volatile csr_eqm_dmard_fifo_bp_th_u eqm_dmard_fifo_bp_th; /* 864 */ + volatile csr_eqm_dmard_fifo_depth0_u eqm_dmard_fifo_depth0; /* 868 */ + volatile csr_eqm_dmard_fifo_depth1_u eqm_dmard_fifo_depth1; /* 86C */ + volatile csr_eqm_dmawr_fifo_depth0_u eqm_dmawr_fifo_depth0; /* 870 */ + volatile csr_eqm_dmawr_fifo_depth1_u eqm_dmawr_fifo_depth1; /* 874 */ + volatile csr_eqm_dmacmd_fifo_depth0_u eqm_dmacmd_fifo_depth0; /* 878 */ + volatile csr_eqm_dmacmd_fifo_depth1_u eqm_dmacmd_fifo_depth1; /* 87C */ + volatile csr_eqm_dmacmd_rdfifo_th_u eqm_dmacmd_rdfifo_th; /* 880 */ + volatile csr_eqm_dmacmd_wrfifo_th0_u eqm_dmacmd_wrfifo_th0; /* 884 */ + volatile csr_eqm_dmacmd_wrfifo_th1_u eqm_dmacmd_wrfifo_th1; /* 888 */ + volatile csr_eqm_outstd_fifo_alempty_th_u eqm_outstd_fifo_alempty_th; /* 88C */ + volatile csr_eqm_dmacmd_fifo_af_gap0_u eqm_dmacmd_fifo_af_gap0; /* 890 */ + volatile csr_eqm_dmacmd_fifo_af_gap1_u eqm_dmacmd_fifo_af_gap1; /* 894 */ + volatile csr_eqm_dmawr_fifo_bp_gap_u eqm_dmawr_fifo_bp_gap; /* 898 */ + volatile csr_eqm_inner_bp_status0_u eqm_inner_bp_status0; /* 1000 */ + volatile csr_eqm_inner_bp_status1_u eqm_inner_bp_status1; /* 1004 */ + volatile csr_eqm_fifo_status0_u eqm_fifo_status0; /* 1008 */ + volatile csr_eqm_fifo_status1_u eqm_fifo_status1; /* 100C */ + volatile csr_eqm_ring_dfx_err_cnt_u eqm_ring_dfx_err_cnt; /* 1800 */ + volatile csr_eqm_sm_ovfl_cnt_u eqm_sm_ovfl_cnt; /* 1804 */ + volatile csr_eqm_dwq_free_addr_cnt_u eqm_dwq_free_addr_cnt; /* 1808 */ + volatile csr_eqm_dwq_list_db_cnt_u eqm_dwq_list_db_cnt; /* 180C */ + volatile csr_eqm_dwq_hostx_list_len_u eqm_dwq_hostx_list_len[4]; /* 1810 */ + volatile csr_eqm_brmfap_hostx_db_eop_cnt_u eqm_brmfap_hostx_db_eop_cnt[4]; /* 1820 */ + volatile csr_eqm_nmq_db_cnt_u eqm_nmq_db_cnt; /* 1830 */ + volatile csr_eqm_nmq_hostx_db_cnt_u eqm_nmq_hostx_db_cnt[4]; /* 1840 */ + volatile csr_eqm_nfmq_db_cnt_u eqm_nfmq_db_cnt; /* 1850 */ + volatile csr_eqm_nfmq_hostx_db_cnt_u eqm_nfmq_hostx_db_cnt[4]; /* 1860 */ + volatile csr_eqm_hostx_dma_free_addr_cnt_u eqm_hostx_dma_free_addr_cnt[4]; /* 1870 */ + volatile csr_eqm_dwq_tile_cnt_u eqm_dwq_tile_cnt; /* 1880 */ + volatile csr_eqm_dwq_sm_cnt_u eqm_dwq_sm_cnt; /* 1884 */ + volatile csr_eqm_dwq_qu_cnt_u eqm_dwq_qu_cnt; /* 1888 */ + volatile csr_eqm_dwq_cpi_cnt_u eqm_dwq_cpi_cnt; /* 188C */ + volatile csr_eqm_dwq_cpi_hostx_cnt_u eqm_dwq_cpi_hostx_cnt[4]; /* 1890 */ + volatile csr_eqm_ecqm_hostx_enq_cmd_cnt_u eqm_ecqm_hostx_enq_cmd_cnt[4]; /* 18A0 */ + volatile csr_eqm_ecqm_hostx_deq_cmd_cnt_u eqm_ecqm_hostx_deq_cmd_cnt[4]; /* 18B0 */ + volatile csr_eqm_ecqm_hostx_sec_deq_cmd_cnt_u eqm_ecqm_hostx_sec_deq_cmd_cnt[4]; /* 18C0 */ + volatile csr_eqm_dmagen_hostx_wr_cmd_cnt_u eqm_dmagen_hostx_wr_cmd_cnt[4]; /* 18D0 */ + volatile csr_eqm_dmagen_hostx_rd_cmd_cnt_u eqm_dmagen_hostx_rd_cmd_cnt[4]; /* 18E0 */ + volatile csr_eqm_ring_hostx_wr_db_cnt_u eqm_ring_hostx_wr_db_cnt[4]; /* 18F0 */ + volatile csr_eqm_ring_hostx_rd_db_cnt_u eqm_ring_hostx_rd_db_cnt[4]; /* 1900 */ + volatile csr_eqm_hostx_enq_db_cnt_u eqm_hostx_enq_db_cnt[4]; /* 1910 */ + volatile csr_eqm_iqm_send_db_cnt_u eqm_iqm_send_db_cnt; /* 1920 */ + volatile csr_eqm_ring_hostx_pre_rd_db_cnt_u eqm_ring_hostx_pre_rd_db_cnt[4]; /* 1930 */ + volatile csr_eqm_dma_outstand_dfx0_u eqm_dma_outstand_dfx0; /* 1940 */ + volatile csr_eqm_dma_outstand_dfx1_u eqm_dma_outstand_dfx1; /* 1944 */ + volatile csr_eqm_ecc_1bit_err_cnt_u eqm_ecc_1bit_err_cnt; /* 1948 */ + volatile csr_eqm_ecc_2bit_err_cnt_u eqm_ecc_2bit_err_cnt; /* 194C */ +} S_mqm_eqm_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_eqm */ +extern volatile S_mqm_eqm_REGS_TYPE *gopmqm_eqmAllReg; + +/* Declare the functions that set the member value */ +int iSetEQM_RW_RSV0_eqm_rw_rsv0(unsigned int ueqm_rw_rsv0); +int iSetEQM_RW_RSV1_eqm_rw_rsv1(unsigned int ueqm_rw_rsv1); +int iSetEQM_RW_RSV2_eqm_rw_rsv2(unsigned int ueqm_rw_rsv2); +int iSetEQM_RW_RSV3_eqm_rw_rsv3(unsigned int ueqm_rw_rsv3); +int iSetEQM_INDRECT_CTRL_eqm_indrect_addr(unsigned int ueqm_indrect_addr); +int iSetEQM_INDRECT_CTRL_eqm_indrect_tab(unsigned int ueqm_indrect_tab); +int iSetEQM_INDRECT_CTRL_eqm_indrect_status(unsigned int ueqm_indrect_status); +int iSetEQM_INDRECT_CTRL_eqm_indrect_mode(unsigned int ueqm_indrect_mode); +int iSetEQM_INDRECT_CTRL_eqm_indrect_vld(unsigned int ueqm_indrect_vld); +int iSetEQM_INDRECT_TIMEOUT_eqm_indrect_timeout(unsigned int ueqm_indrect_timeout); +int iSetEQM_INDRECT_DATA_eqm_indrect_data(unsigned int ueqm_indrect_data); +int iSetEQM_ECQM_BP_BYPASS_ecqm_hfifo_bp_bypass(unsigned int uecqm_hfifo_bp_bypass); +int iSetEQM_MEM_ECC_BYPASS_EN_eqm_mem_ecc_bypass_en(unsigned int ueqm_mem_ecc_bypass_en); +int iSetEQM_MEM_CTRL_BUS_CFG0_eqm_mem_ctrl_bus_0(unsigned int ueqm_mem_ctrl_bus_0); +int iSetEQM_MEM_CTRL_BUS_CFG1_eqm_mem_ctrl_bus_1(unsigned int ueqm_mem_ctrl_bus_1); +int iSetEQM_MEM_CTRL_BUS_CFG2_eqm_mem_ctrl_bus_2(unsigned int ueqm_mem_ctrl_bus_2); +int iSetEQM_MEM_CTRL_BUS_CFG3_eqm_mem_ctrl_bus_3(unsigned int ueqm_mem_ctrl_bus_3); +int iSetEQM_MEM_CTRL_BUS_CFG4_eqm_mem_ctrl_bus_4(unsigned int ueqm_mem_ctrl_bus_4); +int iSetEQM_INT_VECTOR_eqm_cpi_int_index(unsigned int ueqm_cpi_int_index); +int iSetEQM_INT_VECTOR_eqm_enable(unsigned int ueqm_enable); +int iSetEQM_INT_VECTOR_eqm_int_issue(unsigned int ueqm_int_issue); +int iSetEQM_INT_int_data(unsigned int uint_data); +int iSetEQM_INT_eqm_int_program_csr_id_ro(unsigned int ueqm_int_program_csr_id_ro); +int iSetEQM_INT_EN_eqm_int_err_en(unsigned int ueqm_int_err_en); +int iSetEQM_INT_EN_eqm_int_en_program_csr_id(unsigned int ueqm_int_en_program_csr_id); +int iSetEQM_MEM_ECC_REQ_eqm_dwq_free_rsc_err_req(unsigned int ueqm_dwq_free_rsc_err_req); +int iSetEQM_MEM_ECC_REQ_host_link_err_req(unsigned int uhost_link_err_req); +int iSetEQM_MEM_ECC_REQ_hfifo_mem_err_req(unsigned int uhfifo_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host0_ecll_mem_err_req(unsigned int uhost0_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host1_ecll_mem_err_req(unsigned int uhost1_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host2_ecll_mem_err_req(unsigned int uhost2_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host3_ecll_mem_err_req(unsigned int uhost3_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_head_mem_err_req(unsigned int uhead_mem_err_req); +int iSetEQM_MEM_ECC_REQ_tail_mem_err_req(unsigned int utail_mem_err_req); +int iSetEQM_MEM_ECC_REQ_link_list_mem_err_req(unsigned int ulink_list_mem_err_req); +int iSetEQM_MEM_ECC_REQ_ecll_mqlen_err_req(unsigned int uecll_mqlen_err_req); +int iSetEQM_MEM_ECC_REQ_dmacmd_mem_err_req(unsigned int udmacmd_mem_err_req); +int iSetEQM_MEM_ECC_REQ_dmard_mem_err_req(unsigned int udmard_mem_err_req); +int iSetEQM_MEM_ECC_REQ_dmawr_mem_err_req(unsigned int udmawr_mem_err_req); +int iSetEQM_MEM_1BIT_ERR_eqm_mem_1bit_err(unsigned int ueqm_mem_1bit_err); +int iSetEQM_MEM_1BIT_ERR_eqm_mem_1bit_err_insrt(unsigned int ueqm_mem_1bit_err_insrt); +int iSetEQM_MEM_1BIT_ERR_eqm_mem_1bit_err_sticky(unsigned int ueqm_mem_1bit_err_sticky); +int iSetEQM_MEM_2BIT_ERR_eqm_mem_2bit_err(unsigned int ueqm_mem_2bit_err); +int iSetEQM_MEM_2BIT_ERR_eqm_mem_2bit_err_insrt(unsigned int ueqm_mem_2bit_err_insrt); +int iSetEQM_MEM_2BIT_ERR_eqm_mem_2bit_err_sticky(unsigned int ueqm_mem_2bit_err_sticky); +int iSetEQM_QL_DEQ_EMPTY_INT_eqm_ql_deq_empty_err(unsigned int ueqm_ql_deq_empty_err); +int iSetEQM_QL_DEQ_EMPTY_INT_eqm_ql_deq_empty_err_insrt(unsigned int ueqm_ql_deq_empty_err_insrt); +int iSetEQM_QL_DEQ_EMPTY_INT_eqm_ql_deq_empty_err_sticky(unsigned int ueqm_ql_deq_empty_err_sticky); +int iSetEQM_CLL_FAP_EXHAUSTED_INT_eqm_cll_fap_exhuasted_err(unsigned int ueqm_cll_fap_exhuasted_err); +int iSetEQM_CLL_FAP_EXHAUSTED_INT_eqm_cll_fap_exhuasted_err_insrt(unsigned int ueqm_cll_fap_exhuasted_err_insrt); +int iSetEQM_CLL_FAP_EXHAUSTED_INT_eqm_cll_fap_exhuasted_err_sticky(unsigned int ueqm_cll_fap_exhuasted_err_sticky); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err0(unsigned int ufifo_ovfl_err0); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt0(unsigned int ufifo_ovfl_err_insrt0); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err1(unsigned int ufifo_ovfl_err1); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt1(unsigned int ufifo_ovfl_err_insrt1); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err2(unsigned int ufifo_ovfl_err2); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt2(unsigned int ufifo_ovfl_err_insrt2); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err3(unsigned int ufifo_ovfl_err3); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt3(unsigned int ufifo_ovfl_err_insrt3); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err4(unsigned int ufifo_ovfl_err4); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt4(unsigned int ufifo_ovfl_err_insrt4); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err5(unsigned int ufifo_ovfl_err5); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt5(unsigned int ufifo_ovfl_err_insrt5); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err6(unsigned int ufifo_ovfl_err6); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt6(unsigned int ufifo_ovfl_err_insrt6); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err7(unsigned int ufifo_ovfl_err7); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt7(unsigned int ufifo_ovfl_err_insrt7); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err8(unsigned int ufifo_ovfl_err8); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt8(unsigned int ufifo_ovfl_err_insrt8); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err9(unsigned int ufifo_ovfl_err9); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt9(unsigned int ufifo_ovfl_err_insrt9); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err10(unsigned int ufifo_ovfl_err10); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt10(unsigned int ufifo_ovfl_err_insrt10); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err11(unsigned int ufifo_ovfl_err11); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt11(unsigned int ufifo_ovfl_err_insrt11); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err12(unsigned int ufifo_ovfl_err12); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt12(unsigned int ufifo_ovfl_err_insrt12); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err13(unsigned int ufifo_ovfl_err13); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt13(unsigned int ufifo_ovfl_err_insrt13); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err14(unsigned int ufifo_ovfl_err14); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt14(unsigned int ufifo_ovfl_err_insrt14); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err15(unsigned int ufifo_ovfl_err15); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt15(unsigned int ufifo_ovfl_err_insrt15); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err0_en(unsigned int ufifo_ovfl_err0_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err1_en(unsigned int ufifo_ovfl_err1_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err2_en(unsigned int ufifo_ovfl_err2_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err3_en(unsigned int ufifo_ovfl_err3_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err4_en(unsigned int ufifo_ovfl_err4_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err5_en(unsigned int ufifo_ovfl_err5_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err6_en(unsigned int ufifo_ovfl_err6_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err7_en(unsigned int ufifo_ovfl_err7_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err8_en(unsigned int ufifo_ovfl_err8_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err9_en(unsigned int ufifo_ovfl_err9_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err10_en(unsigned int ufifo_ovfl_err10_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err11_en(unsigned int ufifo_ovfl_err11_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err12_en(unsigned int ufifo_ovfl_err12_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err13_en(unsigned int ufifo_ovfl_err13_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err14_en(unsigned int ufifo_ovfl_err14_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err15_en(unsigned int ufifo_ovfl_err15_en); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err16(unsigned int ufifo_ovfl_err16); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt16(unsigned int ufifo_ovfl_err_insrt16); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err17(unsigned int ufifo_ovfl_err17); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt17(unsigned int ufifo_ovfl_err_insrt17); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err18(unsigned int ufifo_ovfl_err18); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt18(unsigned int ufifo_ovfl_err_insrt18); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err19(unsigned int ufifo_ovfl_err19); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt19(unsigned int ufifo_ovfl_err_insrt19); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err20(unsigned int ufifo_ovfl_err20); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt20(unsigned int ufifo_ovfl_err_insrt20); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err21(unsigned int ufifo_ovfl_err21); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt21(unsigned int ufifo_ovfl_err_insrt21); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err22(unsigned int ufifo_ovfl_err22); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt22(unsigned int ufifo_ovfl_err_insrt22); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err23(unsigned int ufifo_ovfl_err23); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt23(unsigned int ufifo_ovfl_err_insrt23); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err16_en(unsigned int ufifo_ovfl_err16_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err17_en(unsigned int ufifo_ovfl_err17_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err18_en(unsigned int ufifo_ovfl_err18_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err19_en(unsigned int ufifo_ovfl_err19_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err20_en(unsigned int ufifo_ovfl_err20_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err21_en(unsigned int ufifo_ovfl_err21_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err22_en(unsigned int ufifo_ovfl_err22_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err23_en(unsigned int ufifo_ovfl_err23_en); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err0(unsigned int ufifo_underfl_err0); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt0(unsigned int ufifo_underfl_err_insrt0); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err1(unsigned int ufifo_underfl_err1); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt1(unsigned int ufifo_underfl_err_insrt1); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err2(unsigned int ufifo_underfl_err2); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt2(unsigned int ufifo_underfl_err_insrt2); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err3(unsigned int ufifo_underfl_err3); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt3(unsigned int ufifo_underfl_err_insrt3); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err4(unsigned int ufifo_underfl_err4); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt4(unsigned int ufifo_underfl_err_insrt4); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err5(unsigned int ufifo_underfl_err5); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt5(unsigned int ufifo_underfl_err_insrt5); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err6(unsigned int ufifo_underfl_err6); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt6(unsigned int ufifo_underfl_err_insrt6); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err7(unsigned int ufifo_underfl_err7); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt7(unsigned int ufifo_underfl_err_insrt7); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err8(unsigned int ufifo_underfl_err8); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt8(unsigned int ufifo_underfl_err_insrt8); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err9(unsigned int ufifo_underfl_err9); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt9(unsigned int ufifo_underfl_err_insrt9); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err10(unsigned int ufifo_underfl_err10); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt10(unsigned int ufifo_underfl_err_insrt10); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err11(unsigned int ufifo_underfl_err11); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt11(unsigned int ufifo_underfl_err_insrt11); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err12(unsigned int ufifo_underfl_err12); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt12(unsigned int ufifo_underfl_err_insrt12); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err13(unsigned int ufifo_underfl_err13); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt13(unsigned int ufifo_underfl_err_insrt13); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err14(unsigned int ufifo_underfl_err14); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt14(unsigned int ufifo_underfl_err_insrt14); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err15(unsigned int ufifo_underfl_err15); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt15(unsigned int ufifo_underfl_err_insrt15); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err0_en(unsigned int ufifo_underfl_err0_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err1_en(unsigned int ufifo_underfl_err1_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err2_en(unsigned int ufifo_underfl_err2_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err3_en(unsigned int ufifo_underfl_err3_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err4_en(unsigned int ufifo_underfl_err4_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err5_en(unsigned int ufifo_underfl_err5_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err6_en(unsigned int ufifo_underfl_err6_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err7_en(unsigned int ufifo_underfl_err7_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err8_en(unsigned int ufifo_underfl_err8_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err9_en(unsigned int ufifo_underfl_err9_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err10_en(unsigned int ufifo_underfl_err10_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err11_en(unsigned int ufifo_underfl_err11_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err12_en(unsigned int ufifo_underfl_err12_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err13_en(unsigned int ufifo_underfl_err13_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err14_en(unsigned int ufifo_underfl_err14_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err15_en(unsigned int ufifo_underfl_err15_en); +int iSetEQM_RING_DFX_ERR_INT_eqm_ring_dfx_err(unsigned int ueqm_ring_dfx_err); +int iSetEQM_RING_DFX_ERR_INT_eqm_ring_dfx_err_insrt(unsigned int ueqm_ring_dfx_err_insrt); +int iSetEQM_RING_DFX_ERR_INT_eqm_ring_dfx_err_sticky(unsigned int ueqm_ring_dfx_err_sticky); +int iSetEQM_BRMATT_RD_INT_eqm_brmatt_rd_err(unsigned int ueqm_brmatt_rd_err); +int iSetEQM_BRMATT_RD_INT_eqm_brmatt_rd_err_insrt(unsigned int ueqm_brmatt_rd_err_insrt); +int iSetEQM_BRMATT_RD_INT_eqm_brmatt_rd_err_sticky(unsigned int ueqm_brmatt_rd_err_sticky); +int iSetEQM_RING_DFX_ERR_INT1_eqm_ring_dfx_err1(unsigned int ueqm_ring_dfx_err1); +int iSetEQM_RING_DFX_ERR_INT1_eqm_ring_dfx_err1_insrt(unsigned int ueqm_ring_dfx_err1_insrt); +int iSetEQM_RING_DFX_ERR_INT1_eqm_ring_dfx_err1_sticky(unsigned int ueqm_ring_dfx_err1_sticky); +int iSetEQM_UNCRT_INT_EN_addrtran_rd_uncrt_int_en(unsigned int uaddrtran_rd_uncrt_int_en); +int iSetEQM_UNCRT_INT_EN_rsc_exhausted_uncrt_int_en(unsigned int ursc_exhausted_uncrt_int_en); +int iSetEQM_UNCRT_INT_EN_ql_deq_empty_uncrt_int_en(unsigned int uql_deq_empty_uncrt_int_en); +int iSetEQM_DWQ_RSC_DEP_CFG_dwq_free_rsc_depth(unsigned int udwq_free_rsc_depth); +int iSetEQM_PACK_CHANNEL_CFG_packing_en(unsigned int upacking_en); +int iSetEQM_PACK_CHANNEL_CFG_packing_num(unsigned int upacking_num); +int iSetEQM_PACK_CHANNEL_CFG_packing_pri_en(unsigned int upacking_pri_en); +int iSetEQM_PACK_CHANNEL_CFG_packing_aging_time(unsigned int upacking_aging_time); +int iSetEQM_DB_STORE_SPACE_SEL_db_overflow_mode(unsigned int udb_overflow_mode); +int iSetEQM_DB_STORE_SPACE_SEL_usr_appoint_host_id(unsigned int uusr_appoint_host_id); +int iSetEQM_HOST_CHUNK_NUM_CFG0_host0_chunk_num(unsigned int uhost0_chunk_num); +int iSetEQM_HOST_CHUNK_NUM_CFG0_host1_chunk_num(unsigned int uhost1_chunk_num); +int iSetEQM_HOST_CHUNK_NUM_CFG1_host2_chunk_num(unsigned int uhost2_chunk_num); +int iSetEQM_HOST_CHUNK_NUM_CFG1_host3_chunk_num(unsigned int uhost3_chunk_num); +int iSetEQM_PAGE_SIZE_CFG_host0_page_size(unsigned int uhost0_page_size); +int iSetEQM_PAGE_SIZE_CFG_host1_page_size(unsigned int uhost1_page_size); +int iSetEQM_PAGE_SIZE_CFG_host2_page_size(unsigned int uhost2_page_size); +int iSetEQM_PAGE_SIZE_CFG_host3_page_size(unsigned int uhost3_page_size); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmard_so_ro(unsigned int uhostx_dmard_so_ro); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmawr_so_ro(unsigned int uhostx_dmawr_so_ro); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmard_attr_offset(unsigned int uhostx_dmard_attr_offset); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmawr_attr_offset(unsigned int uhostx_dmawr_attr_offset); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_pf_id(unsigned int uhostx_pf_id); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmard_c_chl(unsigned int uhostx_dmard_c_chl); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmawr_c_chl(unsigned int uhostx_dmawr_c_chl); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG0_host0_search_gpa_baddr(unsigned int uhost0_search_gpa_baddr); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG0_host1_search_gpa_baddr(unsigned int uhost1_search_gpa_baddr); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG1_host2_search_gpa_baddr(unsigned int uhost2_search_gpa_baddr); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG1_host3_search_gpa_baddr(unsigned int uhost3_search_gpa_baddr); +int iSetEQM_DMA_OUTSTD_NUM_dma_outstd_num(unsigned int udma_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host0_outstd_num(unsigned int uhost0_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host1_outstd_num(unsigned int uhost1_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host2_outstd_num(unsigned int uhost2_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host3_outstd_num(unsigned int uhost3_outstd_num); +int iSetEQM_FIFO_GAP_CFG_iqm_enq_aful_gap(unsigned int uiqm_enq_aful_gap); +int iSetEQM_FIFO_GAP_CFG_enqc_enq_aful_gap(unsigned int uenqc_enq_aful_gap); +int iSetEQM_DWQ_INF_TH_CFG0_dwq_smm_bp_th(unsigned int udwq_smm_bp_th); +int iSetEQM_DWQ_INF_TH_CFG0_dwq_til_bp_th(unsigned int udwq_til_bp_th); +int iSetEQM_DWQ_INF_TH_CFG1_dwq_cpi_bp_th(unsigned int udwq_cpi_bp_th); +int iSetEQM_DWQ_INF_TH_CFG1_dwq_qu_bp_th(unsigned int udwq_qu_bp_th); +int iSetEQM_DWQ_INF_TH_CFG2_dwq_sch_bp_th(unsigned int udwq_sch_bp_th); +int iSetEQM_HOSTX_CPI_HALT_TH_CFG_hostx_cpi_halt_lth(unsigned int uhostx_cpi_halt_lth); +int iSetEQM_HOSTX_CPI_HALT_TH_CFG_hostx_cpi_halt_hth(unsigned int uhostx_cpi_halt_hth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host0_hfifo_depth(unsigned int uhost0_hfifo_depth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host1_hfifo_depth(unsigned int uhost1_hfifo_depth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host2_hfifo_depth(unsigned int uhost2_hfifo_depth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host3_hfifo_depth(unsigned int uhost3_hfifo_depth); +int iSetEQM_DMARD_FIFO_BP_TH_host0_dmard_fifo_bp_th(unsigned int uhost0_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_BP_TH_host1_dmard_fifo_bp_th(unsigned int uhost1_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_BP_TH_host2_dmard_fifo_bp_th(unsigned int uhost2_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_BP_TH_host3_dmard_fifo_bp_th(unsigned int uhost3_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_DEPTH0_host0_dmard_fifo_depth(unsigned int uhost0_dmard_fifo_depth); +int iSetEQM_DMARD_FIFO_DEPTH0_host1_dmard_fifo_depth(unsigned int uhost1_dmard_fifo_depth); +int iSetEQM_DMARD_FIFO_DEPTH1_host2_dmard_fifo_depth(unsigned int uhost2_dmard_fifo_depth); +int iSetEQM_DMARD_FIFO_DEPTH1_host3_dmard_fifo_depth(unsigned int uhost3_dmard_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH0_host0_dmawr_fifo_depth(unsigned int uhost0_dmawr_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH0_host1_dmawr_fifo_depth(unsigned int uhost1_dmawr_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH1_host2_dmawr_fifo_depth(unsigned int uhost2_dmawr_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH1_host3_dmawr_fifo_depth(unsigned int uhost3_dmawr_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH0_host0_dmacmd_fifo_depth(unsigned int uhost0_dmacmd_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH0_host1_dmacmd_fifo_depth(unsigned int uhost1_dmacmd_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH1_host2_dmacmd_fifo_depth(unsigned int uhost2_dmacmd_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH1_host3_dmacmd_fifo_depth(unsigned int uhost3_dmacmd_fifo_depth); +int iSetEQM_DMACMD_RDFIFO_TH_host0_dmardcmd_fifo_th(unsigned int uhost0_dmardcmd_fifo_th); +int iSetEQM_DMACMD_RDFIFO_TH_host1_dmardcmd_fifo_th(unsigned int uhost1_dmardcmd_fifo_th); +int iSetEQM_DMACMD_RDFIFO_TH_host2_dmardcmd_fifo_th(unsigned int uhost2_dmardcmd_fifo_th); +int iSetEQM_DMACMD_RDFIFO_TH_host3_dmardcmd_fifo_th(unsigned int uhost3_dmardcmd_fifo_th); +int iSetEQM_DMACMD_WRFIFO_TH0_host0_dmawrcmd_fifo_aful_th(unsigned int uhost0_dmawrcmd_fifo_aful_th); +int iSetEQM_DMACMD_WRFIFO_TH0_host1_dmawrcmd_fifo_aful_th(unsigned int uhost1_dmawrcmd_fifo_aful_th); +int iSetEQM_DMACMD_WRFIFO_TH1_host2_dmawrcmd_fifo_aful_th(unsigned int uhost2_dmawrcmd_fifo_aful_th); +int iSetEQM_DMACMD_WRFIFO_TH1_host3_dmawrcmd_fifo_aful_th(unsigned int uhost3_dmawrcmd_fifo_aful_th); +int iSetEQM_OUTSTD_FIFO_ALEMPTY_TH_outstd_fifo_ampt_th(unsigned int uoutstd_fifo_ampt_th); +int iSetEQM_DMACMD_FIFO_AF_GAP0_host0_dmacmd_fifo_af_gap(unsigned int uhost0_dmacmd_fifo_af_gap); +int iSetEQM_DMACMD_FIFO_AF_GAP0_host1_dmacmd_fifo_af_gap(unsigned int uhost1_dmacmd_fifo_af_gap); +int iSetEQM_DMACMD_FIFO_AF_GAP1_host2_dmacmd_fifo_af_gap(unsigned int uhost2_dmacmd_fifo_af_gap); +int iSetEQM_DMACMD_FIFO_AF_GAP1_host3_dmacmd_fifo_af_gap(unsigned int uhost3_dmacmd_fifo_af_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host0_dmawr_fifo_bp_gap(unsigned int uhost0_dmawr_fifo_bp_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host1_dmawr_fifo_bp_gap(unsigned int uhost1_dmawr_fifo_bp_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host2_dmawr_fifo_bp_gap(unsigned int uhost2_dmawr_fifo_bp_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host3_dmawr_fifo_bp_gap(unsigned int uhost3_dmawr_fifo_bp_gap); +int iSetEQM_INNER_BP_STATUS0_eqm_enqc_cpi_bp(unsigned int ueqm_enqc_cpi_bp); +int iSetEQM_INNER_BP_STATUS0_eqm_enqc_tile_bp(unsigned int ueqm_enqc_tile_bp); +int iSetEQM_INNER_BP_STATUS0_eqm_enqc_qu_bp(unsigned int ueqm_enqc_qu_bp); +int iSetEQM_INNER_BP_STATUS0_mqm_cpi_halt_port(unsigned int umqm_cpi_halt_port); +int iSetEQM_INNER_BP_STATUS0_hfifo_dwqm_bp(unsigned int uhfifo_dwqm_bp); +int iSetEQM_INNER_BP_STATUS0_dmacmd_fifo_aful(unsigned int udmacmd_fifo_aful); +int iSetEQM_INNER_BP_STATUS0_host_rdcmd_cnt_aful(unsigned int uhost_rdcmd_cnt_aful); +int iSetEQM_INNER_BP_STATUS0_host_wrcmd_cnt_aful(unsigned int uhost_wrcmd_cnt_aful); +int iSetEQM_INNER_BP_STATUS0_dmard_fifo_bp(unsigned int udmard_fifo_bp); +int iSetEQM_INNER_BP_STATUS0_dmawd_fifo_aful(unsigned int udmawd_fifo_aful); +int iSetEQM_INNER_BP_STATUS1_eqm_deqc_root_bp(unsigned int ueqm_deqc_root_bp); +int iSetEQM_INNER_BP_STATUS1_eqm_deqc_host_bp(unsigned int ueqm_deqc_host_bp); +int iSetEQM_INNER_BP_STATUS1_host_dmard_outstand_bp(unsigned int uhost_dmard_outstand_bp); +int iSetEQM_INNER_BP_STATUS1_eqm_ring_fifo_aful(unsigned int ueqm_ring_fifo_aful); +int iSetEQM_INNER_BP_STATUS1_ring_eqm_fifo_aful(unsigned int uring_eqm_fifo_aful); +int iSetEQM_INNER_BP_STATUS1_eqm_iqm_enq_xoff(unsigned int ueqm_iqm_enq_xoff); +int iSetEQM_INNER_BP_STATUS1_host_chunk_aempty(unsigned int uhost_chunk_aempty); +int iSetEQM_FIFO_STATUS0_iqm_enq_fifo_dfx(unsigned int uiqm_enq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_enqc_enq_fifo_dfx(unsigned int uenqc_enq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_dwq_deq_fifo_dfx(unsigned int udwq_deq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_pack_enq_fifo_dfx(unsigned int upack_enq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host0_fifo_dfx(unsigned int uhost0_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host1_fifo_dfx(unsigned int uhost1_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host2_fifo_dfx(unsigned int uhost2_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host3_fifo_dfx(unsigned int uhost3_fifo_dfx); +int iSetEQM_FIFO_STATUS0_ring_eqm_fifo_dfx(unsigned int uring_eqm_fifo_dfx); +int iSetEQM_FIFO_STATUS0_eqm_ring_fifo_dfx(unsigned int ueqm_ring_fifo_dfx); +int iSetEQM_FIFO_STATUS0_dmacmd_infifo_dfx(unsigned int udmacmd_infifo_dfx); +int iSetEQM_FIFO_STATUS1_host0_dma_wdfifo_dfx(unsigned int uhost0_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host1_dma_wdfifo_dfx(unsigned int uhost1_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host2_dma_wdfifo_dfx(unsigned int uhost2_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host3_dma_wdfifo_dfx(unsigned int uhost3_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host0_dma_rdfifo_dfx(unsigned int uhost0_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host1_dma_rdfifo_dfx(unsigned int uhost1_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host2_dma_rdfifo_dfx(unsigned int uhost2_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host3_dma_rdfifo_dfx(unsigned int uhost3_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host0_dma_cmdfifo_dfx(unsigned int uhost0_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host1_dma_cmdfifo_dfx(unsigned int uhost1_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host2_dma_cmdfifo_dfx(unsigned int uhost2_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host3_dma_cmdfifo_dfx(unsigned int uhost3_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_outstd_fifo_dfx(unsigned int uoutstd_fifo_dfx); +int iSetEQM_RING_DFX_ERR_CNT_ring_dfx_err_cnt(unsigned int uring_dfx_err_cnt); +int iSetEQM_SM_OVFL_CNT_sm_ovfl_cnt(unsigned int usm_ovfl_cnt); +int iSetEQM_DWQ_FREE_ADDR_CNT_dwq_free_addr_cnt(unsigned int udwq_free_addr_cnt); +int iSetEQM_DWQ_LIST_DB_CNT_dwq_list_db_cnt(unsigned int udwq_list_db_cnt); +int iSetEQM_DWQ_HOSTX_LIST_LEN_dwq_hostx_list_len(unsigned int udwq_hostx_list_len); +int iSetEQM_BRMFAP_HOSTX_DB_EOP_CNT_brmfap_hostx_wr_eop_cnt(unsigned int ubrmfap_hostx_wr_eop_cnt); +int iSetEQM_NMQ_DB_CNT_nmq_db_cnt(unsigned int unmq_db_cnt); +int iSetEQM_NMQ_HOSTX_DB_CNT_nmq_hostx_db_cnt(unsigned int unmq_hostx_db_cnt); +int iSetEQM_NFMQ_DB_CNT_nfmq_db_cnt(unsigned int unfmq_db_cnt); +int iSetEQM_NFMQ_HOSTX_DB_CNT_nfmq_hostx_db_cnt(unsigned int unfmq_hostx_db_cnt); +int iSetEQM_HOSTX_DMA_FREE_ADDR_CNT_hostx_dma_free_rsc_cnt(unsigned int uhostx_dma_free_rsc_cnt); +int iSetEQM_DWQ_TILE_CNT_dwq_tile_cnt(unsigned int udwq_tile_cnt); +int iSetEQM_DWQ_SM_CNT_dwq_sm_cnt(unsigned int udwq_sm_cnt); +int iSetEQM_DWQ_QU_CNT_dwq_qu_cnt(unsigned int udwq_qu_cnt); +int iSetEQM_DWQ_CPI_CNT_dwq_cpi_cnt(unsigned int udwq_cpi_cnt); +int iSetEQM_DWQ_CPI_HOSTX_CNT_hostx_dwq_cpi_cnt(unsigned int uhostx_dwq_cpi_cnt); +int iSetEQM_ECQM_HOSTX_ENQ_CMD_CNT_ecqm_hostx_enq_cmd_cnt(unsigned int uecqm_hostx_enq_cmd_cnt); +int iSetEQM_ECQM_HOSTX_DEQ_CMD_CNT_ecqm_hostx_deq_cmd_cnt(unsigned int uecqm_hostx_deq_cmd_cnt); +int iSetEQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_ecqm_hostx_sec_deq_cmd_cnt(unsigned int uecqm_hostx_sec_deq_cmd_cnt); +int iSetEQM_DMAGEN_HOSTX_WR_CMD_CNT_dmagen_hostx_enq_cmd_cnt(unsigned int udmagen_hostx_enq_cmd_cnt); +int iSetEQM_DMAGEN_HOSTX_RD_CMD_CNT_dmagen_hostx_deq_cmd_cnt(unsigned int udmagen_hostx_deq_cmd_cnt); +int iSetEQM_RING_HOSTX_WR_DB_CNT_hostx_dma_wr_db_cnt(unsigned int uhostx_dma_wr_db_cnt); +int iSetEQM_RING_HOSTX_RD_DB_CNT_hostx_dma_rd_db_cnt(unsigned int uhostx_dma_rd_db_cnt); +int iSetEQM_HOSTX_ENQ_DB_CNT_eqm_hostx_enq_db_cnt(unsigned int ueqm_hostx_enq_db_cnt); +int iSetEQM_IQM_SEND_DB_CNT_eqm_iqm_send_db_cnt(unsigned int ueqm_iqm_send_db_cnt); +int iSetEQM_RING_HOSTX_PRE_RD_DB_CNT_hostx_dma_pre_rd_db_cnt(unsigned int uhostx_dma_pre_rd_db_cnt); +int iSetEQM_DMA_OUTSTAND_DFX0_dma_outstand_fifo_cnt(unsigned int udma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host0_dma_outstand_fifo_cnt(unsigned int uhost0_dma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host1_dma_outstand_fifo_cnt(unsigned int uhost1_dma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host2_dma_outstand_fifo_cnt(unsigned int uhost2_dma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host3_dma_outstand_fifo_cnt(unsigned int uhost3_dma_outstand_fifo_cnt); +int iSetEQM_ECC_1BIT_ERR_CNT_ecc_1bit_err_cnt(unsigned int uecc_1bit_err_cnt); +int iSetEQM_ECC_2BIT_ERR_CNT_ecc_2bit_err_cnt(unsigned int uecc_2bit_err_cnt); + +/* Define the union csr_msc_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv0_u; + +/* Define the union csr_msc_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv1_u; + +/* Define the union csr_msc_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv2_u; + +/* Define the union csr_msc_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv3_u; + +/* Define the union csr_msc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_addr : 20; /* [19:0] */ + u32 msc_indrect_tab : 8; /* [27:20] */ + u32 msc_indrect_stat : 2; /* [29:28] */ + u32 msc_indrect_mode : 1; /* [30] */ + u32 msc_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_ctrl_u; + +/* Define the union csr_msc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_timeout_u; + +/* Define the union csr_msc_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_data_0_u; + +/* Define the union csr_msc_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_data_1_u; + +/* Define the union csr_msc_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ecc_bypass_en_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_msc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 msc_enable : 1; /* [27] */ + u32 msc_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_int_vector_u; + +/* Define the union csr_msc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_int_data : 15; /* [14:0] */ + u32 rsv_4 : 1; /* [15] */ + u32 msc_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_int_u; + +/* Define the union csr_msc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_int_en : 15; /* [14:0] */ + u32 rsv_5 : 1; /* [15] */ + u32 msc_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_int_en_u; + +/* Define the union csr_msc_mem_err_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_0 : 1; /* [0] */ + u32 msc_mem_err_req_1 : 1; /* [1] */ + u32 msc_mem_err_req_2 : 1; /* [2] */ + u32 msc_mem_err_req_3 : 1; /* [3] */ + u32 msc_mem_err_req_4 : 1; /* [4] */ + u32 msc_mem_err_req_5 : 1; /* [5] */ + u32 msc_mem_err_req_6 : 1; /* [6] */ + u32 msc_mem_err_req_7 : 1; /* [7] */ + u32 msc_mem_err_req_8 : 1; /* [8] */ + u32 msc_mem_err_req_9 : 1; /* [9] */ + u32 msc_mem_err_req_10 : 1; /* [10] */ + u32 msc_mem_err_req_11 : 1; /* [11] */ + u32 msc_mem_err_req_12 : 1; /* [12] */ + u32 msc_mem_err_req_13 : 1; /* [13] */ + u32 msc_mem_err_req_14 : 1; /* [14] */ + u32 msc_mem_err_req_15 : 1; /* [15] */ + u32 msc_mem_err_req_16 : 1; /* [16] */ + u32 msc_mem_err_req_17 : 1; /* [17] */ + u32 msc_mem_err_req_18 : 1; /* [18] */ + u32 msc_mem_err_req_19 : 1; /* [19] */ + u32 msc_mem_err_req_20 : 1; /* [20] */ + u32 msc_mem_err_req_21 : 1; /* [21] */ + u32 msc_mem_err_req_22 : 1; /* [22] */ + u32 msc_mem_err_req_23 : 1; /* [23] */ + u32 msc_mem_err_req_24 : 1; /* [24] */ + u32 msc_mem_err_req_25 : 1; /* [25] */ + u32 msc_mem_err_req_26 : 1; /* [26] */ + u32 msc_mem_err_req_27 : 1; /* [27] */ + u32 msc_mem_err_req_28 : 1; /* [28] */ + u32 msc_mem_err_req_29 : 1; /* [29] */ + u32 rsv_6 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req0_u; + +/* Define the union csr_msc_mem_err_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_32 : 1; /* [0] */ + u32 msc_mem_err_req_33 : 1; /* [1] */ + u32 msc_mem_err_req_34 : 1; /* [2] */ + u32 msc_mem_err_req_35 : 1; /* [3] */ + u32 msc_mem_err_req_36 : 1; /* [4] */ + u32 msc_mem_err_req_37 : 1; /* [5] */ + u32 msc_mem_err_req_38 : 1; /* [6] */ + u32 msc_mem_err_req_39 : 1; /* [7] */ + u32 msc_mem_err_req_40 : 1; /* [8] */ + u32 msc_mem_err_req_41 : 1; /* [9] */ + u32 msc_mem_err_req_42 : 1; /* [10] */ + u32 msc_mem_err_req_43 : 1; /* [11] */ + u32 msc_mem_err_req_44 : 1; /* [12] */ + u32 msc_mem_err_req_45 : 1; /* [13] */ + u32 msc_mem_err_req_46 : 1; /* [14] */ + u32 msc_mem_err_req_47 : 1; /* [15] */ + u32 msc_mem_err_req_48 : 1; /* [16] */ + u32 msc_mem_err_req_49 : 1; /* [17] */ + u32 msc_mem_err_req_50 : 1; /* [18] */ + u32 msc_mem_err_req_51 : 1; /* [19] */ + u32 msc_mem_err_req_52 : 1; /* [20] */ + u32 msc_mem_err_req_53 : 1; /* [21] */ + u32 msc_mem_err_req_54 : 1; /* [22] */ + u32 msc_mem_err_req_55 : 1; /* [23] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req1_u; + +/* Define the union csr_msc_mem_err_req2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_64 : 1; /* [0] */ + u32 msc_mem_err_req_65 : 1; /* [1] */ + u32 msc_mem_err_req_66 : 1; /* [2] */ + u32 msc_mem_err_req_67 : 1; /* [3] */ + u32 msc_mem_err_req_68 : 1; /* [4] */ + u32 msc_mem_err_req_69 : 1; /* [5] */ + u32 msc_mem_err_req_70 : 1; /* [6] */ + u32 msc_mem_err_req_71 : 1; /* [7] */ + u32 msc_mem_err_req_72 : 1; /* [8] */ + u32 msc_mem_err_req_73 : 1; /* [9] */ + u32 msc_mem_err_req_74 : 1; /* [10] */ + u32 msc_mem_err_req_75 : 1; /* [11] */ + u32 msc_mem_err_req_76 : 1; /* [12] */ + u32 msc_mem_err_req_77 : 1; /* [13] */ + u32 msc_mem_err_req_78 : 1; /* [14] */ + u32 msc_mem_err_req_79 : 1; /* [15] */ + u32 msc_mem_err_req_80 : 1; /* [16] */ + u32 msc_mem_err_req_81 : 1; /* [17] */ + u32 msc_mem_err_req_82 : 1; /* [18] */ + u32 msc_mem_err_req_83 : 1; /* [19] */ + u32 msc_mem_err_req_84 : 1; /* [20] */ + u32 msc_mem_err_req_85 : 1; /* [21] */ + u32 msc_mem_err_req_86 : 1; /* [22] */ + u32 msc_mem_err_req_87 : 1; /* [23] */ + u32 msc_mem_err_req_88 : 1; /* [24] */ + u32 msc_mem_err_req_89 : 1; /* [25] */ + u32 msc_mem_err_req_90 : 1; /* [26] */ + u32 msc_mem_err_req_91 : 1; /* [27] */ + u32 msc_mem_err_req_92 : 1; /* [28] */ + u32 msc_mem_err_req_93 : 1; /* [29] */ + u32 msc_mem_err_req_94 : 1; /* [30] */ + u32 msc_mem_err_req_95 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req2_u; + +/* Define the union csr_msc_mem_err_req3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_96 : 1; /* [0] */ + u32 msc_mem_err_req_97 : 1; /* [1] */ + u32 msc_mem_err_req_98 : 1; /* [2] */ + u32 msc_mem_err_req_99 : 1; /* [3] */ + u32 msc_mem_err_req_100 : 1; /* [4] */ + u32 msc_mem_err_req_101 : 1; /* [5] */ + u32 msc_mem_err_req_102 : 1; /* [6] */ + u32 msc_mem_err_req_103 : 1; /* [7] */ + u32 msc_mem_err_req_104 : 1; /* [8] */ + u32 msc_mem_err_req_105 : 1; /* [9] */ + u32 msc_mem_err_req_106 : 1; /* [10] */ + u32 msc_mem_err_req_107 : 1; /* [11] */ + u32 msc_mem_err_req_108 : 1; /* [12] */ + u32 msc_mem_err_req_109 : 1; /* [13] */ + u32 msc_mem_err_req_110 : 1; /* [14] */ + u32 msc_mem_err_req_111 : 1; /* [15] */ + u32 msc_mem_err_req_112 : 1; /* [16] */ + u32 msc_mem_err_req_113 : 1; /* [17] */ + u32 msc_mem_err_req_114 : 1; /* [18] */ + u32 msc_mem_err_req_115 : 1; /* [19] */ + u32 msc_mem_err_req_116 : 1; /* [20] */ + u32 msc_mem_err_req_117 : 1; /* [21] */ + u32 msc_mem_err_req_118 : 1; /* [22] */ + u32 msc_mem_err_req_119 : 1; /* [23] */ + u32 msc_mem_err_req_120 : 1; /* [24] */ + u32 msc_mem_err_req_121 : 1; /* [25] */ + u32 msc_mem_err_req_122 : 1; /* [26] */ + u32 msc_mem_err_req_123 : 1; /* [27] */ + u32 msc_mem_err_req_124 : 1; /* [28] */ + u32 msc_mem_err_req_125 : 1; /* [29] */ + u32 msc_mem_err_req_126 : 1; /* [30] */ + u32 msc_mem_err_req_127 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req3_u; + +/* Define the union csr_msc_mem_err_req4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_128 : 1; /* [0] */ + u32 msc_mem_err_req_129 : 1; /* [1] */ + u32 msc_mem_err_req_130 : 1; /* [2] */ + u32 msc_mem_err_req_131 : 1; /* [3] */ + u32 msc_mem_err_req_132 : 1; /* [4] */ + u32 msc_mem_err_req_133 : 1; /* [5] */ + u32 msc_mem_err_req_134 : 1; /* [6] */ + u32 msc_mem_err_req_135 : 1; /* [7] */ + u32 msc_mem_err_req_136 : 1; /* [8] */ + u32 msc_mem_err_req_137 : 1; /* [9] */ + u32 msc_mem_err_req_138 : 1; /* [10] */ + u32 msc_mem_err_req_139 : 1; /* [11] */ + u32 msc_mem_err_req_140 : 1; /* [12] */ + u32 msc_mem_err_req_141 : 1; /* [13] */ + u32 msc_mem_err_req_142 : 1; /* [14] */ + u32 msc_mem_err_req_143 : 1; /* [15] */ + u32 msc_mem_err_req_144 : 1; /* [16] */ + u32 msc_mem_err_req_145 : 1; /* [17] */ + u32 msc_mem_err_req_146 : 1; /* [18] */ + u32 msc_mem_err_req_147 : 1; /* [19] */ + u32 msc_mem_err_req_148 : 1; /* [20] */ + u32 msc_mem_err_req_149 : 1; /* [21] */ + u32 msc_mem_err_req_150 : 1; /* [22] */ + u32 msc_mem_err_req_151 : 1; /* [23] */ + u32 msc_mem_err_req_152 : 1; /* [24] */ + u32 msc_mem_err_req_153 : 1; /* [25] */ + u32 msc_mem_err_req_154 : 1; /* [26] */ + u32 msc_mem_err_req_155 : 1; /* [27] */ + u32 msc_mem_err_req_156 : 1; /* [28] */ + u32 msc_mem_err_req_157 : 1; /* [29] */ + u32 rsv_8 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req4_u; + +/* Define the union csr_msc_ecc_one_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_1bit_err : 1; /* [0] */ + u32 msc_ecc_1bit_err_insrt : 1; /* [1] */ + u32 msc_ecc_1bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_one_bit_int_u; + +/* Define the union csr_msc_ecc_two_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_2bit_err : 1; /* [0] */ + u32 msc_ecc_2bit_err_insrt : 1; /* [1] */ + u32 msc_ecc_2bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_two_bit_int_u; + +/* Define the union csr_msc_mq_bind_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_bind_cfg_err : 1; /* [0] */ + u32 msc_bind_cfg_err_insrt : 1; /* [1] */ + u32 msc_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mq_bind_int_u; + +/* Define the union csr_msc_vnic_spcnt_inf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_vf_sp_cnt_inf_err : 1; /* [0] */ + u32 msc_vf_sp_cnt_inf_err_insrt : 1; /* [1] */ + u32 msc_vf_sp_cnt_inf_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_vnic_spcnt_inf_int_u; + +/* Define the union csr_msc_vnic_spcnt_cal_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_vf_sp_cnt_cal_err : 1; /* [0] */ + u32 msc_vf_sp_cnt_cal_err_insrt : 1; /* [1] */ + u32 msc_vf_sp_cnt_cal_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_vnic_spcnt_cal_int_u; + +/* Define the union csr_msc_socep_spcnt_inf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_socep_sp_cnt_inf_err : 1; /* [0] */ + u32 msc_socep_sp_cnt_inf_err_insrt : 1; /* [1] */ + u32 msc_socep_sp_cnt_inf_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_socep_spcnt_inf_int_u; + +/* Define the union csr_msc_socep_spcnt_cal_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_socep_sp_cnt_cal_err : 1; /* [0] */ + u32 msc_socep_sp_cnt_cal_err_insrt : 1; /* [1] */ + u32 msc_socep_sp_cnt_cal_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_socep_spcnt_cal_int_u; + +/* Define the union csr_msc_fifo_int0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int0_err0 : 1; /* [0] */ + u32 msc_fifo_int0_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int0_err1 : 1; /* [2] */ + u32 msc_fifo_int0_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int0_err2 : 1; /* [4] */ + u32 msc_fifo_int0_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int0_err3 : 1; /* [6] */ + u32 msc_fifo_int0_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int0_err4 : 1; /* [8] */ + u32 msc_fifo_int0_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int0_err5 : 1; /* [10] */ + u32 msc_fifo_int0_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int0_err6 : 1; /* [12] */ + u32 msc_fifo_int0_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int0_err7 : 1; /* [14] */ + u32 msc_fifo_int0_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int0_err8 : 1; /* [16] */ + u32 msc_fifo_int0_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int0_err9 : 1; /* [18] */ + u32 msc_fifo_int0_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int0_err10 : 1; /* [20] */ + u32 msc_fifo_int0_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int0_err11 : 1; /* [22] */ + u32 msc_fifo_int0_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int0_err12 : 1; /* [24] */ + u32 msc_fifo_int0_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int0_err13 : 1; /* [26] */ + u32 msc_fifo_int0_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int0_err14 : 1; /* [28] */ + u32 msc_fifo_int0_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int0_err15 : 1; /* [30] */ + u32 msc_fifo_int0_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int0_u; + +/* Define the union csr_msc_fifo_int0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int0_err0_en : 1; /* [0] */ + u32 msc_fifo_int0_err1_en : 1; /* [1] */ + u32 msc_fifo_int0_err2_en : 1; /* [2] */ + u32 msc_fifo_int0_err3_en : 1; /* [3] */ + u32 msc_fifo_int0_err4_en : 1; /* [4] */ + u32 msc_fifo_int0_err5_en : 1; /* [5] */ + u32 msc_fifo_int0_err6_en : 1; /* [6] */ + u32 msc_fifo_int0_err7_en : 1; /* [7] */ + u32 msc_fifo_int0_err8_en : 1; /* [8] */ + u32 msc_fifo_int0_err9_en : 1; /* [9] */ + u32 msc_fifo_int0_err10_en : 1; /* [10] */ + u32 msc_fifo_int0_err11_en : 1; /* [11] */ + u32 msc_fifo_int0_err12_en : 1; /* [12] */ + u32 msc_fifo_int0_err13_en : 1; /* [13] */ + u32 msc_fifo_int0_err14_en : 1; /* [14] */ + u32 msc_fifo_int0_err15_en : 1; /* [15] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int0_mask_u; + +/* Define the union csr_msc_fifo_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int1_err0 : 1; /* [0] */ + u32 msc_fifo_int1_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int1_err1 : 1; /* [2] */ + u32 msc_fifo_int1_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int1_err2 : 1; /* [4] */ + u32 msc_fifo_int1_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int1_err3 : 1; /* [6] */ + u32 msc_fifo_int1_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int1_err4 : 1; /* [8] */ + u32 msc_fifo_int1_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int1_err5 : 1; /* [10] */ + u32 msc_fifo_int1_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int1_err6 : 1; /* [12] */ + u32 msc_fifo_int1_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int1_err7 : 1; /* [14] */ + u32 msc_fifo_int1_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int1_err8 : 1; /* [16] */ + u32 msc_fifo_int1_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int1_err9 : 1; /* [18] */ + u32 msc_fifo_int1_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int1_err10 : 1; /* [20] */ + u32 msc_fifo_int1_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int1_err11 : 1; /* [22] */ + u32 msc_fifo_int1_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int1_err12 : 1; /* [24] */ + u32 msc_fifo_int1_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int1_err13 : 1; /* [26] */ + u32 msc_fifo_int1_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int1_err14 : 1; /* [28] */ + u32 msc_fifo_int1_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int1_err15 : 1; /* [30] */ + u32 msc_fifo_int1_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int1_u; + +/* Define the union csr_msc_fifo_int1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int1_err0_en : 1; /* [0] */ + u32 msc_fifo_int1_err1_en : 1; /* [1] */ + u32 msc_fifo_int1_err2_en : 1; /* [2] */ + u32 msc_fifo_int1_err3_en : 1; /* [3] */ + u32 msc_fifo_int1_err4_en : 1; /* [4] */ + u32 msc_fifo_int1_err5_en : 1; /* [5] */ + u32 msc_fifo_int1_err6_en : 1; /* [6] */ + u32 msc_fifo_int1_err7_en : 1; /* [7] */ + u32 msc_fifo_int1_err8_en : 1; /* [8] */ + u32 msc_fifo_int1_err9_en : 1; /* [9] */ + u32 msc_fifo_int1_err10_en : 1; /* [10] */ + u32 msc_fifo_int1_err11_en : 1; /* [11] */ + u32 msc_fifo_int1_err12_en : 1; /* [12] */ + u32 msc_fifo_int1_err13_en : 1; /* [13] */ + u32 msc_fifo_int1_err14_en : 1; /* [14] */ + u32 msc_fifo_int1_err15_en : 1; /* [15] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int1_mask_u; + +/* Define the union csr_msc_fifo_int2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int2_err0 : 1; /* [0] */ + u32 msc_fifo_int2_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int2_err1 : 1; /* [2] */ + u32 msc_fifo_int2_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int2_err2 : 1; /* [4] */ + u32 msc_fifo_int2_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int2_err3 : 1; /* [6] */ + u32 msc_fifo_int2_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int2_err4 : 1; /* [8] */ + u32 msc_fifo_int2_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int2_err5 : 1; /* [10] */ + u32 msc_fifo_int2_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int2_err6 : 1; /* [12] */ + u32 msc_fifo_int2_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int2_err7 : 1; /* [14] */ + u32 msc_fifo_int2_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int2_err8 : 1; /* [16] */ + u32 msc_fifo_int2_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int2_err9 : 1; /* [18] */ + u32 msc_fifo_int2_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int2_err10 : 1; /* [20] */ + u32 msc_fifo_int2_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int2_err11 : 1; /* [22] */ + u32 msc_fifo_int2_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int2_err12 : 1; /* [24] */ + u32 msc_fifo_int2_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int2_err13 : 1; /* [26] */ + u32 msc_fifo_int2_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int2_err14 : 1; /* [28] */ + u32 msc_fifo_int2_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int2_err15 : 1; /* [30] */ + u32 msc_fifo_int2_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int2_u; + +/* Define the union csr_msc_fifo_int2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int2_err0_en : 1; /* [0] */ + u32 msc_fifo_int2_err1_en : 1; /* [1] */ + u32 msc_fifo_int2_err2_en : 1; /* [2] */ + u32 msc_fifo_int2_err3_en : 1; /* [3] */ + u32 msc_fifo_int2_err4_en : 1; /* [4] */ + u32 msc_fifo_int2_err5_en : 1; /* [5] */ + u32 msc_fifo_int2_err6_en : 1; /* [6] */ + u32 msc_fifo_int2_err7_en : 1; /* [7] */ + u32 msc_fifo_int2_err8_en : 1; /* [8] */ + u32 msc_fifo_int2_err9_en : 1; /* [9] */ + u32 msc_fifo_int2_err10_en : 1; /* [10] */ + u32 msc_fifo_int2_err11_en : 1; /* [11] */ + u32 msc_fifo_int2_err12_en : 1; /* [12] */ + u32 msc_fifo_int2_err13_en : 1; /* [13] */ + u32 msc_fifo_int2_err14_en : 1; /* [14] */ + u32 msc_fifo_int2_err15_en : 1; /* [15] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int2_mask_u; + +/* Define the union csr_msc_fifo_int3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int3_err0 : 1; /* [0] */ + u32 msc_fifo_int3_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int3_err1 : 1; /* [2] */ + u32 msc_fifo_int3_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int3_err2 : 1; /* [4] */ + u32 msc_fifo_int3_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int3_err3 : 1; /* [6] */ + u32 msc_fifo_int3_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int3_err4 : 1; /* [8] */ + u32 msc_fifo_int3_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int3_err5 : 1; /* [10] */ + u32 msc_fifo_int3_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int3_err6 : 1; /* [12] */ + u32 msc_fifo_int3_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int3_err7 : 1; /* [14] */ + u32 msc_fifo_int3_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int3_err8 : 1; /* [16] */ + u32 msc_fifo_int3_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int3_err9 : 1; /* [18] */ + u32 msc_fifo_int3_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int3_err10 : 1; /* [20] */ + u32 msc_fifo_int3_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int3_err11 : 1; /* [22] */ + u32 msc_fifo_int3_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int3_err12 : 1; /* [24] */ + u32 msc_fifo_int3_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int3_err13 : 1; /* [26] */ + u32 msc_fifo_int3_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int3_err14 : 1; /* [28] */ + u32 msc_fifo_int3_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int3_err15 : 1; /* [30] */ + u32 msc_fifo_int3_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int3_u; + +/* Define the union csr_msc_fifo_int3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int3_err0_en : 1; /* [0] */ + u32 msc_fifo_int3_err1_en : 1; /* [1] */ + u32 msc_fifo_int3_err2_en : 1; /* [2] */ + u32 msc_fifo_int3_err3_en : 1; /* [3] */ + u32 msc_fifo_int3_err4_en : 1; /* [4] */ + u32 msc_fifo_int3_err5_en : 1; /* [5] */ + u32 msc_fifo_int3_err6_en : 1; /* [6] */ + u32 msc_fifo_int3_err7_en : 1; /* [7] */ + u32 msc_fifo_int3_err8_en : 1; /* [8] */ + u32 msc_fifo_int3_err9_en : 1; /* [9] */ + u32 msc_fifo_int3_err10_en : 1; /* [10] */ + u32 msc_fifo_int3_err11_en : 1; /* [11] */ + u32 msc_fifo_int3_err12_en : 1; /* [12] */ + u32 msc_fifo_int3_err13_en : 1; /* [13] */ + u32 msc_fifo_int3_err14_en : 1; /* [14] */ + u32 msc_fifo_int3_err15_en : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int3_mask_u; + +/* Define the union csr_msc_fifo_int4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int4_err0 : 1; /* [0] */ + u32 msc_fifo_int4_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int4_err1 : 1; /* [2] */ + u32 msc_fifo_int4_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int4_err2 : 1; /* [4] */ + u32 msc_fifo_int4_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int4_err3 : 1; /* [6] */ + u32 msc_fifo_int4_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int4_err4 : 1; /* [8] */ + u32 msc_fifo_int4_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int4_err5 : 1; /* [10] */ + u32 msc_fifo_int4_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int4_err6 : 1; /* [12] */ + u32 msc_fifo_int4_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int4_err7 : 1; /* [14] */ + u32 msc_fifo_int4_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int4_err8 : 1; /* [16] */ + u32 msc_fifo_int4_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int4_err9 : 1; /* [18] */ + u32 msc_fifo_int4_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int4_err10 : 1; /* [20] */ + u32 msc_fifo_int4_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int4_err11 : 1; /* [22] */ + u32 msc_fifo_int4_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int4_err12 : 1; /* [24] */ + u32 msc_fifo_int4_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int4_err13 : 1; /* [26] */ + u32 msc_fifo_int4_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int4_err14 : 1; /* [28] */ + u32 msc_fifo_int4_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int4_err15 : 1; /* [30] */ + u32 msc_fifo_int4_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int4_u; + +/* Define the union csr_msc_fifo_int4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int4_err0_en : 1; /* [0] */ + u32 msc_fifo_int4_err1_en : 1; /* [1] */ + u32 msc_fifo_int4_err2_en : 1; /* [2] */ + u32 msc_fifo_int4_err3_en : 1; /* [3] */ + u32 msc_fifo_int4_err4_en : 1; /* [4] */ + u32 msc_fifo_int4_err5_en : 1; /* [5] */ + u32 msc_fifo_int4_err6_en : 1; /* [6] */ + u32 msc_fifo_int4_err7_en : 1; /* [7] */ + u32 msc_fifo_int4_err8_en : 1; /* [8] */ + u32 msc_fifo_int4_err9_en : 1; /* [9] */ + u32 msc_fifo_int4_err10_en : 1; /* [10] */ + u32 msc_fifo_int4_err11_en : 1; /* [11] */ + u32 msc_fifo_int4_err12_en : 1; /* [12] */ + u32 msc_fifo_int4_err13_en : 1; /* [13] */ + u32 msc_fifo_int4_err14_en : 1; /* [14] */ + u32 msc_fifo_int4_err15_en : 1; /* [15] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int4_mask_u; + +/* Define the union csr_msc_fifo_int5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int5_err0 : 1; /* [0] */ + u32 msc_fifo_int5_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int5_err1 : 1; /* [2] */ + u32 msc_fifo_int5_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int5_err2 : 1; /* [4] */ + u32 msc_fifo_int5_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int5_err3 : 1; /* [6] */ + u32 msc_fifo_int5_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int5_err4 : 1; /* [8] */ + u32 msc_fifo_int5_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int5_err5 : 1; /* [10] */ + u32 msc_fifo_int5_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int5_err6 : 1; /* [12] */ + u32 msc_fifo_int5_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int5_err7 : 1; /* [14] */ + u32 msc_fifo_int5_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int5_err8 : 1; /* [16] */ + u32 msc_fifo_int5_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int5_err9 : 1; /* [18] */ + u32 msc_fifo_int5_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int5_err10 : 1; /* [20] */ + u32 msc_fifo_int5_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int5_err11 : 1; /* [22] */ + u32 msc_fifo_int5_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int5_err12 : 1; /* [24] */ + u32 msc_fifo_int5_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int5_err13 : 1; /* [26] */ + u32 msc_fifo_int5_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int5_err14 : 1; /* [28] */ + u32 msc_fifo_int5_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int5_err15 : 1; /* [30] */ + u32 msc_fifo_int5_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int5_u; + +/* Define the union csr_msc_fifo_int5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int5_err0_en : 1; /* [0] */ + u32 msc_fifo_int5_err1_en : 1; /* [1] */ + u32 msc_fifo_int5_err2_en : 1; /* [2] */ + u32 msc_fifo_int5_err3_en : 1; /* [3] */ + u32 msc_fifo_int5_err4_en : 1; /* [4] */ + u32 msc_fifo_int5_err5_en : 1; /* [5] */ + u32 msc_fifo_int5_err6_en : 1; /* [6] */ + u32 msc_fifo_int5_err7_en : 1; /* [7] */ + u32 msc_fifo_int5_err8_en : 1; /* [8] */ + u32 msc_fifo_int5_err9_en : 1; /* [9] */ + u32 msc_fifo_int5_err10_en : 1; /* [10] */ + u32 msc_fifo_int5_err11_en : 1; /* [11] */ + u32 msc_fifo_int5_err12_en : 1; /* [12] */ + u32 msc_fifo_int5_err13_en : 1; /* [13] */ + u32 msc_fifo_int5_err14_en : 1; /* [14] */ + u32 msc_fifo_int5_err15_en : 1; /* [15] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int5_mask_u; + +/* Define the union csr_msc_fifo_int6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int6_err0 : 1; /* [0] */ + u32 msc_fifo_int6_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int6_err1 : 1; /* [2] */ + u32 msc_fifo_int6_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int6_err2 : 1; /* [4] */ + u32 msc_fifo_int6_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int6_err3 : 1; /* [6] */ + u32 msc_fifo_int6_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int6_err4 : 1; /* [8] */ + u32 msc_fifo_int6_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int6_err5 : 1; /* [10] */ + u32 msc_fifo_int6_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int6_err6 : 1; /* [12] */ + u32 msc_fifo_int6_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int6_err7 : 1; /* [14] */ + u32 msc_fifo_int6_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int6_err8 : 1; /* [16] */ + u32 msc_fifo_int6_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int6_err9 : 1; /* [18] */ + u32 msc_fifo_int6_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int6_err10 : 1; /* [20] */ + u32 msc_fifo_int6_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int6_err11 : 1; /* [22] */ + u32 msc_fifo_int6_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int6_err12 : 1; /* [24] */ + u32 msc_fifo_int6_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int6_err13 : 1; /* [26] */ + u32 msc_fifo_int6_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int6_err14 : 1; /* [28] */ + u32 msc_fifo_int6_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int6_err15 : 1; /* [30] */ + u32 msc_fifo_int6_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int6_u; + +/* Define the union csr_msc_fifo_int6_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int6_err0_en : 1; /* [0] */ + u32 msc_fifo_int6_err1_en : 1; /* [1] */ + u32 msc_fifo_int6_err2_en : 1; /* [2] */ + u32 msc_fifo_int6_err3_en : 1; /* [3] */ + u32 msc_fifo_int6_err4_en : 1; /* [4] */ + u32 msc_fifo_int6_err5_en : 1; /* [5] */ + u32 msc_fifo_int6_err6_en : 1; /* [6] */ + u32 msc_fifo_int6_err7_en : 1; /* [7] */ + u32 msc_fifo_int6_err8_en : 1; /* [8] */ + u32 msc_fifo_int6_err9_en : 1; /* [9] */ + u32 msc_fifo_int6_err10_en : 1; /* [10] */ + u32 msc_fifo_int6_err11_en : 1; /* [11] */ + u32 msc_fifo_int6_err12_en : 1; /* [12] */ + u32 msc_fifo_int6_err13_en : 1; /* [13] */ + u32 msc_fifo_int6_err14_en : 1; /* [14] */ + u32 msc_fifo_int6_err15_en : 1; /* [15] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int6_mask_u; + +/* Define the union csr_msc_fifo_int7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int7_err0 : 1; /* [0] */ + u32 msc_fifo_int7_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int7_err1 : 1; /* [2] */ + u32 msc_fifo_int7_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int7_err2 : 1; /* [4] */ + u32 msc_fifo_int7_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int7_err3 : 1; /* [6] */ + u32 msc_fifo_int7_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int7_err4 : 1; /* [8] */ + u32 msc_fifo_int7_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int7_err5 : 1; /* [10] */ + u32 msc_fifo_int7_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int7_err6 : 1; /* [12] */ + u32 msc_fifo_int7_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int7_err7 : 1; /* [14] */ + u32 msc_fifo_int7_err7_insrt : 1; /* [15] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int7_u; + +/* Define the union csr_msc_fifo_int7_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int7_err0_en : 1; /* [0] */ + u32 msc_fifo_int7_err1_en : 1; /* [1] */ + u32 msc_fifo_int7_err2_en : 1; /* [2] */ + u32 msc_fifo_int7_err3_en : 1; /* [3] */ + u32 msc_fifo_int7_err4_en : 1; /* [4] */ + u32 msc_fifo_int7_err5_en : 1; /* [5] */ + u32 msc_fifo_int7_err6_en : 1; /* [6] */ + u32 msc_fifo_int7_err7_en : 1; /* [7] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int7_mask_u; + +/* Define the union csr_msc_bp_delay_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_bp_delay_cnt : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_bp_delay_cnt_u; + +/* Define the union csr_msc_vf_sp_cnt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_sp_cnt_flag_en : 1; /* [0] */ + u32 rsv_19 : 3; /* [3:1] */ + u32 socep_sp_cnt_flag_en : 1; /* [4] */ + u32 rsv_20 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_vf_sp_cnt_en_u; + +/* Define the union csr_presub_pktlen_ns_stf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_ns_stf : 18; /* [17:0] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_ns_stf_u; + +/* Define the union csr_presub_pktlen_ns_stl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_ns_stl : 18; /* [17:0] */ + u32 rsv_22 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_ns_stl_u; + +/* Define the union csr_cmq_presub_pktlen_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_presub_pktlen_cs : 18; /* [17:0] */ + u32 rsv_23 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_presub_pktlen_cs_u; + +/* Define the union csr_nfmq_presub_pktlen_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_presub_pktlen_cs : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_presub_pktlen_cs_u; + +/* Define the union csr_presub_pktnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktnum_ns_stl : 8; /* [7:0] */ + u32 presub_pktnum_ns_stf : 8; /* [15:8] */ + u32 presub_pktnum_cs_cmq : 8; /* [23:16] */ + u32 presub_pktnum_cs_nfmq : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktnum_u; + +/* Define the union csr_presub_pktlen_socnmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_socnmq : 18; /* [17:0] */ + u32 rsv_25 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_socnmq_u; + +/* Define the union csr_presub_pktlen_soccmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_soccmq : 18; /* [17:0] */ + u32 rsv_26 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_soccmq_u; + +/* Define the union csr_presub_pktnum_soc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktnum_socnmq : 8; /* [7:0] */ + u32 presub_pktnum_soccmq : 8; /* [15:8] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktnum_soc_u; + +/* Define the union csr_msc_pps_shaper_cfg_pktlen_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_pps_typical_pktlen_cfg : 3; /* [2:0] */ + u32 rsv_28 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_pps_shaper_cfg_pktlen_u; + +/* Define the union csr_msc_root_crr_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_crr_weight_cfg_ns : 3; /* [2:0] */ + u32 rsv_29 : 5; /* [7:3] */ + u32 msc_crr_weight_cfg_cs : 3; /* [10:8] */ + u32 rsv_30 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_root_crr_weight_cfg_u; + +/* Define the union csr_socmsc_root_sch_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_rt_sch_wgt_cfg : 3; /* [2:0] */ + u32 rsv_31 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_root_sch_wgt_cfg_u; + +/* Define the union csr_weight_ns_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_weight_ns_offset : 5; /* [4:0] */ + u32 rsv_32 : 3; /* [7:5] */ + u32 ep_weight_ns_offset : 5; /* [12:8] */ + u32 rsv_33 : 3; /* [15:13] */ + u32 host_weight_ns_offset : 5; /* [20:16] */ + u32 rsv_34 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_weight_ns_offset_u; + +/* Define the union csr_weight_cs_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_cos_weight_cs_offset : 5; /* [4:0] */ + u32 rsv_35 : 3; /* [7:5] */ + u32 cmq_cos_weight_cs_offset : 5; /* [12:8] */ + u32 rsv_36 : 3; /* [15:13] */ + u32 ep_weight_cs_offset : 5; /* [20:16] */ + u32 rsv_37 : 3; /* [23:21] */ + u32 host_weight_cs_offset : 5; /* [28:24] */ + u32 rsv_38 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_weight_cs_offset_u; + +/* Define the union csr_weight_mscsoc_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_mq_weight_offset : 5; /* [4:0] */ + u32 rsv_39 : 3; /* [7:5] */ + u32 soc_ep_weight_offset : 5; /* [12:8] */ + u32 rsv_40 : 3; /* [15:13] */ + u32 soc_serv_weight_offset : 5; /* [20:16] */ + u32 rsv_41 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_weight_mscsoc_offset_u; + +/* Define the union csr_host_weight_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_weight_ns_0 : 8; /* [7:0] */ + u32 host_weight_ns_1 : 8; /* [15:8] */ + u32 host_weight_ns_2 : 8; /* [23:16] */ + u32 host_weight_ns_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_weight_ns_u; + +/* Define the union csr_host_weight_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_weight_cs_0 : 8; /* [7:0] */ + u32 host_weight_cs_1 : 8; /* [15:8] */ + u32 host_weight_cs_2 : 8; /* [23:16] */ + u32 host_weight_cs_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_weight_cs_u; + +/* Define the union csr_qa_weight_cfg_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_qa_weight_cfg_cs : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qa_weight_cfg_cs_u; + +/* Define the union csr_ep_weight_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mscep_weight_cfg_ns : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_cfg_ns_u; + +/* Define the union csr_ep_weight_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mscep_weight_cfg_cmq : 8; /* [7:0] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_cfg_cmq_u; + +/* Define the union csr_ep_weight_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mscep_weight_cfg_nfmq : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_cfg_nfmq_u; + +/* Define the union csr_soc_mq_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmq_weight_cfg : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_mq_weight_cfg_u; + +/* Define the union csr_soc_ep_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socep_weight_cfg : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_ep_weight_cfg_u; + +/* Define the union csr_soc_serv_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socserv_weight_cfg : 8; /* [7:0] */ + u32 rsv_48 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_serv_weight_cfg_u; + +/* Define the union csr_host_shap_bps_cfg_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_bps_cfg_cs : 25; /* [24:0] */ + u32 rsv_49 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_bps_cfg_cs_u; + +/* Define the union csr_host_shap_pps_cfg_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_pps_cfg_cs : 25; /* [24:0] */ + u32 rsv_50 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_pps_cfg_cs_u; + +/* Define the union csr_host_shap_bps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_bps_cfg_ns : 25; /* [24:0] */ + u32 rsv_51 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_bps_cfg_ns_u; + +/* Define the union csr_host_shap_pps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_pps_cfg_ns : 25; /* [24:0] */ + u32 rsv_52 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_pps_cfg_ns_u; + +/* Define the union csr_ep_shap_bps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg_ns : 25; /* [24:0] */ + u32 rsv_53 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_ns_u; + +/* Define the union csr_ep_shap_pps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg_ns : 25; /* [24:0] */ + u32 rsv_54 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_ns_u; + +/* Define the union csr_ep_shap_bps_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg_cmq : 25; /* [24:0] */ + u32 rsv_55 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_cmq_u; + +/* Define the union csr_ep_shap_pps_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg_cmq : 25; /* [24:0] */ + u32 rsv_56 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_cmq_u; + +/* Define the union csr_ep_shap_bps_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg_nfmq : 25; /* [24:0] */ + u32 rsv_57 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_nfmq_u; + +/* Define the union csr_ep_shap_pps_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg_nfmq : 25; /* [24:0] */ + u32 rsv_58 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_nfmq_u; + +/* Define the union csr_socmq_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmq_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_59 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmq_shap_bps_cfg_u; + +/* Define the union csr_socmq_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmq_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_60 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmq_shap_pps_cfg_u; + +/* Define the union csr_socep_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socep_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_61 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socep_shap_bps_cfg_u; + +/* Define the union csr_socep_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socep_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_62 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socep_shap_pps_cfg_u; + +/* Define the union csr_socserv_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socserv_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_63 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socserv_shap_bps_cfg_u; + +/* Define the union csr_socserv_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socserv_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_64 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socserv_shap_pps_cfg_u; + +/* Define the union csr_socrt_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socrt_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_65 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socrt_shap_bps_cfg_u; + +/* Define the union csr_socrt_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socrt_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_66 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socrt_shap_pps_cfg_u; + +/* Define the union csr_msc_shap_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_nmq_shap_byp_vld : 1; /* [0] */ + u32 msc_ns_vnic_shap_byp_vld : 1; /* [1] */ + u32 msc_ns_vnicgrp_shap_byp_vld : 1; /* [2] */ + u32 msc_ns_ep_shap_byp_vld : 1; /* [3] */ + u32 msc_ns_host_shap_byp_vld : 1; /* [4] */ + u32 rsv_67 : 3; /* [7:5] */ + u32 msc_cmq_shap_byp_vld : 1; /* [8] */ + u32 msc_nfmq_vnic_shap_byp_vld : 1; /* [9] */ + u32 msc_cs_ep_shap_byp_vld : 1; /* [10] */ + u32 msc_cs_host_shap_byp_vld : 1; /* [11] */ + u32 rsv_68 : 4; /* [15:12] */ + u32 socmsc_mq_shap_byp_vld : 1; /* [16] */ + u32 socmsc_ep_shap_byp_vld : 1; /* [17] */ + u32 socmsc_serv_shap_byp_vld : 1; /* [18] */ + u32 socmsc_rt_shap_byp_vld : 1; /* [19] */ + u32 rsv_69 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_shap_bypass_cfg_u; + +/* Define the union csr_msc_host_root_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_xon_cfg_ns : 4; /* [3:0] */ + u32 msc_host_xon_cfg_cs : 4; /* [7:4] */ + u32 msc_root_xon_cfg_ns : 1; /* [8] */ + u32 msc_root_xon_cfg_cs : 1; /* [9] */ + u32 rsv_70 : 2; /* [11:10] */ + u32 msc_root_xon_cfg : 1; /* [12] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_root_xon_cfg_u; + +/* Define the union csr_msc_soc_root_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ep_xon_cfg_ns : 8; /* [7:0] */ + u32 socmsc_ep_xon_cfg_cs : 8; /* [15:8] */ + u32 socmsc_root_xon_cfg_ns : 1; /* [16] */ + u32 socmsc_root_xon_cfg_cs : 1; /* [17] */ + u32 rsv_72 : 6; /* [23:18] */ + u32 socmsc_root_xon_cfg : 1; /* [24] */ + u32 rsv_73 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_soc_root_xon_cfg_u; + +/* Define the union csr_msc_host_ep_xon_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_hostep_xon_cfg_ns : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_ep_xon_cfg_ns_u; + +/* Define the union csr_msc_host_ep_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_hostep_xon_cfg_nfmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_ep_xon_cfg_nfmq_u; + +/* Define the union csr_msc_host_ep_xon_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_hostep_xon_cfg_cmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_ep_xon_cfg_cmq_u; + +/* Define the union csr_socmsc_mq_xon_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_mq_xon_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_mq_xon_cfg_ns_u; + +/* Define the union csr_msc_prm_port_bp_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_dp_ep_bp : 8; /* [7:0] */ + u32 prm_mqm_cp_ep_bp : 8; /* [15:8] */ + u32 prm_mqm_dp_root_bp : 1; /* [16] */ + u32 prm_mqm_cp_root_bp : 1; /* [17] */ + u32 prm_mqm_root_bp : 1; /* [18] */ + u32 rsv_74 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_prm_port_bp_sta0_u; + +/* Define the union csr_msc_prm_port_bp_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_soc_dp_cos_bp : 8; /* [7:0] */ + u32 prm_mqm_soc_cp_cos_bp : 8; /* [15:8] */ + u32 prm_mqm_soc_dp_root_bp : 1; /* [16] */ + u32 prm_mqm_soc_cp_root_bp : 1; /* [17] */ + u32 rsv_75 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_prm_port_bp_sta1_u; + +/* Define the union csr_msc_qu_cos_bp_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_dp_ep_cos_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_qu_cos_bp_sta0_u; + +/* Define the union csr_msc_qu_cos_bp_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_dp_ep_cos_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_qu_cos_bp_sta1_u; + +/* Define the union csr_socmsc_rt_ep_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_el_bp : 16; /* [15:0] */ + u32 socmsc_sl_bp : 2; /* [17:16] */ + u32 socmsc_rl_bp : 1; /* [18] */ + u32 rsv_76 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_rt_ep_bp_sta_u; + +/* Define the union csr_socmsc_queue_bp_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta0_u; + +/* Define the union csr_socmsc_queue_bp_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta1_u; + +/* Define the union csr_socmsc_queue_bp_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta2_u; + +/* Define the union csr_socmsc_queue_bp_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta3_u; + +/* Define the union csr_socmsc_queue_eligible_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta0_u; + +/* Define the union csr_socmsc_queue_eligible_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta1_u; + +/* Define the union csr_socmsc_queue_eligible_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta2_u; + +/* Define the union csr_socmsc_queue_eligible_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta3_u; + +/* Define the union csr_msc_rt_host_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ns_hl_bp : 4; /* [3:0] */ + u32 msc_cs_hl_bp : 4; /* [7:4] */ + u32 msc_ns_sl_bp : 1; /* [8] */ + u32 msc_cs_sl_bp : 1; /* [9] */ + u32 msc_rl_bp : 1; /* [10] */ + u32 enqc_msc_dp_bp : 1; /* [11] */ + u32 enqc_msc_cp_bp : 1; /* [12] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rt_host_bp_sta_u; + +/* Define the union csr_msc_hostep_ns_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_ep_ns_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_hostep_ns_bp_sta_u; + +/* Define the union csr_msc_hostep_nfmq_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_ep_nfmq_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_hostep_nfmq_bp_sta_u; + +/* Define the union csr_msc_hostep_cmq_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_ep_cmq_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_hostep_cmq_bp_sta_u; + +/* Define the union csr_msc_fifo_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ns_du_fifo_gap : 4; /* [3:0] */ + u32 msc_cs_du_fifo_gap : 4; /* [7:4] */ + u32 socmsc_du_fifo_gap : 3; /* [10:8] */ + u32 rsv_78 : 1; /* [11] */ + u32 msc_fast_cnp_fifo_gap : 4; /* [15:12] */ + u32 rsv_79 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_th_cfg_u; + +/* Define the union csr_msc_fifo_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st0 : 2; /* [1:0] */ + u32 msc_fifo1_st0 : 2; /* [3:2] */ + u32 msc_fifo2_st0 : 2; /* [5:4] */ + u32 msc_fifo3_st0 : 2; /* [7:6] */ + u32 msc_fifo4_st0 : 2; /* [9:8] */ + u32 msc_fifo5_st0 : 2; /* [11:10] */ + u32 msc_fifo6_st0 : 2; /* [13:12] */ + u32 msc_fifo7_st0 : 2; /* [15:14] */ + u32 msc_fifo8_st0 : 2; /* [17:16] */ + u32 msc_fifo9_st0 : 2; /* [19:18] */ + u32 msc_fifo10_st0 : 2; /* [21:20] */ + u32 msc_fifo11_st0 : 2; /* [23:22] */ + u32 msc_fifo12_st0 : 2; /* [25:24] */ + u32 msc_fifo13_st0 : 2; /* [27:26] */ + u32 msc_fifo14_st0 : 2; /* [29:28] */ + u32 msc_fifo15_st0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st0_u; + +/* Define the union csr_msc_fifo_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st1 : 2; /* [1:0] */ + u32 msc_fifo1_st1 : 2; /* [3:2] */ + u32 msc_fifo2_st1 : 2; /* [5:4] */ + u32 msc_fifo3_st1 : 2; /* [7:6] */ + u32 msc_fifo4_st1 : 2; /* [9:8] */ + u32 msc_fifo5_st1 : 2; /* [11:10] */ + u32 msc_fifo6_st1 : 2; /* [13:12] */ + u32 msc_fifo7_st1 : 2; /* [15:14] */ + u32 msc_fifo8_st1 : 2; /* [17:16] */ + u32 msc_fifo9_st1 : 2; /* [19:18] */ + u32 msc_fifo10_st1 : 2; /* [21:20] */ + u32 msc_fifo11_st1 : 2; /* [23:22] */ + u32 msc_fifo12_st1 : 2; /* [25:24] */ + u32 msc_fifo13_st1 : 2; /* [27:26] */ + u32 msc_fifo14_st1 : 2; /* [29:28] */ + u32 msc_fifo15_st1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st1_u; + +/* Define the union csr_msc_fifo_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st2 : 2; /* [1:0] */ + u32 msc_fifo1_st2 : 2; /* [3:2] */ + u32 msc_fifo2_st2 : 2; /* [5:4] */ + u32 msc_fifo3_st2 : 2; /* [7:6] */ + u32 msc_fifo4_st2 : 2; /* [9:8] */ + u32 msc_fifo5_st2 : 2; /* [11:10] */ + u32 msc_fifo6_st2 : 2; /* [13:12] */ + u32 msc_fifo7_st2 : 2; /* [15:14] */ + u32 msc_fifo8_st2 : 2; /* [17:16] */ + u32 msc_fifo9_st2 : 2; /* [19:18] */ + u32 msc_fifo10_st2 : 2; /* [21:20] */ + u32 msc_fifo11_st2 : 2; /* [23:22] */ + u32 msc_fifo12_st2 : 2; /* [25:24] */ + u32 msc_fifo13_st2 : 2; /* [27:26] */ + u32 msc_fifo14_st2 : 2; /* [29:28] */ + u32 msc_fifo15_st2 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st2_u; + +/* Define the union csr_msc_fifo_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st3 : 2; /* [1:0] */ + u32 msc_fifo1_st3 : 2; /* [3:2] */ + u32 msc_fifo2_st3 : 2; /* [5:4] */ + u32 msc_fifo3_st3 : 2; /* [7:6] */ + u32 msc_fifo4_st3 : 2; /* [9:8] */ + u32 msc_fifo5_st3 : 2; /* [11:10] */ + u32 msc_fifo6_st3 : 2; /* [13:12] */ + u32 msc_fifo7_st3 : 2; /* [15:14] */ + u32 msc_fifo8_st3 : 2; /* [17:16] */ + u32 msc_fifo9_st3 : 2; /* [19:18] */ + u32 msc_fifo10_st3 : 2; /* [21:20] */ + u32 msc_fifo11_st3 : 2; /* [23:22] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st3_u; + +/* Define the union csr_cmq_rx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_rx_up_cnt_u; + +/* Define the union csr_nfmq_rx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_rx_up_cnt_u; + +/* Define the union csr_nmq_rx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_rx_up_cnt_u; + +/* Define the union csr_cmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_sch_cnt_u; + +/* Define the union csr_nfmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_sch_cnt_u; + +/* Define the union csr_nmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_sch_cnt_u; + +/* Define the union csr_soccmq_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soccmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soccmq_up_cnt_u; + +/* Define the union csr_socnmq_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socnmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socnmq_up_cnt_u; + +/* Define the union csr_soccmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soccmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soccmq_sch_cnt_u; + +/* Define the union csr_socnmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socnmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socnmq_sch_cnt_u; + +/* Define the union csr_cmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_empt_sch_cnt_u; + +/* Define the union csr_nfmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_empt_sch_cnt_u; + +/* Define the union csr_nmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_empt_sch_cnt_u; + +/* Define the union csr_cmq_rx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_rx_du_cnt_u; + +/* Define the union csr_nfmq_rx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_rx_du_cnt_u; + +/* Define the union csr_nmq_rx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_rx_du_cnt_u; + +/* Define the union csr_soccmq_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soccmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soccmq_du_cnt_u; + +/* Define the union csr_socnmq_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socnmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socnmq_du_cnt_u; + +/* Define the union csr_msc_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_1bit_err_cnt_u; + +/* Define the union csr_msc_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_2bit_err_cnt_u; + +/* Define the union csr_sch_mq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_cfg : 13; /* [12:0] */ + u32 rsv_81 : 3; /* [15:13] */ + u32 sch_mq_qa_dfx_cfg : 2; /* [17:16] */ + u32 rsv_82 : 2; /* [19:18] */ + u32 sch_mq_dfx_cfg_vld : 1; /* [20] */ + u32 rsv_83 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_cfg_u; + +/* Define the union csr_sch_mq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_up_cnt_u; + +/* Define the union csr_sch_mq_dfx_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_sch_cnt_u; + +/* Define the union csr_sch_mq_dfx_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_empt_sch_cnt_u; + +/* Define the union csr_sch_mq_dfx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_du_cnt_u; + +/* Define the union csr_sch_socmq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_cfg : 7; /* [6:0] */ + u32 rsv_84 : 1; /* [7] */ + u32 sch_socmq_dfx_cfg_vld : 1; /* [8] */ + u32 rsv_85 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_cfg_u; + +/* Define the union csr_sch_socmq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_up_cnt_u; + +/* Define the union csr_sch_socmq_dfx_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_sch_cnt_u; + +/* Define the union csr_sch_socmq_dfx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_du_cnt_u; + +/* Define the union csr_socmsc_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_mcd_len_info : 26; /* [25:0] */ + u32 rsv_86 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_mcd_du_info_ptr0_u; + +/* Define the union csr_socmsc_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_mcd_id_info : 10; /* [9:0] */ + u32 rsv_87 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_mcd_du_info_ptr1_u; + +/* Define the union csr_msc_cs_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_cs_len_info : 26; /* [25:0] */ + u32 rsv_88 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_cs_mcd_du_info_ptr0_u; + +/* Define the union csr_msc_cs_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_cs_id_info_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_cs_mcd_du_info_ptr1_u; + +/* Define the union csr_msc_cs_mcd_du_info_ptr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_cs_id_info_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_cs_mcd_du_info_ptr2_u; + +/* Define the union csr_msc_ns_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_ns_len_info : 26; /* [25:0] */ + u32 rsv_89 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ns_mcd_du_info_ptr0_u; + +/* Define the union csr_msc_ns_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_ns_id_info_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ns_mcd_du_info_ptr1_u; + +/* Define the union csr_msc_ns_mcd_du_info_ptr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_ns_id_info_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ns_mcd_du_info_ptr2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msc_rw_rsv0_u msc_rw_rsv0; /* 0 */ + volatile csr_msc_rw_rsv1_u msc_rw_rsv1; /* 4 */ + volatile csr_msc_rw_rsv2_u msc_rw_rsv2; /* 8 */ + volatile csr_msc_rw_rsv3_u msc_rw_rsv3; /* C */ + volatile csr_msc_indrect_ctrl_u msc_indrect_ctrl; /* 10 */ + volatile csr_msc_indrect_timeout_u msc_indrect_timeout; /* 14 */ + volatile csr_msc_indrect_data_0_u msc_indrect_data_0; /* 18 */ + volatile csr_msc_indrect_data_1_u msc_indrect_data_1; /* 1C */ + volatile csr_msc_mem_ecc_bypass_en_u msc_mem_ecc_bypass_en; /* 20 */ + volatile csr_msc_mem_ctrl_bus_cfg0_u msc_mem_ctrl_bus_cfg0; /* 24 */ + volatile csr_msc_mem_ctrl_bus_cfg1_u msc_mem_ctrl_bus_cfg1; /* 28 */ + volatile csr_msc_mem_ctrl_bus_cfg2_u msc_mem_ctrl_bus_cfg2; /* 2C */ + volatile csr_msc_mem_ctrl_bus_cfg3_u msc_mem_ctrl_bus_cfg3; /* 30 */ + volatile csr_msc_mem_ctrl_bus_cfg4_u msc_mem_ctrl_bus_cfg4; /* 34 */ + volatile csr_msc_int_vector_u msc_int_vector; /* 100 */ + volatile csr_msc_int_u msc_int; /* 104 */ + volatile csr_msc_int_en_u msc_int_en; /* 108 */ + volatile csr_msc_mem_err_req0_u msc_mem_err_req0; /* 10C */ + volatile csr_msc_mem_err_req1_u msc_mem_err_req1; /* 110 */ + volatile csr_msc_mem_err_req2_u msc_mem_err_req2; /* 114 */ + volatile csr_msc_mem_err_req3_u msc_mem_err_req3; /* 118 */ + volatile csr_msc_mem_err_req4_u msc_mem_err_req4; /* 11C */ + volatile csr_msc_ecc_one_bit_int_u msc_ecc_one_bit_int; /* 120 */ + volatile csr_msc_ecc_two_bit_int_u msc_ecc_two_bit_int; /* 124 */ + volatile csr_msc_mq_bind_int_u msc_mq_bind_int; /* 128 */ + volatile csr_msc_vnic_spcnt_inf_int_u msc_vnic_spcnt_inf_int; /* 12C */ + volatile csr_msc_vnic_spcnt_cal_int_u msc_vnic_spcnt_cal_int; /* 130 */ + volatile csr_msc_socep_spcnt_inf_int_u msc_socep_spcnt_inf_int; /* 134 */ + volatile csr_msc_socep_spcnt_cal_int_u msc_socep_spcnt_cal_int; /* 138 */ + volatile csr_msc_fifo_int0_u msc_fifo_int0; /* 150 */ + volatile csr_msc_fifo_int0_mask_u msc_fifo_int0_mask; /* 154 */ + volatile csr_msc_fifo_int1_u msc_fifo_int1; /* 158 */ + volatile csr_msc_fifo_int1_mask_u msc_fifo_int1_mask; /* 15C */ + volatile csr_msc_fifo_int2_u msc_fifo_int2; /* 160 */ + volatile csr_msc_fifo_int2_mask_u msc_fifo_int2_mask; /* 164 */ + volatile csr_msc_fifo_int3_u msc_fifo_int3; /* 168 */ + volatile csr_msc_fifo_int3_mask_u msc_fifo_int3_mask; /* 16C */ + volatile csr_msc_fifo_int4_u msc_fifo_int4; /* 170 */ + volatile csr_msc_fifo_int4_mask_u msc_fifo_int4_mask; /* 174 */ + volatile csr_msc_fifo_int5_u msc_fifo_int5; /* 178 */ + volatile csr_msc_fifo_int5_mask_u msc_fifo_int5_mask; /* 17C */ + volatile csr_msc_fifo_int6_u msc_fifo_int6; /* 180 */ + volatile csr_msc_fifo_int6_mask_u msc_fifo_int6_mask; /* 184 */ + volatile csr_msc_fifo_int7_u msc_fifo_int7; /* 188 */ + volatile csr_msc_fifo_int7_mask_u msc_fifo_int7_mask; /* 18C */ + volatile csr_msc_bp_delay_cnt_u msc_bp_delay_cnt; /* 200 */ + volatile csr_msc_vf_sp_cnt_en_u msc_vf_sp_cnt_en; /* 204 */ + volatile csr_presub_pktlen_ns_stf_u presub_pktlen_ns_stf; /* 250 */ + volatile csr_presub_pktlen_ns_stl_u presub_pktlen_ns_stl; /* 254 */ + volatile csr_cmq_presub_pktlen_cs_u cmq_presub_pktlen_cs; /* 258 */ + volatile csr_nfmq_presub_pktlen_cs_u nfmq_presub_pktlen_cs; /* 25C */ + volatile csr_presub_pktnum_u presub_pktnum; /* 260 */ + volatile csr_presub_pktlen_socnmq_u presub_pktlen_socnmq; /* 264 */ + volatile csr_presub_pktlen_soccmq_u presub_pktlen_soccmq; /* 268 */ + volatile csr_presub_pktnum_soc_u presub_pktnum_soc; /* 26C */ + volatile csr_msc_pps_shaper_cfg_pktlen_u msc_pps_shaper_cfg_pktlen; /* 270 */ + volatile csr_msc_root_crr_weight_cfg_u msc_root_crr_weight_cfg; /* 274 */ + volatile csr_socmsc_root_sch_wgt_cfg_u socmsc_root_sch_wgt_cfg; /* 278 */ + volatile csr_weight_ns_offset_u weight_ns_offset; /* 27C */ + volatile csr_weight_cs_offset_u weight_cs_offset; /* 280 */ + volatile csr_weight_mscsoc_offset_u weight_mscsoc_offset; /* 284 */ + volatile csr_host_weight_ns_u host_weight_ns; /* 288 */ + volatile csr_host_weight_cs_u host_weight_cs; /* 28C */ + volatile csr_qa_weight_cfg_cs_u qa_weight_cfg_cs[4]; /* 2F0 */ + volatile csr_ep_weight_cfg_ns_u ep_weight_cfg_ns[32]; /* 300 */ + volatile csr_ep_weight_cfg_cmq_u ep_weight_cfg_cmq[32]; /* 380 */ + volatile csr_ep_weight_cfg_nfmq_u ep_weight_cfg_nfmq[32]; /* 400 */ + volatile csr_soc_mq_weight_cfg_u soc_mq_weight_cfg[128]; /* 500 */ + volatile csr_soc_ep_weight_cfg_u soc_ep_weight_cfg[16]; /* 700 */ + volatile csr_soc_serv_weight_cfg_u soc_serv_weight_cfg[2]; /* 740 */ + volatile csr_host_shap_bps_cfg_cs_u host_shap_bps_cfg_cs[4]; /* 750 */ + volatile csr_host_shap_pps_cfg_cs_u host_shap_pps_cfg_cs[4]; /* 760 */ + volatile csr_host_shap_bps_cfg_ns_u host_shap_bps_cfg_ns[4]; /* 770 */ + volatile csr_host_shap_pps_cfg_ns_u host_shap_pps_cfg_ns[4]; /* 780 */ + volatile csr_ep_shap_bps_cfg_ns_u ep_shap_bps_cfg_ns[32]; /* 790 */ + volatile csr_ep_shap_pps_cfg_ns_u ep_shap_pps_cfg_ns[32]; /* 810 */ + volatile csr_ep_shap_bps_cfg_cmq_u ep_shap_bps_cfg_cmq[32]; /* 890 */ + volatile csr_ep_shap_pps_cfg_cmq_u ep_shap_pps_cfg_cmq[32]; /* 910 */ + volatile csr_ep_shap_bps_cfg_nfmq_u ep_shap_bps_cfg_nfmq[32]; /* 990 */ + volatile csr_ep_shap_pps_cfg_nfmq_u ep_shap_pps_cfg_nfmq[32]; /* A10 */ + volatile csr_socmq_shap_bps_cfg_u socmq_shap_bps_cfg[128]; /* B00 */ + volatile csr_socmq_shap_pps_cfg_u socmq_shap_pps_cfg[128]; /* D00 */ + volatile csr_socep_shap_bps_cfg_u socep_shap_bps_cfg[16]; /* F00 */ + volatile csr_socep_shap_pps_cfg_u socep_shap_pps_cfg[16]; /* F40 */ + volatile csr_socserv_shap_bps_cfg_u socserv_shap_bps_cfg[2]; /* F80 */ + volatile csr_socserv_shap_pps_cfg_u socserv_shap_pps_cfg[2]; /* F88 */ + volatile csr_socrt_shap_bps_cfg_u socrt_shap_bps_cfg; /* F90 */ + volatile csr_socrt_shap_pps_cfg_u socrt_shap_pps_cfg; /* F94 */ + volatile csr_msc_shap_bypass_cfg_u msc_shap_bypass_cfg; /* 1200 */ + volatile csr_msc_host_root_xon_cfg_u msc_host_root_xon_cfg; /* 1204 */ + volatile csr_msc_soc_root_xon_cfg_u msc_soc_root_xon_cfg; /* 1208 */ + volatile csr_msc_host_ep_xon_cfg_ns_u msc_host_ep_xon_cfg_ns; /* 120C */ + volatile csr_msc_host_ep_xon_cfg_nfmq_u msc_host_ep_xon_cfg_nfmq; /* 1210 */ + volatile csr_msc_host_ep_xon_cfg_cmq_u msc_host_ep_xon_cfg_cmq; /* 1214 */ + volatile csr_socmsc_mq_xon_cfg_ns_u socmsc_mq_xon_cfg_ns[4]; /* 1220 */ + volatile csr_msc_prm_port_bp_sta0_u msc_prm_port_bp_sta0; /* 1230 */ + volatile csr_msc_prm_port_bp_sta1_u msc_prm_port_bp_sta1; /* 1234 */ + volatile csr_msc_qu_cos_bp_sta0_u msc_qu_cos_bp_sta0; /* 1238 */ + volatile csr_msc_qu_cos_bp_sta1_u msc_qu_cos_bp_sta1; /* 123C */ + volatile csr_socmsc_rt_ep_bp_sta_u socmsc_rt_ep_bp_sta; /* 1240 */ + volatile csr_socmsc_queue_bp_sta0_u socmsc_queue_bp_sta0; /* 1244 */ + volatile csr_socmsc_queue_bp_sta1_u socmsc_queue_bp_sta1; /* 1248 */ + volatile csr_socmsc_queue_bp_sta2_u socmsc_queue_bp_sta2; /* 124C */ + volatile csr_socmsc_queue_bp_sta3_u socmsc_queue_bp_sta3; /* 1250 */ + volatile csr_socmsc_queue_eligible_sta0_u socmsc_queue_eligible_sta0; /* 1254 */ + volatile csr_socmsc_queue_eligible_sta1_u socmsc_queue_eligible_sta1; /* 1258 */ + volatile csr_socmsc_queue_eligible_sta2_u socmsc_queue_eligible_sta2; /* 125C */ + volatile csr_socmsc_queue_eligible_sta3_u socmsc_queue_eligible_sta3; /* 1260 */ + volatile csr_msc_rt_host_bp_sta_u msc_rt_host_bp_sta; /* 1264 */ + volatile csr_msc_hostep_ns_bp_sta_u msc_hostep_ns_bp_sta; /* 1268 */ + volatile csr_msc_hostep_nfmq_bp_sta_u msc_hostep_nfmq_bp_sta; /* 126C */ + volatile csr_msc_hostep_cmq_bp_sta_u msc_hostep_cmq_bp_sta; /* 1270 */ + volatile csr_msc_fifo_th_cfg_u msc_fifo_th_cfg; /* 1274 */ + volatile csr_msc_fifo_st0_u msc_fifo_st0; /* 1290 */ + volatile csr_msc_fifo_st1_u msc_fifo_st1; /* 1294 */ + volatile csr_msc_fifo_st2_u msc_fifo_st2; /* 1298 */ + volatile csr_msc_fifo_st3_u msc_fifo_st3; /* 129C */ + volatile csr_cmq_rx_up_cnt_u cmq_rx_up_cnt; /* 12A0 */ + volatile csr_nfmq_rx_up_cnt_u nfmq_rx_up_cnt; /* 12A4 */ + volatile csr_nmq_rx_up_cnt_u nmq_rx_up_cnt; /* 12A8 */ + volatile csr_cmq_sch_cnt_u cmq_sch_cnt; /* 12AC */ + volatile csr_nfmq_sch_cnt_u nfmq_sch_cnt; /* 12B0 */ + volatile csr_nmq_sch_cnt_u nmq_sch_cnt; /* 12B4 */ + volatile csr_soccmq_up_cnt_u soccmq_up_cnt; /* 12B8 */ + volatile csr_socnmq_up_cnt_u socnmq_up_cnt; /* 12BC */ + volatile csr_soccmq_sch_cnt_u soccmq_sch_cnt; /* 12C0 */ + volatile csr_socnmq_sch_cnt_u socnmq_sch_cnt; /* 12C4 */ + volatile csr_cmq_empt_sch_cnt_u cmq_empt_sch_cnt; /* 12C8 */ + volatile csr_nfmq_empt_sch_cnt_u nfmq_empt_sch_cnt; /* 12CC */ + volatile csr_nmq_empt_sch_cnt_u nmq_empt_sch_cnt; /* 12D0 */ + volatile csr_cmq_rx_du_cnt_u cmq_rx_du_cnt; /* 12D4 */ + volatile csr_nfmq_rx_du_cnt_u nfmq_rx_du_cnt; /* 12D8 */ + volatile csr_nmq_rx_du_cnt_u nmq_rx_du_cnt; /* 12DC */ + volatile csr_soccmq_du_cnt_u soccmq_du_cnt; /* 12E0 */ + volatile csr_socnmq_du_cnt_u socnmq_du_cnt; /* 12E4 */ + volatile csr_msc_ecc_1bit_err_cnt_u msc_ecc_1bit_err_cnt; /* 12E8 */ + volatile csr_msc_ecc_2bit_err_cnt_u msc_ecc_2bit_err_cnt; /* 12EC */ + volatile csr_sch_mq_dfx_cfg_u sch_mq_dfx_cfg; /* 1320 */ + volatile csr_sch_mq_dfx_up_cnt_u sch_mq_dfx_up_cnt; /* 1324 */ + volatile csr_sch_mq_dfx_sch_cnt_u sch_mq_dfx_sch_cnt; /* 1328 */ + volatile csr_sch_mq_dfx_empt_sch_cnt_u sch_mq_dfx_empt_sch_cnt; /* 132C */ + volatile csr_sch_mq_dfx_du_cnt_u sch_mq_dfx_du_cnt; /* 1330 */ + volatile csr_sch_socmq_dfx_cfg_u sch_socmq_dfx_cfg; /* 1334 */ + volatile csr_sch_socmq_dfx_up_cnt_u sch_socmq_dfx_up_cnt; /* 1338 */ + volatile csr_sch_socmq_dfx_sch_cnt_u sch_socmq_dfx_sch_cnt; /* 133C */ + volatile csr_sch_socmq_dfx_du_cnt_u sch_socmq_dfx_du_cnt; /* 1340 */ + volatile csr_socmsc_mcd_du_info_ptr0_u socmsc_mcd_du_info_ptr0; /* 1344 */ + volatile csr_socmsc_mcd_du_info_ptr1_u socmsc_mcd_du_info_ptr1; /* 1348 */ + volatile csr_msc_cs_mcd_du_info_ptr0_u msc_cs_mcd_du_info_ptr0; /* 134C */ + volatile csr_msc_cs_mcd_du_info_ptr1_u msc_cs_mcd_du_info_ptr1; /* 1350 */ + volatile csr_msc_cs_mcd_du_info_ptr2_u msc_cs_mcd_du_info_ptr2; /* 1354 */ + volatile csr_msc_ns_mcd_du_info_ptr0_u msc_ns_mcd_du_info_ptr0; /* 1358 */ + volatile csr_msc_ns_mcd_du_info_ptr1_u msc_ns_mcd_du_info_ptr1; /* 135C */ + volatile csr_msc_ns_mcd_du_info_ptr2_u msc_ns_mcd_du_info_ptr2; /* 1360 */ +} S_mqm_msc_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_msc */ +extern volatile S_mqm_msc_REGS_TYPE *gopmqm_mscAllReg; + +/* Declare the functions that set the member value */ +int iSetMSC_RW_RSV0_msc_rw_rsv0(unsigned int umsc_rw_rsv0); +int iSetMSC_RW_RSV1_msc_rw_rsv1(unsigned int umsc_rw_rsv1); +int iSetMSC_RW_RSV2_msc_rw_rsv2(unsigned int umsc_rw_rsv2); +int iSetMSC_RW_RSV3_msc_rw_rsv3(unsigned int umsc_rw_rsv3); +int iSetMSC_INDRECT_CTRL_msc_indrect_addr(unsigned int umsc_indrect_addr); +int iSetMSC_INDRECT_CTRL_msc_indrect_tab(unsigned int umsc_indrect_tab); +int iSetMSC_INDRECT_CTRL_msc_indrect_stat(unsigned int umsc_indrect_stat); +int iSetMSC_INDRECT_CTRL_msc_indrect_mode(unsigned int umsc_indrect_mode); +int iSetMSC_INDRECT_CTRL_msc_indrect_vld(unsigned int umsc_indrect_vld); +int iSetMSC_INDRECT_TIMEOUT_msc_indrect_timeout(unsigned int umsc_indrect_timeout); +int iSetMSC_INDRECT_DATA_0_msc_indrect_data_0(unsigned int umsc_indrect_data_0); +int iSetMSC_INDRECT_DATA_1_msc_indrect_data_1(unsigned int umsc_indrect_data_1); +int iSetMSC_MEM_ECC_BYPASS_EN_msc_mem_ecc_bypass(unsigned int umsc_mem_ecc_bypass); +int iSetMSC_MEM_CTRL_BUS_CFG0_msc_mem_ctrl_bus_0(unsigned int umsc_mem_ctrl_bus_0); +int iSetMSC_MEM_CTRL_BUS_CFG1_msc_mem_ctrl_bus_1(unsigned int umsc_mem_ctrl_bus_1); +int iSetMSC_MEM_CTRL_BUS_CFG2_msc_mem_ctrl_bus_2(unsigned int umsc_mem_ctrl_bus_2); +int iSetMSC_MEM_CTRL_BUS_CFG3_msc_mem_ctrl_bus_3(unsigned int umsc_mem_ctrl_bus_3); +int iSetMSC_MEM_CTRL_BUS_CFG4_msc_mem_ctrl_bus_4(unsigned int umsc_mem_ctrl_bus_4); +int iSetMSC_INT_VECTOR_msc_cpi_int_index(unsigned int umsc_cpi_int_index); +int iSetMSC_INT_VECTOR_msc_enable(unsigned int umsc_enable); +int iSetMSC_INT_VECTOR_msc_int_issue(unsigned int umsc_int_issue); +int iSetMSC_INT_msc_int_data(unsigned int umsc_int_data); +int iSetMSC_INT_msc_program_csr_id_ro(unsigned int umsc_program_csr_id_ro); +int iSetMSC_INT_EN_msc_int_en(unsigned int umsc_int_en); +int iSetMSC_INT_EN_msc_program_csr_id(unsigned int umsc_program_csr_id); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_0(unsigned int umsc_mem_err_req_0); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_1(unsigned int umsc_mem_err_req_1); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_2(unsigned int umsc_mem_err_req_2); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_3(unsigned int umsc_mem_err_req_3); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_4(unsigned int umsc_mem_err_req_4); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_5(unsigned int umsc_mem_err_req_5); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_6(unsigned int umsc_mem_err_req_6); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_7(unsigned int umsc_mem_err_req_7); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_8(unsigned int umsc_mem_err_req_8); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_9(unsigned int umsc_mem_err_req_9); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_10(unsigned int umsc_mem_err_req_10); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_11(unsigned int umsc_mem_err_req_11); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_12(unsigned int umsc_mem_err_req_12); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_13(unsigned int umsc_mem_err_req_13); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_14(unsigned int umsc_mem_err_req_14); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_15(unsigned int umsc_mem_err_req_15); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_16(unsigned int umsc_mem_err_req_16); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_17(unsigned int umsc_mem_err_req_17); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_18(unsigned int umsc_mem_err_req_18); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_19(unsigned int umsc_mem_err_req_19); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_20(unsigned int umsc_mem_err_req_20); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_21(unsigned int umsc_mem_err_req_21); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_22(unsigned int umsc_mem_err_req_22); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_23(unsigned int umsc_mem_err_req_23); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_24(unsigned int umsc_mem_err_req_24); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_25(unsigned int umsc_mem_err_req_25); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_26(unsigned int umsc_mem_err_req_26); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_27(unsigned int umsc_mem_err_req_27); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_28(unsigned int umsc_mem_err_req_28); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_29(unsigned int umsc_mem_err_req_29); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_32(unsigned int umsc_mem_err_req_32); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_33(unsigned int umsc_mem_err_req_33); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_34(unsigned int umsc_mem_err_req_34); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_35(unsigned int umsc_mem_err_req_35); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_36(unsigned int umsc_mem_err_req_36); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_37(unsigned int umsc_mem_err_req_37); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_38(unsigned int umsc_mem_err_req_38); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_39(unsigned int umsc_mem_err_req_39); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_40(unsigned int umsc_mem_err_req_40); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_41(unsigned int umsc_mem_err_req_41); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_42(unsigned int umsc_mem_err_req_42); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_43(unsigned int umsc_mem_err_req_43); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_44(unsigned int umsc_mem_err_req_44); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_45(unsigned int umsc_mem_err_req_45); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_46(unsigned int umsc_mem_err_req_46); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_47(unsigned int umsc_mem_err_req_47); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_48(unsigned int umsc_mem_err_req_48); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_49(unsigned int umsc_mem_err_req_49); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_50(unsigned int umsc_mem_err_req_50); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_51(unsigned int umsc_mem_err_req_51); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_52(unsigned int umsc_mem_err_req_52); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_53(unsigned int umsc_mem_err_req_53); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_54(unsigned int umsc_mem_err_req_54); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_55(unsigned int umsc_mem_err_req_55); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_64(unsigned int umsc_mem_err_req_64); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_65(unsigned int umsc_mem_err_req_65); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_66(unsigned int umsc_mem_err_req_66); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_67(unsigned int umsc_mem_err_req_67); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_68(unsigned int umsc_mem_err_req_68); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_69(unsigned int umsc_mem_err_req_69); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_70(unsigned int umsc_mem_err_req_70); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_71(unsigned int umsc_mem_err_req_71); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_72(unsigned int umsc_mem_err_req_72); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_73(unsigned int umsc_mem_err_req_73); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_74(unsigned int umsc_mem_err_req_74); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_75(unsigned int umsc_mem_err_req_75); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_76(unsigned int umsc_mem_err_req_76); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_77(unsigned int umsc_mem_err_req_77); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_78(unsigned int umsc_mem_err_req_78); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_79(unsigned int umsc_mem_err_req_79); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_80(unsigned int umsc_mem_err_req_80); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_81(unsigned int umsc_mem_err_req_81); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_82(unsigned int umsc_mem_err_req_82); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_83(unsigned int umsc_mem_err_req_83); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_84(unsigned int umsc_mem_err_req_84); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_85(unsigned int umsc_mem_err_req_85); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_86(unsigned int umsc_mem_err_req_86); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_87(unsigned int umsc_mem_err_req_87); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_88(unsigned int umsc_mem_err_req_88); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_89(unsigned int umsc_mem_err_req_89); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_90(unsigned int umsc_mem_err_req_90); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_91(unsigned int umsc_mem_err_req_91); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_92(unsigned int umsc_mem_err_req_92); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_93(unsigned int umsc_mem_err_req_93); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_94(unsigned int umsc_mem_err_req_94); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_95(unsigned int umsc_mem_err_req_95); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_96(unsigned int umsc_mem_err_req_96); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_97(unsigned int umsc_mem_err_req_97); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_98(unsigned int umsc_mem_err_req_98); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_99(unsigned int umsc_mem_err_req_99); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_100(unsigned int umsc_mem_err_req_100); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_101(unsigned int umsc_mem_err_req_101); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_102(unsigned int umsc_mem_err_req_102); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_103(unsigned int umsc_mem_err_req_103); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_104(unsigned int umsc_mem_err_req_104); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_105(unsigned int umsc_mem_err_req_105); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_106(unsigned int umsc_mem_err_req_106); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_107(unsigned int umsc_mem_err_req_107); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_108(unsigned int umsc_mem_err_req_108); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_109(unsigned int umsc_mem_err_req_109); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_110(unsigned int umsc_mem_err_req_110); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_111(unsigned int umsc_mem_err_req_111); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_112(unsigned int umsc_mem_err_req_112); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_113(unsigned int umsc_mem_err_req_113); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_114(unsigned int umsc_mem_err_req_114); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_115(unsigned int umsc_mem_err_req_115); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_116(unsigned int umsc_mem_err_req_116); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_117(unsigned int umsc_mem_err_req_117); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_118(unsigned int umsc_mem_err_req_118); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_119(unsigned int umsc_mem_err_req_119); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_120(unsigned int umsc_mem_err_req_120); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_121(unsigned int umsc_mem_err_req_121); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_122(unsigned int umsc_mem_err_req_122); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_123(unsigned int umsc_mem_err_req_123); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_124(unsigned int umsc_mem_err_req_124); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_125(unsigned int umsc_mem_err_req_125); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_126(unsigned int umsc_mem_err_req_126); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_127(unsigned int umsc_mem_err_req_127); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_128(unsigned int umsc_mem_err_req_128); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_129(unsigned int umsc_mem_err_req_129); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_130(unsigned int umsc_mem_err_req_130); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_131(unsigned int umsc_mem_err_req_131); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_132(unsigned int umsc_mem_err_req_132); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_133(unsigned int umsc_mem_err_req_133); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_134(unsigned int umsc_mem_err_req_134); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_135(unsigned int umsc_mem_err_req_135); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_136(unsigned int umsc_mem_err_req_136); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_137(unsigned int umsc_mem_err_req_137); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_138(unsigned int umsc_mem_err_req_138); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_139(unsigned int umsc_mem_err_req_139); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_140(unsigned int umsc_mem_err_req_140); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_141(unsigned int umsc_mem_err_req_141); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_142(unsigned int umsc_mem_err_req_142); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_143(unsigned int umsc_mem_err_req_143); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_144(unsigned int umsc_mem_err_req_144); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_145(unsigned int umsc_mem_err_req_145); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_146(unsigned int umsc_mem_err_req_146); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_147(unsigned int umsc_mem_err_req_147); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_148(unsigned int umsc_mem_err_req_148); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_149(unsigned int umsc_mem_err_req_149); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_150(unsigned int umsc_mem_err_req_150); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_151(unsigned int umsc_mem_err_req_151); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_152(unsigned int umsc_mem_err_req_152); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_153(unsigned int umsc_mem_err_req_153); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_154(unsigned int umsc_mem_err_req_154); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_155(unsigned int umsc_mem_err_req_155); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_156(unsigned int umsc_mem_err_req_156); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_157(unsigned int umsc_mem_err_req_157); +int iSetMSC_ECC_ONE_BIT_INT_msc_ecc_1bit_err(unsigned int umsc_ecc_1bit_err); +int iSetMSC_ECC_ONE_BIT_INT_msc_ecc_1bit_err_insrt(unsigned int umsc_ecc_1bit_err_insrt); +int iSetMSC_ECC_ONE_BIT_INT_msc_ecc_1bit_err_info(unsigned int umsc_ecc_1bit_err_info); +int iSetMSC_ECC_TWO_BIT_INT_msc_ecc_2bit_err(unsigned int umsc_ecc_2bit_err); +int iSetMSC_ECC_TWO_BIT_INT_msc_ecc_2bit_err_insrt(unsigned int umsc_ecc_2bit_err_insrt); +int iSetMSC_ECC_TWO_BIT_INT_msc_ecc_2bit_err_info(unsigned int umsc_ecc_2bit_err_info); +int iSetMSC_MQ_BIND_INT_msc_bind_cfg_err(unsigned int umsc_bind_cfg_err); +int iSetMSC_MQ_BIND_INT_msc_bind_cfg_err_insrt(unsigned int umsc_bind_cfg_err_insrt); +int iSetMSC_MQ_BIND_INT_msc_bind_cfg_err_info(unsigned int umsc_bind_cfg_err_info); +int iSetMSC_VNIC_SPCNT_INF_INT_msc_vf_sp_cnt_inf_err(unsigned int umsc_vf_sp_cnt_inf_err); +int iSetMSC_VNIC_SPCNT_INF_INT_msc_vf_sp_cnt_inf_err_insrt(unsigned int umsc_vf_sp_cnt_inf_err_insrt); +int iSetMSC_VNIC_SPCNT_INF_INT_msc_vf_sp_cnt_inf_err_info(unsigned int umsc_vf_sp_cnt_inf_err_info); +int iSetMSC_VNIC_SPCNT_CAL_INT_msc_vf_sp_cnt_cal_err(unsigned int umsc_vf_sp_cnt_cal_err); +int iSetMSC_VNIC_SPCNT_CAL_INT_msc_vf_sp_cnt_cal_err_insrt(unsigned int umsc_vf_sp_cnt_cal_err_insrt); +int iSetMSC_VNIC_SPCNT_CAL_INT_msc_vf_sp_cnt_cal_err_info(unsigned int umsc_vf_sp_cnt_cal_err_info); +int iSetMSC_SOCEP_SPCNT_INF_INT_msc_socep_sp_cnt_inf_err(unsigned int umsc_socep_sp_cnt_inf_err); +int iSetMSC_SOCEP_SPCNT_INF_INT_msc_socep_sp_cnt_inf_err_insrt(unsigned int umsc_socep_sp_cnt_inf_err_insrt); +int iSetMSC_SOCEP_SPCNT_INF_INT_msc_socep_sp_cnt_inf_err_info(unsigned int umsc_socep_sp_cnt_inf_err_info); +int iSetMSC_SOCEP_SPCNT_CAL_INT_msc_socep_sp_cnt_cal_err(unsigned int umsc_socep_sp_cnt_cal_err); +int iSetMSC_SOCEP_SPCNT_CAL_INT_msc_socep_sp_cnt_cal_err_insrt(unsigned int umsc_socep_sp_cnt_cal_err_insrt); +int iSetMSC_SOCEP_SPCNT_CAL_INT_msc_socep_sp_cnt_cal_err_info(unsigned int umsc_socep_sp_cnt_cal_err_info); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err0(unsigned int umsc_fifo_int0_err0); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err0_insrt(unsigned int umsc_fifo_int0_err0_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err1(unsigned int umsc_fifo_int0_err1); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err1_insrt(unsigned int umsc_fifo_int0_err1_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err2(unsigned int umsc_fifo_int0_err2); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err2_insrt(unsigned int umsc_fifo_int0_err2_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err3(unsigned int umsc_fifo_int0_err3); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err3_insrt(unsigned int umsc_fifo_int0_err3_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err4(unsigned int umsc_fifo_int0_err4); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err4_insrt(unsigned int umsc_fifo_int0_err4_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err5(unsigned int umsc_fifo_int0_err5); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err5_insrt(unsigned int umsc_fifo_int0_err5_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err6(unsigned int umsc_fifo_int0_err6); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err6_insrt(unsigned int umsc_fifo_int0_err6_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err7(unsigned int umsc_fifo_int0_err7); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err7_insrt(unsigned int umsc_fifo_int0_err7_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err8(unsigned int umsc_fifo_int0_err8); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err8_insrt(unsigned int umsc_fifo_int0_err8_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err9(unsigned int umsc_fifo_int0_err9); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err9_insrt(unsigned int umsc_fifo_int0_err9_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err10(unsigned int umsc_fifo_int0_err10); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err10_insrt(unsigned int umsc_fifo_int0_err10_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err11(unsigned int umsc_fifo_int0_err11); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err11_insrt(unsigned int umsc_fifo_int0_err11_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err12(unsigned int umsc_fifo_int0_err12); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err12_insrt(unsigned int umsc_fifo_int0_err12_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err13(unsigned int umsc_fifo_int0_err13); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err13_insrt(unsigned int umsc_fifo_int0_err13_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err14(unsigned int umsc_fifo_int0_err14); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err14_insrt(unsigned int umsc_fifo_int0_err14_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err15(unsigned int umsc_fifo_int0_err15); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err15_insrt(unsigned int umsc_fifo_int0_err15_insrt); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err0_en(unsigned int umsc_fifo_int0_err0_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err1_en(unsigned int umsc_fifo_int0_err1_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err2_en(unsigned int umsc_fifo_int0_err2_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err3_en(unsigned int umsc_fifo_int0_err3_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err4_en(unsigned int umsc_fifo_int0_err4_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err5_en(unsigned int umsc_fifo_int0_err5_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err6_en(unsigned int umsc_fifo_int0_err6_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err7_en(unsigned int umsc_fifo_int0_err7_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err8_en(unsigned int umsc_fifo_int0_err8_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err9_en(unsigned int umsc_fifo_int0_err9_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err10_en(unsigned int umsc_fifo_int0_err10_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err11_en(unsigned int umsc_fifo_int0_err11_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err12_en(unsigned int umsc_fifo_int0_err12_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err13_en(unsigned int umsc_fifo_int0_err13_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err14_en(unsigned int umsc_fifo_int0_err14_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err15_en(unsigned int umsc_fifo_int0_err15_en); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err0(unsigned int umsc_fifo_int1_err0); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err0_insrt(unsigned int umsc_fifo_int1_err0_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err1(unsigned int umsc_fifo_int1_err1); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err1_insrt(unsigned int umsc_fifo_int1_err1_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err2(unsigned int umsc_fifo_int1_err2); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err2_insrt(unsigned int umsc_fifo_int1_err2_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err3(unsigned int umsc_fifo_int1_err3); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err3_insrt(unsigned int umsc_fifo_int1_err3_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err4(unsigned int umsc_fifo_int1_err4); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err4_insrt(unsigned int umsc_fifo_int1_err4_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err5(unsigned int umsc_fifo_int1_err5); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err5_insrt(unsigned int umsc_fifo_int1_err5_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err6(unsigned int umsc_fifo_int1_err6); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err6_insrt(unsigned int umsc_fifo_int1_err6_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err7(unsigned int umsc_fifo_int1_err7); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err7_insrt(unsigned int umsc_fifo_int1_err7_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err8(unsigned int umsc_fifo_int1_err8); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err8_insrt(unsigned int umsc_fifo_int1_err8_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err9(unsigned int umsc_fifo_int1_err9); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err9_insrt(unsigned int umsc_fifo_int1_err9_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err10(unsigned int umsc_fifo_int1_err10); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err10_insrt(unsigned int umsc_fifo_int1_err10_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err11(unsigned int umsc_fifo_int1_err11); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err11_insrt(unsigned int umsc_fifo_int1_err11_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err12(unsigned int umsc_fifo_int1_err12); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err12_insrt(unsigned int umsc_fifo_int1_err12_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err13(unsigned int umsc_fifo_int1_err13); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err13_insrt(unsigned int umsc_fifo_int1_err13_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err14(unsigned int umsc_fifo_int1_err14); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err14_insrt(unsigned int umsc_fifo_int1_err14_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err15(unsigned int umsc_fifo_int1_err15); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err15_insrt(unsigned int umsc_fifo_int1_err15_insrt); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err0_en(unsigned int umsc_fifo_int1_err0_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err1_en(unsigned int umsc_fifo_int1_err1_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err2_en(unsigned int umsc_fifo_int1_err2_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err3_en(unsigned int umsc_fifo_int1_err3_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err4_en(unsigned int umsc_fifo_int1_err4_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err5_en(unsigned int umsc_fifo_int1_err5_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err6_en(unsigned int umsc_fifo_int1_err6_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err7_en(unsigned int umsc_fifo_int1_err7_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err8_en(unsigned int umsc_fifo_int1_err8_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err9_en(unsigned int umsc_fifo_int1_err9_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err10_en(unsigned int umsc_fifo_int1_err10_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err11_en(unsigned int umsc_fifo_int1_err11_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err12_en(unsigned int umsc_fifo_int1_err12_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err13_en(unsigned int umsc_fifo_int1_err13_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err14_en(unsigned int umsc_fifo_int1_err14_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err15_en(unsigned int umsc_fifo_int1_err15_en); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err0(unsigned int umsc_fifo_int2_err0); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err0_insrt(unsigned int umsc_fifo_int2_err0_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err1(unsigned int umsc_fifo_int2_err1); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err1_insrt(unsigned int umsc_fifo_int2_err1_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err2(unsigned int umsc_fifo_int2_err2); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err2_insrt(unsigned int umsc_fifo_int2_err2_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err3(unsigned int umsc_fifo_int2_err3); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err3_insrt(unsigned int umsc_fifo_int2_err3_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err4(unsigned int umsc_fifo_int2_err4); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err4_insrt(unsigned int umsc_fifo_int2_err4_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err5(unsigned int umsc_fifo_int2_err5); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err5_insrt(unsigned int umsc_fifo_int2_err5_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err6(unsigned int umsc_fifo_int2_err6); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err6_insrt(unsigned int umsc_fifo_int2_err6_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err7(unsigned int umsc_fifo_int2_err7); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err7_insrt(unsigned int umsc_fifo_int2_err7_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err8(unsigned int umsc_fifo_int2_err8); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err8_insrt(unsigned int umsc_fifo_int2_err8_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err9(unsigned int umsc_fifo_int2_err9); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err9_insrt(unsigned int umsc_fifo_int2_err9_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err10(unsigned int umsc_fifo_int2_err10); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err10_insrt(unsigned int umsc_fifo_int2_err10_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err11(unsigned int umsc_fifo_int2_err11); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err11_insrt(unsigned int umsc_fifo_int2_err11_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err12(unsigned int umsc_fifo_int2_err12); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err12_insrt(unsigned int umsc_fifo_int2_err12_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err13(unsigned int umsc_fifo_int2_err13); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err13_insrt(unsigned int umsc_fifo_int2_err13_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err14(unsigned int umsc_fifo_int2_err14); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err14_insrt(unsigned int umsc_fifo_int2_err14_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err15(unsigned int umsc_fifo_int2_err15); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err15_insrt(unsigned int umsc_fifo_int2_err15_insrt); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err0_en(unsigned int umsc_fifo_int2_err0_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err1_en(unsigned int umsc_fifo_int2_err1_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err2_en(unsigned int umsc_fifo_int2_err2_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err3_en(unsigned int umsc_fifo_int2_err3_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err4_en(unsigned int umsc_fifo_int2_err4_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err5_en(unsigned int umsc_fifo_int2_err5_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err6_en(unsigned int umsc_fifo_int2_err6_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err7_en(unsigned int umsc_fifo_int2_err7_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err8_en(unsigned int umsc_fifo_int2_err8_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err9_en(unsigned int umsc_fifo_int2_err9_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err10_en(unsigned int umsc_fifo_int2_err10_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err11_en(unsigned int umsc_fifo_int2_err11_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err12_en(unsigned int umsc_fifo_int2_err12_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err13_en(unsigned int umsc_fifo_int2_err13_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err14_en(unsigned int umsc_fifo_int2_err14_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err15_en(unsigned int umsc_fifo_int2_err15_en); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err0(unsigned int umsc_fifo_int3_err0); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err0_insrt(unsigned int umsc_fifo_int3_err0_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err1(unsigned int umsc_fifo_int3_err1); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err1_insrt(unsigned int umsc_fifo_int3_err1_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err2(unsigned int umsc_fifo_int3_err2); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err2_insrt(unsigned int umsc_fifo_int3_err2_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err3(unsigned int umsc_fifo_int3_err3); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err3_insrt(unsigned int umsc_fifo_int3_err3_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err4(unsigned int umsc_fifo_int3_err4); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err4_insrt(unsigned int umsc_fifo_int3_err4_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err5(unsigned int umsc_fifo_int3_err5); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err5_insrt(unsigned int umsc_fifo_int3_err5_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err6(unsigned int umsc_fifo_int3_err6); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err6_insrt(unsigned int umsc_fifo_int3_err6_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err7(unsigned int umsc_fifo_int3_err7); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err7_insrt(unsigned int umsc_fifo_int3_err7_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err8(unsigned int umsc_fifo_int3_err8); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err8_insrt(unsigned int umsc_fifo_int3_err8_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err9(unsigned int umsc_fifo_int3_err9); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err9_insrt(unsigned int umsc_fifo_int3_err9_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err10(unsigned int umsc_fifo_int3_err10); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err10_insrt(unsigned int umsc_fifo_int3_err10_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err11(unsigned int umsc_fifo_int3_err11); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err11_insrt(unsigned int umsc_fifo_int3_err11_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err12(unsigned int umsc_fifo_int3_err12); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err12_insrt(unsigned int umsc_fifo_int3_err12_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err13(unsigned int umsc_fifo_int3_err13); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err13_insrt(unsigned int umsc_fifo_int3_err13_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err14(unsigned int umsc_fifo_int3_err14); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err14_insrt(unsigned int umsc_fifo_int3_err14_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err15(unsigned int umsc_fifo_int3_err15); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err15_insrt(unsigned int umsc_fifo_int3_err15_insrt); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err0_en(unsigned int umsc_fifo_int3_err0_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err1_en(unsigned int umsc_fifo_int3_err1_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err2_en(unsigned int umsc_fifo_int3_err2_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err3_en(unsigned int umsc_fifo_int3_err3_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err4_en(unsigned int umsc_fifo_int3_err4_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err5_en(unsigned int umsc_fifo_int3_err5_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err6_en(unsigned int umsc_fifo_int3_err6_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err7_en(unsigned int umsc_fifo_int3_err7_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err8_en(unsigned int umsc_fifo_int3_err8_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err9_en(unsigned int umsc_fifo_int3_err9_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err10_en(unsigned int umsc_fifo_int3_err10_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err11_en(unsigned int umsc_fifo_int3_err11_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err12_en(unsigned int umsc_fifo_int3_err12_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err13_en(unsigned int umsc_fifo_int3_err13_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err14_en(unsigned int umsc_fifo_int3_err14_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err15_en(unsigned int umsc_fifo_int3_err15_en); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err0(unsigned int umsc_fifo_int4_err0); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err0_insrt(unsigned int umsc_fifo_int4_err0_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err1(unsigned int umsc_fifo_int4_err1); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err1_insrt(unsigned int umsc_fifo_int4_err1_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err2(unsigned int umsc_fifo_int4_err2); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err2_insrt(unsigned int umsc_fifo_int4_err2_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err3(unsigned int umsc_fifo_int4_err3); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err3_insrt(unsigned int umsc_fifo_int4_err3_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err4(unsigned int umsc_fifo_int4_err4); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err4_insrt(unsigned int umsc_fifo_int4_err4_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err5(unsigned int umsc_fifo_int4_err5); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err5_insrt(unsigned int umsc_fifo_int4_err5_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err6(unsigned int umsc_fifo_int4_err6); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err6_insrt(unsigned int umsc_fifo_int4_err6_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err7(unsigned int umsc_fifo_int4_err7); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err7_insrt(unsigned int umsc_fifo_int4_err7_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err8(unsigned int umsc_fifo_int4_err8); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err8_insrt(unsigned int umsc_fifo_int4_err8_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err9(unsigned int umsc_fifo_int4_err9); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err9_insrt(unsigned int umsc_fifo_int4_err9_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err10(unsigned int umsc_fifo_int4_err10); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err10_insrt(unsigned int umsc_fifo_int4_err10_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err11(unsigned int umsc_fifo_int4_err11); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err11_insrt(unsigned int umsc_fifo_int4_err11_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err12(unsigned int umsc_fifo_int4_err12); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err12_insrt(unsigned int umsc_fifo_int4_err12_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err13(unsigned int umsc_fifo_int4_err13); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err13_insrt(unsigned int umsc_fifo_int4_err13_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err14(unsigned int umsc_fifo_int4_err14); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err14_insrt(unsigned int umsc_fifo_int4_err14_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err15(unsigned int umsc_fifo_int4_err15); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err15_insrt(unsigned int umsc_fifo_int4_err15_insrt); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err0_en(unsigned int umsc_fifo_int4_err0_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err1_en(unsigned int umsc_fifo_int4_err1_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err2_en(unsigned int umsc_fifo_int4_err2_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err3_en(unsigned int umsc_fifo_int4_err3_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err4_en(unsigned int umsc_fifo_int4_err4_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err5_en(unsigned int umsc_fifo_int4_err5_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err6_en(unsigned int umsc_fifo_int4_err6_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err7_en(unsigned int umsc_fifo_int4_err7_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err8_en(unsigned int umsc_fifo_int4_err8_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err9_en(unsigned int umsc_fifo_int4_err9_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err10_en(unsigned int umsc_fifo_int4_err10_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err11_en(unsigned int umsc_fifo_int4_err11_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err12_en(unsigned int umsc_fifo_int4_err12_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err13_en(unsigned int umsc_fifo_int4_err13_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err14_en(unsigned int umsc_fifo_int4_err14_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err15_en(unsigned int umsc_fifo_int4_err15_en); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err0(unsigned int umsc_fifo_int5_err0); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err0_insrt(unsigned int umsc_fifo_int5_err0_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err1(unsigned int umsc_fifo_int5_err1); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err1_insrt(unsigned int umsc_fifo_int5_err1_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err2(unsigned int umsc_fifo_int5_err2); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err2_insrt(unsigned int umsc_fifo_int5_err2_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err3(unsigned int umsc_fifo_int5_err3); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err3_insrt(unsigned int umsc_fifo_int5_err3_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err4(unsigned int umsc_fifo_int5_err4); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err4_insrt(unsigned int umsc_fifo_int5_err4_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err5(unsigned int umsc_fifo_int5_err5); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err5_insrt(unsigned int umsc_fifo_int5_err5_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err6(unsigned int umsc_fifo_int5_err6); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err6_insrt(unsigned int umsc_fifo_int5_err6_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err7(unsigned int umsc_fifo_int5_err7); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err7_insrt(unsigned int umsc_fifo_int5_err7_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err8(unsigned int umsc_fifo_int5_err8); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err8_insrt(unsigned int umsc_fifo_int5_err8_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err9(unsigned int umsc_fifo_int5_err9); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err9_insrt(unsigned int umsc_fifo_int5_err9_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err10(unsigned int umsc_fifo_int5_err10); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err10_insrt(unsigned int umsc_fifo_int5_err10_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err11(unsigned int umsc_fifo_int5_err11); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err11_insrt(unsigned int umsc_fifo_int5_err11_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err12(unsigned int umsc_fifo_int5_err12); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err12_insrt(unsigned int umsc_fifo_int5_err12_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err13(unsigned int umsc_fifo_int5_err13); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err13_insrt(unsigned int umsc_fifo_int5_err13_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err14(unsigned int umsc_fifo_int5_err14); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err14_insrt(unsigned int umsc_fifo_int5_err14_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err15(unsigned int umsc_fifo_int5_err15); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err15_insrt(unsigned int umsc_fifo_int5_err15_insrt); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err0_en(unsigned int umsc_fifo_int5_err0_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err1_en(unsigned int umsc_fifo_int5_err1_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err2_en(unsigned int umsc_fifo_int5_err2_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err3_en(unsigned int umsc_fifo_int5_err3_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err4_en(unsigned int umsc_fifo_int5_err4_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err5_en(unsigned int umsc_fifo_int5_err5_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err6_en(unsigned int umsc_fifo_int5_err6_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err7_en(unsigned int umsc_fifo_int5_err7_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err8_en(unsigned int umsc_fifo_int5_err8_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err9_en(unsigned int umsc_fifo_int5_err9_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err10_en(unsigned int umsc_fifo_int5_err10_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err11_en(unsigned int umsc_fifo_int5_err11_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err12_en(unsigned int umsc_fifo_int5_err12_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err13_en(unsigned int umsc_fifo_int5_err13_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err14_en(unsigned int umsc_fifo_int5_err14_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err15_en(unsigned int umsc_fifo_int5_err15_en); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err0(unsigned int umsc_fifo_int6_err0); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err0_insrt(unsigned int umsc_fifo_int6_err0_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err1(unsigned int umsc_fifo_int6_err1); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err1_insrt(unsigned int umsc_fifo_int6_err1_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err2(unsigned int umsc_fifo_int6_err2); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err2_insrt(unsigned int umsc_fifo_int6_err2_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err3(unsigned int umsc_fifo_int6_err3); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err3_insrt(unsigned int umsc_fifo_int6_err3_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err4(unsigned int umsc_fifo_int6_err4); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err4_insrt(unsigned int umsc_fifo_int6_err4_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err5(unsigned int umsc_fifo_int6_err5); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err5_insrt(unsigned int umsc_fifo_int6_err5_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err6(unsigned int umsc_fifo_int6_err6); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err6_insrt(unsigned int umsc_fifo_int6_err6_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err7(unsigned int umsc_fifo_int6_err7); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err7_insrt(unsigned int umsc_fifo_int6_err7_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err8(unsigned int umsc_fifo_int6_err8); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err8_insrt(unsigned int umsc_fifo_int6_err8_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err9(unsigned int umsc_fifo_int6_err9); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err9_insrt(unsigned int umsc_fifo_int6_err9_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err10(unsigned int umsc_fifo_int6_err10); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err10_insrt(unsigned int umsc_fifo_int6_err10_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err11(unsigned int umsc_fifo_int6_err11); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err11_insrt(unsigned int umsc_fifo_int6_err11_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err12(unsigned int umsc_fifo_int6_err12); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err12_insrt(unsigned int umsc_fifo_int6_err12_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err13(unsigned int umsc_fifo_int6_err13); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err13_insrt(unsigned int umsc_fifo_int6_err13_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err14(unsigned int umsc_fifo_int6_err14); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err14_insrt(unsigned int umsc_fifo_int6_err14_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err15(unsigned int umsc_fifo_int6_err15); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err15_insrt(unsigned int umsc_fifo_int6_err15_insrt); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err0_en(unsigned int umsc_fifo_int6_err0_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err1_en(unsigned int umsc_fifo_int6_err1_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err2_en(unsigned int umsc_fifo_int6_err2_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err3_en(unsigned int umsc_fifo_int6_err3_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err4_en(unsigned int umsc_fifo_int6_err4_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err5_en(unsigned int umsc_fifo_int6_err5_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err6_en(unsigned int umsc_fifo_int6_err6_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err7_en(unsigned int umsc_fifo_int6_err7_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err8_en(unsigned int umsc_fifo_int6_err8_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err9_en(unsigned int umsc_fifo_int6_err9_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err10_en(unsigned int umsc_fifo_int6_err10_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err11_en(unsigned int umsc_fifo_int6_err11_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err12_en(unsigned int umsc_fifo_int6_err12_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err13_en(unsigned int umsc_fifo_int6_err13_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err14_en(unsigned int umsc_fifo_int6_err14_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err15_en(unsigned int umsc_fifo_int6_err15_en); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err0(unsigned int umsc_fifo_int7_err0); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err0_insrt(unsigned int umsc_fifo_int7_err0_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err1(unsigned int umsc_fifo_int7_err1); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err1_insrt(unsigned int umsc_fifo_int7_err1_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err2(unsigned int umsc_fifo_int7_err2); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err2_insrt(unsigned int umsc_fifo_int7_err2_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err3(unsigned int umsc_fifo_int7_err3); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err3_insrt(unsigned int umsc_fifo_int7_err3_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err4(unsigned int umsc_fifo_int7_err4); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err4_insrt(unsigned int umsc_fifo_int7_err4_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err5(unsigned int umsc_fifo_int7_err5); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err5_insrt(unsigned int umsc_fifo_int7_err5_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err6(unsigned int umsc_fifo_int7_err6); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err6_insrt(unsigned int umsc_fifo_int7_err6_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err7(unsigned int umsc_fifo_int7_err7); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err7_insrt(unsigned int umsc_fifo_int7_err7_insrt); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err0_en(unsigned int umsc_fifo_int7_err0_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err1_en(unsigned int umsc_fifo_int7_err1_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err2_en(unsigned int umsc_fifo_int7_err2_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err3_en(unsigned int umsc_fifo_int7_err3_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err4_en(unsigned int umsc_fifo_int7_err4_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err5_en(unsigned int umsc_fifo_int7_err5_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err6_en(unsigned int umsc_fifo_int7_err6_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err7_en(unsigned int umsc_fifo_int7_err7_en); +int iSetMSC_BP_DELAY_CNT_msc_bp_delay_cnt(unsigned int umsc_bp_delay_cnt); +int iSetMSC_VF_SP_CNT_EN_vf_sp_cnt_flag_en(unsigned int uvf_sp_cnt_flag_en); +int iSetMSC_VF_SP_CNT_EN_socep_sp_cnt_flag_en(unsigned int usocep_sp_cnt_flag_en); +int iSetPRESUB_PKTLEN_NS_STF_presub_pktlen_ns_stf(unsigned int upresub_pktlen_ns_stf); +int iSetPRESUB_PKTLEN_NS_STL_presub_pktlen_ns_stl(unsigned int upresub_pktlen_ns_stl); +int iSetCMQ_PRESUB_PKTLEN_CS_cmq_presub_pktlen_cs(unsigned int ucmq_presub_pktlen_cs); +int iSetNFMQ_PRESUB_PKTLEN_CS_nfmq_presub_pktlen_cs(unsigned int unfmq_presub_pktlen_cs); +int iSetPRESUB_PKTNUM_presub_pktnum_ns_stl(unsigned int upresub_pktnum_ns_stl); +int iSetPRESUB_PKTNUM_presub_pktnum_ns_stf(unsigned int upresub_pktnum_ns_stf); +int iSetPRESUB_PKTNUM_presub_pktnum_cs_cmq(unsigned int upresub_pktnum_cs_cmq); +int iSetPRESUB_PKTNUM_presub_pktnum_cs_nfmq(unsigned int upresub_pktnum_cs_nfmq); +int iSetPRESUB_PKTLEN_SOCNMQ_presub_pktlen_socnmq(unsigned int upresub_pktlen_socnmq); +int iSetPRESUB_PKTLEN_SOCCMQ_presub_pktlen_soccmq(unsigned int upresub_pktlen_soccmq); +int iSetPRESUB_PKTNUM_SOC_presub_pktnum_socnmq(unsigned int upresub_pktnum_socnmq); +int iSetPRESUB_PKTNUM_SOC_presub_pktnum_soccmq(unsigned int upresub_pktnum_soccmq); +int iSetMSC_PPS_SHAPER_CFG_PKTLEN_msc_pps_typical_pktlen_cfg(unsigned int umsc_pps_typical_pktlen_cfg); +int iSetMSC_ROOT_CRR_WEIGHT_CFG_msc_crr_weight_cfg_ns(unsigned int umsc_crr_weight_cfg_ns); +int iSetMSC_ROOT_CRR_WEIGHT_CFG_msc_crr_weight_cfg_cs(unsigned int umsc_crr_weight_cfg_cs); +int iSetSOCMSC_ROOT_SCH_WGT_CFG_socmsc_rt_sch_wgt_cfg(unsigned int usocmsc_rt_sch_wgt_cfg); +int iSetWEIGHT_NS_OFFSET_cos_weight_ns_offset(unsigned int ucos_weight_ns_offset); +int iSetWEIGHT_NS_OFFSET_ep_weight_ns_offset(unsigned int uep_weight_ns_offset); +int iSetWEIGHT_NS_OFFSET_host_weight_ns_offset(unsigned int uhost_weight_ns_offset); +int iSetWEIGHT_CS_OFFSET_nfmq_cos_weight_cs_offset(unsigned int unfmq_cos_weight_cs_offset); +int iSetWEIGHT_CS_OFFSET_cmq_cos_weight_cs_offset(unsigned int ucmq_cos_weight_cs_offset); +int iSetWEIGHT_CS_OFFSET_ep_weight_cs_offset(unsigned int uep_weight_cs_offset); +int iSetWEIGHT_CS_OFFSET_host_weight_cs_offset(unsigned int uhost_weight_cs_offset); +int iSetWEIGHT_MSCSOC_OFFSET_soc_mq_weight_offset(unsigned int usoc_mq_weight_offset); +int iSetWEIGHT_MSCSOC_OFFSET_soc_ep_weight_offset(unsigned int usoc_ep_weight_offset); +int iSetWEIGHT_MSCSOC_OFFSET_soc_serv_weight_offset(unsigned int usoc_serv_weight_offset); +int iSetHOST_WEIGHT_NS_host_weight_ns_0(unsigned int uhost_weight_ns_0); +int iSetHOST_WEIGHT_NS_host_weight_ns_1(unsigned int uhost_weight_ns_1); +int iSetHOST_WEIGHT_NS_host_weight_ns_2(unsigned int uhost_weight_ns_2); +int iSetHOST_WEIGHT_NS_host_weight_ns_3(unsigned int uhost_weight_ns_3); +int iSetHOST_WEIGHT_CS_host_weight_cs_0(unsigned int uhost_weight_cs_0); +int iSetHOST_WEIGHT_CS_host_weight_cs_1(unsigned int uhost_weight_cs_1); +int iSetHOST_WEIGHT_CS_host_weight_cs_2(unsigned int uhost_weight_cs_2); +int iSetHOST_WEIGHT_CS_host_weight_cs_3(unsigned int uhost_weight_cs_3); +int iSetQA_WEIGHT_CFG_CS_msc_qa_weight_cfg_cs(unsigned int umsc_qa_weight_cfg_cs); +int iSetEP_WEIGHT_CFG_NS_mscep_weight_cfg_ns(unsigned int umscep_weight_cfg_ns); +int iSetEP_WEIGHT_CFG_CMQ_mscep_weight_cfg_cmq(unsigned int umscep_weight_cfg_cmq); +int iSetEP_WEIGHT_CFG_NFMQ_mscep_weight_cfg_nfmq(unsigned int umscep_weight_cfg_nfmq); +int iSetSOC_MQ_WEIGHT_CFG_socmq_weight_cfg(unsigned int usocmq_weight_cfg); +int iSetSOC_EP_WEIGHT_CFG_socep_weight_cfg(unsigned int usocep_weight_cfg); +int iSetSOC_SERV_WEIGHT_CFG_socserv_weight_cfg(unsigned int usocserv_weight_cfg); +int iSetHOST_SHAP_BPS_CFG_CS_host_shap_bps_cfg_cs(unsigned int uhost_shap_bps_cfg_cs); +int iSetHOST_SHAP_PPS_CFG_CS_host_shap_pps_cfg_cs(unsigned int uhost_shap_pps_cfg_cs); +int iSetHOST_SHAP_BPS_CFG_NS_host_shap_bps_cfg_ns(unsigned int uhost_shap_bps_cfg_ns); +int iSetHOST_SHAP_PPS_CFG_NS_host_shap_pps_cfg_ns(unsigned int uhost_shap_pps_cfg_ns); +int iSetEP_SHAP_BPS_CFG_NS_ep_shap_bps_cfg_ns(unsigned int uep_shap_bps_cfg_ns); +int iSetEP_SHAP_PPS_CFG_NS_ep_shap_pps_cfg_ns(unsigned int uep_shap_pps_cfg_ns); +int iSetEP_SHAP_BPS_CFG_CMQ_ep_shap_bps_cfg_cmq(unsigned int uep_shap_bps_cfg_cmq); +int iSetEP_SHAP_PPS_CFG_CMQ_ep_shap_pps_cfg_cmq(unsigned int uep_shap_pps_cfg_cmq); +int iSetEP_SHAP_BPS_CFG_NFMQ_ep_shap_bps_cfg_nfmq(unsigned int uep_shap_bps_cfg_nfmq); +int iSetEP_SHAP_PPS_CFG_NFMQ_ep_shap_pps_cfg_nfmq(unsigned int uep_shap_pps_cfg_nfmq); +int iSetSOCMQ_SHAP_BPS_CFG_socmq_shap_bps_cfg(unsigned int usocmq_shap_bps_cfg); +int iSetSOCMQ_SHAP_PPS_CFG_socmq_shap_pps_cfg(unsigned int usocmq_shap_pps_cfg); +int iSetSOCEP_SHAP_BPS_CFG_socep_shap_bps_cfg(unsigned int usocep_shap_bps_cfg); +int iSetSOCEP_SHAP_PPS_CFG_socep_shap_pps_cfg(unsigned int usocep_shap_pps_cfg); +int iSetSOCSERV_SHAP_BPS_CFG_socserv_shap_bps_cfg(unsigned int usocserv_shap_bps_cfg); +int iSetSOCSERV_SHAP_PPS_CFG_socserv_shap_pps_cfg(unsigned int usocserv_shap_pps_cfg); +int iSetSOCRT_SHAP_BPS_CFG_socrt_shap_bps_cfg(unsigned int usocrt_shap_bps_cfg); +int iSetSOCRT_SHAP_PPS_CFG_socrt_shap_pps_cfg(unsigned int usocrt_shap_pps_cfg); +int iSetMSC_SHAP_BYPASS_CFG_msc_nmq_shap_byp_vld(unsigned int umsc_nmq_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_vnic_shap_byp_vld(unsigned int umsc_ns_vnic_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_vnicgrp_shap_byp_vld(unsigned int umsc_ns_vnicgrp_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_ep_shap_byp_vld(unsigned int umsc_ns_ep_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_host_shap_byp_vld(unsigned int umsc_ns_host_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_cmq_shap_byp_vld(unsigned int umsc_cmq_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_nfmq_vnic_shap_byp_vld(unsigned int umsc_nfmq_vnic_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_cs_ep_shap_byp_vld(unsigned int umsc_cs_ep_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_cs_host_shap_byp_vld(unsigned int umsc_cs_host_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_mq_shap_byp_vld(unsigned int usocmsc_mq_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_ep_shap_byp_vld(unsigned int usocmsc_ep_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_serv_shap_byp_vld(unsigned int usocmsc_serv_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_rt_shap_byp_vld(unsigned int usocmsc_rt_shap_byp_vld); +int iSetMSC_HOST_ROOT_XON_CFG_msc_host_xon_cfg_ns(unsigned int umsc_host_xon_cfg_ns); +int iSetMSC_HOST_ROOT_XON_CFG_msc_host_xon_cfg_cs(unsigned int umsc_host_xon_cfg_cs); +int iSetMSC_HOST_ROOT_XON_CFG_msc_root_xon_cfg_ns(unsigned int umsc_root_xon_cfg_ns); +int iSetMSC_HOST_ROOT_XON_CFG_msc_root_xon_cfg_cs(unsigned int umsc_root_xon_cfg_cs); +int iSetMSC_HOST_ROOT_XON_CFG_msc_root_xon_cfg(unsigned int umsc_root_xon_cfg); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_ep_xon_cfg_ns(unsigned int usocmsc_ep_xon_cfg_ns); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_ep_xon_cfg_cs(unsigned int usocmsc_ep_xon_cfg_cs); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_root_xon_cfg_ns(unsigned int usocmsc_root_xon_cfg_ns); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_root_xon_cfg_cs(unsigned int usocmsc_root_xon_cfg_cs); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_root_xon_cfg(unsigned int usocmsc_root_xon_cfg); +int iSetMSC_HOST_EP_XON_CFG_NS_msc_hostep_xon_cfg_ns(unsigned int umsc_hostep_xon_cfg_ns); +int iSetMSC_HOST_EP_XON_CFG_NFMQ_msc_hostep_xon_cfg_nfmq(unsigned int umsc_hostep_xon_cfg_nfmq); +int iSetMSC_HOST_EP_XON_CFG_CMQ_msc_hostep_xon_cfg_cmq(unsigned int umsc_hostep_xon_cfg_cmq); +int iSetSOCMSC_MQ_XON_CFG_NS_socmsc_mq_xon_cfg(unsigned int usocmsc_mq_xon_cfg); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_dp_ep_bp(unsigned int uprm_mqm_dp_ep_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_cp_ep_bp(unsigned int uprm_mqm_cp_ep_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_dp_root_bp(unsigned int uprm_mqm_dp_root_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_cp_root_bp(unsigned int uprm_mqm_cp_root_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_root_bp(unsigned int uprm_mqm_root_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_dp_cos_bp(unsigned int uprm_mqm_soc_dp_cos_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_cp_cos_bp(unsigned int uprm_mqm_soc_cp_cos_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_dp_root_bp(unsigned int uprm_mqm_soc_dp_root_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_cp_root_bp(unsigned int uprm_mqm_soc_cp_root_bp); +int iSetMSC_QU_COS_BP_STA0_prm_mqm_dp_ep_cos_bp0(unsigned int uprm_mqm_dp_ep_cos_bp0); +int iSetMSC_QU_COS_BP_STA1_prm_mqm_dp_ep_cos_bp1(unsigned int uprm_mqm_dp_ep_cos_bp1); +int iSetSOCMSC_RT_EP_BP_STA_socmsc_el_bp(unsigned int usocmsc_el_bp); +int iSetSOCMSC_RT_EP_BP_STA_socmsc_sl_bp(unsigned int usocmsc_sl_bp); +int iSetSOCMSC_RT_EP_BP_STA_socmsc_rl_bp(unsigned int usocmsc_rl_bp); +int iSetSOCMSC_QUEUE_BP_STA0_socmsc_ql_bp0(unsigned int usocmsc_ql_bp0); +int iSetSOCMSC_QUEUE_BP_STA1_socmsc_ql_bp1(unsigned int usocmsc_ql_bp1); +int iSetSOCMSC_QUEUE_BP_STA2_socmsc_ql_bp2(unsigned int usocmsc_ql_bp2); +int iSetSOCMSC_QUEUE_BP_STA3_socmsc_ql_bp3(unsigned int usocmsc_ql_bp3); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA0_socmsc_ql_eligible0(unsigned int usocmsc_ql_eligible0); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA1_socmsc_ql_eligible1(unsigned int usocmsc_ql_eligible1); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA2_socmsc_ql_eligible2(unsigned int usocmsc_ql_eligible2); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA3_socmsc_ql_eligible3(unsigned int usocmsc_ql_eligible3); +int iSetMSC_RT_HOST_BP_STA_msc_ns_hl_bp(unsigned int umsc_ns_hl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_cs_hl_bp(unsigned int umsc_cs_hl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_ns_sl_bp(unsigned int umsc_ns_sl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_cs_sl_bp(unsigned int umsc_cs_sl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_rl_bp(unsigned int umsc_rl_bp); +int iSetMSC_RT_HOST_BP_STA_enqc_msc_dp_bp(unsigned int uenqc_msc_dp_bp); +int iSetMSC_RT_HOST_BP_STA_enqc_msc_cp_bp(unsigned int uenqc_msc_cp_bp); +int iSetMSC_HOSTEP_NS_BP_STA_msc_host_ep_ns_bp(unsigned int umsc_host_ep_ns_bp); +int iSetMSC_HOSTEP_NFMQ_BP_STA_msc_host_ep_nfmq_bp(unsigned int umsc_host_ep_nfmq_bp); +int iSetMSC_HOSTEP_CMQ_BP_STA_msc_host_ep_cmq_bp(unsigned int umsc_host_ep_cmq_bp); +int iSetMSC_FIFO_TH_CFG_msc_ns_du_fifo_gap(unsigned int umsc_ns_du_fifo_gap); +int iSetMSC_FIFO_TH_CFG_msc_cs_du_fifo_gap(unsigned int umsc_cs_du_fifo_gap); +int iSetMSC_FIFO_TH_CFG_socmsc_du_fifo_gap(unsigned int usocmsc_du_fifo_gap); +int iSetMSC_FIFO_TH_CFG_msc_fast_cnp_fifo_gap(unsigned int umsc_fast_cnp_fifo_gap); +int iSetMSC_FIFO_ST0_msc_fifo0_st0(unsigned int umsc_fifo0_st0); +int iSetMSC_FIFO_ST0_msc_fifo1_st0(unsigned int umsc_fifo1_st0); +int iSetMSC_FIFO_ST0_msc_fifo2_st0(unsigned int umsc_fifo2_st0); +int iSetMSC_FIFO_ST0_msc_fifo3_st0(unsigned int umsc_fifo3_st0); +int iSetMSC_FIFO_ST0_msc_fifo4_st0(unsigned int umsc_fifo4_st0); +int iSetMSC_FIFO_ST0_msc_fifo5_st0(unsigned int umsc_fifo5_st0); +int iSetMSC_FIFO_ST0_msc_fifo6_st0(unsigned int umsc_fifo6_st0); +int iSetMSC_FIFO_ST0_msc_fifo7_st0(unsigned int umsc_fifo7_st0); +int iSetMSC_FIFO_ST0_msc_fifo8_st0(unsigned int umsc_fifo8_st0); +int iSetMSC_FIFO_ST0_msc_fifo9_st0(unsigned int umsc_fifo9_st0); +int iSetMSC_FIFO_ST0_msc_fifo10_st0(unsigned int umsc_fifo10_st0); +int iSetMSC_FIFO_ST0_msc_fifo11_st0(unsigned int umsc_fifo11_st0); +int iSetMSC_FIFO_ST0_msc_fifo12_st0(unsigned int umsc_fifo12_st0); +int iSetMSC_FIFO_ST0_msc_fifo13_st0(unsigned int umsc_fifo13_st0); +int iSetMSC_FIFO_ST0_msc_fifo14_st0(unsigned int umsc_fifo14_st0); +int iSetMSC_FIFO_ST0_msc_fifo15_st0(unsigned int umsc_fifo15_st0); +int iSetMSC_FIFO_ST1_msc_fifo0_st1(unsigned int umsc_fifo0_st1); +int iSetMSC_FIFO_ST1_msc_fifo1_st1(unsigned int umsc_fifo1_st1); +int iSetMSC_FIFO_ST1_msc_fifo2_st1(unsigned int umsc_fifo2_st1); +int iSetMSC_FIFO_ST1_msc_fifo3_st1(unsigned int umsc_fifo3_st1); +int iSetMSC_FIFO_ST1_msc_fifo4_st1(unsigned int umsc_fifo4_st1); +int iSetMSC_FIFO_ST1_msc_fifo5_st1(unsigned int umsc_fifo5_st1); +int iSetMSC_FIFO_ST1_msc_fifo6_st1(unsigned int umsc_fifo6_st1); +int iSetMSC_FIFO_ST1_msc_fifo7_st1(unsigned int umsc_fifo7_st1); +int iSetMSC_FIFO_ST1_msc_fifo8_st1(unsigned int umsc_fifo8_st1); +int iSetMSC_FIFO_ST1_msc_fifo9_st1(unsigned int umsc_fifo9_st1); +int iSetMSC_FIFO_ST1_msc_fifo10_st1(unsigned int umsc_fifo10_st1); +int iSetMSC_FIFO_ST1_msc_fifo11_st1(unsigned int umsc_fifo11_st1); +int iSetMSC_FIFO_ST1_msc_fifo12_st1(unsigned int umsc_fifo12_st1); +int iSetMSC_FIFO_ST1_msc_fifo13_st1(unsigned int umsc_fifo13_st1); +int iSetMSC_FIFO_ST1_msc_fifo14_st1(unsigned int umsc_fifo14_st1); +int iSetMSC_FIFO_ST1_msc_fifo15_st1(unsigned int umsc_fifo15_st1); +int iSetMSC_FIFO_ST2_msc_fifo0_st2(unsigned int umsc_fifo0_st2); +int iSetMSC_FIFO_ST2_msc_fifo1_st2(unsigned int umsc_fifo1_st2); +int iSetMSC_FIFO_ST2_msc_fifo2_st2(unsigned int umsc_fifo2_st2); +int iSetMSC_FIFO_ST2_msc_fifo3_st2(unsigned int umsc_fifo3_st2); +int iSetMSC_FIFO_ST2_msc_fifo4_st2(unsigned int umsc_fifo4_st2); +int iSetMSC_FIFO_ST2_msc_fifo5_st2(unsigned int umsc_fifo5_st2); +int iSetMSC_FIFO_ST2_msc_fifo6_st2(unsigned int umsc_fifo6_st2); +int iSetMSC_FIFO_ST2_msc_fifo7_st2(unsigned int umsc_fifo7_st2); +int iSetMSC_FIFO_ST2_msc_fifo8_st2(unsigned int umsc_fifo8_st2); +int iSetMSC_FIFO_ST2_msc_fifo9_st2(unsigned int umsc_fifo9_st2); +int iSetMSC_FIFO_ST2_msc_fifo10_st2(unsigned int umsc_fifo10_st2); +int iSetMSC_FIFO_ST2_msc_fifo11_st2(unsigned int umsc_fifo11_st2); +int iSetMSC_FIFO_ST2_msc_fifo12_st2(unsigned int umsc_fifo12_st2); +int iSetMSC_FIFO_ST2_msc_fifo13_st2(unsigned int umsc_fifo13_st2); +int iSetMSC_FIFO_ST2_msc_fifo14_st2(unsigned int umsc_fifo14_st2); +int iSetMSC_FIFO_ST2_msc_fifo15_st2(unsigned int umsc_fifo15_st2); +int iSetMSC_FIFO_ST3_msc_fifo0_st3(unsigned int umsc_fifo0_st3); +int iSetMSC_FIFO_ST3_msc_fifo1_st3(unsigned int umsc_fifo1_st3); +int iSetMSC_FIFO_ST3_msc_fifo2_st3(unsigned int umsc_fifo2_st3); +int iSetMSC_FIFO_ST3_msc_fifo3_st3(unsigned int umsc_fifo3_st3); +int iSetMSC_FIFO_ST3_msc_fifo4_st3(unsigned int umsc_fifo4_st3); +int iSetMSC_FIFO_ST3_msc_fifo5_st3(unsigned int umsc_fifo5_st3); +int iSetMSC_FIFO_ST3_msc_fifo6_st3(unsigned int umsc_fifo6_st3); +int iSetMSC_FIFO_ST3_msc_fifo7_st3(unsigned int umsc_fifo7_st3); +int iSetMSC_FIFO_ST3_msc_fifo8_st3(unsigned int umsc_fifo8_st3); +int iSetMSC_FIFO_ST3_msc_fifo9_st3(unsigned int umsc_fifo9_st3); +int iSetMSC_FIFO_ST3_msc_fifo10_st3(unsigned int umsc_fifo10_st3); +int iSetMSC_FIFO_ST3_msc_fifo11_st3(unsigned int umsc_fifo11_st3); +int iSetCMQ_RX_UP_CNT_cmq_up_cnt(unsigned int ucmq_up_cnt); +int iSetNFMQ_RX_UP_CNT_nfmq_up_cnt(unsigned int unfmq_up_cnt); +int iSetNMQ_RX_UP_CNT_nmq_up_cnt(unsigned int unmq_up_cnt); +int iSetCMQ_SCH_CNT_cmq_sch_cnt(unsigned int ucmq_sch_cnt); +int iSetNFMQ_SCH_CNT_nfmq_sch_cnt(unsigned int unfmq_sch_cnt); +int iSetNMQ_SCH_CNT_nmq_sch_cnt(unsigned int unmq_sch_cnt); +int iSetSOCCMQ_UP_CNT_soccmq_up_cnt(unsigned int usoccmq_up_cnt); +int iSetSOCNMQ_UP_CNT_socnmq_up_cnt(unsigned int usocnmq_up_cnt); +int iSetSOCCMQ_SCH_CNT_soccmq_sch_cnt(unsigned int usoccmq_sch_cnt); +int iSetSOCNMQ_SCH_CNT_socnmq_sch_cnt(unsigned int usocnmq_sch_cnt); +int iSetCMQ_EMPT_SCH_CNT_cmq_empt_sch_cnt(unsigned int ucmq_empt_sch_cnt); +int iSetNFMQ_EMPT_SCH_CNT_nfmq_empt_sch_cnt(unsigned int unfmq_empt_sch_cnt); +int iSetNMQ_EMPT_SCH_CNT_nmq_empt_sch_cnt(unsigned int unmq_empt_sch_cnt); +int iSetCMQ_RX_DU_CNT_cmq_du_cnt(unsigned int ucmq_du_cnt); +int iSetNFMQ_RX_DU_CNT_nfmq_du_cnt(unsigned int unfmq_du_cnt); +int iSetNMQ_RX_DU_CNT_nmq_du_cnt(unsigned int unmq_du_cnt); +int iSetSOCCMQ_DU_CNT_soccmq_du_cnt(unsigned int usoccmq_du_cnt); +int iSetSOCNMQ_DU_CNT_socnmq_du_cnt(unsigned int usocnmq_du_cnt); +int iSetMSC_ECC_1BIT_ERR_CNT_msc_ecc_1bit_err_cnt(unsigned int umsc_ecc_1bit_err_cnt); +int iSetMSC_ECC_2BIT_ERR_CNT_msc_ecc_2bit_err_cnt(unsigned int umsc_ecc_2bit_err_cnt); +int iSetSCH_MQ_DFX_CFG_sch_mq_dfx_cfg(unsigned int usch_mq_dfx_cfg); +int iSetSCH_MQ_DFX_CFG_sch_mq_qa_dfx_cfg(unsigned int usch_mq_qa_dfx_cfg); +int iSetSCH_MQ_DFX_CFG_sch_mq_dfx_cfg_vld(unsigned int usch_mq_dfx_cfg_vld); +int iSetSCH_MQ_DFX_UP_CNT_sch_mq_dfx_up_cnt(unsigned int usch_mq_dfx_up_cnt); +int iSetSCH_MQ_DFX_SCH_CNT_sch_mq_dfx_sch_cnt(unsigned int usch_mq_dfx_sch_cnt); +int iSetSCH_MQ_DFX_EMPT_SCH_CNT_sch_mq_dfx_empt_sch_cnt(unsigned int usch_mq_dfx_empt_sch_cnt); +int iSetSCH_MQ_DFX_DU_CNT_sch_mq_dfx_du_cnt(unsigned int usch_mq_dfx_du_cnt); +int iSetSCH_SOCMQ_DFX_CFG_sch_socmq_dfx_cfg(unsigned int usch_socmq_dfx_cfg); +int iSetSCH_SOCMQ_DFX_CFG_sch_socmq_dfx_cfg_vld(unsigned int usch_socmq_dfx_cfg_vld); +int iSetSCH_SOCMQ_DFX_UP_CNT_sch_socmq_dfx_up_cnt(unsigned int usch_socmq_dfx_up_cnt); +int iSetSCH_SOCMQ_DFX_SCH_CNT_sch_socmq_dfx_sch_cnt(unsigned int usch_socmq_dfx_sch_cnt); +int iSetSCH_SOCMQ_DFX_DU_CNT_sch_socmq_dfx_du_cnt(unsigned int usch_socmq_dfx_du_cnt); +int iSetSOCMSC_MCD_DU_INFO_PTR0_socmsc_mcd_len_info(unsigned int usocmsc_mcd_len_info); +int iSetSOCMSC_MCD_DU_INFO_PTR1_socmsc_mcd_id_info(unsigned int usocmsc_mcd_id_info); +int iSetMSC_CS_MCD_DU_INFO_PTR0_msc_mcd_cs_len_info(unsigned int umsc_mcd_cs_len_info); +int iSetMSC_CS_MCD_DU_INFO_PTR1_msc_mcd_cs_id_info_0(unsigned int umsc_mcd_cs_id_info_0); +int iSetMSC_CS_MCD_DU_INFO_PTR2_msc_mcd_cs_id_info_1(unsigned int umsc_mcd_cs_id_info_1); +int iSetMSC_NS_MCD_DU_INFO_PTR0_msc_mcd_ns_len_info(unsigned int umsc_mcd_ns_len_info); +int iSetMSC_NS_MCD_DU_INFO_PTR1_msc_mcd_ns_id_info_0(unsigned int umsc_mcd_ns_id_info_0); +int iSetMSC_NS_MCD_DU_INFO_PTR2_msc_mcd_ns_id_info_1(unsigned int umsc_mcd_ns_id_info_1); + +/* Define the union csr_deqc_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv0_u; + +/* Define the union csr_deqc_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv1_u; + +/* Define the union csr_deqc_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv2_u; + +/* Define the union csr_deqc_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv3_u; + +/* Define the union csr_deqc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_indrect_addr : 24; /* [23:0] */ + u32 deqc_indrect_tab : 4; /* [27:24] */ + u32 deqc_indrect_stat : 2; /* [29:28] */ + u32 deqc_indrect_mode : 1; /* [30] */ + u32 deqc_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_indrect_ctrl_u; + +/* Define the union csr_deqc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_indrect_timeout_u; + +/* Define the union csr_deqc_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_indrect_data_u; + +/* Define the union csr_deqc_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ecc_bypass_en_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_deqc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 deqc_enable : 1; /* [27] */ + u32 deqc_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_int_vector_u; + +/* Define the union csr_deqc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 deqc_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_int_u; + +/* Define the union csr_deqc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_int_en : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 deqc_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_int_en_u; + +/* Define the union csr_deqc_mem_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_1bit_err : 1; /* [0] */ + u32 deqc_ecc_1bit_err_insrt : 1; /* [1] */ + u32 deqc_ecc_1bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_1bit_err_u; + +/* Define the union csr_deqc_mem_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_2bit_err : 1; /* [0] */ + u32 deqc_ecc_2bit_err_insrt : 1; /* [1] */ + u32 deqc_ecc_2bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_2bit_err_u; + +/* Define the union csr_deqc_enmq_bind_config_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_enmq_bind_cfg_err : 1; /* [0] */ + u32 deqc_enmq_bind_cfg_err_insrt : 1; /* [1] */ + u32 deqc_enmq_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_enmq_bind_config_err_u; + +/* Define the union csr_deqc_enfmq_bind_config_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_enfmq_bind_cfg_err : 1; /* [0] */ + u32 deqc_enfmq_bind_cfg_err_insrt : 1; /* [1] */ + u32 deqc_enfmq_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_enfmq_bind_config_err_u; + +/* Define the union csr_deqc_mem_err_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_err_req_0 : 1; /* [0] */ + u32 deqc_mem_err_req_1 : 1; /* [1] */ + u32 deqc_mem_err_req_2 : 1; /* [2] */ + u32 deqc_mem_err_req_3 : 1; /* [3] */ + u32 deqc_mem_err_req_4 : 1; /* [4] */ + u32 deqc_mem_err_req_5 : 1; /* [5] */ + u32 deqc_mem_err_req_6 : 1; /* [6] */ + u32 deqc_mem_err_req_7 : 1; /* [7] */ + u32 deqc_mem_err_req_8 : 1; /* [8] */ + u32 deqc_mem_err_req_9 : 1; /* [9] */ + u32 deqc_mem_err_req_10 : 1; /* [10] */ + u32 deqc_mem_err_req_11 : 1; /* [11] */ + u32 deqc_mem_err_req_12 : 1; /* [12] */ + u32 deqc_mem_err_req_13 : 1; /* [13] */ + u32 deqc_mem_err_req_14 : 1; /* [14] */ + u32 deqc_mem_err_req_15 : 1; /* [15] */ + u32 deqc_mem_err_req_16 : 1; /* [16] */ + u32 deqc_mem_err_req_17 : 1; /* [17] */ + u32 deqc_mem_err_req_18 : 1; /* [18] */ + u32 deqc_mem_err_req_19 : 1; /* [19] */ + u32 deqc_mem_err_req_20 : 1; /* [20] */ + u32 deqc_mem_err_req_21 : 1; /* [21] */ + u32 deqc_mem_err_req_22 : 1; /* [22] */ + u32 deqc_mem_err_req_23 : 1; /* [23] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_err_req_u; + +/* Define the union csr_deqc_fifo_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_fifo_int0_err0 : 1; /* [0] */ + u32 deqc_fifo_int0_err0_insrt : 1; /* [1] */ + u32 deqc_fifo_int0_err1 : 1; /* [2] */ + u32 deqc_fifo_int0_err1_insrt : 1; /* [3] */ + u32 deqc_fifo_int0_err2 : 1; /* [4] */ + u32 deqc_fifo_int0_err2_insrt : 1; /* [5] */ + u32 deqc_fifo_int0_err3 : 1; /* [6] */ + u32 deqc_fifo_int0_err3_insrt : 1; /* [7] */ + u32 deqc_fifo_int0_err4 : 1; /* [8] */ + u32 deqc_fifo_int0_err4_insrt : 1; /* [9] */ + u32 deqc_fifo_int0_err5 : 1; /* [10] */ + u32 deqc_fifo_int0_err5_insrt : 1; /* [11] */ + u32 deqc_fifo_int0_err6 : 1; /* [12] */ + u32 deqc_fifo_int0_err6_insrt : 1; /* [13] */ + u32 deqc_fifo_int0_err7 : 1; /* [14] */ + u32 deqc_fifo_int0_err7_insrt : 1; /* [15] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_fifo_int_u; + +/* Define the union csr_deqc_fifo_wr_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_fifo_int0_err0_en : 1; /* [0] */ + u32 deqc_fifo_int0_err1_en : 1; /* [1] */ + u32 deqc_fifo_int0_err2_en : 1; /* [2] */ + u32 deqc_fifo_int0_err3_en : 1; /* [3] */ + u32 deqc_fifo_int0_err4_en : 1; /* [4] */ + u32 deqc_fifo_int0_err5_en : 1; /* [5] */ + u32 deqc_fifo_int0_err6_en : 1; /* [6] */ + u32 deqc_fifo_int0_err7_en : 1; /* [7] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_fifo_wr_int_mask_u; + +/* Define the union csr_deqc_times_count_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deq_times_count : 4; /* [3:0] */ + u32 rsv_9 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_times_count_cfg_u; + +/* Define the union csr_deqc_blk_data_len0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 blk_data_len_0 : 8; /* [7:0] */ + u32 blk_data_len_1 : 8; /* [15:8] */ + u32 blk_data_len_2 : 8; /* [23:16] */ + u32 blk_data_len_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_blk_data_len0_u; + +/* Define the union csr_deqc_blk_data_len1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 blk_data_len_4 : 8; /* [7:0] */ + u32 blk_data_len_5 : 8; /* [15:8] */ + u32 blk_data_len_6 : 8; /* [23:16] */ + u32 blk_data_len_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_blk_data_len1_u; + +/* Define the union csr_deqc_root_crr_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_crr_weight_cfg_ns : 3; /* [2:0] */ + u32 rsv_10 : 5; /* [7:3] */ + u32 deqc_crr_weight_cfg_cs : 3; /* [10:8] */ + u32 rsv_11 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_root_crr_weight_cfg_u; + +/* Define the union csr_deqc_weight_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 weight_offset : 2; /* [1:0] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_weight_offset_u; + +/* Define the union csr_deqc_nmq_ep_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_ep_weight : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_ep_weight_u; + +/* Define the union csr_deqc_nfmq_ep_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_ep_weight : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_ep_weight_u; + +/* Define the union csr_deqc_nmq_host_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_weight : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_weight_u; + +/* Define the union csr_deqc_nfmq_host_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_weight : 8; /* [7:0] */ + u32 rsv_16 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_weight_u; + +/* Define the union csr_deqc_nmq_host_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_shap_cfg : 25; /* [24:0] */ + u32 rsv_17 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_shap_cfg_u; + +/* Define the union csr_deqc_nfmq_host_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_shap_cfg : 25; /* [24:0] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_shap_cfg_u; + +/* Define the union csr_deqc_serv_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 service_shap_cfg : 25; /* [24:0] */ + u32 rsv_19 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_serv_shap_cfg_u; + +/* Define the union csr_deqc_root_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_shap_cfg : 25; /* [24:0] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_root_shap_cfg_u; + +/* Define the union csr_deqc_shap_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ns_host_shap_byp_vld : 1; /* [0] */ + u32 rsv_21 : 3; /* [3:1] */ + u32 deqc_cs_host_shap_byp_vld : 1; /* [4] */ + u32 rsv_22 : 3; /* [7:5] */ + u32 deqc_serv_shap_byp_vld : 1; /* [8] */ + u32 rsv_23 : 3; /* [11:9] */ + u32 deqc_rt_shap_byp_vld : 1; /* [12] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_shap_bypass_cfg_u; + +/* Define the union csr_deqc_spcos_share_rsc_xon_rsp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_spcos_rsc_xon_resp_en : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_spcos_share_rsc_xon_rsp_cfg_u; + +/* Define the union csr_deqc_rh_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_root_xon_cfg : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 deqc_service_xon_cfg_nmq : 1; /* [8] */ + u32 deqc_service_xon_cfg_nfmq : 1; /* [9] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rh_xon_cfg_u; + +/* Define the union csr_deqc_host_xon_cfg_nmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_host_xon_cfg_nmq : 4; /* [3:0] */ + u32 rsv_28 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_host_xon_cfg_nmq_u; + +/* Define the union csr_deqc_host_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_host_xon_cfg_nfmq : 4; /* [3:0] */ + u32 rsv_29 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_host_xon_cfg_nfmq_u; + +/* Define the union csr_deqc_ep_xon_cfg_nmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ep_xon_cfg_nmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ep_xon_cfg_nmq_u; + +/* Define the union csr_deqc_ep_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ep_xon_cfg_nfmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ep_xon_cfg_nfmq_u; + +/* Define the union csr_deqc_cos_xon_cfg_nmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_cos_xon_cfg_nmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_cos_xon_cfg_nmq_u; + +/* Define the union csr_deqc_cos_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_cos_xon_cfg_nfmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_cos_xon_cfg_nfmq_u; + +/* Define the union csr_deqc_root_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_xon_st : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_root_xon_st_u; + +/* Define the union csr_deqc_nmq_service_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_serve_xon_st : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_service_xon_st_u; + +/* Define the union csr_deqc_nfmq_service_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_serve_xon_st : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_service_xon_st_u; + +/* Define the union csr_deqc_nmq_host_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_xon_st : 4; /* [3:0] */ + u32 rsv_33 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_xon_st_u; + +/* Define the union csr_deqc_nfmq_host_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_xon_st : 4; /* [3:0] */ + u32 rsv_34 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_xon_st_u; + +/* Define the union csr_deqc_nmq_host_ep_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_ep_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_ep_xon_st_u; + +/* Define the union csr_deqc_nfmq_host_ep_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_ep_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_ep_xon_st_u; + +/* Define the union csr_deqc_nmq_host_spass_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_spass_st : 4; /* [3:0] */ + u32 rsv_35 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_spass_st_u; + +/* Define the union csr_deqc_nfmq_host_shap_pass_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_spass_st : 4; /* [3:0] */ + u32 rsv_36 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_shap_pass_st_u; + +/* Define the union csr_deqc_fifo_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_cs_shap_sch_fifo_dfx : 2; /* [1:0] */ + u32 host_ns_shap_sch_fifo_dfx : 2; /* [3:2] */ + u32 serv_shap_sch_fifo_dfx : 2; /* [5:4] */ + u32 root_shap_sch_fifo_dfx : 2; /* [7:6] */ + u32 rsv_37 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_fifo_dfx_u; + +/* Define the union csr_deqc_nmq_up_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_up_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_up_pkt_cnt_u; + +/* Define the union csr_deqc_nfmq_up_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_up_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_up_pkt_cnt_u; + +/* Define the union csr_deqc_nmq_deq_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_deq_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_deq_pkt_cnt_u; + +/* Define the union csr_deqc_nfmq_deq_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_deq_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_deq_pkt_cnt_u; + +/* Define the union csr_deqc_nmq_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_deq_cmd_cnt_u; + +/* Define the union csr_deqc_nfmq_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_deq_cmd_cnt_u; + +/* Define the union csr_deqc_nfmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_empt_sch_cnt_u; + +/* Define the union csr_deqc_nmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_empt_sch_cnt_u; + +/* Define the union csr_deqc_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ecc_1bit_err_cnt_u; + +/* Define the union csr_deqc_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ecc_2bit_err_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_cfg : 13; /* [12:0] */ + u32 rsv_38 : 3; /* [15:13] */ + u32 deqc_sch_mq_qa_dfx_cfg : 1; /* [16] */ + u32 rsv_39 : 3; /* [19:17] */ + u32 deqc_sch_mq_dfx_cfg_vld : 1; /* [20] */ + u32 rsv_40 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_cfg_u; + +/* Define the union csr_deqc_sch_mq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_up_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_deq_cmd_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_deq_num_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_deq_num_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_deq_num_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_empt_sch_cnt_u; + +/* Define the union csr_deqc_nmq_host_ep_cos_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_ep_cos_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_ep_cos_xon_st_u; + +/* Define the union csr_deqc_nfmq_host_ep_cos_xon_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_ep_cos_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_ep_cos_xon_st0_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_deqc_rw_rsv0_u deqc_rw_rsv0; /* 0 */ + volatile csr_deqc_rw_rsv1_u deqc_rw_rsv1; /* 4 */ + volatile csr_deqc_rw_rsv2_u deqc_rw_rsv2; /* 8 */ + volatile csr_deqc_rw_rsv3_u deqc_rw_rsv3; /* C */ + volatile csr_deqc_indrect_ctrl_u deqc_indrect_ctrl; /* 10 */ + volatile csr_deqc_indrect_timeout_u deqc_indrect_timeout; /* 14 */ + volatile csr_deqc_indrect_data_u deqc_indrect_data; /* 18 */ + volatile csr_deqc_mem_ecc_bypass_en_u deqc_mem_ecc_bypass_en; /* 20 */ + volatile csr_deqc_mem_ctrl_bus_cfg0_u deqc_mem_ctrl_bus_cfg0; /* 24 */ + volatile csr_deqc_mem_ctrl_bus_cfg1_u deqc_mem_ctrl_bus_cfg1; /* 28 */ + volatile csr_deqc_mem_ctrl_bus_cfg2_u deqc_mem_ctrl_bus_cfg2; /* 2C */ + volatile csr_deqc_mem_ctrl_bus_cfg3_u deqc_mem_ctrl_bus_cfg3; /* 30 */ + volatile csr_deqc_mem_ctrl_bus_cfg4_u deqc_mem_ctrl_bus_cfg4; /* 34 */ + volatile csr_deqc_int_vector_u deqc_int_vector; /* 100 */ + volatile csr_deqc_int_u deqc_int; /* 104 */ + volatile csr_deqc_int_en_u deqc_int_en; /* 108 */ + volatile csr_deqc_mem_1bit_err_u deqc_mem_1bit_err; /* 10C */ + volatile csr_deqc_mem_2bit_err_u deqc_mem_2bit_err; /* 110 */ + volatile csr_deqc_enmq_bind_config_err_u deqc_enmq_bind_config_err; /* 114 */ + volatile csr_deqc_enfmq_bind_config_err_u deqc_enfmq_bind_config_err; /* 118 */ + volatile csr_deqc_mem_err_req_u deqc_mem_err_req; /* 150 */ + volatile csr_deqc_fifo_int_u deqc_fifo_int; /* 154 */ + volatile csr_deqc_fifo_wr_int_mask_u deqc_fifo_wr_int_mask; /* 158 */ + volatile csr_deqc_times_count_cfg_u deqc_times_count_cfg; /* 200 */ + volatile csr_deqc_blk_data_len0_u deqc_blk_data_len0; /* 204 */ + volatile csr_deqc_blk_data_len1_u deqc_blk_data_len1; /* 208 */ + volatile csr_deqc_root_crr_weight_cfg_u deqc_root_crr_weight_cfg; /* 20C */ + volatile csr_deqc_weight_offset_u deqc_weight_offset; /* 210 */ + volatile csr_deqc_nmq_ep_weight_u deqc_nmq_ep_weight[32]; /* 300 */ + volatile csr_deqc_nfmq_ep_weight_u deqc_nfmq_ep_weight[32]; /* 380 */ + volatile csr_deqc_nmq_host_weight_u deqc_nmq_host_weight[4]; /* 400 */ + volatile csr_deqc_nfmq_host_weight_u deqc_nfmq_host_weight[4]; /* 410 */ + volatile csr_deqc_nmq_host_shap_cfg_u deqc_nmq_host_shap_cfg[4]; /* 420 */ + volatile csr_deqc_nfmq_host_shap_cfg_u deqc_nfmq_host_shap_cfg[4]; /* 430 */ + volatile csr_deqc_serv_shap_cfg_u deqc_serv_shap_cfg[2]; /* 440 */ + volatile csr_deqc_root_shap_cfg_u deqc_root_shap_cfg; /* 450 */ + volatile csr_deqc_shap_bypass_cfg_u deqc_shap_bypass_cfg; /* 500 */ + volatile csr_deqc_spcos_share_rsc_xon_rsp_cfg_u deqc_spcos_share_rsc_xon_rsp_cfg; /* 504 */ + volatile csr_deqc_rh_xon_cfg_u deqc_rh_xon_cfg; /* 508 */ + volatile csr_deqc_host_xon_cfg_nmq_u deqc_host_xon_cfg_nmq; /* 50C */ + volatile csr_deqc_host_xon_cfg_nfmq_u deqc_host_xon_cfg_nfmq; /* 510 */ + volatile csr_deqc_ep_xon_cfg_nmq_u deqc_ep_xon_cfg_nmq; /* 514 */ + volatile csr_deqc_ep_xon_cfg_nfmq_u deqc_ep_xon_cfg_nfmq; /* 518 */ + volatile csr_deqc_cos_xon_cfg_nmq_u deqc_cos_xon_cfg_nmq[8]; /* 520 */ + volatile csr_deqc_cos_xon_cfg_nfmq_u deqc_cos_xon_cfg_nfmq[8]; /* 540 */ + volatile csr_deqc_root_xon_st_u deqc_root_xon_st; /* 560 */ + volatile csr_deqc_nmq_service_xon_st_u deqc_nmq_service_xon_st; /* 564 */ + volatile csr_deqc_nfmq_service_xon_st_u deqc_nfmq_service_xon_st; /* 568 */ + volatile csr_deqc_nmq_host_xon_st_u deqc_nmq_host_xon_st; /* 56C */ + volatile csr_deqc_nfmq_host_xon_st_u deqc_nfmq_host_xon_st; /* 570 */ + volatile csr_deqc_nmq_host_ep_xon_st_u deqc_nmq_host_ep_xon_st; /* 574 */ + volatile csr_deqc_nfmq_host_ep_xon_st_u deqc_nfmq_host_ep_xon_st; /* 578 */ + volatile csr_deqc_nmq_host_spass_st_u deqc_nmq_host_spass_st; /* 57C */ + volatile csr_deqc_nfmq_host_shap_pass_st_u deqc_nfmq_host_shap_pass_st; /* 580 */ + volatile csr_deqc_fifo_dfx_u deqc_fifo_dfx; /* 584 */ + volatile csr_deqc_nmq_up_pkt_cnt_u deqc_nmq_up_pkt_cnt; /* 5C0 */ + volatile csr_deqc_nfmq_up_pkt_cnt_u deqc_nfmq_up_pkt_cnt; /* 5C4 */ + volatile csr_deqc_nmq_deq_pkt_cnt_u deqc_nmq_deq_pkt_cnt; /* 5C8 */ + volatile csr_deqc_nfmq_deq_pkt_cnt_u deqc_nfmq_deq_pkt_cnt; /* 5CC */ + volatile csr_deqc_nmq_deq_cmd_cnt_u deqc_nmq_deq_cmd_cnt; /* 5D0 */ + volatile csr_deqc_nfmq_deq_cmd_cnt_u deqc_nfmq_deq_cmd_cnt; /* 5D4 */ + volatile csr_deqc_nfmq_empt_sch_cnt_u deqc_nfmq_empt_sch_cnt; /* 5D8 */ + volatile csr_deqc_nmq_empt_sch_cnt_u deqc_nmq_empt_sch_cnt; /* 5DC */ + volatile csr_deqc_ecc_1bit_err_cnt_u deqc_ecc_1bit_err_cnt; /* 5E0 */ + volatile csr_deqc_ecc_2bit_err_cnt_u deqc_ecc_2bit_err_cnt; /* 5E4 */ + volatile csr_deqc_sch_mq_dfx_cfg_u deqc_sch_mq_dfx_cfg; /* 5E8 */ + volatile csr_deqc_sch_mq_dfx_up_cnt_u deqc_sch_mq_dfx_up_cnt; /* 5EC */ + volatile csr_deqc_sch_mq_dfx_deq_cmd_cnt_u deqc_sch_mq_dfx_deq_cmd_cnt; /* 5F0 */ + volatile csr_deqc_sch_mq_dfx_deq_num_cnt_u deqc_sch_mq_dfx_deq_num_cnt; /* 5F4 */ + volatile csr_deqc_sch_mq_dfx_empt_sch_cnt_u deqc_sch_mq_dfx_empt_sch_cnt; /* 5F8 */ + volatile csr_deqc_nmq_host_ep_cos_xon_st_u deqc_nmq_host_ep_cos_xon_st[8]; /* 600 */ + volatile csr_deqc_nfmq_host_ep_cos_xon_st0_u deqc_nfmq_host_ep_cos_xon_st0[8]; /* 620 */ +} S_mqm_deqc_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_deqc */ +extern volatile S_mqm_deqc_REGS_TYPE *gopmqm_deqcAllReg; + +/* Declare the functions that set the member value */ +int iSetDEQC_RW_RSV0_deqc_rw_rsv0(unsigned int udeqc_rw_rsv0); +int iSetDEQC_RW_RSV1_deqc_rw_rsv1(unsigned int udeqc_rw_rsv1); +int iSetDEQC_RW_RSV2_deqc_rw_rsv2(unsigned int udeqc_rw_rsv2); +int iSetDEQC_RW_RSV3_deqc_rw_rsv3(unsigned int udeqc_rw_rsv3); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_addr(unsigned int udeqc_indrect_addr); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_tab(unsigned int udeqc_indrect_tab); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_stat(unsigned int udeqc_indrect_stat); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_mode(unsigned int udeqc_indrect_mode); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_vld(unsigned int udeqc_indrect_vld); +int iSetDEQC_INDRECT_TIMEOUT_deqc_indrect_timeout(unsigned int udeqc_indrect_timeout); +int iSetDEQC_INDRECT_DATA_deqc_indrect_data(unsigned int udeqc_indrect_data); +int iSetDEQC_MEM_ECC_BYPASS_EN_deqc_mem_ecc_bypass(unsigned int udeqc_mem_ecc_bypass); +int iSetDEQC_MEM_CTRL_BUS_CFG0_deqc_mem_ctrl_bus_0(unsigned int udeqc_mem_ctrl_bus_0); +int iSetDEQC_MEM_CTRL_BUS_CFG1_deqc_mem_ctrl_bus_1(unsigned int udeqc_mem_ctrl_bus_1); +int iSetDEQC_MEM_CTRL_BUS_CFG2_deqc_mem_ctrl_bus_2(unsigned int udeqc_mem_ctrl_bus_2); +int iSetDEQC_MEM_CTRL_BUS_CFG3_deqc_mem_ctrl_bus_3(unsigned int udeqc_mem_ctrl_bus_3); +int iSetDEQC_MEM_CTRL_BUS_CFG4_deqc_mem_ctrl_bus_4(unsigned int udeqc_mem_ctrl_bus_4); +int iSetDEQC_INT_VECTOR_deqc_cpi_int_index(unsigned int udeqc_cpi_int_index); +int iSetDEQC_INT_VECTOR_deqc_enable(unsigned int udeqc_enable); +int iSetDEQC_INT_VECTOR_deqc_int_issue(unsigned int udeqc_int_issue); +int iSetDEQC_INT_deqc_int_data(unsigned int udeqc_int_data); +int iSetDEQC_INT_deqc_program_csr_id_ro(unsigned int udeqc_program_csr_id_ro); +int iSetDEQC_INT_EN_deqc_int_en(unsigned int udeqc_int_en); +int iSetDEQC_INT_EN_deqc_program_csr_id(unsigned int udeqc_program_csr_id); +int iSetDEQC_MEM_1BIT_ERR_deqc_ecc_1bit_err(unsigned int udeqc_ecc_1bit_err); +int iSetDEQC_MEM_1BIT_ERR_deqc_ecc_1bit_err_insrt(unsigned int udeqc_ecc_1bit_err_insrt); +int iSetDEQC_MEM_1BIT_ERR_deqc_ecc_1bit_err_info(unsigned int udeqc_ecc_1bit_err_info); +int iSetDEQC_MEM_2BIT_ERR_deqc_ecc_2bit_err(unsigned int udeqc_ecc_2bit_err); +int iSetDEQC_MEM_2BIT_ERR_deqc_ecc_2bit_err_insrt(unsigned int udeqc_ecc_2bit_err_insrt); +int iSetDEQC_MEM_2BIT_ERR_deqc_ecc_2bit_err_info(unsigned int udeqc_ecc_2bit_err_info); +int iSetDEQC_ENMQ_BIND_CONFIG_ERR_deqc_enmq_bind_cfg_err(unsigned int udeqc_enmq_bind_cfg_err); +int iSetDEQC_ENMQ_BIND_CONFIG_ERR_deqc_enmq_bind_cfg_err_insrt(unsigned int udeqc_enmq_bind_cfg_err_insrt); +int iSetDEQC_ENMQ_BIND_CONFIG_ERR_deqc_enmq_bind_cfg_err_info(unsigned int udeqc_enmq_bind_cfg_err_info); +int iSetDEQC_ENFMQ_BIND_CONFIG_ERR_deqc_enfmq_bind_cfg_err(unsigned int udeqc_enfmq_bind_cfg_err); +int iSetDEQC_ENFMQ_BIND_CONFIG_ERR_deqc_enfmq_bind_cfg_err_insrt(unsigned int udeqc_enfmq_bind_cfg_err_insrt); +int iSetDEQC_ENFMQ_BIND_CONFIG_ERR_deqc_enfmq_bind_cfg_err_info(unsigned int udeqc_enfmq_bind_cfg_err_info); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_0(unsigned int udeqc_mem_err_req_0); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_1(unsigned int udeqc_mem_err_req_1); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_2(unsigned int udeqc_mem_err_req_2); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_3(unsigned int udeqc_mem_err_req_3); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_4(unsigned int udeqc_mem_err_req_4); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_5(unsigned int udeqc_mem_err_req_5); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_6(unsigned int udeqc_mem_err_req_6); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_7(unsigned int udeqc_mem_err_req_7); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_8(unsigned int udeqc_mem_err_req_8); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_9(unsigned int udeqc_mem_err_req_9); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_10(unsigned int udeqc_mem_err_req_10); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_11(unsigned int udeqc_mem_err_req_11); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_12(unsigned int udeqc_mem_err_req_12); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_13(unsigned int udeqc_mem_err_req_13); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_14(unsigned int udeqc_mem_err_req_14); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_15(unsigned int udeqc_mem_err_req_15); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_16(unsigned int udeqc_mem_err_req_16); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_17(unsigned int udeqc_mem_err_req_17); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_18(unsigned int udeqc_mem_err_req_18); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_19(unsigned int udeqc_mem_err_req_19); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_20(unsigned int udeqc_mem_err_req_20); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_21(unsigned int udeqc_mem_err_req_21); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_22(unsigned int udeqc_mem_err_req_22); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_23(unsigned int udeqc_mem_err_req_23); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err0(unsigned int udeqc_fifo_int0_err0); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err0_insrt(unsigned int udeqc_fifo_int0_err0_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err1(unsigned int udeqc_fifo_int0_err1); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err1_insrt(unsigned int udeqc_fifo_int0_err1_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err2(unsigned int udeqc_fifo_int0_err2); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err2_insrt(unsigned int udeqc_fifo_int0_err2_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err3(unsigned int udeqc_fifo_int0_err3); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err3_insrt(unsigned int udeqc_fifo_int0_err3_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err4(unsigned int udeqc_fifo_int0_err4); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err4_insrt(unsigned int udeqc_fifo_int0_err4_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err5(unsigned int udeqc_fifo_int0_err5); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err5_insrt(unsigned int udeqc_fifo_int0_err5_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err6(unsigned int udeqc_fifo_int0_err6); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err6_insrt(unsigned int udeqc_fifo_int0_err6_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err7(unsigned int udeqc_fifo_int0_err7); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err7_insrt(unsigned int udeqc_fifo_int0_err7_insrt); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err0_en(unsigned int udeqc_fifo_int0_err0_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err1_en(unsigned int udeqc_fifo_int0_err1_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err2_en(unsigned int udeqc_fifo_int0_err2_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err3_en(unsigned int udeqc_fifo_int0_err3_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err4_en(unsigned int udeqc_fifo_int0_err4_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err5_en(unsigned int udeqc_fifo_int0_err5_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err6_en(unsigned int udeqc_fifo_int0_err6_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err7_en(unsigned int udeqc_fifo_int0_err7_en); +int iSetDEQC_TIMES_COUNT_CFG_deq_times_count(unsigned int udeq_times_count); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_0(unsigned int ublk_data_len_0); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_1(unsigned int ublk_data_len_1); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_2(unsigned int ublk_data_len_2); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_3(unsigned int ublk_data_len_3); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_4(unsigned int ublk_data_len_4); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_5(unsigned int ublk_data_len_5); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_6(unsigned int ublk_data_len_6); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_7(unsigned int ublk_data_len_7); +int iSetDEQC_ROOT_CRR_WEIGHT_CFG_deqc_crr_weight_cfg_ns(unsigned int udeqc_crr_weight_cfg_ns); +int iSetDEQC_ROOT_CRR_WEIGHT_CFG_deqc_crr_weight_cfg_cs(unsigned int udeqc_crr_weight_cfg_cs); +int iSetDEQC_WEIGHT_OFFSET_weight_offset(unsigned int uweight_offset); +int iSetDEQC_NMQ_EP_WEIGHT_nmq_ep_weight(unsigned int unmq_ep_weight); +int iSetDEQC_NFMQ_EP_WEIGHT_nfmq_ep_weight(unsigned int unfmq_ep_weight); +int iSetDEQC_NMQ_HOST_WEIGHT_nmq_host_weight(unsigned int unmq_host_weight); +int iSetDEQC_NFMQ_HOST_WEIGHT_nfmq_host_weight(unsigned int unfmq_host_weight); +int iSetDEQC_NMQ_HOST_SHAP_CFG_nmq_host_shap_cfg(unsigned int unmq_host_shap_cfg); +int iSetDEQC_NFMQ_HOST_SHAP_CFG_nfmq_host_shap_cfg(unsigned int unfmq_host_shap_cfg); +int iSetDEQC_SERV_SHAP_CFG_service_shap_cfg(unsigned int uservice_shap_cfg); +int iSetDEQC_ROOT_SHAP_CFG_root_shap_cfg(unsigned int uroot_shap_cfg); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_ns_host_shap_byp_vld(unsigned int udeqc_ns_host_shap_byp_vld); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_cs_host_shap_byp_vld(unsigned int udeqc_cs_host_shap_byp_vld); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_serv_shap_byp_vld(unsigned int udeqc_serv_shap_byp_vld); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_rt_shap_byp_vld(unsigned int udeqc_rt_shap_byp_vld); +int iSetDEQC_SPCOS_SHARE_RSC_XON_RSP_CFG_deqc_spcos_rsc_xon_resp_en(unsigned int udeqc_spcos_rsc_xon_resp_en); +int iSetDEQC_RH_XON_CFG_deqc_root_xon_cfg(unsigned int udeqc_root_xon_cfg); +int iSetDEQC_RH_XON_CFG_deqc_service_xon_cfg_nmq(unsigned int udeqc_service_xon_cfg_nmq); +int iSetDEQC_RH_XON_CFG_deqc_service_xon_cfg_nfmq(unsigned int udeqc_service_xon_cfg_nfmq); +int iSetDEQC_HOST_XON_CFG_NMQ_deqc_host_xon_cfg_nmq(unsigned int udeqc_host_xon_cfg_nmq); +int iSetDEQC_HOST_XON_CFG_NFMQ_deqc_host_xon_cfg_nfmq(unsigned int udeqc_host_xon_cfg_nfmq); +int iSetDEQC_EP_XON_CFG_NMQ_deqc_ep_xon_cfg_nmq(unsigned int udeqc_ep_xon_cfg_nmq); +int iSetDEQC_EP_XON_CFG_NFMQ_deqc_ep_xon_cfg_nfmq(unsigned int udeqc_ep_xon_cfg_nfmq); +int iSetDEQC_COS_XON_CFG_NMQ_deqc_cos_xon_cfg_nmq(unsigned int udeqc_cos_xon_cfg_nmq); +int iSetDEQC_COS_XON_CFG_NFMQ_deqc_cos_xon_cfg_nfmq(unsigned int udeqc_cos_xon_cfg_nfmq); +int iSetDEQC_ROOT_XON_ST_root_xon_st(unsigned int uroot_xon_st); +int iSetDEQC_NMQ_SERVICE_XON_ST_nmq_serve_xon_st(unsigned int unmq_serve_xon_st); +int iSetDEQC_NFMQ_SERVICE_XON_ST_nfmq_serve_xon_st(unsigned int unfmq_serve_xon_st); +int iSetDEQC_NMQ_HOST_XON_ST_nmq_host_xon_st(unsigned int unmq_host_xon_st); +int iSetDEQC_NFMQ_HOST_XON_ST_nfmq_host_xon_st(unsigned int unfmq_host_xon_st); +int iSetDEQC_NMQ_HOST_EP_XON_ST_nmq_host_ep_xon_st(unsigned int unmq_host_ep_xon_st); +int iSetDEQC_NFMQ_HOST_EP_XON_ST_nfmq_host_ep_xon_st(unsigned int unfmq_host_ep_xon_st); +int iSetDEQC_NMQ_HOST_SPASS_ST_nmq_host_spass_st(unsigned int unmq_host_spass_st); +int iSetDEQC_NFMQ_HOST_SHAP_PASS_ST_nfmq_host_spass_st(unsigned int unfmq_host_spass_st); +int iSetDEQC_FIFO_DFX_host_cs_shap_sch_fifo_dfx(unsigned int uhost_cs_shap_sch_fifo_dfx); +int iSetDEQC_FIFO_DFX_host_ns_shap_sch_fifo_dfx(unsigned int uhost_ns_shap_sch_fifo_dfx); +int iSetDEQC_FIFO_DFX_serv_shap_sch_fifo_dfx(unsigned int userv_shap_sch_fifo_dfx); +int iSetDEQC_FIFO_DFX_root_shap_sch_fifo_dfx(unsigned int uroot_shap_sch_fifo_dfx); +int iSetDEQC_NMQ_UP_PKT_CNT_deqc_nmq_up_pkt_cnt(unsigned int udeqc_nmq_up_pkt_cnt); +int iSetDEQC_NFMQ_UP_PKT_CNT_deqc_nfmq_up_pkt_cnt(unsigned int udeqc_nfmq_up_pkt_cnt); +int iSetDEQC_NMQ_DEQ_PKT_CNT_deqc_nmq_deq_pkt_cnt(unsigned int udeqc_nmq_deq_pkt_cnt); +int iSetDEQC_NFMQ_DEQ_PKT_CNT_deqc_nfmq_deq_pkt_cnt(unsigned int udeqc_nfmq_deq_pkt_cnt); +int iSetDEQC_NMQ_DEQ_CMD_CNT_deqc_nmq_deq_cmd_cnt(unsigned int udeqc_nmq_deq_cmd_cnt); +int iSetDEQC_NFMQ_DEQ_CMD_CNT_deqc_nfmq_deq_cmd_cnt(unsigned int udeqc_nfmq_deq_cmd_cnt); +int iSetDEQC_NFMQ_EMPT_SCH_CNT_deqc_nfmq_empt_sch_cnt(unsigned int udeqc_nfmq_empt_sch_cnt); +int iSetDEQC_NMQ_EMPT_SCH_CNT_deqc_nmq_empt_sch_cnt(unsigned int udeqc_nmq_empt_sch_cnt); +int iSetDEQC_ECC_1BIT_ERR_CNT_deqc_ecc_1bit_err_cnt(unsigned int udeqc_ecc_1bit_err_cnt); +int iSetDEQC_ECC_2BIT_ERR_CNT_deqc_ecc_2bit_err_cnt(unsigned int udeqc_ecc_2bit_err_cnt); +int iSetDEQC_SCH_MQ_DFX_CFG_deqc_sch_mq_dfx_cfg(unsigned int udeqc_sch_mq_dfx_cfg); +int iSetDEQC_SCH_MQ_DFX_CFG_deqc_sch_mq_qa_dfx_cfg(unsigned int udeqc_sch_mq_qa_dfx_cfg); +int iSetDEQC_SCH_MQ_DFX_CFG_deqc_sch_mq_dfx_cfg_vld(unsigned int udeqc_sch_mq_dfx_cfg_vld); +int iSetDEQC_SCH_MQ_DFX_UP_CNT_deqc_sch_mq_dfx_up_cnt(unsigned int udeqc_sch_mq_dfx_up_cnt); +int iSetDEQC_SCH_MQ_DFX_DEQ_CMD_CNT_deqc_sch_mq_dfx_deq_cmd_cnt(unsigned int udeqc_sch_mq_dfx_deq_cmd_cnt); +int iSetDEQC_SCH_MQ_DFX_DEQ_NUM_CNT_deqc_sch_mq_dfx_deq_num_cnt(unsigned int udeqc_sch_mq_dfx_deq_num_cnt); +int iSetDEQC_SCH_MQ_DFX_EMPT_SCH_CNT_deqc_sch_mq_dfx_empt_sch_cnt(unsigned int udeqc_sch_mq_dfx_empt_sch_cnt); +int iSetDEQC_NMQ_HOST_EP_COS_XON_ST_nmq_host_ep_cos_xon_st(unsigned int unmq_host_ep_cos_xon_st); +int iSetDEQC_NFMQ_HOST_EP_COS_XON_ST0_nfmq_host_ep_cos_xon_st(unsigned int unfmq_host_ep_cos_xon_st); + + +#endif // MQM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_reg_offset.h new file mode 100644 index 000000000..04cb4aba9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_reg_offset.h @@ -0,0 +1,3696 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : mqm_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:55:25 Create file +// ****************************************************************************** + +#ifndef MQM_REG_OFFSET_H +#define MQM_REG_OFFSET_H + +/* MQM_TOP Base address of Module's Register */ +#define CSR_MQM_TOP_BASE (0x2000) + +/* **************************************************************************** */ +/* MQM_TOP Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_TOP_MQM_EDITION_REG (CSR_MQM_TOP_BASE + 0x0) /* Version Register */ +#define CSR_MQM_TOP_MQM_INITCTAB_START_REG (CSR_MQM_TOP_BASE + 0x4) /* 配置表初始化使能寄存器 */ +#define CSR_MQM_TOP_MQM_INITCTAB_DONE_REG (CSR_MQM_TOP_BASE + 0x8) /* 配置表初始化状态寄存器 */ +#define CSR_MQM_TOP_MQM_CFG_OK_REG (CSR_MQM_TOP_BASE + 0xC) /* MQM 配置完成寄存器 */ +#define CSR_MQM_TOP_MQM_INITLOGIC_DONE_REG (CSR_MQM_TOP_BASE + 0x10) /* 芯片逻辑初始化状态寄存器 */ +#define CSR_MQM_TOP_MQM_TOP_INT_VECTOR_REG (CSR_MQM_TOP_BASE + 0x30) /* MQM Interrupt Vector Register */ +#define CSR_MQM_TOP_MQM_TOP_INT_REG (CSR_MQM_TOP_BASE + 0x34) /* MQM Interrupt Register */ +#define CSR_MQM_TOP_MQM_TOP_INT_EN_REG (CSR_MQM_TOP_BASE + 0x38) /* MQM Interrupt Mask Register */ +#define CSR_MQM_TOP_VF_FLUSH_DONE_INT_REG (CSR_MQM_TOP_BASE + 0x3C) /* VF FLUSH finish done Interrupt register. */ +#define CSR_MQM_TOP_MQM_RX_CNP_E0_ERR_INT_REG (CSR_MQM_TOP_BASE + 0x40) /* Receive Ring CNP E0 error int */ +#define CSR_MQM_TOP_MQM_RX_CNP_E1_ERR_INT_REG (CSR_MQM_TOP_BASE + 0x44) /* Receive Ring CNP E1 error int */ +#define CSR_MQM_TOP_MQM_TOP_FIFO_INT_REG (CSR_MQM_TOP_BASE + 0x48) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_TOP_MQM_TOP_FIFO_INT_MASK_REG \ + (CSR_MQM_TOP_BASE + 0x4C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_TOP_USE_HOST_BITMAP_REG (CSR_MQM_TOP_BASE + 0x80) /* HOST使用指示寄存器 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB0_REG (CSR_MQM_TOP_BASE + 0x84) /* DB TYPE映射表0 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB1_REG (CSR_MQM_TOP_BASE + 0x88) /* DB TYPE映射表1 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB2_REG (CSR_MQM_TOP_BASE + 0x8C) /* DB TYPE映射表2 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB3_REG (CSR_MQM_TOP_BASE + 0x90) /* DB TYPE映射表3 */ +#define CSR_MQM_TOP_MQM_CMQ_ENQ_MODE_CFG_REG (CSR_MQM_TOP_BASE + 0x94) /* MQM CMQ ENQ MODE CFG */ +#define CSR_MQM_TOP_MQM_MAX_DMA_CRDT_CFG_REG (CSR_MQM_TOP_BASE + 0x98) /* Config value for dma credit */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_0_REG (CSR_MQM_TOP_BASE + 0x9C) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_1_REG (CSR_MQM_TOP_BASE + 0xA0) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_2_REG (CSR_MQM_TOP_BASE + 0xA4) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_3_REG (CSR_MQM_TOP_BASE + 0xA8) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_PF_CFG_REG (CSR_MQM_TOP_BASE + 0xAC) /* MQM PF CFG */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_CFG_REG (CSR_MQM_TOP_BASE + 0x100) /* VF FLUSH配置寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_0_REG (CSR_MQM_TOP_BASE + 0x104) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_1_REG (CSR_MQM_TOP_BASE + 0x108) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_2_REG (CSR_MQM_TOP_BASE + 0x10C) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_3_REG (CSR_MQM_TOP_BASE + 0x110) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_4_REG (CSR_MQM_TOP_BASE + 0x114) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_5_REG (CSR_MQM_TOP_BASE + 0x118) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_6_REG (CSR_MQM_TOP_BASE + 0x11C) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_7_REG (CSR_MQM_TOP_BASE + 0x120) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_0_REG (CSR_MQM_TOP_BASE + 0x124) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_1_REG (CSR_MQM_TOP_BASE + 0x128) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_2_REG (CSR_MQM_TOP_BASE + 0x12C) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_3_REG (CSR_MQM_TOP_BASE + 0x130) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_4_REG (CSR_MQM_TOP_BASE + 0x134) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_5_REG (CSR_MQM_TOP_BASE + 0x138) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_6_REG (CSR_MQM_TOP_BASE + 0x13C) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_7_REG (CSR_MQM_TOP_BASE + 0x140) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_VF_FLUSH_R_TXQ_NUM_REG \ + (CSR_MQM_TOP_BASE + 0x144) /* The number of Remote RDMA Read VF flush txqid */ +#define CSR_MQM_TOP_VF_FLUSH_R_TXQ_BADDR_REG \ + (CSR_MQM_TOP_BASE + 0x148) /* The base address of Remote RDMA Read VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_S_TXQ_NUM_REG (CSR_MQM_TOP_BASE + 0x14C) /* The number of Send Queue VF flush txqid */ +#define CSR_MQM_TOP_VF_FLUSH_S_TXQ_BADDR_REG (CSR_MQM_TOP_BASE + 0x150) /* The base address of Send Queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_F_TXQ_NUM_REG \ + (CSR_MQM_TOP_BASE + 0x154) /* The number of Filterable stateful RQ queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_F_TXQ_BADDR_REG \ + (CSR_MQM_TOP_BASE + 0x158) /* The base address of Filterable stateful RQ queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_U_TXQ_NUM_REG (CSR_MQM_TOP_BASE + 0x15C) /* The number of uCode CMQ VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_U_TXQ_BADDR_REG (CSR_MQM_TOP_BASE + 0x160) /* The base address of uCode CMQ VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_LNIC_SQ_TXQ_INFO_REG \ + (CSR_MQM_TOP_BASE + 0x164) /* The information of L2NIC SQ Queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_LNIC_RQ_TXQ_INFO_REG \ + (CSR_MQM_TOP_BASE + 0x168) /* The information of L2NIC RQ Queue VF flush */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_DONE_REG (CSR_MQM_TOP_BASE + 0x174) /* Record the status for flush when VF Flush */ +#define CSR_MQM_TOP_MQM_UNCRT_ERR_MASK_REG (CSR_MQM_TOP_BASE + 0x200) /* MQM Urgency Interrupt Mask Register。 */ +#define CSR_MQM_TOP_MQM_UNCRT_ERR_CLR_REG (CSR_MQM_TOP_BASE + 0x204) /* MQM Urgency Interrupt Clear Register。 */ +#define CSR_MQM_TOP_MQM_VF_COUNT_CFG_REG \ + (CSR_MQM_TOP_BASE + \ + 0x304) /* cfg vfid that mqm need statistics the number of doorbell which is belong to designated vfid */ +#define CSR_MQM_TOP_MQM_RX_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x308) /* Statics the number of doorbell which mqm received and belongs to the designate vfid \ + */ +#define CSR_MQM_TOP_MQM_FILT_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + \ + 0x30C) /* Statics the number of doorbell which filted by mqm and belongs to the designate vfid */ +#define CSR_MQM_TOP_MQM_TX_SM_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x310) /* Statics the number of doorbell which send to sm and belongs to the designate vfid */ +#define CSR_MQM_TOP_MQM_TX_QU_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x314) /* Statics the number of doorbell which send to qu and belongs to the designate vfid */ +#define CSR_MQM_TOP_MQM_RCV_TILE_API_OP_ERR_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x318) /* Statics the number of API from tile with opid err */ +#define CSR_MQM_TOP_MQM_RCV_TILE_FAST_CNP_API_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x31C) /* Statics the number of FAST CNP API from Tile */ +#define CSR_MQM_TOP_MQM_RCV_TILE_CNP_API_E0E1_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x320) /* Statics the number of FAST CNP E0E1 API from Tile */ +#define CSR_MQM_TOP_MQM_ND_RS_RQST_CREDIT_REG \ + (CSR_MQM_TOP_BASE + 0x324) /* MQM node interface with Ring credit request cnt */ +#define CSR_MQM_TOP_MQM_TOP_FIFO_ST_REG (CSR_MQM_TOP_BASE + 0x328) /* MQM TOP fifo full and empt state */ + +/* MQM_ENQC Base address of Module's Register */ +#define CSR_MQM_ENQC_BASE (0x4000) + +/* **************************************************************************** */ +/* MQM_ENQC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_ENQC_ENQC_RW_RSV0_REG (CSR_MQM_ENQC_BASE + 0x0) /* enqc rw reserved register 0 */ +#define CSR_MQM_ENQC_ENQC_RW_RSV1_REG (CSR_MQM_ENQC_BASE + 0x4) /* enqc rw reserved register 1 */ +#define CSR_MQM_ENQC_ENQC_RW_RSV2_REG (CSR_MQM_ENQC_BASE + 0x8) /* enqc rw reserved register 2 */ +#define CSR_MQM_ENQC_ENQC_RW_RSV3_REG (CSR_MQM_ENQC_BASE + 0xC) /* enqc rw reserved register 3 */ +#define CSR_MQM_ENQC_ENQC_INDRECT_CTRL_REG (CSR_MQM_ENQC_BASE + 0x10) /* ENQC Indirect access ctrl Register */ +#define CSR_MQM_ENQC_ENQC_INDRECT_TIMEOUT_REG (CSR_MQM_ENQC_BASE + 0x14) /* ENQC Indirect Access Timeout Register */ +#define CSR_MQM_ENQC_ENQC_INDRECT_DATA_0_REG (CSR_MQM_ENQC_BASE + 0x18) /* ENQC Indirect Access Data Register0 */ +#define CSR_MQM_ENQC_ENQC_INDRECT_DATA_1_REG (CSR_MQM_ENQC_BASE + 0x1C) /* ENQC Indirect Access Data Register1 */ +#define CSR_MQM_ENQC_ENQC_INT_VECTOR_REG (CSR_MQM_ENQC_BASE + 0x20) /* enqc int vector */ +#define CSR_MQM_ENQC_ENQC_INT_REG (CSR_MQM_ENQC_BASE + 0x24) /* enqc int */ +#define CSR_MQM_ENQC_ENQC_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x28) /* enqc int mask */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_ERR0_REG (CSR_MQM_ENQC_BASE + 0x2C) /* RAM ECC ONE BIT ERR */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_ERR1_REG (CSR_MQM_ENQC_BASE + 0x30) /* RAM ECC TWO BIT ERR */ +#define CSR_MQM_ENQC_TABLE_RD_INVLD_INT_REG (CSR_MQM_ENQC_BASE + 0x34) /* table read invalid */ +#define CSR_MQM_ENQC_VFPF_TO_HOST_ID_INT_REG (CSR_MQM_ENQC_BASE + 0x38) /* VF or PF map to HOST ID err */ +#define CSR_MQM_ENQC_QU_ENQC_DB_IF_INT_REG (CSR_MQM_ENQC_BASE + 0x3C) /* QU to ENQC db interface err */ +#define CSR_MQM_ENQC_CPI_DISCARD_INT_REG (CSR_MQM_ENQC_BASE + 0x40) /* this int indicate cpi discard doorbell */ +#define CSR_MQM_ENQC_ENQC_FIFO_INT_REG (CSR_MQM_ENQC_BASE + 0x44) /* enqc fifo write overflow and read underflow */ +#define CSR_MQM_ENQC_ENQC_FIFO_INT_EN_REG \ + (CSR_MQM_ENQC_BASE + 0x48) /* enqc fifo write overflow mask and read overflow */ +#define CSR_MQM_ENQC_ENQC_QF_INT_REG (CSR_MQM_ENQC_BASE + 0x4C) /* enqc queue filter error int */ +#define CSR_MQM_ENQC_RX_RING_E0_ERR_INT_REG (CSR_MQM_ENQC_BASE + 0x50) /* Receive Ring E0 error int */ +#define CSR_MQM_ENQC_RX_RING_E1_ERR_INT_REG (CSR_MQM_ENQC_BASE + 0x54) /* Receive Ring E1 error int */ +#define CSR_MQM_ENQC_ENQC_TXQID_OVFL_VF_RANGE_INT_REG \ + (CSR_MQM_ENQC_BASE + 0x58) /* The int that filter doorbell's txqid overflow the range of VF */ +#define CSR_MQM_ENQC_ENQC_NONF_NUM_OVFL_THR_INT_REG \ + (CSR_MQM_ENQC_BASE + 0x5C) /* The int that The number of non-filter doorbell overflow the threshold */ +#define CSR_MQM_ENQC_ENQC_ERR_TYP_DB_INT_REG (CSR_MQM_ENQC_BASE + 0x60) /* The int that error type doorbell for mqm */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_REQ0_REG (CSR_MQM_ENQC_BASE + 0x80) /* ENQC memory ecc insert request Register0 */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_REQ1_REG (CSR_MQM_ENQC_BASE + 0x84) /* ENQC memory ecc insert request Register1 */ +#define CSR_MQM_ENQC_ENQC_QU_DB_IF_UNCRT_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x88) /* qu to enqc uncorrect int enable */ +#define CSR_MQM_ENQC_ENQC_UNCRT_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x8C) /* enqc uncorrect int enable */ +#define CSR_MQM_ENQC_ENQC_SENDQ_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xB0) /* SQ TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_SENDQ_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xB4) /* SQ TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_TASKIO_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xB8) /* TASKIO TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_TASKIO_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xBC) /* TASKIO TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_RDMA_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xC0) /* RDMA TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_RDMA_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xC4) /* RDMA TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_FTXQID_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xC8) /* RQ TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_FTXQID_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xCC) /* RQ TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_UTXQID_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xD0) /* uCode TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_UTXQID_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xD4) /* uCode TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_0_REG \ + (CSR_MQM_ENQC_BASE + 0xD8) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_1_REG \ + (CSR_MQM_ENQC_BASE + 0xDC) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_2_REG \ + (CSR_MQM_ENQC_BASE + 0xE0) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_3_REG \ + (CSR_MQM_ENQC_BASE + 0xE4) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_4_REG \ + (CSR_MQM_ENQC_BASE + 0xE8) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_5_REG \ + (CSR_MQM_ENQC_BASE + 0xEC) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_6_REG \ + (CSR_MQM_ENQC_BASE + 0xF0) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_7_REG \ + (CSR_MQM_ENQC_BASE + 0xF4) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_0_REG \ + (CSR_MQM_ENQC_BASE + 0xF8) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_1_REG \ + (CSR_MQM_ENQC_BASE + 0xFC) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_2_REG \ + (CSR_MQM_ENQC_BASE + 0x100) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_3_REG \ + (CSR_MQM_ENQC_BASE + 0x104) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_4_REG \ + (CSR_MQM_ENQC_BASE + 0x108) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_5_REG \ + (CSR_MQM_ENQC_BASE + 0x10C) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_6_REG \ + (CSR_MQM_ENQC_BASE + 0x110) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_7_REG \ + (CSR_MQM_ENQC_BASE + 0x114) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_SQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x118) /* Host L2NIC SQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_SQ_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x11C) /* Host L2NIC SQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_RQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x120) /* Host L2NIC RQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_RQ_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x124) /* Host L2NIC RQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_SQ_CNT_BADDR_REG (CSR_MQM_ENQC_BASE + 0x128) /* SQ PI store base address in pi store space \ + */ +#define CSR_MQM_ENQC_ENQC_SQ_CNT_LIMIT_REG (CSR_MQM_ENQC_BASE + 0x12C) /* SQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_CMQ_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x130) /* Host L2NIC CMQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x134) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x138) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x13C) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x140) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_4_REG (CSR_MQM_ENQC_BASE + 0x144) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x148) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x14C) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x150) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x154) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x158) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x15C) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x160) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x164) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_ENQC_CFG_REG (CSR_MQM_ENQC_BASE + 0x168) /* ENQC module configuration */ +#define CSR_MQM_ENQC_SOC_STATEFUL_DB_MAP_HID_REG (CSR_MQM_ENQC_BASE + 0x16C) /* soc stateful db map host id */ +#define CSR_MQM_ENQC_ENQC_IN_FIFO_GAP_REG (CSR_MQM_ENQC_BASE + 0x170) /* MQM input interface backpress threshold cfg \ + */ +#define CSR_MQM_ENQC_ENQC_EQM_PT_FIFO_GAP_REG \ + (CSR_MQM_ENQC_BASE + 0x174) /* MQM passthrough fifo and eqm enq fifo backpress threshold cfg */ +#define CSR_MQM_ENQC_ENQC_MRF_FIFO_BP_TH_REG \ + (CSR_MQM_ENQC_BASE + 0x178) /* MRF FIFO backpress threshold configuration */ +#define CSR_MQM_ENQC_ENQC_DURF_FIFO_BP_TH_REG \ + (CSR_MQM_ENQC_BASE + 0x17C) /* DURF FIFO backpress threshold configuration */ +#define CSR_MQM_ENQC_ENQC_WRR_WEIGHT0_REG (CSR_MQM_ENQC_BASE + 0x180) /* WRR weight configuration for SM/Tile/CPI */ +#define CSR_MQM_ENQC_ENQC_WRR_WEIGHT1_REG (CSR_MQM_ENQC_BASE + 0x184) /* WRR weight configuration */ +#define CSR_MQM_ENQC_ENQC_RX_DU_LEN_CLR_REG (CSR_MQM_ENQC_BASE + 0x188) /* Clr ENQC rx du length cnt */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_ENQC_BASE + 0x18C) /* ENQC RAM ECC BYPASS ctrl en */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_ENQC_BASE + 0x190) /* ENQC RAM ctrl bus cfg reg0 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_ENQC_BASE + 0x194) /* ENQC RAM ctrl bus cfg reg1 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_ENQC_BASE + 0x198) /* ENQC RAM ctrl bus cfg reg2 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_ENQC_BASE + 0x19C) /* ENQC RAM ctrl bus cfg reg3 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_ENQC_BASE + 0x1A0) /* ENQC RAM ctrl bus cfg reg4 */ +#define CSR_MQM_ENQC_ENQC_HOST_CMQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1A4) /* HOST L2NIC CMQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_LNIC_SQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1A8) /* SOC L2NIC SQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_LNIC_RQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1AC) /* SOC L2NIC RQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_CMQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1B0) /* SOC L2NIC CMQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_DB_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x1B4) /* SOC L2NIC SQ/RQ/CMQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_PASS_THROUGH_CFG_REG (CSR_MQM_ENQC_BASE + 0x1B8) /* Pass through function enable register. */ +#define CSR_MQM_ENQC_ENQC_ROOT_HOST_XON_STA_REG (CSR_MQM_ENQC_BASE + 0x1C0) /* HOST and Root level backpress status */ +#define CSR_MQM_ENQC_ENQC_HOSTEP_INMQ_XON_STA_REG (CSR_MQM_ENQC_BASE + 0x1C4) /* INMQ HOST EP level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_HOSTEP_INFMQ_XON_STA_REG \ + (CSR_MQM_ENQC_BASE + 0x1C8) /* INFMQ HOST EP level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_0_REG \ + (CSR_MQM_ENQC_BASE + 0x1CC) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_1_REG \ + (CSR_MQM_ENQC_BASE + 0x1D0) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_2_REG \ + (CSR_MQM_ENQC_BASE + 0x1D4) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_3_REG \ + (CSR_MQM_ENQC_BASE + 0x1D8) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_4_REG \ + (CSR_MQM_ENQC_BASE + 0x1DC) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_5_REG \ + (CSR_MQM_ENQC_BASE + 0x1E0) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_6_REG \ + (CSR_MQM_ENQC_BASE + 0x1E4) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_7_REG \ + (CSR_MQM_ENQC_BASE + 0x1E8) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_0_REG \ + (CSR_MQM_ENQC_BASE + 0x1EC) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_1_REG \ + (CSR_MQM_ENQC_BASE + 0x1F0) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_2_REG \ + (CSR_MQM_ENQC_BASE + 0x1F4) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_3_REG \ + (CSR_MQM_ENQC_BASE + 0x1F8) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_4_REG \ + (CSR_MQM_ENQC_BASE + 0x1FC) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_5_REG \ + (CSR_MQM_ENQC_BASE + 0x200) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_6_REG \ + (CSR_MQM_ENQC_BASE + 0x204) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_7_REG \ + (CSR_MQM_ENQC_BASE + 0x208) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_0_REG (CSR_MQM_ENQC_BASE + 0x20C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_1_REG (CSR_MQM_ENQC_BASE + 0x210) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_2_REG (CSR_MQM_ENQC_BASE + 0x214) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_3_REG (CSR_MQM_ENQC_BASE + 0x218) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_4_REG (CSR_MQM_ENQC_BASE + 0x21C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_5_REG (CSR_MQM_ENQC_BASE + 0x220) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_6_REG (CSR_MQM_ENQC_BASE + 0x224) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_7_REG (CSR_MQM_ENQC_BASE + 0x228) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_8_REG (CSR_MQM_ENQC_BASE + 0x22C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_9_REG (CSR_MQM_ENQC_BASE + 0x230) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_10_REG (CSR_MQM_ENQC_BASE + 0x234) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_11_REG (CSR_MQM_ENQC_BASE + 0x238) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_12_REG (CSR_MQM_ENQC_BASE + 0x23C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_13_REG (CSR_MQM_ENQC_BASE + 0x240) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_14_REG (CSR_MQM_ENQC_BASE + 0x244) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_15_REG (CSR_MQM_ENQC_BASE + 0x248) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_16_REG (CSR_MQM_ENQC_BASE + 0x24C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_17_REG (CSR_MQM_ENQC_BASE + 0x250) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_18_REG (CSR_MQM_ENQC_BASE + 0x254) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_19_REG (CSR_MQM_ENQC_BASE + 0x258) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_20_REG (CSR_MQM_ENQC_BASE + 0x25C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_21_REG (CSR_MQM_ENQC_BASE + 0x260) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_22_REG (CSR_MQM_ENQC_BASE + 0x264) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_23_REG (CSR_MQM_ENQC_BASE + 0x268) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_24_REG (CSR_MQM_ENQC_BASE + 0x26C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_25_REG (CSR_MQM_ENQC_BASE + 0x270) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_26_REG (CSR_MQM_ENQC_BASE + 0x274) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_27_REG (CSR_MQM_ENQC_BASE + 0x278) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_28_REG (CSR_MQM_ENQC_BASE + 0x27C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_29_REG (CSR_MQM_ENQC_BASE + 0x280) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_30_REG (CSR_MQM_ENQC_BASE + 0x284) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_31_REG (CSR_MQM_ENQC_BASE + 0x288) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_32_REG (CSR_MQM_ENQC_BASE + 0x28C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_33_REG (CSR_MQM_ENQC_BASE + 0x290) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_34_REG (CSR_MQM_ENQC_BASE + 0x294) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_35_REG (CSR_MQM_ENQC_BASE + 0x298) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_36_REG (CSR_MQM_ENQC_BASE + 0x29C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_37_REG (CSR_MQM_ENQC_BASE + 0x2A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_38_REG (CSR_MQM_ENQC_BASE + 0x2A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_39_REG (CSR_MQM_ENQC_BASE + 0x2A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_40_REG (CSR_MQM_ENQC_BASE + 0x2AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_41_REG (CSR_MQM_ENQC_BASE + 0x2B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_42_REG (CSR_MQM_ENQC_BASE + 0x2B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_43_REG (CSR_MQM_ENQC_BASE + 0x2B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_44_REG (CSR_MQM_ENQC_BASE + 0x2BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_45_REG (CSR_MQM_ENQC_BASE + 0x2C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_46_REG (CSR_MQM_ENQC_BASE + 0x2C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_47_REG (CSR_MQM_ENQC_BASE + 0x2C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_48_REG (CSR_MQM_ENQC_BASE + 0x2CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_49_REG (CSR_MQM_ENQC_BASE + 0x2D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_50_REG (CSR_MQM_ENQC_BASE + 0x2D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_51_REG (CSR_MQM_ENQC_BASE + 0x2D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_52_REG (CSR_MQM_ENQC_BASE + 0x2DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_53_REG (CSR_MQM_ENQC_BASE + 0x2E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_54_REG (CSR_MQM_ENQC_BASE + 0x2E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_55_REG (CSR_MQM_ENQC_BASE + 0x2E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_56_REG (CSR_MQM_ENQC_BASE + 0x2EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_57_REG (CSR_MQM_ENQC_BASE + 0x2F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_58_REG (CSR_MQM_ENQC_BASE + 0x2F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_59_REG (CSR_MQM_ENQC_BASE + 0x2F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_60_REG (CSR_MQM_ENQC_BASE + 0x2FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_61_REG (CSR_MQM_ENQC_BASE + 0x300) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_62_REG (CSR_MQM_ENQC_BASE + 0x304) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_63_REG (CSR_MQM_ENQC_BASE + 0x308) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_64_REG (CSR_MQM_ENQC_BASE + 0x30C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_65_REG (CSR_MQM_ENQC_BASE + 0x310) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_66_REG (CSR_MQM_ENQC_BASE + 0x314) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_67_REG (CSR_MQM_ENQC_BASE + 0x318) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_68_REG (CSR_MQM_ENQC_BASE + 0x31C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_69_REG (CSR_MQM_ENQC_BASE + 0x320) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_70_REG (CSR_MQM_ENQC_BASE + 0x324) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_71_REG (CSR_MQM_ENQC_BASE + 0x328) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_72_REG (CSR_MQM_ENQC_BASE + 0x32C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_73_REG (CSR_MQM_ENQC_BASE + 0x330) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_74_REG (CSR_MQM_ENQC_BASE + 0x334) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_75_REG (CSR_MQM_ENQC_BASE + 0x338) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_76_REG (CSR_MQM_ENQC_BASE + 0x33C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_77_REG (CSR_MQM_ENQC_BASE + 0x340) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_78_REG (CSR_MQM_ENQC_BASE + 0x344) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_79_REG (CSR_MQM_ENQC_BASE + 0x348) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_80_REG (CSR_MQM_ENQC_BASE + 0x34C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_81_REG (CSR_MQM_ENQC_BASE + 0x350) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_82_REG (CSR_MQM_ENQC_BASE + 0x354) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_83_REG (CSR_MQM_ENQC_BASE + 0x358) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_84_REG (CSR_MQM_ENQC_BASE + 0x35C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_85_REG (CSR_MQM_ENQC_BASE + 0x360) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_86_REG (CSR_MQM_ENQC_BASE + 0x364) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_87_REG (CSR_MQM_ENQC_BASE + 0x368) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_88_REG (CSR_MQM_ENQC_BASE + 0x36C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_89_REG (CSR_MQM_ENQC_BASE + 0x370) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_90_REG (CSR_MQM_ENQC_BASE + 0x374) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_91_REG (CSR_MQM_ENQC_BASE + 0x378) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_92_REG (CSR_MQM_ENQC_BASE + 0x37C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_93_REG (CSR_MQM_ENQC_BASE + 0x380) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_94_REG (CSR_MQM_ENQC_BASE + 0x384) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_95_REG (CSR_MQM_ENQC_BASE + 0x388) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_96_REG (CSR_MQM_ENQC_BASE + 0x38C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_97_REG (CSR_MQM_ENQC_BASE + 0x390) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_98_REG (CSR_MQM_ENQC_BASE + 0x394) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_99_REG (CSR_MQM_ENQC_BASE + 0x398) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_100_REG (CSR_MQM_ENQC_BASE + 0x39C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_101_REG (CSR_MQM_ENQC_BASE + 0x3A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_102_REG (CSR_MQM_ENQC_BASE + 0x3A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_103_REG (CSR_MQM_ENQC_BASE + 0x3A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_104_REG (CSR_MQM_ENQC_BASE + 0x3AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_105_REG (CSR_MQM_ENQC_BASE + 0x3B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_106_REG (CSR_MQM_ENQC_BASE + 0x3B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_107_REG (CSR_MQM_ENQC_BASE + 0x3B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_108_REG (CSR_MQM_ENQC_BASE + 0x3BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_109_REG (CSR_MQM_ENQC_BASE + 0x3C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_110_REG (CSR_MQM_ENQC_BASE + 0x3C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_111_REG (CSR_MQM_ENQC_BASE + 0x3C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_112_REG (CSR_MQM_ENQC_BASE + 0x3CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_113_REG (CSR_MQM_ENQC_BASE + 0x3D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_114_REG (CSR_MQM_ENQC_BASE + 0x3D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_115_REG (CSR_MQM_ENQC_BASE + 0x3D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_116_REG (CSR_MQM_ENQC_BASE + 0x3DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_117_REG (CSR_MQM_ENQC_BASE + 0x3E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_118_REG (CSR_MQM_ENQC_BASE + 0x3E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_119_REG (CSR_MQM_ENQC_BASE + 0x3E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_120_REG (CSR_MQM_ENQC_BASE + 0x3EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_121_REG (CSR_MQM_ENQC_BASE + 0x3F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_122_REG (CSR_MQM_ENQC_BASE + 0x3F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_123_REG (CSR_MQM_ENQC_BASE + 0x3F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_124_REG (CSR_MQM_ENQC_BASE + 0x3FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_125_REG (CSR_MQM_ENQC_BASE + 0x400) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_126_REG (CSR_MQM_ENQC_BASE + 0x404) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_127_REG (CSR_MQM_ENQC_BASE + 0x408) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_128_REG (CSR_MQM_ENQC_BASE + 0x40C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_129_REG (CSR_MQM_ENQC_BASE + 0x410) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_130_REG (CSR_MQM_ENQC_BASE + 0x414) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_131_REG (CSR_MQM_ENQC_BASE + 0x418) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_132_REG (CSR_MQM_ENQC_BASE + 0x41C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_133_REG (CSR_MQM_ENQC_BASE + 0x420) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_134_REG (CSR_MQM_ENQC_BASE + 0x424) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_135_REG (CSR_MQM_ENQC_BASE + 0x428) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_136_REG (CSR_MQM_ENQC_BASE + 0x42C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_137_REG (CSR_MQM_ENQC_BASE + 0x430) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_138_REG (CSR_MQM_ENQC_BASE + 0x434) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_139_REG (CSR_MQM_ENQC_BASE + 0x438) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_140_REG (CSR_MQM_ENQC_BASE + 0x43C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_141_REG (CSR_MQM_ENQC_BASE + 0x440) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_142_REG (CSR_MQM_ENQC_BASE + 0x444) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_143_REG (CSR_MQM_ENQC_BASE + 0x448) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_144_REG (CSR_MQM_ENQC_BASE + 0x44C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_145_REG (CSR_MQM_ENQC_BASE + 0x450) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_146_REG (CSR_MQM_ENQC_BASE + 0x454) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_147_REG (CSR_MQM_ENQC_BASE + 0x458) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_148_REG (CSR_MQM_ENQC_BASE + 0x45C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_149_REG (CSR_MQM_ENQC_BASE + 0x460) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_150_REG (CSR_MQM_ENQC_BASE + 0x464) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_151_REG (CSR_MQM_ENQC_BASE + 0x468) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_152_REG (CSR_MQM_ENQC_BASE + 0x46C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_153_REG (CSR_MQM_ENQC_BASE + 0x470) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_154_REG (CSR_MQM_ENQC_BASE + 0x474) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_155_REG (CSR_MQM_ENQC_BASE + 0x478) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_156_REG (CSR_MQM_ENQC_BASE + 0x47C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_157_REG (CSR_MQM_ENQC_BASE + 0x480) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_158_REG (CSR_MQM_ENQC_BASE + 0x484) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_159_REG (CSR_MQM_ENQC_BASE + 0x488) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_160_REG (CSR_MQM_ENQC_BASE + 0x48C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_161_REG (CSR_MQM_ENQC_BASE + 0x490) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_162_REG (CSR_MQM_ENQC_BASE + 0x494) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_163_REG (CSR_MQM_ENQC_BASE + 0x498) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_164_REG (CSR_MQM_ENQC_BASE + 0x49C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_165_REG (CSR_MQM_ENQC_BASE + 0x4A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_166_REG (CSR_MQM_ENQC_BASE + 0x4A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_167_REG (CSR_MQM_ENQC_BASE + 0x4A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_168_REG (CSR_MQM_ENQC_BASE + 0x4AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_169_REG (CSR_MQM_ENQC_BASE + 0x4B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_170_REG (CSR_MQM_ENQC_BASE + 0x4B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_171_REG (CSR_MQM_ENQC_BASE + 0x4B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_172_REG (CSR_MQM_ENQC_BASE + 0x4BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_173_REG (CSR_MQM_ENQC_BASE + 0x4C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_174_REG (CSR_MQM_ENQC_BASE + 0x4C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_175_REG (CSR_MQM_ENQC_BASE + 0x4C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_176_REG (CSR_MQM_ENQC_BASE + 0x4CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_177_REG (CSR_MQM_ENQC_BASE + 0x4D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_178_REG (CSR_MQM_ENQC_BASE + 0x4D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_179_REG (CSR_MQM_ENQC_BASE + 0x4D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_180_REG (CSR_MQM_ENQC_BASE + 0x4DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_181_REG (CSR_MQM_ENQC_BASE + 0x4E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_182_REG (CSR_MQM_ENQC_BASE + 0x4E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_183_REG (CSR_MQM_ENQC_BASE + 0x4E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_184_REG (CSR_MQM_ENQC_BASE + 0x4EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_185_REG (CSR_MQM_ENQC_BASE + 0x4F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_186_REG (CSR_MQM_ENQC_BASE + 0x4F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_187_REG (CSR_MQM_ENQC_BASE + 0x4F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_188_REG (CSR_MQM_ENQC_BASE + 0x4FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_189_REG (CSR_MQM_ENQC_BASE + 0x500) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_190_REG (CSR_MQM_ENQC_BASE + 0x504) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_191_REG (CSR_MQM_ENQC_BASE + 0x508) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_192_REG (CSR_MQM_ENQC_BASE + 0x50C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_193_REG (CSR_MQM_ENQC_BASE + 0x510) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_194_REG (CSR_MQM_ENQC_BASE + 0x514) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_195_REG (CSR_MQM_ENQC_BASE + 0x518) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_196_REG (CSR_MQM_ENQC_BASE + 0x51C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_197_REG (CSR_MQM_ENQC_BASE + 0x520) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_198_REG (CSR_MQM_ENQC_BASE + 0x524) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_199_REG (CSR_MQM_ENQC_BASE + 0x528) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_200_REG (CSR_MQM_ENQC_BASE + 0x52C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_201_REG (CSR_MQM_ENQC_BASE + 0x530) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_202_REG (CSR_MQM_ENQC_BASE + 0x534) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_203_REG (CSR_MQM_ENQC_BASE + 0x538) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_204_REG (CSR_MQM_ENQC_BASE + 0x53C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_205_REG (CSR_MQM_ENQC_BASE + 0x540) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_206_REG (CSR_MQM_ENQC_BASE + 0x544) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_207_REG (CSR_MQM_ENQC_BASE + 0x548) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_208_REG (CSR_MQM_ENQC_BASE + 0x54C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_209_REG (CSR_MQM_ENQC_BASE + 0x550) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_210_REG (CSR_MQM_ENQC_BASE + 0x554) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_211_REG (CSR_MQM_ENQC_BASE + 0x558) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_212_REG (CSR_MQM_ENQC_BASE + 0x55C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_213_REG (CSR_MQM_ENQC_BASE + 0x560) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_214_REG (CSR_MQM_ENQC_BASE + 0x564) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_215_REG (CSR_MQM_ENQC_BASE + 0x568) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_216_REG (CSR_MQM_ENQC_BASE + 0x56C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_217_REG (CSR_MQM_ENQC_BASE + 0x570) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_218_REG (CSR_MQM_ENQC_BASE + 0x574) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_219_REG (CSR_MQM_ENQC_BASE + 0x578) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_220_REG (CSR_MQM_ENQC_BASE + 0x57C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_221_REG (CSR_MQM_ENQC_BASE + 0x580) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_222_REG (CSR_MQM_ENQC_BASE + 0x584) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_223_REG (CSR_MQM_ENQC_BASE + 0x588) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_224_REG (CSR_MQM_ENQC_BASE + 0x58C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_225_REG (CSR_MQM_ENQC_BASE + 0x590) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_226_REG (CSR_MQM_ENQC_BASE + 0x594) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_227_REG (CSR_MQM_ENQC_BASE + 0x598) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_228_REG (CSR_MQM_ENQC_BASE + 0x59C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_229_REG (CSR_MQM_ENQC_BASE + 0x5A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_230_REG (CSR_MQM_ENQC_BASE + 0x5A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_231_REG (CSR_MQM_ENQC_BASE + 0x5A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_232_REG (CSR_MQM_ENQC_BASE + 0x5AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_233_REG (CSR_MQM_ENQC_BASE + 0x5B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_234_REG (CSR_MQM_ENQC_BASE + 0x5B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_235_REG (CSR_MQM_ENQC_BASE + 0x5B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_236_REG (CSR_MQM_ENQC_BASE + 0x5BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_237_REG (CSR_MQM_ENQC_BASE + 0x5C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_238_REG (CSR_MQM_ENQC_BASE + 0x5C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_239_REG (CSR_MQM_ENQC_BASE + 0x5C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_240_REG (CSR_MQM_ENQC_BASE + 0x5CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_241_REG (CSR_MQM_ENQC_BASE + 0x5D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_242_REG (CSR_MQM_ENQC_BASE + 0x5D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_243_REG (CSR_MQM_ENQC_BASE + 0x5D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_244_REG (CSR_MQM_ENQC_BASE + 0x5DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_245_REG (CSR_MQM_ENQC_BASE + 0x5E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_246_REG (CSR_MQM_ENQC_BASE + 0x5E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_247_REG (CSR_MQM_ENQC_BASE + 0x5E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_248_REG (CSR_MQM_ENQC_BASE + 0x5EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_249_REG (CSR_MQM_ENQC_BASE + 0x5F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_250_REG (CSR_MQM_ENQC_BASE + 0x5F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_251_REG (CSR_MQM_ENQC_BASE + 0x5F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_252_REG (CSR_MQM_ENQC_BASE + 0x5FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_253_REG (CSR_MQM_ENQC_BASE + 0x600) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_254_REG (CSR_MQM_ENQC_BASE + 0x604) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_255_REG (CSR_MQM_ENQC_BASE + 0x608) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_0_REG (CSR_MQM_ENQC_BASE + 0x60C) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_1_REG (CSR_MQM_ENQC_BASE + 0x610) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_2_REG (CSR_MQM_ENQC_BASE + 0x614) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_3_REG (CSR_MQM_ENQC_BASE + 0x618) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_4_REG (CSR_MQM_ENQC_BASE + 0x61C) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_5_REG (CSR_MQM_ENQC_BASE + 0x620) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_6_REG (CSR_MQM_ENQC_BASE + 0x624) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_7_REG (CSR_MQM_ENQC_BASE + 0x628) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_8_REG (CSR_MQM_ENQC_BASE + 0x62C) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_9_REG (CSR_MQM_ENQC_BASE + 0x630) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_10_REG (CSR_MQM_ENQC_BASE + 0x634) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_11_REG (CSR_MQM_ENQC_BASE + 0x638) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_12_REG (CSR_MQM_ENQC_BASE + 0x63C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_13_REG (CSR_MQM_ENQC_BASE + 0x640) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_14_REG (CSR_MQM_ENQC_BASE + 0x644) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_15_REG (CSR_MQM_ENQC_BASE + 0x648) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_16_REG (CSR_MQM_ENQC_BASE + 0x64C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_17_REG (CSR_MQM_ENQC_BASE + 0x650) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_18_REG (CSR_MQM_ENQC_BASE + 0x654) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_19_REG (CSR_MQM_ENQC_BASE + 0x658) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_20_REG (CSR_MQM_ENQC_BASE + 0x65C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_21_REG (CSR_MQM_ENQC_BASE + 0x660) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_22_REG (CSR_MQM_ENQC_BASE + 0x664) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_23_REG (CSR_MQM_ENQC_BASE + 0x668) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_24_REG (CSR_MQM_ENQC_BASE + 0x66C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_25_REG (CSR_MQM_ENQC_BASE + 0x670) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_26_REG (CSR_MQM_ENQC_BASE + 0x674) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_27_REG (CSR_MQM_ENQC_BASE + 0x678) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_28_REG (CSR_MQM_ENQC_BASE + 0x67C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_29_REG (CSR_MQM_ENQC_BASE + 0x680) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_30_REG (CSR_MQM_ENQC_BASE + 0x684) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_31_REG (CSR_MQM_ENQC_BASE + 0x688) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_32_REG (CSR_MQM_ENQC_BASE + 0x68C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_33_REG (CSR_MQM_ENQC_BASE + 0x690) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_34_REG (CSR_MQM_ENQC_BASE + 0x694) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_35_REG (CSR_MQM_ENQC_BASE + 0x698) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_36_REG (CSR_MQM_ENQC_BASE + 0x69C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_37_REG (CSR_MQM_ENQC_BASE + 0x6A0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_38_REG (CSR_MQM_ENQC_BASE + 0x6A4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_39_REG (CSR_MQM_ENQC_BASE + 0x6A8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_40_REG (CSR_MQM_ENQC_BASE + 0x6AC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_41_REG (CSR_MQM_ENQC_BASE + 0x6B0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_42_REG (CSR_MQM_ENQC_BASE + 0x6B4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_43_REG (CSR_MQM_ENQC_BASE + 0x6B8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_44_REG (CSR_MQM_ENQC_BASE + 0x6BC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_45_REG (CSR_MQM_ENQC_BASE + 0x6C0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_46_REG (CSR_MQM_ENQC_BASE + 0x6C4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_47_REG (CSR_MQM_ENQC_BASE + 0x6C8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_48_REG (CSR_MQM_ENQC_BASE + 0x6CC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_49_REG (CSR_MQM_ENQC_BASE + 0x6D0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_50_REG (CSR_MQM_ENQC_BASE + 0x6D4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_51_REG (CSR_MQM_ENQC_BASE + 0x6D8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_52_REG (CSR_MQM_ENQC_BASE + 0x6DC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_53_REG (CSR_MQM_ENQC_BASE + 0x6E0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_54_REG (CSR_MQM_ENQC_BASE + 0x6E4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_55_REG (CSR_MQM_ENQC_BASE + 0x6E8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_56_REG (CSR_MQM_ENQC_BASE + 0x6EC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_57_REG (CSR_MQM_ENQC_BASE + 0x6F0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_58_REG (CSR_MQM_ENQC_BASE + 0x6F4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_59_REG (CSR_MQM_ENQC_BASE + 0x6F8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_60_REG (CSR_MQM_ENQC_BASE + 0x6FC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_61_REG (CSR_MQM_ENQC_BASE + 0x700) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_62_REG (CSR_MQM_ENQC_BASE + 0x704) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_63_REG (CSR_MQM_ENQC_BASE + 0x708) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_64_REG (CSR_MQM_ENQC_BASE + 0x70C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_65_REG (CSR_MQM_ENQC_BASE + 0x710) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_66_REG (CSR_MQM_ENQC_BASE + 0x714) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_67_REG (CSR_MQM_ENQC_BASE + 0x718) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_68_REG (CSR_MQM_ENQC_BASE + 0x71C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_69_REG (CSR_MQM_ENQC_BASE + 0x720) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_70_REG (CSR_MQM_ENQC_BASE + 0x724) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_71_REG (CSR_MQM_ENQC_BASE + 0x728) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_72_REG (CSR_MQM_ENQC_BASE + 0x72C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_73_REG (CSR_MQM_ENQC_BASE + 0x730) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_74_REG (CSR_MQM_ENQC_BASE + 0x734) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_75_REG (CSR_MQM_ENQC_BASE + 0x738) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_76_REG (CSR_MQM_ENQC_BASE + 0x73C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_77_REG (CSR_MQM_ENQC_BASE + 0x740) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_78_REG (CSR_MQM_ENQC_BASE + 0x744) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_79_REG (CSR_MQM_ENQC_BASE + 0x748) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_80_REG (CSR_MQM_ENQC_BASE + 0x74C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_81_REG (CSR_MQM_ENQC_BASE + 0x750) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_82_REG (CSR_MQM_ENQC_BASE + 0x754) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_83_REG (CSR_MQM_ENQC_BASE + 0x758) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_84_REG (CSR_MQM_ENQC_BASE + 0x75C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_85_REG (CSR_MQM_ENQC_BASE + 0x760) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_86_REG (CSR_MQM_ENQC_BASE + 0x764) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_87_REG (CSR_MQM_ENQC_BASE + 0x768) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_88_REG (CSR_MQM_ENQC_BASE + 0x76C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_89_REG (CSR_MQM_ENQC_BASE + 0x770) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_90_REG (CSR_MQM_ENQC_BASE + 0x774) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_91_REG (CSR_MQM_ENQC_BASE + 0x778) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_92_REG (CSR_MQM_ENQC_BASE + 0x77C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_93_REG (CSR_MQM_ENQC_BASE + 0x780) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_94_REG (CSR_MQM_ENQC_BASE + 0x784) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_95_REG (CSR_MQM_ENQC_BASE + 0x788) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_96_REG (CSR_MQM_ENQC_BASE + 0x78C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_97_REG (CSR_MQM_ENQC_BASE + 0x790) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_98_REG (CSR_MQM_ENQC_BASE + 0x794) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_99_REG (CSR_MQM_ENQC_BASE + 0x798) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_100_REG (CSR_MQM_ENQC_BASE + 0x79C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_101_REG (CSR_MQM_ENQC_BASE + 0x7A0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_102_REG (CSR_MQM_ENQC_BASE + 0x7A4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_103_REG (CSR_MQM_ENQC_BASE + 0x7A8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_104_REG (CSR_MQM_ENQC_BASE + 0x7AC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_105_REG (CSR_MQM_ENQC_BASE + 0x7B0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_106_REG (CSR_MQM_ENQC_BASE + 0x7B4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_107_REG (CSR_MQM_ENQC_BASE + 0x7B8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_108_REG (CSR_MQM_ENQC_BASE + 0x7BC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_109_REG (CSR_MQM_ENQC_BASE + 0x7C0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_110_REG (CSR_MQM_ENQC_BASE + 0x7C4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_111_REG (CSR_MQM_ENQC_BASE + 0x7C8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_112_REG (CSR_MQM_ENQC_BASE + 0x7CC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_113_REG (CSR_MQM_ENQC_BASE + 0x7D0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_114_REG (CSR_MQM_ENQC_BASE + 0x7D4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_115_REG (CSR_MQM_ENQC_BASE + 0x7D8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_116_REG (CSR_MQM_ENQC_BASE + 0x7DC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_117_REG (CSR_MQM_ENQC_BASE + 0x7E0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_118_REG (CSR_MQM_ENQC_BASE + 0x7E4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_119_REG (CSR_MQM_ENQC_BASE + 0x7E8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_120_REG (CSR_MQM_ENQC_BASE + 0x7EC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_121_REG (CSR_MQM_ENQC_BASE + 0x7F0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_122_REG (CSR_MQM_ENQC_BASE + 0x7F4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_123_REG (CSR_MQM_ENQC_BASE + 0x7F8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_124_REG (CSR_MQM_ENQC_BASE + 0x7FC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_125_REG (CSR_MQM_ENQC_BASE + 0x800) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_126_REG (CSR_MQM_ENQC_BASE + 0x804) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_127_REG (CSR_MQM_ENQC_BASE + 0x808) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_FLUSH_QF_EMQCNT_DONE_REG (CSR_MQM_ENQC_BASE + 0x80C) /* enqc flush qf done and emq cnt done \ + */ +#define CSR_MQM_ENQC_ENQC_ECC_1BIT_ERR_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x810) /* statistics counter of ENQC memory ECC 1bit ERR */ +#define CSR_MQM_ENQC_ENQC_ECC_2BIT_ERR_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x814) /* statistics counter of ENQC memory ECC 2bit ERR */ +#define CSR_MQM_ENQC_ENQC_RX_DU_PACKET_REG \ + (CSR_MQM_ENQC_BASE + 0x830) /* statistics of the number of delay-update packet received by mqm */ +#define CSR_MQM_ENQC_ENQC_RX_DU_LENGTH_REG \ + (CSR_MQM_ENQC_BASE + 0x834) /* statistics of the length that delay-update packet received by MQM */ +#define CSR_MQM_ENQC_CPI_IN_EMQCNT_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x838) /* the status of cpi input fifo */ +#define CSR_MQM_ENQC_SM_IN_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x83C) /* the status of sm input fifo */ +#define CSR_MQM_ENQC_TILE_QU_IN_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x840) /* the status of tile and qu input fifo */ +#define CSR_MQM_ENQC_ENQC_MRF_DU_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x844) /* the status of message receive fifo */ +#define CSR_MQM_ENQC_ENQC_PASSTHRU_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x848) /* enqc passthrough fifo status */ +#define CSR_MQM_ENQC_ENQC_INPUT_BP_REG (CSR_MQM_ENQC_BASE + 0x84C) /* the backpress enqc to cpi doorbell interface */ +#define CSR_MQM_ENQC_ENQC_EQM_QD_CNT_REG (CSR_MQM_ENQC_BASE + 0x850) /* EQM QD cnt */ +#define CSR_MQM_ENQC_ENQC_RX_CPI_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x854) /* statistics of the number of doorbell receive from CPI */ +#define CSR_MQM_ENQC_ENQC_RX_SM_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x858) /* statistics of the number of doorbell receive from SM */ +#define CSR_MQM_ENQC_ENQC_RX_TILE_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x85C) /* statistics of the number of doorbell receive from Tile */ +#define CSR_MQM_ENQC_ENQC_RX_QU_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x860) /* statistics of the number of doorbell receive from QU */ +#define CSR_MQM_ENQC_ENQC_DIS_CPI_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x864) /* statistics of the number of doorbell discard by mqm which come from CPI */ +#define CSR_MQM_ENQC_ENQC_RX_RING_ERR_DB_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x868) /* statistics of the number of doorbell which is ring error */ +#define CSR_MQM_ENQC_ENQC_ENQ_IQM_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x86C) /* statistics of the number of doobell en-queue to IQM */ +#define CSR_MQM_ENQC_ENQC_ENQ_EQM_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x870) /* statistics of the number of doorbell en-queue to EQM */ +#define CSR_MQM_ENQC_ENQC_FILTERD_DB_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x874) /* statistics of the number of doorbell which is filterd by queue filter function */ +#define CSR_MQM_ENQC_ENQC_RX_SM_CP_SGE_CRDT_REG (CSR_MQM_ENQC_BASE + 0x878) /* enqc rx sm cp sge comp crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_SM_DP_SGE_CRDT_REG (CSR_MQM_ENQC_BASE + 0x87C) /* enqc rx sm dp sge comp crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_SM_CP_DATA_CRDT_REG (CSR_MQM_ENQC_BASE + 0x880) /* enqc rx sm cp comp data crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_SM_DP_DATA_CRDT_REG (CSR_MQM_ENQC_BASE + 0x884) /* enqc rx sm dp comp data crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_DP_NOFL_DB_REG (CSR_MQM_ENQC_BASE + 0x888) /* enqc rx dp nonfilter db cnt */ +#define CSR_MQM_ENQC_DB_OVFL_VF_RANGE_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x88C) /* Statics the number of doorbell's txqid overflow range of VF */ +#define CSR_MQM_ENQC_NONF_DB_NUM_OVFL_THR_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x890) /* Statics the number of non-filter doorbell overflow threshold of VF */ +#define CSR_MQM_ENQC_MQM_ERR_TYP_DB_CNT_REG (CSR_MQM_ENQC_BASE + 0x894) /* Static the number of error type doorbell */ +#define CSR_MQM_ENQC_PASS_THROUGH_STA_REG (CSR_MQM_ENQC_BASE + 0x898) /* Pass through function status register. */ + +/* MQM_BRM Base address of Module's Register */ +#define CSR_MQM_BRM_BASE (0x6000) + +/* **************************************************************************** */ +/* MQM_BRM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_BRM_BRM_RW_RSV0_REG (CSR_MQM_BRM_BASE + 0x0) /* brm rw reserved register 0 */ +#define CSR_MQM_BRM_BRM_RW_RSV1_REG (CSR_MQM_BRM_BASE + 0x4) /* brm rw reserved register 1 */ +#define CSR_MQM_BRM_BRM_RW_RSV2_REG (CSR_MQM_BRM_BASE + 0x8) /* brm rw reserved register 2 */ +#define CSR_MQM_BRM_BRM_RW_RSV3_REG (CSR_MQM_BRM_BASE + 0xC) /* brm rw reserved register 3 */ +#define CSR_MQM_BRM_BRM_INDRECT_CTRL_REG (CSR_MQM_BRM_BASE + 0x10) /* BRM Indirect access ctrl Register。 */ +#define CSR_MQM_BRM_BRM_INDRECT_TIMEOUT_REG (CSR_MQM_BRM_BASE + 0x14) /* BRM Indirect Access Timeout Register。 */ +#define CSR_MQM_BRM_BRM_INDRECT_DATA_0_REG (CSR_MQM_BRM_BASE + 0x18) /* BRM Indirect Access Data Register0 */ +#define CSR_MQM_BRM_BRM_INDRECT_DATA_1_REG (CSR_MQM_BRM_BASE + 0x1C) /* BRM Indirect Access Data Register1 */ +#define CSR_MQM_BRM_BRM_INT_VECTOR_REG (CSR_MQM_BRM_BASE + 0x20) /* brm int vector */ +#define CSR_MQM_BRM_BRM_INT_REG (CSR_MQM_BRM_BASE + 0x24) /* brm int */ +#define CSR_MQM_BRM_BRM_INT_EN_REG (CSR_MQM_BRM_BASE + 0x28) /* brm int enable */ +#define CSR_MQM_BRM_BRM_MEM_ECC0_REG (CSR_MQM_BRM_BASE + 0x2C) /* RAM ECC ONE BIT ERR */ +#define CSR_MQM_BRM_BRM_MEM_ECC1_REG (CSR_MQM_BRM_BASE + 0x30) /* RAM ECC TWO BIT ERR */ +#define CSR_MQM_BRM_BRM_DB_FLT_ADDR_OVFL_INT_REG \ + (CSR_MQM_BRM_BASE + 0x34) /* BRM Doorbell Fliter Address Overflow Int */ +#define CSR_MQM_BRM_BRM_CNT_ADDR_OVFL_INT_REG (CSR_MQM_BRM_BASE + 0x38) /* BRM PI Store Address Overflow cfg Int */ +#define CSR_MQM_BRM_BRM_ATT_CNT_MEM_ECC_REQ_REG \ + (CSR_MQM_BRM_BASE + 0x50) /* BRM PI/ATT memory ecc insert request Register */ +#define CSR_MQM_BRM_BRM_QF_QD_MEM_ECC_REQ_REG \ + (CSR_MQM_BRM_BASE + 0x54) /* BRM QF/QD memory ecc insert request Register */ +#define CSR_MQM_BRM_BRM_QUE_FILT_SPA_REG \ + (CSR_MQM_BRM_BASE + 0x80) /* the space of queue filter and queue description cfg */ +#define CSR_MQM_BRM_BRM_ATT_SIZE_REG \ + (CSR_MQM_BRM_BASE + 0x84) /* the space of GPA address translation and PI store space cfg */ +#define CSR_MQM_BRM_BRM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_BRM_BASE + 0x88) /* BRM RAM ECC BYPASS ctrl en */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_BRM_BASE + 0x8C) /* BRM RAM ctrl bus cfg reg0 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_BRM_BASE + 0x90) /* BRM RAM ctrl bus cfg reg1 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_BRM_BASE + 0x94) /* BRM RAM ctrl bus cfg reg2 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_BRM_BASE + 0x98) /* BRM RAM ctrl bus cfg reg3 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_BRM_BASE + 0x9C) /* BRM RAM ctrl bus cfg reg4 */ +#define CSR_MQM_BRM_BRM_ECC_1BIT_ERR_CNT_REG \ + (CSR_MQM_BRM_BASE + 0xB0) /* statistics counter of BRM memory ECC 1bit ERR */ +#define CSR_MQM_BRM_BRM_ECC_2BIT_ERR_CNT_REG \ + (CSR_MQM_BRM_BASE + 0xB4) /* statistics counter of BRM memory ECC 2bit ERR */ + +/* MQM_IQM Base address of Module's Register */ +#define CSR_MQM_IQM_BASE (0x8000) + +/* **************************************************************************** */ +/* MQM_IQM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_IQM_IQM_RW_RSV0_REG (CSR_MQM_IQM_BASE + 0x0) /* iqm rw reserved register 0 */ +#define CSR_MQM_IQM_IQM_RW_RSV1_REG (CSR_MQM_IQM_BASE + 0x4) /* iqm rw reserved register 1 */ +#define CSR_MQM_IQM_IQM_RW_RSV2_REG (CSR_MQM_IQM_BASE + 0x8) /* iqm rw reserved register 2 */ +#define CSR_MQM_IQM_IQM_RW_RSV3_REG (CSR_MQM_IQM_BASE + 0xC) /* iqm rw reserved register 3 */ +#define CSR_MQM_IQM_IQM_INDRECT_CTRL_REG (CSR_MQM_IQM_BASE + 0x10) /* IQM Indirect access ctrl Register。 */ +#define CSR_MQM_IQM_IQM_INDRECT_TIMEOUT_REG (CSR_MQM_IQM_BASE + 0x14) /* IQM Indirect Access Timeout Register。 */ +#define CSR_MQM_IQM_IQM_INDRECT_DATA_0_REG (CSR_MQM_IQM_BASE + 0x18) /* IQM Indirect Access Data Register0 */ +#define CSR_MQM_IQM_IQM_INDRECT_DATA_1_REG (CSR_MQM_IQM_BASE + 0x1C) /* IQM Indirect Access Data Register1 */ +#define CSR_MQM_IQM_IQM_INT_VECTOR_REG (CSR_MQM_IQM_BASE + 0x20) /* iqm int vector */ +#define CSR_MQM_IQM_IQM_INT_REG (CSR_MQM_IQM_BASE + 0x24) /* iqm int */ +#define CSR_MQM_IQM_IQM_INT_EN_REG (CSR_MQM_IQM_BASE + 0x28) /* iqm int enable */ +#define CSR_MQM_IQM_IQM_MEM_ECC0_REG (CSR_MQM_IQM_BASE + 0x2C) /* RAM ECC ONE BIT ERR */ +#define CSR_MQM_IQM_IQM_MEM_ECC1_REG (CSR_MQM_IQM_BASE + 0x30) /* RAM ECC TWO BIT ERR */ +#define CSR_MQM_IQM_IQM_AGING_INT_REG (CSR_MQM_IQM_BASE + 0x34) /* iqm aging int */ +#define CSR_MQM_IQM_IQM_CMQ_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x38) /* iqm cmq link list deq emtpy int */ +#define CSR_MQM_IQM_IQM_FIFO_WR_OVFL_INT_REG (CSR_MQM_IQM_BASE + 0x3C) /* iqm fifo write overflow int */ +#define CSR_MQM_IQM_IQM_FIFO_RD_UDFL_INT_REG (CSR_MQM_IQM_BASE + 0x40) /* iqm fifo read underflow int */ +#define CSR_MQM_IQM_IQM_FREE_RSC_BMP_OVERFLOW_INT_REG \ + (CSR_MQM_IQM_BASE + 0x44) /* iqm free resource bitmap ovfl int err */ +#define CSR_MQM_IQM_IQM_CLL_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x48) /* iqm nmq/nfmq chunk link list deq emtpy int \ + */ +#define CSR_MQM_IQM_IQM_UXMQ_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x4C) /* iqm unmq or ucmq link list deq empty int \ + */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ1_REG (CSR_MQM_IQM_BASE + 0x50) /* IQM FIFO INT REQ1 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ2_REG (CSR_MQM_IQM_BASE + 0x54) /* IQM FIFO INT REQ2 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ3_REG (CSR_MQM_IQM_BASE + 0x58) /* IQM FIFO INT REQ3 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ4_REG (CSR_MQM_IQM_BASE + 0x5C) /* IQM FIFO INT REQ4 */ +#define CSR_MQM_IQM_IQM_MEM_ECC_REQ0_REG (CSR_MQM_IQM_BASE + 0x60) /* IQM memory ecc insert request Register0 */ +#define CSR_MQM_IQM_IQM_MEM_ECC_REQ1_REG (CSR_MQM_IQM_BASE + 0x64) /* IQM memory ecc insert request Register1 */ +#define CSR_MQM_IQM_IQM_UNCRT_INT_EN_REG (CSR_MQM_IQM_BASE + 0x68) /* IQM uncorect int mask */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ5_REG (CSR_MQM_IQM_BASE + 0x6C) /* IQM FIFO INT REQ5 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ6_REG (CSR_MQM_IQM_BASE + 0x70) /* IQM FIFO INT REQ6 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ7_REG (CSR_MQM_IQM_BASE + 0x74) /* IQM FIFO INT REQ7 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ8_REG (CSR_MQM_IQM_BASE + 0x78) /* IQM FIFO INT REQ8 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ9_REG (CSR_MQM_IQM_BASE + 0x7C) /* IQM FIFO INT REQ9 */ +#define CSR_MQM_IQM_IQM_CHUNK_REG (CSR_MQM_IQM_BASE + 0x80) /* chunk configuration register */ +#define CSR_MQM_IQM_IQM_OUT_FIFO_TH_GAP_REG (CSR_MQM_IQM_BASE + 0x84) /* IQM fifo threshold configuration */ +#define CSR_MQM_IQM_IQM_ENQ_FIFO_AFUL_GAP_REG \ + (CSR_MQM_IQM_BASE + 0x88) /* IQM en-queue almost full threshold config register */ +#define CSR_MQM_IQM_IQM_CRDT_COMP_FIFO_GAP_CFG_REG (CSR_MQM_IQM_BASE + 0x8C) /* iqm credit comp fifo gap */ +#define CSR_MQM_IQM_IQM_AGING_CFG_REG (CSR_MQM_IQM_BASE + 0x90) /* aging configuration register */ +#define CSR_MQM_IQM_IQM_DES_QUE_DEQ_CFG0_REG (CSR_MQM_IQM_BASE + 0x94) /* IQM designate Queue De-queue cfg register */ +#define CSR_MQM_IQM_IQM_DES_QUE_DEQ_CFG1_REG (CSR_MQM_IQM_BASE + 0x98) /* IQM designate queue De-queue vld and VF ID \ + */ +#define CSR_MQM_IQM_IQM_ROOT_THR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x9C) /* the static threshold for root level config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_ROOT_HTHR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0xA0) /* the high threshold offset parameter for root config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_ROOT_THR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0xA4) /* the static threshold of root level nmq config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_ROOT_THR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0xA8) /* the static threshold of root level nfmq config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST0_TH_REG \ + (CSR_MQM_IQM_BASE + 0xAC) /* the static threshold of nmq host0 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST1_TH_REG \ + (CSR_MQM_IQM_BASE + 0xB0) /* the static threshold of nmq host1 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST2_TH_REG \ + (CSR_MQM_IQM_BASE + 0xB4) /* the static threshold of nmq host2 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST3_TH_REG \ + (CSR_MQM_IQM_BASE + 0xB8) /* the static threshold of nmq host3 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST_HTH_PA_REG \ + (CSR_MQM_IQM_BASE + 0xBC) /* the nmq high threshold offset parameter config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST0_TH_REG \ + (CSR_MQM_IQM_BASE + 0xC0) /* the static threshold of nfmq host0 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST1_TH_REG \ + (CSR_MQM_IQM_BASE + 0xC4) /* the static threshold of nfmq host1 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST2_TH_REG \ + (CSR_MQM_IQM_BASE + 0xC8) /* the static threshold of nfmq host2 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST3_TH_REG \ + (CSR_MQM_IQM_BASE + 0xCC) /* the static threshold of nfmq host3 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST_HTH_PA_REG \ + (CSR_MQM_IQM_BASE + 0xD0) /* the nfmq high threshold offset parameter config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_0_REG \ + (CSR_MQM_IQM_BASE + 0xD4) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_1_REG \ + (CSR_MQM_IQM_BASE + 0xD8) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_2_REG \ + (CSR_MQM_IQM_BASE + 0xDC) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_3_REG \ + (CSR_MQM_IQM_BASE + 0xE0) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_0_REG \ + (CSR_MQM_IQM_BASE + 0xE4) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_1_REG \ + (CSR_MQM_IQM_BASE + 0xE8) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_2_REG \ + (CSR_MQM_IQM_BASE + 0xEC) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_3_REG \ + (CSR_MQM_IQM_BASE + 0xF0) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_0_REG \ + (CSR_MQM_IQM_BASE + 0xF4) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_1_REG \ + (CSR_MQM_IQM_BASE + 0xF8) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_2_REG \ + (CSR_MQM_IQM_BASE + 0xFC) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_3_REG \ + (CSR_MQM_IQM_BASE + 0x100) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_4_REG \ + (CSR_MQM_IQM_BASE + 0x104) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_5_REG \ + (CSR_MQM_IQM_BASE + 0x108) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_6_REG \ + (CSR_MQM_IQM_BASE + 0x10C) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_7_REG \ + (CSR_MQM_IQM_BASE + 0x110) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_8_REG \ + (CSR_MQM_IQM_BASE + 0x114) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_9_REG \ + (CSR_MQM_IQM_BASE + 0x118) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_10_REG \ + (CSR_MQM_IQM_BASE + 0x11C) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_11_REG \ + (CSR_MQM_IQM_BASE + 0x120) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_12_REG \ + (CSR_MQM_IQM_BASE + 0x124) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_13_REG \ + (CSR_MQM_IQM_BASE + 0x128) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_14_REG \ + (CSR_MQM_IQM_BASE + 0x12C) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_15_REG \ + (CSR_MQM_IQM_BASE + 0x130) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_0_REG \ + (CSR_MQM_IQM_BASE + 0x134) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_1_REG \ + (CSR_MQM_IQM_BASE + 0x138) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_2_REG \ + (CSR_MQM_IQM_BASE + 0x13C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_3_REG \ + (CSR_MQM_IQM_BASE + 0x140) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_4_REG \ + (CSR_MQM_IQM_BASE + 0x144) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_5_REG \ + (CSR_MQM_IQM_BASE + 0x148) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_6_REG \ + (CSR_MQM_IQM_BASE + 0x14C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_7_REG \ + (CSR_MQM_IQM_BASE + 0x150) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_8_REG \ + (CSR_MQM_IQM_BASE + 0x154) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_9_REG \ + (CSR_MQM_IQM_BASE + 0x158) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_10_REG \ + (CSR_MQM_IQM_BASE + 0x15C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_11_REG \ + (CSR_MQM_IQM_BASE + 0x160) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_12_REG \ + (CSR_MQM_IQM_BASE + 0x164) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_13_REG \ + (CSR_MQM_IQM_BASE + 0x168) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_14_REG \ + (CSR_MQM_IQM_BASE + 0x16C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_15_REG \ + (CSR_MQM_IQM_BASE + 0x170) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_QTSS_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x174) /* queue level share space config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HETSS_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x178) /* host_ep level share space config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HECTSS_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x17C) /* host_ep_cos level share space config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_0_REG \ + (CSR_MQM_IQM_BASE + 0x180) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_1_REG \ + (CSR_MQM_IQM_BASE + 0x184) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_2_REG \ + (CSR_MQM_IQM_BASE + 0x188) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_3_REG \ + (CSR_MQM_IQM_BASE + 0x18C) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_4_REG \ + (CSR_MQM_IQM_BASE + 0x190) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_CREDIT_TSS_CFG_DATA_REG \ + (CSR_MQM_IQM_BASE + 0x194) /* the total share data ep credit space of sm */ +#define CSR_MQM_IQM_IQM_SM_CREDIT_TSS_CFG_SGE_REG \ + (CSR_MQM_IQM_BASE + 0x198) /* the total share sge ep credit space of sm */ +#define CSR_MQM_IQM_IQM_QU_CREDIT_TSS_CFG_REG (CSR_MQM_IQM_BASE + 0x19C) /* the total share ep credit space of qu */ +#define CSR_MQM_IQM_IQM_CRR_WGT_CFG_REG (CSR_MQM_IQM_BASE + 0x1A0) /* out to sm or qu crr weight cfg */ +#define CSR_MQM_IQM_IQM_DB_MERGER_CFG_REG (CSR_MQM_IQM_BASE + 0x1A4) /* IQM DB Merger conctrl Register */ +#define CSR_MQM_IQM_SMF_DST_HASH_CFG_REG (CSR_MQM_IQM_BASE + 0x1A8) /* SMF destination hash cfg */ +#define CSR_MQM_IQM_IQM_AGING_CLR_CFG_REG (CSR_MQM_IQM_BASE + 0x1AC) /* aging cnt and vld clr register */ +#define CSR_MQM_IQM_IQM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_IQM_BASE + 0x1B0) /* IQM RAM ECC BYPASS ctrl en */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_IQM_BASE + 0x1B4) /* IQM RAM ctrl bus cfg reg0 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_IQM_BASE + 0x1B8) /* IQM RAM ctrl bus cfg reg1 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_IQM_BASE + 0x1BC) /* IQM RAM ctrl bus cfg reg2 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_IQM_BASE + 0x1C0) /* IQM RAM ctrl bus cfg reg3 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_IQM_BASE + 0x1C4) /* IQM RAM ctrl bus cfg reg4 */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_0_REG (CSR_MQM_IQM_BASE + 0x1E0) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_1_REG (CSR_MQM_IQM_BASE + 0x1E4) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_2_REG (CSR_MQM_IQM_BASE + 0x1E8) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_3_REG (CSR_MQM_IQM_BASE + 0x1EC) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_4_REG (CSR_MQM_IQM_BASE + 0x1F0) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_5_REG (CSR_MQM_IQM_BASE + 0x1F4) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_6_REG (CSR_MQM_IQM_BASE + 0x1F8) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_7_REG (CSR_MQM_IQM_BASE + 0x1FC) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_8_REG (CSR_MQM_IQM_BASE + 0x200) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_9_REG (CSR_MQM_IQM_BASE + 0x204) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_10_REG (CSR_MQM_IQM_BASE + 0x208) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_11_REG (CSR_MQM_IQM_BASE + 0x20C) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_12_REG (CSR_MQM_IQM_BASE + 0x210) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_13_REG (CSR_MQM_IQM_BASE + 0x214) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_0_REG (CSR_MQM_IQM_BASE + 0x218) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_1_REG (CSR_MQM_IQM_BASE + 0x21C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_2_REG (CSR_MQM_IQM_BASE + 0x220) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_3_REG (CSR_MQM_IQM_BASE + 0x224) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_4_REG (CSR_MQM_IQM_BASE + 0x228) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_5_REG (CSR_MQM_IQM_BASE + 0x22C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_6_REG (CSR_MQM_IQM_BASE + 0x230) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_7_REG (CSR_MQM_IQM_BASE + 0x234) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_8_REG (CSR_MQM_IQM_BASE + 0x238) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_9_REG (CSR_MQM_IQM_BASE + 0x23C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_10_REG (CSR_MQM_IQM_BASE + 0x240) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_11_REG (CSR_MQM_IQM_BASE + 0x244) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_12_REG (CSR_MQM_IQM_BASE + 0x248) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_13_REG (CSR_MQM_IQM_BASE + 0x24C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_14_REG (CSR_MQM_IQM_BASE + 0x250) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_15_REG (CSR_MQM_IQM_BASE + 0x254) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_16_REG (CSR_MQM_IQM_BASE + 0x258) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_17_REG (CSR_MQM_IQM_BASE + 0x25C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_CMQ_CNT_REG (CSR_MQM_IQM_BASE + 0x260) /* the number of CMQ queue descriptor store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOST_CNT0_REG \ + (CSR_MQM_IQM_BASE + 0x264) /* the number of queue descriptor belone to CMQ host0 and CMQ host1 store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOST_CNT1_REG \ + (CSR_MQM_IQM_BASE + 0x268) /* the number of queue descriptor belone to CMQ host2 and cmq host3 store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_0_REG \ + (CSR_MQM_IQM_BASE + 0x26C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_1_REG \ + (CSR_MQM_IQM_BASE + 0x270) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_2_REG \ + (CSR_MQM_IQM_BASE + 0x274) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_3_REG \ + (CSR_MQM_IQM_BASE + 0x278) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_4_REG \ + (CSR_MQM_IQM_BASE + 0x27C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_5_REG \ + (CSR_MQM_IQM_BASE + 0x280) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_6_REG \ + (CSR_MQM_IQM_BASE + 0x284) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_7_REG \ + (CSR_MQM_IQM_BASE + 0x288) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_8_REG \ + (CSR_MQM_IQM_BASE + 0x28C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_9_REG \ + (CSR_MQM_IQM_BASE + 0x290) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_10_REG \ + (CSR_MQM_IQM_BASE + 0x294) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_11_REG \ + (CSR_MQM_IQM_BASE + 0x298) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_12_REG \ + (CSR_MQM_IQM_BASE + 0x29C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_13_REG \ + (CSR_MQM_IQM_BASE + 0x2A0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_14_REG \ + (CSR_MQM_IQM_BASE + 0x2A4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_15_REG \ + (CSR_MQM_IQM_BASE + 0x2A8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_16_REG \ + (CSR_MQM_IQM_BASE + 0x2AC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_17_REG \ + (CSR_MQM_IQM_BASE + 0x2B0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_18_REG \ + (CSR_MQM_IQM_BASE + 0x2B4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_19_REG \ + (CSR_MQM_IQM_BASE + 0x2B8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_20_REG \ + (CSR_MQM_IQM_BASE + 0x2BC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_21_REG \ + (CSR_MQM_IQM_BASE + 0x2C0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_22_REG \ + (CSR_MQM_IQM_BASE + 0x2C4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_23_REG \ + (CSR_MQM_IQM_BASE + 0x2C8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_24_REG \ + (CSR_MQM_IQM_BASE + 0x2CC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_25_REG \ + (CSR_MQM_IQM_BASE + 0x2D0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_26_REG \ + (CSR_MQM_IQM_BASE + 0x2D4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_27_REG \ + (CSR_MQM_IQM_BASE + 0x2D8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_28_REG \ + (CSR_MQM_IQM_BASE + 0x2DC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_29_REG \ + (CSR_MQM_IQM_BASE + 0x2E0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_30_REG \ + (CSR_MQM_IQM_BASE + 0x2E4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_31_REG \ + (CSR_MQM_IQM_BASE + 0x2E8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_ROOTX_CNT_REG \ + (CSR_MQM_IQM_BASE + 0x2EC) /* statistics of the number of root level NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NMQ_HOSTX_CNT0_REG \ + (CSR_MQM_IQM_BASE + 0x2F0) /* statistics of the number of host0 and host1 NMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NMQ_HOSTX_CNT1_REG \ + (CSR_MQM_IQM_BASE + 0x2F4) /* statistics of the number of host2 and host3 NMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NFMQ_HOSTX_CNT0_REG \ + (CSR_MQM_IQM_BASE + 0x2F8) /* statistics of the number of host0 and host1 NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NFMQ_HOSTX_CNT1_REG \ + (CSR_MQM_IQM_BASE + 0x2FC) /* statistics of the number of host2 and host3 NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_0_REG \ + (CSR_MQM_IQM_BASE + \ + 0x300) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_1_REG \ + (CSR_MQM_IQM_BASE + \ + 0x304) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_2_REG \ + (CSR_MQM_IQM_BASE + \ + 0x308) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_3_REG \ + (CSR_MQM_IQM_BASE + \ + 0x30C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_4_REG \ + (CSR_MQM_IQM_BASE + \ + 0x310) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_5_REG \ + (CSR_MQM_IQM_BASE + \ + 0x314) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_6_REG \ + (CSR_MQM_IQM_BASE + \ + 0x318) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_7_REG \ + (CSR_MQM_IQM_BASE + \ + 0x31C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_8_REG \ + (CSR_MQM_IQM_BASE + \ + 0x320) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_9_REG \ + (CSR_MQM_IQM_BASE + \ + 0x324) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_10_REG \ + (CSR_MQM_IQM_BASE + \ + 0x328) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_11_REG \ + (CSR_MQM_IQM_BASE + \ + 0x32C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_12_REG \ + (CSR_MQM_IQM_BASE + \ + 0x330) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_13_REG \ + (CSR_MQM_IQM_BASE + \ + 0x334) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_14_REG \ + (CSR_MQM_IQM_BASE + \ + 0x338) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_15_REG \ + (CSR_MQM_IQM_BASE + \ + 0x33C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_16_REG \ + (CSR_MQM_IQM_BASE + \ + 0x340) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_17_REG \ + (CSR_MQM_IQM_BASE + \ + 0x344) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_18_REG \ + (CSR_MQM_IQM_BASE + \ + 0x348) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_19_REG \ + (CSR_MQM_IQM_BASE + \ + 0x34C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_20_REG \ + (CSR_MQM_IQM_BASE + \ + 0x350) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_21_REG \ + (CSR_MQM_IQM_BASE + \ + 0x354) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_22_REG \ + (CSR_MQM_IQM_BASE + \ + 0x358) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_23_REG \ + (CSR_MQM_IQM_BASE + \ + 0x35C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_24_REG \ + (CSR_MQM_IQM_BASE + \ + 0x360) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_25_REG \ + (CSR_MQM_IQM_BASE + \ + 0x364) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_26_REG \ + (CSR_MQM_IQM_BASE + \ + 0x368) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_27_REG \ + (CSR_MQM_IQM_BASE + \ + 0x36C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_28_REG \ + (CSR_MQM_IQM_BASE + \ + 0x370) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_29_REG \ + (CSR_MQM_IQM_BASE + \ + 0x374) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_30_REG \ + (CSR_MQM_IQM_BASE + \ + 0x378) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_31_REG \ + (CSR_MQM_IQM_BASE + \ + 0x37C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_UCMQ_ROOT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0x380) /* statistics of the number of root level ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UNMQ_ROOT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0x384) /* statistics of the number of root level unmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_0_REG \ + (CSR_MQM_IQM_BASE + 0x388) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_1_REG \ + (CSR_MQM_IQM_BASE + 0x38C) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_2_REG \ + (CSR_MQM_IQM_BASE + 0x390) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_3_REG \ + (CSR_MQM_IQM_BASE + 0x394) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_4_REG \ + (CSR_MQM_IQM_BASE + 0x398) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_5_REG \ + (CSR_MQM_IQM_BASE + 0x39C) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_6_REG \ + (CSR_MQM_IQM_BASE + 0x3A0) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_7_REG \ + (CSR_MQM_IQM_BASE + 0x3A4) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_0_REG \ + (CSR_MQM_IQM_BASE + 0x3A8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_1_REG \ + (CSR_MQM_IQM_BASE + 0x3AC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_2_REG \ + (CSR_MQM_IQM_BASE + 0x3B0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_3_REG \ + (CSR_MQM_IQM_BASE + 0x3B4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_4_REG \ + (CSR_MQM_IQM_BASE + 0x3B8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_5_REG \ + (CSR_MQM_IQM_BASE + 0x3BC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_6_REG \ + (CSR_MQM_IQM_BASE + 0x3C0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_7_REG \ + (CSR_MQM_IQM_BASE + 0x3C4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_8_REG \ + (CSR_MQM_IQM_BASE + 0x3C8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_9_REG \ + (CSR_MQM_IQM_BASE + 0x3CC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_10_REG \ + (CSR_MQM_IQM_BASE + 0x3D0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_11_REG \ + (CSR_MQM_IQM_BASE + 0x3D4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_12_REG \ + (CSR_MQM_IQM_BASE + 0x3D8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_13_REG \ + (CSR_MQM_IQM_BASE + 0x3DC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_14_REG \ + (CSR_MQM_IQM_BASE + 0x3E0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_15_REG \ + (CSR_MQM_IQM_BASE + 0x3E4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_16_REG \ + (CSR_MQM_IQM_BASE + 0x3E8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_17_REG \ + (CSR_MQM_IQM_BASE + 0x3EC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_18_REG \ + (CSR_MQM_IQM_BASE + 0x3F0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_19_REG \ + (CSR_MQM_IQM_BASE + 0x3F4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_20_REG \ + (CSR_MQM_IQM_BASE + 0x3F8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_21_REG \ + (CSR_MQM_IQM_BASE + 0x3FC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_22_REG \ + (CSR_MQM_IQM_BASE + 0x400) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_23_REG \ + (CSR_MQM_IQM_BASE + 0x404) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_24_REG \ + (CSR_MQM_IQM_BASE + 0x408) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_25_REG \ + (CSR_MQM_IQM_BASE + 0x40C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_26_REG \ + (CSR_MQM_IQM_BASE + 0x410) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_27_REG \ + (CSR_MQM_IQM_BASE + 0x414) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_28_REG \ + (CSR_MQM_IQM_BASE + 0x418) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_29_REG \ + (CSR_MQM_IQM_BASE + 0x41C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_30_REG \ + (CSR_MQM_IQM_BASE + 0x420) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_31_REG \ + (CSR_MQM_IQM_BASE + 0x424) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_32_REG \ + (CSR_MQM_IQM_BASE + 0x428) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_33_REG \ + (CSR_MQM_IQM_BASE + 0x42C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_34_REG \ + (CSR_MQM_IQM_BASE + 0x430) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_35_REG \ + (CSR_MQM_IQM_BASE + 0x434) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_36_REG \ + (CSR_MQM_IQM_BASE + 0x438) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_37_REG \ + (CSR_MQM_IQM_BASE + 0x43C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_38_REG \ + (CSR_MQM_IQM_BASE + 0x440) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_39_REG \ + (CSR_MQM_IQM_BASE + 0x444) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_40_REG \ + (CSR_MQM_IQM_BASE + 0x448) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_41_REG \ + (CSR_MQM_IQM_BASE + 0x44C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_42_REG \ + (CSR_MQM_IQM_BASE + 0x450) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_43_REG \ + (CSR_MQM_IQM_BASE + 0x454) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_44_REG \ + (CSR_MQM_IQM_BASE + 0x458) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_45_REG \ + (CSR_MQM_IQM_BASE + 0x45C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_46_REG \ + (CSR_MQM_IQM_BASE + 0x460) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_47_REG \ + (CSR_MQM_IQM_BASE + 0x464) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_48_REG \ + (CSR_MQM_IQM_BASE + 0x468) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_49_REG \ + (CSR_MQM_IQM_BASE + 0x46C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_50_REG \ + (CSR_MQM_IQM_BASE + 0x470) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_51_REG \ + (CSR_MQM_IQM_BASE + 0x474) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_52_REG \ + (CSR_MQM_IQM_BASE + 0x478) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_53_REG \ + (CSR_MQM_IQM_BASE + 0x47C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_54_REG \ + (CSR_MQM_IQM_BASE + 0x480) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_55_REG \ + (CSR_MQM_IQM_BASE + 0x484) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_56_REG \ + (CSR_MQM_IQM_BASE + 0x488) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_57_REG \ + (CSR_MQM_IQM_BASE + 0x48C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_58_REG \ + (CSR_MQM_IQM_BASE + 0x490) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_59_REG \ + (CSR_MQM_IQM_BASE + 0x494) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_60_REG \ + (CSR_MQM_IQM_BASE + 0x498) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_61_REG \ + (CSR_MQM_IQM_BASE + 0x49C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_62_REG \ + (CSR_MQM_IQM_BASE + 0x4A0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_63_REG \ + (CSR_MQM_IQM_BASE + 0x4A4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_EQM_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4A8) /* THE STATUS OF EQM EN_QUEUE FIFO */ +#define CSR_MQM_IQM_DEQC_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4AC) /* THE STATUS OF DEQC EN_QUEUE FIFO */ +#define CSR_MQM_IQM_IQM_ENQC_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4B0) /* THE STATUS OF ENQC EN_QUEUE FIFO */ +#define CSR_MQM_IQM_IQM_ENQC_SOC_ENQ_FIFO_STATUS_REG \ + (CSR_MQM_IQM_BASE + 0x4B4) /* the status of enqc soc enq_queue fifo */ +#define CSR_MQM_IQM_IQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_REG \ + (CSR_MQM_IQM_BASE + 0x4B8) /* iqm cpi sge credit comp fifo status */ +#define CSR_MQM_IQM_IQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_REG \ + (CSR_MQM_IQM_BASE + 0x4BC) /* iqm cpi data credit comp fifo status */ +#define CSR_MQM_IQM_IQM_SM_CRDT_COMP_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C0) /* sm credit comp fifo status */ +#define CSR_MQM_IQM_IQM_SM_OUT_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C4) /* sm out fifo status */ +#define CSR_MQM_IQM_IQM_QU_CRDT_COMP_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C8) /* iqm qu credit comp fifo status */ +#define CSR_MQM_IQM_ICLL_FREE_CNT_REG (CSR_MQM_IQM_BASE + 0x4CC) /* report the free resource in IQM */ +#define CSR_MQM_IQM_IQM_SM_TOTAL_CAM_CNT_REG (CSR_MQM_IQM_BASE + 0x4D0) /* iqm sm total cam counter */ +#define CSR_MQM_IQM_IQM_SM_HOST_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4D4) /* iqm sm host credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_RR_SGE_CRDT_BP_REG \ + (CSR_MQM_IQM_BASE + 0x4D8) /* iqm sm ep host dp rr sge credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_RR_DAT_CRDT_BP_REG \ + (CSR_MQM_IQM_BASE + 0x4DC) /* iqm sm ep host dp rr data credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_SGE_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E0) /* iqm sm ep host dp sge credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_DAT_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E4) /* iqm sm ep host dp data credit bp \ + */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_CP_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E8) /* iqm sm ep host cp rr credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_SOC_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4EC) /* iqm sm ep soc dp/cp rr credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_CP_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4F0) /* iqm sm ep host cp credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_SOC_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4F4) /* iqm sm ep soc dp/cp credit bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_CRDT_BP0_REG (CSR_MQM_IQM_BASE + 0x4F8) /* iqm qu ep dp credit resource 0-31 bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_CRDT_BP1_REG (CSR_MQM_IQM_BASE + 0x4FC) /* iqm qu ep dp credit resource 32-63 bp */ +#define CSR_MQM_IQM_IQM_QU_EP_CP_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x500) /* iqm qu ep cp credit bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_RR_CRDT_BP0_REG \ + (CSR_MQM_IQM_BASE + 0x504) /* iqm qu ep dp credit resource 0-31 rr bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_RR_CRDT_BP1_REG \ + (CSR_MQM_IQM_BASE + 0x508) /* iqm qu ep dp credit resource 32-63 rr bp */ +#define CSR_MQM_IQM_IQM_QU_EP_CP_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x50C) /* iqm qu ep cp credit rr bp */ +#define CSR_MQM_IQM_IQM_FLUSH_ICLL_CAM_DONE_REG \ + (CSR_MQM_IQM_BASE + 0x510) /* iqm flush soc and host mq done and cam flush done */ +#define CSR_MQM_IQM_IQM_AGING_NMQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB38) /* times of iqm nmq hardware aging nmq */ +#define CSR_MQM_IQM_IQM_AGING_NFMQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB3C) /* times of iqm nfmq hardware aging nmq */ +#define CSR_MQM_IQM_IQM_AGING_DISCARD_CNT_REG (CSR_MQM_IQM_BASE + 0xB40) /* iqm aging discard queue descriptor cnt */ +#define CSR_MQM_IQM_IQM_TO_EQM_QD_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB44) /* iqm aging or designated deq to eqm queue descriptor cnt */ +#define CSR_MQM_IQM_IQM_DEQ_SM_CNT_REG (CSR_MQM_IQM_BASE + 0xB48) /* statistics of the nunber de-queue to sm */ +#define CSR_MQM_IQM_IQM_DEQ_QU_CNT_REG (CSR_MQM_IQM_BASE + 0xB4C) /* statistics of the nunber de-queue to qu */ +#define CSR_MQM_IQM_MSC_IQM_DEQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB50) /* the number of de-queue operation that msc send to iqm */ +#define CSR_MQM_IQM_IQM_NMQNFMQ_ENQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB54) /* the number of iqm en-queue operation for nmq and nfmq */ +#define CSR_MQM_IQM_IQM_NMQNFMQ_DEQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB58) /* the number of iqm de-queue operation for nmq and nfmq */ +#define CSR_MQM_IQM_IQM_CMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB5C) /* the number of iqm en-queue operation for cmq */ +#define CSR_MQM_IQM_IQM_CMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB60) /* the number of iqm de-queue operation for cmq */ +#define CSR_MQM_IQM_SOC_MSC_IQM_DEQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB64) /* the number of de-queue operation that soc msc send to iqm */ +#define CSR_MQM_IQM_IQM_UNMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB68) /* the number of iqm en-queue operation for unmq \ + */ +#define CSR_MQM_IQM_IQM_UNMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB6C) /* the number of iqm de-queue operation for unmq \ + */ +#define CSR_MQM_IQM_IQM_UCMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB70) /* the number of iqm en-queue operation for ucmq \ + */ +#define CSR_MQM_IQM_IQM_UCMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB74) /* the number of iqm de-queue operation for ucmq \ + */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_HOST_SGE_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB78) /* iqm rx cpi comp host sge credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_HOST_DAT_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB7C) /* iqm rx cpi comp host data credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_DP_SGE_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB80) /* iqm rx cpi comp ep dp sge credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_CP_SGE_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB84) /* iqm rx cpi comp ep cp sge credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_DP_DAT_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB88) /* iqm rx cpi comp ep dp data credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_CP_DAT_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB8C) /* iqm rx cpi comp ep cp data credit cnt */ +#define CSR_MQM_IQM_IQM_RX_QU_COMP_EP_DP_CRDT_CNT_REG (CSR_MQM_IQM_BASE + 0xB90) /* iqm rx qu comp ep dp credit cnt */ +#define CSR_MQM_IQM_IQM_RX_QU_COMP_EP_CP_CRDT_CNT_REG (CSR_MQM_IQM_BASE + 0xB94) /* iqm rx qu comp ep cp credit cnt */ +#define CSR_MQM_IQM_IQM_ECC_1BIT_ERR_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB98) /* statistics counter of IQM memory ECC 1bit ERR */ +#define CSR_MQM_IQM_IQM_ECC_2BIT_ERR_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB9C) /* statistics counter of IQM memory ECC 2bit ERR */ + +/* MQM_EQM Base address of Module's Register */ +#define CSR_MQM_EQM_BASE (0xA000) + +/* **************************************************************************** */ +/* MQM_EQM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_EQM_EQM_RW_RSV0_REG (CSR_MQM_EQM_BASE + 0x0) /* EQM rw reserved 0 */ +#define CSR_MQM_EQM_EQM_RW_RSV1_REG (CSR_MQM_EQM_BASE + 0x4) /* EQM rw reserved 1 */ +#define CSR_MQM_EQM_EQM_RW_RSV2_REG (CSR_MQM_EQM_BASE + 0x8) /* EQM rw reserved 2 */ +#define CSR_MQM_EQM_EQM_RW_RSV3_REG (CSR_MQM_EQM_BASE + 0xC) /* EQM rw reserved 3 */ +#define CSR_MQM_EQM_EQM_INDRECT_CTRL_REG (CSR_MQM_EQM_BASE + 0x10) /* EQM Indirect access ctrl Register。 */ +#define CSR_MQM_EQM_EQM_INDRECT_TIMEOUT_REG (CSR_MQM_EQM_BASE + 0x14) /* EQM Indirect Access Timeout Register。 */ +#define CSR_MQM_EQM_EQM_INDRECT_DATA_REG (CSR_MQM_EQM_BASE + 0x18) /* EQM Indirect Access Data Register. */ +#define CSR_MQM_EQM_EQM_ECQM_BP_BYPASS_REG (CSR_MQM_EQM_BASE + 0x1C) /* EQM ECQM_HFIFO Backpresssure Bypass */ +#define CSR_MQM_EQM_EQM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_EQM_BASE + 0x20) /* EQM RAM ECC Bypass控制寄存器 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_EQM_BASE + 0x24) /* EQM RAM ctrl bus cfg reg0 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_EQM_BASE + 0x28) /* EQM RAM ctrl bus cfg reg1 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_EQM_BASE + 0x2C) /* EQM RAM ctrl bus cfg reg2 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_EQM_BASE + 0x30) /* EQM RAM ctrl bus cfg reg3 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_EQM_BASE + 0x34) /* EQM RAM ctrl bus cfg reg4 */ +#define CSR_MQM_EQM_EQM_INT_VECTOR_REG (CSR_MQM_EQM_BASE + 0x40) /* EQM Internal ERR Interrupt Vector Register. */ +#define CSR_MQM_EQM_EQM_INT_REG (CSR_MQM_EQM_BASE + 0x44) /* EQM Internal ERR Interrupt Register. */ +#define CSR_MQM_EQM_EQM_INT_EN_REG (CSR_MQM_EQM_BASE + 0x48) /* EQM Internal ERR Interrupt Mask Register. */ +#define CSR_MQM_EQM_EQM_MEM_ECC_REQ_REG (CSR_MQM_EQM_BASE + 0x4C) /* EQM memory ecc insert request Register */ +#define CSR_MQM_EQM_EQM_MEM_1BIT_ERR_REG (CSR_MQM_EQM_BASE + 0x50) /* EQM 1Bit ECC Check Err Register. */ +#define CSR_MQM_EQM_EQM_MEM_2BIT_ERR_REG (CSR_MQM_EQM_BASE + 0x54) /* EQM 2Bit ECC Check Err Register. */ +#define CSR_MQM_EQM_EQM_QL_DEQ_EMPTY_INT_REG \ + (CSR_MQM_EQM_BASE + 0x58) /* EQM Queue Deq Interrupt Register When Queue Empty */ +#define CSR_MQM_EQM_EQM_CLL_FAP_EXHAUSTED_INT_REG \ + (CSR_MQM_EQM_BASE + 0x5C) /* EQM CHUNK Link List Interrupt Register When Free Addr Pool Resource Exhausted。 */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT0_REG \ + (CSR_MQM_EQM_BASE + 0x60) /* EQM FIFO Write Interrupt Register When Full */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT0_EN_REG \ + (CSR_MQM_EQM_BASE + 0x64) /* EQM FIFO Write Interrupt Mask Register When Full */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT1_REG \ + (CSR_MQM_EQM_BASE + 0x68) /* EQM FIFO Write Interrupt Register Whenable Full */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT1_EN_REG \ + (CSR_MQM_EQM_BASE + 0x6C) /* EQM FIFO Write Interrupt Mask Register When Full */ +#define CSR_MQM_EQM_EQM_FIFO_RD_UNDEL_INT_REG \ + (CSR_MQM_EQM_BASE + 0x70) /* EQM FIFO Read Interrupt Register When Empty */ +#define CSR_MQM_EQM_EQM_FIFO_RD_UNDEL_INT_EN_REG \ + (CSR_MQM_EQM_BASE + 0x74) /* EQM FIFO Read Interrupt Mask Register When Empty */ +#define CSR_MQM_EQM_EQM_RING_DFX_ERR_INT_REG \ + (CSR_MQM_EQM_BASE + 0x78) /* EQM Receive E0 Interrupt Register From RING Interface */ +#define CSR_MQM_EQM_EQM_BRMATT_RD_INT_REG (CSR_MQM_EQM_BASE + 0x7C) /* EQM Read ATT Error Interrupt from BRM */ +#define CSR_MQM_EQM_EQM_RING_DFX_ERR_INT1_REG \ + (CSR_MQM_EQM_BASE + 0x80) /* EQM Receive E1 Interrupt Register From RING Interface */ +#define CSR_MQM_EQM_EQM_UNCRT_INT_EN_REG (CSR_MQM_EQM_BASE + 0x84) /* enqc uncorrect int en */ +#define CSR_MQM_EQM_EQM_DWQ_RSC_DEP_CFG_REG \ + (CSR_MQM_EQM_BASE + 0x800) /* EQM DWQ Space Addr Pool Depth config Register. */ +#define CSR_MQM_EQM_EQM_PACK_CHANNEL_CFG_REG (CSR_MQM_EQM_BASE + 0x804) /* EQM Packing Channel Config Register. */ +#define CSR_MQM_EQM_EQM_DB_STORE_SPACE_SEL_REG (CSR_MQM_EQM_BASE + 0x808) /* DB溢出空间选择 */ +#define CSR_MQM_EQM_EQM_HOST_CHUNK_NUM_CFG0_REG \ + (CSR_MQM_EQM_BASE + 0x80C) /* EQM HOST0~1 chunk number Config Register. */ +#define CSR_MQM_EQM_EQM_HOST_CHUNK_NUM_CFG1_REG \ + (CSR_MQM_EQM_BASE + 0x810) /* EQM HOST2~3 chunk number Config Register. */ +#define CSR_MQM_EQM_EQM_PAGE_SIZE_CFG_REG (CSR_MQM_EQM_BASE + 0x814) /* EQM HOST MEM page size Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_0_REG (CSR_MQM_EQM_BASE + 0x820) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_1_REG (CSR_MQM_EQM_BASE + 0x824) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_2_REG (CSR_MQM_EQM_BASE + 0x828) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_3_REG (CSR_MQM_EQM_BASE + 0x82C) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOST_SEARCH_GPA_BADDR_CFG0_REG \ + (CSR_MQM_EQM_BASE + 0x830) /* EQM HOST search the BRM(10K GPA) Base Address Config Register0 */ +#define CSR_MQM_EQM_EQM_HOST_SEARCH_GPA_BADDR_CFG1_REG \ + (CSR_MQM_EQM_BASE + 0x834) /* EQM HOST search the BRM(10K GPA) Base Address Config Register1 */ +#define CSR_MQM_EQM_EQM_DMA_OUTSTD_NUM_REG \ + (CSR_MQM_EQM_BASE + 0x838) /* EQM Outstanding config Register for every Host */ +#define CSR_MQM_EQM_EQM_HOST_DMA_OUTSTD_NUM_REG \ + (CSR_MQM_EQM_BASE + 0x83C) /* EQM Outstanding config Register for every Host */ +#define CSR_MQM_EQM_EQM_FIFO_GAP_CFG_REG (CSR_MQM_EQM_BASE + 0x840) /* EQM FIFO Back Press Threshold config register. \ + */ +#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG0_REG \ + (CSR_MQM_EQM_BASE + 0x844) /* EQM DWQ Interface Back Press Threshold config Register. */ +#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG1_REG \ + (CSR_MQM_EQM_BASE + 0x848) /* EQM DWQ Interface Back Press Threshold config Register. */ +#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG2_REG \ + (CSR_MQM_EQM_BASE + 0x84C) /* EQM DWQ Interface Back Press Threshold config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_0_REG \ + (CSR_MQM_EQM_BASE + 0x850) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_1_REG \ + (CSR_MQM_EQM_BASE + 0x854) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_2_REG \ + (CSR_MQM_EQM_BASE + 0x858) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_3_REG \ + (CSR_MQM_EQM_BASE + 0x85C) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOST_FIFO_DEPTH_CFG_REG (CSR_MQM_EQM_BASE + 0x860) /* EQM Host FIFO Depth Config Register */ +#define CSR_MQM_EQM_EQM_DMARD_FIFO_BP_TH_REG \ + (CSR_MQM_EQM_BASE + 0x864) /* EQM DMA Read fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMARD_FIFO_DEPTH0_REG \ + (CSR_MQM_EQM_BASE + 0x868) /* EQM DMA Read fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMARD_FIFO_DEPTH1_REG \ + (CSR_MQM_EQM_BASE + 0x86C) /* EQM DMA Read fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMAWR_FIFO_DEPTH0_REG \ + (CSR_MQM_EQM_BASE + 0x870) /* EQM DMA Write fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMAWR_FIFO_DEPTH1_REG \ + (CSR_MQM_EQM_BASE + 0x874) /* EQM DMA Write fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_DEPTH0_REG \ + (CSR_MQM_EQM_BASE + 0x878) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_DEPTH1_REG \ + (CSR_MQM_EQM_BASE + 0x87C) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_DMACMD_RDFIFO_TH_REG (CSR_MQM_EQM_BASE + 0x880) /* EQM HOST0 DMA Channel FIFO Config Register \ + */ +#define CSR_MQM_EQM_EQM_DMACMD_WRFIFO_TH0_REG \ + (CSR_MQM_EQM_BASE + 0x884) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_DMACMD_WRFIFO_TH1_REG \ + (CSR_MQM_EQM_BASE + 0x888) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_OUTSTD_FIFO_ALEMPTY_TH_REG (CSR_MQM_EQM_BASE + 0x88C) /* outstand fifo 将空水线 */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_AF_GAP0_REG (CSR_MQM_EQM_BASE + 0x890) /* EQM Host0 Host1 DMA CMD FIFO ALFUL GAP \ + */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_AF_GAP1_REG (CSR_MQM_EQM_BASE + 0x894) /* EQM Host2 Host3 DMA CMD FIFO ALFUL GAP \ + */ +#define CSR_MQM_EQM_EQM_DMAWR_FIFO_BP_GAP_REG \ + (CSR_MQM_EQM_BASE + 0x898) /* EQM DMA Write fifo Backpress gap threshold config register */ +#define CSR_MQM_EQM_EQM_INNER_BP_STATUS0_REG (CSR_MQM_EQM_BASE + 0x1000) /* EQM Inner backpress status Register0 */ +#define CSR_MQM_EQM_EQM_INNER_BP_STATUS1_REG (CSR_MQM_EQM_BASE + 0x1004) /* EQM Inner backpress status Register1 */ +#define CSR_MQM_EQM_EQM_FIFO_STATUS0_REG \ + (CSR_MQM_EQM_BASE + 0x1008) /* EQM Internal FIFO DFX Register.(including full、empty) */ +#define CSR_MQM_EQM_EQM_FIFO_STATUS1_REG \ + (CSR_MQM_EQM_BASE + 0x100C) /* EQM Internal FIFO DFX Register.(including full、empty) */ +#define CSR_MQM_EQM_EQM_RING_DFX_ERR_CNT_REG \ + (CSR_MQM_EQM_BASE + 0x1800) /* EQM Receive E0/E1 Interrupt Count Register. */ +#define CSR_MQM_EQM_EQM_SM_OVFL_CNT_REG (CSR_MQM_EQM_BASE + 0x1804) /* The redundant DoorBell number overflow form SM \ + */ +#define CSR_MQM_EQM_EQM_DWQ_FREE_ADDR_CNT_REG (CSR_MQM_EQM_BASE + 0x1808) /* EQM DWQ Free Addr Count Register. */ +#define CSR_MQM_EQM_EQM_DWQ_LIST_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x180C) /* DWQ LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_0_REG (CSR_MQM_EQM_BASE + 0x1810) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_1_REG (CSR_MQM_EQM_BASE + 0x1814) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_2_REG (CSR_MQM_EQM_BASE + 0x1818) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_3_REG (CSR_MQM_EQM_BASE + 0x181C) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1820) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1824) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1828) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x182C) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_NMQ_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1830) /* EQM NMQ DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_0_REG (CSR_MQM_EQM_BASE + 0x1840) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_1_REG (CSR_MQM_EQM_BASE + 0x1844) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_2_REG (CSR_MQM_EQM_BASE + 0x1848) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_3_REG (CSR_MQM_EQM_BASE + 0x184C) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NFMQ_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1850) /* EQM NFMQ DB Count Register. */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_0_REG (CSR_MQM_EQM_BASE + 0x1860) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_1_REG (CSR_MQM_EQM_BASE + 0x1864) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_2_REG (CSR_MQM_EQM_BASE + 0x1868) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_3_REG (CSR_MQM_EQM_BASE + 0x186C) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1870) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1874) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1878) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x187C) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_DWQ_TILE_CNT_REG (CSR_MQM_EQM_BASE + 0x1880) /* EQM DWQ Space Count Register For TILE. */ +#define CSR_MQM_EQM_EQM_DWQ_SM_CNT_REG (CSR_MQM_EQM_BASE + 0x1884) /* EQM DWQ Space Count Register For Small-Memory. \ + */ +#define CSR_MQM_EQM_EQM_DWQ_QU_CNT_REG (CSR_MQM_EQM_BASE + 0x1888) /* EQM DWQ Space Count Register For QU. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_CNT_REG (CSR_MQM_EQM_BASE + 0x188C) /* EQM DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1890) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1894) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1898) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x189C) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_0_REG (CSR_MQM_EQM_BASE + 0x18A0) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_1_REG (CSR_MQM_EQM_BASE + 0x18A4) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_2_REG (CSR_MQM_EQM_BASE + 0x18A8) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_3_REG (CSR_MQM_EQM_BASE + 0x18AC) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_0_REG (CSR_MQM_EQM_BASE + 0x18B0) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_1_REG (CSR_MQM_EQM_BASE + 0x18B4) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_2_REG (CSR_MQM_EQM_BASE + 0x18B8) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_3_REG (CSR_MQM_EQM_BASE + 0x18BC) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18C0) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18C4) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18C8) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18CC) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18D0) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18D4) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18D8) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18DC) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18E0) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18E4) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18E8) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18EC) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18F0) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18F4) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18F8) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18FC) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1900) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1904) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1908) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x190C) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1910) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1914) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1918) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x191C) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_IQM_SEND_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1920) /* EQM DB Count that be sended to IQM. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1930) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1934) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1938) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x193C) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_DMA_OUTSTAND_DFX0_REG \ + (CSR_MQM_EQM_BASE + 0x1940) /* EQM Outstand Count Register for DMA Operate. */ +#define CSR_MQM_EQM_EQM_DMA_OUTSTAND_DFX1_REG \ + (CSR_MQM_EQM_BASE + 0x1944) /* EQM Host Outstand Count Register for DMA Operate. */ +#define CSR_MQM_EQM_EQM_ECC_1BIT_ERR_CNT_REG (CSR_MQM_EQM_BASE + 0x1948) /* EQM Memory ECC 1bit count */ +#define CSR_MQM_EQM_EQM_ECC_2BIT_ERR_CNT_REG (CSR_MQM_EQM_BASE + 0x194C) /* EQM Memory ECC 2bit count */ + +/* MQM_MSC Base address of Module's Register */ +#define CSR_MQM_MSC_BASE (0xC000) + +/* **************************************************************************** */ +/* MQM_MSC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_MSC_MSC_RW_RSV0_REG (CSR_MQM_MSC_BASE + 0x0) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_RW_RSV1_REG (CSR_MQM_MSC_BASE + 0x4) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_RW_RSV2_REG (CSR_MQM_MSC_BASE + 0x8) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_RW_RSV3_REG (CSR_MQM_MSC_BASE + 0xC) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_INDRECT_CTRL_REG (CSR_MQM_MSC_BASE + 0x10) /* Indirect access ctrl Register。 */ +#define CSR_MQM_MSC_MSC_INDRECT_TIMEOUT_REG (CSR_MQM_MSC_BASE + 0x14) /* Indirect Access Timeout Register。 */ +#define CSR_MQM_MSC_MSC_INDRECT_DATA_0_REG (CSR_MQM_MSC_BASE + 0x18) /* Indirect Access Data Register BIT63_32 */ +#define CSR_MQM_MSC_MSC_INDRECT_DATA_1_REG (CSR_MQM_MSC_BASE + 0x1C) /* Indirect Access Data Register BIT31_0 */ +#define CSR_MQM_MSC_MSC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_MSC_BASE + 0x20) /* RAM ECC BYPASS控制寄存器 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_MSC_BASE + 0x24) /* RAM CTRL_BUS寄存器0 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_MSC_BASE + 0x28) /* RAM CTRL_BUS寄存器1 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_MSC_BASE + 0x2C) /* RAM CTRL_BUS寄存器2 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_MSC_BASE + 0x30) /* RAM CTRL_BUS寄存器3 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_MSC_BASE + 0x34) /* RAM CTRL_BUS寄存器4 */ +#define CSR_MQM_MSC_MSC_INT_VECTOR_REG (CSR_MQM_MSC_BASE + 0x100) /* MSC ERROR INT VECTOR */ +#define CSR_MQM_MSC_MSC_INT_REG (CSR_MQM_MSC_BASE + 0x104) /* MSC ERROR INT */ +#define CSR_MQM_MSC_MSC_INT_EN_REG (CSR_MQM_MSC_BASE + 0x108) /* MSC ERROR ENABLE */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ0_REG (CSR_MQM_MSC_BASE + 0x10C) /* Msc mem Error Request register0. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ1_REG (CSR_MQM_MSC_BASE + 0x110) /* Msc mem Error Request registe1. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ2_REG (CSR_MQM_MSC_BASE + 0x114) /* Msc mem Error Request registe2. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ3_REG (CSR_MQM_MSC_BASE + 0x118) /* Msc mem Error Request registe3. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ4_REG (CSR_MQM_MSC_BASE + 0x11C) /* Msc mem Error Request registe4. */ +#define CSR_MQM_MSC_MSC_ECC_ONE_BIT_INT_REG (CSR_MQM_MSC_BASE + 0x120) /* RAM ECC ONE BIT ERROR */ +#define CSR_MQM_MSC_MSC_ECC_TWO_BIT_INT_REG (CSR_MQM_MSC_BASE + 0x124) /* RAM ECC TWO BIT ERROR */ +#define CSR_MQM_MSC_MSC_MQ_BIND_INT_REG (CSR_MQM_MSC_BASE + 0x128) /* MQ MAPPING CONFIG ERROR */ +#define CSR_MQM_MSC_MSC_VNIC_SPCNT_INF_INT_REG (CSR_MQM_MSC_BASE + 0x12C) /* VF SPCNT Interface ERROR */ +#define CSR_MQM_MSC_MSC_VNIC_SPCNT_CAL_INT_REG (CSR_MQM_MSC_BASE + 0x130) /* VF SPCNT Calculation ERROR */ +#define CSR_MQM_MSC_MSC_SOCEP_SPCNT_INF_INT_REG (CSR_MQM_MSC_BASE + 0x134) /* SOCEP SPCNT Interface ERROR */ +#define CSR_MQM_MSC_MSC_SOCEP_SPCNT_CAL_INT_REG (CSR_MQM_MSC_BASE + 0x138) /* SOCEP SPCNT Calculation ERROR */ +#define CSR_MQM_MSC_MSC_FIFO_INT0_REG (CSR_MQM_MSC_BASE + 0x150) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT0_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x154) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT1_REG (CSR_MQM_MSC_BASE + 0x158) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT1_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x15C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT2_REG (CSR_MQM_MSC_BASE + 0x160) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT2_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x164) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT3_REG (CSR_MQM_MSC_BASE + 0x168) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT3_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x16C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT4_REG (CSR_MQM_MSC_BASE + 0x170) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT4_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x174) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT5_REG (CSR_MQM_MSC_BASE + 0x178) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT5_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x17C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT6_REG (CSR_MQM_MSC_BASE + 0x180) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT6_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x184) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT7_REG (CSR_MQM_MSC_BASE + 0x188) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT7_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x18C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_BP_DELAY_CNT_REG (CSR_MQM_MSC_BASE + 0x200) /* MSC EP and Cos backpress delay cnt */ +#define CSR_MQM_MSC_MSC_VF_SP_CNT_EN_REG (CSR_MQM_MSC_BASE + 0x204) /* MSC VF SP CNT EN */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_NS_STF_REG (CSR_MQM_MSC_BASE + 0x250) /* Normal Service pre-subtract the pktlen */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_NS_STL_REG (CSR_MQM_MSC_BASE + 0x254) /* Normal Service pre-subtract the pktlen */ +#define CSR_MQM_MSC_CMQ_PRESUB_PKTLEN_CS_REG (CSR_MQM_MSC_BASE + 0x258) /* CMQ pre-subtract the pktlen */ +#define CSR_MQM_MSC_NFMQ_PRESUB_PKTLEN_CS_REG (CSR_MQM_MSC_BASE + 0x25C) /* NFMQ pre-subtract the pktlen */ +#define CSR_MQM_MSC_PRESUB_PKTNUM_REG (CSR_MQM_MSC_BASE + 0x260) /* MSC pre-subtract the pktnum */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_SOCNMQ_REG \ + (CSR_MQM_MSC_BASE + 0x264) /* Normal Service pre-subtract the pktlen For SOCMSC */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_SOCCMQ_REG \ + (CSR_MQM_MSC_BASE + 0x268) /* Command Service pre-subtract the pktlen For SOCMSC */ +#define CSR_MQM_MSC_PRESUB_PKTNUM_SOC_REG (CSR_MQM_MSC_BASE + 0x26C) /* MSC pre-subtract the pktnum for SOCMSC */ +#define CSR_MQM_MSC_MSC_PPS_SHAPER_CFG_PKTLEN_REG (CSR_MQM_MSC_BASE + 0x270) /* MSC Shaper Config Pktlen */ +#define CSR_MQM_MSC_MSC_ROOT_CRR_WEIGHT_CFG_REG (CSR_MQM_MSC_BASE + 0x274) /* MSC ROOT CRR WEIGHT Config */ +#define CSR_MQM_MSC_SOCMSC_ROOT_SCH_WGT_CFG_REG (CSR_MQM_MSC_BASE + 0x278) /* SOC MSC ROOT SCH Weight Config */ +#define CSR_MQM_MSC_WEIGHT_NS_OFFSET_REG (CSR_MQM_MSC_BASE + 0x27C) /* Normal queue weight offset */ +#define CSR_MQM_MSC_WEIGHT_CS_OFFSET_REG (CSR_MQM_MSC_BASE + 0x280) /* Command queue weight offset */ +#define CSR_MQM_MSC_WEIGHT_MSCSOC_OFFSET_REG (CSR_MQM_MSC_BASE + 0x284) /* SOC MSCl queue weight offset */ +#define CSR_MQM_MSC_HOST_WEIGHT_NS_REG (CSR_MQM_MSC_BASE + 0x288) /* Normal MQ host weight */ +#define CSR_MQM_MSC_HOST_WEIGHT_CS_REG (CSR_MQM_MSC_BASE + 0x28C) /* CMQ Host Node Weight Configuration Table */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_0_REG (CSR_MQM_MSC_BASE + 0x2F0) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_1_REG (CSR_MQM_MSC_BASE + 0x2F4) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_2_REG (CSR_MQM_MSC_BASE + 0x2F8) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_3_REG (CSR_MQM_MSC_BASE + 0x2FC) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_0_REG (CSR_MQM_MSC_BASE + 0x300) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_1_REG (CSR_MQM_MSC_BASE + 0x304) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_2_REG (CSR_MQM_MSC_BASE + 0x308) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_3_REG (CSR_MQM_MSC_BASE + 0x30C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_4_REG (CSR_MQM_MSC_BASE + 0x310) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_5_REG (CSR_MQM_MSC_BASE + 0x314) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_6_REG (CSR_MQM_MSC_BASE + 0x318) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_7_REG (CSR_MQM_MSC_BASE + 0x31C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_8_REG (CSR_MQM_MSC_BASE + 0x320) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_9_REG (CSR_MQM_MSC_BASE + 0x324) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_10_REG (CSR_MQM_MSC_BASE + 0x328) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_11_REG (CSR_MQM_MSC_BASE + 0x32C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_12_REG (CSR_MQM_MSC_BASE + 0x330) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_13_REG (CSR_MQM_MSC_BASE + 0x334) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_14_REG (CSR_MQM_MSC_BASE + 0x338) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_15_REG (CSR_MQM_MSC_BASE + 0x33C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_16_REG (CSR_MQM_MSC_BASE + 0x340) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_17_REG (CSR_MQM_MSC_BASE + 0x344) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_18_REG (CSR_MQM_MSC_BASE + 0x348) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_19_REG (CSR_MQM_MSC_BASE + 0x34C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_20_REG (CSR_MQM_MSC_BASE + 0x350) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_21_REG (CSR_MQM_MSC_BASE + 0x354) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_22_REG (CSR_MQM_MSC_BASE + 0x358) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_23_REG (CSR_MQM_MSC_BASE + 0x35C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_24_REG (CSR_MQM_MSC_BASE + 0x360) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_25_REG (CSR_MQM_MSC_BASE + 0x364) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_26_REG (CSR_MQM_MSC_BASE + 0x368) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_27_REG (CSR_MQM_MSC_BASE + 0x36C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_28_REG (CSR_MQM_MSC_BASE + 0x370) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_29_REG (CSR_MQM_MSC_BASE + 0x374) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_30_REG (CSR_MQM_MSC_BASE + 0x378) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_31_REG (CSR_MQM_MSC_BASE + 0x37C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_0_REG (CSR_MQM_MSC_BASE + 0x380) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_1_REG (CSR_MQM_MSC_BASE + 0x384) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_2_REG (CSR_MQM_MSC_BASE + 0x388) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_3_REG (CSR_MQM_MSC_BASE + 0x38C) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_4_REG (CSR_MQM_MSC_BASE + 0x390) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_5_REG (CSR_MQM_MSC_BASE + 0x394) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_6_REG (CSR_MQM_MSC_BASE + 0x398) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_7_REG (CSR_MQM_MSC_BASE + 0x39C) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_8_REG (CSR_MQM_MSC_BASE + 0x3A0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_9_REG (CSR_MQM_MSC_BASE + 0x3A4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_10_REG (CSR_MQM_MSC_BASE + 0x3A8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_11_REG (CSR_MQM_MSC_BASE + 0x3AC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_12_REG (CSR_MQM_MSC_BASE + 0x3B0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_13_REG (CSR_MQM_MSC_BASE + 0x3B4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_14_REG (CSR_MQM_MSC_BASE + 0x3B8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_15_REG (CSR_MQM_MSC_BASE + 0x3BC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_16_REG (CSR_MQM_MSC_BASE + 0x3C0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_17_REG (CSR_MQM_MSC_BASE + 0x3C4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_18_REG (CSR_MQM_MSC_BASE + 0x3C8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_19_REG (CSR_MQM_MSC_BASE + 0x3CC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_20_REG (CSR_MQM_MSC_BASE + 0x3D0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_21_REG (CSR_MQM_MSC_BASE + 0x3D4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_22_REG (CSR_MQM_MSC_BASE + 0x3D8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_23_REG (CSR_MQM_MSC_BASE + 0x3DC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_24_REG (CSR_MQM_MSC_BASE + 0x3E0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_25_REG (CSR_MQM_MSC_BASE + 0x3E4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_26_REG (CSR_MQM_MSC_BASE + 0x3E8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_27_REG (CSR_MQM_MSC_BASE + 0x3EC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_28_REG (CSR_MQM_MSC_BASE + 0x3F0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_29_REG (CSR_MQM_MSC_BASE + 0x3F4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_30_REG (CSR_MQM_MSC_BASE + 0x3F8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_31_REG (CSR_MQM_MSC_BASE + 0x3FC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x400) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x404) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x408) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x40C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x410) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x414) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x418) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x41C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x420) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x424) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x428) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x42C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x430) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x434) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x438) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x43C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x440) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x444) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x448) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x44C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x450) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x454) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x458) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x45C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x460) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x464) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x468) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x46C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0x470) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0x474) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0x478) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0x47C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_0_REG (CSR_MQM_MSC_BASE + 0x500) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_1_REG (CSR_MQM_MSC_BASE + 0x504) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_2_REG (CSR_MQM_MSC_BASE + 0x508) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_3_REG (CSR_MQM_MSC_BASE + 0x50C) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_4_REG (CSR_MQM_MSC_BASE + 0x510) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_5_REG (CSR_MQM_MSC_BASE + 0x514) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_6_REG (CSR_MQM_MSC_BASE + 0x518) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_7_REG (CSR_MQM_MSC_BASE + 0x51C) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_8_REG (CSR_MQM_MSC_BASE + 0x520) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_9_REG (CSR_MQM_MSC_BASE + 0x524) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_10_REG (CSR_MQM_MSC_BASE + 0x528) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_11_REG (CSR_MQM_MSC_BASE + 0x52C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_12_REG (CSR_MQM_MSC_BASE + 0x530) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_13_REG (CSR_MQM_MSC_BASE + 0x534) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_14_REG (CSR_MQM_MSC_BASE + 0x538) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_15_REG (CSR_MQM_MSC_BASE + 0x53C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_16_REG (CSR_MQM_MSC_BASE + 0x540) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_17_REG (CSR_MQM_MSC_BASE + 0x544) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_18_REG (CSR_MQM_MSC_BASE + 0x548) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_19_REG (CSR_MQM_MSC_BASE + 0x54C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_20_REG (CSR_MQM_MSC_BASE + 0x550) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_21_REG (CSR_MQM_MSC_BASE + 0x554) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_22_REG (CSR_MQM_MSC_BASE + 0x558) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_23_REG (CSR_MQM_MSC_BASE + 0x55C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_24_REG (CSR_MQM_MSC_BASE + 0x560) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_25_REG (CSR_MQM_MSC_BASE + 0x564) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_26_REG (CSR_MQM_MSC_BASE + 0x568) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_27_REG (CSR_MQM_MSC_BASE + 0x56C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_28_REG (CSR_MQM_MSC_BASE + 0x570) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_29_REG (CSR_MQM_MSC_BASE + 0x574) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_30_REG (CSR_MQM_MSC_BASE + 0x578) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_31_REG (CSR_MQM_MSC_BASE + 0x57C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_32_REG (CSR_MQM_MSC_BASE + 0x580) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_33_REG (CSR_MQM_MSC_BASE + 0x584) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_34_REG (CSR_MQM_MSC_BASE + 0x588) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_35_REG (CSR_MQM_MSC_BASE + 0x58C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_36_REG (CSR_MQM_MSC_BASE + 0x590) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_37_REG (CSR_MQM_MSC_BASE + 0x594) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_38_REG (CSR_MQM_MSC_BASE + 0x598) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_39_REG (CSR_MQM_MSC_BASE + 0x59C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_40_REG (CSR_MQM_MSC_BASE + 0x5A0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_41_REG (CSR_MQM_MSC_BASE + 0x5A4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_42_REG (CSR_MQM_MSC_BASE + 0x5A8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_43_REG (CSR_MQM_MSC_BASE + 0x5AC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_44_REG (CSR_MQM_MSC_BASE + 0x5B0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_45_REG (CSR_MQM_MSC_BASE + 0x5B4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_46_REG (CSR_MQM_MSC_BASE + 0x5B8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_47_REG (CSR_MQM_MSC_BASE + 0x5BC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_48_REG (CSR_MQM_MSC_BASE + 0x5C0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_49_REG (CSR_MQM_MSC_BASE + 0x5C4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_50_REG (CSR_MQM_MSC_BASE + 0x5C8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_51_REG (CSR_MQM_MSC_BASE + 0x5CC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_52_REG (CSR_MQM_MSC_BASE + 0x5D0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_53_REG (CSR_MQM_MSC_BASE + 0x5D4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_54_REG (CSR_MQM_MSC_BASE + 0x5D8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_55_REG (CSR_MQM_MSC_BASE + 0x5DC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_56_REG (CSR_MQM_MSC_BASE + 0x5E0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_57_REG (CSR_MQM_MSC_BASE + 0x5E4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_58_REG (CSR_MQM_MSC_BASE + 0x5E8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_59_REG (CSR_MQM_MSC_BASE + 0x5EC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_60_REG (CSR_MQM_MSC_BASE + 0x5F0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_61_REG (CSR_MQM_MSC_BASE + 0x5F4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_62_REG (CSR_MQM_MSC_BASE + 0x5F8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_63_REG (CSR_MQM_MSC_BASE + 0x5FC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_64_REG (CSR_MQM_MSC_BASE + 0x600) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_65_REG (CSR_MQM_MSC_BASE + 0x604) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_66_REG (CSR_MQM_MSC_BASE + 0x608) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_67_REG (CSR_MQM_MSC_BASE + 0x60C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_68_REG (CSR_MQM_MSC_BASE + 0x610) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_69_REG (CSR_MQM_MSC_BASE + 0x614) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_70_REG (CSR_MQM_MSC_BASE + 0x618) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_71_REG (CSR_MQM_MSC_BASE + 0x61C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_72_REG (CSR_MQM_MSC_BASE + 0x620) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_73_REG (CSR_MQM_MSC_BASE + 0x624) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_74_REG (CSR_MQM_MSC_BASE + 0x628) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_75_REG (CSR_MQM_MSC_BASE + 0x62C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_76_REG (CSR_MQM_MSC_BASE + 0x630) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_77_REG (CSR_MQM_MSC_BASE + 0x634) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_78_REG (CSR_MQM_MSC_BASE + 0x638) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_79_REG (CSR_MQM_MSC_BASE + 0x63C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_80_REG (CSR_MQM_MSC_BASE + 0x640) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_81_REG (CSR_MQM_MSC_BASE + 0x644) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_82_REG (CSR_MQM_MSC_BASE + 0x648) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_83_REG (CSR_MQM_MSC_BASE + 0x64C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_84_REG (CSR_MQM_MSC_BASE + 0x650) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_85_REG (CSR_MQM_MSC_BASE + 0x654) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_86_REG (CSR_MQM_MSC_BASE + 0x658) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_87_REG (CSR_MQM_MSC_BASE + 0x65C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_88_REG (CSR_MQM_MSC_BASE + 0x660) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_89_REG (CSR_MQM_MSC_BASE + 0x664) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_90_REG (CSR_MQM_MSC_BASE + 0x668) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_91_REG (CSR_MQM_MSC_BASE + 0x66C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_92_REG (CSR_MQM_MSC_BASE + 0x670) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_93_REG (CSR_MQM_MSC_BASE + 0x674) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_94_REG (CSR_MQM_MSC_BASE + 0x678) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_95_REG (CSR_MQM_MSC_BASE + 0x67C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_96_REG (CSR_MQM_MSC_BASE + 0x680) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_97_REG (CSR_MQM_MSC_BASE + 0x684) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_98_REG (CSR_MQM_MSC_BASE + 0x688) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_99_REG (CSR_MQM_MSC_BASE + 0x68C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_100_REG (CSR_MQM_MSC_BASE + 0x690) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_101_REG (CSR_MQM_MSC_BASE + 0x694) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_102_REG (CSR_MQM_MSC_BASE + 0x698) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_103_REG (CSR_MQM_MSC_BASE + 0x69C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_104_REG (CSR_MQM_MSC_BASE + 0x6A0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_105_REG (CSR_MQM_MSC_BASE + 0x6A4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_106_REG (CSR_MQM_MSC_BASE + 0x6A8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_107_REG (CSR_MQM_MSC_BASE + 0x6AC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_108_REG (CSR_MQM_MSC_BASE + 0x6B0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_109_REG (CSR_MQM_MSC_BASE + 0x6B4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_110_REG (CSR_MQM_MSC_BASE + 0x6B8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_111_REG (CSR_MQM_MSC_BASE + 0x6BC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_112_REG (CSR_MQM_MSC_BASE + 0x6C0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_113_REG (CSR_MQM_MSC_BASE + 0x6C4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_114_REG (CSR_MQM_MSC_BASE + 0x6C8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_115_REG (CSR_MQM_MSC_BASE + 0x6CC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_116_REG (CSR_MQM_MSC_BASE + 0x6D0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_117_REG (CSR_MQM_MSC_BASE + 0x6D4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_118_REG (CSR_MQM_MSC_BASE + 0x6D8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_119_REG (CSR_MQM_MSC_BASE + 0x6DC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_120_REG (CSR_MQM_MSC_BASE + 0x6E0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_121_REG (CSR_MQM_MSC_BASE + 0x6E4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_122_REG (CSR_MQM_MSC_BASE + 0x6E8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_123_REG (CSR_MQM_MSC_BASE + 0x6EC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_124_REG (CSR_MQM_MSC_BASE + 0x6F0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_125_REG (CSR_MQM_MSC_BASE + 0x6F4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_126_REG (CSR_MQM_MSC_BASE + 0x6F8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_127_REG (CSR_MQM_MSC_BASE + 0x6FC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_0_REG (CSR_MQM_MSC_BASE + 0x700) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_1_REG (CSR_MQM_MSC_BASE + 0x704) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_2_REG (CSR_MQM_MSC_BASE + 0x708) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_3_REG (CSR_MQM_MSC_BASE + 0x70C) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_4_REG (CSR_MQM_MSC_BASE + 0x710) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_5_REG (CSR_MQM_MSC_BASE + 0x714) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_6_REG (CSR_MQM_MSC_BASE + 0x718) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_7_REG (CSR_MQM_MSC_BASE + 0x71C) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_8_REG (CSR_MQM_MSC_BASE + 0x720) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_9_REG (CSR_MQM_MSC_BASE + 0x724) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_10_REG (CSR_MQM_MSC_BASE + 0x728) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_11_REG (CSR_MQM_MSC_BASE + 0x72C) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_12_REG (CSR_MQM_MSC_BASE + 0x730) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_13_REG (CSR_MQM_MSC_BASE + 0x734) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_14_REG (CSR_MQM_MSC_BASE + 0x738) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_15_REG (CSR_MQM_MSC_BASE + 0x73C) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_SERV_WEIGHT_CFG_0_REG \ + (CSR_MQM_MSC_BASE + 0x740) /* SOCMSC SERVICE Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_SERV_WEIGHT_CFG_1_REG \ + (CSR_MQM_MSC_BASE + 0x744) /* SOCMSC SERVICE Node Weight Configuration Table */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_0_REG \ + (CSR_MQM_MSC_BASE + 0x750) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_1_REG \ + (CSR_MQM_MSC_BASE + 0x754) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_2_REG \ + (CSR_MQM_MSC_BASE + 0x758) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_3_REG \ + (CSR_MQM_MSC_BASE + 0x75C) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_0_REG \ + (CSR_MQM_MSC_BASE + 0x760) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_1_REG \ + (CSR_MQM_MSC_BASE + 0x764) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_2_REG \ + (CSR_MQM_MSC_BASE + 0x768) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_3_REG \ + (CSR_MQM_MSC_BASE + 0x76C) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x770) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x774) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x778) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x77C) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x780) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x784) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x788) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x78C) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x790) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x794) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x798) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x79C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_4_REG \ + (CSR_MQM_MSC_BASE + 0x7A0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_5_REG \ + (CSR_MQM_MSC_BASE + 0x7A4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_6_REG \ + (CSR_MQM_MSC_BASE + 0x7A8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_7_REG \ + (CSR_MQM_MSC_BASE + 0x7AC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_8_REG \ + (CSR_MQM_MSC_BASE + 0x7B0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_9_REG \ + (CSR_MQM_MSC_BASE + 0x7B4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_10_REG \ + (CSR_MQM_MSC_BASE + 0x7B8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_11_REG \ + (CSR_MQM_MSC_BASE + 0x7BC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_12_REG \ + (CSR_MQM_MSC_BASE + 0x7C0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_13_REG \ + (CSR_MQM_MSC_BASE + 0x7C4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_14_REG \ + (CSR_MQM_MSC_BASE + 0x7C8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_15_REG \ + (CSR_MQM_MSC_BASE + 0x7CC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_16_REG \ + (CSR_MQM_MSC_BASE + 0x7D0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_17_REG \ + (CSR_MQM_MSC_BASE + 0x7D4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_18_REG \ + (CSR_MQM_MSC_BASE + 0x7D8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_19_REG \ + (CSR_MQM_MSC_BASE + 0x7DC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_20_REG \ + (CSR_MQM_MSC_BASE + 0x7E0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_21_REG \ + (CSR_MQM_MSC_BASE + 0x7E4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_22_REG \ + (CSR_MQM_MSC_BASE + 0x7E8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_23_REG \ + (CSR_MQM_MSC_BASE + 0x7EC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_24_REG \ + (CSR_MQM_MSC_BASE + 0x7F0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_25_REG \ + (CSR_MQM_MSC_BASE + 0x7F4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_26_REG \ + (CSR_MQM_MSC_BASE + 0x7F8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_27_REG \ + (CSR_MQM_MSC_BASE + 0x7FC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_28_REG \ + (CSR_MQM_MSC_BASE + 0x800) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_29_REG \ + (CSR_MQM_MSC_BASE + 0x804) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_30_REG \ + (CSR_MQM_MSC_BASE + 0x808) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_31_REG \ + (CSR_MQM_MSC_BASE + 0x80C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x810) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x814) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x818) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x81C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_4_REG \ + (CSR_MQM_MSC_BASE + 0x820) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_5_REG \ + (CSR_MQM_MSC_BASE + 0x824) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_6_REG \ + (CSR_MQM_MSC_BASE + 0x828) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_7_REG \ + (CSR_MQM_MSC_BASE + 0x82C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_8_REG \ + (CSR_MQM_MSC_BASE + 0x830) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_9_REG \ + (CSR_MQM_MSC_BASE + 0x834) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_10_REG \ + (CSR_MQM_MSC_BASE + 0x838) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_11_REG \ + (CSR_MQM_MSC_BASE + 0x83C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_12_REG \ + (CSR_MQM_MSC_BASE + 0x840) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_13_REG \ + (CSR_MQM_MSC_BASE + 0x844) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_14_REG \ + (CSR_MQM_MSC_BASE + 0x848) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_15_REG \ + (CSR_MQM_MSC_BASE + 0x84C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_16_REG \ + (CSR_MQM_MSC_BASE + 0x850) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_17_REG \ + (CSR_MQM_MSC_BASE + 0x854) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_18_REG \ + (CSR_MQM_MSC_BASE + 0x858) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_19_REG \ + (CSR_MQM_MSC_BASE + 0x85C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_20_REG \ + (CSR_MQM_MSC_BASE + 0x860) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_21_REG \ + (CSR_MQM_MSC_BASE + 0x864) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_22_REG \ + (CSR_MQM_MSC_BASE + 0x868) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_23_REG \ + (CSR_MQM_MSC_BASE + 0x86C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_24_REG \ + (CSR_MQM_MSC_BASE + 0x870) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_25_REG \ + (CSR_MQM_MSC_BASE + 0x874) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_26_REG \ + (CSR_MQM_MSC_BASE + 0x878) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_27_REG \ + (CSR_MQM_MSC_BASE + 0x87C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_28_REG \ + (CSR_MQM_MSC_BASE + 0x880) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_29_REG \ + (CSR_MQM_MSC_BASE + 0x884) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_30_REG \ + (CSR_MQM_MSC_BASE + 0x888) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_31_REG \ + (CSR_MQM_MSC_BASE + 0x88C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x890) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x894) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x898) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x89C) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x8A0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x8A4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x8A8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x8AC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x8B0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x8B4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x8B8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x8BC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x8C0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x8C4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x8C8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x8CC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x8D0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x8D4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x8D8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x8DC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x8E0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x8E4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x8E8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x8EC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x8F0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x8F4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x8F8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x8FC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0x900) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0x904) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0x908) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0x90C) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x910) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x914) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x918) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x91C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x920) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x924) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x928) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x92C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x930) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x934) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x938) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x93C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x940) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x944) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x948) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x94C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x950) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x954) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x958) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x95C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x960) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x964) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x968) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x96C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x970) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x974) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x978) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x97C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0x980) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0x984) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0x988) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0x98C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x990) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x994) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x998) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x99C) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x9A0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x9A4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x9A8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x9AC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x9B0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x9B4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x9B8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x9BC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x9C0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x9C4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x9C8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x9CC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x9D0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x9D4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x9D8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x9DC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x9E0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x9E4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x9E8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x9EC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x9F0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x9F4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x9F8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x9FC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0xA00) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0xA04) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0xA08) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0xA0C) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0xA10) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0xA14) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0xA18) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0xA1C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0xA20) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0xA24) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0xA28) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0xA2C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0xA30) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0xA34) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0xA38) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0xA3C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0xA40) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0xA44) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0xA48) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0xA4C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0xA50) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0xA54) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0xA58) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0xA5C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0xA60) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0xA64) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0xA68) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0xA6C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0xA70) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0xA74) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0xA78) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0xA7C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0xA80) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0xA84) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0xA88) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0xA8C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xB00) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xB04) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xB08) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xB0C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xB10) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xB14) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xB18) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xB1C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xB20) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xB24) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xB28) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xB2C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xB30) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xB34) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xB38) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xB3C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_16_REG (CSR_MQM_MSC_BASE + 0xB40) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_17_REG (CSR_MQM_MSC_BASE + 0xB44) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_18_REG (CSR_MQM_MSC_BASE + 0xB48) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_19_REG (CSR_MQM_MSC_BASE + 0xB4C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_20_REG (CSR_MQM_MSC_BASE + 0xB50) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_21_REG (CSR_MQM_MSC_BASE + 0xB54) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_22_REG (CSR_MQM_MSC_BASE + 0xB58) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_23_REG (CSR_MQM_MSC_BASE + 0xB5C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_24_REG (CSR_MQM_MSC_BASE + 0xB60) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_25_REG (CSR_MQM_MSC_BASE + 0xB64) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_26_REG (CSR_MQM_MSC_BASE + 0xB68) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_27_REG (CSR_MQM_MSC_BASE + 0xB6C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_28_REG (CSR_MQM_MSC_BASE + 0xB70) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_29_REG (CSR_MQM_MSC_BASE + 0xB74) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_30_REG (CSR_MQM_MSC_BASE + 0xB78) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_31_REG (CSR_MQM_MSC_BASE + 0xB7C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_32_REG (CSR_MQM_MSC_BASE + 0xB80) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_33_REG (CSR_MQM_MSC_BASE + 0xB84) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_34_REG (CSR_MQM_MSC_BASE + 0xB88) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_35_REG (CSR_MQM_MSC_BASE + 0xB8C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_36_REG (CSR_MQM_MSC_BASE + 0xB90) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_37_REG (CSR_MQM_MSC_BASE + 0xB94) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_38_REG (CSR_MQM_MSC_BASE + 0xB98) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_39_REG (CSR_MQM_MSC_BASE + 0xB9C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_40_REG (CSR_MQM_MSC_BASE + 0xBA0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_41_REG (CSR_MQM_MSC_BASE + 0xBA4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_42_REG (CSR_MQM_MSC_BASE + 0xBA8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_43_REG (CSR_MQM_MSC_BASE + 0xBAC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_44_REG (CSR_MQM_MSC_BASE + 0xBB0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_45_REG (CSR_MQM_MSC_BASE + 0xBB4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_46_REG (CSR_MQM_MSC_BASE + 0xBB8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_47_REG (CSR_MQM_MSC_BASE + 0xBBC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_48_REG (CSR_MQM_MSC_BASE + 0xBC0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_49_REG (CSR_MQM_MSC_BASE + 0xBC4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_50_REG (CSR_MQM_MSC_BASE + 0xBC8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_51_REG (CSR_MQM_MSC_BASE + 0xBCC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_52_REG (CSR_MQM_MSC_BASE + 0xBD0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_53_REG (CSR_MQM_MSC_BASE + 0xBD4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_54_REG (CSR_MQM_MSC_BASE + 0xBD8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_55_REG (CSR_MQM_MSC_BASE + 0xBDC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_56_REG (CSR_MQM_MSC_BASE + 0xBE0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_57_REG (CSR_MQM_MSC_BASE + 0xBE4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_58_REG (CSR_MQM_MSC_BASE + 0xBE8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_59_REG (CSR_MQM_MSC_BASE + 0xBEC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_60_REG (CSR_MQM_MSC_BASE + 0xBF0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_61_REG (CSR_MQM_MSC_BASE + 0xBF4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_62_REG (CSR_MQM_MSC_BASE + 0xBF8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_63_REG (CSR_MQM_MSC_BASE + 0xBFC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_64_REG (CSR_MQM_MSC_BASE + 0xC00) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_65_REG (CSR_MQM_MSC_BASE + 0xC04) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_66_REG (CSR_MQM_MSC_BASE + 0xC08) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_67_REG (CSR_MQM_MSC_BASE + 0xC0C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_68_REG (CSR_MQM_MSC_BASE + 0xC10) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_69_REG (CSR_MQM_MSC_BASE + 0xC14) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_70_REG (CSR_MQM_MSC_BASE + 0xC18) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_71_REG (CSR_MQM_MSC_BASE + 0xC1C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_72_REG (CSR_MQM_MSC_BASE + 0xC20) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_73_REG (CSR_MQM_MSC_BASE + 0xC24) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_74_REG (CSR_MQM_MSC_BASE + 0xC28) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_75_REG (CSR_MQM_MSC_BASE + 0xC2C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_76_REG (CSR_MQM_MSC_BASE + 0xC30) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_77_REG (CSR_MQM_MSC_BASE + 0xC34) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_78_REG (CSR_MQM_MSC_BASE + 0xC38) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_79_REG (CSR_MQM_MSC_BASE + 0xC3C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_80_REG (CSR_MQM_MSC_BASE + 0xC40) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_81_REG (CSR_MQM_MSC_BASE + 0xC44) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_82_REG (CSR_MQM_MSC_BASE + 0xC48) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_83_REG (CSR_MQM_MSC_BASE + 0xC4C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_84_REG (CSR_MQM_MSC_BASE + 0xC50) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_85_REG (CSR_MQM_MSC_BASE + 0xC54) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_86_REG (CSR_MQM_MSC_BASE + 0xC58) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_87_REG (CSR_MQM_MSC_BASE + 0xC5C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_88_REG (CSR_MQM_MSC_BASE + 0xC60) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_89_REG (CSR_MQM_MSC_BASE + 0xC64) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_90_REG (CSR_MQM_MSC_BASE + 0xC68) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_91_REG (CSR_MQM_MSC_BASE + 0xC6C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_92_REG (CSR_MQM_MSC_BASE + 0xC70) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_93_REG (CSR_MQM_MSC_BASE + 0xC74) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_94_REG (CSR_MQM_MSC_BASE + 0xC78) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_95_REG (CSR_MQM_MSC_BASE + 0xC7C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_96_REG (CSR_MQM_MSC_BASE + 0xC80) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_97_REG (CSR_MQM_MSC_BASE + 0xC84) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_98_REG (CSR_MQM_MSC_BASE + 0xC88) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_99_REG (CSR_MQM_MSC_BASE + 0xC8C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_100_REG \ + (CSR_MQM_MSC_BASE + 0xC90) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_101_REG \ + (CSR_MQM_MSC_BASE + 0xC94) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_102_REG \ + (CSR_MQM_MSC_BASE + 0xC98) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_103_REG \ + (CSR_MQM_MSC_BASE + 0xC9C) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_104_REG \ + (CSR_MQM_MSC_BASE + 0xCA0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_105_REG \ + (CSR_MQM_MSC_BASE + 0xCA4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_106_REG \ + (CSR_MQM_MSC_BASE + 0xCA8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_107_REG \ + (CSR_MQM_MSC_BASE + 0xCAC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_108_REG \ + (CSR_MQM_MSC_BASE + 0xCB0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_109_REG \ + (CSR_MQM_MSC_BASE + 0xCB4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_110_REG \ + (CSR_MQM_MSC_BASE + 0xCB8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_111_REG \ + (CSR_MQM_MSC_BASE + 0xCBC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_112_REG \ + (CSR_MQM_MSC_BASE + 0xCC0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_113_REG \ + (CSR_MQM_MSC_BASE + 0xCC4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_114_REG \ + (CSR_MQM_MSC_BASE + 0xCC8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_115_REG \ + (CSR_MQM_MSC_BASE + 0xCCC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_116_REG \ + (CSR_MQM_MSC_BASE + 0xCD0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_117_REG \ + (CSR_MQM_MSC_BASE + 0xCD4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_118_REG \ + (CSR_MQM_MSC_BASE + 0xCD8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_119_REG \ + (CSR_MQM_MSC_BASE + 0xCDC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_120_REG \ + (CSR_MQM_MSC_BASE + 0xCE0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_121_REG \ + (CSR_MQM_MSC_BASE + 0xCE4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_122_REG \ + (CSR_MQM_MSC_BASE + 0xCE8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_123_REG \ + (CSR_MQM_MSC_BASE + 0xCEC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_124_REG \ + (CSR_MQM_MSC_BASE + 0xCF0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_125_REG \ + (CSR_MQM_MSC_BASE + 0xCF4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_126_REG \ + (CSR_MQM_MSC_BASE + 0xCF8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_127_REG \ + (CSR_MQM_MSC_BASE + 0xCFC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xD00) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xD04) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xD08) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xD0C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xD10) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xD14) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xD18) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xD1C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xD20) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xD24) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xD28) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xD2C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xD30) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xD34) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xD38) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xD3C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_16_REG (CSR_MQM_MSC_BASE + 0xD40) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_17_REG (CSR_MQM_MSC_BASE + 0xD44) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_18_REG (CSR_MQM_MSC_BASE + 0xD48) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_19_REG (CSR_MQM_MSC_BASE + 0xD4C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_20_REG (CSR_MQM_MSC_BASE + 0xD50) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_21_REG (CSR_MQM_MSC_BASE + 0xD54) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_22_REG (CSR_MQM_MSC_BASE + 0xD58) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_23_REG (CSR_MQM_MSC_BASE + 0xD5C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_24_REG (CSR_MQM_MSC_BASE + 0xD60) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_25_REG (CSR_MQM_MSC_BASE + 0xD64) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_26_REG (CSR_MQM_MSC_BASE + 0xD68) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_27_REG (CSR_MQM_MSC_BASE + 0xD6C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_28_REG (CSR_MQM_MSC_BASE + 0xD70) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_29_REG (CSR_MQM_MSC_BASE + 0xD74) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_30_REG (CSR_MQM_MSC_BASE + 0xD78) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_31_REG (CSR_MQM_MSC_BASE + 0xD7C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_32_REG (CSR_MQM_MSC_BASE + 0xD80) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_33_REG (CSR_MQM_MSC_BASE + 0xD84) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_34_REG (CSR_MQM_MSC_BASE + 0xD88) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_35_REG (CSR_MQM_MSC_BASE + 0xD8C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_36_REG (CSR_MQM_MSC_BASE + 0xD90) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_37_REG (CSR_MQM_MSC_BASE + 0xD94) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_38_REG (CSR_MQM_MSC_BASE + 0xD98) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_39_REG (CSR_MQM_MSC_BASE + 0xD9C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_40_REG (CSR_MQM_MSC_BASE + 0xDA0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_41_REG (CSR_MQM_MSC_BASE + 0xDA4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_42_REG (CSR_MQM_MSC_BASE + 0xDA8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_43_REG (CSR_MQM_MSC_BASE + 0xDAC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_44_REG (CSR_MQM_MSC_BASE + 0xDB0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_45_REG (CSR_MQM_MSC_BASE + 0xDB4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_46_REG (CSR_MQM_MSC_BASE + 0xDB8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_47_REG (CSR_MQM_MSC_BASE + 0xDBC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_48_REG (CSR_MQM_MSC_BASE + 0xDC0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_49_REG (CSR_MQM_MSC_BASE + 0xDC4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_50_REG (CSR_MQM_MSC_BASE + 0xDC8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_51_REG (CSR_MQM_MSC_BASE + 0xDCC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_52_REG (CSR_MQM_MSC_BASE + 0xDD0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_53_REG (CSR_MQM_MSC_BASE + 0xDD4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_54_REG (CSR_MQM_MSC_BASE + 0xDD8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_55_REG (CSR_MQM_MSC_BASE + 0xDDC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_56_REG (CSR_MQM_MSC_BASE + 0xDE0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_57_REG (CSR_MQM_MSC_BASE + 0xDE4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_58_REG (CSR_MQM_MSC_BASE + 0xDE8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_59_REG (CSR_MQM_MSC_BASE + 0xDEC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_60_REG (CSR_MQM_MSC_BASE + 0xDF0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_61_REG (CSR_MQM_MSC_BASE + 0xDF4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_62_REG (CSR_MQM_MSC_BASE + 0xDF8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_63_REG (CSR_MQM_MSC_BASE + 0xDFC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_64_REG (CSR_MQM_MSC_BASE + 0xE00) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_65_REG (CSR_MQM_MSC_BASE + 0xE04) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_66_REG (CSR_MQM_MSC_BASE + 0xE08) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_67_REG (CSR_MQM_MSC_BASE + 0xE0C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_68_REG (CSR_MQM_MSC_BASE + 0xE10) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_69_REG (CSR_MQM_MSC_BASE + 0xE14) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_70_REG (CSR_MQM_MSC_BASE + 0xE18) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_71_REG (CSR_MQM_MSC_BASE + 0xE1C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_72_REG (CSR_MQM_MSC_BASE + 0xE20) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_73_REG (CSR_MQM_MSC_BASE + 0xE24) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_74_REG (CSR_MQM_MSC_BASE + 0xE28) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_75_REG (CSR_MQM_MSC_BASE + 0xE2C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_76_REG (CSR_MQM_MSC_BASE + 0xE30) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_77_REG (CSR_MQM_MSC_BASE + 0xE34) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_78_REG (CSR_MQM_MSC_BASE + 0xE38) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_79_REG (CSR_MQM_MSC_BASE + 0xE3C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_80_REG (CSR_MQM_MSC_BASE + 0xE40) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_81_REG (CSR_MQM_MSC_BASE + 0xE44) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_82_REG (CSR_MQM_MSC_BASE + 0xE48) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_83_REG (CSR_MQM_MSC_BASE + 0xE4C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_84_REG (CSR_MQM_MSC_BASE + 0xE50) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_85_REG (CSR_MQM_MSC_BASE + 0xE54) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_86_REG (CSR_MQM_MSC_BASE + 0xE58) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_87_REG (CSR_MQM_MSC_BASE + 0xE5C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_88_REG (CSR_MQM_MSC_BASE + 0xE60) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_89_REG (CSR_MQM_MSC_BASE + 0xE64) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_90_REG (CSR_MQM_MSC_BASE + 0xE68) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_91_REG (CSR_MQM_MSC_BASE + 0xE6C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_92_REG (CSR_MQM_MSC_BASE + 0xE70) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_93_REG (CSR_MQM_MSC_BASE + 0xE74) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_94_REG (CSR_MQM_MSC_BASE + 0xE78) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_95_REG (CSR_MQM_MSC_BASE + 0xE7C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_96_REG (CSR_MQM_MSC_BASE + 0xE80) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_97_REG (CSR_MQM_MSC_BASE + 0xE84) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_98_REG (CSR_MQM_MSC_BASE + 0xE88) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_99_REG (CSR_MQM_MSC_BASE + 0xE8C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_100_REG \ + (CSR_MQM_MSC_BASE + 0xE90) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_101_REG \ + (CSR_MQM_MSC_BASE + 0xE94) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_102_REG \ + (CSR_MQM_MSC_BASE + 0xE98) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_103_REG \ + (CSR_MQM_MSC_BASE + 0xE9C) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_104_REG \ + (CSR_MQM_MSC_BASE + 0xEA0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_105_REG \ + (CSR_MQM_MSC_BASE + 0xEA4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_106_REG \ + (CSR_MQM_MSC_BASE + 0xEA8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_107_REG \ + (CSR_MQM_MSC_BASE + 0xEAC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_108_REG \ + (CSR_MQM_MSC_BASE + 0xEB0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_109_REG \ + (CSR_MQM_MSC_BASE + 0xEB4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_110_REG \ + (CSR_MQM_MSC_BASE + 0xEB8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_111_REG \ + (CSR_MQM_MSC_BASE + 0xEBC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_112_REG \ + (CSR_MQM_MSC_BASE + 0xEC0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_113_REG \ + (CSR_MQM_MSC_BASE + 0xEC4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_114_REG \ + (CSR_MQM_MSC_BASE + 0xEC8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_115_REG \ + (CSR_MQM_MSC_BASE + 0xECC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_116_REG \ + (CSR_MQM_MSC_BASE + 0xED0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_117_REG \ + (CSR_MQM_MSC_BASE + 0xED4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_118_REG \ + (CSR_MQM_MSC_BASE + 0xED8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_119_REG \ + (CSR_MQM_MSC_BASE + 0xEDC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_120_REG \ + (CSR_MQM_MSC_BASE + 0xEE0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_121_REG \ + (CSR_MQM_MSC_BASE + 0xEE4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_122_REG \ + (CSR_MQM_MSC_BASE + 0xEE8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_123_REG \ + (CSR_MQM_MSC_BASE + 0xEEC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_124_REG \ + (CSR_MQM_MSC_BASE + 0xEF0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_125_REG \ + (CSR_MQM_MSC_BASE + 0xEF4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_126_REG \ + (CSR_MQM_MSC_BASE + 0xEF8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_127_REG \ + (CSR_MQM_MSC_BASE + 0xEFC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xF00) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xF04) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xF08) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xF0C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xF10) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xF14) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xF18) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xF1C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xF20) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xF24) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xF28) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xF2C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xF30) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xF34) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xF38) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xF3C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xF40) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xF44) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xF48) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xF4C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xF50) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xF54) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xF58) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xF5C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xF60) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xF64) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xF68) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xF6C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xF70) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xF74) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xF78) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xF7C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCSERV_SHAP_BPS_CFG_0_REG \ + (CSR_MQM_MSC_BASE + 0xF80) /* SOC Service Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCSERV_SHAP_BPS_CFG_1_REG \ + (CSR_MQM_MSC_BASE + 0xF84) /* SOC Service Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCSERV_SHAP_PPS_CFG_0_REG \ + (CSR_MQM_MSC_BASE + 0xF88) /* SOC Service Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCSERV_SHAP_PPS_CFG_1_REG \ + (CSR_MQM_MSC_BASE + 0xF8C) /* SOC Service Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCRT_SHAP_BPS_CFG_REG (CSR_MQM_MSC_BASE + 0xF90) /* SOC Root Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCRT_SHAP_PPS_CFG_REG (CSR_MQM_MSC_BASE + 0xF94) /* SOC Root Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_MSC_SHAP_BYPASS_CFG_REG (CSR_MQM_MSC_BASE + 0x1200) /* MSC Shaper Bypass Configuration */ +#define CSR_MQM_MSC_MSC_HOST_ROOT_XON_CFG_REG \ + (CSR_MQM_MSC_BASE + 0x1204) /* The XON Configuration of the HOST ROOT node */ +#define CSR_MQM_MSC_MSC_SOC_ROOT_XON_CFG_REG \ + (CSR_MQM_MSC_BASE + 0x1208) /* The XON Configuration of the SOC ROOT node */ +#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_NS_REG \ + (CSR_MQM_MSC_BASE + 0x120C) /* The XON Configuration of the NS HOST EP node */ +#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_NFMQ_REG \ + (CSR_MQM_MSC_BASE + 0x1210) /* The XON Configuration of the NFMQ HOST EP node */ +#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_CMQ_REG \ + (CSR_MQM_MSC_BASE + 0x1214) /* The XON Configuration of the CMQ HOST EP node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x1220) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x1224) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x1228) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x122C) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_MSC_PRM_PORT_BP_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1230) /* MSC Port backpress status Register 0 from PRM */ +#define CSR_MQM_MSC_MSC_PRM_PORT_BP_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x1234) /* MSC Port backpress status Register 1 from PRM */ +#define CSR_MQM_MSC_MSC_QU_COS_BP_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1238) /* MSC COS Level backpress status Register for NMQ EP0~EP3 */ +#define CSR_MQM_MSC_MSC_QU_COS_BP_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x123C) /* MSC COS Level backpress status Register for NMQ EP4~EP7 */ +#define CSR_MQM_MSC_SOCMSC_RT_EP_BP_STA_REG (CSR_MQM_MSC_BASE + 0x1240) /* SOC MSC backpress status Register */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1244) /* SOCMSC QUEUE Level backpress status Register 0 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x1248) /* SOCMSC QUEUE Level backpress status Register 1 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA2_REG \ + (CSR_MQM_MSC_BASE + 0x124C) /* SOCMSC QUEUE Level backpress status Register 2 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA3_REG \ + (CSR_MQM_MSC_BASE + 0x1250) /* SOCMSC QUEUE Level backpress status Register 3 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1254) /* SOCMSC QUEUE Level eligible status Register 0 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x1258) /* SOCMSC QUEUE Level eligible status Register 1 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA2_REG \ + (CSR_MQM_MSC_BASE + 0x125C) /* SOCMSC QUEUE Level eligible status Register 2 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA3_REG \ + (CSR_MQM_MSC_BASE + 0x1260) /* SOCMSC QUEUE Level eligible status Register 3 */ +#define CSR_MQM_MSC_MSC_RT_HOST_BP_STA_REG (CSR_MQM_MSC_BASE + 0x1264) /* MSC root host backpress status Register */ +#define CSR_MQM_MSC_MSC_HOSTEP_NS_BP_STA_REG \ + (CSR_MQM_MSC_BASE + 0x1268) /* MSC NS HSOT_EP Level backpress status Register */ +#define CSR_MQM_MSC_MSC_HOSTEP_NFMQ_BP_STA_REG \ + (CSR_MQM_MSC_BASE + 0x126C) /* MSC NFMQ HSOT_EP Level backpress status Register */ +#define CSR_MQM_MSC_MSC_HOSTEP_CMQ_BP_STA_REG \ + (CSR_MQM_MSC_BASE + 0x1270) /* MSC CMQ HSOT_EP Level backpress status Register */ +#define CSR_MQM_MSC_MSC_FIFO_TH_CFG_REG (CSR_MQM_MSC_BASE + 0x1274) /* The Threshold Config Of MSC FIFO */ +#define CSR_MQM_MSC_MSC_FIFO_ST0_REG (CSR_MQM_MSC_BASE + 0x1290) /* fifo full and empt state */ +#define CSR_MQM_MSC_MSC_FIFO_ST1_REG (CSR_MQM_MSC_BASE + 0x1294) /* fifo full and empt state */ +#define CSR_MQM_MSC_MSC_FIFO_ST2_REG (CSR_MQM_MSC_BASE + 0x1298) /* fifo full and empt state */ +#define CSR_MQM_MSC_MSC_FIFO_ST3_REG (CSR_MQM_MSC_BASE + 0x129C) /* fifo full and empt state */ +#define CSR_MQM_MSC_CMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A0) /* Command MQ ENQ UP count */ +#define CSR_MQM_MSC_NFMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A4) /* Non-filter MQ ENQ UP count */ +#define CSR_MQM_MSC_NMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A8) /* Normal MQ ENQ UP count */ +#define CSR_MQM_MSC_CMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12AC) /* Command MQ schedule count */ +#define CSR_MQM_MSC_NFMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12B0) /* Non-filter MQ schedule count. */ +#define CSR_MQM_MSC_NMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12B4) /* Normal MQ schedule cnt numbers */ +#define CSR_MQM_MSC_SOCCMQ_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12B8) /* SOC Command MQ UP count */ +#define CSR_MQM_MSC_SOCNMQ_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12BC) /* SOC NMQ UP count. */ +#define CSR_MQM_MSC_SOCCMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C0) /* SOC Command MQ schedule count */ +#define CSR_MQM_MSC_SOCNMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C4) /* SOC NMQ schedule count. */ +#define CSR_MQM_MSC_CMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C8) /* Command MQ EMPT schedule count */ +#define CSR_MQM_MSC_NFMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12CC) /* Non-filter MQ EMPT schedule count */ +#define CSR_MQM_MSC_NMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12D0) /* Normal MQ EMPT schedule count */ +#define CSR_MQM_MSC_CMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12D4) /* Command MQ DU count */ +#define CSR_MQM_MSC_NFMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12D8) /* Non-filter MQ DU count */ +#define CSR_MQM_MSC_NMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12DC) /* Normal MQ DU count */ +#define CSR_MQM_MSC_SOCCMQ_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12E0) /* SOC Command MQ DU count */ +#define CSR_MQM_MSC_SOCNMQ_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12E4) /* SOC NMQ DU count. */ +#define CSR_MQM_MSC_MSC_ECC_1BIT_ERR_CNT_REG (CSR_MQM_MSC_BASE + 0x12E8) /* MSC MEMORY ECC 1BIT ERR count */ +#define CSR_MQM_MSC_MSC_ECC_2BIT_ERR_CNT_REG (CSR_MQM_MSC_BASE + 0x12EC) /* MSC MEMORY ECC 2BIT ERR count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_CFG_REG (CSR_MQM_MSC_BASE + 0x1320) /* MQ DFX NUM configure */ +#define CSR_MQM_MSC_SCH_MQ_DFX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x1324) /* MQ DFX NUM ENQ UP count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x1328) /* MQ DFX NUM DEQ SCH count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x132C) /* MQ DFX NUM DEQ EMPT SCH count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x1330) /* MQ DFX NUM DU count */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_CFG_REG (CSR_MQM_MSC_BASE + 0x1334) /* SOCMQ DFX NUM configure */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x1338) /* SOCMQ DFX NUM ENQ UP count */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x133C) /* SOCMQ DFX NUM DEQ SCH count */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x1340) /* SOCMQ DFX NUM DU count */ +#define CSR_MQM_MSC_SOCMSC_MCD_DU_INFO_PTR0_REG \ + (CSR_MQM_MSC_BASE + 0x1344) /* MQM SOCMSC MCD DU INFO 0 status Register */ +#define CSR_MQM_MSC_SOCMSC_MCD_DU_INFO_PTR1_REG \ + (CSR_MQM_MSC_BASE + 0x1348) /* MQM SOCMSC MCD DU INFO 1 status Register */ +#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR0_REG \ + (CSR_MQM_MSC_BASE + 0x134C) /* MQM MSC CS MCD DU INFO 0 status Register */ +#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR1_REG \ + (CSR_MQM_MSC_BASE + 0x1350) /* MQM MSC CS MCD DU INFO 1 status Register */ +#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR2_REG \ + (CSR_MQM_MSC_BASE + 0x1354) /* MQM MSC CS MCD DU INFO 2 status Register */ +#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR0_REG \ + (CSR_MQM_MSC_BASE + 0x1358) /* MQM MSC NS MCD DU INFO 0 status Register */ +#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR1_REG \ + (CSR_MQM_MSC_BASE + 0x135C) /* MQM MSC NS MCD DU INFO 1 status Register */ +#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR2_REG \ + (CSR_MQM_MSC_BASE + 0x1360) /* MQM MSC NS MCD DU INFO 2 status Register */ + +/* MQM_DEQC Base address of Module's Register */ +#define CSR_MQM_DEQC_BASE (0xE000) + +/* **************************************************************************** */ +/* MQM_DEQC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_DEQC_DEQC_RW_RSV0_REG (CSR_MQM_DEQC_BASE + 0x0) /* DEQC Read-Write Register0 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_RW_RSV1_REG (CSR_MQM_DEQC_BASE + 0x4) /* DEQC Read-Write Register1 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_RW_RSV2_REG (CSR_MQM_DEQC_BASE + 0x8) /* DEQC Read-Write Register2 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_RW_RSV3_REG (CSR_MQM_DEQC_BASE + 0xC) /* DEQC Read-Write Register3 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_INDRECT_CTRL_REG (CSR_MQM_DEQC_BASE + 0x10) /* DEQC Indirect access ctrl Register。 */ +#define CSR_MQM_DEQC_DEQC_INDRECT_TIMEOUT_REG (CSR_MQM_DEQC_BASE + 0x14) /* DEQC Indirect Access Timeout Register。 */ +#define CSR_MQM_DEQC_DEQC_INDRECT_DATA_REG (CSR_MQM_DEQC_BASE + 0x18) /* DEQC Indirect Access Data Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_DEQC_BASE + 0x20) /* RAM ECC BYPASS控制寄存器 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_DEQC_BASE + 0x24) /* RAM CTRL_BUS寄存器0 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_DEQC_BASE + 0x28) /* RAM CTRL_BUS寄存器1 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_DEQC_BASE + 0x2C) /* RAM CTRL_BUS寄存器2 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_DEQC_BASE + 0x30) /* RAM CTRL_BUS寄存器3 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_DEQC_BASE + 0x34) /* RAM CTRL_BUS寄存器4 */ +#define CSR_MQM_DEQC_DEQC_INT_VECTOR_REG (CSR_MQM_DEQC_BASE + 0x100) /* DEQC Internal ERR Interrupt Vector Register. \ + */ +#define CSR_MQM_DEQC_DEQC_INT_REG (CSR_MQM_DEQC_BASE + 0x104) /* DEQC Internal ERR Interrupt Register. */ +#define CSR_MQM_DEQC_DEQC_INT_EN_REG (CSR_MQM_DEQC_BASE + 0x108) /* DEQC Internal ERR Interrupt Mask Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_1BIT_ERR_REG (CSR_MQM_DEQC_BASE + 0x10C) /* DEQC 1Bit ECC Check Err Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_2BIT_ERR_REG (CSR_MQM_DEQC_BASE + 0x110) /* DEQC 2Bit ECC Check Err Register. */ +#define CSR_MQM_DEQC_DEQC_ENMQ_BIND_CONFIG_ERR_REG (CSR_MQM_DEQC_BASE + 0x114) /* DEQC ENMQ BIND CONFIG Err Register. \ + */ +#define CSR_MQM_DEQC_DEQC_ENFMQ_BIND_CONFIG_ERR_REG \ + (CSR_MQM_DEQC_BASE + 0x118) /* DEQC ENFMQ BIND CONFIG Err Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_ERR_REQ_REG (CSR_MQM_DEQC_BASE + 0x150) /* DEQC Internal Memory ERR Req Register. */ +#define CSR_MQM_DEQC_DEQC_FIFO_INT_REG (CSR_MQM_DEQC_BASE + 0x154) /* DEQC FIFO Write Interrupt Register. */ +#define CSR_MQM_DEQC_DEQC_FIFO_WR_INT_MASK_REG \ + (CSR_MQM_DEQC_BASE + 0x158) /* DEQC FIFO Write Interrupt Mask Register. */ +#define CSR_MQM_DEQC_DEQC_TIMES_COUNT_CFG_REG (CSR_MQM_DEQC_BASE + 0x200) /* DEQC TIMES Count Configuration Register \ + */ +#define CSR_MQM_DEQC_DEQC_BLK_DATA_LEN0_REG (CSR_MQM_DEQC_BASE + 0x204) /* DEQC Queue Descriptors Block Size. */ +#define CSR_MQM_DEQC_DEQC_BLK_DATA_LEN1_REG (CSR_MQM_DEQC_BASE + 0x208) /* DEQC Queue Descriptors Block Size. */ +#define CSR_MQM_DEQC_DEQC_ROOT_CRR_WEIGHT_CFG_REG (CSR_MQM_DEQC_BASE + 0x20C) /* DEQC ROOT CRR WEIGHT Config */ +#define CSR_MQM_DEQC_DEQC_WEIGHT_OFFSET_REG (CSR_MQM_DEQC_BASE + 0x210) /* DEQC Weight Offset Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x300) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x304) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x308) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x30C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_4_REG \ + (CSR_MQM_DEQC_BASE + 0x310) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_5_REG \ + (CSR_MQM_DEQC_BASE + 0x314) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_6_REG \ + (CSR_MQM_DEQC_BASE + 0x318) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_7_REG \ + (CSR_MQM_DEQC_BASE + 0x31C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_8_REG \ + (CSR_MQM_DEQC_BASE + 0x320) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_9_REG \ + (CSR_MQM_DEQC_BASE + 0x324) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_10_REG \ + (CSR_MQM_DEQC_BASE + 0x328) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_11_REG \ + (CSR_MQM_DEQC_BASE + 0x32C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_12_REG \ + (CSR_MQM_DEQC_BASE + 0x330) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_13_REG \ + (CSR_MQM_DEQC_BASE + 0x334) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_14_REG \ + (CSR_MQM_DEQC_BASE + 0x338) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_15_REG \ + (CSR_MQM_DEQC_BASE + 0x33C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_16_REG \ + (CSR_MQM_DEQC_BASE + 0x340) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_17_REG \ + (CSR_MQM_DEQC_BASE + 0x344) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_18_REG \ + (CSR_MQM_DEQC_BASE + 0x348) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_19_REG \ + (CSR_MQM_DEQC_BASE + 0x34C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_20_REG \ + (CSR_MQM_DEQC_BASE + 0x350) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_21_REG \ + (CSR_MQM_DEQC_BASE + 0x354) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_22_REG \ + (CSR_MQM_DEQC_BASE + 0x358) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_23_REG \ + (CSR_MQM_DEQC_BASE + 0x35C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_24_REG \ + (CSR_MQM_DEQC_BASE + 0x360) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_25_REG \ + (CSR_MQM_DEQC_BASE + 0x364) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_26_REG \ + (CSR_MQM_DEQC_BASE + 0x368) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_27_REG \ + (CSR_MQM_DEQC_BASE + 0x36C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_28_REG \ + (CSR_MQM_DEQC_BASE + 0x370) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_29_REG \ + (CSR_MQM_DEQC_BASE + 0x374) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_30_REG \ + (CSR_MQM_DEQC_BASE + 0x378) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_31_REG \ + (CSR_MQM_DEQC_BASE + 0x37C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x380) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x384) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x388) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x38C) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_4_REG \ + (CSR_MQM_DEQC_BASE + 0x390) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_5_REG \ + (CSR_MQM_DEQC_BASE + 0x394) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_6_REG \ + (CSR_MQM_DEQC_BASE + 0x398) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_7_REG \ + (CSR_MQM_DEQC_BASE + 0x39C) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_8_REG \ + (CSR_MQM_DEQC_BASE + 0x3A0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_9_REG \ + (CSR_MQM_DEQC_BASE + 0x3A4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_10_REG \ + (CSR_MQM_DEQC_BASE + 0x3A8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_11_REG \ + (CSR_MQM_DEQC_BASE + 0x3AC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_12_REG \ + (CSR_MQM_DEQC_BASE + 0x3B0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_13_REG \ + (CSR_MQM_DEQC_BASE + 0x3B4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_14_REG \ + (CSR_MQM_DEQC_BASE + 0x3B8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_15_REG \ + (CSR_MQM_DEQC_BASE + 0x3BC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_16_REG \ + (CSR_MQM_DEQC_BASE + 0x3C0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_17_REG \ + (CSR_MQM_DEQC_BASE + 0x3C4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_18_REG \ + (CSR_MQM_DEQC_BASE + 0x3C8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_19_REG \ + (CSR_MQM_DEQC_BASE + 0x3CC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_20_REG \ + (CSR_MQM_DEQC_BASE + 0x3D0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_21_REG \ + (CSR_MQM_DEQC_BASE + 0x3D4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_22_REG \ + (CSR_MQM_DEQC_BASE + 0x3D8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_23_REG \ + (CSR_MQM_DEQC_BASE + 0x3DC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_24_REG \ + (CSR_MQM_DEQC_BASE + 0x3E0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_25_REG \ + (CSR_MQM_DEQC_BASE + 0x3E4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_26_REG \ + (CSR_MQM_DEQC_BASE + 0x3E8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_27_REG \ + (CSR_MQM_DEQC_BASE + 0x3EC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_28_REG \ + (CSR_MQM_DEQC_BASE + 0x3F0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_29_REG \ + (CSR_MQM_DEQC_BASE + 0x3F4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_30_REG \ + (CSR_MQM_DEQC_BASE + 0x3F8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_31_REG \ + (CSR_MQM_DEQC_BASE + 0x3FC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x400) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x404) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x408) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x40C) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x410) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x414) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x418) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x41C) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_0_REG \ + (CSR_MQM_DEQC_BASE + 0x420) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_1_REG \ + (CSR_MQM_DEQC_BASE + 0x424) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_2_REG \ + (CSR_MQM_DEQC_BASE + 0x428) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_3_REG \ + (CSR_MQM_DEQC_BASE + 0x42C) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_0_REG \ + (CSR_MQM_DEQC_BASE + 0x430) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_1_REG \ + (CSR_MQM_DEQC_BASE + 0x434) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_2_REG \ + (CSR_MQM_DEQC_BASE + 0x438) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_3_REG \ + (CSR_MQM_DEQC_BASE + 0x43C) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_SERV_SHAP_CFG_0_REG \ + (CSR_MQM_DEQC_BASE + 0x440) /* DEQC SERVICE Node Shaper Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_SERV_SHAP_CFG_1_REG \ + (CSR_MQM_DEQC_BASE + 0x444) /* DEQC SERVICE Node Shaper Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_ROOT_SHAP_CFG_REG \ + (CSR_MQM_DEQC_BASE + 0x450) /* DEQC ROOT Node Shaper Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_SHAP_BYPASS_CFG_REG (CSR_MQM_DEQC_BASE + 0x500) /* DEQC Shaper Bypass Configuration */ +#define CSR_MQM_DEQC_DEQC_SPCOS_SHARE_RSC_XON_RSP_CFG_REG \ + (CSR_MQM_DEQC_BASE + 0x504) /* DEQC Spcos Share Resource XON Response Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_RH_XON_CFG_REG \ + (CSR_MQM_DEQC_BASE + 0x508) /* NFMQ ROOT SERVICE Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_HOST_XON_CFG_NMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x50C) /* NMQ HOST Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_HOST_XON_CFG_NFMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x510) /* NFMQ HOST Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_EP_XON_CFG_NMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x514) /* NMQ EP Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_EP_XON_CFG_NFMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x518) /* NFMQ EP Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_0_REG \ + (CSR_MQM_DEQC_BASE + 0x520) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_1_REG \ + (CSR_MQM_DEQC_BASE + 0x524) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_2_REG \ + (CSR_MQM_DEQC_BASE + 0x528) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_3_REG \ + (CSR_MQM_DEQC_BASE + 0x52C) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_4_REG \ + (CSR_MQM_DEQC_BASE + 0x530) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_5_REG \ + (CSR_MQM_DEQC_BASE + 0x534) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_6_REG \ + (CSR_MQM_DEQC_BASE + 0x538) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_7_REG \ + (CSR_MQM_DEQC_BASE + 0x53C) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_0_REG \ + (CSR_MQM_DEQC_BASE + 0x540) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_1_REG \ + (CSR_MQM_DEQC_BASE + 0x544) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_2_REG \ + (CSR_MQM_DEQC_BASE + 0x548) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_3_REG \ + (CSR_MQM_DEQC_BASE + 0x54C) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_4_REG \ + (CSR_MQM_DEQC_BASE + 0x550) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_5_REG \ + (CSR_MQM_DEQC_BASE + 0x554) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_6_REG \ + (CSR_MQM_DEQC_BASE + 0x558) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_7_REG \ + (CSR_MQM_DEQC_BASE + 0x55C) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_ROOT_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x560) /* Root Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_SERVICE_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x564) /* ENMQ Service Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_SERVICE_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x568) /* ENFMQ Service Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x56C) /* ENMQ Host Node XON Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x570) /* ENFMQ Host Node XON Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x574) /* ENMQ host_ep Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x578) /* ENFMQ host_ep Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SPASS_ST_REG (CSR_MQM_DEQC_BASE + 0x57C) /* ENMQ Host Node Shaping Pass Flag Table \ + */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_PASS_ST_REG \ + (CSR_MQM_DEQC_BASE + 0x580) /* ENFMQ Host Node Shaping Pass Flag Table */ +#define CSR_MQM_DEQC_DEQC_FIFO_DFX_REG (CSR_MQM_DEQC_BASE + 0x584) /* DEQC FIFO Empty and Full DFX Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_UP_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C0) /* ENMQ UP descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_UP_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C4) /* ENFMQ UP descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_DEQ_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C8) /* ENMQ Deq descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_DEQ_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5CC) /* ENFMQ Deq descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D0) /* ENMQ Deq cmd count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D4) /* ENFMQ Deq cmd count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EMPT_SCH_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D8) /* DEQC Non-filter MQ EMPT schedule count \ + */ +#define CSR_MQM_DEQC_DEQC_NMQ_EMPT_SCH_CNT_REG (CSR_MQM_DEQC_BASE + 0x5DC) /* DEQC Normal MQ EMPT schedule count */ +#define CSR_MQM_DEQC_DEQC_ECC_1BIT_ERR_CNT_REG (CSR_MQM_DEQC_BASE + 0x5E0) /* DEQC MEMORY ECC 1BIT ERR count */ +#define CSR_MQM_DEQC_DEQC_ECC_2BIT_ERR_CNT_REG (CSR_MQM_DEQC_BASE + 0x5E4) /* DEQC MEMORY ECC 2BIT ERR count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_CFG_REG (CSR_MQM_DEQC_BASE + 0x5E8) /* DEQC_MQ DFX NUM configure */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_UP_CNT_REG (CSR_MQM_DEQC_BASE + 0x5EC) /* DEQC_MQ DFX NUM ENQ UP count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5F0) /* DEQC_MQ DFX NUM DEQ CMD count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_DEQ_NUM_CNT_REG (CSR_MQM_DEQC_BASE + 0x5F4) /* DEQC_MQ DFX NUM DEQ NUM count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_EMPT_SCH_CNT_REG \ + (CSR_MQM_DEQC_BASE + 0x5F8) /* DEQC_MQ DFX NUM DEQ EMPT SCH count */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_0_REG \ + (CSR_MQM_DEQC_BASE + 0x600) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_1_REG \ + (CSR_MQM_DEQC_BASE + 0x604) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_2_REG \ + (CSR_MQM_DEQC_BASE + 0x608) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_3_REG \ + (CSR_MQM_DEQC_BASE + 0x60C) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_4_REG \ + (CSR_MQM_DEQC_BASE + 0x610) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_5_REG \ + (CSR_MQM_DEQC_BASE + 0x614) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_6_REG \ + (CSR_MQM_DEQC_BASE + 0x618) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_7_REG \ + (CSR_MQM_DEQC_BASE + 0x61C) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_0_REG \ + (CSR_MQM_DEQC_BASE + 0x620) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_1_REG \ + (CSR_MQM_DEQC_BASE + 0x624) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_2_REG \ + (CSR_MQM_DEQC_BASE + 0x628) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_3_REG \ + (CSR_MQM_DEQC_BASE + 0x62C) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_4_REG \ + (CSR_MQM_DEQC_BASE + 0x630) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_5_REG \ + (CSR_MQM_DEQC_BASE + 0x634) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_6_REG \ + (CSR_MQM_DEQC_BASE + 0x638) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_7_REG \ + (CSR_MQM_DEQC_BASE + 0x63C) /* ENFMQ host_ep_cos Node XON State Table0 */ + +#endif // MQM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_c_union_define.h new file mode 100644 index 000000000..6f24eea08 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_c_union_define.h @@ -0,0 +1,2285 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : oq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:07:14 Create file +// ****************************************************************************** + +#ifndef OQ_C_UNION_DEFINE_H +#define OQ_C_UNION_DEFINE_H + +/* Define the union csr_qu_versions_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_versions_u; + +/* Define the union csr_oq_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 16; /* [15:0] */ + u32 csr_oq_other_uncrt_err2itf_en : 1; /* [16] */ + u32 csr_oq_ram_uncrt_err2itf_en : 1; /* [17] */ + u32 csr_oq_mem_init_start : 1; /* [18] */ + u32 csr_oq_mem_ecc_bypass : 1; /* [19] */ + u32 csr_oq_mem_ecc_req : 2; /* [21:20] */ + u32 csr_oq_net_loopback_pre_adj : 4; /* [25:22] */ + u32 csr_oq_net_loopback_prealloc_en : 1; /* [26] */ + u32 csr_oq_hst_dma_coalescing_en : 4; /* [30:27] */ + u32 csr_oq_dma_rcmd_prealloc_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mode_u; + +/* Define the union csr_oq_mode1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_tpmem_timing_ctrl : 8; /* [7:0] */ + u32 csr_oq_spmem_timing_ctrl : 8; /* [15:8] */ + u32 csr_oq_tpmem_power_ctrl : 3; /* [18:16] */ + u32 csr_oq_spmem_power_ctrl : 3; /* [21:19] */ + u32 rsv_1 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mode1_u; + +/* Define the union csr_oq_desenq_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_disenq_oqid : 16; /* [15:0] */ + u32 rsv_2 : 15; /* [30:16] */ + u32 csr_oq_disenq_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_desenq_cfg_u; + +/* Define the union csr_oq_pthru_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_port_pthru_nside : 8; /* [7:0] */ + u32 csr_oq_port_pthru_hside : 6; /* [13:8] */ + u32 csr_oq_pthu_bd_ctr_nside : 8; /* [21:14] */ + u32 csr_oq_pthu_bd_ctr_hside : 6; /* [27:22] */ + u32 csr_oq_dma_rcmd_pthu_en : 1; /* [28] */ + u32 rsv_3 : 2; /* [30:29] */ + u32 csr_oq_port_pthru_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_cfg_u; + +/* Define the union csr_oq_pthru_bd_ctr_win_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_win_len_nside : 10; /* [9:0] */ + u32 csr_oq_win_len_hside : 10; /* [19:10] */ + u32 rsv_4 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_win_cfg_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck0 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck1 : 12; /* [23:12] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg0_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck2 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck3 : 12; /* [23:12] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg1_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck4 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck5 : 12; /* [23:12] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg2_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck6 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck7 : 12; /* [23:12] */ + u32 rsv_8 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg3_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck8 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck9 : 12; /* [23:12] */ + u32 rsv_9 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg4_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck10 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck11 : 12; /* [23:12] */ + u32 rsv_10 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg5_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck12 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck13 : 12; /* [23:12] */ + u32 rsv_11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg6_u; + +/* Define the union csr_oq_fifo_af_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_nrq_af_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_hrq_af_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_mdp_drp_af_th : 5; /* [16:12] */ + u32 rsv_12 : 1; /* [17] */ + u32 csr_oq_sfifo_stlfq_fcnp_af_th : 5; /* [22:18] */ + u32 rsv_13 : 1; /* [23] */ + u32 csr_oq_sfifo_stffq0_fcnp_af_th : 5; /* [28:24] */ + u32 rsv_14 : 1; /* [29] */ + u32 rsv_15 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_af_cfg0_u; + +/* Define the union csr_oq_fifo_af_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stffq1_fcnp_af_th : 5; /* [4:0] */ + u32 rsv_16 : 1; /* [5] */ + u32 csr_oq_sfifo_stlfq_dsp_af_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_stffq0_dsp_af_th : 6; /* [17:12] */ + u32 csr_oq_sfifo_stffq1_dsp_af_th : 6; /* [23:18] */ + u32 csr_oq_sfifo_stliq_fp_af_th : 6; /* [29:24] */ + u32 rsv_17 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_af_cfg1_u; + +/* Define the union csr_oq_fifo_af_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stfiq_fp_af_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_stlfq_rep_af_th : 6; /* [11:6] */ + u32 rsv_18 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_af_cfg2_u; + +/* Define the union csr_oq_fifo_ae_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_nrq_ae_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_hrq_ae_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_mdp_drp_ae_th : 5; /* [16:12] */ + u32 rsv_19 : 1; /* [17] */ + u32 csr_oq_sfifo_stlfq_fcnp_ae_th : 5; /* [22:18] */ + u32 rsv_20 : 1; /* [23] */ + u32 csr_oq_sfifo_stffq0_fcnp_ae_th : 5; /* [28:24] */ + u32 rsv_21 : 1; /* [29] */ + u32 rsv_22 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_ae_cfg0_u; + +/* Define the union csr_oq_fifo_ae_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stffq1_fcnp_ae_th : 5; /* [4:0] */ + u32 rsv_23 : 1; /* [5] */ + u32 csr_oq_sfifo_stlfq_dsp_ae_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_stffq0_dsp_ae_th : 6; /* [17:12] */ + u32 csr_oq_sfifo_stffq1_dsp_ae_th : 6; /* [23:18] */ + u32 csr_oq_sfifo_stliq_fp_ae_th : 6; /* [29:24] */ + u32 rsv_24 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_ae_cfg1_u; + +/* Define the union csr_oq_fifo_ae_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stfiq_fp_ae_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_stlfq_rep_ae_th : 6; /* [11:6] */ + u32 rsv_25 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_ae_cfg2_u; + +/* Define the union csr_oq_hst01_coalescing_watermark_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst0_coalescing_watermark : 16; /* [15:0] */ + u32 csr_oq_hst1_coalescing_watermark : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst01_coalescing_watermark_u; + +/* Define the union csr_oq_hst23_coalescing_watermark_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst2_coalescing_watermark : 16; /* [15:0] */ + u32 csr_oq_hst3_coalescing_watermark : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst23_coalescing_watermark_u; + +/* Define the union csr_oq_hst0_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst0_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst0_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_hst1_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst1_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst1_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_hst2_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst2_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst2_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_hst3_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst3_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst3_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_aging_host_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_host_aging_rstep_len : 31; /* [30:0] */ + u32 csr_oq_host_aging_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_aging_host_cfg_u; + +/* Define the union csr_oq_aging_net_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_net_aging_rstep_len : 31; /* [30:0] */ + u32 csr_oq_net_aging_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_aging_net_cfg_u; + +/* Define the union csr_oq_wrr_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_wrr_stf_fq0_weight : 4; /* [3:0] */ + u32 csr_oq_wrr_stf_fq1_weight : 4; /* [7:4] */ + u32 csr_oq_wrr_stl_fq_weight : 4; /* [11:8] */ + u32 csr_oq_wrr_stf_iq_weight : 4; /* [15:12] */ + u32 csr_oq_wrr_stl_iq_weight : 4; /* [19:16] */ + u32 rsv_26 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_wrr_weight_cfg_u; + +/* Define the union csr_oq_nreal_deq_dpl_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_nreal_deq_dpl_len : 18; /* [17:0] */ + u32 rsv_27 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_nreal_deq_dpl_len_u; + +/* Define the union csr_oq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sample_mode : 1; /* [0] */ + u32 csr_oq_spec_port_en : 1; /* [1] */ + u32 csr_oq_done_clr : 1; /* [2] */ + u32 rsv_28 : 1; /* [3] */ + u32 csr_oq_spec_port_num : 4; /* [7:4] */ + u32 csr_oq_spec_pptr_typ : 10; /* [17:8] */ + u32 rsv_29 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_latency_cfg_u; + +/* Define the union csr_oq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_sample_done : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_latency_sta_u; + +/* Define the union csr_oq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_sample_tmr_u; + +/* Define the union csr_oq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_31 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_32 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int_vector_u; + +/* Define the union csr_oq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 7; /* [6:0] */ + u32 rsv_33 : 9; /* [15:7] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int_u; + +/* Define the union csr_oq_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 7; /* [6:0] */ + u32 rsv_34 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int_en_u; + +/* Define the union csr_oq_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_1bit_ecc_err : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 oq_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int0_sticky_u; + +/* Define the union csr_oq_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_2bit_ecc_err : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 oq_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int1_sticky_u; + +/* Define the union csr_oq_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_fifo_overflow : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 oq_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int2_sticky_u; + +/* Define the union csr_oq_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_fifo_underflow : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 oq_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int3_sticky_u; + +/* Define the union csr_oq_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_host_age_happen : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 oq_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int4_sticky_u; + +/* Define the union csr_oq_int5_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_network_age_happen : 1; /* [0] */ + u32 int_insrt5 : 1; /* [1] */ + u32 oq_int5_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int5_sticky_u; + +/* Define the union csr_oq_int6_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_empty_queue_deq_int : 1; /* [0] */ + u32 int_insrt6 : 1; /* [1] */ + u32 oq_int6_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int6_sticky_u; + +/* Define the union csr_oq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_ctrl_u; + +/* Define the union csr_oq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_timeout_u; + +/* Define the union csr_oq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat0_u; + +/* Define the union csr_oq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat1_u; + +/* Define the union csr_oq_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat2_u; + +/* Define the union csr_oq_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat3_u; + +/* Define the union csr_oq_fifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_fp_fifo_fill : 6; /* [5:0] */ + u32 stfiq_fp_fifo_fill : 6; /* [11:6] */ + u32 stffq0_dsp_fifo_fill : 6; /* [17:12] */ + u32 stffq1_dsp_fifo_fill : 6; /* [23:18] */ + u32 stlfq_dsp_fifo_fill : 6; /* [29:24] */ + u32 rsv_35 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_fill0_u; + +/* Define the union csr_oq_fifo_fill1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlfq_fcnp_fifo_fill : 5; /* [4:0] */ + u32 rsv_36 : 1; /* [5] */ + u32 mdp_fifo_fill : 5; /* [10:6] */ + u32 rsv_37 : 1; /* [11] */ + u32 nrq_fifo_fill : 6; /* [17:12] */ + u32 hrq_fifo_fill : 6; /* [23:18] */ + u32 stlfq_rep_fifo_fill : 6; /* [29:24] */ + u32 rsv_38 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_fill1_u; + +/* Define the union csr_oq_fifo_fill2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stffq0_fcnp_fifo_fill : 5; /* [4:0] */ + u32 rsv_39 : 1; /* [5] */ + u32 stffq1_fcnp_fifo_fill : 5; /* [10:6] */ + u32 rsv_40 : 1; /* [11] */ + u32 rsv_41 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_fill2_u; + +/* Define the union csr_oq_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_done : 1; /* [0] */ + u32 rsv_42 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mem_init_done_u; + +/* Define the union csr_oq_csr_stlfq_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stliq_fp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stliq_fp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stliq_fp_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_bi_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_bi_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_bi_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_bi_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_bi_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_bi_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_rep_info_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_rep_info_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_rep_info_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_rep_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_rep_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_rep_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_rep_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_rep_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_rep_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_rep_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_rep_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_rep_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lrep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lrep_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lrep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lrep_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lrep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lrep_cnt_u; + +/* Define the union csr_oq_csr_orep_rep_cnt_add_inc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_orep_rep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_orep_rep_cnt_add_inc_u; + +/* Define the union csr_oq_csr_orep_lrep_inc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_orep_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_orep_lrep_inc_u; + +/* Define the union csr_oq_csr_stlfq_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stliq_fp_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stliq_fp_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stliq_fp_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_mdp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_mdp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_mdp_packet_cnt_u; + +/* Define the union csr_oq_csr_hrq_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_hrq_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_hrq_packet_cnt_u; + +/* Define the union csr_oq_csr_hrq_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_hrq_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_hrq_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_nrq_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_nrq_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_nrq_packet_cnt_u; + +/* Define the union csr_oq_csr_rqc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_rqc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_rqc_cnt_u; + +/* Define the union csr_oq_csr_rqc_rvld_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_rqc_rvld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_rqc_rvld_cnt_u; + +/* Define the union csr_oq_csr_host_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_host_pthru_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_host_pthru_cnt_u; + +/* Define the union csr_oq_csr_network_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_network_pthru_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_network_pthru_cnt_u; + +/* Define the union csr_oq_csr_network_check_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_network_check_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_network_check_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_network_dissenq_drop_packet_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_network_dissenq_drop_packet : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_network_dissenq_drop_packet_u; + +/* Define the union csr_oq_csr_pie_check_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_pie_check_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_pie_check_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_host_dissenq_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_host_dissenq_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_host_dissenq_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_eqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_eqs_cnt_u; + +/* Define the union csr_oq_csr_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dqr_cnt_u; + +/* Define the union csr_oq_csr_not_real_deq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_not_real_deq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_not_real_deq_u; + +/* Define the union csr_oq_csr_deq_empty_queue_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_empty_queue : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_empty_queue_u; + +/* Define the union csr_oq_csr_deq_bp_by_prm_icd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_bp_by_prm_icd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_bp_by_prm_icd_u; + +/* Define the union csr_oq_csr_deq_bp_by_prm_dcd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_bp_by_prm_dcd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_bp_by_prm_dcd_u; + +/* Define the union csr_oq_csr_deq_bp_by_stfiq_lb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_bp_by_stfiq_lb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_bp_by_stfiq_lb_u; + +/* Define the union csr_oq_csr_stfiq_oq_fcnp_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_oq_fcnp_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_oq_fcnp_bp_cnt_u; + +/* Define the union csr_oq_csr_cpbtx_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_cpbtx_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_cpbtx_bp_cnt_u; + +/* Define the union csr_oq_csr_cpbrx_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_cpbrx_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_cpbrx_bp_cnt_u; + +/* Define the union csr_oq_csr_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dqs_cnt_u; + +/* Define the union csr_oq_csr_enq_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_2k_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_2k_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_2k_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_pie_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_pie_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_pie_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_ddr_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_ddr_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_ddr_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_loopback_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_loopback_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_loopback_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_network_4k_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_network_4k_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_network_4k_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_network_loopback_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_network_loopback_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_network_loopback_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_drop_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_drop_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_drop_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_tpd_to_citf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_tpd_to_citf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_tpd_to_citf_cnt_u; + +/* Define the union csr_oq_csr_tid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_tid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_tid_cnt_u; + +/* Define the union csr_oq_csr_stp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stp_cnt_u; + +/* Define the union csr_oq_csr_stffq0_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_fcnp_u; + +/* Define the union csr_oq_csr_stffq1_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_fcnp_u; + +/* Define the union csr_oq_csr_stlfq_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_fcnp_u; + +/* Define the union csr_oq_csr_oq_esch_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_oq_esch_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_oq_esch_fcnp_u; + +/* Define the union csr_oq_csr_oq_stfiq_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_oq_stfiq_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_oq_stfiq_fcnp_u; + +/* Define the union csr_oq_csr_epd_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_tso12_to_network_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_tso12_to_network_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_tso12_to_network_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_lro12_to_network_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro12_to_network_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro12_to_network_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_lro12_to_host_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro12_to_host_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro12_to_host_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_tso3_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_tso3_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_tso3_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_lro3_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro3_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro3_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_tso12_piece_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_tso12_piece_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_tso12_piece_cnt_u; + +/* Define the union csr_oq_csr_epd_lro12_piece_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro12_piece_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro12_piece_cnt_u; + +/* Define the union csr_oq_csr_epd_dmarcnd_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_dmarcnd_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_dmarcnd_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_rep_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_rep_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_rep_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_drop_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_drop_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_drop_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_dpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dpl_cnt_u; + +/* Define the union csr_oq_csr_olb_to_iq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_olb_to_iq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_olb_to_iq_cnt_u; + +/* Define the union csr_oq_csr_disable_epd_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_disable_epd_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_disable_epd_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_prls_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_prls_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_prls_cnt_u; + +/* Define the union csr_oq_csr_icd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_icd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_icd_cnt_u; + +/* Define the union csr_oq_csr_dcd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dcd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dcd_cnt_u; + +/* Define the union csr_oq_csr_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_pthru_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_pthru_cnt_u; + +/* Define the union csr_oq_mem_ecc_1bit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_mem_1bit_ecc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mem_ecc_1bit_cnt_u; + +/* Define the union csr_oq_csr_drop_queue_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_drop_queue_depth : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_drop_queue_depth_u; + +/* Define the union csr_oq_bp_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_oq_orep_bp : 1; /* [0] */ + u32 esch_qu_epd_bp_dps : 14; /* [14:1] */ + u32 cpb_oq_tx_bp : 1; /* [15] */ + u32 cpb_oq_rx_bp : 1; /* [16] */ + u32 iq_oq_olb_bp : 1; /* [17] */ + u32 stfiq_oq_fcnp_bp : 1; /* [18] */ + u32 cpb_qu_drp_bp : 1; /* [19] */ + u32 prm_oq_prls_bp : 1; /* [20] */ + u32 prm_oq_icd_q_fc_mux : 1; /* [21] */ + u32 prm_oq_icd_afull : 1; /* [22] */ + u32 prm_oq_dcd_afull : 1; /* [23] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_bp_status_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_oq_versions_u qu_versions; /* 0 */ + volatile csr_oq_mode_u oq_mode; /* 4 */ + volatile csr_oq_mode1_u oq_mode1; /* 8 */ + volatile csr_oq_desenq_cfg_u oq_desenq_cfg; /* C */ + volatile csr_oq_pthru_cfg_u oq_pthru_cfg; /* 10 */ + volatile csr_oq_pthru_bd_ctr_win_cfg_u oq_pthru_bd_ctr_win_cfg; /* 14 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg0_u oq_pthru_bd_ctr_max_pthu_cfg0; /* 18 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg1_u oq_pthru_bd_ctr_max_pthu_cfg1; /* 1C */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg2_u oq_pthru_bd_ctr_max_pthu_cfg2; /* 20 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg3_u oq_pthru_bd_ctr_max_pthu_cfg3; /* 24 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg4_u oq_pthru_bd_ctr_max_pthu_cfg4; /* 28 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg5_u oq_pthru_bd_ctr_max_pthu_cfg5; /* 2C */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg6_u oq_pthru_bd_ctr_max_pthu_cfg6; /* 30 */ + volatile csr_oq_fifo_af_cfg0_u oq_fifo_af_cfg0; /* 34 */ + volatile csr_oq_fifo_af_cfg1_u oq_fifo_af_cfg1; /* 38 */ + volatile csr_oq_fifo_af_cfg2_u oq_fifo_af_cfg2; /* 3C */ + volatile csr_oq_fifo_ae_cfg0_u oq_fifo_ae_cfg0; /* 40 */ + volatile csr_oq_fifo_ae_cfg1_u oq_fifo_ae_cfg1; /* 44 */ + volatile csr_oq_fifo_ae_cfg2_u oq_fifo_ae_cfg2; /* 48 */ + volatile csr_oq_hst01_coalescing_watermark_u oq_hst01_coalescing_watermark; /* 4C */ + volatile csr_oq_hst23_coalescing_watermark_u oq_hst23_coalescing_watermark; /* 50 */ + volatile csr_oq_hst0_coalescing_watchdog_exp_u oq_hst0_coalescing_watchdog_exp; /* 54 */ + volatile csr_oq_hst1_coalescing_watchdog_exp_u oq_hst1_coalescing_watchdog_exp; /* 58 */ + volatile csr_oq_hst2_coalescing_watchdog_exp_u oq_hst2_coalescing_watchdog_exp; /* 5C */ + volatile csr_oq_hst3_coalescing_watchdog_exp_u oq_hst3_coalescing_watchdog_exp; /* 60 */ + volatile csr_oq_aging_host_cfg_u oq_aging_host_cfg; /* 64 */ + volatile csr_oq_aging_net_cfg_u oq_aging_net_cfg; /* 68 */ + volatile csr_oq_wrr_weight_cfg_u oq_wrr_weight_cfg; /* 6C */ + volatile csr_oq_nreal_deq_dpl_len_u oq_nreal_deq_dpl_len; /* 70 */ + volatile csr_oq_latency_cfg_u oq_latency_cfg; /* 74 */ + volatile csr_oq_latency_sta_u oq_latency_sta; /* 78 */ + volatile csr_oq_sample_tmr_u oq_sample_tmr; /* 7C */ + volatile csr_oq_int_vector_u oq_int_vector; /* 84 */ + volatile csr_oq_int_u oq_int; /* 88 */ + volatile csr_oq_int_en_u oq_int_en; /* 8C */ + volatile csr_oq_int0_sticky_u oq_int0_sticky; /* 90 */ + volatile csr_oq_int1_sticky_u oq_int1_sticky; /* 94 */ + volatile csr_oq_int2_sticky_u oq_int2_sticky; /* 98 */ + volatile csr_oq_int3_sticky_u oq_int3_sticky; /* 9C */ + volatile csr_oq_int4_sticky_u oq_int4_sticky; /* A0 */ + volatile csr_oq_int5_sticky_u oq_int5_sticky; /* A4 */ + volatile csr_oq_int6_sticky_u oq_int6_sticky; /* A8 */ + volatile csr_oq_indrect_ctrl_u oq_indrect_ctrl; /* AC */ + volatile csr_oq_indrect_timeout_u oq_indrect_timeout; /* B0 */ + volatile csr_oq_indrect_dat0_u oq_indrect_dat0; /* B4 */ + volatile csr_oq_indrect_dat1_u oq_indrect_dat1; /* B8 */ + volatile csr_oq_indrect_dat2_u oq_indrect_dat2; /* BC */ + volatile csr_oq_indrect_dat3_u oq_indrect_dat3; /* C0 */ + volatile csr_oq_fifo_fill0_u oq_fifo_fill0; /* C4 */ + volatile csr_oq_fifo_fill1_u oq_fifo_fill1; /* C8 */ + volatile csr_oq_fifo_fill2_u oq_fifo_fill2; /* CC */ + volatile csr_oq_mem_init_done_u oq_mem_init_done; /* D0 */ + volatile csr_oq_csr_stlfq_dsp_packet_cnt_u oq_csr_stlfq_dsp_packet_cnt; /* D4 */ + volatile csr_oq_csr_stffq0_dsp_packet_cnt_u oq_csr_stffq0_dsp_packet_cnt; /* D8 */ + volatile csr_oq_csr_stffq1_dsp_packet_cnt_u oq_csr_stffq1_dsp_packet_cnt; /* DC */ + volatile csr_oq_csr_stliq_fp_packet_cnt_u oq_csr_stliq_fp_packet_cnt; /* E0 */ + volatile csr_oq_csr_stfiq_fp_packet_cnt_u oq_csr_stfiq_fp_packet_cnt; /* E4 */ + volatile csr_oq_csr_stffq0_bi_dsp_packet_cnt_u oq_csr_stffq0_bi_dsp_packet_cnt; /* E8 */ + volatile csr_oq_csr_stffq1_bi_dsp_packet_cnt_u oq_csr_stffq1_bi_dsp_packet_cnt; /* EC */ + volatile csr_oq_csr_stlfq_rep_info_cnt_u oq_csr_stlfq_rep_info_cnt; /* F0 */ + volatile csr_oq_csr_stlfq_dsp_tso12_packet_cnt_u oq_csr_stlfq_dsp_tso12_packet_cnt; /* F4 */ + volatile csr_oq_csr_stffq0_dsp_tso12_packet_cnt_u oq_csr_stffq0_dsp_tso12_packet_cnt; /* F8 */ + volatile csr_oq_csr_stffq1_dsp_tso12_packet_cnt_u oq_csr_stffq1_dsp_tso12_packet_cnt; /* FC */ + volatile csr_oq_csr_stfiq_fp_tso12_packet_cnt_u oq_csr_stfiq_fp_tso12_packet_cnt; /* 100 */ + volatile csr_oq_csr_stlfq_dsp_lro12_network_packet_cnt_u oq_csr_stlfq_dsp_lro12_network_packet_cnt; /* 104 */ + volatile csr_oq_csr_stffq0_dsp_lro12_network_packet_cnt_u oq_csr_stffq0_dsp_lro12_network_packet_cnt; /* 108 */ + volatile csr_oq_csr_stffq1_dsp_lro12_network_packet_cnt_u oq_csr_stffq1_dsp_lro12_network_packet_cnt; /* 10C */ + volatile csr_oq_csr_stfiq_fp_lro12_network_packet_cnt_u oq_csr_stfiq_fp_lro12_network_packet_cnt; /* 110 */ + volatile csr_oq_csr_stlfq_dsp_lro12_host_packet_cnt_u oq_csr_stlfq_dsp_lro12_host_packet_cnt; /* 114 */ + volatile csr_oq_csr_stffq0_dsp_lro12_host_packet_cnt_u oq_csr_stffq0_dsp_lro12_host_packet_cnt; /* 118 */ + volatile csr_oq_csr_stffq1_dsp_lro12_host_packet_cnt_u oq_csr_stffq1_dsp_lro12_host_packet_cnt; /* 11C */ + volatile csr_oq_csr_stfiq_fp_lro12_host_packet_cnt_u oq_csr_stfiq_fp_lro12_host_packet_cnt; /* 120 */ + volatile csr_oq_csr_stlfq_dsp_tso3_packet_cnt_u oq_csr_stlfq_dsp_tso3_packet_cnt; /* 124 */ + volatile csr_oq_csr_stffq0_dsp_tso3_packet_cnt_u oq_csr_stffq0_dsp_tso3_packet_cnt; /* 128 */ + volatile csr_oq_csr_stffq1_dsp_tso3_packet_cnt_u oq_csr_stffq1_dsp_tso3_packet_cnt; /* 12C */ + volatile csr_oq_csr_stfiq_fp_tso3_packet_cnt_u oq_csr_stfiq_fp_tso3_packet_cnt; /* 130 */ + volatile csr_oq_csr_stlfq_dsp_lro3_packet_cnt_u oq_csr_stlfq_dsp_lro3_packet_cnt; /* 134 */ + volatile csr_oq_csr_stffq0_dsp_lro3_packet_cnt_u oq_csr_stffq0_dsp_lro3_packet_cnt; /* 138 */ + volatile csr_oq_csr_stffq1_dsp_lro3_packet_cnt_u oq_csr_stffq1_dsp_lro3_packet_cnt; /* 13C */ + volatile csr_oq_csr_stfiq_fp_lro3_packet_cnt_u oq_csr_stfiq_fp_lro3_packet_cnt; /* 140 */ + volatile csr_oq_csr_stlfq_dsp_rep_packet_cnt_u oq_csr_stlfq_dsp_rep_packet_cnt; /* 144 */ + volatile csr_oq_csr_stffq0_dsp_rep_packet_cnt_u oq_csr_stffq0_dsp_rep_packet_cnt; /* 148 */ + volatile csr_oq_csr_stffq1_dsp_rep_packet_cnt_u oq_csr_stffq1_dsp_rep_packet_cnt; /* 14C */ + volatile csr_oq_csr_stlfq_dsp_lrep_cnt_u oq_csr_stlfq_dsp_lrep_cnt; /* 150 */ + volatile csr_oq_csr_stffq0_dsp_lrep_cnt_u oq_csr_stffq0_dsp_lrep_cnt; /* 154 */ + volatile csr_oq_csr_stffq1_dsp_lrep_cnt_u oq_csr_stffq1_dsp_lrep_cnt; /* 158 */ + volatile csr_oq_csr_orep_rep_cnt_add_inc_u oq_csr_orep_rep_cnt_add_inc; /* 15C */ + volatile csr_oq_csr_orep_lrep_inc_u oq_csr_orep_lrep_inc; /* 160 */ + volatile csr_oq_csr_stlfq_drop_packet_cnt_u oq_csr_stlfq_drop_packet_cnt; /* 164 */ + volatile csr_oq_csr_stffq0_drop_packet_cnt_u oq_csr_stffq0_drop_packet_cnt; /* 168 */ + volatile csr_oq_csr_stffq1_drop_packet_cnt_u oq_csr_stffq1_drop_packet_cnt; /* 16C */ + volatile csr_oq_csr_stliq_fp_drop_packet_cnt_u oq_csr_stliq_fp_drop_packet_cnt; /* 170 */ + volatile csr_oq_csr_stfiq_fp_drop_packet_cnt_u oq_csr_stfiq_fp_drop_packet_cnt; /* 174 */ + volatile csr_oq_csr_mdp_packet_cnt_u oq_csr_mdp_packet_cnt; /* 178 */ + volatile csr_oq_csr_hrq_packet_cnt_u oq_csr_hrq_packet_cnt; /* 17C */ + volatile csr_oq_csr_hrq_drop_packet_cnt_u oq_csr_hrq_drop_packet_cnt; /* 180 */ + volatile csr_oq_csr_nrq_packet_cnt_u oq_csr_nrq_packet_cnt; /* 184 */ + volatile csr_oq_csr_rqc_cnt_u oq_csr_rqc_cnt; /* 188 */ + volatile csr_oq_csr_rqc_rvld_cnt_u oq_csr_rqc_rvld_cnt; /* 18C */ + volatile csr_oq_csr_host_pthru_cnt_u oq_csr_host_pthru_cnt; /* 190 */ + volatile csr_oq_csr_network_pthru_cnt_u oq_csr_network_pthru_cnt; /* 194 */ + volatile csr_oq_csr_network_check_drop_packet_cnt_u oq_csr_network_check_drop_packet_cnt; /* 198 */ + volatile csr_oq_csr_network_dissenq_drop_packet_u oq_csr_network_dissenq_drop_packet; /* 19C */ + volatile csr_oq_csr_pie_check_drop_packet_cnt_u oq_csr_pie_check_drop_packet_cnt; /* 1A0 */ + volatile csr_oq_csr_host_dissenq_drop_packet_cnt_u oq_csr_host_dissenq_drop_packet_cnt; /* 1A4 */ + volatile csr_oq_csr_eqs_cnt_u oq_csr_eqs_cnt; /* 1A8 */ + volatile csr_oq_csr_dqr_cnt_u oq_csr_dqr_cnt; /* 1AC */ + volatile csr_oq_csr_not_real_deq_u oq_csr_not_real_deq; /* 1B0 */ + volatile csr_oq_csr_deq_empty_queue_u oq_csr_deq_empty_queue; /* 1B4 */ + volatile csr_oq_csr_deq_bp_by_prm_icd_u oq_csr_deq_bp_by_prm_icd; /* 1B8 */ + volatile csr_oq_csr_deq_bp_by_prm_dcd_u oq_csr_deq_bp_by_prm_dcd; /* 1BC */ + volatile csr_oq_csr_deq_bp_by_stfiq_lb_u oq_csr_deq_bp_by_stfiq_lb; /* 1C0 */ + volatile csr_oq_csr_stfiq_oq_fcnp_bp_cnt_u oq_csr_stfiq_oq_fcnp_bp_cnt; /* 1C4 */ + volatile csr_oq_csr_cpbtx_bp_cnt_u oq_csr_cpbtx_bp_cnt; /* 1C8 */ + volatile csr_oq_csr_cpbrx_bp_cnt_u oq_csr_cpbrx_bp_cnt; /* 1CC */ + volatile csr_oq_csr_dqs_cnt_u oq_csr_dqs_cnt; /* 1D0 */ + volatile csr_oq_csr_enq_packet_cnt_u oq_csr_enq_packet_cnt; /* 1D4 */ + volatile csr_oq_csr_enq_host_2k_queue_packet_cnt_u oq_csr_enq_host_2k_queue_packet_cnt; /* 1D8 */ + volatile csr_oq_csr_enq_host_pie_queue_packet_cnt_u oq_csr_enq_host_pie_queue_packet_cnt; /* 1DC */ + volatile csr_oq_csr_enq_host_ddr_queue_packet_cnt_u oq_csr_enq_host_ddr_queue_packet_cnt; /* 1E0 */ + volatile csr_oq_csr_enq_host_loopback_queue_packet_cnt_u oq_csr_enq_host_loopback_queue_packet_cnt; /* 1E4 */ + volatile csr_oq_csr_enq_network_4k_queue_packet_cnt_u oq_csr_enq_network_4k_queue_packet_cnt; /* 1E8 */ + volatile csr_oq_csr_enq_network_loopback_queue_packet_cnt_u oq_csr_enq_network_loopback_queue_packet_cnt; /* 1EC */ + volatile csr_oq_csr_enq_drop_queue_packet_cnt_u oq_csr_enq_drop_queue_packet_cnt; /* 1F0 */ + volatile csr_oq_csr_tpd_to_citf_cnt_u oq_csr_tpd_to_citf_cnt; /* 1F4 */ + volatile csr_oq_csr_tid_cnt_u oq_csr_tid_cnt; /* 1F8 */ + volatile csr_oq_csr_stp_cnt_u oq_csr_stp_cnt; /* 1FC */ + volatile csr_oq_csr_stffq0_fcnp_u oq_csr_stffq0_fcnp; /* 200 */ + volatile csr_oq_csr_stffq1_fcnp_u oq_csr_stffq1_fcnp; /* 204 */ + volatile csr_oq_csr_stlfq_fcnp_u oq_csr_stlfq_fcnp; /* 208 */ + volatile csr_oq_csr_oq_esch_fcnp_u oq_csr_oq_esch_fcnp; /* 20C */ + volatile csr_oq_csr_oq_stfiq_fcnp_u oq_csr_oq_stfiq_fcnp; /* 210 */ + volatile csr_oq_csr_epd_to_cpb_cnt_u oq_csr_epd_to_cpb_cnt; /* 214 */ + volatile csr_oq_csr_epd_tso12_to_network_cpb_cnt_u oq_csr_epd_tso12_to_network_cpb_cnt; /* 218 */ + volatile csr_oq_csr_epd_lro12_to_network_cpb_cnt_u oq_csr_epd_lro12_to_network_cpb_cnt; /* 21C */ + volatile csr_oq_csr_epd_lro12_to_host_cpb_cnt_u oq_csr_epd_lro12_to_host_cpb_cnt; /* 220 */ + volatile csr_oq_csr_epd_tso3_to_cpb_cnt_u oq_csr_epd_tso3_to_cpb_cnt; /* 224 */ + volatile csr_oq_csr_epd_lro3_to_cpb_cnt_u oq_csr_epd_lro3_to_cpb_cnt; /* 228 */ + volatile csr_oq_csr_epd_tso12_piece_cnt_u oq_csr_epd_tso12_piece_cnt; /* 22C */ + volatile csr_oq_csr_epd_lro12_piece_cnt_u oq_csr_epd_lro12_piece_cnt; /* 230 */ + volatile csr_oq_csr_epd_dmarcnd_to_cpb_cnt_u oq_csr_epd_dmarcnd_to_cpb_cnt; /* 234 */ + volatile csr_oq_csr_epd_rep_to_cpb_cnt_u oq_csr_epd_rep_to_cpb_cnt; /* 238 */ + volatile csr_oq_csr_drop_to_cpb_cnt_u oq_csr_drop_to_cpb_cnt; /* 23C */ + volatile csr_oq_csr_dpl_cnt_u oq_csr_dpl_cnt; /* 240 */ + volatile csr_oq_csr_olb_to_iq_cnt_u oq_csr_olb_to_iq_cnt; /* 244 */ + volatile csr_oq_csr_disable_epd_to_cpb_cnt_u oq_csr_disable_epd_to_cpb_cnt; /* 248 */ + volatile csr_oq_csr_prls_cnt_u oq_csr_prls_cnt; /* 24C */ + volatile csr_oq_csr_icd_cnt_u oq_csr_icd_cnt; /* 250 */ + volatile csr_oq_csr_dcd_cnt_u oq_csr_dcd_cnt; /* 254 */ + volatile csr_oq_csr_pthru_cnt_u oq_csr_pthru_cnt; /* 258 */ + volatile csr_oq_mem_ecc_1bit_cnt_u oq_mem_ecc_1bit_cnt; /* 25C */ + volatile csr_oq_csr_drop_queue_depth_u oq_csr_drop_queue_depth; /* 260 */ + volatile csr_oq_bp_status_u oq_bp_status; /* 264 */ +} S_qu_oq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_oq_csr */ +extern volatile S_qu_oq_csr_REGS_TYPE *gopqu_oq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetQU_VERSIONS_qu_version(unsigned int uqu_version); +int iSetOQ_MODE_csr_oq_other_uncrt_err2itf_en(unsigned int ucsr_oq_other_uncrt_err2itf_en); +int iSetOQ_MODE_csr_oq_ram_uncrt_err2itf_en(unsigned int ucsr_oq_ram_uncrt_err2itf_en); +int iSetOQ_MODE_csr_oq_mem_init_start(unsigned int ucsr_oq_mem_init_start); +int iSetOQ_MODE_csr_oq_mem_ecc_bypass(unsigned int ucsr_oq_mem_ecc_bypass); +int iSetOQ_MODE_csr_oq_mem_ecc_req(unsigned int ucsr_oq_mem_ecc_req); +int iSetOQ_MODE_csr_oq_net_loopback_pre_adj(unsigned int ucsr_oq_net_loopback_pre_adj); +int iSetOQ_MODE_csr_oq_net_loopback_prealloc_en(unsigned int ucsr_oq_net_loopback_prealloc_en); +int iSetOQ_MODE_csr_oq_hst_dma_coalescing_en(unsigned int ucsr_oq_hst_dma_coalescing_en); +int iSetOQ_MODE_csr_oq_dma_rcmd_prealloc_en(unsigned int ucsr_oq_dma_rcmd_prealloc_en); +int iSetOQ_MODE1_csr_oq_tpmem_timing_ctrl(unsigned int ucsr_oq_tpmem_timing_ctrl); +int iSetOQ_MODE1_csr_oq_spmem_timing_ctrl(unsigned int ucsr_oq_spmem_timing_ctrl); +int iSetOQ_MODE1_csr_oq_tpmem_power_ctrl(unsigned int ucsr_oq_tpmem_power_ctrl); +int iSetOQ_MODE1_csr_oq_spmem_power_ctrl(unsigned int ucsr_oq_spmem_power_ctrl); +int iSetOQ_DESENQ_CFG_csr_oq_disenq_oqid(unsigned int ucsr_oq_disenq_oqid); +int iSetOQ_DESENQ_CFG_csr_oq_disenq_en(unsigned int ucsr_oq_disenq_en); +int iSetOQ_PTHRU_CFG_csr_oq_port_pthru_nside(unsigned int ucsr_oq_port_pthru_nside); +int iSetOQ_PTHRU_CFG_csr_oq_port_pthru_hside(unsigned int ucsr_oq_port_pthru_hside); +int iSetOQ_PTHRU_CFG_csr_oq_pthu_bd_ctr_nside(unsigned int ucsr_oq_pthu_bd_ctr_nside); +int iSetOQ_PTHRU_CFG_csr_oq_pthu_bd_ctr_hside(unsigned int ucsr_oq_pthu_bd_ctr_hside); +int iSetOQ_PTHRU_CFG_csr_oq_dma_rcmd_pthu_en(unsigned int ucsr_oq_dma_rcmd_pthu_en); +int iSetOQ_PTHRU_CFG_csr_oq_port_pthru_en(unsigned int ucsr_oq_port_pthru_en); +int iSetOQ_PTHRU_BD_CTR_WIN_CFG_csr_oq_win_len_nside(unsigned int ucsr_oq_win_len_nside); +int iSetOQ_PTHRU_BD_CTR_WIN_CFG_csr_oq_win_len_hside(unsigned int ucsr_oq_win_len_hside); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG0_csr_oq_max_pthu_pck0(unsigned int ucsr_oq_max_pthu_pck0); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG0_csr_oq_max_pthu_pck1(unsigned int ucsr_oq_max_pthu_pck1); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG1_csr_oq_max_pthu_pck2(unsigned int ucsr_oq_max_pthu_pck2); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG1_csr_oq_max_pthu_pck3(unsigned int ucsr_oq_max_pthu_pck3); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG2_csr_oq_max_pthu_pck4(unsigned int ucsr_oq_max_pthu_pck4); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG2_csr_oq_max_pthu_pck5(unsigned int ucsr_oq_max_pthu_pck5); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG3_csr_oq_max_pthu_pck6(unsigned int ucsr_oq_max_pthu_pck6); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG3_csr_oq_max_pthu_pck7(unsigned int ucsr_oq_max_pthu_pck7); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG4_csr_oq_max_pthu_pck8(unsigned int ucsr_oq_max_pthu_pck8); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG4_csr_oq_max_pthu_pck9(unsigned int ucsr_oq_max_pthu_pck9); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG5_csr_oq_max_pthu_pck10(unsigned int ucsr_oq_max_pthu_pck10); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG5_csr_oq_max_pthu_pck11(unsigned int ucsr_oq_max_pthu_pck11); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG6_csr_oq_max_pthu_pck12(unsigned int ucsr_oq_max_pthu_pck12); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG6_csr_oq_max_pthu_pck13(unsigned int ucsr_oq_max_pthu_pck13); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_nrq_af_th(unsigned int ucsr_oq_sfifo_nrq_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_hrq_af_th(unsigned int ucsr_oq_sfifo_hrq_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_mdp_drp_af_th(unsigned int ucsr_oq_sfifo_mdp_drp_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_stlfq_fcnp_af_th(unsigned int ucsr_oq_sfifo_stlfq_fcnp_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_stffq0_fcnp_af_th(unsigned int ucsr_oq_sfifo_stffq0_fcnp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stffq1_fcnp_af_th(unsigned int ucsr_oq_sfifo_stffq1_fcnp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stlfq_dsp_af_th(unsigned int ucsr_oq_sfifo_stlfq_dsp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stffq0_dsp_af_th(unsigned int ucsr_oq_sfifo_stffq0_dsp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stffq1_dsp_af_th(unsigned int ucsr_oq_sfifo_stffq1_dsp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stliq_fp_af_th(unsigned int ucsr_oq_sfifo_stliq_fp_af_th); +int iSetOQ_FIFO_AF_CFG2_csr_oq_sfifo_stfiq_fp_af_th(unsigned int ucsr_oq_sfifo_stfiq_fp_af_th); +int iSetOQ_FIFO_AF_CFG2_csr_oq_sfifo_stlfq_rep_af_th(unsigned int ucsr_oq_sfifo_stlfq_rep_af_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_nrq_ae_th(unsigned int ucsr_oq_sfifo_nrq_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_hrq_ae_th(unsigned int ucsr_oq_sfifo_hrq_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_mdp_drp_ae_th(unsigned int ucsr_oq_sfifo_mdp_drp_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_stlfq_fcnp_ae_th(unsigned int ucsr_oq_sfifo_stlfq_fcnp_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_stffq0_fcnp_ae_th(unsigned int ucsr_oq_sfifo_stffq0_fcnp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stffq1_fcnp_ae_th(unsigned int ucsr_oq_sfifo_stffq1_fcnp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stlfq_dsp_ae_th(unsigned int ucsr_oq_sfifo_stlfq_dsp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stffq0_dsp_ae_th(unsigned int ucsr_oq_sfifo_stffq0_dsp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stffq1_dsp_ae_th(unsigned int ucsr_oq_sfifo_stffq1_dsp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stliq_fp_ae_th(unsigned int ucsr_oq_sfifo_stliq_fp_ae_th); +int iSetOQ_FIFO_AE_CFG2_csr_oq_sfifo_stfiq_fp_ae_th(unsigned int ucsr_oq_sfifo_stfiq_fp_ae_th); +int iSetOQ_FIFO_AE_CFG2_csr_oq_sfifo_stlfq_rep_ae_th(unsigned int ucsr_oq_sfifo_stlfq_rep_ae_th); +int iSetOQ_HST01_COALESCING_WATERMARK_csr_oq_hst0_coalescing_watermark(unsigned int ucsr_oq_hst0_coalescing_watermark); +int iSetOQ_HST01_COALESCING_WATERMARK_csr_oq_hst1_coalescing_watermark(unsigned int ucsr_oq_hst1_coalescing_watermark); +int iSetOQ_HST23_COALESCING_WATERMARK_csr_oq_hst2_coalescing_watermark(unsigned int ucsr_oq_hst2_coalescing_watermark); +int iSetOQ_HST23_COALESCING_WATERMARK_csr_oq_hst3_coalescing_watermark(unsigned int ucsr_oq_hst3_coalescing_watermark); +int iSetOQ_HST0_COALESCING_WATCHDOG_EXP_csr_oq_hst0_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst0_coalescing_watchdog_exp); +int iSetOQ_HST1_COALESCING_WATCHDOG_EXP_csr_oq_hst1_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst1_coalescing_watchdog_exp); +int iSetOQ_HST2_COALESCING_WATCHDOG_EXP_csr_oq_hst2_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst2_coalescing_watchdog_exp); +int iSetOQ_HST3_COALESCING_WATCHDOG_EXP_csr_oq_hst3_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst3_coalescing_watchdog_exp); +int iSetOQ_AGING_HOST_CFG_csr_oq_host_aging_rstep_len(unsigned int ucsr_oq_host_aging_rstep_len); +int iSetOQ_AGING_HOST_CFG_csr_oq_host_aging_en(unsigned int ucsr_oq_host_aging_en); +int iSetOQ_AGING_NET_CFG_csr_oq_net_aging_rstep_len(unsigned int ucsr_oq_net_aging_rstep_len); +int iSetOQ_AGING_NET_CFG_csr_oq_net_aging_en(unsigned int ucsr_oq_net_aging_en); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stf_fq0_weight(unsigned int ucsr_oq_wrr_stf_fq0_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stf_fq1_weight(unsigned int ucsr_oq_wrr_stf_fq1_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stl_fq_weight(unsigned int ucsr_oq_wrr_stl_fq_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stf_iq_weight(unsigned int ucsr_oq_wrr_stf_iq_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stl_iq_weight(unsigned int ucsr_oq_wrr_stl_iq_weight); +int iSetOQ_NREAL_DEQ_DPL_LEN_csr_oq_nreal_deq_dpl_len(unsigned int ucsr_oq_nreal_deq_dpl_len); +int iSetOQ_LATENCY_CFG_csr_oq_sample_mode(unsigned int ucsr_oq_sample_mode); +int iSetOQ_LATENCY_CFG_csr_oq_spec_port_en(unsigned int ucsr_oq_spec_port_en); +int iSetOQ_LATENCY_CFG_csr_oq_done_clr(unsigned int ucsr_oq_done_clr); +int iSetOQ_LATENCY_CFG_csr_oq_spec_port_num(unsigned int ucsr_oq_spec_port_num); +int iSetOQ_LATENCY_CFG_csr_oq_spec_pptr_typ(unsigned int ucsr_oq_spec_pptr_typ); +int iSetOQ_LATENCY_STA_oq_csr_sample_done(unsigned int uoq_csr_sample_done); +int iSetOQ_SAMPLE_TMR_oq_csr_sample_tmr(unsigned int uoq_csr_sample_tmr); +int iSetOQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetOQ_INT_VECTOR_enable(unsigned int uenable); +int iSetOQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetOQ_INT_int_data(unsigned int uint_data); +int iSetOQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetOQ_INT_EN_int_en(unsigned int uint_en); +int iSetOQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetOQ_INT0_STICKY_oq_1bit_ecc_err(unsigned int uoq_1bit_ecc_err); +int iSetOQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetOQ_INT0_STICKY_oq_int0_sticky(unsigned int uoq_int0_sticky); +int iSetOQ_INT1_STICKY_oq_2bit_ecc_err(unsigned int uoq_2bit_ecc_err); +int iSetOQ_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetOQ_INT1_STICKY_oq_int1_sticky(unsigned int uoq_int1_sticky); +int iSetOQ_INT2_STICKY_oq_fifo_overflow(unsigned int uoq_fifo_overflow); +int iSetOQ_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetOQ_INT2_STICKY_oq_int2_sticky(unsigned int uoq_int2_sticky); +int iSetOQ_INT3_STICKY_oq_fifo_underflow(unsigned int uoq_fifo_underflow); +int iSetOQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetOQ_INT3_STICKY_oq_int3_sticky(unsigned int uoq_int3_sticky); +int iSetOQ_INT4_STICKY_oq_host_age_happen(unsigned int uoq_host_age_happen); +int iSetOQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4); +int iSetOQ_INT4_STICKY_oq_int4_sticky(unsigned int uoq_int4_sticky); +int iSetOQ_INT5_STICKY_oq_network_age_happen(unsigned int uoq_network_age_happen); +int iSetOQ_INT5_STICKY_int_insrt5(unsigned int uint_insrt5); +int iSetOQ_INT5_STICKY_oq_int5_sticky(unsigned int uoq_int5_sticky); +int iSetOQ_INT6_STICKY_oq_empty_queue_deq_int(unsigned int uoq_empty_queue_deq_int); +int iSetOQ_INT6_STICKY_int_insrt6(unsigned int uint_insrt6); +int iSetOQ_INT6_STICKY_oq_int6_sticky(unsigned int uoq_int6_sticky); +int iSetOQ_INDRECT_CTRL_csr_oq_indrect_ctrl(unsigned int ucsr_oq_indrect_ctrl); +int iSetOQ_INDRECT_TIMEOUT_csr_oq_indrect_timeout(unsigned int ucsr_oq_indrect_timeout); +int iSetOQ_INDRECT_DAT0_csr_oq_indrect_data0(unsigned int ucsr_oq_indrect_data0); +int iSetOQ_INDRECT_DAT1_csr_oq_indrect_data1(unsigned int ucsr_oq_indrect_data1); +int iSetOQ_INDRECT_DAT2_csr_oq_indrect_data2(unsigned int ucsr_oq_indrect_data2); +int iSetOQ_INDRECT_DAT3_csr_oq_indrect_data3(unsigned int ucsr_oq_indrect_data3); +int iSetOQ_FIFO_FILL0_stliq_fp_fifo_fill(unsigned int ustliq_fp_fifo_fill); +int iSetOQ_FIFO_FILL0_stfiq_fp_fifo_fill(unsigned int ustfiq_fp_fifo_fill); +int iSetOQ_FIFO_FILL0_stffq0_dsp_fifo_fill(unsigned int ustffq0_dsp_fifo_fill); +int iSetOQ_FIFO_FILL0_stffq1_dsp_fifo_fill(unsigned int ustffq1_dsp_fifo_fill); +int iSetOQ_FIFO_FILL0_stlfq_dsp_fifo_fill(unsigned int ustlfq_dsp_fifo_fill); +int iSetOQ_FIFO_FILL1_stlfq_fcnp_fifo_fill(unsigned int ustlfq_fcnp_fifo_fill); +int iSetOQ_FIFO_FILL1_mdp_fifo_fill(unsigned int umdp_fifo_fill); +int iSetOQ_FIFO_FILL1_nrq_fifo_fill(unsigned int unrq_fifo_fill); +int iSetOQ_FIFO_FILL1_hrq_fifo_fill(unsigned int uhrq_fifo_fill); +int iSetOQ_FIFO_FILL1_stlfq_rep_fifo_fill(unsigned int ustlfq_rep_fifo_fill); +int iSetOQ_FIFO_FILL2_stffq0_fcnp_fifo_fill(unsigned int ustffq0_fcnp_fifo_fill); +int iSetOQ_FIFO_FILL2_stffq1_fcnp_fifo_fill(unsigned int ustffq1_fcnp_fifo_fill); +int iSetOQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done); +int iSetOQ_CSR_STLFQ_DSP_PACKET_CNT_oq_csr_stlfq_dsp_packet_cnt(unsigned int uoq_csr_stlfq_dsp_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_PACKET_CNT_oq_csr_stffq0_dsp_packet_cnt(unsigned int uoq_csr_stffq0_dsp_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_PACKET_CNT_oq_csr_stffq1_dsp_packet_cnt(unsigned int uoq_csr_stffq1_dsp_packet_cnt); +int iSetOQ_CSR_STLIQ_FP_PACKET_CNT_oq_csr_stliq_fp_packet_cnt(unsigned int uoq_csr_stliq_fp_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_PACKET_CNT_oq_csr_stfiq_fp_packet_cnt(unsigned int uoq_csr_stfiq_fp_packet_cnt); +int iSetOQ_CSR_STFFQ0_BI_DSP_PACKET_CNT_oq_csr_stffq0_bi_dsp_packet_cnt(unsigned int uoq_csr_stffq0_bi_dsp_packet_cnt); +int iSetOQ_CSR_STFFQ1_BI_DSP_PACKET_CNT_oq_csr_stffq1_bi_dsp_packet_cnt(unsigned int uoq_csr_stffq1_bi_dsp_packet_cnt); +int iSetOQ_CSR_STLFQ_REP_INFO_CNT_oq_csr_stlfq_rep_info_cnt(unsigned int uoq_csr_stlfq_rep_info_cnt); +int iSetOQ_CSR_STLFQ_DSP_TSO12_PACKET_CNT_oq_csr_stlfq_dsp_tso12_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_tso12_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_TSO12_PACKET_CNT_oq_csr_stffq0_dsp_tso12_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_tso12_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_TSO12_PACKET_CNT_oq_csr_stffq1_dsp_tso12_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_tso12_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_TSO12_PACKET_CNT_oq_csr_stfiq_fp_tso12_packet_cnt( + unsigned int uoq_csr_stfiq_fp_tso12_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LRO12_NETWORK_PACKET_CNT_oq_csr_stlfq_dsp_lro12_network_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_lro12_network_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LRO12_NETWORK_PACKET_CNT_oq_csr_stffq0_dsp_lro12_network_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_lro12_network_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LRO12_NETWORK_PACKET_CNT_oq_csr_stffq1_dsp_lro12_network_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_lro12_network_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_LRO12_NETWORK_PACKET_CNT_oq_csr_stfiq_fp_lro12_network_packet_cnt( + unsigned int uoq_csr_stfiq_fp_lro12_network_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LRO12_HOST_PACKET_CNT_oq_csr_stlfq_dsp_lro12_host_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_lro12_host_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LRO12_HOST_PACKET_CNT_oq_csr_stffq0_dsp_lro12_host_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_lro12_host_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LRO12_HOST_PACKET_CNT_oq_csr_stffq1_dsp_lro12_host_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_lro12_host_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_LRO12_HOST_PACKET_CNT_oq_csr_stfiq_fp_lro12_host_packet_cnt( + unsigned int uoq_csr_stfiq_fp_lro12_host_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_TSO3_PACKET_CNT_oq_csr_stlfq_dsp_tso3_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_tso3_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_TSO3_PACKET_CNT_oq_csr_stffq0_dsp_tso3_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_tso3_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_TSO3_PACKET_CNT_oq_csr_stffq1_dsp_tso3_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_tso3_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_TSO3_PACKET_CNT_oq_csr_stfiq_fp_tso3_packet_cnt(unsigned int uoq_csr_stfiq_fp_tso3_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LRO3_PACKET_CNT_oq_csr_stlfq_dsp_lro3_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_lro3_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LRO3_PACKET_CNT_oq_csr_stffq0_dsp_lro3_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_lro3_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LRO3_PACKET_CNT_oq_csr_stffq1_dsp_lro3_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_lro3_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_LRO3_PACKET_CNT_oq_csr_stfiq_fp_lro3_packet_cnt(unsigned int uoq_csr_stfiq_fp_lro3_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_REP_PACKET_CNT_oq_csr_stlfq_dsp_rep_packet_cnt(unsigned int uoq_csr_stlfq_dsp_rep_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_REP_PACKET_CNT_oq_csr_stffq0_dsp_rep_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_rep_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_REP_PACKET_CNT_oq_csr_stffq1_dsp_rep_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_rep_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LREP_CNT_oq_csr_stlfq_dsp_lrep_cnt(unsigned int uoq_csr_stlfq_dsp_lrep_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LREP_CNT_oq_csr_stffq0_dsp_lrep_cnt(unsigned int uoq_csr_stffq0_dsp_lrep_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LREP_CNT_oq_csr_stffq1_dsp_lrep_cnt(unsigned int uoq_csr_stffq1_dsp_lrep_cnt); +int iSetOQ_CSR_OREP_REP_CNT_ADD_INC_oq_csr_orep_rep_cnt(unsigned int uoq_csr_orep_rep_cnt); +int iSetOQ_CSR_OREP_LREP_INC_oq_csr_orep_lrep_cnt(unsigned int uoq_csr_orep_lrep_cnt); +int iSetOQ_CSR_STLFQ_DROP_PACKET_CNT_oq_csr_stlfq_drop_packet_cnt(unsigned int uoq_csr_stlfq_drop_packet_cnt); +int iSetOQ_CSR_STFFQ0_DROP_PACKET_CNT_oq_csr_stffq0_drop_packet_cnt(unsigned int uoq_csr_stffq0_drop_packet_cnt); +int iSetOQ_CSR_STFFQ1_DROP_PACKET_CNT_oq_csr_stffq1_drop_packet_cnt(unsigned int uoq_csr_stffq1_drop_packet_cnt); +int iSetOQ_CSR_STLIQ_FP_DROP_PACKET_CNT_oq_csr_stliq_fp_drop_packet_cnt(unsigned int uoq_csr_stliq_fp_drop_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_DROP_PACKET_CNT_oq_csr_stfiq_fp_drop_packet_cnt(unsigned int uoq_csr_stfiq_fp_drop_packet_cnt); +int iSetOQ_CSR_MDP_PACKET_CNT_oq_csr_mdp_packet_cnt(unsigned int uoq_csr_mdp_packet_cnt); +int iSetOQ_CSR_HRQ_PACKET_CNT_oq_csr_hrq_packet_cnt(unsigned int uoq_csr_hrq_packet_cnt); +int iSetOQ_CSR_HRQ_DROP_PACKET_CNT_oq_csr_hrq_drop_packet_cnt(unsigned int uoq_csr_hrq_drop_packet_cnt); +int iSetOQ_CSR_NRQ_PACKET_CNT_oq_csr_nrq_packet_cnt(unsigned int uoq_csr_nrq_packet_cnt); +int iSetOQ_CSR_RQC_CNT_oq_csr_rqc_cnt(unsigned int uoq_csr_rqc_cnt); +int iSetOQ_CSR_RQC_RVLD_CNT_oq_csr_rqc_rvld_cnt(unsigned int uoq_csr_rqc_rvld_cnt); +int iSetOQ_CSR_HOST_PTHRU_CNT_oq_csr_host_pthru_cnt(unsigned int uoq_csr_host_pthru_cnt); +int iSetOQ_CSR_NETWORK_PTHRU_CNT_oq_csr_network_pthru_cnt(unsigned int uoq_csr_network_pthru_cnt); +int iSetOQ_CSR_NETWORK_CHECK_DROP_PACKET_CNT_oq_csr_network_check_drop_packet_cnt( + unsigned int uoq_csr_network_check_drop_packet_cnt); +int iSetOQ_CSR_NETWORK_DISSENQ_DROP_PACKET_oq_csr_network_dissenq_drop_packet( + unsigned int uoq_csr_network_dissenq_drop_packet); +int iSetOQ_CSR_PIE_CHECK_DROP_PACKET_CNT_oq_csr_pie_check_drop_packet_cnt( + unsigned int uoq_csr_pie_check_drop_packet_cnt); +int iSetOQ_CSR_HOST_DISSENQ_DROP_PACKET_CNT_oq_csr_host_dissenq_drop_packet_cnt( + unsigned int uoq_csr_host_dissenq_drop_packet_cnt); +int iSetOQ_CSR_EQS_CNT_oq_csr_eqs_cnt(unsigned int uoq_csr_eqs_cnt); +int iSetOQ_CSR_DQR_CNT_oq_csr_dqr_cnt(unsigned int uoq_csr_dqr_cnt); +int iSetOQ_CSR_NOT_REAL_DEQ_oq_csr_not_real_deq(unsigned int uoq_csr_not_real_deq); +int iSetOQ_CSR_DEQ_EMPTY_QUEUE_oq_csr_deq_empty_queue(unsigned int uoq_csr_deq_empty_queue); +int iSetOQ_CSR_DEQ_BP_BY_PRM_ICD_oq_csr_deq_bp_by_prm_icd(unsigned int uoq_csr_deq_bp_by_prm_icd); +int iSetOQ_CSR_DEQ_BP_BY_PRM_DCD_oq_csr_deq_bp_by_prm_dcd(unsigned int uoq_csr_deq_bp_by_prm_dcd); +int iSetOQ_CSR_DEQ_BP_BY_STFIQ_LB_oq_csr_deq_bp_by_stfiq_lb(unsigned int uoq_csr_deq_bp_by_stfiq_lb); +int iSetOQ_CSR_STFIQ_OQ_FCNP_BP_CNT_oq_csr_stfiq_oq_fcnp_bp_cnt(unsigned int uoq_csr_stfiq_oq_fcnp_bp_cnt); +int iSetOQ_CSR_CPBTX_BP_CNT_oq_csr_cpbtx_bp_cnt(unsigned int uoq_csr_cpbtx_bp_cnt); +int iSetOQ_CSR_CPBRX_BP_CNT_oq_csr_cpbrx_bp_cnt(unsigned int uoq_csr_cpbrx_bp_cnt); +int iSetOQ_CSR_DQS_CNT_oq_csr_dqs_cnt(unsigned int uoq_csr_dqs_cnt); +int iSetOQ_CSR_ENQ_PACKET_CNT_oq_csr_enq_packet_cnt(unsigned int uoq_csr_enq_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_2K_QUEUE_PACKET_CNT_oq_csr_enq_host_2k_queue_packet_cnt( + unsigned int uoq_csr_enq_host_2k_queue_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_PIE_QUEUE_PACKET_CNT_oq_csr_enq_host_pie_queue_packet_cnt( + unsigned int uoq_csr_enq_host_pie_queue_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_DDR_QUEUE_PACKET_CNT_oq_csr_enq_host_ddr_queue_packet_cnt( + unsigned int uoq_csr_enq_host_ddr_queue_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_LOOPBACK_QUEUE_PACKET_CNT_oq_csr_enq_host_loopback_queue_packet_cnt( + unsigned int uoq_csr_enq_host_loopback_queue_packet_cnt); +int iSetOQ_CSR_ENQ_NETWORK_4K_QUEUE_PACKET_CNT_oq_csr_enq_network_4k_queue_packet_cnt( + unsigned int uoq_csr_enq_network_4k_queue_packet_cnt); +int iSetOQ_CSR_ENQ_NETWORK_LOOPBACK_QUEUE_PACKET_CNT_oq_csr_enq_network_loopback_queue_packet_cnt( + unsigned int uoq_csr_enq_network_loopback_queue_packet_cnt); +int iSetOQ_CSR_ENQ_DROP_QUEUE_PACKET_CNT_oq_csr_enq_drop_queue_packet_cnt( + unsigned int uoq_csr_enq_drop_queue_packet_cnt); +int iSetOQ_CSR_TPD_TO_CITF_CNT_oq_csr_tpd_to_citf_cnt(unsigned int uoq_csr_tpd_to_citf_cnt); +int iSetOQ_CSR_TID_CNT_oq_csr_tid_cnt(unsigned int uoq_csr_tid_cnt); +int iSetOQ_CSR_STP_CNT_oq_csr_stp_cnt(unsigned int uoq_csr_stp_cnt); +int iSetOQ_CSR_STFFQ0_FCNP_oq_csr_stffq0_fcnp(unsigned int uoq_csr_stffq0_fcnp); +int iSetOQ_CSR_STFFQ1_FCNP_oq_csr_stffq1_fcnp(unsigned int uoq_csr_stffq1_fcnp); +int iSetOQ_CSR_STLFQ_FCNP_oq_csr_stlfq_fcnp(unsigned int uoq_csr_stlfq_fcnp); +int iSetOQ_CSR_OQ_ESCH_FCNP_oq_csr_oq_esch_fcnp(unsigned int uoq_csr_oq_esch_fcnp); +int iSetOQ_CSR_OQ_STFIQ_FCNP_oq_csr_oq_stfiq_fcnp(unsigned int uoq_csr_oq_stfiq_fcnp); +int iSetOQ_CSR_EPD_TO_CPB_CNT_oq_csr_epd_to_cpb_cnt(unsigned int uoq_csr_epd_to_cpb_cnt); +int iSetOQ_CSR_EPD_TSO12_TO_NETWORK_CPB_CNT_oq_csr_epd_tso12_to_network_cpb_cnt( + unsigned int uoq_csr_epd_tso12_to_network_cpb_cnt); +int iSetOQ_CSR_EPD_LRO12_TO_NETWORK_CPB_CNT_oq_csr_epd_lro12_to_network_cpb_cnt( + unsigned int uoq_csr_epd_lro12_to_network_cpb_cnt); +int iSetOQ_CSR_EPD_LRO12_TO_HOST_CPB_CNT_oq_csr_epd_lro12_to_host_cpb_cnt( + unsigned int uoq_csr_epd_lro12_to_host_cpb_cnt); +int iSetOQ_CSR_EPD_TSO3_TO_CPB_CNT_oq_csr_epd_tso3_to_cpb_cnt(unsigned int uoq_csr_epd_tso3_to_cpb_cnt); +int iSetOQ_CSR_EPD_LRO3_TO_CPB_CNT_oq_csr_epd_lro3_to_cpb_cnt(unsigned int uoq_csr_epd_lro3_to_cpb_cnt); +int iSetOQ_CSR_EPD_TSO12_PIECE_CNT_oq_csr_epd_tso12_piece_cnt(unsigned int uoq_csr_epd_tso12_piece_cnt); +int iSetOQ_CSR_EPD_LRO12_PIECE_CNT_oq_csr_epd_lro12_piece_cnt(unsigned int uoq_csr_epd_lro12_piece_cnt); +int iSetOQ_CSR_EPD_DMARCND_TO_CPB_CNT_oq_csr_epd_dmarcnd_to_cpb_cnt(unsigned int uoq_csr_epd_dmarcnd_to_cpb_cnt); +int iSetOQ_CSR_EPD_REP_TO_CPB_CNT_oq_csr_epd_rep_to_cpb_cnt(unsigned int uoq_csr_epd_rep_to_cpb_cnt); +int iSetOQ_CSR_DROP_TO_CPB_CNT_oq_csr_drop_to_cpb_cnt(unsigned int uoq_csr_drop_to_cpb_cnt); +int iSetOQ_CSR_DPL_CNT_oq_csr_dpl_cnt(unsigned int uoq_csr_dpl_cnt); +int iSetOQ_CSR_OLB_TO_IQ_CNT_oq_csr_olb_to_iq_cnt(unsigned int uoq_csr_olb_to_iq_cnt); +int iSetOQ_CSR_DISABLE_EPD_TO_CPB_CNT_oq_csr_disable_epd_to_cpb_cnt(unsigned int uoq_csr_disable_epd_to_cpb_cnt); +int iSetOQ_CSR_PRLS_CNT_oq_csr_prls_cnt(unsigned int uoq_csr_prls_cnt); +int iSetOQ_CSR_ICD_CNT_oq_csr_icd_cnt(unsigned int uoq_csr_icd_cnt); +int iSetOQ_CSR_DCD_CNT_oq_csr_dcd_cnt(unsigned int uoq_csr_dcd_cnt); +int iSetOQ_CSR_PTHRU_CNT_oq_csr_pthru_cnt(unsigned int uoq_csr_pthru_cnt); +int iSetOQ_MEM_ECC_1BIT_CNT_oq_csr_mem_1bit_ecc(unsigned int uoq_csr_mem_1bit_ecc); +int iSetOQ_CSR_DROP_QUEUE_DEPTH_oq_csr_drop_queue_depth(unsigned int uoq_csr_drop_queue_depth); +int iSetOQ_BP_STATUS_prm_oq_orep_bp(unsigned int uprm_oq_orep_bp); +int iSetOQ_BP_STATUS_esch_qu_epd_bp_dps(unsigned int uesch_qu_epd_bp_dps); +int iSetOQ_BP_STATUS_cpb_oq_tx_bp(unsigned int ucpb_oq_tx_bp); +int iSetOQ_BP_STATUS_cpb_oq_rx_bp(unsigned int ucpb_oq_rx_bp); +int iSetOQ_BP_STATUS_iq_oq_olb_bp(unsigned int uiq_oq_olb_bp); +int iSetOQ_BP_STATUS_stfiq_oq_fcnp_bp(unsigned int ustfiq_oq_fcnp_bp); +int iSetOQ_BP_STATUS_cpb_qu_drp_bp(unsigned int ucpb_qu_drp_bp); +int iSetOQ_BP_STATUS_prm_oq_prls_bp(unsigned int uprm_oq_prls_bp); +int iSetOQ_BP_STATUS_prm_oq_icd_q_fc_mux(unsigned int uprm_oq_icd_q_fc_mux); +int iSetOQ_BP_STATUS_prm_oq_icd_afull(unsigned int uprm_oq_icd_afull); +int iSetOQ_BP_STATUS_prm_oq_dcd_afull(unsigned int uprm_oq_dcd_afull); + + +#endif // OQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_reg_offset.h new file mode 100644 index 000000000..b76cbd6a6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_reg_offset.h @@ -0,0 +1,261 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : oq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:07:14 Create file +// ****************************************************************************** + +#ifndef OQ_REG_OFFSET_H +#define OQ_REG_OFFSET_H + +/* QU_OQ_CSR Base address of Module's Register */ +#define CSR_QU_OQ_CSR_BASE (0x8000) + +/* **************************************************************************** */ +/* QU_OQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_OQ_CSR_QU_VERSIONS_REG (CSR_QU_OQ_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_QU_OQ_CSR_OQ_MODE_REG (CSR_QU_OQ_CSR_BASE + 0x4) /* OQ operation mode register */ +#define CSR_QU_OQ_CSR_OQ_MODE1_REG (CSR_QU_OQ_CSR_BASE + 0x8) /* OQ operation mode register */ +#define CSR_QU_OQ_CSR_OQ_DESENQ_CFG_REG (CSR_QU_OQ_CSR_BASE + 0xC) /* disable队列配置 */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x10) /* pass-through配置 */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_WIN_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x14) /* pass-through带宽限制窗口配置 */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG0_REG \ + (CSR_QU_OQ_CSR_BASE + 0x18) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG1_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG2_REG \ + (CSR_QU_OQ_CSR_BASE + 0x20) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG3_REG \ + (CSR_QU_OQ_CSR_BASE + 0x24) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG4_REG \ + (CSR_QU_OQ_CSR_BASE + 0x28) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG5_REG \ + (CSR_QU_OQ_CSR_BASE + 0x2C) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG6_REG \ + (CSR_QU_OQ_CSR_BASE + 0x30) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AF_CFG0_REG (CSR_QU_OQ_CSR_BASE + 0x34) /* oq fifo almost-full waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AF_CFG1_REG (CSR_QU_OQ_CSR_BASE + 0x38) /* oq fifo almost-full waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AF_CFG2_REG (CSR_QU_OQ_CSR_BASE + 0x3C) /* oq fifo almost-full waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AE_CFG0_REG (CSR_QU_OQ_CSR_BASE + 0x40) /* oq fifo almost-empty waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AE_CFG1_REG (CSR_QU_OQ_CSR_BASE + 0x44) /* oq fifo almost-empty waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AE_CFG2_REG (CSR_QU_OQ_CSR_BASE + 0x48) /* oq fifo almost-empty waterline config */ +#define CSR_QU_OQ_CSR_OQ_HST01_COALESCING_WATERMARK_REG (CSR_QU_OQ_CSR_BASE + 0x4C) /* OQ_HST01_COALESCING_WATERMARK \ + */ +#define CSR_QU_OQ_CSR_OQ_HST23_COALESCING_WATERMARK_REG (CSR_QU_OQ_CSR_BASE + 0x50) /* OQ_HST23_COALESCING_WATERMARK \ + */ +#define CSR_QU_OQ_CSR_OQ_HST0_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x54) /* OQ_HST0_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_HST1_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x58) /* OQ_HST1_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_HST2_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x5C) /* OQ_HST2_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_HST3_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x60) /* OQ_HST3_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_AGING_HOST_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x64) /* OQ_AGING_HOST_CFG */ +#define CSR_QU_OQ_CSR_OQ_AGING_NET_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x68) /* 网络侧队列老化配置 */ +#define CSR_QU_OQ_CSR_OQ_WRR_WEIGHT_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x6C) /* OQ入口的WRR权重配置 */ +#define CSR_QU_OQ_CSR_OQ_NREAL_DEQ_DPL_LEN_REG \ + (CSR_QU_OQ_CSR_BASE + 0x70) /* OQ出队DPL=0时，配置plen给ESCH，用于调度权重刷新。 */ +#define CSR_QU_OQ_CSR_OQ_LATENCY_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x74) /* oq的时延采样DFX配置 */ +#define CSR_QU_OQ_CSR_OQ_LATENCY_STA_REG (CSR_QU_OQ_CSR_BASE + 0x78) /* oq的时延采样DFX状态 */ +#define CSR_QU_OQ_CSR_OQ_SAMPLE_TMR_REG (CSR_QU_OQ_CSR_BASE + 0x7C) /* oq的时延采样DFX时间 */ +#define CSR_QU_OQ_CSR_OQ_INT_VECTOR_REG (CSR_QU_OQ_CSR_BASE + 0x84) /* 中断向量 */ +#define CSR_QU_OQ_CSR_OQ_INT_REG (CSR_QU_OQ_CSR_BASE + 0x88) /* 中断状态 */ +#define CSR_QU_OQ_CSR_OQ_INT_EN_REG (CSR_QU_OQ_CSR_BASE + 0x8C) /* 中断使能 */ +#define CSR_QU_OQ_CSR_OQ_INT0_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x90) /* 中断0的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT1_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x94) /* 中断1的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT2_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x98) /* 中断2的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT3_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x9C) /* 中断3的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT4_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0xA0) /* 中断4的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT5_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0xA4) /* 中断5的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT6_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0xA8) /* 中断6的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_CTRL_REG (CSR_QU_OQ_CSR_BASE + 0xAC) /* 间接寻址控制寄存器 */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_TIMEOUT_REG (CSR_QU_OQ_CSR_BASE + 0xB0) /* OQ间接寻址timeout水线配置 */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT0_REG \ + (CSR_QU_OQ_CSR_BASE + 0xB4) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT1_REG \ + (CSR_QU_OQ_CSR_BASE + 0xB8) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT2_REG \ + (CSR_QU_OQ_CSR_BASE + 0xBC) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT3_REG \ + (CSR_QU_OQ_CSR_BASE + 0xC0) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_FIFO_FILL0_REG (CSR_QU_OQ_CSR_BASE + 0xC4) /* FIFO内数据个数 */ +#define CSR_QU_OQ_CSR_OQ_FIFO_FILL1_REG (CSR_QU_OQ_CSR_BASE + 0xC8) /* FIFO内数据个数 */ +#define CSR_QU_OQ_CSR_OQ_FIFO_FILL2_REG (CSR_QU_OQ_CSR_BASE + 0xCC) /* FIFO内数据个数 */ +#define CSR_QU_OQ_CSR_OQ_MEM_INIT_DONE_REG (CSR_QU_OQ_CSR_BASE + 0xD0) /* 所有mem在init完成后拉高 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xD4) /* 从stlfq进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xD8) /* 从stffq0进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xDC) /* 从stffq1进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLIQ_FP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xE0) /* 从stliq进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xE4) /* 从stfiq进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_BI_DSP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xE8) /* 从stffq0进入OQ的bi_dsp报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_BI_DSP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xEC) /* 从stffq1进入OQ的bi_dsp报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_REP_INFO_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xF0) /* 从stlfq 通过复制报文进入OQ的指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xF4) /* 从stlfq进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xF8) /* 从stffq0进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xFC) /* 从stffq1进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x100) /* 从stfiq进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x104) /* 从stlfq进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x108) /* 从stffq0进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x10C) /* 从stffq1进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x110) /* 从stfiq进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x114) /* 从stlfq进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x118) /* 从stffq0进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x11C) /* 从stffq1进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x120) /* 从stfiq进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x124) /* 从stlfq进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x128) /* 从stffq0进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x12C) /* 从stffq1进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x130) /* 从stfiq进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x134) /* 从stlfq进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x138) /* 从stffq0进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x13C) /* 从stffq1进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x140) /* 从stfiq进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_REP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x144) /* 从stlfq进入OQ的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_REP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x148) /* 从stffq0进入OQ的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_REP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x14C) /* 从stffq1进入OQ的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LREP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x150) /* 从stlfq进入OQ的lrep指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LREP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x154) /* 从stffq0进入OQ的lrep指令个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LREP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x158) /* 从stffq1进入OQ的lrep指令个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_OREP_REP_CNT_ADD_INC_REG \ + (CSR_QU_OQ_CSR_BASE + 0x15C) /* oq通过orep接口向prm发送触发rep_cnt++的指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OREP_LREP_INC_REG \ + (CSR_QU_OQ_CSR_BASE + 0x160) /* oq通过orep接口向prm发送的lrep指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x164) /* 从stlfq进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x168) /* 从stffq0进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x16C) /* 从stffq1进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLIQ_FP_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x170) /* 从stliq进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x174) /* 从stfiq进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_MDP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x178) /* oq通过mdp接口收到的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_HRQ_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x17C) /* oq通过hrq_fifo的主机侧报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_HRQ_DROP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x180) /* oq通过hrq_fifo的丢弃报文个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_NRQ_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x184) /* oq通过nrq_fifo的网络侧报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_RQC_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x188) /* oq通过RQC接口向ESCH请求查询的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_RQC_RVLD_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x18C) /* oq通过RQC接口收到ESCH查询结果的次数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_HOST_PTHRU_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x190) /* oq主机侧报文pass-through个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_NETWORK_PTHRU_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x194) /* oq网络侧报文pass-through个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_NETWORK_CHECK_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x198) /* oq网络侧通过drop-tail和wred丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_NETWORK_DISSENQ_DROP_PACKET_REG \ + (CSR_QU_OQ_CSR_BASE + 0x19C) /* oq网络侧由于disable队列丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_PIE_CHECK_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1A0) /* oq PIE接口由于drop-tail丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_HOST_DISSENQ_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1A4) /* oq主机侧由于disable队列丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EQS_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1A8) /* oq发起EQS次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DQR_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1AC) /* oq收到的DQR次数统计该次数=ESCH发起的调度次数 + OQ的drop报文个数； */ +#define CSR_QU_OQ_CSR_OQ_CSR_NOT_REAL_DEQ_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1B0) /* oq出队失败次数统计。oq假出队会影响调度带宽和调度shaper精度。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_EMPTY_QUEUE_REG (CSR_QU_OQ_CSR_BASE + 0x1B4) /* ESCH对oq发起空调度的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_BP_BY_PRM_ICD_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1B8) /* 主机侧队列或者网络侧lb队列向PRM预扣被反压次数计数器。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_BP_BY_PRM_DCD_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1BC) /* 主机侧队列换src时，向PRM释放资源被反压次数计数器。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_BP_BY_STFIQ_LB_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C0) /* 主机侧队列向STFIQ lb时，被STFIQ反压次数计数器。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_OQ_FCNP_BP_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C4) /* STFIQ对OQ的FCNP反压周期计数器，正常情况该计数器应当为0 */ +#define CSR_QU_OQ_CSR_OQ_CSR_CPBTX_BP_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C8) /* CPB对OQ的TX方向反压周期计数器，正常情况该计数器应当为0 */ +#define CSR_QU_OQ_CSR_OQ_CSR_CPBRX_BP_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1CC) /* CPB对OQ的RX方向反压周期计数器，正常情况该计数器应当为0 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DQS_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1D0) /* oq发起DQS的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1D4) /* oq发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_2K_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1D8) /* oq向主机侧2K个队列发起入队次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_PIE_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1DC) /* oq向PIE队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_DDR_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1E0) /* oq向DDR队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_LOOPBACK_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1E4) /* oq向主机侧loopback队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_NETWORK_4K_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1E8) /* oq向网络侧4K个队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_NETWORK_LOOPBACK_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1EC) /* oq向网络侧loopback队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_DROP_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1F0) /* oq向丢弃队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_TPD_TO_CITF_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1F4) /* oqm向citf发送的pd次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_TID_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1F8) /* oqm发起tid操作的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1FC) /* oqm发起stp操作的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x200) /* stffq0发起fcnp操作次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x204) /* stffq1发起fcnp操作次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x208) /* stlfq发起fcnp操作次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OQ_ESCH_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x20C) /* oq向ESCH发起fcnp指令次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OQ_STFIQ_FCNP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x210) /* oq向stfiq发起fcnp task-event队列入队的请求次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x214) /* oq向cpb发送的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TSO12_TO_NETWORK_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x218) /* oq向cpb发送的网络侧tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO12_TO_NETWORK_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x21C) /* oq向cpb发送的网络侧lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO12_TO_HOST_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x220) /* oq向cpb发送的主机侧lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TSO3_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x224) /* oq向cpb发送的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO3_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x228) /* oq向cpb发送的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TSO12_PIECE_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x22C) /* oq向cpb发送的tso1/2分片个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO12_PIECE_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x230) /* oq向cpb发送的lro1/2分片个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_DMARCND_TO_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x234) /* oq向cpb发送的dmarcmd报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_REP_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x238) /* oq向cpb发送的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DROP_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x23C) /* oq向cpb发送的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DPL_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x240) /* oq向ESCH发起的DPL次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OLB_TO_IQ_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x244) /* oq向iq发送OLB的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DISABLE_EPD_TO_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x248) /* citf模块由于配置，没有发给cpb的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_PRLS_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x24C) /* oq由于丢弃复制报文，向prm发起prls的次数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_ICD_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x250) /* oq向prm发起预扣次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DCD_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x254) /* oq向prm发起释放次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_PTHRU_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x258) /* citf模块收到的pass-through报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_MEM_ECC_1BIT_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x25C) /* oq内部RAM发生1BIT ECC的次数 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DROP_QUEUE_DEPTH_REG (CSR_QU_OQ_CSR_BASE + 0x260) /* DROP队列深度 */ +#define CSR_QU_OQ_CSR_OQ_BP_STATUS_REG (CSR_QU_OQ_CSR_BASE + 0x264) /* OQ受到的所有反压状态 */ + +#endif // OQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_c_union_define.h new file mode 100644 index 000000000..85da3628b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_c_union_define.h @@ -0,0 +1,1819 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : pe_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/05 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/08/10 14:30:28 Create file +// ****************************************************************************** + +#ifndef PE_C_UNION_DEFINE_H +#define PE_C_UNION_DEFINE_H + +/* Define the union csr_petx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fpga_ver_u; + +/* Define the union csr_petx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_emu_ver_u; + +/* Define the union csr_petx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ini_cmd_ram_start : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_initctab_start_u; + +/* Define the union csr_petx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ini_cmd_ram_done : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_initctab_done_u; + +/* Define the union csr_petx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 petx_int_enable : 1; /* [27] */ + u32 petx_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_int_vector_u; + +/* Define the union csr_petx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 petx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_int_u; + +/* Define the union csr_petx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_int_en : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 petx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_int_en_u; + +/* Define the union csr_petx_cmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cmd_err : 1; /* [0] */ + u32 petx_cmd_inj_err : 1; /* [1] */ + u32 petx_cmd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_cmd_err_u; + +/* Define the union csr_petx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_ucerr : 1; /* [0] */ + u32 petx_inj_ram_ucerr : 1; /* [1] */ + u32 petx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_ucerr_u; + +/* Define the union csr_petx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_cerr : 1; /* [0] */ + u32 petx_inj_ram_cerr : 1; /* [1] */ + u32 petx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_cerr_u; + +/* Define the union csr_petx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_crdt_err : 1; /* [0] */ + u32 petx_crdt_inj_err : 1; /* [1] */ + u32 petx_crdt_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_crdt_err_u; + +/* Define the union csr_petx_fifo_ovf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_fifo_ovf_err : 1; /* [0] */ + u32 petx_fifo_ovf_inj_err : 1; /* [1] */ + u32 petx_fifo_ovf_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_ovf_err_u; + +/* Define the union csr_petx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_indrect_addr : 24; /* [23:0] */ + u32 petx_indrect_tab : 4; /* [27:24] */ + u32 petx_indrect_state : 2; /* [29:28] */ + u32 petx_indrect_mode : 1; /* [30] */ + u32 petx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_indrect_ctrl_u; + +/* Define the union csr_petx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_indrect_timeout_u; + +/* Define the union csr_petx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_indrect_data_u; + +/* Define the union csr_petx_ucerr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cmd_ucerr_ctrl : 1; /* [0] */ + u32 petx_crdt_ucerr_ctrl : 1; /* [1] */ + u32 petx_cpsfo_ovf_ctrl : 1; /* [2] */ + u32 petx_hefo_ovf_ctrl : 1; /* [3] */ + u32 petx_gbfo_ovf_ctrl : 1; /* [4] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 petx_cdf_ram_ucerr_ctrl : 1; /* [8] */ + u32 petx_cpsfo_ram_ucerr_ctrl : 1; /* [9] */ + u32 petx_gsope_ram_ucerr_ctrl : 1; /* [10] */ + u32 petx_he_ram_ucerr_ctrl : 1; /* [11] */ + u32 petx_cht_ram_ucerr_ctrl : 1; /* [12] */ + u32 petx_gbfo_ram_ucerr_ctrl : 1; /* [13] */ + u32 rsv_7 : 17; /* [30:14] */ + u32 petx_ucerr_ctrl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ucerr_ctrl_u; + +/* Define the union csr_petx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_err_chk_bypass : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_err_chk_bypass_u; + +/* Define the union csr_petx_inj_ram_err_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_inj_cdf_ram_cerr : 1; /* [0] */ + u32 petx_inj_cdf_ram_ucerr : 1; /* [1] */ + u32 petx_inj_cpsfo_ram_cerr : 1; /* [2] */ + u32 petx_inj_cpsfo_ram_ucerr : 1; /* [3] */ + u32 petx_inj_gsope_ram_cerr : 1; /* [4] */ + u32 petx_inj_gsope_ram_ucerr : 1; /* [5] */ + u32 petx_inj_he_ram_cerr : 1; /* [6] */ + u32 petx_inj_he_ram_ucerr : 1; /* [7] */ + u32 petx_inj_cht_ram_cerr : 1; /* [8] */ + u32 petx_inj_cht_ram_ucerr : 1; /* [9] */ + u32 petx_inj_gbfo_ram_cerr : 1; /* [10] */ + u32 petx_inj_gbfo_ram_ucerr : 1; /* [11] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_inj_ram_err_cfg_u; + +/* Define the union csr_petx_en_hcmd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_en_hcmd_num : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_en_hcmd_num_u; + +/* Define the union csr_petx_chnl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_chnl_hcmd_en : 1; /* [0] */ + u32 rsv_9 : 22; /* [22:1] */ + u32 petx_chnl_idle_th : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_chnl_cfg_u; + +/* Define the union csr_petx_pre_alc_pkt_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_pre_alc_pkt_crdt : 4; /* [3:0] */ + u32 petx_ertn_pkt_crdt_th : 4; /* [7:4] */ + u32 rsvd : 24; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_pre_alc_pkt_crdt_u; + +/* Define the union csr_petx_ecrc_ini0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ecrc_ini0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ecrc_ini0_u; + +/* Define the union csr_petx_ecrc_ini1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ecrc_ini1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ecrc_ini1_u; + +/* Define the union csr_petx_ecrc_msk0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk0_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk0_h_u; + +/* Define the union csr_petx_ecrc_msk0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk0_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk0_l_u; + +/* Define the union csr_petx_ecrc_msk1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk1_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk1_h_u; + +/* Define the union csr_petx_ecrc_msk1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk1_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk1_l_u; + +/* Define the union csr_petx_ecrc_msk2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk2_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk2_h_u; + +/* Define the union csr_petx_ecrc_msk2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk2_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk2_l_u; + +/* Define the union csr_petx_ecrc_msk3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk3_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk3_h_u; + +/* Define the union csr_petx_ecrc_msk3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk3_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk3_l_u; + +/* Define the union csr_petx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_af_th : 8; /* [7:0] */ + u32 petx_hefo_af_th : 7; /* [14:8] */ + u32 rsvd : 17; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_af_th_u; + +/* Define the union csr_petx_n1588_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_n1588_clk_ofs : 31; /* [30:0] */ + u32 petx_n1588_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_n1588_clk_ofs_u; + +/* Define the union csr_petx_1588_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_1588_clk_ofs : 31; /* [30:0] */ + u32 petx_1588_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_1588_clk_ofs_u; + +/* Define the union csr_petx_vbs_hcrc_ini0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_vbs_hcrc_ini0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_vbs_hcrc_ini0_u; + +/* Define the union csr_petx_vbs_hcrc_ini1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_vbs_hcrc_ini1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_vbs_hcrc_ini1_u; + +/* Define the union csr_petx_gip0_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip0_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip0_id_u; + +/* Define the union csr_petx_gip1_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip1_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip1_id_u; + +/* Define the union csr_petx_gip2_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip2_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip2_id_u; + +/* Define the union csr_petx_gip3_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip3_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip3_id_u; + +/* Define the union csr_petx_ram_ctrl_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_ctrl_h : 6; /* [5:0] */ + u32 rsvd : 26; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_ctrl_h_u; + +/* Define the union csr_petx_ram_ctrl_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ram_ctrl_m : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ram_ctrl_m_u; + +/* Define the union csr_petx_ram_ctrl_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ram_ctrl_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ram_ctrl_l_u; + +/* Define the union csr_petx_clk_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_clk_period_fraction : 30; /* [29:0] */ + u32 petx_clk_period_integer : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_clk_period_u; + +/* Define the union csr_petx_chnl_sof_eof_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_chnl_sof_eof_st : 11; /* [10:0] */ + u32 rsvd : 21; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_chnl_sof_eof_st_u; + +/* Define the union csr_petx_chnl_crdt_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_chnl_crdt_st : 11; /* [10:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_chnl_crdt_st_u; + +/* Define the union csr_petx_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_cnt : 8; /* [7:0] */ + u32 petx_hefo_cnt : 7; /* [14:8] */ + u32 rsvd : 17; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_cnt_u; + +/* Define the union csr_petx_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_ovf_cur : 1; /* [0] */ + u32 petx_gbfo_full_cur : 1; /* [1] */ + u32 petx_gbfo_empty_cur : 1; /* [2] */ + u32 rsv_10 : 1; /* [3] */ + u32 petx_hefo_ovf_cur : 1; /* [4] */ + u32 petx_hefo_full_cur : 1; /* [5] */ + u32 petx_hefo_empty_cur : 1; /* [6] */ + u32 rsv_11 : 1; /* [7] */ + u32 rsv_12 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_cur_st_u; + +/* Define the union csr_petx_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_ovf_hst : 1; /* [0] */ + u32 petx_gbfo_full_hst : 1; /* [1] */ + u32 petx_hefo_ovf_hst : 1; /* [2] */ + u32 petx_hefo_full_hst : 1; /* [3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_hst_st_u; + +/* Define the union csr_petx_sof_eof_err_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_sof_eof_err_hst : 11; /* [10:0] */ + u32 rsvd : 21; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_sof_eof_err_hst_st_u; + +/* Define the union csr_petx_cpb_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cpb_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_cpb_pkt_cnt_u; + +/* Define the union csr_petx_mag_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_mag_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_mag_pkt_cnt_u; + +/* Define the union csr_petx_cpb_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cpb_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_cpb_err_pkt_cnt_u; + +/* Define the union csr_petx_mag_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_mag_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_mag_err_pkt_cnt_u; + +/* Define the union csr_petx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_ucerr_cnt_u; + +/* Define the union csr_petx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_cerr_cnt_u; + +/* Define the union csr_petx_rcv_cpb_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rcv_cpb_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rcv_cpb_cyc_cnt_u; + +/* Define the union csr_petx_rtn_cpb_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rtn_cpb_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rtn_cpb_crdt_cnt_u; + +/* Define the union csr_petx_rtn_cpb_ififo_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rtn_cpb_ififo_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rtn_cpb_ififo_crdt_cnt_u; + +/* Define the union csr_petx_rtn_cpb_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rtn_cpb_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rtn_cpb_cmdidx_crdt_cnt_u; + +/* Define the union csr_petx_snt_mag_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_snt_mag_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_snt_mag_cyc_cnt_u; + +/* Define the union csr_petx_rcv_mag_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rcv_mag_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rcv_mag_crdt_cnt_u; + +/* Define the union csr_petx_rcv_mag_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rcv_mag_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rcv_mag_cmdidx_crdt_cnt_u; + + +/* Define the union csr_perx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fpga_ver_u; + +/* Define the union csr_perx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_emu_ver_u; + +/* Define the union csr_perx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ini_cmd_ram_start : 1; /* [0] */ + u32 perx_ini_dgst_ram_start : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_initctab_start_u; + +/* Define the union csr_perx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ini_cmd_ram_done : 1; /* [0] */ + u32 perx_ini_dgst_ram_done : 1; /* [1] */ + u32 rsv_1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_initctab_done_u; + +/* Define the union csr_perx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 perx_int_enable : 1; /* [27] */ + u32 perx_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_int_vector_u; + +/* Define the union csr_perx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 perx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_int_u; + +/* Define the union csr_perx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_int_en : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 perx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_int_en_u; + +/* Define the union csr_perx_cmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cmd_err : 1; /* [0] */ + u32 perx_cmd_inj_err : 1; /* [1] */ + u32 perx_cmd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cmd_err_u; + +/* Define the union csr_perx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_ucerr : 1; /* [0] */ + u32 perx_inj_ram_ucerr : 1; /* [1] */ + u32 perx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_ucerr_u; + +/* Define the union csr_perx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_cerr : 1; /* [0] */ + u32 perx_inj_ram_cerr : 1; /* [1] */ + u32 perx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_cerr_u; + +/* Define the union csr_perx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_crdt_err : 1; /* [0] */ + u32 perx_crdt_inj_err : 1; /* [1] */ + u32 perx_crdt_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_crdt_err_u; + +/* Define the union csr_perx_fifo_ovf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fifo_ovf_err : 1; /* [0] */ + u32 perx_fifo_ovf_inj_err : 1; /* [1] */ + u32 perx_fifo_ovf_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_ovf_err_u; + +/* Define the union csr_perx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_indrect_addr : 24; /* [23:0] */ + u32 perx_indrect_tab : 4; /* [27:24] */ + u32 perx_indrect_state : 2; /* [29:28] */ + u32 perx_indrect_mode : 1; /* [30] */ + u32 perx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_indrect_ctrl_u; + +/* Define the union csr_perx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_indrect_timeout_u; + +/* Define the union csr_perx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_indrect_data_u; + +/* Define the union csr_perx_ucerr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cmd_ucerr_ctrl : 1; /* [0] */ + u32 perx_crdt_ucerr_ctrl : 1; /* [1] */ + u32 perx_cpb_ifo_ovf_ctrl : 1; /* [2] */ + u32 perx_dcry_ifo_ovf_ctrl : 1; /* [3] */ + u32 perx_hefo_ovf_ctrl : 1; /* [4] */ + u32 perx_fst_gbfo_ovf_ctrl : 1; /* [5] */ + u32 perx_difxoc_fifo_ovf_ctrl : 1; /* [6] */ + u32 rsv_6 : 1; /* [7] */ + u32 perx_cpb_cdf_ram_ucerr_ctrl : 1; /* [8] */ + u32 perx_cpb_ifo_ram_ucerr_ctrl : 1; /* [9] */ + u32 perx_dcry_cdf_ram_ucerr_ctrl : 1; /* [10] */ + u32 perx_dcry_ifo_ram_ucerr_ctrl : 1; /* [11] */ + u32 perx_cpsfo_ram_ucerr_ctrl : 1; /* [12] */ + u32 perx_he_ram_ucerr_ctrl : 1; /* [13] */ + u32 perx_fcht_ram_ucerr_ctrl : 1; /* [14] */ + u32 perx_fst_gbfo_ram_ucerr_ctrl : 1; /* [15] */ + u32 perx_dctx_ram_ucerr_ctrl : 1; /* [16] */ + u32 perx_difxpp_ram_ucerr_ctrl : 1; /* [17] */ + u32 perx_difx_ioc_ram_ucerr_ctrl : 1; /* [18] */ + u32 perx_difxoc_dram_ucerr_ctrl : 1; /* [19] */ + u32 perx_difxoc_smd_ram_ucerr_ctrl : 1; /* [20] */ + u32 perx_mpu_ipsurx_ram_ucerr_ctrl : 1; /* [21] */ + u32 perx_otcc_rocfo_ram_ucerr_ctrl : 1; /* [22] */ + u32 perx_otcc_rwcfo_ram_ucerr_ctrl : 1; /* [23] */ + u32 rsv_7 : 7; /* [30:24] */ + u32 perx_ucerr_ctrl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ucerr_ctrl_u; + +/* Define the union csr_perx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_err_chk_bypass : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_err_chk_bypass_u; + +/* Define the union csr_perx_inj_ram_err_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_inj_cpb_cdf_ram_cerr : 1; /* [0] */ + u32 perx_inj_cpb_cdf_ram_ucerr : 1; /* [1] */ + u32 perx_inj_cpb_ifo_ram_cerr : 1; /* [2] */ + u32 perx_inj_cpb_ifo_ram_ucerr : 1; /* [3] */ + u32 perx_inj_dcry_cdf_ram_cerr : 1; /* [4] */ + u32 perx_inj_dcry_cdf_ram_ucerr : 1; /* [5] */ + u32 perx_inj_dcry_ifo_ram_cerr : 1; /* [6] */ + u32 perx_inj_dcry_ifo_ram_ucerr : 1; /* [7] */ + u32 perx_inj_cpsfo_ram_cerr : 1; /* [8] */ + u32 perx_inj_cpsfo_ram_ucerr : 1; /* [9] */ + u32 perx_inj_he_ram_cerr : 1; /* [10] */ + u32 perx_inj_he_ram_ucerr : 1; /* [11] */ + u32 perx_inj_fcht_ram_cerr : 1; /* [12] */ + u32 perx_inj_fcht_ram_ucerr : 1; /* [13] */ + u32 perx_inj_fst_gbfo_ram_cerr : 1; /* [14] */ + u32 perx_inj_fst_gbfo_ram_ucerr : 1; /* [15] */ + u32 perx_inj_dctx_ram_cerr : 1; /* [16] */ + u32 perx_inj_dctx_ram_ucerr : 1; /* [17] */ + u32 perx_inj_difxpp_ram_cerr : 1; /* [18] */ + u32 perx_inj_difxpp_ram_ucerr : 1; /* [19] */ + u32 perx_inj_difx_ioc_ram_cerr : 1; /* [20] */ + u32 perx_inj_difx_ioc_ram_ucerr : 1; /* [21] */ + u32 perx_inj_difxoc_dat_ram_cerr : 1; /* [22] */ + u32 perx_inj_difxoc_dat_ram_ucerr : 1; /* [23] */ + u32 perx_inj_difxoc_smd_ram_cerr : 1; /* [24] */ + u32 perx_inj_difxoc_smd_ram_ucerr : 1; /* [25] */ + u32 perx_inj_mpu_ipsurx_ram_cerr : 1; /* [26] */ + u32 perx_inj_mpu_ipsurx_ram_ucerr : 1; /* [27] */ + u32 perx_inj_otcc_rocfo_ram_cerr : 1; /* [28] */ + u32 perx_inj_otcc_rocfo_ram_ucerr : 1; /* [29] */ + u32 perx_inj_otcc_rwcfo_ram_cerr : 1; /* [30] */ + u32 perx_inj_otcc_rwcfo_ram_ucerr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_inj_ram_err_cfg_u; + +/* Define the union csr_perx_en_hcmd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_en_hcmd_num : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_en_hcmd_num_u; + +/* Define the union csr_perx_chnl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_chnl_hcmd_en : 1; /* [0] */ + u32 perx_chnl_dcry_en : 1; /* [1] */ + u32 perx_chnl_difxe_en : 1; /* [2] */ + u32 perx_dsgl_smd_num : 5; /* [7:3] */ + u32 rsv_8 : 15; /* [22:8] */ + u32 perx_chnl_idle_th : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_chnl_cfg_u; + +/* Define the union csr_perx_pre_alc_pkt_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_pre_alc_pkt_crdt0 : 4; /* [3:0] */ + u32 perx_pre_alc_pkt_crdt1 : 4; /* [7:4] */ + u32 perx_ertn_pkt_crdt_th : 4; /* [11:8] */ + u32 rsvd : 20; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_pre_alc_pkt_crdt_u; + +/* Define the union csr_perx_lp_mpu_chnl_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ipsurx_chnl1_crdt : 7; /* [6:0] */ + u32 rsv_9 : 1; /* [7] */ + u32 perx_ipsurx_chnl0_crdt : 7; /* [14:8] */ + u32 rsv_10 : 1; /* [15] */ + u32 perx_mpu_chnl_crdt : 7; /* [22:16] */ + u32 rsv_11 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_lp_mpu_chnl_crdt_u; + +/* Define the union csr_perx_icrc_ini0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_ini0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_ini0_u; + +/* Define the union csr_perx_icrc_ini1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_ini1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_ini1_u; + +/* Define the union csr_perx_icrc_mgc0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_mgc0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_mgc0_u; + +/* Define the union csr_perx_icrc_mgc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_mgc1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_mgc1_u; + +/* Define the union csr_perx_difx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_grd_crc_ini : 16; /* [15:0] */ + u32 perx_grd_cs_ini : 16; /* [31:16] */ + u32 perx_difx_vrf_special_en : 1; /* [32] */ + u32 perx_difx_rev_ipcs_rslt : 1; /* [33] */ + u32 perx_difx_rev_ipcs_f1_rslt : 1; /* [34] */ + u32 perx_difx_rev_ipcs_f0_rslt : 1; /* [35] */ + u32 perx_difx_rev_crc16_rslt : 1; /* [36] */ + u32 perx_difx_crc16_rslt_odr : 1; /* [37] */ + u32 perx_difx_crc16_in_dat_odr : 1; /* [38] */ + u32 rsvd : 25; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_difx_cfg_u; + +/* Define the union csr_perx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fgbfo_af_th : 8; /* [7:0] */ + u32 perx_hefo_af_th : 7; /* [14:8] */ + u32 rsv_12 : 1; /* [15] */ + u32 perx_difxoc_fifo_af_th : 7; /* [22:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_af_th_u; + +/* Define the union csr_perx_1588_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_1588_clk_ofs : 31; /* [30:0] */ + u32 perx_1588_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_1588_clk_ofs_u; + +/* Define the union csr_perx_ppop_chnl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ppop_ack_chnl : 5; /* [4:0] */ + u32 rsv_13 : 3; /* [7:5] */ + u32 perx_ppop_rqst_chnl : 5; /* [12:8] */ + u32 perx_ppop_en : 1; /* [13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ppop_chnl_u; + +/* Define the union csr_perx_ram_ctrl_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_ctrl_hh : 6; /* [5:0] */ + u32 rsvd : 26; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_ctrl_h_u; + +/* Define the union csr_perx_ram_ctrl_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 perx_ram_ctrl_hm : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_ram_ctrl_m_u; + +/* Define the union csr_perx_ram_ctrl_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 perx_ram_ctrl_mm : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_ram_ctrl_l_u; + +/* Define the union csr_perx_clk_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_clk_period_fraction : 30; /* [29:0] */ + u32 perx_clk_period_integer : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_clk_period_u; + +/* Define the union csr_perx_chnl_sop_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_sop_eop_st : 23; /* [22:0] */ + u32 rsv_14 : 1; /* [23] */ + u32 perx_dcry_sop_eop_st : 18; /* [41:24] */ + u32 rsvd : 22; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_chnl_sop_eop_st_u; + +/* Define the union csr_perx_chnl_crdt_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_chnl_crdt_st : 23; /* [22:0] */ + u32 rsv_15 : 1; /* [23] */ + u32 perx_dcry_chnl_crdt_st : 3; /* [26:24] */ + u32 rsvd : 5; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_chnl_crdt_st_u; + +/* Define the union csr_perx_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fst_gbfo_cnt : 8; /* [7:0] */ + u32 perx_hefo_cnt : 7; /* [14:8] */ + u32 rsv_16 : 1; /* [15] */ + u32 perx_difxoc_fifo_cnt : 7; /* [22:16] */ + u32 rsvd : 9; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_cnt_u; + +/* Define the union csr_perx_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fst_gbfo_ovf_cur : 1; /* [0] */ + u32 perx_fst_gbfo_full_cur : 1; /* [1] */ + u32 perx_fst_gbfo_empty_cur : 1; /* [2] */ + u32 rsv_17 : 1; /* [3] */ + u32 perx_hefo_ovf_cur : 1; /* [4] */ + u32 perx_hefo_full_cur : 1; /* [5] */ + u32 perx_hefo_empty_cur : 1; /* [6] */ + u32 rsv_18 : 1; /* [7] */ + u32 perx_difxoc_fifo_ovf_cur : 1; /* [8] */ + u32 perx_difxoc_fifo_full_cur : 1; /* [9] */ + u32 perx_difxoc_fifo_empty_cur : 1; /* [10] */ + u32 rsv_19 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_cur_st_u; + +/* Define the union csr_perx_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fst_gbfo_ovf_hst : 1; /* [0] */ + u32 perx_fst_gbfo_full_hst : 1; /* [1] */ + u32 perx_hefo_ovf_hst : 1; /* [2] */ + u32 perx_hefo_full_hst : 1; /* [3] */ + u32 perx_difxoc_fifo_ovf_hst : 1; /* [4] */ + u32 perx_difxoc_fifo_full_hst : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_hst_st_u; + +/* Define the union csr_perx_sop_eop_err_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_sop_eop_err_hst : 23; /* [22:0] */ + u32 rsv_20 : 1; /* [23] */ + u32 perx_dcry_sop_eop_err_hst : 18; /* [41:24] */ + u32 rsvd : 22; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sop_eop_err_hst_st_u; + +/* Define the union csr_perx_cpb_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpb_pkt_cnt_u; + +/* Define the union csr_perx_s_dcry_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_s_dcry_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_s_dcry_pkt_cnt_u; + +/* Define the union csr_perx_r_dcry_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_r_dcry_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_r_dcry_pkt_cnt_u; + +/* Define the union csr_perx_cmi_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cmi_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cmi_pkt_cnt_u; + +/* Define the union csr_perx_ppop_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ppop_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ppop_pkt_cnt_u; + +/* Define the union csr_perx_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_drp_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_drp_pkt_cnt_u; + +/* Define the union csr_perx_cpb_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpb_err_pkt_cnt_u; + +/* Define the union csr_perx_s_dcry_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_s_dcry_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_s_dcry_err_pkt_cnt_u; + +/* Define the union csr_perx_r_dcry_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_r_dcry_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_r_dcry_err_pkt_cnt_u; + +/* Define the union csr_perx_cpi_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpi_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpi_err_pkt_cnt_u; + +/* Define the union csr_perx_ipsurx_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ipsurx_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ipsurx_err_pkt_cnt_u; + +/* Define the union csr_perx_mpu_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_mpu_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_mpu_err_pkt_cnt_u; + +/* Define the union csr_perx_ppop_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ppop_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ppop_err_pkt_cnt_u; + +/* Define the union csr_perx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_ucerr_cnt_u; + +/* Define the union csr_perx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_cerr_cnt_u; + +/* Define the union csr_perx_cpi_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpi_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpi_bp_cnt_u; + +/* Define the union csr_perx_mpu_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_mpu_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_mpu_bp_cnt_u; + +/* Define the union csr_perx_rcv_cpb_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_cpb_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_cpb_cyc_cnt_u; + +/* Define the union csr_perx_rtn_cpb_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_cpb_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_cpb_crdt_cnt_u; + +/* Define the union csr_perx_rtn_cpb_ififo_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_cpb_ififo_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_cpb_ififo_crdt_cnt_u; + +/* Define the union csr_perx_rtn_cpb_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_cpb_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_cpb_cmdidx_crdt_cnt_u; + +/* Define the union csr_perx_snt_dcry_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_snt_dcry_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_snt_dcry_cyc_cnt_u; + +/* Define the union csr_perx_rcv_dcry_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_dcry_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_dcry_crdt_cnt_u; + +/* Define the union csr_perx_rcv_dcry_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_dcry_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_dcry_cyc_cnt_u; + +/* Define the union csr_perx_rtn_dcry_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_dcry_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_dcry_crdt_cnt_u; + +/* Define the union csr_perx_rtn_dcry_ififo_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_dcry_ififo_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_dcry_ififo_crdt_cnt_u; + +/* Define the union csr_perx_rtn_dcry_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_dcry_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_dcry_cmdidx_crdt_cnt_u; + +/* Define the union csr_perx_snt_cpi_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_snt_cpi_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_snt_cpi_cyc_cnt_u; + +/* Define the union csr_perx_snt_ipsurx_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_snt_ipsurx_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_snt_ipsurx_cyc_cnt_u; + +/* Define the union csr_perx_rcv_ipsurx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_ipsurx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_ipsurx_crdt_cnt_u; + +/* Define the union csr_perx_dgst_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_dgst_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_dgst_err_cnt_u; + +/* Define the union csr_perx_sector_grd_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_sector_grd_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sector_grd_ilgl_cnt_u; + +/* Define the union csr_perx_sector_ref_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_sector_ref_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sector_ref_ilgl_cnt_u; + +/* Define the union csr_perx_sector_app_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_sector_app_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sector_app_ilgl_cnt_u; + +/* Define the union csr_perx_difx_err_dfx_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_err_dfx_clr : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_dfx_clr_u; + +/* Define the union csr_perx_difx_err_info_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_guard_err : 1; /* [0] */ + u32 perx_difx_app_err : 1; /* [1] */ + u32 perx_difx_ref_err : 1; /* [2] */ + u32 rsv_22 : 1; /* [3] */ + u32 perx_difx_vrf_type : 2; /* [5:4] */ + u32 rsv_23 : 2; /* [7:6] */ + u32 perx_difx_err_chnl : 5; /* [12:8] */ + u32 rsv_24 : 3; /* [15:13] */ + u32 perx_difx_task_tag : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw0_u; + +/* Define the union csr_perx_difx_err_info_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_rcv_guard : 16; /* [15:0] */ + u32 perx_difx_rcv_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw1_u; + +/* Define the union csr_perx_difx_err_info_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_rcv_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw2_u; + +/* Define the union csr_perx_difx_err_info_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_exp_guard : 16; /* [15:0] */ + u32 perx_difx_exp_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw3_u; + +/* Define the union csr_perx_difx_err_info_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_exp_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw4_u; + + +#endif // PE_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_reg_offset.h new file mode 100644 index 000000000..7b545e252 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_reg_offset.h @@ -0,0 +1,493 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : pe_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/05 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/05/07 11:24:30 Create file +// ****************************************************************************** + +#ifndef PE_REG_OFFSET_H +#define PE_REG_OFFSET_H + +/* PETX_CSR Base address of Module's Register */ +#define CSR_PETX_CSR_BASE (0xA000) + +/* **************************************************************************** */ +/* PETX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PETX_CSR_PETX_FPGA_VER_REG (CSR_PETX_CSR_BASE + 0x0) /* FPGA版本寄存器 */ +#define CSR_PETX_CSR_PETX_EMU_VER_REG (CSR_PETX_CSR_BASE + 0x8) /* EMU版本寄存器 */ +#define CSR_PETX_CSR_PETX_INITCTAB_START_REG (CSR_PETX_CSR_BASE + 0x10) /* 配置表初始化使能寄存器 */ +#define CSR_PETX_CSR_PETX_INITCTAB_DONE_REG (CSR_PETX_CSR_BASE + 0x18) /* 配置表初始化状态寄存器 */ +#define CSR_PETX_CSR_PETX_INT_VECTOR_REG (CSR_PETX_CSR_BASE + 0x20) /* 中断向量寄存器 */ +#define CSR_PETX_CSR_PETX_INT_REG (CSR_PETX_CSR_BASE + 0x28) /* 中断数据寄存器 */ +#define CSR_PETX_CSR_PETX_INT_EN_REG (CSR_PETX_CSR_BASE + 0x30) /* 中断使能寄存器 */ +#define CSR_PETX_CSR_PETX_CMD_ERR_REG (CSR_PETX_CSR_BASE + 0x38) /* CMD错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_RAM_UCERR_REG (CSR_PETX_CSR_BASE + 0x40) /* RAM 不可纠错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_RAM_CERR_REG (CSR_PETX_CSR_BASE + 0x48) /* RAM 可纠错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_CRDT_ERR_REG (CSR_PETX_CSR_BASE + 0x50) /* 信用错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_FIFO_OVF_ERR_REG (CSR_PETX_CSR_BASE + 0x58) /* FIFO溢出中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_INDRECT_CTRL_REG (CSR_PETX_CSR_BASE + 0x320) /* 间接寻址控制寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_TIMEOUT_REG (CSR_PETX_CSR_BASE + 0x328) /* 间接寻址TIMEOUT配置寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_0_REG (CSR_PETX_CSR_BASE + 0x330) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_1_REG (CSR_PETX_CSR_BASE + 0x334) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_2_REG (CSR_PETX_CSR_BASE + 0x338) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_3_REG (CSR_PETX_CSR_BASE + 0x33C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_4_REG (CSR_PETX_CSR_BASE + 0x340) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_5_REG (CSR_PETX_CSR_BASE + 0x344) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_6_REG (CSR_PETX_CSR_BASE + 0x348) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_7_REG (CSR_PETX_CSR_BASE + 0x34C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_8_REG (CSR_PETX_CSR_BASE + 0x350) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_9_REG (CSR_PETX_CSR_BASE + 0x354) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_10_REG (CSR_PETX_CSR_BASE + 0x358) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_11_REG (CSR_PETX_CSR_BASE + 0x35C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_12_REG (CSR_PETX_CSR_BASE + 0x360) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_13_REG (CSR_PETX_CSR_BASE + 0x364) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_14_REG (CSR_PETX_CSR_BASE + 0x368) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_15_REG (CSR_PETX_CSR_BASE + 0x36C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_UCERR_CTRL_REG (CSR_PETX_CSR_BASE + 0x400) /* petx致命错误控制寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_ERR_CHK_BYPASS_REG (CSR_PETX_CSR_BASE + 0x410) /* petx模块RAM错误检查BYPASS寄存器 */ +#define CSR_PETX_CSR_PETX_INJ_RAM_ERR_CFG_REG (CSR_PETX_CSR_BASE + 0x418) /* petx模块RAM错误注入寄存器 */ +#define CSR_PETX_CSR_PETX_EN_HCMD_NUM_REG (CSR_PETX_CSR_BASE + 0x420) /* HDR_CMD使能寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_0_REG (CSR_PETX_CSR_BASE + 0x428) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_1_REG (CSR_PETX_CSR_BASE + 0x42C) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_2_REG (CSR_PETX_CSR_BASE + 0x430) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_3_REG (CSR_PETX_CSR_BASE + 0x434) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_4_REG (CSR_PETX_CSR_BASE + 0x438) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_5_REG (CSR_PETX_CSR_BASE + 0x43C) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_6_REG (CSR_PETX_CSR_BASE + 0x440) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_7_REG (CSR_PETX_CSR_BASE + 0x444) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_8_REG (CSR_PETX_CSR_BASE + 0x448) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_9_REG (CSR_PETX_CSR_BASE + 0x44C) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_10_REG (CSR_PETX_CSR_BASE + 0x450) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_PRE_ALC_PKT_CRDT_REG (CSR_PETX_CSR_BASE + 0x500) /* PKT预扣信用寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_INI0_REG (CSR_PETX_CSR_BASE + 0x508) /* FC/RoCE CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_INI1_REG (CSR_PETX_CSR_BASE + 0x510) /* FC/RoCE CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK0_H_REG (CSR_PETX_CSR_BASE + 0x518) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK0_L_REG (CSR_PETX_CSR_BASE + 0x520) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK1_H_REG (CSR_PETX_CSR_BASE + 0x528) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK1_L_REG (CSR_PETX_CSR_BASE + 0x530) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK2_H_REG (CSR_PETX_CSR_BASE + 0x538) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK2_L_REG (CSR_PETX_CSR_BASE + 0x540) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK3_H_REG (CSR_PETX_CSR_BASE + 0x548) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK3_L_REG (CSR_PETX_CSR_BASE + 0x550) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_FIFO_AF_TH_REG (CSR_PETX_CSR_BASE + 0x558) /* FIFO配置寄存器 */ +#define CSR_PETX_CSR_PETX_N1588_CLK_OFS_REG (CSR_PETX_CSR_BASE + 0x560) /* EPTX 非1588时钟偏移配置寄存器 */ +#define CSR_PETX_CSR_PETX_1588_CLK_OFS_REG (CSR_PETX_CSR_BASE + 0x568) /* EPTX1588时钟偏移配置寄存器 */ +#define CSR_PETX_CSR_PETX_VBS_HCRC_INI0_REG (CSR_PETX_CSR_BASE + 0x570) /* VBS HDR CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_VBS_HCRC_INI1_REG (CSR_PETX_CSR_BASE + 0x578) /* VBS HDR CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_GIP0_ID_REG (CSR_PETX_CSR_BASE + 0x580) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_GIP1_ID_REG (CSR_PETX_CSR_BASE + 0x588) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_GIP2_ID_REG (CSR_PETX_CSR_BASE + 0x590) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_GIP3_ID_REG (CSR_PETX_CSR_BASE + 0x598) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_CTRL_H_REG (CSR_PETX_CSR_BASE + 0x5A0) /* RAM MOD控制寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_CTRL_M_REG (CSR_PETX_CSR_BASE + 0x5A8) /* RAM MOD控制寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_CTRL_L_REG (CSR_PETX_CSR_BASE + 0x5B0) /* RAM MOD控制寄存器 */ +#define CSR_PETX_CSR_PETX_CLK_PERIOD_REG \ + (CSR_PETX_CSR_BASE + 0x5B8) /* PETX时钟周期配置寄存器。用于在CPI提供的时钟基础上维护PETX本地时钟。 */ +#define CSR_PETX_CSR_PETX_CHNL_SOF_EOF_ST_REG (CSR_PETX_CSR_BASE + 0xF98) /* 通道SOF/EOF状态 */ +#define CSR_PETX_CSR_PETX_CHNL_CRDT_ST_REG (CSR_PETX_CSR_BASE + 0xFA0) /* 通道信用状态 */ +#define CSR_PETX_CSR_PETX_FIFO_CNT_REG (CSR_PETX_CSR_BASE + 0xFA8) /* FIFO当前深度计数寄存器 */ +#define CSR_PETX_CSR_PETX_FIFO_CUR_ST_REG (CSR_PETX_CSR_BASE + 0xFB0) /* FIFO当前状态寄存器 */ +#define CSR_PETX_CSR_PETX_FIFO_HST_ST_REG (CSR_PETX_CSR_BASE + 0xFB8) /* FIFO历史状态寄存器 */ +#define CSR_PETX_CSR_PETX_SOF_EOF_ERR_HST_ST_REG (CSR_PETX_CSR_BASE + 0xFC0) /* 通道SOF/EOF ERR历史寄存器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x12C0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x12C4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x12C8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x12CC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x12D0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x12D4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x12D8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x12DC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x12E0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x12E4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x12E8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x13C0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x13C4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x13C8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x13CC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x13D0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x13D4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x13D8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x13DC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x13E0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x13E4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x13E8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_ERR_PKT_CNT_REG (CSR_PETX_CSR_BASE + 0x1500) /* 错误报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_ERR_PKT_CNT_REG (CSR_PETX_CSR_BASE + 0x1508) /* 错误报文计数器 */ +#define CSR_PETX_CSR_PETX_RAM_UCERR_CNT_REG (CSR_PETX_CSR_BASE + 0x1510) /* PETX RAM 不可纠错误计数器 */ +#define CSR_PETX_CSR_PETX_RAM_CERR_CNT_REG (CSR_PETX_CSR_BASE + 0x1518) /* PETX RAM 可纠错误计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1600) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1604) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1608) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_3_REG (CSR_PETX_CSR_BASE + 0x160C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1610) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1614) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1618) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_7_REG (CSR_PETX_CSR_BASE + 0x161C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1620) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1624) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1628) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1700) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1704) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1708) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x170C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1710) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1714) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1718) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x171C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1720) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1724) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1728) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_IFIFO_CRDT_CNT_REG (CSR_PETX_CSR_BASE + 0x1750) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CMDIDX_CRDT_CNT_REG (CSR_PETX_CSR_BASE + 0x1754) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1800) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1804) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1808) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_3_REG (CSR_PETX_CSR_BASE + 0x180C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1810) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1814) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1818) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_7_REG (CSR_PETX_CSR_BASE + 0x181C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1820) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1824) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1828) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1900) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1904) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1908) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x190C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1910) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1914) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1918) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x191C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1920) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1924) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1928) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CMDIDX_CRDT_CNT_REG (CSR_PETX_CSR_BASE + 0x1954) /* 信用计数器 */ + +/* PERX_CSR Base address of Module's Register */ +#define CSR_PERX_CSR_BASE (0x8000) + +/* **************************************************************************** */ +/* PERX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PERX_CSR_PERX_FPGA_VER_REG (CSR_PERX_CSR_BASE + 0x0) /* FPGA版本寄存器 */ +#define CSR_PERX_CSR_PERX_EMU_VER_REG (CSR_PERX_CSR_BASE + 0x8) /* EMU版本寄存器 */ +#define CSR_PERX_CSR_PERX_INITCTAB_START_REG (CSR_PERX_CSR_BASE + 0x10) /* 配置表初始化使能寄存器 */ +#define CSR_PERX_CSR_PERX_INITCTAB_DONE_REG (CSR_PERX_CSR_BASE + 0x18) /* 配置表初始化状态寄存器 */ +#define CSR_PERX_CSR_PERX_INT_VECTOR_REG (CSR_PERX_CSR_BASE + 0x20) /* 中断向量寄存器 */ +#define CSR_PERX_CSR_PERX_INT_REG (CSR_PERX_CSR_BASE + 0x28) /* 中断数据寄存器 */ +#define CSR_PERX_CSR_PERX_INT_EN_REG (CSR_PERX_CSR_BASE + 0x30) /* 中断使能寄存器 */ +#define CSR_PERX_CSR_PERX_CMD_ERR_REG (CSR_PERX_CSR_BASE + 0x38) /* CMD错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_RAM_UCERR_REG (CSR_PERX_CSR_BASE + 0x40) /* RAM 不可纠错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_RAM_CERR_REG (CSR_PERX_CSR_BASE + 0x48) /* RAM 可纠错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_CRDT_ERR_REG (CSR_PERX_CSR_BASE + 0x50) /* 信用错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_FIFO_OVF_ERR_REG (CSR_PERX_CSR_BASE + 0x58) /* FIFO溢出中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_INDRECT_CTRL_REG (CSR_PERX_CSR_BASE + 0x320) /* 间接寻址控制寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_TIMEOUT_REG (CSR_PERX_CSR_BASE + 0x328) /* 间接寻址TIMEOUT配置寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_0_REG (CSR_PERX_CSR_BASE + 0x330) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_1_REG (CSR_PERX_CSR_BASE + 0x334) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_2_REG (CSR_PERX_CSR_BASE + 0x338) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_3_REG (CSR_PERX_CSR_BASE + 0x33C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_4_REG (CSR_PERX_CSR_BASE + 0x340) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_5_REG (CSR_PERX_CSR_BASE + 0x344) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_6_REG (CSR_PERX_CSR_BASE + 0x348) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_7_REG (CSR_PERX_CSR_BASE + 0x34C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_8_REG (CSR_PERX_CSR_BASE + 0x350) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_9_REG (CSR_PERX_CSR_BASE + 0x354) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_10_REG (CSR_PERX_CSR_BASE + 0x358) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_11_REG (CSR_PERX_CSR_BASE + 0x35C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_12_REG (CSR_PERX_CSR_BASE + 0x360) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_13_REG (CSR_PERX_CSR_BASE + 0x364) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_14_REG (CSR_PERX_CSR_BASE + 0x368) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_15_REG (CSR_PERX_CSR_BASE + 0x36C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_UCERR_CTRL_REG (CSR_PERX_CSR_BASE + 0x400) /* perx致命错误控制寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_ERR_CHK_BYPASS_REG (CSR_PERX_CSR_BASE + 0x410) /* perx模块RAM错误检查BYPASS寄存器 */ +#define CSR_PERX_CSR_PERX_INJ_RAM_ERR_CFG_REG (CSR_PERX_CSR_BASE + 0x418) /* perx模块RAM错误注入寄存器 */ +#define CSR_PERX_CSR_PERX_EN_HCMD_NUM_REG (CSR_PERX_CSR_BASE + 0x420) /* HDR_CMD使能配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_0_REG (CSR_PERX_CSR_BASE + 0x428) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_1_REG (CSR_PERX_CSR_BASE + 0x42C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_2_REG (CSR_PERX_CSR_BASE + 0x430) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_3_REG (CSR_PERX_CSR_BASE + 0x434) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_4_REG (CSR_PERX_CSR_BASE + 0x438) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_5_REG (CSR_PERX_CSR_BASE + 0x43C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_6_REG (CSR_PERX_CSR_BASE + 0x440) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_7_REG (CSR_PERX_CSR_BASE + 0x444) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_8_REG (CSR_PERX_CSR_BASE + 0x448) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_9_REG (CSR_PERX_CSR_BASE + 0x44C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_10_REG (CSR_PERX_CSR_BASE + 0x450) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_11_REG (CSR_PERX_CSR_BASE + 0x454) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_12_REG (CSR_PERX_CSR_BASE + 0x458) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_13_REG (CSR_PERX_CSR_BASE + 0x45C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_14_REG (CSR_PERX_CSR_BASE + 0x460) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_15_REG (CSR_PERX_CSR_BASE + 0x464) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_16_REG (CSR_PERX_CSR_BASE + 0x468) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_17_REG (CSR_PERX_CSR_BASE + 0x46C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_18_REG (CSR_PERX_CSR_BASE + 0x470) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_19_REG (CSR_PERX_CSR_BASE + 0x474) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_20_REG (CSR_PERX_CSR_BASE + 0x478) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_21_REG (CSR_PERX_CSR_BASE + 0x47C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_22_REG (CSR_PERX_CSR_BASE + 0x480) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_PRE_ALC_PKT_CRDT_REG (CSR_PERX_CSR_BASE + 0x500) /* PKT预扣信用寄存器 */ +#define CSR_PERX_CSR_PERX_LP_MPU_CHNL_CRDT_REG (CSR_PERX_CSR_BASE + 0x508) /* PERX环回/MPU通道信用配置寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_INI0_REG (CSR_PERX_CSR_BASE + 0x510) /* ICRC初始值寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_INI1_REG (CSR_PERX_CSR_BASE + 0x518) /* ICRC初始值寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_MGC0_REG (CSR_PERX_CSR_BASE + 0x520) /* ICRC MAGIC NUMBER寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_MGC1_REG (CSR_PERX_CSR_BASE + 0x528) /* ICRC MAGIC NUMBER寄存器 */ +#define CSR_PERX_CSR_PERX_DIFX_CFG_REG (CSR_PERX_CSR_BASE + 0x530) /* DIF/DIX校验配置寄存器 */ +#define CSR_PERX_CSR_PERX_FIFO_AF_TH_REG (CSR_PERX_CSR_BASE + 0x538) /* FIFO配置寄存器 */ +#define CSR_PERX_CSR_PERX_1588_CLK_OFS_REG (CSR_PERX_CSR_BASE + 0x540) /* EPRX1588时钟偏移配置寄存器 */ +#define CSR_PERX_CSR_PERX_PPOP_CHNL_REG (CSR_PERX_CSR_BASE + 0x548) /* PPOP channel配置寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_CTRL_H_REG (CSR_PERX_CSR_BASE + 0x550) /* RAM MOD控制寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_CTRL_M_REG (CSR_PERX_CSR_BASE + 0x558) /* RAM MOD控制寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_CTRL_L_REG (CSR_PERX_CSR_BASE + 0x560) /* RAM MOD控制寄存器 */ +#define CSR_PERX_CSR_PERX_CLK_PERIOD_REG \ + (CSR_PERX_CSR_BASE + 0x568) /* PERX时钟周期配置寄存器。用于在CPI提供的时钟基础上维护PERX本地时钟。 */ +#define CSR_PERX_CSR_PERX_CHNL_SOP_EOP_ST_REG (CSR_PERX_CSR_BASE + 0xF98) /* 通道SOP/EOP状态 */ +#define CSR_PERX_CSR_PERX_CHNL_CRDT_ST_REG (CSR_PERX_CSR_BASE + 0xFA0) /* 通道信用状态 */ +#define CSR_PERX_CSR_PERX_FIFO_CNT_REG (CSR_PERX_CSR_BASE + 0xFA8) /* FIFO当前深度计数寄存器 */ +#define CSR_PERX_CSR_PERX_FIFO_CUR_ST_REG (CSR_PERX_CSR_BASE + 0xFB0) /* FIFO当前状态寄存器 */ +#define CSR_PERX_CSR_PERX_FIFO_HST_ST_REG (CSR_PERX_CSR_BASE + 0xFB8) /* FIFO历史状态寄存器 */ +#define CSR_PERX_CSR_PERX_SOP_EOP_ERR_HST_ST_REG (CSR_PERX_CSR_BASE + 0xFC0) /* 通道SOP/EOP错误历史寄存器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x12C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x12C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x12C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x12CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x12D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x12D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x12D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x12DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x12E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x12E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x12E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x12EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x12F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x12F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x12F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x12FC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1300) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1304) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1308) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_19_REG (CSR_PERX_CSR_BASE + 0x130C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1310) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1314) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1318) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x13C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x13C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x13C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x13CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x13D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x13D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x13D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x13DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x13E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x13E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x13E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x13EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x13F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x13F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x13F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x13FC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1400) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1404) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1440) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1444) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1448) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x144C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x1450) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x1454) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x1458) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x145C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x1460) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x1464) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x1468) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x146C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x1470) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x1474) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x1478) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x147C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1480) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1484) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x14C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x14C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x14C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x14CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x14D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x14D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x14D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x14DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x14E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x14E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x14E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x14EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x14F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x14F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x14F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x14FC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1500) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1504) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1508) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_19_REG (CSR_PERX_CSR_BASE + 0x150C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1510) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1514) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1518) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_PPOP_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x151C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x15C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x15C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x15C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x15CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x15D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x15D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x15D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x15DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x15E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x15E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x15E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x15EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x15F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x15F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x15F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1700) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1708) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1710) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_CPI_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1718) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_IPSURX_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1720) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_MPU_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1728) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_PPOP_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x172C) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_RAM_UCERR_CNT_REG (CSR_PERX_CSR_BASE + 0x1730) /* PERX RAM 不可纠错误计数器 */ +#define CSR_PERX_CSR_PERX_RAM_CERR_CNT_REG (CSR_PERX_CSR_BASE + 0x1738) /* PERX RAM 可纠错误计数器 */ +#define CSR_PERX_CSR_PERX_CPI_BP_CNT_REG (CSR_PERX_CSR_BASE + 0x1740) /* CPI反压PERX计数器 */ +#define CSR_PERX_CSR_PERX_MPU_BP_CNT_REG (CSR_PERX_CSR_BASE + 0x1748) /* MPU反压PERX计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x17C0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x17C4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x17C8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x17CC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x17D0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x17D4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x17D8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x17DC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x17E0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x17E4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x17E8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x17EC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x17F0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x17F4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x17F8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x17FC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1800) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1804) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1808) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_19_REG (CSR_PERX_CSR_BASE + 0x180C) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1810) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1814) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1818) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x18C0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x18C4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x18C8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x18CC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x18D0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x18D4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x18D8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x18DC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x18E0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x18E4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x18E8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x18EC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x18F0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x18F4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x18F8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x18FC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1900) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1904) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1908) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_19_REG (CSR_PERX_CSR_BASE + 0x190C) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1910) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1914) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1918) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_IFIFO_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1988) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CMDIDX_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x19BC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x19C0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x19C4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x19C8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x19CC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x19D0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x19D4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x19D8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x19DC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x19E0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x19E4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x19E8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x19EC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x19F0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x19F4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x19F8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x19FC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1A00) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1A04) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CRDT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1AC0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CRDT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1AC4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CRDT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1AC8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1BC0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1BC4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1BC8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x1BCC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x1BD0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x1BD4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x1BD8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x1BDC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x1BE0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x1BE4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x1BE8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x1BEC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x1BF0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x1BF4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x1BF8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x1BFC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1C00) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1C04) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CRDT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1CC0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CRDT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1CC4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CRDT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1CC8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_IFIFO_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1DB8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CMDIDX_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1DBC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1DC0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1DC4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1DC8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x1DCC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x1DD0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x1DD4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x1DD8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x1DDC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x1DE0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x1DE4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x1DE8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x1DEC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x1DF0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x1DF4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x1DF8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x1DFC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1E00) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1E04) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1E08) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_19_REG (CSR_PERX_CSR_BASE + 0x1E0C) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_IPSURX_CYC_CNT_REG (CSR_PERX_CSR_BASE + 0x1EC0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_IPSURX_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1EC8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_DGST_ERR_CNT_REG (CSR_PERX_CSR_BASE + 0x1ED0) /* Digest校验错误计数器 */ +#define CSR_PERX_CSR_PERX_SECTOR_GRD_ILGL_CNT_REG (CSR_PERX_CSR_BASE + 0x1ED8) /* 扇区guard域段校验错误计数器 */ +#define CSR_PERX_CSR_PERX_SECTOR_REF_ILGL_CNT_REG (CSR_PERX_CSR_BASE + 0x1EE0) /* 扇区REF域段校验错误计数器 */ +#define CSR_PERX_CSR_PERX_SECTOR_APP_ILGL_CNT_REG (CSR_PERX_CSR_BASE + 0x1EE8) /* 扇区APP域段校验错误计数器 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_DFX_CLR_REG (CSR_PERX_CSR_BASE + 0x1EF0) /* PERX DIF/DIX错误DFX清除寄存器 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW0_REG (CSR_PERX_CSR_BASE + 0x1EF8) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW1_REG (CSR_PERX_CSR_BASE + 0x1F00) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW2_REG (CSR_PERX_CSR_BASE + 0x1F08) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW3_REG (CSR_PERX_CSR_BASE + 0x1F10) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW4_REG (CSR_PERX_CSR_BASE + 0x1F18) /* PERX DIF/DIX错误信息 */ + +#endif // PE_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_c_union_define.h new file mode 100644 index 000000000..34ddfecbd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_c_union_define.h @@ -0,0 +1,2091 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : pqm_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:57:27 Create file +// ****************************************************************************** + +#ifndef PQM_C_UNION_DEFINE_H +#define PQM_C_UNION_DEFINE_H + +/* Define the union csr_pqm_edition_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_edition_u; + +/* Define the union csr_pqm_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_wgt_initctab_start : 1; /* [0] */ + u32 pqm_shaper_initctab_start : 1; /* [1] */ + u32 pqm_sch_initctab_start : 1; /* [2] */ + u32 pqm_cfg_initctab_start : 1; /* [3] */ + u32 rsv_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_initctab_start_u; + +/* Define the union csr_pqm_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_initctab_done : 1; /* [0] */ + u32 rsv_1 : 15; /* [15:1] */ + u32 pqm_wgt_init_done : 1; /* [16] */ + u32 pqm_shaper_init_done : 1; /* [17] */ + u32 pqm_sch_init_done : 1; /* [18] */ + u32 pqm_cfg_init_done : 1; /* [19] */ + u32 rsv_2 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_initctab_done_u; + +/* Define the union csr_pqm_cfg_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_cfg_ok : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_cfg_ok_u; + +/* Define the union csr_pqm_initlogic_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_initlogic_done : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_initlogic_done_u; + +/* Define the union csr_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ecc_bypass_en_u; + +/* Define the union csr_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_pqm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_7 : 3; /* [26:24] */ + u32 pqm_enable : 1; /* [27] */ + u32 pqm_int_issue : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_int_vector_u; + +/* Define the union csr_pqm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_int_data : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 pqm_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_int_u; + +/* Define the union csr_pqm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_int_en : 12; /* [11:0] */ + u32 rsv_10 : 4; /* [15:12] */ + u32 pqm_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_int_en_u; + +/* Define the union csr_pqm_mem_err_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_0 : 1; /* [0] */ + u32 pqm_mem_err_req_1 : 1; /* [1] */ + u32 pqm_mem_err_req_2 : 1; /* [2] */ + u32 pqm_mem_err_req_3 : 1; /* [3] */ + u32 pqm_mem_err_req_4 : 1; /* [4] */ + u32 pqm_mem_err_req_5 : 1; /* [5] */ + u32 pqm_mem_err_req_6 : 1; /* [6] */ + u32 pqm_mem_err_req_7 : 1; /* [7] */ + u32 pqm_mem_err_req_8 : 1; /* [8] */ + u32 pqm_mem_err_req_9 : 1; /* [9] */ + u32 pqm_mem_err_req_10 : 1; /* [10] */ + u32 pqm_mem_err_req_11 : 1; /* [11] */ + u32 pqm_mem_err_req_12 : 1; /* [12] */ + u32 pqm_mem_err_req_13 : 1; /* [13] */ + u32 pqm_mem_err_req_14 : 1; /* [14] */ + u32 pqm_mem_err_req_15 : 1; /* [15] */ + u32 pqm_mem_err_req_16 : 1; /* [16] */ + u32 pqm_mem_err_req_17 : 1; /* [17] */ + u32 pqm_mem_err_req_18 : 1; /* [18] */ + u32 pqm_mem_err_req_19 : 1; /* [19] */ + u32 pqm_mem_err_req_20 : 1; /* [20] */ + u32 pqm_mem_err_req_21 : 1; /* [21] */ + u32 pqm_mem_err_req_22 : 1; /* [22] */ + u32 pqm_mem_err_req_23 : 1; /* [23] */ + u32 pqm_mem_err_req_24 : 1; /* [24] */ + u32 pqm_mem_err_req_25 : 1; /* [25] */ + u32 pqm_mem_err_req_26 : 1; /* [26] */ + u32 pqm_mem_err_req_27 : 1; /* [27] */ + u32 pqm_mem_err_req_28 : 1; /* [28] */ + u32 pqm_mem_err_req_29 : 1; /* [29] */ + u32 pqm_mem_err_req_30 : 1; /* [30] */ + u32 pqm_mem_err_req_31 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req0_u; + +/* Define the union csr_pqm_mem_err_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_32 : 1; /* [0] */ + u32 pqm_mem_err_req_33 : 1; /* [1] */ + u32 pqm_mem_err_req_34 : 1; /* [2] */ + u32 pqm_mem_err_req_35 : 1; /* [3] */ + u32 pqm_mem_err_req_36 : 1; /* [4] */ + u32 pqm_mem_err_req_37 : 1; /* [5] */ + u32 pqm_mem_err_req_38 : 1; /* [6] */ + u32 pqm_mem_err_req_39 : 1; /* [7] */ + u32 pqm_mem_err_req_40 : 1; /* [8] */ + u32 pqm_mem_err_req_41 : 1; /* [9] */ + u32 pqm_mem_err_req_42 : 1; /* [10] */ + u32 pqm_mem_err_req_43 : 1; /* [11] */ + u32 pqm_mem_err_req_44 : 1; /* [12] */ + u32 pqm_mem_err_req_45 : 1; /* [13] */ + u32 pqm_mem_err_req_46 : 1; /* [14] */ + u32 pqm_mem_err_req_47 : 1; /* [15] */ + u32 pqm_mem_err_req_48 : 1; /* [16] */ + u32 pqm_mem_err_req_49 : 1; /* [17] */ + u32 pqm_mem_err_req_50 : 1; /* [18] */ + u32 pqm_mem_err_req_51 : 1; /* [19] */ + u32 pqm_mem_err_req_52 : 1; /* [20] */ + u32 pqm_mem_err_req_53 : 1; /* [21] */ + u32 pqm_mem_err_req_54 : 1; /* [22] */ + u32 pqm_mem_err_req_55 : 1; /* [23] */ + u32 pqm_mem_err_req_56 : 1; /* [24] */ + u32 pqm_mem_err_req_57 : 1; /* [25] */ + u32 pqm_mem_err_req_58 : 1; /* [26] */ + u32 pqm_mem_err_req_59 : 1; /* [27] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req1_u; + +/* Define the union csr_pqm_mem_err_req2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_64 : 1; /* [0] */ + u32 pqm_mem_err_req_65 : 1; /* [1] */ + u32 pqm_mem_err_req_66 : 1; /* [2] */ + u32 pqm_mem_err_req_67 : 1; /* [3] */ + u32 pqm_mem_err_req_68 : 1; /* [4] */ + u32 pqm_mem_err_req_69 : 1; /* [5] */ + u32 pqm_mem_err_req_70 : 1; /* [6] */ + u32 pqm_mem_err_req_71 : 1; /* [7] */ + u32 pqm_mem_err_req_72 : 1; /* [8] */ + u32 pqm_mem_err_req_73 : 1; /* [9] */ + u32 pqm_mem_err_req_74 : 1; /* [10] */ + u32 pqm_mem_err_req_75 : 1; /* [11] */ + u32 pqm_mem_err_req_76 : 1; /* [12] */ + u32 pqm_mem_err_req_77 : 1; /* [13] */ + u32 pqm_mem_err_req_78 : 1; /* [14] */ + u32 pqm_mem_err_req_79 : 1; /* [15] */ + u32 pqm_mem_err_req_80 : 1; /* [16] */ + u32 pqm_mem_err_req_81 : 1; /* [17] */ + u32 pqm_mem_err_req_82 : 1; /* [18] */ + u32 pqm_mem_err_req_83 : 1; /* [19] */ + u32 pqm_mem_err_req_84 : 1; /* [20] */ + u32 pqm_mem_err_req_85 : 1; /* [21] */ + u32 pqm_mem_err_req_86 : 1; /* [22] */ + u32 pqm_mem_err_req_87 : 1; /* [23] */ + u32 pqm_mem_err_req_88 : 1; /* [24] */ + u32 pqm_mem_err_req_89 : 1; /* [25] */ + u32 pqm_mem_err_req_90 : 1; /* [26] */ + u32 pqm_mem_err_req_91 : 1; /* [27] */ + u32 pqm_mem_err_req_92 : 1; /* [28] */ + u32 pqm_mem_err_req_93 : 1; /* [29] */ + u32 pqm_mem_err_req_94 : 1; /* [30] */ + u32 pqm_mem_err_req_95 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req2_u; + +/* Define the union csr_pqm_mem_err_req3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_96 : 1; /* [0] */ + u32 pqm_mem_err_req_97 : 1; /* [1] */ + u32 pqm_mem_err_req_98 : 1; /* [2] */ + u32 pqm_mem_err_req_99 : 1; /* [3] */ + u32 pqm_mem_err_req_100 : 1; /* [4] */ + u32 pqm_mem_err_req_101 : 1; /* [5] */ + u32 pqm_mem_err_req_102 : 1; /* [6] */ + u32 pqm_mem_err_req_103 : 1; /* [7] */ + u32 pqm_mem_err_req_104 : 1; /* [8] */ + u32 pqm_mem_err_req_105 : 1; /* [9] */ + u32 pqm_mem_err_req_106 : 1; /* [10] */ + u32 pqm_mem_err_req_107 : 1; /* [11] */ + u32 pqm_mem_err_req_108 : 1; /* [12] */ + u32 pqm_mem_err_req_109 : 1; /* [13] */ + u32 pqm_mem_err_req_110 : 1; /* [14] */ + u32 pqm_mem_err_req_111 : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req3_u; + +/* Define the union csr_pqm_ecc_one_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_1bit_err : 1; /* [0] */ + u32 pqm_ecc_1bit_err_insrt : 1; /* [1] */ + u32 pqm_ecc_1bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_one_bit_int_u; + +/* Define the union csr_pqm_ecc_two_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_2bit_err : 1; /* [0] */ + u32 pqm_ecc_2bit_err_insrt : 1; /* [1] */ + u32 pqm_ecc_2bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_two_bit_int_u; + +/* Define the union csr_pqm_mq_bind_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_bind_cfg_err : 1; /* [0] */ + u32 pqm_bind_cfg_err_insrt : 1; /* [1] */ + u32 pqm_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mq_bind_int_u; + +/* Define the union csr_pqm_mq_bind_mcd_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mcd_bind_cfg_err : 1; /* [0] */ + u32 pqm_mcd_bind_cfg_err_insrt : 1; /* [1] */ + u32 pqm_mcd_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mq_bind_mcd_int_u; + +/* Define the union csr_pqm_fifo_int0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int0_err0 : 1; /* [0] */ + u32 pqm_fifo_int0_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int0_err1 : 1; /* [2] */ + u32 pqm_fifo_int0_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int0_err2 : 1; /* [4] */ + u32 pqm_fifo_int0_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int0_err3 : 1; /* [6] */ + u32 pqm_fifo_int0_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int0_err4 : 1; /* [8] */ + u32 pqm_fifo_int0_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int0_err5 : 1; /* [10] */ + u32 pqm_fifo_int0_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int0_err6 : 1; /* [12] */ + u32 pqm_fifo_int0_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int0_err7 : 1; /* [14] */ + u32 pqm_fifo_int0_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int0_err8 : 1; /* [16] */ + u32 pqm_fifo_int0_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int0_err9 : 1; /* [18] */ + u32 pqm_fifo_int0_err9_insrt : 1; /* [19] */ + u32 rsv_13 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int0_u; + +/* Define the union csr_pqm_fifo_int0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int0_err0_en : 1; /* [0] */ + u32 pqm_fifo_int0_err1_en : 1; /* [1] */ + u32 pqm_fifo_int0_err2_en : 1; /* [2] */ + u32 pqm_fifo_int0_err3_en : 1; /* [3] */ + u32 pqm_fifo_int0_err4_en : 1; /* [4] */ + u32 pqm_fifo_int0_err5_en : 1; /* [5] */ + u32 pqm_fifo_int0_err6_en : 1; /* [6] */ + u32 pqm_fifo_int0_err7_en : 1; /* [7] */ + u32 pqm_fifo_int0_err8_en : 1; /* [8] */ + u32 pqm_fifo_int0_err9_en : 1; /* [9] */ + u32 rsv_14 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int0_mask_u; + +/* Define the union csr_pqm_fifo_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int1_err0 : 1; /* [0] */ + u32 pqm_fifo_int1_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int1_err1 : 1; /* [2] */ + u32 pqm_fifo_int1_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int1_err2 : 1; /* [4] */ + u32 pqm_fifo_int1_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int1_err3 : 1; /* [6] */ + u32 pqm_fifo_int1_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int1_err4 : 1; /* [8] */ + u32 pqm_fifo_int1_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int1_err5 : 1; /* [10] */ + u32 pqm_fifo_int1_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int1_err6 : 1; /* [12] */ + u32 pqm_fifo_int1_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int1_err7 : 1; /* [14] */ + u32 pqm_fifo_int1_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int1_err8 : 1; /* [16] */ + u32 pqm_fifo_int1_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int1_err9 : 1; /* [18] */ + u32 pqm_fifo_int1_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int1_err10 : 1; /* [20] */ + u32 pqm_fifo_int1_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int1_err11 : 1; /* [22] */ + u32 pqm_fifo_int1_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int1_err12 : 1; /* [24] */ + u32 pqm_fifo_int1_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int1_err13 : 1; /* [26] */ + u32 pqm_fifo_int1_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int1_err14 : 1; /* [28] */ + u32 pqm_fifo_int1_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int1_err15 : 1; /* [30] */ + u32 pqm_fifo_int1_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int1_u; + +/* Define the union csr_pqm_fifo_int1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int1_err0_en : 1; /* [0] */ + u32 pqm_fifo_int1_err1_en : 1; /* [1] */ + u32 pqm_fifo_int1_err2_en : 1; /* [2] */ + u32 pqm_fifo_int1_err3_en : 1; /* [3] */ + u32 pqm_fifo_int1_err4_en : 1; /* [4] */ + u32 pqm_fifo_int1_err5_en : 1; /* [5] */ + u32 pqm_fifo_int1_err6_en : 1; /* [6] */ + u32 pqm_fifo_int1_err7_en : 1; /* [7] */ + u32 pqm_fifo_int1_err8_en : 1; /* [8] */ + u32 pqm_fifo_int1_err9_en : 1; /* [9] */ + u32 pqm_fifo_int1_err10_en : 1; /* [10] */ + u32 pqm_fifo_int1_err11_en : 1; /* [11] */ + u32 pqm_fifo_int1_err12_en : 1; /* [12] */ + u32 pqm_fifo_int1_err13_en : 1; /* [13] */ + u32 pqm_fifo_int1_err14_en : 1; /* [14] */ + u32 pqm_fifo_int1_err15_en : 1; /* [15] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int1_mask_u; + +/* Define the union csr_pqm_fifo_int2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int2_err0 : 1; /* [0] */ + u32 pqm_fifo_int2_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int2_err1 : 1; /* [2] */ + u32 pqm_fifo_int2_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int2_err2 : 1; /* [4] */ + u32 pqm_fifo_int2_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int2_err3 : 1; /* [6] */ + u32 pqm_fifo_int2_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int2_err4 : 1; /* [8] */ + u32 pqm_fifo_int2_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int2_err5 : 1; /* [10] */ + u32 pqm_fifo_int2_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int2_err6 : 1; /* [12] */ + u32 pqm_fifo_int2_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int2_err7 : 1; /* [14] */ + u32 pqm_fifo_int2_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int2_err8 : 1; /* [16] */ + u32 pqm_fifo_int2_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int2_err9 : 1; /* [18] */ + u32 pqm_fifo_int2_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int2_err10 : 1; /* [20] */ + u32 pqm_fifo_int2_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int2_err11 : 1; /* [22] */ + u32 pqm_fifo_int2_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int2_err12 : 1; /* [24] */ + u32 pqm_fifo_int2_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int2_err13 : 1; /* [26] */ + u32 pqm_fifo_int2_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int2_err14 : 1; /* [28] */ + u32 pqm_fifo_int2_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int2_err15 : 1; /* [30] */ + u32 pqm_fifo_int2_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int2_u; + +/* Define the union csr_pqm_fifo_int2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int2_err0_en : 1; /* [0] */ + u32 pqm_fifo_int2_err1_en : 1; /* [1] */ + u32 pqm_fifo_int2_err2_en : 1; /* [2] */ + u32 pqm_fifo_int2_err3_en : 1; /* [3] */ + u32 pqm_fifo_int2_err4_en : 1; /* [4] */ + u32 pqm_fifo_int2_err5_en : 1; /* [5] */ + u32 pqm_fifo_int2_err6_en : 1; /* [6] */ + u32 pqm_fifo_int2_err7_en : 1; /* [7] */ + u32 pqm_fifo_int2_err8_en : 1; /* [8] */ + u32 pqm_fifo_int2_err9_en : 1; /* [9] */ + u32 pqm_fifo_int2_err10_en : 1; /* [10] */ + u32 pqm_fifo_int2_err11_en : 1; /* [11] */ + u32 pqm_fifo_int2_err12_en : 1; /* [12] */ + u32 pqm_fifo_int2_err13_en : 1; /* [13] */ + u32 pqm_fifo_int2_err14_en : 1; /* [14] */ + u32 pqm_fifo_int2_err15_en : 1; /* [15] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int2_mask_u; + +/* Define the union csr_pqm_fifo_int3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int3_err0 : 1; /* [0] */ + u32 pqm_fifo_int3_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int3_err1 : 1; /* [2] */ + u32 pqm_fifo_int3_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int3_err2 : 1; /* [4] */ + u32 pqm_fifo_int3_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int3_err3 : 1; /* [6] */ + u32 pqm_fifo_int3_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int3_err4 : 1; /* [8] */ + u32 pqm_fifo_int3_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int3_err5 : 1; /* [10] */ + u32 pqm_fifo_int3_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int3_err6 : 1; /* [12] */ + u32 pqm_fifo_int3_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int3_err7 : 1; /* [14] */ + u32 pqm_fifo_int3_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int3_err8 : 1; /* [16] */ + u32 pqm_fifo_int3_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int3_err9 : 1; /* [18] */ + u32 pqm_fifo_int3_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int3_err10 : 1; /* [20] */ + u32 pqm_fifo_int3_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int3_err11 : 1; /* [22] */ + u32 pqm_fifo_int3_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int3_err12 : 1; /* [24] */ + u32 pqm_fifo_int3_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int3_err13 : 1; /* [26] */ + u32 pqm_fifo_int3_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int3_err14 : 1; /* [28] */ + u32 pqm_fifo_int3_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int3_err15 : 1; /* [30] */ + u32 pqm_fifo_int3_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int3_u; + +/* Define the union csr_pqm_fifo_int3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int3_err0_en : 1; /* [0] */ + u32 pqm_fifo_int3_err1_en : 1; /* [1] */ + u32 pqm_fifo_int3_err2_en : 1; /* [2] */ + u32 pqm_fifo_int3_err3_en : 1; /* [3] */ + u32 pqm_fifo_int3_err4_en : 1; /* [4] */ + u32 pqm_fifo_int3_err5_en : 1; /* [5] */ + u32 pqm_fifo_int3_err6_en : 1; /* [6] */ + u32 pqm_fifo_int3_err7_en : 1; /* [7] */ + u32 pqm_fifo_int3_err8_en : 1; /* [8] */ + u32 pqm_fifo_int3_err9_en : 1; /* [9] */ + u32 pqm_fifo_int3_err10_en : 1; /* [10] */ + u32 pqm_fifo_int3_err11_en : 1; /* [11] */ + u32 pqm_fifo_int3_err12_en : 1; /* [12] */ + u32 pqm_fifo_int3_err13_en : 1; /* [13] */ + u32 pqm_fifo_int3_err14_en : 1; /* [14] */ + u32 pqm_fifo_int3_err15_en : 1; /* [15] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int3_mask_u; + +/* Define the union csr_pqm_fifo_int4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int4_err0 : 1; /* [0] */ + u32 pqm_fifo_int4_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int4_err1 : 1; /* [2] */ + u32 pqm_fifo_int4_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int4_err2 : 1; /* [4] */ + u32 pqm_fifo_int4_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int4_err3 : 1; /* [6] */ + u32 pqm_fifo_int4_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int4_err4 : 1; /* [8] */ + u32 pqm_fifo_int4_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int4_err5 : 1; /* [10] */ + u32 pqm_fifo_int4_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int4_err6 : 1; /* [12] */ + u32 pqm_fifo_int4_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int4_err7 : 1; /* [14] */ + u32 pqm_fifo_int4_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int4_err8 : 1; /* [16] */ + u32 pqm_fifo_int4_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int4_err9 : 1; /* [18] */ + u32 pqm_fifo_int4_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int4_err10 : 1; /* [20] */ + u32 pqm_fifo_int4_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int4_err11 : 1; /* [22] */ + u32 pqm_fifo_int4_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int4_err12 : 1; /* [24] */ + u32 pqm_fifo_int4_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int4_err13 : 1; /* [26] */ + u32 pqm_fifo_int4_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int4_err14 : 1; /* [28] */ + u32 pqm_fifo_int4_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int4_err15 : 1; /* [30] */ + u32 pqm_fifo_int4_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int4_u; + +/* Define the union csr_pqm_fifo_int4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int4_err0_en : 1; /* [0] */ + u32 pqm_fifo_int4_err1_en : 1; /* [1] */ + u32 pqm_fifo_int4_err2_en : 1; /* [2] */ + u32 pqm_fifo_int4_err3_en : 1; /* [3] */ + u32 pqm_fifo_int4_err4_en : 1; /* [4] */ + u32 pqm_fifo_int4_err5_en : 1; /* [5] */ + u32 pqm_fifo_int4_err6_en : 1; /* [6] */ + u32 pqm_fifo_int4_err7_en : 1; /* [7] */ + u32 pqm_fifo_int4_err8_en : 1; /* [8] */ + u32 pqm_fifo_int4_err9_en : 1; /* [9] */ + u32 pqm_fifo_int4_err10_en : 1; /* [10] */ + u32 pqm_fifo_int4_err11_en : 1; /* [11] */ + u32 pqm_fifo_int4_err12_en : 1; /* [12] */ + u32 pqm_fifo_int4_err13_en : 1; /* [13] */ + u32 pqm_fifo_int4_err14_en : 1; /* [14] */ + u32 pqm_fifo_int4_err15_en : 1; /* [15] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int4_mask_u; + +/* Define the union csr_pqm_fifo_int5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int5_err0 : 1; /* [0] */ + u32 pqm_fifo_int5_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int5_err1 : 1; /* [2] */ + u32 pqm_fifo_int5_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int5_err2 : 1; /* [4] */ + u32 pqm_fifo_int5_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int5_err3 : 1; /* [6] */ + u32 pqm_fifo_int5_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int5_err4 : 1; /* [8] */ + u32 pqm_fifo_int5_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int5_err5 : 1; /* [10] */ + u32 pqm_fifo_int5_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int5_err6 : 1; /* [12] */ + u32 pqm_fifo_int5_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int5_err7 : 1; /* [14] */ + u32 pqm_fifo_int5_err7_insrt : 1; /* [15] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int5_u; + +/* Define the union csr_pqm_fifo_int5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int5_err0_en : 1; /* [0] */ + u32 pqm_fifo_int5_err1_en : 1; /* [1] */ + u32 pqm_fifo_int5_err2_en : 1; /* [2] */ + u32 pqm_fifo_int5_err3_en : 1; /* [3] */ + u32 pqm_fifo_int5_err4_en : 1; /* [4] */ + u32 pqm_fifo_int5_err5_en : 1; /* [5] */ + u32 pqm_fifo_int5_err6_en : 1; /* [6] */ + u32 pqm_fifo_int5_err7_en : 1; /* [7] */ + u32 rsv_20 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int5_mask_u; + +/* Define the union csr_pqm_rx_ring_e0_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ring_e0_err : 1; /* [0] */ + u32 pqm_ring_e0_err_insert : 1; /* [1] */ + u32 pqm_ring_e0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rx_ring_e0_err_int_u; + +/* Define the union csr_pqm_rx_ring_e1_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ring_e1_err : 1; /* [0] */ + u32 pqm_ring_e1_err_insert : 1; /* [1] */ + u32 pqm_ring_e1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rx_ring_e1_err_int_u; + +/* Define the union csr_pqm_fifo_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo0_st0 : 2; /* [1:0] */ + u32 pqm_fifo1_st0 : 2; /* [3:2] */ + u32 pqm_fifo2_st0 : 2; /* [5:4] */ + u32 pqm_fifo3_st0 : 2; /* [7:6] */ + u32 pqm_fifo4_st0 : 2; /* [9:8] */ + u32 pqm_fifo5_st0 : 2; /* [11:10] */ + u32 pqm_fifo6_st0 : 2; /* [13:12] */ + u32 pqm_fifo7_st0 : 2; /* [15:14] */ + u32 pqm_fifo8_st0 : 2; /* [17:16] */ + u32 pqm_fifo9_st0 : 2; /* [19:18] */ + u32 pqm_fifo10_st0 : 2; /* [21:20] */ + u32 pqm_fifo11_st0 : 2; /* [23:22] */ + u32 pqm_fifo12_st0 : 2; /* [25:24] */ + u32 rsv_21 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_st0_u; + +/* Define the union csr_pqm_fifo_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo0_st1 : 2; /* [1:0] */ + u32 pqm_fifo1_st1 : 2; /* [3:2] */ + u32 pqm_fifo2_st1 : 2; /* [5:4] */ + u32 pqm_fifo3_st1 : 2; /* [7:6] */ + u32 pqm_fifo4_st1 : 2; /* [9:8] */ + u32 pqm_fifo5_st1 : 2; /* [11:10] */ + u32 pqm_fifo6_st1 : 2; /* [13:12] */ + u32 pqm_fifo7_st1 : 2; /* [15:14] */ + u32 pqm_fifo8_st1 : 2; /* [17:16] */ + u32 pqm_fifo9_st1 : 2; /* [19:18] */ + u32 pqm_fifo10_st1 : 2; /* [21:20] */ + u32 pqm_fifo11_st1 : 2; /* [23:22] */ + u32 pqm_fifo12_st1 : 2; /* [25:24] */ + u32 pqm_fifo13_st1 : 2; /* [27:26] */ + u32 pqm_fifo14_st1 : 2; /* [29:28] */ + u32 pqm_fifo15_st1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_st1_u; + +/* Define the union csr_pqm_fifo_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo0_st2 : 2; /* [1:0] */ + u32 pqm_fifo1_st2 : 2; /* [3:2] */ + u32 pqm_fifo2_st2 : 2; /* [5:4] */ + u32 pqm_fifo3_st2 : 2; /* [7:6] */ + u32 pqm_fifo4_st2 : 2; /* [9:8] */ + u32 pqm_fifo5_st2 : 2; /* [11:10] */ + u32 pqm_fifo6_st2 : 2; /* [13:12] */ + u32 pqm_fifo7_st2 : 2; /* [15:14] */ + u32 pqm_fifo8_st2 : 2; /* [17:16] */ + u32 pqm_fifo9_st2 : 2; /* [19:18] */ + u32 pqm_fifo10_st2 : 2; /* [21:20] */ + u32 pqm_fifo11_st2 : 2; /* [23:22] */ + u32 rsv_22 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_st2_u; + +/* Define the union csr_pqm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv0_u; + +/* Define the union csr_pqm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv1_u; + +/* Define the union csr_pqm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv2_u; + +/* Define the union csr_pqm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv3_u; + +/* Define the union csr_pqm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_addr : 20; /* [19:0] */ + u32 pqm_indrect_tab : 8; /* [27:20] */ + u32 pqm_indrect_stat : 2; /* [29:28] */ + u32 pqm_indrect_mode : 1; /* [30] */ + u32 pqm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_ctrl_u; + +/* Define the union csr_pqm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_timeout_u; + +/* Define the union csr_pqm_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_data_0_u; + +/* Define the union csr_pqm_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_data_1_u; + +/* Define the union csr_pqm_pass_through_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_passthru_enable : 1; /* [0] */ + u32 rsv_23 : 7; /* [7:1] */ + u32 pqm_passthru_wgt_cfg : 3; /* [10:8] */ + u32 rsv_24 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_pass_through_cfg_u; + +/* Define the union csr_pqm_weight_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_cos_weight_offset : 5; /* [4:0] */ + u32 rsv_25 : 3; /* [7:5] */ + u32 pqm_ep_weight_offset : 5; /* [12:8] */ + u32 rsv_26 : 3; /* [15:13] */ + u32 pqm_host_weight_offset : 5; /* [20:16] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_weight_offset_u; + +/* Define the union csr_pqm_pps_shaper_cfg_pktlen_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_pps_typical_pktlen_cfg : 3; /* [2:0] */ + u32 rsv_28 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_pps_shaper_cfg_pktlen_u; + +/* Define the union csr_pqm_root_sch_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_root_sch_wgt_cfg : 3; /* [2:0] */ + u32 rsv_29 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_root_sch_weight_cfg_u; + +/* Define the union csr_host_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_weight_cfg : 8; /* [7:0] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_weight_u; + +/* Define the union csr_host_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_31 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_bps_cfg_u; + +/* Define the union csr_host_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_32 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_pps_cfg_u; + +/* Define the union csr_ep_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_weight_cfg : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_u; + +/* Define the union csr_ep_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_u; + +/* Define the union csr_ep_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_35 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_u; + +/* Define the union csr_pqm_shap_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_nmq_shap_byp_vld : 1; /* [0] */ + u32 pqm_vnic_shap_byp_vld : 1; /* [1] */ + u32 pqm_vnicgrp_shap_byp_vld : 1; /* [2] */ + u32 pqm_ep_shap_byp_vld : 1; /* [3] */ + u32 pqm_host_shap_byp_vld : 1; /* [4] */ + u32 rsv_36 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_shap_bypass_cfg_u; + +/* Define the union csr_pqm_host_ep_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_hostep_xon_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_ep_xon_cfg_u; + +/* Define the union csr_pqm_host_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_xon_cfg : 4; /* [3:0] */ + u32 msc_root_xon_cfg : 1; /* [4] */ + u32 rsv_37 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_xon_cfg_u; + +/* Define the union csr_pqm_host_ep_bps_spf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_hostep_bps_spf_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_ep_bps_spf_st_u; + +/* Define the union csr_pqm_host_ep_pps_spf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_hostep_pps_spf_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_ep_pps_spf_st_u; + +/* Define the union csr_pqm_host_spf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_bps_spf_st : 4; /* [3:0] */ + u32 msc_host_pps_spf_st : 4; /* [7:4] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_spf_st_u; + +/* Define the union csr_pqm_sch_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_host_bp : 4; /* [3:0] */ + u32 pqm_scan_bp : 1; /* [4] */ + u32 rsv_39 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_sch_bp_sta_u; + +/* Define the union csr_pqm_sch_ep_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ep_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_sch_ep_bp_sta_u; + +/* Define the union csr_pqm_fifo_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_du_fifo_gap : 5; /* [4:0] */ + u32 rsv_40 : 3; /* [7:5] */ + u32 pqm_pt_fifo_gap : 5; /* [12:8] */ + u32 rsv_41 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_th_cfg_u; + +/* Define the union csr_pqm_dpl_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dpl_plen : 16; /* [15:0] */ + u32 pqm_dpl_pnum : 4; /* [19:16] */ + u32 rsv_42 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_dpl_info_ptr0_u; + +/* Define the union csr_pqm_dpl_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dpl_pqid : 14; /* [13:0] */ + u32 rsv_43 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_dpl_info_ptr1_u; + +/* Define the union csr_pqm_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mcd_plen : 19; /* [18:0] */ + u32 rsv_44 : 5; /* [23:19] */ + u32 pqm_mcd_pnum : 5; /* [28:24] */ + u32 rsv_45 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mcd_du_info_ptr0_u; + +/* Define the union csr_pqm_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mcd_pqid : 14; /* [13:0] */ + u32 rsv_46 : 2; /* [15:14] */ + u32 pqm_mcd_color : 3; /* [18:16] */ + u32 rsv_47 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mcd_du_info_ptr1_u; + +/* Define the union csr_pqm_uncrt_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_mask : 1; /* [0] */ + u32 other_uncrt_err_mask : 1; /* [1] */ + u32 rsv_48 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_uncrt_err_mask_u; + +/* Define the union csr_pqm_uncrt_err_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_clr : 1; /* [0] */ + u32 other_uncrt_err_clr : 1; /* [1] */ + u32 rsv_49 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_uncrt_err_clr_u; + +/* Define the union csr_pq_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_eqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_eqs_cnt_u; + +/* Define the union csr_pq_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_dqs_cnt_u; + +/* Define the union csr_pq_empt_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_empt_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_empt_dqs_cnt_u; + +/* Define the union csr_pq_sch_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_sch_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_sch_dqr_cnt_u; + +/* Define the union csr_pq_sch_empt_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_sch_empt_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_sch_empt_dqr_cnt_u; + +/* Define the union csr_pq_pt_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_pt_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_pt_dqr_cnt_u; + +/* Define the union csr_pq_dpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_dpl_cnt_u; + +/* Define the union csr_pq_du_vld_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_du_info_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_du_vld_cnt_u; + +/* Define the union csr_pq_du_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_du_info_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_du_err_cnt_u; + +/* Define the union csr_pqm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_1bit_err_cnt_u; + +/* Define the union csr_pqm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_2bit_err_cnt_u; + +/* Define the union csr_sch_pq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_cfg : 14; /* [13:0] */ + u32 rsv_50 : 2; /* [15:14] */ + u32 sch_pq_dfx_cfg_vld : 1; /* [16] */ + u32 rsv_51 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_cfg_u; + +/* Define the union csr_sch_pq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_up_cnt_u; + +/* Define the union csr_sch_pq_dfx_empt_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_empt_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_empt_up_cnt_u; + +/* Define the union csr_sch_pq_dfx_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_sch_cnt_u; + +/* Define the union csr_sch_pq_dfx_pt_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_pt_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_pt_deq_cnt_u; + +/* Define the union csr_sch_pq_dfx_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_empt_sch_cnt_u; + +/* Define the union csr_sch_pq_dfx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_du_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_pqm_edition_u pqm_edition; /* 0 */ + volatile csr_pqm_initctab_start_u pqm_initctab_start; /* 4 */ + volatile csr_pqm_initctab_done_u pqm_initctab_done; /* 8 */ + volatile csr_pqm_cfg_ok_u pqm_cfg_ok; /* C */ + volatile csr_pqm_initlogic_done_u pqm_initlogic_done; /* 10 */ + volatile csr_mem_ecc_bypass_en_u mem_ecc_bypass_en; /* 14 */ + volatile csr_mem_ctrl_bus_cfg0_u mem_ctrl_bus_cfg0; /* 18 */ + volatile csr_mem_ctrl_bus_cfg1_u mem_ctrl_bus_cfg1; /* 1C */ + volatile csr_mem_ctrl_bus_cfg2_u mem_ctrl_bus_cfg2; /* 20 */ + volatile csr_mem_ctrl_bus_cfg3_u mem_ctrl_bus_cfg3; /* 24 */ + volatile csr_mem_ctrl_bus_cfg4_u mem_ctrl_bus_cfg4; /* 28 */ + volatile csr_pqm_int_vector_u pqm_int_vector; /* 100 */ + volatile csr_pqm_int_u pqm_int; /* 104 */ + volatile csr_pqm_int_en_u pqm_int_en; /* 108 */ + volatile csr_pqm_mem_err_req0_u pqm_mem_err_req0; /* 10C */ + volatile csr_pqm_mem_err_req1_u pqm_mem_err_req1; /* 110 */ + volatile csr_pqm_mem_err_req2_u pqm_mem_err_req2; /* 114 */ + volatile csr_pqm_mem_err_req3_u pqm_mem_err_req3; /* 118 */ + volatile csr_pqm_ecc_one_bit_int_u pqm_ecc_one_bit_int; /* 11C */ + volatile csr_pqm_ecc_two_bit_int_u pqm_ecc_two_bit_int; /* 120 */ + volatile csr_pqm_mq_bind_int_u pqm_mq_bind_int; /* 130 */ + volatile csr_pqm_mq_bind_mcd_int_u pqm_mq_bind_mcd_int; /* 134 */ + volatile csr_pqm_fifo_int0_u pqm_fifo_int0; /* 138 */ + volatile csr_pqm_fifo_int0_mask_u pqm_fifo_int0_mask; /* 13C */ + volatile csr_pqm_fifo_int1_u pqm_fifo_int1; /* 140 */ + volatile csr_pqm_fifo_int1_mask_u pqm_fifo_int1_mask; /* 144 */ + volatile csr_pqm_fifo_int2_u pqm_fifo_int2; /* 148 */ + volatile csr_pqm_fifo_int2_mask_u pqm_fifo_int2_mask; /* 14C */ + volatile csr_pqm_fifo_int3_u pqm_fifo_int3; /* 150 */ + volatile csr_pqm_fifo_int3_mask_u pqm_fifo_int3_mask; /* 154 */ + volatile csr_pqm_fifo_int4_u pqm_fifo_int4; /* 158 */ + volatile csr_pqm_fifo_int4_mask_u pqm_fifo_int4_mask; /* 15C */ + volatile csr_pqm_fifo_int5_u pqm_fifo_int5; /* 160 */ + volatile csr_pqm_fifo_int5_mask_u pqm_fifo_int5_mask; /* 164 */ + volatile csr_pqm_rx_ring_e0_err_int_u pqm_rx_ring_e0_err_int; /* 168 */ + volatile csr_pqm_rx_ring_e1_err_int_u pqm_rx_ring_e1_err_int; /* 16C */ + volatile csr_pqm_fifo_st0_u pqm_fifo_st0; /* 180 */ + volatile csr_pqm_fifo_st1_u pqm_fifo_st1; /* 184 */ + volatile csr_pqm_fifo_st2_u pqm_fifo_st2; /* 188 */ + volatile csr_pqm_rw_rsv0_u pqm_rw_rsv0; /* 300 */ + volatile csr_pqm_rw_rsv1_u pqm_rw_rsv1; /* 304 */ + volatile csr_pqm_rw_rsv2_u pqm_rw_rsv2; /* 308 */ + volatile csr_pqm_rw_rsv3_u pqm_rw_rsv3; /* 30C */ + volatile csr_pqm_indrect_ctrl_u pqm_indrect_ctrl; /* 310 */ + volatile csr_pqm_indrect_timeout_u pqm_indrect_timeout; /* 314 */ + volatile csr_pqm_indrect_data_0_u pqm_indrect_data_0; /* 318 */ + volatile csr_pqm_indrect_data_1_u pqm_indrect_data_1; /* 31C */ + volatile csr_pqm_pass_through_cfg_u pqm_pass_through_cfg; /* 320 */ + volatile csr_pqm_weight_offset_u pqm_weight_offset; /* 324 */ + volatile csr_pqm_pps_shaper_cfg_pktlen_u pqm_pps_shaper_cfg_pktlen; /* 328 */ + volatile csr_pqm_root_sch_weight_cfg_u pqm_root_sch_weight_cfg; /* 32C */ + volatile csr_host_weight_u host_weight[4]; /* 340 */ + volatile csr_host_shap_bps_cfg_u host_shap_bps_cfg[4]; /* 350 */ + volatile csr_host_shap_pps_cfg_u host_shap_pps_cfg[4]; /* 360 */ + volatile csr_ep_weight_u ep_weight[32]; /* 370 */ + volatile csr_ep_shap_bps_cfg_u ep_shap_bps_cfg[32]; /* 3F0 */ + volatile csr_ep_shap_pps_cfg_u ep_shap_pps_cfg[32]; /* 470 */ + volatile csr_pqm_shap_bypass_cfg_u pqm_shap_bypass_cfg; /* 4F0 */ + volatile csr_pqm_host_ep_xon_cfg_u pqm_host_ep_xon_cfg; /* 1000 */ + volatile csr_pqm_host_xon_cfg_u pqm_host_xon_cfg; /* 1004 */ + volatile csr_pqm_host_ep_bps_spf_st_u pqm_host_ep_bps_spf_st; /* 1008 */ + volatile csr_pqm_host_ep_pps_spf_st_u pqm_host_ep_pps_spf_st; /* 100C */ + volatile csr_pqm_host_spf_st_u pqm_host_spf_st; /* 1010 */ + volatile csr_pqm_sch_bp_sta_u pqm_sch_bp_sta; /* 1014 */ + volatile csr_pqm_sch_ep_bp_sta_u pqm_sch_ep_bp_sta; /* 1018 */ + volatile csr_pqm_fifo_th_cfg_u pqm_fifo_th_cfg; /* 101C */ + volatile csr_pqm_dpl_info_ptr0_u pqm_dpl_info_ptr0; /* 1020 */ + volatile csr_pqm_dpl_info_ptr1_u pqm_dpl_info_ptr1; /* 1024 */ + volatile csr_pqm_mcd_du_info_ptr0_u pqm_mcd_du_info_ptr0; /* 1028 */ + volatile csr_pqm_mcd_du_info_ptr1_u pqm_mcd_du_info_ptr1; /* 102C */ + volatile csr_pqm_uncrt_err_mask_u pqm_uncrt_err_mask; /* 1400 */ + volatile csr_pqm_uncrt_err_clr_u pqm_uncrt_err_clr; /* 1404 */ + volatile csr_pq_eqs_cnt_u pq_eqs_cnt; /* 1408 */ + volatile csr_pq_dqs_cnt_u pq_dqs_cnt; /* 140C */ + volatile csr_pq_empt_dqs_cnt_u pq_empt_dqs_cnt; /* 1410 */ + volatile csr_pq_sch_dqr_cnt_u pq_sch_dqr_cnt; /* 1414 */ + volatile csr_pq_sch_empt_dqr_cnt_u pq_sch_empt_dqr_cnt; /* 1418 */ + volatile csr_pq_pt_dqr_cnt_u pq_pt_dqr_cnt; /* 141C */ + volatile csr_pq_dpl_cnt_u pq_dpl_cnt; /* 1420 */ + volatile csr_pq_du_vld_cnt_u pq_du_vld_cnt; /* 1424 */ + volatile csr_pq_du_err_cnt_u pq_du_err_cnt; /* 1428 */ + volatile csr_pqm_ecc_1bit_err_cnt_u pqm_ecc_1bit_err_cnt; /* 142C */ + volatile csr_pqm_ecc_2bit_err_cnt_u pqm_ecc_2bit_err_cnt; /* 1430 */ + volatile csr_sch_pq_dfx_cfg_u sch_pq_dfx_cfg; /* 14A0 */ + volatile csr_sch_pq_dfx_up_cnt_u sch_pq_dfx_up_cnt; /* 14A4 */ + volatile csr_sch_pq_dfx_empt_up_cnt_u sch_pq_dfx_empt_up_cnt; /* 14A8 */ + volatile csr_sch_pq_dfx_sch_cnt_u sch_pq_dfx_sch_cnt; /* 14AC */ + volatile csr_sch_pq_dfx_pt_deq_cnt_u sch_pq_dfx_pt_deq_cnt; /* 14B0 */ + volatile csr_sch_pq_dfx_empt_sch_cnt_u sch_pq_dfx_empt_sch_cnt; /* 14B4 */ + volatile csr_sch_pq_dfx_du_cnt_u sch_pq_dfx_du_cnt; /* 14B8 */ +} S_pqm_top_REGS_TYPE; + +/* Declare the struct pointor of the module pqm_top */ +extern volatile S_pqm_top_REGS_TYPE *goppqm_topAllReg; + +/* Declare the functions that set the member value */ +int iSetPQM_EDITION_pqm_version(unsigned int upqm_version); +int iSetPQM_INITCTAB_START_pqm_wgt_initctab_start(unsigned int upqm_wgt_initctab_start); +int iSetPQM_INITCTAB_START_pqm_shaper_initctab_start(unsigned int upqm_shaper_initctab_start); +int iSetPQM_INITCTAB_START_pqm_sch_initctab_start(unsigned int upqm_sch_initctab_start); +int iSetPQM_INITCTAB_START_pqm_cfg_initctab_start(unsigned int upqm_cfg_initctab_start); +int iSetPQM_INITCTAB_DONE_pqm_initctab_done(unsigned int upqm_initctab_done); +int iSetPQM_INITCTAB_DONE_pqm_wgt_init_done(unsigned int upqm_wgt_init_done); +int iSetPQM_INITCTAB_DONE_pqm_shaper_init_done(unsigned int upqm_shaper_init_done); +int iSetPQM_INITCTAB_DONE_pqm_sch_init_done(unsigned int upqm_sch_init_done); +int iSetPQM_INITCTAB_DONE_pqm_cfg_init_done(unsigned int upqm_cfg_init_done); +int iSetPQM_CFG_OK_pqm_cfg_ok(unsigned int upqm_cfg_ok); +int iSetPQM_INITLOGIC_DONE_pqm_initlogic_done(unsigned int upqm_initlogic_done); +int iSetMEM_ECC_BYPASS_EN_pqm_mem_ecc_bypass(unsigned int upqm_mem_ecc_bypass); +int iSetMEM_CTRL_BUS_CFG0_pqm_mem_ctrl_bus_0(unsigned int upqm_mem_ctrl_bus_0); +int iSetMEM_CTRL_BUS_CFG1_pqm_mem_ctrl_bus_1(unsigned int upqm_mem_ctrl_bus_1); +int iSetMEM_CTRL_BUS_CFG2_pqm_mem_ctrl_bus_2(unsigned int upqm_mem_ctrl_bus_2); +int iSetMEM_CTRL_BUS_CFG3_pqm_mem_ctrl_bus_3(unsigned int upqm_mem_ctrl_bus_3); +int iSetMEM_CTRL_BUS_CFG4_pqm_mem_ctrl_bus_4(unsigned int upqm_mem_ctrl_bus_4); +int iSetPQM_INT_VECTOR_pqm_cpi_int_index(unsigned int upqm_cpi_int_index); +int iSetPQM_INT_VECTOR_pqm_enable(unsigned int upqm_enable); +int iSetPQM_INT_VECTOR_pqm_int_issue(unsigned int upqm_int_issue); +int iSetPQM_INT_pqm_int_data(unsigned int upqm_int_data); +int iSetPQM_INT_pqm_program_csr_id_ro(unsigned int upqm_program_csr_id_ro); +int iSetPQM_INT_EN_pqm_int_en(unsigned int upqm_int_en); +int iSetPQM_INT_EN_pqm_program_csr_id(unsigned int upqm_program_csr_id); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_0(unsigned int upqm_mem_err_req_0); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_1(unsigned int upqm_mem_err_req_1); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_2(unsigned int upqm_mem_err_req_2); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_3(unsigned int upqm_mem_err_req_3); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_4(unsigned int upqm_mem_err_req_4); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_5(unsigned int upqm_mem_err_req_5); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_6(unsigned int upqm_mem_err_req_6); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_7(unsigned int upqm_mem_err_req_7); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_8(unsigned int upqm_mem_err_req_8); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_9(unsigned int upqm_mem_err_req_9); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_10(unsigned int upqm_mem_err_req_10); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_11(unsigned int upqm_mem_err_req_11); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_12(unsigned int upqm_mem_err_req_12); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_13(unsigned int upqm_mem_err_req_13); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_14(unsigned int upqm_mem_err_req_14); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_15(unsigned int upqm_mem_err_req_15); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_16(unsigned int upqm_mem_err_req_16); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_17(unsigned int upqm_mem_err_req_17); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_18(unsigned int upqm_mem_err_req_18); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_19(unsigned int upqm_mem_err_req_19); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_20(unsigned int upqm_mem_err_req_20); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_21(unsigned int upqm_mem_err_req_21); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_22(unsigned int upqm_mem_err_req_22); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_23(unsigned int upqm_mem_err_req_23); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_24(unsigned int upqm_mem_err_req_24); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_25(unsigned int upqm_mem_err_req_25); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_26(unsigned int upqm_mem_err_req_26); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_27(unsigned int upqm_mem_err_req_27); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_28(unsigned int upqm_mem_err_req_28); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_29(unsigned int upqm_mem_err_req_29); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_30(unsigned int upqm_mem_err_req_30); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_31(unsigned int upqm_mem_err_req_31); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_32(unsigned int upqm_mem_err_req_32); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_33(unsigned int upqm_mem_err_req_33); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_34(unsigned int upqm_mem_err_req_34); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_35(unsigned int upqm_mem_err_req_35); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_36(unsigned int upqm_mem_err_req_36); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_37(unsigned int upqm_mem_err_req_37); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_38(unsigned int upqm_mem_err_req_38); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_39(unsigned int upqm_mem_err_req_39); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_40(unsigned int upqm_mem_err_req_40); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_41(unsigned int upqm_mem_err_req_41); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_42(unsigned int upqm_mem_err_req_42); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_43(unsigned int upqm_mem_err_req_43); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_44(unsigned int upqm_mem_err_req_44); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_45(unsigned int upqm_mem_err_req_45); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_46(unsigned int upqm_mem_err_req_46); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_47(unsigned int upqm_mem_err_req_47); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_48(unsigned int upqm_mem_err_req_48); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_49(unsigned int upqm_mem_err_req_49); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_50(unsigned int upqm_mem_err_req_50); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_51(unsigned int upqm_mem_err_req_51); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_52(unsigned int upqm_mem_err_req_52); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_53(unsigned int upqm_mem_err_req_53); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_54(unsigned int upqm_mem_err_req_54); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_55(unsigned int upqm_mem_err_req_55); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_56(unsigned int upqm_mem_err_req_56); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_57(unsigned int upqm_mem_err_req_57); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_58(unsigned int upqm_mem_err_req_58); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_59(unsigned int upqm_mem_err_req_59); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_64(unsigned int upqm_mem_err_req_64); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_65(unsigned int upqm_mem_err_req_65); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_66(unsigned int upqm_mem_err_req_66); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_67(unsigned int upqm_mem_err_req_67); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_68(unsigned int upqm_mem_err_req_68); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_69(unsigned int upqm_mem_err_req_69); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_70(unsigned int upqm_mem_err_req_70); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_71(unsigned int upqm_mem_err_req_71); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_72(unsigned int upqm_mem_err_req_72); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_73(unsigned int upqm_mem_err_req_73); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_74(unsigned int upqm_mem_err_req_74); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_75(unsigned int upqm_mem_err_req_75); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_76(unsigned int upqm_mem_err_req_76); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_77(unsigned int upqm_mem_err_req_77); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_78(unsigned int upqm_mem_err_req_78); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_79(unsigned int upqm_mem_err_req_79); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_80(unsigned int upqm_mem_err_req_80); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_81(unsigned int upqm_mem_err_req_81); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_82(unsigned int upqm_mem_err_req_82); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_83(unsigned int upqm_mem_err_req_83); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_84(unsigned int upqm_mem_err_req_84); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_85(unsigned int upqm_mem_err_req_85); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_86(unsigned int upqm_mem_err_req_86); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_87(unsigned int upqm_mem_err_req_87); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_88(unsigned int upqm_mem_err_req_88); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_89(unsigned int upqm_mem_err_req_89); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_90(unsigned int upqm_mem_err_req_90); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_91(unsigned int upqm_mem_err_req_91); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_92(unsigned int upqm_mem_err_req_92); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_93(unsigned int upqm_mem_err_req_93); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_94(unsigned int upqm_mem_err_req_94); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_95(unsigned int upqm_mem_err_req_95); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_96(unsigned int upqm_mem_err_req_96); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_97(unsigned int upqm_mem_err_req_97); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_98(unsigned int upqm_mem_err_req_98); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_99(unsigned int upqm_mem_err_req_99); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_100(unsigned int upqm_mem_err_req_100); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_101(unsigned int upqm_mem_err_req_101); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_102(unsigned int upqm_mem_err_req_102); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_103(unsigned int upqm_mem_err_req_103); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_104(unsigned int upqm_mem_err_req_104); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_105(unsigned int upqm_mem_err_req_105); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_106(unsigned int upqm_mem_err_req_106); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_107(unsigned int upqm_mem_err_req_107); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_108(unsigned int upqm_mem_err_req_108); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_109(unsigned int upqm_mem_err_req_109); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_110(unsigned int upqm_mem_err_req_110); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_111(unsigned int upqm_mem_err_req_111); +int iSetPQM_ECC_ONE_BIT_INT_pqm_ecc_1bit_err(unsigned int upqm_ecc_1bit_err); +int iSetPQM_ECC_ONE_BIT_INT_pqm_ecc_1bit_err_insrt(unsigned int upqm_ecc_1bit_err_insrt); +int iSetPQM_ECC_ONE_BIT_INT_pqm_ecc_1bit_err_info(unsigned int upqm_ecc_1bit_err_info); +int iSetPQM_ECC_TWO_BIT_INT_pqm_ecc_2bit_err(unsigned int upqm_ecc_2bit_err); +int iSetPQM_ECC_TWO_BIT_INT_pqm_ecc_2bit_err_insrt(unsigned int upqm_ecc_2bit_err_insrt); +int iSetPQM_ECC_TWO_BIT_INT_pqm_ecc_2bit_err_info(unsigned int upqm_ecc_2bit_err_info); +int iSetPQM_MQ_BIND_INT_pqm_bind_cfg_err(unsigned int upqm_bind_cfg_err); +int iSetPQM_MQ_BIND_INT_pqm_bind_cfg_err_insrt(unsigned int upqm_bind_cfg_err_insrt); +int iSetPQM_MQ_BIND_INT_pqm_bind_cfg_err_info(unsigned int upqm_bind_cfg_err_info); +int iSetPQM_MQ_BIND_MCD_INT_pqm_mcd_bind_cfg_err(unsigned int upqm_mcd_bind_cfg_err); +int iSetPQM_MQ_BIND_MCD_INT_pqm_mcd_bind_cfg_err_insrt(unsigned int upqm_mcd_bind_cfg_err_insrt); +int iSetPQM_MQ_BIND_MCD_INT_pqm_mcd_bind_cfg_err_info(unsigned int upqm_mcd_bind_cfg_err_info); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err0(unsigned int upqm_fifo_int0_err0); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err0_insrt(unsigned int upqm_fifo_int0_err0_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err1(unsigned int upqm_fifo_int0_err1); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err1_insrt(unsigned int upqm_fifo_int0_err1_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err2(unsigned int upqm_fifo_int0_err2); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err2_insrt(unsigned int upqm_fifo_int0_err2_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err3(unsigned int upqm_fifo_int0_err3); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err3_insrt(unsigned int upqm_fifo_int0_err3_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err4(unsigned int upqm_fifo_int0_err4); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err4_insrt(unsigned int upqm_fifo_int0_err4_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err5(unsigned int upqm_fifo_int0_err5); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err5_insrt(unsigned int upqm_fifo_int0_err5_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err6(unsigned int upqm_fifo_int0_err6); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err6_insrt(unsigned int upqm_fifo_int0_err6_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err7(unsigned int upqm_fifo_int0_err7); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err7_insrt(unsigned int upqm_fifo_int0_err7_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err8(unsigned int upqm_fifo_int0_err8); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err8_insrt(unsigned int upqm_fifo_int0_err8_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err9(unsigned int upqm_fifo_int0_err9); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err9_insrt(unsigned int upqm_fifo_int0_err9_insrt); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err0_en(unsigned int upqm_fifo_int0_err0_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err1_en(unsigned int upqm_fifo_int0_err1_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err2_en(unsigned int upqm_fifo_int0_err2_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err3_en(unsigned int upqm_fifo_int0_err3_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err4_en(unsigned int upqm_fifo_int0_err4_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err5_en(unsigned int upqm_fifo_int0_err5_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err6_en(unsigned int upqm_fifo_int0_err6_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err7_en(unsigned int upqm_fifo_int0_err7_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err8_en(unsigned int upqm_fifo_int0_err8_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err9_en(unsigned int upqm_fifo_int0_err9_en); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err0(unsigned int upqm_fifo_int1_err0); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err0_insrt(unsigned int upqm_fifo_int1_err0_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err1(unsigned int upqm_fifo_int1_err1); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err1_insrt(unsigned int upqm_fifo_int1_err1_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err2(unsigned int upqm_fifo_int1_err2); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err2_insrt(unsigned int upqm_fifo_int1_err2_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err3(unsigned int upqm_fifo_int1_err3); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err3_insrt(unsigned int upqm_fifo_int1_err3_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err4(unsigned int upqm_fifo_int1_err4); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err4_insrt(unsigned int upqm_fifo_int1_err4_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err5(unsigned int upqm_fifo_int1_err5); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err5_insrt(unsigned int upqm_fifo_int1_err5_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err6(unsigned int upqm_fifo_int1_err6); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err6_insrt(unsigned int upqm_fifo_int1_err6_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err7(unsigned int upqm_fifo_int1_err7); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err7_insrt(unsigned int upqm_fifo_int1_err7_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err8(unsigned int upqm_fifo_int1_err8); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err8_insrt(unsigned int upqm_fifo_int1_err8_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err9(unsigned int upqm_fifo_int1_err9); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err9_insrt(unsigned int upqm_fifo_int1_err9_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err10(unsigned int upqm_fifo_int1_err10); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err10_insrt(unsigned int upqm_fifo_int1_err10_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err11(unsigned int upqm_fifo_int1_err11); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err11_insrt(unsigned int upqm_fifo_int1_err11_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err12(unsigned int upqm_fifo_int1_err12); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err12_insrt(unsigned int upqm_fifo_int1_err12_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err13(unsigned int upqm_fifo_int1_err13); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err13_insrt(unsigned int upqm_fifo_int1_err13_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err14(unsigned int upqm_fifo_int1_err14); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err14_insrt(unsigned int upqm_fifo_int1_err14_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err15(unsigned int upqm_fifo_int1_err15); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err15_insrt(unsigned int upqm_fifo_int1_err15_insrt); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err0_en(unsigned int upqm_fifo_int1_err0_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err1_en(unsigned int upqm_fifo_int1_err1_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err2_en(unsigned int upqm_fifo_int1_err2_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err3_en(unsigned int upqm_fifo_int1_err3_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err4_en(unsigned int upqm_fifo_int1_err4_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err5_en(unsigned int upqm_fifo_int1_err5_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err6_en(unsigned int upqm_fifo_int1_err6_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err7_en(unsigned int upqm_fifo_int1_err7_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err8_en(unsigned int upqm_fifo_int1_err8_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err9_en(unsigned int upqm_fifo_int1_err9_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err10_en(unsigned int upqm_fifo_int1_err10_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err11_en(unsigned int upqm_fifo_int1_err11_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err12_en(unsigned int upqm_fifo_int1_err12_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err13_en(unsigned int upqm_fifo_int1_err13_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err14_en(unsigned int upqm_fifo_int1_err14_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err15_en(unsigned int upqm_fifo_int1_err15_en); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err0(unsigned int upqm_fifo_int2_err0); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err0_insrt(unsigned int upqm_fifo_int2_err0_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err1(unsigned int upqm_fifo_int2_err1); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err1_insrt(unsigned int upqm_fifo_int2_err1_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err2(unsigned int upqm_fifo_int2_err2); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err2_insrt(unsigned int upqm_fifo_int2_err2_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err3(unsigned int upqm_fifo_int2_err3); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err3_insrt(unsigned int upqm_fifo_int2_err3_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err4(unsigned int upqm_fifo_int2_err4); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err4_insrt(unsigned int upqm_fifo_int2_err4_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err5(unsigned int upqm_fifo_int2_err5); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err5_insrt(unsigned int upqm_fifo_int2_err5_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err6(unsigned int upqm_fifo_int2_err6); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err6_insrt(unsigned int upqm_fifo_int2_err6_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err7(unsigned int upqm_fifo_int2_err7); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err7_insrt(unsigned int upqm_fifo_int2_err7_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err8(unsigned int upqm_fifo_int2_err8); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err8_insrt(unsigned int upqm_fifo_int2_err8_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err9(unsigned int upqm_fifo_int2_err9); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err9_insrt(unsigned int upqm_fifo_int2_err9_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err10(unsigned int upqm_fifo_int2_err10); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err10_insrt(unsigned int upqm_fifo_int2_err10_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err11(unsigned int upqm_fifo_int2_err11); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err11_insrt(unsigned int upqm_fifo_int2_err11_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err12(unsigned int upqm_fifo_int2_err12); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err12_insrt(unsigned int upqm_fifo_int2_err12_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err13(unsigned int upqm_fifo_int2_err13); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err13_insrt(unsigned int upqm_fifo_int2_err13_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err14(unsigned int upqm_fifo_int2_err14); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err14_insrt(unsigned int upqm_fifo_int2_err14_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err15(unsigned int upqm_fifo_int2_err15); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err15_insrt(unsigned int upqm_fifo_int2_err15_insrt); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err0_en(unsigned int upqm_fifo_int2_err0_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err1_en(unsigned int upqm_fifo_int2_err1_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err2_en(unsigned int upqm_fifo_int2_err2_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err3_en(unsigned int upqm_fifo_int2_err3_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err4_en(unsigned int upqm_fifo_int2_err4_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err5_en(unsigned int upqm_fifo_int2_err5_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err6_en(unsigned int upqm_fifo_int2_err6_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err7_en(unsigned int upqm_fifo_int2_err7_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err8_en(unsigned int upqm_fifo_int2_err8_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err9_en(unsigned int upqm_fifo_int2_err9_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err10_en(unsigned int upqm_fifo_int2_err10_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err11_en(unsigned int upqm_fifo_int2_err11_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err12_en(unsigned int upqm_fifo_int2_err12_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err13_en(unsigned int upqm_fifo_int2_err13_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err14_en(unsigned int upqm_fifo_int2_err14_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err15_en(unsigned int upqm_fifo_int2_err15_en); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err0(unsigned int upqm_fifo_int3_err0); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err0_insrt(unsigned int upqm_fifo_int3_err0_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err1(unsigned int upqm_fifo_int3_err1); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err1_insrt(unsigned int upqm_fifo_int3_err1_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err2(unsigned int upqm_fifo_int3_err2); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err2_insrt(unsigned int upqm_fifo_int3_err2_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err3(unsigned int upqm_fifo_int3_err3); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err3_insrt(unsigned int upqm_fifo_int3_err3_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err4(unsigned int upqm_fifo_int3_err4); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err4_insrt(unsigned int upqm_fifo_int3_err4_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err5(unsigned int upqm_fifo_int3_err5); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err5_insrt(unsigned int upqm_fifo_int3_err5_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err6(unsigned int upqm_fifo_int3_err6); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err6_insrt(unsigned int upqm_fifo_int3_err6_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err7(unsigned int upqm_fifo_int3_err7); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err7_insrt(unsigned int upqm_fifo_int3_err7_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err8(unsigned int upqm_fifo_int3_err8); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err8_insrt(unsigned int upqm_fifo_int3_err8_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err9(unsigned int upqm_fifo_int3_err9); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err9_insrt(unsigned int upqm_fifo_int3_err9_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err10(unsigned int upqm_fifo_int3_err10); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err10_insrt(unsigned int upqm_fifo_int3_err10_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err11(unsigned int upqm_fifo_int3_err11); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err11_insrt(unsigned int upqm_fifo_int3_err11_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err12(unsigned int upqm_fifo_int3_err12); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err12_insrt(unsigned int upqm_fifo_int3_err12_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err13(unsigned int upqm_fifo_int3_err13); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err13_insrt(unsigned int upqm_fifo_int3_err13_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err14(unsigned int upqm_fifo_int3_err14); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err14_insrt(unsigned int upqm_fifo_int3_err14_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err15(unsigned int upqm_fifo_int3_err15); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err15_insrt(unsigned int upqm_fifo_int3_err15_insrt); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err0_en(unsigned int upqm_fifo_int3_err0_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err1_en(unsigned int upqm_fifo_int3_err1_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err2_en(unsigned int upqm_fifo_int3_err2_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err3_en(unsigned int upqm_fifo_int3_err3_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err4_en(unsigned int upqm_fifo_int3_err4_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err5_en(unsigned int upqm_fifo_int3_err5_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err6_en(unsigned int upqm_fifo_int3_err6_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err7_en(unsigned int upqm_fifo_int3_err7_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err8_en(unsigned int upqm_fifo_int3_err8_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err9_en(unsigned int upqm_fifo_int3_err9_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err10_en(unsigned int upqm_fifo_int3_err10_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err11_en(unsigned int upqm_fifo_int3_err11_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err12_en(unsigned int upqm_fifo_int3_err12_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err13_en(unsigned int upqm_fifo_int3_err13_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err14_en(unsigned int upqm_fifo_int3_err14_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err15_en(unsigned int upqm_fifo_int3_err15_en); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err0(unsigned int upqm_fifo_int4_err0); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err0_insrt(unsigned int upqm_fifo_int4_err0_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err1(unsigned int upqm_fifo_int4_err1); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err1_insrt(unsigned int upqm_fifo_int4_err1_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err2(unsigned int upqm_fifo_int4_err2); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err2_insrt(unsigned int upqm_fifo_int4_err2_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err3(unsigned int upqm_fifo_int4_err3); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err3_insrt(unsigned int upqm_fifo_int4_err3_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err4(unsigned int upqm_fifo_int4_err4); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err4_insrt(unsigned int upqm_fifo_int4_err4_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err5(unsigned int upqm_fifo_int4_err5); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err5_insrt(unsigned int upqm_fifo_int4_err5_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err6(unsigned int upqm_fifo_int4_err6); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err6_insrt(unsigned int upqm_fifo_int4_err6_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err7(unsigned int upqm_fifo_int4_err7); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err7_insrt(unsigned int upqm_fifo_int4_err7_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err8(unsigned int upqm_fifo_int4_err8); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err8_insrt(unsigned int upqm_fifo_int4_err8_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err9(unsigned int upqm_fifo_int4_err9); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err9_insrt(unsigned int upqm_fifo_int4_err9_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err10(unsigned int upqm_fifo_int4_err10); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err10_insrt(unsigned int upqm_fifo_int4_err10_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err11(unsigned int upqm_fifo_int4_err11); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err11_insrt(unsigned int upqm_fifo_int4_err11_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err12(unsigned int upqm_fifo_int4_err12); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err12_insrt(unsigned int upqm_fifo_int4_err12_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err13(unsigned int upqm_fifo_int4_err13); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err13_insrt(unsigned int upqm_fifo_int4_err13_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err14(unsigned int upqm_fifo_int4_err14); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err14_insrt(unsigned int upqm_fifo_int4_err14_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err15(unsigned int upqm_fifo_int4_err15); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err15_insrt(unsigned int upqm_fifo_int4_err15_insrt); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err0_en(unsigned int upqm_fifo_int4_err0_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err1_en(unsigned int upqm_fifo_int4_err1_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err2_en(unsigned int upqm_fifo_int4_err2_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err3_en(unsigned int upqm_fifo_int4_err3_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err4_en(unsigned int upqm_fifo_int4_err4_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err5_en(unsigned int upqm_fifo_int4_err5_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err6_en(unsigned int upqm_fifo_int4_err6_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err7_en(unsigned int upqm_fifo_int4_err7_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err8_en(unsigned int upqm_fifo_int4_err8_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err9_en(unsigned int upqm_fifo_int4_err9_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err10_en(unsigned int upqm_fifo_int4_err10_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err11_en(unsigned int upqm_fifo_int4_err11_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err12_en(unsigned int upqm_fifo_int4_err12_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err13_en(unsigned int upqm_fifo_int4_err13_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err14_en(unsigned int upqm_fifo_int4_err14_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err15_en(unsigned int upqm_fifo_int4_err15_en); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err0(unsigned int upqm_fifo_int5_err0); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err0_insrt(unsigned int upqm_fifo_int5_err0_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err1(unsigned int upqm_fifo_int5_err1); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err1_insrt(unsigned int upqm_fifo_int5_err1_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err2(unsigned int upqm_fifo_int5_err2); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err2_insrt(unsigned int upqm_fifo_int5_err2_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err3(unsigned int upqm_fifo_int5_err3); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err3_insrt(unsigned int upqm_fifo_int5_err3_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err4(unsigned int upqm_fifo_int5_err4); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err4_insrt(unsigned int upqm_fifo_int5_err4_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err5(unsigned int upqm_fifo_int5_err5); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err5_insrt(unsigned int upqm_fifo_int5_err5_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err6(unsigned int upqm_fifo_int5_err6); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err6_insrt(unsigned int upqm_fifo_int5_err6_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err7(unsigned int upqm_fifo_int5_err7); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err7_insrt(unsigned int upqm_fifo_int5_err7_insrt); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err0_en(unsigned int upqm_fifo_int5_err0_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err1_en(unsigned int upqm_fifo_int5_err1_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err2_en(unsigned int upqm_fifo_int5_err2_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err3_en(unsigned int upqm_fifo_int5_err3_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err4_en(unsigned int upqm_fifo_int5_err4_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err5_en(unsigned int upqm_fifo_int5_err5_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err6_en(unsigned int upqm_fifo_int5_err6_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err7_en(unsigned int upqm_fifo_int5_err7_en); +int iSetPQM_RX_RING_E0_ERR_INT_pqm_ring_e0_err(unsigned int upqm_ring_e0_err); +int iSetPQM_RX_RING_E0_ERR_INT_pqm_ring_e0_err_insert(unsigned int upqm_ring_e0_err_insert); +int iSetPQM_RX_RING_E0_ERR_INT_pqm_ring_e0_err_info(unsigned int upqm_ring_e0_err_info); +int iSetPQM_RX_RING_E1_ERR_INT_pqm_ring_e1_err(unsigned int upqm_ring_e1_err); +int iSetPQM_RX_RING_E1_ERR_INT_pqm_ring_e1_err_insert(unsigned int upqm_ring_e1_err_insert); +int iSetPQM_RX_RING_E1_ERR_INT_pqm_ring_e1_err_info(unsigned int upqm_ring_e1_err_info); +int iSetPQM_FIFO_ST0_pqm_fifo0_st0(unsigned int upqm_fifo0_st0); +int iSetPQM_FIFO_ST0_pqm_fifo1_st0(unsigned int upqm_fifo1_st0); +int iSetPQM_FIFO_ST0_pqm_fifo2_st0(unsigned int upqm_fifo2_st0); +int iSetPQM_FIFO_ST0_pqm_fifo3_st0(unsigned int upqm_fifo3_st0); +int iSetPQM_FIFO_ST0_pqm_fifo4_st0(unsigned int upqm_fifo4_st0); +int iSetPQM_FIFO_ST0_pqm_fifo5_st0(unsigned int upqm_fifo5_st0); +int iSetPQM_FIFO_ST0_pqm_fifo6_st0(unsigned int upqm_fifo6_st0); +int iSetPQM_FIFO_ST0_pqm_fifo7_st0(unsigned int upqm_fifo7_st0); +int iSetPQM_FIFO_ST0_pqm_fifo8_st0(unsigned int upqm_fifo8_st0); +int iSetPQM_FIFO_ST0_pqm_fifo9_st0(unsigned int upqm_fifo9_st0); +int iSetPQM_FIFO_ST0_pqm_fifo10_st0(unsigned int upqm_fifo10_st0); +int iSetPQM_FIFO_ST0_pqm_fifo11_st0(unsigned int upqm_fifo11_st0); +int iSetPQM_FIFO_ST0_pqm_fifo12_st0(unsigned int upqm_fifo12_st0); +int iSetPQM_FIFO_ST1_pqm_fifo0_st1(unsigned int upqm_fifo0_st1); +int iSetPQM_FIFO_ST1_pqm_fifo1_st1(unsigned int upqm_fifo1_st1); +int iSetPQM_FIFO_ST1_pqm_fifo2_st1(unsigned int upqm_fifo2_st1); +int iSetPQM_FIFO_ST1_pqm_fifo3_st1(unsigned int upqm_fifo3_st1); +int iSetPQM_FIFO_ST1_pqm_fifo4_st1(unsigned int upqm_fifo4_st1); +int iSetPQM_FIFO_ST1_pqm_fifo5_st1(unsigned int upqm_fifo5_st1); +int iSetPQM_FIFO_ST1_pqm_fifo6_st1(unsigned int upqm_fifo6_st1); +int iSetPQM_FIFO_ST1_pqm_fifo7_st1(unsigned int upqm_fifo7_st1); +int iSetPQM_FIFO_ST1_pqm_fifo8_st1(unsigned int upqm_fifo8_st1); +int iSetPQM_FIFO_ST1_pqm_fifo9_st1(unsigned int upqm_fifo9_st1); +int iSetPQM_FIFO_ST1_pqm_fifo10_st1(unsigned int upqm_fifo10_st1); +int iSetPQM_FIFO_ST1_pqm_fifo11_st1(unsigned int upqm_fifo11_st1); +int iSetPQM_FIFO_ST1_pqm_fifo12_st1(unsigned int upqm_fifo12_st1); +int iSetPQM_FIFO_ST1_pqm_fifo13_st1(unsigned int upqm_fifo13_st1); +int iSetPQM_FIFO_ST1_pqm_fifo14_st1(unsigned int upqm_fifo14_st1); +int iSetPQM_FIFO_ST1_pqm_fifo15_st1(unsigned int upqm_fifo15_st1); +int iSetPQM_FIFO_ST2_pqm_fifo0_st2(unsigned int upqm_fifo0_st2); +int iSetPQM_FIFO_ST2_pqm_fifo1_st2(unsigned int upqm_fifo1_st2); +int iSetPQM_FIFO_ST2_pqm_fifo2_st2(unsigned int upqm_fifo2_st2); +int iSetPQM_FIFO_ST2_pqm_fifo3_st2(unsigned int upqm_fifo3_st2); +int iSetPQM_FIFO_ST2_pqm_fifo4_st2(unsigned int upqm_fifo4_st2); +int iSetPQM_FIFO_ST2_pqm_fifo5_st2(unsigned int upqm_fifo5_st2); +int iSetPQM_FIFO_ST2_pqm_fifo6_st2(unsigned int upqm_fifo6_st2); +int iSetPQM_FIFO_ST2_pqm_fifo7_st2(unsigned int upqm_fifo7_st2); +int iSetPQM_FIFO_ST2_pqm_fifo8_st2(unsigned int upqm_fifo8_st2); +int iSetPQM_FIFO_ST2_pqm_fifo9_st2(unsigned int upqm_fifo9_st2); +int iSetPQM_FIFO_ST2_pqm_fifo10_st2(unsigned int upqm_fifo10_st2); +int iSetPQM_FIFO_ST2_pqm_fifo11_st2(unsigned int upqm_fifo11_st2); +int iSetPQM_RW_RSV0_pqm_rw_rsv0(unsigned int upqm_rw_rsv0); +int iSetPQM_RW_RSV1_pqm_rw_rsv1(unsigned int upqm_rw_rsv1); +int iSetPQM_RW_RSV2_pqm_rw_rsv2(unsigned int upqm_rw_rsv2); +int iSetPQM_RW_RSV3_pqm_rw_rsv3(unsigned int upqm_rw_rsv3); +int iSetPQM_INDRECT_CTRL_pqm_indrect_addr(unsigned int upqm_indrect_addr); +int iSetPQM_INDRECT_CTRL_pqm_indrect_tab(unsigned int upqm_indrect_tab); +int iSetPQM_INDRECT_CTRL_pqm_indrect_stat(unsigned int upqm_indrect_stat); +int iSetPQM_INDRECT_CTRL_pqm_indrect_mode(unsigned int upqm_indrect_mode); +int iSetPQM_INDRECT_CTRL_pqm_indrect_vld(unsigned int upqm_indrect_vld); +int iSetPQM_INDRECT_TIMEOUT_pqm_indrect_timeout(unsigned int upqm_indrect_timeout); +int iSetPQM_INDRECT_DATA_0_pqm_indrect_data_0(unsigned int upqm_indrect_data_0); +int iSetPQM_INDRECT_DATA_1_pqm_indrect_data_1(unsigned int upqm_indrect_data_1); +int iSetPQM_PASS_THROUGH_CFG_pqm_passthru_enable(unsigned int upqm_passthru_enable); +int iSetPQM_PASS_THROUGH_CFG_pqm_passthru_wgt_cfg(unsigned int upqm_passthru_wgt_cfg); +int iSetPQM_WEIGHT_OFFSET_pqm_cos_weight_offset(unsigned int upqm_cos_weight_offset); +int iSetPQM_WEIGHT_OFFSET_pqm_ep_weight_offset(unsigned int upqm_ep_weight_offset); +int iSetPQM_WEIGHT_OFFSET_pqm_host_weight_offset(unsigned int upqm_host_weight_offset); +int iSetPQM_PPS_SHAPER_CFG_PKTLEN_pqm_pps_typical_pktlen_cfg(unsigned int upqm_pps_typical_pktlen_cfg); +int iSetPQM_ROOT_SCH_WEIGHT_CFG_pqm_root_sch_wgt_cfg(unsigned int upqm_root_sch_wgt_cfg); +int iSetHOST_WEIGHT_host_weight_cfg(unsigned int uhost_weight_cfg); +int iSetHOST_SHAP_BPS_CFG_host_shap_bps_cfg(unsigned int uhost_shap_bps_cfg); +int iSetHOST_SHAP_PPS_CFG_host_shap_pps_cfg(unsigned int uhost_shap_pps_cfg); +int iSetEP_WEIGHT_ep_weight_cfg(unsigned int uep_weight_cfg); +int iSetEP_SHAP_BPS_CFG_ep_shap_bps_cfg(unsigned int uep_shap_bps_cfg); +int iSetEP_SHAP_PPS_CFG_ep_shap_pps_cfg(unsigned int uep_shap_pps_cfg); +int iSetPQM_SHAP_BYPASS_CFG_pqm_nmq_shap_byp_vld(unsigned int upqm_nmq_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_vnic_shap_byp_vld(unsigned int upqm_vnic_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_vnicgrp_shap_byp_vld(unsigned int upqm_vnicgrp_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_ep_shap_byp_vld(unsigned int upqm_ep_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_host_shap_byp_vld(unsigned int upqm_host_shap_byp_vld); +int iSetPQM_HOST_EP_XON_CFG_pqm_hostep_xon_cfg(unsigned int upqm_hostep_xon_cfg); +int iSetPQM_HOST_XON_CFG_msc_host_xon_cfg(unsigned int umsc_host_xon_cfg); +int iSetPQM_HOST_XON_CFG_msc_root_xon_cfg(unsigned int umsc_root_xon_cfg); +int iSetPQM_HOST_EP_BPS_SPF_ST_pqm_hostep_bps_spf_st(unsigned int upqm_hostep_bps_spf_st); +int iSetPQM_HOST_EP_PPS_SPF_ST_pqm_hostep_pps_spf_st(unsigned int upqm_hostep_pps_spf_st); +int iSetPQM_HOST_SPF_ST_msc_host_bps_spf_st(unsigned int umsc_host_bps_spf_st); +int iSetPQM_HOST_SPF_ST_msc_host_pps_spf_st(unsigned int umsc_host_pps_spf_st); +int iSetPQM_SCH_BP_STA_pqm_host_bp(unsigned int upqm_host_bp); +int iSetPQM_SCH_BP_STA_pqm_scan_bp(unsigned int upqm_scan_bp); +int iSetPQM_SCH_EP_BP_STA_pqm_ep_bp(unsigned int upqm_ep_bp); +int iSetPQM_FIFO_TH_CFG_pqm_du_fifo_gap(unsigned int upqm_du_fifo_gap); +int iSetPQM_FIFO_TH_CFG_pqm_pt_fifo_gap(unsigned int upqm_pt_fifo_gap); +int iSetPQM_DPL_INFO_PTR0_pqm_dpl_plen(unsigned int upqm_dpl_plen); +int iSetPQM_DPL_INFO_PTR0_pqm_dpl_pnum(unsigned int upqm_dpl_pnum); +int iSetPQM_DPL_INFO_PTR1_pqm_dpl_pqid(unsigned int upqm_dpl_pqid); +int iSetPQM_MCD_DU_INFO_PTR0_pqm_mcd_plen(unsigned int upqm_mcd_plen); +int iSetPQM_MCD_DU_INFO_PTR0_pqm_mcd_pnum(unsigned int upqm_mcd_pnum); +int iSetPQM_MCD_DU_INFO_PTR1_pqm_mcd_pqid(unsigned int upqm_mcd_pqid); +int iSetPQM_MCD_DU_INFO_PTR1_pqm_mcd_color(unsigned int upqm_mcd_color); +int iSetPQM_UNCRT_ERR_MASK_ram_uncrt_err_mask(unsigned int uram_uncrt_err_mask); +int iSetPQM_UNCRT_ERR_MASK_other_uncrt_err_mask(unsigned int uother_uncrt_err_mask); +int iSetPQM_UNCRT_ERR_CLR_ram_uncrt_err_clr(unsigned int uram_uncrt_err_clr); +int iSetPQM_UNCRT_ERR_CLR_other_uncrt_err_clr(unsigned int uother_uncrt_err_clr); +int iSetPQ_EQS_CNT_pqm_eqs_cnt(unsigned int upqm_eqs_cnt); +int iSetPQ_DQS_CNT_pqm_dqs_cnt(unsigned int upqm_dqs_cnt); +int iSetPQ_EMPT_DQS_CNT_pqm_empt_dqs_cnt(unsigned int upqm_empt_dqs_cnt); +int iSetPQ_SCH_DQR_CNT_pqm_sch_dqr_cnt(unsigned int upqm_sch_dqr_cnt); +int iSetPQ_SCH_EMPT_DQR_CNT_pqm_sch_empt_dqr_cnt(unsigned int upqm_sch_empt_dqr_cnt); +int iSetPQ_PT_DQR_CNT_pqm_pt_dqr_cnt(unsigned int upqm_pt_dqr_cnt); +int iSetPQ_DPL_CNT_pqm_dpl_cnt(unsigned int upqm_dpl_cnt); +int iSetPQ_DU_VLD_CNT_pqm_du_info_vld_cnt(unsigned int upqm_du_info_vld_cnt); +int iSetPQ_DU_ERR_CNT_pqm_du_info_err_cnt(unsigned int upqm_du_info_err_cnt); +int iSetPQM_ECC_1BIT_ERR_CNT_pqm_ecc_1bit_err_cnt(unsigned int upqm_ecc_1bit_err_cnt); +int iSetPQM_ECC_2BIT_ERR_CNT_pqm_ecc_2bit_err_cnt(unsigned int upqm_ecc_2bit_err_cnt); +int iSetSCH_PQ_DFX_CFG_sch_pq_dfx_cfg(unsigned int usch_pq_dfx_cfg); +int iSetSCH_PQ_DFX_CFG_sch_pq_dfx_cfg_vld(unsigned int usch_pq_dfx_cfg_vld); +int iSetSCH_PQ_DFX_UP_CNT_sch_pq_dfx_up_cnt(unsigned int usch_pq_dfx_up_cnt); +int iSetSCH_PQ_DFX_EMPT_UP_CNT_sch_pq_dfx_empt_up_cnt(unsigned int usch_pq_dfx_empt_up_cnt); +int iSetSCH_PQ_DFX_SCH_CNT_sch_pq_dfx_sch_cnt(unsigned int usch_pq_dfx_sch_cnt); +int iSetSCH_PQ_DFX_PT_DEQ_CNT_sch_pq_dfx_pt_dqr_cnt(unsigned int usch_pq_dfx_pt_dqr_cnt); +int iSetSCH_PQ_DFX_EMPT_SCH_CNT_sch_pq_dfx_empt_sch_cnt(unsigned int usch_pq_dfx_empt_sch_cnt); +int iSetSCH_PQ_DFX_DU_CNT_sch_pq_dfx_du_cnt(unsigned int usch_pq_dfx_du_cnt); + + +#endif // PQM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_reg_offset.h new file mode 100644 index 000000000..00682ed5b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_reg_offset.h @@ -0,0 +1,291 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : pqm_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:57:27 Create file +// ****************************************************************************** + +#ifndef PQM_REG_OFFSET_H +#define PQM_REG_OFFSET_H + +/* PQM_TOP Base address of Module's Register */ +#define CSR_PQM_TOP_BASE (0xC000) + +/* **************************************************************************** */ +/* PQM_TOP Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PQM_TOP_PQM_EDITION_REG (CSR_PQM_TOP_BASE + 0x0) /* Version Register */ +#define CSR_PQM_TOP_PQM_INITCTAB_START_REG (CSR_PQM_TOP_BASE + 0x4) /* 配置表初始化使能寄存器 */ +#define CSR_PQM_TOP_PQM_INITCTAB_DONE_REG (CSR_PQM_TOP_BASE + 0x8) /* 配置表初始化状态寄存器 */ +#define CSR_PQM_TOP_PQM_CFG_OK_REG (CSR_PQM_TOP_BASE + 0xC) /* PQM 配置完成寄存器 */ +#define CSR_PQM_TOP_PQM_INITLOGIC_DONE_REG (CSR_PQM_TOP_BASE + 0x10) /* 芯片逻辑初始化状态寄存器 */ +#define CSR_PQM_TOP_MEM_ECC_BYPASS_EN_REG (CSR_PQM_TOP_BASE + 0x14) /* RAM ECC BYPASS控制寄存器 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG0_REG (CSR_PQM_TOP_BASE + 0x18) /* RAM CTRL_BUS寄存器0 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG1_REG (CSR_PQM_TOP_BASE + 0x1C) /* RAM CTRL_BUS寄存器1 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG2_REG (CSR_PQM_TOP_BASE + 0x20) /* RAM CTRL_BUS寄存器2 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG3_REG (CSR_PQM_TOP_BASE + 0x24) /* RAM CTRL_BUS寄存器3 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG4_REG (CSR_PQM_TOP_BASE + 0x28) /* RAM CTRL_BUS寄存器4 */ +#define CSR_PQM_TOP_PQM_INT_VECTOR_REG (CSR_PQM_TOP_BASE + 0x100) /* PQM Interrupt Vector Register */ +#define CSR_PQM_TOP_PQM_INT_REG (CSR_PQM_TOP_BASE + 0x104) /* PQM Interrupt Register */ +#define CSR_PQM_TOP_PQM_INT_EN_REG (CSR_PQM_TOP_BASE + 0x108) /* PQM Interrupt Mask Register */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ0_REG (CSR_PQM_TOP_BASE + 0x10C) /* PQM mem Error Request register0. */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ1_REG (CSR_PQM_TOP_BASE + 0x110) /* PQM mem Error Request register1. */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ2_REG (CSR_PQM_TOP_BASE + 0x114) /* PQM mem Error Request register2. */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ3_REG (CSR_PQM_TOP_BASE + 0x118) /* PQM mem Error Request register3. */ +#define CSR_PQM_TOP_PQM_ECC_ONE_BIT_INT_REG (CSR_PQM_TOP_BASE + 0x11C) /* RAM ECC ONE BIT ERROR */ +#define CSR_PQM_TOP_PQM_ECC_TWO_BIT_INT_REG (CSR_PQM_TOP_BASE + 0x120) /* RAM ECC TWO BITS ERROR */ +#define CSR_PQM_TOP_PQM_MQ_BIND_INT_REG (CSR_PQM_TOP_BASE + 0x130) /* MQ MAPPING CONFIG ERROR */ +#define CSR_PQM_TOP_PQM_MQ_BIND_MCD_INT_REG (CSR_PQM_TOP_BASE + 0x134) /* MQ MAPPING CONFIG FOR MCD ERROR */ +#define CSR_PQM_TOP_PQM_FIFO_INT0_REG (CSR_PQM_TOP_BASE + 0x138) /* FIFO 0 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT0_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x13C) /* FIFO 0 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT1_REG (CSR_PQM_TOP_BASE + 0x140) /* FIFO 1 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT1_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x144) /* FIFO 1 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT2_REG (CSR_PQM_TOP_BASE + 0x148) /* FIFO 2 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT2_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x14C) /* FIFO 2 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT3_REG (CSR_PQM_TOP_BASE + 0x150) /* FIFO 3 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT3_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x154) /* FIFO 3 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT4_REG (CSR_PQM_TOP_BASE + 0x158) /* FIFO 4 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT4_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x15C) /* FIFO 4 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT5_REG (CSR_PQM_TOP_BASE + 0x160) /* FIFO 5 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT5_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x164) /* FIFO 5 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_RX_RING_E0_ERR_INT_REG (CSR_PQM_TOP_BASE + 0x168) /* Receive Ring E0 error int */ +#define CSR_PQM_TOP_PQM_RX_RING_E1_ERR_INT_REG (CSR_PQM_TOP_BASE + 0x16C) /* Receive Ring E0 error int */ +#define CSR_PQM_TOP_PQM_FIFO_ST0_REG (CSR_PQM_TOP_BASE + 0x180) /* fifo full and empt state0 */ +#define CSR_PQM_TOP_PQM_FIFO_ST1_REG (CSR_PQM_TOP_BASE + 0x184) /* fifo full and empt state1 */ +#define CSR_PQM_TOP_PQM_FIFO_ST2_REG (CSR_PQM_TOP_BASE + 0x188) /* fifo full and empt state2 */ +#define CSR_PQM_TOP_PQM_RW_RSV0_REG (CSR_PQM_TOP_BASE + 0x300) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_RW_RSV1_REG (CSR_PQM_TOP_BASE + 0x304) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_RW_RSV2_REG (CSR_PQM_TOP_BASE + 0x308) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_RW_RSV3_REG (CSR_PQM_TOP_BASE + 0x30C) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_INDRECT_CTRL_REG (CSR_PQM_TOP_BASE + 0x310) /* Indirect access ctrl Register。 */ +#define CSR_PQM_TOP_PQM_INDRECT_TIMEOUT_REG (CSR_PQM_TOP_BASE + 0x314) /* Indirect Access Timeout Register。 */ +#define CSR_PQM_TOP_PQM_INDRECT_DATA_0_REG (CSR_PQM_TOP_BASE + 0x318) /* Indirect Access Data Register BIT63_32 */ +#define CSR_PQM_TOP_PQM_INDRECT_DATA_1_REG (CSR_PQM_TOP_BASE + 0x31C) /* Indirect Access Data Register BIT31_0 */ +#define CSR_PQM_TOP_PQM_PASS_THROUGH_CFG_REG (CSR_PQM_TOP_BASE + 0x320) /* Pass through function enable register. */ +#define CSR_PQM_TOP_PQM_WEIGHT_OFFSET_REG (CSR_PQM_TOP_BASE + 0x324) /* Normal queue weight offset */ +#define CSR_PQM_TOP_PQM_PPS_SHAPER_CFG_PKTLEN_REG (CSR_PQM_TOP_BASE + 0x328) /* PQM Shaper Config Pktlen */ +#define CSR_PQM_TOP_PQM_ROOT_SCH_WEIGHT_CFG_REG (CSR_PQM_TOP_BASE + 0x32C) /* PQM ROOT SCH WEIGHT Config */ +#define CSR_PQM_TOP_HOST_WEIGHT_0_REG (CSR_PQM_TOP_BASE + 0x340) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_WEIGHT_1_REG (CSR_PQM_TOP_BASE + 0x344) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_WEIGHT_2_REG (CSR_PQM_TOP_BASE + 0x348) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_WEIGHT_3_REG (CSR_PQM_TOP_BASE + 0x34C) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x350) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x354) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x358) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x35C) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x360) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x364) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x368) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x36C) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_EP_WEIGHT_0_REG (CSR_PQM_TOP_BASE + 0x370) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_1_REG (CSR_PQM_TOP_BASE + 0x374) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_2_REG (CSR_PQM_TOP_BASE + 0x378) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_3_REG (CSR_PQM_TOP_BASE + 0x37C) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_4_REG (CSR_PQM_TOP_BASE + 0x380) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_5_REG (CSR_PQM_TOP_BASE + 0x384) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_6_REG (CSR_PQM_TOP_BASE + 0x388) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_7_REG (CSR_PQM_TOP_BASE + 0x38C) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_8_REG (CSR_PQM_TOP_BASE + 0x390) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_9_REG (CSR_PQM_TOP_BASE + 0x394) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_10_REG (CSR_PQM_TOP_BASE + 0x398) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_11_REG (CSR_PQM_TOP_BASE + 0x39C) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_12_REG (CSR_PQM_TOP_BASE + 0x3A0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_13_REG (CSR_PQM_TOP_BASE + 0x3A4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_14_REG (CSR_PQM_TOP_BASE + 0x3A8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_15_REG (CSR_PQM_TOP_BASE + 0x3AC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_16_REG (CSR_PQM_TOP_BASE + 0x3B0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_17_REG (CSR_PQM_TOP_BASE + 0x3B4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_18_REG (CSR_PQM_TOP_BASE + 0x3B8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_19_REG (CSR_PQM_TOP_BASE + 0x3BC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_20_REG (CSR_PQM_TOP_BASE + 0x3C0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_21_REG (CSR_PQM_TOP_BASE + 0x3C4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_22_REG (CSR_PQM_TOP_BASE + 0x3C8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_23_REG (CSR_PQM_TOP_BASE + 0x3CC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_24_REG (CSR_PQM_TOP_BASE + 0x3D0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_25_REG (CSR_PQM_TOP_BASE + 0x3D4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_26_REG (CSR_PQM_TOP_BASE + 0x3D8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_27_REG (CSR_PQM_TOP_BASE + 0x3DC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_28_REG (CSR_PQM_TOP_BASE + 0x3E0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_29_REG (CSR_PQM_TOP_BASE + 0x3E4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_30_REG (CSR_PQM_TOP_BASE + 0x3E8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_31_REG (CSR_PQM_TOP_BASE + 0x3EC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x3F0) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x3F4) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x3F8) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x3FC) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_4_REG (CSR_PQM_TOP_BASE + 0x400) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_5_REG (CSR_PQM_TOP_BASE + 0x404) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_6_REG (CSR_PQM_TOP_BASE + 0x408) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_7_REG (CSR_PQM_TOP_BASE + 0x40C) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_8_REG (CSR_PQM_TOP_BASE + 0x410) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_9_REG (CSR_PQM_TOP_BASE + 0x414) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_10_REG \ + (CSR_PQM_TOP_BASE + 0x418) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_11_REG \ + (CSR_PQM_TOP_BASE + 0x41C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_12_REG \ + (CSR_PQM_TOP_BASE + 0x420) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_13_REG \ + (CSR_PQM_TOP_BASE + 0x424) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_14_REG \ + (CSR_PQM_TOP_BASE + 0x428) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_15_REG \ + (CSR_PQM_TOP_BASE + 0x42C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_16_REG \ + (CSR_PQM_TOP_BASE + 0x430) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_17_REG \ + (CSR_PQM_TOP_BASE + 0x434) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_18_REG \ + (CSR_PQM_TOP_BASE + 0x438) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_19_REG \ + (CSR_PQM_TOP_BASE + 0x43C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_20_REG \ + (CSR_PQM_TOP_BASE + 0x440) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_21_REG \ + (CSR_PQM_TOP_BASE + 0x444) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_22_REG \ + (CSR_PQM_TOP_BASE + 0x448) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_23_REG \ + (CSR_PQM_TOP_BASE + 0x44C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_24_REG \ + (CSR_PQM_TOP_BASE + 0x450) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_25_REG \ + (CSR_PQM_TOP_BASE + 0x454) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_26_REG \ + (CSR_PQM_TOP_BASE + 0x458) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_27_REG \ + (CSR_PQM_TOP_BASE + 0x45C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_28_REG \ + (CSR_PQM_TOP_BASE + 0x460) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_29_REG \ + (CSR_PQM_TOP_BASE + 0x464) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_30_REG \ + (CSR_PQM_TOP_BASE + 0x468) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_31_REG \ + (CSR_PQM_TOP_BASE + 0x46C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x470) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x474) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x478) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x47C) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_4_REG (CSR_PQM_TOP_BASE + 0x480) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_5_REG (CSR_PQM_TOP_BASE + 0x484) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_6_REG (CSR_PQM_TOP_BASE + 0x488) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_7_REG (CSR_PQM_TOP_BASE + 0x48C) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_8_REG (CSR_PQM_TOP_BASE + 0x490) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_9_REG (CSR_PQM_TOP_BASE + 0x494) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_10_REG \ + (CSR_PQM_TOP_BASE + 0x498) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_11_REG \ + (CSR_PQM_TOP_BASE + 0x49C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_12_REG \ + (CSR_PQM_TOP_BASE + 0x4A0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_13_REG \ + (CSR_PQM_TOP_BASE + 0x4A4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_14_REG \ + (CSR_PQM_TOP_BASE + 0x4A8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_15_REG \ + (CSR_PQM_TOP_BASE + 0x4AC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_16_REG \ + (CSR_PQM_TOP_BASE + 0x4B0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_17_REG \ + (CSR_PQM_TOP_BASE + 0x4B4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_18_REG \ + (CSR_PQM_TOP_BASE + 0x4B8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_19_REG \ + (CSR_PQM_TOP_BASE + 0x4BC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_20_REG \ + (CSR_PQM_TOP_BASE + 0x4C0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_21_REG \ + (CSR_PQM_TOP_BASE + 0x4C4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_22_REG \ + (CSR_PQM_TOP_BASE + 0x4C8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_23_REG \ + (CSR_PQM_TOP_BASE + 0x4CC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_24_REG \ + (CSR_PQM_TOP_BASE + 0x4D0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_25_REG \ + (CSR_PQM_TOP_BASE + 0x4D4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_26_REG \ + (CSR_PQM_TOP_BASE + 0x4D8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_27_REG \ + (CSR_PQM_TOP_BASE + 0x4DC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_28_REG \ + (CSR_PQM_TOP_BASE + 0x4E0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_29_REG \ + (CSR_PQM_TOP_BASE + 0x4E4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_30_REG \ + (CSR_PQM_TOP_BASE + 0x4E8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_31_REG \ + (CSR_PQM_TOP_BASE + 0x4EC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_PQM_SHAP_BYPASS_CFG_REG (CSR_PQM_TOP_BASE + 0x4F0) /* PQM Shaper Bypass Configuration */ +#define CSR_PQM_TOP_PQM_HOST_EP_XON_CFG_REG (CSR_PQM_TOP_BASE + 0x1000) /* The XON Configuration of the HOST EP node \ + */ +#define CSR_PQM_TOP_PQM_HOST_XON_CFG_REG (CSR_PQM_TOP_BASE + 0x1004) /* The XON Configuration of the HOST node */ +#define CSR_PQM_TOP_PQM_HOST_EP_BPS_SPF_ST_REG \ + (CSR_PQM_TOP_BASE + 0x1008) /* The BPS Shap Pass Flag State of the HOST EP node */ +#define CSR_PQM_TOP_PQM_HOST_EP_PPS_SPF_ST_REG \ + (CSR_PQM_TOP_BASE + 0x100C) /* The PPS Shap Pass Flag State of the HOST EP node */ +#define CSR_PQM_TOP_PQM_HOST_SPF_ST_REG (CSR_PQM_TOP_BASE + 0x1010) /* The Shap Pass Flag State of the HOST node */ +#define CSR_PQM_TOP_PQM_SCH_BP_STA_REG (CSR_PQM_TOP_BASE + 0x1014) /* PQM ROOT Level backpress status Register */ +#define CSR_PQM_TOP_PQM_SCH_EP_BP_STA_REG (CSR_PQM_TOP_BASE + 0x1018) /* PQM HSOT_EP Level backpress status Register \ + */ +#define CSR_PQM_TOP_PQM_FIFO_TH_CFG_REG (CSR_PQM_TOP_BASE + 0x101C) /* The Threshold Config Of PQM FIFO */ +#define CSR_PQM_TOP_PQM_DPL_INFO_PTR0_REG (CSR_PQM_TOP_BASE + 0x1020) /* PQM DPL INFO 0 status Register */ +#define CSR_PQM_TOP_PQM_DPL_INFO_PTR1_REG (CSR_PQM_TOP_BASE + 0x1024) /* PQM DPL INFO 1 status Register */ +#define CSR_PQM_TOP_PQM_MCD_DU_INFO_PTR0_REG (CSR_PQM_TOP_BASE + 0x1028) /* PQM MCD DU INFO 0 status Register */ +#define CSR_PQM_TOP_PQM_MCD_DU_INFO_PTR1_REG (CSR_PQM_TOP_BASE + 0x102C) /* PQM MCD DU INFO 1 status Register */ +#define CSR_PQM_TOP_PQM_UNCRT_ERR_MASK_REG (CSR_PQM_TOP_BASE + 0x1400) /* PQM Urgency Interrupt Mask Register。 */ +#define CSR_PQM_TOP_PQM_UNCRT_ERR_CLR_REG (CSR_PQM_TOP_BASE + 0x1404) /* PQM Urgency Interrupt Clear Register。 */ +#define CSR_PQM_TOP_PQ_EQS_CNT_REG (CSR_PQM_TOP_BASE + 0x1408) /* PQM MQ ENQ EQS count */ +#define CSR_PQM_TOP_PQ_DQS_CNT_REG (CSR_PQM_TOP_BASE + 0x140C) /* PQM MQ DQS count */ +#define CSR_PQM_TOP_PQ_EMPT_DQS_CNT_REG (CSR_PQM_TOP_BASE + 0x1410) /* PQM MQ EMPT DQS count */ +#define CSR_PQM_TOP_PQ_SCH_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x1414) /* PQM MQ SCH DQR count */ +#define CSR_PQM_TOP_PQ_SCH_EMPT_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x1418) /* PQM MQ SCH EMPT DQR count */ +#define CSR_PQM_TOP_PQ_PT_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x141C) /* PQM MQ PT DQR count */ +#define CSR_PQM_TOP_PQ_DPL_CNT_REG (CSR_PQM_TOP_BASE + 0x1420) /* PQM MQ DPL count */ +#define CSR_PQM_TOP_PQ_DU_VLD_CNT_REG (CSR_PQM_TOP_BASE + 0x1424) /* PQM DU VLD count */ +#define CSR_PQM_TOP_PQ_DU_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x1428) /* PQM DU ERR count */ +#define CSR_PQM_TOP_PQM_ECC_1BIT_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x142C) /* PQM MEMORY ECC 1BIT ERR count */ +#define CSR_PQM_TOP_PQM_ECC_2BIT_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x1430) /* PQM MEMORY ECC 2BIT ERR count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_CFG_REG (CSR_PQM_TOP_BASE + 0x14A0) /* PQ DFX NUM configure */ +#define CSR_PQM_TOP_SCH_PQ_DFX_UP_CNT_REG (CSR_PQM_TOP_BASE + 0x14A4) /* PQ DFX NUM ENQ UP count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_EMPT_UP_CNT_REG (CSR_PQM_TOP_BASE + 0x14A8) /* PQ DFX NUM ENQ EMPT UP count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_SCH_CNT_REG (CSR_PQM_TOP_BASE + 0x14AC) /* PQ DFX NUM DEQ SCH count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_PT_DEQ_CNT_REG (CSR_PQM_TOP_BASE + 0x14B0) /* PQ DFX NUM PT DEQ SCH count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_EMPT_SCH_CNT_REG (CSR_PQM_TOP_BASE + 0x14B4) /* PQ DFX NUM DEQ EMPT SCH count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_DU_CNT_REG (CSR_PQM_TOP_BASE + 0x14B8) /* PQ DFX NUM DU count */ + +#endif // PQM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_c_union_define.h new file mode 100644 index 000000000..1b93261f5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_c_union_define.h @@ -0,0 +1,2937 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmrx_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:59:21 Create file +// ****************************************************************************** + +#ifndef PRMRX_C_UNION_DEFINE_H +#define PRMRX_C_UNION_DEFINE_H + +/* Define the union csr_prm_top_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_decode_mem_ecc_req : 2; /* [1:0] */ + u32 csr_decode_mem_ecc_bypass : 1; /* [2] */ + u32 mem_power_ctrl : 3; /* [5:3] */ + u32 mem_timing_ctrl : 8; /* [13:6] */ + u32 mem_init_start : 1; /* [14] */ + u32 mem_init_done : 1; /* [15] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mem_ctrl_u; + +/* Define the union csr_prm_top_mqm_bp_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_root_bp_mask : 1; /* [0] */ + u32 mqm_prm_bp_mode : 1; /* [1] */ + u32 rsv_1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask0_u; + +/* Define the union csr_prm_top_mqm_bp_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_ep_bp_mask : 8; /* [7:0] */ + u32 mqm_host_dp_root_bp_mask : 1; /* [8] */ + u32 rsv_2 : 3; /* [11:9] */ + u32 mqm_host_cp_ep_bp_mask : 8; /* [19:12] */ + u32 mqm_host_cp_root_bp_mask : 1; /* [20] */ + u32 rsv_3 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask1_u; + +/* Define the union csr_prm_top_mqm_bp_mask2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_soc_dp_ep_bp_mask : 8; /* [7:0] */ + u32 mqm_soc_dp_root_bp_mask : 1; /* [8] */ + u32 rsv_4 : 3; /* [11:9] */ + u32 mqm_soc_cp_ep_bp_mask : 8; /* [19:12] */ + u32 mqm_soc_cp_root_bp_mask : 1; /* [20] */ + u32 rsv_5 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask2_u; + +/* Define the union csr_prm_top_mqm_bp_mask3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_cos_bp_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask3_u; + +/* Define the union csr_prm_top_mqm_bp_mask4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_cos_bp_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask4_u; + +/* Define the union csr_prm_top_bp_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_fc_mask : 1; /* [0] */ + u32 stfiq_fc_mask : 1; /* [1] */ + u32 oq_fc_mask : 1; /* [2] */ + u32 mag_fc_mask : 1; /* [3] */ + u32 cpb_fc_mask : 1; /* [4] */ + u32 cpi_fc_mask : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_bp_mask_u; + +/* Define the union csr_prm_top_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_7 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int_vector_u; + +/* Define the union csr_prm_top_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_9 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int_u; + +/* Define the union csr_prm_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_10 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int_en_u; + +/* Define the union csr_prm_top_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_fifo_overflow : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 prm_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int0_sticky_u; + +/* Define the union csr_prm_top_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_fifo_underflow : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 prm_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int1_sticky_u; + +/* Define the union csr_prm_top_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_2bit : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 prm_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int2_sticky_u; + +/* Define the union csr_prm_top_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 prm_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int3_sticky_u; + +/* Define the union csr_prm_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_pd_proc_cnt_underflow : 1; /* [0] */ + u32 int_insr4 : 1; /* [1] */ + u32 prm_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_int4_sticky_u; + +/* Define the union csr_prm_int5_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_rx_lb_cos_drop : 1; /* [0] */ + u32 int_insr5 : 1; /* [1] */ + u32 prm_int5_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_int5_sticky_u; + +/* Define the union csr_prm_fifo_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fifo_over_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st0_u; + +/* Define the union csr_prm_fifo_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fifo_under_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st1_u; + +/* Define the union csr_prm_fifo_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fifo_over_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st2_u; + +/* Define the union csr_prm_fifo_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fifo_under_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st3_u; + +/* Define the union csr_prm_src_in_vio_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_in_vio : 15; /* [14:0] */ + u32 rsv_11 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_src_in_vio_u; + +/* Define the union csr_prm_top_mqm_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_root_bp : 1; /* [0] */ + u32 rsv_12 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp0_u; + +/* Define the union csr_prm_top_mqm_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_ep_bp : 8; /* [7:0] */ + u32 mqm_host_dp_root_bp : 1; /* [8] */ + u32 rsv_13 : 3; /* [11:9] */ + u32 mqm_host_cp_ep_bp : 8; /* [19:12] */ + u32 mqm_host_cp_root_bp : 1; /* [20] */ + u32 rsv_14 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp1_u; + +/* Define the union csr_prm_top_mqm_bp2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_soc_dp_ep_bp : 8; /* [7:0] */ + u32 mqm_soc_dp_root_bp : 1; /* [8] */ + u32 rsv_15 : 3; /* [11:9] */ + u32 mqm_soc_cp_ep_bp : 8; /* [19:12] */ + u32 mqm_soc_cp_root_bp : 1; /* [20] */ + u32 rsv_16 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp2_u; + +/* Define the union csr_prm_top_mqm_bp3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_cos_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp3_u; + +/* Define the union csr_prm_top_mag_port_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mag_rx_port_bp : 8; /* [7:0] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mag_port_bp_u; + +/* Define the union csr_prm_top_mag_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_fc_cos_n_merg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mag_cos_bp_u; + +/* Define the union csr_prm_top_oq_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_fc_cos_n_merg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_oq_cos_bp_u; + +/* Define the union csr_prm_top_cpi_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_cpi_cos_bp_u; + +/* Define the union csr_prm_top_cpb_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fc_cos_n_merg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_cpb_cos_bp_u; + +/* Define the union csr_prm_top_iq_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iq_bp_sft_sub_port : 5; /* [4:0] */ + u32 iq_bp_sft_side : 1; /* [5] */ + u32 iq_bp_sft_en : 1; /* [6] */ + u32 rsv_18 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_iq_bp_cfg_u; + +/* Define the union csr_prm_top_stl_iq_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_stliq_icb_stf_eventq_plb_bp : 8; /* [7:0] */ + u32 prm_stliq_icb_evntq_llb_bp : 8; /* [15:8] */ + u32 prm_stliq_icb_evntq_plb_bp : 8; /* [23:16] */ + u32 prm_stliq_icb_nrmlq_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stl_iq_bp0_u; + +/* Define the union csr_prm_top_stl_iq_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 8; /* [7:0] */ + u32 rsv_20 : 8; /* [15:8] */ + u32 rsv_21 : 8; /* [23:16] */ + u32 prm_stliq_icb_stf_eventq_llb_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stl_iq_bp1_u; + +/* Define the union csr_prm_top_stf_iq_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_stfiq_icb_evntq_ddr_bp : 8; /* [7:0] */ + u32 prm_stfiq_icb_evntq_llb_bp : 8; /* [15:8] */ + u32 prm_stfiq_icb_evntq_plb_bp : 8; /* [23:16] */ + u32 prm_stfiq_icb_shallowq_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stf_iq_bp0_u; + +/* Define the union csr_prm_top_stf_iq_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_stfiq_icb_cmd_dbe_bp : 8; /* [7:0] */ + u32 prm_stfiq_icb_cmd_pkt_bp : 8; /* [15:8] */ + u32 prm_stfiq_icb_nret_bp : 8; /* [23:16] */ + u32 prm_stfiq_icb_nrml_dbe_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stf_iq_bp1_u; + +/* Define the union csr_prm_top_1bit_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_1bit_ecc_err_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_top_mem_ctrl_u prm_top_mem_ctrl; /* 0 */ + volatile csr_prm_top_mqm_bp_mask0_u prm_top_mqm_bp_mask0; /* 4 */ + volatile csr_prm_top_mqm_bp_mask1_u prm_top_mqm_bp_mask1; /* 8 */ + volatile csr_prm_top_mqm_bp_mask2_u prm_top_mqm_bp_mask2; /* C */ + volatile csr_prm_top_mqm_bp_mask3_u prm_top_mqm_bp_mask3; /* 10 */ + volatile csr_prm_top_mqm_bp_mask4_u prm_top_mqm_bp_mask4; /* 14 */ + volatile csr_prm_top_bp_mask_u prm_top_bp_mask; /* 18 */ + volatile csr_prm_top_int_vector_u prm_top_int_vector; /* 5C */ + volatile csr_prm_top_int_u prm_top_int; /* 60 */ + volatile csr_prm_top_int_en_u prm_top_int_en; /* 64 */ + volatile csr_prm_top_int0_sticky_u prm_top_int0_sticky; /* 68 */ + volatile csr_prm_top_int1_sticky_u prm_top_int1_sticky; /* 6C */ + volatile csr_prm_top_int2_sticky_u prm_top_int2_sticky; /* 70 */ + volatile csr_prm_top_int3_sticky_u prm_top_int3_sticky; /* 74 */ + volatile csr_prm_int4_sticky_u prm_int4_sticky; /* 78 */ + volatile csr_prm_int5_sticky_u prm_int5_sticky; /* 7C */ + volatile csr_prm_fifo_st0_u prm_fifo_st0; /* 100 */ + volatile csr_prm_fifo_st1_u prm_fifo_st1; /* 104 */ + volatile csr_prm_fifo_st2_u prm_fifo_st2; /* 108 */ + volatile csr_prm_fifo_st3_u prm_fifo_st3; /* 10C */ + volatile csr_prm_src_in_vio_u prm_src_in_vio; /* 110 */ + volatile csr_prm_top_mqm_bp0_u prm_top_mqm_bp0; /* 204 */ + volatile csr_prm_top_mqm_bp1_u prm_top_mqm_bp1; /* 208 */ + volatile csr_prm_top_mqm_bp2_u prm_top_mqm_bp2; /* 20C */ + volatile csr_prm_top_mqm_bp3_u prm_top_mqm_bp3[2]; /* 210 */ + volatile csr_prm_top_mag_port_bp_u prm_top_mag_port_bp; /* 220 */ + volatile csr_prm_top_mag_cos_bp_u prm_top_mag_cos_bp[2]; /* 240 */ + volatile csr_prm_top_oq_cos_bp_u prm_top_oq_cos_bp[4]; /* 250 */ + volatile csr_prm_top_cpi_cos_bp_u prm_top_cpi_cos_bp[3]; /* 260 */ + volatile csr_prm_top_cpb_cos_bp_u prm_top_cpb_cos_bp[3]; /* 270 */ + volatile csr_prm_top_iq_bp_cfg_u prm_top_iq_bp_cfg; /* 290 */ + volatile csr_prm_top_stl_iq_bp0_u prm_top_stl_iq_bp0; /* 294 */ + volatile csr_prm_top_stl_iq_bp1_u prm_top_stl_iq_bp1; /* 298 */ + volatile csr_prm_top_stf_iq_bp0_u prm_top_stf_iq_bp0; /* 29C */ + volatile csr_prm_top_stf_iq_bp1_u prm_top_stf_iq_bp1; /* 2A0 */ + volatile csr_prm_top_1bit_ecc_err_u prm_top_1bit_ecc_err; /* 2A4 */ +} S_qu_prm_top_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_top_csr */ +extern volatile S_qu_prm_top_csr_REGS_TYPE *gopqu_prm_top_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_TOP_MEM_CTRL_csr_decode_mem_ecc_req(unsigned int ucsr_decode_mem_ecc_req); +int iSetPRM_TOP_MEM_CTRL_csr_decode_mem_ecc_bypass(unsigned int ucsr_decode_mem_ecc_bypass); +int iSetPRM_TOP_MEM_CTRL_mem_power_ctrl(unsigned int umem_power_ctrl); +int iSetPRM_TOP_MEM_CTRL_mem_timing_ctrl(unsigned int umem_timing_ctrl); +int iSetPRM_TOP_MEM_CTRL_mem_init_start(unsigned int umem_init_start); +int iSetPRM_TOP_MEM_CTRL_mem_init_done(unsigned int umem_init_done); +int iSetPRM_TOP_MQM_BP_MASK0_mqm_root_bp_mask(unsigned int umqm_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK0_mqm_prm_bp_mode(unsigned int umqm_prm_bp_mode); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_dp_ep_bp_mask(unsigned int umqm_host_dp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_dp_root_bp_mask(unsigned int umqm_host_dp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_cp_ep_bp_mask(unsigned int umqm_host_cp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_cp_root_bp_mask(unsigned int umqm_host_cp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_dp_ep_bp_mask(unsigned int umqm_soc_dp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_dp_root_bp_mask(unsigned int umqm_soc_dp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_cp_ep_bp_mask(unsigned int umqm_soc_cp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_cp_root_bp_mask(unsigned int umqm_soc_cp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK3_mqm_host_dp_cos_bp_mask0(unsigned int umqm_host_dp_cos_bp_mask0); +int iSetPRM_TOP_MQM_BP_MASK4_mqm_host_dp_cos_bp_mask1(unsigned int umqm_host_dp_cos_bp_mask1); +int iSetPRM_TOP_BP_MASK_stliq_fc_mask(unsigned int ustliq_fc_mask); +int iSetPRM_TOP_BP_MASK_stfiq_fc_mask(unsigned int ustfiq_fc_mask); +int iSetPRM_TOP_BP_MASK_oq_fc_mask(unsigned int uoq_fc_mask); +int iSetPRM_TOP_BP_MASK_mag_fc_mask(unsigned int umag_fc_mask); +int iSetPRM_TOP_BP_MASK_cpb_fc_mask(unsigned int ucpb_fc_mask); +int iSetPRM_TOP_BP_MASK_cpi_fc_mask(unsigned int ucpi_fc_mask); +int iSetPRM_TOP_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetPRM_TOP_INT_VECTOR_enable(unsigned int uenable); +int iSetPRM_TOP_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetPRM_TOP_INT_int_data(unsigned int uint_data); +int iSetPRM_TOP_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetPRM_TOP_INT_EN_int_en(unsigned int uint_en); +int iSetPRM_TOP_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetPRM_TOP_INT0_STICKY_prm_fifo_overflow(unsigned int uprm_fifo_overflow); +int iSetPRM_TOP_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetPRM_TOP_INT0_STICKY_prm_int0_sticky(unsigned int uprm_int0_sticky); +int iSetPRM_TOP_INT1_STICKY_prm_fifo_underflow(unsigned int uprm_fifo_underflow); +int iSetPRM_TOP_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetPRM_TOP_INT1_STICKY_prm_int1_sticky(unsigned int uprm_int1_sticky); +int iSetPRM_TOP_INT2_STICKY_mem_ecc_2bit(unsigned int umem_ecc_2bit); +int iSetPRM_TOP_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetPRM_TOP_INT2_STICKY_prm_int2_sticky(unsigned int uprm_int2_sticky); +int iSetPRM_TOP_INT3_STICKY_mem_ecc_1bit(unsigned int umem_ecc_1bit); +int iSetPRM_TOP_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetPRM_TOP_INT3_STICKY_prm_int3_sticky(unsigned int uprm_int3_sticky); +int iSetPRM_INT4_STICKY_prm_pd_proc_cnt_underflow(unsigned int uprm_pd_proc_cnt_underflow); +int iSetPRM_INT4_STICKY_int_insr4(unsigned int uint_insr4); +int iSetPRM_INT4_STICKY_prm_int4_sticky(unsigned int uprm_int4_sticky); +int iSetPRM_INT5_STICKY_prm_rx_lb_cos_drop(unsigned int uprm_rx_lb_cos_drop); +int iSetPRM_INT5_STICKY_int_insr5(unsigned int uint_insr5); +int iSetPRM_INT5_STICKY_prm_int5_sticky(unsigned int uprm_int5_sticky); +int iSetPRM_FIFO_ST0_tx_fifo_over_flag(unsigned int utx_fifo_over_flag); +int iSetPRM_FIFO_ST1_tx_fifo_under_flag(unsigned int utx_fifo_under_flag); +int iSetPRM_FIFO_ST2_rx_fifo_over_flag(unsigned int urx_fifo_over_flag); +int iSetPRM_FIFO_ST3_rx_fifo_under_flag(unsigned int urx_fifo_under_flag); +int iSetPRM_SRC_IN_VIO_src_in_vio(unsigned int usrc_in_vio); +int iSetPRM_TOP_MQM_BP0_mqm_root_bp(unsigned int umqm_root_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_dp_ep_bp(unsigned int umqm_host_dp_ep_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_dp_root_bp(unsigned int umqm_host_dp_root_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_cp_ep_bp(unsigned int umqm_host_cp_ep_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_cp_root_bp(unsigned int umqm_host_cp_root_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_dp_ep_bp(unsigned int umqm_soc_dp_ep_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_dp_root_bp(unsigned int umqm_soc_dp_root_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_cp_ep_bp(unsigned int umqm_soc_cp_ep_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_cp_root_bp(unsigned int umqm_soc_cp_root_bp); +int iSetPRM_TOP_MQM_BP3_mqm_host_dp_cos_bp(unsigned int umqm_host_dp_cos_bp); +int iSetPRM_TOP_MAG_PORT_BP_prm_mag_rx_port_bp(unsigned int uprm_mag_rx_port_bp); +int iSetPRM_TOP_MAG_COS_BP_mag_fc_cos_n_merg(unsigned int umag_fc_cos_n_merg); +int iSetPRM_TOP_OQ_COS_BP_oq_fc_cos_n_merg(unsigned int uoq_fc_cos_n_merg); +int iSetPRM_TOP_CPI_COS_BP_prm_cpi_src_bp(unsigned int uprm_cpi_src_bp); +int iSetPRM_TOP_CPB_COS_BP_cpb_fc_cos_n_merg(unsigned int ucpb_fc_cos_n_merg); +int iSetPRM_TOP_IQ_BP_CFG_iq_bp_sft_sub_port(unsigned int uiq_bp_sft_sub_port); +int iSetPRM_TOP_IQ_BP_CFG_iq_bp_sft_side(unsigned int uiq_bp_sft_side); +int iSetPRM_TOP_IQ_BP_CFG_iq_bp_sft_en(unsigned int uiq_bp_sft_en); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_stf_eventq_plb_bp(unsigned int uprm_stliq_icb_stf_eventq_plb_bp); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_evntq_llb_bp(unsigned int uprm_stliq_icb_evntq_llb_bp); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_evntq_plb_bp(unsigned int uprm_stliq_icb_evntq_plb_bp); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_nrmlq_bp(unsigned int uprm_stliq_icb_nrmlq_bp); +int iSetPRM_TOP_STL_IQ_BP1_prm_stliq_icb_stf_eventq_llb_bp(unsigned int uprm_stliq_icb_stf_eventq_llb_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_evntq_ddr_bp(unsigned int uprm_stfiq_icb_evntq_ddr_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_evntq_llb_bp(unsigned int uprm_stfiq_icb_evntq_llb_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_evntq_plb_bp(unsigned int uprm_stfiq_icb_evntq_plb_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_shallowq_bp(unsigned int uprm_stfiq_icb_shallowq_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_cmd_dbe_bp(unsigned int uprm_stfiq_icb_cmd_dbe_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_cmd_pkt_bp(unsigned int uprm_stfiq_icb_cmd_pkt_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_nret_bp(unsigned int uprm_stfiq_icb_nret_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_nrml_dbe_bp(unsigned int uprm_stfiq_icb_nrml_dbe_bp); +int iSetPRM_TOP_1BIT_ECC_ERR_mem_ecc_1bit_inc(unsigned int umem_ecc_1bit_inc); + +/* Define the union csr_prm_rx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_ctrl_u; + +/* Define the union csr_prm_rx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_timeout_u; + +/* Define the union csr_prm_rx_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat0_u; + +/* Define the union csr_prm_rx_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat1_u; + +/* Define the union csr_prm_rx_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat2_u; + +/* Define the union csr_prm_rx_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat3_u; + +/* Define the union csr_prm_rx_csr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dyn_csr_req_src : 8; /* [7:0] */ + u32 bmr_dyn_csr_req : 1; /* [8] */ + u32 bmy_dyn_csr_req : 1; /* [9] */ + u32 bmn_dyn_csr_req : 1; /* [10] */ + u32 rsv_0 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_csr_cfg_u; + +/* Define the union csr_prm_rx_y_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_fc_th_cfg_u; + +/* Define the union csr_prm_rx_y_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_fc_th_cfg_u; + +/* Define the union csr_prm_rx_r_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_fc_th_cfg_u; + +/* Define the union csr_prm_rx_r_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_fc_th_cfg_u; + +/* Define the union csr_prm_rx_y_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_rsvd_cfg_u; + +/* Define the union csr_prm_rx_y_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_rsvd_cfg_u; + +/* Define the union csr_prm_rx_r_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_rsvd_cfg_u; + +/* Define the union csr_prm_rx_r_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_rsvd_cfg_u; + +/* Define the union csr_prm_rx_y_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_cnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_cnt_u; + +/* Define the union csr_prm_rx_y_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_cnt : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_cnt_u; + +/* Define the union csr_prm_rx_r_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_cnt : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_cnt_u; + +/* Define the union csr_prm_rx_r_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_cnt : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_cnt_u; + +/* Define the union csr_prm_rx_y_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_sh_cnt_u; + +/* Define the union csr_prm_rx_y_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_sh_cnt_u; + +/* Define the union csr_prm_rx_r_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_sh_cnt_u; + +/* Define the union csr_prm_rx_r_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_sh_cnt_u; + +/* Define the union csr_prm_rx_y_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_17 : 1; /* [3] */ + u32 bmy_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_18 : 3; /* [11:9] */ + u32 bmy_cfg_mon_srv : 1; /* [12] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 bmy_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_20 : 2; /* [19:18] */ + u32 bmy_cfg_cnt_en : 1; /* [20] */ + u32 rsv_21 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_mon_cfg_u; + +/* Define the union csr_prm_rx_y_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_22 : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 bmy_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_24 : 3; /* [11:9] */ + u32 bmy_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_25 : 3; /* [15:13] */ + u32 bmy_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_26 : 3; /* [19:17] */ + u32 bmy_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_his_cfg_u; + +/* Define the union csr_prm_rx_r_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_28 : 1; /* [3] */ + u32 bmr_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_29 : 3; /* [11:9] */ + u32 bmr_cfg_mon_srv : 1; /* [12] */ + u32 rsv_30 : 3; /* [15:13] */ + u32 bmr_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_31 : 2; /* [19:18] */ + u32 bmr_cfg_cnt_en : 1; /* [20] */ + u32 rsv_32 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_mon_cfg_u; + +/* Define the union csr_prm_rx_r_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 3; /* [2:0] */ + u32 rsv_34 : 1; /* [3] */ + u32 bmr_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_35 : 3; /* [11:9] */ + u32 bmr_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_36 : 3; /* [15:13] */ + u32 bmr_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_37 : 3; /* [19:17] */ + u32 bmr_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_38 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_his_cfg_u; + +/* Define the union csr_prm_rx_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_aloc_u; + +/* Define the union csr_prm_rx_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_aloc_u; + +/* Define the union csr_prm_rx_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_aloc_u; + +/* Define the union csr_prm_rx_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_daloc_u; + +/* Define the union csr_prm_rx_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_daloc_u; + +/* Define the union csr_prm_rx_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_daloc_u; + +/* Define the union csr_prm_rx_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_daloc_u; + +/* Define the union csr_prm_rx_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_drop_u; + +/* Define the union csr_prm_rx_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_oq_daloc_u; + +/* Define the union csr_prm_rx_stlfq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_aloc_cnt_u; + +/* Define the union csr_prm_rx_stffq0_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_aloc_cnt_u; + +/* Define the union csr_prm_rx_stffq1_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_aloc_cnt_u; + +/* Define the union csr_prm_rx_stlfq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_daloc_cnt_u; + +/* Define the union csr_prm_rx_stffq0_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_daloc_cnt_u; + +/* Define the union csr_prm_rx_stffq1_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_daloc_cnt_u; + +/* Define the union csr_prm_rx_cpb_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_daloc_cnt_u; + +/* Define the union csr_prm_rx_cpb_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_drop_cnt_u; + +/* Define the union csr_prm_rx_oq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_oq_daloc_cnt_u; + +/* Define the union csr_prm_rx_r_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_p_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_p_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_srv_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_srv_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_srv_sh_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_srv_sh_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_45 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_st_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_46 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_st_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_stfiq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stfiq_aloc_u; + +/* Define the union csr_prm_rx_stliq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stliq_aloc_u; + +/* Define the union csr_prm_rx_yda_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_yda_daloc_u; + +/* Define the union csr_prm_rx_stfiq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stfiq_aloc_cnt_u; + +/* Define the union csr_prm_rx_stliq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stliq_aloc_cnt_u; + +/* Define the union csr_prm_rx_yda_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_yda_daloc_cnt_u; + +/* Define the union csr_prm_rx_y_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_p_his_cnt_u; + +/* Define the union csr_prm_rx_y_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_50 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_p_his_cnt_u; + +/* Define the union csr_prm_rx_y_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_st_his_cnt_u; + +/* Define the union csr_prm_rx_y_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_st_his_cnt_u; + +/* Define the union csr_prm_rx_y_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_y_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_g_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_55 : 1; /* [3] */ + u32 bmn_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_56 : 3; /* [11:9] */ + u32 bmn_cfg_mon_side : 1; /* [12] */ + u32 rsv_57 : 3; /* [15:13] */ + u32 bmn_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_58 : 2; /* [19:18] */ + u32 bmn_cfg_cnt_en : 1; /* [20] */ + u32 rsv_59 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_g_mon_cfg_u; + +/* Define the union csr_prm_rx_g_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cfg_his_cnt_cos : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 bmn_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_61 : 3; /* [11:9] */ + u32 rsv_62 : 1; /* [12] */ + u32 rsv_63 : 3; /* [15:13] */ + u32 bmn_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_64 : 3; /* [19:17] */ + u32 bmn_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_65 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_g_his_cfg_u; + +/* Define the union csr_prm_rx_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cpb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_aloc_u; + +/* Define the union csr_prm_rx_grq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_aloc_u; + +/* Define the union csr_prm_rx_grq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_daloc_u; + +/* Define the union csr_prm_rx_cpb_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cpb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_aloc_cnt_u; + +/* Define the union csr_prm_rx_grq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_aloc_cnt_u; + +/* Define the union csr_prm_rx_grq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_daloc_cnt_u; + +/* Define the union csr_prm_rx_n_cos_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_cnt_cos : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_cos_his_cnt_u; + +/* Define the union csr_prm_rx_n_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_cnt_port : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_p_his_cnt_u; + +/* Define the union csr_prm_rx_n_p_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_sh_cnt_port : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_p_sh_his_cnt_u; + +/* Define the union csr_prm_rx_n_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_srv_his_cnt_u; + +/* Define the union csr_prm_rx_n_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_sh_cnt_srv : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_srv_sh_his_cnt_u; + +/* Define the union csr_prm_rx_glb_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_rsvd_th : 16; /* [15:0] */ + u32 rsv_71 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_rsvd_cfg_u; + +/* Define the union csr_prm_rx_glb_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc0_th_on : 16; /* [15:0] */ + u32 glb_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_glb_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc1_th_on : 16; /* [15:0] */ + u32 glb_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_73 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_glb_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc2_th_on : 16; /* [15:0] */ + u32 glb_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_74 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_glb_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_drp_th_on : 16; /* [15:0] */ + u32 glb_drp_th_dif : 8; /* [23:16] */ + u32 rsv_75 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg0_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_rsvd_th : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_rsvd_cfg_u; + +/* Define the union csr_prm_rx_pg0_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_fc0_th_on : 16; /* [15:0] */ + u32 pg0_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_77 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_pg0_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_fc1_th_on : 16; /* [15:0] */ + u32 pg0_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_78 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_pg0_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_fc2_th_on : 16; /* [15:0] */ + u32 pg0_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_79 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_pg0_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_drp_th_on : 16; /* [15:0] */ + u32 pg0_drp_th_dif : 8; /* [23:16] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg2_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_rsvd_th : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_rsvd_cfg_u; + +/* Define the union csr_prm_rx_pg2_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc0_th_on : 16; /* [15:0] */ + u32 pg2_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_82 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_pg2_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc1_th_on : 16; /* [15:0] */ + u32 pg2_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_83 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_pg2_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc2_th_on : 16; /* [15:0] */ + u32 pg2_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_84 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_pg2_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_drp_th_on : 16; /* [15:0] */ + u32 pg2_drp_th_dif : 8; /* [23:16] */ + u32 rsv_85 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg3_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_rsvd_th : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_rsvd_cfg_u; + +/* Define the union csr_prm_rx_pg3_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc0_th_on : 16; /* [15:0] */ + u32 pg3_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_87 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_pg3_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc1_th_on : 16; /* [15:0] */ + u32 pg3_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_pg3_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc2_th_on : 16; /* [15:0] */ + u32 pg3_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_pg3_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_drp_th_on : 16; /* [15:0] */ + u32 pg3_drp_th_dif : 8; /* [23:16] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg0_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg0_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_cnt_u; + +/* Define the union csr_prm_rx_pg2_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg2_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_cnt_u; + +/* Define the union csr_prm_rx_pg3_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg3_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_cnt_u; + +/* Define the union csr_prm_rx_glb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_curr_sh_cnt_st : 16; /* [15:0] */ + u32 glb_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_cnt_u; + +/* Define the union csr_prm_rx_glb_max_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_glb_max_th : 16; /* [15:0] */ + u32 cfg_glb_max_sh : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_max_cnt_cfg_u; + +/* Define the union csr_prm_rx_ipsu_bp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_bp_all_th : 16; /* [15:0] */ + u32 ipsurx_bp_rand_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_ipsu_bp_th_cfg_u; + +/* Define the union csr_prm_rx_bmn_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmn_wrr_wgt_cfg : 8; /* [7:0] */ + u32 rsv_91 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmn_wrr_cfg_u; + +/* Define the union csr_prm_rx_bmy_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmy_wrr_wgt_cfg : 12; /* [11:0] */ + u32 rsv_92 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmy_wrr_cfg_u; + +/* Define the union csr_prm_rx_bmr_wrr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmr_wrr_wgt_cfg0 : 24; /* [23:0] */ + u32 rsv_93 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmr_wrr_cfg0_u; + +/* Define the union csr_prm_rx_bmr_wrr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmn_wrr_wgt_cfg1 : 12; /* [11:0] */ + u32 rsv_94 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmr_wrr_cfg1_u; + +/* Define the union csr_prm_rx_bmg_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmg_wrr_wgt_cfg : 16; /* [15:0] */ + u32 rsv_95 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmg_wrr_cfg_u; + +/* Define the union csr_prm_rx_cnt_over_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_n_of : 1; /* [0] */ + u32 mem_cnt_p_n_of : 1; /* [1] */ + u32 mem_cnt_srv_n_of : 1; /* [2] */ + u32 mem_sh_cnt_p_n_of : 1; /* [3] */ + u32 mem_sh_cnt_srv_n_of : 1; /* [4] */ + u32 mem_cnt_stf_p_y_of : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_of : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_of : 1; /* [7] */ + u32 mem_cnt_stl_p_y_of : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_of : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_of : 1; /* [10] */ + u32 mem_cnt_stf_p_r_of : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_of : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_of : 1; /* [13] */ + u32 mem_cnt_stl_p_r_of : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_of : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_of : 1; /* [16] */ + u32 glb_cnt_of : 1; /* [17] */ + u32 pg3_cnt_of : 1; /* [18] */ + u32 pg2_cnt_of : 1; /* [19] */ + u32 pg0_cnt_of : 1; /* [20] */ + u32 glb_sh_cnt_of : 1; /* [21] */ + u32 pg3_sh_cnt_of : 1; /* [22] */ + u32 pg2_sh_cnt_of : 1; /* [23] */ + u32 pg0_sh_cnt_of : 1; /* [24] */ + u32 rsv_96 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cnt_over_flag_u; + +/* Define the union csr_prm_rx_cnt_under_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_n_uf : 1; /* [0] */ + u32 mem_cnt_p_n_uf : 1; /* [1] */ + u32 mem_cnt_srv_n_uf : 1; /* [2] */ + u32 mem_sh_cnt_p_n_uf : 1; /* [3] */ + u32 mem_sh_cnt_srv_n_uf : 1; /* [4] */ + u32 mem_cnt_stf_p_y_uf : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_uf : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_uf : 1; /* [7] */ + u32 mem_cnt_stl_p_y_uf : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_uf : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_uf : 1; /* [10] */ + u32 mem_cnt_stf_p_r_uf : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_uf : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_uf : 1; /* [13] */ + u32 mem_cnt_stl_p_r_uf : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_uf : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_uf : 1; /* [16] */ + u32 glb_cnt_uf : 1; /* [17] */ + u32 pg3_cnt_uf : 1; /* [18] */ + u32 pg2_cnt_uf : 1; /* [19] */ + u32 pg0_cnt_uf : 1; /* [20] */ + u32 glb_sh_cnt_uf : 1; /* [21] */ + u32 pg3_sh_cnt_uf : 1; /* [22] */ + u32 pg2_sh_cnt_uf : 1; /* [23] */ + u32 pg0_sh_cnt_uf : 1; /* [24] */ + u32 rsv_97 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cnt_under_flag_u; + +/* Define the union csr_prm_rx_fifo_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stffq1_daloc_n_af_th : 5; /* [4:0] */ + u32 stffq1_aloc_n_af_th : 5; /* [9:5] */ + u32 stffq0_daloc_n_af_th : 5; /* [14:10] */ + u32 stffq0_aloc_n_af_th : 5; /* [19:15] */ + u32 stlfq_daloc_n_af_th : 5; /* [24:20] */ + u32 stlfq_aloc_n_af_th : 5; /* [29:25] */ + u32 rsv_98 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_fifo_th_cfg0_u; + +/* Define the union csr_prm_rx_fifo_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_n_af_th : 5; /* [4:0] */ + u32 stliq_n_af_th : 5; /* [9:5] */ + u32 oq_daloc_n_af_th : 5; /* [14:10] */ + u32 rsv_99 : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_fifo_th_cfg1_u; + +/* Define the union csr_prm_rx_fifo_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_aloc_n_af_th : 6; /* [5:0] */ + u32 rsv_101 : 2; /* [7:6] */ + u32 cpb_daloc_n_af_th : 6; /* [13:8] */ + u32 rsv_102 : 2; /* [15:14] */ + u32 rsv_103 : 7; /* [22:16] */ + u32 rsv_104 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_fifo_th_cfg2_u; + +/* Define the union csr_prm_rx_double_daloc_wgt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_stl_daloc_pg3_wgt_cfg : 8; /* [7:0] */ + u32 stf_stl_daloc_pg2_wgt_cfg : 8; /* [15:8] */ + u32 rsv_105 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_double_daloc_wgt_u; + +/* Define the union csr_prm_rx_pqm_uload_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_pqm_underloading_th : 16; /* [15:0] */ + u32 rsv_106 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pqm_uload_cfg_u; + +/* Define the union csr_prm_rx_err_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_uder_src_err : 9; /* [8:0] */ + u32 cos_over_src_err : 9; /* [17:9] */ + u32 rsv_107 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_err_src_u; + +/* Define the union csr_prmrx_bw_monitor_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_cpb_aloc_bdmonitor_en : 1; /* [0] */ + u32 csr_prmrx_cpb_daloc_bdmonitor_en : 1; /* [1] */ + u32 csr_prmrx_cpb_src1_daloc_bdmonitor_en : 1; /* [2] */ + u32 csr_prmrx_cpb_drop_bdmonitor_en : 1; /* [3] */ + u32 csr_prmrx_stliq_bdmonitor_en : 1; /* [4] */ + u32 csr_prmrx_stfiq_bdmonitor_en : 1; /* [5] */ + u32 csr_prmrx_stlfq_aloc_bdmonitor_en : 1; /* [6] */ + u32 csr_prmrx_stffq0_aloc_bdmonitor_en : 1; /* [7] */ + u32 csr_prmrx_stffq1_aloc_bdmonitor_en : 1; /* [8] */ + u32 csr_prmrx_stlfq_daloc_bdmonitor_en : 1; /* [9] */ + u32 csr_prmrx_stffq0_daloc_bdmonitor_en : 1; /* [10] */ + u32 csr_prmrx_stffq1_daloc_bdmonitor_en : 1; /* [11] */ + u32 csr_prmrx_oq_daloc_bdmonitor_en : 1; /* [12] */ + u32 rsv_108 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_en_u; + +/* Define the union csr_prmrx_bw_monitor_win_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_win_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_win_len_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_src1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_src1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_src1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_drop_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stliq_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stfiq_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stlfq_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq0_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq1_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stlfq_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq0_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_oq_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_win_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_win_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_win_cnt_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_src1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_drop_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stliq_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stfiq_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_oq_daloc_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_rx_indrect_ctrl_u prm_rx_indrect_ctrl; /* 0 */ + volatile csr_prm_rx_indrect_timeout_u prm_rx_indrect_timeout; /* 4 */ + volatile csr_prm_rx_indrect_dat0_u prm_rx_indrect_dat0; /* 8 */ + volatile csr_prm_rx_indrect_dat1_u prm_rx_indrect_dat1; /* C */ + volatile csr_prm_rx_indrect_dat2_u prm_rx_indrect_dat2; /* 10 */ + volatile csr_prm_rx_indrect_dat3_u prm_rx_indrect_dat3; /* 14 */ + volatile csr_prm_rx_csr_cfg_u prm_rx_csr_cfg; /* 30 */ + volatile csr_prm_rx_y_stf_fc_th_cfg_u prm_rx_y_stf_fc_th_cfg; /* 34 */ + volatile csr_prm_rx_y_stl_fc_th_cfg_u prm_rx_y_stl_fc_th_cfg; /* 38 */ + volatile csr_prm_rx_r_stf_fc_th_cfg_u prm_rx_r_stf_fc_th_cfg; /* 3C */ + volatile csr_prm_rx_r_stl_fc_th_cfg_u prm_rx_r_stl_fc_th_cfg; /* 40 */ + volatile csr_prm_rx_y_stf_rsvd_cfg_u prm_rx_y_stf_rsvd_cfg; /* 44 */ + volatile csr_prm_rx_y_stl_rsvd_cfg_u prm_rx_y_stl_rsvd_cfg; /* 48 */ + volatile csr_prm_rx_r_stf_rsvd_cfg_u prm_rx_r_stf_rsvd_cfg; /* 4C */ + volatile csr_prm_rx_r_stl_rsvd_cfg_u prm_rx_r_stl_rsvd_cfg; /* 50 */ + volatile csr_prm_rx_y_stf_cnt_u prm_rx_y_stf_cnt; /* 54 */ + volatile csr_prm_rx_y_stl_cnt_u prm_rx_y_stl_cnt; /* 58 */ + volatile csr_prm_rx_r_stf_cnt_u prm_rx_r_stf_cnt; /* 5C */ + volatile csr_prm_rx_r_stl_cnt_u prm_rx_r_stl_cnt; /* 60 */ + volatile csr_prm_rx_y_stf_sh_cnt_u prm_rx_y_stf_sh_cnt; /* 64 */ + volatile csr_prm_rx_y_stl_sh_cnt_u prm_rx_y_stl_sh_cnt; /* 68 */ + volatile csr_prm_rx_r_stf_sh_cnt_u prm_rx_r_stf_sh_cnt; /* 6C */ + volatile csr_prm_rx_r_stl_sh_cnt_u prm_rx_r_stl_sh_cnt; /* 70 */ + volatile csr_prm_rx_y_mon_cfg_u prm_rx_y_mon_cfg; /* 74 */ + volatile csr_prm_rx_y_his_cfg_u prm_rx_y_his_cfg; /* 78 */ + volatile csr_prm_rx_r_mon_cfg_u prm_rx_r_mon_cfg; /* 7C */ + volatile csr_prm_rx_r_his_cfg_u prm_rx_r_his_cfg; /* 80 */ + volatile csr_prm_rx_stlfq_aloc_u prm_rx_stlfq_aloc; /* 84 */ + volatile csr_prm_rx_stffq0_aloc_u prm_rx_stffq0_aloc; /* 88 */ + volatile csr_prm_rx_stffq1_aloc_u prm_rx_stffq1_aloc; /* 8C */ + volatile csr_prm_rx_stlfq_daloc_u prm_rx_stlfq_daloc; /* 90 */ + volatile csr_prm_rx_stffq0_daloc_u prm_rx_stffq0_daloc; /* 94 */ + volatile csr_prm_rx_stffq1_daloc_u prm_rx_stffq1_daloc; /* 98 */ + volatile csr_prm_rx_cpb_daloc_u prm_rx_cpb_daloc; /* 9C */ + volatile csr_prm_rx_cpb_drop_u prm_rx_cpb_drop; /* A0 */ + volatile csr_prm_rx_oq_daloc_u prm_rx_oq_daloc; /* A4 */ + volatile csr_prm_rx_stlfq_aloc_cnt_u prm_rx_stlfq_aloc_cnt; /* A8 */ + volatile csr_prm_rx_stffq0_aloc_cnt_u prm_rx_stffq0_aloc_cnt; /* AC */ + volatile csr_prm_rx_stffq1_aloc_cnt_u prm_rx_stffq1_aloc_cnt; /* B0 */ + volatile csr_prm_rx_stlfq_daloc_cnt_u prm_rx_stlfq_daloc_cnt; /* B4 */ + volatile csr_prm_rx_stffq0_daloc_cnt_u prm_rx_stffq0_daloc_cnt; /* B8 */ + volatile csr_prm_rx_stffq1_daloc_cnt_u prm_rx_stffq1_daloc_cnt; /* BC */ + volatile csr_prm_rx_cpb_daloc_cnt_u prm_rx_cpb_daloc_cnt; /* C0 */ + volatile csr_prm_rx_cpb_drop_cnt_u prm_rx_cpb_drop_cnt; /* C4 */ + volatile csr_prm_rx_oq_daloc_cnt_u prm_rx_oq_daloc_cnt; /* C8 */ + volatile csr_prm_rx_r_stf_p_his_cnt_u prm_rx_r_stf_p_his_cnt; /* CC */ + volatile csr_prm_rx_r_stl_p_his_cnt_u prm_rx_r_stl_p_his_cnt; /* D0 */ + volatile csr_prm_rx_r_stf_srv_his_cnt_u prm_rx_r_stf_srv_his_cnt; /* D4 */ + volatile csr_prm_rx_r_stl_srv_his_cnt_u prm_rx_r_stl_srv_his_cnt; /* D8 */ + volatile csr_prm_rx_r_stf_srv_sh_his_cnt_u prm_rx_r_stf_srv_sh_his_cnt; /* DC */ + volatile csr_prm_rx_r_stl_srv_sh_his_cnt_u prm_rx_r_stl_srv_sh_his_cnt; /* E0 */ + volatile csr_prm_rx_r_stf_st_his_cnt_u prm_rx_r_stf_st_his_cnt; /* E4 */ + volatile csr_prm_rx_r_stl_st_his_cnt_u prm_rx_r_stl_st_his_cnt; /* E8 */ + volatile csr_prm_rx_r_stf_st_sh_his_cnt_u prm_rx_r_stf_st_sh_his_cnt; /* EC */ + volatile csr_prm_rx_r_stl_st_sh_his_cnt_u prm_rx_r_stl_st_sh_his_cnt; /* F0 */ + volatile csr_prm_rx_stfiq_aloc_u prm_rx_stfiq_aloc; /* F4 */ + volatile csr_prm_rx_stliq_aloc_u prm_rx_stliq_aloc; /* F8 */ + volatile csr_prm_rx_yda_daloc_u prm_rx_yda_daloc; /* FC */ + volatile csr_prm_rx_stfiq_aloc_cnt_u prm_rx_stfiq_aloc_cnt; /* 100 */ + volatile csr_prm_rx_stliq_aloc_cnt_u prm_rx_stliq_aloc_cnt; /* 104 */ + volatile csr_prm_rx_yda_daloc_cnt_u prm_rx_yda_daloc_cnt; /* 108 */ + volatile csr_prm_rx_y_stf_p_his_cnt_u prm_rx_y_stf_p_his_cnt; /* 10C */ + volatile csr_prm_rx_y_stl_p_his_cnt_u prm_rx_y_stl_p_his_cnt; /* 110 */ + volatile csr_prm_rx_y_stf_st_his_cnt_u prm_rx_y_stf_st_his_cnt; /* 114 */ + volatile csr_prm_rx_y_stl_st_his_cnt_u prm_rx_y_stl_st_his_cnt; /* 118 */ + volatile csr_prm_rx_y_stf_st_sh_his_cnt_u prm_rx_y_stf_st_sh_his_cnt; /* 11C */ + volatile csr_prm_rx_y_stl_st_sh_his_cnt_u prm_rx_y_stl_st_sh_his_cnt; /* 120 */ + volatile csr_prm_rx_g_mon_cfg_u prm_rx_g_mon_cfg; /* 124 */ + volatile csr_prm_rx_g_his_cfg_u prm_rx_g_his_cfg; /* 128 */ + volatile csr_prm_rx_cpb_aloc_u prm_rx_cpb_aloc; /* 12C */ + volatile csr_prm_rx_grq_aloc_u prm_rx_grq_aloc; /* 130 */ + volatile csr_prm_rx_grq_daloc_u prm_rx_grq_daloc; /* 134 */ + volatile csr_prm_rx_cpb_aloc_cnt_u prm_rx_cpb_aloc_cnt; /* 138 */ + volatile csr_prm_rx_grq_aloc_cnt_u prm_rx_grq_aloc_cnt; /* 13C */ + volatile csr_prm_rx_grq_daloc_cnt_u prm_rx_grq_daloc_cnt; /* 140 */ + volatile csr_prm_rx_n_cos_his_cnt_u prm_rx_n_cos_his_cnt; /* 144 */ + volatile csr_prm_rx_n_p_his_cnt_u prm_rx_n_p_his_cnt; /* 148 */ + volatile csr_prm_rx_n_p_sh_his_cnt_u prm_rx_n_p_sh_his_cnt; /* 14C */ + volatile csr_prm_rx_n_srv_his_cnt_u prm_rx_n_srv_his_cnt; /* 150 */ + volatile csr_prm_rx_n_srv_sh_his_cnt_u prm_rx_n_srv_sh_his_cnt; /* 154 */ + volatile csr_prm_rx_glb_rsvd_cfg_u prm_rx_glb_rsvd_cfg; /* 158 */ + volatile csr_prm_rx_glb_fc_th_cfg0_u prm_rx_glb_fc_th_cfg0; /* 15C */ + volatile csr_prm_rx_glb_fc_th_cfg1_u prm_rx_glb_fc_th_cfg1; /* 160 */ + volatile csr_prm_rx_glb_fc_th_cfg2_u prm_rx_glb_fc_th_cfg2; /* 164 */ + volatile csr_prm_rx_glb_drp_th_cfg_u prm_rx_glb_drp_th_cfg; /* 168 */ + volatile csr_prm_rx_pg0_rsvd_cfg_u prm_rx_pg0_rsvd_cfg; /* 16C */ + volatile csr_prm_rx_pg0_fc_th_cfg0_u prm_rx_pg0_fc_th_cfg0; /* 170 */ + volatile csr_prm_rx_pg0_fc_th_cfg1_u prm_rx_pg0_fc_th_cfg1; /* 174 */ + volatile csr_prm_rx_pg0_fc_th_cfg2_u prm_rx_pg0_fc_th_cfg2; /* 178 */ + volatile csr_prm_rx_pg0_drp_th_cfg_u prm_rx_pg0_drp_th_cfg; /* 17C */ + volatile csr_prm_rx_pg2_rsvd_cfg_u prm_rx_pg2_rsvd_cfg; /* 180 */ + volatile csr_prm_rx_pg2_fc_th_cfg0_u prm_rx_pg2_fc_th_cfg0; /* 184 */ + volatile csr_prm_rx_pg2_fc_th_cfg1_u prm_rx_pg2_fc_th_cfg1; /* 188 */ + volatile csr_prm_rx_pg2_fc_th_cfg2_u prm_rx_pg2_fc_th_cfg2; /* 18C */ + volatile csr_prm_rx_pg2_drp_th_cfg_u prm_rx_pg2_drp_th_cfg; /* 190 */ + volatile csr_prm_rx_pg3_rsvd_cfg_u prm_rx_pg3_rsvd_cfg; /* 194 */ + volatile csr_prm_rx_pg3_fc_th_cfg0_u prm_rx_pg3_fc_th_cfg0; /* 198 */ + volatile csr_prm_rx_pg3_fc_th_cfg1_u prm_rx_pg3_fc_th_cfg1; /* 19C */ + volatile csr_prm_rx_pg3_fc_th_cfg2_u prm_rx_pg3_fc_th_cfg2; /* 1A0 */ + volatile csr_prm_rx_pg3_drp_th_cfg_u prm_rx_pg3_drp_th_cfg; /* 1A4 */ + volatile csr_prm_rx_pg0_cnt_u prm_rx_pg0_cnt; /* 1A8 */ + volatile csr_prm_rx_pg2_cnt_u prm_rx_pg2_cnt; /* 1AC */ + volatile csr_prm_rx_pg3_cnt_u prm_rx_pg3_cnt; /* 1B0 */ + volatile csr_prm_rx_glb_cnt_u prm_rx_glb_cnt; /* 1B4 */ + volatile csr_prm_rx_glb_max_cnt_cfg_u prm_rx_glb_max_cnt_cfg; /* 1B8 */ + volatile csr_prm_rx_ipsu_bp_th_cfg_u prm_rx_ipsu_bp_th_cfg; /* 1BC */ + volatile csr_prm_rx_bmn_wrr_cfg_u prm_rx_bmn_wrr_cfg; /* 1C0 */ + volatile csr_prm_rx_bmy_wrr_cfg_u prm_rx_bmy_wrr_cfg; /* 1C4 */ + volatile csr_prm_rx_bmr_wrr_cfg0_u prm_rx_bmr_wrr_cfg0; /* 1C8 */ + volatile csr_prm_rx_bmr_wrr_cfg1_u prm_rx_bmr_wrr_cfg1; /* 1CC */ + volatile csr_prm_rx_bmg_wrr_cfg_u prm_rx_bmg_wrr_cfg; /* 1D0 */ + volatile csr_prm_rx_cnt_over_flag_u prm_rx_cnt_over_flag; /* 1D4 */ + volatile csr_prm_rx_cnt_under_flag_u prm_rx_cnt_under_flag; /* 1D8 */ + volatile csr_prm_rx_fifo_th_cfg0_u prm_rx_fifo_th_cfg0; /* 1E0 */ + volatile csr_prm_rx_fifo_th_cfg1_u prm_rx_fifo_th_cfg1; /* 1E4 */ + volatile csr_prm_rx_fifo_th_cfg2_u prm_rx_fifo_th_cfg2; /* 1E8 */ + volatile csr_prm_rx_double_daloc_wgt_u prm_rx_double_daloc_wgt; /* 1EC */ + volatile csr_prm_rx_pqm_uload_cfg_u prm_rx_pqm_uload_cfg; /* 1F0 */ + volatile csr_prm_rx_err_src_u prm_rx_err_src; /* 1F4 */ + volatile csr_prmrx_bw_monitor_en_u prmrx_bw_monitor_en; /* 230 */ + volatile csr_prmrx_bw_monitor_win_len_u prmrx_bw_monitor_win_len; /* 234 */ + volatile csr_prmrx_bw_monitor_max_times_cpb_aloc_u prmrx_bw_monitor_max_times_cpb_aloc; /* 238 */ + volatile csr_prmrx_bw_monitor_max_times_cpb_daloc_u prmrx_bw_monitor_max_times_cpb_daloc; /* 23C */ + volatile csr_prmrx_bw_monitor_max_times_cpb_src1_daloc_u prmrx_bw_monitor_max_times_cpb_src1_daloc; /* 240 */ + volatile csr_prmrx_bw_monitor_max_times_cpb_drop_u prmrx_bw_monitor_max_times_cpb_drop; /* 244 */ + volatile csr_prmrx_bw_monitor_max_times_stliq_u prmrx_bw_monitor_max_times_stliq; /* 248 */ + volatile csr_prmrx_bw_monitor_max_times_stfiq_u prmrx_bw_monitor_max_times_stfiq; /* 24C */ + volatile csr_prmrx_bw_monitor_max_times_stlfq_aloc_u prmrx_bw_monitor_max_times_stlfq_aloc; /* 250 */ + volatile csr_prmrx_bw_monitor_max_times_stffq0_aloc_u prmrx_bw_monitor_max_times_stffq0_aloc; /* 254 */ + volatile csr_prmrx_bw_monitor_max_times_stffq1_aloc_u prmrx_bw_monitor_max_times_stffq1_aloc; /* 258 */ + volatile csr_prmrx_bw_monitor_max_times_stlfq_daloc_u prmrx_bw_monitor_max_times_stlfq_daloc; /* 25C */ + volatile csr_prmrx_bw_monitor_max_times_stffq0_daloc_u prmrx_bw_monitor_max_times_stffq0_daloc; /* 260 */ + volatile csr_prmrx_bw_monitor_max_times_stffq1_daloc_u prmrx_bw_monitor_max_times_stffq1_daloc; /* 264 */ + volatile csr_prmrx_bw_monitor_max_times_oq_daloc_u prmrx_bw_monitor_max_times_oq_daloc; /* 268 */ + volatile csr_prmrx_bw_monitor_win_cnt_u prmrx_bw_monitor_win_cnt; /* 26C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_aloc_u prmrx_bw_monitor_over_max_times_cnt_cpb_aloc; /* 270 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_daloc_u prmrx_bw_monitor_over_max_times_cnt_cpb_daloc; /* 274 + */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc_u + prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc; /* 278 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_drop_u prmrx_bw_monitor_over_max_times_cnt_cpb_drop; /* 27C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stliq_u prmrx_bw_monitor_over_max_times_cnt_stliq; /* 280 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stfiq_u prmrx_bw_monitor_over_max_times_cnt_stfiq; /* 284 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc_u prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc; /* 288 + */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc; /* 28C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc; /* 290 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc_u + prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc; /* 294 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc; /* 298 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc; /* 29C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_oq_daloc_u prmrx_bw_monitor_over_max_times_cnt_oq_daloc; /* 2A0 */ +} S_qu_prm_rx_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_rx_csr */ +extern volatile S_qu_prm_rx_csr_REGS_TYPE *gopqu_prm_rx_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_RX_INDRECT_CTRL_indirect_ctrl(unsigned int uindirect_ctrl); +int iSetPRM_RX_INDRECT_TIMEOUT_indirect_timeout(unsigned int uindirect_timeout); +int iSetPRM_RX_INDRECT_DAT0_indirect_dat0(unsigned int uindirect_dat0); +int iSetPRM_RX_INDRECT_DAT1_indirect_dat1(unsigned int uindirect_dat1); +int iSetPRM_RX_INDRECT_DAT2_indirect_dat2(unsigned int uindirect_dat2); +int iSetPRM_RX_INDRECT_DAT3_indirect_dat3(unsigned int uindirect_dat3); +int iSetPRM_RX_CSR_CFG_dyn_csr_req_src(unsigned int udyn_csr_req_src); +int iSetPRM_RX_CSR_CFG_bmr_dyn_csr_req(unsigned int ubmr_dyn_csr_req); +int iSetPRM_RX_CSR_CFG_bmy_dyn_csr_req(unsigned int ubmy_dyn_csr_req); +int iSetPRM_RX_CSR_CFG_bmn_dyn_csr_req(unsigned int ubmn_dyn_csr_req); +int iSetPRM_RX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_on(unsigned int ustf_state_y_fc0_th_on); +int iSetPRM_RX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_dif(unsigned int ustf_state_y_fc0_th_dif); +int iSetPRM_RX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_on(unsigned int ustl_state_y_fc0_th_on); +int iSetPRM_RX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_dif(unsigned int ustl_state_y_fc0_th_dif); +int iSetPRM_RX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_on(unsigned int ustf_state_r_fc0_th_on); +int iSetPRM_RX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_dif(unsigned int ustf_state_r_fc0_th_dif); +int iSetPRM_RX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_on(unsigned int ustl_state_r_fc0_th_on); +int iSetPRM_RX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_dif(unsigned int ustl_state_r_fc0_th_dif); +int iSetPRM_RX_Y_STF_RSVD_CFG_stf_state_y_rsvd(unsigned int ustf_state_y_rsvd); +int iSetPRM_RX_Y_STL_RSVD_CFG_stl_state_y_rsvd(unsigned int ustl_state_y_rsvd); +int iSetPRM_RX_R_STF_RSVD_CFG_stf_state_r_rsvd(unsigned int ustf_state_r_rsvd); +int iSetPRM_RX_R_STL_RSVD_CFG_stl_state_r_rsvd(unsigned int ustl_state_r_rsvd); +int iSetPRM_RX_Y_STF_CNT_stf_state_y_cnt(unsigned int ustf_state_y_cnt); +int iSetPRM_RX_Y_STL_CNT_stl_state_y_cnt(unsigned int ustl_state_y_cnt); +int iSetPRM_RX_R_STF_CNT_stf_state_r_cnt(unsigned int ustf_state_r_cnt); +int iSetPRM_RX_R_STL_CNT_stl_state_r_cnt(unsigned int ustl_state_r_cnt); +int iSetPRM_RX_Y_STF_SH_CNT_stf_state_y_sh_cnt(unsigned int ustf_state_y_sh_cnt); +int iSetPRM_RX_Y_STL_SH_CNT_stl_state_y_sh_cnt(unsigned int ustl_state_y_sh_cnt); +int iSetPRM_RX_R_STF_SH_CNT_stf_state_r_sh_cnt(unsigned int ustf_state_r_sh_cnt); +int iSetPRM_RX_R_STL_SH_CNT_stl_state_r_sh_cnt(unsigned int ustl_state_r_sh_cnt); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_mon_cos(unsigned int ubmy_cfg_mon_cos); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_mon_sp(unsigned int ubmy_cfg_mon_sp); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_mon_srv(unsigned int ubmy_cfg_mon_srv); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_cnt_type(unsigned int ubmy_cfg_cnt_type); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_cnt_en(unsigned int ubmy_cfg_cnt_en); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_sp(unsigned int ubmy_cfg_his_cnt_sp); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_srv(unsigned int ubmy_cfg_his_cnt_srv); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_clr(unsigned int ubmy_cfg_his_cnt_clr); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_en(unsigned int ubmy_cfg_his_cnt_en); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_mon_cos(unsigned int ubmr_cfg_mon_cos); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_mon_sp(unsigned int ubmr_cfg_mon_sp); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_mon_srv(unsigned int ubmr_cfg_mon_srv); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_cnt_type(unsigned int ubmr_cfg_cnt_type); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_cnt_en(unsigned int ubmr_cfg_cnt_en); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_sp(unsigned int ubmr_cfg_his_cnt_sp); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_srv(unsigned int ubmr_cfg_his_cnt_srv); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_clr(unsigned int ubmr_cfg_his_cnt_clr); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_en(unsigned int ubmr_cfg_his_cnt_en); +int iSetPRM_RX_STLFQ_ALOC_bmr_stlfq_aloc_cnt_wr_v(unsigned int ubmr_stlfq_aloc_cnt_wr_v); +int iSetPRM_RX_STFFQ0_ALOC_bmr_stffq0_aloc_cnt_wr_v(unsigned int ubmr_stffq0_aloc_cnt_wr_v); +int iSetPRM_RX_STFFQ1_ALOC_bmr_stffq1_aloc_cnt_wr_v(unsigned int ubmr_stffq1_aloc_cnt_wr_v); +int iSetPRM_RX_STLFQ_DALOC_bmr_stlfq_daloc_cnt_wr_v(unsigned int ubmr_stlfq_daloc_cnt_wr_v); +int iSetPRM_RX_STFFQ0_DALOC_bmr_stffq0_daloc_cnt_wr_v(unsigned int ubmr_stffq0_daloc_cnt_wr_v); +int iSetPRM_RX_STFFQ1_DALOC_bmr_stffq1_daloc_cnt_wr_v(unsigned int ubmr_stffq1_daloc_cnt_wr_v); +int iSetPRM_RX_CPB_DALOC_bmr_cpb_daloc_cnt_wr_v(unsigned int ubmr_cpb_daloc_cnt_wr_v); +int iSetPRM_RX_CPB_DROP_bmr_cpb_drop_cnt_wr_v(unsigned int ubmr_cpb_drop_cnt_wr_v); +int iSetPRM_RX_OQ_DALOC_bmr_oq_daloc_cnt_wr_v(unsigned int ubmr_oq_daloc_cnt_wr_v); +int iSetPRM_RX_STLFQ_ALOC_CNT_bmr_stlfq_aloc_cnt_num_v(unsigned int ubmr_stlfq_aloc_cnt_num_v); +int iSetPRM_RX_STFFQ0_ALOC_CNT_bmr_stffq0_aloc_cnt_num_v(unsigned int ubmr_stffq0_aloc_cnt_num_v); +int iSetPRM_RX_STFFQ1_ALOC_CNT_bmr_stffq1_aloc_cnt_num_v(unsigned int ubmr_stffq1_aloc_cnt_num_v); +int iSetPRM_RX_STLFQ_DALOC_CNT_bmr_stlfq_daloc_cnt_num_v(unsigned int ubmr_stlfq_daloc_cnt_num_v); +int iSetPRM_RX_STFFQ0_DALOC_CNT_bmr_stffq0_daloc_cnt_num_v(unsigned int ubmr_stffq0_daloc_cnt_num_v); +int iSetPRM_RX_STFFQ1_DALOC_CNT_bmr_stffq1_daloc_cnt_num_v(unsigned int ubmr_stffq1_daloc_cnt_num_v); +int iSetPRM_RX_CPB_DALOC_CNT_bmr_cpb_daloc_cnt_num_v(unsigned int ubmr_cpb_daloc_cnt_num_v); +int iSetPRM_RX_CPB_DROP_CNT_bmr_cpb_drop_cnt_num_v(unsigned int ubmr_cpb_drop_cnt_num_v); +int iSetPRM_RX_OQ_DALOC_CNT_bmr_oq_daloc_cnt_num_v(unsigned int ubmr_oq_daloc_cnt_num_v); +int iSetPRM_RX_R_STF_P_HIS_CNT_bmr_stf_his_cnt_port(unsigned int ubmr_stf_his_cnt_port); +int iSetPRM_RX_R_STL_P_HIS_CNT_bmr_stl_his_cnt_port(unsigned int ubmr_stl_his_cnt_port); +int iSetPRM_RX_R_STF_SRV_HIS_CNT_bmr_stf_his_cnt_srv(unsigned int ubmr_stf_his_cnt_srv); +int iSetPRM_RX_R_STL_SRV_HIS_CNT_bmr_stl_his_cnt_srv(unsigned int ubmr_stl_his_cnt_srv); +int iSetPRM_RX_R_STF_SRV_SH_HIS_CNT_bmr_stf_his_cnt_srv_sh(unsigned int ubmr_stf_his_cnt_srv_sh); +int iSetPRM_RX_R_STL_SRV_SH_HIS_CNT_bmr_stl_his_cnt_srv_sh(unsigned int ubmr_stl_his_cnt_srv_sh); +int iSetPRM_RX_R_STF_ST_HIS_CNT_bmr_stf_his_cnt_st(unsigned int ubmr_stf_his_cnt_st); +int iSetPRM_RX_R_STL_ST_HIS_CNT_bmr_stl_his_cnt_st(unsigned int ubmr_stl_his_cnt_st); +int iSetPRM_RX_R_STF_ST_SH_HIS_CNT_bmr_stf_his_cnt_st_sh(unsigned int ubmr_stf_his_cnt_st_sh); +int iSetPRM_RX_R_STL_ST_SH_HIS_CNT_bmr_stl_his_cnt_st_sh(unsigned int ubmr_stl_his_cnt_st_sh); +int iSetPRM_RX_STFIQ_ALOC_bmy_stf_iq_icb_aloc_cnt_wr(unsigned int ubmy_stf_iq_icb_aloc_cnt_wr); +int iSetPRM_RX_STLIQ_ALOC_bmy_stl_iq_icb_aloc_cnt_wr(unsigned int ubmy_stl_iq_icb_aloc_cnt_wr); +int iSetPRM_RX_YDA_DALOC_bmy_yda_daloc_cnt_wr(unsigned int ubmy_yda_daloc_cnt_wr); +int iSetPRM_RX_STFIQ_ALOC_CNT_bmy_stf_iq_icb_aloc_cnt_num(unsigned int ubmy_stf_iq_icb_aloc_cnt_num); +int iSetPRM_RX_STLIQ_ALOC_CNT_bmy_stl_iq_icb_aloc_cnt_num(unsigned int ubmy_stl_iq_icb_aloc_cnt_num); +int iSetPRM_RX_YDA_DALOC_CNT_bmy_yda_daloc_cnt_num(unsigned int ubmy_yda_daloc_cnt_num); +int iSetPRM_RX_Y_STF_P_HIS_CNT_bmy_stf_his_cnt_port(unsigned int ubmy_stf_his_cnt_port); +int iSetPRM_RX_Y_STL_P_HIS_CNT_bmy_stl_his_cnt_port(unsigned int ubmy_stl_his_cnt_port); +int iSetPRM_RX_Y_STF_ST_HIS_CNT_bmy_stf_his_cnt_st(unsigned int ubmy_stf_his_cnt_st); +int iSetPRM_RX_Y_STL_ST_HIS_CNT_bmy_stl_his_cnt_st(unsigned int ubmy_stl_his_cnt_st); +int iSetPRM_RX_Y_STF_ST_SH_HIS_CNT_bmy_stf_his_cnt_st_sh(unsigned int ubmy_stf_his_cnt_st_sh); +int iSetPRM_RX_Y_STL_ST_SH_HIS_CNT_bmy_stl_his_cnt_st_sh(unsigned int ubmy_stl_his_cnt_st_sh); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_mon_cos(unsigned int ubmn_cfg_mon_cos); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_mon_sp(unsigned int ubmn_cfg_mon_sp); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_mon_side(unsigned int ubmn_cfg_mon_side); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_cnt_type(unsigned int ubmn_cfg_cnt_type); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_cnt_en(unsigned int ubmn_cfg_cnt_en); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_cos(unsigned int ubmn_cfg_his_cnt_cos); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_sp(unsigned int ubmn_cfg_his_cnt_sp); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_clr(unsigned int ubmn_cfg_his_cnt_clr); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_en(unsigned int ubmn_cfg_his_cnt_en); +int iSetPRM_RX_CPB_ALOC_bmn_cpb_aloc_cnt_wr(unsigned int ubmn_cpb_aloc_cnt_wr); +int iSetPRM_RX_GRQ_ALOC_bmn_grq_aloc_cnt_wr(unsigned int ubmn_grq_aloc_cnt_wr); +int iSetPRM_RX_GRQ_DALOC_bmn_grq_daloc_cnt_wr(unsigned int ubmn_grq_daloc_cnt_wr); +int iSetPRM_RX_CPB_ALOC_CNT_bmn_cpb_aloc_cnt_num(unsigned int ubmn_cpb_aloc_cnt_num); +int iSetPRM_RX_GRQ_ALOC_CNT_bmn_grq_aloc_cnt_num(unsigned int ubmn_grq_aloc_cnt_num); +int iSetPRM_RX_GRQ_DALOC_CNT_bmn_grq_daloc_cnt_num(unsigned int ubmn_grq_daloc_cnt_num); +int iSetPRM_RX_N_COS_HIS_CNT_bmn_his_cnt_cos(unsigned int ubmn_his_cnt_cos); +int iSetPRM_RX_N_P_HIS_CNT_bmn_his_cnt_port(unsigned int ubmn_his_cnt_port); +int iSetPRM_RX_N_P_SH_HIS_CNT_bmn_his_sh_cnt_port(unsigned int ubmn_his_sh_cnt_port); +int iSetPRM_RX_N_SRV_HIS_CNT_bmn_his_cnt_srv(unsigned int ubmn_his_cnt_srv); +int iSetPRM_RX_N_SRV_SH_HIS_CNT_bmn_his_sh_cnt_srv(unsigned int ubmn_his_sh_cnt_srv); +int iSetPRM_RX_GLB_RSVD_CFG_glb_rsvd_th(unsigned int uglb_rsvd_th); +int iSetPRM_RX_GLB_FC_TH_CFG0_glb_fc0_th_on(unsigned int uglb_fc0_th_on); +int iSetPRM_RX_GLB_FC_TH_CFG0_glb_fc0_th_dif(unsigned int uglb_fc0_th_dif); +int iSetPRM_RX_GLB_FC_TH_CFG1_glb_fc1_th_on(unsigned int uglb_fc1_th_on); +int iSetPRM_RX_GLB_FC_TH_CFG1_glb_fc1_th_dif(unsigned int uglb_fc1_th_dif); +int iSetPRM_RX_GLB_FC_TH_CFG2_glb_fc2_th_on(unsigned int uglb_fc2_th_on); +int iSetPRM_RX_GLB_FC_TH_CFG2_glb_fc2_th_dif(unsigned int uglb_fc2_th_dif); +int iSetPRM_RX_GLB_DRP_TH_CFG_glb_drp_th_on(unsigned int uglb_drp_th_on); +int iSetPRM_RX_GLB_DRP_TH_CFG_glb_drp_th_dif(unsigned int uglb_drp_th_dif); +int iSetPRM_RX_PG0_RSVD_CFG_pg0_rsvd_th(unsigned int upg0_rsvd_th); +int iSetPRM_RX_PG0_FC_TH_CFG0_pg0_fc0_th_on(unsigned int upg0_fc0_th_on); +int iSetPRM_RX_PG0_FC_TH_CFG0_pg0_fc0_th_dif(unsigned int upg0_fc0_th_dif); +int iSetPRM_RX_PG0_FC_TH_CFG1_pg0_fc1_th_on(unsigned int upg0_fc1_th_on); +int iSetPRM_RX_PG0_FC_TH_CFG1_pg0_fc1_th_dif(unsigned int upg0_fc1_th_dif); +int iSetPRM_RX_PG0_FC_TH_CFG2_pg0_fc2_th_on(unsigned int upg0_fc2_th_on); +int iSetPRM_RX_PG0_FC_TH_CFG2_pg0_fc2_th_dif(unsigned int upg0_fc2_th_dif); +int iSetPRM_RX_PG0_DRP_TH_CFG_pg0_drp_th_on(unsigned int upg0_drp_th_on); +int iSetPRM_RX_PG0_DRP_TH_CFG_pg0_drp_th_dif(unsigned int upg0_drp_th_dif); +int iSetPRM_RX_PG2_RSVD_CFG_pg2_rsvd_th(unsigned int upg2_rsvd_th); +int iSetPRM_RX_PG2_FC_TH_CFG0_pg2_fc0_th_on(unsigned int upg2_fc0_th_on); +int iSetPRM_RX_PG2_FC_TH_CFG0_pg2_fc0_th_dif(unsigned int upg2_fc0_th_dif); +int iSetPRM_RX_PG2_FC_TH_CFG1_pg2_fc1_th_on(unsigned int upg2_fc1_th_on); +int iSetPRM_RX_PG2_FC_TH_CFG1_pg2_fc1_th_dif(unsigned int upg2_fc1_th_dif); +int iSetPRM_RX_PG2_FC_TH_CFG2_pg2_fc2_th_on(unsigned int upg2_fc2_th_on); +int iSetPRM_RX_PG2_FC_TH_CFG2_pg2_fc2_th_dif(unsigned int upg2_fc2_th_dif); +int iSetPRM_RX_PG2_DRP_TH_CFG_pg2_drp_th_on(unsigned int upg2_drp_th_on); +int iSetPRM_RX_PG2_DRP_TH_CFG_pg2_drp_th_dif(unsigned int upg2_drp_th_dif); +int iSetPRM_RX_PG3_RSVD_CFG_pg3_rsvd_th(unsigned int upg3_rsvd_th); +int iSetPRM_RX_PG3_FC_TH_CFG0_pg3_fc0_th_on(unsigned int upg3_fc0_th_on); +int iSetPRM_RX_PG3_FC_TH_CFG0_pg3_fc0_th_dif(unsigned int upg3_fc0_th_dif); +int iSetPRM_RX_PG3_FC_TH_CFG1_pg3_fc1_th_on(unsigned int upg3_fc1_th_on); +int iSetPRM_RX_PG3_FC_TH_CFG1_pg3_fc1_th_dif(unsigned int upg3_fc1_th_dif); +int iSetPRM_RX_PG3_FC_TH_CFG2_pg3_fc2_th_on(unsigned int upg3_fc2_th_on); +int iSetPRM_RX_PG3_FC_TH_CFG2_pg3_fc2_th_dif(unsigned int upg3_fc2_th_dif); +int iSetPRM_RX_PG3_DRP_TH_CFG_pg3_drp_th_on(unsigned int upg3_drp_th_on); +int iSetPRM_RX_PG3_DRP_TH_CFG_pg3_drp_th_dif(unsigned int upg3_drp_th_dif); +int iSetPRM_RX_PG0_CNT_pg0_curr_sh_cnt_st(unsigned int upg0_curr_sh_cnt_st); +int iSetPRM_RX_PG0_CNT_pg0_curr_cnt_st(unsigned int upg0_curr_cnt_st); +int iSetPRM_RX_PG2_CNT_pg2_curr_sh_cnt_st(unsigned int upg2_curr_sh_cnt_st); +int iSetPRM_RX_PG2_CNT_pg2_curr_cnt_st(unsigned int upg2_curr_cnt_st); +int iSetPRM_RX_PG3_CNT_pg3_curr_sh_cnt_st(unsigned int upg3_curr_sh_cnt_st); +int iSetPRM_RX_PG3_CNT_pg3_curr_cnt_st(unsigned int upg3_curr_cnt_st); +int iSetPRM_RX_GLB_CNT_glb_curr_sh_cnt_st(unsigned int uglb_curr_sh_cnt_st); +int iSetPRM_RX_GLB_CNT_glb_curr_cnt_st(unsigned int uglb_curr_cnt_st); +int iSetPRM_RX_GLB_MAX_CNT_CFG_cfg_glb_max_th(unsigned int ucfg_glb_max_th); +int iSetPRM_RX_GLB_MAX_CNT_CFG_cfg_glb_max_sh(unsigned int ucfg_glb_max_sh); +int iSetPRM_RX_IPSU_BP_TH_CFG_ipsurx_bp_all_th(unsigned int uipsurx_bp_all_th); +int iSetPRM_RX_IPSU_BP_TH_CFG_ipsurx_bp_rand_th(unsigned int uipsurx_bp_rand_th); +int iSetPRM_RX_BMN_WRR_CFG_rx_bmn_wrr_wgt_cfg(unsigned int urx_bmn_wrr_wgt_cfg); +int iSetPRM_RX_BMY_WRR_CFG_rx_bmy_wrr_wgt_cfg(unsigned int urx_bmy_wrr_wgt_cfg); +int iSetPRM_RX_BMR_WRR_CFG0_rx_bmr_wrr_wgt_cfg0(unsigned int urx_bmr_wrr_wgt_cfg0); +int iSetPRM_RX_BMR_WRR_CFG1_rx_bmn_wrr_wgt_cfg1(unsigned int urx_bmn_wrr_wgt_cfg1); +int iSetPRM_RX_BMG_WRR_CFG_rx_bmg_wrr_wgt_cfg(unsigned int urx_bmg_wrr_wgt_cfg); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_cos_n_of(unsigned int umem_cnt_cos_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_p_n_of(unsigned int umem_cnt_p_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_srv_n_of(unsigned int umem_cnt_srv_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_p_n_of(unsigned int umem_sh_cnt_p_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_srv_n_of(unsigned int umem_sh_cnt_srv_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_p_y_of(unsigned int umem_cnt_stf_p_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_srv_y_of(unsigned int umem_cnt_stf_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_y_of(unsigned int umem_sh_cnt_stf_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_p_y_of(unsigned int umem_cnt_stl_p_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_srv_y_of(unsigned int umem_cnt_stl_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_y_of(unsigned int umem_sh_cnt_stl_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_p_r_of(unsigned int umem_cnt_stf_p_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_srv_r_of(unsigned int umem_cnt_stf_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_r_of(unsigned int umem_sh_cnt_stf_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_p_r_of(unsigned int umem_cnt_stl_p_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_srv_r_of(unsigned int umem_cnt_stl_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_r_of(unsigned int umem_sh_cnt_stl_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_glb_cnt_of(unsigned int uglb_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg3_cnt_of(unsigned int upg3_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg2_cnt_of(unsigned int upg2_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg0_cnt_of(unsigned int upg0_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_glb_sh_cnt_of(unsigned int uglb_sh_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg3_sh_cnt_of(unsigned int upg3_sh_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg2_sh_cnt_of(unsigned int upg2_sh_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg0_sh_cnt_of(unsigned int upg0_sh_cnt_of); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_cos_n_uf(unsigned int umem_cnt_cos_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_p_n_uf(unsigned int umem_cnt_p_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_srv_n_uf(unsigned int umem_cnt_srv_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_p_n_uf(unsigned int umem_sh_cnt_p_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_srv_n_uf(unsigned int umem_sh_cnt_srv_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_p_y_uf(unsigned int umem_cnt_stf_p_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_srv_y_uf(unsigned int umem_cnt_stf_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_y_uf(unsigned int umem_sh_cnt_stf_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_p_y_uf(unsigned int umem_cnt_stl_p_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_srv_y_uf(unsigned int umem_cnt_stl_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_y_uf(unsigned int umem_sh_cnt_stl_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_p_r_uf(unsigned int umem_cnt_stf_p_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_srv_r_uf(unsigned int umem_cnt_stf_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_r_uf(unsigned int umem_sh_cnt_stf_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_p_r_uf(unsigned int umem_cnt_stl_p_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_srv_r_uf(unsigned int umem_cnt_stl_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_r_uf(unsigned int umem_sh_cnt_stl_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_glb_cnt_uf(unsigned int uglb_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg3_cnt_uf(unsigned int upg3_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg2_cnt_uf(unsigned int upg2_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg0_cnt_uf(unsigned int upg0_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_glb_sh_cnt_uf(unsigned int uglb_sh_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg3_sh_cnt_uf(unsigned int upg3_sh_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg2_sh_cnt_uf(unsigned int upg2_sh_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg0_sh_cnt_uf(unsigned int upg0_sh_cnt_uf); +int iSetPRM_RX_FIFO_TH_CFG0_stffq1_daloc_n_af_th(unsigned int ustffq1_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stffq1_aloc_n_af_th(unsigned int ustffq1_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stffq0_daloc_n_af_th(unsigned int ustffq0_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stffq0_aloc_n_af_th(unsigned int ustffq0_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stlfq_daloc_n_af_th(unsigned int ustlfq_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stlfq_aloc_n_af_th(unsigned int ustlfq_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG1_stfiq_n_af_th(unsigned int ustfiq_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG1_stliq_n_af_th(unsigned int ustliq_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG1_oq_daloc_n_af_th(unsigned int uoq_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG2_cpb_aloc_n_af_th(unsigned int ucpb_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG2_cpb_daloc_n_af_th(unsigned int ucpb_daloc_n_af_th); +int iSetPRM_RX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg3_wgt_cfg(unsigned int ustf_stl_daloc_pg3_wgt_cfg); +int iSetPRM_RX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg2_wgt_cfg(unsigned int ustf_stl_daloc_pg2_wgt_cfg); +int iSetPRM_RX_PQM_ULOAD_CFG_qu_pqm_underloading_th(unsigned int uqu_pqm_underloading_th); +int iSetPRM_RX_ERR_SRC_cos_uder_src_err(unsigned int ucos_uder_src_err); +int iSetPRM_RX_ERR_SRC_cos_over_src_err(unsigned int ucos_over_src_err); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_aloc_bdmonitor_en(unsigned int ucsr_prmrx_cpb_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_daloc_bdmonitor_en(unsigned int ucsr_prmrx_cpb_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_src1_daloc_bdmonitor_en(unsigned int ucsr_prmrx_cpb_src1_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_drop_bdmonitor_en(unsigned int ucsr_prmrx_cpb_drop_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stliq_bdmonitor_en(unsigned int ucsr_prmrx_stliq_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stfiq_bdmonitor_en(unsigned int ucsr_prmrx_stfiq_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stlfq_aloc_bdmonitor_en(unsigned int ucsr_prmrx_stlfq_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq0_aloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq0_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq1_aloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq1_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stlfq_daloc_bdmonitor_en(unsigned int ucsr_prmrx_stlfq_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq0_daloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq0_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq1_daloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq1_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_oq_daloc_bdmonitor_en(unsigned int ucsr_prmrx_oq_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_WIN_LEN_csr_prmrx_bdmonitro_win_len(unsigned int ucsr_prmrx_bdmonitro_win_len); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_ALOC_csr_prmrx_bdmonitro_max_times_cpb_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_DALOC_csr_prmrx_bdmonitro_max_times_cpb_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_SRC1_DALOC_csr_prmrx_bdmonitro_max_times_cpb_src1_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_src1_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_DROP_csr_prmrx_bdmonitro_max_times_cpb_drop( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_drop); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STLIQ_csr_prmrx_bdmonitro_max_times_stliq( + unsigned int ucsr_prmrx_bdmonitro_max_times_stliq); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFIQ_csr_prmrx_bdmonitro_max_times_stfiq( + unsigned int ucsr_prmrx_bdmonitro_max_times_stfiq); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_csr_prmrx_bdmonitro_max_times_stlfq_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stlfq_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_csr_prmrx_bdmonitro_max_times_stffq0_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq0_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_csr_prmrx_bdmonitro_max_times_stffq1_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq1_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_csr_prmrx_bdmonitro_max_times_stlfq_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stlfq_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_csr_prmrx_bdmonitro_max_times_stffq0_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq0_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_csr_prmrx_bdmonitro_max_times_stffq1_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq1_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_OQ_DALOC_csr_prmrx_bdmonitro_max_times_oq_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_oq_daloc); +int iSetPRMRX_BW_MONITOR_WIN_CNT_prmrx_csr_bdmonitor_win_cnt(unsigned int uprmrx_csr_bdmonitor_win_cnt); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_prmrx_csr_bdmonitor_over_max_cnt_cpb_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_prmrx_csr_bdmonitor_over_max_cnt_cpb_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_SRC1_DALOC_prmrx_csr_bdmonitor_over_max_cnt_cpb_src1_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_src1_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_prmrx_csr_bdmonitor_over_max_cnt_cpb_drop( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_drop); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_prmrx_csr_bdmonitor_over_max_cnt_stliq( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stliq); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_prmrx_csr_bdmonitor_over_max_cnt_stfiq( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stfiq); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_prmrx_csr_bdmonitor_over_max_cnt_stlfq_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stlfq_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq0_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq0_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq1_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq1_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_prmrx_csr_bdmonitor_over_max_cnt_stlfq_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stlfq_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq0_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq0_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq1_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq1_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_prmrx_csr_bdmonitor_over_max_cnt_oq_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_oq_daloc); + + +#endif // PRMRX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_reg_offset.h new file mode 100644 index 000000000..0c069f244 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_reg_offset.h @@ -0,0 +1,258 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmrx_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:59:21 Create file +// ****************************************************************************** + +#ifndef PRMRX_REG_OFFSET_H +#define PRMRX_REG_OFFSET_H + +/* QU_PRM_TOP_CSR Base address of Module's Register */ +#define CSR_QU_PRM_TOP_CSR_BASE (0x7000) + +/* **************************************************************************** */ +/* QU_PRM_TOP_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MEM_CTRL_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x0) /* MEM控制 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x4) /* MQM_BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x8) /* MQM_HOST BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0xC) /* MQM_SOC BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK3_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x10) /* MQM_COS0 BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK4_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x14) /* MQM_COS1 BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_BP_MASK_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x18) /* PRM BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT_VECTOR_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x5C) /* 中断向量 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x60) /* 中断状态 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT_EN_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x64) /* 中断屏蔽 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT0_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x68) /* 中断0的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT1_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x6C) /* 中断1的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT2_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x70) /* 中断2的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT3_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x74) /* 中断3的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_INT4_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x78) /* 中断4的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_INT5_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x7C) /* 中断5的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x100) /* TX FIFO OVER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x104) /* TX FIFO UNDER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x108) /* RX FIFO OVER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST3_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x10C) /* RX FIFO UNDER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_SRC_IN_VIO_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x110) /* 申请src超过定义范围 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x204) /* MQM_BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x208) /* MQM_HOST BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x20C) /* MQM_SOC BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP3_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x210) /* MQM_COS0 BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP3_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x214) /* MQM_COS0 BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MAG_PORT_BP_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x220) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MAG_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x240) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MAG_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x244) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x250) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x254) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x258) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_3_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x25C) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPI_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x260) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPI_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x264) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPI_COS_BP_2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x268) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPB_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x270) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPB_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x274) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPB_COS_BP_2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x278) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_IQ_BP_CFG_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x290) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STL_IQ_BP0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x294) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STL_IQ_BP1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x298) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STF_IQ_BP0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x29C) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STF_IQ_BP1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x2A0) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_1BIT_ECC_ERR_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x2A4) + +/* QU_PRM_RX_CSR Base address of Module's Register */ +#define CSR_QU_PRM_RX_CSR_BASE (0x6000) + +/* **************************************************************************** */ +/* QU_PRM_RX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_CTRL_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x0) /* PRM memory indirect access ctrl register */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_TIMEOUT_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x4) /* PRM indirect access timeout configuration */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT0_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x8) /* PRM indirect access write or read data. */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT1_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC) +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x10) +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT3_REG (CSR_QU_PRM_RX_CSR_BASE + 0x14) +#define CSR_QU_PRM_RX_CSR_PRM_RX_CSR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x30) /* 软件申请配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x34) /* 黄区STF阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x38) /* 黄区STL阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x3C) /* 红区STF阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x40) /* 红区STL阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x44) /* 黄区STF RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x48) /* 黄区STL RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x4C) /* 红区STF RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x50) /* 红区STL RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x54) /* 黄区STF 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x58) /* 黄区STL 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x5C) /* 红区STF 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x60) /* 红区STL 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x64) /* 黄区STF 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x68) /* 黄区STL 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x6C) /* 红区STF 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x70) /* 红区STL 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_MON_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x74) /* 黄区monitor配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_HIS_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x78) /* 黄区最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_MON_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x7C) /* 红区monitor配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_HIS_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x80) /* 红区最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x84) /* STLFQ ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x88) /* STFFQ0 ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x8C) /* STFFQ1 ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x90) /* STLFQ DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x94) /* STFFQ0 DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x98) /* STFFQ1 DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x9C) /* CPB DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DROP_REG (CSR_QU_PRM_RX_CSR_BASE + 0xA0) /* CPB DROP 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_OQ_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xA4) /* OQ DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xA8) /* STLFQ ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xAC) /* STFFQ0 ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xB0) /* STFFQ1 ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xB4) /* STLFQ DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xB8) /* STFFQ0 DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xBC) /* STFFQ1 DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC0) /* CPB DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DROP_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC4) /* CPB DROP CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_OQ_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC8) /* OQ DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xCC) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xD0) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_SRV_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xD4) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_SRV_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xD8) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xDC) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xE0) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xE4) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xE8) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xEC) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xF0) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFIQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xF4) /* STFIQ ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLIQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xF8) /* STLIQ ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_YDA_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xFC) /* YDA DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFIQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x100) /* STFIQ ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLIQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x104) /* STLIQ ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_YDA_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x108) /* YDA DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x10C) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x110) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x114) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x118) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x11C) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x120) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_G_MON_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x124) /* 绿区monitor配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_G_HIS_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x128) /* 绿区最大值记录配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x12C) /* PRM_RX_CPB_ALOC */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x130) /* PRM_RX_GRQ_ALOC */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x134) /* PRM_RX_GRQ_DALOC */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x138) /* PRM_RX_CPB_ALOC_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x13C) /* PRM_RX_GRQ_ALOC_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x140) /* PRM_RX_GRQ_DALOC_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_COS_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x144) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x148) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_P_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x14C) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_SRV_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x150) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x154) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x158) /* GLB RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x15C) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x160) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x164) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x168) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x16C) /* PG0 RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x170) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x174) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x178) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x17C) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x180) /* PG2 RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x184) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x188) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x18C) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x190) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x194) /* PG3 RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x198) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x19C) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1A0) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1A4) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1A8) /* PG0资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1AC) /* PG2黄区资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1B0) /* PG3红区资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1B4) /* PG0资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_MAX_CNT_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1B8) +#define CSR_QU_PRM_RX_CSR_PRM_RX_IPSU_BP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1BC) /* IPSU 反压阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMN_WRR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1C0) /* RX绿区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMY_WRR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1C4) /* RX黄区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMR_WRR_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1C8) /* RX红区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMR_WRR_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1CC) /* RX红区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMG_WRR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1D0) /* RX GLB 区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CNT_OVER_FLAG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1D4) /* CNT上溢出标志 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CNT_UNDER_FLAG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1D8) /* CNT下溢出标志 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_FIFO_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1E0) /* RX fifo阈值配置0 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_FIFO_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1E4) /* RX fifo阈值配置1 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_FIFO_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1E8) /* RX fifo阈值配置2 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_DOUBLE_DALOC_WGT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1EC) /* RX双黄/红区释放权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PQM_ULOAD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1F0) /* PG0轻负载阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_ERR_SRC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1F4) /* RX溢出DFX */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_EN_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x230) /* PRMRX侧的入口FIFO带宽监测使能配置 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_WIN_LEN_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x234) /* PRMRX侧的入口FIFO带宽监测，窗口长度配置 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x238) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x23C) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_SRC1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x240) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_DROP_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x244) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STLIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x248) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x24C) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x250) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x254) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x258) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x25C) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x260) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x264) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_OQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x268) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_WIN_CNT_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x26C) /* PRMRX侧的入口FIFO带宽监测，窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x270) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x274) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_SRC1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x278) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x27C) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x280) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x284) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x288) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x28C) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x290) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x294) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x298) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x29C) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x2A0) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ + +#endif // PRMRX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_c_union_define.h new file mode 100644 index 000000000..cc8ef9a5b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_c_union_define.h @@ -0,0 +1,2758 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmtx_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:01:17 Create file +// ****************************************************************************** + +#ifndef PRMTX_C_UNION_DEFINE_H +#define PRMTX_C_UNION_DEFINE_H + +/* Define the union csr_prm_tx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_ctrl_u; + +/* Define the union csr_prm_tx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_timeout_u; + +/* Define the union csr_prm_tx_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat0_u; + +/* Define the union csr_prm_tx_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat1_u; + +/* Define the union csr_prm_tx_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat2_u; + +/* Define the union csr_prm_tx_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat3_u; + +/* Define the union csr_prm_tx_indrect_dat4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat4_u; + +/* Define the union csr_prm_tx_indrect_dat5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat5_u; + +/* Define the union csr_prm_tx_indrect_dat6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat6_u; + +/* Define the union csr_prm_tx_csr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dyn_csr_req_src : 12; /* [11:0] */ + u32 bmr_dyn_csr_req : 1; /* [12] */ + u32 bmy_dyn_csr_req : 1; /* [13] */ + u32 bmh_dyn_csr_req : 1; /* [14] */ + u32 rsv_0 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_csr_cfg_u; + +/* Define the union csr_prm_tx_y_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_fc_th_cfg_u; + +/* Define the union csr_prm_tx_y_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_fc_th_cfg_u; + +/* Define the union csr_prm_tx_r_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_fc_th_cfg_u; + +/* Define the union csr_prm_tx_r_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_fc_th_cfg_u; + +/* Define the union csr_prm_tx_y_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_rsvd_cfg_u; + +/* Define the union csr_prm_tx_y_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_rsvd_cfg_u; + +/* Define the union csr_prm_tx_r_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_rsvd_cfg_u; + +/* Define the union csr_prm_tx_r_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_rsvd_cfg_u; + +/* Define the union csr_prm_tx_y_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_cnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_cnt_u; + +/* Define the union csr_prm_tx_y_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_cnt : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_cnt_u; + +/* Define the union csr_prm_tx_r_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_cnt : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_cnt_u; + +/* Define the union csr_prm_tx_r_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_cnt : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_cnt_u; + +/* Define the union csr_prm_tx_y_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_sh_cnt_u; + +/* Define the union csr_prm_tx_y_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_sh_cnt_u; + +/* Define the union csr_prm_tx_r_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_sh_cnt_u; + +/* Define the union csr_prm_tx_r_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_sh_cnt_u; + +/* Define the union csr_prm_tx_y_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_17 : 1; /* [3] */ + u32 bmy_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_18 : 3; /* [11:9] */ + u32 bmy_cfg_mon_srv : 1; /* [12] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 bmy_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_20 : 2; /* [19:18] */ + u32 bmy_cfg_cnt_en : 1; /* [20] */ + u32 rsv_21 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_mon_cfg_u; + +/* Define the union csr_prm_tx_y_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_22 : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 bmy_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_24 : 3; /* [11:9] */ + u32 bmy_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_25 : 3; /* [15:13] */ + u32 bmy_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_26 : 3; /* [19:17] */ + u32 bmy_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_his_cfg_u; + +/* Define the union csr_prm_tx_r_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_28 : 1; /* [3] */ + u32 bmr_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_29 : 3; /* [11:9] */ + u32 bmr_cfg_mon_srv : 1; /* [12] */ + u32 rsv_30 : 3; /* [15:13] */ + u32 bmr_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_31 : 2; /* [19:18] */ + u32 bmr_cfg_cnt_en : 1; /* [20] */ + u32 rsv_32 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_mon_cfg_u; + +/* Define the union csr_prm_tx_r_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 3; /* [2:0] */ + u32 rsv_34 : 1; /* [3] */ + u32 bmr_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_35 : 3; /* [11:9] */ + u32 bmr_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_36 : 3; /* [15:13] */ + u32 bmr_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_37 : 3; /* [19:17] */ + u32 bmr_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_38 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_his_cfg_u; + +/* Define the union csr_prm_tx_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_aloc_u; + +/* Define the union csr_prm_tx_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_aloc_u; + +/* Define the union csr_prm_tx_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_aloc_u; + +/* Define the union csr_prm_tx_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_daloc_u; + +/* Define the union csr_prm_tx_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_daloc_u; + +/* Define the union csr_prm_tx_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_daloc_u; + +/* Define the union csr_prm_tx_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_daloc_u; + +/* Define the union csr_prm_tx_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_drop_u; + +/* Define the union csr_prm_tx_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_daloc_u; + +/* Define the union csr_prm_tx_stlfq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_aloc_cnt_u; + +/* Define the union csr_prm_tx_stffq0_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_aloc_cnt_u; + +/* Define the union csr_prm_tx_stffq1_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_aloc_cnt_u; + +/* Define the union csr_prm_tx_stlfq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_daloc_cnt_u; + +/* Define the union csr_prm_tx_stffq0_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_daloc_cnt_u; + +/* Define the union csr_prm_tx_stffq1_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_daloc_cnt_u; + +/* Define the union csr_prm_tx_cpb_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_daloc_cnt_u; + +/* Define the union csr_prm_tx_cpb_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_drop_cnt_u; + +/* Define the union csr_prm_tx_oq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_daloc_cnt_u; + +/* Define the union csr_prm_tx_r_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_p_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_p_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_srv_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_srv_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_srv_sh_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_srv_sh_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_45 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_st_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_46 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_st_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_stfiq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stfiq_aloc_u; + +/* Define the union csr_prm_tx_stliq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stliq_aloc_u; + +/* Define the union csr_prm_tx_yda_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_yda_daloc_u; + +/* Define the union csr_prm_tx_stfiq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stfiq_aloc_cnt_u; + +/* Define the union csr_prm_tx_stliq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stliq_aloc_cnt_u; + +/* Define the union csr_prm_tx_yda_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_yda_daloc_cnt_u; + +/* Define the union csr_prm_tx_y_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_p_his_cnt_u; + +/* Define the union csr_prm_tx_y_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_50 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_p_his_cnt_u; + +/* Define the union csr_prm_tx_y_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_st_his_cnt_u; + +/* Define the union csr_prm_tx_y_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_st_his_cnt_u; + +/* Define the union csr_prm_tx_y_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_y_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_g_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_55 : 1; /* [3] */ + u32 bmh_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_56 : 3; /* [11:9] */ + u32 bmh_cfg_mon_side : 1; /* [12] */ + u32 rsv_57 : 3; /* [15:13] */ + u32 bmh_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_58 : 2; /* [19:18] */ + u32 bmh_cfg_cnt_en : 1; /* [20] */ + u32 rsv_59 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_g_mon_cfg_u; + +/* Define the union csr_prm_tx_g_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cfg_his_cnt_cos : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 bmh_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_61 : 3; /* [11:9] */ + u32 rsv_62 : 1; /* [12] */ + u32 rsv_63 : 3; /* [15:13] */ + u32 bmh_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_64 : 3; /* [19:17] */ + u32 bmh_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_65 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_g_his_cfg_u; + +/* Define the union csr_prm_tx_cpi_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpi_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpi_aloc_u; + +/* Define the union csr_prm_tx_grq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_aloc_u; + +/* Define the union csr_prm_tx_grq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_daloc_u; + +/* Define the union csr_prm_tx_cpi_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpi_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpi_aloc_cnt_u; + +/* Define the union csr_prm_tx_grq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_aloc_cnt_u; + +/* Define the union csr_prm_tx_grq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_daloc_cnt_u; + +/* Define the union csr_prm_tx_h_cos_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_cnt_cos : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_cos_his_cnt_u; + +/* Define the union csr_prm_tx_h_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_cnt_port : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_p_his_cnt_u; + +/* Define the union csr_prm_tx_h_p_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_sh_cnt_port : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_p_sh_his_cnt_u; + +/* Define the union csr_prm_tx_h_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_srv_his_cnt_u; + +/* Define the union csr_prm_tx_h_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_sh_cnt_srv : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_srv_sh_his_cnt_u; + +/* Define the union csr_prm_tx_glb_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_rsvd_th : 16; /* [15:0] */ + u32 rsv_71 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_rsvd_cfg_u; + +/* Define the union csr_prm_tx_glb_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc0_th_on : 16; /* [15:0] */ + u32 glb_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_glb_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc1_th_on : 16; /* [15:0] */ + u32 glb_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_73 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_glb_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc2_th_on : 16; /* [15:0] */ + u32 glb_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_74 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_glb_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_drp_th_on : 16; /* [15:0] */ + u32 glb_drp_th_dif : 8; /* [23:16] */ + u32 rsv_75 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg1_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_rsvd_th : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_rsvd_cfg_u; + +/* Define the union csr_prm_tx_pg1_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_fc0_th_on : 16; /* [15:0] */ + u32 pg1_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_77 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_pg1_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_fc1_th_on : 16; /* [15:0] */ + u32 pg1_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_78 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_pg1_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_fc2_th_on : 16; /* [15:0] */ + u32 pg1_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_79 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_pg1_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_drp_th_on : 16; /* [15:0] */ + u32 pg1_drp_th_dif : 8; /* [23:16] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg2_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_rsvd_th : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_rsvd_cfg_u; + +/* Define the union csr_prm_tx_pg2_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc0_th_on : 16; /* [15:0] */ + u32 pg2_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_82 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_pg2_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc1_th_on : 16; /* [15:0] */ + u32 pg2_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_83 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_pg2_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc2_th_on : 16; /* [15:0] */ + u32 pg2_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_84 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_pg2_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_drp_th_on : 16; /* [15:0] */ + u32 pg2_drp_th_dif : 8; /* [23:16] */ + u32 rsv_85 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg3_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_rsvd_th : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_rsvd_cfg_u; + +/* Define the union csr_prm_tx_pg3_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc0_th_on : 16; /* [15:0] */ + u32 pg3_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_87 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_pg3_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc1_th_on : 16; /* [15:0] */ + u32 pg3_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_pg3_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc2_th_on : 16; /* [15:0] */ + u32 pg3_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_pg3_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_drp_th_on : 16; /* [15:0] */ + u32 pg3_drp_th_dif : 8; /* [23:16] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg1_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_cnt_u; + +/* Define the union csr_prm_tx_pg2_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg2_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_cnt_u; + +/* Define the union csr_prm_tx_pg3_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg3_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_cnt_u; + +/* Define the union csr_prm_tx_glb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_curr_sh_cnt_st : 16; /* [15:0] */ + u32 glb_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_cnt_u; + +/* Define the union csr_prm_tx_glb_max_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_glb_max_th : 16; /* [15:0] */ + u32 cfg_glb_max_sh : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_max_cnt_cfg_u; + +/* Define the union csr_prm_tx_cpi_req_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cpi_wg_period : 14; /* [13:0] */ + u32 cfg_cpi_toke_unit : 10; /* [23:14] */ + u32 msk_sel_cpi_req : 1; /* [24] */ + u32 rsv_91 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpi_req_cfg_u; + +/* Define the union csr_prm_tx_mqm_uload_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_mqm_underloading_th : 16; /* [15:0] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_mqm_uload_cfg_u; + +/* Define the union csr_prm_tx_bmh_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmh_wrr_wgt_cfg : 16; /* [15:0] */ + u32 rsv_93 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmh_wrr_cfg_u; + +/* Define the union csr_prm_tx_bmy_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmy_wrr_wgt_cfg : 12; /* [11:0] */ + u32 rsv_94 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmy_wrr_cfg_u; + +/* Define the union csr_prm_tx_bmr_wrr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmr_wrr_wgt_cfg0 : 24; /* [23:0] */ + u32 rsv_95 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmr_wrr_cfg0_u; + +/* Define the union csr_prm_tx_bmr_wrr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmr_wrr_wgt_cfg1 : 12; /* [11:0] */ + u32 rsv_96 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmr_wrr_cfg1_u; + +/* Define the union csr_prm_tx_bmg_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmg_wrr_wgt_cfg : 16; /* [15:0] */ + u32 rsv_97 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmg_wrr_cfg_u; + +/* Define the union csr_prm_tx_cnt_over_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_h_of : 1; /* [0] */ + u32 mem_cnt_p_h_of : 1; /* [1] */ + u32 mem_cnt_srv_h_of : 1; /* [2] */ + u32 mem_sh_cnt_p_h_of : 1; /* [3] */ + u32 mem_sh_cnt_srv_h_of : 1; /* [4] */ + u32 mem_cnt_stf_p_y_of : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_of : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_of : 1; /* [7] */ + u32 mem_cnt_stl_p_y_of : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_of : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_of : 1; /* [10] */ + u32 mem_cnt_stf_p_r_of : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_of : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_of : 1; /* [13] */ + u32 mem_cnt_stl_p_r_of : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_of : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_of : 1; /* [16] */ + u32 glb_cnt_of : 1; /* [17] */ + u32 pg3_cnt_of : 1; /* [18] */ + u32 pg2_cnt_of : 1; /* [19] */ + u32 pg1_cnt_of : 1; /* [20] */ + u32 glb_sh_cnt_of : 1; /* [21] */ + u32 pg3_sh_cnt_of : 1; /* [22] */ + u32 pg2_sh_cnt_of : 1; /* [23] */ + u32 pg1_sh_cnt_of : 1; /* [24] */ + u32 rsv_98 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cnt_over_flag_u; + +/* Define the union csr_prm_tx_cnt_under_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_h_uf : 1; /* [0] */ + u32 mem_cnt_p_h_uf : 1; /* [1] */ + u32 mem_cnt_srv_h_uf : 1; /* [2] */ + u32 mem_sh_cnt_p_h_uf : 1; /* [3] */ + u32 mem_sh_cnt_srv_h_uf : 1; /* [4] */ + u32 mem_cnt_stf_p_y_uf : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_uf : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_uf : 1; /* [7] */ + u32 mem_cnt_stl_p_y_uf : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_uf : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_uf : 1; /* [10] */ + u32 mem_cnt_stf_p_r_uf : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_uf : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_uf : 1; /* [13] */ + u32 mem_cnt_stl_p_r_uf : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_uf : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_uf : 1; /* [16] */ + u32 glb_cnt_uf : 1; /* [17] */ + u32 pg3_cnt_uf : 1; /* [18] */ + u32 pg2_cnt_uf : 1; /* [19] */ + u32 pg1_cnt_uf : 1; /* [20] */ + u32 glb_sh_cnt_uf : 1; /* [21] */ + u32 pg3_sh_cnt_uf : 1; /* [22] */ + u32 pg2_sh_cnt_uf : 1; /* [23] */ + u32 pg1_sh_cnt_uf : 1; /* [24] */ + u32 rsv_99 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cnt_under_flag_u; + +/* Define the union csr_prm_tx_fifo_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stffq1_daloc_n_af_th : 5; /* [4:0] */ + u32 stffq1_aloc_n_af_th : 5; /* [9:5] */ + u32 stffq0_daloc_n_af_th : 5; /* [14:10] */ + u32 stffq0_aloc_n_af_th : 5; /* [19:15] */ + u32 stlfq_daloc_n_af_th : 5; /* [24:20] */ + u32 stlfq_aloc_n_af_th : 5; /* [29:25] */ + u32 rsv_100 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_fifo_th_cfg0_u; + +/* Define the union csr_prm_tx_fifo_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_n_af_th : 5; /* [4:0] */ + u32 stliq_n_af_th : 5; /* [9:5] */ + u32 oq_daloc_n_af_th : 5; /* [14:10] */ + u32 oq_aloc_n_af_th : 5; /* [19:15] */ + u32 rsv_101 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_fifo_th_cfg1_u; + +/* Define the union csr_prm_tx_fifo_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_aloc_n_af_th : 6; /* [5:0] */ + u32 rsv_102 : 2; /* [7:6] */ + u32 cpb_daloc_n_af_th : 6; /* [13:8] */ + u32 rsv_103 : 2; /* [15:14] */ + u32 cpi_aloc_n_af_th : 7; /* [22:16] */ + u32 rsv_104 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_fifo_th_cfg2_u; + +/* Define the union csr_prm_tx_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_aloc_u; + +/* Define the union csr_prm_tx_cpb_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_aloc_cnt_u; + +/* Define the union csr_prm_tx_oq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_oq_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_aloc_u; + +/* Define the union csr_prm_tx_oq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_oq_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_aloc_cnt_u; + +/* Define the union csr_prm_tx_double_daloc_wgt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_stl_daloc_pg3_wgt_cfg : 8; /* [7:0] */ + u32 stf_stl_daloc_pg2_wgt_cfg : 8; /* [15:8] */ + u32 rsv_105 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_double_daloc_wgt_u; + +/* Define the union csr_prm_tx_err_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_uder_src_err : 9; /* [8:0] */ + u32 cos_over_src_err : 9; /* [17:9] */ + u32 rsv_106 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_err_src_u; + +/* Define the union csr_prmtx_bw_monitor_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_cpb_aloc_bdmonitor_en : 1; /* [0] */ + u32 csr_prmtx_cpi_aloc_bdmonitor_en : 1; /* [1] */ + u32 csr_prmtx_oq_aloc_bdmonitor_en : 1; /* [2] */ + u32 csr_prmtx_cpb_daloc_bdmonitor_en : 1; /* [3] */ + u32 csr_prmtx_cpb_drop_bdmonitor_en : 1; /* [4] */ + u32 csr_prmtx_stliq_bdmonitor_en : 1; /* [5] */ + u32 csr_prmtx_stfiq_bdmonitor_en : 1; /* [6] */ + u32 csr_prmtx_stlfq_aloc_bdmonitor_en : 1; /* [7] */ + u32 csr_prmtx_stffq0_aloc_bdmonitor_en : 1; /* [8] */ + u32 csr_prmtx_stffq1_aloc_bdmonitor_en : 1; /* [9] */ + u32 csr_prmtx_stlfq_daloc_bdmonitor_en : 1; /* [10] */ + u32 csr_prmtx_stffq0_daloc_bdmonitor_en : 1; /* [11] */ + u32 csr_prmtx_stffq1_daloc_bdmonitor_en : 1; /* [12] */ + u32 csr_prmtx_oq_daloc_bdmonitor_en : 1; /* [13] */ + u32 rsv_107 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_en_u; + +/* Define the union csr_prmtx_bw_monitor_win_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_win_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_win_len_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpb_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpi_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpi_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpi_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_oq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_oq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_oq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpb_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpb_drop_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stliq_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stfiq_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stlfq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq0_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq1_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stlfq_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq0_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq1_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_oq_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_win_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_win_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_win_cnt_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpb_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpi_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpi_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpi_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_oq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_oq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_oq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpb_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpb_drop_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stliq_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stfiq_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_oq_daloc_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_tx_indrect_ctrl_u prm_tx_indrect_ctrl; /* 0 */ + volatile csr_prm_tx_indrect_timeout_u prm_tx_indrect_timeout; /* 4 */ + volatile csr_prm_tx_indrect_dat0_u prm_tx_indrect_dat0; /* 8 */ + volatile csr_prm_tx_indrect_dat1_u prm_tx_indrect_dat1; /* C */ + volatile csr_prm_tx_indrect_dat2_u prm_tx_indrect_dat2; /* 10 */ + volatile csr_prm_tx_indrect_dat3_u prm_tx_indrect_dat3; /* 14 */ + volatile csr_prm_tx_indrect_dat4_u prm_tx_indrect_dat4; /* 18 */ + volatile csr_prm_tx_indrect_dat5_u prm_tx_indrect_dat5; /* 1C */ + volatile csr_prm_tx_indrect_dat6_u prm_tx_indrect_dat6; /* 20 */ + volatile csr_prm_tx_csr_cfg_u prm_tx_csr_cfg; /* 30 */ + volatile csr_prm_tx_y_stf_fc_th_cfg_u prm_tx_y_stf_fc_th_cfg; /* 34 */ + volatile csr_prm_tx_y_stl_fc_th_cfg_u prm_tx_y_stl_fc_th_cfg; /* 38 */ + volatile csr_prm_tx_r_stf_fc_th_cfg_u prm_tx_r_stf_fc_th_cfg; /* 3C */ + volatile csr_prm_tx_r_stl_fc_th_cfg_u prm_tx_r_stl_fc_th_cfg; /* 40 */ + volatile csr_prm_tx_y_stf_rsvd_cfg_u prm_tx_y_stf_rsvd_cfg; /* 44 */ + volatile csr_prm_tx_y_stl_rsvd_cfg_u prm_tx_y_stl_rsvd_cfg; /* 48 */ + volatile csr_prm_tx_r_stf_rsvd_cfg_u prm_tx_r_stf_rsvd_cfg; /* 4C */ + volatile csr_prm_tx_r_stl_rsvd_cfg_u prm_tx_r_stl_rsvd_cfg; /* 50 */ + volatile csr_prm_tx_y_stf_cnt_u prm_tx_y_stf_cnt; /* 54 */ + volatile csr_prm_tx_y_stl_cnt_u prm_tx_y_stl_cnt; /* 58 */ + volatile csr_prm_tx_r_stf_cnt_u prm_tx_r_stf_cnt; /* 5C */ + volatile csr_prm_tx_r_stl_cnt_u prm_tx_r_stl_cnt; /* 60 */ + volatile csr_prm_tx_y_stf_sh_cnt_u prm_tx_y_stf_sh_cnt; /* 64 */ + volatile csr_prm_tx_y_stl_sh_cnt_u prm_tx_y_stl_sh_cnt; /* 68 */ + volatile csr_prm_tx_r_stf_sh_cnt_u prm_tx_r_stf_sh_cnt; /* 6C */ + volatile csr_prm_tx_r_stl_sh_cnt_u prm_tx_r_stl_sh_cnt; /* 70 */ + volatile csr_prm_tx_y_mon_cfg_u prm_tx_y_mon_cfg; /* 74 */ + volatile csr_prm_tx_y_his_cfg_u prm_tx_y_his_cfg; /* 78 */ + volatile csr_prm_tx_r_mon_cfg_u prm_tx_r_mon_cfg; /* 7C */ + volatile csr_prm_tx_r_his_cfg_u prm_tx_r_his_cfg; /* 80 */ + volatile csr_prm_tx_stlfq_aloc_u prm_tx_stlfq_aloc; /* 84 */ + volatile csr_prm_tx_stffq0_aloc_u prm_tx_stffq0_aloc; /* 88 */ + volatile csr_prm_tx_stffq1_aloc_u prm_tx_stffq1_aloc; /* 8C */ + volatile csr_prm_tx_stlfq_daloc_u prm_tx_stlfq_daloc; /* 90 */ + volatile csr_prm_tx_stffq0_daloc_u prm_tx_stffq0_daloc; /* 94 */ + volatile csr_prm_tx_stffq1_daloc_u prm_tx_stffq1_daloc; /* 98 */ + volatile csr_prm_tx_cpb_daloc_u prm_tx_cpb_daloc; /* 9C */ + volatile csr_prm_tx_cpb_drop_u prm_tx_cpb_drop; /* A0 */ + volatile csr_prm_tx_oq_daloc_u prm_tx_oq_daloc; /* A4 */ + volatile csr_prm_tx_stlfq_aloc_cnt_u prm_tx_stlfq_aloc_cnt; /* A8 */ + volatile csr_prm_tx_stffq0_aloc_cnt_u prm_tx_stffq0_aloc_cnt; /* AC */ + volatile csr_prm_tx_stffq1_aloc_cnt_u prm_tx_stffq1_aloc_cnt; /* B0 */ + volatile csr_prm_tx_stlfq_daloc_cnt_u prm_tx_stlfq_daloc_cnt; /* B4 */ + volatile csr_prm_tx_stffq0_daloc_cnt_u prm_tx_stffq0_daloc_cnt; /* B8 */ + volatile csr_prm_tx_stffq1_daloc_cnt_u prm_tx_stffq1_daloc_cnt; /* BC */ + volatile csr_prm_tx_cpb_daloc_cnt_u prm_tx_cpb_daloc_cnt; /* C0 */ + volatile csr_prm_tx_cpb_drop_cnt_u prm_tx_cpb_drop_cnt; /* C4 */ + volatile csr_prm_tx_oq_daloc_cnt_u prm_tx_oq_daloc_cnt; /* C8 */ + volatile csr_prm_tx_r_stf_p_his_cnt_u prm_tx_r_stf_p_his_cnt; /* CC */ + volatile csr_prm_tx_r_stl_p_his_cnt_u prm_tx_r_stl_p_his_cnt; /* D0 */ + volatile csr_prm_tx_r_stf_srv_his_cnt_u prm_tx_r_stf_srv_his_cnt; /* D4 */ + volatile csr_prm_tx_r_stl_srv_his_cnt_u prm_tx_r_stl_srv_his_cnt; /* D8 */ + volatile csr_prm_tx_r_stf_srv_sh_his_cnt_u prm_tx_r_stf_srv_sh_his_cnt; /* DC */ + volatile csr_prm_tx_r_stl_srv_sh_his_cnt_u prm_tx_r_stl_srv_sh_his_cnt; /* E0 */ + volatile csr_prm_tx_r_stf_st_his_cnt_u prm_tx_r_stf_st_his_cnt; /* E4 */ + volatile csr_prm_tx_r_stl_st_his_cnt_u prm_tx_r_stl_st_his_cnt; /* E8 */ + volatile csr_prm_tx_r_stf_st_sh_his_cnt_u prm_tx_r_stf_st_sh_his_cnt; /* EC */ + volatile csr_prm_tx_r_stl_st_sh_his_cnt_u prm_tx_r_stl_st_sh_his_cnt; /* F0 */ + volatile csr_prm_tx_stfiq_aloc_u prm_tx_stfiq_aloc; /* F4 */ + volatile csr_prm_tx_stliq_aloc_u prm_tx_stliq_aloc; /* F8 */ + volatile csr_prm_tx_yda_daloc_u prm_tx_yda_daloc; /* FC */ + volatile csr_prm_tx_stfiq_aloc_cnt_u prm_tx_stfiq_aloc_cnt; /* 100 */ + volatile csr_prm_tx_stliq_aloc_cnt_u prm_tx_stliq_aloc_cnt; /* 104 */ + volatile csr_prm_tx_yda_daloc_cnt_u prm_tx_yda_daloc_cnt; /* 108 */ + volatile csr_prm_tx_y_stf_p_his_cnt_u prm_tx_y_stf_p_his_cnt; /* 10C */ + volatile csr_prm_tx_y_stl_p_his_cnt_u prm_tx_y_stl_p_his_cnt; /* 110 */ + volatile csr_prm_tx_y_stf_st_his_cnt_u prm_tx_y_stf_st_his_cnt; /* 114 */ + volatile csr_prm_tx_y_stl_st_his_cnt_u prm_tx_y_stl_st_his_cnt; /* 118 */ + volatile csr_prm_tx_y_stf_st_sh_his_cnt_u prm_tx_y_stf_st_sh_his_cnt; /* 11C */ + volatile csr_prm_tx_y_stl_st_sh_his_cnt_u prm_tx_y_stl_st_sh_his_cnt; /* 120 */ + volatile csr_prm_tx_g_mon_cfg_u prm_tx_g_mon_cfg; /* 124 */ + volatile csr_prm_tx_g_his_cfg_u prm_tx_g_his_cfg; /* 128 */ + volatile csr_prm_tx_cpi_aloc_u prm_tx_cpi_aloc; /* 12C */ + volatile csr_prm_tx_grq_aloc_u prm_tx_grq_aloc; /* 130 */ + volatile csr_prm_tx_grq_daloc_u prm_tx_grq_daloc; /* 134 */ + volatile csr_prm_tx_cpi_aloc_cnt_u prm_tx_cpi_aloc_cnt; /* 138 */ + volatile csr_prm_tx_grq_aloc_cnt_u prm_tx_grq_aloc_cnt; /* 13C */ + volatile csr_prm_tx_grq_daloc_cnt_u prm_tx_grq_daloc_cnt; /* 140 */ + volatile csr_prm_tx_h_cos_his_cnt_u prm_tx_h_cos_his_cnt; /* 144 */ + volatile csr_prm_tx_h_p_his_cnt_u prm_tx_h_p_his_cnt; /* 148 */ + volatile csr_prm_tx_h_p_sh_his_cnt_u prm_tx_h_p_sh_his_cnt; /* 14C */ + volatile csr_prm_tx_h_srv_his_cnt_u prm_tx_h_srv_his_cnt; /* 150 */ + volatile csr_prm_tx_h_srv_sh_his_cnt_u prm_tx_h_srv_sh_his_cnt; /* 154 */ + volatile csr_prm_tx_glb_rsvd_cfg_u prm_tx_glb_rsvd_cfg; /* 158 */ + volatile csr_prm_tx_glb_fc_th_cfg0_u prm_tx_glb_fc_th_cfg0; /* 15C */ + volatile csr_prm_tx_glb_fc_th_cfg1_u prm_tx_glb_fc_th_cfg1; /* 160 */ + volatile csr_prm_tx_glb_fc_th_cfg2_u prm_tx_glb_fc_th_cfg2; /* 164 */ + volatile csr_prm_tx_glb_drp_th_cfg_u prm_tx_glb_drp_th_cfg; /* 168 */ + volatile csr_prm_tx_pg1_rsvd_cfg_u prm_tx_pg1_rsvd_cfg; /* 16C */ + volatile csr_prm_tx_pg1_fc_th_cfg0_u prm_tx_pg1_fc_th_cfg0; /* 170 */ + volatile csr_prm_tx_pg1_fc_th_cfg1_u prm_tx_pg1_fc_th_cfg1; /* 174 */ + volatile csr_prm_tx_pg1_fc_th_cfg2_u prm_tx_pg1_fc_th_cfg2; /* 178 */ + volatile csr_prm_tx_pg1_drp_th_cfg_u prm_tx_pg1_drp_th_cfg; /* 17C */ + volatile csr_prm_tx_pg2_rsvd_cfg_u prm_tx_pg2_rsvd_cfg; /* 180 */ + volatile csr_prm_tx_pg2_fc_th_cfg0_u prm_tx_pg2_fc_th_cfg0; /* 184 */ + volatile csr_prm_tx_pg2_fc_th_cfg1_u prm_tx_pg2_fc_th_cfg1; /* 188 */ + volatile csr_prm_tx_pg2_fc_th_cfg2_u prm_tx_pg2_fc_th_cfg2; /* 18C */ + volatile csr_prm_tx_pg2_drp_th_cfg_u prm_tx_pg2_drp_th_cfg; /* 190 */ + volatile csr_prm_tx_pg3_rsvd_cfg_u prm_tx_pg3_rsvd_cfg; /* 194 */ + volatile csr_prm_tx_pg3_fc_th_cfg0_u prm_tx_pg3_fc_th_cfg0; /* 198 */ + volatile csr_prm_tx_pg3_fc_th_cfg1_u prm_tx_pg3_fc_th_cfg1; /* 19C */ + volatile csr_prm_tx_pg3_fc_th_cfg2_u prm_tx_pg3_fc_th_cfg2; /* 1A0 */ + volatile csr_prm_tx_pg3_drp_th_cfg_u prm_tx_pg3_drp_th_cfg; /* 1A4 */ + volatile csr_prm_tx_pg1_cnt_u prm_tx_pg1_cnt; /* 1A8 */ + volatile csr_prm_tx_pg2_cnt_u prm_tx_pg2_cnt; /* 1AC */ + volatile csr_prm_tx_pg3_cnt_u prm_tx_pg3_cnt; /* 1B0 */ + volatile csr_prm_tx_glb_cnt_u prm_tx_glb_cnt; /* 1B4 */ + volatile csr_prm_tx_glb_max_cnt_cfg_u prm_tx_glb_max_cnt_cfg; /* 1B8 */ + volatile csr_prm_tx_cpi_req_cfg_u prm_tx_cpi_req_cfg; /* 1BC */ + volatile csr_prm_tx_mqm_uload_cfg_u prm_tx_mqm_uload_cfg; /* 1C0 */ + volatile csr_prm_tx_bmh_wrr_cfg_u prm_tx_bmh_wrr_cfg; /* 1C4 */ + volatile csr_prm_tx_bmy_wrr_cfg_u prm_tx_bmy_wrr_cfg; /* 1C8 */ + volatile csr_prm_tx_bmr_wrr_cfg0_u prm_tx_bmr_wrr_cfg0; /* 1CC */ + volatile csr_prm_tx_bmr_wrr_cfg1_u prm_tx_bmr_wrr_cfg1; /* 1D0 */ + volatile csr_prm_tx_bmg_wrr_cfg_u prm_tx_bmg_wrr_cfg; /* 1D4 */ + volatile csr_prm_tx_cnt_over_flag_u prm_tx_cnt_over_flag; /* 1D8 */ + volatile csr_prm_tx_cnt_under_flag_u prm_tx_cnt_under_flag; /* 1DC */ + volatile csr_prm_tx_fifo_th_cfg0_u prm_tx_fifo_th_cfg0; /* 1E0 */ + volatile csr_prm_tx_fifo_th_cfg1_u prm_tx_fifo_th_cfg1; /* 1E4 */ + volatile csr_prm_tx_fifo_th_cfg2_u prm_tx_fifo_th_cfg2; /* 1E8 */ + volatile csr_prm_tx_cpb_aloc_u prm_tx_cpb_aloc; /* 1EC */ + volatile csr_prm_tx_cpb_aloc_cnt_u prm_tx_cpb_aloc_cnt; /* 1F0 */ + volatile csr_prm_tx_oq_aloc_u prm_tx_oq_aloc; /* 1F4 */ + volatile csr_prm_tx_oq_aloc_cnt_u prm_tx_oq_aloc_cnt; /* 1F8 */ + volatile csr_prm_tx_double_daloc_wgt_u prm_tx_double_daloc_wgt; /* 1FC */ + volatile csr_prm_tx_err_src_u prm_tx_err_src; /* 200 */ + volatile csr_prmtx_bw_monitor_en_u prmtx_bw_monitor_en; /* 234 */ + volatile csr_prmtx_bw_monitor_win_len_u prmtx_bw_monitor_win_len; /* 238 */ + volatile csr_prmtx_bw_monitor_max_times_cpb_aloc_u prmtx_bw_monitor_max_times_cpb_aloc; /* 23C */ + volatile csr_prmtx_bw_monitor_max_times_cpi_aloc_u prmtx_bw_monitor_max_times_cpi_aloc; /* 240 */ + volatile csr_prmtx_bw_monitor_max_times_oq_aloc_u prmtx_bw_monitor_max_times_oq_aloc; /* 244 */ + volatile csr_prmtx_bw_monitor_max_times_cpb_daloc_u prmtx_bw_monitor_max_times_cpb_daloc; /* 248 */ + volatile csr_prmtx_bw_monitor_max_times_cpb_drop_u prmtx_bw_monitor_max_times_cpb_drop; /* 24C */ + volatile csr_prmtx_bw_monitor_max_times_stliq_u prmtx_bw_monitor_max_times_stliq; /* 250 */ + volatile csr_prmtx_bw_monitor_max_times_stfiq_u prmtx_bw_monitor_max_times_stfiq; /* 254 */ + volatile csr_prmtx_bw_monitor_max_times_stlfq_aloc_u prmtx_bw_monitor_max_times_stlfq_aloc; /* 258 */ + volatile csr_prmtx_bw_monitor_max_times_stffq0_aloc_u prmtx_bw_monitor_max_times_stffq0_aloc; /* 25C */ + volatile csr_prmtx_bw_monitor_max_times_stffq1_aloc_u prmtx_bw_monitor_max_times_stffq1_aloc; /* 260 */ + volatile csr_prmtx_bw_monitor_max_times_stlfq_daloc_u prmtx_bw_monitor_max_times_stlfq_daloc; /* 264 */ + volatile csr_prmtx_bw_monitor_max_times_stffq0_daloc_u prmtx_bw_monitor_max_times_stffq0_daloc; /* 268 */ + volatile csr_prmtx_bw_monitor_max_times_stffq1_daloc_u prmtx_bw_monitor_max_times_stffq1_daloc; /* 26C */ + volatile csr_prmtx_bw_monitor_max_times_oq_daloc_u prmtx_bw_monitor_max_times_oq_daloc; /* 270 */ + volatile csr_prmtx_bw_monitor_win_cnt_u prmtx_bw_monitor_win_cnt; /* 274 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpb_aloc_u prmtx_bw_monitor_over_max_times_cnt_cpb_aloc; /* 278 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpi_aloc_u prmtx_bw_monitor_over_max_times_cnt_cpi_aloc; /* 27C */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_oq_aloc_u prmtx_bw_monitor_over_max_times_cnt_oq_aloc; /* 280 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpb_daloc_u prmtx_bw_monitor_over_max_times_cnt_cpb_daloc; /* 284 + */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpb_drop_u prmtx_bw_monitor_over_max_times_cnt_cpb_drop; /* 288 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stliq_u prmtx_bw_monitor_over_max_times_cnt_stliq; /* 28C */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stfiq_u prmtx_bw_monitor_over_max_times_cnt_stfiq; /* 290 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc_u prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc; /* 294 + */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc; /* 298 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc; /* 29C */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc_u + prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc; /* 2A0 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc; /* 2A4 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc; /* 2A8 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_oq_daloc_u prmtx_bw_monitor_over_max_times_cnt_oq_daloc; /* 2AC */ +} S_qu_prm_tx_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_tx_csr */ +extern volatile S_qu_prm_tx_csr_REGS_TYPE *gopqu_prm_tx_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_TX_INDRECT_CTRL_indirect_ctrl(unsigned int uindirect_ctrl); +int iSetPRM_TX_INDRECT_TIMEOUT_indirect_timeout(unsigned int uindirect_timeout); +int iSetPRM_TX_INDRECT_DAT0_indirect_dat0(unsigned int uindirect_dat0); +int iSetPRM_TX_INDRECT_DAT1_indirect_dat1(unsigned int uindirect_dat1); +int iSetPRM_TX_INDRECT_DAT2_indirect_dat2(unsigned int uindirect_dat2); +int iSetPRM_TX_INDRECT_DAT3_indirect_dat3(unsigned int uindirect_dat3); +int iSetPRM_TX_INDRECT_DAT4_indirect_dat4(unsigned int uindirect_dat4); +int iSetPRM_TX_INDRECT_DAT5_indirect_dat5(unsigned int uindirect_dat5); +int iSetPRM_TX_INDRECT_DAT6_indirect_dat6(unsigned int uindirect_dat6); +int iSetPRM_TX_CSR_CFG_dyn_csr_req_src(unsigned int udyn_csr_req_src); +int iSetPRM_TX_CSR_CFG_bmr_dyn_csr_req(unsigned int ubmr_dyn_csr_req); +int iSetPRM_TX_CSR_CFG_bmy_dyn_csr_req(unsigned int ubmy_dyn_csr_req); +int iSetPRM_TX_CSR_CFG_bmh_dyn_csr_req(unsigned int ubmh_dyn_csr_req); +int iSetPRM_TX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_on(unsigned int ustf_state_y_fc0_th_on); +int iSetPRM_TX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_dif(unsigned int ustf_state_y_fc0_th_dif); +int iSetPRM_TX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_on(unsigned int ustl_state_y_fc0_th_on); +int iSetPRM_TX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_dif(unsigned int ustl_state_y_fc0_th_dif); +int iSetPRM_TX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_on(unsigned int ustf_state_r_fc0_th_on); +int iSetPRM_TX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_dif(unsigned int ustf_state_r_fc0_th_dif); +int iSetPRM_TX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_on(unsigned int ustl_state_r_fc0_th_on); +int iSetPRM_TX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_dif(unsigned int ustl_state_r_fc0_th_dif); +int iSetPRM_TX_Y_STF_RSVD_CFG_stf_state_y_rsvd(unsigned int ustf_state_y_rsvd); +int iSetPRM_TX_Y_STL_RSVD_CFG_stl_state_y_rsvd(unsigned int ustl_state_y_rsvd); +int iSetPRM_TX_R_STF_RSVD_CFG_stf_state_r_rsvd(unsigned int ustf_state_r_rsvd); +int iSetPRM_TX_R_STL_RSVD_CFG_stl_state_r_rsvd(unsigned int ustl_state_r_rsvd); +int iSetPRM_TX_Y_STF_CNT_stf_state_y_cnt(unsigned int ustf_state_y_cnt); +int iSetPRM_TX_Y_STL_CNT_stl_state_y_cnt(unsigned int ustl_state_y_cnt); +int iSetPRM_TX_R_STF_CNT_stf_state_r_cnt(unsigned int ustf_state_r_cnt); +int iSetPRM_TX_R_STL_CNT_stl_state_r_cnt(unsigned int ustl_state_r_cnt); +int iSetPRM_TX_Y_STF_SH_CNT_stf_state_y_sh_cnt(unsigned int ustf_state_y_sh_cnt); +int iSetPRM_TX_Y_STL_SH_CNT_stl_state_y_sh_cnt(unsigned int ustl_state_y_sh_cnt); +int iSetPRM_TX_R_STF_SH_CNT_stf_state_r_sh_cnt(unsigned int ustf_state_r_sh_cnt); +int iSetPRM_TX_R_STL_SH_CNT_stl_state_r_sh_cnt(unsigned int ustl_state_r_sh_cnt); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_mon_cos(unsigned int ubmy_cfg_mon_cos); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_mon_sp(unsigned int ubmy_cfg_mon_sp); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_mon_srv(unsigned int ubmy_cfg_mon_srv); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_cnt_type(unsigned int ubmy_cfg_cnt_type); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_cnt_en(unsigned int ubmy_cfg_cnt_en); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_sp(unsigned int ubmy_cfg_his_cnt_sp); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_srv(unsigned int ubmy_cfg_his_cnt_srv); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_clr(unsigned int ubmy_cfg_his_cnt_clr); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_en(unsigned int ubmy_cfg_his_cnt_en); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_mon_cos(unsigned int ubmr_cfg_mon_cos); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_mon_sp(unsigned int ubmr_cfg_mon_sp); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_mon_srv(unsigned int ubmr_cfg_mon_srv); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_cnt_type(unsigned int ubmr_cfg_cnt_type); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_cnt_en(unsigned int ubmr_cfg_cnt_en); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_sp(unsigned int ubmr_cfg_his_cnt_sp); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_srv(unsigned int ubmr_cfg_his_cnt_srv); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_clr(unsigned int ubmr_cfg_his_cnt_clr); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_en(unsigned int ubmr_cfg_his_cnt_en); +int iSetPRM_TX_STLFQ_ALOC_bmr_stlfq_aloc_cnt_wr_v(unsigned int ubmr_stlfq_aloc_cnt_wr_v); +int iSetPRM_TX_STFFQ0_ALOC_bmr_stffq0_aloc_cnt_wr_v(unsigned int ubmr_stffq0_aloc_cnt_wr_v); +int iSetPRM_TX_STFFQ1_ALOC_bmr_stffq1_aloc_cnt_wr_v(unsigned int ubmr_stffq1_aloc_cnt_wr_v); +int iSetPRM_TX_STLFQ_DALOC_bmr_stlfq_daloc_cnt_wr_v(unsigned int ubmr_stlfq_daloc_cnt_wr_v); +int iSetPRM_TX_STFFQ0_DALOC_bmr_stffq0_daloc_cnt_wr_v(unsigned int ubmr_stffq0_daloc_cnt_wr_v); +int iSetPRM_TX_STFFQ1_DALOC_bmr_stffq1_daloc_cnt_wr_v(unsigned int ubmr_stffq1_daloc_cnt_wr_v); +int iSetPRM_TX_CPB_DALOC_bmr_cpb_daloc_cnt_wr_v(unsigned int ubmr_cpb_daloc_cnt_wr_v); +int iSetPRM_TX_CPB_DROP_bmr_cpb_drop_cnt_wr_v(unsigned int ubmr_cpb_drop_cnt_wr_v); +int iSetPRM_TX_OQ_DALOC_bmr_oq_daloc_cnt_wr_v(unsigned int ubmr_oq_daloc_cnt_wr_v); +int iSetPRM_TX_STLFQ_ALOC_CNT_bmr_stlfq_aloc_cnt_num_v(unsigned int ubmr_stlfq_aloc_cnt_num_v); +int iSetPRM_TX_STFFQ0_ALOC_CNT_bmr_stffq0_aloc_cnt_num_v(unsigned int ubmr_stffq0_aloc_cnt_num_v); +int iSetPRM_TX_STFFQ1_ALOC_CNT_bmr_stffq1_aloc_cnt_num_v(unsigned int ubmr_stffq1_aloc_cnt_num_v); +int iSetPRM_TX_STLFQ_DALOC_CNT_bmr_stlfq_daloc_cnt_num_v(unsigned int ubmr_stlfq_daloc_cnt_num_v); +int iSetPRM_TX_STFFQ0_DALOC_CNT_bmr_stffq0_daloc_cnt_num_v(unsigned int ubmr_stffq0_daloc_cnt_num_v); +int iSetPRM_TX_STFFQ1_DALOC_CNT_bmr_stffq1_daloc_cnt_num_v(unsigned int ubmr_stffq1_daloc_cnt_num_v); +int iSetPRM_TX_CPB_DALOC_CNT_bmr_cpb_daloc_cnt_num_v(unsigned int ubmr_cpb_daloc_cnt_num_v); +int iSetPRM_TX_CPB_DROP_CNT_bmr_cpb_drop_cnt_num_v(unsigned int ubmr_cpb_drop_cnt_num_v); +int iSetPRM_TX_OQ_DALOC_CNT_bmr_oq_daloc_cnt_num_v(unsigned int ubmr_oq_daloc_cnt_num_v); +int iSetPRM_TX_R_STF_P_HIS_CNT_bmr_stf_his_cnt_port(unsigned int ubmr_stf_his_cnt_port); +int iSetPRM_TX_R_STL_P_HIS_CNT_bmr_stl_his_cnt_port(unsigned int ubmr_stl_his_cnt_port); +int iSetPRM_TX_R_STF_SRV_HIS_CNT_bmr_stf_his_cnt_srv(unsigned int ubmr_stf_his_cnt_srv); +int iSetPRM_TX_R_STL_SRV_HIS_CNT_bmr_stl_his_cnt_srv(unsigned int ubmr_stl_his_cnt_srv); +int iSetPRM_TX_R_STF_SRV_SH_HIS_CNT_bmr_stf_his_cnt_srv_sh(unsigned int ubmr_stf_his_cnt_srv_sh); +int iSetPRM_TX_R_STL_SRV_SH_HIS_CNT_bmr_stl_his_cnt_srv_sh(unsigned int ubmr_stl_his_cnt_srv_sh); +int iSetPRM_TX_R_STF_ST_HIS_CNT_bmr_stf_his_cnt_st(unsigned int ubmr_stf_his_cnt_st); +int iSetPRM_TX_R_STL_ST_HIS_CNT_bmr_stl_his_cnt_st(unsigned int ubmr_stl_his_cnt_st); +int iSetPRM_TX_R_STF_ST_SH_HIS_CNT_bmr_stf_his_cnt_st_sh(unsigned int ubmr_stf_his_cnt_st_sh); +int iSetPRM_TX_R_STL_ST_SH_HIS_CNT_bmr_stl_his_cnt_st_sh(unsigned int ubmr_stl_his_cnt_st_sh); +int iSetPRM_TX_STFIQ_ALOC_bmy_stf_iq_icb_aloc_cnt_wr(unsigned int ubmy_stf_iq_icb_aloc_cnt_wr); +int iSetPRM_TX_STLIQ_ALOC_bmy_stl_iq_icb_aloc_cnt_wr(unsigned int ubmy_stl_iq_icb_aloc_cnt_wr); +int iSetPRM_TX_YDA_DALOC_bmy_yda_daloc_cnt_wr(unsigned int ubmy_yda_daloc_cnt_wr); +int iSetPRM_TX_STFIQ_ALOC_CNT_bmy_stf_iq_icb_aloc_cnt_num(unsigned int ubmy_stf_iq_icb_aloc_cnt_num); +int iSetPRM_TX_STLIQ_ALOC_CNT_bmy_stl_iq_icb_aloc_cnt_num(unsigned int ubmy_stl_iq_icb_aloc_cnt_num); +int iSetPRM_TX_YDA_DALOC_CNT_bmy_yda_daloc_cnt_num(unsigned int ubmy_yda_daloc_cnt_num); +int iSetPRM_TX_Y_STF_P_HIS_CNT_bmy_stf_his_cnt_port(unsigned int ubmy_stf_his_cnt_port); +int iSetPRM_TX_Y_STL_P_HIS_CNT_bmy_stl_his_cnt_port(unsigned int ubmy_stl_his_cnt_port); +int iSetPRM_TX_Y_STF_ST_HIS_CNT_bmy_stf_his_cnt_st(unsigned int ubmy_stf_his_cnt_st); +int iSetPRM_TX_Y_STL_ST_HIS_CNT_bmy_stl_his_cnt_st(unsigned int ubmy_stl_his_cnt_st); +int iSetPRM_TX_Y_STF_ST_SH_HIS_CNT_bmy_stf_his_cnt_st_sh(unsigned int ubmy_stf_his_cnt_st_sh); +int iSetPRM_TX_Y_STL_ST_SH_HIS_CNT_bmy_stl_his_cnt_st_sh(unsigned int ubmy_stl_his_cnt_st_sh); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_mon_cos(unsigned int ubmh_cfg_mon_cos); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_mon_sp(unsigned int ubmh_cfg_mon_sp); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_mon_side(unsigned int ubmh_cfg_mon_side); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_cnt_type(unsigned int ubmh_cfg_cnt_type); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_cnt_en(unsigned int ubmh_cfg_cnt_en); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_cos(unsigned int ubmh_cfg_his_cnt_cos); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_sp(unsigned int ubmh_cfg_his_cnt_sp); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_clr(unsigned int ubmh_cfg_his_cnt_clr); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_en(unsigned int ubmh_cfg_his_cnt_en); +int iSetPRM_TX_CPI_ALOC_bmh_cpi_aloc_cnt_wr(unsigned int ubmh_cpi_aloc_cnt_wr); +int iSetPRM_TX_GRQ_ALOC_bmh_grq_aloc_cnt_wr(unsigned int ubmh_grq_aloc_cnt_wr); +int iSetPRM_TX_GRQ_DALOC_bmh_grq_daloc_cnt_wr(unsigned int ubmh_grq_daloc_cnt_wr); +int iSetPRM_TX_CPI_ALOC_CNT_bmh_cpi_aloc_cnt_num(unsigned int ubmh_cpi_aloc_cnt_num); +int iSetPRM_TX_GRQ_ALOC_CNT_bmh_grq_aloc_cnt_num(unsigned int ubmh_grq_aloc_cnt_num); +int iSetPRM_TX_GRQ_DALOC_CNT_bmh_grq_daloc_cnt_num(unsigned int ubmh_grq_daloc_cnt_num); +int iSetPRM_TX_H_COS_HIS_CNT_bmh_his_cnt_cos(unsigned int ubmh_his_cnt_cos); +int iSetPRM_TX_H_P_HIS_CNT_bmh_his_cnt_port(unsigned int ubmh_his_cnt_port); +int iSetPRM_TX_H_P_SH_HIS_CNT_bmh_his_sh_cnt_port(unsigned int ubmh_his_sh_cnt_port); +int iSetPRM_TX_H_SRV_HIS_CNT_bmh_his_cnt_srv(unsigned int ubmh_his_cnt_srv); +int iSetPRM_TX_H_SRV_SH_HIS_CNT_bmh_his_sh_cnt_srv(unsigned int ubmh_his_sh_cnt_srv); +int iSetPRM_TX_GLB_RSVD_CFG_glb_rsvd_th(unsigned int uglb_rsvd_th); +int iSetPRM_TX_GLB_FC_TH_CFG0_glb_fc0_th_on(unsigned int uglb_fc0_th_on); +int iSetPRM_TX_GLB_FC_TH_CFG0_glb_fc0_th_dif(unsigned int uglb_fc0_th_dif); +int iSetPRM_TX_GLB_FC_TH_CFG1_glb_fc1_th_on(unsigned int uglb_fc1_th_on); +int iSetPRM_TX_GLB_FC_TH_CFG1_glb_fc1_th_dif(unsigned int uglb_fc1_th_dif); +int iSetPRM_TX_GLB_FC_TH_CFG2_glb_fc2_th_on(unsigned int uglb_fc2_th_on); +int iSetPRM_TX_GLB_FC_TH_CFG2_glb_fc2_th_dif(unsigned int uglb_fc2_th_dif); +int iSetPRM_TX_GLB_DRP_TH_CFG_glb_drp_th_on(unsigned int uglb_drp_th_on); +int iSetPRM_TX_GLB_DRP_TH_CFG_glb_drp_th_dif(unsigned int uglb_drp_th_dif); +int iSetPRM_TX_PG1_RSVD_CFG_pg1_rsvd_th(unsigned int upg1_rsvd_th); +int iSetPRM_TX_PG1_FC_TH_CFG0_pg1_fc0_th_on(unsigned int upg1_fc0_th_on); +int iSetPRM_TX_PG1_FC_TH_CFG0_pg1_fc0_th_dif(unsigned int upg1_fc0_th_dif); +int iSetPRM_TX_PG1_FC_TH_CFG1_pg1_fc1_th_on(unsigned int upg1_fc1_th_on); +int iSetPRM_TX_PG1_FC_TH_CFG1_pg1_fc1_th_dif(unsigned int upg1_fc1_th_dif); +int iSetPRM_TX_PG1_FC_TH_CFG2_pg1_fc2_th_on(unsigned int upg1_fc2_th_on); +int iSetPRM_TX_PG1_FC_TH_CFG2_pg1_fc2_th_dif(unsigned int upg1_fc2_th_dif); +int iSetPRM_TX_PG1_DRP_TH_CFG_pg1_drp_th_on(unsigned int upg1_drp_th_on); +int iSetPRM_TX_PG1_DRP_TH_CFG_pg1_drp_th_dif(unsigned int upg1_drp_th_dif); +int iSetPRM_TX_PG2_RSVD_CFG_pg2_rsvd_th(unsigned int upg2_rsvd_th); +int iSetPRM_TX_PG2_FC_TH_CFG0_pg2_fc0_th_on(unsigned int upg2_fc0_th_on); +int iSetPRM_TX_PG2_FC_TH_CFG0_pg2_fc0_th_dif(unsigned int upg2_fc0_th_dif); +int iSetPRM_TX_PG2_FC_TH_CFG1_pg2_fc1_th_on(unsigned int upg2_fc1_th_on); +int iSetPRM_TX_PG2_FC_TH_CFG1_pg2_fc1_th_dif(unsigned int upg2_fc1_th_dif); +int iSetPRM_TX_PG2_FC_TH_CFG2_pg2_fc2_th_on(unsigned int upg2_fc2_th_on); +int iSetPRM_TX_PG2_FC_TH_CFG2_pg2_fc2_th_dif(unsigned int upg2_fc2_th_dif); +int iSetPRM_TX_PG2_DRP_TH_CFG_pg2_drp_th_on(unsigned int upg2_drp_th_on); +int iSetPRM_TX_PG2_DRP_TH_CFG_pg2_drp_th_dif(unsigned int upg2_drp_th_dif); +int iSetPRM_TX_PG3_RSVD_CFG_pg3_rsvd_th(unsigned int upg3_rsvd_th); +int iSetPRM_TX_PG3_FC_TH_CFG0_pg3_fc0_th_on(unsigned int upg3_fc0_th_on); +int iSetPRM_TX_PG3_FC_TH_CFG0_pg3_fc0_th_dif(unsigned int upg3_fc0_th_dif); +int iSetPRM_TX_PG3_FC_TH_CFG1_pg3_fc1_th_on(unsigned int upg3_fc1_th_on); +int iSetPRM_TX_PG3_FC_TH_CFG1_pg3_fc1_th_dif(unsigned int upg3_fc1_th_dif); +int iSetPRM_TX_PG3_FC_TH_CFG2_pg3_fc2_th_on(unsigned int upg3_fc2_th_on); +int iSetPRM_TX_PG3_FC_TH_CFG2_pg3_fc2_th_dif(unsigned int upg3_fc2_th_dif); +int iSetPRM_TX_PG3_DRP_TH_CFG_pg3_drp_th_on(unsigned int upg3_drp_th_on); +int iSetPRM_TX_PG3_DRP_TH_CFG_pg3_drp_th_dif(unsigned int upg3_drp_th_dif); +int iSetPRM_TX_PG1_CNT_pg1_curr_sh_cnt_st(unsigned int upg1_curr_sh_cnt_st); +int iSetPRM_TX_PG1_CNT_pg1_curr_cnt_st(unsigned int upg1_curr_cnt_st); +int iSetPRM_TX_PG2_CNT_pg2_curr_sh_cnt_st(unsigned int upg2_curr_sh_cnt_st); +int iSetPRM_TX_PG2_CNT_pg2_curr_cnt_st(unsigned int upg2_curr_cnt_st); +int iSetPRM_TX_PG3_CNT_pg3_curr_sh_cnt_st(unsigned int upg3_curr_sh_cnt_st); +int iSetPRM_TX_PG3_CNT_pg3_curr_cnt_st(unsigned int upg3_curr_cnt_st); +int iSetPRM_TX_GLB_CNT_glb_curr_sh_cnt_st(unsigned int uglb_curr_sh_cnt_st); +int iSetPRM_TX_GLB_CNT_glb_curr_cnt_st(unsigned int uglb_curr_cnt_st); +int iSetPRM_TX_GLB_MAX_CNT_CFG_cfg_glb_max_th(unsigned int ucfg_glb_max_th); +int iSetPRM_TX_GLB_MAX_CNT_CFG_cfg_glb_max_sh(unsigned int ucfg_glb_max_sh); +int iSetPRM_TX_CPI_REQ_CFG_cfg_cpi_wg_period(unsigned int ucfg_cpi_wg_period); +int iSetPRM_TX_CPI_REQ_CFG_cfg_cpi_toke_unit(unsigned int ucfg_cpi_toke_unit); +int iSetPRM_TX_CPI_REQ_CFG_msk_sel_cpi_req(unsigned int umsk_sel_cpi_req); +int iSetPRM_TX_MQM_ULOAD_CFG_qu_mqm_underloading_th(unsigned int uqu_mqm_underloading_th); +int iSetPRM_TX_BMH_WRR_CFG_tx_bmh_wrr_wgt_cfg(unsigned int utx_bmh_wrr_wgt_cfg); +int iSetPRM_TX_BMY_WRR_CFG_tx_bmy_wrr_wgt_cfg(unsigned int utx_bmy_wrr_wgt_cfg); +int iSetPRM_TX_BMR_WRR_CFG0_tx_bmr_wrr_wgt_cfg0(unsigned int utx_bmr_wrr_wgt_cfg0); +int iSetPRM_TX_BMR_WRR_CFG1_tx_bmr_wrr_wgt_cfg1(unsigned int utx_bmr_wrr_wgt_cfg1); +int iSetPRM_TX_BMG_WRR_CFG_tx_bmg_wrr_wgt_cfg(unsigned int utx_bmg_wrr_wgt_cfg); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_cos_h_of(unsigned int umem_cnt_cos_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_p_h_of(unsigned int umem_cnt_p_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_srv_h_of(unsigned int umem_cnt_srv_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_p_h_of(unsigned int umem_sh_cnt_p_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_srv_h_of(unsigned int umem_sh_cnt_srv_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_p_y_of(unsigned int umem_cnt_stf_p_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_srv_y_of(unsigned int umem_cnt_stf_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_y_of(unsigned int umem_sh_cnt_stf_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_p_y_of(unsigned int umem_cnt_stl_p_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_srv_y_of(unsigned int umem_cnt_stl_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_y_of(unsigned int umem_sh_cnt_stl_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_p_r_of(unsigned int umem_cnt_stf_p_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_srv_r_of(unsigned int umem_cnt_stf_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_r_of(unsigned int umem_sh_cnt_stf_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_p_r_of(unsigned int umem_cnt_stl_p_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_srv_r_of(unsigned int umem_cnt_stl_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_r_of(unsigned int umem_sh_cnt_stl_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_glb_cnt_of(unsigned int uglb_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg3_cnt_of(unsigned int upg3_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg2_cnt_of(unsigned int upg2_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg1_cnt_of(unsigned int upg1_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_glb_sh_cnt_of(unsigned int uglb_sh_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg3_sh_cnt_of(unsigned int upg3_sh_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg2_sh_cnt_of(unsigned int upg2_sh_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg1_sh_cnt_of(unsigned int upg1_sh_cnt_of); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_cos_h_uf(unsigned int umem_cnt_cos_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_p_h_uf(unsigned int umem_cnt_p_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_srv_h_uf(unsigned int umem_cnt_srv_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_p_h_uf(unsigned int umem_sh_cnt_p_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_srv_h_uf(unsigned int umem_sh_cnt_srv_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_p_y_uf(unsigned int umem_cnt_stf_p_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_srv_y_uf(unsigned int umem_cnt_stf_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_y_uf(unsigned int umem_sh_cnt_stf_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_p_y_uf(unsigned int umem_cnt_stl_p_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_srv_y_uf(unsigned int umem_cnt_stl_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_y_uf(unsigned int umem_sh_cnt_stl_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_p_r_uf(unsigned int umem_cnt_stf_p_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_srv_r_uf(unsigned int umem_cnt_stf_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_r_uf(unsigned int umem_sh_cnt_stf_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_p_r_uf(unsigned int umem_cnt_stl_p_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_srv_r_uf(unsigned int umem_cnt_stl_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_r_uf(unsigned int umem_sh_cnt_stl_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_glb_cnt_uf(unsigned int uglb_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg3_cnt_uf(unsigned int upg3_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg2_cnt_uf(unsigned int upg2_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg1_cnt_uf(unsigned int upg1_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_glb_sh_cnt_uf(unsigned int uglb_sh_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg3_sh_cnt_uf(unsigned int upg3_sh_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg2_sh_cnt_uf(unsigned int upg2_sh_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg1_sh_cnt_uf(unsigned int upg1_sh_cnt_uf); +int iSetPRM_TX_FIFO_TH_CFG0_stffq1_daloc_n_af_th(unsigned int ustffq1_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stffq1_aloc_n_af_th(unsigned int ustffq1_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stffq0_daloc_n_af_th(unsigned int ustffq0_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stffq0_aloc_n_af_th(unsigned int ustffq0_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stlfq_daloc_n_af_th(unsigned int ustlfq_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stlfq_aloc_n_af_th(unsigned int ustlfq_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_stfiq_n_af_th(unsigned int ustfiq_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_stliq_n_af_th(unsigned int ustliq_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_oq_daloc_n_af_th(unsigned int uoq_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_oq_aloc_n_af_th(unsigned int uoq_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG2_cpb_aloc_n_af_th(unsigned int ucpb_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG2_cpb_daloc_n_af_th(unsigned int ucpb_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG2_cpi_aloc_n_af_th(unsigned int ucpi_aloc_n_af_th); +int iSetPRM_TX_CPB_ALOC_bmh_cpb_aloc_cnt_wr(unsigned int ubmh_cpb_aloc_cnt_wr); +int iSetPRM_TX_CPB_ALOC_CNT_bmh_cpb_aloc_cnt_num(unsigned int ubmh_cpb_aloc_cnt_num); +int iSetPRM_TX_OQ_ALOC_bmh_oq_aloc_cnt_wr(unsigned int ubmh_oq_aloc_cnt_wr); +int iSetPRM_TX_OQ_ALOC_CNT_bmh_oq_aloc_cnt_num(unsigned int ubmh_oq_aloc_cnt_num); +int iSetPRM_TX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg3_wgt_cfg(unsigned int ustf_stl_daloc_pg3_wgt_cfg); +int iSetPRM_TX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg2_wgt_cfg(unsigned int ustf_stl_daloc_pg2_wgt_cfg); +int iSetPRM_TX_ERR_SRC_cos_uder_src_err(unsigned int ucos_uder_src_err); +int iSetPRM_TX_ERR_SRC_cos_over_src_err(unsigned int ucos_over_src_err); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpb_aloc_bdmonitor_en(unsigned int ucsr_prmtx_cpb_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpi_aloc_bdmonitor_en(unsigned int ucsr_prmtx_cpi_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_oq_aloc_bdmonitor_en(unsigned int ucsr_prmtx_oq_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpb_daloc_bdmonitor_en(unsigned int ucsr_prmtx_cpb_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpb_drop_bdmonitor_en(unsigned int ucsr_prmtx_cpb_drop_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stliq_bdmonitor_en(unsigned int ucsr_prmtx_stliq_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stfiq_bdmonitor_en(unsigned int ucsr_prmtx_stfiq_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stlfq_aloc_bdmonitor_en(unsigned int ucsr_prmtx_stlfq_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq0_aloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq0_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq1_aloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq1_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stlfq_daloc_bdmonitor_en(unsigned int ucsr_prmtx_stlfq_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq0_daloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq0_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq1_daloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq1_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_oq_daloc_bdmonitor_en(unsigned int ucsr_prmtx_oq_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_WIN_LEN_csr_prmtx_bdmonitro_win_len(unsigned int ucsr_prmtx_bdmonitro_win_len); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPB_ALOC_csr_prmtx_bdmonitro_max_times_cpb_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpb_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPI_ALOC_csr_prmtx_bdmonitro_max_times_cpi_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpi_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_OQ_ALOC_csr_prmtx_bdmonitro_max_times_oq_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_oq_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPB_DALOC_csr_prmtx_bdmonitro_max_times_cpb_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpb_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPB_DROP_csr_prmtx_bdmonitro_max_times_cpb_drop( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpb_drop); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STLIQ_csr_prmtx_bdmonitro_max_times_stliq( + unsigned int ucsr_prmtx_bdmonitro_max_times_stliq); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFIQ_csr_prmtx_bdmonitro_max_times_stfiq( + unsigned int ucsr_prmtx_bdmonitro_max_times_stfiq); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_csr_prmtx_bdmonitro_max_times_stlfq_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stlfq_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_csr_prmtx_bdmonitro_max_times_stffq0_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq0_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_csr_prmtx_bdmonitro_max_times_stffq1_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq1_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_csr_prmtx_bdmonitro_max_times_stlfq_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stlfq_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_csr_prmtx_bdmonitro_max_times_stffq0_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq0_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_csr_prmtx_bdmonitro_max_times_stffq1_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq1_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_OQ_DALOC_csr_prmtx_bdmonitro_max_times_oq_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_oq_daloc); +int iSetPRMTX_BW_MONITOR_WIN_CNT_prmtx_csr_bdmonitor_win_cnt(unsigned int uprmtx_csr_bdmonitor_win_cnt); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_prmtx_csr_bdmonitor_over_max_cnt_cpb_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpb_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPI_ALOC_prmtx_csr_bdmonitor_over_max_cnt_cpi_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpi_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_ALOC_prmtx_csr_bdmonitor_over_max_cnt_oq_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_oq_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_prmtx_csr_bdmonitor_over_max_cnt_cpb_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpb_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_prmtx_csr_bdmonitor_over_max_cnt_cpb_drop( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpb_drop); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_prmtx_csr_bdmonitor_over_max_cnt_stliq( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stliq); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_prmtx_csr_bdmonitor_over_max_cnt_stfiq( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stfiq); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_prmtx_csr_bdmonitor_over_max_cnt_stlfq_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stlfq_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq0_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq0_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq1_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq1_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_prmtx_csr_bdmonitor_over_max_cnt_stlfq_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stlfq_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq0_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq0_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq1_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq1_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_prmtx_csr_bdmonitor_over_max_cnt_oq_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_oq_daloc); + +/* Define the union csr_prm_fifo_af_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_sfifo_oq_orep_af_th : 6; /* [5:0] */ + u32 csr_prm_sfifo_oq_prls_af_th : 6; /* [11:6] */ + u32 csr_prm_sfifo_cpb_prls_af_th : 8; /* [19:12] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_af_cfg0_u; + +/* Define the union csr_prm_fifo_ae_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_sfifo_oq_orep_ae_th : 6; /* [5:0] */ + u32 csr_prm_sfifo_oq_prls_ae_th : 6; /* [11:6] */ + u32 csr_prm_sfifo_cpb_prls_ae_th : 8; /* [19:12] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_ae_cfg0_u; + +/* Define the union csr_prm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_indrect_ctrl_u; + +/* Define the union csr_prm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_indrect_timeout_u; + +/* Define the union csr_prm_bw_monitor_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_oq_orep_bdmonitor_en : 1; /* [0] */ + u32 csr_prm_oq_prls_bdmonitor_en : 1; /* [1] */ + u32 csr_prm_cpb_prls_bdmonitor_en : 1; /* [2] */ + u32 rsv_2 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_en_u; + +/* Define the union csr_prm_bw_monitor_win_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_win_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_win_len_u; + +/* Define the union csr_prm_bw_monitor_max_times_oq_orep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_max_times_oq_orep : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_max_times_oq_orep_u; + +/* Define the union csr_prm_bw_monitor_max_times_oq_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_max_times_oq_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_max_times_oq_prls_u; + +/* Define the union csr_prm_bw_monitor_max_times_cpb_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_max_times_cpb_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_max_times_cpb_prls_u; + +/* Define the union csr_prm_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_indrect_dat0_u; + +/* Define the union csr_prm_fifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_orep_fifo_fill : 6; /* [5:0] */ + u32 oq_prls_fifo_fill : 6; /* [11:6] */ + u32 cpb_prls_fifo_fill : 8; /* [19:12] */ + u32 rsv_3 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_fill0_u; + +/* Define the union csr_oq_prm_orep_rep_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_prm_orep_rep_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_prm_orep_rep_pck_u; + +/* Define the union csr_oq_prm_orep_lrep_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_prm_orep_lrep_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_prm_orep_lrep_pck_u; + +/* Define the union csr_oq_prm_prls_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_prm_prls_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_prm_prls_pck_u; + +/* Define the union csr_cpb_prm_prls_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_prm_prls_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_prm_prls_pck_u; + +/* Define the union csr_prm_oq_mdp_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_oq_mdp_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_oq_mdp_pck_u; + +/* Define the union csr_prm_bw_monitor_win_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_win_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_win_cnt_u; + +/* Define the union csr_prm_bw_monitor_over_max_times_cnt_oq_orep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_over_max_cnt_oq_orep : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_over_max_times_cnt_oq_orep_u; + +/* Define the union csr_prm_bw_monitor_over_max_times_cnt_oq_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_over_max_cnt_oq_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_over_max_times_cnt_oq_prls_u; + +/* Define the union csr_prm_bw_monitor_over_max_times_cnt_cpb_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_over_max_cnt_cpb_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_over_max_times_cnt_cpb_prls_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_fifo_af_cfg0_u prm_fifo_af_cfg0; /* 0 */ + volatile csr_prm_fifo_ae_cfg0_u prm_fifo_ae_cfg0; /* 4 */ + volatile csr_prm_indrect_ctrl_u prm_indrect_ctrl; /* 8 */ + volatile csr_prm_indrect_timeout_u prm_indrect_timeout; /* C */ + volatile csr_prm_bw_monitor_en_u prm_bw_monitor_en; /* 10 */ + volatile csr_prm_bw_monitor_win_len_u prm_bw_monitor_win_len; /* 14 */ + volatile csr_prm_bw_monitor_max_times_oq_orep_u prm_bw_monitor_max_times_oq_orep; /* 18 */ + volatile csr_prm_bw_monitor_max_times_oq_prls_u prm_bw_monitor_max_times_oq_prls; /* 1C */ + volatile csr_prm_bw_monitor_max_times_cpb_prls_u prm_bw_monitor_max_times_cpb_prls; /* 20 */ + volatile csr_prm_indrect_dat0_u prm_indrect_dat0; /* 24 */ + volatile csr_prm_fifo_fill0_u prm_fifo_fill0; /* 28 */ + volatile csr_oq_prm_orep_rep_pck_u oq_prm_orep_rep_pck; /* 2C */ + volatile csr_oq_prm_orep_lrep_pck_u oq_prm_orep_lrep_pck; /* 30 */ + volatile csr_oq_prm_prls_pck_u oq_prm_prls_pck; /* 34 */ + volatile csr_cpb_prm_prls_pck_u cpb_prm_prls_pck; /* 38 */ + volatile csr_prm_oq_mdp_pck_u prm_oq_mdp_pck; /* 3C */ + volatile csr_prm_bw_monitor_win_cnt_u prm_bw_monitor_win_cnt; /* 40 */ + volatile csr_prm_bw_monitor_over_max_times_cnt_oq_orep_u prm_bw_monitor_over_max_times_cnt_oq_orep; /* 44 */ + volatile csr_prm_bw_monitor_over_max_times_cnt_oq_prls_u prm_bw_monitor_over_max_times_cnt_oq_prls; /* 48 */ + volatile csr_prm_bw_monitor_over_max_times_cnt_cpb_prls_u prm_bw_monitor_over_max_times_cnt_cpb_prls; /* 4C */ +} S_qu_prm_pd_proc_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_pd_proc_csr */ +extern volatile S_qu_prm_pd_proc_csr_REGS_TYPE *gopqu_prm_pd_proc_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_FIFO_AF_CFG0_csr_prm_sfifo_oq_orep_af_th(unsigned int ucsr_prm_sfifo_oq_orep_af_th); +int iSetPRM_FIFO_AF_CFG0_csr_prm_sfifo_oq_prls_af_th(unsigned int ucsr_prm_sfifo_oq_prls_af_th); +int iSetPRM_FIFO_AF_CFG0_csr_prm_sfifo_cpb_prls_af_th(unsigned int ucsr_prm_sfifo_cpb_prls_af_th); +int iSetPRM_FIFO_AE_CFG0_csr_prm_sfifo_oq_orep_ae_th(unsigned int ucsr_prm_sfifo_oq_orep_ae_th); +int iSetPRM_FIFO_AE_CFG0_csr_prm_sfifo_oq_prls_ae_th(unsigned int ucsr_prm_sfifo_oq_prls_ae_th); +int iSetPRM_FIFO_AE_CFG0_csr_prm_sfifo_cpb_prls_ae_th(unsigned int ucsr_prm_sfifo_cpb_prls_ae_th); +int iSetPRM_INDRECT_CTRL_csr_prm_indrect_ctrl(unsigned int ucsr_prm_indrect_ctrl); +int iSetPRM_INDRECT_TIMEOUT_csr_prm_indrect_timeout(unsigned int ucsr_prm_indrect_timeout); +int iSetPRM_BW_MONITOR_EN_csr_prm_oq_orep_bdmonitor_en(unsigned int ucsr_prm_oq_orep_bdmonitor_en); +int iSetPRM_BW_MONITOR_EN_csr_prm_oq_prls_bdmonitor_en(unsigned int ucsr_prm_oq_prls_bdmonitor_en); +int iSetPRM_BW_MONITOR_EN_csr_prm_cpb_prls_bdmonitor_en(unsigned int ucsr_prm_cpb_prls_bdmonitor_en); +int iSetPRM_BW_MONITOR_WIN_LEN_csr_prm_bdmonitro_win_len(unsigned int ucsr_prm_bdmonitro_win_len); +int iSetPRM_BW_MONITOR_MAX_TIMES_OQ_OREP_csr_prm_bdmonitro_max_times_oq_orep( + unsigned int ucsr_prm_bdmonitro_max_times_oq_orep); +int iSetPRM_BW_MONITOR_MAX_TIMES_OQ_PRLS_csr_prm_bdmonitro_max_times_oq_prls( + unsigned int ucsr_prm_bdmonitro_max_times_oq_prls); +int iSetPRM_BW_MONITOR_MAX_TIMES_CPB_PRLS_csr_prm_bdmonitro_max_times_cpb_prls( + unsigned int ucsr_prm_bdmonitro_max_times_cpb_prls); +int iSetPRM_INDRECT_DAT0_csr_prm_indrect_data0(unsigned int ucsr_prm_indrect_data0); +int iSetPRM_FIFO_FILL0_oq_orep_fifo_fill(unsigned int uoq_orep_fifo_fill); +int iSetPRM_FIFO_FILL0_oq_prls_fifo_fill(unsigned int uoq_prls_fifo_fill); +int iSetPRM_FIFO_FILL0_cpb_prls_fifo_fill(unsigned int ucpb_prls_fifo_fill); +int iSetOQ_PRM_OREP_REP_PCK_oq_prm_orep_rep_pck(unsigned int uoq_prm_orep_rep_pck); +int iSetOQ_PRM_OREP_LREP_PCK_oq_prm_orep_lrep_pck(unsigned int uoq_prm_orep_lrep_pck); +int iSetOQ_PRM_PRLS_PCK_oq_prm_prls_pck(unsigned int uoq_prm_prls_pck); +int iSetCPB_PRM_PRLS_PCK_cpb_prm_prls_pck(unsigned int ucpb_prm_prls_pck); +int iSetPRM_OQ_MDP_PCK_prm_oq_mdp_pck(unsigned int uprm_oq_mdp_pck); +int iSetPRM_BW_MONITOR_WIN_CNT_prm_csr_bdmonitor_win_cnt(unsigned int uprm_csr_bdmonitor_win_cnt); +int iSetPRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_OREP_prm_csr_bdmonitor_over_max_cnt_oq_orep( + unsigned int uprm_csr_bdmonitor_over_max_cnt_oq_orep); +int iSetPRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_PRLS_prm_csr_bdmonitor_over_max_cnt_oq_prls( + unsigned int uprm_csr_bdmonitor_over_max_cnt_oq_prls); +int iSetPRM_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_PRLS_prm_csr_bdmonitor_over_max_cnt_cpb_prls( + unsigned int uprm_csr_bdmonitor_over_max_cnt_cpb_prls); + + +#endif // PRMTX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_reg_offset.h new file mode 100644 index 000000000..e8174b730 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_reg_offset.h @@ -0,0 +1,264 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmtx_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:01:17 Create file +// ****************************************************************************** + +#ifndef PRMTX_REG_OFFSET_H +#define PRMTX_REG_OFFSET_H + +/* QU_PRM_TX_CSR Base address of Module's Register */ +#define CSR_QU_PRM_TX_CSR_BASE (0x6800) + +/* **************************************************************************** */ +/* QU_PRM_TX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_CTRL_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x0) /* PRM memory indirect access ctrl register */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_TIMEOUT_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x4) /* PRM indirect access timeout configuration */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT0_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x8) /* PRM indirect access write or read data. */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT1_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x10) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT3_REG (CSR_QU_PRM_TX_CSR_BASE + 0x14) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT4_REG (CSR_QU_PRM_TX_CSR_BASE + 0x18) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT5_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT6_REG (CSR_QU_PRM_TX_CSR_BASE + 0x20) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CSR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x30) /* 软件申请配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x34) /* 黄区STF阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x38) /* 黄区STL阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x3C) /* 红区STF阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x40) /* 红区STL阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x44) /* 黄区STF RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x48) /* 黄区STL RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x4C) /* 红区STF RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x50) /* 红区STL RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x54) /* 黄区STF 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x58) /* 黄区STL 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x5C) /* 红区STF 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x60) /* 红区STL 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x64) /* 黄区STF 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x68) /* 黄区STL 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x6C) /* 红区STF 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x70) /* 红区STL 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_MON_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x74) /* 黄区monitor配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_HIS_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x78) /* 黄区最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_MON_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x7C) /* 红区monitor配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_HIS_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x80) /* 红区最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x84) /* STLFQ ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x88) /* STFFQ0 ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x8C) /* STFFQ1 ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x90) /* STLFQ DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x94) /* STFFQ0 DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x98) /* STFFQ1 DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x9C) /* CPB DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DROP_REG (CSR_QU_PRM_TX_CSR_BASE + 0xA0) /* CPB DROP 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xA4) /* OQ DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xA8) /* STLFQ ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xAC) /* STFFQ0 ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xB0) /* STFFQ1 ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xB4) /* STLFQ DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xB8) /* STFFQ0 DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xBC) /* STFFQ1 DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC0) /* CPB DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DROP_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC4) /* CPB DROP CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC8) /* OQ DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xCC) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xD0) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_SRV_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xD4) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_SRV_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xD8) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xDC) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xE0) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xE4) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xE8) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xEC) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xF0) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFIQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xF4) /* STFIQ ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLIQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xF8) /* STLIQ ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_YDA_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xFC) /* YDA DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFIQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x100) /* STFIQ ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLIQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x104) /* STLIQ ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_YDA_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x108) /* YDA DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x10C) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x110) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x114) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x118) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x11C) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x120) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_G_MON_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x124) /* 绿区monitor配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_G_HIS_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x128) /* 绿区最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPI_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x12C) /* PRM_TX_CPI_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x130) /* PRM_TX_GRQ_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x134) /* PRM_TX_GRQ_DALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPI_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x138) /* PRM_TX_CPI_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x13C) /* PRM_TX_GRQ_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x140) /* PRM_TX_GRQ_DALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_COS_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x144) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x148) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_P_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x14C) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_SRV_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x150) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x154) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x158) /* GLB RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x15C) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x160) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x164) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x168) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x16C) /* PG0 RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x170) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x174) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x178) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x17C) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x180) /* PG2 RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x184) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x188) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x18C) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x190) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x194) /* PG3 RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x198) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x19C) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1A0) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1A4) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1A8) /* PG1资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1AC) /* PG2黄区资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1B0) /* PG3红区资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1B4) /* GLB资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_MAX_CNT_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1B8) /* GLB最大阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPI_REQ_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1BC) /* CPI PRE预扣配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_MQM_ULOAD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C0) /* PG1轻负载阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMH_WRR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C4) /* TX绿区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMY_WRR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C8) /* TX黄区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMR_WRR_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1CC) /* TX红区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMR_WRR_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1D0) /* TX红区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMG_WRR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1D4) /* TX GLB 区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CNT_OVER_FLAG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1D8) /* CNT上溢出标志 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CNT_UNDER_FLAG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1DC) /* CNT下溢出标志 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_FIFO_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1E0) /* TX fifo阈值配置0 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_FIFO_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1E4) /* TX fifo阈值配置1 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_FIFO_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1E8) /* TX fifo阈值配置2 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1EC) /* PRM_TX_CPB_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1F0) /* PRM_TX_CPB_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1F4) /* PRM_TX_OQ_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1F8) /* PRM_TX_OQ_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_DOUBLE_DALOC_WGT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1FC) /* TX双黄/红区释放权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_ERR_SRC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x200) /* TX溢出DFX */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_EN_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x234) /* PRMTX侧的入口FIFO带宽监测使能配置 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_WIN_LEN_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x238) /* PRMTX侧的入口FIFO带宽监测，窗口长度配置 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPB_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x23C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPI_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x240) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_OQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x244) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPB_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x248) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPB_DROP_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x24C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STLIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x250) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x254) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x258) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x25C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x260) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x264) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x268) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x26C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_OQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x270) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_WIN_CNT_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x274) /* PRMTX侧的入口FIFO带宽监测，窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x278) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPI_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x27C) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x280) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x284) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x288) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x28C) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x290) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x294) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x298) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x29C) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2A0) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2A4) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2A8) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2AC) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ + +/* QU_PRM_PD_PROC_CSR Base address of Module's Register */ +#define CSR_QU_PRM_PD_PROC_CSR_BASE (0x7800) + +/* **************************************************************************** */ +/* QU_PRM_PD_PROC_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_PD_PROC_CSR_PRM_FIFO_AF_CFG0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x0) /* 复制流程模块FIFO的almost-full水线配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_FIFO_AE_CFG0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x4) /* 复制流程模块FIFO的almost-empty水线配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_INDRECT_CTRL_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x8) /* PRM复制流程模块间接寻址控制寄存器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_INDRECT_TIMEOUT_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0xC) /* PRM间接寻址Timeout水线配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_EN_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x10) /* PRM的入口FIFO带宽监测使能配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_WIN_LEN_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x14) /* PRM的入口FIFO带宽监测，窗口长度配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_MAX_TIMES_OQ_OREP_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x18) /* PRM的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_MAX_TIMES_OQ_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x1C) /* PRM的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_MAX_TIMES_CPB_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x20) /* PRM的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_INDRECT_DAT0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x24) /* PRM memory indirect access write data or read data. */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_FIFO_FILL0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x28) /* 复制流程模块的FIFO内数据个数 */ +#define CSR_QU_PRM_PD_PROC_CSR_OQ_PRM_OREP_REP_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x2C) /* PRM通过orep接口收到OQ的复制报文指令（不包含lrep指令）计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_OQ_PRM_OREP_LREP_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x30) /* PRM通过orep接口收到OQ的lrep指令计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_OQ_PRM_PRLS_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x34) /* PRM收到OQ的prls指令计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_CPB_PRM_PRLS_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x38) /* PRM收到CPB的prls指令计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_OQ_MDP_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x3C) /* PRM通过MDP接口向OQ丢弃报文个数计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_WIN_CNT_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x40) /* PRM的入口FIFO带宽监测，窗口个数计数器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_OREP_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x44) /* PRM的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x48) /* PRM的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x4C) /* PRM的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ + +#endif // PRMTX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_c_union_define.h new file mode 100644 index 000000000..32b33ef0e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_c_union_define.h @@ -0,0 +1,314 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : ring_cnb_c_union_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:46:44 Create file +// ****************************************************************************** + +#ifndef RING_CNB_C_UNION_DEFINE_H +#define RING_CNB_C_UNION_DEFINE_H + +/* Define the union csr_cnb_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_version_u; + +/* Define the union csr_cnb_tmout_cnt_thd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tmout_cnt_thd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_tmout_cnt_thd_u; + +/* Define the union csr_cnb_empty_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 26; /* [25:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_empty_addr_u; + +/* Define the union csr_cnb_api_err_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_err_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_err_flit_cnt_u; + +/* Define the union csr_cnb_api_crt_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_crt_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_crt_msge_cnt_u; + +/* Define the union csr_cnb_api_tx_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_tx_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_tx_msge_cnt_u; + +/* Define the union csr_cnb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_vector_u; + +/* Define the union csr_cnb_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_2 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_u; + +/* Define the union csr_cnb_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 6; /* [5:0] */ + u32 rsv_3 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_mask_u; + +/* Define the union csr_cnb_api_op_code_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_op_code_err_u; + +/* Define the union csr_cnb_csr_cmd_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_cmd_parity_err_u; + +/* Define the union csr_cnb_csr_wr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_wr_err_u; + +/* Define the union csr_cnb_csr_rddat_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rddat_parity_err_u; + +/* Define the union csr_cnb_csr_rd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rd_err_u; + +/* Define the union csr_cnb_merr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_tmout_cnt_ovf_err : 1; /* [0] */ + u32 cnb_tmout_cnt_ovf_merr : 1; /* [1] */ + u32 cnb_int_parity_err : 1; /* [2] */ + u32 cnb_int_parity_merr : 1; /* [3] */ + u32 cnb_api_e1_err : 1; /* [4] */ + u32 cnb_api_e1_merr : 1; /* [5] */ + u32 cnb_api_e0_err : 1; /* [6] */ + u32 cnb_api_e0_merr : 1; /* [7] */ + u32 cnb_api_token_err : 1; /* [8] */ + u32 cnb_api_token_merr : 1; /* [9] */ + u32 cnb_api_protocol_err : 1; /* [10] */ + u32 cnb_api_protocol_merr : 1; /* [11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_u; + +/* Define the union csr_cnb_merr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_tmout_cnt_ovf_err_mask : 1; /* [0] */ + u32 cnb_int_parity_err_mask : 1; /* [1] */ + u32 cnb_api_e1_err_mask : 1; /* [2] */ + u32 cnb_api_e0_err_mask : 1; /* [3] */ + u32 cnb_api_token_err_mask : 1; /* [4] */ + u32 cnb_api_procotol_err_mask : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_mask_u; + +/* Define the union csr_rs_nd_pe_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sta : 10; /* [9:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rs_nd_pe_crdt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cnb_version_u cnb_version; /* 0 */ + volatile csr_cnb_tmout_cnt_thd_u cnb_tmout_cnt_thd; /* 4 */ + volatile csr_cnb_empty_addr_u cnb_empty_addr; /* 8 */ + volatile csr_cnb_api_err_flit_cnt_u cnb_api_err_flit_cnt; /* C */ + volatile csr_cnb_api_crt_msge_cnt_u cnb_api_crt_msge_cnt; /* 10 */ + volatile csr_cnb_api_tx_msge_cnt_u cnb_api_tx_msge_cnt; /* 14 */ + volatile csr_cnb_int_vector_u cnb_int_vector; /* 18 */ + volatile csr_cnb_int_u cnb_int; /* 1C */ + volatile csr_cnb_int_mask_u cnb_int_mask; /* 20 */ + volatile csr_cnb_api_op_code_err_u cnb_api_op_code_err; /* 24 */ + volatile csr_cnb_csr_cmd_parity_err_u cnb_csr_cmd_parity_err; /* 28 */ + volatile csr_cnb_csr_wr_err_u cnb_csr_wr_err; /* 2C */ + volatile csr_cnb_csr_rddat_parity_err_u cnb_csr_rddat_parity_err; /* 30 */ + volatile csr_cnb_csr_rd_err_u cnb_csr_rd_err; /* 34 */ + volatile csr_cnb_merr_u cnb_merr; /* 38 */ + volatile csr_cnb_merr_mask_u cnb_merr_mask; /* 3C */ + volatile csr_rs_nd_pe_crdt_u rs_nd_pe_crdt; /* 40 */ +} S_ring_cnb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ring_cnb_csr */ +extern volatile S_ring_cnb_csr_REGS_TYPE *gopring_cnb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCNB_VERSION_cnb_version(unsigned int ucnb_version); +int iSetCNB_TMOUT_CNT_THD_rp_tmout_cnt_thd(unsigned int urp_tmout_cnt_thd); +int iSetCNB_EMPTY_ADDR_ctp(unsigned int uctp); +int iSetCNB_API_ERR_FLIT_CNT_cnb_api_err_flit_cnt(unsigned int ucnb_api_err_flit_cnt); +int iSetCNB_API_CRT_MSGE_CNT_cnb_api_crt_msge_cnt(unsigned int ucnb_api_crt_msge_cnt); +int iSetCNB_API_TX_MSGE_CNT_cnb_api_tx_msge_cnt(unsigned int ucnb_api_tx_msge_cnt); +int iSetCNB_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetCNB_INT_VECTOR_enable(unsigned int uenable); +int iSetCNB_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetCNB_INT_int_data(unsigned int uint_data); +int iSetCNB_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetCNB_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetCNB_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetCNB_API_OP_CODE_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_API_OP_CODE_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_API_OP_CODE_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_CMD_PARITY_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_CMD_PARITY_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_CMD_PARITY_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_WR_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_WR_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_WR_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_RDDAT_PARITY_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_RDDAT_PARITY_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_RDDAT_PARITY_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_RD_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_RD_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_RD_ERR_sticky(unsigned int usticky); +int iSetCNB_MERR_cnb_tmout_cnt_ovf_err(unsigned int ucnb_tmout_cnt_ovf_err); +int iSetCNB_MERR_cnb_tmout_cnt_ovf_merr(unsigned int ucnb_tmout_cnt_ovf_merr); +int iSetCNB_MERR_cnb_int_parity_err(unsigned int ucnb_int_parity_err); +int iSetCNB_MERR_cnb_int_parity_merr(unsigned int ucnb_int_parity_merr); +int iSetCNB_MERR_cnb_api_e1_err(unsigned int ucnb_api_e1_err); +int iSetCNB_MERR_cnb_api_e1_merr(unsigned int ucnb_api_e1_merr); +int iSetCNB_MERR_cnb_api_e0_err(unsigned int ucnb_api_e0_err); +int iSetCNB_MERR_cnb_api_e0_merr(unsigned int ucnb_api_e0_merr); +int iSetCNB_MERR_cnb_api_token_err(unsigned int ucnb_api_token_err); +int iSetCNB_MERR_cnb_api_token_merr(unsigned int ucnb_api_token_merr); +int iSetCNB_MERR_cnb_api_protocol_err(unsigned int ucnb_api_protocol_err); +int iSetCNB_MERR_cnb_api_protocol_merr(unsigned int ucnb_api_protocol_merr); +int iSetCNB_MERR_MASK_cnb_tmout_cnt_ovf_err_mask(unsigned int ucnb_tmout_cnt_ovf_err_mask); +int iSetCNB_MERR_MASK_cnb_int_parity_err_mask(unsigned int ucnb_int_parity_err_mask); +int iSetCNB_MERR_MASK_cnb_api_e1_err_mask(unsigned int ucnb_api_e1_err_mask); +int iSetCNB_MERR_MASK_cnb_api_e0_err_mask(unsigned int ucnb_api_e0_err_mask); +int iSetCNB_MERR_MASK_cnb_api_token_err_mask(unsigned int ucnb_api_token_err_mask); +int iSetCNB_MERR_MASK_cnb_api_procotol_err_mask(unsigned int ucnb_api_procotol_err_mask); +int iSetRS_ND_PE_CRDT_sta(unsigned int usta); + + +#endif // RING_CNB_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_reg_offset.h new file mode 100644 index 000000000..82d954785 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_reg_offset.h @@ -0,0 +1,52 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : ring_cnb_reg_offset.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:46:44 Create file +// ****************************************************************************** + +#ifndef RING_CNB_REG_OFFSET_H +#define RING_CNB_REG_OFFSET_H + +/* ring_cnb_csr Base address of Module's Register */ +#define CSR_RING_CNB_CSR_BASE (0x3F00) + +/* **************************************************************************** */ +/* ring_cnb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_RING_CNB_CSR_CNB_VERSION_REG (CSR_RING_CNB_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_RING_CNB_CSR_CNB_TMOUT_CNT_THD_REG \ + (CSR_RING_CNB_CSR_BASE + 0x4) /* CNB timeout counter overflow threshold */ +#define CSR_RING_CNB_CSR_CNB_EMPTY_ADDR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x8) /* record the read error or write error API address */ +#define CSR_RING_CNB_CSR_CNB_API_ERR_FLIT_CNT_REG (CSR_RING_CNB_CSR_BASE + 0xC) /* error flit counter */ +#define CSR_RING_CNB_CSR_CNB_API_CRT_MSGE_CNT_REG (CSR_RING_CNB_CSR_BASE + 0x10) /* API correct message counter */ +#define CSR_RING_CNB_CSR_CNB_API_TX_MSGE_CNT_REG \ + (CSR_RING_CNB_CSR_BASE + 0x14) /* message counter for API transmit from CNB */ +#define CSR_RING_CNB_CSR_CNB_INT_VECTOR_REG (CSR_RING_CNB_CSR_BASE + 0x18) /* interrupt vector */ +#define CSR_RING_CNB_CSR_CNB_INT_REG (CSR_RING_CNB_CSR_BASE + 0x1C) /* interrupt data */ +#define CSR_RING_CNB_CSR_CNB_INT_MASK_REG (CSR_RING_CNB_CSR_BASE + 0x20) /* interrupt mask */ +#define CSR_RING_CNB_CSR_CNB_API_OP_CODE_ERR_REG (CSR_RING_CNB_CSR_BASE + 0x24) /* illegal op_code error */ +#define CSR_RING_CNB_CSR_CNB_CSR_CMD_PARITY_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x28) /* parity check error when the command is arrived at its destination CSR */ +#define CSR_RING_CNB_CSR_CNB_CSR_WR_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x2C) /* csr write error: the write address is empty or the data size is mismatch */ +#define CSR_RING_CNB_CSR_CNB_CSR_RDDAT_PARITY_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x30) /* read back data/op_info error: the read back data or op_info has parity error */ +#define CSR_RING_CNB_CSR_CNB_CSR_RD_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x34) /* csr read error: the read address is empty or the data size is mismatch */ +#define CSR_RING_CNB_CSR_CNB_MERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x38) /* MERR register for CNB error, Please refer to the member comments */ +#define CSR_RING_CNB_CSR_CNB_MERR_MASK_REG \ + (CSR_RING_CNB_CSR_BASE + 0x3C) /* mask control for errors list in CNB_MERR register */ +#define CSR_RING_CNB_CSR_RS_ND_PE_CRDT_REG \ + (CSR_RING_CNB_CSR_BASE + 0x40) /* record the credit cnt for RIGN packet eject port */ + +#endif // RING_CNB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_c_union_define.h new file mode 100644 index 000000000..b6b83a94c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_c_union_define.h @@ -0,0 +1,6441 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : sm_c_union_define.h +// Project line : IT Product Line +// Department : ICT Processor Chipset Development Department +// Version : V100 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// file +// ****************************************************************************** + +#ifndef SM_C_UNION_DEFINE_H +#define SM_C_UNION_DEFINE_H + +/* Define the union csr_smrt_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smrt_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_version_u; + +/* Define the union csr_smxr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_chk_en : 1; /* [0] */ + u32 smxr_cnt_sel : 2; /* [2:1] */ + u32 rsv_0 : 2; /* [4:3] */ + u32 tifoe_pi_copy_enb : 1; /* [5] */ + u32 roce_pi_copy_enb : 1; /* [6] */ + u32 iwarp_pi_copy_enb : 1; /* [7] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 mem_ret1n : 1; /* [16] */ + u32 rsv_1 : 1; /* [17] */ + u32 tifoe_pftch_ctl : 2; /* [19:18] */ + u32 tifoe_pftch_wqe_num : 2; /* [21:20] */ + u32 rp_sm_uncrt_err_clr : 1; /* [22] */ + u32 rp_sm_uncrt_err_mask : 7; /* [29:23] */ + u32 rp_crt_err_inj_req : 1; /* [30] */ + u32 rp_uncrt_err_inj_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg1_u; + +/* Define the union csr_smxr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_inst_id_mqm : 5; /* [4:0] */ + u32 rp_lb_mqm : 2; /* [6:5] */ + u32 rp_inst_id_qu_ld_wqe : 5; /* [11:7] */ + u32 rp_lb_qu_ld_wqe : 2; /* [13:12] */ + u32 rsv_2 : 1; /* [14] */ + u32 rp_fairness_en : 1; /* [15] */ + u32 rp_fairness_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg0_u; + +/* Define the union csr_smxt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dis_tx_eg : 1; /* [0] */ + u32 dis_tx_mc : 1; /* [1] */ + u32 dis_tx_eg_tl0 : 1; /* [2] */ + u32 dis_tx_eg_tl1 : 1; /* [3] */ + u32 reg_cap_ch_sel : 2; /* [5:4] */ + u32 cap_start : 1; /* [6] */ + u32 rsv_3 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cfg_u; + +/* Define the union csr_smxr_tm_grt01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tm_grt0 : 13; /* [12:0] */ + u32 rsv_4 : 3; /* [15:13] */ + u32 rp_tm_grt1 : 13; /* [28:16] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_tm_grt01_u; + +/* Define the union csr_smxr_tm_grt23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tm_grt2 : 13; /* [12:0] */ + u32 rsv_6 : 3; /* [15:13] */ + u32 rp_tm_grt3 : 13; /* [28:16] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_tm_grt23_u; + +/* Define the union csr_smrt_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_8 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_9 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_int_vector_u; + +/* Define the union csr_smrt_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_10 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_int_u; + +/* Define the union csr_smrt_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_11 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_int_mask_u; + +/* Define the union csr_smxr_req_mem_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_req_mem_crt_err_u; + +/* Define the union csr_smxr_req_mem_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_req_mem_uncrt_err_u; + +/* Define the union csr_smxr_miss_sop_eop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_miss_sop_eop_err_u; + +/* Define the union csr_smxr_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_indir_addr : 24; /* [23:0] */ + u32 smxr_indir_tab : 4; /* [27:24] */ + u32 smxr_indir_stat : 2; /* [29:28] */ + u32 smxr_indir_mode : 1; /* [30] */ + u32 smxr_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_indrect_ctrl_u; + +/* Define the union csr_smxr_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_indrect_timeout_u; + +/* Define the union csr_smxr_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_indrect_data_u; + +/* Define the union csr_smxt_cap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_tag_l_en : 1; /* [0] */ + u32 cap_tag_h_en : 1; /* [1] */ + u32 cap_thd_id_en : 1; /* [2] */ + u32 cap_dnid_en : 1; /* [3] */ + u32 flit0_127_123 : 5; /* [8:4] */ + u32 flit0_127_123_msk : 5; /* [13:9] */ + u32 rsv_12 : 17; /* [30:14] */ + u32 cap_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cap_cfg_u; + +/* Define the union csr_smxt_cap_field_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dst_tag_l : 12; /* [11:0] */ + u32 dst_tag_h : 6; /* [17:12] */ + u32 dst_thd_id : 7; /* [24:18] */ + u32 dst_nd_id : 6; /* [30:25] */ + u32 rsv_13 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cap_field_cfg_u; + +/* Define the union csr_smxt_cnt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_en_cnt_0 : 9; /* [8:0] */ + u32 rsv_14 : 7; /* [15:9] */ + u32 smxt_en_cnt_1 : 9; /* [24:16] */ + u32 rsv_15 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt_cfg0_u; + +/* Define the union csr_smxt_cnt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_en_cnt_2 : 9; /* [8:0] */ + u32 rsv_16 : 7; /* [15:9] */ + u32 smxt_en_cnt_3 : 9; /* [24:16] */ + u32 rsv_17 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt_cfg1_u; + +/* Define the union csr_smxt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt0_u; + +/* Define the union csr_smxt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt1_u; + +/* Define the union csr_smxt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt2_u; + +/* Define the union csr_smxt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt3_u; + +/* Define the union csr_smxt_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl1_ctp : 5; /* [4:0] */ + u32 tl0_ctp : 5; /* [9:5] */ + u32 ring_resp_ctp : 3; /* [12:10] */ + u32 ring_rqst_ctp : 3; /* [15:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_crdt_cnt_u; + +/* Define the union csr_smxt_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 if0_tl1_ctp : 4; /* [3:0] */ + u64 if0_tl0_ctp : 4; /* [7:4] */ + u64 if0_ring_resp_ctp : 4; /* [11:8] */ + u64 if0_ring_rqst_ctp : 4; /* [15:12] */ + u64 if1_tl1_ctp : 4; /* [19:16] */ + u64 if1_tl0_ctp : 4; /* [23:20] */ + u64 if1_ring_resp_ctp : 4; /* [27:24] */ + u64 if1_ring_rqst_ctp : 4; /* [31:28] */ + u64 mc_ctp : 3; /* [34:32] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smxt_fifo_depth0_u; + +/* Define the union csr_smxt_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 if2_tl1_ctp : 4; /* [3:0] */ + u32 if2_tl0_ctp : 4; /* [7:4] */ + u32 if2_ring_resp_ctp : 4; /* [11:8] */ + u32 if2_ring_rqst_ctp : 4; /* [15:12] */ + u32 if3_tl1_ctp : 4; /* [19:16] */ + u32 if3_tl0_ctp : 4; /* [23:20] */ + u32 if3_ring_resp_ctp : 4; /* [27:24] */ + u32 if3_ring_rqst_ctp : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_fifo_depth1_u; + +/* Define the union csr_tl0_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 l1_ctp : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 l2_ctp : 6; /* [21:16] */ + u32 rsv_20 : 2; /* [23:22] */ + u32 l3_ctp : 6; /* [29:24] */ + u32 rsv_21 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl0_q_dep_u; + +/* Define the union csr_tl1_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 6; /* [5:0] */ + u32 rsv_22 : 2; /* [7:6] */ + u32 l1_ctp : 6; /* [13:8] */ + u32 rsv_23 : 2; /* [15:14] */ + u32 l2_ctp : 6; /* [21:16] */ + u32 rsv_24 : 2; /* [23:22] */ + u32 l3_ctp : 6; /* [29:24] */ + u32 rsv_25 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl1_q_dep_u; + +/* Define the union csr_rqst_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 4; /* [3:0] */ + u32 l1_ctp : 4; /* [7:4] */ + u32 l2_ctp : 4; /* [11:8] */ + u32 l3_ctp : 4; /* [15:12] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rqst_q_dep_u; + +/* Define the union csr_rsp_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 4; /* [3:0] */ + u32 l1_ctp : 4; /* [7:4] */ + u32 l2_ctp : 4; /* [11:8] */ + u32 l3_ctp : 4; /* [15:12] */ + u32 l4_ctp : 4; /* [19:16] */ + u32 rsv_27 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsp_q_dep_u; + +/* Define the union csr_rqst_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm0_ctp : 5; /* [4:0] */ + u32 sm1_ctp : 5; /* [9:5] */ + u32 sm2_ctp : 5; /* [14:10] */ + u32 sm3_ctp : 5; /* [19:15] */ + u32 rsv_28 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rqst_crdt_cnt_u; + +/* Define the union csr_resp_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm0_ctp : 5; /* [4:0] */ + u32 sm1_ctp : 8; /* [12:5] */ + u32 sm2_ctp : 5; /* [17:13] */ + u32 sm3_ctp : 5; /* [22:18] */ + u32 smmc_ctp : 5; /* [27:23] */ + u32 rsv_29 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_resp_crdt_cnt_u; + +/* Define the union csr_smxr_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt0_u; + +/* Define the union csr_smxr_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt1_u; + +/* Define the union csr_smxr_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt2_u; + +/* Define the union csr_smxr_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt3_u; + +/* Define the union csr_smxt_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_cap_done : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_ctp_u; + +/* Define the union csr_smxr_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_virtio_core_inst_id : 6; /* [5:0] */ + u32 rsv_31 : 2; /* [7:6] */ + u32 rp_virtio_core_en : 1; /* [8] */ + u32 rsv_32 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg2_u; + +/* Define the union csr_smxr_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_virtio_csr_crdt_init_val : 5; /* [4:0] */ + u32 rsv_33 : 2; /* [6:5] */ + u32 rp_virtio_csr_crdt_init_en : 1; /* [7] */ + u32 rp_virtio_rqst_crdt_init_val : 4; /* [11:8] */ + u32 rsv_34 : 3; /* [14:12] */ + u32 rp_virtio_rqst_crdt_init_en : 1; /* [15] */ + u32 rp_virtio_resp_crdt_init_val : 8; /* [23:16] */ + u32 rp_virtio_resp_crdt_init_en : 1; /* [24] */ + u32 rsv_35 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg3_u; + +/* Define the union csr_cfg_mem_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus0_u; + +/* Define the union csr_cfg_mem_ctrl_bus1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus1_u; + +/* Define the union csr_cfg_mem_ctrl_bus2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus2_u; + +/* Define the union csr_cfg_mem_ctrl_bus3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus3_u; + +/* Define the union csr_cfg_mem_ctrl_bus4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus4 : 6; /* [5:0] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus4_u; + +/* Define the union csr_smxt_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_fake_vf_info_pos : 2; /* [1:0] */ + u32 rp_fake_vf_info_value : 2; /* [3:2] */ + u32 rp_fake_vf_info_en : 1; /* [4] */ + u32 rsv_37 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cfg2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smrt_version_u smrt_version; /* 0 */ + volatile csr_smxr_cfg1_u smxr_cfg1; /* 4 */ + volatile csr_smxr_cfg0_u smxr_cfg0; /* 8 */ + volatile csr_smxt_cfg_u smxt_cfg; /* C */ + volatile csr_smxr_tm_grt01_u smxr_tm_grt01; /* 10 */ + volatile csr_smxr_tm_grt23_u smxr_tm_grt23; /* 14 */ + volatile csr_smrt_int_vector_u smrt_int_vector; /* 18 */ + volatile csr_smrt_int_u smrt_int; /* 1C */ + volatile csr_smrt_int_mask_u smrt_int_mask; /* 20 */ + volatile csr_smxr_req_mem_crt_err_u smxr_req_mem_crt_err; /* 24 */ + volatile csr_smxr_req_mem_uncrt_err_u smxr_req_mem_uncrt_err; /* 28 */ + volatile csr_smxr_miss_sop_eop_err_u smxr_miss_sop_eop_err; /* 2C */ + volatile csr_smxr_indrect_ctrl_u smxr_indrect_ctrl; /* 30 */ + volatile csr_smxr_indrect_timeout_u smxr_indrect_timeout; /* 34 */ + volatile csr_smxr_indrect_data_u smxr_indrect_data; /* 38 */ + volatile csr_smxt_cap_cfg_u smxt_cap_cfg; /* 3C */ + volatile csr_smxt_cap_field_cfg_u smxt_cap_field_cfg; /* 40 */ + volatile csr_smxt_cnt_cfg0_u smxt_cnt_cfg0; /* 44 */ + volatile csr_smxt_cnt_cfg1_u smxt_cnt_cfg1; /* 48 */ + volatile csr_smxt_cnt0_u smxt_cnt0; /* 4C */ + volatile csr_smxt_cnt1_u smxt_cnt1; /* 50 */ + volatile csr_smxt_cnt2_u smxt_cnt2; /* 54 */ + volatile csr_smxt_cnt3_u smxt_cnt3; /* 58 */ + volatile csr_smxt_crdt_cnt_u smxt_crdt_cnt; /* 5C */ + volatile csr_smxt_fifo_depth0_u smxt_fifo_depth0; /* 60 */ + volatile csr_smxt_fifo_depth1_u smxt_fifo_depth1; /* 68 */ + volatile csr_tl0_q_dep_u tl0_q_dep; /* 6C */ + volatile csr_tl1_q_dep_u tl1_q_dep; /* 70 */ + volatile csr_rqst_q_dep_u rqst_q_dep; /* 74 */ + volatile csr_rsp_q_dep_u rsp_q_dep; /* 78 */ + volatile csr_rqst_crdt_cnt_u rqst_crdt_cnt; /* 7C */ + volatile csr_resp_crdt_cnt_u resp_crdt_cnt; /* 80 */ + volatile csr_smxr_cnt0_u smxr_cnt0; /* 84 */ + volatile csr_smxr_cnt1_u smxr_cnt1; /* 88 */ + volatile csr_smxr_cnt2_u smxr_cnt2; /* 8C */ + volatile csr_smxr_cnt3_u smxr_cnt3; /* 90 */ + volatile csr_smxt_ctp_u smxt_ctp; /* 94 */ + volatile csr_smxr_cfg2_u smxr_cfg2; /* 98 */ + volatile csr_smxr_cfg3_u smxr_cfg3; /* 9C */ + volatile csr_cfg_mem_ctrl_bus0_u cfg_mem_ctrl_bus0; /* A0 */ + volatile csr_cfg_mem_ctrl_bus1_u cfg_mem_ctrl_bus1; /* A4 */ + volatile csr_cfg_mem_ctrl_bus2_u cfg_mem_ctrl_bus2; /* A8 */ + volatile csr_cfg_mem_ctrl_bus3_u cfg_mem_ctrl_bus3; /* AC */ + volatile csr_cfg_mem_ctrl_bus4_u cfg_mem_ctrl_bus4; /* B0 */ + volatile csr_smxt_cfg2_u smxt_cfg2; /* B4 */ +} S_smrt_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smrt_csr */ +extern volatile S_smrt_csr_REGS_TYPE *gopsmrt_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMRT_VERSION_smrt_version(unsigned int usmrt_version); +int iSetSMXR_CFG1_mem_chk_en(unsigned int umem_chk_en); +int iSetSMXR_CFG1_smxr_cnt_sel(unsigned int usmxr_cnt_sel); +int iSetSMXR_CFG1_tifoe_pi_copy_enb(unsigned int utifoe_pi_copy_enb); +int iSetSMXR_CFG1_roce_pi_copy_enb(unsigned int uroce_pi_copy_enb); +int iSetSMXR_CFG1_iwarp_pi_copy_enb(unsigned int uiwarp_pi_copy_enb); +int iSetSMXR_CFG1_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMXR_CFG1_mem_ret1n(unsigned int umem_ret1n); +int iSetSMXR_CFG1_tifoe_pftch_ctl(unsigned int utifoe_pftch_ctl); +int iSetSMXR_CFG1_tifoe_pftch_wqe_num(unsigned int utifoe_pftch_wqe_num); +int iSetSMXR_CFG1_rp_sm_uncrt_err_clr(unsigned int urp_sm_uncrt_err_clr); +int iSetSMXR_CFG1_rp_sm_uncrt_err_mask(unsigned int urp_sm_uncrt_err_mask); +int iSetSMXR_CFG1_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMXR_CFG1_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMXR_CFG0_rp_inst_id_mqm(unsigned int urp_inst_id_mqm); +int iSetSMXR_CFG0_rp_lb_mqm(unsigned int urp_lb_mqm); +int iSetSMXR_CFG0_rp_inst_id_qu_ld_wqe(unsigned int urp_inst_id_qu_ld_wqe); +int iSetSMXR_CFG0_rp_lb_qu_ld_wqe(unsigned int urp_lb_qu_ld_wqe); +int iSetSMXR_CFG0_rp_fairness_en(unsigned int urp_fairness_en); +int iSetSMXR_CFG0_rp_fairness_num(unsigned int urp_fairness_num); +int iSetSMXT_CFG_dis_tx_eg(unsigned int udis_tx_eg); +int iSetSMXT_CFG_dis_tx_mc(unsigned int udis_tx_mc); +int iSetSMXT_CFG_dis_tx_eg_tl0(unsigned int udis_tx_eg_tl0); +int iSetSMXT_CFG_dis_tx_eg_tl1(unsigned int udis_tx_eg_tl1); +int iSetSMXT_CFG_reg_cap_ch_sel(unsigned int ureg_cap_ch_sel); +int iSetSMXT_CFG_cap_start(unsigned int ucap_start); +int iSetSMXR_TM_GRT01_rp_tm_grt0(unsigned int urp_tm_grt0); +int iSetSMXR_TM_GRT01_rp_tm_grt1(unsigned int urp_tm_grt1); +int iSetSMXR_TM_GRT23_rp_tm_grt2(unsigned int urp_tm_grt2); +int iSetSMXR_TM_GRT23_rp_tm_grt3(unsigned int urp_tm_grt3); +int iSetSMRT_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMRT_INT_VECTOR_enable(unsigned int uenable); +int iSetSMRT_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMRT_INT_int_data(unsigned int uint_data); +int iSetSMRT_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMRT_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMRT_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMXR_REQ_MEM_CRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMXR_REQ_MEM_CRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMXR_REQ_MEM_CRT_ERR_sticky(unsigned int usticky); +int iSetSMXR_REQ_MEM_UNCRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMXR_REQ_MEM_UNCRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMXR_REQ_MEM_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMXR_MISS_SOP_EOP_ERR_error_bit(unsigned int uerror_bit); +int iSetSMXR_MISS_SOP_EOP_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMXR_MISS_SOP_EOP_ERR_sticky(unsigned int usticky); +int iSetSMXR_INDRECT_CTRL_smxr_indir_addr(unsigned int usmxr_indir_addr); +int iSetSMXR_INDRECT_CTRL_smxr_indir_tab(unsigned int usmxr_indir_tab); +int iSetSMXR_INDRECT_CTRL_smxr_indir_stat(unsigned int usmxr_indir_stat); +int iSetSMXR_INDRECT_CTRL_smxr_indir_mode(unsigned int usmxr_indir_mode); +int iSetSMXR_INDRECT_CTRL_smxr_indir_vld(unsigned int usmxr_indir_vld); +int iSetSMXR_INDRECT_TIMEOUT_smxr_indir_timeout(unsigned int usmxr_indir_timeout); +int iSetSMXR_INDRECT_DATA_smxr_indir_data(unsigned int usmxr_indir_data); +int iSetSMXT_CAP_CFG_cap_tag_l_en(unsigned int ucap_tag_l_en); +int iSetSMXT_CAP_CFG_cap_tag_h_en(unsigned int ucap_tag_h_en); +int iSetSMXT_CAP_CFG_cap_thd_id_en(unsigned int ucap_thd_id_en); +int iSetSMXT_CAP_CFG_cap_dnid_en(unsigned int ucap_dnid_en); +int iSetSMXT_CAP_CFG_flit0_127_123(unsigned int uflit0_127_123); +int iSetSMXT_CAP_CFG_flit0_127_123_msk(unsigned int uflit0_127_123_msk); +int iSetSMXT_CAP_CFG_cap_mode(unsigned int ucap_mode); +int iSetSMXT_CAP_FIELD_CFG_dst_tag_l(unsigned int udst_tag_l); +int iSetSMXT_CAP_FIELD_CFG_dst_tag_h(unsigned int udst_tag_h); +int iSetSMXT_CAP_FIELD_CFG_dst_thd_id(unsigned int udst_thd_id); +int iSetSMXT_CAP_FIELD_CFG_dst_nd_id(unsigned int udst_nd_id); +int iSetSMXT_CNT_CFG0_smxt_en_cnt_0(unsigned int usmxt_en_cnt_0); +int iSetSMXT_CNT_CFG0_smxt_en_cnt_1(unsigned int usmxt_en_cnt_1); +int iSetSMXT_CNT_CFG1_smxt_en_cnt_2(unsigned int usmxt_en_cnt_2); +int iSetSMXT_CNT_CFG1_smxt_en_cnt_3(unsigned int usmxt_en_cnt_3); +int iSetSMXT_CNT0_smxt_cnt0(unsigned int usmxt_cnt0); +int iSetSMXT_CNT1_smxt_cnt1(unsigned int usmxt_cnt1); +int iSetSMXT_CNT2_smxt_cnt2(unsigned int usmxt_cnt2); +int iSetSMXT_CNT3_smxt_cnt3(unsigned int usmxt_cnt3); +int iSetSMXT_CRDT_CNT_tl1_ctp(unsigned int utl1_ctp); +int iSetSMXT_CRDT_CNT_tl0_ctp(unsigned int utl0_ctp); +int iSetSMXT_CRDT_CNT_ring_resp_ctp(unsigned int uring_resp_ctp); +int iSetSMXT_CRDT_CNT_ring_rqst_ctp(unsigned int uring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_tl1_ctp(unsigned int uif0_tl1_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_tl0_ctp(unsigned int uif0_tl0_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_ring_resp_ctp(unsigned int uif0_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_ring_rqst_ctp(unsigned int uif0_ring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_tl1_ctp(unsigned int uif1_tl1_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_tl0_ctp(unsigned int uif1_tl0_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_ring_resp_ctp(unsigned int uif1_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_ring_rqst_ctp(unsigned int uif1_ring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH0_mc_ctp(unsigned int umc_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_tl1_ctp(unsigned int uif2_tl1_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_tl0_ctp(unsigned int uif2_tl0_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_ring_resp_ctp(unsigned int uif2_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_ring_rqst_ctp(unsigned int uif2_ring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_tl1_ctp(unsigned int uif3_tl1_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_tl0_ctp(unsigned int uif3_tl0_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_ring_resp_ctp(unsigned int uif3_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_ring_rqst_ctp(unsigned int uif3_ring_rqst_ctp); +int iSetTL0_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetTL0_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetTL0_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetTL0_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetTL1_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetTL1_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetTL1_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetTL1_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetRQST_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetRQST_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetRQST_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetRQST_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetRSP_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetRSP_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetRSP_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetRSP_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetRSP_Q_DEP_l4_ctp(unsigned int ul4_ctp); +int iSetRQST_CRDT_CNT_sm0_ctp(unsigned int usm0_ctp); +int iSetRQST_CRDT_CNT_sm1_ctp(unsigned int usm1_ctp); +int iSetRQST_CRDT_CNT_sm2_ctp(unsigned int usm2_ctp); +int iSetRQST_CRDT_CNT_sm3_ctp(unsigned int usm3_ctp); +int iSetRESP_CRDT_CNT_sm0_ctp(unsigned int usm0_ctp); +int iSetRESP_CRDT_CNT_sm1_ctp(unsigned int usm1_ctp); +int iSetRESP_CRDT_CNT_sm2_ctp(unsigned int usm2_ctp); +int iSetRESP_CRDT_CNT_sm3_ctp(unsigned int usm3_ctp); +int iSetRESP_CRDT_CNT_smmc_ctp(unsigned int usmmc_ctp); +int iSetSMXR_CNT0_smxr_cnt0(unsigned int usmxr_cnt0); +int iSetSMXR_CNT1_smxr_cnt1(unsigned int usmxr_cnt1); +int iSetSMXR_CNT2_smxr_cnt2(unsigned int usmxr_cnt2); +int iSetSMXR_CNT3_smxr_cnt3(unsigned int usmxr_cnt3); +int iSetSMXT_CTP_api_cap_done(unsigned int uapi_cap_done); +int iSetSMXR_CFG2_rp_virtio_core_inst_id(unsigned int urp_virtio_core_inst_id); +int iSetSMXR_CFG2_rp_virtio_core_en(unsigned int urp_virtio_core_en); +int iSetSMXR_CFG3_rp_virtio_csr_crdt_init_val(unsigned int urp_virtio_csr_crdt_init_val); +int iSetSMXR_CFG3_rp_virtio_csr_crdt_init_en(unsigned int urp_virtio_csr_crdt_init_en); +int iSetSMXR_CFG3_rp_virtio_rqst_crdt_init_val(unsigned int urp_virtio_rqst_crdt_init_val); +int iSetSMXR_CFG3_rp_virtio_rqst_crdt_init_en(unsigned int urp_virtio_rqst_crdt_init_en); +int iSetSMXR_CFG3_rp_virtio_resp_crdt_init_val(unsigned int urp_virtio_resp_crdt_init_val); +int iSetSMXR_CFG3_rp_virtio_resp_crdt_init_en(unsigned int urp_virtio_resp_crdt_init_en); +int iSetCFG_MEM_CTRL_BUS0_cfg_mem_ctrl_bus0(unsigned int ucfg_mem_ctrl_bus0); +int iSetCFG_MEM_CTRL_BUS1_cfg_mem_ctrl_bus1(unsigned int ucfg_mem_ctrl_bus1); +int iSetCFG_MEM_CTRL_BUS2_cfg_mem_ctrl_bus2(unsigned int ucfg_mem_ctrl_bus2); +int iSetCFG_MEM_CTRL_BUS3_cfg_mem_ctrl_bus3(unsigned int ucfg_mem_ctrl_bus3); +int iSetCFG_MEM_CTRL_BUS4_cfg_mem_ctrl_bus4(unsigned int ucfg_mem_ctrl_bus4); +int iSetSMXT_CFG2_rp_fake_vf_info_pos(unsigned int urp_fake_vf_info_pos); +int iSetSMXT_CFG2_rp_fake_vf_info_value(unsigned int urp_fake_vf_info_value); +int iSetSMXT_CFG2_rp_fake_vf_info_en(unsigned int urp_fake_vf_info_en); + +/* Define the union csr_smir_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_version_u; + +/* Define the union csr_smir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dis_rx_rqst : 1; /* [0] */ + u32 dis_rx_resp : 1; /* [1] */ + u32 simple_hash : 1; /* [2] */ + u32 reg_cap_ch_sel : 1; /* [3] */ + u32 msb_thread_cfg : 1; /* [4] */ + u32 mem_chk_en : 1; /* [5] */ + u32 rp_l2nic_db_pseudo_api_en : 1; /* [6] */ + u32 rsv_0 : 9; /* [15:7] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 rp_crt_err_inj_req : 1; /* [24] */ + u32 rp_uncrt_err_inj_req : 1; /* [25] */ + u32 rsv_1 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cfg_u; + +/* Define the union csr_smir_hash_seed0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_hash_seed0_u; + +/* Define the union csr_smir_hash_seed1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_hash_seed1_u; + +/* Define the union csr_smir_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_int_vector_u; + +/* Define the union csr_smir_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_int_u; + +/* Define the union csr_smir_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_int_mask_u; + +/* Define the union csr_smir_err_spec_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_err_spec_th_u; + +/* Define the union csr_smir_req_msg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_req_msg_err_u; + +/* Define the union csr_smir_resp_msg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_resp_msg_err_u; + +/* Define the union csr_smir_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_mem_ecc_crt_err_u; + +/* Define the union csr_smir_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_mem_ecc_uncrt_err_u; + +/* Define the union csr_smir_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_indir_addr : 24; /* [23:0] */ + u32 smir_indir_tab : 4; /* [27:24] */ + u32 smir_indir_stat : 2; /* [29:28] */ + u32 smir_indir_mode : 1; /* [30] */ + u32 smir_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_indrect_ctrl_u; + +/* Define the union csr_smir_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_indrect_timeout_u; + +/* Define the union csr_smir_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_indrect_data_u; + +/* Define the union csr_smir_cap0_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stag_h : 7; /* [6:0] */ + u32 rsv_6 : 3; /* [9:7] */ + u32 src : 5; /* [14:10] */ + u32 s_inst_id : 6; /* [20:15] */ + u32 s_op_id : 6; /* [26:21] */ + u32 s_code : 2; /* [28:27] */ + u32 s_e0_bit : 1; /* [29] */ + u32 s_e1_bit : 1; /* [30] */ + u32 cap_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap0_cfg_u; + +/* Define the union csr_smir_cap1_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_111_96_msk : 16; /* [15:0] */ + u32 flit0_111_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap1_cfg_u; + +/* Define the union csr_smir_cap2_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap2_cfg_u; + +/* Define the union csr_smir_cap3_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap3_cfg_u; + +/* Define the union csr_smir_cap4_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap4_cfg_u; + +/* Define the union csr_smir_cap6_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stag_l : 12; /* [11:0] */ + u32 thread_id : 7; /* [18:12] */ + u32 cap_thread_id_en : 1; /* [19] */ + u32 flit0_95_0_msk : 6; /* [25:20] */ + u32 rsv_7 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap6_cfg_u; + +/* Define the union csr_smir_en_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_en_cnt_0 : 8; /* [7:0] */ + u32 smir_en_cnt_1 : 8; /* [15:8] */ + u32 smir_en_cnt_2 : 8; /* [23:16] */ + u32 cap_stag_h_en : 1; /* [24] */ + u32 cap_src_en : 1; /* [25] */ + u32 cap_inst_en : 1; /* [26] */ + u32 cap_op_en : 1; /* [27] */ + u32 cap_code_en : 1; /* [28] */ + u32 cap_err0_en : 1; /* [29] */ + u32 cap_err1_en : 1; /* [30] */ + u32 cap_stag_l_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_en_cnt_u; + +/* Define the union csr_smir_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cnt0_u; + +/* Define the union csr_smir_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cnt1_u; + +/* Define the union csr_smir_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cnt2_u; + +/* Define the union csr_smir_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eg0_ctp : 3; /* [2:0] */ + u32 resp_ctp : 3; /* [5:3] */ + u32 rqst_ctp : 3; /* [8:6] */ + u32 smmc_ctp : 5; /* [13:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_crdt_cnt_u; + +/* Define the union csr_smir_cap_flit0_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit0_data0_u; + +/* Define the union csr_smir_cap_flit0_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit0_data1_u; + +/* Define the union csr_smir_cap_flit1_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit1_data0_u; + +/* Define the union csr_smir_cap_flit1_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit1_data1_u; + +/* Define the union csr_smir_cap_flit2_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit2_data0_u; + +/* Define the union csr_smir_cap_flit2_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit2_data1_u; + +/* Define the union csr_smir_cap_flit3_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit3_data0_u; + +/* Define the union csr_smir_cap_flit3_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit3_data1_u; + +/* Define the union csr_smir_cap_flit4_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit4_data0_u; + +/* Define the union csr_smir_cap_flit4_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit4_data1_u; + +/* Define the union csr_smir_cap_flit5_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit5_data0_u; + +/* Define the union csr_smir_cap_flit5_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit5_data1_u; + +/* Define the union csr_smir_cap_flit0_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit0_data2_u; + +/* Define the union csr_smir_cap_flit1_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit1_data2_u; + +/* Define the union csr_smir_cap_flit2_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit2_data2_u; + +/* Define the union csr_smir_cap_flit3_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit3_data2_u; + +/* Define the union csr_smir_cap_flit4_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit4_data2_u; + +/* Define the union csr_smir_cap_flit5_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit5_data2_u; + +/* Define the union csr_smir_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_l2nic_pf_start_idx : 4; /* [3:0] */ + u32 rp_l2nic_pf_end_idx : 4; /* [7:4] */ + u32 rp_l2nic_lb_md : 2; /* [9:8] */ + u32 rp_l2nic_cmdq_md : 2; /* [11:10] */ + u32 rp_l2nic_flexible_md : 1; /* [12] */ + u32 rsv_8 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cfg1_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smir_version_u smir_version; /* 0 */ + volatile csr_smir_cfg_u smir_cfg; /* 4 */ + volatile csr_smir_hash_seed0_u smir_hash_seed0; /* 8 */ + volatile csr_smir_hash_seed1_u smir_hash_seed1; /* C */ + volatile csr_smir_int_vector_u smir_int_vector; /* 10 */ + volatile csr_smir_int_u smir_int; /* 14 */ + volatile csr_smir_int_mask_u smir_int_mask; /* 18 */ + volatile csr_smir_err_spec_th_u smir_err_spec_th; /* 1C */ + volatile csr_smir_req_msg_err_u smir_req_msg_err; /* 20 */ + volatile csr_smir_resp_msg_err_u smir_resp_msg_err; /* 24 */ + volatile csr_smir_mem_ecc_crt_err_u smir_mem_ecc_crt_err; /* 28 */ + volatile csr_smir_mem_ecc_uncrt_err_u smir_mem_ecc_uncrt_err; /* 2C */ + volatile csr_smir_indrect_ctrl_u smir_indrect_ctrl; /* 30 */ + volatile csr_smir_indrect_timeout_u smir_indrect_timeout; /* 34 */ + volatile csr_smir_indrect_data_u smir_indrect_data; /* 38 */ + volatile csr_smir_cap0_cfg_u smir_cap0_cfg; /* 3C */ + volatile csr_smir_cap1_cfg_u smir_cap1_cfg; /* 40 */ + volatile csr_smir_cap2_cfg_u smir_cap2_cfg; /* 44 */ + volatile csr_smir_cap3_cfg_u smir_cap3_cfg; /* 48 */ + volatile csr_smir_cap4_cfg_u smir_cap4_cfg; /* 4C */ + volatile csr_smir_cap6_cfg_u smir_cap6_cfg; /* 50 */ + volatile csr_smir_en_cnt_u smir_en_cnt; /* 54 */ + volatile csr_smir_cnt0_u smir_cnt0; /* 58 */ + volatile csr_smir_cnt1_u smir_cnt1; /* 5C */ + volatile csr_smir_cnt2_u smir_cnt2; /* 60 */ + volatile csr_smir_crdt_cnt_u smir_crdt_cnt; /* 64 */ + volatile csr_smir_cap_flit0_data0_u smir_cap_flit0_data0; /* 68 */ + volatile csr_smir_cap_flit0_data1_u smir_cap_flit0_data1; /* 70 */ + volatile csr_smir_cap_flit1_data0_u smir_cap_flit1_data0; /* 78 */ + volatile csr_smir_cap_flit1_data1_u smir_cap_flit1_data1; /* 80 */ + volatile csr_smir_cap_flit2_data0_u smir_cap_flit2_data0; /* 88 */ + volatile csr_smir_cap_flit2_data1_u smir_cap_flit2_data1; /* 90 */ + volatile csr_smir_cap_flit3_data0_u smir_cap_flit3_data0; /* 98 */ + volatile csr_smir_cap_flit3_data1_u smir_cap_flit3_data1; /* A0 */ + volatile csr_smir_cap_flit4_data0_u smir_cap_flit4_data0; /* A8 */ + volatile csr_smir_cap_flit4_data1_u smir_cap_flit4_data1; /* B0 */ + volatile csr_smir_cap_flit5_data0_u smir_cap_flit5_data0; /* B8 */ + volatile csr_smir_cap_flit5_data1_u smir_cap_flit5_data1; /* C0 */ + volatile csr_smir_cap_flit0_data2_u smir_cap_flit0_data2; /* C8 */ + volatile csr_smir_cap_flit1_data2_u smir_cap_flit1_data2; /* CC */ + volatile csr_smir_cap_flit2_data2_u smir_cap_flit2_data2; /* D0 */ + volatile csr_smir_cap_flit3_data2_u smir_cap_flit3_data2; /* D4 */ + volatile csr_smir_cap_flit4_data2_u smir_cap_flit4_data2; /* D8 */ + volatile csr_smir_cap_flit5_data2_u smir_cap_flit5_data2; /* DC */ + volatile csr_smir_cfg1_u smir_cfg1; /* E0 */ +} S_smir_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smir_csr */ +extern volatile S_smir_csr_REGS_TYPE *gopsmir_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMIR_VERSION_smir_version(unsigned int usmir_version); +int iSetSMIR_CFG_dis_rx_rqst(unsigned int udis_rx_rqst); +int iSetSMIR_CFG_dis_rx_resp(unsigned int udis_rx_resp); +int iSetSMIR_CFG_simple_hash(unsigned int usimple_hash); +int iSetSMIR_CFG_reg_cap_ch_sel(unsigned int ureg_cap_ch_sel); +int iSetSMIR_CFG_msb_thread_cfg(unsigned int umsb_thread_cfg); +int iSetSMIR_CFG_mem_chk_en(unsigned int umem_chk_en); +int iSetSMIR_CFG_rp_l2nic_db_pseudo_api_en(unsigned int urp_l2nic_db_pseudo_api_en); +int iSetSMIR_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMIR_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMIR_CFG_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMIR_CFG_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMIR_HASH_SEED0_hash_seed_cfg0(unsigned int uhash_seed_cfg0); +int iSetSMIR_HASH_SEED1_hash_seed_cfg1(unsigned int uhash_seed_cfg1); +int iSetSMIR_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMIR_INT_VECTOR_enable(unsigned int uenable); +int iSetSMIR_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMIR_INT_int_data(unsigned int uint_data); +int iSetSMIR_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIR_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMIR_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIR_ERR_SPEC_TH_err(unsigned int uerr); +int iSetSMIR_ERR_SPEC_TH_multi_err(unsigned int umulti_err); +int iSetSMIR_ERR_SPEC_TH_sticky(unsigned int usticky); +int iSetSMIR_REQ_MSG_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_REQ_MSG_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_REQ_MSG_ERR_sticky(unsigned int usticky); +int iSetSMIR_RESP_MSG_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_RESP_MSG_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_RESP_MSG_ERR_sticky(unsigned int usticky); +int iSetSMIR_MEM_ECC_CRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_MEM_ECC_CRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMIR_MEM_ECC_UNCRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_MEM_ECC_UNCRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMIR_INDRECT_CTRL_smir_indir_addr(unsigned int usmir_indir_addr); +int iSetSMIR_INDRECT_CTRL_smir_indir_tab(unsigned int usmir_indir_tab); +int iSetSMIR_INDRECT_CTRL_smir_indir_stat(unsigned int usmir_indir_stat); +int iSetSMIR_INDRECT_CTRL_smir_indir_mode(unsigned int usmir_indir_mode); +int iSetSMIR_INDRECT_CTRL_smir_indir_vld(unsigned int usmir_indir_vld); +int iSetSMIR_INDRECT_TIMEOUT_smir_indir_timeout(unsigned int usmir_indir_timeout); +int iSetSMIR_INDRECT_DATA_smir_indir_data(unsigned int usmir_indir_data); +int iSetSMIR_CAP0_CFG_stag_h(unsigned int ustag_h); +int iSetSMIR_CAP0_CFG_src(unsigned int usrc); +int iSetSMIR_CAP0_CFG_s_inst_id(unsigned int us_inst_id); +int iSetSMIR_CAP0_CFG_s_op_id(unsigned int us_op_id); +int iSetSMIR_CAP0_CFG_s_code(unsigned int us_code); +int iSetSMIR_CAP0_CFG_s_e0_bit(unsigned int us_e0_bit); +int iSetSMIR_CAP0_CFG_s_e1_bit(unsigned int us_e1_bit); +int iSetSMIR_CAP0_CFG_cap_mode(unsigned int ucap_mode); +int iSetSMIR_CAP1_CFG_flit0_111_96_msk(unsigned int uflit0_111_96_msk); +int iSetSMIR_CAP1_CFG_flit0_111_96(unsigned int uflit0_111_96); +int iSetSMIR_CAP2_CFG_flit0_95_64(unsigned int uflit0_95_64); +int iSetSMIR_CAP3_CFG_flit0_63_32(unsigned int uflit0_63_32); +int iSetSMIR_CAP4_CFG_flit0_31_0(unsigned int uflit0_31_0); +int iSetSMIR_CAP6_CFG_stag_l(unsigned int ustag_l); +int iSetSMIR_CAP6_CFG_thread_id(unsigned int uthread_id); +int iSetSMIR_CAP6_CFG_cap_thread_id_en(unsigned int ucap_thread_id_en); +int iSetSMIR_CAP6_CFG_flit0_95_0_msk(unsigned int uflit0_95_0_msk); +int iSetSMIR_EN_CNT_smir_en_cnt_0(unsigned int usmir_en_cnt_0); +int iSetSMIR_EN_CNT_smir_en_cnt_1(unsigned int usmir_en_cnt_1); +int iSetSMIR_EN_CNT_smir_en_cnt_2(unsigned int usmir_en_cnt_2); +int iSetSMIR_EN_CNT_cap_stag_h_en(unsigned int ucap_stag_h_en); +int iSetSMIR_EN_CNT_cap_src_en(unsigned int ucap_src_en); +int iSetSMIR_EN_CNT_cap_inst_en(unsigned int ucap_inst_en); +int iSetSMIR_EN_CNT_cap_op_en(unsigned int ucap_op_en); +int iSetSMIR_EN_CNT_cap_code_en(unsigned int ucap_code_en); +int iSetSMIR_EN_CNT_cap_err0_en(unsigned int ucap_err0_en); +int iSetSMIR_EN_CNT_cap_err1_en(unsigned int ucap_err1_en); +int iSetSMIR_EN_CNT_cap_stag_l_en(unsigned int ucap_stag_l_en); +int iSetSMIR_CNT0_smir_cnt0(unsigned int usmir_cnt0); +int iSetSMIR_CNT1_smir_cnt1(unsigned int usmir_cnt1); +int iSetSMIR_CNT2_smir_cnt2(unsigned int usmir_cnt2); +int iSetSMIR_CRDT_CNT_eg0_ctp(unsigned int ueg0_ctp); +int iSetSMIR_CRDT_CNT_resp_ctp(unsigned int uresp_ctp); +int iSetSMIR_CRDT_CNT_rqst_ctp(unsigned int urqst_ctp); +int iSetSMIR_CRDT_CNT_smmc_ctp(unsigned int usmmc_ctp); +int iSetSMIR_CAP_FLIT0_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT0_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT0_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT0_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT1_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT1_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT1_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT1_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT2_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT2_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT2_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT2_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT3_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT3_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT3_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT3_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT4_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT4_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT4_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT4_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT5_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT5_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT5_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT5_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT0_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT0_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT1_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT1_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT2_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT2_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT3_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT3_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT4_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT4_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT5_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT5_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CFG1_rp_l2nic_pf_start_idx(unsigned int urp_l2nic_pf_start_idx); +int iSetSMIR_CFG1_rp_l2nic_pf_end_idx(unsigned int urp_l2nic_pf_end_idx); +int iSetSMIR_CFG1_rp_l2nic_lb_md(unsigned int urp_l2nic_lb_md); +int iSetSMIR_CFG1_rp_l2nic_cmdq_md(unsigned int urp_l2nic_cmdq_md); +int iSetSMIR_CFG1_rp_l2nic_flexible_md(unsigned int urp_l2nic_flexible_md); + +/* Define the union csr_smeg0_abuf0_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf0_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf0_version_u; + +/* Define the union csr_sm_abuf_th_grw_wm_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_0 : 30; /* [29:0] */ + u32 rsv_0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_0_u; + +/* Define the union csr_sm_abuf_th_grw_wm_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_1 : 30; /* [29:0] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_1_u; + +/* Define the union csr_sm_abuf_th_grw_wm_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_2 : 30; /* [29:0] */ + u32 rsv_2 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_2_u; + +/* Define the union csr_sm_abuf_th_grw_wm_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_3 : 30; /* [29:0] */ + u32 rsv_3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_3_u; + +/* Define the union csr_sm_abuf_th_grw_wm_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_4 : 30; /* [29:0] */ + u32 rsv_4 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_4_u; + +/* Define the union csr_sm_abuf_th_grw_wm_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_5 : 30; /* [29:0] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_5_u; + +/* Define the union csr_sm_abuf_th_grw_wm_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_6 : 12; /* [11:0] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_6_u; + +/* Define the union csr_sm_abuf_th_shk_wm_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_0 : 30; /* [29:0] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_0_u; + +/* Define the union csr_sm_abuf_th_shk_wm_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_1 : 30; /* [29:0] */ + u32 rsv_8 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_1_u; + +/* Define the union csr_sm_abuf_th_shk_wm_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_2 : 30; /* [29:0] */ + u32 rsv_9 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_2_u; + +/* Define the union csr_sm_abuf_th_shk_wm_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_3 : 30; /* [29:0] */ + u32 rsv_10 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_3_u; + +/* Define the union csr_sm_abuf_th_shk_wm_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_4 : 30; /* [29:0] */ + u32 rsv_11 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_4_u; + +/* Define the union csr_sm_abuf_th_shk_wm_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_5 : 30; /* [29:0] */ + u32 rsv_12 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_5_u; + +/* Define the union csr_sm_abuf_th_shk_wm_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_6 : 12; /* [11:0] */ + u32 rsv_13 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_6_u; + +/* Define the union csr_sm_abuf_flrc_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flid_torc : 5; /* [4:0] */ + u32 rsv_14 : 3; /* [7:5] */ + u32 en_rclm : 1; /* [8] */ + u32 stop_rclm : 1; /* [9] */ + u32 rsv_15 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_attr_u; + +/* Define the union csr_sm_abuf_flrc_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_rclm : 28; /* [27:0] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_num_u; + +/* Define the union csr_sm_abuf_flrc_bound_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_flrc_bound_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_bound_u_u; + +/* Define the union csr_sm_abuf_flrc_bound_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_flrc_bound_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_bound_l_u; + +/* Define the union csr_sm_abuf_pf_lifo_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_pf_lifo_clr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_pf_lifo_clr_u; + +/* Define the union csr_sm_abuf_mem_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lifo_pberr_gen : 1; /* [0] */ + u32 info_pberr_gen : 1; /* [1] */ + u32 ibuf_pberr_gen : 1; /* [2] */ + u32 ireq_pberr_gen : 1; /* [3] */ + u32 pb_chk_en : 1; /* [4] */ + u32 rsv_17 : 3; /* [7:5] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 tp_ram_tmod : 8; /* [23:16] */ + u32 rsv_18 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_mem_cfg_u; + +/* Define the union csr_sm_abuf_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_19 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_20 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_int_vector_u; + +/* Define the union csr_sm_abuf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_21 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_int_u; + +/* Define the union csr_sm_abuf_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 6; /* [5:0] */ + u32 rsv_22 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_int_mask_u; + +/* Define the union csr_sm_abuf_pberr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_pberr_u; + +/* Define the union csr_sm_abuf_fl_uflow_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_fl_uflow_err_u; + +/* Define the union csr_sm_abuf_fl_oflow_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_fl_oflow_err_u; + +/* Define the union csr_sm_abuf_fl_tail_miss_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_fl_tail_miss_err_u; + +/* Define the union csr_smeg0_abuf_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf_indir_addr : 24; /* [23:0] */ + u32 smeg0_abuf_indir_tab : 4; /* [27:24] */ + u32 smeg0_abuf_indir_stat : 2; /* [29:28] */ + u32 smeg0_abuf_indir_mode : 1; /* [30] */ + u32 smeg0_abuf_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf_indrect_ctrl_u; + +/* Define the union csr_smeg0_abuf_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf_indrect_timeout_u; + +/* Define the union csr_smeg0_abuf_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf_indrect_data_u; + +/* Define the union csr_sm_abuf_dis_alloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_dis_alloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_dis_alloc_u; + +/* Define the union csr_sm_abuf_dis_de_alloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_dis_de_alloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_dis_de_alloc_u; + +/* Define the union csr_sm_abuf_flrc_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 done_rclm : 1; /* [0] */ + u32 rlist_cleaning : 1; /* [1] */ + u32 wlist_cleaning : 1; /* [2] */ + u32 rsv_23 : 1; /* [3] */ + u32 ctp : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_st_u; + +/* Define the union csr_sm_abuf_empty_fl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_empty_fl_u; + +/* Define the union csr_sm_abuf_full_fl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_full_fl_u; + +/* Define the union csr_sm_abuf_st_wm_grow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_st_wm_grow_u; + +/* Define the union csr_sm_abuf_st_wm_shrink_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_st_wm_shrink_u; + +/* Define the union csr_sm_abuf_cnt_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_src_sel : 5; /* [4:0] */ + u32 cnt0_event_sel : 3; /* [7:5] */ + u32 cnt1_src_sel : 5; /* [12:8] */ + u32 cnt1_event_sel : 3; /* [15:13] */ + u32 cnt2_src_sel : 5; /* [20:16] */ + u32 cnt2_event_sel : 3; /* [23:21] */ + u32 cnt3_src_sel : 5; /* [28:24] */ + u32 cnt3_event_sel : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_cnt_sel0_u; + +/* Define the union csr_sm_abuf_cnt_sel1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt4_src_sel : 5; /* [4:0] */ + u32 cnt4_event_sel : 3; /* [7:5] */ + u32 cnt5_src_sel : 5; /* [12:8] */ + u32 cnt5_event_sel : 3; /* [15:13] */ + u32 cnt_enable : 6; /* [21:16] */ + u32 rsv_24 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_cnt_sel1_u; + +/* Define the union csr_sm_abuf_counter0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter0_u; + +/* Define the union csr_sm_abuf_counter1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter1_u; + +/* Define the union csr_sm_abuf_counter2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter2_u; + +/* Define the union csr_sm_abuf_counter3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter3_u; + +/* Define the union csr_sm_abuf_counter4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter4_u; + +/* Define the union csr_sm_abuf_counter5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter5_u; + +/* Define the union csr_sm_abuf_pfetch_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_pfetch_flag_u; + +/* Define the union csr_sm_abuf_ireq_list_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ireq_list_sta_u; + +/* Define the union csr_sm_abuf_tail_miss0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_tail_miss0_u; + +/* Define the union csr_sm_abuf_tail_miss1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_tail_miss1_u; + +/* Define the union csr_sm_abuf_cnt_lifo_pfetch_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_cnt_lifo_pfetch_0_u; + +/* Define the union csr_sm_abuf_cnt_lifo_pfetch_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_cnt_lifo_pfetch_1_u; + +/* Define the union csr_sm_abuf_cnt_lifo_pfetch_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_cnt_lifo_pfetch_2_u; + +/* Define the union csr_sm_abuf_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 list_info_1b_ecc_inj_en : 1; /* [0] */ + u32 list_info_2b_ecc_inj_en : 1; /* [1] */ + u32 list_info_ecc_en : 1; /* [2] */ + u32 rsv_25 : 1; /* [3] */ + u32 lifo_1b_ecc_inj_en : 1; /* [4] */ + u32 lifo_2b_ecc_inj_en : 1; /* [5] */ + u32 lifo_ecc_en : 1; /* [6] */ + u32 rsv_26 : 1; /* [7] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ecc_cfg_u; + +/* Define the union csr_sm_abuf_ecc_1b_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ecc_1b_err_int_u; + +/* Define the union csr_sm_abuf_ecc_2b_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ecc_2b_err_int_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg0_abuf0_version_u smeg0_abuf0_version; /* 0 */ + volatile csr_sm_abuf_th_grw_wm_0_u sm_abuf_th_grw_wm_0; /* 4 */ + volatile csr_sm_abuf_th_grw_wm_1_u sm_abuf_th_grw_wm_1; /* 8 */ + volatile csr_sm_abuf_th_grw_wm_2_u sm_abuf_th_grw_wm_2; /* C */ + volatile csr_sm_abuf_th_grw_wm_3_u sm_abuf_th_grw_wm_3; /* 10 */ + volatile csr_sm_abuf_th_grw_wm_4_u sm_abuf_th_grw_wm_4; /* 14 */ + volatile csr_sm_abuf_th_grw_wm_5_u sm_abuf_th_grw_wm_5; /* 18 */ + volatile csr_sm_abuf_th_grw_wm_6_u sm_abuf_th_grw_wm_6; /* 1C */ + volatile csr_sm_abuf_th_shk_wm_0_u sm_abuf_th_shk_wm_0; /* 20 */ + volatile csr_sm_abuf_th_shk_wm_1_u sm_abuf_th_shk_wm_1; /* 24 */ + volatile csr_sm_abuf_th_shk_wm_2_u sm_abuf_th_shk_wm_2; /* 28 */ + volatile csr_sm_abuf_th_shk_wm_3_u sm_abuf_th_shk_wm_3; /* 2C */ + volatile csr_sm_abuf_th_shk_wm_4_u sm_abuf_th_shk_wm_4; /* 30 */ + volatile csr_sm_abuf_th_shk_wm_5_u sm_abuf_th_shk_wm_5; /* 34 */ + volatile csr_sm_abuf_th_shk_wm_6_u sm_abuf_th_shk_wm_6; /* 38 */ + volatile csr_sm_abuf_flrc_attr_u sm_abuf_flrc_attr; /* 3C */ + volatile csr_sm_abuf_flrc_num_u sm_abuf_flrc_num; /* 40 */ + volatile csr_sm_abuf_flrc_bound_u_u sm_abuf_flrc_bound_u; /* 44 */ + volatile csr_sm_abuf_flrc_bound_l_u sm_abuf_flrc_bound_l; /* 48 */ + volatile csr_sm_abuf_pf_lifo_clr_u sm_abuf_pf_lifo_clr; /* 4C */ + volatile csr_sm_abuf_mem_cfg_u sm_abuf_mem_cfg; /* 50 */ + volatile csr_sm_abuf_int_vector_u sm_abuf_int_vector; /* 54 */ + volatile csr_sm_abuf_int_u sm_abuf_int; /* 58 */ + volatile csr_sm_abuf_int_mask_u sm_abuf_int_mask; /* 5C */ + volatile csr_sm_abuf_pberr_u sm_abuf_pberr; /* 60 */ + volatile csr_sm_abuf_fl_uflow_err_u sm_abuf_fl_uflow_err; /* 64 */ + volatile csr_sm_abuf_fl_oflow_err_u sm_abuf_fl_oflow_err; /* 68 */ + volatile csr_sm_abuf_fl_tail_miss_err_u sm_abuf_fl_tail_miss_err; /* 6C */ + volatile csr_smeg0_abuf_indrect_ctrl_u smeg0_abuf_indrect_ctrl; /* 70 */ + volatile csr_smeg0_abuf_indrect_timeout_u smeg0_abuf_indrect_timeout; /* 74 */ + volatile csr_smeg0_abuf_indrect_data_u smeg0_abuf_indrect_data; /* 78 */ + volatile csr_sm_abuf_dis_alloc_u sm_abuf_dis_alloc; /* 7C */ + volatile csr_sm_abuf_dis_de_alloc_u sm_abuf_dis_de_alloc; /* 80 */ + volatile csr_sm_abuf_flrc_st_u sm_abuf_flrc_st; /* 84 */ + volatile csr_sm_abuf_empty_fl_u sm_abuf_empty_fl; /* 88 */ + volatile csr_sm_abuf_full_fl_u sm_abuf_full_fl; /* 8C */ + volatile csr_sm_abuf_st_wm_grow_u sm_abuf_st_wm_grow; /* 90 */ + volatile csr_sm_abuf_st_wm_shrink_u sm_abuf_st_wm_shrink; /* 94 */ + volatile csr_sm_abuf_cnt_sel0_u sm_abuf_cnt_sel0; /* 98 */ + volatile csr_sm_abuf_cnt_sel1_u sm_abuf_cnt_sel1; /* 9C */ + volatile csr_sm_abuf_counter0_u sm_abuf_counter0; /* A0 */ + volatile csr_sm_abuf_counter1_u sm_abuf_counter1; /* A4 */ + volatile csr_sm_abuf_counter2_u sm_abuf_counter2; /* A8 */ + volatile csr_sm_abuf_counter3_u sm_abuf_counter3; /* AC */ + volatile csr_sm_abuf_counter4_u sm_abuf_counter4; /* B0 */ + volatile csr_sm_abuf_counter5_u sm_abuf_counter5; /* B4 */ + volatile csr_sm_abuf_pfetch_flag_u sm_abuf_pfetch_flag; /* B8 */ + volatile csr_sm_abuf_ireq_list_sta_u sm_abuf_ireq_list_sta; /* BC */ + volatile csr_sm_abuf_tail_miss0_u sm_abuf_tail_miss0; /* C0 */ + volatile csr_sm_abuf_tail_miss1_u sm_abuf_tail_miss1; /* C8 */ + volatile csr_sm_abuf_cnt_lifo_pfetch_0_u sm_abuf_cnt_lifo_pfetch_0; /* D0 */ + volatile csr_sm_abuf_cnt_lifo_pfetch_1_u sm_abuf_cnt_lifo_pfetch_1; /* D8 */ + volatile csr_sm_abuf_cnt_lifo_pfetch_2_u sm_abuf_cnt_lifo_pfetch_2; /* E0 */ + volatile csr_sm_abuf_ecc_cfg_u sm_abuf_ecc_cfg; /* E4 */ + volatile csr_sm_abuf_ecc_1b_err_int_u sm_abuf_ecc_1b_err_int; /* E8 */ + volatile csr_sm_abuf_ecc_2b_err_int_u sm_abuf_ecc_2b_err_int; /* EC */ +} S_smeg0_abuf0_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg0_abuf0_csr */ +extern volatile S_smeg0_abuf0_csr_REGS_TYPE *gopsmeg0_abuf0_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG0_ABUF0_VERSION_smeg0_abuf0_version(unsigned int usmeg0_abuf0_version); +int iSetSM_ABUF_TH_GRW_WM_0_th_grow_0(unsigned int uth_grow_0); +int iSetSM_ABUF_TH_GRW_WM_1_th_grow_1(unsigned int uth_grow_1); +int iSetSM_ABUF_TH_GRW_WM_2_th_grow_2(unsigned int uth_grow_2); +int iSetSM_ABUF_TH_GRW_WM_3_th_grow_3(unsigned int uth_grow_3); +int iSetSM_ABUF_TH_GRW_WM_4_th_grow_4(unsigned int uth_grow_4); +int iSetSM_ABUF_TH_GRW_WM_5_th_grow_5(unsigned int uth_grow_5); +int iSetSM_ABUF_TH_GRW_WM_6_th_grow_6(unsigned int uth_grow_6); +int iSetSM_ABUF_TH_SHK_WM_0_th_shrink_0(unsigned int uth_shrink_0); +int iSetSM_ABUF_TH_SHK_WM_1_th_shrink_1(unsigned int uth_shrink_1); +int iSetSM_ABUF_TH_SHK_WM_2_th_shrink_2(unsigned int uth_shrink_2); +int iSetSM_ABUF_TH_SHK_WM_3_th_shrink_3(unsigned int uth_shrink_3); +int iSetSM_ABUF_TH_SHK_WM_4_th_shrink_4(unsigned int uth_shrink_4); +int iSetSM_ABUF_TH_SHK_WM_5_th_shrink_5(unsigned int uth_shrink_5); +int iSetSM_ABUF_TH_SHK_WM_6_th_shrink_6(unsigned int uth_shrink_6); +int iSetSM_ABUF_FLRC_ATTR_flid_torc(unsigned int uflid_torc); +int iSetSM_ABUF_FLRC_ATTR_en_rclm(unsigned int uen_rclm); +int iSetSM_ABUF_FLRC_ATTR_stop_rclm(unsigned int ustop_rclm); +int iSetSM_ABUF_FLRC_NUM_num_rclm(unsigned int unum_rclm); +int iSetSM_ABUF_FLRC_BOUND_U_sm_abuf_flrc_bound_u(unsigned int usm_abuf_flrc_bound_u); +int iSetSM_ABUF_FLRC_BOUND_L_sm_abuf_flrc_bound_l(unsigned int usm_abuf_flrc_bound_l); +int iSetSM_ABUF_PF_LIFO_CLR_sm_abuf_pf_lifo_clr(unsigned int usm_abuf_pf_lifo_clr); +int iSetSM_ABUF_MEM_CFG_lifo_pberr_gen(unsigned int ulifo_pberr_gen); +int iSetSM_ABUF_MEM_CFG_info_pberr_gen(unsigned int uinfo_pberr_gen); +int iSetSM_ABUF_MEM_CFG_ibuf_pberr_gen(unsigned int uibuf_pberr_gen); +int iSetSM_ABUF_MEM_CFG_ireq_pberr_gen(unsigned int uireq_pberr_gen); +int iSetSM_ABUF_MEM_CFG_pb_chk_en(unsigned int upb_chk_en); +int iSetSM_ABUF_MEM_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSM_ABUF_MEM_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSM_ABUF_MEM_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSM_ABUF_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSM_ABUF_INT_VECTOR_enable(unsigned int uenable); +int iSetSM_ABUF_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSM_ABUF_INT_int_data(unsigned int uint_data); +int iSetSM_ABUF_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSM_ABUF_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSM_ABUF_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSM_ABUF_PBERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_PBERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_PBERR_sticky(unsigned int usticky); +int iSetSM_ABUF_FL_UFLOW_ERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_FL_UFLOW_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_FL_UFLOW_ERR_sticky(unsigned int usticky); +int iSetSM_ABUF_FL_OFLOW_ERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_FL_OFLOW_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_FL_OFLOW_ERR_sticky(unsigned int usticky); +int iSetSM_ABUF_FL_TAIL_MISS_ERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_FL_TAIL_MISS_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_FL_TAIL_MISS_ERR_sticky(unsigned int usticky); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_addr(unsigned int usmeg0_abuf_indir_addr); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_tab(unsigned int usmeg0_abuf_indir_tab); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_stat(unsigned int usmeg0_abuf_indir_stat); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_mode(unsigned int usmeg0_abuf_indir_mode); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_vld(unsigned int usmeg0_abuf_indir_vld); +int iSetSMEG0_ABUF_INDRECT_TIMEOUT_smeg0_abuf_indir_timeout(unsigned int usmeg0_abuf_indir_timeout); +int iSetSMEG0_ABUF_INDRECT_DATA_smeg0_abuf_indir_data(unsigned int usmeg0_abuf_indir_data); +int iSetSM_ABUF_DIS_ALLOC_sm_abuf_dis_alloc(unsigned int usm_abuf_dis_alloc); +int iSetSM_ABUF_DIS_DE_ALLOC_sm_abuf_dis_de_alloc(unsigned int usm_abuf_dis_de_alloc); +int iSetSM_ABUF_FLRC_ST_done_rclm(unsigned int udone_rclm); +int iSetSM_ABUF_FLRC_ST_rlist_cleaning(unsigned int urlist_cleaning); +int iSetSM_ABUF_FLRC_ST_wlist_cleaning(unsigned int uwlist_cleaning); +int iSetSM_ABUF_FLRC_ST_ctp(unsigned int uctp); +int iSetSM_ABUF_EMPTY_FL_ctp(unsigned int uctp); +int iSetSM_ABUF_FULL_FL_ctp(unsigned int uctp); +int iSetSM_ABUF_ST_WM_GROW_ctp(unsigned int uctp); +int iSetSM_ABUF_ST_WM_SHRINK_ctp(unsigned int uctp); +int iSetSM_ABUF_CNT_SEL0_cnt0_src_sel(unsigned int ucnt0_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt0_event_sel(unsigned int ucnt0_event_sel); +int iSetSM_ABUF_CNT_SEL0_cnt1_src_sel(unsigned int ucnt1_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt1_event_sel(unsigned int ucnt1_event_sel); +int iSetSM_ABUF_CNT_SEL0_cnt2_src_sel(unsigned int ucnt2_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt2_event_sel(unsigned int ucnt2_event_sel); +int iSetSM_ABUF_CNT_SEL0_cnt3_src_sel(unsigned int ucnt3_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt3_event_sel(unsigned int ucnt3_event_sel); +int iSetSM_ABUF_CNT_SEL1_cnt4_src_sel(unsigned int ucnt4_src_sel); +int iSetSM_ABUF_CNT_SEL1_cnt4_event_sel(unsigned int ucnt4_event_sel); +int iSetSM_ABUF_CNT_SEL1_cnt5_src_sel(unsigned int ucnt5_src_sel); +int iSetSM_ABUF_CNT_SEL1_cnt5_event_sel(unsigned int ucnt5_event_sel); +int iSetSM_ABUF_CNT_SEL1_cnt_enable(unsigned int ucnt_enable); +int iSetSM_ABUF_COUNTER0_sm_abuf_counter0(unsigned int usm_abuf_counter0); +int iSetSM_ABUF_COUNTER1_sm_abuf_counter1(unsigned int usm_abuf_counter1); +int iSetSM_ABUF_COUNTER2_sm_abuf_counter2(unsigned int usm_abuf_counter2); +int iSetSM_ABUF_COUNTER3_sm_abuf_counter3(unsigned int usm_abuf_counter3); +int iSetSM_ABUF_COUNTER4_sm_abuf_counter4(unsigned int usm_abuf_counter4); +int iSetSM_ABUF_COUNTER5_sm_abuf_counter5(unsigned int usm_abuf_counter5); +int iSetSM_ABUF_PFETCH_FLAG_ctp(unsigned int uctp); +int iSetSM_ABUF_IREQ_LIST_STA_ctp(unsigned int uctp); +int iSetSM_ABUF_TAIL_MISS0_capture_data(unsigned int ucapture_data); +int iSetSM_ABUF_TAIL_MISS0_trigger_enable(unsigned int utrigger_enable); +int iSetSM_ABUF_TAIL_MISS1_capture_data(unsigned int ucapture_data); +int iSetSM_ABUF_TAIL_MISS1_trigger_enable(unsigned int utrigger_enable); +int iSetSM_ABUF_CNT_LIFO_PFETCH_0_ctp(unsigned int uctp); +int iSetSM_ABUF_CNT_LIFO_PFETCH_1_ctp(unsigned int uctp); +int iSetSM_ABUF_CNT_LIFO_PFETCH_2_ctp(unsigned int uctp); +int iSetSM_ABUF_ECC_CFG_list_info_1b_ecc_inj_en(unsigned int ulist_info_1b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_list_info_2b_ecc_inj_en(unsigned int ulist_info_2b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_list_info_ecc_en(unsigned int ulist_info_ecc_en); +int iSetSM_ABUF_ECC_CFG_lifo_1b_ecc_inj_en(unsigned int ulifo_1b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_lifo_2b_ecc_inj_en(unsigned int ulifo_2b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_lifo_ecc_en(unsigned int ulifo_ecc_en); +int iSetSM_ABUF_ECC_1B_ERR_INT_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_ECC_1B_ERR_INT_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_ECC_1B_ERR_INT_sticky(unsigned int usticky); +int iSetSM_ABUF_ECC_2B_ERR_INT_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_ECC_2B_ERR_INT_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_ECC_2B_ERR_INT_sticky(unsigned int usticky); + +/* Define the union csr_smeg0_aget_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_version_u; + +/* Define the union csr_smeg0_aget_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_chk_en : 1; /* [0] */ + u32 rsv_0 : 7; /* [7:1] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 smeg_core_mem_init_start : 1; /* [16] */ + u32 smeg0_cnt0_cfg : 2; /* [18:17] */ + u32 smeg0_cnt1_cfg : 2; /* [20:19] */ + u32 rsv_1 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_cfg_u; + +/* Define the union csr_smeg0_aget_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_int_vector_u; + +/* Define the union csr_smeg0_aget_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 2; /* [1:0] */ + u32 rsv_4 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_int_u; + +/* Define the union csr_smeg0_aget_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 2; /* [1:0] */ + u32 rsv_5 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_int_mask_u; + +/* Define the union csr_smeg0_aget_mem_prty_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_mem_prty_err_u; + +/* Define the union csr_smeg0_aget_boundary_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_boundary_err_u; + +/* Define the union csr_smeg0_aget_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_indir_addr : 24; /* [23:0] */ + u32 smeg0_aget_indir_tab : 4; /* [27:24] */ + u32 smeg0_aget_indir_stat : 2; /* [29:28] */ + u32 smeg0_aget_indir_mode : 1; /* [30] */ + u32 smeg0_aget_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_indrect_ctrl_u; + +/* Define the union csr_smeg0_aget_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_indrect_timeout_u; + +/* Define the union csr_smeg0_aget_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_indrect_data_u; + +/* Define the union csr_smeg_core_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 done : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg_core_mem_init_u; + +/* Define the union csr_smeg0_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_cnt0_u; + +/* Define the union csr_smeg0_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_cnt1_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg0_aget_version_u smeg0_aget_version; /* 0 */ + volatile csr_smeg0_aget_cfg_u smeg0_aget_cfg; /* 4 */ + volatile csr_smeg0_aget_int_vector_u smeg0_aget_int_vector; /* 8 */ + volatile csr_smeg0_aget_int_u smeg0_aget_int; /* C */ + volatile csr_smeg0_aget_int_mask_u smeg0_aget_int_mask; /* 10 */ + volatile csr_smeg0_aget_mem_prty_err_u smeg0_aget_mem_prty_err; /* 14 */ + volatile csr_smeg0_aget_boundary_err_u smeg0_aget_boundary_err; /* 18 */ + volatile csr_smeg0_aget_indrect_ctrl_u smeg0_aget_indrect_ctrl; /* 1C */ + volatile csr_smeg0_aget_indrect_timeout_u smeg0_aget_indrect_timeout; /* 20 */ + volatile csr_smeg0_aget_indrect_data_u smeg0_aget_indrect_data; /* 24 */ + volatile csr_smeg_core_mem_init_u smeg_core_mem_init; /* 28 */ + volatile csr_smeg0_cnt0_u smeg0_cnt0; /* 2C */ + volatile csr_smeg0_cnt1_u smeg0_cnt1; /* 30 */ +} S_smeg0_aget_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg0_aget_csr */ +extern volatile S_smeg0_aget_csr_REGS_TYPE *gopsmeg0_aget_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG0_AGET_VERSION_smeg0_aget_version(unsigned int usmeg0_aget_version); +int iSetSMEG0_AGET_CFG_mem_chk_en(unsigned int umem_chk_en); +int iSetSMEG0_AGET_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMEG0_AGET_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMEG0_AGET_CFG_smeg_core_mem_init_start(unsigned int usmeg_core_mem_init_start); +int iSetSMEG0_AGET_CFG_smeg0_cnt0_cfg(unsigned int usmeg0_cnt0_cfg); +int iSetSMEG0_AGET_CFG_smeg0_cnt1_cfg(unsigned int usmeg0_cnt1_cfg); +int iSetSMEG0_AGET_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMEG0_AGET_INT_VECTOR_enable(unsigned int uenable); +int iSetSMEG0_AGET_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMEG0_AGET_INT_int_data(unsigned int uint_data); +int iSetSMEG0_AGET_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_AGET_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMEG0_AGET_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_AGET_MEM_PRTY_ERR_err(unsigned int uerr); +int iSetSMEG0_AGET_MEM_PRTY_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_AGET_MEM_PRTY_ERR_sticky(unsigned int usticky); +int iSetSMEG0_AGET_BOUNDARY_ERR_err(unsigned int uerr); +int iSetSMEG0_AGET_BOUNDARY_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_AGET_BOUNDARY_ERR_sticky(unsigned int usticky); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_addr(unsigned int usmeg0_aget_indir_addr); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_tab(unsigned int usmeg0_aget_indir_tab); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_stat(unsigned int usmeg0_aget_indir_stat); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_mode(unsigned int usmeg0_aget_indir_mode); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_vld(unsigned int usmeg0_aget_indir_vld); +int iSetSMEG0_AGET_INDRECT_TIMEOUT_smeg0_aget_indir_timeout(unsigned int usmeg0_aget_indir_timeout); +int iSetSMEG0_AGET_INDRECT_DATA_smeg0_aget_indir_data(unsigned int usmeg0_aget_indir_data); +int iSetSMEG_CORE_MEM_INIT_done(unsigned int udone); +int iSetSMEG0_CNT0_smeg0_cnt0(unsigned int usmeg0_cnt0); +int iSetSMEG0_CNT1_smeg0_cnt1(unsigned int usmeg0_cnt1); + +/* Define the union csr_smeg0_lu_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_version_u; + +/* Define the union csr_smeg0_lu_chk_enable_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 1; /* [0] */ + u32 flit_fifo_chk_enable : 1; /* [1] */ + u32 pipe1_mem_chk_enable : 1; /* [2] */ + u32 pipe0_mem_chk_enable : 1; /* [3] */ + u32 rsv_1 : 4; /* [7:4] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_chk_enable_cfg_u; + +/* Define the union csr_smeg0_lu_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_3 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_int_vector_u; + +/* Define the union csr_smeg0_lu_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 7; /* [6:0] */ + u32 rsv_5 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_int_u; + +/* Define the union csr_smeg0_lu_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 7; /* [6:0] */ + u32 rsv_6 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_int_mask_u; + +/* Define the union csr_smeg0_lu_pipe0_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe0_mem_ecc_crt_err_u; + +/* Define the union csr_smeg0_lu_pipe0_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe0_mem_ecc_uncrt_err_u; + +/* Define the union csr_smeg0_lu_pipe1_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe1_mem_ecc_crt_err_u; + +/* Define the union csr_smeg0_lu_pipe1_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe1_mem_ecc_uncrt_err_u; + +/* Define the union csr_smeg0_lu_flitfifo_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_flitfifo_mem_ecc_crt_err_u; + +/* Define the union csr_smeg0_lu_flitfifo_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_flitfifo_mem_ecc_uncrt_err_u; + +/* Define the union csr_smeg0_lu_sw_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_sw_err_u; + +/* Define the union csr_smeg0_lu_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_indir_addr : 24; /* [23:0] */ + u32 smeg0_lu_indir_tab : 4; /* [27:24] */ + u32 smeg0_lu_indir_stat : 2; /* [29:28] */ + u32 smeg0_lu_indir_mode : 1; /* [30] */ + u32 smeg0_lu_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_indrect_ctrl_u; + +/* Define the union csr_smeg0_lu_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_indrect_timeout_u; + +/* Define the union csr_smeg0_lu_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_indrect_data_u; + +/* Define the union csr_smeg0_lu_err_inj_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pipe0_crt_err_inj_req : 1; /* [0] */ + u32 pipe0_uncrt_err_inj_req : 1; /* [1] */ + u32 pipe1_crt_err_inj_req : 1; /* [2] */ + u32 pipe1_uncrt_err_inj_req : 1; /* [3] */ + u32 flitf_crt_err_inj_req : 1; /* [4] */ + u32 flitf_uncrt_err_inj_req : 1; /* [5] */ + u32 rsv_7 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_err_inj_cfg_u; + +/* Define the union csr_smeg0_lu_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_enable : 4; /* [3:0] */ + u32 cnt0_event_sel : 1; /* [4] */ + u32 cnt1_event_sel : 1; /* [5] */ + u32 cnt2_event_sel : 1; /* [6] */ + u32 cnt3_event_sel : 1; /* [7] */ + u32 eng_event_grp : 3; /* [10:8] */ + u32 rsv_8 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt_cfg_u; + +/* Define the union csr_smeg0_lu_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt0_u; + +/* Define the union csr_smeg0_lu_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt1_u; + +/* Define the union csr_smeg0_lu_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt2_u; + +/* Define the union csr_smeg0_lu_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt3_u; + +/* Define the union csr_smeg0_lu_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_in_result_fifo : 5; /* [4:0] */ + u32 num_in_original_fifo : 5; /* [9:5] */ + u32 rsv_9 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_ctp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg0_lu_version_u smeg0_lu_version; /* 0 */ + volatile csr_smeg0_lu_chk_enable_cfg_u smeg0_lu_chk_enable_cfg; /* 4 */ + volatile csr_smeg0_lu_int_vector_u smeg0_lu_int_vector; /* 8 */ + volatile csr_smeg0_lu_int_u smeg0_lu_int; /* C */ + volatile csr_smeg0_lu_int_mask_u smeg0_lu_int_mask; /* 10 */ + volatile csr_smeg0_lu_pipe0_mem_ecc_crt_err_u smeg0_lu_pipe0_mem_ecc_crt_err; /* 14 */ + volatile csr_smeg0_lu_pipe0_mem_ecc_uncrt_err_u smeg0_lu_pipe0_mem_ecc_uncrt_err; /* 18 */ + volatile csr_smeg0_lu_pipe1_mem_ecc_crt_err_u smeg0_lu_pipe1_mem_ecc_crt_err; /* 1C */ + volatile csr_smeg0_lu_pipe1_mem_ecc_uncrt_err_u smeg0_lu_pipe1_mem_ecc_uncrt_err; /* 20 */ + volatile csr_smeg0_lu_flitfifo_mem_ecc_crt_err_u smeg0_lu_flitfifo_mem_ecc_crt_err; /* 24 */ + volatile csr_smeg0_lu_flitfifo_mem_ecc_uncrt_err_u smeg0_lu_flitfifo_mem_ecc_uncrt_err; /* 28 */ + volatile csr_smeg0_lu_sw_err_u smeg0_lu_sw_err; /* 2C */ + volatile csr_smeg0_lu_indrect_ctrl_u smeg0_lu_indrect_ctrl; /* 30 */ + volatile csr_smeg0_lu_indrect_timeout_u smeg0_lu_indrect_timeout; /* 34 */ + volatile csr_smeg0_lu_indrect_data_u smeg0_lu_indrect_data; /* 38 */ + volatile csr_smeg0_lu_err_inj_cfg_u smeg0_lu_err_inj_cfg; /* 3C */ + volatile csr_smeg0_lu_cnt_cfg_u smeg0_lu_cnt_cfg; /* 40 */ + volatile csr_smeg0_lu_cnt0_u smeg0_lu_cnt0; /* 44 */ + volatile csr_smeg0_lu_cnt1_u smeg0_lu_cnt1; /* 48 */ + volatile csr_smeg0_lu_cnt2_u smeg0_lu_cnt2; /* 4C */ + volatile csr_smeg0_lu_cnt3_u smeg0_lu_cnt3; /* 50 */ + volatile csr_smeg0_lu_ctp_u smeg0_lu_ctp; /* 54 */ +} S_smeg0_lu_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg0_lu_csr */ +extern volatile S_smeg0_lu_csr_REGS_TYPE *gopsmeg0_lu_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG0_LU_VERSION_smeg0_lu_version(unsigned int usmeg0_lu_version); +int iSetSMEG0_LU_CHK_ENABLE_CFG_flit_fifo_chk_enable(unsigned int uflit_fifo_chk_enable); +int iSetSMEG0_LU_CHK_ENABLE_CFG_pipe1_mem_chk_enable(unsigned int upipe1_mem_chk_enable); +int iSetSMEG0_LU_CHK_ENABLE_CFG_pipe0_mem_chk_enable(unsigned int upipe0_mem_chk_enable); +int iSetSMEG0_LU_CHK_ENABLE_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMEG0_LU_CHK_ENABLE_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMEG0_LU_CHK_ENABLE_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMEG0_LU_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMEG0_LU_INT_VECTOR_enable(unsigned int uenable); +int iSetSMEG0_LU_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMEG0_LU_INT_int_data(unsigned int uint_data); +int iSetSMEG0_LU_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_LU_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMEG0_LU_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_SW_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_SW_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_SW_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_addr(unsigned int usmeg0_lu_indir_addr); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_tab(unsigned int usmeg0_lu_indir_tab); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_stat(unsigned int usmeg0_lu_indir_stat); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_mode(unsigned int usmeg0_lu_indir_mode); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_vld(unsigned int usmeg0_lu_indir_vld); +int iSetSMEG0_LU_INDRECT_TIMEOUT_smeg0_lu_indir_timeout(unsigned int usmeg0_lu_indir_timeout); +int iSetSMEG0_LU_INDRECT_DATA_smeg0_lu_indir_data(unsigned int usmeg0_lu_indir_data); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe0_crt_err_inj_req(unsigned int upipe0_crt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe0_uncrt_err_inj_req(unsigned int upipe0_uncrt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe1_crt_err_inj_req(unsigned int upipe1_crt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe1_uncrt_err_inj_req(unsigned int upipe1_uncrt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_flitf_crt_err_inj_req(unsigned int uflitf_crt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_flitf_uncrt_err_inj_req(unsigned int uflitf_uncrt_err_inj_req); +int iSetSMEG0_LU_CNT_CFG_cnt_enable(unsigned int ucnt_enable); +int iSetSMEG0_LU_CNT_CFG_cnt0_event_sel(unsigned int ucnt0_event_sel); +int iSetSMEG0_LU_CNT_CFG_cnt1_event_sel(unsigned int ucnt1_event_sel); +int iSetSMEG0_LU_CNT_CFG_cnt2_event_sel(unsigned int ucnt2_event_sel); +int iSetSMEG0_LU_CNT_CFG_cnt3_event_sel(unsigned int ucnt3_event_sel); +int iSetSMEG0_LU_CNT_CFG_eng_event_grp(unsigned int ueng_event_grp); +int iSetSMEG0_LU_CNT0_smeg0_lu_cnt0(unsigned int usmeg0_lu_cnt0); +int iSetSMEG0_LU_CNT1_smeg0_lu_cnt1(unsigned int usmeg0_lu_cnt1); +int iSetSMEG0_LU_CNT2_smeg0_lu_cnt2(unsigned int usmeg0_lu_cnt2); +int iSetSMEG0_LU_CNT3_smeg0_lu_cnt3(unsigned int usmeg0_lu_cnt3); +int iSetSMEG0_LU_CTP_num_in_result_fifo(unsigned int unum_in_result_fifo); +int iSetSMEG0_LU_CTP_num_in_original_fifo(unsigned int unum_in_original_fifo); + +/* Define the union csr_smeg1_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_version_u; + +/* Define the union csr_smeg1_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_runaway_thread : 1; /* [0] */ + u32 preload_fairness : 1; /* [1] */ + u32 premem_count : 4; /* [5:2] */ + u32 halt_sw_err : 1; /* [6] */ + u32 halt_on_ebit : 1; /* [7] */ + u32 halt_sw_err1 : 1; /* [8] */ + u32 ctp_active_bits : 1; /* [9] */ + u32 halt_on_runaway_err : 1; /* [10] */ + u32 tcd_thd_id : 6; /* [16:11] */ + u32 msb_thread_cfg : 1; /* [17] */ + u32 mem_chk_en : 1; /* [18] */ + u32 rp_inlld_ll_ivld_en : 1; /* [19] */ + u32 bt_inst_id : 6; /* [25:20] */ + u32 rp_halt_thread_max_num : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cfg0_u; + +/* Define the union csr_smeg1_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tp_ram_tmod : 8; /* [7:0] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 rp_crt_err_inj_req : 1; /* [16] */ + u32 rp_uncrt_err_inj_req : 1; /* [17] */ + u32 fidr_crt_err_inj_req : 1; /* [18] */ + u32 fidr_uncrt_err_inj_req : 1; /* [19] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cfg1_u; + +/* Define the union csr_smeg1_runaway_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_runaway_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_runaway_cfg_u; + +/* Define the union csr_smeg1_thread_enable_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_thread_enable_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_thread_enable_cfg_u; + +/* Define the union csr_smeg1_tm_ts_fast2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_fast2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_fast2_u; + +/* Define the union csr_smeg1_tm_ts_fast3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_fast3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_fast3_u; + +/* Define the union csr_smeg1_tm_ts_slow0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_slow0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_slow0_u; + +/* Define the union csr_smeg1_tm_ts_slow1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_slow1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_slow1_u; + +/* Define the union csr_smeg1_tm_tmt_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt28 : 8; /* [7:0] */ + u32 smeg1_tm_tmt29 : 8; /* [15:8] */ + u32 smeg1_tm_tmt30 : 8; /* [23:16] */ + u32 smeg1_tm_tmt31 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg7_u; + +/* Define the union csr_smeg1_tm_tmt_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt24 : 8; /* [7:0] */ + u32 smeg1_tm_tmt25 : 8; /* [15:8] */ + u32 smeg1_tm_tmt26 : 8; /* [23:16] */ + u32 smeg1_tm_tmt27 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg6_u; + +/* Define the union csr_smeg1_tm_tmt_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt20 : 8; /* [7:0] */ + u32 smeg1_tm_tmt21 : 8; /* [15:8] */ + u32 smeg1_tm_tmt22 : 8; /* [23:16] */ + u32 smeg1_tm_tmt23 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg5_u; + +/* Define the union csr_smeg1_tm_tmt_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt16 : 8; /* [7:0] */ + u32 smeg1_tm_tmt17 : 8; /* [15:8] */ + u32 smeg1_tm_tmt18 : 8; /* [23:16] */ + u32 smeg1_tm_tmt19 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg4_u; + +/* Define the union csr_smeg1_tm_tmt_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt12 : 8; /* [7:0] */ + u32 smeg1_tm_tmt13 : 8; /* [15:8] */ + u32 smeg1_tm_tmt14 : 8; /* [23:16] */ + u32 smeg1_tm_tmt15 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg3_u; + +/* Define the union csr_smeg1_tm_tmt_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt8 : 8; /* [7:0] */ + u32 smeg1_tm_tmt9 : 8; /* [15:8] */ + u32 smeg1_tm_tmt10 : 8; /* [23:16] */ + u32 smeg1_tm_tmt11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg2_u; + +/* Define the union csr_smeg1_tm_tmt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt4 : 8; /* [7:0] */ + u32 smeg1_tm_tmt5 : 8; /* [15:8] */ + u32 smeg1_tm_tmt6 : 8; /* [23:16] */ + u32 smeg1_tm_tmt7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg1_u; + +/* Define the union csr_smeg1_tm_tmt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt0 : 8; /* [7:0] */ + u32 smeg1_tm_tmt1 : 8; /* [15:8] */ + u32 smeg1_tm_tmt2 : 8; /* [23:16] */ + u32 smeg1_tm_tmt3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg0_u; + +/* Define the union csr_smeg1_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_int_vector_u; + +/* Define the union csr_smeg1_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_3 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_int_u; + +/* Define the union csr_smeg1_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_4 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_int_mask_u; + +/* Define the union csr_smeg1_engine_sw_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_engine_sw_err_u; + +/* Define the union csr_smeg1_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_crt_err0 : 1; /* [0] */ + u32 ecc_crt_merr0 : 1; /* [1] */ + u32 ecc_crt_err1 : 1; /* [2] */ + u32 ecc_crt_merr1 : 1; /* [3] */ + u32 ecc_crt_err2 : 1; /* [4] */ + u32 ecc_crt_merr2 : 1; /* [5] */ + u32 ecc_crt_err3 : 1; /* [6] */ + u32 ecc_crt_merr3 : 1; /* [7] */ + u32 ecc_crt_err4 : 1; /* [8] */ + u32 ecc_crt_merr4 : 1; /* [9] */ + u32 ecc_crt_err5 : 1; /* [10] */ + u32 ecc_crt_merr5 : 1; /* [11] */ + u32 ecc_crt_err6 : 1; /* [12] */ + u32 ecc_crt_merr6 : 1; /* [13] */ + u32 ecc_crt_err7 : 1; /* [14] */ + u32 ecc_crt_merr7 : 1; /* [15] */ + u32 runaway_err : 1; /* [16] */ + u32 runaway_merr : 1; /* [17] */ + u32 ecc_crt_err8 : 1; /* [18] */ + u32 ecc_crt_merr8 : 1; /* [19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err0_u; + +/* Define the union csr_smeg1_err0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_crt_err_mask0 : 1; /* [0] */ + u32 ecc_crt_err_mask1 : 1; /* [1] */ + u32 ecc_crt_err_mask2 : 1; /* [2] */ + u32 ecc_crt_err_mask3 : 1; /* [3] */ + u32 ecc_crt_err_mask4 : 1; /* [4] */ + u32 ecc_crt_err_mask5 : 1; /* [5] */ + u32 ecc_crt_err_mask6 : 1; /* [6] */ + u32 ecc_crt_err_mask7 : 1; /* [7] */ + u32 runaway_err_mask : 1; /* [8] */ + u32 ecc_crt_err_mask8 : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err0_mask_u; + +/* Define the union csr_smeg1_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_uncrt_err0 : 1; /* [0] */ + u32 ecc_uncrt_merr0 : 1; /* [1] */ + u32 ecc_uncrt_err1 : 1; /* [2] */ + u32 ecc_uncrt_merr1 : 1; /* [3] */ + u32 ecc_uncrt_err2 : 1; /* [4] */ + u32 ecc_uncrt_merr2 : 1; /* [5] */ + u32 ecc_uncrt_err3 : 1; /* [6] */ + u32 ecc_uncrt_merr3 : 1; /* [7] */ + u32 ecc_uncrt_err4 : 1; /* [8] */ + u32 ecc_uncrt_merr4 : 1; /* [9] */ + u32 ecc_uncrt_err5 : 1; /* [10] */ + u32 ecc_uncrt_merr5 : 1; /* [11] */ + u32 ecc_uncrt_err6 : 1; /* [12] */ + u32 ecc_uncrt_merr6 : 1; /* [13] */ + u32 ecc_uncrt_err7 : 1; /* [14] */ + u32 ecc_uncrt_merr7 : 1; /* [15] */ + u32 ecc_uncrt_err8 : 1; /* [16] */ + u32 ecc_uncrt_merr8 : 1; /* [17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err1_u; + +/* Define the union csr_smeg1_err1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_uncrt_err_mask0 : 1; /* [0] */ + u32 ecc_uncrt_err_mask1 : 1; /* [1] */ + u32 ecc_uncrt_err_mask2 : 1; /* [2] */ + u32 ecc_uncrt_err_mask3 : 1; /* [3] */ + u32 ecc_uncrt_err_mask4 : 1; /* [4] */ + u32 ecc_uncrt_err_mask5 : 1; /* [5] */ + u32 ecc_uncrt_err_mask6 : 1; /* [6] */ + u32 ecc_uncrt_err_mask7 : 1; /* [7] */ + u32 ecc_uncrt_err_mask8 : 1; /* [8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err1_mask_u; + +/* Define the union csr_smeg1_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_indir_addr : 24; /* [23:0] */ + u32 smeg1_indir_tab : 4; /* [27:24] */ + u32 smeg1_indir_stat : 2; /* [29:28] */ + u32 smeg1_indir_mode : 1; /* [30] */ + u32 smeg1_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_indrect_ctrl_u; + +/* Define the union csr_smeg1_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_indrect_timeout_u; + +/* Define the union csr_smeg1_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_indrect_data_u; + +/* Define the union csr_smeg1_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_enable : 1; /* [0] */ + u32 cnt1_enable : 1; /* [1] */ + u32 cnt2_enable : 1; /* [2] */ + u32 cnt3_enable : 1; /* [3] */ + u32 cnt0_match_en : 1; /* [4] */ + u32 cnt1_match_en : 1; /* [5] */ + u32 cnt2_match_en : 1; /* [6] */ + u32 cnt3_match_en : 1; /* [7] */ + u32 cnt0_sel : 1; /* [8] */ + u32 cnt1_sel : 2; /* [10:9] */ + u32 cnt2_sel : 1; /* [11] */ + u32 cnt3_sel : 1; /* [12] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cnt_cfg_u; + +/* Define the union csr_smeg1_cnt_match_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_match_id : 6; /* [5:0] */ + u32 cnt1_match_id : 6; /* [11:6] */ + u32 cnt2_match_id : 6; /* [17:12] */ + u32 cnt3_match_id : 6; /* [23:18] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cnt_match_id_u; + +/* Define the union csr_smeg1_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt0 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt0_u; + +/* Define the union csr_smeg1_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt1 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt1_u; + +/* Define the union csr_smeg1_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt2 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt2_u; + +/* Define the union csr_smeg1_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt3 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt3_u; + +/* Define the union csr_rsv_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_1_u; + +/* Define the union csr_rsv_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_2_u; + +/* Define the union csr_smeg1_thread_enable_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_thread_enable_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_thread_enable_cfg2_u; + +/* Define the union csr_rsv_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_3_u; + +/* Define the union csr_rsv_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_4_u; + +/* Define the union csr_rsv_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_5_u; + +/* Define the union csr_rsv_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_6_u; + +/* Define the union csr_smeg1_tmt_ext_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tmt_ext_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tmt_ext_cfg_u; + +/* Define the union csr_smeg1_mem_ecc_err_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flag : 9; /* [8:0] */ + u32 rsv_13 : 7; /* [15:9] */ + u32 addr : 7; /* [22:16] */ + u32 rsv_14 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_mem_ecc_err_ctp_u; + +/* Define the union csr_smmc_cache_resource_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_cnt : 14; /* [13:0] */ + u32 rsv_15 : 2; /* [15:14] */ + u32 rq_cnt : 14; /* [29:16] */ + u32 rsv_16 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_cache_resource_ctp_u; + +/* Define the union csr_smeg1_sync_api_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 snapshot_eng_id : 5; /* [4:0] */ + u32 snapshot_eng_en : 1; /* [5] */ + u32 rsv_17 : 2; /* [7:6] */ + u32 sync_cnt_threshold : 2; /* [9:8] */ + u32 rsv_18 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_sync_api_cfg_u; + +/* Define the union csr_rsv_183_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_183_u; + +/* Define the union csr_smeg1_cur_timestamp_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 49; /* [48:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cur_timestamp_us_u; + +/* Define the union csr_smeg1_runaway_thd_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_runaway_thd_ctp_u; + +/* Define the union csr_smeg1_ctp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 active_runaway_thd : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_ctp0_u; + +/* Define the union csr_smeg1_ctp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_internal : 44; /* [43:0] */ + u64 rsv_20 : 20; /* [63:44] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_ctp1_u; + +/* Define the union csr_smeg1_ctp2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 wt_runaway : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_ctp2_u; + +/* Define the union csr_smeg1_ctp3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_ctp3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg1_version_u smeg1_version; /* 0 */ + volatile csr_smeg1_cfg0_u smeg1_cfg0; /* 4 */ + volatile csr_smeg1_cfg1_u smeg1_cfg1; /* 8 */ + volatile csr_smeg1_runaway_cfg_u smeg1_runaway_cfg; /* C */ + volatile csr_smeg1_thread_enable_cfg_u smeg1_thread_enable_cfg; /* 10 */ + volatile csr_smeg1_tm_ts_fast2_u smeg1_tm_ts_fast2; /* 14 */ + volatile csr_smeg1_tm_ts_fast3_u smeg1_tm_ts_fast3; /* 18 */ + volatile csr_smeg1_tm_ts_slow0_u smeg1_tm_ts_slow0; /* 1C */ + volatile csr_smeg1_tm_ts_slow1_u smeg1_tm_ts_slow1; /* 20 */ + volatile csr_smeg1_tm_tmt_cfg7_u smeg1_tm_tmt_cfg7; /* 24 */ + volatile csr_smeg1_tm_tmt_cfg6_u smeg1_tm_tmt_cfg6; /* 28 */ + volatile csr_smeg1_tm_tmt_cfg5_u smeg1_tm_tmt_cfg5; /* 2C */ + volatile csr_smeg1_tm_tmt_cfg4_u smeg1_tm_tmt_cfg4; /* 30 */ + volatile csr_smeg1_tm_tmt_cfg3_u smeg1_tm_tmt_cfg3; /* 34 */ + volatile csr_smeg1_tm_tmt_cfg2_u smeg1_tm_tmt_cfg2; /* 38 */ + volatile csr_smeg1_tm_tmt_cfg1_u smeg1_tm_tmt_cfg1; /* 3C */ + volatile csr_smeg1_tm_tmt_cfg0_u smeg1_tm_tmt_cfg0; /* 40 */ + volatile csr_smeg1_int_vector_u smeg1_int_vector; /* 44 */ + volatile csr_smeg1_int_u smeg1_int; /* 48 */ + volatile csr_smeg1_int_mask_u smeg1_int_mask; /* 4C */ + volatile csr_smeg1_engine_sw_err_u smeg1_engine_sw_err; /* 50 */ + volatile csr_smeg1_err0_u smeg1_err0; /* 54 */ + volatile csr_smeg1_err0_mask_u smeg1_err0_mask; /* 58 */ + volatile csr_smeg1_err1_u smeg1_err1; /* 5C */ + volatile csr_smeg1_err1_mask_u smeg1_err1_mask; /* 60 */ + volatile csr_smeg1_indrect_ctrl_u smeg1_indrect_ctrl; /* 64 */ + volatile csr_smeg1_indrect_timeout_u smeg1_indrect_timeout; /* 68 */ + volatile csr_smeg1_indrect_data_u smeg1_indrect_data; /* 6C */ + volatile csr_smeg1_cnt_cfg_u smeg1_cnt_cfg; /* 70 */ + volatile csr_smeg1_cnt_match_id_u smeg1_cnt_match_id; /* 74 */ + volatile csr_smeg1_cnt0_u smeg1_cnt0; /* 78 */ + volatile csr_smeg1_cnt1_u smeg1_cnt1; /* 80 */ + volatile csr_smeg1_cnt2_u smeg1_cnt2; /* 88 */ + volatile csr_smeg1_cnt3_u smeg1_cnt3; /* 90 */ + volatile csr_rsv_1_u rsv_1; /* 98 */ + volatile csr_rsv_2_u rsv_2; /* 9C */ + volatile csr_smeg1_thread_enable_cfg2_u smeg1_thread_enable_cfg2; /* A0 */ + volatile csr_rsv_3_u rsv_3; /* A4 */ + volatile csr_rsv_4_u rsv_4; /* A8 */ + volatile csr_rsv_5_u rsv_5; /* AC */ + volatile csr_rsv_6_u rsv_6; /* B0 */ + volatile csr_smeg1_tmt_ext_cfg_u smeg1_tmt_ext_cfg; /* B4 */ + volatile csr_smeg1_mem_ecc_err_ctp_u smeg1_mem_ecc_err_ctp; /* B8 */ + volatile csr_smmc_cache_resource_ctp_u smmc_cache_resource_ctp; /* BC */ + volatile csr_smeg1_sync_api_cfg_u smeg1_sync_api_cfg; /* C0 */ + volatile csr_rsv_183_u rsv_183; /* C4 */ + volatile csr_smeg1_cur_timestamp_us_u smeg1_cur_timestamp_us; /* C8 */ + volatile csr_smeg1_runaway_thd_ctp_u smeg1_runaway_thd_ctp; /* D0 */ + volatile csr_smeg1_ctp0_u smeg1_ctp0; /* D8 */ + volatile csr_smeg1_ctp1_u smeg1_ctp1; /* E0 */ + volatile csr_smeg1_ctp2_u smeg1_ctp2; /* E8 */ + volatile csr_smeg1_ctp3_u smeg1_ctp3; /* F0 */ +} S_smeg1_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg1_csr */ +extern volatile S_smeg1_csr_REGS_TYPE *gopsmeg1_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG1_VERSION_smeg1_version(unsigned int usmeg1_version); +int iSetSMEG1_CFG0_detect_runaway_thread(unsigned int udetect_runaway_thread); +int iSetSMEG1_CFG0_preload_fairness(unsigned int upreload_fairness); +int iSetSMEG1_CFG0_premem_count(unsigned int upremem_count); +int iSetSMEG1_CFG0_halt_sw_err(unsigned int uhalt_sw_err); +int iSetSMEG1_CFG0_halt_on_ebit(unsigned int uhalt_on_ebit); +int iSetSMEG1_CFG0_halt_sw_err1(unsigned int uhalt_sw_err1); +int iSetSMEG1_CFG0_ctp_active_bits(unsigned int uctp_active_bits); +int iSetSMEG1_CFG0_halt_on_runaway_err(unsigned int uhalt_on_runaway_err); +int iSetSMEG1_CFG0_tcd_thd_id(unsigned int utcd_thd_id); +int iSetSMEG1_CFG0_msb_thread_cfg(unsigned int umsb_thread_cfg); +int iSetSMEG1_CFG0_mem_chk_en(unsigned int umem_chk_en); +int iSetSMEG1_CFG0_rp_inlld_ll_ivld_en(unsigned int urp_inlld_ll_ivld_en); +int iSetSMEG1_CFG0_bt_inst_id(unsigned int ubt_inst_id); +int iSetSMEG1_CFG0_rp_halt_thread_max_num(unsigned int urp_halt_thread_max_num); +int iSetSMEG1_CFG1_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMEG1_CFG1_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMEG1_CFG1_mem_ret1n(unsigned int umem_ret1n); +int iSetSMEG1_CFG1_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMEG1_CFG1_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMEG1_CFG1_fidr_crt_err_inj_req(unsigned int ufidr_crt_err_inj_req); +int iSetSMEG1_CFG1_fidr_uncrt_err_inj_req(unsigned int ufidr_uncrt_err_inj_req); +int iSetSMEG1_RUNAWAY_CFG_smeg1_runaway_cfg(unsigned int usmeg1_runaway_cfg); +int iSetSMEG1_THREAD_ENABLE_CFG_smeg1_thread_enable_cfg(unsigned int usmeg1_thread_enable_cfg); +int iSetSMEG1_TM_TS_FAST2_smeg1_tm_ts_fast2(unsigned int usmeg1_tm_ts_fast2); +int iSetSMEG1_TM_TS_FAST3_smeg1_tm_ts_fast3(unsigned int usmeg1_tm_ts_fast3); +int iSetSMEG1_TM_TS_SLOW0_smeg1_tm_ts_slow0(unsigned int usmeg1_tm_ts_slow0); +int iSetSMEG1_TM_TS_SLOW1_smeg1_tm_ts_slow1(unsigned int usmeg1_tm_ts_slow1); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt28(unsigned int usmeg1_tm_tmt28); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt29(unsigned int usmeg1_tm_tmt29); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt30(unsigned int usmeg1_tm_tmt30); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt31(unsigned int usmeg1_tm_tmt31); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt24(unsigned int usmeg1_tm_tmt24); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt25(unsigned int usmeg1_tm_tmt25); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt26(unsigned int usmeg1_tm_tmt26); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt27(unsigned int usmeg1_tm_tmt27); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt20(unsigned int usmeg1_tm_tmt20); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt21(unsigned int usmeg1_tm_tmt21); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt22(unsigned int usmeg1_tm_tmt22); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt23(unsigned int usmeg1_tm_tmt23); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt16(unsigned int usmeg1_tm_tmt16); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt17(unsigned int usmeg1_tm_tmt17); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt18(unsigned int usmeg1_tm_tmt18); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt19(unsigned int usmeg1_tm_tmt19); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt12(unsigned int usmeg1_tm_tmt12); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt13(unsigned int usmeg1_tm_tmt13); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt14(unsigned int usmeg1_tm_tmt14); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt15(unsigned int usmeg1_tm_tmt15); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt8(unsigned int usmeg1_tm_tmt8); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt9(unsigned int usmeg1_tm_tmt9); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt10(unsigned int usmeg1_tm_tmt10); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt11(unsigned int usmeg1_tm_tmt11); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt4(unsigned int usmeg1_tm_tmt4); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt5(unsigned int usmeg1_tm_tmt5); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt6(unsigned int usmeg1_tm_tmt6); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt7(unsigned int usmeg1_tm_tmt7); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt0(unsigned int usmeg1_tm_tmt0); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt1(unsigned int usmeg1_tm_tmt1); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt2(unsigned int usmeg1_tm_tmt2); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt3(unsigned int usmeg1_tm_tmt3); +int iSetSMEG1_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMEG1_INT_VECTOR_enable(unsigned int uenable); +int iSetSMEG1_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMEG1_INT_int_data(unsigned int uint_data); +int iSetSMEG1_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG1_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMEG1_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG1_ENGINE_SW_ERR_error_bit(unsigned int uerror_bit); +int iSetSMEG1_ENGINE_SW_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMEG1_ENGINE_SW_ERR_sticky(unsigned int usticky); +int iSetSMEG1_ERR0_ecc_crt_err0(unsigned int uecc_crt_err0); +int iSetSMEG1_ERR0_ecc_crt_merr0(unsigned int uecc_crt_merr0); +int iSetSMEG1_ERR0_ecc_crt_err1(unsigned int uecc_crt_err1); +int iSetSMEG1_ERR0_ecc_crt_merr1(unsigned int uecc_crt_merr1); +int iSetSMEG1_ERR0_ecc_crt_err2(unsigned int uecc_crt_err2); +int iSetSMEG1_ERR0_ecc_crt_merr2(unsigned int uecc_crt_merr2); +int iSetSMEG1_ERR0_ecc_crt_err3(unsigned int uecc_crt_err3); +int iSetSMEG1_ERR0_ecc_crt_merr3(unsigned int uecc_crt_merr3); +int iSetSMEG1_ERR0_ecc_crt_err4(unsigned int uecc_crt_err4); +int iSetSMEG1_ERR0_ecc_crt_merr4(unsigned int uecc_crt_merr4); +int iSetSMEG1_ERR0_ecc_crt_err5(unsigned int uecc_crt_err5); +int iSetSMEG1_ERR0_ecc_crt_merr5(unsigned int uecc_crt_merr5); +int iSetSMEG1_ERR0_ecc_crt_err6(unsigned int uecc_crt_err6); +int iSetSMEG1_ERR0_ecc_crt_merr6(unsigned int uecc_crt_merr6); +int iSetSMEG1_ERR0_ecc_crt_err7(unsigned int uecc_crt_err7); +int iSetSMEG1_ERR0_ecc_crt_merr7(unsigned int uecc_crt_merr7); +int iSetSMEG1_ERR0_runaway_err(unsigned int urunaway_err); +int iSetSMEG1_ERR0_runaway_merr(unsigned int urunaway_merr); +int iSetSMEG1_ERR0_ecc_crt_err8(unsigned int uecc_crt_err8); +int iSetSMEG1_ERR0_ecc_crt_merr8(unsigned int uecc_crt_merr8); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask0(unsigned int uecc_crt_err_mask0); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask1(unsigned int uecc_crt_err_mask1); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask2(unsigned int uecc_crt_err_mask2); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask3(unsigned int uecc_crt_err_mask3); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask4(unsigned int uecc_crt_err_mask4); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask5(unsigned int uecc_crt_err_mask5); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask6(unsigned int uecc_crt_err_mask6); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask7(unsigned int uecc_crt_err_mask7); +int iSetSMEG1_ERR0_MASK_runaway_err_mask(unsigned int urunaway_err_mask); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask8(unsigned int uecc_crt_err_mask8); +int iSetSMEG1_ERR1_ecc_uncrt_err0(unsigned int uecc_uncrt_err0); +int iSetSMEG1_ERR1_ecc_uncrt_merr0(unsigned int uecc_uncrt_merr0); +int iSetSMEG1_ERR1_ecc_uncrt_err1(unsigned int uecc_uncrt_err1); +int iSetSMEG1_ERR1_ecc_uncrt_merr1(unsigned int uecc_uncrt_merr1); +int iSetSMEG1_ERR1_ecc_uncrt_err2(unsigned int uecc_uncrt_err2); +int iSetSMEG1_ERR1_ecc_uncrt_merr2(unsigned int uecc_uncrt_merr2); +int iSetSMEG1_ERR1_ecc_uncrt_err3(unsigned int uecc_uncrt_err3); +int iSetSMEG1_ERR1_ecc_uncrt_merr3(unsigned int uecc_uncrt_merr3); +int iSetSMEG1_ERR1_ecc_uncrt_err4(unsigned int uecc_uncrt_err4); +int iSetSMEG1_ERR1_ecc_uncrt_merr4(unsigned int uecc_uncrt_merr4); +int iSetSMEG1_ERR1_ecc_uncrt_err5(unsigned int uecc_uncrt_err5); +int iSetSMEG1_ERR1_ecc_uncrt_merr5(unsigned int uecc_uncrt_merr5); +int iSetSMEG1_ERR1_ecc_uncrt_err6(unsigned int uecc_uncrt_err6); +int iSetSMEG1_ERR1_ecc_uncrt_merr6(unsigned int uecc_uncrt_merr6); +int iSetSMEG1_ERR1_ecc_uncrt_err7(unsigned int uecc_uncrt_err7); +int iSetSMEG1_ERR1_ecc_uncrt_merr7(unsigned int uecc_uncrt_merr7); +int iSetSMEG1_ERR1_ecc_uncrt_err8(unsigned int uecc_uncrt_err8); +int iSetSMEG1_ERR1_ecc_uncrt_merr8(unsigned int uecc_uncrt_merr8); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask0(unsigned int uecc_uncrt_err_mask0); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask1(unsigned int uecc_uncrt_err_mask1); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask2(unsigned int uecc_uncrt_err_mask2); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask3(unsigned int uecc_uncrt_err_mask3); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask4(unsigned int uecc_uncrt_err_mask4); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask5(unsigned int uecc_uncrt_err_mask5); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask6(unsigned int uecc_uncrt_err_mask6); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask7(unsigned int uecc_uncrt_err_mask7); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask8(unsigned int uecc_uncrt_err_mask8); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_addr(unsigned int usmeg1_indir_addr); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_tab(unsigned int usmeg1_indir_tab); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_stat(unsigned int usmeg1_indir_stat); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_mode(unsigned int usmeg1_indir_mode); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_vld(unsigned int usmeg1_indir_vld); +int iSetSMEG1_INDRECT_TIMEOUT_smeg1_indir_timeout(unsigned int usmeg1_indir_timeout); +int iSetSMEG1_INDRECT_DATA_smeg1_indir_data(unsigned int usmeg1_indir_data); +int iSetSMEG1_CNT_CFG_cnt0_enable(unsigned int ucnt0_enable); +int iSetSMEG1_CNT_CFG_cnt1_enable(unsigned int ucnt1_enable); +int iSetSMEG1_CNT_CFG_cnt2_enable(unsigned int ucnt2_enable); +int iSetSMEG1_CNT_CFG_cnt3_enable(unsigned int ucnt3_enable); +int iSetSMEG1_CNT_CFG_cnt0_match_en(unsigned int ucnt0_match_en); +int iSetSMEG1_CNT_CFG_cnt1_match_en(unsigned int ucnt1_match_en); +int iSetSMEG1_CNT_CFG_cnt2_match_en(unsigned int ucnt2_match_en); +int iSetSMEG1_CNT_CFG_cnt3_match_en(unsigned int ucnt3_match_en); +int iSetSMEG1_CNT_CFG_cnt0_sel(unsigned int ucnt0_sel); +int iSetSMEG1_CNT_CFG_cnt1_sel(unsigned int ucnt1_sel); +int iSetSMEG1_CNT_CFG_cnt2_sel(unsigned int ucnt2_sel); +int iSetSMEG1_CNT_CFG_cnt3_sel(unsigned int ucnt3_sel); +int iSetSMEG1_CNT_MATCH_ID_cnt0_match_id(unsigned int ucnt0_match_id); +int iSetSMEG1_CNT_MATCH_ID_cnt1_match_id(unsigned int ucnt1_match_id); +int iSetSMEG1_CNT_MATCH_ID_cnt2_match_id(unsigned int ucnt2_match_id); +int iSetSMEG1_CNT_MATCH_ID_cnt3_match_id(unsigned int ucnt3_match_id); +int iSetSMEG1_CNT0_smeg1_cnt0(unsigned int usmeg1_cnt0); +int iSetSMEG1_CNT1_smeg1_cnt1(unsigned int usmeg1_cnt1); +int iSetSMEG1_CNT2_smeg1_cnt2(unsigned int usmeg1_cnt2); +int iSetSMEG1_CNT3_smeg1_cnt3(unsigned int usmeg1_cnt3); + + +int iSetSMEG1_THREAD_ENABLE_CFG2_smeg1_thread_enable_cfg2(unsigned int usmeg1_thread_enable_cfg2); + + +int iSetSMEG1_TMT_EXT_CFG_smeg1_tmt_ext_cfg(unsigned int usmeg1_tmt_ext_cfg); +int iSetSMEG1_MEM_ECC_ERR_CTP_flag(unsigned int uflag); +int iSetSMEG1_MEM_ECC_ERR_CTP_addr(unsigned int uaddr); +int iSetSMMC_CACHE_RESOURCE_CTP_sq_cnt(unsigned int usq_cnt); +int iSetSMMC_CACHE_RESOURCE_CTP_rq_cnt(unsigned int urq_cnt); +int iSetSMEG1_SYNC_API_CFG_snapshot_eng_id(unsigned int usnapshot_eng_id); +int iSetSMEG1_SYNC_API_CFG_snapshot_eng_en(unsigned int usnapshot_eng_en); +int iSetSMEG1_SYNC_API_CFG_sync_cnt_threshold(unsigned int usync_cnt_threshold); + +int iSetSMEG1_CUR_TIMESTAMP_US_ctp(unsigned int uctp); +int iSetSMEG1_RUNAWAY_THD_CTP_ctp(unsigned int uctp); +int iSetSMEG1_CTP0_active_runaway_thd(unsigned int uactive_runaway_thd); +int iSetSMEG1_CTP1_smeg1_internal(unsigned int usmeg1_internal); +int iSetSMEG1_CTP2_wt_runaway(unsigned int uwt_runaway); +int iSetSMEG1_CTP3_tcd(unsigned int utcd); + +/* Define the union csr_smit_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_version_u; + +/* Define the union csr_smit_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dis_oder : 1; /* [0] */ + u32 rsv_0 : 7; /* [7:1] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 mem_ret1n : 1; /* [16] */ + u32 mem_pb_chk_en : 1; /* [17] */ + u32 rp_crt_err_inj_req : 1; /* [18] */ + u32 rp_uncrt_err_inj_req : 1; /* [19] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_cfg_u; + +/* Define the union csr_smit_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_int_vector_u; + +/* Define the union csr_smit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_4 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_int_u; + +/* Define the union csr_smit_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_5 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_int_mask_u; + +/* Define the union csr_smit_err_prty_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_err_prty_u; + +/* Define the union csr_smit_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_mem_ecc_crt_err_u; + +/* Define the union csr_smit_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_mem_ecc_uncrt_err_u; + +/* Define the union csr_smit_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_indir_addr : 24; /* [23:0] */ + u32 smit_indir_tab : 4; /* [27:24] */ + u32 smit_indir_stat : 2; /* [29:28] */ + u32 smit_indir_mode : 1; /* [30] */ + u32 smit_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_indrect_ctrl_u; + +/* Define the union csr_smit_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_indrect_timeout_u; + +/* Define the union csr_smit_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_indrect_data_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smit_version_u smit_version; /* 0 */ + volatile csr_smit_cfg_u smit_cfg; /* 4 */ + volatile csr_smit_int_vector_u smit_int_vector; /* 8 */ + volatile csr_smit_int_u smit_int; /* C */ + volatile csr_smit_int_mask_u smit_int_mask; /* 10 */ + volatile csr_smit_err_prty_u smit_err_prty; /* 14 */ + volatile csr_smit_mem_ecc_crt_err_u smit_mem_ecc_crt_err; /* 18 */ + volatile csr_smit_mem_ecc_uncrt_err_u smit_mem_ecc_uncrt_err; /* 1C */ + volatile csr_smit_indrect_ctrl_u smit_indrect_ctrl; /* 20 */ + volatile csr_smit_indrect_timeout_u smit_indrect_timeout; /* 24 */ + volatile csr_smit_indrect_data_u smit_indrect_data; /* 28 */ + volatile csr_cfg_mem_ctrl_bus0_u cfg_mem_ctrl_bus0; /* 2C */ + volatile csr_cfg_mem_ctrl_bus1_u cfg_mem_ctrl_bus1; /* 30 */ + volatile csr_cfg_mem_ctrl_bus2_u cfg_mem_ctrl_bus2; /* 34 */ + volatile csr_cfg_mem_ctrl_bus3_u cfg_mem_ctrl_bus3; /* 38 */ + volatile csr_cfg_mem_ctrl_bus4_u cfg_mem_ctrl_bus4; /* 3C */ +} S_smit_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smit_csr */ +extern volatile S_smit_csr_REGS_TYPE *gopsmit_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMIT_VERSION_smit_version(unsigned int usmit_version); +int iSetSMIT_CFG_dis_oder(unsigned int udis_oder); +int iSetSMIT_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMIT_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMIT_CFG_mem_pb_chk_en(unsigned int umem_pb_chk_en); +int iSetSMIT_CFG_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMIT_CFG_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMIT_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMIT_INT_VECTOR_enable(unsigned int uenable); +int iSetSMIT_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMIT_INT_int_data(unsigned int uint_data); +int iSetSMIT_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIT_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMIT_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIT_ERR_PRTY_error_bit(unsigned int uerror_bit); +int iSetSMIT_ERR_PRTY_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIT_ERR_PRTY_sticky(unsigned int usticky); +int iSetSMIT_MEM_ECC_CRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIT_MEM_ECC_CRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIT_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMIT_MEM_ECC_UNCRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIT_MEM_ECC_UNCRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIT_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMIT_INDRECT_CTRL_smit_indir_addr(unsigned int usmit_indir_addr); +int iSetSMIT_INDRECT_CTRL_smit_indir_tab(unsigned int usmit_indir_tab); +int iSetSMIT_INDRECT_CTRL_smit_indir_stat(unsigned int usmit_indir_stat); +int iSetSMIT_INDRECT_CTRL_smit_indir_mode(unsigned int usmit_indir_mode); +int iSetSMIT_INDRECT_CTRL_smit_indir_vld(unsigned int usmit_indir_vld); +int iSetSMIT_INDRECT_TIMEOUT_smit_indir_timeout(unsigned int usmit_indir_timeout); +int iSetSMIT_INDRECT_DATA_smit_indir_data(unsigned int usmit_indir_data); +int iSetCFG_MEM_CTRL_BUS0_cfg_mem_ctrl_bus0(unsigned int ucfg_mem_ctrl_bus0); +int iSetCFG_MEM_CTRL_BUS1_cfg_mem_ctrl_bus1(unsigned int ucfg_mem_ctrl_bus1); +int iSetCFG_MEM_CTRL_BUS2_cfg_mem_ctrl_bus2(unsigned int ucfg_mem_ctrl_bus2); +int iSetCFG_MEM_CTRL_BUS3_cfg_mem_ctrl_bus3(unsigned int ucfg_mem_ctrl_bus3); +int iSetCFG_MEM_CTRL_BUS4_cfg_mem_ctrl_bus4(unsigned int ucfg_mem_ctrl_bus4); + +/* Define the union csr_smlc_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_version_u; + +/* Define the union csr_smlc_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_ecc_chk_en : 1; /* [0] */ + u32 smlc_crt_err_inj : 1; /* [1] */ + u32 smlc_uncrt_err_inj : 1; /* [2] */ + u32 rsv_0 : 5; /* [7:3] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cfg0_u; + +/* Define the union csr_smlc_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bypass_cd_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cfg1_u; + +/* Define the union csr_smlc_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bypass_cd_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cfg2_u; + +/* Define the union csr_smlc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_int_vector_u; + +/* Define the union csr_smlc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 2; /* [1:0] */ + u32 rsv_4 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_int_u; + +/* Define the union csr_smlc_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 2; /* [1:0] */ + u32 rsv_5 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_int_mask_u; + +/* Define the union csr_smlc_srf_ov_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_srf_ov_err_u; + +/* Define the union csr_smlc_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_rsv_u; + +/* Define the union csr_smlc_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fiar_1b_ecc_err : 1; /* [0] */ + u32 fiar_1b_ecc_merr : 1; /* [1] */ + u32 fiar_2b_ecc_err : 1; /* [2] */ + u32 fiar_2b_ecc_merr : 1; /* [3] */ + u32 bat_1b_ecc_err : 1; /* [4] */ + u32 bat_1b_ecc_merr : 1; /* [5] */ + u32 bat_2b_ecc_err : 1; /* [6] */ + u32 bat_2b_ecc_merr : 1; /* [7] */ + u32 stb_1b_ecc_err : 1; /* [8] */ + u32 stb_1b_ecc_merr : 1; /* [9] */ + u32 stb_2b_ecc_err : 1; /* [10] */ + u32 stb_2b_ecc_merr : 1; /* [11] */ + u32 cdb0_1b_ecc_err : 1; /* [12] */ + u32 cdb0_1b_ecc_merr : 1; /* [13] */ + u32 cdb0_2b_ecc_err : 1; /* [14] */ + u32 cdb0_2b_ecc_merr : 1; /* [15] */ + u32 cdb1_1b_ecc_err : 1; /* [16] */ + u32 cdb1_1b_ecc_merr : 1; /* [17] */ + u32 cdb1_2b_ecc_err : 1; /* [18] */ + u32 cdb1_2b_ecc_merr : 1; /* [19] */ + u32 pab_1b_ecc_err : 1; /* [20] */ + u32 pab_1b_ecc_merr : 1; /* [21] */ + u32 pab_2b_ecc_err : 1; /* [22] */ + u32 pab_2b_ecc_merr : 1; /* [23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_ecc_err_u; + +/* Define the union csr_smlc_ecc_errpr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fiar_1b_ecc_err_mask : 1; /* [0] */ + u32 fiar_2b_ecc_err_mask : 1; /* [1] */ + u32 bat_1b_ecc_err_mask : 1; /* [2] */ + u32 bat_2b_ecc_err_mask : 1; /* [3] */ + u32 stb_1b_ecc_err_mask : 1; /* [4] */ + u32 stb_2b_ecc_err_mask : 1; /* [5] */ + u32 cdb0_1b_ecc_err_mask : 1; /* [6] */ + u32 cdb0_2b_ecc_err_mask : 1; /* [7] */ + u32 cdb1_1b_ecc_err_mask : 1; /* [8] */ + u32 cdb1_2b_ecc_err_mask : 1; /* [9] */ + u32 pab_1b_ecc_err_mask : 1; /* [10] */ + u32 pab_2b_ecc_err_mask : 1; /* [11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_ecc_errpr_mask_u; + +/* Define the union csr_smlc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_indir_addr : 20; /* [19:0] */ + u32 smlc_indir_tab : 8; /* [27:20] */ + u32 smlc_indir_stat : 2; /* [29:28] */ + u32 smlc_indir_mode : 1; /* [30] */ + u32 smlc_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_indrect_ctrl_u; + +/* Define the union csr_smlc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_indrect_timeout_u; + +/* Define the union csr_smlc_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_indrect_data_u; + +/* Define the union csr_smlc_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt0 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt0_u; + +/* Define the union csr_smlc_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt1 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt1_u; + +/* Define the union csr_smlc_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt2 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt2_u; + +/* Define the union csr_smlc_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt3 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt3_u; + +/* Define the union csr_smlc_cnt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_enable : 4; /* [3:0] */ + u32 cnt0_inst_match_enable : 1; /* [4] */ + u32 cnt1_inst_match_enable : 1; /* [5] */ + u32 cnt2_inst_match_enable : 1; /* [6] */ + u32 cnt3_inst_match_enable : 1; /* [7] */ + u32 cnt0_match_inst_id : 6; /* [13:8] */ + u32 cnt1_match_inst_id : 6; /* [19:14] */ + u32 cnt2_match_inst_id : 6; /* [25:20] */ + u32 cnt3_match_inst_id : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cnt_cfg0_u; + +/* Define the union csr_smlc_cnt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_event_sel : 4; /* [3:0] */ + u32 cnt1_event_sel : 4; /* [7:4] */ + u32 cnt2_event_sel : 4; /* [11:8] */ + u32 cnt3_event_sel : 4; /* [15:12] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cnt_cfg1_u; + +/* Define the union csr_smlc_credit_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_credit : 5; /* [4:0] */ + u32 vc_credit : 2; /* [6:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_credit_ctp_u; + +/* Define the union csr_smlc_fifo_depth_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srf_fifo_depth : 6; /* [5:0] */ + u32 rsv_8 : 4; /* [9:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_fifo_depth_ctp_u; + +/* Define the union csr_smlc_ecc_err_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_error_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_ecc_err_ctp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smlc_version_u smlc_version; /* 0 */ + volatile csr_smlc_cfg0_u smlc_cfg0; /* 4 */ + volatile csr_smlc_cfg1_u smlc_cfg1; /* 8 */ + volatile csr_smlc_cfg2_u smlc_cfg2; /* C */ + volatile csr_smlc_int_vector_u smlc_int_vector; /* 10 */ + volatile csr_smlc_int_u smlc_int; /* 14 */ + volatile csr_smlc_int_mask_u smlc_int_mask; /* 18 */ + volatile csr_smlc_srf_ov_err_u smlc_srf_ov_err; /* 1C */ + volatile csr_smlc_rsv_u smlc_rsv; /* 20 */ + volatile csr_smlc_ecc_err_u smlc_ecc_err; /* 24 */ + volatile csr_smlc_ecc_errpr_mask_u smlc_ecc_errpr_mask; /* 28 */ + volatile csr_smlc_indrect_ctrl_u smlc_indrect_ctrl; /* 2C */ + volatile csr_smlc_indrect_timeout_u smlc_indrect_timeout; /* 30 */ + volatile csr_smlc_indrect_data_u smlc_indrect_data; /* 34 */ + volatile csr_smlc_cnt0_u smlc_cnt0; /* 38 */ + volatile csr_smlc_cnt1_u smlc_cnt1; /* 40 */ + volatile csr_smlc_cnt2_u smlc_cnt2; /* 48 */ + volatile csr_smlc_cnt3_u smlc_cnt3; /* 50 */ + volatile csr_smlc_cnt_cfg0_u smlc_cnt_cfg0; /* 58 */ + volatile csr_smlc_cnt_cfg1_u smlc_cnt_cfg1; /* 5C */ + volatile csr_smlc_credit_ctp_u smlc_credit_ctp; /* 60 */ + volatile csr_smlc_fifo_depth_ctp_u smlc_fifo_depth_ctp; /* 64 */ + volatile csr_smlc_ecc_err_ctp_u smlc_ecc_err_ctp; /* 68 */ +} S_smlc_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smlc_csr */ +extern volatile S_smlc_csr_REGS_TYPE *gopsmlc_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMLC_VERSION_smlc_version(unsigned int usmlc_version); +int iSetSMLC_CFG0_smlc_ecc_chk_en(unsigned int usmlc_ecc_chk_en); +int iSetSMLC_CFG0_smlc_crt_err_inj(unsigned int usmlc_crt_err_inj); +int iSetSMLC_CFG0_smlc_uncrt_err_inj(unsigned int usmlc_uncrt_err_inj); +int iSetSMLC_CFG0_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMLC_CFG0_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMLC_CFG0_mem_ret1n(unsigned int umem_ret1n); +int iSetSMLC_CFG1_bypass_cd_31_0(unsigned int ubypass_cd_31_0); +int iSetSMLC_CFG2_bypass_cd_63_32(unsigned int ubypass_cd_63_32); +int iSetSMLC_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMLC_INT_VECTOR_enable(unsigned int uenable); +int iSetSMLC_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMLC_INT_int_data(unsigned int uint_data); +int iSetSMLC_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMLC_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMLC_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMLC_SRF_OV_ERR_error_bit(unsigned int uerror_bit); +int iSetSMLC_SRF_OV_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMLC_SRF_OV_ERR_sticky(unsigned int usticky); + +int iSetSMLC_ECC_ERR_fiar_1b_ecc_err(unsigned int ufiar_1b_ecc_err); +int iSetSMLC_ECC_ERR_fiar_1b_ecc_merr(unsigned int ufiar_1b_ecc_merr); +int iSetSMLC_ECC_ERR_fiar_2b_ecc_err(unsigned int ufiar_2b_ecc_err); +int iSetSMLC_ECC_ERR_fiar_2b_ecc_merr(unsigned int ufiar_2b_ecc_merr); +int iSetSMLC_ECC_ERR_bat_1b_ecc_err(unsigned int ubat_1b_ecc_err); +int iSetSMLC_ECC_ERR_bat_1b_ecc_merr(unsigned int ubat_1b_ecc_merr); +int iSetSMLC_ECC_ERR_bat_2b_ecc_err(unsigned int ubat_2b_ecc_err); +int iSetSMLC_ECC_ERR_bat_2b_ecc_merr(unsigned int ubat_2b_ecc_merr); +int iSetSMLC_ECC_ERR_stb_1b_ecc_err(unsigned int ustb_1b_ecc_err); +int iSetSMLC_ECC_ERR_stb_1b_ecc_merr(unsigned int ustb_1b_ecc_merr); +int iSetSMLC_ECC_ERR_stb_2b_ecc_err(unsigned int ustb_2b_ecc_err); +int iSetSMLC_ECC_ERR_stb_2b_ecc_merr(unsigned int ustb_2b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb0_1b_ecc_err(unsigned int ucdb0_1b_ecc_err); +int iSetSMLC_ECC_ERR_cdb0_1b_ecc_merr(unsigned int ucdb0_1b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb0_2b_ecc_err(unsigned int ucdb0_2b_ecc_err); +int iSetSMLC_ECC_ERR_cdb0_2b_ecc_merr(unsigned int ucdb0_2b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb1_1b_ecc_err(unsigned int ucdb1_1b_ecc_err); +int iSetSMLC_ECC_ERR_cdb1_1b_ecc_merr(unsigned int ucdb1_1b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb1_2b_ecc_err(unsigned int ucdb1_2b_ecc_err); +int iSetSMLC_ECC_ERR_cdb1_2b_ecc_merr(unsigned int ucdb1_2b_ecc_merr); +int iSetSMLC_ECC_ERR_pab_1b_ecc_err(unsigned int upab_1b_ecc_err); +int iSetSMLC_ECC_ERR_pab_1b_ecc_merr(unsigned int upab_1b_ecc_merr); +int iSetSMLC_ECC_ERR_pab_2b_ecc_err(unsigned int upab_2b_ecc_err); +int iSetSMLC_ECC_ERR_pab_2b_ecc_merr(unsigned int upab_2b_ecc_merr); +int iSetSMLC_ECC_ERRPR_MASK_fiar_1b_ecc_err_mask(unsigned int ufiar_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_fiar_2b_ecc_err_mask(unsigned int ufiar_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_bat_1b_ecc_err_mask(unsigned int ubat_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_bat_2b_ecc_err_mask(unsigned int ubat_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_stb_1b_ecc_err_mask(unsigned int ustb_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_stb_2b_ecc_err_mask(unsigned int ustb_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb0_1b_ecc_err_mask(unsigned int ucdb0_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb0_2b_ecc_err_mask(unsigned int ucdb0_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb1_1b_ecc_err_mask(unsigned int ucdb1_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb1_2b_ecc_err_mask(unsigned int ucdb1_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_pab_1b_ecc_err_mask(unsigned int upab_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_pab_2b_ecc_err_mask(unsigned int upab_2b_ecc_err_mask); +int iSetSMLC_INDRECT_CTRL_smlc_indir_addr(unsigned int usmlc_indir_addr); +int iSetSMLC_INDRECT_CTRL_smlc_indir_tab(unsigned int usmlc_indir_tab); +int iSetSMLC_INDRECT_CTRL_smlc_indir_stat(unsigned int usmlc_indir_stat); +int iSetSMLC_INDRECT_CTRL_smlc_indir_mode(unsigned int usmlc_indir_mode); +int iSetSMLC_INDRECT_CTRL_smlc_indir_vld(unsigned int usmlc_indir_vld); +int iSetSMLC_INDRECT_TIMEOUT_smlc_indir_timeout(unsigned int usmlc_indir_timeout); +int iSetSMLC_INDRECT_DATA_smlc_indir_data(unsigned int usmlc_indir_data); +int iSetSMLC_CNT0_smlc_cnt0(unsigned int usmlc_cnt0); +int iSetSMLC_CNT1_smlc_cnt1(unsigned int usmlc_cnt1); +int iSetSMLC_CNT2_smlc_cnt2(unsigned int usmlc_cnt2); +int iSetSMLC_CNT3_smlc_cnt3(unsigned int usmlc_cnt3); +int iSetSMLC_CNT_CFG0_cnt_enable(unsigned int ucnt_enable); +int iSetSMLC_CNT_CFG0_cnt0_inst_match_enable(unsigned int ucnt0_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt1_inst_match_enable(unsigned int ucnt1_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt2_inst_match_enable(unsigned int ucnt2_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt3_inst_match_enable(unsigned int ucnt3_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt0_match_inst_id(unsigned int ucnt0_match_inst_id); +int iSetSMLC_CNT_CFG0_cnt1_match_inst_id(unsigned int ucnt1_match_inst_id); +int iSetSMLC_CNT_CFG0_cnt2_match_inst_id(unsigned int ucnt2_match_inst_id); +int iSetSMLC_CNT_CFG0_cnt3_match_inst_id(unsigned int ucnt3_match_inst_id); +int iSetSMLC_CNT_CFG1_cnt0_event_sel(unsigned int ucnt0_event_sel); +int iSetSMLC_CNT_CFG1_cnt1_event_sel(unsigned int ucnt1_event_sel); +int iSetSMLC_CNT_CFG1_cnt2_event_sel(unsigned int ucnt2_event_sel); +int iSetSMLC_CNT_CFG1_cnt3_event_sel(unsigned int ucnt3_event_sel); +int iSetSMLC_CREDIT_CTP_smmc_credit(unsigned int usmmc_credit); +int iSetSMLC_CREDIT_CTP_vc_credit(unsigned int uvc_credit); +int iSetSMLC_FIFO_DEPTH_CTP_srf_fifo_depth(unsigned int usrf_fifo_depth); +int iSetSMLC_ECC_ERR_CTP_ecc_error_info(unsigned int uecc_error_info); + +/* Define the union csr_smmc_f_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_version_u; + +/* Define the union csr_smmc_f_mc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_tx_ctp_enb : 1; /* [0] */ + u32 smmc_f_qu_rx_ctp_enb : 1; /* [1] */ + u32 smmc_mc_cla_chk_enb : 1; /* [2] */ + u32 smmc_mc_ecc_parity_enable : 1; /* [3] */ + u32 smmc_qu_return_fifo_bpon_thd : 6; /* [9:4] */ + u32 smmc_qu_return_fifo_bp0ff_thd : 6; /* [15:10] */ + u32 smmc_qu_store_bp_thd : 8; /* [23:16] */ + u32 mem_bank_id_pst : 2; /* [25:24] */ + u32 write_so_ro : 2; /* [27:26] */ + u32 read_so_ro : 2; /* [29:28] */ + u32 rsv_0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cfg_u; + +/* Define the union csr_smmc_f_mc_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cid_src : 15; /* [14:0] */ + u32 bankid_src : 15; /* [29:15] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cfg1_u; + +/* Define the union csr_smmc_hash_seed0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_hash_seed0_u; + +/* Define the union csr_smmc_hash_seed1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_hash_seed1_u; + +/* Define the union csr_smmc_f_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tp_ram_tmod : 8; /* [7:0] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 smmc_f_bank_vld_num : 2; /* [17:16] */ + u32 smmc_f_bank_vld_id : 4; /* [21:18] */ + u32 rsv_2 : 2; /* [23:22] */ + u32 sp_ram_tmod_div2 : 7; /* [30:24] */ + u32 mem_ret1n_div2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_cfg_u; + +/* Define the union csr_smmc_f_mc_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_mc_init : 1; /* [0] */ + u32 smmc_mc_init_start_addr : 14; /* [14:1] */ + u32 smmc_mc_init_end_addr : 14; /* [28:15] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_init_u; + +/* Define the union csr_smmc_f_mc_rf_timeout_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_refill_timeout_interval : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_rf_timeout_interval_u; + +/* Define the union csr_smmc_f_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_int_vector_u; + +/* Define the union csr_smmc_f_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_6 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_int_u; + +/* Define the union csr_smmc_f_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 6; /* [5:0] */ + u32 rsv_7 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_int_mask_u; + +/* Define the union csr_smmc_f_mc_cache_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_tag0_1b_ecc_err : 1; /* [0] */ + u32 mc_tag0_1b_ecc_merr : 1; /* [1] */ + u32 mc_tag0_2b_ecc_err : 1; /* [2] */ + u32 mc_tag0_2b_ecc_merr : 1; /* [3] */ + u32 mc_tag1_1b_ecc_err : 1; /* [4] */ + u32 mc_tag1_1b_ecc_merr : 1; /* [5] */ + u32 mc_tag1_2b_ecc_err : 1; /* [6] */ + u32 mc_tag1_2b_ecc_merr : 1; /* [7] */ + u32 mc_tag2_1b_ecc_err : 1; /* [8] */ + u32 mc_tag2_1b_ecc_merr : 1; /* [9] */ + u32 mc_tag2_2b_ecc_err : 1; /* [10] */ + u32 mc_tag2_2b_ecc_merr : 1; /* [11] */ + u32 mc_tag3_1b_ecc_err : 1; /* [12] */ + u32 mc_tag3_1b_ecc_merr : 1; /* [13] */ + u32 mc_tag3_2b_ecc_err : 1; /* [14] */ + u32 mc_tag3_2b_ecc_merr : 1; /* [15] */ + u32 mc_data0_1b_ecc_err : 1; /* [16] */ + u32 mc_data0_1b_ecc_merr : 1; /* [17] */ + u32 mc_data0_2b_ecc_err : 1; /* [18] */ + u32 mc_data0_2b_ecc_merr : 1; /* [19] */ + u32 mc_data1_1b_ecc_err : 1; /* [20] */ + u32 mc_data1_1b_ecc_merr : 1; /* [21] */ + u32 mc_data1_2b_ecc_err : 1; /* [22] */ + u32 mc_data1_2b_ecc_merr : 1; /* [23] */ + u32 mc_data2_1b_ecc_err : 1; /* [24] */ + u32 mc_data2_1b_ecc_merr : 1; /* [25] */ + u32 mc_data2_2b_ecc_err : 1; /* [26] */ + u32 mc_data2_2b_ecc_merr : 1; /* [27] */ + u32 mc_data3_1b_ecc_err : 1; /* [28] */ + u32 mc_data3_1b_ecc_merr : 1; /* [29] */ + u32 mc_data3_2b_ecc_err : 1; /* [30] */ + u32 mc_data3_2b_ecc_merr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cache_err_u; + +/* Define the union csr_smmc_f_mc_cache_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_tag0_1b_ecc_err_mask : 1; /* [0] */ + u32 mc_tag0_2b_ecc_err_mask : 1; /* [1] */ + u32 mc_tag1_1b_ecc_err_mask : 1; /* [2] */ + u32 mc_tag1_2b_ecc_err_mask : 1; /* [3] */ + u32 mc_tag2_1b_ecc_err_mask : 1; /* [4] */ + u32 mc_tag2_2b_ecc_err_mask : 1; /* [5] */ + u32 mc_tag3_1b_ecc_err_mask : 1; /* [6] */ + u32 mc_tag3_2b_ecc_err_mask : 1; /* [7] */ + u32 mc_data0_1b_ecc_err_mask : 1; /* [8] */ + u32 mc_data0_2b_ecc_err_mask : 1; /* [9] */ + u32 mc_data1_1b_ecc_err_mask : 1; /* [10] */ + u32 mc_data1_2b_ecc_err_mask : 1; /* [11] */ + u32 mc_data2_1b_ecc_err_mask : 1; /* [12] */ + u32 mc_data2_2b_ecc_err_mask : 1; /* [13] */ + u32 mc_data3_1b_ecc_err_mask : 1; /* [14] */ + u32 mc_data3_2b_ecc_err_mask : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cache_mask_u; + +/* Define the union csr_smmc_f_mc_cache_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cache_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cache_err_info_u; + +/* Define the union csr_smmc_f_buffer_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_qu_vfa_1b_ecc_err : 1; /* [0] */ + u32 mc_qu_vfa_1b_ecc_merr : 1; /* [1] */ + u32 mc_qu_vfa_2b_ecc_err : 1; /* [2] */ + u32 mc_qu_vfa_2b_ecc_merr : 1; /* [3] */ + u32 mc_eng_stbuf_1b_ecc_err : 1; /* [4] */ + u32 mc_eng_stbuf_1b_ecc_merr : 1; /* [5] */ + u32 mc_eng_stbuf_2b_ecc_err : 1; /* [6] */ + u32 mc_eng_stbuf_2b_ecc_merr : 1; /* [7] */ + u32 mc_qu_stbuf_1b_ecc_err : 1; /* [8] */ + u32 mc_qu_stbuf_1b_ecc_merr : 1; /* [9] */ + u32 mc_qu_stbuf_2b_ecc_err : 1; /* [10] */ + u32 mc_qu_stbuf_2b_ecc_merr : 1; /* [11] */ + u32 mc_qu_lrn_1b_ecc_err : 1; /* [12] */ + u32 mc_qu_lrn_1b_ecc_merr : 1; /* [13] */ + u32 mc_qu_lrn_2b_ecc_err : 1; /* [14] */ + u32 mc_qu_lrn_2b_ecc_merr : 1; /* [15] */ + u32 mc_qu_datafifo_1b_ecc_err : 1; /* [16] */ + u32 mc_qu_datafifo_1b_ecc_merr : 1; /* [17] */ + u32 mc_qu_datafifo_2b_ecc_err : 1; /* [18] */ + u32 mc_qu_datafifo_2b_ecc_merr : 1; /* [19] */ + u32 mc_rfbuf_1b_ecc_err : 1; /* [20] */ + u32 mc_rfbuf_1b_ecc_merr : 1; /* [21] */ + u32 mc_rfbuf_2b_ecc_err : 1; /* [22] */ + u32 mc_rfbuf_2b_ecc_merr : 1; /* [23] */ + u32 vc_smxtf_buf_1b_ecc_err : 1; /* [24] */ + u32 vc_smxtf_buf_1b_ecc_merr : 1; /* [25] */ + u32 vc_smxtf_buf_2b_ecc_err : 1; /* [26] */ + u32 vc_smxtf_buf_2b_ecc_merr : 1; /* [27] */ + u32 directwqe_err : 1; /* [28] */ + u32 directwqe_merr : 1; /* [29] */ + u32 fifo_ovf_err : 1; /* [30] */ + u32 fifo_ovf_merr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_buffer_err_u; + +/* Define the union csr_smmc_f_buffer_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_qu_vfa_1b_ecc_err_mask : 1; /* [0] */ + u32 mc_qu_vfa_2b_ecc_err_mask : 1; /* [1] */ + u32 mc_eng_stbuf_1b_ecc_err_mask : 1; /* [2] */ + u32 mc_eng_stbuf_2b_ecc_err_mask : 1; /* [3] */ + u32 mc_qu_stbuf_1b_ecc_err_mask : 1; /* [4] */ + u32 mc_qu_stbuf_2b_ecc_err_mask : 1; /* [5] */ + u32 mc_qu_lrn_1b_ecc_err_mask : 1; /* [6] */ + u32 mc_qu_lrn_2b_ecc_err_mask : 1; /* [7] */ + u32 mc_qu_datafifo_1b_ecc_err_mask : 1; /* [8] */ + u32 mc_qu_datafifo_2b_ecc_err_mask : 1; /* [9] */ + u32 mc_rfbuf_1b_ecc_err_mask : 1; /* [10] */ + u32 mc_rfbuf_2b_ecc_err_mask : 1; /* [11] */ + u32 vc_smxtf_buf_1b_ecc_err_mask : 1; /* [12] */ + u32 vc_smxtf_buf_2b_ecc_err_mask : 1; /* [13] */ + u32 directwqe_err_mask : 1; /* [14] */ + u32 fifo_ovf_err_mask : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_buffer_mask_u; + +/* Define the union csr_smmc_f_buffer_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_buffer_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_buffer_err_info_u; + +/* Define the union csr_smmc_f_bus_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_rf_timeout_err : 1; /* [0] */ + u32 mc_rf_timeout_merr : 1; /* [1] */ + u32 mc_rf_rtn_err : 1; /* [2] */ + u32 mc_rf_rtn_merr : 1; /* [3] */ + u32 qpc_ring_e01_err : 1; /* [4] */ + u32 qpc_ring_e01_merr : 1; /* [5] */ + u32 qu_lrn_fifo_1bit_ecc_err : 1; /* [6] */ + u32 qu_lrn_fifo_1bit_ecc_merr : 1; /* [7] */ + u32 qu_lrn_fifo_2bit_ecc_err : 1; /* [8] */ + u32 qu_lrn_fifo_2bit_ecc_merr : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_bus_err_u; + +/* Define the union csr_smmc_f_bus_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_rf_timeout_err_mask : 1; /* [0] */ + u32 mc_rf_rtn_err_mask : 1; /* [1] */ + u32 qpc_ring_e01_err_mask : 1; /* [2] */ + u32 qu_lrn_fifo_1bit_ecc_err_mask : 1; /* [3] */ + u32 qu_lrn_fifo_2bit_ecc_err_mask : 1; /* [4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_bus_mask_u; + +/* Define the union csr_smmc_f_mc_multi_hit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_multi_hit_err_u; + +/* Define the union csr_smmc_f_vc_cache_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_wb0_1b_ecc_err : 1; /* [0] */ + u32 vc_wb0_1b_ecc_merr : 1; /* [1] */ + u32 vc_wb0_2b_ecc_err : 1; /* [2] */ + u32 vc_wb0_2b_ecc_merr : 1; /* [3] */ + u32 vc_wb1_1b_ecc_err : 1; /* [4] */ + u32 vc_wb1_1b_ecc_merr : 1; /* [5] */ + u32 vc_wb1_2b_ecc_err : 1; /* [6] */ + u32 vc_wb1_2b_ecc_merr : 1; /* [7] */ + u32 vc_wb2_1b_ecc_err : 1; /* [8] */ + u32 vc_wb2_1b_ecc_merr : 1; /* [9] */ + u32 vc_wb2_2b_ecc_err : 1; /* [10] */ + u32 vc_wb2_2b_ecc_merr : 1; /* [11] */ + u32 vc_wb3_1b_ecc_err : 1; /* [12] */ + u32 vc_wb3_1b_ecc_merr : 1; /* [13] */ + u32 vc_wb3_2b_ecc_err : 1; /* [14] */ + u32 vc_wb3_2b_ecc_merr : 1; /* [15] */ + u32 vc_data0_1b_ecc_err : 1; /* [16] */ + u32 vc_data0_1b_ecc_merr : 1; /* [17] */ + u32 vc_data0_2b_ecc_err : 1; /* [18] */ + u32 vc_data0_2b_ecc_merr : 1; /* [19] */ + u32 vc_data1_1b_ecc_err : 1; /* [20] */ + u32 vc_data1_1b_ecc_merr : 1; /* [21] */ + u32 vc_data1_2b_ecc_err : 1; /* [22] */ + u32 vc_data1_2b_ecc_merr : 1; /* [23] */ + u32 vc_data2_1b_ecc_err : 1; /* [24] */ + u32 vc_data2_1b_ecc_merr : 1; /* [25] */ + u32 vc_data2_2b_ecc_err : 1; /* [26] */ + u32 vc_data2_2b_ecc_merr : 1; /* [27] */ + u32 vc_data3_1b_ecc_err : 1; /* [28] */ + u32 vc_data3_1b_ecc_merr : 1; /* [29] */ + u32 vc_data3_2b_ecc_err : 1; /* [30] */ + u32 vc_data3_2b_ecc_merr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_cache_err_u; + +/* Define the union csr_smmc_f_vc_cache_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_wb0_1b_ecc_err_mask : 1; /* [0] */ + u32 vc_wb0_2b_ecc_err_mask : 1; /* [1] */ + u32 vc_wb1_1b_ecc_err_mask : 1; /* [2] */ + u32 vc_wb1_2b_ecc_err_mask : 1; /* [3] */ + u32 vc_wb2_1b_ecc_err_mask : 1; /* [4] */ + u32 vc_wb2_2b_ecc_err_mask : 1; /* [5] */ + u32 vc_wb3_1b_ecc_err_mask : 1; /* [6] */ + u32 vc_wb3_2b_ecc_err_mask : 1; /* [7] */ + u32 vc_data0_1b_ecc_err_mask : 1; /* [8] */ + u32 vc_data0_2b_ecc_err_mask : 1; /* [9] */ + u32 vc_data1_1b_ecc_err_mask : 1; /* [10] */ + u32 vc_data1_2b_ecc_err_mask : 1; /* [11] */ + u32 vc_data2_1b_ecc_err_mask : 1; /* [12] */ + u32 vc_data2_2b_ecc_err_mask : 1; /* [13] */ + u32 vc_data3_1b_ecc_err_mask : 1; /* [14] */ + u32 vc_data3_2b_ecc_err_mask : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_cache_mask_u; + +/* Define the union csr_smmc_f_vc_cache_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_cache_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_cache_err_info_u; + +/* Define the union csr_smmc_f_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_addr : 24; /* [23:0] */ + u32 smmc_f_indir_tab : 4; /* [27:24] */ + u32 smmc_f_indir_stat : 2; /* [29:28] */ + u32 smmc_f_indir_mode : 1; /* [30] */ + u32 smmc_f_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_indrect_ctrl_u; + +/* Define the union csr_smmc_f_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_indrect_timeout_u; + +/* Define the union csr_smmc_f_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_indrect_data_u; + +/* Define the union csr_smmc_f_mc_cnt_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_mc_cnt_enb : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_enb_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel_enb_grp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_mc_cnt_event_sel_enb0 : 8; /* [7:0] */ + u32 smmc_f_mc_cnt_event_sel_enb1 : 8; /* [15:8] */ + u32 smmc_f_mc_cnt_event_sel_enb2 : 8; /* [23:16] */ + u32 smmc_f_mc_cnt_event_sel_enb3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel_enb_grp0_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel_enb_grp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_mc_cnt_event_sel_enb4 : 8; /* [7:0] */ + u32 smmc_f_mc_cnt_event_sel_enb5 : 8; /* [15:8] */ + u32 smmc_f_mc_cnt_event_sel_enb6 : 8; /* [23:16] */ + u32 smmc_f_mc_cnt_event_sel_enb7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel_enb_grp1_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel0_vf_id : 10; /* [9:0] */ + u32 rsv_8 : 5; /* [14:10] */ + u32 mc_cnt_event_sel0_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel0_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel0_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel0_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel0_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel0_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel0_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel1_vf_id : 10; /* [9:0] */ + u32 rsv_9 : 5; /* [14:10] */ + u32 mc_cnt_event_sel1_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel1_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel1_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel1_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel1_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel1_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel1_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel2_vf_id : 10; /* [9:0] */ + u32 rsv_10 : 5; /* [14:10] */ + u32 mc_cnt_event_sel2_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel2_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel2_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel2_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel2_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel2_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel2_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel3_vf_id : 10; /* [9:0] */ + u32 rsv_11 : 5; /* [14:10] */ + u32 mc_cnt_event_sel3_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel3_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel3_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel3_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel3_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel3_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel3_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel4_vf_id : 10; /* [9:0] */ + u32 rsv_12 : 5; /* [14:10] */ + u32 mc_cnt_event_sel4_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel4_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel4_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel4_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel4_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel4_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel4_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel5_vf_id : 10; /* [9:0] */ + u32 rsv_13 : 5; /* [14:10] */ + u32 mc_cnt_event_sel5_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel5_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel5_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel5_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel5_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel5_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel5_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel6_vf_id : 10; /* [9:0] */ + u32 rsv_14 : 5; /* [14:10] */ + u32 mc_cnt_event_sel6_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel6_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel6_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel6_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel6_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel6_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel6_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel7_vf_id : 10; /* [9:0] */ + u32 rsv_15 : 5; /* [14:10] */ + u32 mc_cnt_event_sel7_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel7_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel7_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel7_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel7_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel7_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel7_u; + +/* Define the union csr_smmc_f_mc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_init_done : 1; /* [0] */ + u32 mc_free_tag_num : 7; /* [7:1] */ + u32 qu_rx_flit_ctp_done : 1; /* [8] */ + u32 qu_tx_flit_ctp_done : 1; /* [9] */ + u32 smmc_rf_timeout : 1; /* [10] */ + u32 rsv_16 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_status_u; + +/* Define the union csr_smmc_f_mc_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt0 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt0_u; + +/* Define the union csr_smmc_f_mc_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt1 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt1_u; + +/* Define the union csr_smmc_f_mc_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt2 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt2_u; + +/* Define the union csr_smmc_f_mc_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt3 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt3_u; + +/* Define the union csr_smmc_f_mc_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt4 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt4_u; + +/* Define the union csr_smmc_f_mc_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt5 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt5_u; + +/* Define the union csr_smmc_f_mc_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt6 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt6_u; + +/* Define the union csr_smmc_f_mc_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt7 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt7_u; + +/* Define the union csr_smmc_f_vc_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_wb_data_fifo_depth : 5; /* [4:0] */ + u32 vc1_wb_data_fifo_depth : 5; /* [9:5] */ + u32 vc2_wb_data_fifo_depth : 5; /* [14:10] */ + u32 vc3_wb_data_fifo_depth : 5; /* [19:15] */ + u32 vc0_wb_ctrl_fifo_depth : 3; /* [22:20] */ + u32 vc1_wb_ctrl_fifo_depth : 3; /* [25:23] */ + u32 vc2_wb_ctrl_fifo_depth : 3; /* [28:26] */ + u32 vc3_wb_ctrl_fifo_depth : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_fifo_depth0_u; + +/* Define the union csr_smmc_f_vc_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_ctrl_fifo_depth : 2; /* [1:0] */ + u32 vc1_ctrl_fifo_depth : 2; /* [3:2] */ + u32 vc2_ctrl_fifo_depth : 2; /* [5:4] */ + u32 vc3_ctrl_fifo_depth : 2; /* [7:6] */ + u32 vc0_data_fifo_depth : 2; /* [9:8] */ + u32 vc1_data_fifo_depth : 2; /* [11:10] */ + u32 vc2_data_fifo_depth : 2; /* [13:12] */ + u32 vc3_data_fifo_depth : 2; /* [15:14] */ + u32 smxtf_fifo_depth : 6; /* [21:16] */ + u32 vc_crdt_from_smit : 3; /* [24:22] */ + u32 data_credit_from_qu : 6; /* [30:25] */ + u32 rsv_17 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_fifo_depth1_u; + +/* Define the union csr_smmc_f_mc_fifo1_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_cmd_fifo_depth : 4; /* [3:0] */ + u32 qu_data_fifo_depth : 6; /* [9:4] */ + u32 lrb0_fifo_depth : 6; /* [15:10] */ + u32 lrb1_fifo_depth : 6; /* [21:16] */ + u32 lrb2_fifo_depth : 6; /* [27:22] */ + u32 rsv_18 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_fifo1_depth_u; + +/* Define the union csr_smmc_f_mc_fifo2_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_return_fifo_depth : 6; /* [5:0] */ + u32 qu_return_fifo_bp : 1; /* [6] */ + u32 qu_store_buffer_bp : 1; /* [7] */ + u32 lrb3_fifo_depth : 6; /* [13:8] */ + u32 rfbuf_credit : 9; /* [22:14] */ + u32 qu_store_buffer_depth : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_fifo2_depth_u; + +/* Define the union csr_smmc_f_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_vc0_crt_err_inj : 1; /* [0] */ + u32 smmc_vc0_uncrt_err_inj : 1; /* [1] */ + u32 smmc_vc1_crt_err_inj : 1; /* [2] */ + u32 smmc_vc1_uncrt_err_inj : 1; /* [3] */ + u32 smmc_vc2_crt_err_inj : 1; /* [4] */ + u32 smmc_vc2_uncrt_err_inj : 1; /* [5] */ + u32 smmc_vc3_crt_err_inj : 1; /* [6] */ + u32 smmc_vc3_uncrt_err_inj : 1; /* [7] */ + u32 smmc_mc0_crt_err_inj : 1; /* [8] */ + u32 smmc_mc0_uncrt_err_inj : 1; /* [9] */ + u32 smmc_mc1_crt_err_inj : 1; /* [10] */ + u32 smmc_mc1_uncrt_err_inj : 1; /* [11] */ + u32 smmc_mc2_crt_err_inj : 1; /* [12] */ + u32 smmc_mc2_uncrt_err_inj : 1; /* [13] */ + u32 smmc_mc3_crt_err_inj : 1; /* [14] */ + u32 smmc_mc3_uncrt_err_inj : 1; /* [15] */ + u32 smmc_qu_intf_crt_err_inj : 1; /* [16] */ + u32 smmc_qu_intf_uncrt_err_inj : 1; /* [17] */ + u32 smmc_rf_buf_crt_err_inj : 1; /* [18] */ + u32 smmc_rf_buf_uncrt_err_inj : 1; /* [19] */ + u32 smmc_vfa_crt_err_inj : 1; /* [20] */ + u32 smmc_vfa_uncrt_err_inj : 1; /* [21] */ + u32 smmc_stb_crt_err_inj : 1; /* [22] */ + u32 smmc_stb_uncrt_err_inj : 1; /* [23] */ + u32 smmc_smxtfb_crt_err_inj : 1; /* [24] */ + u32 smmc_smxtfb_uncrt_err_inj : 1; /* [25] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_err_inj_u; + +/* Define the union csr_smmc_f_gpa_trans_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_gpa_trans_err_u; + +/* Define the union csr_smmc_f_qu_intf_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_intf_tx_cnt_cfg : 16; /* [15:0] */ + u32 smmc_f_qu_intf_rx_cnt_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_qu_intf_cnt_cfg_u; + +/* Define the union csr_smmc_f_qu_intf_rx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_intf_rx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_qu_intf_rx_cnt_u; + +/* Define the union csr_smmc_f_qu_intf_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_intf_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_qu_intf_tx_cnt_u; + +/* Define the union csr_smmc_f_mc_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_rsc_cnt_mix_en : 1; /* [0] */ + u32 smmc_f_rtt_cnt_type : 1; /* [1] */ + u32 smmc_f_rtt_cnt_enb : 1; /* [2] */ + u32 smmc_f_rf_err_ctp_clr : 1; /* [3] */ + u32 smf_common_mem_power_mode : 6; /* [9:4] */ + u32 mc_refill_timeout_enb : 1; /* [10] */ + u32 bypass_smvc : 1; /* [11] */ + u32 rsv_20 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cfg2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smmc_f_version_u smmc_f_version; /* 0 */ + volatile csr_smmc_f_mc_cfg_u smmc_f_mc_cfg; /* 4 */ + volatile csr_smmc_f_mc_cfg1_u smmc_f_mc_cfg1; /* 8 */ + volatile csr_smmc_hash_seed0_u smmc_hash_seed0; /* C */ + volatile csr_smmc_hash_seed1_u smmc_hash_seed1; /* 10 */ + volatile csr_smmc_f_cfg_u smmc_f_cfg; /* 14 */ + volatile csr_smmc_f_mc_init_u smmc_f_mc_init; /* 18 */ + volatile csr_smmc_f_mc_rf_timeout_interval_u smmc_f_mc_rf_timeout_interval; /* 1C */ + volatile csr_smmc_f_int_vector_u smmc_f_int_vector; /* 20 */ + volatile csr_smmc_f_int_u smmc_f_int; /* 24 */ + volatile csr_smmc_f_int_mask_u smmc_f_int_mask; /* 28 */ + volatile csr_smmc_f_mc_cache_err_u smmc_f_mc_cache_err; /* 2C */ + volatile csr_smmc_f_mc_cache_mask_u smmc_f_mc_cache_mask; /* 30 */ + volatile csr_smmc_f_mc_cache_err_info_u smmc_f_mc_cache_err_info; /* 34 */ + volatile csr_smmc_f_buffer_err_u smmc_f_buffer_err; /* 38 */ + volatile csr_smmc_f_buffer_mask_u smmc_f_buffer_mask; /* 3C */ + volatile csr_smmc_f_buffer_err_info_u smmc_f_buffer_err_info; /* 40 */ + volatile csr_smmc_f_bus_err_u smmc_f_bus_err; /* 44 */ + volatile csr_smmc_f_bus_mask_u smmc_f_bus_mask; /* 48 */ + volatile csr_smmc_f_mc_multi_hit_err_u smmc_f_mc_multi_hit_err; /* 4C */ + volatile csr_smmc_f_vc_cache_err_u smmc_f_vc_cache_err; /* 50 */ + volatile csr_smmc_f_vc_cache_mask_u smmc_f_vc_cache_mask; /* 54 */ + volatile csr_smmc_f_vc_cache_err_info_u smmc_f_vc_cache_err_info; /* 58 */ + volatile csr_smmc_f_indrect_ctrl_u smmc_f_indrect_ctrl; /* 5C */ + volatile csr_smmc_f_indrect_timeout_u smmc_f_indrect_timeout; /* 60 */ + volatile csr_smmc_f_indrect_data_u smmc_f_indrect_data; /* 64 */ + volatile csr_smmc_f_mc_cnt_enb_u smmc_f_mc_cnt_enb; /* 68 */ + volatile csr_smmc_f_mc_cnt_event_sel_enb_grp0_u smmc_f_mc_cnt_event_sel_enb_grp0; /* 6C */ + volatile csr_smmc_f_mc_cnt_event_sel_enb_grp1_u smmc_f_mc_cnt_event_sel_enb_grp1; /* 70 */ + volatile csr_smmc_f_mc_cnt_event_sel0_u smmc_f_mc_cnt_event_sel0; /* 74 */ + volatile csr_smmc_f_mc_cnt_event_sel1_u smmc_f_mc_cnt_event_sel1; /* 78 */ + volatile csr_smmc_f_mc_cnt_event_sel2_u smmc_f_mc_cnt_event_sel2; /* 7C */ + volatile csr_smmc_f_mc_cnt_event_sel3_u smmc_f_mc_cnt_event_sel3; /* 80 */ + volatile csr_smmc_f_mc_cnt_event_sel4_u smmc_f_mc_cnt_event_sel4; /* 84 */ + volatile csr_smmc_f_mc_cnt_event_sel5_u smmc_f_mc_cnt_event_sel5; /* 88 */ + volatile csr_smmc_f_mc_cnt_event_sel6_u smmc_f_mc_cnt_event_sel6; /* 8C */ + volatile csr_smmc_f_mc_cnt_event_sel7_u smmc_f_mc_cnt_event_sel7; /* 90 */ + volatile csr_smmc_f_mc_status_u smmc_f_mc_status; /* 94 */ + volatile csr_smmc_f_mc_cnt0_u smmc_f_mc_cnt0; /* 98 */ + volatile csr_smmc_f_mc_cnt1_u smmc_f_mc_cnt1; /* A0 */ + volatile csr_smmc_f_mc_cnt2_u smmc_f_mc_cnt2; /* A8 */ + volatile csr_smmc_f_mc_cnt3_u smmc_f_mc_cnt3; /* B0 */ + volatile csr_smmc_f_mc_cnt4_u smmc_f_mc_cnt4; /* B8 */ + volatile csr_smmc_f_mc_cnt5_u smmc_f_mc_cnt5; /* C0 */ + volatile csr_smmc_f_mc_cnt6_u smmc_f_mc_cnt6; /* C8 */ + volatile csr_smmc_f_mc_cnt7_u smmc_f_mc_cnt7; /* D0 */ + volatile csr_smmc_f_vc_fifo_depth0_u smmc_f_vc_fifo_depth0; /* D8 */ + volatile csr_smmc_f_vc_fifo_depth1_u smmc_f_vc_fifo_depth1; /* DC */ + volatile csr_smmc_f_mc_fifo1_depth_u smmc_f_mc_fifo1_depth; /* E0 */ + volatile csr_smmc_f_mc_fifo2_depth_u smmc_f_mc_fifo2_depth; /* E4 */ + volatile csr_smmc_f_err_inj_u smmc_f_err_inj; /* E8 */ + volatile csr_smmc_f_gpa_trans_err_u smmc_f_gpa_trans_err; /* EC */ + volatile csr_smmc_f_qu_intf_cnt_cfg_u smmc_f_qu_intf_cnt_cfg; /* F0 */ + volatile csr_smmc_f_qu_intf_rx_cnt_u smmc_f_qu_intf_rx_cnt; /* F4 */ + volatile csr_smmc_f_qu_intf_tx_cnt_u smmc_f_qu_intf_tx_cnt; /* F8 */ + volatile csr_smmc_f_mc_cfg2_u smmc_f_mc_cfg2; /* FC */ +} S_smmc_f_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smmc_f_csr */ +extern volatile S_smmc_f_csr_REGS_TYPE *gopsmmc_f_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMMC_F_VERSION_smmc_f_version(unsigned int usmmc_f_version); +int iSetSMMC_F_MC_CFG_smmc_f_qu_tx_ctp_enb(unsigned int usmmc_f_qu_tx_ctp_enb); +int iSetSMMC_F_MC_CFG_smmc_f_qu_rx_ctp_enb(unsigned int usmmc_f_qu_rx_ctp_enb); +int iSetSMMC_F_MC_CFG_smmc_mc_cla_chk_enb(unsigned int usmmc_mc_cla_chk_enb); +int iSetSMMC_F_MC_CFG_smmc_mc_ecc_parity_enable(unsigned int usmmc_mc_ecc_parity_enable); +int iSetSMMC_F_MC_CFG_smmc_qu_return_fifo_bpon_thd(unsigned int usmmc_qu_return_fifo_bpon_thd); +int iSetSMMC_F_MC_CFG_smmc_qu_return_fifo_bp0ff_thd(unsigned int usmmc_qu_return_fifo_bp0ff_thd); +int iSetSMMC_F_MC_CFG_smmc_qu_store_bp_thd(unsigned int usmmc_qu_store_bp_thd); +int iSetSMMC_F_MC_CFG_mem_bank_id_pst(unsigned int umem_bank_id_pst); +int iSetSMMC_F_MC_CFG_write_so_ro(unsigned int uwrite_so_ro); +int iSetSMMC_F_MC_CFG_read_so_ro(unsigned int uread_so_ro); +int iSetSMMC_F_MC_CFG1_cid_src(unsigned int ucid_src); +int iSetSMMC_F_MC_CFG1_bankid_src(unsigned int ubankid_src); +int iSetSMMC_HASH_SEED0_hash_seed_cfg0(unsigned int uhash_seed_cfg0); +int iSetSMMC_HASH_SEED1_hash_seed_cfg1(unsigned int uhash_seed_cfg1); +int iSetSMMC_F_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMMC_F_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMMC_F_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMMC_F_CFG_smmc_f_bank_vld_num(unsigned int usmmc_f_bank_vld_num); +int iSetSMMC_F_CFG_smmc_f_bank_vld_id(unsigned int usmmc_f_bank_vld_id); +int iSetSMMC_F_CFG_sp_ram_tmod_div2(unsigned int usp_ram_tmod_div2); +int iSetSMMC_F_CFG_mem_ret1n_div2(unsigned int umem_ret1n_div2); +int iSetSMMC_F_MC_INIT_smmc_mc_init(unsigned int usmmc_mc_init); +int iSetSMMC_F_MC_INIT_smmc_mc_init_start_addr(unsigned int usmmc_mc_init_start_addr); +int iSetSMMC_F_MC_INIT_smmc_mc_init_end_addr(unsigned int usmmc_mc_init_end_addr); +int iSetSMMC_F_MC_RF_TIMEOUT_INTERVAL_mc_refill_timeout_interval(unsigned int umc_refill_timeout_interval); +int iSetSMMC_F_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMMC_F_INT_VECTOR_enable(unsigned int uenable); +int iSetSMMC_F_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMMC_F_INT_int_data(unsigned int uint_data); +int iSetSMMC_F_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_F_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMMC_F_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_1b_ecc_err(unsigned int umc_tag0_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_1b_ecc_merr(unsigned int umc_tag0_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_2b_ecc_err(unsigned int umc_tag0_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_2b_ecc_merr(unsigned int umc_tag0_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_1b_ecc_err(unsigned int umc_tag1_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_1b_ecc_merr(unsigned int umc_tag1_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_2b_ecc_err(unsigned int umc_tag1_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_2b_ecc_merr(unsigned int umc_tag1_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_1b_ecc_err(unsigned int umc_tag2_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_1b_ecc_merr(unsigned int umc_tag2_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_2b_ecc_err(unsigned int umc_tag2_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_2b_ecc_merr(unsigned int umc_tag2_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_1b_ecc_err(unsigned int umc_tag3_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_1b_ecc_merr(unsigned int umc_tag3_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_2b_ecc_err(unsigned int umc_tag3_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_2b_ecc_merr(unsigned int umc_tag3_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_1b_ecc_err(unsigned int umc_data0_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_1b_ecc_merr(unsigned int umc_data0_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_2b_ecc_err(unsigned int umc_data0_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_2b_ecc_merr(unsigned int umc_data0_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_1b_ecc_err(unsigned int umc_data1_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_1b_ecc_merr(unsigned int umc_data1_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_2b_ecc_err(unsigned int umc_data1_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_2b_ecc_merr(unsigned int umc_data1_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_1b_ecc_err(unsigned int umc_data2_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_1b_ecc_merr(unsigned int umc_data2_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_2b_ecc_err(unsigned int umc_data2_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_2b_ecc_merr(unsigned int umc_data2_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_1b_ecc_err(unsigned int umc_data3_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_1b_ecc_merr(unsigned int umc_data3_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_2b_ecc_err(unsigned int umc_data3_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_2b_ecc_merr(unsigned int umc_data3_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag0_1b_ecc_err_mask(unsigned int umc_tag0_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag0_2b_ecc_err_mask(unsigned int umc_tag0_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag1_1b_ecc_err_mask(unsigned int umc_tag1_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag1_2b_ecc_err_mask(unsigned int umc_tag1_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag2_1b_ecc_err_mask(unsigned int umc_tag2_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag2_2b_ecc_err_mask(unsigned int umc_tag2_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag3_1b_ecc_err_mask(unsigned int umc_tag3_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag3_2b_ecc_err_mask(unsigned int umc_tag3_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data0_1b_ecc_err_mask(unsigned int umc_data0_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data0_2b_ecc_err_mask(unsigned int umc_data0_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data1_1b_ecc_err_mask(unsigned int umc_data1_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data1_2b_ecc_err_mask(unsigned int umc_data1_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data2_1b_ecc_err_mask(unsigned int umc_data2_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data2_2b_ecc_err_mask(unsigned int umc_data2_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data3_1b_ecc_err_mask(unsigned int umc_data3_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data3_2b_ecc_err_mask(unsigned int umc_data3_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_ERR_INFO_mc_cache_err_info(unsigned int umc_cache_err_info); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_1b_ecc_err(unsigned int umc_qu_vfa_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_1b_ecc_merr(unsigned int umc_qu_vfa_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_2b_ecc_err(unsigned int umc_qu_vfa_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_2b_ecc_merr(unsigned int umc_qu_vfa_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_1b_ecc_err(unsigned int umc_eng_stbuf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_1b_ecc_merr(unsigned int umc_eng_stbuf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_2b_ecc_err(unsigned int umc_eng_stbuf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_2b_ecc_merr(unsigned int umc_eng_stbuf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_1b_ecc_err(unsigned int umc_qu_stbuf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_1b_ecc_merr(unsigned int umc_qu_stbuf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_2b_ecc_err(unsigned int umc_qu_stbuf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_2b_ecc_merr(unsigned int umc_qu_stbuf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_1b_ecc_err(unsigned int umc_qu_lrn_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_1b_ecc_merr(unsigned int umc_qu_lrn_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_2b_ecc_err(unsigned int umc_qu_lrn_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_2b_ecc_merr(unsigned int umc_qu_lrn_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_1b_ecc_err(unsigned int umc_qu_datafifo_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_1b_ecc_merr(unsigned int umc_qu_datafifo_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_2b_ecc_err(unsigned int umc_qu_datafifo_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_2b_ecc_merr(unsigned int umc_qu_datafifo_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_1b_ecc_err(unsigned int umc_rfbuf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_1b_ecc_merr(unsigned int umc_rfbuf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_2b_ecc_err(unsigned int umc_rfbuf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_2b_ecc_merr(unsigned int umc_rfbuf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_1b_ecc_err(unsigned int uvc_smxtf_buf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_1b_ecc_merr(unsigned int uvc_smxtf_buf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_2b_ecc_err(unsigned int uvc_smxtf_buf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_2b_ecc_merr(unsigned int uvc_smxtf_buf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_directwqe_err(unsigned int udirectwqe_err); +int iSetSMMC_F_BUFFER_ERR_directwqe_merr(unsigned int udirectwqe_merr); +int iSetSMMC_F_BUFFER_ERR_fifo_ovf_err(unsigned int ufifo_ovf_err); +int iSetSMMC_F_BUFFER_ERR_fifo_ovf_merr(unsigned int ufifo_ovf_merr); +int iSetSMMC_F_BUFFER_MASK_mc_qu_vfa_1b_ecc_err_mask(unsigned int umc_qu_vfa_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_vfa_2b_ecc_err_mask(unsigned int umc_qu_vfa_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_eng_stbuf_1b_ecc_err_mask(unsigned int umc_eng_stbuf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_eng_stbuf_2b_ecc_err_mask(unsigned int umc_eng_stbuf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_stbuf_1b_ecc_err_mask(unsigned int umc_qu_stbuf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_stbuf_2b_ecc_err_mask(unsigned int umc_qu_stbuf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_lrn_1b_ecc_err_mask(unsigned int umc_qu_lrn_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_lrn_2b_ecc_err_mask(unsigned int umc_qu_lrn_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_datafifo_1b_ecc_err_mask(unsigned int umc_qu_datafifo_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_datafifo_2b_ecc_err_mask(unsigned int umc_qu_datafifo_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_rfbuf_1b_ecc_err_mask(unsigned int umc_rfbuf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_rfbuf_2b_ecc_err_mask(unsigned int umc_rfbuf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_vc_smxtf_buf_1b_ecc_err_mask(unsigned int uvc_smxtf_buf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_vc_smxtf_buf_2b_ecc_err_mask(unsigned int uvc_smxtf_buf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_directwqe_err_mask(unsigned int udirectwqe_err_mask); +int iSetSMMC_F_BUFFER_MASK_fifo_ovf_err_mask(unsigned int ufifo_ovf_err_mask); +int iSetSMMC_F_BUFFER_ERR_INFO_mc_buffer_err_info(unsigned int umc_buffer_err_info); +int iSetSMMC_F_BUS_ERR_mc_rf_timeout_err(unsigned int umc_rf_timeout_err); +int iSetSMMC_F_BUS_ERR_mc_rf_timeout_merr(unsigned int umc_rf_timeout_merr); +int iSetSMMC_F_BUS_ERR_mc_rf_rtn_err(unsigned int umc_rf_rtn_err); +int iSetSMMC_F_BUS_ERR_mc_rf_rtn_merr(unsigned int umc_rf_rtn_merr); +int iSetSMMC_F_BUS_ERR_qpc_ring_e01_err(unsigned int uqpc_ring_e01_err); +int iSetSMMC_F_BUS_ERR_qpc_ring_e01_merr(unsigned int uqpc_ring_e01_merr); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_1bit_ecc_err(unsigned int uqu_lrn_fifo_1bit_ecc_err); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_1bit_ecc_merr(unsigned int uqu_lrn_fifo_1bit_ecc_merr); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_2bit_ecc_err(unsigned int uqu_lrn_fifo_2bit_ecc_err); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_2bit_ecc_merr(unsigned int uqu_lrn_fifo_2bit_ecc_merr); +int iSetSMMC_F_BUS_MASK_mc_rf_timeout_err_mask(unsigned int umc_rf_timeout_err_mask); +int iSetSMMC_F_BUS_MASK_mc_rf_rtn_err_mask(unsigned int umc_rf_rtn_err_mask); +int iSetSMMC_F_BUS_MASK_qpc_ring_e01_err_mask(unsigned int uqpc_ring_e01_err_mask); +int iSetSMMC_F_BUS_MASK_qu_lrn_fifo_1bit_ecc_err_mask(unsigned int uqu_lrn_fifo_1bit_ecc_err_mask); +int iSetSMMC_F_BUS_MASK_qu_lrn_fifo_2bit_ecc_err_mask(unsigned int uqu_lrn_fifo_2bit_ecc_err_mask); +int iSetSMMC_F_MC_MULTI_HIT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMMC_F_MC_MULTI_HIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMMC_F_MC_MULTI_HIT_ERR_sticky(unsigned int usticky); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_1b_ecc_err(unsigned int uvc_wb0_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_1b_ecc_merr(unsigned int uvc_wb0_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_2b_ecc_err(unsigned int uvc_wb0_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_2b_ecc_merr(unsigned int uvc_wb0_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_1b_ecc_err(unsigned int uvc_wb1_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_1b_ecc_merr(unsigned int uvc_wb1_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_2b_ecc_err(unsigned int uvc_wb1_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_2b_ecc_merr(unsigned int uvc_wb1_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_1b_ecc_err(unsigned int uvc_wb2_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_1b_ecc_merr(unsigned int uvc_wb2_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_2b_ecc_err(unsigned int uvc_wb2_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_2b_ecc_merr(unsigned int uvc_wb2_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_1b_ecc_err(unsigned int uvc_wb3_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_1b_ecc_merr(unsigned int uvc_wb3_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_2b_ecc_err(unsigned int uvc_wb3_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_2b_ecc_merr(unsigned int uvc_wb3_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_1b_ecc_err(unsigned int uvc_data0_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_1b_ecc_merr(unsigned int uvc_data0_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_2b_ecc_err(unsigned int uvc_data0_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_2b_ecc_merr(unsigned int uvc_data0_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_1b_ecc_err(unsigned int uvc_data1_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_1b_ecc_merr(unsigned int uvc_data1_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_2b_ecc_err(unsigned int uvc_data1_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_2b_ecc_merr(unsigned int uvc_data1_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_1b_ecc_err(unsigned int uvc_data2_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_1b_ecc_merr(unsigned int uvc_data2_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_2b_ecc_err(unsigned int uvc_data2_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_2b_ecc_merr(unsigned int uvc_data2_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_1b_ecc_err(unsigned int uvc_data3_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_1b_ecc_merr(unsigned int uvc_data3_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_2b_ecc_err(unsigned int uvc_data3_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_2b_ecc_merr(unsigned int uvc_data3_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb0_1b_ecc_err_mask(unsigned int uvc_wb0_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb0_2b_ecc_err_mask(unsigned int uvc_wb0_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb1_1b_ecc_err_mask(unsigned int uvc_wb1_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb1_2b_ecc_err_mask(unsigned int uvc_wb1_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb2_1b_ecc_err_mask(unsigned int uvc_wb2_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb2_2b_ecc_err_mask(unsigned int uvc_wb2_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb3_1b_ecc_err_mask(unsigned int uvc_wb3_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb3_2b_ecc_err_mask(unsigned int uvc_wb3_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data0_1b_ecc_err_mask(unsigned int uvc_data0_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data0_2b_ecc_err_mask(unsigned int uvc_data0_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data1_1b_ecc_err_mask(unsigned int uvc_data1_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data1_2b_ecc_err_mask(unsigned int uvc_data1_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data2_1b_ecc_err_mask(unsigned int uvc_data2_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data2_2b_ecc_err_mask(unsigned int uvc_data2_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data3_1b_ecc_err_mask(unsigned int uvc_data3_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data3_2b_ecc_err_mask(unsigned int uvc_data3_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_ERR_INFO_vc_cache_err_info(unsigned int uvc_cache_err_info); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_addr(unsigned int usmmc_f_indir_addr); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_tab(unsigned int usmmc_f_indir_tab); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_stat(unsigned int usmmc_f_indir_stat); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_mode(unsigned int usmmc_f_indir_mode); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_vld(unsigned int usmmc_f_indir_vld); +int iSetSMMC_F_INDRECT_TIMEOUT_smmc_f_indir_timeout(unsigned int usmmc_f_indir_timeout); +int iSetSMMC_F_INDRECT_DATA_smmc_f_indir_data(unsigned int usmmc_f_indir_data); +int iSetSMMC_F_MC_CNT_ENB_smmc_f_mc_cnt_enb(unsigned int usmmc_f_mc_cnt_enb); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb0(unsigned int usmmc_f_mc_cnt_event_sel_enb0); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb1(unsigned int usmmc_f_mc_cnt_event_sel_enb1); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb2(unsigned int usmmc_f_mc_cnt_event_sel_enb2); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb3(unsigned int usmmc_f_mc_cnt_event_sel_enb3); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb4(unsigned int usmmc_f_mc_cnt_event_sel_enb4); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb5(unsigned int usmmc_f_mc_cnt_event_sel_enb5); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb6(unsigned int usmmc_f_mc_cnt_event_sel_enb6); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb7(unsigned int usmmc_f_mc_cnt_event_sel_enb7); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_vf_id(unsigned int umc_cnt_event_sel0_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_tag_type(unsigned int umc_cnt_event_sel0_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_bank_id(unsigned int umc_cnt_event_sel0_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_req_src(unsigned int umc_cnt_event_sel0_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_api_type(unsigned int umc_cnt_event_sel0_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_event_type(unsigned int umc_cnt_event_sel0_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_unit_type(unsigned int umc_cnt_event_sel0_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_vf_id(unsigned int umc_cnt_event_sel1_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_tag_type(unsigned int umc_cnt_event_sel1_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_bank_id(unsigned int umc_cnt_event_sel1_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_req_src(unsigned int umc_cnt_event_sel1_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_api_type(unsigned int umc_cnt_event_sel1_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_event_type(unsigned int umc_cnt_event_sel1_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_unit_type(unsigned int umc_cnt_event_sel1_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_vf_id(unsigned int umc_cnt_event_sel2_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_tag_type(unsigned int umc_cnt_event_sel2_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_bank_id(unsigned int umc_cnt_event_sel2_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_req_src(unsigned int umc_cnt_event_sel2_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_api_type(unsigned int umc_cnt_event_sel2_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_event_type(unsigned int umc_cnt_event_sel2_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_unit_type(unsigned int umc_cnt_event_sel2_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_vf_id(unsigned int umc_cnt_event_sel3_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_tag_type(unsigned int umc_cnt_event_sel3_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_bank_id(unsigned int umc_cnt_event_sel3_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_req_src(unsigned int umc_cnt_event_sel3_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_api_type(unsigned int umc_cnt_event_sel3_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_event_type(unsigned int umc_cnt_event_sel3_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_unit_type(unsigned int umc_cnt_event_sel3_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_vf_id(unsigned int umc_cnt_event_sel4_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_tag_type(unsigned int umc_cnt_event_sel4_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_bank_id(unsigned int umc_cnt_event_sel4_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_req_src(unsigned int umc_cnt_event_sel4_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_api_type(unsigned int umc_cnt_event_sel4_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_event_type(unsigned int umc_cnt_event_sel4_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_unit_type(unsigned int umc_cnt_event_sel4_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_vf_id(unsigned int umc_cnt_event_sel5_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_tag_type(unsigned int umc_cnt_event_sel5_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_bank_id(unsigned int umc_cnt_event_sel5_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_req_src(unsigned int umc_cnt_event_sel5_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_api_type(unsigned int umc_cnt_event_sel5_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_event_type(unsigned int umc_cnt_event_sel5_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_unit_type(unsigned int umc_cnt_event_sel5_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_vf_id(unsigned int umc_cnt_event_sel6_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_tag_type(unsigned int umc_cnt_event_sel6_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_bank_id(unsigned int umc_cnt_event_sel6_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_req_src(unsigned int umc_cnt_event_sel6_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_api_type(unsigned int umc_cnt_event_sel6_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_event_type(unsigned int umc_cnt_event_sel6_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_unit_type(unsigned int umc_cnt_event_sel6_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_vf_id(unsigned int umc_cnt_event_sel7_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_tag_type(unsigned int umc_cnt_event_sel7_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_bank_id(unsigned int umc_cnt_event_sel7_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_req_src(unsigned int umc_cnt_event_sel7_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_api_type(unsigned int umc_cnt_event_sel7_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_event_type(unsigned int umc_cnt_event_sel7_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_unit_type(unsigned int umc_cnt_event_sel7_unit_type); +int iSetSMMC_F_MC_STATUS_mc_init_done(unsigned int umc_init_done); +int iSetSMMC_F_MC_STATUS_mc_free_tag_num(unsigned int umc_free_tag_num); +int iSetSMMC_F_MC_STATUS_qu_rx_flit_ctp_done(unsigned int uqu_rx_flit_ctp_done); +int iSetSMMC_F_MC_STATUS_qu_tx_flit_ctp_done(unsigned int uqu_tx_flit_ctp_done); +int iSetSMMC_F_MC_STATUS_smmc_rf_timeout(unsigned int usmmc_rf_timeout); +int iSetSMMC_F_MC_CNT0_smmc_f_mc_cnt0(unsigned int usmmc_f_mc_cnt0); +int iSetSMMC_F_MC_CNT1_smmc_f_mc_cnt1(unsigned int usmmc_f_mc_cnt1); +int iSetSMMC_F_MC_CNT2_smmc_f_mc_cnt2(unsigned int usmmc_f_mc_cnt2); +int iSetSMMC_F_MC_CNT3_smmc_f_mc_cnt3(unsigned int usmmc_f_mc_cnt3); +int iSetSMMC_F_MC_CNT4_smmc_f_mc_cnt4(unsigned int usmmc_f_mc_cnt4); +int iSetSMMC_F_MC_CNT5_smmc_f_mc_cnt5(unsigned int usmmc_f_mc_cnt5); +int iSetSMMC_F_MC_CNT6_smmc_f_mc_cnt6(unsigned int usmmc_f_mc_cnt6); +int iSetSMMC_F_MC_CNT7_smmc_f_mc_cnt7(unsigned int usmmc_f_mc_cnt7); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc0_wb_data_fifo_depth(unsigned int uvc0_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc1_wb_data_fifo_depth(unsigned int uvc1_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc2_wb_data_fifo_depth(unsigned int uvc2_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc3_wb_data_fifo_depth(unsigned int uvc3_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc0_wb_ctrl_fifo_depth(unsigned int uvc0_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc1_wb_ctrl_fifo_depth(unsigned int uvc1_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc2_wb_ctrl_fifo_depth(unsigned int uvc2_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc3_wb_ctrl_fifo_depth(unsigned int uvc3_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc0_ctrl_fifo_depth(unsigned int uvc0_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc1_ctrl_fifo_depth(unsigned int uvc1_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc2_ctrl_fifo_depth(unsigned int uvc2_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc3_ctrl_fifo_depth(unsigned int uvc3_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc0_data_fifo_depth(unsigned int uvc0_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc1_data_fifo_depth(unsigned int uvc1_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc2_data_fifo_depth(unsigned int uvc2_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc3_data_fifo_depth(unsigned int uvc3_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_smxtf_fifo_depth(unsigned int usmxtf_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc_crdt_from_smit(unsigned int uvc_crdt_from_smit); +int iSetSMMC_F_VC_FIFO_DEPTH1_data_credit_from_qu(unsigned int udata_credit_from_qu); +int iSetSMMC_F_MC_FIFO1_DEPTH_qu_cmd_fifo_depth(unsigned int uqu_cmd_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_qu_data_fifo_depth(unsigned int uqu_data_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_lrb0_fifo_depth(unsigned int ulrb0_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_lrb1_fifo_depth(unsigned int ulrb1_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_lrb2_fifo_depth(unsigned int ulrb2_fifo_depth); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_return_fifo_depth(unsigned int uqu_return_fifo_depth); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_return_fifo_bp(unsigned int uqu_return_fifo_bp); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_store_buffer_bp(unsigned int uqu_store_buffer_bp); +int iSetSMMC_F_MC_FIFO2_DEPTH_lrb3_fifo_depth(unsigned int ulrb3_fifo_depth); +int iSetSMMC_F_MC_FIFO2_DEPTH_rfbuf_credit(unsigned int urfbuf_credit); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_store_buffer_depth(unsigned int uqu_store_buffer_depth); +int iSetSMMC_F_ERR_INJ_smmc_vc0_crt_err_inj(unsigned int usmmc_vc0_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc0_uncrt_err_inj(unsigned int usmmc_vc0_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc1_crt_err_inj(unsigned int usmmc_vc1_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc1_uncrt_err_inj(unsigned int usmmc_vc1_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc2_crt_err_inj(unsigned int usmmc_vc2_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc2_uncrt_err_inj(unsigned int usmmc_vc2_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc3_crt_err_inj(unsigned int usmmc_vc3_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc3_uncrt_err_inj(unsigned int usmmc_vc3_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc0_crt_err_inj(unsigned int usmmc_mc0_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc0_uncrt_err_inj(unsigned int usmmc_mc0_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc1_crt_err_inj(unsigned int usmmc_mc1_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc1_uncrt_err_inj(unsigned int usmmc_mc1_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc2_crt_err_inj(unsigned int usmmc_mc2_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc2_uncrt_err_inj(unsigned int usmmc_mc2_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc3_crt_err_inj(unsigned int usmmc_mc3_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc3_uncrt_err_inj(unsigned int usmmc_mc3_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_qu_intf_crt_err_inj(unsigned int usmmc_qu_intf_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_qu_intf_uncrt_err_inj(unsigned int usmmc_qu_intf_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_rf_buf_crt_err_inj(unsigned int usmmc_rf_buf_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_rf_buf_uncrt_err_inj(unsigned int usmmc_rf_buf_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vfa_crt_err_inj(unsigned int usmmc_vfa_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vfa_uncrt_err_inj(unsigned int usmmc_vfa_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_stb_crt_err_inj(unsigned int usmmc_stb_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_stb_uncrt_err_inj(unsigned int usmmc_stb_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_smxtfb_crt_err_inj(unsigned int usmmc_smxtfb_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_smxtfb_uncrt_err_inj(unsigned int usmmc_smxtfb_uncrt_err_inj); +int iSetSMMC_F_GPA_TRANS_ERR_error_bit(unsigned int uerror_bit); +int iSetSMMC_F_GPA_TRANS_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMMC_F_GPA_TRANS_ERR_sticky(unsigned int usticky); +int iSetSMMC_F_QU_INTF_CNT_CFG_smmc_f_qu_intf_tx_cnt_cfg(unsigned int usmmc_f_qu_intf_tx_cnt_cfg); +int iSetSMMC_F_QU_INTF_CNT_CFG_smmc_f_qu_intf_rx_cnt_cfg(unsigned int usmmc_f_qu_intf_rx_cnt_cfg); +int iSetSMMC_F_QU_INTF_RX_CNT_smmc_f_qu_intf_rx_cnt(unsigned int usmmc_f_qu_intf_rx_cnt); +int iSetSMMC_F_QU_INTF_TX_CNT_smmc_f_qu_intf_tx_cnt(unsigned int usmmc_f_qu_intf_tx_cnt); +int iSetSMMC_F_MC_CFG2_smmc_f_rsc_cnt_mix_en(unsigned int usmmc_f_rsc_cnt_mix_en); +int iSetSMMC_F_MC_CFG2_smmc_f_rtt_cnt_type(unsigned int usmmc_f_rtt_cnt_type); +int iSetSMMC_F_MC_CFG2_smmc_f_rtt_cnt_enb(unsigned int usmmc_f_rtt_cnt_enb); +int iSetSMMC_F_MC_CFG2_smmc_f_rf_err_ctp_clr(unsigned int usmmc_f_rf_err_ctp_clr); +int iSetSMMC_F_MC_CFG2_smf_common_mem_power_mode(unsigned int usmf_common_mem_power_mode); +int iSetSMMC_F_MC_CFG2_mc_refill_timeout_enb(unsigned int umc_refill_timeout_enb); +int iSetSMMC_F_MC_CFG2_bypass_smvc(unsigned int ubypass_smvc); + +/* Define the union csr_smmc_l_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_version_u; + +/* Define the union csr_smmc_l_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_parity_chk : 1; /* [0] */ + u32 smmc_l_ecc_chk : 1; /* [1] */ + u32 mem_ini_en : 1; /* [2] */ + u32 rsv_0 : 13; /* [15:3] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 sp_ram_tmod_div2 : 7; /* [30:24] */ + u32 mem_ret1n_div2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cfg_u; + +/* Define the union csr_smmc_l_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ini_done : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_stat_u; + +/* Define the union csr_smmc_l_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_int_vector_u; + +/* Define the union csr_smmc_l_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 1; /* [0] */ + u32 rsv_4 : 15; /* [15:1] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_int_u; + +/* Define the union csr_smmc_l_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 1; /* [0] */ + u32 rsv_5 : 15; /* [15:1] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_int_mask_u; + +/* Define the union csr_smmc_l_mem_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 main_mem_2b_ecc_err : 1; /* [0] */ + u32 main_mem_2b_ecc_merr : 1; /* [1] */ + u32 main_mem_1b_ecc_err : 1; /* [2] */ + u32 main_mem_1b_ecc_merr : 1; /* [3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_mem_err_u; + +/* Define the union csr_smmc_l_mem_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 main_mem_2b_ecc_err_mask : 1; /* [0] */ + u32 main_mem_1b_ecc_err_mask : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_mem_err_mask_u; + +/* Define the union csr_smmc_l_mem_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_err_index : 15; /* [14:0] */ + u32 rsv_6 : 1; /* [15] */ + u32 mem_err_info_type : 2; /* [17:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_mem_err_info_u; + +/* Define the union csr_smmc_l_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_indir_addr : 24; /* [23:0] */ + u32 smmc_l_indir_tab : 4; /* [27:24] */ + u32 smmc_l_indir_stat : 2; /* [29:28] */ + u32 smmc_l_indir_mode : 1; /* [30] */ + u32 smmc_l_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_indrect_ctrl_u; + +/* Define the union csr_smmc_l_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_indrect_timeout_u; + +/* Define the union csr_smmc_l_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_indrect_data_u; + +/* Define the union csr_smmc_l_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_enable : 1; /* [0] */ + u32 cnt1_enable : 1; /* [1] */ + u32 cnt2_enable : 1; /* [2] */ + u32 cnt3_enable : 1; /* [3] */ + u32 cnt0_match_en : 2; /* [5:4] */ + u32 cnt1_match_en : 2; /* [7:6] */ + u32 cnt2_match_en : 2; /* [9:8] */ + u32 cnt3_match_en : 2; /* [11:10] */ + u32 cnt0_sel : 2; /* [13:12] */ + u32 cnt1_sel : 2; /* [15:14] */ + u32 cnt2_sel : 2; /* [17:16] */ + u32 cnt3_sel : 2; /* [19:18] */ + u32 rsv_7 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt_cfg_u; + +/* Define the union csr_smmc_l_cnt_match_bank_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_match_bank : 4; /* [3:0] */ + u32 cnt1_match_bank : 4; /* [7:4] */ + u32 cnt2_match_bank : 4; /* [11:8] */ + u32 cnt3_match_bank : 4; /* [15:12] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt_match_bank_u; + +/* Define the union csr_smmc_l_cnt_match_instance_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_match_inst : 5; /* [4:0] */ + u32 cnt1_match_inst : 5; /* [9:5] */ + u32 cnt2_match_inst : 5; /* [14:10] */ + u32 cnt3_match_inst : 5; /* [19:15] */ + u32 rsv_9 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt_match_instance_u; + +/* Define the union csr_smmc_l_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt0_u; + +/* Define the union csr_smmc_l_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt1_u; + +/* Define the union csr_smmc_l_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt2_u; + +/* Define the union csr_smmc_l_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt3_u; + +/* Define the union csr_smmc_l_bank_queue_depth_ctp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_depth_bank0 : 4; /* [3:0] */ + u32 cur_depth_bank1 : 4; /* [7:4] */ + u32 cur_depth_bank2 : 4; /* [11:8] */ + u32 cur_depth_bank3 : 4; /* [15:12] */ + u32 cur_depth_bank4 : 4; /* [19:16] */ + u32 cur_depth_bank5 : 4; /* [23:20] */ + u32 cur_depth_bank6 : 4; /* [27:24] */ + u32 cur_depth_bank7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_bank_queue_depth_ctp0_u; + +/* Define the union csr_smmc_l_bank_queue_depth_ctp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_depth_bank8 : 4; /* [3:0] */ + u32 cur_depth_bank9 : 4; /* [7:4] */ + u32 cur_depth_bank10 : 4; /* [11:8] */ + u32 cur_depth_bank11 : 4; /* [15:12] */ + u32 cur_depth_bank12 : 4; /* [19:16] */ + u32 cur_depth_bank13 : 4; /* [23:20] */ + u32 cur_depth_bank14 : 4; /* [27:24] */ + u32 cur_depth_bank15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_bank_queue_depth_ctp1_u; + +/* Define the union csr_smmc_l_ecc_inj_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_1b_ecc_inj_en : 1; /* [0] */ + u32 smmc_l_2b_ecc_inj_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_ecc_inj_cfg_u; + +/* Define the union csr_smmc_l_pg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_pg_grp1_id : 2; /* [1:0] */ + u32 smmc_l_pg_grp0_id : 2; /* [3:2] */ + u32 smmc_l_pg_grp_num : 1; /* [4] */ + u32 rsv_11 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_pg_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smmc_l_version_u smmc_l_version; /* 0 */ + volatile csr_smmc_l_cfg_u smmc_l_cfg; /* 4 */ + volatile csr_smmc_l_stat_u smmc_l_stat; /* 8 */ + volatile csr_smmc_l_int_vector_u smmc_l_int_vector; /* C */ + volatile csr_smmc_l_int_u smmc_l_int; /* 10 */ + volatile csr_smmc_l_int_mask_u smmc_l_int_mask; /* 14 */ + volatile csr_smmc_l_mem_err_u smmc_l_mem_err; /* 18 */ + volatile csr_smmc_l_mem_err_mask_u smmc_l_mem_err_mask; /* 1C */ + volatile csr_smmc_l_mem_err_info_u smmc_l_mem_err_info; /* 20 */ + volatile csr_smmc_l_indrect_ctrl_u smmc_l_indrect_ctrl; /* 24 */ + volatile csr_smmc_l_indrect_timeout_u smmc_l_indrect_timeout; /* 28 */ + volatile csr_smmc_l_indrect_data_u smmc_l_indrect_data; /* 2C */ + volatile csr_smmc_l_cnt_cfg_u smmc_l_cnt_cfg; /* 30 */ + volatile csr_smmc_l_cnt_match_bank_u smmc_l_cnt_match_bank; /* 34 */ + volatile csr_smmc_l_cnt_match_instance_u smmc_l_cnt_match_instance; /* 38 */ + volatile csr_smmc_l_cnt0_u smmc_l_cnt0; /* 3C */ + volatile csr_smmc_l_cnt1_u smmc_l_cnt1; /* 40 */ + volatile csr_smmc_l_cnt2_u smmc_l_cnt2; /* 44 */ + volatile csr_smmc_l_cnt3_u smmc_l_cnt3; /* 48 */ + volatile csr_smmc_l_bank_queue_depth_ctp0_u smmc_l_bank_queue_depth_ctp0; /* 4C */ + volatile csr_smmc_l_bank_queue_depth_ctp1_u smmc_l_bank_queue_depth_ctp1; /* 50 */ + volatile csr_smmc_l_ecc_inj_cfg_u smmc_l_ecc_inj_cfg; /* 54 */ + volatile csr_smmc_l_pg_cfg_u smmc_l_pg_cfg; /* 58 */ +} S_smmc_l_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smmc_l_csr */ +extern volatile S_smmc_l_csr_REGS_TYPE *gopsmmc_l_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMMC_L_VERSION_smmc_l_version(unsigned int usmmc_l_version); +int iSetSMMC_L_CFG_smmc_l_parity_chk(unsigned int usmmc_l_parity_chk); +int iSetSMMC_L_CFG_smmc_l_ecc_chk(unsigned int usmmc_l_ecc_chk); +int iSetSMMC_L_CFG_mem_ini_en(unsigned int umem_ini_en); +int iSetSMMC_L_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMMC_L_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMMC_L_CFG_sp_ram_tmod_div2(unsigned int usp_ram_tmod_div2); +int iSetSMMC_L_CFG_mem_ret1n_div2(unsigned int umem_ret1n_div2); +int iSetSMMC_L_STAT_mem_ini_done(unsigned int umem_ini_done); +int iSetSMMC_L_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMMC_L_INT_VECTOR_enable(unsigned int uenable); +int iSetSMMC_L_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMMC_L_INT_int_data(unsigned int uint_data); +int iSetSMMC_L_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_L_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMMC_L_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_L_MEM_ERR_main_mem_2b_ecc_err(unsigned int umain_mem_2b_ecc_err); +int iSetSMMC_L_MEM_ERR_main_mem_2b_ecc_merr(unsigned int umain_mem_2b_ecc_merr); +int iSetSMMC_L_MEM_ERR_main_mem_1b_ecc_err(unsigned int umain_mem_1b_ecc_err); +int iSetSMMC_L_MEM_ERR_main_mem_1b_ecc_merr(unsigned int umain_mem_1b_ecc_merr); +int iSetSMMC_L_MEM_ERR_MASK_main_mem_2b_ecc_err_mask(unsigned int umain_mem_2b_ecc_err_mask); +int iSetSMMC_L_MEM_ERR_MASK_main_mem_1b_ecc_err_mask(unsigned int umain_mem_1b_ecc_err_mask); +int iSetSMMC_L_MEM_ERR_INFO_mem_err_index(unsigned int umem_err_index); +int iSetSMMC_L_MEM_ERR_INFO_mem_err_info_type(unsigned int umem_err_info_type); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_addr(unsigned int usmmc_l_indir_addr); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_tab(unsigned int usmmc_l_indir_tab); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_stat(unsigned int usmmc_l_indir_stat); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_mode(unsigned int usmmc_l_indir_mode); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_vld(unsigned int usmmc_l_indir_vld); +int iSetSMMC_L_INDRECT_TIMEOUT_smmc_l_indir_timeout(unsigned int usmmc_l_indir_timeout); +int iSetSMMC_L_INDRECT_DATA_smmc_f_indir_data(unsigned int usmmc_f_indir_data); +int iSetSMMC_L_CNT_CFG_cnt0_enable(unsigned int ucnt0_enable); +int iSetSMMC_L_CNT_CFG_cnt1_enable(unsigned int ucnt1_enable); +int iSetSMMC_L_CNT_CFG_cnt2_enable(unsigned int ucnt2_enable); +int iSetSMMC_L_CNT_CFG_cnt3_enable(unsigned int ucnt3_enable); +int iSetSMMC_L_CNT_CFG_cnt0_match_en(unsigned int ucnt0_match_en); +int iSetSMMC_L_CNT_CFG_cnt1_match_en(unsigned int ucnt1_match_en); +int iSetSMMC_L_CNT_CFG_cnt2_match_en(unsigned int ucnt2_match_en); +int iSetSMMC_L_CNT_CFG_cnt3_match_en(unsigned int ucnt3_match_en); +int iSetSMMC_L_CNT_CFG_cnt0_sel(unsigned int ucnt0_sel); +int iSetSMMC_L_CNT_CFG_cnt1_sel(unsigned int ucnt1_sel); +int iSetSMMC_L_CNT_CFG_cnt2_sel(unsigned int ucnt2_sel); +int iSetSMMC_L_CNT_CFG_cnt3_sel(unsigned int ucnt3_sel); +int iSetSMMC_L_CNT_MATCH_BANK_cnt0_match_bank(unsigned int ucnt0_match_bank); +int iSetSMMC_L_CNT_MATCH_BANK_cnt1_match_bank(unsigned int ucnt1_match_bank); +int iSetSMMC_L_CNT_MATCH_BANK_cnt2_match_bank(unsigned int ucnt2_match_bank); +int iSetSMMC_L_CNT_MATCH_BANK_cnt3_match_bank(unsigned int ucnt3_match_bank); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt0_match_inst(unsigned int ucnt0_match_inst); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt1_match_inst(unsigned int ucnt1_match_inst); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt2_match_inst(unsigned int ucnt2_match_inst); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt3_match_inst(unsigned int ucnt3_match_inst); +int iSetSMMC_L_CNT0_smmc_l_cnt0(unsigned int usmmc_l_cnt0); +int iSetSMMC_L_CNT1_smmc_l_cnt1(unsigned int usmmc_l_cnt1); +int iSetSMMC_L_CNT2_smmc_l_cnt2(unsigned int usmmc_l_cnt2); +int iSetSMMC_L_CNT3_smmc_l_cnt3(unsigned int usmmc_l_cnt3); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank0(unsigned int ucur_depth_bank0); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank1(unsigned int ucur_depth_bank1); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank2(unsigned int ucur_depth_bank2); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank3(unsigned int ucur_depth_bank3); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank4(unsigned int ucur_depth_bank4); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank5(unsigned int ucur_depth_bank5); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank6(unsigned int ucur_depth_bank6); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank7(unsigned int ucur_depth_bank7); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank8(unsigned int ucur_depth_bank8); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank9(unsigned int ucur_depth_bank9); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank10(unsigned int ucur_depth_bank10); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank11(unsigned int ucur_depth_bank11); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank12(unsigned int ucur_depth_bank12); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank13(unsigned int ucur_depth_bank13); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank14(unsigned int ucur_depth_bank14); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank15(unsigned int ucur_depth_bank15); +int iSetSMMC_L_ECC_INJ_CFG_smmc_l_1b_ecc_inj_en(unsigned int usmmc_l_1b_ecc_inj_en); +int iSetSMMC_L_ECC_INJ_CFG_smmc_l_2b_ecc_inj_en(unsigned int usmmc_l_2b_ecc_inj_en); +int iSetSMMC_L_PG_CFG_smmc_l_pg_grp1_id(unsigned int usmmc_l_pg_grp1_id); +int iSetSMMC_L_PG_CFG_smmc_l_pg_grp0_id(unsigned int usmmc_l_pg_grp0_id); +int iSetSMMC_L_PG_CFG_smmc_l_pg_grp_num(unsigned int usmmc_l_pg_grp_num); + + +#endif // SM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_reg_offset.h new file mode 100644 index 000000000..66ebe8c62 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_reg_offset.h @@ -0,0 +1,860 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hi1822_reg_offset.h +// Project line : IT Product Line +// Department : ICT Processor Chipset Development Department +// Version : V100 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// file +// ****************************************************************************** + +#ifndef SM_REG_OFFSET_H +#define SM_REG_OFFSET_H + +/* smrt_csr Base address of Module's Register */ +#define CSR_SMRT_CSR_BASE (0xA00) + +/* **************************************************************************** */ +/* smrt_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMRT_CSR_SMRT_VERSION_REG (CSR_SMRT_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMRT_CSR_SMXR_CFG1_REG (CSR_SMRT_CSR_BASE + 0x4) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_SMXR_CFG0_REG (CSR_SMRT_CSR_BASE + 0x8) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_SMXT_CFG_REG \ + (CSR_SMRT_CSR_BASE + 0xC) /* This is the Smart Memory Infra Cross Transmission (SMXT) module configuration \ + register. The software use this register for debug. */ +#define CSR_SMRT_CSR_SMXR_TM_GRT01_REG (CSR_SMRT_CSR_BASE + 0x10) /* Timer Group Routing table element 0 and 1 */ +#define CSR_SMRT_CSR_SMXR_TM_GRT23_REG (CSR_SMRT_CSR_BASE + 0x14) /* Timer Group Routing table element 2 and 3 */ +#define CSR_SMRT_CSR_SMRT_INT_VECTOR_REG (CSR_SMRT_CSR_BASE + 0x18) +#define CSR_SMRT_CSR_SMRT_INT_REG (CSR_SMRT_CSR_BASE + 0x1C) /* SMRT interrupt data */ +#define CSR_SMRT_CSR_SMRT_INT_MASK_REG (CSR_SMRT_CSR_BASE + 0x20) /* SMIR interrupt mask configuration */ +#define CSR_SMRT_CSR_SMXR_REQ_MEM_CRT_ERR_REG \ + (CSR_SMRT_CSR_BASE + 0x24) /* ECC correctable memory detected on SMXR request memory */ +#define CSR_SMRT_CSR_SMXR_REQ_MEM_UNCRT_ERR_REG \ + (CSR_SMRT_CSR_BASE + 0x28) /* ECC un-correctable memory detected on SMXR request memory */ +#define CSR_SMRT_CSR_SMXR_MISS_SOP_EOP_ERR_REG (CSR_SMRT_CSR_BASE + 0x2C) /* SMXR received miss EOP API */ +#define CSR_SMRT_CSR_SMXR_INDRECT_CTRL_REG (CSR_SMRT_CSR_BASE + 0x30) /* indirect access address registers */ +#define CSR_SMRT_CSR_SMXR_INDRECT_TIMEOUT_REG (CSR_SMRT_CSR_BASE + 0x34) /* memory access timeout configure */ +#define CSR_SMRT_CSR_SMXR_INDRECT_DATA_REG (CSR_SMRT_CSR_BASE + 0x38) /* indirect access data registers */ +#define CSR_SMRT_CSR_SMXT_CAP_CFG_REG \ + (CSR_SMRT_CSR_BASE + \ + 0x3C) /* smxt capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per \ + field via <cap_sel_en> in <smxr_en_cnt> ) */ +#define CSR_SMRT_CSR_SMXT_CAP_FIELD_CFG_REG \ + (CSR_SMRT_CSR_BASE + \ + 0x40) /* SMXT capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per \ + field via <cap_sel_en> in <smxr_en_cnt> ) */ +#define CSR_SMRT_CSR_SMXT_CNT_CFG0_REG \ + (CSR_SMRT_CSR_BASE + 0x44) /* SMXT mappable event counter controal . The software use this control to configure \ + expected counter mapping . */ +#define CSR_SMRT_CSR_SMXT_CNT_CFG1_REG \ + (CSR_SMRT_CSR_BASE + 0x48) /* SMXT mappable event counter controal . The software use this control to configure \ + expected counter mapping . */ +#define CSR_SMRT_CSR_SMXT_CNT0_REG \ + (CSR_SMRT_CSR_BASE + 0x4C) /* SMXT physical counter 0.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . */ +#define CSR_SMRT_CSR_SMXT_CNT1_REG \ + (CSR_SMRT_CSR_BASE + 0x50) /* SMXT physical counter 1.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . */ +#define CSR_SMRT_CSR_SMXT_CNT2_REG \ + (CSR_SMRT_CSR_BASE + 0x54) /* SMXT physical counter 2.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . */ +#define CSR_SMRT_CSR_SMXT_CNT3_REG \ + (CSR_SMRT_CSR_BASE + 0x58) /* SMXT physical counter 3.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . */ +#define CSR_SMRT_CSR_SMXT_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x5C) /* smxt credit counter CTP registers */ +#define CSR_SMRT_CSR_SMXT_FIFO_DEPTH0_REG \ + (CSR_SMRT_CSR_BASE + 0x60) /* FIFO depth CTP registers for SMXT FIFOs for SMF infra1 and infra0 */ +#define CSR_SMRT_CSR_SMXT_FIFO_DEPTH1_REG \ + (CSR_SMRT_CSR_BASE + 0x68) /* FIFO depth CTP registers for SMXT FIFOs for SMF infra3 and Infra2 */ +#define CSR_SMRT_CSR_TL0_Q_DEP_REG (CSR_SMRT_CSR_BASE + 0x6C) /* queue depth for API from TILE0 in SMXR */ +#define CSR_SMRT_CSR_TL1_Q_DEP_REG (CSR_SMRT_CSR_BASE + 0x70) /* queue depth for API from TILE1 in SMXR */ +#define CSR_SMRT_CSR_RQST_Q_DEP_REG \ + (CSR_SMRT_CSR_BASE + 0x74) /* queue depth for API from RING request channel in SMXR */ +#define CSR_SMRT_CSR_RSP_Q_DEP_REG \ + (CSR_SMRT_CSR_BASE + 0x78) /* queue depth for API from RING request channel in SMXR */ +#define CSR_SMRT_CSR_RQST_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x7C) /* rqst channel credit counter in SMXR */ +#define CSR_SMRT_CSR_RESP_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x80) /* rsponse channel credit counter in SMXR */ +#define CSR_SMRT_CSR_SMXR_CNT0_REG (CSR_SMRT_CSR_BASE + 0x84) /* Cnt for tile0 direct channel */ +#define CSR_SMRT_CSR_SMXR_CNT1_REG (CSR_SMRT_CSR_BASE + 0x88) /* Cnt for tile1 direct channel */ +#define CSR_SMRT_CSR_SMXR_CNT2_REG (CSR_SMRT_CSR_BASE + 0x8C) /* Cnt for ring request channel */ +#define CSR_SMRT_CSR_SMXR_CNT3_REG (CSR_SMRT_CSR_BASE + 0x90) /* Cnt for ring rsponse channel */ +#define CSR_SMRT_CSR_SMXT_CTP_REG (CSR_SMRT_CSR_BASE + 0x94) /* SMXT CTP registers */ +#define CSR_SMRT_CSR_SMXR_CFG2_REG (CSR_SMRT_CSR_BASE + 0x98) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_SMXR_CFG3_REG (CSR_SMRT_CSR_BASE + 0x9C) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS0_REG (CSR_SMRT_CSR_BASE + 0xA0) /* RAM CTRL_BUS寄存器0 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS1_REG (CSR_SMRT_CSR_BASE + 0xA4) /* RAM CTRL_BUS寄存器1 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS2_REG (CSR_SMRT_CSR_BASE + 0xA8) /* RAM CTRL_BUS寄存器2 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS3_REG (CSR_SMRT_CSR_BASE + 0xAC) /* RAM CTRL_BUS寄存器3 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS4_REG (CSR_SMRT_CSR_BASE + 0xB0) /* RAM CTRL_BUS寄存器4 */ +#define CSR_SMRT_CSR_SMXT_CFG2_REG (CSR_SMRT_CSR_BASE + 0xB4) /* SMXT cofigure registers */ + +/* smir_csr Base address of Module's Register */ +#define CSR_SMIR_CSR_BASE (0x100) + +/* **************************************************************************** */ +/* smir_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMIR_CSR_SMIR_VERSION_REG (CSR_SMIR_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMIR_CSR_SMIR_CFG_REG \ + (CSR_SMIR_CSR_BASE + 0x4) /* This is the Smart Memory Infra Receive (SMIR) module configuration register. Use this \ + register for debug. */ +#define CSR_SMIR_CSR_SMIR_HASH_SEED0_REG \ + (CSR_SMIR_CSR_BASE + 0x8) /* Hash function seed conifg register. This register used to change the original seed of \ + hash function. */ +#define CSR_SMIR_CSR_SMIR_HASH_SEED1_REG \ + (CSR_SMIR_CSR_BASE + 0xC) /* Hash function seed conifg register. This register used to change the original seed of \ + hash function. */ +#define CSR_SMIR_CSR_SMIR_INT_VECTOR_REG (CSR_SMIR_CSR_BASE + 0x10) +#define CSR_SMIR_CSR_SMIR_INT_REG (CSR_SMIR_CSR_BASE + 0x14) /* SMIR interrupt data */ +#define CSR_SMIR_CSR_SMIR_INT_MASK_REG (CSR_SMIR_CSR_BASE + 0x18) /* SMIR interrupt mask configuration */ +#define CSR_SMIR_CSR_SMIR_ERR_SPEC_TH_REG (CSR_SMIR_CSR_BASE + 0x1C) /* Int[0] :specital thread drop for busy. */ +#define CSR_SMIR_CSR_SMIR_REQ_MSG_ERR_REG (CSR_SMIR_CSR_BASE + 0x20) /* SMIR request channel message error register. \ + */ +#define CSR_SMIR_CSR_SMIR_RESP_MSG_ERR_REG \ + (CSR_SMIR_CSR_BASE + 0x24) /* SMIR response channel message error register. */ +#define CSR_SMIR_CSR_SMIR_MEM_ECC_CRT_ERR_REG (CSR_SMIR_CSR_BASE + 0x28) /* smir memory ecc correctable error */ +#define CSR_SMIR_CSR_SMIR_MEM_ECC_UNCRT_ERR_REG (CSR_SMIR_CSR_BASE + 0x2C) /* smir memory ecc uncorrectable error */ +#define CSR_SMIR_CSR_SMIR_INDRECT_CTRL_REG (CSR_SMIR_CSR_BASE + 0x30) /* indirect access address registers */ +#define CSR_SMIR_CSR_SMIR_INDRECT_TIMEOUT_REG (CSR_SMIR_CSR_BASE + 0x34) /* memory access timeout configure */ +#define CSR_SMIR_CSR_SMIR_INDRECT_DATA_REG (CSR_SMIR_CSR_BASE + 0x38) /* indirect access data registers */ +#define CSR_SMIR_CSR_SMIR_CAP0_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x3C) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per \ + field via <cap_sel_en> in <smir_en_cnt> ) */ +#define CSR_SMIR_CSR_SMIR_CAP1_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x40) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP2_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x44) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP3_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x48) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP4_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x4C) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP6_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x50) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_EN_CNT_REG \ + (CSR_SMIR_CSR_BASE + 0x54) /* SMIR mappable event counter controal . The software use this control to configure \ + expected counter mapping . */ +#define CSR_SMIR_CSR_SMIR_CNT0_REG \ + (CSR_SMIR_CSR_BASE + 0x58) /* SMIR physical counter 0.software can enable which events to be counted into it via \ + field <smir_en_cnt_0> in register <SMIR_EN_CNT> . */ +#define CSR_SMIR_CSR_SMIR_CNT1_REG \ + (CSR_SMIR_CSR_BASE + 0x5C) /* SMIR physical counter 1.software can enable which events to be counted into it via \ + field <smir_en_cnt_1> in register <SMIR_EN_CNT> . */ +#define CSR_SMIR_CSR_SMIR_CNT2_REG \ + (CSR_SMIR_CSR_BASE + 0x60) /* SMIR physical counter 2.software can enable which events to be counted into it via \ + field <smir_en_cnt_2> in register <SMIR_EN_CNT> . */ +#define CSR_SMIR_CSR_SMIR_CRDT_CNT_REG (CSR_SMIR_CSR_BASE + 0x64) /* SMIR credit counter CTP register */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x68) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0x70) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x78) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0x80) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x88) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0x90) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x98) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0xA0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0xA8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0xB0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0xB8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0xC0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xC8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xCC) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xD0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xD4) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xD8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xDC) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CFG1_REG \ + (CSR_SMIR_CSR_BASE + 0xE0) /* This is the Smart Memory Infra Receive (SMIR) module configuration register. Use \ + this register for debug. */ + +/* smeg0_abuf0_csr Base address of Module's Register */ +#define CSR_SMEG0_ABUF0_CSR_BASE (0x200) + +/* **************************************************************************** */ +/* smeg0_abuf0_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF0_VERSION_REG (CSR_SMEG0_ABUF0_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_0_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x4) /* This is the Sm Abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_1_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x8) /* This is the Sm abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_2_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xC) /* This is the Sm abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_3_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x10) /* This is the Sm abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_4_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x14) /* This is the Sm abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_5_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x18) /* This is the Sm abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_GRW_WM_6_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x1C) /* This is the Sm abuf0 grow watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_0_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x20) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_1_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x24) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_2_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x28) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_3_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x2C) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_4_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x30) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_5_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x34) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TH_SHK_WM_6_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x38) /* This is the Sm abuf0 shrink watermark config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_ATTR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x3C) /* This is the free list reclaim attribute config register.This is used to set \ + up the reclaim operation on one free list. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_NUM_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x40) /* This is the Sm abuf0 free list reclaim number config register.This is used to set the total number of \ + free nodes that the software wants to get from the particular free list.This register must be set \ + before the reclaim operation is set up. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_BOUND_U_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x44) /* This is the Sm abuf0 reclaim upper boundary config register.This is used to \ + set the upper boundary of the reclaim region. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_BOUND_L_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x48) /* Sm abuf0 reclaim lower boundary config register. This register is used to set \ + the lower boundary of the reclaim region. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_PF_LIFO_CLR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x4C) /* This is the Sm abuf0 pre-fetch lifo clear register.This is used to clear any \ + pfetch lifos if software wants.(here lifo means Last in first out) */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_MEM_CFG_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x50) /* This is the Sm abuf0 parity bit check enable config register. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_INT_VECTOR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x54) /* This is the Smart Memory (SM) abuf0 interrupt vector register.This is used \ + to determine the CP interrupt address, disable and enable an interrupt \ + report,and provide the total status of an abuf0 interrupt. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_INT_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x58) /* This is the SM abuf0 interrupt data register.This is used to record the history of the interrupt \ + status since the last clear operation. Software can use this register to let the CP know, which CSR \ + module, or group of CSR modules, requested the interrupt. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_INT_MASK_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x5C) /* This is the SM abuf0 interrupt mask register.This is used to mask the bits of the interrupt register \ + that should not be reported to an upper level.Software can use this register to mask corresponding \ + bits if they do not want those bits reporting to an upper level. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_PBERR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x60) /* This is the ireq_list's output data Parity Bit Error interrupt register.Software can get related \ + ireq_list information from this register. This register is used for debug. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FL_UFLOW_ERR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x64) /* This is the free list underflow error interrupt register.This register is used to record the \ + underflow status of 32 free lists.Any free lists are in underflow status,this register will \ + trigger.This register is used for debug. Software can use this register to scan the status of 32 \ + free lists. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FL_OFLOW_ERR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x68) /* This is the free list overflow error interrupt register.This register is used to record the overflow \ + status of 32 free lists.If any free lists are in an overflow state,this register will trigger.This \ + register is used for debug. Software can use this register to scan the status of the 32 free \ + lists. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FL_TAIL_MISS_ERR_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x6C) /* This is the tail missed error interrupt register.This is used to capture information of regarding \ + list whose tail pointer is not equal to the last pointer of the link list,when the free node \ + group(including the last pointer) is load from outside DDR.This register is used for debug. */ +#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF_INDRECT_CTRL_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x70) /* indirect access address registers */ +#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF_INDRECT_TIMEOUT_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x74) /* memory access timeout configure */ +#define CSR_SMEG0_ABUF0_CSR_SMEG0_ABUF_INDRECT_DATA_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x78) /* indirect access data registers */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_DIS_ALLOC_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x7C) /* This is the SM Abuf0 disable allocation config register.This is used by software to disable the \ + allocate operation if you do not want to release any free nodes from the particular list. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_DIS_DE_ALLOC_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x80) /* This is the SM Abuf0 de_allocate disable config register.This is used by software to disable the \ + de-allocate operation if you do not want to put any free nodes to the particular list. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FLRC_ST_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x84) /* This is the Sm abuf0 free list reclaim status register.This is used by the \ + software to scan the reclaimed working state. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_EMPTY_FL_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x88) /* This is the Sm abuf0 free list empty status register.This is used by software \ + to scan whether regarding list is empty or not. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_FULL_FL_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x8C) /* This is the Sm abuf0 free list full/almost full status register.This is used by the software to scan \ + whether the list is full, almost full, or none of the above. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ST_WM_GROW_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + \ + 0x90) /* This is the Sm abuf0 free list grow watermark status register.This is used by the softeware to scan \ + whether the free list is in status that need to grow. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ST_WM_SHRINK_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x94) /* This is the Sm abuf0 free list shrink watermark status register.This is used \ + by the softeware to scan whether the free list is in a shrink status. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_SEL0_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x98) /* This is the Sm abuf0 csr counter select config register.This is used to \ + select which free list must be counted. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_SEL1_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0x9C) /* Sm abuf ireq list status register.Sw can use this register to judge if the \ + request queue is empty or not. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER0_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xA0) /* This is the Sm abuf0 allocate free node count register.This is used to count \ + the free nodes that have been allocated successfully by abuf0. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER1_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xA4) /* This is the Sm abuf0 de-allocate free node count register.This is used to \ + count the free nodes that have been de-allocated successfully by abuf0. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER2_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xA8) /* This is the allocate failed operation count register.This is used to count \ + the total number of failed allocate operation attempts. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER3_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xAC) /* This is the Sm abuf0 de-allocate failed operation count register.This is used \ + to count the total number of failed de-allocate operation attempts. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER4_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xB0) /* This is the Sm abuf0 total pre-fetch load operation count register.This is \ + used to count the total number of pre-fetched load operations. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_COUNTER5_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xB4) /* This is the Sm abuf0 total pre-fetch store operation count register.This is \ + used to count the total pre-fetched store operations. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_PFETCH_FLAG_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xB8) /* Sm abuf pre-fetch load/store setup flag.This is used to record which free \ + list has initiated pre-fetch load/store operation. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_IREQ_LIST_STA_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xBC) /* Sm abuf ireq list status register.Sw can use this register to judge if the \ + request queue is empty or not. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TAIL_MISS0_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xC0) /* This is the SM abuf0 tail miss capture register. This is used to capture the \ + information of the tail-missed free list. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_TAIL_MISS1_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xC8) /* This is the SM abuf0 tail miss capture register. This is used to capture the \ + information of the tail-missed free list. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_LIFO_PFETCH_0_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xD0) /* This is the Sm abuf0 pfetch lifo node number register.This is used to record \ + the free node number in each pfetch lifo. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_LIFO_PFETCH_1_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xD8) /* This is the Sm abuf0 pfetch lifo node number register.This is used to record \ + the free node number in each pfetch lifo. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_CNT_LIFO_PFETCH_2_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xE0) /* This is the Sm abuf0 pfetch lifo node number register.This is used to record \ + the free node number in each pfetch lifo. */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ECC_CFG_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xE4) /* SMEG0_ABUF ECC function configration register */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ECC_1B_ERR_INT_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xE8) /* 1 bit error sticky register */ +#define CSR_SMEG0_ABUF0_CSR_SM_ABUF_ECC_2B_ERR_INT_REG \ + (CSR_SMEG0_ABUF0_CSR_BASE + 0xEC) /* 2 bit error sticky register */ + +/* smeg0_aget_csr Base address of Module's Register */ +#define CSR_SMEG0_AGET_CSR_BASE (0x300) + +/* **************************************************************************** */ +/* smeg0_aget_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_VERSION_REG (CSR_SMEG0_AGET_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_CFG_REG (CSR_SMEG0_AGET_CSR_BASE + 0x4) /* age table configure registers */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INT_VECTOR_REG (CSR_SMEG0_AGET_CSR_BASE + 0x8) /* interrupt vector */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INT_REG (CSR_SMEG0_AGET_CSR_BASE + 0xC) /* interrupt data */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INT_MASK_REG (CSR_SMEG0_AGET_CSR_BASE + 0x10) /* interrupt mask */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_MEM_PRTY_ERR_REG \ + (CSR_SMEG0_AGET_CSR_BASE + 0x14) /* SMEG0_AGET age flag memory parity error */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_BOUNDARY_ERR_REG \ + (CSR_SMEG0_AGET_CSR_BASE + 0x18) /* SMEG0_AGET operation is out of the table boundary */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INDRECT_CTRL_REG \ + (CSR_SMEG0_AGET_CSR_BASE + 0x1C) /* indirect access address registers */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INDRECT_TIMEOUT_REG \ + (CSR_SMEG0_AGET_CSR_BASE + 0x20) /* memory access timeout configure */ +#define CSR_SMEG0_AGET_CSR_SMEG0_AGET_INDRECT_DATA_REG \ + (CSR_SMEG0_AGET_CSR_BASE + 0x24) /* indirect access data registers */ +#define CSR_SMEG0_AGET_CSR_SMEG_CORE_MEM_INIT_REG (CSR_SMEG0_AGET_CSR_BASE + 0x28) /* smeg core memory init done flag \ + */ +#define CSR_SMEG0_AGET_CSR_SMEG0_CNT0_REG (CSR_SMEG0_AGET_CSR_BASE + 0x2C) /* SMEG0 Counter 0 */ +#define CSR_SMEG0_AGET_CSR_SMEG0_CNT1_REG (CSR_SMEG0_AGET_CSR_BASE + 0x30) /* SMEG0 Counter 1 */ + +/* smeg0_lu_csr Base address of Module's Register */ +#define CSR_SMEG0_LU_CSR_BASE (0x400) + +/* **************************************************************************** */ +/* smeg0_lu_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMEG0_LU_CSR_SMEG0_LU_VERSION_REG (CSR_SMEG0_LU_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CHK_ENABLE_CFG_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x4) /* configuration register for memory check enbale */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_INT_VECTOR_REG (CSR_SMEG0_LU_CSR_BASE + 0x8) /* interrupt vector */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_INT_REG (CSR_SMEG0_LU_CSR_BASE + 0xC) /* interrupt data */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_INT_MASK_REG (CSR_SMEG0_LU_CSR_BASE + 0x10) /* interrupt mask */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x14) /* SMEG0_LOOKUP_PIPE0MEM ECC 1bit error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x18) /* SMEG0_LOOKUP_PIPE0MEM ECC multi-bit error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x1C) /* SMEG0_LOOKUP_PIPE1MEM ECC 1bit error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x20) /* SMEG0_LOOKUP_PIPE1MEM ECC multi-bit error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x24) /* SMEG0_LU_FLITFIFO 1bit error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x28) /* SMEG0_LU_FLITFIFO multi-bit error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_SW_ERR_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x2C) /* BTREE engine detected software fatal error */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_INDRECT_CTRL_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x30) /* indirect access address registers */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_INDRECT_TIMEOUT_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x34) /* memory access timeout configure */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_INDRECT_DATA_REG (CSR_SMEG0_LU_CSR_BASE + 0x38) /* indirect access data registers */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_ERR_INJ_CFG_REG \ + (CSR_SMEG0_LU_CSR_BASE + \ + 0x3C) /* configuration register for error injection of FIFO memories. FIFO doesn't support CSR access. \ + Software can set error inject enable bit to test error handling. */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT_CFG_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x40) /* counter related configuration register */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT0_REG (CSR_SMEG0_LU_CSR_BASE + 0x44) /* counter0 */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT1_REG (CSR_SMEG0_LU_CSR_BASE + 0x48) /* counter1 */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT2_REG (CSR_SMEG0_LU_CSR_BASE + 0x4C) /* counter2 */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CNT3_REG (CSR_SMEG0_LU_CSR_BASE + 0x50) /* counter3 */ +#define CSR_SMEG0_LU_CSR_SMEG0_LU_CTP_REG \ + (CSR_SMEG0_LU_CSR_BASE + 0x54) /* SMEG0 Profile Register for performance monitor. */ + +/* smeg1_csr Base address of Module's Register */ +#define CSR_SMEG1_CSR_BASE (0x500) + +/* **************************************************************************** */ +/* smeg1_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMEG1_CSR_SMEG1_VERSION_REG (CSR_SMEG1_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMEG1_CSR_SMEG1_CFG0_REG \ + (CSR_SMEG1_CSR_BASE + 0x4) /* Smart Memory Infra Engine Group1 (SMEG1) configuration register . This is used to \ + configure additional features, and for debug. */ +#define CSR_SMEG1_CSR_SMEG1_CFG1_REG \ + (CSR_SMEG1_CSR_BASE + 0x8) /* Smart Memory Infra Engine Group1 (SMEG1) configuration register . */ +#define CSR_SMEG1_CSR_SMEG1_RUNAWAY_CFG_REG \ + (CSR_SMEG1_CSR_BASE + 0xC) /* Smart Memory Infra Engine Group1 (SMEG1) Runaway sampling count configuration \ + register. In the normal operation, this can be used as a watch dog timer for 16 or \ + 64 threads in a smart memory tile. */ +#define CSR_SMEG1_CSR_SMEG1_THREAD_ENABLE_CFG_REG \ + (CSR_SMEG1_CSR_BASE + 0x10) /* Thread enable configure; bitmap for 16/32/64 thread in smeg1;Refer to \ + "SMEG1_THREAD_ENABLE_CFG2" for thread[63:32] enable; */ +#define CSR_SMEG1_CSR_SMEG1_TM_TS_FAST2_REG (CSR_SMEG1_CSR_BASE + 0x14) /* timer wheel control info */ +#define CSR_SMEG1_CSR_SMEG1_TM_TS_FAST3_REG (CSR_SMEG1_CSR_BASE + 0x18) /* TIMER engine wheel control info */ +#define CSR_SMEG1_CSR_SMEG1_TM_TS_SLOW0_REG (CSR_SMEG1_CSR_BASE + 0x1C) /* TIMER engine control info */ +#define CSR_SMEG1_CSR_SMEG1_TM_TS_SLOW1_REG (CSR_SMEG1_CSR_BASE + 0x20) /* TIMER engine control info */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG7_REG (CSR_SMEG1_CSR_BASE + 0x24) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG6_REG (CSR_SMEG1_CSR_BASE + 0x28) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG5_REG (CSR_SMEG1_CSR_BASE + 0x2C) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG4_REG (CSR_SMEG1_CSR_BASE + 0x30) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG3_REG (CSR_SMEG1_CSR_BASE + 0x34) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG2_REG (CSR_SMEG1_CSR_BASE + 0x38) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG1_REG (CSR_SMEG1_CSR_BASE + 0x3C) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_TM_TMT_CFG0_REG (CSR_SMEG1_CSR_BASE + 0x40) /* TIMER engine type cfg */ +#define CSR_SMEG1_CSR_SMEG1_INT_VECTOR_REG (CSR_SMEG1_CSR_BASE + 0x44) +#define CSR_SMEG1_CSR_SMEG1_INT_REG (CSR_SMEG1_CSR_BASE + 0x48) +#define CSR_SMEG1_CSR_SMEG1_INT_MASK_REG (CSR_SMEG1_CSR_BASE + 0x4C) +#define CSR_SMEG1_CSR_SMEG1_ENGINE_SW_ERR_REG \ + (CSR_SMEG1_CSR_BASE + \ + 0x50) /* This is Smart Memory Infra Engine Group1 (SMEG1) engine software error log register. */ +#define CSR_SMEG1_CSR_SMEG1_ERR0_REG (CSR_SMEG1_CSR_BASE + 0x54) /* error register 0 */ +#define CSR_SMEG1_CSR_SMEG1_ERR0_MASK_REG (CSR_SMEG1_CSR_BASE + 0x58) /* error register 1 */ +#define CSR_SMEG1_CSR_SMEG1_ERR1_REG (CSR_SMEG1_CSR_BASE + 0x5C) +#define CSR_SMEG1_CSR_SMEG1_ERR1_MASK_REG (CSR_SMEG1_CSR_BASE + 0x60) +#define CSR_SMEG1_CSR_SMEG1_INDRECT_CTRL_REG (CSR_SMEG1_CSR_BASE + 0x64) /* indirect access address registers */ +#define CSR_SMEG1_CSR_SMEG1_INDRECT_TIMEOUT_REG (CSR_SMEG1_CSR_BASE + 0x68) /* memory access timeout configure */ +#define CSR_SMEG1_CSR_SMEG1_INDRECT_DATA_REG (CSR_SMEG1_CSR_BASE + 0x6C) /* indirect access data registers */ +#define CSR_SMEG1_CSR_SMEG1_CNT_CFG_REG \ + (CSR_SMEG1_CSR_BASE + 0x70) /* SMEG1 counter configuration register. This register is used for debug or for \ + statistics collection */ +#define CSR_SMEG1_CSR_SMEG1_CNT_MATCH_ID_REG \ + (CSR_SMEG1_CSR_BASE + 0x74) /* This register is used to configure Instance IDs for all four counters. This can be \ + used for debug or for performance analysis. */ +#define CSR_SMEG1_CSR_SMEG1_CNT0_REG \ + (CSR_SMEG1_CSR_BASE + \ + 0x78) /* This smmeg1 counter0 register is a statistics counter that counts API install and engine event0 */ +#define CSR_SMEG1_CSR_SMEG1_CNT1_REG \ + (CSR_SMEG1_CSR_BASE + 0x80) /* This smeg1 counter1 register is a statistics counter that counts load, store, \ + sleep, wakeup, and engine event 1 */ +#define CSR_SMEG1_CSR_SMEG1_CNT2_REG \ + (CSR_SMEG1_CSR_BASE + \ + 0x88) /* This smeg1 counter1 register is a statistics counter that counts 'finish' or engine event 2 */ +#define CSR_SMEG1_CSR_SMEG1_CNT3_REG \ + (CSR_SMEG1_CSR_BASE + \ + 0x90) /* This smeg1 counter3 register is a statistics counter that counts 'send' and engine event 3 */ +#define CSR_SMEG1_CSR_RSV_1_REG (CSR_SMEG1_CSR_BASE + 0x98) /* reserved */ +#define CSR_SMEG1_CSR_RSV_2_REG (CSR_SMEG1_CSR_BASE + 0x9C) /* reserved */ +#define CSR_SMEG1_CSR_SMEG1_THREAD_ENABLE_CFG2_REG \ + (CSR_SMEG1_CSR_BASE + 0xA0) /* Thread enable configure; bitmap for thread[63:32] of 64 threads in smeg1 */ +#define CSR_SMEG1_CSR_RSV_3_REG (CSR_SMEG1_CSR_BASE + 0xA4) /* reserved */ +#define CSR_SMEG1_CSR_RSV_4_REG (CSR_SMEG1_CSR_BASE + 0xA8) /* reserved */ +#define CSR_SMEG1_CSR_RSV_5_REG (CSR_SMEG1_CSR_BASE + 0xAC) /* reserved */ +#define CSR_SMEG1_CSR_RSV_6_REG (CSR_SMEG1_CSR_BASE + 0xB0) /* reserved */ +#define CSR_SMEG1_CSR_SMEG1_TMT_EXT_CFG_REG (CSR_SMEG1_CSR_BASE + 0xB4) /* TIMER engine control info */ +#define CSR_SMEG1_CSR_SMEG1_MEM_ECC_ERR_CTP_REG \ + (CSR_SMEG1_CSR_BASE + \ + 0xB8) /* ecc ERR ADDR; CAPTURE the last err addr;only valid when the ECC interrupt is reported; */ +#define CSR_SMEG1_CSR_SMMC_CACHE_RESOURCE_CTP_REG (CSR_SMEG1_CSR_BASE + 0xBC) /* SMMC WQE Cache resource counter */ +#define CSR_SMEG1_CSR_SMEG1_SYNC_API_CFG_REG (CSR_SMEG1_CSR_BASE + 0xC0) /* SYNC_API configuration register */ +#define CSR_SMEG1_CSR_RSV_183_REG (CSR_SMEG1_CSR_BASE + 0xC4) /* reserved */ +#define CSR_SMEG1_CSR_SMEG1_CUR_TIMESTAMP_US_REG (CSR_SMEG1_CSR_BASE + 0xC8) /* Current timestamp (us) */ +#define CSR_SMEG1_CSR_SMEG1_RUNAWAY_THD_CTP_REG \ + (CSR_SMEG1_CSR_BASE + 0xD0) /* Each bit represents a runaway thread. When a thread runs for more than a sampling \ + time, it is considered a runaway thread. Bit63 logs runaway errors for the thread \ + 63, and bit0 logs the error for the thread 0 respectively. */ +#define CSR_SMEG1_CSR_SMEG1_CTP0_REG \ + (CSR_SMEG1_CSR_BASE + 0xD8) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */ +#define CSR_SMEG1_CSR_SMEG1_CTP1_REG \ + (CSR_SMEG1_CSR_BASE + 0xE0) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */ +#define CSR_SMEG1_CSR_SMEG1_CTP2_REG \ + (CSR_SMEG1_CSR_BASE + 0xE8) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */ +#define CSR_SMEG1_CSR_SMEG1_CTP3_REG \ + (CSR_SMEG1_CSR_BASE + 0xF0) /* This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. */ + +/* smit_csr Base address of Module's Register */ +#define CSR_SMIT_CSR_BASE (0x600) + +/* **************************************************************************** */ +/* smit_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMIT_CSR_SMIT_VERSION_REG (CSR_SMIT_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMIT_CSR_SMIT_CFG_REG \ + (CSR_SMIT_CSR_BASE + 0x4) /* This is the Smart Memory Infra Transmission (SMIT) module configuration register. \ + The software use this register for debug. */ +#define CSR_SMIT_CSR_SMIT_INT_VECTOR_REG (CSR_SMIT_CSR_BASE + 0x8) /* SMIT interrupt vector */ +#define CSR_SMIT_CSR_SMIT_INT_REG (CSR_SMIT_CSR_BASE + 0xC) /* SMIT interrupt status vector */ +#define CSR_SMIT_CSR_SMIT_INT_MASK_REG (CSR_SMIT_CSR_BASE + 0x10) /* SMIT interrupt mask vector */ +#define CSR_SMIT_CSR_SMIT_ERR_PRTY_REG (CSR_SMIT_CSR_BASE + 0x14) /* RSV */ +#define CSR_SMIT_CSR_SMIT_MEM_ECC_CRT_ERR_REG (CSR_SMIT_CSR_BASE + 0x18) /* tmdr ecc correctable err */ +#define CSR_SMIT_CSR_SMIT_MEM_ECC_UNCRT_ERR_REG (CSR_SMIT_CSR_BASE + 0x1C) /* tmdr ecc uncorrectable err */ +#define CSR_SMIT_CSR_SMIT_INDRECT_CTRL_REG (CSR_SMIT_CSR_BASE + 0x20) /* indirect access address registers */ +#define CSR_SMIT_CSR_SMIT_INDRECT_TIMEOUT_REG (CSR_SMIT_CSR_BASE + 0x24) /* memory access timeout configure */ +#define CSR_SMIT_CSR_SMIT_INDRECT_DATA_REG (CSR_SMIT_CSR_BASE + 0x28) /* indirect access data registers */ +#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS0_REG (CSR_SMIT_CSR_BASE + 0x2C) /* RAM CTRL_BUS寄存器0 */ +#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS1_REG (CSR_SMIT_CSR_BASE + 0x30) /* RAM CTRL_BUS寄存器1 */ +#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS2_REG (CSR_SMIT_CSR_BASE + 0x34) /* RAM CTRL_BUS寄存器2 */ +#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS3_REG (CSR_SMIT_CSR_BASE + 0x38) /* RAM CTRL_BUS寄存器3 */ +#define CSR_SMIT_CSR_CFG_MEM_CTRL_BUS4_REG (CSR_SMIT_CSR_BASE + 0x3C) /* RAM CTRL_BUS寄存器4 */ + +/* smlc_csr Base address of Module's Register */ +#define CSR_SMLC_CSR_BASE (0x700) + +/* **************************************************************************** */ +/* smlc_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMLC_CSR_SMLC_VERSION_REG (CSR_SMLC_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMLC_CSR_SMLC_CFG0_REG \ + (CSR_SMLC_CSR_BASE + 0x4) /* Smart Memory Lock Cache Controller (SMLC) configuration 0. */ +#define CSR_SMLC_CSR_SMLC_CFG1_REG \ + (CSR_SMLC_CSR_BASE + 0x8) /* Smart Memory Lock Cache Controller (SMLC) configuration 1. */ +#define CSR_SMLC_CSR_SMLC_CFG2_REG \ + (CSR_SMLC_CSR_BASE + 0xC) /* Smart Memory Lock Cache Controller (SMLC) configuration 2. */ +#define CSR_SMLC_CSR_SMLC_INT_VECTOR_REG \ + (CSR_SMLC_CSR_BASE + 0x10) /* Smart Memory Lock Cache Controller (SMLC) interrupt vector register */ +#define CSR_SMLC_CSR_SMLC_INT_REG \ + (CSR_SMLC_CSR_BASE + 0x14) /* Smart Memory Lock Cache Controller (SMLC) interrupt data register */ +#define CSR_SMLC_CSR_SMLC_INT_MASK_REG \ + (CSR_SMLC_CSR_BASE + 0x18) /* Smart Memory Lock Cache Controller (SMLC) interrupt mask register. */ +#define CSR_SMLC_CSR_SMLC_SRF_OV_ERR_REG (CSR_SMLC_CSR_BASE + 0x1C) /* srf fifo overflow error. */ +#define CSR_SMLC_CSR_SMLC_RSV_REG (CSR_SMLC_CSR_BASE + 0x20) +#define CSR_SMLC_CSR_SMLC_ECC_ERR_REG (CSR_SMLC_CSR_BASE + 0x24) /* memory ecc error. */ +#define CSR_SMLC_CSR_SMLC_ECC_ERRPR_MASK_REG (CSR_SMLC_CSR_BASE + 0x28) +#define CSR_SMLC_CSR_SMLC_INDRECT_CTRL_REG (CSR_SMLC_CSR_BASE + 0x2C) /* indirect access address registers */ +#define CSR_SMLC_CSR_SMLC_INDRECT_TIMEOUT_REG (CSR_SMLC_CSR_BASE + 0x30) /* memory access timeout configure */ +#define CSR_SMLC_CSR_SMLC_INDRECT_DATA_REG (CSR_SMLC_CSR_BASE + 0x34) /* indirect access data registers */ +#define CSR_SMLC_CSR_SMLC_CNT0_REG \ + (CSR_SMLC_CSR_BASE + 0x38) /* Smart Memory Lock Cache Controller (SMLC) event counter0 */ +#define CSR_SMLC_CSR_SMLC_CNT1_REG \ + (CSR_SMLC_CSR_BASE + 0x40) /* Smart Memory Lock Cache Controller (SMLC) event counter1 */ +#define CSR_SMLC_CSR_SMLC_CNT2_REG \ + (CSR_SMLC_CSR_BASE + 0x48) /* Smart Memory Lock Cache Controller (SMLC) event counter2 */ +#define CSR_SMLC_CSR_SMLC_CNT3_REG \ + (CSR_SMLC_CSR_BASE + 0x50) /* Smart Memory Lock Cache Controller (SMLC) event counter3 */ +#define CSR_SMLC_CSR_SMLC_CNT_CFG0_REG \ + (CSR_SMLC_CSR_BASE + 0x58) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 0 */ +#define CSR_SMLC_CSR_SMLC_CNT_CFG1_REG \ + (CSR_SMLC_CSR_BASE + 0x5C) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 1 */ +#define CSR_SMLC_CSR_SMLC_CREDIT_CTP_REG \ + (CSR_SMLC_CSR_BASE + 0x60) /* Smart Memory Lock Cache Controller (SMLC)credit snapshot register. */ +#define CSR_SMLC_CSR_SMLC_FIFO_DEPTH_CTP_REG \ + (CSR_SMLC_CSR_BASE + 0x64) /* Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register. */ +#define CSR_SMLC_CSR_SMLC_ECC_ERR_CTP_REG \ + (CSR_SMLC_CSR_BASE + 0x68) /* Smart Memory Lock Cache Controller (SMLC)parity error snapshot register. */ + +/* virtio_smlc_csr Base address of Module's Register */ +#define CSR_VIRTIO_SMLC_CSR_BASE (0x2700) + +/* **************************************************************************** */ +/* virtio_smlc_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_VIRTIO_SMLC_CSR_SMLC_VERSION_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CFG0_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x4) /* Smart Memory Lock Cache Controller (SMLC) configuration 0. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CFG1_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x8) /* Smart Memory Lock Cache Controller (SMLC) configuration 1. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CFG2_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0xC) /* Smart Memory Lock Cache Controller (SMLC) configuration 2. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_INT_VECTOR_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x10) /* Smart Memory Lock Cache Controller (SMLC) interrupt vector register */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_INT_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x14) /* Smart Memory Lock Cache Controller (SMLC) interrupt data register */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_INT_MASK_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x18) /* Smart Memory Lock Cache Controller (SMLC) interrupt mask register. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_SRF_OV_ERR_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x1C) /* srf fifo overflow error. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_RSV_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x20) +#define CSR_VIRTIO_SMLC_CSR_SMLC_ECC_ERR_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x24) /* memory ecc error. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_ECC_ERRPR_MASK_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x28) +#define CSR_VIRTIO_SMLC_CSR_SMLC_INDRECT_CTRL_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x2C) /* indirect access address registers */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_INDRECT_TIMEOUT_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x30) /* memory access timeout configure */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_INDRECT_DATA_REG (CSR_VIRTIO_SMLC_CSR_BASE + 0x34) /* indirect access data registers \ + */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT0_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x38) /* Smart Memory Lock Cache Controller (SMLC) event counter0 */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT1_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x40) /* Smart Memory Lock Cache Controller (SMLC) event counter1 */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT2_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x48) /* Smart Memory Lock Cache Controller (SMLC) event counter2 */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT3_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x50) /* Smart Memory Lock Cache Controller (SMLC) event counter3 */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT_CFG0_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x58) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 0 */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CNT_CFG1_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x5C) /* Smart Memory Lock Cache Controller (SMLC) event counter configuration 1 */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_CREDIT_CTP_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x60) /* Smart Memory Lock Cache Controller (SMLC)credit snapshot register. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_FIFO_DEPTH_CTP_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x64) /* Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register. */ +#define CSR_VIRTIO_SMLC_CSR_SMLC_ECC_ERR_CTP_REG \ + (CSR_VIRTIO_SMLC_CSR_BASE + 0x68) /* Smart Memory Lock Cache Controller (SMLC)parity error snapshot register. */ + +/* smmc_f_csr Base address of Module's Register */ +#define CSR_SMMC_F_CSR_BASE (0x800) + +/* **************************************************************************** */ +/* smmc_f_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMMC_F_CSR_SMMC_F_VERSION_REG (CSR_SMMC_F_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CFG_REG (CSR_SMMC_F_CSR_BASE + 0x4) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CFG1_REG (CSR_SMMC_F_CSR_BASE + 0x8) +#define CSR_SMMC_F_CSR_SMMC_HASH_SEED0_REG \ + (CSR_SMMC_F_CSR_BASE + 0xC) /* Hash function seed conifg register. This register used to change the original seed \ + of hash function. */ +#define CSR_SMMC_F_CSR_SMMC_HASH_SEED1_REG \ + (CSR_SMMC_F_CSR_BASE + 0x10) /* Hash function seed conifg register. This register used to change the original seed \ + of hash function. */ +#define CSR_SMMC_F_CSR_SMMC_F_CFG_REG (CSR_SMMC_F_CSR_BASE + 0x14) /* SMMF_F configuration register . */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_INIT_REG (CSR_SMMC_F_CSR_BASE + 0x18) /* SMMC_F main cache initialization */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_REG (CSR_SMMC_F_CSR_BASE + 0x1C) +#define CSR_SMMC_F_CSR_SMMC_F_INT_VECTOR_REG \ + (CSR_SMMC_F_CSR_BASE + 0x20) /* Statefull Smart Memory Memory Controller (SMMC_F) interrupt vector register */ +#define CSR_SMMC_F_CSR_SMMC_F_INT_REG \ + (CSR_SMMC_F_CSR_BASE + 0x24) /* Smart Memory Memory Controller (SMMC) interrupt data register */ +#define CSR_SMMC_F_CSR_SMMC_F_INT_MASK_REG \ + (CSR_SMMC_F_CSR_BASE + 0x28) /* Statefull Smart Memory Memory Controller (SMMC_F) interrupt mask register. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CACHE_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x2C) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CACHE_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x30) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CACHE_ERR_INFO_REG (CSR_SMMC_F_CSR_BASE + 0x34) +#define CSR_SMMC_F_CSR_SMMC_F_BUFFER_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x38) +#define CSR_SMMC_F_CSR_SMMC_F_BUFFER_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x3C) +#define CSR_SMMC_F_CSR_SMMC_F_BUFFER_ERR_INFO_REG (CSR_SMMC_F_CSR_BASE + 0x40) +#define CSR_SMMC_F_CSR_SMMC_F_BUS_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x44) +#define CSR_SMMC_F_CSR_SMMC_F_BUS_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x48) +#define CSR_SMMC_F_CSR_SMMC_F_MC_MULTI_HIT_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x4C) +#define CSR_SMMC_F_CSR_SMMC_F_VC_CACHE_ERR_REG (CSR_SMMC_F_CSR_BASE + 0x50) +#define CSR_SMMC_F_CSR_SMMC_F_VC_CACHE_MASK_REG (CSR_SMMC_F_CSR_BASE + 0x54) +#define CSR_SMMC_F_CSR_SMMC_F_VC_CACHE_ERR_INFO_REG (CSR_SMMC_F_CSR_BASE + 0x58) +#define CSR_SMMC_F_CSR_SMMC_F_INDRECT_CTRL_REG (CSR_SMMC_F_CSR_BASE + 0x5C) /* indirect access address registers */ +#define CSR_SMMC_F_CSR_SMMC_F_INDRECT_TIMEOUT_REG (CSR_SMMC_F_CSR_BASE + 0x60) /* memory access timeout configure */ +#define CSR_SMMC_F_CSR_SMMC_F_INDRECT_DATA_REG (CSR_SMMC_F_CSR_BASE + 0x64) /* indirect access data registers */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_ENB_REG (CSR_SMMC_F_CSR_BASE + 0x68) /* counter enable */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_REG \ + (CSR_SMMC_F_CSR_BASE + 0x6C) /* counter event selection enable */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_REG \ + (CSR_SMMC_F_CSR_BASE + 0x70) /* counter event selection enable */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL0_REG (CSR_SMMC_F_CSR_BASE + 0x74) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL1_REG (CSR_SMMC_F_CSR_BASE + 0x78) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL2_REG (CSR_SMMC_F_CSR_BASE + 0x7C) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL3_REG (CSR_SMMC_F_CSR_BASE + 0x80) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL4_REG (CSR_SMMC_F_CSR_BASE + 0x84) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL5_REG (CSR_SMMC_F_CSR_BASE + 0x88) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL6_REG (CSR_SMMC_F_CSR_BASE + 0x8C) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT_EVENT_SEL7_REG (CSR_SMMC_F_CSR_BASE + 0x90) +#define CSR_SMMC_F_CSR_SMMC_F_MC_STATUS_REG (CSR_SMMC_F_CSR_BASE + 0x94) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT0_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0x98) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB0 and SMMC_F_MC_CNT_EVENT_SEL0. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT1_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xA0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB1 and SMMC_F_MC_CNT_EVENT_SEL1. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT2_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xA8) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB2 and SMMC_F_MC_CNT_EVENT_SEL2. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT3_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xB0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB3 and SMMC_F_MC_CNT_EVENT_SEL3. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT4_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xB8) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB4 and SMMC_F_MC_CNT_EVENT_SEL4. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT5_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xC0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB5 and SMMC_F_MC_CNT_EVENT_SEL5. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT6_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xC8) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB6 and SMMC_F_MC_CNT_EVENT_SEL6. */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_CNT7_REG \ + (CSR_SMMC_F_CSR_BASE + \ + 0xD0) /* This SMMC main cache counter0 register is a dynamic counter to count any event that is configured by \ + SMMC_F_MC_CNT_EVENT_SEL_ENB7 and SMMC_F_MC_CNT_EVENT_SEL7. */ +#define CSR_SMMC_F_CSR_SMMC_F_VC_FIFO_DEPTH0_REG \ + (CSR_SMMC_F_CSR_BASE + 0xD8) /* SMMC_F victim cache FIFO depth or credit */ +#define CSR_SMMC_F_CSR_SMMC_F_VC_FIFO_DEPTH1_REG \ + (CSR_SMMC_F_CSR_BASE + 0xDC) /* SMMC_F victim cache FIFO depth or credit */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_FIFO1_DEPTH_REG \ + (CSR_SMMC_F_CSR_BASE + 0xE0) /* SMMC_F main cache FIFO depth or credit */ +#define CSR_SMMC_F_CSR_SMMC_F_MC_FIFO2_DEPTH_REG (CSR_SMMC_F_CSR_BASE + 0xE4) /* SMMC_F main cache FIFO depth */ +#define CSR_SMMC_F_CSR_SMMC_F_ERR_INJ_REG (CSR_SMMC_F_CSR_BASE + 0xE8) +#define CSR_SMMC_F_CSR_SMMC_F_GPA_TRANS_ERR_REG (CSR_SMMC_F_CSR_BASE + 0xEC) +#define CSR_SMMC_F_CSR_SMMC_F_QU_INTF_CNT_CFG_REG (CSR_SMMC_F_CSR_BASE + 0xF0) +#define CSR_SMMC_F_CSR_SMMC_F_QU_INTF_RX_CNT_REG (CSR_SMMC_F_CSR_BASE + 0xF4) +#define CSR_SMMC_F_CSR_SMMC_F_QU_INTF_TX_CNT_REG (CSR_SMMC_F_CSR_BASE + 0xF8) +#define CSR_SMMC_F_CSR_SMMC_F_MC_CFG2_REG (CSR_SMMC_F_CSR_BASE + 0xFC) + +/* smmc_l_csr Base address of Module's Register */ +#define CSR_SMMC_L_CSR_BASE (0x900) + +/* **************************************************************************** */ +/* smmc_l_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMMC_L_CSR_SMMC_L_VERSION_REG (CSR_SMMC_L_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMMC_L_CSR_SMMC_L_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x4) /* SMMC_L configure register */ +#define CSR_SMMC_L_CSR_SMMC_L_STAT_REG (CSR_SMMC_L_CSR_BASE + 0x8) /* SMMC_L status register */ +#define CSR_SMMC_L_CSR_SMMC_L_INT_VECTOR_REG (CSR_SMMC_L_CSR_BASE + 0xC) /* SMMC_L interrupt vector register */ +#define CSR_SMMC_L_CSR_SMMC_L_INT_REG (CSR_SMMC_L_CSR_BASE + 0x10) /* SMMC_L interrupt register */ +#define CSR_SMMC_L_CSR_SMMC_L_INT_MASK_REG (CSR_SMMC_L_CSR_BASE + 0x14) /* SMMC_L interrupt mask register */ +#define CSR_SMMC_L_CSR_SMMC_L_MEM_ERR_REG (CSR_SMMC_L_CSR_BASE + 0x18) /* SMMC_L MEM error register */ +#define CSR_SMMC_L_CSR_SMMC_L_MEM_ERR_MASK_REG (CSR_SMMC_L_CSR_BASE + 0x1C) /* SMMC_L MEM error mask register */ +#define CSR_SMMC_L_CSR_SMMC_L_MEM_ERR_INFO_REG (CSR_SMMC_L_CSR_BASE + 0x20) /* SMMC_L MEM error info register */ +#define CSR_SMMC_L_CSR_SMMC_L_INDRECT_CTRL_REG (CSR_SMMC_L_CSR_BASE + 0x24) /* indirect access address registers */ +#define CSR_SMMC_L_CSR_SMMC_L_INDRECT_TIMEOUT_REG (CSR_SMMC_L_CSR_BASE + 0x28) /* memory access timeout configure */ +#define CSR_SMMC_L_CSR_SMMC_L_INDRECT_DATA_REG (CSR_SMMC_L_CSR_BASE + 0x2C) /* indirect access data registers */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x30) /* SMMC_L counter configure register */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT_MATCH_BANK_REG \ + (CSR_SMMC_L_CSR_BASE + 0x34) /* SMMC_L counter configure register for matching instance ID */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT_MATCH_INSTANCE_REG \ + (CSR_SMMC_L_CSR_BASE + 0x38) /* SMMC_L counter configure register for matching instance ID */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT0_REG (CSR_SMMC_L_CSR_BASE + 0x3C) /* SMMC_L counter 0 register */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT1_REG (CSR_SMMC_L_CSR_BASE + 0x40) /* SMMC_L counter 1 register */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT2_REG (CSR_SMMC_L_CSR_BASE + 0x44) /* SMMC_L counter 2 register */ +#define CSR_SMMC_L_CSR_SMMC_L_CNT3_REG (CSR_SMMC_L_CSR_BASE + 0x48) /* SMMC_L counter 3 register */ +#define CSR_SMMC_L_CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_REG \ + (CSR_SMMC_L_CSR_BASE + 0x4C) /* SMMC_L bank queue's depth register 0 */ +#define CSR_SMMC_L_CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_REG \ + (CSR_SMMC_L_CSR_BASE + 0x50) /* SMMC_L bank queue's depth register 1 */ +#define CSR_SMMC_L_CSR_SMMC_L_ECC_INJ_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x54) /* SMMC_L ECC inject register */ +#define CSR_SMMC_L_CSR_SMMC_L_PG_CFG_REG (CSR_SMMC_L_CSR_BASE + 0x58) /* SMMC_L Partial Good register */ + +#endif // SM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stffq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stffq_c_union_define.h new file mode 100644 index 000000000..ca04f11b9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stffq_c_union_define.h @@ -0,0 +1,6438 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stffq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:03:30 Create file +// ****************************************************************************** + +#ifndef STFFQ_C_UNION_DEFINE_H +#define STFFQ_C_UNION_DEFINE_H + +/* Define the union csr_fq_mode_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_oeid : 9; /* [8:0] */ + u32 cfg_mode_init_def_fq_tx : 2; /* [10:9] */ + u32 enable_stf : 1; /* [11] */ + u32 cfg_ngsf_mod : 1; /* [12] */ + u32 enable_pro : 1; /* [13] */ + u32 enable_asc : 1; /* [14] */ + u32 cfg_psh_msg_en : 1; /* [15] */ + u32 cfg_base_init_def_fq : 12; /* [27:16] */ + u32 cfg_mode_init_def_fq : 2; /* [29:28] */ + u32 cfg_mode_pn : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mode_reg_u; + +/* Define the union csr_fq_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_start : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_initctab_start_u; + +/* Define the union csr_fq_initctab_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_init_ctab_st_done : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_initctab_st_u; + +/* Define the union csr_fq_init_logic_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_init_logic_st_done : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_init_logic_st_u; + +/* Define the union csr_fq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_3 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_vector_u; + +/* Define the union csr_fq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 16; /* [15:0] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_u; + +/* Define the union csr_fq_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 16; /* [15:0] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_mask_u; + +/* Define the union csr_fq_int_mem_err_2b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_2bit_error : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 mem_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_mem_err_2b_u; + +/* Define the union csr_fq_int_oeid_aged_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oeid_age_err_error_bit : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 oeid_age_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_oeid_aged_err_u; + +/* Define the union csr_fq_int_scan_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 scan_err_error_bit : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 scan_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_scan_err_u; + +/* Define the union csr_fq_int_fcmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcmd_err_error_bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 fcmd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fcmd_err_u; + +/* Define the union csr_fq_int_dsp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsp_err_error_bit : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 dsp_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_dsp_err_u; + +/* Define the union csr_fq_int_pfh_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfh_err_error_bit : 1; /* [0] */ + u32 int_insrt5 : 1; /* [1] */ + u32 pfh_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_pfh_err_u; + +/* Define the union csr_fq_int_dbe_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbe_err_error_bit : 1; /* [0] */ + u32 int_insrt6 : 1; /* [1] */ + u32 dbe_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_dbe_err_u; + +/* Define the union csr_fq_int_qrsc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qrsc_err_error_bit : 1; /* [0] */ + u32 int_insrt7 : 1; /* [1] */ + u32 qrsc_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_qrsc_err_u; + +/* Define the union csr_fq_int_buf_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_uf_error_bit : 1; /* [0] */ + u32 int_insrt8 : 1; /* [1] */ + u32 buf_uf_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_buf_uf_err_u; + +/* Define the union csr_fq_int_fifo0_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_err_error_bit : 1; /* [0] */ + u32 int_insrt9 : 1; /* [1] */ + u32 fifo_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fifo0_err_u; + +/* Define the union csr_fq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_vld : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_ctrl_u; + +/* Define the union csr_fq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stffq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_timeout_u; + +/* Define the union csr_fq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stffq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_dat0_u; + +/* Define the union csr_fq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stffq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_dat1_u; + +/* Define the union csr_fq_qcntx_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wm_lru : 8; /* [7:0] */ + u32 rsv_5 : 4; /* [11:8] */ + u32 cfg_lqp_lru : 1; /* [12] */ + u32 cfg_w2r_byps_en : 1; /* [13] */ + u32 cfg_rcmd_npa_lb_oq_en : 1; /* [14] */ + u32 cfg_rcmd_pa_lb_oq_en : 1; /* [15] */ + u32 cfg_wdog_rfil_period : 8; /* [23:16] */ + u32 cfg_wdog_rfil_en : 1; /* [24] */ + u32 rsv_6 : 6; /* [30:25] */ + u32 cfg_rfl_fastlck_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_qcntx_mode_u; + +/* Define the union csr_fq_age_period_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_age_period : 12; /* [11:0] */ + u32 cfg_age_period_bg : 4; /* [15:12] */ + u32 cfg_fstr_wg : 8; /* [23:16] */ + u32 rsv_7 : 2; /* [25:24] */ + u32 cfg_age_oeid_bg_en : 1; /* [26] */ + u32 cfg_wg_eng_en : 1; /* [27] */ + u32 cfg_age_oeid_en : 1; /* [28] */ + u32 cfg_age2un_en : 1; /* [29] */ + u32 cfg_fq_age_unit : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_age_period_reg_u; + +/* Define the union csr_stffq_dbe_hw_pfh_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_pfh_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stffq_dbe_hw_pfh_cfg_u; + +/* Define the union csr_fq_tmr_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_tmr_defer : 8; /* [7:0] */ + u32 st_tmr_exp : 8; /* [15:8] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_st_u; + +/* Define the union csr_fq_cpb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_adj_attr : 4; /* [3:0] */ + u32 dma_adj_attr_def : 4; /* [7:4] */ + u32 rsv_9 : 4; /* [11:8] */ + u32 otsd_psh_plen : 3; /* [14:12] */ + u32 rsv_10 : 1; /* [15] */ + u32 psh_plen_en : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cpb_cfg_u; + +/* Define the union csr_fq_crdt_2tlsmf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_crdt_cmd_smf : 4; /* [3:0] */ + u32 rsv_11 : 4; /* [7:4] */ + u32 cnt_crdt_dat_smf : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 cnt_crdt_tl0 : 4; /* [19:16] */ + u32 rsv_13 : 4; /* [23:20] */ + u32 cnt_crdt_tl1 : 5; /* [28:24] */ + u32 rsv_14 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_crdt_2tlsmf_st_u; + +/* Define the union csr_fq_crdt_2tlsmf_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_def_crdt_cmd_smf : 4; /* [3:0] */ + u32 cfg_def_crdt_dat_smf : 5; /* [8:4] */ + u32 rsv_15 : 3; /* [11:9] */ + u32 cfg_def_crdt_tl0_rsp : 4; /* [15:12] */ + u32 cfg_def_crdt_tl1_rsp : 4; /* [19:16] */ + u32 cfg_def_crdt_tmrs : 7; /* [26:20] */ + u32 rsv_16 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_crdt_2tlsmf_reg_u; + +/* Define the union csr_fq_cnt_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_17 : 18; /* [17:0] */ + u32 mon_sel_idx : 6; /* [23:18] */ + u32 cfg_cnt6_en : 1; /* [24] */ + u32 cfg_flit_cnt_en : 1; /* [25] */ + u32 cfg_cnt_en : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl_u; + +/* Define the union csr_fq_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt0_u; + +/* Define the union csr_fq_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt1_u; + +/* Define the union csr_fq_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt2_u; + +/* Define the union csr_fq_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt3_u; + +/* Define the union csr_fq_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt4_u; + +/* Define the union csr_fq_snapshot_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_snapsot_srv_typ : 4; /* [3:0] */ + u32 cfg_snapsot_src : 9; /* [12:4] */ + u32 cfg_snapsot_req_typ : 2; /* [14:13] */ + u32 cfg_snapsot_fqid : 12; /* [26:15] */ + u32 cfg_snapshot_filt_typ_en : 4; /* [30:27] */ + u32 cfg_snapshot_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_snapshot_ctl_u; + +/* Define the union csr_fq_snapshot_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_asc_latency : 8; /* [7:0] */ + u32 max_latency_stg : 8; /* [15:8] */ + u32 total_latency : 8; /* [23:16] */ + u32 rsv_18 : 7; /* [30:24] */ + u32 snapshot_done : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_snapshot_st_u; + +/* Define the union csr_fq_dbe_hw_wqe_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en_u; + +/* Define the union csr_fq_dbe_hw_wqe_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stagh_wqe_ld : 5; /* [4:0] */ + u32 cfg_opid_wqe_ld : 5; /* [9:5] */ + u32 cfg_aext_wqe_ld : 3; /* [12:10] */ + u32 cfg_ftid_wqe_ld : 6; /* [18:13] */ + u32 cfg_aext_ord : 3; /* [21:19] */ + u32 cfg_txpfl_qp_push : 3; /* [24:22] */ + u32 cfg_rxpfl_qp_push : 3; /* [27:25] */ + u32 cfg_otsd_qp_push : 3; /* [30:28] */ + u32 rsv_19 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_cfg_u; + +/* Define the union csr_fq_fifo_gap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gap_fifo_rsp2tl : 7; /* [6:0] */ + u32 rsv_20 : 1; /* [7] */ + u32 gap_cmds_fifos : 4; /* [11:8] */ + u32 gap_fifo_p2t_cmd : 5; /* [16:12] */ + u32 rsv_21 : 3; /* [19:17] */ + u32 gap_afifo_cpback : 5; /* [24:20] */ + u32 gap_bnd_oeid : 3; /* [27:25] */ + u32 gap_afifo_icc_rsp : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_fifo_gap_cfg_u; + +/* Define the union csr_fq_his_fifo_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 p2e_f : 4; /* [3:0] */ + u32 p2e_rbnd : 4; /* [7:4] */ + u32 p2e_ulck : 4; /* [11:8] */ + u32 rlck_pcm : 4; /* [15:12] */ + u32 cpback : 8; /* [23:16] */ + u32 icc_rsp : 4; /* [27:24] */ + u32 rlck : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_his_fifo_cnt0_u; + +/* Define the union csr_fq_his_fifo_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 empty_tpfh : 1; /* [0] */ + u32 empty_spqc : 1; /* [1] */ + u32 empty_rqpc : 1; /* [2] */ + u32 empty_ism : 1; /* [3] */ + u32 empty_tpcl : 1; /* [4] */ + u32 empty_tcm : 1; /* [5] */ + u32 rsv_22 : 2; /* [7:6] */ + u32 tl0_req : 6; /* [13:8] */ + u32 tl1_req : 6; /* [19:14] */ + u32 tl2p_cmds : 4; /* [23:20] */ + u32 tl2p_rfl : 4; /* [27:24] */ + u32 p2tl_cmds : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_his_fifo_cnt1_u; + +/* Define the union csr_fq_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 afull_tl0_rsp : 1; /* [0] */ + u32 afull_tl1_rsp : 1; /* [1] */ + u32 afull_tl0_req : 1; /* [2] */ + u32 afull_tl1_req : 1; /* [3] */ + u32 afull_tl2p_cmds : 1; /* [4] */ + u32 afull_tl2p_rfl : 1; /* [5] */ + u32 afull_p2tl_cmds : 1; /* [6] */ + u32 afull_p2e_f : 1; /* [7] */ + u32 afull_p2e_rbnd : 1; /* [8] */ + u32 afull_p2e_ulck : 1; /* [9] */ + u32 afull_rlck_pcm : 1; /* [10] */ + u32 afull_cpback : 1; /* [11] */ + u32 afull_icc_rsp : 1; /* [12] */ + u32 afull_bnd : 1; /* [13] */ + u32 empty_tl0_0dat : 1; /* [14] */ + u32 empty_tl0_idat : 1; /* [15] */ + u32 empty_tl1_0dat : 1; /* [16] */ + u32 empty_tl1_idat : 1; /* [17] */ + u32 empty_tl0_rsp : 1; /* [18] */ + u32 empty_tl1_rsp : 1; /* [19] */ + u32 empty_tl0_req : 1; /* [20] */ + u32 empty_tl1_req : 1; /* [21] */ + u32 empty_tl2p_cmds : 1; /* [22] */ + u32 empty_tl2p_rfl : 1; /* [23] */ + u32 empty_p2tl_cmds : 1; /* [24] */ + u32 empty_p2e_f : 1; /* [25] */ + u32 empty_p2e_rbnd : 1; /* [26] */ + u32 empty_p2e_ulck : 1; /* [27] */ + u32 empty_rlck_pcm : 1; /* [28] */ + u32 empty_cpback : 1; /* [29] */ + u32 empty_icc_rsp : 1; /* [30] */ + u32 empty_bnd : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_fifo_st_u; + +/* Define the union csr_fq_his_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 his_ful_tl0_rsp : 1; /* [0] */ + u32 his_ful_tl1_rsp : 1; /* [1] */ + u32 his_ful_tl0_req : 1; /* [2] */ + u32 his_ful_tl1_req : 1; /* [3] */ + u32 his_ful_fifo_tl2p_cmds : 1; /* [4] */ + u32 his_ful_fifo_tl2p_rfl : 1; /* [5] */ + u32 his_ful_fifo_p2tl_cmds : 1; /* [6] */ + u32 his_ful_fifo_p2e_f : 1; /* [7] */ + u32 his_ful_fifo_p2e_rbnd : 1; /* [8] */ + u32 his_ful_fifo_p2e_ulck : 1; /* [9] */ + u32 his_ful_fifo_rlck_pcm : 1; /* [10] */ + u32 his_ful_afifo_cpback : 1; /* [11] */ + u32 his_ful_afifo_icc_rsp : 1; /* [12] */ + u32 his_ful_afifo_bnd : 1; /* [13] */ + u32 his_ful_tl0_idat : 1; /* [14] */ + u32 his_ful_tl0_odat : 1; /* [15] */ + u32 his_ful_tl1_idat : 1; /* [16] */ + u32 his_ful_tl1_odat : 1; /* [17] */ + u32 his_ful_ism_dat : 1; /* [18] */ + u32 his_ful_sqpc : 1; /* [19] */ + u32 his_ful_rqpc : 1; /* [20] */ + u32 his_ful_tpfh : 1; /* [21] */ + u32 his_ful_tpcl : 1; /* [22] */ + u32 his_ful_tcm : 1; /* [23] */ + u32 rsv_23 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_his_fifo_st_u; + +/* Define the union csr_fq_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_power_ctrl_sp : 3; /* [2:0] */ + u32 rsv_24 : 1; /* [3] */ + u32 mem_timing_ctrl_sp : 8; /* [11:4] */ + u32 mem_power_ctrl_tp : 3; /* [14:12] */ + u32 rsv_25 : 1; /* [15] */ + u32 mem_timing_ctrl_tp : 8; /* [23:16] */ + u32 rsv_26 : 4; /* [27:24] */ + u32 err_req : 2; /* [29:28] */ + u32 indirect_mem_ecc_en : 1; /* [30] */ + u32 mem_ecc_bypass : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mem_ctrl_u; + +/* Define the union csr_fq_cfg_ep2host_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_map_ep2host : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_ep2host_u; + +/* Define the union csr_fq_pcar_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcar_sh : 20; /* [19:0] */ + u32 cfg_pcar_sml : 1; /* [20] */ + u32 cfg_pcar_opid : 5; /* [25:21] */ + u32 cfg_pcar_inst : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_pcar_cfg_u; + +/* Define the union csr_fq_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt5_u; + +/* Define the union csr_fq_mod_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 base_sub_pro_typ : 4; /* [3:0] */ + u32 max_sub_pro_typ : 4; /* [7:4] */ + u32 cfg_pro_typ_nret_pkt : 4; /* [11:8] */ + u32 cfg_pro_typ_lb : 4; /* [15:12] */ + u32 cfg_th_fc_on : 8; /* [23:16] */ + u32 cfg_th_fc_dif : 4; /* [27:24] */ + u32 cfg_th_fc_mode : 2; /* [29:28] */ + u32 cfg_dsp_fstr_cup_en : 1; /* [30] */ + u32 cfg_dsp_fastlck_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mod_reg1_u; + +/* Define the union csr_fq_inner_bp_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_27 : 3; /* [2:0] */ + u32 tmr_stf_bp : 1; /* [3] */ + u32 tmr_stl_bp : 1; /* [4] */ + u32 pro2cmd_bp : 1; /* [5] */ + u32 t2cup_bp : 1; /* [6] */ + u32 fcam_pfh_bp : 1; /* [7] */ + u32 fq2smf_bp : 1; /* [8] */ + u32 smf2fq_dat_bp : 1; /* [9] */ + u32 smf2fq_cmd_bp : 1; /* [10] */ + u32 rsc_qidx_bp : 1; /* [11] */ + u32 rsc_fqg_bp : 1; /* [12] */ + u32 rsc_lqp_bp : 1; /* [13] */ + u32 t2fsg_rls_bp : 1; /* [14] */ + u32 t2fsg_bp : 1; /* [15] */ + u32 t2rfl_bp : 1; /* [16] */ + u32 t2pfh_bp : 1; /* [17] */ + u32 rstg1_bp : 1; /* [18] */ + u32 rstg0_bp : 1; /* [19] */ + u32 fq2tl1_req_bp : 1; /* [20] */ + u32 tl02fq_req_bp : 1; /* [21] */ + u32 fq2tl1_rsp_bp : 1; /* [22] */ + u32 fq2tl0_rsp_bp : 1; /* [23] */ + u32 fq2pdm_dcc_bp : 1; /* [24] */ + u32 fq2pdm_icc_bp : 1; /* [25] */ + u32 ritf_tcm_bp : 1; /* [26] */ + u32 ritf_ord_bp : 1; /* [27] */ + u32 fq_psh_msg_bp : 1; /* [28] */ + u32 fq2iq_lb_bp : 1; /* [29] */ + u32 fq2oq_dsp_bp : 1; /* [30] */ + u32 fq2iq_bnd_bp : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_bp_st_u; + +/* Define the union csr_fq_inner_mon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st_u; + +/* Define the union csr_fq_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt6_u; + +/* Define the union csr_fq_cnt_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fa_cnt1_reserved : 4; /* [3:0] */ + u32 cfg_typ_cnt9 : 2; /* [5:4] */ + u32 rsv_28 : 16; /* [21:6] */ + u32 cfg_cnt_1_en : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl1_u; + +/* Define the union csr_fq_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt7_u; + +/* Define the union csr_fq_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt8_u; + +/* Define the union csr_fq_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt9_u; + +/* Define the union csr_fq_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt10_u; + +/* Define the union csr_fq_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt11_u; + +/* Define the union csr_fq_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt12_u; + +/* Define the union csr_fq_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt13_u; + +/* Define the union csr_fq_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt14_u; + +/* Define the union csr_fq_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt15_u; + +/* Define the union csr_fq_cnt16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt16_u; + +/* Define the union csr_fq_int_mem_err_1b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_err_1b_error_bit : 1; /* [0] */ + u32 int_insrt10 : 1; /* [1] */ + u32 mem_err_1b_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_mem_err_1b_u; + +/* Define the union csr_cfg_styp_th_fc_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_styp_th_fc_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_styp_th_fc_en_u; + +/* Define the union csr_cfg_zero_esch_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_zero_esch_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_zero_esch_len_u; + +/* Define the union csr_cfg_fq_bubble_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_bubble_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_fq_bubble_ctl_u; + +/* Define the union csr_cfg_l2dcache_bubble_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_l2dcache_bubble_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_l2dcache_bubble_ctl_u; + +/* Define the union csr_fq_def_fq_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_tx_base_init_def_fq : 12; /* [11:0] */ + u32 cfg_tx_mode_init_def_fq : 2; /* [13:12] */ + u32 reserved2 : 2; /* [15:14] */ + u32 cfg_rx_base_init_def_fq : 12; /* [27:16] */ + u32 cfg_rx_mode_init_def_fq : 2; /* [29:28] */ + u32 reserved1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_def_fq_ctl_u; + +/* Define the union csr_fq_smf_ldbctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_smf_ldb_ctl_vfen : 1; /* [0] */ + u32 fq_smf_ldb_ctl_ofst : 5; /* [5:1] */ + u32 fq_tmr_pro_typ_ctl : 14; /* [19:6] */ + u32 fq_smf_only1_ctl : 1; /* [20] */ + u32 fq_smf_lbctl_reserved1 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_smf_ldbctl_u; + +/* Define the union csr_fq_cfg_ep2host_h2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_map_ep2host_h2 : 16; /* [15:0] */ + u32 cfg_map_ep2host_rsvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_ep2host_h2_u; + +/* Define the union csr_fq_cfg_prefetch_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_pfhctl_coco_xid20 : 1; /* [0] */ + u32 fq_base_sub_pro_typ : 7; /* [7:1] */ + u32 fq_max_sub_pro_typ : 7; /* [14:8] */ + u32 fq_cfg_pro_typ_nret_pkt : 7; /* [21:15] */ + u32 fq_cfg_pro_typ_lb : 7; /* [28:22] */ + u32 fq_cfg_pro_typ_lb_org : 1; /* [29] */ + u32 fq_cfg_pro_typ_nret_org : 1; /* [30] */ + u32 fq_cfg_prefetch_ctl_rsvd : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_prefetch_ctl_u; + +/* Define the union csr_fq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_fq_sample_mode : 1; /* [0] */ + u32 csr_fq_spec_port_en : 1; /* [1] */ + u32 csr_fq_done_clr : 1; /* [2] */ + u32 rsv_29 : 1; /* [3] */ + u32 csr_fq_spec_port_num : 4; /* [7:4] */ + u32 csr_fq_spec_pptr_typ : 8; /* [15:8] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_latency_cfg_u; + +/* Define the union csr_fq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_csr_sample_done : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_latency_sta_u; + +/* Define the union csr_fq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_sample_tmr_u; + +/* Define the union csr_fq_cfg_fake_vf_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_fake_vfid_pf_rsvd2 : 16; /* [15:0] */ + u32 fq_fake_vfid_pf_start_bit : 4; /* [19:16] */ + u32 fq_fake_vfid_pf_end_bit : 4; /* [23:20] */ + u32 fq_fake_vfid_pf_rsvd1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_fake_vf_ctl_u; + +/* Define the union csr_fq_cfg_bps_dly_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_bps_dly_dbld : 1; /* [0] */ + u32 fq_cfg_bps_dly_fsg : 1; /* [1] */ + u32 fq_cfg_bpsfsg_oeid_th : 11; /* [12:2] */ + u32 fq_cfg_bps_dly_rsvd : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_bps_dly_ctl_u; + +/* Define the union csr_fq_cfg_otsd_base_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_otsd_base_ctl_val : 4; /* [3:0] */ + u32 fq_cfg_otsd_base_ctl_rsvd : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_otsd_base_ctl_u; + +/* Define the union csr_fq_cnt_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_32 : 22; /* [21:0] */ + u32 cfg_cnt_2_en : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl2_u; + +/* Define the union csr_fq_cnt17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt17_u; + +/* Define the union csr_fq_cnt18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt18_u; + +/* Define the union csr_fq_cnt19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt19_u; + +/* Define the union csr_fq_cnt20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt20_u; + +/* Define the union csr_fq_cnt21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt21_u; + +/* Define the union csr_fq_cnt22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt22_u; + +/* Define the union csr_fq_cnt23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt23_u; + +/* Define the union csr_fq_cnt24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt24_u; + +/* Define the union csr_fq_cnt25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt25_u; + +/* Define the union csr_fq_cnt26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt26_u; + +/* Define the union csr_fq_cnt_ctl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 22; /* [21:0] */ + u32 cfg_cnt_3_en : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl3_u; + +/* Define the union csr_fq_cnt27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt27_u; + +/* Define the union csr_fq_cnt28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt28_u; + +/* Define the union csr_fq_cnt29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt29_u; + +/* Define the union csr_fq_cnt30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt30_u; + +/* Define the union csr_fq_cnt31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt31_u; + +/* Define the union csr_fq_cnt32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt32_u; + +/* Define the union csr_fq_cnt33_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt33 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt33_u; + +/* Define the union csr_fq_cnt34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt34 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt34_u; + +/* Define the union csr_fq_cnt35_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt35 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt35_u; + +/* Define the union csr_fq_cnt36_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt36 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt36_u; + +/* Define the union csr_fq_cnt_ctl4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_34 : 21; /* [20:0] */ + u32 cfg_cnt_4_en : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl4_u; + +/* Define the union csr_fq_cnt37_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt37 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt37_u; + +/* Define the union csr_fq_cnt38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt38 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt38_u; + +/* Define the union csr_fq_cnt39_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt39 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt39_u; + +/* Define the union csr_fq_cnt40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt40_u; + +/* Define the union csr_fq_cnt41_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt41 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt41_u; + +/* Define the union csr_fq_cnt42_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt42 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt42_u; + +/* Define the union csr_fq_cnt43_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt43 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt43_u; + +/* Define the union csr_fq_cnt44_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt44 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt44_u; + +/* Define the union csr_fq_cnt45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt45 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt45_u; + +/* Define the union csr_fq_cnt46_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt46 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt46_u; + +/* Define the union csr_fq_qu2smf_tmr_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_qu2smf_tmr_dly_val : 31; /* [30:0] */ + u32 fq_qu2smf_tmr_dly_op : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_qu2smf_tmr_dly_u; + +/* Define the union csr_fq_magic_box_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_mgbx_quf_pg : 2; /* [1:0] */ + u32 fq_mgbx_smf_pg : 4; /* [5:2] */ + u32 fq_mgbx_lbf_mode : 2; /* [7:6] */ + u32 rsv_35 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_magic_box_ctl_u; + +/* Define the union csr_fq_mgbx_srv2hash_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_mgbx_srv2hash : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mgbx_srv2hash_u; + +/* Define the union csr_fq_inner_mon_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st1_u; + +/* Define the union csr_fq_inner_mon_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st2_u; + +/* Define the union csr_fq_inner_mon_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st3_u; + +/* Define the union csr_fq_inner_mon_st4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st4_u; + +/* Define the union csr_fq_inner_mon_st5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st5_u; + +/* Define the union csr_fq_inner_mon_st6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st6_u; + +/* Define the union csr_fq_inner_mon_st7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st7_u; + +/* Define the union csr_fq_inner_mon_st8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st8_u; + +/* Define the union csr_fq_inner_mon_st9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st9_u; + +/* Define the union csr_fq_inner_mon_st10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st10_u; + +/* Define the union csr_fq_inner_mon_st11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st11_u; + +/* Define the union csr_fq_inner_mon_st12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st12_u; + +/* Define the union csr_fq_inner_mon_st13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st13_u; + +/* Define the union csr_fq_inner_mon_st14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st14_u; + +/* Define the union csr_fq_inner_mon_st15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st15_u; + +/* Define the union csr_fq_inner_mon_st16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st16_u; + +/* Define the union csr_fq_inner_mon_st17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st17_u; + +/* Define the union csr_fq_inner_mon_st18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st18_u; + +/* Define the union csr_fq_inner_mon_st19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st19_u; + +/* Define the union csr_fq_inner_mon_st20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st20_u; + +/* Define the union csr_fq_inner_mon_st21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st21_u; + +/* Define the union csr_fq_inner_mon_st22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st22_u; + +/* Define the union csr_fq_inner_mon_st23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st23_u; + +/* Define the union csr_fq_inner_mon_st24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st24_u; + +/* Define the union csr_fq_inner_mon_st25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st25_u; + +/* Define the union csr_fq_inner_mon_st26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st26_u; + +/* Define the union csr_fq_inner_mon_st27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st27_u; + +/* Define the union csr_fq_inner_mon_st28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st28_u; + +/* Define the union csr_fq_inner_mon_st29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st29_u; + +/* Define the union csr_fq_inner_mon_st30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st30_u; + +/* Define the union csr_fq_inner_mon_st31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st31_u; + +/* Define the union csr_fq_inner_mon_st32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st32_u; + +/* Define the union csr_fq_inner_mon_st33_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st33 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st33_u; + +/* Define the union csr_fq_inner_mon_st34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st34 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st34_u; + +/* Define the union csr_fq_inner_mon_st35_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st35 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st35_u; + +/* Define the union csr_fq_inner_mon_st36_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st36 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st36_u; + +/* Define the union csr_fq_inner_mon_st37_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st37 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st37_u; + +/* Define the union csr_fq_inner_mon_st38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st38 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st38_u; + +/* Define the union csr_fq_inner_mon_st39_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st39 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st39_u; + +/* Define the union csr_fq_inner_mon_st40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st40_u; + +/* Define the union csr_fq_inner_mon_st41_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st41 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st41_u; + +/* Define the union csr_fq_inner_mon_st42_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st42 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st42_u; + +/* Define the union csr_fq_inner_mon_st43_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st43 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st43_u; + +/* Define the union csr_fq_inner_mon_st44_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st44 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st44_u; + +/* Define the union csr_fq_inner_mon_st45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st45 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st45_u; + +/* Define the union csr_fq_inner_mon_st46_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st46 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st46_u; + +/* Define the union csr_fq_inner_mon_st47_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st47_u; + +/* Define the union csr_fq_inner_mon_st48_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st48 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st48_u; + +/* Define the union csr_fq_cnt47_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt47_u; + +/* Define the union csr_fq_rou_rqst_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_rqst_fifo_st0 : 16; /* [15:0] */ + u32 rou_rqst_i_ae_th0 : 8; /* [23:16] */ + u32 rou_rqst_i_af_th0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_rqst_fifo0_u; + +/* Define the union csr_fq_rou_rsp_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_rsp_fifo_st0 : 16; /* [15:0] */ + u32 rou_rsp_i_ae_th0 : 8; /* [23:16] */ + u32 rou_rsp_i_af_th0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_rsp_fifo0_u; + +/* Define the union csr_fq_rou_rsp_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_rsp_fifo_st1 : 16; /* [15:0] */ + u32 rou_rsp_i_ae_th1 : 8; /* [23:16] */ + u32 rou_rsp_i_af_th1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_rsp_fifo1_u; + +/* Define the union csr_fq_rou_tmrodr_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst0_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst0_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst0_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo0_u; + +/* Define the union csr_fq_rou_tmrodr_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst1_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst1_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst1_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo1_u; + +/* Define the union csr_fq_rou_tmrodr_fifo2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst2_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst2_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst2_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo2_u; + +/* Define the union csr_fq_rou_tmrodr_fifo3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst3_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst3_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst3_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo3_u; + +/* Define the union csr_fq_rin_rqst_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rin_rqst_fifo_st : 16; /* [15:0] */ + u32 rin_rqst_i_ae_th : 8; /* [23:16] */ + u32 rin_rqst_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rin_rqst_fifo_u; + +/* Define the union csr_fq_rin_rsp_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rin_rsp_fifo_st : 16; /* [15:0] */ + u32 rin_rsp_i_ae_th : 8; /* [23:16] */ + u32 rin_rsp_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rin_rsp_fifo_u; + +/* Define the union csr_fq_smf_rsp_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rsp0_fifo_st : 16; /* [15:0] */ + u32 smf_rsp0_i_ae_th : 8; /* [23:16] */ + u32 smf_rsp0_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_smf_rsp_fifo0_u; + +/* Define the union csr_fq_smf_rsp_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rsp1_fifo_st : 16; /* [15:0] */ + u32 smf_rsp1_i_ae_th : 8; /* [23:16] */ + u32 smf_rsp1_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_smf_rsp_fifo1_u; + +/* Define the union csr_fq_tl0_cmd_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl0_cmd_fifo_st : 16; /* [15:0] */ + u32 tl0_cmd_i_ae_th : 8; /* [23:16] */ + u32 tl0_cmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl0_cmd_fifo0_u; + +/* Define the union csr_fq_tl0_extcmd_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl0_extcmd_fifo_st : 16; /* [15:0] */ + u32 tl0_extcmd_i_ae_th : 8; /* [23:16] */ + u32 tl0_extcmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl0_extcmd_fifo0_u; + +/* Define the union csr_fq_tl1_cmd_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl1_cmd_fifo_st : 16; /* [15:0] */ + u32 tl1_cmd_i_ae_th : 8; /* [23:16] */ + u32 tl1_cmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl1_cmd_fifo1_u; + +/* Define the union csr_fq_tl1_extcmd_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl1_extcmd_fifo_st : 16; /* [15:0] */ + u32 tl1_extcmd_i_ae_th : 8; /* [23:16] */ + u32 tl1_extcmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl1_extcmd_fifo0_u; + +/* Define the union csr_fq_fq2oq_fcnp_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq2oq_fcnp_fifo_st : 16; /* [15:0] */ + u32 fq2oq_fcnp_i_ae_th : 8; /* [23:16] */ + u32 fq2oq_fcnp_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_fq2oq_fcnp_fifo_u; + +/* Define the union csr_fq_oq2fq_fcnp_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq2fq_fcnp_fifo_st : 16; /* [15:0] */ + u32 oq2fq_fcnp_i_ae_th : 8; /* [23:16] */ + u32 oq2fq_fcnp_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_oq2fq_fcnp_fifo_u; + +/* Define the union csr_fq_tmr_rsp_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp0_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp0_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp0_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo0_u; + +/* Define the union csr_fq_tmr_rsp_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp1_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp1_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp1_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo1_u; + +/* Define the union csr_fq_tmr_rsp_fifo2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp2_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp2_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp2_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo2_u; + +/* Define the union csr_fq_tmr_rsp_fifo3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp3_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp3_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp3_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo3_u; + +/* Define the union csr_fq_tmr_rsp_fifo4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp4_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp4_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp4_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo4_u; + +/* Define the union csr_fq_tmr_rsp_fifo5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp5_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp5_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp5_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo5_u; + +/* Define the union csr_fq_tmr_rsp_fifo6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp6_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp6_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp6_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo6_u; + +/* Define the union csr_fq_tmr_rsp_fifo7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp7_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp7_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp7_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo7_u; + +/* Define the union csr_fq_tmr_rsp_fifo8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp8_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp8_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp8_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo8_u; + +/* Define the union csr_fq_tmr_rsp_fifo9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp9_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp9_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp9_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo9_u; + +/* Define the union csr_fq_tmr_rsp_fifo10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp10_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp10_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp10_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo10_u; + +/* Define the union csr_fq_tmr_rsp_fifo11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp11_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp11_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp11_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo11_u; + +/* Define the union csr_fq_tmr_rsp_fifo12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp12_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp12_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp12_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo12_u; + +/* Define the union csr_fq_tmr_rsp_fifo13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp13_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp13_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp13_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo13_u; + +/* Define the union csr_fq_tmr_rsp_fifo14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp14_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp14_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp14_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo14_u; + +/* Define the union csr_fq_tmr_rsp_fifo15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp15_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp15_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp15_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo15_u; + +/* Define the union csr_fq_int_rin_rqst_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_rin_rqst_err : 1; /* [0] */ + u32 int_insrt11 : 1; /* [1] */ + u32 fq_rin_rqst_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_rin_rqst_err_u; + +/* Define the union csr_fq_int_rin_rsp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_rin_rsp_err : 1; /* [0] */ + u32 int_insrt12 : 1; /* [1] */ + u32 fq_rin_rsp_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_rin_rsp_err_u; + +/* Define the union csr_fq_int_rin_trsp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_rin_trsp_err : 1; /* [0] */ + u32 int_insrt13 : 1; /* [1] */ + u32 fq_rin_trsp_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_rin_trsp_err_u; + +/* Define the union csr_fq_int_fifo1_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_fifo1_err : 1; /* [0] */ + u32 int_insrt14 : 1; /* [1] */ + u32 fq_fifo1_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fifo1_err_u; + +/* Define the union csr_fq_int_fifo2_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_fifo2_err : 1; /* [0] */ + u32 int_insrt15 : 1; /* [1] */ + u32 fq_fifo2_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fifo2_err_u; + +/* Define the union csr_fq_cnt48_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt48 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt48_u; + +/* Define the union csr_fq_cfg_stg_qp_push0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_stg_qp_push0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_stg_qp_push0_u; + +/* Define the union csr_fq_cfg_stg_qp_push1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_stg_qp_push1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_stg_qp_push1_u; + +/* Define the union csr_fq_cfg_stg_qp_push2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_stg_qp_push2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_stg_qp_push2_u; + +/* Define the union csr_fq_dbe_hw_wqe_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en1_u; + +/* Define the union csr_fq_dbe_hw_wqe_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en2_u; + +/* Define the union csr_fq_dbe_hw_wqe_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en3_u; + +/* Define the union csr_fq_dbe_hw_wqe_en4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en4_u; + +/* Define the union csr_fq_dbe_hw_wqe_en5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en5_u; + +/* Define the union csr_fq_dbe_hw_wqe_en6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en6_u; + +/* Define the union csr_fq_dbe_hw_wqe_en7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en7_u; + +/* Define the union csr_fq_dbe_hw_wqe_en8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en8_u; + +/* Define the union csr_fq_dbe_hw_wqe_en9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en9_u; + +/* Define the union csr_fq_dbe_hw_wqe_en10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en10_u; + +/* Define the union csr_fq_dbe_hw_wqe_en11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en11_u; + +/* Define the union csr_fq_dbe_hw_wqe_en12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en12_u; + +/* Define the union csr_fq_dbe_hw_wqe_en13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en13_u; + +/* Define the union csr_fq_dbe_hw_wqe_en14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en14_u; + +/* Define the union csr_fq_dbe_hw_wqe_en15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en15_u; + +/* Define the union csr_fq_cnt49_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt49 : 24; /* [23:0] */ + u32 rsv_36 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt49_u; + +/* Define the union csr_fq_cnt50_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt50 : 24; /* [23:0] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt50_u; + +/* Define the union csr_fq_cnt51_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt51 : 24; /* [23:0] */ + u32 rsv_38 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt51_u; + +/* Define the union csr_fq_cnt52_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt52 : 24; /* [23:0] */ + u32 rsv_39 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt52_u; + +/* Define the union csr_fq_cnt53_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt53 : 24; /* [23:0] */ + u32 rsv_40 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt53_u; + +/* Define the union csr_fq_cnt54_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt54 : 24; /* [23:0] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt54_u; + +/* Define the union csr_fq_cnt55_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt55 : 24; /* [23:0] */ + u32 rsv_42 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt55_u; + +/* Define the union csr_fq_cnt56_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt56 : 24; /* [23:0] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt56_u; + +/* Define the union csr_fq_cnt57_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt57 : 24; /* [23:0] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt57_u; + +/* Define the union csr_fq_cnt58_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt58 : 24; /* [23:0] */ + u32 rsv_45 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt58_u; + +/* Define the union csr_fq_cnt59_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt59 : 24; /* [23:0] */ + u32 rsv_46 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt59_u; + +/* Define the union csr_fq_cnt60_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt60 : 24; /* [23:0] */ + u32 rsv_47 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt60_u; + +/* Define the union csr_fq_cnt61_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt61 : 24; /* [23:0] */ + u32 rsv_48 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt61_u; + +/* Define the union csr_fq_cnt62_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt62 : 24; /* [23:0] */ + u32 rsv_49 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt62_u; + +/* Define the union csr_fq_cnt63_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt63 : 24; /* [23:0] */ + u32 rsv_50 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt63_u; + +/* Define the union csr_fq_cnt64_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt64 : 24; /* [23:0] */ + u32 rsv_51 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt64_u; + +/* Define the union csr_fq_cnt65_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt65 : 24; /* [23:0] */ + u32 rsv_52 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt65_u; + +/* Define the union csr_fq_cnt66_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt66 : 24; /* [23:0] */ + u32 rsv_53 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt66_u; + +/* Define the union csr_fq_cnt67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt67 : 24; /* [23:0] */ + u32 rsv_54 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt67_u; + +/* Define the union csr_fq_cnt68_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt68 : 24; /* [23:0] */ + u32 rsv_55 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt68_u; + +/* Define the union csr_fq_cnt69_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt69 : 24; /* [23:0] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt69_u; + +/* Define the union csr_fq_cnt70_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt70 : 24; /* [23:0] */ + u32 rsv_57 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt70_u; + +/* Define the union csr_fq_cnt71_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt71 : 24; /* [23:0] */ + u32 rsv_58 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt71_u; + +/* Define the union csr_fq_cnt72_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt72 : 24; /* [23:0] */ + u32 rsv_59 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt72_u; + +/* Define the union csr_fq_cnt73_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt73 : 24; /* [23:0] */ + u32 rsv_60 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt73_u; + +/* Define the union csr_fq_cnt74_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt74 : 24; /* [23:0] */ + u32 rsv_61 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt74_u; + +/* Define the union csr_fq_cnt75_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt75 : 24; /* [23:0] */ + u32 rsv_62 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt75_u; + +/* Define the union csr_fq_cnt76_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt76 : 24; /* [23:0] */ + u32 rsv_63 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt76_u; + +/* Define the union csr_fq_cnt77_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt77 : 24; /* [23:0] */ + u32 rsv_64 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt77_u; + +/* Define the union csr_fq_cnt78_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt78 : 24; /* [23:0] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt78_u; + +/* Define the union csr_fq_cnt79_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt79 : 24; /* [23:0] */ + u32 rsv_66 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt79_u; + +/* Define the union csr_fq_cnt80_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt80 : 24; /* [23:0] */ + u32 rsv_67 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt80_u; + +/* Define the union csr_fq_cnt81_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt81 : 24; /* [23:0] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt81_u; + +/* Define the union csr_fq_cnt82_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt82 : 24; /* [23:0] */ + u32 rsv_69 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt82_u; + +/* Define the union csr_fq_cnt83_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt83 : 24; /* [23:0] */ + u32 rsv_70 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt83_u; + +/* Define the union csr_fq_cnt84_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt84 : 24; /* [23:0] */ + u32 rsv_71 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt84_u; + +/* Define the union csr_fq_cnt85_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt85 : 24; /* [23:0] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt85_u; + +/* Define the union csr_fq_cnt86_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt86 : 24; /* [23:0] */ + u32 rsv_73 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt86_u; + +/* Define the union csr_fq_cnt87_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt87 : 24; /* [23:0] */ + u32 rsv_74 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt87_u; + +/* Define the union csr_fq_cnt88_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt88 : 24; /* [23:0] */ + u32 rsv_75 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt88_u; + +/* Define the union csr_fq_cnt89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt89 : 24; /* [23:0] */ + u32 rsv_76 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt89_u; + +/* Define the union csr_fq_cnt90_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt90 : 24; /* [23:0] */ + u32 rsv_77 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt90_u; + +/* Define the union csr_fq_cnt91_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt91 : 24; /* [23:0] */ + u32 rsv_78 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt91_u; + +/* Define the union csr_fq_cnt92_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt92 : 24; /* [23:0] */ + u32 rsv_79 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt92_u; + +/* Define the union csr_fq_cnt93_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt93 : 24; /* [23:0] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt93_u; + +/* Define the union csr_fq_cnt94_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt94 : 24; /* [23:0] */ + u32 rsv_81 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt94_u; + +/* Define the union csr_fq_cnt95_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt95 : 24; /* [23:0] */ + u32 rsv_82 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt95_u; + +/* Define the union csr_fq_cnt96_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt96 : 24; /* [23:0] */ + u32 rsv_83 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt96_u; + +/* Define the union csr_fq_cnt97_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt97 : 24; /* [23:0] */ + u32 rsv_84 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt97_u; + +/* Define the union csr_fq_cnt98_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt98 : 24; /* [23:0] */ + u32 rsv_85 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt98_u; + +/* Define the union csr_fq_cnt99_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt99 : 24; /* [23:0] */ + u32 rsv_86 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt99_u; + +/* Define the union csr_fq_cnt100_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt100 : 24; /* [23:0] */ + u32 rsv_87 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt100_u; + +/* Define the union csr_fq_cnt101_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt101 : 24; /* [23:0] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt101_u; + +/* Define the union csr_fq_cnt102_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt102 : 24; /* [23:0] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt102_u; + +/* Define the union csr_fq_cnt103_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt103 : 24; /* [23:0] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt103_u; + +/* Define the union csr_fq_cnt104_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt104 : 24; /* [23:0] */ + u32 rsv_91 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt104_u; + +/* Define the union csr_fq_cnt105_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt105 : 24; /* [23:0] */ + u32 rsv_92 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt105_u; + +/* Define the union csr_fq_cnt106_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt106 : 24; /* [23:0] */ + u32 rsv_93 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt106_u; + +/* Define the union csr_fq_cnt107_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt107 : 24; /* [23:0] */ + u32 rsv_94 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt107_u; + +/* Define the union csr_fq_cnt108_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt108 : 24; /* [23:0] */ + u32 rsv_95 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt108_u; + +/* Define the union csr_fq_cnt109_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt109 : 24; /* [23:0] */ + u32 rsv_96 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt109_u; + +/* Define the union csr_fq_cnt110_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt110 : 24; /* [23:0] */ + u32 rsv_97 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt110_u; + +/* Define the union csr_fq_cnt111_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt111 : 24; /* [23:0] */ + u32 rsv_98 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt111_u; + +/* Define the union csr_fq_cnt112_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt112 : 24; /* [23:0] */ + u32 rsv_99 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt112_u; + +/* Define the union csr_fq_cnt113_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt113 : 24; /* [23:0] */ + u32 rsv_100 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt113_u; + +/* Define the union csr_fq_cnt114_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt114 : 24; /* [23:0] */ + u32 rsv_101 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt114_u; + +/* Define the union csr_fq_cnt115_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt115 : 24; /* [23:0] */ + u32 rsv_102 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt115_u; + +/* Define the union csr_fq_cnt116_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt116 : 24; /* [23:0] */ + u32 rsv_103 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt116_u; + +/* Define the union csr_fq_cnt117_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt117 : 24; /* [23:0] */ + u32 rsv_104 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt117_u; + +/* Define the union csr_fq_cnt118_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt118 : 24; /* [23:0] */ + u32 rsv_105 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt118_u; + +/* Define the union csr_fq_cnt119_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt119 : 24; /* [23:0] */ + u32 rsv_106 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt119_u; + +/* Define the union csr_fq_cnt120_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt120 : 24; /* [23:0] */ + u32 rsv_107 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt120_u; + +/* Define the union csr_fq_cnt121_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt121 : 24; /* [23:0] */ + u32 rsv_108 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt121_u; + +/* Define the union csr_fq_cnt122_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt122 : 24; /* [23:0] */ + u32 rsv_109 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt122_u; + +/* Define the union csr_fq_cnt123_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt123 : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt123_u; + +/* Define the union csr_fq_cnt124_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt124 : 24; /* [23:0] */ + u32 rsv_111 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt124_u; + +/* Define the union csr_fq_cnt125_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt125 : 24; /* [23:0] */ + u32 rsv_112 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt125_u; + +/* Define the union csr_fq_cnt126_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt126 : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt126_u; + +/* Define the union csr_fq_cnt127_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt127 : 24; /* [23:0] */ + u32 rsv_114 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt127_u; + +/* Define the union csr_fq_cnt128_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt128 : 24; /* [23:0] */ + u32 rsv_115 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt128_u; + +/* Define the union csr_fq_cnt129_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt129 : 24; /* [23:0] */ + u32 rsv_116 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt129_u; + +/* Define the union csr_fq_cnt130_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt130 : 24; /* [23:0] */ + u32 rsv_117 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt130_u; + +/* Define the union csr_fq_cnt131_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt131 : 24; /* [23:0] */ + u32 rsv_118 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt131_u; + +/* Define the union csr_fq_cnt132_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt132 : 24; /* [23:0] */ + u32 rsv_119 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt132_u; + +/* Define the union csr_fq_cnt133_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt133 : 24; /* [23:0] */ + u32 rsv_120 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt133_u; + +/* Define the union csr_fq_cnt134_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt134 : 24; /* [23:0] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt134_u; + +/* Define the union csr_fq_cnt135_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt135 : 24; /* [23:0] */ + u32 rsv_122 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt135_u; + +/* Define the union csr_fq_cnt136_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt136 : 24; /* [23:0] */ + u32 rsv_123 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt136_u; + +/* Define the union csr_fq_cnt137_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt137 : 24; /* [23:0] */ + u32 rsv_124 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt137_u; + +/* Define the union csr_fq_cnt138_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt138 : 24; /* [23:0] */ + u32 rsv_125 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt138_u; + +/* Define the union csr_fq_cnt139_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt139 : 24; /* [23:0] */ + u32 rsv_126 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt139_u; + +/* Define the union csr_fq_cnt140_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt140 : 24; /* [23:0] */ + u32 rsv_127 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt140_u; + +/* Define the union csr_fq_cnt141_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt141 : 24; /* [23:0] */ + u32 rsv_128 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt141_u; + +/* Define the union csr_fq_cnt142_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt142 : 24; /* [23:0] */ + u32 rsv_129 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt142_u; + +/* Define the union csr_fq_cnt143_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt143 : 24; /* [23:0] */ + u32 rsv_130 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt143_u; + +/* Define the union csr_fq_cnt144_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt144 : 24; /* [23:0] */ + u32 rsv_131 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt144_u; + +/* Define the union csr_fq_cnt145_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt145 : 24; /* [23:0] */ + u32 rsv_132 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt145_u; + +/* Define the union csr_fq_cnt146_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt146 : 24; /* [23:0] */ + u32 rsv_133 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt146_u; + +/* Define the union csr_fq_cnt147_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt147 : 24; /* [23:0] */ + u32 rsv_134 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt147_u; + +/* Define the union csr_fq_cnt148_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt148 : 24; /* [23:0] */ + u32 rsv_135 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt148_u; + +/* Define the union csr_fq_cnt149_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt149 : 24; /* [23:0] */ + u32 rsv_136 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt149_u; + +/* Define the union csr_fq_cnt150_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt150 : 24; /* [23:0] */ + u32 rsv_137 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt150_u; + +/* Define the union csr_fq_cnt151_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt151 : 24; /* [23:0] */ + u32 rsv_138 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt151_u; + +/* Define the union csr_fq_cnt152_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt152 : 24; /* [23:0] */ + u32 rsv_139 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt152_u; + +/* Define the union csr_fq_cnt153_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt153 : 24; /* [23:0] */ + u32 rsv_140 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt153_u; + +/* Define the union csr_fq_cnt154_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt154 : 24; /* [23:0] */ + u32 rsv_141 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt154_u; + +/* Define the union csr_fq_cnt155_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt155 : 24; /* [23:0] */ + u32 rsv_142 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt155_u; + +/* Define the union csr_fq_cnt156_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt156 : 24; /* [23:0] */ + u32 rsv_143 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt156_u; + +/* Define the union csr_fq_cnt157_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt157 : 24; /* [23:0] */ + u32 rsv_144 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt157_u; + +/* Define the union csr_fq_cnt158_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt158 : 24; /* [23:0] */ + u32 rsv_145 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt158_u; + +/* Define the union csr_fq_cnt159_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt159 : 24; /* [23:0] */ + u32 rsv_146 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt159_u; + +/* Define the union csr_fq_cnt160_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt160 : 24; /* [23:0] */ + u32 rsv_147 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt160_u; + +/* Define the union csr_fq_cnt161_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt161 : 24; /* [23:0] */ + u32 rsv_148 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt161_u; + +/* Define the union csr_fq_cnt162_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt162 : 24; /* [23:0] */ + u32 rsv_149 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt162_u; + +/* Define the union csr_fq_cnt163_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt163 : 24; /* [23:0] */ + u32 rsv_150 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt163_u; + +/* Define the union csr_fq_cnt164_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt164 : 24; /* [23:0] */ + u32 rsv_151 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt164_u; + +/* Define the union csr_fq_cnt165_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt165 : 24; /* [23:0] */ + u32 rsv_152 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt165_u; + +/* Define the union csr_fq_cnt166_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt166 : 24; /* [23:0] */ + u32 rsv_153 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt166_u; + +/* Define the union csr_fq_cnt167_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt167 : 24; /* [23:0] */ + u32 rsv_154 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt167_u; + +/* Define the union csr_fq_cnt168_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt168 : 24; /* [23:0] */ + u32 rsv_155 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt168_u; + +/* Define the union csr_fq_cnt169_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt169 : 24; /* [23:0] */ + u32 rsv_156 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt169_u; + +/* Define the union csr_fq_cnt170_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt170 : 24; /* [23:0] */ + u32 rsv_157 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt170_u; + +/* Define the union csr_fq_cnt171_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt171 : 24; /* [23:0] */ + u32 rsv_158 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt171_u; + +/* Define the union csr_fq_cnt172_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt172 : 24; /* [23:0] */ + u32 rsv_159 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt172_u; + +/* Define the union csr_fq_cnt173_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt173 : 24; /* [23:0] */ + u32 rsv_160 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt173_u; + +/* Define the union csr_fq_cnt174_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt174 : 24; /* [23:0] */ + u32 rsv_161 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt174_u; + +/* Define the union csr_fq_cnt175_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt175 : 24; /* [23:0] */ + u32 rsv_162 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt175_u; + +/* Define the union csr_fq_cnt176_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt176 : 24; /* [23:0] */ + u32 rsv_163 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt176_u; + +/* Define the union csr_fq_cnt177_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt177 : 24; /* [23:0] */ + u32 rsv_164 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt177_u; + +/* Define the union csr_fq_cnt178_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt178 : 24; /* [23:0] */ + u32 rsv_165 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt178_u; + +/* Define the union csr_fq_cnt179_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt179 : 24; /* [23:0] */ + u32 rsv_166 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt179_u; + +/* Define the union csr_fq_cnt180_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt180 : 24; /* [23:0] */ + u32 rsv_167 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt180_u; + +/* Define the union csr_fq_cnt181_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt181 : 24; /* [23:0] */ + u32 rsv_168 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt181_u; + +/* Define the union csr_fq_cnt182_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt182 : 24; /* [23:0] */ + u32 rsv_169 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt182_u; + +/* Define the union csr_fq_cnt183_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt183 : 24; /* [23:0] */ + u32 rsv_170 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt183_u; + +/* Define the union csr_fq_cnt184_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt184 : 24; /* [23:0] */ + u32 rsv_171 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt184_u; + +/* Define the union csr_fq_cnt185_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt185 : 24; /* [23:0] */ + u32 rsv_172 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt185_u; + +/* Define the union csr_fq_cnt186_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt186 : 24; /* [23:0] */ + u32 rsv_173 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt186_u; + +/* Define the union csr_fq_cnt187_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt187 : 24; /* [23:0] */ + u32 rsv_174 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt187_u; + +/* Define the union csr_fq_cnt188_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt188 : 24; /* [23:0] */ + u32 rsv_175 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt188_u; + +/* Define the union csr_fq_cnt189_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt189 : 24; /* [23:0] */ + u32 rsv_176 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt189_u; + +/* Define the union csr_fq_cnt190_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt190 : 24; /* [23:0] */ + u32 rsv_177 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt190_u; + +/* Define the union csr_fq_cnt191_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt191 : 24; /* [23:0] */ + u32 rsv_178 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt191_u; + +/* Define the union csr_fq_cnt192_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt192 : 24; /* [23:0] */ + u32 rsv_179 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt192_u; + +/* Define the union csr_fq_cnt193_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt193 : 24; /* [23:0] */ + u32 rsv_180 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt193_u; + +/* Define the union csr_fq_cnt194_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt194 : 24; /* [23:0] */ + u32 rsv_181 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt194_u; + +/* Define the union csr_fq_cnt195_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt195 : 24; /* [23:0] */ + u32 rsv_182 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt195_u; + +/* Define the union csr_fq_cnt196_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt196 : 24; /* [23:0] */ + u32 rsv_183 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt196_u; + +/* Define the union csr_fq_cnt197_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt197 : 24; /* [23:0] */ + u32 rsv_184 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt197_u; + +/* Define the union csr_fq_cnt198_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt198 : 24; /* [23:0] */ + u32 rsv_185 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt198_u; + +/* Define the union csr_fq_cnt199_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt199 : 24; /* [23:0] */ + u32 rsv_186 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt199_u; + +/* Define the union csr_fq_cnt200_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt200 : 24; /* [23:0] */ + u32 rsv_187 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt200_u; + +/* Define the union csr_fq_cnt201_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt201 : 24; /* [23:0] */ + u32 rsv_188 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt201_u; + +/* Define the union csr_fq_cnt202_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt202 : 24; /* [23:0] */ + u32 rsv_189 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt202_u; + +/* Define the union csr_fq_cnt203_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt203 : 24; /* [23:0] */ + u32 rsv_190 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt203_u; + +/* Define the union csr_fq_cnt204_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt204 : 24; /* [23:0] */ + u32 rsv_191 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt204_u; + +/* Define the union csr_fq_cnt205_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt205 : 24; /* [23:0] */ + u32 rsv_192 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt205_u; + +/* Define the union csr_fq_cnt206_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt206 : 24; /* [23:0] */ + u32 rsv_193 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt206_u; + +/* Define the union csr_fq_cnt207_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt207 : 24; /* [23:0] */ + u32 rsv_194 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt207_u; + +/* Define the union csr_fq_cnt208_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt208 : 24; /* [23:0] */ + u32 rsv_195 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt208_u; + +/* Define the union csr_fq_cnt209_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt209 : 24; /* [23:0] */ + u32 rsv_196 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt209_u; + +/* Define the union csr_fq_cnt210_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt210 : 24; /* [23:0] */ + u32 rsv_197 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt210_u; + +/* Define the union csr_fq_cnt211_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt211 : 24; /* [23:0] */ + u32 rsv_198 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt211_u; + +/* Define the union csr_fq_cnt212_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt212 : 24; /* [23:0] */ + u32 rsv_199 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt212_u; + +/* Define the union csr_fq_cnt213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt213 : 24; /* [23:0] */ + u32 rsv_200 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt213_u; + +/* Define the union csr_fq_cnt214_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt214 : 24; /* [23:0] */ + u32 rsv_201 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt214_u; + +/* Define the union csr_fq_cnt215_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt215 : 24; /* [23:0] */ + u32 rsv_202 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt215_u; + +/* Define the union csr_fq_cnt216_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt216 : 24; /* [23:0] */ + u32 rsv_203 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt216_u; + +/* Define the union csr_fq_cnt217_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt217 : 24; /* [23:0] */ + u32 rsv_204 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt217_u; + +/* Define the union csr_fq_cnt218_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt218 : 24; /* [23:0] */ + u32 rsv_205 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt218_u; + +/* Define the union csr_fq_cnt219_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt219 : 24; /* [23:0] */ + u32 rsv_206 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt219_u; + +/* Define the union csr_fq_cnt220_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt220 : 24; /* [23:0] */ + u32 rsv_207 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt220_u; + +/* Define the union csr_fq_cnt221_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt221 : 24; /* [23:0] */ + u32 rsv_208 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt221_u; + +/* Define the union csr_fq_cnt222_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt222 : 24; /* [23:0] */ + u32 rsv_209 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt222_u; + +/* Define the union csr_fq_cnt223_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt223 : 24; /* [23:0] */ + u32 rsv_210 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt223_u; + +/* Define the union csr_fq_cnt224_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt224 : 24; /* [23:0] */ + u32 rsv_211 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt224_u; + +/* Define the union csr_fq_rxpsh_cid_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_rxpsh_cid_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rxpsh_cid_ctl_u; + +/* Define the union csr_fq_roce_db_odr_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_roce_db_odr_ctl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_roce_db_odr_ctl1_u; + +/* Define the union csr_fq_roce_db_odr_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_roce_db_odr_ctl2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_roce_db_odr_ctl2_u; + +/* Define the union csr_fq_norm_nic_odr_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_norm_nic_odr_ctl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_norm_nic_odr_ctl1_u; + +/* Define the union csr_fq_norm_nic_odr_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_norm_nic_odr_ctl2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_norm_nic_odr_ctl2_u; + +/* Define the union csr_fq_odr_flit256_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl1_u; + +/* Define the union csr_fq_odr_flit256_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl2_u; + +/* Define the union csr_fq_odr_flit256_ctl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl3_u; + +/* Define the union csr_fq_odr_flit256_ctl4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl4_u; + +/* Define the union csr_fq_odr_stype_cid2qid_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_stype_cid2qid_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_stype_cid2qid_en_u; + +/* Define the union csr_fq_cnt225_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt225 : 24; /* [23:0] */ + u32 rsv_212 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt225_u; + +/* Define the union csr_fq_cnt226_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt226 : 24; /* [23:0] */ + u32 rsv_213 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt226_u; + +/* Define the union csr_fq_cnt227_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt227 : 24; /* [23:0] */ + u32 rsv_214 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt227_u; + +/* Define the union csr_fq_cnt228_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt228 : 24; /* [23:0] */ + u32 rsv_215 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt228_u; + +/* Define the union csr_fq_cnt229_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt229 : 24; /* [23:0] */ + u32 rsv_216 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt229_u; + +/* Define the union csr_fq_cnt230_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt230 : 24; /* [23:0] */ + u32 rsv_217 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt230_u; + +/* Define the union csr_fq_cnt231_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt231 : 24; /* [23:0] */ + u32 rsv_218 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt231_u; + +/* Define the union csr_fq_cnt232_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt232 : 24; /* [23:0] */ + u32 rsv_219 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt232_u; + +/* Define the union csr_fq_cnt233_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt233 : 24; /* [23:0] */ + u32 rsv_220 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt233_u; + +/* Define the union csr_fq_cnt234_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt234 : 24; /* [23:0] */ + u32 rsv_221 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt234_u; + +/* Define the union csr_fq_cnt235_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt235 : 24; /* [23:0] */ + u32 rsv_222 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt235_u; + +/* Define the union csr_fq_cnt236_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt236 : 24; /* [23:0] */ + u32 rsv_223 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt236_u; + +/* Define the union csr_fq_cnt237_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt237 : 24; /* [23:0] */ + u32 rsv_224 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt237_u; + +/* Define the union csr_fq_cnt238_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt238 : 24; /* [23:0] */ + u32 rsv_225 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt238_u; + +/* Define the union csr_fq_cnt239_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt239 : 24; /* [23:0] */ + u32 rsv_226 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt239_u; + +/* Define the union csr_fq_cnt240_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt240 : 24; /* [23:0] */ + u32 rsv_227 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt240_u; + +/* Define the union csr_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_228 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_tcam_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_tcam_ctrl_bus : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tcam_ctrl_bus_cfg4_u; + +/* Define the union csr_fq_cnt241_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt241 : 24; /* [23:0] */ + u32 rsv_230 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt241_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_fq_mode_reg_u fq_mode_reg; /* 0 */ + volatile csr_fq_initctab_start_u fq_initctab_start; /* 4 */ + volatile csr_fq_initctab_st_u fq_initctab_st; /* 8 */ + volatile csr_fq_init_logic_st_u fq_init_logic_st; /* C */ + volatile csr_fq_int_vector_u fq_int_vector; /* 10 */ + volatile csr_fq_int_u fq_int; /* 14 */ + volatile csr_fq_int_mask_u fq_int_mask; /* 18 */ + volatile csr_fq_int_mem_err_2b_u fq_int_mem_err_2b; /* 1C */ + volatile csr_fq_int_oeid_aged_err_u fq_int_oeid_aged_err; /* 20 */ + volatile csr_fq_int_scan_err_u fq_int_scan_err; /* 24 */ + volatile csr_fq_int_fcmd_err_u fq_int_fcmd_err; /* 28 */ + volatile csr_fq_int_dsp_err_u fq_int_dsp_err; /* 2C */ + volatile csr_fq_int_pfh_err_u fq_int_pfh_err; /* 30 */ + volatile csr_fq_int_dbe_err_u fq_int_dbe_err; /* 34 */ + volatile csr_fq_int_qrsc_err_u fq_int_qrsc_err; /* 38 */ + volatile csr_fq_int_buf_uf_err_u fq_int_buf_uf_err; /* 3C */ + volatile csr_fq_int_fifo0_err_u fq_int_fifo0_err; /* 40 */ + volatile csr_fq_indrect_ctrl_u fq_indrect_ctrl; /* 44 */ + volatile csr_fq_indrect_timeout_u fq_indrect_timeout; /* 48 */ + volatile csr_fq_indrect_dat0_u fq_indrect_dat0; /* 4C */ + volatile csr_fq_indrect_dat1_u fq_indrect_dat1; /* 50 */ + volatile csr_fq_qcntx_mode_u fq_qcntx_mode; /* 54 */ + volatile csr_fq_age_period_reg_u fq_age_period_reg; /* 58 */ + volatile csr_stffq_dbe_hw_pfh_cfg_u stffq_dbe_hw_pfh_cfg; /* 5C */ + volatile csr_fq_tmr_st_u fq_tmr_st; /* 60 */ + volatile csr_fq_cpb_cfg_u fq_cpb_cfg; /* 64 */ + volatile csr_fq_crdt_2tlsmf_st_u fq_crdt_2tlsmf_st; /* 68 */ + volatile csr_fq_crdt_2tlsmf_reg_u fq_crdt_2tlsmf_reg; /* 6C */ + volatile csr_fq_cnt_ctl_u fq_cnt_ctl; /* 70 */ + volatile csr_fq_cnt0_u fq_cnt0; /* 74 */ + volatile csr_fq_cnt1_u fq_cnt1; /* 78 */ + volatile csr_fq_cnt2_u fq_cnt2; /* 7C */ + volatile csr_fq_cnt3_u fq_cnt3; /* 80 */ + volatile csr_fq_cnt4_u fq_cnt4; /* 84 */ + volatile csr_fq_snapshot_ctl_u fq_snapshot_ctl; /* 88 */ + volatile csr_fq_snapshot_st_u fq_snapshot_st; /* 8C */ + volatile csr_fq_dbe_hw_wqe_en_u fq_dbe_hw_wqe_en; /* 90 */ + volatile csr_fq_dbe_hw_wqe_cfg_u fq_dbe_hw_wqe_cfg; /* 94 */ + volatile csr_fq_fifo_gap_cfg_u fq_fifo_gap_cfg; /* 98 */ + volatile csr_fq_his_fifo_cnt0_u fq_his_fifo_cnt0; /* 9C */ + volatile csr_fq_his_fifo_cnt1_u fq_his_fifo_cnt1; /* A0 */ + volatile csr_fq_fifo_st_u fq_fifo_st; /* A4 */ + volatile csr_fq_his_fifo_st_u fq_his_fifo_st; /* A8 */ + volatile csr_fq_mem_ctrl_u fq_mem_ctrl; /* AC */ + volatile csr_fq_cfg_ep2host_u fq_cfg_ep2host; /* B0 */ + volatile csr_fq_pcar_cfg_u fq_pcar_cfg; /* B4 */ + volatile csr_fq_cnt5_u fq_cnt5; /* B8 */ + volatile csr_fq_mod_reg1_u fq_mod_reg1; /* BC */ + volatile csr_fq_inner_bp_st_u fq_inner_bp_st; /* C0 */ + volatile csr_fq_inner_mon_st_u fq_inner_mon_st; /* C4 */ + volatile csr_fq_cnt6_u fq_cnt6; /* C8 */ + volatile csr_fq_cnt_ctl1_u fq_cnt_ctl1; /* CC */ + volatile csr_fq_cnt7_u fq_cnt7; /* D0 */ + volatile csr_fq_cnt8_u fq_cnt8; /* D4 */ + volatile csr_fq_cnt9_u fq_cnt9; /* D8 */ + volatile csr_fq_cnt10_u fq_cnt10; /* DC */ + volatile csr_fq_cnt11_u fq_cnt11; /* E0 */ + volatile csr_fq_cnt12_u fq_cnt12; /* E4 */ + volatile csr_fq_cnt13_u fq_cnt13; /* E8 */ + volatile csr_fq_cnt14_u fq_cnt14; /* EC */ + volatile csr_fq_cnt15_u fq_cnt15; /* F0 */ + volatile csr_fq_cnt16_u fq_cnt16; /* F4 */ + volatile csr_fq_int_mem_err_1b_u fq_int_mem_err_1b; /* F8 */ + volatile csr_cfg_styp_th_fc_en_u cfg_styp_th_fc_en; /* FC */ + volatile csr_cfg_zero_esch_len_u cfg_zero_esch_len; /* 100 */ + volatile csr_cfg_fq_bubble_ctl_u cfg_fq_bubble_ctl; /* 104 */ + volatile csr_cfg_l2dcache_bubble_ctl_u cfg_l2dcache_bubble_ctl; /* 108 */ + volatile csr_fq_def_fq_ctl_u fq_def_fq_ctl; /* 10C */ + volatile csr_fq_smf_ldbctl_u fq_smf_ldbctl; /* 110 */ + volatile csr_fq_cfg_ep2host_h2_u fq_cfg_ep2host_h2; /* 114 */ + volatile csr_fq_cfg_prefetch_ctl_u fq_cfg_prefetch_ctl; /* 118 */ + volatile csr_fq_latency_cfg_u fq_latency_cfg; /* 11C */ + volatile csr_fq_latency_sta_u fq_latency_sta; /* 120 */ + volatile csr_fq_sample_tmr_u fq_sample_tmr; /* 124 */ + volatile csr_fq_cfg_fake_vf_ctl_u fq_cfg_fake_vf_ctl; /* 128 */ + volatile csr_fq_cfg_bps_dly_ctl_u fq_cfg_bps_dly_ctl; /* 12C */ + volatile csr_fq_cfg_otsd_base_ctl_u fq_cfg_otsd_base_ctl; /* 130 */ + volatile csr_fq_cnt_ctl2_u fq_cnt_ctl2; /* 134 */ + volatile csr_fq_cnt17_u fq_cnt17; /* 138 */ + volatile csr_fq_cnt18_u fq_cnt18; /* 13C */ + volatile csr_fq_cnt19_u fq_cnt19; /* 140 */ + volatile csr_fq_cnt20_u fq_cnt20; /* 144 */ + volatile csr_fq_cnt21_u fq_cnt21; /* 148 */ + volatile csr_fq_cnt22_u fq_cnt22; /* 14C */ + volatile csr_fq_cnt23_u fq_cnt23; /* 150 */ + volatile csr_fq_cnt24_u fq_cnt24; /* 154 */ + volatile csr_fq_cnt25_u fq_cnt25; /* 158 */ + volatile csr_fq_cnt26_u fq_cnt26; /* 15C */ + volatile csr_fq_cnt_ctl3_u fq_cnt_ctl3; /* 160 */ + volatile csr_fq_cnt27_u fq_cnt27; /* 164 */ + volatile csr_fq_cnt28_u fq_cnt28; /* 168 */ + volatile csr_fq_cnt29_u fq_cnt29; /* 16C */ + volatile csr_fq_cnt30_u fq_cnt30; /* 170 */ + volatile csr_fq_cnt31_u fq_cnt31; /* 174 */ + volatile csr_fq_cnt32_u fq_cnt32; /* 178 */ + volatile csr_fq_cnt33_u fq_cnt33; /* 17C */ + volatile csr_fq_cnt34_u fq_cnt34; /* 180 */ + volatile csr_fq_cnt35_u fq_cnt35; /* 184 */ + volatile csr_fq_cnt36_u fq_cnt36; /* 188 */ + volatile csr_fq_cnt_ctl4_u fq_cnt_ctl4; /* 18C */ + volatile csr_fq_cnt37_u fq_cnt37; /* 190 */ + volatile csr_fq_cnt38_u fq_cnt38; /* 194 */ + volatile csr_fq_cnt39_u fq_cnt39; /* 198 */ + volatile csr_fq_cnt40_u fq_cnt40; /* 19C */ + volatile csr_fq_cnt41_u fq_cnt41; /* 1A0 */ + volatile csr_fq_cnt42_u fq_cnt42; /* 1A4 */ + volatile csr_fq_cnt43_u fq_cnt43; /* 1A8 */ + volatile csr_fq_cnt44_u fq_cnt44; /* 1AC */ + volatile csr_fq_cnt45_u fq_cnt45; /* 1B0 */ + volatile csr_fq_cnt46_u fq_cnt46; /* 1B4 */ + volatile csr_fq_qu2smf_tmr_dly_u fq_qu2smf_tmr_dly; /* 1B8 */ + volatile csr_fq_magic_box_ctl_u fq_magic_box_ctl; /* 1BC */ + volatile csr_fq_mgbx_srv2hash_u fq_mgbx_srv2hash; /* 1C0 */ + volatile csr_fq_inner_mon_st1_u fq_inner_mon_st1; /* 1C4 */ + volatile csr_fq_inner_mon_st2_u fq_inner_mon_st2; /* 1C8 */ + volatile csr_fq_inner_mon_st3_u fq_inner_mon_st3; /* 1CC */ + volatile csr_fq_inner_mon_st4_u fq_inner_mon_st4; /* 1D0 */ + volatile csr_fq_inner_mon_st5_u fq_inner_mon_st5; /* 1D4 */ + volatile csr_fq_inner_mon_st6_u fq_inner_mon_st6; /* 1D8 */ + volatile csr_fq_inner_mon_st7_u fq_inner_mon_st7; /* 1DC */ + volatile csr_fq_inner_mon_st8_u fq_inner_mon_st8; /* 1E0 */ + volatile csr_fq_inner_mon_st9_u fq_inner_mon_st9; /* 1E4 */ + volatile csr_fq_inner_mon_st10_u fq_inner_mon_st10; /* 1E8 */ + volatile csr_fq_inner_mon_st11_u fq_inner_mon_st11; /* 1EC */ + volatile csr_fq_inner_mon_st12_u fq_inner_mon_st12; /* 1F0 */ + volatile csr_fq_inner_mon_st13_u fq_inner_mon_st13; /* 1F4 */ + volatile csr_fq_inner_mon_st14_u fq_inner_mon_st14; /* 1F8 */ + volatile csr_fq_inner_mon_st15_u fq_inner_mon_st15; /* 1FC */ + volatile csr_fq_inner_mon_st16_u fq_inner_mon_st16; /* 200 */ + volatile csr_fq_inner_mon_st17_u fq_inner_mon_st17; /* 204 */ + volatile csr_fq_inner_mon_st18_u fq_inner_mon_st18; /* 208 */ + volatile csr_fq_inner_mon_st19_u fq_inner_mon_st19; /* 20C */ + volatile csr_fq_inner_mon_st20_u fq_inner_mon_st20; /* 210 */ + volatile csr_fq_inner_mon_st21_u fq_inner_mon_st21; /* 214 */ + volatile csr_fq_inner_mon_st22_u fq_inner_mon_st22; /* 218 */ + volatile csr_fq_inner_mon_st23_u fq_inner_mon_st23; /* 21C */ + volatile csr_fq_inner_mon_st24_u fq_inner_mon_st24; /* 220 */ + volatile csr_fq_inner_mon_st25_u fq_inner_mon_st25; /* 224 */ + volatile csr_fq_inner_mon_st26_u fq_inner_mon_st26; /* 228 */ + volatile csr_fq_inner_mon_st27_u fq_inner_mon_st27; /* 22C */ + volatile csr_fq_inner_mon_st28_u fq_inner_mon_st28; /* 230 */ + volatile csr_fq_inner_mon_st29_u fq_inner_mon_st29; /* 234 */ + volatile csr_fq_inner_mon_st30_u fq_inner_mon_st30; /* 238 */ + volatile csr_fq_inner_mon_st31_u fq_inner_mon_st31; /* 23C */ + volatile csr_fq_inner_mon_st32_u fq_inner_mon_st32; /* 240 */ + volatile csr_fq_inner_mon_st33_u fq_inner_mon_st33; /* 244 */ + volatile csr_fq_inner_mon_st34_u fq_inner_mon_st34; /* 248 */ + volatile csr_fq_inner_mon_st35_u fq_inner_mon_st35; /* 24C */ + volatile csr_fq_inner_mon_st36_u fq_inner_mon_st36; /* 250 */ + volatile csr_fq_inner_mon_st37_u fq_inner_mon_st37; /* 254 */ + volatile csr_fq_inner_mon_st38_u fq_inner_mon_st38; /* 258 */ + volatile csr_fq_inner_mon_st39_u fq_inner_mon_st39; /* 25C */ + volatile csr_fq_inner_mon_st40_u fq_inner_mon_st40; /* 260 */ + volatile csr_fq_inner_mon_st41_u fq_inner_mon_st41; /* 264 */ + volatile csr_fq_inner_mon_st42_u fq_inner_mon_st42; /* 26C */ + volatile csr_fq_inner_mon_st43_u fq_inner_mon_st43; /* 270 */ + volatile csr_fq_inner_mon_st44_u fq_inner_mon_st44; /* 274 */ + volatile csr_fq_inner_mon_st45_u fq_inner_mon_st45; /* 278 */ + volatile csr_fq_inner_mon_st46_u fq_inner_mon_st46; /* 27C */ + volatile csr_fq_inner_mon_st47_u fq_inner_mon_st47; /* 280 */ + volatile csr_fq_inner_mon_st48_u fq_inner_mon_st48; /* 284 */ + volatile csr_fq_cnt47_u fq_cnt47; /* 288 */ + volatile csr_fq_rou_rqst_fifo0_u fq_rou_rqst_fifo0; /* 28C */ + volatile csr_fq_rou_rsp_fifo0_u fq_rou_rsp_fifo0; /* 290 */ + volatile csr_fq_rou_rsp_fifo1_u fq_rou_rsp_fifo1; /* 298 */ + volatile csr_fq_rou_tmrodr_fifo0_u fq_rou_tmrodr_fifo0; /* 29C */ + volatile csr_fq_rou_tmrodr_fifo1_u fq_rou_tmrodr_fifo1; /* 2A0 */ + volatile csr_fq_rou_tmrodr_fifo2_u fq_rou_tmrodr_fifo2; /* 2A4 */ + volatile csr_fq_rou_tmrodr_fifo3_u fq_rou_tmrodr_fifo3; /* 2A8 */ + volatile csr_fq_rin_rqst_fifo_u fq_rin_rqst_fifo; /* 2BC */ + volatile csr_fq_rin_rsp_fifo_u fq_rin_rsp_fifo; /* 2C0 */ + volatile csr_fq_smf_rsp_fifo0_u fq_smf_rsp_fifo0; /* 2D4 */ + volatile csr_fq_smf_rsp_fifo1_u fq_smf_rsp_fifo1; /* 2D8 */ + volatile csr_fq_tl0_cmd_fifo0_u fq_tl0_cmd_fifo0; /* 2DC */ + volatile csr_fq_tl0_extcmd_fifo0_u fq_tl0_extcmd_fifo0; /* 2E0 */ + volatile csr_fq_tl1_cmd_fifo1_u fq_tl1_cmd_fifo1; /* 2E4 */ + volatile csr_fq_tl1_extcmd_fifo0_u fq_tl1_extcmd_fifo0; /* 2E8 */ + volatile csr_fq_fq2oq_fcnp_fifo_u fq_fq2oq_fcnp_fifo; /* 2EC */ + volatile csr_fq_oq2fq_fcnp_fifo_u fq_oq2fq_fcnp_fifo; /* 2F0 */ + volatile csr_fq_tmr_rsp_fifo0_u fq_tmr_rsp_fifo0; /* 2F4 */ + volatile csr_fq_tmr_rsp_fifo1_u fq_tmr_rsp_fifo1; /* 2F8 */ + volatile csr_fq_tmr_rsp_fifo2_u fq_tmr_rsp_fifo2; /* 2FC */ + volatile csr_fq_tmr_rsp_fifo3_u fq_tmr_rsp_fifo3; /* 300 */ + volatile csr_fq_tmr_rsp_fifo4_u fq_tmr_rsp_fifo4; /* 304 */ + volatile csr_fq_tmr_rsp_fifo5_u fq_tmr_rsp_fifo5; /* 308 */ + volatile csr_fq_tmr_rsp_fifo6_u fq_tmr_rsp_fifo6; /* 30C */ + volatile csr_fq_tmr_rsp_fifo7_u fq_tmr_rsp_fifo7; /* 310 */ + volatile csr_fq_tmr_rsp_fifo8_u fq_tmr_rsp_fifo8; /* 314 */ + volatile csr_fq_tmr_rsp_fifo9_u fq_tmr_rsp_fifo9; /* 318 */ + volatile csr_fq_tmr_rsp_fifo10_u fq_tmr_rsp_fifo10; /* 31C */ + volatile csr_fq_tmr_rsp_fifo11_u fq_tmr_rsp_fifo11; /* 320 */ + volatile csr_fq_tmr_rsp_fifo12_u fq_tmr_rsp_fifo12; /* 324 */ + volatile csr_fq_tmr_rsp_fifo13_u fq_tmr_rsp_fifo13; /* 328 */ + volatile csr_fq_tmr_rsp_fifo14_u fq_tmr_rsp_fifo14; /* 32C */ + volatile csr_fq_tmr_rsp_fifo15_u fq_tmr_rsp_fifo15; /* 330 */ + volatile csr_fq_int_rin_rqst_err_u fq_int_rin_rqst_err; /* 334 */ + volatile csr_fq_int_rin_rsp_err_u fq_int_rin_rsp_err; /* 338 */ + volatile csr_fq_int_rin_trsp_err_u fq_int_rin_trsp_err; /* 33C */ + volatile csr_fq_int_fifo1_err_u fq_int_fifo1_err; /* 340 */ + volatile csr_fq_int_fifo2_err_u fq_int_fifo2_err; /* 344 */ + volatile csr_fq_cnt48_u fq_cnt48; /* 348 */ + volatile csr_fq_cfg_stg_qp_push0_u fq_cfg_stg_qp_push0; /* 34C */ + volatile csr_fq_cfg_stg_qp_push1_u fq_cfg_stg_qp_push1; /* 350 */ + volatile csr_fq_cfg_stg_qp_push2_u fq_cfg_stg_qp_push2; /* 354 */ + volatile csr_fq_dbe_hw_wqe_en1_u fq_dbe_hw_wqe_en1; /* 358 */ + volatile csr_fq_dbe_hw_wqe_en2_u fq_dbe_hw_wqe_en2; /* 35C */ + volatile csr_fq_dbe_hw_wqe_en3_u fq_dbe_hw_wqe_en3; /* 360 */ + volatile csr_fq_dbe_hw_wqe_en4_u fq_dbe_hw_wqe_en4; /* 364 */ + volatile csr_fq_dbe_hw_wqe_en5_u fq_dbe_hw_wqe_en5; /* 368 */ + volatile csr_fq_dbe_hw_wqe_en6_u fq_dbe_hw_wqe_en6; /* 36C */ + volatile csr_fq_dbe_hw_wqe_en7_u fq_dbe_hw_wqe_en7; /* 370 */ + volatile csr_fq_dbe_hw_wqe_en8_u fq_dbe_hw_wqe_en8; /* 374 */ + volatile csr_fq_dbe_hw_wqe_en9_u fq_dbe_hw_wqe_en9; /* 378 */ + volatile csr_fq_dbe_hw_wqe_en10_u fq_dbe_hw_wqe_en10; /* 37C */ + volatile csr_fq_dbe_hw_wqe_en11_u fq_dbe_hw_wqe_en11; /* 380 */ + volatile csr_fq_dbe_hw_wqe_en12_u fq_dbe_hw_wqe_en12; /* 384 */ + volatile csr_fq_dbe_hw_wqe_en13_u fq_dbe_hw_wqe_en13; /* 388 */ + volatile csr_fq_dbe_hw_wqe_en14_u fq_dbe_hw_wqe_en14; /* 38C */ + volatile csr_fq_dbe_hw_wqe_en15_u fq_dbe_hw_wqe_en15; /* 390 */ + volatile csr_fq_cnt49_u fq_cnt49; /* 394 */ + volatile csr_fq_cnt50_u fq_cnt50; /* 398 */ + volatile csr_fq_cnt51_u fq_cnt51; /* 39C */ + volatile csr_fq_cnt52_u fq_cnt52; /* 3A0 */ + volatile csr_fq_cnt53_u fq_cnt53; /* 3A4 */ + volatile csr_fq_cnt54_u fq_cnt54; /* 3A8 */ + volatile csr_fq_cnt55_u fq_cnt55; /* 3AC */ + volatile csr_fq_cnt56_u fq_cnt56; /* 3B0 */ + volatile csr_fq_cnt57_u fq_cnt57; /* 3B4 */ + volatile csr_fq_cnt58_u fq_cnt58; /* 3B8 */ + volatile csr_fq_cnt59_u fq_cnt59; /* 3BC */ + volatile csr_fq_cnt60_u fq_cnt60; /* 3C0 */ + volatile csr_fq_cnt61_u fq_cnt61; /* 3C4 */ + volatile csr_fq_cnt62_u fq_cnt62; /* 3C8 */ + volatile csr_fq_cnt63_u fq_cnt63; /* 3CC */ + volatile csr_fq_cnt64_u fq_cnt64; /* 3D0 */ + volatile csr_fq_cnt65_u fq_cnt65; /* 3D4 */ + volatile csr_fq_cnt66_u fq_cnt66; /* 3D8 */ + volatile csr_fq_cnt67_u fq_cnt67; /* 3DC */ + volatile csr_fq_cnt68_u fq_cnt68; /* 3E0 */ + volatile csr_fq_cnt69_u fq_cnt69; /* 3E4 */ + volatile csr_fq_cnt70_u fq_cnt70; /* 3E8 */ + volatile csr_fq_cnt71_u fq_cnt71; /* 3EC */ + volatile csr_fq_cnt72_u fq_cnt72; /* 3F0 */ + volatile csr_fq_cnt73_u fq_cnt73; /* 3F4 */ + volatile csr_fq_cnt74_u fq_cnt74; /* 3F8 */ + volatile csr_fq_cnt75_u fq_cnt75; /* 3FC */ + volatile csr_fq_cnt76_u fq_cnt76; /* 400 */ + volatile csr_fq_cnt77_u fq_cnt77; /* 404 */ + volatile csr_fq_cnt78_u fq_cnt78; /* 408 */ + volatile csr_fq_cnt79_u fq_cnt79; /* 40C */ + volatile csr_fq_cnt80_u fq_cnt80; /* 410 */ + volatile csr_fq_cnt81_u fq_cnt81; /* 414 */ + volatile csr_fq_cnt82_u fq_cnt82; /* 418 */ + volatile csr_fq_cnt83_u fq_cnt83; /* 41C */ + volatile csr_fq_cnt84_u fq_cnt84; /* 420 */ + volatile csr_fq_cnt85_u fq_cnt85; /* 424 */ + volatile csr_fq_cnt86_u fq_cnt86; /* 428 */ + volatile csr_fq_cnt87_u fq_cnt87; /* 42C */ + volatile csr_fq_cnt88_u fq_cnt88; /* 430 */ + volatile csr_fq_cnt89_u fq_cnt89; /* 434 */ + volatile csr_fq_cnt90_u fq_cnt90; /* 438 */ + volatile csr_fq_cnt91_u fq_cnt91; /* 43C */ + volatile csr_fq_cnt92_u fq_cnt92; /* 440 */ + volatile csr_fq_cnt93_u fq_cnt93; /* 444 */ + volatile csr_fq_cnt94_u fq_cnt94; /* 448 */ + volatile csr_fq_cnt95_u fq_cnt95; /* 44C */ + volatile csr_fq_cnt96_u fq_cnt96; /* 450 */ + volatile csr_fq_cnt97_u fq_cnt97; /* 454 */ + volatile csr_fq_cnt98_u fq_cnt98; /* 458 */ + volatile csr_fq_cnt99_u fq_cnt99; /* 45C */ + volatile csr_fq_cnt100_u fq_cnt100; /* 460 */ + volatile csr_fq_cnt101_u fq_cnt101; /* 464 */ + volatile csr_fq_cnt102_u fq_cnt102; /* 468 */ + volatile csr_fq_cnt103_u fq_cnt103; /* 46C */ + volatile csr_fq_cnt104_u fq_cnt104; /* 470 */ + volatile csr_fq_cnt105_u fq_cnt105; /* 474 */ + volatile csr_fq_cnt106_u fq_cnt106; /* 478 */ + volatile csr_fq_cnt107_u fq_cnt107; /* 47C */ + volatile csr_fq_cnt108_u fq_cnt108; /* 480 */ + volatile csr_fq_cnt109_u fq_cnt109; /* 484 */ + volatile csr_fq_cnt110_u fq_cnt110; /* 488 */ + volatile csr_fq_cnt111_u fq_cnt111; /* 48C */ + volatile csr_fq_cnt112_u fq_cnt112; /* 490 */ + volatile csr_fq_cnt113_u fq_cnt113; /* 494 */ + volatile csr_fq_cnt114_u fq_cnt114; /* 498 */ + volatile csr_fq_cnt115_u fq_cnt115; /* 49C */ + volatile csr_fq_cnt116_u fq_cnt116; /* 4A0 */ + volatile csr_fq_cnt117_u fq_cnt117; /* 4A4 */ + volatile csr_fq_cnt118_u fq_cnt118; /* 4A8 */ + volatile csr_fq_cnt119_u fq_cnt119; /* 4AC */ + volatile csr_fq_cnt120_u fq_cnt120; /* 4B0 */ + volatile csr_fq_cnt121_u fq_cnt121; /* 4B4 */ + volatile csr_fq_cnt122_u fq_cnt122; /* 4B8 */ + volatile csr_fq_cnt123_u fq_cnt123; /* 4BC */ + volatile csr_fq_cnt124_u fq_cnt124; /* 4C0 */ + volatile csr_fq_cnt125_u fq_cnt125; /* 4C4 */ + volatile csr_fq_cnt126_u fq_cnt126; /* 4C8 */ + volatile csr_fq_cnt127_u fq_cnt127; /* 4CC */ + volatile csr_fq_cnt128_u fq_cnt128; /* 4D0 */ + volatile csr_fq_cnt129_u fq_cnt129; /* 4D4 */ + volatile csr_fq_cnt130_u fq_cnt130; /* 4D8 */ + volatile csr_fq_cnt131_u fq_cnt131; /* 4DC */ + volatile csr_fq_cnt132_u fq_cnt132; /* 4E0 */ + volatile csr_fq_cnt133_u fq_cnt133; /* 4E4 */ + volatile csr_fq_cnt134_u fq_cnt134; /* 4E8 */ + volatile csr_fq_cnt135_u fq_cnt135; /* 4EC */ + volatile csr_fq_cnt136_u fq_cnt136; /* 4F0 */ + volatile csr_fq_cnt137_u fq_cnt137; /* 4F4 */ + volatile csr_fq_cnt138_u fq_cnt138; /* 4F8 */ + volatile csr_fq_cnt139_u fq_cnt139; /* 4FC */ + volatile csr_fq_cnt140_u fq_cnt140; /* 500 */ + volatile csr_fq_cnt141_u fq_cnt141; /* 504 */ + volatile csr_fq_cnt142_u fq_cnt142; /* 508 */ + volatile csr_fq_cnt143_u fq_cnt143; /* 50C */ + volatile csr_fq_cnt144_u fq_cnt144; /* 510 */ + volatile csr_fq_cnt145_u fq_cnt145; /* 514 */ + volatile csr_fq_cnt146_u fq_cnt146; /* 518 */ + volatile csr_fq_cnt147_u fq_cnt147; /* 51C */ + volatile csr_fq_cnt148_u fq_cnt148; /* 520 */ + volatile csr_fq_cnt149_u fq_cnt149; /* 524 */ + volatile csr_fq_cnt150_u fq_cnt150; /* 528 */ + volatile csr_fq_cnt151_u fq_cnt151; /* 52C */ + volatile csr_fq_cnt152_u fq_cnt152; /* 530 */ + volatile csr_fq_cnt153_u fq_cnt153; /* 534 */ + volatile csr_fq_cnt154_u fq_cnt154; /* 538 */ + volatile csr_fq_cnt155_u fq_cnt155; /* 53C */ + volatile csr_fq_cnt156_u fq_cnt156; /* 540 */ + volatile csr_fq_cnt157_u fq_cnt157; /* 544 */ + volatile csr_fq_cnt158_u fq_cnt158; /* 548 */ + volatile csr_fq_cnt159_u fq_cnt159; /* 54C */ + volatile csr_fq_cnt160_u fq_cnt160; /* 550 */ + volatile csr_fq_cnt161_u fq_cnt161; /* 554 */ + volatile csr_fq_cnt162_u fq_cnt162; /* 558 */ + volatile csr_fq_cnt163_u fq_cnt163; /* 55C */ + volatile csr_fq_cnt164_u fq_cnt164; /* 560 */ + volatile csr_fq_cnt165_u fq_cnt165; /* 564 */ + volatile csr_fq_cnt166_u fq_cnt166; /* 568 */ + volatile csr_fq_cnt167_u fq_cnt167; /* 56C */ + volatile csr_fq_cnt168_u fq_cnt168; /* 570 */ + volatile csr_fq_cnt169_u fq_cnt169; /* 574 */ + volatile csr_fq_cnt170_u fq_cnt170; /* 578 */ + volatile csr_fq_cnt171_u fq_cnt171; /* 57C */ + volatile csr_fq_cnt172_u fq_cnt172; /* 580 */ + volatile csr_fq_cnt173_u fq_cnt173; /* 584 */ + volatile csr_fq_cnt174_u fq_cnt174; /* 588 */ + volatile csr_fq_cnt175_u fq_cnt175; /* 58C */ + volatile csr_fq_cnt176_u fq_cnt176; /* 590 */ + volatile csr_fq_cnt177_u fq_cnt177; /* 594 */ + volatile csr_fq_cnt178_u fq_cnt178; /* 598 */ + volatile csr_fq_cnt179_u fq_cnt179; /* 59C */ + volatile csr_fq_cnt180_u fq_cnt180; /* 5A0 */ + volatile csr_fq_cnt181_u fq_cnt181; /* 5A4 */ + volatile csr_fq_cnt182_u fq_cnt182; /* 5A8 */ + volatile csr_fq_cnt183_u fq_cnt183; /* 5AC */ + volatile csr_fq_cnt184_u fq_cnt184; /* 5B0 */ + volatile csr_fq_cnt185_u fq_cnt185; /* 5B4 */ + volatile csr_fq_cnt186_u fq_cnt186; /* 5B8 */ + volatile csr_fq_cnt187_u fq_cnt187; /* 5BC */ + volatile csr_fq_cnt188_u fq_cnt188; /* 5C0 */ + volatile csr_fq_cnt189_u fq_cnt189; /* 5C4 */ + volatile csr_fq_cnt190_u fq_cnt190; /* 5C8 */ + volatile csr_fq_cnt191_u fq_cnt191; /* 5CC */ + volatile csr_fq_cnt192_u fq_cnt192; /* 5D0 */ + volatile csr_fq_cnt193_u fq_cnt193; /* 5D4 */ + volatile csr_fq_cnt194_u fq_cnt194; /* 5D8 */ + volatile csr_fq_cnt195_u fq_cnt195; /* 5DC */ + volatile csr_fq_cnt196_u fq_cnt196; /* 5E0 */ + volatile csr_fq_cnt197_u fq_cnt197; /* 5E4 */ + volatile csr_fq_cnt198_u fq_cnt198; /* 5E8 */ + volatile csr_fq_cnt199_u fq_cnt199; /* 5EC */ + volatile csr_fq_cnt200_u fq_cnt200; /* 5F0 */ + volatile csr_fq_cnt201_u fq_cnt201; /* 5F4 */ + volatile csr_fq_cnt202_u fq_cnt202; /* 5F8 */ + volatile csr_fq_cnt203_u fq_cnt203; /* 5FC */ + volatile csr_fq_cnt204_u fq_cnt204; /* 600 */ + volatile csr_fq_cnt205_u fq_cnt205; /* 604 */ + volatile csr_fq_cnt206_u fq_cnt206; /* 608 */ + volatile csr_fq_cnt207_u fq_cnt207; /* 60C */ + volatile csr_fq_cnt208_u fq_cnt208; /* 610 */ + volatile csr_fq_cnt209_u fq_cnt209; /* 614 */ + volatile csr_fq_cnt210_u fq_cnt210; /* 618 */ + volatile csr_fq_cnt211_u fq_cnt211; /* 61C */ + volatile csr_fq_cnt212_u fq_cnt212; /* 620 */ + volatile csr_fq_cnt213_u fq_cnt213; /* 624 */ + volatile csr_fq_cnt214_u fq_cnt214; /* 628 */ + volatile csr_fq_cnt215_u fq_cnt215; /* 62C */ + volatile csr_fq_cnt216_u fq_cnt216; /* 630 */ + volatile csr_fq_cnt217_u fq_cnt217; /* 634 */ + volatile csr_fq_cnt218_u fq_cnt218; /* 638 */ + volatile csr_fq_cnt219_u fq_cnt219; /* 63C */ + volatile csr_fq_cnt220_u fq_cnt220; /* 640 */ + volatile csr_fq_cnt221_u fq_cnt221; /* 644 */ + volatile csr_fq_cnt222_u fq_cnt222; /* 648 */ + volatile csr_fq_cnt223_u fq_cnt223; /* 64C */ + volatile csr_fq_cnt224_u fq_cnt224; /* 650 */ + volatile csr_fq_rxpsh_cid_ctl_u fq_rxpsh_cid_ctl; /* 654 */ + volatile csr_fq_roce_db_odr_ctl1_u fq_roce_db_odr_ctl1; /* 658 */ + volatile csr_fq_roce_db_odr_ctl2_u fq_roce_db_odr_ctl2; /* 65C */ + volatile csr_fq_norm_nic_odr_ctl1_u fq_norm_nic_odr_ctl1; /* 660 */ + volatile csr_fq_norm_nic_odr_ctl2_u fq_norm_nic_odr_ctl2; /* 664 */ + volatile csr_fq_odr_flit256_ctl1_u fq_odr_flit256_ctl1; /* 668 */ + volatile csr_fq_odr_flit256_ctl2_u fq_odr_flit256_ctl2; /* 66C */ + volatile csr_fq_odr_flit256_ctl3_u fq_odr_flit256_ctl3; /* 670 */ + volatile csr_fq_odr_flit256_ctl4_u fq_odr_flit256_ctl4; /* 674 */ + volatile csr_fq_odr_stype_cid2qid_en_u fq_odr_stype_cid2qid_en; /* 678 */ + volatile csr_fq_cnt225_u fq_cnt225; /* 67C */ + volatile csr_fq_cnt226_u fq_cnt226; /* 680 */ + volatile csr_fq_cnt227_u fq_cnt227; /* 684 */ + volatile csr_fq_cnt228_u fq_cnt228; /* 688 */ + volatile csr_fq_cnt229_u fq_cnt229; /* 68C */ + volatile csr_fq_cnt230_u fq_cnt230; /* 690 */ + volatile csr_fq_cnt231_u fq_cnt231; /* 694 */ + volatile csr_fq_cnt232_u fq_cnt232; /* 698 */ + volatile csr_fq_cnt233_u fq_cnt233; /* 69C */ + volatile csr_fq_cnt234_u fq_cnt234; /* 6A0 */ + volatile csr_fq_cnt235_u fq_cnt235; /* 6A4 */ + volatile csr_fq_cnt236_u fq_cnt236; /* 6A8 */ + volatile csr_fq_cnt237_u fq_cnt237; /* 6AC */ + volatile csr_fq_cnt238_u fq_cnt238; /* 6B0 */ + volatile csr_fq_cnt239_u fq_cnt239; /* 6B4 */ + volatile csr_fq_cnt240_u fq_cnt240; /* 6B8 */ + volatile csr_mem_ctrl_bus_cfg0_u mem_ctrl_bus_cfg0; /* 6BC */ + volatile csr_mem_ctrl_bus_cfg1_u mem_ctrl_bus_cfg1; /* 6C0 */ + volatile csr_mem_ctrl_bus_cfg2_u mem_ctrl_bus_cfg2; /* 6C4 */ + volatile csr_mem_ctrl_bus_cfg3_u mem_ctrl_bus_cfg3; /* 6C8 */ + volatile csr_mem_ctrl_bus_cfg4_u mem_ctrl_bus_cfg4; /* 6CC */ + volatile csr_tcam_ctrl_bus_cfg4_u tcam_ctrl_bus_cfg4; /* 6D0 */ + volatile csr_fq_cnt241_u fq_cnt241; /* 6D4 */ +} S_qu_stffq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_stffq_csr */ +extern volatile S_qu_stffq_csr_REGS_TYPE *gopqu_stffq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetFQ_MODE_REG_cfg_max_oeid(unsigned int ucfg_max_oeid); +int iSetFQ_MODE_REG_cfg_mode_init_def_fq_tx(unsigned int ucfg_mode_init_def_fq_tx); +int iSetFQ_MODE_REG_enable_stf(unsigned int uenable_stf); +int iSetFQ_MODE_REG_cfg_ngsf_mod(unsigned int ucfg_ngsf_mod); +int iSetFQ_MODE_REG_enable_pro(unsigned int uenable_pro); +int iSetFQ_MODE_REG_enable_asc(unsigned int uenable_asc); +int iSetFQ_MODE_REG_cfg_psh_msg_en(unsigned int ucfg_psh_msg_en); +int iSetFQ_MODE_REG_cfg_base_init_def_fq(unsigned int ucfg_base_init_def_fq); +int iSetFQ_MODE_REG_cfg_mode_init_def_fq(unsigned int ucfg_mode_init_def_fq); +int iSetFQ_MODE_REG_cfg_mode_pn(unsigned int ucfg_mode_pn); +int iSetFQ_INITCTAB_START_init_start(unsigned int uinit_start); +int iSetFQ_INITCTAB_ST_fq_init_ctab_st_done(unsigned int ufq_init_ctab_st_done); +int iSetFQ_INIT_LOGIC_ST_fq_init_logic_st_done(unsigned int ufq_init_logic_st_done); +int iSetFQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetFQ_INT_VECTOR_enable(unsigned int uenable); +int iSetFQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetFQ_INT_int_data(unsigned int uint_data); +int iSetFQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetFQ_INT_MASK_int_en(unsigned int uint_en); +int iSetFQ_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetFQ_INT_MEM_ERR_2B_mem_2bit_error(unsigned int umem_2bit_error); +int iSetFQ_INT_MEM_ERR_2B_int_insrt0(unsigned int uint_insrt0); +int iSetFQ_INT_MEM_ERR_2B_mem_err_sticky(unsigned int umem_err_sticky); +int iSetFQ_INT_OEID_AGED_ERR_oeid_age_err_error_bit(unsigned int uoeid_age_err_error_bit); +int iSetFQ_INT_OEID_AGED_ERR_int_insrt1(unsigned int uint_insrt1); +int iSetFQ_INT_OEID_AGED_ERR_oeid_age_err_sticky(unsigned int uoeid_age_err_sticky); +int iSetFQ_INT_SCAN_ERR_scan_err_error_bit(unsigned int uscan_err_error_bit); +int iSetFQ_INT_SCAN_ERR_int_insrt2(unsigned int uint_insrt2); +int iSetFQ_INT_SCAN_ERR_scan_err_sticky(unsigned int uscan_err_sticky); +int iSetFQ_INT_FCMD_ERR_fcmd_err_error_bit(unsigned int ufcmd_err_error_bit); +int iSetFQ_INT_FCMD_ERR_int_insrt3(unsigned int uint_insrt3); +int iSetFQ_INT_FCMD_ERR_fcmd_err_sticky(unsigned int ufcmd_err_sticky); +int iSetFQ_INT_DSP_ERR_dsp_err_error_bit(unsigned int udsp_err_error_bit); +int iSetFQ_INT_DSP_ERR_int_insrt4(unsigned int uint_insrt4); +int iSetFQ_INT_DSP_ERR_dsp_err_sticky(unsigned int udsp_err_sticky); +int iSetFQ_INT_PFH_ERR_pfh_err_error_bit(unsigned int upfh_err_error_bit); +int iSetFQ_INT_PFH_ERR_int_insrt5(unsigned int uint_insrt5); +int iSetFQ_INT_PFH_ERR_pfh_err_sticky(unsigned int upfh_err_sticky); +int iSetFQ_INT_DBE_ERR_dbe_err_error_bit(unsigned int udbe_err_error_bit); +int iSetFQ_INT_DBE_ERR_int_insrt6(unsigned int uint_insrt6); +int iSetFQ_INT_DBE_ERR_dbe_err_sticky(unsigned int udbe_err_sticky); +int iSetFQ_INT_QRSC_ERR_qrsc_err_error_bit(unsigned int uqrsc_err_error_bit); +int iSetFQ_INT_QRSC_ERR_int_insrt7(unsigned int uint_insrt7); +int iSetFQ_INT_QRSC_ERR_qrsc_err_sticky(unsigned int uqrsc_err_sticky); +int iSetFQ_INT_BUF_UF_ERR_buf_uf_error_bit(unsigned int ubuf_uf_error_bit); +int iSetFQ_INT_BUF_UF_ERR_int_insrt8(unsigned int uint_insrt8); +int iSetFQ_INT_BUF_UF_ERR_buf_uf_sticky(unsigned int ubuf_uf_sticky); +int iSetFQ_INT_FIFO0_ERR_fifo_err_error_bit(unsigned int ufifo_err_error_bit); +int iSetFQ_INT_FIFO0_ERR_int_insrt9(unsigned int uint_insrt9); +int iSetFQ_INT_FIFO0_ERR_fifo_err_sticky(unsigned int ufifo_err_sticky); +int iSetFQ_INDRECT_CTRL_indirect_vld(unsigned int uindirect_vld); +int iSetFQ_INDRECT_TIMEOUT_csr_stffq_indrect_timeout(unsigned int ucsr_stffq_indrect_timeout); +int iSetFQ_INDRECT_DAT0_csr_stffq_indrect_data0(unsigned int ucsr_stffq_indrect_data0); +int iSetFQ_INDRECT_DAT1_csr_stffq_indrect_data1(unsigned int ucsr_stffq_indrect_data1); +int iSetFQ_QCNTX_MODE_cfg_wm_lru(unsigned int ucfg_wm_lru); +int iSetFQ_QCNTX_MODE_cfg_lqp_lru(unsigned int ucfg_lqp_lru); +int iSetFQ_QCNTX_MODE_cfg_w2r_byps_en(unsigned int ucfg_w2r_byps_en); +int iSetFQ_QCNTX_MODE_cfg_rcmd_npa_lb_oq_en(unsigned int ucfg_rcmd_npa_lb_oq_en); +int iSetFQ_QCNTX_MODE_cfg_rcmd_pa_lb_oq_en(unsigned int ucfg_rcmd_pa_lb_oq_en); +int iSetFQ_QCNTX_MODE_cfg_wdog_rfil_period(unsigned int ucfg_wdog_rfil_period); +int iSetFQ_QCNTX_MODE_cfg_wdog_rfil_en(unsigned int ucfg_wdog_rfil_en); +int iSetFQ_QCNTX_MODE_cfg_rfl_fastlck_en(unsigned int ucfg_rfl_fastlck_en); +int iSetFQ_AGE_PERIOD_REG_cfg_age_period(unsigned int ucfg_age_period); +int iSetFQ_AGE_PERIOD_REG_cfg_age_period_bg(unsigned int ucfg_age_period_bg); +int iSetFQ_AGE_PERIOD_REG_cfg_fstr_wg(unsigned int ucfg_fstr_wg); +int iSetFQ_AGE_PERIOD_REG_cfg_age_oeid_bg_en(unsigned int ucfg_age_oeid_bg_en); +int iSetFQ_AGE_PERIOD_REG_cfg_wg_eng_en(unsigned int ucfg_wg_eng_en); +int iSetFQ_AGE_PERIOD_REG_cfg_age_oeid_en(unsigned int ucfg_age_oeid_en); +int iSetFQ_AGE_PERIOD_REG_cfg_age2un_en(unsigned int ucfg_age2un_en); +int iSetFQ_AGE_PERIOD_REG_cfg_fq_age_unit(unsigned int ucfg_fq_age_unit); +int iSetSTFFQ_DBE_HW_PFH_CFG_cfg_dbe_hw_pfh_en(unsigned int ucfg_dbe_hw_pfh_en); +int iSetFQ_TMR_ST_st_tmr_defer(unsigned int ust_tmr_defer); +int iSetFQ_TMR_ST_st_tmr_exp(unsigned int ust_tmr_exp); +int iSetFQ_CPB_CFG_dma_adj_attr(unsigned int udma_adj_attr); +int iSetFQ_CPB_CFG_dma_adj_attr_def(unsigned int udma_adj_attr_def); +int iSetFQ_CPB_CFG_otsd_psh_plen(unsigned int uotsd_psh_plen); +int iSetFQ_CPB_CFG_psh_plen_en(unsigned int upsh_plen_en); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_cmd_smf(unsigned int ucnt_crdt_cmd_smf); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_dat_smf(unsigned int ucnt_crdt_dat_smf); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_tl0(unsigned int ucnt_crdt_tl0); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_tl1(unsigned int ucnt_crdt_tl1); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_cmd_smf(unsigned int ucfg_def_crdt_cmd_smf); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_dat_smf(unsigned int ucfg_def_crdt_dat_smf); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_tl0_rsp(unsigned int ucfg_def_crdt_tl0_rsp); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_tl1_rsp(unsigned int ucfg_def_crdt_tl1_rsp); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_tmrs(unsigned int ucfg_def_crdt_tmrs); +int iSetFQ_CNT_CTL_mon_sel_idx(unsigned int umon_sel_idx); +int iSetFQ_CNT_CTL_cfg_cnt6_en(unsigned int ucfg_cnt6_en); +int iSetFQ_CNT_CTL_cfg_flit_cnt_en(unsigned int ucfg_flit_cnt_en); +int iSetFQ_CNT_CTL_cfg_cnt_en(unsigned int ucfg_cnt_en); +int iSetFQ_CNT0_fq_cnt0(unsigned int ufq_cnt0); +int iSetFQ_CNT1_fq_cnt1(unsigned int ufq_cnt1); +int iSetFQ_CNT2_fq_cnt2(unsigned int ufq_cnt2); +int iSetFQ_CNT3_fq_cnt3(unsigned int ufq_cnt3); +int iSetFQ_CNT4_fq_cnt4(unsigned int ufq_cnt4); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_srv_typ(unsigned int ucfg_snapsot_srv_typ); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_src(unsigned int ucfg_snapsot_src); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_req_typ(unsigned int ucfg_snapsot_req_typ); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_fqid(unsigned int ucfg_snapsot_fqid); +int iSetFQ_SNAPSHOT_CTL_cfg_snapshot_filt_typ_en(unsigned int ucfg_snapshot_filt_typ_en); +int iSetFQ_SNAPSHOT_CTL_cfg_snapshot_en(unsigned int ucfg_snapshot_en); +int iSetFQ_SNAPSHOT_ST_max_asc_latency(unsigned int umax_asc_latency); +int iSetFQ_SNAPSHOT_ST_max_latency_stg(unsigned int umax_latency_stg); +int iSetFQ_SNAPSHOT_ST_total_latency(unsigned int utotal_latency); +int iSetFQ_SNAPSHOT_ST_snapshot_done(unsigned int usnapshot_done); +int iSetFQ_DBE_HW_WQE_EN_cfg_dbe_hw_wqe_en(unsigned int ucfg_dbe_hw_wqe_en); +int iSetFQ_DBE_HW_WQE_CFG_cfg_stagh_wqe_ld(unsigned int ucfg_stagh_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_opid_wqe_ld(unsigned int ucfg_opid_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_aext_wqe_ld(unsigned int ucfg_aext_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_ftid_wqe_ld(unsigned int ucfg_ftid_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_aext_ord(unsigned int ucfg_aext_ord); +int iSetFQ_DBE_HW_WQE_CFG_cfg_txpfl_qp_push(unsigned int ucfg_txpfl_qp_push); +int iSetFQ_DBE_HW_WQE_CFG_cfg_rxpfl_qp_push(unsigned int ucfg_rxpfl_qp_push); +int iSetFQ_DBE_HW_WQE_CFG_cfg_otsd_qp_push(unsigned int ucfg_otsd_qp_push); +int iSetFQ_FIFO_GAP_CFG_gap_fifo_rsp2tl(unsigned int ugap_fifo_rsp2tl); +int iSetFQ_FIFO_GAP_CFG_gap_cmds_fifos(unsigned int ugap_cmds_fifos); +int iSetFQ_FIFO_GAP_CFG_gap_fifo_p2t_cmd(unsigned int ugap_fifo_p2t_cmd); +int iSetFQ_FIFO_GAP_CFG_gap_afifo_cpback(unsigned int ugap_afifo_cpback); +int iSetFQ_FIFO_GAP_CFG_gap_bnd_oeid(unsigned int ugap_bnd_oeid); +int iSetFQ_FIFO_GAP_CFG_gap_afifo_icc_rsp(unsigned int ugap_afifo_icc_rsp); +int iSetFQ_HIS_FIFO_CNT0_p2e_f(unsigned int up2e_f); +int iSetFQ_HIS_FIFO_CNT0_p2e_rbnd(unsigned int up2e_rbnd); +int iSetFQ_HIS_FIFO_CNT0_p2e_ulck(unsigned int up2e_ulck); +int iSetFQ_HIS_FIFO_CNT0_rlck_pcm(unsigned int urlck_pcm); +int iSetFQ_HIS_FIFO_CNT0_cpback(unsigned int ucpback); +int iSetFQ_HIS_FIFO_CNT0_icc_rsp(unsigned int uicc_rsp); +int iSetFQ_HIS_FIFO_CNT0_rlck(unsigned int urlck); +int iSetFQ_HIS_FIFO_CNT1_empty_tpfh(unsigned int uempty_tpfh); +int iSetFQ_HIS_FIFO_CNT1_empty_spqc(unsigned int uempty_spqc); +int iSetFQ_HIS_FIFO_CNT1_empty_rqpc(unsigned int uempty_rqpc); +int iSetFQ_HIS_FIFO_CNT1_empty_ism(unsigned int uempty_ism); +int iSetFQ_HIS_FIFO_CNT1_empty_tpcl(unsigned int uempty_tpcl); +int iSetFQ_HIS_FIFO_CNT1_empty_tcm(unsigned int uempty_tcm); +int iSetFQ_HIS_FIFO_CNT1_tl0_req(unsigned int utl0_req); +int iSetFQ_HIS_FIFO_CNT1_tl1_req(unsigned int utl1_req); +int iSetFQ_HIS_FIFO_CNT1_tl2p_cmds(unsigned int utl2p_cmds); +int iSetFQ_HIS_FIFO_CNT1_tl2p_rfl(unsigned int utl2p_rfl); +int iSetFQ_HIS_FIFO_CNT1_p2tl_cmds(unsigned int up2tl_cmds); +int iSetFQ_FIFO_ST_afull_tl0_rsp(unsigned int uafull_tl0_rsp); +int iSetFQ_FIFO_ST_afull_tl1_rsp(unsigned int uafull_tl1_rsp); +int iSetFQ_FIFO_ST_afull_tl0_req(unsigned int uafull_tl0_req); +int iSetFQ_FIFO_ST_afull_tl1_req(unsigned int uafull_tl1_req); +int iSetFQ_FIFO_ST_afull_tl2p_cmds(unsigned int uafull_tl2p_cmds); +int iSetFQ_FIFO_ST_afull_tl2p_rfl(unsigned int uafull_tl2p_rfl); +int iSetFQ_FIFO_ST_afull_p2tl_cmds(unsigned int uafull_p2tl_cmds); +int iSetFQ_FIFO_ST_afull_p2e_f(unsigned int uafull_p2e_f); +int iSetFQ_FIFO_ST_afull_p2e_rbnd(unsigned int uafull_p2e_rbnd); +int iSetFQ_FIFO_ST_afull_p2e_ulck(unsigned int uafull_p2e_ulck); +int iSetFQ_FIFO_ST_afull_rlck_pcm(unsigned int uafull_rlck_pcm); +int iSetFQ_FIFO_ST_afull_cpback(unsigned int uafull_cpback); +int iSetFQ_FIFO_ST_afull_icc_rsp(unsigned int uafull_icc_rsp); +int iSetFQ_FIFO_ST_afull_bnd(unsigned int uafull_bnd); +int iSetFQ_FIFO_ST_empty_tl0_0dat(unsigned int uempty_tl0_0dat); +int iSetFQ_FIFO_ST_empty_tl0_idat(unsigned int uempty_tl0_idat); +int iSetFQ_FIFO_ST_empty_tl1_0dat(unsigned int uempty_tl1_0dat); +int iSetFQ_FIFO_ST_empty_tl1_idat(unsigned int uempty_tl1_idat); +int iSetFQ_FIFO_ST_empty_tl0_rsp(unsigned int uempty_tl0_rsp); +int iSetFQ_FIFO_ST_empty_tl1_rsp(unsigned int uempty_tl1_rsp); +int iSetFQ_FIFO_ST_empty_tl0_req(unsigned int uempty_tl0_req); +int iSetFQ_FIFO_ST_empty_tl1_req(unsigned int uempty_tl1_req); +int iSetFQ_FIFO_ST_empty_tl2p_cmds(unsigned int uempty_tl2p_cmds); +int iSetFQ_FIFO_ST_empty_tl2p_rfl(unsigned int uempty_tl2p_rfl); +int iSetFQ_FIFO_ST_empty_p2tl_cmds(unsigned int uempty_p2tl_cmds); +int iSetFQ_FIFO_ST_empty_p2e_f(unsigned int uempty_p2e_f); +int iSetFQ_FIFO_ST_empty_p2e_rbnd(unsigned int uempty_p2e_rbnd); +int iSetFQ_FIFO_ST_empty_p2e_ulck(unsigned int uempty_p2e_ulck); +int iSetFQ_FIFO_ST_empty_rlck_pcm(unsigned int uempty_rlck_pcm); +int iSetFQ_FIFO_ST_empty_cpback(unsigned int uempty_cpback); +int iSetFQ_FIFO_ST_empty_icc_rsp(unsigned int uempty_icc_rsp); +int iSetFQ_FIFO_ST_empty_bnd(unsigned int uempty_bnd); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_rsp(unsigned int uhis_ful_tl0_rsp); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_rsp(unsigned int uhis_ful_tl1_rsp); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_req(unsigned int uhis_ful_tl0_req); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_req(unsigned int uhis_ful_tl1_req); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_tl2p_cmds(unsigned int uhis_ful_fifo_tl2p_cmds); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_tl2p_rfl(unsigned int uhis_ful_fifo_tl2p_rfl); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2tl_cmds(unsigned int uhis_ful_fifo_p2tl_cmds); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2e_f(unsigned int uhis_ful_fifo_p2e_f); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2e_rbnd(unsigned int uhis_ful_fifo_p2e_rbnd); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2e_ulck(unsigned int uhis_ful_fifo_p2e_ulck); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_rlck_pcm(unsigned int uhis_ful_fifo_rlck_pcm); +int iSetFQ_HIS_FIFO_ST_his_ful_afifo_cpback(unsigned int uhis_ful_afifo_cpback); +int iSetFQ_HIS_FIFO_ST_his_ful_afifo_icc_rsp(unsigned int uhis_ful_afifo_icc_rsp); +int iSetFQ_HIS_FIFO_ST_his_ful_afifo_bnd(unsigned int uhis_ful_afifo_bnd); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_idat(unsigned int uhis_ful_tl0_idat); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_odat(unsigned int uhis_ful_tl0_odat); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_idat(unsigned int uhis_ful_tl1_idat); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_odat(unsigned int uhis_ful_tl1_odat); +int iSetFQ_HIS_FIFO_ST_his_ful_ism_dat(unsigned int uhis_ful_ism_dat); +int iSetFQ_HIS_FIFO_ST_his_ful_sqpc(unsigned int uhis_ful_sqpc); +int iSetFQ_HIS_FIFO_ST_his_ful_rqpc(unsigned int uhis_ful_rqpc); +int iSetFQ_HIS_FIFO_ST_his_ful_tpfh(unsigned int uhis_ful_tpfh); +int iSetFQ_HIS_FIFO_ST_his_ful_tpcl(unsigned int uhis_ful_tpcl); +int iSetFQ_HIS_FIFO_ST_his_ful_tcm(unsigned int uhis_ful_tcm); +int iSetFQ_MEM_CTRL_mem_power_ctrl_sp(unsigned int umem_power_ctrl_sp); +int iSetFQ_MEM_CTRL_mem_timing_ctrl_sp(unsigned int umem_timing_ctrl_sp); +int iSetFQ_MEM_CTRL_mem_power_ctrl_tp(unsigned int umem_power_ctrl_tp); +int iSetFQ_MEM_CTRL_mem_timing_ctrl_tp(unsigned int umem_timing_ctrl_tp); +int iSetFQ_MEM_CTRL_err_req(unsigned int uerr_req); +int iSetFQ_MEM_CTRL_indirect_mem_ecc_en(unsigned int uindirect_mem_ecc_en); +int iSetFQ_MEM_CTRL_mem_ecc_bypass(unsigned int umem_ecc_bypass); +int iSetFQ_CFG_EP2HOST_cfg_map_ep2host(unsigned int ucfg_map_ep2host); +int iSetFQ_PCAR_CFG_cfg_pcar_sh(unsigned int ucfg_pcar_sh); +int iSetFQ_PCAR_CFG_cfg_pcar_sml(unsigned int ucfg_pcar_sml); +int iSetFQ_PCAR_CFG_cfg_pcar_opid(unsigned int ucfg_pcar_opid); +int iSetFQ_PCAR_CFG_cfg_pcar_inst(unsigned int ucfg_pcar_inst); +int iSetFQ_CNT5_fq_cnt5(unsigned int ufq_cnt5); +int iSetFQ_MOD_REG1_base_sub_pro_typ(unsigned int ubase_sub_pro_typ); +int iSetFQ_MOD_REG1_max_sub_pro_typ(unsigned int umax_sub_pro_typ); +int iSetFQ_MOD_REG1_cfg_pro_typ_nret_pkt(unsigned int ucfg_pro_typ_nret_pkt); +int iSetFQ_MOD_REG1_cfg_pro_typ_lb(unsigned int ucfg_pro_typ_lb); +int iSetFQ_MOD_REG1_cfg_th_fc_on(unsigned int ucfg_th_fc_on); +int iSetFQ_MOD_REG1_cfg_th_fc_dif(unsigned int ucfg_th_fc_dif); +int iSetFQ_MOD_REG1_cfg_th_fc_mode(unsigned int ucfg_th_fc_mode); +int iSetFQ_MOD_REG1_cfg_dsp_fstr_cup_en(unsigned int ucfg_dsp_fstr_cup_en); +int iSetFQ_MOD_REG1_cfg_dsp_fastlck_en(unsigned int ucfg_dsp_fastlck_en); +int iSetFQ_INNER_BP_ST_tmr_stf_bp(unsigned int utmr_stf_bp); +int iSetFQ_INNER_BP_ST_tmr_stl_bp(unsigned int utmr_stl_bp); +int iSetFQ_INNER_BP_ST_pro2cmd_bp(unsigned int upro2cmd_bp); +int iSetFQ_INNER_BP_ST_t2cup_bp(unsigned int ut2cup_bp); +int iSetFQ_INNER_BP_ST_fcam_pfh_bp(unsigned int ufcam_pfh_bp); +int iSetFQ_INNER_BP_ST_fq2smf_bp(unsigned int ufq2smf_bp); +int iSetFQ_INNER_BP_ST_smf2fq_dat_bp(unsigned int usmf2fq_dat_bp); +int iSetFQ_INNER_BP_ST_smf2fq_cmd_bp(unsigned int usmf2fq_cmd_bp); +int iSetFQ_INNER_BP_ST_rsc_qidx_bp(unsigned int ursc_qidx_bp); +int iSetFQ_INNER_BP_ST_rsc_fqg_bp(unsigned int ursc_fqg_bp); +int iSetFQ_INNER_BP_ST_rsc_lqp_bp(unsigned int ursc_lqp_bp); +int iSetFQ_INNER_BP_ST_t2fsg_rls_bp(unsigned int ut2fsg_rls_bp); +int iSetFQ_INNER_BP_ST_t2fsg_bp(unsigned int ut2fsg_bp); +int iSetFQ_INNER_BP_ST_t2rfl_bp(unsigned int ut2rfl_bp); +int iSetFQ_INNER_BP_ST_t2pfh_bp(unsigned int ut2pfh_bp); +int iSetFQ_INNER_BP_ST_rstg1_bp(unsigned int urstg1_bp); +int iSetFQ_INNER_BP_ST_rstg0_bp(unsigned int urstg0_bp); +int iSetFQ_INNER_BP_ST_fq2tl1_req_bp(unsigned int ufq2tl1_req_bp); +int iSetFQ_INNER_BP_ST_tl02fq_req_bp(unsigned int utl02fq_req_bp); +int iSetFQ_INNER_BP_ST_fq2tl1_rsp_bp(unsigned int ufq2tl1_rsp_bp); +int iSetFQ_INNER_BP_ST_fq2tl0_rsp_bp(unsigned int ufq2tl0_rsp_bp); +int iSetFQ_INNER_BP_ST_fq2pdm_dcc_bp(unsigned int ufq2pdm_dcc_bp); +int iSetFQ_INNER_BP_ST_fq2pdm_icc_bp(unsigned int ufq2pdm_icc_bp); +int iSetFQ_INNER_BP_ST_ritf_tcm_bp(unsigned int uritf_tcm_bp); +int iSetFQ_INNER_BP_ST_ritf_ord_bp(unsigned int uritf_ord_bp); +int iSetFQ_INNER_BP_ST_fq_psh_msg_bp(unsigned int ufq_psh_msg_bp); +int iSetFQ_INNER_BP_ST_fq2iq_lb_bp(unsigned int ufq2iq_lb_bp); +int iSetFQ_INNER_BP_ST_fq2oq_dsp_bp(unsigned int ufq2oq_dsp_bp); +int iSetFQ_INNER_BP_ST_fq2iq_bnd_bp(unsigned int ufq2iq_bnd_bp); +int iSetFQ_INNER_MON_ST_ctp(unsigned int uctp); +int iSetFQ_CNT6_fq_cnt6(unsigned int ufq_cnt6); +int iSetFQ_CNT_CTL1_fa_cnt1_reserved(unsigned int ufa_cnt1_reserved); +int iSetFQ_CNT_CTL1_cfg_typ_cnt9(unsigned int ucfg_typ_cnt9); +int iSetFQ_CNT_CTL1_cfg_cnt_1_en(unsigned int ucfg_cnt_1_en); +int iSetFQ_CNT7_fq_cnt7(unsigned int ufq_cnt7); +int iSetFQ_CNT8_fq_cnt8(unsigned int ufq_cnt8); +int iSetFQ_CNT9_fq_cnt9(unsigned int ufq_cnt9); +int iSetFQ_CNT10_fq_cnt10(unsigned int ufq_cnt10); +int iSetFQ_CNT11_fq_cnt11(unsigned int ufq_cnt11); +int iSetFQ_CNT12_fq_cnt12(unsigned int ufq_cnt12); +int iSetFQ_CNT13_fq_cnt13(unsigned int ufq_cnt13); +int iSetFQ_CNT14_fq_cnt14(unsigned int ufq_cnt14); +int iSetFQ_CNT15_fq_cnt15(unsigned int ufq_cnt15); +int iSetFQ_CNT16_fq_cnt16(unsigned int ufq_cnt16); +int iSetFQ_INT_MEM_ERR_1B_mem_err_1b_error_bit(unsigned int umem_err_1b_error_bit); +int iSetFQ_INT_MEM_ERR_1B_int_insrt10(unsigned int uint_insrt10); +int iSetFQ_INT_MEM_ERR_1B_mem_err_1b_sticky(unsigned int umem_err_1b_sticky); +int iSetCFG_STYP_TH_FC_EN_cfg_styp_th_fc_en(unsigned int ucfg_styp_th_fc_en); +int iSetCFG_ZERO_ESCH_LEN_cfg_zero_esch_len(unsigned int ucfg_zero_esch_len); +int iSetCFG_FQ_BUBBLE_CTL_cfg_fq_bubble_ctl(unsigned int ucfg_fq_bubble_ctl); +int iSetCFG_L2DCACHE_BUBBLE_CTL_cfg_l2dcache_bubble_ctl(unsigned int ucfg_l2dcache_bubble_ctl); +int iSetFQ_DEF_FQ_CTL_cfg_tx_base_init_def_fq(unsigned int ucfg_tx_base_init_def_fq); +int iSetFQ_DEF_FQ_CTL_cfg_tx_mode_init_def_fq(unsigned int ucfg_tx_mode_init_def_fq); +int iSetFQ_DEF_FQ_CTL_reserved2(unsigned int ureserved2); +int iSetFQ_DEF_FQ_CTL_cfg_rx_base_init_def_fq(unsigned int ucfg_rx_base_init_def_fq); +int iSetFQ_DEF_FQ_CTL_cfg_rx_mode_init_def_fq(unsigned int ucfg_rx_mode_init_def_fq); +int iSetFQ_DEF_FQ_CTL_reserved1(unsigned int ureserved1); +int iSetFQ_SMF_LDBCTL_fq_smf_ldb_ctl_vfen(unsigned int ufq_smf_ldb_ctl_vfen); +int iSetFQ_SMF_LDBCTL_fq_smf_ldb_ctl_ofst(unsigned int ufq_smf_ldb_ctl_ofst); +int iSetFQ_SMF_LDBCTL_fq_tmr_pro_typ_ctl(unsigned int ufq_tmr_pro_typ_ctl); +int iSetFQ_SMF_LDBCTL_fq_smf_only1_ctl(unsigned int ufq_smf_only1_ctl); +int iSetFQ_SMF_LDBCTL_fq_smf_lbctl_reserved1(unsigned int ufq_smf_lbctl_reserved1); +int iSetFQ_CFG_EP2HOST_H2_cfg_map_ep2host_h2(unsigned int ucfg_map_ep2host_h2); +int iSetFQ_CFG_EP2HOST_H2_cfg_map_ep2host_rsvd(unsigned int ucfg_map_ep2host_rsvd); +int iSetFQ_CFG_PREFETCH_CTL_fq_pfhctl_coco_xid20(unsigned int ufq_pfhctl_coco_xid20); +int iSetFQ_CFG_PREFETCH_CTL_fq_base_sub_pro_typ(unsigned int ufq_base_sub_pro_typ); +int iSetFQ_CFG_PREFETCH_CTL_fq_max_sub_pro_typ(unsigned int ufq_max_sub_pro_typ); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_nret_pkt(unsigned int ufq_cfg_pro_typ_nret_pkt); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_lb(unsigned int ufq_cfg_pro_typ_lb); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_lb_org(unsigned int ufq_cfg_pro_typ_lb_org); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_nret_org(unsigned int ufq_cfg_pro_typ_nret_org); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_prefetch_ctl_rsvd(unsigned int ufq_cfg_prefetch_ctl_rsvd); +int iSetFQ_LATENCY_CFG_csr_fq_sample_mode(unsigned int ucsr_fq_sample_mode); +int iSetFQ_LATENCY_CFG_csr_fq_spec_port_en(unsigned int ucsr_fq_spec_port_en); +int iSetFQ_LATENCY_CFG_csr_fq_done_clr(unsigned int ucsr_fq_done_clr); +int iSetFQ_LATENCY_CFG_csr_fq_spec_port_num(unsigned int ucsr_fq_spec_port_num); +int iSetFQ_LATENCY_CFG_csr_fq_spec_pptr_typ(unsigned int ucsr_fq_spec_pptr_typ); +int iSetFQ_LATENCY_STA_fq_csr_sample_done(unsigned int ufq_csr_sample_done); +int iSetFQ_SAMPLE_TMR_fq_csr_sample_tmr(unsigned int ufq_csr_sample_tmr); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_rsvd2(unsigned int ufq_fake_vfid_pf_rsvd2); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_start_bit(unsigned int ufq_fake_vfid_pf_start_bit); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_end_bit(unsigned int ufq_fake_vfid_pf_end_bit); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_rsvd1(unsigned int ufq_fake_vfid_pf_rsvd1); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bps_dly_dbld(unsigned int ufq_cfg_bps_dly_dbld); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bps_dly_fsg(unsigned int ufq_cfg_bps_dly_fsg); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bpsfsg_oeid_th(unsigned int ufq_cfg_bpsfsg_oeid_th); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bps_dly_rsvd(unsigned int ufq_cfg_bps_dly_rsvd); +int iSetFQ_CFG_OTSD_BASE_CTL_fq_cfg_otsd_base_ctl_val(unsigned int ufq_cfg_otsd_base_ctl_val); +int iSetFQ_CFG_OTSD_BASE_CTL_fq_cfg_otsd_base_ctl_rsvd(unsigned int ufq_cfg_otsd_base_ctl_rsvd); +int iSetFQ_CNT_CTL2_cfg_cnt_2_en(unsigned int ucfg_cnt_2_en); +int iSetFQ_CNT17_fq_cnt17(unsigned int ufq_cnt17); +int iSetFQ_CNT18_fq_cnt18(unsigned int ufq_cnt18); +int iSetFQ_CNT19_fq_cnt19(unsigned int ufq_cnt19); +int iSetFQ_CNT20_fq_cnt20(unsigned int ufq_cnt20); +int iSetFQ_CNT21_fq_cnt21(unsigned int ufq_cnt21); +int iSetFQ_CNT22_fq_cnt22(unsigned int ufq_cnt22); +int iSetFQ_CNT23_fq_cnt23(unsigned int ufq_cnt23); +int iSetFQ_CNT24_fq_cnt24(unsigned int ufq_cnt24); +int iSetFQ_CNT25_fq_cnt25(unsigned int ufq_cnt25); +int iSetFQ_CNT26_fq_cnt26(unsigned int ufq_cnt26); +int iSetFQ_CNT_CTL3_cfg_cnt_3_en(unsigned int ucfg_cnt_3_en); +int iSetFQ_CNT27_fq_cnt27(unsigned int ufq_cnt27); +int iSetFQ_CNT28_fq_cnt28(unsigned int ufq_cnt28); +int iSetFQ_CNT29_fq_cnt29(unsigned int ufq_cnt29); +int iSetFQ_CNT30_fq_cnt30(unsigned int ufq_cnt30); +int iSetFQ_CNT31_fq_cnt31(unsigned int ufq_cnt31); +int iSetFQ_CNT32_fq_cnt32(unsigned int ufq_cnt32); +int iSetFQ_CNT33_fq_cnt33(unsigned int ufq_cnt33); +int iSetFQ_CNT34_fq_cnt34(unsigned int ufq_cnt34); +int iSetFQ_CNT35_fq_cnt35(unsigned int ufq_cnt35); +int iSetFQ_CNT36_fq_cnt36(unsigned int ufq_cnt36); +int iSetFQ_CNT_CTL4_cfg_cnt_4_en(unsigned int ucfg_cnt_4_en); +int iSetFQ_CNT37_fq_cnt37(unsigned int ufq_cnt37); +int iSetFQ_CNT38_fq_cnt38(unsigned int ufq_cnt38); +int iSetFQ_CNT39_fq_cnt39(unsigned int ufq_cnt39); +int iSetFQ_CNT40_fq_cnt40(unsigned int ufq_cnt40); +int iSetFQ_CNT41_fq_cnt41(unsigned int ufq_cnt41); +int iSetFQ_CNT42_fq_cnt42(unsigned int ufq_cnt42); +int iSetFQ_CNT43_fq_cnt43(unsigned int ufq_cnt43); +int iSetFQ_CNT44_fq_cnt44(unsigned int ufq_cnt44); +int iSetFQ_CNT45_fq_cnt45(unsigned int ufq_cnt45); +int iSetFQ_CNT46_fq_cnt46(unsigned int ufq_cnt46); +int iSetFQ_QU2SMF_TMR_DLY_fq_qu2smf_tmr_dly_val(unsigned int ufq_qu2smf_tmr_dly_val); +int iSetFQ_QU2SMF_TMR_DLY_fq_qu2smf_tmr_dly_op(unsigned int ufq_qu2smf_tmr_dly_op); +int iSetFQ_MAGIC_BOX_CTL_fq_mgbx_quf_pg(unsigned int ufq_mgbx_quf_pg); +int iSetFQ_MAGIC_BOX_CTL_fq_mgbx_smf_pg(unsigned int ufq_mgbx_smf_pg); +int iSetFQ_MAGIC_BOX_CTL_fq_mgbx_lbf_mode(unsigned int ufq_mgbx_lbf_mode); +int iSetFQ_MGBX_SRV2HASH_fq_mgbx_srv2hash(unsigned int ufq_mgbx_srv2hash); +int iSetFQ_INNER_MON_ST1_fq_inner_mon_st1(unsigned int ufq_inner_mon_st1); +int iSetFQ_INNER_MON_ST2_fq_inner_mon_st2(unsigned int ufq_inner_mon_st2); +int iSetFQ_INNER_MON_ST3_fq_inner_mon_st3(unsigned int ufq_inner_mon_st3); +int iSetFQ_INNER_MON_ST4_fq_inner_mon_st4(unsigned int ufq_inner_mon_st4); +int iSetFQ_INNER_MON_ST5_fq_inner_mon_st5(unsigned int ufq_inner_mon_st5); +int iSetFQ_INNER_MON_ST6_fq_inner_mon_st6(unsigned int ufq_inner_mon_st6); +int iSetFQ_INNER_MON_ST7_fq_inner_mon_st7(unsigned int ufq_inner_mon_st7); +int iSetFQ_INNER_MON_ST8_fq_inner_mon_st8(unsigned int ufq_inner_mon_st8); +int iSetFQ_INNER_MON_ST9_fq_inner_mon_st9(unsigned int ufq_inner_mon_st9); +int iSetFQ_INNER_MON_ST10_fq_inner_mon_st10(unsigned int ufq_inner_mon_st10); +int iSetFQ_INNER_MON_ST11_fq_inner_mon_st11(unsigned int ufq_inner_mon_st11); +int iSetFQ_INNER_MON_ST12_fq_inner_mon_st12(unsigned int ufq_inner_mon_st12); +int iSetFQ_INNER_MON_ST13_fq_inner_mon_st13(unsigned int ufq_inner_mon_st13); +int iSetFQ_INNER_MON_ST14_fq_inner_mon_st14(unsigned int ufq_inner_mon_st14); +int iSetFQ_INNER_MON_ST15_fq_inner_mon_st15(unsigned int ufq_inner_mon_st15); +int iSetFQ_INNER_MON_ST16_fq_inner_mon_st16(unsigned int ufq_inner_mon_st16); +int iSetFQ_INNER_MON_ST17_fq_inner_mon_st17(unsigned int ufq_inner_mon_st17); +int iSetFQ_INNER_MON_ST18_fq_inner_mon_st18(unsigned int ufq_inner_mon_st18); +int iSetFQ_INNER_MON_ST19_fq_inner_mon_st19(unsigned int ufq_inner_mon_st19); +int iSetFQ_INNER_MON_ST20_fq_inner_mon_st20(unsigned int ufq_inner_mon_st20); +int iSetFQ_INNER_MON_ST21_fq_inner_mon_st21(unsigned int ufq_inner_mon_st21); +int iSetFQ_INNER_MON_ST22_fq_inner_mon_st22(unsigned int ufq_inner_mon_st22); +int iSetFQ_INNER_MON_ST23_fq_inner_mon_st23(unsigned int ufq_inner_mon_st23); +int iSetFQ_INNER_MON_ST24_fq_inner_mon_st24(unsigned int ufq_inner_mon_st24); +int iSetFQ_INNER_MON_ST25_fq_inner_mon_st25(unsigned int ufq_inner_mon_st25); +int iSetFQ_INNER_MON_ST26_fq_inner_mon_st26(unsigned int ufq_inner_mon_st26); +int iSetFQ_INNER_MON_ST27_fq_inner_mon_st27(unsigned int ufq_inner_mon_st27); +int iSetFQ_INNER_MON_ST28_fq_inner_mon_st28(unsigned int ufq_inner_mon_st28); +int iSetFQ_INNER_MON_ST29_fq_inner_mon_st29(unsigned int ufq_inner_mon_st29); +int iSetFQ_INNER_MON_ST30_fq_inner_mon_st30(unsigned int ufq_inner_mon_st30); +int iSetFQ_INNER_MON_ST31_fq_inner_mon_st31(unsigned int ufq_inner_mon_st31); +int iSetFQ_INNER_MON_ST32_fq_inner_mon_st32(unsigned int ufq_inner_mon_st32); +int iSetFQ_INNER_MON_ST33_fq_inner_mon_st33(unsigned int ufq_inner_mon_st33); +int iSetFQ_INNER_MON_ST34_fq_inner_mon_st34(unsigned int ufq_inner_mon_st34); +int iSetFQ_INNER_MON_ST35_fq_inner_mon_st35(unsigned int ufq_inner_mon_st35); +int iSetFQ_INNER_MON_ST36_fq_inner_mon_st36(unsigned int ufq_inner_mon_st36); +int iSetFQ_INNER_MON_ST37_fq_inner_mon_st37(unsigned int ufq_inner_mon_st37); +int iSetFQ_INNER_MON_ST38_fq_inner_mon_st38(unsigned int ufq_inner_mon_st38); +int iSetFQ_INNER_MON_ST39_fq_inner_mon_st39(unsigned int ufq_inner_mon_st39); +int iSetFQ_INNER_MON_ST40_fq_inner_mon_st40(unsigned int ufq_inner_mon_st40); +int iSetFQ_INNER_MON_ST41_fq_inner_mon_st41(unsigned int ufq_inner_mon_st41); +int iSetFQ_INNER_MON_ST42_fq_inner_mon_st42(unsigned int ufq_inner_mon_st42); +int iSetFQ_INNER_MON_ST43_fq_inner_mon_st43(unsigned int ufq_inner_mon_st43); +int iSetFQ_INNER_MON_ST44_fq_inner_mon_st44(unsigned int ufq_inner_mon_st44); +int iSetFQ_INNER_MON_ST45_fq_inner_mon_st45(unsigned int ufq_inner_mon_st45); +int iSetFQ_INNER_MON_ST46_fq_inner_mon_st46(unsigned int ufq_inner_mon_st46); +int iSetFQ_INNER_MON_ST47_fq_inner_mon_st47(unsigned int ufq_inner_mon_st47); +int iSetFQ_INNER_MON_ST48_fq_inner_mon_st48(unsigned int ufq_inner_mon_st48); +int iSetFQ_CNT47_fq_cnt47(unsigned int ufq_cnt47); +int iSetFQ_ROU_RQST_FIFO0_rou_rqst_fifo_st0(unsigned int urou_rqst_fifo_st0); +int iSetFQ_ROU_RQST_FIFO0_rou_rqst_i_ae_th0(unsigned int urou_rqst_i_ae_th0); +int iSetFQ_ROU_RQST_FIFO0_rou_rqst_i_af_th0(unsigned int urou_rqst_i_af_th0); +int iSetFQ_ROU_RSP_FIFO0_rou_rsp_fifo_st0(unsigned int urou_rsp_fifo_st0); +int iSetFQ_ROU_RSP_FIFO0_rou_rsp_i_ae_th0(unsigned int urou_rsp_i_ae_th0); +int iSetFQ_ROU_RSP_FIFO0_rou_rsp_i_af_th0(unsigned int urou_rsp_i_af_th0); +int iSetFQ_ROU_RSP_FIFO1_rou_rsp_fifo_st1(unsigned int urou_rsp_fifo_st1); +int iSetFQ_ROU_RSP_FIFO1_rou_rsp_i_ae_th1(unsigned int urou_rsp_i_ae_th1); +int iSetFQ_ROU_RSP_FIFO1_rou_rsp_i_af_th1(unsigned int urou_rsp_i_af_th1); +int iSetFQ_ROU_TMRODR_FIFO0_rou_tmrodr_rqst0_fifo_st(unsigned int urou_tmrodr_rqst0_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO0_rou_tmrodr_rqst0_i_ae_th(unsigned int urou_tmrodr_rqst0_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO0_rou_tmrodr_rqst0_i_af_th(unsigned int urou_tmrodr_rqst0_i_af_th); +int iSetFQ_ROU_TMRODR_FIFO1_rou_tmrodr_rqst1_fifo_st(unsigned int urou_tmrodr_rqst1_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO1_rou_tmrodr_rqst1_i_ae_th(unsigned int urou_tmrodr_rqst1_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO1_rou_tmrodr_rqst1_i_af_th(unsigned int urou_tmrodr_rqst1_i_af_th); +int iSetFQ_ROU_TMRODR_FIFO2_rou_tmrodr_rqst2_fifo_st(unsigned int urou_tmrodr_rqst2_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO2_rou_tmrodr_rqst2_i_ae_th(unsigned int urou_tmrodr_rqst2_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO2_rou_tmrodr_rqst2_i_af_th(unsigned int urou_tmrodr_rqst2_i_af_th); +int iSetFQ_ROU_TMRODR_FIFO3_rou_tmrodr_rqst3_fifo_st(unsigned int urou_tmrodr_rqst3_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO3_rou_tmrodr_rqst3_i_ae_th(unsigned int urou_tmrodr_rqst3_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO3_rou_tmrodr_rqst3_i_af_th(unsigned int urou_tmrodr_rqst3_i_af_th); +int iSetFQ_RIN_RQST_FIFO_rin_rqst_fifo_st(unsigned int urin_rqst_fifo_st); +int iSetFQ_RIN_RQST_FIFO_rin_rqst_i_ae_th(unsigned int urin_rqst_i_ae_th); +int iSetFQ_RIN_RQST_FIFO_rin_rqst_i_af_th(unsigned int urin_rqst_i_af_th); +int iSetFQ_RIN_RSP_FIFO_rin_rsp_fifo_st(unsigned int urin_rsp_fifo_st); +int iSetFQ_RIN_RSP_FIFO_rin_rsp_i_ae_th(unsigned int urin_rsp_i_ae_th); +int iSetFQ_RIN_RSP_FIFO_rin_rsp_i_af_th(unsigned int urin_rsp_i_af_th); +int iSetFQ_SMF_RSP_FIFO0_smf_rsp0_fifo_st(unsigned int usmf_rsp0_fifo_st); +int iSetFQ_SMF_RSP_FIFO0_smf_rsp0_i_ae_th(unsigned int usmf_rsp0_i_ae_th); +int iSetFQ_SMF_RSP_FIFO0_smf_rsp0_i_af_th(unsigned int usmf_rsp0_i_af_th); +int iSetFQ_SMF_RSP_FIFO1_smf_rsp1_fifo_st(unsigned int usmf_rsp1_fifo_st); +int iSetFQ_SMF_RSP_FIFO1_smf_rsp1_i_ae_th(unsigned int usmf_rsp1_i_ae_th); +int iSetFQ_SMF_RSP_FIFO1_smf_rsp1_i_af_th(unsigned int usmf_rsp1_i_af_th); +int iSetFQ_TL0_CMD_FIFO0_tl0_cmd_fifo_st(unsigned int utl0_cmd_fifo_st); +int iSetFQ_TL0_CMD_FIFO0_tl0_cmd_i_ae_th(unsigned int utl0_cmd_i_ae_th); +int iSetFQ_TL0_CMD_FIFO0_tl0_cmd_i_af_th(unsigned int utl0_cmd_i_af_th); +int iSetFQ_TL0_EXTCMD_FIFO0_tl0_extcmd_fifo_st(unsigned int utl0_extcmd_fifo_st); +int iSetFQ_TL0_EXTCMD_FIFO0_tl0_extcmd_i_ae_th(unsigned int utl0_extcmd_i_ae_th); +int iSetFQ_TL0_EXTCMD_FIFO0_tl0_extcmd_i_af_th(unsigned int utl0_extcmd_i_af_th); +int iSetFQ_TL1_CMD_FIFO1_tl1_cmd_fifo_st(unsigned int utl1_cmd_fifo_st); +int iSetFQ_TL1_CMD_FIFO1_tl1_cmd_i_ae_th(unsigned int utl1_cmd_i_ae_th); +int iSetFQ_TL1_CMD_FIFO1_tl1_cmd_i_af_th(unsigned int utl1_cmd_i_af_th); +int iSetFQ_TL1_EXTCMD_FIFO0_tl1_extcmd_fifo_st(unsigned int utl1_extcmd_fifo_st); +int iSetFQ_TL1_EXTCMD_FIFO0_tl1_extcmd_i_ae_th(unsigned int utl1_extcmd_i_ae_th); +int iSetFQ_TL1_EXTCMD_FIFO0_tl1_extcmd_i_af_th(unsigned int utl1_extcmd_i_af_th); +int iSetFQ_FQ2OQ_FCNP_FIFO_fq2oq_fcnp_fifo_st(unsigned int ufq2oq_fcnp_fifo_st); +int iSetFQ_FQ2OQ_FCNP_FIFO_fq2oq_fcnp_i_ae_th(unsigned int ufq2oq_fcnp_i_ae_th); +int iSetFQ_FQ2OQ_FCNP_FIFO_fq2oq_fcnp_i_af_th(unsigned int ufq2oq_fcnp_i_af_th); +int iSetFQ_OQ2FQ_FCNP_FIFO_oq2fq_fcnp_fifo_st(unsigned int uoq2fq_fcnp_fifo_st); +int iSetFQ_OQ2FQ_FCNP_FIFO_oq2fq_fcnp_i_ae_th(unsigned int uoq2fq_fcnp_i_ae_th); +int iSetFQ_OQ2FQ_FCNP_FIFO_oq2fq_fcnp_i_af_th(unsigned int uoq2fq_fcnp_i_af_th); +int iSetFQ_TMR_RSP_FIFO0_tmr_rsp0_fifo_st(unsigned int utmr_rsp0_fifo_st); +int iSetFQ_TMR_RSP_FIFO0_tmr_rsp0_i_ae_th(unsigned int utmr_rsp0_i_ae_th); +int iSetFQ_TMR_RSP_FIFO0_tmr_rsp0_i_af_th(unsigned int utmr_rsp0_i_af_th); +int iSetFQ_TMR_RSP_FIFO1_tmr_rsp1_fifo_st(unsigned int utmr_rsp1_fifo_st); +int iSetFQ_TMR_RSP_FIFO1_tmr_rsp1_i_ae_th(unsigned int utmr_rsp1_i_ae_th); +int iSetFQ_TMR_RSP_FIFO1_tmr_rsp1_i_af_th(unsigned int utmr_rsp1_i_af_th); +int iSetFQ_TMR_RSP_FIFO2_tmr_rsp2_fifo_st(unsigned int utmr_rsp2_fifo_st); +int iSetFQ_TMR_RSP_FIFO2_tmr_rsp2_i_ae_th(unsigned int utmr_rsp2_i_ae_th); +int iSetFQ_TMR_RSP_FIFO2_tmr_rsp2_i_af_th(unsigned int utmr_rsp2_i_af_th); +int iSetFQ_TMR_RSP_FIFO3_tmr_rsp3_fifo_st(unsigned int utmr_rsp3_fifo_st); +int iSetFQ_TMR_RSP_FIFO3_tmr_rsp3_i_ae_th(unsigned int utmr_rsp3_i_ae_th); +int iSetFQ_TMR_RSP_FIFO3_tmr_rsp3_i_af_th(unsigned int utmr_rsp3_i_af_th); +int iSetFQ_TMR_RSP_FIFO4_tmr_rsp4_fifo_st(unsigned int utmr_rsp4_fifo_st); +int iSetFQ_TMR_RSP_FIFO4_tmr_rsp4_i_ae_th(unsigned int utmr_rsp4_i_ae_th); +int iSetFQ_TMR_RSP_FIFO4_tmr_rsp4_i_af_th(unsigned int utmr_rsp4_i_af_th); +int iSetFQ_TMR_RSP_FIFO5_tmr_rsp5_fifo_st(unsigned int utmr_rsp5_fifo_st); +int iSetFQ_TMR_RSP_FIFO5_tmr_rsp5_i_ae_th(unsigned int utmr_rsp5_i_ae_th); +int iSetFQ_TMR_RSP_FIFO5_tmr_rsp5_i_af_th(unsigned int utmr_rsp5_i_af_th); +int iSetFQ_TMR_RSP_FIFO6_tmr_rsp6_fifo_st(unsigned int utmr_rsp6_fifo_st); +int iSetFQ_TMR_RSP_FIFO6_tmr_rsp6_i_ae_th(unsigned int utmr_rsp6_i_ae_th); +int iSetFQ_TMR_RSP_FIFO6_tmr_rsp6_i_af_th(unsigned int utmr_rsp6_i_af_th); +int iSetFQ_TMR_RSP_FIFO7_tmr_rsp7_fifo_st(unsigned int utmr_rsp7_fifo_st); +int iSetFQ_TMR_RSP_FIFO7_tmr_rsp7_i_ae_th(unsigned int utmr_rsp7_i_ae_th); +int iSetFQ_TMR_RSP_FIFO7_tmr_rsp7_i_af_th(unsigned int utmr_rsp7_i_af_th); +int iSetFQ_TMR_RSP_FIFO8_tmr_rsp8_fifo_st(unsigned int utmr_rsp8_fifo_st); +int iSetFQ_TMR_RSP_FIFO8_tmr_rsp8_i_ae_th(unsigned int utmr_rsp8_i_ae_th); +int iSetFQ_TMR_RSP_FIFO8_tmr_rsp8_i_af_th(unsigned int utmr_rsp8_i_af_th); +int iSetFQ_TMR_RSP_FIFO9_tmr_rsp9_fifo_st(unsigned int utmr_rsp9_fifo_st); +int iSetFQ_TMR_RSP_FIFO9_tmr_rsp9_i_ae_th(unsigned int utmr_rsp9_i_ae_th); +int iSetFQ_TMR_RSP_FIFO9_tmr_rsp9_i_af_th(unsigned int utmr_rsp9_i_af_th); +int iSetFQ_TMR_RSP_FIFO10_tmr_rsp10_fifo_st(unsigned int utmr_rsp10_fifo_st); +int iSetFQ_TMR_RSP_FIFO10_tmr_rsp10_i_ae_th(unsigned int utmr_rsp10_i_ae_th); +int iSetFQ_TMR_RSP_FIFO10_tmr_rsp10_i_af_th(unsigned int utmr_rsp10_i_af_th); +int iSetFQ_TMR_RSP_FIFO11_tmr_rsp11_fifo_st(unsigned int utmr_rsp11_fifo_st); +int iSetFQ_TMR_RSP_FIFO11_tmr_rsp11_i_ae_th(unsigned int utmr_rsp11_i_ae_th); +int iSetFQ_TMR_RSP_FIFO11_tmr_rsp11_i_af_th(unsigned int utmr_rsp11_i_af_th); +int iSetFQ_TMR_RSP_FIFO12_tmr_rsp12_fifo_st(unsigned int utmr_rsp12_fifo_st); +int iSetFQ_TMR_RSP_FIFO12_tmr_rsp12_i_ae_th(unsigned int utmr_rsp12_i_ae_th); +int iSetFQ_TMR_RSP_FIFO12_tmr_rsp12_i_af_th(unsigned int utmr_rsp12_i_af_th); +int iSetFQ_TMR_RSP_FIFO13_tmr_rsp13_fifo_st(unsigned int utmr_rsp13_fifo_st); +int iSetFQ_TMR_RSP_FIFO13_tmr_rsp13_i_ae_th(unsigned int utmr_rsp13_i_ae_th); +int iSetFQ_TMR_RSP_FIFO13_tmr_rsp13_i_af_th(unsigned int utmr_rsp13_i_af_th); +int iSetFQ_TMR_RSP_FIFO14_tmr_rsp14_fifo_st(unsigned int utmr_rsp14_fifo_st); +int iSetFQ_TMR_RSP_FIFO14_tmr_rsp14_i_ae_th(unsigned int utmr_rsp14_i_ae_th); +int iSetFQ_TMR_RSP_FIFO14_tmr_rsp14_i_af_th(unsigned int utmr_rsp14_i_af_th); +int iSetFQ_TMR_RSP_FIFO15_tmr_rsp15_fifo_st(unsigned int utmr_rsp15_fifo_st); +int iSetFQ_TMR_RSP_FIFO15_tmr_rsp15_i_ae_th(unsigned int utmr_rsp15_i_ae_th); +int iSetFQ_TMR_RSP_FIFO15_tmr_rsp15_i_af_th(unsigned int utmr_rsp15_i_af_th); +int iSetFQ_INT_RIN_RQST_ERR_fq_rin_rqst_err(unsigned int ufq_rin_rqst_err); +int iSetFQ_INT_RIN_RQST_ERR_int_insrt11(unsigned int uint_insrt11); +int iSetFQ_INT_RIN_RQST_ERR_fq_rin_rqst_err_sticky(unsigned int ufq_rin_rqst_err_sticky); +int iSetFQ_INT_RIN_RSP_ERR_fq_rin_rsp_err(unsigned int ufq_rin_rsp_err); +int iSetFQ_INT_RIN_RSP_ERR_int_insrt12(unsigned int uint_insrt12); +int iSetFQ_INT_RIN_RSP_ERR_fq_rin_rsp_err_sticky(unsigned int ufq_rin_rsp_err_sticky); +int iSetFQ_INT_RIN_TRSP_ERR_fq_rin_trsp_err(unsigned int ufq_rin_trsp_err); +int iSetFQ_INT_RIN_TRSP_ERR_int_insrt13(unsigned int uint_insrt13); +int iSetFQ_INT_RIN_TRSP_ERR_fq_rin_trsp_err_sticky(unsigned int ufq_rin_trsp_err_sticky); +int iSetFQ_INT_FIFO1_ERR_fq_fifo1_err(unsigned int ufq_fifo1_err); +int iSetFQ_INT_FIFO1_ERR_int_insrt14(unsigned int uint_insrt14); +int iSetFQ_INT_FIFO1_ERR_fq_fifo1_err_sticky(unsigned int ufq_fifo1_err_sticky); +int iSetFQ_INT_FIFO2_ERR_fq_fifo2_err(unsigned int ufq_fifo2_err); +int iSetFQ_INT_FIFO2_ERR_int_insrt15(unsigned int uint_insrt15); +int iSetFQ_INT_FIFO2_ERR_fq_fifo2_err_sticky(unsigned int ufq_fifo2_err_sticky); +int iSetFQ_CNT48_fq_cnt48(unsigned int ufq_cnt48); +int iSetFQ_CFG_STG_QP_PUSH0_fq_cfg_stg_qp_push0(unsigned int ufq_cfg_stg_qp_push0); +int iSetFQ_CFG_STG_QP_PUSH1_fq_cfg_stg_qp_push1(unsigned int ufq_cfg_stg_qp_push1); +int iSetFQ_CFG_STG_QP_PUSH2_fq_cfg_stg_qp_push2(unsigned int ufq_cfg_stg_qp_push2); +int iSetFQ_DBE_HW_WQE_EN1_cfg_dbe_hw_wqe_en1(unsigned int ucfg_dbe_hw_wqe_en1); +int iSetFQ_DBE_HW_WQE_EN2_cfg_dbe_hw_wqe_en2(unsigned int ucfg_dbe_hw_wqe_en2); +int iSetFQ_DBE_HW_WQE_EN3_cfg_dbe_hw_wqe_en3(unsigned int ucfg_dbe_hw_wqe_en3); +int iSetFQ_DBE_HW_WQE_EN4_cfg_dbe_hw_wqe_en4(unsigned int ucfg_dbe_hw_wqe_en4); +int iSetFQ_DBE_HW_WQE_EN5_cfg_dbe_hw_wqe_en5(unsigned int ucfg_dbe_hw_wqe_en5); +int iSetFQ_DBE_HW_WQE_EN6_cfg_dbe_hw_wqe_en6(unsigned int ucfg_dbe_hw_wqe_en6); +int iSetFQ_DBE_HW_WQE_EN7_cfg_dbe_hw_wqe_en7(unsigned int ucfg_dbe_hw_wqe_en7); +int iSetFQ_DBE_HW_WQE_EN8_cfg_dbe_hw_wqe_en8(unsigned int ucfg_dbe_hw_wqe_en8); +int iSetFQ_DBE_HW_WQE_EN9_cfg_dbe_hw_wqe_en9(unsigned int ucfg_dbe_hw_wqe_en9); +int iSetFQ_DBE_HW_WQE_EN10_cfg_dbe_hw_wqe_en10(unsigned int ucfg_dbe_hw_wqe_en10); +int iSetFQ_DBE_HW_WQE_EN11_cfg_dbe_hw_wqe_en11(unsigned int ucfg_dbe_hw_wqe_en11); +int iSetFQ_DBE_HW_WQE_EN12_cfg_dbe_hw_wqe_en12(unsigned int ucfg_dbe_hw_wqe_en12); +int iSetFQ_DBE_HW_WQE_EN13_cfg_dbe_hw_wqe_en13(unsigned int ucfg_dbe_hw_wqe_en13); +int iSetFQ_DBE_HW_WQE_EN14_cfg_dbe_hw_wqe_en14(unsigned int ucfg_dbe_hw_wqe_en14); +int iSetFQ_DBE_HW_WQE_EN15_cfg_dbe_hw_wqe_en15(unsigned int ucfg_dbe_hw_wqe_en15); +int iSetFQ_CNT49_fq_cnt49(unsigned int ufq_cnt49); +int iSetFQ_CNT50_fq_cnt50(unsigned int ufq_cnt50); +int iSetFQ_CNT51_fq_cnt51(unsigned int ufq_cnt51); +int iSetFQ_CNT52_fq_cnt52(unsigned int ufq_cnt52); +int iSetFQ_CNT53_fq_cnt53(unsigned int ufq_cnt53); +int iSetFQ_CNT54_fq_cnt54(unsigned int ufq_cnt54); +int iSetFQ_CNT55_fq_cnt55(unsigned int ufq_cnt55); +int iSetFQ_CNT56_fq_cnt56(unsigned int ufq_cnt56); +int iSetFQ_CNT57_fq_cnt57(unsigned int ufq_cnt57); +int iSetFQ_CNT58_fq_cnt58(unsigned int ufq_cnt58); +int iSetFQ_CNT59_fq_cnt59(unsigned int ufq_cnt59); +int iSetFQ_CNT60_fq_cnt60(unsigned int ufq_cnt60); +int iSetFQ_CNT61_fq_cnt61(unsigned int ufq_cnt61); +int iSetFQ_CNT62_fq_cnt62(unsigned int ufq_cnt62); +int iSetFQ_CNT63_fq_cnt63(unsigned int ufq_cnt63); +int iSetFQ_CNT64_fq_cnt64(unsigned int ufq_cnt64); +int iSetFQ_CNT65_fq_cnt65(unsigned int ufq_cnt65); +int iSetFQ_CNT66_fq_cnt66(unsigned int ufq_cnt66); +int iSetFQ_CNT67_fq_cnt67(unsigned int ufq_cnt67); +int iSetFQ_CNT68_fq_cnt68(unsigned int ufq_cnt68); +int iSetFQ_CNT69_fq_cnt69(unsigned int ufq_cnt69); +int iSetFQ_CNT70_fq_cnt70(unsigned int ufq_cnt70); +int iSetFQ_CNT71_fq_cnt71(unsigned int ufq_cnt71); +int iSetFQ_CNT72_fq_cnt72(unsigned int ufq_cnt72); +int iSetFQ_CNT73_fq_cnt73(unsigned int ufq_cnt73); +int iSetFQ_CNT74_fq_cnt74(unsigned int ufq_cnt74); +int iSetFQ_CNT75_fq_cnt75(unsigned int ufq_cnt75); +int iSetFQ_CNT76_fq_cnt76(unsigned int ufq_cnt76); +int iSetFQ_CNT77_fq_cnt77(unsigned int ufq_cnt77); +int iSetFQ_CNT78_fq_cnt78(unsigned int ufq_cnt78); +int iSetFQ_CNT79_fq_cnt79(unsigned int ufq_cnt79); +int iSetFQ_CNT80_fq_cnt80(unsigned int ufq_cnt80); +int iSetFQ_CNT81_fq_cnt81(unsigned int ufq_cnt81); +int iSetFQ_CNT82_fq_cnt82(unsigned int ufq_cnt82); +int iSetFQ_CNT83_fq_cnt83(unsigned int ufq_cnt83); +int iSetFQ_CNT84_fq_cnt84(unsigned int ufq_cnt84); +int iSetFQ_CNT85_fq_cnt85(unsigned int ufq_cnt85); +int iSetFQ_CNT86_fq_cnt86(unsigned int ufq_cnt86); +int iSetFQ_CNT87_fq_cnt87(unsigned int ufq_cnt87); +int iSetFQ_CNT88_fq_cnt88(unsigned int ufq_cnt88); +int iSetFQ_CNT89_fq_cnt89(unsigned int ufq_cnt89); +int iSetFQ_CNT90_fq_cnt90(unsigned int ufq_cnt90); +int iSetFQ_CNT91_fq_cnt91(unsigned int ufq_cnt91); +int iSetFQ_CNT92_fq_cnt92(unsigned int ufq_cnt92); +int iSetFQ_CNT93_fq_cnt93(unsigned int ufq_cnt93); +int iSetFQ_CNT94_fq_cnt94(unsigned int ufq_cnt94); +int iSetFQ_CNT95_fq_cnt95(unsigned int ufq_cnt95); +int iSetFQ_CNT96_fq_cnt96(unsigned int ufq_cnt96); +int iSetFQ_CNT97_fq_cnt97(unsigned int ufq_cnt97); +int iSetFQ_CNT98_fq_cnt98(unsigned int ufq_cnt98); +int iSetFQ_CNT99_fq_cnt99(unsigned int ufq_cnt99); +int iSetFQ_CNT100_fq_cnt100(unsigned int ufq_cnt100); +int iSetFQ_CNT101_fq_cnt101(unsigned int ufq_cnt101); +int iSetFQ_CNT102_fq_cnt102(unsigned int ufq_cnt102); +int iSetFQ_CNT103_fq_cnt103(unsigned int ufq_cnt103); +int iSetFQ_CNT104_fq_cnt104(unsigned int ufq_cnt104); +int iSetFQ_CNT105_fq_cnt105(unsigned int ufq_cnt105); +int iSetFQ_CNT106_fq_cnt106(unsigned int ufq_cnt106); +int iSetFQ_CNT107_fq_cnt107(unsigned int ufq_cnt107); +int iSetFQ_CNT108_fq_cnt108(unsigned int ufq_cnt108); +int iSetFQ_CNT109_fq_cnt109(unsigned int ufq_cnt109); +int iSetFQ_CNT110_fq_cnt110(unsigned int ufq_cnt110); +int iSetFQ_CNT111_fq_cnt111(unsigned int ufq_cnt111); +int iSetFQ_CNT112_fq_cnt112(unsigned int ufq_cnt112); +int iSetFQ_CNT113_fq_cnt113(unsigned int ufq_cnt113); +int iSetFQ_CNT114_fq_cnt114(unsigned int ufq_cnt114); +int iSetFQ_CNT115_fq_cnt115(unsigned int ufq_cnt115); +int iSetFQ_CNT116_fq_cnt116(unsigned int ufq_cnt116); +int iSetFQ_CNT117_fq_cnt117(unsigned int ufq_cnt117); +int iSetFQ_CNT118_fq_cnt118(unsigned int ufq_cnt118); +int iSetFQ_CNT119_fq_cnt119(unsigned int ufq_cnt119); +int iSetFQ_CNT120_fq_cnt120(unsigned int ufq_cnt120); +int iSetFQ_CNT121_fq_cnt121(unsigned int ufq_cnt121); +int iSetFQ_CNT122_fq_cnt122(unsigned int ufq_cnt122); +int iSetFQ_CNT123_fq_cnt123(unsigned int ufq_cnt123); +int iSetFQ_CNT124_fq_cnt124(unsigned int ufq_cnt124); +int iSetFQ_CNT125_fq_cnt125(unsigned int ufq_cnt125); +int iSetFQ_CNT126_fq_cnt126(unsigned int ufq_cnt126); +int iSetFQ_CNT127_fq_cnt127(unsigned int ufq_cnt127); +int iSetFQ_CNT128_fq_cnt128(unsigned int ufq_cnt128); +int iSetFQ_CNT129_fq_cnt129(unsigned int ufq_cnt129); +int iSetFQ_CNT130_fq_cnt130(unsigned int ufq_cnt130); +int iSetFQ_CNT131_fq_cnt131(unsigned int ufq_cnt131); +int iSetFQ_CNT132_fq_cnt132(unsigned int ufq_cnt132); +int iSetFQ_CNT133_fq_cnt133(unsigned int ufq_cnt133); +int iSetFQ_CNT134_fq_cnt134(unsigned int ufq_cnt134); +int iSetFQ_CNT135_fq_cnt135(unsigned int ufq_cnt135); +int iSetFQ_CNT136_fq_cnt136(unsigned int ufq_cnt136); +int iSetFQ_CNT137_fq_cnt137(unsigned int ufq_cnt137); +int iSetFQ_CNT138_fq_cnt138(unsigned int ufq_cnt138); +int iSetFQ_CNT139_fq_cnt139(unsigned int ufq_cnt139); +int iSetFQ_CNT140_fq_cnt140(unsigned int ufq_cnt140); +int iSetFQ_CNT141_fq_cnt141(unsigned int ufq_cnt141); +int iSetFQ_CNT142_fq_cnt142(unsigned int ufq_cnt142); +int iSetFQ_CNT143_fq_cnt143(unsigned int ufq_cnt143); +int iSetFQ_CNT144_fq_cnt144(unsigned int ufq_cnt144); +int iSetFQ_CNT145_fq_cnt145(unsigned int ufq_cnt145); +int iSetFQ_CNT146_fq_cnt146(unsigned int ufq_cnt146); +int iSetFQ_CNT147_fq_cnt147(unsigned int ufq_cnt147); +int iSetFQ_CNT148_fq_cnt148(unsigned int ufq_cnt148); +int iSetFQ_CNT149_fq_cnt149(unsigned int ufq_cnt149); +int iSetFQ_CNT150_fq_cnt150(unsigned int ufq_cnt150); +int iSetFQ_CNT151_fq_cnt151(unsigned int ufq_cnt151); +int iSetFQ_CNT152_fq_cnt152(unsigned int ufq_cnt152); +int iSetFQ_CNT153_fq_cnt153(unsigned int ufq_cnt153); +int iSetFQ_CNT154_fq_cnt154(unsigned int ufq_cnt154); +int iSetFQ_CNT155_fq_cnt155(unsigned int ufq_cnt155); +int iSetFQ_CNT156_fq_cnt156(unsigned int ufq_cnt156); +int iSetFQ_CNT157_fq_cnt157(unsigned int ufq_cnt157); +int iSetFQ_CNT158_fq_cnt158(unsigned int ufq_cnt158); +int iSetFQ_CNT159_fq_cnt159(unsigned int ufq_cnt159); +int iSetFQ_CNT160_fq_cnt160(unsigned int ufq_cnt160); +int iSetFQ_CNT161_fq_cnt161(unsigned int ufq_cnt161); +int iSetFQ_CNT162_fq_cnt162(unsigned int ufq_cnt162); +int iSetFQ_CNT163_fq_cnt163(unsigned int ufq_cnt163); +int iSetFQ_CNT164_fq_cnt164(unsigned int ufq_cnt164); +int iSetFQ_CNT165_fq_cnt165(unsigned int ufq_cnt165); +int iSetFQ_CNT166_fq_cnt166(unsigned int ufq_cnt166); +int iSetFQ_CNT167_fq_cnt167(unsigned int ufq_cnt167); +int iSetFQ_CNT168_fq_cnt168(unsigned int ufq_cnt168); +int iSetFQ_CNT169_fq_cnt169(unsigned int ufq_cnt169); +int iSetFQ_CNT170_fq_cnt170(unsigned int ufq_cnt170); +int iSetFQ_CNT171_fq_cnt171(unsigned int ufq_cnt171); +int iSetFQ_CNT172_fq_cnt172(unsigned int ufq_cnt172); +int iSetFQ_CNT173_fq_cnt173(unsigned int ufq_cnt173); +int iSetFQ_CNT174_fq_cnt174(unsigned int ufq_cnt174); +int iSetFQ_CNT175_fq_cnt175(unsigned int ufq_cnt175); +int iSetFQ_CNT176_fq_cnt176(unsigned int ufq_cnt176); +int iSetFQ_CNT177_fq_cnt177(unsigned int ufq_cnt177); +int iSetFQ_CNT178_fq_cnt178(unsigned int ufq_cnt178); +int iSetFQ_CNT179_fq_cnt179(unsigned int ufq_cnt179); +int iSetFQ_CNT180_fq_cnt180(unsigned int ufq_cnt180); +int iSetFQ_CNT181_fq_cnt181(unsigned int ufq_cnt181); +int iSetFQ_CNT182_fq_cnt182(unsigned int ufq_cnt182); +int iSetFQ_CNT183_fq_cnt183(unsigned int ufq_cnt183); +int iSetFQ_CNT184_fq_cnt184(unsigned int ufq_cnt184); +int iSetFQ_CNT185_fq_cnt185(unsigned int ufq_cnt185); +int iSetFQ_CNT186_fq_cnt186(unsigned int ufq_cnt186); +int iSetFQ_CNT187_fq_cnt187(unsigned int ufq_cnt187); +int iSetFQ_CNT188_fq_cnt188(unsigned int ufq_cnt188); +int iSetFQ_CNT189_fq_cnt189(unsigned int ufq_cnt189); +int iSetFQ_CNT190_fq_cnt190(unsigned int ufq_cnt190); +int iSetFQ_CNT191_fq_cnt191(unsigned int ufq_cnt191); +int iSetFQ_CNT192_fq_cnt192(unsigned int ufq_cnt192); +int iSetFQ_CNT193_fq_cnt193(unsigned int ufq_cnt193); +int iSetFQ_CNT194_fq_cnt194(unsigned int ufq_cnt194); +int iSetFQ_CNT195_fq_cnt195(unsigned int ufq_cnt195); +int iSetFQ_CNT196_fq_cnt196(unsigned int ufq_cnt196); +int iSetFQ_CNT197_fq_cnt197(unsigned int ufq_cnt197); +int iSetFQ_CNT198_fq_cnt198(unsigned int ufq_cnt198); +int iSetFQ_CNT199_fq_cnt199(unsigned int ufq_cnt199); +int iSetFQ_CNT200_fq_cnt200(unsigned int ufq_cnt200); +int iSetFQ_CNT201_fq_cnt201(unsigned int ufq_cnt201); +int iSetFQ_CNT202_fq_cnt202(unsigned int ufq_cnt202); +int iSetFQ_CNT203_fq_cnt203(unsigned int ufq_cnt203); +int iSetFQ_CNT204_fq_cnt204(unsigned int ufq_cnt204); +int iSetFQ_CNT205_fq_cnt205(unsigned int ufq_cnt205); +int iSetFQ_CNT206_fq_cnt206(unsigned int ufq_cnt206); +int iSetFQ_CNT207_fq_cnt207(unsigned int ufq_cnt207); +int iSetFQ_CNT208_fq_cnt208(unsigned int ufq_cnt208); +int iSetFQ_CNT209_fq_cnt209(unsigned int ufq_cnt209); +int iSetFQ_CNT210_fq_cnt210(unsigned int ufq_cnt210); +int iSetFQ_CNT211_fq_cnt211(unsigned int ufq_cnt211); +int iSetFQ_CNT212_fq_cnt212(unsigned int ufq_cnt212); +int iSetFQ_CNT213_fq_cnt213(unsigned int ufq_cnt213); +int iSetFQ_CNT214_fq_cnt214(unsigned int ufq_cnt214); +int iSetFQ_CNT215_fq_cnt215(unsigned int ufq_cnt215); +int iSetFQ_CNT216_fq_cnt216(unsigned int ufq_cnt216); +int iSetFQ_CNT217_fq_cnt217(unsigned int ufq_cnt217); +int iSetFQ_CNT218_fq_cnt218(unsigned int ufq_cnt218); +int iSetFQ_CNT219_fq_cnt219(unsigned int ufq_cnt219); +int iSetFQ_CNT220_fq_cnt220(unsigned int ufq_cnt220); +int iSetFQ_CNT221_fq_cnt221(unsigned int ufq_cnt221); +int iSetFQ_CNT222_fq_cnt222(unsigned int ufq_cnt222); +int iSetFQ_CNT223_fq_cnt223(unsigned int ufq_cnt223); +int iSetFQ_CNT224_fq_cnt224(unsigned int ufq_cnt224); +int iSetFQ_RXPSH_CID_CTL_cfg_fq_rxpsh_cid_ctl(unsigned int ucfg_fq_rxpsh_cid_ctl); +int iSetFQ_ROCE_DB_ODR_CTL1_cfg_fq_roce_db_odr_ctl1(unsigned int ucfg_fq_roce_db_odr_ctl1); +int iSetFQ_ROCE_DB_ODR_CTL2_cfg_fq_roce_db_odr_ctl2(unsigned int ucfg_fq_roce_db_odr_ctl2); +int iSetFQ_NORM_NIC_ODR_CTL1_cfg_fq_norm_nic_odr_ctl1(unsigned int ucfg_fq_norm_nic_odr_ctl1); +int iSetFQ_NORM_NIC_ODR_CTL2_cfg_fq_norm_nic_odr_ctl2(unsigned int ucfg_fq_norm_nic_odr_ctl2); +int iSetFQ_ODR_FLIT256_CTL1_cfg_fq_odr_flit256_ctl1(unsigned int ucfg_fq_odr_flit256_ctl1); +int iSetFQ_ODR_FLIT256_CTL2_cfg_fq_odr_flit256_ctl2(unsigned int ucfg_fq_odr_flit256_ctl2); +int iSetFQ_ODR_FLIT256_CTL3_cfg_fq_odr_flit256_ctl3(unsigned int ucfg_fq_odr_flit256_ctl3); +int iSetFQ_ODR_FLIT256_CTL4_cfg_fq_odr_flit256_ctl4(unsigned int ucfg_fq_odr_flit256_ctl4); +int iSetFQ_ODR_STYPE_CID2QID_EN_cfg_fq_odr_stype_cid2qid_en(unsigned int ucfg_fq_odr_stype_cid2qid_en); +int iSetFQ_CNT225_fq_cnt225(unsigned int ufq_cnt225); +int iSetFQ_CNT226_fq_cnt226(unsigned int ufq_cnt226); +int iSetFQ_CNT227_fq_cnt227(unsigned int ufq_cnt227); +int iSetFQ_CNT228_fq_cnt228(unsigned int ufq_cnt228); +int iSetFQ_CNT229_fq_cnt229(unsigned int ufq_cnt229); +int iSetFQ_CNT230_fq_cnt230(unsigned int ufq_cnt230); +int iSetFQ_CNT231_fq_cnt231(unsigned int ufq_cnt231); +int iSetFQ_CNT232_fq_cnt232(unsigned int ufq_cnt232); +int iSetFQ_CNT233_fq_cnt233(unsigned int ufq_cnt233); +int iSetFQ_CNT234_fq_cnt234(unsigned int ufq_cnt234); +int iSetFQ_CNT235_fq_cnt235(unsigned int ufq_cnt235); +int iSetFQ_CNT236_fq_cnt236(unsigned int ufq_cnt236); +int iSetFQ_CNT237_fq_cnt237(unsigned int ufq_cnt237); +int iSetFQ_CNT238_fq_cnt238(unsigned int ufq_cnt238); +int iSetFQ_CNT239_fq_cnt239(unsigned int ufq_cnt239); +int iSetFQ_CNT240_fq_cnt240(unsigned int ufq_cnt240); +int iSetMEM_CTRL_BUS_CFG0_stfqu_mem_ctrl_bus_0(unsigned int ustfqu_mem_ctrl_bus_0); +int iSetMEM_CTRL_BUS_CFG1_stfqu_mem_ctrl_bus_1(unsigned int ustfqu_mem_ctrl_bus_1); +int iSetMEM_CTRL_BUS_CFG2_stfqu_mem_ctrl_bus_2(unsigned int ustfqu_mem_ctrl_bus_2); +int iSetMEM_CTRL_BUS_CFG3_stfqu_mem_ctrl_bus_3(unsigned int ustfqu_mem_ctrl_bus_3); +int iSetMEM_CTRL_BUS_CFG4_stfqu_mem_ctrl_bus_4(unsigned int ustfqu_mem_ctrl_bus_4); +int iSetTCAM_CTRL_BUS_CFG4_stfqu_tcam_ctrl_bus(unsigned int ustfqu_tcam_ctrl_bus); +int iSetFQ_CNT241_fq_cnt241(unsigned int ufq_cnt241); + + +#endif // STFFQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stffq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stffq_reg_offset.h new file mode 100644 index 000000000..9f9992c0e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stffq_reg_offset.h @@ -0,0 +1,1059 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stffq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:03:30 Create file +// ****************************************************************************** + +#ifndef STFFQ_REG_OFFSET_H +#define STFFQ_REG_OFFSET_H + +/* QU_STFFQ_CSR Base address of Module's Register */ +#define CSR_QU_STFFQ_CSR_BASE (0x6000) +#define CSR_QU_STFFQ1_CSR_BASE (0x8000) + +/* **************************************************************************** */ +/* QU_STFFQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_STFFQ_CSR_FQ_MODE_REG_REG (CSR_QU_STFFQ_CSR_BASE + 0x0) /* FQ operation mode register */ +#define CSR_QU_STFFQ_CSR_FQ_INITCTAB_START_REG (CSR_QU_STFFQ_CSR_BASE + 0x4) /* FQ initialization start control */ +#define CSR_QU_STFFQ_CSR_FQ_INITCTAB_ST_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x8) /* FQ configurable tables' hw initilization done state. */ +#define CSR_QU_STFFQ_CSR_FQ_INIT_LOGIC_ST_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0xC) /* FQ non-configuration memory's hw initilization done state. */ +#define CSR_QU_STFFQ_CSR_FQ_INT_VECTOR_REG (CSR_QU_STFFQ_CSR_BASE + 0x10) /* FQ interrupt vector */ +#define CSR_QU_STFFQ_CSR_FQ_INT_REG (CSR_QU_STFFQ_CSR_BASE + 0x14) /* FQ_INT */ +#define CSR_QU_STFFQ_CSR_FQ_INT_MASK_REG (CSR_QU_STFFQ_CSR_BASE + 0x18) /* 中断屏蔽 */ +#define CSR_QU_STFFQ_CSR_FQ_INT_MEM_ERR_2B_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x1C) /* FQ uncorrected memory error(2b) registers.(fatal error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_OEID_AGED_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x20) /* FQ aged oeid error register.(severe error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_SCAN_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x24) /* Abnormal flow queue scan register.(fatal error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_FCMD_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x28) /* Abnormal commands status in fcell register.(Normal error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_DSP_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x2C) /* Abnormal commands ("dispath and cpb ack pair status" or "abnormal Tile cmds") \ + register.(Normal error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_PFH_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + \ + 0x30) /* FQ fetch qcntx (via qcmc) from smf timeout or error response status register.（severe error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_DBE_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + \ + 0x34) /* DBE(iq) fetch (via qcmc) qcntx from smf timeout or error response status register.(severe error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_QRSC_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x38) /* Abnormal qpc resource status register.(severe error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_BUF_UF_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + \ + 0x3C) /* uCode allocated buffer abnormal underflow for dispatch or overflow when allocation.(severe error) */ +#define CSR_QU_STFFQ_CSR_FQ_INT_FIFO0_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x40) /* FQ fifo abnoraml register.(severe error) */ +#define CSR_QU_STFFQ_CSR_FQ_INDRECT_CTRL_REG (CSR_QU_STFFQ_CSR_BASE + 0x44) /* FQ间接寻址控制寄存器 */ +#define CSR_QU_STFFQ_CSR_FQ_INDRECT_TIMEOUT_REG (CSR_QU_STFFQ_CSR_BASE + 0x48) /* FQ间接寻址Timeout水线配置 */ +#define CSR_QU_STFFQ_CSR_FQ_INDRECT_DAT0_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x4C) /* FQ memory indirect access write data0 or read data0. */ +#define CSR_QU_STFFQ_CSR_FQ_INDRECT_DAT1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x50) /* FQ memory indirect access write data0 or read data1. */ +#define CSR_QU_STFFQ_CSR_FQ_QCNTX_MODE_REG (CSR_QU_STFFQ_CSR_BASE + 0x54) /* FQ_QCNTX_MODE */ +#define CSR_QU_STFFQ_CSR_FQ_AGE_PERIOD_REG_REG (CSR_QU_STFFQ_CSR_BASE + 0x58) /* Aging period configuration */ +#define CSR_QU_STFFQ_CSR_STFFQ_DBE_HW_PFH_CFG_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x5C) /* FQ pre-fetch qcntx for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0x60) /* Timer trigger status register. */ +#define CSR_QU_STFFQ_CSR_FQ_CPB_CFG_REG (CSR_QU_STFFQ_CSR_BASE + 0x64) /* CPB packet buffer related configuration */ +#define CSR_QU_STFFQ_CSR_FQ_CRDT_2TLSMF_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0x68) /* Credits Values status */ +#define CSR_QU_STFFQ_CSR_FQ_CRDT_2TLSMF_REG_REG (CSR_QU_STFFQ_CSR_BASE + 0x6C) /* Default credits to SMF/Tiels. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x70) /* FQ counter sets control congifuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT0_REG (CSR_QU_STFFQ_CSR_BASE + 0x74) /* FQ counter 0 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT1_REG (CSR_QU_STFFQ_CSR_BASE + 0x78) /* FQ counter 1 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT2_REG (CSR_QU_STFFQ_CSR_BASE + 0x7C) /* FQ counter 2 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT3_REG (CSR_QU_STFFQ_CSR_BASE + 0x80) /* FQ counter 3 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT4_REG (CSR_QU_STFFQ_CSR_BASE + 0x84) /* FQ counter 4 */ +#define CSR_QU_STFFQ_CSR_FQ_SNAPSHOT_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x88) /* FQ snapshot control configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_SNAPSHOT_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0x8C) /* FQ snapshot status. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x90) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_CFG_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x94) /* FQ pre-fetch qpc/wqe for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_FIFO_GAP_CFG_REG (CSR_QU_STFFQ_CSR_BASE + 0x98) /* FQ fifo almost full gap configuration. \ + */ +#define CSR_QU_STFFQ_CSR_FQ_HIS_FIFO_CNT0_REG (CSR_QU_STFFQ_CSR_BASE + 0x9C) /* fifo's occupied counter0. */ +#define CSR_QU_STFFQ_CSR_FQ_HIS_FIFO_CNT1_REG (CSR_QU_STFFQ_CSR_BASE + 0xA0) /* fifo's occupied counter1. */ +#define CSR_QU_STFFQ_CSR_FQ_FIFO_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0xA4) /* FQ Fifos status */ +#define CSR_QU_STFFQ_CSR_FQ_HIS_FIFO_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0xA8) /* FQ Fifos history full status */ +#define CSR_QU_STFFQ_CSR_FQ_MEM_CTRL_REG (CSR_QU_STFFQ_CSR_BASE + 0xAC) /* Memory controls parameters setting. */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_EP2HOST_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0xB0) /* host side,host ep to host id map configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_PCAR_CFG_REG (CSR_QU_STFFQ_CSR_BASE + 0xB4) /* Post car configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT5_REG (CSR_QU_STFFQ_CSR_BASE + 0xB8) /* FQ counter 5 */ +#define CSR_QU_STFFQ_CSR_FQ_MOD_REG1_REG (CSR_QU_STFFQ_CSR_BASE + 0xBC) /* FQ mode regitesrs */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_BP_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0xC0) /* FQ inner interface backpressure status \ + */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST_REG (CSR_QU_STFFQ_CSR_BASE + 0xC4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT6_REG (CSR_QU_STFFQ_CSR_BASE + 0xC8) /* FQ counter 6 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT_CTL1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0xCC) /* Counter7~16 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT7_REG (CSR_QU_STFFQ_CSR_BASE + 0xD0) /* FQ Cnt 7 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT8_REG (CSR_QU_STFFQ_CSR_BASE + 0xD4) /* FQ Cnt 8 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT9_REG (CSR_QU_STFFQ_CSR_BASE + 0xD8) /* FQ Cnt 9 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT10_REG (CSR_QU_STFFQ_CSR_BASE + 0xDC) /* FQ Cnt 10 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT11_REG (CSR_QU_STFFQ_CSR_BASE + 0xE0) /* FQ Cnt 11 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT12_REG (CSR_QU_STFFQ_CSR_BASE + 0xE4) /* FQ Cnt 12 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT13_REG (CSR_QU_STFFQ_CSR_BASE + 0xE8) /* FQ Cnt 13 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT14_REG (CSR_QU_STFFQ_CSR_BASE + 0xEC) /* FQ Cnt 14 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT15_REG (CSR_QU_STFFQ_CSR_BASE + 0xF0) /* FQ Cnt 15 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT16_REG (CSR_QU_STFFQ_CSR_BASE + 0xF4) /* FQ Cnt 16 */ +#define CSR_QU_STFFQ_CSR_FQ_INT_MEM_ERR_1B_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0xF8) /* FQ correctable memory error(1bit) registers.(normal error) */ +#define CSR_QU_STFFQ_CSR_CFG_STYP_TH_FC_EN_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0xFC) /* Stateful thread resource flow control enable configuration. */ +#define CSR_QU_STFFQ_CSR_CFG_ZERO_ESCH_LEN_REG (CSR_QU_STFFQ_CSR_BASE + 0x100) /* 设置缺省状态下的esch调度length. */ +#define CSR_QU_STFFQ_CSR_CFG_FQ_BUBBLE_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x104) /* 控制插入fq流水线的气泡数量. */ +#define CSR_QU_STFFQ_CSR_CFG_L2DCACHE_BUBBLE_CTL_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x108) /* 控制插入L2DCache流水线的气泡数量. */ +#define CSR_QU_STFFQ_CSR_FQ_DEF_FQ_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x10C) /* Default FQ control register */ +#define CSR_QU_STFFQ_CSR_FQ_SMF_LDBCTL_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x110) /* Default STFFQ to SMF load balance control register */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_EP2HOST_H2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x114) /* host side,host ep to host id map configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_PREFETCH_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x118) /* fq预取wqe和qpc的配置寄存器. */ +#define CSR_QU_STFFQ_CSR_FQ_LATENCY_CFG_REG (CSR_QU_STFFQ_CSR_BASE + 0x11C) /* ICDQ的时延采样DFX配置 */ +#define CSR_QU_STFFQ_CSR_FQ_LATENCY_STA_REG (CSR_QU_STFFQ_CSR_BASE + 0x120) /* fq的时延采样DFX状态 */ +#define CSR_QU_STFFQ_CSR_FQ_SAMPLE_TMR_REG (CSR_QU_STFFQ_CSR_BASE + 0x124) /* fq的时延采样DFX时间 */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_FAKE_VF_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x128) /* fake vfid模式下的控制寄存器。 */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_BPS_DLY_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x12C) /* fq低延时bypass控制寄存器。 */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_OTSD_BASE_CTL_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x130) /* qu的otsd的起始编号。Qu接口传给fq的otsd需要减去这个base值，Fq内部只存3bit \ + otsd，fq还回给tile的otsd需要再加上这个base值。 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT_CTL2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x134) /* Counter17~26 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT17_REG (CSR_QU_STFFQ_CSR_BASE + 0x138) /* FQ Cnt 17 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT18_REG (CSR_QU_STFFQ_CSR_BASE + 0x13C) /* FQ Cnt 18 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT19_REG (CSR_QU_STFFQ_CSR_BASE + 0x140) /* FQ Cnt 19 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT20_REG (CSR_QU_STFFQ_CSR_BASE + 0x144) /* FQ Cnt 20 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT21_REG (CSR_QU_STFFQ_CSR_BASE + 0x148) /* FQ Cnt 21 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT22_REG (CSR_QU_STFFQ_CSR_BASE + 0x14C) /* FQ Cnt 22 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT23_REG (CSR_QU_STFFQ_CSR_BASE + 0x150) /* FQ Cnt 23 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT24_REG (CSR_QU_STFFQ_CSR_BASE + 0x154) /* FQ Cnt 24 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT25_REG (CSR_QU_STFFQ_CSR_BASE + 0x158) /* FQ Cnt 25 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT26_REG (CSR_QU_STFFQ_CSR_BASE + 0x15C) /* FQ Cnt 26 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT_CTL3_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x160) /* Counter27~36 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT27_REG (CSR_QU_STFFQ_CSR_BASE + 0x164) /* FQ Cnt 27 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT28_REG (CSR_QU_STFFQ_CSR_BASE + 0x168) /* FQ Cnt 28 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT29_REG (CSR_QU_STFFQ_CSR_BASE + 0x16C) /* FQ Cnt 29 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT30_REG (CSR_QU_STFFQ_CSR_BASE + 0x170) /* FQ Cnt 30 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT31_REG (CSR_QU_STFFQ_CSR_BASE + 0x174) /* FQ Cnt 31 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT32_REG (CSR_QU_STFFQ_CSR_BASE + 0x178) /* FQ Cnt 32 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT33_REG (CSR_QU_STFFQ_CSR_BASE + 0x17C) /* FQ Cnt 33 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT34_REG (CSR_QU_STFFQ_CSR_BASE + 0x180) /* FQ Cnt 34 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT35_REG (CSR_QU_STFFQ_CSR_BASE + 0x184) /* FQ Cnt 35 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT36_REG (CSR_QU_STFFQ_CSR_BASE + 0x188) /* FQ Cnt 36 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT_CTL4_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x18C) /* Counter27~36 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT37_REG (CSR_QU_STFFQ_CSR_BASE + 0x190) /* FQ Cnt 37 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT38_REG (CSR_QU_STFFQ_CSR_BASE + 0x194) /* FQ Cnt 38 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT39_REG (CSR_QU_STFFQ_CSR_BASE + 0x198) /* FQ Cnt 39 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT40_REG (CSR_QU_STFFQ_CSR_BASE + 0x19C) /* FQ Cnt 40 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT41_REG (CSR_QU_STFFQ_CSR_BASE + 0x1A0) /* FQ Cnt 41 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT42_REG (CSR_QU_STFFQ_CSR_BASE + 0x1A4) /* FQ Cnt 42 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT43_REG (CSR_QU_STFFQ_CSR_BASE + 0x1A8) /* FQ Cnt 43 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT44_REG (CSR_QU_STFFQ_CSR_BASE + 0x1AC) /* FQ Cnt 44 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT45_REG (CSR_QU_STFFQ_CSR_BASE + 0x1B0) /* FQ Cnt 45 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT46_REG (CSR_QU_STFFQ_CSR_BASE + 0x1B4) /* FQ Cnt 46 */ +#define CSR_QU_STFFQ_CSR_FQ_QU2SMF_TMR_DLY_REG (CSR_QU_STFFQ_CSR_BASE + 0x1B8) /* 控制fq送给smf的时戳 */ +#define CSR_QU_STFFQ_CSR_FQ_MAGIC_BOX_CTL_REG (CSR_QU_STFFQ_CSR_BASE + 0x1BC) /* fq的magic box的控制寄存器 */ +#define CSR_QU_STFFQ_CSR_FQ_MGBX_SRV2HASH_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x1C0) /* serve type的hash属性，用于magic box的输入。 */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST1_REG (CSR_QU_STFFQ_CSR_BASE + 0x1C4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST2_REG (CSR_QU_STFFQ_CSR_BASE + 0x1C8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST3_REG (CSR_QU_STFFQ_CSR_BASE + 0x1CC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST4_REG (CSR_QU_STFFQ_CSR_BASE + 0x1D0) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST5_REG (CSR_QU_STFFQ_CSR_BASE + 0x1D4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST6_REG (CSR_QU_STFFQ_CSR_BASE + 0x1D8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST7_REG (CSR_QU_STFFQ_CSR_BASE + 0x1DC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST8_REG (CSR_QU_STFFQ_CSR_BASE + 0x1E0) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST9_REG (CSR_QU_STFFQ_CSR_BASE + 0x1E4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST10_REG (CSR_QU_STFFQ_CSR_BASE + 0x1E8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST11_REG (CSR_QU_STFFQ_CSR_BASE + 0x1EC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST12_REG (CSR_QU_STFFQ_CSR_BASE + 0x1F0) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST13_REG (CSR_QU_STFFQ_CSR_BASE + 0x1F4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST14_REG (CSR_QU_STFFQ_CSR_BASE + 0x1F8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST15_REG (CSR_QU_STFFQ_CSR_BASE + 0x1FC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST16_REG (CSR_QU_STFFQ_CSR_BASE + 0x200) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST17_REG (CSR_QU_STFFQ_CSR_BASE + 0x204) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST18_REG (CSR_QU_STFFQ_CSR_BASE + 0x208) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST19_REG (CSR_QU_STFFQ_CSR_BASE + 0x20C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST20_REG (CSR_QU_STFFQ_CSR_BASE + 0x210) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST21_REG (CSR_QU_STFFQ_CSR_BASE + 0x214) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST22_REG (CSR_QU_STFFQ_CSR_BASE + 0x218) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST23_REG (CSR_QU_STFFQ_CSR_BASE + 0x21C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST24_REG (CSR_QU_STFFQ_CSR_BASE + 0x220) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST25_REG (CSR_QU_STFFQ_CSR_BASE + 0x224) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST26_REG (CSR_QU_STFFQ_CSR_BASE + 0x228) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST27_REG (CSR_QU_STFFQ_CSR_BASE + 0x22C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST28_REG (CSR_QU_STFFQ_CSR_BASE + 0x230) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST29_REG (CSR_QU_STFFQ_CSR_BASE + 0x234) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST30_REG (CSR_QU_STFFQ_CSR_BASE + 0x238) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST31_REG (CSR_QU_STFFQ_CSR_BASE + 0x23C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST32_REG (CSR_QU_STFFQ_CSR_BASE + 0x240) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST33_REG (CSR_QU_STFFQ_CSR_BASE + 0x244) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST34_REG (CSR_QU_STFFQ_CSR_BASE + 0x248) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST35_REG (CSR_QU_STFFQ_CSR_BASE + 0x24C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST36_REG (CSR_QU_STFFQ_CSR_BASE + 0x250) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST37_REG (CSR_QU_STFFQ_CSR_BASE + 0x254) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST38_REG (CSR_QU_STFFQ_CSR_BASE + 0x258) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST39_REG (CSR_QU_STFFQ_CSR_BASE + 0x25C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST40_REG (CSR_QU_STFFQ_CSR_BASE + 0x260) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST41_REG (CSR_QU_STFFQ_CSR_BASE + 0x264) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST42_REG (CSR_QU_STFFQ_CSR_BASE + 0x26C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST43_REG (CSR_QU_STFFQ_CSR_BASE + 0x270) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST44_REG (CSR_QU_STFFQ_CSR_BASE + 0x274) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST45_REG (CSR_QU_STFFQ_CSR_BASE + 0x278) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST46_REG (CSR_QU_STFFQ_CSR_BASE + 0x27C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST47_REG (CSR_QU_STFFQ_CSR_BASE + 0x280) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_INNER_MON_ST48_REG (CSR_QU_STFFQ_CSR_BASE + 0x284) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT47_REG (CSR_QU_STFFQ_CSR_BASE + 0x288) /* FQ Cnt 47 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_RQST_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x28C) /* STF FQ的ROU的RQST fifo0的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_RSP_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x290) /* STF FQ的ROU的RSP fifo0的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_RSP_FIFO1_REG (CSR_QU_STFFQ_CSR_BASE + 0x298) /* STF FQ的ROU的RSP fifo1的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_TMRODR_FIFO0_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x29C) /* STF FQ的TMR和ODR的ROU的RQST fifo0的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_TMRODR_FIFO1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x2A0) /* STF FQ的TMR和ODR的ROU的RQST fifo1的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_TMRODR_FIFO2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x2A4) /* STF FQ的TMR和ODR的ROU的RQST fifo2的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_ROU_TMRODR_FIFO3_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x2A8) /* STF FQ的TMR和ODR的ROU的RQST fifo3的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_RIN_RQST_FIFO_REG (CSR_QU_STFFQ_CSR_BASE + 0x2BC) /* STFFQ的RIN的RQST fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_RIN_RSP_FIFO_REG (CSR_QU_STFFQ_CSR_BASE + 0x2C0) /* STF FQ的RIN的RSP fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_SMF_RSP_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x2D4) /* FQ的QPC Ring的SMF RSP fifo0的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_SMF_RSP_FIFO1_REG (CSR_QU_STFFQ_CSR_BASE + 0x2D8) /* FQ的QPC Ring的SMF RSP fifo1的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_TL0_CMD_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x2DC) /* FQ的Tile0的CMD fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_TL0_EXTCMD_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x2E0) /* FQ的Tile0的EXTCMD fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_TL1_CMD_FIFO1_REG (CSR_QU_STFFQ_CSR_BASE + 0x2E4) /* FQ的Tile1的CMD fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_TL1_EXTCMD_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x2E8) /* FQ的Tile1的EXTCMD fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_FQ2OQ_FCNP_FIFO_REG (CSR_QU_STFFQ_CSR_BASE + 0x2EC) /* FQ的FQ2OQ的FCNP fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_OQ2FQ_FCNP_FIFO_REG (CSR_QU_STFFQ_CSR_BASE + 0x2F0) /* FQ的OQ2FQ的FCNP fifo的状态 */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO0_REG (CSR_QU_STFFQ_CSR_BASE + 0x2F4) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO1_REG (CSR_QU_STFFQ_CSR_BASE + 0x2F8) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO2_REG (CSR_QU_STFFQ_CSR_BASE + 0x2FC) /* FQ的TIMER FIRE API的RSP fifo2的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO3_REG (CSR_QU_STFFQ_CSR_BASE + 0x300) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO4_REG (CSR_QU_STFFQ_CSR_BASE + 0x304) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO5_REG (CSR_QU_STFFQ_CSR_BASE + 0x308) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO6_REG (CSR_QU_STFFQ_CSR_BASE + 0x30C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO7_REG (CSR_QU_STFFQ_CSR_BASE + 0x310) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO8_REG (CSR_QU_STFFQ_CSR_BASE + 0x314) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO9_REG (CSR_QU_STFFQ_CSR_BASE + 0x318) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO10_REG (CSR_QU_STFFQ_CSR_BASE + 0x31C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO11_REG (CSR_QU_STFFQ_CSR_BASE + 0x320) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO12_REG (CSR_QU_STFFQ_CSR_BASE + 0x324) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO13_REG (CSR_QU_STFFQ_CSR_BASE + 0x328) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO14_REG (CSR_QU_STFFQ_CSR_BASE + 0x32C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_TMR_RSP_FIFO15_REG (CSR_QU_STFFQ_CSR_BASE + 0x330) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_INT_RIN_RQST_ERR_REG (CSR_QU_STFFQ_CSR_BASE + 0x334) /* fq的ring进来的请求数据发现错误。 \ + */ +#define CSR_QU_STFFQ_CSR_FQ_INT_RIN_RSP_ERR_REG (CSR_QU_STFFQ_CSR_BASE + 0x338) /* fq的ring进来的响应数据发现错误。 */ +#define CSR_QU_STFFQ_CSR_FQ_INT_RIN_TRSP_ERR_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x33C) /* fq的ring进来的timer fire的响应数据发现错误。 */ +#define CSR_QU_STFFQ_CSR_FQ_INT_FIFO1_ERR_REG (CSR_QU_STFFQ_CSR_BASE + 0x340) /* 新增fifo的err中断。 */ +#define CSR_QU_STFFQ_CSR_FQ_INT_FIFO2_ERR_REG (CSR_QU_STFFQ_CSR_BASE + 0x344) /* 新增fifo的err中断。 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT48_REG (CSR_QU_STFFQ_CSR_BASE + 0x348) /* FQ Cnt 48 */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_STG_QP_PUSH0_REG (CSR_QU_STFFQ_CSR_BASE + 0x34C) /* FQ_cfg_stg_qp_push0 */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_STG_QP_PUSH1_REG (CSR_QU_STFFQ_CSR_BASE + 0x350) /* FQ_cfg_stg_qp_push1 */ +#define CSR_QU_STFFQ_CSR_FQ_CFG_STG_QP_PUSH2_REG (CSR_QU_STFFQ_CSR_BASE + 0x354) /* FQ_cfg_stg_qp_push2 */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x358) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x35C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN3_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x360) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN4_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x364) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN5_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x368) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN6_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x36C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN7_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x370) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN8_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x374) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN9_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x378) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN10_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x37C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN11_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x380) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN12_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x384) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN13_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x388) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN14_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x38C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_DBE_HW_WQE_EN15_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x390) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ_CSR_FQ_CNT49_REG (CSR_QU_STFFQ_CSR_BASE + 0x394) /* FQ Cnt 49 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT50_REG (CSR_QU_STFFQ_CSR_BASE + 0x398) /* FQ Cnt 50 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT51_REG (CSR_QU_STFFQ_CSR_BASE + 0x39C) /* FQ Cnt 51 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT52_REG (CSR_QU_STFFQ_CSR_BASE + 0x3A0) /* FQ Cnt 52 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT53_REG (CSR_QU_STFFQ_CSR_BASE + 0x3A4) /* FQ Cnt 53 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT54_REG (CSR_QU_STFFQ_CSR_BASE + 0x3A8) /* FQ Cnt 54 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT55_REG (CSR_QU_STFFQ_CSR_BASE + 0x3AC) /* FQ Cnt 55 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT56_REG (CSR_QU_STFFQ_CSR_BASE + 0x3B0) /* FQ Cnt 56 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT57_REG (CSR_QU_STFFQ_CSR_BASE + 0x3B4) /* FQ Cnt 57 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT58_REG (CSR_QU_STFFQ_CSR_BASE + 0x3B8) /* FQ Cnt 58 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT59_REG (CSR_QU_STFFQ_CSR_BASE + 0x3BC) /* FQ Cnt 59 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT60_REG (CSR_QU_STFFQ_CSR_BASE + 0x3C0) /* FQ Cnt 60 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT61_REG (CSR_QU_STFFQ_CSR_BASE + 0x3C4) /* FQ Cnt 61 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT62_REG (CSR_QU_STFFQ_CSR_BASE + 0x3C8) /* FQ Cnt 62 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT63_REG (CSR_QU_STFFQ_CSR_BASE + 0x3CC) /* FQ Cnt 63 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT64_REG (CSR_QU_STFFQ_CSR_BASE + 0x3D0) /* FQ Cnt 64 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT65_REG (CSR_QU_STFFQ_CSR_BASE + 0x3D4) /* FQ Cnt 65 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT66_REG (CSR_QU_STFFQ_CSR_BASE + 0x3D8) /* FQ Cnt 66 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT67_REG (CSR_QU_STFFQ_CSR_BASE + 0x3DC) /* FQ Cnt 67 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT68_REG (CSR_QU_STFFQ_CSR_BASE + 0x3E0) /* FQ Cnt 68 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT69_REG (CSR_QU_STFFQ_CSR_BASE + 0x3E4) /* FQ Cnt 69 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT70_REG (CSR_QU_STFFQ_CSR_BASE + 0x3E8) /* FQ Cnt 70 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT71_REG (CSR_QU_STFFQ_CSR_BASE + 0x3EC) /* FQ Cnt 71 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT72_REG (CSR_QU_STFFQ_CSR_BASE + 0x3F0) /* FQ Cnt 72 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT73_REG (CSR_QU_STFFQ_CSR_BASE + 0x3F4) /* FQ Cnt 73 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT74_REG (CSR_QU_STFFQ_CSR_BASE + 0x3F8) /* FQ Cnt 74 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT75_REG (CSR_QU_STFFQ_CSR_BASE + 0x3FC) /* FQ Cnt 75 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT76_REG (CSR_QU_STFFQ_CSR_BASE + 0x400) /* FQ Cnt 76 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT77_REG (CSR_QU_STFFQ_CSR_BASE + 0x404) /* FQ Cnt 77 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT78_REG (CSR_QU_STFFQ_CSR_BASE + 0x408) /* FQ Cnt 78 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT79_REG (CSR_QU_STFFQ_CSR_BASE + 0x40C) /* FQ Cnt 79 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT80_REG (CSR_QU_STFFQ_CSR_BASE + 0x410) /* FQ Cnt 80 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT81_REG (CSR_QU_STFFQ_CSR_BASE + 0x414) /* FQ Cnt 81 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT82_REG (CSR_QU_STFFQ_CSR_BASE + 0x418) /* FQ Cnt 82 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT83_REG (CSR_QU_STFFQ_CSR_BASE + 0x41C) /* FQ Cnt 83 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT84_REG (CSR_QU_STFFQ_CSR_BASE + 0x420) /* FQ Cnt 84 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT85_REG (CSR_QU_STFFQ_CSR_BASE + 0x424) /* FQ Cnt 85 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT86_REG (CSR_QU_STFFQ_CSR_BASE + 0x428) /* FQ Cnt 86 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT87_REG (CSR_QU_STFFQ_CSR_BASE + 0x42C) /* FQ Cnt 87 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT88_REG (CSR_QU_STFFQ_CSR_BASE + 0x430) /* FQ Cnt 88 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT89_REG (CSR_QU_STFFQ_CSR_BASE + 0x434) /* FQ Cnt 89 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT90_REG (CSR_QU_STFFQ_CSR_BASE + 0x438) /* FQ Cnt 90 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT91_REG (CSR_QU_STFFQ_CSR_BASE + 0x43C) /* FQ Cnt 91 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT92_REG (CSR_QU_STFFQ_CSR_BASE + 0x440) /* FQ Cnt 92 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT93_REG (CSR_QU_STFFQ_CSR_BASE + 0x444) /* FQ Cnt 93 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT94_REG (CSR_QU_STFFQ_CSR_BASE + 0x448) /* FQ Cnt 94 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT95_REG (CSR_QU_STFFQ_CSR_BASE + 0x44C) /* FQ Cnt 95 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT96_REG (CSR_QU_STFFQ_CSR_BASE + 0x450) /* FQ Cnt 96 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT97_REG (CSR_QU_STFFQ_CSR_BASE + 0x454) /* FQ Cnt 97 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT98_REG (CSR_QU_STFFQ_CSR_BASE + 0x458) /* FQ Cnt 98 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT99_REG (CSR_QU_STFFQ_CSR_BASE + 0x45C) /* FQ Cnt 99 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT100_REG (CSR_QU_STFFQ_CSR_BASE + 0x460) /* FQ Cnt 100 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT101_REG (CSR_QU_STFFQ_CSR_BASE + 0x464) /* FQ Cnt 101 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT102_REG (CSR_QU_STFFQ_CSR_BASE + 0x468) /* FQ Cnt 102 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT103_REG (CSR_QU_STFFQ_CSR_BASE + 0x46C) /* FQ Cnt 103 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT104_REG (CSR_QU_STFFQ_CSR_BASE + 0x470) /* FQ Cnt 104 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT105_REG (CSR_QU_STFFQ_CSR_BASE + 0x474) /* FQ Cnt 105 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT106_REG (CSR_QU_STFFQ_CSR_BASE + 0x478) /* FQ Cnt 106 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT107_REG (CSR_QU_STFFQ_CSR_BASE + 0x47C) /* FQ Cnt 107 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT108_REG (CSR_QU_STFFQ_CSR_BASE + 0x480) /* FQ Cnt 108 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT109_REG (CSR_QU_STFFQ_CSR_BASE + 0x484) /* FQ Cnt 109 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT110_REG (CSR_QU_STFFQ_CSR_BASE + 0x488) /* FQ Cnt 110 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT111_REG (CSR_QU_STFFQ_CSR_BASE + 0x48C) /* FQ Cnt 111 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT112_REG (CSR_QU_STFFQ_CSR_BASE + 0x490) /* FQ Cnt 112 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT113_REG (CSR_QU_STFFQ_CSR_BASE + 0x494) /* FQ Cnt 113 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT114_REG (CSR_QU_STFFQ_CSR_BASE + 0x498) /* FQ Cnt 114 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT115_REG (CSR_QU_STFFQ_CSR_BASE + 0x49C) /* FQ Cnt 115 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT116_REG (CSR_QU_STFFQ_CSR_BASE + 0x4A0) /* FQ Cnt 116 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT117_REG (CSR_QU_STFFQ_CSR_BASE + 0x4A4) /* FQ Cnt 117 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT118_REG (CSR_QU_STFFQ_CSR_BASE + 0x4A8) /* FQ Cnt 118 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT119_REG (CSR_QU_STFFQ_CSR_BASE + 0x4AC) /* FQ Cnt 119 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT120_REG (CSR_QU_STFFQ_CSR_BASE + 0x4B0) /* FQ Cnt 120 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT121_REG (CSR_QU_STFFQ_CSR_BASE + 0x4B4) /* FQ Cnt 121 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT122_REG (CSR_QU_STFFQ_CSR_BASE + 0x4B8) /* FQ Cnt 122 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT123_REG (CSR_QU_STFFQ_CSR_BASE + 0x4BC) /* FQ Cnt 123 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT124_REG (CSR_QU_STFFQ_CSR_BASE + 0x4C0) /* FQ Cnt 124 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT125_REG (CSR_QU_STFFQ_CSR_BASE + 0x4C4) /* FQ Cnt 125 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT126_REG (CSR_QU_STFFQ_CSR_BASE + 0x4C8) /* FQ Cnt 126 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT127_REG (CSR_QU_STFFQ_CSR_BASE + 0x4CC) /* FQ Cnt 127 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT128_REG (CSR_QU_STFFQ_CSR_BASE + 0x4D0) /* FQ Cnt 128 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT129_REG (CSR_QU_STFFQ_CSR_BASE + 0x4D4) /* FQ Cnt 129 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT130_REG (CSR_QU_STFFQ_CSR_BASE + 0x4D8) /* FQ Cnt 130 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT131_REG (CSR_QU_STFFQ_CSR_BASE + 0x4DC) /* FQ Cnt 131 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT132_REG (CSR_QU_STFFQ_CSR_BASE + 0x4E0) /* FQ Cnt 132 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT133_REG (CSR_QU_STFFQ_CSR_BASE + 0x4E4) /* FQ Cnt 133 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT134_REG (CSR_QU_STFFQ_CSR_BASE + 0x4E8) /* FQ Cnt 134 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT135_REG (CSR_QU_STFFQ_CSR_BASE + 0x4EC) /* FQ Cnt 135 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT136_REG (CSR_QU_STFFQ_CSR_BASE + 0x4F0) /* FQ Cnt 136 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT137_REG (CSR_QU_STFFQ_CSR_BASE + 0x4F4) /* FQ Cnt 137 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT138_REG (CSR_QU_STFFQ_CSR_BASE + 0x4F8) /* FQ Cnt 138 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT139_REG (CSR_QU_STFFQ_CSR_BASE + 0x4FC) /* FQ Cnt 139 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT140_REG (CSR_QU_STFFQ_CSR_BASE + 0x500) /* FQ Cnt 140 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT141_REG (CSR_QU_STFFQ_CSR_BASE + 0x504) /* FQ Cnt 141 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT142_REG (CSR_QU_STFFQ_CSR_BASE + 0x508) /* FQ Cnt 142 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT143_REG (CSR_QU_STFFQ_CSR_BASE + 0x50C) /* FQ Cnt 143 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT144_REG (CSR_QU_STFFQ_CSR_BASE + 0x510) /* FQ Cnt 144 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT145_REG (CSR_QU_STFFQ_CSR_BASE + 0x514) /* FQ Cnt 145 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT146_REG (CSR_QU_STFFQ_CSR_BASE + 0x518) /* FQ Cnt 146 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT147_REG (CSR_QU_STFFQ_CSR_BASE + 0x51C) /* FQ Cnt 147 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT148_REG (CSR_QU_STFFQ_CSR_BASE + 0x520) /* FQ Cnt 148 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT149_REG (CSR_QU_STFFQ_CSR_BASE + 0x524) /* FQ Cnt 149 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT150_REG (CSR_QU_STFFQ_CSR_BASE + 0x528) /* FQ Cnt 150 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT151_REG (CSR_QU_STFFQ_CSR_BASE + 0x52C) /* FQ Cnt 151 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT152_REG (CSR_QU_STFFQ_CSR_BASE + 0x530) /* FQ Cnt 152 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT153_REG (CSR_QU_STFFQ_CSR_BASE + 0x534) /* FQ Cnt 153 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT154_REG (CSR_QU_STFFQ_CSR_BASE + 0x538) /* FQ Cnt 154 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT155_REG (CSR_QU_STFFQ_CSR_BASE + 0x53C) /* FQ Cnt 155 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT156_REG (CSR_QU_STFFQ_CSR_BASE + 0x540) /* FQ Cnt 156 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT157_REG (CSR_QU_STFFQ_CSR_BASE + 0x544) /* FQ Cnt 157 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT158_REG (CSR_QU_STFFQ_CSR_BASE + 0x548) /* FQ Cnt 158 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT159_REG (CSR_QU_STFFQ_CSR_BASE + 0x54C) /* FQ Cnt 159 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT160_REG (CSR_QU_STFFQ_CSR_BASE + 0x550) /* FQ Cnt 160 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT161_REG (CSR_QU_STFFQ_CSR_BASE + 0x554) /* FQ Cnt 161 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT162_REG (CSR_QU_STFFQ_CSR_BASE + 0x558) /* FQ Cnt 162 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT163_REG (CSR_QU_STFFQ_CSR_BASE + 0x55C) /* FQ Cnt 163 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT164_REG (CSR_QU_STFFQ_CSR_BASE + 0x560) /* FQ Cnt 164 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT165_REG (CSR_QU_STFFQ_CSR_BASE + 0x564) /* FQ Cnt 165 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT166_REG (CSR_QU_STFFQ_CSR_BASE + 0x568) /* FQ Cnt 166 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT167_REG (CSR_QU_STFFQ_CSR_BASE + 0x56C) /* FQ Cnt 167 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT168_REG (CSR_QU_STFFQ_CSR_BASE + 0x570) /* FQ Cnt 168 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT169_REG (CSR_QU_STFFQ_CSR_BASE + 0x574) /* FQ Cnt 169 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT170_REG (CSR_QU_STFFQ_CSR_BASE + 0x578) /* FQ Cnt 170 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT171_REG (CSR_QU_STFFQ_CSR_BASE + 0x57C) /* FQ Cnt 171 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT172_REG (CSR_QU_STFFQ_CSR_BASE + 0x580) /* FQ Cnt 172 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT173_REG (CSR_QU_STFFQ_CSR_BASE + 0x584) /* FQ Cnt 173 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT174_REG (CSR_QU_STFFQ_CSR_BASE + 0x588) /* FQ Cnt 174 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT175_REG (CSR_QU_STFFQ_CSR_BASE + 0x58C) /* FQ Cnt 175 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT176_REG (CSR_QU_STFFQ_CSR_BASE + 0x590) /* FQ Cnt 176 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT177_REG (CSR_QU_STFFQ_CSR_BASE + 0x594) /* FQ Cnt 177 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT178_REG (CSR_QU_STFFQ_CSR_BASE + 0x598) /* FQ Cnt 178 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT179_REG (CSR_QU_STFFQ_CSR_BASE + 0x59C) /* FQ Cnt 179 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT180_REG (CSR_QU_STFFQ_CSR_BASE + 0x5A0) /* FQ Cnt 180 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT181_REG (CSR_QU_STFFQ_CSR_BASE + 0x5A4) /* FQ Cnt 181 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT182_REG (CSR_QU_STFFQ_CSR_BASE + 0x5A8) /* FQ Cnt 182 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT183_REG (CSR_QU_STFFQ_CSR_BASE + 0x5AC) /* FQ Cnt 183 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT184_REG (CSR_QU_STFFQ_CSR_BASE + 0x5B0) /* FQ Cnt 184 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT185_REG (CSR_QU_STFFQ_CSR_BASE + 0x5B4) /* FQ Cnt 185 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT186_REG (CSR_QU_STFFQ_CSR_BASE + 0x5B8) /* FQ Cnt 186 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT187_REG (CSR_QU_STFFQ_CSR_BASE + 0x5BC) /* FQ Cnt 187 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT188_REG (CSR_QU_STFFQ_CSR_BASE + 0x5C0) /* FQ Cnt 188 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT189_REG (CSR_QU_STFFQ_CSR_BASE + 0x5C4) /* FQ Cnt 189 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT190_REG (CSR_QU_STFFQ_CSR_BASE + 0x5C8) /* FQ Cnt 190 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT191_REG (CSR_QU_STFFQ_CSR_BASE + 0x5CC) /* FQ Cnt 191 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT192_REG (CSR_QU_STFFQ_CSR_BASE + 0x5D0) /* FQ Cnt 192 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT193_REG (CSR_QU_STFFQ_CSR_BASE + 0x5D4) /* FQ Cnt 193 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT194_REG (CSR_QU_STFFQ_CSR_BASE + 0x5D8) /* FQ Cnt 194 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT195_REG (CSR_QU_STFFQ_CSR_BASE + 0x5DC) /* FQ Cnt 195 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT196_REG (CSR_QU_STFFQ_CSR_BASE + 0x5E0) /* FQ Cnt 196 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT197_REG (CSR_QU_STFFQ_CSR_BASE + 0x5E4) /* FQ Cnt 197 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT198_REG (CSR_QU_STFFQ_CSR_BASE + 0x5E8) /* FQ Cnt 198 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT199_REG (CSR_QU_STFFQ_CSR_BASE + 0x5EC) /* FQ Cnt 199 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT200_REG (CSR_QU_STFFQ_CSR_BASE + 0x5F0) /* FQ Cnt 200 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT201_REG (CSR_QU_STFFQ_CSR_BASE + 0x5F4) /* FQ Cnt 201 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT202_REG (CSR_QU_STFFQ_CSR_BASE + 0x5F8) /* FQ Cnt 202 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT203_REG (CSR_QU_STFFQ_CSR_BASE + 0x5FC) /* FQ Cnt 203 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT204_REG (CSR_QU_STFFQ_CSR_BASE + 0x600) /* FQ Cnt 204 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT205_REG (CSR_QU_STFFQ_CSR_BASE + 0x604) /* FQ Cnt 205 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT206_REG (CSR_QU_STFFQ_CSR_BASE + 0x608) /* FQ Cnt 206 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT207_REG (CSR_QU_STFFQ_CSR_BASE + 0x60C) /* FQ Cnt 207 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT208_REG (CSR_QU_STFFQ_CSR_BASE + 0x610) /* FQ Cnt 208 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT209_REG (CSR_QU_STFFQ_CSR_BASE + 0x614) /* FQ Cnt 209 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT210_REG (CSR_QU_STFFQ_CSR_BASE + 0x618) /* FQ Cnt 210 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT211_REG (CSR_QU_STFFQ_CSR_BASE + 0x61C) /* FQ Cnt 211 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT212_REG (CSR_QU_STFFQ_CSR_BASE + 0x620) /* FQ Cnt 212 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT213_REG (CSR_QU_STFFQ_CSR_BASE + 0x624) /* FQ Cnt 213 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT214_REG (CSR_QU_STFFQ_CSR_BASE + 0x628) /* FQ Cnt 214 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT215_REG (CSR_QU_STFFQ_CSR_BASE + 0x62C) /* FQ Cnt 215 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT216_REG (CSR_QU_STFFQ_CSR_BASE + 0x630) /* FQ Cnt 216 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT217_REG (CSR_QU_STFFQ_CSR_BASE + 0x634) /* FQ Cnt 217 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT218_REG (CSR_QU_STFFQ_CSR_BASE + 0x638) /* FQ Cnt 218 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT219_REG (CSR_QU_STFFQ_CSR_BASE + 0x63C) /* FQ Cnt 219 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT220_REG (CSR_QU_STFFQ_CSR_BASE + 0x640) /* FQ Cnt 220 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT221_REG (CSR_QU_STFFQ_CSR_BASE + 0x644) /* FQ Cnt 221 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT222_REG (CSR_QU_STFFQ_CSR_BASE + 0x648) /* FQ Cnt 222 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT223_REG (CSR_QU_STFFQ_CSR_BASE + 0x64C) /* FQ Cnt 223 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT224_REG (CSR_QU_STFFQ_CSR_BASE + 0x650) /* FQ Cnt 224 */ +#define CSR_QU_STFFQ_CSR_FQ_RXPSH_CID_CTL_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x654) /* 控制fq rxfastflow推qpc时的xid转cid控制信号。 */ +#define CSR_QU_STFFQ_CSR_FQ_ROCE_DB_ODR_CTL1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x658) /* 控制RoCE的DB触发的QU继承order命令推SQE的socket的比特。 */ +#define CSR_QU_STFFQ_CSR_FQ_ROCE_DB_ODR_CTL2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x65C) /* 控制RoCE的DB触发的QU继承order命令推SQE的socket的比特。 */ +#define CSR_QU_STFFQ_CSR_FQ_NORM_NIC_ODR_CTL1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x660) /* 控制NIC的QU继承order命令推SQE的256bit flit的flit[191:160]。 */ +#define CSR_QU_STFFQ_CSR_FQ_NORM_NIC_ODR_CTL2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x664) /* 控制NIC的QU继承order命令推SQE的256bit flit的flit[159:128]。 */ +#define CSR_QU_STFFQ_CSR_FQ_ODR_FLIT256_CTL1_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x668) /* 控制QU发送的order命令的256bit宽度的flit的[127:96]。 */ +#define CSR_QU_STFFQ_CSR_FQ_ODR_FLIT256_CTL2_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x66C) /* 控制QU发送的order命令的256bit宽度的flit的[95:64]。 */ +#define CSR_QU_STFFQ_CSR_FQ_ODR_FLIT256_CTL3_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x670) /* 控制QU发送的order命令的256bit宽度的flit的[63:32]。 */ +#define CSR_QU_STFFQ_CSR_FQ_ODR_FLIT256_CTL4_REG \ + (CSR_QU_STFFQ_CSR_BASE + 0x674) /* 控制QU发送的order命令的256bit宽度的flit的[31:0]。 */ +#define CSR_QU_STFFQ_CSR_FQ_ODR_STYPE_CID2QID_EN_REG \ + (CSR_QU_STFFQ_CSR_BASE + \ + 0x678) /* 控制根据serve type来确定map表里的cid的低4比特是否是DB里的queue id（仅RoCE业务使能这个寄存器）。 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT225_REG (CSR_QU_STFFQ_CSR_BASE + 0x67C) /* FQ Cnt 225 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT226_REG (CSR_QU_STFFQ_CSR_BASE + 0x680) /* FQ Cnt 226 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT227_REG (CSR_QU_STFFQ_CSR_BASE + 0x684) /* FQ Cnt 227 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT228_REG (CSR_QU_STFFQ_CSR_BASE + 0x688) /* FQ Cnt 228 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT229_REG (CSR_QU_STFFQ_CSR_BASE + 0x68C) /* FQ Cnt 229 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT230_REG (CSR_QU_STFFQ_CSR_BASE + 0x690) /* FQ Cnt 230 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT231_REG (CSR_QU_STFFQ_CSR_BASE + 0x694) /* FQ Cnt 231 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT232_REG (CSR_QU_STFFQ_CSR_BASE + 0x698) /* FQ Cnt 232 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT233_REG (CSR_QU_STFFQ_CSR_BASE + 0x69C) /* FQ Cnt 233 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT234_REG (CSR_QU_STFFQ_CSR_BASE + 0x6A0) /* FQ Cnt 234 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT235_REG (CSR_QU_STFFQ_CSR_BASE + 0x6A4) /* FQ Cnt 235 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT236_REG (CSR_QU_STFFQ_CSR_BASE + 0x6A8) /* FQ Cnt 236 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT237_REG (CSR_QU_STFFQ_CSR_BASE + 0x6AC) /* FQ Cnt 237 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT238_REG (CSR_QU_STFFQ_CSR_BASE + 0x6B0) /* FQ Cnt 238 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT239_REG (CSR_QU_STFFQ_CSR_BASE + 0x6B4) /* FQ Cnt 239 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT240_REG (CSR_QU_STFFQ_CSR_BASE + 0x6B8) /* FQ Cnt 240 */ +#define CSR_QU_STFFQ_CSR_MEM_CTRL_BUS_CFG0_REG (CSR_QU_STFFQ_CSR_BASE + 0x6BC) /* RAM CTRL_BUS寄存器0 */ +#define CSR_QU_STFFQ_CSR_MEM_CTRL_BUS_CFG1_REG (CSR_QU_STFFQ_CSR_BASE + 0x6C0) /* RAM CTRL_BUS寄存器1 */ +#define CSR_QU_STFFQ_CSR_MEM_CTRL_BUS_CFG2_REG (CSR_QU_STFFQ_CSR_BASE + 0x6C4) /* RAM CTRL_BUS寄存器2 */ +#define CSR_QU_STFFQ_CSR_MEM_CTRL_BUS_CFG3_REG (CSR_QU_STFFQ_CSR_BASE + 0x6C8) /* RAM CTRL_BUS寄存器3 */ +#define CSR_QU_STFFQ_CSR_MEM_CTRL_BUS_CFG4_REG (CSR_QU_STFFQ_CSR_BASE + 0x6CC) /* RAM CTRL_BUS寄存器4 */ +#define CSR_QU_STFFQ_CSR_TCAM_CTRL_BUS_CFG4_REG (CSR_QU_STFFQ_CSR_BASE + 0x6D0) /* TCAM CTRL_BUS寄存器 */ +#define CSR_QU_STFFQ_CSR_FQ_CNT241_REG (CSR_QU_STFFQ_CSR_BASE + 0x6D4) /* FQ Cnt 241 */ + +#define CSR_QU_STFFQ1_CSR_FQ_MODE_REG_REG (CSR_QU_STFFQ1_CSR_BASE + 0x0) /* FQ operation mode register */ +#define CSR_QU_STFFQ1_CSR_FQ_INITCTAB_START_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4) /* FQ initialization start control */ +#define CSR_QU_STFFQ1_CSR_FQ_INITCTAB_ST_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x8) /* FQ configurable tables' hw initilization done state. */ +#define CSR_QU_STFFQ1_CSR_FQ_INIT_LOGIC_ST_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0xC) /* FQ non-configuration memory's hw initilization done state. */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_VECTOR_REG (CSR_QU_STFFQ1_CSR_BASE + 0x10) /* FQ interrupt vector */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_REG (CSR_QU_STFFQ1_CSR_BASE + 0x14) /* FQ_INT */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_MASK_REG (CSR_QU_STFFQ1_CSR_BASE + 0x18) /* 中断屏蔽 */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_MEM_ERR_2B_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x1C) /* FQ uncorrected memory error(2b) registers.(fatal error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_OEID_AGED_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x20) /* FQ aged oeid error register.(severe error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_SCAN_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x24) /* Abnormal flow queue scan register.(fatal error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_FCMD_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x28) /* Abnormal commands status in fcell register.(Normal error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_DSP_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x2C) /* Abnormal commands ("dispath and cpb ack pair status" or "abnormal Tile cmds") \ + register.(Normal error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_PFH_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + \ + 0x30) /* FQ fetch qcntx (via qcmc) from smf timeout or error response status register.（severe error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_DBE_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + \ + 0x34) /* DBE(iq) fetch (via qcmc) qcntx from smf timeout or error response status register.(severe error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_QRSC_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x38) /* Abnormal qpc resource status register.(severe error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_BUF_UF_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + \ + 0x3C) /* uCode allocated buffer abnormal underflow for dispatch or overflow when allocation.(severe error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_FIFO0_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x40) /* FQ fifo abnoraml register.(severe error) */ +#define CSR_QU_STFFQ1_CSR_FQ_INDRECT_CTRL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x44) /* FQ间接寻址控制寄存器 */ +#define CSR_QU_STFFQ1_CSR_FQ_INDRECT_TIMEOUT_REG (CSR_QU_STFFQ1_CSR_BASE + 0x48) /* FQ间接寻址Timeout水线配置 */ +#define CSR_QU_STFFQ1_CSR_FQ_INDRECT_DAT0_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x4C) /* FQ memory indirect access write data0 or read data0. */ +#define CSR_QU_STFFQ1_CSR_FQ_INDRECT_DAT1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x50) /* FQ memory indirect access write data0 or read data1. */ +#define CSR_QU_STFFQ1_CSR_FQ_QCNTX_MODE_REG (CSR_QU_STFFQ1_CSR_BASE + 0x54) /* FQ_QCNTX_MODE */ +#define CSR_QU_STFFQ1_CSR_FQ_AGE_PERIOD_REG_REG (CSR_QU_STFFQ1_CSR_BASE + 0x58) /* Aging period configuration */ +#define CSR_QU_STFFQ1_CSR_STFFQ1_DBE_HW_PFH_CFG_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x5C) /* FQ pre-fetch qcntx for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0x60) /* Timer trigger status register. */ +#define CSR_QU_STFFQ1_CSR_FQ_CPB_CFG_REG (CSR_QU_STFFQ1_CSR_BASE + 0x64) /* CPB packet buffer related configuration */ +#define CSR_QU_STFFQ1_CSR_FQ_CRDT_2TLSMF_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0x68) /* Credits Values status */ +#define CSR_QU_STFFQ1_CSR_FQ_CRDT_2TLSMF_REG_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6C) /* Default credits to SMF/Tiels. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x70) /* FQ counter sets control congifuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x74) /* FQ counter 0 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x78) /* FQ counter 1 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT2_REG (CSR_QU_STFFQ1_CSR_BASE + 0x7C) /* FQ counter 2 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT3_REG (CSR_QU_STFFQ1_CSR_BASE + 0x80) /* FQ counter 3 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT4_REG (CSR_QU_STFFQ1_CSR_BASE + 0x84) /* FQ counter 4 */ +#define CSR_QU_STFFQ1_CSR_FQ_SNAPSHOT_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x88) /* FQ snapshot control configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_SNAPSHOT_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0x8C) /* FQ snapshot status. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x90) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_CFG_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x94) /* FQ pre-fetch qpc/wqe for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_FIFO_GAP_CFG_REG (CSR_QU_STFFQ1_CSR_BASE + 0x98) /* FQ fifo almost full gap configuration. \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_HIS_FIFO_CNT0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x9C) /* fifo's occupied counter0. */ +#define CSR_QU_STFFQ1_CSR_FQ_HIS_FIFO_CNT1_REG (CSR_QU_STFFQ1_CSR_BASE + 0xA0) /* fifo's occupied counter1. */ +#define CSR_QU_STFFQ1_CSR_FQ_FIFO_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0xA4) /* FQ Fifos status */ +#define CSR_QU_STFFQ1_CSR_FQ_HIS_FIFO_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0xA8) /* FQ Fifos history full status */ +#define CSR_QU_STFFQ1_CSR_FQ_MEM_CTRL_REG (CSR_QU_STFFQ1_CSR_BASE + 0xAC) /* Memory controls parameters setting. */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_EP2HOST_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0xB0) /* host side,host ep to host id map configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_PCAR_CFG_REG (CSR_QU_STFFQ1_CSR_BASE + 0xB4) /* Post car configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT5_REG (CSR_QU_STFFQ1_CSR_BASE + 0xB8) /* FQ counter 5 */ +#define CSR_QU_STFFQ1_CSR_FQ_MOD_REG1_REG (CSR_QU_STFFQ1_CSR_BASE + 0xBC) /* FQ mode regitesrs */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_BP_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0xC0) /* FQ inner interface backpressure status \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST_REG (CSR_QU_STFFQ1_CSR_BASE + 0xC4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT6_REG (CSR_QU_STFFQ1_CSR_BASE + 0xC8) /* FQ counter 6 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT_CTL1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0xCC) /* Counter7~16 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT7_REG (CSR_QU_STFFQ1_CSR_BASE + 0xD0) /* FQ Cnt 7 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT8_REG (CSR_QU_STFFQ1_CSR_BASE + 0xD4) /* FQ Cnt 8 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT9_REG (CSR_QU_STFFQ1_CSR_BASE + 0xD8) /* FQ Cnt 9 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT10_REG (CSR_QU_STFFQ1_CSR_BASE + 0xDC) /* FQ Cnt 10 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT11_REG (CSR_QU_STFFQ1_CSR_BASE + 0xE0) /* FQ Cnt 11 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT12_REG (CSR_QU_STFFQ1_CSR_BASE + 0xE4) /* FQ Cnt 12 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT13_REG (CSR_QU_STFFQ1_CSR_BASE + 0xE8) /* FQ Cnt 13 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT14_REG (CSR_QU_STFFQ1_CSR_BASE + 0xEC) /* FQ Cnt 14 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT15_REG (CSR_QU_STFFQ1_CSR_BASE + 0xF0) /* FQ Cnt 15 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT16_REG (CSR_QU_STFFQ1_CSR_BASE + 0xF4) /* FQ Cnt 16 */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_MEM_ERR_1B_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0xF8) /* FQ correctable memory error(1bit) registers.(normal error) */ +#define CSR_QU_STFFQ1_CSR_CFG_STYP_TH_FC_EN_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0xFC) /* Stateful thread resource flow control enable configuration. */ +#define CSR_QU_STFFQ1_CSR_CFG_ZERO_ESCH_LEN_REG (CSR_QU_STFFQ1_CSR_BASE + 0x100) /* 设置缺省状态下的esch调度length. */ +#define CSR_QU_STFFQ1_CSR_CFG_FQ_BUBBLE_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x104) /* 控制插入fq流水线的气泡数量. */ +#define CSR_QU_STFFQ1_CSR_CFG_L2DCACHE_BUBBLE_CTL_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x108) /* 控制插入L2DCache流水线的气泡数量. */ +#define CSR_QU_STFFQ1_CSR_FQ_DEF_FQ_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x10C) /* Default FQ control register */ +#define CSR_QU_STFFQ1_CSR_FQ_SMF_LDBCTL_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x110) /* Default STFFQ1 to SMF load balance control register */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_EP2HOST_H2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x114) /* host side,host ep to host id map configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_PREFETCH_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x118) /* fq预取wqe和qpc的配置寄存器. */ +#define CSR_QU_STFFQ1_CSR_FQ_LATENCY_CFG_REG (CSR_QU_STFFQ1_CSR_BASE + 0x11C) /* ICDQ的时延采样DFX配置 */ +#define CSR_QU_STFFQ1_CSR_FQ_LATENCY_STA_REG (CSR_QU_STFFQ1_CSR_BASE + 0x120) /* fq的时延采样DFX状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_SAMPLE_TMR_REG (CSR_QU_STFFQ1_CSR_BASE + 0x124) /* fq的时延采样DFX时间 */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_FAKE_VF_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x128) /* fake vfid模式下的控制寄存器。 */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_BPS_DLY_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x12C) /* fq低延时bypass控制寄存器。 */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_OTSD_BASE_CTL_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x130) /* qu的otsd的起始编号。Qu接口传给fq的otsd需要减去这个base值，Fq内部只存3bit \ + otsd，fq还回给tile的otsd需要再加上这个base值。 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT_CTL2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x134) /* Counter17~26 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT17_REG (CSR_QU_STFFQ1_CSR_BASE + 0x138) /* FQ Cnt 17 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT18_REG (CSR_QU_STFFQ1_CSR_BASE + 0x13C) /* FQ Cnt 18 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT19_REG (CSR_QU_STFFQ1_CSR_BASE + 0x140) /* FQ Cnt 19 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT20_REG (CSR_QU_STFFQ1_CSR_BASE + 0x144) /* FQ Cnt 20 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT21_REG (CSR_QU_STFFQ1_CSR_BASE + 0x148) /* FQ Cnt 21 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT22_REG (CSR_QU_STFFQ1_CSR_BASE + 0x14C) /* FQ Cnt 22 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT23_REG (CSR_QU_STFFQ1_CSR_BASE + 0x150) /* FQ Cnt 23 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT24_REG (CSR_QU_STFFQ1_CSR_BASE + 0x154) /* FQ Cnt 24 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT25_REG (CSR_QU_STFFQ1_CSR_BASE + 0x158) /* FQ Cnt 25 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT26_REG (CSR_QU_STFFQ1_CSR_BASE + 0x15C) /* FQ Cnt 26 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT_CTL3_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x160) /* Counter27~36 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT27_REG (CSR_QU_STFFQ1_CSR_BASE + 0x164) /* FQ Cnt 27 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT28_REG (CSR_QU_STFFQ1_CSR_BASE + 0x168) /* FQ Cnt 28 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT29_REG (CSR_QU_STFFQ1_CSR_BASE + 0x16C) /* FQ Cnt 29 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT30_REG (CSR_QU_STFFQ1_CSR_BASE + 0x170) /* FQ Cnt 30 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT31_REG (CSR_QU_STFFQ1_CSR_BASE + 0x174) /* FQ Cnt 31 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT32_REG (CSR_QU_STFFQ1_CSR_BASE + 0x178) /* FQ Cnt 32 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT33_REG (CSR_QU_STFFQ1_CSR_BASE + 0x17C) /* FQ Cnt 33 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT34_REG (CSR_QU_STFFQ1_CSR_BASE + 0x180) /* FQ Cnt 34 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT35_REG (CSR_QU_STFFQ1_CSR_BASE + 0x184) /* FQ Cnt 35 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT36_REG (CSR_QU_STFFQ1_CSR_BASE + 0x188) /* FQ Cnt 36 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT_CTL4_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x18C) /* Counter27~36 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT37_REG (CSR_QU_STFFQ1_CSR_BASE + 0x190) /* FQ Cnt 37 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT38_REG (CSR_QU_STFFQ1_CSR_BASE + 0x194) /* FQ Cnt 38 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT39_REG (CSR_QU_STFFQ1_CSR_BASE + 0x198) /* FQ Cnt 39 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT40_REG (CSR_QU_STFFQ1_CSR_BASE + 0x19C) /* FQ Cnt 40 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT41_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1A0) /* FQ Cnt 41 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT42_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1A4) /* FQ Cnt 42 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT43_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1A8) /* FQ Cnt 43 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT44_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1AC) /* FQ Cnt 44 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT45_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1B0) /* FQ Cnt 45 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT46_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1B4) /* FQ Cnt 46 */ +#define CSR_QU_STFFQ1_CSR_FQ_QU2SMF_TMR_DLY_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1B8) /* 控制fq送给smf的时戳 */ +#define CSR_QU_STFFQ1_CSR_FQ_MAGIC_BOX_CTL_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1BC) /* fq的magic box的控制寄存器 */ +#define CSR_QU_STFFQ1_CSR_FQ_MGBX_SRV2HASH_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x1C0) /* serve type的hash属性，用于magic box的输入。 */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1C4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST2_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1C8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST3_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1CC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST4_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1D0) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST5_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1D4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST6_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1D8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST7_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1DC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST8_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1E0) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST9_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1E4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST10_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1E8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST11_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1EC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST12_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1F0) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST13_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1F4) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST14_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1F8) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST15_REG (CSR_QU_STFFQ1_CSR_BASE + 0x1FC) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST16_REG (CSR_QU_STFFQ1_CSR_BASE + 0x200) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST17_REG (CSR_QU_STFFQ1_CSR_BASE + 0x204) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST18_REG (CSR_QU_STFFQ1_CSR_BASE + 0x208) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST19_REG (CSR_QU_STFFQ1_CSR_BASE + 0x20C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST20_REG (CSR_QU_STFFQ1_CSR_BASE + 0x210) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST21_REG (CSR_QU_STFFQ1_CSR_BASE + 0x214) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST22_REG (CSR_QU_STFFQ1_CSR_BASE + 0x218) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST23_REG (CSR_QU_STFFQ1_CSR_BASE + 0x21C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST24_REG (CSR_QU_STFFQ1_CSR_BASE + 0x220) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST25_REG (CSR_QU_STFFQ1_CSR_BASE + 0x224) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST26_REG (CSR_QU_STFFQ1_CSR_BASE + 0x228) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST27_REG (CSR_QU_STFFQ1_CSR_BASE + 0x22C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST28_REG (CSR_QU_STFFQ1_CSR_BASE + 0x230) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST29_REG (CSR_QU_STFFQ1_CSR_BASE + 0x234) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST30_REG (CSR_QU_STFFQ1_CSR_BASE + 0x238) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST31_REG (CSR_QU_STFFQ1_CSR_BASE + 0x23C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST32_REG (CSR_QU_STFFQ1_CSR_BASE + 0x240) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST33_REG (CSR_QU_STFFQ1_CSR_BASE + 0x244) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST34_REG (CSR_QU_STFFQ1_CSR_BASE + 0x248) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST35_REG (CSR_QU_STFFQ1_CSR_BASE + 0x24C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST36_REG (CSR_QU_STFFQ1_CSR_BASE + 0x250) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST37_REG (CSR_QU_STFFQ1_CSR_BASE + 0x254) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST38_REG (CSR_QU_STFFQ1_CSR_BASE + 0x258) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST39_REG (CSR_QU_STFFQ1_CSR_BASE + 0x25C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST40_REG (CSR_QU_STFFQ1_CSR_BASE + 0x260) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST41_REG (CSR_QU_STFFQ1_CSR_BASE + 0x264) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST42_REG (CSR_QU_STFFQ1_CSR_BASE + 0x26C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST43_REG (CSR_QU_STFFQ1_CSR_BASE + 0x270) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST44_REG (CSR_QU_STFFQ1_CSR_BASE + 0x274) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST45_REG (CSR_QU_STFFQ1_CSR_BASE + 0x278) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST46_REG (CSR_QU_STFFQ1_CSR_BASE + 0x27C) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST47_REG (CSR_QU_STFFQ1_CSR_BASE + 0x280) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_INNER_MON_ST48_REG (CSR_QU_STFFQ1_CSR_BASE + 0x284) /* FQ innser status monitor bus. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT47_REG (CSR_QU_STFFQ1_CSR_BASE + 0x288) /* FQ Cnt 47 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_RQST_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x28C) /* STF FQ的ROU的RQST fifo0的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_RSP_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x290) /* STF FQ的ROU的RSP fifo0的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_RSP_FIFO1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x298) /* STF FQ的ROU的RSP fifo1的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_TMRODR_FIFO0_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x29C) /* STF FQ的TMR和ODR的ROU的RQST fifo0的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_TMRODR_FIFO1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x2A0) /* STF FQ的TMR和ODR的ROU的RQST fifo1的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_TMRODR_FIFO2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x2A4) /* STF FQ的TMR和ODR的ROU的RQST fifo2的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROU_TMRODR_FIFO3_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x2A8) /* STF FQ的TMR和ODR的ROU的RQST fifo3的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_RIN_RQST_FIFO_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2BC) /* STFFQ的RIN的RQST fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_RIN_RSP_FIFO_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2C0) /* STF FQ的RIN的RSP fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_SMF_RSP_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2D4) /* FQ的QPC Ring的SMF RSP fifo0的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_SMF_RSP_FIFO1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2D8) /* FQ的QPC Ring的SMF RSP fifo1的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_TL0_CMD_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2DC) /* FQ的Tile0的CMD fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_TL0_EXTCMD_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2E0) /* FQ的Tile0的EXTCMD fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_TL1_CMD_FIFO1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2E4) /* FQ的Tile1的CMD fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_TL1_EXTCMD_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2E8) /* FQ的Tile1的EXTCMD fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_FQ2OQ_FCNP_FIFO_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2EC) /* FQ的FQ2OQ的FCNP fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_OQ2FQ_FCNP_FIFO_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2F0) /* FQ的OQ2FQ的FCNP fifo的状态 */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2F4) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2F8) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO2_REG (CSR_QU_STFFQ1_CSR_BASE + 0x2FC) /* FQ的TIMER FIRE API的RSP fifo2的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO3_REG (CSR_QU_STFFQ1_CSR_BASE + 0x300) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO4_REG (CSR_QU_STFFQ1_CSR_BASE + 0x304) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO5_REG (CSR_QU_STFFQ1_CSR_BASE + 0x308) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO6_REG (CSR_QU_STFFQ1_CSR_BASE + 0x30C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO7_REG (CSR_QU_STFFQ1_CSR_BASE + 0x310) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO8_REG (CSR_QU_STFFQ1_CSR_BASE + 0x314) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO9_REG (CSR_QU_STFFQ1_CSR_BASE + 0x318) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO10_REG (CSR_QU_STFFQ1_CSR_BASE + 0x31C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO11_REG (CSR_QU_STFFQ1_CSR_BASE + 0x320) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO12_REG (CSR_QU_STFFQ1_CSR_BASE + 0x324) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO13_REG (CSR_QU_STFFQ1_CSR_BASE + 0x328) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO14_REG (CSR_QU_STFFQ1_CSR_BASE + 0x32C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_TMR_RSP_FIFO15_REG (CSR_QU_STFFQ1_CSR_BASE + 0x330) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_RIN_RQST_ERR_REG (CSR_QU_STFFQ1_CSR_BASE + 0x334) /* fq的ring进来的请求数据发现错误。 \ + */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_RIN_RSP_ERR_REG (CSR_QU_STFFQ1_CSR_BASE + 0x338) /* fq的ring进来的响应数据发现错误。 */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_RIN_TRSP_ERR_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x33C) /* fq的ring进来的timer fire的响应数据发现错误。 */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_FIFO1_ERR_REG (CSR_QU_STFFQ1_CSR_BASE + 0x340) /* 新增fifo的err中断。 */ +#define CSR_QU_STFFQ1_CSR_FQ_INT_FIFO2_ERR_REG (CSR_QU_STFFQ1_CSR_BASE + 0x344) /* 新增fifo的err中断。 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT48_REG (CSR_QU_STFFQ1_CSR_BASE + 0x348) /* FQ Cnt 48 */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_STG_QP_PUSH0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x34C) /* FQ_cfg_stg_qp_push0 */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_STG_QP_PUSH1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x350) /* FQ_cfg_stg_qp_push1 */ +#define CSR_QU_STFFQ1_CSR_FQ_CFG_STG_QP_PUSH2_REG (CSR_QU_STFFQ1_CSR_BASE + 0x354) /* FQ_cfg_stg_qp_push2 */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x358) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x35C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN3_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x360) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN4_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x364) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN5_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x368) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN6_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x36C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN7_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x370) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN8_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x374) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN9_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x378) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN10_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x37C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN11_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x380) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN12_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x384) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN13_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x388) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN14_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x38C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_DBE_HW_WQE_EN15_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x390) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT49_REG (CSR_QU_STFFQ1_CSR_BASE + 0x394) /* FQ Cnt 49 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT50_REG (CSR_QU_STFFQ1_CSR_BASE + 0x398) /* FQ Cnt 50 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT51_REG (CSR_QU_STFFQ1_CSR_BASE + 0x39C) /* FQ Cnt 51 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT52_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3A0) /* FQ Cnt 52 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT53_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3A4) /* FQ Cnt 53 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT54_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3A8) /* FQ Cnt 54 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT55_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3AC) /* FQ Cnt 55 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT56_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3B0) /* FQ Cnt 56 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT57_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3B4) /* FQ Cnt 57 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT58_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3B8) /* FQ Cnt 58 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT59_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3BC) /* FQ Cnt 59 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT60_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3C0) /* FQ Cnt 60 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT61_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3C4) /* FQ Cnt 61 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT62_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3C8) /* FQ Cnt 62 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT63_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3CC) /* FQ Cnt 63 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT64_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3D0) /* FQ Cnt 64 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT65_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3D4) /* FQ Cnt 65 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT66_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3D8) /* FQ Cnt 66 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT67_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3DC) /* FQ Cnt 67 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT68_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3E0) /* FQ Cnt 68 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT69_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3E4) /* FQ Cnt 69 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT70_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3E8) /* FQ Cnt 70 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT71_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3EC) /* FQ Cnt 71 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT72_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3F0) /* FQ Cnt 72 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT73_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3F4) /* FQ Cnt 73 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT74_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3F8) /* FQ Cnt 74 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT75_REG (CSR_QU_STFFQ1_CSR_BASE + 0x3FC) /* FQ Cnt 75 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT76_REG (CSR_QU_STFFQ1_CSR_BASE + 0x400) /* FQ Cnt 76 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT77_REG (CSR_QU_STFFQ1_CSR_BASE + 0x404) /* FQ Cnt 77 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT78_REG (CSR_QU_STFFQ1_CSR_BASE + 0x408) /* FQ Cnt 78 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT79_REG (CSR_QU_STFFQ1_CSR_BASE + 0x40C) /* FQ Cnt 79 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT80_REG (CSR_QU_STFFQ1_CSR_BASE + 0x410) /* FQ Cnt 80 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT81_REG (CSR_QU_STFFQ1_CSR_BASE + 0x414) /* FQ Cnt 81 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT82_REG (CSR_QU_STFFQ1_CSR_BASE + 0x418) /* FQ Cnt 82 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT83_REG (CSR_QU_STFFQ1_CSR_BASE + 0x41C) /* FQ Cnt 83 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT84_REG (CSR_QU_STFFQ1_CSR_BASE + 0x420) /* FQ Cnt 84 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT85_REG (CSR_QU_STFFQ1_CSR_BASE + 0x424) /* FQ Cnt 85 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT86_REG (CSR_QU_STFFQ1_CSR_BASE + 0x428) /* FQ Cnt 86 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT87_REG (CSR_QU_STFFQ1_CSR_BASE + 0x42C) /* FQ Cnt 87 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT88_REG (CSR_QU_STFFQ1_CSR_BASE + 0x430) /* FQ Cnt 88 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT89_REG (CSR_QU_STFFQ1_CSR_BASE + 0x434) /* FQ Cnt 89 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT90_REG (CSR_QU_STFFQ1_CSR_BASE + 0x438) /* FQ Cnt 90 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT91_REG (CSR_QU_STFFQ1_CSR_BASE + 0x43C) /* FQ Cnt 91 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT92_REG (CSR_QU_STFFQ1_CSR_BASE + 0x440) /* FQ Cnt 92 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT93_REG (CSR_QU_STFFQ1_CSR_BASE + 0x444) /* FQ Cnt 93 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT94_REG (CSR_QU_STFFQ1_CSR_BASE + 0x448) /* FQ Cnt 94 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT95_REG (CSR_QU_STFFQ1_CSR_BASE + 0x44C) /* FQ Cnt 95 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT96_REG (CSR_QU_STFFQ1_CSR_BASE + 0x450) /* FQ Cnt 96 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT97_REG (CSR_QU_STFFQ1_CSR_BASE + 0x454) /* FQ Cnt 97 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT98_REG (CSR_QU_STFFQ1_CSR_BASE + 0x458) /* FQ Cnt 98 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT99_REG (CSR_QU_STFFQ1_CSR_BASE + 0x45C) /* FQ Cnt 99 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT100_REG (CSR_QU_STFFQ1_CSR_BASE + 0x460) /* FQ Cnt 100 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT101_REG (CSR_QU_STFFQ1_CSR_BASE + 0x464) /* FQ Cnt 101 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT102_REG (CSR_QU_STFFQ1_CSR_BASE + 0x468) /* FQ Cnt 102 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT103_REG (CSR_QU_STFFQ1_CSR_BASE + 0x46C) /* FQ Cnt 103 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT104_REG (CSR_QU_STFFQ1_CSR_BASE + 0x470) /* FQ Cnt 104 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT105_REG (CSR_QU_STFFQ1_CSR_BASE + 0x474) /* FQ Cnt 105 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT106_REG (CSR_QU_STFFQ1_CSR_BASE + 0x478) /* FQ Cnt 106 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT107_REG (CSR_QU_STFFQ1_CSR_BASE + 0x47C) /* FQ Cnt 107 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT108_REG (CSR_QU_STFFQ1_CSR_BASE + 0x480) /* FQ Cnt 108 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT109_REG (CSR_QU_STFFQ1_CSR_BASE + 0x484) /* FQ Cnt 109 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT110_REG (CSR_QU_STFFQ1_CSR_BASE + 0x488) /* FQ Cnt 110 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT111_REG (CSR_QU_STFFQ1_CSR_BASE + 0x48C) /* FQ Cnt 111 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT112_REG (CSR_QU_STFFQ1_CSR_BASE + 0x490) /* FQ Cnt 112 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT113_REG (CSR_QU_STFFQ1_CSR_BASE + 0x494) /* FQ Cnt 113 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT114_REG (CSR_QU_STFFQ1_CSR_BASE + 0x498) /* FQ Cnt 114 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT115_REG (CSR_QU_STFFQ1_CSR_BASE + 0x49C) /* FQ Cnt 115 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT116_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4A0) /* FQ Cnt 116 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT117_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4A4) /* FQ Cnt 117 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT118_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4A8) /* FQ Cnt 118 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT119_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4AC) /* FQ Cnt 119 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT120_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4B0) /* FQ Cnt 120 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT121_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4B4) /* FQ Cnt 121 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT122_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4B8) /* FQ Cnt 122 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT123_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4BC) /* FQ Cnt 123 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT124_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4C0) /* FQ Cnt 124 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT125_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4C4) /* FQ Cnt 125 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT126_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4C8) /* FQ Cnt 126 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT127_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4CC) /* FQ Cnt 127 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT128_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4D0) /* FQ Cnt 128 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT129_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4D4) /* FQ Cnt 129 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT130_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4D8) /* FQ Cnt 130 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT131_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4DC) /* FQ Cnt 131 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT132_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4E0) /* FQ Cnt 132 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT133_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4E4) /* FQ Cnt 133 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT134_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4E8) /* FQ Cnt 134 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT135_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4EC) /* FQ Cnt 135 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT136_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4F0) /* FQ Cnt 136 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT137_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4F4) /* FQ Cnt 137 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT138_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4F8) /* FQ Cnt 138 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT139_REG (CSR_QU_STFFQ1_CSR_BASE + 0x4FC) /* FQ Cnt 139 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT140_REG (CSR_QU_STFFQ1_CSR_BASE + 0x500) /* FQ Cnt 140 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT141_REG (CSR_QU_STFFQ1_CSR_BASE + 0x504) /* FQ Cnt 141 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT142_REG (CSR_QU_STFFQ1_CSR_BASE + 0x508) /* FQ Cnt 142 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT143_REG (CSR_QU_STFFQ1_CSR_BASE + 0x50C) /* FQ Cnt 143 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT144_REG (CSR_QU_STFFQ1_CSR_BASE + 0x510) /* FQ Cnt 144 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT145_REG (CSR_QU_STFFQ1_CSR_BASE + 0x514) /* FQ Cnt 145 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT146_REG (CSR_QU_STFFQ1_CSR_BASE + 0x518) /* FQ Cnt 146 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT147_REG (CSR_QU_STFFQ1_CSR_BASE + 0x51C) /* FQ Cnt 147 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT148_REG (CSR_QU_STFFQ1_CSR_BASE + 0x520) /* FQ Cnt 148 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT149_REG (CSR_QU_STFFQ1_CSR_BASE + 0x524) /* FQ Cnt 149 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT150_REG (CSR_QU_STFFQ1_CSR_BASE + 0x528) /* FQ Cnt 150 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT151_REG (CSR_QU_STFFQ1_CSR_BASE + 0x52C) /* FQ Cnt 151 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT152_REG (CSR_QU_STFFQ1_CSR_BASE + 0x530) /* FQ Cnt 152 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT153_REG (CSR_QU_STFFQ1_CSR_BASE + 0x534) /* FQ Cnt 153 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT154_REG (CSR_QU_STFFQ1_CSR_BASE + 0x538) /* FQ Cnt 154 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT155_REG (CSR_QU_STFFQ1_CSR_BASE + 0x53C) /* FQ Cnt 155 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT156_REG (CSR_QU_STFFQ1_CSR_BASE + 0x540) /* FQ Cnt 156 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT157_REG (CSR_QU_STFFQ1_CSR_BASE + 0x544) /* FQ Cnt 157 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT158_REG (CSR_QU_STFFQ1_CSR_BASE + 0x548) /* FQ Cnt 158 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT159_REG (CSR_QU_STFFQ1_CSR_BASE + 0x54C) /* FQ Cnt 159 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT160_REG (CSR_QU_STFFQ1_CSR_BASE + 0x550) /* FQ Cnt 160 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT161_REG (CSR_QU_STFFQ1_CSR_BASE + 0x554) /* FQ Cnt 161 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT162_REG (CSR_QU_STFFQ1_CSR_BASE + 0x558) /* FQ Cnt 162 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT163_REG (CSR_QU_STFFQ1_CSR_BASE + 0x55C) /* FQ Cnt 163 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT164_REG (CSR_QU_STFFQ1_CSR_BASE + 0x560) /* FQ Cnt 164 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT165_REG (CSR_QU_STFFQ1_CSR_BASE + 0x564) /* FQ Cnt 165 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT166_REG (CSR_QU_STFFQ1_CSR_BASE + 0x568) /* FQ Cnt 166 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT167_REG (CSR_QU_STFFQ1_CSR_BASE + 0x56C) /* FQ Cnt 167 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT168_REG (CSR_QU_STFFQ1_CSR_BASE + 0x570) /* FQ Cnt 168 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT169_REG (CSR_QU_STFFQ1_CSR_BASE + 0x574) /* FQ Cnt 169 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT170_REG (CSR_QU_STFFQ1_CSR_BASE + 0x578) /* FQ Cnt 170 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT171_REG (CSR_QU_STFFQ1_CSR_BASE + 0x57C) /* FQ Cnt 171 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT172_REG (CSR_QU_STFFQ1_CSR_BASE + 0x580) /* FQ Cnt 172 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT173_REG (CSR_QU_STFFQ1_CSR_BASE + 0x584) /* FQ Cnt 173 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT174_REG (CSR_QU_STFFQ1_CSR_BASE + 0x588) /* FQ Cnt 174 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT175_REG (CSR_QU_STFFQ1_CSR_BASE + 0x58C) /* FQ Cnt 175 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT176_REG (CSR_QU_STFFQ1_CSR_BASE + 0x590) /* FQ Cnt 176 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT177_REG (CSR_QU_STFFQ1_CSR_BASE + 0x594) /* FQ Cnt 177 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT178_REG (CSR_QU_STFFQ1_CSR_BASE + 0x598) /* FQ Cnt 178 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT179_REG (CSR_QU_STFFQ1_CSR_BASE + 0x59C) /* FQ Cnt 179 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT180_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5A0) /* FQ Cnt 180 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT181_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5A4) /* FQ Cnt 181 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT182_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5A8) /* FQ Cnt 182 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT183_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5AC) /* FQ Cnt 183 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT184_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5B0) /* FQ Cnt 184 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT185_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5B4) /* FQ Cnt 185 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT186_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5B8) /* FQ Cnt 186 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT187_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5BC) /* FQ Cnt 187 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT188_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5C0) /* FQ Cnt 188 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT189_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5C4) /* FQ Cnt 189 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT190_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5C8) /* FQ Cnt 190 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT191_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5CC) /* FQ Cnt 191 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT192_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5D0) /* FQ Cnt 192 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT193_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5D4) /* FQ Cnt 193 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT194_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5D8) /* FQ Cnt 194 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT195_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5DC) /* FQ Cnt 195 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT196_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5E0) /* FQ Cnt 196 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT197_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5E4) /* FQ Cnt 197 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT198_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5E8) /* FQ Cnt 198 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT199_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5EC) /* FQ Cnt 199 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT200_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5F0) /* FQ Cnt 200 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT201_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5F4) /* FQ Cnt 201 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT202_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5F8) /* FQ Cnt 202 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT203_REG (CSR_QU_STFFQ1_CSR_BASE + 0x5FC) /* FQ Cnt 203 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT204_REG (CSR_QU_STFFQ1_CSR_BASE + 0x600) /* FQ Cnt 204 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT205_REG (CSR_QU_STFFQ1_CSR_BASE + 0x604) /* FQ Cnt 205 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT206_REG (CSR_QU_STFFQ1_CSR_BASE + 0x608) /* FQ Cnt 206 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT207_REG (CSR_QU_STFFQ1_CSR_BASE + 0x60C) /* FQ Cnt 207 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT208_REG (CSR_QU_STFFQ1_CSR_BASE + 0x610) /* FQ Cnt 208 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT209_REG (CSR_QU_STFFQ1_CSR_BASE + 0x614) /* FQ Cnt 209 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT210_REG (CSR_QU_STFFQ1_CSR_BASE + 0x618) /* FQ Cnt 210 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT211_REG (CSR_QU_STFFQ1_CSR_BASE + 0x61C) /* FQ Cnt 211 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT212_REG (CSR_QU_STFFQ1_CSR_BASE + 0x620) /* FQ Cnt 212 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT213_REG (CSR_QU_STFFQ1_CSR_BASE + 0x624) /* FQ Cnt 213 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT214_REG (CSR_QU_STFFQ1_CSR_BASE + 0x628) /* FQ Cnt 214 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT215_REG (CSR_QU_STFFQ1_CSR_BASE + 0x62C) /* FQ Cnt 215 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT216_REG (CSR_QU_STFFQ1_CSR_BASE + 0x630) /* FQ Cnt 216 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT217_REG (CSR_QU_STFFQ1_CSR_BASE + 0x634) /* FQ Cnt 217 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT218_REG (CSR_QU_STFFQ1_CSR_BASE + 0x638) /* FQ Cnt 218 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT219_REG (CSR_QU_STFFQ1_CSR_BASE + 0x63C) /* FQ Cnt 219 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT220_REG (CSR_QU_STFFQ1_CSR_BASE + 0x640) /* FQ Cnt 220 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT221_REG (CSR_QU_STFFQ1_CSR_BASE + 0x644) /* FQ Cnt 221 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT222_REG (CSR_QU_STFFQ1_CSR_BASE + 0x648) /* FQ Cnt 222 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT223_REG (CSR_QU_STFFQ1_CSR_BASE + 0x64C) /* FQ Cnt 223 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT224_REG (CSR_QU_STFFQ1_CSR_BASE + 0x650) /* FQ Cnt 224 */ +#define CSR_QU_STFFQ1_CSR_FQ_RXPSH_CID_CTL_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x654) /* 控制fq rxfastflow推qpc时的xid转cid控制信号。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROCE_DB_ODR_CTL1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x658) /* 控制RoCE的DB触发的QU继承order命令推SQE的socket的比特。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ROCE_DB_ODR_CTL2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x65C) /* 控制RoCE的DB触发的QU继承order命令推SQE的socket的比特。 */ +#define CSR_QU_STFFQ1_CSR_FQ_NORM_NIC_ODR_CTL1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x660) /* 控制NIC的QU继承order命令推SQE的256bit flit的flit[191:160]。 */ +#define CSR_QU_STFFQ1_CSR_FQ_NORM_NIC_ODR_CTL2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x664) /* 控制NIC的QU继承order命令推SQE的256bit flit的flit[159:128]。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ODR_FLIT256_CTL1_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x668) /* 控制QU发送的order命令的256bit宽度的flit的[127:96]。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ODR_FLIT256_CTL2_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x66C) /* 控制QU发送的order命令的256bit宽度的flit的[95:64]。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ODR_FLIT256_CTL3_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x670) /* 控制QU发送的order命令的256bit宽度的flit的[63:32]。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ODR_FLIT256_CTL4_REG \ + (CSR_QU_STFFQ1_CSR_BASE + 0x674) /* 控制QU发送的order命令的256bit宽度的flit的[31:0]。 */ +#define CSR_QU_STFFQ1_CSR_FQ_ODR_STYPE_CID2QID_EN_REG \ + (CSR_QU_STFFQ1_CSR_BASE + \ + 0x678) /* 控制根据serve type来确定map表里的cid的低4比特是否是DB里的queue id（仅RoCE业务使能这个寄存器）。 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT225_REG (CSR_QU_STFFQ1_CSR_BASE + 0x67C) /* FQ Cnt 225 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT226_REG (CSR_QU_STFFQ1_CSR_BASE + 0x680) /* FQ Cnt 226 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT227_REG (CSR_QU_STFFQ1_CSR_BASE + 0x684) /* FQ Cnt 227 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT228_REG (CSR_QU_STFFQ1_CSR_BASE + 0x688) /* FQ Cnt 228 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT229_REG (CSR_QU_STFFQ1_CSR_BASE + 0x68C) /* FQ Cnt 229 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT230_REG (CSR_QU_STFFQ1_CSR_BASE + 0x690) /* FQ Cnt 230 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT231_REG (CSR_QU_STFFQ1_CSR_BASE + 0x694) /* FQ Cnt 231 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT232_REG (CSR_QU_STFFQ1_CSR_BASE + 0x698) /* FQ Cnt 232 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT233_REG (CSR_QU_STFFQ1_CSR_BASE + 0x69C) /* FQ Cnt 233 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT234_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6A0) /* FQ Cnt 234 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT235_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6A4) /* FQ Cnt 235 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT236_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6A8) /* FQ Cnt 236 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT237_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6AC) /* FQ Cnt 237 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT238_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6B0) /* FQ Cnt 238 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT239_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6B4) /* FQ Cnt 239 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT240_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6B8) /* FQ Cnt 240 */ +#define CSR_QU_STFFQ1_CSR_MEM_CTRL_BUS_CFG0_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6BC) /* RAM CTRL_BUS寄存器0 */ +#define CSR_QU_STFFQ1_CSR_MEM_CTRL_BUS_CFG1_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6C0) /* RAM CTRL_BUS寄存器1 */ +#define CSR_QU_STFFQ1_CSR_MEM_CTRL_BUS_CFG2_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6C4) /* RAM CTRL_BUS寄存器2 */ +#define CSR_QU_STFFQ1_CSR_MEM_CTRL_BUS_CFG3_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6C8) /* RAM CTRL_BUS寄存器3 */ +#define CSR_QU_STFFQ1_CSR_MEM_CTRL_BUS_CFG4_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6CC) /* RAM CTRL_BUS寄存器4 */ +#define CSR_QU_STFFQ1_CSR_TCAM_CTRL_BUS_CFG4_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6D0) /* TCAM CTRL_BUS寄存器 */ +#define CSR_QU_STFFQ1_CSR_FQ_CNT241_REG (CSR_QU_STFFQ1_CSR_BASE + 0x6D4) /* FQ Cnt 241 */ + +#endif // STFFQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfiq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfiq_c_union_define.h new file mode 100644 index 000000000..de54e096c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfiq_c_union_define.h @@ -0,0 +1,1413 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : stfiq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : V100 +// Date : 2018/12/04 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/10/17 10:06:12 Create file +// ****************************************************************************** + +#ifndef STFIQ_C_UNION_DEFINE_H +#define STFIQ_C_UNION_DEFINE_H + +/* Define the union csr_stfiq_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_tpmem_timing_ctrl : 8; /* [7:0] */ + u32 csr_stfiq_spmem_timing_ctrl : 8; /* [15:8] */ + u32 csr_stfiq_tpmem_power_ctrl : 3; /* [18:16] */ + u32 csr_stfiq_spmem_power_ctrl : 3; /* [21:19] */ + u32 csr_stfiq_mem_init_start : 1; /* [22] */ + u32 csr_stfiq_mem_ecc_bypass : 1; /* [23] */ + u32 csr_stfiq_mem_ecc_req : 2; /* [25:24] */ + u32 csr_stfiq_cntx_sf_watchdog_en : 1; /* [26] */ + u32 rsv_0 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_mode_u; + +/* Define the union csr_stfiq_imsg_bm_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_bm_ini_start : 1; /* [0] */ + u32 imsg_bm_ini_depth : 8; /* [8:1] */ + u32 imsg_bm_time_out_interval_cfg : 1; /* [9] */ + u32 rsv_1 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_bm_ini_u; + +/* Define the union csr_stfiq_imsg_bm_time_out_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_bm_time_out_interval : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_bm_time_out_interval_u; + +/* Define the union csr_stfiq_imsg_bm_infor_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_bm_ini_busy : 1; /* [0] */ + u32 imsg_bm_ini_done : 1; /* [1] */ + u32 rsv_2 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_bm_infor_u; + +/* Define the union csr_stfiq_imsg_pro_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_stf_tmr_pro_typ : 7; /* [6:0] */ + u32 imsg_stl_tmr_pro_typ : 7; /* [13:7] */ + u32 imsg_fcnp_pro_typ : 7; /* [20:14] */ + u32 imsg_event_pro_typ : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_pro_type_u; + +/* Define the union csr_stfiq_imsg_source_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_msg_pfhid_limit : 9; /* [8:0] */ + u32 imsg_msg_pfhid_stl_task_tmr_limit : 8; /* [16:9] */ + u32 rsv_3 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_source_limit_u; + +/* Define the union csr_stfiq_imsg_dbe_psh_cpb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_dbe_psh_cpb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_dbe_psh_cpb_u; + +/* Define the union csr_stfiq_imsg_tmr_src_define0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_tmr_stl_src : 12; /* [11:0] */ + u32 imsg_tmr_stf_src : 12; /* [23:12] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_tmr_src_define0_u; + +/* Define the union csr_stfiq_imsg_event_src_define1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_tsk_src : 12; /* [11:0] */ + u32 imsg_fcnp_src : 12; /* [23:12] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_event_src_define1_u; + +/* Define the union csr_stfiq_close_fq_load_balance_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 close_fq_load_balance : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_close_fq_load_balance_u; + +/* Define the union csr_stfiq_fq_qpc_rsp_fifo_aful_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_fq0_qpc_rsp_aful : 6; /* [5:0] */ + u32 stfiq_fq1_qpc_rsp_aful : 6; /* [11:6] */ + u32 rsv_7 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_fq_qpc_rsp_fifo_aful_u; + +/* Define the union csr_stfiq_fq_qpc_rsp_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_fq0_qpc_rsp_cnt : 6; /* [5:0] */ + u32 stfiq_fq1_qpc_rsp_cnt : 6; /* [11:6] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_fq_qpc_rsp_fifo_cnt_u; + +/* Define the union csr_stfiq_ritf_perx_io_last_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_io_last_flag_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_perx_io_last_num_u; + +/* Define the union csr_stfiq_ritf_perx_io_first_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_io_first_flag_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_perx_io_first_num_u; + +/* Define the union csr_stfiq_ritf_ipsutx_io_last_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_io_last_flag_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_ipsutx_io_last_num_u; + +/* Define the union csr_stfiq_ritf_ipsutx_io_first_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_io_first_flag_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_ipsutx_io_first_num_u; + +/* Define the union csr_stfiq_ritf_io_rsp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ritf_io_rsp_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_io_rsp_num_u; + +/* Define the union csr_stfiq_wrr_weight_enq0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_wrr_weight_stffq_lb : 8; /* [7:0] */ + u32 stfiq_wrr_weight_oq_lb : 8; /* [15:8] */ + u32 stfiq_wrr_weight_icdq : 8; /* [23:16] */ + u32 stfiq_wrr_weight_stlfq_dsp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_wrr_weight_enq0_u; + +/* Define the union csr_stfiq_wrr_weight_enq1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_wrr_weight_stliq_ret : 8; /* [7:0] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_wrr_weight_enq1_u; + +/* Define the union csr_stfiq_flb_update_pd_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flb_update_pd_en : 1; /* [0] */ + u32 flb_update_epd_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_flb_update_pd_en_u; + +/* Define the union csr_stfiq_errpkt_drop_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errpkt_drop_en0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_errpkt_drop_en0_u; + +/* Define the union csr_stfiq_errpkt_drop_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errpkt_drop_en1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_errpkt_drop_en1_u; + +/* Define the union csr_stfiq_errpkt_drop_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errpkt_drop_en2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_errpkt_drop_en2_u; + +/* Define the union csr_stfiq_errpkt_drop_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errpkt_drop_en3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_errpkt_drop_en3_u; + +/* Define the union csr_stfiq_wrr_weight_enq2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_wrr_weight_qry : 8; /* [7:0] */ + u32 stfiq_wrr_weight_enq : 8; /* [15:8] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_wrr_weight_enq2_u; + +/* Define the union csr_stfiq_imsg_msg_fifo_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_dbe_aful : 9; /* [8:0] */ + u32 fq0_timer_aful : 9; /* [17:9] */ + u32 fq1_timer_aful : 9; /* [26:18] */ + u32 rsv_12 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_msg_fifo_af_u; + +/* Define the union csr_stfiq_imsg_stl_stf_msg_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlmsg_aful : 6; /* [5:0] */ + u32 stfmsg_aful : 6; /* [11:6] */ + u32 rsv_13 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_stl_stf_msg_af_u; + +/* Define the union csr_stfiq_ritf_fifo_aful0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_event_aful : 5; /* [4:0] */ + u32 fcnp_event_aful : 13; /* [17:5] */ + u32 perx_event_aful : 6; /* [23:18] */ + u32 ipsutx_event_aful : 6; /* [29:24] */ + u32 rsv_14 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_fifo_aful0_u; + +/* Define the union csr_stfiq_ritf_fifo_aful1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 taskid_order_aful : 15; /* [14:0] */ + u32 rsv_15 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_fifo_aful1_u; + +/* Define the union csr_stfiq_iarb_fifo_aful0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stor_icdq_infor_aful : 7; /* [6:0] */ + u32 stor_stffq0_flb_infor_aful : 7; /* [13:7] */ + u32 stor_stffq1_flb_infor_aful : 7; /* [20:14] */ + u32 stor_oq_olb_infor_aful : 7; /* [27:21] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iarb_fifo_aful0_u; + +/* Define the union csr_stfiq_iarb_fifo_aful1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stor_stliq_ret_infor_aful : 7; /* [6:0] */ + u32 stor_stlfq_dsp_infor_aful : 7; /* [13:7] */ + u32 stor_stffq0_qry_infor_aful : 7; /* [20:14] */ + u32 stor_stffq1_qry_infor_aful : 7; /* [27:21] */ + u32 rsv_17 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iarb_fifo_aful1_u; + +/* Define the union csr_stfiq_iarb_fifo_aful2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stor_pd_infor_aful : 7; /* [6:0] */ + u32 rsv_18 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iarb_fifo_aful2_u; + +/* Define the union csr_stfiq_imsg_msg_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_dbe_cnt : 9; /* [8:0] */ + u32 fq0_timer_cnt : 9; /* [17:9] */ + u32 fq1_timer_cnt : 9; /* [26:18] */ + u32 rsv_19 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_msg_fifo_cnt_u; + +/* Define the union csr_stfiq_imsg_stl_stf_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlmsg_cnt : 6; /* [5:0] */ + u32 stfmsg_cnt0 : 6; /* [11:6] */ + u32 stfmsg_cnt1 : 6; /* [17:12] */ + u32 rsv_20 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_imsg_stl_stf_msg_cnt_u; + +/* Define the union csr_stfiq_ritf_fifo_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_event_cnt : 5; /* [4:0] */ + u32 fcnp_event_cnt : 13; /* [17:5] */ + u32 perx_event_cnt : 6; /* [23:18] */ + u32 ipsutx_event_cnt : 6; /* [29:24] */ + u32 rsv_21 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_fifo_cnt0_u; + +/* Define the union csr_stfiq_ritf_fifo_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 taskid_order_cnt : 15; /* [14:0] */ + u32 rsv_22 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ritf_fifo_cnt1_u; + +/* Define the union csr_stfiq_iarb_fifo_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stor_icdq_infor_cnt : 7; /* [6:0] */ + u32 stor_stffq0_flb_infor_cnt : 7; /* [13:7] */ + u32 stor_stffq1_flb_infor_cnt : 7; /* [20:14] */ + u32 stor_oq_olb_infor_cnt : 7; /* [27:21] */ + u32 rsv_23 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iarb_fifo_cnt0_u; + +/* Define the union csr_stfiq_iarb_fifo_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stor_stliq_ret_infor_cnt : 7; /* [6:0] */ + u32 stor_stlfq_dsp_infor_cnt : 7; /* [13:7] */ + u32 stor_stffq0_qry_infor_cnt : 7; /* [20:14] */ + u32 stor_stffq1_qry_infor_cnt : 7; /* [27:21] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iarb_fifo_cnt1_u; + +/* Define the union csr_stfiq_iarb_fifo_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stor_pd_infor_cnt : 7; /* [6:0] */ + u32 rsv_25 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iarb_fifo_cnt2_u; + +/* Define the union csr_stfiq_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_done : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_mem_init_done_u; + +/* Define the union csr_stfiq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_27 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_28 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int_vector_u; + +/* Define the union csr_stfiq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 16; /* [15:0] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int_u; + +/* Define the union csr_stfiq_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 16; /* [15:0] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int_en_u; + +/* Define the union csr_stfiq_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imsg_bm_time_out_rpt : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 stfiq_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int0_sticky_u; + +/* Define the union csr_stfiq_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_fifo_overflow0 : 1; /* [0] */ + u32 int_insrt10 : 1; /* [1] */ + u32 stfiq_int1_sticky0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int1_sticky_u; + +/* Define the union csr_stfiq_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_fifo_underflow0 : 1; /* [0] */ + u32 int_insrt20 : 1; /* [1] */ + u32 stfiq_int2_sticky0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int2_sticky_u; + +/* Define the union csr_stfiq_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_ram_ecc_cerr : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 stfiq_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int3_sticky_u; + +/* Define the union csr_stfiq_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_ram_ecc_ucerr : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 stfiq_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_int4_sticky_u; + +/* Define the union csr_stfiq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_ctrl_u; + +/* Define the union csr_stfiq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_timeout_u; + +/* Define the union csr_stfiq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat0_u; + +/* Define the union csr_stfiq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat1_u; + +/* Define the union csr_stfiq_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat2_u; + +/* Define the union csr_stfiq_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat3_u; + +/* Define the union csr_stfiq_indrect_dat4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat4_u; + +/* Define the union csr_stfiq_indrect_dat5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat5_u; + +/* Define the union csr_stfiq_indrect_dat6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_indrect_data6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_indrect_dat6_u; + +/* Define the union csr_stfiq_prefetch_req_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_prefetch_req_inc0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_prefetch_req_cnt0_u; + +/* Define the union csr_stfiq_prefetch_req_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_prefetch_req_inc1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_prefetch_req_cnt1_u; + +/* Define the union csr_stfiq_prefetch_rsp_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_prefetch_rsp_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_prefetch_rsp_cnt0_u; + +/* Define the union csr_stfiq_prefetch_rsp_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_prefetch_rsp_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_prefetch_rsp_cnt1_u; + +/* Define the union csr_stfiq_cnt_db_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_cnt_db_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_cnt_db_u; + +/* Define the union csr_stfiq_cnt_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_cnt_tmr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_cnt_tmr_u; + +/* Define the union csr_stfiq_cnt_tsk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_cnt_tsk_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_cnt_tsk_u; + +/* Define the union csr_stfiq_cnt_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_cnt_fcnp_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_cnt_fcnp_u; + +/* Define the union csr_stfiq_cnt_msg_schedule_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_cnt_msg_schedule_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_cnt_msg_schedule_u; + +/* Define the union csr_stfiq_earb_roce_rd_pro_type0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_roce_rd_pro_type0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_earb_roce_rd_pro_type0_u; + +/* Define the union csr_stfiq_iqm_fret_err_drop0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fret_err_drop_en0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iqm_fret_err_drop0_u; + +/* Define the union csr_stfiq_iqm_fret_err_drop1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fret_err_drop_en1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iqm_fret_err_drop1_u; + +/* Define the union csr_stfiq_iqm_fret_err_drop2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fret_err_drop_en2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iqm_fret_err_drop2_u; + +/* Define the union csr_stfiq_iqm_fret_err_drop3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fret_err_drop_en3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_iqm_fret_err_drop3_u; + +/* Define the union csr_stfiq_ifp_start_time_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_ifp_start_time_cnt : 8; /* [7:0] */ + u32 rsv_29 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_ifp_start_time_cnt_u; + +/* Define the union csr_stfiq_qry_fifo_aful_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qry_eop_gain_fifo_af_th : 7; /* [6:0] */ + u32 cntxsf_fifo_af_th : 6; /* [12:7] */ + u32 rsv_30 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_qry_fifo_aful_u; + +/* Define the union csr_stfiq_qry_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qry_eop_gain_fifo_fill : 7; /* [6:0] */ + u32 cntxsf_fifo_fill : 6; /* [12:7] */ + u32 rsv_31 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_qry_fifo_cnt_u; + +/* Define the union csr_stfiq_icdq_sqd_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_cfg_sqd_bp : 8; /* [7:0] */ + u32 rsv_32 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_icdq_sqd_bp_u; + +/* Define the union csr_stfiq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_sample_mode : 1; /* [0] */ + u32 csr_stfiq_spec_port_en : 1; /* [1] */ + u32 csr_stfiq_done_clr : 1; /* [2] */ + u32 rsv_33 : 1; /* [3] */ + u32 csr_stfiq_spec_port_num : 4; /* [7:4] */ + u32 csr_stfiq_spec_pptr_typ : 8; /* [15:8] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_latency_cfg_u; + +/* Define the union csr_stfiq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_sample_done : 1; /* [0] */ + u32 rsv_35 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_latency_sta_u; + +/* Define the union csr_stfiq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_sample_tmr_u; + +/* Define the union csr_stfiq_earb_roce_rd_pro_type1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_roce_rd_pro_type1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_earb_roce_rd_pro_type1_u; + +/* Define the union csr_stfiq_earb_roce_rd_pro_type2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_roce_rd_pro_type2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_earb_roce_rd_pro_type2_u; + +/* Define the union csr_stfiq_earb_roce_rd_pro_type3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_roce_rd_pro_type3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_earb_roce_rd_pro_type3_u; + +/* Define the union csr_stfiq_quf_pg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_quf_pg_cfg : 2; /* [1:0] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_quf_pg_cfg_u; + +/* Define the union csr_stfiq_cntx_timout_wattermark_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_cntx_sf_timeout_watermark : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_cntx_timout_wattermark_u; + +/* Define the union csr_stfiq_fake_vf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stfiq_fake_vf_mask : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_fake_vf_mask_u; + +/* Define the union csr_cmd_pkt_ichannel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_pkt_ichannel0 : 8; /* [7:0] */ + u32 cmd_pkt_ichannel1 : 8; /* [15:8] */ + u32 cmd_pkt_ichannel2 : 8; /* [23:16] */ + u32 cmd_pkt_ichannel3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmd_pkt_ichannel0_u; + +/* Define the union csr_cmd_pkt_ichannel1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_pkt_ichannel4 : 8; /* [7:0] */ + u32 cmd_pkt_ichannel5 : 8; /* [15:8] */ + u32 cmd_pkt_ichannel6 : 8; /* [23:16] */ + u32 cmd_pkt_ichannel7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmd_pkt_ichannel1_u; + +/* Define the union csr_csr_iqm_cfg_threshold_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_cfg_threshold0 : 16; /* [15:0] */ + u32 csr_iqm_cfg_threshold1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_iqm_cfg_threshold_u; + +/* Define the union csr_csr_iqm_time_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_time_interval : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_iqm_time_interval_u; + +/* Define the union csr_csr_iqm_time_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_time_out_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_iqm_time_out_cnt_u; + +/* Define the union csr_csr_iqm_time_out_queue0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_time_out_queue0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_iqm_time_out_queue0_u; + +/* Define the union csr_csr_iqm_time_out_queue1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_time_out_queue1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_iqm_time_out_queue1_u; + +/* Define the union csr_csr_iqm_time_out_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_iqm_time_out_start : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_iqm_time_out_start_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_stfiq_mode_u stfiq_mode; /* 0 */ + volatile csr_stfiq_imsg_bm_ini_u stfiq_imsg_bm_ini; /* 4 */ + volatile csr_stfiq_imsg_bm_time_out_interval_u stfiq_imsg_bm_time_out_interval; /* 8 */ + volatile csr_stfiq_imsg_bm_infor_u stfiq_imsg_bm_infor; /* C */ + volatile csr_stfiq_imsg_pro_type_u stfiq_imsg_pro_type; /* 10 */ + volatile csr_stfiq_imsg_source_limit_u stfiq_imsg_source_limit; /* 14 */ + volatile csr_stfiq_imsg_dbe_psh_cpb_u stfiq_imsg_dbe_psh_cpb; /* 18 */ + volatile csr_stfiq_imsg_tmr_src_define0_u stfiq_imsg_tmr_src_define0; /* 1C */ + volatile csr_stfiq_imsg_event_src_define1_u stfiq_imsg_event_src_define1; /* 20 */ + volatile csr_stfiq_close_fq_load_balance_u stfiq_close_fq_load_balance; /* 24 */ + volatile csr_stfiq_fq_qpc_rsp_fifo_aful_u stfiq_fq_qpc_rsp_fifo_aful; /* 28 */ + volatile csr_stfiq_fq_qpc_rsp_fifo_cnt_u stfiq_fq_qpc_rsp_fifo_cnt; /* 2C */ + volatile csr_stfiq_ritf_perx_io_last_num_u stfiq_ritf_perx_io_last_num; /* 30 */ + volatile csr_stfiq_ritf_perx_io_first_num_u stfiq_ritf_perx_io_first_num; /* 34 */ + volatile csr_stfiq_ritf_ipsutx_io_last_num_u stfiq_ritf_ipsutx_io_last_num; /* 38 */ + volatile csr_stfiq_ritf_ipsutx_io_first_num_u stfiq_ritf_ipsutx_io_first_num; /* 3C */ + volatile csr_stfiq_ritf_io_rsp_num_u stfiq_ritf_io_rsp_num; /* 40 */ + volatile csr_stfiq_wrr_weight_enq0_u stfiq_wrr_weight_enq0; /* 44 */ + volatile csr_stfiq_wrr_weight_enq1_u stfiq_wrr_weight_enq1; /* 48 */ + volatile csr_stfiq_flb_update_pd_en_u stfiq_flb_update_pd_en; /* 4C */ + volatile csr_stfiq_errpkt_drop_en0_u stfiq_errpkt_drop_en0; /* 50 */ + volatile csr_stfiq_errpkt_drop_en1_u stfiq_errpkt_drop_en1; /* 54 */ + volatile csr_stfiq_errpkt_drop_en2_u stfiq_errpkt_drop_en2; /* 58 */ + volatile csr_stfiq_errpkt_drop_en3_u stfiq_errpkt_drop_en3; /* 5C */ + volatile csr_stfiq_wrr_weight_enq2_u stfiq_wrr_weight_enq2; /* 60 */ + volatile csr_stfiq_imsg_msg_fifo_af_u stfiq_imsg_msg_fifo_af; /* 64 */ + volatile csr_stfiq_imsg_stl_stf_msg_af_u stfiq_imsg_stl_stf_msg_af; /* 68 */ + volatile csr_stfiq_ritf_fifo_aful0_u stfiq_ritf_fifo_aful0; /* 6C */ + volatile csr_stfiq_ritf_fifo_aful1_u stfiq_ritf_fifo_aful1; /* 70 */ + volatile csr_stfiq_iarb_fifo_aful0_u stfiq_iarb_fifo_aful0; /* 74 */ + volatile csr_stfiq_iarb_fifo_aful1_u stfiq_iarb_fifo_aful1; /* 78 */ + volatile csr_stfiq_iarb_fifo_aful2_u stfiq_iarb_fifo_aful2; /* 7C */ + volatile csr_stfiq_imsg_msg_fifo_cnt_u stfiq_imsg_msg_fifo_cnt; /* 80 */ + volatile csr_stfiq_imsg_stl_stf_msg_cnt_u stfiq_imsg_stl_stf_msg_cnt; /* 84 */ + volatile csr_stfiq_ritf_fifo_cnt0_u stfiq_ritf_fifo_cnt0; /* 88 */ + volatile csr_stfiq_ritf_fifo_cnt1_u stfiq_ritf_fifo_cnt1; /* 8C */ + volatile csr_stfiq_iarb_fifo_cnt0_u stfiq_iarb_fifo_cnt0; /* 90 */ + volatile csr_stfiq_iarb_fifo_cnt1_u stfiq_iarb_fifo_cnt1; /* 94 */ + volatile csr_stfiq_iarb_fifo_cnt2_u stfiq_iarb_fifo_cnt2; /* 98 */ + volatile csr_stfiq_mem_init_done_u stfiq_mem_init_done; /* 9C */ + volatile csr_stfiq_int_vector_u stfiq_int_vector; /* A0 */ + volatile csr_stfiq_int_u stfiq_int; /* A4 */ + volatile csr_stfiq_int_en_u stfiq_int_en; /* A8 */ + volatile csr_stfiq_int0_sticky_u stfiq_int0_sticky; /* AC */ + volatile csr_stfiq_int1_sticky_u stfiq_int1_sticky; /* B0 */ + volatile csr_stfiq_int2_sticky_u stfiq_int2_sticky; /* C8 */ + volatile csr_stfiq_int3_sticky_u stfiq_int3_sticky; /* E0 */ + volatile csr_stfiq_int4_sticky_u stfiq_int4_sticky; /* E4 */ + volatile csr_stfiq_indrect_ctrl_u stfiq_indrect_ctrl; /* E8 */ + volatile csr_stfiq_indrect_timeout_u stfiq_indrect_timeout; /* EC */ + volatile csr_stfiq_indrect_dat0_u stfiq_indrect_dat0; /* F0 */ + volatile csr_stfiq_indrect_dat1_u stfiq_indrect_dat1; /* F4 */ + volatile csr_stfiq_indrect_dat2_u stfiq_indrect_dat2; /* F8 */ + volatile csr_stfiq_indrect_dat3_u stfiq_indrect_dat3; /* FC */ + volatile csr_stfiq_indrect_dat4_u stfiq_indrect_dat4; /* 100 */ + volatile csr_stfiq_indrect_dat5_u stfiq_indrect_dat5; /* 104 */ + volatile csr_stfiq_indrect_dat6_u stfiq_indrect_dat6; /* 108 */ + volatile csr_stfiq_prefetch_req_cnt0_u stfiq_prefetch_req_cnt0; /* 10C */ + volatile csr_stfiq_prefetch_req_cnt1_u stfiq_prefetch_req_cnt1; /* 110 */ + volatile csr_stfiq_prefetch_rsp_cnt0_u stfiq_prefetch_rsp_cnt0; /* 114 */ + volatile csr_stfiq_prefetch_rsp_cnt1_u stfiq_prefetch_rsp_cnt1; /* 118 */ + volatile csr_stfiq_cnt_db_u stfiq_cnt_db; /* 11C */ + volatile csr_stfiq_cnt_tmr_u stfiq_cnt_tmr; /* 120 */ + volatile csr_stfiq_cnt_tsk_u stfiq_cnt_tsk; /* 124 */ + volatile csr_stfiq_cnt_fcnp_u stfiq_cnt_fcnp; /* 128 */ + volatile csr_stfiq_cnt_msg_schedule_u stfiq_cnt_msg_schedule; /* 12C */ + volatile csr_stfiq_earb_roce_rd_pro_type0_u stfiq_earb_roce_rd_pro_type0; /* 130 */ + volatile csr_stfiq_iqm_fret_err_drop0_u stfiq_iqm_fret_err_drop0; /* 134 */ + volatile csr_stfiq_iqm_fret_err_drop1_u stfiq_iqm_fret_err_drop1; /* 138 */ + volatile csr_stfiq_iqm_fret_err_drop2_u stfiq_iqm_fret_err_drop2; /* 13C */ + volatile csr_stfiq_iqm_fret_err_drop3_u stfiq_iqm_fret_err_drop3; /* 140 */ + volatile csr_stfiq_ifp_start_time_cnt_u stfiq_ifp_start_time_cnt; /* 144 */ + volatile csr_stfiq_qry_fifo_aful_u stfiq_qry_fifo_aful; /* 148 */ + volatile csr_stfiq_qry_fifo_cnt_u stfiq_qry_fifo_cnt; /* 14C */ + volatile csr_stfiq_icdq_sqd_bp_u stfiq_icdq_sqd_bp; /* 150 */ + volatile csr_stfiq_latency_cfg_u stfiq_latency_cfg; /* 154 */ + volatile csr_stfiq_latency_sta_u stfiq_latency_sta; /* 158 */ + volatile csr_stfiq_sample_tmr_u stfiq_sample_tmr; /* 15C */ + volatile csr_stfiq_earb_roce_rd_pro_type1_u stfiq_earb_roce_rd_pro_type1; /* 160 */ + volatile csr_stfiq_earb_roce_rd_pro_type2_u stfiq_earb_roce_rd_pro_type2; /* 164 */ + volatile csr_stfiq_earb_roce_rd_pro_type3_u stfiq_earb_roce_rd_pro_type3; /* 168 */ + volatile csr_stfiq_quf_pg_cfg_u stfiq_quf_pg_cfg; /* 16C */ + volatile csr_stfiq_cntx_timout_wattermark_u stfiq_cntx_timout_wattermark; /* 170 */ + volatile csr_stfiq_fake_vf_mask_u stfiq_fake_vf_mask; /* 174 */ + volatile csr_cmd_pkt_ichannel0_u cmd_pkt_ichannel0; /* 178 */ + volatile csr_cmd_pkt_ichannel1_u cmd_pkt_ichannel1; /* 17C */ + volatile csr_csr_iqm_cfg_threshold_u csr_iqm_cfg_threshold; /* 180 */ + volatile csr_csr_iqm_time_interval_u csr_iqm_time_interval; /* 184 */ + volatile csr_csr_iqm_time_out_cnt_u csr_iqm_time_out_cnt; /* 188 */ + volatile csr_csr_iqm_time_out_queue0_u csr_iqm_time_out_queue0; /* 18C */ + volatile csr_csr_iqm_time_out_queue1_u csr_iqm_time_out_queue1; /* 190 */ + volatile csr_csr_iqm_time_out_start_u csr_iqm_time_out_start; /* 194 */ +} S_qu_stfiq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_stfiq_csr */ +extern volatile S_qu_stfiq_csr_REGS_TYPE *gopqu_stfiq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSTFIQ_MODE_csr_stfiq_tpmem_timing_ctrl(unsigned int ucsr_stfiq_tpmem_timing_ctrl); +int iSetSTFIQ_MODE_csr_stfiq_spmem_timing_ctrl(unsigned int ucsr_stfiq_spmem_timing_ctrl); +int iSetSTFIQ_MODE_csr_stfiq_tpmem_power_ctrl(unsigned int ucsr_stfiq_tpmem_power_ctrl); +int iSetSTFIQ_MODE_csr_stfiq_spmem_power_ctrl(unsigned int ucsr_stfiq_spmem_power_ctrl); +int iSetSTFIQ_MODE_csr_stfiq_mem_init_start(unsigned int ucsr_stfiq_mem_init_start); +int iSetSTFIQ_MODE_csr_stfiq_mem_ecc_bypass(unsigned int ucsr_stfiq_mem_ecc_bypass); +int iSetSTFIQ_MODE_csr_stfiq_mem_ecc_req(unsigned int ucsr_stfiq_mem_ecc_req); +int iSetSTFIQ_MODE_csr_stfiq_cntx_sf_watchdog_en(unsigned int ucsr_stfiq_cntx_sf_watchdog_en); +int iSetSTFIQ_IMSG_BM_INI_imsg_bm_ini_start(unsigned int uimsg_bm_ini_start); +int iSetSTFIQ_IMSG_BM_INI_imsg_bm_ini_depth(unsigned int uimsg_bm_ini_depth); +int iSetSTFIQ_IMSG_BM_INI_imsg_bm_time_out_interval_cfg(unsigned int uimsg_bm_time_out_interval_cfg); +int iSetSTFIQ_IMSG_BM_TIME_OUT_INTERVAL_imsg_bm_time_out_interval(unsigned int uimsg_bm_time_out_interval); +int iSetSTFIQ_IMSG_BM_INFOR_imsg_bm_ini_busy(unsigned int uimsg_bm_ini_busy); +int iSetSTFIQ_IMSG_BM_INFOR_imsg_bm_ini_done(unsigned int uimsg_bm_ini_done); +int iSetSTFIQ_IMSG_PRO_TYPE_imsg_stf_tmr_pro_typ(unsigned int uimsg_stf_tmr_pro_typ); +int iSetSTFIQ_IMSG_PRO_TYPE_imsg_stl_tmr_pro_typ(unsigned int uimsg_stl_tmr_pro_typ); +int iSetSTFIQ_IMSG_PRO_TYPE_imsg_fcnp_pro_typ(unsigned int uimsg_fcnp_pro_typ); +int iSetSTFIQ_IMSG_PRO_TYPE_imsg_event_pro_typ(unsigned int uimsg_event_pro_typ); +int iSetSTFIQ_IMSG_SOURCE_LIMIT_imsg_msg_pfhid_limit(unsigned int uimsg_msg_pfhid_limit); +int iSetSTFIQ_IMSG_SOURCE_LIMIT_imsg_msg_pfhid_stl_task_tmr_limit(unsigned int uimsg_msg_pfhid_stl_task_tmr_limit); +int iSetSTFIQ_IMSG_DBE_PSH_CPB_imsg_dbe_psh_cpb(unsigned int uimsg_dbe_psh_cpb); +int iSetSTFIQ_IMSG_TMR_SRC_DEFINE0_imsg_tmr_stl_src(unsigned int uimsg_tmr_stl_src); +int iSetSTFIQ_IMSG_TMR_SRC_DEFINE0_imsg_tmr_stf_src(unsigned int uimsg_tmr_stf_src); +int iSetSTFIQ_IMSG_EVENT_SRC_DEFINE1_imsg_tsk_src(unsigned int uimsg_tsk_src); +int iSetSTFIQ_IMSG_EVENT_SRC_DEFINE1_imsg_fcnp_src(unsigned int uimsg_fcnp_src); +int iSetSTFIQ_CLOSE_FQ_LOAD_BALANCE_close_fq_load_balance(unsigned int uclose_fq_load_balance); +int iSetSTFIQ_FQ_QPC_RSP_FIFO_AFUL_stfiq_fq0_qpc_rsp_aful(unsigned int ustfiq_fq0_qpc_rsp_aful); +int iSetSTFIQ_FQ_QPC_RSP_FIFO_AFUL_stfiq_fq1_qpc_rsp_aful(unsigned int ustfiq_fq1_qpc_rsp_aful); +int iSetSTFIQ_FQ_QPC_RSP_FIFO_CNT_stfiq_fq0_qpc_rsp_cnt(unsigned int ustfiq_fq0_qpc_rsp_cnt); +int iSetSTFIQ_FQ_QPC_RSP_FIFO_CNT_stfiq_fq1_qpc_rsp_cnt(unsigned int ustfiq_fq1_qpc_rsp_cnt); +int iSetSTFIQ_RITF_PERX_IO_LAST_NUM_perx_io_last_flag_num(unsigned int uperx_io_last_flag_num); +int iSetSTFIQ_RITF_PERX_IO_FIRST_NUM_perx_io_first_flag_num(unsigned int uperx_io_first_flag_num); +int iSetSTFIQ_RITF_IPSUTX_IO_LAST_NUM_ipsutx_io_last_flag_num(unsigned int uipsutx_io_last_flag_num); +int iSetSTFIQ_RITF_IPSUTX_IO_FIRST_NUM_ipsutx_io_first_flag_num(unsigned int uipsutx_io_first_flag_num); +int iSetSTFIQ_RITF_IO_RSP_NUM_ritf_io_rsp_num(unsigned int uritf_io_rsp_num); +int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_stffq_lb(unsigned int ustfiq_wrr_weight_stffq_lb); +int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_oq_lb(unsigned int ustfiq_wrr_weight_oq_lb); +int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_icdq(unsigned int ustfiq_wrr_weight_icdq); +int iSetSTFIQ_WRR_WEIGHT_ENQ0_stfiq_wrr_weight_stlfq_dsp(unsigned int ustfiq_wrr_weight_stlfq_dsp); +int iSetSTFIQ_WRR_WEIGHT_ENQ1_stfiq_wrr_weight_stliq_ret(unsigned int ustfiq_wrr_weight_stliq_ret); +int iSetSTFIQ_FLB_UPDATE_PD_EN_flb_update_pd_en(unsigned int uflb_update_pd_en); +int iSetSTFIQ_FLB_UPDATE_PD_EN_flb_update_epd_en(unsigned int uflb_update_epd_en); +int iSetSTFIQ_ERRPKT_DROP_EN0_errpkt_drop_en0(unsigned int uerrpkt_drop_en0); +int iSetSTFIQ_ERRPKT_DROP_EN1_errpkt_drop_en1(unsigned int uerrpkt_drop_en1); +int iSetSTFIQ_ERRPKT_DROP_EN2_errpkt_drop_en2(unsigned int uerrpkt_drop_en2); +int iSetSTFIQ_ERRPKT_DROP_EN3_errpkt_drop_en3(unsigned int uerrpkt_drop_en3); +int iSetSTFIQ_WRR_WEIGHT_ENQ2_stfiq_wrr_weight_qry(unsigned int ustfiq_wrr_weight_qry); +int iSetSTFIQ_WRR_WEIGHT_ENQ2_stfiq_wrr_weight_enq(unsigned int ustfiq_wrr_weight_enq); +int iSetSTFIQ_IMSG_MSG_FIFO_AF_imsg_dbe_aful(unsigned int uimsg_dbe_aful); +int iSetSTFIQ_IMSG_MSG_FIFO_AF_fq0_timer_aful(unsigned int ufq0_timer_aful); +int iSetSTFIQ_IMSG_MSG_FIFO_AF_fq1_timer_aful(unsigned int ufq1_timer_aful); +int iSetSTFIQ_IMSG_STL_STF_MSG_AF_stlmsg_aful(unsigned int ustlmsg_aful); +int iSetSTFIQ_IMSG_STL_STF_MSG_AF_stfmsg_aful(unsigned int ustfmsg_aful); +int iSetSTFIQ_RITF_FIFO_AFUL0_pe_event_aful(unsigned int upe_event_aful); +int iSetSTFIQ_RITF_FIFO_AFUL0_fcnp_event_aful(unsigned int ufcnp_event_aful); +int iSetSTFIQ_RITF_FIFO_AFUL0_perx_event_aful(unsigned int uperx_event_aful); +int iSetSTFIQ_RITF_FIFO_AFUL0_ipsutx_event_aful(unsigned int uipsutx_event_aful); +int iSetSTFIQ_RITF_FIFO_AFUL1_taskid_order_aful(unsigned int utaskid_order_aful); +int iSetSTFIQ_IARB_FIFO_AFUL0_stor_icdq_infor_aful(unsigned int ustor_icdq_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL0_stor_stffq0_flb_infor_aful(unsigned int ustor_stffq0_flb_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL0_stor_stffq1_flb_infor_aful(unsigned int ustor_stffq1_flb_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL0_stor_oq_olb_infor_aful(unsigned int ustor_oq_olb_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stliq_ret_infor_aful(unsigned int ustor_stliq_ret_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stlfq_dsp_infor_aful(unsigned int ustor_stlfq_dsp_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stffq0_qry_infor_aful(unsigned int ustor_stffq0_qry_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL1_stor_stffq1_qry_infor_aful(unsigned int ustor_stffq1_qry_infor_aful); +int iSetSTFIQ_IARB_FIFO_AFUL2_stor_pd_infor_aful(unsigned int ustor_pd_infor_aful); +int iSetSTFIQ_IMSG_MSG_FIFO_CNT_imsg_dbe_cnt(unsigned int uimsg_dbe_cnt); +int iSetSTFIQ_IMSG_MSG_FIFO_CNT_fq0_timer_cnt(unsigned int ufq0_timer_cnt); +int iSetSTFIQ_IMSG_MSG_FIFO_CNT_fq1_timer_cnt(unsigned int ufq1_timer_cnt); +int iSetSTFIQ_IMSG_STL_STF_MSG_CNT_stlmsg_cnt(unsigned int ustlmsg_cnt); +int iSetSTFIQ_IMSG_STL_STF_MSG_CNT_stfmsg_cnt0(unsigned int ustfmsg_cnt0); +int iSetSTFIQ_IMSG_STL_STF_MSG_CNT_stfmsg_cnt1(unsigned int ustfmsg_cnt1); +int iSetSTFIQ_RITF_FIFO_CNT0_pe_event_cnt(unsigned int upe_event_cnt); +int iSetSTFIQ_RITF_FIFO_CNT0_fcnp_event_cnt(unsigned int ufcnp_event_cnt); +int iSetSTFIQ_RITF_FIFO_CNT0_perx_event_cnt(unsigned int uperx_event_cnt); +int iSetSTFIQ_RITF_FIFO_CNT0_ipsutx_event_cnt(unsigned int uipsutx_event_cnt); +int iSetSTFIQ_RITF_FIFO_CNT1_taskid_order_cnt(unsigned int utaskid_order_cnt); +int iSetSTFIQ_IARB_FIFO_CNT0_stor_icdq_infor_cnt(unsigned int ustor_icdq_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT0_stor_stffq0_flb_infor_cnt(unsigned int ustor_stffq0_flb_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT0_stor_stffq1_flb_infor_cnt(unsigned int ustor_stffq1_flb_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT0_stor_oq_olb_infor_cnt(unsigned int ustor_oq_olb_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT1_stor_stliq_ret_infor_cnt(unsigned int ustor_stliq_ret_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT1_stor_stlfq_dsp_infor_cnt(unsigned int ustor_stlfq_dsp_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT1_stor_stffq0_qry_infor_cnt(unsigned int ustor_stffq0_qry_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT1_stor_stffq1_qry_infor_cnt(unsigned int ustor_stffq1_qry_infor_cnt); +int iSetSTFIQ_IARB_FIFO_CNT2_stor_pd_infor_cnt(unsigned int ustor_pd_infor_cnt); +int iSetSTFIQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done); +int iSetSTFIQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSTFIQ_INT_VECTOR_enable(unsigned int uenable); +int iSetSTFIQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSTFIQ_INT_int_data(unsigned int uint_data); +int iSetSTFIQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetSTFIQ_INT_EN_int_en(unsigned int uint_en); +int iSetSTFIQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetSTFIQ_INT0_STICKY_imsg_bm_time_out_rpt(unsigned int uimsg_bm_time_out_rpt); +int iSetSTFIQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetSTFIQ_INT0_STICKY_stfiq_int0_sticky(unsigned int ustfiq_int0_sticky); +int iSetSTFIQ_INT1_STICKY_stfiq_fifo_overflow0(unsigned int ustfiq_fifo_overflow0); +int iSetSTFIQ_INT1_STICKY_int_insrt10(unsigned int uint_insrt10); +int iSetSTFIQ_INT1_STICKY_stfiq_int1_sticky0(unsigned int ustfiq_int1_sticky0); +int iSetSTFIQ_INT2_STICKY_stfiq_fifo_underflow0(unsigned int ustfiq_fifo_underflow0); +int iSetSTFIQ_INT2_STICKY_int_insrt20(unsigned int uint_insrt20); +int iSetSTFIQ_INT2_STICKY_stfiq_int2_sticky0(unsigned int ustfiq_int2_sticky0); +int iSetSTFIQ_INT3_STICKY_stfiq_ram_ecc_cerr(unsigned int ustfiq_ram_ecc_cerr); +int iSetSTFIQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetSTFIQ_INT3_STICKY_stfiq_int3_sticky(unsigned int ustfiq_int3_sticky); +int iSetSTFIQ_INT4_STICKY_stfiq_ram_ecc_ucerr(unsigned int ustfiq_ram_ecc_ucerr); +int iSetSTFIQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4); +int iSetSTFIQ_INT4_STICKY_stfiq_int4_sticky(unsigned int ustfiq_int4_sticky); +int iSetSTFIQ_INDRECT_CTRL_csr_stfiq_indrect_ctrl(unsigned int ucsr_stfiq_indrect_ctrl); +int iSetSTFIQ_INDRECT_TIMEOUT_csr_stfiq_indrect_timeout(unsigned int ucsr_stfiq_indrect_timeout); +int iSetSTFIQ_INDRECT_DAT0_csr_stfiq_indrect_data0(unsigned int ucsr_stfiq_indrect_data0); +int iSetSTFIQ_INDRECT_DAT1_csr_stfiq_indrect_data1(unsigned int ucsr_stfiq_indrect_data1); +int iSetSTFIQ_INDRECT_DAT2_csr_stfiq_indrect_data2(unsigned int ucsr_stfiq_indrect_data2); +int iSetSTFIQ_INDRECT_DAT3_csr_stfiq_indrect_data3(unsigned int ucsr_stfiq_indrect_data3); +int iSetSTFIQ_INDRECT_DAT4_csr_stfiq_indrect_data4(unsigned int ucsr_stfiq_indrect_data4); +int iSetSTFIQ_INDRECT_DAT5_csr_stfiq_indrect_data5(unsigned int ucsr_stfiq_indrect_data5); +int iSetSTFIQ_INDRECT_DAT6_csr_stfiq_indrect_data6(unsigned int ucsr_stfiq_indrect_data6); +int iSetSTFIQ_PREFETCH_REQ_CNT0_stfiq_csr_prefetch_req_inc0(unsigned int ustfiq_csr_prefetch_req_inc0); +int iSetSTFIQ_PREFETCH_REQ_CNT1_stfiq_csr_prefetch_req_inc1(unsigned int ustfiq_csr_prefetch_req_inc1); +int iSetSTFIQ_PREFETCH_RSP_CNT0_stfiq_csr_prefetch_rsp_cnt0(unsigned int ustfiq_csr_prefetch_rsp_cnt0); +int iSetSTFIQ_PREFETCH_RSP_CNT1_stfiq_csr_prefetch_rsp_cnt1(unsigned int ustfiq_csr_prefetch_rsp_cnt1); +int iSetSTFIQ_CNT_DB_stfiq_csr_cnt_db_inc(unsigned int ustfiq_csr_cnt_db_inc); +int iSetSTFIQ_CNT_TMR_stfiq_csr_cnt_tmr_inc(unsigned int ustfiq_csr_cnt_tmr_inc); +int iSetSTFIQ_CNT_TSK_stfiq_csr_cnt_tsk_inc(unsigned int ustfiq_csr_cnt_tsk_inc); +int iSetSTFIQ_CNT_FCNP_stfiq_csr_cnt_fcnp_inc(unsigned int ustfiq_csr_cnt_fcnp_inc); +int iSetSTFIQ_CNT_MSG_SCHEDULE_stfiq_csr_cnt_msg_schedule_inc(unsigned int ustfiq_csr_cnt_msg_schedule_inc); +int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE0_csr_stfiq_roce_rd_pro_type0(unsigned int ucsr_stfiq_roce_rd_pro_type0); +int iSetSTFIQ_IQM_FRET_ERR_DROP0_fret_err_drop_en0(unsigned int ufret_err_drop_en0); +int iSetSTFIQ_IQM_FRET_ERR_DROP1_fret_err_drop_en1(unsigned int ufret_err_drop_en1); +int iSetSTFIQ_IQM_FRET_ERR_DROP2_fret_err_drop_en2(unsigned int ufret_err_drop_en2); +int iSetSTFIQ_IQM_FRET_ERR_DROP3_fret_err_drop_en3(unsigned int ufret_err_drop_en3); +int iSetSTFIQ_IFP_START_TIME_CNT_csr_stfiq_ifp_start_time_cnt(unsigned int ucsr_stfiq_ifp_start_time_cnt); +int iSetSTFIQ_QRY_FIFO_AFUL_qry_eop_gain_fifo_af_th(unsigned int uqry_eop_gain_fifo_af_th); +int iSetSTFIQ_QRY_FIFO_AFUL_cntxsf_fifo_af_th(unsigned int ucntxsf_fifo_af_th); +int iSetSTFIQ_QRY_FIFO_CNT_qry_eop_gain_fifo_fill(unsigned int uqry_eop_gain_fifo_fill); +int iSetSTFIQ_QRY_FIFO_CNT_cntxsf_fifo_fill(unsigned int ucntxsf_fifo_fill); +int iSetSTFIQ_ICDQ_SQD_BP_csr_iqm_cfg_sqd_bp(unsigned int ucsr_iqm_cfg_sqd_bp); +int iSetSTFIQ_LATENCY_CFG_csr_stfiq_sample_mode(unsigned int ucsr_stfiq_sample_mode); +int iSetSTFIQ_LATENCY_CFG_csr_stfiq_spec_port_en(unsigned int ucsr_stfiq_spec_port_en); +int iSetSTFIQ_LATENCY_CFG_csr_stfiq_done_clr(unsigned int ucsr_stfiq_done_clr); +int iSetSTFIQ_LATENCY_CFG_csr_stfiq_spec_port_num(unsigned int ucsr_stfiq_spec_port_num); +int iSetSTFIQ_LATENCY_CFG_csr_stfiq_spec_pptr_typ(unsigned int ucsr_stfiq_spec_pptr_typ); +int iSetSTFIQ_LATENCY_STA_stfiq_csr_sample_done(unsigned int ustfiq_csr_sample_done); +int iSetSTFIQ_SAMPLE_TMR_stfiq_csr_sample_tmr(unsigned int ustfiq_csr_sample_tmr); +int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE1_csr_stfiq_roce_rd_pro_type1(unsigned int ucsr_stfiq_roce_rd_pro_type1); +int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE2_csr_stfiq_roce_rd_pro_type2(unsigned int ucsr_stfiq_roce_rd_pro_type2); +int iSetSTFIQ_EARB_ROCE_RD_PRO_TYPE3_csr_stfiq_roce_rd_pro_type3(unsigned int ucsr_stfiq_roce_rd_pro_type3); +int iSetSTFIQ_QUF_PG_CFG_csr_stfiq_quf_pg_cfg(unsigned int ucsr_stfiq_quf_pg_cfg); +int iSetSTFIQ_CNTX_TIMOUT_WATTERMARK_csr_cntx_sf_timeout_watermark(unsigned int ucsr_cntx_sf_timeout_watermark); +int iSetSTFIQ_FAKE_VF_MASK_csr_stfiq_fake_vf_mask(unsigned int ucsr_stfiq_fake_vf_mask); +int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel0(unsigned int ucmd_pkt_ichannel0); +int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel1(unsigned int ucmd_pkt_ichannel1); +int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel2(unsigned int ucmd_pkt_ichannel2); +int iSetCMD_PKT_ICHANNEL0_cmd_pkt_ichannel3(unsigned int ucmd_pkt_ichannel3); +int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel4(unsigned int ucmd_pkt_ichannel4); +int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel5(unsigned int ucmd_pkt_ichannel5); +int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel6(unsigned int ucmd_pkt_ichannel6); +int iSetCMD_PKT_ICHANNEL1_cmd_pkt_ichannel7(unsigned int ucmd_pkt_ichannel7); +int iSetCSR_IQM_CFG_THRESHOLD_csr_iqm_cfg_threshold0(unsigned int ucsr_iqm_cfg_threshold0); +int iSetCSR_IQM_CFG_THRESHOLD_csr_iqm_cfg_threshold1(unsigned int ucsr_iqm_cfg_threshold1); +int iSetCSR_IQM_TIME_INTERVAL_csr_iqm_time_interval(unsigned int ucsr_iqm_time_interval); +int iSetCSR_IQM_TIME_OUT_CNT_csr_iqm_time_out_cnt(unsigned int ucsr_iqm_time_out_cnt); +int iSetCSR_IQM_TIME_OUT_QUEUE0_csr_iqm_time_out_queue0(unsigned int ucsr_iqm_time_out_queue0); +int iSetCSR_IQM_TIME_OUT_QUEUE1_csr_iqm_time_out_queue1(unsigned int ucsr_iqm_time_out_queue1); +int iSetCSR_IQM_TIME_OUT_START_csr_iqm_time_out_start(unsigned int ucsr_iqm_time_out_start); + + +#endif // STFIQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfiq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfiq_reg_offset.h new file mode 100644 index 000000000..33dac5139 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfiq_reg_offset.h @@ -0,0 +1,148 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : stfiq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : V100 +// Date : 2018/12/04 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/10/17 10:06:12 Create file +// ****************************************************************************** + +#ifndef STFIQ_REG_OFFSET_H +#define STFIQ_REG_OFFSET_H + +/* QU_STFIQ_CSR Base address of Module's Register */ +#define CSR_QU_STFIQ_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* QU_STFIQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_STFIQ_CSR_STFIQ_MODE_REG (CSR_QU_STFIQ_CSR_BASE + 0x0) /* 模式配置寄存器 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_BM_INI_REG (CSR_QU_STFIQ_CSR_BASE + 0x4) /* 初始化IMSG模块中的bitmap */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_BM_TIME_OUT_INTERVAL_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x8) /* 配置IMSG模块的bitmap老化时间 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_BM_INFOR_REG (CSR_QU_STFIQ_CSR_BASE + 0xC) /* 查询IMSG模块中bitmap相关信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_PRO_TYPE_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x10) /* 配置task event/fcnp/stateless timer/stateful timer的pro type */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_SOURCE_LIMIT_REG (CSR_QU_STFIQ_CSR_BASE + 0x14) /* 配置Bitmap使用水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_DBE_PSH_CPB_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x18) /* 配置待处理DBE的sev type类型是否需要推送信息给CPB */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_TMR_SRC_DEFINE0_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x1C) /* 配置stateful timer msg与stateless timer msg的源信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_EVENT_SRC_DEFINE1_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x20) /* 配置fcnp event与task event的源信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_CLOSE_FQ_LOAD_BALANCE_REG (CSR_QU_STFIQ_CSR_BASE + 0x24) /* 配置fq load balance策略 */ +#define CSR_QU_STFIQ_CSR_STFIQ_FQ_QPC_RSP_FIFO_AFUL_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x28) /* 配置存放FQ返回QPC的fifo aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_FQ_QPC_RSP_FIFO_CNT_REG (CSR_QU_STFIQ_CSR_BASE + 0x2C) /* 获取存放FQ返回QPC的fifo cnt \ + */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_PERX_IO_LAST_NUM_REG (CSR_QU_STFIQ_CSR_BASE + 0x30) /* rx侧IO eop统计个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_PERX_IO_FIRST_NUM_REG (CSR_QU_STFIQ_CSR_BASE + 0x34) /* rx侧IO sop统计个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_IPSUTX_IO_LAST_NUM_REG (CSR_QU_STFIQ_CSR_BASE + 0x38) /* tx侧IO eop统计个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_IPSUTX_IO_FIRST_NUM_REG (CSR_QU_STFIQ_CSR_BASE + 0x3C) /* tx侧IO sop统计个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_IO_RSP_NUM_REG (CSR_QU_STFIQ_CSR_BASE + 0x40) /* IO统计个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_WRR_WEIGHT_ENQ0_REG (CSR_QU_STFIQ_CSR_BASE + 0x44) /* 配置入队权重 */ +#define CSR_QU_STFIQ_CSR_STFIQ_WRR_WEIGHT_ENQ1_REG (CSR_QU_STFIQ_CSR_BASE + 0x48) /* 配置入队权重 */ +#define CSR_QU_STFIQ_CSR_STFIQ_FLB_UPDATE_PD_EN_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x4C) /* 配置FQ发出的event loop入队操作是否需要刷新PD */ +#define CSR_QU_STFIQ_CSR_STFIQ_ERRPKT_DROP_EN0_REG (CSR_QU_STFIQ_CSR_BASE + 0x50) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_ERRPKT_DROP_EN1_REG (CSR_QU_STFIQ_CSR_BASE + 0x54) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_ERRPKT_DROP_EN2_REG (CSR_QU_STFIQ_CSR_BASE + 0x58) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_ERRPKT_DROP_EN3_REG (CSR_QU_STFIQ_CSR_BASE + 0x5C) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_WRR_WEIGHT_ENQ2_REG (CSR_QU_STFIQ_CSR_BASE + 0x60) /* 配置入队和FQ查询权重 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_MSG_FIFO_AF_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x64) /* 配置MQM DB及FQ timer信息FIFO的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_STL_STF_MSG_AF_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x68) /* 配置STL/STF信息FIFO的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_FIFO_AFUL0_REG (CSR_QU_STFIQ_CSR_BASE + 0x6C) /* 配置RITF模块中fifo的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_FIFO_AFUL1_REG (CSR_QU_STFIQ_CSR_BASE + 0x70) /* 配置RITF模块中fifo的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IARB_FIFO_AFUL0_REG (CSR_QU_STFIQ_CSR_BASE + 0x74) /* 配置IARB模块中fifo的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IARB_FIFO_AFUL1_REG (CSR_QU_STFIQ_CSR_BASE + 0x78) /* 配置IARB模块中fifo的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IARB_FIFO_AFUL2_REG (CSR_QU_STFIQ_CSR_BASE + 0x7C) /* 配置IARB模块中fifo的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_MSG_FIFO_CNT_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x80) /* MQM DB及FQ timer信息FIFO内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IMSG_STL_STF_MSG_CNT_REG (CSR_QU_STFIQ_CSR_BASE + 0x84) /* STL/STF信息FIFO内的数据个数 \ + */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_FIFO_CNT0_REG (CSR_QU_STFIQ_CSR_BASE + 0x88) /* RITF模块中fifo内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_RITF_FIFO_CNT1_REG (CSR_QU_STFIQ_CSR_BASE + 0x8C) /* RITF模块中fifo内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IARB_FIFO_CNT0_REG (CSR_QU_STFIQ_CSR_BASE + 0x90) /* IARB模块中fifo内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IARB_FIFO_CNT1_REG (CSR_QU_STFIQ_CSR_BASE + 0x94) /* IARB模块中fifo内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_IARB_FIFO_CNT2_REG (CSR_QU_STFIQ_CSR_BASE + 0x98) /* IARB模块中fifo内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_MEM_INIT_DONE_REG (CSR_QU_STFIQ_CSR_BASE + 0x9C) /* STFIQ中memory初始化完毕标志 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT_VECTOR_REG (CSR_QU_STFIQ_CSR_BASE + 0xA0) /* 中断向量 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT_REG (CSR_QU_STFIQ_CSR_BASE + 0xA4) /* 中断状态 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT_EN_REG (CSR_QU_STFIQ_CSR_BASE + 0xA8) /* 中断屏蔽 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT0_STICKY_REG (CSR_QU_STFIQ_CSR_BASE + 0xAC) /* 中断0的sticky信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT1_STICKY_REG (CSR_QU_STFIQ_CSR_BASE + 0xB0) /* 中断1的sticky信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT2_STICKY_REG (CSR_QU_STFIQ_CSR_BASE + 0xC8) /* 中断2的sticky信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT3_STICKY_REG (CSR_QU_STFIQ_CSR_BASE + 0xE0) /* 中断3的sticky信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INT4_STICKY_REG (CSR_QU_STFIQ_CSR_BASE + 0xE4) /* 中断4的sticky信息 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_CTRL_REG (CSR_QU_STFIQ_CSR_BASE + 0xE8) /* STFIQ间接寻址控制寄存器 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_TIMEOUT_REG (CSR_QU_STFIQ_CSR_BASE + 0xEC) /* IQ间接寻址Timeout水线配置 */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT0_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0xF0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT1_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0xF4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT2_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0xF8) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT3_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0xFC) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT4_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x100) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT5_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x104) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_INDRECT_DAT6_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x108) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STFIQ_CSR_STFIQ_PREFETCH_REQ_CNT0_REG (CSR_QU_STFIQ_CSR_BASE + 0x10C) /* 向STFFQ0发起的预取QPC次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_PREFETCH_REQ_CNT1_REG (CSR_QU_STFIQ_CSR_BASE + 0x110) /* 向STFFQ1发起的预取QPC次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_PREFETCH_RSP_CNT0_REG (CSR_QU_STFIQ_CSR_BASE + 0x114) /* STFFQ0返回QPC次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_PREFETCH_RSP_CNT1_REG (CSR_QU_STFIQ_CSR_BASE + 0x118) /* STFFQ1返回QPC次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_CNT_DB_REG (CSR_QU_STFIQ_CSR_BASE + 0x11C) /* 接收处理DB次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_CNT_TMR_REG (CSR_QU_STFIQ_CSR_BASE + 0x120) /* 接收处理TMR次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_CNT_TSK_REG (CSR_QU_STFIQ_CSR_BASE + 0x124) /* 接收处理TSK次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_CNT_FCNP_REG (CSR_QU_STFIQ_CSR_BASE + 0x128) /* 接收处理FCNP次数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_CNT_MSG_SCHEDULE_REG (CSR_QU_STFIQ_CSR_BASE + 0x12C) /* 消息被ISCH调度出队的次数统计 */ +#define CSR_QU_STFIQ_CSR_STFIQ_EARB_ROCE_RD_PRO_TYPE0_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x130) /* 配置需要查找pc_ptr_offset表项的ROCE RD pro type */ +#define CSR_QU_STFIQ_CSR_STFIQ_IQM_FRET_ERR_DROP0_REG (CSR_QU_STFIQ_CSR_BASE + 0x134) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_IQM_FRET_ERR_DROP1_REG (CSR_QU_STFIQ_CSR_BASE + 0x138) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_IQM_FRET_ERR_DROP2_REG (CSR_QU_STFIQ_CSR_BASE + 0x13C) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_IQM_FRET_ERR_DROP3_REG (CSR_QU_STFIQ_CSR_BASE + 0x140) /* 配置需要硬件丢弃的err type */ +#define CSR_QU_STFIQ_CSR_STFIQ_IFP_START_TIME_CNT_REG (CSR_QU_STFIQ_CSR_BASE + 0x144) /* 启动IFP调度的周期间隔 */ +#define CSR_QU_STFIQ_CSR_STFIQ_QRY_FIFO_AFUL_REG (CSR_QU_STFIQ_CSR_BASE + 0x148) /* 配置QRY模块中fifo的aful水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_QRY_FIFO_CNT_REG (CSR_QU_STFIQ_CSR_BASE + 0x14C) /* RITF模块中fifo内的数据个数 */ +#define CSR_QU_STFIQ_CSR_STFIQ_ICDQ_SQD_BP_REG (CSR_QU_STFIQ_CSR_BASE + 0x150) /* 配置shallow queue对ICDQ的反压水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_LATENCY_CFG_REG (CSR_QU_STFIQ_CSR_BASE + 0x154) /* STFIQ的时延采样DFX配置 */ +#define CSR_QU_STFIQ_CSR_STFIQ_LATENCY_STA_REG (CSR_QU_STFIQ_CSR_BASE + 0x158) /* STFIQ的时延采样DFX状态 */ +#define CSR_QU_STFIQ_CSR_STFIQ_SAMPLE_TMR_REG (CSR_QU_STFIQ_CSR_BASE + 0x15C) /* STFIQ的时延采样DFX时间 */ +#define CSR_QU_STFIQ_CSR_STFIQ_EARB_ROCE_RD_PRO_TYPE1_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x160) /* 配置需要查找pc_ptr_offset表项的ROCE RD pro type */ +#define CSR_QU_STFIQ_CSR_STFIQ_EARB_ROCE_RD_PRO_TYPE2_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x164) /* 配置需要查找pc_ptr_offset表项的ROCE RD pro type */ +#define CSR_QU_STFIQ_CSR_STFIQ_EARB_ROCE_RD_PRO_TYPE3_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x168) /* 配置需要查找pc_ptr_offset表项的ROCE RD pro type */ +#define CSR_QU_STFIQ_CSR_STFIQ_QUF_PG_CFG_REG (CSR_QU_STFIQ_CSR_BASE + 0x16C) /* 配置FQ */ +#define CSR_QU_STFIQ_CSR_STFIQ_CNTX_TIMOUT_WATTERMARK_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x170) /* QUERY EOP时，等待EOP到来的超时水线 */ +#define CSR_QU_STFIQ_CSR_STFIQ_FAKE_VF_MASK_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x174) /* 配置fake vf maks，将DB中含有的fake VF转换为真实VF。 */ +#define CSR_QU_STFIQ_CSR_CMD_PKT_ICHANNEL0_REG (CSR_QU_STFIQ_CSR_BASE + 0x178) /* 配置host cmd队列的ichannel号 */ +#define CSR_QU_STFIQ_CSR_CMD_PKT_ICHANNEL1_REG (CSR_QU_STFIQ_CSR_BASE + 0x17C) /* 配置host cmd队列的ichannel号 */ +#define CSR_QU_STFIQ_CSR_CSR_IQM_CFG_THRESHOLD_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x180) /* 配置STFIQ队列判断水线，每个报文出队push给tile时，需要将其所在队列的消息深度同该寄存器做比较，如果超过水线，则需要将相关域段置1通知tile \ + */ +#define CSR_QU_STFIQ_CSR_CSR_IQM_TIME_INTERVAL_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x184) /* STFIQ fast return队列轮询的时间间隔 */ +#define CSR_QU_STFIQ_CSR_CSR_IQM_TIME_OUT_CNT_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x188) /* STFIQ fast return队列超时时间设置 */ +#define CSR_QU_STFIQ_CSR_CSR_IQM_TIME_OUT_QUEUE0_REG (CSR_QU_STFIQ_CSR_BASE + 0x18C) /* STFIQ fast return超时的队列ID \ + */ +#define CSR_QU_STFIQ_CSR_CSR_IQM_TIME_OUT_QUEUE1_REG (CSR_QU_STFIQ_CSR_BASE + 0x190) /* STFIQ fast return超时的队列ID \ + */ +#define CSR_QU_STFIQ_CSR_CSR_IQM_TIME_OUT_START_REG \ + (CSR_QU_STFIQ_CSR_BASE + 0x194) /* 启动STFIQ fast return对列超时功能 */ + +#endif // STFIQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfisch_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfisch_c_union_define.h new file mode 100644 index 000000000..c278ec024 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfisch_c_union_define.h @@ -0,0 +1,420 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : stfisch_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/08/26 16:45:09 Create file +// ****************************************************************************** + +#ifndef STFISCH_C_UNION_DEFINE_H +#define STFISCH_C_UNION_DEFINE_H + +/* Define the union csr_cnb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_vector_u; + +/* Define the union csr_isch_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 2; /* [1:0] */ + u32 rsv_2 : 14; /* [15:2] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_int_u; + +/* Define the union csr_isch_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 2; /* [1:0] */ + u32 rsv_3 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_int_en_u; + +/* Define the union csr_isch_th_rls_c_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_rls_c_err : 1; /* [0] */ + u32 th_rls_c_err_insrt : 1; /* [1] */ + u32 th_rls_c_err_info : 8; /* [9:2] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_th_rls_c_error_status_u; + +/* Define the union csr_isch_time_out_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timeout_err : 1; /* [0] */ + u32 timeout_err_insrt : 1; /* [1] */ + u32 timeout_err_info : 8; /* [9:2] */ + u32 rsv_5 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_time_out_error_status_u; + +/* Define the union csr_isch_fq_tile_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq0_tile_map : 4; /* [3:0] */ + u32 fq1_tile_map : 4; /* [7:4] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_fq_tile_map_u; + +/* Define the union csr_isch_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_fq0_bp_st : 1; /* [0] */ + u32 qu_fq0_bp_bypass : 1; /* [1] */ + u32 qu_fq0_bp_set : 1; /* [2] */ + u32 qu_fq1_bp_st : 1; /* [3] */ + u32 qu_fq1_bp_bypass : 1; /* [4] */ + u32 qu_fq1_bp_set : 1; /* [5] */ + u32 rsv_7 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_bp_ctrl_u; + +/* Define the union csr_isch_force_rls_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_id_frc : 8; /* [7:0] */ + u32 ctrl_frc : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_force_rls_ctrl_u; + +/* Define the union csr_isch_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 watchdog_mode : 3; /* [2:0] */ + u32 core_sel_mode : 2; /* [4:3] */ + u32 watch_dog_test_mode : 1; /* [5] */ + u32 srv_type_sel_en : 1; /* [6] */ + u32 rsv_9 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_mod_u; + +/* Define the union csr_isch_tile_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_en : 4; /* [3:0] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_tile_en_u; + +/* Define the union csr_isch_core_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer_cr : 10; /* [9:0] */ + u32 rsv_11 : 2; /* [11:10] */ + u32 cwd_en_cr : 1; /* [12] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 th_en_cr : 4; /* [19:16] */ + u32 pg_id_cr : 4; /* [23:20] */ + u32 rsv_13 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_core_cfg_u; + +/* Define the union csr_isch_channel_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_cnt_ch : 9; /* [8:0] */ + u32 rsv_14 : 3; /* [11:9] */ + u32 pg_id_ch : 4; /* [15:12] */ + u32 wght_ch : 5; /* [20:16] */ + u32 cr_sel_sign_ch : 1; /* [21] */ + u32 rsv_15 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_channel_cfg_u; + +/* Define the union csr_isch_4iq_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wght_iq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_4iq_cfg_u; + +/* Define the union csr_isch_2th_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sta_th2 : 1; /* [0] */ + u32 rsv_16 : 3; /* [3:1] */ + u32 ch_id_th2 : 8; /* [11:4] */ + u32 sta_th3 : 1; /* [12] */ + u32 rsv_17 : 3; /* [15:13] */ + u32 ch_id_th3 : 8; /* [23:16] */ + u32 rsv_18 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_2th_sta1_u; + +/* Define the union csr_isch_2th_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sta_th0 : 1; /* [0] */ + u32 rsv_19 : 3; /* [3:1] */ + u32 ch_id_th0 : 8; /* [11:4] */ + u32 sta_th1 : 1; /* [12] */ + u32 rsv_20 : 3; /* [15:13] */ + u32 ch_id_th1 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_2th_sta2_u; + +/* Define the union csr_isch_core0_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th0_his_cr : 1; /* [0] */ + u32 th1_his_cr : 1; /* [1] */ + u32 th2_his_cr : 1; /* [2] */ + u32 th3_his_cr : 1; /* [3] */ + u32 rsv_22 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_core0_sta_u; + +/* Define the union csr_isch_rls_c_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isch_rls_c_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_rls_c_cnt_u; + +/* Define the union csr_isch_time_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isch_time_out_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_time_out_cnt_u; + +/* Define the union csr_isch_th_rls_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isch_th_rls_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_th_rls_cnt_u; + +/* Define the union csr_isch_th_alc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isch_th_alc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_th_alc_cnt_u; + +/* Define the union csr_isch_tl_idle_th_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isch_tile_idle_th_cnt : 8; /* [7:0] */ + u32 rsv_23 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_tl_idle_th_cnt_u; + +/* Define the union csr_isch_scoreboard_cfg_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 score_en : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_scoreboard_cfg_en_u; + +/* Define the union csr_isch_scoreboard_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 score_th_cfg : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_scoreboard_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cnb_int_vector_u cnb_int_vector; /* 0 */ + volatile csr_isch_int_u isch_int; /* 4 */ + volatile csr_isch_int_en_u isch_int_en; /* 8 */ + volatile csr_isch_th_rls_c_error_status_u isch_th_rls_c_error_status; /* 10 */ + volatile csr_isch_time_out_error_status_u isch_time_out_error_status; /* 14 */ + volatile csr_isch_fq_tile_map_u isch_fq_tile_map; /* 18 */ + volatile csr_isch_bp_ctrl_u isch_bp_ctrl; /* 1C */ + volatile csr_isch_force_rls_ctrl_u isch_force_rls_ctrl; /* 20 */ + volatile csr_isch_mod_u isch_mod; /* 24 */ + volatile csr_isch_tile_en_u isch_tile_en; /* 28 */ + volatile csr_isch_core_cfg_u isch_core_cfg[64]; /* 30 */ + volatile csr_isch_channel_cfg_u isch_channel_cfg[256]; /* 130 */ + volatile csr_isch_4iq_cfg_u isch_4iq_cfg[256]; /* 530 */ + volatile csr_isch_2th_sta1_u isch_2th_sta1[64]; /* 950 */ + volatile csr_isch_2th_sta2_u isch_2th_sta2[64]; /* A50 */ + volatile csr_isch_core0_sta_u isch_core0_sta[64]; /* B50 */ + volatile csr_isch_rls_c_cnt_u isch_rls_c_cnt; /* C54 */ + volatile csr_isch_time_out_cnt_u isch_time_out_cnt; /* C58 */ + volatile csr_isch_th_rls_cnt_u isch_th_rls_cnt; /* C5C */ + volatile csr_isch_th_alc_cnt_u isch_th_alc_cnt; /* C60 */ + volatile csr_isch_tl_idle_th_cnt_u isch_tl_idle_th_cnt[4]; /* C64 */ + volatile csr_isch_scoreboard_cfg_en_u isch_scoreboard_cfg_en; /* C74 */ + volatile csr_isch_scoreboard_cfg_u isch_scoreboard_cfg[16]; /* C78 */ +} S_qu_stfisch_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_stfisch_csr */ +extern volatile S_qu_stfisch_csr_REGS_TYPE *gopqu_stfisch_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCNB_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetCNB_INT_VECTOR_enable(unsigned int uenable); +int iSetCNB_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetISCH_INT_int_data(unsigned int uint_data); +int iSetISCH_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetISCH_INT_EN_int_en(unsigned int uint_en); +int iSetISCH_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetISCH_TH_RLS_C_ERROR_STATUS_th_rls_c_err(unsigned int uth_rls_c_err); +int iSetISCH_TH_RLS_C_ERROR_STATUS_th_rls_c_err_insrt(unsigned int uth_rls_c_err_insrt); +int iSetISCH_TH_RLS_C_ERROR_STATUS_th_rls_c_err_info(unsigned int uth_rls_c_err_info); +int iSetISCH_TIME_OUT_ERROR_STATUS_timeout_err(unsigned int utimeout_err); +int iSetISCH_TIME_OUT_ERROR_STATUS_timeout_err_insrt(unsigned int utimeout_err_insrt); +int iSetISCH_TIME_OUT_ERROR_STATUS_timeout_err_info(unsigned int utimeout_err_info); +int iSetISCH_FQ_TILE_MAP_fq0_tile_map(unsigned int ufq0_tile_map); +int iSetISCH_FQ_TILE_MAP_fq1_tile_map(unsigned int ufq1_tile_map); +int iSetISCH_BP_CTRL_qu_fq0_bp_st(unsigned int uqu_fq0_bp_st); +int iSetISCH_BP_CTRL_qu_fq0_bp_bypass(unsigned int uqu_fq0_bp_bypass); +int iSetISCH_BP_CTRL_qu_fq0_bp_set(unsigned int uqu_fq0_bp_set); +int iSetISCH_BP_CTRL_qu_fq1_bp_st(unsigned int uqu_fq1_bp_st); +int iSetISCH_BP_CTRL_qu_fq1_bp_bypass(unsigned int uqu_fq1_bp_bypass); +int iSetISCH_BP_CTRL_qu_fq1_bp_set(unsigned int uqu_fq1_bp_set); +int iSetISCH_FORCE_RLS_CTRL_th_id_frc(unsigned int uth_id_frc); +int iSetISCH_FORCE_RLS_CTRL_ctrl_frc(unsigned int uctrl_frc); +int iSetISCH_MOD_watchdog_mode(unsigned int uwatchdog_mode); +int iSetISCH_MOD_core_sel_mode(unsigned int ucore_sel_mode); +int iSetISCH_MOD_watch_dog_test_mode(unsigned int uwatch_dog_test_mode); +int iSetISCH_MOD_srv_type_sel_en(unsigned int usrv_type_sel_en); +int iSetISCH_TILE_EN_tile_en(unsigned int utile_en); +int iSetISCH_CORE_CFG_timer_cr(unsigned int utimer_cr); +int iSetISCH_CORE_CFG_cwd_en_cr(unsigned int ucwd_en_cr); +int iSetISCH_CORE_CFG_th_en_cr(unsigned int uth_en_cr); +int iSetISCH_CORE_CFG_pg_id_cr(unsigned int upg_id_cr); +int iSetISCH_CHANNEL_CFG_max_cnt_ch(unsigned int umax_cnt_ch); +int iSetISCH_CHANNEL_CFG_pg_id_ch(unsigned int upg_id_ch); +int iSetISCH_CHANNEL_CFG_wght_ch(unsigned int uwght_ch); +int iSetISCH_CHANNEL_CFG_cr_sel_sign_ch(unsigned int ucr_sel_sign_ch); +int iSetISCH_4IQ_CFG_wght_iq(unsigned int uwght_iq); +int iSetISCH_2TH_STA1_sta_th2(unsigned int usta_th2); +int iSetISCH_2TH_STA1_ch_id_th2(unsigned int uch_id_th2); +int iSetISCH_2TH_STA1_sta_th3(unsigned int usta_th3); +int iSetISCH_2TH_STA1_ch_id_th3(unsigned int uch_id_th3); +int iSetISCH_2TH_STA2_sta_th0(unsigned int usta_th0); +int iSetISCH_2TH_STA2_ch_id_th0(unsigned int uch_id_th0); +int iSetISCH_2TH_STA2_sta_th1(unsigned int usta_th1); +int iSetISCH_2TH_STA2_ch_id_th1(unsigned int uch_id_th1); +int iSetISCH_CORE0_STA_th0_his_cr(unsigned int uth0_his_cr); +int iSetISCH_CORE0_STA_th1_his_cr(unsigned int uth1_his_cr); +int iSetISCH_CORE0_STA_th2_his_cr(unsigned int uth2_his_cr); +int iSetISCH_CORE0_STA_th3_his_cr(unsigned int uth3_his_cr); +int iSetISCH_RLS_C_CNT_isch_rls_c_cnt(unsigned int uisch_rls_c_cnt); +int iSetISCH_TIME_OUT_CNT_isch_time_out_cnt(unsigned int uisch_time_out_cnt); +int iSetISCH_TH_RLS_CNT_isch_th_rls_cnt(unsigned int uisch_th_rls_cnt); +int iSetISCH_TH_ALC_CNT_isch_th_alc_cnt(unsigned int uisch_th_alc_cnt); +int iSetISCH_TL_IDLE_TH_CNT_isch_tile_idle_th_cnt(unsigned int uisch_tile_idle_th_cnt); +int iSetISCH_SCOREBOARD_CFG_EN_score_en(unsigned int uscore_en); +int iSetISCH_SCOREBOARD_CFG_score_th_cfg(unsigned int uscore_th_cfg); + + +#endif // STFISCH_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfisch_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfisch_reg_offset.h new file mode 100644 index 000000000..60746cc46 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stfisch_reg_offset.h @@ -0,0 +1,828 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : stfisch_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/08/26 16:45:09 Create file +// ****************************************************************************** + +#ifndef STFISCH_REG_OFFSET_H +#define STFISCH_REG_OFFSET_H + +/* QU_STFISCH_CSR Base address of Module's Register */ +#define CSR_QU_STFISCH_CSR_BASE (0x4000) + +/* **************************************************************************** */ +/* QU_STFISCH_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_STFISCH_CSR_CNB_INT_VECTOR_REG (CSR_QU_STFISCH_CSR_BASE + 0x0) /* 中断向量 */ +#define CSR_QU_STFISCH_CSR_ISCH_INT_REG (CSR_QU_STFISCH_CSR_BASE + 0x4) /* 中断状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_INT_EN_REG (CSR_QU_STFISCH_CSR_BASE + 0x8) /* 中断使能。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TH_RLS_C_ERROR_STATUS_REG (CSR_QU_STFISCH_CSR_BASE + 0x10) /* 线程释放冲突。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TIME_OUT_ERROR_STATUS_REG (CSR_QU_STFISCH_CSR_BASE + 0x14) /* 线程占用超时中断 */ +#define CSR_QU_STFISCH_CSR_ISCH_FQ_TILE_MAP_REG (CSR_QU_STFISCH_CSR_BASE + 0x18) /* FQ MAP 寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_BP_CTRL_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C) /* ISCH反压控制寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_FORCE_RLS_CTRL_REG (CSR_QU_STFISCH_CSR_BASE + 0x20) /* ISCH强制释放寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_MOD_REG (CSR_QU_STFISCH_CSR_BASE + 0x24) /* ISCH模式控制寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_TILE_EN_REG (CSR_QU_STFISCH_CSR_BASE + 0x28) /* TILE使能开关 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x30) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x34) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x38) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x40) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x44) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x48) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x50) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x54) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x58) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x60) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x64) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x68) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x70) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x74) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x78) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x80) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x84) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x88) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x90) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x94) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x98) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_28_REG (CSR_QU_STFISCH_CSR_BASE + 0xA0) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_29_REG (CSR_QU_STFISCH_CSR_BASE + 0xA4) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_30_REG (CSR_QU_STFISCH_CSR_BASE + 0xA8) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_31_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_32_REG (CSR_QU_STFISCH_CSR_BASE + 0xB0) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_33_REG (CSR_QU_STFISCH_CSR_BASE + 0xB4) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_34_REG (CSR_QU_STFISCH_CSR_BASE + 0xB8) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_35_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_36_REG (CSR_QU_STFISCH_CSR_BASE + 0xC0) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_37_REG (CSR_QU_STFISCH_CSR_BASE + 0xC4) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_38_REG (CSR_QU_STFISCH_CSR_BASE + 0xC8) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_39_REG (CSR_QU_STFISCH_CSR_BASE + 0xCC) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_40_REG (CSR_QU_STFISCH_CSR_BASE + 0xD0) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_41_REG (CSR_QU_STFISCH_CSR_BASE + 0xD4) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_42_REG (CSR_QU_STFISCH_CSR_BASE + 0xD8) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_43_REG (CSR_QU_STFISCH_CSR_BASE + 0xDC) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xE0) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xE4) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xE8) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xEC) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xF0) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xF4) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xF8) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xFC) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_52_REG (CSR_QU_STFISCH_CSR_BASE + 0x100) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_53_REG (CSR_QU_STFISCH_CSR_BASE + 0x104) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_54_REG (CSR_QU_STFISCH_CSR_BASE + 0x108) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_55_REG (CSR_QU_STFISCH_CSR_BASE + 0x10C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_56_REG (CSR_QU_STFISCH_CSR_BASE + 0x110) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_57_REG (CSR_QU_STFISCH_CSR_BASE + 0x114) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_58_REG (CSR_QU_STFISCH_CSR_BASE + 0x118) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_59_REG (CSR_QU_STFISCH_CSR_BASE + 0x11C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_60_REG (CSR_QU_STFISCH_CSR_BASE + 0x120) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_61_REG (CSR_QU_STFISCH_CSR_BASE + 0x124) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_62_REG (CSR_QU_STFISCH_CSR_BASE + 0x128) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_63_REG (CSR_QU_STFISCH_CSR_BASE + 0x12C) /* core属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x130) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x134) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x138) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x13C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x140) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x144) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x148) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x14C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x150) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x154) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x158) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x15C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x160) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x164) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x168) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x16C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x170) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x174) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x178) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x17C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x180) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x184) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x188) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x18C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x190) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x194) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x198) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x19C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_28_REG (CSR_QU_STFISCH_CSR_BASE + 0x1A0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_29_REG (CSR_QU_STFISCH_CSR_BASE + 0x1A4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_30_REG (CSR_QU_STFISCH_CSR_BASE + 0x1A8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_31_REG (CSR_QU_STFISCH_CSR_BASE + 0x1AC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_32_REG (CSR_QU_STFISCH_CSR_BASE + 0x1B0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_33_REG (CSR_QU_STFISCH_CSR_BASE + 0x1B4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_34_REG (CSR_QU_STFISCH_CSR_BASE + 0x1B8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_35_REG (CSR_QU_STFISCH_CSR_BASE + 0x1BC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_36_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_37_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_38_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_39_REG (CSR_QU_STFISCH_CSR_BASE + 0x1CC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_40_REG (CSR_QU_STFISCH_CSR_BASE + 0x1D0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_41_REG (CSR_QU_STFISCH_CSR_BASE + 0x1D4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_42_REG (CSR_QU_STFISCH_CSR_BASE + 0x1D8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_43_REG (CSR_QU_STFISCH_CSR_BASE + 0x1DC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_44_REG (CSR_QU_STFISCH_CSR_BASE + 0x1E0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_45_REG (CSR_QU_STFISCH_CSR_BASE + 0x1E4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_46_REG (CSR_QU_STFISCH_CSR_BASE + 0x1E8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_47_REG (CSR_QU_STFISCH_CSR_BASE + 0x1EC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_48_REG (CSR_QU_STFISCH_CSR_BASE + 0x1F0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_49_REG (CSR_QU_STFISCH_CSR_BASE + 0x1F4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_50_REG (CSR_QU_STFISCH_CSR_BASE + 0x1F8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_51_REG (CSR_QU_STFISCH_CSR_BASE + 0x1FC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_52_REG (CSR_QU_STFISCH_CSR_BASE + 0x200) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_53_REG (CSR_QU_STFISCH_CSR_BASE + 0x204) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_54_REG (CSR_QU_STFISCH_CSR_BASE + 0x208) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_55_REG (CSR_QU_STFISCH_CSR_BASE + 0x20C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_56_REG (CSR_QU_STFISCH_CSR_BASE + 0x210) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_57_REG (CSR_QU_STFISCH_CSR_BASE + 0x214) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_58_REG (CSR_QU_STFISCH_CSR_BASE + 0x218) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_59_REG (CSR_QU_STFISCH_CSR_BASE + 0x21C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_60_REG (CSR_QU_STFISCH_CSR_BASE + 0x220) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_61_REG (CSR_QU_STFISCH_CSR_BASE + 0x224) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_62_REG (CSR_QU_STFISCH_CSR_BASE + 0x228) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_63_REG (CSR_QU_STFISCH_CSR_BASE + 0x22C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_64_REG (CSR_QU_STFISCH_CSR_BASE + 0x230) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_65_REG (CSR_QU_STFISCH_CSR_BASE + 0x234) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_66_REG (CSR_QU_STFISCH_CSR_BASE + 0x238) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_67_REG (CSR_QU_STFISCH_CSR_BASE + 0x23C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_68_REG (CSR_QU_STFISCH_CSR_BASE + 0x240) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_69_REG (CSR_QU_STFISCH_CSR_BASE + 0x244) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_70_REG (CSR_QU_STFISCH_CSR_BASE + 0x248) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_71_REG (CSR_QU_STFISCH_CSR_BASE + 0x24C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_72_REG (CSR_QU_STFISCH_CSR_BASE + 0x250) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_73_REG (CSR_QU_STFISCH_CSR_BASE + 0x254) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_74_REG (CSR_QU_STFISCH_CSR_BASE + 0x258) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_75_REG (CSR_QU_STFISCH_CSR_BASE + 0x25C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_76_REG (CSR_QU_STFISCH_CSR_BASE + 0x260) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_77_REG (CSR_QU_STFISCH_CSR_BASE + 0x264) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_78_REG (CSR_QU_STFISCH_CSR_BASE + 0x268) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_79_REG (CSR_QU_STFISCH_CSR_BASE + 0x26C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_80_REG (CSR_QU_STFISCH_CSR_BASE + 0x270) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_81_REG (CSR_QU_STFISCH_CSR_BASE + 0x274) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_82_REG (CSR_QU_STFISCH_CSR_BASE + 0x278) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_83_REG (CSR_QU_STFISCH_CSR_BASE + 0x27C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_84_REG (CSR_QU_STFISCH_CSR_BASE + 0x280) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_85_REG (CSR_QU_STFISCH_CSR_BASE + 0x284) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_86_REG (CSR_QU_STFISCH_CSR_BASE + 0x288) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_87_REG (CSR_QU_STFISCH_CSR_BASE + 0x28C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_88_REG (CSR_QU_STFISCH_CSR_BASE + 0x290) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_89_REG (CSR_QU_STFISCH_CSR_BASE + 0x294) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_90_REG (CSR_QU_STFISCH_CSR_BASE + 0x298) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_91_REG (CSR_QU_STFISCH_CSR_BASE + 0x29C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_92_REG (CSR_QU_STFISCH_CSR_BASE + 0x2A0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_93_REG (CSR_QU_STFISCH_CSR_BASE + 0x2A4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_94_REG (CSR_QU_STFISCH_CSR_BASE + 0x2A8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_95_REG (CSR_QU_STFISCH_CSR_BASE + 0x2AC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_96_REG (CSR_QU_STFISCH_CSR_BASE + 0x2B0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_97_REG (CSR_QU_STFISCH_CSR_BASE + 0x2B4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_98_REG (CSR_QU_STFISCH_CSR_BASE + 0x2B8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_99_REG (CSR_QU_STFISCH_CSR_BASE + 0x2BC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_100_REG (CSR_QU_STFISCH_CSR_BASE + 0x2C0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_101_REG (CSR_QU_STFISCH_CSR_BASE + 0x2C4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_102_REG (CSR_QU_STFISCH_CSR_BASE + 0x2C8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_103_REG (CSR_QU_STFISCH_CSR_BASE + 0x2CC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_104_REG (CSR_QU_STFISCH_CSR_BASE + 0x2D0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_105_REG (CSR_QU_STFISCH_CSR_BASE + 0x2D4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_106_REG (CSR_QU_STFISCH_CSR_BASE + 0x2D8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_107_REG (CSR_QU_STFISCH_CSR_BASE + 0x2DC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_108_REG (CSR_QU_STFISCH_CSR_BASE + 0x2E0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_109_REG (CSR_QU_STFISCH_CSR_BASE + 0x2E4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_110_REG (CSR_QU_STFISCH_CSR_BASE + 0x2E8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_111_REG (CSR_QU_STFISCH_CSR_BASE + 0x2EC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_112_REG (CSR_QU_STFISCH_CSR_BASE + 0x2F0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_113_REG (CSR_QU_STFISCH_CSR_BASE + 0x2F4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_114_REG (CSR_QU_STFISCH_CSR_BASE + 0x2F8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_115_REG (CSR_QU_STFISCH_CSR_BASE + 0x2FC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_116_REG (CSR_QU_STFISCH_CSR_BASE + 0x300) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_117_REG (CSR_QU_STFISCH_CSR_BASE + 0x304) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_118_REG (CSR_QU_STFISCH_CSR_BASE + 0x308) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_119_REG (CSR_QU_STFISCH_CSR_BASE + 0x30C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_120_REG (CSR_QU_STFISCH_CSR_BASE + 0x310) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_121_REG (CSR_QU_STFISCH_CSR_BASE + 0x314) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_122_REG (CSR_QU_STFISCH_CSR_BASE + 0x318) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_123_REG (CSR_QU_STFISCH_CSR_BASE + 0x31C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_124_REG (CSR_QU_STFISCH_CSR_BASE + 0x320) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_125_REG (CSR_QU_STFISCH_CSR_BASE + 0x324) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_126_REG (CSR_QU_STFISCH_CSR_BASE + 0x328) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_127_REG (CSR_QU_STFISCH_CSR_BASE + 0x32C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_128_REG (CSR_QU_STFISCH_CSR_BASE + 0x330) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_129_REG (CSR_QU_STFISCH_CSR_BASE + 0x334) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_130_REG (CSR_QU_STFISCH_CSR_BASE + 0x338) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_131_REG (CSR_QU_STFISCH_CSR_BASE + 0x33C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_132_REG (CSR_QU_STFISCH_CSR_BASE + 0x340) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_133_REG (CSR_QU_STFISCH_CSR_BASE + 0x344) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_134_REG (CSR_QU_STFISCH_CSR_BASE + 0x348) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_135_REG (CSR_QU_STFISCH_CSR_BASE + 0x34C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_136_REG (CSR_QU_STFISCH_CSR_BASE + 0x350) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_137_REG (CSR_QU_STFISCH_CSR_BASE + 0x354) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_138_REG (CSR_QU_STFISCH_CSR_BASE + 0x358) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_139_REG (CSR_QU_STFISCH_CSR_BASE + 0x35C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_140_REG (CSR_QU_STFISCH_CSR_BASE + 0x360) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_141_REG (CSR_QU_STFISCH_CSR_BASE + 0x364) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_142_REG (CSR_QU_STFISCH_CSR_BASE + 0x368) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_143_REG (CSR_QU_STFISCH_CSR_BASE + 0x36C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_144_REG (CSR_QU_STFISCH_CSR_BASE + 0x370) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_145_REG (CSR_QU_STFISCH_CSR_BASE + 0x374) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_146_REG (CSR_QU_STFISCH_CSR_BASE + 0x378) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_147_REG (CSR_QU_STFISCH_CSR_BASE + 0x37C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_148_REG (CSR_QU_STFISCH_CSR_BASE + 0x380) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_149_REG (CSR_QU_STFISCH_CSR_BASE + 0x384) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_150_REG (CSR_QU_STFISCH_CSR_BASE + 0x388) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_151_REG (CSR_QU_STFISCH_CSR_BASE + 0x38C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_152_REG (CSR_QU_STFISCH_CSR_BASE + 0x390) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_153_REG (CSR_QU_STFISCH_CSR_BASE + 0x394) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_154_REG (CSR_QU_STFISCH_CSR_BASE + 0x398) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_155_REG (CSR_QU_STFISCH_CSR_BASE + 0x39C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_156_REG (CSR_QU_STFISCH_CSR_BASE + 0x3A0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_157_REG (CSR_QU_STFISCH_CSR_BASE + 0x3A4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_158_REG (CSR_QU_STFISCH_CSR_BASE + 0x3A8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_159_REG (CSR_QU_STFISCH_CSR_BASE + 0x3AC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_160_REG (CSR_QU_STFISCH_CSR_BASE + 0x3B0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_161_REG (CSR_QU_STFISCH_CSR_BASE + 0x3B4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_162_REG (CSR_QU_STFISCH_CSR_BASE + 0x3B8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_163_REG (CSR_QU_STFISCH_CSR_BASE + 0x3BC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_164_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_165_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_166_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_167_REG (CSR_QU_STFISCH_CSR_BASE + 0x3CC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_168_REG (CSR_QU_STFISCH_CSR_BASE + 0x3D0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_169_REG (CSR_QU_STFISCH_CSR_BASE + 0x3D4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_170_REG (CSR_QU_STFISCH_CSR_BASE + 0x3D8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_171_REG (CSR_QU_STFISCH_CSR_BASE + 0x3DC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_172_REG (CSR_QU_STFISCH_CSR_BASE + 0x3E0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_173_REG (CSR_QU_STFISCH_CSR_BASE + 0x3E4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_174_REG (CSR_QU_STFISCH_CSR_BASE + 0x3E8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_175_REG (CSR_QU_STFISCH_CSR_BASE + 0x3EC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_176_REG (CSR_QU_STFISCH_CSR_BASE + 0x3F0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_177_REG (CSR_QU_STFISCH_CSR_BASE + 0x3F4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_178_REG (CSR_QU_STFISCH_CSR_BASE + 0x3F8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_179_REG (CSR_QU_STFISCH_CSR_BASE + 0x3FC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_180_REG (CSR_QU_STFISCH_CSR_BASE + 0x400) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_181_REG (CSR_QU_STFISCH_CSR_BASE + 0x404) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_182_REG (CSR_QU_STFISCH_CSR_BASE + 0x408) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_183_REG (CSR_QU_STFISCH_CSR_BASE + 0x40C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_184_REG (CSR_QU_STFISCH_CSR_BASE + 0x410) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_185_REG (CSR_QU_STFISCH_CSR_BASE + 0x414) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_186_REG (CSR_QU_STFISCH_CSR_BASE + 0x418) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_187_REG (CSR_QU_STFISCH_CSR_BASE + 0x41C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_188_REG (CSR_QU_STFISCH_CSR_BASE + 0x420) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_189_REG (CSR_QU_STFISCH_CSR_BASE + 0x424) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_190_REG (CSR_QU_STFISCH_CSR_BASE + 0x428) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_191_REG (CSR_QU_STFISCH_CSR_BASE + 0x42C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_192_REG (CSR_QU_STFISCH_CSR_BASE + 0x430) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_193_REG (CSR_QU_STFISCH_CSR_BASE + 0x434) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_194_REG (CSR_QU_STFISCH_CSR_BASE + 0x438) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_195_REG (CSR_QU_STFISCH_CSR_BASE + 0x43C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_196_REG (CSR_QU_STFISCH_CSR_BASE + 0x440) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_197_REG (CSR_QU_STFISCH_CSR_BASE + 0x444) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_198_REG (CSR_QU_STFISCH_CSR_BASE + 0x448) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_199_REG (CSR_QU_STFISCH_CSR_BASE + 0x44C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_200_REG (CSR_QU_STFISCH_CSR_BASE + 0x450) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_201_REG (CSR_QU_STFISCH_CSR_BASE + 0x454) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_202_REG (CSR_QU_STFISCH_CSR_BASE + 0x458) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_203_REG (CSR_QU_STFISCH_CSR_BASE + 0x45C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_204_REG (CSR_QU_STFISCH_CSR_BASE + 0x460) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_205_REG (CSR_QU_STFISCH_CSR_BASE + 0x464) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_206_REG (CSR_QU_STFISCH_CSR_BASE + 0x468) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_207_REG (CSR_QU_STFISCH_CSR_BASE + 0x46C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_208_REG (CSR_QU_STFISCH_CSR_BASE + 0x470) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_209_REG (CSR_QU_STFISCH_CSR_BASE + 0x474) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_210_REG (CSR_QU_STFISCH_CSR_BASE + 0x478) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_211_REG (CSR_QU_STFISCH_CSR_BASE + 0x47C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_212_REG (CSR_QU_STFISCH_CSR_BASE + 0x480) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_213_REG (CSR_QU_STFISCH_CSR_BASE + 0x484) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_214_REG (CSR_QU_STFISCH_CSR_BASE + 0x488) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_215_REG (CSR_QU_STFISCH_CSR_BASE + 0x48C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_216_REG (CSR_QU_STFISCH_CSR_BASE + 0x490) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_217_REG (CSR_QU_STFISCH_CSR_BASE + 0x494) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_218_REG (CSR_QU_STFISCH_CSR_BASE + 0x498) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_219_REG (CSR_QU_STFISCH_CSR_BASE + 0x49C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_220_REG (CSR_QU_STFISCH_CSR_BASE + 0x4A0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_221_REG (CSR_QU_STFISCH_CSR_BASE + 0x4A4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_222_REG (CSR_QU_STFISCH_CSR_BASE + 0x4A8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_223_REG (CSR_QU_STFISCH_CSR_BASE + 0x4AC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_224_REG (CSR_QU_STFISCH_CSR_BASE + 0x4B0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_225_REG (CSR_QU_STFISCH_CSR_BASE + 0x4B4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_226_REG (CSR_QU_STFISCH_CSR_BASE + 0x4B8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_227_REG (CSR_QU_STFISCH_CSR_BASE + 0x4BC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_228_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_229_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_230_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_231_REG (CSR_QU_STFISCH_CSR_BASE + 0x4CC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_232_REG (CSR_QU_STFISCH_CSR_BASE + 0x4D0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_233_REG (CSR_QU_STFISCH_CSR_BASE + 0x4D4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_234_REG (CSR_QU_STFISCH_CSR_BASE + 0x4D8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_235_REG (CSR_QU_STFISCH_CSR_BASE + 0x4DC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_236_REG (CSR_QU_STFISCH_CSR_BASE + 0x4E0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_237_REG (CSR_QU_STFISCH_CSR_BASE + 0x4E4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_238_REG (CSR_QU_STFISCH_CSR_BASE + 0x4E8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_239_REG (CSR_QU_STFISCH_CSR_BASE + 0x4EC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_240_REG (CSR_QU_STFISCH_CSR_BASE + 0x4F0) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_241_REG (CSR_QU_STFISCH_CSR_BASE + 0x4F4) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_242_REG (CSR_QU_STFISCH_CSR_BASE + 0x4F8) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_243_REG (CSR_QU_STFISCH_CSR_BASE + 0x4FC) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_244_REG (CSR_QU_STFISCH_CSR_BASE + 0x500) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_245_REG (CSR_QU_STFISCH_CSR_BASE + 0x504) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_246_REG (CSR_QU_STFISCH_CSR_BASE + 0x508) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_247_REG (CSR_QU_STFISCH_CSR_BASE + 0x50C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_248_REG (CSR_QU_STFISCH_CSR_BASE + 0x510) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_249_REG (CSR_QU_STFISCH_CSR_BASE + 0x514) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_250_REG (CSR_QU_STFISCH_CSR_BASE + 0x518) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_251_REG (CSR_QU_STFISCH_CSR_BASE + 0x51C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_252_REG (CSR_QU_STFISCH_CSR_BASE + 0x520) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_253_REG (CSR_QU_STFISCH_CSR_BASE + 0x524) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_254_REG (CSR_QU_STFISCH_CSR_BASE + 0x528) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_255_REG (CSR_QU_STFISCH_CSR_BASE + 0x52C) /* channel属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x530) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x534) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x538) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x53C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x540) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x544) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x548) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x54C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x550) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x554) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x558) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x55C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x560) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x564) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x568) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x56C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x570) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x574) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x578) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x57C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x580) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x584) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x588) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x58C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x590) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x594) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x598) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x59C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_28_REG (CSR_QU_STFISCH_CSR_BASE + 0x5A0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_29_REG (CSR_QU_STFISCH_CSR_BASE + 0x5A4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_30_REG (CSR_QU_STFISCH_CSR_BASE + 0x5A8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_31_REG (CSR_QU_STFISCH_CSR_BASE + 0x5AC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_32_REG (CSR_QU_STFISCH_CSR_BASE + 0x5B0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_33_REG (CSR_QU_STFISCH_CSR_BASE + 0x5B4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_34_REG (CSR_QU_STFISCH_CSR_BASE + 0x5B8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_35_REG (CSR_QU_STFISCH_CSR_BASE + 0x5BC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_36_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_37_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_38_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_39_REG (CSR_QU_STFISCH_CSR_BASE + 0x5CC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_40_REG (CSR_QU_STFISCH_CSR_BASE + 0x5D0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_41_REG (CSR_QU_STFISCH_CSR_BASE + 0x5D4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_42_REG (CSR_QU_STFISCH_CSR_BASE + 0x5D8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_43_REG (CSR_QU_STFISCH_CSR_BASE + 0x5DC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_44_REG (CSR_QU_STFISCH_CSR_BASE + 0x5E0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_45_REG (CSR_QU_STFISCH_CSR_BASE + 0x5E4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_46_REG (CSR_QU_STFISCH_CSR_BASE + 0x5E8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_47_REG (CSR_QU_STFISCH_CSR_BASE + 0x5EC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_48_REG (CSR_QU_STFISCH_CSR_BASE + 0x5F0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_49_REG (CSR_QU_STFISCH_CSR_BASE + 0x5F4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_50_REG (CSR_QU_STFISCH_CSR_BASE + 0x5F8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_51_REG (CSR_QU_STFISCH_CSR_BASE + 0x5FC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_52_REG (CSR_QU_STFISCH_CSR_BASE + 0x600) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_53_REG (CSR_QU_STFISCH_CSR_BASE + 0x604) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_54_REG (CSR_QU_STFISCH_CSR_BASE + 0x608) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_55_REG (CSR_QU_STFISCH_CSR_BASE + 0x60C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_56_REG (CSR_QU_STFISCH_CSR_BASE + 0x610) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_57_REG (CSR_QU_STFISCH_CSR_BASE + 0x614) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_58_REG (CSR_QU_STFISCH_CSR_BASE + 0x618) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_59_REG (CSR_QU_STFISCH_CSR_BASE + 0x61C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_60_REG (CSR_QU_STFISCH_CSR_BASE + 0x620) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_61_REG (CSR_QU_STFISCH_CSR_BASE + 0x624) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_62_REG (CSR_QU_STFISCH_CSR_BASE + 0x628) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_63_REG (CSR_QU_STFISCH_CSR_BASE + 0x62C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_64_REG (CSR_QU_STFISCH_CSR_BASE + 0x630) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_65_REG (CSR_QU_STFISCH_CSR_BASE + 0x634) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_66_REG (CSR_QU_STFISCH_CSR_BASE + 0x638) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_67_REG (CSR_QU_STFISCH_CSR_BASE + 0x63C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_68_REG (CSR_QU_STFISCH_CSR_BASE + 0x640) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_69_REG (CSR_QU_STFISCH_CSR_BASE + 0x644) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_70_REG (CSR_QU_STFISCH_CSR_BASE + 0x648) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_71_REG (CSR_QU_STFISCH_CSR_BASE + 0x64C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_72_REG (CSR_QU_STFISCH_CSR_BASE + 0x650) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_73_REG (CSR_QU_STFISCH_CSR_BASE + 0x654) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_74_REG (CSR_QU_STFISCH_CSR_BASE + 0x658) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_75_REG (CSR_QU_STFISCH_CSR_BASE + 0x65C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_76_REG (CSR_QU_STFISCH_CSR_BASE + 0x660) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_77_REG (CSR_QU_STFISCH_CSR_BASE + 0x664) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_78_REG (CSR_QU_STFISCH_CSR_BASE + 0x668) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_79_REG (CSR_QU_STFISCH_CSR_BASE + 0x66C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_80_REG (CSR_QU_STFISCH_CSR_BASE + 0x670) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_81_REG (CSR_QU_STFISCH_CSR_BASE + 0x674) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_82_REG (CSR_QU_STFISCH_CSR_BASE + 0x678) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_83_REG (CSR_QU_STFISCH_CSR_BASE + 0x67C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_84_REG (CSR_QU_STFISCH_CSR_BASE + 0x680) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_85_REG (CSR_QU_STFISCH_CSR_BASE + 0x684) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_86_REG (CSR_QU_STFISCH_CSR_BASE + 0x688) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_87_REG (CSR_QU_STFISCH_CSR_BASE + 0x68C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_88_REG (CSR_QU_STFISCH_CSR_BASE + 0x690) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_89_REG (CSR_QU_STFISCH_CSR_BASE + 0x694) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_90_REG (CSR_QU_STFISCH_CSR_BASE + 0x698) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_91_REG (CSR_QU_STFISCH_CSR_BASE + 0x69C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_92_REG (CSR_QU_STFISCH_CSR_BASE + 0x6A0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_93_REG (CSR_QU_STFISCH_CSR_BASE + 0x6A4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_94_REG (CSR_QU_STFISCH_CSR_BASE + 0x6A8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_95_REG (CSR_QU_STFISCH_CSR_BASE + 0x6AC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_96_REG (CSR_QU_STFISCH_CSR_BASE + 0x6B0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_97_REG (CSR_QU_STFISCH_CSR_BASE + 0x6B4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_98_REG (CSR_QU_STFISCH_CSR_BASE + 0x6B8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_99_REG (CSR_QU_STFISCH_CSR_BASE + 0x6BC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_100_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_101_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_102_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_103_REG (CSR_QU_STFISCH_CSR_BASE + 0x6CC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_104_REG (CSR_QU_STFISCH_CSR_BASE + 0x6D0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_105_REG (CSR_QU_STFISCH_CSR_BASE + 0x6D4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_106_REG (CSR_QU_STFISCH_CSR_BASE + 0x6D8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_107_REG (CSR_QU_STFISCH_CSR_BASE + 0x6DC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_108_REG (CSR_QU_STFISCH_CSR_BASE + 0x6E0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_109_REG (CSR_QU_STFISCH_CSR_BASE + 0x6E4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_110_REG (CSR_QU_STFISCH_CSR_BASE + 0x6E8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_111_REG (CSR_QU_STFISCH_CSR_BASE + 0x6EC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_112_REG (CSR_QU_STFISCH_CSR_BASE + 0x6F0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_113_REG (CSR_QU_STFISCH_CSR_BASE + 0x6F4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_114_REG (CSR_QU_STFISCH_CSR_BASE + 0x6F8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_115_REG (CSR_QU_STFISCH_CSR_BASE + 0x6FC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_116_REG (CSR_QU_STFISCH_CSR_BASE + 0x700) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_117_REG (CSR_QU_STFISCH_CSR_BASE + 0x704) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_118_REG (CSR_QU_STFISCH_CSR_BASE + 0x708) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_119_REG (CSR_QU_STFISCH_CSR_BASE + 0x70C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_120_REG (CSR_QU_STFISCH_CSR_BASE + 0x710) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_121_REG (CSR_QU_STFISCH_CSR_BASE + 0x714) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_122_REG (CSR_QU_STFISCH_CSR_BASE + 0x718) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_123_REG (CSR_QU_STFISCH_CSR_BASE + 0x71C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_124_REG (CSR_QU_STFISCH_CSR_BASE + 0x720) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_125_REG (CSR_QU_STFISCH_CSR_BASE + 0x724) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_126_REG (CSR_QU_STFISCH_CSR_BASE + 0x728) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_127_REG (CSR_QU_STFISCH_CSR_BASE + 0x72C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_128_REG (CSR_QU_STFISCH_CSR_BASE + 0x730) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_129_REG (CSR_QU_STFISCH_CSR_BASE + 0x734) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_130_REG (CSR_QU_STFISCH_CSR_BASE + 0x738) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_131_REG (CSR_QU_STFISCH_CSR_BASE + 0x73C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_132_REG (CSR_QU_STFISCH_CSR_BASE + 0x740) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_133_REG (CSR_QU_STFISCH_CSR_BASE + 0x744) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_134_REG (CSR_QU_STFISCH_CSR_BASE + 0x748) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_135_REG (CSR_QU_STFISCH_CSR_BASE + 0x74C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_136_REG (CSR_QU_STFISCH_CSR_BASE + 0x750) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_137_REG (CSR_QU_STFISCH_CSR_BASE + 0x754) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_138_REG (CSR_QU_STFISCH_CSR_BASE + 0x758) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_139_REG (CSR_QU_STFISCH_CSR_BASE + 0x75C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_140_REG (CSR_QU_STFISCH_CSR_BASE + 0x760) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_141_REG (CSR_QU_STFISCH_CSR_BASE + 0x764) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_142_REG (CSR_QU_STFISCH_CSR_BASE + 0x768) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_143_REG (CSR_QU_STFISCH_CSR_BASE + 0x76C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_144_REG (CSR_QU_STFISCH_CSR_BASE + 0x770) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_145_REG (CSR_QU_STFISCH_CSR_BASE + 0x774) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_146_REG (CSR_QU_STFISCH_CSR_BASE + 0x778) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_147_REG (CSR_QU_STFISCH_CSR_BASE + 0x77C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_148_REG (CSR_QU_STFISCH_CSR_BASE + 0x780) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_149_REG (CSR_QU_STFISCH_CSR_BASE + 0x784) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_150_REG (CSR_QU_STFISCH_CSR_BASE + 0x788) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_151_REG (CSR_QU_STFISCH_CSR_BASE + 0x78C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_152_REG (CSR_QU_STFISCH_CSR_BASE + 0x790) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_153_REG (CSR_QU_STFISCH_CSR_BASE + 0x794) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_154_REG (CSR_QU_STFISCH_CSR_BASE + 0x798) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_155_REG (CSR_QU_STFISCH_CSR_BASE + 0x79C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_156_REG (CSR_QU_STFISCH_CSR_BASE + 0x7A0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_157_REG (CSR_QU_STFISCH_CSR_BASE + 0x7A4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_158_REG (CSR_QU_STFISCH_CSR_BASE + 0x7A8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_159_REG (CSR_QU_STFISCH_CSR_BASE + 0x7AC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_160_REG (CSR_QU_STFISCH_CSR_BASE + 0x7B0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_161_REG (CSR_QU_STFISCH_CSR_BASE + 0x7B4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_162_REG (CSR_QU_STFISCH_CSR_BASE + 0x7B8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_163_REG (CSR_QU_STFISCH_CSR_BASE + 0x7BC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_164_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_165_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_166_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_167_REG (CSR_QU_STFISCH_CSR_BASE + 0x7CC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_168_REG (CSR_QU_STFISCH_CSR_BASE + 0x7D0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_169_REG (CSR_QU_STFISCH_CSR_BASE + 0x7D4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_170_REG (CSR_QU_STFISCH_CSR_BASE + 0x7D8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_171_REG (CSR_QU_STFISCH_CSR_BASE + 0x7DC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_172_REG (CSR_QU_STFISCH_CSR_BASE + 0x7E0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_173_REG (CSR_QU_STFISCH_CSR_BASE + 0x7E4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_174_REG (CSR_QU_STFISCH_CSR_BASE + 0x7E8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_175_REG (CSR_QU_STFISCH_CSR_BASE + 0x7EC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_176_REG (CSR_QU_STFISCH_CSR_BASE + 0x7F0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_177_REG (CSR_QU_STFISCH_CSR_BASE + 0x7F4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_178_REG (CSR_QU_STFISCH_CSR_BASE + 0x7F8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_179_REG (CSR_QU_STFISCH_CSR_BASE + 0x7FC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_180_REG (CSR_QU_STFISCH_CSR_BASE + 0x800) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_181_REG (CSR_QU_STFISCH_CSR_BASE + 0x804) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_182_REG (CSR_QU_STFISCH_CSR_BASE + 0x808) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_183_REG (CSR_QU_STFISCH_CSR_BASE + 0x80C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_184_REG (CSR_QU_STFISCH_CSR_BASE + 0x810) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_185_REG (CSR_QU_STFISCH_CSR_BASE + 0x814) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_186_REG (CSR_QU_STFISCH_CSR_BASE + 0x818) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_187_REG (CSR_QU_STFISCH_CSR_BASE + 0x81C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_188_REG (CSR_QU_STFISCH_CSR_BASE + 0x820) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_189_REG (CSR_QU_STFISCH_CSR_BASE + 0x824) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_190_REG (CSR_QU_STFISCH_CSR_BASE + 0x828) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_191_REG (CSR_QU_STFISCH_CSR_BASE + 0x82C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_192_REG (CSR_QU_STFISCH_CSR_BASE + 0x830) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_193_REG (CSR_QU_STFISCH_CSR_BASE + 0x834) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_194_REG (CSR_QU_STFISCH_CSR_BASE + 0x838) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_195_REG (CSR_QU_STFISCH_CSR_BASE + 0x83C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_196_REG (CSR_QU_STFISCH_CSR_BASE + 0x840) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_197_REG (CSR_QU_STFISCH_CSR_BASE + 0x844) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_198_REG (CSR_QU_STFISCH_CSR_BASE + 0x848) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_199_REG (CSR_QU_STFISCH_CSR_BASE + 0x84C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_200_REG (CSR_QU_STFISCH_CSR_BASE + 0x850) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_201_REG (CSR_QU_STFISCH_CSR_BASE + 0x854) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_202_REG (CSR_QU_STFISCH_CSR_BASE + 0x858) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_203_REG (CSR_QU_STFISCH_CSR_BASE + 0x85C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_204_REG (CSR_QU_STFISCH_CSR_BASE + 0x860) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_205_REG (CSR_QU_STFISCH_CSR_BASE + 0x864) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_206_REG (CSR_QU_STFISCH_CSR_BASE + 0x868) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_207_REG (CSR_QU_STFISCH_CSR_BASE + 0x86C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_208_REG (CSR_QU_STFISCH_CSR_BASE + 0x870) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_209_REG (CSR_QU_STFISCH_CSR_BASE + 0x874) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_210_REG (CSR_QU_STFISCH_CSR_BASE + 0x878) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_211_REG (CSR_QU_STFISCH_CSR_BASE + 0x87C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_212_REG (CSR_QU_STFISCH_CSR_BASE + 0x880) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_213_REG (CSR_QU_STFISCH_CSR_BASE + 0x884) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_214_REG (CSR_QU_STFISCH_CSR_BASE + 0x888) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_215_REG (CSR_QU_STFISCH_CSR_BASE + 0x88C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_216_REG (CSR_QU_STFISCH_CSR_BASE + 0x890) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_217_REG (CSR_QU_STFISCH_CSR_BASE + 0x894) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_218_REG (CSR_QU_STFISCH_CSR_BASE + 0x898) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_219_REG (CSR_QU_STFISCH_CSR_BASE + 0x89C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_220_REG (CSR_QU_STFISCH_CSR_BASE + 0x8A0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_221_REG (CSR_QU_STFISCH_CSR_BASE + 0x8A4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_222_REG (CSR_QU_STFISCH_CSR_BASE + 0x8A8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_223_REG (CSR_QU_STFISCH_CSR_BASE + 0x8AC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_224_REG (CSR_QU_STFISCH_CSR_BASE + 0x8B0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_225_REG (CSR_QU_STFISCH_CSR_BASE + 0x8B4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_226_REG (CSR_QU_STFISCH_CSR_BASE + 0x8B8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_227_REG (CSR_QU_STFISCH_CSR_BASE + 0x8BC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_228_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_229_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_230_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_231_REG (CSR_QU_STFISCH_CSR_BASE + 0x8CC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_232_REG (CSR_QU_STFISCH_CSR_BASE + 0x8D0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_233_REG (CSR_QU_STFISCH_CSR_BASE + 0x8D4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_234_REG (CSR_QU_STFISCH_CSR_BASE + 0x8D8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_235_REG (CSR_QU_STFISCH_CSR_BASE + 0x8DC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_236_REG (CSR_QU_STFISCH_CSR_BASE + 0x8E0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_237_REG (CSR_QU_STFISCH_CSR_BASE + 0x8E4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_238_REG (CSR_QU_STFISCH_CSR_BASE + 0x8E8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_239_REG (CSR_QU_STFISCH_CSR_BASE + 0x8EC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_240_REG (CSR_QU_STFISCH_CSR_BASE + 0x8F0) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_241_REG (CSR_QU_STFISCH_CSR_BASE + 0x8F4) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_242_REG (CSR_QU_STFISCH_CSR_BASE + 0x8F8) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_243_REG (CSR_QU_STFISCH_CSR_BASE + 0x8FC) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_244_REG (CSR_QU_STFISCH_CSR_BASE + 0x900) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_245_REG (CSR_QU_STFISCH_CSR_BASE + 0x904) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_246_REG (CSR_QU_STFISCH_CSR_BASE + 0x908) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_247_REG (CSR_QU_STFISCH_CSR_BASE + 0x90C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_248_REG (CSR_QU_STFISCH_CSR_BASE + 0x910) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_249_REG (CSR_QU_STFISCH_CSR_BASE + 0x914) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_250_REG (CSR_QU_STFISCH_CSR_BASE + 0x918) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_251_REG (CSR_QU_STFISCH_CSR_BASE + 0x91C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_252_REG (CSR_QU_STFISCH_CSR_BASE + 0x920) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_253_REG (CSR_QU_STFISCH_CSR_BASE + 0x924) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_254_REG (CSR_QU_STFISCH_CSR_BASE + 0x928) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_255_REG (CSR_QU_STFISCH_CSR_BASE + 0x92C) /* IQ属性配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x950) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x954) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x958) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x95C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x960) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x964) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x968) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x96C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x970) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x974) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x978) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x97C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x980) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x984) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x988) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x98C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x990) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x994) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x998) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x99C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x9A0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x9A4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x9A8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x9AC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x9B0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x9B4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x9B8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x9BC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_28_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_29_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_30_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_31_REG (CSR_QU_STFISCH_CSR_BASE + 0x9CC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_32_REG (CSR_QU_STFISCH_CSR_BASE + 0x9D0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_33_REG (CSR_QU_STFISCH_CSR_BASE + 0x9D4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_34_REG (CSR_QU_STFISCH_CSR_BASE + 0x9D8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_35_REG (CSR_QU_STFISCH_CSR_BASE + 0x9DC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_36_REG (CSR_QU_STFISCH_CSR_BASE + 0x9E0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_37_REG (CSR_QU_STFISCH_CSR_BASE + 0x9E4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_38_REG (CSR_QU_STFISCH_CSR_BASE + 0x9E8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_39_REG (CSR_QU_STFISCH_CSR_BASE + 0x9EC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_40_REG (CSR_QU_STFISCH_CSR_BASE + 0x9F0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_41_REG (CSR_QU_STFISCH_CSR_BASE + 0x9F4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_42_REG (CSR_QU_STFISCH_CSR_BASE + 0x9F8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_43_REG (CSR_QU_STFISCH_CSR_BASE + 0x9FC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xA00) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xA04) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xA08) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xA0C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xA10) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xA14) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xA18) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xA1C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_52_REG (CSR_QU_STFISCH_CSR_BASE + 0xA20) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_53_REG (CSR_QU_STFISCH_CSR_BASE + 0xA24) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_54_REG (CSR_QU_STFISCH_CSR_BASE + 0xA28) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_55_REG (CSR_QU_STFISCH_CSR_BASE + 0xA2C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_56_REG (CSR_QU_STFISCH_CSR_BASE + 0xA30) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_57_REG (CSR_QU_STFISCH_CSR_BASE + 0xA34) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_58_REG (CSR_QU_STFISCH_CSR_BASE + 0xA38) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_59_REG (CSR_QU_STFISCH_CSR_BASE + 0xA3C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_60_REG (CSR_QU_STFISCH_CSR_BASE + 0xA40) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_61_REG (CSR_QU_STFISCH_CSR_BASE + 0xA44) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_62_REG (CSR_QU_STFISCH_CSR_BASE + 0xA48) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_63_REG (CSR_QU_STFISCH_CSR_BASE + 0xA4C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xA50) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xA54) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xA58) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xA5C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_4_REG (CSR_QU_STFISCH_CSR_BASE + 0xA60) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_5_REG (CSR_QU_STFISCH_CSR_BASE + 0xA64) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_6_REG (CSR_QU_STFISCH_CSR_BASE + 0xA68) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_7_REG (CSR_QU_STFISCH_CSR_BASE + 0xA6C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_8_REG (CSR_QU_STFISCH_CSR_BASE + 0xA70) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_9_REG (CSR_QU_STFISCH_CSR_BASE + 0xA74) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_10_REG (CSR_QU_STFISCH_CSR_BASE + 0xA78) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_11_REG (CSR_QU_STFISCH_CSR_BASE + 0xA7C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_12_REG (CSR_QU_STFISCH_CSR_BASE + 0xA80) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_13_REG (CSR_QU_STFISCH_CSR_BASE + 0xA84) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_14_REG (CSR_QU_STFISCH_CSR_BASE + 0xA88) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_15_REG (CSR_QU_STFISCH_CSR_BASE + 0xA8C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_16_REG (CSR_QU_STFISCH_CSR_BASE + 0xA90) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_17_REG (CSR_QU_STFISCH_CSR_BASE + 0xA94) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_18_REG (CSR_QU_STFISCH_CSR_BASE + 0xA98) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_19_REG (CSR_QU_STFISCH_CSR_BASE + 0xA9C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_20_REG (CSR_QU_STFISCH_CSR_BASE + 0xAA0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_21_REG (CSR_QU_STFISCH_CSR_BASE + 0xAA4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_22_REG (CSR_QU_STFISCH_CSR_BASE + 0xAA8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_23_REG (CSR_QU_STFISCH_CSR_BASE + 0xAAC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_24_REG (CSR_QU_STFISCH_CSR_BASE + 0xAB0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_25_REG (CSR_QU_STFISCH_CSR_BASE + 0xAB4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_26_REG (CSR_QU_STFISCH_CSR_BASE + 0xAB8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_27_REG (CSR_QU_STFISCH_CSR_BASE + 0xABC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_28_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_29_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_30_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_31_REG (CSR_QU_STFISCH_CSR_BASE + 0xACC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_32_REG (CSR_QU_STFISCH_CSR_BASE + 0xAD0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_33_REG (CSR_QU_STFISCH_CSR_BASE + 0xAD4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_34_REG (CSR_QU_STFISCH_CSR_BASE + 0xAD8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_35_REG (CSR_QU_STFISCH_CSR_BASE + 0xADC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_36_REG (CSR_QU_STFISCH_CSR_BASE + 0xAE0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_37_REG (CSR_QU_STFISCH_CSR_BASE + 0xAE4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_38_REG (CSR_QU_STFISCH_CSR_BASE + 0xAE8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_39_REG (CSR_QU_STFISCH_CSR_BASE + 0xAEC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_40_REG (CSR_QU_STFISCH_CSR_BASE + 0xAF0) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_41_REG (CSR_QU_STFISCH_CSR_BASE + 0xAF4) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_42_REG (CSR_QU_STFISCH_CSR_BASE + 0xAF8) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_43_REG (CSR_QU_STFISCH_CSR_BASE + 0xAFC) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xB00) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xB04) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xB08) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xB0C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xB10) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xB14) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xB18) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xB1C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_52_REG (CSR_QU_STFISCH_CSR_BASE + 0xB20) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_53_REG (CSR_QU_STFISCH_CSR_BASE + 0xB24) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_54_REG (CSR_QU_STFISCH_CSR_BASE + 0xB28) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_55_REG (CSR_QU_STFISCH_CSR_BASE + 0xB2C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_56_REG (CSR_QU_STFISCH_CSR_BASE + 0xB30) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_57_REG (CSR_QU_STFISCH_CSR_BASE + 0xB34) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_58_REG (CSR_QU_STFISCH_CSR_BASE + 0xB38) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_59_REG (CSR_QU_STFISCH_CSR_BASE + 0xB3C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_60_REG (CSR_QU_STFISCH_CSR_BASE + 0xB40) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_61_REG (CSR_QU_STFISCH_CSR_BASE + 0xB44) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_62_REG (CSR_QU_STFISCH_CSR_BASE + 0xB48) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_63_REG (CSR_QU_STFISCH_CSR_BASE + 0xB4C) /* 线程状态寄存器 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xB50) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xB54) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xB58) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xB5C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_4_REG (CSR_QU_STFISCH_CSR_BASE + 0xB60) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_5_REG (CSR_QU_STFISCH_CSR_BASE + 0xB64) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_6_REG (CSR_QU_STFISCH_CSR_BASE + 0xB68) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_7_REG (CSR_QU_STFISCH_CSR_BASE + 0xB6C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_8_REG (CSR_QU_STFISCH_CSR_BASE + 0xB70) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_9_REG (CSR_QU_STFISCH_CSR_BASE + 0xB74) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_10_REG (CSR_QU_STFISCH_CSR_BASE + 0xB78) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_11_REG (CSR_QU_STFISCH_CSR_BASE + 0xB7C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_12_REG (CSR_QU_STFISCH_CSR_BASE + 0xB80) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_13_REG (CSR_QU_STFISCH_CSR_BASE + 0xB84) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_14_REG (CSR_QU_STFISCH_CSR_BASE + 0xB88) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_15_REG (CSR_QU_STFISCH_CSR_BASE + 0xB8C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_16_REG (CSR_QU_STFISCH_CSR_BASE + 0xB90) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_17_REG (CSR_QU_STFISCH_CSR_BASE + 0xB94) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_18_REG (CSR_QU_STFISCH_CSR_BASE + 0xB98) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_19_REG (CSR_QU_STFISCH_CSR_BASE + 0xB9C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_20_REG (CSR_QU_STFISCH_CSR_BASE + 0xBA0) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_21_REG (CSR_QU_STFISCH_CSR_BASE + 0xBA4) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_22_REG (CSR_QU_STFISCH_CSR_BASE + 0xBA8) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_23_REG (CSR_QU_STFISCH_CSR_BASE + 0xBAC) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_24_REG (CSR_QU_STFISCH_CSR_BASE + 0xBB0) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_25_REG (CSR_QU_STFISCH_CSR_BASE + 0xBB4) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_26_REG (CSR_QU_STFISCH_CSR_BASE + 0xBB8) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_27_REG (CSR_QU_STFISCH_CSR_BASE + 0xBBC) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_28_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC0) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_29_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC4) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_30_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC8) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_31_REG (CSR_QU_STFISCH_CSR_BASE + 0xBCC) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_32_REG (CSR_QU_STFISCH_CSR_BASE + 0xBD0) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_33_REG (CSR_QU_STFISCH_CSR_BASE + 0xBD4) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_34_REG (CSR_QU_STFISCH_CSR_BASE + 0xBD8) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_35_REG (CSR_QU_STFISCH_CSR_BASE + 0xBDC) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_36_REG (CSR_QU_STFISCH_CSR_BASE + 0xBE0) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_37_REG (CSR_QU_STFISCH_CSR_BASE + 0xBE4) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_38_REG (CSR_QU_STFISCH_CSR_BASE + 0xBE8) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_39_REG (CSR_QU_STFISCH_CSR_BASE + 0xBEC) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_40_REG (CSR_QU_STFISCH_CSR_BASE + 0xBF0) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_41_REG (CSR_QU_STFISCH_CSR_BASE + 0xBF4) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_42_REG (CSR_QU_STFISCH_CSR_BASE + 0xBF8) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_43_REG (CSR_QU_STFISCH_CSR_BASE + 0xBFC) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xC00) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xC04) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xC08) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xC0C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xC10) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xC14) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xC18) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xC1C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_52_REG (CSR_QU_STFISCH_CSR_BASE + 0xC20) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_53_REG (CSR_QU_STFISCH_CSR_BASE + 0xC24) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_54_REG (CSR_QU_STFISCH_CSR_BASE + 0xC28) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_55_REG (CSR_QU_STFISCH_CSR_BASE + 0xC2C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_56_REG (CSR_QU_STFISCH_CSR_BASE + 0xC30) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_57_REG (CSR_QU_STFISCH_CSR_BASE + 0xC34) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_58_REG (CSR_QU_STFISCH_CSR_BASE + 0xC38) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_59_REG (CSR_QU_STFISCH_CSR_BASE + 0xC3C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_60_REG (CSR_QU_STFISCH_CSR_BASE + 0xC40) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_61_REG (CSR_QU_STFISCH_CSR_BASE + 0xC44) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_62_REG (CSR_QU_STFISCH_CSR_BASE + 0xC48) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_63_REG (CSR_QU_STFISCH_CSR_BASE + 0xC4C) /* core线程watch_dog状态 */ +#define CSR_QU_STFISCH_CSR_ISCH_RLS_C_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC54) /* 释放线程状态错误计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TIME_OUT_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC58) /* 超时错误计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TH_RLS_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC5C) /* 释放线程总数计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TH_ALC_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC60) /* 分配线程总数计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xC64) /* 分配线程总数计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xC68) /* 分配线程总数计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xC6C) /* 分配线程总数计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xC70) /* 分配线程总数计数器。 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_EN_REG (CSR_QU_STFISCH_CSR_BASE + 0xC74) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xC78) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xC7C) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xC80) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xC84) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0xC88) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0xC8C) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0xC90) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0xC94) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0xC98) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0xC9C) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0xCA0) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0xCA4) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0xCA8) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0xCAC) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0xCB0) /* ScoreBoard 配置 */ +#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0xCB4) /* ScoreBoard 配置 */ + +#endif // STFISCH_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlfq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlfq_c_union_define.h new file mode 100644 index 000000000..c93dd62a1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlfq_c_union_define.h @@ -0,0 +1,6358 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stlfq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:11:44 Create file +// ****************************************************************************** + +#ifndef STLFQ_C_UNION_DEFINE_H +#define STLFQ_C_UNION_DEFINE_H + +/* Define the union csr_fq_mode_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_oeid : 9; /* [8:0] */ + u32 cfg_mode_init_def_fq_tx : 2; /* [10:9] */ + u32 enable_stf : 1; /* [11] */ + u32 cfg_ngsf_mod : 1; /* [12] */ + u32 enable_pro : 1; /* [13] */ + u32 enable_asc : 1; /* [14] */ + u32 cfg_psh_msg_en : 1; /* [15] */ + u32 cfg_base_init_def_fq : 12; /* [27:16] */ + u32 cfg_mode_init_def_fq : 2; /* [29:28] */ + u32 cfg_mode_pn : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mode_reg_u; + +/* Define the union csr_fq_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_start : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_initctab_start_u; + +/* Define the union csr_fq_initctab_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_init_ctab_st_done : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_initctab_st_u; + +/* Define the union csr_fq_init_logic_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_init_logic_st_done : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_init_logic_st_u; + +/* Define the union csr_fq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_3 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_vector_u; + +/* Define the union csr_fq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 16; /* [15:0] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_u; + +/* Define the union csr_fq_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 16; /* [15:0] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_mask_u; + +/* Define the union csr_fq_int_mem_err_2b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_2bit_error : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 mem_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_mem_err_2b_u; + +/* Define the union csr_fq_int_oeid_aged_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oeid_age_err_error_bit : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 oeid_age_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_oeid_aged_err_u; + +/* Define the union csr_fq_int_scan_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 scan_err_error_bit : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 scan_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_scan_err_u; + +/* Define the union csr_fq_int_fcmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcmd_err_error_bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 fcmd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fcmd_err_u; + +/* Define the union csr_fq_int_dsp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsp_err_error_bit : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 dsp_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_dsp_err_u; + +/* Define the union csr_fq_int_pfh_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfh_err_error_bit : 1; /* [0] */ + u32 int_insrt5 : 1; /* [1] */ + u32 pfh_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_pfh_err_u; + +/* Define the union csr_fq_int_dbe_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbe_err_error_bit : 1; /* [0] */ + u32 int_insrt6 : 1; /* [1] */ + u32 dbe_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_dbe_err_u; + +/* Define the union csr_fq_int_qrsc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qrsc_err_error_bit : 1; /* [0] */ + u32 int_insrt7 : 1; /* [1] */ + u32 qrsc_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_qrsc_err_u; + +/* Define the union csr_fq_int_buf_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_uf_error_bit : 1; /* [0] */ + u32 int_insrt8 : 1; /* [1] */ + u32 buf_uf_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_buf_uf_err_u; + +/* Define the union csr_fq_int_fifo0_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_err_error_bit : 1; /* [0] */ + u32 int_insrt9 : 1; /* [1] */ + u32 fifo_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fifo0_err_u; + +/* Define the union csr_fq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_vld : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_ctrl_u; + +/* Define the union csr_fq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stffq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_timeout_u; + +/* Define the union csr_fq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stffq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_dat0_u; + +/* Define the union csr_fq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stffq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_indrect_dat1_u; + +/* Define the union csr_fq_qcntx_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wm_lru : 8; /* [7:0] */ + u32 rsv_5 : 4; /* [11:8] */ + u32 cfg_lqp_lru : 1; /* [12] */ + u32 cfg_w2r_byps_en : 1; /* [13] */ + u32 cfg_rcmd_npa_lb_oq_en : 1; /* [14] */ + u32 cfg_rcmd_pa_lb_oq_en : 1; /* [15] */ + u32 cfg_wdog_rfil_period : 8; /* [23:16] */ + u32 cfg_wdog_rfil_en : 1; /* [24] */ + u32 rsv_6 : 6; /* [30:25] */ + u32 cfg_rfl_fastlck_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_qcntx_mode_u; + +/* Define the union csr_fq_age_period_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_age_period : 12; /* [11:0] */ + u32 cfg_age_period_bg : 4; /* [15:12] */ + u32 cfg_fstr_wg : 8; /* [23:16] */ + u32 rsv_7 : 2; /* [25:24] */ + u32 cfg_age_oeid_bg_en : 1; /* [26] */ + u32 cfg_wg_eng_en : 1; /* [27] */ + u32 cfg_age_oeid_en : 1; /* [28] */ + u32 cfg_age2un_en : 1; /* [29] */ + u32 cfg_fq_age_unit : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_age_period_reg_u; + +/* Define the union csr_stffq_dbe_hw_pfh_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_pfh_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stffq_dbe_hw_pfh_cfg_u; + +/* Define the union csr_fq_tmr_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_tmr_defer : 8; /* [7:0] */ + u32 st_tmr_exp : 8; /* [15:8] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_st_u; + +/* Define the union csr_fq_cpb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_adj_attr : 4; /* [3:0] */ + u32 dma_adj_attr_def : 4; /* [7:4] */ + u32 rsv_9 : 4; /* [11:8] */ + u32 otsd_psh_plen : 3; /* [14:12] */ + u32 rsv_10 : 1; /* [15] */ + u32 psh_plen_en : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cpb_cfg_u; + +/* Define the union csr_fq_crdt_2tlsmf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_crdt_cmd_smf : 4; /* [3:0] */ + u32 rsv_11 : 4; /* [7:4] */ + u32 cnt_crdt_dat_smf : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 cnt_crdt_tl0 : 4; /* [19:16] */ + u32 rsv_13 : 4; /* [23:20] */ + u32 cnt_crdt_tl1 : 5; /* [28:24] */ + u32 rsv_14 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_crdt_2tlsmf_st_u; + +/* Define the union csr_fq_crdt_2tlsmf_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_def_crdt_cmd_smf : 4; /* [3:0] */ + u32 cfg_def_crdt_dat_smf : 5; /* [8:4] */ + u32 rsv_15 : 3; /* [11:9] */ + u32 cfg_def_crdt_tl0_rsp : 4; /* [15:12] */ + u32 cfg_def_crdt_tl1_rsp : 4; /* [19:16] */ + u32 cfg_def_crdt_tmrs : 7; /* [26:20] */ + u32 rsv_16 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_crdt_2tlsmf_reg_u; + +/* Define the union csr_fq_cnt_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_17 : 18; /* [17:0] */ + u32 mon_sel_idx : 6; /* [23:18] */ + u32 cfg_cnt6_en : 1; /* [24] */ + u32 cfg_flit_cnt_en : 1; /* [25] */ + u32 cfg_cnt_en : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl_u; + +/* Define the union csr_fq_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt0_u; + +/* Define the union csr_fq_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt1_u; + +/* Define the union csr_fq_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt2_u; + +/* Define the union csr_fq_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt3_u; + +/* Define the union csr_fq_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt4_u; + +/* Define the union csr_fq_snapshot_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_snapsot_srv_typ : 4; /* [3:0] */ + u32 cfg_snapsot_src : 9; /* [12:4] */ + u32 cfg_snapsot_req_typ : 2; /* [14:13] */ + u32 cfg_snapsot_fqid : 12; /* [26:15] */ + u32 cfg_snapshot_filt_typ_en : 4; /* [30:27] */ + u32 cfg_snapshot_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_snapshot_ctl_u; + +/* Define the union csr_fq_snapshot_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_asc_latency : 8; /* [7:0] */ + u32 max_latency_stg : 8; /* [15:8] */ + u32 total_latency : 8; /* [23:16] */ + u32 rsv_18 : 7; /* [30:24] */ + u32 snapshot_done : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_snapshot_st_u; + +/* Define the union csr_fq_dbe_hw_wqe_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en_u; + +/* Define the union csr_fq_dbe_hw_wqe_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stagh_wqe_ld : 5; /* [4:0] */ + u32 cfg_opid_wqe_ld : 5; /* [9:5] */ + u32 cfg_aext_wqe_ld : 3; /* [12:10] */ + u32 cfg_ftid_wqe_ld : 6; /* [18:13] */ + u32 cfg_aext_ord : 3; /* [21:19] */ + u32 cfg_txpfl_qp_push : 3; /* [24:22] */ + u32 cfg_rxpfl_qp_push : 3; /* [27:25] */ + u32 cfg_otsd_qp_push : 3; /* [30:28] */ + u32 rsv_19 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_cfg_u; + +/* Define the union csr_fq_fifo_gap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gap_fifo_rsp2tl : 7; /* [6:0] */ + u32 rsv_20 : 1; /* [7] */ + u32 gap_cmds_fifos : 4; /* [11:8] */ + u32 gap_fifo_p2t_cmd : 5; /* [16:12] */ + u32 rsv_21 : 3; /* [19:17] */ + u32 gap_afifo_cpback : 5; /* [24:20] */ + u32 gap_bnd_oeid : 3; /* [27:25] */ + u32 gap_afifo_icc_rsp : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_fifo_gap_cfg_u; + +/* Define the union csr_fq_his_fifo_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 p2e_f : 4; /* [3:0] */ + u32 p2e_rbnd : 4; /* [7:4] */ + u32 p2e_ulck : 4; /* [11:8] */ + u32 rlck_pcm : 4; /* [15:12] */ + u32 cpback : 8; /* [23:16] */ + u32 icc_rsp : 4; /* [27:24] */ + u32 rlck : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_his_fifo_cnt0_u; + +/* Define the union csr_fq_his_fifo_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 empty_tpfh : 1; /* [0] */ + u32 empty_spqc : 1; /* [1] */ + u32 empty_rqpc : 1; /* [2] */ + u32 empty_ism : 1; /* [3] */ + u32 empty_tpcl : 1; /* [4] */ + u32 empty_tcm : 1; /* [5] */ + u32 rsv_22 : 2; /* [7:6] */ + u32 tl0_req : 6; /* [13:8] */ + u32 tl1_req : 6; /* [19:14] */ + u32 tl2p_cmds : 4; /* [23:20] */ + u32 tl2p_rfl : 4; /* [27:24] */ + u32 p2tl_cmds : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_his_fifo_cnt1_u; + +/* Define the union csr_fq_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 afull_tl0_rsp : 1; /* [0] */ + u32 afull_tl1_rsp : 1; /* [1] */ + u32 afull_tl0_req : 1; /* [2] */ + u32 afull_tl1_req : 1; /* [3] */ + u32 afull_tl2p_cmds : 1; /* [4] */ + u32 afull_tl2p_rfl : 1; /* [5] */ + u32 afull_p2tl_cmds : 1; /* [6] */ + u32 afull_p2e_f : 1; /* [7] */ + u32 afull_p2e_rbnd : 1; /* [8] */ + u32 afull_p2e_ulck : 1; /* [9] */ + u32 afull_rlck_pcm : 1; /* [10] */ + u32 afull_cpback : 1; /* [11] */ + u32 afull_icc_rsp : 1; /* [12] */ + u32 afull_bnd : 1; /* [13] */ + u32 empty_tl0_0dat : 1; /* [14] */ + u32 empty_tl0_idat : 1; /* [15] */ + u32 empty_tl1_0dat : 1; /* [16] */ + u32 empty_tl1_idat : 1; /* [17] */ + u32 empty_tl0_rsp : 1; /* [18] */ + u32 empty_tl1_rsp : 1; /* [19] */ + u32 empty_tl0_req : 1; /* [20] */ + u32 empty_tl1_req : 1; /* [21] */ + u32 empty_tl2p_cmds : 1; /* [22] */ + u32 empty_tl2p_rfl : 1; /* [23] */ + u32 empty_p2tl_cmds : 1; /* [24] */ + u32 empty_p2e_f : 1; /* [25] */ + u32 empty_p2e_rbnd : 1; /* [26] */ + u32 empty_p2e_ulck : 1; /* [27] */ + u32 empty_rlck_pcm : 1; /* [28] */ + u32 empty_cpback : 1; /* [29] */ + u32 empty_icc_rsp : 1; /* [30] */ + u32 empty_bnd : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_fifo_st_u; + +/* Define the union csr_fq_his_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 his_ful_tl0_rsp : 1; /* [0] */ + u32 his_ful_tl1_rsp : 1; /* [1] */ + u32 his_ful_tl0_req : 1; /* [2] */ + u32 his_ful_tl1_req : 1; /* [3] */ + u32 his_ful_fifo_tl2p_cmds : 1; /* [4] */ + u32 his_ful_fifo_tl2p_rfl : 1; /* [5] */ + u32 his_ful_fifo_p2tl_cmds : 1; /* [6] */ + u32 his_ful_fifo_p2e_f : 1; /* [7] */ + u32 his_ful_fifo_p2e_rbnd : 1; /* [8] */ + u32 his_ful_fifo_p2e_ulck : 1; /* [9] */ + u32 his_ful_fifo_rlck_pcm : 1; /* [10] */ + u32 his_ful_afifo_cpback : 1; /* [11] */ + u32 his_ful_afifo_icc_rsp : 1; /* [12] */ + u32 his_ful_afifo_bnd : 1; /* [13] */ + u32 his_ful_tl0_idat : 1; /* [14] */ + u32 his_ful_tl0_odat : 1; /* [15] */ + u32 his_ful_tl1_idat : 1; /* [16] */ + u32 his_ful_tl1_odat : 1; /* [17] */ + u32 his_ful_ism_dat : 1; /* [18] */ + u32 his_ful_sqpc : 1; /* [19] */ + u32 his_ful_rqpc : 1; /* [20] */ + u32 his_ful_tpfh : 1; /* [21] */ + u32 his_ful_tpcl : 1; /* [22] */ + u32 his_ful_tcm : 1; /* [23] */ + u32 rsv_23 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_his_fifo_st_u; + +/* Define the union csr_fq_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_power_ctrl_sp : 3; /* [2:0] */ + u32 rsv_24 : 1; /* [3] */ + u32 mem_timing_ctrl_sp : 8; /* [11:4] */ + u32 mem_power_ctrl_tp : 3; /* [14:12] */ + u32 rsv_25 : 1; /* [15] */ + u32 mem_timing_ctrl_tp : 8; /* [23:16] */ + u32 rsv_26 : 4; /* [27:24] */ + u32 err_req : 2; /* [29:28] */ + u32 indirect_mem_ecc_en : 1; /* [30] */ + u32 mem_ecc_bypass : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mem_ctrl_u; + +/* Define the union csr_fq_cfg_ep2host_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_map_ep2host : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_ep2host_u; + +/* Define the union csr_fq_pcar_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcar_sh : 20; /* [19:0] */ + u32 cfg_pcar_sml : 1; /* [20] */ + u32 cfg_pcar_opid : 5; /* [25:21] */ + u32 cfg_pcar_inst : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_pcar_cfg_u; + +/* Define the union csr_fq_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt5_u; + +/* Define the union csr_fq_mod_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 base_sub_pro_typ : 4; /* [3:0] */ + u32 max_sub_pro_typ : 4; /* [7:4] */ + u32 cfg_pro_typ_nret_pkt : 4; /* [11:8] */ + u32 cfg_pro_typ_lb : 4; /* [15:12] */ + u32 cfg_th_fc_on : 8; /* [23:16] */ + u32 cfg_th_fc_dif : 4; /* [27:24] */ + u32 cfg_th_fc_mode : 2; /* [29:28] */ + u32 cfg_dsp_fstr_cup_en : 1; /* [30] */ + u32 cfg_dsp_fastlck_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mod_reg1_u; + +/* Define the union csr_fq_inner_bp_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_27 : 3; /* [2:0] */ + u32 tmr_stf_bp : 1; /* [3] */ + u32 tmr_stl_bp : 1; /* [4] */ + u32 pro2cmd_bp : 1; /* [5] */ + u32 t2cup_bp : 1; /* [6] */ + u32 fcam_pfh_bp : 1; /* [7] */ + u32 fq2smf_bp : 1; /* [8] */ + u32 smf2fq_dat_bp : 1; /* [9] */ + u32 smf2fq_cmd_bp : 1; /* [10] */ + u32 rsc_qidx_bp : 1; /* [11] */ + u32 rsc_fqg_bp : 1; /* [12] */ + u32 rsc_lqp_bp : 1; /* [13] */ + u32 t2fsg_rls_bp : 1; /* [14] */ + u32 t2fsg_bp : 1; /* [15] */ + u32 t2rfl_bp : 1; /* [16] */ + u32 t2pfh_bp : 1; /* [17] */ + u32 rstg1_bp : 1; /* [18] */ + u32 rstg0_bp : 1; /* [19] */ + u32 fq2tl1_req_bp : 1; /* [20] */ + u32 tl02fq_req_bp : 1; /* [21] */ + u32 fq2tl1_rsp_bp : 1; /* [22] */ + u32 fq2tl0_rsp_bp : 1; /* [23] */ + u32 fq2pdm_dcc_bp : 1; /* [24] */ + u32 fq2pdm_icc_bp : 1; /* [25] */ + u32 ritf_tcm_bp : 1; /* [26] */ + u32 ritf_ord_bp : 1; /* [27] */ + u32 fq_psh_msg_bp : 1; /* [28] */ + u32 fq2iq_lb_bp : 1; /* [29] */ + u32 fq2oq_dsp_bp : 1; /* [30] */ + u32 fq2iq_bnd_bp : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_bp_st_u; + +/* Define the union csr_fq_inner_mon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st_u; + +/* Define the union csr_fq_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt6_u; + +/* Define the union csr_fq_cnt_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fa_cnt1_reserved : 4; /* [3:0] */ + u32 cfg_typ_cnt9 : 2; /* [5:4] */ + u32 rsv_28 : 16; /* [21:6] */ + u32 cfg_cnt_1_en : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl1_u; + +/* Define the union csr_fq_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt7_u; + +/* Define the union csr_fq_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt8_u; + +/* Define the union csr_fq_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt9_u; + +/* Define the union csr_fq_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt10_u; + +/* Define the union csr_fq_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt11_u; + +/* Define the union csr_fq_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt12_u; + +/* Define the union csr_fq_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt13_u; + +/* Define the union csr_fq_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt14_u; + +/* Define the union csr_fq_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt15_u; + +/* Define the union csr_fq_cnt16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt16_u; + +/* Define the union csr_fq_int_mem_err_1b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_err_1b_error_bit : 1; /* [0] */ + u32 int_insrt10 : 1; /* [1] */ + u32 mem_err_1b_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_mem_err_1b_u; + +/* Define the union csr_cfg_styp_th_fc_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_styp_th_fc_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_styp_th_fc_en_u; + +/* Define the union csr_cfg_zero_esch_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_zero_esch_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_zero_esch_len_u; + +/* Define the union csr_cfg_fq_bubble_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_bubble_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_fq_bubble_ctl_u; + +/* Define the union csr_cfg_l2dcache_bubble_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_l2dcache_bubble_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_l2dcache_bubble_ctl_u; + +/* Define the union csr_fq_def_fq_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_tx_base_init_def_fq : 12; /* [11:0] */ + u32 cfg_tx_mode_init_def_fq : 2; /* [13:12] */ + u32 reserved2 : 2; /* [15:14] */ + u32 cfg_rx_base_init_def_fq : 12; /* [27:16] */ + u32 cfg_rx_mode_init_def_fq : 2; /* [29:28] */ + u32 reserved1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_def_fq_ctl_u; + +/* Define the union csr_fq_smf_ldbctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_smf_ldb_ctl_vfen : 1; /* [0] */ + u32 fq_smf_ldb_ctl_ofst : 5; /* [5:1] */ + u32 fq_tmr_pro_typ_ctl : 14; /* [19:6] */ + u32 fq_smf_only1_ctl : 1; /* [20] */ + u32 fq_smf_lbctl_reserved1 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_smf_ldbctl_u; + +/* Define the union csr_fq_cfg_ep2host_h2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_map_ep2host_h2 : 16; /* [15:0] */ + u32 cfg_map_ep2host_rsvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_ep2host_h2_u; + +/* Define the union csr_fq_cfg_prefetch_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_pfhctl_coco_xid20 : 1; /* [0] */ + u32 fq_base_sub_pro_typ : 7; /* [7:1] */ + u32 fq_max_sub_pro_typ : 7; /* [14:8] */ + u32 fq_cfg_pro_typ_nret_pkt : 7; /* [21:15] */ + u32 fq_cfg_pro_typ_lb : 7; /* [28:22] */ + u32 fq_cfg_pro_typ_lb_org : 1; /* [29] */ + u32 fq_cfg_pro_typ_nret_org : 1; /* [30] */ + u32 fq_cfg_prefetch_ctl_rsvd : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_prefetch_ctl_u; + +/* Define the union csr_fq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_fq_sample_mode : 1; /* [0] */ + u32 csr_fq_spec_port_en : 1; /* [1] */ + u32 csr_fq_done_clr : 1; /* [2] */ + u32 rsv_29 : 1; /* [3] */ + u32 csr_fq_spec_port_num : 4; /* [7:4] */ + u32 csr_fq_spec_pptr_typ : 8; /* [15:8] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_latency_cfg_u; + +/* Define the union csr_fq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_csr_sample_done : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_latency_sta_u; + +/* Define the union csr_fq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_sample_tmr_u; + +/* Define the union csr_fq_cfg_fake_vf_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_fake_vfid_pf_rsvd2 : 16; /* [15:0] */ + u32 fq_fake_vfid_pf_start_bit : 4; /* [19:16] */ + u32 fq_fake_vfid_pf_end_bit : 4; /* [23:20] */ + u32 fq_fake_vfid_pf_rsvd1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_fake_vf_ctl_u; + +/* Define the union csr_fq_cfg_bps_dly_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_bps_dly_dbld : 1; /* [0] */ + u32 fq_cfg_bps_dly_fsg : 1; /* [1] */ + u32 fq_cfg_bpsfsg_oeid_th : 11; /* [12:2] */ + u32 fq_cfg_bps_dly_rsvd : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_bps_dly_ctl_u; + +/* Define the union csr_fq_cfg_otsd_base_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_otsd_base_ctl_val : 4; /* [3:0] */ + u32 fq_cfg_otsd_base_ctl_rsvd : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_otsd_base_ctl_u; + +/* Define the union csr_fq_cnt_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_32 : 22; /* [21:0] */ + u32 cfg_cnt_2_en : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl2_u; + +/* Define the union csr_fq_cnt17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt17_u; + +/* Define the union csr_fq_cnt18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt18_u; + +/* Define the union csr_fq_cnt19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt19_u; + +/* Define the union csr_fq_cnt20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt20_u; + +/* Define the union csr_fq_cnt21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt21_u; + +/* Define the union csr_fq_cnt22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt22_u; + +/* Define the union csr_fq_cnt23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt23_u; + +/* Define the union csr_fq_cnt24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt24_u; + +/* Define the union csr_fq_cnt25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt25_u; + +/* Define the union csr_fq_cnt26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt26_u; + +/* Define the union csr_fq_cnt_ctl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 22; /* [21:0] */ + u32 cfg_cnt_3_en : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl3_u; + +/* Define the union csr_fq_cnt27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt27_u; + +/* Define the union csr_fq_cnt28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt28_u; + +/* Define the union csr_fq_cnt29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt29_u; + +/* Define the union csr_fq_cnt30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt30_u; + +/* Define the union csr_fq_cnt31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt31_u; + +/* Define the union csr_fq_cnt32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt32_u; + +/* Define the union csr_fq_cnt33_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt33 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt33_u; + +/* Define the union csr_fq_cnt34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt34 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt34_u; + +/* Define the union csr_fq_cnt35_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt35 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt35_u; + +/* Define the union csr_fq_cnt36_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt36 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt36_u; + +/* Define the union csr_fq_cnt_ctl4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_34 : 21; /* [20:0] */ + u32 cfg_cnt_4_en : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt_ctl4_u; + +/* Define the union csr_fq_cnt37_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt37 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt37_u; + +/* Define the union csr_fq_cnt38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt38 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt38_u; + +/* Define the union csr_fq_cnt39_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt39 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt39_u; + +/* Define the union csr_fq_cnt40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt40_u; + +/* Define the union csr_fq_cnt41_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt41 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt41_u; + +/* Define the union csr_fq_cnt42_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt42 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt42_u; + +/* Define the union csr_fq_cnt43_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt43 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt43_u; + +/* Define the union csr_fq_cnt44_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt44 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt44_u; + +/* Define the union csr_fq_cnt45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt45 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt45_u; + +/* Define the union csr_fq_cnt46_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt46 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt46_u; + +/* Define the union csr_fq_qu2smf_tmr_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_qu2smf_tmr_dly_val : 31; /* [30:0] */ + u32 fq_qu2smf_tmr_dly_op : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_qu2smf_tmr_dly_u; + +/* Define the union csr_fq_magic_box_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_mgbx_quf_pg : 2; /* [1:0] */ + u32 fq_mgbx_smf_pg : 4; /* [5:2] */ + u32 fq_mgbx_lbf_mode : 2; /* [7:6] */ + u32 rsv_35 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_magic_box_ctl_u; + +/* Define the union csr_fq_mgbx_srv2hash_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_mgbx_srv2hash : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_mgbx_srv2hash_u; + +/* Define the union csr_fq_inner_mon_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st1_u; + +/* Define the union csr_fq_inner_mon_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st2_u; + +/* Define the union csr_fq_inner_mon_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st3_u; + +/* Define the union csr_fq_inner_mon_st4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st4_u; + +/* Define the union csr_fq_inner_mon_st5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st5_u; + +/* Define the union csr_fq_inner_mon_st6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st6_u; + +/* Define the union csr_fq_inner_mon_st7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st7_u; + +/* Define the union csr_fq_inner_mon_st8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st8_u; + +/* Define the union csr_fq_inner_mon_st9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st9_u; + +/* Define the union csr_fq_inner_mon_st10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st10_u; + +/* Define the union csr_fq_inner_mon_st11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st11_u; + +/* Define the union csr_fq_inner_mon_st12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st12_u; + +/* Define the union csr_fq_inner_mon_st13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st13_u; + +/* Define the union csr_fq_inner_mon_st14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st14_u; + +/* Define the union csr_fq_inner_mon_st15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st15_u; + +/* Define the union csr_fq_inner_mon_st16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st16_u; + +/* Define the union csr_fq_inner_mon_st17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st17_u; + +/* Define the union csr_fq_inner_mon_st18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st18_u; + +/* Define the union csr_fq_inner_mon_st19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st19_u; + +/* Define the union csr_fq_inner_mon_st20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st20_u; + +/* Define the union csr_fq_inner_mon_st21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st21_u; + +/* Define the union csr_fq_inner_mon_st22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st22_u; + +/* Define the union csr_fq_inner_mon_st23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st23_u; + +/* Define the union csr_fq_inner_mon_st24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st24_u; + +/* Define the union csr_fq_inner_mon_st25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st25_u; + +/* Define the union csr_fq_inner_mon_st26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st26_u; + +/* Define the union csr_fq_inner_mon_st27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st27_u; + +/* Define the union csr_fq_inner_mon_st28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st28_u; + +/* Define the union csr_fq_inner_mon_st29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st29_u; + +/* Define the union csr_fq_inner_mon_st30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st30_u; + +/* Define the union csr_fq_inner_mon_st31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st31_u; + +/* Define the union csr_fq_inner_mon_st32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st32_u; + +/* Define the union csr_fq_inner_mon_st33_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st33 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st33_u; + +/* Define the union csr_fq_inner_mon_st34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st34 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st34_u; + +/* Define the union csr_fq_inner_mon_st35_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st35 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st35_u; + +/* Define the union csr_fq_inner_mon_st36_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st36 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st36_u; + +/* Define the union csr_fq_inner_mon_st37_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st37 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st37_u; + +/* Define the union csr_fq_inner_mon_st38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st38 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st38_u; + +/* Define the union csr_fq_inner_mon_st39_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st39 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st39_u; + +/* Define the union csr_fq_inner_mon_st40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st40_u; + +/* Define the union csr_fq_inner_mon_st41_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st41 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st41_u; + +/* Define the union csr_fq_inner_mon_st42_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st42 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st42_u; + +/* Define the union csr_fq_inner_mon_st43_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st43 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st43_u; + +/* Define the union csr_fq_inner_mon_st44_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st44 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st44_u; + +/* Define the union csr_fq_inner_mon_st45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st45 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st45_u; + +/* Define the union csr_fq_inner_mon_st46_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st46 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st46_u; + +/* Define the union csr_fq_inner_mon_st47_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st47_u; + +/* Define the union csr_fq_inner_mon_st48_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_inner_mon_st48 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_inner_mon_st48_u; + +/* Define the union csr_fq_cnt47_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt47_u; + +/* Define the union csr_fq_rou_rqst_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_rqst_fifo_st0 : 16; /* [15:0] */ + u32 rou_rqst_i_ae_th0 : 8; /* [23:16] */ + u32 rou_rqst_i_af_th0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_rqst_fifo0_u; + +/* Define the union csr_fq_rou_rsp_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_rsp_fifo_st0 : 16; /* [15:0] */ + u32 rou_rsp_i_ae_th0 : 8; /* [23:16] */ + u32 rou_rsp_i_af_th0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_rsp_fifo0_u; + +/* Define the union csr_fq_rou_rsp_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_rsp_fifo_st1 : 16; /* [15:0] */ + u32 rou_rsp_i_ae_th1 : 8; /* [23:16] */ + u32 rou_rsp_i_af_th1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_rsp_fifo1_u; + +/* Define the union csr_fq_rou_tmrodr_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst0_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst0_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst0_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo0_u; + +/* Define the union csr_fq_rou_tmrodr_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst1_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst1_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst1_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo1_u; + +/* Define the union csr_fq_rou_tmrodr_fifo2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst2_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst2_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst2_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo2_u; + +/* Define the union csr_fq_rou_tmrodr_fifo3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rou_tmrodr_rqst3_fifo_st : 16; /* [15:0] */ + u32 rou_tmrodr_rqst3_i_ae_th : 8; /* [23:16] */ + u32 rou_tmrodr_rqst3_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rou_tmrodr_fifo3_u; + +/* Define the union csr_fq_rin_rqst_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rin_rqst_fifo_st : 16; /* [15:0] */ + u32 rin_rqst_i_ae_th : 8; /* [23:16] */ + u32 rin_rqst_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rin_rqst_fifo_u; + +/* Define the union csr_fq_rin_rsp_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rin_rsp_fifo_st : 16; /* [15:0] */ + u32 rin_rsp_i_ae_th : 8; /* [23:16] */ + u32 rin_rsp_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rin_rsp_fifo_u; + +/* Define the union csr_fq_smf_rsp_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rsp0_fifo_st : 16; /* [15:0] */ + u32 smf_rsp0_i_ae_th : 8; /* [23:16] */ + u32 smf_rsp0_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_smf_rsp_fifo0_u; + +/* Define the union csr_fq_smf_rsp_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rsp1_fifo_st : 16; /* [15:0] */ + u32 smf_rsp1_i_ae_th : 8; /* [23:16] */ + u32 smf_rsp1_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_smf_rsp_fifo1_u; + +/* Define the union csr_fq_tl0_cmd_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl0_cmd_fifo_st : 16; /* [15:0] */ + u32 tl0_cmd_i_ae_th : 8; /* [23:16] */ + u32 tl0_cmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl0_cmd_fifo0_u; + +/* Define the union csr_fq_tl0_extcmd_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl0_extcmd_fifo_st : 16; /* [15:0] */ + u32 tl0_extcmd_i_ae_th : 8; /* [23:16] */ + u32 tl0_extcmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl0_extcmd_fifo0_u; + +/* Define the union csr_fq_tl1_cmd_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl1_cmd_fifo_st : 16; /* [15:0] */ + u32 tl1_cmd_i_ae_th : 8; /* [23:16] */ + u32 tl1_cmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl1_cmd_fifo1_u; + +/* Define the union csr_fq_tl1_extcmd_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl1_extcmd_fifo_st : 16; /* [15:0] */ + u32 tl1_extcmd_i_ae_th : 8; /* [23:16] */ + u32 tl1_extcmd_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tl1_extcmd_fifo0_u; + +/* Define the union csr_fq_fq2oq_fcnp_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq2oq_fcnp_fifo_st : 16; /* [15:0] */ + u32 fq2oq_fcnp_i_ae_th : 8; /* [23:16] */ + u32 fq2oq_fcnp_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_fq2oq_fcnp_fifo_u; + +/* Define the union csr_fq_oq2fq_fcnp_fifo_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq2fq_fcnp_fifo_st : 16; /* [15:0] */ + u32 oq2fq_fcnp_i_ae_th : 8; /* [23:16] */ + u32 oq2fq_fcnp_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_oq2fq_fcnp_fifo_u; + +/* Define the union csr_fq_tmr_rsp_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp0_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp0_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp0_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo0_u; + +/* Define the union csr_fq_tmr_rsp_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp1_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp1_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp1_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo1_u; + +/* Define the union csr_fq_tmr_rsp_fifo2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp2_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp2_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp2_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo2_u; + +/* Define the union csr_fq_tmr_rsp_fifo3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp3_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp3_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp3_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo3_u; + +/* Define the union csr_fq_tmr_rsp_fifo4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp4_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp4_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp4_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo4_u; + +/* Define the union csr_fq_tmr_rsp_fifo5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp5_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp5_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp5_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo5_u; + +/* Define the union csr_fq_tmr_rsp_fifo6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp6_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp6_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp6_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo6_u; + +/* Define the union csr_fq_tmr_rsp_fifo7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp7_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp7_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp7_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo7_u; + +/* Define the union csr_fq_tmr_rsp_fifo8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp8_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp8_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp8_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo8_u; + +/* Define the union csr_fq_tmr_rsp_fifo9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp9_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp9_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp9_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo9_u; + +/* Define the union csr_fq_tmr_rsp_fifo10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp10_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp10_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp10_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo10_u; + +/* Define the union csr_fq_tmr_rsp_fifo11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp11_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp11_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp11_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo11_u; + +/* Define the union csr_fq_tmr_rsp_fifo12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp12_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp12_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp12_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo12_u; + +/* Define the union csr_fq_tmr_rsp_fifo13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp13_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp13_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp13_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo13_u; + +/* Define the union csr_fq_tmr_rsp_fifo14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp14_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp14_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp14_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo14_u; + +/* Define the union csr_fq_tmr_rsp_fifo15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmr_rsp15_fifo_st : 16; /* [15:0] */ + u32 tmr_rsp15_i_ae_th : 8; /* [23:16] */ + u32 tmr_rsp15_i_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_tmr_rsp_fifo15_u; + +/* Define the union csr_fq_int_rin_rqst_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_rin_rqst_err : 1; /* [0] */ + u32 int_insrt11 : 1; /* [1] */ + u32 fq_rin_rqst_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_rin_rqst_err_u; + +/* Define the union csr_fq_int_rin_rsp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_rin_rsp_err : 1; /* [0] */ + u32 int_insrt12 : 1; /* [1] */ + u32 fq_rin_rsp_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_rin_rsp_err_u; + +/* Define the union csr_fq_int_rin_trsp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_rin_trsp_err : 1; /* [0] */ + u32 int_insrt13 : 1; /* [1] */ + u32 fq_rin_trsp_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_rin_trsp_err_u; + +/* Define the union csr_fq_int_fifo1_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_fifo1_err : 1; /* [0] */ + u32 int_insrt14 : 1; /* [1] */ + u32 fq_fifo1_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fifo1_err_u; + +/* Define the union csr_fq_int_fifo2_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_fifo2_err : 1; /* [0] */ + u32 int_insrt15 : 1; /* [1] */ + u32 fq_fifo2_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_int_fifo2_err_u; + +/* Define the union csr_fq_cnt48_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt48 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt48_u; + +/* Define the union csr_fq_cfg_stg_qp_push0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_stg_qp_push0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_stg_qp_push0_u; + +/* Define the union csr_fq_cfg_stg_qp_push1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_stg_qp_push1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_stg_qp_push1_u; + +/* Define the union csr_fq_cfg_stg_qp_push2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cfg_stg_qp_push2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cfg_stg_qp_push2_u; + +/* Define the union csr_fq_dbe_hw_wqe_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en1_u; + +/* Define the union csr_fq_dbe_hw_wqe_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en2_u; + +/* Define the union csr_fq_dbe_hw_wqe_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en3_u; + +/* Define the union csr_fq_dbe_hw_wqe_en4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en4_u; + +/* Define the union csr_fq_dbe_hw_wqe_en5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en5_u; + +/* Define the union csr_fq_dbe_hw_wqe_en6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en6_u; + +/* Define the union csr_fq_dbe_hw_wqe_en7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en7_u; + +/* Define the union csr_fq_dbe_hw_wqe_en8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en8_u; + +/* Define the union csr_fq_dbe_hw_wqe_en9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en9_u; + +/* Define the union csr_fq_dbe_hw_wqe_en10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en10_u; + +/* Define the union csr_fq_dbe_hw_wqe_en11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en11_u; + +/* Define the union csr_fq_dbe_hw_wqe_en12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en12_u; + +/* Define the union csr_fq_dbe_hw_wqe_en13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en13_u; + +/* Define the union csr_fq_dbe_hw_wqe_en14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en14_u; + +/* Define the union csr_fq_dbe_hw_wqe_en15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dbe_hw_wqe_en15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_dbe_hw_wqe_en15_u; + +/* Define the union csr_fq_cnt49_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt49 : 24; /* [23:0] */ + u32 rsv_36 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt49_u; + +/* Define the union csr_fq_cnt50_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt50 : 24; /* [23:0] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt50_u; + +/* Define the union csr_fq_cnt51_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt51 : 24; /* [23:0] */ + u32 rsv_38 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt51_u; + +/* Define the union csr_fq_cnt52_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt52 : 24; /* [23:0] */ + u32 rsv_39 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt52_u; + +/* Define the union csr_fq_cnt53_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt53 : 24; /* [23:0] */ + u32 rsv_40 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt53_u; + +/* Define the union csr_fq_cnt54_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt54 : 24; /* [23:0] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt54_u; + +/* Define the union csr_fq_cnt55_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt55 : 24; /* [23:0] */ + u32 rsv_42 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt55_u; + +/* Define the union csr_fq_cnt56_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt56 : 24; /* [23:0] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt56_u; + +/* Define the union csr_fq_cnt57_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt57 : 24; /* [23:0] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt57_u; + +/* Define the union csr_fq_cnt58_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt58 : 24; /* [23:0] */ + u32 rsv_45 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt58_u; + +/* Define the union csr_fq_cnt59_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt59 : 24; /* [23:0] */ + u32 rsv_46 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt59_u; + +/* Define the union csr_fq_cnt60_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt60 : 24; /* [23:0] */ + u32 rsv_47 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt60_u; + +/* Define the union csr_fq_cnt61_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt61 : 24; /* [23:0] */ + u32 rsv_48 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt61_u; + +/* Define the union csr_fq_cnt62_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt62 : 24; /* [23:0] */ + u32 rsv_49 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt62_u; + +/* Define the union csr_fq_cnt63_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt63 : 24; /* [23:0] */ + u32 rsv_50 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt63_u; + +/* Define the union csr_fq_cnt64_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt64 : 24; /* [23:0] */ + u32 rsv_51 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt64_u; + +/* Define the union csr_fq_cnt65_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt65 : 24; /* [23:0] */ + u32 rsv_52 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt65_u; + +/* Define the union csr_fq_cnt66_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt66 : 24; /* [23:0] */ + u32 rsv_53 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt66_u; + +/* Define the union csr_fq_cnt67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt67 : 24; /* [23:0] */ + u32 rsv_54 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt67_u; + +/* Define the union csr_fq_cnt68_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt68 : 24; /* [23:0] */ + u32 rsv_55 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt68_u; + +/* Define the union csr_fq_cnt69_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt69 : 24; /* [23:0] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt69_u; + +/* Define the union csr_fq_cnt70_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt70 : 24; /* [23:0] */ + u32 rsv_57 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt70_u; + +/* Define the union csr_fq_cnt71_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt71 : 24; /* [23:0] */ + u32 rsv_58 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt71_u; + +/* Define the union csr_fq_cnt72_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt72 : 24; /* [23:0] */ + u32 rsv_59 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt72_u; + +/* Define the union csr_fq_cnt73_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt73 : 24; /* [23:0] */ + u32 rsv_60 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt73_u; + +/* Define the union csr_fq_cnt74_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt74 : 24; /* [23:0] */ + u32 rsv_61 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt74_u; + +/* Define the union csr_fq_cnt75_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt75 : 24; /* [23:0] */ + u32 rsv_62 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt75_u; + +/* Define the union csr_fq_cnt76_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt76 : 24; /* [23:0] */ + u32 rsv_63 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt76_u; + +/* Define the union csr_fq_cnt77_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt77 : 24; /* [23:0] */ + u32 rsv_64 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt77_u; + +/* Define the union csr_fq_cnt78_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt78 : 24; /* [23:0] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt78_u; + +/* Define the union csr_fq_cnt79_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt79 : 24; /* [23:0] */ + u32 rsv_66 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt79_u; + +/* Define the union csr_fq_cnt80_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt80 : 24; /* [23:0] */ + u32 rsv_67 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt80_u; + +/* Define the union csr_fq_cnt81_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt81 : 24; /* [23:0] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt81_u; + +/* Define the union csr_fq_cnt82_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt82 : 24; /* [23:0] */ + u32 rsv_69 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt82_u; + +/* Define the union csr_fq_cnt83_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt83 : 24; /* [23:0] */ + u32 rsv_70 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt83_u; + +/* Define the union csr_fq_cnt84_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt84 : 24; /* [23:0] */ + u32 rsv_71 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt84_u; + +/* Define the union csr_fq_cnt85_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt85 : 24; /* [23:0] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt85_u; + +/* Define the union csr_fq_cnt86_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt86 : 24; /* [23:0] */ + u32 rsv_73 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt86_u; + +/* Define the union csr_fq_cnt87_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt87 : 24; /* [23:0] */ + u32 rsv_74 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt87_u; + +/* Define the union csr_fq_cnt88_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt88 : 24; /* [23:0] */ + u32 rsv_75 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt88_u; + +/* Define the union csr_fq_cnt89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt89 : 24; /* [23:0] */ + u32 rsv_76 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt89_u; + +/* Define the union csr_fq_cnt90_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt90 : 24; /* [23:0] */ + u32 rsv_77 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt90_u; + +/* Define the union csr_fq_cnt91_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt91 : 24; /* [23:0] */ + u32 rsv_78 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt91_u; + +/* Define the union csr_fq_cnt92_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt92 : 24; /* [23:0] */ + u32 rsv_79 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt92_u; + +/* Define the union csr_fq_cnt93_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt93 : 24; /* [23:0] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt93_u; + +/* Define the union csr_fq_cnt94_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt94 : 24; /* [23:0] */ + u32 rsv_81 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt94_u; + +/* Define the union csr_fq_cnt95_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt95 : 24; /* [23:0] */ + u32 rsv_82 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt95_u; + +/* Define the union csr_fq_cnt96_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt96 : 24; /* [23:0] */ + u32 rsv_83 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt96_u; + +/* Define the union csr_fq_cnt97_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt97 : 24; /* [23:0] */ + u32 rsv_84 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt97_u; + +/* Define the union csr_fq_cnt98_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt98 : 24; /* [23:0] */ + u32 rsv_85 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt98_u; + +/* Define the union csr_fq_cnt99_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt99 : 24; /* [23:0] */ + u32 rsv_86 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt99_u; + +/* Define the union csr_fq_cnt100_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt100 : 24; /* [23:0] */ + u32 rsv_87 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt100_u; + +/* Define the union csr_fq_cnt101_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt101 : 24; /* [23:0] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt101_u; + +/* Define the union csr_fq_cnt102_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt102 : 24; /* [23:0] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt102_u; + +/* Define the union csr_fq_cnt103_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt103 : 24; /* [23:0] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt103_u; + +/* Define the union csr_fq_cnt104_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt104 : 24; /* [23:0] */ + u32 rsv_91 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt104_u; + +/* Define the union csr_fq_cnt105_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt105 : 24; /* [23:0] */ + u32 rsv_92 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt105_u; + +/* Define the union csr_fq_cnt106_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt106 : 24; /* [23:0] */ + u32 rsv_93 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt106_u; + +/* Define the union csr_fq_cnt107_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt107 : 24; /* [23:0] */ + u32 rsv_94 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt107_u; + +/* Define the union csr_fq_cnt108_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt108 : 24; /* [23:0] */ + u32 rsv_95 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt108_u; + +/* Define the union csr_fq_cnt109_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt109 : 24; /* [23:0] */ + u32 rsv_96 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt109_u; + +/* Define the union csr_fq_cnt110_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt110 : 24; /* [23:0] */ + u32 rsv_97 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt110_u; + +/* Define the union csr_fq_cnt111_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt111 : 24; /* [23:0] */ + u32 rsv_98 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt111_u; + +/* Define the union csr_fq_cnt112_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt112 : 24; /* [23:0] */ + u32 rsv_99 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt112_u; + +/* Define the union csr_fq_cnt113_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt113 : 24; /* [23:0] */ + u32 rsv_100 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt113_u; + +/* Define the union csr_fq_cnt114_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt114 : 24; /* [23:0] */ + u32 rsv_101 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt114_u; + +/* Define the union csr_fq_cnt115_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt115 : 24; /* [23:0] */ + u32 rsv_102 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt115_u; + +/* Define the union csr_fq_cnt116_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt116 : 24; /* [23:0] */ + u32 rsv_103 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt116_u; + +/* Define the union csr_fq_cnt117_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt117 : 24; /* [23:0] */ + u32 rsv_104 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt117_u; + +/* Define the union csr_fq_cnt118_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt118 : 24; /* [23:0] */ + u32 rsv_105 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt118_u; + +/* Define the union csr_fq_cnt119_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt119 : 24; /* [23:0] */ + u32 rsv_106 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt119_u; + +/* Define the union csr_fq_cnt120_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt120 : 24; /* [23:0] */ + u32 rsv_107 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt120_u; + +/* Define the union csr_fq_cnt121_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt121 : 24; /* [23:0] */ + u32 rsv_108 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt121_u; + +/* Define the union csr_fq_cnt122_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt122 : 24; /* [23:0] */ + u32 rsv_109 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt122_u; + +/* Define the union csr_fq_cnt123_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt123 : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt123_u; + +/* Define the union csr_fq_cnt124_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt124 : 24; /* [23:0] */ + u32 rsv_111 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt124_u; + +/* Define the union csr_fq_cnt125_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt125 : 24; /* [23:0] */ + u32 rsv_112 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt125_u; + +/* Define the union csr_fq_cnt126_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt126 : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt126_u; + +/* Define the union csr_fq_cnt127_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt127 : 24; /* [23:0] */ + u32 rsv_114 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt127_u; + +/* Define the union csr_fq_cnt128_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt128 : 24; /* [23:0] */ + u32 rsv_115 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt128_u; + +/* Define the union csr_fq_cnt129_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt129 : 24; /* [23:0] */ + u32 rsv_116 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt129_u; + +/* Define the union csr_fq_cnt130_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt130 : 24; /* [23:0] */ + u32 rsv_117 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt130_u; + +/* Define the union csr_fq_cnt131_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt131 : 24; /* [23:0] */ + u32 rsv_118 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt131_u; + +/* Define the union csr_fq_cnt132_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt132 : 24; /* [23:0] */ + u32 rsv_119 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt132_u; + +/* Define the union csr_fq_cnt133_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt133 : 24; /* [23:0] */ + u32 rsv_120 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt133_u; + +/* Define the union csr_fq_cnt134_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt134 : 24; /* [23:0] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt134_u; + +/* Define the union csr_fq_cnt135_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt135 : 24; /* [23:0] */ + u32 rsv_122 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt135_u; + +/* Define the union csr_fq_cnt136_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt136 : 24; /* [23:0] */ + u32 rsv_123 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt136_u; + +/* Define the union csr_fq_cnt137_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt137 : 24; /* [23:0] */ + u32 rsv_124 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt137_u; + +/* Define the union csr_fq_cnt138_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt138 : 24; /* [23:0] */ + u32 rsv_125 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt138_u; + +/* Define the union csr_fq_cnt139_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt139 : 24; /* [23:0] */ + u32 rsv_126 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt139_u; + +/* Define the union csr_fq_cnt140_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt140 : 24; /* [23:0] */ + u32 rsv_127 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt140_u; + +/* Define the union csr_fq_cnt141_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt141 : 24; /* [23:0] */ + u32 rsv_128 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt141_u; + +/* Define the union csr_fq_cnt142_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt142 : 24; /* [23:0] */ + u32 rsv_129 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt142_u; + +/* Define the union csr_fq_cnt143_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt143 : 24; /* [23:0] */ + u32 rsv_130 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt143_u; + +/* Define the union csr_fq_cnt144_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt144 : 24; /* [23:0] */ + u32 rsv_131 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt144_u; + +/* Define the union csr_fq_cnt145_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt145 : 24; /* [23:0] */ + u32 rsv_132 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt145_u; + +/* Define the union csr_fq_cnt146_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt146 : 24; /* [23:0] */ + u32 rsv_133 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt146_u; + +/* Define the union csr_fq_cnt147_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt147 : 24; /* [23:0] */ + u32 rsv_134 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt147_u; + +/* Define the union csr_fq_cnt148_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt148 : 24; /* [23:0] */ + u32 rsv_135 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt148_u; + +/* Define the union csr_fq_cnt149_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt149 : 24; /* [23:0] */ + u32 rsv_136 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt149_u; + +/* Define the union csr_fq_cnt150_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt150 : 24; /* [23:0] */ + u32 rsv_137 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt150_u; + +/* Define the union csr_fq_cnt151_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt151 : 24; /* [23:0] */ + u32 rsv_138 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt151_u; + +/* Define the union csr_fq_cnt152_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt152 : 24; /* [23:0] */ + u32 rsv_139 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt152_u; + +/* Define the union csr_fq_cnt153_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt153 : 24; /* [23:0] */ + u32 rsv_140 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt153_u; + +/* Define the union csr_fq_cnt154_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt154 : 24; /* [23:0] */ + u32 rsv_141 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt154_u; + +/* Define the union csr_fq_cnt155_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt155 : 24; /* [23:0] */ + u32 rsv_142 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt155_u; + +/* Define the union csr_fq_cnt156_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt156 : 24; /* [23:0] */ + u32 rsv_143 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt156_u; + +/* Define the union csr_fq_cnt157_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt157 : 24; /* [23:0] */ + u32 rsv_144 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt157_u; + +/* Define the union csr_fq_cnt158_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt158 : 24; /* [23:0] */ + u32 rsv_145 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt158_u; + +/* Define the union csr_fq_cnt159_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt159 : 24; /* [23:0] */ + u32 rsv_146 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt159_u; + +/* Define the union csr_fq_cnt160_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt160 : 24; /* [23:0] */ + u32 rsv_147 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt160_u; + +/* Define the union csr_fq_cnt161_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt161 : 24; /* [23:0] */ + u32 rsv_148 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt161_u; + +/* Define the union csr_fq_cnt162_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt162 : 24; /* [23:0] */ + u32 rsv_149 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt162_u; + +/* Define the union csr_fq_cnt163_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt163 : 24; /* [23:0] */ + u32 rsv_150 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt163_u; + +/* Define the union csr_fq_cnt164_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt164 : 24; /* [23:0] */ + u32 rsv_151 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt164_u; + +/* Define the union csr_fq_cnt165_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt165 : 24; /* [23:0] */ + u32 rsv_152 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt165_u; + +/* Define the union csr_fq_cnt166_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt166 : 24; /* [23:0] */ + u32 rsv_153 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt166_u; + +/* Define the union csr_fq_cnt167_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt167 : 24; /* [23:0] */ + u32 rsv_154 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt167_u; + +/* Define the union csr_fq_cnt168_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt168 : 24; /* [23:0] */ + u32 rsv_155 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt168_u; + +/* Define the union csr_fq_cnt169_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt169 : 24; /* [23:0] */ + u32 rsv_156 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt169_u; + +/* Define the union csr_fq_cnt170_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt170 : 24; /* [23:0] */ + u32 rsv_157 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt170_u; + +/* Define the union csr_fq_cnt171_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt171 : 24; /* [23:0] */ + u32 rsv_158 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt171_u; + +/* Define the union csr_fq_cnt172_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt172 : 24; /* [23:0] */ + u32 rsv_159 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt172_u; + +/* Define the union csr_fq_cnt173_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt173 : 24; /* [23:0] */ + u32 rsv_160 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt173_u; + +/* Define the union csr_fq_cnt174_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt174 : 24; /* [23:0] */ + u32 rsv_161 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt174_u; + +/* Define the union csr_fq_cnt175_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt175 : 24; /* [23:0] */ + u32 rsv_162 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt175_u; + +/* Define the union csr_fq_cnt176_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt176 : 24; /* [23:0] */ + u32 rsv_163 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt176_u; + +/* Define the union csr_fq_cnt177_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt177 : 24; /* [23:0] */ + u32 rsv_164 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt177_u; + +/* Define the union csr_fq_cnt178_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt178 : 24; /* [23:0] */ + u32 rsv_165 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt178_u; + +/* Define the union csr_fq_cnt179_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt179 : 24; /* [23:0] */ + u32 rsv_166 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt179_u; + +/* Define the union csr_fq_cnt180_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt180 : 24; /* [23:0] */ + u32 rsv_167 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt180_u; + +/* Define the union csr_fq_cnt181_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt181 : 24; /* [23:0] */ + u32 rsv_168 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt181_u; + +/* Define the union csr_fq_cnt182_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt182 : 24; /* [23:0] */ + u32 rsv_169 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt182_u; + +/* Define the union csr_fq_cnt183_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt183 : 24; /* [23:0] */ + u32 rsv_170 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt183_u; + +/* Define the union csr_fq_cnt184_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt184 : 24; /* [23:0] */ + u32 rsv_171 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt184_u; + +/* Define the union csr_fq_cnt185_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt185 : 24; /* [23:0] */ + u32 rsv_172 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt185_u; + +/* Define the union csr_fq_cnt186_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt186 : 24; /* [23:0] */ + u32 rsv_173 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt186_u; + +/* Define the union csr_fq_cnt187_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt187 : 24; /* [23:0] */ + u32 rsv_174 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt187_u; + +/* Define the union csr_fq_cnt188_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt188 : 24; /* [23:0] */ + u32 rsv_175 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt188_u; + +/* Define the union csr_fq_cnt189_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt189 : 24; /* [23:0] */ + u32 rsv_176 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt189_u; + +/* Define the union csr_fq_cnt190_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt190 : 24; /* [23:0] */ + u32 rsv_177 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt190_u; + +/* Define the union csr_fq_cnt191_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt191 : 24; /* [23:0] */ + u32 rsv_178 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt191_u; + +/* Define the union csr_fq_cnt192_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt192 : 24; /* [23:0] */ + u32 rsv_179 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt192_u; + +/* Define the union csr_fq_cnt193_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt193 : 24; /* [23:0] */ + u32 rsv_180 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt193_u; + +/* Define the union csr_fq_cnt194_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt194 : 24; /* [23:0] */ + u32 rsv_181 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt194_u; + +/* Define the union csr_fq_cnt195_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt195 : 24; /* [23:0] */ + u32 rsv_182 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt195_u; + +/* Define the union csr_fq_cnt196_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt196 : 24; /* [23:0] */ + u32 rsv_183 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt196_u; + +/* Define the union csr_fq_cnt197_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt197 : 24; /* [23:0] */ + u32 rsv_184 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt197_u; + +/* Define the union csr_fq_cnt198_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt198 : 24; /* [23:0] */ + u32 rsv_185 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt198_u; + +/* Define the union csr_fq_cnt199_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt199 : 24; /* [23:0] */ + u32 rsv_186 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt199_u; + +/* Define the union csr_fq_cnt200_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt200 : 24; /* [23:0] */ + u32 rsv_187 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt200_u; + +/* Define the union csr_fq_cnt201_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt201 : 24; /* [23:0] */ + u32 rsv_188 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt201_u; + +/* Define the union csr_fq_cnt202_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt202 : 24; /* [23:0] */ + u32 rsv_189 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt202_u; + +/* Define the union csr_fq_cnt203_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt203 : 24; /* [23:0] */ + u32 rsv_190 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt203_u; + +/* Define the union csr_fq_cnt204_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt204 : 24; /* [23:0] */ + u32 rsv_191 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt204_u; + +/* Define the union csr_fq_cnt205_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt205 : 24; /* [23:0] */ + u32 rsv_192 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt205_u; + +/* Define the union csr_fq_cnt206_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt206 : 24; /* [23:0] */ + u32 rsv_193 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt206_u; + +/* Define the union csr_fq_cnt207_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt207 : 24; /* [23:0] */ + u32 rsv_194 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt207_u; + +/* Define the union csr_fq_cnt208_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt208 : 24; /* [23:0] */ + u32 rsv_195 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt208_u; + +/* Define the union csr_fq_cnt209_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt209 : 24; /* [23:0] */ + u32 rsv_196 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt209_u; + +/* Define the union csr_fq_cnt210_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt210 : 24; /* [23:0] */ + u32 rsv_197 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt210_u; + +/* Define the union csr_fq_cnt211_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt211 : 24; /* [23:0] */ + u32 rsv_198 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt211_u; + +/* Define the union csr_fq_cnt212_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt212 : 24; /* [23:0] */ + u32 rsv_199 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt212_u; + +/* Define the union csr_fq_cnt213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt213 : 24; /* [23:0] */ + u32 rsv_200 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt213_u; + +/* Define the union csr_fq_cnt214_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt214 : 24; /* [23:0] */ + u32 rsv_201 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt214_u; + +/* Define the union csr_fq_cnt215_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt215 : 24; /* [23:0] */ + u32 rsv_202 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt215_u; + +/* Define the union csr_fq_cnt216_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt216 : 24; /* [23:0] */ + u32 rsv_203 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt216_u; + +/* Define the union csr_fq_cnt217_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt217 : 24; /* [23:0] */ + u32 rsv_204 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt217_u; + +/* Define the union csr_fq_cnt218_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt218 : 24; /* [23:0] */ + u32 rsv_205 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt218_u; + +/* Define the union csr_fq_cnt219_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt219 : 24; /* [23:0] */ + u32 rsv_206 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt219_u; + +/* Define the union csr_fq_cnt220_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt220 : 24; /* [23:0] */ + u32 rsv_207 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt220_u; + +/* Define the union csr_fq_cnt221_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt221 : 24; /* [23:0] */ + u32 rsv_208 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt221_u; + +/* Define the union csr_fq_cnt222_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt222 : 24; /* [23:0] */ + u32 rsv_209 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt222_u; + +/* Define the union csr_fq_cnt223_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt223 : 24; /* [23:0] */ + u32 rsv_210 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt223_u; + +/* Define the union csr_fq_cnt224_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt224 : 24; /* [23:0] */ + u32 rsv_211 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt224_u; + +/* Define the union csr_fq_rxpsh_cid_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_rxpsh_cid_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_rxpsh_cid_ctl_u; + +/* Define the union csr_fq_roce_db_odr_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_roce_db_odr_ctl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_roce_db_odr_ctl1_u; + +/* Define the union csr_fq_roce_db_odr_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_roce_db_odr_ctl2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_roce_db_odr_ctl2_u; + +/* Define the union csr_fq_norm_nic_odr_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_norm_nic_odr_ctl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_norm_nic_odr_ctl1_u; + +/* Define the union csr_fq_norm_nic_odr_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_norm_nic_odr_ctl2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_norm_nic_odr_ctl2_u; + +/* Define the union csr_fq_odr_flit256_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl1_u; + +/* Define the union csr_fq_odr_flit256_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl2_u; + +/* Define the union csr_fq_odr_flit256_ctl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl3_u; + +/* Define the union csr_fq_odr_flit256_ctl4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_flit256_ctl4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_flit256_ctl4_u; + +/* Define the union csr_fq_odr_stype_cid2qid_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_fq_odr_stype_cid2qid_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_odr_stype_cid2qid_en_u; + +/* Define the union csr_fq_cnt225_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt225 : 24; /* [23:0] */ + u32 rsv_212 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt225_u; + +/* Define the union csr_fq_cnt226_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt226 : 24; /* [23:0] */ + u32 rsv_213 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt226_u; + +/* Define the union csr_fq_cnt227_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt227 : 24; /* [23:0] */ + u32 rsv_214 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt227_u; + +/* Define the union csr_fq_cnt228_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt228 : 24; /* [23:0] */ + u32 rsv_215 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt228_u; + +/* Define the union csr_fq_cnt229_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt229 : 24; /* [23:0] */ + u32 rsv_216 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt229_u; + +/* Define the union csr_fq_cnt230_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt230 : 24; /* [23:0] */ + u32 rsv_217 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt230_u; + +/* Define the union csr_fq_cnt231_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt231 : 24; /* [23:0] */ + u32 rsv_218 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt231_u; + +/* Define the union csr_fq_cnt232_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt232 : 24; /* [23:0] */ + u32 rsv_219 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt232_u; + +/* Define the union csr_fq_cnt233_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt233 : 24; /* [23:0] */ + u32 rsv_220 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt233_u; + +/* Define the union csr_fq_cnt234_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt234 : 24; /* [23:0] */ + u32 rsv_221 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt234_u; + +/* Define the union csr_fq_cnt235_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt235 : 24; /* [23:0] */ + u32 rsv_222 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt235_u; + +/* Define the union csr_fq_cnt236_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt236 : 24; /* [23:0] */ + u32 rsv_223 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt236_u; + +/* Define the union csr_fq_cnt237_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt237 : 24; /* [23:0] */ + u32 rsv_224 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt237_u; + +/* Define the union csr_fq_cnt238_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt238 : 24; /* [23:0] */ + u32 rsv_225 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt238_u; + +/* Define the union csr_fq_cnt239_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt239 : 24; /* [23:0] */ + u32 rsv_226 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt239_u; + +/* Define the union csr_fq_cnt240_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt240 : 24; /* [23:0] */ + u32 rsv_227 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt240_u; + +/* Define the union csr_fq_cnt241_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fq_cnt241 : 24; /* [23:0] */ + u32 rsv_228 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fq_cnt241_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_fq_mode_reg_u fq_mode_reg; /* 0 */ + volatile csr_fq_initctab_start_u fq_initctab_start; /* 4 */ + volatile csr_fq_initctab_st_u fq_initctab_st; /* 8 */ + volatile csr_fq_init_logic_st_u fq_init_logic_st; /* C */ + volatile csr_fq_int_vector_u fq_int_vector; /* 10 */ + volatile csr_fq_int_u fq_int; /* 14 */ + volatile csr_fq_int_mask_u fq_int_mask; /* 18 */ + volatile csr_fq_int_mem_err_2b_u fq_int_mem_err_2b; /* 1C */ + volatile csr_fq_int_oeid_aged_err_u fq_int_oeid_aged_err; /* 20 */ + volatile csr_fq_int_scan_err_u fq_int_scan_err; /* 24 */ + volatile csr_fq_int_fcmd_err_u fq_int_fcmd_err; /* 28 */ + volatile csr_fq_int_dsp_err_u fq_int_dsp_err; /* 2C */ + volatile csr_fq_int_pfh_err_u fq_int_pfh_err; /* 30 */ + volatile csr_fq_int_dbe_err_u fq_int_dbe_err; /* 34 */ + volatile csr_fq_int_qrsc_err_u fq_int_qrsc_err; /* 38 */ + volatile csr_fq_int_buf_uf_err_u fq_int_buf_uf_err; /* 3C */ + volatile csr_fq_int_fifo0_err_u fq_int_fifo0_err; /* 40 */ + volatile csr_fq_indrect_ctrl_u fq_indrect_ctrl; /* 44 */ + volatile csr_fq_indrect_timeout_u fq_indrect_timeout; /* 48 */ + volatile csr_fq_indrect_dat0_u fq_indrect_dat0; /* 4C */ + volatile csr_fq_indrect_dat1_u fq_indrect_dat1; /* 50 */ + volatile csr_fq_qcntx_mode_u fq_qcntx_mode; /* 54 */ + volatile csr_fq_age_period_reg_u fq_age_period_reg; /* 58 */ + volatile csr_stffq_dbe_hw_pfh_cfg_u stffq_dbe_hw_pfh_cfg; /* 5C */ + volatile csr_fq_tmr_st_u fq_tmr_st; /* 60 */ + volatile csr_fq_cpb_cfg_u fq_cpb_cfg; /* 64 */ + volatile csr_fq_crdt_2tlsmf_st_u fq_crdt_2tlsmf_st; /* 68 */ + volatile csr_fq_crdt_2tlsmf_reg_u fq_crdt_2tlsmf_reg; /* 6C */ + volatile csr_fq_cnt_ctl_u fq_cnt_ctl; /* 70 */ + volatile csr_fq_cnt0_u fq_cnt0; /* 74 */ + volatile csr_fq_cnt1_u fq_cnt1; /* 78 */ + volatile csr_fq_cnt2_u fq_cnt2; /* 7C */ + volatile csr_fq_cnt3_u fq_cnt3; /* 80 */ + volatile csr_fq_cnt4_u fq_cnt4; /* 84 */ + volatile csr_fq_snapshot_ctl_u fq_snapshot_ctl; /* 88 */ + volatile csr_fq_snapshot_st_u fq_snapshot_st; /* 8C */ + volatile csr_fq_dbe_hw_wqe_en_u fq_dbe_hw_wqe_en; /* 90 */ + volatile csr_fq_dbe_hw_wqe_cfg_u fq_dbe_hw_wqe_cfg; /* 94 */ + volatile csr_fq_fifo_gap_cfg_u fq_fifo_gap_cfg; /* 98 */ + volatile csr_fq_his_fifo_cnt0_u fq_his_fifo_cnt0; /* 9C */ + volatile csr_fq_his_fifo_cnt1_u fq_his_fifo_cnt1; /* A0 */ + volatile csr_fq_fifo_st_u fq_fifo_st; /* A4 */ + volatile csr_fq_his_fifo_st_u fq_his_fifo_st; /* A8 */ + volatile csr_fq_mem_ctrl_u fq_mem_ctrl; /* AC */ + volatile csr_fq_cfg_ep2host_u fq_cfg_ep2host; /* B0 */ + volatile csr_fq_pcar_cfg_u fq_pcar_cfg; /* B4 */ + volatile csr_fq_cnt5_u fq_cnt5; /* B8 */ + volatile csr_fq_mod_reg1_u fq_mod_reg1; /* BC */ + volatile csr_fq_inner_bp_st_u fq_inner_bp_st; /* C0 */ + volatile csr_fq_inner_mon_st_u fq_inner_mon_st; /* C4 */ + volatile csr_fq_cnt6_u fq_cnt6; /* C8 */ + volatile csr_fq_cnt_ctl1_u fq_cnt_ctl1; /* CC */ + volatile csr_fq_cnt7_u fq_cnt7; /* D0 */ + volatile csr_fq_cnt8_u fq_cnt8; /* D4 */ + volatile csr_fq_cnt9_u fq_cnt9; /* D8 */ + volatile csr_fq_cnt10_u fq_cnt10; /* DC */ + volatile csr_fq_cnt11_u fq_cnt11; /* E0 */ + volatile csr_fq_cnt12_u fq_cnt12; /* E4 */ + volatile csr_fq_cnt13_u fq_cnt13; /* E8 */ + volatile csr_fq_cnt14_u fq_cnt14; /* EC */ + volatile csr_fq_cnt15_u fq_cnt15; /* F0 */ + volatile csr_fq_cnt16_u fq_cnt16; /* F4 */ + volatile csr_fq_int_mem_err_1b_u fq_int_mem_err_1b; /* F8 */ + volatile csr_cfg_styp_th_fc_en_u cfg_styp_th_fc_en; /* FC */ + volatile csr_cfg_zero_esch_len_u cfg_zero_esch_len; /* 100 */ + volatile csr_cfg_fq_bubble_ctl_u cfg_fq_bubble_ctl; /* 104 */ + volatile csr_cfg_l2dcache_bubble_ctl_u cfg_l2dcache_bubble_ctl; /* 108 */ + volatile csr_fq_def_fq_ctl_u fq_def_fq_ctl; /* 10C */ + volatile csr_fq_smf_ldbctl_u fq_smf_ldbctl; /* 110 */ + volatile csr_fq_cfg_ep2host_h2_u fq_cfg_ep2host_h2; /* 114 */ + volatile csr_fq_cfg_prefetch_ctl_u fq_cfg_prefetch_ctl; /* 118 */ + volatile csr_fq_latency_cfg_u fq_latency_cfg; /* 11C */ + volatile csr_fq_latency_sta_u fq_latency_sta; /* 120 */ + volatile csr_fq_sample_tmr_u fq_sample_tmr; /* 124 */ + volatile csr_fq_cfg_fake_vf_ctl_u fq_cfg_fake_vf_ctl; /* 128 */ + volatile csr_fq_cfg_bps_dly_ctl_u fq_cfg_bps_dly_ctl; /* 12C */ + volatile csr_fq_cfg_otsd_base_ctl_u fq_cfg_otsd_base_ctl; /* 130 */ + volatile csr_fq_cnt_ctl2_u fq_cnt_ctl2; /* 134 */ + volatile csr_fq_cnt17_u fq_cnt17; /* 138 */ + volatile csr_fq_cnt18_u fq_cnt18; /* 13C */ + volatile csr_fq_cnt19_u fq_cnt19; /* 140 */ + volatile csr_fq_cnt20_u fq_cnt20; /* 144 */ + volatile csr_fq_cnt21_u fq_cnt21; /* 148 */ + volatile csr_fq_cnt22_u fq_cnt22; /* 14C */ + volatile csr_fq_cnt23_u fq_cnt23; /* 150 */ + volatile csr_fq_cnt24_u fq_cnt24; /* 154 */ + volatile csr_fq_cnt25_u fq_cnt25; /* 158 */ + volatile csr_fq_cnt26_u fq_cnt26; /* 15C */ + volatile csr_fq_cnt_ctl3_u fq_cnt_ctl3; /* 160 */ + volatile csr_fq_cnt27_u fq_cnt27; /* 164 */ + volatile csr_fq_cnt28_u fq_cnt28; /* 168 */ + volatile csr_fq_cnt29_u fq_cnt29; /* 16C */ + volatile csr_fq_cnt30_u fq_cnt30; /* 170 */ + volatile csr_fq_cnt31_u fq_cnt31; /* 174 */ + volatile csr_fq_cnt32_u fq_cnt32; /* 178 */ + volatile csr_fq_cnt33_u fq_cnt33; /* 17C */ + volatile csr_fq_cnt34_u fq_cnt34; /* 180 */ + volatile csr_fq_cnt35_u fq_cnt35; /* 184 */ + volatile csr_fq_cnt36_u fq_cnt36; /* 188 */ + volatile csr_fq_cnt_ctl4_u fq_cnt_ctl4; /* 18C */ + volatile csr_fq_cnt37_u fq_cnt37; /* 190 */ + volatile csr_fq_cnt38_u fq_cnt38; /* 194 */ + volatile csr_fq_cnt39_u fq_cnt39; /* 198 */ + volatile csr_fq_cnt40_u fq_cnt40; /* 19C */ + volatile csr_fq_cnt41_u fq_cnt41; /* 1A0 */ + volatile csr_fq_cnt42_u fq_cnt42; /* 1A4 */ + volatile csr_fq_cnt43_u fq_cnt43; /* 1A8 */ + volatile csr_fq_cnt44_u fq_cnt44; /* 1AC */ + volatile csr_fq_cnt45_u fq_cnt45; /* 1B0 */ + volatile csr_fq_cnt46_u fq_cnt46; /* 1B4 */ + volatile csr_fq_qu2smf_tmr_dly_u fq_qu2smf_tmr_dly; /* 1B8 */ + volatile csr_fq_magic_box_ctl_u fq_magic_box_ctl; /* 1BC */ + volatile csr_fq_mgbx_srv2hash_u fq_mgbx_srv2hash; /* 1C0 */ + volatile csr_fq_inner_mon_st1_u fq_inner_mon_st1; /* 1C4 */ + volatile csr_fq_inner_mon_st2_u fq_inner_mon_st2; /* 1C8 */ + volatile csr_fq_inner_mon_st3_u fq_inner_mon_st3; /* 1CC */ + volatile csr_fq_inner_mon_st4_u fq_inner_mon_st4; /* 1D0 */ + volatile csr_fq_inner_mon_st5_u fq_inner_mon_st5; /* 1D4 */ + volatile csr_fq_inner_mon_st6_u fq_inner_mon_st6; /* 1D8 */ + volatile csr_fq_inner_mon_st7_u fq_inner_mon_st7; /* 1DC */ + volatile csr_fq_inner_mon_st8_u fq_inner_mon_st8; /* 1E0 */ + volatile csr_fq_inner_mon_st9_u fq_inner_mon_st9; /* 1E4 */ + volatile csr_fq_inner_mon_st10_u fq_inner_mon_st10; /* 1E8 */ + volatile csr_fq_inner_mon_st11_u fq_inner_mon_st11; /* 1EC */ + volatile csr_fq_inner_mon_st12_u fq_inner_mon_st12; /* 1F0 */ + volatile csr_fq_inner_mon_st13_u fq_inner_mon_st13; /* 1F4 */ + volatile csr_fq_inner_mon_st14_u fq_inner_mon_st14; /* 1F8 */ + volatile csr_fq_inner_mon_st15_u fq_inner_mon_st15; /* 1FC */ + volatile csr_fq_inner_mon_st16_u fq_inner_mon_st16; /* 200 */ + volatile csr_fq_inner_mon_st17_u fq_inner_mon_st17; /* 204 */ + volatile csr_fq_inner_mon_st18_u fq_inner_mon_st18; /* 208 */ + volatile csr_fq_inner_mon_st19_u fq_inner_mon_st19; /* 20C */ + volatile csr_fq_inner_mon_st20_u fq_inner_mon_st20; /* 210 */ + volatile csr_fq_inner_mon_st21_u fq_inner_mon_st21; /* 214 */ + volatile csr_fq_inner_mon_st22_u fq_inner_mon_st22; /* 218 */ + volatile csr_fq_inner_mon_st23_u fq_inner_mon_st23; /* 21C */ + volatile csr_fq_inner_mon_st24_u fq_inner_mon_st24; /* 220 */ + volatile csr_fq_inner_mon_st25_u fq_inner_mon_st25; /* 224 */ + volatile csr_fq_inner_mon_st26_u fq_inner_mon_st26; /* 228 */ + volatile csr_fq_inner_mon_st27_u fq_inner_mon_st27; /* 22C */ + volatile csr_fq_inner_mon_st28_u fq_inner_mon_st28; /* 230 */ + volatile csr_fq_inner_mon_st29_u fq_inner_mon_st29; /* 234 */ + volatile csr_fq_inner_mon_st30_u fq_inner_mon_st30; /* 238 */ + volatile csr_fq_inner_mon_st31_u fq_inner_mon_st31; /* 23C */ + volatile csr_fq_inner_mon_st32_u fq_inner_mon_st32; /* 240 */ + volatile csr_fq_inner_mon_st33_u fq_inner_mon_st33; /* 244 */ + volatile csr_fq_inner_mon_st34_u fq_inner_mon_st34; /* 248 */ + volatile csr_fq_inner_mon_st35_u fq_inner_mon_st35; /* 24C */ + volatile csr_fq_inner_mon_st36_u fq_inner_mon_st36; /* 250 */ + volatile csr_fq_inner_mon_st37_u fq_inner_mon_st37; /* 254 */ + volatile csr_fq_inner_mon_st38_u fq_inner_mon_st38; /* 258 */ + volatile csr_fq_inner_mon_st39_u fq_inner_mon_st39; /* 25C */ + volatile csr_fq_inner_mon_st40_u fq_inner_mon_st40; /* 260 */ + volatile csr_fq_inner_mon_st41_u fq_inner_mon_st41; /* 264 */ + volatile csr_fq_inner_mon_st42_u fq_inner_mon_st42; /* 26C */ + volatile csr_fq_inner_mon_st43_u fq_inner_mon_st43; /* 270 */ + volatile csr_fq_inner_mon_st44_u fq_inner_mon_st44; /* 274 */ + volatile csr_fq_inner_mon_st45_u fq_inner_mon_st45; /* 278 */ + volatile csr_fq_inner_mon_st46_u fq_inner_mon_st46; /* 27C */ + volatile csr_fq_inner_mon_st47_u fq_inner_mon_st47; /* 280 */ + volatile csr_fq_inner_mon_st48_u fq_inner_mon_st48; /* 284 */ + volatile csr_fq_cnt47_u fq_cnt47; /* 288 */ + volatile csr_fq_rou_rqst_fifo0_u fq_rou_rqst_fifo0; /* 28C */ + volatile csr_fq_rou_rsp_fifo0_u fq_rou_rsp_fifo0; /* 290 */ + volatile csr_fq_rou_rsp_fifo1_u fq_rou_rsp_fifo1; /* 298 */ + volatile csr_fq_rou_tmrodr_fifo0_u fq_rou_tmrodr_fifo0; /* 29C */ + volatile csr_fq_rou_tmrodr_fifo1_u fq_rou_tmrodr_fifo1; /* 2A0 */ + volatile csr_fq_rou_tmrodr_fifo2_u fq_rou_tmrodr_fifo2; /* 2A4 */ + volatile csr_fq_rou_tmrodr_fifo3_u fq_rou_tmrodr_fifo3; /* 2A8 */ + volatile csr_fq_rin_rqst_fifo_u fq_rin_rqst_fifo; /* 2BC */ + volatile csr_fq_rin_rsp_fifo_u fq_rin_rsp_fifo; /* 2C0 */ + volatile csr_fq_smf_rsp_fifo0_u fq_smf_rsp_fifo0; /* 2D4 */ + volatile csr_fq_smf_rsp_fifo1_u fq_smf_rsp_fifo1; /* 2D8 */ + volatile csr_fq_tl0_cmd_fifo0_u fq_tl0_cmd_fifo0; /* 2DC */ + volatile csr_fq_tl0_extcmd_fifo0_u fq_tl0_extcmd_fifo0; /* 2E0 */ + volatile csr_fq_tl1_cmd_fifo1_u fq_tl1_cmd_fifo1; /* 2E4 */ + volatile csr_fq_tl1_extcmd_fifo0_u fq_tl1_extcmd_fifo0; /* 2E8 */ + volatile csr_fq_fq2oq_fcnp_fifo_u fq_fq2oq_fcnp_fifo; /* 2EC */ + volatile csr_fq_oq2fq_fcnp_fifo_u fq_oq2fq_fcnp_fifo; /* 2F0 */ + volatile csr_fq_tmr_rsp_fifo0_u fq_tmr_rsp_fifo0; /* 2F4 */ + volatile csr_fq_tmr_rsp_fifo1_u fq_tmr_rsp_fifo1; /* 2F8 */ + volatile csr_fq_tmr_rsp_fifo2_u fq_tmr_rsp_fifo2; /* 2FC */ + volatile csr_fq_tmr_rsp_fifo3_u fq_tmr_rsp_fifo3; /* 300 */ + volatile csr_fq_tmr_rsp_fifo4_u fq_tmr_rsp_fifo4; /* 304 */ + volatile csr_fq_tmr_rsp_fifo5_u fq_tmr_rsp_fifo5; /* 308 */ + volatile csr_fq_tmr_rsp_fifo6_u fq_tmr_rsp_fifo6; /* 30C */ + volatile csr_fq_tmr_rsp_fifo7_u fq_tmr_rsp_fifo7; /* 310 */ + volatile csr_fq_tmr_rsp_fifo8_u fq_tmr_rsp_fifo8; /* 314 */ + volatile csr_fq_tmr_rsp_fifo9_u fq_tmr_rsp_fifo9; /* 318 */ + volatile csr_fq_tmr_rsp_fifo10_u fq_tmr_rsp_fifo10; /* 31C */ + volatile csr_fq_tmr_rsp_fifo11_u fq_tmr_rsp_fifo11; /* 320 */ + volatile csr_fq_tmr_rsp_fifo12_u fq_tmr_rsp_fifo12; /* 324 */ + volatile csr_fq_tmr_rsp_fifo13_u fq_tmr_rsp_fifo13; /* 328 */ + volatile csr_fq_tmr_rsp_fifo14_u fq_tmr_rsp_fifo14; /* 32C */ + volatile csr_fq_tmr_rsp_fifo15_u fq_tmr_rsp_fifo15; /* 330 */ + volatile csr_fq_int_rin_rqst_err_u fq_int_rin_rqst_err; /* 334 */ + volatile csr_fq_int_rin_rsp_err_u fq_int_rin_rsp_err; /* 338 */ + volatile csr_fq_int_rin_trsp_err_u fq_int_rin_trsp_err; /* 33C */ + volatile csr_fq_int_fifo1_err_u fq_int_fifo1_err; /* 340 */ + volatile csr_fq_int_fifo2_err_u fq_int_fifo2_err; /* 344 */ + volatile csr_fq_cnt48_u fq_cnt48; /* 348 */ + volatile csr_fq_cfg_stg_qp_push0_u fq_cfg_stg_qp_push0; /* 34C */ + volatile csr_fq_cfg_stg_qp_push1_u fq_cfg_stg_qp_push1; /* 350 */ + volatile csr_fq_cfg_stg_qp_push2_u fq_cfg_stg_qp_push2; /* 354 */ + volatile csr_fq_dbe_hw_wqe_en1_u fq_dbe_hw_wqe_en1; /* 358 */ + volatile csr_fq_dbe_hw_wqe_en2_u fq_dbe_hw_wqe_en2; /* 35C */ + volatile csr_fq_dbe_hw_wqe_en3_u fq_dbe_hw_wqe_en3; /* 360 */ + volatile csr_fq_dbe_hw_wqe_en4_u fq_dbe_hw_wqe_en4; /* 364 */ + volatile csr_fq_dbe_hw_wqe_en5_u fq_dbe_hw_wqe_en5; /* 368 */ + volatile csr_fq_dbe_hw_wqe_en6_u fq_dbe_hw_wqe_en6; /* 36C */ + volatile csr_fq_dbe_hw_wqe_en7_u fq_dbe_hw_wqe_en7; /* 370 */ + volatile csr_fq_dbe_hw_wqe_en8_u fq_dbe_hw_wqe_en8; /* 374 */ + volatile csr_fq_dbe_hw_wqe_en9_u fq_dbe_hw_wqe_en9; /* 378 */ + volatile csr_fq_dbe_hw_wqe_en10_u fq_dbe_hw_wqe_en10; /* 37C */ + volatile csr_fq_dbe_hw_wqe_en11_u fq_dbe_hw_wqe_en11; /* 380 */ + volatile csr_fq_dbe_hw_wqe_en12_u fq_dbe_hw_wqe_en12; /* 384 */ + volatile csr_fq_dbe_hw_wqe_en13_u fq_dbe_hw_wqe_en13; /* 388 */ + volatile csr_fq_dbe_hw_wqe_en14_u fq_dbe_hw_wqe_en14; /* 38C */ + volatile csr_fq_dbe_hw_wqe_en15_u fq_dbe_hw_wqe_en15; /* 390 */ + volatile csr_fq_cnt49_u fq_cnt49; /* 394 */ + volatile csr_fq_cnt50_u fq_cnt50; /* 398 */ + volatile csr_fq_cnt51_u fq_cnt51; /* 39C */ + volatile csr_fq_cnt52_u fq_cnt52; /* 3A0 */ + volatile csr_fq_cnt53_u fq_cnt53; /* 3A4 */ + volatile csr_fq_cnt54_u fq_cnt54; /* 3A8 */ + volatile csr_fq_cnt55_u fq_cnt55; /* 3AC */ + volatile csr_fq_cnt56_u fq_cnt56; /* 3B0 */ + volatile csr_fq_cnt57_u fq_cnt57; /* 3B4 */ + volatile csr_fq_cnt58_u fq_cnt58; /* 3B8 */ + volatile csr_fq_cnt59_u fq_cnt59; /* 3BC */ + volatile csr_fq_cnt60_u fq_cnt60; /* 3C0 */ + volatile csr_fq_cnt61_u fq_cnt61; /* 3C4 */ + volatile csr_fq_cnt62_u fq_cnt62; /* 3C8 */ + volatile csr_fq_cnt63_u fq_cnt63; /* 3CC */ + volatile csr_fq_cnt64_u fq_cnt64; /* 3D0 */ + volatile csr_fq_cnt65_u fq_cnt65; /* 3D4 */ + volatile csr_fq_cnt66_u fq_cnt66; /* 3D8 */ + volatile csr_fq_cnt67_u fq_cnt67; /* 3DC */ + volatile csr_fq_cnt68_u fq_cnt68; /* 3E0 */ + volatile csr_fq_cnt69_u fq_cnt69; /* 3E4 */ + volatile csr_fq_cnt70_u fq_cnt70; /* 3E8 */ + volatile csr_fq_cnt71_u fq_cnt71; /* 3EC */ + volatile csr_fq_cnt72_u fq_cnt72; /* 3F0 */ + volatile csr_fq_cnt73_u fq_cnt73; /* 3F4 */ + volatile csr_fq_cnt74_u fq_cnt74; /* 3F8 */ + volatile csr_fq_cnt75_u fq_cnt75; /* 3FC */ + volatile csr_fq_cnt76_u fq_cnt76; /* 400 */ + volatile csr_fq_cnt77_u fq_cnt77; /* 404 */ + volatile csr_fq_cnt78_u fq_cnt78; /* 408 */ + volatile csr_fq_cnt79_u fq_cnt79; /* 40C */ + volatile csr_fq_cnt80_u fq_cnt80; /* 410 */ + volatile csr_fq_cnt81_u fq_cnt81; /* 414 */ + volatile csr_fq_cnt82_u fq_cnt82; /* 418 */ + volatile csr_fq_cnt83_u fq_cnt83; /* 41C */ + volatile csr_fq_cnt84_u fq_cnt84; /* 420 */ + volatile csr_fq_cnt85_u fq_cnt85; /* 424 */ + volatile csr_fq_cnt86_u fq_cnt86; /* 428 */ + volatile csr_fq_cnt87_u fq_cnt87; /* 42C */ + volatile csr_fq_cnt88_u fq_cnt88; /* 430 */ + volatile csr_fq_cnt89_u fq_cnt89; /* 434 */ + volatile csr_fq_cnt90_u fq_cnt90; /* 438 */ + volatile csr_fq_cnt91_u fq_cnt91; /* 43C */ + volatile csr_fq_cnt92_u fq_cnt92; /* 440 */ + volatile csr_fq_cnt93_u fq_cnt93; /* 444 */ + volatile csr_fq_cnt94_u fq_cnt94; /* 448 */ + volatile csr_fq_cnt95_u fq_cnt95; /* 44C */ + volatile csr_fq_cnt96_u fq_cnt96; /* 450 */ + volatile csr_fq_cnt97_u fq_cnt97; /* 454 */ + volatile csr_fq_cnt98_u fq_cnt98; /* 458 */ + volatile csr_fq_cnt99_u fq_cnt99; /* 45C */ + volatile csr_fq_cnt100_u fq_cnt100; /* 460 */ + volatile csr_fq_cnt101_u fq_cnt101; /* 464 */ + volatile csr_fq_cnt102_u fq_cnt102; /* 468 */ + volatile csr_fq_cnt103_u fq_cnt103; /* 46C */ + volatile csr_fq_cnt104_u fq_cnt104; /* 470 */ + volatile csr_fq_cnt105_u fq_cnt105; /* 474 */ + volatile csr_fq_cnt106_u fq_cnt106; /* 478 */ + volatile csr_fq_cnt107_u fq_cnt107; /* 47C */ + volatile csr_fq_cnt108_u fq_cnt108; /* 480 */ + volatile csr_fq_cnt109_u fq_cnt109; /* 484 */ + volatile csr_fq_cnt110_u fq_cnt110; /* 488 */ + volatile csr_fq_cnt111_u fq_cnt111; /* 48C */ + volatile csr_fq_cnt112_u fq_cnt112; /* 490 */ + volatile csr_fq_cnt113_u fq_cnt113; /* 494 */ + volatile csr_fq_cnt114_u fq_cnt114; /* 498 */ + volatile csr_fq_cnt115_u fq_cnt115; /* 49C */ + volatile csr_fq_cnt116_u fq_cnt116; /* 4A0 */ + volatile csr_fq_cnt117_u fq_cnt117; /* 4A4 */ + volatile csr_fq_cnt118_u fq_cnt118; /* 4A8 */ + volatile csr_fq_cnt119_u fq_cnt119; /* 4AC */ + volatile csr_fq_cnt120_u fq_cnt120; /* 4B0 */ + volatile csr_fq_cnt121_u fq_cnt121; /* 4B4 */ + volatile csr_fq_cnt122_u fq_cnt122; /* 4B8 */ + volatile csr_fq_cnt123_u fq_cnt123; /* 4BC */ + volatile csr_fq_cnt124_u fq_cnt124; /* 4C0 */ + volatile csr_fq_cnt125_u fq_cnt125; /* 4C4 */ + volatile csr_fq_cnt126_u fq_cnt126; /* 4C8 */ + volatile csr_fq_cnt127_u fq_cnt127; /* 4CC */ + volatile csr_fq_cnt128_u fq_cnt128; /* 4D0 */ + volatile csr_fq_cnt129_u fq_cnt129; /* 4D4 */ + volatile csr_fq_cnt130_u fq_cnt130; /* 4D8 */ + volatile csr_fq_cnt131_u fq_cnt131; /* 4DC */ + volatile csr_fq_cnt132_u fq_cnt132; /* 4E0 */ + volatile csr_fq_cnt133_u fq_cnt133; /* 4E4 */ + volatile csr_fq_cnt134_u fq_cnt134; /* 4E8 */ + volatile csr_fq_cnt135_u fq_cnt135; /* 4EC */ + volatile csr_fq_cnt136_u fq_cnt136; /* 4F0 */ + volatile csr_fq_cnt137_u fq_cnt137; /* 4F4 */ + volatile csr_fq_cnt138_u fq_cnt138; /* 4F8 */ + volatile csr_fq_cnt139_u fq_cnt139; /* 4FC */ + volatile csr_fq_cnt140_u fq_cnt140; /* 500 */ + volatile csr_fq_cnt141_u fq_cnt141; /* 504 */ + volatile csr_fq_cnt142_u fq_cnt142; /* 508 */ + volatile csr_fq_cnt143_u fq_cnt143; /* 50C */ + volatile csr_fq_cnt144_u fq_cnt144; /* 510 */ + volatile csr_fq_cnt145_u fq_cnt145; /* 514 */ + volatile csr_fq_cnt146_u fq_cnt146; /* 518 */ + volatile csr_fq_cnt147_u fq_cnt147; /* 51C */ + volatile csr_fq_cnt148_u fq_cnt148; /* 520 */ + volatile csr_fq_cnt149_u fq_cnt149; /* 524 */ + volatile csr_fq_cnt150_u fq_cnt150; /* 528 */ + volatile csr_fq_cnt151_u fq_cnt151; /* 52C */ + volatile csr_fq_cnt152_u fq_cnt152; /* 530 */ + volatile csr_fq_cnt153_u fq_cnt153; /* 534 */ + volatile csr_fq_cnt154_u fq_cnt154; /* 538 */ + volatile csr_fq_cnt155_u fq_cnt155; /* 53C */ + volatile csr_fq_cnt156_u fq_cnt156; /* 540 */ + volatile csr_fq_cnt157_u fq_cnt157; /* 544 */ + volatile csr_fq_cnt158_u fq_cnt158; /* 548 */ + volatile csr_fq_cnt159_u fq_cnt159; /* 54C */ + volatile csr_fq_cnt160_u fq_cnt160; /* 550 */ + volatile csr_fq_cnt161_u fq_cnt161; /* 554 */ + volatile csr_fq_cnt162_u fq_cnt162; /* 558 */ + volatile csr_fq_cnt163_u fq_cnt163; /* 55C */ + volatile csr_fq_cnt164_u fq_cnt164; /* 560 */ + volatile csr_fq_cnt165_u fq_cnt165; /* 564 */ + volatile csr_fq_cnt166_u fq_cnt166; /* 568 */ + volatile csr_fq_cnt167_u fq_cnt167; /* 56C */ + volatile csr_fq_cnt168_u fq_cnt168; /* 570 */ + volatile csr_fq_cnt169_u fq_cnt169; /* 574 */ + volatile csr_fq_cnt170_u fq_cnt170; /* 578 */ + volatile csr_fq_cnt171_u fq_cnt171; /* 57C */ + volatile csr_fq_cnt172_u fq_cnt172; /* 580 */ + volatile csr_fq_cnt173_u fq_cnt173; /* 584 */ + volatile csr_fq_cnt174_u fq_cnt174; /* 588 */ + volatile csr_fq_cnt175_u fq_cnt175; /* 58C */ + volatile csr_fq_cnt176_u fq_cnt176; /* 590 */ + volatile csr_fq_cnt177_u fq_cnt177; /* 594 */ + volatile csr_fq_cnt178_u fq_cnt178; /* 598 */ + volatile csr_fq_cnt179_u fq_cnt179; /* 59C */ + volatile csr_fq_cnt180_u fq_cnt180; /* 5A0 */ + volatile csr_fq_cnt181_u fq_cnt181; /* 5A4 */ + volatile csr_fq_cnt182_u fq_cnt182; /* 5A8 */ + volatile csr_fq_cnt183_u fq_cnt183; /* 5AC */ + volatile csr_fq_cnt184_u fq_cnt184; /* 5B0 */ + volatile csr_fq_cnt185_u fq_cnt185; /* 5B4 */ + volatile csr_fq_cnt186_u fq_cnt186; /* 5B8 */ + volatile csr_fq_cnt187_u fq_cnt187; /* 5BC */ + volatile csr_fq_cnt188_u fq_cnt188; /* 5C0 */ + volatile csr_fq_cnt189_u fq_cnt189; /* 5C4 */ + volatile csr_fq_cnt190_u fq_cnt190; /* 5C8 */ + volatile csr_fq_cnt191_u fq_cnt191; /* 5CC */ + volatile csr_fq_cnt192_u fq_cnt192; /* 5D0 */ + volatile csr_fq_cnt193_u fq_cnt193; /* 5D4 */ + volatile csr_fq_cnt194_u fq_cnt194; /* 5D8 */ + volatile csr_fq_cnt195_u fq_cnt195; /* 5DC */ + volatile csr_fq_cnt196_u fq_cnt196; /* 5E0 */ + volatile csr_fq_cnt197_u fq_cnt197; /* 5E4 */ + volatile csr_fq_cnt198_u fq_cnt198; /* 5E8 */ + volatile csr_fq_cnt199_u fq_cnt199; /* 5EC */ + volatile csr_fq_cnt200_u fq_cnt200; /* 5F0 */ + volatile csr_fq_cnt201_u fq_cnt201; /* 5F4 */ + volatile csr_fq_cnt202_u fq_cnt202; /* 5F8 */ + volatile csr_fq_cnt203_u fq_cnt203; /* 5FC */ + volatile csr_fq_cnt204_u fq_cnt204; /* 600 */ + volatile csr_fq_cnt205_u fq_cnt205; /* 604 */ + volatile csr_fq_cnt206_u fq_cnt206; /* 608 */ + volatile csr_fq_cnt207_u fq_cnt207; /* 60C */ + volatile csr_fq_cnt208_u fq_cnt208; /* 610 */ + volatile csr_fq_cnt209_u fq_cnt209; /* 614 */ + volatile csr_fq_cnt210_u fq_cnt210; /* 618 */ + volatile csr_fq_cnt211_u fq_cnt211; /* 61C */ + volatile csr_fq_cnt212_u fq_cnt212; /* 620 */ + volatile csr_fq_cnt213_u fq_cnt213; /* 624 */ + volatile csr_fq_cnt214_u fq_cnt214; /* 628 */ + volatile csr_fq_cnt215_u fq_cnt215; /* 62C */ + volatile csr_fq_cnt216_u fq_cnt216; /* 630 */ + volatile csr_fq_cnt217_u fq_cnt217; /* 634 */ + volatile csr_fq_cnt218_u fq_cnt218; /* 638 */ + volatile csr_fq_cnt219_u fq_cnt219; /* 63C */ + volatile csr_fq_cnt220_u fq_cnt220; /* 640 */ + volatile csr_fq_cnt221_u fq_cnt221; /* 644 */ + volatile csr_fq_cnt222_u fq_cnt222; /* 648 */ + volatile csr_fq_cnt223_u fq_cnt223; /* 64C */ + volatile csr_fq_cnt224_u fq_cnt224; /* 650 */ + volatile csr_fq_rxpsh_cid_ctl_u fq_rxpsh_cid_ctl; /* 654 */ + volatile csr_fq_roce_db_odr_ctl1_u fq_roce_db_odr_ctl1; /* 658 */ + volatile csr_fq_roce_db_odr_ctl2_u fq_roce_db_odr_ctl2; /* 65C */ + volatile csr_fq_norm_nic_odr_ctl1_u fq_norm_nic_odr_ctl1; /* 660 */ + volatile csr_fq_norm_nic_odr_ctl2_u fq_norm_nic_odr_ctl2; /* 664 */ + volatile csr_fq_odr_flit256_ctl1_u fq_odr_flit256_ctl1; /* 668 */ + volatile csr_fq_odr_flit256_ctl2_u fq_odr_flit256_ctl2; /* 66C */ + volatile csr_fq_odr_flit256_ctl3_u fq_odr_flit256_ctl3; /* 670 */ + volatile csr_fq_odr_flit256_ctl4_u fq_odr_flit256_ctl4; /* 674 */ + volatile csr_fq_odr_stype_cid2qid_en_u fq_odr_stype_cid2qid_en; /* 678 */ + volatile csr_fq_cnt225_u fq_cnt225; /* 67C */ + volatile csr_fq_cnt226_u fq_cnt226; /* 680 */ + volatile csr_fq_cnt227_u fq_cnt227; /* 684 */ + volatile csr_fq_cnt228_u fq_cnt228; /* 688 */ + volatile csr_fq_cnt229_u fq_cnt229; /* 68C */ + volatile csr_fq_cnt230_u fq_cnt230; /* 690 */ + volatile csr_fq_cnt231_u fq_cnt231; /* 694 */ + volatile csr_fq_cnt232_u fq_cnt232; /* 698 */ + volatile csr_fq_cnt233_u fq_cnt233; /* 69C */ + volatile csr_fq_cnt234_u fq_cnt234; /* 6A0 */ + volatile csr_fq_cnt235_u fq_cnt235; /* 6A4 */ + volatile csr_fq_cnt236_u fq_cnt236; /* 6A8 */ + volatile csr_fq_cnt237_u fq_cnt237; /* 6AC */ + volatile csr_fq_cnt238_u fq_cnt238; /* 6B0 */ + volatile csr_fq_cnt239_u fq_cnt239; /* 6B4 */ + volatile csr_fq_cnt240_u fq_cnt240; /* 6B8 */ + volatile csr_fq_cnt241_u fq_cnt241; /* 6D4 */ +} S_qu_stlfq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_stlfq_csr */ +extern volatile S_qu_stlfq_csr_REGS_TYPE *gopqu_stlfq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetFQ_MODE_REG_cfg_max_oeid(unsigned int ucfg_max_oeid); +int iSetFQ_MODE_REG_cfg_mode_init_def_fq_tx(unsigned int ucfg_mode_init_def_fq_tx); +int iSetFQ_MODE_REG_enable_stf(unsigned int uenable_stf); +int iSetFQ_MODE_REG_cfg_ngsf_mod(unsigned int ucfg_ngsf_mod); +int iSetFQ_MODE_REG_enable_pro(unsigned int uenable_pro); +int iSetFQ_MODE_REG_enable_asc(unsigned int uenable_asc); +int iSetFQ_MODE_REG_cfg_psh_msg_en(unsigned int ucfg_psh_msg_en); +int iSetFQ_MODE_REG_cfg_base_init_def_fq(unsigned int ucfg_base_init_def_fq); +int iSetFQ_MODE_REG_cfg_mode_init_def_fq(unsigned int ucfg_mode_init_def_fq); +int iSetFQ_MODE_REG_cfg_mode_pn(unsigned int ucfg_mode_pn); +int iSetFQ_INITCTAB_START_init_start(unsigned int uinit_start); +int iSetFQ_INITCTAB_ST_fq_init_ctab_st_done(unsigned int ufq_init_ctab_st_done); +int iSetFQ_INIT_LOGIC_ST_fq_init_logic_st_done(unsigned int ufq_init_logic_st_done); +int iSetFQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetFQ_INT_VECTOR_enable(unsigned int uenable); +int iSetFQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetFQ_INT_int_data(unsigned int uint_data); +int iSetFQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetFQ_INT_MASK_int_en(unsigned int uint_en); +int iSetFQ_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetFQ_INT_MEM_ERR_2B_mem_2bit_error(unsigned int umem_2bit_error); +int iSetFQ_INT_MEM_ERR_2B_int_insrt0(unsigned int uint_insrt0); +int iSetFQ_INT_MEM_ERR_2B_mem_err_sticky(unsigned int umem_err_sticky); +int iSetFQ_INT_OEID_AGED_ERR_oeid_age_err_error_bit(unsigned int uoeid_age_err_error_bit); +int iSetFQ_INT_OEID_AGED_ERR_int_insrt1(unsigned int uint_insrt1); +int iSetFQ_INT_OEID_AGED_ERR_oeid_age_err_sticky(unsigned int uoeid_age_err_sticky); +int iSetFQ_INT_SCAN_ERR_scan_err_error_bit(unsigned int uscan_err_error_bit); +int iSetFQ_INT_SCAN_ERR_int_insrt2(unsigned int uint_insrt2); +int iSetFQ_INT_SCAN_ERR_scan_err_sticky(unsigned int uscan_err_sticky); +int iSetFQ_INT_FCMD_ERR_fcmd_err_error_bit(unsigned int ufcmd_err_error_bit); +int iSetFQ_INT_FCMD_ERR_int_insrt3(unsigned int uint_insrt3); +int iSetFQ_INT_FCMD_ERR_fcmd_err_sticky(unsigned int ufcmd_err_sticky); +int iSetFQ_INT_DSP_ERR_dsp_err_error_bit(unsigned int udsp_err_error_bit); +int iSetFQ_INT_DSP_ERR_int_insrt4(unsigned int uint_insrt4); +int iSetFQ_INT_DSP_ERR_dsp_err_sticky(unsigned int udsp_err_sticky); +int iSetFQ_INT_PFH_ERR_pfh_err_error_bit(unsigned int upfh_err_error_bit); +int iSetFQ_INT_PFH_ERR_int_insrt5(unsigned int uint_insrt5); +int iSetFQ_INT_PFH_ERR_pfh_err_sticky(unsigned int upfh_err_sticky); +int iSetFQ_INT_DBE_ERR_dbe_err_error_bit(unsigned int udbe_err_error_bit); +int iSetFQ_INT_DBE_ERR_int_insrt6(unsigned int uint_insrt6); +int iSetFQ_INT_DBE_ERR_dbe_err_sticky(unsigned int udbe_err_sticky); +int iSetFQ_INT_QRSC_ERR_qrsc_err_error_bit(unsigned int uqrsc_err_error_bit); +int iSetFQ_INT_QRSC_ERR_int_insrt7(unsigned int uint_insrt7); +int iSetFQ_INT_QRSC_ERR_qrsc_err_sticky(unsigned int uqrsc_err_sticky); +int iSetFQ_INT_BUF_UF_ERR_buf_uf_error_bit(unsigned int ubuf_uf_error_bit); +int iSetFQ_INT_BUF_UF_ERR_int_insrt8(unsigned int uint_insrt8); +int iSetFQ_INT_BUF_UF_ERR_buf_uf_sticky(unsigned int ubuf_uf_sticky); +int iSetFQ_INT_FIFO0_ERR_fifo_err_error_bit(unsigned int ufifo_err_error_bit); +int iSetFQ_INT_FIFO0_ERR_int_insrt9(unsigned int uint_insrt9); +int iSetFQ_INT_FIFO0_ERR_fifo_err_sticky(unsigned int ufifo_err_sticky); +int iSetFQ_INDRECT_CTRL_indirect_vld(unsigned int uindirect_vld); +int iSetFQ_INDRECT_TIMEOUT_csr_stffq_indrect_timeout(unsigned int ucsr_stffq_indrect_timeout); +int iSetFQ_INDRECT_DAT0_csr_stffq_indrect_data0(unsigned int ucsr_stffq_indrect_data0); +int iSetFQ_INDRECT_DAT1_csr_stffq_indrect_data1(unsigned int ucsr_stffq_indrect_data1); +int iSetFQ_QCNTX_MODE_cfg_wm_lru(unsigned int ucfg_wm_lru); +int iSetFQ_QCNTX_MODE_cfg_lqp_lru(unsigned int ucfg_lqp_lru); +int iSetFQ_QCNTX_MODE_cfg_w2r_byps_en(unsigned int ucfg_w2r_byps_en); +int iSetFQ_QCNTX_MODE_cfg_rcmd_npa_lb_oq_en(unsigned int ucfg_rcmd_npa_lb_oq_en); +int iSetFQ_QCNTX_MODE_cfg_rcmd_pa_lb_oq_en(unsigned int ucfg_rcmd_pa_lb_oq_en); +int iSetFQ_QCNTX_MODE_cfg_wdog_rfil_period(unsigned int ucfg_wdog_rfil_period); +int iSetFQ_QCNTX_MODE_cfg_wdog_rfil_en(unsigned int ucfg_wdog_rfil_en); +int iSetFQ_QCNTX_MODE_cfg_rfl_fastlck_en(unsigned int ucfg_rfl_fastlck_en); +int iSetFQ_AGE_PERIOD_REG_cfg_age_period(unsigned int ucfg_age_period); +int iSetFQ_AGE_PERIOD_REG_cfg_age_period_bg(unsigned int ucfg_age_period_bg); +int iSetFQ_AGE_PERIOD_REG_cfg_fstr_wg(unsigned int ucfg_fstr_wg); +int iSetFQ_AGE_PERIOD_REG_cfg_age_oeid_bg_en(unsigned int ucfg_age_oeid_bg_en); +int iSetFQ_AGE_PERIOD_REG_cfg_wg_eng_en(unsigned int ucfg_wg_eng_en); +int iSetFQ_AGE_PERIOD_REG_cfg_age_oeid_en(unsigned int ucfg_age_oeid_en); +int iSetFQ_AGE_PERIOD_REG_cfg_age2un_en(unsigned int ucfg_age2un_en); +int iSetFQ_AGE_PERIOD_REG_cfg_fq_age_unit(unsigned int ucfg_fq_age_unit); +int iSetSTFFQ_DBE_HW_PFH_CFG_cfg_dbe_hw_pfh_en(unsigned int ucfg_dbe_hw_pfh_en); +int iSetFQ_TMR_ST_st_tmr_defer(unsigned int ust_tmr_defer); +int iSetFQ_TMR_ST_st_tmr_exp(unsigned int ust_tmr_exp); +int iSetFQ_CPB_CFG_dma_adj_attr(unsigned int udma_adj_attr); +int iSetFQ_CPB_CFG_dma_adj_attr_def(unsigned int udma_adj_attr_def); +int iSetFQ_CPB_CFG_otsd_psh_plen(unsigned int uotsd_psh_plen); +int iSetFQ_CPB_CFG_psh_plen_en(unsigned int upsh_plen_en); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_cmd_smf(unsigned int ucnt_crdt_cmd_smf); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_dat_smf(unsigned int ucnt_crdt_dat_smf); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_tl0(unsigned int ucnt_crdt_tl0); +int iSetFQ_CRDT_2TLSMF_ST_cnt_crdt_tl1(unsigned int ucnt_crdt_tl1); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_cmd_smf(unsigned int ucfg_def_crdt_cmd_smf); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_dat_smf(unsigned int ucfg_def_crdt_dat_smf); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_tl0_rsp(unsigned int ucfg_def_crdt_tl0_rsp); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_tl1_rsp(unsigned int ucfg_def_crdt_tl1_rsp); +int iSetFQ_CRDT_2TLSMF_REG_cfg_def_crdt_tmrs(unsigned int ucfg_def_crdt_tmrs); +int iSetFQ_CNT_CTL_mon_sel_idx(unsigned int umon_sel_idx); +int iSetFQ_CNT_CTL_cfg_cnt6_en(unsigned int ucfg_cnt6_en); +int iSetFQ_CNT_CTL_cfg_flit_cnt_en(unsigned int ucfg_flit_cnt_en); +int iSetFQ_CNT_CTL_cfg_cnt_en(unsigned int ucfg_cnt_en); +int iSetFQ_CNT0_fq_cnt0(unsigned int ufq_cnt0); +int iSetFQ_CNT1_fq_cnt1(unsigned int ufq_cnt1); +int iSetFQ_CNT2_fq_cnt2(unsigned int ufq_cnt2); +int iSetFQ_CNT3_fq_cnt3(unsigned int ufq_cnt3); +int iSetFQ_CNT4_fq_cnt4(unsigned int ufq_cnt4); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_srv_typ(unsigned int ucfg_snapsot_srv_typ); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_src(unsigned int ucfg_snapsot_src); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_req_typ(unsigned int ucfg_snapsot_req_typ); +int iSetFQ_SNAPSHOT_CTL_cfg_snapsot_fqid(unsigned int ucfg_snapsot_fqid); +int iSetFQ_SNAPSHOT_CTL_cfg_snapshot_filt_typ_en(unsigned int ucfg_snapshot_filt_typ_en); +int iSetFQ_SNAPSHOT_CTL_cfg_snapshot_en(unsigned int ucfg_snapshot_en); +int iSetFQ_SNAPSHOT_ST_max_asc_latency(unsigned int umax_asc_latency); +int iSetFQ_SNAPSHOT_ST_max_latency_stg(unsigned int umax_latency_stg); +int iSetFQ_SNAPSHOT_ST_total_latency(unsigned int utotal_latency); +int iSetFQ_SNAPSHOT_ST_snapshot_done(unsigned int usnapshot_done); +int iSetFQ_DBE_HW_WQE_EN_cfg_dbe_hw_wqe_en(unsigned int ucfg_dbe_hw_wqe_en); +int iSetFQ_DBE_HW_WQE_CFG_cfg_stagh_wqe_ld(unsigned int ucfg_stagh_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_opid_wqe_ld(unsigned int ucfg_opid_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_aext_wqe_ld(unsigned int ucfg_aext_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_ftid_wqe_ld(unsigned int ucfg_ftid_wqe_ld); +int iSetFQ_DBE_HW_WQE_CFG_cfg_aext_ord(unsigned int ucfg_aext_ord); +int iSetFQ_DBE_HW_WQE_CFG_cfg_txpfl_qp_push(unsigned int ucfg_txpfl_qp_push); +int iSetFQ_DBE_HW_WQE_CFG_cfg_rxpfl_qp_push(unsigned int ucfg_rxpfl_qp_push); +int iSetFQ_DBE_HW_WQE_CFG_cfg_otsd_qp_push(unsigned int ucfg_otsd_qp_push); +int iSetFQ_FIFO_GAP_CFG_gap_fifo_rsp2tl(unsigned int ugap_fifo_rsp2tl); +int iSetFQ_FIFO_GAP_CFG_gap_cmds_fifos(unsigned int ugap_cmds_fifos); +int iSetFQ_FIFO_GAP_CFG_gap_fifo_p2t_cmd(unsigned int ugap_fifo_p2t_cmd); +int iSetFQ_FIFO_GAP_CFG_gap_afifo_cpback(unsigned int ugap_afifo_cpback); +int iSetFQ_FIFO_GAP_CFG_gap_bnd_oeid(unsigned int ugap_bnd_oeid); +int iSetFQ_FIFO_GAP_CFG_gap_afifo_icc_rsp(unsigned int ugap_afifo_icc_rsp); +int iSetFQ_HIS_FIFO_CNT0_p2e_f(unsigned int up2e_f); +int iSetFQ_HIS_FIFO_CNT0_p2e_rbnd(unsigned int up2e_rbnd); +int iSetFQ_HIS_FIFO_CNT0_p2e_ulck(unsigned int up2e_ulck); +int iSetFQ_HIS_FIFO_CNT0_rlck_pcm(unsigned int urlck_pcm); +int iSetFQ_HIS_FIFO_CNT0_cpback(unsigned int ucpback); +int iSetFQ_HIS_FIFO_CNT0_icc_rsp(unsigned int uicc_rsp); +int iSetFQ_HIS_FIFO_CNT0_rlck(unsigned int urlck); +int iSetFQ_HIS_FIFO_CNT1_empty_tpfh(unsigned int uempty_tpfh); +int iSetFQ_HIS_FIFO_CNT1_empty_spqc(unsigned int uempty_spqc); +int iSetFQ_HIS_FIFO_CNT1_empty_rqpc(unsigned int uempty_rqpc); +int iSetFQ_HIS_FIFO_CNT1_empty_ism(unsigned int uempty_ism); +int iSetFQ_HIS_FIFO_CNT1_empty_tpcl(unsigned int uempty_tpcl); +int iSetFQ_HIS_FIFO_CNT1_empty_tcm(unsigned int uempty_tcm); +int iSetFQ_HIS_FIFO_CNT1_tl0_req(unsigned int utl0_req); +int iSetFQ_HIS_FIFO_CNT1_tl1_req(unsigned int utl1_req); +int iSetFQ_HIS_FIFO_CNT1_tl2p_cmds(unsigned int utl2p_cmds); +int iSetFQ_HIS_FIFO_CNT1_tl2p_rfl(unsigned int utl2p_rfl); +int iSetFQ_HIS_FIFO_CNT1_p2tl_cmds(unsigned int up2tl_cmds); +int iSetFQ_FIFO_ST_afull_tl0_rsp(unsigned int uafull_tl0_rsp); +int iSetFQ_FIFO_ST_afull_tl1_rsp(unsigned int uafull_tl1_rsp); +int iSetFQ_FIFO_ST_afull_tl0_req(unsigned int uafull_tl0_req); +int iSetFQ_FIFO_ST_afull_tl1_req(unsigned int uafull_tl1_req); +int iSetFQ_FIFO_ST_afull_tl2p_cmds(unsigned int uafull_tl2p_cmds); +int iSetFQ_FIFO_ST_afull_tl2p_rfl(unsigned int uafull_tl2p_rfl); +int iSetFQ_FIFO_ST_afull_p2tl_cmds(unsigned int uafull_p2tl_cmds); +int iSetFQ_FIFO_ST_afull_p2e_f(unsigned int uafull_p2e_f); +int iSetFQ_FIFO_ST_afull_p2e_rbnd(unsigned int uafull_p2e_rbnd); +int iSetFQ_FIFO_ST_afull_p2e_ulck(unsigned int uafull_p2e_ulck); +int iSetFQ_FIFO_ST_afull_rlck_pcm(unsigned int uafull_rlck_pcm); +int iSetFQ_FIFO_ST_afull_cpback(unsigned int uafull_cpback); +int iSetFQ_FIFO_ST_afull_icc_rsp(unsigned int uafull_icc_rsp); +int iSetFQ_FIFO_ST_afull_bnd(unsigned int uafull_bnd); +int iSetFQ_FIFO_ST_empty_tl0_0dat(unsigned int uempty_tl0_0dat); +int iSetFQ_FIFO_ST_empty_tl0_idat(unsigned int uempty_tl0_idat); +int iSetFQ_FIFO_ST_empty_tl1_0dat(unsigned int uempty_tl1_0dat); +int iSetFQ_FIFO_ST_empty_tl1_idat(unsigned int uempty_tl1_idat); +int iSetFQ_FIFO_ST_empty_tl0_rsp(unsigned int uempty_tl0_rsp); +int iSetFQ_FIFO_ST_empty_tl1_rsp(unsigned int uempty_tl1_rsp); +int iSetFQ_FIFO_ST_empty_tl0_req(unsigned int uempty_tl0_req); +int iSetFQ_FIFO_ST_empty_tl1_req(unsigned int uempty_tl1_req); +int iSetFQ_FIFO_ST_empty_tl2p_cmds(unsigned int uempty_tl2p_cmds); +int iSetFQ_FIFO_ST_empty_tl2p_rfl(unsigned int uempty_tl2p_rfl); +int iSetFQ_FIFO_ST_empty_p2tl_cmds(unsigned int uempty_p2tl_cmds); +int iSetFQ_FIFO_ST_empty_p2e_f(unsigned int uempty_p2e_f); +int iSetFQ_FIFO_ST_empty_p2e_rbnd(unsigned int uempty_p2e_rbnd); +int iSetFQ_FIFO_ST_empty_p2e_ulck(unsigned int uempty_p2e_ulck); +int iSetFQ_FIFO_ST_empty_rlck_pcm(unsigned int uempty_rlck_pcm); +int iSetFQ_FIFO_ST_empty_cpback(unsigned int uempty_cpback); +int iSetFQ_FIFO_ST_empty_icc_rsp(unsigned int uempty_icc_rsp); +int iSetFQ_FIFO_ST_empty_bnd(unsigned int uempty_bnd); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_rsp(unsigned int uhis_ful_tl0_rsp); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_rsp(unsigned int uhis_ful_tl1_rsp); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_req(unsigned int uhis_ful_tl0_req); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_req(unsigned int uhis_ful_tl1_req); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_tl2p_cmds(unsigned int uhis_ful_fifo_tl2p_cmds); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_tl2p_rfl(unsigned int uhis_ful_fifo_tl2p_rfl); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2tl_cmds(unsigned int uhis_ful_fifo_p2tl_cmds); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2e_f(unsigned int uhis_ful_fifo_p2e_f); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2e_rbnd(unsigned int uhis_ful_fifo_p2e_rbnd); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_p2e_ulck(unsigned int uhis_ful_fifo_p2e_ulck); +int iSetFQ_HIS_FIFO_ST_his_ful_fifo_rlck_pcm(unsigned int uhis_ful_fifo_rlck_pcm); +int iSetFQ_HIS_FIFO_ST_his_ful_afifo_cpback(unsigned int uhis_ful_afifo_cpback); +int iSetFQ_HIS_FIFO_ST_his_ful_afifo_icc_rsp(unsigned int uhis_ful_afifo_icc_rsp); +int iSetFQ_HIS_FIFO_ST_his_ful_afifo_bnd(unsigned int uhis_ful_afifo_bnd); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_idat(unsigned int uhis_ful_tl0_idat); +int iSetFQ_HIS_FIFO_ST_his_ful_tl0_odat(unsigned int uhis_ful_tl0_odat); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_idat(unsigned int uhis_ful_tl1_idat); +int iSetFQ_HIS_FIFO_ST_his_ful_tl1_odat(unsigned int uhis_ful_tl1_odat); +int iSetFQ_HIS_FIFO_ST_his_ful_ism_dat(unsigned int uhis_ful_ism_dat); +int iSetFQ_HIS_FIFO_ST_his_ful_sqpc(unsigned int uhis_ful_sqpc); +int iSetFQ_HIS_FIFO_ST_his_ful_rqpc(unsigned int uhis_ful_rqpc); +int iSetFQ_HIS_FIFO_ST_his_ful_tpfh(unsigned int uhis_ful_tpfh); +int iSetFQ_HIS_FIFO_ST_his_ful_tpcl(unsigned int uhis_ful_tpcl); +int iSetFQ_HIS_FIFO_ST_his_ful_tcm(unsigned int uhis_ful_tcm); +int iSetFQ_MEM_CTRL_mem_power_ctrl_sp(unsigned int umem_power_ctrl_sp); +int iSetFQ_MEM_CTRL_mem_timing_ctrl_sp(unsigned int umem_timing_ctrl_sp); +int iSetFQ_MEM_CTRL_mem_power_ctrl_tp(unsigned int umem_power_ctrl_tp); +int iSetFQ_MEM_CTRL_mem_timing_ctrl_tp(unsigned int umem_timing_ctrl_tp); +int iSetFQ_MEM_CTRL_err_req(unsigned int uerr_req); +int iSetFQ_MEM_CTRL_indirect_mem_ecc_en(unsigned int uindirect_mem_ecc_en); +int iSetFQ_MEM_CTRL_mem_ecc_bypass(unsigned int umem_ecc_bypass); +int iSetFQ_CFG_EP2HOST_cfg_map_ep2host(unsigned int ucfg_map_ep2host); +int iSetFQ_PCAR_CFG_cfg_pcar_sh(unsigned int ucfg_pcar_sh); +int iSetFQ_PCAR_CFG_cfg_pcar_sml(unsigned int ucfg_pcar_sml); +int iSetFQ_PCAR_CFG_cfg_pcar_opid(unsigned int ucfg_pcar_opid); +int iSetFQ_PCAR_CFG_cfg_pcar_inst(unsigned int ucfg_pcar_inst); +int iSetFQ_CNT5_fq_cnt5(unsigned int ufq_cnt5); +int iSetFQ_MOD_REG1_base_sub_pro_typ(unsigned int ubase_sub_pro_typ); +int iSetFQ_MOD_REG1_max_sub_pro_typ(unsigned int umax_sub_pro_typ); +int iSetFQ_MOD_REG1_cfg_pro_typ_nret_pkt(unsigned int ucfg_pro_typ_nret_pkt); +int iSetFQ_MOD_REG1_cfg_pro_typ_lb(unsigned int ucfg_pro_typ_lb); +int iSetFQ_MOD_REG1_cfg_th_fc_on(unsigned int ucfg_th_fc_on); +int iSetFQ_MOD_REG1_cfg_th_fc_dif(unsigned int ucfg_th_fc_dif); +int iSetFQ_MOD_REG1_cfg_th_fc_mode(unsigned int ucfg_th_fc_mode); +int iSetFQ_MOD_REG1_cfg_dsp_fstr_cup_en(unsigned int ucfg_dsp_fstr_cup_en); +int iSetFQ_MOD_REG1_cfg_dsp_fastlck_en(unsigned int ucfg_dsp_fastlck_en); +int iSetFQ_INNER_BP_ST_tmr_stf_bp(unsigned int utmr_stf_bp); +int iSetFQ_INNER_BP_ST_tmr_stl_bp(unsigned int utmr_stl_bp); +int iSetFQ_INNER_BP_ST_pro2cmd_bp(unsigned int upro2cmd_bp); +int iSetFQ_INNER_BP_ST_t2cup_bp(unsigned int ut2cup_bp); +int iSetFQ_INNER_BP_ST_fcam_pfh_bp(unsigned int ufcam_pfh_bp); +int iSetFQ_INNER_BP_ST_fq2smf_bp(unsigned int ufq2smf_bp); +int iSetFQ_INNER_BP_ST_smf2fq_dat_bp(unsigned int usmf2fq_dat_bp); +int iSetFQ_INNER_BP_ST_smf2fq_cmd_bp(unsigned int usmf2fq_cmd_bp); +int iSetFQ_INNER_BP_ST_rsc_qidx_bp(unsigned int ursc_qidx_bp); +int iSetFQ_INNER_BP_ST_rsc_fqg_bp(unsigned int ursc_fqg_bp); +int iSetFQ_INNER_BP_ST_rsc_lqp_bp(unsigned int ursc_lqp_bp); +int iSetFQ_INNER_BP_ST_t2fsg_rls_bp(unsigned int ut2fsg_rls_bp); +int iSetFQ_INNER_BP_ST_t2fsg_bp(unsigned int ut2fsg_bp); +int iSetFQ_INNER_BP_ST_t2rfl_bp(unsigned int ut2rfl_bp); +int iSetFQ_INNER_BP_ST_t2pfh_bp(unsigned int ut2pfh_bp); +int iSetFQ_INNER_BP_ST_rstg1_bp(unsigned int urstg1_bp); +int iSetFQ_INNER_BP_ST_rstg0_bp(unsigned int urstg0_bp); +int iSetFQ_INNER_BP_ST_fq2tl1_req_bp(unsigned int ufq2tl1_req_bp); +int iSetFQ_INNER_BP_ST_tl02fq_req_bp(unsigned int utl02fq_req_bp); +int iSetFQ_INNER_BP_ST_fq2tl1_rsp_bp(unsigned int ufq2tl1_rsp_bp); +int iSetFQ_INNER_BP_ST_fq2tl0_rsp_bp(unsigned int ufq2tl0_rsp_bp); +int iSetFQ_INNER_BP_ST_fq2pdm_dcc_bp(unsigned int ufq2pdm_dcc_bp); +int iSetFQ_INNER_BP_ST_fq2pdm_icc_bp(unsigned int ufq2pdm_icc_bp); +int iSetFQ_INNER_BP_ST_ritf_tcm_bp(unsigned int uritf_tcm_bp); +int iSetFQ_INNER_BP_ST_ritf_ord_bp(unsigned int uritf_ord_bp); +int iSetFQ_INNER_BP_ST_fq_psh_msg_bp(unsigned int ufq_psh_msg_bp); +int iSetFQ_INNER_BP_ST_fq2iq_lb_bp(unsigned int ufq2iq_lb_bp); +int iSetFQ_INNER_BP_ST_fq2oq_dsp_bp(unsigned int ufq2oq_dsp_bp); +int iSetFQ_INNER_BP_ST_fq2iq_bnd_bp(unsigned int ufq2iq_bnd_bp); +int iSetFQ_INNER_MON_ST_ctp(unsigned int uctp); +int iSetFQ_CNT6_fq_cnt6(unsigned int ufq_cnt6); +int iSetFQ_CNT_CTL1_fa_cnt1_reserved(unsigned int ufa_cnt1_reserved); +int iSetFQ_CNT_CTL1_cfg_typ_cnt9(unsigned int ucfg_typ_cnt9); +int iSetFQ_CNT_CTL1_cfg_cnt_1_en(unsigned int ucfg_cnt_1_en); +int iSetFQ_CNT7_fq_cnt7(unsigned int ufq_cnt7); +int iSetFQ_CNT8_fq_cnt8(unsigned int ufq_cnt8); +int iSetFQ_CNT9_fq_cnt9(unsigned int ufq_cnt9); +int iSetFQ_CNT10_fq_cnt10(unsigned int ufq_cnt10); +int iSetFQ_CNT11_fq_cnt11(unsigned int ufq_cnt11); +int iSetFQ_CNT12_fq_cnt12(unsigned int ufq_cnt12); +int iSetFQ_CNT13_fq_cnt13(unsigned int ufq_cnt13); +int iSetFQ_CNT14_fq_cnt14(unsigned int ufq_cnt14); +int iSetFQ_CNT15_fq_cnt15(unsigned int ufq_cnt15); +int iSetFQ_CNT16_fq_cnt16(unsigned int ufq_cnt16); +int iSetFQ_INT_MEM_ERR_1B_mem_err_1b_error_bit(unsigned int umem_err_1b_error_bit); +int iSetFQ_INT_MEM_ERR_1B_int_insrt10(unsigned int uint_insrt10); +int iSetFQ_INT_MEM_ERR_1B_mem_err_1b_sticky(unsigned int umem_err_1b_sticky); +int iSetCFG_STYP_TH_FC_EN_cfg_styp_th_fc_en(unsigned int ucfg_styp_th_fc_en); +int iSetCFG_ZERO_ESCH_LEN_cfg_zero_esch_len(unsigned int ucfg_zero_esch_len); +int iSetCFG_FQ_BUBBLE_CTL_cfg_fq_bubble_ctl(unsigned int ucfg_fq_bubble_ctl); +int iSetCFG_L2DCACHE_BUBBLE_CTL_cfg_l2dcache_bubble_ctl(unsigned int ucfg_l2dcache_bubble_ctl); +int iSetFQ_DEF_FQ_CTL_cfg_tx_base_init_def_fq(unsigned int ucfg_tx_base_init_def_fq); +int iSetFQ_DEF_FQ_CTL_cfg_tx_mode_init_def_fq(unsigned int ucfg_tx_mode_init_def_fq); +int iSetFQ_DEF_FQ_CTL_reserved2(unsigned int ureserved2); +int iSetFQ_DEF_FQ_CTL_cfg_rx_base_init_def_fq(unsigned int ucfg_rx_base_init_def_fq); +int iSetFQ_DEF_FQ_CTL_cfg_rx_mode_init_def_fq(unsigned int ucfg_rx_mode_init_def_fq); +int iSetFQ_DEF_FQ_CTL_reserved1(unsigned int ureserved1); +int iSetFQ_SMF_LDBCTL_fq_smf_ldb_ctl_vfen(unsigned int ufq_smf_ldb_ctl_vfen); +int iSetFQ_SMF_LDBCTL_fq_smf_ldb_ctl_ofst(unsigned int ufq_smf_ldb_ctl_ofst); +int iSetFQ_SMF_LDBCTL_fq_tmr_pro_typ_ctl(unsigned int ufq_tmr_pro_typ_ctl); +int iSetFQ_SMF_LDBCTL_fq_smf_only1_ctl(unsigned int ufq_smf_only1_ctl); +int iSetFQ_SMF_LDBCTL_fq_smf_lbctl_reserved1(unsigned int ufq_smf_lbctl_reserved1); +int iSetFQ_CFG_EP2HOST_H2_cfg_map_ep2host_h2(unsigned int ucfg_map_ep2host_h2); +int iSetFQ_CFG_EP2HOST_H2_cfg_map_ep2host_rsvd(unsigned int ucfg_map_ep2host_rsvd); +int iSetFQ_CFG_PREFETCH_CTL_fq_pfhctl_coco_xid20(unsigned int ufq_pfhctl_coco_xid20); +int iSetFQ_CFG_PREFETCH_CTL_fq_base_sub_pro_typ(unsigned int ufq_base_sub_pro_typ); +int iSetFQ_CFG_PREFETCH_CTL_fq_max_sub_pro_typ(unsigned int ufq_max_sub_pro_typ); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_nret_pkt(unsigned int ufq_cfg_pro_typ_nret_pkt); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_lb(unsigned int ufq_cfg_pro_typ_lb); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_lb_org(unsigned int ufq_cfg_pro_typ_lb_org); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_pro_typ_nret_org(unsigned int ufq_cfg_pro_typ_nret_org); +int iSetFQ_CFG_PREFETCH_CTL_fq_cfg_prefetch_ctl_rsvd(unsigned int ufq_cfg_prefetch_ctl_rsvd); +int iSetFQ_LATENCY_CFG_csr_fq_sample_mode(unsigned int ucsr_fq_sample_mode); +int iSetFQ_LATENCY_CFG_csr_fq_spec_port_en(unsigned int ucsr_fq_spec_port_en); +int iSetFQ_LATENCY_CFG_csr_fq_done_clr(unsigned int ucsr_fq_done_clr); +int iSetFQ_LATENCY_CFG_csr_fq_spec_port_num(unsigned int ucsr_fq_spec_port_num); +int iSetFQ_LATENCY_CFG_csr_fq_spec_pptr_typ(unsigned int ucsr_fq_spec_pptr_typ); +int iSetFQ_LATENCY_STA_fq_csr_sample_done(unsigned int ufq_csr_sample_done); +int iSetFQ_SAMPLE_TMR_fq_csr_sample_tmr(unsigned int ufq_csr_sample_tmr); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_rsvd2(unsigned int ufq_fake_vfid_pf_rsvd2); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_start_bit(unsigned int ufq_fake_vfid_pf_start_bit); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_end_bit(unsigned int ufq_fake_vfid_pf_end_bit); +int iSetFQ_CFG_FAKE_VF_CTL_fq_fake_vfid_pf_rsvd1(unsigned int ufq_fake_vfid_pf_rsvd1); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bps_dly_dbld(unsigned int ufq_cfg_bps_dly_dbld); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bps_dly_fsg(unsigned int ufq_cfg_bps_dly_fsg); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bpsfsg_oeid_th(unsigned int ufq_cfg_bpsfsg_oeid_th); +int iSetFQ_CFG_BPS_DLY_CTL_fq_cfg_bps_dly_rsvd(unsigned int ufq_cfg_bps_dly_rsvd); +int iSetFQ_CFG_OTSD_BASE_CTL_fq_cfg_otsd_base_ctl_val(unsigned int ufq_cfg_otsd_base_ctl_val); +int iSetFQ_CFG_OTSD_BASE_CTL_fq_cfg_otsd_base_ctl_rsvd(unsigned int ufq_cfg_otsd_base_ctl_rsvd); +int iSetFQ_CNT_CTL2_cfg_cnt_2_en(unsigned int ucfg_cnt_2_en); +int iSetFQ_CNT17_fq_cnt17(unsigned int ufq_cnt17); +int iSetFQ_CNT18_fq_cnt18(unsigned int ufq_cnt18); +int iSetFQ_CNT19_fq_cnt19(unsigned int ufq_cnt19); +int iSetFQ_CNT20_fq_cnt20(unsigned int ufq_cnt20); +int iSetFQ_CNT21_fq_cnt21(unsigned int ufq_cnt21); +int iSetFQ_CNT22_fq_cnt22(unsigned int ufq_cnt22); +int iSetFQ_CNT23_fq_cnt23(unsigned int ufq_cnt23); +int iSetFQ_CNT24_fq_cnt24(unsigned int ufq_cnt24); +int iSetFQ_CNT25_fq_cnt25(unsigned int ufq_cnt25); +int iSetFQ_CNT26_fq_cnt26(unsigned int ufq_cnt26); +int iSetFQ_CNT_CTL3_cfg_cnt_3_en(unsigned int ucfg_cnt_3_en); +int iSetFQ_CNT27_fq_cnt27(unsigned int ufq_cnt27); +int iSetFQ_CNT28_fq_cnt28(unsigned int ufq_cnt28); +int iSetFQ_CNT29_fq_cnt29(unsigned int ufq_cnt29); +int iSetFQ_CNT30_fq_cnt30(unsigned int ufq_cnt30); +int iSetFQ_CNT31_fq_cnt31(unsigned int ufq_cnt31); +int iSetFQ_CNT32_fq_cnt32(unsigned int ufq_cnt32); +int iSetFQ_CNT33_fq_cnt33(unsigned int ufq_cnt33); +int iSetFQ_CNT34_fq_cnt34(unsigned int ufq_cnt34); +int iSetFQ_CNT35_fq_cnt35(unsigned int ufq_cnt35); +int iSetFQ_CNT36_fq_cnt36(unsigned int ufq_cnt36); +int iSetFQ_CNT_CTL4_cfg_cnt_4_en(unsigned int ucfg_cnt_4_en); +int iSetFQ_CNT37_fq_cnt37(unsigned int ufq_cnt37); +int iSetFQ_CNT38_fq_cnt38(unsigned int ufq_cnt38); +int iSetFQ_CNT39_fq_cnt39(unsigned int ufq_cnt39); +int iSetFQ_CNT40_fq_cnt40(unsigned int ufq_cnt40); +int iSetFQ_CNT41_fq_cnt41(unsigned int ufq_cnt41); +int iSetFQ_CNT42_fq_cnt42(unsigned int ufq_cnt42); +int iSetFQ_CNT43_fq_cnt43(unsigned int ufq_cnt43); +int iSetFQ_CNT44_fq_cnt44(unsigned int ufq_cnt44); +int iSetFQ_CNT45_fq_cnt45(unsigned int ufq_cnt45); +int iSetFQ_CNT46_fq_cnt46(unsigned int ufq_cnt46); +int iSetFQ_QU2SMF_TMR_DLY_fq_qu2smf_tmr_dly_val(unsigned int ufq_qu2smf_tmr_dly_val); +int iSetFQ_QU2SMF_TMR_DLY_fq_qu2smf_tmr_dly_op(unsigned int ufq_qu2smf_tmr_dly_op); +int iSetFQ_MAGIC_BOX_CTL_fq_mgbx_quf_pg(unsigned int ufq_mgbx_quf_pg); +int iSetFQ_MAGIC_BOX_CTL_fq_mgbx_smf_pg(unsigned int ufq_mgbx_smf_pg); +int iSetFQ_MAGIC_BOX_CTL_fq_mgbx_lbf_mode(unsigned int ufq_mgbx_lbf_mode); +int iSetFQ_MGBX_SRV2HASH_fq_mgbx_srv2hash(unsigned int ufq_mgbx_srv2hash); +int iSetFQ_INNER_MON_ST1_fq_inner_mon_st1(unsigned int ufq_inner_mon_st1); +int iSetFQ_INNER_MON_ST2_fq_inner_mon_st2(unsigned int ufq_inner_mon_st2); +int iSetFQ_INNER_MON_ST3_fq_inner_mon_st3(unsigned int ufq_inner_mon_st3); +int iSetFQ_INNER_MON_ST4_fq_inner_mon_st4(unsigned int ufq_inner_mon_st4); +int iSetFQ_INNER_MON_ST5_fq_inner_mon_st5(unsigned int ufq_inner_mon_st5); +int iSetFQ_INNER_MON_ST6_fq_inner_mon_st6(unsigned int ufq_inner_mon_st6); +int iSetFQ_INNER_MON_ST7_fq_inner_mon_st7(unsigned int ufq_inner_mon_st7); +int iSetFQ_INNER_MON_ST8_fq_inner_mon_st8(unsigned int ufq_inner_mon_st8); +int iSetFQ_INNER_MON_ST9_fq_inner_mon_st9(unsigned int ufq_inner_mon_st9); +int iSetFQ_INNER_MON_ST10_fq_inner_mon_st10(unsigned int ufq_inner_mon_st10); +int iSetFQ_INNER_MON_ST11_fq_inner_mon_st11(unsigned int ufq_inner_mon_st11); +int iSetFQ_INNER_MON_ST12_fq_inner_mon_st12(unsigned int ufq_inner_mon_st12); +int iSetFQ_INNER_MON_ST13_fq_inner_mon_st13(unsigned int ufq_inner_mon_st13); +int iSetFQ_INNER_MON_ST14_fq_inner_mon_st14(unsigned int ufq_inner_mon_st14); +int iSetFQ_INNER_MON_ST15_fq_inner_mon_st15(unsigned int ufq_inner_mon_st15); +int iSetFQ_INNER_MON_ST16_fq_inner_mon_st16(unsigned int ufq_inner_mon_st16); +int iSetFQ_INNER_MON_ST17_fq_inner_mon_st17(unsigned int ufq_inner_mon_st17); +int iSetFQ_INNER_MON_ST18_fq_inner_mon_st18(unsigned int ufq_inner_mon_st18); +int iSetFQ_INNER_MON_ST19_fq_inner_mon_st19(unsigned int ufq_inner_mon_st19); +int iSetFQ_INNER_MON_ST20_fq_inner_mon_st20(unsigned int ufq_inner_mon_st20); +int iSetFQ_INNER_MON_ST21_fq_inner_mon_st21(unsigned int ufq_inner_mon_st21); +int iSetFQ_INNER_MON_ST22_fq_inner_mon_st22(unsigned int ufq_inner_mon_st22); +int iSetFQ_INNER_MON_ST23_fq_inner_mon_st23(unsigned int ufq_inner_mon_st23); +int iSetFQ_INNER_MON_ST24_fq_inner_mon_st24(unsigned int ufq_inner_mon_st24); +int iSetFQ_INNER_MON_ST25_fq_inner_mon_st25(unsigned int ufq_inner_mon_st25); +int iSetFQ_INNER_MON_ST26_fq_inner_mon_st26(unsigned int ufq_inner_mon_st26); +int iSetFQ_INNER_MON_ST27_fq_inner_mon_st27(unsigned int ufq_inner_mon_st27); +int iSetFQ_INNER_MON_ST28_fq_inner_mon_st28(unsigned int ufq_inner_mon_st28); +int iSetFQ_INNER_MON_ST29_fq_inner_mon_st29(unsigned int ufq_inner_mon_st29); +int iSetFQ_INNER_MON_ST30_fq_inner_mon_st30(unsigned int ufq_inner_mon_st30); +int iSetFQ_INNER_MON_ST31_fq_inner_mon_st31(unsigned int ufq_inner_mon_st31); +int iSetFQ_INNER_MON_ST32_fq_inner_mon_st32(unsigned int ufq_inner_mon_st32); +int iSetFQ_INNER_MON_ST33_fq_inner_mon_st33(unsigned int ufq_inner_mon_st33); +int iSetFQ_INNER_MON_ST34_fq_inner_mon_st34(unsigned int ufq_inner_mon_st34); +int iSetFQ_INNER_MON_ST35_fq_inner_mon_st35(unsigned int ufq_inner_mon_st35); +int iSetFQ_INNER_MON_ST36_fq_inner_mon_st36(unsigned int ufq_inner_mon_st36); +int iSetFQ_INNER_MON_ST37_fq_inner_mon_st37(unsigned int ufq_inner_mon_st37); +int iSetFQ_INNER_MON_ST38_fq_inner_mon_st38(unsigned int ufq_inner_mon_st38); +int iSetFQ_INNER_MON_ST39_fq_inner_mon_st39(unsigned int ufq_inner_mon_st39); +int iSetFQ_INNER_MON_ST40_fq_inner_mon_st40(unsigned int ufq_inner_mon_st40); +int iSetFQ_INNER_MON_ST41_fq_inner_mon_st41(unsigned int ufq_inner_mon_st41); +int iSetFQ_INNER_MON_ST42_fq_inner_mon_st42(unsigned int ufq_inner_mon_st42); +int iSetFQ_INNER_MON_ST43_fq_inner_mon_st43(unsigned int ufq_inner_mon_st43); +int iSetFQ_INNER_MON_ST44_fq_inner_mon_st44(unsigned int ufq_inner_mon_st44); +int iSetFQ_INNER_MON_ST45_fq_inner_mon_st45(unsigned int ufq_inner_mon_st45); +int iSetFQ_INNER_MON_ST46_fq_inner_mon_st46(unsigned int ufq_inner_mon_st46); +int iSetFQ_INNER_MON_ST47_fq_inner_mon_st47(unsigned int ufq_inner_mon_st47); +int iSetFQ_INNER_MON_ST48_fq_inner_mon_st48(unsigned int ufq_inner_mon_st48); +int iSetFQ_CNT47_fq_cnt47(unsigned int ufq_cnt47); +int iSetFQ_ROU_RQST_FIFO0_rou_rqst_fifo_st0(unsigned int urou_rqst_fifo_st0); +int iSetFQ_ROU_RQST_FIFO0_rou_rqst_i_ae_th0(unsigned int urou_rqst_i_ae_th0); +int iSetFQ_ROU_RQST_FIFO0_rou_rqst_i_af_th0(unsigned int urou_rqst_i_af_th0); +int iSetFQ_ROU_RSP_FIFO0_rou_rsp_fifo_st0(unsigned int urou_rsp_fifo_st0); +int iSetFQ_ROU_RSP_FIFO0_rou_rsp_i_ae_th0(unsigned int urou_rsp_i_ae_th0); +int iSetFQ_ROU_RSP_FIFO0_rou_rsp_i_af_th0(unsigned int urou_rsp_i_af_th0); +int iSetFQ_ROU_RSP_FIFO1_rou_rsp_fifo_st1(unsigned int urou_rsp_fifo_st1); +int iSetFQ_ROU_RSP_FIFO1_rou_rsp_i_ae_th1(unsigned int urou_rsp_i_ae_th1); +int iSetFQ_ROU_RSP_FIFO1_rou_rsp_i_af_th1(unsigned int urou_rsp_i_af_th1); +int iSetFQ_ROU_TMRODR_FIFO0_rou_tmrodr_rqst0_fifo_st(unsigned int urou_tmrodr_rqst0_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO0_rou_tmrodr_rqst0_i_ae_th(unsigned int urou_tmrodr_rqst0_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO0_rou_tmrodr_rqst0_i_af_th(unsigned int urou_tmrodr_rqst0_i_af_th); +int iSetFQ_ROU_TMRODR_FIFO1_rou_tmrodr_rqst1_fifo_st(unsigned int urou_tmrodr_rqst1_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO1_rou_tmrodr_rqst1_i_ae_th(unsigned int urou_tmrodr_rqst1_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO1_rou_tmrodr_rqst1_i_af_th(unsigned int urou_tmrodr_rqst1_i_af_th); +int iSetFQ_ROU_TMRODR_FIFO2_rou_tmrodr_rqst2_fifo_st(unsigned int urou_tmrodr_rqst2_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO2_rou_tmrodr_rqst2_i_ae_th(unsigned int urou_tmrodr_rqst2_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO2_rou_tmrodr_rqst2_i_af_th(unsigned int urou_tmrodr_rqst2_i_af_th); +int iSetFQ_ROU_TMRODR_FIFO3_rou_tmrodr_rqst3_fifo_st(unsigned int urou_tmrodr_rqst3_fifo_st); +int iSetFQ_ROU_TMRODR_FIFO3_rou_tmrodr_rqst3_i_ae_th(unsigned int urou_tmrodr_rqst3_i_ae_th); +int iSetFQ_ROU_TMRODR_FIFO3_rou_tmrodr_rqst3_i_af_th(unsigned int urou_tmrodr_rqst3_i_af_th); +int iSetFQ_RIN_RQST_FIFO_rin_rqst_fifo_st(unsigned int urin_rqst_fifo_st); +int iSetFQ_RIN_RQST_FIFO_rin_rqst_i_ae_th(unsigned int urin_rqst_i_ae_th); +int iSetFQ_RIN_RQST_FIFO_rin_rqst_i_af_th(unsigned int urin_rqst_i_af_th); +int iSetFQ_RIN_RSP_FIFO_rin_rsp_fifo_st(unsigned int urin_rsp_fifo_st); +int iSetFQ_RIN_RSP_FIFO_rin_rsp_i_ae_th(unsigned int urin_rsp_i_ae_th); +int iSetFQ_RIN_RSP_FIFO_rin_rsp_i_af_th(unsigned int urin_rsp_i_af_th); +int iSetFQ_SMF_RSP_FIFO0_smf_rsp0_fifo_st(unsigned int usmf_rsp0_fifo_st); +int iSetFQ_SMF_RSP_FIFO0_smf_rsp0_i_ae_th(unsigned int usmf_rsp0_i_ae_th); +int iSetFQ_SMF_RSP_FIFO0_smf_rsp0_i_af_th(unsigned int usmf_rsp0_i_af_th); +int iSetFQ_SMF_RSP_FIFO1_smf_rsp1_fifo_st(unsigned int usmf_rsp1_fifo_st); +int iSetFQ_SMF_RSP_FIFO1_smf_rsp1_i_ae_th(unsigned int usmf_rsp1_i_ae_th); +int iSetFQ_SMF_RSP_FIFO1_smf_rsp1_i_af_th(unsigned int usmf_rsp1_i_af_th); +int iSetFQ_TL0_CMD_FIFO0_tl0_cmd_fifo_st(unsigned int utl0_cmd_fifo_st); +int iSetFQ_TL0_CMD_FIFO0_tl0_cmd_i_ae_th(unsigned int utl0_cmd_i_ae_th); +int iSetFQ_TL0_CMD_FIFO0_tl0_cmd_i_af_th(unsigned int utl0_cmd_i_af_th); +int iSetFQ_TL0_EXTCMD_FIFO0_tl0_extcmd_fifo_st(unsigned int utl0_extcmd_fifo_st); +int iSetFQ_TL0_EXTCMD_FIFO0_tl0_extcmd_i_ae_th(unsigned int utl0_extcmd_i_ae_th); +int iSetFQ_TL0_EXTCMD_FIFO0_tl0_extcmd_i_af_th(unsigned int utl0_extcmd_i_af_th); +int iSetFQ_TL1_CMD_FIFO1_tl1_cmd_fifo_st(unsigned int utl1_cmd_fifo_st); +int iSetFQ_TL1_CMD_FIFO1_tl1_cmd_i_ae_th(unsigned int utl1_cmd_i_ae_th); +int iSetFQ_TL1_CMD_FIFO1_tl1_cmd_i_af_th(unsigned int utl1_cmd_i_af_th); +int iSetFQ_TL1_EXTCMD_FIFO0_tl1_extcmd_fifo_st(unsigned int utl1_extcmd_fifo_st); +int iSetFQ_TL1_EXTCMD_FIFO0_tl1_extcmd_i_ae_th(unsigned int utl1_extcmd_i_ae_th); +int iSetFQ_TL1_EXTCMD_FIFO0_tl1_extcmd_i_af_th(unsigned int utl1_extcmd_i_af_th); +int iSetFQ_FQ2OQ_FCNP_FIFO_fq2oq_fcnp_fifo_st(unsigned int ufq2oq_fcnp_fifo_st); +int iSetFQ_FQ2OQ_FCNP_FIFO_fq2oq_fcnp_i_ae_th(unsigned int ufq2oq_fcnp_i_ae_th); +int iSetFQ_FQ2OQ_FCNP_FIFO_fq2oq_fcnp_i_af_th(unsigned int ufq2oq_fcnp_i_af_th); +int iSetFQ_OQ2FQ_FCNP_FIFO_oq2fq_fcnp_fifo_st(unsigned int uoq2fq_fcnp_fifo_st); +int iSetFQ_OQ2FQ_FCNP_FIFO_oq2fq_fcnp_i_ae_th(unsigned int uoq2fq_fcnp_i_ae_th); +int iSetFQ_OQ2FQ_FCNP_FIFO_oq2fq_fcnp_i_af_th(unsigned int uoq2fq_fcnp_i_af_th); +int iSetFQ_TMR_RSP_FIFO0_tmr_rsp0_fifo_st(unsigned int utmr_rsp0_fifo_st); +int iSetFQ_TMR_RSP_FIFO0_tmr_rsp0_i_ae_th(unsigned int utmr_rsp0_i_ae_th); +int iSetFQ_TMR_RSP_FIFO0_tmr_rsp0_i_af_th(unsigned int utmr_rsp0_i_af_th); +int iSetFQ_TMR_RSP_FIFO1_tmr_rsp1_fifo_st(unsigned int utmr_rsp1_fifo_st); +int iSetFQ_TMR_RSP_FIFO1_tmr_rsp1_i_ae_th(unsigned int utmr_rsp1_i_ae_th); +int iSetFQ_TMR_RSP_FIFO1_tmr_rsp1_i_af_th(unsigned int utmr_rsp1_i_af_th); +int iSetFQ_TMR_RSP_FIFO2_tmr_rsp2_fifo_st(unsigned int utmr_rsp2_fifo_st); +int iSetFQ_TMR_RSP_FIFO2_tmr_rsp2_i_ae_th(unsigned int utmr_rsp2_i_ae_th); +int iSetFQ_TMR_RSP_FIFO2_tmr_rsp2_i_af_th(unsigned int utmr_rsp2_i_af_th); +int iSetFQ_TMR_RSP_FIFO3_tmr_rsp3_fifo_st(unsigned int utmr_rsp3_fifo_st); +int iSetFQ_TMR_RSP_FIFO3_tmr_rsp3_i_ae_th(unsigned int utmr_rsp3_i_ae_th); +int iSetFQ_TMR_RSP_FIFO3_tmr_rsp3_i_af_th(unsigned int utmr_rsp3_i_af_th); +int iSetFQ_TMR_RSP_FIFO4_tmr_rsp4_fifo_st(unsigned int utmr_rsp4_fifo_st); +int iSetFQ_TMR_RSP_FIFO4_tmr_rsp4_i_ae_th(unsigned int utmr_rsp4_i_ae_th); +int iSetFQ_TMR_RSP_FIFO4_tmr_rsp4_i_af_th(unsigned int utmr_rsp4_i_af_th); +int iSetFQ_TMR_RSP_FIFO5_tmr_rsp5_fifo_st(unsigned int utmr_rsp5_fifo_st); +int iSetFQ_TMR_RSP_FIFO5_tmr_rsp5_i_ae_th(unsigned int utmr_rsp5_i_ae_th); +int iSetFQ_TMR_RSP_FIFO5_tmr_rsp5_i_af_th(unsigned int utmr_rsp5_i_af_th); +int iSetFQ_TMR_RSP_FIFO6_tmr_rsp6_fifo_st(unsigned int utmr_rsp6_fifo_st); +int iSetFQ_TMR_RSP_FIFO6_tmr_rsp6_i_ae_th(unsigned int utmr_rsp6_i_ae_th); +int iSetFQ_TMR_RSP_FIFO6_tmr_rsp6_i_af_th(unsigned int utmr_rsp6_i_af_th); +int iSetFQ_TMR_RSP_FIFO7_tmr_rsp7_fifo_st(unsigned int utmr_rsp7_fifo_st); +int iSetFQ_TMR_RSP_FIFO7_tmr_rsp7_i_ae_th(unsigned int utmr_rsp7_i_ae_th); +int iSetFQ_TMR_RSP_FIFO7_tmr_rsp7_i_af_th(unsigned int utmr_rsp7_i_af_th); +int iSetFQ_TMR_RSP_FIFO8_tmr_rsp8_fifo_st(unsigned int utmr_rsp8_fifo_st); +int iSetFQ_TMR_RSP_FIFO8_tmr_rsp8_i_ae_th(unsigned int utmr_rsp8_i_ae_th); +int iSetFQ_TMR_RSP_FIFO8_tmr_rsp8_i_af_th(unsigned int utmr_rsp8_i_af_th); +int iSetFQ_TMR_RSP_FIFO9_tmr_rsp9_fifo_st(unsigned int utmr_rsp9_fifo_st); +int iSetFQ_TMR_RSP_FIFO9_tmr_rsp9_i_ae_th(unsigned int utmr_rsp9_i_ae_th); +int iSetFQ_TMR_RSP_FIFO9_tmr_rsp9_i_af_th(unsigned int utmr_rsp9_i_af_th); +int iSetFQ_TMR_RSP_FIFO10_tmr_rsp10_fifo_st(unsigned int utmr_rsp10_fifo_st); +int iSetFQ_TMR_RSP_FIFO10_tmr_rsp10_i_ae_th(unsigned int utmr_rsp10_i_ae_th); +int iSetFQ_TMR_RSP_FIFO10_tmr_rsp10_i_af_th(unsigned int utmr_rsp10_i_af_th); +int iSetFQ_TMR_RSP_FIFO11_tmr_rsp11_fifo_st(unsigned int utmr_rsp11_fifo_st); +int iSetFQ_TMR_RSP_FIFO11_tmr_rsp11_i_ae_th(unsigned int utmr_rsp11_i_ae_th); +int iSetFQ_TMR_RSP_FIFO11_tmr_rsp11_i_af_th(unsigned int utmr_rsp11_i_af_th); +int iSetFQ_TMR_RSP_FIFO12_tmr_rsp12_fifo_st(unsigned int utmr_rsp12_fifo_st); +int iSetFQ_TMR_RSP_FIFO12_tmr_rsp12_i_ae_th(unsigned int utmr_rsp12_i_ae_th); +int iSetFQ_TMR_RSP_FIFO12_tmr_rsp12_i_af_th(unsigned int utmr_rsp12_i_af_th); +int iSetFQ_TMR_RSP_FIFO13_tmr_rsp13_fifo_st(unsigned int utmr_rsp13_fifo_st); +int iSetFQ_TMR_RSP_FIFO13_tmr_rsp13_i_ae_th(unsigned int utmr_rsp13_i_ae_th); +int iSetFQ_TMR_RSP_FIFO13_tmr_rsp13_i_af_th(unsigned int utmr_rsp13_i_af_th); +int iSetFQ_TMR_RSP_FIFO14_tmr_rsp14_fifo_st(unsigned int utmr_rsp14_fifo_st); +int iSetFQ_TMR_RSP_FIFO14_tmr_rsp14_i_ae_th(unsigned int utmr_rsp14_i_ae_th); +int iSetFQ_TMR_RSP_FIFO14_tmr_rsp14_i_af_th(unsigned int utmr_rsp14_i_af_th); +int iSetFQ_TMR_RSP_FIFO15_tmr_rsp15_fifo_st(unsigned int utmr_rsp15_fifo_st); +int iSetFQ_TMR_RSP_FIFO15_tmr_rsp15_i_ae_th(unsigned int utmr_rsp15_i_ae_th); +int iSetFQ_TMR_RSP_FIFO15_tmr_rsp15_i_af_th(unsigned int utmr_rsp15_i_af_th); +int iSetFQ_INT_RIN_RQST_ERR_fq_rin_rqst_err(unsigned int ufq_rin_rqst_err); +int iSetFQ_INT_RIN_RQST_ERR_int_insrt11(unsigned int uint_insrt11); +int iSetFQ_INT_RIN_RQST_ERR_fq_rin_rqst_err_sticky(unsigned int ufq_rin_rqst_err_sticky); +int iSetFQ_INT_RIN_RSP_ERR_fq_rin_rsp_err(unsigned int ufq_rin_rsp_err); +int iSetFQ_INT_RIN_RSP_ERR_int_insrt12(unsigned int uint_insrt12); +int iSetFQ_INT_RIN_RSP_ERR_fq_rin_rsp_err_sticky(unsigned int ufq_rin_rsp_err_sticky); +int iSetFQ_INT_RIN_TRSP_ERR_fq_rin_trsp_err(unsigned int ufq_rin_trsp_err); +int iSetFQ_INT_RIN_TRSP_ERR_int_insrt13(unsigned int uint_insrt13); +int iSetFQ_INT_RIN_TRSP_ERR_fq_rin_trsp_err_sticky(unsigned int ufq_rin_trsp_err_sticky); +int iSetFQ_INT_FIFO1_ERR_fq_fifo1_err(unsigned int ufq_fifo1_err); +int iSetFQ_INT_FIFO1_ERR_int_insrt14(unsigned int uint_insrt14); +int iSetFQ_INT_FIFO1_ERR_fq_fifo1_err_sticky(unsigned int ufq_fifo1_err_sticky); +int iSetFQ_INT_FIFO2_ERR_fq_fifo2_err(unsigned int ufq_fifo2_err); +int iSetFQ_INT_FIFO2_ERR_int_insrt15(unsigned int uint_insrt15); +int iSetFQ_INT_FIFO2_ERR_fq_fifo2_err_sticky(unsigned int ufq_fifo2_err_sticky); +int iSetFQ_CNT48_fq_cnt48(unsigned int ufq_cnt48); +int iSetFQ_CFG_STG_QP_PUSH0_fq_cfg_stg_qp_push0(unsigned int ufq_cfg_stg_qp_push0); +int iSetFQ_CFG_STG_QP_PUSH1_fq_cfg_stg_qp_push1(unsigned int ufq_cfg_stg_qp_push1); +int iSetFQ_CFG_STG_QP_PUSH2_fq_cfg_stg_qp_push2(unsigned int ufq_cfg_stg_qp_push2); +int iSetFQ_DBE_HW_WQE_EN1_cfg_dbe_hw_wqe_en1(unsigned int ucfg_dbe_hw_wqe_en1); +int iSetFQ_DBE_HW_WQE_EN2_cfg_dbe_hw_wqe_en2(unsigned int ucfg_dbe_hw_wqe_en2); +int iSetFQ_DBE_HW_WQE_EN3_cfg_dbe_hw_wqe_en3(unsigned int ucfg_dbe_hw_wqe_en3); +int iSetFQ_DBE_HW_WQE_EN4_cfg_dbe_hw_wqe_en4(unsigned int ucfg_dbe_hw_wqe_en4); +int iSetFQ_DBE_HW_WQE_EN5_cfg_dbe_hw_wqe_en5(unsigned int ucfg_dbe_hw_wqe_en5); +int iSetFQ_DBE_HW_WQE_EN6_cfg_dbe_hw_wqe_en6(unsigned int ucfg_dbe_hw_wqe_en6); +int iSetFQ_DBE_HW_WQE_EN7_cfg_dbe_hw_wqe_en7(unsigned int ucfg_dbe_hw_wqe_en7); +int iSetFQ_DBE_HW_WQE_EN8_cfg_dbe_hw_wqe_en8(unsigned int ucfg_dbe_hw_wqe_en8); +int iSetFQ_DBE_HW_WQE_EN9_cfg_dbe_hw_wqe_en9(unsigned int ucfg_dbe_hw_wqe_en9); +int iSetFQ_DBE_HW_WQE_EN10_cfg_dbe_hw_wqe_en10(unsigned int ucfg_dbe_hw_wqe_en10); +int iSetFQ_DBE_HW_WQE_EN11_cfg_dbe_hw_wqe_en11(unsigned int ucfg_dbe_hw_wqe_en11); +int iSetFQ_DBE_HW_WQE_EN12_cfg_dbe_hw_wqe_en12(unsigned int ucfg_dbe_hw_wqe_en12); +int iSetFQ_DBE_HW_WQE_EN13_cfg_dbe_hw_wqe_en13(unsigned int ucfg_dbe_hw_wqe_en13); +int iSetFQ_DBE_HW_WQE_EN14_cfg_dbe_hw_wqe_en14(unsigned int ucfg_dbe_hw_wqe_en14); +int iSetFQ_DBE_HW_WQE_EN15_cfg_dbe_hw_wqe_en15(unsigned int ucfg_dbe_hw_wqe_en15); +int iSetFQ_CNT49_fq_cnt49(unsigned int ufq_cnt49); +int iSetFQ_CNT50_fq_cnt50(unsigned int ufq_cnt50); +int iSetFQ_CNT51_fq_cnt51(unsigned int ufq_cnt51); +int iSetFQ_CNT52_fq_cnt52(unsigned int ufq_cnt52); +int iSetFQ_CNT53_fq_cnt53(unsigned int ufq_cnt53); +int iSetFQ_CNT54_fq_cnt54(unsigned int ufq_cnt54); +int iSetFQ_CNT55_fq_cnt55(unsigned int ufq_cnt55); +int iSetFQ_CNT56_fq_cnt56(unsigned int ufq_cnt56); +int iSetFQ_CNT57_fq_cnt57(unsigned int ufq_cnt57); +int iSetFQ_CNT58_fq_cnt58(unsigned int ufq_cnt58); +int iSetFQ_CNT59_fq_cnt59(unsigned int ufq_cnt59); +int iSetFQ_CNT60_fq_cnt60(unsigned int ufq_cnt60); +int iSetFQ_CNT61_fq_cnt61(unsigned int ufq_cnt61); +int iSetFQ_CNT62_fq_cnt62(unsigned int ufq_cnt62); +int iSetFQ_CNT63_fq_cnt63(unsigned int ufq_cnt63); +int iSetFQ_CNT64_fq_cnt64(unsigned int ufq_cnt64); +int iSetFQ_CNT65_fq_cnt65(unsigned int ufq_cnt65); +int iSetFQ_CNT66_fq_cnt66(unsigned int ufq_cnt66); +int iSetFQ_CNT67_fq_cnt67(unsigned int ufq_cnt67); +int iSetFQ_CNT68_fq_cnt68(unsigned int ufq_cnt68); +int iSetFQ_CNT69_fq_cnt69(unsigned int ufq_cnt69); +int iSetFQ_CNT70_fq_cnt70(unsigned int ufq_cnt70); +int iSetFQ_CNT71_fq_cnt71(unsigned int ufq_cnt71); +int iSetFQ_CNT72_fq_cnt72(unsigned int ufq_cnt72); +int iSetFQ_CNT73_fq_cnt73(unsigned int ufq_cnt73); +int iSetFQ_CNT74_fq_cnt74(unsigned int ufq_cnt74); +int iSetFQ_CNT75_fq_cnt75(unsigned int ufq_cnt75); +int iSetFQ_CNT76_fq_cnt76(unsigned int ufq_cnt76); +int iSetFQ_CNT77_fq_cnt77(unsigned int ufq_cnt77); +int iSetFQ_CNT78_fq_cnt78(unsigned int ufq_cnt78); +int iSetFQ_CNT79_fq_cnt79(unsigned int ufq_cnt79); +int iSetFQ_CNT80_fq_cnt80(unsigned int ufq_cnt80); +int iSetFQ_CNT81_fq_cnt81(unsigned int ufq_cnt81); +int iSetFQ_CNT82_fq_cnt82(unsigned int ufq_cnt82); +int iSetFQ_CNT83_fq_cnt83(unsigned int ufq_cnt83); +int iSetFQ_CNT84_fq_cnt84(unsigned int ufq_cnt84); +int iSetFQ_CNT85_fq_cnt85(unsigned int ufq_cnt85); +int iSetFQ_CNT86_fq_cnt86(unsigned int ufq_cnt86); +int iSetFQ_CNT87_fq_cnt87(unsigned int ufq_cnt87); +int iSetFQ_CNT88_fq_cnt88(unsigned int ufq_cnt88); +int iSetFQ_CNT89_fq_cnt89(unsigned int ufq_cnt89); +int iSetFQ_CNT90_fq_cnt90(unsigned int ufq_cnt90); +int iSetFQ_CNT91_fq_cnt91(unsigned int ufq_cnt91); +int iSetFQ_CNT92_fq_cnt92(unsigned int ufq_cnt92); +int iSetFQ_CNT93_fq_cnt93(unsigned int ufq_cnt93); +int iSetFQ_CNT94_fq_cnt94(unsigned int ufq_cnt94); +int iSetFQ_CNT95_fq_cnt95(unsigned int ufq_cnt95); +int iSetFQ_CNT96_fq_cnt96(unsigned int ufq_cnt96); +int iSetFQ_CNT97_fq_cnt97(unsigned int ufq_cnt97); +int iSetFQ_CNT98_fq_cnt98(unsigned int ufq_cnt98); +int iSetFQ_CNT99_fq_cnt99(unsigned int ufq_cnt99); +int iSetFQ_CNT100_fq_cnt100(unsigned int ufq_cnt100); +int iSetFQ_CNT101_fq_cnt101(unsigned int ufq_cnt101); +int iSetFQ_CNT102_fq_cnt102(unsigned int ufq_cnt102); +int iSetFQ_CNT103_fq_cnt103(unsigned int ufq_cnt103); +int iSetFQ_CNT104_fq_cnt104(unsigned int ufq_cnt104); +int iSetFQ_CNT105_fq_cnt105(unsigned int ufq_cnt105); +int iSetFQ_CNT106_fq_cnt106(unsigned int ufq_cnt106); +int iSetFQ_CNT107_fq_cnt107(unsigned int ufq_cnt107); +int iSetFQ_CNT108_fq_cnt108(unsigned int ufq_cnt108); +int iSetFQ_CNT109_fq_cnt109(unsigned int ufq_cnt109); +int iSetFQ_CNT110_fq_cnt110(unsigned int ufq_cnt110); +int iSetFQ_CNT111_fq_cnt111(unsigned int ufq_cnt111); +int iSetFQ_CNT112_fq_cnt112(unsigned int ufq_cnt112); +int iSetFQ_CNT113_fq_cnt113(unsigned int ufq_cnt113); +int iSetFQ_CNT114_fq_cnt114(unsigned int ufq_cnt114); +int iSetFQ_CNT115_fq_cnt115(unsigned int ufq_cnt115); +int iSetFQ_CNT116_fq_cnt116(unsigned int ufq_cnt116); +int iSetFQ_CNT117_fq_cnt117(unsigned int ufq_cnt117); +int iSetFQ_CNT118_fq_cnt118(unsigned int ufq_cnt118); +int iSetFQ_CNT119_fq_cnt119(unsigned int ufq_cnt119); +int iSetFQ_CNT120_fq_cnt120(unsigned int ufq_cnt120); +int iSetFQ_CNT121_fq_cnt121(unsigned int ufq_cnt121); +int iSetFQ_CNT122_fq_cnt122(unsigned int ufq_cnt122); +int iSetFQ_CNT123_fq_cnt123(unsigned int ufq_cnt123); +int iSetFQ_CNT124_fq_cnt124(unsigned int ufq_cnt124); +int iSetFQ_CNT125_fq_cnt125(unsigned int ufq_cnt125); +int iSetFQ_CNT126_fq_cnt126(unsigned int ufq_cnt126); +int iSetFQ_CNT127_fq_cnt127(unsigned int ufq_cnt127); +int iSetFQ_CNT128_fq_cnt128(unsigned int ufq_cnt128); +int iSetFQ_CNT129_fq_cnt129(unsigned int ufq_cnt129); +int iSetFQ_CNT130_fq_cnt130(unsigned int ufq_cnt130); +int iSetFQ_CNT131_fq_cnt131(unsigned int ufq_cnt131); +int iSetFQ_CNT132_fq_cnt132(unsigned int ufq_cnt132); +int iSetFQ_CNT133_fq_cnt133(unsigned int ufq_cnt133); +int iSetFQ_CNT134_fq_cnt134(unsigned int ufq_cnt134); +int iSetFQ_CNT135_fq_cnt135(unsigned int ufq_cnt135); +int iSetFQ_CNT136_fq_cnt136(unsigned int ufq_cnt136); +int iSetFQ_CNT137_fq_cnt137(unsigned int ufq_cnt137); +int iSetFQ_CNT138_fq_cnt138(unsigned int ufq_cnt138); +int iSetFQ_CNT139_fq_cnt139(unsigned int ufq_cnt139); +int iSetFQ_CNT140_fq_cnt140(unsigned int ufq_cnt140); +int iSetFQ_CNT141_fq_cnt141(unsigned int ufq_cnt141); +int iSetFQ_CNT142_fq_cnt142(unsigned int ufq_cnt142); +int iSetFQ_CNT143_fq_cnt143(unsigned int ufq_cnt143); +int iSetFQ_CNT144_fq_cnt144(unsigned int ufq_cnt144); +int iSetFQ_CNT145_fq_cnt145(unsigned int ufq_cnt145); +int iSetFQ_CNT146_fq_cnt146(unsigned int ufq_cnt146); +int iSetFQ_CNT147_fq_cnt147(unsigned int ufq_cnt147); +int iSetFQ_CNT148_fq_cnt148(unsigned int ufq_cnt148); +int iSetFQ_CNT149_fq_cnt149(unsigned int ufq_cnt149); +int iSetFQ_CNT150_fq_cnt150(unsigned int ufq_cnt150); +int iSetFQ_CNT151_fq_cnt151(unsigned int ufq_cnt151); +int iSetFQ_CNT152_fq_cnt152(unsigned int ufq_cnt152); +int iSetFQ_CNT153_fq_cnt153(unsigned int ufq_cnt153); +int iSetFQ_CNT154_fq_cnt154(unsigned int ufq_cnt154); +int iSetFQ_CNT155_fq_cnt155(unsigned int ufq_cnt155); +int iSetFQ_CNT156_fq_cnt156(unsigned int ufq_cnt156); +int iSetFQ_CNT157_fq_cnt157(unsigned int ufq_cnt157); +int iSetFQ_CNT158_fq_cnt158(unsigned int ufq_cnt158); +int iSetFQ_CNT159_fq_cnt159(unsigned int ufq_cnt159); +int iSetFQ_CNT160_fq_cnt160(unsigned int ufq_cnt160); +int iSetFQ_CNT161_fq_cnt161(unsigned int ufq_cnt161); +int iSetFQ_CNT162_fq_cnt162(unsigned int ufq_cnt162); +int iSetFQ_CNT163_fq_cnt163(unsigned int ufq_cnt163); +int iSetFQ_CNT164_fq_cnt164(unsigned int ufq_cnt164); +int iSetFQ_CNT165_fq_cnt165(unsigned int ufq_cnt165); +int iSetFQ_CNT166_fq_cnt166(unsigned int ufq_cnt166); +int iSetFQ_CNT167_fq_cnt167(unsigned int ufq_cnt167); +int iSetFQ_CNT168_fq_cnt168(unsigned int ufq_cnt168); +int iSetFQ_CNT169_fq_cnt169(unsigned int ufq_cnt169); +int iSetFQ_CNT170_fq_cnt170(unsigned int ufq_cnt170); +int iSetFQ_CNT171_fq_cnt171(unsigned int ufq_cnt171); +int iSetFQ_CNT172_fq_cnt172(unsigned int ufq_cnt172); +int iSetFQ_CNT173_fq_cnt173(unsigned int ufq_cnt173); +int iSetFQ_CNT174_fq_cnt174(unsigned int ufq_cnt174); +int iSetFQ_CNT175_fq_cnt175(unsigned int ufq_cnt175); +int iSetFQ_CNT176_fq_cnt176(unsigned int ufq_cnt176); +int iSetFQ_CNT177_fq_cnt177(unsigned int ufq_cnt177); +int iSetFQ_CNT178_fq_cnt178(unsigned int ufq_cnt178); +int iSetFQ_CNT179_fq_cnt179(unsigned int ufq_cnt179); +int iSetFQ_CNT180_fq_cnt180(unsigned int ufq_cnt180); +int iSetFQ_CNT181_fq_cnt181(unsigned int ufq_cnt181); +int iSetFQ_CNT182_fq_cnt182(unsigned int ufq_cnt182); +int iSetFQ_CNT183_fq_cnt183(unsigned int ufq_cnt183); +int iSetFQ_CNT184_fq_cnt184(unsigned int ufq_cnt184); +int iSetFQ_CNT185_fq_cnt185(unsigned int ufq_cnt185); +int iSetFQ_CNT186_fq_cnt186(unsigned int ufq_cnt186); +int iSetFQ_CNT187_fq_cnt187(unsigned int ufq_cnt187); +int iSetFQ_CNT188_fq_cnt188(unsigned int ufq_cnt188); +int iSetFQ_CNT189_fq_cnt189(unsigned int ufq_cnt189); +int iSetFQ_CNT190_fq_cnt190(unsigned int ufq_cnt190); +int iSetFQ_CNT191_fq_cnt191(unsigned int ufq_cnt191); +int iSetFQ_CNT192_fq_cnt192(unsigned int ufq_cnt192); +int iSetFQ_CNT193_fq_cnt193(unsigned int ufq_cnt193); +int iSetFQ_CNT194_fq_cnt194(unsigned int ufq_cnt194); +int iSetFQ_CNT195_fq_cnt195(unsigned int ufq_cnt195); +int iSetFQ_CNT196_fq_cnt196(unsigned int ufq_cnt196); +int iSetFQ_CNT197_fq_cnt197(unsigned int ufq_cnt197); +int iSetFQ_CNT198_fq_cnt198(unsigned int ufq_cnt198); +int iSetFQ_CNT199_fq_cnt199(unsigned int ufq_cnt199); +int iSetFQ_CNT200_fq_cnt200(unsigned int ufq_cnt200); +int iSetFQ_CNT201_fq_cnt201(unsigned int ufq_cnt201); +int iSetFQ_CNT202_fq_cnt202(unsigned int ufq_cnt202); +int iSetFQ_CNT203_fq_cnt203(unsigned int ufq_cnt203); +int iSetFQ_CNT204_fq_cnt204(unsigned int ufq_cnt204); +int iSetFQ_CNT205_fq_cnt205(unsigned int ufq_cnt205); +int iSetFQ_CNT206_fq_cnt206(unsigned int ufq_cnt206); +int iSetFQ_CNT207_fq_cnt207(unsigned int ufq_cnt207); +int iSetFQ_CNT208_fq_cnt208(unsigned int ufq_cnt208); +int iSetFQ_CNT209_fq_cnt209(unsigned int ufq_cnt209); +int iSetFQ_CNT210_fq_cnt210(unsigned int ufq_cnt210); +int iSetFQ_CNT211_fq_cnt211(unsigned int ufq_cnt211); +int iSetFQ_CNT212_fq_cnt212(unsigned int ufq_cnt212); +int iSetFQ_CNT213_fq_cnt213(unsigned int ufq_cnt213); +int iSetFQ_CNT214_fq_cnt214(unsigned int ufq_cnt214); +int iSetFQ_CNT215_fq_cnt215(unsigned int ufq_cnt215); +int iSetFQ_CNT216_fq_cnt216(unsigned int ufq_cnt216); +int iSetFQ_CNT217_fq_cnt217(unsigned int ufq_cnt217); +int iSetFQ_CNT218_fq_cnt218(unsigned int ufq_cnt218); +int iSetFQ_CNT219_fq_cnt219(unsigned int ufq_cnt219); +int iSetFQ_CNT220_fq_cnt220(unsigned int ufq_cnt220); +int iSetFQ_CNT221_fq_cnt221(unsigned int ufq_cnt221); +int iSetFQ_CNT222_fq_cnt222(unsigned int ufq_cnt222); +int iSetFQ_CNT223_fq_cnt223(unsigned int ufq_cnt223); +int iSetFQ_CNT224_fq_cnt224(unsigned int ufq_cnt224); +int iSetFQ_RXPSH_CID_CTL_cfg_fq_rxpsh_cid_ctl(unsigned int ucfg_fq_rxpsh_cid_ctl); +int iSetFQ_ROCE_DB_ODR_CTL1_cfg_fq_roce_db_odr_ctl1(unsigned int ucfg_fq_roce_db_odr_ctl1); +int iSetFQ_ROCE_DB_ODR_CTL2_cfg_fq_roce_db_odr_ctl2(unsigned int ucfg_fq_roce_db_odr_ctl2); +int iSetFQ_NORM_NIC_ODR_CTL1_cfg_fq_norm_nic_odr_ctl1(unsigned int ucfg_fq_norm_nic_odr_ctl1); +int iSetFQ_NORM_NIC_ODR_CTL2_cfg_fq_norm_nic_odr_ctl2(unsigned int ucfg_fq_norm_nic_odr_ctl2); +int iSetFQ_ODR_FLIT256_CTL1_cfg_fq_odr_flit256_ctl1(unsigned int ucfg_fq_odr_flit256_ctl1); +int iSetFQ_ODR_FLIT256_CTL2_cfg_fq_odr_flit256_ctl2(unsigned int ucfg_fq_odr_flit256_ctl2); +int iSetFQ_ODR_FLIT256_CTL3_cfg_fq_odr_flit256_ctl3(unsigned int ucfg_fq_odr_flit256_ctl3); +int iSetFQ_ODR_FLIT256_CTL4_cfg_fq_odr_flit256_ctl4(unsigned int ucfg_fq_odr_flit256_ctl4); +int iSetFQ_ODR_STYPE_CID2QID_EN_cfg_fq_odr_stype_cid2qid_en(unsigned int ucfg_fq_odr_stype_cid2qid_en); +int iSetFQ_CNT225_fq_cnt225(unsigned int ufq_cnt225); +int iSetFQ_CNT226_fq_cnt226(unsigned int ufq_cnt226); +int iSetFQ_CNT227_fq_cnt227(unsigned int ufq_cnt227); +int iSetFQ_CNT228_fq_cnt228(unsigned int ufq_cnt228); +int iSetFQ_CNT229_fq_cnt229(unsigned int ufq_cnt229); +int iSetFQ_CNT230_fq_cnt230(unsigned int ufq_cnt230); +int iSetFQ_CNT231_fq_cnt231(unsigned int ufq_cnt231); +int iSetFQ_CNT232_fq_cnt232(unsigned int ufq_cnt232); +int iSetFQ_CNT233_fq_cnt233(unsigned int ufq_cnt233); +int iSetFQ_CNT234_fq_cnt234(unsigned int ufq_cnt234); +int iSetFQ_CNT235_fq_cnt235(unsigned int ufq_cnt235); +int iSetFQ_CNT236_fq_cnt236(unsigned int ufq_cnt236); +int iSetFQ_CNT237_fq_cnt237(unsigned int ufq_cnt237); +int iSetFQ_CNT238_fq_cnt238(unsigned int ufq_cnt238); +int iSetFQ_CNT239_fq_cnt239(unsigned int ufq_cnt239); +int iSetFQ_CNT240_fq_cnt240(unsigned int ufq_cnt240); +int iSetFQ_CNT241_fq_cnt241(unsigned int ufq_cnt241); + + +#endif // STLFQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlfq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlfq_reg_offset.h new file mode 100644 index 000000000..57ddd8270 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlfq_reg_offset.h @@ -0,0 +1,535 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stlfq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:11:44 Create file +// ****************************************************************************** + +#ifndef STLFQ_REG_OFFSET_H +#define STLFQ_REG_OFFSET_H + +/* QU_STLFQ_CSR Base address of Module's Register */ +#define CSR_QU_STLFQ_CSR_BASE (0x4000) + +/* **************************************************************************** */ +/* QU_STLFQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_STLFQ_CSR_FQ_MODE_REG_REG (CSR_QU_STLFQ_CSR_BASE + 0x0) /* FQ operation mode register */ +#define CSR_QU_STLFQ_CSR_FQ_INITCTAB_START_REG (CSR_QU_STLFQ_CSR_BASE + 0x4) /* FQ initialization start control */ +#define CSR_QU_STLFQ_CSR_FQ_INITCTAB_ST_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x8) /* FQ configurable tables' hw initilization done state. */ +#define CSR_QU_STLFQ_CSR_FQ_INIT_LOGIC_ST_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0xC) /* FQ non-configuration memory's hw initilization done state. */ +#define CSR_QU_STLFQ_CSR_FQ_INT_VECTOR_REG (CSR_QU_STLFQ_CSR_BASE + 0x10) /* FQ interrupt vector */ +#define CSR_QU_STLFQ_CSR_FQ_INT_REG (CSR_QU_STLFQ_CSR_BASE + 0x14) /* FQ_INT */ +#define CSR_QU_STLFQ_CSR_FQ_INT_MASK_REG (CSR_QU_STLFQ_CSR_BASE + 0x18) /* 中断屏蔽 */ +#define CSR_QU_STLFQ_CSR_FQ_INT_MEM_ERR_2B_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x1C) /* FQ uncorrected memory error(2b) registers.(fatal error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_OEID_AGED_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x20) /* FQ aged oeid error register.(severe error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_SCAN_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x24) /* Abnormal flow queue scan register.(fatal error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_FCMD_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x28) /* Abnormal commands status in fcell register.(Normal error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_DSP_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x2C) /* Abnormal commands ("dispath and cpb ack pair status" or "abnormal Tile cmds") \ + register.(Normal error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_PFH_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + \ + 0x30) /* FQ fetch qcntx (via qcmc) from smf timeout or error response status register.（severe error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_DBE_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + \ + 0x34) /* DBE(iq) fetch (via qcmc) qcntx from smf timeout or error response status register.(severe error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_QRSC_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x38) /* Abnormal qpc resource status register.(severe error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_BUF_UF_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + \ + 0x3C) /* uCode allocated buffer abnormal underflow for dispatch or overflow when allocation.(severe error) */ +#define CSR_QU_STLFQ_CSR_FQ_INT_FIFO0_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x40) /* FQ fifo abnoraml register.(severe error) */ +#define CSR_QU_STLFQ_CSR_FQ_INDRECT_CTRL_REG (CSR_QU_STLFQ_CSR_BASE + 0x44) /* FQ间接寻址控制寄存器 */ +#define CSR_QU_STLFQ_CSR_FQ_INDRECT_TIMEOUT_REG (CSR_QU_STLFQ_CSR_BASE + 0x48) /* FQ间接寻址Timeout水线配置 */ +#define CSR_QU_STLFQ_CSR_FQ_INDRECT_DAT0_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x4C) /* FQ memory indirect access write data0 or read data0. */ +#define CSR_QU_STLFQ_CSR_FQ_INDRECT_DAT1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x50) /* FQ memory indirect access write data0 or read data1. */ +#define CSR_QU_STLFQ_CSR_FQ_QCNTX_MODE_REG (CSR_QU_STLFQ_CSR_BASE + 0x54) /* FQ_QCNTX_MODE */ +#define CSR_QU_STLFQ_CSR_FQ_AGE_PERIOD_REG_REG (CSR_QU_STLFQ_CSR_BASE + 0x58) /* Aging period configuration */ +#define CSR_QU_STLFQ_CSR_STFFQ_DBE_HW_PFH_CFG_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x5C) /* FQ pre-fetch qcntx for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0x60) /* Timer trigger status register. */ +#define CSR_QU_STLFQ_CSR_FQ_CPB_CFG_REG (CSR_QU_STLFQ_CSR_BASE + 0x64) /* CPB packet buffer related configuration */ +#define CSR_QU_STLFQ_CSR_FQ_CRDT_2TLSMF_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0x68) /* Credits Values status */ +#define CSR_QU_STLFQ_CSR_FQ_CRDT_2TLSMF_REG_REG (CSR_QU_STLFQ_CSR_BASE + 0x6C) /* Default credits to SMF/Tiels. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x70) /* FQ counter sets control congifuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT0_REG (CSR_QU_STLFQ_CSR_BASE + 0x74) /* FQ counter 0 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT1_REG (CSR_QU_STLFQ_CSR_BASE + 0x78) /* FQ counter 1 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT2_REG (CSR_QU_STLFQ_CSR_BASE + 0x7C) /* FQ counter 2 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT3_REG (CSR_QU_STLFQ_CSR_BASE + 0x80) /* FQ counter 3 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT4_REG (CSR_QU_STLFQ_CSR_BASE + 0x84) /* FQ counter 4 */ +#define CSR_QU_STLFQ_CSR_FQ_SNAPSHOT_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x88) /* FQ snapshot control configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_SNAPSHOT_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0x8C) /* FQ snapshot status. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x90) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_CFG_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x94) /* FQ pre-fetch qpc/wqe for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_FIFO_GAP_CFG_REG (CSR_QU_STLFQ_CSR_BASE + 0x98) /* FQ fifo almost full gap configuration. \ + */ +#define CSR_QU_STLFQ_CSR_FQ_HIS_FIFO_CNT0_REG (CSR_QU_STLFQ_CSR_BASE + 0x9C) /* fifo's occupied counter0. */ +#define CSR_QU_STLFQ_CSR_FQ_HIS_FIFO_CNT1_REG (CSR_QU_STLFQ_CSR_BASE + 0xA0) /* fifo's occupied counter1. */ +#define CSR_QU_STLFQ_CSR_FQ_FIFO_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0xA4) /* FQ Fifos status */ +#define CSR_QU_STLFQ_CSR_FQ_HIS_FIFO_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0xA8) /* FQ Fifos history full status */ +#define CSR_QU_STLFQ_CSR_FQ_MEM_CTRL_REG (CSR_QU_STLFQ_CSR_BASE + 0xAC) /* Memory controls parameters setting. */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_EP2HOST_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0xB0) /* host side,host ep to host id map configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_PCAR_CFG_REG (CSR_QU_STLFQ_CSR_BASE + 0xB4) /* Post car configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT5_REG (CSR_QU_STLFQ_CSR_BASE + 0xB8) /* FQ counter 5 */ +#define CSR_QU_STLFQ_CSR_FQ_MOD_REG1_REG (CSR_QU_STLFQ_CSR_BASE + 0xBC) /* FQ mode regitesrs */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_BP_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0xC0) /* FQ inner interface backpressure status \ + */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST_REG (CSR_QU_STLFQ_CSR_BASE + 0xC4) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT6_REG (CSR_QU_STLFQ_CSR_BASE + 0xC8) /* FQ counter 6 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT_CTL1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0xCC) /* Counter7~16 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT7_REG (CSR_QU_STLFQ_CSR_BASE + 0xD0) /* FQ Cnt 7 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT8_REG (CSR_QU_STLFQ_CSR_BASE + 0xD4) /* FQ Cnt 8 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT9_REG (CSR_QU_STLFQ_CSR_BASE + 0xD8) /* FQ Cnt 9 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT10_REG (CSR_QU_STLFQ_CSR_BASE + 0xDC) /* FQ Cnt 10 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT11_REG (CSR_QU_STLFQ_CSR_BASE + 0xE0) /* FQ Cnt 11 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT12_REG (CSR_QU_STLFQ_CSR_BASE + 0xE4) /* FQ Cnt 12 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT13_REG (CSR_QU_STLFQ_CSR_BASE + 0xE8) /* FQ Cnt 13 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT14_REG (CSR_QU_STLFQ_CSR_BASE + 0xEC) /* FQ Cnt 14 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT15_REG (CSR_QU_STLFQ_CSR_BASE + 0xF0) /* FQ Cnt 15 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT16_REG (CSR_QU_STLFQ_CSR_BASE + 0xF4) /* FQ Cnt 16 */ +#define CSR_QU_STLFQ_CSR_FQ_INT_MEM_ERR_1B_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0xF8) /* FQ correctable memory error(1bit) registers.(normal error) */ +#define CSR_QU_STLFQ_CSR_CFG_STYP_TH_FC_EN_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0xFC) /* Stateful thread resource flow control enable configuration. */ +#define CSR_QU_STLFQ_CSR_CFG_ZERO_ESCH_LEN_REG (CSR_QU_STLFQ_CSR_BASE + 0x100) /* 设置缺省状态下的esch调度length. */ +#define CSR_QU_STLFQ_CSR_CFG_FQ_BUBBLE_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x104) /* 控制插入fq流水线的气泡数量. */ +#define CSR_QU_STLFQ_CSR_CFG_L2DCACHE_BUBBLE_CTL_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x108) /* 控制插入L2DCache流水线的气泡数量. */ +#define CSR_QU_STLFQ_CSR_FQ_DEF_FQ_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x10C) /* Default FQ control register */ +#define CSR_QU_STLFQ_CSR_FQ_SMF_LDBCTL_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x110) /* Default STFFQ to SMF load balance control register */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_EP2HOST_H2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x114) /* host side,host ep to host id map configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_PREFETCH_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x118) /* fq预取wqe和qpc的配置寄存器. */ +#define CSR_QU_STLFQ_CSR_FQ_LATENCY_CFG_REG (CSR_QU_STLFQ_CSR_BASE + 0x11C) /* ICDQ的时延采样DFX配置 */ +#define CSR_QU_STLFQ_CSR_FQ_LATENCY_STA_REG (CSR_QU_STLFQ_CSR_BASE + 0x120) /* fq的时延采样DFX状态 */ +#define CSR_QU_STLFQ_CSR_FQ_SAMPLE_TMR_REG (CSR_QU_STLFQ_CSR_BASE + 0x124) /* fq的时延采样DFX时间 */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_FAKE_VF_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x128) /* fake vfid模式下的控制寄存器。 */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_BPS_DLY_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x12C) /* fq低延时bypass控制寄存器。 */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_OTSD_BASE_CTL_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x130) /* qu的otsd的起始编号。Qu接口传给fq的otsd需要减去这个base值，Fq内部只存3bit \ + otsd，fq还回给tile的otsd需要再加上这个base值。 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT_CTL2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x134) /* Counter17~26 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT17_REG (CSR_QU_STLFQ_CSR_BASE + 0x138) /* FQ Cnt 17 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT18_REG (CSR_QU_STLFQ_CSR_BASE + 0x13C) /* FQ Cnt 18 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT19_REG (CSR_QU_STLFQ_CSR_BASE + 0x140) /* FQ Cnt 19 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT20_REG (CSR_QU_STLFQ_CSR_BASE + 0x144) /* FQ Cnt 20 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT21_REG (CSR_QU_STLFQ_CSR_BASE + 0x148) /* FQ Cnt 21 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT22_REG (CSR_QU_STLFQ_CSR_BASE + 0x14C) /* FQ Cnt 22 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT23_REG (CSR_QU_STLFQ_CSR_BASE + 0x150) /* FQ Cnt 23 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT24_REG (CSR_QU_STLFQ_CSR_BASE + 0x154) /* FQ Cnt 24 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT25_REG (CSR_QU_STLFQ_CSR_BASE + 0x158) /* FQ Cnt 25 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT26_REG (CSR_QU_STLFQ_CSR_BASE + 0x15C) /* FQ Cnt 26 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT_CTL3_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x160) /* Counter27~36 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT27_REG (CSR_QU_STLFQ_CSR_BASE + 0x164) /* FQ Cnt 27 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT28_REG (CSR_QU_STLFQ_CSR_BASE + 0x168) /* FQ Cnt 28 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT29_REG (CSR_QU_STLFQ_CSR_BASE + 0x16C) /* FQ Cnt 29 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT30_REG (CSR_QU_STLFQ_CSR_BASE + 0x170) /* FQ Cnt 30 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT31_REG (CSR_QU_STLFQ_CSR_BASE + 0x174) /* FQ Cnt 31 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT32_REG (CSR_QU_STLFQ_CSR_BASE + 0x178) /* FQ Cnt 32 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT33_REG (CSR_QU_STLFQ_CSR_BASE + 0x17C) /* FQ Cnt 33 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT34_REG (CSR_QU_STLFQ_CSR_BASE + 0x180) /* FQ Cnt 34 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT35_REG (CSR_QU_STLFQ_CSR_BASE + 0x184) /* FQ Cnt 35 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT36_REG (CSR_QU_STLFQ_CSR_BASE + 0x188) /* FQ Cnt 36 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT_CTL4_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x18C) /* Counter27~36 enable.1,counter enable.0,counter disable.Bit [i] : counter [7+i] \ + enable configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT37_REG (CSR_QU_STLFQ_CSR_BASE + 0x190) /* FQ Cnt 37 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT38_REG (CSR_QU_STLFQ_CSR_BASE + 0x194) /* FQ Cnt 38 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT39_REG (CSR_QU_STLFQ_CSR_BASE + 0x198) /* FQ Cnt 39 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT40_REG (CSR_QU_STLFQ_CSR_BASE + 0x19C) /* FQ Cnt 40 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT41_REG (CSR_QU_STLFQ_CSR_BASE + 0x1A0) /* FQ Cnt 41 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT42_REG (CSR_QU_STLFQ_CSR_BASE + 0x1A4) /* FQ Cnt 42 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT43_REG (CSR_QU_STLFQ_CSR_BASE + 0x1A8) /* FQ Cnt 43 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT44_REG (CSR_QU_STLFQ_CSR_BASE + 0x1AC) /* FQ Cnt 44 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT45_REG (CSR_QU_STLFQ_CSR_BASE + 0x1B0) /* FQ Cnt 45 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT46_REG (CSR_QU_STLFQ_CSR_BASE + 0x1B4) /* FQ Cnt 46 */ +#define CSR_QU_STLFQ_CSR_FQ_QU2SMF_TMR_DLY_REG (CSR_QU_STLFQ_CSR_BASE + 0x1B8) /* 控制fq送给smf的时戳 */ +#define CSR_QU_STLFQ_CSR_FQ_MAGIC_BOX_CTL_REG (CSR_QU_STLFQ_CSR_BASE + 0x1BC) /* fq的magic box的控制寄存器 */ +#define CSR_QU_STLFQ_CSR_FQ_MGBX_SRV2HASH_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x1C0) /* serve type的hash属性，用于magic box的输入。 */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST1_REG (CSR_QU_STLFQ_CSR_BASE + 0x1C4) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST2_REG (CSR_QU_STLFQ_CSR_BASE + 0x1C8) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST3_REG (CSR_QU_STLFQ_CSR_BASE + 0x1CC) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST4_REG (CSR_QU_STLFQ_CSR_BASE + 0x1D0) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST5_REG (CSR_QU_STLFQ_CSR_BASE + 0x1D4) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST6_REG (CSR_QU_STLFQ_CSR_BASE + 0x1D8) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST7_REG (CSR_QU_STLFQ_CSR_BASE + 0x1DC) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST8_REG (CSR_QU_STLFQ_CSR_BASE + 0x1E0) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST9_REG (CSR_QU_STLFQ_CSR_BASE + 0x1E4) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST10_REG (CSR_QU_STLFQ_CSR_BASE + 0x1E8) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST11_REG (CSR_QU_STLFQ_CSR_BASE + 0x1EC) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST12_REG (CSR_QU_STLFQ_CSR_BASE + 0x1F0) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST13_REG (CSR_QU_STLFQ_CSR_BASE + 0x1F4) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST14_REG (CSR_QU_STLFQ_CSR_BASE + 0x1F8) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST15_REG (CSR_QU_STLFQ_CSR_BASE + 0x1FC) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST16_REG (CSR_QU_STLFQ_CSR_BASE + 0x200) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST17_REG (CSR_QU_STLFQ_CSR_BASE + 0x204) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST18_REG (CSR_QU_STLFQ_CSR_BASE + 0x208) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST19_REG (CSR_QU_STLFQ_CSR_BASE + 0x20C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST20_REG (CSR_QU_STLFQ_CSR_BASE + 0x210) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST21_REG (CSR_QU_STLFQ_CSR_BASE + 0x214) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST22_REG (CSR_QU_STLFQ_CSR_BASE + 0x218) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST23_REG (CSR_QU_STLFQ_CSR_BASE + 0x21C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST24_REG (CSR_QU_STLFQ_CSR_BASE + 0x220) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST25_REG (CSR_QU_STLFQ_CSR_BASE + 0x224) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST26_REG (CSR_QU_STLFQ_CSR_BASE + 0x228) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST27_REG (CSR_QU_STLFQ_CSR_BASE + 0x22C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST28_REG (CSR_QU_STLFQ_CSR_BASE + 0x230) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST29_REG (CSR_QU_STLFQ_CSR_BASE + 0x234) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST30_REG (CSR_QU_STLFQ_CSR_BASE + 0x238) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST31_REG (CSR_QU_STLFQ_CSR_BASE + 0x23C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST32_REG (CSR_QU_STLFQ_CSR_BASE + 0x240) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST33_REG (CSR_QU_STLFQ_CSR_BASE + 0x244) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST34_REG (CSR_QU_STLFQ_CSR_BASE + 0x248) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST35_REG (CSR_QU_STLFQ_CSR_BASE + 0x24C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST36_REG (CSR_QU_STLFQ_CSR_BASE + 0x250) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST37_REG (CSR_QU_STLFQ_CSR_BASE + 0x254) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST38_REG (CSR_QU_STLFQ_CSR_BASE + 0x258) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST39_REG (CSR_QU_STLFQ_CSR_BASE + 0x25C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST40_REG (CSR_QU_STLFQ_CSR_BASE + 0x260) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST41_REG (CSR_QU_STLFQ_CSR_BASE + 0x264) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST42_REG (CSR_QU_STLFQ_CSR_BASE + 0x26C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST43_REG (CSR_QU_STLFQ_CSR_BASE + 0x270) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST44_REG (CSR_QU_STLFQ_CSR_BASE + 0x274) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST45_REG (CSR_QU_STLFQ_CSR_BASE + 0x278) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST46_REG (CSR_QU_STLFQ_CSR_BASE + 0x27C) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST47_REG (CSR_QU_STLFQ_CSR_BASE + 0x280) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_INNER_MON_ST48_REG (CSR_QU_STLFQ_CSR_BASE + 0x284) /* FQ innser status monitor bus. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT47_REG (CSR_QU_STLFQ_CSR_BASE + 0x288) /* FQ Cnt 47 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_RQST_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x28C) /* STF FQ的ROU的RQST fifo0的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_RSP_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x290) /* STF FQ的ROU的RSP fifo0的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_RSP_FIFO1_REG (CSR_QU_STLFQ_CSR_BASE + 0x298) /* STF FQ的ROU的RSP fifo1的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_TMRODR_FIFO0_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x29C) /* STF FQ的TMR和ODR的ROU的RQST fifo0的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_TMRODR_FIFO1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x2A0) /* STF FQ的TMR和ODR的ROU的RQST fifo1的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_TMRODR_FIFO2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x2A4) /* STF FQ的TMR和ODR的ROU的RQST fifo2的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_ROU_TMRODR_FIFO3_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x2A8) /* STF FQ的TMR和ODR的ROU的RQST fifo3的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_RIN_RQST_FIFO_REG (CSR_QU_STLFQ_CSR_BASE + 0x2BC) /* STFFQ的RIN的RQST fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_RIN_RSP_FIFO_REG (CSR_QU_STLFQ_CSR_BASE + 0x2C0) /* STF FQ的RIN的RSP fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_SMF_RSP_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x2D4) /* FQ的QPC Ring的SMF RSP fifo0的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_SMF_RSP_FIFO1_REG (CSR_QU_STLFQ_CSR_BASE + 0x2D8) /* FQ的QPC Ring的SMF RSP fifo1的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_TL0_CMD_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x2DC) /* FQ的Tile0的CMD fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_TL0_EXTCMD_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x2E0) /* FQ的Tile0的EXTCMD fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_TL1_CMD_FIFO1_REG (CSR_QU_STLFQ_CSR_BASE + 0x2E4) /* FQ的Tile1的CMD fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_TL1_EXTCMD_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x2E8) /* FQ的Tile1的EXTCMD fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_FQ2OQ_FCNP_FIFO_REG (CSR_QU_STLFQ_CSR_BASE + 0x2EC) /* FQ的FQ2OQ的FCNP fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_OQ2FQ_FCNP_FIFO_REG (CSR_QU_STLFQ_CSR_BASE + 0x2F0) /* FQ的OQ2FQ的FCNP fifo的状态 */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO0_REG (CSR_QU_STLFQ_CSR_BASE + 0x2F4) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO1_REG (CSR_QU_STLFQ_CSR_BASE + 0x2F8) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO2_REG (CSR_QU_STLFQ_CSR_BASE + 0x2FC) /* FQ的TIMER FIRE API的RSP fifo2的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO3_REG (CSR_QU_STLFQ_CSR_BASE + 0x300) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO4_REG (CSR_QU_STLFQ_CSR_BASE + 0x304) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO5_REG (CSR_QU_STLFQ_CSR_BASE + 0x308) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO6_REG (CSR_QU_STLFQ_CSR_BASE + 0x30C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO7_REG (CSR_QU_STLFQ_CSR_BASE + 0x310) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO8_REG (CSR_QU_STLFQ_CSR_BASE + 0x314) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO9_REG (CSR_QU_STLFQ_CSR_BASE + 0x318) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO10_REG (CSR_QU_STLFQ_CSR_BASE + 0x31C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO11_REG (CSR_QU_STLFQ_CSR_BASE + 0x320) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO12_REG (CSR_QU_STLFQ_CSR_BASE + 0x324) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO13_REG (CSR_QU_STLFQ_CSR_BASE + 0x328) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO14_REG (CSR_QU_STLFQ_CSR_BASE + 0x32C) /* FQ的TIMER FIRE API的RSP fifo0的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_TMR_RSP_FIFO15_REG (CSR_QU_STLFQ_CSR_BASE + 0x330) /* FQ的TIMER FIRE API的RSP fifo1的状态 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_INT_RIN_RQST_ERR_REG (CSR_QU_STLFQ_CSR_BASE + 0x334) /* fq的ring进来的请求数据发现错误。 \ + */ +#define CSR_QU_STLFQ_CSR_FQ_INT_RIN_RSP_ERR_REG (CSR_QU_STLFQ_CSR_BASE + 0x338) /* fq的ring进来的响应数据发现错误。 */ +#define CSR_QU_STLFQ_CSR_FQ_INT_RIN_TRSP_ERR_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x33C) /* fq的ring进来的timer fire的响应数据发现E1错误。 */ +#define CSR_QU_STLFQ_CSR_FQ_INT_FIFO1_ERR_REG (CSR_QU_STLFQ_CSR_BASE + 0x340) /* 新增fifo的err中断。 */ +#define CSR_QU_STLFQ_CSR_FQ_INT_FIFO2_ERR_REG (CSR_QU_STLFQ_CSR_BASE + 0x344) /* 新增fifo的err中断。 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT48_REG (CSR_QU_STLFQ_CSR_BASE + 0x348) /* FQ Cnt 48 */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_STG_QP_PUSH0_REG (CSR_QU_STLFQ_CSR_BASE + 0x34C) /* FQ_cfg_stg_qp_push0 */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_STG_QP_PUSH1_REG (CSR_QU_STLFQ_CSR_BASE + 0x350) /* FQ_cfg_stg_qp_push1 */ +#define CSR_QU_STLFQ_CSR_FQ_CFG_STG_QP_PUSH2_REG (CSR_QU_STLFQ_CSR_BASE + 0x354) /* FQ_cfg_stg_qp_push2 */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x358) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x35C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN3_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x360) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN4_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x364) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN5_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x368) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN6_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x36C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN7_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x370) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN8_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x374) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN9_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x378) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN10_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x37C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN11_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x380) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN12_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x384) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN13_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x388) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN14_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x38C) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_DBE_HW_WQE_EN15_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x390) /* FQ pre-fetch for doorbells configuration. */ +#define CSR_QU_STLFQ_CSR_FQ_CNT49_REG (CSR_QU_STLFQ_CSR_BASE + 0x394) /* FQ Cnt 49 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT50_REG (CSR_QU_STLFQ_CSR_BASE + 0x398) /* FQ Cnt 50 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT51_REG (CSR_QU_STLFQ_CSR_BASE + 0x39C) /* FQ Cnt 51 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT52_REG (CSR_QU_STLFQ_CSR_BASE + 0x3A0) /* FQ Cnt 52 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT53_REG (CSR_QU_STLFQ_CSR_BASE + 0x3A4) /* FQ Cnt 53 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT54_REG (CSR_QU_STLFQ_CSR_BASE + 0x3A8) /* FQ Cnt 54 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT55_REG (CSR_QU_STLFQ_CSR_BASE + 0x3AC) /* FQ Cnt 55 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT56_REG (CSR_QU_STLFQ_CSR_BASE + 0x3B0) /* FQ Cnt 56 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT57_REG (CSR_QU_STLFQ_CSR_BASE + 0x3B4) /* FQ Cnt 57 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT58_REG (CSR_QU_STLFQ_CSR_BASE + 0x3B8) /* FQ Cnt 58 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT59_REG (CSR_QU_STLFQ_CSR_BASE + 0x3BC) /* FQ Cnt 59 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT60_REG (CSR_QU_STLFQ_CSR_BASE + 0x3C0) /* FQ Cnt 60 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT61_REG (CSR_QU_STLFQ_CSR_BASE + 0x3C4) /* FQ Cnt 61 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT62_REG (CSR_QU_STLFQ_CSR_BASE + 0x3C8) /* FQ Cnt 62 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT63_REG (CSR_QU_STLFQ_CSR_BASE + 0x3CC) /* FQ Cnt 63 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT64_REG (CSR_QU_STLFQ_CSR_BASE + 0x3D0) /* FQ Cnt 64 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT65_REG (CSR_QU_STLFQ_CSR_BASE + 0x3D4) /* FQ Cnt 65 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT66_REG (CSR_QU_STLFQ_CSR_BASE + 0x3D8) /* FQ Cnt 66 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT67_REG (CSR_QU_STLFQ_CSR_BASE + 0x3DC) /* FQ Cnt 67 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT68_REG (CSR_QU_STLFQ_CSR_BASE + 0x3E0) /* FQ Cnt 68 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT69_REG (CSR_QU_STLFQ_CSR_BASE + 0x3E4) /* FQ Cnt 69 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT70_REG (CSR_QU_STLFQ_CSR_BASE + 0x3E8) /* FQ Cnt 70 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT71_REG (CSR_QU_STLFQ_CSR_BASE + 0x3EC) /* FQ Cnt 71 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT72_REG (CSR_QU_STLFQ_CSR_BASE + 0x3F0) /* FQ Cnt 72 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT73_REG (CSR_QU_STLFQ_CSR_BASE + 0x3F4) /* FQ Cnt 73 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT74_REG (CSR_QU_STLFQ_CSR_BASE + 0x3F8) /* FQ Cnt 74 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT75_REG (CSR_QU_STLFQ_CSR_BASE + 0x3FC) /* FQ Cnt 75 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT76_REG (CSR_QU_STLFQ_CSR_BASE + 0x400) /* FQ Cnt 76 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT77_REG (CSR_QU_STLFQ_CSR_BASE + 0x404) /* FQ Cnt 77 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT78_REG (CSR_QU_STLFQ_CSR_BASE + 0x408) /* FQ Cnt 78 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT79_REG (CSR_QU_STLFQ_CSR_BASE + 0x40C) /* FQ Cnt 79 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT80_REG (CSR_QU_STLFQ_CSR_BASE + 0x410) /* FQ Cnt 80 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT81_REG (CSR_QU_STLFQ_CSR_BASE + 0x414) /* FQ Cnt 81 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT82_REG (CSR_QU_STLFQ_CSR_BASE + 0x418) /* FQ Cnt 82 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT83_REG (CSR_QU_STLFQ_CSR_BASE + 0x41C) /* FQ Cnt 83 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT84_REG (CSR_QU_STLFQ_CSR_BASE + 0x420) /* FQ Cnt 84 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT85_REG (CSR_QU_STLFQ_CSR_BASE + 0x424) /* FQ Cnt 85 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT86_REG (CSR_QU_STLFQ_CSR_BASE + 0x428) /* FQ Cnt 86 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT87_REG (CSR_QU_STLFQ_CSR_BASE + 0x42C) /* FQ Cnt 87 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT88_REG (CSR_QU_STLFQ_CSR_BASE + 0x430) /* FQ Cnt 88 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT89_REG (CSR_QU_STLFQ_CSR_BASE + 0x434) /* FQ Cnt 89 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT90_REG (CSR_QU_STLFQ_CSR_BASE + 0x438) /* FQ Cnt 90 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT91_REG (CSR_QU_STLFQ_CSR_BASE + 0x43C) /* FQ Cnt 91 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT92_REG (CSR_QU_STLFQ_CSR_BASE + 0x440) /* FQ Cnt 92 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT93_REG (CSR_QU_STLFQ_CSR_BASE + 0x444) /* FQ Cnt 93 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT94_REG (CSR_QU_STLFQ_CSR_BASE + 0x448) /* FQ Cnt 94 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT95_REG (CSR_QU_STLFQ_CSR_BASE + 0x44C) /* FQ Cnt 95 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT96_REG (CSR_QU_STLFQ_CSR_BASE + 0x450) /* FQ Cnt 96 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT97_REG (CSR_QU_STLFQ_CSR_BASE + 0x454) /* FQ Cnt 97 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT98_REG (CSR_QU_STLFQ_CSR_BASE + 0x458) /* FQ Cnt 98 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT99_REG (CSR_QU_STLFQ_CSR_BASE + 0x45C) /* FQ Cnt 99 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT100_REG (CSR_QU_STLFQ_CSR_BASE + 0x460) /* FQ Cnt 100 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT101_REG (CSR_QU_STLFQ_CSR_BASE + 0x464) /* FQ Cnt 101 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT102_REG (CSR_QU_STLFQ_CSR_BASE + 0x468) /* FQ Cnt 102 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT103_REG (CSR_QU_STLFQ_CSR_BASE + 0x46C) /* FQ Cnt 103 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT104_REG (CSR_QU_STLFQ_CSR_BASE + 0x470) /* FQ Cnt 104 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT105_REG (CSR_QU_STLFQ_CSR_BASE + 0x474) /* FQ Cnt 105 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT106_REG (CSR_QU_STLFQ_CSR_BASE + 0x478) /* FQ Cnt 106 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT107_REG (CSR_QU_STLFQ_CSR_BASE + 0x47C) /* FQ Cnt 107 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT108_REG (CSR_QU_STLFQ_CSR_BASE + 0x480) /* FQ Cnt 108 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT109_REG (CSR_QU_STLFQ_CSR_BASE + 0x484) /* FQ Cnt 109 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT110_REG (CSR_QU_STLFQ_CSR_BASE + 0x488) /* FQ Cnt 110 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT111_REG (CSR_QU_STLFQ_CSR_BASE + 0x48C) /* FQ Cnt 111 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT112_REG (CSR_QU_STLFQ_CSR_BASE + 0x490) /* FQ Cnt 112 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT113_REG (CSR_QU_STLFQ_CSR_BASE + 0x494) /* FQ Cnt 113 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT114_REG (CSR_QU_STLFQ_CSR_BASE + 0x498) /* FQ Cnt 114 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT115_REG (CSR_QU_STLFQ_CSR_BASE + 0x49C) /* FQ Cnt 115 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT116_REG (CSR_QU_STLFQ_CSR_BASE + 0x4A0) /* FQ Cnt 116 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT117_REG (CSR_QU_STLFQ_CSR_BASE + 0x4A4) /* FQ Cnt 117 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT118_REG (CSR_QU_STLFQ_CSR_BASE + 0x4A8) /* FQ Cnt 118 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT119_REG (CSR_QU_STLFQ_CSR_BASE + 0x4AC) /* FQ Cnt 119 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT120_REG (CSR_QU_STLFQ_CSR_BASE + 0x4B0) /* FQ Cnt 120 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT121_REG (CSR_QU_STLFQ_CSR_BASE + 0x4B4) /* FQ Cnt 121 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT122_REG (CSR_QU_STLFQ_CSR_BASE + 0x4B8) /* FQ Cnt 122 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT123_REG (CSR_QU_STLFQ_CSR_BASE + 0x4BC) /* FQ Cnt 123 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT124_REG (CSR_QU_STLFQ_CSR_BASE + 0x4C0) /* FQ Cnt 124 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT125_REG (CSR_QU_STLFQ_CSR_BASE + 0x4C4) /* FQ Cnt 125 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT126_REG (CSR_QU_STLFQ_CSR_BASE + 0x4C8) /* FQ Cnt 126 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT127_REG (CSR_QU_STLFQ_CSR_BASE + 0x4CC) /* FQ Cnt 127 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT128_REG (CSR_QU_STLFQ_CSR_BASE + 0x4D0) /* FQ Cnt 128 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT129_REG (CSR_QU_STLFQ_CSR_BASE + 0x4D4) /* FQ Cnt 129 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT130_REG (CSR_QU_STLFQ_CSR_BASE + 0x4D8) /* FQ Cnt 130 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT131_REG (CSR_QU_STLFQ_CSR_BASE + 0x4DC) /* FQ Cnt 131 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT132_REG (CSR_QU_STLFQ_CSR_BASE + 0x4E0) /* FQ Cnt 132 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT133_REG (CSR_QU_STLFQ_CSR_BASE + 0x4E4) /* FQ Cnt 133 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT134_REG (CSR_QU_STLFQ_CSR_BASE + 0x4E8) /* FQ Cnt 134 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT135_REG (CSR_QU_STLFQ_CSR_BASE + 0x4EC) /* FQ Cnt 135 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT136_REG (CSR_QU_STLFQ_CSR_BASE + 0x4F0) /* FQ Cnt 136 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT137_REG (CSR_QU_STLFQ_CSR_BASE + 0x4F4) /* FQ Cnt 137 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT138_REG (CSR_QU_STLFQ_CSR_BASE + 0x4F8) /* FQ Cnt 138 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT139_REG (CSR_QU_STLFQ_CSR_BASE + 0x4FC) /* FQ Cnt 139 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT140_REG (CSR_QU_STLFQ_CSR_BASE + 0x500) /* FQ Cnt 140 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT141_REG (CSR_QU_STLFQ_CSR_BASE + 0x504) /* FQ Cnt 141 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT142_REG (CSR_QU_STLFQ_CSR_BASE + 0x508) /* FQ Cnt 142 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT143_REG (CSR_QU_STLFQ_CSR_BASE + 0x50C) /* FQ Cnt 143 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT144_REG (CSR_QU_STLFQ_CSR_BASE + 0x510) /* FQ Cnt 144 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT145_REG (CSR_QU_STLFQ_CSR_BASE + 0x514) /* FQ Cnt 145 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT146_REG (CSR_QU_STLFQ_CSR_BASE + 0x518) /* FQ Cnt 146 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT147_REG (CSR_QU_STLFQ_CSR_BASE + 0x51C) /* FQ Cnt 147 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT148_REG (CSR_QU_STLFQ_CSR_BASE + 0x520) /* FQ Cnt 148 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT149_REG (CSR_QU_STLFQ_CSR_BASE + 0x524) /* FQ Cnt 149 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT150_REG (CSR_QU_STLFQ_CSR_BASE + 0x528) /* FQ Cnt 150 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT151_REG (CSR_QU_STLFQ_CSR_BASE + 0x52C) /* FQ Cnt 151 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT152_REG (CSR_QU_STLFQ_CSR_BASE + 0x530) /* FQ Cnt 152 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT153_REG (CSR_QU_STLFQ_CSR_BASE + 0x534) /* FQ Cnt 153 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT154_REG (CSR_QU_STLFQ_CSR_BASE + 0x538) /* FQ Cnt 154 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT155_REG (CSR_QU_STLFQ_CSR_BASE + 0x53C) /* FQ Cnt 155 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT156_REG (CSR_QU_STLFQ_CSR_BASE + 0x540) /* FQ Cnt 156 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT157_REG (CSR_QU_STLFQ_CSR_BASE + 0x544) /* FQ Cnt 157 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT158_REG (CSR_QU_STLFQ_CSR_BASE + 0x548) /* FQ Cnt 158 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT159_REG (CSR_QU_STLFQ_CSR_BASE + 0x54C) /* FQ Cnt 159 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT160_REG (CSR_QU_STLFQ_CSR_BASE + 0x550) /* FQ Cnt 160 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT161_REG (CSR_QU_STLFQ_CSR_BASE + 0x554) /* FQ Cnt 161 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT162_REG (CSR_QU_STLFQ_CSR_BASE + 0x558) /* FQ Cnt 162 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT163_REG (CSR_QU_STLFQ_CSR_BASE + 0x55C) /* FQ Cnt 163 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT164_REG (CSR_QU_STLFQ_CSR_BASE + 0x560) /* FQ Cnt 164 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT165_REG (CSR_QU_STLFQ_CSR_BASE + 0x564) /* FQ Cnt 165 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT166_REG (CSR_QU_STLFQ_CSR_BASE + 0x568) /* FQ Cnt 166 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT167_REG (CSR_QU_STLFQ_CSR_BASE + 0x56C) /* FQ Cnt 167 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT168_REG (CSR_QU_STLFQ_CSR_BASE + 0x570) /* FQ Cnt 168 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT169_REG (CSR_QU_STLFQ_CSR_BASE + 0x574) /* FQ Cnt 169 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT170_REG (CSR_QU_STLFQ_CSR_BASE + 0x578) /* FQ Cnt 170 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT171_REG (CSR_QU_STLFQ_CSR_BASE + 0x57C) /* FQ Cnt 171 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT172_REG (CSR_QU_STLFQ_CSR_BASE + 0x580) /* FQ Cnt 172 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT173_REG (CSR_QU_STLFQ_CSR_BASE + 0x584) /* FQ Cnt 173 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT174_REG (CSR_QU_STLFQ_CSR_BASE + 0x588) /* FQ Cnt 174 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT175_REG (CSR_QU_STLFQ_CSR_BASE + 0x58C) /* FQ Cnt 175 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT176_REG (CSR_QU_STLFQ_CSR_BASE + 0x590) /* FQ Cnt 176 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT177_REG (CSR_QU_STLFQ_CSR_BASE + 0x594) /* FQ Cnt 177 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT178_REG (CSR_QU_STLFQ_CSR_BASE + 0x598) /* FQ Cnt 178 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT179_REG (CSR_QU_STLFQ_CSR_BASE + 0x59C) /* FQ Cnt 179 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT180_REG (CSR_QU_STLFQ_CSR_BASE + 0x5A0) /* FQ Cnt 180 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT181_REG (CSR_QU_STLFQ_CSR_BASE + 0x5A4) /* FQ Cnt 181 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT182_REG (CSR_QU_STLFQ_CSR_BASE + 0x5A8) /* FQ Cnt 182 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT183_REG (CSR_QU_STLFQ_CSR_BASE + 0x5AC) /* FQ Cnt 183 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT184_REG (CSR_QU_STLFQ_CSR_BASE + 0x5B0) /* FQ Cnt 184 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT185_REG (CSR_QU_STLFQ_CSR_BASE + 0x5B4) /* FQ Cnt 185 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT186_REG (CSR_QU_STLFQ_CSR_BASE + 0x5B8) /* FQ Cnt 186 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT187_REG (CSR_QU_STLFQ_CSR_BASE + 0x5BC) /* FQ Cnt 187 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT188_REG (CSR_QU_STLFQ_CSR_BASE + 0x5C0) /* FQ Cnt 188 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT189_REG (CSR_QU_STLFQ_CSR_BASE + 0x5C4) /* FQ Cnt 189 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT190_REG (CSR_QU_STLFQ_CSR_BASE + 0x5C8) /* FQ Cnt 190 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT191_REG (CSR_QU_STLFQ_CSR_BASE + 0x5CC) /* FQ Cnt 191 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT192_REG (CSR_QU_STLFQ_CSR_BASE + 0x5D0) /* FQ Cnt 192 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT193_REG (CSR_QU_STLFQ_CSR_BASE + 0x5D4) /* FQ Cnt 193 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT194_REG (CSR_QU_STLFQ_CSR_BASE + 0x5D8) /* FQ Cnt 194 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT195_REG (CSR_QU_STLFQ_CSR_BASE + 0x5DC) /* FQ Cnt 195 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT196_REG (CSR_QU_STLFQ_CSR_BASE + 0x5E0) /* FQ Cnt 196 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT197_REG (CSR_QU_STLFQ_CSR_BASE + 0x5E4) /* FQ Cnt 197 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT198_REG (CSR_QU_STLFQ_CSR_BASE + 0x5E8) /* FQ Cnt 198 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT199_REG (CSR_QU_STLFQ_CSR_BASE + 0x5EC) /* FQ Cnt 199 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT200_REG (CSR_QU_STLFQ_CSR_BASE + 0x5F0) /* FQ Cnt 200 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT201_REG (CSR_QU_STLFQ_CSR_BASE + 0x5F4) /* FQ Cnt 201 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT202_REG (CSR_QU_STLFQ_CSR_BASE + 0x5F8) /* FQ Cnt 202 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT203_REG (CSR_QU_STLFQ_CSR_BASE + 0x5FC) /* FQ Cnt 203 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT204_REG (CSR_QU_STLFQ_CSR_BASE + 0x600) /* FQ Cnt 204 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT205_REG (CSR_QU_STLFQ_CSR_BASE + 0x604) /* FQ Cnt 205 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT206_REG (CSR_QU_STLFQ_CSR_BASE + 0x608) /* FQ Cnt 206 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT207_REG (CSR_QU_STLFQ_CSR_BASE + 0x60C) /* FQ Cnt 207 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT208_REG (CSR_QU_STLFQ_CSR_BASE + 0x610) /* FQ Cnt 208 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT209_REG (CSR_QU_STLFQ_CSR_BASE + 0x614) /* FQ Cnt 209 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT210_REG (CSR_QU_STLFQ_CSR_BASE + 0x618) /* FQ Cnt 210 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT211_REG (CSR_QU_STLFQ_CSR_BASE + 0x61C) /* FQ Cnt 211 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT212_REG (CSR_QU_STLFQ_CSR_BASE + 0x620) /* FQ Cnt 212 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT213_REG (CSR_QU_STLFQ_CSR_BASE + 0x624) /* FQ Cnt 213 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT214_REG (CSR_QU_STLFQ_CSR_BASE + 0x628) /* FQ Cnt 214 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT215_REG (CSR_QU_STLFQ_CSR_BASE + 0x62C) /* FQ Cnt 215 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT216_REG (CSR_QU_STLFQ_CSR_BASE + 0x630) /* FQ Cnt 216 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT217_REG (CSR_QU_STLFQ_CSR_BASE + 0x634) /* FQ Cnt 217 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT218_REG (CSR_QU_STLFQ_CSR_BASE + 0x638) /* FQ Cnt 218 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT219_REG (CSR_QU_STLFQ_CSR_BASE + 0x63C) /* FQ Cnt 219 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT220_REG (CSR_QU_STLFQ_CSR_BASE + 0x640) /* FQ Cnt 220 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT221_REG (CSR_QU_STLFQ_CSR_BASE + 0x644) /* FQ Cnt 221 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT222_REG (CSR_QU_STLFQ_CSR_BASE + 0x648) /* FQ Cnt 222 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT223_REG (CSR_QU_STLFQ_CSR_BASE + 0x64C) /* FQ Cnt 223 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT224_REG (CSR_QU_STLFQ_CSR_BASE + 0x650) /* FQ Cnt 224 */ +#define CSR_QU_STLFQ_CSR_FQ_RXPSH_CID_CTL_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x654) /* 控制fq rxfastflow推qpc时的xid转cid控制信号。 */ +#define CSR_QU_STLFQ_CSR_FQ_ROCE_DB_ODR_CTL1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x658) /* 控制RoCE的DB触发的QU继承order命令推SQE的socket的比特。 */ +#define CSR_QU_STLFQ_CSR_FQ_ROCE_DB_ODR_CTL2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x65C) /* 控制RoCE的DB触发的QU继承order命令推SQE的socket的比特。 */ +#define CSR_QU_STLFQ_CSR_FQ_NORM_NIC_ODR_CTL1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x660) /* 控制NIC的QU继承order命令推SQE的256bit flit的flit[191:160]。 */ +#define CSR_QU_STLFQ_CSR_FQ_NORM_NIC_ODR_CTL2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x664) /* 控制NIC的QU继承order命令推SQE的256bit flit的flit[159:128]。 */ +#define CSR_QU_STLFQ_CSR_FQ_ODR_FLIT256_CTL1_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x668) /* 控制QU发送的order命令的256bit宽度的flit的[127:96]。 */ +#define CSR_QU_STLFQ_CSR_FQ_ODR_FLIT256_CTL2_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x66C) /* 控制QU发送的order命令的256bit宽度的flit的[95:64]。 */ +#define CSR_QU_STLFQ_CSR_FQ_ODR_FLIT256_CTL3_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x670) /* 控制QU发送的order命令的256bit宽度的flit的[63:32]。 */ +#define CSR_QU_STLFQ_CSR_FQ_ODR_FLIT256_CTL4_REG \ + (CSR_QU_STLFQ_CSR_BASE + 0x674) /* 控制QU发送的order命令的256bit宽度的flit的[31:0]。 */ +#define CSR_QU_STLFQ_CSR_FQ_ODR_STYPE_CID2QID_EN_REG \ + (CSR_QU_STLFQ_CSR_BASE + \ + 0x678) /* 控制根据serve type来确定map表里的cid的低4比特是否是DB里的queue id（仅RoCE业务使能这个寄存器）。 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT225_REG (CSR_QU_STLFQ_CSR_BASE + 0x67C) /* FQ Cnt 225 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT226_REG (CSR_QU_STLFQ_CSR_BASE + 0x680) /* FQ Cnt 226 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT227_REG (CSR_QU_STLFQ_CSR_BASE + 0x684) /* FQ Cnt 227 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT228_REG (CSR_QU_STLFQ_CSR_BASE + 0x688) /* FQ Cnt 228 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT229_REG (CSR_QU_STLFQ_CSR_BASE + 0x68C) /* FQ Cnt 229 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT230_REG (CSR_QU_STLFQ_CSR_BASE + 0x690) /* FQ Cnt 230 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT231_REG (CSR_QU_STLFQ_CSR_BASE + 0x694) /* FQ Cnt 231 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT232_REG (CSR_QU_STLFQ_CSR_BASE + 0x698) /* FQ Cnt 232 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT233_REG (CSR_QU_STLFQ_CSR_BASE + 0x69C) /* FQ Cnt 233 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT234_REG (CSR_QU_STLFQ_CSR_BASE + 0x6A0) /* FQ Cnt 234 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT235_REG (CSR_QU_STLFQ_CSR_BASE + 0x6A4) /* FQ Cnt 235 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT236_REG (CSR_QU_STLFQ_CSR_BASE + 0x6A8) /* FQ Cnt 236 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT237_REG (CSR_QU_STLFQ_CSR_BASE + 0x6AC) /* FQ Cnt 237 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT238_REG (CSR_QU_STLFQ_CSR_BASE + 0x6B0) /* FQ Cnt 238 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT239_REG (CSR_QU_STLFQ_CSR_BASE + 0x6B4) /* FQ Cnt 239 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT240_REG (CSR_QU_STLFQ_CSR_BASE + 0x6B8) /* FQ Cnt 240 */ +#define CSR_QU_STLFQ_CSR_FQ_CNT241_REG (CSR_QU_STLFQ_CSR_BASE + 0x6D4) /* FQ Cnt 241 */ + +#endif // STLFQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stliq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stliq_c_union_define.h new file mode 100644 index 000000000..b982f49c9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stliq_c_union_define.h @@ -0,0 +1,1109 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stliq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:17:57 Create file +// ****************************************************************************** + +#ifndef STLIQ_C_UNION_DEFINE_H +#define STLIQ_C_UNION_DEFINE_H + +/* Define the union csr_qu_versions_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_versions_u; + +/* Define the union csr_stliq_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 8; /* [7:0] */ + u32 rsv_1 : 8; /* [15:8] */ + u32 rsv_2 : 3; /* [18:16] */ + u32 rsv_3 : 3; /* [21:19] */ + u32 csr_stliq_mem_init_start : 1; /* [22] */ + u32 csr_stliq_cntx_sf_watchdog_en : 1; /* [23] */ + u32 csr_stliq_mem_ecc_bypass : 1; /* [24] */ + u32 csr_stliq_ram_uncrt_err2itf_en : 1; /* [25] */ + u32 csr_stliq_other_uncrt_err2itf_en : 1; /* [26] */ + u32 csr_stliq_mem_ecc_req : 2; /* [28:27] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_mode_u; + +/* Define the union csr_stliq_cntx_timout_watermark_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cntx_sf_timeout_watermark : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_cntx_timout_watermark_u; + +/* Define the union csr_stliq_ltr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_wrr_weight_lb : 8; /* [7:0] */ + u32 csr_stliq_wrr_weight_tx : 8; /* [15:8] */ + u32 csr_stliq_wrr_weight_rx : 8; /* [23:16] */ + u32 csr_stliq_wrr_weight_stf_lb : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_ltr_weight_u; + +/* Define the union csr_stliq_lfp_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_wrr_weight_peq : 4; /* [3:0] */ + u32 csr_stliq_wrr_weight_stfqry0 : 4; /* [7:4] */ + u32 csr_stliq_wrr_weight_stfqry1 : 4; /* [11:8] */ + u32 csr_stliq_wrr_weight_stlqry : 4; /* [15:12] */ + u32 csr_stliq_wrr_weight_rlb : 8; /* [23:16] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_lfp_weight_u; + +/* Define the union csr_stliq_dpth_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_dpth_th0 : 16; /* [15:0] */ + u32 csr_stliq_dpth_th1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_dpth_th_u; + +/* Define the union csr_stliq_tx_ndrop_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_tx_en0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_ndrop_en0_u; + +/* Define the union csr_stliq_tx_ndrop_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_tx_en1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_ndrop_en1_u; + +/* Define the union csr_stliq_tx_ndrop_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_tx_en2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_ndrop_en2_u; + +/* Define the union csr_stliq_tx_ndrop_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_tx_en3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_ndrop_en3_u; + +/* Define the union csr_stliq_rx_ndrop_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_rx_en0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_ndrop_en0_u; + +/* Define the union csr_stliq_rx_ndrop_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_rx_en1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_ndrop_en1_u; + +/* Define the union csr_stliq_rx_ndrop_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_rx_en2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_ndrop_en2_u; + +/* Define the union csr_stliq_rx_ndrop_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_ndrp_rx_en3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_ndrop_en3_u; + +/* Define the union csr_stliq_tmr_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_tmr_src : 12; /* [11:0] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tmr_src_u; + +/* Define the union csr_stliq_sfifo_af0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_rx_af_th : 8; /* [7:0] */ + u32 sfifo_tx_af_th : 8; /* [15:8] */ + u32 sfifo_lb_af_th : 8; /* [23:16] */ + u32 sfifo_peq_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sfifo_af0_u; + +/* Define the union csr_stliq_sfifo_af1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_eop_gain_af_th : 8; /* [7:0] */ + u32 sfifo_stfqry_af_th : 8; /* [15:8] */ + u32 sfifo_stlqry_af_th : 8; /* [23:16] */ + u32 sfifo_tmr_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sfifo_af1_u; + +/* Define the union csr_stliq_sfifo_af2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_stf_lb_af_th : 8; /* [7:0] */ + u32 sfifo_rlb_af_th : 8; /* [15:8] */ + u32 sfifo_rx_iarb_af_th : 8; /* [23:16] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sfifo_af2_u; + +/* Define the union csr_stliq_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_done : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_mem_init_done_u; + +/* Define the union csr_stliq_tx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_tx_drp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_drop_cnt_u; + +/* Define the union csr_stliq_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_rx_drp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_drop_cnt_u; + +/* Define the union csr_stliq_tx_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_tx_sop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_sop_cnt_u; + +/* Define the union csr_stliq_rx_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_rx_sop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_sop_cnt_u; + +/* Define the union csr_stliq_tx_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_tx_eop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_tx_eop_cnt_u; + +/* Define the union csr_stliq_rx_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_rx_eop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_rx_eop_cnt_u; + +/* Define the union csr_stliq_lb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_lb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_lb_cnt_u; + +/* Define the union csr_stliq_qry_stl_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_qry_stl_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_qry_stl_req_cnt_u; + +/* Define the union csr_stliq_qry_stf_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_qry_stf_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_qry_stf_req_cnt_u; + +/* Define the union csr_stliq_qry_stl_rsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_qry_stl_rsp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_qry_stl_rsp_cnt_u; + +/* Define the union csr_stliq_qry_stf_rsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_qry_stf_rsp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_qry_stf_rsp_cnt_u; + +/* Define the union csr_stliq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_9 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_10 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int_vector_u; + +/* Define the union csr_stliq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_11 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int_u; + +/* Define the union csr_stliq_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_12 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int_en_u; + +/* Define the union csr_stliq_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_cntx_sf_timeout : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 stliq_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int0_sticky_u; + +/* Define the union csr_stliq_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_fifo_overflow : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 stliq_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int1_sticky_u; + +/* Define the union csr_stliq_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_fifo_underflow : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 stliq_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int2_sticky_u; + +/* Define the union csr_stliq_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_2bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 stliq_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int3_sticky_u; + +/* Define the union csr_stliq_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 stliq_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_int4_sticky_u; + +/* Define the union csr_stliq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_indrect_ctrl_u; + +/* Define the union csr_stliq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_indrect_timeout_u; + +/* Define the union csr_stliq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_indrect_dat0_u; + +/* Define the union csr_stliq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_indrect_dat1_u; + +/* Define the union csr_stliq_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_indrect_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_indrect_dat2_u; + +/* Define the union csr_stliq_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_indrect_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_indrect_dat3_u; + +/* Define the union csr_stliq_sfifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_rx_fill : 8; /* [7:0] */ + u32 sfifo_tx_fill : 8; /* [15:8] */ + u32 sfifo_lb_fill : 8; /* [23:16] */ + u32 sfifo_peq_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sfifo_fill0_u; + +/* Define the union csr_stliq_sfifo_fill1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_eop_gain_fill : 8; /* [7:0] */ + u32 sfifo_stfqry0_fill : 8; /* [15:8] */ + u32 sfifo_stlqry_fill : 8; /* [23:16] */ + u32 sfifo_tmr_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sfifo_fill1_u; + +/* Define the union csr_stliq_sfifo_fill2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_stfqry1_fill : 8; /* [7:0] */ + u32 sfifo_stffq0_lb_fill : 8; /* [15:8] */ + u32 sfifo_stffq1_lb_fill : 8; /* [23:16] */ + u32 sfifo_stffq_rlb_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sfifo_fill2_u; + +/* Define the union csr_stliq_mem_ecc_1bit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_mem_1bit_ecc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_mem_ecc_1bit_cnt_u; + +/* Define the union csr_stliq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_stliq_sample_mode : 1; /* [0] */ + u32 csr_stliq_spec_port_en : 1; /* [1] */ + u32 csr_stliq_done_clr : 1; /* [2] */ + u32 rsv_13 : 1; /* [3] */ + u32 csr_stliq_spec_port_num : 4; /* [7:4] */ + u32 csr_stliq_spec_pptr_typ : 8; /* [15:8] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_latency_cfg_u; + +/* Define the union csr_stliq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_sample_done : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_latency_sta_u; + +/* Define the union csr_stliq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_sample_tmr_u; + +/* Define the union csr_stliq_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlfq_stliq_bnd_bp : 1; /* [0] */ + u32 cpb_stliq_req_bp : 5; /* [5:1] */ + u32 stliq_stlfq_lb_bp : 1; /* [6] */ + u32 stliq_stlfq_qry_req_bp : 1; /* [7] */ + u32 stlfq_stliq_qry_rsp_bp : 1; /* [8] */ + u32 stliq_stlfq_tmr_bp : 1; /* [9] */ + u32 prm_stliq_prealloc_bp : 1; /* [10] */ + u32 stliq_stffq0_qry_req_bp : 1; /* [11] */ + u32 stffq0_stliq_qry_rsp_bp : 1; /* [12] */ + u32 stliq_stffq0_lb_bp : 1; /* [13] */ + u32 stfiq_stliq_ret_bp : 1; /* [14] */ + u32 oq_stliq_fp_bp : 1; /* [15] */ + u32 icdq_stliq_rxf_bp : 1; /* [16] */ + u32 stliq_stffq1_qry_req_bp : 1; /* [17] */ + u32 stffq1_stliq_qry_rsp_bp : 1; /* [18] */ + u32 stliq_stffq1_lb_bp : 1; /* [19] */ + u32 rsv_16 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_bp_sta_u; + +/* Define the union csr_stliq_icb0_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_icb0_bp_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_icb0_sta_u; + +/* Define the union csr_stliq_icb1_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_icb1_bp_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_icb1_sta_u; + +/* Define the union csr_stliq_to_oq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_oq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_oq_cnt_u; + +/* Define the union csr_stliq_to_stlfq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_stlfq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_stlfq_cnt_u; + +/* Define the union csr_stliq_to_stl_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_stlcpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_stl_cpb_cnt_u; + +/* Define the union csr_stliq_to_rob_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_rob_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_rob_cnt_u; + +/* Define the union csr_stliq_to_stfiq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_stfiq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_stfiq_cnt_u; + +/* Define the union csr_stliq_to_icdq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_icdq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_icdq_cnt_u; + +/* Define the union csr_stliq_from_rob_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_from_rob_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_from_rob_cnt_u; + +/* Define the union csr_stliq_from_stlfq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_from_stlfq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_from_stlfq_cnt_u; + +/* Define the union csr_stliq_from_stffq0_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_from_stffq0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_from_stffq0_cnt_u; + +/* Define the union csr_stliq_from_stffq1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_from_stffq1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_from_stffq1_cnt_u; + +/* Define the union csr_stliq_to_stfiq_fret_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_stfiq_fret_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_stfiq_fret_cnt_u; + +/* Define the union csr_stliq_to_stfiq_nret_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_stfiq_nret_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_stfiq_nret_cnt_u; + +/* Define the union csr_stliq_to_stfiq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_csr_to_stfiq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_to_stfiq_cmd_cnt_u; + +/* Define the union csr_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlqu_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlqu_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlqu_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlqu_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlqu_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg4_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_qu_versions_u qu_versions; /* 0 */ + volatile csr_stliq_mode_u stliq_mode; /* 4 */ + volatile csr_stliq_cntx_timout_watermark_u stliq_cntx_timout_watermark; /* 8 */ + volatile csr_stliq_ltr_weight_u stliq_ltr_weight; /* C */ + volatile csr_stliq_lfp_weight_u stliq_lfp_weight; /* 10 */ + volatile csr_stliq_dpth_th_u stliq_dpth_th; /* 14 */ + volatile csr_stliq_tx_ndrop_en0_u stliq_tx_ndrop_en0; /* 18 */ + volatile csr_stliq_tx_ndrop_en1_u stliq_tx_ndrop_en1; /* 1C */ + volatile csr_stliq_tx_ndrop_en2_u stliq_tx_ndrop_en2; /* 20 */ + volatile csr_stliq_tx_ndrop_en3_u stliq_tx_ndrop_en3; /* 24 */ + volatile csr_stliq_rx_ndrop_en0_u stliq_rx_ndrop_en0; /* 28 */ + volatile csr_stliq_rx_ndrop_en1_u stliq_rx_ndrop_en1; /* 2C */ + volatile csr_stliq_rx_ndrop_en2_u stliq_rx_ndrop_en2; /* 30 */ + volatile csr_stliq_rx_ndrop_en3_u stliq_rx_ndrop_en3; /* 34 */ + volatile csr_stliq_tmr_src_u stliq_tmr_src; /* 38 */ + volatile csr_stliq_sfifo_af0_u stliq_sfifo_af0; /* 3C */ + volatile csr_stliq_sfifo_af1_u stliq_sfifo_af1; /* 40 */ + volatile csr_stliq_sfifo_af2_u stliq_sfifo_af2; /* 44 */ + volatile csr_stliq_mem_init_done_u stliq_mem_init_done; /* 48 */ + volatile csr_stliq_tx_drop_cnt_u stliq_tx_drop_cnt; /* 4C */ + volatile csr_stliq_rx_drop_cnt_u stliq_rx_drop_cnt; /* 50 */ + volatile csr_stliq_tx_sop_cnt_u stliq_tx_sop_cnt; /* 54 */ + volatile csr_stliq_rx_sop_cnt_u stliq_rx_sop_cnt; /* 58 */ + volatile csr_stliq_tx_eop_cnt_u stliq_tx_eop_cnt; /* 5C */ + volatile csr_stliq_rx_eop_cnt_u stliq_rx_eop_cnt; /* 60 */ + volatile csr_stliq_lb_cnt_u stliq_lb_cnt; /* 64 */ + volatile csr_stliq_qry_stl_req_cnt_u stliq_qry_stl_req_cnt; /* 68 */ + volatile csr_stliq_qry_stf_req_cnt_u stliq_qry_stf_req_cnt; /* 6C */ + volatile csr_stliq_qry_stl_rsp_cnt_u stliq_qry_stl_rsp_cnt; /* 70 */ + volatile csr_stliq_qry_stf_rsp_cnt_u stliq_qry_stf_rsp_cnt; /* 74 */ + volatile csr_stliq_int_vector_u stliq_int_vector; /* 78 */ + volatile csr_stliq_int_u stliq_int; /* 7C */ + volatile csr_stliq_int_en_u stliq_int_en; /* 80 */ + volatile csr_stliq_int0_sticky_u stliq_int0_sticky; /* 84 */ + volatile csr_stliq_int1_sticky_u stliq_int1_sticky; /* 88 */ + volatile csr_stliq_int2_sticky_u stliq_int2_sticky; /* 8C */ + volatile csr_stliq_int3_sticky_u stliq_int3_sticky; /* 90 */ + volatile csr_stliq_int4_sticky_u stliq_int4_sticky; /* 94 */ + volatile csr_stliq_indrect_ctrl_u stliq_indrect_ctrl; /* 98 */ + volatile csr_stliq_indrect_timeout_u stliq_indrect_timeout; /* 9C */ + volatile csr_stliq_indrect_dat0_u stliq_indrect_dat0; /* A0 */ + volatile csr_stliq_indrect_dat1_u stliq_indrect_dat1; /* A4 */ + volatile csr_stliq_indrect_dat2_u stliq_indrect_dat2; /* A8 */ + volatile csr_stliq_indrect_dat3_u stliq_indrect_dat3; /* AC */ + volatile csr_stliq_sfifo_fill0_u stliq_sfifo_fill0; /* B0 */ + volatile csr_stliq_sfifo_fill1_u stliq_sfifo_fill1; /* B4 */ + volatile csr_stliq_sfifo_fill2_u stliq_sfifo_fill2; /* B8 */ + volatile csr_stliq_mem_ecc_1bit_cnt_u stliq_mem_ecc_1bit_cnt; /* BC */ + volatile csr_stliq_latency_cfg_u stliq_latency_cfg; /* C0 */ + volatile csr_stliq_latency_sta_u stliq_latency_sta; /* C4 */ + volatile csr_stliq_sample_tmr_u stliq_sample_tmr; /* C8 */ + volatile csr_stliq_bp_sta_u stliq_bp_sta; /* CC */ + volatile csr_stliq_icb0_sta_u stliq_icb0_sta; /* D0 */ + volatile csr_stliq_icb1_sta_u stliq_icb1_sta; /* D4 */ + volatile csr_stliq_to_oq_cnt_u stliq_to_oq_cnt; /* D8 */ + volatile csr_stliq_to_stlfq_cnt_u stliq_to_stlfq_cnt; /* DC */ + volatile csr_stliq_to_stl_cpb_cnt_u stliq_to_stl_cpb_cnt; /* E0 */ + volatile csr_stliq_to_rob_cnt_u stliq_to_rob_cnt; /* E4 */ + volatile csr_stliq_to_stfiq_cnt_u stliq_to_stfiq_cnt; /* E8 */ + volatile csr_stliq_to_icdq_cnt_u stliq_to_icdq_cnt; /* EC */ + volatile csr_stliq_from_rob_cnt_u stliq_from_rob_cnt; /* F0 */ + volatile csr_stliq_from_stlfq_cnt_u stliq_from_stlfq_cnt; /* F4 */ + volatile csr_stliq_from_stffq0_cnt_u stliq_from_stffq0_cnt; /* F8 */ + volatile csr_stliq_from_stffq1_cnt_u stliq_from_stffq1_cnt; /* FC */ + volatile csr_stliq_to_stfiq_fret_cnt_u stliq_to_stfiq_fret_cnt; /* 100 */ + volatile csr_stliq_to_stfiq_nret_cnt_u stliq_to_stfiq_nret_cnt; /* 104 */ + volatile csr_stliq_to_stfiq_cmd_cnt_u stliq_to_stfiq_cmd_cnt; /* 108 */ + volatile csr_mem_ctrl_bus_cfg0_u mem_ctrl_bus_cfg0; /* 10C */ + volatile csr_mem_ctrl_bus_cfg1_u mem_ctrl_bus_cfg1; /* 110 */ + volatile csr_mem_ctrl_bus_cfg2_u mem_ctrl_bus_cfg2; /* 114 */ + volatile csr_mem_ctrl_bus_cfg3_u mem_ctrl_bus_cfg3; /* 118 */ + volatile csr_mem_ctrl_bus_cfg4_u mem_ctrl_bus_cfg4; /* 11C */ +} S_qu_stliq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_stliq_csr */ +extern volatile S_qu_stliq_csr_REGS_TYPE *gopqu_stliq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetQU_VERSIONS_qu_version(unsigned int uqu_version); +int iSetSTLIQ_MODE_csr_stliq_mem_init_start(unsigned int ucsr_stliq_mem_init_start); +int iSetSTLIQ_MODE_csr_stliq_cntx_sf_watchdog_en(unsigned int ucsr_stliq_cntx_sf_watchdog_en); +int iSetSTLIQ_MODE_csr_stliq_mem_ecc_bypass(unsigned int ucsr_stliq_mem_ecc_bypass); +int iSetSTLIQ_MODE_csr_stliq_ram_uncrt_err2itf_en(unsigned int ucsr_stliq_ram_uncrt_err2itf_en); +int iSetSTLIQ_MODE_csr_stliq_other_uncrt_err2itf_en(unsigned int ucsr_stliq_other_uncrt_err2itf_en); +int iSetSTLIQ_MODE_csr_stliq_mem_ecc_req(unsigned int ucsr_stliq_mem_ecc_req); +int iSetSTLIQ_CNTX_TIMOUT_WATERMARK_cntx_sf_timeout_watermark(unsigned int ucntx_sf_timeout_watermark); +int iSetSTLIQ_LTR_WEIGHT_csr_stliq_wrr_weight_lb(unsigned int ucsr_stliq_wrr_weight_lb); +int iSetSTLIQ_LTR_WEIGHT_csr_stliq_wrr_weight_tx(unsigned int ucsr_stliq_wrr_weight_tx); +int iSetSTLIQ_LTR_WEIGHT_csr_stliq_wrr_weight_rx(unsigned int ucsr_stliq_wrr_weight_rx); +int iSetSTLIQ_LTR_WEIGHT_csr_stliq_wrr_weight_stf_lb(unsigned int ucsr_stliq_wrr_weight_stf_lb); +int iSetSTLIQ_LFP_WEIGHT_csr_stliq_wrr_weight_peq(unsigned int ucsr_stliq_wrr_weight_peq); +int iSetSTLIQ_LFP_WEIGHT_csr_stliq_wrr_weight_stfqry0(unsigned int ucsr_stliq_wrr_weight_stfqry0); +int iSetSTLIQ_LFP_WEIGHT_csr_stliq_wrr_weight_stfqry1(unsigned int ucsr_stliq_wrr_weight_stfqry1); +int iSetSTLIQ_LFP_WEIGHT_csr_stliq_wrr_weight_stlqry(unsigned int ucsr_stliq_wrr_weight_stlqry); +int iSetSTLIQ_LFP_WEIGHT_csr_stliq_wrr_weight_rlb(unsigned int ucsr_stliq_wrr_weight_rlb); +int iSetSTLIQ_DPTH_TH_csr_stliq_dpth_th0(unsigned int ucsr_stliq_dpth_th0); +int iSetSTLIQ_DPTH_TH_csr_stliq_dpth_th1(unsigned int ucsr_stliq_dpth_th1); +int iSetSTLIQ_TX_NDROP_EN0_csr_stliq_ndrp_tx_en0(unsigned int ucsr_stliq_ndrp_tx_en0); +int iSetSTLIQ_TX_NDROP_EN1_csr_stliq_ndrp_tx_en1(unsigned int ucsr_stliq_ndrp_tx_en1); +int iSetSTLIQ_TX_NDROP_EN2_csr_stliq_ndrp_tx_en2(unsigned int ucsr_stliq_ndrp_tx_en2); +int iSetSTLIQ_TX_NDROP_EN3_csr_stliq_ndrp_tx_en3(unsigned int ucsr_stliq_ndrp_tx_en3); +int iSetSTLIQ_RX_NDROP_EN0_csr_stliq_ndrp_rx_en0(unsigned int ucsr_stliq_ndrp_rx_en0); +int iSetSTLIQ_RX_NDROP_EN1_csr_stliq_ndrp_rx_en1(unsigned int ucsr_stliq_ndrp_rx_en1); +int iSetSTLIQ_RX_NDROP_EN2_csr_stliq_ndrp_rx_en2(unsigned int ucsr_stliq_ndrp_rx_en2); +int iSetSTLIQ_RX_NDROP_EN3_csr_stliq_ndrp_rx_en3(unsigned int ucsr_stliq_ndrp_rx_en3); +int iSetSTLIQ_TMR_SRC_csr_stliq_tmr_src(unsigned int ucsr_stliq_tmr_src); +int iSetSTLIQ_SFIFO_AF0_sfifo_rx_af_th(unsigned int usfifo_rx_af_th); +int iSetSTLIQ_SFIFO_AF0_sfifo_tx_af_th(unsigned int usfifo_tx_af_th); +int iSetSTLIQ_SFIFO_AF0_sfifo_lb_af_th(unsigned int usfifo_lb_af_th); +int iSetSTLIQ_SFIFO_AF0_sfifo_peq_af_th(unsigned int usfifo_peq_af_th); +int iSetSTLIQ_SFIFO_AF1_sfifo_eop_gain_af_th(unsigned int usfifo_eop_gain_af_th); +int iSetSTLIQ_SFIFO_AF1_sfifo_stfqry_af_th(unsigned int usfifo_stfqry_af_th); +int iSetSTLIQ_SFIFO_AF1_sfifo_stlqry_af_th(unsigned int usfifo_stlqry_af_th); +int iSetSTLIQ_SFIFO_AF1_sfifo_tmr_af_th(unsigned int usfifo_tmr_af_th); +int iSetSTLIQ_SFIFO_AF2_sfifo_stf_lb_af_th(unsigned int usfifo_stf_lb_af_th); +int iSetSTLIQ_SFIFO_AF2_sfifo_rlb_af_th(unsigned int usfifo_rlb_af_th); +int iSetSTLIQ_SFIFO_AF2_sfifo_rx_iarb_af_th(unsigned int usfifo_rx_iarb_af_th); +int iSetSTLIQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done); +int iSetSTLIQ_TX_DROP_CNT_stliq_csr_tx_drp(unsigned int ustliq_csr_tx_drp); +int iSetSTLIQ_RX_DROP_CNT_stliq_csr_rx_drp(unsigned int ustliq_csr_rx_drp); +int iSetSTLIQ_TX_SOP_CNT_stliq_csr_tx_sop(unsigned int ustliq_csr_tx_sop); +int iSetSTLIQ_RX_SOP_CNT_stliq_csr_rx_sop(unsigned int ustliq_csr_rx_sop); +int iSetSTLIQ_TX_EOP_CNT_stliq_csr_tx_eop(unsigned int ustliq_csr_tx_eop); +int iSetSTLIQ_RX_EOP_CNT_stliq_csr_rx_eop(unsigned int ustliq_csr_rx_eop); +int iSetSTLIQ_LB_CNT_stliq_csr_lb(unsigned int ustliq_csr_lb); +int iSetSTLIQ_QRY_STL_REQ_CNT_stliq_csr_qry_stl_req(unsigned int ustliq_csr_qry_stl_req); +int iSetSTLIQ_QRY_STF_REQ_CNT_stliq_csr_qry_stf_req(unsigned int ustliq_csr_qry_stf_req); +int iSetSTLIQ_QRY_STL_RSP_CNT_stliq_csr_qry_stl_rsp(unsigned int ustliq_csr_qry_stl_rsp); +int iSetSTLIQ_QRY_STF_RSP_CNT_stliq_csr_qry_stf_rsp(unsigned int ustliq_csr_qry_stf_rsp); +int iSetSTLIQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSTLIQ_INT_VECTOR_enable(unsigned int uenable); +int iSetSTLIQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSTLIQ_INT_int_data(unsigned int uint_data); +int iSetSTLIQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetSTLIQ_INT_EN_int_en(unsigned int uint_en); +int iSetSTLIQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetSTLIQ_INT0_STICKY_stliq_cntx_sf_timeout(unsigned int ustliq_cntx_sf_timeout); +int iSetSTLIQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetSTLIQ_INT0_STICKY_stliq_int0_sticky(unsigned int ustliq_int0_sticky); +int iSetSTLIQ_INT1_STICKY_stliq_fifo_overflow(unsigned int ustliq_fifo_overflow); +int iSetSTLIQ_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetSTLIQ_INT1_STICKY_stliq_int1_sticky(unsigned int ustliq_int1_sticky); +int iSetSTLIQ_INT2_STICKY_stliq_fifo_underflow(unsigned int ustliq_fifo_underflow); +int iSetSTLIQ_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetSTLIQ_INT2_STICKY_stliq_int2_sticky(unsigned int ustliq_int2_sticky); +int iSetSTLIQ_INT3_STICKY_mem_ecc_2bit(unsigned int umem_ecc_2bit); +int iSetSTLIQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetSTLIQ_INT3_STICKY_stliq_int3_sticky(unsigned int ustliq_int3_sticky); +int iSetSTLIQ_INT4_STICKY_mem_ecc_1bit(unsigned int umem_ecc_1bit); +int iSetSTLIQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4); +int iSetSTLIQ_INT4_STICKY_stliq_int4_sticky(unsigned int ustliq_int4_sticky); +int iSetSTLIQ_INDRECT_CTRL_csr_stliq_indrect_ctrl(unsigned int ucsr_stliq_indrect_ctrl); +int iSetSTLIQ_INDRECT_TIMEOUT_csr_stliq_indrect_timeout(unsigned int ucsr_stliq_indrect_timeout); +int iSetSTLIQ_INDRECT_DAT0_csr_stliq_indrect_data0(unsigned int ucsr_stliq_indrect_data0); +int iSetSTLIQ_INDRECT_DAT1_csr_stliq_indrect_data1(unsigned int ucsr_stliq_indrect_data1); +int iSetSTLIQ_INDRECT_DAT2_csr_stliq_indrect_data2(unsigned int ucsr_stliq_indrect_data2); +int iSetSTLIQ_INDRECT_DAT3_csr_stliq_indrect_data3(unsigned int ucsr_stliq_indrect_data3); +int iSetSTLIQ_SFIFO_FILL0_sfifo_rx_fill(unsigned int usfifo_rx_fill); +int iSetSTLIQ_SFIFO_FILL0_sfifo_tx_fill(unsigned int usfifo_tx_fill); +int iSetSTLIQ_SFIFO_FILL0_sfifo_lb_fill(unsigned int usfifo_lb_fill); +int iSetSTLIQ_SFIFO_FILL0_sfifo_peq_fill(unsigned int usfifo_peq_fill); +int iSetSTLIQ_SFIFO_FILL1_sfifo_eop_gain_fill(unsigned int usfifo_eop_gain_fill); +int iSetSTLIQ_SFIFO_FILL1_sfifo_stfqry0_fill(unsigned int usfifo_stfqry0_fill); +int iSetSTLIQ_SFIFO_FILL1_sfifo_stlqry_fill(unsigned int usfifo_stlqry_fill); +int iSetSTLIQ_SFIFO_FILL1_sfifo_tmr_fill(unsigned int usfifo_tmr_fill); +int iSetSTLIQ_SFIFO_FILL2_sfifo_stfqry1_fill(unsigned int usfifo_stfqry1_fill); +int iSetSTLIQ_SFIFO_FILL2_sfifo_stffq0_lb_fill(unsigned int usfifo_stffq0_lb_fill); +int iSetSTLIQ_SFIFO_FILL2_sfifo_stffq1_lb_fill(unsigned int usfifo_stffq1_lb_fill); +int iSetSTLIQ_SFIFO_FILL2_sfifo_stffq_rlb_fill(unsigned int usfifo_stffq_rlb_fill); +int iSetSTLIQ_MEM_ECC_1BIT_CNT_stliq_csr_mem_1bit_ecc(unsigned int ustliq_csr_mem_1bit_ecc); +int iSetSTLIQ_LATENCY_CFG_csr_stliq_sample_mode(unsigned int ucsr_stliq_sample_mode); +int iSetSTLIQ_LATENCY_CFG_csr_stliq_spec_port_en(unsigned int ucsr_stliq_spec_port_en); +int iSetSTLIQ_LATENCY_CFG_csr_stliq_done_clr(unsigned int ucsr_stliq_done_clr); +int iSetSTLIQ_LATENCY_CFG_csr_stliq_spec_port_num(unsigned int ucsr_stliq_spec_port_num); +int iSetSTLIQ_LATENCY_CFG_csr_stliq_spec_pptr_typ(unsigned int ucsr_stliq_spec_pptr_typ); +int iSetSTLIQ_LATENCY_STA_stliq_csr_sample_done(unsigned int ustliq_csr_sample_done); +int iSetSTLIQ_SAMPLE_TMR_stliq_csr_sample_tmr(unsigned int ustliq_csr_sample_tmr); +int iSetSTLIQ_BP_STA_stlfq_stliq_bnd_bp(unsigned int ustlfq_stliq_bnd_bp); +int iSetSTLIQ_BP_STA_cpb_stliq_req_bp(unsigned int ucpb_stliq_req_bp); +int iSetSTLIQ_BP_STA_stliq_stlfq_lb_bp(unsigned int ustliq_stlfq_lb_bp); +int iSetSTLIQ_BP_STA_stliq_stlfq_qry_req_bp(unsigned int ustliq_stlfq_qry_req_bp); +int iSetSTLIQ_BP_STA_stlfq_stliq_qry_rsp_bp(unsigned int ustlfq_stliq_qry_rsp_bp); +int iSetSTLIQ_BP_STA_stliq_stlfq_tmr_bp(unsigned int ustliq_stlfq_tmr_bp); +int iSetSTLIQ_BP_STA_prm_stliq_prealloc_bp(unsigned int uprm_stliq_prealloc_bp); +int iSetSTLIQ_BP_STA_stliq_stffq0_qry_req_bp(unsigned int ustliq_stffq0_qry_req_bp); +int iSetSTLIQ_BP_STA_stffq0_stliq_qry_rsp_bp(unsigned int ustffq0_stliq_qry_rsp_bp); +int iSetSTLIQ_BP_STA_stliq_stffq0_lb_bp(unsigned int ustliq_stffq0_lb_bp); +int iSetSTLIQ_BP_STA_stfiq_stliq_ret_bp(unsigned int ustfiq_stliq_ret_bp); +int iSetSTLIQ_BP_STA_oq_stliq_fp_bp(unsigned int uoq_stliq_fp_bp); +int iSetSTLIQ_BP_STA_icdq_stliq_rxf_bp(unsigned int uicdq_stliq_rxf_bp); +int iSetSTLIQ_BP_STA_stliq_stffq1_qry_req_bp(unsigned int ustliq_stffq1_qry_req_bp); +int iSetSTLIQ_BP_STA_stffq1_stliq_qry_rsp_bp(unsigned int ustffq1_stliq_qry_rsp_bp); +int iSetSTLIQ_BP_STA_stliq_stffq1_lb_bp(unsigned int ustliq_stffq1_lb_bp); +int iSetSTLIQ_ICB0_STA_stliq_csr_icb0_bp_sta(unsigned int ustliq_csr_icb0_bp_sta); +int iSetSTLIQ_ICB1_STA_stliq_csr_icb1_bp_sta(unsigned int ustliq_csr_icb1_bp_sta); +int iSetSTLIQ_TO_OQ_CNT_stliq_csr_to_oq_cnt(unsigned int ustliq_csr_to_oq_cnt); +int iSetSTLIQ_TO_STLFQ_CNT_stliq_csr_to_stlfq_cnt(unsigned int ustliq_csr_to_stlfq_cnt); +int iSetSTLIQ_TO_STL_CPB_CNT_stliq_csr_to_stlcpb_cnt(unsigned int ustliq_csr_to_stlcpb_cnt); +int iSetSTLIQ_TO_ROB_CNT_stliq_csr_to_rob_cnt(unsigned int ustliq_csr_to_rob_cnt); +int iSetSTLIQ_TO_STFIQ_CNT_stliq_csr_to_stfiq_cnt(unsigned int ustliq_csr_to_stfiq_cnt); +int iSetSTLIQ_TO_ICDQ_CNT_stliq_csr_to_icdq_cnt(unsigned int ustliq_csr_to_icdq_cnt); +int iSetSTLIQ_FROM_ROB_CNT_stliq_csr_from_rob_cnt(unsigned int ustliq_csr_from_rob_cnt); +int iSetSTLIQ_FROM_STLFQ_CNT_stliq_csr_from_stlfq_cnt(unsigned int ustliq_csr_from_stlfq_cnt); +int iSetSTLIQ_FROM_STFFQ0_CNT_stliq_csr_from_stffq0_cnt(unsigned int ustliq_csr_from_stffq0_cnt); +int iSetSTLIQ_FROM_STFFQ1_CNT_stliq_csr_from_stffq1_cnt(unsigned int ustliq_csr_from_stffq1_cnt); +int iSetSTLIQ_TO_STFIQ_FRET_CNT_stliq_csr_to_stfiq_fret_cnt(unsigned int ustliq_csr_to_stfiq_fret_cnt); +int iSetSTLIQ_TO_STFIQ_NRET_CNT_stliq_csr_to_stfiq_nret_cnt(unsigned int ustliq_csr_to_stfiq_nret_cnt); +int iSetSTLIQ_TO_STFIQ_CMD_CNT_stliq_csr_to_stfiq_cmd_cnt(unsigned int ustliq_csr_to_stfiq_cmd_cnt); +int iSetMEM_CTRL_BUS_CFG0_stlqu_mem_ctrl_bus_0(unsigned int ustlqu_mem_ctrl_bus_0); +int iSetMEM_CTRL_BUS_CFG1_stlqu_mem_ctrl_bus_1(unsigned int ustlqu_mem_ctrl_bus_1); +int iSetMEM_CTRL_BUS_CFG2_stlqu_mem_ctrl_bus_2(unsigned int ustlqu_mem_ctrl_bus_2); +int iSetMEM_CTRL_BUS_CFG3_stlqu_mem_ctrl_bus_3(unsigned int ustlqu_mem_ctrl_bus_3); +int iSetMEM_CTRL_BUS_CFG4_stlqu_mem_ctrl_bus_4(unsigned int ustlqu_mem_ctrl_bus_4); + + +#endif // STLIQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stliq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stliq_reg_offset.h new file mode 100644 index 000000000..851e0d367 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stliq_reg_offset.h @@ -0,0 +1,106 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stliq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:17:57 Create file +// ****************************************************************************** + +#ifndef STLIQ_REG_OFFSET_H +#define STLIQ_REG_OFFSET_H + +/* QU_STLIQ_CSR Base address of Module's Register */ +#define CSR_QU_STLIQ_CSR_BASE (0xC000) + +/* **************************************************************************** */ +/* QU_STLIQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_STLIQ_CSR_QU_VERSIONS_REG (CSR_QU_STLIQ_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_QU_STLIQ_CSR_STLIQ_MODE_REG (CSR_QU_STLIQ_CSR_BASE + 0x4) /* 模式配置寄存器 */ +#define CSR_QU_STLIQ_CSR_STLIQ_CNTX_TIMOUT_WATERMARK_REG \ + (CSR_QU_STLIQ_CSR_BASE + 0x8) /* QUERY EOP时，等待EOP到来的超时水线 */ +#define CSR_QU_STLIQ_CSR_STLIQ_LTR_WEIGHT_REG (CSR_QU_STLIQ_CSR_BASE + 0xC) /* LB/TX/RX的权重配置寄存器 */ +#define CSR_QU_STLIQ_CSR_STLIQ_LFP_WEIGHT_REG (CSR_QU_STLIQ_CSR_BASE + 0x10) /* STLQRY/STFQRY/PEQ的权重配置寄存器 */ +#define CSR_QU_STLIQ_CSR_STLIQ_DPTH_TH_REG \ + (CSR_QU_STLIQ_CSR_BASE + 0x14) /* 通告微码当前IQ的深度状态的阈值配置注意：所有IQ队列共享阈值。 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_NDROP_EN0_REG (CSR_QU_STLIQ_CSR_BASE + 0x18) /* 源主机侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_NDROP_EN1_REG (CSR_QU_STLIQ_CSR_BASE + 0x1C) /* 源主机侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_NDROP_EN2_REG (CSR_QU_STLIQ_CSR_BASE + 0x20) /* 源主机侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_NDROP_EN3_REG (CSR_QU_STLIQ_CSR_BASE + 0x24) /* 源主机侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_NDROP_EN0_REG (CSR_QU_STLIQ_CSR_BASE + 0x28) /* 源网络侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_NDROP_EN1_REG (CSR_QU_STLIQ_CSR_BASE + 0x2C) /* 源网络侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_NDROP_EN2_REG (CSR_QU_STLIQ_CSR_BASE + 0x30) /* 源网络侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_NDROP_EN3_REG (CSR_QU_STLIQ_CSR_BASE + 0x34) /* 源网络侧报文丢弃使能配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TMR_SRC_REG (CSR_QU_STLIQ_CSR_BASE + 0x38) /* stateless timer的源信息 */ +#define CSR_QU_STLIQ_CSR_STLIQ_SFIFO_AF0_REG (CSR_QU_STLIQ_CSR_BASE + 0x3C) /* FIFO几乎满水线配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_SFIFO_AF1_REG (CSR_QU_STLIQ_CSR_BASE + 0x40) /* FIFO几乎满水线配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_SFIFO_AF2_REG (CSR_QU_STLIQ_CSR_BASE + 0x44) /* FIFO几乎满水线配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_MEM_INIT_DONE_REG (CSR_QU_STLIQ_CSR_BASE + 0x48) /* 表项初始化完成 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_DROP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x4C) /* 源主机侧报文丢弃次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_DROP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x50) /* 源网络侧报文丢弃次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_SOP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x54) /* 保留 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_SOP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x58) /* 源网络侧报文SOP次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TX_EOP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x5C) /* 源主机侧报文EOP次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_RX_EOP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x60) /* 源网络侧报文EOP次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_LB_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x64) /* STL微码逻辑环回报文次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_QRY_STL_REQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x68) /* stl微码QRY的请求次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_QRY_STF_REQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x6C) /* stf微码QRY的请求次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_QRY_STL_RSP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x70) /* stl微码QRY的响应次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_QRY_STF_RSP_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x74) /* stf微码QRY的响应次数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT_VECTOR_REG (CSR_QU_STLIQ_CSR_BASE + 0x78) /* 中断向量 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT_REG (CSR_QU_STLIQ_CSR_BASE + 0x7C) /* 中断状态 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT_EN_REG (CSR_QU_STLIQ_CSR_BASE + 0x80) /* 中断屏蔽 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT0_STICKY_REG (CSR_QU_STLIQ_CSR_BASE + 0x84) /* 中断0的sticky信息 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT1_STICKY_REG (CSR_QU_STLIQ_CSR_BASE + 0x88) /* 中断1的sticky信息 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT2_STICKY_REG (CSR_QU_STLIQ_CSR_BASE + 0x8C) /* 中断2的sticky信息 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT3_STICKY_REG (CSR_QU_STLIQ_CSR_BASE + 0x90) /* 中断3的sticky信息 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INT4_STICKY_REG (CSR_QU_STLIQ_CSR_BASE + 0x94) /* 中断4的sticky信息 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INDRECT_CTRL_REG (CSR_QU_STLIQ_CSR_BASE + 0x98) /* STLIQ间接寻址控制寄存器 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INDRECT_TIMEOUT_REG (CSR_QU_STLIQ_CSR_BASE + 0x9C) /* IQ间接寻址Timeout水线配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_INDRECT_DAT0_REG \ + (CSR_QU_STLIQ_CSR_BASE + 0xA0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STLIQ_CSR_STLIQ_INDRECT_DAT1_REG \ + (CSR_QU_STLIQ_CSR_BASE + 0xA4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STLIQ_CSR_STLIQ_INDRECT_DAT2_REG \ + (CSR_QU_STLIQ_CSR_BASE + 0xA8) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STLIQ_CSR_STLIQ_INDRECT_DAT3_REG \ + (CSR_QU_STLIQ_CSR_BASE + 0xAC) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_STLIQ_CSR_STLIQ_SFIFO_FILL0_REG (CSR_QU_STLIQ_CSR_BASE + 0xB0) /* FIFO内数据个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_SFIFO_FILL1_REG (CSR_QU_STLIQ_CSR_BASE + 0xB4) /* FIFO内数据个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_SFIFO_FILL2_REG (CSR_QU_STLIQ_CSR_BASE + 0xB8) /* FIFO内数据个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_MEM_ECC_1BIT_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xBC) /* STLIQ内部RAM发生1BIT ECC的次数 \ + */ +#define CSR_QU_STLIQ_CSR_STLIQ_LATENCY_CFG_REG (CSR_QU_STLIQ_CSR_BASE + 0xC0) /* stliq的时延采样DFX配置 */ +#define CSR_QU_STLIQ_CSR_STLIQ_LATENCY_STA_REG (CSR_QU_STLIQ_CSR_BASE + 0xC4) /* stliq的时延采样DFX状态 */ +#define CSR_QU_STLIQ_CSR_STLIQ_SAMPLE_TMR_REG (CSR_QU_STLIQ_CSR_BASE + 0xC8) /* stliq的时延采样DFX时间 */ +#define CSR_QU_STLIQ_CSR_STLIQ_BP_STA_REG (CSR_QU_STLIQ_CSR_BASE + 0xCC) /* STLIQ的外围接口反压状态 */ +#define CSR_QU_STLIQ_CSR_STLIQ_ICB0_STA_REG (CSR_QU_STLIQ_CSR_BASE + 0xD0) /* STLIQ预扣PRM资源接口的反压状态 */ +#define CSR_QU_STLIQ_CSR_STLIQ_ICB1_STA_REG (CSR_QU_STLIQ_CSR_BASE + 0xD4) /* STLIQ预扣PRM资源接口的反压状态 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_OQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xD8) /* STLIQ发往OQ的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_STLFQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xDC) /* STLIQ发往FQ的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_STL_CPB_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xE0) /* STLIQ发往CPB的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_ROB_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xE4) /* STLIQ发往ROB的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_STFIQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xE8) /* STLIQ发往STFIQ的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_ICDQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xEC) /* STLIQ发往ICDQ的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_FROM_ROB_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xF0) /* STLIQ来自ROB的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_FROM_STLFQ_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xF4) /* STLIQ来自STLFQ的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_FROM_STFFQ0_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xF8) /* STLIQ来自STFFQ0的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_FROM_STFFQ1_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0xFC) /* STLIQ来自STFFQ1的报文个数 */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_STFIQ_FRET_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x100) /* STLIQ发往STFIQ的fret报文个数 \ + */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_STFIQ_NRET_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x104) /* STLIQ发往STFIQ的nret报文个数 \ + */ +#define CSR_QU_STLIQ_CSR_STLIQ_TO_STFIQ_CMD_CNT_REG (CSR_QU_STLIQ_CSR_BASE + 0x108) /* STLIQ发往STFIQ的cmd报文个数 */ +#define CSR_QU_STLIQ_CSR_MEM_CTRL_BUS_CFG0_REG (CSR_QU_STLIQ_CSR_BASE + 0x10C) /* RAM CTRL_BUS寄存器0 */ +#define CSR_QU_STLIQ_CSR_MEM_CTRL_BUS_CFG1_REG (CSR_QU_STLIQ_CSR_BASE + 0x110) /* RAM CTRL_BUS寄存器1 */ +#define CSR_QU_STLIQ_CSR_MEM_CTRL_BUS_CFG2_REG (CSR_QU_STLIQ_CSR_BASE + 0x114) /* RAM CTRL_BUS寄存器2 */ +#define CSR_QU_STLIQ_CSR_MEM_CTRL_BUS_CFG3_REG (CSR_QU_STLIQ_CSR_BASE + 0x118) /* RAM CTRL_BUS寄存器3 */ +#define CSR_QU_STLIQ_CSR_MEM_CTRL_BUS_CFG4_REG (CSR_QU_STLIQ_CSR_BASE + 0x11C) /* RAM CTRL_BUS寄存器4 */ + +#endif // STLIQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlisch_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlisch_c_union_define.h new file mode 100644 index 000000000..097f46adb --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlisch_c_union_define.h @@ -0,0 +1,425 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : stlisch_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/05/07 10:21:41 Create file +// ****************************************************************************** + +#ifndef STLISCH_C_UNION_DEFINE_H +#define STLISCH_C_UNION_DEFINE_H + +/* Define the union csr_cnb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_vector_u; + +/* Define the union csr_isch_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_2 : 13; /* [15:3] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_int_u; + +/* Define the union csr_isch_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 3; /* [2:0] */ + u32 rsv_3 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_int_en_u; + +/* Define the union csr_isch_th_rls_e_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_rls_e_err : 1; /* [0] */ + u32 th_rls_e_err_insrt : 1; /* [1] */ + u32 th_rls_e_err_info : 9; /* [10:2] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_th_rls_e_error_status_u; + +/* Define the union csr_isch_th_rls_c_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_rls_c_err : 1; /* [0] */ + u32 th_rls_c_err_insrt : 1; /* [1] */ + u32 th_rls_c_err_info : 9; /* [10:2] */ + u32 rsv_5 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_th_rls_c_error_status_u; + +/* Define the union csr_isch_time_out_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timeout_err : 1; /* [0] */ + u32 timeout_err_insrt : 1; /* [1] */ + u32 timeout_err_info : 9; /* [10:2] */ + u32 rsv_6 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_time_out_error_status_u; + +/* Define the union csr_isch_bp_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_bp : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_bp_status_u; + +/* Define the union csr_isch_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_bp_bypass : 1; /* [0] */ + u32 qu_bp_set : 1; /* [1] */ + u32 rsv_8 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_bp_ctrl_u; + +/* Define the union csr_isch_force_rls_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_id_frc : 9; /* [8:0] */ + u32 rsv_9 : 3; /* [11:9] */ + u32 ctrl_frc : 1; /* [12] */ + u32 rsv_10 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_force_rls_ctrl_u; + +/* Define the union csr_isch_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 watchdog_mode : 3; /* [2:0] */ + u32 watch_dog_test_mode : 1; /* [3] */ + u32 rsv_11 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_mod_u; + +/* Define the union csr_isch_tile_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_en : 4; /* [3:0] */ + u32 rsv_12 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_tile_en_u; + +/* Define the union csr_isch_core0_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer_cr : 10; /* [9:0] */ + u32 rsv_13 : 2; /* [11:10] */ + u32 cwd_en_cr : 1; /* [12] */ + u32 rsv_14 : 3; /* [15:13] */ + u32 th_en_cr : 4; /* [19:16] */ + u32 pg_id_cr : 3; /* [22:20] */ + u32 rsv_15 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_core0_cfg_u; + +/* Define the union csr_isch_channel_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_cnt_ch : 9; /* [8:0] */ + u32 rsv_16 : 3; /* [11:9] */ + u32 pg_id_ch : 3; /* [14:12] */ + u32 rsv_17 : 1; /* [15] */ + u32 wght_ch : 5; /* [20:16] */ + u32 rsv_18 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_channel_cfg_u; + +/* Define the union csr_isch_4iq_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wght_iq : 20; /* [19:0] */ + u32 rsv_19 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_4iq_cfg_u; + +/* Define the union csr_isch_4th_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sta_th0 : 1; /* [0] */ + u32 ch_id_th0 : 6; /* [6:1] */ + u32 rsv_20 : 1; /* [7] */ + u32 sta_th1 : 1; /* [8] */ + u32 ch_id_th1 : 6; /* [14:9] */ + u32 rsv_21 : 1; /* [15] */ + u32 sta_th2 : 1; /* [16] */ + u32 ch_id_th2 : 6; /* [22:17] */ + u32 rsv_22 : 1; /* [23] */ + u32 sta_th3 : 1; /* [24] */ + u32 ch_id_th3 : 6; /* [30:25] */ + u32 rsv_23 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_4th_sta_u; + +/* Define the union csr_isch_core0_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th0_his_cr : 1; /* [0] */ + u32 th1_his_cr : 1; /* [1] */ + u32 th2_his_cr : 1; /* [2] */ + u32 th3_his_cr : 1; /* [3] */ + u32 rsv_24 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_core0_sta_u; + +/* Define the union csr_isch_rls_e_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_e_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_rls_e_cnt_u; + +/* Define the union csr_isch_rls_c_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_c_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_rls_c_cnt_u; + +/* Define the union csr_isch_time_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 time_out_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_time_out_cnt_u; + +/* Define the union csr_isch_rls_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_id_e : 9; /* [8:0] */ + u32 rsv_25 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_rls_e_u; + +/* Define the union csr_isch_rls_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_id_c : 9; /* [8:0] */ + u32 rsv_26 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_rls_c_u; + +/* Define the union csr_isch_rls_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_rls_cnt_u; + +/* Define the union csr_isch_alc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_alc_cnt_u; + +/* Define the union csr_isch_tl_idle_th_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_idle_4tile_cnt : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_tl_idle_th_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cnb_int_vector_u cnb_int_vector; /* 0 */ + volatile csr_isch_int_u isch_int; /* 4 */ + volatile csr_isch_int_en_u isch_int_en; /* 8 */ + volatile csr_isch_th_rls_e_error_status_u isch_th_rls_e_error_status; /* C */ + volatile csr_isch_th_rls_c_error_status_u isch_th_rls_c_error_status; /* 10 */ + volatile csr_isch_time_out_error_status_u isch_time_out_error_status; /* 14 */ + volatile csr_isch_bp_status_u isch_bp_status; /* 18 */ + volatile csr_isch_bp_ctrl_u isch_bp_ctrl; /* 1C */ + volatile csr_isch_force_rls_ctrl_u isch_force_rls_ctrl; /* 20 */ + volatile csr_isch_mod_u isch_mod; /* 24 */ + volatile csr_isch_tile_en_u isch_tile_en; /* 28 */ + volatile csr_isch_core0_cfg_u isch_core0_cfg[96]; /* 30 */ + volatile csr_isch_channel_cfg_u isch_channel_cfg[64]; /* 1B0 */ + volatile csr_isch_4iq_cfg_u isch_4iq_cfg[128]; /* 2B0 */ + volatile csr_isch_4th_sta_u isch_4th_sta[96]; /* 4B0 */ + volatile csr_isch_core0_sta_u isch_core0_sta[96]; /* 6D0 */ + volatile csr_isch_rls_e_cnt_u isch_rls_e_cnt; /* 850 */ + volatile csr_isch_rls_c_cnt_u isch_rls_c_cnt; /* 854 */ + volatile csr_isch_time_out_cnt_u isch_time_out_cnt; /* 858 */ + volatile csr_isch_rls_e_u isch_rls_e; /* 85C */ + volatile csr_isch_rls_c_u isch_rls_c; /* 860 */ + volatile csr_isch_rls_cnt_u isch_rls_cnt; /* 864 */ + volatile csr_isch_alc_cnt_u isch_alc_cnt; /* 868 */ + volatile csr_isch_tl_idle_th_cnt_u isch_tl_idle_th_cnt[4]; /* 870 */ +} S_qu_stlisch_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_stlisch_csr */ +extern volatile S_qu_stlisch_csr_REGS_TYPE *gopqu_stlisch_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCNB_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetCNB_INT_VECTOR_enable(unsigned int uenable); +int iSetCNB_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetISCH_INT_int_data(unsigned int uint_data); +int iSetISCH_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetISCH_INT_EN_int_en(unsigned int uint_en); +int iSetISCH_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetISCH_TH_RLS_E_ERROR_STATUS_th_rls_e_err(unsigned int uth_rls_e_err); +int iSetISCH_TH_RLS_E_ERROR_STATUS_th_rls_e_err_insrt(unsigned int uth_rls_e_err_insrt); +int iSetISCH_TH_RLS_E_ERROR_STATUS_th_rls_e_err_info(unsigned int uth_rls_e_err_info); +int iSetISCH_TH_RLS_C_ERROR_STATUS_th_rls_c_err(unsigned int uth_rls_c_err); +int iSetISCH_TH_RLS_C_ERROR_STATUS_th_rls_c_err_insrt(unsigned int uth_rls_c_err_insrt); +int iSetISCH_TH_RLS_C_ERROR_STATUS_th_rls_c_err_info(unsigned int uth_rls_c_err_info); +int iSetISCH_TIME_OUT_ERROR_STATUS_timeout_err(unsigned int utimeout_err); +int iSetISCH_TIME_OUT_ERROR_STATUS_timeout_err_insrt(unsigned int utimeout_err_insrt); +int iSetISCH_TIME_OUT_ERROR_STATUS_timeout_err_info(unsigned int utimeout_err_info); +int iSetISCH_BP_STATUS_qu_bp(unsigned int uqu_bp); +int iSetISCH_BP_CTRL_qu_bp_bypass(unsigned int uqu_bp_bypass); +int iSetISCH_BP_CTRL_qu_bp_set(unsigned int uqu_bp_set); +int iSetISCH_FORCE_RLS_CTRL_th_id_frc(unsigned int uth_id_frc); +int iSetISCH_FORCE_RLS_CTRL_ctrl_frc(unsigned int uctrl_frc); +int iSetISCH_MOD_watchdog_mode(unsigned int uwatchdog_mode); +int iSetISCH_MOD_watch_dog_test_mode(unsigned int uwatch_dog_test_mode); +int iSetISCH_TILE_EN_tile_en(unsigned int utile_en); +int iSetISCH_CORE0_CFG_timer_cr(unsigned int utimer_cr); +int iSetISCH_CORE0_CFG_cwd_en_cr(unsigned int ucwd_en_cr); +int iSetISCH_CORE0_CFG_th_en_cr(unsigned int uth_en_cr); +int iSetISCH_CORE0_CFG_pg_id_cr(unsigned int upg_id_cr); +int iSetISCH_CHANNEL_CFG_max_cnt_ch(unsigned int umax_cnt_ch); +int iSetISCH_CHANNEL_CFG_pg_id_ch(unsigned int upg_id_ch); +int iSetISCH_CHANNEL_CFG_wght_ch(unsigned int uwght_ch); +int iSetISCH_4IQ_CFG_wght_iq(unsigned int uwght_iq); +int iSetISCH_4TH_STA_sta_th0(unsigned int usta_th0); +int iSetISCH_4TH_STA_ch_id_th0(unsigned int uch_id_th0); +int iSetISCH_4TH_STA_sta_th1(unsigned int usta_th1); +int iSetISCH_4TH_STA_ch_id_th1(unsigned int uch_id_th1); +int iSetISCH_4TH_STA_sta_th2(unsigned int usta_th2); +int iSetISCH_4TH_STA_ch_id_th2(unsigned int uch_id_th2); +int iSetISCH_4TH_STA_sta_th3(unsigned int usta_th3); +int iSetISCH_4TH_STA_ch_id_th3(unsigned int uch_id_th3); +int iSetISCH_CORE0_STA_th0_his_cr(unsigned int uth0_his_cr); +int iSetISCH_CORE0_STA_th1_his_cr(unsigned int uth1_his_cr); +int iSetISCH_CORE0_STA_th2_his_cr(unsigned int uth2_his_cr); +int iSetISCH_CORE0_STA_th3_his_cr(unsigned int uth3_his_cr); +int iSetISCH_RLS_E_CNT_rls_e_err_cnt(unsigned int urls_e_err_cnt); +int iSetISCH_RLS_C_CNT_rls_c_err_cnt(unsigned int urls_c_err_cnt); +int iSetISCH_TIME_OUT_CNT_time_out_err_cnt(unsigned int utime_out_err_cnt); +int iSetISCH_RLS_E_th_id_e(unsigned int uth_id_e); +int iSetISCH_RLS_C_th_id_c(unsigned int uth_id_c); +int iSetISCH_RLS_CNT_rls_cnt(unsigned int urls_cnt); +int iSetISCH_ALC_CNT_alc_cnt(unsigned int ualc_cnt); +int iSetISCH_TL_IDLE_TH_CNT_th_idle_4tile_cnt(unsigned int uth_idle_4tile_cnt); + + +#endif // STLISCH_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlisch_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlisch_reg_offset.h new file mode 100644 index 000000000..8481ee92c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/stlisch_reg_offset.h @@ -0,0 +1,527 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : stlisch_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/05/07 10:21:41 Create file +// ****************************************************************************** + +#ifndef STLISCH_REG_OFFSET_H +#define STLISCH_REG_OFFSET_H + +/* QU_STLISCH_CSR Base address of Module's Register */ +#define CSR_QU_STLISCH_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* QU_STLISCH_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_STLISCH_CSR_CNB_INT_VECTOR_REG (CSR_QU_STLISCH_CSR_BASE + 0x0) /* 中断向量 */ +#define CSR_QU_STLISCH_CSR_ISCH_INT_REG (CSR_QU_STLISCH_CSR_BASE + 0x4) /* 中断状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_INT_EN_REG (CSR_QU_STLISCH_CSR_BASE + 0x8) /* 中断使能。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TH_RLS_E_ERROR_STATUS_REG (CSR_QU_STLISCH_CSR_BASE + 0xC) /* 释放线程ID错误 */ +#define CSR_QU_STLISCH_CSR_ISCH_TH_RLS_C_ERROR_STATUS_REG (CSR_QU_STLISCH_CSR_BASE + 0x10) /* 线程释放冲突。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TIME_OUT_ERROR_STATUS_REG (CSR_QU_STLISCH_CSR_BASE + 0x14) /* 线程占用超时中断 */ +#define CSR_QU_STLISCH_CSR_ISCH_BP_STATUS_REG (CSR_QU_STLISCH_CSR_BASE + 0x18) /* ISCH反压状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_BP_CTRL_REG (CSR_QU_STLISCH_CSR_BASE + 0x1C) /* ISCH反压控制寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_FORCE_RLS_CTRL_REG (CSR_QU_STLISCH_CSR_BASE + 0x20) /* ISCH强制释放寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_MOD_REG (CSR_QU_STLISCH_CSR_BASE + 0x24) /* ISCH模式控制寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_TILE_EN_REG (CSR_QU_STLISCH_CSR_BASE + 0x28) /* TILE使能开关 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_0_REG (CSR_QU_STLISCH_CSR_BASE + 0x30) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_1_REG (CSR_QU_STLISCH_CSR_BASE + 0x34) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_2_REG (CSR_QU_STLISCH_CSR_BASE + 0x38) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_3_REG (CSR_QU_STLISCH_CSR_BASE + 0x3C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_4_REG (CSR_QU_STLISCH_CSR_BASE + 0x40) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_5_REG (CSR_QU_STLISCH_CSR_BASE + 0x44) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_6_REG (CSR_QU_STLISCH_CSR_BASE + 0x48) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_7_REG (CSR_QU_STLISCH_CSR_BASE + 0x4C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_8_REG (CSR_QU_STLISCH_CSR_BASE + 0x50) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_9_REG (CSR_QU_STLISCH_CSR_BASE + 0x54) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_10_REG (CSR_QU_STLISCH_CSR_BASE + 0x58) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_11_REG (CSR_QU_STLISCH_CSR_BASE + 0x5C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_12_REG (CSR_QU_STLISCH_CSR_BASE + 0x60) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_13_REG (CSR_QU_STLISCH_CSR_BASE + 0x64) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_14_REG (CSR_QU_STLISCH_CSR_BASE + 0x68) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_15_REG (CSR_QU_STLISCH_CSR_BASE + 0x6C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_16_REG (CSR_QU_STLISCH_CSR_BASE + 0x70) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_17_REG (CSR_QU_STLISCH_CSR_BASE + 0x74) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_18_REG (CSR_QU_STLISCH_CSR_BASE + 0x78) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_19_REG (CSR_QU_STLISCH_CSR_BASE + 0x7C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_20_REG (CSR_QU_STLISCH_CSR_BASE + 0x80) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_21_REG (CSR_QU_STLISCH_CSR_BASE + 0x84) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_22_REG (CSR_QU_STLISCH_CSR_BASE + 0x88) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_23_REG (CSR_QU_STLISCH_CSR_BASE + 0x8C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_24_REG (CSR_QU_STLISCH_CSR_BASE + 0x90) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_25_REG (CSR_QU_STLISCH_CSR_BASE + 0x94) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_26_REG (CSR_QU_STLISCH_CSR_BASE + 0x98) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_27_REG (CSR_QU_STLISCH_CSR_BASE + 0x9C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_28_REG (CSR_QU_STLISCH_CSR_BASE + 0xA0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_29_REG (CSR_QU_STLISCH_CSR_BASE + 0xA4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_30_REG (CSR_QU_STLISCH_CSR_BASE + 0xA8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_31_REG (CSR_QU_STLISCH_CSR_BASE + 0xAC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_32_REG (CSR_QU_STLISCH_CSR_BASE + 0xB0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_33_REG (CSR_QU_STLISCH_CSR_BASE + 0xB4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_34_REG (CSR_QU_STLISCH_CSR_BASE + 0xB8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_35_REG (CSR_QU_STLISCH_CSR_BASE + 0xBC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_36_REG (CSR_QU_STLISCH_CSR_BASE + 0xC0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_37_REG (CSR_QU_STLISCH_CSR_BASE + 0xC4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_38_REG (CSR_QU_STLISCH_CSR_BASE + 0xC8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_39_REG (CSR_QU_STLISCH_CSR_BASE + 0xCC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_40_REG (CSR_QU_STLISCH_CSR_BASE + 0xD0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_41_REG (CSR_QU_STLISCH_CSR_BASE + 0xD4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_42_REG (CSR_QU_STLISCH_CSR_BASE + 0xD8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_43_REG (CSR_QU_STLISCH_CSR_BASE + 0xDC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_44_REG (CSR_QU_STLISCH_CSR_BASE + 0xE0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_45_REG (CSR_QU_STLISCH_CSR_BASE + 0xE4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_46_REG (CSR_QU_STLISCH_CSR_BASE + 0xE8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_47_REG (CSR_QU_STLISCH_CSR_BASE + 0xEC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_48_REG (CSR_QU_STLISCH_CSR_BASE + 0xF0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_49_REG (CSR_QU_STLISCH_CSR_BASE + 0xF4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_50_REG (CSR_QU_STLISCH_CSR_BASE + 0xF8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_51_REG (CSR_QU_STLISCH_CSR_BASE + 0xFC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_52_REG (CSR_QU_STLISCH_CSR_BASE + 0x100) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_53_REG (CSR_QU_STLISCH_CSR_BASE + 0x104) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_54_REG (CSR_QU_STLISCH_CSR_BASE + 0x108) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_55_REG (CSR_QU_STLISCH_CSR_BASE + 0x10C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_56_REG (CSR_QU_STLISCH_CSR_BASE + 0x110) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_57_REG (CSR_QU_STLISCH_CSR_BASE + 0x114) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_58_REG (CSR_QU_STLISCH_CSR_BASE + 0x118) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_59_REG (CSR_QU_STLISCH_CSR_BASE + 0x11C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_60_REG (CSR_QU_STLISCH_CSR_BASE + 0x120) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_61_REG (CSR_QU_STLISCH_CSR_BASE + 0x124) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_62_REG (CSR_QU_STLISCH_CSR_BASE + 0x128) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_63_REG (CSR_QU_STLISCH_CSR_BASE + 0x12C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_64_REG (CSR_QU_STLISCH_CSR_BASE + 0x130) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_65_REG (CSR_QU_STLISCH_CSR_BASE + 0x134) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_66_REG (CSR_QU_STLISCH_CSR_BASE + 0x138) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_67_REG (CSR_QU_STLISCH_CSR_BASE + 0x13C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_68_REG (CSR_QU_STLISCH_CSR_BASE + 0x140) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_69_REG (CSR_QU_STLISCH_CSR_BASE + 0x144) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_70_REG (CSR_QU_STLISCH_CSR_BASE + 0x148) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_71_REG (CSR_QU_STLISCH_CSR_BASE + 0x14C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_72_REG (CSR_QU_STLISCH_CSR_BASE + 0x150) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_73_REG (CSR_QU_STLISCH_CSR_BASE + 0x154) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_74_REG (CSR_QU_STLISCH_CSR_BASE + 0x158) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_75_REG (CSR_QU_STLISCH_CSR_BASE + 0x15C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_76_REG (CSR_QU_STLISCH_CSR_BASE + 0x160) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_77_REG (CSR_QU_STLISCH_CSR_BASE + 0x164) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_78_REG (CSR_QU_STLISCH_CSR_BASE + 0x168) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_79_REG (CSR_QU_STLISCH_CSR_BASE + 0x16C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_80_REG (CSR_QU_STLISCH_CSR_BASE + 0x170) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_81_REG (CSR_QU_STLISCH_CSR_BASE + 0x174) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_82_REG (CSR_QU_STLISCH_CSR_BASE + 0x178) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_83_REG (CSR_QU_STLISCH_CSR_BASE + 0x17C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_84_REG (CSR_QU_STLISCH_CSR_BASE + 0x180) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_85_REG (CSR_QU_STLISCH_CSR_BASE + 0x184) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_86_REG (CSR_QU_STLISCH_CSR_BASE + 0x188) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_87_REG (CSR_QU_STLISCH_CSR_BASE + 0x18C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_88_REG (CSR_QU_STLISCH_CSR_BASE + 0x190) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_89_REG (CSR_QU_STLISCH_CSR_BASE + 0x194) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_90_REG (CSR_QU_STLISCH_CSR_BASE + 0x198) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_91_REG (CSR_QU_STLISCH_CSR_BASE + 0x19C) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_92_REG (CSR_QU_STLISCH_CSR_BASE + 0x1A0) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_93_REG (CSR_QU_STLISCH_CSR_BASE + 0x1A4) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_94_REG (CSR_QU_STLISCH_CSR_BASE + 0x1A8) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_CFG_95_REG (CSR_QU_STLISCH_CSR_BASE + 0x1AC) /* core属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_0_REG (CSR_QU_STLISCH_CSR_BASE + 0x1B0) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_1_REG (CSR_QU_STLISCH_CSR_BASE + 0x1B4) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_2_REG (CSR_QU_STLISCH_CSR_BASE + 0x1B8) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_3_REG (CSR_QU_STLISCH_CSR_BASE + 0x1BC) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_4_REG (CSR_QU_STLISCH_CSR_BASE + 0x1C0) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_5_REG (CSR_QU_STLISCH_CSR_BASE + 0x1C4) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_6_REG (CSR_QU_STLISCH_CSR_BASE + 0x1C8) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_7_REG (CSR_QU_STLISCH_CSR_BASE + 0x1CC) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_8_REG (CSR_QU_STLISCH_CSR_BASE + 0x1D0) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_9_REG (CSR_QU_STLISCH_CSR_BASE + 0x1D4) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_10_REG (CSR_QU_STLISCH_CSR_BASE + 0x1D8) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_11_REG (CSR_QU_STLISCH_CSR_BASE + 0x1DC) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_12_REG (CSR_QU_STLISCH_CSR_BASE + 0x1E0) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_13_REG (CSR_QU_STLISCH_CSR_BASE + 0x1E4) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_14_REG (CSR_QU_STLISCH_CSR_BASE + 0x1E8) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_15_REG (CSR_QU_STLISCH_CSR_BASE + 0x1EC) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_16_REG (CSR_QU_STLISCH_CSR_BASE + 0x1F0) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_17_REG (CSR_QU_STLISCH_CSR_BASE + 0x1F4) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_18_REG (CSR_QU_STLISCH_CSR_BASE + 0x1F8) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_19_REG (CSR_QU_STLISCH_CSR_BASE + 0x1FC) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_20_REG (CSR_QU_STLISCH_CSR_BASE + 0x200) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_21_REG (CSR_QU_STLISCH_CSR_BASE + 0x204) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_22_REG (CSR_QU_STLISCH_CSR_BASE + 0x208) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_23_REG (CSR_QU_STLISCH_CSR_BASE + 0x20C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_24_REG (CSR_QU_STLISCH_CSR_BASE + 0x210) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_25_REG (CSR_QU_STLISCH_CSR_BASE + 0x214) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_26_REG (CSR_QU_STLISCH_CSR_BASE + 0x218) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_27_REG (CSR_QU_STLISCH_CSR_BASE + 0x21C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_28_REG (CSR_QU_STLISCH_CSR_BASE + 0x220) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_29_REG (CSR_QU_STLISCH_CSR_BASE + 0x224) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_30_REG (CSR_QU_STLISCH_CSR_BASE + 0x228) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_31_REG (CSR_QU_STLISCH_CSR_BASE + 0x22C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_32_REG (CSR_QU_STLISCH_CSR_BASE + 0x230) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_33_REG (CSR_QU_STLISCH_CSR_BASE + 0x234) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_34_REG (CSR_QU_STLISCH_CSR_BASE + 0x238) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_35_REG (CSR_QU_STLISCH_CSR_BASE + 0x23C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_36_REG (CSR_QU_STLISCH_CSR_BASE + 0x240) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_37_REG (CSR_QU_STLISCH_CSR_BASE + 0x244) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_38_REG (CSR_QU_STLISCH_CSR_BASE + 0x248) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_39_REG (CSR_QU_STLISCH_CSR_BASE + 0x24C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_40_REG (CSR_QU_STLISCH_CSR_BASE + 0x250) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_41_REG (CSR_QU_STLISCH_CSR_BASE + 0x254) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_42_REG (CSR_QU_STLISCH_CSR_BASE + 0x258) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_43_REG (CSR_QU_STLISCH_CSR_BASE + 0x25C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_44_REG (CSR_QU_STLISCH_CSR_BASE + 0x260) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_45_REG (CSR_QU_STLISCH_CSR_BASE + 0x264) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_46_REG (CSR_QU_STLISCH_CSR_BASE + 0x268) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_47_REG (CSR_QU_STLISCH_CSR_BASE + 0x26C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_48_REG (CSR_QU_STLISCH_CSR_BASE + 0x270) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_49_REG (CSR_QU_STLISCH_CSR_BASE + 0x274) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_50_REG (CSR_QU_STLISCH_CSR_BASE + 0x278) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_51_REG (CSR_QU_STLISCH_CSR_BASE + 0x27C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_52_REG (CSR_QU_STLISCH_CSR_BASE + 0x280) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_53_REG (CSR_QU_STLISCH_CSR_BASE + 0x284) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_54_REG (CSR_QU_STLISCH_CSR_BASE + 0x288) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_55_REG (CSR_QU_STLISCH_CSR_BASE + 0x28C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_56_REG (CSR_QU_STLISCH_CSR_BASE + 0x290) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_57_REG (CSR_QU_STLISCH_CSR_BASE + 0x294) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_58_REG (CSR_QU_STLISCH_CSR_BASE + 0x298) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_59_REG (CSR_QU_STLISCH_CSR_BASE + 0x29C) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_60_REG (CSR_QU_STLISCH_CSR_BASE + 0x2A0) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_61_REG (CSR_QU_STLISCH_CSR_BASE + 0x2A4) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_62_REG (CSR_QU_STLISCH_CSR_BASE + 0x2A8) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_CHANNEL_CFG_63_REG (CSR_QU_STLISCH_CSR_BASE + 0x2AC) /* channel属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_0_REG (CSR_QU_STLISCH_CSR_BASE + 0x2B0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_1_REG (CSR_QU_STLISCH_CSR_BASE + 0x2B4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_2_REG (CSR_QU_STLISCH_CSR_BASE + 0x2B8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_3_REG (CSR_QU_STLISCH_CSR_BASE + 0x2BC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_4_REG (CSR_QU_STLISCH_CSR_BASE + 0x2C0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_5_REG (CSR_QU_STLISCH_CSR_BASE + 0x2C4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_6_REG (CSR_QU_STLISCH_CSR_BASE + 0x2C8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_7_REG (CSR_QU_STLISCH_CSR_BASE + 0x2CC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_8_REG (CSR_QU_STLISCH_CSR_BASE + 0x2D0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_9_REG (CSR_QU_STLISCH_CSR_BASE + 0x2D4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_10_REG (CSR_QU_STLISCH_CSR_BASE + 0x2D8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_11_REG (CSR_QU_STLISCH_CSR_BASE + 0x2DC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_12_REG (CSR_QU_STLISCH_CSR_BASE + 0x2E0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_13_REG (CSR_QU_STLISCH_CSR_BASE + 0x2E4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_14_REG (CSR_QU_STLISCH_CSR_BASE + 0x2E8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_15_REG (CSR_QU_STLISCH_CSR_BASE + 0x2EC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_16_REG (CSR_QU_STLISCH_CSR_BASE + 0x2F0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_17_REG (CSR_QU_STLISCH_CSR_BASE + 0x2F4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_18_REG (CSR_QU_STLISCH_CSR_BASE + 0x2F8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_19_REG (CSR_QU_STLISCH_CSR_BASE + 0x2FC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_20_REG (CSR_QU_STLISCH_CSR_BASE + 0x300) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_21_REG (CSR_QU_STLISCH_CSR_BASE + 0x304) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_22_REG (CSR_QU_STLISCH_CSR_BASE + 0x308) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_23_REG (CSR_QU_STLISCH_CSR_BASE + 0x30C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_24_REG (CSR_QU_STLISCH_CSR_BASE + 0x310) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_25_REG (CSR_QU_STLISCH_CSR_BASE + 0x314) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_26_REG (CSR_QU_STLISCH_CSR_BASE + 0x318) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_27_REG (CSR_QU_STLISCH_CSR_BASE + 0x31C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_28_REG (CSR_QU_STLISCH_CSR_BASE + 0x320) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_29_REG (CSR_QU_STLISCH_CSR_BASE + 0x324) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_30_REG (CSR_QU_STLISCH_CSR_BASE + 0x328) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_31_REG (CSR_QU_STLISCH_CSR_BASE + 0x32C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_32_REG (CSR_QU_STLISCH_CSR_BASE + 0x330) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_33_REG (CSR_QU_STLISCH_CSR_BASE + 0x334) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_34_REG (CSR_QU_STLISCH_CSR_BASE + 0x338) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_35_REG (CSR_QU_STLISCH_CSR_BASE + 0x33C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_36_REG (CSR_QU_STLISCH_CSR_BASE + 0x340) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_37_REG (CSR_QU_STLISCH_CSR_BASE + 0x344) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_38_REG (CSR_QU_STLISCH_CSR_BASE + 0x348) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_39_REG (CSR_QU_STLISCH_CSR_BASE + 0x34C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_40_REG (CSR_QU_STLISCH_CSR_BASE + 0x350) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_41_REG (CSR_QU_STLISCH_CSR_BASE + 0x354) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_42_REG (CSR_QU_STLISCH_CSR_BASE + 0x358) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_43_REG (CSR_QU_STLISCH_CSR_BASE + 0x35C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_44_REG (CSR_QU_STLISCH_CSR_BASE + 0x360) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_45_REG (CSR_QU_STLISCH_CSR_BASE + 0x364) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_46_REG (CSR_QU_STLISCH_CSR_BASE + 0x368) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_47_REG (CSR_QU_STLISCH_CSR_BASE + 0x36C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_48_REG (CSR_QU_STLISCH_CSR_BASE + 0x370) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_49_REG (CSR_QU_STLISCH_CSR_BASE + 0x374) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_50_REG (CSR_QU_STLISCH_CSR_BASE + 0x378) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_51_REG (CSR_QU_STLISCH_CSR_BASE + 0x37C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_52_REG (CSR_QU_STLISCH_CSR_BASE + 0x380) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_53_REG (CSR_QU_STLISCH_CSR_BASE + 0x384) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_54_REG (CSR_QU_STLISCH_CSR_BASE + 0x388) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_55_REG (CSR_QU_STLISCH_CSR_BASE + 0x38C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_56_REG (CSR_QU_STLISCH_CSR_BASE + 0x390) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_57_REG (CSR_QU_STLISCH_CSR_BASE + 0x394) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_58_REG (CSR_QU_STLISCH_CSR_BASE + 0x398) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_59_REG (CSR_QU_STLISCH_CSR_BASE + 0x39C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_60_REG (CSR_QU_STLISCH_CSR_BASE + 0x3A0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_61_REG (CSR_QU_STLISCH_CSR_BASE + 0x3A4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_62_REG (CSR_QU_STLISCH_CSR_BASE + 0x3A8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_63_REG (CSR_QU_STLISCH_CSR_BASE + 0x3AC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_64_REG (CSR_QU_STLISCH_CSR_BASE + 0x3B0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_65_REG (CSR_QU_STLISCH_CSR_BASE + 0x3B4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_66_REG (CSR_QU_STLISCH_CSR_BASE + 0x3B8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_67_REG (CSR_QU_STLISCH_CSR_BASE + 0x3BC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_68_REG (CSR_QU_STLISCH_CSR_BASE + 0x3C0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_69_REG (CSR_QU_STLISCH_CSR_BASE + 0x3C4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_70_REG (CSR_QU_STLISCH_CSR_BASE + 0x3C8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_71_REG (CSR_QU_STLISCH_CSR_BASE + 0x3CC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_72_REG (CSR_QU_STLISCH_CSR_BASE + 0x3D0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_73_REG (CSR_QU_STLISCH_CSR_BASE + 0x3D4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_74_REG (CSR_QU_STLISCH_CSR_BASE + 0x3D8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_75_REG (CSR_QU_STLISCH_CSR_BASE + 0x3DC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_76_REG (CSR_QU_STLISCH_CSR_BASE + 0x3E0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_77_REG (CSR_QU_STLISCH_CSR_BASE + 0x3E4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_78_REG (CSR_QU_STLISCH_CSR_BASE + 0x3E8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_79_REG (CSR_QU_STLISCH_CSR_BASE + 0x3EC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_80_REG (CSR_QU_STLISCH_CSR_BASE + 0x3F0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_81_REG (CSR_QU_STLISCH_CSR_BASE + 0x3F4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_82_REG (CSR_QU_STLISCH_CSR_BASE + 0x3F8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_83_REG (CSR_QU_STLISCH_CSR_BASE + 0x3FC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_84_REG (CSR_QU_STLISCH_CSR_BASE + 0x400) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_85_REG (CSR_QU_STLISCH_CSR_BASE + 0x404) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_86_REG (CSR_QU_STLISCH_CSR_BASE + 0x408) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_87_REG (CSR_QU_STLISCH_CSR_BASE + 0x40C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_88_REG (CSR_QU_STLISCH_CSR_BASE + 0x410) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_89_REG (CSR_QU_STLISCH_CSR_BASE + 0x414) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_90_REG (CSR_QU_STLISCH_CSR_BASE + 0x418) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_91_REG (CSR_QU_STLISCH_CSR_BASE + 0x41C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_92_REG (CSR_QU_STLISCH_CSR_BASE + 0x420) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_93_REG (CSR_QU_STLISCH_CSR_BASE + 0x424) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_94_REG (CSR_QU_STLISCH_CSR_BASE + 0x428) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_95_REG (CSR_QU_STLISCH_CSR_BASE + 0x42C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_96_REG (CSR_QU_STLISCH_CSR_BASE + 0x430) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_97_REG (CSR_QU_STLISCH_CSR_BASE + 0x434) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_98_REG (CSR_QU_STLISCH_CSR_BASE + 0x438) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_99_REG (CSR_QU_STLISCH_CSR_BASE + 0x43C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_100_REG (CSR_QU_STLISCH_CSR_BASE + 0x440) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_101_REG (CSR_QU_STLISCH_CSR_BASE + 0x444) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_102_REG (CSR_QU_STLISCH_CSR_BASE + 0x448) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_103_REG (CSR_QU_STLISCH_CSR_BASE + 0x44C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_104_REG (CSR_QU_STLISCH_CSR_BASE + 0x450) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_105_REG (CSR_QU_STLISCH_CSR_BASE + 0x454) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_106_REG (CSR_QU_STLISCH_CSR_BASE + 0x458) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_107_REG (CSR_QU_STLISCH_CSR_BASE + 0x45C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_108_REG (CSR_QU_STLISCH_CSR_BASE + 0x460) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_109_REG (CSR_QU_STLISCH_CSR_BASE + 0x464) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_110_REG (CSR_QU_STLISCH_CSR_BASE + 0x468) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_111_REG (CSR_QU_STLISCH_CSR_BASE + 0x46C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_112_REG (CSR_QU_STLISCH_CSR_BASE + 0x470) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_113_REG (CSR_QU_STLISCH_CSR_BASE + 0x474) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_114_REG (CSR_QU_STLISCH_CSR_BASE + 0x478) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_115_REG (CSR_QU_STLISCH_CSR_BASE + 0x47C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_116_REG (CSR_QU_STLISCH_CSR_BASE + 0x480) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_117_REG (CSR_QU_STLISCH_CSR_BASE + 0x484) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_118_REG (CSR_QU_STLISCH_CSR_BASE + 0x488) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_119_REG (CSR_QU_STLISCH_CSR_BASE + 0x48C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_120_REG (CSR_QU_STLISCH_CSR_BASE + 0x490) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_121_REG (CSR_QU_STLISCH_CSR_BASE + 0x494) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_122_REG (CSR_QU_STLISCH_CSR_BASE + 0x498) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_123_REG (CSR_QU_STLISCH_CSR_BASE + 0x49C) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_124_REG (CSR_QU_STLISCH_CSR_BASE + 0x4A0) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_125_REG (CSR_QU_STLISCH_CSR_BASE + 0x4A4) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_126_REG (CSR_QU_STLISCH_CSR_BASE + 0x4A8) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4IQ_CFG_127_REG (CSR_QU_STLISCH_CSR_BASE + 0x4AC) /* IQ属性配置 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_0_REG (CSR_QU_STLISCH_CSR_BASE + 0x4B0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_1_REG (CSR_QU_STLISCH_CSR_BASE + 0x4B4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_2_REG (CSR_QU_STLISCH_CSR_BASE + 0x4B8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_3_REG (CSR_QU_STLISCH_CSR_BASE + 0x4BC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_4_REG (CSR_QU_STLISCH_CSR_BASE + 0x4C0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_5_REG (CSR_QU_STLISCH_CSR_BASE + 0x4C4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_6_REG (CSR_QU_STLISCH_CSR_BASE + 0x4C8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_7_REG (CSR_QU_STLISCH_CSR_BASE + 0x4CC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_8_REG (CSR_QU_STLISCH_CSR_BASE + 0x4D0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_9_REG (CSR_QU_STLISCH_CSR_BASE + 0x4D4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_10_REG (CSR_QU_STLISCH_CSR_BASE + 0x4D8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_11_REG (CSR_QU_STLISCH_CSR_BASE + 0x4DC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_12_REG (CSR_QU_STLISCH_CSR_BASE + 0x4E0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_13_REG (CSR_QU_STLISCH_CSR_BASE + 0x4E4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_14_REG (CSR_QU_STLISCH_CSR_BASE + 0x4E8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_15_REG (CSR_QU_STLISCH_CSR_BASE + 0x4EC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_16_REG (CSR_QU_STLISCH_CSR_BASE + 0x4F0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_17_REG (CSR_QU_STLISCH_CSR_BASE + 0x4F4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_18_REG (CSR_QU_STLISCH_CSR_BASE + 0x4F8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_19_REG (CSR_QU_STLISCH_CSR_BASE + 0x4FC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_20_REG (CSR_QU_STLISCH_CSR_BASE + 0x500) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_21_REG (CSR_QU_STLISCH_CSR_BASE + 0x504) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_22_REG (CSR_QU_STLISCH_CSR_BASE + 0x508) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_23_REG (CSR_QU_STLISCH_CSR_BASE + 0x50C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_24_REG (CSR_QU_STLISCH_CSR_BASE + 0x510) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_25_REG (CSR_QU_STLISCH_CSR_BASE + 0x514) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_26_REG (CSR_QU_STLISCH_CSR_BASE + 0x518) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_27_REG (CSR_QU_STLISCH_CSR_BASE + 0x51C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_28_REG (CSR_QU_STLISCH_CSR_BASE + 0x520) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_29_REG (CSR_QU_STLISCH_CSR_BASE + 0x524) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_30_REG (CSR_QU_STLISCH_CSR_BASE + 0x528) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_31_REG (CSR_QU_STLISCH_CSR_BASE + 0x52C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_32_REG (CSR_QU_STLISCH_CSR_BASE + 0x530) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_33_REG (CSR_QU_STLISCH_CSR_BASE + 0x534) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_34_REG (CSR_QU_STLISCH_CSR_BASE + 0x538) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_35_REG (CSR_QU_STLISCH_CSR_BASE + 0x53C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_36_REG (CSR_QU_STLISCH_CSR_BASE + 0x540) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_37_REG (CSR_QU_STLISCH_CSR_BASE + 0x544) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_38_REG (CSR_QU_STLISCH_CSR_BASE + 0x548) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_39_REG (CSR_QU_STLISCH_CSR_BASE + 0x54C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_40_REG (CSR_QU_STLISCH_CSR_BASE + 0x550) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_41_REG (CSR_QU_STLISCH_CSR_BASE + 0x554) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_42_REG (CSR_QU_STLISCH_CSR_BASE + 0x558) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_43_REG (CSR_QU_STLISCH_CSR_BASE + 0x55C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_44_REG (CSR_QU_STLISCH_CSR_BASE + 0x560) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_45_REG (CSR_QU_STLISCH_CSR_BASE + 0x564) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_46_REG (CSR_QU_STLISCH_CSR_BASE + 0x568) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_47_REG (CSR_QU_STLISCH_CSR_BASE + 0x56C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_48_REG (CSR_QU_STLISCH_CSR_BASE + 0x570) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_49_REG (CSR_QU_STLISCH_CSR_BASE + 0x574) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_50_REG (CSR_QU_STLISCH_CSR_BASE + 0x578) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_51_REG (CSR_QU_STLISCH_CSR_BASE + 0x57C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_52_REG (CSR_QU_STLISCH_CSR_BASE + 0x580) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_53_REG (CSR_QU_STLISCH_CSR_BASE + 0x584) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_54_REG (CSR_QU_STLISCH_CSR_BASE + 0x588) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_55_REG (CSR_QU_STLISCH_CSR_BASE + 0x58C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_56_REG (CSR_QU_STLISCH_CSR_BASE + 0x590) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_57_REG (CSR_QU_STLISCH_CSR_BASE + 0x594) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_58_REG (CSR_QU_STLISCH_CSR_BASE + 0x598) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_59_REG (CSR_QU_STLISCH_CSR_BASE + 0x59C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_60_REG (CSR_QU_STLISCH_CSR_BASE + 0x5A0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_61_REG (CSR_QU_STLISCH_CSR_BASE + 0x5A4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_62_REG (CSR_QU_STLISCH_CSR_BASE + 0x5A8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_63_REG (CSR_QU_STLISCH_CSR_BASE + 0x5AC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_64_REG (CSR_QU_STLISCH_CSR_BASE + 0x5B0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_65_REG (CSR_QU_STLISCH_CSR_BASE + 0x5B4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_66_REG (CSR_QU_STLISCH_CSR_BASE + 0x5B8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_67_REG (CSR_QU_STLISCH_CSR_BASE + 0x5BC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_68_REG (CSR_QU_STLISCH_CSR_BASE + 0x5C0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_69_REG (CSR_QU_STLISCH_CSR_BASE + 0x5C4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_70_REG (CSR_QU_STLISCH_CSR_BASE + 0x5C8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_71_REG (CSR_QU_STLISCH_CSR_BASE + 0x5CC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_72_REG (CSR_QU_STLISCH_CSR_BASE + 0x5D0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_73_REG (CSR_QU_STLISCH_CSR_BASE + 0x5D4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_74_REG (CSR_QU_STLISCH_CSR_BASE + 0x5D8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_75_REG (CSR_QU_STLISCH_CSR_BASE + 0x5DC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_76_REG (CSR_QU_STLISCH_CSR_BASE + 0x5E0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_77_REG (CSR_QU_STLISCH_CSR_BASE + 0x5E4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_78_REG (CSR_QU_STLISCH_CSR_BASE + 0x5E8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_79_REG (CSR_QU_STLISCH_CSR_BASE + 0x5EC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_80_REG (CSR_QU_STLISCH_CSR_BASE + 0x5F0) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_81_REG (CSR_QU_STLISCH_CSR_BASE + 0x5F4) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_82_REG (CSR_QU_STLISCH_CSR_BASE + 0x5F8) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_83_REG (CSR_QU_STLISCH_CSR_BASE + 0x5FC) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_84_REG (CSR_QU_STLISCH_CSR_BASE + 0x600) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_85_REG (CSR_QU_STLISCH_CSR_BASE + 0x604) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_86_REG (CSR_QU_STLISCH_CSR_BASE + 0x608) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_87_REG (CSR_QU_STLISCH_CSR_BASE + 0x60C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_88_REG (CSR_QU_STLISCH_CSR_BASE + 0x610) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_89_REG (CSR_QU_STLISCH_CSR_BASE + 0x614) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_90_REG (CSR_QU_STLISCH_CSR_BASE + 0x618) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_91_REG (CSR_QU_STLISCH_CSR_BASE + 0x61C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_92_REG (CSR_QU_STLISCH_CSR_BASE + 0x620) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_93_REG (CSR_QU_STLISCH_CSR_BASE + 0x624) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_94_REG (CSR_QU_STLISCH_CSR_BASE + 0x628) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_4TH_STA_95_REG (CSR_QU_STLISCH_CSR_BASE + 0x62C) /* 线程状态寄存器 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_0_REG (CSR_QU_STLISCH_CSR_BASE + 0x6D0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_1_REG (CSR_QU_STLISCH_CSR_BASE + 0x6D4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_2_REG (CSR_QU_STLISCH_CSR_BASE + 0x6D8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_3_REG (CSR_QU_STLISCH_CSR_BASE + 0x6DC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_4_REG (CSR_QU_STLISCH_CSR_BASE + 0x6E0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_5_REG (CSR_QU_STLISCH_CSR_BASE + 0x6E4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_6_REG (CSR_QU_STLISCH_CSR_BASE + 0x6E8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_7_REG (CSR_QU_STLISCH_CSR_BASE + 0x6EC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_8_REG (CSR_QU_STLISCH_CSR_BASE + 0x6F0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_9_REG (CSR_QU_STLISCH_CSR_BASE + 0x6F4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_10_REG (CSR_QU_STLISCH_CSR_BASE + 0x6F8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_11_REG (CSR_QU_STLISCH_CSR_BASE + 0x6FC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_12_REG (CSR_QU_STLISCH_CSR_BASE + 0x700) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_13_REG (CSR_QU_STLISCH_CSR_BASE + 0x704) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_14_REG (CSR_QU_STLISCH_CSR_BASE + 0x708) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_15_REG (CSR_QU_STLISCH_CSR_BASE + 0x70C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_16_REG (CSR_QU_STLISCH_CSR_BASE + 0x710) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_17_REG (CSR_QU_STLISCH_CSR_BASE + 0x714) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_18_REG (CSR_QU_STLISCH_CSR_BASE + 0x718) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_19_REG (CSR_QU_STLISCH_CSR_BASE + 0x71C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_20_REG (CSR_QU_STLISCH_CSR_BASE + 0x720) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_21_REG (CSR_QU_STLISCH_CSR_BASE + 0x724) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_22_REG (CSR_QU_STLISCH_CSR_BASE + 0x728) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_23_REG (CSR_QU_STLISCH_CSR_BASE + 0x72C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_24_REG (CSR_QU_STLISCH_CSR_BASE + 0x730) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_25_REG (CSR_QU_STLISCH_CSR_BASE + 0x734) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_26_REG (CSR_QU_STLISCH_CSR_BASE + 0x738) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_27_REG (CSR_QU_STLISCH_CSR_BASE + 0x73C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_28_REG (CSR_QU_STLISCH_CSR_BASE + 0x740) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_29_REG (CSR_QU_STLISCH_CSR_BASE + 0x744) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_30_REG (CSR_QU_STLISCH_CSR_BASE + 0x748) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_31_REG (CSR_QU_STLISCH_CSR_BASE + 0x74C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_32_REG (CSR_QU_STLISCH_CSR_BASE + 0x750) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_33_REG (CSR_QU_STLISCH_CSR_BASE + 0x754) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_34_REG (CSR_QU_STLISCH_CSR_BASE + 0x758) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_35_REG (CSR_QU_STLISCH_CSR_BASE + 0x75C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_36_REG (CSR_QU_STLISCH_CSR_BASE + 0x760) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_37_REG (CSR_QU_STLISCH_CSR_BASE + 0x764) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_38_REG (CSR_QU_STLISCH_CSR_BASE + 0x768) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_39_REG (CSR_QU_STLISCH_CSR_BASE + 0x76C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_40_REG (CSR_QU_STLISCH_CSR_BASE + 0x770) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_41_REG (CSR_QU_STLISCH_CSR_BASE + 0x774) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_42_REG (CSR_QU_STLISCH_CSR_BASE + 0x778) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_43_REG (CSR_QU_STLISCH_CSR_BASE + 0x77C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_44_REG (CSR_QU_STLISCH_CSR_BASE + 0x780) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_45_REG (CSR_QU_STLISCH_CSR_BASE + 0x784) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_46_REG (CSR_QU_STLISCH_CSR_BASE + 0x788) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_47_REG (CSR_QU_STLISCH_CSR_BASE + 0x78C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_48_REG (CSR_QU_STLISCH_CSR_BASE + 0x790) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_49_REG (CSR_QU_STLISCH_CSR_BASE + 0x794) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_50_REG (CSR_QU_STLISCH_CSR_BASE + 0x798) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_51_REG (CSR_QU_STLISCH_CSR_BASE + 0x79C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_52_REG (CSR_QU_STLISCH_CSR_BASE + 0x7A0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_53_REG (CSR_QU_STLISCH_CSR_BASE + 0x7A4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_54_REG (CSR_QU_STLISCH_CSR_BASE + 0x7A8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_55_REG (CSR_QU_STLISCH_CSR_BASE + 0x7AC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_56_REG (CSR_QU_STLISCH_CSR_BASE + 0x7B0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_57_REG (CSR_QU_STLISCH_CSR_BASE + 0x7B4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_58_REG (CSR_QU_STLISCH_CSR_BASE + 0x7B8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_59_REG (CSR_QU_STLISCH_CSR_BASE + 0x7BC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_60_REG (CSR_QU_STLISCH_CSR_BASE + 0x7C0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_61_REG (CSR_QU_STLISCH_CSR_BASE + 0x7C4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_62_REG (CSR_QU_STLISCH_CSR_BASE + 0x7C8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_63_REG (CSR_QU_STLISCH_CSR_BASE + 0x7CC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_64_REG (CSR_QU_STLISCH_CSR_BASE + 0x7D0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_65_REG (CSR_QU_STLISCH_CSR_BASE + 0x7D4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_66_REG (CSR_QU_STLISCH_CSR_BASE + 0x7D8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_67_REG (CSR_QU_STLISCH_CSR_BASE + 0x7DC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_68_REG (CSR_QU_STLISCH_CSR_BASE + 0x7E0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_69_REG (CSR_QU_STLISCH_CSR_BASE + 0x7E4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_70_REG (CSR_QU_STLISCH_CSR_BASE + 0x7E8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_71_REG (CSR_QU_STLISCH_CSR_BASE + 0x7EC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_72_REG (CSR_QU_STLISCH_CSR_BASE + 0x7F0) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_73_REG (CSR_QU_STLISCH_CSR_BASE + 0x7F4) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_74_REG (CSR_QU_STLISCH_CSR_BASE + 0x7F8) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_75_REG (CSR_QU_STLISCH_CSR_BASE + 0x7FC) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_76_REG (CSR_QU_STLISCH_CSR_BASE + 0x800) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_77_REG (CSR_QU_STLISCH_CSR_BASE + 0x804) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_78_REG (CSR_QU_STLISCH_CSR_BASE + 0x808) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_79_REG (CSR_QU_STLISCH_CSR_BASE + 0x80C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_80_REG (CSR_QU_STLISCH_CSR_BASE + 0x810) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_81_REG (CSR_QU_STLISCH_CSR_BASE + 0x814) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_82_REG (CSR_QU_STLISCH_CSR_BASE + 0x818) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_83_REG (CSR_QU_STLISCH_CSR_BASE + 0x81C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_84_REG (CSR_QU_STLISCH_CSR_BASE + 0x820) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_85_REG (CSR_QU_STLISCH_CSR_BASE + 0x824) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_86_REG (CSR_QU_STLISCH_CSR_BASE + 0x828) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_87_REG (CSR_QU_STLISCH_CSR_BASE + 0x82C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_88_REG (CSR_QU_STLISCH_CSR_BASE + 0x830) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_89_REG (CSR_QU_STLISCH_CSR_BASE + 0x834) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_90_REG (CSR_QU_STLISCH_CSR_BASE + 0x838) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_91_REG (CSR_QU_STLISCH_CSR_BASE + 0x83C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_92_REG (CSR_QU_STLISCH_CSR_BASE + 0x840) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_93_REG (CSR_QU_STLISCH_CSR_BASE + 0x844) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_94_REG (CSR_QU_STLISCH_CSR_BASE + 0x848) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_CORE0_STA_95_REG (CSR_QU_STLISCH_CSR_BASE + 0x84C) /* core线程watch_dog状态 */ +#define CSR_QU_STLISCH_CSR_ISCH_RLS_E_CNT_REG (CSR_QU_STLISCH_CSR_BASE + 0x850) /* 释放线程ID不存在错误计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_RLS_C_CNT_REG (CSR_QU_STLISCH_CSR_BASE + 0x854) /* 释放线程状态错误计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TIME_OUT_CNT_REG (CSR_QU_STLISCH_CSR_BASE + 0x858) /* 超时错误计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_RLS_E_REG (CSR_QU_STLISCH_CSR_BASE + 0x85C) /* 释放线程ID不存在错误线程。 */ +#define CSR_QU_STLISCH_CSR_ISCH_RLS_C_REG (CSR_QU_STLISCH_CSR_BASE + 0x860) /* 释放线程状态错误线程。 */ +#define CSR_QU_STLISCH_CSR_ISCH_RLS_CNT_REG (CSR_QU_STLISCH_CSR_BASE + 0x864) /* 释放线程状态错误计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_ALC_CNT_REG (CSR_QU_STLISCH_CSR_BASE + 0x868) /* 超时错误计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TL_IDLE_TH_CNT_0_REG (CSR_QU_STLISCH_CSR_BASE + 0x870) /* 分配线程总数计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TL_IDLE_TH_CNT_1_REG (CSR_QU_STLISCH_CSR_BASE + 0x874) /* 分配线程总数计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TL_IDLE_TH_CNT_2_REG (CSR_QU_STLISCH_CSR_BASE + 0x878) /* 分配线程总数计数器。 */ +#define CSR_QU_STLISCH_CSR_ISCH_TL_IDLE_TH_CNT_3_REG (CSR_QU_STLISCH_CSR_BASE + 0x87C) /* 分配线程总数计数器。 */ + +#endif // STLISCH_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/tile_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/tile_c_union_define.h new file mode 100644 index 000000000..a2f55e63b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/tile_c_union_define.h @@ -0,0 +1,3399 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : SD5860_sd5860_typedef.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/09/18 10:05:20 Create file +// ****************************************************************************** + +#ifndef HI1823_C_UNION_DEFINE_H +#define HI1823_C_UNION_DEFINE_H + +/* Define the union csr_tile_l2i_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_version_u; + +/* Define the union csr_tile_l2i_preload_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_preload_en : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_preload_en_u; + +/* Define the union csr_tile_l2i_preload_start_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_preload_start_addr : 27; /* [26:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_preload_start_addr_u; + +/* Define the union csr_tile_l2i_preload_cacheline_num_m1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_preload_cacheline_num_m1 : 11; /* [10:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_preload_cacheline_num_m1_u; + +/* Define the union csr_tile_l2i_fetch_api_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_tag_l : 12; /* [11:0] */ + u32 instance_id : 6; /* [17:12] */ + u32 rsv_0 : 2; /* [19:18] */ + u32 vcache_sel : 4; /* [23:20] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_fetch_api_cfg_u; + +/* Define the union csr_tile_l2i_imr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imr : 24; /* [23:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_imr_cfg_u; + +/* Define the union csr_tile_l2i_timeout_thd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timeout_thd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_thd_u; + +/* Define the union csr_tile_l2i_int_0_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_int_0_vector_u; + +/* Define the union csr_tile_l2i_int_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 8; /* [7:0] */ + u32 rsv_4 : 8; /* [15:8] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_int_0_u; + +/* Define the union csr_tile_l2i_int_0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 8; /* [7:0] */ + u32 rsv_5 : 8; /* [15:8] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_int_0_mask_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm0_timeout_err0 : 1; /* [0] */ + u32 qcm0_timeout_merr0 : 1; /* [1] */ + u32 qcm0_timeout_err1 : 1; /* [2] */ + u32 qcm0_timeout_merr1 : 1; /* [3] */ + u32 qcm0_timeout_err2 : 1; /* [4] */ + u32 qcm0_timeout_merr2 : 1; /* [5] */ + u32 qcm0_timeout_err3 : 1; /* [6] */ + u32 qcm0_timeout_merr3 : 1; /* [7] */ + u32 qcm0_timeout_err4 : 1; /* [8] */ + u32 qcm0_timeout_merr4 : 1; /* [9] */ + u32 qcm0_timeout_err5 : 1; /* [10] */ + u32 qcm0_timeout_merr5 : 1; /* [11] */ + u32 qcm0_timeout_err6 : 1; /* [12] */ + u32 qcm0_timeout_merr6 : 1; /* [13] */ + u32 qcm0_timeout_err7 : 1; /* [14] */ + u32 qcm0_timeout_merr7 : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm0_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm0_timeout_err0_mask : 1; /* [0] */ + u32 qcm0_timeout_err1_mask : 1; /* [1] */ + u32 qcm0_timeout_err2_mask : 1; /* [2] */ + u32 qcm0_timeout_err3_mask : 1; /* [3] */ + u32 qcm0_timeout_err4_mask : 1; /* [4] */ + u32 qcm0_timeout_err5_mask : 1; /* [5] */ + u32 qcm0_timeout_err6_mask : 1; /* [6] */ + u32 qcm0_timeout_err7_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm0_mask_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm1_timeout_err0 : 1; /* [0] */ + u32 qcm1_timeout_merr0 : 1; /* [1] */ + u32 qcm1_timeout_err1 : 1; /* [2] */ + u32 qcm1_timeout_merr1 : 1; /* [3] */ + u32 qcm1_timeout_err2 : 1; /* [4] */ + u32 qcm1_timeout_merr2 : 1; /* [5] */ + u32 qcm1_timeout_err3 : 1; /* [6] */ + u32 qcm1_timeout_merr3 : 1; /* [7] */ + u32 qcm1_timeout_err4 : 1; /* [8] */ + u32 qcm1_timeout_merr4 : 1; /* [9] */ + u32 qcm1_timeout_err5 : 1; /* [10] */ + u32 qcm1_timeout_merr5 : 1; /* [11] */ + u32 qcm1_timeout_err6 : 1; /* [12] */ + u32 qcm1_timeout_merr6 : 1; /* [13] */ + u32 qcm1_timeout_err7 : 1; /* [14] */ + u32 qcm1_timeout_merr7 : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm1_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm1_timeout_err0_mask : 1; /* [0] */ + u32 qcm1_timeout_err1_mask : 1; /* [1] */ + u32 qcm1_timeout_err2_mask : 1; /* [2] */ + u32 qcm1_timeout_err3_mask : 1; /* [3] */ + u32 qcm1_timeout_err4_mask : 1; /* [4] */ + u32 qcm1_timeout_err5_mask : 1; /* [5] */ + u32 qcm1_timeout_err6_mask : 1; /* [6] */ + u32 qcm1_timeout_err7_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm1_mask_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm2_timeout_err0 : 1; /* [0] */ + u32 qcm2_timeout_merr0 : 1; /* [1] */ + u32 qcm2_timeout_err1 : 1; /* [2] */ + u32 qcm2_timeout_merr1 : 1; /* [3] */ + u32 qcm2_timeout_err2 : 1; /* [4] */ + u32 qcm2_timeout_merr2 : 1; /* [5] */ + u32 qcm2_timeout_err3 : 1; /* [6] */ + u32 qcm2_timeout_merr3 : 1; /* [7] */ + u32 qcm2_timeout_err4 : 1; /* [8] */ + u32 qcm2_timeout_merr4 : 1; /* [9] */ + u32 qcm2_timeout_err5 : 1; /* [10] */ + u32 qcm2_timeout_merr5 : 1; /* [11] */ + u32 qcm2_timeout_err6 : 1; /* [12] */ + u32 qcm2_timeout_merr6 : 1; /* [13] */ + u32 qcm2_timeout_err7 : 1; /* [14] */ + u32 qcm2_timeout_merr7 : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm2_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm2_timeout_err0_mask : 1; /* [0] */ + u32 qcm2_timeout_err1_mask : 1; /* [1] */ + u32 qcm2_timeout_err2_mask : 1; /* [2] */ + u32 qcm2_timeout_err3_mask : 1; /* [3] */ + u32 qcm2_timeout_err4_mask : 1; /* [4] */ + u32 qcm2_timeout_err5_mask : 1; /* [5] */ + u32 qcm2_timeout_err6_mask : 1; /* [6] */ + u32 qcm2_timeout_err7_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm2_mask_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm3_timeout_err0 : 1; /* [0] */ + u32 qcm3_timeout_merr0 : 1; /* [1] */ + u32 qcm3_timeout_err1 : 1; /* [2] */ + u32 qcm3_timeout_merr1 : 1; /* [3] */ + u32 qcm3_timeout_err2 : 1; /* [4] */ + u32 qcm3_timeout_merr2 : 1; /* [5] */ + u32 qcm3_timeout_err3 : 1; /* [6] */ + u32 qcm3_timeout_merr3 : 1; /* [7] */ + u32 qcm3_timeout_err4 : 1; /* [8] */ + u32 qcm3_timeout_merr4 : 1; /* [9] */ + u32 qcm3_timeout_err5 : 1; /* [10] */ + u32 qcm3_timeout_merr5 : 1; /* [11] */ + u32 qcm3_timeout_err6 : 1; /* [12] */ + u32 qcm3_timeout_merr6 : 1; /* [13] */ + u32 qcm3_timeout_err7 : 1; /* [14] */ + u32 qcm3_timeout_merr7 : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm3_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm3_timeout_rr0_mask : 1; /* [0] */ + u32 qcm3_timeout_err1_mask : 1; /* [1] */ + u32 qcm3_timeout_err2_mask : 1; /* [2] */ + u32 qcm3_timeout_err3_mask : 1; /* [3] */ + u32 qcm3_timeout_err4_mask : 1; /* [4] */ + u32 qcm3_timeout_err5_mask : 1; /* [5] */ + u32 qcm3_timeout_err6_mask : 1; /* [6] */ + u32 qcm3_timeout_err7_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm3_mask_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm4_timeout_err0 : 1; /* [0] */ + u32 qcm4_timeout_merr0 : 1; /* [1] */ + u32 qcm4_timeout_err1 : 1; /* [2] */ + u32 qcm4_timeout_merr1 : 1; /* [3] */ + u32 qcm4_timeout_err2 : 1; /* [4] */ + u32 qcm4_timeout_merr2 : 1; /* [5] */ + u32 qcm4_timeout_err3 : 1; /* [6] */ + u32 qcm4_timeout_merr3 : 1; /* [7] */ + u32 qcm4_timeout_err4 : 1; /* [8] */ + u32 qcm4_timeout_merr4 : 1; /* [9] */ + u32 qcm4_timeout_err5 : 1; /* [10] */ + u32 qcm4_timeout_merr5 : 1; /* [11] */ + u32 qcm4_timeout_err6 : 1; /* [12] */ + u32 qcm4_timeout_merr6 : 1; /* [13] */ + u32 qcm4_timeout_err7 : 1; /* [14] */ + u32 qcm4_timeout_merr7 : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm4_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm4_timeout_err0_mask : 1; /* [0] */ + u32 qcm4_timeout_err1_mask : 1; /* [1] */ + u32 qcm4_timeout_err2_mask : 1; /* [2] */ + u32 qcm4_timeout_err3_mask : 1; /* [3] */ + u32 qcm4_timeout_err4_mask : 1; /* [4] */ + u32 qcm4_timeout_err5_mask : 1; /* [5] */ + u32 qcm4_timeout_err6_mask : 1; /* [6] */ + u32 qcm4_timeout_err7_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm4_mask_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm5_timeout_err0 : 1; /* [0] */ + u32 qcm5_timeout_merr0 : 1; /* [1] */ + u32 qcm5_timeout_err1 : 1; /* [2] */ + u32 qcm5_timeout_merr1 : 1; /* [3] */ + u32 qcm5_timeout_err2 : 1; /* [4] */ + u32 qcm5_timeout_merr2 : 1; /* [5] */ + u32 qcm5_timeout_err3 : 1; /* [6] */ + u32 qcm5_timeout_merr3 : 1; /* [7] */ + u32 qcm5_timeout_err4 : 1; /* [8] */ + u32 qcm5_timeout_merr4 : 1; /* [9] */ + u32 qcm5_timeout_err5 : 1; /* [10] */ + u32 qcm5_timeout_merr5 : 1; /* [11] */ + u32 qcm5_timeout_err6 : 1; /* [12] */ + u32 qcm5_timeout_merr6 : 1; /* [13] */ + u32 qcm5_timeout_err7 : 1; /* [14] */ + u32 qcm5_timeout_merr7 : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm5_u; + +/* Define the union csr_tile_l2i_timeout_err_qcm5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qcm5_timeout_err0_mask : 1; /* [0] */ + u32 qcm5_timeout_err1_mask : 1; /* [1] */ + u32 qcm5_timeout_err2_mask : 1; /* [2] */ + u32 qcm5_timeout_err3_mask : 1; /* [3] */ + u32 qcm5_timeout_err4_mask : 1; /* [4] */ + u32 qcm5_timeout_err5_mask : 1; /* [5] */ + u32 qcm5_timeout_err6_mask : 1; /* [6] */ + u32 qcm5_timeout_err7_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_timeout_err_qcm5_mask_u; + +/* Define the union csr_tile_l2i_mem_1bit_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 12; /* [13:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_mem_1bit_ecc_err_u; + +/* Define the union csr_tile_l2i_mem_2bit_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 12; /* [13:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_mem_2bit_ecc_err_u; + +/* Define the union csr_tile_l2i_perf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_perf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_perf_cnt_u; + +/* Define the union csr_tile_l2i_init_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_init_en : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_init_en_u; + +/* Define the union csr_tile_l2i_done_hist_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2i_init_done : 1; /* [0] */ + u32 l2i_preload_done : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_done_hist_u; + +/* Define the union csr_tile_l2i_sp_ram_tmod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_sp_ram_tmod : 7; /* [6:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_sp_ram_tmod_u; + +/* Define the union csr_tile_l2i_clr_v_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_clr_v_flag : 1; /* [0] */ + u32 rsv_6 : 3; /* [3:1] */ + u32 tile_l2i_clr_v_flag_id : 6; /* [9:4] */ + u32 rsv_7 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_clr_v_flag_u; + +/* Define the union csr_tile_l2i_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_refill_mod : 1; /* [0] */ + u32 rsv_8 : 3; /* [3:1] */ + u32 tile_l2i_bypass : 4; /* [7:4] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_mod_u; + +/* Define the union csr_l2i_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2i_indrect_addr : 8; /* [7:0] */ + u32 rsv_10 : 16; /* [23:8] */ + u32 l2i_indrect_tab : 3; /* [26:24] */ + u32 rsv_11 : 1; /* [27] */ + u32 l2i_indrect_status : 2; /* [29:28] */ + u32 l2i_indrect_mode : 1; /* [30] */ + u32 l2i_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_l2i_indrect_ctrl_u; + +/* Define the union csr_l2i_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2i_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_l2i_indrect_timeout_u; + +/* Define the union csr_l2i_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2i_indrect_data : 24; /* [23:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_l2i_indrect_data_u; + +/* Define the union csr_tile_l2i_ecc_err_inj_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_ecc_err_inj_0 : 24; /* [23:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_ecc_err_inj_0_u; + +/* Define the union csr_tile_l2i_ecc_err_inj_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_l2i_ecc_err_inj_1 : 24; /* [23:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_ecc_err_inj_1_u; + +/* Define the union csr_tile_l2i_miss_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data : 27; /* [26:0] */ + u32 trigger_enable : 1; /* [27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_miss_addr_u; + +/* Define the union csr_tile_l2i_imr_ext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imr_smf_0 : 2; /* [1:0] */ + u32 imr_smf_1 : 2; /* [3:2] */ + u32 imr_smf_2 : 2; /* [5:4] */ + u32 imr_smf_3 : 2; /* [7:6] */ + u32 imr_node_n : 2; /* [9:8] */ + u32 rsv_12 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_l2i_imr_ext_u; + + +/* Define the union csr_ppe_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_version_u; + +/* Define the union csr_ppe_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_timeout_en : 1; /* [0] */ + u32 rx_meta_wd_base_offset : 2; /* [2:1] */ + u32 tx_meta_wd_base_offset : 2; /* [4:3] */ + u32 rp_tile_tiu_wakeup_gen : 1; /* [5] */ + u32 pw_mw_out_of_range_chk_en : 1; /* [6] */ + u32 upgrade_online_en : 1; /* [7] */ + u32 ppe_prog_exe_long_clr : 1; /* [8] */ + u32 ppe_prog_num_clr : 1; /* [9] */ + u32 ppe_err_num_clr : 1; /* [10] */ + u32 rsv_0 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_cfg_u; + +/* Define the union csr_ppe_timeout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_timeout_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_timeout_cfg_u; + +/* Define the union csr_ppe_mem_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_ram_tmod : 7; /* [6:0] */ + u32 rsv_1 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_mem_cfg_u; + +/* Define the union csr_ppe_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_int_vector_u; + +/* Define the union csr_ppe_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_4 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_int_u; + +/* Define the union csr_ppe_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_5 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_int_mask_u; + +/* Define the union csr_ppe_mem_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 se_imem_2b_ecc_err : 1; /* [0] */ + u32 se_imem_2b_ecc_merr : 1; /* [1] */ + u32 se_imem_1b_ecc_err : 1; /* [2] */ + u32 se_imem_1b_ecc_merr : 1; /* [3] */ + u32 be_iss0_imem_2b_ecc_err : 1; /* [4] */ + u32 be_iss0_imem_2b_ecc_merr : 1; /* [5] */ + u32 be_iss0_imem_1b_ecc_err : 1; /* [6] */ + u32 be_iss0_imem_1b_ecc_merr : 1; /* [7] */ + u32 be_iss1_imem_2b_ecc_err : 1; /* [8] */ + u32 be_iss1_imem_2b_ecc_merr : 1; /* [9] */ + u32 be_iss1_imem_1b_ecc_err : 1; /* [10] */ + u32 be_iss1_imem_1b_ecc_merr : 1; /* [11] */ + u32 be_iss2_imem_2b_ecc_err : 1; /* [12] */ + u32 be_iss2_imem_2b_ecc_merr : 1; /* [13] */ + u32 be_iss2_imem_1b_ecc_err : 1; /* [14] */ + u32 be_iss2_imem_1b_ecc_merr : 1; /* [15] */ + u32 be_iss3_imem_2b_ecc_err : 1; /* [16] */ + u32 be_iss3_imem_2b_ecc_merr : 1; /* [17] */ + u32 be_iss3_imem_1b_ecc_err : 1; /* [18] */ + u32 be_iss3_imem_1b_ecc_merr : 1; /* [19] */ + u32 ee_imem_2b_ecc_err : 1; /* [20] */ + u32 ee_imem_2b_ecc_merr : 1; /* [21] */ + u32 ee_imem_1b_ecc_err : 1; /* [22] */ + u32 ee_imem_1b_ecc_merr : 1; /* [23] */ + u32 be_rtn_invld_jmp_err : 1; /* [24] */ + u32 be_rtn_invld_jmp_merr : 1; /* [25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_mem_err_u; + +/* Define the union csr_ppe_mem_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 se_imem_2b_ecc_mask : 1; /* [0] */ + u32 se_imem_1b_ecc_mask : 1; /* [1] */ + u32 be_iss0_imem_2b_ecc_mask : 1; /* [2] */ + u32 be_iss0_imem_1b_ecc_mask : 1; /* [3] */ + u32 be_iss1_imem_2b_ecc_mask : 1; /* [4] */ + u32 be_iss1_imem_1b_ecc_mask : 1; /* [5] */ + u32 be_iss2_imem_2b_ecc_mask : 1; /* [6] */ + u32 be_iss2_imem_1b_ecc_mask : 1; /* [7] */ + u32 be_iss3_imem_2b_ecc_mask : 1; /* [8] */ + u32 be_iss3_imem_1b_ecc_mask : 1; /* [9] */ + u32 ee_imem_2b_ecc_mask : 1; /* [10] */ + u32 ee_imem_1b_ecc_mask : 1; /* [11] */ + u32 be_rtn_invld_jmp_mask : 1; /* [12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_mem_err_mask_u; + +/* Define the union csr_ppe_mem_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_err_index : 8; /* [7:0] */ + u32 mem_err_info_type : 4; /* [11:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_mem_err_info_u; + +/* Define the union csr_ppe_timeout_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_timeout_err_u; + +/* Define the union csr_ppe_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_addr : 8; /* [7:0] */ + u32 ppe_indrect_tab : 3; /* [10:8] */ + u32 rsv_6 : 17; /* [27:11] */ + u32 ppe_indrect_stat : 2; /* [29:28] */ + u32 ppe_indrect_mode : 1; /* [30] */ + u32 ppe_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_ctrl_u; + +/* Define the union csr_ppe_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_timeout_u; + +/* Define the union csr_ppe_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_data_0_u; + +/* Define the union csr_ppe_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_data_1_u; + +/* Define the union csr_ppe_indrect_data_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_data_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_data_2_u; + +/* Define the union csr_ppe_indrect_data_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_data_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_data_3_u; + +/* Define the union csr_ppe_indrect_data_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_data_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_data_4_u; + +/* Define the union csr_ppe_indrect_data_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_indrect_data_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_indrect_data_5_u; + +/* Define the union csr_ppe_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_enable : 1; /* [0] */ + u32 cnt1_enable : 1; /* [1] */ + u32 cnt2_enable : 1; /* [2] */ + u32 cnt3_enable : 1; /* [3] */ + u32 cnt0_match_en : 2; /* [5:4] */ + u32 cnt1_match_en : 2; /* [7:6] */ + u32 cnt2_match_en : 2; /* [9:8] */ + u32 cnt3_match_en : 2; /* [11:10] */ + u32 cnt0_sel : 1; /* [12] */ + u32 cnt1_sel : 1; /* [13] */ + u32 cnt2_sel : 1; /* [14] */ + u32 cnt3_sel : 1; /* [15] */ + u32 cnt0_match_core : 2; /* [17:16] */ + u32 cnt1_match_core : 2; /* [19:18] */ + u32 cnt2_match_core : 2; /* [21:20] */ + u32 cnt3_match_core : 2; /* [23:22] */ + u32 cnt0_match_thread : 2; /* [25:24] */ + u32 cnt1_match_thread : 2; /* [27:26] */ + u32 cnt2_match_thread : 2; /* [29:28] */ + u32 cnt3_match_thread : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_cnt_cfg_u; + +/* Define the union csr_ppe_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_cnt0_u; + +/* Define the union csr_ppe_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_cnt1_u; + +/* Define the union csr_ppe_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_cnt2_u; + +/* Define the union csr_ppe_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_cnt3_u; + +/* Define the union csr_ppe_stat_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 be_running : 1; /* [0] */ + u32 ee_running : 1; /* [1] */ + u32 se_running : 1; /* [2] */ + u32 se_waiting : 1; /* [3] */ + u32 launch_wr_sp_pending : 1; /* [4] */ + u32 launch_iss_pending : 1; /* [5] */ + u32 wr_sp_ins_pending : 1; /* [6] */ + u32 obuf_depth : 5; /* [11:7] */ + u32 ibuf_credit : 2; /* [13:12] */ + u32 post_st_credit : 3; /* [16:14] */ + u32 req_fifo_depth : 5; /* [21:17] */ + u32 obuf_full : 1; /* [22] */ + u32 rspn_fifo_full : 1; /* [23] */ + u32 rspn_fifo_depth : 5; /* [28:24] */ + u32 upgrade_rdy : 1; /* [29] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_stat_ctp_u; + +/* Define the union csr_ppe_pc_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 se : 8; /* [7:0] */ + u32 be : 8; /* [15:8] */ + u32 ee : 8; /* [23:16] */ + u32 rsv_8 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_pc_ctp_u; + +/* Define the union csr_ppe_pw_mw_out_of_range_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_pw_mw_out_of_range_err_u; + +/* Define the union csr_ppe_se_ins_exe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_se_ins_exe_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_se_ins_exe_cnt_u; + +/* Define the union csr_ppe_be_ins_exe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_be_ins_exe_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_be_ins_exe_cnt_u; + +/* Define the union csr_ppe_ee_ins_exe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_ee_ins_exe_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_ee_ins_exe_cnt_u; + +/* Define the union csr_ppe_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_data : 8; /* [7:0] */ + u32 tx_api : 8; /* [15:8] */ + u32 rx_data : 8; /* [23:16] */ + u32 rx_api : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_err_num_u; + +/* Define the union csr_ppe_stat_ctp2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 obuf_credit : 9; /* [8:0] */ + u32 rsv_9 : 7; /* [15:9] */ + u32 prog_exe_long_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_stat_ctp2_u; + +/* Define the union csr_ppe_prog_ent_addr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog_ent_addr_0 : 8; /* [7:0] */ + u32 ppe_prog_ent_addr_1 : 8; /* [15:8] */ + u32 ppe_prog_ent_addr_2 : 8; /* [23:16] */ + u32 ppe_prog_ent_addr_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_ent_addr_0_u; + +/* Define the union csr_ppe_prog_ent_addr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog_ent_addr_4 : 8; /* [7:0] */ + u32 ppe_prog_ent_addr_5 : 8; /* [15:8] */ + u32 ppe_prog_ent_addr_6 : 8; /* [23:16] */ + u32 ppe_prog_ent_addr_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_ent_addr_1_u; + +/* Define the union csr_ppe_prog_exit_addr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog_exit_addr_0 : 8; /* [7:0] */ + u32 ppe_prog_exit_addr_1 : 8; /* [15:8] */ + u32 ppe_prog_exit_addr_2 : 8; /* [23:16] */ + u32 ppe_prog_exit_addr_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_exit_addr_0_u; + +/* Define the union csr_ppe_prog_exit_addr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog_exit_addr_4 : 8; /* [7:0] */ + u32 ppe_prog_exit_addr_5 : 8; /* [15:8] */ + u32 ppe_prog_exit_addr_6 : 8; /* [23:16] */ + u32 ppe_prog_exit_addr_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_exit_addr_1_u; + +/* Define the union csr_ent_num_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_0_u; + +/* Define the union csr_ent_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_1_u; + +/* Define the union csr_ent_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_2_u; + +/* Define the union csr_ent_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_3_u; + +/* Define the union csr_ent_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_4_u; + +/* Define the union csr_ent_num_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_5_u; + +/* Define the union csr_ent_num_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_6_u; + +/* Define the union csr_ent_num_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ent_num_7_u; + +/* Define the union csr_exit_num_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_0_u; + +/* Define the union csr_exit_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_1_u; + +/* Define the union csr_exit_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_2_u; + +/* Define the union csr_exit_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_3_u; + +/* Define the union csr_exit_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_4_u; + +/* Define the union csr_exit_num_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_5_u; + +/* Define the union csr_exit_num_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_6_u; + +/* Define the union csr_exit_num_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exit_num_7_u; + +/* Define the union csr_ppe_prog_exe_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog_exe_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_exe_time_u; + +/* Define the union csr_ppe_prog_exe_long_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 se_pc : 8; /* [7:0] */ + u32 be_pc : 8; /* [15:8] */ + u32 ee_pc : 8; /* [23:16] */ + u32 se_runing : 1; /* [24] */ + u32 be_runing : 1; /* [25] */ + u32 ee_runing : 1; /* [26] */ + u32 rsv_10 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_exe_long_u; + +/* Define the union csr_ppe_prog_exe_long_pw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptr_0 : 8; /* [7:0] */ + u32 ptr_1 : 8; /* [15:8] */ + u32 ptr_2 : 8; /* [23:16] */ + u32 ptr_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_exe_long_pw_u; + +/* Define the union csr_ppe_prog_exe_long_mw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptr_0 : 8; /* [7:0] */ + u32 ptr_1 : 8; /* [15:8] */ + u32 ptr_2 : 8; /* [23:16] */ + u32 ptr_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppe_prog_exe_long_mw_u; + +/* Define the union csr_exe_long_pw_reg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_pw_reg_0_u; + +/* Define the union csr_exe_long_pw_reg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_pw_reg_1_u; + +/* Define the union csr_exe_long_pw_reg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_pw_reg_2_u; + +/* Define the union csr_exe_long_pw_reg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_pw_reg_3_u; + +/* Define the union csr_exe_long_mw_reg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_mw_reg_0_u; + +/* Define the union csr_exe_long_mw_reg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_mw_reg_1_u; + +/* Define the union csr_exe_long_mw_reg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_mw_reg_2_u; + +/* Define the union csr_exe_long_mw_reg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ppe_prog : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_exe_long_mw_reg_3_u; + + +/* Define the union csr_tile_qcm_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_version_u; + +/* Define the union csr_tile_qcm_perf_cntl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_perf_cnt0_event : 4; /* [3:0] */ + u32 tile_qcm_perf_cnt1_event : 2; /* [5:4] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 tile_qcm_perf_cnt2_event : 4; /* [11:8] */ + u32 tile_qcm_perf_cnt0_en : 1; /* [12] */ + u32 tile_qcm_perf_cnt1_en : 1; /* [13] */ + u32 tile_qcm_perf_cnt2_en : 1; /* [14] */ + u32 rsv_1 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_perf_cntl_u; + +/* Define the union csr_tile_qcm_common_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_timer_int_tc : 2; /* [1:0] */ + u32 csr_timer_int_c : 1; /* [2] */ + u32 ocp_rsp_err_int_c : 1; /* [3] */ + u32 csr_c_thread_mode : 1; /* [4] */ + u32 rp_spram_err_inject_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 rp_cpb_hw_push_base_f : 1; /* [15] */ + u32 mem_power_ret1n : 1; /* [16] */ + u32 rp_ecc_err_gen_dis : 1; /* [17] */ + u32 kisdon_timer_en : 1; /* [18] */ + u32 lsul2_cache_err_check_dis : 1; /* [19] */ + u32 rsv_3 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_common_cfg_u; + +/* Define the union csr_tile_qcm_reset_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_core0_reset : 1; /* [0] */ + u32 rp_core1_reset : 1; /* [1] */ + u32 rp_core2_reset : 1; /* [2] */ + u32 rp_core3_reset : 1; /* [3] */ + u32 rp_core0_clk_en : 1; /* [4] */ + u32 rp_core1_clk_en : 1; /* [5] */ + u32 rp_core2_clk_en : 1; /* [6] */ + u32 rp_core3_clk_en : 1; /* [7] */ + u32 rp_ppe_clk_en : 1; /* [8] */ + u32 rsv_4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_reset_cfg_u; + +/* Define the union csr_tile_qcm_c0_csr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intr_valid : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 tc_id : 2; /* [5:4] */ + u32 rsv_1 : 8; /* [13:6] */ + u32 intr_ctl : 1; /* [14] */ + u32 intr_infor : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c0_csr_int_u; + +/* Define the union csr_tile_qcm_c1_csr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intr_valid : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 tc_id : 2; /* [5:4] */ + u32 rsv_1 : 8; /* [13:6] */ + u32 intr_ctl : 1; /* [14] */ + u32 intr_infor : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c1_csr_int_u; + +/* Define the union csr_tile_qcm_c2_csr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intr_valid : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 tc_id : 2; /* [5:4] */ + u32 rsv_1 : 8; /* [13:6] */ + u32 intr_ctl : 1; /* [14] */ + u32 intr_infor : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c2_csr_int_u; + +/* Define the union csr_tile_qcm_c3_csr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intr_valid : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 tc_id : 2; /* [5:4] */ + u32 rsv_1 : 8; /* [13:6] */ + u32 intr_ctl : 1; /* [14] */ + u32 intr_infor : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c3_csr_int_u; + +/* Define the union csr_tile_qcm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_5 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_6 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_int_vector_u; + +/* Define the union csr_tile_qcm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 10; /* [9:0] */ + u32 rsv_7 : 6; /* [15:10] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_int_u; + +/* Define the union csr_tile_qcm_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 10; /* [9:0] */ + u32 rsv_8 : 6; /* [15:10] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_int_mask_u; + +/* Define the union csr_tile_qcm_c0_spram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c0_spram_err_u; + +/* Define the union csr_tile_qcm_c1_spram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c1_spram_err_u; + +/* Define the union csr_tile_qcm_c2_spram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c2_spram_err_u; + +/* Define the union csr_tile_qcm_c3_spram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_c3_spram_err_u; + +/* Define the union csr_c0_lsul2_csr_cache_addr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c0_lsul2_csr_cache_addr_err_u; + +/* Define the union csr_c1_lsul2_csr_cache_addr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c1_lsul2_csr_cache_addr_err_u; + +/* Define the union csr_c2_lsul2_csr_cache_addr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2_lsul2_csr_cache_addr_err_u; + +/* Define the union csr_c3_lsul2_csr_cache_addr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c3_lsul2_csr_cache_addr_err_u; + +/* Define the union csr_tile_qcm_lsu_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c0_lsu_csr_dsb_err : 1; /* [0] */ + u32 c0_lsu_csr_dsb_merr : 1; /* [1] */ + u32 c1_lsu_csr_dsb_err : 1; /* [2] */ + u32 c1_lsu_csr_dsb_merr : 1; /* [3] */ + u32 c2_lsu_csr_dsb_err : 1; /* [4] */ + u32 c2_lsu_csr_dsb_merr : 1; /* [5] */ + u32 c3_lsu_csr_dsb_err : 1; /* [6] */ + u32 c3_lsu_csr_dsb_merr : 1; /* [7] */ + u32 c0_lsu_csr_uncache_addr_err : 1; /* [8] */ + u32 c0_lsu_csr_uncache_addr_merr : 1; /* [9] */ + u32 c1_lsu_csr_uncache_addr_err : 1; /* [10] */ + u32 c1_lsu_csr_uncache_addr_merr : 1; /* [11] */ + u32 c2_lsu_csr_uncache_addr_err : 1; /* [12] */ + u32 c2_lsu_csr_uncache_addr_merr : 1; /* [13] */ + u32 c3_lsu_csr_uncache_addr_err : 1; /* [14] */ + u32 c3_lsu_csr_uncache_addr_merr : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_lsu_err_u; + +/* Define the union csr_tile_qcm_lsu_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c0_lsu_csr_dsb_err_mask : 1; /* [0] */ + u32 c1_lsu_csr_dsb_err_mask : 1; /* [1] */ + u32 c2_lsu_csr_dsb_err_mask : 1; /* [2] */ + u32 c3_lsu_csr_dsb_err_mask : 1; /* [3] */ + u32 c0_lsu_csr_uncache_addr_err_mask : 1; /* [4] */ + u32 c1_lsu_csr_uncache_addr_err_mask : 1; /* [5] */ + u32 c2_lsu_csr_uncache_addr_err_mask : 1; /* [6] */ + u32 c3_lsu_csr_uncache_addr_err_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_lsu_err_mask_u; + +/* Define the union csr_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_reservd_u; + +/* Define the union csr_tile_qcm_perf_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 tile_qcm_perf_cnt0 : 48; /* [47:0] */ + u64 rsvd : 16; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_tile_qcm_perf_cnt0_u; + +/* Define the union csr_tile_qcm_perf_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 tile_qcm_perf_cnt1 : 48; /* [47:0] */ + u64 rsvd : 16; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_tile_qcm_perf_cnt1_u; + +/* Define the union csr_tile_qcm_perf_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 tile_qcm_perf_cnt2 : 48; /* [47:0] */ + u64 rsvd : 16; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_tile_qcm_perf_cnt2_u; + +/* Define the union csr_tile_qcm_clr_g_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_clr_g_flag : 1; /* [0] */ + u32 rsv_10 : 3; /* [3:1] */ + u32 tile_qcm_clr_g_flag_id : 3; /* [6:4] */ + u32 rsv_11 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_clr_g_flag_u; + +/* Define the union csr_tile_qcm_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_mon_addr : 8; /* [7:0] */ + u32 tile_qcm_mon_type : 3; /* [10:8] */ + u32 rsv_12 : 1; /* [11] */ + u32 rp_src_tag_oeid_sel : 4; /* [15:12] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_mon_cfg_u; + +/* Define the union csr_tile_qcm_mon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 40; /* [39:0] */ + u64 rsvd : 24; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_tile_qcm_mon_sta_u; + +/* Define the union csr_tile_qcm_osd_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chaw : 16; /* [15:0] */ + u32 inst_g : 8; /* [23:16] */ + u32 inst_c : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_osd_sta_u; + +/* Define the union csr_tile_qcm_src_oeid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 22; /* [21:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_src_oeid_u; + +/* Define the union csr_tile_qcm_mmu_addr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_mmu_addr0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_mmu_addr0_u; + +/* Define the union csr_tile_qcm_mmu_addr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_mmu_addr1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_mmu_addr1_u; + +/* Define the union csr_tile_qcm_mmu_addr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_qcm_mmu_addr2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_mmu_addr2_u; + +/* Define the union csr_tile_qcm_spram_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c0_spram_ecc1_err : 1; /* [0] */ + u32 c0_spram_ecc1_merr : 1; /* [1] */ + u32 c0_spram_eccm_err : 1; /* [2] */ + u32 c0_spram_eccm_merr : 1; /* [3] */ + u32 c1_spram_ecc1_err : 1; /* [4] */ + u32 c1_spram_ecc1_merr : 1; /* [5] */ + u32 c1_spram_eccm_err : 1; /* [6] */ + u32 c1_spram_eccm_merr : 1; /* [7] */ + u32 c2_spram_ecc1_err : 1; /* [8] */ + u32 c2_spram_ecc1_merr : 1; /* [9] */ + u32 c2_spram_eccm_err : 1; /* [10] */ + u32 c2_spram_eccm_merr : 1; /* [11] */ + u32 c3_spram_ecc1_err : 1; /* [12] */ + u32 c3_spram_ecc1_merr : 1; /* [13] */ + u32 c3_spram_eccm_err : 1; /* [14] */ + u32 c3_spram_eccm_merr : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_spram_ecc_err_u; + +/* Define the union csr_tile_qcm_spram_ecc_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c0_spram_ecc1_err_mask : 1; /* [0] */ + u32 c0_spram_eccm_err_mask : 1; /* [1] */ + u32 c1_spram_ecc1_err_mask : 1; /* [2] */ + u32 c1_spram_eccm_err_mask : 1; /* [3] */ + u32 c2_spram_ecc1_err_mask : 1; /* [4] */ + u32 c2_spram_eccm_err_mask : 1; /* [5] */ + u32 c3_spram_ecc1_err_mask : 1; /* [6] */ + u32 c3_spram_eccm_err_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qcm_spram_ecc_err_mask_u; + + +/* Define the union csr_tile_tiu_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tiu_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_version_u; + +/* Define the union csr_tile_tiu_common_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tile_tiu_ring_req_thrd : 3; /* [2:0] */ + u32 rsv_0 : 1; /* [3] */ + u32 rp_tile_tiu_wakeup_gen : 1; /* [4] */ + u32 rp_tile_tiu_qpc_req_thrd : 3; /* [7:5] */ + u32 rp_tile_tiu_l2i_src : 1; /* [8] */ + u32 rsv_1 : 3; /* [11:9] */ + u32 rp_tile_tiu_cnt_sel : 1; /* [12] */ + u32 rsv_2 : 3; /* [15:13] */ + u32 rp_tile_tiu_cnt_en : 1; /* [16] */ + u32 rp_tile_check_en : 1; /* [17] */ + u32 rp_tile_one_bit_err_inj_req : 1; /* [18] */ + u32 rp_tile_two_bit_err_inj_req : 1; /* [19] */ + u32 rp_tiu_scatter_en : 1; /* [20] */ + u32 rp_tiu_stf_col_del_md_hdr_en : 1; /* [21] */ + u32 rp_tile_q2r_one_bit_err_inj_req : 1; /* [22] */ + u32 rp_tile_q2r_two_bit_err_inj_req : 1; /* [23] */ + u32 rp_tile_c2r_one_bit_err_inj_req : 1; /* [24] */ + u32 rp_tile_c2r_two_bit_err_inj_req : 1; /* [25] */ + u32 rsv_3 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_common_cfg_u; + +/* Define the union csr_ring_rx_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_rx_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_rx_correct_api_cnt_u; + +/* Define the union csr_ring_rx_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_rx_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_rx_err_api_cnt_u; + +/* Define the union csr_ring_rx_drop_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_rx_drop_flit_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_rx_drop_flit_cnt_u; + +/* Define the union csr_smf_rx_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rx_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_rx_correct_api_cnt_u; + +/* Define the union csr_smf_rx_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rx_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_rx_err_api_cnt_u; + +/* Define the union csr_smf_rx_drop_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_rx_drop_flit_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_rx_drop_flit_cnt_u; + +/* Define the union csr_cal_rx_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cal_rx_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cal_rx_correct_api_cnt_u; + +/* Define the union csr_cal_rx_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cal_rx_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cal_rx_err_api_cnt_u; + +/* Define the union csr_cal_rx_drop_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cal_rx_drop_flit_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cal_rx_drop_flit_cnt_u; + +/* Define the union csr_qu_rx_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_rx_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_rx_correct_api_cnt_u; + +/* Define the union csr_qu_rx_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_rx_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_rx_err_api_cnt_u; + +/* Define the union csr_qu_rx_drop_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_rx_drop_flit_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_rx_drop_flit_cnt_u; + +/* Define the union csr_cpb_rx_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_correct_api_cnt_u; + +/* Define the union csr_cpb_rx_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_api_cnt_u; + +/* Define the union csr_cpb_rx_drop_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_drop_flit_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_drop_flit_cnt_u; + +/* Define the union csr_tiu_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_int_vector_u; + +/* Define the union csr_tiu_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 15; /* [14:0] */ + u32 rsv_6 : 1; /* [15] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_int_u; + +/* Define the union csr_tiu_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 15; /* [14:0] */ + u32 rsv_7 : 1; /* [15] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_int_mask_u; + +/* Define the union csr_ring_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_api_drop_err : 1; /* [0] */ + u32 ring_api_drop_merr : 1; /* [1] */ + u32 ring_miss_sop_err : 1; /* [2] */ + u32 ring_miss_sop_merr : 1; /* [3] */ + u32 ring_miss_eop_err : 1; /* [4] */ + u32 ring_miss_eop_merr : 1; /* [5] */ + u32 ring_l2i_over_long_err : 1; /* [6] */ + u32 ring_l2i_over_long_merr : 1; /* [7] */ + u32 ring_l2i_too_short_err : 1; /* [8] */ + u32 ring_l2i_too_short_merr : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_itf_err_u; + +/* Define the union csr_ring_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_api_drop_err_mask : 1; /* [0] */ + u32 ring_miss_sop_err_mask : 1; /* [1] */ + u32 ring_miss_eop_err_mask : 1; /* [2] */ + u32 ring_l2i_over_long_err_mask : 1; /* [3] */ + u32 ring_l2i_too_short_err_mask : 1; /* [4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_itf_err_mask_u; + +/* Define the union csr_smf_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_api_drop_err : 1; /* [0] */ + u32 smf_api_drop_merr : 1; /* [1] */ + u32 smf_miss_sop_err : 1; /* [2] */ + u32 smf_miss_sop_merr : 1; /* [3] */ + u32 smf_miss_eop_err : 1; /* [4] */ + u32 smf_miss_eop_merr : 1; /* [5] */ + u32 smf_l2i_over_long_err : 1; /* [6] */ + u32 smf_l2i_over_long_merr : 1; /* [7] */ + u32 smf_l2i_too_short_err : 1; /* [8] */ + u32 smf_l2i_too_short_merr : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_itf_err_u; + +/* Define the union csr_smf_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_api_drop_err_mask : 1; /* [0] */ + u32 smf_miss_sop_err_mask : 1; /* [1] */ + u32 smf_miss_eop_err_mask : 1; /* [2] */ + u32 smf_l2i_over_long_err_mask : 1; /* [3] */ + u32 smf_l2i_too_short_err_mask : 1; /* [4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_itf_err_mask_u; + +/* Define the union csr_cal_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cal_api_drop_err : 1; /* [0] */ + u32 cal_api_drop_merr : 1; /* [1] */ + u32 cal_miss_sop_err : 1; /* [2] */ + u32 cal_miss_sop_merr : 1; /* [3] */ + u32 cal_miss_eop_err : 1; /* [4] */ + u32 cal_miss_eop_merr : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cal_itf_err_u; + +/* Define the union csr_cal_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cal_api_drop_err_mask : 1; /* [0] */ + u32 cal_miss_sop_err_mask : 1; /* [1] */ + u32 cal_miss_eop_err_mask : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cal_itf_err_mask_u; + +/* Define the union csr_qu_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_api_drop_err : 1; /* [0] */ + u32 qu_api_drop_merr : 1; /* [1] */ + u32 qu_miss_sop_err : 1; /* [2] */ + u32 qu_miss_sop_merr : 1; /* [3] */ + u32 qu_miss_eop_err : 1; /* [4] */ + u32 qu_miss_eop_merr : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_itf_err_u; + +/* Define the union csr_qu_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_api_drop_err_mask : 1; /* [0] */ + u32 qu_miss_sop_err_mask : 1; /* [1] */ + u32 qu_miss_eop_err_mask : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_itf_err_mask_u; + +/* Define the union csr_cpb_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_api_drop_err : 1; /* [0] */ + u32 cpb_api_drop_merr : 1; /* [1] */ + u32 cpb_miss_sop_err : 1; /* [2] */ + u32 cpb_miss_sop_merr : 1; /* [3] */ + u32 cpb_miss_eop_err : 1; /* [4] */ + u32 cpb_miss_eop_merr : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_itf_err_u; + +/* Define the union csr_cpb_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_api_drop_err_mask : 1; /* [0] */ + u32 cpb_miss_sop_err_mask : 1; /* [1] */ + u32 cpb_miss_eop_err_mask : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_itf_err_mask_u; + +/* Define the union csr_ring_rqst_chnl_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_rqst_chnl_err : 1; /* [0] */ + u32 ring_rqst_chnl_merr : 1; /* [1] */ + u32 rsv_8 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_rqst_chnl_err_u; + +/* Define the union csr_tiu_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tiu_indir_addr : 24; /* [23:0] */ + u32 tiu_indir_tab : 4; /* [27:24] */ + u32 tiu_indir_stat : 2; /* [29:28] */ + u32 tiu_indir_mode : 1; /* [30] */ + u32 tiu_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_indrect_ctrl_u; + +/* Define the union csr_tiu_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tiu_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_indrect_timeout_u; + +/* Define the union csr_tiu_indrect_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tiu_indir_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_indrect_data0_u; + +/* Define the union csr_tiu_indrect_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tiu_indir_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_indrect_data1_u; + +/* Define the union csr_tiu_indrect_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tiu_indir_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_indrect_data2_u; + +/* Define the union csr_cpb_scat_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_scat_ecc_1b_err : 1; /* [0] */ + u32 cpb_scat_ecc_1b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_scat_ecc_1bit_err_u; + +/* Define the union csr_cpb_scat_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_scat_ecc_2b_err : 1; /* [0] */ + u32 cpb_scat_ecc_2b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_scat_ecc_2bit_err_u; + +/* Define the union csr_tile_tiu_common_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_hw_query_eop_en : 1; /* [0] */ + u32 rsv_9 : 3; /* [3:1] */ + u32 rp_tiu_hw_lt_ld_en : 1; /* [4] */ + u32 rsv_10 : 3; /* [7:5] */ + u32 rp_tiu_hw_ecml_en : 1; /* [8] */ + u32 rsv_11 : 3; /* [11:9] */ + u32 rp_tiu_ecml_lb_en : 1; /* [12] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 rp_tiu_rocpkt_sgid_idx : 12; /* [27:16] */ + u32 rsv_13 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_common_cfg1_u; + +/* Define the union csr_tile_tiu_common_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_ecml_off1 : 4; /* [3:0] */ + u32 rp_tiu_ecml_off2 : 4; /* [7:4] */ + u32 rp_tiu_ecml_off3 : 4; /* [11:8] */ + u32 rp_tiu_ecml_osdid : 4; /* [15:12] */ + u32 rp_tiu_lt_ld_osdid : 4; /* [19:16] */ + u32 rsv_14 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_common_cfg2_u; + +/* Define the union csr_tile_tiu_common_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_lt_ld_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_common_cfg3_u; + +/* Define the union csr_tile_tiu_common_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_ecml_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_common_cfg4_u; + +/* Define the union csr_tile_tiu_common_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_ecml_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_common_cfg5_u; + +/* Define the union csr_tile_tiu_scat_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_scat_ofst0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_scat_cfg0_u; + +/* Define the union csr_tile_tiu_scat_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tiu_scat_ofst1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tiu_scat_cfg1_u; + +/* Define the union csr_qcm10_th_hq_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req : 16; /* [15:0] */ + u32 exist : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qcm10_th_hq_eop_st_u; + +/* Define the union csr_qcm32_th_hq_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req : 16; /* [15:0] */ + u32 exist : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qcm32_th_hq_eop_st_u; + +/* Define the union csr_qcm54_th_hq_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req : 16; /* [15:0] */ + u32 exist : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qcm54_th_hq_eop_st_u; + +/* Define the union csr_tiu_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 q2r_cnt : 8; /* [7:0] */ + u32 rsv_15 : 8; /* [15:8] */ + u32 c2r_cnt : 8; /* [23:16] */ + u32 rsv_16 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_fifo_st_u; + +/* Define the union csr_tiu_hia_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tiu_iofsm_ack_err : 1; /* [0] */ + u32 tiu_iofsm_ack_merr : 1; /* [1] */ + u32 rsv_17 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tiu_hia_err_u; + +/* Define the union csr_c2r_fifo_ov_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ov_err : 1; /* [0] */ + u32 ov_merr : 1; /* [1] */ + u32 rsv_18 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2r_fifo_ov_u; + +/* Define the union csr_q2r_fifo_ov_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ov_err : 1; /* [0] */ + u32 ov_merr : 1; /* [1] */ + u32 rsv_19 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_q2r_fifo_ov_u; + +/* Define the union csr_c2r_fifo_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c2r_fifo_1b_err : 1; /* [0] */ + u32 c2r_fifo_1b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2r_fifo_1bit_err_u; + +/* Define the union csr_c2r_fifo_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c2r_fifo_2b_err : 1; /* [0] */ + u32 c2r_fifo_2b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2r_fifo_2bit_err_u; + +/* Define the union csr_q2r_fifo_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 q2r_fifo_1b_err : 1; /* [0] */ + u32 q2r_fifo_1b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_q2r_fifo_1bit_err_u; + +/* Define the union csr_q2r_fifo_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 q2r_fifo_2b_err : 1; /* [0] */ + u32 q2r_fifo_2b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_q2r_fifo_2bit_err_u; + + +/* Define the union csr_tile_tou_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_version_u; + +/* Define the union csr_tile_exception_base_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 12; /* [11:0] */ + u32 tile_exception_base : 18; /* [29:12] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_exception_base_u; + +/* Define the union csr_tile_tou_common_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tile_check_en : 1; /* [0] */ + u32 rp_tile_tou_oeid_replace_en : 1; /* [1] */ + u32 rp_tile_tou_bubble_insert_en : 1; /* [2] */ + u32 rp_tile_ring_mem_one_bit_err_inj_req : 1; /* [3] */ + u32 rp_tile_tou_cnt_sel : 1; /* [4] */ + u32 rp_tile_ring_mem_two_bit_err_inj_req : 1; /* [5] */ + u32 rp_tile_cpb_mem_one_bit_err_inj_req : 1; /* [6] */ + u32 rp_tile_cpb_mem_two_bit_err_inj_req : 1; /* [7] */ + u32 rp_tile_tou_cnt_en : 1; /* [8] */ + u32 rp_tile_tou_ack_replace_en : 1; /* [9] */ + u32 tile_mem_ret1n : 1; /* [10] */ + u32 rp_oack_sop_en : 1; /* [11] */ + u32 tp_ram_tmod : 8; /* [19:12] */ + u32 rp_tile_prb_one_bit_err_inj_req : 1; /* [20] */ + u32 rp_tile_prb_two_bit_err_inj_req : 1; /* [21] */ + u32 rp_tile_prbn_one_bit_err_inj_req : 1; /* [22] */ + u32 rp_tile_prbn_two_bit_err_inj_req : 1; /* [23] */ + u32 rp_tile_uncrt_err_clr : 1; /* [24] */ + u32 rp_tile_uncrt_err_mask : 5; /* [29:25] */ + u32 rp_tile_qpc_mem_one_bit_err_inj_req : 1; /* [30] */ + u32 rp_tile_qpc_mem_two_bit_err_inj_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_common_cfg_u; + +/* Define the union csr_ring_req_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_req_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_req_correct_api_cnt_u; + +/* Define the union csr_ring_req_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_req_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_req_err_api_cnt_u; + +/* Define the union csr_ring_resp_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_resp_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_resp_correct_api_cnt_u; + +/* Define the union csr_ring_resp_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_resp_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_resp_err_api_cnt_u; + +/* Define the union csr_smf_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_correct_api_cnt_u; + +/* Define the union csr_smf_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_err_api_cnt_u; + +/* Define the union csr_qu_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_correct_api_cnt_u; + +/* Define the union csr_qu_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_err_api_cnt_u; + +/* Define the union csr_cpb_correct_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_correct_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_correct_api_cnt_u; + +/* Define the union csr_cpb_err_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_err_api_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_err_api_cnt_u; + +/* Define the union csr_tou_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_int_vector_u; + +/* Define the union csr_tou_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 12; /* [11:0] */ + u32 rsv_4 : 4; /* [15:12] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_int_u; + +/* Define the union csr_tou_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 12; /* [11:0] */ + u32 rsv_5 : 4; /* [15:12] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_int_mask_u; + +/* Define the union csr_prb_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prb_mem_ecc_1b_err : 1; /* [0] */ + u32 prb_mem_ecc_1b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prb_ecc_1bit_err_u; + +/* Define the union csr_prbn_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prbn_mem_ecc_1b_err : 1; /* [0] */ + u32 prbn_mem_ecc_1b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prbn_ecc_1bit_err_u; + +/* Define the union csr_prb_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prb_mem_ecc_2b_err : 1; /* [0] */ + u32 prb_mem_ecc_2b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prb_ecc_2bit_err_u; + +/* Define the union csr_prbn_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prbn_mem_ecc_2b_err : 1; /* [0] */ + u32 prbn_mem_ecc_2b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prbn_ecc_2bit_err_u; + +/* Define the union csr_tile_tou_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_prbn_weight_cfg : 9; /* [8:0] */ + u32 rsv_6 : 7; /* [15:9] */ + u32 rp_prb_weight_cfg : 12; /* [27:16] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_weight_cfg_u; + +/* Define the union csr_tile_tou_prb_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_mtc_ring_prb_credit : 7; /* [6:0] */ + u32 rsv_8 : 1; /* [7] */ + u32 tile_mtc_nring_prb_credit : 7; /* [14:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_prb_stat_u; + +/* Define the union csr_tile_tou_ring_arb_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_request : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_ring_arb_req_u; + +/* Define the union csr_tile_tou_nring_arb_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_request : 10; /* [9:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_nring_arb_req_u; + +/* Define the union csr_tile_tou_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tile_tou_ring_crdt_sel : 5; /* [4:0] */ + u32 rsv_9 : 3; /* [7:5] */ + u32 rp_tile_tou_nring_crdt_sel : 4; /* [11:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_crdt_cfg_u; + +/* Define the union csr_tile_tou_ring_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_status : 7; /* [6:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_ring_crdt_u; + +/* Define the union csr_tile_tou_nring_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_status : 7; /* [6:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_nring_crdt_u; + +/* Define the union csr_tile_tou_l2i_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_l2i_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_l2i_api_cnt_u; + +/* Define the union csr_tile_tou_thrsl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_thrsl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_thrsl_cnt_u; + +/* Define the union csr_tile_tou_qcm_rst_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_qcm_rst_req : 6; /* [5:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_qcm_rst_req_u; + +/* Define the union csr_tile_tou_vc_timeout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_vc_timeout_thrld : 20; /* [19:0] */ + u32 rp_vc_timeout_mode : 1; /* [20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_vc_timeout_cfg_u; + +/* Define the union csr_tile_tou_ring_req_vc_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_ring_req_vc_timeout_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_ring_req_vc_timeout_cnt_u; + +/* Define the union csr_tile_tou_qu_vc_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_qu_vc_timeout_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_qu_vc_timeout_cnt_u; + +/* Define the union csr_tile_tou_cpb_vc_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_tou_cpb_vc_timeout_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_cpb_vc_timeout_cnt_u; + +/* Define the union csr_tou_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_addr : 24; /* [23:0] */ + u32 tou_indir_tab : 4; /* [27:24] */ + u32 tou_indir_stat : 2; /* [29:28] */ + u32 tou_indir_mode : 1; /* [30] */ + u32 tou_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_ctrl_u; + +/* Define the union csr_tou_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_timeout_u; + +/* Define the union csr_tou_indrect_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_data0_u; + +/* Define the union csr_tou_indrect_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_data1_u; + +/* Define the union csr_tou_indrect_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_data2_u; + +/* Define the union csr_tou_indrect_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_data3_u; + +/* Define the union csr_tou_indrect_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_data4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_data4_u; + +/* Define the union csr_tou_indrect_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_indir_data5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_indrect_data5_u; + +/* Define the union csr_ring_mem_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_mem_ecc_1b_err : 1; /* [0] */ + u32 ring_mem_ecc_1b_merr : 1; /* [1] */ + u32 sticky : 8; /* [9:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_mem_ecc_1bit_err_u; + +/* Define the union csr_ring_mem_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_mem_ecc_2b_err : 1; /* [0] */ + u32 ring_mem_ecc_2b_merr : 1; /* [1] */ + u32 sticky : 8; /* [9:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_mem_ecc_2bit_err_u; + +/* Define the union csr_cpb_mem_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_mem_ecc_1b_err : 1; /* [0] */ + u32 cpb_mem_ecc_1b_merr : 1; /* [1] */ + u32 sticky : 8; /* [9:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_mem_ecc_1bit_err_u; + +/* Define the union csr_cpb_mem_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_mem_ecc_2b_err : 1; /* [0] */ + u32 cpb_mem_ecc_2b_merr : 1; /* [1] */ + u32 sticky : 8; /* [9:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_mem_ecc_2bit_err_u; + +/* Define the union csr_qpc_mem_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qpc_mem_ecc_1b_err : 1; /* [0] */ + u32 qpc_mem_ecc_1b_merr : 1; /* [1] */ + u32 sticky : 8; /* [9:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qpc_mem_ecc_1bit_err_u; + +/* Define the union csr_qpc_mem_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qpc_mem_ecc_2b_err : 1; /* [0] */ + u32 qpc_mem_ecc_2b_merr : 1; /* [1] */ + u32 sticky : 8; /* [9:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qpc_mem_ecc_2bit_err_u; + +/* Define the union csr_tile_tou_new_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tou_smf_pg : 4; /* [3:0] */ + u32 rp_smf_nd2rs_one_bit_err_inj_req : 1; /* [4] */ + u32 rp_smf_nd2rs_two_bit_err_inj_req : 1; /* [5] */ + u32 rp_quf_nd2rs_one_bit_err_inj_req : 1; /* [6] */ + u32 rp_quf_nd2rs_two_bit_err_inj_req : 1; /* [7] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_tou_new_cfg_u; + +/* Define the union csr_quf_nd2rs_fifo_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_1b_err : 1; /* [0] */ + u32 fifo_1b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_quf_nd2rs_fifo_1bit_err_u; + +/* Define the union csr_quf_nd2rs_fifo_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_2b_err : 1; /* [0] */ + u32 fifo_2b_merr : 1; /* [1] */ + u32 sticky : 7; /* [8:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_quf_nd2rs_fifo_2bit_err_u; + +/* Define the union csr_smf_nd2rs_fifo_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_1b_err : 1; /* [0] */ + u32 fifo_1b_merr : 1; /* [1] */ + u32 sticky : 5; /* [6:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_nd2rs_fifo_1bit_err_u; + +/* Define the union csr_smf_nd2rs_fifo_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_2b_err : 1; /* [0] */ + u32 fifo_2b_merr : 1; /* [1] */ + u32 sticky : 5; /* [6:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_nd2rs_fifo_2bit_err_u; + +/* Define the union csr_quf_nd2rs_fifo_ovf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ov_err : 1; /* [0] */ + u32 ov_merr : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_quf_nd2rs_fifo_ovf_u; + +/* Define the union csr_smf_nd2rs_fifo_ovf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ov_err : 1; /* [0] */ + u32 ov_merr : 1; /* [1] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_nd2rs_fifo_ovf_u; + +/* Define the union csr_qpci_nd2rs_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_fill : 7; /* [6:0] */ + u32 rsv_13 : 9; /* [15:7] */ + u32 quf_fill : 8; /* [23:16] */ + u32 rsv_14 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qpci_nd2rs_fifo_st_u; + +/* Define the union csr_tou_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tou_mon_cfg : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_mon_cfg_u; + +/* Define the union csr_tou_mon_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tou_mon_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tou_mon_cnt_u; + + +#endif // SD5860_SD5860_TYPEDEF_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/tile_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/tile_reg_offset.h new file mode 100644 index 000000000..53fcbe2fa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/tile_reg_offset.h @@ -0,0 +1,399 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : SD5860_sd5860_addr_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/09/18 10:05:20 Create file +// ****************************************************************************** +#ifndef HI1823_CSR_TILE_ADDR_DEFINE_H +#define HI1823_CSR_TILE_ADDR_DEFINE_H +#define SD5860_SD5860_ADDR_DEFINE_H + +/* tile_l2i_csr Base address of Module's Register */ +#define CSR_TILE_L2I_CSR_BASE (0x100) + +/* **************************************************************************** */ +/* tile_l2i_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TILE_L2I_CSR_TILE_L2I_VERSION_REG (CSR_TILE_L2I_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_TILE_L2I_CSR_TILE_L2I_PRELOAD_EN_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x4) /* l2i preload enable control.Wiret 1 to start preload */ +#define CSR_TILE_L2I_CSR_TILE_L2I_PRELOAD_START_ADDR_REG (CSR_TILE_L2I_CSR_BASE + 0x8) /* l2i preload start address */ +#define CSR_TILE_L2I_CSR_TILE_L2I_PRELOAD_CACHELINE_NUM_M1_REG \ + (CSR_TILE_L2I_CSR_BASE + 0xC) /* the cache line number minus 1 .The leagle configuration is 0x0~0x7ff */ +#define CSR_TILE_L2I_CSR_TILE_L2I_FETCH_API_CFG_REG (CSR_TILE_L2I_CSR_BASE + 0x10) /* L2I fetch API field. */ +#define CSR_TILE_L2I_CSR_TILE_L2I_IMR_CFG_REG (CSR_TILE_L2I_CSR_BASE + 0x14) /* IMR configuration */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_THD_REG (CSR_TILE_L2I_CSR_BASE + 0x18) /* timeout threshold configuration */ +#define CSR_TILE_L2I_CSR_TILE_L2I_INT_0_VECTOR_REG (CSR_TILE_L2I_CSR_BASE + 0x1C) +#define CSR_TILE_L2I_CSR_TILE_L2I_INT_0_REG (CSR_TILE_L2I_CSR_BASE + 0x20) +#define CSR_TILE_L2I_CSR_TILE_L2I_INT_0_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x24) +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM0_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x28) /* L2I fetch instruction timeout for QCM0 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM0_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x2C) +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM1_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x30) /* L2I fetch instruction timeout for QCM1 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM1_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x34) +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM2_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x38) /* L2I fetch instruction timeout for QCM2 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM2_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x3C) +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM3_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x40) /* L2I fetch instruction timeout for QCM3 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM3_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x44) +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM4_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x48) /* L2I fetch instruction timeout for QCM4 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM4_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x4C) +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM5_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x50) /* L2I fetch instruction timeout for QCM5 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_TIMEOUT_ERR_QCM5_MASK_REG (CSR_TILE_L2I_CSR_BASE + 0x54) +#define CSR_TILE_L2I_CSR_TILE_L2I_MEM_1BIT_ECC_ERR_REG (CSR_TILE_L2I_CSR_BASE + 0x58) /* L2I memory 1 bit ecc error */ +#define CSR_TILE_L2I_CSR_TILE_L2I_MEM_2BIT_ECC_ERR_REG (CSR_TILE_L2I_CSR_BASE + 0x5C) /* L2I memory 2 bit ecc error */ +#define CSR_TILE_L2I_CSR_TILE_L2I_PERF_CNT_REG (CSR_TILE_L2I_CSR_BASE + 0x60) /* counter for all L2I miss */ +#define CSR_TILE_L2I_CSR_TILE_L2I_INIT_EN_REG (CSR_TILE_L2I_CSR_BASE + 0x64) /* initialization the L2I memory bank. */ +#define CSR_TILE_L2I_CSR_TILE_L2I_DONE_HIST_REG (CSR_TILE_L2I_CSR_BASE + 0x68) +#define CSR_TILE_L2I_CSR_TILE_L2I_SP_RAM_TMOD_REG (CSR_TILE_L2I_CSR_BASE + 0x6C) /* ARM memory speed control */ +#define CSR_TILE_L2I_CSR_TILE_L2I_CLR_V_FLAG_REG \ + (CSR_TILE_L2I_CSR_BASE + 0x70) /* control register to clear the v flag in L2I, after l2i time out */ +#define CSR_TILE_L2I_CSR_TILE_L2I_MOD_REG (CSR_TILE_L2I_CSR_BASE + 0x74) /* mode configuration for L2I */ +#define CSR_TILE_L2I_CSR_L2I_INDRECT_CTRL_REG (CSR_TILE_L2I_CSR_BASE + 0x78) /* L2I间接寻址控制寄存器 */ +#define CSR_TILE_L2I_CSR_L2I_INDRECT_TIMEOUT_REG (CSR_TILE_L2I_CSR_BASE + 0x7C) /* L2I间接寻址TIMEOUT配置寄存器 */ +#define CSR_TILE_L2I_CSR_L2I_INDRECT_DATA_REG (CSR_TILE_L2I_CSR_BASE + 0x80) /* L2I间接寻址数据寄存器 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_ECC_ERR_INJ_0_REG (CSR_TILE_L2I_CSR_BASE + 0x84) /* L2I Bank0/1 ECC错误插入寄存器 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_ECC_ERR_INJ_1_REG (CSR_TILE_L2I_CSR_BASE + 0x88) /* L2I Bank2/3 ECC错误插入寄存器 */ +#define CSR_TILE_L2I_CSR_TILE_L2I_MISS_ADDR_REG (CSR_TILE_L2I_CSR_BASE + 0x8C) /* 抓取L2I miss的指令地址高27bit */ +#define CSR_TILE_L2I_CSR_TILE_L2I_IMR_EXT_REG (CSR_TILE_L2I_CSR_BASE + 0x90) /* IMR configuration 1 */ + +/* tile_ppe_csr Base address of Module's Register */ +#define CSR_TILE_PPE_CSR_BASE (0x300) + +/* **************************************************************************** */ +/* tile_ppe_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TILE_PPE_CSR_PPE_VERSION_REG (CSR_TILE_PPE_CSR_BASE + 0x0) /* Version Log register for PPE */ +#define CSR_TILE_PPE_CSR_PPE_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0x4) /* PPE configure register */ +#define CSR_TILE_PPE_CSR_PPE_TIMEOUT_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0x8) /* PPE configure register */ +#define CSR_TILE_PPE_CSR_PPE_MEM_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0xC) /* PPE Memory configure register */ +#define CSR_TILE_PPE_CSR_PPE_INT_VECTOR_REG (CSR_TILE_PPE_CSR_BASE + 0x10) /* PPE interrupt vector register */ +#define CSR_TILE_PPE_CSR_PPE_INT_REG (CSR_TILE_PPE_CSR_BASE + 0x14) /* PPE interrupt register */ +#define CSR_TILE_PPE_CSR_PPE_INT_MASK_REG (CSR_TILE_PPE_CSR_BASE + 0x18) /* PPE interrupt mask register */ +#define CSR_TILE_PPE_CSR_PPE_MEM_ERR_REG (CSR_TILE_PPE_CSR_BASE + 0x1C) /* PPE MEM error register */ +#define CSR_TILE_PPE_CSR_PPE_MEM_ERR_MASK_REG (CSR_TILE_PPE_CSR_BASE + 0x20) /* PPE MEM error mask register */ +#define CSR_TILE_PPE_CSR_PPE_MEM_ERR_INFO_REG (CSR_TILE_PPE_CSR_BASE + 0x24) /* PPE MEM error info register */ +#define CSR_TILE_PPE_CSR_PPE_TIMEOUT_ERR_REG (CSR_TILE_PPE_CSR_BASE + 0x28) /* PPE timeout error register */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_CTRL_REG (CSR_TILE_PPE_CSR_BASE + 0x2C) /* indirect access address registers */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_TIMEOUT_REG (CSR_TILE_PPE_CSR_BASE + 0x30) /* memory access timeout configure */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_0_REG (CSR_TILE_PPE_CSR_BASE + 0x34) /* indirect access data registers 0 */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_1_REG (CSR_TILE_PPE_CSR_BASE + 0x38) /* indirect access data registers 1 */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_2_REG (CSR_TILE_PPE_CSR_BASE + 0x3C) /* indirect access data registers 2 */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_3_REG (CSR_TILE_PPE_CSR_BASE + 0x40) /* indirect access data registers 3 */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_4_REG (CSR_TILE_PPE_CSR_BASE + 0x44) /* indirect access data registers 4 */ +#define CSR_TILE_PPE_CSR_PPE_INDRECT_DATA_5_REG (CSR_TILE_PPE_CSR_BASE + 0x48) /* indirect access data registers 5 */ +#define CSR_TILE_PPE_CSR_PPE_CNT_CFG_REG (CSR_TILE_PPE_CSR_BASE + 0x4C) /* PPE counter configure register */ +#define CSR_TILE_PPE_CSR_PPE_CNT0_REG (CSR_TILE_PPE_CSR_BASE + 0x50) /* PPE counter 0 register */ +#define CSR_TILE_PPE_CSR_PPE_CNT1_REG (CSR_TILE_PPE_CSR_BASE + 0x54) /* PPE counter 1 register */ +#define CSR_TILE_PPE_CSR_PPE_CNT2_REG (CSR_TILE_PPE_CSR_BASE + 0x58) /* PPE counter 2 register */ +#define CSR_TILE_PPE_CSR_PPE_CNT3_REG (CSR_TILE_PPE_CSR_BASE + 0x5C) /* PPE counter 3 register */ +#define CSR_TILE_PPE_CSR_PPE_STAT_CTP_REG (CSR_TILE_PPE_CSR_BASE + 0x60) /* PPE profiling register 0 */ +#define CSR_TILE_PPE_CSR_PPE_PC_CTP_REG (CSR_TILE_PPE_CSR_BASE + 0x64) /* PPE profiling register 1 */ +#define CSR_TILE_PPE_CSR_PPE_PW_MW_OUT_OF_RANGE_ERR_REG \ + (CSR_TILE_PPE_CSR_BASE + 0x68) /* PPE PW MW Out of range error register */ +#define CSR_TILE_PPE_CSR_PPE_SE_INS_EXE_CNT_REG (CSR_TILE_PPE_CSR_BASE + 0x6C) /* PPE counter register */ +#define CSR_TILE_PPE_CSR_PPE_BE_INS_EXE_CNT_REG (CSR_TILE_PPE_CSR_BASE + 0x70) /* PPE counter register */ +#define CSR_TILE_PPE_CSR_PPE_EE_INS_EXE_CNT_REG (CSR_TILE_PPE_CSR_BASE + 0x74) /* PPE counter register */ +#define CSR_TILE_PPE_CSR_PPE_ERR_NUM_REG \ + (CSR_TILE_PPE_CSR_BASE + 0x78) /* The number of error api received in SPC I/F */ +#define CSR_TILE_PPE_CSR_PPE_STAT_CTP2_REG (CSR_TILE_PPE_CSR_BASE + 0x7C) /* PPE profiling register 1 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_ENT_ADDR_0_REG (CSR_TILE_PPE_CSR_BASE + 0x80) /* PPE程序入口统计地址配置 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_ENT_ADDR_1_REG (CSR_TILE_PPE_CSR_BASE + 0x84) /* PPE程序入口统计地址配置 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_EXIT_ADDR_0_REG (CSR_TILE_PPE_CSR_BASE + 0x88) /* PPE程序出口统计地址配置 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_EXIT_ADDR_1_REG (CSR_TILE_PPE_CSR_BASE + 0x8C) /* PPE程序出口统计地址配置 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_0_REG (CSR_TILE_PPE_CSR_BASE + 0x90) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_1_REG (CSR_TILE_PPE_CSR_BASE + 0x94) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_2_REG (CSR_TILE_PPE_CSR_BASE + 0x98) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_3_REG (CSR_TILE_PPE_CSR_BASE + 0x9C) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_4_REG (CSR_TILE_PPE_CSR_BASE + 0xA0) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_5_REG (CSR_TILE_PPE_CSR_BASE + 0xA4) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_6_REG (CSR_TILE_PPE_CSR_BASE + 0xA8) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_ENT_NUM_7_REG (CSR_TILE_PPE_CSR_BASE + 0xAC) /* 匹配对应PPE程序入口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_0_REG (CSR_TILE_PPE_CSR_BASE + 0xB0) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_1_REG (CSR_TILE_PPE_CSR_BASE + 0xB4) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_2_REG (CSR_TILE_PPE_CSR_BASE + 0xB8) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_3_REG (CSR_TILE_PPE_CSR_BASE + 0xBC) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_4_REG (CSR_TILE_PPE_CSR_BASE + 0xC0) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_5_REG (CSR_TILE_PPE_CSR_BASE + 0xC4) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_6_REG (CSR_TILE_PPE_CSR_BASE + 0xC8) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_EXIT_NUM_7_REG (CSR_TILE_PPE_CSR_BASE + 0xCC) /* 匹配对应PPE程序出口地址的请求次数 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_TIME_REG (CSR_TILE_PPE_CSR_BASE + 0xD0) /* PPE程序执行时间 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_LONG_REG (CSR_TILE_PPE_CSR_BASE + 0xD4) /* PPE程序执行时间超长时的Engine状态 */ +#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_LONG_PW_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xD8) /* PPE程序执行时间超长时的4个BR issue的PW_PTR */ +#define CSR_TILE_PPE_CSR_PPE_PROG_EXE_LONG_MW_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xDC) /* PPE程序执行时间超长时的4个BR issue的MW_PTR */ +#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_0_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xE0) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_1_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xE4) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_2_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xE8) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_PW_REG_3_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xEC) /* PPE程序执行时间超长时的4个BR issue的PW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_0_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xF0) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_1_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xF4) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_2_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xF8) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */ +#define CSR_TILE_PPE_CSR_EXE_LONG_MW_REG_3_REG \ + (CSR_TILE_PPE_CSR_BASE + 0xFC) /* PPE程序执行时间超长时的4个BR issue的MW寄存器的值 */ + +/* tile_qcm_csr Base address of Module's Register */ +#define CSR_TILE_QCM_CSR_BASE (0x200) + +/* **************************************************************************** */ +/* tile_qcm_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TILE_QCM_CSR_TILE_QCM_VERSION_REG (CSR_TILE_QCM_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNTL_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x4) /* Quad core performance countrol register */ +#define CSR_TILE_QCM_CSR_TILE_QCM_COMMON_CFG_REG (CSR_TILE_QCM_CSR_BASE + 0x8) /* quad core global congfigure */ +#define CSR_TILE_QCM_CSR_TILE_QCM_RESET_CFG_REG (CSR_TILE_QCM_CSR_BASE + 0xC) /* quad core reset control */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C0_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x10) /* CSR interrupt to KISDON CORE */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C1_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x14) /* CSR interrupt to KISDON CORE */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C2_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x18) /* CSR interrupt to KISDON CORE */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C3_CSR_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x1C) /* CSR interrupt to KISDON CORE */ +#define CSR_TILE_QCM_CSR_TILE_QCM_INT_VECTOR_REG (CSR_TILE_QCM_CSR_BASE + 0x20) /* interrupt vector */ +#define CSR_TILE_QCM_CSR_TILE_QCM_INT_REG (CSR_TILE_QCM_CSR_BASE + 0x24) /* interrupt data */ +#define CSR_TILE_QCM_CSR_TILE_QCM_INT_MASK_REG (CSR_TILE_QCM_CSR_BASE + 0x28) /* interrupt mask */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C0_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x2C) /* KISDON core 0 spram error */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C1_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x30) /* KISDON core 1 spram error */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C2_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x34) /* KISDON core 2 spram error */ +#define CSR_TILE_QCM_CSR_TILE_QCM_C3_SPRAM_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x38) /* KISDON core 3 spram error */ +#define CSR_TILE_QCM_CSR_C0_LSUL2_CSR_CACHE_ADDR_ERR_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x3C) /* KISDON core 0 LSUL2 cache address error */ +#define CSR_TILE_QCM_CSR_C1_LSUL2_CSR_CACHE_ADDR_ERR_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x40) /* KISDON core 1 LSUL2 cache address error */ +#define CSR_TILE_QCM_CSR_C2_LSUL2_CSR_CACHE_ADDR_ERR_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x44) /* KISDON core 2 LSUL2 cache address error */ +#define CSR_TILE_QCM_CSR_C3_LSUL2_CSR_CACHE_ADDR_ERR_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x48) /* KISDON core 3 LSUL2 cache address error */ +#define CSR_TILE_QCM_CSR_TILE_QCM_LSU_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x4C) /* LSU Interface error register */ +#define CSR_TILE_QCM_CSR_TILE_QCM_LSU_ERR_MASK_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x50) /* LSU Interface error register mask */ +#define CSR_TILE_QCM_CSR_RESERVD_REG (CSR_TILE_QCM_CSR_BASE + 0x54) /* RESERVD */ +#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNT0_REG (CSR_TILE_QCM_CSR_BASE + 0x58) /* performance counter */ +#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNT1_REG (CSR_TILE_QCM_CSR_BASE + 0x60) /* performance counter */ +#define CSR_TILE_QCM_CSR_TILE_QCM_PERF_CNT2_REG (CSR_TILE_QCM_CSR_BASE + 0x68) /* performance counter */ +#define CSR_TILE_QCM_CSR_TILE_QCM_CLR_G_FLAG_REG \ + (CSR_TILE_QCM_CSR_BASE + 0x70) /* control register to clear the G flag in QMC/ICRC, after l2i time out */ +#define CSR_TILE_QCM_CSR_TILE_QCM_MON_CFG_REG (CSR_TILE_QCM_CSR_BASE + 0x74) /* monitor control */ +#define CSR_TILE_QCM_CSR_TILE_QCM_MON_STA_REG (CSR_TILE_QCM_CSR_BASE + 0x78) /* monitor status */ +#define CSR_TILE_QCM_CSR_TILE_QCM_OSD_STA_REG (CSR_TILE_QCM_CSR_BASE + 0x80) /* QCM CORE oustanding status */ +#define CSR_TILE_QCM_CSR_TILE_QCM_SRC_OEID_REG (CSR_TILE_QCM_CSR_BASE + 0x84) /* OEID and SRC_TAG_L */ +#define CSR_TILE_QCM_CSR_TILE_QCM_MMU_ADDR0_REG (CSR_TILE_QCM_CSR_BASE + 0x88) /* mmu address0 config */ +#define CSR_TILE_QCM_CSR_TILE_QCM_MMU_ADDR1_REG (CSR_TILE_QCM_CSR_BASE + 0x8C) /* mmu address1 config */ +#define CSR_TILE_QCM_CSR_TILE_QCM_MMU_ADDR2_REG (CSR_TILE_QCM_CSR_BASE + 0x90) /* mmu address2 config */ +#define CSR_TILE_QCM_CSR_TILE_QCM_SPRAM_ECC_ERR_REG (CSR_TILE_QCM_CSR_BASE + 0x94) /* SPRAM ECC ERROR */ +#define CSR_TILE_QCM_CSR_TILE_QCM_SPRAM_ECC_ERR_MASK_REG (CSR_TILE_QCM_CSR_BASE + 0x98) /* SPRAM ECC ERROR mask */ + +/* tile_tiu_csr Base address of Module's Register */ +#define CSR_TILE_TIU_CSR_BASE (0x0) + +/* **************************************************************************** */ +/* tile_tiu_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TILE_TIU_CSR_TILE_TIU_VERSION_REG (CSR_TILE_TIU_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x4) /* This config is used to set a the values that RING interfaces can make a request \ + to MTC when the fullness of RING interface buffer reach to this value. */ +#define CSR_TILE_TIU_CSR_RING_RX_CORRECT_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x8) /* The number of correct api received in RING interfaces */ +#define CSR_TILE_TIU_CSR_RING_RX_ERR_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xC) /* The number of error api received in RING interfaces */ +#define CSR_TILE_TIU_CSR_RING_RX_DROP_FLIT_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x10) /* The number of dropped flits received in RING interfaces */ +#define CSR_TILE_TIU_CSR_SMF_RX_CORRECT_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x14) /* The number of correct api received in SMF interfaces */ +#define CSR_TILE_TIU_CSR_SMF_RX_ERR_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x18) /* The number of error api received in SMF interfaces */ +#define CSR_TILE_TIU_CSR_SMF_RX_DROP_FLIT_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x1C) /* The number of dropped flits received in SMF interfaces */ +#define CSR_TILE_TIU_CSR_CAL_RX_CORRECT_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x20) /* The number of correct api received in CAL interfaces */ +#define CSR_TILE_TIU_CSR_CAL_RX_ERR_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x24) /* The number of error api received in CAL interfaces */ +#define CSR_TILE_TIU_CSR_CAL_RX_DROP_FLIT_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x28) /* The number of dropped flits received in CAL interfaces */ +#define CSR_TILE_TIU_CSR_QU_RX_CORRECT_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x2C) /* The number of correct api received in QU interfaces */ +#define CSR_TILE_TIU_CSR_QU_RX_ERR_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x30) /* The number of error api received in QU interfaces */ +#define CSR_TILE_TIU_CSR_QU_RX_DROP_FLIT_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x34) /* The number of dropped flits received in QU interfaces */ +#define CSR_TILE_TIU_CSR_CPB_RX_CORRECT_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x38) /* The number of correct api received in CPB interfaces */ +#define CSR_TILE_TIU_CSR_CPB_RX_ERR_API_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x3C) /* The number of error api received in CPB interfaces */ +#define CSR_TILE_TIU_CSR_CPB_RX_DROP_FLIT_CNT_REG \ + (CSR_TILE_TIU_CSR_BASE + 0x40) /* The number of dropped flits received in CPB interfaces */ +#define CSR_TILE_TIU_CSR_TIU_INT_VECTOR_REG (CSR_TILE_TIU_CSR_BASE + 0x44) +#define CSR_TILE_TIU_CSR_TIU_INT_REG (CSR_TILE_TIU_CSR_BASE + 0x48) /* SMIR interrupt data */ +#define CSR_TILE_TIU_CSR_TIU_INT_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x4C) /* SMIR interrupt mask configuration */ +#define CSR_TILE_TIU_CSR_RING_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x50) +#define CSR_TILE_TIU_CSR_RING_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x54) +#define CSR_TILE_TIU_CSR_SMF_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x58) +#define CSR_TILE_TIU_CSR_SMF_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x5C) +#define CSR_TILE_TIU_CSR_CAL_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x60) +#define CSR_TILE_TIU_CSR_CAL_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x64) +#define CSR_TILE_TIU_CSR_QU_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x68) +#define CSR_TILE_TIU_CSR_QU_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x6C) +#define CSR_TILE_TIU_CSR_CPB_ITF_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x70) +#define CSR_TILE_TIU_CSR_CPB_ITF_ERR_MASK_REG (CSR_TILE_TIU_CSR_BASE + 0x74) +#define CSR_TILE_TIU_CSR_RING_RQST_CHNL_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0x78) +#define CSR_TILE_TIU_CSR_TIU_INDRECT_CTRL_REG (CSR_TILE_TIU_CSR_BASE + 0x80) /* indirect access address registers */ +#define CSR_TILE_TIU_CSR_TIU_INDRECT_TIMEOUT_REG (CSR_TILE_TIU_CSR_BASE + 0x84) /* memory access timeout configure */ +#define CSR_TILE_TIU_CSR_TIU_INDRECT_DATA0_REG (CSR_TILE_TIU_CSR_BASE + 0x88) /* indirect access data registers */ +#define CSR_TILE_TIU_CSR_TIU_INDRECT_DATA1_REG (CSR_TILE_TIU_CSR_BASE + 0x8C) /* indirect access data registers */ +#define CSR_TILE_TIU_CSR_TIU_INDRECT_DATA2_REG (CSR_TILE_TIU_CSR_BASE + 0x90) /* indirect access data registers */ +#define CSR_TILE_TIU_CSR_CPB_SCAT_ECC_1BIT_ERR_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xA0) /* ECC 1 bit error occurs in cpb scatter table memory */ +#define CSR_TILE_TIU_CSR_CPB_SCAT_ECC_2BIT_ERR_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xA4) /* ECC 2 bit error occurs in cpb scatter table memory */ +#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG1_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xB0) /* This config is used to hardware issue some API */ +#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG2_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xB4) /* This config is used to hardware issue some API */ +#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG3_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xB8) /* This config is used to hardware issue some API */ +#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG4_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xBC) /* This config is used to hardware issue some API */ +#define CSR_TILE_TIU_CSR_TILE_TIU_COMMON_CFG5_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xC0) /* This config is used to hardware issue some API */ +#define CSR_TILE_TIU_CSR_TILE_TIU_SCAT_CFG0_REG (CSR_TILE_TIU_CSR_BASE + 0xC4) /* This config is used for scatter */ +#define CSR_TILE_TIU_CSR_TILE_TIU_SCAT_CFG1_REG (CSR_TILE_TIU_CSR_BASE + 0xC8) /* This config is used for scatter */ +#define CSR_TILE_TIU_CSR_QCM10_TH_HQ_EOP_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xD0) /* TIU HIA状态0 */ +#define CSR_TILE_TIU_CSR_QCM32_TH_HQ_EOP_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xD4) /* TIU HIA状态1 */ +#define CSR_TILE_TIU_CSR_QCM54_TH_HQ_EOP_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xD8) /* TIU HIA状态2 */ +#define CSR_TILE_TIU_CSR_TIU_FIFO_ST_REG (CSR_TILE_TIU_CSR_BASE + 0xDC) /* TIU HIA状态3 */ +#define CSR_TILE_TIU_CSR_TIU_HIA_ERR_REG (CSR_TILE_TIU_CSR_BASE + 0xE0) /* TIU HIA错误 */ +#define CSR_TILE_TIU_CSR_C2R_FIFO_OV_REG (CSR_TILE_TIU_CSR_BASE + 0xE4) /* C2R FIFO溢出 */ +#define CSR_TILE_TIU_CSR_Q2R_FIFO_OV_REG (CSR_TILE_TIU_CSR_BASE + 0xE8) /* Q2R FIFO溢出 */ +#define CSR_TILE_TIU_CSR_C2R_FIFO_1BIT_ERR_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xEC) /* ECC 1 bit error occurs in HIA C2R FIFO memory */ +#define CSR_TILE_TIU_CSR_C2R_FIFO_2BIT_ERR_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xF0) /* ECC 2 bit error occurs in HIA C2R FIFO memory */ +#define CSR_TILE_TIU_CSR_Q2R_FIFO_1BIT_ERR_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xF4) /* ECC 1 bit error occurs in HIA Q2R FIFO memory */ +#define CSR_TILE_TIU_CSR_Q2R_FIFO_2BIT_ERR_REG \ + (CSR_TILE_TIU_CSR_BASE + 0xF8) /* ECC 2 bit error occurs in HIA Q2R FIFO memory */ + +/* tile_tou_csr Base address of Module's Register */ +#define CSR_TILE_TOU_CSR_BASE (0xE00) + +/* **************************************************************************** */ +/* tile_tou_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TILE_TOU_CSR_TILE_TOU_VERSION_REG (CSR_TILE_TOU_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_TILE_TOU_CSR_TILE_EXCEPTION_BASE_REG (CSR_TILE_TOU_CSR_BASE + 0x4) /* Exception base address */ +#define CSR_TILE_TOU_CSR_TILE_TOU_COMMON_CFG_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x8) /* This config is used to set a the values that RING interfaces can make a request \ + to MTC when the fullness of RING interface buffer reach to this value. */ +#define CSR_TILE_TOU_CSR_RING_REQ_CORRECT_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xC) /* The number of correct api sent from RING interfaces */ +#define CSR_TILE_TOU_CSR_RING_REQ_ERR_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x10) /* The number of error api sent from RING interfaces */ +#define CSR_TILE_TOU_CSR_RING_RESP_CORRECT_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x14) /* The number of correct api sent from RING response interfaces */ +#define CSR_TILE_TOU_CSR_RING_RESP_ERR_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x18) /* The number of error api sent from RING response interfaces */ +#define CSR_TILE_TOU_CSR_SMF_CORRECT_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x1C) /* The number of correct api sent from SMF interfaces */ +#define CSR_TILE_TOU_CSR_SMF_ERR_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x20) /* The number of error api sent from SMF interfaces */ +#define CSR_TILE_TOU_CSR_QU_CORRECT_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x24) /* The number of correct api sent from QU interfaces */ +#define CSR_TILE_TOU_CSR_QU_ERR_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x28) /* The number of error api sent from QU interfaces */ +#define CSR_TILE_TOU_CSR_CPB_CORRECT_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x2C) /* The number of correct api sent from CPB interfaces */ +#define CSR_TILE_TOU_CSR_CPB_ERR_API_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x30) /* The number of error api sent from CPB interfaces */ +#define CSR_TILE_TOU_CSR_TOU_INT_VECTOR_REG (CSR_TILE_TOU_CSR_BASE + 0x34) +#define CSR_TILE_TOU_CSR_TOU_INT_REG (CSR_TILE_TOU_CSR_BASE + 0x38) /* TOU interrupt data */ +#define CSR_TILE_TOU_CSR_TOU_INT_MASK_REG (CSR_TILE_TOU_CSR_BASE + 0x3C) /* TOU interrupt mask configuration */ +#define CSR_TILE_TOU_CSR_PRB_ECC_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x40) /* ECC 1 bit error occurs in the PRB memory */ +#define CSR_TILE_TOU_CSR_PRBN_ECC_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x44) /* ECC 1 bit error occurs in the PRBN(non RING)memory */ +#define CSR_TILE_TOU_CSR_PRB_ECC_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x48) /* ECC 2 bit error occurs in the PRB memory */ +#define CSR_TILE_TOU_CSR_PRBN_ECC_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x4C) /* ECC 2 bit error occurs in the PRBN memory */ +#define CSR_TILE_TOU_CSR_TILE_TOU_WEIGHT_CFG_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x50) /* TOU prb/prbn stage 2 WRR weight configure */ +#define CSR_TILE_TOU_CSR_TILE_TOU_PRB_STAT_REG (CSR_TILE_TOU_CSR_BASE + 0x54) /* TOU PRB/PRBN 资源 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_RING_ARB_REQ_REG (CSR_TILE_TOU_CSR_BASE + 0x58) /* TOU RING pipeline 请求 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_NRING_ARB_REQ_REG (CSR_TILE_TOU_CSR_BASE + 0x5C) /* TOU non RING pipeline 请求 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_CRDT_CFG_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x60) /* 选择RING pipeline和non-RING pipeline各个VC的credit counter */ +#define CSR_TILE_TOU_CSR_TILE_TOU_RING_CRDT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x64) /* 当前选中的credit counter，配置来自TILE_TOU_CRDT_CFG的rp_tile_tou_ring_crdt_sel \ + */ +#define CSR_TILE_TOU_CSR_TILE_TOU_NRING_CRDT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x68) /* 当前选中的credit counter，配置来自TILE_TOU_CRDT_CFG的rp_tile_tou_nring_crdt_sel \ + */ +#define CSR_TILE_TOU_CSR_TILE_TOU_L2I_API_CNT_REG (CSR_TILE_TOU_CSR_BASE + 0x6C) /* L2I refill的指令数 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_THRSL_CNT_REG (CSR_TILE_TOU_CSR_BASE + 0x70) /* TILE release thread 个数 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_QCM_RST_REQ_REG (CSR_TILE_TOU_CSR_BASE + 0x74) /* 每个QCM的单独软复位请求 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_VC_TIMEOUT_CFG_REG (CSR_TILE_TOU_CSR_BASE + 0x78) /* VC等待仲裁超时设置 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_RING_REQ_VC_TIMEOUT_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x7C) /* RING通道进入VC超时仲裁模式的次数 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_QU_VC_TIMEOUT_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x80) /* QU通道进入VC超时仲裁模式的次数 */ +#define CSR_TILE_TOU_CSR_TILE_TOU_CPB_VC_TIMEOUT_CNT_REG \ + (CSR_TILE_TOU_CSR_BASE + 0x84) /* CPB通道进入VC超时仲裁模式的次数 */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_CTRL_REG (CSR_TILE_TOU_CSR_BASE + 0x90) /* indirect access address registers */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_TIMEOUT_REG (CSR_TILE_TOU_CSR_BASE + 0x94) /* memory access timeout configure */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA0_REG (CSR_TILE_TOU_CSR_BASE + 0x98) /* indirect access data registers */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA1_REG (CSR_TILE_TOU_CSR_BASE + 0x9C) /* indirect access data registers */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA2_REG (CSR_TILE_TOU_CSR_BASE + 0xA0) /* indirect access data registers */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA3_REG (CSR_TILE_TOU_CSR_BASE + 0xA4) /* indirect access data registers */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA4_REG (CSR_TILE_TOU_CSR_BASE + 0xA8) /* indirect access data registers */ +#define CSR_TILE_TOU_CSR_TOU_INDRECT_DATA5_REG (CSR_TILE_TOU_CSR_BASE + 0xAC) /* indirect access data registers */ +#define CSR_TILE_TOU_CSR_RING_MEM_ECC_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xB0) /* ECC 1 bit error occurs in ring merge table memory */ +#define CSR_TILE_TOU_CSR_RING_MEM_ECC_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xB4) /* ECC 2 bit error occurs in ring merge table memory */ +#define CSR_TILE_TOU_CSR_CPB_MEM_ECC_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xB8) /* ECC 1 bit error occurs in cpb merge table memory */ +#define CSR_TILE_TOU_CSR_CPB_MEM_ECC_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xBC) /* ECC 2 bit error occurs in cpb merge table memory */ +#define CSR_TILE_TOU_CSR_QPC_MEM_ECC_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xC0) /* ECC 1 bit error occurs in qpc merge table memory */ +#define CSR_TILE_TOU_CSR_QPC_MEM_ECC_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xC4) /* ECC 2 bit error occurs in qpc merge table memory */ +#define CSR_TILE_TOU_CSR_TILE_TOU_NEW_CFG_REG (CSR_TILE_TOU_CSR_BASE + 0xD0) /* TOU config */ +#define CSR_TILE_TOU_CSR_QUF_ND2RS_FIFO_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xD4) /* ECC 1 bit error occurs in QUF_ND2RS FIFO memory */ +#define CSR_TILE_TOU_CSR_QUF_ND2RS_FIFO_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xD8) /* ECC 2 bit error occurs in QUF_ND2RS FIFO memory */ +#define CSR_TILE_TOU_CSR_SMF_ND2RS_FIFO_1BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xDC) /* ECC 1 bit error occurs in SMF_ND2RS FIFO memory */ +#define CSR_TILE_TOU_CSR_SMF_ND2RS_FIFO_2BIT_ERR_REG \ + (CSR_TILE_TOU_CSR_BASE + 0xE0) /* ECC 2 bit error occurs in SMF_ND2RS FIFO memory */ +#define CSR_TILE_TOU_CSR_QUF_ND2RS_FIFO_OVF_REG (CSR_TILE_TOU_CSR_BASE + 0xE4) /* FIFO溢出 */ +#define CSR_TILE_TOU_CSR_SMF_ND2RS_FIFO_OVF_REG (CSR_TILE_TOU_CSR_BASE + 0xE8) /* FIFO溢出 */ +#define CSR_TILE_TOU_CSR_QPCI_ND2RS_FIFO_ST_REG (CSR_TILE_TOU_CSR_BASE + 0xEC) /* QPC接口FIFO状态 */ +#define CSR_TILE_TOU_CSR_TOU_MON_CFG_REG (CSR_TILE_TOU_CSR_BASE + 0xF0) /* Monitor相关配置 */ +#define CSR_TILE_TOU_CSR_TOU_MON_CNT_REG (CSR_TILE_TOU_CSR_BASE + 0xF4) /* Monitor统计计数器 */ +#define CSR_TILE_TOU_CSR_TOU_JTAG_EN_REG (CSR_TILE_TOU_CSR_BASE + 0xF8) /* JTAG 配置使能 */ + +#endif // SD5860_SD5860_ADDR_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/virtio_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/virtio_c_union_define.h new file mode 100644 index 000000000..81ad1bf5b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/virtio_c_union_define.h @@ -0,0 +1,4349 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : virtio_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2018/12/05 +// Description : The description of Hi1823V100 project +// Others : Generated automatically by nManager V5.1 +// History : +// ****************************************************************************** + +#ifndef VIRTIO_C_UNION_DEFINE_H +#define VIRTIO_C_UNION_DEFINE_H + +/* Define the union csr_rsvd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 engn_rsvd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsvd0_u; + +/* Define the union csr_rsvd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 engn_rsvd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsvd1_u; + +/* Define the union csr_rsvd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 engn_rsvd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsvd2_u; + +/* Define the union csr_rsvd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 engn_rsvd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsvd3_u; + +/* Define the union csr_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_vector_u; + +/* Define the union csr_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 16; /* [15:0] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_status_u; + +/* Define the union csr_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 16; /* [15:0] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_en_u; + +/* Define the union csr_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int0_rawstatus : 1; /* [0] */ + u32 int0_insert : 1; /* [1] */ + u32 int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int0_sticky_u; + +/* Define the union csr_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int1_rawstatus : 1; /* [0] */ + u32 int1_insert : 1; /* [1] */ + u32 int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int1_sticky_u; + +/* Define the union csr_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int2_rawstatus : 1; /* [0] */ + u32 int2_insert : 1; /* [1] */ + u32 int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int2_sticky_u; + +/* Define the union csr_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int3_rawstatus : 1; /* [0] */ + u32 int3_insert : 1; /* [1] */ + u32 int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int3_sticky_u; + +/* Define the union csr_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int4_rawstatus : 1; /* [0] */ + u32 int4_insert : 1; /* [1] */ + u32 int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int4_sticky_u; + +/* Define the union csr_int5_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int5_rawstatus : 1; /* [0] */ + u32 int5_insert : 1; /* [1] */ + u32 int5_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int5_sticky_u; + +/* Define the union csr_int6_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int6_rawstatus : 1; /* [0] */ + u32 int6_insert : 1; /* [1] */ + u32 int6_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int6_sticky_u; + +/* Define the union csr_int7_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int7_rawstatus : 1; /* [0] */ + u32 int7_insert : 1; /* [1] */ + u32 int7_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int7_sticky_u; + +/* Define the union csr_int8_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int8_rawstatus : 1; /* [0] */ + u32 int8_insert : 1; /* [1] */ + u32 int8_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int8_sticky_u; + +/* Define the union csr_int9_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int9_rawstatus : 1; /* [0] */ + u32 int9_insert : 1; /* [1] */ + u32 int9_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int9_sticky_u; + +/* Define the union csr_int10_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int10_rawstatus : 1; /* [0] */ + u32 int10_insert : 1; /* [1] */ + u32 int10_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int10_sticky_u; + +/* Define the union csr_int11_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int11_rawstatus : 1; /* [0] */ + u32 int11_insert : 1; /* [1] */ + u32 int11_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int11_sticky_u; + +/* Define the union csr_int12_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int12_rawstatus : 1; /* [0] */ + u32 int12_insert : 1; /* [1] */ + u32 int12_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int12_sticky_u; + +/* Define the union csr_int13_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int13_rawstatus : 1; /* [0] */ + u32 int13_insert : 1; /* [1] */ + u32 int13_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int13_sticky_u; + +/* Define the union csr_int14_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int14_rawstatus : 1; /* [0] */ + u32 int14_insert : 1; /* [1] */ + u32 int14_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int14_sticky_u; + +/* Define the union csr_int15_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int15_rawstatus : 1; /* [0] */ + u32 int15_insert : 1; /* [1] */ + u32 int15_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int15_sticky_u; + +/* Define the union csr_common_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_id_table_init_start : 1; /* [0] */ + u32 dtm_bitmap_init_start : 1; /* [1] */ + u32 stm_bitmap_init_start : 1; /* [2] */ + u32 device_attri_table_init_start : 1; /* [3] */ + u32 rsv_2 : 11; /* [14:4] */ + u32 smlc_mem_init_start : 1; /* [15] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_common_mem_init_u; + +/* Define the union csr_common_mem_init_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_id_table_init_done : 1; /* [0] */ + u32 dtm_bitmap_init_done : 1; /* [1] */ + u32 stm_bitmap_init_done : 1; /* [2] */ + u32 device_attri_table_init_done : 1; /* [3] */ + u32 rsv_4 : 12; /* [15:4] */ + u32 host_id_table_init_busy : 1; /* [16] */ + u32 dtm_bitmap_init_busy : 1; /* [17] */ + u32 stm_bitmap_init_busy : 1; /* [18] */ + u32 device_attri_table_init_busy : 1; /* [19] */ + u32 rsv_5 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_common_mem_init_status_u; + +/* Define the union csr_iif_irsp_mem_h_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_mem_h_ecc_ucrt_addr : 10; /* [9:0] */ + u32 rsv_6 : 6; /* [15:10] */ + u32 irsp_mem_h_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 irsp_mem_h_ecc_inj_ack : 2; /* [25:24] */ + u32 irsp_mem_h_ecc_inj_req : 2; /* [27:26] */ + u32 irsp_mem_h_ecc_bypass : 1; /* [28] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iif_irsp_mem_h_ecc_cfg_status_u; + +/* Define the union csr_iif_irsp_mem_l_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_mem_l_ecc_ucrt_addr : 10; /* [9:0] */ + u32 rsv_8 : 6; /* [15:10] */ + u32 irsp_mem_l_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 irsp_mem_l_ecc_inj_ack : 2; /* [25:24] */ + u32 irsp_mem_l_ecc_inj_req : 2; /* [27:26] */ + u32 irsp_mem_l_ecc_bypass : 1; /* [28] */ + u32 rsv_9 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iif_irsp_mem_l_ecc_cfg_status_u; + +/* Define the union csr_ersp_mem_h_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ersp_mem_h_ecc_ucrt_addr : 10; /* [9:0] */ + u32 rsv_10 : 6; /* [15:10] */ + u32 ersp_mem_h_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 ersp_mem_h_ecc_inj_ack : 2; /* [25:24] */ + u32 ersp_mem_h_ecc_inj_req : 2; /* [27:26] */ + u32 ersp_mem_h_ecc_bypass : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ersp_mem_h_ecc_cfg_status_u; + +/* Define the union csr_ersp_mem_l_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ersp_mem_l_ecc_ucrt_addr : 10; /* [9:0] */ + u32 rsv_12 : 6; /* [15:10] */ + u32 ersp_mem_l_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 ersp_mem_l_ecc_inj_ack : 2; /* [25:24] */ + u32 ersp_mem_l_ecc_inj_req : 2; /* [27:26] */ + u32 ersp_mem_l_ecc_bypass : 1; /* [28] */ + u32 rsv_13 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ersp_mem_l_ecc_cfg_status_u; + +/* Define the union csr_erqst_fifo_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 erqst_fifo_ecc_ucrt_addr : 7; /* [6:0] */ + u32 rsv_14 : 9; /* [15:7] */ + u32 erqst_fifo_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 erqst_fifo_ecc_inj_ack : 2; /* [25:24] */ + u32 erqst_fifo_ecc_inj_req : 2; /* [27:26] */ + u32 erqst_fifo_ecc_bypass : 1; /* [28] */ + u32 rsv_15 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_erqst_fifo_ecc_cfg_status_u; + +/* Define the union csr_ecsr_fifo_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecsr_fifo_ecc_ucrt_addr : 7; /* [6:0] */ + u32 rsv_16 : 9; /* [15:7] */ + u32 ecsr_fifo_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 ecsr_fifo_ecc_inj_ack : 2; /* [25:24] */ + u32 ecsr_fifo_ecc_inj_req : 2; /* [27:26] */ + u32 ecsr_fifo_ecc_bypass : 1; /* [28] */ + u32 rsv_17 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecsr_fifo_ecc_cfg_status_u; + +/* Define the union csr_ssb_mem_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ssb_ecc_ucrt_addr : 6; /* [5:0] */ + u32 rsv_18 : 10; /* [15:6] */ + u32 ssb_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 ssb_ecc_inj_ack : 2; /* [25:24] */ + u32 ssb_ecc_inj_req : 2; /* [27:26] */ + u32 ssb_ecc_bypass : 1; /* [28] */ + u32 rsv_19 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ssb_mem_ecc_cfg_status_u; + +/* Define the union csr_dsb_mem_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsb_ecc_ucrt_addr : 7; /* [6:0] */ + u32 rsv_20 : 9; /* [15:7] */ + u32 dsb_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 dsb_ecc_inj_ack : 2; /* [25:24] */ + u32 dsb_ecc_inj_req : 2; /* [27:26] */ + u32 dsb_ecc_bypass : 1; /* [28] */ + u32 rsv_21 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dsb_mem_ecc_cfg_status_u; + +/* Define the union csr_host_id_table_mem_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_id_table_ecc_ucrt_addr : 8; /* [7:0] */ + u32 rsv_22 : 8; /* [15:8] */ + u32 host_id_table_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 host_id_table_ecc_inj_ack : 2; /* [25:24] */ + u32 host_id_table_ecc_inj_req : 2; /* [27:26] */ + u32 host_id_table_ecc_bypass : 1; /* [28] */ + u32 rsv_23 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_id_table_mem_ecc_cfg_status_u; + +/* Define the union csr_dev_attri_table_mem_ecc_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dev_attri_table_ecc_ucrt_addr : 4; /* [3:0] */ + u32 rsv_24 : 12; /* [15:4] */ + u32 dev_attri_table_ecc_crt_err_cnt : 8; /* [23:16] */ + u32 dev_attri_table_ecc_inj_ack : 2; /* [25:24] */ + u32 dev_attri_table_ecc_inj_req : 2; /* [27:26] */ + u32 dev_attri_table_ecc_bypass : 1; /* [28] */ + u32 rsv_25 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dev_attri_table_mem_ecc_cfg_status_u; + +/* Define the union csr_tpram_wr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_addr : 8; /* [7:0] */ + u32 rsv_26 : 4; /* [11:8] */ + u32 virtio_wr_rdy : 1; /* [12] */ + u32 rsv_27 : 3; /* [15:13] */ + u32 virtio_wr_cfg : 1; /* [16] */ + u32 rsv_28 : 3; /* [19:17] */ + u32 virtio_wr_enable : 1; /* [20] */ + u32 rsv_29 : 3; /* [23:21] */ + u32 virtio_wr_sel : 2; /* [25:24] */ + u32 rsv_30 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ctrl_u; + +/* Define the union csr_tpram_wr_wen_data_31_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_31_0_u; + +/* Define the union csr_tpram_wr_wen_data_63_32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_63_32_u; + +/* Define the union csr_tpram_wr_wen_data_95_64_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_95_64_u; + +/* Define the union csr_tpram_wr_wen_data_127_96_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_127_96_u; + +/* Define the union csr_tpram_wr_wen_data_159_128_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_159_128_u; + +/* Define the union csr_tpram_wr_wen_data_191_160_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_191_160_u; + +/* Define the union csr_tpram_wr_wen_data_223_192_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_223_192_u; + +/* Define the union csr_tpram_wr_wen_data_255_224_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_255_224_u; + +/* Define the union csr_tpram_wr_wen_data_287_256_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_287_256 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_287_256_u; + +/* Define the union csr_tpram_wr_wen_data_319_288_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_319_288 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_319_288_u; + +/* Define the union csr_tpram_wr_wen_data_335_320_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_wdata_335_320 : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_wen_data_335_320_u; + +/* Define the union csr_tpram_wr_ren_data_31_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_31_0_u; + +/* Define the union csr_tpram_wr_ren_data_63_32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_63_32_u; + +/* Define the union csr_tpram_wr_ren_data_95_64_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_95_64_u; + +/* Define the union csr_tpram_wr_ren_data_127_96_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_127_96_u; + +/* Define the union csr_tpram_wr_ren_data_159_128_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_159_128_u; + +/* Define the union csr_tpram_wr_ren_data_191_160_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_191_160_u; + +/* Define the union csr_tpram_wr_ren_data_223_192_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_223_192_u; + +/* Define the union csr_tpram_wr_ren_data_255_224_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_255_224_u; + +/* Define the union csr_tpram_wr_ren_data_287_256_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_287_256 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_287_256_u; + +/* Define the union csr_tpram_wr_ren_data_319_288_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_319_288 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_319_288_u; + +/* Define the union csr_tpram_wr_ren_data_351_320_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_351_320 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_351_320_u; + +/* Define the union csr_tpram_wr_ren_data_383_352_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_383_352 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_383_352_u; + +/* Define the union csr_tpram_wr_ren_data_415_384_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_415_384 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_415_384_u; + +/* Define the union csr_tpram_wr_ren_data_447_416_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_447_416 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_447_416_u; + +/* Define the union csr_tpram_wr_ren_data_479_448_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_479_448 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_479_448_u; + +/* Define the union csr_tpram_wr_ren_data_511_480_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_511_480 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_511_480_u; + +/* Define the union csr_tpram_wr_ren_data_543_512_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_543_512 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_543_512_u; + +/* Define the union csr_tpram_wr_ren_data_575_544_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_575_544 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_575_544_u; + +/* Define the union csr_tpram_wr_ren_data_607_576_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_607_576 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_607_576_u; + +/* Define the union csr_tpram_wr_ren_data_639_608_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_639_608 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_639_608_u; + +/* Define the union csr_tpram_wr_ren_data_671_640_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_671_640 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_671_640_u; + +/* Define the union csr_tpram_wr_ren_data_703_672_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_703_672 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_703_672_u; + +/* Define the union csr_tpram_wr_ren_data_735_704_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_735_704 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_735_704_u; + +/* Define the union csr_tpram_wr_ren_data_767_736_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_767_736 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_767_736_u; + +/* Define the union csr_tpram_wr_ren_data_773_768_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_wr_rdata_773_768 : 6; /* [5:0] */ + u32 rsv_32 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tpram_wr_ren_data_773_768_u; + +/* Define the union csr_load_balance_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_engine_magic_box_pg_cfg : 4; /* [3:0] */ + u32 virtio_engine_lbf : 2; /* [5:4] */ + u32 rsv_33 : 2; /* [7:6] */ + u32 virtio_engine_main : 1; /* [8] */ + u32 rsv_34 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_load_balance_cfg_u; + +/* Define the union csr_flex_q_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_engine_flex_q_en : 1; /* [0] */ + u32 rsv_35 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flex_q_cfg_u; + +/* Define the union csr_vq_cntx_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_engine_vq_cntx_size : 2; /* [1:0] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vq_cntx_size_u; + +/* Define the union csr_virtio_region_off_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_region_4_off : 6; /* [5:0] */ + u32 rsv_37 : 2; /* [7:6] */ + u32 virtio_region_3_off : 6; /* [13:8] */ + u32 rsv_38 : 2; /* [15:14] */ + u32 virtio_region_2_off : 6; /* [21:16] */ + u32 rsv_39 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_region_off_cfg_u; + +/* Define the union csr_virtio_loc_sgl_size_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_virtq_sgl_ptr_max : 6; /* [5:0] */ + u32 rsv_40 : 2; /* [7:6] */ + u32 virtio_virtq_sgl_size : 7; /* [14:8] */ + u32 rsv_41 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_loc_sgl_size_cfg_u; + +/* Define the union csr_virtio_loc_idesc_size_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_virtq_idesc_ptr_max : 9; /* [8:0] */ + u32 rsv_42 : 3; /* [11:9] */ + u32 virtio_virtq_idesc_size : 10; /* [21:12] */ + u32 rsv_43 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_loc_idesc_size_cfg_u; + +/* Define the union csr_virtio_dma_wait_max_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_dma_wait_max : 4; /* [3:0] */ + u32 virtio_fetching_sgl_max : 5; /* [8:4] */ + u32 rsv_44 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dma_wait_max_cfg_u; + +/* Define the union csr_virtio_prefetch_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_loc_idesc_aful_th : 10; /* [9:0] */ + u32 rsv_45 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_prefetch_th_u; + +/* Define the union csr_virtio_max_outstand_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_loc_idesc_alempt_th : 10; /* [9:0] */ + u32 rsv_46 : 2; /* [11:10] */ + u32 virtio_avail_idx_alempt_th : 7; /* [18:12] */ + u32 rsv_47 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_max_outstand_th_u; + +/* Define the union csr_virtio_split_chain_speculate_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_split_speculate_th : 4; /* [3:0] */ + u32 rsv_48 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_split_chain_speculate_th_cfg_u; + +/* Define the union csr_virtio_sqe_dma_template_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_sqe_dma_template_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_sqe_dma_template_dw0_u; + +/* Define the union csr_virtio_sqe_dma_template_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_sqe_dma_template_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_sqe_dma_template_dw1_u; + +/* Define the union csr_virtio_sqe_dma_template_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_sqe_dma_template_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_sqe_dma_template_dw2_u; + +/* Define the union csr_virtio_sqe_dma_template_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_sqe_dma_template_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_sqe_dma_template_dw3_u; + +/* Define the union csr_virtio_rqe_dma_template_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_rqe_dma_template_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_rqe_dma_template_dw0_u; + +/* Define the union csr_virtio_rqe_dma_template_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_rqe_dma_template_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_rqe_dma_template_dw1_u; + +/* Define the union csr_virtio_rqe_dma_template_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_rqe_dma_template_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_rqe_dma_template_dw2_u; + +/* Define the union csr_virtio_rqe_dma_template_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_rqe_dma_template_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_rqe_dma_template_dw3_u; + +/* Define the union csr_nvme_qp_cntx_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_region_2_off : 6; /* [5:0] */ + u32 rsv_49 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_qp_cntx_cfg0_u; + +/* Define the union csr_nvme_qp_cntx_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_region_2_ptr_max : 7; /* [6:0] */ + u32 rsv_50 : 1; /* [7] */ + u32 nvme_region_2_size : 8; /* [15:8] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_qp_cntx_cfg1_u; + +/* Define the union csr_virtio_engine_nvme_cntx_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_qp_cntx_start_offset : 21; /* [20:0] */ + u32 rsv_52 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_engine_nvme_cntx_offset_u; + +/* Define the union csr_virtio_engine_virtio_cntx_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_vq_cntx_start_offset : 13; /* [12:0] */ + u32 rsv_53 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_engine_virtio_cntx_offset_u; + +/* Define the union csr_nvme_dma_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_dma_buf_min : 4; /* [3:0] */ + u32 nvme_dma_wait_max : 4; /* [7:4] */ + u32 rsv_54 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_dma_cfg_u; + +/* Define the union csr_nvme_dma_template_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_dma_template_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_dma_template_dw0_u; + +/* Define the union csr_nvme_dma_template_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_dma_template_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_dma_template_dw1_u; + +/* Define the union csr_nvme_dma_template_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_dma_template_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_dma_template_dw2_u; + +/* Define the union csr_irqst_credit_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_credit_cnt : 4; /* [3:0] */ + u32 rsv_55 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_credit_status_u; + +/* Define the union csr_irqst_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_fifo_empty : 1; /* [0] */ + u32 irqst_fifo_full : 1; /* [1] */ + u32 rsv_56 : 2; /* [3:2] */ + u32 irqst_fifo_cnt : 4; /* [7:4] */ + u32 rsv_57 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_fifo_status_u; + +/* Define the union csr_irqst_statistic_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_api_cnt_node_id : 5; /* [4:0] */ + u32 rsv_58 : 3; /* [7:5] */ + u32 irqst_api_cnt_all_node_en : 1; /* [8] */ + u32 rsv_59 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_statistic_api_u; + +/* Define the union csr_irqst_api_with_a_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_api_with_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_api_with_a_cnt_u; + +/* Define the union csr_irqst_api_without_a_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_api_without_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_api_without_a_cnt_u; + +/* Define the union csr_irqst_api_invalid_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_api_invalid_cnt : 8; /* [7:0] */ + u32 irqst_api_invalid_a : 1; /* [8] */ + u32 rsv_60 : 3; /* [11:9] */ + u32 irqst_api_invalid_op_id : 5; /* [16:12] */ + u32 rsv_61 : 3; /* [19:17] */ + u32 irqst_api_invalid_src : 5; /* [24:20] */ + u32 rsv_62 : 3; /* [27:25] */ + u32 irqst_api_invalid_m : 1; /* [28] */ + u32 rsv_63 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_api_invalid_status_u; + +/* Define the union csr_irqst_int_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqst_sop_eop_mismatch_int_en : 1; /* [0] */ + u32 irqst_invalid_flit_int_en : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irqst_int_en_cfg_u; + +/* Define the union csr_irsp_credit_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_credit_cnt : 8; /* [7:0] */ + u32 rsv_65 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irsp_credit_status_u; + +/* Define the union csr_irsp_fifo_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_fifo_empty : 1; /* [0] */ + u32 irsp_fifo_full : 1; /* [1] */ + u32 rsv_66 : 2; /* [3:2] */ + u32 irsp_fifo_cnt : 8; /* [11:4] */ + u32 rsv_67 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irsp_fifo_cfg_status_u; + +/* Define the union csr_irsp_api_statistic_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_api_from_cpi_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irsp_api_statistic_u; + +/* Define the union csr_irsp_invalid_flit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_flit_not_from_cpi_cnt : 8; /* [7:0] */ + u32 irsp_flit_not_from_cpi_src : 5; /* [12:8] */ + u32 rsv_68 : 3; /* [15:13] */ + u32 irsp_api_not_from_cpi_cnt : 8; /* [23:16] */ + u32 rsv_69 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irsp_invalid_flit_u; + +/* Define the union csr_irsp_int_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irsp_flit_not_from_cpi_int_en : 1; /* [0] */ + u32 irsp_sop_eop_mismatch_int_en : 1; /* [1] */ + u32 rsv_70 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_irsp_int_en_cfg_u; + +/* Define the union csr_icsr_credit_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_credit_cnt : 5; /* [4:0] */ + u32 rsv_71 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_credit_status_u; + +/* Define the union csr_icsr_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_fifo_empty : 1; /* [0] */ + u32 icsr_fifo_full : 1; /* [1] */ + u32 rsv_72 : 2; /* [3:2] */ + u32 ics_fifo_cnt : 5; /* [8:4] */ + u32 rsv_73 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_fifo_status_u; + +/* Define the union csr_icsr_api_with_a_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_api_with_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_api_with_a_cnt_u; + +/* Define the union csr_icsr_api_without_a_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_api_without_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_api_without_a_cnt_u; + +/* Define the union csr_icsr_invalid_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_invalid_flit_cnt : 8; /* [7:0] */ + u32 icsr_invalid_flit_op_id : 5; /* [12:8] */ + u32 rsv_74 : 3; /* [15:13] */ + u32 icsr_invalid_flit_src : 5; /* [20:16] */ + u32 rsv_75 : 3; /* [23:21] */ + u32 icsr_invalid_flit_type : 2; /* [25:24] */ + u32 rsv_76 : 2; /* [27:26] */ + u32 icsr_invalid_flit_ack : 1; /* [28] */ + u32 rsv_77 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_invalid_api_u; + +/* Define the union csr_icsr_cpath_timeout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_no_thread_timeout_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_cpath_timeout_cfg_u; + +/* Define the union csr_icsr_cpath_timeout_drop_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_drop_cpath_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_cpath_timeout_drop_api_cnt_u; + +/* Define the union csr_icsr_int_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icsr_invalid_flit_int_en : 1; /* [0] */ + u32 rsv_78 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icsr_int_en_cfg_u; + +/* Define the union csr_isch_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isch_wrr_icsr_weight : 4; /* [3:0] */ + u32 isch_wrr_irsp_weight : 4; /* [7:4] */ + u32 icsr_wrrsp_l_weight : 4; /* [11:8] */ + u32 icsr_wrrsp_m_weight : 4; /* [15:12] */ + u32 icsr_wrrsp_h_weight : 4; /* [19:16] */ + u32 icsr_wrrsp_sp_en : 1; /* [20] */ + u32 rsv_79 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_isch_weight_cfg_u; + +/* Define the union csr_erqst_credit_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 erqst_credit_cnt : 4; /* [3:0] */ + u32 erqst_credit_th : 4; /* [7:4] */ + u32 rsv_80 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_erqst_credit_status_u; + +/* Define the union csr_erqst_dma_template_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 erqst_dma_c_chl : 2; /* [1:0] */ + u32 rsv_81 : 2; /* [3:2] */ + u32 erqst_dma_attr_offset : 6; /* [9:4] */ + u32 rsv_82 : 2; /* [11:10] */ + u32 erqst_dma_so_ro : 2; /* [13:12] */ + u32 rsv_83 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_erqst_dma_template_u; + +/* Define the union csr_erqst_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 erqst_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_erqst_api_cnt_u; + +/* Define the union csr_erqst_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 erqst_fifo_empty : 1; /* [0] */ + u32 erqst_fifo_full : 1; /* [1] */ + u32 rsv_84 : 2; /* [3:2] */ + u32 erqst_fifo_cnt : 9; /* [12:4] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_erqst_fifo_status_u; + +/* Define the union csr_ersp_credit_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ersp_credit_cnt : 4; /* [3:0] */ + u32 ersp_credit_th : 4; /* [7:4] */ + u32 rsv_86 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ersp_credit_status_u; + +/* Define the union csr_ersp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ersp_fifo_empty : 1; /* [0] */ + u32 ersp_fifo_full : 1; /* [1] */ + u32 rsv_87 : 2; /* [3:2] */ + u32 ersp_fifo_cnt : 7; /* [10:4] */ + u32 rsv_88 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ersp_fifo_status_u; + +/* Define the union csr_ersp_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ersp_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ersp_flit_cnt_u; + +/* Define the union csr_ersp_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ersp_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ersp_api_cnt_u; + +/* Define the union csr_ecsr_credit_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecsr_credit_cnt : 2; /* [1:0] */ + u32 rsv_89 : 2; /* [3:2] */ + u32 ecsr_credit_th : 2; /* [5:4] */ + u32 rsv_90 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecsr_credit_status_u; + +/* Define the union csr_ecsr_fifo_cfg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecsr_fifo_empty : 1; /* [0] */ + u32 ecsr_fifo_full : 1; /* [1] */ + u32 rsv_91 : 2; /* [3:2] */ + u32 ecsr_fifo_cnt : 9; /* [12:4] */ + u32 rsv_92 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecsr_fifo_cfg_status_u; + +/* Define the union csr_ecsr_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecsr_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecsr_api_cnt_u; + +/* Define the union csr_sif_smlc_outstanding_thread_scan_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_scan_thread_fun_id : 12; /* [11:0] */ + u32 sif_scan_thread_req : 1; /* [12] */ + u32 rsv_93 : 3; /* [15:13] */ + u32 sif_scan_thread_outst_num : 7; /* [22:16] */ + u32 rsv_94 : 1; /* [23] */ + u32 sif_scan_thread_busy : 1; /* [24] */ + u32 sif_scan_thread_done : 1; /* [25] */ + u32 rsv_95 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_outstanding_thread_scan_u; + +/* Define the union csr_sif_smlc_delay_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_delay_query_thread_id : 6; /* [5:0] */ + u32 rsv_96 : 2; /* [7:6] */ + u32 sif_delay_query_req : 1; /* [8] */ + u32 rsv_97 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_delay_cfg_u; + +/* Define the union csr_sif_smlc_delay_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_delay_query_thread_timer : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_delay_timer_u; + +/* Define the union csr_sif_smlc_delay_min_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_delay_query_thread_timer_min : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_delay_min_u; + +/* Define the union csr_sif_smlc_delay_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_delay_query_thread_timer_max : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_delay_max_u; + +/* Define the union csr_sif_fun_mem_mode_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_func_mem_base_addr : 18; /* [17:0] */ + u32 rsv_98 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_fun_mem_mode_baddr_u; + +/* Define the union csr_sif_vq_mem_mode_baddr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_virtq_mem_base_addr : 18; /* [17:0] */ + u32 rsv_99 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_vq_mem_mode_baddr_cfg_u; + +/* Define the union csr_sif_instance_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_nvme_instance_id : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 sif_virtio_instance_id : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 sif_cache_instance_id : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_instance_id_cfg_u; + +/* Define the union csr_sif_smlc_if_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_func_cntx_mem_en : 1; /* [0] */ + u32 sif_virtq_cntx_stick_en : 1; /* [1] */ + u32 sif_func_cntx_stick_en : 1; /* [2] */ + u32 sif_virtq_cntx_mem_en : 1; /* [3] */ + u32 sif_mem_index_refill_len : 6; /* [9:4] */ + u32 sif_mem_index_refill_len_valid : 1; /* [10] */ + u32 rsv_103 : 9; /* [19:11] */ + u32 sif_cache_mem_index_type : 4; /* [23:20] */ + u32 sif_nvme_mem_index_type : 4; /* [27:24] */ + u32 sif_virtio_mem_index_type : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_if_cfg_0_u; + +/* Define the union csr_sif_smlc_if_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_nvme_region0_subentry : 4; /* [3:0] */ + u32 sif_nvme_region1_subentry : 4; /* [7:4] */ + u32 sif_nvme_region2_subentry : 4; /* [11:8] */ + u32 sif_virtio_region0_subentry : 4; /* [15:12] */ + u32 sif_virtio_region1_subentry : 4; /* [19:16] */ + u32 sif_virtio_region2_subentry : 4; /* [23:20] */ + u32 sif_virtio_region3_subentry : 4; /* [27:24] */ + u32 sif_virtio_region4_subentry : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_if_cfg_1_u; + +/* Define the union csr_sif_smlc_if_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_pcie_template : 6; /* [5:0] */ + u32 rsv_104 : 2; /* [7:6] */ + u32 sif_func_cntx_cache_index_sel : 2; /* [9:8] */ + u32 sif_virtq_cntx_cache_index_sel : 2; /* [11:10] */ + u32 memop_sr_not_early_done_en : 1; /* [12] */ + u32 memop_st_not_early_done_en : 1; /* [13] */ + u32 rsv_105 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_if_cfg_2_u; + +/* Define the union csr_sif_smlc_if_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_thread_timeout_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_if_cfg_3_u; + +/* Define the union csr_host_ppf_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_host2_ppf : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 sif_host3_ppf : 12; /* [27:16] */ + u32 rsv_107 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_ppf_cfg_0_u; + +/* Define the union csr_host_ppf_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_host0_ppf : 12; /* [11:0] */ + u32 rsv_108 : 4; /* [15:12] */ + u32 sif_host1_ppf : 12; /* [27:16] */ + u32 rsv_109 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_ppf_cfg_1_u; + +/* Define the union csr_sif_smlc_thread_timeout_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_smlc_thread_timeout_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_thread_timeout_status_0_u; + +/* Define the union csr_sif_smlc_thread_timeout_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_smlc_thread_timeout_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_smlc_thread_timeout_status_1_u; + +/* Define the union csr_sif_int_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sif_cacheline_index_of_int_en : 1; /* [0] */ + u32 rsv_110 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sif_int_en_cfg_u; + +/* Define the union csr_stm_share_thread_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stm_share_thread_max : 7; /* [6:0] */ + u32 rsv_111 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stm_share_thread_max_u; + +/* Define the union csr_stm_channel_thread_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stm_flr_thread_max : 7; /* [6:0] */ + u32 stm_flr_share_en : 1; /* [7] */ + u32 stm_csr_thread_max : 7; /* [14:8] */ + u32 stm_csr_share_en : 1; /* [15] */ + u32 stm_resp_thread_max : 7; /* [22:16] */ + u32 stm_resp_share_en : 1; /* [23] */ + u32 stm_rqst_thread_max : 7; /* [30:24] */ + u32 stm_rqst_share_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stm_channel_thread_th_cfg_u; + +/* Define the union csr_stm_share_thread_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stm_share_thread_cnt : 7; /* [6:0] */ + u32 rsv_112 : 1; /* [7] */ + u32 stm_free_addr_cnt : 7; /* [14:8] */ + u32 rsv_113 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stm_share_thread_status_u; + +/* Define the union csr_stm_channel_thread_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stm_flr_thread_cnt : 7; /* [6:0] */ + u32 rsv_114 : 1; /* [7] */ + u32 stm_csr_thread_cnt : 7; /* [14:8] */ + u32 rsv_115 : 1; /* [15] */ + u32 stm_resp_thread_cnt : 7; /* [22:16] */ + u32 rsv_116 : 1; /* [23] */ + u32 stm_rqst_thread_cnt : 7; /* [30:24] */ + u32 rsv_117 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stm_channel_thread_status_u; + +/* Define the union csr_stm_fifo0_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stm_fifo_0_empty : 1; /* [0] */ + u32 stm_fifo_0_full : 1; /* [1] */ + u32 rsv_118 : 2; /* [3:2] */ + u32 stm_fifo_0_cnt : 7; /* [10:4] */ + u32 rsv_119 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stm_fifo0_status_u; + +/* Define the union csr_stm_fifo1_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stm_fifo_1_empty : 1; /* [0] */ + u32 stm_fifo_1_full : 1; /* [1] */ + u32 rsv_120 : 2; /* [3:2] */ + u32 stm_fifo_1_cnt : 7; /* [10:4] */ + u32 rsv_121 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stm_fifo1_status_u; + +/* Define the union csr_dtm_tag_alempty_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_desc_tag_aful_th : 8; /* [7:0] */ + u32 rsv_122 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_tag_alempty_th_u; + +/* Define the union csr_dtm_tag_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_desc_tag_max : 8; /* [7:0] */ + u32 dtm_desc_share_en : 1; /* [8] */ + u32 rsv_123 : 3; /* [11:9] */ + u32 dtm_db_tag_max : 8; /* [19:12] */ + u32 dtm_db_share_en : 1; /* [20] */ + u32 rsv_124 : 3; /* [23:21] */ + u32 dtm_share_tag_max : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_tag_th_cfg_u; + +/* Define the union csr_dtm_tag_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_desc_tag_cnt : 8; /* [7:0] */ + u32 dtm_db_tag_cnt : 8; /* [15:8] */ + u32 dtm_share_tag_cnt : 8; /* [23:16] */ + u32 dtm_free_addr_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_tag_status_u; + +/* Define the union csr_dtm_dma_outstanding_tag_scan_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_scan_tag_fun_id : 12; /* [11:0] */ + u32 dtm_scan_tag_req : 1; /* [12] */ + u32 rsv_125 : 3; /* [15:13] */ + u32 dtm_scan_tag_outst_num : 8; /* [23:16] */ + u32 dtm_scan_tag_busy : 1; /* [24] */ + u32 dtm_scan_tag_done : 1; /* [25] */ + u32 rsv_126 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_outstanding_tag_scan_u; + +/* Define the union csr_dtm_dma_delay_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_delay_query_tag_id : 7; /* [6:0] */ + u32 rsv_127 : 1; /* [7] */ + u32 dtm_delay_query_req : 1; /* [8] */ + u32 rsv_128 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_delay_cfg_u; + +/* Define the union csr_dtm_dma_delay_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_delay_query_tag_timer : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_delay_timer_u; + +/* Define the union csr_dtm_dma_delay_min_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_delay_query_tag_timer_min : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_delay_min_u; + +/* Define the union csr_dtm_dma_delay_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_delay_query_tag_timer_max : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_delay_max_u; + +/* Define the union csr_dtm_dma_tag_timeout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_dma_tag_timeout_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_tag_timeout_cfg_u; + +/* Define the union csr_dtm_dma_tag_timeout_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_dma_tag_timeout_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_tag_timeout_status_0_u; + +/* Define the union csr_dtm_dma_tag_timeout_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_dma_tag_timeout_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_tag_timeout_status_1_u; + +/* Define the union csr_dtm_dma_tag_timeout_status_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_dma_tag_timeout_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_tag_timeout_status_2_u; + +/* Define the union csr_dtm_dma_tag_timeout_status_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtm_dma_tag_timeout_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtm_dma_tag_timeout_status_3_u; + +/* Define the union csr_nvme_cpath_total_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_total_st_op_cnt : 16; /* [15:0] */ + u32 ncpath_dfx_total_ld_op_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_total_api_cnt_u; + +/* Define the union csr_nvme_cpath_invalid_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_flr_aeqe_pending_cnt : 4; /* [3:0] */ + u32 ncpath_dfx_aeqe_pending_cnt : 4; /* [7:4] */ + u32 ncpath_dfx_st_no_aeqe_cnt : 4; /* [11:8] */ + u32 ncpath_dfx_invld_st_op_cnt : 4; /* [15:12] */ + u32 ncpath_dfx_invld_ld_op_cnt : 4; /* [19:16] */ + u32 ncpath_dfx_invld_field_cnt : 4; /* [23:20] */ + u32 ncpath_dfx_smlc_err_cnt : 4; /* [27:24] */ + u32 ncpath_dfx_e0e1_api_cnt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_invalid_api_cnt_u; + +/* Define the union csr_nvme_cpath_last_invalid_load_operation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_invld_ld_op_funcid : 12; /* [11:0] */ + u32 ncpath_dfx_last_invld_ld_op_a : 1; /* [12] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ncpath_dfx_last_invld_ld_op_ofst : 9; /* [24:16] */ + u32 rsv_130 : 1; /* [25] */ + u32 ncpath_dfx_last_invld_ld_op_size : 2; /* [27:26] */ + u32 ncpath_dfx_last_invld_ld_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_invalid_load_operation_u; + +/* Define the union csr_nvme_cpath_last_invalid_store_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_invld_st_op_funcid : 12; /* [11:0] */ + u32 ncpath_dfx_last_invld_st_op_a : 1; /* [12] */ + u32 rsv_131 : 3; /* [15:13] */ + u32 ncpath_dfx_last_invld_st_op_ofst : 9; /* [24:16] */ + u32 rsv_132 : 1; /* [25] */ + u32 ncpath_dfx_last_invld_st_op_size : 2; /* [27:26] */ + u32 ncpath_dfx_last_invld_st_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_invalid_store_operation_1_u; + +/* Define the union csr_nvme_cpath_last_invalid_store_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_invld_st_op_wdata_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_invalid_store_operation_2_u; + +/* Define the union csr_nvme_cpath_last_invalid_store_operation_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_invld_st_op_wdata_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_invalid_store_operation_3_u; + +/* Define the union csr_nvme_cpath_last_valid_load_operation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_vld_ld_op_funcid : 12; /* [11:0] */ + u32 ncpath_dfx_last_vld_ld_op_a : 1; /* [12] */ + u32 rsv_133 : 3; /* [15:13] */ + u32 ncpath_dfx_last_vld_ld_op_ofst : 9; /* [24:16] */ + u32 rsv_134 : 1; /* [25] */ + u32 ncpath_dfx_last_vld_ld_op_size : 2; /* [27:26] */ + u32 ncpath_dfx_last_vld_ld_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_valid_load_operation_u; + +/* Define the union csr_nvme_cpath_last_valid_store_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_vld_st_op_funcid : 12; /* [11:0] */ + u32 ncpath_dfx_last_vld_st_op_a : 1; /* [12] */ + u32 rsv_135 : 3; /* [15:13] */ + u32 ncpath_dfx_last_vld_st_op_ofst : 9; /* [24:16] */ + u32 rsv_136 : 1; /* [25] */ + u32 ncpath_dfx_last_vld_st_op_size : 2; /* [27:26] */ + u32 ncpath_dfx_last_vld_st_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_valid_store_operation_1_u; + +/* Define the union csr_nvme_cpath_last_valid_store_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_vld_st_op_wdata_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_valid_store_operation_2_u; + +/* Define the union csr_nvme_cpath_last_valid_store_operation_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_dfx_last_vld_st_op_wdata_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_last_valid_store_operation_3_u; + +/* Define the union csr_nvme_cpath_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncpath_flr_aeqe_pending_int_en : 1; /* [0] */ + u32 ncpath_aeqe_pending_int_en : 1; /* [1] */ + u32 ncpath_invld_api_int_en : 1; /* [2] */ + u32 rsv_137 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_cpath_int_en_u; + +/* Define the union csr_nvme_dpath_load_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ndpath_load_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_dpath_load_api_cnt_u; + +/* Define the union csr_nvme_dpath_store_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ndpath_store_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_dpath_store_api_cnt_u; + +/* Define the union csr_virtio_dfx_func_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_dfx_func_id : 13; /* [12:0] */ + u32 rsv_138 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dfx_func_id_cfg_u; + +/* Define the union csr_virtio_dfx_vqn_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_dfx_vqn : 15; /* [14:0] */ + u32 rsv_139 : 1; /* [15] */ + u32 virtio_dfx_glb_vqn : 15; /* [30:16] */ + u32 rsv_140 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dfx_vqn_cfg_u; + +/* Define the union csr_virtio_dpath_total_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_total_st_op_cnt : 16; /* [15:0] */ + u32 vdpath_dfx_total_ld_op_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_total_api_cnt_u; + +/* Define the union csr_virtio_dpath_abnormal_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_st_offside_cnt : 8; /* [7:0] */ + u32 vdpath_dfx_st_aeqe_none_cnt : 8; /* [15:8] */ + u32 vdpath_dfx_st_invld_cnt : 8; /* [23:16] */ + u32 vdpath_dfx_e0e1_api_cnt : 4; /* [27:24] */ + u32 vdpath_dfx_smlc_err_cnt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_abnormal_api_cnt_u; + +/* Define the union csr_virtio_dpath_invld_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_lb_not_me_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_invld_api_cnt_u; + +/* Define the union csr_virtio_dpath_last_valid_load_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_vld_ld_op_funcid : 12; /* [11:0] */ + u32 vdpath_dfx_last_vld_ld_op_dev_type : 2; /* [13:12] */ + u32 rsv_141 : 2; /* [15:14] */ + u32 vdpath_dfx_last_vld_ld_op_qid : 14; /* [29:16] */ + u32 rsv_142 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_valid_load_operation_1_u; + +/* Define the union csr_virtio_dpath_last_valid_load_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_vld_ld_op_region : 3; /* [2:0] */ + u32 rsv_143 : 5; /* [7:3] */ + u32 vdpath_dfx_last_vld_ld_op_length : 5; /* [12:8] */ + u32 rsv_144 : 3; /* [15:13] */ + u32 vdpath_dfx_last_vld_ld_op_offset : 9; /* [24:16] */ + u32 rsv_145 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_valid_load_operation_2_u; + +/* Define the union csr_virtio_dpath_last_valid_store_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_vld_st_op_funcid : 12; /* [11:0] */ + u32 vdpath_dfx_last_vld_st_op_dev_type : 2; /* [13:12] */ + u32 rsv_146 : 2; /* [15:14] */ + u32 vdpath_dfx_last_vld_st_op_qid : 14; /* [29:16] */ + u32 rsv_147 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_valid_store_operation_1_u; + +/* Define the union csr_virtio_dpath_last_valid_store_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_vld_st_op_region : 3; /* [2:0] */ + u32 rsv_148 : 5; /* [7:3] */ + u32 vdpath_dfx_last_vld_st_op_aeqe : 1; /* [8] */ + u32 rsv_149 : 3; /* [11:9] */ + u32 vdpath_dfx_last_vld_st_op_a : 1; /* [12] */ + u32 rsv_150 : 3; /* [15:13] */ + u32 vdpath_dfx_last_vld_st_op_offset : 9; /* [24:16] */ + u32 rsv_151 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_valid_store_operation_2_u; + +/* Define the union csr_virtio_dpath_last_valid_store_operation_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_vld_st_op_byte_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_valid_store_operation_3_u; + +/* Define the union csr_virtio_dpath_last_invalid_load_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_invld_ld_op_funcid : 12; /* [11:0] */ + u32 vdpath_dfx_last_invld_ld_op_dev_type : 2; /* [13:12] */ + u32 rsv_152 : 2; /* [15:14] */ + u32 vdpath_dfx_last_invld_ld_op_qid : 14; /* [29:16] */ + u32 rsv_153 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_invalid_load_operation_1_u; + +/* Define the union csr_virtio_dpath_last_invalid_load_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_invld_ld_op_region : 3; /* [2:0] */ + u32 rsv_154 : 5; /* [7:3] */ + u32 vdpath_dfx_last_invld_ld_op_length : 5; /* [12:8] */ + u32 rsv_155 : 3; /* [15:13] */ + u32 vdpath_dfx_last_invld_ld_op_offset : 9; /* [24:16] */ + u32 rsv_156 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_invalid_load_operation_2_u; + +/* Define the union csr_virtio_dpath_last_invalid_store_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_invld_st_op_funcid : 12; /* [11:0] */ + u32 vdpath_dfx_last_invld_st_op_dev_type : 2; /* [13:12] */ + u32 rsv_157 : 2; /* [15:14] */ + u32 vdpath_dfx_last_invld_st_op_qid : 14; /* [29:16] */ + u32 rsv_158 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_invalid_store_operation_1_u; + +/* Define the union csr_virtio_dpath_last_invalid_store_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_invld_st_op_region : 3; /* [2:0] */ + u32 rsv_159 : 5; /* [7:3] */ + u32 vdpath_dfx_last_invld_st_op_aeqe : 1; /* [8] */ + u32 rsv_160 : 3; /* [11:9] */ + u32 vdpath_dfx_last_invld_st_op_a : 1; /* [12] */ + u32 rsv_161 : 3; /* [15:13] */ + u32 vdpath_dfx_last_invld_st_op_offset : 9; /* [24:16] */ + u32 rsv_162 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_invalid_store_operation_2_u; + +/* Define the union csr_virtio_dpath_last_invalid_store_operation_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_dfx_last_invld_st_op_byte_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_last_invalid_store_operation_3_u; + +/* Define the union csr_virtio_dpath_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdpath_invld_st_ofst_int_en : 1; /* [0] */ + u32 rsv_163 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_dpath_int_en_u; + +/* Define the union csr_virtio_cpath_total_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_total_st_op_cnt : 16; /* [15:0] */ + u32 vcpath_dfx_total_ld_op_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_total_api_cnt_u; + +/* Define the union csr_virtio_cpath_abnormal_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_aeqe_pending_cnt : 16; /* [15:0] */ + u32 vcpath_dfx_st_invld_cnt : 8; /* [23:16] */ + u32 vcpath_dfx_lb_not_me_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_abnormal_api_cnt_u; + +/* Define the union csr_virtio_cpath_invld_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_invld_vq_cfg_rdy_cnt : 8; /* [7:0] */ + u32 vcpath_dfx_invld_st_cnt : 4; /* [11:8] */ + u32 vcpath_dfx_invld_ld_cnt : 4; /* [15:12] */ + u32 vcpath_dfx_invld_field_cnt : 4; /* [19:16] */ + u32 vcpath_dfx_invld_size_cnt : 4; /* [23:20] */ + u32 vcpath_dfx_e0e1_api_cnt : 4; /* [27:24] */ + u32 vcpath_dfx_smlc_err_cnt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_invld_api_cnt_u; + +/* Define the union csr_virtio_cpath_flr_op_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_flr_st_none_cnt : 16; /* [15:0] */ + u32 vcpath_dfx_flr_ld_rsvd_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_flr_op_api_cnt_u; + +/* Define the union csr_virtio_cpath_last_valid_load_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_vld_ld_op_funcid : 12; /* [11:0] */ + u32 vcpath_dfx_last_vld_ld_op_bar_hit : 1; /* [12] */ + u32 vcpath_dfx_last_vld_ld_op_a : 1; /* [13] */ + u32 rsv_164 : 2; /* [15:14] */ + u32 vcpath_dfx_last_vld_ld_op_ofset : 9; /* [24:16] */ + u32 rsv_165 : 3; /* [27:25] */ + u32 vcpath_dfx_last_vld_ld_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_valid_load_operation_1_u; + +/* Define the union csr_virtio_cpath_last_valid_load_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_vld_ld_op_cntx_vld : 1; /* [0] */ + u32 rsv_166 : 3; /* [3:1] */ + u32 vcpath_dfx_last_vld_ld_op_msix_en : 1; /* [4] */ + u32 rsv_167 : 3; /* [7:5] */ + u32 vcpath_dfx_last_vld_ld_op_dev_sts : 8; /* [15:8] */ + u32 vcpath_dfx_last_vld_ld_op_cur_st : 4; /* [19:16] */ + u32 rsv_168 : 4; /* [23:20] */ + u32 vcpath_dfx_last_vld_ld_op_nxt_st : 4; /* [27:24] */ + u32 rsv_169 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_valid_load_operation_2_u; + +/* Define the union csr_virtio_cpath_last_valid_store_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_vld_st_op_funcid : 12; /* [11:0] */ + u32 vcpath_dfx_last_vld_st_op_bar_hit : 1; /* [12] */ + u32 vcpath_dfx_last_vld_st_op_a : 1; /* [13] */ + u32 rsv_170 : 2; /* [15:14] */ + u32 vcpath_dfx_last_vld_st_op_ofset : 9; /* [24:16] */ + u32 rsv_171 : 3; /* [27:25] */ + u32 vcpath_dfx_last_vld_st_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_valid_store_operation_1_u; + +/* Define the union csr_virtio_cpath_last_valid_store_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_vld_st_op_cntx_vld : 1; /* [0] */ + u32 rsv_172 : 3; /* [3:1] */ + u32 vcpath_dfx_last_vld_st_op_msix_en : 1; /* [4] */ + u32 rsv_173 : 3; /* [7:5] */ + u32 vcpath_dfx_last_vld_st_op_dev_sts : 8; /* [15:8] */ + u32 vcpath_dfx_last_vld_st_op_cur_st : 4; /* [19:16] */ + u32 rsv_174 : 4; /* [23:20] */ + u32 vcpath_dfx_last_vld_st_op_nxt_st : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_valid_store_operation_2_u; + +/* Define the union csr_virtio_cpath_last_valid_store_operation_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_vld_st_op_wdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_valid_store_operation_3_u; + +/* Define the union csr_virtio_cpath_last_invalid_load_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_invld_ld_op_funcid : 12; /* [11:0] */ + u32 vcpath_dfx_last_invld_ld_op_bar_hit : 1; /* [12] */ + u32 vcpath_dfx_last_invld_ld_op_a : 1; /* [13] */ + u32 rsv_176 : 2; /* [15:14] */ + u32 vcpath_dfx_last_invld_ld_op_ofset : 9; /* [24:16] */ + u32 rsv_177 : 1; /* [25] */ + u32 vcpath_dfx_last_invld_ld_op_size : 2; /* [27:26] */ + u32 vcpath_dfx_last_invld_ld_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_invalid_load_operation_1_u; + +/* Define the union csr_virtio_cpath_last_invalid_load_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_invld_ld_op_cntx_vld : 1; /* [0] */ + u32 rsv_178 : 3; /* [3:1] */ + u32 vcpath_dfx_last_invld_ld_op_msix_en : 1; /* [4] */ + u32 rsv_179 : 3; /* [7:5] */ + u32 vcpath_dfx_last_invld_ld_op_dev_sts : 8; /* [15:8] */ + u32 vcpath_dfx_last_invld_ld_op_cur_st : 4; /* [19:16] */ + u32 rsv_180 : 4; /* [23:20] */ + u32 vcpath_dfx_last_invld_ld_op_nxt_st : 4; /* [27:24] */ + u32 rsv_181 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_invalid_load_operation_2_u; + +/* Define the union csr_virtio_cpath_last_invalid_store_operation_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_invld_st_op_funcid : 12; /* [11:0] */ + u32 vcpath_dfx_last_invld_st_op_bar_hit : 1; /* [12] */ + u32 vcpath_dfx_last_invld_st_op_a : 1; /* [13] */ + u32 rsv_182 : 2; /* [15:14] */ + u32 vcpath_dfx_last_invld_st_op_ofset : 9; /* [24:16] */ + u32 rsv_183 : 1; /* [25] */ + u32 vcpath_dfx_last_invld_st_op_size : 2; /* [27:26] */ + u32 vcpath_dfx_last_invld_st_op_dwbe : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_invalid_store_operation_1_u; + +/* Define the union csr_virtio_cpath_last_invalid_store_operation_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_invld_st_op_cntx_vld : 1; /* [0] */ + u32 rsv_184 : 3; /* [3:1] */ + u32 vcpath_dfx_last_invld_st_op_msix_en : 1; /* [4] */ + u32 rsv_185 : 3; /* [7:5] */ + u32 vcpath_dfx_last_invld_st_op_dev_sts : 8; /* [15:8] */ + u32 vcpath_dfx_last_invld_st_op_cur_st : 4; /* [19:16] */ + u32 rsv_186 : 4; /* [23:20] */ + u32 vcpath_dfx_last_invld_st_op_nxt_st : 4; /* [27:24] */ + u32 rsv_187 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_invalid_store_operation_2_u; + +/* Define the union csr_virtio_cpath_last_invalid_store_operation_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_dfx_last_invld_st_op_wdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_last_invalid_store_operation_3_u; + +/* Define the union csr_virtio_cpath_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vcpath_aeqe_pending_int_en : 1; /* [0] */ + u32 vcpath_invld_api_int_en : 1; /* [1] */ + u32 rsv_188 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cpath_int_en_u; + +/* Define the union csr_vdb_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdb_api_without_ack_cnt : 16; /* [15:0] */ + u32 vdb_api_with_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vdb_api_cnt_u; + +typedef union { + /* Define the struct bits */ + struct { + u32 glb_vqn : 14; /* [13:0] */ + u32 rsv_195 : 2; /* [15:14] */ + u32 func_id : 12; /* [27:16] */ + u32 int_cnt : 3; /* [30:28] */ + u32 int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} virtio_adjoint_csr_info_u; + +/* Define the union csr_vsdb_pi_invalid_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsdb_pi_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_189 : 2; /* [15:14] */ + u32 vsdb_pi_invalid_func_id : 12; /* [27:16] */ + u32 vsdb_pi_invalid_cnt : 3; /* [30:28] */ + u32 vsdb_pi_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsdb_pi_invalid_info_u; + +/* Define the union csr_vsavidx_pi_invalid_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsavidx_pi_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_190 : 2; /* [15:14] */ + u32 vsavidx_pi_invalid_func_id : 12; /* [27:16] */ + u32 vsavidx_pi_invalid_cnt : 3; /* [30:28] */ + u32 vsavidx_pi_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsavidx_pi_invalid_info_u; + +/* Define the union csr_vsavring_idx_invalid_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsavring_idx_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_191 : 2; /* [15:14] */ + u32 vsavring_idx_invalid_func_id : 12; /* [27:16] */ + u32 vsavring_idx_invalid_cnt : 3; /* [30:28] */ + u32 vsavring_idx_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsavring_idx_invalid_info_u; + +/* Define the union csr_vsavring_idx_invalid_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsavring_idx_invalid_dat : 16; /* [15:0] */ + u32 vsavring_idx_invalid_entry : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsavring_idx_invalid_dat_u; + +/* Define the union csr_vs1st_len_zero_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vs1st_len_zero_glb_vqn : 14; /* [13:0] */ + u32 rsv_192 : 2; /* [15:14] */ + u32 vs1st_len_zero_func_id : 12; /* [27:16] */ + u32 vs1st_len_zero_cnt : 3; /* [30:28] */ + u32 vs1st_len_zero_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vs1st_len_zero_info_u; + +/* Define the union csr_vs1st_next_invalid_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vs1st_next_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_193 : 2; /* [15:14] */ + u32 vs1st_next_invalid_func_id : 12; /* [27:16] */ + u32 vs1st_next_invalid_cnt : 3; /* [30:28] */ + u32 vs1st_next_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vs1st_next_invalid_info_u; + +/* Define the union csr_vs1st_flag_invalid_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vs1st_flag_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_194 : 2; /* [15:14] */ + u32 vs1st_flag_invalid_func_id : 12; /* [27:16] */ + u32 vs1st_flag_invalid_cnt : 3; /* [30:28] */ + u32 vs1st_flag_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vs1st_flag_invalid_info_u; + +/* Define the union csr_vsleft_len_zero_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsleft_len_zero_glb_vqn : 14; /* [13:0] */ + u32 rsv_195 : 2; /* [15:14] */ + u32 vsleft_len_zero_func_id : 12; /* [27:16] */ + u32 vsleft_len_zero_cnt : 3; /* [30:28] */ + u32 vsleft_len_zero_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsleft_len_zero_info_u; + +/* Define the union csr_vsleft_next_invalid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsleft_next_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_196 : 2; /* [15:14] */ + u32 vsleft_next_invalid_func_id : 12; /* [27:16] */ + u32 vsleft_next_invalid_cnt : 3; /* [30:28] */ + u32 vsleft_next_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsleft_next_invalid_cnt_u; + +/* Define the union csr_vsleft_flag_invalid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsleft_flag_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_197 : 2; /* [15:14] */ + u32 vsleft_flag_invalid_func_id : 12; /* [27:16] */ + u32 vsleft_flag_invalid_cnt : 3; /* [30:28] */ + u32 vsleft_flag_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsleft_flag_invalid_cnt_u; + +/* Define the union csr_vsidesc_len_zero_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsidesc_len_zero_glb_vqn : 14; /* [13:0] */ + u32 rsv_198 : 2; /* [15:14] */ + u32 vsidesc_len_zero_func_id : 12; /* [27:16] */ + u32 vsidesc_len_zero_cnt : 3; /* [30:28] */ + u32 vsidesc_len_zero_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsidesc_len_zero_info_u; + +/* Define the union csr_vsidesc_next_invalid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsidesc_next_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_199 : 2; /* [15:14] */ + u32 vsidesc_next_invalid_func_id : 12; /* [27:16] */ + u32 vsidesc_next_invalid_cnt : 3; /* [30:28] */ + u32 vsidesc_next_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsidesc_next_invalid_cnt_u; + +/* Define the union csr_vsidesc_flag_invalid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vsidesc_flag_invalid_glb_vqn : 14; /* [13:0] */ + u32 rsv_200 : 2; /* [15:14] */ + u32 vsidesc_flag_invalid_func_id : 12; /* [27:16] */ + u32 vsidesc_flag_invalid_cnt : 3; /* [30:28] */ + u32 vsidesc_flag_invalid_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vsidesc_flag_invalid_cnt_u; + +/* Define the union csr_virtio_packed_dsc_invld_desc_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpckd_dfx_last_invld_dsc_vqn : 14; /* [13:0] */ + u32 rsv_201 : 2; /* [15:14] */ + u32 vpckd_dfx_last_invld_dsc_funcid : 12; /* [27:16] */ + u32 vpckd_dfx_invld_dsc_cnt : 3; /* [30:28] */ + u32 vpckd_dfx_invld_dsc_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_packed_dsc_invld_desc_1_u; + +/* Define the union csr_virtio_packed_dsc_invld_desc_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpckd_dfx_last_invld_dsc_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_packed_dsc_invld_desc_2_u; + +/* Define the union csr_virtio_packed_dsc_invld_idesc_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpckd_dfx_last_invld_idsc_vqn : 14; /* [13:0] */ + u32 rsv_202 : 2; /* [15:14] */ + u32 vpckd_dfx_last_invld_idsc_funcid : 12; /* [27:16] */ + u32 vpckd_dfx_invld_idsc_cnt : 3; /* [30:28] */ + u32 vpckd_dfx_invld_idsc_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_packed_dsc_invld_idesc_1_u; + +/* Define the union csr_virtio_packed_dsc_invld_idesc_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpckd_dfx_last_invld_idsc_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_packed_dsc_invld_idesc_2_u; + +/* Define the union csr_vpidesc_dfx_desc_len_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpidesc_dfx_desc_len_err_st : 26; /* [25:0] */ + u32 rsv_203 : 2; /* [27:26] */ + u32 vpidesc_dfx_desc_len_err_cnt : 3; /* [30:28] */ + u32 vpidesc_len_zero_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vpidesc_dfx_desc_len_err_u; + +/* Define the union csr_vpbfhd_dfx_host_desc_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpbfhd_dfx_host_desc_err_st : 26; /* [25:0] */ + u32 rsv_204 : 2; /* [27:26] */ + u32 vpbfhd_dfx_host_desc_err_cnt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vpbfhd_dfx_host_desc_err_cnt_u; + +/* Define the union csr_flr_timeout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_engine_flr_timeout_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_timeout_cfg_u; + +/* Define the union csr_flr_aeqe_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_engine_flr_dev_sts_template : 8; /* [7:0] */ + u32 virtio_engine_aeqe_credit_th : 8; /* [15:8] */ + u32 virtio_engine_flr_aeqe_credit_th : 3; /* [18:16] */ + u32 rsv_205 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_aeqe_cfg_u; + +/* Define the union csr_flr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_engine_flr_func_idx : 12; /* [11:0] */ + u32 virtio_engine_flr_ssb_done : 1; /* [12] */ + u32 virtio_engine_flr_dsb_done : 1; /* [13] */ + u32 virtio_engine_flr_proc_done : 1; /* [14] */ + u32 virtio_engine_flr_icsr_done : 1; /* [15] */ + u32 virtio_engine_flr_irqst_done : 1; /* [16] */ + u32 virtio_engine_flr_ecsr_done : 1; /* [17] */ + u32 virtio_engine_flr_ersp_done : 1; /* [18] */ + u32 virtio_engine_flr_proc_busy : 1; /* [19] */ + u32 virtio_engine_flr_ssb_busy : 1; /* [20] */ + u32 virtio_engine_flr_dsb_busy : 1; /* [21] */ + u32 virtio_engine_flr_icsr_busy : 1; /* [22] */ + u32 virtio_engine_flr_irqst_busy : 1; /* [23] */ + u32 virtio_engine_flr_ecsr_busy : 1; /* [24] */ + u32 virtio_engine_flr_ersp_busy : 1; /* [25] */ + u32 virtio_engine_flr_rst_adminq_en : 1; /* [26] */ + u32 virtio_engine_flr_type : 1; /* [27] */ + u32 virtio_engine_flr_rdy_en : 1; /* [28] */ + u32 rsv_206 : 1; /* [29] */ + u32 virtio_engine_flr_sts : 1; /* [30] */ + u32 virtio_engine_flr_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_status_u; + +/* Define the union csr_pre_flr_dfx_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pflr_dfx_api_cnt : 16; /* [15:0] */ + u32 rsv_207 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pre_flr_dfx_api_cnt_u; + +/* Define the union csr_pre_flr_dfx_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pflr_dfx_cur_st : 22; /* [21:0] */ + u32 rsv_208 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pre_flr_dfx_cur_st_u; + +/* Define the union csr_pre_flr_dfx_aeqe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pflr_dfx_aeqe_credit_uf_func_id : 12; /* [11:0] */ + u32 pflr_dfx_aeqe_credit_uf_flag : 1; /* [12] */ + u32 rsv_209 : 3; /* [15:13] */ + u32 pflr_dfx_aeqe_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pre_flr_dfx_aeqe_u; + +/* Define the union csr_flr_dfx_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flr_dfx_flr_cnt : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_dfx_api_cnt_u; + +/* Define the union csr_flr_dfx_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flr_dfx_cur_st : 27; /* [26:0] */ + u32 rsv_211 : 1; /* [27] */ + u32 flr_timeout_int_en : 1; /* [28] */ + u32 flr_done_with_err_int_en : 1; /* [29] */ + u32 flr_done_without_err_int_en : 1; /* [30] */ + u32 rsv_212 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_dfx_cur_st_u; + +/* Define the union csr_cache_flush_mem_index_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_flush_mem_index_cid : 10; /* [9:0] */ + u32 rsv_213 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_flush_mem_index_h_u; + +/* Define the union csr_cache_bank_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_bank_cfg : 4; /* [3:0] */ + u32 rsv_214 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_bank_cfg_u; + +/* Define the union csr_cache_flush_dfx_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_flush_dfx_api_cnt : 16; /* [15:0] */ + u32 rsv_215 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_flush_dfx_api_cnt_u; + +/* Define the union csr_cache_out_dfx_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_dfx_api_cnt : 16; /* [15:0] */ + u32 rsv_216 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_out_dfx_api_cnt_u; + +/* Define the union csr_cache_out_dfx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_dfx_err_cnt : 16; /* [15:0] */ + u32 rsv_217 : 15; /* [30:16] */ + u32 cache_out_err_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_out_dfx_err_cnt_u; + +/* Define the union csr_cache_out_dfx_cid_err_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_dfx_cid_err_st : 31; /* [30:0] */ + u32 rsv_218 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_out_dfx_cid_err_st_u; + +/* Define the union csr_cache_out_dfx_bank_cfg_err_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_dfx_bank_cfg_err_flag : 1; /* [0] */ + u32 rsv_219 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_out_dfx_bank_cfg_err_flag_u; + +/* Define the union csr_cache_out_dfx_mc_max_num_err_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_dfx_mc_max_num_err_flag : 1; /* [0] */ + u32 rsv_220 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_out_dfx_mc_max_num_err_flag_u; + +/* Define the union csr_cache_out_dfx_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_out_dfx_cur_st : 28; /* [27:0] */ + u32 rsv_221 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_out_dfx_cur_st_u; + +/* Define the union csr_cache_invld_dfx_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_invld_dfx_api_cnt : 16; /* [15:0] */ + u32 rsv_222 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_invld_dfx_api_cnt_u; + +/* Define the union csr_cache_invld_dfx_op_ext_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_invld_dfx_op_ext_err_cnt : 16; /* [15:0] */ + u32 rsv_223 : 15; /* [30:16] */ + u32 cache_invld_op_ext_err_int_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_invld_dfx_op_ext_err_cnt_u; + +/* Define the union csr_cache_invld_dfx_op_ext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_invld_dfx_op_ext_st : 27; /* [26:0] */ + u32 rsv_224 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_invld_dfx_op_ext_u; + +/* Define the union csr_cache_invld_dfx_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cache_invld_dfx_cur_st : 28; /* [27:0] */ + u32 rsv_225 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cache_invld_dfx_cur_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_rsvd0_u rsvd0; /* 0 */ + volatile csr_rsvd1_u rsvd1; /* 4 */ + volatile csr_rsvd2_u rsvd2; /* 8 */ + volatile csr_rsvd3_u rsvd3; /* C */ + volatile csr_int_vector_u int_vector; /* 10 */ + volatile csr_int_status_u int_status; /* 14 */ + volatile csr_int_en_u int_en; /* 18 */ + volatile csr_int0_sticky_u int0_sticky; /* 20 */ + volatile csr_int1_sticky_u int1_sticky; /* 24 */ + volatile csr_int2_sticky_u int2_sticky; /* 28 */ + volatile csr_int3_sticky_u int3_sticky; /* 2C */ + volatile csr_int4_sticky_u int4_sticky; /* 30 */ + volatile csr_int5_sticky_u int5_sticky; /* 34 */ + volatile csr_int6_sticky_u int6_sticky; /* 38 */ + volatile csr_int7_sticky_u int7_sticky; /* 3C */ + volatile csr_int8_sticky_u int8_sticky; /* 40 */ + volatile csr_int9_sticky_u int9_sticky; /* 44 */ + volatile csr_int10_sticky_u int10_sticky; /* 48 */ + volatile csr_int11_sticky_u int11_sticky; /* 4C */ + volatile csr_int12_sticky_u int12_sticky; /* 50 */ + volatile csr_int13_sticky_u int13_sticky; /* 54 */ + volatile csr_int14_sticky_u int14_sticky; /* 58 */ + volatile csr_int15_sticky_u int15_sticky; /* 5C */ + volatile csr_common_mem_init_u common_mem_init; /* 60 */ + volatile csr_common_mem_init_status_u common_mem_init_status; /* 64 */ + volatile csr_iif_irsp_mem_h_ecc_cfg_status_u iif_irsp_mem_h_ecc_cfg_status; /* 70 */ + volatile csr_iif_irsp_mem_l_ecc_cfg_status_u iif_irsp_mem_l_ecc_cfg_status; /* 74 */ + volatile csr_ersp_mem_h_ecc_cfg_status_u ersp_mem_h_ecc_cfg_status; /* 78 */ + volatile csr_ersp_mem_l_ecc_cfg_status_u ersp_mem_l_ecc_cfg_status; /* 7C */ + volatile csr_erqst_fifo_ecc_cfg_status_u erqst_fifo_ecc_cfg_status; /* 80 */ + volatile csr_ecsr_fifo_ecc_cfg_status_u ecsr_fifo_ecc_cfg_status; /* 84 */ + volatile csr_ssb_mem_ecc_cfg_status_u ssb_mem_ecc_cfg_status; /* 88 */ + volatile csr_dsb_mem_ecc_cfg_status_u dsb_mem_ecc_cfg_status; /* 8C */ + volatile csr_host_id_table_mem_ecc_cfg_status_u host_id_table_mem_ecc_cfg_status; /* 90 */ + volatile csr_dev_attri_table_mem_ecc_cfg_status_u dev_attri_table_mem_ecc_cfg_status; /* 94 */ + volatile csr_tpram_wr_ctrl_u tpram_wr_ctrl; /* A0 */ + volatile csr_tpram_wr_wen_data_31_0_u tpram_wr_wen_data_31_0; /* B0 */ + volatile csr_tpram_wr_wen_data_63_32_u tpram_wr_wen_data_63_32; /* B4 */ + volatile csr_tpram_wr_wen_data_95_64_u tpram_wr_wen_data_95_64; /* B8 */ + volatile csr_tpram_wr_wen_data_127_96_u tpram_wr_wen_data_127_96; /* BC */ + volatile csr_tpram_wr_wen_data_159_128_u tpram_wr_wen_data_159_128; /* C0 */ + volatile csr_tpram_wr_wen_data_191_160_u tpram_wr_wen_data_191_160; /* C4 */ + volatile csr_tpram_wr_wen_data_223_192_u tpram_wr_wen_data_223_192; /* C8 */ + volatile csr_tpram_wr_wen_data_255_224_u tpram_wr_wen_data_255_224; /* CC */ + volatile csr_tpram_wr_wen_data_287_256_u tpram_wr_wen_data_287_256; /* D0 */ + volatile csr_tpram_wr_wen_data_319_288_u tpram_wr_wen_data_319_288; /* D4 */ + volatile csr_tpram_wr_wen_data_335_320_u tpram_wr_wen_data_335_320; /* D8 */ + volatile csr_tpram_wr_ren_data_31_0_u tpram_wr_ren_data_31_0; /* E0 */ + volatile csr_tpram_wr_ren_data_63_32_u tpram_wr_ren_data_63_32; /* E4 */ + volatile csr_tpram_wr_ren_data_95_64_u tpram_wr_ren_data_95_64; /* E8 */ + volatile csr_tpram_wr_ren_data_127_96_u tpram_wr_ren_data_127_96; /* EC */ + volatile csr_tpram_wr_ren_data_159_128_u tpram_wr_ren_data_159_128; /* F0 */ + volatile csr_tpram_wr_ren_data_191_160_u tpram_wr_ren_data_191_160; /* F4 */ + volatile csr_tpram_wr_ren_data_223_192_u tpram_wr_ren_data_223_192; /* F8 */ + volatile csr_tpram_wr_ren_data_255_224_u tpram_wr_ren_data_255_224; /* FC */ + volatile csr_tpram_wr_ren_data_287_256_u tpram_wr_ren_data_287_256; /* 100 */ + volatile csr_tpram_wr_ren_data_319_288_u tpram_wr_ren_data_319_288; /* 104 */ + volatile csr_tpram_wr_ren_data_351_320_u tpram_wr_ren_data_351_320; /* 108 */ + volatile csr_tpram_wr_ren_data_383_352_u tpram_wr_ren_data_383_352; /* 10C */ + volatile csr_tpram_wr_ren_data_415_384_u tpram_wr_ren_data_415_384; /* 110 */ + volatile csr_tpram_wr_ren_data_447_416_u tpram_wr_ren_data_447_416; /* 114 */ + volatile csr_tpram_wr_ren_data_479_448_u tpram_wr_ren_data_479_448; /* 118 */ + volatile csr_tpram_wr_ren_data_511_480_u tpram_wr_ren_data_511_480; /* 11C */ + volatile csr_tpram_wr_ren_data_543_512_u tpram_wr_ren_data_543_512; /* 120 */ + volatile csr_tpram_wr_ren_data_575_544_u tpram_wr_ren_data_575_544; /* 124 */ + volatile csr_tpram_wr_ren_data_607_576_u tpram_wr_ren_data_607_576; /* 128 */ + volatile csr_tpram_wr_ren_data_639_608_u tpram_wr_ren_data_639_608; /* 12C */ + volatile csr_tpram_wr_ren_data_671_640_u tpram_wr_ren_data_671_640; /* 130 */ + volatile csr_tpram_wr_ren_data_703_672_u tpram_wr_ren_data_703_672; /* 134 */ + volatile csr_tpram_wr_ren_data_735_704_u tpram_wr_ren_data_735_704; /* 138 */ + volatile csr_tpram_wr_ren_data_767_736_u tpram_wr_ren_data_767_736; /* 13C */ + volatile csr_tpram_wr_ren_data_773_768_u tpram_wr_ren_data_773_768; /* 140 */ + volatile csr_load_balance_cfg_u load_balance_cfg; /* 150 */ + volatile csr_flex_q_cfg_u flex_q_cfg; /* 154 */ + volatile csr_vq_cntx_size_u vq_cntx_size; /* 200 */ + volatile csr_virtio_region_off_cfg_u virtio_region_off_cfg; /* 204 */ + volatile csr_virtio_loc_sgl_size_cfg_u virtio_loc_sgl_size_cfg; /* 208 */ + volatile csr_virtio_loc_idesc_size_cfg_u virtio_loc_idesc_size_cfg; /* 20C */ + volatile csr_virtio_dma_wait_max_cfg_u virtio_dma_wait_max_cfg; /* 210 */ + volatile csr_virtio_prefetch_th_u virtio_prefetch_th; /* 214 */ + volatile csr_virtio_max_outstand_th_u virtio_max_outstand_th; /* 218 */ + volatile csr_virtio_split_chain_speculate_th_cfg_u virtio_split_chain_speculate_th_cfg; /* 21C */ + volatile csr_virtio_sqe_dma_template_dw0_u virtio_sqe_dma_template_dw0; /* 280 */ + volatile csr_virtio_sqe_dma_template_dw1_u virtio_sqe_dma_template_dw1; /* 284 */ + volatile csr_virtio_sqe_dma_template_dw2_u virtio_sqe_dma_template_dw2; /* 288 */ + volatile csr_virtio_sqe_dma_template_dw3_u virtio_sqe_dma_template_dw3; /* 28C */ + volatile csr_virtio_rqe_dma_template_dw0_u virtio_rqe_dma_template_dw0; /* 290 */ + volatile csr_virtio_rqe_dma_template_dw1_u virtio_rqe_dma_template_dw1; /* 294 */ + volatile csr_virtio_rqe_dma_template_dw2_u virtio_rqe_dma_template_dw2; /* 298 */ + volatile csr_virtio_rqe_dma_template_dw3_u virtio_rqe_dma_template_dw3; /* 29C */ + volatile csr_nvme_qp_cntx_cfg0_u nvme_qp_cntx_cfg0; /* 300 */ + volatile csr_nvme_qp_cntx_cfg1_u nvme_qp_cntx_cfg1; /* 304 */ + volatile csr_virtio_engine_nvme_cntx_offset_u virtio_engine_nvme_cntx_offset; /* 308 */ + volatile csr_virtio_engine_virtio_cntx_offset_u virtio_engine_virtio_cntx_offset; /* 30C */ + volatile csr_nvme_dma_cfg_u nvme_dma_cfg; /* 310 */ + volatile csr_nvme_dma_template_dw0_u nvme_dma_template_dw0; /* 314 */ + volatile csr_nvme_dma_template_dw1_u nvme_dma_template_dw1; /* 318 */ + volatile csr_nvme_dma_template_dw2_u nvme_dma_template_dw2; /* 31C */ + volatile csr_irqst_credit_status_u irqst_credit_status; /* 400 */ + volatile csr_irqst_fifo_status_u irqst_fifo_status; /* 404 */ + volatile csr_irqst_statistic_api_u irqst_statistic_api; /* 408 */ + volatile csr_irqst_api_with_a_cnt_u irqst_api_with_a_cnt; /* 40C */ + volatile csr_irqst_api_without_a_cnt_u irqst_api_without_a_cnt; /* 410 */ + volatile csr_irqst_api_invalid_status_u irqst_api_invalid_status; /* 414 */ + volatile csr_irqst_int_en_cfg_u irqst_int_en_cfg; /* 418 */ + volatile csr_irsp_credit_status_u irsp_credit_status; /* 420 */ + volatile csr_irsp_fifo_cfg_status_u irsp_fifo_cfg_status; /* 424 */ + volatile csr_irsp_api_statistic_u irsp_api_statistic; /* 428 */ + volatile csr_irsp_invalid_flit_u irsp_invalid_flit; /* 42C */ + volatile csr_irsp_int_en_cfg_u irsp_int_en_cfg; /* 430 */ + volatile csr_icsr_credit_status_u icsr_credit_status; /* 440 */ + volatile csr_icsr_fifo_status_u icsr_fifo_status; /* 444 */ + volatile csr_icsr_api_with_a_cnt_u icsr_api_with_a_cnt; /* 448 */ + volatile csr_icsr_api_without_a_cnt_u icsr_api_without_a_cnt; /* 44C */ + volatile csr_icsr_invalid_api_u icsr_invalid_api; /* 450 */ + volatile csr_icsr_cpath_timeout_cfg_u icsr_cpath_timeout_cfg; /* 454 */ + volatile csr_icsr_cpath_timeout_drop_api_cnt_u icsr_cpath_timeout_drop_api_cnt; /* 458 */ + volatile csr_icsr_int_en_cfg_u icsr_int_en_cfg; /* 45C */ + volatile csr_isch_weight_cfg_u isch_weight_cfg; /* 460 */ + volatile csr_erqst_credit_status_u erqst_credit_status; /* 470 */ + volatile csr_erqst_dma_template_u erqst_dma_template; /* 474 */ + volatile csr_erqst_api_cnt_u erqst_api_cnt; /* 478 */ + volatile csr_erqst_fifo_status_u erqst_fifo_status; /* 47C */ + volatile csr_ersp_credit_status_u ersp_credit_status; /* 490 */ + volatile csr_ersp_fifo_status_u ersp_fifo_status; /* 494 */ + volatile csr_ersp_flit_cnt_u ersp_flit_cnt; /* 498 */ + volatile csr_ersp_api_cnt_u ersp_api_cnt; /* 49C */ + volatile csr_ecsr_credit_status_u ecsr_credit_status; /* 4B0 */ + volatile csr_ecsr_fifo_cfg_status_u ecsr_fifo_cfg_status; /* 4B4 */ + volatile csr_ecsr_api_cnt_u ecsr_api_cnt; /* 4B8 */ + volatile csr_sif_smlc_outstanding_thread_scan_u sif_smlc_outstanding_thread_scan; /* 4BC */ + volatile csr_sif_smlc_delay_cfg_u sif_smlc_delay_cfg; /* 4C0 */ + volatile csr_sif_smlc_delay_timer_u sif_smlc_delay_timer; /* 4C4 */ + volatile csr_sif_smlc_delay_min_u sif_smlc_delay_min; /* 4C8 */ + volatile csr_sif_smlc_delay_max_u sif_smlc_delay_max; /* 4CC */ + volatile csr_sif_fun_mem_mode_baddr_u sif_fun_mem_mode_baddr; /* 4D0 */ + volatile csr_sif_vq_mem_mode_baddr_cfg_u sif_vq_mem_mode_baddr_cfg; /* 4D4 */ + volatile csr_sif_instance_id_cfg_u sif_instance_id_cfg; /* 4D8 */ + volatile csr_sif_smlc_if_cfg_0_u sif_smlc_if_cfg_0; /* 4DC */ + volatile csr_sif_smlc_if_cfg_1_u sif_smlc_if_cfg_1; /* 4E0 */ + volatile csr_sif_smlc_if_cfg_2_u sif_smlc_if_cfg_2; /* 4E4 */ + volatile csr_sif_smlc_if_cfg_3_u sif_smlc_if_cfg_3; /* 4E8 */ + volatile csr_host_ppf_cfg_0_u host_ppf_cfg_0; /* 4EC */ + volatile csr_host_ppf_cfg_1_u host_ppf_cfg_1; /* 4F0 */ + volatile csr_sif_smlc_thread_timeout_status_0_u sif_smlc_thread_timeout_status_0; /* 4F4 */ + volatile csr_sif_smlc_thread_timeout_status_1_u sif_smlc_thread_timeout_status_1; /* 4F8 */ + volatile csr_sif_int_en_cfg_u sif_int_en_cfg; /* 4FC */ + volatile csr_stm_share_thread_max_u stm_share_thread_max; /* 500 */ + volatile csr_stm_channel_thread_th_cfg_u stm_channel_thread_th_cfg; /* 504 */ + volatile csr_stm_share_thread_status_u stm_share_thread_status; /* 508 */ + volatile csr_stm_channel_thread_status_u stm_channel_thread_status; /* 50C */ + volatile csr_stm_fifo0_status_u stm_fifo0_status; /* 510 */ + volatile csr_stm_fifo1_status_u stm_fifo1_status; /* 514 */ + volatile csr_dtm_tag_alempty_th_u dtm_tag_alempty_th; /* 51C */ + volatile csr_dtm_tag_th_cfg_u dtm_tag_th_cfg; /* 520 */ + volatile csr_dtm_tag_status_u dtm_tag_status; /* 524 */ + volatile csr_dtm_dma_outstanding_tag_scan_u dtm_dma_outstanding_tag_scan; /* 528 */ + volatile csr_dtm_dma_delay_cfg_u dtm_dma_delay_cfg; /* 52C */ + volatile csr_dtm_dma_delay_timer_u dtm_dma_delay_timer; /* 530 */ + volatile csr_dtm_dma_delay_min_u dtm_dma_delay_min; /* 534 */ + volatile csr_dtm_dma_delay_max_u dtm_dma_delay_max; /* 538 */ + volatile csr_dtm_dma_tag_timeout_cfg_u dtm_dma_tag_timeout_cfg; /* 53C */ + volatile csr_dtm_dma_tag_timeout_status_0_u dtm_dma_tag_timeout_status_0; /* 540 */ + volatile csr_dtm_dma_tag_timeout_status_1_u dtm_dma_tag_timeout_status_1; /* 544 */ + volatile csr_dtm_dma_tag_timeout_status_2_u dtm_dma_tag_timeout_status_2; /* 548 */ + volatile csr_dtm_dma_tag_timeout_status_3_u dtm_dma_tag_timeout_status_3; /* 54C */ + volatile csr_nvme_cpath_total_api_cnt_u nvme_cpath_total_api_cnt; /* 800 */ + volatile csr_nvme_cpath_invalid_api_cnt_u nvme_cpath_invalid_api_cnt; /* 804 */ + volatile csr_nvme_cpath_last_invalid_load_operation_u nvme_cpath_last_invalid_load_operation; /* 808 */ + volatile csr_nvme_cpath_last_invalid_store_operation_1_u nvme_cpath_last_invalid_store_operation_1; /* 80C */ + volatile csr_nvme_cpath_last_invalid_store_operation_2_u nvme_cpath_last_invalid_store_operation_2; /* 810 */ + volatile csr_nvme_cpath_last_invalid_store_operation_3_u nvme_cpath_last_invalid_store_operation_3; /* 814 */ + volatile csr_nvme_cpath_last_valid_load_operation_u nvme_cpath_last_valid_load_operation; /* 818 */ + volatile csr_nvme_cpath_last_valid_store_operation_1_u nvme_cpath_last_valid_store_operation_1; /* 81C */ + volatile csr_nvme_cpath_last_valid_store_operation_2_u nvme_cpath_last_valid_store_operation_2; /* 820 */ + volatile csr_nvme_cpath_last_valid_store_operation_3_u nvme_cpath_last_valid_store_operation_3; /* 824 */ + volatile csr_nvme_cpath_int_en_u nvme_cpath_int_en; /* 828 */ + volatile csr_nvme_dpath_load_api_cnt_u nvme_dpath_load_api_cnt; /* 840 */ + volatile csr_nvme_dpath_store_api_cnt_u nvme_dpath_store_api_cnt; /* 844 */ + volatile csr_virtio_dfx_func_id_cfg_u virtio_dfx_func_id_cfg; /* 860 */ + volatile csr_virtio_dfx_vqn_cfg_u virtio_dfx_vqn_cfg; /* 864 */ + volatile csr_virtio_dpath_total_api_cnt_u virtio_dpath_total_api_cnt; /* 880 */ + volatile csr_virtio_dpath_abnormal_api_cnt_u virtio_dpath_abnormal_api_cnt; /* 884 */ + volatile csr_virtio_dpath_invld_api_cnt_u virtio_dpath_invld_api_cnt; /* 8B0 */ + volatile csr_virtio_dpath_last_valid_load_operation_1_u virtio_dpath_last_valid_load_operation_1; /* 888 */ + volatile csr_virtio_dpath_last_valid_load_operation_2_u virtio_dpath_last_valid_load_operation_2; /* 88C */ + volatile csr_virtio_dpath_last_valid_store_operation_1_u virtio_dpath_last_valid_store_operation_1; /* 890 */ + volatile csr_virtio_dpath_last_valid_store_operation_2_u virtio_dpath_last_valid_store_operation_2; /* 894 */ + volatile csr_virtio_dpath_last_valid_store_operation_3_u virtio_dpath_last_valid_store_operation_3; /* 898 */ + volatile csr_virtio_dpath_last_invalid_load_operation_1_u virtio_dpath_last_invalid_load_operation_1; /* 89C */ + volatile csr_virtio_dpath_last_invalid_load_operation_2_u virtio_dpath_last_invalid_load_operation_2; /* 8A0 */ + volatile csr_virtio_dpath_last_invalid_store_operation_1_u virtio_dpath_last_invalid_store_operation_1; /* 8A4 */ + volatile csr_virtio_dpath_last_invalid_store_operation_2_u virtio_dpath_last_invalid_store_operation_2; /* 8A8 */ + volatile csr_virtio_dpath_last_invalid_store_operation_3_u virtio_dpath_last_invalid_store_operation_3; /* 8AC */ + volatile csr_virtio_dpath_int_en_u virtio_dpath_int_en; /* 8B4 */ + volatile csr_virtio_cpath_total_api_cnt_u virtio_cpath_total_api_cnt; /* 8C0 */ + volatile csr_virtio_cpath_abnormal_api_cnt_u virtio_cpath_abnormal_api_cnt; /* 8C4 */ + volatile csr_virtio_cpath_invld_api_cnt_u virtio_cpath_invld_api_cnt; /* 8C8 */ + volatile csr_virtio_cpath_flr_op_api_cnt_u virtio_cpath_flr_op_api_cnt; /* 8F8 */ + volatile csr_virtio_cpath_last_valid_load_operation_1_u virtio_cpath_last_valid_load_operation_1; /* 8D0 */ + volatile csr_virtio_cpath_last_valid_load_operation_2_u virtio_cpath_last_valid_load_operation_2; /* 8D4 */ + volatile csr_virtio_cpath_last_valid_store_operation_1_u virtio_cpath_last_valid_store_operation_1; /* 8D8 */ + volatile csr_virtio_cpath_last_valid_store_operation_2_u virtio_cpath_last_valid_store_operation_2; /* 8DC */ + volatile csr_virtio_cpath_last_valid_store_operation_3_u virtio_cpath_last_valid_store_operation_3; /* 8E0 */ + volatile csr_virtio_cpath_last_invalid_load_operation_1_u virtio_cpath_last_invalid_load_operation_1; /* 8E4 */ + volatile csr_virtio_cpath_last_invalid_load_operation_2_u virtio_cpath_last_invalid_load_operation_2; /* 8E8 */ + volatile csr_virtio_cpath_last_invalid_store_operation_1_u virtio_cpath_last_invalid_store_operation_1; /* 8EC */ + volatile csr_virtio_cpath_last_invalid_store_operation_2_u virtio_cpath_last_invalid_store_operation_2; /* 8F0 */ + volatile csr_virtio_cpath_last_invalid_store_operation_3_u virtio_cpath_last_invalid_store_operation_3; /* 8F4 */ + volatile csr_virtio_cpath_int_en_u virtio_cpath_int_en; /* 8FC */ + volatile csr_vdb_api_cnt_u vdb_api_cnt; /* 900 */ + volatile csr_vsdb_pi_invalid_info_u vsdb_pi_invalid_info; /* 910 */ + volatile csr_vsavidx_pi_invalid_info_u vsavidx_pi_invalid_info; /* 920 */ + volatile csr_vsavring_idx_invalid_info_u vsavring_idx_invalid_info; /* 930 */ + volatile csr_vsavring_idx_invalid_dat_u vsavring_idx_invalid_dat; /* 934 */ + volatile csr_vs1st_len_zero_info_u vs1st_len_zero_info; /* 940 */ + volatile csr_vs1st_next_invalid_info_u vs1st_next_invalid_info; /* 944 */ + volatile csr_vs1st_flag_invalid_info_u vs1st_flag_invalid_info; /* 948 */ + volatile csr_vsleft_len_zero_info_u vsleft_len_zero_info; /* 960 */ + volatile csr_vsleft_next_invalid_cnt_u vsleft_next_invalid_cnt; /* 964 */ + volatile csr_vsleft_flag_invalid_cnt_u vsleft_flag_invalid_cnt; /* 968 */ + volatile csr_vsidesc_len_zero_info_u vsidesc_len_zero_info; /* 980 */ + volatile csr_vsidesc_next_invalid_cnt_u vsidesc_next_invalid_cnt; /* 984 */ + volatile csr_vsidesc_flag_invalid_cnt_u vsidesc_flag_invalid_cnt; /* 988 */ + volatile csr_virtio_packed_dsc_invld_desc_1_u virtio_packed_dsc_invld_desc_1; /* A00 */ + volatile csr_virtio_packed_dsc_invld_desc_2_u virtio_packed_dsc_invld_desc_2; /* A04 */ + volatile csr_virtio_packed_dsc_invld_idesc_1_u virtio_packed_dsc_invld_idesc_1; /* A08 */ + volatile csr_virtio_packed_dsc_invld_idesc_2_u virtio_packed_dsc_invld_idesc_2; /* A0C */ + volatile csr_vpidesc_dfx_desc_len_err_u vpidesc_dfx_desc_len_err; /* A84 */ + volatile csr_vpbfhd_dfx_host_desc_err_cnt_u vpbfhd_dfx_host_desc_err_cnt; /* AC0 */ + volatile csr_flr_timeout_cfg_u flr_timeout_cfg; /* E00 */ + volatile csr_flr_aeqe_cfg_u flr_aeqe_cfg; /* E04 */ + volatile csr_flr_status_u flr_status; /* E08 */ + volatile csr_pre_flr_dfx_api_cnt_u pre_flr_dfx_api_cnt; /* E10 */ + volatile csr_pre_flr_dfx_cur_st_u pre_flr_dfx_cur_st; /* E14 */ + volatile csr_pre_flr_dfx_aeqe_u pre_flr_dfx_aeqe; /* E18 */ + volatile csr_flr_dfx_api_cnt_u flr_dfx_api_cnt; /* E30 */ + volatile csr_flr_dfx_cur_st_u flr_dfx_cur_st; /* E34 */ + volatile csr_cache_flush_mem_index_h_u cache_flush_mem_index_h; /* E80 */ + volatile csr_cache_bank_cfg_u cache_bank_cfg; /* E84 */ + volatile csr_cache_flush_dfx_api_cnt_u cache_flush_dfx_api_cnt; /* E88 */ + volatile csr_cache_out_dfx_api_cnt_u cache_out_dfx_api_cnt; /* E8C */ + volatile csr_cache_out_dfx_err_cnt_u cache_out_dfx_err_cnt; /* E90 */ + volatile csr_cache_out_dfx_cid_err_st_u cache_out_dfx_cid_err_st; /* E94 */ + volatile csr_cache_out_dfx_bank_cfg_err_flag_u cache_out_dfx_bank_cfg_err_flag; /* E98 */ + volatile csr_cache_out_dfx_mc_max_num_err_flag_u cache_out_dfx_mc_max_num_err_flag; /* E9C */ + volatile csr_cache_out_dfx_cur_st_u cache_out_dfx_cur_st; /* EA0 */ + volatile csr_cache_invld_dfx_api_cnt_u cache_invld_dfx_api_cnt; /* EB0 */ + volatile csr_cache_invld_dfx_op_ext_err_cnt_u cache_invld_dfx_op_ext_err_cnt; /* EB4 */ + volatile csr_cache_invld_dfx_op_ext_u cache_invld_dfx_op_ext; /* EB8 */ + volatile csr_cache_invld_dfx_cur_st_u cache_invld_dfx_cur_st; /* EBC */ +} S_virtio_csr_REGS_TYPE; + +/* Declare the struct pointor of the module virtio_csr */ +extern volatile S_virtio_csr_REGS_TYPE *gopvirtio_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetRSVD0_engn_rsvd0(unsigned int uengn_rsvd0); +int iSetRSVD1_engn_rsvd1(unsigned int uengn_rsvd1); +int iSetRSVD2_engn_rsvd2(unsigned int uengn_rsvd2); +int iSetRSVD3_engn_rsvd3(unsigned int uengn_rsvd3); +int iSetINT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetINT_VECTOR_enable(unsigned int uenable); +int iSetINT_VECTOR_int_issue(unsigned int uint_issue); +int iSetINT_STATUS_int_data(unsigned int uint_data); +int iSetINT_STATUS_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetINT_EN_int_en(unsigned int uint_en); +int iSetINT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetINT0_STICKY_int0_rawstatus(unsigned int uint0_rawstatus); +int iSetINT0_STICKY_int0_insert(unsigned int uint0_insert); +int iSetINT0_STICKY_int0_sticky(unsigned int uint0_sticky); +int iSetINT1_STICKY_int1_rawstatus(unsigned int uint1_rawstatus); +int iSetINT1_STICKY_int1_insert(unsigned int uint1_insert); +int iSetINT1_STICKY_int1_sticky(unsigned int uint1_sticky); +int iSetINT2_STICKY_int2_rawstatus(unsigned int uint2_rawstatus); +int iSetINT2_STICKY_int2_insert(unsigned int uint2_insert); +int iSetINT2_STICKY_int2_sticky(unsigned int uint2_sticky); +int iSetINT3_STICKY_int3_rawstatus(unsigned int uint3_rawstatus); +int iSetINT3_STICKY_int3_insert(unsigned int uint3_insert); +int iSetINT3_STICKY_int3_sticky(unsigned int uint3_sticky); +int iSetINT4_STICKY_int4_rawstatus(unsigned int uint4_rawstatus); +int iSetINT4_STICKY_int4_insert(unsigned int uint4_insert); +int iSetINT4_STICKY_int4_sticky(unsigned int uint4_sticky); +int iSetINT5_STICKY_int5_rawstatus(unsigned int uint5_rawstatus); +int iSetINT5_STICKY_int5_insert(unsigned int uint5_insert); +int iSetINT5_STICKY_int5_sticky(unsigned int uint5_sticky); +int iSetINT6_STICKY_int6_rawstatus(unsigned int uint6_rawstatus); +int iSetINT6_STICKY_int6_insert(unsigned int uint6_insert); +int iSetINT6_STICKY_int6_sticky(unsigned int uint6_sticky); +int iSetINT7_STICKY_int7_rawstatus(unsigned int uint7_rawstatus); +int iSetINT7_STICKY_int7_insert(unsigned int uint7_insert); +int iSetINT7_STICKY_int7_sticky(unsigned int uint7_sticky); +int iSetINT8_STICKY_int8_rawstatus(unsigned int uint8_rawstatus); +int iSetINT8_STICKY_int8_insert(unsigned int uint8_insert); +int iSetINT8_STICKY_int8_sticky(unsigned int uint8_sticky); +int iSetINT9_STICKY_int9_rawstatus(unsigned int uint9_rawstatus); +int iSetINT9_STICKY_int9_insert(unsigned int uint9_insert); +int iSetINT9_STICKY_int9_sticky(unsigned int uint9_sticky); +int iSetINT10_STICKY_int10_rawstatus(unsigned int uint10_rawstatus); +int iSetINT10_STICKY_int10_insert(unsigned int uint10_insert); +int iSetINT10_STICKY_int10_sticky(unsigned int uint10_sticky); +int iSetINT11_STICKY_int11_rawstatus(unsigned int uint11_rawstatus); +int iSetINT11_STICKY_int11_insert(unsigned int uint11_insert); +int iSetINT11_STICKY_int11_sticky(unsigned int uint11_sticky); +int iSetINT12_STICKY_int12_rawstatus(unsigned int uint12_rawstatus); +int iSetINT12_STICKY_int12_insert(unsigned int uint12_insert); +int iSetINT12_STICKY_int12_sticky(unsigned int uint12_sticky); +int iSetINT13_STICKY_int13_rawstatus(unsigned int uint13_rawstatus); +int iSetINT13_STICKY_int13_insert(unsigned int uint13_insert); +int iSetINT13_STICKY_int13_sticky(unsigned int uint13_sticky); +int iSetINT14_STICKY_int14_rawstatus(unsigned int uint14_rawstatus); +int iSetINT14_STICKY_int14_insert(unsigned int uint14_insert); +int iSetINT14_STICKY_int14_sticky(unsigned int uint14_sticky); +int iSetINT15_STICKY_int15_rawstatus(unsigned int uint15_rawstatus); +int iSetINT15_STICKY_int15_insert(unsigned int uint15_insert); +int iSetINT15_STICKY_int15_sticky(unsigned int uint15_sticky); +int iSetCOMMON_MEM_INIT_host_id_table_init_start(unsigned int uhost_id_table_init_start); +int iSetCOMMON_MEM_INIT_dtm_bitmap_init_start(unsigned int udtm_bitmap_init_start); +int iSetCOMMON_MEM_INIT_stm_bitmap_init_start(unsigned int ustm_bitmap_init_start); +int iSetCOMMON_MEM_INIT_device_attri_table_init_start(unsigned int udevice_attri_table_init_start); +int iSetCOMMON_MEM_INIT_smlc_mem_init_start(unsigned int usmlc_mem_init_start); +int iSetCOMMON_MEM_INIT_STATUS_host_id_table_init_done(unsigned int uhost_id_table_init_done); +int iSetCOMMON_MEM_INIT_STATUS_dtm_bitmap_init_done(unsigned int udtm_bitmap_init_done); +int iSetCOMMON_MEM_INIT_STATUS_stm_bitmap_init_done(unsigned int ustm_bitmap_init_done); +int iSetCOMMON_MEM_INIT_STATUS_device_attri_table_init_done(unsigned int udevice_attri_table_init_done); +int iSetCOMMON_MEM_INIT_STATUS_host_id_table_init_busy(unsigned int uhost_id_table_init_busy); +int iSetCOMMON_MEM_INIT_STATUS_dtm_bitmap_init_busy(unsigned int udtm_bitmap_init_busy); +int iSetCOMMON_MEM_INIT_STATUS_stm_bitmap_init_busy(unsigned int ustm_bitmap_init_busy); +int iSetCOMMON_MEM_INIT_STATUS_device_attri_table_init_busy(unsigned int udevice_attri_table_init_busy); +int iSetIIF_IRSP_MEM_H_ECC_CFG_STATUS_irsp_mem_h_ecc_ucrt_addr(unsigned int uirsp_mem_h_ecc_ucrt_addr); +int iSetIIF_IRSP_MEM_H_ECC_CFG_STATUS_irsp_mem_h_ecc_crt_err_cnt(unsigned int uirsp_mem_h_ecc_crt_err_cnt); +int iSetIIF_IRSP_MEM_H_ECC_CFG_STATUS_irsp_mem_h_ecc_inj_ack(unsigned int uirsp_mem_h_ecc_inj_ack); +int iSetIIF_IRSP_MEM_H_ECC_CFG_STATUS_irsp_mem_h_ecc_inj_req(unsigned int uirsp_mem_h_ecc_inj_req); +int iSetIIF_IRSP_MEM_H_ECC_CFG_STATUS_irsp_mem_h_ecc_bypass(unsigned int uirsp_mem_h_ecc_bypass); +int iSetIIF_IRSP_MEM_L_ECC_CFG_STATUS_irsp_mem_l_ecc_ucrt_addr(unsigned int uirsp_mem_l_ecc_ucrt_addr); +int iSetIIF_IRSP_MEM_L_ECC_CFG_STATUS_irsp_mem_l_ecc_crt_err_cnt(unsigned int uirsp_mem_l_ecc_crt_err_cnt); +int iSetIIF_IRSP_MEM_L_ECC_CFG_STATUS_irsp_mem_l_ecc_inj_ack(unsigned int uirsp_mem_l_ecc_inj_ack); +int iSetIIF_IRSP_MEM_L_ECC_CFG_STATUS_irsp_mem_l_ecc_inj_req(unsigned int uirsp_mem_l_ecc_inj_req); +int iSetIIF_IRSP_MEM_L_ECC_CFG_STATUS_irsp_mem_l_ecc_bypass(unsigned int uirsp_mem_l_ecc_bypass); +int iSetERSP_MEM_H_ECC_CFG_STATUS_ersp_mem_h_ecc_ucrt_addr(unsigned int uersp_mem_h_ecc_ucrt_addr); +int iSetERSP_MEM_H_ECC_CFG_STATUS_ersp_mem_h_ecc_crt_err_cnt(unsigned int uersp_mem_h_ecc_crt_err_cnt); +int iSetERSP_MEM_H_ECC_CFG_STATUS_ersp_mem_h_ecc_inj_ack(unsigned int uersp_mem_h_ecc_inj_ack); +int iSetERSP_MEM_H_ECC_CFG_STATUS_ersp_mem_h_ecc_inj_req(unsigned int uersp_mem_h_ecc_inj_req); +int iSetERSP_MEM_H_ECC_CFG_STATUS_ersp_mem_h_ecc_bypass(unsigned int uersp_mem_h_ecc_bypass); +int iSetERSP_MEM_L_ECC_CFG_STATUS_ersp_mem_l_ecc_ucrt_addr(unsigned int uersp_mem_l_ecc_ucrt_addr); +int iSetERSP_MEM_L_ECC_CFG_STATUS_ersp_mem_l_ecc_crt_err_cnt(unsigned int uersp_mem_l_ecc_crt_err_cnt); +int iSetERSP_MEM_L_ECC_CFG_STATUS_ersp_mem_l_ecc_inj_ack(unsigned int uersp_mem_l_ecc_inj_ack); +int iSetERSP_MEM_L_ECC_CFG_STATUS_ersp_mem_l_ecc_inj_req(unsigned int uersp_mem_l_ecc_inj_req); +int iSetERSP_MEM_L_ECC_CFG_STATUS_ersp_mem_l_ecc_bypass(unsigned int uersp_mem_l_ecc_bypass); +int iSetERQST_FIFO_ECC_CFG_STATUS_erqst_fifo_ecc_ucrt_addr(unsigned int uerqst_fifo_ecc_ucrt_addr); +int iSetERQST_FIFO_ECC_CFG_STATUS_erqst_fifo_ecc_crt_err_cnt(unsigned int uerqst_fifo_ecc_crt_err_cnt); +int iSetERQST_FIFO_ECC_CFG_STATUS_erqst_fifo_ecc_inj_ack(unsigned int uerqst_fifo_ecc_inj_ack); +int iSetERQST_FIFO_ECC_CFG_STATUS_erqst_fifo_ecc_inj_req(unsigned int uerqst_fifo_ecc_inj_req); +int iSetERQST_FIFO_ECC_CFG_STATUS_erqst_fifo_ecc_bypass(unsigned int uerqst_fifo_ecc_bypass); +int iSetECSR_FIFO_ECC_CFG_STATUS_ecsr_fifo_ecc_ucrt_addr(unsigned int uecsr_fifo_ecc_ucrt_addr); +int iSetECSR_FIFO_ECC_CFG_STATUS_ecsr_fifo_ecc_crt_err_cnt(unsigned int uecsr_fifo_ecc_crt_err_cnt); +int iSetECSR_FIFO_ECC_CFG_STATUS_ecsr_fifo_ecc_inj_ack(unsigned int uecsr_fifo_ecc_inj_ack); +int iSetECSR_FIFO_ECC_CFG_STATUS_ecsr_fifo_ecc_inj_req(unsigned int uecsr_fifo_ecc_inj_req); +int iSetECSR_FIFO_ECC_CFG_STATUS_ecsr_fifo_ecc_bypass(unsigned int uecsr_fifo_ecc_bypass); +int iSetSSB_MEM_ECC_CFG_STATUS_ssb_ecc_ucrt_addr(unsigned int ussb_ecc_ucrt_addr); +int iSetSSB_MEM_ECC_CFG_STATUS_ssb_ecc_crt_err_cnt(unsigned int ussb_ecc_crt_err_cnt); +int iSetSSB_MEM_ECC_CFG_STATUS_ssb_ecc_inj_ack(unsigned int ussb_ecc_inj_ack); +int iSetSSB_MEM_ECC_CFG_STATUS_ssb_ecc_inj_req(unsigned int ussb_ecc_inj_req); +int iSetSSB_MEM_ECC_CFG_STATUS_ssb_ecc_bypass(unsigned int ussb_ecc_bypass); +int iSetDSB_MEM_ECC_CFG_STATUS_dsb_ecc_ucrt_addr(unsigned int udsb_ecc_ucrt_addr); +int iSetDSB_MEM_ECC_CFG_STATUS_dsb_ecc_crt_err_cnt(unsigned int udsb_ecc_crt_err_cnt); +int iSetDSB_MEM_ECC_CFG_STATUS_dsb_ecc_inj_ack(unsigned int udsb_ecc_inj_ack); +int iSetDSB_MEM_ECC_CFG_STATUS_dsb_ecc_inj_req(unsigned int udsb_ecc_inj_req); +int iSetDSB_MEM_ECC_CFG_STATUS_dsb_ecc_bypass(unsigned int udsb_ecc_bypass); +int iSetHOST_ID_TABLE_MEM_ECC_CFG_STATUS_host_id_table_ecc_ucrt_addr(unsigned int uhost_id_table_ecc_ucrt_addr); +int iSetHOST_ID_TABLE_MEM_ECC_CFG_STATUS_host_id_table_ecc_crt_err_cnt(unsigned int uhost_id_table_ecc_crt_err_cnt); +int iSetHOST_ID_TABLE_MEM_ECC_CFG_STATUS_host_id_table_ecc_inj_ack(unsigned int uhost_id_table_ecc_inj_ack); +int iSetHOST_ID_TABLE_MEM_ECC_CFG_STATUS_host_id_table_ecc_inj_req(unsigned int uhost_id_table_ecc_inj_req); +int iSetHOST_ID_TABLE_MEM_ECC_CFG_STATUS_host_id_table_ecc_bypass(unsigned int uhost_id_table_ecc_bypass); +int iSetDEV_ATTRI_TABLE_MEM_ECC_CFG_STATUS_dev_attri_table_ecc_ucrt_addr(unsigned int udev_attri_table_ecc_ucrt_addr); +int iSetDEV_ATTRI_TABLE_MEM_ECC_CFG_STATUS_dev_attri_table_ecc_crt_err_cnt( + unsigned int udev_attri_table_ecc_crt_err_cnt); +int iSetDEV_ATTRI_TABLE_MEM_ECC_CFG_STATUS_dev_attri_table_ecc_inj_ack(unsigned int udev_attri_table_ecc_inj_ack); +int iSetDEV_ATTRI_TABLE_MEM_ECC_CFG_STATUS_dev_attri_table_ecc_inj_req(unsigned int udev_attri_table_ecc_inj_req); +int iSetDEV_ATTRI_TABLE_MEM_ECC_CFG_STATUS_dev_attri_table_ecc_bypass(unsigned int udev_attri_table_ecc_bypass); +int iSetTPRAM_WR_CTRL_virtio_wr_addr(unsigned int uvirtio_wr_addr); +int iSetTPRAM_WR_CTRL_virtio_wr_rdy(unsigned int uvirtio_wr_rdy); +int iSetTPRAM_WR_CTRL_virtio_wr_cfg(unsigned int uvirtio_wr_cfg); +int iSetTPRAM_WR_CTRL_virtio_wr_enable(unsigned int uvirtio_wr_enable); +int iSetTPRAM_WR_CTRL_virtio_wr_sel(unsigned int uvirtio_wr_sel); +int iSetTPRAM_WR_WEN_DATA_31_0_virtio_wr_wdata_31_0(unsigned int uvirtio_wr_wdata_31_0); +int iSetTPRAM_WR_WEN_DATA_63_32_virtio_wr_wdata_63_32(unsigned int uvirtio_wr_wdata_63_32); +int iSetTPRAM_WR_WEN_DATA_95_64_virtio_wr_wdata_95_64(unsigned int uvirtio_wr_wdata_95_64); +int iSetTPRAM_WR_WEN_DATA_127_96_virtio_wr_wdata_127_96(unsigned int uvirtio_wr_wdata_127_96); +int iSetTPRAM_WR_WEN_DATA_159_128_virtio_wr_wdata_159_128(unsigned int uvirtio_wr_wdata_159_128); +int iSetTPRAM_WR_WEN_DATA_191_160_virtio_wr_wdata_191_160(unsigned int uvirtio_wr_wdata_191_160); +int iSetTPRAM_WR_WEN_DATA_223_192_virtio_wr_wdata_223_192(unsigned int uvirtio_wr_wdata_223_192); +int iSetTPRAM_WR_WEN_DATA_255_224_virtio_wr_wdata_255_224(unsigned int uvirtio_wr_wdata_255_224); +int iSetTPRAM_WR_WEN_DATA_287_256_virtio_wr_wdata_287_256(unsigned int uvirtio_wr_wdata_287_256); +int iSetTPRAM_WR_WEN_DATA_319_288_virtio_wr_wdata_319_288(unsigned int uvirtio_wr_wdata_319_288); +int iSetTPRAM_WR_WEN_DATA_335_320_virtio_wr_wdata_335_320(unsigned int uvirtio_wr_wdata_335_320); +int iSetTPRAM_WR_REN_DATA_31_0_virtio_wr_rdata_31_0(unsigned int uvirtio_wr_rdata_31_0); +int iSetTPRAM_WR_REN_DATA_63_32_virtio_wr_rdata_63_32(unsigned int uvirtio_wr_rdata_63_32); +int iSetTPRAM_WR_REN_DATA_95_64_virtio_wr_rdata_95_64(unsigned int uvirtio_wr_rdata_95_64); +int iSetTPRAM_WR_REN_DATA_127_96_virtio_wr_rdata_127_96(unsigned int uvirtio_wr_rdata_127_96); +int iSetTPRAM_WR_REN_DATA_159_128_virtio_wr_rdata_159_128(unsigned int uvirtio_wr_rdata_159_128); +int iSetTPRAM_WR_REN_DATA_191_160_virtio_wr_rdata_191_160(unsigned int uvirtio_wr_rdata_191_160); +int iSetTPRAM_WR_REN_DATA_223_192_virtio_wr_rdata_223_192(unsigned int uvirtio_wr_rdata_223_192); +int iSetTPRAM_WR_REN_DATA_255_224_virtio_wr_rdata_255_224(unsigned int uvirtio_wr_rdata_255_224); +int iSetTPRAM_WR_REN_DATA_287_256_virtio_wr_rdata_287_256(unsigned int uvirtio_wr_rdata_287_256); +int iSetTPRAM_WR_REN_DATA_319_288_virtio_wr_rdata_319_288(unsigned int uvirtio_wr_rdata_319_288); +int iSetTPRAM_WR_REN_DATA_351_320_virtio_wr_rdata_351_320(unsigned int uvirtio_wr_rdata_351_320); +int iSetTPRAM_WR_REN_DATA_383_352_virtio_wr_rdata_383_352(unsigned int uvirtio_wr_rdata_383_352); +int iSetTPRAM_WR_REN_DATA_415_384_virtio_wr_rdata_415_384(unsigned int uvirtio_wr_rdata_415_384); +int iSetTPRAM_WR_REN_DATA_447_416_virtio_wr_rdata_447_416(unsigned int uvirtio_wr_rdata_447_416); +int iSetTPRAM_WR_REN_DATA_479_448_virtio_wr_rdata_479_448(unsigned int uvirtio_wr_rdata_479_448); +int iSetTPRAM_WR_REN_DATA_511_480_virtio_wr_rdata_511_480(unsigned int uvirtio_wr_rdata_511_480); +int iSetTPRAM_WR_REN_DATA_543_512_virtio_wr_rdata_543_512(unsigned int uvirtio_wr_rdata_543_512); +int iSetTPRAM_WR_REN_DATA_575_544_virtio_wr_rdata_575_544(unsigned int uvirtio_wr_rdata_575_544); +int iSetTPRAM_WR_REN_DATA_607_576_virtio_wr_rdata_607_576(unsigned int uvirtio_wr_rdata_607_576); +int iSetTPRAM_WR_REN_DATA_639_608_virtio_wr_rdata_639_608(unsigned int uvirtio_wr_rdata_639_608); +int iSetTPRAM_WR_REN_DATA_671_640_virtio_wr_rdata_671_640(unsigned int uvirtio_wr_rdata_671_640); +int iSetTPRAM_WR_REN_DATA_703_672_virtio_wr_rdata_703_672(unsigned int uvirtio_wr_rdata_703_672); +int iSetTPRAM_WR_REN_DATA_735_704_virtio_wr_rdata_735_704(unsigned int uvirtio_wr_rdata_735_704); +int iSetTPRAM_WR_REN_DATA_767_736_virtio_wr_rdata_767_736(unsigned int uvirtio_wr_rdata_767_736); +int iSetTPRAM_WR_REN_DATA_773_768_virtio_wr_rdata_773_768(unsigned int uvirtio_wr_rdata_773_768); +int iSetLOAD_BALANCE_CFG_virtio_engine_magic_box_pg_cfg(unsigned int uvirtio_engine_magic_box_pg_cfg); +int iSetLOAD_BALANCE_CFG_virtio_engine_lbf(unsigned int uvirtio_engine_lbf); +int iSetLOAD_BALANCE_CFG_virtio_engine_main(unsigned int uvirtio_engine_main); +int iSetFLEX_Q_CFG_virtio_engine_flex_q_en(unsigned int uvirtio_engine_flex_q_en); +int iSetVQ_CNTX_SIZE_virtio_engine_vq_cntx_size(unsigned int uvirtio_engine_vq_cntx_size); +int iSetVIRTIO_REGION_OFF_CFG_virtio_region_4_off(unsigned int uvirtio_region_4_off); +int iSetVIRTIO_REGION_OFF_CFG_virtio_region_3_off(unsigned int uvirtio_region_3_off); +int iSetVIRTIO_REGION_OFF_CFG_virtio_region_2_off(unsigned int uvirtio_region_2_off); +int iSetVIRTIO_LOC_SGL_SIZE_CFG_virtio_virtq_sgl_ptr_max(unsigned int uvirtio_virtq_sgl_ptr_max); +int iSetVIRTIO_LOC_SGL_SIZE_CFG_virtio_virtq_sgl_size(unsigned int uvirtio_virtq_sgl_size); +int iSetVIRTIO_LOC_IDESC_SIZE_CFG_virtio_virtq_idesc_ptr_max(unsigned int uvirtio_virtq_idesc_ptr_max); +int iSetVIRTIO_LOC_IDESC_SIZE_CFG_virtio_virtq_idesc_size(unsigned int uvirtio_virtq_idesc_size); +int iSetVIRTIO_DMA_WAIT_MAX_CFG_virtio_dma_wait_max(unsigned int uvirtio_dma_wait_max); +int iSetVIRTIO_DMA_WAIT_MAX_CFG_virtio_fetching_sgl_max(unsigned int uvirtio_fetching_sgl_max); +int iSetVIRTIO_PREFETCH_TH_virtio_loc_idesc_aful_th(unsigned int uvirtio_loc_idesc_aful_th); +int iSetVIRTIO_MAX_OUTSTAND_TH_virtio_loc_idesc_alempt_th(unsigned int uvirtio_loc_idesc_alempt_th); +int iSetVIRTIO_MAX_OUTSTAND_TH_virtio_avail_idx_alempt_th(unsigned int uvirtio_avail_idx_alempt_th); +int iSetVIRTIO_SPLIT_CHAIN_SPECULATE_TH_CFG_virtio_split_speculate_th(unsigned int uvirtio_split_speculate_th); +int iSetVIRTIO_SQE_DMA_TEMPLATE_DW0_virtio_sqe_dma_template_dw0(unsigned int uvirtio_sqe_dma_template_dw0); +int iSetVIRTIO_SQE_DMA_TEMPLATE_DW1_virtio_sqe_dma_template_dw1(unsigned int uvirtio_sqe_dma_template_dw1); +int iSetVIRTIO_SQE_DMA_TEMPLATE_DW2_virtio_sqe_dma_template_dw2(unsigned int uvirtio_sqe_dma_template_dw2); +int iSetVIRTIO_SQE_DMA_TEMPLATE_DW3_virtio_sqe_dma_template_dw3(unsigned int uvirtio_sqe_dma_template_dw3); +int iSetVIRTIO_RQE_DMA_TEMPLATE_DW0_virtio_rqe_dma_template_dw0(unsigned int uvirtio_rqe_dma_template_dw0); +int iSetVIRTIO_RQE_DMA_TEMPLATE_DW1_virtio_rqe_dma_template_dw1(unsigned int uvirtio_rqe_dma_template_dw1); +int iSetVIRTIO_RQE_DMA_TEMPLATE_DW2_virtio_rqe_dma_template_dw2(unsigned int uvirtio_rqe_dma_template_dw2); +int iSetVIRTIO_RQE_DMA_TEMPLATE_DW3_virtio_rqe_dma_template_dw3(unsigned int uvirtio_rqe_dma_template_dw3); +int iSetNVME_QP_CNTX_CFG0_nvme_region_2_off(unsigned int unvme_region_2_off); +int iSetNVME_QP_CNTX_CFG1_nvme_region_2_ptr_max(unsigned int unvme_region_2_ptr_max); +int iSetNVME_QP_CNTX_CFG1_nvme_region_2_size(unsigned int unvme_region_2_size); +int iSetVIRTIO_ENGINE_NVME_CNTX_OFFSET_nvme_qp_cntx_start_offset(unsigned int unvme_qp_cntx_start_offset); +int iSetVIRTIO_ENGINE_VIRTIO_CNTX_OFFSET_virtio_vq_cntx_start_offset(unsigned int uvirtio_vq_cntx_start_offset); +int iSetNVME_DMA_CFG_nvme_dma_buf_min(unsigned int unvme_dma_buf_min); +int iSetNVME_DMA_CFG_nvme_dma_wait_max(unsigned int unvme_dma_wait_max); +int iSetNVME_DMA_TEMPLATE_DW0_nvme_dma_template_dw0(unsigned int unvme_dma_template_dw0); +int iSetNVME_DMA_TEMPLATE_DW1_nvme_dma_template_dw1(unsigned int unvme_dma_template_dw1); +int iSetNVME_DMA_TEMPLATE_DW2_nvme_dma_template_dw2(unsigned int unvme_dma_template_dw2); +int iSetIRQST_CREDIT_STATUS_irqst_credit_cnt(unsigned int uirqst_credit_cnt); +int iSetIRQST_FIFO_STATUS_irqst_fifo_empty(unsigned int uirqst_fifo_empty); +int iSetIRQST_FIFO_STATUS_irqst_fifo_full(unsigned int uirqst_fifo_full); +int iSetIRQST_FIFO_STATUS_irqst_fifo_cnt(unsigned int uirqst_fifo_cnt); +int iSetIRQST_STATISTIC_API_irqst_api_cnt_node_id(unsigned int uirqst_api_cnt_node_id); +int iSetIRQST_STATISTIC_API_irqst_api_cnt_all_node_en(unsigned int uirqst_api_cnt_all_node_en); +int iSetIRQST_API_WITH_A_CNT_irqst_api_with_ack_cnt(unsigned int uirqst_api_with_ack_cnt); +int iSetIRQST_API_WITHOUT_A_CNT_irqst_api_without_ack_cnt(unsigned int uirqst_api_without_ack_cnt); +int iSetIRQST_API_INVALID_STATUS_irqst_api_invalid_cnt(unsigned int uirqst_api_invalid_cnt); +int iSetIRQST_API_INVALID_STATUS_irqst_api_invalid_a(unsigned int uirqst_api_invalid_a); +int iSetIRQST_API_INVALID_STATUS_irqst_api_invalid_op_id(unsigned int uirqst_api_invalid_op_id); +int iSetIRQST_API_INVALID_STATUS_irqst_api_invalid_src(unsigned int uirqst_api_invalid_src); +int iSetIRQST_API_INVALID_STATUS_irqst_api_invalid_m(unsigned int uirqst_api_invalid_m); +int iSetIRQST_INT_EN_CFG_irqst_sop_eop_mismatch_int_en(unsigned int uirqst_sop_eop_mismatch_int_en); +int iSetIRQST_INT_EN_CFG_irqst_invalid_flit_int_en(unsigned int uirqst_invalid_flit_int_en); +int iSetIRSP_CREDIT_STATUS_irsp_credit_cnt(unsigned int uirsp_credit_cnt); +int iSetIRSP_FIFO_CFG_STATUS_irsp_fifo_empty(unsigned int uirsp_fifo_empty); +int iSetIRSP_FIFO_CFG_STATUS_irsp_fifo_full(unsigned int uirsp_fifo_full); +int iSetIRSP_FIFO_CFG_STATUS_irsp_fifo_cnt(unsigned int uirsp_fifo_cnt); +int iSetIRSP_API_STATISTIC_irsp_api_from_cpi_cnt(unsigned int uirsp_api_from_cpi_cnt); +int iSetIRSP_INVALID_FLIT_irsp_flit_not_from_cpi_cnt(unsigned int uirsp_flit_not_from_cpi_cnt); +int iSetIRSP_INVALID_FLIT_irsp_flit_not_from_cpi_src(unsigned int uirsp_flit_not_from_cpi_src); +int iSetIRSP_INVALID_FLIT_irsp_api_not_from_cpi_cnt(unsigned int uirsp_api_not_from_cpi_cnt); +int iSetIRSP_INT_EN_CFG_irsp_flit_not_from_cpi_int_en(unsigned int uirsp_flit_not_from_cpi_int_en); +int iSetIRSP_INT_EN_CFG_irsp_sop_eop_mismatch_int_en(unsigned int uirsp_sop_eop_mismatch_int_en); +int iSetICSR_CREDIT_STATUS_icsr_credit_cnt(unsigned int uicsr_credit_cnt); +int iSetICSR_FIFO_STATUS_icsr_fifo_empty(unsigned int uicsr_fifo_empty); +int iSetICSR_FIFO_STATUS_icsr_fifo_full(unsigned int uicsr_fifo_full); +int iSetICSR_FIFO_STATUS_ics_fifo_cnt(unsigned int uics_fifo_cnt); +int iSetICSR_API_WITH_A_CNT_icsr_api_with_ack_cnt(unsigned int uicsr_api_with_ack_cnt); +int iSetICSR_API_WITHOUT_A_CNT_icsr_api_without_ack_cnt(unsigned int uicsr_api_without_ack_cnt); +int iSetICSR_INVALID_API_icsr_invalid_flit_cnt(unsigned int uicsr_invalid_flit_cnt); +int iSetICSR_INVALID_API_icsr_invalid_flit_op_id(unsigned int uicsr_invalid_flit_op_id); +int iSetICSR_INVALID_API_icsr_invalid_flit_src(unsigned int uicsr_invalid_flit_src); +int iSetICSR_INVALID_API_icsr_invalid_flit_type(unsigned int uicsr_invalid_flit_type); +int iSetICSR_INVALID_API_icsr_invalid_flit_ack(unsigned int uicsr_invalid_flit_ack); +int iSetICSR_CPATH_TIMEOUT_CFG_icsr_no_thread_timeout_th(unsigned int uicsr_no_thread_timeout_th); +int iSetICSR_CPATH_TIMEOUT_DROP_API_CNT_icsr_drop_cpath_api_cnt(unsigned int uicsr_drop_cpath_api_cnt); +int iSetICSR_INT_EN_CFG_icsr_invalid_flit_int_en(unsigned int uicsr_invalid_flit_int_en); +int iSetISCH_WEIGHT_CFG_isch_wrr_icsr_weight(unsigned int uisch_wrr_icsr_weight); +int iSetISCH_WEIGHT_CFG_isch_wrr_irsp_weight(unsigned int uisch_wrr_irsp_weight); +int iSetISCH_WEIGHT_CFG_icsr_wrrsp_l_weight(unsigned int uicsr_wrrsp_l_weight); +int iSetISCH_WEIGHT_CFG_icsr_wrrsp_m_weight(unsigned int uicsr_wrrsp_m_weight); +int iSetISCH_WEIGHT_CFG_icsr_wrrsp_h_weight(unsigned int uicsr_wrrsp_h_weight); +int iSetISCH_WEIGHT_CFG_icsr_wrrsp_sp_en(unsigned int uicsr_wrrsp_sp_en); +int iSetERQST_CREDIT_STATUS_erqst_credit_cnt(unsigned int uerqst_credit_cnt); +int iSetERQST_CREDIT_STATUS_erqst_credit_th(unsigned int uerqst_credit_th); +int iSetERQST_DMA_TEMPLATE_erqst_dma_c_chl(unsigned int uerqst_dma_c_chl); +int iSetERQST_DMA_TEMPLATE_erqst_dma_attr_offset(unsigned int uerqst_dma_attr_offset); +int iSetERQST_DMA_TEMPLATE_erqst_dma_so_ro(unsigned int uerqst_dma_so_ro); +int iSetERQST_API_CNT_erqst_api_cnt(unsigned int uerqst_api_cnt); +int iSetERQST_FIFO_STATUS_erqst_fifo_empty(unsigned int uerqst_fifo_empty); +int iSetERQST_FIFO_STATUS_erqst_fifo_full(unsigned int uerqst_fifo_full); +int iSetERQST_FIFO_STATUS_erqst_fifo_cnt(unsigned int uerqst_fifo_cnt); +int iSetERSP_CREDIT_STATUS_ersp_credit_cnt(unsigned int uersp_credit_cnt); +int iSetERSP_CREDIT_STATUS_ersp_credit_th(unsigned int uersp_credit_th); +int iSetERSP_FIFO_STATUS_ersp_fifo_empty(unsigned int uersp_fifo_empty); +int iSetERSP_FIFO_STATUS_ersp_fifo_full(unsigned int uersp_fifo_full); +int iSetERSP_FIFO_STATUS_ersp_fifo_cnt(unsigned int uersp_fifo_cnt); +int iSetERSP_FLIT_CNT_ersp_flit_cnt(unsigned int uersp_flit_cnt); +int iSetERSP_API_CNT_ersp_api_cnt(unsigned int uersp_api_cnt); +int iSetECSR_CREDIT_STATUS_ecsr_credit_cnt(unsigned int uecsr_credit_cnt); +int iSetECSR_CREDIT_STATUS_ecsr_credit_th(unsigned int uecsr_credit_th); +int iSetECSR_FIFO_CFG_STATUS_ecsr_fifo_empty(unsigned int uecsr_fifo_empty); +int iSetECSR_FIFO_CFG_STATUS_ecsr_fifo_full(unsigned int uecsr_fifo_full); +int iSetECSR_FIFO_CFG_STATUS_ecsr_fifo_cnt(unsigned int uecsr_fifo_cnt); +int iSetECSR_API_CNT_ecsr_api_cnt(unsigned int uecsr_api_cnt); +int iSetSIF_SMLC_OUTSTANDING_THREAD_SCAN_sif_scan_thread_fun_id(unsigned int usif_scan_thread_fun_id); +int iSetSIF_SMLC_OUTSTANDING_THREAD_SCAN_sif_scan_thread_req(unsigned int usif_scan_thread_req); +int iSetSIF_SMLC_OUTSTANDING_THREAD_SCAN_sif_scan_thread_outst_num(unsigned int usif_scan_thread_outst_num); +int iSetSIF_SMLC_OUTSTANDING_THREAD_SCAN_sif_scan_thread_busy(unsigned int usif_scan_thread_busy); +int iSetSIF_SMLC_OUTSTANDING_THREAD_SCAN_sif_scan_thread_done(unsigned int usif_scan_thread_done); +int iSetSIF_SMLC_DELAY_CFG_sif_delay_query_thread_id(unsigned int usif_delay_query_thread_id); +int iSetSIF_SMLC_DELAY_CFG_sif_delay_query_req(unsigned int usif_delay_query_req); +int iSetSIF_SMLC_DELAY_TIMER_sif_delay_query_thread_timer(unsigned int usif_delay_query_thread_timer); +int iSetSIF_SMLC_DELAY_MIN_sif_delay_query_thread_timer_min(unsigned int usif_delay_query_thread_timer_min); +int iSetSIF_SMLC_DELAY_MAX_sif_delay_query_thread_timer_max(unsigned int usif_delay_query_thread_timer_max); +int iSetSIF_FUN_MEM_MODE_BADDR_sif_func_mem_base_addr(unsigned int usif_func_mem_base_addr); +int iSetSIF_VQ_MEM_MODE_BADDR_CFG_sif_virtq_mem_base_addr(unsigned int usif_virtq_mem_base_addr); +int iSetSIF_INSTANCE_ID_CFG_sif_nvme_instance_id(unsigned int usif_nvme_instance_id); +int iSetSIF_INSTANCE_ID_CFG_sif_virtio_instance_id(unsigned int usif_virtio_instance_id); +int iSetSIF_INSTANCE_ID_CFG_sif_cache_instance_id(unsigned int usif_cache_instance_id); +int iSetSIF_SMLC_IF_CFG_0_sif_func_cntx_mem_en(unsigned int usif_func_cntx_mem_en); +int iSetSIF_SMLC_IF_CFG_0_sif_virtq_cntx_stick_en(unsigned int usif_virtq_cntx_stick_en); +int iSetSIF_SMLC_IF_CFG_0_sif_func_cntx_stick_en(unsigned int usif_func_cntx_stick_en); +int iSetSIF_SMLC_IF_CFG_0_sif_virtq_cntx_mem_en(unsigned int usif_virtq_cntx_mem_en); +int iSetSIF_SMLC_IF_CFG_0_sif_mem_index_refill_len(unsigned int usif_mem_index_refill_len); +int iSetSIF_SMLC_IF_CFG_0_sif_mem_index_refill_len_valid(unsigned int usif_mem_index_refill_len_valid); +int iSetSIF_SMLC_IF_CFG_0_sif_cache_mem_index_type(unsigned int usif_cache_mem_index_type); +int iSetSIF_SMLC_IF_CFG_0_sif_nvme_mem_index_type(unsigned int usif_nvme_mem_index_type); +int iSetSIF_SMLC_IF_CFG_0_sif_virtio_mem_index_type(unsigned int usif_virtio_mem_index_type); +int iSetSIF_SMLC_IF_CFG_1_sif_nvme_region0_subentry(unsigned int usif_nvme_region0_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_nvme_region1_subentry(unsigned int usif_nvme_region1_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_nvme_region2_subentry(unsigned int usif_nvme_region2_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_virtio_region0_subentry(unsigned int usif_virtio_region0_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_virtio_region1_subentry(unsigned int usif_virtio_region1_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_virtio_region2_subentry(unsigned int usif_virtio_region2_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_virtio_region3_subentry(unsigned int usif_virtio_region3_subentry); +int iSetSIF_SMLC_IF_CFG_1_sif_virtio_region4_subentry(unsigned int usif_virtio_region4_subentry); +int iSetSIF_SMLC_IF_CFG_2_sif_pcie_template(unsigned int usif_pcie_template); +int iSetSIF_SMLC_IF_CFG_2_sif_func_cntx_cache_index_sel(unsigned int usif_func_cntx_cache_index_sel); +int iSetSIF_SMLC_IF_CFG_2_sif_virtq_cntx_cache_index_sel(unsigned int usif_virtq_cntx_cache_index_sel); +int iSetSIF_SMLC_IF_CFG_2_memop_sr_not_early_done_en(unsigned int umemop_sr_not_early_done_en); +int iSetSIF_SMLC_IF_CFG_2_memop_st_not_early_done_en(unsigned int umemop_st_not_early_done_en); +int iSetSIF_SMLC_IF_CFG_3_sif_thread_timeout_th(unsigned int usif_thread_timeout_th); +int iSetHOST_PPF_CFG_0_sif_host2_ppf(unsigned int usif_host2_ppf); +int iSetHOST_PPF_CFG_0_sif_host3_ppf(unsigned int usif_host3_ppf); +int iSetHOST_PPF_CFG_1_sif_host0_ppf(unsigned int usif_host0_ppf); +int iSetHOST_PPF_CFG_1_sif_host1_ppf(unsigned int usif_host1_ppf); +int iSetSIF_SMLC_THREAD_TIMEOUT_STATUS_0_sif_smlc_thread_timeout_l(unsigned int usif_smlc_thread_timeout_l); +int iSetSIF_SMLC_THREAD_TIMEOUT_STATUS_1_sif_smlc_thread_timeout_h(unsigned int usif_smlc_thread_timeout_h); +int iSetSIF_INT_EN_CFG_sif_cacheline_index_of_int_en(unsigned int usif_cacheline_index_of_int_en); +int iSetSTM_SHARE_THREAD_MAX_stm_share_thread_max(unsigned int ustm_share_thread_max); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_flr_thread_max(unsigned int ustm_flr_thread_max); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_flr_share_en(unsigned int ustm_flr_share_en); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_csr_thread_max(unsigned int ustm_csr_thread_max); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_csr_share_en(unsigned int ustm_csr_share_en); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_resp_thread_max(unsigned int ustm_resp_thread_max); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_resp_share_en(unsigned int ustm_resp_share_en); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_rqst_thread_max(unsigned int ustm_rqst_thread_max); +int iSetSTM_CHANNEL_THREAD_TH_CFG_stm_rqst_share_en(unsigned int ustm_rqst_share_en); +int iSetSTM_SHARE_THREAD_STATUS_stm_share_thread_cnt(unsigned int ustm_share_thread_cnt); +int iSetSTM_SHARE_THREAD_STATUS_stm_free_addr_cnt(unsigned int ustm_free_addr_cnt); +int iSetSTM_CHANNEL_THREAD_STATUS_stm_flr_thread_cnt(unsigned int ustm_flr_thread_cnt); +int iSetSTM_CHANNEL_THREAD_STATUS_stm_csr_thread_cnt(unsigned int ustm_csr_thread_cnt); +int iSetSTM_CHANNEL_THREAD_STATUS_stm_resp_thread_cnt(unsigned int ustm_resp_thread_cnt); +int iSetSTM_CHANNEL_THREAD_STATUS_stm_rqst_thread_cnt(unsigned int ustm_rqst_thread_cnt); +int iSetSTM_FIFO0_STATUS_stm_fifo_0_empty(unsigned int ustm_fifo_0_empty); +int iSetSTM_FIFO0_STATUS_stm_fifo_0_full(unsigned int ustm_fifo_0_full); +int iSetSTM_FIFO0_STATUS_stm_fifo_0_cnt(unsigned int ustm_fifo_0_cnt); +int iSetSTM_FIFO1_STATUS_stm_fifo_1_empty(unsigned int ustm_fifo_1_empty); +int iSetSTM_FIFO1_STATUS_stm_fifo_1_full(unsigned int ustm_fifo_1_full); +int iSetSTM_FIFO1_STATUS_stm_fifo_1_cnt(unsigned int ustm_fifo_1_cnt); +int iSetDTM_TAG_ALEMPTY_TH_dtm_desc_tag_aful_th(unsigned int udtm_desc_tag_aful_th); +int iSetDTM_TAG_TH_CFG_dtm_desc_tag_max(unsigned int udtm_desc_tag_max); +int iSetDTM_TAG_TH_CFG_dtm_desc_share_en(unsigned int udtm_desc_share_en); +int iSetDTM_TAG_TH_CFG_dtm_db_tag_max(unsigned int udtm_db_tag_max); +int iSetDTM_TAG_TH_CFG_dtm_db_share_en(unsigned int udtm_db_share_en); +int iSetDTM_TAG_TH_CFG_dtm_share_tag_max(unsigned int udtm_share_tag_max); +int iSetDTM_TAG_STATUS_dtm_desc_tag_cnt(unsigned int udtm_desc_tag_cnt); +int iSetDTM_TAG_STATUS_dtm_db_tag_cnt(unsigned int udtm_db_tag_cnt); +int iSetDTM_TAG_STATUS_dtm_share_tag_cnt(unsigned int udtm_share_tag_cnt); +int iSetDTM_TAG_STATUS_dtm_free_addr_cnt(unsigned int udtm_free_addr_cnt); +int iSetDTM_DMA_OUTSTANDING_TAG_SCAN_dtm_scan_tag_fun_id(unsigned int udtm_scan_tag_fun_id); +int iSetDTM_DMA_OUTSTANDING_TAG_SCAN_dtm_scan_tag_req(unsigned int udtm_scan_tag_req); +int iSetDTM_DMA_OUTSTANDING_TAG_SCAN_dtm_scan_tag_outst_num(unsigned int udtm_scan_tag_outst_num); +int iSetDTM_DMA_OUTSTANDING_TAG_SCAN_dtm_scan_tag_busy(unsigned int udtm_scan_tag_busy); +int iSetDTM_DMA_OUTSTANDING_TAG_SCAN_dtm_scan_tag_done(unsigned int udtm_scan_tag_done); +int iSetDTM_DMA_DELAY_CFG_dtm_delay_query_tag_id(unsigned int udtm_delay_query_tag_id); +int iSetDTM_DMA_DELAY_CFG_dtm_delay_query_req(unsigned int udtm_delay_query_req); +int iSetDTM_DMA_DELAY_TIMER_dtm_delay_query_tag_timer(unsigned int udtm_delay_query_tag_timer); +int iSetDTM_DMA_DELAY_MIN_dtm_delay_query_tag_timer_min(unsigned int udtm_delay_query_tag_timer_min); +int iSetDTM_DMA_DELAY_MAX_dtm_delay_query_tag_timer_max(unsigned int udtm_delay_query_tag_timer_max); +int iSetDTM_DMA_TAG_TIMEOUT_CFG_dtm_dma_tag_timeout_th(unsigned int udtm_dma_tag_timeout_th); +int iSetDTM_DMA_TAG_TIMEOUT_STATUS_0_dtm_dma_tag_timeout_31_0(unsigned int udtm_dma_tag_timeout_31_0); +int iSetDTM_DMA_TAG_TIMEOUT_STATUS_1_dtm_dma_tag_timeout_63_32(unsigned int udtm_dma_tag_timeout_63_32); +int iSetDTM_DMA_TAG_TIMEOUT_STATUS_2_dtm_dma_tag_timeout_95_64(unsigned int udtm_dma_tag_timeout_95_64); +int iSetDTM_DMA_TAG_TIMEOUT_STATUS_3_dtm_dma_tag_timeout_127_96(unsigned int udtm_dma_tag_timeout_127_96); +int iSetNVME_CPATH_TOTAL_API_CNT_ncpath_dfx_total_st_op_cnt(unsigned int uncpath_dfx_total_st_op_cnt); +int iSetNVME_CPATH_TOTAL_API_CNT_ncpath_dfx_total_ld_op_cnt(unsigned int uncpath_dfx_total_ld_op_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_flr_aeqe_pending_cnt(unsigned int uncpath_dfx_flr_aeqe_pending_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_aeqe_pending_cnt(unsigned int uncpath_dfx_aeqe_pending_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_st_no_aeqe_cnt(unsigned int uncpath_dfx_st_no_aeqe_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_invld_st_op_cnt(unsigned int uncpath_dfx_invld_st_op_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_invld_ld_op_cnt(unsigned int uncpath_dfx_invld_ld_op_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_invld_field_cnt(unsigned int uncpath_dfx_invld_field_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_smlc_err_cnt(unsigned int uncpath_dfx_smlc_err_cnt); +int iSetNVME_CPATH_INVALID_API_CNT_ncpath_dfx_e0e1_api_cnt(unsigned int uncpath_dfx_e0e1_api_cnt); +int iSetNVME_CPATH_LAST_INVALID_LOAD_OPERATION_ncpath_dfx_last_invld_ld_op_funcid( + unsigned int uncpath_dfx_last_invld_ld_op_funcid); +int iSetNVME_CPATH_LAST_INVALID_LOAD_OPERATION_ncpath_dfx_last_invld_ld_op_a( + unsigned int uncpath_dfx_last_invld_ld_op_a); +int iSetNVME_CPATH_LAST_INVALID_LOAD_OPERATION_ncpath_dfx_last_invld_ld_op_ofst( + unsigned int uncpath_dfx_last_invld_ld_op_ofst); +int iSetNVME_CPATH_LAST_INVALID_LOAD_OPERATION_ncpath_dfx_last_invld_ld_op_size( + unsigned int uncpath_dfx_last_invld_ld_op_size); +int iSetNVME_CPATH_LAST_INVALID_LOAD_OPERATION_ncpath_dfx_last_invld_ld_op_dwbe( + unsigned int uncpath_dfx_last_invld_ld_op_dwbe); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_1_ncpath_dfx_last_invld_st_op_funcid( + unsigned int uncpath_dfx_last_invld_st_op_funcid); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_1_ncpath_dfx_last_invld_st_op_a( + unsigned int uncpath_dfx_last_invld_st_op_a); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_1_ncpath_dfx_last_invld_st_op_ofst( + unsigned int uncpath_dfx_last_invld_st_op_ofst); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_1_ncpath_dfx_last_invld_st_op_size( + unsigned int uncpath_dfx_last_invld_st_op_size); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_1_ncpath_dfx_last_invld_st_op_dwbe( + unsigned int uncpath_dfx_last_invld_st_op_dwbe); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_2_ncpath_dfx_last_invld_st_op_wdata_l( + unsigned int uncpath_dfx_last_invld_st_op_wdata_l); +int iSetNVME_CPATH_LAST_INVALID_STORE_OPERATION_3_ncpath_dfx_last_invld_st_op_wdata_h( + unsigned int uncpath_dfx_last_invld_st_op_wdata_h); +int iSetNVME_CPATH_LAST_VALID_LOAD_OPERATION_ncpath_dfx_last_vld_ld_op_funcid( + unsigned int uncpath_dfx_last_vld_ld_op_funcid); +int iSetNVME_CPATH_LAST_VALID_LOAD_OPERATION_ncpath_dfx_last_vld_ld_op_a(unsigned int uncpath_dfx_last_vld_ld_op_a); +int iSetNVME_CPATH_LAST_VALID_LOAD_OPERATION_ncpath_dfx_last_vld_ld_op_ofst( + unsigned int uncpath_dfx_last_vld_ld_op_ofst); +int iSetNVME_CPATH_LAST_VALID_LOAD_OPERATION_ncpath_dfx_last_vld_ld_op_size( + unsigned int uncpath_dfx_last_vld_ld_op_size); +int iSetNVME_CPATH_LAST_VALID_LOAD_OPERATION_ncpath_dfx_last_vld_ld_op_dwbe( + unsigned int uncpath_dfx_last_vld_ld_op_dwbe); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_1_ncpath_dfx_last_vld_st_op_funcid( + unsigned int uncpath_dfx_last_vld_st_op_funcid); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_1_ncpath_dfx_last_vld_st_op_a(unsigned int uncpath_dfx_last_vld_st_op_a); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_1_ncpath_dfx_last_vld_st_op_ofst( + unsigned int uncpath_dfx_last_vld_st_op_ofst); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_1_ncpath_dfx_last_vld_st_op_size( + unsigned int uncpath_dfx_last_vld_st_op_size); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_1_ncpath_dfx_last_vld_st_op_dwbe( + unsigned int uncpath_dfx_last_vld_st_op_dwbe); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_2_ncpath_dfx_last_vld_st_op_wdata_l( + unsigned int uncpath_dfx_last_vld_st_op_wdata_l); +int iSetNVME_CPATH_LAST_VALID_STORE_OPERATION_3_ncpath_dfx_last_vld_st_op_wdata_h( + unsigned int uncpath_dfx_last_vld_st_op_wdata_h); +int iSetNVME_CPATH_INT_EN_ncpath_flr_aeqe_pending_int_en(unsigned int uncpath_flr_aeqe_pending_int_en); +int iSetNVME_CPATH_INT_EN_ncpath_aeqe_pending_int_en(unsigned int uncpath_aeqe_pending_int_en); +int iSetNVME_CPATH_INT_EN_ncpath_invld_api_int_en(unsigned int uncpath_invld_api_int_en); +int iSetNVME_DPATH_LOAD_API_CNT_ndpath_load_api_cnt(unsigned int undpath_load_api_cnt); +int iSetNVME_DPATH_STORE_API_CNT_ndpath_store_api_cnt(unsigned int undpath_store_api_cnt); +int iSetVIRTIO_DFX_FUNC_ID_CFG_virtio_dfx_func_id(unsigned int uvirtio_dfx_func_id); +int iSetVIRTIO_DFX_VQN_CFG_virtio_dfx_vqn(unsigned int uvirtio_dfx_vqn); +int iSetVIRTIO_DFX_VQN_CFG_virtio_dfx_glb_vqn(unsigned int uvirtio_dfx_glb_vqn); +int iSetVIRTIO_DPATH_TOTAL_API_CNT_vdpath_dfx_total_st_op_cnt(unsigned int uvdpath_dfx_total_st_op_cnt); +int iSetVIRTIO_DPATH_TOTAL_API_CNT_vdpath_dfx_total_ld_op_cnt(unsigned int uvdpath_dfx_total_ld_op_cnt); +int iSetVIRTIO_DPATH_ABNORMAL_API_CNT_vdpath_dfx_st_offside_cnt(unsigned int uvdpath_dfx_st_offside_cnt); +int iSetVIRTIO_DPATH_ABNORMAL_API_CNT_vdpath_dfx_st_aeqe_none_cnt(unsigned int uvdpath_dfx_st_aeqe_none_cnt); +int iSetVIRTIO_DPATH_ABNORMAL_API_CNT_vdpath_dfx_st_invld_cnt(unsigned int uvdpath_dfx_st_invld_cnt); +int iSetVIRTIO_DPATH_ABNORMAL_API_CNT_vdpath_dfx_e0e1_api_cnt(unsigned int uvdpath_dfx_e0e1_api_cnt); +int iSetVIRTIO_DPATH_ABNORMAL_API_CNT_vdpath_dfx_smlc_err_cnt(unsigned int uvdpath_dfx_smlc_err_cnt); +int iSetVIRTIO_DPATH_INVLD_API_CNT_vdpath_dfx_lb_not_me_cnt(unsigned int uvdpath_dfx_lb_not_me_cnt); +int iSetVIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_1_vdpath_dfx_last_vld_ld_op_funcid( + unsigned int uvdpath_dfx_last_vld_ld_op_funcid); +int iSetVIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_1_vdpath_dfx_last_vld_ld_op_dev_type( + unsigned int uvdpath_dfx_last_vld_ld_op_dev_type); +int iSetVIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_1_vdpath_dfx_last_vld_ld_op_qid( + unsigned int uvdpath_dfx_last_vld_ld_op_qid); +int iSetVIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_2_vdpath_dfx_last_vld_ld_op_region( + unsigned int uvdpath_dfx_last_vld_ld_op_region); +int iSetVIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_2_vdpath_dfx_last_vld_ld_op_length( + unsigned int uvdpath_dfx_last_vld_ld_op_length); +int iSetVIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_2_vdpath_dfx_last_vld_ld_op_offset( + unsigned int uvdpath_dfx_last_vld_ld_op_offset); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_1_vdpath_dfx_last_vld_st_op_funcid( + unsigned int uvdpath_dfx_last_vld_st_op_funcid); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_1_vdpath_dfx_last_vld_st_op_dev_type( + unsigned int uvdpath_dfx_last_vld_st_op_dev_type); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_1_vdpath_dfx_last_vld_st_op_qid( + unsigned int uvdpath_dfx_last_vld_st_op_qid); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_2_vdpath_dfx_last_vld_st_op_region( + unsigned int uvdpath_dfx_last_vld_st_op_region); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_2_vdpath_dfx_last_vld_st_op_aeqe( + unsigned int uvdpath_dfx_last_vld_st_op_aeqe); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_2_vdpath_dfx_last_vld_st_op_a( + unsigned int uvdpath_dfx_last_vld_st_op_a); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_2_vdpath_dfx_last_vld_st_op_offset( + unsigned int uvdpath_dfx_last_vld_st_op_offset); +int iSetVIRTIO_DPATH_LAST_VALID_STORE_OPERATION_3_vdpath_dfx_last_vld_st_op_byte_en( + unsigned int uvdpath_dfx_last_vld_st_op_byte_en); +int iSetVIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_1_vdpath_dfx_last_invld_ld_op_funcid( + unsigned int uvdpath_dfx_last_invld_ld_op_funcid); +int iSetVIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_1_vdpath_dfx_last_invld_ld_op_dev_type( + unsigned int uvdpath_dfx_last_invld_ld_op_dev_type); +int iSetVIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_1_vdpath_dfx_last_invld_ld_op_qid( + unsigned int uvdpath_dfx_last_invld_ld_op_qid); +int iSetVIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_2_vdpath_dfx_last_invld_ld_op_region( + unsigned int uvdpath_dfx_last_invld_ld_op_region); +int iSetVIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_2_vdpath_dfx_last_invld_ld_op_length( + unsigned int uvdpath_dfx_last_invld_ld_op_length); +int iSetVIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_2_vdpath_dfx_last_invld_ld_op_offset( + unsigned int uvdpath_dfx_last_invld_ld_op_offset); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_1_vdpath_dfx_last_invld_st_op_funcid( + unsigned int uvdpath_dfx_last_invld_st_op_funcid); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_1_vdpath_dfx_last_invld_st_op_dev_type( + unsigned int uvdpath_dfx_last_invld_st_op_dev_type); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_1_vdpath_dfx_last_invld_st_op_qid( + unsigned int uvdpath_dfx_last_invld_st_op_qid); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_2_vdpath_dfx_last_invld_st_op_region( + unsigned int uvdpath_dfx_last_invld_st_op_region); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_2_vdpath_dfx_last_invld_st_op_aeqe( + unsigned int uvdpath_dfx_last_invld_st_op_aeqe); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_2_vdpath_dfx_last_invld_st_op_a( + unsigned int uvdpath_dfx_last_invld_st_op_a); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_2_vdpath_dfx_last_invld_st_op_offset( + unsigned int uvdpath_dfx_last_invld_st_op_offset); +int iSetVIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_3_vdpath_dfx_last_invld_st_op_byte_en( + unsigned int uvdpath_dfx_last_invld_st_op_byte_en); +int iSetVIRTIO_DPATH_INT_EN_vdpath_invld_st_ofst_int_en(unsigned int uvdpath_invld_st_ofst_int_en); +int iSetVIRTIO_CPATH_TOTAL_API_CNT_vcpath_dfx_total_st_op_cnt(unsigned int uvcpath_dfx_total_st_op_cnt); +int iSetVIRTIO_CPATH_TOTAL_API_CNT_vcpath_dfx_total_ld_op_cnt(unsigned int uvcpath_dfx_total_ld_op_cnt); +int iSetVIRTIO_CPATH_ABNORMAL_API_CNT_vcpath_dfx_aeqe_pending_cnt(unsigned int uvcpath_dfx_aeqe_pending_cnt); +int iSetVIRTIO_CPATH_ABNORMAL_API_CNT_vcpath_dfx_st_invld_cnt(unsigned int uvcpath_dfx_st_invld_cnt); +int iSetVIRTIO_CPATH_ABNORMAL_API_CNT_vcpath_dfx_lb_not_me_cnt(unsigned int uvcpath_dfx_lb_not_me_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_invld_vq_cfg_rdy_cnt(unsigned int uvcpath_dfx_invld_vq_cfg_rdy_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_invld_st_cnt(unsigned int uvcpath_dfx_invld_st_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_invld_ld_cnt(unsigned int uvcpath_dfx_invld_ld_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_invld_field_cnt(unsigned int uvcpath_dfx_invld_field_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_invld_size_cnt(unsigned int uvcpath_dfx_invld_size_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_e0e1_api_cnt(unsigned int uvcpath_dfx_e0e1_api_cnt); +int iSetVIRTIO_CPATH_INVLD_API_CNT_vcpath_dfx_smlc_err_cnt(unsigned int uvcpath_dfx_smlc_err_cnt); +int iSetVIRTIO_CPATH_FLR_OP_API_CNT_vcpath_dfx_flr_st_none_cnt(unsigned int uvcpath_dfx_flr_st_none_cnt); +int iSetVIRTIO_CPATH_FLR_OP_API_CNT_vcpath_dfx_flr_ld_rsvd_cnt(unsigned int uvcpath_dfx_flr_ld_rsvd_cnt); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_1_vcpath_dfx_last_vld_ld_op_funcid( + unsigned int uvcpath_dfx_last_vld_ld_op_funcid); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_1_vcpath_dfx_last_vld_ld_op_bar_hit( + unsigned int uvcpath_dfx_last_vld_ld_op_bar_hit); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_1_vcpath_dfx_last_vld_ld_op_a(unsigned int uvcpath_dfx_last_vld_ld_op_a); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_1_vcpath_dfx_last_vld_ld_op_ofset( + unsigned int uvcpath_dfx_last_vld_ld_op_ofset); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_1_vcpath_dfx_last_vld_ld_op_dwbe( + unsigned int uvcpath_dfx_last_vld_ld_op_dwbe); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_2_vcpath_dfx_last_vld_ld_op_cntx_vld( + unsigned int uvcpath_dfx_last_vld_ld_op_cntx_vld); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_2_vcpath_dfx_last_vld_ld_op_msix_en( + unsigned int uvcpath_dfx_last_vld_ld_op_msix_en); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_2_vcpath_dfx_last_vld_ld_op_dev_sts( + unsigned int uvcpath_dfx_last_vld_ld_op_dev_sts); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_2_vcpath_dfx_last_vld_ld_op_cur_st( + unsigned int uvcpath_dfx_last_vld_ld_op_cur_st); +int iSetVIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_2_vcpath_dfx_last_vld_ld_op_nxt_st( + unsigned int uvcpath_dfx_last_vld_ld_op_nxt_st); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_1_vcpath_dfx_last_vld_st_op_funcid( + unsigned int uvcpath_dfx_last_vld_st_op_funcid); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_1_vcpath_dfx_last_vld_st_op_bar_hit( + unsigned int uvcpath_dfx_last_vld_st_op_bar_hit); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_1_vcpath_dfx_last_vld_st_op_a( + unsigned int uvcpath_dfx_last_vld_st_op_a); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_1_vcpath_dfx_last_vld_st_op_ofset( + unsigned int uvcpath_dfx_last_vld_st_op_ofset); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_1_vcpath_dfx_last_vld_st_op_dwbe( + unsigned int uvcpath_dfx_last_vld_st_op_dwbe); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_2_vcpath_dfx_last_vld_st_op_cntx_vld( + unsigned int uvcpath_dfx_last_vld_st_op_cntx_vld); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_2_vcpath_dfx_last_vld_st_op_msix_en( + unsigned int uvcpath_dfx_last_vld_st_op_msix_en); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_2_vcpath_dfx_last_vld_st_op_dev_sts( + unsigned int uvcpath_dfx_last_vld_st_op_dev_sts); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_2_vcpath_dfx_last_vld_st_op_cur_st( + unsigned int uvcpath_dfx_last_vld_st_op_cur_st); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_2_vcpath_dfx_last_vld_st_op_nxt_st( + unsigned int uvcpath_dfx_last_vld_st_op_nxt_st); +int iSetVIRTIO_CPATH_LAST_VALID_STORE_OPERATION_3_vcpath_dfx_last_vld_st_op_wdata( + unsigned int uvcpath_dfx_last_vld_st_op_wdata); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_vcpath_dfx_last_invld_ld_op_funcid( + unsigned int uvcpath_dfx_last_invld_ld_op_funcid); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_vcpath_dfx_last_invld_ld_op_bar_hit( + unsigned int uvcpath_dfx_last_invld_ld_op_bar_hit); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_vcpath_dfx_last_invld_ld_op_a( + unsigned int uvcpath_dfx_last_invld_ld_op_a); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_vcpath_dfx_last_invld_ld_op_ofset( + unsigned int uvcpath_dfx_last_invld_ld_op_ofset); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_vcpath_dfx_last_invld_ld_op_size( + unsigned int uvcpath_dfx_last_invld_ld_op_size); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_vcpath_dfx_last_invld_ld_op_dwbe( + unsigned int uvcpath_dfx_last_invld_ld_op_dwbe); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_2_vcpath_dfx_last_invld_ld_op_cntx_vld( + unsigned int uvcpath_dfx_last_invld_ld_op_cntx_vld); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_2_vcpath_dfx_last_invld_ld_op_msix_en( + unsigned int uvcpath_dfx_last_invld_ld_op_msix_en); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_2_vcpath_dfx_last_invld_ld_op_dev_sts( + unsigned int uvcpath_dfx_last_invld_ld_op_dev_sts); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_2_vcpath_dfx_last_invld_ld_op_cur_st( + unsigned int uvcpath_dfx_last_invld_ld_op_cur_st); +int iSetVIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_2_vcpath_dfx_last_invld_ld_op_nxt_st( + unsigned int uvcpath_dfx_last_invld_ld_op_nxt_st); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_vcpath_dfx_last_invld_st_op_funcid( + unsigned int uvcpath_dfx_last_invld_st_op_funcid); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_vcpath_dfx_last_invld_st_op_bar_hit( + unsigned int uvcpath_dfx_last_invld_st_op_bar_hit); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_vcpath_dfx_last_invld_st_op_a( + unsigned int uvcpath_dfx_last_invld_st_op_a); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_vcpath_dfx_last_invld_st_op_ofset( + unsigned int uvcpath_dfx_last_invld_st_op_ofset); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_vcpath_dfx_last_invld_st_op_size( + unsigned int uvcpath_dfx_last_invld_st_op_size); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_vcpath_dfx_last_invld_st_op_dwbe( + unsigned int uvcpath_dfx_last_invld_st_op_dwbe); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_2_vcpath_dfx_last_invld_st_op_cntx_vld( + unsigned int uvcpath_dfx_last_invld_st_op_cntx_vld); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_2_vcpath_dfx_last_invld_st_op_msix_en( + unsigned int uvcpath_dfx_last_invld_st_op_msix_en); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_2_vcpath_dfx_last_invld_st_op_dev_sts( + unsigned int uvcpath_dfx_last_invld_st_op_dev_sts); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_2_vcpath_dfx_last_invld_st_op_cur_st( + unsigned int uvcpath_dfx_last_invld_st_op_cur_st); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_2_vcpath_dfx_last_invld_st_op_nxt_st( + unsigned int uvcpath_dfx_last_invld_st_op_nxt_st); +int iSetVIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_3_vcpath_dfx_last_invld_st_op_wdata( + unsigned int uvcpath_dfx_last_invld_st_op_wdata); +int iSetVIRTIO_CPATH_INT_EN_vcpath_aeqe_pending_int_en(unsigned int uvcpath_aeqe_pending_int_en); +int iSetVIRTIO_CPATH_INT_EN_vcpath_invld_api_int_en(unsigned int uvcpath_invld_api_int_en); +int iSetVDB_API_CNT_vdb_api_without_ack_cnt(unsigned int uvdb_api_without_ack_cnt); +int iSetVDB_API_CNT_vdb_api_with_ack_cnt(unsigned int uvdb_api_with_ack_cnt); +int iSetVSDB_PI_INVALID_INFO_vsdb_pi_invalid_glb_vqn(unsigned int uvsdb_pi_invalid_glb_vqn); +int iSetVSDB_PI_INVALID_INFO_vsdb_pi_invalid_func_id(unsigned int uvsdb_pi_invalid_func_id); +int iSetVSDB_PI_INVALID_INFO_vsdb_pi_invalid_cnt(unsigned int uvsdb_pi_invalid_cnt); +int iSetVSDB_PI_INVALID_INFO_vsdb_pi_invalid_int_en(unsigned int uvsdb_pi_invalid_int_en); +int iSetVSAVIDX_PI_INVALID_INFO_vsavidx_pi_invalid_glb_vqn(unsigned int uvsavidx_pi_invalid_glb_vqn); +int iSetVSAVIDX_PI_INVALID_INFO_vsavidx_pi_invalid_func_id(unsigned int uvsavidx_pi_invalid_func_id); +int iSetVSAVIDX_PI_INVALID_INFO_vsavidx_pi_invalid_cnt(unsigned int uvsavidx_pi_invalid_cnt); +int iSetVSAVIDX_PI_INVALID_INFO_vsavidx_pi_invalid_int_en(unsigned int uvsavidx_pi_invalid_int_en); +int iSetVSAVRING_IDX_INVALID_INFO_vsavring_idx_invalid_glb_vqn(unsigned int uvsavring_idx_invalid_glb_vqn); +int iSetVSAVRING_IDX_INVALID_INFO_vsavring_idx_invalid_func_id(unsigned int uvsavring_idx_invalid_func_id); +int iSetVSAVRING_IDX_INVALID_INFO_vsavring_idx_invalid_cnt(unsigned int uvsavring_idx_invalid_cnt); +int iSetVSAVRING_IDX_INVALID_INFO_vsavring_idx_invalid_int_en(unsigned int uvsavring_idx_invalid_int_en); +int iSetVSAVRING_IDX_INVALID_DAT_vsavring_idx_invalid_dat(unsigned int uvsavring_idx_invalid_dat); +int iSetVSAVRING_IDX_INVALID_DAT_vsavring_idx_invalid_entry(unsigned int uvsavring_idx_invalid_entry); +int iSetVS1ST_LEN_ZERO_INFO_vs1st_len_zero_glb_vqn(unsigned int uvs1st_len_zero_glb_vqn); +int iSetVS1ST_LEN_ZERO_INFO_vs1st_len_zero_func_id(unsigned int uvs1st_len_zero_func_id); +int iSetVS1ST_LEN_ZERO_INFO_vs1st_len_zero_cnt(unsigned int uvs1st_len_zero_cnt); +int iSetVS1ST_LEN_ZERO_INFO_vs1st_len_zero_int_en(unsigned int uvs1st_len_zero_int_en); +int iSetVS1ST_NEXT_INVALID_INFO_vs1st_next_invalid_glb_vqn(unsigned int uvs1st_next_invalid_glb_vqn); +int iSetVS1ST_NEXT_INVALID_INFO_vs1st_next_invalid_func_id(unsigned int uvs1st_next_invalid_func_id); +int iSetVS1ST_NEXT_INVALID_INFO_vs1st_next_invalid_cnt(unsigned int uvs1st_next_invalid_cnt); +int iSetVS1ST_NEXT_INVALID_INFO_vs1st_next_invalid_int_en(unsigned int uvs1st_next_invalid_int_en); +int iSetVS1ST_FLAG_INVALID_INFO_vs1st_flag_invalid_glb_vqn(unsigned int uvs1st_flag_invalid_glb_vqn); +int iSetVS1ST_FLAG_INVALID_INFO_vs1st_flag_invalid_func_id(unsigned int uvs1st_flag_invalid_func_id); +int iSetVS1ST_FLAG_INVALID_INFO_vs1st_flag_invalid_cnt(unsigned int uvs1st_flag_invalid_cnt); +int iSetVS1ST_FLAG_INVALID_INFO_vs1st_flag_invalid_int_en(unsigned int uvs1st_flag_invalid_int_en); +int iSetVSLEFT_LEN_ZERO_INFO_vsleft_len_zero_glb_vqn(unsigned int uvsleft_len_zero_glb_vqn); +int iSetVSLEFT_LEN_ZERO_INFO_vsleft_len_zero_func_id(unsigned int uvsleft_len_zero_func_id); +int iSetVSLEFT_LEN_ZERO_INFO_vsleft_len_zero_cnt(unsigned int uvsleft_len_zero_cnt); +int iSetVSLEFT_LEN_ZERO_INFO_vsleft_len_zero_int_en(unsigned int uvsleft_len_zero_int_en); +int iSetVSLEFT_NEXT_INVALID_CNT_vsleft_next_invalid_glb_vqn(unsigned int uvsleft_next_invalid_glb_vqn); +int iSetVSLEFT_NEXT_INVALID_CNT_vsleft_next_invalid_func_id(unsigned int uvsleft_next_invalid_func_id); +int iSetVSLEFT_NEXT_INVALID_CNT_vsleft_next_invalid_cnt(unsigned int uvsleft_next_invalid_cnt); +int iSetVSLEFT_NEXT_INVALID_CNT_vsleft_next_invalid_int_en(unsigned int uvsleft_next_invalid_int_en); +int iSetVSLEFT_FLAG_INVALID_CNT_vsleft_flag_invalid_glb_vqn(unsigned int uvsleft_flag_invalid_glb_vqn); +int iSetVSLEFT_FLAG_INVALID_CNT_vsleft_flag_invalid_func_id(unsigned int uvsleft_flag_invalid_func_id); +int iSetVSLEFT_FLAG_INVALID_CNT_vsleft_flag_invalid_cnt(unsigned int uvsleft_flag_invalid_cnt); +int iSetVSLEFT_FLAG_INVALID_CNT_vsleft_flag_invalid_int_en(unsigned int uvsleft_flag_invalid_int_en); +int iSetVSIDESC_LEN_ZERO_INFO_vsidesc_len_zero_glb_vqn(unsigned int uvsidesc_len_zero_glb_vqn); +int iSetVSIDESC_LEN_ZERO_INFO_vsidesc_len_zero_func_id(unsigned int uvsidesc_len_zero_func_id); +int iSetVSIDESC_LEN_ZERO_INFO_vsidesc_len_zero_cnt(unsigned int uvsidesc_len_zero_cnt); +int iSetVSIDESC_LEN_ZERO_INFO_vsidesc_len_zero_int_en(unsigned int uvsidesc_len_zero_int_en); +int iSetVSIDESC_NEXT_INVALID_CNT_vsidesc_next_invalid_glb_vqn(unsigned int uvsidesc_next_invalid_glb_vqn); +int iSetVSIDESC_NEXT_INVALID_CNT_vsidesc_next_invalid_func_id(unsigned int uvsidesc_next_invalid_func_id); +int iSetVSIDESC_NEXT_INVALID_CNT_vsidesc_next_invalid_cnt(unsigned int uvsidesc_next_invalid_cnt); +int iSetVSIDESC_NEXT_INVALID_CNT_vsidesc_next_invalid_int_en(unsigned int uvsidesc_next_invalid_int_en); +int iSetVSIDESC_FLAG_INVALID_CNT_vsidesc_flag_invalid_glb_vqn(unsigned int uvsidesc_flag_invalid_glb_vqn); +int iSetVSIDESC_FLAG_INVALID_CNT_vsidesc_flag_invalid_func_id(unsigned int uvsidesc_flag_invalid_func_id); +int iSetVSIDESC_FLAG_INVALID_CNT_vsidesc_flag_invalid_cnt(unsigned int uvsidesc_flag_invalid_cnt); +int iSetVSIDESC_FLAG_INVALID_CNT_vsidesc_flag_invalid_int_en(unsigned int uvsidesc_flag_invalid_int_en); +int iSetVIRTIO_PACKED_DSC_INVLD_DESC_1_vpckd_dfx_last_invld_dsc_vqn(unsigned int uvpckd_dfx_last_invld_dsc_vqn); +int iSetVIRTIO_PACKED_DSC_INVLD_DESC_1_vpckd_dfx_last_invld_dsc_funcid(unsigned int uvpckd_dfx_last_invld_dsc_funcid); +int iSetVIRTIO_PACKED_DSC_INVLD_DESC_1_vpckd_dfx_invld_dsc_cnt(unsigned int uvpckd_dfx_invld_dsc_cnt); +int iSetVIRTIO_PACKED_DSC_INVLD_DESC_1_vpckd_dfx_invld_dsc_int_en(unsigned int uvpckd_dfx_invld_dsc_int_en); +int iSetVIRTIO_PACKED_DSC_INVLD_DESC_2_vpckd_dfx_last_invld_dsc_data(unsigned int uvpckd_dfx_last_invld_dsc_data); +int iSetVIRTIO_PACKED_DSC_INVLD_IDESC_1_vpckd_dfx_last_invld_idsc_vqn(unsigned int uvpckd_dfx_last_invld_idsc_vqn); +int iSetVIRTIO_PACKED_DSC_INVLD_IDESC_1_vpckd_dfx_last_invld_idsc_funcid( + unsigned int uvpckd_dfx_last_invld_idsc_funcid); +int iSetVIRTIO_PACKED_DSC_INVLD_IDESC_1_vpckd_dfx_invld_idsc_cnt(unsigned int uvpckd_dfx_invld_idsc_cnt); +int iSetVIRTIO_PACKED_DSC_INVLD_IDESC_1_vpckd_dfx_invld_idsc_int_en(unsigned int uvpckd_dfx_invld_idsc_int_en); +int iSetVIRTIO_PACKED_DSC_INVLD_IDESC_2_vpckd_dfx_last_invld_idsc_data(unsigned int uvpckd_dfx_last_invld_idsc_data); +int iSetVPIDESC_DFX_DESC_LEN_ERR_vpidesc_dfx_desc_len_err_st(unsigned int uvpidesc_dfx_desc_len_err_st); +int iSetVPIDESC_DFX_DESC_LEN_ERR_vpidesc_dfx_desc_len_err_cnt(unsigned int uvpidesc_dfx_desc_len_err_cnt); +int iSetVPIDESC_DFX_DESC_LEN_ERR_vpidesc_len_zero_int_en(unsigned int uvpidesc_len_zero_int_en); +int iSetVPBFHD_DFX_HOST_DESC_ERR_CNT_vpbfhd_dfx_host_desc_err_st(unsigned int uvpbfhd_dfx_host_desc_err_st); +int iSetVPBFHD_DFX_HOST_DESC_ERR_CNT_vpbfhd_dfx_host_desc_err_cnt(unsigned int uvpbfhd_dfx_host_desc_err_cnt); +int iSetFLR_TIMEOUT_CFG_virtio_engine_flr_timeout_th(unsigned int uvirtio_engine_flr_timeout_th); +int iSetFLR_AEQE_CFG_virtio_engine_flr_dev_sts_template(unsigned int uvirtio_engine_flr_dev_sts_template); +int iSetFLR_AEQE_CFG_virtio_engine_aeqe_credit_th(unsigned int uvirtio_engine_aeqe_credit_th); +int iSetFLR_AEQE_CFG_virtio_engine_flr_aeqe_credit_th(unsigned int uvirtio_engine_flr_aeqe_credit_th); +int iSetFLR_STATUS_virtio_engine_flr_func_idx(unsigned int uvirtio_engine_flr_func_idx); +int iSetFLR_STATUS_virtio_engine_flr_ssb_done(unsigned int uvirtio_engine_flr_ssb_done); +int iSetFLR_STATUS_virtio_engine_flr_dsb_done(unsigned int uvirtio_engine_flr_dsb_done); +int iSetFLR_STATUS_virtio_engine_flr_proc_done(unsigned int uvirtio_engine_flr_proc_done); +int iSetFLR_STATUS_virtio_engine_flr_icsr_done(unsigned int uvirtio_engine_flr_icsr_done); +int iSetFLR_STATUS_virtio_engine_flr_irqst_done(unsigned int uvirtio_engine_flr_irqst_done); +int iSetFLR_STATUS_virtio_engine_flr_ecsr_done(unsigned int uvirtio_engine_flr_ecsr_done); +int iSetFLR_STATUS_virtio_engine_flr_ersp_done(unsigned int uvirtio_engine_flr_ersp_done); +int iSetFLR_STATUS_virtio_engine_flr_proc_busy(unsigned int uvirtio_engine_flr_proc_busy); +int iSetFLR_STATUS_virtio_engine_flr_ssb_busy(unsigned int uvirtio_engine_flr_ssb_busy); +int iSetFLR_STATUS_virtio_engine_flr_dsb_busy(unsigned int uvirtio_engine_flr_dsb_busy); +int iSetFLR_STATUS_virtio_engine_flr_icsr_busy(unsigned int uvirtio_engine_flr_icsr_busy); +int iSetFLR_STATUS_virtio_engine_flr_irqst_busy(unsigned int uvirtio_engine_flr_irqst_busy); +int iSetFLR_STATUS_virtio_engine_flr_ecsr_busy(unsigned int uvirtio_engine_flr_ecsr_busy); +int iSetFLR_STATUS_virtio_engine_flr_ersp_busy(unsigned int uvirtio_engine_flr_ersp_busy); +int iSetFLR_STATUS_virtio_engine_flr_rst_adminq_en(unsigned int uvirtio_engine_flr_rst_adminq_en); +int iSetFLR_STATUS_virtio_engine_flr_type(unsigned int uvirtio_engine_flr_type); +int iSetFLR_STATUS_virtio_engine_flr_rdy_en(unsigned int uvirtio_engine_flr_rdy_en); +int iSetFLR_STATUS_virtio_engine_flr_sts(unsigned int uvirtio_engine_flr_sts); +int iSetFLR_STATUS_virtio_engine_flr_req(unsigned int uvirtio_engine_flr_req); +int iSetPRE_FLR_DFX_API_CNT_pflr_dfx_api_cnt(unsigned int upflr_dfx_api_cnt); +int iSetPRE_FLR_DFX_CUR_ST_pflr_dfx_cur_st(unsigned int upflr_dfx_cur_st); +int iSetPRE_FLR_DFX_AEQE_pflr_dfx_aeqe_credit_uf_func_id(unsigned int upflr_dfx_aeqe_credit_uf_func_id); +int iSetPRE_FLR_DFX_AEQE_pflr_dfx_aeqe_credit_uf_flag(unsigned int upflr_dfx_aeqe_credit_uf_flag); +int iSetPRE_FLR_DFX_AEQE_pflr_dfx_aeqe_cnt(unsigned int upflr_dfx_aeqe_cnt); +int iSetFLR_DFX_API_CNT_flr_dfx_flr_cnt(unsigned int uflr_dfx_flr_cnt); +int iSetFLR_DFX_CUR_ST_flr_dfx_cur_st(unsigned int uflr_dfx_cur_st); +int iSetFLR_DFX_CUR_ST_flr_timeout_int_en(unsigned int uflr_timeout_int_en); +int iSetFLR_DFX_CUR_ST_flr_done_with_err_int_en(unsigned int uflr_done_with_err_int_en); +int iSetFLR_DFX_CUR_ST_flr_done_without_err_int_en(unsigned int uflr_done_without_err_int_en); +int iSetCACHE_FLUSH_MEM_INDEX_H_cache_flush_mem_index_cid(unsigned int ucache_flush_mem_index_cid); +int iSetCACHE_BANK_CFG_cache_out_bank_cfg(unsigned int ucache_out_bank_cfg); +int iSetCACHE_FLUSH_DFX_API_CNT_cache_flush_dfx_api_cnt(unsigned int ucache_flush_dfx_api_cnt); +int iSetCACHE_OUT_DFX_API_CNT_cache_out_dfx_api_cnt(unsigned int ucache_out_dfx_api_cnt); +int iSetCACHE_OUT_DFX_ERR_CNT_cache_out_dfx_err_cnt(unsigned int ucache_out_dfx_err_cnt); +int iSetCACHE_OUT_DFX_ERR_CNT_cache_out_err_int_en(unsigned int ucache_out_err_int_en); +int iSetCACHE_OUT_DFX_CID_ERR_ST_cache_out_dfx_cid_err_st(unsigned int ucache_out_dfx_cid_err_st); +int iSetCACHE_OUT_DFX_BANK_CFG_ERR_FLAG_cache_out_dfx_bank_cfg_err_flag(unsigned int ucache_out_dfx_bank_cfg_err_flag); +int iSetCACHE_OUT_DFX_MC_MAX_NUM_ERR_FLAG_cache_out_dfx_mc_max_num_err_flag( + unsigned int ucache_out_dfx_mc_max_num_err_flag); +int iSetCACHE_OUT_DFX_CUR_ST_cache_out_dfx_cur_st(unsigned int ucache_out_dfx_cur_st); +int iSetCACHE_INVLD_DFX_API_CNT_cache_invld_dfx_api_cnt(unsigned int ucache_invld_dfx_api_cnt); +int iSetCACHE_INVLD_DFX_OP_EXT_ERR_CNT_cache_invld_dfx_op_ext_err_cnt(unsigned int ucache_invld_dfx_op_ext_err_cnt); +int iSetCACHE_INVLD_DFX_OP_EXT_ERR_CNT_cache_invld_op_ext_err_int_en(unsigned int ucache_invld_op_ext_err_int_en); +int iSetCACHE_INVLD_DFX_OP_EXT_cache_invld_dfx_op_ext_st(unsigned int ucache_invld_dfx_op_ext_st); +int iSetCACHE_INVLD_DFX_CUR_ST_cache_invld_dfx_cur_st(unsigned int ucache_invld_dfx_cur_st); + + +#endif // VIRTIO_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/virtio_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/virtio_reg_offset.h new file mode 100644 index 000000000..3fb510f5b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/virtio_reg_offset.h @@ -0,0 +1,275 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : virtio_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2018/12/05 +// Description : +// Others : Generated automatically by nManager V5.1 +// History : +// ****************************************************************************** + +#ifndef VIRTIO_REG_OFFSET_H +#define VIRTIO_REG_OFFSET_H + +/* VIRTIO_CSR Base address of Module's Register */ +#define CSR_VIRTIO_CSR_BASE (0x1000) + +/* **************************************************************************** */ +/* VIRTIO_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_VIRTIO_CSR_RSVD0_REG (CSR_VIRTIO_CSR_BASE + 0x0) /* 保留 */ +#define CSR_VIRTIO_CSR_RSVD1_REG (CSR_VIRTIO_CSR_BASE + 0x4) /* 保留 */ +#define CSR_VIRTIO_CSR_RSVD2_REG (CSR_VIRTIO_CSR_BASE + 0x8) /* 保留 */ +#define CSR_VIRTIO_CSR_RSVD3_REG (CSR_VIRTIO_CSR_BASE + 0xC) /* 保留 */ +#define CSR_VIRTIO_CSR_INT_VECTOR_REG (CSR_VIRTIO_CSR_BASE + 0x10) /* 中断向量 */ +#define CSR_VIRTIO_CSR_INT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x14) /* 中断状态 */ +#define CSR_VIRTIO_CSR_INT_EN_REG (CSR_VIRTIO_CSR_BASE + 0x18) /* 中断使能 */ +#define CSR_VIRTIO_CSR_INT0_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x20) /* 中断0 */ +#define CSR_VIRTIO_CSR_INT1_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x24) /* 中断1 */ +#define CSR_VIRTIO_CSR_INT2_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x28) /* 中断2 */ +#define CSR_VIRTIO_CSR_INT3_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x2C) /* 中断3 */ +#define CSR_VIRTIO_CSR_INT4_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x30) /* 中断4 */ +#define CSR_VIRTIO_CSR_INT5_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x34) /* 中断5 */ +#define CSR_VIRTIO_CSR_INT6_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x38) /* 中断6 */ +#define CSR_VIRTIO_CSR_INT7_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x3C) /* 中断7 */ +#define CSR_VIRTIO_CSR_INT8_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x40) /* 中断8 */ +#define CSR_VIRTIO_CSR_INT9_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x44) /* 中断9 */ +#define CSR_VIRTIO_CSR_INT10_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x48) /* 中断10 */ +#define CSR_VIRTIO_CSR_INT11_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x4C) /* 中断11 */ +#define CSR_VIRTIO_CSR_INT12_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x50) /* 中断12 */ +#define CSR_VIRTIO_CSR_INT13_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x54) /* 中断13 */ +#define CSR_VIRTIO_CSR_INT14_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x58) /* 中断14 */ +#define CSR_VIRTIO_CSR_INT15_STICKY_REG (CSR_VIRTIO_CSR_BASE + 0x5C) /* 中断15 */ +#define CSR_VIRTIO_CSR_COMMON_MEM_INIT_REG (CSR_VIRTIO_CSR_BASE + 0x60) /* Memory Initi */ +#define CSR_VIRTIO_CSR_COMMON_MEM_INIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x64) /* Memory Initi */ +#define CSR_VIRTIO_CSR_IIF_IRSP_MEM_H_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x70) /* ECC */ +#define CSR_VIRTIO_CSR_IIF_IRSP_MEM_L_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x74) /* ECC */ +#define CSR_VIRTIO_CSR_ERSP_MEM_H_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x78) /* ECC */ +#define CSR_VIRTIO_CSR_ERSP_MEM_L_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x7C) /* ECC */ +#define CSR_VIRTIO_CSR_ERQST_FIFO_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x80) /* ECC */ +#define CSR_VIRTIO_CSR_ECSR_FIFO_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x84) /* ECC */ +#define CSR_VIRTIO_CSR_SSB_MEM_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x88) /* ECC */ +#define CSR_VIRTIO_CSR_DSB_MEM_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x8C) /* ECC */ +#define CSR_VIRTIO_CSR_HOST_ID_TABLE_MEM_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x90) /* ECC */ +#define CSR_VIRTIO_CSR_DEV_ATTRI_TABLE_MEM_ECC_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x94) /* ECC */ +#define CSR_VIRTIO_CSR_TPRAM_WR_CTRL_REG (CSR_VIRTIO_CSR_BASE + 0xA0) /* Memory CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_31_0_REG (CSR_VIRTIO_CSR_BASE + 0xB0) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_63_32_REG (CSR_VIRTIO_CSR_BASE + 0xB4) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_95_64_REG (CSR_VIRTIO_CSR_BASE + 0xB8) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_127_96_REG (CSR_VIRTIO_CSR_BASE + 0xBC) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_159_128_REG (CSR_VIRTIO_CSR_BASE + 0xC0) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_191_160_REG (CSR_VIRTIO_CSR_BASE + 0xC4) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_223_192_REG (CSR_VIRTIO_CSR_BASE + 0xC8) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_255_224_REG (CSR_VIRTIO_CSR_BASE + 0xCC) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_287_256_REG (CSR_VIRTIO_CSR_BASE + 0xD0) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_319_288_REG (CSR_VIRTIO_CSR_BASE + 0xD4) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_WEN_DATA_335_320_REG (CSR_VIRTIO_CSR_BASE + 0xD8) /* CFG */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_31_0_REG (CSR_VIRTIO_CSR_BASE + 0xE0) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_63_32_REG (CSR_VIRTIO_CSR_BASE + 0xE4) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_95_64_REG (CSR_VIRTIO_CSR_BASE + 0xE8) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_127_96_REG (CSR_VIRTIO_CSR_BASE + 0xEC) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_159_128_REG (CSR_VIRTIO_CSR_BASE + 0xF0) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_191_160_REG (CSR_VIRTIO_CSR_BASE + 0xF4) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_223_192_REG (CSR_VIRTIO_CSR_BASE + 0xF8) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_255_224_REG (CSR_VIRTIO_CSR_BASE + 0xFC) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_287_256_REG (CSR_VIRTIO_CSR_BASE + 0x100) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_319_288_REG (CSR_VIRTIO_CSR_BASE + 0x104) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_351_320_REG (CSR_VIRTIO_CSR_BASE + 0x108) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_383_352_REG (CSR_VIRTIO_CSR_BASE + 0x10C) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_415_384_REG (CSR_VIRTIO_CSR_BASE + 0x110) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_447_416_REG (CSR_VIRTIO_CSR_BASE + 0x114) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_479_448_REG (CSR_VIRTIO_CSR_BASE + 0x118) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_511_480_REG (CSR_VIRTIO_CSR_BASE + 0x11C) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_543_512_REG (CSR_VIRTIO_CSR_BASE + 0x120) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_575_544_REG (CSR_VIRTIO_CSR_BASE + 0x124) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_607_576_REG (CSR_VIRTIO_CSR_BASE + 0x128) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_639_608_REG (CSR_VIRTIO_CSR_BASE + 0x12C) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_671_640_REG (CSR_VIRTIO_CSR_BASE + 0x130) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_703_672_REG (CSR_VIRTIO_CSR_BASE + 0x134) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_735_704_REG (CSR_VIRTIO_CSR_BASE + 0x138) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_767_736_REG (CSR_VIRTIO_CSR_BASE + 0x13C) /* STATUS */ +#define CSR_VIRTIO_CSR_TPRAM_WR_REN_DATA_773_768_REG (CSR_VIRTIO_CSR_BASE + 0x140) /* STATUS */ +#define CSR_VIRTIO_CSR_LOAD_BALANCE_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x150) /* CFG */ +#define CSR_VIRTIO_CSR_FLEX_Q_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x154) /* CFG */ +#define CSR_VIRTIO_CSR_VQ_CNTX_SIZE_REG (CSR_VIRTIO_CSR_BASE + 0x200) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_REGION_OFF_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x204) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_LOC_SGL_SIZE_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x208) +#define CSR_VIRTIO_CSR_VIRTIO_LOC_IDESC_SIZE_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x20C) +#define CSR_VIRTIO_CSR_VIRTIO_DMA_WAIT_MAX_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x210) +#define CSR_VIRTIO_CSR_VIRTIO_PREFETCH_TH_REG (CSR_VIRTIO_CSR_BASE + 0x214) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_MAX_OUTSTAND_TH_REG (CSR_VIRTIO_CSR_BASE + 0x218) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_SPLIT_CHAIN_SPECULATE_TH_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x21C) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_SQE_DMA_TEMPLATE_DW0_REG (CSR_VIRTIO_CSR_BASE + 0x280) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_SQE_DMA_TEMPLATE_DW1_REG (CSR_VIRTIO_CSR_BASE + 0x284) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_SQE_DMA_TEMPLATE_DW2_REG (CSR_VIRTIO_CSR_BASE + 0x288) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_SQE_DMA_TEMPLATE_DW3_REG (CSR_VIRTIO_CSR_BASE + 0x28C) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_RQE_DMA_TEMPLATE_DW0_REG (CSR_VIRTIO_CSR_BASE + 0x290) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_RQE_DMA_TEMPLATE_DW1_REG (CSR_VIRTIO_CSR_BASE + 0x294) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_RQE_DMA_TEMPLATE_DW2_REG (CSR_VIRTIO_CSR_BASE + 0x298) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_RQE_DMA_TEMPLATE_DW3_REG (CSR_VIRTIO_CSR_BASE + 0x29C) /* CFG */ +#define CSR_VIRTIO_CSR_NVME_QP_CNTX_CFG0_REG (CSR_VIRTIO_CSR_BASE + 0x300) +#define CSR_VIRTIO_CSR_NVME_QP_CNTX_CFG1_REG (CSR_VIRTIO_CSR_BASE + 0x304) +#define CSR_VIRTIO_CSR_VIRTIO_ENGINE_NVME_CNTX_OFFSET_REG (CSR_VIRTIO_CSR_BASE + 0x308) /* CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_ENGINE_VIRTIO_CNTX_OFFSET_REG (CSR_VIRTIO_CSR_BASE + 0x30C) /* CFG */ +#define CSR_VIRTIO_CSR_NVME_DMA_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x310) +#define CSR_VIRTIO_CSR_NVME_DMA_TEMPLATE_DW0_REG (CSR_VIRTIO_CSR_BASE + 0x314) +#define CSR_VIRTIO_CSR_NVME_DMA_TEMPLATE_DW1_REG (CSR_VIRTIO_CSR_BASE + 0x318) +#define CSR_VIRTIO_CSR_NVME_DMA_TEMPLATE_DW2_REG (CSR_VIRTIO_CSR_BASE + 0x31C) +#define CSR_VIRTIO_CSR_IRQST_CREDIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x400) +#define CSR_VIRTIO_CSR_IRQST_FIFO_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x404) /* DFX */ +#define CSR_VIRTIO_CSR_IRQST_STATISTIC_API_REG (CSR_VIRTIO_CSR_BASE + 0x408) /* DFX_CFG */ +#define CSR_VIRTIO_CSR_IRQST_API_WITH_A_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x40C) /* DFX */ +#define CSR_VIRTIO_CSR_IRQST_API_WITHOUT_A_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x410) /* DFX */ +#define CSR_VIRTIO_CSR_IRQST_API_INVALID_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x414) /* DFX */ +#define CSR_VIRTIO_CSR_IRQST_INT_EN_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x418) /* CFG */ +#define CSR_VIRTIO_CSR_IRSP_CREDIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x420) /* DFX */ +#define CSR_VIRTIO_CSR_IRSP_FIFO_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x424) /* DFX */ +#define CSR_VIRTIO_CSR_IRSP_API_STATISTIC_REG (CSR_VIRTIO_CSR_BASE + 0x428) /* DFX */ +#define CSR_VIRTIO_CSR_IRSP_INVALID_FLIT_REG (CSR_VIRTIO_CSR_BASE + 0x42C) /* DFX */ +#define CSR_VIRTIO_CSR_IRSP_INT_EN_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x430) /* CFG */ +#define CSR_VIRTIO_CSR_ICSR_CREDIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x440) /* DFX */ +#define CSR_VIRTIO_CSR_ICSR_FIFO_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x444) /* DFX */ +#define CSR_VIRTIO_CSR_ICSR_API_WITH_A_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x448) /* DFX */ +#define CSR_VIRTIO_CSR_ICSR_API_WITHOUT_A_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x44C) /* DFX */ +#define CSR_VIRTIO_CSR_ICSR_INVALID_API_REG (CSR_VIRTIO_CSR_BASE + 0x450) /* DFX */ +#define CSR_VIRTIO_CSR_ICSR_CPATH_TIMEOUT_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x454) /* CFG */ +#define CSR_VIRTIO_CSR_ICSR_CPATH_TIMEOUT_DROP_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x458) /* DFX */ +#define CSR_VIRTIO_CSR_ICSR_INT_EN_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x45C) /* CFG */ +#define CSR_VIRTIO_CSR_ISCH_WEIGHT_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x460) +#define CSR_VIRTIO_CSR_ERQST_CREDIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x470) /* DFX */ +#define CSR_VIRTIO_CSR_ERQST_DMA_TEMPLATE_REG (CSR_VIRTIO_CSR_BASE + 0x474) /* CFG */ +#define CSR_VIRTIO_CSR_ERQST_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x478) /* DFX */ +#define CSR_VIRTIO_CSR_ERQST_FIFO_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x47C) /* DFX */ +#define CSR_VIRTIO_CSR_ERSP_CREDIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x490) /* DFX_CFG */ +#define CSR_VIRTIO_CSR_ERSP_FIFO_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x494) /* DFX */ +#define CSR_VIRTIO_CSR_ERSP_FLIT_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x498) /* DFX */ +#define CSR_VIRTIO_CSR_ERSP_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x49C) /* DFX */ +#define CSR_VIRTIO_CSR_ECSR_CREDIT_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x4B0) /* DFX */ +#define CSR_VIRTIO_CSR_ECSR_FIFO_CFG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x4B4) /* DFX */ +#define CSR_VIRTIO_CSR_ECSR_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x4B8) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_SMLC_OUTSTANDING_THREAD_SCAN_REG (CSR_VIRTIO_CSR_BASE + 0x4BC) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_SMLC_DELAY_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x4C0) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_SMLC_DELAY_TIMER_REG (CSR_VIRTIO_CSR_BASE + 0x4C4) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_SMLC_DELAY_MIN_REG (CSR_VIRTIO_CSR_BASE + 0x4C8) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_SMLC_DELAY_MAX_REG (CSR_VIRTIO_CSR_BASE + 0x4CC) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_FUN_MEM_MODE_BADDR_REG (CSR_VIRTIO_CSR_BASE + 0x4D0) /* CFG */ +#define CSR_VIRTIO_CSR_SIF_VQ_MEM_MODE_BADDR_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x4D4) /* CFG */ +#define CSR_VIRTIO_CSR_SIF_INSTANCE_ID_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x4D8) /* CFG */ +#define CSR_VIRTIO_CSR_SIF_SMLC_IF_CFG_0_REG (CSR_VIRTIO_CSR_BASE + 0x4DC) /* CFG */ +#define CSR_VIRTIO_CSR_SIF_SMLC_IF_CFG_1_REG (CSR_VIRTIO_CSR_BASE + 0x4E0) /* CFG */ +#define CSR_VIRTIO_CSR_SIF_SMLC_IF_CFG_2_REG (CSR_VIRTIO_CSR_BASE + 0x4E4) /* CFG */ +#define CSR_VIRTIO_CSR_SIF_SMLC_IF_CFG_3_REG (CSR_VIRTIO_CSR_BASE + 0x4E8) /* CFG */ +#define CSR_VIRTIO_CSR_HOST_PPF_CFG_0_REG (CSR_VIRTIO_CSR_BASE + 0x4EC) +#define CSR_VIRTIO_CSR_HOST_PPF_CFG_1_REG (CSR_VIRTIO_CSR_BASE + 0x4F0) +#define CSR_VIRTIO_CSR_SIF_SMLC_THREAD_TIMEOUT_STATUS_0_REG (CSR_VIRTIO_CSR_BASE + 0x4F4) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_SMLC_THREAD_TIMEOUT_STATUS_1_REG (CSR_VIRTIO_CSR_BASE + 0x4F8) /* DFX */ +#define CSR_VIRTIO_CSR_SIF_INT_EN_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x4FC) /* CFG */ +#define CSR_VIRTIO_CSR_STM_SHARE_THREAD_MAX_REG (CSR_VIRTIO_CSR_BASE + 0x500) /* CFG */ +#define CSR_VIRTIO_CSR_STM_CHANNEL_THREAD_TH_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x504) /* CFG */ +#define CSR_VIRTIO_CSR_STM_SHARE_THREAD_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x508) /* STATUS */ +#define CSR_VIRTIO_CSR_STM_CHANNEL_THREAD_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x50C) /* STATUS */ +#define CSR_VIRTIO_CSR_STM_FIFO0_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x510) /* STATUS */ +#define CSR_VIRTIO_CSR_STM_FIFO1_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x514) /* STATUS */ +#define CSR_VIRTIO_CSR_DTM_TAG_ALEMPTY_TH_REG (CSR_VIRTIO_CSR_BASE + 0x51C) /* CFG */ +#define CSR_VIRTIO_CSR_DTM_TAG_TH_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x520) /* CFG */ +#define CSR_VIRTIO_CSR_DTM_TAG_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0x524) /* STATUS */ +#define CSR_VIRTIO_CSR_DTM_DMA_OUTSTANDING_TAG_SCAN_REG (CSR_VIRTIO_CSR_BASE + 0x528) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_DELAY_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x52C) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_DELAY_TIMER_REG (CSR_VIRTIO_CSR_BASE + 0x530) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_DELAY_MIN_REG (CSR_VIRTIO_CSR_BASE + 0x534) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_DELAY_MAX_REG (CSR_VIRTIO_CSR_BASE + 0x538) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_TAG_TIMEOUT_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x53C) /* CFG */ +#define CSR_VIRTIO_CSR_DTM_DMA_TAG_TIMEOUT_STATUS_0_REG (CSR_VIRTIO_CSR_BASE + 0x540) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_TAG_TIMEOUT_STATUS_1_REG (CSR_VIRTIO_CSR_BASE + 0x544) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_TAG_TIMEOUT_STATUS_2_REG (CSR_VIRTIO_CSR_BASE + 0x548) /* DFX */ +#define CSR_VIRTIO_CSR_DTM_DMA_TAG_TIMEOUT_STATUS_3_REG (CSR_VIRTIO_CSR_BASE + 0x54C) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_TOTAL_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x800) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_INVALID_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x804) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_INVALID_LOAD_OPERATION_REG (CSR_VIRTIO_CSR_BASE + 0x808) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_INVALID_STORE_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x80C) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_INVALID_STORE_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x810) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_INVALID_STORE_OPERATION_3_REG (CSR_VIRTIO_CSR_BASE + 0x814) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_VALID_LOAD_OPERATION_REG (CSR_VIRTIO_CSR_BASE + 0x818) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_VALID_STORE_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x81C) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_VALID_STORE_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x820) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_LAST_VALID_STORE_OPERATION_3_REG (CSR_VIRTIO_CSR_BASE + 0x824) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_CPATH_INT_EN_REG (CSR_VIRTIO_CSR_BASE + 0x828) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_DPATH_LOAD_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x840) /* DFX */ +#define CSR_VIRTIO_CSR_NVME_DPATH_STORE_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x844) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DFX_FUNC_ID_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x860) /* DFX_CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_DFX_VQN_CFG_REG (CSR_VIRTIO_CSR_BASE + 0x864) /* DFX_CFG */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_TOTAL_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x880) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_ABNORMAL_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x884) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_INVLD_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x8B0) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x888) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_VALID_LOAD_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x88C) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_VALID_STORE_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x890) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_VALID_STORE_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x894) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_VALID_STORE_OPERATION_3_REG (CSR_VIRTIO_CSR_BASE + 0x898) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x89C) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_INVALID_LOAD_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x8A0) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x8A4) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x8A8) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_LAST_INVALID_STORE_OPERATION_3_REG (CSR_VIRTIO_CSR_BASE + 0x8AC) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_DPATH_INT_EN_REG (CSR_VIRTIO_CSR_BASE + 0x8B4) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_TOTAL_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x8C0) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_ABNORMAL_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x8C4) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_INVLD_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x8C8) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_FLR_OP_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x8F8) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x8D0) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_VALID_LOAD_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x8D4) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_VALID_STORE_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x8D8) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_VALID_STORE_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x8DC) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_VALID_STORE_OPERATION_3_REG (CSR_VIRTIO_CSR_BASE + 0x8E0) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x8E4) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_INVALID_LOAD_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x8E8) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_1_REG (CSR_VIRTIO_CSR_BASE + 0x8EC) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_2_REG (CSR_VIRTIO_CSR_BASE + 0x8F0) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_LAST_INVALID_STORE_OPERATION_3_REG (CSR_VIRTIO_CSR_BASE + 0x8F4) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_CPATH_INT_EN_REG (CSR_VIRTIO_CSR_BASE + 0x8FC) /* DFX */ +#define CSR_VIRTIO_CSR_VDB_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x900) /* DFX */ +#define CSR_VIRTIO_CSR_VSDB_PI_INVALID_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x910) /* DFX */ +#define CSR_VIRTIO_CSR_VSAVIDX_PI_INVALID_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x920) /* DFX */ +#define CSR_VIRTIO_CSR_VSAVRING_IDX_INVALID_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x930) /* DFX */ +#define CSR_VIRTIO_CSR_VSAVRING_IDX_INVALID_DAT_REG (CSR_VIRTIO_CSR_BASE + 0x934) /* DFX */ +#define CSR_VIRTIO_CSR_VS1ST_LEN_ZERO_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x940) /* DFX */ +#define CSR_VIRTIO_CSR_VS1ST_NEXT_INVALID_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x944) /* DFX */ +#define CSR_VIRTIO_CSR_VS1ST_FLAG_INVALID_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x948) /* DFX */ +#define CSR_VIRTIO_CSR_VSLEFT_LEN_ZERO_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x960) /* DFX */ +#define CSR_VIRTIO_CSR_VSLEFT_NEXT_INVALID_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x964) /* DFX */ +#define CSR_VIRTIO_CSR_VSLEFT_FLAG_INVALID_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x968) /* DFX */ +#define CSR_VIRTIO_CSR_VSIDESC_LEN_ZERO_INFO_REG (CSR_VIRTIO_CSR_BASE + 0x980) /* DFX */ +#define CSR_VIRTIO_CSR_VSIDESC_NEXT_INVALID_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x984) /* DFX */ +#define CSR_VIRTIO_CSR_VSIDESC_FLAG_INVALID_CNT_REG (CSR_VIRTIO_CSR_BASE + 0x988) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_PACKED_DSC_INVLD_DESC_1_REG (CSR_VIRTIO_CSR_BASE + 0xA00) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_PACKED_DSC_INVLD_DESC_2_REG (CSR_VIRTIO_CSR_BASE + 0xA04) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_PACKED_DSC_INVLD_IDESC_1_REG (CSR_VIRTIO_CSR_BASE + 0xA08) /* DFX */ +#define CSR_VIRTIO_CSR_VIRTIO_PACKED_DSC_INVLD_IDESC_2_REG (CSR_VIRTIO_CSR_BASE + 0xA0C) /* DFX */ +#define CSR_VIRTIO_CSR_VPIDESC_DFX_DESC_LEN_ERR_REG (CSR_VIRTIO_CSR_BASE + 0xA84) /* DFX */ +#define CSR_VIRTIO_CSR_VPBFHD_DFX_HOST_DESC_ERR_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xAC0) /* DFX */ +#define CSR_VIRTIO_CSR_FLR_TIMEOUT_CFG_REG (CSR_VIRTIO_CSR_BASE + 0xE00) /* CFG */ +#define CSR_VIRTIO_CSR_FLR_AEQE_CFG_REG (CSR_VIRTIO_CSR_BASE + 0xE04) /* CFG */ +#define CSR_VIRTIO_CSR_FLR_STATUS_REG (CSR_VIRTIO_CSR_BASE + 0xE08) /* CFG */ +#define CSR_VIRTIO_CSR_PRE_FLR_DFX_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xE10) /* DFX */ +#define CSR_VIRTIO_CSR_PRE_FLR_DFX_CUR_ST_REG (CSR_VIRTIO_CSR_BASE + 0xE14) /* DFX */ +#define CSR_VIRTIO_CSR_PRE_FLR_DFX_AEQE_REG (CSR_VIRTIO_CSR_BASE + 0xE18) /* DFX */ +#define CSR_VIRTIO_CSR_FLR_DFX_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xE30) /* DFX */ +#define CSR_VIRTIO_CSR_FLR_DFX_CUR_ST_REG (CSR_VIRTIO_CSR_BASE + 0xE34) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_FLUSH_MEM_INDEX_H_REG (CSR_VIRTIO_CSR_BASE + 0xE80) /* CFG */ +#define CSR_VIRTIO_CSR_CACHE_BANK_CFG_REG (CSR_VIRTIO_CSR_BASE + 0xE84) /* CFG */ +#define CSR_VIRTIO_CSR_CACHE_FLUSH_DFX_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xE88) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_OUT_DFX_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xE8C) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_OUT_DFX_ERR_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xE90) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_OUT_DFX_CID_ERR_ST_REG (CSR_VIRTIO_CSR_BASE + 0xE94) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_OUT_DFX_BANK_CFG_ERR_FLAG_REG (CSR_VIRTIO_CSR_BASE + 0xE98) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_OUT_DFX_MC_MAX_NUM_ERR_FLAG_REG (CSR_VIRTIO_CSR_BASE + 0xE9C) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_OUT_DFX_CUR_ST_REG (CSR_VIRTIO_CSR_BASE + 0xEA0) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_INVLD_DFX_API_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xEB0) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_INVLD_DFX_OP_EXT_ERR_CNT_REG (CSR_VIRTIO_CSR_BASE + 0xEB4) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_INVLD_DFX_OP_EXT_REG (CSR_VIRTIO_CSR_BASE + 0xEB8) /* DFX */ +#define CSR_VIRTIO_CSR_CACHE_INVLD_DFX_CUR_ST_REG (CSR_VIRTIO_CSR_BASE + 0xEBC) /* DFX */ + +#endif // VIRTIO_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/c_union_define_mag_top.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/c_union_define_mag_top.h new file mode 100644 index 000000000..335e84627 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/c_union_define_mag_top.h @@ -0,0 +1,1695 @@ +/* +* Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved. +* Description: mag top union define +* Author: ETH group +* Modify: 2021-02-05 + */ + +#ifndef MAG_TOP_C_UNION_DEFINE_H +#define MAG_TOP_C_UNION_DEFINE_H + +#include "common.h" + +/* Define the union csr_mag_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_fpga_ver_u; + +/* Define the union csr_mag_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_emu_ver_u; + +/* Define the union csr_mag_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 mag_int_enable : 1; /* [27] */ + u32 mag_int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_int_vector_u; + +/* Define the union csr_mag_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_int_data : 6; /* [5:0] */ + u32 rsv_2 : 10; /* [15:6] */ + u32 mag_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_int_u; + +/* Define the union csr_mag_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_int_en : 6; /* [5:0] */ + u32 rsv_3 : 10; /* [15:6] */ + u32 mag_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_int_en_u; + +/* Define the union csr_mag_sopeop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_sopeop_err : 1; /* [0] */ + u32 mag_sopeop_inj_err : 1; /* [1] */ + u32 mag_sopeop_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_sopeop_err_u; + +/* Define the union csr_mag_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ucerr : 1; /* [0] */ + u32 mag_ram_inj_ucerr : 1; /* [1] */ + u32 mag_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ucerr_u; + +/* Define the union csr_mag_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_cerr : 1; /* [0] */ + u32 mag_ram_inj_cerr : 1; /* [1] */ + u32 mag_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_cerr_u; + +/* Define the union csr_mag_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_crdt_err : 1; /* [0] */ + u32 mag_crdt_inj_err : 1; /* [1] */ + u32 mag_crdt_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_crdt_err_u; + +/* Define the union csr_mag_fifo_ovfl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_fifo_ovfl_err : 1; /* [0] */ + u32 mag_fifo_ovfl_inj_err : 1; /* [1] */ + u32 mag_fifo_ovfl_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_fifo_ovfl_u; + +/* Define the union csr_mag_indir_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_indir_ilgl_err : 1; /* [0] */ + u32 mag_indir_ilgl_inj_err : 1; /* [1] */ + u32 mag_indir_ilgl_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_indir_err_u; + +/* Define the union csr_mag_ucerr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_ram_ucerr_ctrl : 1; /* [0] */ + u32 mag_txp2s_ram_ucerr_ctrl : 1; /* [1] */ + u32 mag_rxs2p_ram_ucerr_ctrl : 1; /* [2] */ + u32 mag_cpd_ram_ucerr_ctrl : 1; /* [3] */ + u32 rsv_4 : 4; /* [7:4] */ + u32 mag_cse_pdm_sfifo_ovfl_ctrl : 1; /* [8] */ + u32 mag_cse_cry_crdt_ovfl_ctrl : 1; /* [9] */ + u32 mag_txp2s_dat_afifo_ovfl_ctrl : 1; /* [10] */ + u32 mag_txp2s_dat_sfifo_ovfl_ctrl : 1; /* [11] */ + u32 mag_txp2s_crdt_err_ctrl : 1; /* [12] */ + u32 mag_rtsp_afifo_ovfl_ctrl : 1; /* [13] */ + u32 mag_rxs2p_dat_afifo_ovfl_ctrl : 1; /* [14] */ + u32 mag_cpd_dat_sfifo_ovfl_ctrl : 1; /* [15] */ + u32 rsv_5 : 12; /* [27:16] */ + u32 mag_top_ucerr_ctrl : 1; /* [28] */ + u32 top_mag_ucerr_ctrl : 1; /* [29] */ + u32 mag_top_ucerr_set : 1; /* [30] */ + u32 top_mag_ucerr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ucerr_ctrl_u; + +/* Define the union csr_mag_ram_ctrl_hh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ctrl_hh : 6; /* [5:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ctrl_hh_u; + +/* Define the union csr_mag_ram_ctrl_hm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ctrl_hm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ctrl_hm_u; + +/* Define the union csr_mag_ram_ctrl_mm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ctrl_mm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ctrl_mm_u; + +/* Define the union csr_mag_ram_ctrl_ml_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ctrl_ml : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ctrl_ml_u; + +/* Define the union csr_mag_ram_ctrl_ll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ctrl_ll : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ctrl_ll_u; + +/* Define the union csr_mag_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_err_chk_bypass : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_err_chk_bypass_u; + +/* Define the union csr_mag_inj_ram_err_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_inj_cse_ram_cerr : 1; /* [0] */ + u32 mag_inj_cse_ram_ucerr : 1; /* [1] */ + u32 mag_inj_txdp_txp2s_ram_cerr : 1; /* [2] */ + u32 mag_inj_txdp_txp2s_ram_ucerr : 1; /* [3] */ + u32 mag_inj_rxdp_cpd_ram_cerr : 1; /* [4] */ + u32 mag_inj_rxdp_cpd_ram_ucerr : 1; /* [5] */ + u32 mag_inj_rxdp_rxs2p_ram_cerr : 1; /* [6] */ + u32 mag_inj_rxdp_rxs2p_ram_ucerr : 1; /* [7] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_inj_ram_err_cfg_u; + +/* Define the union csr_mag_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txp2s_sfifo_sch_th : 6; /* [5:0] */ + u32 rsv_7 : 2; /* [7:6] */ + u32 mag_rtsp_drop_th : 7; /* [14:8] */ + u32 rsv_8 : 1; /* [15] */ + u32 mag_rxdp_cpd_fifo_drop_th : 6; /* [21:16] */ + u32 rsv_9 : 2; /* [23:22] */ + u32 mag_rxs2p_afifo_drop_th : 6; /* [29:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_fifo_th_u; + +/* Define the union csr_mag_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_ucerr_cnt_u; + +/* Define the union csr_mag_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ram_cerr_cnt_u; + +/* Define the union csr_mag_indir_access_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_indir_access_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_indir_access_ilgl_cnt_u; + +/* Define the union csr_mag_work_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_mac_work_mode : 16; /* [15:0] */ + u32 mag_mac_fc_mode : 1; /* [16] */ + u32 mag_txdp_rxdp_loop : 1; /* [17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_work_mode_u; + +/* Define the union csr_mag_ptp_da_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_da_h : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_da_h_u; + +/* Define the union csr_mag_ptp_da_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_da_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_da_l_u; + +/* Define the union csr_mag_ptp_sa_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_sa_h : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_sa_h_u; + +/* Define the union csr_mag_ptp_sa_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_sa_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_sa_l_u; + +/* Define the union csr_mag_ptp_etype_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_etype : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_etype_u; + +/* Define the union csr_mag_ptp_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_mask : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_mask_u; + +/* Define the union csr_mag_ptp_clk_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_clk_period_fraction : 30; /* [29:0] */ + u32 mag_ptp_clk_period_integer : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_clk_period_u; + +/* Define the union csr_mag_ptp_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_clk_ofs : 31; /* [30:0] */ + u32 mag_ptp_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_clk_ofs_u; + +/* Define the union csr_mag_ptp_clk_snap_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_clk_snap_en : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_clk_snap_en_u; + +/* Define the union csr_mag_ptp_snapd_80bclk_h16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_snapd_80bclk_h16 : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_snapd_80bclk_h16_u; + +/* Define the union csr_mag_ptp_snapd_80bclk_m32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_snapd_80bclk_m32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_snapd_80bclk_m32_u; + +/* Define the union csr_mag_ptp_snapd_80bclk_l32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_snapd_80bclk_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_snapd_80bclk_l32_u; + +/* Define the union csr_mag_ptp_snapd_48bclk_h16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_snapd_48bclk_h16 : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_snapd_48bclk_h16_u; + +/* Define the union csr_mag_ptp_snapd_48bclk_l32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ptp_snapd_48bclk_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ptp_snapd_48bclk_l32_u; + +/* Define the union csr_mag_ledc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_led_prt_sel : 3; /* [2:0] */ + u32 rsv_10 : 1; /* [3] */ + u32 mag_led_mode : 4; /* [7:4] */ + u32 mag_led_blink_prd : 3; /* [10:8] */ + u32 rsv_11 : 1; /* [11] */ + u32 mag_led_pulse_prd : 3; /* [14:12] */ + u32 rsv_12 : 1; /* [15] */ + u32 mag_led_polarity : 1; /* [16] */ + u32 mag_led_en : 1; /* [17] */ + u32 rsv_13 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ledc_cfg_u; + +/* Define the union csr_mag_flc_port_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_port_map : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_port_map_u; + +/* Define the union csr_mag_flc_tx_cos_bc_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_tx_cos4_bc : 8; /* [7:0] */ + u32 mag_flc_tx_cos5_bc : 8; /* [15:8] */ + u32 mag_flc_tx_cos6_bc : 8; /* [23:16] */ + u32 mag_flc_tx_cos7_bc : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_tx_cos_bc_h_u; + +/* Define the union csr_mag_flc_tx_cos_bc_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_tx_cos0_bc : 8; /* [7:0] */ + u32 mag_flc_tx_cos1_bc : 8; /* [15:8] */ + u32 mag_flc_tx_cos2_bc : 8; /* [23:16] */ + u32 mag_flc_tx_cos3_bc : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_tx_cos_bc_l_u; + +/* Define the union csr_mag_flc_ipsurx_link_xoff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_from_ipsurx_link_xoff_bypass : 1; /* [0] */ + u32 mag_flc_from_ipsurx_link_xoff_set : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_ipsurx_link_xoff_u; + +/* Define the union csr_mag_flc_bp_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_from_rxmac_cos_bp_set : 8; /* [7:0] */ + u32 mag_flc_from_rxmac_port_bp_set : 1; /* [8] */ + u32 rsv_14 : 7; /* [15:9] */ + u32 mag_flc_from_txprm_cos_bp_set : 8; /* [23:16] */ + u32 mag_flc_from_txprm_port_bp_set : 1; /* [24] */ + u32 mag_flc_from_txfc_port_bp_set : 1; /* [25] */ + u32 rsv_15 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_bp_set_u; + +/* Define the union csr_mag_flc_bp_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_from_rxmac_cos_bp_bypass : 8; /* [7:0] */ + u32 mag_flc_from_rxmac_port_bp_bypass : 1; /* [8] */ + u32 rsv_16 : 7; /* [15:9] */ + u32 mag_flc_from_txprm_cos_bp_bypass : 8; /* [23:16] */ + u32 mag_flc_from_txprm_port_bp_bypass : 1; /* [24] */ + u32 mag_flc_from_txfc_port_bp_bypass : 1; /* [25] */ + u32 rsv_17 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_bp_bypass_u; + +/* Define the union csr_mag_flc_bp_st_cur_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_from_rxmac_cos_bp_cur : 8; /* [7:0] */ + u32 mag_flc_from_rxmac_port_bp_cur : 1; /* [8] */ + u32 rsv_18 : 7; /* [15:9] */ + u32 mag_flc_from_txprm_cos_bp_cur : 8; /* [23:16] */ + u32 mag_flc_from_txprm_port_bp_cur : 1; /* [24] */ + u32 mag_flc_from_txfc_port_bp_cur : 1; /* [25] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_bp_st_cur_u; + +/* Define the union csr_mag_flc_bp_st_hst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_flc_from_rxmac_cos_bp_hst : 8; /* [7:0] */ + u32 mag_flc_from_rxmac_port_bp_hst : 1; /* [8] */ + u32 rsv_20 : 7; /* [15:9] */ + u32 mag_flc_from_txprm_cos_bp_hst : 8; /* [23:16] */ + u32 mag_flc_from_txprm_port_bp_hst : 1; /* [24] */ + u32 mag_flc_from_txfc_port_bp_hst : 1; /* [25] */ + u32 rsv_21 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_flc_bp_st_hst_u; + +/* Define the union csr_mag_cse_port_crdt_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_port_crdt_ini : 7; /* [6:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_port_crdt_ini_u; + +/* Define the union csr_mag_cse_port_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_port_dat_cnt : 8; /* [7:0] */ + u32 mag_cse_port_rdy : 1; /* [8] */ + u32 mag_cse_wsnd_sopeop_st : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_port_st_u; + +/* Define the union csr_mag_cse_rcvd_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_rcvd_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_rcvd_pkt_cnt_u; + +/* Define the union csr_mag_cse_snt_good_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_snt_good_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_snt_good_pkt_cnt_u; + +/* Define the union csr_mag_cse_snt_bad_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_snt_bad_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_snt_bad_pkt_cnt_u; + +/* Define the union csr_mag_cse_rcv_petx_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rcv_petx_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_rcv_petx_cyc_cnt_u; + +/* Define the union csr_mag_cse_snt_petx_pkt_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_snt_petx_pkt_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_snt_petx_pkt_crdt_cnt_u; + +/* Define the union csr_mag_cse_snt_petx_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_snt_petx_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_snt_petx_cmdidx_crdt_cnt_u; + +/* Define the union csr_mag_cse_snt_cry_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_snt_cry_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_snt_cry_cyc_cnt_u; + +/* Define the union csr_mag_cse_rcv_cry_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cse_rcv_cry_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_cse_rcv_cry_crdt_cnt_u; + +/* Define the union csr_mag_txdp_port_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_mac_port_crdt_ini : 11; /* [10:0] */ + u32 rsv_22 : 13; /* [23:11] */ + u32 mag_txdp_port_cp_dst_rxport : 3; /* [26:24] */ + u32 mag_txdp_port_cp_frm : 1; /* [27] */ + u32 mag_txdp_port_ptp_en : 1; /* [28] */ + u32 rsv_23 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_port_cfg_u; + +/* Define the union csr_mag_txdp_sch_calendar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_ts0_port : 3; /* [2:0] */ + u32 mag_txdp_ts0_vld : 1; /* [3] */ + u32 mag_txdp_ts1_port : 3; /* [6:4] */ + u32 mag_txdp_ts1_vld : 1; /* [7] */ + u32 mag_txdp_ts2_port : 3; /* [10:8] */ + u32 mag_txdp_ts2_vld : 1; /* [11] */ + u32 mag_txdp_ts3_port : 3; /* [14:12] */ + u32 mag_txdp_ts3_vld : 1; /* [15] */ + u32 mag_txdp_ts4_port : 3; /* [18:16] */ + u32 mag_txdp_ts4_vld : 1; /* [19] */ + u32 mag_txdp_ts5_port : 3; /* [22:20] */ + u32 mag_txdp_ts5_vld : 1; /* [23] */ + u32 mag_txdp_ts6_port : 3; /* [26:24] */ + u32 mag_txdp_ts6_vld : 1; /* [27] */ + u32 mag_txdp_ts7_port : 3; /* [30:28] */ + u32 mag_txdp_ts7_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_sch_calendar_u; + +/* Define the union csr_mag_txdp_short_mac_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_short_mac_pkt_len : 6; /* [5:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_short_mac_pkt_len_u; + +/* Define the union csr_mag_txdp_perf_mon_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_start : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_start_u; + +/* Define the union csr_mag_txdp_perf_mon_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_port : 3; /* [2:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_port_u; + +/* Define the union csr_mag_txdp_perf_mon_time_h32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_time_h32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_time_h32_u; + +/* Define the union csr_mag_txdp_perf_mon_time_l32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_time_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_time_l32_u; + +/* Define the union csr_mag_txdp_perf_mon_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_done : 1; /* [0] */ + u32 mag_txdp_perf_mon_pkt_cnt_ovf : 1; /* [1] */ + u32 mag_txdp_perf_mon_byte_cnt_ovf : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_done_u; + +/* Define the union csr_mag_txdp_port_st_cur_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_mac_port_crdt_cur : 11; /* [10:0] */ + u32 mag_txdp_port_wsnd_sopeop_st : 1; /* [11] */ + u32 mag_txdp_from_fc_bp_cur : 1; /* [12] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_port_st_cur_u; + +/* Define the union csr_mag_txdp_perf_mon_byte_num_h32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_byte_num_h32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_byte_num_h32_u; + +/* Define the union csr_mag_txdp_perf_mon_byte_num_l32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_byte_num_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_byte_num_l32_u; + +/* Define the union csr_mag_txdp_perf_mon_pkt_num_h32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_pkt_num_h32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_pkt_num_h32_u; + +/* Define the union csr_mag_txdp_perf_mon_pkt_num_l32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_perf_mon_pkt_num_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_perf_mon_pkt_num_l32_u; + +/* Define the union csr_mag_txdp_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txp2s_dat_afifo_wcnt : 4; /* [3:0] */ + u32 rsv_25 : 4; /* [7:4] */ + u32 mag_txp2s_dat_sfifo_cnt : 7; /* [14:8] */ + u32 rsv_26 : 1; /* [15] */ + u32 mag_txp2s_crdt_afifo_rcnt : 5; /* [20:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_fifo_cnt_u; + +/* Define the union csr_mag_txdp_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txp2s_dat_afifo_ovfl_cur : 1; /* [0] */ + u32 mag_txp2s_dat_afifo_full_cur : 1; /* [1] */ + u32 mag_txp2s_dat_afifo_empty_cur : 1; /* [2] */ + u32 rsv_27 : 5; /* [7:3] */ + u32 mag_txp2s_dat_sfifo_ovfl_cur : 1; /* [8] */ + u32 mag_txp2s_dat_sfifo_full_cur : 1; /* [9] */ + u32 mag_txp2s_dat_sfifo_empty_cur : 1; /* [10] */ + u32 rsv_28 : 5; /* [15:11] */ + u32 mag_txp2s_crdt_afifo_ovfl_cur : 1; /* [16] */ + u32 mag_txp2s_crdt_afifo_full_cur : 1; /* [17] */ + u32 mag_txp2s_crdt_afifo_empty_cur : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_fifo_cur_st_u; + +/* Define the union csr_mag_txdp_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txp2s_dat_afifo_ovfl_hst : 1; /* [0] */ + u32 mag_txp2s_dat_afifo_full_hst : 1; /* [1] */ + u32 rsv_30 : 6; /* [7:2] */ + u32 mag_txp2s_dat_sfifo_ovfl_hst : 1; /* [8] */ + u32 mag_txp2s_dat_sfifo_full_hst : 1; /* [9] */ + u32 rsv_31 : 6; /* [15:10] */ + u32 mag_txp2s_crdt_afifo_ovfl_hst : 1; /* [16] */ + u32 mag_txp2s_crdt_afifo_full_hst : 1; /* [17] */ + u32 rsv_32 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_fifo_hst_st_u; + +/* Define the union csr_mag_txdp_from_fc_bp_hst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_from_fc_bp_hst : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_from_fc_bp_hst_u; + +/* Define the union csr_mag_txdp_rcvd_ptp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_rcvd_ptp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_rcvd_ptp_cnt_u; + +/* Define the union csr_mag_txdp_recd_sopeop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_recd_sopeop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_recd_sopeop_err_cnt_u; + +/* Define the union csr_mag_txdp_port_snt_good_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_port_snt_good_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_port_snt_good_pkt_cnt_u; + +/* Define the union csr_mag_txdp_port_snt_bad_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_port_snt_bad_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_port_snt_bad_pkt_cnt_u; + +/* Define the union csr_mag_txdp_short_mac_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_txdp_short_mac_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_txdp_short_mac_pkt_cnt_u; + +/* Define the union csr_mag_snt_himac_seg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_snt_himac_seg_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_snt_himac_seg_cnt_u; + +/* Define the union csr_mag_rcv_himac_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rcv_himac_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rcv_himac_crdt_cnt_u; + +/* Define the union csr_mag_rxdp_port_drop_pfc_pause_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_port_drop_pfc_pause : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_port_drop_pfc_pause_u; + +/* Define the union csr_mag_rxdp_rts_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_rts_port : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_rts_port_u; + +/* Define the union csr_mag_rxdp_rts_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_rts_gap : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_rts_gap_u; + +/* Define the union csr_mag_rxdp_clr_mac_drop_cnt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_clr_mac_drop_cnt_en : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_clr_mac_drop_cnt_en_u; + +/* Define the union csr_mag_rxdp_from_ipsurx_bp_cur_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_from_ipsurx_bp_cur : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_from_ipsurx_bp_cur_u; + +/* Define the union csr_mag_rxdp_port_sopeop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_port_rcvd_sop_err_cur : 8; /* [7:0] */ + u32 mag_rxdp_port_rcvd_eop_err_cur : 8; /* [15:8] */ + u32 mag_rxdp_port_wrec_sopeop_st : 8; /* [23:16] */ + u32 mag_ipsurx_wsnd_sopeop_st : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_port_sopeop_st_u; + +/* Define the union csr_mag_rxdp_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rtsp_afifo_cnt : 8; /* [7:0] */ + u32 mag_cpd_sfifo_cnt : 7; /* [14:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_fifo_cnt_u; + +/* Define the union csr_mag_rxdp_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxs2p_dat_afifo_ovfl_cur : 1; /* [0] */ + u32 mag_rxs2p_dat_afifo_full_cur : 1; /* [1] */ + u32 mag_rxs2p_dat_afifo_empty_cur : 1; /* [2] */ + u32 rsv_33 : 13; /* [15:3] */ + u32 mag_rtsp_afifo_ovfl_cur : 1; /* [16] */ + u32 mag_rtsp_afifo_full_cur : 1; /* [17] */ + u32 mag_rtsp_afifo_empty_cur : 1; /* [18] */ + u32 rsv_34 : 5; /* [23:19] */ + u32 mag_rxdp_cpd_sfifo_ovfl_cur : 1; /* [24] */ + u32 mag_rxdp_cpd_sfifo_full_cur : 1; /* [25] */ + u32 mag_rxdp_cpd_sfifo_empty_cur : 1; /* [26] */ + u32 rsv_35 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_fifo_cur_st_u; + +/* Define the union csr_mag_rxdp_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxs2p_dat_afifo_ovfl_hst : 1; /* [0] */ + u32 mag_rxs2p_dat_afifo_full_hst : 1; /* [1] */ + u32 rsv_36 : 14; /* [15:2] */ + u32 mag_rtsp_afifo_ovfl_hst : 1; /* [16] */ + u32 mag_rtsp_afifo_full_hst : 1; /* [17] */ + u32 rsv_37 : 6; /* [23:18] */ + u32 mag_rxdp_cpd_sfifo_ovfl_hst : 1; /* [24] */ + u32 mag_rxdp_cpd_sfifo_full_hst : 1; /* [25] */ + u32 rsv_38 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_fifo_hst_st_u; + +/* Define the union csr_mag_rxdp_port_rcvd_seop_err_hst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_port_rcvd_sop_err_hst : 8; /* [7:0] */ + u32 mag_rxdp_port_rcvd_eop_err_hst : 8; /* [15:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_port_rcvd_seop_err_hst_u; + +/* Define the union csr_mag_rxdp_from_ipsurx_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_from_ipsurx_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_from_ipsurx_bp_cnt_u; + +/* Define the union csr_mag_rxdp_rcvd_rts_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_rts_rcvd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_rcvd_rts_cnt_u; + +/* Define the union csr_mag_rxdp_rts_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_rts_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_rts_drop_cnt_u; + +/* Define the union csr_mag_rxdp_rtsp_ovfl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_rtsp_ovfl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_rtsp_ovfl_cnt_u; + +/* Define the union csr_mag_rxdp_port_recd_good_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_port_recd_good_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_port_recd_good_pkt_cnt_u; + +/* Define the union csr_mag_rxdp_port_recd_bad_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_port_recd_bad_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_port_recd_bad_pkt_cnt_u; + +/* Define the union csr_mag_rxdp_pause_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_pause_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_pause_drop_cnt_u; + +/* Define the union csr_mag_rxs2p_afifo_ovfl_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxs2p_afifo_ovfl_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxs2p_afifo_ovfl_drop_cnt_u; + +/* Define the union csr_mag_rxdp_cpd_port_recd_good_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_cpd_port_recd_good_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_cpd_port_recd_good_pkt_cnt_u; + +/* Define the union csr_mag_rxdp_cpd_port_recd_bad_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_cpd_port_recd_bad_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_cpd_port_recd_bad_pkt_cnt_u; + +/* Define the union csr_mag_rxdp_cpd_fifo_ovfl_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxdp_cpd_fifo_ovfl_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_rxdp_cpd_fifo_ovfl_drop_cnt_u; + +/* Define the union csr_mag_ipsurx_port_snt_good_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ipsurx_port_snt_good_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ipsurx_port_snt_good_pkt_cnt_u; + +/* Define the union csr_mag_ipsurx_port_snt_bad_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_ipsurx_port_snt_bad_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_ipsurx_port_snt_bad_pkt_cnt_u; + +/* Define the union csr_mag_lane_los_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_rxlos_io_sel : 4; /* [3:0] */ + u32 mag_sds_los_en : 1; /* [4] */ + u32 mag_rxlos_en : 1; /* [5] */ + u32 rsv_39 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_lane_los_config_u; + +/* Define the union csr_mag_smux_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_smux_m7_afifo_rcnt : 5; /* [4:0] */ + u32 mag_smux_m7_afifo_ovfl_cur : 1; /* [5] */ + u32 mag_smux_m7_afifo_full_cur : 1; /* [6] */ + u32 mag_smux_m7_afifo_empty_cur : 1; /* [7] */ + u32 mag_smux_m6_afifo_rcnt : 5; /* [12:8] */ + u32 mag_smux_m6_afifo_ovfl_cur : 1; /* [13] */ + u32 mag_smux_m6_afifo_full_cur : 1; /* [14] */ + u32 mag_smux_m6_afifo_empty_cur : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_smux_fifo_cur_st_u; + +/* Define the union csr_mag_smux_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_smux_m7_afifo_ovfl_hst : 1; /* [0] */ + u32 mag_smux_m7_afifo_full_hst : 1; /* [1] */ + u32 rsv_40 : 6; /* [7:2] */ + u32 mag_smux_m6_afifo_ovfl_hst : 1; /* [8] */ + u32 mag_smux_m6_afifo_full_hst : 1; /* [9] */ + u32 rsv_41 : 6; /* [15:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_smux_fifo_hst_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mag_fpga_ver_u mag_fpga_ver; /* 0 */ + volatile csr_mag_emu_ver_u mag_emu_ver; /* 4 */ + volatile csr_mag_int_vector_u mag_int_vector; /* 10 */ + volatile csr_mag_int_u mag_int; /* 14 */ + volatile csr_mag_int_en_u mag_int_en; /* 18 */ + volatile csr_mag_sopeop_err_u mag_sopeop_err; /* 1C */ + volatile csr_mag_ram_ucerr_u mag_ram_ucerr; /* 20 */ + volatile csr_mag_ram_cerr_u mag_ram_cerr; /* 24 */ + volatile csr_mag_crdt_err_u mag_crdt_err; /* 28 */ + volatile csr_mag_fifo_ovfl_u mag_fifo_ovfl; /* 2C */ + volatile csr_mag_indir_err_u mag_indir_err; /* 30 */ + volatile csr_mag_ucerr_ctrl_u mag_ucerr_ctrl; /* 100 */ + volatile csr_mag_ram_ctrl_hh_u mag_ram_ctrl_hh; /* 104 */ + volatile csr_mag_ram_ctrl_hm_u mag_ram_ctrl_hm; /* 108 */ + volatile csr_mag_ram_ctrl_mm_u mag_ram_ctrl_mm; /* 10C */ + volatile csr_mag_ram_ctrl_ml_u mag_ram_ctrl_ml; /* 110 */ + volatile csr_mag_ram_ctrl_ll_u mag_ram_ctrl_ll; /* 114 */ + volatile csr_mag_ram_err_chk_bypass_u mag_ram_err_chk_bypass; /* 118 */ + volatile csr_mag_inj_ram_err_cfg_u mag_inj_ram_err_cfg; /* 11C */ + volatile csr_mag_fifo_th_u mag_fifo_th; /* 120 */ + volatile csr_mag_ram_ucerr_cnt_u mag_ram_ucerr_cnt; /* 600 */ + volatile csr_mag_ram_cerr_cnt_u mag_ram_cerr_cnt; /* 604 */ + volatile csr_mag_indir_access_ilgl_cnt_u mag_indir_access_ilgl_cnt; /* 608 */ + volatile csr_mag_work_mode_u mag_work_mode; /* 1000 */ + volatile csr_mag_ptp_da_h_u mag_ptp_da_h; /* 1004 */ + volatile csr_mag_ptp_da_l_u mag_ptp_da_l; /* 1008 */ + volatile csr_mag_ptp_sa_h_u mag_ptp_sa_h; /* 100C */ + volatile csr_mag_ptp_sa_l_u mag_ptp_sa_l; /* 1010 */ + volatile csr_mag_ptp_etype_u mag_ptp_etype; /* 1014 */ + volatile csr_mag_ptp_mask_u mag_ptp_mask; /* 1018 */ + volatile csr_mag_ptp_clk_period_u mag_ptp_clk_period; /* 5000 */ + volatile csr_mag_ptp_clk_ofs_u mag_ptp_clk_ofs; /* 5004 */ + volatile csr_mag_ptp_clk_snap_en_u mag_ptp_clk_snap_en; /* 5008 */ + volatile csr_mag_ptp_snapd_80bclk_h16_u mag_ptp_snapd_80bclk_h16; /* 5400 */ + volatile csr_mag_ptp_snapd_80bclk_m32_u mag_ptp_snapd_80bclk_m32; /* 5404 */ + volatile csr_mag_ptp_snapd_80bclk_l32_u mag_ptp_snapd_80bclk_l32; /* 5408 */ + volatile csr_mag_ptp_snapd_48bclk_h16_u mag_ptp_snapd_48bclk_h16; /* 540C */ + volatile csr_mag_ptp_snapd_48bclk_l32_u mag_ptp_snapd_48bclk_l32; /* 5410 */ + volatile csr_mag_ledc_cfg_u mag_ledc_cfg[24]; /* 6000 */ + volatile csr_mag_flc_port_map_u mag_flc_port_map; /* 7000 */ + volatile csr_mag_flc_tx_cos_bc_h_u mag_flc_tx_cos_bc_h[8]; /* 7004 */ + volatile csr_mag_flc_tx_cos_bc_l_u mag_flc_tx_cos_bc_l[8]; /* 7100 */ + volatile csr_mag_flc_ipsurx_link_xoff_u mag_flc_ipsurx_link_xoff; /* 7200 */ + volatile csr_mag_flc_bp_set_u mag_flc_bp_set[8]; /* 7300 */ + volatile csr_mag_flc_bp_bypass_u mag_flc_bp_bypass[8]; /* 7400 */ + volatile csr_mag_flc_bp_st_cur_u mag_flc_bp_st_cur[8]; /* 7700 */ + volatile csr_mag_flc_bp_st_hst_u mag_flc_bp_st_hst[8]; /* 7800 */ + volatile csr_mag_cse_port_crdt_ini_u mag_cse_port_crdt_ini[11]; /* 8000 */ + volatile csr_mag_cse_port_st_u mag_cse_port_st[11]; /* 8400 */ + volatile csr_mag_cse_rcvd_pkt_cnt_u mag_cse_rcvd_pkt_cnt[11]; /* 8C00 */ + volatile csr_mag_cse_snt_good_pkt_cnt_u mag_cse_snt_good_pkt_cnt[11]; /* 8C40 */ + volatile csr_mag_cse_snt_bad_pkt_cnt_u mag_cse_snt_bad_pkt_cnt[11]; /* 8C80 */ + volatile csr_mag_cse_rcv_petx_cyc_cnt_u mag_cse_rcv_petx_cyc_cnt[11]; /* 8CC0 */ + volatile csr_mag_cse_snt_petx_pkt_crdt_cnt_u mag_cse_snt_petx_pkt_crdt_cnt[11]; /* 8CEC */ + volatile csr_mag_cse_snt_petx_cmdidx_crdt_cnt_u mag_cse_snt_petx_cmdidx_crdt_cnt; /* 8D18 */ + volatile csr_mag_cse_snt_cry_cyc_cnt_u mag_cse_snt_cry_cyc_cnt[3]; /* 8D1C */ + volatile csr_mag_cse_rcv_cry_crdt_cnt_u mag_cse_rcv_cry_crdt_cnt[3]; /* 8D28 */ + volatile csr_mag_txdp_port_cfg_u mag_txdp_port_cfg[8]; /* 9000 */ + volatile csr_mag_txdp_sch_calendar_u mag_txdp_sch_calendar; /* 9040 */ + volatile csr_mag_txdp_short_mac_pkt_len_u mag_txdp_short_mac_pkt_len; /* 9044 */ + volatile csr_mag_txdp_perf_mon_start_u mag_txdp_perf_mon_start; /* 9048 */ + volatile csr_mag_txdp_perf_mon_port_u mag_txdp_perf_mon_port; /* 904C */ + volatile csr_mag_txdp_perf_mon_time_h32_u mag_txdp_perf_mon_time_h32; /* 9050 */ + volatile csr_mag_txdp_perf_mon_time_l32_u mag_txdp_perf_mon_time_l32; /* 9054 */ + volatile csr_mag_txdp_perf_mon_done_u mag_txdp_perf_mon_done; /* 9400 */ + volatile csr_mag_txdp_port_st_cur_u mag_txdp_port_st_cur[8]; /* 9410 */ + volatile csr_mag_txdp_perf_mon_byte_num_h32_u mag_txdp_perf_mon_byte_num_h32; /* 9440 */ + volatile csr_mag_txdp_perf_mon_byte_num_l32_u mag_txdp_perf_mon_byte_num_l32; /* 9444 */ + volatile csr_mag_txdp_perf_mon_pkt_num_h32_u mag_txdp_perf_mon_pkt_num_h32; /* 9448 */ + volatile csr_mag_txdp_perf_mon_pkt_num_l32_u mag_txdp_perf_mon_pkt_num_l32; /* 944C */ + volatile csr_mag_txdp_fifo_cnt_u mag_txdp_fifo_cnt; /* 9450 */ + volatile csr_mag_txdp_fifo_cur_st_u mag_txdp_fifo_cur_st; /* 9454 */ + volatile csr_mag_txdp_fifo_hst_st_u mag_txdp_fifo_hst_st; /* 9458 */ + volatile csr_mag_txdp_from_fc_bp_hst_u mag_txdp_from_fc_bp_hst; /* 945C */ + volatile csr_mag_txdp_rcvd_ptp_cnt_u mag_txdp_rcvd_ptp_cnt; /* 9C00 */ + volatile csr_mag_txdp_recd_sopeop_err_cnt_u mag_txdp_recd_sopeop_err_cnt; /* 9C04 */ + volatile csr_mag_txdp_port_snt_good_pkt_cnt_u mag_txdp_port_snt_good_pkt_cnt[8]; /* 9C08 */ + volatile csr_mag_txdp_port_snt_bad_pkt_cnt_u mag_txdp_port_snt_bad_pkt_cnt[8]; /* 9C48 */ + volatile csr_mag_txdp_short_mac_pkt_cnt_u mag_txdp_short_mac_pkt_cnt; /* 9C80 */ + volatile csr_mag_snt_himac_seg_cnt_u mag_snt_himac_seg_cnt[8]; /* 9C84 */ + volatile csr_mag_rcv_himac_crdt_cnt_u mag_rcv_himac_crdt_cnt[8]; /* 9CA4 */ + volatile csr_mag_rxdp_port_drop_pfc_pause_u mag_rxdp_port_drop_pfc_pause; /* A000 */ + volatile csr_mag_rxdp_rts_port_u mag_rxdp_rts_port; /* A004 */ + volatile csr_mag_rxdp_rts_gap_u mag_rxdp_rts_gap; /* A008 */ + volatile csr_mag_rxdp_clr_mac_drop_cnt_en_u mag_rxdp_clr_mac_drop_cnt_en; /* A00C */ + volatile csr_mag_rxdp_from_ipsurx_bp_cur_u mag_rxdp_from_ipsurx_bp_cur; /* A010 */ + volatile csr_mag_rxdp_port_sopeop_st_u mag_rxdp_port_sopeop_st; /* A014 */ + volatile csr_mag_rxdp_fifo_cnt_u mag_rxdp_fifo_cnt; /* A018 */ + volatile csr_mag_rxdp_fifo_cur_st_u mag_rxdp_fifo_cur_st; /* A01C */ + volatile csr_mag_rxdp_fifo_hst_st_u mag_rxdp_fifo_hst_st; /* A020 */ + volatile csr_mag_rxdp_port_rcvd_seop_err_hst_u mag_rxdp_port_rcvd_seop_err_hst; /* A024 */ + volatile csr_mag_rxdp_from_ipsurx_bp_cnt_u mag_rxdp_from_ipsurx_bp_cnt; /* A028 */ + volatile csr_mag_rxdp_rcvd_rts_cnt_u mag_rxdp_rcvd_rts_cnt; /* A02C */ + volatile csr_mag_rxdp_rts_drop_cnt_u mag_rxdp_rts_drop_cnt; /* A030 */ + volatile csr_mag_rxdp_rtsp_ovfl_cnt_u mag_rxdp_rtsp_ovfl_cnt; /* A034 */ + volatile csr_mag_rxdp_port_recd_good_pkt_cnt_u mag_rxdp_port_recd_good_pkt_cnt[8]; /* AC90 */ + volatile csr_mag_rxdp_port_recd_bad_pkt_cnt_u mag_rxdp_port_recd_bad_pkt_cnt[8]; /* ACD0 */ + volatile csr_mag_rxdp_pause_drop_cnt_u mag_rxdp_pause_drop_cnt[8]; /* AD10 */ + volatile csr_mag_rxs2p_afifo_ovfl_drop_cnt_u mag_rxs2p_afifo_ovfl_drop_cnt[8]; /* AD50 */ + volatile csr_mag_rxdp_cpd_port_recd_good_pkt_cnt_u mag_rxdp_cpd_port_recd_good_pkt_cnt[8]; /* AD90 */ + volatile csr_mag_rxdp_cpd_port_recd_bad_pkt_cnt_u mag_rxdp_cpd_port_recd_bad_pkt_cnt[8]; /* ADD0 */ + volatile csr_mag_rxdp_cpd_fifo_ovfl_drop_cnt_u mag_rxdp_cpd_fifo_ovfl_drop_cnt[8]; /* AE10 */ + volatile csr_mag_ipsurx_port_snt_good_pkt_cnt_u mag_ipsurx_port_snt_good_pkt_cnt[8]; /* AE50 */ + volatile csr_mag_ipsurx_port_snt_bad_pkt_cnt_u mag_ipsurx_port_snt_bad_pkt_cnt[8]; /* AE90 */ + volatile csr_mag_lane_los_config_u mag_lane_los_config[8]; /* B000 */ + volatile csr_mag_smux_fifo_cur_st_u mag_smux_fifo_cur_st; /* B020 */ + volatile csr_mag_smux_fifo_hst_st_u mag_smux_fifo_hst_st; /* B024 */ +} S_mag_csr_REGS_TYPE; + +/* Declare the struct pointor of the module mag_csr */ +extern volatile S_mag_csr_REGS_TYPE *gopmag_csrAllReg; + +/* 1822 reserved for emu test */ +/* Define the union u_magtop_int_status */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rxdp : 1; /* [0] */ + unsigned int txdp : 1; /* [1] */ + unsigned int fc : 1; /* [2] */ + unsigned int tsp : 1; /* [3] */ + unsigned int unimac : 6; /* [9..4] */ + unsigned int reserved_0 : 22; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_int_status; + +/* Define the union u_magtop_int_enable */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rxdp : 1; /* [0] */ + unsigned int txdp : 1; /* [1] */ + unsigned int fc : 1; /* [2] */ + unsigned int tsp : 1; /* [3] */ + unsigned int unimac : 6; /* [9..4] */ + unsigned int reserved_0 : 22; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_int_enable; + +/* Define the union u_magtop_glb_rstn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int logic : 1; /* [0] */ + unsigned int reserved_0 : 31; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_glb_rstn; + +/* Define the union u_magtop_rxdp_rstn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int logic : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int all : 1; /* [4] */ + unsigned int reserved_1 : 27; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_rxdp_rstn; + +/* Define the union u_magtop_txdp_rstn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int logic : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int all : 1; /* [4] */ + unsigned int reserved_1 : 27; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_txdp_rstn; + +/* Define the union u_magtop_unimac_rstn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int logic : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int all : 1; /* [4] */ + unsigned int reserved_1 : 27; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_unimac_rstn; + +/* Define the union u_magtop_fc_rstn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int logic : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int all : 1; /* [4] */ + unsigned int reserved_1 : 27; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_fc_rstn; + +/* Define the union u_magtop_tsp_rstn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int logic : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int all : 1; /* [4] */ + unsigned int reserved_1 : 3; /* [7..5] */ + unsigned int i2c : 1; /* [8] */ + unsigned int reserved_2 : 23; /* [31..9] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_tsp_rstn; + +/* Define the union u_magtop_port_ctrl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int port_mode : 5; /* [4..0] */ + unsigned int reserved_0 : 27; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_port_ctrl; + +/* Define the union u_magtop_slv_base_addr_h */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int base_addr : 16; /* [15..0] */ + unsigned int reserved_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_slv_base_addr_h; + +/* Define the union u_magtop_loop_en */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rxdp2txdp : 1; /* [0] */ + unsigned int reserved_0 : 31; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_loop_en; + +/* Define the union u_magtop_uer_cfg */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int mask : 2; /* [1..0] */ + unsigned int reserved_0 : 2; /* [3..2] */ + unsigned int set : 2; /* [5..4] */ + unsigned int reserved_1 : 26; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_uer_cfg; + +/* Define the union u_magtop_uer_info */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int block_id : 10; /* [9..0] */ + unsigned int reserved_0 : 22; /* [31..10] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_uer_info; + +/* Define the union u_magtop_mfs_sch_calendar */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int cal : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int vld : 1; /* [4] */ + unsigned int reserved_1 : 27; /* [31..5] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_mfs_sch_calendar; + +/* Define the union u_magtop_mfs_sch_calendar_length */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int len : 4; /* [3..0] */ + unsigned int reserved_0 : 28; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_magtop_mfs_sch_calendar_length; + +#endif // MAG_TOP_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/c_union_define_smag_cfg.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/c_union_define_smag_cfg.h new file mode 100644 index 000000000..167b77d11 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/c_union_define_smag_cfg.h @@ -0,0 +1,1457 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2021. All rights reserved. + * File name : c_union_define_smag_cfg.h + * Date : 2020/3/5 + * Description : the definition of smg reg + */ + +#ifndef C_UNION_DEFINE_SMAG_CFG_H +#define C_UNION_DEFINE_SMAG_CFG_H + +/* Define the union u_smag_mode */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int loop4_mode : 1; /* [0] */ + unsigned int loop5_mode : 1; /* [1] */ + unsigned int loop6_mode : 1; /* [2] */ + unsigned int cfg_rxdp_pkt_dis : 1; /* [3] */ + unsigned int mag_mfs_sch_calendar_vld : 16; /* [19..4] */ + unsigned int loop5_mode_port : 4; /* [23..20] */ + unsigned int smag_version : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_mode; + +/* Define the union u_smag2mac_sig_detect */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int axis_tx_tready_max_num : 4; /* [3..0] */ + unsigned int axis_tx_tready_max_hit : 4; /* [7..4] */ + unsigned int p0_axis_tx_tready_max : 4; /* [11..8] */ + unsigned int p1_axis_tx_tready_max : 4; /* [15..12] */ + unsigned int p2_axis_tx_tready_max : 4; /* [19..16] */ + unsigned int p3_axis_tx_tready_max : 4; /* [23..20] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_sig_detect; + +/* Define the union u_smag2mac_tx0_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_sop_cnt_0 : 16; /* [15..0] */ + unsigned int smag2mac_eop_cnt_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx0_dfx_0; + +/* Define the union u_smag2mac_tx0_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_vld_cnt_0 : 16; /* [15..0] */ + unsigned int tx_afifo_rd_trig_0 : 5; /* [20..16] */ + unsigned int reserved_0 : 11; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx0_dfx_1; + +/* Define the union u_smag_int_status */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_sop_eop_int : 1; /* [0] */ + unsigned int p1_sop_eop_int : 1; /* [1] */ + unsigned int p2_sop_eop_int : 1; /* [2] */ + unsigned int p3_sop_eop_int : 1; /* [3] */ + unsigned int p4_sop_eop_int : 1; /* [4] */ + unsigned int p5_sop_eop_int : 1; /* [5] */ + unsigned int p6_sop_eop_int : 1; /* [6] */ + unsigned int p7_sop_eop_int : 1; /* [7] */ + unsigned int reserved_0 : 24; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_int_status; + +/* Define the union u_tx0_afifo_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_sop_cnt_0 : 16; /* [15..0] */ + unsigned int tx_afifo_eop_cnt_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx0_afifo_dfx_0; + +/* Define the union u_tx0_afifo_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_vld_cnt_0 : 16; /* [15..0] */ + unsigned int cnt_afifo_w_cnt_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx0_afifo_dfx_1; + +/* Define the union u_smag_rx_tx_en */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag_rx_en : 8; /* [7..0] */ + unsigned int smag_tx_en : 8; /* [15..8] */ + unsigned int rsvd_cfg : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_rx_tx_en; + +/* Define the union u_smag_int_mask */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_sop_eop_int_msk : 1; /* [0] */ + unsigned int p1_sop_eop_int_msk : 1; /* [1] */ + unsigned int p2_sop_eop_int_msk : 1; /* [2] */ + unsigned int p3_sop_eop_int_msk : 1; /* [3] */ + unsigned int p4_sop_eop_int_msk : 1; /* [4] */ + unsigned int p5_sop_eop_int_msk : 1; /* [5] */ + unsigned int p6_sop_eop_int_msk : 1; /* [6] */ + unsigned int p7_sop_eop_int_msk : 1; /* [7] */ + unsigned int reserved_0 : 24; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_int_mask; + +/* Define the union u_smag_int_set */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_sop_eop_int_set : 1; /* [0] */ + unsigned int p1_sop_eop_int_set : 1; /* [1] */ + unsigned int p2_sop_eop_int_set : 1; /* [2] */ + unsigned int p3_sop_eop_int_set : 1; /* [3] */ + unsigned int p4_sop_eop_int_set : 1; /* [4] */ + unsigned int p5_sop_eop_int_set : 1; /* [5] */ + unsigned int p6_sop_eop_int_set : 1; /* [6] */ + unsigned int p7_sop_eop_int_set : 1; /* [7] */ + unsigned int reserved_0 : 24; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_int_set; + +/* Define the union u_smag_mac_debug */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int mac_rx_cnt_min_0 : 4; /* [3..0] */ + unsigned int mac_rx_cnt_min_1 : 4; /* [7..4] */ + unsigned int mac_rx_cnt_min_2 : 4; /* [11..8] */ + unsigned int mac_rx_cnt_min_3 : 4; /* [15..12] */ + unsigned int mac_glitch_pkt_cnt_0 : 4; /* [19..16] */ + unsigned int mac_glitch_pkt_cnt_1 : 4; /* [23..20] */ + unsigned int mac_glitch_pkt_cnt_2 : 4; /* [27..24] */ + unsigned int mac_glitch_pkt_cnt_3 : 4; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_mac_debug; + +/* Define the union u_smag_ipsurx_err_debug0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pkt_loss_eop_err : 16; /* [15..0] */ + unsigned int pkt_loss_sop_err : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_ipsurx_err_debug0; + +/* Define the union u_smag_ipsurx_err_debug1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pkt_nop_vld_err : 16; /* [15..0] */ + unsigned int reserved_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_ipsurx_err_debug1; + +/* Define the union u_smag_chan_xoff_debug */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int chan_xoff_min : 16; /* [15..0] */ + unsigned int chan_xoff_min_cos_sel : 3; /* [18..16] */ + unsigned int reserved_0 : 1; /* [19] */ + unsigned int chan_xoff_min_port_sel : 2; /* [21..20] */ + unsigned int reserved_1 : 10; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_chan_xoff_debug; + +/* Define the union u_smag_pe_dfx_p00 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_sop_cnt_0 : 16; /* [15..0] */ + unsigned int pe2mag_eop_cnt_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p00; + +/* Define the union u_smag_pe_dfx_p01 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_vld_cnt_0 : 16; /* [15..0] */ + unsigned int pe2mag_longest_pkt_cnt_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p01; + +/* Define the union u_smag_pe_dfx_p10 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_sop_cnt_1 : 16; /* [15..0] */ + unsigned int pe2mag_eop_cnt_1 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p10; + +/* Define the union u_smag_pe_dfx_p11 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_vld_cnt_1 : 16; /* [15..0] */ + unsigned int pe2mag_longest_pkt_cnt_1 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p11; + +/* Define the union u_smag_pe_dfx_p20 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_sop_cnt_2 : 16; /* [15..0] */ + unsigned int pe2mag_eop_cnt_2 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p20; + +/* Define the union u_smag_pe_dfx_p21 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_vld_cnt_2 : 16; /* [15..0] */ + unsigned int pe2mag_longest_pkt_cnt_2 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p21; + +/* Define the union u_smag_pe_dfx_p30 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_sop_cnt_3 : 16; /* [15..0] */ + unsigned int pe2mag_eop_cnt_3 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p30; + +/* Define the union u_smag_pe_dfx_p31 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe2mag_vld_cnt_3 : 16; /* [15..0] */ + unsigned int pe2mag_longest_pkt_cnt_3 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_pe_dfx_p31; + +/* Define the union u_smag_cnt_fifo_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int cnt_fifo_wcnt_0 : 11; /* [10..0] */ + unsigned int reserved_0 : 5; /* [15..11] */ + unsigned int cnt_fifo_wcnt_1 : 11; /* [26..16] */ + unsigned int reserved_1 : 5; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_cnt_fifo_0; + +/* Define the union u_smag_cnt_fifo_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int cnt_fifo_wcnt_2 : 11; /* [10..0] */ + unsigned int reserved_0 : 5; /* [15..11] */ + unsigned int cnt_fifo_wcnt_3 : 11; /* [26..16] */ + unsigned int reserved_1 : 5; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_cnt_fifo_1; + +/* Define the union u_smag2mac_tx1_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_sop_cnt_1 : 16; /* [15..0] */ + unsigned int smag2mac_eop_cnt_1 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx1_dfx_0; + +/* Define the union u_smag2mac_tx1_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_vld_cnt_1 : 16; /* [15..0] */ + unsigned int tx_afifo_rd_trig_1 : 5; /* [20..16] */ + unsigned int reserved_0 : 11; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx1_dfx_1; + +/* Define the union u_tx1_afifo_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_sop_cnt_1 : 16; /* [15..0] */ + unsigned int tx_afifo_eop_cnt_1 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx1_afifo_dfx_0; + +/* Define the union u_tx1_afifo_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_vld_cnt_1 : 16; /* [15..0] */ + unsigned int cnt_afifo_w_cnt_1 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx1_afifo_dfx_1; + +/* Define the union u_smag2mac_tx2_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_sop_cnt_2 : 16; /* [15..0] */ + unsigned int smag2mac_eop_cnt_2 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx2_dfx_0; + +/* Define the union u_smag2mac_tx2_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_vld_cnt_2 : 16; /* [15..0] */ + unsigned int tx_afifo_rd_trig_2 : 5; /* [20..16] */ + unsigned int reserved_0 : 11; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx2_dfx_1; + +/* Define the union u_tx2_afifo_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_sop_cnt_2 : 16; /* [15..0] */ + unsigned int tx_afifo_eop_cnt_2 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx2_afifo_dfx_0; + +/* Define the union u_tx2_afifo_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_vld_cnt_2 : 16; /* [15..0] */ + unsigned int cnt_afifo_w_cnt_2 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx2_afifo_dfx_1; + +/* Define the union u_smag2mac_tx3_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_sop_cnt_3 : 16; /* [15..0] */ + unsigned int smag2mac_eop_cnt_3 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx3_dfx_0; + +/* Define the union u_smag2mac_tx3_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag2mac_vld_cnt_3 : 16; /* [15..0] */ + unsigned int tx_afifo_rd_trig_3 : 5; /* [20..16] */ + unsigned int reserved_0 : 11; /* [31..21] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag2mac_tx3_dfx_1; + +/* Define the union u_tx3_afifo_dfx_0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_sop_cnt_3 : 16; /* [15..0] */ + unsigned int tx_afifo_eop_cnt_3 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx3_afifo_dfx_0; + +/* Define the union u_tx3_afifo_dfx_1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int tx_afifo_vld_cnt_3 : 16; /* [15..0] */ + unsigned int cnt_afifo_w_cnt_3 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_tx3_afifo_dfx_1; + +/* Define the union u_smag_xgem_fifo_af_th1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_send_fifo_af_th : 11; /* [10..0] */ + unsigned int p1_send_fifo_af_th : 11; /* [21..11] */ + unsigned int reserved_0 : 10; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th1; + +/* Define the union u_smag_xgem_fifo_af_th2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p2_send_fifo_af_th : 11; /* [10..0] */ + unsigned int p3_send_fifo_af_th : 11; /* [21..11] */ + unsigned int reserved_0 : 10; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th2; + +/* Define the union u_smag_xgem_fifo_af_th3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p4_send_fifo_af_th : 11; /* [10..0] */ + unsigned int p5_send_fifo_af_th : 11; /* [21..11] */ + unsigned int reserved_0 : 10; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th3; + +/* Define the union u_smag_xgem_fifo_af_th4 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p6_send_fifo_af_th : 11; /* [10..0] */ + unsigned int p7_send_fifo_af_th : 11; /* [21..11] */ + unsigned int reserved_0 : 10; /* [31..22] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th4; + +/* Define the union u_smag_xgem_fifo_af_th5 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_rec_fifo_af_th : 13; /* [12..0] */ + unsigned int p1_rec_fifo_af_th : 13; /* [25..13] */ + unsigned int reserved_0 : 6; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th5; + +/* Define the union u_smag_xgem_fifo_af_th6 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p2_rec_fifo_af_th : 13; /* [12..0] */ + unsigned int p3_rec_fifo_af_th : 13; /* [25..13] */ + unsigned int reserved_0 : 6; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th6; + +/* Define the union u_smag_xgem_fifo_af_th7 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_rec_fifo_af_th_clr : 13; /* [12..0] */ + unsigned int p1_rec_fifo_af_th_clr : 13; /* [25..13] */ + unsigned int reserved_0 : 6; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th7; + +/* Define the union u_smag_xgem_fifo_af_th8 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p2_rec_fifo_af_th_clr : 13; /* [12..0] */ + unsigned int p3_rec_fifo_af_th_clr : 13; /* [25..13] */ + unsigned int reserved_0 : 6; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_af_th8; + +/* Define the union u_smag_xgem_fifo_cnt1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_send_fifo_cnt : 12; /* [11..0] */ + unsigned int p1_send_fifo_cnt : 12; /* [23..12] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt1; + +/* Define the union u_smag_xgem_fifo_cnt2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p2_send_fifo_cnt : 12; /* [11..0] */ + unsigned int p3_send_fifo_cnt : 12; /* [23..12] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt2; + +/* Define the union u_smag_xgem_fifo_cnt3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p4_send_fifo_cnt : 12; /* [11..0] */ + unsigned int p5_send_fifo_cnt : 12; /* [23..12] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt3; + +/* Define the union u_smag_xgem_fifo_cnt4 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p6_send_fifo_cnt : 12; /* [11..0] */ + unsigned int p7_send_fifo_cnt : 12; /* [23..12] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt4; + +/* Define the union u_smag_xgem_fifo_cnt5 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_rec_fifo_cnt : 14; /* [13..0] */ + unsigned int p1_rec_fifo_cnt : 14; /* [27..14] */ + unsigned int reserved_0 : 4; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt5; + +/* Define the union u_smag_xgem_fifo_cnt6 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p2_rec_fifo_cnt : 14; /* [13..0] */ + unsigned int p3_rec_fifo_cnt : 14; /* [27..14] */ + unsigned int reserved_0 : 4; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt6; + +/* Define the union u_smag_xgem_fifo_cnt7 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p4_rec_fifo_cnt : 14; /* [13..0] */ + unsigned int p5_rec_fifo_cnt : 14; /* [27..14] */ + unsigned int reserved_0 : 4; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt7; + +/* Define the union u_smag_xgem_fifo_cnt8 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p6_rec_fifo_cnt : 14; /* [13..0] */ + unsigned int p7_rec_fifo_cnt : 14; /* [27..14] */ + unsigned int reserved_0 : 4; /* [31..28] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_cnt8; + +/* Define the union u_smag_xgem_fifo_status1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_send_fifo_empt : 1; /* [0] */ + unsigned int p0_send_fifo_full : 1; /* [1] */ + unsigned int p0_send_fifo_afull : 1; /* [2] */ + unsigned int p0_send_fifo_of : 1; /* [3] */ + unsigned int p1_send_fifo_empt : 1; /* [4] */ + unsigned int p1_send_fifo_full : 1; /* [5] */ + unsigned int p1_send_fifo_afull : 1; /* [6] */ + unsigned int p1_send_fifo_of : 1; /* [7] */ + unsigned int p2_send_fifo_empt : 1; /* [8] */ + unsigned int p2_send_fifo_full : 1; /* [9] */ + unsigned int p2_send_fifo_afull : 1; /* [10] */ + unsigned int p2_send_fifo_of : 1; /* [11] */ + unsigned int p3_send_fifo_empt : 1; /* [12] */ + unsigned int p3_send_fifo_full : 1; /* [13] */ + unsigned int p3_send_fifo_afull : 1; /* [14] */ + unsigned int p3_send_fifo_of : 1; /* [15] */ + unsigned int p4_send_fifo_empt : 1; /* [16] */ + unsigned int p4_send_fifo_full : 1; /* [17] */ + unsigned int p4_send_fifo_afull : 1; /* [18] */ + unsigned int p4_send_fifo_of : 1; /* [19] */ + unsigned int p5_send_fifo_empt : 1; /* [20] */ + unsigned int p5_send_fifo_full : 1; /* [21] */ + unsigned int p5_send_fifo_afull : 1; /* [22] */ + unsigned int p5_send_fifo_of : 1; /* [23] */ + unsigned int p6_send_fifo_empt : 1; /* [24] */ + unsigned int p6_send_fifo_full : 1; /* [25] */ + unsigned int p6_send_fifo_afull : 1; /* [26] */ + unsigned int p6_send_fifo_of : 1; /* [27] */ + unsigned int p7_send_fifo_empt : 1; /* [28] */ + unsigned int p7_send_fifo_full : 1; /* [29] */ + unsigned int p7_send_fifo_afull : 1; /* [30] */ + unsigned int p7_send_fifo_of : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_status1; + +/* Define the union u_smag_xgem_fifo_status2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_rec_fifo_empt : 1; /* [0] */ + unsigned int p0_rec_fifo_full : 1; /* [1] */ + unsigned int p0_rec_fifo_afull : 1; /* [2] */ + unsigned int p0_rec_fifo_of : 1; /* [3] */ + unsigned int p1_rec_fifo_empt : 1; /* [4] */ + unsigned int p1_rec_fifo_full : 1; /* [5] */ + unsigned int p1_rec_fifo_afull : 1; /* [6] */ + unsigned int p1_rec_fifo_of : 1; /* [7] */ + unsigned int p2_rec_fifo_empt : 1; /* [8] */ + unsigned int p2_rec_fifo_full : 1; /* [9] */ + unsigned int p2_rec_fifo_afull : 1; /* [10] */ + unsigned int p2_rec_fifo_of : 1; /* [11] */ + unsigned int p3_rec_fifo_empt : 1; /* [12] */ + unsigned int p3_rec_fifo_full : 1; /* [13] */ + unsigned int p3_rec_fifo_afull : 1; /* [14] */ + unsigned int p3_rec_fifo_of : 1; /* [15] */ + unsigned int p4_rec_fifo_empt : 1; /* [16] */ + unsigned int p4_rec_fifo_full : 1; /* [17] */ + unsigned int p4_rec_fifo_afull : 1; /* [18] */ + unsigned int p4_rec_fifo_of : 1; /* [19] */ + unsigned int p5_rec_fifo_empt : 1; /* [20] */ + unsigned int p5_rec_fifo_full : 1; /* [21] */ + unsigned int p5_rec_fifo_afull : 1; /* [22] */ + unsigned int p5_rec_fifo_of : 1; /* [23] */ + unsigned int p6_rec_fifo_empt : 1; /* [24] */ + unsigned int p6_rec_fifo_full : 1; /* [25] */ + unsigned int p6_rec_fifo_afull : 1; /* [26] */ + unsigned int p6_rec_fifo_of : 1; /* [27] */ + unsigned int p7_rec_fifo_empt : 1; /* [28] */ + unsigned int p7_rec_fifo_full : 1; /* [29] */ + unsigned int p7_rec_fifo_afull : 1; /* [30] */ + unsigned int p7_rec_fifo_of : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_status2; + +/* Define the union u_smag_xgem_fifo_status3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_rec_fifo_aempt : 1; /* [0] */ + unsigned int p0_rec_fifo_uf : 1; /* [1] */ + unsigned int p0_send_fifo_aempt : 1; /* [2] */ + unsigned int p0_send_fifo_uf : 1; /* [3] */ + unsigned int p1_rec_fifo_aempt : 1; /* [4] */ + unsigned int p1_rec_fifo_uf : 1; /* [5] */ + unsigned int p1_send_fifo_aempt : 1; /* [6] */ + unsigned int p1_send_fifo_uf : 1; /* [7] */ + unsigned int p2_rec_fifo_aempt : 1; /* [8] */ + unsigned int p2_rec_fifo_uf : 1; /* [9] */ + unsigned int p2_send_fifo_aempt : 1; /* [10] */ + unsigned int p2_send_fifo_uf : 1; /* [11] */ + unsigned int p3_rec_fifo_aempt : 1; /* [12] */ + unsigned int p3_rec_fifo_uf : 1; /* [13] */ + unsigned int p3_send_fifo_aempt : 1; /* [14] */ + unsigned int p3_send_fifo_uf : 1; /* [15] */ + unsigned int p4_rec_fifo_aempt : 1; /* [16] */ + unsigned int p4_rec_fifo_uf : 1; /* [17] */ + unsigned int p4_send_fifo_aempt : 1; /* [18] */ + unsigned int p4_send_fifo_uf : 1; /* [19] */ + unsigned int p5_rec_fifo_aempt : 1; /* [20] */ + unsigned int p5_rec_fifo_uf : 1; /* [21] */ + unsigned int p5_send_fifo_aempt : 1; /* [22] */ + unsigned int p5_send_fifo_uf : 1; /* [23] */ + unsigned int p6_rec_fifo_aempt : 1; /* [24] */ + unsigned int p6_rec_fifo_uf : 1; /* [25] */ + unsigned int p6_send_fifo_aempt : 1; /* [26] */ + unsigned int p6_send_fifo_uf : 1; /* [27] */ + unsigned int p7_rec_fifo_aempt : 1; /* [28] */ + unsigned int p7_rec_fifo_uf : 1; /* [29] */ + unsigned int p7_send_fifo_aempt : 1; /* [30] */ + unsigned int p7_send_fifo_uf : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_fifo_status3; + +/* Define the union u_smag_xgem_syn */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int clksmag_clk156_pos : 1; /* [0] */ + unsigned int reserved_0 : 31; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_syn; + +/* Define the union u_smag_xgem_ctl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int xgem_tx_ifd : 8; /* [7..0] */ + unsigned int p0_tx_axis_aresetn : 1; /* [8] */ + unsigned int p0_rx_axis_aresetn : 1; /* [9] */ + unsigned int p1_tx_axis_aresetn : 1; /* [10] */ + unsigned int p1_rx_axis_aresetn : 1; /* [11] */ + unsigned int p2_tx_axis_aresetn : 1; /* [12] */ + unsigned int p2_rx_axis_aresetn : 1; /* [13] */ + unsigned int p3_tx_axis_aresetn : 1; /* [14] */ + unsigned int p3_rx_axis_aresetn : 1; /* [15] */ + unsigned int p4_tx_axis_aresetn : 1; /* [16] */ + unsigned int p4_rx_axis_aresetn : 1; /* [17] */ + unsigned int p5_tx_axis_aresetn : 1; /* [18] */ + unsigned int p5_rx_axis_aresetn : 1; /* [19] */ + unsigned int p6_tx_axis_aresetn : 1; /* [20] */ + unsigned int p6_rx_axis_aresetn : 1; /* [21] */ + unsigned int p7_tx_axis_aresetn : 1; /* [22] */ + unsigned int p7_rx_axis_aresetn : 1; /* [23] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_ctl; + +/* Define the union u_smag_xgem_status2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p4_pcspma_status : 8; /* [7..0] */ + unsigned int p5_pcspma_status : 8; /* [15..8] */ + unsigned int p6_pcspma_status : 8; /* [23..16] */ + unsigned int p7_pcspma_status : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_status2; + +/* Define the union u_smag_xgem_status1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_pcspma_status : 8; /* [7..0] */ + unsigned int p1_pcspma_status : 8; /* [15..8] */ + unsigned int p2_pcspma_status : 8; /* [23..16] */ + unsigned int p3_pcspma_status : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_status1; + +/* Define the union u_smag_xgem_status3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_rx_tkeep_err : 1; /* [0] */ + unsigned int p1_rx_tkeep_err : 1; /* [1] */ + unsigned int p2_rx_tkeep_err : 1; /* [2] */ + unsigned int p3_rx_tkeep_err : 1; /* [3] */ + unsigned int p4_rx_tkeep_err : 1; /* [4] */ + unsigned int p5_rx_tkeep_err : 1; /* [5] */ + unsigned int p6_rx_tkeep_err : 1; /* [6] */ + unsigned int p7_rx_tkeep_err : 1; /* [7] */ + unsigned int reserved_0 : 24; /* [31..8] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_status3; + +/* Define the union u_smag_xgem_pause_tdata1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p0_pause_tdata : 16; /* [15..0] */ + unsigned int p1_pause_tdata : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_pause_tdata1; + +/* Define the union u_smag_xgem_pause_tdata2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p2_pause_tdata : 16; /* [15..0] */ + unsigned int p3_pause_tdata : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_pause_tdata2; + +/* Define the union u_smag_xgem_pause_tdata3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p4_pause_tdata : 16; /* [15..0] */ + unsigned int p5_pause_tdata : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_pause_tdata3; + +/* Define the union u_smag_xgem_pause_tdata4 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int p6_pause_tdata : 16; /* [15..0] */ + unsigned int p7_pause_tdata : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_xgem_pause_tdata4; + +/* Define the union u_smag_rxdp_fifo_status */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rxdp_fifo_uf : 1; /* [0] */ + unsigned int rxdp_fifo_of : 1; /* [1] */ + unsigned int rxdp_fifo_cnt : 1; /* [2] */ + unsigned int rxdp_fifo_empty : 1; /* [3] */ + unsigned int rxdp_fifo_aempty : 1; /* [4] */ + unsigned int rxdp_fifo_afull : 1; /* [5] */ + unsigned int rxdp_fifo_full : 1; /* [6] */ + unsigned int reserved_0 : 25; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_rxdp_fifo_status; + +/* Define the union u_smag_dp_fifo_th1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p0_afull_th : 6; /* [5..0] */ + unsigned int txdp_p1_afull_th : 6; /* [11..6] */ + unsigned int txdp_p2_afull_th : 6; /* [17..12] */ + unsigned int txdp_p3_afull_th : 6; /* [23..18] */ + unsigned int rxdp_fifo_afull_th : 5; /* [28..24] */ + unsigned int reserved_0 : 3; /* [31..29] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_dp_fifo_th1; + +/* Define the union u_smag_dp_fifo_th2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p4_afull_th : 6; /* [5..0] */ + unsigned int txdp_p5_afull_th : 6; /* [11..6] */ + unsigned int txdp_p6_afull_th : 6; /* [17..12] */ + unsigned int txdp_p7_afull_th : 6; /* [23..18] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_dp_fifo_th2; + +/* Define the union u_smag_txdp_fifo_status1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p0_uf : 1; /* [0] */ + unsigned int txdp_p0_of : 1; /* [1] */ + unsigned int txdp_p0_empty : 1; /* [2] */ + unsigned int txdp_p0_aempty : 1; /* [3] */ + unsigned int txdp_p0_afull : 1; /* [4] */ + unsigned int txdp_p0_full : 1; /* [5] */ + unsigned int txdp_p1_uf : 1; /* [6] */ + unsigned int txdp_p1_of : 1; /* [7] */ + unsigned int txdp_p1_empty : 1; /* [8] */ + unsigned int txdp_p1_aempty : 1; /* [9] */ + unsigned int txdp_p1_afull : 1; /* [10] */ + unsigned int txdp_p1_full : 1; /* [11] */ + unsigned int txdp_p2_uf : 1; /* [12] */ + unsigned int txdp_p2_of : 1; /* [13] */ + unsigned int txdp_p2_empty : 1; /* [14] */ + unsigned int txdp_p2_aempty : 1; /* [15] */ + unsigned int txdp_p2_afull : 1; /* [16] */ + unsigned int txdp_p2_full : 1; /* [17] */ + unsigned int txdp_p3_uf : 1; /* [18] */ + unsigned int txdp_p3_of : 1; /* [19] */ + unsigned int txdp_p3_empty : 1; /* [20] */ + unsigned int txdp_p3_aempty : 1; /* [21] */ + unsigned int txdp_p3_afull : 1; /* [22] */ + unsigned int txdp_p3_full : 1; /* [23] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_fifo_status1; + +/* Define the union u_smag_txdp_fifo_status2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p4_uf : 1; /* [0] */ + unsigned int txdp_p4_of : 1; /* [1] */ + unsigned int txdp_p4_empty : 1; /* [2] */ + unsigned int txdp_p4_aempty : 1; /* [3] */ + unsigned int txdp_p4_afull : 1; /* [4] */ + unsigned int txdp_p4_full : 1; /* [5] */ + unsigned int txdp_p5_uf : 1; /* [6] */ + unsigned int txdp_p5_of : 1; /* [7] */ + unsigned int txdp_p5_empty : 1; /* [8] */ + unsigned int txdp_p5_aempty : 1; /* [9] */ + unsigned int txdp_p5_afull : 1; /* [10] */ + unsigned int txdp_p5_full : 1; /* [11] */ + unsigned int txdp_p6_uf : 1; /* [12] */ + unsigned int txdp_p6_of : 1; /* [13] */ + unsigned int txdp_p6_empty : 1; /* [14] */ + unsigned int txdp_p6_aempty : 1; /* [15] */ + unsigned int txdp_p6_afull : 1; /* [16] */ + unsigned int txdp_p6_full : 1; /* [17] */ + unsigned int txdp_p7_uf : 1; /* [18] */ + unsigned int txdp_p7_of : 1; /* [19] */ + unsigned int txdp_p7_empty : 1; /* [20] */ + unsigned int txdp_p7_aempty : 1; /* [21] */ + unsigned int txdp_p7_afull : 1; /* [22] */ + unsigned int txdp_p7_full : 1; /* [23] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_fifo_status2; + +/* Define the union u_smag_txdp_p0_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p0_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p0_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p0_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p0_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p0_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p0_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p0_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p0_err_cnt; + +/* Define the union u_smag_txdp_p1_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p1_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p1_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p1_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p1_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p1_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p1_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p1_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p1_err_cnt; + +/* Define the union u_smag_txdp_p2_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p2_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p2_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p2_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p2_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p2_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p2_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p2_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p2_err_cnt; + +/* Define the union u_smag_txdp_p3_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p3_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p3_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p3_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p3_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p3_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p3_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p3_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p3_err_cnt; + +/* Define the union u_smag_txdp_p4_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p4_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p4_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p4_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p4_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p4_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p4_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p4_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p4_err_cnt; + +/* Define the union u_smag_txdp_p5_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p5_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p5_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p5_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p5_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p5_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p5_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p5_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p5_err_cnt; + +/* Define the union u_smag_txdp_p6_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p6_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p6_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p6_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p6_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p6_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p6_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p6_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p6_err_cnt; + +/* Define the union u_smag_txdp_p7_err_cnt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p7_ck1_cnt : 13; /* [12..0] */ + unsigned int txdp_p7_ck1_cnt_clr : 1; /* [13] */ + unsigned int txdp_p7_ck1_cnt_of : 1; /* [14] */ + unsigned int txdp_p7_ck2_cnt : 13; /* [27..15] */ + unsigned int txdp_p7_ck2_cnt_clr : 1; /* [28] */ + unsigned int txdp_p7_ck2_cnt_of : 1; /* [29] */ + unsigned int txdp_p7_sop_eop_err : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_p7_err_cnt; + +/* Define the union u_smag_phy2lgc_remap_en */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int phy2lgc_remap_en : 1; /* [0] */ + unsigned int reserved_0 : 3; /* [3..1] */ + unsigned int fc_pause_en : 1; /* [4] */ + unsigned int reserved_1 : 3; /* [7..5] */ + unsigned int mag_mfs_sch_calendar_len : 4; /* [11..8] */ + unsigned int reserved_2 : 4; /* [15..12] */ + unsigned int mag_mfs_sch_calendar_cal : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_phy2lgc_remap_en; + +/* Define the union u_smag_rx_cos_mode */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rx_cos0_mode : 3; /* [2..0] */ + unsigned int reserved_0 : 1; /* [3] */ + unsigned int rx_cos1_mode : 3; /* [6..4] */ + unsigned int reserved_1 : 1; /* [7] */ + unsigned int rx_cos2_mode : 3; /* [10..8] */ + unsigned int reserved_2 : 1; /* [11] */ + unsigned int rx_cos3_mode : 3; /* [14..12] */ + unsigned int reserved_3 : 1; /* [15] */ + unsigned int rx_cos4_mode : 3; /* [18..16] */ + unsigned int reserved_4 : 1; /* [19] */ + unsigned int rx_cos5_mode : 3; /* [22..20] */ + unsigned int reserved_5 : 1; /* [23] */ + unsigned int rx_cos6_mode : 3; /* [26..24] */ + unsigned int reserved_6 : 1; /* [27] */ + unsigned int rx_cos7_mode : 3; /* [30..28] */ + unsigned int reserved_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_rx_cos_mode; + +/* Define the union u_smag_tx_cos_mode */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int qu_cos0_mode : 3; /* [2..0] */ + unsigned int reserved_0 : 1; /* [3] */ + unsigned int qu_cos1_mode : 3; /* [6..4] */ + unsigned int reserved_1 : 1; /* [7] */ + unsigned int qu_cos2_mode : 3; /* [10..8] */ + unsigned int reserved_2 : 1; /* [11] */ + unsigned int qu_cos3_mode : 3; /* [14..12] */ + unsigned int reserved_3 : 1; /* [15] */ + unsigned int qu_cos4_mode : 3; /* [18..16] */ + unsigned int reserved_4 : 1; /* [19] */ + unsigned int qu_cos5_mode : 3; /* [22..20] */ + unsigned int reserved_5 : 1; /* [23] */ + unsigned int qu_cos6_mode : 3; /* [26..24] */ + unsigned int reserved_6 : 1; /* [27] */ + unsigned int qu_cos7_mode : 3; /* [30..28] */ + unsigned int reserved_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_tx_cos_mode; + +/* Define the union u_smag_rx_debug */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rx_afifo_ren_cnt : 16; /* [15..0] */ + unsigned int mac2smag_vld_cnt : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_rx_debug; + +/* Define the union u_smag_bp_history */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int qu_mag_rx_port_bp_history : 8; /* [7..0] */ + unsigned int mag_pe_bp_history : 8; /* [15..8] */ + unsigned int ipsurx_mag_bp_history : 1; /* [16] */ + unsigned int reserved_0 : 3; /* [19..17] */ + unsigned int fc_pause_rcvd_history : 4; /* [23..20] */ + unsigned int rec_fifo_afull_history : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_bp_history; + +/* Define the union u_smag_rx_ok_pkt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int mac2smag_abort_pkt_cnt : 16; /* [15..0] */ + unsigned int smag_rx_ok_pkt_cnt : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_rx_ok_pkt; + +/* Define the union u_smag_rx_drop_pkt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag_rx_abort_pkt_cnt : 16; /* [15..0] */ + unsigned int smag_rx_drop_pkt_cnt : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_rx_drop_pkt; + +/* Define the union u_smag_ipsurx_ok_pkt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag_ipsurx_abort_pkt : 16; /* [15..0] */ + unsigned int smag_ipsurx_ok_pkt : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_ipsurx_ok_pkt; + +/* Define the union u_pe_smag_ok_pkt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pe_smag_abort_pkt : 16; /* [15..0] */ + unsigned int pe_smag_ok_pkt : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_pe_smag_ok_pkt; + +/* Define the union u_smag_tx_ok_pkt */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag_tx_err_pkt : 16; /* [15..0] */ + unsigned int smag_tx_ok_pkt : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_tx_ok_pkt; + +/* Define the union u_smag_txdp_fifo_cnt0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p0_cnt : 7; /* [6..0] */ + unsigned int reserved_0 : 1; /* [7] */ + unsigned int txdp_p1_cnt : 7; /* [14..8] */ + unsigned int reserved_1 : 1; /* [15] */ + unsigned int txdp_p2_cnt : 7; /* [22..16] */ + unsigned int reserved_2 : 1; /* [23] */ + unsigned int txdp_p3_cnt : 7; /* [30..24] */ + unsigned int reserved_3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_fifo_cnt0; + +/* Define the union u_smag_txdp_fifo_cnt1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int txdp_p4_cnt : 7; /* [6..0] */ + unsigned int reserved_0 : 1; /* [7] */ + unsigned int txdp_p5_cnt : 7; /* [14..8] */ + unsigned int reserved_1 : 1; /* [15] */ + unsigned int txdp_p6_cnt : 7; /* [22..16] */ + unsigned int reserved_2 : 1; /* [23] */ + unsigned int txdp_p7_cnt : 7; /* [30..24] */ + unsigned int reserved_3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_txdp_fifo_cnt1; + +/* Define the union u_smag_bp_rtime */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int qu_mag_rx_port_bp : 8; /* [7..0] */ + unsigned int mag_pe_bp : 8; /* [15..8] */ + unsigned int ipsurx_mag_bp : 1; /* [16] */ + unsigned int reserved_0 : 3; /* [19..17] */ + unsigned int fc_pause_rcvd : 4; /* [23..20] */ + unsigned int rec_fifo_afull : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_bp_rtime; + +/* Define the union u_smag_mfs_adp_cfg */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int mfs_adp_stat : 16; /* [15..0] */ + unsigned int mfs_adp_cfg : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_mfs_adp_cfg; + +/* Define the union u_smag_ip_sel */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int smag_ip_sel : 3; /* [2..0] */ + unsigned int reserved_0 : 29; /* [31..3] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_smag_ip_sel; + +#endif /* C_UNION_DEFINE_SMAG_CFG_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/hi1822_csr_mag_offset_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/hi1822_csr_mag_offset_union_define.h new file mode 100644 index 000000000..262e332af --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/hi1822_csr_mag_offset_union_define.h @@ -0,0 +1,22 @@ +#ifndef HI1823_CSR_MAG_OFFSET_UNION_DEFINE_H +#define HI1823_CSR_MAG_OFFSET_UNION_DEFINE_H + +#include "c_union_define_mag_top.h" + +#include "mag_top_reg_offset.h" +#include "mac_reg_com_offset.h" +#include "mac_reg_mib_offset.h" +#include "mac_reg_rx_brfec_offset.h" +#include "mac_reg_rx_mac_offset.h" +#include "mac_reg_rx_pcs_offset.h" +#include "mac_reg_rx_rsfec_offset.h" +#include "mac_reg_rxpma_core_offset.h" +#include "mac_reg_rxpma_lane_offset.h" +#include "mac_reg_tx_brfec_offset.h" +#include "mac_reg_tx_mac_offset.h" +#include "mac_reg_tx_pcs_offset.h" +#include "mac_reg_tx_rsfec_offset.h" +#include "mac_reg_txpma_core_offset.h" +#include "mac_reg_txpma_lane_offset.h" + +#endif /* HI1823_CSR_MAG_OFFSET_UNION_DEFINE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_an_lth60_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_an_lth60_offset.h new file mode 100644 index 000000000..05836d7e5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_an_lth60_offset.h @@ -0,0 +1,483 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021. All rights reserved. + * Description: AN_LTH60 REG Definition + * Author: ETH group + * Create: 2021-4-8 + */ +#ifndef MAC_REG_AN_LTH60_H +#define MAC_REG_AN_LTH60_H + +/* Base address of Module's Register */ +#define AN_LTH60_BASE (0x0) + +#define AN_LTH60_COMMON_INT_INFO_R (AN_LTH60_BASE + 0x0) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE0_INT_F (AN_LTH60_BASE + 0x0), (0x00000001) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE1_INT_F (AN_LTH60_BASE + 0x0), (0x00000002) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE2_INT_F (AN_LTH60_BASE + 0x0), (0x00000004) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE3_INT_F (AN_LTH60_BASE + 0x0), (0x00000008) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE4_INT_F (AN_LTH60_BASE + 0x0), (0x00000010) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE5_INT_F (AN_LTH60_BASE + 0x0), (0x00000020) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE6_INT_F (AN_LTH60_BASE + 0x0), (0x00000040) +#define AN_LTH60_COMMON_INT_INFO_R_AN_LANE7_INT_F (AN_LTH60_BASE + 0x0), (0x00000080) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE0_INT_F (AN_LTH60_BASE + 0x0), (0x00000100) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE1_INT_F (AN_LTH60_BASE + 0x0), (0x00000200) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE2_INT_F (AN_LTH60_BASE + 0x0), (0x00000400) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE3_INT_F (AN_LTH60_BASE + 0x0), (0x00000800) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE4_INT_F (AN_LTH60_BASE + 0x0), (0x00001000) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE5_INT_F (AN_LTH60_BASE + 0x0), (0x00002000) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE6_INT_F (AN_LTH60_BASE + 0x0), (0x00004000) +#define AN_LTH60_COMMON_INT_INFO_R_LT_LANE7_INT_F (AN_LTH60_BASE + 0x0), (0x00008000) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R (AN_LTH60_BASE + 0x4) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R_CAP_CMD_F (AN_LTH60_BASE + 0x4), (0x000000ff) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R_CAP_LOCAL_REMOTE_F (AN_LTH60_BASE + 0x4), (0x00000100) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R_CAP_DATA_CMD_F (AN_LTH60_BASE + 0x4), (0x00000200) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R_CAP_CONTROL_STATUS_F (AN_LTH60_BASE + 0x4), (0x00000400) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R_CAP_NUM_F (AN_LTH60_BASE + 0x4), (0x003f0000) +#define AN_LTH60_COMMON_LT_CAPTURE_CFG_R_CAP_OFFSET_F (AN_LTH60_BASE + 0x4), (0xff000000) +#define AN_LTH60_COMMON_LT_CAPTURE_STATUS_R (AN_LTH60_BASE + 0x8) +#define AN_LTH60_COMMON_LT_CAPTURE_STATUS_R_CAP_ON_WORK_F (AN_LTH60_BASE + 0x8), (0x00000001) +#define AN_LTH60_COMMON_LT_CAPTURE_STATUS_R_CAP_TRIGGERED_F (AN_LTH60_BASE + 0x8), (0x00000002) +#define AN_LTH60_COMMON_LT_CAPTURE_STATUS_R_CAP_DONE_F (AN_LTH60_BASE + 0x8), (0x00000004) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA0_R (AN_LTH60_BASE + 0xc) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA0_R_DATA0_F (AN_LTH60_BASE + 0xc), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA1_R (AN_LTH60_BASE + 0x10) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA1_R_DATA1_F (AN_LTH60_BASE + 0x10), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA2_R (AN_LTH60_BASE + 0x14) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA2_R_DATA2_F (AN_LTH60_BASE + 0x14), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA3_R (AN_LTH60_BASE + 0x18) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA3_R_DATA3_F (AN_LTH60_BASE + 0x18), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA4_R (AN_LTH60_BASE + 0x1c) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA4_R_DATA4_F (AN_LTH60_BASE + 0x1c), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA5_R (AN_LTH60_BASE + 0x20) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA5_R_DATA5_F (AN_LTH60_BASE + 0x20), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA6_R (AN_LTH60_BASE + 0x24) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA6_R_DATA6_F (AN_LTH60_BASE + 0x24), (0xffffffff) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA7_R (AN_LTH60_BASE + 0x28) +#define AN_LTH60_COMMON_LT_CAPTURE_DATA7_R_DATA7_F (AN_LTH60_BASE + 0x28), (0xffffffff) +#define AN_LTH60_COMMON_SPARE_R (AN_LTH60_BASE + 0x30) +#define AN_LTH60_COMMON_SPARE_R_SPARE_F (AN_LTH60_BASE + 0x30), (0xffffffff) +#define AN_LTH60_COMMON_SPARE_CNT_R (AN_LTH60_BASE + 0x34) +#define AN_LTH60_COMMON_SPARE_CNT_R_CNT_F (AN_LTH60_BASE + 0x34), (0x0000ffff) +#define AN_LTH60_LT_LANE0_INT_STATUS_R (AN_LTH60_BASE + 0x100) +#define AN_LTH60_LT_LANE0_INT_STATUS_R_TRAIN_SUCCESS_F (AN_LTH60_BASE + 0x100), (0x00000001) +#define AN_LTH60_LT_LANE0_INT_STATUS_R_TRAIN_FAIL_F (AN_LTH60_BASE + 0x100), (0x00000002) +#define AN_LTH60_LT_LANE0_INT_STATUS_R_TRAIN_SOFT_CMD_TRIP_END_F (AN_LTH60_BASE + 0x100), (0x00000004) +#define AN_LTH60_LT_LANE0_INT_STATUS_R_TRAIN_SOFT_FETCH_EYE_F (AN_LTH60_BASE + 0x100), (0x00000008) +#define AN_LTH60_LT_LANE0_INT_STATUS_R_INIT_AUX_TIMER_OUT_F (AN_LTH60_BASE + 0x100), (0x00000010) +#define AN_LTH60_LT_LANE0_INT_ENABLE_R (AN_LTH60_BASE + 0x104) +#define AN_LTH60_LT_LANE0_INT_ENABLE_R_TRAIN_SUCCESS_F (AN_LTH60_BASE + 0x104), (0x00000001) +#define AN_LTH60_LT_LANE0_INT_ENABLE_R_TRAIN_FAIL_F (AN_LTH60_BASE + 0x104), (0x00000002) +#define AN_LTH60_LT_LANE0_INT_ENABLE_R_TRAIN_SOFT_CMD_TRIP_END_F (AN_LTH60_BASE + 0x104), (0x00000004) +#define AN_LTH60_LT_LANE0_INT_ENABLE_R_TRAIN_SOFT_FETCH_EYE_F (AN_LTH60_BASE + 0x104), (0x00000008) +#define AN_LTH60_LT_LANE0_INT_ENABLE_R_INIT_AUX_TIMER_OUT_F (AN_LTH60_BASE + 0x104), (0x00000010) +#define AN_LTH60_LT_LANE0_INT_SET_R (AN_LTH60_BASE + 0x108) +#define AN_LTH60_LT_LANE0_INT_SET_R_TRAIN_SUCCESS_F (AN_LTH60_BASE + 0x108), (0x00000001) +#define AN_LTH60_LT_LANE0_INT_SET_R_TRAIN_FAIL_F (AN_LTH60_BASE + 0x108), (0x00000002) +#define AN_LTH60_LT_LANE0_INT_SET_R_TRAIN_SOFT_CMD_TRIP_END_F (AN_LTH60_BASE + 0x108), (0x00000004) +#define AN_LTH60_LT_LANE0_INT_SET_R_TRAIN_SOFT_FETCH_EYE_F (AN_LTH60_BASE + 0x108), (0x00000008) +#define AN_LTH60_LT_LANE0_INT_SET_R_INIT_AUX_TIMER_OUT_F (AN_LTH60_BASE + 0x108), (0x00000010) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R (AN_LTH60_BASE + 0x10c) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TRAINING_ENABLE_F (AN_LTH60_BASE + 0x10c), (0x00000001) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TRAINING_MODE_F (AN_LTH60_BASE + 0x10c), (0x00000002) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_TRAIN_RESTART_F (AN_LTH60_BASE + 0x10c), (0x00000004) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_AP_LMT_MODE_F (AN_LTH60_BASE + 0x10c), (0x00000008) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_VPK_MODE_F (AN_LTH60_BASE + 0x10c), (0x00000010) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_AP_MAIN_MODE_F (AN_LTH60_BASE + 0x10c), (0x00000020) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TRAIN_INV_MAIN_F (AN_LTH60_BASE + 0x10c), (0x00000040) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TRAIN_INV_PRE_F (AN_LTH60_BASE + 0x10c), (0x00000080) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TRAIN_INV_POST_F (AN_LTH60_BASE + 0x10c), (0x00000100) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TRAIN_INV_PRE2_F (AN_LTH60_BASE + 0x10c), (0x00000200) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_PHASE1_TRIGGER_TIMER_F (AN_LTH60_BASE + 0x10c), (0x00ff0000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_MAN_DEC_F (AN_LTH60_BASE + 0x10c), (0x03000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_MARKER_DEC_F (AN_LTH60_BASE + 0x10c), (0x0c000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_RX_BIT_ORDER_F (AN_LTH60_BASE + 0x10c), (0x10000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG1_R_CFG_TX_BIT_ORDER_F (AN_LTH60_BASE + 0x10c), (0x20000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R (AN_LTH60_BASE + 0x110) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_CFG_INC_STEP_F (AN_LTH60_BASE + 0x110), (0x00000003) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_REMOTE_RX_READY_CHECK_EN_F (AN_LTH60_BASE + 0x110), (0x00000008) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_CFG_HCF_ENABLE_F (AN_LTH60_BASE + 0x110), (0x00000010) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_CFG_DATA_WIDTH_F (AN_LTH60_BASE + 0x110), (0x000000e0) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_CFG_LIMIT_2_F (AN_LTH60_BASE + 0x110), (0x0000ff00) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_CFG_LIMIT_1_F (AN_LTH60_BASE + 0x110), (0x00ff0000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_CFG_PRST_CHOOSE_F (AN_LTH60_BASE + 0x110), (0x03000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_RESET_TRAIN_TX_F (AN_LTH60_BASE + 0x110), (0x04000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_RESET_TRAIN_RX_F (AN_LTH60_BASE + 0x110), (0x08000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_RESET_SPI_F (AN_LTH60_BASE + 0x110), (0x10000000) +#define AN_LTH60_LT_LANE0_CONTROL_CFG2_R_FROZEN_INI_EN_F (AN_LTH60_BASE + 0x110), (0x40000000) +#define AN_LTH60_LT_LANE0_PAM4_CFG_R (AN_LTH60_BASE + 0x114) +#define AN_LTH60_LT_LANE0_PAM4_CFG_R_CFG_RX_SYMBOL_BIT_ORDER_F (AN_LTH60_BASE + 0x114), (0x00000001) +#define AN_LTH60_LT_LANE0_PAM4_CFG_R_CFG_TX_SYMBOL_BIT_ORDER_F (AN_LTH60_BASE + 0x114), (0x00000002) +#define AN_LTH60_LT_LANE0_PAM4_CFG_R_CFG_PRE2_SUPPORT_F (AN_LTH60_BASE + 0x114), (0x10000000) +#define AN_LTH60_LT_LANE0_PAM4_CFG_R_CFG_TRAIN_PRE2_ENB_F (AN_LTH60_BASE + 0x114), (0x20000000) +#define AN_LTH60_LT_LANE0_PAM4_CFG_R_CFG_MODE_CHOOSE_F (AN_LTH60_BASE + 0x114), (0xc0000000) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R (AN_LTH60_BASE + 0x118) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_CMD_START_F (AN_LTH60_BASE + 0x118), (0x00000001) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_POST_CMD_F (AN_LTH60_BASE + 0x118), (0x00000030) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_MAIN_CMD_F (AN_LTH60_BASE + 0x118), (0x000000c0) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_PRE_CMD_F (AN_LTH60_BASE + 0x118), (0x00000300) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_PRE2_CMD_F (AN_LTH60_BASE + 0x118), (0x00000c00) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_PRESET_CMD_F (AN_LTH60_BASE + 0x118), (0x00003000) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_START_BER_CMD_F (AN_LTH60_BASE + 0x118), (0x00004000) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_START_SNR_CMD_F (AN_LTH60_BASE + 0x118), (0x00008000) +#define AN_LTH60_LT_LANE0_SOFT_TRAIN_CFG_R_CFG_RECEIVE_READY_CMD_F (AN_LTH60_BASE + 0x118), (0x80000000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R (AN_LTH60_BASE + 0x11c) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_TRAIN_EYE_MARGIN_MAX_F (AN_LTH60_BASE + 0x11c), (0x00007fff) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_TRAIN_CUR_CMD_KEEP_F (AN_LTH60_BASE + 0x11c), (0x00010000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_INITIAL_OR_PRESET_ONLY_F (AN_LTH60_BASE + 0x11c), (0x00020000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_CFG_PRE2_ITERATION_F (AN_LTH60_BASE + 0x11c), (0x00700000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_CFG_PAM4_MAXIMUM_WAIT_TIMER_F (AN_LTH60_BASE + 0x11c), (0x00800000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_CFG_SETTLE_WAIT_TIMER_F (AN_LTH60_BASE + 0x11c), (0x7f000000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG1_R_CFG_SINGAL_METRIC_F (AN_LTH60_BASE + 0x11c), (0x80000000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG2_R (AN_LTH60_BASE + 0x120) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG2_R_TRAIN_TERMINATE_TIMER_F (AN_LTH60_BASE + 0x120), (0x0000ffff) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG2_R_TRAIN_TERMINATE_EN_F (AN_LTH60_BASE + 0x120), (0x00010000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG2_R_CFG_INIT_TIMER_F (AN_LTH60_BASE + 0x120), (0x1ff00000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG3_R (AN_LTH60_BASE + 0x124) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG3_R_TRAIN_ITERATION_TIMER_F (AN_LTH60_BASE + 0x124), (0x000001ff) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG3_R_TRAIN_ITERATION_CTL_EN_F (AN_LTH60_BASE + 0x124), (0x00010000) +#define AN_LTH60_LT_LANE0_HARD_TRAIN_CFG3_R_CFG_INIT_AUX_TIMER_F (AN_LTH60_BASE + 0x124), (0x3ff00000) +#define AN_LTH60_LT_LANE0_MARKER_THRESHOLD_CFG_R (AN_LTH60_BASE + 0x128) +#define AN_LTH60_LT_LANE0_MARKER_THRESHOLD_CFG_R_BAD_MARKER_THD_F (AN_LTH60_BASE + 0x128), (0x0000000f) +#define AN_LTH60_LT_LANE0_MARKER_THRESHOLD_CFG_R_GOOD_MARKER_THD_F (AN_LTH60_BASE + 0x128), (0x00000070) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG1_R (AN_LTH60_BASE + 0x12c) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG1_R_CFG_TRAIN_PRESET3_PRE2_F (AN_LTH60_BASE + 0x12c), (0x000000ff) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG1_R_CFG_TRAIN_PRESET2_PRE2_F (AN_LTH60_BASE + 0x12c), (0x0000ff00) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG1_R_CFG_TRAIN_PRESET1_PRE2_F (AN_LTH60_BASE + 0x12c), (0x00ff0000) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG2_R (AN_LTH60_BASE + 0x130) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG2_R_CFG_TRAIN_MIN_PRE2_F (AN_LTH60_BASE + 0x130), (0x000000ff) +#define AN_LTH60_LT_LANE0_PRE2_CURSOR_CFG2_R_CFG_TRAIN_MAX_PRE2_F (AN_LTH60_BASE + 0x130), (0x0000ff00) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG1_R (AN_LTH60_BASE + 0x134) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG1_R_CFG_TRAIN_PRESET3_PRE_F (AN_LTH60_BASE + 0x134), (0x000000ff) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG1_R_CFG_TRAIN_PRESET2_PRE_F (AN_LTH60_BASE + 0x134), (0x0000ff00) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG1_R_CFG_TRAIN_PRESET1_PRE_F (AN_LTH60_BASE + 0x134), (0x00ff0000) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG1_R_CFG_TRAIN_INIT_PRE_F (AN_LTH60_BASE + 0x134), (0xff000000) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG2_R (AN_LTH60_BASE + 0x138) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG2_R_CFG_TRAIN_MIN_PRE_F (AN_LTH60_BASE + 0x138), (0x000000ff) +#define AN_LTH60_LT_LANE0_PRE_CURSOR_CFG2_R_CFG_TRAIN_MAX_PRE_F (AN_LTH60_BASE + 0x138), (0x0000ff00) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG1_R (AN_LTH60_BASE + 0x13c) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG1_R_CFG_TRAIN_PRESET3_POST_F (AN_LTH60_BASE + 0x13c), (0x000000ff) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG1_R_CFG_TRAIN_PRESET2_POST_F (AN_LTH60_BASE + 0x13c), (0x0000ff00) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG1_R_CFG_TRAIN_PRESET1_POST_F (AN_LTH60_BASE + 0x13c), (0x00ff0000) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG1_R_CFG_TRAIN_INIT_POST_F (AN_LTH60_BASE + 0x13c), (0xff000000) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG2_R (AN_LTH60_BASE + 0x140) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG2_R_CFG_TRAIN_MIN_POST_F (AN_LTH60_BASE + 0x140), (0x000000ff) +#define AN_LTH60_LT_LANE0_POST_CURSOR_CFG2_R_CFG_TRAIN_MAX_POST_F (AN_LTH60_BASE + 0x140), (0x0000ff00) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG1_R (AN_LTH60_BASE + 0x144) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG1_R_CFG_TRAIN_PRESET3_MAIN_F (AN_LTH60_BASE + 0x144), (0x000000ff) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG1_R_CFG_TRAIN_PRESET2_MAIN_F (AN_LTH60_BASE + 0x144), (0x0000ff00) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG1_R_CFG_TRAIN_PRESET1_MAIN_F (AN_LTH60_BASE + 0x144), (0x00ff0000) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG1_R_CFG_TRAIN_INIT_MAIN_F (AN_LTH60_BASE + 0x144), (0xff000000) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG2_R (AN_LTH60_BASE + 0x148) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG2_R_CFG_TRAIN_MIN_MAIN_F (AN_LTH60_BASE + 0x148), (0x000000ff) +#define AN_LTH60_LT_LANE0_MAIN_CURSOR_CFG2_R_CFG_TRAIN_MAX_MAIN_F (AN_LTH60_BASE + 0x148), (0x0000ff00) +#define AN_LTH60_LT_LANE0_PRBS_CFG_R (AN_LTH60_BASE + 0x14c) +#define AN_LTH60_LT_LANE0_PRBS_CFG_R_CFG_PRBS_SEED_CUSTOM_F (AN_LTH60_BASE + 0x14c), (0x000007ff) +#define AN_LTH60_LT_LANE0_PRBS_CFG_R_CFG_PRBS_SEED_FIXED_F (AN_LTH60_BASE + 0x14c), (0x00001800) +#define AN_LTH60_LT_LANE0_PRBS_CFG_R_CFG_PRBS_SEED_MODE_F (AN_LTH60_BASE + 0x14c), (0x0000e000) +#define AN_LTH60_LT_LANE0_PRBS_CFG_R_CFG_PRBS_AUTO_DETECT_MODE_F (AN_LTH60_BASE + 0x14c), (0x00010000) +#define AN_LTH60_LT_LANE0_SPI_CFG_R (AN_LTH60_BASE + 0x150) +#define AN_LTH60_LT_LANE0_SPI_CFG_R_CFG_EYE_SCAN_TIMER_F (AN_LTH60_BASE + 0x150), (0x000003ff) +#define AN_LTH60_LT_LANE0_SPI_CFG_R_CFG_EYE_SCAN_TIMER_ENB_F (AN_LTH60_BASE + 0x150), (0x00000400) +#define AN_LTH60_LT_LANE0_SPI_CFG_R_CFG_READ_DELAY_F (AN_LTH60_BASE + 0x150), (0x7c000000) +#define AN_LTH60_LT_LANE0_SNR_BER_CFG_R (AN_LTH60_BASE + 0x154) +#define AN_LTH60_LT_LANE0_SNR_BER_CFG_R_CFG_SNR_NUM_F (AN_LTH60_BASE + 0x154), (0x000001ff) +#define AN_LTH60_LT_LANE0_SNR_BER_CFG_R_CFG_BER_NUM_SEARCH_UPDATE_F (AN_LTH60_BASE + 0x154), (0x001ffc00) +#define AN_LTH60_LT_LANE0_SNR_BER_CFG_R_CFG_BER_NUM_SDS_UPDATE_F (AN_LTH60_BASE + 0x154), (0xffe00000) +#define AN_LTH60_LT_LANE0_TIMER_CNT_CFG_R (AN_LTH60_BASE + 0x158) +#define AN_LTH60_LT_LANE0_TIMER_CNT_CFG_R_TRAIN_TIMER_1MS_UNIT_F (AN_LTH60_BASE + 0x158), (0x001fffff) +#define AN_LTH60_LT_LANE0_TIMER_CNT_CFG_R_TRAIN_TIMER_1US_UNIT_F (AN_LTH60_BASE + 0x158), (0xffe00000) +#define AN_LTH60_LT_LANE0_TIMER_CFG1_R (AN_LTH60_BASE + 0x15c) +#define AN_LTH60_LT_LANE0_TIMER_CFG1_R_CFG_TRAIN_MAX_TIMER_F (AN_LTH60_BASE + 0x15c), (0x0000ffff) +#define AN_LTH60_LT_LANE0_TIMER_CFG1_R_CFG_TRAIN_MAX_TIMER_ENB_F (AN_LTH60_BASE + 0x15c), (0x00010000) +#define AN_LTH60_LT_LANE0_TIMER_CFG1_R_CFG_LINK_WAIT_TIMER_F (AN_LTH60_BASE + 0x15c), (0x03fe0000) +#define AN_LTH60_LT_LANE0_TIMER_CFG2_R (AN_LTH60_BASE + 0x160) +#define AN_LTH60_LT_LANE0_TIMER_CFG2_R_CFG_MAX_WAIT_TIMER_F (AN_LTH60_BASE + 0x160), (0x0000ffff) +#define AN_LTH60_LT_LANE0_TIMER_CFG2_R_CFG_TRAIN_HOLDOFF_TIMER_F (AN_LTH60_BASE + 0x160), (0x007f0000) +#define AN_LTH60_LT_LANE0_DME_STATUS_R (AN_LTH60_BASE + 0x164) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_TRAINING_COMPLETE_F (AN_LTH60_BASE + 0x164), (0x00000001) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_FRAME_LOCK_F (AN_LTH60_BASE + 0x164), (0x00000002) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_TRAINING_FAILURE_F (AN_LTH60_BASE + 0x164), (0x00000004) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_LOCAL_TRAINING_COMPLETE_F (AN_LTH60_BASE + 0x164), (0x00000008) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_REMOTE_TRAINING_COMPLETE_F (AN_LTH60_BASE + 0x164), (0x00000010) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_REMOTE_TF_LOCK_F (AN_LTH60_BASE + 0x164), (0x00000020) +#define AN_LTH60_LT_LANE0_DME_STATUS_R_PRBS_MODE_F (AN_LTH60_BASE + 0x164), (0x000000c0) +#define AN_LTH60_LT_LANE0_CUR_EYE_MARGIN_STATUS_R (AN_LTH60_BASE + 0x168) +#define AN_LTH60_LT_LANE0_CUR_EYE_MARGIN_STATUS_R_MARGIN_VALUE_F (AN_LTH60_BASE + 0x168), (0x7fffffff) +#define AN_LTH60_LT_LANE0_CUR_EYE_MARGIN_STATUS_R_EYE_SCAN_COMPLETE_F (AN_LTH60_BASE + 0x168), (0x80000000) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R (AN_LTH60_BASE + 0x16c) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_STAT_POST_F (AN_LTH60_BASE + 0x16c), (0x00000003) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_STAT_MAIN_F (AN_LTH60_BASE + 0x16c), (0x0000000c) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_STAT_PRE_F (AN_LTH60_BASE + 0x16c), (0x00000030) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_MODULATION_DONE_F (AN_LTH60_BASE + 0x16c), (0x00000200) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_COEF_ECHO_F (AN_LTH60_BASE + 0x16c), (0x00038000) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_COEF_STATUS_F (AN_LTH60_BASE + 0x16c), (0x00700000) +#define AN_LTH60_LT_LANE0_RMT_STATUS_R_RMT_PRE2_NOT_SUPPORT_F (AN_LTH60_BASE + 0x16c), (0x80000000) +#define AN_LTH60_LT_LANE0_CUR_TAP_WEIGHT_STATUS_R (AN_LTH60_BASE + 0x170) +#define AN_LTH60_LT_LANE0_CUR_TAP_WEIGHT_STATUS_R_CUR_POST_F (AN_LTH60_BASE + 0x170), (0x000000ff) +#define AN_LTH60_LT_LANE0_CUR_TAP_WEIGHT_STATUS_R_CUR_MAIN_F (AN_LTH60_BASE + 0x170), (0x0000ff00) +#define AN_LTH60_LT_LANE0_CUR_TAP_WEIGHT_STATUS_R_CUR_PRE_F (AN_LTH60_BASE + 0x170), (0x00ff0000) +#define AN_LTH60_LT_LANE0_CUR_TAP_WEIGHT_STATUS_R_CUR_PRE2_F (AN_LTH60_BASE + 0x170), (0xff000000) +#define AN_LTH60_LT_LANE0_STATUS_R (AN_LTH60_BASE + 0x174) +#define AN_LTH60_LT_LANE0_STATUS_R_RMT_STAT_POST_SOFT_F (AN_LTH60_BASE + 0x174), (0x00000003) +#define AN_LTH60_LT_LANE0_STATUS_R_RMT_STAT_MAIN_SOFT_F (AN_LTH60_BASE + 0x174), (0x0000000c) +#define AN_LTH60_LT_LANE0_STATUS_R_RMT_STAT_PRE_SOFT_F (AN_LTH60_BASE + 0x174), (0x00000030) +#define AN_LTH60_LT_LANE0_STATUS_R_RMT_COEF_SOFT_F (AN_LTH60_BASE + 0x174), (0x00000700) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R (AN_LTH60_BASE + 0x178) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R_TRAIN_STATE_F (AN_LTH60_BASE + 0x178), (0x00007fff) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R_SDS_ARB_STATE_F (AN_LTH60_BASE + 0x178), (0x000e0000) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R_PRE2_UPD_STATE_F (AN_LTH60_BASE + 0x178), (0x00700000) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R_PRE_UPD_STATE_F (AN_LTH60_BASE + 0x178), (0x03800000) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R_MAIN_UPD_STATE_F (AN_LTH60_BASE + 0x178), (0x1c000000) +#define AN_LTH60_LT_LANE0_DBG_INFO0_R_POST_UPD_STATE_F (AN_LTH60_BASE + 0x178), (0xe0000000) +#define AN_LTH60_LT_LANE0_DBG_INFO1_R (AN_LTH60_BASE + 0x17c) +#define AN_LTH60_LT_LANE0_DBG_INFO1_R_SEARCH_STATE_F (AN_LTH60_BASE + 0x17c), (0x00007fff) +#define AN_LTH60_LT_LANE0_DBG_INFO1_R_MEASURE_POS_F (AN_LTH60_BASE + 0x17c), (0x007f8000) +#define AN_LTH60_LT_LANE0_DBG_INFO1_R_MEASURE_POS2_F (AN_LTH60_BASE + 0x17c), (0x0f000000) +#define AN_LTH60_LT_LANE0_DBG_INFO1_R_SEARCH_STEP2_ACTIVE_F (AN_LTH60_BASE + 0x17c), (0x10000000) +#define AN_LTH60_LT_LANE0_DBG_INFO2_R (AN_LTH60_BASE + 0x180) +#define AN_LTH60_LT_LANE0_DBG_INFO2_R_MAX_WAIT_TIMER_ENTER_TRAINL_F (AN_LTH60_BASE + 0x180), (0x0000ffff) +#define AN_LTH60_LT_LANE0_DBG_INFO2_R_MAX_WAIT_TIMER_EXIT_TRAINL_F (AN_LTH60_BASE + 0x180), (0xffff0000) +#define AN_LTH60_LT_LANE0_DBG_INFO3_R (AN_LTH60_BASE + 0x184) +#define AN_LTH60_LT_LANE0_DBG_INFO3_R_MAX_WAIT_TIMER_ENTER_TRAINR_F (AN_LTH60_BASE + 0x184), (0x0000ffff) +#define AN_LTH60_LT_LANE0_DBG_INFO3_R_MAX_WAIT_TIMER_EXIT_TRAINR_F (AN_LTH60_BASE + 0x184), (0xffff0000) +#define AN_LTH60_LT_LANE0_DBG_INFO4_R (AN_LTH60_BASE + 0x188) +#define AN_LTH60_LT_LANE0_DBG_INFO4_R_SPI_COEFF_UPD_STATE_F (AN_LTH60_BASE + 0x188), (0x00000003) +#define AN_LTH60_LT_LANE0_DBG_INFO4_R_SPI_EYE_SCAN_STATE_F (AN_LTH60_BASE + 0x188), (0x0000000c) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R (AN_LTH60_BASE + 0x18c) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_SUM_COMPARE_CNT_F (AN_LTH60_BASE + 0x18c), (0x000001ff) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_LOCK_RESTART_CNT_F (AN_LTH60_BASE + 0x18c), (0x000f0000) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_MARGIN_MAX_CNT_F (AN_LTH60_BASE + 0x18c), (0x00f00000) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_MARGIN_ZERO_CNT_F (AN_LTH60_BASE + 0x18c), (0x0f000000) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_RETRY_MARGIN_MAX_F (AN_LTH60_BASE + 0x18c), (0x10000000) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_RETRY_MARGIN_ZERO_F (AN_LTH60_BASE + 0x18c), (0x20000000) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_RESPONSE_2MS_VIOLATION_F (AN_LTH60_BASE + 0x18c), (0x40000000) +#define AN_LTH60_LT_LANE0_DBG_INFO5_R_RESPONSE_50MS_VIOLATION_F (AN_LTH60_BASE + 0x18c), (0x80000000) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R (AN_LTH60_BASE + 0x190) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_MAIN_MIN_CNT_F (AN_LTH60_BASE + 0x190), (0x00000003) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_MAIN_MAX_CNT_F (AN_LTH60_BASE + 0x190), (0x0000000c) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_POST_MIN_CNT_F (AN_LTH60_BASE + 0x190), (0x00000030) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_POST_MAX_CNT_F (AN_LTH60_BASE + 0x190), (0x000000c0) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_PRE_MIN_CNT_F (AN_LTH60_BASE + 0x190), (0x00000300) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_PRE_MAX_CNT_F (AN_LTH60_BASE + 0x190), (0x00000c00) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_PRE2_MIN_CNT_F (AN_LTH60_BASE + 0x190), (0x00003000) +#define AN_LTH60_LT_LANE0_DBG_INFO6_R_PRE2_MAX_CNT_F (AN_LTH60_BASE + 0x190), (0x0000c000) +#define AN_LTH60_LT_LANE0_SNR_INFO1_R (AN_LTH60_BASE + 0x194) +#define AN_LTH60_LT_LANE0_SNR_INFO1_R_SNR_BEST_F (AN_LTH60_BASE + 0x194), (0x7fffffff) +#define AN_LTH60_LT_LANE0_SNR_INFO2_R (AN_LTH60_BASE + 0x198) +#define AN_LTH60_LT_LANE0_SNR_INFO2_R_SNR_WORST_F (AN_LTH60_BASE + 0x198), (0x7fffffff) +#define AN_LTH60_LT_LANE0_DME_INFO_R (AN_LTH60_BASE + 0x19c) +#define AN_LTH60_LT_LANE0_DME_INFO_R_EYE_SCAN_TIMEOUT_F (AN_LTH60_BASE + 0x19c), (0x00000001) +#define AN_LTH60_LT_LANE0_DME_INFO_R_REPEAT_POS_DONE_F (AN_LTH60_BASE + 0x19c), (0x00000004) +#define AN_LTH60_LT_LANE0_DME_INFO_R_TRAIN_COMP_CNT_DONE_F (AN_LTH60_BASE + 0x19c), (0x00000010) +#define AN_LTH60_LT_LANE0_DME_INFO_R_TRAIN_TIME_DONE_F (AN_LTH60_BASE + 0x19c), (0x00000020) +#define AN_LTH60_LT_LANE0_DME_INFO_R_MAX_BOUNDARY_DONE_F (AN_LTH60_BASE + 0x19c), (0x00000040) +#define AN_LTH60_LT_LANE0_DME_INFO_R_PRESET_INI_CMD_ERR_F (AN_LTH60_BASE + 0x19c), (0x00000080) +#define AN_LTH60_LT_LANE0_DME_INFO_R_PRESET_INI_ERR_F (AN_LTH60_BASE + 0x19c), (0x00000100) +#define AN_LTH60_LT_LANE0_FRAME_LOCK_FSM_INFO_R (AN_LTH60_BASE + 0x1a0) +#define AN_LTH60_LT_LANE0_FRAME_LOCK_FSM_INFO_R_STATE_F (AN_LTH60_BASE + 0x1a0), (0x3fffffff) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO1_R (AN_LTH60_BASE + 0x1a4) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO1_R_PRE_HIS_F (AN_LTH60_BASE + 0x1a4), (0x000000ff) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO1_R_MAIN_HIS_F (AN_LTH60_BASE + 0x1a4), (0x0000ff00) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO1_R_POST_HIS_F (AN_LTH60_BASE + 0x1a4), (0x00ff0000) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO1_R_PRESET_HIS_F (AN_LTH60_BASE + 0x1a4), (0x03000000) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO1_R_INIT_HIS_F (AN_LTH60_BASE + 0x1a4), (0x0c000000) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO2_R (AN_LTH60_BASE + 0x1a8) +#define AN_LTH60_LT_LANE0_TX_CMD_INFO2_R_CMD_INTE_HIS_F (AN_LTH60_BASE + 0x1a8), (0x000001ff) +#define AN_LTH60_LT_LANE0_TFL_PHASE_INFO_R (AN_LTH60_BASE + 0x1ac) +#define AN_LTH60_LT_LANE0_TFL_PHASE_INFO_R_TRAINING_FRAME_LOCKED_F (AN_LTH60_BASE + 0x1ac), (0x00000001) +#define AN_LTH60_LT_LANE0_TFL_PHASE_INFO_R_PHASE3_REACHED_F (AN_LTH60_BASE + 0x1ac), (0x00000002) +#define AN_LTH60_LT_LANE0_TFL_PHASE_INFO_R_PHASE4_REACHED_F (AN_LTH60_BASE + 0x1ac), (0x00000004) +#define AN_LTH60_LT_LANE0_DME_CNT_R (AN_LTH60_BASE + 0x1b0) +#define AN_LTH60_LT_LANE0_DME_CNT_R_DME_ERROR_CNT_F (AN_LTH60_BASE + 0x1b0), (0x0000000f) +#define AN_LTH60_LT_LANE0_DME_CNT_R_FRAME_LOCK_LOSS_CNT_F (AN_LTH60_BASE + 0x1b0), (0x0000ff00) +#define AN_LTH60_LT_LANE0_DME_CNT_R_RMT_RDY_FALL_CNT_F (AN_LTH60_BASE + 0x1b0), (0x00030000) +#define AN_LTH60_LT_LANE0_DME_CNT_R_RMT_LOCK_FALL_CNT_F (AN_LTH60_BASE + 0x1b0), (0x000c0000) +#define AN_LTH60_LT_LANE0_DME_CNT_R_RMT_PARITY_ERR_F (AN_LTH60_BASE + 0x1b0), (0x00100000) +#define AN_LTH60_LT_LANE0_SM_DURATION0_CNT_R (AN_LTH60_BASE + 0x1b4) +#define AN_LTH60_LT_LANE0_SM_DURATION0_CNT_R_TRAIN_LOCAL_DURATION_F (AN_LTH60_BASE + 0x1b4), (0x0000ffff) +#define AN_LTH60_LT_LANE0_SM_DURATION0_CNT_R_TRAIN_REMOTE_DURATION_F (AN_LTH60_BASE + 0x1b4), (0xffff0000) +#define AN_LTH60_LT_LANE0_SM_DURATION1_CNT_R (AN_LTH60_BASE + 0x1b8) +#define AN_LTH60_LT_LANE0_SM_DURATION1_CNT_R_SEND_TRAINING_DURATION_F (AN_LTH60_BASE + 0x1b8), (0x0000ffff) +#define AN_LTH60_LT_LANE0_SM_DURATION1_CNT_R_TRAIN_WHOLE_DURATION_F (AN_LTH60_BASE + 0x1b8), (0xffff0000) +#define AN_LTH60_LT_LANE0_SPARE_R (AN_LTH60_BASE + 0x1c0) +#define AN_LTH60_LT_LANE0_SPARE_R_SPARE_F (AN_LTH60_BASE + 0x1c0), (0xffffffff) +#define AN_LTH60_LT_LANE0_SPARE_CNT_R (AN_LTH60_BASE + 0x1c4) +#define AN_LTH60_LT_LANE0_SPARE_CNT_R_CNT_F (AN_LTH60_BASE + 0x1c4), (0x0000ffff) +#define AN_LTH60_AN_LANE0_INT_STATUS_R (AN_LTH60_BASE + 0x900) +#define AN_LTH60_AN_LANE0_INT_STATUS_R_AN_SUCCESS_F (AN_LTH60_BASE + 0x900), (0x00000001) +#define AN_LTH60_AN_LANE0_INT_STATUS_R_AN_FAIL_F (AN_LTH60_BASE + 0x900), (0x00000002) +#define AN_LTH60_AN_LANE0_INT_STATUS_R_AN_UPDATE_F (AN_LTH60_BASE + 0x900), (0x00000004) +#define AN_LTH60_AN_LANE0_INT_STATUS_R_AN_NO_HCD_F (AN_LTH60_BASE + 0x900), (0x00000008) +#define AN_LTH60_AN_LANE0_INT_ENABLE_R (AN_LTH60_BASE + 0x904) +#define AN_LTH60_AN_LANE0_INT_ENABLE_R_AN_SUCCESS_F (AN_LTH60_BASE + 0x904), (0x00000001) +#define AN_LTH60_AN_LANE0_INT_ENABLE_R_AN_FAIL_F (AN_LTH60_BASE + 0x904), (0x00000002) +#define AN_LTH60_AN_LANE0_INT_ENABLE_R_AN_UPDATE_F (AN_LTH60_BASE + 0x904), (0x00000004) +#define AN_LTH60_AN_LANE0_INT_ENABLE_R_AN_NO_HCD_F (AN_LTH60_BASE + 0x904), (0x00000008) +#define AN_LTH60_AN_LANE0_INT_SET_R (AN_LTH60_BASE + 0x908) +#define AN_LTH60_AN_LANE0_INT_SET_R_AN_SUCCESS_F (AN_LTH60_BASE + 0x908), (0x00000001) +#define AN_LTH60_AN_LANE0_INT_SET_R_AN_FAIL_F (AN_LTH60_BASE + 0x908), (0x00000002) +#define AN_LTH60_AN_LANE0_INT_SET_R_AN_UPDATE_F (AN_LTH60_BASE + 0x908), (0x00000004) +#define AN_LTH60_AN_LANE0_INT_SET_R_AN_NO_HCD_F (AN_LTH60_BASE + 0x908), (0x00000008) +#define AN_LTH60_AN_LANE0_MODE_CFG_R (AN_LTH60_BASE + 0x90c) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_TX_BIT_ORDER_REVERSE_F (AN_LTH60_BASE + 0x90c), (0x00000001) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_RX_BIT_ORDER_REVERSE_F (AN_LTH60_BASE + 0x90c), (0x00000002) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_TX_IDLE_PATTERN_F (AN_LTH60_BASE + 0x90c), (0x00000004) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_LINK_STATUS_SEL_F (AN_LTH60_BASE + 0x90c), (0x00000008) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_BIT_DIVISOR_F (AN_LTH60_BASE + 0x90c), (0x00001ff0) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_INCOMPATIBLE_LINK_F (AN_LTH60_BASE + 0x90c), (0x00002000) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_NP_NUMBER_F (AN_LTH60_BASE + 0x90c), (0x0000c000) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_TOGGLE_SEL_F (AN_LTH60_BASE + 0x90c), (0x00010000) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_PARALLEL_DETECT_DISABLE_F (AN_LTH60_BASE + 0x90c), (0x00020000) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_PARALLEL_DATA_WIDTH_F (AN_LTH60_BASE + 0x90c), (0x00780000) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_AN_LOSE_THD_F (AN_LTH60_BASE + 0x90c), (0x7f800000) +#define AN_LTH60_AN_LANE0_MODE_CFG_R_AN_LOSE_THD_ENABLE_F (AN_LTH60_BASE + 0x90c), (0x80000000) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R (AN_LTH60_BASE + 0x910) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R_AUTONEG_ENABLE_F (AN_LTH60_BASE + 0x910), (0x00000001) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R_AUTONEG_RESET_F (AN_LTH60_BASE + 0x910), (0x00000002) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R_AUTONEG_RESTART_F (AN_LTH60_BASE + 0x910), (0x00000004) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R_NEXT_PAGE_LOADED_F (AN_LTH60_BASE + 0x910), (0x00000008) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R_FORCE_NONCE_MISMATCH_F (AN_LTH60_BASE + 0x910), (0x00000020) +#define AN_LTH60_AN_LANE0_CTRL_CFG_R_TRANSMITTED_NONCE_SEL_F (AN_LTH60_BASE + 0x910), (0x00000040) +#define AN_LTH60_AN_LANE0_TIMER_0_CFG_R (AN_LTH60_BASE + 0x914) +#define AN_LTH60_AN_LANE0_TIMER_0_CFG_R_AUTONEG_WAIT_TIMER_F (AN_LTH60_BASE + 0x914), (0x0000ffff) +#define AN_LTH60_AN_LANE0_TIMER_0_CFG_R_BREAK_LINK_TIMER_F (AN_LTH60_BASE + 0x914), (0xffff0000) +#define AN_LTH60_AN_LANE0_TIMER_1_CFG_R (AN_LTH60_BASE + 0x918) +#define AN_LTH60_AN_LANE0_TIMER_1_CFG_R_LINK_FAIL_INHIBIT_TIMER0_F (AN_LTH60_BASE + 0x918), (0x00007fff) +#define AN_LTH60_AN_LANE0_TIMER_1_CFG_R_LINK_FAIL_INHIBIT_TIMER0_NO_EXPIRE_F (AN_LTH60_BASE + 0x918), (0x00008000) +#define AN_LTH60_AN_LANE0_TIMER_1_CFG_R_LINK_FAIL_INHIBIT_TIMER1_F (AN_LTH60_BASE + 0x918), (0x7fff0000) +#define AN_LTH60_AN_LANE0_TIMER_1_CFG_R_LINK_FAIL_INHIBIT_TIMER1_NO_EXPIRE_F (AN_LTH60_BASE + 0x918), (0x80000000) +#define AN_LTH60_AN_LANE0_TIMER_2_CFG_R (AN_LTH60_BASE + 0x91c) +#define AN_LTH60_AN_LANE0_TIMER_2_CFG_R_LINK_FAIL_INHIBIT_TIMER2_F (AN_LTH60_BASE + 0x91c), (0x00007fff) +#define AN_LTH60_AN_LANE0_TIMER_2_CFG_R_LINK_FAIL_INHIBIT_TIMER2_NO_EXPIRE_F (AN_LTH60_BASE + 0x91c), (0x00008000) +#define AN_LTH60_AN_LANE0_TIMER_2_CFG_R_LINK_FAIL_INHIBIT_TIMER3_F (AN_LTH60_BASE + 0x91c), (0x7fff0000) +#define AN_LTH60_AN_LANE0_TIMER_2_CFG_R_LINK_FAIL_INHIBIT_TIMER3_NO_EXPIRE_F (AN_LTH60_BASE + 0x91c), (0x80000000) +#define AN_LTH60_AN_LANE0_TIMER_3_CFG_R (AN_LTH60_BASE + 0x920) +#define AN_LTH60_AN_LANE0_TIMER_3_CFG_R_MAX_PAGE_TIMER_THD_F (AN_LTH60_BASE + 0x920), (0x000001ff) +#define AN_LTH60_AN_LANE0_TIMER_UNIT_CFG_R (AN_LTH60_BASE + 0x924) +#define AN_LTH60_AN_LANE0_TIMER_UNIT_CFG_R_UNIT_1MS_F (AN_LTH60_BASE + 0x924), (0x001fffff) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R (AN_LTH60_BASE + 0x928) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_SELECTOR_FIELD_F (AN_LTH60_BASE + 0x928), (0x0000001f) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_ECHOED_NONCE_F (AN_LTH60_BASE + 0x928), (0x000003e0) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_PAUSE_ABILITY_F (AN_LTH60_BASE + 0x928), (0x00001c00) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_REMOTE_FAULT_F (AN_LTH60_BASE + 0x928), (0x00002000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_ACKNOWLEDGE_F (AN_LTH60_BASE + 0x928), (0x00004000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_NEXT_PAGE_F (AN_LTH60_BASE + 0x928), (0x00008000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_TRANSMITTED_NONCE_F (AN_LTH60_BASE + 0x928), (0x001f0000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_FEC_ABILITY_F (AN_LTH60_BASE + 0x928), (0x00200000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_FEC_REQUEST_F (AN_LTH60_BASE + 0x928), (0x00400000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_G25_RSFEC_REQUEST_F (AN_LTH60_BASE + 0x928), (0x00800000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_G25_FEC_REQUEST_F (AN_LTH60_BASE + 0x928), (0x01000000) +#define AN_LTH60_AN_LANE0_BP_ABILITY0_CFG_R_G100_RSFEC_INT_REQUEST_F (AN_LTH60_BASE + 0x928), (0x02000000) +#define AN_LTH60_AN_LANE0_BP_ABILITY1_CFG_R (AN_LTH60_BASE + 0x92c) +#define AN_LTH60_AN_LANE0_BP_ABILITY1_CFG_R_TECHNOLOGY_ABILITY_F (AN_LTH60_BASE + 0x92c), (0x003fffff) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R (AN_LTH60_BASE + 0x930) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R_NP0_MESSAGE_CODE_F (AN_LTH60_BASE + 0x930), (0x000007ff) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R_NP0_TOGGLE_F (AN_LTH60_BASE + 0x930), (0x00000800) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R_NP0_ACKNOWLEDGE2_F (AN_LTH60_BASE + 0x930), (0x00001000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R_NP0_MESSAGE_PAGE_F (AN_LTH60_BASE + 0x930), (0x00002000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R_NP0_ACKNOWLEDGE_F (AN_LTH60_BASE + 0x930), (0x00004000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY0_CFG_R_NP0_NEXT_PAGE_F (AN_LTH60_BASE + 0x930), (0x00008000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY1_CFG_R (AN_LTH60_BASE + 0x934) +#define AN_LTH60_AN_LANE0_XNP_ABILITY1_CFG_R_NP0_UNFORMATTED_CODE_F (AN_LTH60_BASE + 0x934), (0xffffffff) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R (AN_LTH60_BASE + 0x938) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R_NP1_MESSAGE_CODE_F (AN_LTH60_BASE + 0x938), (0x000007ff) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R_NP1_TOGGLE_F (AN_LTH60_BASE + 0x938), (0x00000800) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R_NP1_ACKNOWLEDGE2_F (AN_LTH60_BASE + 0x938), (0x00001000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R_NP1_MESSAGE_PAGE_F (AN_LTH60_BASE + 0x938), (0x00002000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R_NP1_ACKNOWLEDGE_F (AN_LTH60_BASE + 0x938), (0x00004000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY2_CFG_R_NP1_NEXT_PAGE_F (AN_LTH60_BASE + 0x938), (0x00008000) +#define AN_LTH60_AN_LANE0_XNP_ABILITY3_CFG_R (AN_LTH60_BASE + 0x93c) +#define AN_LTH60_AN_LANE0_XNP_ABILITY3_CFG_R_NP1_UNFORMATTED_CODE_F (AN_LTH60_BASE + 0x93c), (0xffffffff) +#define AN_LTH60_AN_LANE0_LINK_STATUS_CFG_R (AN_LTH60_BASE + 0x940) +#define AN_LTH60_AN_LANE0_LINK_STATUS_CFG_R_LINK_UP_KX_F (AN_LTH60_BASE + 0x940), (0x00000001) +#define AN_LTH60_AN_LANE0_LINK_STATUS_CFG_R_LINK_UP_2P5G_KX_F (AN_LTH60_BASE + 0x940), (0x00000002) +#define AN_LTH60_AN_LANE0_LINK_STATUS_CFG_R_LINK_UP_KX4_F (AN_LTH60_BASE + 0x940), (0x00000004) +#define AN_LTH60_AN_LANE0_LINK_STATUS_CFG_R_LINK_UP_OTHER_F (AN_LTH60_BASE + 0x940), (0x00000008) +#define AN_LTH60_AN_LANE0_RX_SAMPLE_TOLERANCE_CFG_R (AN_LTH60_BASE + 0x944) +#define AN_LTH60_AN_LANE0_RX_SAMPLE_TOLERANCE_CFG_R_AN_MAX_DEV_F (AN_LTH60_BASE + 0x944), (0x000000ff) +#define AN_LTH60_AN_LANE0_RX_SAMPLE_TOLERANCE_CFG_R_AN_MIN_DEV_F (AN_LTH60_BASE + 0x944), (0x0000ff00) +#define AN_LTH60_AN_LANE0_STATUS_R (AN_LTH60_BASE + 0x948) +#define AN_LTH60_AN_LANE0_STATUS_R_LP_AUTONEG_ABLE_F (AN_LTH60_BASE + 0x948), (0x00000001) +#define AN_LTH60_AN_LANE0_STATUS_R_PAGE_RX_F (AN_LTH60_BASE + 0x948), (0x00000002) +#define AN_LTH60_AN_LANE0_STATUS_R_RENEW_PAGE_F (AN_LTH60_BASE + 0x948), (0x00000004) +#define AN_LTH60_AN_LANE0_STATUS_R_AUTONEG_COMPLETE_F (AN_LTH60_BASE + 0x948), (0x00000008) +#define AN_LTH60_AN_LANE0_STATUS_R_PARALLEL_DETECTION_FAULT_F (AN_LTH60_BASE + 0x948), (0x00000010) +#define AN_LTH60_AN_LANE0_STATUS_R_INCOMPATIBLE_LINK_F (AN_LTH60_BASE + 0x948), (0x00000020) +#define AN_LTH60_AN_LANE0_STATUS_R_AN_LINK_GOOD_F (AN_LTH60_BASE + 0x948), (0x00000040) +#define AN_LTH60_AN_LANE0_STATUS_R_FEC_NEGOTIATED_F (AN_LTH60_BASE + 0x948), (0x00000080) +#define AN_LTH60_AN_LANE0_STATUS_R_RSFEC_NEGOTIATED_F (AN_LTH60_BASE + 0x948), (0x00000100) +#define AN_LTH60_AN_LANE0_STATUS_R_PAUSE_NEGOTIATED_F (AN_LTH60_BASE + 0x948), (0x00000600) +#define AN_LTH60_AN_LANE0_STATUS_R_AN_ARB_STATE_HIS_F (AN_LTH60_BASE + 0x948), (0x7ffff800) +#define AN_LTH60_AN_LANE0_STATUS_R_RSFEC_INT_NEGOTIATED_F (AN_LTH60_BASE + 0x948), (0x80000000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R (AN_LTH60_BASE + 0x94c) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G1_KX_F (AN_LTH60_BASE + 0x94c), (0x00000003) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G10_KX4_F (AN_LTH60_BASE + 0x94c), (0x0000000c) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G10_KR_F (AN_LTH60_BASE + 0x94c), (0x00000030) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G40_KR4_F (AN_LTH60_BASE + 0x94c), (0x000000c0) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G40_CR4_F (AN_LTH60_BASE + 0x94c), (0x00000300) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G100_CR10_F (AN_LTH60_BASE + 0x94c), (0x00000c00) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G100_KP4_F (AN_LTH60_BASE + 0x94c), (0x00003000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G100_KR4_F (AN_LTH60_BASE + 0x94c), (0x0000c000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G100_CR4_F (AN_LTH60_BASE + 0x94c), (0x00030000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G25_KRCR_S_F (AN_LTH60_BASE + 0x94c), (0x000c0000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G25_KRCR_F (AN_LTH60_BASE + 0x94c), (0x00300000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G2P5_KX_F (AN_LTH60_BASE + 0x94c), (0x00c00000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G5_KR_F (AN_LTH60_BASE + 0x94c), (0x03000000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G50_KR_CR_F (AN_LTH60_BASE + 0x94c), (0x0c000000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G100_KR2_CR2_F (AN_LTH60_BASE + 0x94c), (0x30000000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL0_STATUS_R_G200_KR4_CR4_F (AN_LTH60_BASE + 0x94c), (0xc0000000) +#define AN_LTH60_AN_LANE0_LINK_CONTROL1_STATUS_R (AN_LTH60_BASE + 0x950) +#define AN_LTH60_AN_LANE0_LINK_CONTROL1_STATUS_R_G100_CR_KR_F (AN_LTH60_BASE + 0x950), (0x00000003) +#define AN_LTH60_AN_LANE0_LINK_CONTROL1_STATUS_R_G200_CR2_KR2_F (AN_LTH60_BASE + 0x950), (0x0000000c) +#define AN_LTH60_AN_LANE0_LINK_CONTROL1_STATUS_R_G400_CR4_KR4_F (AN_LTH60_BASE + 0x950), (0x00000030) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R (AN_LTH60_BASE + 0x954) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_SELECTOR_FIELD_F (AN_LTH60_BASE + 0x954), (0x0000001f) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_ECHOED_NONCE_F (AN_LTH60_BASE + 0x954), (0x000003e0) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_PAUSE_ABILITY_F (AN_LTH60_BASE + 0x954), (0x00001c00) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_REMOTE_FAULT_F (AN_LTH60_BASE + 0x954), (0x00002000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_ACKNOWLEDGE_F (AN_LTH60_BASE + 0x954), (0x00004000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_NEXT_PAGE_F (AN_LTH60_BASE + 0x954), (0x00008000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_TRANSMITTED_NONCE_F (AN_LTH60_BASE + 0x954), (0x001f0000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_FEC_ABILITY_F (AN_LTH60_BASE + 0x954), (0x00200000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_FEC_REQUEST_F (AN_LTH60_BASE + 0x954), (0x00400000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_G25_RSFEC_REQUEST_F (AN_LTH60_BASE + 0x954), (0x00800000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_G25_FEC_REQUEST_F (AN_LTH60_BASE + 0x954), (0x01000000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY0_STATUS_R_G100_RSFEC_INT_REQUEST_F (AN_LTH60_BASE + 0x954), (0x02000000) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY1_STATUS_R (AN_LTH60_BASE + 0x958) +#define AN_LTH60_AN_LANE0_LP_BP_ABILITY1_STATUS_R_TECHNOLOGY_ABILITY_F (AN_LTH60_BASE + 0x958), (0x003fffff) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R (AN_LTH60_BASE + 0x95c) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R_NP0_MESSAGE_CODE_F (AN_LTH60_BASE + 0x95c), (0x000007ff) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R_NP0_TOGGLE_F (AN_LTH60_BASE + 0x95c), (0x00000800) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R_NP0_ACKNOWLEDGE2_F (AN_LTH60_BASE + 0x95c), (0x00001000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R_NP0_MESSAGE_PAGE_F (AN_LTH60_BASE + 0x95c), (0x00002000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R_NP0_ACKNOWLEDGE_F (AN_LTH60_BASE + 0x95c), (0x00004000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY0_STATUS_R_NP0_NEXT_PAGE_F (AN_LTH60_BASE + 0x95c), (0x00008000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY1_STATUS_R (AN_LTH60_BASE + 0x960) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY1_STATUS_R_NP0_UNFORMATTED_CODE_F (AN_LTH60_BASE + 0x960), (0xffffffff) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R (AN_LTH60_BASE + 0x964) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R_NP1_MESSAGE_CODE_F (AN_LTH60_BASE + 0x964), (0x000007ff) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R_NP1_TOGGLE_F (AN_LTH60_BASE + 0x964), (0x00000800) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R_NP1_ACKNOWLEDGE2_F (AN_LTH60_BASE + 0x964), (0x00001000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R_NP1_MESSAGE_PAGE_F (AN_LTH60_BASE + 0x964), (0x00002000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R_NP1_ACKNOWLEDGE_F (AN_LTH60_BASE + 0x964), (0x00004000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY2_STATUS_R_NP1_NEXT_PAGE_F (AN_LTH60_BASE + 0x964), (0x00008000) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY3_STATUS_R (AN_LTH60_BASE + 0x968) +#define AN_LTH60_AN_LANE0_LP_XNP_ABILITY3_STATUS_R_NP1_UNFORMATTED_CODE_F (AN_LTH60_BASE + 0x968), (0xffffffff) +#define AN_LTH60_AN_LANE0_RX_DME_STAT_CNT_R (AN_LTH60_BASE + 0x96c) +#define AN_LTH60_AN_LANE0_RX_DME_STAT_CNT_R_TWO_TRANS_ERR_F (AN_LTH60_BASE + 0x96c), (0x0000000f) +#define AN_LTH60_AN_LANE0_RX_DME_STAT_CNT_R_MORE_TRANS_ERR_F (AN_LTH60_BASE + 0x96c), (0x000000f0) +#define AN_LTH60_AN_LANE0_RX_DME_STAT_CNT_R_AN_RX_STATE_F (AN_LTH60_BASE + 0x96c), (0x000fff00) +#define AN_LTH60_AN_LANE0_DBG_INFO_R (AN_LTH60_BASE + 0x970) +#define AN_LTH60_AN_LANE0_DBG_INFO_R_AN_RX_IDLE_CNT_F (AN_LTH60_BASE + 0x970), (0x0000000f) +#define AN_LTH60_AN_LANE0_DBG_INFO_R_AN_CONSISTENCY_NMATCH_CNT_F (AN_LTH60_BASE + 0x970), (0x000000f0) +#define AN_LTH60_AN_LANE0_DBG_INFO_R_AN_NPAGE_CNT_PREVIOUS_F (AN_LTH60_BASE + 0x970), (0x00000f00) +#define AN_LTH60_AN_LANE0_DBG_INFO_R_AN_NPAGE_CNT_FINAL_F (AN_LTH60_BASE + 0x970), (0x0000f000) +#define AN_LTH60_AN_LANE0_DBG_INFO_R_AN_LOSE_CNT_F (AN_LTH60_BASE + 0x970), (0x000f0000) +#define AN_LTH60_AN_LANE0_DBG_TIMER_R (AN_LTH60_BASE + 0x974) +#define AN_LTH60_AN_LANE0_DBG_TIMER_R_AN_GOOD_CHECK_CNT_F (AN_LTH60_BASE + 0x974), (0x0000ffff) +#define AN_LTH60_AN_LANE0_SPARE_R (AN_LTH60_BASE + 0x978) +#define AN_LTH60_AN_LANE0_SPARE_R_SPARE_F (AN_LTH60_BASE + 0x978), (0xffffffff) +#define AN_LTH60_AN_LANE0_SPARE_CNT_R (AN_LTH60_BASE + 0x97c) +#define AN_LTH60_AN_LANE0_SPARE_CNT_R_CNT_F (AN_LTH60_BASE + 0x97c), (0x0000ffff) + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_com_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_com_offset.h new file mode 100644 index 000000000..2b57d2382 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_com_offset.h @@ -0,0 +1,33 @@ +#ifndef MAC_REG_COM_H +#define MAC_REG_COM_H + +/* Base address of Module's Register */ +#define CSR_COM_BASE (0x30000) + +#define CSR_COM_IP_VER (CSR_COM_BASE + 0x0) +#define CSR_COM_IP_MD5_ (CSR_COM_BASE + 0x10) +#define CSR_COM_INT_STATUS (CSR_COM_BASE + 0x20) +#define CSR_COM_INT_ENABLE (CSR_COM_BASE + 0x24) +#define CSR_COM_MODE (CSR_COM_BASE + 0x28) +#define CSR_COM_RST_DLY_CFG (CSR_COM_BASE + 0x2c) +#define CSR_COM_BLK_RSTN_LOGIC (CSR_COM_BASE + 0x30) +#define CSR_COM_BLK_RSTN_CFG (CSR_COM_BASE + 0x34) +#define CSR_COM_PHY_RSTN_LOGIC (CSR_COM_BASE + 0x40) +#define CSR_COM_PHY_RSTN_CFG (CSR_COM_BASE + 0x60) +#define CSR_COM_PORT_RSTN_LOGIC (CSR_COM_BASE + 0x80) +#define CSR_COM_CLK_GATE_CTRL (CSR_COM_BASE + 0xa0) +#define CSR_COM_CLK_GATE_CTRL_800GE (CSR_COM_BASE + 0xa4) +#define CSR_COM_TX_PHY_MODE (CSR_COM_BASE + 0xc0) +#define CSR_COM_RX_PHY_MODE (CSR_COM_BASE + 0xe0) +#define CSR_COM_PMA_EXT_MODE_800G (CSR_COM_BASE + 0x100) +#define CSR_COM_BLK_RSTN_LOGIC_C1 (CSR_COM_BASE + 0x104) +#define CSR_COM_BLK_RSTN_CFG_C1 (CSR_COM_BASE + 0x108) +#define CSR_COM_CLK_GATE_CTRL_C1 (CSR_COM_BASE + 0x10c) +#define CSR_COM_CLK_GATE_CTRL_EXT_PMA (CSR_COM_BASE + 0x110) +#define CSR_COM_BLK_RSTN_LOGIC_EXT_PMA (CSR_COM_BASE + 0x120) +#define CSR_COM_BLK_RSTN_CFG_EXT_PMA (CSR_COM_BASE + 0x124) +#define CSR_COM_RSFEC_800GE_EN (CSR_COM_BASE + 0x128) +#define CSR_COM_SPARE (CSR_COM_BASE + 0x200) +#define CSR_COM_SPARE_CNT (CSR_COM_BASE + 0x204) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_mib_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_mib_offset.h new file mode 100644 index 000000000..8f54f631e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_mib_offset.h @@ -0,0 +1,26 @@ +#ifndef MAC_REG_MIB_H +#define MAC_REG_MIB_H + +/* Base address of Module's Register */ +#define CSR_MIB_BASE (0x2c000) + +#define CSR_MIB_PORT_MIB_CNT_DIR (CSR_MIB_BASE + 0x0) +#define CSR_MIB_PORT_MIB_TXPRI0PAUSEPKTS (CSR_MIB_BASE + 0xF0) +#define CSR_MIB_PORT_MIB_TXPRI3XOFFTIME (CSR_MIB_BASE + 0x128) +#define CSR_MIB_PORT_MIB_RXPRI0PAUSEPKTS (CSR_MIB_BASE + 0x250) +#define CSR_MIB_PORT_MIB_RXPRI3XOFFTIME (CSR_MIB_BASE + 0x288) +#define CSR_MIB_INT_STATUS (CSR_MIB_BASE + 0x2000) +#define CSR_MIB_INT_ENABLE (CSR_MIB_BASE + 0x2004) +#define CSR_MIB_INT_SET (CSR_MIB_BASE + 0x2008) +#define CSR_MIB_IERR_U_INFO (CSR_MIB_BASE + 0x200c) +#define CSR_MIB_IERR_C_INFO (CSR_MIB_BASE + 0x2010) +#define CSR_MIB_IERR_U_CNT (CSR_MIB_BASE + 0x2014) +#define CSR_MIB_IERR_C_CNT (CSR_MIB_BASE + 0x2018) +#define CSR_MIB_DBG_IERR_INSERT (CSR_MIB_BASE + 0x201c) +#define CSR_MIB_MEM_INIT_START (CSR_MIB_BASE + 0x2020) +#define CSR_MIB_MEM_INIT_STATUS (CSR_MIB_BASE + 0x2024) +#define CSR_MIB_PORT_MIB_CONTROL (CSR_MIB_BASE + 0x2040) +#define CSR_MIB_SPARE (CSR_MIB_BASE + 0x2080) +#define CSR_MIB_SPARE_CNT (CSR_MIB_BASE + 0x2084) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_brfec_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_brfec_offset.h new file mode 100644 index 000000000..c799d9024 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_brfec_offset.h @@ -0,0 +1,68 @@ +#ifndef MAC_REG_RX_BRFEC_H +#define MAC_REG_RX_BRFEC_H + +/* Base address of Module's Register */ +#define CSR_RX_BRFEC_BASE (0x10000) + +#define CSR_RX_BRFEC_INT_STATUS (CSR_RX_BRFEC_BASE + 0x0) +#define CSR_RX_BRFEC_INT_ENABLE (CSR_RX_BRFEC_BASE + 0x4) +#define CSR_RX_BRFEC_INT_SET (CSR_RX_BRFEC_BASE + 0x8) +#define CSR_RX_BRFEC_OVF_INT_STATUS (CSR_RX_BRFEC_BASE + 0xc) +#define CSR_RX_BRFEC_OVF_INT_ENABLE (CSR_RX_BRFEC_BASE + 0x10) +#define CSR_RX_BRFEC_OVF_INT_SET (CSR_RX_BRFEC_BASE + 0x14) +#define CSR_RX_BRFEC_PHY_CERR_INT_STATUS (CSR_RX_BRFEC_BASE + 0x18) +#define CSR_RX_BRFEC_PHY_CERR_INT_ENABLE (CSR_RX_BRFEC_BASE + 0x1c) +#define CSR_RX_BRFEC_PHY_CERR_INT_SET (CSR_RX_BRFEC_BASE + 0x20) +#define CSR_RX_BRFEC_PHY_UERR_INT_STATUS (CSR_RX_BRFEC_BASE + 0x24) +#define CSR_RX_BRFEC_PHY_UERR_INT_ENABLE (CSR_RX_BRFEC_BASE + 0x28) +#define CSR_RX_BRFEC_PHY_UERR_INT_SET (CSR_RX_BRFEC_BASE + 0x2c) +#define CSR_RX_BRFEC_PHY_RSTN (CSR_RX_BRFEC_BASE + 0x40) +#define CSR_RX_BRFEC_DBG_IERR_INSERT (CSR_RX_BRFEC_BASE + 0x60) +#define CSR_RX_BRFEC_IERR_U_INFO (CSR_RX_BRFEC_BASE + 0x64) +#define CSR_RX_BRFEC_IERR_C_INFO (CSR_RX_BRFEC_BASE + 0x68) +#define CSR_RX_BRFEC_IERR_U_CNT (CSR_RX_BRFEC_BASE + 0x6c) +#define CSR_RX_BRFEC_IERR_C_CNT (CSR_RX_BRFEC_BASE + 0x70) +#define CSR_RX_BRFEC_SPARE (CSR_RX_BRFEC_BASE + 0x80) +#define CSR_RX_BRFEC_SPARE_CNT (CSR_RX_BRFEC_BASE + 0x84) +#define CSR_RX_BRFEC_PHY0_CONTROL (CSR_RX_BRFEC_BASE + 0x100) +#define CSR_RX_BRFEC_PHY0_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x140) +#define CSR_RX_BRFEC_PHY0_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x150) +#define CSR_RX_BRFEC_PHY0_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x160) +#define CSR_RX_BRFEC_PHY0_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x170) +#define CSR_RX_BRFEC_PHY1_CONTROL (CSR_RX_BRFEC_BASE + 0x180) +#define CSR_RX_BRFEC_PHY1_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x190) +#define CSR_RX_BRFEC_PHY1_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x194) +#define CSR_RX_BRFEC_PHY1_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x198) +#define CSR_RX_BRFEC_PHY1_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x19c) +#define CSR_RX_BRFEC_PHY2_CONTROL (CSR_RX_BRFEC_BASE + 0x200) +#define CSR_RX_BRFEC_PHY2_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x240) +#define CSR_RX_BRFEC_PHY2_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x250) +#define CSR_RX_BRFEC_PHY2_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x260) +#define CSR_RX_BRFEC_PHY2_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x270) +#define CSR_RX_BRFEC_PHY3_CONTROL (CSR_RX_BRFEC_BASE + 0x280) +#define CSR_RX_BRFEC_PHY3_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x290) +#define CSR_RX_BRFEC_PHY3_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x294) +#define CSR_RX_BRFEC_PHY3_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x298) +#define CSR_RX_BRFEC_PHY3_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x29c) +#define CSR_RX_BRFEC_PHY4_CONTROL (CSR_RX_BRFEC_BASE + 0x300) +#define CSR_RX_BRFEC_PHY4_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x340) +#define CSR_RX_BRFEC_PHY4_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x350) +#define CSR_RX_BRFEC_PHY4_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x360) +#define CSR_RX_BRFEC_PHY4_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x370) +#define CSR_RX_BRFEC_PHY5_CONTROL (CSR_RX_BRFEC_BASE + 0x380) +#define CSR_RX_BRFEC_PHY5_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x390) +#define CSR_RX_BRFEC_PHY5_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x394) +#define CSR_RX_BRFEC_PHY5_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x398) +#define CSR_RX_BRFEC_PHY5_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x39c) +#define CSR_RX_BRFEC_PHY6_CONTROL (CSR_RX_BRFEC_BASE + 0x400) +#define CSR_RX_BRFEC_PHY6_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x440) +#define CSR_RX_BRFEC_PHY6_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x450) +#define CSR_RX_BRFEC_PHY6_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x460) +#define CSR_RX_BRFEC_PHY6_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x470) +#define CSR_RX_BRFEC_PHY7_CONTROL (CSR_RX_BRFEC_BASE + 0x480) +#define CSR_RX_BRFEC_PHY7_DIAG_FEC_VL_STATE_ (CSR_RX_BRFEC_BASE + 0x490) +#define CSR_RX_BRFEC_PHY7_DIAG_FEC_VL_HIS_STATE_ (CSR_RX_BRFEC_BASE + 0x494) +#define CSR_RX_BRFEC_PHY7_DIAG_CORR_BLK_ (CSR_RX_BRFEC_BASE + 0x498) +#define CSR_RX_BRFEC_PHY7_DIAG_UCORR_BLK_ (CSR_RX_BRFEC_BASE + 0x49c) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_mac_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_mac_offset.h new file mode 100644 index 000000000..a7a4eac5e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_mac_offset.h @@ -0,0 +1,95 @@ +#ifndef MAC_REG_RX_MAC_H +#define MAC_REG_RX_MAC_H + +/* Base address of Module's Register */ +#define CSR_RX_MAC_BASE (0x0) + +#define CSR_RX_MAC_INT_STATUS (CSR_RX_MAC_BASE + 0x0) +#define CSR_RX_MAC_INT_ENABLE (CSR_RX_MAC_BASE + 0x4) +#define CSR_RX_MAC_LF_INT_STATUS (CSR_RX_MAC_BASE + 0x8) +#define CSR_RX_MAC_LF_INT_ENABLE (CSR_RX_MAC_BASE + 0xc) +#define CSR_RX_MAC_LF_INT_SET (CSR_RX_MAC_BASE + 0x10) +#define CSR_RX_MAC_RF_INT_STATUS (CSR_RX_MAC_BASE + 0x14) +#define CSR_RX_MAC_RF_INT_ENABLE (CSR_RX_MAC_BASE + 0x18) +#define CSR_RX_MAC_RF_INT_SET (CSR_RX_MAC_BASE + 0x1c) +#define CSR_RX_MAC_LINT_INT_STATUS (CSR_RX_MAC_BASE + 0x20) +#define CSR_RX_MAC_LINT_INT_ENABLE (CSR_RX_MAC_BASE + 0x24) +#define CSR_RX_MAC_LINT_INT_SET (CSR_RX_MAC_BASE + 0x28) +#define CSR_RX_MAC_LINK_UP_INT_STATUS (CSR_RX_MAC_BASE + 0x2c) +#define CSR_RX_MAC_LINK_UP_INT_ENABLE (CSR_RX_MAC_BASE + 0x30) +#define CSR_RX_MAC_LINK_UP_INT_SET (CSR_RX_MAC_BASE + 0x34) +#define CSR_RX_MAC_LINK_DOWN_INT_STATUS (CSR_RX_MAC_BASE + 0x38) +#define CSR_RX_MAC_LINK_DOWN_INT_ENABLE (CSR_RX_MAC_BASE + 0x3c) +#define CSR_RX_MAC_LINK_DOWN_INT_SET (CSR_RX_MAC_BASE + 0x40) +#define CSR_RX_MAC_REF_1588_OVF_INT_STATUS (CSR_RX_MAC_BASE + 0x44) +#define CSR_RX_MAC_REF_1588_OVF_INT_ENABLE (CSR_RX_MAC_BASE + 0x48) +#define CSR_RX_MAC_REF_1588_OVF_INT_SET (CSR_RX_MAC_BASE + 0x4c) +#define CSR_RX_MAC_PREAMB_ERR_INT_STATUS (CSR_RX_MAC_BASE + 0x50) +#define CSR_RX_MAC_PREAMB_ERR_INT_ENABLE (CSR_RX_MAC_BASE + 0x54) +#define CSR_RX_MAC_PREAMB_ERR_INT_SET (CSR_RX_MAC_BASE + 0x58) +#define CSR_RX_MAC_EOP_TIMEOUT_CYC (CSR_RX_MAC_BASE + 0x400) +#define CSR_RX_MAC_PHY_LINK_STATUS (CSR_RX_MAC_BASE + 0x420) +#define CSR_RX_MAC_PHY_LINK_CONTROL (CSR_RX_MAC_BASE + 0x440) +#define CSR_RX_MAC_PHY_LFRF_STATUS (CSR_RX_MAC_BASE + 0x460) +#define CSR_RX_MAC_PHY_1588_CFG (CSR_RX_MAC_BASE + 0x480) +#define CSR_RX_MAC_PORT_RSTN_LOGIC (CSR_RX_MAC_BASE + 0x4a0) +#define CSR_RX_MAC_PORT_ENABLE (CSR_RX_MAC_BASE + 0x4c0) +#define CSR_RX_MAC_PORT_CONTROL (CSR_RX_MAC_BASE + 0x4e0) +#define CSR_RX_MAC_PORT_CONTROL1 (CSR_RX_MAC_BASE + 0x500) +#define CSR_RX_MAC_PORT_PAUSE_CTRL (CSR_RX_MAC_BASE + 0x520) +#define CSR_RX_MAC_PORT_PAUSE_LOCAL_MAC (CSR_RX_MAC_BASE + 0x540) +#define CSR_RX_MAC_PORT_1588_CTRL (CSR_RX_MAC_BASE + 0x580) +#define CSR_RX_MAC_PORT_1588_PORT_DELAY (CSR_RX_MAC_BASE + 0x5a0) +#define CSR_RX_MAC_PORT_DBG_XOFF_SET (CSR_RX_MAC_BASE + 0x5c0) +#define CSR_RX_MAC_PORT_DIAG_CURR_STATUS (CSR_RX_MAC_BASE + 0x5e0) +#define CSR_RX_MAC_PORT_DIAG_HIS_STATUS (CSR_RX_MAC_BASE + 0x600) +#define CSR_RX_MAC_PORT_DIAG_EFD_ERR_CNT (CSR_RX_MAC_BASE + 0x620) +#define CSR_RX_MAC_PORT_DIAG_PRE_ERR_CNT (CSR_RX_MAC_BASE + 0x640) +#define CSR_RX_MAC_PORT_DIAG_FILTER_CNT (CSR_RX_MAC_BASE + 0x680) +#define CSR_RX_MAC_PHY_DIAG_HIS_STATUS (CSR_RX_MAC_BASE + 0x6c0) +#define CSR_RX_MAC_PHY_DIAG_1588_REF_GAP_JIT_MAX (CSR_RX_MAC_BASE + 0x6e0) +#define CSR_RX_MAC_PHY_DIAG_1588_REF_GAP_JIT_CLR (CSR_RX_MAC_BASE + 0x700) +#define CSR_RX_MAC_PHY_DIAG_1588_REF_GAP_JIT_TH (CSR_RX_MAC_BASE + 0x720) +#define CSR_RX_MAC_DBG_1588_CFG (CSR_RX_MAC_BASE + 0x728) +#define CSR_RX_MAC_DBG_1588_CHK_MAX (CSR_RX_MAC_BASE + 0x730) +#define CSR_RX_MAC_DBG_1588_CHK_MIN (CSR_RX_MAC_BASE + 0x738) +#define CSR_RX_MAC_DIAG_PAYLOAD_RATE_CFG (CSR_RX_MAC_BASE + 0x740) +#define CSR_RX_MAC_DIAG_PAYLOAD_RATE_WIN (CSR_RX_MAC_BASE + 0x748) +#define CSR_RX_MAC_DIAG_PAYLOAD_RATE_PKT (CSR_RX_MAC_BASE + 0x750) +#define CSR_RX_MAC_DIAG_PAYLOAD_RATE_BYTE (CSR_RX_MAC_BASE + 0x760) +#define CSR_RX_MAC_DIAG_CURR_STATUS (CSR_RX_MAC_BASE + 0x770) +#define CSR_RX_MAC_DIAG_HIS_STATUS (CSR_RX_MAC_BASE + 0x774) +#define CSR_RX_MAC_F_INTF_TDM_SLOT_800G (CSR_RX_MAC_BASE + 0x780) +#define CSR_RX_MAC_PORT_DIAG_F_INTF_DROP_CNT_800G (CSR_RX_MAC_BASE + 0x790) +#define CSR_RX_MAC_SPARE (CSR_RX_MAC_BASE + 0x7a0) +#define CSR_RX_MAC_SPARE_CNT (CSR_RX_MAC_BASE + 0x7a4) +#define CSR_RX_MAC_HEE_MSG_SFD (CSR_RX_MAC_BASE + 0x800) +#define CSR_RX_MAC_HEE_SDSU_CFG (CSR_RX_MAC_BASE + 0x804) +#define CSR_RX_MAC_PHY0_HEE_CFG (CSR_RX_MAC_BASE + 0x808) +#define CSR_RX_MAC_PHY2_HEE_CFG (CSR_RX_MAC_BASE + 0x80c) +#define CSR_RX_MAC_PHY0_HEE_OP_START (CSR_RX_MAC_BASE + 0x810) +#define CSR_RX_MAC_PHY2_HEE_OP_START (CSR_RX_MAC_BASE + 0x814) +#define CSR_RX_MAC_PHY0_HEE_OP_CMD (CSR_RX_MAC_BASE + 0x818) +#define CSR_RX_MAC_PHY2_HEE_OP_CMD (CSR_RX_MAC_BASE + 0x81c) +#define CSR_RX_MAC_PHY0_HEE_OP_STATUS (CSR_RX_MAC_BASE + 0x820) +#define CSR_RX_MAC_PHY2_HEE_OP_STATUS (CSR_RX_MAC_BASE + 0x824) +#define CSR_RX_MAC_PHY0_HEE_RCV_STATUS (CSR_RX_MAC_BASE + 0x828) +#define CSR_RX_MAC_PHY2_HEE_RCV_STATUS (CSR_RX_MAC_BASE + 0x82c) +#define CSR_RX_MAC_PHY0_DBG_HEE_RSTN (CSR_RX_MAC_BASE + 0x830) +#define CSR_RX_MAC_PHY2_DBG_HEE_RSTN (CSR_RX_MAC_BASE + 0x834) +#define CSR_RX_MAC_PHY0_DIAG_HEE_HIS_STATUS (CSR_RX_MAC_BASE + 0x838) +#define CSR_RX_MAC_PHY2_DIAG_HEE_HIS_STATUS (CSR_RX_MAC_BASE + 0x83c) +#define CSR_RX_MAC_PHY0_DIAG_HEE_CURR_STATUS (CSR_RX_MAC_BASE + 0x840) +#define CSR_RX_MAC_PHY2_DIAG_HEE_CURR_STATUS (CSR_RX_MAC_BASE + 0x844) +#define CSR_RX_MAC_PHY0_DIAG_HEE_V_PKT_CNT (CSR_RX_MAC_BASE + 0x848) +#define CSR_RX_MAC_PHY2_DIAG_HEE_V_PKT_CNT (CSR_RX_MAC_BASE + 0x84c) +#define CSR_RX_MAC_PHY0_DIAG_HEE_R_PKT_CNT (CSR_RX_MAC_BASE + 0x850) +#define CSR_RX_MAC_PHY2_DIAG_HEE_R_PKT_CNT (CSR_RX_MAC_BASE + 0x854) +#define CSR_RX_MAC_PHY0_DIAG_HEE_SD_PKT_CNT (CSR_RX_MAC_BASE + 0x858) +#define CSR_RX_MAC_PHY2_DIAG_HEE_SD_PKT_CNT (CSR_RX_MAC_BASE + 0x85c) +#define CSR_RX_MAC_PHY0_DIAG_HEE_SU_PKT_CNT (CSR_RX_MAC_BASE + 0x860) +#define CSR_RX_MAC_PHY2_DIAG_HEE_SU_PKT_CNT (CSR_RX_MAC_BASE + 0x864) +#define CSR_RX_MAC_PHY0_DIAG_HEE_ERR_PKT_CNT (CSR_RX_MAC_BASE + 0x868) +#define CSR_RX_MAC_PHY2_DIAG_HEE_ERR_PKT_CNT (CSR_RX_MAC_BASE + 0x86c) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_pcs_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_pcs_offset.h new file mode 100644 index 000000000..68e4579de --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_pcs_offset.h @@ -0,0 +1,343 @@ +#ifndef MAC_REG_RX_PCS_H +#define MAC_REG_RX_PCS_H + +/* Base address of Module's Register */ +#define CSR_RX_PCS_BASE (0x4000) + +#define CSR_RX_PCS_INT_STATUS (CSR_RX_PCS_BASE + 0x0) +#define CSR_RX_PCS_INT_ENABLE (CSR_RX_PCS_BASE + 0x4) +#define CSR_RX_PCS_INT_SET (CSR_RX_PCS_BASE + 0x8) +#define CSR_RX_PCS_OVF_INT_STATUS (CSR_RX_PCS_BASE + 0xc) +#define CSR_RX_PCS_OVF_INT_ENABLE (CSR_RX_PCS_BASE + 0x10) +#define CSR_RX_PCS_OVF_INT_SET (CSR_RX_PCS_BASE + 0x14) +#define CSR_RX_PCS_SD_INT_STATUS (CSR_RX_PCS_BASE + 0x18) +#define CSR_RX_PCS_SD_INT_ENABLE (CSR_RX_PCS_BASE + 0x1c) +#define CSR_RX_PCS_SD_INT_SET (CSR_RX_PCS_BASE + 0x20) +#define CSR_RX_PCS_SF_INT_STATUS (CSR_RX_PCS_BASE + 0x24) +#define CSR_RX_PCS_SF_INT_ENABLE (CSR_RX_PCS_BASE + 0x28) +#define CSR_RX_PCS_SF_INT_SET (CSR_RX_PCS_BASE + 0x2c) +#define CSR_RX_PCS_IERR_U_INFO (CSR_RX_PCS_BASE + 0x80) +#define CSR_RX_PCS_IERR_C_INFO (CSR_RX_PCS_BASE + 0x84) +#define CSR_RX_PCS_IERR_U_CNT (CSR_RX_PCS_BASE + 0x88) +#define CSR_RX_PCS_IERR_C_CNT (CSR_RX_PCS_BASE + 0x8c) +#define CSR_RX_PCS_PHY_RSTN (CSR_RX_PCS_BASE + 0xa0) +#define CSR_RX_PCS_DBG_IERR_INSERT (CSR_RX_PCS_BASE + 0xc0) +#define CSR_RX_PCS_DBG_COM_CTRL (CSR_RX_PCS_BASE + 0xc4) +#define CSR_RX_PCS_RSFEC_TDM_DELAY (CSR_RX_PCS_BASE + 0xc8) +#define CSR_RX_PCS_AN_LINK_CTRL (CSR_RX_PCS_BASE + 0xcc) +#define CSR_RX_PCS_LINK_UP_TYPE_CTRL (CSR_RX_PCS_BASE + 0xd0) +#define CSR_RX_PCS_DBG_DEC_CAP (CSR_RX_PCS_BASE + 0xd4) +#define CSR_RX_PCS_DBG_DEC_CAP_CMD (CSR_RX_PCS_BASE + 0xd8) +#define CSR_RX_PCS_DBG_DEC_CAP_STATUS (CSR_RX_PCS_BASE + 0xdc) +#define CSR_RX_PCS_DBG_DEC_CAP_DATA (CSR_RX_PCS_BASE + 0xe0) +#define CSR_RX_PCS_LINK_STATUS (CSR_RX_PCS_BASE + 0xf0) +#define CSR_RX_PCS_LOOP_FIFO_CURR_STATUS (CSR_RX_PCS_BASE + 0xf4) +#define CSR_RX_PCS_LOOP_FIFO_HIS_STATUS (CSR_RX_PCS_BASE + 0xf8) +#define CSR_RX_PCS_SPARE (CSR_RX_PCS_BASE + 0x100) +#define CSR_RX_PCS_SPARE_CNT (CSR_RX_PCS_BASE + 0x104) +#define CSR_RX_PCS_PHY0_CTRL_CFG (CSR_RX_PCS_BASE + 0x400) +#define CSR_RX_PCS_PHY0_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x404) +#define CSR_RX_PCS_PHY0_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x408) +#define CSR_RX_PCS_PHY0_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x40c) +#define CSR_RX_PCS_PHY0_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x410) +#define CSR_RX_PCS_PHY0_TEST_CONTROL (CSR_RX_PCS_BASE + 0x414) +#define CSR_RX_PCS_PHY0_DBG_CONTROL (CSR_RX_PCS_BASE + 0x418) +#define CSR_RX_PCS_PHY0_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x41c) +#define CSR_RX_PCS_PHY0_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x420) +#define CSR_RX_PCS_PHY0_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x424) +#define CSR_RX_PCS_PHY0_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x428) +#define CSR_RX_PCS_PHY0_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x42c) +#define CSR_RX_PCS_PHY0_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x430) +#define CSR_RX_PCS_PHY0_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x434) +#define CSR_RX_PCS_PHY0_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x438) +#define CSR_RX_PCS_PHY0_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x43c) +#define CSR_RX_PCS_PHY0_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x440) +#define CSR_RX_PCS_PHY0_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x444) +#define CSR_RX_PCS_PHY0_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x448) +#define CSR_RX_PCS_PHY0_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x44c) +#define CSR_RX_PCS_PHY0_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x450) +#define CSR_RX_PCS_PHY0_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x454) +#define CSR_RX_PCS_PHY0_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x458) +#define CSR_RX_PCS_PHY0_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x45c) +#define CSR_RX_PCS_PHY0_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x460) +#define CSR_RX_PCS_PHY0_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x464) +#define CSR_RX_PCS_PHY0_BER_CNT (CSR_RX_PCS_BASE + 0x468) +#define CSR_RX_PCS_PHY0_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x46c) +#define CSR_RX_PCS_PHY0_E_BLK_CNT (CSR_RX_PCS_BASE + 0x470) +#define CSR_RX_PCS_PHY0_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x474) +#define CSR_RX_PCS_PHY0_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x478) +#define CSR_RX_PCS_PHY0__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x480) +#define CSR_RX_PCS_PHY0_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x500) +#define CSR_RX_PCS_PHY0_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x504) +#define CSR_RX_PCS_PHY0_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x508) +#define CSR_RX_PCS_PHY0_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x50c) +#define CSR_RX_PCS_PHY0_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x510) +#define CSR_RX_PCS_PHY0_BASER_800G_CONTROL (CSR_RX_PCS_BASE + 0x600) +#define CSR_RX_PCS_PHY0_TEST_800G_PRBS_MODE (CSR_RX_PCS_BASE + 0x604) +#define CSR_RX_PCS_PHY0_PRBS_800G_ERR_CNT (CSR_RX_PCS_BASE + 0x608) +#define CSR_RX_PCS_PHY0_PRBS_800G_BIT_CNT (CSR_RX_PCS_BASE + 0x60c) +#define CSR_RX_PCS_PHY0_PRBS_800G_CW_CNT (CSR_RX_PCS_BASE + 0x610) +#define CSR_RX_PCS_PHY0_INV_BLOCK_800G_CNT (CSR_RX_PCS_BASE + 0x614) +#define CSR_RX_PCS_PHY0_DBG_CUR_800G_STATUS (CSR_RX_PCS_BASE + 0x618) +#define CSR_RX_PCS_PHY0_DBG_HIS_800G_STATUS (CSR_RX_PCS_BASE + 0x61c) +#define CSR_RX_PCS_PHY1_CTRL_CFG (CSR_RX_PCS_BASE + 0x800) +#define CSR_RX_PCS_PHY1_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x804) +#define CSR_RX_PCS_PHY1_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x808) +#define CSR_RX_PCS_PHY1_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x80c) +#define CSR_RX_PCS_PHY1_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x810) +#define CSR_RX_PCS_PHY1_TEST_CONTROL (CSR_RX_PCS_BASE + 0x814) +#define CSR_RX_PCS_PHY1_DBG_CONTROL (CSR_RX_PCS_BASE + 0x818) +#define CSR_RX_PCS_PHY1_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x81c) +#define CSR_RX_PCS_PHY1_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x820) +#define CSR_RX_PCS_PHY1_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x824) +#define CSR_RX_PCS_PHY1_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x828) +#define CSR_RX_PCS_PHY1_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x82c) +#define CSR_RX_PCS_PHY1_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x830) +#define CSR_RX_PCS_PHY1_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x834) +#define CSR_RX_PCS_PHY1_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x838) +#define CSR_RX_PCS_PHY1_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x83c) +#define CSR_RX_PCS_PHY1_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x840) +#define CSR_RX_PCS_PHY1_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x844) +#define CSR_RX_PCS_PHY1_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x848) +#define CSR_RX_PCS_PHY1_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x84c) +#define CSR_RX_PCS_PHY1_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x850) +#define CSR_RX_PCS_PHY1_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x854) +#define CSR_RX_PCS_PHY1_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x858) +#define CSR_RX_PCS_PHY1_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x85c) +#define CSR_RX_PCS_PHY1_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x860) +#define CSR_RX_PCS_PHY1_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x864) +#define CSR_RX_PCS_PHY1_BER_CNT (CSR_RX_PCS_BASE + 0x868) +#define CSR_RX_PCS_PHY1_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x86c) +#define CSR_RX_PCS_PHY1_E_BLK_CNT (CSR_RX_PCS_BASE + 0x870) +#define CSR_RX_PCS_PHY1_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x874) +#define CSR_RX_PCS_PHY1_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x878) +#define CSR_RX_PCS_PHY1__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x880) +#define CSR_RX_PCS_PHY1_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x900) +#define CSR_RX_PCS_PHY1_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x904) +#define CSR_RX_PCS_PHY1_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x908) +#define CSR_RX_PCS_PHY1_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x90c) +#define CSR_RX_PCS_PHY1_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x910) +#define CSR_RX_PCS_PHY2_CTRL_CFG (CSR_RX_PCS_BASE + 0xa00) +#define CSR_RX_PCS_PHY2_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0xa04) +#define CSR_RX_PCS_PHY2_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0xa08) +#define CSR_RX_PCS_PHY2_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0xa0c) +#define CSR_RX_PCS_PHY2_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0xa10) +#define CSR_RX_PCS_PHY2_TEST_CONTROL (CSR_RX_PCS_BASE + 0xa14) +#define CSR_RX_PCS_PHY2_DBG_CONTROL (CSR_RX_PCS_BASE + 0xa18) +#define CSR_RX_PCS_PHY2_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0xa1c) +#define CSR_RX_PCS_PHY2_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xa20) +#define CSR_RX_PCS_PHY2_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xa24) +#define CSR_RX_PCS_PHY2_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xa28) +#define CSR_RX_PCS_PHY2_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xa2c) +#define CSR_RX_PCS_PHY2_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xa30) +#define CSR_RX_PCS_PHY2_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xa34) +#define CSR_RX_PCS_PHY2_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xa38) +#define CSR_RX_PCS_PHY2_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xa3c) +#define CSR_RX_PCS_PHY2_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa40) +#define CSR_RX_PCS_PHY2_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa44) +#define CSR_RX_PCS_PHY2_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa48) +#define CSR_RX_PCS_PHY2_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa4c) +#define CSR_RX_PCS_PHY2_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa50) +#define CSR_RX_PCS_PHY2_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa54) +#define CSR_RX_PCS_PHY2_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa58) +#define CSR_RX_PCS_PHY2_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa5c) +#define CSR_RX_PCS_PHY2_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0xa60) +#define CSR_RX_PCS_PHY2_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0xa64) +#define CSR_RX_PCS_PHY2_BER_CNT (CSR_RX_PCS_BASE + 0xa68) +#define CSR_RX_PCS_PHY2_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0xa6c) +#define CSR_RX_PCS_PHY2_E_BLK_CNT (CSR_RX_PCS_BASE + 0xa70) +#define CSR_RX_PCS_PHY2_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0xa74) +#define CSR_RX_PCS_PHY2_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0xa78) +#define CSR_RX_PCS_PHY2__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0xa80) +#define CSR_RX_PCS_PHY2_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0xb00) +#define CSR_RX_PCS_PHY2_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0xb04) +#define CSR_RX_PCS_PHY2_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0xb08) +#define CSR_RX_PCS_PHY2_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0xb0c) +#define CSR_RX_PCS_PHY2_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0xb10) +#define CSR_RX_PCS_PHY3_CTRL_CFG (CSR_RX_PCS_BASE + 0xc00) +#define CSR_RX_PCS_PHY3_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0xc04) +#define CSR_RX_PCS_PHY3_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0xc08) +#define CSR_RX_PCS_PHY3_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0xc0c) +#define CSR_RX_PCS_PHY3_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0xc10) +#define CSR_RX_PCS_PHY3_TEST_CONTROL (CSR_RX_PCS_BASE + 0xc14) +#define CSR_RX_PCS_PHY3_DBG_CONTROL (CSR_RX_PCS_BASE + 0xc18) +#define CSR_RX_PCS_PHY3_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0xc1c) +#define CSR_RX_PCS_PHY3_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xc20) +#define CSR_RX_PCS_PHY3_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xc24) +#define CSR_RX_PCS_PHY3_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xc28) +#define CSR_RX_PCS_PHY3_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xc2c) +#define CSR_RX_PCS_PHY3_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xc30) +#define CSR_RX_PCS_PHY3_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xc34) +#define CSR_RX_PCS_PHY3_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xc38) +#define CSR_RX_PCS_PHY3_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xc3c) +#define CSR_RX_PCS_PHY3_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc40) +#define CSR_RX_PCS_PHY3_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc44) +#define CSR_RX_PCS_PHY3_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc48) +#define CSR_RX_PCS_PHY3_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc4c) +#define CSR_RX_PCS_PHY3_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc50) +#define CSR_RX_PCS_PHY3_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc54) +#define CSR_RX_PCS_PHY3_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc58) +#define CSR_RX_PCS_PHY3_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc5c) +#define CSR_RX_PCS_PHY3_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0xc60) +#define CSR_RX_PCS_PHY3_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0xc64) +#define CSR_RX_PCS_PHY3_BER_CNT (CSR_RX_PCS_BASE + 0xc68) +#define CSR_RX_PCS_PHY3_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0xc6c) +#define CSR_RX_PCS_PHY3_E_BLK_CNT (CSR_RX_PCS_BASE + 0xc70) +#define CSR_RX_PCS_PHY3_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0xc74) +#define CSR_RX_PCS_PHY3_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0xc78) +#define CSR_RX_PCS_PHY3__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0xc80) +#define CSR_RX_PCS_PHY3_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0xd00) +#define CSR_RX_PCS_PHY3_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0xd04) +#define CSR_RX_PCS_PHY3_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0xd08) +#define CSR_RX_PCS_PHY3_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0xd0c) +#define CSR_RX_PCS_PHY3_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0xd10) +#define CSR_RX_PCS_PHY4_CTRL_CFG (CSR_RX_PCS_BASE + 0xe00) +#define CSR_RX_PCS_PHY4_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0xe04) +#define CSR_RX_PCS_PHY4_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0xe08) +#define CSR_RX_PCS_PHY4_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0xe0c) +#define CSR_RX_PCS_PHY4_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0xe10) +#define CSR_RX_PCS_PHY4_TEST_CONTROL (CSR_RX_PCS_BASE + 0xe14) +#define CSR_RX_PCS_PHY4_DBG_CONTROL (CSR_RX_PCS_BASE + 0xe18) +#define CSR_RX_PCS_PHY4_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0xe1c) +#define CSR_RX_PCS_PHY4_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xe20) +#define CSR_RX_PCS_PHY4_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xe24) +#define CSR_RX_PCS_PHY4_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xe28) +#define CSR_RX_PCS_PHY4_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xe2c) +#define CSR_RX_PCS_PHY4_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xe30) +#define CSR_RX_PCS_PHY4_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xe34) +#define CSR_RX_PCS_PHY4_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xe38) +#define CSR_RX_PCS_PHY4_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xe3c) +#define CSR_RX_PCS_PHY4_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe40) +#define CSR_RX_PCS_PHY4_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe44) +#define CSR_RX_PCS_PHY4_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe48) +#define CSR_RX_PCS_PHY4_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe4c) +#define CSR_RX_PCS_PHY4_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe50) +#define CSR_RX_PCS_PHY4_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe54) +#define CSR_RX_PCS_PHY4_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe58) +#define CSR_RX_PCS_PHY4_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe5c) +#define CSR_RX_PCS_PHY4_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0xe60) +#define CSR_RX_PCS_PHY4_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0xe64) +#define CSR_RX_PCS_PHY4_BER_CNT (CSR_RX_PCS_BASE + 0xe68) +#define CSR_RX_PCS_PHY4_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0xe6c) +#define CSR_RX_PCS_PHY4_E_BLK_CNT (CSR_RX_PCS_BASE + 0xe70) +#define CSR_RX_PCS_PHY4_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0xe74) +#define CSR_RX_PCS_PHY4_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0xe78) +#define CSR_RX_PCS_PHY4__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0xe80) +#define CSR_RX_PCS_PHY4_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0xf00) +#define CSR_RX_PCS_PHY4_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0xf04) +#define CSR_RX_PCS_PHY4_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0xf08) +#define CSR_RX_PCS_PHY4_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0xf0c) +#define CSR_RX_PCS_PHY4_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0xf10) +#define CSR_RX_PCS_PHY5_CTRL_CFG (CSR_RX_PCS_BASE + 0x1000) +#define CSR_RX_PCS_PHY5_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x1004) +#define CSR_RX_PCS_PHY5_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x1008) +#define CSR_RX_PCS_PHY5_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x100c) +#define CSR_RX_PCS_PHY5_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x1010) +#define CSR_RX_PCS_PHY5_TEST_CONTROL (CSR_RX_PCS_BASE + 0x1014) +#define CSR_RX_PCS_PHY5_DBG_CONTROL (CSR_RX_PCS_BASE + 0x1018) +#define CSR_RX_PCS_PHY5_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x101c) +#define CSR_RX_PCS_PHY5_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1020) +#define CSR_RX_PCS_PHY5_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x1024) +#define CSR_RX_PCS_PHY5_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1028) +#define CSR_RX_PCS_PHY5_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x102c) +#define CSR_RX_PCS_PHY5_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1030) +#define CSR_RX_PCS_PHY5_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x1034) +#define CSR_RX_PCS_PHY5_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1038) +#define CSR_RX_PCS_PHY5_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x103c) +#define CSR_RX_PCS_PHY5_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1040) +#define CSR_RX_PCS_PHY5_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1044) +#define CSR_RX_PCS_PHY5_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1048) +#define CSR_RX_PCS_PHY5_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x104c) +#define CSR_RX_PCS_PHY5_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1050) +#define CSR_RX_PCS_PHY5_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1054) +#define CSR_RX_PCS_PHY5_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1058) +#define CSR_RX_PCS_PHY5_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x105c) +#define CSR_RX_PCS_PHY5_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x1060) +#define CSR_RX_PCS_PHY5_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x1064) +#define CSR_RX_PCS_PHY5_BER_CNT (CSR_RX_PCS_BASE + 0x1068) +#define CSR_RX_PCS_PHY5_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x106c) +#define CSR_RX_PCS_PHY5_E_BLK_CNT (CSR_RX_PCS_BASE + 0x1070) +#define CSR_RX_PCS_PHY5_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x1074) +#define CSR_RX_PCS_PHY5_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x1078) +#define CSR_RX_PCS_PHY5__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x1080) +#define CSR_RX_PCS_PHY5_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x1100) +#define CSR_RX_PCS_PHY5_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x1104) +#define CSR_RX_PCS_PHY5_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x1108) +#define CSR_RX_PCS_PHY5_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x110c) +#define CSR_RX_PCS_PHY5_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x1110) +#define CSR_RX_PCS_PHY6_CTRL_CFG (CSR_RX_PCS_BASE + 0x1200) +#define CSR_RX_PCS_PHY6_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x1204) +#define CSR_RX_PCS_PHY6_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x1208) +#define CSR_RX_PCS_PHY6_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x120c) +#define CSR_RX_PCS_PHY6_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x1210) +#define CSR_RX_PCS_PHY6_TEST_CONTROL (CSR_RX_PCS_BASE + 0x1214) +#define CSR_RX_PCS_PHY6_DBG_CONTROL (CSR_RX_PCS_BASE + 0x1218) +#define CSR_RX_PCS_PHY6_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x121c) +#define CSR_RX_PCS_PHY6_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1220) +#define CSR_RX_PCS_PHY6_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x1224) +#define CSR_RX_PCS_PHY6_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1228) +#define CSR_RX_PCS_PHY6_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x122c) +#define CSR_RX_PCS_PHY6_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1230) +#define CSR_RX_PCS_PHY6_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x1234) +#define CSR_RX_PCS_PHY6_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1238) +#define CSR_RX_PCS_PHY6_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x123c) +#define CSR_RX_PCS_PHY6_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1240) +#define CSR_RX_PCS_PHY6_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1244) +#define CSR_RX_PCS_PHY6_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1248) +#define CSR_RX_PCS_PHY6_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x124c) +#define CSR_RX_PCS_PHY6_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1250) +#define CSR_RX_PCS_PHY6_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1254) +#define CSR_RX_PCS_PHY6_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1258) +#define CSR_RX_PCS_PHY6_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x125c) +#define CSR_RX_PCS_PHY6_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x1260) +#define CSR_RX_PCS_PHY6_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x1264) +#define CSR_RX_PCS_PHY6_BER_CNT (CSR_RX_PCS_BASE + 0x1268) +#define CSR_RX_PCS_PHY6_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x126c) +#define CSR_RX_PCS_PHY6_E_BLK_CNT (CSR_RX_PCS_BASE + 0x1270) +#define CSR_RX_PCS_PHY6_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x1274) +#define CSR_RX_PCS_PHY6_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x1278) +#define CSR_RX_PCS_PHY6__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x1280) +#define CSR_RX_PCS_PHY6_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x1300) +#define CSR_RX_PCS_PHY6_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x1304) +#define CSR_RX_PCS_PHY6_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x1308) +#define CSR_RX_PCS_PHY6_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x130c) +#define CSR_RX_PCS_PHY6_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x1310) +#define CSR_RX_PCS_PHY7_CTRL_CFG (CSR_RX_PCS_BASE + 0x1400) +#define CSR_RX_PCS_PHY7_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x1404) +#define CSR_RX_PCS_PHY7_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x1408) +#define CSR_RX_PCS_PHY7_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x140c) +#define CSR_RX_PCS_PHY7_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x1410) +#define CSR_RX_PCS_PHY7_TEST_CONTROL (CSR_RX_PCS_BASE + 0x1414) +#define CSR_RX_PCS_PHY7_DBG_CONTROL (CSR_RX_PCS_BASE + 0x1418) +#define CSR_RX_PCS_PHY7_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x141c) +#define CSR_RX_PCS_PHY7_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1420) +#define CSR_RX_PCS_PHY7_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x1424) +#define CSR_RX_PCS_PHY7_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1428) +#define CSR_RX_PCS_PHY7_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x142c) +#define CSR_RX_PCS_PHY7_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1430) +#define CSR_RX_PCS_PHY7_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x1434) +#define CSR_RX_PCS_PHY7_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1438) +#define CSR_RX_PCS_PHY7_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x143c) +#define CSR_RX_PCS_PHY7_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1440) +#define CSR_RX_PCS_PHY7_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1444) +#define CSR_RX_PCS_PHY7_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1448) +#define CSR_RX_PCS_PHY7_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x144c) +#define CSR_RX_PCS_PHY7_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1450) +#define CSR_RX_PCS_PHY7_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1454) +#define CSR_RX_PCS_PHY7_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1458) +#define CSR_RX_PCS_PHY7_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x145c) +#define CSR_RX_PCS_PHY7_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x1460) +#define CSR_RX_PCS_PHY7_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x1464) +#define CSR_RX_PCS_PHY7_BER_CNT (CSR_RX_PCS_BASE + 0x1468) +#define CSR_RX_PCS_PHY7_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x146c) +#define CSR_RX_PCS_PHY7_E_BLK_CNT (CSR_RX_PCS_BASE + 0x1470) +#define CSR_RX_PCS_PHY7_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x1474) +#define CSR_RX_PCS_PHY7_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x1478) +#define CSR_RX_PCS_PHY7__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x1480) +#define CSR_RX_PCS_PHY7_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x1500) +#define CSR_RX_PCS_PHY7_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x1504) +#define CSR_RX_PCS_PHY7_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x1508) +#define CSR_RX_PCS_PHY7_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x150c) +#define CSR_RX_PCS_PHY7_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x1510) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_rsfec_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_rsfec_offset.h new file mode 100644 index 000000000..1893dd84c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rx_rsfec_offset.h @@ -0,0 +1,503 @@ +#ifndef MAC_REG_RX_RSFEC_H +#define MAC_REG_RX_RSFEC_H + +/* Base address of Module's Register */ +#define CSR_RX_RSFEC_BASE (0x8000) + +#define CSR_RX_RSFEC_INT_STATUS (CSR_RX_RSFEC_BASE + 0x0) +#define CSR_RX_RSFEC_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x4) +#define CSR_RX_RSFEC_INT_SET (CSR_RX_RSFEC_BASE + 0x8) +#define CSR_RX_RSFEC_LINK_UP_INT_STATUS (CSR_RX_RSFEC_BASE + 0xc) +#define CSR_RX_RSFEC_LINK_UP_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x10) +#define CSR_RX_RSFEC_LINK_UP_INT_SET (CSR_RX_RSFEC_BASE + 0x14) +#define CSR_RX_RSFEC_LINK_DOWN_INT_STATUS (CSR_RX_RSFEC_BASE + 0x18) +#define CSR_RX_RSFEC_LINK_DOWN_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x1c) +#define CSR_RX_RSFEC_LINK_DOWN_INT_SET (CSR_RX_RSFEC_BASE + 0x20) +#define CSR_RX_RSFEC_TIME_OUT_INT_STATUS (CSR_RX_RSFEC_BASE + 0x24) +#define CSR_RX_RSFEC_TIME_OUT_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x28) +#define CSR_RX_RSFEC_TIME_OUT_INT_SET (CSR_RX_RSFEC_BASE + 0x2c) +#define CSR_RX_RSFEC_OVF_INT_STATUS (CSR_RX_RSFEC_BASE + 0x30) +#define CSR_RX_RSFEC_OVF_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x34) +#define CSR_RX_RSFEC_OVF_INT_SET (CSR_RX_RSFEC_BASE + 0x38) +#define CSR_RX_RSFEC_LOC_SER_INT_STATUS (CSR_RX_RSFEC_BASE + 0x3c) +#define CSR_RX_RSFEC_LOC_SER_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x40) +#define CSR_RX_RSFEC_LOC_SER_INT_SET (CSR_RX_RSFEC_BASE + 0x44) +#define CSR_RX_RSFEC_RM_SER_INT_STATUS (CSR_RX_RSFEC_BASE + 0x48) +#define CSR_RX_RSFEC_RM_SER_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x4c) +#define CSR_RX_RSFEC_RM_SER_INT_SET (CSR_RX_RSFEC_BASE + 0x50) +#define CSR_RX_RSFEC_HI_BER_INT_STATUS (CSR_RX_RSFEC_BASE + 0x54) +#define CSR_RX_RSFEC_HI_BER_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x58) +#define CSR_RX_RSFEC_HI_BER_INT_SET (CSR_RX_RSFEC_BASE + 0x5c) +#define CSR_RX_RSFEC_SD_INT_STATUS (CSR_RX_RSFEC_BASE + 0x60) +#define CSR_RX_RSFEC_SD_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x64) +#define CSR_RX_RSFEC_SD_INT_SET (CSR_RX_RSFEC_BASE + 0x68) +#define CSR_RX_RSFEC_SF_INT_STATUS (CSR_RX_RSFEC_BASE + 0x6c) +#define CSR_RX_RSFEC_SF_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x70) +#define CSR_RX_RSFEC_SF_INT_SET (CSR_RX_RSFEC_BASE + 0x74) +#define CSR_RX_RSFEC_PHY_CERR_INT_STATUS (CSR_RX_RSFEC_BASE + 0x78) +#define CSR_RX_RSFEC_PHY_CERR_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x7c) +#define CSR_RX_RSFEC_PHY_CERR_INT_SET (CSR_RX_RSFEC_BASE + 0x80) +#define CSR_RX_RSFEC_PHY_UERR_INT_STATUS (CSR_RX_RSFEC_BASE + 0x84) +#define CSR_RX_RSFEC_PHY_UERR_INT_ENABLE (CSR_RX_RSFEC_BASE + 0x88) +#define CSR_RX_RSFEC_PHY_UERR_INT_SET (CSR_RX_RSFEC_BASE + 0x8c) +#define CSR_RX_RSFEC_IERR_U_INFO (CSR_RX_RSFEC_BASE + 0x90) +#define CSR_RX_RSFEC_IERR_C_INFO (CSR_RX_RSFEC_BASE + 0x94) +#define CSR_RX_RSFEC_IERR_U_CNT (CSR_RX_RSFEC_BASE + 0x98) +#define CSR_RX_RSFEC_IERR_C_CNT (CSR_RX_RSFEC_BASE + 0x9c) +#define CSR_RX_RSFEC_PHY_RSTN (CSR_RX_RSFEC_BASE + 0xa0) +#define CSR_RX_RSFEC_PHY0_SUBPHY_RSTN (CSR_RX_RSFEC_BASE + 0xc0) +#define CSR_RX_RSFEC_PHY2_SUBPHY_RSTN (CSR_RX_RSFEC_BASE + 0xd0) +#define CSR_RX_RSFEC_MEM_INIT_START (CSR_RX_RSFEC_BASE + 0xd8) +#define CSR_RX_RSFEC_MEM_INIT_STATUS (CSR_RX_RSFEC_BASE + 0xdc) +#define CSR_RX_RSFEC_DBG_IERR_INSERT (CSR_RX_RSFEC_BASE + 0xe0) +#define CSR_RX_RSFEC_PHY_DEC_MEM_ADDR_CFG (CSR_RX_RSFEC_BASE + 0x100) +#define CSR_RX_RSFEC_PHY_SU_MEM_ADDR_CFG (CSR_RX_RSFEC_BASE + 0x120) +#define CSR_RX_RSFEC_IDC_PIPE_CFG (CSR_RX_RSFEC_BASE + 0x140) +#define CSR_RX_RSFEC_DEC_ERR_PAT_CFG (CSR_RX_RSFEC_BASE + 0x144) +#define CSR_RX_RSFEC_DEC_ERR_PAT_CFG2 (CSR_RX_RSFEC_BASE + 0x148) +#define CSR_RX_RSFEC_DEC_ERR_PAT_LANE (CSR_RX_RSFEC_BASE + 0x160) +#define CSR_RX_RSFEC_PRBS_MOD_CFG (CSR_RX_RSFEC_BASE + 0x180) +#define CSR_RX_RSFEC_DEC_DFX_CFG (CSR_RX_RSFEC_BASE + 0x184) +#define CSR_RX_RSFEC_DEC_DFX_GAP_CFG (CSR_RX_RSFEC_BASE + 0x188) +#define CSR_RX_RSFEC_DEC_DFX_STATUS (CSR_RX_RSFEC_BASE + 0x190) +#define CSR_RX_RSFEC_PRBS_ERR_CNT (CSR_RX_RSFEC_BASE + 0x194) +#define CSR_RX_RSFEC_PRBS_BIT_CNT (CSR_RX_RSFEC_BASE + 0x198) +#define CSR_RX_RSFEC_PRBS_SYM_CNT (CSR_RX_RSFEC_BASE + 0x19c) +#define CSR_RX_RSFEC_PRBS_CW_CNT (CSR_RX_RSFEC_BASE + 0x1a0) +#define CSR_RX_RSFEC_PRBS_STATUS (CSR_RX_RSFEC_BASE + 0x1a4) +#define CSR_RX_RSFEC_CW_DEC_ALL_CNT (CSR_RX_RSFEC_BASE + 0x1a8) +#define CSR_RX_RSFEC_CW_1SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1b0) +#define CSR_RX_RSFEC_CW_2SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1b8) +#define CSR_RX_RSFEC_CW_3SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1c0) +#define CSR_RX_RSFEC_CW_4SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1c8) +#define CSR_RX_RSFEC_CW_5SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1d0) +#define CSR_RX_RSFEC_CW_6SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1d8) +#define CSR_RX_RSFEC_CW_7SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1e0) +#define CSR_RX_RSFEC_CW_8SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1e8) +#define CSR_RX_RSFEC_CW_9SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1f0) +#define CSR_RX_RSFEC_CW_10SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x1f8) +#define CSR_RX_RSFEC_CW_11SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x200) +#define CSR_RX_RSFEC_CW_12SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x208) +#define CSR_RX_RSFEC_CW_13SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x210) +#define CSR_RX_RSFEC_CW_14SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x218) +#define CSR_RX_RSFEC_CW_15SYM_ERR_CNT (CSR_RX_RSFEC_BASE + 0x220) +#define CSR_RX_RSFEC_CW_FAIL_ERR_CNT (CSR_RX_RSFEC_BASE + 0x228) +#define CSR_RX_RSFEC_CW_1SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x230) +#define CSR_RX_RSFEC_CW_2SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x238) +#define CSR_RX_RSFEC_CW_3SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x240) +#define CSR_RX_RSFEC_CW_4SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x248) +#define CSR_RX_RSFEC_CW_5SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x250) +#define CSR_RX_RSFEC_CW_6SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x258) +#define CSR_RX_RSFEC_CW_7SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x260) +#define CSR_RX_RSFEC_CW_8SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x268) +#define CSR_RX_RSFEC_CW_9SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x270) +#define CSR_RX_RSFEC_CW_10SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x278) +#define CSR_RX_RSFEC_CW_11SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x280) +#define CSR_RX_RSFEC_CW_12SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x288) +#define CSR_RX_RSFEC_CW_13SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x290) +#define CSR_RX_RSFEC_CW_14SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x298) +#define CSR_RX_RSFEC_CW_15SYM_ERR_BUR_CNT (CSR_RX_RSFEC_BASE + 0x2a0) +#define CSR_RX_RSFEC_SPARE (CSR_RX_RSFEC_BASE + 0x400) +#define CSR_RX_RSFEC_SPARE_CNT (CSR_RX_RSFEC_BASE + 0x404) +#define CSR_RX_RSFEC_PHY0_CONTROL (CSR_RX_RSFEC_BASE + 0x800) +#define CSR_RX_RSFEC_PHY0_HISER_CFG (CSR_RX_RSFEC_BASE + 0x804) +#define CSR_RX_RSFEC_PHY0_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x808) +#define CSR_RX_RSFEC_PHY0_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x80c) +#define CSR_RX_RSFEC_PHY0_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x810) +#define CSR_RX_RSFEC_PHY0_HEE_CFG (CSR_RX_RSFEC_BASE + 0x814) +#define CSR_RX_RSFEC_PHY0_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x818) +#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x81c) +#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x820) +#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x824) +#define CSR_RX_RSFEC_PHY0_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x828) +#define CSR_RX_RSFEC_PHY0_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x82c) +#define CSR_RX_RSFEC_PHY0_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x830) +#define CSR_RX_RSFEC_PHY0_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x834) +#define CSR_RX_RSFEC_PHY0_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x838) +#define CSR_RX_RSFEC_PHY0_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x83c) +#define CSR_RX_RSFEC_PHY0_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x840) +#define CSR_RX_RSFEC_PHY0_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x844) +#define CSR_RX_RSFEC_PHY0_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x850) +#define CSR_RX_RSFEC_PHY0_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x854) +#define CSR_RX_RSFEC_PHY0_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x858) +#define CSR_RX_RSFEC_PHY0_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x85c) +#define CSR_RX_RSFEC_PHY0_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x860) +#define CSR_RX_RSFEC_PHY0_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x864) +#define CSR_RX_RSFEC_PHY0_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x868) +#define CSR_RX_RSFEC_PHY0_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x86c) +#define CSR_RX_RSFEC_PHY0_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x870) +#define CSR_RX_RSFEC_PHY0_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x874) +#define CSR_RX_RSFEC_PHY0_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x878) +#define CSR_RX_RSFEC_PHY0_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x87c) +#define CSR_RX_RSFEC_PHY0_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x880) +#define CSR_RX_RSFEC_PHY0_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x884) +#define CSR_RX_RSFEC_PHY0_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x888) +#define CSR_RX_RSFEC_PHY0_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x88c) +#define CSR_RX_RSFEC_PHY0_STATUS (CSR_RX_RSFEC_BASE + 0x890) +#define CSR_RX_RSFEC_PHY0_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x894) +#define CSR_RX_RSFEC_PHY0_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x898) +#define CSR_RX_RSFEC_PHY0_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x89c) +#define CSR_RX_RSFEC_PHY0_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x8a0) +#define CSR_RX_RSFEC_PHY0_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x8a4) +#define CSR_RX_RSFEC_PHY0_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x8a8) +#define CSR_RX_RSFEC_PHY0_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x8ac) +#define CSR_RX_RSFEC_PHY0_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x8b0) +#define CSR_RX_RSFEC_PHY0_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x900) +#define CSR_RX_RSFEC_PHY0_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x908) +#define CSR_RX_RSFEC_PHY0_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x910) +#define CSR_RX_RSFEC_PHY0_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x918) +#define CSR_RX_RSFEC_PHY0_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x940) +#define CSR_RX_RSFEC_PHY0_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x980) +#define CSR_RX_RSFEC_PHY0_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x9c0) +#define CSR_RX_RSFEC_PHY1_CONTROL (CSR_RX_RSFEC_BASE + 0xa00) +#define CSR_RX_RSFEC_PHY1_HISER_CFG (CSR_RX_RSFEC_BASE + 0xa04) +#define CSR_RX_RSFEC_PHY1_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0xa08) +#define CSR_RX_RSFEC_PHY1_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0xa0c) +#define CSR_RX_RSFEC_PHY1_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0xa10) +#define CSR_RX_RSFEC_PHY1_HEE_CFG (CSR_RX_RSFEC_BASE + 0xa14) +#define CSR_RX_RSFEC_PHY1_DIAG_CFG (CSR_RX_RSFEC_BASE + 0xa18) +#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0xa1c) +#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0xa20) +#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0xa24) +#define CSR_RX_RSFEC_PHY1_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0xa28) +#define CSR_RX_RSFEC_PHY1_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0xa2c) +#define CSR_RX_RSFEC_PHY1_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0xa30) +#define CSR_RX_RSFEC_PHY1_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0xa34) +#define CSR_RX_RSFEC_PHY1_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0xa38) +#define CSR_RX_RSFEC_PHY1_HI_BER_SET (CSR_RX_RSFEC_BASE + 0xa3c) +#define CSR_RX_RSFEC_PHY1_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0xa40) +#define CSR_RX_RSFEC_PHY1_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0xa44) +#define CSR_RX_RSFEC_PHY1_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa50) +#define CSR_RX_RSFEC_PHY1_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa54) +#define CSR_RX_RSFEC_PHY1_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa58) +#define CSR_RX_RSFEC_PHY1_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xa5c) +#define CSR_RX_RSFEC_PHY1_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa60) +#define CSR_RX_RSFEC_PHY1_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa64) +#define CSR_RX_RSFEC_PHY1_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa68) +#define CSR_RX_RSFEC_PHY1_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xa6c) +#define CSR_RX_RSFEC_PHY1_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa70) +#define CSR_RX_RSFEC_PHY1_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa74) +#define CSR_RX_RSFEC_PHY1_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa78) +#define CSR_RX_RSFEC_PHY1_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xa7c) +#define CSR_RX_RSFEC_PHY1_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa80) +#define CSR_RX_RSFEC_PHY1_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa84) +#define CSR_RX_RSFEC_PHY1_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa88) +#define CSR_RX_RSFEC_PHY1_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xa8c) +#define CSR_RX_RSFEC_PHY1_STATUS (CSR_RX_RSFEC_BASE + 0xa90) +#define CSR_RX_RSFEC_PHY1_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0xa94) +#define CSR_RX_RSFEC_PHY1_BOND_STATUS (CSR_RX_RSFEC_BASE + 0xa98) +#define CSR_RX_RSFEC_PHY1_ISO_STATUS (CSR_RX_RSFEC_BASE + 0xa9c) +#define CSR_RX_RSFEC_PHY1_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0xaa0) +#define CSR_RX_RSFEC_PHY1_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0xaa4) +#define CSR_RX_RSFEC_PHY1_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0xaa8) +#define CSR_RX_RSFEC_PHY1_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0xaac) +#define CSR_RX_RSFEC_PHY1_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0xab0) +#define CSR_RX_RSFEC_PHY1_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb00) +#define CSR_RX_RSFEC_PHY1_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb08) +#define CSR_RX_RSFEC_PHY1_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb10) +#define CSR_RX_RSFEC_PHY1_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xb18) +#define CSR_RX_RSFEC_PHY1_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0xb20) +#define CSR_RX_RSFEC_PHY1_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0xb30) +#define CSR_RX_RSFEC_PHY1_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0xb40) +#define CSR_RX_RSFEC_PHY2_CONTROL (CSR_RX_RSFEC_BASE + 0xc00) +#define CSR_RX_RSFEC_PHY2_HISER_CFG (CSR_RX_RSFEC_BASE + 0xc04) +#define CSR_RX_RSFEC_PHY2_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0xc08) +#define CSR_RX_RSFEC_PHY2_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0xc0c) +#define CSR_RX_RSFEC_PHY2_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0xc10) +#define CSR_RX_RSFEC_PHY2_HEE_CFG (CSR_RX_RSFEC_BASE + 0xc14) +#define CSR_RX_RSFEC_PHY2_DIAG_CFG (CSR_RX_RSFEC_BASE + 0xc18) +#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0xc1c) +#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0xc20) +#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0xc24) +#define CSR_RX_RSFEC_PHY2_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0xc28) +#define CSR_RX_RSFEC_PHY2_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0xc2c) +#define CSR_RX_RSFEC_PHY2_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0xc30) +#define CSR_RX_RSFEC_PHY2_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0xc34) +#define CSR_RX_RSFEC_PHY2_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0xc38) +#define CSR_RX_RSFEC_PHY2_HI_BER_SET (CSR_RX_RSFEC_BASE + 0xc3c) +#define CSR_RX_RSFEC_PHY2_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0xc40) +#define CSR_RX_RSFEC_PHY2_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0xc44) +#define CSR_RX_RSFEC_PHY2_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc50) +#define CSR_RX_RSFEC_PHY2_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc54) +#define CSR_RX_RSFEC_PHY2_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc58) +#define CSR_RX_RSFEC_PHY2_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xc5c) +#define CSR_RX_RSFEC_PHY2_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc60) +#define CSR_RX_RSFEC_PHY2_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc64) +#define CSR_RX_RSFEC_PHY2_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc68) +#define CSR_RX_RSFEC_PHY2_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xc6c) +#define CSR_RX_RSFEC_PHY2_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc70) +#define CSR_RX_RSFEC_PHY2_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc74) +#define CSR_RX_RSFEC_PHY2_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc78) +#define CSR_RX_RSFEC_PHY2_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xc7c) +#define CSR_RX_RSFEC_PHY2_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc80) +#define CSR_RX_RSFEC_PHY2_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc84) +#define CSR_RX_RSFEC_PHY2_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc88) +#define CSR_RX_RSFEC_PHY2_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xc8c) +#define CSR_RX_RSFEC_PHY2_STATUS (CSR_RX_RSFEC_BASE + 0xc90) +#define CSR_RX_RSFEC_PHY2_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0xc94) +#define CSR_RX_RSFEC_PHY2_BOND_STATUS (CSR_RX_RSFEC_BASE + 0xc98) +#define CSR_RX_RSFEC_PHY2_ISO_STATUS (CSR_RX_RSFEC_BASE + 0xc9c) +#define CSR_RX_RSFEC_PHY2_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0xca0) +#define CSR_RX_RSFEC_PHY2_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0xca4) +#define CSR_RX_RSFEC_PHY2_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0xca8) +#define CSR_RX_RSFEC_PHY2_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0xcac) +#define CSR_RX_RSFEC_PHY2_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0xcb0) +#define CSR_RX_RSFEC_PHY2_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd00) +#define CSR_RX_RSFEC_PHY2_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd08) +#define CSR_RX_RSFEC_PHY2_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd10) +#define CSR_RX_RSFEC_PHY2_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xd18) +#define CSR_RX_RSFEC_PHY2_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0xd20) +#define CSR_RX_RSFEC_PHY2_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0xd40) +#define CSR_RX_RSFEC_PHY2_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0xd60) +#define CSR_RX_RSFEC_PHY3_CONTROL (CSR_RX_RSFEC_BASE + 0xe00) +#define CSR_RX_RSFEC_PHY3_HISER_CFG (CSR_RX_RSFEC_BASE + 0xe04) +#define CSR_RX_RSFEC_PHY3_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0xe08) +#define CSR_RX_RSFEC_PHY3_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0xe0c) +#define CSR_RX_RSFEC_PHY3_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0xe10) +#define CSR_RX_RSFEC_PHY3_HEE_CFG (CSR_RX_RSFEC_BASE + 0xe14) +#define CSR_RX_RSFEC_PHY3_DIAG_CFG (CSR_RX_RSFEC_BASE + 0xe18) +#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0xe1c) +#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0xe20) +#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0xe24) +#define CSR_RX_RSFEC_PHY3_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0xe28) +#define CSR_RX_RSFEC_PHY3_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0xe2c) +#define CSR_RX_RSFEC_PHY3_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0xe30) +#define CSR_RX_RSFEC_PHY3_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0xe34) +#define CSR_RX_RSFEC_PHY3_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0xe38) +#define CSR_RX_RSFEC_PHY3_HI_BER_SET (CSR_RX_RSFEC_BASE + 0xe3c) +#define CSR_RX_RSFEC_PHY3_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0xe40) +#define CSR_RX_RSFEC_PHY3_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0xe44) +#define CSR_RX_RSFEC_PHY3_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe50) +#define CSR_RX_RSFEC_PHY3_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe54) +#define CSR_RX_RSFEC_PHY3_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe58) +#define CSR_RX_RSFEC_PHY3_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0xe5c) +#define CSR_RX_RSFEC_PHY3_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe60) +#define CSR_RX_RSFEC_PHY3_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe64) +#define CSR_RX_RSFEC_PHY3_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe68) +#define CSR_RX_RSFEC_PHY3_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0xe6c) +#define CSR_RX_RSFEC_PHY3_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe70) +#define CSR_RX_RSFEC_PHY3_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe74) +#define CSR_RX_RSFEC_PHY3_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe78) +#define CSR_RX_RSFEC_PHY3_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0xe7c) +#define CSR_RX_RSFEC_PHY3_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe80) +#define CSR_RX_RSFEC_PHY3_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe84) +#define CSR_RX_RSFEC_PHY3_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe88) +#define CSR_RX_RSFEC_PHY3_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0xe8c) +#define CSR_RX_RSFEC_PHY3_STATUS (CSR_RX_RSFEC_BASE + 0xe90) +#define CSR_RX_RSFEC_PHY3_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0xe94) +#define CSR_RX_RSFEC_PHY3_BOND_STATUS (CSR_RX_RSFEC_BASE + 0xe98) +#define CSR_RX_RSFEC_PHY3_ISO_STATUS (CSR_RX_RSFEC_BASE + 0xe9c) +#define CSR_RX_RSFEC_PHY3_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0xea0) +#define CSR_RX_RSFEC_PHY3_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0xea4) +#define CSR_RX_RSFEC_PHY3_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0xea8) +#define CSR_RX_RSFEC_PHY3_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0xeac) +#define CSR_RX_RSFEC_PHY3_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0xeb0) +#define CSR_RX_RSFEC_PHY3_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf00) +#define CSR_RX_RSFEC_PHY3_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf08) +#define CSR_RX_RSFEC_PHY3_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf10) +#define CSR_RX_RSFEC_PHY3_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0xf18) +#define CSR_RX_RSFEC_PHY3_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0xf20) +#define CSR_RX_RSFEC_PHY3_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0xf30) +#define CSR_RX_RSFEC_PHY3_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0xf40) +#define CSR_RX_RSFEC_PHY4_CONTROL (CSR_RX_RSFEC_BASE + 0x1000) +#define CSR_RX_RSFEC_PHY4_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1004) +#define CSR_RX_RSFEC_PHY4_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1008) +#define CSR_RX_RSFEC_PHY4_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x100c) +#define CSR_RX_RSFEC_PHY4_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1010) +#define CSR_RX_RSFEC_PHY4_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1014) +#define CSR_RX_RSFEC_PHY4_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1018) +#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x101c) +#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1020) +#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1024) +#define CSR_RX_RSFEC_PHY4_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1028) +#define CSR_RX_RSFEC_PHY4_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x102c) +#define CSR_RX_RSFEC_PHY4_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1030) +#define CSR_RX_RSFEC_PHY4_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1034) +#define CSR_RX_RSFEC_PHY4_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1038) +#define CSR_RX_RSFEC_PHY4_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x103c) +#define CSR_RX_RSFEC_PHY4_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1040) +#define CSR_RX_RSFEC_PHY4_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1044) +#define CSR_RX_RSFEC_PHY4_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1050) +#define CSR_RX_RSFEC_PHY4_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1054) +#define CSR_RX_RSFEC_PHY4_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1058) +#define CSR_RX_RSFEC_PHY4_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x105c) +#define CSR_RX_RSFEC_PHY4_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1060) +#define CSR_RX_RSFEC_PHY4_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1064) +#define CSR_RX_RSFEC_PHY4_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1068) +#define CSR_RX_RSFEC_PHY4_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x106c) +#define CSR_RX_RSFEC_PHY4_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1070) +#define CSR_RX_RSFEC_PHY4_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1074) +#define CSR_RX_RSFEC_PHY4_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1078) +#define CSR_RX_RSFEC_PHY4_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x107c) +#define CSR_RX_RSFEC_PHY4_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1080) +#define CSR_RX_RSFEC_PHY4_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1084) +#define CSR_RX_RSFEC_PHY4_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1088) +#define CSR_RX_RSFEC_PHY4_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x108c) +#define CSR_RX_RSFEC_PHY4_STATUS (CSR_RX_RSFEC_BASE + 0x1090) +#define CSR_RX_RSFEC_PHY4_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1094) +#define CSR_RX_RSFEC_PHY4_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1098) +#define CSR_RX_RSFEC_PHY4_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x109c) +#define CSR_RX_RSFEC_PHY4_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x10a0) +#define CSR_RX_RSFEC_PHY4_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x10a4) +#define CSR_RX_RSFEC_PHY4_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x10a8) +#define CSR_RX_RSFEC_PHY4_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x10ac) +#define CSR_RX_RSFEC_PHY4_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x10b0) +#define CSR_RX_RSFEC_PHY4_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1100) +#define CSR_RX_RSFEC_PHY4_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1108) +#define CSR_RX_RSFEC_PHY4_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1110) +#define CSR_RX_RSFEC_PHY4_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1118) +#define CSR_RX_RSFEC_PHY4_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1120) +#define CSR_RX_RSFEC_PHY4_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1140) +#define CSR_RX_RSFEC_PHY4_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1160) +#define CSR_RX_RSFEC_PHY5_CONTROL (CSR_RX_RSFEC_BASE + 0x1200) +#define CSR_RX_RSFEC_PHY5_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1204) +#define CSR_RX_RSFEC_PHY5_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1208) +#define CSR_RX_RSFEC_PHY5_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x120c) +#define CSR_RX_RSFEC_PHY5_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1210) +#define CSR_RX_RSFEC_PHY5_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1214) +#define CSR_RX_RSFEC_PHY5_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1218) +#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x121c) +#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1220) +#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1224) +#define CSR_RX_RSFEC_PHY5_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1228) +#define CSR_RX_RSFEC_PHY5_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x122c) +#define CSR_RX_RSFEC_PHY5_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1230) +#define CSR_RX_RSFEC_PHY5_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1234) +#define CSR_RX_RSFEC_PHY5_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1238) +#define CSR_RX_RSFEC_PHY5_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x123c) +#define CSR_RX_RSFEC_PHY5_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1240) +#define CSR_RX_RSFEC_PHY5_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1244) +#define CSR_RX_RSFEC_PHY5_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1250) +#define CSR_RX_RSFEC_PHY5_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1254) +#define CSR_RX_RSFEC_PHY5_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1258) +#define CSR_RX_RSFEC_PHY5_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x125c) +#define CSR_RX_RSFEC_PHY5_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1260) +#define CSR_RX_RSFEC_PHY5_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1264) +#define CSR_RX_RSFEC_PHY5_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1268) +#define CSR_RX_RSFEC_PHY5_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x126c) +#define CSR_RX_RSFEC_PHY5_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1270) +#define CSR_RX_RSFEC_PHY5_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1274) +#define CSR_RX_RSFEC_PHY5_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1278) +#define CSR_RX_RSFEC_PHY5_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x127c) +#define CSR_RX_RSFEC_PHY5_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1280) +#define CSR_RX_RSFEC_PHY5_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1284) +#define CSR_RX_RSFEC_PHY5_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1288) +#define CSR_RX_RSFEC_PHY5_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x128c) +#define CSR_RX_RSFEC_PHY5_STATUS (CSR_RX_RSFEC_BASE + 0x1290) +#define CSR_RX_RSFEC_PHY5_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1294) +#define CSR_RX_RSFEC_PHY5_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1298) +#define CSR_RX_RSFEC_PHY5_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x129c) +#define CSR_RX_RSFEC_PHY5_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x12a0) +#define CSR_RX_RSFEC_PHY5_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x12a4) +#define CSR_RX_RSFEC_PHY5_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x12a8) +#define CSR_RX_RSFEC_PHY5_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x12ac) +#define CSR_RX_RSFEC_PHY5_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x12b0) +#define CSR_RX_RSFEC_PHY5_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1300) +#define CSR_RX_RSFEC_PHY5_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1304) +#define CSR_RX_RSFEC_PHY5_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1308) +#define CSR_RX_RSFEC_PHY5_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x130c) +#define CSR_RX_RSFEC_PHY5_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1310) +#define CSR_RX_RSFEC_PHY5_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1318) +#define CSR_RX_RSFEC_PHY5_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1320) +#define CSR_RX_RSFEC_PHY6_CONTROL (CSR_RX_RSFEC_BASE + 0x1400) +#define CSR_RX_RSFEC_PHY6_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1404) +#define CSR_RX_RSFEC_PHY6_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1408) +#define CSR_RX_RSFEC_PHY6_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x140c) +#define CSR_RX_RSFEC_PHY6_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1410) +#define CSR_RX_RSFEC_PHY6_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1414) +#define CSR_RX_RSFEC_PHY6_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1418) +#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x141c) +#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1420) +#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1424) +#define CSR_RX_RSFEC_PHY6_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1428) +#define CSR_RX_RSFEC_PHY6_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x142c) +#define CSR_RX_RSFEC_PHY6_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1430) +#define CSR_RX_RSFEC_PHY6_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1434) +#define CSR_RX_RSFEC_PHY6_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1438) +#define CSR_RX_RSFEC_PHY6_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x143c) +#define CSR_RX_RSFEC_PHY6_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1440) +#define CSR_RX_RSFEC_PHY6_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1444) +#define CSR_RX_RSFEC_PHY6_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1450) +#define CSR_RX_RSFEC_PHY6_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1454) +#define CSR_RX_RSFEC_PHY6_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1458) +#define CSR_RX_RSFEC_PHY6_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x145c) +#define CSR_RX_RSFEC_PHY6_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1460) +#define CSR_RX_RSFEC_PHY6_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1464) +#define CSR_RX_RSFEC_PHY6_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1468) +#define CSR_RX_RSFEC_PHY6_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x146c) +#define CSR_RX_RSFEC_PHY6_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1470) +#define CSR_RX_RSFEC_PHY6_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1474) +#define CSR_RX_RSFEC_PHY6_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1478) +#define CSR_RX_RSFEC_PHY6_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x147c) +#define CSR_RX_RSFEC_PHY6_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1480) +#define CSR_RX_RSFEC_PHY6_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1484) +#define CSR_RX_RSFEC_PHY6_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1488) +#define CSR_RX_RSFEC_PHY6_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x148c) +#define CSR_RX_RSFEC_PHY6_STATUS (CSR_RX_RSFEC_BASE + 0x1490) +#define CSR_RX_RSFEC_PHY6_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1494) +#define CSR_RX_RSFEC_PHY6_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1498) +#define CSR_RX_RSFEC_PHY6_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x149c) +#define CSR_RX_RSFEC_PHY6_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x14a0) +#define CSR_RX_RSFEC_PHY6_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x14a4) +#define CSR_RX_RSFEC_PHY6_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x14a8) +#define CSR_RX_RSFEC_PHY6_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x14ac) +#define CSR_RX_RSFEC_PHY6_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x14b0) +#define CSR_RX_RSFEC_PHY6_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1500) +#define CSR_RX_RSFEC_PHY6_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1508) +#define CSR_RX_RSFEC_PHY6_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1510) +#define CSR_RX_RSFEC_PHY6_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1518) +#define CSR_RX_RSFEC_PHY6_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1520) +#define CSR_RX_RSFEC_PHY6_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1530) +#define CSR_RX_RSFEC_PHY6_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1540) +#define CSR_RX_RSFEC_PHY7_CONTROL (CSR_RX_RSFEC_BASE + 0x1600) +#define CSR_RX_RSFEC_PHY7_HISER_CFG (CSR_RX_RSFEC_BASE + 0x1604) +#define CSR_RX_RSFEC_PHY7_HISER_GAP_CFG (CSR_RX_RSFEC_BASE + 0x1608) +#define CSR_RX_RSFEC_PHY7_ERR_STA_CFG (CSR_RX_RSFEC_BASE + 0x160c) +#define CSR_RX_RSFEC_PHY7_LINK_TIMEOUT_CFG (CSR_RX_RSFEC_BASE + 0x1610) +#define CSR_RX_RSFEC_PHY7_HEE_CFG (CSR_RX_RSFEC_BASE + 0x1614) +#define CSR_RX_RSFEC_PHY7_DIAG_CFG (CSR_RX_RSFEC_BASE + 0x1618) +#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_CFG (CSR_RX_RSFEC_BASE + 0x161c) +#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_SET (CSR_RX_RSFEC_BASE + 0x1620) +#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_CLR (CSR_RX_RSFEC_BASE + 0x1624) +#define CSR_RX_RSFEC_PHY7_DEGRADE_SER_CW (CSR_RX_RSFEC_BASE + 0x1628) +#define CSR_RX_RSFEC_PHY7_PHY_BER_CFG (CSR_RX_RSFEC_BASE + 0x162c) +#define CSR_RX_RSFEC_PHY7_PHY_BER_SET (CSR_RX_RSFEC_BASE + 0x1630) +#define CSR_RX_RSFEC_PHY7_PHY_BER_CLR (CSR_RX_RSFEC_BASE + 0x1634) +#define CSR_RX_RSFEC_PHY7_PHY_BER_CW (CSR_RX_RSFEC_BASE + 0x1638) +#define CSR_RX_RSFEC_PHY7_HI_BER_SET (CSR_RX_RSFEC_BASE + 0x163c) +#define CSR_RX_RSFEC_PHY7_HI_BER_CLR (CSR_RX_RSFEC_BASE + 0x1640) +#define CSR_RX_RSFEC_PHY7_HI_BER_GAP (CSR_RX_RSFEC_BASE + 0x1644) +#define CSR_RX_RSFEC_PHY7_SD_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1650) +#define CSR_RX_RSFEC_PHY7_SD_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1654) +#define CSR_RX_RSFEC_PHY7_SF_SET_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x1658) +#define CSR_RX_RSFEC_PHY7_SF_CLR_WINDOW_NS (CSR_RX_RSFEC_BASE + 0x165c) +#define CSR_RX_RSFEC_PHY7_SD_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1660) +#define CSR_RX_RSFEC_PHY7_SD_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1664) +#define CSR_RX_RSFEC_PHY7_SF_SET_WINDOW_B (CSR_RX_RSFEC_BASE + 0x1668) +#define CSR_RX_RSFEC_PHY7_SF_CLR_WINDOW_B (CSR_RX_RSFEC_BASE + 0x166c) +#define CSR_RX_RSFEC_PHY7_SD_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1670) +#define CSR_RX_RSFEC_PHY7_SD_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1674) +#define CSR_RX_RSFEC_PHY7_SF_SET_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x1678) +#define CSR_RX_RSFEC_PHY7_SF_CLR_THRESHOLD_L (CSR_RX_RSFEC_BASE + 0x167c) +#define CSR_RX_RSFEC_PHY7_SD_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1680) +#define CSR_RX_RSFEC_PHY7_SD_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1684) +#define CSR_RX_RSFEC_PHY7_SF_SET_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x1688) +#define CSR_RX_RSFEC_PHY7_SF_CLR_THRESHOLD_M (CSR_RX_RSFEC_BASE + 0x168c) +#define CSR_RX_RSFEC_PHY7_STATUS (CSR_RX_RSFEC_BASE + 0x1690) +#define CSR_RX_RSFEC_PHY7_RX_HIS_STATUS (CSR_RX_RSFEC_BASE + 0x1694) +#define CSR_RX_RSFEC_PHY7_BOND_STATUS (CSR_RX_RSFEC_BASE + 0x1698) +#define CSR_RX_RSFEC_PHY7_ISO_STATUS (CSR_RX_RSFEC_BASE + 0x169c) +#define CSR_RX_RSFEC_PHY7_TIME_OUT_STATUS (CSR_RX_RSFEC_BASE + 0x16a0) +#define CSR_RX_RSFEC_PHY7_IDLE_CHK_ERR_CNT (CSR_RX_RSFEC_BASE + 0x16a4) +#define CSR_RX_RSFEC_PHY7_RX_INV_BLOCK_CNT (CSR_RX_RSFEC_BASE + 0x16a8) +#define CSR_RX_RSFEC_PHY7_ERR_BIT_CNT (CSR_RX_RSFEC_BASE + 0x16ac) +#define CSR_RX_RSFEC_PHY7_ERR_SYM_CNT (CSR_RX_RSFEC_BASE + 0x16b0) +#define CSR_RX_RSFEC_PHY7_DEC_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1700) +#define CSR_RX_RSFEC_PHY7_ERR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1704) +#define CSR_RX_RSFEC_PHY7_CORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x1708) +#define CSR_RX_RSFEC_PHY7_UNCORR_CW_CNT_ (CSR_RX_RSFEC_BASE + 0x170c) +#define CSR_RX_RSFEC_PHY7_CORR_LANE_SYM_CNT_ (CSR_RX_RSFEC_BASE + 0x1710) +#define CSR_RX_RSFEC_PHY7_LANE_COR0_CNT_ (CSR_RX_RSFEC_BASE + 0x1718) +#define CSR_RX_RSFEC_PHY7_LANE_COR1_CNT_ (CSR_RX_RSFEC_BASE + 0x1720) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rxpma_core_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rxpma_core_offset.h new file mode 100644 index 000000000..1bbd26463 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rxpma_core_offset.h @@ -0,0 +1,213 @@ +#ifndef MAC_REG_RXPMA_CORE_H +#define MAC_REG_RXPMA_CORE_H + +/* Base address of Module's Register */ +#define CSR_RXPMA_CORE_BASE (0x14000) + +#define CSR_RXPMA_CORE_INT_STATUS (CSR_RXPMA_CORE_BASE + 0x0) +#define CSR_RXPMA_CORE_INT_ENABLE (CSR_RXPMA_CORE_BASE + 0x4) +#define CSR_RXPMA_CORE_INT_SET (CSR_RXPMA_CORE_BASE + 0x8) +#define CSR_RXPMA_CORE_OVF_INT_STATUS (CSR_RXPMA_CORE_BASE + 0xc) +#define CSR_RXPMA_CORE_OVF_INT_ENABLE (CSR_RXPMA_CORE_BASE + 0x10) +#define CSR_RXPMA_CORE_OVF_INT_SET (CSR_RXPMA_CORE_BASE + 0x14) +#define CSR_RXPMA_CORE_UDF_INT_STATUS (CSR_RXPMA_CORE_BASE + 0x18) +#define CSR_RXPMA_CORE_UDF_INT_ENABLE (CSR_RXPMA_CORE_BASE + 0x1c) +#define CSR_RXPMA_CORE_UDF_INT_SET (CSR_RXPMA_CORE_BASE + 0x20) +#define CSR_RXPMA_CORE_IERR_U_INFO (CSR_RXPMA_CORE_BASE + 0x800) +#define CSR_RXPMA_CORE_IERR_C_INFO (CSR_RXPMA_CORE_BASE + 0x804) +#define CSR_RXPMA_CORE_IERR_U_CNT (CSR_RXPMA_CORE_BASE + 0x808) +#define CSR_RXPMA_CORE_IERR_C_CNT (CSR_RXPMA_CORE_BASE + 0x80c) +#define CSR_RXPMA_CORE_PHY_RSTN (CSR_RXPMA_CORE_BASE + 0x820) +#define CSR_RXPMA_CORE_CALENDAR_TABLE (CSR_RXPMA_CORE_BASE + 0x840) +#define CSR_RXPMA_CORE_CALEN_DEPTH (CSR_RXPMA_CORE_BASE + 0x880) +#define CSR_RXPMA_CORE_CALEN_SEL (CSR_RXPMA_CORE_BASE + 0x884) +#define CSR_RXPMA_CORE_COMB1_CALENDAR_TABLE (CSR_RXPMA_CORE_BASE + 0x8c0) +#define CSR_RXPMA_CORE_COMB1_CALEN_DEPTH (CSR_RXPMA_CORE_BASE + 0x900) +#define CSR_RXPMA_CORE_COMB1_CALEN_SEL (CSR_RXPMA_CORE_BASE + 0x904) +#define CSR_RXPMA_CORE_PHY_AMWINSIZE (CSR_RXPMA_CORE_BASE + 0x920) +#define CSR_RXPMA_CORE_PHY_MODE (CSR_RXPMA_CORE_BASE + 0x940) +#define CSR_RXPMA_CORE_PTP_CLK_FREQ_SEL (CSR_RXPMA_CORE_BASE + 0x960) +#define CSR_RXPMA_CORE_RTC_PERIOD_MAC_CORE_CLK (CSR_RXPMA_CORE_BASE + 0x964) +#define CSR_RXPMA_CORE_MULTI_PHASE_SEL (CSR_RXPMA_CORE_BASE + 0x968) +#define CSR_RXPMA_CORE_VL_MAP (CSR_RXPMA_CORE_BASE + 0x96c) +#define CSR_RXPMA_CORE_TX_TS_AGG_EN (CSR_RXPMA_CORE_BASE + 0x970) +#define CSR_RXPMA_CORE_RX_1588_TS_INFO (CSR_RXPMA_CORE_BASE + 0xa00) +#define CSR_RXPMA_CORE_PHY_1588_CW_INFO (CSR_RXPMA_CORE_BASE + 0xc00) +#define CSR_RXPMA_CORE_PHY_MAPPING (CSR_RXPMA_CORE_BASE + 0xc20) +#define CSR_RXPMA_CORE_AM0_L (CSR_RXPMA_CORE_BASE + 0xc40) +#define CSR_RXPMA_CORE_AM0_H (CSR_RXPMA_CORE_BASE + 0xc44) +#define CSR_RXPMA_CORE_AM4_L (CSR_RXPMA_CORE_BASE + 0xc48) +#define CSR_RXPMA_CORE_AM4_H (CSR_RXPMA_CORE_BASE + 0xc4c) +#define CSR_RXPMA_CORE_AM5_L (CSR_RXPMA_CORE_BASE + 0xc50) +#define CSR_RXPMA_CORE_AM5_H (CSR_RXPMA_CORE_BASE + 0xc54) +#define CSR_RXPMA_CORE_AM6_L (CSR_RXPMA_CORE_BASE + 0xc58) +#define CSR_RXPMA_CORE_AM6_H (CSR_RXPMA_CORE_BASE + 0xc5c) +#define CSR_RXPMA_CORE_AM7_L (CSR_RXPMA_CORE_BASE + 0xc60) +#define CSR_RXPMA_CORE_AM7_H (CSR_RXPMA_CORE_BASE + 0xc64) +#define CSR_RXPMA_CORE_AM8_L (CSR_RXPMA_CORE_BASE + 0xc68) +#define CSR_RXPMA_CORE_AM8_H (CSR_RXPMA_CORE_BASE + 0xc6c) +#define CSR_RXPMA_CORE_AM9_L (CSR_RXPMA_CORE_BASE + 0xc70) +#define CSR_RXPMA_CORE_AM9_H (CSR_RXPMA_CORE_BASE + 0xc74) +#define CSR_RXPMA_CORE_AM10_L (CSR_RXPMA_CORE_BASE + 0xc78) +#define CSR_RXPMA_CORE_AM10_H (CSR_RXPMA_CORE_BASE + 0xc7c) +#define CSR_RXPMA_CORE_AM11_L (CSR_RXPMA_CORE_BASE + 0xc80) +#define CSR_RXPMA_CORE_AM11_H (CSR_RXPMA_CORE_BASE + 0xc84) +#define CSR_RXPMA_CORE_AM12_L (CSR_RXPMA_CORE_BASE + 0xc88) +#define CSR_RXPMA_CORE_AM12_H (CSR_RXPMA_CORE_BASE + 0xc8c) +#define CSR_RXPMA_CORE_AM13_L (CSR_RXPMA_CORE_BASE + 0xc90) +#define CSR_RXPMA_CORE_AM13_H (CSR_RXPMA_CORE_BASE + 0xc94) +#define CSR_RXPMA_CORE_AM14_L (CSR_RXPMA_CORE_BASE + 0xc98) +#define CSR_RXPMA_CORE_AM14_H (CSR_RXPMA_CORE_BASE + 0xc9c) +#define CSR_RXPMA_CORE_AM15_L (CSR_RXPMA_CORE_BASE + 0xca0) +#define CSR_RXPMA_CORE_AM15_H (CSR_RXPMA_CORE_BASE + 0xca4) +#define CSR_RXPMA_CORE_AM0_800G_L0 (CSR_RXPMA_CORE_BASE + 0xca8) +#define CSR_RXPMA_CORE_AM0_800G_L1 (CSR_RXPMA_CORE_BASE + 0xcac) +#define CSR_RXPMA_CORE_AM0_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcb0) +#define CSR_RXPMA_CORE_AM0_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcb4) +#define CSR_RXPMA_CORE_AM1_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcb8) +#define CSR_RXPMA_CORE_AM1_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcbc) +#define CSR_RXPMA_CORE_AM2_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcc0) +#define CSR_RXPMA_CORE_AM2_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcc4) +#define CSR_RXPMA_CORE_AM3_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcc8) +#define CSR_RXPMA_CORE_AM3_800G_H1 (CSR_RXPMA_CORE_BASE + 0xccc) +#define CSR_RXPMA_CORE_AM4_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcd0) +#define CSR_RXPMA_CORE_AM4_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcd4) +#define CSR_RXPMA_CORE_AM5_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcd8) +#define CSR_RXPMA_CORE_AM5_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcdc) +#define CSR_RXPMA_CORE_AM6_800G_H0 (CSR_RXPMA_CORE_BASE + 0xce0) +#define CSR_RXPMA_CORE_AM6_800G_H1 (CSR_RXPMA_CORE_BASE + 0xce4) +#define CSR_RXPMA_CORE_AM7_800G_H0 (CSR_RXPMA_CORE_BASE + 0xce8) +#define CSR_RXPMA_CORE_AM7_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcec) +#define CSR_RXPMA_CORE_AM8_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcf0) +#define CSR_RXPMA_CORE_AM8_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcf4) +#define CSR_RXPMA_CORE_AM9_800G_H0 (CSR_RXPMA_CORE_BASE + 0xcf8) +#define CSR_RXPMA_CORE_AM9_800G_H1 (CSR_RXPMA_CORE_BASE + 0xcfc) +#define CSR_RXPMA_CORE_AM10_800G_H0 (CSR_RXPMA_CORE_BASE + 0xd00) +#define CSR_RXPMA_CORE_AM10_800G_H1 (CSR_RXPMA_CORE_BASE + 0xd04) +#define CSR_RXPMA_CORE_AM11_800G_H0 (CSR_RXPMA_CORE_BASE + 0xd08) +#define CSR_RXPMA_CORE_AM11_800G_H1 (CSR_RXPMA_CORE_BASE + 0xd0c) +#define CSR_RXPMA_CORE_AM12_800G_H0 (CSR_RXPMA_CORE_BASE + 0xd10) +#define CSR_RXPMA_CORE_AM12_800G_H1 (CSR_RXPMA_CORE_BASE + 0xd14) +#define CSR_RXPMA_CORE_AM13_800G_H0 (CSR_RXPMA_CORE_BASE + 0xd18) +#define CSR_RXPMA_CORE_AM13_800G_H1 (CSR_RXPMA_CORE_BASE + 0xd1c) +#define CSR_RXPMA_CORE_AM14_800G_H0 (CSR_RXPMA_CORE_BASE + 0xd20) +#define CSR_RXPMA_CORE_AM14_800G_H1 (CSR_RXPMA_CORE_BASE + 0xd24) +#define CSR_RXPMA_CORE_AM15_800G_H0 (CSR_RXPMA_CORE_BASE + 0xd28) +#define CSR_RXPMA_CORE_AM15_800G_H1 (CSR_RXPMA_CORE_BASE + 0xd2c) +#define CSR_RXPMA_CORE_DBG_IERR_INSERT (CSR_RXPMA_CORE_BASE + 0xd30) +#define CSR_RXPMA_CORE_SPARE (CSR_RXPMA_CORE_BASE + 0x1000) +#define CSR_RXPMA_CORE_SPARE_CNT (CSR_RXPMA_CORE_BASE + 0x1004) +#define CSR_RXPMA_CORE_PHY0_CONTROL (CSR_RXPMA_CORE_BASE + 0x2000) +#define CSR_RXPMA_CORE_PHY0_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2004) +#define CSR_RXPMA_CORE_PHY0_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2008) +#define CSR_RXPMA_CORE_PHY0_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x200c) +#define CSR_RXPMA_CORE_PHY0_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2010) +#define CSR_RXPMA_CORE_PHY0_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2014) +#define CSR_RXPMA_CORE_PHY0_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2018) +#define CSR_RXPMA_CORE_PHY0_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x201c) +#define CSR_RXPMA_CORE_PHY0_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2020) +#define CSR_RXPMA_CORE_PHY0_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2024) +#define CSR_RXPMA_CORE_PHY0_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2028) +#define CSR_RXPMA_CORE_PHY0__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2080) +#define CSR_RXPMA_CORE_PHY0__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2100) +#define CSR_RXPMA_CORE_PHY0__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2180) +#define CSR_RXPMA_CORE_PHY1_CONTROL (CSR_RXPMA_CORE_BASE + 0x2200) +#define CSR_RXPMA_CORE_PHY1_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2204) +#define CSR_RXPMA_CORE_PHY1_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2208) +#define CSR_RXPMA_CORE_PHY1_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x220c) +#define CSR_RXPMA_CORE_PHY1_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2210) +#define CSR_RXPMA_CORE_PHY1_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2214) +#define CSR_RXPMA_CORE_PHY1_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2218) +#define CSR_RXPMA_CORE_PHY1_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x221c) +#define CSR_RXPMA_CORE_PHY1_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2220) +#define CSR_RXPMA_CORE_PHY1_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2224) +#define CSR_RXPMA_CORE_PHY1_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2228) +#define CSR_RXPMA_CORE_PHY1__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2280) +#define CSR_RXPMA_CORE_PHY1__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2300) +#define CSR_RXPMA_CORE_PHY1__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2380) +#define CSR_RXPMA_CORE_PHY2_CONTROL (CSR_RXPMA_CORE_BASE + 0x2400) +#define CSR_RXPMA_CORE_PHY2_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2404) +#define CSR_RXPMA_CORE_PHY2_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2408) +#define CSR_RXPMA_CORE_PHY2_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x240c) +#define CSR_RXPMA_CORE_PHY2_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2410) +#define CSR_RXPMA_CORE_PHY2_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2414) +#define CSR_RXPMA_CORE_PHY2_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2418) +#define CSR_RXPMA_CORE_PHY2_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x241c) +#define CSR_RXPMA_CORE_PHY2_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2420) +#define CSR_RXPMA_CORE_PHY2_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2424) +#define CSR_RXPMA_CORE_PHY2_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2428) +#define CSR_RXPMA_CORE_PHY2__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2480) +#define CSR_RXPMA_CORE_PHY2__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2500) +#define CSR_RXPMA_CORE_PHY2__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2580) +#define CSR_RXPMA_CORE_PHY3_CONTROL (CSR_RXPMA_CORE_BASE + 0x2600) +#define CSR_RXPMA_CORE_PHY3_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2604) +#define CSR_RXPMA_CORE_PHY3_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2608) +#define CSR_RXPMA_CORE_PHY3_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x260c) +#define CSR_RXPMA_CORE_PHY3_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2610) +#define CSR_RXPMA_CORE_PHY3_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2614) +#define CSR_RXPMA_CORE_PHY3_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2618) +#define CSR_RXPMA_CORE_PHY3_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x261c) +#define CSR_RXPMA_CORE_PHY3_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2620) +#define CSR_RXPMA_CORE_PHY3_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2624) +#define CSR_RXPMA_CORE_PHY3_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2628) +#define CSR_RXPMA_CORE_PHY3__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2680) +#define CSR_RXPMA_CORE_PHY3__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2700) +#define CSR_RXPMA_CORE_PHY3__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2780) +#define CSR_RXPMA_CORE_PHY4_CONTROL (CSR_RXPMA_CORE_BASE + 0x2800) +#define CSR_RXPMA_CORE_PHY4_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2804) +#define CSR_RXPMA_CORE_PHY4_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2808) +#define CSR_RXPMA_CORE_PHY4_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x280c) +#define CSR_RXPMA_CORE_PHY4_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2810) +#define CSR_RXPMA_CORE_PHY4_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2814) +#define CSR_RXPMA_CORE_PHY4_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2818) +#define CSR_RXPMA_CORE_PHY4_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x281c) +#define CSR_RXPMA_CORE_PHY4_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2820) +#define CSR_RXPMA_CORE_PHY4_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2824) +#define CSR_RXPMA_CORE_PHY4_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2828) +#define CSR_RXPMA_CORE_PHY4__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2880) +#define CSR_RXPMA_CORE_PHY4__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2900) +#define CSR_RXPMA_CORE_PHY4__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2980) +#define CSR_RXPMA_CORE_PHY5_CONTROL (CSR_RXPMA_CORE_BASE + 0x2a00) +#define CSR_RXPMA_CORE_PHY5_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2a04) +#define CSR_RXPMA_CORE_PHY5_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2a08) +#define CSR_RXPMA_CORE_PHY5_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x2a0c) +#define CSR_RXPMA_CORE_PHY5_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2a10) +#define CSR_RXPMA_CORE_PHY5_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2a14) +#define CSR_RXPMA_CORE_PHY5_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2a18) +#define CSR_RXPMA_CORE_PHY5_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2a1c) +#define CSR_RXPMA_CORE_PHY5_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2a20) +#define CSR_RXPMA_CORE_PHY5_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2a24) +#define CSR_RXPMA_CORE_PHY5_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2a28) +#define CSR_RXPMA_CORE_PHY5__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2a80) +#define CSR_RXPMA_CORE_PHY5__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2b00) +#define CSR_RXPMA_CORE_PHY5__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2b80) +#define CSR_RXPMA_CORE_PHY6_CONTROL (CSR_RXPMA_CORE_BASE + 0x2c00) +#define CSR_RXPMA_CORE_PHY6_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2c04) +#define CSR_RXPMA_CORE_PHY6_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2c08) +#define CSR_RXPMA_CORE_PHY6_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x2c0c) +#define CSR_RXPMA_CORE_PHY6_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2c10) +#define CSR_RXPMA_CORE_PHY6_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2c14) +#define CSR_RXPMA_CORE_PHY6_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2c18) +#define CSR_RXPMA_CORE_PHY6_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2c1c) +#define CSR_RXPMA_CORE_PHY6_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2c20) +#define CSR_RXPMA_CORE_PHY6_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2c24) +#define CSR_RXPMA_CORE_PHY6_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2c28) +#define CSR_RXPMA_CORE_PHY6__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2c80) +#define CSR_RXPMA_CORE_PHY6__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2d00) +#define CSR_RXPMA_CORE_PHY6__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2d80) +#define CSR_RXPMA_CORE_PHY7_CONTROL (CSR_RXPMA_CORE_BASE + 0x2e00) +#define CSR_RXPMA_CORE_PHY7_VL_CTRL_CFG (CSR_RXPMA_CORE_BASE + 0x2e04) +#define CSR_RXPMA_CORE_PHY7_AMWIN_ERR_CFG (CSR_RXPMA_CORE_BASE + 0x2e08) +#define CSR_RXPMA_CORE_PHY7_RX_1588_CFG (CSR_RXPMA_CORE_BASE + 0x2e0c) +#define CSR_RXPMA_CORE_PHY7_RX_TS_DLY (CSR_RXPMA_CORE_BASE + 0x2e10) +#define CSR_RXPMA_CORE_PHY7_RX_1588_SAMPLE_STATUS (CSR_RXPMA_CORE_BASE + 0x2e14) +#define CSR_RXPMA_CORE_PHY7_RX_TS_LINKUP_DLY (CSR_RXPMA_CORE_BASE + 0x2e18) +#define CSR_RXPMA_CORE_PHY7_DBG_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2e1c) +#define CSR_RXPMA_CORE_PHY7_DBG_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2e20) +#define CSR_RXPMA_CORE_PHY7_DBG_MUTIL_LANE_INFO (CSR_RXPMA_CORE_BASE + 0x2e24) +#define CSR_RXPMA_CORE_PHY7_ISO_STATUS (CSR_RXPMA_CORE_BASE + 0x2e28) +#define CSR_RXPMA_CORE_PHY7__LANE_CURR_STATUS (CSR_RXPMA_CORE_BASE + 0x2e80) +#define CSR_RXPMA_CORE_PHY7__LANE_HIS_STATUS (CSR_RXPMA_CORE_BASE + 0x2f00) +#define CSR_RXPMA_CORE_PHY7__LANE_SKEW_FIFO_INFO (CSR_RXPMA_CORE_BASE + 0x2f80) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rxpma_lane_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rxpma_lane_offset.h new file mode 100644 index 000000000..e38793913 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_rxpma_lane_offset.h @@ -0,0 +1,44 @@ +#ifndef MAC_REG_RXPMA_LANE_H +#define MAC_REG_RXPMA_LANE_H + +/* Base address of Module's Register */ +#define CSR_RXPMA_LANE_BASE (0x18000) + +#define CSR_RXPMA_LANE_INT_STATUS (CSR_RXPMA_LANE_BASE + 0x0) +#define CSR_RXPMA_LANE_INT_ENABLE (CSR_RXPMA_LANE_BASE + 0x4) +#define CSR_RXPMA_LANE_INT_SET (CSR_RXPMA_LANE_BASE + 0x8) +#define CSR_RXPMA_LANE_OVF_INT_STATUS (CSR_RXPMA_LANE_BASE + 0xc) +#define CSR_RXPMA_LANE_OVF_INT_ENABLE (CSR_RXPMA_LANE_BASE + 0x10) +#define CSR_RXPMA_LANE_OVF_INT_SET (CSR_RXPMA_LANE_BASE + 0x14) +#define CSR_RXPMA_LANE_UDF_INT_STATUS (CSR_RXPMA_LANE_BASE + 0x18) +#define CSR_RXPMA_LANE_UDF_INT_ENABLE (CSR_RXPMA_LANE_BASE + 0x1c) +#define CSR_RXPMA_LANE_UDF_INT_SET (CSR_RXPMA_LANE_BASE + 0x20) +#define CSR_RXPMA_LANE_IERR_U_INFO (CSR_RXPMA_LANE_BASE + 0x400) +#define CSR_RXPMA_LANE_IERR_U_CNT (CSR_RXPMA_LANE_BASE + 0x404) +#define CSR_RXPMA_LANE_PHY_RSTN (CSR_RXPMA_LANE_BASE + 0x420) +#define CSR_RXPMA_LANE_AFIFO_RSTN (CSR_RXPMA_LANE_BASE + 0x440) +#define CSR_RXPMA_LANE_LANE_RSTN (CSR_RXPMA_LANE_BASE + 0x444) +#define CSR_RXPMA_LANE_PHY_SELF_RESET_EN (CSR_RXPMA_LANE_BASE + 0x460) +#define CSR_RXPMA_LANE_PHY_ENABLE (CSR_RXPMA_LANE_BASE + 0x480) +#define CSR_RXPMA_LANE_PHY_CONTROL (CSR_RXPMA_LANE_BASE + 0x4a0) +#define CSR_RXPMA_LANE_PHY_CLK_SKEW_CONTROL (CSR_RXPMA_LANE_BASE + 0x4c0) +#define CSR_RXPMA_LANE_PHY_1588_CFG (CSR_RXPMA_LANE_BASE + 0x4e0) +#define CSR_RXPMA_LANE_DBG_IERR_INSERT (CSR_RXPMA_LANE_BASE + 0x500) +#define CSR_RXPMA_LANE_LANE_CLOCK_BIST_START (CSR_RXPMA_LANE_BASE + 0x520) +#define CSR_RXPMA_LANE_LANE_CLOCK_BIST_TIME (CSR_RXPMA_LANE_BASE + 0x540) +#define CSR_RXPMA_LANE_AFIFO__CTRL (CSR_RXPMA_LANE_BASE + 0x560) +#define CSR_RXPMA_LANE_LANE_CLOCK_BIST_DONE (CSR_RXPMA_LANE_BASE + 0x580) +#define CSR_RXPMA_LANE_LANE_CLOCK_BIST_VALUE (CSR_RXPMA_LANE_BASE + 0x5a0) +#define CSR_RXPMA_LANE_AFIFO__CURR_STATUS (CSR_RXPMA_LANE_BASE + 0x5c0) +#define CSR_RXPMA_LANE_AFIFO__STATUS (CSR_RXPMA_LANE_BASE + 0x5e0) +#define CSR_RXPMA_LANE__SIGNAL_HIS_STATUS (CSR_RXPMA_LANE_BASE + 0x600) +#define CSR_RXPMA_LANE__SIGNAL_STATUS (CSR_RXPMA_LANE_BASE + 0x620) +#define CSR_RXPMA_LANE_PHY_SKEW_CURR_STATUS (CSR_RXPMA_LANE_BASE + 0x640) +#define CSR_RXPMA_LANE_PHY_SKEW_HIS_STATUS (CSR_RXPMA_LANE_BASE + 0x660) +#define CSR_RXPMA_LANE_DBG__CTRL (CSR_RXPMA_LANE_BASE + 0x680) +#define CSR_RXPMA_LANE_DBG__CURR_STATUS (CSR_RXPMA_LANE_BASE + 0x6a0) +#define CSR_RXPMA_LANE_DBG__HIS_STATUS (CSR_RXPMA_LANE_BASE + 0x6c0) +#define CSR_RXPMA_LANE_SPARE (CSR_RXPMA_LANE_BASE + 0x800) +#define CSR_RXPMA_LANE_SPARE_CNT (CSR_RXPMA_LANE_BASE + 0x804) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_brfec_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_brfec_offset.h new file mode 100644 index 000000000..b2bee9018 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_brfec_offset.h @@ -0,0 +1,62 @@ +#ifndef MAC_REG_TX_BRFEC_H +#define MAC_REG_TX_BRFEC_H + +/* Base address of Module's Register */ +#define CSR_TX_BRFEC_BASE (0x1e000) + +#define CSR_TX_BRFEC_INT_STATUS (CSR_TX_BRFEC_BASE + 0x0) +#define CSR_TX_BRFEC_INT_ENABLE (CSR_TX_BRFEC_BASE + 0x4) +#define CSR_TX_BRFEC_INT_SET (CSR_TX_BRFEC_BASE + 0x8) +#define CSR_TX_BRFEC_PHY_RSTN (CSR_TX_BRFEC_BASE + 0x20) +#define CSR_TX_BRFEC_PHY0_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x40) +#define CSR_TX_BRFEC_PHY0_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x44) +#define CSR_TX_BRFEC_PHY0_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x48) +#define CSR_TX_BRFEC_PHY0_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x4c) +#define CSR_TX_BRFEC_PHY0_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x50) +#define CSR_TX_BRFEC_PHY0_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x54) +#define CSR_TX_BRFEC_PHY1_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x60) +#define CSR_TX_BRFEC_PHY1_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x64) +#define CSR_TX_BRFEC_PHY1_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x68) +#define CSR_TX_BRFEC_PHY1_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x6c) +#define CSR_TX_BRFEC_PHY1_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x70) +#define CSR_TX_BRFEC_PHY1_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x74) +#define CSR_TX_BRFEC_PHY2_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x80) +#define CSR_TX_BRFEC_PHY2_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x84) +#define CSR_TX_BRFEC_PHY2_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x88) +#define CSR_TX_BRFEC_PHY2_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x8c) +#define CSR_TX_BRFEC_PHY2_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x90) +#define CSR_TX_BRFEC_PHY2_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x94) +#define CSR_TX_BRFEC_PHY3_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0xa0) +#define CSR_TX_BRFEC_PHY3_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0xa4) +#define CSR_TX_BRFEC_PHY3_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0xa8) +#define CSR_TX_BRFEC_PHY3_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0xac) +#define CSR_TX_BRFEC_PHY3_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0xb0) +#define CSR_TX_BRFEC_PHY3_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0xb4) +#define CSR_TX_BRFEC_PHY4_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0xc0) +#define CSR_TX_BRFEC_PHY4_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0xc4) +#define CSR_TX_BRFEC_PHY4_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0xc8) +#define CSR_TX_BRFEC_PHY4_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0xcc) +#define CSR_TX_BRFEC_PHY4_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0xd0) +#define CSR_TX_BRFEC_PHY4_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0xd4) +#define CSR_TX_BRFEC_PHY5_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0xe0) +#define CSR_TX_BRFEC_PHY5_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0xe4) +#define CSR_TX_BRFEC_PHY5_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0xe8) +#define CSR_TX_BRFEC_PHY5_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0xec) +#define CSR_TX_BRFEC_PHY5_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0xf0) +#define CSR_TX_BRFEC_PHY5_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0xf4) +#define CSR_TX_BRFEC_PHY6_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x100) +#define CSR_TX_BRFEC_PHY6_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x104) +#define CSR_TX_BRFEC_PHY6_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x108) +#define CSR_TX_BRFEC_PHY6_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x10c) +#define CSR_TX_BRFEC_PHY6_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x110) +#define CSR_TX_BRFEC_PHY6_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x114) +#define CSR_TX_BRFEC_PHY7_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x120) +#define CSR_TX_BRFEC_PHY7_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x124) +#define CSR_TX_BRFEC_PHY7_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x128) +#define CSR_TX_BRFEC_PHY7_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x12c) +#define CSR_TX_BRFEC_PHY7_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x130) +#define CSR_TX_BRFEC_PHY7_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x134) +#define CSR_TX_BRFEC_SPARE (CSR_TX_BRFEC_BASE + 0x140) +#define CSR_TX_BRFEC_SPARE_CNT (CSR_TX_BRFEC_BASE + 0x144) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_mac_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_mac_offset.h new file mode 100644 index 000000000..6a5a92748 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_mac_offset.h @@ -0,0 +1,109 @@ +#ifndef MAC_REG_TX_MAC_H +#define MAC_REG_TX_MAC_H + +/* Base address of Module's Register */ +#define CSR_TX_MAC_BASE (0x28000) + +#define CSR_TX_MAC_INT_STATUS (CSR_TX_MAC_BASE + 0x0) +#define CSR_TX_MAC_INT_ENABLE (CSR_TX_MAC_BASE + 0x4) +#define CSR_TX_MAC_INT_SET (CSR_TX_MAC_BASE + 0x8) +#define CSR_TX_MAC_QUE_OVF_INT_STATUS (CSR_TX_MAC_BASE + 0xc) +#define CSR_TX_MAC_QUE_OVF_INT_ENABLE (CSR_TX_MAC_BASE + 0x10) +#define CSR_TX_MAC_QUE_OVF_INT_SET (CSR_TX_MAC_BASE + 0x14) +#define CSR_TX_MAC_QUE_UDR_INT_STATUS (CSR_TX_MAC_BASE + 0x18) +#define CSR_TX_MAC_QUE_UDR_INT_ENABLE (CSR_TX_MAC_BASE + 0x1c) +#define CSR_TX_MAC_QUE_UDR_INT_SET (CSR_TX_MAC_BASE + 0x20) +#define CSR_TX_MAC_REF_1588_OVF_INT_STATUS (CSR_TX_MAC_BASE + 0x24) +#define CSR_TX_MAC_REF_1588_OVF_INT_ENABLE (CSR_TX_MAC_BASE + 0x28) +#define CSR_TX_MAC_REF_1588_OVF_INT_SET (CSR_TX_MAC_BASE + 0x2c) +#define CSR_TX_MAC_MEM_INIT_START (CSR_TX_MAC_BASE + 0x1000) +#define CSR_TX_MAC_MEM_INIT_STATUS (CSR_TX_MAC_BASE + 0x1004) +#define CSR_TX_MAC_TX_IDLE_DEL_GAP (CSR_TX_MAC_BASE + 0x1008) +#define CSR_TX_MAC_EOP_TIMEOUT_CYC (CSR_TX_MAC_BASE + 0x100c) +#define CSR_TX_MAC_GLB_LOW_LAT_CFG (CSR_TX_MAC_BASE + 0x1010) +#define CSR_TX_MAC_AM_ADJ_CFG (CSR_TX_MAC_BASE + 0x1014) +#define CSR_TX_MAC_AM_ADJ_START (CSR_TX_MAC_BASE + 0x1018) +#define CSR_TX_MAC_AM_ADJ_DONE (CSR_TX_MAC_BASE + 0x101c) +#define CSR_TX_MAC_AM_PERIOD (CSR_TX_MAC_BASE + 0x1020) +#define CSR_TX_MAC_AM_ADJ_COMP (CSR_TX_MAC_BASE + 0x1024) +#define CSR_TX_MAC_AM_ADJ_RSTN_WIDTH (CSR_TX_MAC_BASE + 0x1028) +#define CSR_TX_MAC_AM_ADJ_RTC_TS (CSR_TX_MAC_BASE + 0x102c) +#define CSR_TX_MAC_GLB_TDM_SCH_CFG (CSR_TX_MAC_BASE + 0x1030) +#define CSR_TX_MAC_CALEN_DEPTH (CSR_TX_MAC_BASE + 0x1034) +#define CSR_TX_MAC_CALEN_SEL (CSR_TX_MAC_BASE + 0x1038) +#define CSR_TX_MAC_CALENDAR_TABLE (CSR_TX_MAC_BASE + 0x1200) +#define CSR_TX_MAC_PHY_RSTN_LOGIC (CSR_TX_MAC_BASE + 0x1400) +#define CSR_TX_MAC_PHY_1588_CFG (CSR_TX_MAC_BASE + 0x1420) +#define CSR_TX_MAC_PHY_AMWINSIZE (CSR_TX_MAC_BASE + 0x1440) +#define CSR_TX_MAC_PHY_TDM_SCH_CFG (CSR_TX_MAC_BASE + 0x1460) +#define CSR_TX_MAC_PHY_TDM_TOKEN (CSR_TX_MAC_BASE + 0x1480) +#define CSR_TX_MAC_PORT_RSTN_LOGIC (CSR_TX_MAC_BASE + 0x14a0) +#define CSR_TX_MAC_PORT_BUF_ADDR_MAP (CSR_TX_MAC_BASE + 0x14c0) +#define CSR_TX_MAC_PORT_XOFF_TH (CSR_TX_MAC_BASE + 0x14e0) +#define CSR_TX_MAC_PORT_CTRL_TH (CSR_TX_MAC_BASE + 0x1500) +#define CSR_TX_MAC_PORT_ENABLE (CSR_TX_MAC_BASE + 0x1520) +#define CSR_TX_MAC_PORT_CONTROL (CSR_TX_MAC_BASE + 0x1540) +#define CSR_TX_MAC_PORT_CONTROL1 (CSR_TX_MAC_BASE + 0x1560) +#define CSR_TX_MAC_PORT_PAUSE_CTRL (CSR_TX_MAC_BASE + 0x1580) +#define CSR_TX_MAC_PORT_PAUSE_CTRL1 (CSR_TX_MAC_BASE + 0x15a0) +#define CSR_TX_MAC_PORT_PAUSE_LOCAL_MAC (CSR_TX_MAC_BASE + 0x15c0) +#define CSR_TX_MAC_PORT_PAUSE_PEER_MAC (CSR_TX_MAC_BASE + 0x1600) +#define CSR_TX_MAC_PORT_1588_CTRL (CSR_TX_MAC_BASE + 0x1640) +#define CSR_TX_MAC_PORT_1588_PORT_DELAY (CSR_TX_MAC_BASE + 0x1660) +#define CSR_TX_MAC_PORT_1588_ASYM_DELAY (CSR_TX_MAC_BASE + 0x1680) +#define CSR_TX_MAC_PORT_TEST_CTRL (CSR_TX_MAC_BASE + 0x16a0) +#define CSR_TX_MAC_PORT_TEST_CTRL1 (CSR_TX_MAC_BASE + 0x16c0) +#define CSR_TX_MAC_PORT_TEST_BURST_DONE (CSR_TX_MAC_BASE + 0x16e0) +#define CSR_TX_MAC_PORT_DIAG_DROP_OCTET_CNT (CSR_TX_MAC_BASE + 0x1700) +#define CSR_TX_MAC_PORT_DIAG_RUNT_PKT_CNT (CSR_TX_MAC_BASE + 0x1720) +#define CSR_TX_MAC_PORT_DIAG_LFRF_TERM_PKT_CNT (CSR_TX_MAC_BASE + 0x1740) +#define CSR_TX_MAC_PORT_DIAG_HIS_STATUS (CSR_TX_MAC_BASE + 0x1760) +#define CSR_TX_MAC_PHY_DIAG_HIS_STATUS (CSR_TX_MAC_BASE + 0x1780) +#define CSR_TX_MAC_PHY_DIAG_1588_REF_GAP_JIT_MAX (CSR_TX_MAC_BASE + 0x17a0) +#define CSR_TX_MAC_PHY_DIAG_1588_REF_GAP_JIT_CLR (CSR_TX_MAC_BASE + 0x17c0) +#define CSR_TX_MAC_PHY_DIAG_1588_REF_GAP_JIT_TH (CSR_TX_MAC_BASE + 0x17e0) +#define CSR_TX_MAC_DBG_IERR_INSERT (CSR_TX_MAC_BASE + 0x17e4) +#define CSR_TX_MAC_IERR_U_INFO (CSR_TX_MAC_BASE + 0x17e8) +#define CSR_TX_MAC_IERR_C_INFO (CSR_TX_MAC_BASE + 0x17ec) +#define CSR_TX_MAC_IERR_U_CNT (CSR_TX_MAC_BASE + 0x17f0) +#define CSR_TX_MAC_IERR_C_CNT (CSR_TX_MAC_BASE + 0x17f4) +#define CSR_TX_MAC_DIAG_TX_QUE_EMPTY (CSR_TX_MAC_BASE + 0x17f8) +#define CSR_TX_MAC_DIAG_LP_ID (CSR_TX_MAC_BASE + 0x17fc) +#define CSR_TX_MAC_DIAG_FSM_INFO (CSR_TX_MAC_BASE + 0x1800) +#define CSR_TX_MAC_DIAG_CURR_STATUS (CSR_TX_MAC_BASE + 0x1804) +#define CSR_TX_MAC_DIAG_HIS_STATUS (CSR_TX_MAC_BASE + 0x1808) +#define CSR_TX_MAC_DIAG_APP_TX_RATE_JITTER_CMD (CSR_TX_MAC_BASE + 0x180c) +#define CSR_TX_MAC_DIAG_APP_TX_RATE_JITTER (CSR_TX_MAC_BASE + 0x1810) +#define CSR_TX_MAC_DIAG_PAYLOAD_RATE_CFG (CSR_TX_MAC_BASE + 0x1818) +#define CSR_TX_MAC_DIAG_PAYLOAD_RATE_WIN (CSR_TX_MAC_BASE + 0x1820) +#define CSR_TX_MAC_DIAG_PAYLOAD_RATE_PKT (CSR_TX_MAC_BASE + 0x1828) +#define CSR_TX_MAC_DIAG_PAYLOAD_RATE_BYTE (CSR_TX_MAC_BASE + 0x1830) +#define CSR_TX_MAC_SPARE (CSR_TX_MAC_BASE + 0x1840) +#define CSR_TX_MAC_SPARE_CNT (CSR_TX_MAC_BASE + 0x1844) +#define CSR_TX_MAC_HEE_MSG_RSVD_HEAD (CSR_TX_MAC_BASE + 0x2000) +#define CSR_TX_MAC_HEE_MSG_SFD (CSR_TX_MAC_BASE + 0x2010) +#define CSR_TX_MAC_HEE_VERIFY_CFG (CSR_TX_MAC_BASE + 0x2014) +#define CSR_TX_MAC_HEE_RSP_CFG (CSR_TX_MAC_BASE + 0x2018) +#define CSR_TX_MAC_HEE_SDSU_CFG (CSR_TX_MAC_BASE + 0x201c) +#define CSR_TX_MAC_PHY0_HEE_CFG (CSR_TX_MAC_BASE + 0x2020) +#define CSR_TX_MAC_PHY2_HEE_CFG (CSR_TX_MAC_BASE + 0x2024) +#define CSR_TX_MAC_PHY0_HEE_OP_START (CSR_TX_MAC_BASE + 0x2028) +#define CSR_TX_MAC_PHY2_HEE_OP_START (CSR_TX_MAC_BASE + 0x202c) +#define CSR_TX_MAC_PHY0_HEE_OP_CMD (CSR_TX_MAC_BASE + 0x2030) +#define CSR_TX_MAC_PHY2_HEE_OP_CMD (CSR_TX_MAC_BASE + 0x2034) +#define CSR_TX_MAC_PHY0_HEE_OP_STATUS (CSR_TX_MAC_BASE + 0x2038) +#define CSR_TX_MAC_PHY2_HEE_OP_STATUS (CSR_TX_MAC_BASE + 0x203c) +#define CSR_TX_MAC_PHY0_DBG_HEE_RSTN (CSR_TX_MAC_BASE + 0x2040) +#define CSR_TX_MAC_PHY2_DBG_HEE_RSTN (CSR_TX_MAC_BASE + 0x2044) +#define CSR_TX_MAC_PHY0_DIAG_HEE_HIS_STATUS (CSR_TX_MAC_BASE + 0x2048) +#define CSR_TX_MAC_PHY2_DIAG_HEE_HIS_STATUS (CSR_TX_MAC_BASE + 0x204c) +#define CSR_TX_MAC_PHY0_DIAG_HEE_V_PKT_CNT (CSR_TX_MAC_BASE + 0x2050) +#define CSR_TX_MAC_PHY2_DIAG_HEE_V_PKT_CNT (CSR_TX_MAC_BASE + 0x2054) +#define CSR_TX_MAC_PHY0_DIAG_HEE_R_PKT_CNT (CSR_TX_MAC_BASE + 0x2058) +#define CSR_TX_MAC_PHY2_DIAG_HEE_R_PKT_CNT (CSR_TX_MAC_BASE + 0x205c) +#define CSR_TX_MAC_PHY0_DIAG_HEE_SD_PKT_CNT (CSR_TX_MAC_BASE + 0x2060) +#define CSR_TX_MAC_PHY2_DIAG_HEE_SD_PKT_CNT (CSR_TX_MAC_BASE + 0x2064) +#define CSR_TX_MAC_PHY0_DIAG_HEE_SU_PKT_CNT (CSR_TX_MAC_BASE + 0x2068) +#define CSR_TX_MAC_PHY2_DIAG_HEE_SU_PKT_CNT (CSR_TX_MAC_BASE + 0x206c) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_pcs_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_pcs_offset.h new file mode 100644 index 000000000..62c696f1f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_pcs_offset.h @@ -0,0 +1,169 @@ +#ifndef MAC_REG_TX_PCS_H +#define MAC_REG_TX_PCS_H + +/* Base address of Module's Register */ +#define CSR_TX_PCS_BASE (0x24000) + +#define CSR_TX_PCS_INT_STATUS (CSR_TX_PCS_BASE + 0x0) +#define CSR_TX_PCS_INT_ENABLE (CSR_TX_PCS_BASE + 0x4) +#define CSR_TX_PCS_INT_SET (CSR_TX_PCS_BASE + 0x8) +#define CSR_TX_PCS_IERR_U_INFO (CSR_TX_PCS_BASE + 0x80) +#define CSR_TX_PCS_IERR_C_INFO (CSR_TX_PCS_BASE + 0x84) +#define CSR_TX_PCS_IERR_U_CNT (CSR_TX_PCS_BASE + 0x88) +#define CSR_TX_PCS_IERR_C_CNT (CSR_TX_PCS_BASE + 0x8c) +#define CSR_TX_PCS_PHY_RSTN (CSR_TX_PCS_BASE + 0xa0) +#define CSR_TX_PCS_PHY_AMWINSIZE (CSR_TX_PCS_BASE + 0xc0) +#define CSR_TX_PCS_DBG_IERR_INSERT (CSR_TX_PCS_BASE + 0xe0) +#define CSR_TX_PCS_PHY0_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x100) +#define CSR_TX_PCS_PHY0_TEST_CONTROL (CSR_TX_PCS_BASE + 0x104) +#define CSR_TX_PCS_PHY0_BASER_CONTROL (CSR_TX_PCS_BASE + 0x108) +#define CSR_TX_PCS_PHY0_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x10c) +#define CSR_TX_PCS_PHY0_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x110) +#define CSR_TX_PCS_PHY0_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x114) +#define CSR_TX_PCS_PHY0_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x118) +#define CSR_TX_PCS_PHY0_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x11c) +#define CSR_TX_PCS_PHY0_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x120) +#define CSR_TX_PCS_PHY0_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x124) +#define CSR_TX_PCS_PHY0_AM0_800G_L0 (CSR_TX_PCS_BASE + 0x200) +#define CSR_TX_PCS_PHY0_AM0_800G_L1 (CSR_TX_PCS_BASE + 0x204) +#define CSR_TX_PCS_PHY0_AM0_800G_H0 (CSR_TX_PCS_BASE + 0x208) +#define CSR_TX_PCS_PHY0_AM0_800G_H1 (CSR_TX_PCS_BASE + 0x20c) +#define CSR_TX_PCS_PHY0_AM1_800G_L0 (CSR_TX_PCS_BASE + 0x210) +#define CSR_TX_PCS_PHY0_AM1_800G_L1 (CSR_TX_PCS_BASE + 0x214) +#define CSR_TX_PCS_PHY0_AM1_800G_H0 (CSR_TX_PCS_BASE + 0x218) +#define CSR_TX_PCS_PHY0_AM1_800G_H1 (CSR_TX_PCS_BASE + 0x21c) +#define CSR_TX_PCS_PHY0_AM2_800G_L0 (CSR_TX_PCS_BASE + 0x220) +#define CSR_TX_PCS_PHY0_AM2_800G_L1 (CSR_TX_PCS_BASE + 0x224) +#define CSR_TX_PCS_PHY0_AM2_800G_H0 (CSR_TX_PCS_BASE + 0x228) +#define CSR_TX_PCS_PHY0_AM2_800G_H1 (CSR_TX_PCS_BASE + 0x22c) +#define CSR_TX_PCS_PHY0_AM3_800G_L0 (CSR_TX_PCS_BASE + 0x230) +#define CSR_TX_PCS_PHY0_AM3_800G_L1 (CSR_TX_PCS_BASE + 0x234) +#define CSR_TX_PCS_PHY0_AM3_800G_H0 (CSR_TX_PCS_BASE + 0x238) +#define CSR_TX_PCS_PHY0_AM3_800G_H1 (CSR_TX_PCS_BASE + 0x23c) +#define CSR_TX_PCS_PHY0_AM4_800G_L0 (CSR_TX_PCS_BASE + 0x240) +#define CSR_TX_PCS_PHY0_AM4_800G_L1 (CSR_TX_PCS_BASE + 0x244) +#define CSR_TX_PCS_PHY0_AM4_800G_H0 (CSR_TX_PCS_BASE + 0x248) +#define CSR_TX_PCS_PHY0_AM4_800G_H1 (CSR_TX_PCS_BASE + 0x24c) +#define CSR_TX_PCS_PHY0_AM5_800G_L0 (CSR_TX_PCS_BASE + 0x250) +#define CSR_TX_PCS_PHY0_AM5_800G_L1 (CSR_TX_PCS_BASE + 0x254) +#define CSR_TX_PCS_PHY0_AM5_800G_H0 (CSR_TX_PCS_BASE + 0x258) +#define CSR_TX_PCS_PHY0_AM5_800G_H1 (CSR_TX_PCS_BASE + 0x25c) +#define CSR_TX_PCS_PHY0_AM6_800G_L0 (CSR_TX_PCS_BASE + 0x260) +#define CSR_TX_PCS_PHY0_AM6_800G_L1 (CSR_TX_PCS_BASE + 0x264) +#define CSR_TX_PCS_PHY0_AM6_800G_H0 (CSR_TX_PCS_BASE + 0x268) +#define CSR_TX_PCS_PHY0_AM6_800G_H1 (CSR_TX_PCS_BASE + 0x26c) +#define CSR_TX_PCS_PHY0_AM7_800G_L0 (CSR_TX_PCS_BASE + 0x270) +#define CSR_TX_PCS_PHY0_AM7_800G_L1 (CSR_TX_PCS_BASE + 0x274) +#define CSR_TX_PCS_PHY0_AM7_800G_H0 (CSR_TX_PCS_BASE + 0x278) +#define CSR_TX_PCS_PHY0_AM7_800G_H1 (CSR_TX_PCS_BASE + 0x27c) +#define CSR_TX_PCS_PHY0_AM8_800G_L0 (CSR_TX_PCS_BASE + 0x280) +#define CSR_TX_PCS_PHY0_AM8_800G_L1 (CSR_TX_PCS_BASE + 0x284) +#define CSR_TX_PCS_PHY0_AM8_800G_H0 (CSR_TX_PCS_BASE + 0x288) +#define CSR_TX_PCS_PHY0_AM8_800G_H1 (CSR_TX_PCS_BASE + 0x28c) +#define CSR_TX_PCS_PHY0_AM9_800G_L0 (CSR_TX_PCS_BASE + 0x290) +#define CSR_TX_PCS_PHY0_AM9_800G_L1 (CSR_TX_PCS_BASE + 0x294) +#define CSR_TX_PCS_PHY0_AM9_800G_H0 (CSR_TX_PCS_BASE + 0x298) +#define CSR_TX_PCS_PHY0_AM9_800G_H1 (CSR_TX_PCS_BASE + 0x29c) +#define CSR_TX_PCS_PHY0_AM10_800G_L0 (CSR_TX_PCS_BASE + 0x2a0) +#define CSR_TX_PCS_PHY0_AM10_800G_L1 (CSR_TX_PCS_BASE + 0x2a4) +#define CSR_TX_PCS_PHY0_AM10_800G_H0 (CSR_TX_PCS_BASE + 0x2a8) +#define CSR_TX_PCS_PHY0_AM10_800G_H1 (CSR_TX_PCS_BASE + 0x2ac) +#define CSR_TX_PCS_PHY0_AM11_800G_L0 (CSR_TX_PCS_BASE + 0x2b0) +#define CSR_TX_PCS_PHY0_AM11_800G_L1 (CSR_TX_PCS_BASE + 0x2b4) +#define CSR_TX_PCS_PHY0_AM11_800G_H0 (CSR_TX_PCS_BASE + 0x2b8) +#define CSR_TX_PCS_PHY0_AM11_800G_H1 (CSR_TX_PCS_BASE + 0x2bc) +#define CSR_TX_PCS_PHY0_AM12_800G_L0 (CSR_TX_PCS_BASE + 0x2c0) +#define CSR_TX_PCS_PHY0_AM12_800G_L1 (CSR_TX_PCS_BASE + 0x2c4) +#define CSR_TX_PCS_PHY0_AM12_800G_H0 (CSR_TX_PCS_BASE + 0x2c8) +#define CSR_TX_PCS_PHY0_AM12_800G_H1 (CSR_TX_PCS_BASE + 0x2cc) +#define CSR_TX_PCS_PHY0_AM13_800G_L0 (CSR_TX_PCS_BASE + 0x2d0) +#define CSR_TX_PCS_PHY0_AM13_800G_L1 (CSR_TX_PCS_BASE + 0x2d4) +#define CSR_TX_PCS_PHY0_AM13_800G_H0 (CSR_TX_PCS_BASE + 0x2d8) +#define CSR_TX_PCS_PHY0_AM13_800G_H1 (CSR_TX_PCS_BASE + 0x2dc) +#define CSR_TX_PCS_PHY0_AM14_800G_L0 (CSR_TX_PCS_BASE + 0x2e0) +#define CSR_TX_PCS_PHY0_AM14_800G_L1 (CSR_TX_PCS_BASE + 0x2e4) +#define CSR_TX_PCS_PHY0_AM14_800G_H0 (CSR_TX_PCS_BASE + 0x2e8) +#define CSR_TX_PCS_PHY0_AM14_800G_H1 (CSR_TX_PCS_BASE + 0x2ec) +#define CSR_TX_PCS_PHY0_AM15_800G_L0 (CSR_TX_PCS_BASE + 0x2f0) +#define CSR_TX_PCS_PHY0_AM15_800G_L1 (CSR_TX_PCS_BASE + 0x2f4) +#define CSR_TX_PCS_PHY0_AM15_800G_H0 (CSR_TX_PCS_BASE + 0x2f8) +#define CSR_TX_PCS_PHY0_AM15_800G_H1 (CSR_TX_PCS_BASE + 0x2fc) +#define CSR_TX_PCS_PHY0_BASER_800G_CONTROL (CSR_TX_PCS_BASE + 0x300) +#define CSR_TX_PCS_PHY0_TEST_800G_PRBS_MODE (CSR_TX_PCS_BASE + 0x304) +#define CSR_TX_PCS_PHY0_TEST_800G_PRBS_SEED (CSR_TX_PCS_BASE + 0x308) +#define CSR_TX_PCS_PHY0_DEGRAD_800G_SER_CFG (CSR_TX_PCS_BASE + 0x30c) +#define CSR_TX_PCS_PHY0_INV_BLOCK_CNT (CSR_TX_PCS_BASE + 0x310) +#define CSR_TX_PCS_PHY1_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x400) +#define CSR_TX_PCS_PHY1_TEST_CONTROL (CSR_TX_PCS_BASE + 0x404) +#define CSR_TX_PCS_PHY1_BASER_CONTROL (CSR_TX_PCS_BASE + 0x408) +#define CSR_TX_PCS_PHY1_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x40c) +#define CSR_TX_PCS_PHY1_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x410) +#define CSR_TX_PCS_PHY1_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x414) +#define CSR_TX_PCS_PHY1_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x418) +#define CSR_TX_PCS_PHY1_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x41c) +#define CSR_TX_PCS_PHY1_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x420) +#define CSR_TX_PCS_PHY1_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x424) +#define CSR_TX_PCS_PHY2_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x440) +#define CSR_TX_PCS_PHY2_TEST_CONTROL (CSR_TX_PCS_BASE + 0x444) +#define CSR_TX_PCS_PHY2_BASER_CONTROL (CSR_TX_PCS_BASE + 0x448) +#define CSR_TX_PCS_PHY2_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x44c) +#define CSR_TX_PCS_PHY2_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x450) +#define CSR_TX_PCS_PHY2_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x454) +#define CSR_TX_PCS_PHY2_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x458) +#define CSR_TX_PCS_PHY2_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x45c) +#define CSR_TX_PCS_PHY2_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x460) +#define CSR_TX_PCS_PHY2_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x464) +#define CSR_TX_PCS_PHY3_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x480) +#define CSR_TX_PCS_PHY3_TEST_CONTROL (CSR_TX_PCS_BASE + 0x484) +#define CSR_TX_PCS_PHY3_BASER_CONTROL (CSR_TX_PCS_BASE + 0x488) +#define CSR_TX_PCS_PHY3_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x48c) +#define CSR_TX_PCS_PHY3_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x490) +#define CSR_TX_PCS_PHY3_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x494) +#define CSR_TX_PCS_PHY3_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x498) +#define CSR_TX_PCS_PHY3_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x49c) +#define CSR_TX_PCS_PHY3_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x4a0) +#define CSR_TX_PCS_PHY3_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x4a4) +#define CSR_TX_PCS_PHY4_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x4c0) +#define CSR_TX_PCS_PHY4_TEST_CONTROL (CSR_TX_PCS_BASE + 0x4c4) +#define CSR_TX_PCS_PHY4_BASER_CONTROL (CSR_TX_PCS_BASE + 0x4c8) +#define CSR_TX_PCS_PHY4_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x4cc) +#define CSR_TX_PCS_PHY4_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x4d0) +#define CSR_TX_PCS_PHY4_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x4d4) +#define CSR_TX_PCS_PHY4_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x4d8) +#define CSR_TX_PCS_PHY4_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x4dc) +#define CSR_TX_PCS_PHY4_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x4e0) +#define CSR_TX_PCS_PHY4_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x4e4) +#define CSR_TX_PCS_PHY5_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x500) +#define CSR_TX_PCS_PHY5_TEST_CONTROL (CSR_TX_PCS_BASE + 0x504) +#define CSR_TX_PCS_PHY5_BASER_CONTROL (CSR_TX_PCS_BASE + 0x508) +#define CSR_TX_PCS_PHY5_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x50c) +#define CSR_TX_PCS_PHY5_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x510) +#define CSR_TX_PCS_PHY5_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x514) +#define CSR_TX_PCS_PHY5_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x518) +#define CSR_TX_PCS_PHY5_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x51c) +#define CSR_TX_PCS_PHY5_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x520) +#define CSR_TX_PCS_PHY5_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x524) +#define CSR_TX_PCS_PHY6_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x540) +#define CSR_TX_PCS_PHY6_TEST_CONTROL (CSR_TX_PCS_BASE + 0x544) +#define CSR_TX_PCS_PHY6_BASER_CONTROL (CSR_TX_PCS_BASE + 0x548) +#define CSR_TX_PCS_PHY6_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x54c) +#define CSR_TX_PCS_PHY6_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x550) +#define CSR_TX_PCS_PHY6_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x554) +#define CSR_TX_PCS_PHY6_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x558) +#define CSR_TX_PCS_PHY6_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x55c) +#define CSR_TX_PCS_PHY6_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x560) +#define CSR_TX_PCS_PHY6_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x564) +#define CSR_TX_PCS_PHY7_RSTN_CONTROL (CSR_TX_PCS_BASE + 0x580) +#define CSR_TX_PCS_PHY7_TEST_CONTROL (CSR_TX_PCS_BASE + 0x584) +#define CSR_TX_PCS_PHY7_BASER_CONTROL (CSR_TX_PCS_BASE + 0x588) +#define CSR_TX_PCS_PHY7_BASER_SEEDA_0 (CSR_TX_PCS_BASE + 0x58c) +#define CSR_TX_PCS_PHY7_BASER_SEEDA_1 (CSR_TX_PCS_BASE + 0x590) +#define CSR_TX_PCS_PHY7_BASER_SEEDB_0 (CSR_TX_PCS_BASE + 0x594) +#define CSR_TX_PCS_PHY7_BASER_SEEDB_1 (CSR_TX_PCS_BASE + 0x598) +#define CSR_TX_PCS_PHY7_AM_DET_CONTROL (CSR_TX_PCS_BASE + 0x59c) +#define CSR_TX_PCS_PHY7_AM_BIP_CONTROL (CSR_TX_PCS_BASE + 0x5a0) +#define CSR_TX_PCS_PHY7_DBG_HIS_STATUS (CSR_TX_PCS_BASE + 0x5a4) +#define CSR_TX_PCS_SPARE (CSR_TX_PCS_BASE + 0x5c0) +#define CSR_TX_PCS_SPARE_CNT (CSR_TX_PCS_BASE + 0x5c4) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_rsfec_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_rsfec_offset.h new file mode 100644 index 000000000..2e821d8ec --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_tx_rsfec_offset.h @@ -0,0 +1,75 @@ +#ifndef MAC_REG_TX_RSFEC_H +#define MAC_REG_TX_RSFEC_H + +/* Base address of Module's Register */ +#define CSR_TX_RSFEC_BASE (0x20000) + +#define CSR_TX_RSFEC_INT_STATUS (CSR_TX_RSFEC_BASE + 0x0) +#define CSR_TX_RSFEC_INT_ENABLE (CSR_TX_RSFEC_BASE + 0x4) +#define CSR_TX_RSFEC_INT_SET (CSR_TX_RSFEC_BASE + 0x8) +#define CSR_TX_RSFEC_PHY_ERR_STATUS (CSR_TX_RSFEC_BASE + 0x20) +#define CSR_TX_RSFEC_PHY_RSTN (CSR_TX_RSFEC_BASE + 0x200) +#define CSR_TX_RSFEC_PHY_CONTROL (CSR_TX_RSFEC_BASE + 0x220) +#define CSR_TX_RSFEC_PHY_AMWINSIZE (CSR_TX_RSFEC_BASE + 0x240) +#define CSR_TX_RSFEC_SCH_SEL (CSR_TX_RSFEC_BASE + 0x260) +#define CSR_TX_RSFEC_SCH_CFG (CSR_TX_RSFEC_BASE + 0x264) +#define CSR_TX_RSFEC_PRBS_MODE (CSR_TX_RSFEC_BASE + 0x268) +#define CSR_TX_RSFEC_PRBS_SEED (CSR_TX_RSFEC_BASE + 0x26c) +#define CSR_TX_RSFEC_RS272_PAD_CFG (CSR_TX_RSFEC_BASE + 0x270) +#define CSR_TX_RSFEC_AM0_L (CSR_TX_RSFEC_BASE + 0x274) +#define CSR_TX_RSFEC_AM0_H (CSR_TX_RSFEC_BASE + 0x278) +#define CSR_TX_RSFEC_AM1_L (CSR_TX_RSFEC_BASE + 0x27c) +#define CSR_TX_RSFEC_AM1_H (CSR_TX_RSFEC_BASE + 0x280) +#define CSR_TX_RSFEC_AM2_L (CSR_TX_RSFEC_BASE + 0x284) +#define CSR_TX_RSFEC_AM2_H (CSR_TX_RSFEC_BASE + 0x288) +#define CSR_TX_RSFEC_AM3_L (CSR_TX_RSFEC_BASE + 0x28c) +#define CSR_TX_RSFEC_AM3_H (CSR_TX_RSFEC_BASE + 0x290) +#define CSR_TX_RSFEC_AM4_L (CSR_TX_RSFEC_BASE + 0x294) +#define CSR_TX_RSFEC_AM4_H (CSR_TX_RSFEC_BASE + 0x298) +#define CSR_TX_RSFEC_AM5_L (CSR_TX_RSFEC_BASE + 0x29c) +#define CSR_TX_RSFEC_AM5_H (CSR_TX_RSFEC_BASE + 0x2a0) +#define CSR_TX_RSFEC_AM6_L (CSR_TX_RSFEC_BASE + 0x2a4) +#define CSR_TX_RSFEC_AM6_H (CSR_TX_RSFEC_BASE + 0x2a8) +#define CSR_TX_RSFEC_AM7_L (CSR_TX_RSFEC_BASE + 0x2ac) +#define CSR_TX_RSFEC_AM7_H (CSR_TX_RSFEC_BASE + 0x2b0) +#define CSR_TX_RSFEC_AM8_L (CSR_TX_RSFEC_BASE + 0x2b4) +#define CSR_TX_RSFEC_AM8_H (CSR_TX_RSFEC_BASE + 0x2b8) +#define CSR_TX_RSFEC_AM9_L (CSR_TX_RSFEC_BASE + 0x2bc) +#define CSR_TX_RSFEC_AM9_H (CSR_TX_RSFEC_BASE + 0x2c0) +#define CSR_TX_RSFEC_AM10_L (CSR_TX_RSFEC_BASE + 0x2c4) +#define CSR_TX_RSFEC_AM10_H (CSR_TX_RSFEC_BASE + 0x2c8) +#define CSR_TX_RSFEC_AM11_L (CSR_TX_RSFEC_BASE + 0x2cc) +#define CSR_TX_RSFEC_AM11_H (CSR_TX_RSFEC_BASE + 0x2d0) +#define CSR_TX_RSFEC_AM12_L (CSR_TX_RSFEC_BASE + 0x2d4) +#define CSR_TX_RSFEC_AM12_H (CSR_TX_RSFEC_BASE + 0x2d8) +#define CSR_TX_RSFEC_AM13_L (CSR_TX_RSFEC_BASE + 0x2dc) +#define CSR_TX_RSFEC_AM13_H (CSR_TX_RSFEC_BASE + 0x2e0) +#define CSR_TX_RSFEC_AM14_L (CSR_TX_RSFEC_BASE + 0x2e4) +#define CSR_TX_RSFEC_AM14_H (CSR_TX_RSFEC_BASE + 0x2e8) +#define CSR_TX_RSFEC_AM15_L (CSR_TX_RSFEC_BASE + 0x2ec) +#define CSR_TX_RSFEC_AM15_H (CSR_TX_RSFEC_BASE + 0x2f0) +#define CSR_TX_RSFEC_AM16_L (CSR_TX_RSFEC_BASE + 0x2f4) +#define CSR_TX_RSFEC_AM16_H (CSR_TX_RSFEC_BASE + 0x2f8) +#define CSR_TX_RSFEC_AM17_L (CSR_TX_RSFEC_BASE + 0x2fc) +#define CSR_TX_RSFEC_AM17_H (CSR_TX_RSFEC_BASE + 0x300) +#define CSR_TX_RSFEC_AM18_L (CSR_TX_RSFEC_BASE + 0x304) +#define CSR_TX_RSFEC_AM18_H (CSR_TX_RSFEC_BASE + 0x308) +#define CSR_TX_RSFEC_AM19_L (CSR_TX_RSFEC_BASE + 0x30c) +#define CSR_TX_RSFEC_AM19_H (CSR_TX_RSFEC_BASE + 0x310) +#define CSR_TX_RSFEC_DEGRAD_SER_CFG (CSR_TX_RSFEC_BASE + 0x314) +#define CSR_TX_RSFEC_BOND_LF_CFG (CSR_TX_RSFEC_BASE + 0x318) +#define CSR_TX_RSFEC_TX_ERR_INS_MOD_ (CSR_TX_RSFEC_BASE + 0x320) +#define CSR_TX_RSFEC_TX_ERR_INS_SYM_ (CSR_TX_RSFEC_BASE + 0x328) +#define CSR_TX_RSFEC_TX_ERR_INS_NUM_ (CSR_TX_RSFEC_BASE + 0x330) +#define CSR_TX_RSFEC_TX_ERR_INS_POS_ (CSR_TX_RSFEC_BASE + 0x338) +#define CSR_TX_RSFEC_TX_ERR_INS_CWN_ (CSR_TX_RSFEC_BASE + 0x340) +#define CSR_TX_RSFEC_TX_ERR_INS_SEED_ (CSR_TX_RSFEC_BASE + 0x348) +#define CSR_TX_RSFEC_TX_ERR_INS_GAP_ (CSR_TX_RSFEC_BASE + 0x350) +#define CSR_TX_RSFEC_TX_HI_ERR_INS_ (CSR_TX_RSFEC_BASE + 0x358) +#define CSR_TX_RSFEC_TX_ERR_CW_CNT_ (CSR_TX_RSFEC_BASE + 0x360) +#define CSR_TX_RSFEC_TX_INV_BLOCK_CNT (CSR_TX_RSFEC_BASE + 0x380) +#define CSR_TX_RSFEC_TS_CTRL_BUF_MAX (CSR_TX_RSFEC_BASE + 0x3a0) +#define CSR_TX_RSFEC_SPARE (CSR_TX_RSFEC_BASE + 0x400) +#define CSR_TX_RSFEC_SPARE_CNT (CSR_TX_RSFEC_BASE + 0x404) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_txpma_core_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_txpma_core_offset.h new file mode 100644 index 000000000..d69f3e028 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_txpma_core_offset.h @@ -0,0 +1,19 @@ +#ifndef MAC_REG_TXPMA_CORE_H +#define MAC_REG_TXPMA_CORE_H + +/* Base address of Module's Register */ +#define CSR_TXPMA_CORE_BASE (0x1c000) + +#define CSR_TXPMA_CORE_INT_STATUS (CSR_TXPMA_CORE_BASE + 0x0) +#define CSR_TXPMA_CORE_INT_ENABLE (CSR_TXPMA_CORE_BASE + 0x4) +#define CSR_TXPMA_CORE_INT_SET (CSR_TXPMA_CORE_BASE + 0x8) +#define CSR_TXPMA_CORE_OVF_INT_STATUS (CSR_TXPMA_CORE_BASE + 0xc) +#define CSR_TXPMA_CORE_OVF_INT_ENABLE (CSR_TXPMA_CORE_BASE + 0x10) +#define CSR_TXPMA_CORE_OVF_INT_SET (CSR_TXPMA_CORE_BASE + 0x14) +#define CSR_TXPMA_CORE_PHY_RSTN (CSR_TXPMA_CORE_BASE + 0x80) +#define CSR_TXPMA_CORE_PHY_MAPPING (CSR_TXPMA_CORE_BASE + 0xa0) +#define CSR_TXPMA_CORE_PHY_MODE (CSR_TXPMA_CORE_BASE + 0xc0) +#define CSR_TXPMA_CORE_SPARE (CSR_TXPMA_CORE_BASE + 0xe0) +#define CSR_TXPMA_CORE_SPARE_CNT (CSR_TXPMA_CORE_BASE + 0xe4) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_txpma_lane_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_txpma_lane_offset.h new file mode 100644 index 000000000..afe9d68f9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mac_reg_txpma_lane_offset.h @@ -0,0 +1,43 @@ +#ifndef MAC_REG_TXPMA_LANE_H +#define MAC_REG_TXPMA_LANE_H + +/* Base address of Module's Register */ +#define CSR_TXPMA_LANE_BASE (0x1a000) + +#define CSR_TXPMA_LANE_INT_STATUS (CSR_TXPMA_LANE_BASE + 0x0) +#define CSR_TXPMA_LANE_INT_ENABLE (CSR_TXPMA_LANE_BASE + 0x4) +#define CSR_TXPMA_LANE_INT_SET (CSR_TXPMA_LANE_BASE + 0x8) +#define CSR_TXPMA_LANE_OVF_INT_STATUS (CSR_TXPMA_LANE_BASE + 0xc) +#define CSR_TXPMA_LANE_OVF_INT_ENABLE (CSR_TXPMA_LANE_BASE + 0x10) +#define CSR_TXPMA_LANE_OVF_INT_SET (CSR_TXPMA_LANE_BASE + 0x14) +#define CSR_TXPMA_LANE_UDF_INT_STATUS (CSR_TXPMA_LANE_BASE + 0x18) +#define CSR_TXPMA_LANE_UDF_INT_ENABLE (CSR_TXPMA_LANE_BASE + 0x1c) +#define CSR_TXPMA_LANE_UDF_INT_SET (CSR_TXPMA_LANE_BASE + 0x20) +#define CSR_TXPMA_LANE_IERR_U_INFO (CSR_TXPMA_LANE_BASE + 0x400) +#define CSR_TXPMA_LANE_IERR_U_CNT (CSR_TXPMA_LANE_BASE + 0x404) +#define CSR_TXPMA_LANE_DBG_ECC_INSERT (CSR_TXPMA_LANE_BASE + 0x408) +#define CSR_TXPMA_LANE_LANE_RSTN (CSR_TXPMA_LANE_BASE + 0x40c) +#define CSR_TXPMA_LANE_AFIFO_RSTN (CSR_TXPMA_LANE_BASE + 0x410) +#define CSR_TXPMA_LANE_PHY_SELF_RESET_EN (CSR_TXPMA_LANE_BASE + 0x420) +#define CSR_TXPMA_LANE_PHY_LOW_LATENCY_EN (CSR_TXPMA_LANE_BASE + 0x440) +#define CSR_TXPMA_LANE_PHY_RD_ALIGN_EN (CSR_TXPMA_LANE_BASE + 0x460) +#define CSR_TXPMA_LANE_PHY_RD_DELAY_TH (CSR_TXPMA_LANE_BASE + 0x480) +#define CSR_TXPMA_LANE_PHY_START_TH (CSR_TXPMA_LANE_BASE + 0x4a0) +#define CSR_TXPMA_LANE_LANE_SMUX_MAPPING (CSR_TXPMA_LANE_BASE + 0x4c0) +#define CSR_TXPMA_LANE_PHY_CONTROL (CSR_TXPMA_LANE_BASE + 0x4e0) +#define CSR_TXPMA_LANE_PHY_1588_EN (CSR_TXPMA_LANE_BASE + 0x500) +#define CSR_TXPMA_LANE_LANE_PRBS_CFG (CSR_TXPMA_LANE_BASE + 0x520) +#define CSR_TXPMA_LANE_PRBS_SEED (CSR_TXPMA_LANE_BASE + 0x540) +#define CSR_TXPMA_LANE_LANE_CLOCK_BIST_START (CSR_TXPMA_LANE_BASE + 0x560) +#define CSR_TXPMA_LANE_LANE_CLOCK_BIST_TIME (CSR_TXPMA_LANE_BASE + 0x580) +#define CSR_TXPMA_LANE_LANE_SQU_CFG (CSR_TXPMA_LANE_BASE + 0x5a0) +#define CSR_TXPMA_LANE_LANE_FIFO_CURR_CNT (CSR_TXPMA_LANE_BASE + 0x5c0) +#define CSR_TXPMA_LANE_LANE_FIFO_CNT_MAX (CSR_TXPMA_LANE_BASE + 0x5e0) +#define CSR_TXPMA_LANE_LANE_FIFO_CNT_MIN (CSR_TXPMA_LANE_BASE + 0x600) +#define CSR_TXPMA_LANE_LANE_CLOCK_BIST_DONE (CSR_TXPMA_LANE_BASE + 0x620) +#define CSR_TXPMA_LANE_LANE_CLOCK_BIST_VALUE (CSR_TXPMA_LANE_BASE + 0x640) +#define CSR_TXPMA_LANE_PHY_SUB_PHY_CURR_STATUS (CSR_TXPMA_LANE_BASE + 0x660) +#define CSR_TXPMA_LANE_SPARE (CSR_TXPMA_LANE_BASE + 0x680) +#define CSR_TXPMA_LANE_SPARE_CNT (CSR_TXPMA_LANE_BASE + 0x684) + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mag_fc_sds_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mag_fc_sds_harden_reg_offset.h new file mode 100644 index 000000000..f74f37875 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mag_fc_sds_harden_reg_offset.h @@ -0,0 +1,60 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : mag_fc_sds_harden_reg_offset.h + * Project line : Platform And Key Technologies Development + * Department : + * Version : V100 + * Date : + * Description : The description of xxx project + * Others : Generated automatically by nManager V5.1 + * History : + */ + +#ifndef MAG_FC_SDS_HARDEN_REG_OFFSET_H +#define MAG_FC_SDS_HARDEN_REG_OFFSET_H + +/* MAG_IP_CFG_CSR Base address of Module's Register */ +#define CSR_MAG_IP_CFG_CSR_BASE (0x22100000) + +/* **************************************************************************** */ +/* MAG_IP_CFG_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD000) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD004) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_2_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD008) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_3_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD00C) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_4_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD010) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_5_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD014) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_6_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD018) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_CFG_7_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD01C) /* PLL2的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_STATE_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD024) /* PLL2状态寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL2_STATE_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD028) /* PLL2状态寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD02C) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD030) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_2_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD034) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_3_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD038) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_4_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD03C) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_5_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD040) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_6_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD044) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_CFG_7_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD048) /* PLL3的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_STATE_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD050) /* PLL3状态寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL3_STATE_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD054) /* PLL3状态寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD058) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD05C) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_2_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD060) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_3_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD064) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_4_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD068) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_5_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD06C) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_6_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD070) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_CFG_7_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD074) /* PLL4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_STATE_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD07C) /* PLL4状态寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL4_STATE_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD080) /* PLL4状态寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL234_COM_CFG_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD084) /* PLL2/3/4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL234_COM_CFG_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD088) /* PLL2/3/4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_PLL234_COM_CFG_2_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD08C) /* PLL2/3/4的config寄存器 */ +#define CSR_MAG_IP_CFG_CSR_TSENSOR_CFG_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD100) /* TSENSOR IP的配置寄存器 */ +#define CSR_MAG_IP_CFG_CSR_TSENSOR_CFG_1_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD104) /* TSENSOR IP的配置寄存器 */ +#define CSR_MAG_IP_CFG_CSR_TSENSOR_SATUS_0_REG (CSR_MAG_IP_CFG_CSR_BASE + 0xD108) /* TSENSOR IP的状态寄存器 */ + +#endif // __MAG_FC_SDS_HARDEN_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mag_top_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mag_top_reg_offset.h new file mode 100644 index 000000000..3d63417d9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/mag_top_reg_offset.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2021. All rights reserved. + * File name : mag_top_reg_offset.h + * Date : 2020/3/5 + * Description : the definition of mag top reg + */ + +#ifndef MAG_TOP_REG_OFFSET_H +#define MAG_TOP_REG_OFFSET_H + +/* MAG_CSR Base address of Module's Register */ +#define CSR_MAG_CSR_BASE (0x22100000) + +/* **************************************************************************** */ +/* MAG_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MAG_CSR_MAG_FPGA_VER_REG (CSR_MAG_CSR_BASE + 0x0) /* FPGA版本寄存器 */ +#define CSR_MAG_CSR_MAG_EMU_VER_REG (CSR_MAG_CSR_BASE + 0x4) /* EMU版本寄存器 */ +#define CSR_MAG_CSR_MAG_INT_VECTOR_REG (CSR_MAG_CSR_BASE + 0x10) /* 中断向量寄存器 */ +#define CSR_MAG_CSR_MAG_INT_REG (CSR_MAG_CSR_BASE + 0x14) /* 中断数据寄存器 */ +#define CSR_MAG_CSR_MAG_INT_EN_REG (CSR_MAG_CSR_BASE + 0x18) /* 中断使能寄存器 */ +#define CSR_MAG_CSR_MAG_SOPEOP_ERR_REG (CSR_MAG_CSR_BASE + 0x1C) /* MAG SOPEOP MISS中断错误寄存器。 */ +#define CSR_MAG_CSR_MAG_RAM_UCERR_REG (CSR_MAG_CSR_BASE + 0x20) /* RAM 不可纠错误中断错误寄存器。 */ +#define CSR_MAG_CSR_MAG_RAM_CERR_REG (CSR_MAG_CSR_BASE + 0x24) /* RAM 可纠错误中断错误寄存器。 */ +#define CSR_MAG_CSR_MAG_CRDT_ERR_REG (CSR_MAG_CSR_BASE + 0x28) /* 信用错误中断错误寄存器。 */ +#define CSR_MAG_CSR_MAG_FIFO_OVFL_REG (CSR_MAG_CSR_BASE + 0x2C) /* FIFO溢出中断错误寄存器。 */ +#define CSR_MAG_CSR_MAG_INDIR_ERR_REG (CSR_MAG_CSR_BASE + 0x30) /* HIMAC和ANLT间接访问错误寄存器 */ +#define CSR_MAG_CSR_MAG_UCERR_CTRL_REG (CSR_MAG_CSR_BASE + 0x100) /* MAG致命错误控制寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_CTRL_HH_REG (CSR_MAG_CSR_BASE + 0x104) /* MAG模块RAM MOD控制寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_CTRL_HM_REG (CSR_MAG_CSR_BASE + 0x108) /* MAG模块RAM MOD控制寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_CTRL_MM_REG (CSR_MAG_CSR_BASE + 0x10C) /* MAG模块RAM MOD控制寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_CTRL_ML_REG (CSR_MAG_CSR_BASE + 0x110) /* MAG模块RAM MOD控制寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_CTRL_LL_REG (CSR_MAG_CSR_BASE + 0x114) /* MAG模块RAM MOD控制寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_ERR_CHK_BYPASS_REG (CSR_MAG_CSR_BASE + 0x118) /* MAG模块RAM错误检查BYPASS寄存器 */ +#define CSR_MAG_CSR_MAG_INJ_RAM_ERR_CFG_REG (CSR_MAG_CSR_BASE + 0x11C) /* MAG模块RAM错误注入寄存器 */ +#define CSR_MAG_CSR_MAG_FIFO_TH_REG (CSR_MAG_CSR_BASE + 0x120) /* FIFO门限配置寄存器 */ +#define CSR_MAG_CSR_MAG_RAM_UCERR_CNT_REG (CSR_MAG_CSR_BASE + 0x600) /* RAM 不可纠错误计数器 */ +#define CSR_MAG_CSR_MAG_RAM_CERR_CNT_REG (CSR_MAG_CSR_BASE + 0x604) /* RAM 可纠错误计数器 */ +#define CSR_MAG_CSR_MAG_INDIR_ACCESS_ILGL_CNT_REG (CSR_MAG_CSR_BASE + 0x608) /* 间接访问错误计数器 */ +#define CSR_MAG_CSR_MAG_WORK_MODE_REG (CSR_MAG_CSR_BASE + 0x1000) /* MAG工作模式配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_DA_H_REG (CSR_MAG_CSR_BASE + 0x1004) /* MAG PTP报文DA配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_DA_L_REG (CSR_MAG_CSR_BASE + 0x1008) /* MAG PTP报文DA配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_SA_H_REG (CSR_MAG_CSR_BASE + 0x100C) /* MAG PTP报文SA配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_SA_L_REG (CSR_MAG_CSR_BASE + 0x1010) /* MAG PTP报文SA配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_ETYPE_REG (CSR_MAG_CSR_BASE + 0x1014) /* MAG PTP报文EtherType配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_MASK_REG (CSR_MAG_CSR_BASE + 0x1018) /* MAG PTP报文MASK配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_CLK_PERIOD_REG \ + (CSR_MAG_CSR_BASE + 0x5000) /* PTP时钟周期配置寄存器。用于在CPI提供的时钟基础上维护PTP本地时钟。 */ +#define CSR_MAG_CSR_MAG_PTP_CLK_OFS_REG (CSR_MAG_CSR_BASE + 0x5004) /* MAG PTP 时钟偏移配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_CLK_SNAP_EN_REG (CSR_MAG_CSR_BASE + 0x5008) /* Capture PTP时钟配置寄存器 */ +#define CSR_MAG_CSR_MAG_PTP_SNAPD_80BCLK_H16_REG (CSR_MAG_CSR_BASE + 0x5400) /* 80比特PTP时钟 */ +#define CSR_MAG_CSR_MAG_PTP_SNAPD_80BCLK_M32_REG (CSR_MAG_CSR_BASE + 0x5404) /* 80比特PTP时钟 */ +#define CSR_MAG_CSR_MAG_PTP_SNAPD_80BCLK_L32_REG (CSR_MAG_CSR_BASE + 0x5408) /* 80比特PTP时钟 */ +#define CSR_MAG_CSR_MAG_PTP_SNAPD_48BCLK_H16_REG (CSR_MAG_CSR_BASE + 0x540C) /* 48比特PTP时钟 */ +#define CSR_MAG_CSR_MAG_PTP_SNAPD_48BCLK_L32_REG (CSR_MAG_CSR_BASE + 0x5410) /* 48比特PTP时钟 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_0_REG (CSR_MAG_CSR_BASE + 0x6000) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_1_REG (CSR_MAG_CSR_BASE + 0x6004) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_2_REG (CSR_MAG_CSR_BASE + 0x6008) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_3_REG (CSR_MAG_CSR_BASE + 0x600C) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_4_REG (CSR_MAG_CSR_BASE + 0x6010) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_5_REG (CSR_MAG_CSR_BASE + 0x6014) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_6_REG (CSR_MAG_CSR_BASE + 0x6018) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_7_REG (CSR_MAG_CSR_BASE + 0x601C) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_8_REG (CSR_MAG_CSR_BASE + 0x6020) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_9_REG (CSR_MAG_CSR_BASE + 0x6024) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_10_REG (CSR_MAG_CSR_BASE + 0x6028) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_11_REG (CSR_MAG_CSR_BASE + 0x602C) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_12_REG (CSR_MAG_CSR_BASE + 0x6030) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_13_REG (CSR_MAG_CSR_BASE + 0x6034) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_14_REG (CSR_MAG_CSR_BASE + 0x6038) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_15_REG (CSR_MAG_CSR_BASE + 0x603C) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_16_REG (CSR_MAG_CSR_BASE + 0x6040) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_17_REG (CSR_MAG_CSR_BASE + 0x6044) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_18_REG (CSR_MAG_CSR_BASE + 0x6048) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_19_REG (CSR_MAG_CSR_BASE + 0x604C) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_20_REG (CSR_MAG_CSR_BASE + 0x6050) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_21_REG (CSR_MAG_CSR_BASE + 0x6054) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_22_REG (CSR_MAG_CSR_BASE + 0x6058) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_LEDC_CFG_23_REG (CSR_MAG_CSR_BASE + 0x605C) /* LED点灯控制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_PORT_MAP_REG (CSR_MAG_CSR_BASE + 0x7000) /* 流控端口映射寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_0_REG (CSR_MAG_CSR_BASE + 0x7004) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_1_REG (CSR_MAG_CSR_BASE + 0x7008) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_2_REG (CSR_MAG_CSR_BASE + 0x700C) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_3_REG (CSR_MAG_CSR_BASE + 0x7010) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_4_REG (CSR_MAG_CSR_BASE + 0x7014) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_5_REG (CSR_MAG_CSR_BASE + 0x7018) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_6_REG (CSR_MAG_CSR_BASE + 0x701C) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_H_7_REG (CSR_MAG_CSR_BASE + 0x7020) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_0_REG (CSR_MAG_CSR_BASE + 0x7100) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_1_REG (CSR_MAG_CSR_BASE + 0x7104) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_2_REG (CSR_MAG_CSR_BASE + 0x7108) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_3_REG (CSR_MAG_CSR_BASE + 0x710C) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_4_REG (CSR_MAG_CSR_BASE + 0x7110) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_5_REG (CSR_MAG_CSR_BASE + 0x7114) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_6_REG (CSR_MAG_CSR_BASE + 0x7118) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_TX_COS_BC_L_7_REG (CSR_MAG_CSR_BASE + 0x711C) /* MAG TX COS复制配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_IPSURX_LINK_XOFF_REG (CSR_MAG_CSR_BASE + 0x7200) /* IPSURX反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_0_REG (CSR_MAG_CSR_BASE + 0x7300) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_1_REG (CSR_MAG_CSR_BASE + 0x7304) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_2_REG (CSR_MAG_CSR_BASE + 0x7308) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_3_REG (CSR_MAG_CSR_BASE + 0x730C) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_4_REG (CSR_MAG_CSR_BASE + 0x7310) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_5_REG (CSR_MAG_CSR_BASE + 0x7314) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_6_REG (CSR_MAG_CSR_BASE + 0x7318) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_SET_7_REG (CSR_MAG_CSR_BASE + 0x731C) /* 反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_0_REG (CSR_MAG_CSR_BASE + 0x7400) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_1_REG (CSR_MAG_CSR_BASE + 0x7404) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_2_REG (CSR_MAG_CSR_BASE + 0x7408) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_3_REG (CSR_MAG_CSR_BASE + 0x740C) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_4_REG (CSR_MAG_CSR_BASE + 0x7410) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_5_REG (CSR_MAG_CSR_BASE + 0x7414) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_6_REG (CSR_MAG_CSR_BASE + 0x7418) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_BYPASS_7_REG (CSR_MAG_CSR_BASE + 0x741C) /* BYPASS反压配置寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_0_REG (CSR_MAG_CSR_BASE + 0x7700) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_1_REG (CSR_MAG_CSR_BASE + 0x7704) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_2_REG (CSR_MAG_CSR_BASE + 0x7708) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_3_REG (CSR_MAG_CSR_BASE + 0x770C) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_4_REG (CSR_MAG_CSR_BASE + 0x7710) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_5_REG (CSR_MAG_CSR_BASE + 0x7714) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_6_REG (CSR_MAG_CSR_BASE + 0x7718) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_CUR_7_REG (CSR_MAG_CSR_BASE + 0x771C) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_0_REG (CSR_MAG_CSR_BASE + 0x7800) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_1_REG (CSR_MAG_CSR_BASE + 0x7804) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_2_REG (CSR_MAG_CSR_BASE + 0x7808) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_3_REG (CSR_MAG_CSR_BASE + 0x780C) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_4_REG (CSR_MAG_CSR_BASE + 0x7810) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_5_REG (CSR_MAG_CSR_BASE + 0x7814) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_6_REG (CSR_MAG_CSR_BASE + 0x7818) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_FLC_BP_ST_HST_7_REG (CSR_MAG_CSR_BASE + 0x781C) /* 反压状态寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_0_REG (CSR_MAG_CSR_BASE + 0x8000) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_1_REG (CSR_MAG_CSR_BASE + 0x8004) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_2_REG (CSR_MAG_CSR_BASE + 0x8008) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_3_REG (CSR_MAG_CSR_BASE + 0x800C) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_4_REG (CSR_MAG_CSR_BASE + 0x8010) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_5_REG (CSR_MAG_CSR_BASE + 0x8014) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_6_REG (CSR_MAG_CSR_BASE + 0x8018) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_7_REG (CSR_MAG_CSR_BASE + 0x801C) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_8_REG (CSR_MAG_CSR_BASE + 0x8020) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_9_REG (CSR_MAG_CSR_BASE + 0x8024) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_CRDT_INI_10_REG (CSR_MAG_CSR_BASE + 0x8028) /* 通道信用配置寄存器 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_0_REG (CSR_MAG_CSR_BASE + 0x8400) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_1_REG (CSR_MAG_CSR_BASE + 0x8404) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_2_REG (CSR_MAG_CSR_BASE + 0x8408) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_3_REG (CSR_MAG_CSR_BASE + 0x840C) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_4_REG (CSR_MAG_CSR_BASE + 0x8410) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_5_REG (CSR_MAG_CSR_BASE + 0x8414) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_6_REG (CSR_MAG_CSR_BASE + 0x8418) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_7_REG (CSR_MAG_CSR_BASE + 0x841C) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_8_REG (CSR_MAG_CSR_BASE + 0x8420) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_9_REG (CSR_MAG_CSR_BASE + 0x8424) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_PORT_ST_10_REG (CSR_MAG_CSR_BASE + 0x8428) /* 通道数据状态 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8C00) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8C04) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8C08) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x8C0C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x8C10) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x8C14) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x8C18) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x8C1C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_8_REG (CSR_MAG_CSR_BASE + 0x8C20) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_9_REG (CSR_MAG_CSR_BASE + 0x8C24) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCVD_PKT_CNT_10_REG (CSR_MAG_CSR_BASE + 0x8C28) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8C40) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8C44) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8C48) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x8C4C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x8C50) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x8C54) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x8C58) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x8C5C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_8_REG (CSR_MAG_CSR_BASE + 0x8C60) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_9_REG (CSR_MAG_CSR_BASE + 0x8C64) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_GOOD_PKT_CNT_10_REG (CSR_MAG_CSR_BASE + 0x8C68) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8C80) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8C84) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8C88) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x8C8C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x8C90) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x8C94) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x8C98) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x8C9C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_8_REG (CSR_MAG_CSR_BASE + 0x8CA0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_9_REG (CSR_MAG_CSR_BASE + 0x8CA4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_BAD_PKT_CNT_10_REG (CSR_MAG_CSR_BASE + 0x8CA8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8CC0) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8CC4) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8CC8) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_3_REG (CSR_MAG_CSR_BASE + 0x8CCC) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_4_REG (CSR_MAG_CSR_BASE + 0x8CD0) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_5_REG (CSR_MAG_CSR_BASE + 0x8CD4) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_6_REG (CSR_MAG_CSR_BASE + 0x8CD8) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_7_REG (CSR_MAG_CSR_BASE + 0x8CDC) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_8_REG (CSR_MAG_CSR_BASE + 0x8CE0) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_9_REG (CSR_MAG_CSR_BASE + 0x8CE4) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_PETX_CYC_CNT_10_REG (CSR_MAG_CSR_BASE + 0x8CE8) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8CEC) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8CF0) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8CF4) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x8CF8) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x8CFC) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x8D00) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x8D04) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x8D08) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_8_REG (CSR_MAG_CSR_BASE + 0x8D0C) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_9_REG (CSR_MAG_CSR_BASE + 0x8D10) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_PKT_CRDT_CNT_10_REG (CSR_MAG_CSR_BASE + 0x8D14) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_PETX_CMDIDX_CRDT_CNT_REG (CSR_MAG_CSR_BASE + 0x8D18) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_CRY_CYC_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8D1C) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_CRY_CYC_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8D20) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_SNT_CRY_CYC_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8D24) /* 报文拍数计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_CRY_CRDT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x8D28) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_CRY_CRDT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x8D2C) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_CSE_RCV_CRY_CRDT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x8D30) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_0_REG (CSR_MAG_CSR_BASE + 0x9000) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_1_REG (CSR_MAG_CSR_BASE + 0x9004) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_2_REG (CSR_MAG_CSR_BASE + 0x9008) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_3_REG (CSR_MAG_CSR_BASE + 0x900C) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_4_REG (CSR_MAG_CSR_BASE + 0x9010) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_5_REG (CSR_MAG_CSR_BASE + 0x9014) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_6_REG (CSR_MAG_CSR_BASE + 0x9018) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_CFG_7_REG (CSR_MAG_CSR_BASE + 0x901C) /* TXDP端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_SCH_CALENDAR_REG (CSR_MAG_CSR_BASE + 0x9040) /* TXDP调度时隙表配置 */ +#define CSR_MAG_CSR_MAG_TXDP_SHORT_MAC_PKT_LEN_REG (CSR_MAG_CSR_BASE + 0x9044) /* 短包长度配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_START_REG (CSR_MAG_CSR_BASE + 0x9048) /* 性能测试配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_PORT_REG (CSR_MAG_CSR_BASE + 0x904C) /* 性能测试配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_TIME_H32_REG (CSR_MAG_CSR_BASE + 0x9050) /* 性能测试配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_TIME_L32_REG (CSR_MAG_CSR_BASE + 0x9054) /* 性能测试配置寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_DONE_REG (CSR_MAG_CSR_BASE + 0x9400) /* 性能测试结束状态寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_0_REG (CSR_MAG_CSR_BASE + 0x9410) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_1_REG (CSR_MAG_CSR_BASE + 0x9414) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_2_REG (CSR_MAG_CSR_BASE + 0x9418) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_3_REG (CSR_MAG_CSR_BASE + 0x941C) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_4_REG (CSR_MAG_CSR_BASE + 0x9420) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_5_REG (CSR_MAG_CSR_BASE + 0x9424) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_6_REG (CSR_MAG_CSR_BASE + 0x9428) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_ST_CUR_7_REG (CSR_MAG_CSR_BASE + 0x942C) /* MAC TXDP PORT状态 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_BYTE_NUM_H32_REG (CSR_MAG_CSR_BASE + 0x9440) /* 性能计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_BYTE_NUM_L32_REG (CSR_MAG_CSR_BASE + 0x9444) /* 性能计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_PKT_NUM_H32_REG (CSR_MAG_CSR_BASE + 0x9448) /* 性能计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PERF_MON_PKT_NUM_L32_REG (CSR_MAG_CSR_BASE + 0x944C) /* 性能计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_FIFO_CNT_REG (CSR_MAG_CSR_BASE + 0x9450) /* FIFO当前深度计数寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_FIFO_CUR_ST_REG (CSR_MAG_CSR_BASE + 0x9454) /* FIFO当前状态寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_FIFO_HST_ST_REG (CSR_MAG_CSR_BASE + 0x9458) /* FIFO历史状态寄存器 */ +#define CSR_MAG_CSR_MAG_TXDP_FROM_FC_BP_HST_REG (CSR_MAG_CSR_BASE + 0x945C) /* FC反压状态 */ +#define CSR_MAG_CSR_MAG_TXDP_RCVD_PTP_CNT_REG (CSR_MAG_CSR_BASE + 0x9C00) /* 时戳报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_RECD_SOPEOP_ERR_CNT_REG (CSR_MAG_CSR_BASE + 0x9C04) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x9C08) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x9C0C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x9C10) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x9C14) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x9C18) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x9C1C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x9C20) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_GOOD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x9C24) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x9C48) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x9C4C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x9C50) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x9C54) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x9C58) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x9C5C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x9C60) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_PORT_SNT_BAD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x9C64) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_TXDP_SHORT_MAC_PKT_CNT_REG (CSR_MAG_CSR_BASE + 0x9C80) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_0_REG (CSR_MAG_CSR_BASE + 0x9C84) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_1_REG (CSR_MAG_CSR_BASE + 0x9C88) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_2_REG (CSR_MAG_CSR_BASE + 0x9C8C) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_3_REG (CSR_MAG_CSR_BASE + 0x9C90) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_4_REG (CSR_MAG_CSR_BASE + 0x9C94) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_5_REG (CSR_MAG_CSR_BASE + 0x9C98) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_6_REG (CSR_MAG_CSR_BASE + 0x9C9C) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_SNT_HIMAC_SEG_CNT_7_REG (CSR_MAG_CSR_BASE + 0x9CA0) /* 报文segment数计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_0_REG (CSR_MAG_CSR_BASE + 0x9CA4) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_1_REG (CSR_MAG_CSR_BASE + 0x9CA8) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_2_REG (CSR_MAG_CSR_BASE + 0x9CAC) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_3_REG (CSR_MAG_CSR_BASE + 0x9CB0) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_4_REG (CSR_MAG_CSR_BASE + 0x9CB4) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_5_REG (CSR_MAG_CSR_BASE + 0x9CB8) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_6_REG (CSR_MAG_CSR_BASE + 0x9CBC) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RCV_HIMAC_CRDT_CNT_7_REG (CSR_MAG_CSR_BASE + 0x9CC0) /* 信用计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_DROP_PFC_PAUSE_REG (CSR_MAG_CSR_BASE + 0xA000) /* MAC端口配置寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_RTS_PORT_REG (CSR_MAG_CSR_BASE + 0xA004) /* 回传时戳port配置寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_RTS_GAP_REG (CSR_MAG_CSR_BASE + 0xA008) /* 回传时戳GAP配置寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_CLR_MAC_DROP_CNT_EN_REG \ + (CSR_MAG_CSR_BASE + 0xA00C) /* 清除MAC PORT丢弃PFC/PUASE的CNT和溢出丢弃CNT */ +#define CSR_MAG_CSR_MAG_RXDP_FROM_IPSURX_BP_CUR_REG (CSR_MAG_CSR_BASE + 0xA010) /* IPSURX反压状态 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_SOPEOP_ST_REG (CSR_MAG_CSR_BASE + 0xA014) /* SOP/EOP状态寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_FIFO_CNT_REG (CSR_MAG_CSR_BASE + 0xA018) /* FIFO当前深度计数寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_FIFO_CUR_ST_REG (CSR_MAG_CSR_BASE + 0xA01C) /* FIFO当前状态寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_FIFO_HST_ST_REG (CSR_MAG_CSR_BASE + 0xA020) /* FIFO历史状态寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RCVD_SEOP_ERR_HST_REG (CSR_MAG_CSR_BASE + 0xA024) /* SOP/EOP错误历史寄存器 */ +#define CSR_MAG_CSR_MAG_RXDP_FROM_IPSURX_BP_CNT_REG (CSR_MAG_CSR_BASE + 0xA028) /* 反压计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_RCVD_RTS_CNT_REG (CSR_MAG_CSR_BASE + 0xA02C) /* 接收到的回传时戳计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_RTS_DROP_CNT_REG (CSR_MAG_CSR_BASE + 0xA030) /* 回传时戳丢弃计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_RTSP_OVFL_CNT_REG (CSR_MAG_CSR_BASE + 0xA034) /* 回传时戳FIFO溢出计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAC90) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAC94) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAC98) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAC9C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0xACA0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0xACA4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0xACA8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_GOOD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0xACAC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0xACD0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0xACD4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0xACD8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0xACDC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0xACE0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0xACE4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0xACE8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PORT_RECD_BAD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0xACEC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAD10) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAD14) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAD18) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAD1C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_4_REG (CSR_MAG_CSR_BASE + 0xAD20) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_5_REG (CSR_MAG_CSR_BASE + 0xAD24) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_6_REG (CSR_MAG_CSR_BASE + 0xAD28) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_PAUSE_DROP_CNT_7_REG (CSR_MAG_CSR_BASE + 0xAD2C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAD50) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAD54) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAD58) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAD5C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_4_REG (CSR_MAG_CSR_BASE + 0xAD60) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_5_REG (CSR_MAG_CSR_BASE + 0xAD64) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_6_REG (CSR_MAG_CSR_BASE + 0xAD68) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXS2P_AFIFO_OVFL_DROP_CNT_7_REG (CSR_MAG_CSR_BASE + 0xAD6C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAD90) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAD94) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAD98) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAD9C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0xADA0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0xADA4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0xADA8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_GOOD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0xADAC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0xADD0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0xADD4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0xADD8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0xADDC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0xADE0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0xADE4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0xADE8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_PORT_RECD_BAD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0xADEC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAE10) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAE14) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAE18) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAE1C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_4_REG (CSR_MAG_CSR_BASE + 0xAE20) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_5_REG (CSR_MAG_CSR_BASE + 0xAE24) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_6_REG (CSR_MAG_CSR_BASE + 0xAE28) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_RXDP_CPD_FIFO_OVFL_DROP_CNT_7_REG (CSR_MAG_CSR_BASE + 0xAE2C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAE50) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAE54) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAE58) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAE5C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0xAE60) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0xAE64) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0xAE68) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_GOOD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0xAE6C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_0_REG (CSR_MAG_CSR_BASE + 0xAE90) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_1_REG (CSR_MAG_CSR_BASE + 0xAE94) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_2_REG (CSR_MAG_CSR_BASE + 0xAE98) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_3_REG (CSR_MAG_CSR_BASE + 0xAE9C) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_4_REG (CSR_MAG_CSR_BASE + 0xAEA0) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_5_REG (CSR_MAG_CSR_BASE + 0xAEA4) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_6_REG (CSR_MAG_CSR_BASE + 0xAEA8) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_IPSURX_PORT_SNT_BAD_PKT_CNT_7_REG (CSR_MAG_CSR_BASE + 0xAEAC) /* 报文计数器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_0_REG (CSR_MAG_CSR_BASE + 0xB000) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_1_REG (CSR_MAG_CSR_BASE + 0xB004) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_2_REG (CSR_MAG_CSR_BASE + 0xB008) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_3_REG (CSR_MAG_CSR_BASE + 0xB00C) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_4_REG (CSR_MAG_CSR_BASE + 0xB010) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_5_REG (CSR_MAG_CSR_BASE + 0xB014) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_6_REG (CSR_MAG_CSR_BASE + 0xB018) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_LANE_LOS_CONFIG_7_REG (CSR_MAG_CSR_BASE + 0xB01C) /* LANE LOS信号配置寄存器 */ +#define CSR_MAG_CSR_MAG_SMUX_FIFO_CUR_ST_REG (CSR_MAG_CSR_BASE + 0xB020) /* FIFO当前状态寄存器 */ +#define CSR_MAG_CSR_MAG_SMUX_FIFO_HST_ST_REG (CSR_MAG_CSR_BASE + 0xB024) /* FIFO历史状态寄存器 */ + +#endif // MAG_TOP_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mag/smag_cfg_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/smag_cfg_reg_offset.h new file mode 100644 index 000000000..6f8883462 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mag/smag_cfg_reg_offset.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2017-2021. All rights reserved. + * File name : smag_cfg_reg_offset.h + * Date : 2017/02/21 + * Description : smag reg header file + */ + +#ifndef SMAG_CFG_REG_OFFSET_H +#define SMAG_CFG_REG_OFFSET_H + +/* SMAG_CFG Base address of Module's Register */ +#define HI1823_SMAG_CFG_BASE (0x22120000) + +/* **************************************************************************** */ +/* HI1823 SMAG_CFG Registers' Definitions */ +/* **************************************************************************** */ + +#define HI1823_SMAG_CFG_SMAG_MODE_REG (HI1823_SMAG_CFG_BASE + 0x0) /* SMAGģʽ���ƼĴ����� */ +#define HI1823_SMAG_CFG_SMAG2MAC_SIG_DETECT_REG (HI1823_SMAG_CFG_BASE + 0x4) /* SMAG���͸�MAC���źſ��ȼ�� */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX0_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x8) /* SMAG���͸�MAC��Port0����ͳ��DFX0 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX0_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0xC) /* SMAG���͸�MAC��Port0����ͳ��DFX1 */ +#define HI1823_SMAG_CFG_SMAG_INT_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x10) /* SMAGģ���ж�״̬�Ĵ��� */ +#define HI1823_SMAG_CFG_TX0_AFIFO_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x14) /* д��Port0�����첽FIFO�ı���ͳ��DFX0 */ +#define HI1823_SMAG_CFG_TX0_AFIFO_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x18) /* д��Port0�����첽FIFO�ı���ͳ��DFX1 */ +#define HI1823_SMAG_CFG_SMAG_RX_TX_EN_REG (HI1823_SMAG_CFG_BASE + 0x1C) /* SMAG RX/TXʹ�ܼĴ��� */ +#define HI1823_SMAG_CFG_SMAG_INT_MASK_REG (HI1823_SMAG_CFG_BASE + 0x20) /* SMAGģ���ж����μĴ��� */ +#define HI1823_SMAG_CFG_SMAG_INT_SET_REG (HI1823_SMAG_CFG_BASE + 0x30) /* SMAGģ���ж���λ�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_MAC_DEBUG_REG (HI1823_SMAG_CFG_BASE + 0x34) /* MAC Debug �Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_IPSURX_ERR_DEBUG0_REG (HI1823_SMAG_CFG_BASE + 0x38) /* SMAG��IPSURX�ӿڵ��쳣ͳ�� */ +#define HI1823_SMAG_CFG_SMAG_IPSURX_ERR_DEBUG1_REG (HI1823_SMAG_CFG_BASE + 0x3C) /* SAMG��IPSURX�ӿڵ��쳣ͳ�� */ +#define HI1823_SMAG_CFG_SMAG_CHAN_XOFF_DEBUG_REG (HI1823_SMAG_CFG_BASE + 0x40) /* SMAG���յ���QU��COS��ѹDEBUG�Ĵ��� \ + */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P00_REG (HI1823_SMAG_CFG_BASE + 0x44) /* SMAG��PE�ӿڶ˿�0 DFX�Ĵ���0 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P01_REG (HI1823_SMAG_CFG_BASE + 0x48) /* SMAG��PE�ӿڶ˿�0 DFX�Ĵ���1 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P10_REG (HI1823_SMAG_CFG_BASE + 0x4C) /* SMAG��PE�ӿڶ˿�1 DFX�Ĵ���0 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P11_REG (HI1823_SMAG_CFG_BASE + 0x50) /* SMAG��PE�ӿڶ˿�1 DFX�Ĵ���1 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P20_REG (HI1823_SMAG_CFG_BASE + 0x54) /* SMAG��PE�ӿڶ˿�2 DFX�Ĵ���0 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P21_REG (HI1823_SMAG_CFG_BASE + 0x58) /* SMAG��PE�ӿڶ˿�2 DFX�Ĵ���1 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P30_REG (HI1823_SMAG_CFG_BASE + 0x5C) /* SMAG��PE�ӿڶ˿�3 DFX�Ĵ���0 */ +#define HI1823_SMAG_CFG_SMAG_PE_DFX_P31_REG (HI1823_SMAG_CFG_BASE + 0x60) /* SMAG��PE�ӿڶ˿�3 DFX�Ĵ���1 */ +#define HI1823_SMAG_CFG_SMAG_CNT_FIFO_0_REG (HI1823_SMAG_CFG_BASE + 0x64) /* SMAG��������CNT FIFO DFX�Ĵ���0 */ +#define HI1823_SMAG_CFG_SMAG_CNT_FIFO_1_REG (HI1823_SMAG_CFG_BASE + 0x68) /* SMAG��������CNT FIFO DFX�Ĵ���1 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX1_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x6C) /* SMAG���͸�MAC��Port1����ͳ��DFX0 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX1_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x70) /* SMAG���͸�MAC��Port1����ͳ��DFX1 */ +#define HI1823_SMAG_CFG_TX1_AFIFO_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x74) /* д��Port1�����첽FIFO�ı���ͳ��DFX0 */ +#define HI1823_SMAG_CFG_TX1_AFIFO_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x78) /* д��Port1�����첽FIFO�ı���ͳ��DFX1 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX2_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x7C) /* SMAG���͸�MAC��Port2����ͳ��DFX0 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX2_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x80) /* SMAG���͸�MAC��Port2����ͳ��DFX1 */ +#define HI1823_SMAG_CFG_TX2_AFIFO_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x84) /* д��Port2�����첽FIFO�ı���ͳ��DFX0 */ +#define HI1823_SMAG_CFG_TX2_AFIFO_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x88) /* д��Port2�����첽FIFO�ı���ͳ��DFX1 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX3_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x8C) /* SMAG���͸�MAC��Port3����ͳ��DFX0 */ +#define HI1823_SMAG_CFG_SMAG2MAC_TX3_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x90) /* SMAG���͸�MAC��Port3����ͳ��DFX1 */ +#define HI1823_SMAG_CFG_TX3_AFIFO_DFX_0_REG (HI1823_SMAG_CFG_BASE + 0x94) /* д��Port3�����첽FIFO�ı���ͳ��DFX0 */ +#define HI1823_SMAG_CFG_TX3_AFIFO_DFX_1_REG (HI1823_SMAG_CFG_BASE + 0x98) /* д��Port3�����첽FIFO�ı���ͳ��DFX1 */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH1_REG \ + (HI1823_SMAG_CFG_BASE + 0xA0) /* SMAGģ�鷢���첽FIFO����ˮ��port0~port1�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH2_REG \ + (HI1823_SMAG_CFG_BASE + 0xA4) /* SMAGģ�鷢���첽FIFO����ˮ��port2~port3�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH3_REG \ + (HI1823_SMAG_CFG_BASE + 0xA8) /* SMAGģ�鷢���첽FIFO����ˮ��port4~port5�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH4_REG \ + (HI1823_SMAG_CFG_BASE + 0xAC) /* SMAGģ�鷢���첽FIFO����ˮ��port6~port7�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH5_REG \ + (HI1823_SMAG_CFG_BASE + 0xB0) /* SMAGģ������첽�첽FIFO����ˮ��port0~port1��port4~port5�ĸ�ˮ�� */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH6_REG \ + (HI1823_SMAG_CFG_BASE + 0xB4) /* SMAGģ������첽FIFO����ˮ��port2~port3��port6~port7�ĸ�ˮ�� */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH7_REG \ + (HI1823_SMAG_CFG_BASE + 0xB8) /* SMAGģ������첽FIFO����ˮ��port0~port1��port4~port5�ĵ�ˮ�� */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_AF_TH8_REG \ + (HI1823_SMAG_CFG_BASE + 0xBC) /* SMAGģ������첽FIFO����ˮ��port2~port3��port6~port7�ĵ�ˮ�� */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT1_REG \ + (HI1823_SMAG_CFG_BASE + 0xC0) /* SMAGģ�鷢���첽FIFOд���ݸ���port0~port1�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT2_REG \ + (HI1823_SMAG_CFG_BASE + 0xC4) /* SMAGģ�鷢���첽FIFOд���ݸ���port2~port3�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT3_REG \ + (HI1823_SMAG_CFG_BASE + 0xC8) /* SMAGģ�鷢���첽FIFOд���ݸ���port4~port5�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT4_REG \ + (HI1823_SMAG_CFG_BASE + 0xCC) /* SMAGģ�鷢���첽FIFOд���ݸ���port6~port7�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT5_REG \ + (HI1823_SMAG_CFG_BASE + 0xD0) /* SMAGģ������첽FIFOд���ݸ���port0~port1�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT6_REG \ + (HI1823_SMAG_CFG_BASE + 0xD4) /* SMAGģ������첽FIFOд���ݸ���port2~port3�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT7_REG \ + (HI1823_SMAG_CFG_BASE + 0xD8) /* SMAGģ������첽FIFOд���ݸ���port4~port5�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_CNT8_REG \ + (HI1823_SMAG_CFG_BASE + 0xDC) /* SMAGģ������첽FIFOд���ݸ���port6~port7�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_STATUS1_REG \ + (HI1823_SMAG_CFG_BASE + 0xE0) /* SMAGģ�鷢���첽FIFO״̬�Ĵ���port0~port7�ķ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_STATUS2_REG \ + (HI1823_SMAG_CFG_BASE + 0xE4) /* SMAGģ���첽����FIFO״̬�Ĵ���port0~port7�Ľ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_FIFO_STATUS3_REG \ + (HI1823_SMAG_CFG_BASE + 0xE8) /* SMAGģ���첽���͡�����FIFO״̬�Ĵ���port0~port7�Ľ���FIFO */ +#define HI1823_SMAG_CFG_SMAG_XGEM_SYN_REG (HI1823_SMAG_CFG_BASE + 0xEC) /* �첽FIFO����ˮ��ͬ������ */ +#define HI1823_SMAG_CFG_SMAG_XGEM_CTL_REG (HI1823_SMAG_CFG_BASE + 0xF0) /* SMAGģ���XGEM��ģ����ƼĴ��� */ +#define HI1823_SMAG_CFG_SMAG_XGEM_STATUS2_REG \ + (HI1823_SMAG_CFG_BASE + 0xF4) /* SMAGģ���XGEM��ģ��PCSPMA��״̬port4~port7 */ +#define HI1823_SMAG_CFG_SMAG_XGEM_STATUS1_REG \ + (HI1823_SMAG_CFG_BASE + 0xF8) /* SMAGģ���XGEM��ģ��PCSPMA��״̬port0~port3 */ +#define HI1823_SMAG_CFG_SMAG_XGEM_STATUS3_REG (HI1823_SMAG_CFG_BASE + 0xFC) /* SMAGģ���XGEM��ģ���״̬�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_XGEM_PAUSE_TDATA1_REG \ + (HI1823_SMAG_CFG_BASE + 0x100) /* SMAGģ���XGEM��ģ���pause_tdata0~1 */ +#define HI1823_SMAG_CFG_SMAG_XGEM_PAUSE_TDATA2_REG \ + (HI1823_SMAG_CFG_BASE + 0x104) /* SMAGģ���XGEM��ģ���pause_tdata2~3 */ +#define HI1823_SMAG_CFG_SMAG_XGEM_PAUSE_TDATA3_REG \ + (HI1823_SMAG_CFG_BASE + 0x108) /* SMAGģ���XGEM��ģ���pause_tdata4~5 */ +#define HI1823_SMAG_CFG_SMAG_XGEM_PAUSE_TDATA4_REG \ + (HI1823_SMAG_CFG_BASE + 0x10C) /* SMAGģ���XGEM��ģ���pause_tdata6~7 */ +#define HI1823_SMAG_CFG_SMAG_RXDP_FIFO_STATUS_REG \ + (HI1823_SMAG_CFG_BASE + 0x110) /* SMAGģ��rxdp��txdp��FIFO״̬�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_DP_FIFO_TH1_REG (HI1823_SMAG_CFG_BASE + 0x114) /* SMAGģ��rxdp��txdp��FIFOˮ�����üĴ��� \ + */ +#define HI1823_SMAG_CFG_SMAG_DP_FIFO_TH2_REG (HI1823_SMAG_CFG_BASE + 0x118) /* SMAGģ��rxdp��txdp��FIFOˮ�����üĴ��� \ + */ +#define HI1823_SMAG_CFG_SMAG_TXDP_FIFO_STATUS1_REG (HI1823_SMAG_CFG_BASE + 0x11C) /* SMAGģ��txdp��FIFO״̬�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_FIFO_STATUS2_REG (HI1823_SMAG_CFG_BASE + 0x120) /* SMAGģ��txdp��FIFO״̬�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_SOP_EOP_ERR_CNT_REG \ + (HI1823_SMAG_CFG_BASE + 0x124) /* SMAGģ��txdpģ���鵽SOP EOP������������ϱ� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_SOP_ERR_CNT_REG \ + (HI1823_SMAG_CFG_BASE + 0x128) /* SMAGģ��txdpģ���鵽SOP ������������ϱ� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_EOP_ERR_CNT_REG \ + (HI1823_SMAG_CFG_BASE + 0x12C) /* SMAGģ��txdpģ���鵽EOP ������������ϱ� */ +#define HI1823_SMAG_CFG_PE_SMAG_PKT_STATISTICS_0_REG \ + (HI1823_SMAG_CFG_BASE + 0x130) /* SMAG TX���յ���PE ��������/�쳣���ĸ��� */ +#define HI1823_SMAG_CFG_PE_SMAG_PKT_STATISTICS_1_REG \ + (HI1823_SMAG_CFG_BASE + 0x134) /* SMAG TX���յ���PE ��������/�쳣���ĸ��� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_P5_ERR_CNT_REG \ + (HI1823_SMAG_CFG_BASE + 0x138) /* SMAGģ��txdpģ���鵽P5�˿ڵ�SOP EOP������������ϱ� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_P6_ERR_CNT_REG \ + (HI1823_SMAG_CFG_BASE + 0x13C) /* SMAGģ��txdpģ���鵽P6�˿ڵ�SOP EOP������������ϱ� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_P7_ERR_CNT_REG \ + (HI1823_SMAG_CFG_BASE + 0x140) /* SMAGģ��txdpģ���鵽P7�˿ڵ�SOP EOP������������ϱ� */ +#define HI1823_SMAG_CFG_SMAG_PHY2LGC_REMAP_EN_REG \ + (HI1823_SMAG_CFG_BASE + 0x144) /* SMAG�ڲ�4�������˿����ڲ��߼�ͨ������ӳ��ʹ�ܼĴ��� */ +#define HI1823_SMAG_CFG_SMAG_RX_COS_MODE_REG \ + (HI1823_SMAG_CFG_BASE + 0x148) /* SMAG�Խ��յ���PFC����֡�����ȼ���ӳ��Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_TX_COS_MODE_REG \ + (HI1823_SMAG_CFG_BASE + 0x14C) /* SMAG�Է��͵�PFC����֡�����ȼ���ӳ��Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_TIMER_HISTORY_0_REG \ + (HI1823_SMAG_CFG_BASE + 0x150) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬��������Cycle����ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_TIMER_HISTORY_1_REG \ + (HI1823_SMAG_CFG_BASE + 0x154) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬��������Cycle����ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_TIMER_HISTORY_2_REG \ + (HI1823_SMAG_CFG_BASE + 0x158) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬��������Cycle����ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_TIMER_HISTORY_3_REG \ + (HI1823_SMAG_CFG_BASE + 0x15C) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬��������Cycle����ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_INB_CNT_HISTORY_0_REG \ + (HI1823_SMAG_CFG_BASE + 0x160) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬�����������յ���8B��������ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_INB_CNT_HISTORY_1_REG \ + (HI1823_SMAG_CFG_BASE + 0x164) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬�����������յ���8B��������ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_INB_CNT_HISTORY_2_REG \ + (HI1823_SMAG_CFG_BASE + 0x168) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬�����������յ���8B��������ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_EMP2TH_INB_CNT_HISTORY_3_REG \ + (HI1823_SMAG_CFG_BASE + 0x16C) /* SMAG RX�첽FIFO�ɿ���ת���ǿ�״ֱ̬�����������յ���8B��������ʷ���ֵ */ +#define HI1823_SMAG_CFG_SMAG_RX_DEBUG_0_REG (HI1823_SMAG_CFG_BASE + 0x170) /* SMAG���յ����ܱ���vld���� */ +#define HI1823_SMAG_CFG_SMAG_RX_DEBUG_1_REG (HI1823_SMAG_CFG_BASE + 0x174) /* SMAG���յ����ܱ���vld���� */ +#define HI1823_SMAG_CFG_SMAG_RX_DEBUG_2_REG (HI1823_SMAG_CFG_BASE + 0x178) /* SMAG���յ����ܱ���vld���� */ +#define HI1823_SMAG_CFG_SMAG_RX_DEBUG_3_REG (HI1823_SMAG_CFG_BASE + 0x17C) /* SMAG���յ����ܱ���vld���� */ +#define HI1823_SMAG_CFG_SMAG_BP_HISTORY_REG (HI1823_SMAG_CFG_BASE + 0x180) /* SMAG�ⲿ�ӿڼ�����FIFO��ʷ��ѹ״̬ */ +#define HI1823_SMAG_CFG_SMAG_RX_COS_L_HISTORY_REG \ + (HI1823_SMAG_CFG_BASE + 0x184) /* SMAG���յ���QU����COS[31:0]��ѹ��ʷֵ */ +#define HI1823_SMAG_CFG_SMAG_RX_COS_H_HISTORY_REG \ + (HI1823_SMAG_CFG_BASE + 0x188) /* SMAG���յ���QU����COS[63:32]��ѹ��ʷֵ */ +#define HI1823_SMAG_CFG_SMAG_AFULL_TIMER_HISTORY_0_REG \ + (HI1823_SMAG_CFG_BASE + 0x18C) /* SMAG RX�첽FIFO�������ֵ����ʱ�� */ +#define HI1823_SMAG_CFG_SMAG_AFULL_TIMER_HISTORY_1_REG \ + (HI1823_SMAG_CFG_BASE + 0x190) /* SMAG RX�첽FIFO�������ֵ����ʱ�� */ +#define HI1823_SMAG_CFG_SMAG_AFULL_TIMER_HISTORY_2_REG \ + (HI1823_SMAG_CFG_BASE + 0x194) /* SMAG RX�첽FIFO�������ֵ����ʱ�� */ +#define HI1823_SMAG_CFG_SMAG_AFULL_TIMER_HISTORY_3_REG \ + (HI1823_SMAG_CFG_BASE + 0x198) /* SMAG RX�첽FIFO�������ֵ����ʱ�� */ +#define HI1823_SMAG_CFG_SMAG_RX_OK_PKT_0_REG \ + (HI1823_SMAG_CFG_BASE + 0x19C) /* SMAG ���յ��������ܱ���������������FIFO����������ı��ļ�������Ϊ�쳣�ı��ģ� \ + */ +#define HI1823_SMAG_CFG_SMAG_RX_OK_PKT_1_REG \ + (HI1823_SMAG_CFG_BASE + 0x1A0) /* SMAG ���յ��������ܱ���������������FIFO����������ı��ļ�������Ϊ�쳣�ı��ģ� \ + */ +#define HI1823_SMAG_CFG_SMAG_RX_OK_PKT_2_REG \ + (HI1823_SMAG_CFG_BASE + 0x1A4) /* SMAG ���յ��������ܱ���������������FIFO����������ı��ļ�������Ϊ�쳣�ı��ģ� \ + */ +#define HI1823_SMAG_CFG_SMAG_RX_OK_PKT_3_REG \ + (HI1823_SMAG_CFG_BASE + 0x1A8) /* SMAG ���յ��������ܱ���������������FIFO����������ı��ļ�������Ϊ�쳣�ı��ģ� \ + */ +#define HI1823_SMAG_CFG_SMAG_RX_DROP_PKT_0_REG (HI1823_SMAG_CFG_BASE + 0x1AC) /* SMAG���յ��ĵ����쳣�����ı��� */ +#define HI1823_SMAG_CFG_SMAG_RX_DROP_PKT_1_REG (HI1823_SMAG_CFG_BASE + 0x1B0) /* SMAG���յ��ĵ����쳣�����ı��� */ +#define HI1823_SMAG_CFG_SMAG_RX_DROP_PKT_2_REG (HI1823_SMAG_CFG_BASE + 0x1B4) /* SMAG���յ��ĵ����쳣�����ı��� */ +#define HI1823_SMAG_CFG_SMAG_RX_DROP_PKT_3_REG (HI1823_SMAG_CFG_BASE + 0x1B8) /* SMAG���յ��ĵ����쳣�����ı��� */ +#define HI1823_SMAG_CFG_SMAG_IPSURX_OK_PKT_REG (HI1823_SMAG_CFG_BASE + 0x1BC) /* SMAG ���͸�IPSURX����/�쳣���ĸ��� */ +#define HI1823_SMAG_CFG_PE_SMAG_OK_PKT_REG (HI1823_SMAG_CFG_BASE + 0x1C0) /* SMAG TX���յ���PE��������/�쳣���ĸ��� */ +#define HI1823_SMAG_CFG_SMAG_TX_OK_PKT_0_REG \ + (HI1823_SMAG_CFG_BASE + 0x1C4) /* SMAG TX���͸�MAC IP������/�쳣�ܱ����������������첽FIFO�ı��ģ� */ +#define HI1823_SMAG_CFG_SMAG_TX_OK_PKT_1_REG \ + (HI1823_SMAG_CFG_BASE + 0x1C8) /* SMAG TX���͸�MAC IP������/�쳣�ܱ����������������첽FIFO�ı��ģ� */ +#define HI1823_SMAG_CFG_SMAG_TX_OK_PKT_2_REG \ + (HI1823_SMAG_CFG_BASE + 0x1CC) /* SMAG TX���͸�MAC IP������/�쳣�ܱ����������������첽FIFO�ı��ģ� */ +#define HI1823_SMAG_CFG_SMAG_TX_OK_PKT_3_REG \ + (HI1823_SMAG_CFG_BASE + 0x1D0) /* SMAG TX���͸�MAC IP������/�쳣�ܱ����������������첽FIFO�ı��ģ� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_FIFO_CNT0_REG (HI1823_SMAG_CFG_BASE + 0x1D4) /* SMAGģ��txdp��FIFO0~3 CNT�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_TXDP_FIFO_CNT1_REG (HI1823_SMAG_CFG_BASE + 0x1D8) /* SMAGģ��txdp��FIFO4~7 CNT�Ĵ��� */ +#define HI1823_SMAG_CFG_SMAG_BP_RTIME_REG (HI1823_SMAG_CFG_BASE + 0x1DC) /* SMAG�ⲿ�ӿڼ�����FIFOʵʱ��ѹ״̬ */ +#define HI1823_SMAG_CFG_SMAG_RX_COS_L_RTIME_REG \ + (HI1823_SMAG_CFG_BASE + 0x1E0) /* SMAG���յ���QU����COS[31:0]��ѹʵʱֵ */ +#define HI1823_SMAG_CFG_SMAG_RX_COS_H_RTIME_REG \ + (HI1823_SMAG_CFG_BASE + 0x1E4) /* SMAG���յ���QU����COS[63:32]��ѹʵʱֵ */ +#define HI1823_SMAG_CFG_SMAG_RX_SDS_COS_L_HISTORY_REG \ + (HI1823_SMAG_CFG_BASE + 0x1E8) /* SMAG���յ���SDS����COS[31:0]��ѹ��ʷֵ */ +#define HI1823_SMAG_CFG_SMAG_RX_SDS_COS_H_HISTORY_REG \ + (HI1823_SMAG_CFG_BASE + 0x1EC) /* SMAG���յ���SDS����COS[63:32]��ѹ��ʷֵ */ +#define HI1823_SMAG_CFG_SMAG_SDS_RX_COS_L_RTIME_REG \ + (HI1823_SMAG_CFG_BASE + 0x1F0) /* SMAG���յ���SDS����COS[31:0]��ѹʵʱֵ */ +#define HI1823_SMAG_CFG_SMAG_SDS_RX_COS_H_RTIME_REG \ + (HI1823_SMAG_CFG_BASE + 0x1F4) /* SMAG���յ���SDS����COS[63:32]��ѹʵʱֵ */ +#define HI1823_SMAG_CFG_SMAG_MFS_ADP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x1F8) /* MFS�����߼����üĴ��� */ +#define HI1823_SMAG_CFG_SMAG_IP_SEL_REG (HI1823_SMAG_CFG_BASE + 0x1FC) /* SMAG�ڲ�8��10GE AXI subsys������ѡ��Ĵ��� \ + */ +#define HI1823_SMAG_CFG_SMAG_LOOP4_CFG_REG (HI1823_SMAG_CFG_BASE + 0x200) /* LOOP4_MODE */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_CFG_REG (HI1823_SMAG_CFG_BASE + 0x204) /* LOOP5_MODE */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_CAPTURE_PACKET_REG (HI1823_SMAG_CFG_BASE + 0x208) /* SMAG TXץȡ����ʹ�����üĴ��� */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_0_REG (HI1823_SMAG_CFG_BASE + 0x210) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_1_REG (HI1823_SMAG_CFG_BASE + 0x214) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_2_REG (HI1823_SMAG_CFG_BASE + 0x218) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_3_REG (HI1823_SMAG_CFG_BASE + 0x21C) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_4_REG (HI1823_SMAG_CFG_BASE + 0x220) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_5_REG (HI1823_SMAG_CFG_BASE + 0x224) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_6_REG (HI1823_SMAG_CFG_BASE + 0x228) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP5_PORT_BPS_SHAPER_7_REG (HI1823_SMAG_CFG_BASE + 0x22C) /* */ +#define HI1823_SMAG_CFG_SMAG_LOOP6_CFG_REG (HI1823_SMAG_CFG_BASE + 0x230) /* LOOP6_MODE */ +#define HI1823_SMAG_CFG_SMAG_LOOP7_CFG_REG (HI1823_SMAG_CFG_BASE + 0x234) /* LOOP7_MODE */ +#define HI1823_SMAG_CFG_RXDP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x240) /* RXDP_PAUSE_DISC */ +#define HI1823_SMAG_CFG_RX_GBOX1_SFIFO_P7_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x280) /* */ +#define HI1823_SMAG_CFG_RX_GBOX1_SFIFO_P6_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x284) /* */ +#define HI1823_SMAG_CFG_RX_GBOX1_SFIFO_P5_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x288) /* */ +#define HI1823_SMAG_CFG_RX_GBOX1_SFIFO_P4_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x28C) /* */ +#define HI1823_SMAG_CFG_RX_GBOX0_SFIFO_P3_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x290) /* */ +#define HI1823_SMAG_CFG_RX_GBOX0_SFIFO_P2_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x294) /* */ +#define HI1823_SMAG_CFG_RX_GBOX0_SFIFO_P1_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x298) /* */ +#define HI1823_SMAG_CFG_RX_GBOX0_SFIFO_P0_CFG_STATUS_REG (HI1823_SMAG_CFG_BASE + 0x29C) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P7_REG (HI1823_SMAG_CFG_BASE + 0x320) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P6_REG (HI1823_SMAG_CFG_BASE + 0x324) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P5_REG (HI1823_SMAG_CFG_BASE + 0x328) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P4_REG (HI1823_SMAG_CFG_BASE + 0x32C) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P3_REG (HI1823_SMAG_CFG_BASE + 0x330) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P2_REG (HI1823_SMAG_CFG_BASE + 0x334) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P1_REG (HI1823_SMAG_CFG_BASE + 0x338) /* */ +#define HI1823_SMAG_CFG_TX_GBOX_MAC_IF_DFX_P0_REG (HI1823_SMAG_CFG_BASE + 0x33C) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P7_REG (HI1823_SMAG_CFG_BASE + 0x340) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P6_REG (HI1823_SMAG_CFG_BASE + 0x344) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P5_REG (HI1823_SMAG_CFG_BASE + 0x348) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P4_REG (HI1823_SMAG_CFG_BASE + 0x34C) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P3_REG (HI1823_SMAG_CFG_BASE + 0x350) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P2_REG (HI1823_SMAG_CFG_BASE + 0x354) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P1_REG (HI1823_SMAG_CFG_BASE + 0x358) /* */ +#define HI1823_SMAG_CFG_RX_GBOX_MAC_IF_DFX_P0_REG (HI1823_SMAG_CFG_BASE + 0x35C) /* */ +#define HI1823_SMAG_CFG_TX_P0_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x380) /* */ +#define HI1823_SMAG_CFG_TX_P1_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x384) /* */ +#define HI1823_SMAG_CFG_TX_P2_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x388) /* */ +#define HI1823_SMAG_CFG_TX_P3_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x38C) /* */ +#define HI1823_SMAG_CFG_TX_P4_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x390) /* */ +#define HI1823_SMAG_CFG_TX_P5_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x394) /* */ +#define HI1823_SMAG_CFG_TX_P6_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x398) /* */ +#define HI1823_SMAG_CFG_TX_P7_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x39C) /* */ +#define HI1823_SMAG_CFG_RX_P0_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3A0) /* */ +#define HI1823_SMAG_CFG_RX_P1_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3A4) /* */ +#define HI1823_SMAG_CFG_RX_P2_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3A8) /* */ +#define HI1823_SMAG_CFG_RX_P3_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3AC) /* */ +#define HI1823_SMAG_CFG_RX_P4_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3B0) /* */ +#define HI1823_SMAG_CFG_RX_P5_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3B4) /* */ +#define HI1823_SMAG_CFG_RX_P6_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3B8) /* */ +#define HI1823_SMAG_CFG_RX_P7_COS_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3BC) /* */ +#define HI1823_SMAG_CFG_SMAG_QU_BP_REMAP_CFG_REG (HI1823_SMAG_CFG_BASE + 0x3C0) /* */ + +/* MF_CTL */ +#define HI1823_MF_CTL_CFG_BASE (0x22110000) +#define HI1823_CSE_PORT_CRDT_CFG(port) (HI1823_MF_CTL_CFG_BASE + 0x100 + 0x4 * (port)) /* ͨ���������üĴ��� */ +#define HI1823_MFD_PORT_ENABLE_CFG_REG (HI1823_MF_CTL_CFG_BASE + 0x200) /* MFD�˿�ʹ��,15-8 enable 7-0 mag fc select */ +#define HI1823_MFS_CFG_REG (HI1823_MF_CTL_CFG_BASE + 0x300) /* MFSʱ϶���� */ + +#endif // SMAG_CFG_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/misc/sfc_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/misc/sfc_c_union_define.h new file mode 100644 index 000000000..652f0b4fe --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/misc/sfc_c_union_define.h @@ -0,0 +1,721 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : sfc_c_union_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : 项目描述信息 +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/21 16:59:29 Create file +// ****************************************************************************** + +#ifndef SFC_C_UNION_DEFINE_H +#define SFC_C_UNION_DEFINE_H + +/* Define the union csr_global_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mode : 1; /* [0] */ + u32 wp_en : 1; /* [1] */ + u32 flash_cs0_addr_mode : 1; /* [2] */ + u32 rd_delay : 2; /* [4:3] */ + u32 flash_cs1_addr_mode : 1; /* [5] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_global_config_u; + +/* Define the union csr_timing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tshsl : 4; /* [3:0] */ + u32 rsv_1 : 4; /* [7:4] */ + u32 tcss : 3; /* [10:8] */ + u32 rsv_2 : 1; /* [11] */ + u32 tcsh : 3; /* [14:12] */ + u32 rsv_3 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timing_u; + +/* Define the union csr_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_op_end_raw_status : 1; /* [0] */ + u32 dma_done_int_raw_status : 1; /* [1] */ + u32 pp_fail_int_raw_status : 1; /* [2] */ + u32 mem_ecc_fail_int_raw_status : 1; /* [3] */ + u32 mem_ecc_val_int_raw_status : 1; /* [4] */ + u32 sc_trig_raw_status : 1; /* [5] */ + u32 lock_timeout_raw_status : 1; /* [6] */ + u32 wait_wip_before_op_timeout_raw_status : 1; /* [7] */ + u32 lock_ahb_conflict_raw_status : 1; /* [8] */ + u32 rsv_4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_raw_status_u; + +/* Define the union csr_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_op_end_status : 1; /* [0] */ + u32 dma_done_int_status : 1; /* [1] */ + u32 pp_fail_int_status : 1; /* [2] */ + u32 mem_ecc_fail_int_status : 1; /* [3] */ + u32 mem_ecc_val_int_status : 1; /* [4] */ + u32 sc_trig_status : 1; /* [5] */ + u32 lock_timeout_status : 1; /* [6] */ + u32 wait_wip_before_op_timeout_status : 1; /* [7] */ + u32 lock_ahb_conflict_status : 1; /* [8] */ + u32 rsv_5 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_status_u; + +/* Define the union csr_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_op_end_int_mask : 1; /* [0] */ + u32 dma_done_int_mask : 1; /* [1] */ + u32 pp_fail_int_mask : 1; /* [2] */ + u32 mem_ecc_fail_int_mask : 1; /* [3] */ + u32 mem_ecc_val_int_mask : 1; /* [4] */ + u32 sc_trig_mask : 1; /* [5] */ + u32 lock_timeout_mask : 1; /* [6] */ + u32 wait_wip_before_op_timeout_mask : 1; /* [7] */ + u32 lock_ahb_conflict_mask : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_mask_u; + +/* Define the union csr_int_clear_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_op_end_int_clr : 1; /* [0] */ + u32 rsv_7 : 1; /* [1] */ + u32 pp_fail_int_clr : 1; /* [2] */ + u32 mem_ecc_fail_clr : 1; /* [3] */ + u32 mem_ecc_val_clr : 1; /* [4] */ + u32 sc_trig_clr : 1; /* [5] */ + u32 lock_timeout_clr : 1; /* [6] */ + u32 wait_wip_before_op_timeout_clr : 1; /* [7] */ + u32 lock_ahb_conflict_clr : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_clear_u; + +/* Define the union csr_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_version_u; + +/* Define the union csr_sys_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sys_version_u; + +/* Define the union csr_sys_version_lock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_version_lock : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sys_version_lock_u; + +/* Define the union csr_bus_config1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bus_rd_mem_if_type : 3; /* [2:0] */ + u32 bus_rd_dummy_bytes : 3; /* [5:3] */ + u32 bus_rd_prefetch_cnt : 2; /* [7:6] */ + u32 bus_rd_ins : 8; /* [15:8] */ + u32 bus_wr_mem_if_type : 3; /* [18:16] */ + u32 bus_wr_dummy_bytes : 3; /* [21:19] */ + u32 bus_wr_ins : 8; /* [29:22] */ + u32 bus_wr_enable : 1; /* [30] */ + u32 bus_rd_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bus_config1_u; + +/* Define the union csr_bus_config2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bus_wip_locate : 3; /* [2:0] */ + u32 rsv_10 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bus_config2_u; + +/* Define the union csr_bus_flash_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bus_flash_size_cs0 : 4; /* [3:0] */ + u32 rsv_11 : 4; /* [7:4] */ + u32 bus_flash_size_cs1 : 4; /* [11:8] */ + u32 rsv_12 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bus_flash_size_u; + +/* Define the union csr_bus_base_addr_cs0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 16; /* [15:0] */ + u32 bus_base_addr_high_cs0 : 14; /* [29:16] */ + u32 rsv_14 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bus_base_addr_cs0_u; + +/* Define the union csr_bus_base_addr_cs1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_15 : 16; /* [15:0] */ + u32 bus_base_addr_high_cs1 : 14; /* [29:16] */ + u32 rsv_16 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bus_base_addr_cs1_u; + +/* Define the union csr_pp_timing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pp_busy_time : 24; /* [23:0] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pp_timing_u; + +/* Define the union csr_cmd_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_start : 1; /* [0] */ + u32 cmd_sel_cs : 1; /* [1] */ + u32 rsv_18 : 1; /* [2] */ + u32 cmd_addr_en : 1; /* [3] */ + u32 cmd_dummy_byte_cnt : 3; /* [6:4] */ + u32 cmd_data_en : 1; /* [7] */ + u32 cmd_rw : 1; /* [8] */ + u32 cmd_data_cnt : 8; /* [16:9] */ + u32 cmd_mem_if_type : 3; /* [19:17] */ + u32 cmd_lock_flash : 1; /* [20] */ + u32 rsv_19 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmd_config_u; + +/* Define the union csr_cmd_ins_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_ins : 8; /* [7:0] */ + u32 rsv_20 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmd_ins_u; + +/* Define the union csr_cmd_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_addr : 30; /* [29:0] */ + u32 rsv_21 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmd_addr_u; + +/* Define the union csr_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ctrl : 24; /* [23:0] */ + u32 rsv_22 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_u; + +/* Define the union csr_mem_ecc_info1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_inval_muti_err : 1; /* [0] */ + u32 ecc_inval_err_syn : 5; /* [5:1] */ + u32 err_inval_addr : 9; /* [14:6] */ + u32 rsv_23 : 1; /* [15] */ + u32 ecc_val_err : 1; /* [16] */ + u32 ecc_val_err_syn : 5; /* [21:17] */ + u32 err_val_addr : 9; /* [30:22] */ + u32 rsv_24 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ecc_info1_u; + +/* Define the union csr_arb_wip_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arb_wip_timeout_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arb_wip_timeout_u; + +/* Define the union csr_arb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lock_timeout : 1; /* [0] */ + u32 lock_ahb_conflict : 1; /* [1] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arb_cfg_u; + +/* Define the union csr_arb_lock_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arb_lock_timeout_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arb_lock_timeout_cnt_u; + +/* Define the union csr_cmd_databuf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_databuf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmd_databuf_u; + +/* Define the union csr_sc_pro_saddrp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_26 : 12; /* [11:0] */ + u32 saddr : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_saddrp_u; + +/* Define the union csr_sc_pro_eaddrp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_27 : 12; /* [11:0] */ + u32 eaddr : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_eaddrp_u; + +/* Define the union csr_sc_pro_saf_cmd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saf_cmd0 : 8; /* [7:0] */ + u32 saf_cmd1 : 8; /* [15:8] */ + u32 saf_cmd2 : 8; /* [23:16] */ + u32 saf_cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_saf_cmd0_u; + +/* Define the union csr_sc_pro_saf_cmd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saf_1cmd0 : 8; /* [7:0] */ + u32 saf_1cmd1 : 8; /* [15:8] */ + u32 saf_1cmd2 : 8; /* [23:16] */ + u32 saf_1cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_saf_cmd1_u; + +/* Define the union csr_sc_pro_saf_cmd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saf_2cmd0 : 8; /* [7:0] */ + u32 saf_2cmd1 : 8; /* [15:8] */ + u32 saf_2cmd2 : 8; /* [23:16] */ + u32 saf_2cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_saf_cmd2_u; + +/* Define the union csr_sc_pro_saf_cmd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saf_3cmd0 : 8; /* [7:0] */ + u32 saf_3cmd1 : 8; /* [15:8] */ + u32 saf_3cmd2 : 8; /* [23:16] */ + u32 saf_3cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_saf_cmd3_u; + +/* Define the union csr_sc_pro_saf_cmd4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saf_4cmd0 : 8; /* [7:0] */ + u32 saf_4cmd1 : 8; /* [15:8] */ + u32 saf_4cmd2 : 8; /* [23:16] */ + u32 saf_4cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_pro_saf_cmd4_u; + +/* Define the union csr_sc_std_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 std_cmd0 : 8; /* [7:0] */ + u32 std_cmd1 : 8; /* [15:8] */ + u32 std_cmd2 : 8; /* [23:16] */ + u32 std_cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_std_cmd_u; + +/* Define the union csr_sc_dido_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 di_do_cmd0 : 8; /* [7:0] */ + u32 di_do_cmd1 : 8; /* [15:8] */ + u32 di_do_cmd2 : 8; /* [23:16] */ + u32 di_do_cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_dido_cmd_u; + +/* Define the union csr_sc_dio_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dio_cmd0 : 8; /* [7:0] */ + u32 dio_cmd1 : 8; /* [15:8] */ + u32 dio_cmd2 : 8; /* [23:16] */ + u32 dio_cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_dio_cmd_u; + +/* Define the union csr_sc_qiqo_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qi_qo_cmd0 : 8; /* [7:0] */ + u32 qi_qo_cmd1 : 8; /* [15:8] */ + u32 qi_qo_cmd2 : 8; /* [23:16] */ + u32 qi_qo_cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_qiqo_cmd_u; + +/* Define the union csr_sc_qio_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qio_cmd0 : 8; /* [7:0] */ + u32 qio_cmd1 : 8; /* [15:8] */ + u32 qio_cmd2 : 8; /* [23:16] */ + u32 qio_cmd3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_qio_cmd_u; + +/* Define the union csr_sc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_en : 1; /* [0] */ + u32 lock_sc_reg : 1; /* [1] */ + u32 rsv_28 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_ctrl_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_global_config_u global_config; /* 100 */ + volatile csr_timing_u timing; /* 110 */ + volatile csr_int_raw_status_u int_raw_status; /* 120 */ + volatile csr_int_status_u int_status; /* 124 */ + volatile csr_int_mask_u int_mask; /* 128 */ + volatile csr_int_clear_u int_clear; /* 12C */ + volatile csr_version_u version; /* 1F8 */ + volatile csr_sys_version_u sys_version; /* 1FC */ + volatile csr_sys_version_lock_u sys_version_lock; /* FC */ + volatile csr_bus_config1_u bus_config1; /* 200 */ + volatile csr_bus_config2_u bus_config2; /* 204 */ + volatile csr_bus_flash_size_u bus_flash_size; /* 210 */ + volatile csr_bus_base_addr_cs0_u bus_base_addr_cs0; /* 214 */ + volatile csr_bus_base_addr_cs1_u bus_base_addr_cs1; /* 218 */ + volatile csr_pp_timing_u pp_timing; /* 254 */ + volatile csr_cmd_config_u cmd_config; /* 300 */ + volatile csr_cmd_ins_u cmd_ins; /* 308 */ + volatile csr_cmd_addr_u cmd_addr; /* 30C */ + volatile csr_mem_ctrl_u mem_ctrl; /* 318 */ + volatile csr_mem_ecc_info1_u mem_ecc_info1; /* 320 */ + volatile csr_arb_wip_timeout_u arb_wip_timeout; /* 340 */ + volatile csr_arb_cfg_u arb_cfg; /* 344 */ + volatile csr_arb_lock_timeout_cnt_u arb_lock_timeout_cnt; /* 348 */ + volatile csr_cmd_databuf_u cmd_databuf[64]; /* 400 */ + volatile csr_sc_pro_saddrp_u sc_pro_saddrp[5]; /* 500 */ + volatile csr_sc_pro_eaddrp_u sc_pro_eaddrp[5]; /* 504 */ + volatile csr_sc_pro_saf_cmd0_u sc_pro_saf_cmd0; /* 530 */ + volatile csr_sc_pro_saf_cmd1_u sc_pro_saf_cmd1; /* 534 */ + volatile csr_sc_pro_saf_cmd2_u sc_pro_saf_cmd2; /* 538 */ + volatile csr_sc_pro_saf_cmd3_u sc_pro_saf_cmd3; /* 53C */ + volatile csr_sc_pro_saf_cmd4_u sc_pro_saf_cmd4; /* 540 */ + volatile csr_sc_std_cmd_u sc_std_cmd; /* 544 */ + volatile csr_sc_dido_cmd_u sc_dido_cmd; /* 548 */ + volatile csr_sc_dio_cmd_u sc_dio_cmd; /* 54C */ + volatile csr_sc_qiqo_cmd_u sc_qiqo_cmd; /* 550 */ + volatile csr_sc_qio_cmd_u sc_qio_cmd; /* 554 */ + volatile csr_sc_ctrl_u sc_ctrl; /* 558 */ +} S_sfc_REGS_TYPE; + +/* Declare the struct pointor of the module sfc */ +extern volatile S_sfc_REGS_TYPE *gopsfcAllReg; + +/* Declare the functions that set the member value */ +int iSetGLOBAL_CONFIG_mode(unsigned int umode); +int iSetGLOBAL_CONFIG_wp_en(unsigned int uwp_en); +int iSetGLOBAL_CONFIG_flash_cs0_addr_mode(unsigned int uflash_cs0_addr_mode); +int iSetGLOBAL_CONFIG_rd_delay(unsigned int urd_delay); +int iSetGLOBAL_CONFIG_flash_cs1_addr_mode(unsigned int uflash_cs1_addr_mode); +int iSetTIMING_tshsl(unsigned int utshsl); +int iSetTIMING_tcss(unsigned int utcss); +int iSetTIMING_tcsh(unsigned int utcsh); +int iSetINT_RAW_STATUS_cmd_op_end_raw_status(unsigned int ucmd_op_end_raw_status); +int iSetINT_RAW_STATUS_dma_done_int_raw_status(unsigned int udma_done_int_raw_status); +int iSetINT_RAW_STATUS_pp_fail_int_raw_status(unsigned int upp_fail_int_raw_status); +int iSetINT_RAW_STATUS_mem_ecc_fail_int_raw_status(unsigned int umem_ecc_fail_int_raw_status); +int iSetINT_RAW_STATUS_mem_ecc_val_int_raw_status(unsigned int umem_ecc_val_int_raw_status); +int iSetINT_RAW_STATUS_sc_trig_raw_status(unsigned int usc_trig_raw_status); +int iSetINT_RAW_STATUS_lock_timeout_raw_status(unsigned int ulock_timeout_raw_status); +int iSetINT_RAW_STATUS_wait_wip_before_op_timeout_raw_status(unsigned int uwait_wip_before_op_timeout_raw_status); +int iSetINT_RAW_STATUS_lock_ahb_conflict_raw_status(unsigned int ulock_ahb_conflict_raw_status); +int iSetINT_STATUS_cmd_op_end_status(unsigned int ucmd_op_end_status); +int iSetINT_STATUS_dma_done_int_status(unsigned int udma_done_int_status); +int iSetINT_STATUS_pp_fail_int_status(unsigned int upp_fail_int_status); +int iSetINT_STATUS_mem_ecc_fail_int_status(unsigned int umem_ecc_fail_int_status); +int iSetINT_STATUS_mem_ecc_val_int_status(unsigned int umem_ecc_val_int_status); +int iSetINT_STATUS_sc_trig_status(unsigned int usc_trig_status); +int iSetINT_STATUS_lock_timeout_status(unsigned int ulock_timeout_status); +int iSetINT_STATUS_wait_wip_before_op_timeout_status(unsigned int uwait_wip_before_op_timeout_status); +int iSetINT_STATUS_lock_ahb_conflict_status(unsigned int ulock_ahb_conflict_status); +int iSetINT_MASK_cmd_op_end_int_mask(unsigned int ucmd_op_end_int_mask); +int iSetINT_MASK_dma_done_int_mask(unsigned int udma_done_int_mask); +int iSetINT_MASK_pp_fail_int_mask(unsigned int upp_fail_int_mask); +int iSetINT_MASK_mem_ecc_fail_int_mask(unsigned int umem_ecc_fail_int_mask); +int iSetINT_MASK_mem_ecc_val_int_mask(unsigned int umem_ecc_val_int_mask); +int iSetINT_MASK_sc_trig_mask(unsigned int usc_trig_mask); +int iSetINT_MASK_lock_timeout_mask(unsigned int ulock_timeout_mask); +int iSetINT_MASK_wait_wip_before_op_timeout_mask(unsigned int uwait_wip_before_op_timeout_mask); +int iSetINT_MASK_lock_ahb_conflict_mask(unsigned int ulock_ahb_conflict_mask); +int iSetINT_CLEAR_cmd_op_end_int_clr(unsigned int ucmd_op_end_int_clr); +int iSetINT_CLEAR_pp_fail_int_clr(unsigned int upp_fail_int_clr); +int iSetINT_CLEAR_mem_ecc_fail_clr(unsigned int umem_ecc_fail_clr); +int iSetINT_CLEAR_mem_ecc_val_clr(unsigned int umem_ecc_val_clr); +int iSetINT_CLEAR_sc_trig_clr(unsigned int usc_trig_clr); +int iSetINT_CLEAR_lock_timeout_clr(unsigned int ulock_timeout_clr); +int iSetINT_CLEAR_wait_wip_before_op_timeout_clr(unsigned int uwait_wip_before_op_timeout_clr); +int iSetINT_CLEAR_lock_ahb_conflict_clr(unsigned int ulock_ahb_conflict_clr); +int iSetVERSION_version(unsigned int uversion); +int iSetSYS_VERSION_sys_version(unsigned int usys_version); +int iSetSYS_VERSION_LOCK_sys_version_lock(unsigned int usys_version_lock); +int iSetBUS_CONFIG1_bus_rd_mem_if_type(unsigned int ubus_rd_mem_if_type); +int iSetBUS_CONFIG1_bus_rd_dummy_bytes(unsigned int ubus_rd_dummy_bytes); +int iSetBUS_CONFIG1_bus_rd_prefetch_cnt(unsigned int ubus_rd_prefetch_cnt); +int iSetBUS_CONFIG1_bus_rd_ins(unsigned int ubus_rd_ins); +int iSetBUS_CONFIG1_bus_wr_mem_if_type(unsigned int ubus_wr_mem_if_type); +int iSetBUS_CONFIG1_bus_wr_dummy_bytes(unsigned int ubus_wr_dummy_bytes); +int iSetBUS_CONFIG1_bus_wr_ins(unsigned int ubus_wr_ins); +int iSetBUS_CONFIG1_bus_wr_enable(unsigned int ubus_wr_enable); +int iSetBUS_CONFIG1_bus_rd_enable(unsigned int ubus_rd_enable); +int iSetBUS_CONFIG2_bus_wip_locate(unsigned int ubus_wip_locate); +int iSetBUS_FLASH_SIZE_bus_flash_size_cs0(unsigned int ubus_flash_size_cs0); +int iSetBUS_FLASH_SIZE_bus_flash_size_cs1(unsigned int ubus_flash_size_cs1); +int iSetBUS_BASE_ADDR_CS0_bus_base_addr_high_cs0(unsigned int ubus_base_addr_high_cs0); +int iSetBUS_BASE_ADDR_CS1_bus_base_addr_high_cs1(unsigned int ubus_base_addr_high_cs1); +int iSetPP_TIMING_pp_busy_time(unsigned int upp_busy_time); +int iSetCMD_CONFIG_cmd_start(unsigned int ucmd_start); +int iSetCMD_CONFIG_cmd_sel_cs(unsigned int ucmd_sel_cs); +int iSetCMD_CONFIG_cmd_addr_en(unsigned int ucmd_addr_en); +int iSetCMD_CONFIG_cmd_dummy_byte_cnt(unsigned int ucmd_dummy_byte_cnt); +int iSetCMD_CONFIG_cmd_data_en(unsigned int ucmd_data_en); +int iSetCMD_CONFIG_cmd_rw(unsigned int ucmd_rw); +int iSetCMD_CONFIG_cmd_data_cnt(unsigned int ucmd_data_cnt); +int iSetCMD_CONFIG_cmd_mem_if_type(unsigned int ucmd_mem_if_type); +int iSetCMD_CONFIG_cmd_lock_flash(unsigned int ucmd_lock_flash); +int iSetCMD_INS_cmd_ins(unsigned int ucmd_ins); +int iSetCMD_ADDR_cmd_addr(unsigned int ucmd_addr); +int iSetMEM_CTRL_mem_ctrl(unsigned int umem_ctrl); +int iSetMEM_ECC_INFO1_ecc_inval_muti_err(unsigned int uecc_inval_muti_err); +int iSetMEM_ECC_INFO1_ecc_inval_err_syn(unsigned int uecc_inval_err_syn); +int iSetMEM_ECC_INFO1_err_inval_addr(unsigned int uerr_inval_addr); +int iSetMEM_ECC_INFO1_ecc_val_err(unsigned int uecc_val_err); +int iSetMEM_ECC_INFO1_ecc_val_err_syn(unsigned int uecc_val_err_syn); +int iSetMEM_ECC_INFO1_err_val_addr(unsigned int uerr_val_addr); +int iSetARB_WIP_TIMEOUT_arb_wip_timeout_cnt(unsigned int uarb_wip_timeout_cnt); +int iSetARB_CFG_lock_timeout(unsigned int ulock_timeout); +int iSetARB_CFG_lock_ahb_conflict(unsigned int ulock_ahb_conflict); +int iSetARB_LOCK_TIMEOUT_CNT_arb_lock_timeout_cnt(unsigned int uarb_lock_timeout_cnt); +int iSetCMD_DATABUF_cmd_databuf(unsigned int ucmd_databuf); +int iSetSC_PRO_SADDRP_saddr(unsigned int usaddr); +int iSetSC_PRO_EADDRP_eaddr(unsigned int ueaddr); +int iSetSC_PRO_SAF_CMD0_saf_cmd0(unsigned int usaf_cmd0); +int iSetSC_PRO_SAF_CMD0_saf_cmd1(unsigned int usaf_cmd1); +int iSetSC_PRO_SAF_CMD0_saf_cmd2(unsigned int usaf_cmd2); +int iSetSC_PRO_SAF_CMD0_saf_cmd3(unsigned int usaf_cmd3); +int iSetSC_PRO_SAF_CMD1_saf_1cmd0(unsigned int usaf_1cmd0); +int iSetSC_PRO_SAF_CMD1_saf_1cmd1(unsigned int usaf_1cmd1); +int iSetSC_PRO_SAF_CMD1_saf_1cmd2(unsigned int usaf_1cmd2); +int iSetSC_PRO_SAF_CMD1_saf_1cmd3(unsigned int usaf_1cmd3); +int iSetSC_PRO_SAF_CMD2_saf_2cmd0(unsigned int usaf_2cmd0); +int iSetSC_PRO_SAF_CMD2_saf_2cmd1(unsigned int usaf_2cmd1); +int iSetSC_PRO_SAF_CMD2_saf_2cmd2(unsigned int usaf_2cmd2); +int iSetSC_PRO_SAF_CMD2_saf_2cmd3(unsigned int usaf_2cmd3); +int iSetSC_PRO_SAF_CMD3_saf_3cmd0(unsigned int usaf_3cmd0); +int iSetSC_PRO_SAF_CMD3_saf_3cmd1(unsigned int usaf_3cmd1); +int iSetSC_PRO_SAF_CMD3_saf_3cmd2(unsigned int usaf_3cmd2); +int iSetSC_PRO_SAF_CMD3_saf_3cmd3(unsigned int usaf_3cmd3); +int iSetSC_PRO_SAF_CMD4_saf_4cmd0(unsigned int usaf_4cmd0); +int iSetSC_PRO_SAF_CMD4_saf_4cmd1(unsigned int usaf_4cmd1); +int iSetSC_PRO_SAF_CMD4_saf_4cmd2(unsigned int usaf_4cmd2); +int iSetSC_PRO_SAF_CMD4_saf_4cmd3(unsigned int usaf_4cmd3); +int iSetSC_STD_CMD_std_cmd0(unsigned int ustd_cmd0); +int iSetSC_STD_CMD_std_cmd1(unsigned int ustd_cmd1); +int iSetSC_STD_CMD_std_cmd2(unsigned int ustd_cmd2); +int iSetSC_STD_CMD_std_cmd3(unsigned int ustd_cmd3); +int iSetSC_DIDO_CMD_di_do_cmd0(unsigned int udi_do_cmd0); +int iSetSC_DIDO_CMD_di_do_cmd1(unsigned int udi_do_cmd1); +int iSetSC_DIDO_CMD_di_do_cmd2(unsigned int udi_do_cmd2); +int iSetSC_DIDO_CMD_di_do_cmd3(unsigned int udi_do_cmd3); +int iSetSC_DIO_CMD_dio_cmd0(unsigned int udio_cmd0); +int iSetSC_DIO_CMD_dio_cmd1(unsigned int udio_cmd1); +int iSetSC_DIO_CMD_dio_cmd2(unsigned int udio_cmd2); +int iSetSC_DIO_CMD_dio_cmd3(unsigned int udio_cmd3); +int iSetSC_QIQO_CMD_qi_qo_cmd0(unsigned int uqi_qo_cmd0); +int iSetSC_QIQO_CMD_qi_qo_cmd1(unsigned int uqi_qo_cmd1); +int iSetSC_QIQO_CMD_qi_qo_cmd2(unsigned int uqi_qo_cmd2); +int iSetSC_QIQO_CMD_qi_qo_cmd3(unsigned int uqi_qo_cmd3); +int iSetSC_QIO_CMD_qio_cmd0(unsigned int uqio_cmd0); +int iSetSC_QIO_CMD_qio_cmd1(unsigned int uqio_cmd1); +int iSetSC_QIO_CMD_qio_cmd2(unsigned int uqio_cmd2); +int iSetSC_QIO_CMD_qio_cmd3(unsigned int uqio_cmd3); +int iSetSC_CTRL_sc_en(unsigned int usc_en); +int iSetSC_CTRL_lock_sc_reg(unsigned int ulock_sc_reg); + + +#endif // SFC_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/misc/sfc_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/misc/sfc_reg_offset.h new file mode 100644 index 000000000..0abcca3d6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/misc/sfc_reg_offset.h @@ -0,0 +1,217 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : sfc_reg_offset.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : 项目描述信息 +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/21 16:59:29 Create file +// ****************************************************************************** + +#ifndef SFC_REG_OFFSET_H +#define SFC_REG_OFFSET_H + +/* SFC2 Base address of Module's Register */ +#define CSR_SFC_BASE (0x236000000) + +/* **************************************************************************** */ +/* SFC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SFC_GLOBAL_CONFIG_REG \ + (CSR_SFC_BASE + 0x100) /* 全局配置寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_TIMING_REG (CSR_SFC_BASE + 0x110) /* Timing配置寄存器。（只有IMU可配置） */ +#define CSR_SFC_INT_RAW_STATUS_REG (CSR_SFC_BASE + 0x120) /* 中断原始状态寄存器。（AP M7 IMU分别独立） */ +#define CSR_SFC_INT_STATUS_REG (CSR_SFC_BASE + 0x124) /* 经过屏蔽处理的中断状态寄存器。（AP M7 IMU分别独立） */ +#define CSR_SFC_INT_MASK_REG (CSR_SFC_BASE + 0x128) /* 中断屏蔽寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_INT_CLEAR_REG (CSR_SFC_BASE + 0x12C) /* 中断清除寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_VERSION_REG (CSR_SFC_BASE + 0x1F8) /* 版本寄存器。 */ +#define CSR_SFC_SYS_VERSION_REG (CSR_SFC_BASE + 0x1FC) /* 系统版本寄存器。 */ +#define CSR_SFC_SYS_VERSION_LOCK_REG (CSR_SFC_BASE + 0xFC) /* 系统版本寄存器锁定寄存器。 */ +#define CSR_SFC_BUS_CONFIG1_REG \ + (CSR_SFC_BASE + 0x200) /* 总线操作方式配置寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_BUS_CONFIG2_REG \ + (CSR_SFC_BASE + 0x204) /* 总线操作方式配置寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_BUS_FLASH_SIZE_REG \ + (CSR_SFC_BASE + 0x210) /* 总线操作方式映射尺寸寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_BUS_BASE_ADDR_CS0_REG \ + (CSR_SFC_BASE + 0x214) /* 总线操作方式片选0映射基地址寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_BUS_BASE_ADDR_CS1_REG \ + (CSR_SFC_BASE + 0x218) /* 总线操作方式片选1映射基地址寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_PP_TIMING_REG (CSR_SFC_BASE + 0x254) /* 编程时间寄存器。（只有IMU可配置） */ +#define CSR_SFC_CMD_CONFIG_REG (CSR_SFC_BASE + 0x300) /* 命令操作方式配置寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_INS_REG (CSR_SFC_BASE + 0x308) /* 命令操作方式指令寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_ADDR_REG (CSR_SFC_BASE + 0x30C) /* 命令操作方式地址寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_MEM_CTRL_REG (CSR_SFC_BASE + 0x318) /* 例化mem管理配置寄存器。（只有IMU可配置） */ +#define CSR_SFC_MEM_ECC_INFO1_REG (CSR_SFC_BASE + 0x320) /* memoryECC纠错信息寄存器。 */ +#define CSR_SFC_ARB_WIP_TIMEOUT_REG \ + (CSR_SFC_BASE + 0x340) /* 获得仲裁后轮询WIP位超时时间配置寄存器。（只有IMU可配置） */ +#define CSR_SFC_ARB_CFG_REG (CSR_SFC_BASE + 0x344) /* 仲裁控制状态寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_ARB_LOCK_TIMEOUT_CNT_REG \ + (CSR_SFC_BASE + 0x348) /* flash控制权锁定超时时间配置寄存器。（只有IMU可配置） */ +#define CSR_SFC_CMD_DATABUF_0_REG (CSR_SFC_BASE + 0x400) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_1_REG (CSR_SFC_BASE + 0x404) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_2_REG (CSR_SFC_BASE + 0x408) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_3_REG (CSR_SFC_BASE + 0x40C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_4_REG (CSR_SFC_BASE + 0x410) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_5_REG (CSR_SFC_BASE + 0x414) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_6_REG (CSR_SFC_BASE + 0x418) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_7_REG (CSR_SFC_BASE + 0x41C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_8_REG (CSR_SFC_BASE + 0x420) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_9_REG (CSR_SFC_BASE + 0x424) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） */ +#define CSR_SFC_CMD_DATABUF_10_REG (CSR_SFC_BASE + 0x428) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_11_REG (CSR_SFC_BASE + 0x42C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_12_REG (CSR_SFC_BASE + 0x430) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_13_REG (CSR_SFC_BASE + 0x434) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_14_REG (CSR_SFC_BASE + 0x438) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_15_REG (CSR_SFC_BASE + 0x43C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_16_REG (CSR_SFC_BASE + 0x440) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_17_REG (CSR_SFC_BASE + 0x444) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_18_REG (CSR_SFC_BASE + 0x448) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_19_REG (CSR_SFC_BASE + 0x44C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_20_REG (CSR_SFC_BASE + 0x450) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_21_REG (CSR_SFC_BASE + 0x454) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_22_REG (CSR_SFC_BASE + 0x458) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_23_REG (CSR_SFC_BASE + 0x45C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_24_REG (CSR_SFC_BASE + 0x460) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_25_REG (CSR_SFC_BASE + 0x464) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_26_REG (CSR_SFC_BASE + 0x468) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_27_REG (CSR_SFC_BASE + 0x46C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_28_REG (CSR_SFC_BASE + 0x470) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_29_REG (CSR_SFC_BASE + 0x474) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_30_REG (CSR_SFC_BASE + 0x478) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_31_REG (CSR_SFC_BASE + 0x47C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_32_REG (CSR_SFC_BASE + 0x480) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_33_REG (CSR_SFC_BASE + 0x484) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_34_REG (CSR_SFC_BASE + 0x488) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_35_REG (CSR_SFC_BASE + 0x48C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_36_REG (CSR_SFC_BASE + 0x490) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_37_REG (CSR_SFC_BASE + 0x494) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_38_REG (CSR_SFC_BASE + 0x498) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_39_REG (CSR_SFC_BASE + 0x49C) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_40_REG (CSR_SFC_BASE + 0x4A0) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_41_REG (CSR_SFC_BASE + 0x4A4) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_42_REG (CSR_SFC_BASE + 0x4A8) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_43_REG (CSR_SFC_BASE + 0x4AC) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_44_REG (CSR_SFC_BASE + 0x4B0) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_45_REG (CSR_SFC_BASE + 0x4B4) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_46_REG (CSR_SFC_BASE + 0x4B8) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_47_REG (CSR_SFC_BASE + 0x4BC) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_48_REG (CSR_SFC_BASE + 0x4C0) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_49_REG (CSR_SFC_BASE + 0x4C4) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_50_REG (CSR_SFC_BASE + 0x4C8) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_51_REG (CSR_SFC_BASE + 0x4CC) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_52_REG (CSR_SFC_BASE + 0x4D0) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_53_REG (CSR_SFC_BASE + 0x4D4) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_54_REG (CSR_SFC_BASE + 0x4D8) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_55_REG (CSR_SFC_BASE + 0x4DC) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_56_REG (CSR_SFC_BASE + 0x4E0) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_57_REG (CSR_SFC_BASE + 0x4E4) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_58_REG (CSR_SFC_BASE + 0x4E8) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_59_REG (CSR_SFC_BASE + 0x4EC) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_60_REG (CSR_SFC_BASE + 0x4F0) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_61_REG (CSR_SFC_BASE + 0x4F4) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_62_REG (CSR_SFC_BASE + 0x4F8) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_CMD_DATABUF_63_REG (CSR_SFC_BASE + 0x4FC) /* 命令操作方式数据Buffer寄存器。（AP M7 IMU分别单独配置） \ + */ +#define CSR_SFC_SC_PRO_SADDRP_0_REG \ + (CSR_SFC_BASE + 0x500) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SADDRP_1_REG \ + (CSR_SFC_BASE + 0x508) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SADDRP_2_REG \ + (CSR_SFC_BASE + 0x510) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SADDRP_3_REG \ + (CSR_SFC_BASE + 0x518) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SADDRP_4_REG \ + (CSR_SFC_BASE + 0x520) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_EADDRP_0_REG \ + (CSR_SFC_BASE + 0x504) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_EADDRP_1_REG \ + (CSR_SFC_BASE + 0x50C) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_EADDRP_2_REG \ + (CSR_SFC_BASE + 0x514) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_EADDRP_3_REG \ + (CSR_SFC_BASE + 0x51C) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_EADDRP_4_REG \ + (CSR_SFC_BASE + 0x524) /* 第p段安全地址信息寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SAF_CMD0_REG \ + (CSR_SFC_BASE + 0x530) /* 安全命令白名单0寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SAF_CMD1_REG \ + (CSR_SFC_BASE + 0x534) /* 安全命令白名单1寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SAF_CMD2_REG \ + (CSR_SFC_BASE + 0x538) /* 安全命令白名单2寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SAF_CMD3_REG \ + (CSR_SFC_BASE + 0x53C) /* 安全命令白名单3寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_PRO_SAF_CMD4_REG \ + (CSR_SFC_BASE + 0x540) /* 安全命令白名单4寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_STD_CMD_REG \ + (CSR_SFC_BASE + 0x544) /* Standard接口类型的命令白名单0寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） \ + */ +#define CSR_SFC_SC_DIDO_CMD_REG \ + (CSR_SFC_BASE + 0x548) /* DI_DO接口类型的命令白名单寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_DIO_CMD_REG \ + (CSR_SFC_BASE + 0x54C) /* DIO接口类型的命令白名单寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_QIQO_CMD_REG \ + (CSR_SFC_BASE + 0x550) /* DI_DO接口类型的命令白名单寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_QIO_CMD_REG \ + (CSR_SFC_BASE + 0x554) /* QIO接口类型的命令白名单寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ +#define CSR_SFC_SC_CTRL_REG \ + (CSR_SFC_BASE + 0x558) /* 安全模式控制寄存器寄存器。（只有IMU可配置，安全锁定使能后该寄存器不可配置） */ + +#endif // SFC_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/c_union_define_crg.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/c_union_define_crg.h new file mode 100644 index 000000000..440a93907 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/c_union_define_crg.h @@ -0,0 +1,625 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2016, Hisilicon Technologies Co. Ltd. +// File name : c_union_define_CRG.h +// Project line : IT Product Line +// Department : ICT Processor Chipset Development Department +// Version : V100 +// Date : 2014/5/8 +// Description : The description of xxx project +// Others : Generated automatically by nManager V4.0.2.5 +// History : 2016/08/17 15:16:31 Create file +// ****************************************************************************** + +#ifndef C_UNION_DEFINE_CRG_H +#define C_UNION_DEFINE_CRG_H + +/* Define the union u_crg_pll_cfg0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll0_frac : 24; /* [23..0] */ + unsigned int pll0_fout4phasepd : 1; /* [24] */ + unsigned int pll0_foutvcopd : 1; /* [25] */ + unsigned int pll0_foutpostdivpd : 1; /* [26] */ + unsigned int pll0_dsmpd : 1; /* [27] */ + unsigned int pll0_dacpd : 1; /* [28] */ + unsigned int pll0_bypass : 1; /* [29] */ + unsigned int pll0_pd : 1; /* [30] */ + unsigned int pll0_dbg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_cfg0; + +/* Define the union u_crg_pll_cfg1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll1_frac : 24; /* [23..0] */ + unsigned int pll1_fout4phasepd : 1; /* [24] */ + unsigned int pll1_foutvcopd : 1; /* [25] */ + unsigned int pll1_foutpostdivpd : 1; /* [26] */ + unsigned int pll1_dsmpd : 1; /* [27] */ + unsigned int pll1_dacpd : 1; /* [28] */ + unsigned int pll1_bypass : 1; /* [29] */ + unsigned int pll1_pd : 1; /* [30] */ + unsigned int pll1_dbg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_cfg1; + +/* Define the union u_crg_pll_cfg2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll2_frac : 24; /* [23..0] */ + unsigned int pll2_fout4phasepd : 1; /* [24] */ + unsigned int pll2_foutvcopd : 1; /* [25] */ + unsigned int pll2_foutpostdivpd : 1; /* [26] */ + unsigned int pll2_dsmpd : 1; /* [27] */ + unsigned int pll2_dacpd : 1; /* [28] */ + unsigned int pll2_bypass : 1; /* [29] */ + unsigned int pll2_pd : 1; /* [30] */ + unsigned int pll2_dbg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_cfg2; + +/* Define the union u_crg_pll_cfg3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll3_frac : 24; /* [23..0] */ + unsigned int pll3_fout4phasepd : 1; /* [24] */ + unsigned int pll3_foutvcopd : 1; /* [25] */ + unsigned int pll3_foutpostdivpd : 1; /* [26] */ + unsigned int pll3_dsmpd : 1; /* [27] */ + unsigned int pll3_dacpd : 1; /* [28] */ + unsigned int pll3_bypass : 1; /* [29] */ + unsigned int pll3_pd : 1; /* [30] */ + unsigned int pll3_dbg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_cfg3; + +/* Define the union u_crg_pll_cfg4 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll4_frac : 24; /* [23..0] */ + unsigned int pll4_fout4phasepd : 1; /* [24] */ + unsigned int pll4_foutvcopd : 1; /* [25] */ + unsigned int pll4_foutpostdivpd : 1; /* [26] */ + unsigned int pll4_dsmpd : 1; /* [27] */ + unsigned int pll4_dacpd : 1; /* [28] */ + unsigned int pll4_bypass : 1; /* [29] */ + unsigned int pll4_pd : 1; /* [30] */ + unsigned int pll4_dbg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_cfg4; + +/* Define the union u_crg_pll_cfg5 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll5_frac : 24; /* [23..0] */ + unsigned int pll5_fout4phasepd : 1; /* [24] */ + unsigned int pll5_foutvcopd : 1; /* [25] */ + unsigned int pll5_foutpostdivpd : 1; /* [26] */ + unsigned int pll5_dsmpd : 1; /* [27] */ + unsigned int pll5_dacpd : 1; /* [28] */ + unsigned int pll5_bypass : 1; /* [29] */ + unsigned int pll5_pd : 1; /* [30] */ + unsigned int pll5_dbg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_cfg5; + +/* Define the union u_crg_pll_div0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll0_fbdiv : 12; /* [11..0] */ + unsigned int pll0_refdiv : 6; /* [17..12] */ + unsigned int pll0_postdiv2 : 3; /* [20..18] */ + unsigned int pll0_postdiv1 : 3; /* [23..21] */ + unsigned int pll0_acg_enable : 1; /* [24] */ + unsigned int pll0_acg_update : 1; /* [25] */ + unsigned int reserved_0 : 6; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_div0; + +/* Define the union u_crg_pll_div1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll1_fbdiv : 12; /* [11..0] */ + unsigned int pll1_refdiv : 6; /* [17..12] */ + unsigned int pll1_postdiv2 : 3; /* [20..18] */ + unsigned int pll1_postdiv1 : 3; /* [23..21] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_div1; + +/* Define the union u_crg_pll_div2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll2_fbdiv : 12; /* [11..0] */ + unsigned int pll2_refdiv : 6; /* [17..12] */ + unsigned int pll2_postdiv2 : 3; /* [20..18] */ + unsigned int pll2_postdiv1 : 3; /* [23..21] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_div2; + +/* Define the union u_crg_pll_div3 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll3_fbdiv : 12; /* [11..0] */ + unsigned int pll3_refdiv : 6; /* [17..12] */ + unsigned int pll3_postdiv2 : 3; /* [20..18] */ + unsigned int pll3_postdiv1 : 3; /* [23..21] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_div3; + +/* Define the union u_crg_pll_div4 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll4_fbdiv : 12; /* [11..0] */ + unsigned int pll4_refdiv : 6; /* [17..12] */ + unsigned int pll4_postdiv2 : 3; /* [20..18] */ + unsigned int pll4_postdiv1 : 3; /* [23..21] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_div4; + +/* Define the union u_crg_pll_div5 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll5_fbdiv : 12; /* [11..0] */ + unsigned int pll5_refdiv : 6; /* [17..12] */ + unsigned int pll5_postdiv2 : 3; /* [20..18] */ + unsigned int pll5_postdiv1 : 3; /* [23..21] */ + unsigned int reserved_0 : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pll_div5; + +/* Define the union u_crg_sys_clk_cfg0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int dp_clk_sel : 1; /* [0] */ + unsigned int up_clk_sel : 1; /* [1] */ + unsigned int cp_clk_sel : 1; /* [2] */ + unsigned int ahb_clk_sel : 1; /* [3] */ + unsigned int apb_clk_sel : 1; /* [4] */ + unsigned int sfc_clk_sel : 1; /* [5] */ + unsigned int itf_clk_sel : 1; /* [6] */ + unsigned int ncsi_mac_clk_sel : 1; /* [7] */ + unsigned int mag_an_clk_sel : 1; /* [8] */ + unsigned int lcam_clk_sel : 1; /* [9] */ + unsigned int fic_ref_clk_sel : 1; /* [10] */ + unsigned int reserved_0 : 21; /* [31..11] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_clk_cfg0; + +/* Define the union u_crg_sys_clk_en0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int lcam_clk_en : 5; /* [4..0] */ + unsigned int cp_clk_en : 1; /* [5] */ + unsigned int dp_clk_en : 1; /* [6] */ + unsigned int dcip_clk_en : 1; /* [7] */ + unsigned int itf_clk_en : 1; /* [8] */ + unsigned int lcam_common_clk_en : 1; /* [9] */ + unsigned int arm_clk_en : 1; /* [10] */ + unsigned int mag_dp_clk_en : 1; /* [11] */ + unsigned int fic_dp_clk_en : 1; /* [12] */ + unsigned int sys_spi_clk_en : 1; /* [13] */ + unsigned int sys_pie_clk_en : 1; /* [14] */ + unsigned int sys_ncsi_clk_en : 1; /* [15] */ + unsigned int sml1_clk_en : 1; /* [16] */ + unsigned int sml0_clk_en : 1; /* [17] */ + unsigned int ckd_clk_en : 1; /* [18] */ + unsigned int fic_ref_clk_en : 1; /* [19] */ + unsigned int fic_sync_clk_en : 1; /* [20] */ + unsigned int mag_cfg_clk_en : 1; /* [21] */ + unsigned int mag_ptp_clk_en : 1; /* [22] */ + unsigned int fic_cp_clk_en : 1; /* [23] */ + unsigned int fic_cfg_clk_en : 1; /* [24] */ + unsigned int pcie_pcs_apb_clk_en : 1; /* [25] */ + unsigned int pcie_sw_apb_clk_en : 1; /* [26] */ + unsigned int pcie_core_apb_clk_en : 1; /* [27] */ + unsigned int iocfg_apb_clk_en : 1; /* [28] */ + unsigned int pcie_sw_dev_clk_en : 1; /* [29] */ + unsigned int pcie_pcs_local_clk_en : 1; /* [30] */ + unsigned int reserved_0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_clk_en0; + +/* Define the union u_crg_sys_rst_req0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int lcam_rst_req : 5; /* [4..0] */ + unsigned int cp_rst_req : 1; /* [5] */ + unsigned int dp_rst_req : 1; /* [6] */ + unsigned int dcip_rst_req : 1; /* [7] */ + unsigned int itf_rst_req : 1; /* [8] */ + unsigned int lcam_common_rst_req : 1; /* [9] */ + unsigned int reserved_0 : 1; /* [10] */ + unsigned int mag_dp_rst_req : 1; /* [11] */ + unsigned int fic_dp_rst_req : 1; /* [12] */ + unsigned int sys_spi_rst_req : 1; /* [13] */ + unsigned int sys_pie_rst_req : 1; /* [14] */ + unsigned int sys_ncsi_rst_req : 1; /* [15] */ + unsigned int sml1_rst_req : 1; /* [16] */ + unsigned int sml0_rst_req : 1; /* [17] */ + unsigned int ckd_rst_req : 1; /* [18] */ + unsigned int fic_ref_rst_req : 1; /* [19] */ + unsigned int fic_sync_rst_req : 1; /* [20] */ + unsigned int mag_cfg_rst_req : 1; /* [21] */ + unsigned int reserved_1 : 1; /* [22] */ + unsigned int fic_cp_rst_req : 1; /* [23] */ + unsigned int fic_cfg_rst_req : 1; /* [24] */ + unsigned int pcie_pcs_apb_rst_req : 1; /* [25] */ + unsigned int pcie_sw_apb_rst_req : 1; /* [26] */ + unsigned int pcie_core_apb_rst_req : 1; /* [27] */ + unsigned int iocfg_apb_rst_req : 1; /* [28] */ + unsigned int pcie_sw_dev_rst_req : 1; /* [29] */ + unsigned int reserved_2 : 1; /* [30] */ + unsigned int mag_rst_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_rst_req0; + +/* Define the union u_crg_sys_clk_cfg1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int sfc_clk_div : 5; /* [4..0] */ + unsigned int up_clk_cfg : 1; /* [5] */ + unsigned int dp_clk_cfg : 1; /* [6] */ + unsigned int cp_clk_cfg : 1; /* [7] */ + unsigned int lcam_clk_div : 4; /* [11..8] */ + unsigned int fmag_rcd0_pd : 1; /* [12] */ + unsigned int fmag_rcd0_drv : 3; /* [15..13] */ + unsigned int fmag_rcd1_pd : 1; /* [16] */ + unsigned int fmag_rcd1_drv : 3; /* [19..17] */ + unsigned int ckd_clk_sel : 2; /* [21..20] */ + unsigned int fic_sync_clk_cfg : 2; /* [23..22] */ + unsigned int mbist_fun_clk_div : 8; /* [31..24] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_clk_cfg1; + +/* Define the union u_crg_sys_clk_en1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int i2c_clk_en : 5; /* [4..0] */ + unsigned int led_clk_en : 1; /* [5] */ + unsigned int temp_clk_en : 1; /* [6] */ + unsigned int apb2ff_clk_en : 1; /* [7] */ + unsigned int mdio_clk_en : 5; /* [12..8] */ + unsigned int avs_clk_en : 1; /* [13] */ + unsigned int smb_clk_en : 1; /* [14] */ + unsigned int uart_clk_en : 1; /* [15] */ + unsigned int gpio_clk_en : 4; /* [19..16] */ + unsigned int smeg_clk_en : 4; /* [23..20] */ + unsigned int fmag_ahb_clk_en : 1; /* [24] */ + unsigned int pcie_ahb_clk_en : 1; /* [25] */ + unsigned int ncsi_mac_clk_en : 1; /* [26] */ + unsigned int reserved_0 : 1; /* [27] */ + unsigned int ncsi_clk_en : 1; /* [28] */ + unsigned int tile0_clk_en : 1; /* [29] */ + unsigned int tile1_clk_en : 1; /* [30] */ + unsigned int smf_clk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_clk_en1; + +/* Define the union u_crg_sys_rst_req1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int i2c_rst_req : 5; /* [4..0] */ + unsigned int led_rst_req : 1; /* [5] */ + unsigned int reserved_0 : 1; /* [6] */ + unsigned int apb2ff_rst_req : 1; /* [7] */ + unsigned int mdio_rst_req : 5; /* [12..8] */ + unsigned int avs_rst_req : 1; /* [13] */ + unsigned int smb_rst_req : 1; /* [14] */ + unsigned int uart_rst_req : 1; /* [15] */ + unsigned int gpio_rst_req : 4; /* [19..16] */ + unsigned int smeg_rst_req : 4; /* [23..20] */ + unsigned int reserved_1 : 1; /* [24] */ + unsigned int reserved_2 : 1; /* [25] */ + unsigned int ncsi_mac_rst_req : 1; /* [26] */ + unsigned int spi_rst_req : 1; /* [27] */ + unsigned int ncsi_rst_req : 1; /* [28] */ + unsigned int tile0_rst_req : 1; /* [29] */ + unsigned int tile1_rst_req : 1; /* [30] */ + unsigned int smf_rst_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_rst_req1; + +/* Define the union u_crg_sys_clk_en2 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int cpi_itf_clk_en : 1; /* [0] */ + unsigned int mqm_itf_clk_en : 1; /* [1] */ + unsigned int reserved_0 : 30; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_sys_clk_en2; + +/* Define the union u_crg_pcie_hilink_rst */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pcie_grstb_rst_req : 4; /* [3..0] */ + unsigned int pcie_ahb_rst_req : 4; /* [7..4] */ + unsigned int pcie_perstn_enable : 4; /* [11..8] */ + unsigned int pcie_perstn_clear : 4; /* [15..12] */ + unsigned int reserved_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pcie_hilink_rst; + +/* Define the union u_crg_pcie_clk_cfg0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pcie_mclk_div_rst_req : 4; /* [3..0] */ + unsigned int reserved_0 : 28; /* [31..4] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pcie_clk_cfg0; + +/* Define the union u_crg_pcie_clk_en0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pcie_lane_clk_en : 16; /* [15..0] */ + unsigned int reserved_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pcie_clk_en0; + +/* Define the union u_crg_pcie_rst_req0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pcie_lane_rst_req : 16; /* [15..0] */ + unsigned int pcie_sticky_rst_req : 4; /* [19..16] */ + unsigned int pcie_port_rst_req : 4; /* [23..20] */ + unsigned int pcie_pcs_sft_rst_req : 1; /* [24] */ + unsigned int pcie_sft_rst_req : 1; /* [25] */ + unsigned int reserved_0 : 6; /* [31..26] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pcie_rst_req0; + +/* Define the union u_crg_pcie_obs_cfg */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pcie_obs_clk_sel : 5; /* [4..0] */ + unsigned int pcie_obs_rst_req : 1; /* [5] */ + unsigned int pcie_probe_rst_req : 1; /* [6] */ + unsigned int reserved_0 : 25; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_pcie_obs_cfg; + +/* Define the union u_crg_status0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int pll_lock : 6; /* [5..0] */ + unsigned int pll_loss_lock : 6; /* [11..6] */ + unsigned int reserved_0 : 20; /* [31..12] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_status0; + +/* Define the union u_crg_top_obs_cfg */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int top_obs_clk_sel : 5; /* [4..0] */ + unsigned int top_obs_rst_req : 1; /* [5] */ + unsigned int pll_probe_rst_req : 1; /* [6] */ + unsigned int reserved_0 : 25; /* [31..7] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_top_obs_cfg; + +/* Define the union u_crg_wdg_ctrl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int wdg_en : 1; /* [0] */ + unsigned int wdg_rst_req : 1; /* [1] */ + unsigned int reserved_0 : 30; /* [31..2] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_wdg_ctrl; + +/* Define the union u_crg_wdg_clr_dly */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int wdg_clr_dly : 27; /* [26..0] */ + unsigned int reserved_0 : 5; /* [31..27] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_wdg_clr_dly; + +/* Define the union u_crg_rst_wdg_lock */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int rst_wdg_lock : 1; /* [0] */ + unsigned int reserved_0 : 31; /* [31..1] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_rst_wdg_lock; + +/* Define the union u_crg_wdg_rst_status0 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int up_ring_exception_req : 1; /* [0] */ + unsigned int up_ring_lpbx_mode : 1; /* [1] */ + unsigned int up_ring_exception_ack : 1; /* [2] */ + unsigned int up_ring_exception_active : 1; /* [3] */ + unsigned int up_cpi_exception_req : 1; /* [4] */ + unsigned int up_cpi_lpbx_mode : 1; /* [5] */ + unsigned int up_cpi_exception_ack : 1; /* [6] */ + unsigned int up_cpi_exception_active : 1; /* [7] */ + unsigned int reserved_0 : 7; /* [14..8] */ + unsigned int up_wdg_rst_type : 1; /* [15] */ + unsigned int reserved_1 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_wdg_rst_status0; + +/* Define the union u_crg_wdg_boot_status1 */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int boot_sel_cnt : 15; /* [14..0] */ + unsigned int boot_sel_cnt_of : 1; /* [15] */ + unsigned int boot_sel : 1; /* [16] */ + unsigned int reserved_0 : 15; /* [31..17] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_wdg_boot_status1; + +/* Define the union u_crg_htc_clk_en */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int htc_dat_clk_en : 2; /* [1..0] */ + unsigned int htc_cfg_clk_en : 1; /* [2] */ + unsigned int htc_up_div80_clk_en : 1; /* [3] */ + unsigned int htc_dp_div90_clk_en : 1; /* [4] */ + unsigned int htc_dp_div70_clk_en : 1; /* [5] */ + unsigned int reserved_0 : 26; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_htc_clk_en; + +/* Define the union u_crg_htc_rst_req */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int htc_dat_rst_req : 2; /* [1..0] */ + unsigned int htc_cfg_rst_req : 1; /* [2] */ + unsigned int htc_up_div80_rst_req : 1; /* [3] */ + unsigned int htc_dp_div90_rst_req : 1; /* [4] */ + unsigned int htc_dp_div70_rst_req : 1; /* [5] */ + unsigned int reserved_0 : 26; /* [31..6] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_htc_rst_req; + +/* Define the union u_crg_htc_clk_cfg */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int htc_dp_div90_div_num : 8; /* [7..0] */ + unsigned int htc_dp_div70_div_num : 8; /* [15..8] */ + unsigned int reserved_0 : 16; /* [31..16] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_crg_htc_clk_cfg; + + +#endif /* C_UNION_DEFINE_CRG_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/crg_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/crg_reg_offset.h new file mode 100644 index 000000000..94d4877fc --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/crg_reg_offset.h @@ -0,0 +1,68 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2016, Hisilicon Technologies Co. Ltd. +// File name : crg_reg_offset.h +// Project line : IT Product Line +// Department : ICT Processor Chipset Development Department +// Version : V100 +// Date : 2014/5/8 +// Description : The description of xxx project +// Others : Generated automatically by nManager V4.0.2.5 +// History : 2016/08/17 15:16:31 Create file +// ****************************************************************************** + +#ifndef CRG_REG_OFFSET_H +#define CRG_REG_OFFSET_H + +/* CRG Base address of Module's Register */ +#define HI1822_CRG_BASE (0x1805000) + +/* **************************************************************************** */ +/* CRG Registers' Definitions */ +/* **************************************************************************** */ + +#define HI1822_CRG_CRG_PLL_CFG0_REG (HI1822_CRG_BASE + 0xA0) /* PLL0�������� */ +#define HI1822_CRG_CRG_PLL_CFG1_REG (HI1822_CRG_BASE + 0xA4) /* PLL1�������� */ +#define HI1822_CRG_CRG_PLL_CFG2_REG (HI1822_CRG_BASE + 0xA8) /* PLL2�������� */ +#define HI1822_CRG_CRG_PLL_CFG3_REG (HI1822_CRG_BASE + 0xAC) /* PLL3�������� */ +#define HI1822_CRG_CRG_PLL_CFG4_REG (HI1822_CRG_BASE + 0xB0) /* PLL4�������� */ +#define HI1822_CRG_CRG_PLL_CFG5_REG (HI1822_CRG_BASE + 0xB4) /* PLL5�������� */ +#define HI1822_CRG_CRG_PLL_DIV0_REG (HI1822_CRG_BASE + 0xB8) /* PLL0��Ƶ���� */ +#define HI1822_CRG_CRG_PLL_DIV1_REG (HI1822_CRG_BASE + 0xBC) /* PLL1��Ƶ���� */ +#define HI1822_CRG_CRG_PLL_DIV2_REG (HI1822_CRG_BASE + 0xC0) /* PLL2��Ƶ���� */ +#define HI1822_CRG_CRG_PLL_DIV3_REG (HI1822_CRG_BASE + 0xC4) /* PLL3��Ƶ���� */ +#define HI1822_CRG_CRG_PLL_DIV4_REG (HI1822_CRG_BASE + 0xC8) /* PLL4��Ƶ���� */ +#define HI1822_CRG_CRG_PLL_DIV5_REG (HI1822_CRG_BASE + 0xCC) /* PLL5��Ƶ���� */ +#define HI1822_CRG_CRG_SYS_CLK_CFG0_REG (HI1822_CRG_BASE + 0xD0) /* ϵͳʱ������0 */ +#define HI1822_CRG_CRG_SYS_CLK_EN0_REG (HI1822_CRG_BASE + 0xD4) /* ϵͳʱ��ʹ��0 */ +#define HI1822_CRG_CRG_SYS_RST_REQ0_REG (HI1822_CRG_BASE + 0xD8) /* ϵͳ��λ����0 */ +#define HI1822_CRG_CRG_SYS_CLK_CFG1_REG (HI1822_CRG_BASE + 0xDC) /* ϵͳʱ������1 */ +#define HI1822_CRG_CRG_SYS_CLK_EN1_REG (HI1822_CRG_BASE + 0xE0) /* ϵͳʱ��ʹ��1 */ +#define HI1822_CRG_CRG_SYS_RST_REQ1_REG (HI1822_CRG_BASE + 0xE4) /* ϵͳ��λ����1 */ +#define HI1822_CRG_CRG_SYS_CLK_EN2_REG (HI1822_CRG_BASE + 0xE8) /* ϵͳʱ��ʹ��2 */ +#define HI1822_CRG_CRG_PCIE_HILINK_RST_REG (HI1822_CRG_BASE + 0x100) /* HILINK��λ���� */ +#define HI1822_CRG_CRG_PCIE_CLK_CFG0_REG (HI1822_CRG_BASE + 0x104) /* PCIEʱ������0 */ +#define HI1822_CRG_CRG_PCIE_CLK_EN0_REG (HI1822_CRG_BASE + 0x108) /* PCIEʱ��ʹ��0 */ +#define HI1822_CRG_CRG_PCIE_RST_REQ0_REG (HI1822_CRG_BASE + 0x200) /* PCIE��λ����0 */ +#define HI1822_CRG_CRG_PCIE_RST_REQ1_REG (HI1822_CRG_BASE + 0x300) /* PCIE��λ����1 */ +#define HI1822_CRG_CRG_PCIE_OBS_CFG_REG (HI1822_CRG_BASE + 0x304) /* CRGʱ�ӹ۲����� */ +#define HI1822_CRG_CRG_PCIE_RSVD0_REG (HI1822_CRG_BASE + 0x308) /* �����Ĵ��� */ +#define HI1822_CRG_CRG_PCIE_RSVD1_REG (HI1822_CRG_BASE + 0x30C) /* �����Ĵ��� */ +#define HI1822_CRG_CRG_STATUS0_REG (HI1822_CRG_BASE + 0x800) /* CRG״̬�Ĵ���0 */ +#define HI1822_CRG_CRG_TOP_OBS_CFG_REG (HI1822_CRG_BASE + 0x804) /* CRGʱ�ӹ۲����� */ +#define HI1822_CRG_CRG_TOP_RSVD0_REG (HI1822_CRG_BASE + 0x808) /* �����Ĵ��� */ +#define HI1822_CRG_CRG_TOP_RSVD1_REG (HI1822_CRG_BASE + 0x80C) /* �����Ĵ��� */ +#define HI1822_CRG_CRG_SFT_RST_FCHIP_REG (HI1822_CRG_BASE + 0x900) /* оƬ����λ���� */ +#define HI1822_CRG_CRG_SFT_RST_UPSYS_REG (HI1822_CRG_BASE + 0x904) /* UP����λ���� */ +#define HI1822_CRG_CRG_WDG_CTRL_REG (HI1822_CRG_BASE + 0x910) /* ���Ź����� */ +#define HI1822_CRG_CRG_WDG_CNT_CONFIG_REG (HI1822_CRG_BASE + 0x914) /* ���Ź�����ʱ�� */ +#define HI1822_CRG_CRG_WDG_CLR_DLY_REG (HI1822_CRG_BASE + 0x918) /* ���Ź���λ�ӳ� */ +#define HI1822_CRG_CRG_WDG_RSVD0_REG (HI1822_CRG_BASE + 0x91C) /* ���� */ +#define HI1822_CRG_CRG_WDG_FEED_REG (HI1822_CRG_BASE + 0xA00) /* ���Ź�ι�� */ +#define HI1822_CRG_CRG_RST_WDG_LOCK_REG (HI1822_CRG_BASE + 0xA04) /* ����λ�����Ź��Ĵ������� */ +#define HI1822_CRG_CRG_WDG_RST_STATUS0_REG (HI1822_CRG_BASE + 0xA08) /* оƬWDG��λ״̬0 */ +#define HI1822_CRG_CRG_WDG_BOOT_STATUS1_REG (HI1822_CRG_BASE + 0xA0C) /* оƬWDG��λ״̬1 */ +#define HI1822_CRG_CRG_HTC_CLK_EN_REG (HI1822_CRG_BASE + 0xF00) +#define HI1822_CRG_CRG_HTC_RST_REQ_REG (HI1822_CRG_BASE + 0xF04) +#define HI1822_CRG_CRG_HTC_CLK_CFG_REG (HI1822_CRG_BASE + 0xF08) + +#endif // CRG_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_c_union_define.h new file mode 100644 index 000000000..229d2ee70 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_c_union_define.h @@ -0,0 +1,15330 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : mpu_c_union_define.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Version : V100 +// Date : +// Description : Hi1823 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V5.1 History : 2021/01/25 14:24:23 Create +// file +// ****************************************************************************** + +#ifndef MPU_C_UNION_DEFINE_H +#define MPU_C_UNION_DEFINE_H + +/* Define the union csr_ncsi_sys_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_sys_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_sys_version_u; + +/* Define the union csr_ncsi_chnl_smac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_mac_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_chnl_smac_l_u; + +/* Define the union csr_ncsi_chnl_smac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_mac_h : 16; /* [15:0] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_chnl_smac_h_u; + +/* Define the union csr_ncsi_chnl_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txchnl_en : 1; /* [0] */ + u32 rsv_1 : 3; /* [3:1] */ + u32 chnl_cos : 3; /* [6:4] */ + u32 rsv_2 : 1; /* [7] */ + u32 dst_port : 4; /* [11:8] */ + u32 rsv_3 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_chnl_ctrl_u; + +/* Define the union csr_ncsi_app_bd_empty_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_bd_empty_interval : 10; /* [9:0] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_app_bd_empty_interval_u; + +/* Define the union csr_ncsi_ctrl_chksum_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chksum_en : 1; /* [0] */ + u32 rsv_5 : 3; /* [3:1] */ + u32 tx_chksum_en : 1; /* [4] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ctrl_chksum_cfg_u; + +/* Define the union csr_ncsi_tx_max_frame_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_max_frame_size : 12; /* [11:0] */ + u32 rsv_7 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_max_frame_size_u; + +/* Define the union csr_ncsi_tx_min_frame_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_min_frame_size : 7; /* [6:0] */ + u32 rsv_8 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_min_frame_size_u; + +/* Define the union csr_ncsi_ram_sys_ecc_err_insr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram4_cerr_insr : 1; /* [0] */ + u32 ram4_ucerr_insr : 1; /* [1] */ + u32 rsv_9 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram_sys_ecc_err_insr_u; + +/* Define the union csr_ncsi_tcmd_afifo_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcmd_afifo_afull_th : 5; /* [4:0] */ + u32 rsv_10 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tcmd_afifo_level_u; + +/* Define the union csr_ncsi_txbd_fifo_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbd_fifo_afull_th : 2; /* [1:0] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_txbd_fifo_level_u; + +/* Define the union csr_ncsi_wr_acc_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_acc_max : 2; /* [1:0] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_wr_acc_max_u; + +/* Define the union csr_ncsi_rd_acc_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_acc_max : 2; /* [1:0] */ + u32 rsv_13 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rd_acc_max_u; + +/* Define the union csr_ncsi_bd_dst_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_dst_mode : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_bd_dst_mode_u; + +/* Define the union csr_ncsi_tx_bd_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pie2ncsi_tx_bd_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_bd_wrd0_u; + +/* Define the union csr_ncsi_tx_bd_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pie2ncsi_tx_bd_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_bd_wrd1_u; + +/* Define the union csr_ncsi_tx_bd_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pie2ncsi_tx_bd_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_bd_wrd2_u; + +/* Define the union csr_ncsi_tx_bd_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pie2ncsi_tx_bd_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_bd_wrd3_u; + +/* Define the union csr_ncsi_app_bd_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_bd_en : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_app_bd_en_u; + +/* Define the union csr_ncsi_rls_bd_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 4; /* [3:0] */ + u32 rls_bd_ncsi2pie_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rls_bd_addr_u; + +/* Define the union csr_ncsi_add_bd_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_17 : 4; /* [3:0] */ + u32 add_bd_ncsi2pie_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_add_bd_addr_u; + +/* Define the union csr_ncsi_app_pt_bd_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 4; /* [3:0] */ + u32 app_pt_bd_ncsi2pie_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_app_pt_bd_addr_u; + +/* Define the union csr_ncsi_app_ctrl_bd_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 app_ctrl_bd_ncsi2pie_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_app_ctrl_bd_addr_u; + +/* Define the union csr_ncsi_long_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_long_latency : 1; /* [0] */ + u32 rsv_20 : 3; /* [3:1] */ + u32 ncsi_long_latency_sel : 3; /* [6:4] */ + u32 rsv_21 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_long_latency_cfg_u; + +/* Define the union csr_ncsi_tx_add_pad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passpkt_pad_en : 1; /* [0] */ + u32 ctrlpkt_pad_en : 1; /* [1] */ + u32 rsv_22 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_add_pad_u; + +/* Define the union csr_ncsi_ram_sys_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram4_cerr : 1; /* [0] */ + u32 rsv_23 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram_sys_cerr_u; + +/* Define the union csr_ncsi_ram4_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram4_err_addr : 9; /* [8:0] */ + u32 rsv_24 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram4_ecc_err_addr_u; + +/* Define the union csr_ncsi_txbd_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbd_fifo_cnt : 3; /* [2:0] */ + u32 rsv_25 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_txbd_fifo_cnt_u; + +/* Define the union csr_ncsi_txbd_fifo_flow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbd_fifo_of : 1; /* [0] */ + u32 txbd_fifo_uf : 1; /* [1] */ + u32 rsv_26 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_txbd_fifo_flow_u; + +/* Define the union csr_ncsi_tcmd_afifo_of_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcmd_afifo_of : 1; /* [0] */ + u32 rsv_27 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tcmd_afifo_of_u; + +/* Define the union csr_ncsi_tcmd_afifo_wcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcmd_afifo_wcnt : 6; /* [5:0] */ + u32 rsv_28 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tcmd_afifo_wcnt_u; + +/* Define the union csr_ncsi_tx_afifo_wcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_afifo_wcnt : 9; /* [8:0] */ + u32 rsv_29 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_afifo_wcnt_u; + +/* Define the union csr_ncsi_tx_afifo_of_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_afifo_of : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_afifo_of_u; + +/* Define the union csr_ncsi_pt_bd_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_pt_bd_fifo_cnt : 2; /* [1:0] */ + u32 rsv_31 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pt_bd_fifo_cnt_u; + +/* Define the union csr_ncsi_pt_bd_fifo_flow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_pt_bd_fifo_of : 1; /* [0] */ + u32 app_pt_bd_fifo_uf : 1; /* [1] */ + u32 rsv_32 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pt_bd_fifo_flow_u; + +/* Define the union csr_ncsi_ctrl_bd_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_ctrl_bd_fifo_cnt : 2; /* [1:0] */ + u32 rsv_33 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ctrl_bd_fifo_cnt_u; + +/* Define the union csr_ncsi_ctrl_bd_fifo_flow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_ctrl_bd_fifo_of : 1; /* [0] */ + u32 app_ctrl_bd_fifo_uf : 1; /* [1] */ + u32 rsv_34 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ctrl_bd_fifo_flow_u; + +/* Define the union csr_ncsi_axi_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_otd_cnt : 3; /* [2:0] */ + u32 rsv_35 : 1; /* [3] */ + u32 axi_rd_otd_cnt : 3; /* [6:4] */ + u32 rsv_36 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_axi_otd_cnt_u; + +/* Define the union csr_ncsi_app_bd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_bd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_app_bd_cnt_u; + +/* Define the union csr_ncsi_add_bd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_add_bd_cnt_u; + +/* Define the union csr_ncsi_rx_txbd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_txbd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_txbd_cnt_u; + +/* Define the union csr_ncsi_rx_txbd_empty_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_txbd_empty_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_txbd_empty_cnt_u; + +/* Define the union csr_ncsi_rx_txbd_code_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_txbd_code_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_txbd_code_err_cnt_u; + +/* Define the union csr_ncsi_rx_txbd_min_frame_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_txbd_min_frame_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_txbd_min_frame_cnt_u; + +/* Define the union csr_ncsi_rx_txbd_max_frame_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_txbd_max_frame_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_txbd_max_frame_cnt_u; + +/* Define the union csr_ncsi_rls_bd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rls_bd_cnt_u; + +/* Define the union csr_ncsi_rx_pt_pkt_cnt_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pt_pkt_cnt_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_pt_pkt_cnt_low_u; + +/* Define the union csr_ncsi_rx_pt_pkt_cnt_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pt_pkt_cnt_high : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_pt_pkt_cnt_high_u; + +/* Define the union csr_ncsi_rx_pt_pkt_disc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pt_pkt_disc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_pt_pkt_disc_cnt_u; + +/* Define the union csr_ncsi_rx_pt_ch_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pt_ch_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_pt_ch_err_cnt_u; + +/* Define the union csr_ncsi_tx_pt_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pt_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_pt_pkt_cnt_u; + +/* Define the union csr_ncsi_rx_ctrl_ok_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_ctrl_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_ctrl_ok_cnt_u; + +/* Define the union csr_ncsi_rx_ctrl_disc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_ctrl_disc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_ctrl_disc_cnt_u; + +/* Define the union csr_ncsi_rx_ctrl_chksum_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_ctrl_chksum_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_ctrl_chksum_err_cnt_u; + +/* Define the union csr_ncsi_tx_ctrl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ctrl_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_ctrl_pkt_cnt_u; + +/* Define the union csr_ncsi_tx_ctrl_len_mismatch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ctrl_len_mismatch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_ctrl_len_mismatch_cnt_u; + +/* Define the union csr_ncsi_tx_ctrl_len_short_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ctrl_len_short_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_ctrl_len_short_u; + +/* Define the union csr_ncsi_bd_busy_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bd_dealing : 1; /* [0] */ + u32 rsv_38 : 7; /* [7:1] */ + u32 pt_bd_dealing : 1; /* [8] */ + u32 rsv_39 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_bd_busy_stat_u; + +/* Define the union csr_ncsi_rx_pt_ch_ok_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pt_ch_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_pt_ch_ok_cnt_u; + +/* Define the union csr_ncsi_rx_ctrl_payload_len_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_ctrl_payload_len_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_ctrl_payload_len_err_cnt_u; + +/* Define the union csr_ncsi_rx_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_cur_st : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_cur_st_u; + +/* Define the union csr_ncsi_app_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 app_cur_st : 4; /* [3:0] */ + u32 rsv_41 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_app_cur_st_u; + +/* Define the union csr_ncsi_wshm_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wshm_cur_st : 6; /* [5:0] */ + u32 rsv_42 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_wshm_cur_st_u; + +/* Define the union csr_ncsi_add_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_cur_st : 2; /* [1:0] */ + u32 rsv_43 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_add_cur_st_u; + +/* Define the union csr_ncsi_rshm_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rshm_cur_st : 7; /* [6:0] */ + u32 rsv_44 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rshm_cur_st_u; + +/* Define the union csr_ncsi_rls_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_cur_st : 2; /* [1:0] */ + u32 rsv_45 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rls_cur_st_u; + +/* Define the union csr_ncsi_axi_rch_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rch_cur_st : 2; /* [1:0] */ + u32 rsv_46 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_axi_rch_cur_st_u; + +/* Define the union csr_ncsi_axi_wch_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wch_cur_st : 2; /* [1:0] */ + u32 rsv_47 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_axi_wch_cur_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ncsi_sys_version_u ncsi_sys_version; /* 0 */ + volatile csr_ncsi_chnl_smac_l_u ncsi_chnl_smac_l[4]; /* 100 */ + volatile csr_ncsi_chnl_smac_h_u ncsi_chnl_smac_h[4]; /* 110 */ + volatile csr_ncsi_chnl_ctrl_u ncsi_chnl_ctrl[4]; /* 120 */ + volatile csr_ncsi_app_bd_empty_interval_u ncsi_app_bd_empty_interval; /* 130 */ + volatile csr_ncsi_ctrl_chksum_cfg_u ncsi_ctrl_chksum_cfg; /* 134 */ + volatile csr_ncsi_tx_max_frame_size_u ncsi_tx_max_frame_size; /* 138 */ + volatile csr_ncsi_tx_min_frame_size_u ncsi_tx_min_frame_size; /* 13C */ + volatile csr_ncsi_ram_sys_ecc_err_insr_u ncsi_ram_sys_ecc_err_insr; /* 140 */ + volatile csr_ncsi_tcmd_afifo_level_u ncsi_tcmd_afifo_level; /* 144 */ + volatile csr_ncsi_txbd_fifo_level_u ncsi_txbd_fifo_level; /* 148 */ + volatile csr_ncsi_wr_acc_max_u ncsi_wr_acc_max; /* 14C */ + volatile csr_ncsi_rd_acc_max_u ncsi_rd_acc_max; /* 150 */ + volatile csr_ncsi_bd_dst_mode_u ncsi_bd_dst_mode; /* 154 */ + volatile csr_ncsi_tx_bd_wrd0_u ncsi_tx_bd_wrd0; /* 200 */ + volatile csr_ncsi_tx_bd_wrd1_u ncsi_tx_bd_wrd1; /* 204 */ + volatile csr_ncsi_tx_bd_wrd2_u ncsi_tx_bd_wrd2; /* 208 */ + volatile csr_ncsi_tx_bd_wrd3_u ncsi_tx_bd_wrd3; /* 20C */ + volatile csr_ncsi_app_bd_en_u ncsi_app_bd_en; /* 210 */ + volatile csr_ncsi_rls_bd_addr_u ncsi_rls_bd_addr; /* 214 */ + volatile csr_ncsi_add_bd_addr_u ncsi_add_bd_addr; /* 218 */ + volatile csr_ncsi_app_pt_bd_addr_u ncsi_app_pt_bd_addr; /* 21C */ + volatile csr_ncsi_app_ctrl_bd_addr_u ncsi_app_ctrl_bd_addr; /* 220 */ + volatile csr_ncsi_long_latency_cfg_u ncsi_long_latency_cfg; /* 224 */ + volatile csr_ncsi_tx_add_pad_u ncsi_tx_add_pad; /* 228 */ + volatile csr_ncsi_ram_sys_cerr_u ncsi_ram_sys_cerr; /* 300 */ + volatile csr_ncsi_ram4_ecc_err_addr_u ncsi_ram4_ecc_err_addr; /* 304 */ + volatile csr_ncsi_txbd_fifo_cnt_u ncsi_txbd_fifo_cnt; /* 308 */ + volatile csr_ncsi_txbd_fifo_flow_u ncsi_txbd_fifo_flow; /* 30C */ + volatile csr_ncsi_tcmd_afifo_of_u ncsi_tcmd_afifo_of; /* 310 */ + volatile csr_ncsi_tcmd_afifo_wcnt_u ncsi_tcmd_afifo_wcnt; /* 314 */ + volatile csr_ncsi_tx_afifo_wcnt_u ncsi_tx_afifo_wcnt; /* 318 */ + volatile csr_ncsi_tx_afifo_of_u ncsi_tx_afifo_of; /* 31C */ + volatile csr_ncsi_pt_bd_fifo_cnt_u ncsi_pt_bd_fifo_cnt; /* 320 */ + volatile csr_ncsi_pt_bd_fifo_flow_u ncsi_pt_bd_fifo_flow; /* 324 */ + volatile csr_ncsi_ctrl_bd_fifo_cnt_u ncsi_ctrl_bd_fifo_cnt; /* 328 */ + volatile csr_ncsi_ctrl_bd_fifo_flow_u ncsi_ctrl_bd_fifo_flow; /* 32C */ + volatile csr_ncsi_axi_otd_cnt_u ncsi_axi_otd_cnt; /* 330 */ + volatile csr_ncsi_app_bd_cnt_u ncsi_app_bd_cnt; /* 400 */ + volatile csr_ncsi_add_bd_cnt_u ncsi_add_bd_cnt; /* 404 */ + volatile csr_ncsi_rx_txbd_cnt_u ncsi_rx_txbd_cnt; /* 408 */ + volatile csr_ncsi_rx_txbd_empty_cnt_u ncsi_rx_txbd_empty_cnt; /* 40C */ + volatile csr_ncsi_rx_txbd_code_err_cnt_u ncsi_rx_txbd_code_err_cnt; /* 410 */ + volatile csr_ncsi_rx_txbd_min_frame_cnt_u ncsi_rx_txbd_min_frame_cnt; /* 414 */ + volatile csr_ncsi_rx_txbd_max_frame_cnt_u ncsi_rx_txbd_max_frame_cnt; /* 418 */ + volatile csr_ncsi_rls_bd_cnt_u ncsi_rls_bd_cnt; /* 41C */ + volatile csr_ncsi_rx_pt_pkt_cnt_low_u ncsi_rx_pt_pkt_cnt_low; /* 420 */ + volatile csr_ncsi_rx_pt_pkt_cnt_high_u ncsi_rx_pt_pkt_cnt_high; /* 424 */ + volatile csr_ncsi_rx_pt_pkt_disc_cnt_u ncsi_rx_pt_pkt_disc_cnt; /* 428 */ + volatile csr_ncsi_rx_pt_ch_err_cnt_u ncsi_rx_pt_ch_err_cnt[4]; /* 42C */ + volatile csr_ncsi_tx_pt_pkt_cnt_u ncsi_tx_pt_pkt_cnt; /* 43C */ + volatile csr_ncsi_rx_ctrl_ok_cnt_u ncsi_rx_ctrl_ok_cnt; /* 440 */ + volatile csr_ncsi_rx_ctrl_disc_cnt_u ncsi_rx_ctrl_disc_cnt; /* 444 */ + volatile csr_ncsi_rx_ctrl_chksum_err_cnt_u ncsi_rx_ctrl_chksum_err_cnt; /* 448 */ + volatile csr_ncsi_tx_ctrl_pkt_cnt_u ncsi_tx_ctrl_pkt_cnt; /* 44C */ + volatile csr_ncsi_tx_ctrl_len_mismatch_cnt_u ncsi_tx_ctrl_len_mismatch_cnt; /* 450 */ + volatile csr_ncsi_tx_ctrl_len_short_u ncsi_tx_ctrl_len_short; /* 454 */ + volatile csr_ncsi_bd_busy_stat_u ncsi_bd_busy_stat; /* 458 */ + volatile csr_ncsi_rx_pt_ch_ok_cnt_u ncsi_rx_pt_ch_ok_cnt[4]; /* 45C */ + volatile csr_ncsi_rx_ctrl_payload_len_err_cnt_u ncsi_rx_ctrl_payload_len_err_cnt; /* 46C */ + volatile csr_ncsi_rx_cur_st_u ncsi_rx_cur_st; /* 500 */ + volatile csr_ncsi_app_cur_st_u ncsi_app_cur_st; /* 504 */ + volatile csr_ncsi_wshm_cur_st_u ncsi_wshm_cur_st; /* 508 */ + volatile csr_ncsi_add_cur_st_u ncsi_add_cur_st; /* 50C */ + volatile csr_ncsi_rshm_cur_st_u ncsi_rshm_cur_st; /* 510 */ + volatile csr_ncsi_rls_cur_st_u ncsi_rls_cur_st; /* 514 */ + volatile csr_ncsi_axi_rch_cur_st_u ncsi_axi_rch_cur_st; /* 518 */ + volatile csr_ncsi_axi_wch_cur_st_u ncsi_axi_wch_cur_st; /* 51C */ +} S_ncsi_sys_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ncsi_sys_csr */ +extern volatile S_ncsi_sys_csr_REGS_TYPE *gopncsi_sys_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetNCSI_SYS_VERSION_ncsi_sys_version(unsigned int uncsi_sys_version); +int iSetNCSI_CHNL_SMAC_L_src_mac_l(unsigned int usrc_mac_l); +int iSetNCSI_CHNL_SMAC_H_src_mac_h(unsigned int usrc_mac_h); +int iSetNCSI_CHNL_CTRL_txchnl_en(unsigned int utxchnl_en); +int iSetNCSI_CHNL_CTRL_chnl_cos(unsigned int uchnl_cos); +int iSetNCSI_CHNL_CTRL_dst_port(unsigned int udst_port); +int iSetNCSI_APP_BD_EMPTY_INTERVAL_app_bd_empty_interval(unsigned int uapp_bd_empty_interval); +int iSetNCSI_CTRL_CHKSUM_CFG_rx_chksum_en(unsigned int urx_chksum_en); +int iSetNCSI_CTRL_CHKSUM_CFG_tx_chksum_en(unsigned int utx_chksum_en); +int iSetNCSI_TX_MAX_FRAME_SIZE_tx_max_frame_size(unsigned int utx_max_frame_size); +int iSetNCSI_TX_MIN_FRAME_SIZE_tx_min_frame_size(unsigned int utx_min_frame_size); +int iSetNCSI_RAM_SYS_ECC_ERR_INSR_ram4_cerr_insr(unsigned int uram4_cerr_insr); +int iSetNCSI_RAM_SYS_ECC_ERR_INSR_ram4_ucerr_insr(unsigned int uram4_ucerr_insr); +int iSetNCSI_TCMD_AFIFO_LEVEL_tcmd_afifo_afull_th(unsigned int utcmd_afifo_afull_th); +int iSetNCSI_TXBD_FIFO_LEVEL_txbd_fifo_afull_th(unsigned int utxbd_fifo_afull_th); +int iSetNCSI_WR_ACC_MAX_axi_wr_acc_max(unsigned int uaxi_wr_acc_max); +int iSetNCSI_RD_ACC_MAX_axi_rd_acc_max(unsigned int uaxi_rd_acc_max); +int iSetNCSI_BD_DST_MODE_bd_dst_mode(unsigned int ubd_dst_mode); +int iSetNCSI_TX_BD_WRD0_pie2ncsi_tx_bd_wrd0(unsigned int upie2ncsi_tx_bd_wrd0); +int iSetNCSI_TX_BD_WRD1_pie2ncsi_tx_bd_wrd1(unsigned int upie2ncsi_tx_bd_wrd1); +int iSetNCSI_TX_BD_WRD2_pie2ncsi_tx_bd_wrd2(unsigned int upie2ncsi_tx_bd_wrd2); +int iSetNCSI_TX_BD_WRD3_pie2ncsi_tx_bd_wrd3(unsigned int upie2ncsi_tx_bd_wrd3); +int iSetNCSI_APP_BD_EN_app_bd_en(unsigned int uapp_bd_en); +int iSetNCSI_RLS_BD_ADDR_rls_bd_ncsi2pie_addr(unsigned int urls_bd_ncsi2pie_addr); +int iSetNCSI_ADD_BD_ADDR_add_bd_ncsi2pie_addr(unsigned int uadd_bd_ncsi2pie_addr); +int iSetNCSI_APP_PT_BD_ADDR_app_pt_bd_ncsi2pie_addr(unsigned int uapp_pt_bd_ncsi2pie_addr); +int iSetNCSI_APP_CTRL_BD_ADDR_app_ctrl_bd_ncsi2pie_addr(unsigned int uapp_ctrl_bd_ncsi2pie_addr); +int iSetNCSI_LONG_LATENCY_CFG_ncsi_long_latency(unsigned int uncsi_long_latency); +int iSetNCSI_LONG_LATENCY_CFG_ncsi_long_latency_sel(unsigned int uncsi_long_latency_sel); +int iSetNCSI_TX_ADD_PAD_passpkt_pad_en(unsigned int upasspkt_pad_en); +int iSetNCSI_TX_ADD_PAD_ctrlpkt_pad_en(unsigned int uctrlpkt_pad_en); +int iSetNCSI_RAM_SYS_CERR_ram4_cerr(unsigned int uram4_cerr); +int iSetNCSI_RAM4_ECC_ERR_ADDR_ram4_err_addr(unsigned int uram4_err_addr); +int iSetNCSI_TXBD_FIFO_CNT_txbd_fifo_cnt(unsigned int utxbd_fifo_cnt); +int iSetNCSI_TXBD_FIFO_FLOW_txbd_fifo_of(unsigned int utxbd_fifo_of); +int iSetNCSI_TXBD_FIFO_FLOW_txbd_fifo_uf(unsigned int utxbd_fifo_uf); +int iSetNCSI_TCMD_AFIFO_OF_tcmd_afifo_of(unsigned int utcmd_afifo_of); +int iSetNCSI_TCMD_AFIFO_WCNT_tcmd_afifo_wcnt(unsigned int utcmd_afifo_wcnt); +int iSetNCSI_TX_AFIFO_WCNT_tx_afifo_wcnt(unsigned int utx_afifo_wcnt); +int iSetNCSI_TX_AFIFO_OF_tx_afifo_of(unsigned int utx_afifo_of); +int iSetNCSI_PT_BD_FIFO_CNT_app_pt_bd_fifo_cnt(unsigned int uapp_pt_bd_fifo_cnt); +int iSetNCSI_PT_BD_FIFO_FLOW_app_pt_bd_fifo_of(unsigned int uapp_pt_bd_fifo_of); +int iSetNCSI_PT_BD_FIFO_FLOW_app_pt_bd_fifo_uf(unsigned int uapp_pt_bd_fifo_uf); +int iSetNCSI_CTRL_BD_FIFO_CNT_app_ctrl_bd_fifo_cnt(unsigned int uapp_ctrl_bd_fifo_cnt); +int iSetNCSI_CTRL_BD_FIFO_FLOW_app_ctrl_bd_fifo_of(unsigned int uapp_ctrl_bd_fifo_of); +int iSetNCSI_CTRL_BD_FIFO_FLOW_app_ctrl_bd_fifo_uf(unsigned int uapp_ctrl_bd_fifo_uf); +int iSetNCSI_AXI_OTD_CNT_axi_wr_otd_cnt(unsigned int uaxi_wr_otd_cnt); +int iSetNCSI_AXI_OTD_CNT_axi_rd_otd_cnt(unsigned int uaxi_rd_otd_cnt); +int iSetNCSI_APP_BD_CNT_app_bd_cnt(unsigned int uapp_bd_cnt); +int iSetNCSI_ADD_BD_CNT_add_bd_cnt(unsigned int uadd_bd_cnt); +int iSetNCSI_RX_TXBD_CNT_rx_txbd_cnt(unsigned int urx_txbd_cnt); +int iSetNCSI_RX_TXBD_EMPTY_CNT_rx_txbd_empty_cnt(unsigned int urx_txbd_empty_cnt); +int iSetNCSI_RX_TXBD_CODE_ERR_CNT_rx_txbd_code_err_cnt(unsigned int urx_txbd_code_err_cnt); +int iSetNCSI_RX_TXBD_MIN_FRAME_CNT_rx_txbd_min_frame_cnt(unsigned int urx_txbd_min_frame_cnt); +int iSetNCSI_RX_TXBD_MAX_FRAME_CNT_rx_txbd_max_frame_cnt(unsigned int urx_txbd_max_frame_cnt); +int iSetNCSI_RLS_BD_CNT_rls_bd_cnt(unsigned int urls_bd_cnt); +int iSetNCSI_RX_PT_PKT_CNT_LOW_rx_pt_pkt_cnt_low(unsigned int urx_pt_pkt_cnt_low); +int iSetNCSI_RX_PT_PKT_CNT_HIGH_rx_pt_pkt_cnt_high(unsigned int urx_pt_pkt_cnt_high); +int iSetNCSI_RX_PT_PKT_DISC_CNT_rx_pt_pkt_disc_cnt(unsigned int urx_pt_pkt_disc_cnt); +int iSetNCSI_RX_PT_CH_ERR_CNT_rx_pt_ch_err_cnt(unsigned int urx_pt_ch_err_cnt); +int iSetNCSI_TX_PT_PKT_CNT_tx_pt_pkt_cnt(unsigned int utx_pt_pkt_cnt); +int iSetNCSI_RX_CTRL_OK_CNT_rx_ctrl_ok_cnt(unsigned int urx_ctrl_ok_cnt); +int iSetNCSI_RX_CTRL_DISC_CNT_rx_ctrl_disc_cnt(unsigned int urx_ctrl_disc_cnt); +int iSetNCSI_RX_CTRL_CHKSUM_ERR_CNT_rx_ctrl_chksum_err_cnt(unsigned int urx_ctrl_chksum_err_cnt); +int iSetNCSI_TX_CTRL_PKT_CNT_tx_ctrl_pkt_cnt(unsigned int utx_ctrl_pkt_cnt); +int iSetNCSI_TX_CTRL_LEN_MISMATCH_CNT_tx_ctrl_len_mismatch_cnt(unsigned int utx_ctrl_len_mismatch_cnt); +int iSetNCSI_TX_CTRL_LEN_SHORT_tx_ctrl_len_short_cnt(unsigned int utx_ctrl_len_short_cnt); +int iSetNCSI_BD_BUSY_STAT_ctrl_bd_dealing(unsigned int uctrl_bd_dealing); +int iSetNCSI_BD_BUSY_STAT_pt_bd_dealing(unsigned int upt_bd_dealing); +int iSetNCSI_RX_PT_CH_OK_CNT_rx_pt_ch_ok_cnt(unsigned int urx_pt_ch_ok_cnt); +int iSetNCSI_RX_CTRL_PAYLOAD_LEN_ERR_CNT_rx_ctrl_payload_len_err_cnt(unsigned int urx_ctrl_payload_len_err_cnt); +int iSetNCSI_RX_CUR_ST_rx_cur_st(unsigned int urx_cur_st); +int iSetNCSI_APP_CUR_ST_app_cur_st(unsigned int uapp_cur_st); +int iSetNCSI_WSHM_CUR_ST_wshm_cur_st(unsigned int uwshm_cur_st); +int iSetNCSI_ADD_CUR_ST_add_cur_st(unsigned int uadd_cur_st); +int iSetNCSI_RSHM_CUR_ST_rshm_cur_st(unsigned int urshm_cur_st); +int iSetNCSI_RLS_CUR_ST_rls_cur_st(unsigned int urls_cur_st); +int iSetNCSI_AXI_RCH_CUR_ST_axi_rch_cur_st(unsigned int uaxi_rch_cur_st); +int iSetNCSI_AXI_WCH_CUR_ST_axi_wch_cur_st(unsigned int uaxi_wch_cur_st); + +/* Define the union csr_ncsi_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_version_u; + +/* Define the union csr_ncsi_hw_arb_bps_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hw_arb_bps : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_hw_arb_bps_u; + +/* Define the union csr_ncsi_pause_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pause_en : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pause_en_u; + +/* Define the union csr_ncsi_hw_arb_ipg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hw_arb_ipg : 4; /* [3:0] */ + u32 rsv_2 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_hw_arb_ipg_u; + +/* Define the union csr_ncsi_send_token_time_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_token_time_gap : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_send_token_time_gap_u; + +/* Define the union csr_ncsi_tr_pkt_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tr_pkt_timeout : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tr_pkt_timeout_u; + +/* Define the union csr_ncsi_xoff_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_xoff_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_xoff_timeout_u; + +/* Define the union csr_ncsi_pkg_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_pkg_id : 3; /* [2:0] */ + u32 rsv_5 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pkg_id_u; + +/* Define the union csr_ncsi_arb_mstr_event_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arb_mstr_event : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_arb_mstr_event_u; + +/* Define the union csr_ncsi_arb_pkg_id_msb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arb_pkg_id_msb : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_arb_pkg_id_msb_u; + +/* Define the union csr_ncsi_rcvd_lower_flush_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rcvd_lower_flush_mode : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rcvd_lower_flush_mode_u; + +/* Define the union csr_ncsi_wait_idle_rcvd_pause_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_idle_rcvd_pause_mode : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_wait_idle_rcvd_pause_mode_u; + +/* Define the union csr_ncsi_pad_ext_pulldown_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_pad_ext_pulldown : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pad_ext_pulldown_u; + +/* Define the union csr_ncsi_code_sync_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 code_sync_cur_st : 6; /* [5:0] */ + u32 rsv_11 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_code_sync_u; + +/* Define the union csr_ncsi_rx_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_code_cur_st : 15; /* [14:0] */ + u32 rsv_12 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_code_u; + +/* Define the union csr_ncsi_arb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arb_cur_st : 5; /* [4:0] */ + u32 rsv_13 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_arb_u; + +/* Define the union csr_ncsi_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 token_cur_st : 7; /* [6:0] */ + u32 rsv_14 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_token_u; + +/* Define the union csr_ncsi_pause_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pause_cur_st : 10; /* [9:0] */ + u32 rsv_15 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pause_u; + +/* Define the union csr_ncsi_tx_op_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_op_code : 3; /* [2:0] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_op_code_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ncsi_version_u ncsi_version; /* 0 */ + volatile csr_ncsi_hw_arb_bps_u ncsi_hw_arb_bps; /* 100 */ + volatile csr_ncsi_pause_en_u ncsi_pause_en; /* 104 */ + volatile csr_ncsi_hw_arb_ipg_u ncsi_hw_arb_ipg; /* 108 */ + volatile csr_ncsi_send_token_time_gap_u ncsi_send_token_time_gap; /* 10C */ + volatile csr_ncsi_tr_pkt_timeout_u ncsi_tr_pkt_timeout; /* 110 */ + volatile csr_ncsi_xoff_timeout_u ncsi_xoff_timeout; /* 114 */ + volatile csr_ncsi_pkg_id_u ncsi_pkg_id; /* 118 */ + volatile csr_ncsi_arb_mstr_event_u ncsi_arb_mstr_event; /* 11C */ + volatile csr_ncsi_arb_pkg_id_msb_u ncsi_arb_pkg_id_msb; /* 120 */ + volatile csr_ncsi_rcvd_lower_flush_mode_u ncsi_rcvd_lower_flush_mode; /* 124 */ + volatile csr_ncsi_wait_idle_rcvd_pause_mode_u ncsi_wait_idle_rcvd_pause_mode; /* 128 */ + volatile csr_ncsi_pad_ext_pulldown_u ncsi_pad_ext_pulldown; /* 12C */ + volatile csr_ncsi_code_sync_u ncsi_code_sync; /* 500 */ + volatile csr_ncsi_rx_code_u ncsi_rx_code; /* 504 */ + volatile csr_ncsi_arb_u ncsi_arb; /* 508 */ + volatile csr_ncsi_token_u ncsi_token; /* 50C */ + volatile csr_ncsi_pause_u ncsi_pause; /* 510 */ + volatile csr_ncsi_tx_op_code_u ncsi_tx_op_code; /* 514 */ +} S_ncsi_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ncsi_csr */ +extern volatile S_ncsi_csr_REGS_TYPE *gopncsi_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetNCSI_VERSION_ncsi_version(unsigned int uncsi_version); +int iSetNCSI_HW_ARB_BPS_hw_arb_bps(unsigned int uhw_arb_bps); +int iSetNCSI_PAUSE_EN_tx_pause_en(unsigned int utx_pause_en); +int iSetNCSI_HW_ARB_IPG_hw_arb_ipg(unsigned int uhw_arb_ipg); +int iSetNCSI_SEND_TOKEN_TIME_GAP_send_token_time_gap(unsigned int usend_token_time_gap); +int iSetNCSI_TR_PKT_TIMEOUT_tr_pkt_timeout(unsigned int utr_pkt_timeout); +int iSetNCSI_XOFF_TIMEOUT_tx_xoff_timeout(unsigned int utx_xoff_timeout); +int iSetNCSI_PKG_ID_local_pkg_id(unsigned int ulocal_pkg_id); +int iSetNCSI_ARB_MSTR_EVENT_arb_mstr_event(unsigned int uarb_mstr_event); +int iSetNCSI_ARB_PKG_ID_MSB_arb_pkg_id_msb(unsigned int uarb_pkg_id_msb); +int iSetNCSI_RCVD_LOWER_FLUSH_MODE_rcvd_lower_flush_mode(unsigned int urcvd_lower_flush_mode); +int iSetNCSI_WAIT_IDLE_RCVD_PAUSE_MODE_wait_idle_rcvd_pause_mode(unsigned int uwait_idle_rcvd_pause_mode); +int iSetNCSI_PAD_EXT_PULLDOWN_ncsi_pad_ext_pulldown(unsigned int uncsi_pad_ext_pulldown); +int iSetNCSI_CODE_SYNC_code_sync_cur_st(unsigned int ucode_sync_cur_st); +int iSetNCSI_RX_CODE_rx_code_cur_st(unsigned int urx_code_cur_st); +int iSetNCSI_ARB_arb_cur_st(unsigned int uarb_cur_st); +int iSetNCSI_TOKEN_token_cur_st(unsigned int utoken_cur_st); +int iSetNCSI_PAUSE_pause_cur_st(unsigned int upause_cur_st); +int iSetNCSI_TX_OP_CODE_tx_op_code(unsigned int utx_op_code); + +/* Define the union csr_ncsi_mac_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_mac_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_mac_version_u; + +/* Define the union csr_ncsi_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fifo_err_int_status : 1; /* [0] */ + u32 ram0_ucerr_int_status : 1; /* [1] */ + u32 ram1_ucerr_int_status : 1; /* [2] */ + u32 ram2_ucerr_int_status : 1; /* [3] */ + u32 ram3_ucerr_int_status : 1; /* [4] */ + u32 ram4_ucerr_int_status : 1; /* [5] */ + u32 ncsi_domain_non_stable_int_status : 1; /* [6] */ + u32 rsv_0 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_int_status_u; + +/* Define the union csr_ncsi_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fifo_err_int_en : 1; /* [0] */ + u32 ram0_ucerr_int_en : 1; /* [1] */ + u32 ram1_ucerr_int_en : 1; /* [2] */ + u32 ram2_ucerr_int_en : 1; /* [3] */ + u32 ram3_ucerr_int_en : 1; /* [4] */ + u32 ram4_ucerr_int_en : 1; /* [5] */ + u32 ncsi_domain_non_stable_int_en : 1; /* [6] */ + u32 rsv_1 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_int_en_u; + +/* Define the union csr_ncsi_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fifo_err_int_set : 1; /* [0] */ + u32 ram0_ucerr_int_set : 1; /* [1] */ + u32 ram1_ucerr_int_set : 1; /* [2] */ + u32 ram2_ucerr_int_set : 1; /* [3] */ + u32 ram3_ucerr_int_set : 1; /* [4] */ + u32 ram4_ucerr_int_set : 1; /* [5] */ + u32 ncsi_domain_non_stable_int_set : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_int_set_u; + +/* Define the union csr_ncsi_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fifo_err_int_raw_status : 1; /* [0] */ + u32 ram0_ucerr_int_raw_status : 1; /* [1] */ + u32 ram1_ucerr_int_raw_status : 1; /* [2] */ + u32 ram2_ucerr_int_raw_status : 1; /* [3] */ + u32 ram3_ucerr_int_raw_status : 1; /* [4] */ + u32 ram4_ucerr_int_raw_status : 1; /* [5] */ + u32 ncsi_domain_non_stable_int_raw_status : 1; /* [6] */ + u32 rsv_3 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_int_raw_status_u; + +/* Define the union csr_ncsi_tp_ram_tmod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tp_ram_tmod : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tp_ram_tmod_u; + +/* Define the union csr_ncsi_mem_power_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_power_mode : 6; /* [5:0] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_mem_power_mode_u; + +/* Define the union csr_ncsi_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_bypass : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram_ecc_bypass_u; + +/* Define the union csr_ncsi_hw_arb_bps_mac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hw_arb_bps_mac : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_hw_arb_bps_mac_u; + +/* Define the union csr_ncsi_xon_xoff_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xon_frame_len : 6; /* [5:0] */ + u32 rsv_8 : 2; /* [7:6] */ + u32 xoff_frame_len : 6; /* [13:8] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_xon_xoff_len_u; + +/* Define the union csr_ncsi_xon_frame_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xon_frame : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_xon_frame_u; + +/* Define the union csr_ncsi_xoff_frame_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xoff_frame : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_xoff_frame_u; + +/* Define the union csr_ncsi_ram_ecc_err_insr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_cerr_insr : 1; /* [0] */ + u32 ram1_cerr_insr : 1; /* [1] */ + u32 ram2_cerr_insr : 1; /* [2] */ + u32 ram3_cerr_insr : 1; /* [3] */ + u32 ram0_ucerr_insr : 1; /* [4] */ + u32 ram1_ucerr_insr : 1; /* [5] */ + u32 ram2_ucerr_insr : 1; /* [6] */ + u32 ram3_ucerr_insr : 1; /* [7] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram_ecc_err_insr_u; + +/* Define the union csr_ncsi_rx_afifo_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_afifo_low_level : 9; /* [8:0] */ + u32 rsv_11 : 7; /* [15:9] */ + u32 rx_afifo_high_level : 9; /* [24:16] */ + u32 rsv_12 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_afifo_level_u; + +/* Define the union csr_ncsi_rx_afifo_afull_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_afifo_afull_th : 9; /* [8:0] */ + u32 rsv_13 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_afifo_afull_th_u; + +/* Define the union csr_ncsi_rcmd_afifo_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rcmd_afifo_afull_th : 6; /* [5:0] */ + u32 rsv_14 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rcmd_afifo_level_u; + +/* Define the union csr_ncsi_tx_afifo_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_afifo_afull_th : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_afifo_level_u; + +/* Define the union csr_ncsi_domain_chk_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_domain_chk_cnt : 6; /* [5:0] */ + u32 rsv_16 : 2; /* [7:6] */ + u32 ncsi_domain_jitter_max : 4; /* [11:8] */ + u32 rsv_17 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_domain_chk_cnt_u; + +/* Define the union csr_ncsi_domain_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_domain_rdy : 1; /* [0] */ + u32 rsv_18 : 3; /* [3:1] */ + u32 ncsi_domain_rw_en : 1; /* [4] */ + u32 rsv_19 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_domain_stat_u; + +/* Define the union csr_ncsi_domain_self_shield_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_domain_self_shield_mode : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_domain_self_shield_mode_u; + +/* Define the union csr_ncsi_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_cerr : 1; /* [0] */ + u32 rsv_21 : 3; /* [3:1] */ + u32 ram1_cerr : 1; /* [4] */ + u32 rsv_22 : 3; /* [7:5] */ + u32 ram2_cerr : 1; /* [8] */ + u32 rsv_23 : 3; /* [11:9] */ + u32 ram3_cerr : 1; /* [12] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram_cerr_u; + +/* Define the union csr_ncsi_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_err_addr : 7; /* [6:0] */ + u32 rsv_25 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram0_ecc_err_addr_u; + +/* Define the union csr_ncsi_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram1_err_addr : 5; /* [4:0] */ + u32 rsv_26 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram1_ecc_err_addr_u; + +/* Define the union csr_ncsi_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram2_err_addr : 5; /* [4:0] */ + u32 rsv_27 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram2_ecc_err_addr_u; + +/* Define the union csr_ncsi_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram3_err_addr : 8; /* [7:0] */ + u32 rsv_28 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_ram3_ecc_err_addr_u; + +/* Define the union csr_ncsi_rx_afifo_of_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_afifo_of : 1; /* [0] */ + u32 rsv_29 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_afifo_of_u; + +/* Define the union csr_ncsi_rx_afifo_rcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_afifo_wcnt : 10; /* [9:0] */ + u32 rsv_30 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rx_afifo_rcnt_u; + +/* Define the union csr_ncsi_rcmd_afifo_of_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rcmd_afifo_of : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rcmd_afifo_of_u; + +/* Define the union csr_ncsi_rcmd_afifo_rcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rcmd_afifo_wcnt : 7; /* [6:0] */ + u32 rsv_32 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_rcmd_afifo_rcnt_u; + +/* Define the union csr_ncsi_domain_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_domain_non_stable : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_domain_err_u; + +/* Define the union csr_ncsi_tx_frm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_frm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_frm_cnt_u; + +/* Define the union csr_ncsi_tx_frm_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_frm_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_frm_err_cnt_u; + +/* Define the union csr_ncsi_tx_xon_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_xon_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_xon_cnt_u; + +/* Define the union csr_ncsi_tx_xoff_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_xoff_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_xoff_cnt_u; + +/* Define the union csr_ncsi_tx_xon_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_xon_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_xon_err_cnt_u; + +/* Define the union csr_ncsi_tx_empty_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_empty_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_empty_err_cnt_u; + +/* Define the union csr_ncsi_tx_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_cur_st : 7; /* [6:0] */ + u32 rsv_34 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_tx_cur_st_u; + +/* Define the union csr_ncsi_pause_frm_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pause_frm_cur_st : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_pause_frm_cur_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ncsi_mac_version_u ncsi_mac_version; /* 0 */ + volatile csr_ncsi_int_status_u ncsi_int_status; /* 10 */ + volatile csr_ncsi_int_en_u ncsi_int_en; /* 14 */ + volatile csr_ncsi_int_set_u ncsi_int_set; /* 18 */ + volatile csr_ncsi_int_raw_status_u ncsi_int_raw_status; /* 1C */ + volatile csr_ncsi_tp_ram_tmod_u ncsi_tp_ram_tmod; /* 100 */ + volatile csr_ncsi_mem_power_mode_u ncsi_mem_power_mode; /* 104 */ + volatile csr_ncsi_ram_ecc_bypass_u ncsi_ram_ecc_bypass; /* 108 */ + volatile csr_ncsi_hw_arb_bps_mac_u ncsi_hw_arb_bps_mac; /* 10C */ + volatile csr_ncsi_xon_xoff_len_u ncsi_xon_xoff_len; /* 110 */ + volatile csr_ncsi_xon_frame_u ncsi_xon_frame[16]; /* 114 */ + volatile csr_ncsi_xoff_frame_u ncsi_xoff_frame[16]; /* 154 */ + volatile csr_ncsi_ram_ecc_err_insr_u ncsi_ram_ecc_err_insr; /* 194 */ + volatile csr_ncsi_rx_afifo_level_u ncsi_rx_afifo_level; /* 198 */ + volatile csr_ncsi_rx_afifo_afull_th_u ncsi_rx_afifo_afull_th; /* 19C */ + volatile csr_ncsi_rcmd_afifo_level_u ncsi_rcmd_afifo_level; /* 1A0 */ + volatile csr_ncsi_tx_afifo_level_u ncsi_tx_afifo_level; /* 1A4 */ + volatile csr_ncsi_domain_chk_cnt_u ncsi_domain_chk_cnt; /* 1A8 */ + volatile csr_ncsi_domain_stat_u ncsi_domain_stat; /* 1AC */ + volatile csr_ncsi_domain_self_shield_mode_u ncsi_domain_self_shield_mode; /* 1B0 */ + volatile csr_ncsi_ram_cerr_u ncsi_ram_cerr; /* 300 */ + volatile csr_ncsi_ram0_ecc_err_addr_u ncsi_ram0_ecc_err_addr; /* 304 */ + volatile csr_ncsi_ram1_ecc_err_addr_u ncsi_ram1_ecc_err_addr; /* 308 */ + volatile csr_ncsi_ram2_ecc_err_addr_u ncsi_ram2_ecc_err_addr; /* 30C */ + volatile csr_ncsi_ram3_ecc_err_addr_u ncsi_ram3_ecc_err_addr; /* 310 */ + volatile csr_ncsi_rx_afifo_of_u ncsi_rx_afifo_of; /* 314 */ + volatile csr_ncsi_rx_afifo_rcnt_u ncsi_rx_afifo_rcnt; /* 318 */ + volatile csr_ncsi_rcmd_afifo_of_u ncsi_rcmd_afifo_of; /* 31C */ + volatile csr_ncsi_rcmd_afifo_rcnt_u ncsi_rcmd_afifo_rcnt; /* 320 */ + volatile csr_ncsi_domain_err_u ncsi_domain_err; /* 324 */ + volatile csr_ncsi_tx_frm_cnt_u ncsi_tx_frm_cnt; /* 400 */ + volatile csr_ncsi_tx_frm_err_cnt_u ncsi_tx_frm_err_cnt; /* 404 */ + volatile csr_ncsi_tx_xon_cnt_u ncsi_tx_xon_cnt; /* 408 */ + volatile csr_ncsi_tx_xoff_cnt_u ncsi_tx_xoff_cnt; /* 40C */ + volatile csr_ncsi_tx_xon_err_cnt_u ncsi_tx_xon_err_cnt; /* 410 */ + volatile csr_ncsi_tx_empty_err_cnt_u ncsi_tx_empty_err_cnt; /* 414 */ + volatile csr_ncsi_tx_cur_st_u ncsi_tx_cur_st; /* 500 */ + volatile csr_ncsi_pause_frm_cur_st_u ncsi_pause_frm_cur_st; /* 504 */ +} S_ncsi_mac_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ncsi_mac_csr */ +extern volatile S_ncsi_mac_csr_REGS_TYPE *gopncsi_mac_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetNCSI_MAC_VERSION_ncsi_mac_version(unsigned int uncsi_mac_version); +int iSetNCSI_INT_STATUS_mac_fifo_err_int_status(unsigned int umac_fifo_err_int_status); +int iSetNCSI_INT_STATUS_ram0_ucerr_int_status(unsigned int uram0_ucerr_int_status); +int iSetNCSI_INT_STATUS_ram1_ucerr_int_status(unsigned int uram1_ucerr_int_status); +int iSetNCSI_INT_STATUS_ram2_ucerr_int_status(unsigned int uram2_ucerr_int_status); +int iSetNCSI_INT_STATUS_ram3_ucerr_int_status(unsigned int uram3_ucerr_int_status); +int iSetNCSI_INT_STATUS_ram4_ucerr_int_status(unsigned int uram4_ucerr_int_status); +int iSetNCSI_INT_STATUS_ncsi_domain_non_stable_int_status(unsigned int uncsi_domain_non_stable_int_status); +int iSetNCSI_INT_EN_mac_fifo_err_int_en(unsigned int umac_fifo_err_int_en); +int iSetNCSI_INT_EN_ram0_ucerr_int_en(unsigned int uram0_ucerr_int_en); +int iSetNCSI_INT_EN_ram1_ucerr_int_en(unsigned int uram1_ucerr_int_en); +int iSetNCSI_INT_EN_ram2_ucerr_int_en(unsigned int uram2_ucerr_int_en); +int iSetNCSI_INT_EN_ram3_ucerr_int_en(unsigned int uram3_ucerr_int_en); +int iSetNCSI_INT_EN_ram4_ucerr_int_en(unsigned int uram4_ucerr_int_en); +int iSetNCSI_INT_EN_ncsi_domain_non_stable_int_en(unsigned int uncsi_domain_non_stable_int_en); +int iSetNCSI_INT_SET_mac_fifo_err_int_set(unsigned int umac_fifo_err_int_set); +int iSetNCSI_INT_SET_ram0_ucerr_int_set(unsigned int uram0_ucerr_int_set); +int iSetNCSI_INT_SET_ram1_ucerr_int_set(unsigned int uram1_ucerr_int_set); +int iSetNCSI_INT_SET_ram2_ucerr_int_set(unsigned int uram2_ucerr_int_set); +int iSetNCSI_INT_SET_ram3_ucerr_int_set(unsigned int uram3_ucerr_int_set); +int iSetNCSI_INT_SET_ram4_ucerr_int_set(unsigned int uram4_ucerr_int_set); +int iSetNCSI_INT_SET_ncsi_domain_non_stable_int_set(unsigned int uncsi_domain_non_stable_int_set); +int iSetNCSI_INT_RAW_STATUS_mac_fifo_err_int_raw_status(unsigned int umac_fifo_err_int_raw_status); +int iSetNCSI_INT_RAW_STATUS_ram0_ucerr_int_raw_status(unsigned int uram0_ucerr_int_raw_status); +int iSetNCSI_INT_RAW_STATUS_ram1_ucerr_int_raw_status(unsigned int uram1_ucerr_int_raw_status); +int iSetNCSI_INT_RAW_STATUS_ram2_ucerr_int_raw_status(unsigned int uram2_ucerr_int_raw_status); +int iSetNCSI_INT_RAW_STATUS_ram3_ucerr_int_raw_status(unsigned int uram3_ucerr_int_raw_status); +int iSetNCSI_INT_RAW_STATUS_ram4_ucerr_int_raw_status(unsigned int uram4_ucerr_int_raw_status); +int iSetNCSI_INT_RAW_STATUS_ncsi_domain_non_stable_int_raw_status(unsigned int uncsi_domain_non_stable_int_raw_status); +int iSetNCSI_TP_RAM_TMOD_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetNCSI_MEM_POWER_MODE_mem_power_mode(unsigned int umem_power_mode); +int iSetNCSI_RAM_ECC_BYPASS_ecc_bypass(unsigned int uecc_bypass); +int iSetNCSI_HW_ARB_BPS_MAC_hw_arb_bps_mac(unsigned int uhw_arb_bps_mac); +int iSetNCSI_XON_XOFF_LEN_xon_frame_len(unsigned int uxon_frame_len); +int iSetNCSI_XON_XOFF_LEN_xoff_frame_len(unsigned int uxoff_frame_len); +int iSetNCSI_XON_FRAME_xon_frame(unsigned int uxon_frame); +int iSetNCSI_XOFF_FRAME_xoff_frame(unsigned int uxoff_frame); +int iSetNCSI_RAM_ECC_ERR_INSR_ram0_cerr_insr(unsigned int uram0_cerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram1_cerr_insr(unsigned int uram1_cerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram2_cerr_insr(unsigned int uram2_cerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram3_cerr_insr(unsigned int uram3_cerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram0_ucerr_insr(unsigned int uram0_ucerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram1_ucerr_insr(unsigned int uram1_ucerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram2_ucerr_insr(unsigned int uram2_ucerr_insr); +int iSetNCSI_RAM_ECC_ERR_INSR_ram3_ucerr_insr(unsigned int uram3_ucerr_insr); +int iSetNCSI_RX_AFIFO_LEVEL_rx_afifo_low_level(unsigned int urx_afifo_low_level); +int iSetNCSI_RX_AFIFO_LEVEL_rx_afifo_high_level(unsigned int urx_afifo_high_level); +int iSetNCSI_RX_AFIFO_AFULL_TH_rx_afifo_afull_th(unsigned int urx_afifo_afull_th); +int iSetNCSI_RCMD_AFIFO_LEVEL_rcmd_afifo_afull_th(unsigned int urcmd_afifo_afull_th); +int iSetNCSI_TX_AFIFO_LEVEL_tx_afifo_afull_th(unsigned int utx_afifo_afull_th); +int iSetNCSI_DOMAIN_CHK_CNT_ncsi_domain_chk_cnt(unsigned int uncsi_domain_chk_cnt); +int iSetNCSI_DOMAIN_CHK_CNT_ncsi_domain_jitter_max(unsigned int uncsi_domain_jitter_max); +int iSetNCSI_DOMAIN_STAT_ncsi_domain_rdy(unsigned int uncsi_domain_rdy); +int iSetNCSI_DOMAIN_STAT_ncsi_domain_rw_en(unsigned int uncsi_domain_rw_en); +int iSetNCSI_DOMAIN_SELF_SHIELD_MODE_ncsi_domain_self_shield_mode(unsigned int uncsi_domain_self_shield_mode); +int iSetNCSI_RAM_CERR_ram0_cerr(unsigned int uram0_cerr); +int iSetNCSI_RAM_CERR_ram1_cerr(unsigned int uram1_cerr); +int iSetNCSI_RAM_CERR_ram2_cerr(unsigned int uram2_cerr); +int iSetNCSI_RAM_CERR_ram3_cerr(unsigned int uram3_cerr); +int iSetNCSI_RAM0_ECC_ERR_ADDR_ram0_err_addr(unsigned int uram0_err_addr); +int iSetNCSI_RAM1_ECC_ERR_ADDR_ram1_err_addr(unsigned int uram1_err_addr); +int iSetNCSI_RAM2_ECC_ERR_ADDR_ram2_err_addr(unsigned int uram2_err_addr); +int iSetNCSI_RAM3_ECC_ERR_ADDR_ram3_err_addr(unsigned int uram3_err_addr); +int iSetNCSI_RX_AFIFO_OF_rx_afifo_of(unsigned int urx_afifo_of); +int iSetNCSI_RX_AFIFO_RCNT_rx_afifo_wcnt(unsigned int urx_afifo_wcnt); +int iSetNCSI_RCMD_AFIFO_OF_rcmd_afifo_of(unsigned int urcmd_afifo_of); +int iSetNCSI_RCMD_AFIFO_RCNT_rcmd_afifo_wcnt(unsigned int urcmd_afifo_wcnt); +int iSetNCSI_DOMAIN_ERR_ncsi_domain_non_stable(unsigned int uncsi_domain_non_stable); +int iSetNCSI_TX_FRM_CNT_tx_frm_cnt(unsigned int utx_frm_cnt); +int iSetNCSI_TX_FRM_ERR_CNT_tx_frm_err_cnt(unsigned int utx_frm_err_cnt); +int iSetNCSI_TX_XON_CNT_tx_xon_cnt(unsigned int utx_xon_cnt); +int iSetNCSI_TX_XOFF_CNT_tx_xoff_cnt(unsigned int utx_xoff_cnt); +int iSetNCSI_TX_XON_ERR_CNT_tx_xon_err_cnt(unsigned int utx_xon_err_cnt); +int iSetNCSI_TX_EMPTY_ERR_CNT_tx_empty_err_cnt(unsigned int utx_empty_err_cnt); +int iSetNCSI_TX_CUR_ST_tx_cur_st(unsigned int utx_cur_st); +int iSetNCSI_PAUSE_FRM_CUR_ST_pause_frm_cur_st(unsigned int upause_frm_cur_st); + +/* Define the union csr_duplex_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 duplex_sel : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_duplex_type_u; + +/* Define the union csr_fd_fc_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fd_fc_type : 16; /* [15:0] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fd_fc_type_u; + +/* Define the union csr_fc_tx_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_tx_timer : 16; /* [15:0] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fc_tx_timer_u; + +/* Define the union csr_fd_fc_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fd_fc_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fd_fc_addr_low_u; + +/* Define the union csr_fd_fc_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fd_fc_addr_high : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fd_fc_addr_high_u; + +/* Define the union csr_ipg_tx_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipg_tx_timer : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipg_tx_timer_u; + +/* Define the union csr_pause_thr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pause_thr : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pause_thr_u; + +/* Define the union csr_max_frm_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_frm_size : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_max_frm_size_u; + +/* Define the union csr_port_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_mode : 4; /* [3:0] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 rmii_clk_edge : 1; /* [8] */ + u32 rmii_rst : 1; /* [9] */ + u32 rsv_8 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_mode_u; + +/* Define the union csr_port_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 1; /* [0] */ + u32 rx_en : 1; /* [1] */ + u32 tx_en : 1; /* [2] */ + u32 rsv_10 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_en_u; + +/* Define the union csr_pause_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fdfc : 1; /* [0] */ + u32 tx_fdfc : 1; /* [1] */ + u32 tx_hdfc : 1; /* [2] */ + u32 rsv_11 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pause_en_u; + +/* Define the union csr_short_runts_thr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 short_runts_thr : 5; /* [4:0] */ + u32 rsv_12 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_short_runts_thr_u; + +/* Define the union csr_an_neg_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_an_neg_state_u; + +/* Define the union csr_tx_local_page_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_local_page_u; + +/* Define the union csr_transmit_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_15 : 6; /* [5:0] */ + u32 crc_add : 1; /* [6] */ + u32 pad_enable : 1; /* [7] */ + u32 rsv_16 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_transmit_control_u; + +/* Define the union csr_rec_filt_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 uc_match_en : 1; /* [0] */ + u32 mc_match_en : 1; /* [1] */ + u32 bc_drop_en : 1; /* [2] */ + u32 rsv_17 : 1; /* [3] */ + u32 pause_frm_pass : 1; /* [4] */ + u32 crc_err_pass : 1; /* [5] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rec_filt_control_u; + +/* Define the union csr_ptp_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_config_u; + +/* Define the union csr_rx_octets_total_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_octets_total_ok : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_octets_total_ok_u; + +/* Define the union csr_rx_octets_bad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_octets_bad : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_octets_bad_u; + +/* Define the union csr_rx_uc_pkts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_uc_pkts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_uc_pkts_u; + +/* Define the union csr_rx_mc_pkts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mc_pkts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_mc_pkts_u; + +/* Define the union csr_rx_bc_pkts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bc_pkts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_bc_pkts_u; + +/* Define the union csr_rx_pkts_64octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_64octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_64octets_u; + +/* Define the union csr_rx_pkts_65to127octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_65to127octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_65to127octets_u; + +/* Define the union csr_rx_pkts_128to255octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_128to255octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_128to255octets_u; + +/* Define the union csr_rx_pkts_255to511octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_256to511octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_255to511octets_u; + +/* Define the union csr_rx_pkts_512to1023octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_512to1023octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_512to1023octets_u; + +/* Define the union csr_rx_pkts_1024to1518octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_1024to1518octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_1024to1518octets_u; + +/* Define the union csr_rx_pkts_1519tomaxoctets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pkts_1519tomaxoctes : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkts_1519tomaxoctets_u; + +/* Define the union csr_rx_fcs_errors_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fcs_errors : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_fcs_errors_u; + +/* Define the union csr_rx_tagged_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tagged : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tagged_u; + +/* Define the union csr_rx_data_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_data_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_data_err_u; + +/* Define the union csr_rx_align_errors_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_align_errors : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_align_errors_u; + +/* Define the union csr_rx_long_errors_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_long_errors : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_long_errors_u; + +/* Define the union csr_rx_jabber_errors_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_jabber_errors : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_jabber_errors_u; + +/* Define the union csr_rx_pause_maccontrol_framcounter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_pause_maccontrol_framecounter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pause_maccontrol_framcounter_u; + +/* Define the union csr_rx_unknown_maccontrol_framcounter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_unknown_maccontrol_framecounter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_unknown_maccontrol_framcounter_u; + +/* Define the union csr_rx_very_long_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_very_long_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_very_long_err_cnt_u; + +/* Define the union csr_rx_runt_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_runt_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_runt_err_cnt_u; + +/* Define the union csr_rx_short_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_short_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_short_err_cnt_u; + +/* Define the union csr_rx_filt_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_filt_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_filt_pkt_cnt_u; + +/* Define the union csr_rx_octets_total_filt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_octets_total_filt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_octets_total_filt_u; + +/* Define the union csr_octets_transmitted_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octets_transmitted_ok : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octets_transmitted_ok_u; + +/* Define the union csr_octets_transmitted_bad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octets_transmitted_bad : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octets_transmitted_bad_u; + +/* Define the union csr_tx_uc_pkts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_uc_pkts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_uc_pkts_u; + +/* Define the union csr_tx_mc_pkts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_mc_pkts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_mc_pkts_u; + +/* Define the union csr_tx_bc_pkts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bc_pkts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_bc_pkts_u; + +/* Define the union csr_tx_pkts_64octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_64octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_64octets_u; + +/* Define the union csr_tx_pkts_65to127octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_65to127octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_65to127octets_u; + +/* Define the union csr_tx_pkts_128to255octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_128to255octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_128to255octets_u; + +/* Define the union csr_tx_pkts_255to511octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_256to511octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_255to511octets_u; + +/* Define the union csr_tx_pkts_512to1023octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_512to1023octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_512to1023octets_u; + +/* Define the union csr_tx_pkts_1024to1518octets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_1024to1518octets : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_1024to1518octets_u; + +/* Define the union csr_tx_pkts_1519tomaxoctets_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pkts_1519tomaxoctes : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pkts_1519tomaxoctets_u; + +/* Define the union csr_tx_underrun_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_underrun : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_underrun_u; + +/* Define the union csr_tx_tagged_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tagged : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tagged_u; + +/* Define the union csr_tx_crc_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crc_error : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crc_error_u; + +/* Define the union csr_tx_pause_frames_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pause_frames : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pause_frames_u; + +/* Define the union csr_line_loop_back_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 line_loop_back : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_line_loop_back_u; + +/* Define the union csr_cf_crc_strip_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_crc_strip : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cf_crc_strip_u; + +/* Define the union csr_mode_change_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mode_change_en : 1; /* [0] */ + u32 rsv_22 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mode_change_en_u; + +/* Define the union csr_loop_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_23 : 1; /* [0] */ + u32 cf_ext_drive_lp : 1; /* [1] */ + u32 cf2mi_lp_en : 1; /* [2] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_loop_reg_u; + +/* Define the union csr_recv_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_25 : 3; /* [2:0] */ + u32 strip_pad_en : 1; /* [3] */ + u32 runt_pkt_en : 1; /* [4] */ + u32 rsv_26 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_recv_control_u; + +/* Define the union csr_vlan_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vlan_code_u; + +/* Define the union csr_rx_overrun_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_overrun_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_overrun_cnt_u; + +/* Define the union csr_rx_lengthfield_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_lengthfield_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lengthfield_err_cnt_u; + +/* Define the union csr_rx_fail_comma_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fail_comma_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_fail_comma_cnt_u; + +/* Define the union csr_station_addr_low_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_0_u; + +/* Define the union csr_station_addr_high_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_0 : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_0_u; + +/* Define the union csr_station_addr_low_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_1_u; + +/* Define the union csr_station_addr_high_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_1 : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_1_u; + +/* Define the union csr_station_addr_low_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_2_u; + +/* Define the union csr_station_addr_high_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_2 : 16; /* [15:0] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_2_u; + +/* Define the union csr_station_addr_low_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_3_u; + +/* Define the union csr_station_addr_high_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_3 : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_3_u; + +/* Define the union csr_station_addr_low_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_4_u; + +/* Define the union csr_station_addr_high_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_4 : 16; /* [15:0] */ + u32 rsv_32 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_4_u; + +/* Define the union csr_station_addr_low_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_5_u; + +/* Define the union csr_station_addr_high_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_5 : 16; /* [15:0] */ + u32 rsv_33 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_5_u; + +/* Define the union csr_station_addr_low_msk_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_msk_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_msk_0_u; + +/* Define the union csr_station_addr_high_msk_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_msk_0 : 16; /* [15:0] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_msk_0_u; + +/* Define the union csr_station_addr_low_msk_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_low_msk_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_low_msk_1_u; + +/* Define the union csr_station_addr_high_msk_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 station_addr_high_msk_1 : 16; /* [15:0] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_station_addr_high_msk_1_u; + +/* Define the union csr_mac_skip_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_skip_len : 6; /* [5:0] */ + u32 mac_skip_crc : 1; /* [6] */ + u32 rsv_36 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mac_skip_len_u; + +/* Define the union csr_debug_rd_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_37 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_debug_rd_data_u; + +/* Define the union csr_debug_pkt_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_38 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_debug_pkt_ptr_u; + +/* Define the union csr_debug_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_39 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_debug_en_u; + +/* Define the union csr_intr_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intr_state_u; + +/* Define the union csr_intr_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_41 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intr_clr_u; + +/* Define the union csr_intr_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_42 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intr_msk_u; + +/* Define the union csr_seq_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_43 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_seq_id_u; + +/* Define the union csr_stp_63_to_32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_44 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stp_63_to_32_u; + +/* Define the union csr_stp_31_to_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_45 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stp_31_to_0_u; + +/* Define the union csr_dbg_grp0_vld_words_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_46 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbg_grp0_vld_words_u; + +/* Define the union csr_dbg_grp1_vld_words_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbg_grp1_vld_words_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_duplex_type_u duplex_type; /* 8 */ + volatile csr_fd_fc_type_u fd_fc_type; /* C */ + volatile csr_fc_tx_timer_u fc_tx_timer; /* 1C */ + volatile csr_fd_fc_addr_low_u fd_fc_addr_low; /* 20 */ + volatile csr_fd_fc_addr_high_u fd_fc_addr_high; /* 24 */ + volatile csr_ipg_tx_timer_u ipg_tx_timer; /* 30 */ + volatile csr_pause_thr_u pause_thr; /* 38 */ + volatile csr_max_frm_size_u max_frm_size; /* 3C */ + volatile csr_port_mode_u port_mode; /* 40 */ + volatile csr_port_en_u port_en; /* 44 */ + volatile csr_pause_en_u pause_en; /* 48 */ + volatile csr_short_runts_thr_u short_runts_thr; /* 50 */ + volatile csr_an_neg_state_u an_neg_state; /* 58 */ + volatile csr_tx_local_page_u tx_local_page; /* 5C */ + volatile csr_transmit_control_u transmit_control; /* 60 */ + volatile csr_rec_filt_control_u rec_filt_control; /* 64 */ + volatile csr_ptp_config_u ptp_config; /* 74 */ + volatile csr_rx_octets_total_ok_u rx_octets_total_ok; /* 80 */ + volatile csr_rx_octets_bad_u rx_octets_bad; /* 84 */ + volatile csr_rx_uc_pkts_u rx_uc_pkts; /* 88 */ + volatile csr_rx_mc_pkts_u rx_mc_pkts; /* 8C */ + volatile csr_rx_bc_pkts_u rx_bc_pkts; /* 90 */ + volatile csr_rx_pkts_64octets_u rx_pkts_64octets; /* 94 */ + volatile csr_rx_pkts_65to127octets_u rx_pkts_65to127octets; /* 98 */ + volatile csr_rx_pkts_128to255octets_u rx_pkts_128to255octets; /* 9C */ + volatile csr_rx_pkts_255to511octets_u rx_pkts_255to511octets; /* A0 */ + volatile csr_rx_pkts_512to1023octets_u rx_pkts_512to1023octets; /* A4 */ + volatile csr_rx_pkts_1024to1518octets_u rx_pkts_1024to1518octets; /* A8 */ + volatile csr_rx_pkts_1519tomaxoctets_u rx_pkts_1519tomaxoctets; /* AC */ + volatile csr_rx_fcs_errors_u rx_fcs_errors; /* B0 */ + volatile csr_rx_tagged_u rx_tagged; /* B4 */ + volatile csr_rx_data_err_u rx_data_err; /* B8 */ + volatile csr_rx_align_errors_u rx_align_errors; /* BC */ + volatile csr_rx_long_errors_u rx_long_errors; /* C0 */ + volatile csr_rx_jabber_errors_u rx_jabber_errors; /* C4 */ + volatile csr_rx_pause_maccontrol_framcounter_u rx_pause_maccontrol_framcounter; /* C8 */ + volatile csr_rx_unknown_maccontrol_framcounter_u rx_unknown_maccontrol_framcounter; /* CC */ + volatile csr_rx_very_long_err_cnt_u rx_very_long_err_cnt; /* D0 */ + volatile csr_rx_runt_err_cnt_u rx_runt_err_cnt; /* D4 */ + volatile csr_rx_short_err_cnt_u rx_short_err_cnt; /* D8 */ + volatile csr_rx_filt_pkt_cnt_u rx_filt_pkt_cnt; /* E8 */ + volatile csr_rx_octets_total_filt_u rx_octets_total_filt; /* EC */ + volatile csr_octets_transmitted_ok_u octets_transmitted_ok; /* 100 */ + volatile csr_octets_transmitted_bad_u octets_transmitted_bad; /* 104 */ + volatile csr_tx_uc_pkts_u tx_uc_pkts; /* 108 */ + volatile csr_tx_mc_pkts_u tx_mc_pkts; /* 10C */ + volatile csr_tx_bc_pkts_u tx_bc_pkts; /* 110 */ + volatile csr_tx_pkts_64octets_u tx_pkts_64octets; /* 114 */ + volatile csr_tx_pkts_65to127octets_u tx_pkts_65to127octets; /* 118 */ + volatile csr_tx_pkts_128to255octets_u tx_pkts_128to255octets; /* 11C */ + volatile csr_tx_pkts_255to511octets_u tx_pkts_255to511octets; /* 120 */ + volatile csr_tx_pkts_512to1023octets_u tx_pkts_512to1023octets; /* 124 */ + volatile csr_tx_pkts_1024to1518octets_u tx_pkts_1024to1518octets; /* 128 */ + volatile csr_tx_pkts_1519tomaxoctets_u tx_pkts_1519tomaxoctets; /* 12C */ + volatile csr_tx_underrun_u tx_underrun; /* 150 */ + volatile csr_tx_tagged_u tx_tagged; /* 154 */ + volatile csr_tx_crc_error_u tx_crc_error; /* 158 */ + volatile csr_tx_pause_frames_u tx_pause_frames; /* 15C */ + volatile csr_line_loop_back_u line_loop_back; /* 1A8 */ + volatile csr_cf_crc_strip_u cf_crc_strip; /* 1B0 */ + volatile csr_mode_change_en_u mode_change_en; /* 1B4 */ + volatile csr_loop_reg_u loop_reg; /* 1DC */ + volatile csr_recv_control_u recv_control; /* 1E0 */ + volatile csr_vlan_code_u vlan_code; /* 1E8 */ + volatile csr_rx_overrun_cnt_u rx_overrun_cnt; /* 1EC */ + volatile csr_rx_lengthfield_err_cnt_u rx_lengthfield_err_cnt; /* 1F4 */ + volatile csr_rx_fail_comma_cnt_u rx_fail_comma_cnt; /* 1F8 */ + volatile csr_station_addr_low_0_u station_addr_low_0; /* 200 */ + volatile csr_station_addr_high_0_u station_addr_high_0; /* 204 */ + volatile csr_station_addr_low_1_u station_addr_low_1; /* 208 */ + volatile csr_station_addr_high_1_u station_addr_high_1; /* 20C */ + volatile csr_station_addr_low_2_u station_addr_low_2; /* 210 */ + volatile csr_station_addr_high_2_u station_addr_high_2; /* 214 */ + volatile csr_station_addr_low_3_u station_addr_low_3; /* 218 */ + volatile csr_station_addr_high_3_u station_addr_high_3; /* 21C */ + volatile csr_station_addr_low_4_u station_addr_low_4; /* 220 */ + volatile csr_station_addr_high_4_u station_addr_high_4; /* 224 */ + volatile csr_station_addr_low_5_u station_addr_low_5; /* 228 */ + volatile csr_station_addr_high_5_u station_addr_high_5; /* 22C */ + volatile csr_station_addr_low_msk_0_u station_addr_low_msk_0; /* 230 */ + volatile csr_station_addr_high_msk_0_u station_addr_high_msk_0; /* 234 */ + volatile csr_station_addr_low_msk_1_u station_addr_low_msk_1; /* 238 */ + volatile csr_station_addr_high_msk_1_u station_addr_high_msk_1; /* 23C */ + volatile csr_mac_skip_len_u mac_skip_len; /* 240 */ + volatile csr_debug_rd_data_u debug_rd_data[64]; /* 244 */ + volatile csr_debug_pkt_ptr_u debug_pkt_ptr; /* 344 */ + volatile csr_debug_en_u debug_en; /* 348 */ + volatile csr_intr_state_u intr_state; /* 34C */ + volatile csr_intr_clr_u intr_clr; /* 350 */ + volatile csr_intr_msk_u intr_msk; /* 354 */ + volatile csr_seq_id_u seq_id; /* 358 */ + volatile csr_stp_63_to_32_u stp_63_to_32; /* 35C */ + volatile csr_stp_31_to_0_u stp_31_to_0; /* 360 */ + volatile csr_dbg_grp0_vld_words_u dbg_grp0_vld_words; /* 364 */ + volatile csr_dbg_grp1_vld_words_u dbg_grp1_vld_words; /* 368 */ +} S_ncsi_mac_core_REGS_TYPE; + +/* Declare the struct pointor of the module ncsi_mac_core */ +extern volatile S_ncsi_mac_core_REGS_TYPE *gopncsi_mac_coreAllReg; + +/* Declare the functions that set the member value */ +int iSetDUPLEX_TYPE_duplex_sel(unsigned int uduplex_sel); +int iSetFD_FC_TYPE_fd_fc_type(unsigned int ufd_fc_type); +int iSetFC_TX_TIMER_fc_tx_timer(unsigned int ufc_tx_timer); +int iSetFD_FC_ADDR_LOW_fd_fc_addr_low(unsigned int ufd_fc_addr_low); +int iSetFD_FC_ADDR_HIGH_fd_fc_addr_high(unsigned int ufd_fc_addr_high); +int iSetIPG_TX_TIMER_ipg_tx_timer(unsigned int uipg_tx_timer); +int iSetPAUSE_THR_pause_thr(unsigned int upause_thr); +int iSetMAX_FRM_SIZE_max_frm_size(unsigned int umax_frm_size); +int iSetPORT_MODE_port_mode(unsigned int uport_mode); +int iSetPORT_MODE_rmii_clk_edge(unsigned int urmii_clk_edge); +int iSetPORT_MODE_rmii_rst(unsigned int urmii_rst); +int iSetPORT_EN_rx_en(unsigned int urx_en); +int iSetPORT_EN_tx_en(unsigned int utx_en); +int iSetPAUSE_EN_rx_fdfc(unsigned int urx_fdfc); +int iSetPAUSE_EN_tx_fdfc(unsigned int utx_fdfc); +int iSetPAUSE_EN_tx_hdfc(unsigned int utx_hdfc); +int iSetSHORT_RUNTS_THR_short_runts_thr(unsigned int ushort_runts_thr); + + +int iSetTRANSMIT_CONTROL_crc_add(unsigned int ucrc_add); +int iSetTRANSMIT_CONTROL_pad_enable(unsigned int upad_enable); +int iSetREC_FILT_CONTROL_uc_match_en(unsigned int uuc_match_en); +int iSetREC_FILT_CONTROL_mc_match_en(unsigned int umc_match_en); +int iSetREC_FILT_CONTROL_bc_drop_en(unsigned int ubc_drop_en); +int iSetREC_FILT_CONTROL_pause_frm_pass(unsigned int upause_frm_pass); +int iSetREC_FILT_CONTROL_crc_err_pass(unsigned int ucrc_err_pass); + +int iSetRX_OCTETS_TOTAL_OK_rx_octets_total_ok(unsigned int urx_octets_total_ok); +int iSetRX_OCTETS_BAD_rx_octets_bad(unsigned int urx_octets_bad); +int iSetRX_UC_PKTS_rx_uc_pkts(unsigned int urx_uc_pkts); +int iSetRX_MC_PKTS_rx_mc_pkts(unsigned int urx_mc_pkts); +int iSetRX_BC_PKTS_rx_bc_pkts(unsigned int urx_bc_pkts); +int iSetRX_PKTS_64OCTETS_rx_pkts_64octets(unsigned int urx_pkts_64octets); +int iSetRX_PKTS_65TO127OCTETS_rx_pkts_65to127octets(unsigned int urx_pkts_65to127octets); +int iSetRX_PKTS_128TO255OCTETS_rx_pkts_128to255octets(unsigned int urx_pkts_128to255octets); +int iSetRX_PKTS_255TO511OCTETS_rx_pkts_256to511octets(unsigned int urx_pkts_256to511octets); +int iSetRX_PKTS_512TO1023OCTETS_rx_pkts_512to1023octets(unsigned int urx_pkts_512to1023octets); +int iSetRX_PKTS_1024TO1518OCTETS_rx_pkts_1024to1518octets(unsigned int urx_pkts_1024to1518octets); +int iSetRX_PKTS_1519TOMAXOCTETS_rx_pkts_1519tomaxoctes(unsigned int urx_pkts_1519tomaxoctes); +int iSetRX_FCS_ERRORS_rx_fcs_errors(unsigned int urx_fcs_errors); +int iSetRX_TAGGED_rx_tagged(unsigned int urx_tagged); +int iSetRX_DATA_ERR_rx_data_err(unsigned int urx_data_err); +int iSetRX_ALIGN_ERRORS_rx_align_errors(unsigned int urx_align_errors); +int iSetRX_LONG_ERRORS_rx_long_errors(unsigned int urx_long_errors); +int iSetRX_JABBER_ERRORS_rx_jabber_errors(unsigned int urx_jabber_errors); +int iSetRX_PAUSE_MACCONTROL_FRAMCOUNTER_rx_pause_maccontrol_framecounter( + unsigned int urx_pause_maccontrol_framecounter); +int iSetRX_UNKNOWN_MACCONTROL_FRAMCOUNTER_rx_unknown_maccontrol_framecounter( + unsigned int urx_unknown_maccontrol_framecounter); +int iSetRX_VERY_LONG_ERR_CNT_rx_very_long_err_cnt(unsigned int urx_very_long_err_cnt); +int iSetRX_RUNT_ERR_CNT_rx_runt_err_cnt(unsigned int urx_runt_err_cnt); +int iSetRX_SHORT_ERR_CNT_rx_short_err_cnt(unsigned int urx_short_err_cnt); +int iSetRX_FILT_PKT_CNT_rx_filt_pkt_cnt(unsigned int urx_filt_pkt_cnt); +int iSetRX_OCTETS_TOTAL_FILT_rx_octets_total_filt(unsigned int urx_octets_total_filt); +int iSetOCTETS_TRANSMITTED_OK_octets_transmitted_ok(unsigned int uoctets_transmitted_ok); +int iSetOCTETS_TRANSMITTED_BAD_octets_transmitted_bad(unsigned int uoctets_transmitted_bad); +int iSetTX_UC_PKTS_tx_uc_pkts(unsigned int utx_uc_pkts); +int iSetTX_MC_PKTS_tx_mc_pkts(unsigned int utx_mc_pkts); +int iSetTX_BC_PKTS_tx_bc_pkts(unsigned int utx_bc_pkts); +int iSetTX_PKTS_64OCTETS_tx_pkts_64octets(unsigned int utx_pkts_64octets); +int iSetTX_PKTS_65TO127OCTETS_tx_pkts_65to127octets(unsigned int utx_pkts_65to127octets); +int iSetTX_PKTS_128TO255OCTETS_tx_pkts_128to255octets(unsigned int utx_pkts_128to255octets); +int iSetTX_PKTS_255TO511OCTETS_tx_pkts_256to511octets(unsigned int utx_pkts_256to511octets); +int iSetTX_PKTS_512TO1023OCTETS_tx_pkts_512to1023octets(unsigned int utx_pkts_512to1023octets); +int iSetTX_PKTS_1024TO1518OCTETS_tx_pkts_1024to1518octets(unsigned int utx_pkts_1024to1518octets); +int iSetTX_PKTS_1519TOMAXOCTETS_tx_pkts_1519tomaxoctes(unsigned int utx_pkts_1519tomaxoctes); +int iSetTX_UNDERRUN_tx_underrun(unsigned int utx_underrun); +int iSetTX_TAGGED_tx_tagged(unsigned int utx_tagged); +int iSetTX_CRC_ERROR_tx_crc_error(unsigned int utx_crc_error); +int iSetTX_PAUSE_FRAMES_tx_pause_frames(unsigned int utx_pause_frames); +int iSetLINE_LOOP_BACK_line_loop_back(unsigned int uline_loop_back); +int iSetCF_CRC_STRIP_cf_crc_strip(unsigned int ucf_crc_strip); +int iSetMODE_CHANGE_EN_mode_change_en(unsigned int umode_change_en); +int iSetLOOP_REG_cf_ext_drive_lp(unsigned int ucf_ext_drive_lp); +int iSetLOOP_REG_cf2mi_lp_en(unsigned int ucf2mi_lp_en); +int iSetRECV_CONTROL_strip_pad_en(unsigned int ustrip_pad_en); +int iSetRECV_CONTROL_runt_pkt_en(unsigned int urunt_pkt_en); + +int iSetRX_OVERRUN_CNT_rx_overrun_cnt(unsigned int urx_overrun_cnt); +int iSetRX_LENGTHFIELD_ERR_CNT_rx_lengthfield_err_cnt(unsigned int urx_lengthfield_err_cnt); +int iSetRX_FAIL_COMMA_CNT_rx_fail_comma_cnt(unsigned int urx_fail_comma_cnt); +int iSetSTATION_ADDR_LOW_0_station_addr_low_0(unsigned int ustation_addr_low_0); +int iSetSTATION_ADDR_HIGH_0_station_addr_high_0(unsigned int ustation_addr_high_0); +int iSetSTATION_ADDR_LOW_1_station_addr_low_1(unsigned int ustation_addr_low_1); +int iSetSTATION_ADDR_HIGH_1_station_addr_high_1(unsigned int ustation_addr_high_1); +int iSetSTATION_ADDR_LOW_2_station_addr_low_2(unsigned int ustation_addr_low_2); +int iSetSTATION_ADDR_HIGH_2_station_addr_high_2(unsigned int ustation_addr_high_2); +int iSetSTATION_ADDR_LOW_3_station_addr_low_3(unsigned int ustation_addr_low_3); +int iSetSTATION_ADDR_HIGH_3_station_addr_high_3(unsigned int ustation_addr_high_3); +int iSetSTATION_ADDR_LOW_4_station_addr_low_4(unsigned int ustation_addr_low_4); +int iSetSTATION_ADDR_HIGH_4_station_addr_high_4(unsigned int ustation_addr_high_4); +int iSetSTATION_ADDR_LOW_5_station_addr_low_5(unsigned int ustation_addr_low_5); +int iSetSTATION_ADDR_HIGH_5_station_addr_high_5(unsigned int ustation_addr_high_5); +int iSetSTATION_ADDR_LOW_MSK_0_station_addr_low_msk_0(unsigned int ustation_addr_low_msk_0); +int iSetSTATION_ADDR_HIGH_MSK_0_station_addr_high_msk_0(unsigned int ustation_addr_high_msk_0); +int iSetSTATION_ADDR_LOW_MSK_1_station_addr_low_msk_1(unsigned int ustation_addr_low_msk_1); +int iSetSTATION_ADDR_HIGH_MSK_1_station_addr_high_msk_1(unsigned int ustation_addr_high_msk_1); +int iSetMAC_SKIP_LEN_mac_skip_len(unsigned int umac_skip_len); +int iSetMAC_SKIP_LEN_mac_skip_crc(unsigned int umac_skip_crc); + + +/* Define the union csr_ckd_int_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_int_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_int_sta_u; + +/* Define the union csr_pll_int_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll_lock : 22; /* [21:0] */ + u32 rsv_0 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll_int_sta_u; + +/* Define the union csr_ckd_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_int_mask_u; + +/* Define the union csr_ckd_pll_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_pll_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_pll_int_mask_u; + +/* Define the union csr_ckd_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_int_set_u; + +/* Define the union csr_ckd_pll_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_pll_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_pll_int_set_u; + +/* Define the union csr_ckd_err_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_err_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_err_sta_u; + +/* Define the union csr_pll_lock_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll_lock_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll_lock_sta_u; + +/* Define the union csr_ckd_ok_int_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_ok_int_sta_u; + +/* Define the union csr_ckd_ok_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_ok_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_ok_int_mask_u; + +/* Define the union csr_ckd_ok_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ckd_ok_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_ok_int_set_u; + +/* Define the union csr_ckd_clk_ok_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cld_ok_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ckd_clk_ok_sta_u; + +/* Define the union csr_det_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 det_clk_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_det_clk_en_u; + +/* Define the union csr_det_pll_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 det_pll_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_det_pll_en_u; + +/* Define the union csr_det_clk_ok_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 det_pll_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_det_clk_ok_en_u; + +/* Define the union csr_det_clk_ok_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clk_ok_cnt : 16; /* [15:0] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_det_clk_ok_cnt_u; + +/* Define the union csr_det_clk_min_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 det_clk_min_width : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_det_clk_min_width_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ckd_int_sta_u ckd_int_sta; /* 10 */ + volatile csr_pll_int_sta_u pll_int_sta; /* 14 */ + volatile csr_ckd_int_mask_u ckd_int_mask; /* 20 */ + volatile csr_ckd_pll_int_mask_u ckd_pll_int_mask; /* 24 */ + volatile csr_ckd_int_set_u ckd_int_set; /* 30 */ + volatile csr_ckd_pll_int_set_u ckd_pll_int_set; /* 34 */ + volatile csr_ckd_err_sta_u ckd_err_sta; /* 40 */ + volatile csr_pll_lock_sta_u pll_lock_sta; /* 44 */ + volatile csr_ckd_ok_int_sta_u ckd_ok_int_sta; /* 48 */ + volatile csr_ckd_ok_int_mask_u ckd_ok_int_mask; /* 4C */ + volatile csr_ckd_ok_int_set_u ckd_ok_int_set; /* 50 */ + volatile csr_ckd_clk_ok_sta_u ckd_clk_ok_sta; /* 54 */ + volatile csr_det_clk_en_u det_clk_en; /* A0 */ + volatile csr_det_pll_en_u det_pll_en; /* A4 */ + volatile csr_det_clk_ok_en_u det_clk_ok_en; /* A8 */ + volatile csr_det_clk_ok_cnt_u det_clk_ok_cnt; /* AC */ + volatile csr_det_clk_min_width_u det_clk_min_width[32]; /* B0 */ +} S_clk_det0_REGS_TYPE; + +/* Declare the struct pointor of the module clk_det0 */ +extern volatile S_clk_det0_REGS_TYPE *gopclk_det0AllReg; + +/* Declare the functions that set the member value */ +int iSetCKD_INT_STA_ckd_int_sta(unsigned int uckd_int_sta); +int iSetPLL_INT_STA_pll_lock(unsigned int upll_lock); +int iSetCKD_INT_MASK_ckd_int_mask(unsigned int uckd_int_mask); +int iSetCKD_PLL_INT_MASK_ckd_pll_int_mask(unsigned int uckd_pll_int_mask); +int iSetCKD_INT_SET_ckd_int_set(unsigned int uckd_int_set); +int iSetCKD_PLL_INT_SET_ckd_pll_int_set(unsigned int uckd_pll_int_set); +int iSetCKD_ERR_STA_ckd_err_sta(unsigned int uckd_err_sta); +int iSetPLL_LOCK_STA_pll_lock_sta(unsigned int upll_lock_sta); + +int iSetCKD_OK_INT_MASK_ckd_ok_int_mask(unsigned int uckd_ok_int_mask); +int iSetCKD_OK_INT_SET_ckd_ok_int_set(unsigned int uckd_ok_int_set); +int iSetCKD_CLK_OK_STA_cld_ok_sta(unsigned int ucld_ok_sta); +int iSetDET_CLK_EN_det_clk_en(unsigned int udet_clk_en); +int iSetDET_PLL_EN_det_pll_en(unsigned int udet_pll_en); +int iSetDET_CLK_OK_EN_det_pll_en(unsigned int udet_pll_en); +int iSetDET_CLK_OK_CNT_clk_ok_cnt(unsigned int uclk_ok_cnt); +int iSetDET_CLK_MIN_WIDTH_det_clk_min_width(unsigned int udet_clk_min_width); + +/* Define the union csr_i2c_awaddr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awaddr0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awaddr0_u; + +/* Define the union csr_i2c_awaddr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awaddr1 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awaddr1_u; + +/* Define the union csr_i2c_awaddr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awaddr2 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awaddr2_u; + +/* Define the union csr_i2c_awaddr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awaddr3 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awaddr3_u; + +/* Define the union csr_i2c_wdata0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata0_u; + +/* Define the union csr_i2c_wdata1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata1_u; + +/* Define the union csr_i2c_wdata2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata2_u; + +/* Define the union csr_i2c_wdata3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata3_u; + +/* Define the union csr_i2c_wdata4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata4_u; + +/* Define the union csr_i2c_wdata5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata5_u; + +/* Define the union csr_i2c_wdata6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata6_u; + +/* Define the union csr_i2c_wdata7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wdata7_u; + +/* Define the union csr_i2c_wstrb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_wstrb : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_wstrb_u; + +/* Define the union csr_i2c_awsize_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awsize : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awsize_u; + +/* Define the union csr_i2c_awid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awid : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awid_u; + +/* Define the union csr_i2c_awlock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awlock : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awlock_u; + +/* Define the union csr_i2c_awcache_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awcache : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awcache_u; + +/* Define the union csr_i2c_awprot_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_awprot : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_awprot_u; + +/* Define the union csr_i2c_araddr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_araddr0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_araddr0_u; + +/* Define the union csr_i2c_araddr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_araddr1 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_araddr1_u; + +/* Define the union csr_i2c_araddr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_araddr2 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_araddr2_u; + +/* Define the union csr_i2c_araddr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_araddr3 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_araddr3_u; + +/* Define the union csr_i2c_arsize_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_arsize : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_arsize_u; + +/* Define the union csr_i2c_arid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_arid : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_arid_u; + +/* Define the union csr_i2c_arlock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_arlock : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_arlock_u; + +/* Define the union csr_i2c_arcache_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_arcache : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_arcache_u; + +/* Define the union csr_i2c_arprot_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_arprot : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_arprot_u; + +/* Define the union csr_axi_bresp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_bresp : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_bresp_u; + +/* Define the union csr_axi_bid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_bid : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_bid_u; + +/* Define the union csr_axi_rresp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rresp : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rresp_u; + +/* Define the union csr_axi_rdata0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata0 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata0_u; + +/* Define the union csr_axi_rdata1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata1 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata1_u; + +/* Define the union csr_axi_rdata2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata2 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata2_u; + +/* Define the union csr_axi_rdata3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata3 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata3_u; + +/* Define the union csr_axi_rdata4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata4 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata4_u; + +/* Define the union csr_axi_rdata5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata5 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata5_u; + +/* Define the union csr_axi_rdata6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata6 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata6_u; + +/* Define the union csr_axi_rdata7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rdata7 : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rdata7_u; + +/* Define the union csr_axi_rid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rid : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rid_u; + +/* Define the union csr_wr_rd_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_rd_cmd : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wr_rd_cmd_u; + +/* Define the union csr_version_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 version_number : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_version_number_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_i2c_awaddr0_u i2c_awaddr0; /* 0 */ + volatile csr_i2c_awaddr1_u i2c_awaddr1; /* 1 */ + volatile csr_i2c_awaddr2_u i2c_awaddr2; /* 2 */ + volatile csr_i2c_awaddr3_u i2c_awaddr3; /* 3 */ + volatile csr_i2c_wdata0_u i2c_wdata0; /* 4 */ + volatile csr_i2c_wdata1_u i2c_wdata1; /* 5 */ + volatile csr_i2c_wdata2_u i2c_wdata2; /* 6 */ + volatile csr_i2c_wdata3_u i2c_wdata3; /* 7 */ + volatile csr_i2c_wdata4_u i2c_wdata4; /* 8 */ + volatile csr_i2c_wdata5_u i2c_wdata5; /* 9 */ + volatile csr_i2c_wdata6_u i2c_wdata6; /* A */ + volatile csr_i2c_wdata7_u i2c_wdata7; /* B */ + volatile csr_i2c_wstrb_u i2c_wstrb; /* C */ + volatile csr_i2c_awsize_u i2c_awsize; /* D */ + volatile csr_i2c_awid_u i2c_awid; /* E */ + volatile csr_i2c_awlock_u i2c_awlock; /* F */ + volatile csr_i2c_awcache_u i2c_awcache; /* 10 */ + volatile csr_i2c_awprot_u i2c_awprot; /* 11 */ + volatile csr_i2c_araddr0_u i2c_araddr0; /* 30 */ + volatile csr_i2c_araddr1_u i2c_araddr1; /* 31 */ + volatile csr_i2c_araddr2_u i2c_araddr2; /* 32 */ + volatile csr_i2c_araddr3_u i2c_araddr3; /* 33 */ + volatile csr_i2c_arsize_u i2c_arsize; /* 34 */ + volatile csr_i2c_arid_u i2c_arid; /* 35 */ + volatile csr_i2c_arlock_u i2c_arlock; /* 36 */ + volatile csr_i2c_arcache_u i2c_arcache; /* 37 */ + volatile csr_i2c_arprot_u i2c_arprot; /* 38 */ + volatile csr_axi_bresp_u axi_bresp; /* 60 */ + volatile csr_axi_bid_u axi_bid; /* 61 */ + volatile csr_axi_rresp_u axi_rresp; /* 70 */ + volatile csr_axi_rdata0_u axi_rdata0; /* 71 */ + volatile csr_axi_rdata1_u axi_rdata1; /* 72 */ + volatile csr_axi_rdata2_u axi_rdata2; /* 73 */ + volatile csr_axi_rdata3_u axi_rdata3; /* 74 */ + volatile csr_axi_rdata4_u axi_rdata4; /* 75 */ + volatile csr_axi_rdata5_u axi_rdata5; /* 76 */ + volatile csr_axi_rdata6_u axi_rdata6; /* 77 */ + volatile csr_axi_rdata7_u axi_rdata7; /* 78 */ + volatile csr_axi_rid_u axi_rid; /* 79 */ + volatile csr_wr_rd_cmd_u wr_rd_cmd; /* 80 */ + volatile csr_version_number_u version_number; /* 90 */ +} S_i2c2axi_REGS_TYPE; + +/* Declare the struct pointor of the module i2c2axi */ +extern volatile S_i2c2axi_REGS_TYPE *gopi2c2axiAllReg; + +/* Declare the functions that set the member value */ +int iSetI2C_AWADDR0_i2c_awaddr0(unsigned int ui2c_awaddr0); +int iSetI2C_AWADDR1_i2c_awaddr1(unsigned int ui2c_awaddr1); +int iSetI2C_AWADDR2_i2c_awaddr2(unsigned int ui2c_awaddr2); +int iSetI2C_AWADDR3_i2c_awaddr3(unsigned int ui2c_awaddr3); +int iSetI2C_WDATA0_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA1_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA2_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA3_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA4_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA5_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA6_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WDATA7_i2c_wdata0(unsigned int ui2c_wdata0); +int iSetI2C_WSTRB_i2c_wstrb(unsigned int ui2c_wstrb); +int iSetI2C_AWSIZE_i2c_awsize(unsigned int ui2c_awsize); +int iSetI2C_AWID_i2c_awid(unsigned int ui2c_awid); +int iSetI2C_AWLOCK_i2c_awlock(unsigned int ui2c_awlock); +int iSetI2C_AWCACHE_i2c_awcache(unsigned int ui2c_awcache); +int iSetI2C_AWPROT_i2c_awprot(unsigned int ui2c_awprot); +int iSetI2C_ARADDR0_i2c_araddr0(unsigned int ui2c_araddr0); +int iSetI2C_ARADDR1_i2c_araddr1(unsigned int ui2c_araddr1); +int iSetI2C_ARADDR2_i2c_araddr2(unsigned int ui2c_araddr2); +int iSetI2C_ARADDR3_i2c_araddr3(unsigned int ui2c_araddr3); +int iSetI2C_ARSIZE_i2c_arsize(unsigned int ui2c_arsize); +int iSetI2C_ARID_i2c_arid(unsigned int ui2c_arid); +int iSetI2C_ARLOCK_i2c_arlock(unsigned int ui2c_arlock); +int iSetI2C_ARCACHE_i2c_arcache(unsigned int ui2c_arcache); +int iSetI2C_ARPROT_i2c_arprot(unsigned int ui2c_arprot); +int iSetAXI_BRESP_axi_bresp(unsigned int uaxi_bresp); +int iSetAXI_BID_axi_bid(unsigned int uaxi_bid); +int iSetAXI_RRESP_axi_rresp(unsigned int uaxi_rresp); +int iSetAXI_RDATA0_axi_rdata0(unsigned int uaxi_rdata0); +int iSetAXI_RDATA1_axi_rdata1(unsigned int uaxi_rdata1); +int iSetAXI_RDATA2_axi_rdata2(unsigned int uaxi_rdata2); +int iSetAXI_RDATA3_axi_rdata3(unsigned int uaxi_rdata3); +int iSetAXI_RDATA4_axi_rdata4(unsigned int uaxi_rdata4); +int iSetAXI_RDATA5_axi_rdata5(unsigned int uaxi_rdata5); +int iSetAXI_RDATA6_axi_rdata6(unsigned int uaxi_rdata6); +int iSetAXI_RDATA7_axi_rdata7(unsigned int uaxi_rdata7); +int iSetAXI_RID_axi_rid(unsigned int uaxi_rid); +int iSetWR_RD_CMD_wr_rd_cmd(unsigned int uwr_rd_cmd); +int iSetVERSION_NUMBER_version_number(unsigned int uversion_number); + +/* Define the union csr_spi_rx_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_rx_st : 16; /* [15:0] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_rx_st_u; + +/* Define the union csr_spi_tx_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_txdat_len : 11; /* [10:0] */ + u32 pkt_type : 1; /* [11] */ + u32 spi_pkt_cnt : 4; /* [15:12] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_tx_st_u; + +/* Define the union csr_spi_buf_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_size : 11; /* [10:0] */ + u32 rsv_2 : 4; /* [14:11] */ + u32 ready : 1; /* [15] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_buf_size_u; + +/* Define the union csr_int_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_rxrb_int_st : 1; /* [0] */ + u32 spi_txrb_int_st : 1; /* [1] */ + u32 rxfifo_ovfl_intst : 1; /* [2] */ + u32 txfifo_unfl_int_st : 1; /* [3] */ + u32 rsv_4 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_st_u; + +/* Define the union csr_int_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_rxrb_int_en : 1; /* [0] */ + u32 spi_txrb_int_en : 1; /* [1] */ + u32 rxfifo_ovfl_int_en : 1; /* [2] */ + u32 txfifo_unfl_int_en : 1; /* [3] */ + u32 rsv_5 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_ctl_u; + +/* Define the union csr_int_coll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_coll : 3; /* [2:0] */ + u32 rsv_6 : 13; /* [15:3] */ + u32 coll_timeout : 8; /* [23:16] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_coll_u; + +/* Define the union csr_spi_intr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_intr : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_intr_u; + +/* Define the union csr_spi_bd_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_ba : 27; /* [26:0] */ + u32 rsv_9 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_bd_ba_u; + +/* Define the union csr_spi_rxbd_pool_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_rxbd_pool : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_rxbd_pool_u; + +/* Define the union csr_spi_txbd_pool_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_txbd_pool : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_txbd_pool_u; + +/* Define the union csr_spi_rxbd_if_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_rxbd_if : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_rxbd_if_u; + +/* Define the union csr_spi_txbd_if_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_txbd_if : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_txbd_if_u; + +/* Define the union csr_spi_bd_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxbd_pool_empty : 1; /* [0] */ + u32 rxbd_pool_full : 1; /* [1] */ + u32 rsv_10 : 2; /* [3:2] */ + u32 rxbd_pool_cnt : 4; /* [7:4] */ + u32 txbd_pool_empty : 1; /* [8] */ + u32 txbd_pool_full : 1; /* [9] */ + u32 rsv_11 : 2; /* [11:10] */ + u32 txbd_pool_cnt : 4; /* [15:12] */ + u32 rxbd_empty : 1; /* [16] */ + u32 rxbd_full : 1; /* [17] */ + u32 rsv_12 : 2; /* [19:18] */ + u32 rxbd_cnt : 4; /* [23:20] */ + u32 txbd_empty : 1; /* [24] */ + u32 txbd_full : 1; /* [25] */ + u32 rsv_13 : 2; /* [27:26] */ + u32 txbd_cnt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_bd_st_u; + +/* Define the union csr_spi_err_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxbd_pool_rdempty : 1; /* [0] */ + u32 rxbd_pool_wrfull : 1; /* [1] */ + u32 txbd_pool_rdempty : 1; /* [2] */ + u32 txbd_pool_wrfull : 1; /* [3] */ + u32 rxbd_rdempty : 1; /* [4] */ + u32 rxbd_wrfull : 1; /* [5] */ + u32 txbd_rdempty : 1; /* [6] */ + u32 txbd_wrfull : 1; /* [7] */ + u32 axi_rd_err : 1; /* [8] */ + u32 axi_wr_err : 1; /* [9] */ + u32 txfifo_unfl : 1; /* [10] */ + u32 rxfifo_ovfl : 1; /* [11] */ + u32 rxdat_len_ovfl : 1; /* [12] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_err_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_spi_rx_st_u spi_rx_st; /* 0 */ + volatile csr_spi_tx_st_u spi_tx_st; /* 4 */ + volatile csr_spi_buf_size_u spi_buf_size; /* 8 */ + volatile csr_int_st_u int_st; /* 10 */ + volatile csr_int_ctl_u int_ctl; /* 14 */ + volatile csr_int_coll_u int_coll; /* 18 */ + volatile csr_spi_intr_u spi_intr; /* 1C */ + volatile csr_spi_bd_ba_u spi_bd_ba; /* 20 */ + volatile csr_spi_rxbd_pool_u spi_rxbd_pool; /* 30 */ + volatile csr_spi_txbd_pool_u spi_txbd_pool; /* 34 */ + volatile csr_spi_rxbd_if_u spi_rxbd_if; /* 38 */ + volatile csr_spi_txbd_if_u spi_txbd_if; /* 3C */ + volatile csr_spi_bd_st_u spi_bd_st; /* 40 */ + volatile csr_spi_err_st_u spi_err_st; /* 44 */ +} S_spi2axi_REGS_TYPE; + +/* Declare the struct pointor of the module spi2axi */ +extern volatile S_spi2axi_REGS_TYPE *gopspi2axiAllReg; + +/* Declare the functions that set the member value */ +int iSetSPI_RX_ST_spi_rx_st(unsigned int uspi_rx_st); +int iSetSPI_TX_ST_spi_txdat_len(unsigned int uspi_txdat_len); +int iSetSPI_TX_ST_pkt_type(unsigned int upkt_type); +int iSetSPI_TX_ST_spi_pkt_cnt(unsigned int uspi_pkt_cnt); +int iSetSPI_BUF_SIZE_buf_size(unsigned int ubuf_size); +int iSetSPI_BUF_SIZE_ready(unsigned int uready); +int iSetINT_ST_spi_rxrb_int_st(unsigned int uspi_rxrb_int_st); +int iSetINT_ST_spi_txrb_int_st(unsigned int uspi_txrb_int_st); +int iSetINT_ST_rxfifo_ovfl_intst(unsigned int urxfifo_ovfl_intst); +int iSetINT_ST_txfifo_unfl_int_st(unsigned int utxfifo_unfl_int_st); +int iSetINT_CTL_spi_rxrb_int_en(unsigned int uspi_rxrb_int_en); +int iSetINT_CTL_spi_txrb_int_en(unsigned int uspi_txrb_int_en); +int iSetINT_CTL_rxfifo_ovfl_int_en(unsigned int urxfifo_ovfl_int_en); +int iSetINT_CTL_txfifo_unfl_int_en(unsigned int utxfifo_unfl_int_en); +int iSetINT_COLL_int_coll(unsigned int uint_coll); +int iSetINT_COLL_coll_timeout(unsigned int ucoll_timeout); +int iSetSPI_INTR_spi_intr(unsigned int uspi_intr); +int iSetSPI_BD_BA_bd_ba(unsigned int ubd_ba); +int iSetSPI_RXBD_POOL_spi_rxbd_pool(unsigned int uspi_rxbd_pool); +int iSetSPI_TXBD_POOL_spi_txbd_pool(unsigned int uspi_txbd_pool); +int iSetSPI_RXBD_IF_spi_rxbd_if(unsigned int uspi_rxbd_if); +int iSetSPI_TXBD_IF_spi_txbd_if(unsigned int uspi_txbd_if); +int iSetSPI_BD_ST_rxbd_pool_empty(unsigned int urxbd_pool_empty); +int iSetSPI_BD_ST_rxbd_pool_full(unsigned int urxbd_pool_full); +int iSetSPI_BD_ST_rxbd_pool_cnt(unsigned int urxbd_pool_cnt); +int iSetSPI_BD_ST_txbd_pool_empty(unsigned int utxbd_pool_empty); +int iSetSPI_BD_ST_txbd_pool_full(unsigned int utxbd_pool_full); +int iSetSPI_BD_ST_txbd_pool_cnt(unsigned int utxbd_pool_cnt); +int iSetSPI_BD_ST_rxbd_empty(unsigned int urxbd_empty); +int iSetSPI_BD_ST_rxbd_full(unsigned int urxbd_full); +int iSetSPI_BD_ST_rxbd_cnt(unsigned int urxbd_cnt); +int iSetSPI_BD_ST_txbd_empty(unsigned int utxbd_empty); +int iSetSPI_BD_ST_txbd_full(unsigned int utxbd_full); +int iSetSPI_BD_ST_txbd_cnt(unsigned int utxbd_cnt); +int iSetSPI_ERR_ST_rxbd_pool_rdempty(unsigned int urxbd_pool_rdempty); +int iSetSPI_ERR_ST_rxbd_pool_wrfull(unsigned int urxbd_pool_wrfull); +int iSetSPI_ERR_ST_txbd_pool_rdempty(unsigned int utxbd_pool_rdempty); +int iSetSPI_ERR_ST_txbd_pool_wrfull(unsigned int utxbd_pool_wrfull); +int iSetSPI_ERR_ST_rxbd_rdempty(unsigned int urxbd_rdempty); +int iSetSPI_ERR_ST_rxbd_wrfull(unsigned int urxbd_wrfull); +int iSetSPI_ERR_ST_txbd_rdempty(unsigned int utxbd_rdempty); +int iSetSPI_ERR_ST_txbd_wrfull(unsigned int utxbd_wrfull); +int iSetSPI_ERR_ST_axi_rd_err(unsigned int uaxi_rd_err); +int iSetSPI_ERR_ST_axi_wr_err(unsigned int uaxi_wr_err); +int iSetSPI_ERR_ST_txfifo_unfl(unsigned int utxfifo_unfl); +int iSetSPI_ERR_ST_rxfifo_ovfl(unsigned int urxfifo_ovfl); +int iSetSPI_ERR_ST_rxdat_len_ovfl(unsigned int urxdat_len_ovfl); + +/* Define the union csr_ring2axi_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkup_filt_neg_int_status : 8; /* [7:0] */ + u32 linkup_filt_pos_int_status : 8; /* [15:8] */ + u32 msgbuf_int_status : 1; /* [16] */ + u32 msgbuf_afull_int_status : 1; /* [17] */ + u32 msgbuf_timeout_int_status : 1; /* [18] */ + u32 api_e0_err_int_status : 1; /* [19] */ + u32 api_e1_err_int_status : 1; /* [20] */ + u32 short_pkt_int_status : 1; /* [21] */ + u32 long_pkt_int_status : 1; /* [22] */ + u32 loss_sop_eop_int_status : 1; /* [23] */ + u32 loss_sop_int_status : 1; /* [24] */ + u32 loss_eop_int_status : 1; /* [25] */ + u32 op_id_err_int_status : 1; /* [26] */ + u32 load_mem_illegal_int_status : 1; /* [27] */ + u32 axi_rerr_int_status : 1; /* [28] */ + u32 axi_berr_int_status : 1; /* [29] */ + u32 rsv_0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_int_status_u; + +/* Define the union csr_ring2axi_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkup_filt_neg_int_en : 8; /* [7:0] */ + u32 linkup_filt_pos_int_en : 8; /* [15:8] */ + u32 msgbuf_int_en : 1; /* [16] */ + u32 msgbuf_afull_int_en : 1; /* [17] */ + u32 msgbuf_timeout_int_en : 1; /* [18] */ + u32 api_e0_err_int_en : 1; /* [19] */ + u32 api_e1_err_int_en : 1; /* [20] */ + u32 short_pkt_int_en : 1; /* [21] */ + u32 long_pkt_int_en : 1; /* [22] */ + u32 loss_sop_eop_int_en : 1; /* [23] */ + u32 loss_sop_int_en : 1; /* [24] */ + u32 loss_eop_int_en : 1; /* [25] */ + u32 op_id_err_int_en : 1; /* [26] */ + u32 load_mem_illegal_int_en : 1; /* [27] */ + u32 axi_rerr_int_en : 1; /* [28] */ + u32 axi_berr_int_en : 1; /* [29] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_int_en_u; + +/* Define the union csr_ring2axi_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkup_filt_neg_int_set : 8; /* [7:0] */ + u32 linkup_filt_pos_int_set : 8; /* [15:8] */ + u32 msgbuf_int_set : 1; /* [16] */ + u32 msgbuf_afull_int_set : 1; /* [17] */ + u32 msgbuf_timeout_int_set : 1; /* [18] */ + u32 api_e0_err_int_set : 1; /* [19] */ + u32 api_e1_err_int_set : 1; /* [20] */ + u32 short_pkt_int_set : 1; /* [21] */ + u32 long_pkt_int_set : 1; /* [22] */ + u32 loss_sop_eop_int_set : 1; /* [23] */ + u32 loss_sop_int_set : 1; /* [24] */ + u32 loss_eop_int_set : 1; /* [25] */ + u32 op_id_err_int_set : 1; /* [26] */ + u32 load_mem_illegal_int_set : 1; /* [27] */ + u32 axi_rerr_int_set : 1; /* [28] */ + u32 axi_berr_int_set : 1; /* [29] */ + u32 rsv_2 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_int_set_u; + +/* Define the union csr_ring2axi_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkup_filt_neg_int_raw_status : 8; /* [7:0] */ + u32 linkup_filt_pos_int_raw_status : 8; /* [15:8] */ + u32 msgbuf_int_raw_status : 1; /* [16] */ + u32 msgbuf_afull_int_raw_status : 1; /* [17] */ + u32 msgbuf_timeout_int_raw_status : 1; /* [18] */ + u32 api_e0_err_int_raw_status : 1; /* [19] */ + u32 api_e1_err_int_raw_status : 1; /* [20] */ + u32 short_pkt_int_raw_status : 1; /* [21] */ + u32 long_pkt_int_raw_status : 1; /* [22] */ + u32 loss_sop_eop_int_raw_status : 1; /* [23] */ + u32 loss_sop_int_raw_status : 1; /* [24] */ + u32 loss_eop_int_raw_status : 1; /* [25] */ + u32 op_id_err_int_raw_status : 1; /* [26] */ + u32 load_mem_illegal_int_raw_status : 1; /* [27] */ + u32 axi_rerr_int_raw_status : 1; /* [28] */ + u32 axi_berr_int_raw_status : 1; /* [29] */ + u32 rsv_3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_int_raw_status_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_len : 21; /* [20:0] */ + u32 rsv_4 : 7; /* [27:21] */ + u32 ovfl_mode : 1; /* [28] */ + u32 msgbuf_int_rpt_now_en : 1; /* [29] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_mode_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_ba : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_ba_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_ci : 21; /* [20:0] */ + u32 msgbuf_ci_sign : 1; /* [21] */ + u32 rsv_6 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_ci_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_afull_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_afull_th : 21; /* [20:0] */ + u32 rsv_7 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_afull_th_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_afull_clr_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_afull_clr_th : 21; /* [20:0] */ + u32 rsv_8 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_afull_clr_th_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_time_out_en : 1; /* [0] */ + u32 rsv_9 : 3; /* [3:1] */ + u32 msgbuf_time_out_max_cnt : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_timeout_u; + +/* Define the union csr_ring2axi_cfg_msgbuf_timeout_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_time_out_cnt_clr : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_msgbuf_timeout_clr_u; + +/* Define the union csr_ring2axi_cfg_mem_api_endian_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_mem_endian_sel : 1; /* [0] */ + u32 rsv_11 : 3; /* [3:1] */ + u32 load_mem_endian_sel : 1; /* [4] */ + u32 rsv_12 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_mem_api_endian_sel_u; + +/* Define the union csr_ring2axi_cfg_api_max_index_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_max_index : 14; /* [13:0] */ + u32 rsv_13 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_api_max_index_u; + +/* Define the union csr_ring2axi_cfg_bw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_acc_max : 2; /* [1:0] */ + u32 rsv_14 : 2; /* [3:2] */ + u32 axi_wr_acc_max : 2; /* [5:4] */ + u32 rsv_15 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_bw_u; + +/* Define the union csr_ring2axi_cfg_api_flit_cnt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_api_flit_cnt_init : 1; /* [0] */ + u32 rsv_16 : 3; /* [3:1] */ + u32 tx_api_flit_cnt_init : 1; /* [4] */ + u32 rsv_17 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_api_flit_cnt_init_u; + +/* Define the union csr_ring2axi_cfg_rx_disc_flit_cnt_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_disc_flit_cnt_clr : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_rx_disc_flit_cnt_clr_u; + +/* Define the union csr_ring2axi_cfg_rx_dealed_flit_cnt_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dealed_flit_cnt_clr : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_cfg_rx_dealed_flit_cnt_clr_u; + +/* Define the union csr_ring2axi_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asyn_ififo_afull_th : 3; /* [2:0] */ + u32 rsv_20 : 1; /* [3] */ + u32 asyn_efifo_afull_th : 3; /* [6:4] */ + u32 rsv_21 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_fifo_cfg_u; + +/* Define the union csr_ring2axi_msgbuf_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_pi : 21; /* [20:0] */ + u32 msgbuf_pi_sign : 1; /* [21] */ + u32 rsv_22 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_msgbuf_pi_u; + +/* Define the union csr_ring2axi_msgbuf_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_cnt : 22; /* [21:0] */ + u32 rsv_23 : 2; /* [23:22] */ + u32 msgbuf_empty : 1; /* [24] */ + u32 rsv_24 : 3; /* [27:25] */ + u32 msgbuf_full : 1; /* [28] */ + u32 msgbuf_afull : 1; /* [29] */ + u32 rsv_25 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_msgbuf_stat_u; + +/* Define the union csr_ring2axi_msgbuf_of_uf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msgbuf_of : 1; /* [0] */ + u32 rsv_26 : 3; /* [3:1] */ + u32 msgbuf_uf : 1; /* [4] */ + u32 rsv_27 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_msgbuf_of_uf_u; + +/* Define the union csr_ring2axi_inner_buf_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inner_buf_cnt : 22; /* [21:0] */ + u32 rsv_28 : 2; /* [23:22] */ + u32 inner_buf_empty : 1; /* [24] */ + u32 rsv_29 : 3; /* [27:25] */ + u32 inner_buf_full : 1; /* [28] */ + u32 rsv_30 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_inner_buf_stat_u; + +/* Define the union csr_ring2axi_inner_buf_of_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inner_buf_of : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_inner_buf_of_u; + +/* Define the union csr_ring2axi_rx_api_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_api_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_rx_api_flit_cnt_u; + +/* Define the union csr_ring2axi_tx_api_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_api_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_tx_api_flit_cnt_u; + +/* Define the union csr_ring2axi_axi_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_latency_cnt : 16; /* [15:0] */ + u32 rsv_32 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_rd_latency_u; + +/* Define the union csr_ring2axi_axi_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_latency_cnt : 16; /* [15:0] */ + u32 rsv_33 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_wr_latency_u; + +/* Define the union csr_ring2axi_axi_rd_latency_min_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_latency_min_cnt : 16; /* [15:0] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_rd_latency_min_cnt_u; + +/* Define the union csr_ring2axi_axi_wr_latency_min_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_latency_min_cnt : 16; /* [15:0] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_wr_latency_min_cnt_u; + +/* Define the union csr_ring2axi_axi_rd_latency_max_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_latency_max_cnt : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_rd_latency_max_cnt_u; + +/* Define the union csr_ring2axi_axi_wr_latency_max_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_latency_max_cnt : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_wr_latency_max_cnt_u; + +/* Define the union csr_ring2axi_axi_rd_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_otd_cnt : 3; /* [2:0] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_rd_otd_cnt_u; + +/* Define the union csr_ring2axi_axi_wr_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_otd_cnt : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_wr_otd_cnt_u; + +/* Define the union csr_ring2axi_axi_rd_otd_max_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_otd_max_cnt : 3; /* [2:0] */ + u32 rsv_40 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_rd_otd_max_cnt_u; + +/* Define the union csr_ring2axi_axi_wr_otd_max_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_otd_max_cnt : 3; /* [2:0] */ + u32 rsv_41 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_axi_wr_otd_max_cnt_u; + +/* Define the union csr_ring2axi_fsm_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rch_cur_st : 2; /* [1:0] */ + u32 rsv_42 : 2; /* [3:2] */ + u32 r_rsp_cur_st : 2; /* [5:4] */ + u32 rsv_43 : 2; /* [7:6] */ + u32 wch_cur_st : 3; /* [10:8] */ + u32 rsv_44 : 1; /* [11] */ + u32 w_rsp_cur_st : 2; /* [13:12] */ + u32 rsv_45 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_fsm_stat_u; + +/* Define the union csr_ring2axi_fifo_err_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_legal_efifo_of : 1; /* [0] */ + u32 load_legal_efifo_of : 1; /* [1] */ + u32 load_addr_fifo_of : 1; /* [2] */ + u32 load_cmd_fifo_of : 1; /* [3] */ + u32 store_csr_addr_fifo_of : 1; /* [4] */ + u32 store_mem_cmd_fifo_of : 1; /* [5] */ + u32 store_csr_cmd_fifo_of : 1; /* [6] */ + u32 store_csr_mem_seq_fifo0_of : 1; /* [7] */ + u32 store_csr_mem_seq_fifo1_of : 1; /* [8] */ + u32 sync_ififo_of_sync : 1; /* [9] */ + u32 asyn_ififo_of_sync : 1; /* [10] */ + u32 asyn_efifo_of : 1; /* [11] */ + u32 rsv_46 : 4; /* [15:12] */ + u32 store_legal_efifo_uf : 1; /* [16] */ + u32 load_legal_efifo_uf : 1; /* [17] */ + u32 load_addr_fifo_uf : 1; /* [18] */ + u32 load_cmd_fifo_uf : 1; /* [19] */ + u32 store_csr_addr_fifo_uf : 1; /* [20] */ + u32 store_mem_cmd_fifo_uf : 1; /* [21] */ + u32 store_csr_cmd_fifo_uf : 1; /* [22] */ + u32 store_csr_mem_seq_fifo0_uf : 1; /* [23] */ + u32 store_csr_mem_seq_fifo1_uf : 1; /* [24] */ + u32 rsv_47 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_fifo_err_flag_u; + +/* Define the union csr_ring2axi_store_legal_efifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_legal_efifo_cnt : 4; /* [3:0] */ + u32 store_legal_efifo_empty : 1; /* [4] */ + u32 rsv_48 : 3; /* [7:5] */ + u32 store_legal_efifo_full : 1; /* [8] */ + u32 rsv_49 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_legal_efifo_stat_u; + +/* Define the union csr_ring2axi_load_legal_efifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 load_legal_efifo_cnt : 5; /* [4:0] */ + u32 rsv_50 : 3; /* [7:5] */ + u32 load_legal_efifo_empty : 1; /* [8] */ + u32 rsv_51 : 4; /* [12:9] */ + u32 load_legal_efifo_full : 1; /* [13] */ + u32 rsv_52 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_load_legal_efifo_stat_u; + +/* Define the union csr_ring2axi_load_addr_fifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 load_addr_fifo_cnt : 4; /* [3:0] */ + u32 load_addr_fifo_empty : 1; /* [4] */ + u32 rsv_53 : 3; /* [7:5] */ + u32 load_addr_fifo_full : 1; /* [8] */ + u32 rsv_54 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_load_addr_fifo_stat_u; + +/* Define the union csr_ring2axi_load_cmd_fifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 load_cmd_fifo_cnt : 4; /* [3:0] */ + u32 load_cmd_fifo_empty : 1; /* [4] */ + u32 rsv_55 : 3; /* [7:5] */ + u32 load_cmd_fifo_full : 1; /* [8] */ + u32 rsv_56 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_load_cmd_fifo_stat_u; + +/* Define the union csr_ring2axi_store_csr_addr_fifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_csr_addr_fifo_cnt : 4; /* [3:0] */ + u32 store_csr_addr_fifo_empty : 1; /* [4] */ + u32 rsv_57 : 3; /* [7:5] */ + u32 store_csr_addr_fifo_full : 1; /* [8] */ + u32 rsv_58 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_csr_addr_fifo_stat_u; + +/* Define the union csr_ring2axi_store_mem_cmd_fifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_mem_cmd_fifo_cnt : 4; /* [3:0] */ + u32 store_mem_cmd_fifo_empty : 1; /* [4] */ + u32 rsv_59 : 3; /* [7:5] */ + u32 store_mem_cmd_fifo_full : 1; /* [8] */ + u32 rsv_60 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_mem_cmd_fifo_stat_u; + +/* Define the union csr_ring2axi_store_csr_cmd_fifo_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_csr_cmd_fifo_cnt : 4; /* [3:0] */ + u32 store_csr_cmd_fifo_empty : 1; /* [4] */ + u32 rsv_61 : 3; /* [7:5] */ + u32 store_csr_cmd_fifo_full : 1; /* [8] */ + u32 rsv_62 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_csr_cmd_fifo_stat_u; + +/* Define the union csr_ring2axi_store_csr_mem_fifo0_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_csr_mem_seq_fifo0_cnt : 4; /* [3:0] */ + u32 store_csr_mem_seq_fifo0_empty : 1; /* [4] */ + u32 rsv_63 : 3; /* [7:5] */ + u32 store_csr_mem_seq_fifo0_full : 1; /* [8] */ + u32 rsv_64 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_csr_mem_fifo0_stat_u; + +/* Define the union csr_ring2axi_store_csr_mem_fifo1_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_csr_mem_seq_fifo1_cnt : 4; /* [3:0] */ + u32 store_csr_mem_seq_fifo1_empty : 1; /* [4] */ + u32 rsv_65 : 3; /* [7:5] */ + u32 store_csr_mem_seq_fifo1_full : 1; /* [8] */ + u32 rsv_66 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_csr_mem_fifo1_stat_u; + +/* Define the union csr_ring2axi_if_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sync_ififo_cnt_sync : 4; /* [3:0] */ + u32 rsv_67 : 4; /* [7:4] */ + u32 asyn_ififo_rcnt : 4; /* [11:8] */ + u32 rsv_68 : 4; /* [15:12] */ + u32 asyn_efifo_wcnt : 4; /* [19:16] */ + u32 rsv_69 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_if_fifo_cnt_u; + +/* Define the union csr_ring2axi_ejection_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crdt_cnt_sync : 3; /* [2:0] */ + u32 rsv_70 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_ejection_crdt_cnt_u; + +/* Define the union csr_ring2axi_illegal_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_illegal_index : 1; /* [0] */ + u32 rsv_71 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_illegal_stat_u; + +/* Define the union csr_ring2axi_store_mem_api_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 store_mem_api_vld : 1; /* [0] */ + u32 rsv_72 : 3; /* [3:1] */ + u32 store_mem_flit_cnt : 3; /* [6:4] */ + u32 rsv_73 : 1; /* [7] */ + u32 store_mem_api_4flit : 1; /* [8] */ + u32 rsv_74 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_store_mem_api_stat_u; + +/* Define the union csr_ring2axi_rx_disc_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_disc_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_rx_disc_flit_cnt_u; + +/* Define the union csr_ring2axi_rx_dealed_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dealed_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_rx_dealed_flit_cnt_u; + +/* Define the union csr_ring2axi_up_filt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_flit_cfg_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_up_filt_cnt_u; + +/* Define the union csr_ring2axi_dn_filt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dn_flit_cfg_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_dn_filt_cnt_u; + +/* Define the union csr_ring2axi_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring2axi_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_version_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ring2axi_int_status_u ring2axi_int_status; /* 10 */ + volatile csr_ring2axi_int_en_u ring2axi_int_en; /* 20 */ + volatile csr_ring2axi_int_set_u ring2axi_int_set; /* 30 */ + volatile csr_ring2axi_int_raw_status_u ring2axi_int_raw_status; /* 40 */ + volatile csr_ring2axi_cfg_msgbuf_mode_u ring2axi_cfg_msgbuf_mode; /* A0 */ + volatile csr_ring2axi_cfg_msgbuf_ba_u ring2axi_cfg_msgbuf_ba; /* A4 */ + volatile csr_ring2axi_cfg_msgbuf_ci_u ring2axi_cfg_msgbuf_ci; /* A8 */ + volatile csr_ring2axi_cfg_msgbuf_afull_th_u ring2axi_cfg_msgbuf_afull_th; /* AC */ + volatile csr_ring2axi_cfg_msgbuf_afull_clr_th_u ring2axi_cfg_msgbuf_afull_clr_th; /* B0 */ + volatile csr_ring2axi_cfg_msgbuf_timeout_u ring2axi_cfg_msgbuf_timeout; /* B4 */ + volatile csr_ring2axi_cfg_msgbuf_timeout_clr_u ring2axi_cfg_msgbuf_timeout_clr; /* B8 */ + volatile csr_ring2axi_cfg_mem_api_endian_sel_u ring2axi_cfg_mem_api_endian_sel; /* BC */ + volatile csr_ring2axi_cfg_api_max_index_u ring2axi_cfg_api_max_index; /* C0 */ + volatile csr_ring2axi_cfg_bw_u ring2axi_cfg_bw; /* C4 */ + volatile csr_ring2axi_cfg_api_flit_cnt_init_u ring2axi_cfg_api_flit_cnt_init; /* C8 */ + volatile csr_ring2axi_cfg_rx_disc_flit_cnt_clr_u ring2axi_cfg_rx_disc_flit_cnt_clr; /* CC */ + volatile csr_ring2axi_cfg_rx_dealed_flit_cnt_clr_u ring2axi_cfg_rx_dealed_flit_cnt_clr; /* D0 */ + volatile csr_ring2axi_fifo_cfg_u ring2axi_fifo_cfg; /* D4 */ + volatile csr_ring2axi_msgbuf_pi_u ring2axi_msgbuf_pi; /* 200 */ + volatile csr_ring2axi_msgbuf_stat_u ring2axi_msgbuf_stat; /* 204 */ + volatile csr_ring2axi_msgbuf_of_uf_u ring2axi_msgbuf_of_uf; /* 208 */ + volatile csr_ring2axi_inner_buf_stat_u ring2axi_inner_buf_stat; /* 20C */ + volatile csr_ring2axi_inner_buf_of_u ring2axi_inner_buf_of; /* 210 */ + volatile csr_ring2axi_rx_api_flit_cnt_u ring2axi_rx_api_flit_cnt; /* 214 */ + volatile csr_ring2axi_tx_api_flit_cnt_u ring2axi_tx_api_flit_cnt; /* 218 */ + volatile csr_ring2axi_axi_rd_latency_u ring2axi_axi_rd_latency; /* 21C */ + volatile csr_ring2axi_axi_wr_latency_u ring2axi_axi_wr_latency; /* 220 */ + volatile csr_ring2axi_axi_rd_latency_min_cnt_u ring2axi_axi_rd_latency_min_cnt; /* 224 */ + volatile csr_ring2axi_axi_wr_latency_min_cnt_u ring2axi_axi_wr_latency_min_cnt; /* 228 */ + volatile csr_ring2axi_axi_rd_latency_max_cnt_u ring2axi_axi_rd_latency_max_cnt; /* 22C */ + volatile csr_ring2axi_axi_wr_latency_max_cnt_u ring2axi_axi_wr_latency_max_cnt; /* 230 */ + volatile csr_ring2axi_axi_rd_otd_cnt_u ring2axi_axi_rd_otd_cnt; /* 234 */ + volatile csr_ring2axi_axi_wr_otd_cnt_u ring2axi_axi_wr_otd_cnt; /* 238 */ + volatile csr_ring2axi_axi_rd_otd_max_cnt_u ring2axi_axi_rd_otd_max_cnt; /* 23C */ + volatile csr_ring2axi_axi_wr_otd_max_cnt_u ring2axi_axi_wr_otd_max_cnt; /* 240 */ + volatile csr_ring2axi_fsm_stat_u ring2axi_fsm_stat; /* 244 */ + volatile csr_ring2axi_fifo_err_flag_u ring2axi_fifo_err_flag; /* 248 */ + volatile csr_ring2axi_store_legal_efifo_stat_u ring2axi_store_legal_efifo_stat; /* 24C */ + volatile csr_ring2axi_load_legal_efifo_stat_u ring2axi_load_legal_efifo_stat; /* 250 */ + volatile csr_ring2axi_load_addr_fifo_stat_u ring2axi_load_addr_fifo_stat; /* 254 */ + volatile csr_ring2axi_load_cmd_fifo_stat_u ring2axi_load_cmd_fifo_stat; /* 258 */ + volatile csr_ring2axi_store_csr_addr_fifo_stat_u ring2axi_store_csr_addr_fifo_stat; /* 25C */ + volatile csr_ring2axi_store_mem_cmd_fifo_stat_u ring2axi_store_mem_cmd_fifo_stat; /* 260 */ + volatile csr_ring2axi_store_csr_cmd_fifo_stat_u ring2axi_store_csr_cmd_fifo_stat; /* 264 */ + volatile csr_ring2axi_store_csr_mem_fifo0_stat_u ring2axi_store_csr_mem_fifo0_stat; /* 268 */ + volatile csr_ring2axi_store_csr_mem_fifo1_stat_u ring2axi_store_csr_mem_fifo1_stat; /* 26C */ + volatile csr_ring2axi_if_fifo_cnt_u ring2axi_if_fifo_cnt; /* 270 */ + volatile csr_ring2axi_ejection_crdt_cnt_u ring2axi_ejection_crdt_cnt; /* 274 */ + volatile csr_ring2axi_illegal_stat_u ring2axi_illegal_stat; /* 278 */ + volatile csr_ring2axi_store_mem_api_stat_u ring2axi_store_mem_api_stat; /* 27C */ + volatile csr_ring2axi_rx_disc_flit_cnt_u ring2axi_rx_disc_flit_cnt; /* 400 */ + volatile csr_ring2axi_rx_dealed_flit_cnt_u ring2axi_rx_dealed_flit_cnt; /* 404 */ + volatile csr_ring2axi_up_filt_cnt_u ring2axi_up_filt_cnt; /* 410 */ + volatile csr_ring2axi_dn_filt_cnt_u ring2axi_dn_filt_cnt; /* 414 */ + volatile csr_ring2axi_version_u ring2axi_version; /* 500 */ +} S_ring2axi_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ring2axi_csr */ +extern volatile S_ring2axi_csr_REGS_TYPE *gopring2axi_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetRING2AXI_INT_STATUS_linkup_filt_neg_int_status(unsigned int ulinkup_filt_neg_int_status); +int iSetRING2AXI_INT_STATUS_linkup_filt_pos_int_status(unsigned int ulinkup_filt_pos_int_status); +int iSetRING2AXI_INT_STATUS_msgbuf_int_status(unsigned int umsgbuf_int_status); +int iSetRING2AXI_INT_STATUS_msgbuf_afull_int_status(unsigned int umsgbuf_afull_int_status); +int iSetRING2AXI_INT_STATUS_msgbuf_timeout_int_status(unsigned int umsgbuf_timeout_int_status); +int iSetRING2AXI_INT_STATUS_api_e0_err_int_status(unsigned int uapi_e0_err_int_status); +int iSetRING2AXI_INT_STATUS_api_e1_err_int_status(unsigned int uapi_e1_err_int_status); +int iSetRING2AXI_INT_STATUS_short_pkt_int_status(unsigned int ushort_pkt_int_status); +int iSetRING2AXI_INT_STATUS_long_pkt_int_status(unsigned int ulong_pkt_int_status); +int iSetRING2AXI_INT_STATUS_loss_sop_eop_int_status(unsigned int uloss_sop_eop_int_status); +int iSetRING2AXI_INT_STATUS_loss_sop_int_status(unsigned int uloss_sop_int_status); +int iSetRING2AXI_INT_STATUS_loss_eop_int_status(unsigned int uloss_eop_int_status); +int iSetRING2AXI_INT_STATUS_op_id_err_int_status(unsigned int uop_id_err_int_status); +int iSetRING2AXI_INT_STATUS_load_mem_illegal_int_status(unsigned int uload_mem_illegal_int_status); +int iSetRING2AXI_INT_STATUS_axi_rerr_int_status(unsigned int uaxi_rerr_int_status); +int iSetRING2AXI_INT_STATUS_axi_berr_int_status(unsigned int uaxi_berr_int_status); +int iSetRING2AXI_INT_EN_linkup_filt_neg_int_en(unsigned int ulinkup_filt_neg_int_en); +int iSetRING2AXI_INT_EN_linkup_filt_pos_int_en(unsigned int ulinkup_filt_pos_int_en); +int iSetRING2AXI_INT_EN_msgbuf_int_en(unsigned int umsgbuf_int_en); +int iSetRING2AXI_INT_EN_msgbuf_afull_int_en(unsigned int umsgbuf_afull_int_en); +int iSetRING2AXI_INT_EN_msgbuf_timeout_int_en(unsigned int umsgbuf_timeout_int_en); +int iSetRING2AXI_INT_EN_api_e0_err_int_en(unsigned int uapi_e0_err_int_en); +int iSetRING2AXI_INT_EN_api_e1_err_int_en(unsigned int uapi_e1_err_int_en); +int iSetRING2AXI_INT_EN_short_pkt_int_en(unsigned int ushort_pkt_int_en); +int iSetRING2AXI_INT_EN_long_pkt_int_en(unsigned int ulong_pkt_int_en); +int iSetRING2AXI_INT_EN_loss_sop_eop_int_en(unsigned int uloss_sop_eop_int_en); +int iSetRING2AXI_INT_EN_loss_sop_int_en(unsigned int uloss_sop_int_en); +int iSetRING2AXI_INT_EN_loss_eop_int_en(unsigned int uloss_eop_int_en); +int iSetRING2AXI_INT_EN_op_id_err_int_en(unsigned int uop_id_err_int_en); +int iSetRING2AXI_INT_EN_load_mem_illegal_int_en(unsigned int uload_mem_illegal_int_en); +int iSetRING2AXI_INT_EN_axi_rerr_int_en(unsigned int uaxi_rerr_int_en); +int iSetRING2AXI_INT_EN_axi_berr_int_en(unsigned int uaxi_berr_int_en); +int iSetRING2AXI_INT_SET_linkup_filt_neg_int_set(unsigned int ulinkup_filt_neg_int_set); +int iSetRING2AXI_INT_SET_linkup_filt_pos_int_set(unsigned int ulinkup_filt_pos_int_set); +int iSetRING2AXI_INT_SET_msgbuf_int_set(unsigned int umsgbuf_int_set); +int iSetRING2AXI_INT_SET_msgbuf_afull_int_set(unsigned int umsgbuf_afull_int_set); +int iSetRING2AXI_INT_SET_msgbuf_timeout_int_set(unsigned int umsgbuf_timeout_int_set); +int iSetRING2AXI_INT_SET_api_e0_err_int_set(unsigned int uapi_e0_err_int_set); +int iSetRING2AXI_INT_SET_api_e1_err_int_set(unsigned int uapi_e1_err_int_set); +int iSetRING2AXI_INT_SET_short_pkt_int_set(unsigned int ushort_pkt_int_set); +int iSetRING2AXI_INT_SET_long_pkt_int_set(unsigned int ulong_pkt_int_set); +int iSetRING2AXI_INT_SET_loss_sop_eop_int_set(unsigned int uloss_sop_eop_int_set); +int iSetRING2AXI_INT_SET_loss_sop_int_set(unsigned int uloss_sop_int_set); +int iSetRING2AXI_INT_SET_loss_eop_int_set(unsigned int uloss_eop_int_set); +int iSetRING2AXI_INT_SET_op_id_err_int_set(unsigned int uop_id_err_int_set); +int iSetRING2AXI_INT_SET_load_mem_illegal_int_set(unsigned int uload_mem_illegal_int_set); +int iSetRING2AXI_INT_SET_axi_rerr_int_set(unsigned int uaxi_rerr_int_set); +int iSetRING2AXI_INT_SET_axi_berr_int_set(unsigned int uaxi_berr_int_set); +int iSetRING2AXI_INT_RAW_STATUS_linkup_filt_neg_int_raw_status(unsigned int ulinkup_filt_neg_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_linkup_filt_pos_int_raw_status(unsigned int ulinkup_filt_pos_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_msgbuf_int_raw_status(unsigned int umsgbuf_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_msgbuf_afull_int_raw_status(unsigned int umsgbuf_afull_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_msgbuf_timeout_int_raw_status(unsigned int umsgbuf_timeout_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_api_e0_err_int_raw_status(unsigned int uapi_e0_err_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_api_e1_err_int_raw_status(unsigned int uapi_e1_err_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_short_pkt_int_raw_status(unsigned int ushort_pkt_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_long_pkt_int_raw_status(unsigned int ulong_pkt_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_loss_sop_eop_int_raw_status(unsigned int uloss_sop_eop_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_loss_sop_int_raw_status(unsigned int uloss_sop_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_loss_eop_int_raw_status(unsigned int uloss_eop_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_op_id_err_int_raw_status(unsigned int uop_id_err_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_load_mem_illegal_int_raw_status(unsigned int uload_mem_illegal_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_axi_rerr_int_raw_status(unsigned int uaxi_rerr_int_raw_status); +int iSetRING2AXI_INT_RAW_STATUS_axi_berr_int_raw_status(unsigned int uaxi_berr_int_raw_status); +int iSetRING2AXI_CFG_MSGBUF_MODE_msgbuf_len(unsigned int umsgbuf_len); +int iSetRING2AXI_CFG_MSGBUF_MODE_ovfl_mode(unsigned int uovfl_mode); +int iSetRING2AXI_CFG_MSGBUF_MODE_msgbuf_int_rpt_now_en(unsigned int umsgbuf_int_rpt_now_en); +int iSetRING2AXI_CFG_MSGBUF_BA_msgbuf_ba(unsigned int umsgbuf_ba); +int iSetRING2AXI_CFG_MSGBUF_CI_msgbuf_ci(unsigned int umsgbuf_ci); +int iSetRING2AXI_CFG_MSGBUF_CI_msgbuf_ci_sign(unsigned int umsgbuf_ci_sign); +int iSetRING2AXI_CFG_MSGBUF_AFULL_TH_msgbuf_afull_th(unsigned int umsgbuf_afull_th); +int iSetRING2AXI_CFG_MSGBUF_AFULL_CLR_TH_msgbuf_afull_clr_th(unsigned int umsgbuf_afull_clr_th); +int iSetRING2AXI_CFG_MSGBUF_TIMEOUT_msgbuf_time_out_en(unsigned int umsgbuf_time_out_en); +int iSetRING2AXI_CFG_MSGBUF_TIMEOUT_msgbuf_time_out_max_cnt(unsigned int umsgbuf_time_out_max_cnt); +int iSetRING2AXI_CFG_MSGBUF_TIMEOUT_CLR_msgbuf_time_out_cnt_clr(unsigned int umsgbuf_time_out_cnt_clr); +int iSetRING2AXI_CFG_MEM_API_ENDIAN_SEL_store_mem_endian_sel(unsigned int ustore_mem_endian_sel); +int iSetRING2AXI_CFG_MEM_API_ENDIAN_SEL_load_mem_endian_sel(unsigned int uload_mem_endian_sel); +int iSetRING2AXI_CFG_API_MAX_INDEX_api_max_index(unsigned int uapi_max_index); +int iSetRING2AXI_CFG_BW_axi_rd_acc_max(unsigned int uaxi_rd_acc_max); +int iSetRING2AXI_CFG_BW_axi_wr_acc_max(unsigned int uaxi_wr_acc_max); +int iSetRING2AXI_CFG_API_FLIT_CNT_INIT_rx_api_flit_cnt_init(unsigned int urx_api_flit_cnt_init); +int iSetRING2AXI_CFG_API_FLIT_CNT_INIT_tx_api_flit_cnt_init(unsigned int utx_api_flit_cnt_init); +int iSetRING2AXI_CFG_RX_DISC_FLIT_CNT_CLR_rx_disc_flit_cnt_clr(unsigned int urx_disc_flit_cnt_clr); +int iSetRING2AXI_CFG_RX_DEALED_FLIT_CNT_CLR_rx_dealed_flit_cnt_clr(unsigned int urx_dealed_flit_cnt_clr); +int iSetRING2AXI_FIFO_CFG_asyn_ififo_afull_th(unsigned int uasyn_ififo_afull_th); +int iSetRING2AXI_FIFO_CFG_asyn_efifo_afull_th(unsigned int uasyn_efifo_afull_th); +int iSetRING2AXI_MSGBUF_PI_msgbuf_pi(unsigned int umsgbuf_pi); +int iSetRING2AXI_MSGBUF_PI_msgbuf_pi_sign(unsigned int umsgbuf_pi_sign); +int iSetRING2AXI_MSGBUF_STAT_msgbuf_cnt(unsigned int umsgbuf_cnt); +int iSetRING2AXI_MSGBUF_STAT_msgbuf_empty(unsigned int umsgbuf_empty); +int iSetRING2AXI_MSGBUF_STAT_msgbuf_full(unsigned int umsgbuf_full); +int iSetRING2AXI_MSGBUF_STAT_msgbuf_afull(unsigned int umsgbuf_afull); +int iSetRING2AXI_MSGBUF_OF_UF_msgbuf_of(unsigned int umsgbuf_of); +int iSetRING2AXI_MSGBUF_OF_UF_msgbuf_uf(unsigned int umsgbuf_uf); +int iSetRING2AXI_INNER_BUF_STAT_inner_buf_cnt(unsigned int uinner_buf_cnt); +int iSetRING2AXI_INNER_BUF_STAT_inner_buf_empty(unsigned int uinner_buf_empty); +int iSetRING2AXI_INNER_BUF_STAT_inner_buf_full(unsigned int uinner_buf_full); +int iSetRING2AXI_INNER_BUF_OF_inner_buf_of(unsigned int uinner_buf_of); +int iSetRING2AXI_RX_API_FLIT_CNT_rx_api_flit_cnt(unsigned int urx_api_flit_cnt); +int iSetRING2AXI_TX_API_FLIT_CNT_tx_api_flit_cnt(unsigned int utx_api_flit_cnt); +int iSetRING2AXI_AXI_RD_LATENCY_axi_rd_latency_cnt(unsigned int uaxi_rd_latency_cnt); +int iSetRING2AXI_AXI_WR_LATENCY_axi_wr_latency_cnt(unsigned int uaxi_wr_latency_cnt); +int iSetRING2AXI_AXI_RD_LATENCY_MIN_CNT_axi_rd_latency_min_cnt(unsigned int uaxi_rd_latency_min_cnt); +int iSetRING2AXI_AXI_WR_LATENCY_MIN_CNT_axi_wr_latency_min_cnt(unsigned int uaxi_wr_latency_min_cnt); +int iSetRING2AXI_AXI_RD_LATENCY_MAX_CNT_axi_rd_latency_max_cnt(unsigned int uaxi_rd_latency_max_cnt); +int iSetRING2AXI_AXI_WR_LATENCY_MAX_CNT_axi_wr_latency_max_cnt(unsigned int uaxi_wr_latency_max_cnt); +int iSetRING2AXI_AXI_RD_OTD_CNT_axi_rd_otd_cnt(unsigned int uaxi_rd_otd_cnt); +int iSetRING2AXI_AXI_WR_OTD_CNT_axi_wr_otd_cnt(unsigned int uaxi_wr_otd_cnt); +int iSetRING2AXI_AXI_RD_OTD_MAX_CNT_axi_rd_otd_max_cnt(unsigned int uaxi_rd_otd_max_cnt); +int iSetRING2AXI_AXI_WR_OTD_MAX_CNT_axi_wr_otd_max_cnt(unsigned int uaxi_wr_otd_max_cnt); +int iSetRING2AXI_FSM_STAT_rch_cur_st(unsigned int urch_cur_st); +int iSetRING2AXI_FSM_STAT_r_rsp_cur_st(unsigned int ur_rsp_cur_st); +int iSetRING2AXI_FSM_STAT_wch_cur_st(unsigned int uwch_cur_st); +int iSetRING2AXI_FSM_STAT_w_rsp_cur_st(unsigned int uw_rsp_cur_st); +int iSetRING2AXI_FIFO_ERR_FLAG_store_legal_efifo_of(unsigned int ustore_legal_efifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_load_legal_efifo_of(unsigned int uload_legal_efifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_load_addr_fifo_of(unsigned int uload_addr_fifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_load_cmd_fifo_of(unsigned int uload_cmd_fifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_addr_fifo_of(unsigned int ustore_csr_addr_fifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_store_mem_cmd_fifo_of(unsigned int ustore_mem_cmd_fifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_cmd_fifo_of(unsigned int ustore_csr_cmd_fifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_mem_seq_fifo0_of(unsigned int ustore_csr_mem_seq_fifo0_of); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_mem_seq_fifo1_of(unsigned int ustore_csr_mem_seq_fifo1_of); +int iSetRING2AXI_FIFO_ERR_FLAG_sync_ififo_of_sync(unsigned int usync_ififo_of_sync); +int iSetRING2AXI_FIFO_ERR_FLAG_asyn_ififo_of_sync(unsigned int uasyn_ififo_of_sync); +int iSetRING2AXI_FIFO_ERR_FLAG_asyn_efifo_of(unsigned int uasyn_efifo_of); +int iSetRING2AXI_FIFO_ERR_FLAG_store_legal_efifo_uf(unsigned int ustore_legal_efifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_load_legal_efifo_uf(unsigned int uload_legal_efifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_load_addr_fifo_uf(unsigned int uload_addr_fifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_load_cmd_fifo_uf(unsigned int uload_cmd_fifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_addr_fifo_uf(unsigned int ustore_csr_addr_fifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_store_mem_cmd_fifo_uf(unsigned int ustore_mem_cmd_fifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_cmd_fifo_uf(unsigned int ustore_csr_cmd_fifo_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_mem_seq_fifo0_uf(unsigned int ustore_csr_mem_seq_fifo0_uf); +int iSetRING2AXI_FIFO_ERR_FLAG_store_csr_mem_seq_fifo1_uf(unsigned int ustore_csr_mem_seq_fifo1_uf); +int iSetRING2AXI_STORE_LEGAL_EFIFO_STAT_store_legal_efifo_cnt(unsigned int ustore_legal_efifo_cnt); +int iSetRING2AXI_STORE_LEGAL_EFIFO_STAT_store_legal_efifo_empty(unsigned int ustore_legal_efifo_empty); +int iSetRING2AXI_STORE_LEGAL_EFIFO_STAT_store_legal_efifo_full(unsigned int ustore_legal_efifo_full); +int iSetRING2AXI_LOAD_LEGAL_EFIFO_STAT_load_legal_efifo_cnt(unsigned int uload_legal_efifo_cnt); +int iSetRING2AXI_LOAD_LEGAL_EFIFO_STAT_load_legal_efifo_empty(unsigned int uload_legal_efifo_empty); +int iSetRING2AXI_LOAD_LEGAL_EFIFO_STAT_load_legal_efifo_full(unsigned int uload_legal_efifo_full); +int iSetRING2AXI_LOAD_ADDR_FIFO_STAT_load_addr_fifo_cnt(unsigned int uload_addr_fifo_cnt); +int iSetRING2AXI_LOAD_ADDR_FIFO_STAT_load_addr_fifo_empty(unsigned int uload_addr_fifo_empty); +int iSetRING2AXI_LOAD_ADDR_FIFO_STAT_load_addr_fifo_full(unsigned int uload_addr_fifo_full); +int iSetRING2AXI_LOAD_CMD_FIFO_STAT_load_cmd_fifo_cnt(unsigned int uload_cmd_fifo_cnt); +int iSetRING2AXI_LOAD_CMD_FIFO_STAT_load_cmd_fifo_empty(unsigned int uload_cmd_fifo_empty); +int iSetRING2AXI_LOAD_CMD_FIFO_STAT_load_cmd_fifo_full(unsigned int uload_cmd_fifo_full); +int iSetRING2AXI_STORE_CSR_ADDR_FIFO_STAT_store_csr_addr_fifo_cnt(unsigned int ustore_csr_addr_fifo_cnt); +int iSetRING2AXI_STORE_CSR_ADDR_FIFO_STAT_store_csr_addr_fifo_empty(unsigned int ustore_csr_addr_fifo_empty); +int iSetRING2AXI_STORE_CSR_ADDR_FIFO_STAT_store_csr_addr_fifo_full(unsigned int ustore_csr_addr_fifo_full); +int iSetRING2AXI_STORE_MEM_CMD_FIFO_STAT_store_mem_cmd_fifo_cnt(unsigned int ustore_mem_cmd_fifo_cnt); +int iSetRING2AXI_STORE_MEM_CMD_FIFO_STAT_store_mem_cmd_fifo_empty(unsigned int ustore_mem_cmd_fifo_empty); +int iSetRING2AXI_STORE_MEM_CMD_FIFO_STAT_store_mem_cmd_fifo_full(unsigned int ustore_mem_cmd_fifo_full); +int iSetRING2AXI_STORE_CSR_CMD_FIFO_STAT_store_csr_cmd_fifo_cnt(unsigned int ustore_csr_cmd_fifo_cnt); +int iSetRING2AXI_STORE_CSR_CMD_FIFO_STAT_store_csr_cmd_fifo_empty(unsigned int ustore_csr_cmd_fifo_empty); +int iSetRING2AXI_STORE_CSR_CMD_FIFO_STAT_store_csr_cmd_fifo_full(unsigned int ustore_csr_cmd_fifo_full); +int iSetRING2AXI_STORE_CSR_MEM_FIFO0_STAT_store_csr_mem_seq_fifo0_cnt(unsigned int ustore_csr_mem_seq_fifo0_cnt); +int iSetRING2AXI_STORE_CSR_MEM_FIFO0_STAT_store_csr_mem_seq_fifo0_empty(unsigned int ustore_csr_mem_seq_fifo0_empty); +int iSetRING2AXI_STORE_CSR_MEM_FIFO0_STAT_store_csr_mem_seq_fifo0_full(unsigned int ustore_csr_mem_seq_fifo0_full); +int iSetRING2AXI_STORE_CSR_MEM_FIFO1_STAT_store_csr_mem_seq_fifo1_cnt(unsigned int ustore_csr_mem_seq_fifo1_cnt); +int iSetRING2AXI_STORE_CSR_MEM_FIFO1_STAT_store_csr_mem_seq_fifo1_empty(unsigned int ustore_csr_mem_seq_fifo1_empty); +int iSetRING2AXI_STORE_CSR_MEM_FIFO1_STAT_store_csr_mem_seq_fifo1_full(unsigned int ustore_csr_mem_seq_fifo1_full); +int iSetRING2AXI_IF_FIFO_CNT_sync_ififo_cnt_sync(unsigned int usync_ififo_cnt_sync); +int iSetRING2AXI_IF_FIFO_CNT_asyn_ififo_rcnt(unsigned int uasyn_ififo_rcnt); +int iSetRING2AXI_IF_FIFO_CNT_asyn_efifo_wcnt(unsigned int uasyn_efifo_wcnt); +int iSetRING2AXI_EJECTION_CRDT_CNT_crdt_cnt_sync(unsigned int ucrdt_cnt_sync); +int iSetRING2AXI_ILLEGAL_STAT_api_illegal_index(unsigned int uapi_illegal_index); +int iSetRING2AXI_STORE_MEM_API_STAT_store_mem_api_vld(unsigned int ustore_mem_api_vld); +int iSetRING2AXI_STORE_MEM_API_STAT_store_mem_flit_cnt(unsigned int ustore_mem_flit_cnt); +int iSetRING2AXI_STORE_MEM_API_STAT_store_mem_api_4flit(unsigned int ustore_mem_api_4flit); +int iSetRING2AXI_RX_DISC_FLIT_CNT_rx_disc_flit_cnt(unsigned int urx_disc_flit_cnt); +int iSetRING2AXI_RX_DEALED_FLIT_CNT_rx_dealed_flit_cnt(unsigned int urx_dealed_flit_cnt); +int iSetRING2AXI_UP_FILT_CNT_up_flit_cfg_cnt(unsigned int uup_flit_cfg_cnt); +int iSetRING2AXI_DN_FILT_CNT_dn_flit_cfg_cnt(unsigned int udn_flit_cfg_cnt); +int iSetRING2AXI_VERSION_ring2axi_version(unsigned int uring2axi_version); + +/* Define the union csr_int_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_stat : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_stat_u; + +/* Define the union csr_int_tc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_tc1 : 8; /* [7:0] */ + u32 rsv_1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tc1_u; + +/* Define the union csr_int_tc2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_tc2 : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tc2_u; + +/* Define the union csr_int_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err1 : 8; /* [7:0] */ + u32 rsv_3 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err1_u; + +/* Define the union csr_int_err2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err2 : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err2_u; + +/* Define the union csr_int_err3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err3 : 8; /* [7:0] */ + u32 rsv_5 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err3_u; + +/* Define the union csr_int_tc1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_tc1_mask : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tc1_mask_u; + +/* Define the union csr_int_tc2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_tc2_mask : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tc2_mask_u; + +/* Define the union csr_int_err1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err1_mask : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err1_mask_u; + +/* Define the union csr_int_err2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err2_mask : 8; /* [7:0] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err2_mask_u; + +/* Define the union csr_int_err3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err3_mask : 8; /* [7:0] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err3_mask_u; + +/* Define the union csr_int_tc1_raw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_tc1_raw : 8; /* [7:0] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tc1_raw_u; + +/* Define the union csr_int_tc2_raw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_tc2_raw : 8; /* [7:0] */ + u32 rsv_12 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tc2_raw_u; + +/* Define the union csr_int_err1_raw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err1_raw : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err1_raw_u; + +/* Define the union csr_int_err2_raw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err2_raw : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err2_raw_u; + +/* Define the union csr_int_err3_raw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_err3_raw : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_err3_raw_u; + +/* Define the union csr_sreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sreq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sreq_u; + +/* Define the union csr_lsreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lsreq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lsreq_u; + +/* Define the union csr_breq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 breq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_breq_u; + +/* Define the union csr_lbreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lbreq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lbreq_u; + +/* Define the union csr_freq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 freq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_freq_u; + +/* Define the union csr_lfreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lfreq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lfreq_u; + +/* Define the union csr_ch_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch0_pri : 2; /* [1:0] */ + u32 ch1_pri : 2; /* [3:2] */ + u32 ch2_pri : 2; /* [5:4] */ + u32 ch3_pri : 2; /* [7:6] */ + u32 ch4_pri : 2; /* [9:8] */ + u32 ch5_pri : 2; /* [11:10] */ + u32 ch6_pri : 2; /* [13:12] */ + u32 ch7_pri : 2; /* [15:14] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ch_pri_u; + +/* Define the union csr_ch_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_stat : 8; /* [7:0] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ch_stat_u; + +/* Define the union csr_dma_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 halt_ack : 1; /* [0] */ + u32 halt_req : 1; /* [1] */ + u32 rsv_18 : 2; /* [3:2] */ + u32 conf_out4 : 1; /* [4] */ + u32 rsv_19 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_u; + +/* Define the union csr_cx_curr_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_c_count : 16; /* [15:0] */ + u32 rsv_20 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_curr_cnt1_u; + +/* Define the union csr_cx_curr_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_a_count : 16; /* [15:0] */ + u32 curr_b_count : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_curr_cnt0_u; + +/* Define the union csr_cx_curr_src_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_src_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_curr_src_addr_u; + +/* Define the union csr_cx_curr_des_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_des_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_curr_des_addr_u; + +/* Define the union csr_cx_lli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chain_en : 2; /* [1:0] */ + u32 rsv_21 : 3; /* [4:2] */ + u32 lli : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_lli_u; + +/* Define the union csr_cx_bindx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_bindx : 15; /* [14:0] */ + u32 des_bsign : 1; /* [15] */ + u32 src_bindx : 15; /* [30:16] */ + u32 src_bsign : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_bindx_u; + +/* Define the union csr_cx_cindx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_cindx : 15; /* [14:0] */ + u32 des_csign : 1; /* [15] */ + u32 src_cindx : 15; /* [30:16] */ + u32 src_csign : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_cindx_u; + +/* Define the union csr_cx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c_count : 16; /* [15:0] */ + u32 rsv_22 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_cnt1_u; + +/* Define the union csr_cx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a_count : 16; /* [15:0] */ + u32 b_count : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_cnt0_u; + +/* Define the union csr_cx_src_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_src_addr_u; + +/* Define the union csr_cx_des_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_des_addr_u; + +/* Define the union csr_cx_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_en : 1; /* [0] */ + u32 itc_en : 1; /* [1] */ + u32 flow_ctrl : 2; /* [3:2] */ + u32 peri : 6; /* [9:4] */ + u32 rsv_23 : 2; /* [11:10] */ + u32 dw : 3; /* [14:12] */ + u32 rsv_24 : 1; /* [15] */ + u32 sw : 3; /* [18:16] */ + u32 rsv_25 : 1; /* [19] */ + u32 dl : 4; /* [23:20] */ + u32 sl : 4; /* [27:24] */ + u32 dmode : 1; /* [28] */ + u32 smode : 1; /* [29] */ + u32 di : 1; /* [30] */ + u32 si : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_config_u; + +/* Define the union csr_cx_axi_conf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aruser : 5; /* [4:0] */ + u32 arprot : 3; /* [7:5] */ + u32 arcache : 4; /* [11:8] */ + u32 awuser : 5; /* [16:12] */ + u32 awprot : 3; /* [19:17] */ + u32 awcache : 4; /* [23:20] */ + u32 rsv_26 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cx_axi_conf_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_int_stat_u int_stat; /* 0 */ + volatile csr_int_tc1_u int_tc1; /* 4 */ + volatile csr_int_tc2_u int_tc2; /* 8 */ + volatile csr_int_err1_u int_err1; /* C */ + volatile csr_int_err2_u int_err2; /* 10 */ + volatile csr_int_err3_u int_err3; /* 14 */ + volatile csr_int_tc1_mask_u int_tc1_mask; /* 18 */ + volatile csr_int_tc2_mask_u int_tc2_mask; /* 1C */ + volatile csr_int_err1_mask_u int_err1_mask; /* 20 */ + volatile csr_int_err2_mask_u int_err2_mask; /* 24 */ + volatile csr_int_err3_mask_u int_err3_mask; /* 28 */ + volatile csr_int_tc1_raw_u int_tc1_raw; /* 600 */ + volatile csr_int_tc2_raw_u int_tc2_raw; /* 608 */ + volatile csr_int_err1_raw_u int_err1_raw; /* 610 */ + volatile csr_int_err2_raw_u int_err2_raw; /* 618 */ + volatile csr_int_err3_raw_u int_err3_raw; /* 620 */ + volatile csr_sreq_u sreq; /* 660 */ + volatile csr_lsreq_u lsreq; /* 664 */ + volatile csr_breq_u breq; /* 668 */ + volatile csr_lbreq_u lbreq; /* 66C */ + volatile csr_freq_u freq; /* 670 */ + volatile csr_lfreq_u lfreq; /* 674 */ + volatile csr_ch_pri_u ch_pri; /* 688 */ + volatile csr_ch_stat_u ch_stat; /* 690 */ + volatile csr_dma_ctrl_u dma_ctrl; /* 698 */ + volatile csr_cx_curr_cnt1_u cx_curr_cnt1[16]; /* 700 */ + volatile csr_cx_curr_cnt0_u cx_curr_cnt0[16]; /* 704 */ + volatile csr_cx_curr_src_addr_u cx_curr_src_addr[16]; /* 708 */ + volatile csr_cx_curr_des_addr_u cx_curr_des_addr[16]; /* 70C */ + volatile csr_cx_lli_u cx_lli[16]; /* 800 */ + volatile csr_cx_bindx_u cx_bindx[16]; /* 804 */ + volatile csr_cx_cindx_u cx_cindx[16]; /* 808 */ + volatile csr_cx_cnt1_u cx_cnt1[16]; /* 80C */ + volatile csr_cx_cnt0_u cx_cnt0[16]; /* 810 */ + volatile csr_cx_src_addr_u cx_src_addr[16]; /* 814 */ + volatile csr_cx_des_addr_u cx_des_addr[16]; /* 818 */ + volatile csr_cx_config_u cx_config[16]; /* 81C */ + volatile csr_cx_axi_conf_u cx_axi_conf[16]; /* 820 */ +} S_dmac_REGS_TYPE; + +/* Declare the struct pointor of the module dmac */ +extern volatile S_dmac_REGS_TYPE *gopdmacAllReg; + +/* Declare the functions that set the member value */ +int iSetINT_STAT_int_stat(unsigned int uint_stat); +int iSetINT_TC1_int_tc1(unsigned int uint_tc1); +int iSetINT_TC2_int_tc2(unsigned int uint_tc2); +int iSetINT_ERR1_int_err1(unsigned int uint_err1); +int iSetINT_ERR2_int_err2(unsigned int uint_err2); +int iSetINT_ERR3_int_err3(unsigned int uint_err3); +int iSetINT_TC1_MASK_int_tc1_mask(unsigned int uint_tc1_mask); +int iSetINT_TC2_MASK_int_tc2_mask(unsigned int uint_tc2_mask); +int iSetINT_ERR1_MASK_int_err1_mask(unsigned int uint_err1_mask); +int iSetINT_ERR2_MASK_int_err2_mask(unsigned int uint_err2_mask); +int iSetINT_ERR3_MASK_int_err3_mask(unsigned int uint_err3_mask); +int iSetINT_TC1_RAW_int_tc1_raw(unsigned int uint_tc1_raw); +int iSetINT_TC2_RAW_int_tc2_raw(unsigned int uint_tc2_raw); +int iSetINT_ERR1_RAW_int_err1_raw(unsigned int uint_err1_raw); +int iSetINT_ERR2_RAW_int_err2_raw(unsigned int uint_err2_raw); +int iSetINT_ERR3_RAW_int_err3_raw(unsigned int uint_err3_raw); +int iSetSREQ_sreq(unsigned int usreq); +int iSetLSREQ_lsreq(unsigned int ulsreq); +int iSetBREQ_breq(unsigned int ubreq); +int iSetLBREQ_lbreq(unsigned int ulbreq); +int iSetFREQ_freq(unsigned int ufreq); +int iSetLFREQ_lfreq(unsigned int ulfreq); +int iSetCH_PRI_ch0_pri(unsigned int uch0_pri); +int iSetCH_PRI_ch1_pri(unsigned int uch1_pri); +int iSetCH_PRI_ch2_pri(unsigned int uch2_pri); +int iSetCH_PRI_ch3_pri(unsigned int uch3_pri); +int iSetCH_PRI_ch4_pri(unsigned int uch4_pri); +int iSetCH_PRI_ch5_pri(unsigned int uch5_pri); +int iSetCH_PRI_ch6_pri(unsigned int uch6_pri); +int iSetCH_PRI_ch7_pri(unsigned int uch7_pri); +int iSetCH_STAT_ch_stat(unsigned int uch_stat); +int iSetDMA_CTRL_halt_ack(unsigned int uhalt_ack); +int iSetDMA_CTRL_halt_req(unsigned int uhalt_req); +int iSetDMA_CTRL_conf_out4(unsigned int uconf_out4); +int iSetCX_CURR_CNT1_curr_c_count(unsigned int ucurr_c_count); +int iSetCX_CURR_CNT0_curr_a_count(unsigned int ucurr_a_count); +int iSetCX_CURR_CNT0_curr_b_count(unsigned int ucurr_b_count); +int iSetCX_CURR_SRC_ADDR_curr_src_addr(unsigned int ucurr_src_addr); +int iSetCX_CURR_DES_ADDR_curr_des_addr(unsigned int ucurr_des_addr); +int iSetCX_LLI_chain_en(unsigned int uchain_en); +int iSetCX_LLI_lli(unsigned int ulli); +int iSetCX_BINDX_des_bindx(unsigned int udes_bindx); +int iSetCX_BINDX_des_bsign(unsigned int udes_bsign); +int iSetCX_BINDX_src_bindx(unsigned int usrc_bindx); +int iSetCX_BINDX_src_bsign(unsigned int usrc_bsign); +int iSetCX_CINDX_des_cindx(unsigned int udes_cindx); +int iSetCX_CINDX_des_csign(unsigned int udes_csign); +int iSetCX_CINDX_src_cindx(unsigned int usrc_cindx); +int iSetCX_CINDX_src_csign(unsigned int usrc_csign); +int iSetCX_CNT1_c_count(unsigned int uc_count); +int iSetCX_CNT0_a_count(unsigned int ua_count); +int iSetCX_CNT0_b_count(unsigned int ub_count); +int iSetCX_SRC_ADDR_src_addr(unsigned int usrc_addr); +int iSetCX_DES_ADDR_des_addr(unsigned int udes_addr); +int iSetCX_CONFIG_ch_en(unsigned int uch_en); +int iSetCX_CONFIG_itc_en(unsigned int uitc_en); +int iSetCX_CONFIG_flow_ctrl(unsigned int uflow_ctrl); +int iSetCX_CONFIG_peri(unsigned int uperi); +int iSetCX_CONFIG_dw(unsigned int udw); +int iSetCX_CONFIG_sw(unsigned int usw); +int iSetCX_CONFIG_dl(unsigned int udl); +int iSetCX_CONFIG_sl(unsigned int usl); +int iSetCX_CONFIG_dmode(unsigned int udmode); +int iSetCX_CONFIG_smode(unsigned int usmode); +int iSetCX_CONFIG_di(unsigned int udi); +int iSetCX_CONFIG_si(unsigned int usi); +int iSetCX_AXI_CONF_aruser(unsigned int uaruser); +int iSetCX_AXI_CONF_arprot(unsigned int uarprot); +int iSetCX_AXI_CONF_arcache(unsigned int uarcache); +int iSetCX_AXI_CONF_awuser(unsigned int uawuser); +int iSetCX_AXI_CONF_awprot(unsigned int uawprot); +int iSetCX_AXI_CONF_awcache(unsigned int uawcache); + +/* Define the union csr_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_u; + +/* Define the union csr_sc_test0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test0_u; + +/* Define the union csr_sc_test1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test1_u; + +/* Define the union csr_sc_test2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test2_u; + +/* Define the union csr_sc_test3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test3_u; + +/* Define the union csr_sc_test4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test4_u; + +/* Define the union csr_sc_test5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test5_u; + +/* Define the union csr_sc_test6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test6_u; + +/* Define the union csr_sc_test7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test7_u; + +/* Define the union csr_sc_test8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test8_u; + +/* Define the union csr_sc_test9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test9_u; + +/* Define the union csr_sc_test10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test10_u; + +/* Define the union csr_sc_test11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test11_u; + +/* Define the union csr_sc_test12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test12_u; + +/* Define the union csr_sc_test13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test13_u; + +/* Define the union csr_sc_test14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test14_u; + +/* Define the union csr_sc_test15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test15_u; + +/* Define the union csr_sc_test16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test16_u; + +/* Define the union csr_sc_test17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test17_u; + +/* Define the union csr_sc_test18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test18_u; + +/* Define the union csr_sc_test19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test19_u; + +/* Define the union csr_sc_test20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test20_u; + +/* Define the union csr_sc_test21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test21_u; + +/* Define the union csr_sc_test22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test22_u; + +/* Define the union csr_sc_test23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test23_u; + +/* Define the union csr_sc_test24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test24_u; + +/* Define the union csr_sc_test25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test25_u; + +/* Define the union csr_sc_test26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test26_u; + +/* Define the union csr_sc_test27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test27_u; + +/* Define the union csr_sc_test28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test28_u; + +/* Define the union csr_sc_test29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test29_u; + +/* Define the union csr_sc_test30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test30_u; + +/* Define the union csr_sc_test31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_test31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_test31_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_rsv_u rsv; /* 24 */ + volatile csr_sc_test0_u sc_test0; /* 100 */ + volatile csr_sc_test1_u sc_test1; /* 104 */ + volatile csr_sc_test2_u sc_test2; /* 108 */ + volatile csr_sc_test3_u sc_test3; /* 10C */ + volatile csr_sc_test4_u sc_test4; /* 110 */ + volatile csr_sc_test5_u sc_test5; /* 114 */ + volatile csr_sc_test6_u sc_test6; /* 118 */ + volatile csr_sc_test7_u sc_test7; /* 11C */ + volatile csr_sc_test8_u sc_test8; /* 120 */ + volatile csr_sc_test9_u sc_test9; /* 124 */ + volatile csr_sc_test10_u sc_test10; /* 128 */ + volatile csr_sc_test11_u sc_test11; /* 12C */ + volatile csr_sc_test12_u sc_test12; /* 130 */ + volatile csr_sc_test13_u sc_test13; /* 134 */ + volatile csr_sc_test14_u sc_test14; /* 138 */ + volatile csr_sc_test15_u sc_test15; /* 13C */ + volatile csr_sc_test16_u sc_test16; /* 140 */ + volatile csr_sc_test17_u sc_test17; /* 144 */ + volatile csr_sc_test18_u sc_test18; /* 148 */ + volatile csr_sc_test19_u sc_test19; /* 14C */ + volatile csr_sc_test20_u sc_test20; /* 150 */ + volatile csr_sc_test21_u sc_test21; /* 154 */ + volatile csr_sc_test22_u sc_test22; /* 158 */ + volatile csr_sc_test23_u sc_test23; /* 15C */ + volatile csr_sc_test24_u sc_test24; /* 160 */ + volatile csr_sc_test25_u sc_test25; /* 164 */ + volatile csr_sc_test26_u sc_test26; /* 168 */ + volatile csr_sc_test27_u sc_test27; /* 16C */ + volatile csr_sc_test28_u sc_test28; /* 170 */ + volatile csr_sc_test29_u sc_test29; /* 174 */ + volatile csr_sc_test30_u sc_test30; /* 178 */ + volatile csr_sc_test31_u sc_test31; /* 17C */ +} S_sysctrl_csr0_REGS_TYPE; + +/* Declare the struct pointor of the module sysctrl_csr0 */ +extern volatile S_sysctrl_csr0_REGS_TYPE *gopsysctrl_csr0AllReg; + +/* Declare the functions that set the member value */ +int iSetRSV_rsv(unsigned int ursv); +int iSetSC_TEST0_sc_test0(unsigned int usc_test0); +int iSetSC_TEST1_sc_test1(unsigned int usc_test1); +int iSetSC_TEST2_sc_test2(unsigned int usc_test2); +int iSetSC_TEST3_sc_test3(unsigned int usc_test3); +int iSetSC_TEST4_sc_test4(unsigned int usc_test4); +int iSetSC_TEST5_sc_test5(unsigned int usc_test5); +int iSetSC_TEST6_sc_test6(unsigned int usc_test6); +int iSetSC_TEST7_sc_test7(unsigned int usc_test7); +int iSetSC_TEST8_sc_test8(unsigned int usc_test8); +int iSetSC_TEST9_sc_test9(unsigned int usc_test9); +int iSetSC_TEST10_sc_test10(unsigned int usc_test10); +int iSetSC_TEST11_sc_test11(unsigned int usc_test11); +int iSetSC_TEST12_sc_test12(unsigned int usc_test12); +int iSetSC_TEST13_sc_test13(unsigned int usc_test13); +int iSetSC_TEST14_sc_test14(unsigned int usc_test14); +int iSetSC_TEST15_sc_test15(unsigned int usc_test15); +int iSetSC_TEST16_sc_test16(unsigned int usc_test16); +int iSetSC_TEST17_sc_test17(unsigned int usc_test17); +int iSetSC_TEST18_sc_test18(unsigned int usc_test18); +int iSetSC_TEST19_sc_test19(unsigned int usc_test19); +int iSetSC_TEST20_sc_test20(unsigned int usc_test20); +int iSetSC_TEST21_sc_test21(unsigned int usc_test21); +int iSetSC_TEST22_sc_test22(unsigned int usc_test22); +int iSetSC_TEST23_sc_test23(unsigned int usc_test23); +int iSetSC_TEST24_sc_test24(unsigned int usc_test24); +int iSetSC_TEST25_sc_test25(unsigned int usc_test25); +int iSetSC_TEST26_sc_test26(unsigned int usc_test26); +int iSetSC_TEST27_sc_test27(unsigned int usc_test27); +int iSetSC_TEST28_sc_test28(unsigned int usc_test28); +int iSetSC_TEST29_sc_test29(unsigned int usc_test29); +int iSetSC_TEST30_sc_test30(unsigned int usc_test30); +int iSetSC_TEST31_sc_test31(unsigned int usc_test31); + +/* Define the union csr_sc_up_tile_bitmap_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_up_tile_bitmap_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_up_tile_bitmap_en_u; + +/* Define the union csr_sc_tile_bitmap_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_tile_bitmap_stat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_tile_bitmap_stat_u; + +/* Define the union csr_sc_tile_bitmap_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_tile_bitmap_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_tile_bitmap_set_u; + +/* Define the union csr_mcore_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mcore_stat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mcore_stat_u; + +/* Define the union csr_mcore_stat_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mcore_stat_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mcore_stat_set_u; + +/* Define the union csr_mpu_mcore_stat_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_mcore_stat_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_mcore_stat_set_u; + +/* Define the union csr_c2j_mbist_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbist_written : 1; /* [0] */ + u32 mbist_enable : 1; /* [1] */ + u32 mbist_resetn : 1; /* [2] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_mbist_ctrl_u; + +/* Define the union csr_c2j_mbist_datain_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbist_datain : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_mbist_datain_u; + +/* Define the union csr_c2j_mbist_dataout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbist_dataout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_mbist_dataout_u; + +/* Define the union csr_a55_sub_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gic600_fault_int_status : 1; /* [0] */ + u32 gic600_err_int_status : 1; /* [1] */ + u32 gic600_pmu_int_status : 1; /* [2] */ + u32 nfaultirq_int_status : 2; /* [4:3] */ + u32 nerrirq_int_status : 2; /* [6:5] */ + u32 ncommirq_int_status : 1; /* [7] */ + u32 nclusterpmuirq_int_status : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_sub_int_status_u; + +/* Define the union csr_a55_sub_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gic600_fault_int_en : 1; /* [0] */ + u32 gic600_err_int_en : 1; /* [1] */ + u32 gic600_pmu_int_en : 1; /* [2] */ + u32 nfaultirq_int_en : 2; /* [4:3] */ + u32 nerrirq_int_en : 2; /* [6:5] */ + u32 ncommirq_int_en : 1; /* [7] */ + u32 nclusterpmuirq_int_en : 1; /* [8] */ + u32 gic600_fault_unc_en : 1; /* [9] */ + u32 gic600_err_unc_en : 1; /* [10] */ + u32 nfaultirq_unc_en : 2; /* [12:11] */ + u32 nerrirq_unc_en : 2; /* [14:13] */ + u32 rsv_2 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_sub_int_en_u; + +/* Define the union csr_a55_sub_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gic600_fault_int_set : 1; /* [0] */ + u32 gic600_err_int_set : 1; /* [1] */ + u32 gic600_pmu_int_set : 1; /* [2] */ + u32 nfaultirq_int_set : 2; /* [4:3] */ + u32 nerrirq_int_set : 2; /* [6:5] */ + u32 ncommirq_int_set : 1; /* [7] */ + u32 nclusterpmuirq_int_set : 1; /* [8] */ + u32 rsv_3 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_sub_int_set_u; + +/* Define the union csr_a55_sub_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gic600_fault_int_raw_status : 1; /* [0] */ + u32 gic600_err_int_raw_status : 1; /* [1] */ + u32 gic600_pmu_int_raw_status : 1; /* [2] */ + u32 nfaultirq_int_raw_status : 2; /* [4:3] */ + u32 nerrirq_int_raw_status : 2; /* [6:5] */ + u32 ncommirq_int_raw_status : 1; /* [7] */ + u32 nclusterpmuirq_int_raw_status : 1; /* [8] */ + u32 rsv_4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_sub_int_raw_status_u; + +/* Define the union csr_r52_wfi_wfe_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_wfi_wfe_stat : 2; /* [1:0] */ + u32 rsv_5 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_r52_wfi_wfe_stat_u; + +/* Define the union csr_ncsi_func_mbist_clk_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 func_mbist_clk_sel : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_func_mbist_clk_sel_u; + +/* Define the union csr_wol_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt_wol_int_status : 4; /* [3:0] */ + u32 pcie_prt_lp_req_int_status : 4; /* [7:4] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wol_int_status_u; + +/* Define the union csr_wol_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt_wol_int_en : 4; /* [3:0] */ + u32 pcie_prt_lp_req_int_en : 4; /* [7:4] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wol_int_en_u; + +/* Define the union csr_wol_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wol_int_set : 4; /* [3:0] */ + u32 rsv_9 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wol_int_set_u; + +/* Define the union csr_wol_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt_wol_int_raw_status : 4; /* [3:0] */ + u32 pcie_prt_lp_req_int_raw_status : 4; /* [7:4] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wol_int_raw_status_u; + +/* Define the union csr_wol_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt_mag_en : 4; /* [3:0] */ + u32 pcie_prt_link_en : 4; /* [7:4] */ + u32 pcie_prt_wol_en : 4; /* [11:8] */ + u32 rsv_11 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wol_ctl_u; + +/* Define the union csr_lp_intset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt0_lp_req_int_set : 1; /* [0] */ + u32 rsv_12 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lp_intset0_u; + +/* Define the union csr_lp_intset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt1_lp_req_int_set : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lp_intset1_u; + +/* Define the union csr_lp_intset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt2_lp_req_int_set : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lp_intset2_u; + +/* Define the union csr_lp_intset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_prt3_lp_req_int_set : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lp_intset3_u; + +/* Define the union csr_lp_ready_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_ready : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lp_ready_u; + +/* Define the union csr_perstn_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_int_status : 8; /* [7:0] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_int_status_u; + +/* Define the union csr_perstn_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_int_en : 8; /* [7:0] */ + u32 rsv_18 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_int_en_u; + +/* Define the union csr_perstn_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_int_set : 8; /* [7:0] */ + u32 rsv_19 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_int_set_u; + +/* Define the union csr_perstn_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_int_raw_status : 8; /* [7:0] */ + u32 rsv_20 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_int_raw_status_u; + +/* Define the union csr_up_uncrt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_uncrt_en : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_uncrt_en_u; + +/* Define the union csr_axi_bresp_mon_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_bresp_stats : 30; /* [29:0] */ + u32 axi_bresp_clr : 1; /* [30] */ + u32 rsv_22 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_bresp_mon_u; + +/* Define the union csr_axi_rresp_mon_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rresp_stats : 30; /* [29:0] */ + u32 axi_rresp_clr : 1; /* [30] */ + u32 rsv_23 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rresp_mon_u; + +/* Define the union csr_axi_resp_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rsp_mask_en : 1; /* [0] */ + u32 hiss_axi_rsp_mask_en : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_resp_mask_u; + +/* Define the union csr_perstn_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_status : 4; /* [3:0] */ + u32 rsv_25 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_status_u; + +/* Define the union csr_perstn_hiss_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_hiss_int_status : 8; /* [7:0] */ + u32 rsv_26 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_hiss_int_status_u; + +/* Define the union csr_perstn_hiss_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perstn_hiss_int_en : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perstn_hiss_int_en_u; + +/* Define the union csr_axi4toaxi3_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_axi4toaxi3_byapss : 1; /* [0] */ + u32 rsv_28 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi4toaxi3_bypass_u; + +/* Define the union csr_axi4toaxi3_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_axi4toaxi3_fifo_empty : 1; /* [0] */ + u32 sc_axi4toaxi3_fifo_full : 1; /* [1] */ + u32 sc_axi4toaxi3_aw_err : 1; /* [2] */ + u32 rsv_29 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi4toaxi3_status_u; + +/* Define the union csr_smb_dw_apb_i2c_debug_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smb_debug_addr_10bit : 1; /* [0] */ + u32 smb_debug_slaver_act : 1; /* [1] */ + u32 smb_debug_master_act : 1; /* [2] */ + u32 smb_debug_hs : 1; /* [3] */ + u32 smb_debug_wr : 1; /* [4] */ + u32 smb_debug_rd : 1; /* [5] */ + u32 smb_debug_addr : 1; /* [6] */ + u32 smb_debug_adata : 1; /* [7] */ + u32 smb_debug_p_gen : 1; /* [8] */ + u32 smb_debug_s_gen : 1; /* [9] */ + u32 smb_debug_slv_cstate : 4; /* [13:10] */ + u32 smb_debug_mst_cstate : 5; /* [18:14] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_dw_apb_i2c_debug_u; + +/* Define the union csr_a55_fcm_cluster_config0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_sc_sercure_debug_en : 1; /* [0] */ + u32 a55_sc_stretch_l2ramclk_en : 1; /* [1] */ + u32 rsv_31 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_fcm_cluster_config0_u; + +/* Define the union csr_a55_fcm_cluster_config1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_aa64naa32 : 1; /* [0] */ + u32 a55_cfgend : 1; /* [1] */ + u32 a55_cfgte : 1; /* [2] */ + u32 a55_clusteridaff2 : 8; /* [10:3] */ + u32 a55_clusteridaff3 : 8; /* [18:11] */ + u32 a55_giccdisable : 1; /* [19] */ + u32 a55_vinithi : 1; /* [20] */ + u32 nfiq : 1; /* [21] */ + u32 nirq : 1; /* [22] */ + u32 rsv_32 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_fcm_cluster_config1_u; + +/* Define the union csr_a55_rvbaraddry_cfg_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_rvbaraddry_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_rvbaraddry_cfg_l_u; + +/* Define the union csr_a55_rvbaraddry_cfg_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_rvbaraddry_h : 6; /* [5:0] */ + u32 rsv_33 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_rvbaraddry_cfg_h_u; + +/* Define the union csr_a55_broadcast_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_broadcastcachemaint : 1; /* [0] */ + u32 a55_broadcastcachemaintpou : 1; /* [1] */ + u32 a55_broadcastpersist : 1; /* [2] */ + u32 a55_broadcastouter : 1; /* [3] */ + u32 rsv_34 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_broadcast_cfg_u; + +/* Define the union csr_a55_debug_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_dbgen : 1; /* [0] */ + u32 a55_niden : 1; /* [1] */ + u32 a55_spiden : 1; /* [2] */ + u32 a55_spniden : 1; /* [3] */ + u32 a55_dbgconnected : 1; /* [4] */ + u32 rsv_35 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_debug_cfg_u; + +/* Define the union csr_a55_fcm_cluster_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_custom_wfi : 1; /* [0] */ + u32 a55_custom_wfe : 1; /* [1] */ + u32 a55_sc_pmccnt_q63bit : 1; /* [2] */ + u32 a55_sc_gic_irq : 1; /* [3] */ + u32 a55_sc_gic_fiq : 1; /* [4] */ + u32 a55_sc_dbg_ack : 1; /* [5] */ + u32 reg_clusterpmccntr_63bit : 1; /* [6] */ + u32 rsv_36 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_fcm_cluster_status_u; + +/* Define the union csr_a55_pmu_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_coreinstrret : 1; /* [0] */ + u32 a55_coreinstrrun : 1; /* [1] */ + u32 rsv_37 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_pmu_status_u; + +/* Define the union csr_dbg_block_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_block_dbgpwrupreq : 1; /* [0] */ + u32 dbg_block_clusterdbgpwrupreq : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbg_block_status_u; + +/* Define the union csr_gic600_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gic600_sample_req_gic : 1; /* [0] */ + u32 gic600_gict_allow_ns : 1; /* [1] */ + u32 gic600_gicp_allow_ns : 1; /* [2] */ + u32 gic600_cpu_active : 1; /* [3] */ + u32 rsv_39 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gic600_cfg_u; + +/* Define the union csr_gic600_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gic600_sample_ack_gic : 1; /* [0] */ + u32 rsv_40 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gic600_status_u; + +/* Define the union csr_crg_clk_div_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aclkm_div_sel : 2; /* [1:0] */ + u32 aclks_div_sel : 2; /* [3:2] */ + u32 aclkmp_div_sel : 2; /* [5:4] */ + u32 periphclk_div_sel : 4; /* [9:6] */ + u32 pclk_div_sel : 4; /* [13:10] */ + u32 atclk_div_sel : 4; /* [17:14] */ + u32 rsv_41 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_clk_div_sel_u; + +/* Define the union csr_crg_clkoff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clkoff_coreclk : 1; /* [0] */ + u32 clkoff_periphclk : 1; /* [1] */ + u32 clkoff_sclk : 1; /* [2] */ + u32 clkoff_atclk : 1; /* [3] */ + u32 clkoff_pclk : 1; /* [4] */ + u32 clkoff_aclkmp : 1; /* [5] */ + u32 clkoff_aclks : 1; /* [6] */ + u32 clkoff_alckm : 1; /* [7] */ + u32 clkoff_swclktck : 1; /* [8] */ + u32 clkoff_hpm : 1; /* [9] */ + u32 rsv_42 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_clkoff_u; + +/* Define the union csr_crg_srst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_napbreset : 1; /* [0] */ + u32 srst_req_ncpucorereset : 1; /* [1] */ + u32 srst_req_ncorereset : 1; /* [2] */ + u32 srst_req_npreset : 1; /* [3] */ + u32 srst_req_nsporeset : 1; /* [4] */ + u32 srst_req_nsreset : 1; /* [5] */ + u32 srst_req_natreset : 1; /* [6] */ + u32 srst_req_ngicreset : 1; /* [7] */ + u32 srst_req_nperiphreset : 1; /* [8] */ + u32 srst_req_ndapreset : 1; /* [9] */ + u32 srst_req_nmstreset : 1; /* [10] */ + u32 srst_req_nppreset : 1; /* [11] */ + u32 srst_req_ndbgppreset : 1; /* [12] */ + u32 rsv_43 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_srst_u; + +/* Define the union csr_spi_ssp_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spi_ssp_sel : 1; /* [0] */ + u32 rsv_44 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spi_ssp_sel_u; + +/* Define the union csr_a55_core_pchl_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corepactive : 18; /* [17:0] */ + u32 rsv_45 : 2; /* [19:18] */ + u32 corepaccept : 1; /* [20] */ + u32 corepdeny : 1; /* [21] */ + u32 rsv_46 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_core_pchl_stat_u; + +/* Define the union csr_a55_core_pchl_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corepstate : 6; /* [5:0] */ + u32 rsv_47 : 2; /* [7:6] */ + u32 corepreq : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_core_pchl_req_u; + +/* Define the union csr_a55_cluster_pchl_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clusterpactive : 20; /* [19:0] */ + u32 clusterpaccept : 1; /* [20] */ + u32 clusterpdeny : 1; /* [21] */ + u32 rsv_49 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_cluster_pchl_stat_u; + +/* Define the union csr_a55_cluster_pchl_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clusterpstate : 7; /* [6:0] */ + u32 rsv_50 : 1; /* [7] */ + u32 clusterpreq : 1; /* [8] */ + u32 rsv_51 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_cluster_pchl_req_u; + +/* Define the union csr_sc_mpu_map_addr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr0 : 12; /* [11:0] */ + u32 rsv_52 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr0_u; + +/* Define the union csr_sc_mpu_map_addr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr1 : 12; /* [11:0] */ + u32 rsv_53 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr1_u; + +/* Define the union csr_sc_mpu_map_addr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr2 : 12; /* [11:0] */ + u32 rsv_54 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr2_u; + +/* Define the union csr_sc_mpu_map_addr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr3 : 12; /* [11:0] */ + u32 rsv_55 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr3_u; + +/* Define the union csr_sc_mpu_map_addr4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr4 : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr4_u; + +/* Define the union csr_sc_mpu_map_addr5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr5 : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr5_u; + +/* Define the union csr_sc_mpu_map_addr6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr6 : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr6_u; + +/* Define the union csr_sc_mpu_map_addr7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr7 : 12; /* [11:0] */ + u32 rsv_59 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr7_u; + +/* Define the union csr_sc_mpu_map_addr8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr8 : 12; /* [11:0] */ + u32 rsv_60 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr8_u; + +/* Define the union csr_sc_mpu_map_addr9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr9 : 12; /* [11:0] */ + u32 rsv_61 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr9_u; + +/* Define the union csr_sc_mpu_map_addr10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr10 : 12; /* [11:0] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr10_u; + +/* Define the union csr_sc_mpu_map_addr11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr11 : 12; /* [11:0] */ + u32 rsv_63 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr11_u; + +/* Define the union csr_sc_mpu_map_addr12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr12 : 12; /* [11:0] */ + u32 rsv_64 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr12_u; + +/* Define the union csr_sc_mpu_map_addr13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr13 : 12; /* [11:0] */ + u32 rsv_65 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr13_u; + +/* Define the union csr_sc_mpu_map_addr14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr14 : 12; /* [11:0] */ + u32 rsv_66 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr14_u; + +/* Define the union csr_sc_mpu_map_addr15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_map_addr15 : 12; /* [11:0] */ + u32 rsv_67 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_map_addr15_u; + +/* Define the union csr_sc_spu_axuser_no_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 awuser_no_spu : 1; /* [0] */ + u32 aruser_no_spu : 1; /* [1] */ + u32 rsv_68 : 6; /* [7:2] */ + u32 awuser_no_sel_spu : 1; /* [8] */ + u32 aruser_no_sel_spu : 1; /* [9] */ + u32 rsv_69 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_spu_axuser_no_ctrl_u; + +/* Define the union csr_sc_mpu_axuser_31_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_axuser_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_axuser_31_0_u; + +/* Define the union csr_sc_mpu_axuser_63_32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_axuser_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_axuser_63_32_u; + +/* Define the union csr_sc_mpu_axuser_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_axuser_67_64 : 4; /* [3:0] */ + u32 mpu_axqos : 4; /* [7:4] */ + u32 mpu_wuser : 4; /* [11:8] */ + u32 rsv_70 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_axuser_u; + +/* Define the union csr_sc_mpu_axuser_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_axuser_38 : 1; /* [0] */ + u32 rsv_71 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_axuser_ns_u; + +/* Define the union csr_sc_mpu_axuser_ns_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_axuser_ns_mux : 1; /* [0] */ + u32 a55_axprot_ctrl : 1; /* [1] */ + u32 rsv_72 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_axuser_ns_ctrl_u; + +/* Define the union csr_sc_mpu_lpbx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spu_exception_req : 1; /* [0] */ + u32 spu_lpbx_mode : 1; /* [1] */ + u32 spu_exception_ack : 1; /* [2] */ + u32 spu_exception_active : 1; /* [3] */ + u32 spu_ruser_src_sel : 1; /* [4] */ + u32 rsv_73 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_lpbx_ctrl_u; + +/* Define the union csr_a55_to_r52_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_to_r52_int_status : 4; /* [3:0] */ + u32 rsv_74 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_to_r52_int_status_u; + +/* Define the union csr_a55_to_r52_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_to_r52_int_en : 4; /* [3:0] */ + u32 rsv_75 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_to_r52_int_en_u; + +/* Define the union csr_a55_to_r52_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 a55_to_r52_int_set : 4; /* [3:0] */ + u32 rsv_76 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_to_r52_int_set_u; + +/* Define the union csr_r52_to_a55_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 r52_to_a55_int_status : 4; /* [3:0] */ + u32 rsv_77 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_r52_to_a55_int_status_u; + +/* Define the union csr_r52_to_a55_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 r52_to_a55_int_en : 4; /* [3:0] */ + u32 rsv_78 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_r52_to_a55_int_en_u; + +/* Define the union csr_r52_to_a55_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 r52_to_a55_int_set : 4; /* [3:0] */ + u32 rsv_79 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_r52_to_a55_int_set_u; + +/* Define the union csr_a55_r52_int_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_uart_int_en : 1; /* [0] */ + u32 mpu_uart_int_en : 1; /* [1] */ + u32 hiss_djtagm_int_en : 1; /* [2] */ + u32 mpu_djtagm_int_en : 1; /* [3] */ + u32 rsv_80 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_a55_r52_int_sel_u; + +/* Define the union csr_cpi_mpu_lpbx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_exception_req : 1; /* [0] */ + u32 cpi_lpbx_mode : 1; /* [1] */ + u32 cpi_exception_ack : 1; /* [2] */ + u32 cpi_exception_active : 1; /* [3] */ + u32 rsv_81 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_mpu_lpbx_ctrl_u; + +/* Define the union csr_ring2axi_mpu_lpbx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring2axi_exception_req : 1; /* [0] */ + u32 ring2axi_lpbx_mode : 1; /* [1] */ + u32 ring2axi_exception_ack : 1; /* [2] */ + u32 ring2axi_exception_active : 1; /* [3] */ + u32 rsv_82 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring2axi_mpu_lpbx_ctrl_u; + +/* Define the union csr_crg_wdg_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_en : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_wdg_ctrl_u; + +/* Define the union csr_crg_wdg_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_cnt_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_wdg_cnt_config_u; + +/* Define the union csr_crg_wdg_feed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_feed : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_wdg_feed_u; + +/* Define the union csr_wdg_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_int_status : 1; /* [0] */ + u32 rsv_84 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wdg_int_status_u; + +/* Define the union csr_wdg_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_int_en : 1; /* [0] */ + u32 rsv_85 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wdg_int_en_u; + +/* Define the union csr_wdg_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_int_set : 1; /* [0] */ + u32 rsv_86 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wdg_int_set_u; + +/* Define the union csr_wdg_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wdg_int_raw_status : 1; /* [0] */ + u32 rsv_87 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_wdg_int_raw_status_u; + +/* Define the union csr_hiss_unc_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_rom_mecc_int_status : 1; /* [0] */ + u32 hiss_r52_int_status : 1; /* [1] */ + u32 hiss_wdg_int_status : 1; /* [2] */ + u32 rsv_88 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hiss_unc_int_status_u; + +/* Define the union csr_hiss_unc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_rom_mecc_int_en : 1; /* [0] */ + u32 hiss_r52_int_en : 1; /* [1] */ + u32 hiss_wdg_int_en : 1; /* [2] */ + u32 hiss_rom_mecc_unc_en : 1; /* [3] */ + u32 hiss_r52_unc_en : 1; /* [4] */ + u32 hiss_wdg_unc_en : 1; /* [5] */ + u32 rsv_89 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hiss_unc_int_en_u; + +/* Define the union csr_hiss_unc_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_rom_mecc_int_set : 1; /* [0] */ + u32 hiss_r52_int_set : 1; /* [1] */ + u32 hiss_wdg_int_set : 1; /* [2] */ + u32 rsv_90 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hiss_unc_int_set_u; + +/* Define the union csr_hiss_unc_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_rom_mecc_int_raw_status : 1; /* [0] */ + u32 hiss_r52_int_raw_status : 1; /* [1] */ + u32 hiss_wdg_int_raw_status : 1; /* [2] */ + u32 rsv_91 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hiss_unc_int_raw_status_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_sc_up_tile_bitmap_en_u sc_up_tile_bitmap_en[14]; /* 800 */ + volatile csr_sc_tile_bitmap_stat_u sc_tile_bitmap_stat[14]; /* 838 */ + volatile csr_sc_tile_bitmap_set_u sc_tile_bitmap_set[14]; /* 870 */ + volatile csr_mcore_stat_u mcore_stat[14]; /* 8B8 */ + volatile csr_mcore_stat_set_u mcore_stat_set[14]; /* 8F0 */ + volatile csr_mpu_mcore_stat_set_u mpu_mcore_stat_set[14]; /* 928 */ + volatile csr_c2j_mbist_ctrl_u c2j_mbist_ctrl; /* 974 */ + volatile csr_c2j_mbist_datain_u c2j_mbist_datain; /* 978 */ + volatile csr_c2j_mbist_dataout_u c2j_mbist_dataout; /* 97C */ + volatile csr_a55_sub_int_status_u a55_sub_int_status; /* 980 */ + volatile csr_a55_sub_int_en_u a55_sub_int_en; /* 984 */ + volatile csr_a55_sub_int_set_u a55_sub_int_set; /* 988 */ + volatile csr_a55_sub_int_raw_status_u a55_sub_int_raw_status; /* 98C */ + volatile csr_r52_wfi_wfe_stat_u r52_wfi_wfe_stat; /* 990 */ + volatile csr_ncsi_func_mbist_clk_sel_u ncsi_func_mbist_clk_sel; /* 994 */ + volatile csr_wol_int_status_u wol_int_status; /* 9A0 */ + volatile csr_wol_int_en_u wol_int_en; /* 9A4 */ + volatile csr_wol_int_set_u wol_int_set; /* 9A8 */ + volatile csr_wol_int_raw_status_u wol_int_raw_status; /* 9AC */ + volatile csr_wol_ctl_u wol_ctl; /* 9B0 */ + volatile csr_lp_intset0_u lp_intset0; /* 9B4 */ + volatile csr_lp_intset1_u lp_intset1; /* 9B8 */ + volatile csr_lp_intset2_u lp_intset2; /* 9BC */ + volatile csr_lp_intset3_u lp_intset3; /* 9C0 */ + volatile csr_lp_ready_u lp_ready; /* 9C4 */ + volatile csr_perstn_int_status_u perstn_int_status; /* 9C8 */ + volatile csr_perstn_int_en_u perstn_int_en; /* 9CC */ + volatile csr_perstn_int_set_u perstn_int_set; /* 9D0 */ + volatile csr_perstn_int_raw_status_u perstn_int_raw_status; /* 9D4 */ + volatile csr_up_uncrt_en_u up_uncrt_en; /* 9D8 */ + volatile csr_axi_bresp_mon_u axi_bresp_mon; /* 9DC */ + volatile csr_axi_rresp_mon_u axi_rresp_mon; /* 9E0 */ + volatile csr_axi_resp_mask_u axi_resp_mask; /* 9E4 */ + volatile csr_perstn_status_u perstn_status; /* 9E8 */ + volatile csr_perstn_hiss_int_status_u perstn_hiss_int_status; /* 9EC */ + volatile csr_perstn_hiss_int_en_u perstn_hiss_int_en; /* 9F0 */ + volatile csr_axi4toaxi3_bypass_u axi4toaxi3_bypass; /* 9F4 */ + volatile csr_axi4toaxi3_status_u axi4toaxi3_status; /* 9F8 */ + volatile csr_smb_dw_apb_i2c_debug_u smb_dw_apb_i2c_debug; /* 9FC */ + volatile csr_a55_fcm_cluster_config0_u a55_fcm_cluster_config0; /* A04 */ + volatile csr_a55_fcm_cluster_config1_u a55_fcm_cluster_config1; /* A08 */ + volatile csr_a55_rvbaraddry_cfg_l_u a55_rvbaraddry_cfg_l; /* A0C */ + volatile csr_a55_rvbaraddry_cfg_h_u a55_rvbaraddry_cfg_h; /* A10 */ + volatile csr_a55_broadcast_cfg_u a55_broadcast_cfg; /* A14 */ + volatile csr_a55_debug_cfg_u a55_debug_cfg; /* A18 */ + volatile csr_a55_fcm_cluster_status_u a55_fcm_cluster_status; /* A1C */ + volatile csr_a55_pmu_status_u a55_pmu_status; /* A20 */ + volatile csr_dbg_block_status_u dbg_block_status; /* A24 */ + volatile csr_gic600_cfg_u gic600_cfg; /* A28 */ + volatile csr_gic600_status_u gic600_status; /* A2C */ + volatile csr_crg_clk_div_sel_u crg_clk_div_sel; /* A30 */ + volatile csr_crg_clkoff_u crg_clkoff; /* A34 */ + volatile csr_crg_srst_u crg_srst; /* A38 */ + volatile csr_spi_ssp_sel_u spi_ssp_sel; /* A3C */ + volatile csr_a55_core_pchl_stat_u a55_core_pchl_stat; /* A40 */ + volatile csr_a55_core_pchl_req_u a55_core_pchl_req; /* A44 */ + volatile csr_a55_cluster_pchl_stat_u a55_cluster_pchl_stat; /* A48 */ + volatile csr_a55_cluster_pchl_req_u a55_cluster_pchl_req; /* A4C */ + volatile csr_sc_mpu_map_addr0_u sc_mpu_map_addr0; /* B00 */ + volatile csr_sc_mpu_map_addr1_u sc_mpu_map_addr1; /* B04 */ + volatile csr_sc_mpu_map_addr2_u sc_mpu_map_addr2; /* B08 */ + volatile csr_sc_mpu_map_addr3_u sc_mpu_map_addr3; /* B0C */ + volatile csr_sc_mpu_map_addr4_u sc_mpu_map_addr4; /* B10 */ + volatile csr_sc_mpu_map_addr5_u sc_mpu_map_addr5; /* B14 */ + volatile csr_sc_mpu_map_addr6_u sc_mpu_map_addr6; /* B18 */ + volatile csr_sc_mpu_map_addr7_u sc_mpu_map_addr7; /* B1C */ + volatile csr_sc_mpu_map_addr8_u sc_mpu_map_addr8; /* B20 */ + volatile csr_sc_mpu_map_addr9_u sc_mpu_map_addr9; /* B24 */ + volatile csr_sc_mpu_map_addr10_u sc_mpu_map_addr10; /* B28 */ + volatile csr_sc_mpu_map_addr11_u sc_mpu_map_addr11; /* B2C */ + volatile csr_sc_mpu_map_addr12_u sc_mpu_map_addr12; /* B30 */ + volatile csr_sc_mpu_map_addr13_u sc_mpu_map_addr13; /* B34 */ + volatile csr_sc_mpu_map_addr14_u sc_mpu_map_addr14; /* B38 */ + volatile csr_sc_mpu_map_addr15_u sc_mpu_map_addr15; /* B3C */ + volatile csr_sc_spu_axuser_no_ctrl_u sc_spu_axuser_no_ctrl; /* B40 */ + volatile csr_sc_mpu_axuser_31_0_u sc_mpu_axuser_31_0; /* B44 */ + volatile csr_sc_mpu_axuser_63_32_u sc_mpu_axuser_63_32; /* B48 */ + volatile csr_sc_mpu_axuser_u sc_mpu_axuser; /* B4C */ + volatile csr_sc_mpu_axuser_ns_u sc_mpu_axuser_ns; /* B50 */ + volatile csr_sc_mpu_axuser_ns_ctrl_u sc_mpu_axuser_ns_ctrl; /* B54 */ + volatile csr_sc_mpu_lpbx_ctrl_u sc_mpu_lpbx_ctrl; /* B58 */ + volatile csr_a55_to_r52_int_status_u a55_to_r52_int_status; /* C00 */ + volatile csr_a55_to_r52_int_en_u a55_to_r52_int_en; /* C04 */ + volatile csr_a55_to_r52_int_set_u a55_to_r52_int_set; /* C08 */ + volatile csr_r52_to_a55_int_status_u r52_to_a55_int_status; /* C0C */ + volatile csr_r52_to_a55_int_en_u r52_to_a55_int_en; /* C10 */ + volatile csr_r52_to_a55_int_set_u r52_to_a55_int_set; /* C14 */ + volatile csr_a55_r52_int_sel_u a55_r52_int_sel; /* C18 */ + volatile csr_cpi_mpu_lpbx_ctrl_u cpi_mpu_lpbx_ctrl; /* C1C */ + volatile csr_ring2axi_mpu_lpbx_ctrl_u ring2axi_mpu_lpbx_ctrl; /* C20 */ + volatile csr_crg_wdg_ctrl_u crg_wdg_ctrl; /* C24 */ + volatile csr_crg_wdg_cnt_config_u crg_wdg_cnt_config; /* C28 */ + volatile csr_crg_wdg_feed_u crg_wdg_feed; /* C2C */ + volatile csr_wdg_int_status_u wdg_int_status; /* C30 */ + volatile csr_wdg_int_en_u wdg_int_en; /* C34 */ + volatile csr_wdg_int_set_u wdg_int_set; /* C38 */ + volatile csr_wdg_int_raw_status_u wdg_int_raw_status; /* C3C */ + volatile csr_hiss_unc_int_status_u hiss_unc_int_status; /* C40 */ + volatile csr_hiss_unc_int_en_u hiss_unc_int_en; /* C44 */ + volatile csr_hiss_unc_int_set_u hiss_unc_int_set; /* C48 */ + volatile csr_hiss_unc_int_raw_status_u hiss_unc_int_raw_status; /* C4C */ +} S_sysctrl_csr1_REGS_TYPE; + +/* Declare the struct pointor of the module sysctrl_csr1 */ +extern volatile S_sysctrl_csr1_REGS_TYPE *gopsysctrl_csr1AllReg; + +/* Declare the functions that set the member value */ +int iSetSC_UP_TILE_BITMAP_EN_sc_up_tile_bitmap_en(unsigned int usc_up_tile_bitmap_en); +int iSetSC_TILE_BITMAP_STAT_sc_tile_bitmap_stat(unsigned int usc_tile_bitmap_stat); +int iSetSC_TILE_BITMAP_SET_sc_tile_bitmap_set(unsigned int usc_tile_bitmap_set); +int iSetMCORE_STAT_mcore_stat(unsigned int umcore_stat); +int iSetMCORE_STAT_SET_mcore_stat_set(unsigned int umcore_stat_set); +int iSetMPU_MCORE_STAT_SET_mpu_mcore_stat_set(unsigned int umpu_mcore_stat_set); +int iSetC2J_MBIST_CTRL_mbist_written(unsigned int umbist_written); +int iSetC2J_MBIST_CTRL_mbist_enable(unsigned int umbist_enable); +int iSetC2J_MBIST_CTRL_mbist_resetn(unsigned int umbist_resetn); +int iSetC2J_MBIST_DATAIN_mbist_datain(unsigned int umbist_datain); +int iSetC2J_MBIST_DATAOUT_mbist_dataout(unsigned int umbist_dataout); +int iSetA55_SUB_INT_STATUS_gic600_fault_int_status(unsigned int ugic600_fault_int_status); +int iSetA55_SUB_INT_STATUS_gic600_err_int_status(unsigned int ugic600_err_int_status); +int iSetA55_SUB_INT_STATUS_gic600_pmu_int_status(unsigned int ugic600_pmu_int_status); +int iSetA55_SUB_INT_STATUS_nfaultirq_int_status(unsigned int unfaultirq_int_status); +int iSetA55_SUB_INT_STATUS_nerrirq_int_status(unsigned int unerrirq_int_status); +int iSetA55_SUB_INT_STATUS_ncommirq_int_status(unsigned int uncommirq_int_status); +int iSetA55_SUB_INT_STATUS_nclusterpmuirq_int_status(unsigned int unclusterpmuirq_int_status); +int iSetA55_SUB_INT_EN_gic600_fault_int_en(unsigned int ugic600_fault_int_en); +int iSetA55_SUB_INT_EN_gic600_err_int_en(unsigned int ugic600_err_int_en); +int iSetA55_SUB_INT_EN_gic600_pmu_int_en(unsigned int ugic600_pmu_int_en); +int iSetA55_SUB_INT_EN_nfaultirq_int_en(unsigned int unfaultirq_int_en); +int iSetA55_SUB_INT_EN_nerrirq_int_en(unsigned int unerrirq_int_en); +int iSetA55_SUB_INT_EN_ncommirq_int_en(unsigned int uncommirq_int_en); +int iSetA55_SUB_INT_EN_nclusterpmuirq_int_en(unsigned int unclusterpmuirq_int_en); +int iSetA55_SUB_INT_EN_gic600_fault_unc_en(unsigned int ugic600_fault_unc_en); +int iSetA55_SUB_INT_EN_gic600_err_unc_en(unsigned int ugic600_err_unc_en); +int iSetA55_SUB_INT_EN_nfaultirq_unc_en(unsigned int unfaultirq_unc_en); +int iSetA55_SUB_INT_EN_nerrirq_unc_en(unsigned int unerrirq_unc_en); +int iSetA55_SUB_INT_SET_gic600_fault_int_set(unsigned int ugic600_fault_int_set); +int iSetA55_SUB_INT_SET_gic600_err_int_set(unsigned int ugic600_err_int_set); +int iSetA55_SUB_INT_SET_gic600_pmu_int_set(unsigned int ugic600_pmu_int_set); +int iSetA55_SUB_INT_SET_nfaultirq_int_set(unsigned int unfaultirq_int_set); +int iSetA55_SUB_INT_SET_nerrirq_int_set(unsigned int unerrirq_int_set); +int iSetA55_SUB_INT_SET_ncommirq_int_set(unsigned int uncommirq_int_set); +int iSetA55_SUB_INT_SET_nclusterpmuirq_int_set(unsigned int unclusterpmuirq_int_set); +int iSetA55_SUB_INT_RAW_STATUS_gic600_fault_int_raw_status(unsigned int ugic600_fault_int_raw_status); +int iSetA55_SUB_INT_RAW_STATUS_gic600_err_int_raw_status(unsigned int ugic600_err_int_raw_status); +int iSetA55_SUB_INT_RAW_STATUS_gic600_pmu_int_raw_status(unsigned int ugic600_pmu_int_raw_status); +int iSetA55_SUB_INT_RAW_STATUS_nfaultirq_int_raw_status(unsigned int unfaultirq_int_raw_status); +int iSetA55_SUB_INT_RAW_STATUS_nerrirq_int_raw_status(unsigned int unerrirq_int_raw_status); +int iSetA55_SUB_INT_RAW_STATUS_ncommirq_int_raw_status(unsigned int uncommirq_int_raw_status); +int iSetA55_SUB_INT_RAW_STATUS_nclusterpmuirq_int_raw_status(unsigned int unclusterpmuirq_int_raw_status); +int iSetR52_WFI_WFE_STAT_hiss_wfi_wfe_stat(unsigned int uhiss_wfi_wfe_stat); +int iSetNCSI_FUNC_MBIST_CLK_SEL_func_mbist_clk_sel(unsigned int ufunc_mbist_clk_sel); +int iSetWOL_INT_STATUS_pcie_prt_wol_int_status(unsigned int upcie_prt_wol_int_status); +int iSetWOL_INT_STATUS_pcie_prt_lp_req_int_status(unsigned int upcie_prt_lp_req_int_status); +int iSetWOL_INT_EN_pcie_prt_wol_int_en(unsigned int upcie_prt_wol_int_en); +int iSetWOL_INT_EN_pcie_prt_lp_req_int_en(unsigned int upcie_prt_lp_req_int_en); +int iSetWOL_INT_SET_wol_int_set(unsigned int uwol_int_set); +int iSetWOL_INT_RAW_STATUS_pcie_prt_wol_int_raw_status(unsigned int upcie_prt_wol_int_raw_status); +int iSetWOL_INT_RAW_STATUS_pcie_prt_lp_req_int_raw_status(unsigned int upcie_prt_lp_req_int_raw_status); +int iSetWOL_CTL_pcie_prt_mag_en(unsigned int upcie_prt_mag_en); +int iSetWOL_CTL_pcie_prt_link_en(unsigned int upcie_prt_link_en); +int iSetWOL_CTL_pcie_prt_wol_en(unsigned int upcie_prt_wol_en); +int iSetLP_INTSET0_pcie_prt0_lp_req_int_set(unsigned int upcie_prt0_lp_req_int_set); +int iSetLP_INTSET1_pcie_prt1_lp_req_int_set(unsigned int upcie_prt1_lp_req_int_set); +int iSetLP_INTSET2_pcie_prt2_lp_req_int_set(unsigned int upcie_prt2_lp_req_int_set); +int iSetLP_INTSET3_pcie_prt3_lp_req_int_set(unsigned int upcie_prt3_lp_req_int_set); +int iSetLP_READY_lp_ready(unsigned int ulp_ready); +int iSetPERSTN_INT_STATUS_perstn_int_status(unsigned int uperstn_int_status); +int iSetPERSTN_INT_EN_perstn_int_en(unsigned int uperstn_int_en); +int iSetPERSTN_INT_SET_perstn_int_set(unsigned int uperstn_int_set); +int iSetPERSTN_INT_RAW_STATUS_perstn_int_raw_status(unsigned int uperstn_int_raw_status); +int iSetUP_UNCRT_EN_up_uncrt_en(unsigned int uup_uncrt_en); +int iSetAXI_BRESP_MON_axi_bresp_stats(unsigned int uaxi_bresp_stats); +int iSetAXI_BRESP_MON_axi_bresp_clr(unsigned int uaxi_bresp_clr); +int iSetAXI_RRESP_MON_axi_rresp_stats(unsigned int uaxi_rresp_stats); +int iSetAXI_RRESP_MON_axi_rresp_clr(unsigned int uaxi_rresp_clr); +int iSetAXI_RESP_MASK_axi_rsp_mask_en(unsigned int uaxi_rsp_mask_en); +int iSetAXI_RESP_MASK_hiss_axi_rsp_mask_en(unsigned int uhiss_axi_rsp_mask_en); +int iSetPERSTN_STATUS_perstn_status(unsigned int uperstn_status); +int iSetPERSTN_HISS_INT_STATUS_perstn_hiss_int_status(unsigned int uperstn_hiss_int_status); +int iSetPERSTN_HISS_INT_EN_perstn_hiss_int_en(unsigned int uperstn_hiss_int_en); +int iSetAXI4TOAXI3_BYPASS_sc_axi4toaxi3_byapss(unsigned int usc_axi4toaxi3_byapss); +int iSetAXI4TOAXI3_STATUS_sc_axi4toaxi3_fifo_empty(unsigned int usc_axi4toaxi3_fifo_empty); +int iSetAXI4TOAXI3_STATUS_sc_axi4toaxi3_fifo_full(unsigned int usc_axi4toaxi3_fifo_full); +int iSetAXI4TOAXI3_STATUS_sc_axi4toaxi3_aw_err(unsigned int usc_axi4toaxi3_aw_err); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_addr_10bit(unsigned int usmb_debug_addr_10bit); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_slaver_act(unsigned int usmb_debug_slaver_act); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_master_act(unsigned int usmb_debug_master_act); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_hs(unsigned int usmb_debug_hs); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_wr(unsigned int usmb_debug_wr); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_rd(unsigned int usmb_debug_rd); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_addr(unsigned int usmb_debug_addr); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_adata(unsigned int usmb_debug_adata); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_p_gen(unsigned int usmb_debug_p_gen); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_s_gen(unsigned int usmb_debug_s_gen); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_slv_cstate(unsigned int usmb_debug_slv_cstate); +int iSetSMB_DW_APB_I2C_DEBUG_smb_debug_mst_cstate(unsigned int usmb_debug_mst_cstate); +int iSetA55_FCM_CLUSTER_CONFIG0_a55_sc_sercure_debug_en(unsigned int ua55_sc_sercure_debug_en); +int iSetA55_FCM_CLUSTER_CONFIG0_a55_sc_stretch_l2ramclk_en(unsigned int ua55_sc_stretch_l2ramclk_en); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_aa64naa32(unsigned int ua55_aa64naa32); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_cfgend(unsigned int ua55_cfgend); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_cfgte(unsigned int ua55_cfgte); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_clusteridaff2(unsigned int ua55_clusteridaff2); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_clusteridaff3(unsigned int ua55_clusteridaff3); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_giccdisable(unsigned int ua55_giccdisable); +int iSetA55_FCM_CLUSTER_CONFIG1_a55_vinithi(unsigned int ua55_vinithi); +int iSetA55_FCM_CLUSTER_CONFIG1_nfiq(unsigned int unfiq); +int iSetA55_FCM_CLUSTER_CONFIG1_nirq(unsigned int unirq); +int iSetA55_RVBARADDRY_CFG_L_a55_rvbaraddry_l(unsigned int ua55_rvbaraddry_l); +int iSetA55_RVBARADDRY_CFG_H_a55_rvbaraddry_h(unsigned int ua55_rvbaraddry_h); +int iSetA55_BROADCAST_CFG_a55_broadcastcachemaint(unsigned int ua55_broadcastcachemaint); +int iSetA55_BROADCAST_CFG_a55_broadcastcachemaintpou(unsigned int ua55_broadcastcachemaintpou); +int iSetA55_BROADCAST_CFG_a55_broadcastpersist(unsigned int ua55_broadcastpersist); +int iSetA55_BROADCAST_CFG_a55_broadcastouter(unsigned int ua55_broadcastouter); +int iSetA55_DEBUG_CFG_a55_dbgen(unsigned int ua55_dbgen); +int iSetA55_DEBUG_CFG_a55_niden(unsigned int ua55_niden); +int iSetA55_DEBUG_CFG_a55_spiden(unsigned int ua55_spiden); +int iSetA55_DEBUG_CFG_a55_spniden(unsigned int ua55_spniden); +int iSetA55_DEBUG_CFG_a55_dbgconnected(unsigned int ua55_dbgconnected); +int iSetA55_FCM_CLUSTER_STATUS_a55_custom_wfi(unsigned int ua55_custom_wfi); +int iSetA55_FCM_CLUSTER_STATUS_a55_custom_wfe(unsigned int ua55_custom_wfe); +int iSetA55_FCM_CLUSTER_STATUS_a55_sc_pmccnt_q63bit(unsigned int ua55_sc_pmccnt_q63bit); +int iSetA55_FCM_CLUSTER_STATUS_a55_sc_gic_irq(unsigned int ua55_sc_gic_irq); +int iSetA55_FCM_CLUSTER_STATUS_a55_sc_gic_fiq(unsigned int ua55_sc_gic_fiq); +int iSetA55_FCM_CLUSTER_STATUS_a55_sc_dbg_ack(unsigned int ua55_sc_dbg_ack); +int iSetA55_FCM_CLUSTER_STATUS_reg_clusterpmccntr_63bit(unsigned int ureg_clusterpmccntr_63bit); +int iSetA55_PMU_STATUS_a55_coreinstrret(unsigned int ua55_coreinstrret); +int iSetA55_PMU_STATUS_a55_coreinstrrun(unsigned int ua55_coreinstrrun); +int iSetDBG_BLOCK_STATUS_dbg_block_dbgpwrupreq(unsigned int udbg_block_dbgpwrupreq); +int iSetDBG_BLOCK_STATUS_dbg_block_clusterdbgpwrupreq(unsigned int udbg_block_clusterdbgpwrupreq); +int iSetGIC600_CFG_gic600_sample_req_gic(unsigned int ugic600_sample_req_gic); +int iSetGIC600_CFG_gic600_gict_allow_ns(unsigned int ugic600_gict_allow_ns); +int iSetGIC600_CFG_gic600_gicp_allow_ns(unsigned int ugic600_gicp_allow_ns); +int iSetGIC600_CFG_gic600_cpu_active(unsigned int ugic600_cpu_active); +int iSetGIC600_STATUS_gic600_sample_ack_gic(unsigned int ugic600_sample_ack_gic); +int iSetCRG_CLK_DIV_SEL_aclkm_div_sel(unsigned int uaclkm_div_sel); +int iSetCRG_CLK_DIV_SEL_aclks_div_sel(unsigned int uaclks_div_sel); +int iSetCRG_CLK_DIV_SEL_aclkmp_div_sel(unsigned int uaclkmp_div_sel); +int iSetCRG_CLK_DIV_SEL_periphclk_div_sel(unsigned int uperiphclk_div_sel); +int iSetCRG_CLK_DIV_SEL_pclk_div_sel(unsigned int upclk_div_sel); +int iSetCRG_CLK_DIV_SEL_atclk_div_sel(unsigned int uatclk_div_sel); +int iSetCRG_CLKOFF_clkoff_coreclk(unsigned int uclkoff_coreclk); +int iSetCRG_CLKOFF_clkoff_periphclk(unsigned int uclkoff_periphclk); +int iSetCRG_CLKOFF_clkoff_sclk(unsigned int uclkoff_sclk); +int iSetCRG_CLKOFF_clkoff_atclk(unsigned int uclkoff_atclk); +int iSetCRG_CLKOFF_clkoff_pclk(unsigned int uclkoff_pclk); +int iSetCRG_CLKOFF_clkoff_aclkmp(unsigned int uclkoff_aclkmp); +int iSetCRG_CLKOFF_clkoff_aclks(unsigned int uclkoff_aclks); +int iSetCRG_CLKOFF_clkoff_alckm(unsigned int uclkoff_alckm); +int iSetCRG_CLKOFF_clkoff_swclktck(unsigned int uclkoff_swclktck); +int iSetCRG_CLKOFF_clkoff_hpm(unsigned int uclkoff_hpm); +int iSetCRG_SRST_srst_req_napbreset(unsigned int usrst_req_napbreset); +int iSetCRG_SRST_srst_req_ncpucorereset(unsigned int usrst_req_ncpucorereset); +int iSetCRG_SRST_srst_req_ncorereset(unsigned int usrst_req_ncorereset); +int iSetCRG_SRST_srst_req_npreset(unsigned int usrst_req_npreset); +int iSetCRG_SRST_srst_req_nsporeset(unsigned int usrst_req_nsporeset); +int iSetCRG_SRST_srst_req_nsreset(unsigned int usrst_req_nsreset); +int iSetCRG_SRST_srst_req_natreset(unsigned int usrst_req_natreset); +int iSetCRG_SRST_srst_req_ngicreset(unsigned int usrst_req_ngicreset); +int iSetCRG_SRST_srst_req_nperiphreset(unsigned int usrst_req_nperiphreset); +int iSetCRG_SRST_srst_req_ndapreset(unsigned int usrst_req_ndapreset); +int iSetCRG_SRST_srst_req_nmstreset(unsigned int usrst_req_nmstreset); +int iSetCRG_SRST_srst_req_nppreset(unsigned int usrst_req_nppreset); +int iSetCRG_SRST_srst_req_ndbgppreset(unsigned int usrst_req_ndbgppreset); +int iSetSPI_SSP_SEL_spi_ssp_sel(unsigned int uspi_ssp_sel); +int iSetA55_CORE_PCHL_STAT_corepactive(unsigned int ucorepactive); +int iSetA55_CORE_PCHL_STAT_corepaccept(unsigned int ucorepaccept); +int iSetA55_CORE_PCHL_STAT_corepdeny(unsigned int ucorepdeny); +int iSetA55_CORE_PCHL_REQ_corepstate(unsigned int ucorepstate); +int iSetA55_CORE_PCHL_REQ_corepreq(unsigned int ucorepreq); +int iSetA55_CLUSTER_PCHL_STAT_clusterpactive(unsigned int uclusterpactive); +int iSetA55_CLUSTER_PCHL_STAT_clusterpaccept(unsigned int uclusterpaccept); +int iSetA55_CLUSTER_PCHL_STAT_clusterpdeny(unsigned int uclusterpdeny); +int iSetA55_CLUSTER_PCHL_REQ_clusterpstate(unsigned int uclusterpstate); +int iSetA55_CLUSTER_PCHL_REQ_clusterpreq(unsigned int uclusterpreq); +int iSetSC_MPU_MAP_ADDR0_mpu_map_addr0(unsigned int umpu_map_addr0); +int iSetSC_MPU_MAP_ADDR1_mpu_map_addr1(unsigned int umpu_map_addr1); +int iSetSC_MPU_MAP_ADDR2_mpu_map_addr2(unsigned int umpu_map_addr2); +int iSetSC_MPU_MAP_ADDR3_mpu_map_addr3(unsigned int umpu_map_addr3); +int iSetSC_MPU_MAP_ADDR4_mpu_map_addr4(unsigned int umpu_map_addr4); +int iSetSC_MPU_MAP_ADDR5_mpu_map_addr5(unsigned int umpu_map_addr5); +int iSetSC_MPU_MAP_ADDR6_mpu_map_addr6(unsigned int umpu_map_addr6); +int iSetSC_MPU_MAP_ADDR7_mpu_map_addr7(unsigned int umpu_map_addr7); +int iSetSC_MPU_MAP_ADDR8_mpu_map_addr8(unsigned int umpu_map_addr8); +int iSetSC_MPU_MAP_ADDR9_mpu_map_addr9(unsigned int umpu_map_addr9); +int iSetSC_MPU_MAP_ADDR10_mpu_map_addr10(unsigned int umpu_map_addr10); +int iSetSC_MPU_MAP_ADDR11_mpu_map_addr11(unsigned int umpu_map_addr11); +int iSetSC_MPU_MAP_ADDR12_mpu_map_addr12(unsigned int umpu_map_addr12); +int iSetSC_MPU_MAP_ADDR13_mpu_map_addr13(unsigned int umpu_map_addr13); +int iSetSC_MPU_MAP_ADDR14_mpu_map_addr14(unsigned int umpu_map_addr14); +int iSetSC_MPU_MAP_ADDR15_mpu_map_addr15(unsigned int umpu_map_addr15); +int iSetSC_SPU_AXUSER_NO_CTRL_awuser_no_spu(unsigned int uawuser_no_spu); +int iSetSC_SPU_AXUSER_NO_CTRL_aruser_no_spu(unsigned int uaruser_no_spu); +int iSetSC_SPU_AXUSER_NO_CTRL_awuser_no_sel_spu(unsigned int uawuser_no_sel_spu); +int iSetSC_SPU_AXUSER_NO_CTRL_aruser_no_sel_spu(unsigned int uaruser_no_sel_spu); +int iSetSC_MPU_AXUSER_31_0_mpu_axuser_31_0(unsigned int umpu_axuser_31_0); +int iSetSC_MPU_AXUSER_63_32_mpu_axuser_63_32(unsigned int umpu_axuser_63_32); +int iSetSC_MPU_AXUSER_mpu_axuser_67_64(unsigned int umpu_axuser_67_64); +int iSetSC_MPU_AXUSER_mpu_axqos(unsigned int umpu_axqos); +int iSetSC_MPU_AXUSER_mpu_wuser(unsigned int umpu_wuser); +int iSetSC_MPU_AXUSER_NS_mpu_axuser_38(unsigned int umpu_axuser_38); +int iSetSC_MPU_AXUSER_NS_CTRL_mpu_axuser_ns_mux(unsigned int umpu_axuser_ns_mux); +int iSetSC_MPU_AXUSER_NS_CTRL_a55_axprot_ctrl(unsigned int ua55_axprot_ctrl); +int iSetSC_MPU_LPBX_CTRL_spu_exception_req(unsigned int uspu_exception_req); +int iSetSC_MPU_LPBX_CTRL_spu_lpbx_mode(unsigned int uspu_lpbx_mode); +int iSetSC_MPU_LPBX_CTRL_spu_exception_ack(unsigned int uspu_exception_ack); +int iSetSC_MPU_LPBX_CTRL_spu_exception_active(unsigned int uspu_exception_active); +int iSetSC_MPU_LPBX_CTRL_spu_ruser_src_sel(unsigned int uspu_ruser_src_sel); +int iSetA55_TO_R52_INT_STATUS_a55_to_r52_int_status(unsigned int ua55_to_r52_int_status); +int iSetA55_TO_R52_INT_EN_a55_to_r52_int_en(unsigned int ua55_to_r52_int_en); +int iSetA55_TO_R52_INT_SET_a55_to_r52_int_set(unsigned int ua55_to_r52_int_set); +int iSetR52_TO_A55_INT_STATUS_r52_to_a55_int_status(unsigned int ur52_to_a55_int_status); +int iSetR52_TO_A55_INT_EN_r52_to_a55_int_en(unsigned int ur52_to_a55_int_en); +int iSetR52_TO_A552_INT_SET_r52_to_a55_int_set(unsigned int ur52_to_a55_int_set); +int iSetA55_R52_INT_SEL_hiss_uart_int_en(unsigned int uhiss_uart_int_en); +int iSetA55_R52_INT_SEL_mpu_uart_int_en(unsigned int umpu_uart_int_en); +int iSetA55_R52_INT_SEL_hiss_djtagm_int_en(unsigned int uhiss_djtagm_int_en); +int iSetA55_R52_INT_SEL_mpu_djtagm_int_en(unsigned int umpu_djtagm_int_en); +int iSetCPI_MPU_LPBX_CTRL_cpi_exception_req(unsigned int ucpi_exception_req); +int iSetCPI_MPU_LPBX_CTRL_cpi_lpbx_mode(unsigned int ucpi_lpbx_mode); +int iSetCPI_MPU_LPBX_CTRL_cpi_exception_ack(unsigned int ucpi_exception_ack); +int iSetCPI_MPU_LPBX_CTRL_cpi_exception_active(unsigned int ucpi_exception_active); +int iSetRING2AXI_MPU_LPBX_CTRL_ring2axi_exception_req(unsigned int uring2axi_exception_req); +int iSetRING2AXI_MPU_LPBX_CTRL_ring2axi_lpbx_mode(unsigned int uring2axi_lpbx_mode); +int iSetRING2AXI_MPU_LPBX_CTRL_ring2axi_exception_ack(unsigned int uring2axi_exception_ack); +int iSetRING2AXI_MPU_LPBX_CTRL_ring2axi_exception_active(unsigned int uring2axi_exception_active); +int iSetCRG_WDG_CTRL_wdg_en(unsigned int uwdg_en); +int iSetCRG_WDG_CNT_CONFIG_wdg_cnt_cfg(unsigned int uwdg_cnt_cfg); +int iSetCRG_WDG_FEED_wdg_feed(unsigned int uwdg_feed); +int iSetWDG_INT_STATUS_wdg_int_status(unsigned int uwdg_int_status); +int iSetWDG_INT_EN_wdg_int_en(unsigned int uwdg_int_en); +int iSetWDG_INT_SET_wdg_int_set(unsigned int uwdg_int_set); +int iSetWDG_INT_RAW_STATUS_wdg_int_raw_status(unsigned int uwdg_int_raw_status); +int iSetHISS_UNC_INT_STATUS_hiss_rom_mecc_int_status(unsigned int uhiss_rom_mecc_int_status); +int iSetHISS_UNC_INT_STATUS_hiss_r52_int_status(unsigned int uhiss_r52_int_status); +int iSetHISS_UNC_INT_STATUS_hiss_wdg_int_status(unsigned int uhiss_wdg_int_status); +int iSetHISS_UNC_INT_EN_hiss_rom_mecc_int_en(unsigned int uhiss_rom_mecc_int_en); +int iSetHISS_UNC_INT_EN_hiss_r52_int_en(unsigned int uhiss_r52_int_en); +int iSetHISS_UNC_INT_EN_hiss_wdg_int_en(unsigned int uhiss_wdg_int_en); +int iSetHISS_UNC_INT_EN_hiss_rom_mecc_unc_en(unsigned int uhiss_rom_mecc_unc_en); +int iSetHISS_UNC_INT_EN_hiss_r52_unc_en(unsigned int uhiss_r52_unc_en); +int iSetHISS_UNC_INT_EN_hiss_wdg_unc_en(unsigned int uhiss_wdg_unc_en); +int iSetHISS_UNC_INT_SET_hiss_rom_mecc_int_set(unsigned int uhiss_rom_mecc_int_set); +int iSetHISS_UNC_INT_SET_hiss_r52_int_set(unsigned int uhiss_r52_int_set); +int iSetHISS_UNC_INT_SET_hiss_wdg_int_set(unsigned int uhiss_wdg_int_set); +int iSetHISS_UNC_INT_RAW_STATUS_hiss_rom_mecc_int_raw_status(unsigned int uhiss_rom_mecc_int_raw_status); +int iSetHISS_UNC_INT_RAW_STATUS_hiss_r52_int_raw_status(unsigned int uhiss_r52_int_raw_status); +int iSetHISS_UNC_INT_RAW_STATUS_hiss_wdg_int_raw_status(unsigned int uhiss_wdg_int_raw_status); + +/* Define the union csr_c2j_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 1; /* [0] */ + u32 jtag_ir_size : 5; /* [5:1] */ + u32 jtag_ir_tail : 1; /* [6] */ + u32 jtag_ir_tail_wr : 1; /* [7] */ + u32 rsv_1 : 1; /* [8] */ + u32 jtag_dr_size : 5; /* [13:9] */ + u32 jtag_dr_tail : 1; /* [14] */ + u32 jtag_dr_tail_wr : 1; /* [15] */ + u32 jtag_enable : 1; /* [16] */ + u32 rsv_2 : 3; /* [19:17] */ + u32 jtag_clk_factor : 4; /* [23:20] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_ctrl_u; + +/* Define the union csr_c2j_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ir_done : 1; /* [0] */ + u32 dr_done : 1; /* [1] */ + u32 shift_done_master : 1; /* [2] */ + u32 data_out_wr : 1; /* [3] */ + u32 rsv_4 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_status_u; + +/* Define the union csr_c2j_datain_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c2j_datain : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_datain_u; + +/* Define the union csr_c2j_dataout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 c2j_dataout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_dataout_u; + +/* Define the union csr_c2j_dr_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 jtag_dr_start : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_dr_start_u; + +/* Define the union csr_c2j_ir_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 jtag_ir_start : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_c2j_ir_start_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_c2j_ctrl_u c2j_ctrl; /* 0 */ + volatile csr_c2j_status_u c2j_status; /* 4 */ + volatile csr_c2j_datain_u c2j_datain; /* 8 */ + volatile csr_c2j_dataout_u c2j_dataout; /* C */ + volatile csr_c2j_dr_start_u c2j_dr_start; /* 10 */ + volatile csr_c2j_ir_start_u c2j_ir_start; /* 14 */ +} S_c2j_REGS_TYPE; + +/* Declare the struct pointor of the module c2j */ +extern volatile S_c2j_REGS_TYPE *gopc2jAllReg; + +/* Declare the functions that set the member value */ +int iSetC2J_CTRL_jtag_ir_size(unsigned int ujtag_ir_size); +int iSetC2J_CTRL_jtag_ir_tail(unsigned int ujtag_ir_tail); +int iSetC2J_CTRL_jtag_ir_tail_wr(unsigned int ujtag_ir_tail_wr); +int iSetC2J_CTRL_jtag_dr_size(unsigned int ujtag_dr_size); +int iSetC2J_CTRL_jtag_dr_tail(unsigned int ujtag_dr_tail); +int iSetC2J_CTRL_jtag_dr_tail_wr(unsigned int ujtag_dr_tail_wr); +int iSetC2J_CTRL_jtag_enable(unsigned int ujtag_enable); +int iSetC2J_CTRL_jtag_clk_factor(unsigned int ujtag_clk_factor); +int iSetC2J_STATUS_ir_done(unsigned int uir_done); +int iSetC2J_STATUS_dr_done(unsigned int udr_done); +int iSetC2J_STATUS_shift_done_master(unsigned int ushift_done_master); +int iSetC2J_STATUS_data_out_wr(unsigned int udata_out_wr); +int iSetC2J_DATAIN_c2j_datain(unsigned int uc2j_datain); +int iSetC2J_DATAOUT_c2j_dataout(unsigned int uc2j_dataout); +int iSetC2J_DR_START_jtag_dr_start(unsigned int ujtag_dr_start); +int iSetC2J_IR_START_jtag_ir_start(unsigned int ujtag_ir_start); + +/* Define the union csr_mdio_command_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mdio_devad : 5; /* [4:0] */ + u32 mdio_prtad : 5; /* [9:5] */ + u32 mdio_op : 2; /* [11:10] */ + u32 mdio_st : 2; /* [13:12] */ + u32 mdio_start : 1; /* [14] */ + u32 rsv_0 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mdio_command_reg_u; + +/* Define the union csr_mdio_addr_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mdio_address : 16; /* [15:0] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mdio_addr_reg_u; + +/* Define the union csr_mdio_wdata_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mdio_wdata : 16; /* [15:0] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mdio_wdata_reg_u; + +/* Define the union csr_mdio_rdata_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mdio_rdata : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mdio_rdata_reg_u; + +/* Define the union csr_mdio_sta_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mdio_sta : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mdio_sta_reg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mdio_command_reg_u mdio_command_reg; /* 0 */ + volatile csr_mdio_addr_reg_u mdio_addr_reg; /* 4 */ + volatile csr_mdio_wdata_reg_u mdio_wdata_reg; /* 8 */ + volatile csr_mdio_rdata_reg_u mdio_rdata_reg; /* C */ + volatile csr_mdio_sta_reg_u mdio_sta_reg; /* 10 */ +} S_mdio_0_REGS_TYPE; + +/* Declare the struct pointor of the module mdio_0 */ +extern volatile S_mdio_0_REGS_TYPE *gopmdio_0AllReg; + +/* Declare the functions that set the member value */ +int iSetMDIO_COMMAND_REG_mdio_devad(unsigned int umdio_devad); +int iSetMDIO_COMMAND_REG_mdio_prtad(unsigned int umdio_prtad); +int iSetMDIO_COMMAND_REG_mdio_op(unsigned int umdio_op); +int iSetMDIO_COMMAND_REG_mdio_st(unsigned int umdio_st); +int iSetMDIO_COMMAND_REG_mdio_start(unsigned int umdio_start); +int iSetMDIO_ADDR_REG_mdio_address(unsigned int umdio_address); +int iSetMDIO_WDATA_REG_mdio_wdata(unsigned int umdio_wdata); +int iSetMDIO_RDATA_REG_mdio_rdata(unsigned int umdio_rdata); +int iSetMDIO_STA_REG_mdio_sta(unsigned int umdio_sta); + +/* Define the union csr_i2c_con_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 master : 1; /* [0] */ + u32 speed : 2; /* [2:1] */ + u32 slave_10bit : 1; /* [3] */ + u32 master_10bit_rd_only : 1; /* [4] */ + u32 restart_en : 1; /* [5] */ + u32 slave_disable : 1; /* [6] */ + u32 rsv_0 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_con_u; + +/* Define the union csr_i2c_tar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_tar : 10; /* [9:0] */ + u32 gc_or_start : 1; /* [10] */ + u32 special : 1; /* [11] */ + u32 master_10bit : 1; /* [12] */ + u32 rsv_1 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_tar_u; + +/* Define the union csr_i2c_sar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_sar : 10; /* [9:0] */ + u32 rsv_2 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_sar_u; + +/* Define the union csr_i2c_hs_maddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_hs_mar : 3; /* [2:0] */ + u32 rsv_3 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_hs_maddr_u; + +/* Define the union csr_i2c_data_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat : 8; /* [7:0] */ + u32 cmd : 1; /* [8] */ + u32 rsv_4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_data_cmd_u; + +/* Define the union csr_i2c_ss_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ss_scl_hcnt : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_ss_scl_hcnt_u; + +/* Define the union csr_i2c_ss_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ss_scl_lcnt : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_ss_scl_lcnt_u; + +/* Define the union csr_i2c_fs_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fs_scl_hcnt : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_fs_scl_hcnt_u; + +/* Define the union csr_i2c_fs_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fs_scl_lcnt : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_fs_scl_lcnt_u; + +/* Define the union csr_i2c_hs_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hs_scl_hcnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_hs_scl_hcnt_u; + +/* Define the union csr_i2c_hs_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hs_scl_lcnt : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_hs_scl_lcnt_u; + +/* Define the union csr_i2c_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 r_rx_under : 1; /* [0] */ + u32 r_rx_over : 1; /* [1] */ + u32 r_rx_full : 1; /* [2] */ + u32 r_tx_over : 1; /* [3] */ + u32 r_tx_empty : 1; /* [4] */ + u32 r_rd_req : 1; /* [5] */ + u32 r_tx_abrt : 1; /* [6] */ + u32 r_rx_done : 1; /* [7] */ + u32 r_activity : 1; /* [8] */ + u32 r_stop_det : 1; /* [9] */ + u32 r_start_det : 1; /* [10] */ + u32 r_gen_call : 1; /* [11] */ + u32 rsv_11 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_intr_stat_u; + +/* Define the union csr_i2c_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 m_rx_under : 1; /* [0] */ + u32 m_rx_over : 1; /* [1] */ + u32 m_rx_full : 1; /* [2] */ + u32 m_tx_over : 1; /* [3] */ + u32 m_tx_empty : 1; /* [4] */ + u32 m_rd_req : 1; /* [5] */ + u32 m_tx_abrt : 1; /* [6] */ + u32 m_rx_done : 1; /* [7] */ + u32 m_activity : 1; /* [8] */ + u32 m_stop_det : 1; /* [9] */ + u32 m_start_det : 1; /* [10] */ + u32 m_gen_call : 1; /* [11] */ + u32 rsv_12 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_intr_mask_u; + +/* Define the union csr_i2c_raw_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_under : 1; /* [0] */ + u32 rx_over : 1; /* [1] */ + u32 rx_full : 1; /* [2] */ + u32 tx_over : 1; /* [3] */ + u32 tx_empty : 1; /* [4] */ + u32 rd_req : 1; /* [5] */ + u32 tx_abrt : 1; /* [6] */ + u32 rx_done : 1; /* [7] */ + u32 activity : 1; /* [8] */ + u32 stop_det : 1; /* [9] */ + u32 start_det : 1; /* [10] */ + u32 gen_call : 1; /* [11] */ + u32 rsv_13 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_raw_intr_stat_u; + +/* Define the union csr_i2c_rx_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tl : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_rx_tl_u; + +/* Define the union csr_i2c_tx_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tl : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_tx_tl_u; + +/* Define the union csr_i2c_clr_intr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_intr : 1; /* [0] */ + u32 rsv_16 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_intr_u; + +/* Define the union csr_i2c_clr_rx_under_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rx_under : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_rx_under_u; + +/* Define the union csr_i2c_clr_rx_over_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rx_over : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_rx_over_u; + +/* Define the union csr_i2c_clr_tx_over_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_tx_over : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_tx_over_u; + +/* Define the union csr_i2c_clr_rd_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rd_req : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_rd_req_u; + +/* Define the union csr_i2c_clr_tx_abrt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_tx_abrt : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_tx_abrt_u; + +/* Define the union csr_i2c_clr_rx_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rx_done : 1; /* [0] */ + u32 rsv_22 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_rx_done_u; + +/* Define the union csr_i2c_clr_activity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_activity : 1; /* [0] */ + u32 rsv_23 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_activity_u; + +/* Define the union csr_i2c_clr_stop_det_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_stop_det : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_stop_det_u; + +/* Define the union csr_i2c_clr_start_det_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_start_det : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_start_det_u; + +/* Define the union csr_i2c_clr_gen_call_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_gen_call : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_clr_gen_call_u; + +/* Define the union csr_i2c_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_27 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_enable_u; + +/* Define the union csr_i2c_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 activity : 1; /* [0] */ + u32 tfnf : 1; /* [1] */ + u32 tfe : 1; /* [2] */ + u32 rfne : 1; /* [3] */ + u32 rff : 1; /* [4] */ + u32 mst_activity : 1; /* [5] */ + u32 slv_activity : 1; /* [6] */ + u32 rsv_28 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_status_u; + +/* Define the union csr_i2c_txflr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txflr : 4; /* [3:0] */ + u32 rsv_29 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_txflr_u; + +/* Define the union csr_i2c_rxflr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxflr : 4; /* [3:0] */ + u32 rsv_30 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_rxflr_u; + +/* Define the union csr_i2c_sda_hold_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_sda_hold : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_sda_hold_u; + +/* Define the union csr_i2c_tx_abrt_source_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 abrt_7b_addr_noack : 1; /* [0] */ + u32 abrt_10addr1_noack : 1; /* [1] */ + u32 abrt_10addr2_noack : 1; /* [2] */ + u32 abrt_txdata_noack : 1; /* [3] */ + u32 abrt_gcall_noack : 1; /* [4] */ + u32 abrt_gcall_read : 1; /* [5] */ + u32 abrt_hs_ackdet : 1; /* [6] */ + u32 abrt_sbyte_ackdet : 1; /* [7] */ + u32 abrt_hs_norstrt : 1; /* [8] */ + u32 abrt_sbyte_norstrt : 1; /* [9] */ + u32 abrt_10b_rd_norstrt : 1; /* [10] */ + u32 arb_master_dis : 1; /* [11] */ + u32 arb_lost : 1; /* [12] */ + u32 abrt_slvflush_txfifo : 1; /* [13] */ + u32 abrt_slv_arblost : 1; /* [14] */ + u32 abrt_slvrd_intx : 1; /* [15] */ + u32 rsv_32 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_tx_abrt_source_u; + +/* Define the union csr_i2c_slv_data_nack_only_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nack : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_slv_data_nack_only_u; + +/* Define the union csr_i2c_dma_cr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdmae : 1; /* [0] */ + u32 tdmae : 1; /* [1] */ + u32 rsv_34 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_dma_cr_u; + +/* Define the union csr_i2c_dma_tdlr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_tdlr : 4; /* [3:0] */ + u32 rsv_35 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_dma_tdlr_u; + +/* Define the union csr_i2c_dma_rdlr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_rdlr : 4; /* [3:0] */ + u32 rsv_36 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_dma_rdlr_u; + +/* Define the union csr_i2c_sda_setup_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sda_setup : 8; /* [7:0] */ + u32 rsv_37 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_sda_setup_u; + +/* Define the union csr_i2c_ack_general_call_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_gen_call : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_ack_general_call_u; + +/* Define the union csr_i2c_enable_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_en : 1; /* [0] */ + u32 slv_rx_aborted : 1; /* [1] */ + u32 slv_rx_data_lost : 1; /* [2] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_enable_status_u; + +/* Define the union csr_i2c_comp_param_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_data_width : 2; /* [1:0] */ + u32 max_speed_mode : 2; /* [3:2] */ + u32 hc_count_values : 1; /* [4] */ + u32 intr_io : 1; /* [5] */ + u32 has_dma : 1; /* [6] */ + u32 add_encoded_params : 1; /* [7] */ + u32 rx_buffer_depth : 8; /* [15:8] */ + u32 tx_buffer_depth : 8; /* [23:16] */ + u32 rsv_40 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_comp_param_1_u; + +/* Define the union csr_i2c_comp_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_comp_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_comp_version_u; + +/* Define the union csr_i2c_comp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_comp_type : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_i2c_comp_type_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_i2c_con_u i2c_con; /* 0 */ + volatile csr_i2c_tar_u i2c_tar; /* 4 */ + volatile csr_i2c_sar_u i2c_sar; /* 8 */ + volatile csr_i2c_hs_maddr_u i2c_hs_maddr; /* C */ + volatile csr_i2c_data_cmd_u i2c_data_cmd; /* 10 */ + volatile csr_i2c_ss_scl_hcnt_u i2c_ss_scl_hcnt; /* 14 */ + volatile csr_i2c_ss_scl_lcnt_u i2c_ss_scl_lcnt; /* 18 */ + volatile csr_i2c_fs_scl_hcnt_u i2c_fs_scl_hcnt; /* 1C */ + volatile csr_i2c_fs_scl_lcnt_u i2c_fs_scl_lcnt; /* 20 */ + volatile csr_i2c_hs_scl_hcnt_u i2c_hs_scl_hcnt; /* 24 */ + volatile csr_i2c_hs_scl_lcnt_u i2c_hs_scl_lcnt; /* 28 */ + volatile csr_i2c_intr_stat_u i2c_intr_stat; /* 2C */ + volatile csr_i2c_intr_mask_u i2c_intr_mask; /* 30 */ + volatile csr_i2c_raw_intr_stat_u i2c_raw_intr_stat; /* 34 */ + volatile csr_i2c_rx_tl_u i2c_rx_tl; /* 38 */ + volatile csr_i2c_tx_tl_u i2c_tx_tl; /* 3C */ + volatile csr_i2c_clr_intr_u i2c_clr_intr; /* 40 */ + volatile csr_i2c_clr_rx_under_u i2c_clr_rx_under; /* 44 */ + volatile csr_i2c_clr_rx_over_u i2c_clr_rx_over; /* 48 */ + volatile csr_i2c_clr_tx_over_u i2c_clr_tx_over; /* 4C */ + volatile csr_i2c_clr_rd_req_u i2c_clr_rd_req; /* 50 */ + volatile csr_i2c_clr_tx_abrt_u i2c_clr_tx_abrt; /* 54 */ + volatile csr_i2c_clr_rx_done_u i2c_clr_rx_done; /* 58 */ + volatile csr_i2c_clr_activity_u i2c_clr_activity; /* 5C */ + volatile csr_i2c_clr_stop_det_u i2c_clr_stop_det; /* 60 */ + volatile csr_i2c_clr_start_det_u i2c_clr_start_det; /* 64 */ + volatile csr_i2c_clr_gen_call_u i2c_clr_gen_call; /* 68 */ + volatile csr_i2c_enable_u i2c_enable; /* 6C */ + volatile csr_i2c_status_u i2c_status; /* 70 */ + volatile csr_i2c_txflr_u i2c_txflr; /* 74 */ + volatile csr_i2c_rxflr_u i2c_rxflr; /* 78 */ + volatile csr_i2c_sda_hold_u i2c_sda_hold; /* 7C */ + volatile csr_i2c_tx_abrt_source_u i2c_tx_abrt_source; /* 80 */ + volatile csr_i2c_slv_data_nack_only_u i2c_slv_data_nack_only; /* 84 */ + volatile csr_i2c_dma_cr_u i2c_dma_cr; /* 88 */ + volatile csr_i2c_dma_tdlr_u i2c_dma_tdlr; /* 8C */ + volatile csr_i2c_dma_rdlr_u i2c_dma_rdlr; /* 90 */ + volatile csr_i2c_sda_setup_u i2c_sda_setup; /* 94 */ + volatile csr_i2c_ack_general_call_u i2c_ack_general_call; /* 98 */ + volatile csr_i2c_enable_status_u i2c_enable_status; /* 9C */ + volatile csr_i2c_comp_param_1_u i2c_comp_param_1; /* F4 */ + volatile csr_i2c_comp_version_u i2c_comp_version; /* F8 */ + volatile csr_i2c_comp_type_u i2c_comp_type; /* FC */ +} S_i2c_0_REGS_TYPE; + +/* Declare the struct pointor of the module i2c_0 */ +extern volatile S_i2c_0_REGS_TYPE *gopi2c_0AllReg; + +/* Declare the functions that set the member value */ +int iSetI2C_CON_master(unsigned int umaster); +int iSetI2C_CON_speed(unsigned int uspeed); +int iSetI2C_CON_slave_10bit(unsigned int uslave_10bit); +int iSetI2C_CON_master_10bit_rd_only(unsigned int umaster_10bit_rd_only); +int iSetI2C_CON_restart_en(unsigned int urestart_en); +int iSetI2C_CON_slave_disable(unsigned int uslave_disable); +int iSetI2C_TAR_ic_tar(unsigned int uic_tar); +int iSetI2C_TAR_gc_or_start(unsigned int ugc_or_start); +int iSetI2C_TAR_special(unsigned int uspecial); +int iSetI2C_TAR_master_10bit(unsigned int umaster_10bit); +int iSetI2C_SAR_i2c_sar(unsigned int ui2c_sar); +int iSetI2C_HS_MADDR_i2c_hs_mar(unsigned int ui2c_hs_mar); +int iSetI2C_DATA_CMD_dat(unsigned int udat); +int iSetI2C_DATA_CMD_cmd(unsigned int ucmd); +int iSetI2C_SS_SCL_HCNT_ss_scl_hcnt(unsigned int uss_scl_hcnt); +int iSetI2C_SS_SCL_LCNT_ss_scl_lcnt(unsigned int uss_scl_lcnt); +int iSetI2C_FS_SCL_HCNT_fs_scl_hcnt(unsigned int ufs_scl_hcnt); +int iSetI2C_FS_SCL_LCNT_fs_scl_lcnt(unsigned int ufs_scl_lcnt); +int iSetI2C_HS_SCL_HCNT_hs_scl_hcnt(unsigned int uhs_scl_hcnt); +int iSetI2C_HS_SCL_LCNT_hs_scl_lcnt(unsigned int uhs_scl_lcnt); +int iSetI2C_INTR_STAT_r_rx_under(unsigned int ur_rx_under); +int iSetI2C_INTR_STAT_r_rx_over(unsigned int ur_rx_over); +int iSetI2C_INTR_STAT_r_rx_full(unsigned int ur_rx_full); +int iSetI2C_INTR_STAT_r_tx_over(unsigned int ur_tx_over); +int iSetI2C_INTR_STAT_r_tx_empty(unsigned int ur_tx_empty); +int iSetI2C_INTR_STAT_r_rd_req(unsigned int ur_rd_req); +int iSetI2C_INTR_STAT_r_tx_abrt(unsigned int ur_tx_abrt); +int iSetI2C_INTR_STAT_r_rx_done(unsigned int ur_rx_done); +int iSetI2C_INTR_STAT_r_activity(unsigned int ur_activity); +int iSetI2C_INTR_STAT_r_stop_det(unsigned int ur_stop_det); +int iSetI2C_INTR_STAT_r_start_det(unsigned int ur_start_det); +int iSetI2C_INTR_STAT_r_gen_call(unsigned int ur_gen_call); +int iSetI2C_INTR_MASK_m_rx_under(unsigned int um_rx_under); +int iSetI2C_INTR_MASK_m_rx_over(unsigned int um_rx_over); +int iSetI2C_INTR_MASK_m_rx_full(unsigned int um_rx_full); +int iSetI2C_INTR_MASK_m_tx_over(unsigned int um_tx_over); +int iSetI2C_INTR_MASK_m_tx_empty(unsigned int um_tx_empty); +int iSetI2C_INTR_MASK_m_rd_req(unsigned int um_rd_req); +int iSetI2C_INTR_MASK_m_tx_abrt(unsigned int um_tx_abrt); +int iSetI2C_INTR_MASK_m_rx_done(unsigned int um_rx_done); +int iSetI2C_INTR_MASK_m_activity(unsigned int um_activity); +int iSetI2C_INTR_MASK_m_stop_det(unsigned int um_stop_det); +int iSetI2C_INTR_MASK_m_start_det(unsigned int um_start_det); +int iSetI2C_INTR_MASK_m_gen_call(unsigned int um_gen_call); +int iSetI2C_RAW_INTR_STAT_rx_under(unsigned int urx_under); +int iSetI2C_RAW_INTR_STAT_rx_over(unsigned int urx_over); +int iSetI2C_RAW_INTR_STAT_rx_full(unsigned int urx_full); +int iSetI2C_RAW_INTR_STAT_tx_over(unsigned int utx_over); +int iSetI2C_RAW_INTR_STAT_tx_empty(unsigned int utx_empty); +int iSetI2C_RAW_INTR_STAT_rd_req(unsigned int urd_req); +int iSetI2C_RAW_INTR_STAT_tx_abrt(unsigned int utx_abrt); +int iSetI2C_RAW_INTR_STAT_rx_done(unsigned int urx_done); +int iSetI2C_RAW_INTR_STAT_activity(unsigned int uactivity); +int iSetI2C_RAW_INTR_STAT_stop_det(unsigned int ustop_det); +int iSetI2C_RAW_INTR_STAT_start_det(unsigned int ustart_det); +int iSetI2C_RAW_INTR_STAT_gen_call(unsigned int ugen_call); +int iSetI2C_RX_TL_rx_tl(unsigned int urx_tl); +int iSetI2C_TX_TL_tx_tl(unsigned int utx_tl); +int iSetI2C_CLR_INTR_clr_intr(unsigned int uclr_intr); +int iSetI2C_CLR_RX_UNDER_clr_rx_under(unsigned int uclr_rx_under); +int iSetI2C_CLR_RX_OVER_clr_rx_over(unsigned int uclr_rx_over); +int iSetI2C_CLR_TX_OVER_clr_tx_over(unsigned int uclr_tx_over); +int iSetI2C_CLR_RD_REQ_clr_rd_req(unsigned int uclr_rd_req); +int iSetI2C_CLR_TX_ABRT_clr_tx_abrt(unsigned int uclr_tx_abrt); +int iSetI2C_CLR_RX_DONE_clr_rx_done(unsigned int uclr_rx_done); +int iSetI2C_CLR_ACTIVITY_clr_activity(unsigned int uclr_activity); +int iSetI2C_CLR_STOP_DET_clr_stop_det(unsigned int uclr_stop_det); +int iSetI2C_CLR_START_DET_clr_start_det(unsigned int uclr_start_det); +int iSetI2C_CLR_GEN_CALL_clr_gen_call(unsigned int uclr_gen_call); +int iSetI2C_ENABLE_enable(unsigned int uenable); +int iSetI2C_STATUS_activity(unsigned int uactivity); +int iSetI2C_STATUS_tfnf(unsigned int utfnf); +int iSetI2C_STATUS_tfe(unsigned int utfe); +int iSetI2C_STATUS_rfne(unsigned int urfne); +int iSetI2C_STATUS_rff(unsigned int urff); +int iSetI2C_STATUS_mst_activity(unsigned int umst_activity); +int iSetI2C_STATUS_slv_activity(unsigned int uslv_activity); +int iSetI2C_TXFLR_txflr(unsigned int utxflr); +int iSetI2C_RXFLR_rxflr(unsigned int urxflr); +int iSetI2C_SDA_HOLD_ic_sda_hold(unsigned int uic_sda_hold); +int iSetI2C_TX_ABRT_SOURCE_abrt_7b_addr_noack(unsigned int uabrt_7b_addr_noack); +int iSetI2C_TX_ABRT_SOURCE_abrt_10addr1_noack(unsigned int uabrt_10addr1_noack); +int iSetI2C_TX_ABRT_SOURCE_abrt_10addr2_noack(unsigned int uabrt_10addr2_noack); +int iSetI2C_TX_ABRT_SOURCE_abrt_txdata_noack(unsigned int uabrt_txdata_noack); +int iSetI2C_TX_ABRT_SOURCE_abrt_gcall_noack(unsigned int uabrt_gcall_noack); +int iSetI2C_TX_ABRT_SOURCE_abrt_gcall_read(unsigned int uabrt_gcall_read); +int iSetI2C_TX_ABRT_SOURCE_abrt_hs_ackdet(unsigned int uabrt_hs_ackdet); +int iSetI2C_TX_ABRT_SOURCE_abrt_sbyte_ackdet(unsigned int uabrt_sbyte_ackdet); +int iSetI2C_TX_ABRT_SOURCE_abrt_hs_norstrt(unsigned int uabrt_hs_norstrt); +int iSetI2C_TX_ABRT_SOURCE_abrt_sbyte_norstrt(unsigned int uabrt_sbyte_norstrt); +int iSetI2C_TX_ABRT_SOURCE_abrt_10b_rd_norstrt(unsigned int uabrt_10b_rd_norstrt); +int iSetI2C_TX_ABRT_SOURCE_arb_master_dis(unsigned int uarb_master_dis); +int iSetI2C_TX_ABRT_SOURCE_arb_lost(unsigned int uarb_lost); +int iSetI2C_TX_ABRT_SOURCE_abrt_slvflush_txfifo(unsigned int uabrt_slvflush_txfifo); +int iSetI2C_TX_ABRT_SOURCE_abrt_slv_arblost(unsigned int uabrt_slv_arblost); +int iSetI2C_TX_ABRT_SOURCE_abrt_slvrd_intx(unsigned int uabrt_slvrd_intx); +int iSetI2C_SLV_DATA_NACK_ONLY_nack(unsigned int unack); +int iSetI2C_DMA_CR_rdmae(unsigned int urdmae); +int iSetI2C_DMA_CR_tdmae(unsigned int utdmae); +int iSetI2C_DMA_TDLR_dma_tdlr(unsigned int udma_tdlr); +int iSetI2C_DMA_RDLR_dma_rdlr(unsigned int udma_rdlr); +int iSetI2C_SDA_SETUP_sda_setup(unsigned int usda_setup); +int iSetI2C_ACK_GENERAL_CALL_ack_gen_call(unsigned int uack_gen_call); +int iSetI2C_ENABLE_STATUS_ic_en(unsigned int uic_en); +int iSetI2C_ENABLE_STATUS_slv_rx_aborted(unsigned int uslv_rx_aborted); +int iSetI2C_ENABLE_STATUS_slv_rx_data_lost(unsigned int uslv_rx_data_lost); +int iSetI2C_COMP_PARAM_1_apb_data_width(unsigned int uapb_data_width); +int iSetI2C_COMP_PARAM_1_max_speed_mode(unsigned int umax_speed_mode); +int iSetI2C_COMP_PARAM_1_hc_count_values(unsigned int uhc_count_values); +int iSetI2C_COMP_PARAM_1_intr_io(unsigned int uintr_io); +int iSetI2C_COMP_PARAM_1_has_dma(unsigned int uhas_dma); +int iSetI2C_COMP_PARAM_1_add_encoded_params(unsigned int uadd_encoded_params); +int iSetI2C_COMP_PARAM_1_rx_buffer_depth(unsigned int urx_buffer_depth); +int iSetI2C_COMP_PARAM_1_tx_buffer_depth(unsigned int utx_buffer_depth); +int iSetI2C_COMP_VERSION_i2c_comp_version(unsigned int ui2c_comp_version); +int iSetI2C_COMP_TYPE_i2c_comp_type(unsigned int ui2c_comp_type); + +/* Define the union csr_cntcr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 en : 1; /* [0] */ + u32 hdbg : 1; /* [1] */ + u32 rsv_0 : 6; /* [7:2] */ + u32 fcrfeq : 3; /* [10:8] */ + u32 rsv_1 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntcr_u; + +/* Define the union csr_cntsr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 1; /* [0] */ + u32 dbgh : 1; /* [1] */ + u32 rsv_3 : 6; /* [7:2] */ + u32 fcack : 3; /* [10:8] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntsr_u; + +/* Define the union csr_cntcvl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 countvalue_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntcvl_u; + +/* Define the union csr_cntcvh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 countvalue_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntcvh_u; + +/* Define the union csr_cntfid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cntfid0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntfid0_u; + +/* Define the union csr_cntfid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cntfid1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntfid1_u; + +/* Define the union csr_cntfid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cntfid2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntfid2_u; + +/* Define the union csr_cntcvl_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 countvalue_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntcvl_ns_u; + +/* Define the union csr_cntcvh_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 countvalue_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cntcvh_ns_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cntcr_u cntcr; /* 0 */ + volatile csr_cntsr_u cntsr; /* 4 */ + volatile csr_cntcvl_u cntcvl; /* 8 */ + volatile csr_cntcvh_u cntcvh; /* C */ + volatile csr_cntfid0_u cntfid0; /* 20 */ + volatile csr_cntfid1_u cntfid1; /* 24 */ + volatile csr_cntfid2_u cntfid2; /* 28 */ + volatile csr_cntcvl_ns_u cntcvl_ns; /* 1008 */ + volatile csr_cntcvh_ns_u cntcvh_ns; /* 100C */ +} S_counter_REGS_TYPE; + +/* Declare the struct pointor of the module counter */ +extern volatile S_counter_REGS_TYPE *gopcounterAllReg; + +/* Declare the functions that set the member value */ +int iSetCNTCR_en(unsigned int uen); +int iSetCNTCR_hdbg(unsigned int uhdbg); +int iSetCNTCR_fcrfeq(unsigned int ufcrfeq); +int iSetCNTSR_dbgh(unsigned int udbgh); +int iSetCNTSR_fcack(unsigned int ufcack); +int iSetCNTCVL_countvalue_low(unsigned int ucountvalue_low); +int iSetCNTCVH_countvalue_high(unsigned int ucountvalue_high); +int iSetCNTFID0_cntfid0(unsigned int ucntfid0); +int iSetCNTFID1_cntfid1(unsigned int ucntfid1); +int iSetCNTFID2_cntfid2(unsigned int ucntfid2); +int iSetCNTCVL_NS_countvalue_low(unsigned int ucountvalue_low); +int iSetCNTCVH_NS_countvalue_high(unsigned int ucountvalue_high); + +/* Define the union csr_timer0_load_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_load_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_load_l_u; + +/* Define the union csr_timer0_load_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_load_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_load_h_u; + +/* Define the union csr_timer0_value_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_value_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_value_l_u; + +/* Define the union csr_timer0_value_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_value_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_value_h_u; + +/* Define the union csr_timer0_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_oneshot : 1; /* [0] */ + u32 timer0_size : 1; /* [1] */ + u32 timer0_pre : 2; /* [3:2] */ + u32 rsv_0 : 1; /* [4] */ + u32 timer0_intenable : 1; /* [5] */ + u32 timer0_mode : 1; /* [6] */ + u32 timer0_en : 1; /* [7] */ + u32 rsv_1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_control_u; + +/* Define the union csr_timer0_intclr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_intclr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_intclr_u; + +/* Define the union csr_timer0_ris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_ris : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_ris_u; + +/* Define the union csr_timer0_mis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_mis : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_mis_u; + +/* Define the union csr_timer0_bgload_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_bgload_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_bgload_l_u; + +/* Define the union csr_timer0_bgload_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer0_bgload_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer0_bgload_h_u; + +/* Define the union csr_timer1_load_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_load_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_load_l_u; + +/* Define the union csr_timer1_load_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_load_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_load_h_u; + +/* Define the union csr_timer1_value_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_value_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_value_l_u; + +/* Define the union csr_timer1_value_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_value_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_value_h_u; + +/* Define the union csr_timer1_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_oneshot : 1; /* [0] */ + u32 timer1_size : 1; /* [1] */ + u32 timer1_pre : 2; /* [3:2] */ + u32 rsv_4 : 1; /* [4] */ + u32 timer1_intenable : 1; /* [5] */ + u32 timer1_mode : 1; /* [6] */ + u32 timer1_en : 1; /* [7] */ + u32 rsv_5 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_control_u; + +/* Define the union csr_timer1_intclr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_intclr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_intclr_u; + +/* Define the union csr_timer1_ris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_ris : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_ris_u; + +/* Define the union csr_timer1_mis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_mis : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_mis_u; + +/* Define the union csr_timer1_bgload_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_bgload_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_bgload_l_u; + +/* Define the union csr_timer1_bgload_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timer1_bgload_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timer1_bgload_h_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_timer0_load_l_u timer0_load_l; /* 0 */ + volatile csr_timer0_load_h_u timer0_load_h; /* 4 */ + volatile csr_timer0_value_l_u timer0_value_l; /* 8 */ + volatile csr_timer0_value_h_u timer0_value_h; /* C */ + volatile csr_timer0_control_u timer0_control; /* 10 */ + volatile csr_timer0_intclr_u timer0_intclr; /* 14 */ + volatile csr_timer0_ris_u timer0_ris; /* 18 */ + volatile csr_timer0_mis_u timer0_mis; /* 1C */ + volatile csr_timer0_bgload_l_u timer0_bgload_l; /* 20 */ + volatile csr_timer0_bgload_h_u timer0_bgload_h; /* 24 */ + volatile csr_timer1_load_l_u timer1_load_l; /* 40 */ + volatile csr_timer1_load_h_u timer1_load_h; /* 44 */ + volatile csr_timer1_value_l_u timer1_value_l; /* 48 */ + volatile csr_timer1_value_h_u timer1_value_h; /* 4C */ + volatile csr_timer1_control_u timer1_control; /* 50 */ + volatile csr_timer1_intclr_u timer1_intclr; /* 54 */ + volatile csr_timer1_ris_u timer1_ris; /* 58 */ + volatile csr_timer1_mis_u timer1_mis; /* 5C */ + volatile csr_timer1_bgload_l_u timer1_bgload_l; /* 60 */ + volatile csr_timer1_bgload_h_u timer1_bgload_h; /* 64 */ +} S_timer64_REGS_TYPE; + +/* Declare the struct pointor of the module timer64 */ +extern volatile S_timer64_REGS_TYPE *goptimer64AllReg; + +/* Declare the functions that set the member value */ +int iSetTIMER0_LOAD_L_timer0_load_l(unsigned int utimer0_load_l); +int iSetTIMER0_LOAD_H_timer0_load_h(unsigned int utimer0_load_h); +int iSetTIMER0_VALUE_L_timer0_value_l(unsigned int utimer0_value_l); +int iSetTIMER0_VALUE_H_timer0_value_h(unsigned int utimer0_value_h); +int iSetTIMER0_CONTROL_timer0_oneshot(unsigned int utimer0_oneshot); +int iSetTIMER0_CONTROL_timer0_size(unsigned int utimer0_size); +int iSetTIMER0_CONTROL_timer0_pre(unsigned int utimer0_pre); +int iSetTIMER0_CONTROL_timer0_intenable(unsigned int utimer0_intenable); +int iSetTIMER0_CONTROL_timer0_mode(unsigned int utimer0_mode); +int iSetTIMER0_CONTROL_timer0_en(unsigned int utimer0_en); +int iSetTIMER0_INTCLR_timer0_intclr(unsigned int utimer0_intclr); +int iSetTIMER0_RIS_timer0_ris(unsigned int utimer0_ris); +int iSetTIMER0_MIS_timer0_mis(unsigned int utimer0_mis); +int iSetTIMER0_BGLOAD_L_timer0_bgload_l(unsigned int utimer0_bgload_l); +int iSetTIMER0_BGLOAD_H_timer0_bgload_h(unsigned int utimer0_bgload_h); +int iSetTIMER1_LOAD_L_timer1_load_l(unsigned int utimer1_load_l); +int iSetTIMER1_LOAD_H_timer1_load_h(unsigned int utimer1_load_h); +int iSetTIMER1_VALUE_L_timer1_value_l(unsigned int utimer1_value_l); +int iSetTIMER1_VALUE_H_timer1_value_h(unsigned int utimer1_value_h); +int iSetTIMER1_CONTROL_timer1_oneshot(unsigned int utimer1_oneshot); +int iSetTIMER1_CONTROL_timer1_size(unsigned int utimer1_size); +int iSetTIMER1_CONTROL_timer1_pre(unsigned int utimer1_pre); +int iSetTIMER1_CONTROL_timer1_intenable(unsigned int utimer1_intenable); +int iSetTIMER1_CONTROL_timer1_mode(unsigned int utimer1_mode); +int iSetTIMER1_CONTROL_timer1_en(unsigned int utimer1_en); +int iSetTIMER1_INTCLR_timer1_intclr(unsigned int utimer1_intclr); +int iSetTIMER1_RIS_timer1_ris(unsigned int utimer1_ris); +int iSetTIMER1_MIS_timer1_mis(unsigned int utimer1_mis); +int iSetTIMER1_BGLOAD_L_timer1_bgload_l(unsigned int utimer1_bgload_l); +int iSetTIMER1_BGLOAD_H_timer1_bgload_h(unsigned int utimer1_bgload_h); + +/* Define the union csr_gpio_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_data_u; + +/* Define the union csr_gpio_direction_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_direction : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_direction_u; + +/* Define the union csr_gpio_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_ctl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_ctl_u; + +/* Define the union csr_gpio_inten_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_inten : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_inten_u; + +/* Define the union csr_gpio_intmask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_intmask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_intmask_u; + +/* Define the union csr_gpio_inttype_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_inttype_level : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_inttype_level_u; + +/* Define the union csr_gpio_int_polarity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_int_polarity : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_int_polarity_u; + +/* Define the union csr_gpio_intstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_intstatus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_intstatus_u; + +/* Define the union csr_gpio_rawintstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_rawintstatus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_rawintstatus_u; + +/* Define the union csr_gpio_debounce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_debounce : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_debounce_u; + +/* Define the union csr_gpio_porta_eoi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_porta_eoi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_porta_eoi_u; + +/* Define the union csr_gpio_ext_porta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_ext_porta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_ext_porta_u; + +/* Define the union csr_gpio_ls_sync_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_ls_sync : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_ls_sync_u; + +/* Define the union csr_gpio_id_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_id_code : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_id_code_u; + +/* Define the union csr_gpio_comp_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gpio_comp_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gpio_comp_ver_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_gpio_data_u gpio_data; /* 0 */ + volatile csr_gpio_direction_u gpio_direction; /* 4 */ + volatile csr_gpio_ctl_u gpio_ctl; /* 8 */ + volatile csr_gpio_inten_u gpio_inten; /* 30 */ + volatile csr_gpio_intmask_u gpio_intmask; /* 34 */ + volatile csr_gpio_inttype_level_u gpio_inttype_level; /* 38 */ + volatile csr_gpio_int_polarity_u gpio_int_polarity; /* 3C */ + volatile csr_gpio_intstatus_u gpio_intstatus; /* 40 */ + volatile csr_gpio_rawintstatus_u gpio_rawintstatus; /* 44 */ + volatile csr_gpio_debounce_u gpio_debounce; /* 48 */ + volatile csr_gpio_porta_eoi_u gpio_porta_eoi; /* 4C */ + volatile csr_gpio_ext_porta_u gpio_ext_porta; /* 50 */ + volatile csr_gpio_ls_sync_u gpio_ls_sync; /* 60 */ + volatile csr_gpio_id_code_u gpio_id_code; /* 64 */ + volatile csr_gpio_comp_ver_u gpio_comp_ver; /* 6C */ +} S_gpio_0_REGS_TYPE; + +/* Declare the struct pointor of the module gpio_0 */ +extern volatile S_gpio_0_REGS_TYPE *gopgpio_0AllReg; + +/* Declare the functions that set the member value */ +int iSetGPIO_DATA_gpio_data(unsigned int ugpio_data); +int iSetGPIO_DIRECTION_gpio_direction(unsigned int ugpio_direction); +int iSetGPIO_CTL_gpio_ctl(unsigned int ugpio_ctl); +int iSetGPIO_INTEN_gpio_inten(unsigned int ugpio_inten); +int iSetGPIO_INTMASK_gpio_intmask(unsigned int ugpio_intmask); +int iSetGPIO_INTTYPE_LEVEL_gpio_inttype_level(unsigned int ugpio_inttype_level); +int iSetGPIO_INT_POLARITY_gpio_int_polarity(unsigned int ugpio_int_polarity); +int iSetGPIO_INTSTATUS_gpio_intstatus(unsigned int ugpio_intstatus); +int iSetGPIO_RAWINTSTATUS_gpio_rawintstatus(unsigned int ugpio_rawintstatus); +int iSetGPIO_DEBOUNCE_gpio_debounce(unsigned int ugpio_debounce); +int iSetGPIO_PORTA_EOI_gpio_porta_eoi(unsigned int ugpio_porta_eoi); +int iSetGPIO_EXT_PORTA_gpio_ext_porta(unsigned int ugpio_ext_porta); +int iSetGPIO_LS_SYNC_gpio_ls_sync(unsigned int ugpio_ls_sync); +int iSetGPIO_ID_CODE_gpio_id_code(unsigned int ugpio_id_code); +int iSetGPIO_COMP_VER_gpio_comp_ver(unsigned int ugpio_comp_ver); + +/* Define the union csr_thr_rbr_dll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 thr : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_thr_rbr_dll_u; + +/* Define the union csr_ier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 erbfi : 1; /* [0] */ + u32 etbei : 1; /* [1] */ + u32 elsi : 1; /* [2] */ + u32 rsv_1 : 4; /* [6:3] */ + u32 ptime : 1; /* [7] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ier_u; + +/* Define the union csr_fcr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_en : 1; /* [0] */ + u32 rx_fifo_rst : 1; /* [1] */ + u32 tx_fifo_rst : 1; /* [2] */ + u32 dam_mode : 1; /* [3] */ + u32 tx_fifio_line : 2; /* [5:4] */ + u32 rx_fifio_line : 2; /* [7:6] */ + u32 rsv_3 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fcr_u; + +/* Define the union csr_lcr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dls : 2; /* [1:0] */ + u32 stop : 1; /* [2] */ + u32 check_en : 1; /* [3] */ + u32 parity_en : 1; /* [4] */ + u32 stick_parity : 1; /* [5] */ + u32 brk : 1; /* [6] */ + u32 dlab : 1; /* [7] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcr_u; + +/* Define the union csr_mcr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 datater_rdy : 1; /* [0] */ + u32 tx_req : 1; /* [1] */ + u32 rsv_5 : 2; /* [3:2] */ + u32 loop_back : 1; /* [4] */ + u32 auto_flowctl_en : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mcr_u; + +/* Define the union csr_lsr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_rdy : 1; /* [0] */ + u32 overflow_ind : 1; /* [1] */ + u32 parity_err : 1; /* [2] */ + u32 frame_err : 1; /* [3] */ + u32 break_ind : 1; /* [4] */ + u32 tx_buf_empty : 1; /* [5] */ + u32 tx_empty : 1; /* [6] */ + u32 rx_fifo_err : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lsr_u; + +/* Define the union csr_scr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 scr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_scr_u; + +/* Define the union csr_far_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_access_ctrl : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_far_u; + +/* Define the union csr_tfr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fifio_rd : 8; /* [7:0] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tfr_u; + +/* Define the union csr_rfw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fifo_wr : 8; /* [7:0] */ + u32 rx_fifo_parity_err : 1; /* [8] */ + u32 rx_fifo_frame_err : 1; /* [9] */ + u32 rsv_11 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rfw_u; + +/* Define the union csr_usr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 busy : 1; /* [0] */ + u32 tx_fifo_nofull : 1; /* [1] */ + u32 tx_fifo_empty : 1; /* [2] */ + u32 rx_fifo_noempty : 1; /* [3] */ + u32 rx_fifo_full : 1; /* [4] */ + u32 rsv_12 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_usr_u; + +/* Define the union csr_tfl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fifo_line : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tfl_u; + +/* Define the union csr_rfl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fifo_line : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rfl_u; + +/* Define the union csr_htx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_halt : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_htx_u; + +/* Define the union csr_dmasa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_soft_ans : 1; /* [0] */ + u32 rsv_16 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmasa_u; + +/* Define the union csr_cpr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_data_width : 2; /* [1:0] */ + u32 rsv_17 : 2; /* [3:2] */ + u32 afce_mode : 1; /* [4] */ + u32 thre_mode : 1; /* [5] */ + u32 sir_mode : 1; /* [6] */ + u32 sir_lp_mode : 1; /* [7] */ + u32 additional_feat : 1; /* [8] */ + u32 fifo_access : 1; /* [9] */ + u32 fifo_stat : 1; /* [10] */ + u32 shadow : 1; /* [11] */ + u32 uart_add_encode_params : 1; /* [12] */ + u32 dma_extra : 1; /* [13] */ + u32 rsv_18 : 2; /* [15:14] */ + u32 fifo_mode : 8; /* [23:16] */ + u32 rsv_19 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_u; + +/* Define the union csr_ucv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucv_u; + +/* Define the union csr_ctr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctr_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_thr_rbr_dll_u thr_rbr_dll; /* 0 */ + volatile csr_ier_u ier; /* 4 */ + volatile csr_fcr_u fcr; /* 8 */ + volatile csr_lcr_u lcr; /* C */ + volatile csr_mcr_u mcr; /* 10 */ + volatile csr_lsr_u lsr; /* 14 */ + volatile csr_scr_u scr; /* 1C */ + volatile csr_far_u far; /* 70 */ + volatile csr_tfr_u tfr; /* 74 */ + volatile csr_rfw_u rfw; /* 78 */ + volatile csr_usr_u usr; /* 7C */ + volatile csr_tfl_u tfl; /* 80 */ + volatile csr_rfl_u rfl; /* 84 */ + volatile csr_htx_u htx; /* A4 */ + volatile csr_dmasa_u dmasa; /* A8 */ + volatile csr_cpr_u cpr; /* F4 */ + volatile csr_ucv_u ucv; /* F8 */ + volatile csr_ctr_u ctr; /* FC */ +} S_uart_REGS_TYPE; + +/* Declare the struct pointor of the module uart */ +extern volatile S_uart_REGS_TYPE *gopuartAllReg; + +/* Declare the functions that set the member value */ +int iSetTHR_RBR_DLL_thr(unsigned int uthr); +int iSetIER_erbfi(unsigned int uerbfi); +int iSetIER_etbei(unsigned int uetbei); +int iSetIER_elsi(unsigned int uelsi); +int iSetIER_ptime(unsigned int uptime); +int iSetFCR_fifo_en(unsigned int ufifo_en); +int iSetFCR_rx_fifo_rst(unsigned int urx_fifo_rst); +int iSetFCR_tx_fifo_rst(unsigned int utx_fifo_rst); +int iSetFCR_dam_mode(unsigned int udam_mode); +int iSetFCR_tx_fifio_line(unsigned int utx_fifio_line); +int iSetFCR_rx_fifio_line(unsigned int urx_fifio_line); +int iSetLCR_dls(unsigned int udls); +int iSetLCR_stop(unsigned int ustop); +int iSetLCR_check_en(unsigned int ucheck_en); +int iSetLCR_parity_en(unsigned int uparity_en); +int iSetLCR_stick_parity(unsigned int ustick_parity); +int iSetLCR_break(unsigned int ubreak); +int iSetLCR_dlab(unsigned int udlab); +int iSetMCR_datater_rdy(unsigned int udatater_rdy); +int iSetMCR_tx_req(unsigned int utx_req); +int iSetMCR_loop_back(unsigned int uloop_back); +int iSetMCR_auto_flowctl_en(unsigned int uauto_flowctl_en); +int iSetLSR_data_rdy(unsigned int udata_rdy); +int iSetLSR_overflow_ind(unsigned int uoverflow_ind); +int iSetLSR_parity_err(unsigned int uparity_err); +int iSetLSR_frame_err(unsigned int uframe_err); +int iSetLSR_break_ind(unsigned int ubreak_ind); +int iSetLSR_tx_buf_empty(unsigned int utx_buf_empty); +int iSetLSR_tx_empty(unsigned int utx_empty); +int iSetLSR_rx_fifo_err(unsigned int urx_fifo_err); +int iSetSCR_scr(unsigned int uscr); +int iSetFAR_fifo_access_ctrl(unsigned int ufifo_access_ctrl); +int iSetTFR_tx_fifio_rd(unsigned int utx_fifio_rd); +int iSetRFW_rx_fifo_wr(unsigned int urx_fifo_wr); +int iSetRFW_rx_fifo_parity_err(unsigned int urx_fifo_parity_err); +int iSetRFW_rx_fifo_frame_err(unsigned int urx_fifo_frame_err); +int iSetUSR_busy(unsigned int ubusy); +int iSetUSR_tx_fifo_nofull(unsigned int utx_fifo_nofull); +int iSetUSR_tx_fifo_empty(unsigned int utx_fifo_empty); +int iSetUSR_rx_fifo_noempty(unsigned int urx_fifo_noempty); +int iSetUSR_rx_fifo_full(unsigned int urx_fifo_full); +int iSetTFL_tx_fifo_line(unsigned int utx_fifo_line); +int iSetRFL_rx_fifo_line(unsigned int urx_fifo_line); +int iSetHTX_tx_halt(unsigned int utx_halt); +int iSetDMASA_dma_soft_ans(unsigned int udma_soft_ans); +int iSetCPR_apb_data_width(unsigned int uapb_data_width); +int iSetCPR_afce_mode(unsigned int uafce_mode); +int iSetCPR_thre_mode(unsigned int uthre_mode); +int iSetCPR_sir_mode(unsigned int usir_mode); +int iSetCPR_sir_lp_mode(unsigned int usir_lp_mode); +int iSetCPR_additional_feat(unsigned int uadditional_feat); +int iSetCPR_fifo_access(unsigned int ufifo_access); +int iSetCPR_fifo_stat(unsigned int ufifo_stat); +int iSetCPR_shadow(unsigned int ushadow); +int iSetCPR_uart_add_encode_params(unsigned int uuart_add_encode_params); +int iSetCPR_dma_extra(unsigned int udma_extra); +int iSetCPR_fifo_mode(unsigned int ufifo_mode); +int iSetUCV_ucv(unsigned int uucv); +int iSetCTR_ctr(unsigned int uctr); + +/* Define the union csr_smb_i2c_con_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 master_enable : 1; /* [0] */ + u32 speed : 2; /* [2:1] */ + u32 slave_10bit : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 restart_en : 1; /* [5] */ + u32 slave_disable : 1; /* [6] */ + u32 rsv_1 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_con_u; + +/* Define the union csr_smb_i2c_tar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 8; /* [7:0] */ + u32 i2c_tar : 2; /* [9:8] */ + u32 gc_or_start : 1; /* [10] */ + u32 special : 1; /* [11] */ + u32 master_10bit : 1; /* [12] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_tar_u; + +/* Define the union csr_smb_i2c_sar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_sar : 10; /* [9:0] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_sar_u; + +/* Define the union csr_smb_i2c_data_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr_or_data : 8; /* [7:0] */ + u32 cmd : 1; /* [8] */ + u32 addr_en : 1; /* [9] */ + u32 stop_en : 1; /* [10] */ + u32 rsv_5 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_data_cmd_u; + +/* Define the union csr_smb_i2c_ss_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_ss_scl_hcnt : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_ss_scl_hcnt_u; + +/* Define the union csr_smb_i2c_ss_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_ss_scl_lcnt : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_ss_scl_lcnt_u; + +/* Define the union csr_smb_i2c_fs_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_fs_scl_hcnt : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_fs_scl_hcnt_u; + +/* Define the union csr_smb_i2c_fs_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_fs_scl_lcnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_fs_scl_lcnt_u; + +/* Define the union csr_smb_i2c_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_under_stat : 1; /* [0] */ + u32 rx_over_stat : 1; /* [1] */ + u32 rx_full_stat : 1; /* [2] */ + u32 tx_over_stat : 1; /* [3] */ + u32 tx_empty_stat : 1; /* [4] */ + u32 rd_req_stat : 1; /* [5] */ + u32 tx_abrt_stat : 1; /* [6] */ + u32 tx_done_stat : 1; /* [7] */ + u32 activity_stat : 1; /* [8] */ + u32 stop_det_stat : 1; /* [9] */ + u32 start_det_stat : 1; /* [10] */ + u32 gen_call_stat : 1; /* [11] */ + u32 alert_det_stat : 1; /* [12] */ + u32 slv_data_receive_stat : 1; /* [13] */ + u32 slv_addr_receive_stat : 1; /* [14] */ + u32 scl_low_tout_stat : 1; /* [15] */ + u32 scl_high_tout_stat : 1; /* [16] */ + u32 pmbus_cmd_finish_stat : 1; /* [17] */ + u32 pec_rd_err_stat : 1; /* [18] */ + u32 arp_cmd_err_stat : 1; /* [19] */ + u32 rsv_10 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_intr_stat_u; + +/* Define the union csr_smb_i2c_intr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_under_en : 1; /* [0] */ + u32 rx_over_en : 1; /* [1] */ + u32 rx_full_en : 1; /* [2] */ + u32 tx_over_en : 1; /* [3] */ + u32 tx_empty_en : 1; /* [4] */ + u32 rd_req_en : 1; /* [5] */ + u32 tx_abrt_en : 1; /* [6] */ + u32 tx_done_en : 1; /* [7] */ + u32 activity_en : 1; /* [8] */ + u32 stop_det_en : 1; /* [9] */ + u32 start_det_en : 1; /* [10] */ + u32 gen_call_en : 1; /* [11] */ + u32 alert_det_en : 1; /* [12] */ + u32 slv_data_receive_en : 1; /* [13] */ + u32 slv_addr_receive_en : 1; /* [14] */ + u32 scl_low_tout_en : 1; /* [15] */ + u32 scl_high_tout_en : 1; /* [16] */ + u32 pmbus_cmd_finish_en : 1; /* [17] */ + u32 pec_rd_err_en : 1; /* [18] */ + u32 arp_cmd_err_en : 1; /* [19] */ + u32 rsv_11 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_intr_en_u; + +/* Define the union csr_smb_i2c_intr_raw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_under : 1; /* [0] */ + u32 rx_over : 1; /* [1] */ + u32 rx_full : 1; /* [2] */ + u32 tx_over : 1; /* [3] */ + u32 tx_empty : 1; /* [4] */ + u32 rd_req : 1; /* [5] */ + u32 tx_abrt : 1; /* [6] */ + u32 tx_done : 1; /* [7] */ + u32 activity : 1; /* [8] */ + u32 stop_det : 1; /* [9] */ + u32 start_det : 1; /* [10] */ + u32 gen_call : 1; /* [11] */ + u32 alert_det : 1; /* [12] */ + u32 slv_data_receive : 1; /* [13] */ + u32 slv_addr_received : 1; /* [14] */ + u32 scl_low_tout : 1; /* [15] */ + u32 scl_high_tout : 1; /* [16] */ + u32 pmbus_cmd_finish : 1; /* [17] */ + u32 pec_rd_err : 1; /* [18] */ + u32 arp_cmd_err : 1; /* [19] */ + u32 rsv_12 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_intr_raw_u; + +/* Define the union csr_smb_i2c_rx_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tl : 6; /* [5:0] */ + u32 rsv_13 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_rx_tl_u; + +/* Define the union csr_smb_i2c_tx_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tl : 6; /* [5:0] */ + u32 rsv_14 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_tx_tl_u; + +/* Define the union csr_smb_i2c_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_enable_u; + +/* Define the union csr_smb_i2c_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_activity : 1; /* [0] */ + u32 tx_fifo_nfull : 1; /* [1] */ + u32 tx_fifo_empty : 1; /* [2] */ + u32 rx_fifo_nempty : 1; /* [3] */ + u32 rx_fifo_full : 1; /* [4] */ + u32 timeout_sda : 1; /* [5] */ + u32 timeout_scl : 1; /* [6] */ + u32 bus_busy : 1; /* [7] */ + u32 alert_status : 1; /* [8] */ + u32 sda_in : 1; /* [9] */ + u32 scl_in : 1; /* [10] */ + u32 rsv_16 : 1; /* [11] */ + u32 mst_activity : 1; /* [12] */ + u32 mst_cur_fsm : 5; /* [17:13] */ + u32 mst_timeout_fsm : 5; /* [22:18] */ + u32 slv_activity : 1; /* [23] */ + u32 slv_cur_fsm : 4; /* [27:24] */ + u32 slv_timeout_fsm : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_status_u; + +/* Define the union csr_smb_i2c_txflr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_flr : 7; /* [6:0] */ + u32 rsv_17 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_txflr_u; + +/* Define the union csr_smb_i2c_rxflr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_flr : 7; /* [6:0] */ + u32 rsv_18 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_rxflr_u; + +/* Define the union csr_smb_i2c_sda_hold_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sda_hold : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_sda_hold_u; + +/* Define the union csr_smb_i2c_tx_abrt_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 abrt_7b_addr_noack : 1; /* [0] */ + u32 abrt_10addr1_noack : 1; /* [1] */ + u32 abrt_10addr2_noack : 1; /* [2] */ + u32 abrt_txdata_noack : 1; /* [3] */ + u32 abrt_gcall_noack : 1; /* [4] */ + u32 abrt_gcall_read : 1; /* [5] */ + u32 abrt_hs_ackdet : 1; /* [6] */ + u32 abrt_sbyte_ackdet : 1; /* [7] */ + u32 abrt_hs_norstrt : 1; /* [8] */ + u32 abrt_sbyte_norstrt : 1; /* [9] */ + u32 abrt_10b_rd_norstrt : 1; /* [10] */ + u32 rsv_20 : 1; /* [11] */ + u32 arb_lost : 1; /* [12] */ + u32 abrt_slvflush_txfifo : 1; /* [13] */ + u32 abrt_slv_lft : 1; /* [14] */ + u32 abrt_slvrd_intx : 1; /* [15] */ + u32 abrt_slv_stop : 1; /* [16] */ + u32 abrt_slv_alert : 1; /* [17] */ + u32 abrt_slv_pec : 1; /* [18] */ + u32 abrt_nack_pec : 1; /* [19] */ + u32 abrt_mst_comb : 1; /* [20] */ + u32 abrt_mst_alert : 1; /* [21] */ + u32 rsv_21 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_tx_abrt_src_u; + +/* Define the union csr_smb_i2c_sda_setup_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sda_setup : 16; /* [15:0] */ + u32 rsv_22 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_sda_setup_u; + +/* Define the union csr_smb_i2c_ack_general_call_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_gen_call : 1; /* [0] */ + u32 rsv_23 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_ack_general_call_u; + +/* Define the union csr_smb_i2c_enable_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_en : 1; /* [0] */ + u32 slv_disable_while_busy : 1; /* [1] */ + u32 slv_rx_lost : 1; /* [2] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_enable_status_u; + +/* Define the union csr_smb_i2c_scl_switch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 scl_switch : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_scl_switch_u; + +/* Define the union csr_smb_i2c_scl_sim_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 scl_sim : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_scl_sim_u; + +/* Define the union csr_smb_i2c_lpif_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_lpif_state : 3; /* [2:0] */ + u32 rsv_27 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_lpif_state_u; + +/* Define the union csr_smb_i2c_lock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_lock : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_lock_u; + +/* Define the union csr_smb_i2c_sda_switch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sda_switch : 1; /* [0] */ + u32 rsv_28 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_sda_switch_u; + +/* Define the union csr_smb_i2c_sda_sim_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sda_sim : 1; /* [0] */ + u32 rsv_29 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_sda_sim_u; + +/* Define the union csr_smb_i2c_sar_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_sar_mask : 10; /* [9:0] */ + u32 rsv_30 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_sar_mask_u; + +/* Define the union csr_smb_i2c_pmbus_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_mode : 1; /* [0] */ + u32 alert_en : 1; /* [1] */ + u32 pec_en : 1; /* [2] */ + u32 arp_en : 1; /* [3] */ + u32 rsv_31 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_pmbus_ctrl_u; + +/* Define the union csr_smb_i2c_low_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_low_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_low_timeout_u; + +/* Define the union csr_smb_i2c_high_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_high_timeout : 15; /* [14:0] */ + u32 rsv_32 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_high_timeout_u; + +/* Define the union csr_smb_i2c_slv_alert_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alert_set : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_slv_alert_set_u; + +/* Define the union csr_smb_i2c_mst_alert_do_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alert_do : 1; /* [0] */ + u32 rsv_34 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_mst_alert_do_u; + +/* Define the union csr_smb_i2c_ack_resp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_resp : 1; /* [0] */ + u32 rsv_35 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_ack_resp_u; + +/* Define the union csr_smb_i2c_pec_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pec_receive : 8; /* [7:0] */ + u32 pec_valid : 1; /* [8] */ + u32 pec_check : 1; /* [9] */ + u32 pec_err_info : 8; /* [17:10] */ + u32 rsv_36 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_pec_info_u; + +/* Define the union csr_smb_i2c_addr_receive_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slv_addr_receive : 10; /* [9:0] */ + u32 rsv_37 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_addr_receive_u; + +/* Define the union csr_smb_i2c_manu_ack_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_manu_ack_cnt : 6; /* [5:0] */ + u32 rsv_38 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_manu_ack_cnt_u; + +/* Define the union csr_smb_i2c_grp_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 group_cmd_en : 1; /* [0] */ + u32 rsv_39 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_grp_cmd_u; + +/* Define the union csr_smb_i2c_pmbus_scl_det_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 scl_idle_det_en : 1; /* [0] */ + u32 scl_ltimeout_en : 1; /* [1] */ + u32 scl_htimeout_en : 1; /* [2] */ + u32 rsv_40 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_pmbus_scl_det_u; + +/* Define the union csr_smb_i2c_pmbus_idlecnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmbus_idle_cnt : 15; /* [14:0] */ + u32 rsv_41 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_pmbus_idlecnt_u; + +/* Define the union csr_smb_i2c_pmbus_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst : 1; /* [0] */ + u32 rsv_42 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_pmbus_rst_u; + +/* Define the union csr_smb_i2c_tx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_addr_or_data : 8; /* [7:0] */ + u32 i2c_cmd : 1; /* [8] */ + u32 i2c_addr_en : 1; /* [9] */ + u32 i2c_stop_en : 1; /* [10] */ + u32 rsv_43 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_tx_info_u; + +/* Define the union csr_smb_i2c_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_tx_cnt : 7; /* [6:0] */ + u32 rsv_44 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_tx_cnt_u; + +/* Define the union csr_smb_i2c_trigger_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i2c_trigger_en : 1; /* [0] */ + u32 rsv_45 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_i2c_trigger_en_u; + +/* Define the union csr_smb_udid_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_spec_id : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_udid_0_u; + +/* Define the union csr_smb_udid_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 subsys_device_id : 16; /* [15:0] */ + u32 subsys_vendor_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_udid_1_u; + +/* Define the union csr_smb_udid_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smbus_version : 4; /* [3:0] */ + u32 support_protocol : 12; /* [15:4] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_udid_2_u; + +/* Define the union csr_smb_udid_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 silicon_revision_id : 3; /* [18:16] */ + u32 udid_version : 3; /* [21:19] */ + u32 rsv_46 : 2; /* [23:22] */ + u32 arp_pec_en : 1; /* [24] */ + u32 rsv_47 : 5; /* [29:25] */ + u32 addr_type : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_udid_3_u; + +/* Define the union csr_smb_arp_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arp_addr : 7; /* [6:0] */ + u32 rsv_48 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_arp_addr_u; + +/* Define the union csr_smb_psa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smb_psa : 7; /* [6:0] */ + u32 rsv_49 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_psa_u; + +/* Define the union csr_smb_notify_do_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_do : 1; /* [0] */ + u32 rsv_50 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_notify_do_u; + +/* Define the union csr_smb_arp_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 av_flg : 1; /* [0] */ + u32 ar_flg : 1; /* [1] */ + u32 arp_done : 1; /* [2] */ + u32 arp_cmd_err : 1; /* [3] */ + u32 rxed_wrong_cmd : 8; /* [11:4] */ + u32 rsv_51 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smb_arp_info_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smb_i2c_con_u smb_i2c_con; /* 0 */ + volatile csr_smb_i2c_tar_u smb_i2c_tar; /* 4 */ + volatile csr_smb_i2c_sar_u smb_i2c_sar; /* 8 */ + volatile csr_smb_i2c_data_cmd_u smb_i2c_data_cmd; /* 10 */ + volatile csr_smb_i2c_ss_scl_hcnt_u smb_i2c_ss_scl_hcnt; /* 14 */ + volatile csr_smb_i2c_ss_scl_lcnt_u smb_i2c_ss_scl_lcnt; /* 18 */ + volatile csr_smb_i2c_fs_scl_hcnt_u smb_i2c_fs_scl_hcnt; /* 1C */ + volatile csr_smb_i2c_fs_scl_lcnt_u smb_i2c_fs_scl_lcnt; /* 20 */ + volatile csr_smb_i2c_intr_stat_u smb_i2c_intr_stat; /* 2C */ + volatile csr_smb_i2c_intr_en_u smb_i2c_intr_en; /* 30 */ + volatile csr_smb_i2c_intr_raw_u smb_i2c_intr_raw; /* 34 */ + volatile csr_smb_i2c_rx_tl_u smb_i2c_rx_tl; /* 38 */ + volatile csr_smb_i2c_tx_tl_u smb_i2c_tx_tl; /* 3C */ + volatile csr_smb_i2c_enable_u smb_i2c_enable; /* 6C */ + volatile csr_smb_i2c_status_u smb_i2c_status; /* 70 */ + volatile csr_smb_i2c_txflr_u smb_i2c_txflr; /* 74 */ + volatile csr_smb_i2c_rxflr_u smb_i2c_rxflr; /* 78 */ + volatile csr_smb_i2c_sda_hold_u smb_i2c_sda_hold; /* 7C */ + volatile csr_smb_i2c_tx_abrt_src_u smb_i2c_tx_abrt_src; /* 80 */ + volatile csr_smb_i2c_sda_setup_u smb_i2c_sda_setup; /* 94 */ + volatile csr_smb_i2c_ack_general_call_u smb_i2c_ack_general_call; /* 98 */ + volatile csr_smb_i2c_enable_status_u smb_i2c_enable_status; /* 9C */ + volatile csr_smb_i2c_scl_switch_u smb_i2c_scl_switch; /* A0 */ + volatile csr_smb_i2c_scl_sim_u smb_i2c_scl_sim; /* A4 */ + volatile csr_smb_i2c_lpif_state_u smb_i2c_lpif_state; /* A8 */ + volatile csr_smb_i2c_lock_u smb_i2c_lock; /* AC */ + volatile csr_smb_i2c_sda_switch_u smb_i2c_sda_switch; /* B0 */ + volatile csr_smb_i2c_sda_sim_u smb_i2c_sda_sim; /* B4 */ + volatile csr_smb_i2c_sar_mask_u smb_i2c_sar_mask; /* 100 */ + volatile csr_smb_i2c_pmbus_ctrl_u smb_i2c_pmbus_ctrl; /* 104 */ + volatile csr_smb_i2c_low_timeout_u smb_i2c_low_timeout; /* 108 */ + volatile csr_smb_i2c_high_timeout_u smb_i2c_high_timeout; /* 10C */ + volatile csr_smb_i2c_slv_alert_set_u smb_i2c_slv_alert_set; /* 110 */ + volatile csr_smb_i2c_mst_alert_do_u smb_i2c_mst_alert_do; /* 114 */ + volatile csr_smb_i2c_ack_resp_u smb_i2c_ack_resp; /* 118 */ + volatile csr_smb_i2c_pec_info_u smb_i2c_pec_info; /* 11C */ + volatile csr_smb_i2c_addr_receive_u smb_i2c_addr_receive; /* 120 */ + volatile csr_smb_i2c_manu_ack_cnt_u smb_i2c_manu_ack_cnt; /* 124 */ + volatile csr_smb_i2c_grp_cmd_u smb_i2c_grp_cmd; /* 128 */ + volatile csr_smb_i2c_pmbus_scl_det_u smb_i2c_pmbus_scl_det; /* 12C */ + volatile csr_smb_i2c_pmbus_idlecnt_u smb_i2c_pmbus_idlecnt; /* 130 */ + volatile csr_smb_i2c_pmbus_rst_u smb_i2c_pmbus_rst; /* 134 */ + volatile csr_smb_i2c_tx_info_u smb_i2c_tx_info[64]; /* 138 */ + volatile csr_smb_i2c_tx_cnt_u smb_i2c_tx_cnt; /* 238 */ + volatile csr_smb_i2c_trigger_en_u smb_i2c_trigger_en; /* 23C */ + volatile csr_smb_udid_0_u smb_udid_0; /* 240 */ + volatile csr_smb_udid_1_u smb_udid_1; /* 244 */ + volatile csr_smb_udid_2_u smb_udid_2; /* 248 */ + volatile csr_smb_udid_3_u smb_udid_3; /* 24C */ + volatile csr_smb_arp_addr_u smb_arp_addr; /* 250 */ + volatile csr_smb_psa_u smb_psa; /* 254 */ + volatile csr_smb_notify_do_u smb_notify_do; /* 258 */ + volatile csr_smb_arp_info_u smb_arp_info; /* 25C */ +} S_smbus_REGS_TYPE; + +/* Declare the struct pointor of the module smbus */ +extern volatile S_smbus_REGS_TYPE *gopsmbusAllReg; + +/* Declare the functions that set the member value */ +int iSetSMB_I2C_CON_master_enable(unsigned int umaster_enable); +int iSetSMB_I2C_CON_speed(unsigned int uspeed); +int iSetSMB_I2C_CON_slave_10bit(unsigned int uslave_10bit); +int iSetSMB_I2C_CON_restart_en(unsigned int urestart_en); +int iSetSMB_I2C_CON_slave_disable(unsigned int uslave_disable); +int iSetSMB_I2C_TAR_i2c_tar(unsigned int ui2c_tar); +int iSetSMB_I2C_TAR_gc_or_start(unsigned int ugc_or_start); +int iSetSMB_I2C_TAR_special(unsigned int uspecial); +int iSetSMB_I2C_TAR_master_10bit(unsigned int umaster_10bit); +int iSetSMB_I2C_SAR_i2c_sar(unsigned int ui2c_sar); +int iSetSMB_I2C_DATA_CMD_addr_or_data(unsigned int uaddr_or_data); +int iSetSMB_I2C_DATA_CMD_cmd(unsigned int ucmd); +int iSetSMB_I2C_DATA_CMD_addr_en(unsigned int uaddr_en); +int iSetSMB_I2C_DATA_CMD_stop_en(unsigned int ustop_en); +int iSetSMB_I2C_SS_SCL_HCNT_i2c_ss_scl_hcnt(unsigned int ui2c_ss_scl_hcnt); +int iSetSMB_I2C_SS_SCL_LCNT_i2c_ss_scl_lcnt(unsigned int ui2c_ss_scl_lcnt); +int iSetSMB_I2C_FS_SCL_HCNT_i2c_fs_scl_hcnt(unsigned int ui2c_fs_scl_hcnt); +int iSetSMB_I2C_FS_SCL_LCNT_i2c_fs_scl_lcnt(unsigned int ui2c_fs_scl_lcnt); +int iSetSMB_I2C_INTR_STAT_rx_under_stat(unsigned int urx_under_stat); +int iSetSMB_I2C_INTR_STAT_rx_over_stat(unsigned int urx_over_stat); +int iSetSMB_I2C_INTR_STAT_rx_full_stat(unsigned int urx_full_stat); +int iSetSMB_I2C_INTR_STAT_tx_over_stat(unsigned int utx_over_stat); +int iSetSMB_I2C_INTR_STAT_tx_empty_stat(unsigned int utx_empty_stat); +int iSetSMB_I2C_INTR_STAT_rd_req_stat(unsigned int urd_req_stat); +int iSetSMB_I2C_INTR_STAT_tx_abrt_stat(unsigned int utx_abrt_stat); +int iSetSMB_I2C_INTR_STAT_tx_done_stat(unsigned int utx_done_stat); +int iSetSMB_I2C_INTR_STAT_activity_stat(unsigned int uactivity_stat); +int iSetSMB_I2C_INTR_STAT_stop_det_stat(unsigned int ustop_det_stat); +int iSetSMB_I2C_INTR_STAT_start_det_stat(unsigned int ustart_det_stat); +int iSetSMB_I2C_INTR_STAT_gen_call_stat(unsigned int ugen_call_stat); +int iSetSMB_I2C_INTR_STAT_alert_det_stat(unsigned int ualert_det_stat); +int iSetSMB_I2C_INTR_STAT_slv_data_receive_stat(unsigned int uslv_data_receive_stat); +int iSetSMB_I2C_INTR_STAT_slv_addr_receive_stat(unsigned int uslv_addr_receive_stat); +int iSetSMB_I2C_INTR_STAT_scl_low_tout_stat(unsigned int uscl_low_tout_stat); +int iSetSMB_I2C_INTR_STAT_scl_high_tout_stat(unsigned int uscl_high_tout_stat); +int iSetSMB_I2C_INTR_STAT_pmbus_cmd_finish_stat(unsigned int upmbus_cmd_finish_stat); +int iSetSMB_I2C_INTR_STAT_pec_rd_err_stat(unsigned int upec_rd_err_stat); +int iSetSMB_I2C_INTR_STAT_arp_cmd_err_stat(unsigned int uarp_cmd_err_stat); +int iSetSMB_I2C_INTR_EN_rx_under_en(unsigned int urx_under_en); +int iSetSMB_I2C_INTR_EN_rx_over_en(unsigned int urx_over_en); +int iSetSMB_I2C_INTR_EN_rx_full_en(unsigned int urx_full_en); +int iSetSMB_I2C_INTR_EN_tx_over_en(unsigned int utx_over_en); +int iSetSMB_I2C_INTR_EN_tx_empty_en(unsigned int utx_empty_en); +int iSetSMB_I2C_INTR_EN_rd_req_en(unsigned int urd_req_en); +int iSetSMB_I2C_INTR_EN_tx_abrt_en(unsigned int utx_abrt_en); +int iSetSMB_I2C_INTR_EN_tx_done_en(unsigned int utx_done_en); +int iSetSMB_I2C_INTR_EN_activity_en(unsigned int uactivity_en); +int iSetSMB_I2C_INTR_EN_stop_det_en(unsigned int ustop_det_en); +int iSetSMB_I2C_INTR_EN_start_det_en(unsigned int ustart_det_en); +int iSetSMB_I2C_INTR_EN_gen_call_en(unsigned int ugen_call_en); +int iSetSMB_I2C_INTR_EN_alert_det_en(unsigned int ualert_det_en); +int iSetSMB_I2C_INTR_EN_slv_data_receive_en(unsigned int uslv_data_receive_en); +int iSetSMB_I2C_INTR_EN_slv_addr_receive_en(unsigned int uslv_addr_receive_en); +int iSetSMB_I2C_INTR_EN_scl_low_tout_en(unsigned int uscl_low_tout_en); +int iSetSMB_I2C_INTR_EN_scl_high_tout_en(unsigned int uscl_high_tout_en); +int iSetSMB_I2C_INTR_EN_pmbus_cmd_finish_en(unsigned int upmbus_cmd_finish_en); +int iSetSMB_I2C_INTR_EN_pec_rd_err_en(unsigned int upec_rd_err_en); +int iSetSMB_I2C_INTR_EN_arp_cmd_err_en(unsigned int uarp_cmd_err_en); +int iSetSMB_I2C_INTR_RAW_rx_under(unsigned int urx_under); +int iSetSMB_I2C_INTR_RAW_rx_over(unsigned int urx_over); +int iSetSMB_I2C_INTR_RAW_rx_full(unsigned int urx_full); +int iSetSMB_I2C_INTR_RAW_tx_over(unsigned int utx_over); +int iSetSMB_I2C_INTR_RAW_tx_empty(unsigned int utx_empty); +int iSetSMB_I2C_INTR_RAW_rd_req(unsigned int urd_req); +int iSetSMB_I2C_INTR_RAW_tx_abrt(unsigned int utx_abrt); +int iSetSMB_I2C_INTR_RAW_tx_done(unsigned int utx_done); +int iSetSMB_I2C_INTR_RAW_activity(unsigned int uactivity); +int iSetSMB_I2C_INTR_RAW_stop_det(unsigned int ustop_det); +int iSetSMB_I2C_INTR_RAW_start_det(unsigned int ustart_det); +int iSetSMB_I2C_INTR_RAW_gen_call(unsigned int ugen_call); +int iSetSMB_I2C_INTR_RAW_alert_det(unsigned int ualert_det); +int iSetSMB_I2C_INTR_RAW_slv_data_receive(unsigned int uslv_data_receive); +int iSetSMB_I2C_INTR_RAW_slv_addr_received(unsigned int uslv_addr_received); +int iSetSMB_I2C_INTR_RAW_scl_low_tout(unsigned int uscl_low_tout); +int iSetSMB_I2C_INTR_RAW_scl_high_tout(unsigned int uscl_high_tout); +int iSetSMB_I2C_INTR_RAW_pmbus_cmd_finish(unsigned int upmbus_cmd_finish); +int iSetSMB_I2C_INTR_RAW_pec_rd_err(unsigned int upec_rd_err); +int iSetSMB_I2C_INTR_RAW_arp_cmd_err(unsigned int uarp_cmd_err); +int iSetSMB_I2C_RX_TL_rx_tl(unsigned int urx_tl); +int iSetSMB_I2C_TX_TL_tx_tl(unsigned int utx_tl); +int iSetSMB_I2C_ENABLE_enable(unsigned int uenable); +int iSetSMB_I2C_STATUS_i2c_activity(unsigned int ui2c_activity); +int iSetSMB_I2C_STATUS_tx_fifo_nfull(unsigned int utx_fifo_nfull); +int iSetSMB_I2C_STATUS_tx_fifo_empty(unsigned int utx_fifo_empty); +int iSetSMB_I2C_STATUS_rx_fifo_nempty(unsigned int urx_fifo_nempty); +int iSetSMB_I2C_STATUS_rx_fifo_full(unsigned int urx_fifo_full); +int iSetSMB_I2C_STATUS_timeout_sda(unsigned int utimeout_sda); +int iSetSMB_I2C_STATUS_timeout_scl(unsigned int utimeout_scl); +int iSetSMB_I2C_STATUS_bus_busy(unsigned int ubus_busy); +int iSetSMB_I2C_STATUS_alert_status(unsigned int ualert_status); +int iSetSMB_I2C_STATUS_sda_in(unsigned int usda_in); +int iSetSMB_I2C_STATUS_scl_in(unsigned int uscl_in); +int iSetSMB_I2C_STATUS_mst_activity(unsigned int umst_activity); +int iSetSMB_I2C_STATUS_mst_cur_fsm(unsigned int umst_cur_fsm); +int iSetSMB_I2C_STATUS_mst_timeout_fsm(unsigned int umst_timeout_fsm); +int iSetSMB_I2C_STATUS_slv_activity(unsigned int uslv_activity); +int iSetSMB_I2C_STATUS_slv_cur_fsm(unsigned int uslv_cur_fsm); +int iSetSMB_I2C_STATUS_slv_timeout_fsm(unsigned int uslv_timeout_fsm); +int iSetSMB_I2C_TXFLR_tx_flr(unsigned int utx_flr); +int iSetSMB_I2C_RXFLR_rx_flr(unsigned int urx_flr); +int iSetSMB_I2C_SDA_HOLD_sda_hold(unsigned int usda_hold); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_7b_addr_noack(unsigned int uabrt_7b_addr_noack); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_10addr1_noack(unsigned int uabrt_10addr1_noack); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_10addr2_noack(unsigned int uabrt_10addr2_noack); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_txdata_noack(unsigned int uabrt_txdata_noack); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_gcall_noack(unsigned int uabrt_gcall_noack); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_gcall_read(unsigned int uabrt_gcall_read); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_hs_ackdet(unsigned int uabrt_hs_ackdet); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_sbyte_ackdet(unsigned int uabrt_sbyte_ackdet); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_hs_norstrt(unsigned int uabrt_hs_norstrt); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_sbyte_norstrt(unsigned int uabrt_sbyte_norstrt); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_10b_rd_norstrt(unsigned int uabrt_10b_rd_norstrt); +int iSetSMB_I2C_TX_ABRT_SRC_arb_lost(unsigned int uarb_lost); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_slvflush_txfifo(unsigned int uabrt_slvflush_txfifo); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_slv_lft(unsigned int uabrt_slv_lft); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_slvrd_intx(unsigned int uabrt_slvrd_intx); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_slv_stop(unsigned int uabrt_slv_stop); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_slv_alert(unsigned int uabrt_slv_alert); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_slv_pec(unsigned int uabrt_slv_pec); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_nack_pec(unsigned int uabrt_nack_pec); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_mst_comb(unsigned int uabrt_mst_comb); +int iSetSMB_I2C_TX_ABRT_SRC_abrt_mst_alert(unsigned int uabrt_mst_alert); +int iSetSMB_I2C_SDA_SETUP_sda_setup(unsigned int usda_setup); +int iSetSMB_I2C_ACK_GENERAL_CALL_ack_gen_call(unsigned int uack_gen_call); +int iSetSMB_I2C_ENABLE_STATUS_i2c_en(unsigned int ui2c_en); +int iSetSMB_I2C_ENABLE_STATUS_slv_disable_while_busy(unsigned int uslv_disable_while_busy); +int iSetSMB_I2C_ENABLE_STATUS_slv_rx_lost(unsigned int uslv_rx_lost); +int iSetSMB_I2C_SCL_SWITCH_scl_switch(unsigned int uscl_switch); +int iSetSMB_I2C_SCL_SIM_scl_sim(unsigned int uscl_sim); +int iSetSMB_I2C_LPIF_STATE_i2c_lpif_state(unsigned int ui2c_lpif_state); +int iSetSMB_I2C_LOCK_i2c_lock(unsigned int ui2c_lock); +int iSetSMB_I2C_SDA_SWITCH_sda_switch(unsigned int usda_switch); +int iSetSMB_I2C_SDA_SIM_sda_sim(unsigned int usda_sim); +int iSetSMB_I2C_SAR_MASK_i2c_sar_mask(unsigned int ui2c_sar_mask); +int iSetSMB_I2C_PMBUS_CTRL_ack_mode(unsigned int uack_mode); +int iSetSMB_I2C_PMBUS_CTRL_alert_en(unsigned int ualert_en); +int iSetSMB_I2C_PMBUS_CTRL_pec_en(unsigned int upec_en); +int iSetSMB_I2C_PMBUS_CTRL_arp_en(unsigned int uarp_en); +int iSetSMB_I2C_LOW_TIMEOUT_i2c_low_timeout(unsigned int ui2c_low_timeout); +int iSetSMB_I2C_HIGH_TIMEOUT_i2c_high_timeout(unsigned int ui2c_high_timeout); +int iSetSMB_I2C_SLV_ALERT_SET_alert_set(unsigned int ualert_set); +int iSetSMB_I2C_MST_ALERT_DO_alert_do(unsigned int ualert_do); +int iSetSMB_I2C_ACK_RESP_ack_resp(unsigned int uack_resp); +int iSetSMB_I2C_PEC_INFO_pec_receive(unsigned int upec_receive); +int iSetSMB_I2C_PEC_INFO_pec_valid(unsigned int upec_valid); +int iSetSMB_I2C_PEC_INFO_pec_check(unsigned int upec_check); +int iSetSMB_I2C_PEC_INFO_pec_err_info(unsigned int upec_err_info); +int iSetSMB_I2C_ADDR_RECEIVE_slv_addr_receive(unsigned int uslv_addr_receive); +int iSetSMB_I2C_MANU_ACK_CNT_i2c_manu_ack_cnt(unsigned int ui2c_manu_ack_cnt); +int iSetSMB_I2C_GRP_CMD_group_cmd_en(unsigned int ugroup_cmd_en); +int iSetSMB_I2C_PMBUS_SCL_DET_scl_idle_det_en(unsigned int uscl_idle_det_en); +int iSetSMB_I2C_PMBUS_SCL_DET_scl_ltimeout_en(unsigned int uscl_ltimeout_en); +int iSetSMB_I2C_PMBUS_SCL_DET_scl_htimeout_en(unsigned int uscl_htimeout_en); +int iSetSMB_I2C_PMBUS_IDLECNT_pmbus_idle_cnt(unsigned int upmbus_idle_cnt); +int iSetSMB_I2C_PMBUS_RST_srst(unsigned int usrst); +int iSetSMB_I2C_TX_INFO_i2c_addr_or_data(unsigned int ui2c_addr_or_data); +int iSetSMB_I2C_TX_INFO_i2c_cmd(unsigned int ui2c_cmd); +int iSetSMB_I2C_TX_INFO_i2c_addr_en(unsigned int ui2c_addr_en); +int iSetSMB_I2C_TX_INFO_i2c_stop_en(unsigned int ui2c_stop_en); +int iSetSMB_I2C_TX_CNT_i2c_tx_cnt(unsigned int ui2c_tx_cnt); +int iSetSMB_I2C_TRIGGER_EN_i2c_trigger_en(unsigned int ui2c_trigger_en); +int iSetSMB_UDID_0_vendor_spec_id(unsigned int uvendor_spec_id); +int iSetSMB_UDID_1_subsys_device_id(unsigned int usubsys_device_id); +int iSetSMB_UDID_1_subsys_vendor_id(unsigned int usubsys_vendor_id); +int iSetSMB_UDID_2_smbus_version(unsigned int usmbus_version); +int iSetSMB_UDID_2_support_protocol(unsigned int usupport_protocol); +int iSetSMB_UDID_2_device_id(unsigned int udevice_id); +int iSetSMB_UDID_3_vendor_id(unsigned int uvendor_id); +int iSetSMB_UDID_3_silicon_revision_id(unsigned int usilicon_revision_id); +int iSetSMB_UDID_3_udid_version(unsigned int uudid_version); +int iSetSMB_UDID_3_arp_pec_en(unsigned int uarp_pec_en); +int iSetSMB_UDID_3_addr_type(unsigned int uaddr_type); +int iSetSMB_ARP_ADDR_arp_addr(unsigned int uarp_addr); +int iSetSMB_PSA_smb_psa(unsigned int usmb_psa); +int iSetSMB_NOTIFY_DO_notify_do(unsigned int unotify_do); +int iSetSMB_ARP_INFO_av_flg(unsigned int uav_flg); +int iSetSMB_ARP_INFO_ar_flg(unsigned int uar_flg); +int iSetSMB_ARP_INFO_arp_done(unsigned int uarp_done); +int iSetSMB_ARP_INFO_arp_cmd_err(unsigned int uarp_cmd_err); +int iSetSMB_ARP_INFO_rxed_wrong_cmd(unsigned int urxed_wrong_cmd); + + +/* Define the union csr_ic_con_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 master : 1; /* [0] */ + u32 speed : 2; /* [2:1] */ + u32 slave_10bit : 1; /* [3] */ + u32 master_10bit : 1; /* [4] */ + u32 restart_en : 1; /* [5] */ + u32 slave_disable : 1; /* [6] */ + u32 stop_det_ifaddressed : 1; /* [7] */ + u32 tx_empty_ctrl : 1; /* [8] */ + u32 rx_fifo_full_hld_ctrl : 1; /* [9] */ + u32 stop_det_if_master_active : 1; /* [10] */ + u32 bus_clear_feature_ctrl : 1; /* [11] */ + u32 rsv_0 : 4; /* [15:12] */ + u32 optional_sar_ctrl : 1; /* [16] */ + u32 smbus_slave_quick_en : 1; /* [17] */ + u32 smbus_arp_en : 1; /* [18] */ + u32 smbus_persistent_slv_addr_en : 1; /* [19] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_con_u; + +/* Define the union csr_ic_tar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_tar : 10; /* [9:0] */ + u32 gc_or_start : 1; /* [10] */ + u32 special : 1; /* [11] */ + u32 ic_10bitaddr_master : 1; /* [12] */ + u32 device_id_in_tar : 1; /* [13] */ + u32 rsv_2 : 2; /* [15:14] */ + u32 smbus_quick_cmd : 1; /* [16] */ + u32 rsv_3 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_tar_u; + +/* Define the union csr_ic_sar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_sar : 10; /* [9:0] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_sar_u; + +/* Define the union csr_ic_hs_maddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_hs_mar : 3; /* [2:0] */ + u32 rsv_5 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_hs_maddr_u; + +/* Define the union csr_ic_data_cmd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat : 8; /* [7:0] */ + u32 cmd : 1; /* [8] */ + u32 stop : 1; /* [9] */ + u32 restart : 1; /* [10] */ + u32 first_data_byte : 1; /* [11] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_data_cmd_u; + +/* Define the union csr_ic_ss_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_ss_scl_hcnt : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_ss_scl_hcnt_u; + +/* Define the union csr_ic_ss_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_ss_scl_lcnt : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_ss_scl_lcnt_u; + +/* Define the union csr_ic_fs_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_fs_scl_hcnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_fs_scl_hcnt_u; + +/* Define the union csr_ic_fs_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_fs_scl_lcnt : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_fs_scl_lcnt_u; + +/* Define the union csr_ic_hs_scl_hcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_hs_scl_hcnt : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_hs_scl_hcnt_u; + +/* Define the union csr_ic_hs_scl_lcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_hs_scl_lcnt : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_hs_scl_lcnt_u; + +/* Define the union csr_ic_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 r_rx_under : 1; /* [0] */ + u32 r_rx_over : 1; /* [1] */ + u32 r_rx_full : 1; /* [2] */ + u32 r_tx_over : 1; /* [3] */ + u32 r_tx_empty : 1; /* [4] */ + u32 r_rd_req : 1; /* [5] */ + u32 r_tx_abrt : 1; /* [6] */ + u32 r_rx_done : 1; /* [7] */ + u32 r_activity : 1; /* [8] */ + u32 r_stop_det : 1; /* [9] */ + u32 r_start_det : 1; /* [10] */ + u32 r_gen_call : 1; /* [11] */ + u32 r_restart_det : 1; /* [12] */ + u32 r_mst_on_hold : 1; /* [13] */ + u32 r_scl_stuck_at_low : 1; /* [14] */ + u32 rsv_13 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_intr_stat_u; + +/* Define the union csr_ic_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 m_rx_under : 1; /* [0] */ + u32 m_rx_over : 1; /* [1] */ + u32 m_rx_full : 1; /* [2] */ + u32 m_tx_over : 1; /* [3] */ + u32 m_tx_empty : 1; /* [4] */ + u32 m_rd_req : 1; /* [5] */ + u32 m_tx_abrt : 1; /* [6] */ + u32 m_rx_done : 1; /* [7] */ + u32 m_activity : 1; /* [8] */ + u32 m_stop_det : 1; /* [9] */ + u32 m_start_det : 1; /* [10] */ + u32 m_gen_call : 1; /* [11] */ + u32 m_restart_det : 1; /* [12] */ + u32 m_mst_on_hold : 1; /* [13] */ + u32 m_scl_stuck_at_low : 1; /* [14] */ + u32 rsv_14 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_intr_mask_u; + +/* Define the union csr_ic_raw_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_under : 1; /* [0] */ + u32 rx_over : 1; /* [1] */ + u32 rx_full : 1; /* [2] */ + u32 tx_over : 1; /* [3] */ + u32 tx_empty : 1; /* [4] */ + u32 rd_req : 1; /* [5] */ + u32 tx_abrt : 1; /* [6] */ + u32 rx_done : 1; /* [7] */ + u32 activity : 1; /* [8] */ + u32 stop_det : 1; /* [9] */ + u32 start_det : 1; /* [10] */ + u32 gen_call : 1; /* [11] */ + u32 restart_det : 1; /* [12] */ + u32 mst_on_hold : 1; /* [13] */ + u32 scl_stuck_at_low : 1; /* [14] */ + u32 rsv_15 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_raw_intr_stat_u; + +/* Define the union csr_ic_rx_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tl : 8; /* [7:0] */ + u32 rsv_16 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_rx_tl_u; + +/* Define the union csr_ic_tx_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tl : 8; /* [7:0] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_tx_tl_u; + +/* Define the union csr_ic_clr_intr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_intr : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_intr_u; + +/* Define the union csr_ic_clr_rx_under_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rx_under : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_rx_under_u; + +/* Define the union csr_ic_clr_rx_over_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rx_over : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_rx_over_u; + +/* Define the union csr_ic_clr_tx_over_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_tx_over : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_tx_over_u; + +/* Define the union csr_ic_clr_rd_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rd_req : 1; /* [0] */ + u32 rsv_22 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_rd_req_u; + +/* Define the union csr_ic_clr_tx_abrt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_tx_abrt : 1; /* [0] */ + u32 rsv_23 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_tx_abrt_u; + +/* Define the union csr_ic_clr_rx_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_rx_done : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_rx_done_u; + +/* Define the union csr_ic_clr_activity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_activity : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_activity_u; + +/* Define the union csr_ic_clr_stop_det_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_stop_det : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_stop_det_u; + +/* Define the union csr_ic_clr_start_det_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_start_det : 1; /* [0] */ + u32 rsv_27 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_start_det_u; + +/* Define the union csr_ic_clr_gen_call_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_gen_call : 1; /* [0] */ + u32 rsv_28 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_gen_call_u; + +/* Define the union csr_ic_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 abort : 1; /* [1] */ + u32 tx_cmd_block : 1; /* [2] */ + u32 sda_stuck_recovery_enable : 1; /* [3] */ + u32 rsv_29 : 12; /* [15:4] */ + u32 smbus_clk_reset : 1; /* [16] */ + u32 smbus_suspend_en : 1; /* [17] */ + u32 smbus_alert_en : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_enable_u; + +/* Define the union csr_ic_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 activity_s : 1; /* [0] */ + u32 tfnf : 1; /* [1] */ + u32 tfe : 1; /* [2] */ + u32 rfne : 1; /* [3] */ + u32 rff : 1; /* [4] */ + u32 mst_activity : 1; /* [5] */ + u32 slv_activity : 1; /* [6] */ + u32 mst_hold_tx_fifo_empty : 1; /* [7] */ + u32 mst_hold_rx_fifo_full : 1; /* [8] */ + u32 slv_hold_tx_fifo_empty : 1; /* [9] */ + u32 slv_hold_rx_fifo_full : 1; /* [10] */ + u32 sda_stuck_not_recovered : 1; /* [11] */ + u32 rsv_31 : 4; /* [15:12] */ + u32 smbus_quick_cmd_bit : 1; /* [16] */ + u32 smbus_slave_addr_valid : 1; /* [17] */ + u32 smbus_slave_addr_resolved : 1; /* [18] */ + u32 smbus_suspend_status : 1; /* [19] */ + u32 smbus_alert_status : 1; /* [20] */ + u32 rsv_32 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_status_u; + +/* Define the union csr_ic_txflr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txflr : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_txflr_u; + +/* Define the union csr_ic_rxflr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxflr : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_rxflr_u; + +/* Define the union csr_ic_sda_hold_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_sda_tx_hold : 16; /* [15:0] */ + u32 ic_sda_rx_hold : 8; /* [23:16] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_sda_hold_u; + +/* Define the union csr_ic_tx_abrt_source_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 abrt_7b_addr_noack : 1; /* [0] */ + u32 abrt_10addr1_noack : 1; /* [1] */ + u32 abrt_10addr2_noack : 1; /* [2] */ + u32 abrt_txdata_noack : 1; /* [3] */ + u32 abrt_gcall_noack : 1; /* [4] */ + u32 abrt_gcall_read : 1; /* [5] */ + u32 abrt_hs_ackdet : 1; /* [6] */ + u32 abrt_sbyte_ackdet : 1; /* [7] */ + u32 abrt_hs_norstrt : 1; /* [8] */ + u32 abrt_sbyte_norstrt : 1; /* [9] */ + u32 abrt_10b_rd_norstrt : 1; /* [10] */ + u32 arb_master_dis : 1; /* [11] */ + u32 arb_lost : 1; /* [12] */ + u32 abrt_slvflush_txfifo : 1; /* [13] */ + u32 abrt_slv_arblost : 1; /* [14] */ + u32 abrt_slvrd_intx : 1; /* [15] */ + u32 abrt_user_abrt : 1; /* [16] */ + u32 abrt_sda_stuck_at_low : 1; /* [17] */ + u32 abrt_device_noack : 1; /* [18] */ + u32 abrt_device_slvaddr_noack : 1; /* [19] */ + u32 abrt_device_write : 1; /* [20] */ + u32 rsv_36 : 2; /* [22:21] */ + u32 tx_flush_cnt : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_tx_abrt_source_u; + +/* Define the union csr_ic_slv_data_only_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nack : 1; /* [0] */ + u32 rsv_37 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_slv_data_only_u; + +/* Define the union csr_ic_sda_setup_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sda_setup : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_sda_setup_u; + +/* Define the union csr_ic_ack_general_call_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_gen_call : 1; /* [0] */ + u32 rsv_39 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_ack_general_call_u; + +/* Define the union csr_ic_enable_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_en : 1; /* [0] */ + u32 slv_disable_while_busy : 1; /* [1] */ + u32 slv_rx_data_lost : 1; /* [2] */ + u32 rsv_40 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_enable_status_u; + +/* Define the union csr_ic_fs_spklen_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_fs_spklen : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_fs_spklen_u; + +/* Define the union csr_ic_scl_stuck_at_low_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_scl_stuck_low_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_scl_stuck_at_low_timeout_u; + +/* Define the union csr_ic_sda_stuck_at_low_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_sda_stuck_low_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_sda_stuck_at_low_timeout_u; + +/* Define the union csr_ic_clr_scl_stuck_det_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_scl_stuck_det : 1; /* [0] */ + u32 rsv_42 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_scl_stuck_det_u; + +/* Define the union csr_ic_smbus_clk_low_sext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smbus_clk_low_sext_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_clk_low_sext_u; + +/* Define the union csr_ic_smbus_clk_low_mext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smbus_clk_low_mext_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_clk_low_mext_u; + +/* Define the union csr_ic_smbus_thigh_max_idle_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smbus_thigh_max_bus_idle_cnt : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_thigh_max_idle_count_u; + +/* Define the union csr_ic_smbus_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 r_slv_clock_extnd_timeout : 1; /* [0] */ + u32 r_mst_clock_extnd_timeout : 1; /* [1] */ + u32 r_quick_cmd_det : 1; /* [2] */ + u32 r_host_notify_mst_det : 1; /* [3] */ + u32 r_arp_prepare_cmd_det : 1; /* [4] */ + u32 r_arp_rst_cmd_det : 1; /* [5] */ + u32 r_arp_get_udid_cmd_det : 1; /* [6] */ + u32 r_arp_assgn_addr_cmd_det : 1; /* [7] */ + u32 r_slv_rx_pec_nack : 1; /* [8] */ + u32 r_smbus_suspend_det : 1; /* [9] */ + u32 r_smbus_alert_det : 1; /* [10] */ + u32 rsv_44 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_intr_stat_u; + +/* Define the union csr_ic_smbus_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 m_slv_clock_extnd_timeout : 1; /* [0] */ + u32 m_mst_clock_extnd_timeout : 1; /* [1] */ + u32 m_quick_cmd_det : 1; /* [2] */ + u32 m_host_notify_mst_det : 1; /* [3] */ + u32 m_arp_prepare_cmd_det : 1; /* [4] */ + u32 m_arp_rst_cmd_det : 1; /* [5] */ + u32 m_arp_get_udid_cmd_det : 1; /* [6] */ + u32 m_arp_assgn_addr_cmd_det : 1; /* [7] */ + u32 m_slv_rx_pec_nack : 1; /* [8] */ + u32 m_smbus_suspend_det : 1; /* [9] */ + u32 m_smbus_alert_det : 1; /* [10] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_intr_mask_u; + +/* Define the union csr_ic_smbus_raw_intr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ri_slv_clock_extnd_timeout : 1; /* [0] */ + u32 ri_mst_clock_extnd_timeout : 1; /* [1] */ + u32 ri_quick_cmd_det : 1; /* [2] */ + u32 ri_host_notify_mst_det : 1; /* [3] */ + u32 ri_arp_prepare_cmd_det : 1; /* [4] */ + u32 ri_arp_rst_cmd_det : 1; /* [5] */ + u32 ri_arp_get_udid_cmd_det : 1; /* [6] */ + u32 ri_arp_assgn_addr_cmd_det : 1; /* [7] */ + u32 ri_slv_rx_pec_nack : 1; /* [8] */ + u32 ri_smbus_suspend_det : 1; /* [9] */ + u32 ri_smbus_alert_det : 1; /* [10] */ + u32 rsv_46 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_raw_intr_stat_u; + +/* Define the union csr_ic_clr_smbus_intr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_slv_clock_extnd_timeout : 1; /* [0] */ + u32 clr_mst_clock_extnd_timeout : 1; /* [1] */ + u32 clr_quick_cmd_det : 1; /* [2] */ + u32 clr_host_notify_mst_det : 1; /* [3] */ + u32 clr_arp_prepare_cmd_det : 1; /* [4] */ + u32 clr_arp_rst_cmd_det : 1; /* [5] */ + u32 clr_arp_get_udid_cmd_det : 1; /* [6] */ + u32 clr_arp_assgn_addr_cmd_det : 1; /* [7] */ + u32 clr_slv_rx_pec_nack : 1; /* [8] */ + u32 clr_smbus_suspend_det : 1; /* [9] */ + u32 clr_smbus_alert_det : 1; /* [10] */ + u32 rsv_47 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_clr_smbus_intr_u; + +/* Define the union csr_ic_smbus_udid_lsb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smbus_udid_lsb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_udid_lsb_u; + +/* Define the union csr_ic_comp_param_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_data_width : 2; /* [1:0] */ + u32 max_speed_mode : 2; /* [3:2] */ + u32 hc_count_values : 1; /* [4] */ + u32 intr_io : 1; /* [5] */ + u32 has_dma : 1; /* [6] */ + u32 add_encoded_params : 1; /* [7] */ + u32 rx_buffer_depth : 8; /* [15:8] */ + u32 tx_buffer_depth : 8; /* [23:16] */ + u32 rsv_48 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_comp_param_1_u; + +/* Define the union csr_ic_comp_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_comp_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_comp_version_u; + +/* Define the union csr_ic_comp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_comp_type : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_comp_type_u; + +/* Define the union csr_ic_smbus_udid_msb0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_smbus_udid_msb0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_udid_msb0_u; + +/* Define the union csr_ic_smbus_udid_msb1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_smbus_udid_msb1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_udid_msb1_u; + +/* Define the union csr_ic_smbus_udid_msb2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ic_smbus_udid_msb2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ic_smbus_udid_msb2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ic_con_u ic_con; /* 0 */ + volatile csr_ic_tar_u ic_tar; /* 4 */ + volatile csr_ic_sar_u ic_sar; /* 8 */ + volatile csr_ic_hs_maddr_u ic_hs_maddr; /* C */ + volatile csr_ic_data_cmd_u ic_data_cmd; /* 10 */ + volatile csr_ic_ss_scl_hcnt_u ic_ss_scl_hcnt; /* 14 */ + volatile csr_ic_ss_scl_lcnt_u ic_ss_scl_lcnt; /* 18 */ + volatile csr_ic_fs_scl_hcnt_u ic_fs_scl_hcnt; /* 1C */ + volatile csr_ic_fs_scl_lcnt_u ic_fs_scl_lcnt; /* 20 */ + volatile csr_ic_hs_scl_hcnt_u ic_hs_scl_hcnt; /* 24 */ + volatile csr_ic_hs_scl_lcnt_u ic_hs_scl_lcnt; /* 28 */ + volatile csr_ic_intr_stat_u ic_intr_stat; /* 2C */ + volatile csr_ic_intr_mask_u ic_intr_mask; /* 30 */ + volatile csr_ic_raw_intr_stat_u ic_raw_intr_stat; /* 34 */ + volatile csr_ic_rx_tl_u ic_rx_tl; /* 38 */ + volatile csr_ic_tx_tl_u ic_tx_tl; /* 3C */ + volatile csr_ic_clr_intr_u ic_clr_intr; /* 40 */ + volatile csr_ic_clr_rx_under_u ic_clr_rx_under; /* 44 */ + volatile csr_ic_clr_rx_over_u ic_clr_rx_over; /* 48 */ + volatile csr_ic_clr_tx_over_u ic_clr_tx_over; /* 4C */ + volatile csr_ic_clr_rd_req_u ic_clr_rd_req; /* 50 */ + volatile csr_ic_clr_tx_abrt_u ic_clr_tx_abrt; /* 54 */ + volatile csr_ic_clr_rx_done_u ic_clr_rx_done; /* 58 */ + volatile csr_ic_clr_activity_u ic_clr_activity; /* 5C */ + volatile csr_ic_clr_stop_det_u ic_clr_stop_det; /* 60 */ + volatile csr_ic_clr_start_det_u ic_clr_start_det; /* 64 */ + volatile csr_ic_clr_gen_call_u ic_clr_gen_call; /* 68 */ + volatile csr_ic_enable_u ic_enable; /* 6C */ + volatile csr_ic_status_u ic_status; /* 70 */ + volatile csr_ic_txflr_u ic_txflr; /* 74 */ + volatile csr_ic_rxflr_u ic_rxflr; /* 78 */ + volatile csr_ic_sda_hold_u ic_sda_hold; /* 7C */ + volatile csr_ic_tx_abrt_source_u ic_tx_abrt_source; /* 80 */ + volatile csr_ic_slv_data_only_u ic_slv_data_only; /* 84 */ + volatile csr_ic_sda_setup_u ic_sda_setup; /* 94 */ + volatile csr_ic_ack_general_call_u ic_ack_general_call; /* 98 */ + volatile csr_ic_enable_status_u ic_enable_status; /* 9C */ + volatile csr_ic_fs_spklen_u ic_fs_spklen; /* A0 */ + volatile csr_ic_scl_stuck_at_low_timeout_u ic_scl_stuck_at_low_timeout; /* AC */ + volatile csr_ic_sda_stuck_at_low_timeout_u ic_sda_stuck_at_low_timeout; /* B0 */ + volatile csr_ic_clr_scl_stuck_det_u ic_clr_scl_stuck_det; /* B4 */ + volatile csr_ic_smbus_clk_low_sext_u ic_smbus_clk_low_sext; /* BC */ + volatile csr_ic_smbus_clk_low_mext_u ic_smbus_clk_low_mext; /* C0 */ + volatile csr_ic_smbus_thigh_max_idle_count_u ic_smbus_thigh_max_idle_count; /* C4 */ + volatile csr_ic_smbus_intr_stat_u ic_smbus_intr_stat; /* C8 */ + volatile csr_ic_smbus_intr_mask_u ic_smbus_intr_mask; /* CC */ + volatile csr_ic_smbus_raw_intr_stat_u ic_smbus_raw_intr_stat; /* D0 */ + volatile csr_ic_clr_smbus_intr_u ic_clr_smbus_intr; /* D4 */ + volatile csr_ic_smbus_udid_lsb_u ic_smbus_udid_lsb; /* DC */ + volatile csr_ic_comp_param_1_u ic_comp_param_1; /* F4 */ + volatile csr_ic_comp_version_u ic_comp_version; /* F8 */ + volatile csr_ic_comp_type_u ic_comp_type; /* FC */ + volatile csr_ic_smbus_udid_msb0_u ic_smbus_udid_msb0; /* E0 */ + volatile csr_ic_smbus_udid_msb1_u ic_smbus_udid_msb1; /* E4 */ + volatile csr_ic_smbus_udid_msb2_u ic_smbus_udid_msb2; /* E8 */ +} S_smbus_new_cfg_REGS_TYPE; + +/* Declare the struct pointor of the module smbus_new_cfg */ +extern volatile S_smbus_new_cfg_REGS_TYPE *gopsmbus_new_cfgAllReg; + +/* Declare the functions that set the member value */ +int iSetIC_CON_master(unsigned int umaster); +int iSetIC_CON_speed(unsigned int uspeed); +int iSetIC_CON_slave_10bit(unsigned int uslave_10bit); +int iSetIC_CON_master_10bit(unsigned int umaster_10bit); +int iSetIC_CON_restart_en(unsigned int urestart_en); +int iSetIC_CON_slave_disable(unsigned int uslave_disable); +int iSetIC_CON_stop_det_ifaddressed(unsigned int ustop_det_ifaddressed); +int iSetIC_CON_tx_empty_ctrl(unsigned int utx_empty_ctrl); +int iSetIC_CON_rx_fifo_full_hld_ctrl(unsigned int urx_fifo_full_hld_ctrl); +int iSetIC_CON_stop_det_if_master_active(unsigned int ustop_det_if_master_active); +int iSetIC_CON_bus_clear_feature_ctrl(unsigned int ubus_clear_feature_ctrl); +int iSetIC_CON_optional_sar_ctrl(unsigned int uoptional_sar_ctrl); +int iSetIC_CON_smbus_slave_quick_en(unsigned int usmbus_slave_quick_en); +int iSetIC_CON_smbus_arp_en(unsigned int usmbus_arp_en); +int iSetIC_CON_smbus_persistent_slv_addr_en(unsigned int usmbus_persistent_slv_addr_en); +int iSetIC_TAR_ic_tar(unsigned int uic_tar); +int iSetIC_TAR_gc_or_start(unsigned int ugc_or_start); +int iSetIC_TAR_special(unsigned int uspecial); +int iSetIC_TAR_ic_10bitaddr_master(unsigned int uic_10bitaddr_master); +int iSetIC_TAR_device_id_in_tar(unsigned int udevice_id_in_tar); +int iSetIC_TAR_smbus_quick_cmd(unsigned int usmbus_quick_cmd); +int iSetIC_SAR_ic_sar(unsigned int uic_sar); +int iSetIC_HS_MADDR_ic_hs_mar(unsigned int uic_hs_mar); +int iSetIC_DATA_CMD_dat(unsigned int udat); +int iSetIC_DATA_CMD_cmd(unsigned int ucmd); +int iSetIC_DATA_CMD_stop(unsigned int ustop); +int iSetIC_DATA_CMD_restart(unsigned int urestart); +int iSetIC_DATA_CMD_first_data_byte(unsigned int ufirst_data_byte); +int iSetIC_SS_SCL_HCNT_ic_ss_scl_hcnt(unsigned int uic_ss_scl_hcnt); +int iSetIC_SS_SCL_LCNT_ic_ss_scl_lcnt(unsigned int uic_ss_scl_lcnt); +int iSetIC_FS_SCL_HCNT_ic_fs_scl_hcnt(unsigned int uic_fs_scl_hcnt); +int iSetIC_FS_SCL_LCNT_ic_fs_scl_lcnt(unsigned int uic_fs_scl_lcnt); +int iSetIC_HS_SCL_HCNT_ic_hs_scl_hcnt(unsigned int uic_hs_scl_hcnt); +int iSetIC_HS_SCL_LCNT_ic_hs_scl_lcnt(unsigned int uic_hs_scl_lcnt); +int iSetIC_INTR_STAT_r_rx_under(unsigned int ur_rx_under); +int iSetIC_INTR_STAT_r_rx_over(unsigned int ur_rx_over); +int iSetIC_INTR_STAT_r_rx_full(unsigned int ur_rx_full); +int iSetIC_INTR_STAT_r_tx_over(unsigned int ur_tx_over); +int iSetIC_INTR_STAT_r_tx_empty(unsigned int ur_tx_empty); +int iSetIC_INTR_STAT_r_rd_req(unsigned int ur_rd_req); +int iSetIC_INTR_STAT_r_tx_abrt(unsigned int ur_tx_abrt); +int iSetIC_INTR_STAT_r_rx_done(unsigned int ur_rx_done); +int iSetIC_INTR_STAT_r_activity(unsigned int ur_activity); +int iSetIC_INTR_STAT_r_stop_det(unsigned int ur_stop_det); +int iSetIC_INTR_STAT_r_start_det(unsigned int ur_start_det); +int iSetIC_INTR_STAT_r_gen_call(unsigned int ur_gen_call); +int iSetIC_INTR_STAT_r_restart_det(unsigned int ur_restart_det); +int iSetIC_INTR_STAT_r_mst_on_hold(unsigned int ur_mst_on_hold); +int iSetIC_INTR_STAT_r_scl_stuck_at_low(unsigned int ur_scl_stuck_at_low); +int iSetIC_INTR_MASK_m_rx_under(unsigned int um_rx_under); +int iSetIC_INTR_MASK_m_rx_over(unsigned int um_rx_over); +int iSetIC_INTR_MASK_m_rx_full(unsigned int um_rx_full); +int iSetIC_INTR_MASK_m_tx_over(unsigned int um_tx_over); +int iSetIC_INTR_MASK_m_tx_empty(unsigned int um_tx_empty); +int iSetIC_INTR_MASK_m_rd_req(unsigned int um_rd_req); +int iSetIC_INTR_MASK_m_tx_abrt(unsigned int um_tx_abrt); +int iSetIC_INTR_MASK_m_rx_done(unsigned int um_rx_done); +int iSetIC_INTR_MASK_m_activity(unsigned int um_activity); +int iSetIC_INTR_MASK_m_stop_det(unsigned int um_stop_det); +int iSetIC_INTR_MASK_m_start_det(unsigned int um_start_det); +int iSetIC_INTR_MASK_m_gen_call(unsigned int um_gen_call); +int iSetIC_INTR_MASK_m_restart_det(unsigned int um_restart_det); +int iSetIC_INTR_MASK_m_mst_on_hold(unsigned int um_mst_on_hold); +int iSetIC_INTR_MASK_m_scl_stuck_at_low(unsigned int um_scl_stuck_at_low); +int iSetIC_RAW_INTR_STAT_rx_under(unsigned int urx_under); +int iSetIC_RAW_INTR_STAT_rx_over(unsigned int urx_over); +int iSetIC_RAW_INTR_STAT_rx_full(unsigned int urx_full); +int iSetIC_RAW_INTR_STAT_tx_over(unsigned int utx_over); +int iSetIC_RAW_INTR_STAT_tx_empty(unsigned int utx_empty); +int iSetIC_RAW_INTR_STAT_rd_req(unsigned int urd_req); +int iSetIC_RAW_INTR_STAT_tx_abrt(unsigned int utx_abrt); +int iSetIC_RAW_INTR_STAT_rx_done(unsigned int urx_done); +int iSetIC_RAW_INTR_STAT_activity(unsigned int uactivity); +int iSetIC_RAW_INTR_STAT_stop_det(unsigned int ustop_det); +int iSetIC_RAW_INTR_STAT_start_det(unsigned int ustart_det); +int iSetIC_RAW_INTR_STAT_gen_call(unsigned int ugen_call); +int iSetIC_RAW_INTR_STAT_restart_det(unsigned int urestart_det); +int iSetIC_RAW_INTR_STAT_mst_on_hold(unsigned int umst_on_hold); +int iSetIC_RAW_INTR_STAT_scl_stuck_at_low(unsigned int uscl_stuck_at_low); +int iSetIC_RX_TL_rx_tl(unsigned int urx_tl); +int iSetIC_TX_TL_tx_tl(unsigned int utx_tl); +int iSetIC_CLR_INTR_clr_intr(unsigned int uclr_intr); +int iSetIC_CLR_RX_UNDER_clr_rx_under(unsigned int uclr_rx_under); +int iSetIC_CLR_RX_OVER_clr_rx_over(unsigned int uclr_rx_over); +int iSetIC_CLR_TX_OVER_clr_tx_over(unsigned int uclr_tx_over); +int iSetIC_CLR_RD_REQ_clr_rd_req(unsigned int uclr_rd_req); +int iSetIC_CLR_TX_ABRT_clr_tx_abrt(unsigned int uclr_tx_abrt); +int iSetIC_CLR_RX_DONE_clr_rx_done(unsigned int uclr_rx_done); +int iSetIC_CLR_ACTIVITY_clr_activity(unsigned int uclr_activity); +int iSetIC_CLR_STOP_DET_clr_stop_det(unsigned int uclr_stop_det); +int iSetIC_CLR_START_DET_clr_start_det(unsigned int uclr_start_det); +int iSetIC_CLR_GEN_CALL_clr_gen_call(unsigned int uclr_gen_call); +int iSetIC_ENABLE_enable(unsigned int uenable); +int iSetIC_ENABLE_abort(unsigned int uabort); +int iSetIC_ENABLE_tx_cmd_block(unsigned int utx_cmd_block); +int iSetIC_ENABLE_sda_stuck_recovery_enable(unsigned int usda_stuck_recovery_enable); +int iSetIC_ENABLE_smbus_clk_reset(unsigned int usmbus_clk_reset); +int iSetIC_ENABLE_smbus_suspend_en(unsigned int usmbus_suspend_en); +int iSetIC_ENABLE_smbus_alert_en(unsigned int usmbus_alert_en); +int iSetIC_STATUS_activity_s(unsigned int uactivity_s); +int iSetIC_STATUS_tfnf(unsigned int utfnf); +int iSetIC_STATUS_tfe(unsigned int utfe); +int iSetIC_STATUS_rfne(unsigned int urfne); +int iSetIC_STATUS_rff(unsigned int urff); +int iSetIC_STATUS_mst_activity(unsigned int umst_activity); +int iSetIC_STATUS_slv_activity(unsigned int uslv_activity); +int iSetIC_STATUS_mst_hold_tx_fifo_empty(unsigned int umst_hold_tx_fifo_empty); +int iSetIC_STATUS_mst_hold_rx_fifo_full(unsigned int umst_hold_rx_fifo_full); +int iSetIC_STATUS_slv_hold_tx_fifo_empty(unsigned int uslv_hold_tx_fifo_empty); +int iSetIC_STATUS_slv_hold_rx_fifo_full(unsigned int uslv_hold_rx_fifo_full); +int iSetIC_STATUS_sda_stuck_not_recovered(unsigned int usda_stuck_not_recovered); +int iSetIC_STATUS_smbus_quick_cmd_bit(unsigned int usmbus_quick_cmd_bit); +int iSetIC_STATUS_smbus_slave_addr_valid(unsigned int usmbus_slave_addr_valid); +int iSetIC_STATUS_smbus_slave_addr_resolved(unsigned int usmbus_slave_addr_resolved); +int iSetIC_STATUS_smbus_suspend_status(unsigned int usmbus_suspend_status); +int iSetIC_STATUS_smbus_alert_status(unsigned int usmbus_alert_status); +int iSetIC_TXFLR_txflr(unsigned int utxflr); +int iSetIC_RXFLR_rxflr(unsigned int urxflr); +int iSetIC_SDA_HOLD_ic_sda_tx_hold(unsigned int uic_sda_tx_hold); +int iSetIC_SDA_HOLD_ic_sda_rx_hold(unsigned int uic_sda_rx_hold); +int iSetIC_TX_ABRT_SOURCE_abrt_7b_addr_noack(unsigned int uabrt_7b_addr_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_10addr1_noack(unsigned int uabrt_10addr1_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_10addr2_noack(unsigned int uabrt_10addr2_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_txdata_noack(unsigned int uabrt_txdata_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_gcall_noack(unsigned int uabrt_gcall_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_gcall_read(unsigned int uabrt_gcall_read); +int iSetIC_TX_ABRT_SOURCE_abrt_hs_ackdet(unsigned int uabrt_hs_ackdet); +int iSetIC_TX_ABRT_SOURCE_abrt_sbyte_ackdet(unsigned int uabrt_sbyte_ackdet); +int iSetIC_TX_ABRT_SOURCE_abrt_hs_norstrt(unsigned int uabrt_hs_norstrt); +int iSetIC_TX_ABRT_SOURCE_abrt_sbyte_norstrt(unsigned int uabrt_sbyte_norstrt); +int iSetIC_TX_ABRT_SOURCE_abrt_10b_rd_norstrt(unsigned int uabrt_10b_rd_norstrt); +int iSetIC_TX_ABRT_SOURCE_arb_master_dis(unsigned int uarb_master_dis); +int iSetIC_TX_ABRT_SOURCE_arb_lost(unsigned int uarb_lost); +int iSetIC_TX_ABRT_SOURCE_abrt_slvflush_txfifo(unsigned int uabrt_slvflush_txfifo); +int iSetIC_TX_ABRT_SOURCE_abrt_slv_arblost(unsigned int uabrt_slv_arblost); +int iSetIC_TX_ABRT_SOURCE_abrt_slvrd_intx(unsigned int uabrt_slvrd_intx); +int iSetIC_TX_ABRT_SOURCE_abrt_user_abrt(unsigned int uabrt_user_abrt); +int iSetIC_TX_ABRT_SOURCE_abrt_sda_stuck_at_low(unsigned int uabrt_sda_stuck_at_low); +int iSetIC_TX_ABRT_SOURCE_abrt_device_noack(unsigned int uabrt_device_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_device_slvaddr_noack(unsigned int uabrt_device_slvaddr_noack); +int iSetIC_TX_ABRT_SOURCE_abrt_device_write(unsigned int uabrt_device_write); +int iSetIC_TX_ABRT_SOURCE_tx_flush_cnt(unsigned int utx_flush_cnt); +int iSetIC_SLV_DATA_ONLY_nack(unsigned int unack); +int iSetIC_SDA_SETUP_sda_setup(unsigned int usda_setup); +int iSetIC_ACK_GENERAL_CALL_ack_gen_call(unsigned int uack_gen_call); +int iSetIC_ENABLE_STATUS_ic_en(unsigned int uic_en); +int iSetIC_ENABLE_STATUS_slv_disable_while_busy(unsigned int uslv_disable_while_busy); +int iSetIC_ENABLE_STATUS_slv_rx_data_lost(unsigned int uslv_rx_data_lost); +int iSetIC_FS_SPKLEN_ic_fs_spklen(unsigned int uic_fs_spklen); +int iSetIC_SCL_STUCK_AT_LOW_TIMEOUT_ic_scl_stuck_low_timeout(unsigned int uic_scl_stuck_low_timeout); +int iSetIC_SDA_STUCK_AT_LOW_TIMEOUT_ic_sda_stuck_low_timeout(unsigned int uic_sda_stuck_low_timeout); +int iSetIC_CLR_SCL_STUCK_DET_clr_scl_stuck_det(unsigned int uclr_scl_stuck_det); +int iSetIC_SMBUS_CLK_LOW_SEXT_smbus_clk_low_sext_timeout(unsigned int usmbus_clk_low_sext_timeout); +int iSetIC_SMBUS_CLK_LOW_MEXT_smbus_clk_low_mext_timeout(unsigned int usmbus_clk_low_mext_timeout); +int iSetIC_SMBUS_THIGH_MAX_IDLE_COUNT_smbus_thigh_max_bus_idle_cnt(unsigned int usmbus_thigh_max_bus_idle_cnt); +int iSetIC_SMBUS_INTR_STAT_r_slv_clock_extnd_timeout(unsigned int ur_slv_clock_extnd_timeout); +int iSetIC_SMBUS_INTR_STAT_r_mst_clock_extnd_timeout(unsigned int ur_mst_clock_extnd_timeout); +int iSetIC_SMBUS_INTR_STAT_r_quick_cmd_det(unsigned int ur_quick_cmd_det); +int iSetIC_SMBUS_INTR_STAT_r_host_notify_mst_det(unsigned int ur_host_notify_mst_det); +int iSetIC_SMBUS_INTR_STAT_r_arp_prepare_cmd_det(unsigned int ur_arp_prepare_cmd_det); +int iSetIC_SMBUS_INTR_STAT_r_arp_rst_cmd_det(unsigned int ur_arp_rst_cmd_det); +int iSetIC_SMBUS_INTR_STAT_r_arp_get_udid_cmd_det(unsigned int ur_arp_get_udid_cmd_det); +int iSetIC_SMBUS_INTR_STAT_r_arp_assgn_addr_cmd_det(unsigned int ur_arp_assgn_addr_cmd_det); +int iSetIC_SMBUS_INTR_STAT_r_slv_rx_pec_nack(unsigned int ur_slv_rx_pec_nack); +int iSetIC_SMBUS_INTR_STAT_r_smbus_suspend_det(unsigned int ur_smbus_suspend_det); +int iSetIC_SMBUS_INTR_STAT_r_smbus_alert_det(unsigned int ur_smbus_alert_det); +int iSetIC_SMBUS_INTR_MASK_m_slv_clock_extnd_timeout(unsigned int um_slv_clock_extnd_timeout); +int iSetIC_SMBUS_INTR_MASK_m_mst_clock_extnd_timeout(unsigned int um_mst_clock_extnd_timeout); +int iSetIC_SMBUS_INTR_MASK_m_quick_cmd_det(unsigned int um_quick_cmd_det); +int iSetIC_SMBUS_INTR_MASK_m_host_notify_mst_det(unsigned int um_host_notify_mst_det); +int iSetIC_SMBUS_INTR_MASK_m_arp_prepare_cmd_det(unsigned int um_arp_prepare_cmd_det); +int iSetIC_SMBUS_INTR_MASK_m_arp_rst_cmd_det(unsigned int um_arp_rst_cmd_det); +int iSetIC_SMBUS_INTR_MASK_m_arp_get_udid_cmd_det(unsigned int um_arp_get_udid_cmd_det); +int iSetIC_SMBUS_INTR_MASK_m_arp_assgn_addr_cmd_det(unsigned int um_arp_assgn_addr_cmd_det); +int iSetIC_SMBUS_INTR_MASK_m_slv_rx_pec_nack(unsigned int um_slv_rx_pec_nack); +int iSetIC_SMBUS_INTR_MASK_m_smbus_suspend_det(unsigned int um_smbus_suspend_det); +int iSetIC_SMBUS_INTR_MASK_m_smbus_alert_det(unsigned int um_smbus_alert_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_slv_clock_extnd_timeout(unsigned int uri_slv_clock_extnd_timeout); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_mst_clock_extnd_timeout(unsigned int uri_mst_clock_extnd_timeout); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_quick_cmd_det(unsigned int uri_quick_cmd_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_host_notify_mst_det(unsigned int uri_host_notify_mst_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_arp_prepare_cmd_det(unsigned int uri_arp_prepare_cmd_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_arp_rst_cmd_det(unsigned int uri_arp_rst_cmd_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_arp_get_udid_cmd_det(unsigned int uri_arp_get_udid_cmd_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_arp_assgn_addr_cmd_det(unsigned int uri_arp_assgn_addr_cmd_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_slv_rx_pec_nack(unsigned int uri_slv_rx_pec_nack); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_smbus_suspend_det(unsigned int uri_smbus_suspend_det); +int iSetIC_SMBUS_RAW_INTR_STAT_ri_smbus_alert_det(unsigned int uri_smbus_alert_det); +int iSetIC_CLR_SMBUS_INTR_clr_slv_clock_extnd_timeout(unsigned int uclr_slv_clock_extnd_timeout); +int iSetIC_CLR_SMBUS_INTR_clr_mst_clock_extnd_timeout(unsigned int uclr_mst_clock_extnd_timeout); +int iSetIC_CLR_SMBUS_INTR_clr_quick_cmd_det(unsigned int uclr_quick_cmd_det); +int iSetIC_CLR_SMBUS_INTR_clr_host_notify_mst_det(unsigned int uclr_host_notify_mst_det); +int iSetIC_CLR_SMBUS_INTR_clr_arp_prepare_cmd_det(unsigned int uclr_arp_prepare_cmd_det); +int iSetIC_CLR_SMBUS_INTR_clr_arp_rst_cmd_det(unsigned int uclr_arp_rst_cmd_det); +int iSetIC_CLR_SMBUS_INTR_clr_arp_get_udid_cmd_det(unsigned int uclr_arp_get_udid_cmd_det); +int iSetIC_CLR_SMBUS_INTR_clr_arp_assgn_addr_cmd_det(unsigned int uclr_arp_assgn_addr_cmd_det); +int iSetIC_CLR_SMBUS_INTR_clr_slv_rx_pec_nack(unsigned int uclr_slv_rx_pec_nack); +int iSetIC_CLR_SMBUS_INTR_clr_smbus_suspend_det(unsigned int uclr_smbus_suspend_det); +int iSetIC_CLR_SMBUS_INTR_clr_smbus_alert_det(unsigned int uclr_smbus_alert_det); +int iSetIC_SMBUS_UDID_LSB_smbus_udid_lsb(unsigned int usmbus_udid_lsb); +int iSetIC_COMP_PARAM_1_apb_data_width(unsigned int uapb_data_width); +int iSetIC_COMP_PARAM_1_max_speed_mode(unsigned int umax_speed_mode); +int iSetIC_COMP_PARAM_1_hc_count_values(unsigned int uhc_count_values); +int iSetIC_COMP_PARAM_1_intr_io(unsigned int uintr_io); +int iSetIC_COMP_PARAM_1_has_dma(unsigned int uhas_dma); +int iSetIC_COMP_PARAM_1_add_encoded_params(unsigned int uadd_encoded_params); +int iSetIC_COMP_PARAM_1_rx_buffer_depth(unsigned int urx_buffer_depth); +int iSetIC_COMP_PARAM_1_tx_buffer_depth(unsigned int utx_buffer_depth); +int iSetIC_COMP_VERSION_ic_comp_version(unsigned int uic_comp_version); +int iSetIC_COMP_TYPE_ic_comp_type(unsigned int uic_comp_type); +int iSetIC_SMBUS_UDID_MSB0_ic_smbus_udid_msb0(unsigned int uic_smbus_udid_msb0); +int iSetIC_SMBUS_UDID_MSB1_ic_smbus_udid_msb1(unsigned int uic_smbus_udid_msb1); +int iSetIC_SMBUS_UDID_MSB2_ic_smbus_udid_msb2(unsigned int uic_smbus_udid_msb2); + +/* Define the union csr_shm_init_chk_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_mode : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_mode_u; + +/* Define the union csr_shm_init_chk_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_start : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_start_u; + +/* Define the union csr_shm_init_chk_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_done : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_stat_u; + +/* Define the union csr_shm_int_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sbit_err_int_stat : 1; /* [0] */ + u32 mbit_err_int_stat : 1; /* [1] */ + u32 addr_out_int_stat : 1; /* [2] */ + u32 eco_rsv0_int_stat : 1; /* [3] */ + u32 eco_rsv1_int_stat : 1; /* [4] */ + u32 rsv_3 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_int_stat_u; + +/* Define the union csr_shm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sbit_err_int_en : 1; /* [0] */ + u32 mbit_err_int_en : 1; /* [1] */ + u32 addr_out_int_en : 1; /* [2] */ + u32 eco_rsv0_int_en : 1; /* [3] */ + u32 eco_rsv1_int_en : 1; /* [4] */ + u32 rsv_4 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_int_en_u; + +/* Define the union csr_shm_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sbit_err_int_set : 1; /* [0] */ + u32 mbit_err_int_set : 1; /* [1] */ + u32 addr_out_int_set : 1; /* [2] */ + u32 eco_rsv0_int_set : 1; /* [3] */ + u32 eco_rsv1_int_set : 1; /* [4] */ + u32 rsv_5 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_int_set_u; + +/* Define the union csr_shm_raw_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sbit_err_raw_stat : 1; /* [0] */ + u32 mbit_err_raw_stat : 1; /* [1] */ + u32 addr_out_raw_stat : 1; /* [2] */ + u32 eco_rsv0_raw_stat : 1; /* [3] */ + u32 eco_rsv1_raw_stat : 1; /* [4] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_raw_stat_u; + +/* Define the union csr_shm_init_chk_saddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_start_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_saddr_u; + +/* Define the union csr_shm_init_chk_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_len : 19; /* [18:0] */ + u32 rsv_7 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_len_u; + +/* Define the union csr_shm_init_chk_ldata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_low_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_ldata_u; + +/* Define the union csr_shm_init_chk_hdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_high_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_hdata_u; + +/* Define the union csr_shm_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_bypass : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_ecc_bypass_u; + +/* Define the union csr_shm_ecc_insr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bank0_sb_err_insr : 1; /* [0] */ + u32 bank0_mb_err_insr : 1; /* [1] */ + u32 bank1_sb_err_insr : 1; /* [2] */ + u32 bank1_mb_err_insr : 1; /* [3] */ + u32 bank2_sb_err_insr : 1; /* [4] */ + u32 bank2_mb_err_insr : 1; /* [5] */ + u32 bank3_sb_err_insr : 1; /* [6] */ + u32 bank3_mb_err_insr : 1; /* [7] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_ecc_insr_u; + +/* Define the union csr_shm_ecc_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_autow : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_ecc_rst_u; + +/* Define the union csr_shm_pw_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ret1n : 1; /* [0] */ + u32 rsv_11 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_pw_mode_u; + +/* Define the union csr_shm_tmod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_ram_tmod : 7; /* [6:0] */ + u32 rsv_12 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_tmod_u; + +/* Define the union csr_shm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_slv_busy : 1; /* [0] */ + u32 axi_wburst_mode : 2; /* [2:1] */ + u32 axi_rburst_mode : 2; /* [4:3] */ + u32 rsv_13 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_status_u; + +/* Define the union csr_shm_init_chk_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_chk_err : 1; /* [0] */ + u32 addr_chk_err : 1; /* [1] */ + u32 rsv_14 : 1; /* [2] */ + u32 init_saddr_over : 1; /* [3] */ + u32 init_len_over : 1; /* [4] */ + u32 rsv_15 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_err_u; + +/* Define the union csr_shm_init_chk_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_err_addr : 22; /* [21:0] */ + u32 rsv_16 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_err_addr_u; + +/* Define the union csr_shm_init_chk_err_ldata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_err_ldata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_err_ldata_u; + +/* Define the union csr_shm_init_chk_err_hdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_chk_err_hdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_init_chk_err_hdata_u; + +/* Define the union csr_shm_serr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 single_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_serr_cnt_u; + +/* Define the union csr_shm_merr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 multi_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_merr_cnt_u; + +/* Define the union csr_shm_serr_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 serr_addr : 22; /* [21:0] */ + u32 serr_addr_vld : 1; /* [22] */ + u32 rsv_17 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_serr_addr_u; + +/* Define the union csr_shm_merr_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 merr_addr : 22; /* [21:0] */ + u32 merr_addr_vld : 1; /* [22] */ + u32 rsv_18 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_shm_merr_addr_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_shm_init_chk_mode_u shm_init_chk_mode; /* 0 */ + volatile csr_shm_init_chk_start_u shm_init_chk_start; /* 4 */ + volatile csr_shm_init_chk_stat_u shm_init_chk_stat; /* 8 */ + volatile csr_shm_int_stat_u shm_int_stat; /* 20 */ + volatile csr_shm_int_en_u shm_int_en; /* 30 */ + volatile csr_shm_int_set_u shm_int_set; /* 34 */ + volatile csr_shm_raw_stat_u shm_raw_stat; /* 38 */ + volatile csr_shm_init_chk_saddr_u shm_init_chk_saddr; /* A0 */ + volatile csr_shm_init_chk_len_u shm_init_chk_len; /* A4 */ + volatile csr_shm_init_chk_ldata_u shm_init_chk_ldata; /* A8 */ + volatile csr_shm_init_chk_hdata_u shm_init_chk_hdata; /* AC */ + volatile csr_shm_ecc_bypass_u shm_ecc_bypass; /* B0 */ + volatile csr_shm_ecc_insr_u shm_ecc_insr; /* B4 */ + volatile csr_shm_ecc_rst_u shm_ecc_rst; /* B8 */ + volatile csr_shm_pw_mode_u shm_pw_mode; /* BC */ + volatile csr_shm_tmod_u shm_tmod; /* C0 */ + volatile csr_shm_status_u shm_status; /* C4 */ + volatile csr_shm_init_chk_err_u shm_init_chk_err; /* C8 */ + volatile csr_shm_init_chk_err_addr_u shm_init_chk_err_addr; /* CC */ + volatile csr_shm_init_chk_err_ldata_u shm_init_chk_err_ldata; /* D0 */ + volatile csr_shm_init_chk_err_hdata_u shm_init_chk_err_hdata; /* D4 */ + volatile csr_shm_serr_cnt_u shm_serr_cnt; /* D8 */ + volatile csr_shm_merr_cnt_u shm_merr_cnt; /* DC */ + volatile csr_shm_serr_addr_u shm_serr_addr; /* F0 */ + volatile csr_shm_merr_addr_u shm_merr_addr; /* F4 */ +} S_shm_csr_REGS_TYPE; + +/* Declare the struct pointor of the module shm_csr */ +extern volatile S_shm_csr_REGS_TYPE *gopshm_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSHM_INIT_CHK_MODE_init_chk_mode(unsigned int uinit_chk_mode); +int iSetSHM_INIT_CHK_START_init_chk_start(unsigned int uinit_chk_start); +int iSetSHM_INIT_CHK_STAT_init_chk_done(unsigned int uinit_chk_done); +int iSetSHM_INT_STAT_sbit_err_int_stat(unsigned int usbit_err_int_stat); +int iSetSHM_INT_STAT_mbit_err_int_stat(unsigned int umbit_err_int_stat); +int iSetSHM_INT_STAT_addr_out_int_stat(unsigned int uaddr_out_int_stat); +int iSetSHM_INT_STAT_eco_rsv0_int_stat(unsigned int ueco_rsv0_int_stat); +int iSetSHM_INT_STAT_eco_rsv1_int_stat(unsigned int ueco_rsv1_int_stat); +int iSetSHM_INT_EN_sbit_err_int_en(unsigned int usbit_err_int_en); +int iSetSHM_INT_EN_mbit_err_int_en(unsigned int umbit_err_int_en); +int iSetSHM_INT_EN_addr_out_int_en(unsigned int uaddr_out_int_en); +int iSetSHM_INT_EN_eco_rsv0_int_en(unsigned int ueco_rsv0_int_en); +int iSetSHM_INT_EN_eco_rsv1_int_en(unsigned int ueco_rsv1_int_en); +int iSetSHM_INT_SET_sbit_err_int_set(unsigned int usbit_err_int_set); +int iSetSHM_INT_SET_mbit_err_int_set(unsigned int umbit_err_int_set); +int iSetSHM_INT_SET_addr_out_int_set(unsigned int uaddr_out_int_set); +int iSetSHM_INT_SET_eco_rsv0_int_set(unsigned int ueco_rsv0_int_set); +int iSetSHM_INT_SET_eco_rsv1_int_set(unsigned int ueco_rsv1_int_set); +int iSetSHM_RAW_STAT_sbit_err_raw_stat(unsigned int usbit_err_raw_stat); +int iSetSHM_RAW_STAT_mbit_err_raw_stat(unsigned int umbit_err_raw_stat); +int iSetSHM_RAW_STAT_addr_out_raw_stat(unsigned int uaddr_out_raw_stat); +int iSetSHM_RAW_STAT_eco_rsv0_raw_stat(unsigned int ueco_rsv0_raw_stat); +int iSetSHM_RAW_STAT_eco_rsv1_raw_stat(unsigned int ueco_rsv1_raw_stat); +int iSetSHM_INIT_CHK_SADDR_init_chk_start_addr(unsigned int uinit_chk_start_addr); +int iSetSHM_INIT_CHK_LEN_init_chk_len(unsigned int uinit_chk_len); +int iSetSHM_INIT_CHK_LDATA_init_chk_low_data(unsigned int uinit_chk_low_data); +int iSetSHM_INIT_CHK_HDATA_init_chk_high_data(unsigned int uinit_chk_high_data); +int iSetSHM_ECC_BYPASS_ecc_bypass(unsigned int uecc_bypass); +int iSetSHM_ECC_INSR_bank0_sb_err_insr(unsigned int ubank0_sb_err_insr); +int iSetSHM_ECC_INSR_bank0_mb_err_insr(unsigned int ubank0_mb_err_insr); +int iSetSHM_ECC_INSR_bank1_sb_err_insr(unsigned int ubank1_sb_err_insr); +int iSetSHM_ECC_INSR_bank1_mb_err_insr(unsigned int ubank1_mb_err_insr); +int iSetSHM_ECC_INSR_bank2_sb_err_insr(unsigned int ubank2_sb_err_insr); +int iSetSHM_ECC_INSR_bank2_mb_err_insr(unsigned int ubank2_mb_err_insr); +int iSetSHM_ECC_INSR_bank3_sb_err_insr(unsigned int ubank3_sb_err_insr); +int iSetSHM_ECC_INSR_bank3_mb_err_insr(unsigned int ubank3_mb_err_insr); +int iSetSHM_ECC_RST_ecc_autow(unsigned int uecc_autow); +int iSetSHM_PW_MODE_ram_ret1n(unsigned int uram_ret1n); +int iSetSHM_TMOD_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSHM_STATUS_axi_slv_busy(unsigned int uaxi_slv_busy); +int iSetSHM_STATUS_axi_wburst_mode(unsigned int uaxi_wburst_mode); +int iSetSHM_STATUS_axi_rburst_mode(unsigned int uaxi_rburst_mode); +int iSetSHM_INIT_CHK_ERR_data_chk_err(unsigned int udata_chk_err); +int iSetSHM_INIT_CHK_ERR_addr_chk_err(unsigned int uaddr_chk_err); +int iSetSHM_INIT_CHK_ERR_init_saddr_over(unsigned int uinit_saddr_over); +int iSetSHM_INIT_CHK_ERR_init_len_over(unsigned int uinit_len_over); +int iSetSHM_INIT_CHK_ERR_ADDR_init_chk_err_addr(unsigned int uinit_chk_err_addr); +int iSetSHM_INIT_CHK_ERR_LDATA_init_chk_err_ldata(unsigned int uinit_chk_err_ldata); +int iSetSHM_INIT_CHK_ERR_HDATA_init_chk_err_hdata(unsigned int uinit_chk_err_hdata); +int iSetSHM_SERR_CNT_single_err_cnt(unsigned int usingle_err_cnt); +int iSetSHM_MERR_CNT_multi_err_cnt(unsigned int umulti_err_cnt); +int iSetSHM_SERR_ADDR_serr_addr(unsigned int userr_addr); +int iSetSHM_SERR_ADDR_serr_addr_vld(unsigned int userr_addr_vld); +int iSetSHM_MERR_ADDR_merr_addr(unsigned int umerr_addr); +int iSetSHM_MERR_ADDR_merr_addr_vld(unsigned int umerr_addr_vld); + +/* Define the union csr_eco_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_rsvd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eco_rsvd_u; + +/* Define the union csr_pie_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_oq2up_cvg_raw_status : 1; /* [0] */ + u32 sgl_cvg_raw_status : 1; /* [1] */ + u32 rsv_0 : 4; /* [5:2] */ + u32 bm_fifo_ful_raw_status : 1; /* [6] */ + u32 oq_eccm_raw_status : 1; /* [7] */ + u32 oq_eccs_raw_status : 1; /* [8] */ + u32 tx_parity_raw_status : 1; /* [9] */ + u32 rx_parity_raw_status : 1; /* [10] */ + u32 bd_oq2ipsu_ful_raw_status : 1; /* [11] */ + u32 bd_oq2ncsi_ful_raw_status : 1; /* [12] */ + u32 bd_oq2up_ful_raw_status : 1; /* [13] */ + u32 tx_ucerr_raw_status : 1; /* [14] */ + u32 rx_ucerr_raw_status : 1; /* [15] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pie_int_raw_status_u; + +/* Define the union csr_pie_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_oq2up_cvg_en : 1; /* [0] */ + u32 sgl_cvg_en : 1; /* [1] */ + u32 rsv_2 : 4; /* [5:2] */ + u32 bm_fifo_ful_en : 1; /* [6] */ + u32 oq_eccm_en : 1; /* [7] */ + u32 oq_eccs_en : 1; /* [8] */ + u32 tx_parity_en : 1; /* [9] */ + u32 rx_parity_en : 1; /* [10] */ + u32 bd_oq2ipsu_ful_en : 1; /* [11] */ + u32 bd_oq2ncsi_ful_en : 1; /* [12] */ + u32 bd_oq2up_ful_en : 1; /* [13] */ + u32 tx_ucerr_en : 1; /* [14] */ + u32 rx_ucerr_en : 1; /* [15] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pie_int_en_u; + +/* Define the union csr_pie_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_oq2up_cvg_set : 1; /* [0] */ + u32 sgl_cvg_set : 1; /* [1] */ + u32 rsv_4 : 4; /* [5:2] */ + u32 bm_fifo_ful_set : 1; /* [6] */ + u32 oq_eccm_set : 1; /* [7] */ + u32 oq_eccs_set : 1; /* [8] */ + u32 tx_parity_set : 1; /* [9] */ + u32 rx_parity_set : 1; /* [10] */ + u32 bd_oq2ipsu_ful_set : 1; /* [11] */ + u32 bd_oq2ncsi_ful_set : 1; /* [12] */ + u32 bd_oq2up_ful_set : 1; /* [13] */ + u32 tx_ucerr_set : 1; /* [14] */ + u32 rx_ucerr_set : 1; /* [15] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pie_int_set_u; + +/* Define the union csr_pie_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_oq2up_cvg_int_status : 1; /* [0] */ + u32 sgl_cvg_int_status : 1; /* [1] */ + u32 rsv_6 : 4; /* [5:2] */ + u32 bm_fifo_ful_int_status : 1; /* [6] */ + u32 oq_eccm_int_status : 1; /* [7] */ + u32 oq_eccs_int_status : 1; /* [8] */ + u32 tx_parity_int_status : 1; /* [9] */ + u32 rx_parity_int_status : 1; /* [10] */ + u32 bd_oq2ipsu_ful_int_status : 1; /* [11] */ + u32 bd_oq2ncsi_ful_int_status : 1; /* [12] */ + u32 bd_oq2up_ful_int_status : 1; /* [13] */ + u32 tx_ucerr_int_status : 1; /* [14] */ + u32 rx_ucerr_int_status : 1; /* [15] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pie_int_status_u; + +/* Define the union csr_csr_pool_fun_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo0_fun : 3; /* [2:0] */ + u32 rsv_8 : 1; /* [3] */ + u32 fifo1_fun : 3; /* [6:4] */ + u32 rsv_9 : 1; /* [7] */ + u32 fifo2_fun : 3; /* [10:8] */ + u32 rsv_10 : 1; /* [11] */ + u32 fifo3_fun : 3; /* [14:12] */ + u32 rsv_11 : 1; /* [15] */ + u32 fifo4_fun : 3; /* [18:16] */ + u32 rsv_12 : 1; /* [19] */ + u32 fifo5_fun : 3; /* [22:20] */ + u32 rsv_13 : 1; /* [23] */ + u32 fifo6_fun : 3; /* [26:24] */ + u32 rsv_14 : 1; /* [27] */ + u32 fifo7_fun : 3; /* [30:28] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_pool_fun_u; + +/* Define the union csr_csr_pool_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo4_depth : 7; /* [6:0] */ + u32 rsv_16 : 1; /* [7] */ + u32 fifo5_depth : 7; /* [14:8] */ + u32 rsv_17 : 1; /* [15] */ + u32 fifo6_depth : 7; /* [22:16] */ + u32 rsv_18 : 1; /* [23] */ + u32 fifo7_depth : 7; /* [30:24] */ + u32 rsv_19 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_pool_depth0_u; + +/* Define the union csr_csr_pool_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo0_depth : 7; /* [6:0] */ + u32 rsv_20 : 1; /* [7] */ + u32 fifo1_depth : 7; /* [14:8] */ + u32 rsv_21 : 1; /* [15] */ + u32 fifo2_depth : 7; /* [22:16] */ + u32 rsv_22 : 1; /* [23] */ + u32 fifo3_depth : 7; /* [30:24] */ + u32 rsv_23 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_pool_depth1_u; + +/* Define the union csr_csr_pt_pkt_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pt_pkt_type : 5; /* [4:0] */ + u32 rsv_24 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_pt_pkt_type_u; + +/* Define the union csr_max_frame_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_frame_len : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_max_frame_len_u; + +/* Define the union csr_min_frame_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 min_frame_len : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_min_frame_len_u; + +/* Define the union csr_csr_peif_fun_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_27 : 4; /* [3:0] */ + u32 peif_rbd_delay : 6; /* [9:4] */ + u32 rsv_28 : 3; /* [12:10] */ + u32 csr_peif_unsop_err : 1; /* [13] */ + u32 csr_peif_uneop_err : 1; /* [14] */ + u32 peif_fifo_gap : 5; /* [19:15] */ + u32 rsv_29 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_peif_fun_u; + +/* Define the union csr_csr_qm_fun_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iq_fifo_gap : 3; /* [2:0] */ + u32 rsv_30 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_qm_fun_u; + +/* Define the union csr_dma_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_otd_cnt : 2; /* [1:0] */ + u32 rsv_31 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_otd_cnt_u; + +/* Define the union csr_csr_txbd_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbd_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_txbd_addr_u; + +/* Define the union csr_csr_bd2up_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_int_th : 3; /* [2:0] */ + u32 rsv_32 : 13; /* [15:3] */ + u32 bd_int_timeout : 8; /* [23:16] */ + u32 rsv_33 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd2up_time_u; + +/* Define the union csr_csr_sgl_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sgl_int_th : 3; /* [2:0] */ + u32 rsv_34 : 13; /* [15:3] */ + u32 sgl_int_timeout : 8; /* [23:16] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_sgl_time_u; + +/* Define the union csr_csr_mem_tmod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_ram_tmod : 7; /* [6:0] */ + u32 rsv_36 : 1; /* [7] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_mem_tmod_u; + +/* Define the union csr_csr_mem_dft_power_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_power_mode : 6; /* [5:0] */ + u32 rsv_38 : 2; /* [7:6] */ + u32 ret1n : 1; /* [8] */ + u32 rsv_39 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_mem_dft_power_u; + +/* Define the union csr_csr_bd_if0_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if0_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if0_wrd0_u; + +/* Define the union csr_csr_bd_if0_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if0_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if0_wrd1_u; + +/* Define the union csr_csr_bd_if0_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if0_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if0_wrd2_u; + +/* Define the union csr_csr_bd_if0_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if0_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if0_wrd3_u; + +/* Define the union csr_csr_bd_if1_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if1_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if1_wrd0_u; + +/* Define the union csr_csr_bd_if1_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if1_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if1_wrd1_u; + +/* Define the union csr_csr_bd_if1_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if1_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if1_wrd2_u; + +/* Define the union csr_csr_bd_if1_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if1_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if1_wrd3_u; + +/* Define the union csr_csr_bd_if2_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if2_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if2_wrd0_u; + +/* Define the union csr_csr_bd_if2_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if2_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if2_wrd1_u; + +/* Define the union csr_csr_bd_if2_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if2_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if2_wrd2_u; + +/* Define the union csr_csr_bd_if2_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if2_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if2_wrd3_u; + +/* Define the union csr_csr_bd_if3_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if3_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if3_wrd0_u; + +/* Define the union csr_csr_bd_if3_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if3_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if3_wrd1_u; + +/* Define the union csr_csr_bd_if3_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if3_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if3_wrd2_u; + +/* Define the union csr_csr_bd_if3_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if3_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if3_wrd3_u; + +/* Define the union csr_csr_bd_if4_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if4_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if4_wrd0_u; + +/* Define the union csr_csr_bd_if4_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if4_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if4_wrd1_u; + +/* Define the union csr_csr_bd_if4_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if4_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if4_wrd2_u; + +/* Define the union csr_csr_bd_if4_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if4_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if4_wrd3_u; + +/* Define the union csr_csr_bd_if5_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if5_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if5_wrd0_u; + +/* Define the union csr_csr_bd_if5_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if5_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if5_wrd1_u; + +/* Define the union csr_csr_bd_if5_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if5_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if5_wrd2_u; + +/* Define the union csr_csr_bd_if5_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if5_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if5_wrd3_u; + +/* Define the union csr_csr_bd_if6_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if6_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if6_wrd0_u; + +/* Define the union csr_csr_bd_if6_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if6_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if6_wrd1_u; + +/* Define the union csr_csr_bd_if6_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if6_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if6_wrd2_u; + +/* Define the union csr_csr_bd_if6_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if6_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if6_wrd3_u; + +/* Define the union csr_csr_bd_if7_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if7_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if7_wrd0_u; + +/* Define the union csr_csr_bd_if7_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if7_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if7_wrd1_u; + +/* Define the union csr_csr_bd_if7_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if7_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if7_wrd2_u; + +/* Define the union csr_csr_bd_if7_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bd_if7_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_bd_if7_wrd3_u; + +/* Define the union csr_rls_bd_if0_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if0_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if0_wrd0_u; + +/* Define the union csr_rls_bd_if0_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if0_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if0_wrd1_u; + +/* Define the union csr_rls_bd_if0_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if0_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if0_wrd2_u; + +/* Define the union csr_rls_bd_if0_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if0_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if0_wrd3_u; + +/* Define the union csr_rls_bd_if1_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if1_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if1_wrd0_u; + +/* Define the union csr_rls_bd_if1_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if1_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if1_wrd1_u; + +/* Define the union csr_rls_bd_if1_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if1_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if1_wrd2_u; + +/* Define the union csr_rls_bd_if1_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rls_bd_if1_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rls_bd_if1_wrd3_u; + +/* Define the union csr_add_bd_if0_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if0_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if0_wrd0_u; + +/* Define the union csr_add_bd_if0_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if0_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if0_wrd1_u; + +/* Define the union csr_add_bd_if0_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if0_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if0_wrd2_u; + +/* Define the union csr_add_bd_if0_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if0_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if0_wrd3_u; + +/* Define the union csr_add_bd_if1_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if1_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if1_wrd0_u; + +/* Define the union csr_add_bd_if1_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if1_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if1_wrd1_u; + +/* Define the union csr_add_bd_if1_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if1_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if1_wrd2_u; + +/* Define the union csr_add_bd_if1_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 add_bd_if1_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_add_bd_if1_wrd3_u; + +/* Define the union csr_oq2up_bd_if_wrd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq2up_bd_if_wrd0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq2up_bd_if_wrd0_u; + +/* Define the union csr_oq2up_bd_if_wrd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq2up_bd_if_wrd1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq2up_bd_if_wrd1_u; + +/* Define the union csr_oq2up_bd_if_wrd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq2up_bd_if_wrd2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq2up_bd_if_wrd2_u; + +/* Define the union csr_oq2up_bd_if_wrd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq2up_bd_if_wrd3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq2up_bd_if_wrd3_u; + +/* Define the union csr_csr_axi_msr_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_cnt_wr_acc_clr : 1; /* [0] */ + u32 axi_cnt_rd_acc_clr : 1; /* [1] */ + u32 axi_cnt_wr_latency_clr : 1; /* [2] */ + u32 axi_cnt_rd_latency_clr : 1; /* [3] */ + u32 rsv_40 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_csr_axi_msr_inf_u; + +/* Define the union csr_bd_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_reg_err : 1; /* [0] */ + u32 csr_2pe_err : 1; /* [1] */ + u32 csr_npe_err : 1; /* [2] */ + u32 csr_ovflw_err : 1; /* [3] */ + u32 rsv_41 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bd_err_status_u; + +/* Define the union csr_bm_read0_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read0_cnt_u; + +/* Define the union csr_bm_read1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read1_cnt_u; + +/* Define the union csr_bm_read2_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read2_cnt_u; + +/* Define the union csr_bm_read3_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read3_cnt_u; + +/* Define the union csr_bm_read4_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read4_cnt_u; + +/* Define the union csr_bm_read5_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read5_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read5_cnt_u; + +/* Define the union csr_bm_read6_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read6_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read6_cnt_u; + +/* Define the union csr_bm_read7_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read7_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read7_cnt_u; + +/* Define the union csr_bm_write0_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write0_cnt_u; + +/* Define the union csr_bm_write1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write1_cnt_u; + +/* Define the union csr_bm_write2_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write2_cnt_u; + +/* Define the union csr_bm_write3_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write3_cnt_u; + +/* Define the union csr_bm_write4_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write4_cnt_u; + +/* Define the union csr_bm_write5_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write5_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write5_cnt_u; + +/* Define the union csr_bm_write6_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write6_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write6_cnt_u; + +/* Define the union csr_bm_write7_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_write7_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_write7_cnt_u; + +/* Define the union csr_bm_fifo0x1_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_fifo0_cnt : 8; /* [7:0] */ + u32 bm_fifo0_ful : 1; /* [8] */ + u32 bm_fifo0_ept : 1; /* [9] */ + u32 rsv_42 : 6; /* [15:10] */ + u32 bm_fifo1_cnt : 8; /* [23:16] */ + u32 bm_fifo1_ful : 1; /* [24] */ + u32 bm_fifo1_ept : 1; /* [25] */ + u32 rsv_43 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_fifo0x1_status_u; + +/* Define the union csr_bm_fifo2x3_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_fifo2_cnt : 8; /* [7:0] */ + u32 bm_fifo2_ful : 1; /* [8] */ + u32 bm_fifo2_ept : 1; /* [9] */ + u32 rsv_44 : 6; /* [15:10] */ + u32 bm_fifo3_cnt : 8; /* [23:16] */ + u32 bm_fifo3_ful : 1; /* [24] */ + u32 bm_fifo3_ept : 1; /* [25] */ + u32 rsv_45 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_fifo2x3_status_u; + +/* Define the union csr_bm_fifo4x5_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_fifo4_cnt : 8; /* [7:0] */ + u32 bm_fifo4_ful : 1; /* [8] */ + u32 bm_fifo4_ept : 1; /* [9] */ + u32 rsv_46 : 6; /* [15:10] */ + u32 bm_fifo5_cnt : 8; /* [23:16] */ + u32 bm_fifo5_ful : 1; /* [24] */ + u32 bm_fifo5_ept : 1; /* [25] */ + u32 rsv_47 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_fifo4x5_status_u; + +/* Define the union csr_bm_fifo6x7_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_fifo6_cnt : 8; /* [7:0] */ + u32 bm_fifo6_ful : 1; /* [8] */ + u32 bm_fifo6_ept : 1; /* [9] */ + u32 rsv_48 : 6; /* [15:10] */ + u32 bm_fifo7_cnt : 8; /* [23:16] */ + u32 bm_fifo7_ful : 1; /* [24] */ + u32 bm_fifo7_ept : 1; /* [25] */ + u32 rsv_49 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_fifo6x7_status_u; + +/* Define the union csr_bm_read0_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read0_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read0_emp_cnt_u; + +/* Define the union csr_bm_read1_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read1_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read1_emp_cnt_u; + +/* Define the union csr_bm_read2_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read2_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read2_emp_cnt_u; + +/* Define the union csr_bm_read3_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read3_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read3_emp_cnt_u; + +/* Define the union csr_bm_read4_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read4_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read4_emp_cnt_u; + +/* Define the union csr_bm_read5_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read5_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read5_emp_cnt_u; + +/* Define the union csr_bm_read6_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read6_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read6_emp_cnt_u; + +/* Define the union csr_bm_read7_emp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read7_emp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read7_emp_cnt_u; + +/* Define the union csr_rx_pkt_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_size_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_pkt_status_u; + +/* Define the union csr_ncsi_bpr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ncsi_bpr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ncsi_bpr_cnt_u; + +/* Define the union csr_iq_bd_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iq_bd_cnt : 4; /* [3:0] */ + u32 iq_bd_ful : 1; /* [4] */ + u32 iq_bd_ept : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iq_bd_status_u; + +/* Define the union csr_oq_bd2up_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_bd2up_cnt : 4; /* [3:0] */ + u32 oq_bd2up_ful : 1; /* [4] */ + u32 oq_bd2up_ept : 1; /* [5] */ + u32 rsv_51 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_bd2up_status_u; + +/* Define the union csr_oq_bd2ncsi_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_bd2ncsi_cnt : 4; /* [3:0] */ + u32 oq_bd2ncsi_ful : 1; /* [4] */ + u32 oq_bd2ncsi_ept : 1; /* [5] */ + u32 rsv_52 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_bd2ncsi_status_u; + +/* Define the union csr_oq_bd2ipsu_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_bd2ipsu_cnt : 4; /* [3:0] */ + u32 oq_bd2ipsu_ful : 1; /* [4] */ + u32 oq_bd2ipsu_ept : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_bd2ipsu_status_u; + +/* Define the union csr_out2up_bd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 out2up_bd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_out2up_bd_cnt_u; + +/* Define the union csr_out2ipsu_bd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 out2ipsu_bd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_out2ipsu_bd_cnt_u; + +/* Define the union csr_out2ncsi_bd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 out2ncsi_bd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_out2ncsi_bd_cnt_u; + +/* Define the union csr_oq_eccs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_eccs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_eccs_cnt_u; + +/* Define the union csr_oq_eccm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_eccm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_eccm_cnt_u; + +/* Define the union csr_axi_rd_latency_avg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_latency_avg_cnt : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rd_latency_avg_cnt_u; + +/* Define the union csr_axi_wr_latency_avg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_latency_avg_cnt : 16; /* [15:0] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_wr_latency_avg_cnt_u; + +/* Define the union csr_axi_rd_latency_max_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_latency_max_cnt : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rd_latency_max_cnt_u; + +/* Define the union csr_axi_wr_latency_max_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_latency_max_cnt : 16; /* [15:0] */ + u32 rsv_57 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_wr_latency_max_cnt_u; + +/* Define the union csr_axi_rd_acc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_rd_acc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rd_acc_cnt_u; + +/* Define the union csr_axi_wr_acc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_acc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_wr_acc_cnt_u; + +/* Define the union csr_axi_rd_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axiwr_bresp_err : 1; /* [0] */ + u32 axird_bresp_err : 1; /* [1] */ + u32 rsv_58 : 2; /* [3:2] */ + u32 axi_rd_otd_cnt : 24; /* [27:4] */ + u32 rsv_59 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_rd_otd_cnt_u; + +/* Define the union csr_axi_wr_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axi_wr_otd_cnt : 24; /* [23:0] */ + u32 rsv_60 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_axi_wr_otd_cnt_u; + +/* Define the union csr_txdma_dat_ff_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_fifo_alempt_gap : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 dat_fifo_aful_gap : 6; /* [13:8] */ + u32 rsv_62 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txdma_dat_ff_th_u; + +/* Define the union csr_txdma_dat_ff_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_fifo_alempt_ff : 1; /* [0] */ + u32 dat_fifo_empt_ff : 1; /* [1] */ + u32 dat_fifo_aful_ff : 1; /* [2] */ + u32 dat_fifo_ful_ff : 1; /* [3] */ + u32 dat_fifo_underflow_ff : 1; /* [4] */ + u32 dat_fifo_overflow_ff : 1; /* [5] */ + u32 rsv_63 : 2; /* [7:6] */ + u32 dat_fifo_cnt_ff : 7; /* [14:8] */ + u32 rsv_64 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txdma_dat_ff_sta_u; + +/* Define the union csr_txdma_inf_ff_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inf_fifo_alempt_gap : 6; /* [5:0] */ + u32 rsv_65 : 2; /* [7:6] */ + u32 inf_fifo_aful_gap : 6; /* [13:8] */ + u32 rsv_66 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txdma_inf_ff_th_u; + +/* Define the union csr_txdma_inf_ff_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inf_fifo_alempt_ff : 1; /* [0] */ + u32 inf_fifo_empt_ff : 1; /* [1] */ + u32 inf_fifo_aful_ff : 1; /* [2] */ + u32 inf_fifo_ful_ff : 1; /* [3] */ + u32 inf_fifo_underflow_ff : 1; /* [4] */ + u32 inf_fifo_overflow_ff : 1; /* [5] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 inf_fifo_cnt_ff : 7; /* [14:8] */ + u32 rsv_68 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txdma_inf_ff_sta_u; + +/* Define the union csr_ipsuif_ff_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsuif_fifo_alempt_th : 4; /* [3:0] */ + u32 ipsuif_fifo_afull_th : 4; /* [7:4] */ + u32 rsv_69 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsuif_ff_th_u; + +/* Define the union csr_ipsuif_ff_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsuif_fifo_alempt : 1; /* [0] */ + u32 ipsuif_fifo_empt : 1; /* [1] */ + u32 ipsuif_fifo_aful : 1; /* [2] */ + u32 ipsuif_fifo_full : 1; /* [3] */ + u32 ipsuif_fifo_overflow : 1; /* [4] */ + u32 rsv_70 : 3; /* [7:5] */ + u32 ipsuif_fifo_wfifo_cnt : 5; /* [12:8] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsuif_ff_sta_u; + +/* Define the union csr_bm_read0_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read0_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read0_ful_cnt_u; + +/* Define the union csr_bm_read1_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read1_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read1_ful_cnt_u; + +/* Define the union csr_bm_read2_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read2_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read2_ful_cnt_u; + +/* Define the union csr_bm_read3_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read3_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read3_ful_cnt_u; + +/* Define the union csr_bm_read4_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read4_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read4_ful_cnt_u; + +/* Define the union csr_bm_read5_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read5_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read5_ful_cnt_u; + +/* Define the union csr_bm_read6_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read6_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read6_ful_cnt_u; + +/* Define the union csr_bm_read7_ful_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bm_read7_ful_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bm_read7_ful_cnt_u; + +/* Define the union csr_rx_parity_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxdma_parity_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_parity_err_cnt_u; + +/* Define the union csr_tx_parity_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txdma_parity_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_parity_err_cnt_u; + +/* Define the union csr_tx_minlen_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txdma_minlen_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_minlen_err_cnt_u; + +/* Define the union csr_tx_bdsize_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txdma_bdsize_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_bdsize_err_cnt_u; + +/* Define the union csr_tx_bdcode_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txdma_bdcode_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_bdcode_err_cnt_u; + +/* Define the union csr_tx_sgl_ci_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sgl_ci_th : 6; /* [5:0] */ + u32 rsv_72 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_sgl_ci_th_u; + +/* Define the union csr_tx_sgl_ci_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sgl_ci_cnt : 6; /* [5:0] */ + u32 rsv_73 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_sgl_ci_cnt_u; + +/* Define the union csr_qm_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qm_ecc_err_addr : 6; /* [5:0] */ + u32 rsv_74 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qm_ecc_err_addr_u; + +/* Define the union csr_pie_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qm_ecc_bypass : 1; /* [0] */ + u32 rsv_75 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pie_ecc_bypass_u; + +/* Define the union csr_peif_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 peif_fifo_aful : 1; /* [0] */ + u32 peif_fifo_full : 1; /* [1] */ + u32 peif_fifo_oflow : 1; /* [2] */ + u32 rsv_76 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_peif_fifo_sta_u; + +/* Define the union csr_qm_ram_ecc_insr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qm_ram_cerr_insr : 1; /* [0] */ + u32 qm_ram_ucerr_insr : 1; /* [1] */ + u32 rsv_77 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qm_ram_ecc_insr_u; + +/* Define the union csr_pie_initial_end_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 peif_prefetch_start : 1; /* [0] */ + u32 rsv_78 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pie_initial_end_u; + +/* Define the union csr_tx_rx_ram_ecc_insr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ram_cerr_insr : 1; /* [0] */ + u32 tx_ram_ucerr_insr : 1; /* [1] */ + u32 rx_ram_cerr_insr : 1; /* [2] */ + u32 rx_ram_ucerr_insr : 1; /* [3] */ + u32 rsv_79 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_rx_ram_ecc_insr_u; + +/* Define the union csr_rx_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cerr_cnt_u; + +/* Define the union csr_rx_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_ucerr_cnt_u; + +/* Define the union csr_tx_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_cerr_cnt_u; + +/* Define the union csr_tx_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_ucerr_cnt_u; + +/* Define the union csr_rx_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxdma_ecc_err_addr : 6; /* [5:0] */ + u32 rsv_80 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_ecc_err_addr_u; + +/* Define the union csr_tx_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txdma_ecc_err_addr : 6; /* [5:0] */ + u32 rsv_81 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_ecc_err_addr_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_eco_rsvd_u eco_rsvd; /* 0 */ + volatile csr_pie_int_raw_status_u pie_int_raw_status; /* 10 */ + volatile csr_pie_int_en_u pie_int_en; /* 20 */ + volatile csr_pie_int_set_u pie_int_set; /* 30 */ + volatile csr_pie_int_status_u pie_int_status; /* 40 */ + volatile csr_csr_pool_fun_u csr_pool_fun; /* A0 */ + volatile csr_csr_pool_depth0_u csr_pool_depth0; /* A4 */ + volatile csr_csr_pool_depth1_u csr_pool_depth1; /* A8 */ + volatile csr_csr_pt_pkt_type_u csr_pt_pkt_type; /* AC */ + volatile csr_max_frame_len_u max_frame_len; /* B0 */ + volatile csr_min_frame_len_u min_frame_len; /* B4 */ + volatile csr_csr_peif_fun_u csr_peif_fun; /* B8 */ + volatile csr_csr_qm_fun_u csr_qm_fun; /* BC */ + volatile csr_dma_otd_cnt_u dma_otd_cnt; /* C0 */ + volatile csr_csr_txbd_addr_u csr_txbd_addr; /* C4 */ + volatile csr_csr_bd2up_time_u csr_bd2up_time; /* C8 */ + volatile csr_csr_sgl_time_u csr_sgl_time; /* CC */ + volatile csr_csr_mem_tmod_u csr_mem_tmod; /* D0 */ + volatile csr_csr_mem_dft_power_u csr_mem_dft_power; /* D4 */ + volatile csr_csr_bd_if0_wrd0_u csr_bd_if0_wrd0; /* 100 */ + volatile csr_csr_bd_if0_wrd1_u csr_bd_if0_wrd1; /* 104 */ + volatile csr_csr_bd_if0_wrd2_u csr_bd_if0_wrd2; /* 108 */ + volatile csr_csr_bd_if0_wrd3_u csr_bd_if0_wrd3; /* 10C */ + volatile csr_csr_bd_if1_wrd0_u csr_bd_if1_wrd0; /* 110 */ + volatile csr_csr_bd_if1_wrd1_u csr_bd_if1_wrd1; /* 114 */ + volatile csr_csr_bd_if1_wrd2_u csr_bd_if1_wrd2; /* 118 */ + volatile csr_csr_bd_if1_wrd3_u csr_bd_if1_wrd3; /* 11C */ + volatile csr_csr_bd_if2_wrd0_u csr_bd_if2_wrd0; /* 120 */ + volatile csr_csr_bd_if2_wrd1_u csr_bd_if2_wrd1; /* 124 */ + volatile csr_csr_bd_if2_wrd2_u csr_bd_if2_wrd2; /* 128 */ + volatile csr_csr_bd_if2_wrd3_u csr_bd_if2_wrd3; /* 12C */ + volatile csr_csr_bd_if3_wrd0_u csr_bd_if3_wrd0; /* 130 */ + volatile csr_csr_bd_if3_wrd1_u csr_bd_if3_wrd1; /* 134 */ + volatile csr_csr_bd_if3_wrd2_u csr_bd_if3_wrd2; /* 138 */ + volatile csr_csr_bd_if3_wrd3_u csr_bd_if3_wrd3; /* 13C */ + volatile csr_csr_bd_if4_wrd0_u csr_bd_if4_wrd0; /* 140 */ + volatile csr_csr_bd_if4_wrd1_u csr_bd_if4_wrd1; /* 144 */ + volatile csr_csr_bd_if4_wrd2_u csr_bd_if4_wrd2; /* 148 */ + volatile csr_csr_bd_if4_wrd3_u csr_bd_if4_wrd3; /* 14C */ + volatile csr_csr_bd_if5_wrd0_u csr_bd_if5_wrd0; /* 150 */ + volatile csr_csr_bd_if5_wrd1_u csr_bd_if5_wrd1; /* 154 */ + volatile csr_csr_bd_if5_wrd2_u csr_bd_if5_wrd2; /* 158 */ + volatile csr_csr_bd_if5_wrd3_u csr_bd_if5_wrd3; /* 15C */ + volatile csr_csr_bd_if6_wrd0_u csr_bd_if6_wrd0; /* 160 */ + volatile csr_csr_bd_if6_wrd1_u csr_bd_if6_wrd1; /* 164 */ + volatile csr_csr_bd_if6_wrd2_u csr_bd_if6_wrd2; /* 168 */ + volatile csr_csr_bd_if6_wrd3_u csr_bd_if6_wrd3; /* 16C */ + volatile csr_csr_bd_if7_wrd0_u csr_bd_if7_wrd0; /* 170 */ + volatile csr_csr_bd_if7_wrd1_u csr_bd_if7_wrd1; /* 174 */ + volatile csr_csr_bd_if7_wrd2_u csr_bd_if7_wrd2; /* 178 */ + volatile csr_csr_bd_if7_wrd3_u csr_bd_if7_wrd3; /* 17C */ + volatile csr_rls_bd_if0_wrd0_u rls_bd_if0_wrd0; /* 180 */ + volatile csr_rls_bd_if0_wrd1_u rls_bd_if0_wrd1; /* 184 */ + volatile csr_rls_bd_if0_wrd2_u rls_bd_if0_wrd2; /* 188 */ + volatile csr_rls_bd_if0_wrd3_u rls_bd_if0_wrd3; /* 18C */ + volatile csr_rls_bd_if1_wrd0_u rls_bd_if1_wrd0; /* 190 */ + volatile csr_rls_bd_if1_wrd1_u rls_bd_if1_wrd1; /* 194 */ + volatile csr_rls_bd_if1_wrd2_u rls_bd_if1_wrd2; /* 198 */ + volatile csr_rls_bd_if1_wrd3_u rls_bd_if1_wrd3; /* 19C */ + volatile csr_add_bd_if0_wrd0_u add_bd_if0_wrd0; /* 200 */ + volatile csr_add_bd_if0_wrd1_u add_bd_if0_wrd1; /* 204 */ + volatile csr_add_bd_if0_wrd2_u add_bd_if0_wrd2; /* 208 */ + volatile csr_add_bd_if0_wrd3_u add_bd_if0_wrd3; /* 20C */ + volatile csr_add_bd_if1_wrd0_u add_bd_if1_wrd0; /* 210 */ + volatile csr_add_bd_if1_wrd1_u add_bd_if1_wrd1; /* 214 */ + volatile csr_add_bd_if1_wrd2_u add_bd_if1_wrd2; /* 218 */ + volatile csr_add_bd_if1_wrd3_u add_bd_if1_wrd3; /* 21C */ + volatile csr_oq2up_bd_if_wrd0_u oq2up_bd_if_wrd0; /* 220 */ + volatile csr_oq2up_bd_if_wrd1_u oq2up_bd_if_wrd1; /* 224 */ + volatile csr_oq2up_bd_if_wrd2_u oq2up_bd_if_wrd2; /* 228 */ + volatile csr_oq2up_bd_if_wrd3_u oq2up_bd_if_wrd3; /* 22C */ + volatile csr_csr_axi_msr_inf_u csr_axi_msr_inf; /* 240 */ + volatile csr_bd_err_status_u bd_err_status; /* 300 */ + volatile csr_bm_read0_cnt_u bm_read0_cnt; /* 308 */ + volatile csr_bm_read1_cnt_u bm_read1_cnt; /* 30C */ + volatile csr_bm_read2_cnt_u bm_read2_cnt; /* 310 */ + volatile csr_bm_read3_cnt_u bm_read3_cnt; /* 314 */ + volatile csr_bm_read4_cnt_u bm_read4_cnt; /* 318 */ + volatile csr_bm_read5_cnt_u bm_read5_cnt; /* 31C */ + volatile csr_bm_read6_cnt_u bm_read6_cnt; /* 320 */ + volatile csr_bm_read7_cnt_u bm_read7_cnt; /* 324 */ + volatile csr_bm_write0_cnt_u bm_write0_cnt; /* 328 */ + volatile csr_bm_write1_cnt_u bm_write1_cnt; /* 32C */ + volatile csr_bm_write2_cnt_u bm_write2_cnt; /* 330 */ + volatile csr_bm_write3_cnt_u bm_write3_cnt; /* 334 */ + volatile csr_bm_write4_cnt_u bm_write4_cnt; /* 338 */ + volatile csr_bm_write5_cnt_u bm_write5_cnt; /* 33C */ + volatile csr_bm_write6_cnt_u bm_write6_cnt; /* 340 */ + volatile csr_bm_write7_cnt_u bm_write7_cnt; /* 344 */ + volatile csr_bm_fifo0x1_status_u bm_fifo0x1_status; /* 348 */ + volatile csr_bm_fifo2x3_status_u bm_fifo2x3_status; /* 34C */ + volatile csr_bm_fifo4x5_status_u bm_fifo4x5_status; /* 350 */ + volatile csr_bm_fifo6x7_status_u bm_fifo6x7_status; /* 354 */ + volatile csr_bm_read0_emp_cnt_u bm_read0_emp_cnt; /* 358 */ + volatile csr_bm_read1_emp_cnt_u bm_read1_emp_cnt; /* 35C */ + volatile csr_bm_read2_emp_cnt_u bm_read2_emp_cnt; /* 360 */ + volatile csr_bm_read3_emp_cnt_u bm_read3_emp_cnt; /* 364 */ + volatile csr_bm_read4_emp_cnt_u bm_read4_emp_cnt; /* 368 */ + volatile csr_bm_read5_emp_cnt_u bm_read5_emp_cnt; /* 36C */ + volatile csr_bm_read6_emp_cnt_u bm_read6_emp_cnt; /* 370 */ + volatile csr_bm_read7_emp_cnt_u bm_read7_emp_cnt; /* 374 */ + volatile csr_rx_pkt_status_u rx_pkt_status; /* 378 */ + volatile csr_ncsi_bpr_cnt_u ncsi_bpr_cnt; /* 37C */ + volatile csr_iq_bd_status_u iq_bd_status; /* 380 */ + volatile csr_oq_bd2up_status_u oq_bd2up_status; /* 384 */ + volatile csr_oq_bd2ncsi_status_u oq_bd2ncsi_status; /* 388 */ + volatile csr_oq_bd2ipsu_status_u oq_bd2ipsu_status; /* 38C */ + volatile csr_out2up_bd_cnt_u out2up_bd_cnt; /* 390 */ + volatile csr_out2ipsu_bd_cnt_u out2ipsu_bd_cnt; /* 394 */ + volatile csr_out2ncsi_bd_cnt_u out2ncsi_bd_cnt; /* 398 */ + volatile csr_oq_eccs_cnt_u oq_eccs_cnt; /* 39C */ + volatile csr_oq_eccm_cnt_u oq_eccm_cnt; /* 4A0 */ + volatile csr_axi_rd_latency_avg_cnt_u axi_rd_latency_avg_cnt; /* 4A4 */ + volatile csr_axi_wr_latency_avg_cnt_u axi_wr_latency_avg_cnt; /* 4A8 */ + volatile csr_axi_rd_latency_max_cnt_u axi_rd_latency_max_cnt; /* 4AC */ + volatile csr_axi_wr_latency_max_cnt_u axi_wr_latency_max_cnt; /* 4B0 */ + volatile csr_axi_rd_acc_cnt_u axi_rd_acc_cnt; /* 4B4 */ + volatile csr_axi_wr_acc_cnt_u axi_wr_acc_cnt; /* 4B8 */ + volatile csr_axi_rd_otd_cnt_u axi_rd_otd_cnt; /* 4BC */ + volatile csr_axi_wr_otd_cnt_u axi_wr_otd_cnt; /* 4C0 */ + volatile csr_txdma_dat_ff_th_u txdma_dat_ff_th; /* 4D0 */ + volatile csr_txdma_dat_ff_sta_u txdma_dat_ff_sta; /* 4D4 */ + volatile csr_txdma_inf_ff_th_u txdma_inf_ff_th; /* 4D8 */ + volatile csr_txdma_inf_ff_sta_u txdma_inf_ff_sta; /* 4DC */ + volatile csr_ipsuif_ff_th_u ipsuif_ff_th; /* 4E0 */ + volatile csr_ipsuif_ff_sta_u ipsuif_ff_sta; /* 4E4 */ + volatile csr_bm_read0_ful_cnt_u bm_read0_ful_cnt; /* 4E8 */ + volatile csr_bm_read1_ful_cnt_u bm_read1_ful_cnt; /* 4EC */ + volatile csr_bm_read2_ful_cnt_u bm_read2_ful_cnt; /* 4F0 */ + volatile csr_bm_read3_ful_cnt_u bm_read3_ful_cnt; /* 4F4 */ + volatile csr_bm_read4_ful_cnt_u bm_read4_ful_cnt; /* 4F8 */ + volatile csr_bm_read5_ful_cnt_u bm_read5_ful_cnt; /* 4FC */ + volatile csr_bm_read6_ful_cnt_u bm_read6_ful_cnt; /* 500 */ + volatile csr_bm_read7_ful_cnt_u bm_read7_ful_cnt; /* 504 */ + volatile csr_rx_parity_err_cnt_u rx_parity_err_cnt; /* 508 */ + volatile csr_tx_parity_err_cnt_u tx_parity_err_cnt; /* 50C */ + volatile csr_tx_minlen_err_cnt_u tx_minlen_err_cnt; /* 510 */ + volatile csr_tx_bdsize_err_cnt_u tx_bdsize_err_cnt; /* 514 */ + volatile csr_tx_bdcode_err_cnt_u tx_bdcode_err_cnt; /* 518 */ + volatile csr_tx_sgl_ci_th_u tx_sgl_ci_th; /* 51C */ + volatile csr_tx_sgl_ci_cnt_u tx_sgl_ci_cnt; /* 520 */ + volatile csr_qm_ecc_err_addr_u qm_ecc_err_addr; /* 524 */ + volatile csr_pie_ecc_bypass_u pie_ecc_bypass; /* 528 */ + volatile csr_peif_fifo_sta_u peif_fifo_sta; /* 52C */ + volatile csr_qm_ram_ecc_insr_u qm_ram_ecc_insr; /* 530 */ + volatile csr_pie_initial_end_u pie_initial_end; /* 534 */ + volatile csr_tx_rx_ram_ecc_insr_u tx_rx_ram_ecc_insr; /* 538 */ + volatile csr_rx_cerr_cnt_u rx_cerr_cnt; /* 53C */ + volatile csr_rx_ucerr_cnt_u rx_ucerr_cnt; /* 540 */ + volatile csr_tx_cerr_cnt_u tx_cerr_cnt; /* 544 */ + volatile csr_tx_ucerr_cnt_u tx_ucerr_cnt; /* 548 */ + volatile csr_rx_ecc_err_addr_u rx_ecc_err_addr; /* 54C */ + volatile csr_tx_ecc_err_addr_u tx_ecc_err_addr; /* 550 */ +} S_pie_REGS_TYPE; + +/* Declare the struct pointor of the module pie */ +extern volatile S_pie_REGS_TYPE *goppieAllReg; + +/* Declare the functions that set the member value */ +int iSetECO_RSVD_eco_rsvd(unsigned int ueco_rsvd); +int iSetPIE_INT_RAW_STATUS_bd_oq2up_cvg_raw_status(unsigned int ubd_oq2up_cvg_raw_status); +int iSetPIE_INT_RAW_STATUS_sgl_cvg_raw_status(unsigned int usgl_cvg_raw_status); +int iSetPIE_INT_RAW_STATUS_bm_fifo_ful_raw_status(unsigned int ubm_fifo_ful_raw_status); +int iSetPIE_INT_RAW_STATUS_oq_eccm_raw_status(unsigned int uoq_eccm_raw_status); +int iSetPIE_INT_RAW_STATUS_oq_eccs_raw_status(unsigned int uoq_eccs_raw_status); +int iSetPIE_INT_RAW_STATUS_tx_parity_raw_status(unsigned int utx_parity_raw_status); +int iSetPIE_INT_RAW_STATUS_rx_parity_raw_status(unsigned int urx_parity_raw_status); +int iSetPIE_INT_RAW_STATUS_bd_oq2ipsu_ful_raw_status(unsigned int ubd_oq2ipsu_ful_raw_status); +int iSetPIE_INT_RAW_STATUS_bd_oq2ncsi_ful_raw_status(unsigned int ubd_oq2ncsi_ful_raw_status); +int iSetPIE_INT_RAW_STATUS_bd_oq2up_ful_raw_status(unsigned int ubd_oq2up_ful_raw_status); +int iSetPIE_INT_RAW_STATUS_tx_ucerr_raw_status(unsigned int utx_ucerr_raw_status); +int iSetPIE_INT_RAW_STATUS_rx_ucerr_raw_status(unsigned int urx_ucerr_raw_status); +int iSetPIE_INT_EN_bd_oq2up_cvg_en(unsigned int ubd_oq2up_cvg_en); +int iSetPIE_INT_EN_sgl_cvg_en(unsigned int usgl_cvg_en); +int iSetPIE_INT_EN_bm_fifo_ful_en(unsigned int ubm_fifo_ful_en); +int iSetPIE_INT_EN_oq_eccm_en(unsigned int uoq_eccm_en); +int iSetPIE_INT_EN_oq_eccs_en(unsigned int uoq_eccs_en); +int iSetPIE_INT_EN_tx_parity_en(unsigned int utx_parity_en); +int iSetPIE_INT_EN_rx_parity_en(unsigned int urx_parity_en); +int iSetPIE_INT_EN_bd_oq2ipsu_ful_en(unsigned int ubd_oq2ipsu_ful_en); +int iSetPIE_INT_EN_bd_oq2ncsi_ful_en(unsigned int ubd_oq2ncsi_ful_en); +int iSetPIE_INT_EN_bd_oq2up_ful_en(unsigned int ubd_oq2up_ful_en); +int iSetPIE_INT_EN_tx_ucerr_en(unsigned int utx_ucerr_en); +int iSetPIE_INT_EN_rx_ucerr_en(unsigned int urx_ucerr_en); +int iSetPIE_INT_SET_bd_oq2up_cvg_set(unsigned int ubd_oq2up_cvg_set); +int iSetPIE_INT_SET_sgl_cvg_set(unsigned int usgl_cvg_set); +int iSetPIE_INT_SET_bm_fifo_ful_set(unsigned int ubm_fifo_ful_set); +int iSetPIE_INT_SET_oq_eccm_set(unsigned int uoq_eccm_set); +int iSetPIE_INT_SET_oq_eccs_set(unsigned int uoq_eccs_set); +int iSetPIE_INT_SET_tx_parity_set(unsigned int utx_parity_set); +int iSetPIE_INT_SET_rx_parity_set(unsigned int urx_parity_set); +int iSetPIE_INT_SET_bd_oq2ipsu_ful_set(unsigned int ubd_oq2ipsu_ful_set); +int iSetPIE_INT_SET_bd_oq2ncsi_ful_set(unsigned int ubd_oq2ncsi_ful_set); +int iSetPIE_INT_SET_bd_oq2up_ful_set(unsigned int ubd_oq2up_ful_set); +int iSetPIE_INT_SET_tx_ucerr_set(unsigned int utx_ucerr_set); +int iSetPIE_INT_SET_rx_ucerr_set(unsigned int urx_ucerr_set); +int iSetPIE_INT_STATUS_bd_oq2up_cvg_int_status(unsigned int ubd_oq2up_cvg_int_status); +int iSetPIE_INT_STATUS_sgl_cvg_int_status(unsigned int usgl_cvg_int_status); +int iSetPIE_INT_STATUS_bm_fifo_ful_int_status(unsigned int ubm_fifo_ful_int_status); +int iSetPIE_INT_STATUS_oq_eccm_int_status(unsigned int uoq_eccm_int_status); +int iSetPIE_INT_STATUS_oq_eccs_int_status(unsigned int uoq_eccs_int_status); +int iSetPIE_INT_STATUS_tx_parity_int_status(unsigned int utx_parity_int_status); +int iSetPIE_INT_STATUS_rx_parity_int_status(unsigned int urx_parity_int_status); +int iSetPIE_INT_STATUS_bd_oq2ipsu_ful_int_status(unsigned int ubd_oq2ipsu_ful_int_status); +int iSetPIE_INT_STATUS_bd_oq2ncsi_ful_int_status(unsigned int ubd_oq2ncsi_ful_int_status); +int iSetPIE_INT_STATUS_bd_oq2up_ful_int_status(unsigned int ubd_oq2up_ful_int_status); +int iSetPIE_INT_STATUS_tx_ucerr_int_status(unsigned int utx_ucerr_int_status); +int iSetPIE_INT_STATUS_rx_ucerr_int_status(unsigned int urx_ucerr_int_status); +int iSetCSR_POOL_FUN_fifo0_fun(unsigned int ufifo0_fun); +int iSetCSR_POOL_FUN_fifo1_fun(unsigned int ufifo1_fun); +int iSetCSR_POOL_FUN_fifo2_fun(unsigned int ufifo2_fun); +int iSetCSR_POOL_FUN_fifo3_fun(unsigned int ufifo3_fun); +int iSetCSR_POOL_FUN_fifo4_fun(unsigned int ufifo4_fun); +int iSetCSR_POOL_FUN_fifo5_fun(unsigned int ufifo5_fun); +int iSetCSR_POOL_FUN_fifo6_fun(unsigned int ufifo6_fun); +int iSetCSR_POOL_FUN_fifo7_fun(unsigned int ufifo7_fun); +int iSetCSR_POOL_DEPTH0_fifo4_depth(unsigned int ufifo4_depth); +int iSetCSR_POOL_DEPTH0_fifo5_depth(unsigned int ufifo5_depth); +int iSetCSR_POOL_DEPTH0_fifo6_depth(unsigned int ufifo6_depth); +int iSetCSR_POOL_DEPTH0_fifo7_depth(unsigned int ufifo7_depth); +int iSetCSR_POOL_DEPTH1_fifo0_depth(unsigned int ufifo0_depth); +int iSetCSR_POOL_DEPTH1_fifo1_depth(unsigned int ufifo1_depth); +int iSetCSR_POOL_DEPTH1_fifo2_depth(unsigned int ufifo2_depth); +int iSetCSR_POOL_DEPTH1_fifo3_depth(unsigned int ufifo3_depth); +int iSetCSR_PT_PKT_TYPE_cfg_pt_pkt_type(unsigned int ucfg_pt_pkt_type); +int iSetMAX_FRAME_LEN_max_frame_len(unsigned int umax_frame_len); +int iSetMIN_FRAME_LEN_min_frame_len(unsigned int umin_frame_len); +int iSetCSR_PEIF_FUN_peif_rbd_delay(unsigned int upeif_rbd_delay); +int iSetCSR_PEIF_FUN_csr_peif_unsop_err(unsigned int ucsr_peif_unsop_err); +int iSetCSR_PEIF_FUN_csr_peif_uneop_err(unsigned int ucsr_peif_uneop_err); +int iSetCSR_PEIF_FUN_peif_fifo_gap(unsigned int upeif_fifo_gap); +int iSetCSR_QM_FUN_iq_fifo_gap(unsigned int uiq_fifo_gap); +int iSetDMA_OTD_CNT_dma_otd_cnt(unsigned int udma_otd_cnt); +int iSetCSR_TXBD_ADDR_cfg_txbd_addr(unsigned int ucfg_txbd_addr); +int iSetCSR_BD2UP_TIME_bd_int_th(unsigned int ubd_int_th); +int iSetCSR_BD2UP_TIME_bd_int_timeout(unsigned int ubd_int_timeout); +int iSetCSR_SGL_TIME_sgl_int_th(unsigned int usgl_int_th); +int iSetCSR_SGL_TIME_sgl_int_timeout(unsigned int usgl_int_timeout); +int iSetCSR_MEM_TMOD_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetCSR_MEM_TMOD_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetCSR_MEM_DFT_POWER_mem_power_mode(unsigned int umem_power_mode); +int iSetCSR_MEM_DFT_POWER_ret1n(unsigned int uret1n); +int iSetCSR_BD_IF0_WRD0_csr_bd_if0_wrd0(unsigned int ucsr_bd_if0_wrd0); +int iSetCSR_BD_IF0_WRD1_csr_bd_if0_wrd1(unsigned int ucsr_bd_if0_wrd1); +int iSetCSR_BD_IF0_WRD2_csr_bd_if0_wrd2(unsigned int ucsr_bd_if0_wrd2); +int iSetCSR_BD_IF0_WRD3_csr_bd_if0_wrd3(unsigned int ucsr_bd_if0_wrd3); +int iSetCSR_BD_IF1_WRD0_csr_bd_if1_wrd0(unsigned int ucsr_bd_if1_wrd0); +int iSetCSR_BD_IF1_WRD1_csr_bd_if1_wrd1(unsigned int ucsr_bd_if1_wrd1); +int iSetCSR_BD_IF1_WRD2_csr_bd_if1_wrd2(unsigned int ucsr_bd_if1_wrd2); +int iSetCSR_BD_IF1_WRD3_csr_bd_if1_wrd3(unsigned int ucsr_bd_if1_wrd3); +int iSetCSR_BD_IF2_WRD0_csr_bd_if2_wrd0(unsigned int ucsr_bd_if2_wrd0); +int iSetCSR_BD_IF2_WRD1_csr_bd_if2_wrd1(unsigned int ucsr_bd_if2_wrd1); +int iSetCSR_BD_IF2_WRD2_csr_bd_if2_wrd2(unsigned int ucsr_bd_if2_wrd2); +int iSetCSR_BD_IF2_WRD3_csr_bd_if2_wrd3(unsigned int ucsr_bd_if2_wrd3); +int iSetCSR_BD_IF3_WRD0_csr_bd_if3_wrd0(unsigned int ucsr_bd_if3_wrd0); +int iSetCSR_BD_IF3_WRD1_csr_bd_if3_wrd1(unsigned int ucsr_bd_if3_wrd1); +int iSetCSR_BD_IF3_WRD2_csr_bd_if3_wrd2(unsigned int ucsr_bd_if3_wrd2); +int iSetCSR_BD_IF3_WRD3_csr_bd_if3_wrd3(unsigned int ucsr_bd_if3_wrd3); +int iSetCSR_BD_IF4_WRD0_csr_bd_if4_wrd0(unsigned int ucsr_bd_if4_wrd0); +int iSetCSR_BD_IF4_WRD1_csr_bd_if4_wrd1(unsigned int ucsr_bd_if4_wrd1); +int iSetCSR_BD_IF4_WRD2_csr_bd_if4_wrd2(unsigned int ucsr_bd_if4_wrd2); +int iSetCSR_BD_IF4_WRD3_csr_bd_if4_wrd3(unsigned int ucsr_bd_if4_wrd3); +int iSetCSR_BD_IF5_WRD0_csr_bd_if5_wrd0(unsigned int ucsr_bd_if5_wrd0); +int iSetCSR_BD_IF5_WRD1_csr_bd_if5_wrd1(unsigned int ucsr_bd_if5_wrd1); +int iSetCSR_BD_IF5_WRD2_csr_bd_if5_wrd2(unsigned int ucsr_bd_if5_wrd2); +int iSetCSR_BD_IF5_WRD3_csr_bd_if5_wrd3(unsigned int ucsr_bd_if5_wrd3); +int iSetCSR_BD_IF6_WRD0_csr_bd_if6_wrd0(unsigned int ucsr_bd_if6_wrd0); +int iSetCSR_BD_IF6_WRD1_csr_bd_if6_wrd1(unsigned int ucsr_bd_if6_wrd1); +int iSetCSR_BD_IF6_WRD2_csr_bd_if6_wrd2(unsigned int ucsr_bd_if6_wrd2); +int iSetCSR_BD_IF6_WRD3_csr_bd_if6_wrd3(unsigned int ucsr_bd_if6_wrd3); +int iSetCSR_BD_IF7_WRD0_csr_bd_if7_wrd0(unsigned int ucsr_bd_if7_wrd0); +int iSetCSR_BD_IF7_WRD1_csr_bd_if7_wrd1(unsigned int ucsr_bd_if7_wrd1); +int iSetCSR_BD_IF7_WRD2_csr_bd_if7_wrd2(unsigned int ucsr_bd_if7_wrd2); +int iSetCSR_BD_IF7_WRD3_csr_bd_if7_wrd3(unsigned int ucsr_bd_if7_wrd3); +int iSetRLS_BD_IF0_WRD0_rls_bd_if0_wrd0(unsigned int urls_bd_if0_wrd0); +int iSetRLS_BD_IF0_WRD1_rls_bd_if0_wrd1(unsigned int urls_bd_if0_wrd1); +int iSetRLS_BD_IF0_WRD2_rls_bd_if0_wrd2(unsigned int urls_bd_if0_wrd2); +int iSetRLS_BD_IF0_WRD3_rls_bd_if0_wrd3(unsigned int urls_bd_if0_wrd3); +int iSetRLS_BD_IF1_WRD0_rls_bd_if1_wrd0(unsigned int urls_bd_if1_wrd0); +int iSetRLS_BD_IF1_WRD1_rls_bd_if1_wrd1(unsigned int urls_bd_if1_wrd1); +int iSetRLS_BD_IF1_WRD2_rls_bd_if1_wrd2(unsigned int urls_bd_if1_wrd2); +int iSetRLS_BD_IF1_WRD3_rls_bd_if1_wrd3(unsigned int urls_bd_if1_wrd3); +int iSetADD_BD_IF0_WRD0_add_bd_if0_wrd0(unsigned int uadd_bd_if0_wrd0); +int iSetADD_BD_IF0_WRD1_add_bd_if0_wrd1(unsigned int uadd_bd_if0_wrd1); +int iSetADD_BD_IF0_WRD2_add_bd_if0_wrd2(unsigned int uadd_bd_if0_wrd2); +int iSetADD_BD_IF0_WRD3_add_bd_if0_wrd3(unsigned int uadd_bd_if0_wrd3); +int iSetADD_BD_IF1_WRD0_add_bd_if1_wrd0(unsigned int uadd_bd_if1_wrd0); +int iSetADD_BD_IF1_WRD1_add_bd_if1_wrd1(unsigned int uadd_bd_if1_wrd1); +int iSetADD_BD_IF1_WRD2_add_bd_if1_wrd2(unsigned int uadd_bd_if1_wrd2); +int iSetADD_BD_IF1_WRD3_add_bd_if1_wrd3(unsigned int uadd_bd_if1_wrd3); +int iSetOQ2UP_BD_IF_WRD0_oq2up_bd_if_wrd0(unsigned int uoq2up_bd_if_wrd0); +int iSetOQ2UP_BD_IF_WRD1_oq2up_bd_if_wrd1(unsigned int uoq2up_bd_if_wrd1); +int iSetOQ2UP_BD_IF_WRD2_oq2up_bd_if_wrd2(unsigned int uoq2up_bd_if_wrd2); +int iSetOQ2UP_BD_IF_WRD3_oq2up_bd_if_wrd3(unsigned int uoq2up_bd_if_wrd3); +int iSetCSR_AXI_MSR_INF_axi_cnt_wr_acc_clr(unsigned int uaxi_cnt_wr_acc_clr); +int iSetCSR_AXI_MSR_INF_axi_cnt_rd_acc_clr(unsigned int uaxi_cnt_rd_acc_clr); +int iSetCSR_AXI_MSR_INF_axi_cnt_wr_latency_clr(unsigned int uaxi_cnt_wr_latency_clr); +int iSetCSR_AXI_MSR_INF_axi_cnt_rd_latency_clr(unsigned int uaxi_cnt_rd_latency_clr); +int iSetBD_ERR_STATUS_csr_reg_err(unsigned int ucsr_reg_err); +int iSetBD_ERR_STATUS_csr_2pe_err(unsigned int ucsr_2pe_err); +int iSetBD_ERR_STATUS_csr_npe_err(unsigned int ucsr_npe_err); +int iSetBD_ERR_STATUS_csr_ovflw_err(unsigned int ucsr_ovflw_err); +int iSetBM_READ0_CNT_bm_read0_cnt(unsigned int ubm_read0_cnt); +int iSetBM_READ1_CNT_bm_read1_cnt(unsigned int ubm_read1_cnt); +int iSetBM_READ2_CNT_bm_read2_cnt(unsigned int ubm_read2_cnt); +int iSetBM_READ3_CNT_bm_read3_cnt(unsigned int ubm_read3_cnt); +int iSetBM_READ4_CNT_bm_read4_cnt(unsigned int ubm_read4_cnt); +int iSetBM_READ5_CNT_bm_read5_cnt(unsigned int ubm_read5_cnt); +int iSetBM_READ6_CNT_bm_read6_cnt(unsigned int ubm_read6_cnt); +int iSetBM_READ7_CNT_bm_read7_cnt(unsigned int ubm_read7_cnt); +int iSetBM_WRITE0_CNT_bm_write0_cnt(unsigned int ubm_write0_cnt); +int iSetBM_WRITE1_CNT_bm_write1_cnt(unsigned int ubm_write1_cnt); +int iSetBM_WRITE2_CNT_bm_write2_cnt(unsigned int ubm_write2_cnt); +int iSetBM_WRITE3_CNT_bm_write3_cnt(unsigned int ubm_write3_cnt); +int iSetBM_WRITE4_CNT_bm_write4_cnt(unsigned int ubm_write4_cnt); +int iSetBM_WRITE5_CNT_bm_write5_cnt(unsigned int ubm_write5_cnt); +int iSetBM_WRITE6_CNT_bm_write6_cnt(unsigned int ubm_write6_cnt); +int iSetBM_WRITE7_CNT_bm_write7_cnt(unsigned int ubm_write7_cnt); +int iSetBM_FIFO0X1_STATUS_bm_fifo0_cnt(unsigned int ubm_fifo0_cnt); +int iSetBM_FIFO0X1_STATUS_bm_fifo0_ful(unsigned int ubm_fifo0_ful); +int iSetBM_FIFO0X1_STATUS_bm_fifo0_ept(unsigned int ubm_fifo0_ept); +int iSetBM_FIFO0X1_STATUS_bm_fifo1_cnt(unsigned int ubm_fifo1_cnt); +int iSetBM_FIFO0X1_STATUS_bm_fifo1_ful(unsigned int ubm_fifo1_ful); +int iSetBM_FIFO0X1_STATUS_bm_fifo1_ept(unsigned int ubm_fifo1_ept); +int iSetBM_FIFO2X3_STATUS_bm_fifo2_cnt(unsigned int ubm_fifo2_cnt); +int iSetBM_FIFO2X3_STATUS_bm_fifo2_ful(unsigned int ubm_fifo2_ful); +int iSetBM_FIFO2X3_STATUS_bm_fifo2_ept(unsigned int ubm_fifo2_ept); +int iSetBM_FIFO2X3_STATUS_bm_fifo3_cnt(unsigned int ubm_fifo3_cnt); +int iSetBM_FIFO2X3_STATUS_bm_fifo3_ful(unsigned int ubm_fifo3_ful); +int iSetBM_FIFO2X3_STATUS_bm_fifo3_ept(unsigned int ubm_fifo3_ept); +int iSetBM_FIFO4X5_STATUS_bm_fifo4_cnt(unsigned int ubm_fifo4_cnt); +int iSetBM_FIFO4X5_STATUS_bm_fifo4_ful(unsigned int ubm_fifo4_ful); +int iSetBM_FIFO4X5_STATUS_bm_fifo4_ept(unsigned int ubm_fifo4_ept); +int iSetBM_FIFO4X5_STATUS_bm_fifo5_cnt(unsigned int ubm_fifo5_cnt); +int iSetBM_FIFO4X5_STATUS_bm_fifo5_ful(unsigned int ubm_fifo5_ful); +int iSetBM_FIFO4X5_STATUS_bm_fifo5_ept(unsigned int ubm_fifo5_ept); +int iSetBM_FIFO6X7_STATUS_bm_fifo6_cnt(unsigned int ubm_fifo6_cnt); +int iSetBM_FIFO6X7_STATUS_bm_fifo6_ful(unsigned int ubm_fifo6_ful); +int iSetBM_FIFO6X7_STATUS_bm_fifo6_ept(unsigned int ubm_fifo6_ept); +int iSetBM_FIFO6X7_STATUS_bm_fifo7_cnt(unsigned int ubm_fifo7_cnt); +int iSetBM_FIFO6X7_STATUS_bm_fifo7_ful(unsigned int ubm_fifo7_ful); +int iSetBM_FIFO6X7_STATUS_bm_fifo7_ept(unsigned int ubm_fifo7_ept); +int iSetBM_READ0_EMP_CNT_bm_read0_emp_cnt(unsigned int ubm_read0_emp_cnt); +int iSetBM_READ1_EMP_CNT_bm_read1_emp_cnt(unsigned int ubm_read1_emp_cnt); +int iSetBM_READ2_EMP_CNT_bm_read2_emp_cnt(unsigned int ubm_read2_emp_cnt); +int iSetBM_READ3_EMP_CNT_bm_read3_emp_cnt(unsigned int ubm_read3_emp_cnt); +int iSetBM_READ4_EMP_CNT_bm_read4_emp_cnt(unsigned int ubm_read4_emp_cnt); +int iSetBM_READ5_EMP_CNT_bm_read5_emp_cnt(unsigned int ubm_read5_emp_cnt); +int iSetBM_READ6_EMP_CNT_bm_read6_emp_cnt(unsigned int ubm_read6_emp_cnt); +int iSetBM_READ7_EMP_CNT_bm_read7_emp_cnt(unsigned int ubm_read7_emp_cnt); +int iSetRX_PKT_STATUS_rx_size_up_cnt(unsigned int urx_size_up_cnt); +int iSetNCSI_BPR_CNT_ncsi_bpr_cnt(unsigned int uncsi_bpr_cnt); +int iSetIQ_BD_STATUS_iq_bd_cnt(unsigned int uiq_bd_cnt); +int iSetIQ_BD_STATUS_iq_bd_ful(unsigned int uiq_bd_ful); +int iSetIQ_BD_STATUS_iq_bd_ept(unsigned int uiq_bd_ept); +int iSetOQ_BD2UP_STATUS_oq_bd2up_cnt(unsigned int uoq_bd2up_cnt); +int iSetOQ_BD2UP_STATUS_oq_bd2up_ful(unsigned int uoq_bd2up_ful); +int iSetOQ_BD2UP_STATUS_oq_bd2up_ept(unsigned int uoq_bd2up_ept); +int iSetOQ_BD2NCSI_STATUS_oq_bd2ncsi_cnt(unsigned int uoq_bd2ncsi_cnt); +int iSetOQ_BD2NCSI_STATUS_oq_bd2ncsi_ful(unsigned int uoq_bd2ncsi_ful); +int iSetOQ_BD2NCSI_STATUS_oq_bd2ncsi_ept(unsigned int uoq_bd2ncsi_ept); +int iSetOQ_BD2IPSU_STATUS_oq_bd2ipsu_cnt(unsigned int uoq_bd2ipsu_cnt); +int iSetOQ_BD2IPSU_STATUS_oq_bd2ipsu_ful(unsigned int uoq_bd2ipsu_ful); +int iSetOQ_BD2IPSU_STATUS_oq_bd2ipsu_ept(unsigned int uoq_bd2ipsu_ept); +int iSetOUT2UP_BD_CNT_out2up_bd_cnt(unsigned int uout2up_bd_cnt); +int iSetOUT2IPSU_BD_CNT_out2ipsu_bd_cnt(unsigned int uout2ipsu_bd_cnt); +int iSetOUT2NCSI_BD_CNT_out2ncsi_bd_cnt(unsigned int uout2ncsi_bd_cnt); +int iSetOQ_ECCS_CNT_oq_eccs_cnt(unsigned int uoq_eccs_cnt); +int iSetOQ_ECCM_CNT_oq_eccm_cnt(unsigned int uoq_eccm_cnt); +int iSetAXI_RD_LATENCY_AVG_CNT_axi_rd_latency_avg_cnt(unsigned int uaxi_rd_latency_avg_cnt); +int iSetAXI_WR_LATENCY_AVG_CNT_axi_wr_latency_avg_cnt(unsigned int uaxi_wr_latency_avg_cnt); +int iSetAXI_RD_LATENCY_MAX_CNT_axi_rd_latency_max_cnt(unsigned int uaxi_rd_latency_max_cnt); +int iSetAXI_WR_LATENCY_MAX_CNT_axi_wr_latency_max_cnt(unsigned int uaxi_wr_latency_max_cnt); +int iSetAXI_RD_ACC_CNT_axi_rd_acc_cnt(unsigned int uaxi_rd_acc_cnt); +int iSetAXI_WR_ACC_CNT_axi_wr_acc_cnt(unsigned int uaxi_wr_acc_cnt); +int iSetAXI_RD_OTD_CNT_axiwr_bresp_err(unsigned int uaxiwr_bresp_err); +int iSetAXI_RD_OTD_CNT_axird_bresp_err(unsigned int uaxird_bresp_err); +int iSetAXI_RD_OTD_CNT_axi_rd_otd_cnt(unsigned int uaxi_rd_otd_cnt); +int iSetAXI_WR_OTD_CNT_axi_wr_otd_cnt(unsigned int uaxi_wr_otd_cnt); +int iSetTXDMA_DAT_FF_TH_dat_fifo_alempt_gap(unsigned int udat_fifo_alempt_gap); +int iSetTXDMA_DAT_FF_TH_dat_fifo_aful_gap(unsigned int udat_fifo_aful_gap); +int iSetTXDMA_DAT_FF_STA_dat_fifo_alempt_ff(unsigned int udat_fifo_alempt_ff); +int iSetTXDMA_DAT_FF_STA_dat_fifo_empt_ff(unsigned int udat_fifo_empt_ff); +int iSetTXDMA_DAT_FF_STA_dat_fifo_aful_ff(unsigned int udat_fifo_aful_ff); +int iSetTXDMA_DAT_FF_STA_dat_fifo_ful_ff(unsigned int udat_fifo_ful_ff); +int iSetTXDMA_DAT_FF_STA_dat_fifo_underflow_ff(unsigned int udat_fifo_underflow_ff); +int iSetTXDMA_DAT_FF_STA_dat_fifo_overflow_ff(unsigned int udat_fifo_overflow_ff); +int iSetTXDMA_DAT_FF_STA_dat_fifo_cnt_ff(unsigned int udat_fifo_cnt_ff); +int iSetTXDMA_INF_FF_TH_inf_fifo_alempt_gap(unsigned int uinf_fifo_alempt_gap); +int iSetTXDMA_INF_FF_TH_inf_fifo_aful_gap(unsigned int uinf_fifo_aful_gap); +int iSetTXDMA_INF_FF_STA_inf_fifo_alempt_ff(unsigned int uinf_fifo_alempt_ff); +int iSetTXDMA_INF_FF_STA_inf_fifo_empt_ff(unsigned int uinf_fifo_empt_ff); +int iSetTXDMA_INF_FF_STA_inf_fifo_aful_ff(unsigned int uinf_fifo_aful_ff); +int iSetTXDMA_INF_FF_STA_inf_fifo_ful_ff(unsigned int uinf_fifo_ful_ff); +int iSetTXDMA_INF_FF_STA_inf_fifo_underflow_ff(unsigned int uinf_fifo_underflow_ff); +int iSetTXDMA_INF_FF_STA_inf_fifo_overflow_ff(unsigned int uinf_fifo_overflow_ff); +int iSetTXDMA_INF_FF_STA_inf_fifo_cnt_ff(unsigned int uinf_fifo_cnt_ff); +int iSetIPSUIF_FF_TH_ipsuif_fifo_alempt_th(unsigned int uipsuif_fifo_alempt_th); +int iSetIPSUIF_FF_TH_ipsuif_fifo_afull_th(unsigned int uipsuif_fifo_afull_th); +int iSetIPSUIF_FF_STA_ipsuif_fifo_alempt(unsigned int uipsuif_fifo_alempt); +int iSetIPSUIF_FF_STA_ipsuif_fifo_empt(unsigned int uipsuif_fifo_empt); +int iSetIPSUIF_FF_STA_ipsuif_fifo_aful(unsigned int uipsuif_fifo_aful); +int iSetIPSUIF_FF_STA_ipsuif_fifo_full(unsigned int uipsuif_fifo_full); +int iSetIPSUIF_FF_STA_ipsuif_fifo_overflow(unsigned int uipsuif_fifo_overflow); +int iSetIPSUIF_FF_STA_ipsuif_fifo_wfifo_cnt(unsigned int uipsuif_fifo_wfifo_cnt); +int iSetBM_READ0_FUL_CNT_bm_read0_ful_cnt(unsigned int ubm_read0_ful_cnt); +int iSetBM_READ1_FUL_CNT_bm_read1_ful_cnt(unsigned int ubm_read1_ful_cnt); +int iSetBM_READ2_FUL_CNT_bm_read2_ful_cnt(unsigned int ubm_read2_ful_cnt); +int iSetBM_READ3_FUL_CNT_bm_read3_ful_cnt(unsigned int ubm_read3_ful_cnt); +int iSetBM_READ4_FUL_CNT_bm_read4_ful_cnt(unsigned int ubm_read4_ful_cnt); +int iSetBM_READ5_FUL_CNT_bm_read5_ful_cnt(unsigned int ubm_read5_ful_cnt); +int iSetBM_READ6_FUL_CNT_bm_read6_ful_cnt(unsigned int ubm_read6_ful_cnt); +int iSetBM_READ7_FUL_CNT_bm_read7_ful_cnt(unsigned int ubm_read7_ful_cnt); +int iSetRX_PARITY_ERR_CNT_rxdma_parity_err_cnt(unsigned int urxdma_parity_err_cnt); +int iSetTX_PARITY_ERR_CNT_txdma_parity_err_cnt(unsigned int utxdma_parity_err_cnt); +int iSetTX_MINLEN_ERR_CNT_txdma_minlen_err_cnt(unsigned int utxdma_minlen_err_cnt); +int iSetTX_BDSIZE_ERR_CNT_txdma_bdsize_err_cnt(unsigned int utxdma_bdsize_err_cnt); +int iSetTX_BDCODE_ERR_CNT_txdma_bdcode_err_cnt(unsigned int utxdma_bdcode_err_cnt); +int iSetTX_SGL_CI_TH_tx_sgl_ci_th(unsigned int utx_sgl_ci_th); +int iSetTX_SGL_CI_CNT_tx_sgl_ci_cnt(unsigned int utx_sgl_ci_cnt); +int iSetQM_ECC_ERR_ADDR_qm_ecc_err_addr(unsigned int uqm_ecc_err_addr); +int iSetPIE_ECC_BYPASS_qm_ecc_bypass(unsigned int uqm_ecc_bypass); +int iSetPEIF_FIFO_STA_peif_fifo_aful(unsigned int upeif_fifo_aful); +int iSetPEIF_FIFO_STA_peif_fifo_full(unsigned int upeif_fifo_full); +int iSetPEIF_FIFO_STA_peif_fifo_oflow(unsigned int upeif_fifo_oflow); +int iSetQM_RAM_ECC_INSR_qm_ram_cerr_insr(unsigned int uqm_ram_cerr_insr); +int iSetQM_RAM_ECC_INSR_qm_ram_ucerr_insr(unsigned int uqm_ram_ucerr_insr); +int iSetPIE_INITIAL_END_peif_prefetch_start(unsigned int upeif_prefetch_start); +int iSetTX_RX_RAM_ECC_INSR_tx_ram_cerr_insr(unsigned int utx_ram_cerr_insr); +int iSetTX_RX_RAM_ECC_INSR_tx_ram_ucerr_insr(unsigned int utx_ram_ucerr_insr); +int iSetTX_RX_RAM_ECC_INSR_rx_ram_cerr_insr(unsigned int urx_ram_cerr_insr); +int iSetTX_RX_RAM_ECC_INSR_rx_ram_ucerr_insr(unsigned int urx_ram_ucerr_insr); +int iSetRX_CERR_CNT_rx_cerr_cnt(unsigned int urx_cerr_cnt); +int iSetRX_UCERR_CNT_rx_ucerr_cnt(unsigned int urx_ucerr_cnt); +int iSetTX_CERR_CNT_tx_cerr_cnt(unsigned int utx_cerr_cnt); +int iSetTX_UCERR_CNT_tx_ucerr_cnt(unsigned int utx_ucerr_cnt); +int iSetRX_ECC_ERR_ADDR_rxdma_ecc_err_addr(unsigned int urxdma_ecc_err_addr); +int iSetTX_ECC_ERR_ADDR_txdma_ecc_err_addr(unsigned int utxdma_ecc_err_addr); + +/* Define the union csr_sc_chain_err_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chain_err_int_status : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_chain_err_int_status_u; + +/* Define the union csr_sc_chain_err_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chain_err_int_en : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_chain_err_int_en_u; + +/* Define the union csr_sc_chain_err_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chain_err_int_set : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_chain_err_int_set_u; + +/* Define the union csr_sc_chain_err_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chain_err_raw_status : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_chain_err_int_raw_status_u; + +/* Define the union csr_sc_saw_errrsp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errrsp_disable : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_saw_errrsp_u; + +/* Define the union csr_sc_cfg_smmu_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_smmu_bdf : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_cfg_smmu_bdf_u; + +/* Define the union csr_sc_cfg_mbix_didba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mbix_didba : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_cfg_mbix_didba_u; + +/* Define the union csr_sc_smmu_event_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmu_event : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_smmu_event_u; + +/* Define the union csr_sc_mpu_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_icl_ns_ctrl : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_mpu_ctrl_u; + +/* Define the union csr_sc_cfg_bus_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_wait_cycle : 10; /* [9:0] */ + u32 rsv_9 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_cfg_bus_ctrl_u; + +/* Define the union csr_sc_cmd_dely_define_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_dely_define : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_cmd_dely_define_u; + +/* Define the union csr_sc_reg_res_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_reg_res_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_reg_res_0_u; + +/* Define the union csr_sc_reg_res_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_reg_res_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_reg_res_1_u; + +/* Define the union csr_sc_reg_res_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_reg_res_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_reg_res_2_u; + +/* Define the union csr_sc_reg_res_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_reg_res_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sc_reg_res_3_u; + +/* Define the union csr_nc_reg_res_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nc_reg_res_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nc_reg_res_0_u; + +/* Define the union csr_nc_reg_res_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nc_reg_res_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nc_reg_res_1_u; + +/* Define the union csr_nc_reg_res_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nc_reg_res_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nc_reg_res_2_u; + +/* Define the union csr_nc_reg_res_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nc_reg_res_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nc_reg_res_3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_sc_chain_err_int_status_u sc_chain_err_int_status; /* 0 */ + volatile csr_sc_chain_err_int_en_u sc_chain_err_int_en; /* 4 */ + volatile csr_sc_chain_err_int_set_u sc_chain_err_int_set; /* 8 */ + volatile csr_sc_chain_err_int_raw_status_u sc_chain_err_int_raw_status; /* C */ + volatile csr_sc_saw_errrsp_u sc_saw_errrsp; /* 10 */ + volatile csr_sc_cfg_smmu_bdf_u sc_cfg_smmu_bdf; /* 14 */ + volatile csr_sc_cfg_mbix_didba_u sc_cfg_mbix_didba; /* 18 */ + volatile csr_sc_smmu_event_u sc_smmu_event; /* 1C */ + volatile csr_sc_mpu_ctrl_u sc_mpu_ctrl; /* 20 */ + volatile csr_sc_cfg_bus_ctrl_u sc_cfg_bus_ctrl; /* 24 */ + volatile csr_sc_cmd_dely_define_u sc_cmd_dely_define; /* 28 */ + volatile csr_sc_reg_res_0_u sc_reg_res_0; /* 2C */ + volatile csr_sc_reg_res_1_u sc_reg_res_1; /* 30 */ + volatile csr_sc_reg_res_2_u sc_reg_res_2; /* 34 */ + volatile csr_sc_reg_res_3_u sc_reg_res_3; /* 38 */ + volatile csr_nc_reg_res_0_u nc_reg_res_0; /* 3C */ + volatile csr_nc_reg_res_1_u nc_reg_res_1; /* 40 */ + volatile csr_nc_reg_res_2_u nc_reg_res_2; /* 44 */ + volatile csr_nc_reg_res_3_u nc_reg_res_3; /* 48 */ +} S_mpu_icl_subctrl_REGS_TYPE; + +/* Declare the struct pointor of the module mpu_icl_subctrl */ +extern volatile S_mpu_icl_subctrl_REGS_TYPE *gopmpu_icl_subctrlAllReg; + +/* Declare the functions that set the member value */ +int iSetSC_CHAIN_ERR_INT_STATUS_chain_err_int_status(unsigned int uchain_err_int_status); +int iSetSC_CHAIN_ERR_INT_EN_chain_err_int_en(unsigned int uchain_err_int_en); +int iSetSC_CHAIN_ERR_INT_SET_chain_err_int_set(unsigned int uchain_err_int_set); +int iSetSC_CHAIN_ERR_INT_RAW_STATUS_chain_err_raw_status(unsigned int uchain_err_raw_status); +int iSetSC_SAW_ERRRSP_errrsp_disable(unsigned int uerrrsp_disable); +int iSetSC_CFG_SMMU_BDF_cfg_smmu_bdf(unsigned int ucfg_smmu_bdf); +int iSetSC_CFG_MBIX_DIDBA_cfg_mbix_didba(unsigned int ucfg_mbix_didba); +int iSetSC_SMMU_EVENT_smmu_event(unsigned int usmmu_event); +int iSetSC_MPU_CTRL_mpu_icl_ns_ctrl(unsigned int umpu_icl_ns_ctrl); +int iSetSC_CFG_BUS_CTRL_rd_wait_cycle(unsigned int urd_wait_cycle); +int iSetSC_CMD_DELY_DEFINE_cmd_dely_define(unsigned int ucmd_dely_define); +int iSetSC_REG_RES_0_sc_reg_res_0(unsigned int usc_reg_res_0); +int iSetSC_REG_RES_1_sc_reg_res_1(unsigned int usc_reg_res_1); +int iSetSC_REG_RES_2_sc_reg_res_2(unsigned int usc_reg_res_2); +int iSetSC_REG_RES_3_sc_reg_res_3(unsigned int usc_reg_res_3); +int iSetNC_REG_RES_0_nc_reg_res_0(unsigned int unc_reg_res_0); +int iSetNC_REG_RES_1_nc_reg_res_1(unsigned int unc_reg_res_1); +int iSetNC_REG_RES_2_nc_reg_res_2(unsigned int unc_reg_res_2); +int iSetNC_REG_RES_3_nc_reg_res_3(unsigned int unc_reg_res_3); + +/* Define the union csr_apb2ff_fic_indir_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fic_indir_addr : 22; /* [21:0] */ + u32 fic_indir_len : 5; /* [26:22] */ + u32 fic_indir_cnt_car : 1; /* [27] */ + u32 fic_indir_stat : 2; /* [29:28] */ + u32 fic_indir_mode : 1; /* [30] */ + u32 fic_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_fic_indir_ctrl_u; + +/* Define the union csr_apb2ff_fic_indir_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fic_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_fic_indir_timeout_u; + +/* Define the union csr_apb2ff_fic_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fic_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_fic_indir_data_u; + +/* Define the union csr_apb2ff_fic_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb2ff_fic_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_fic_version_u; + +/* Define the union csr_apb2ff_mag_indir_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_indir_addr : 22; /* [21:0] */ + u32 mag_indir_len : 5; /* [26:22] */ + u32 mag_indir_cnt_car : 1; /* [27] */ + u32 mag_indir_stat : 2; /* [29:28] */ + u32 mag_indir_mode : 1; /* [30] */ + u32 mag_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_mag_indir_ctrl_u; + +/* Define the union csr_apb2ff_mag_indir_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_mag_indir_timeout_u; + +/* Define the union csr_apb2ff_mag_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_mag_indir_data_u; + +/* Define the union csr_apb2ff_mag_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb2ff_mag_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_mag_version_u; + +/* Define the union csr_apb2ff_ngpcs_indir_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ngpcs_indir_addr : 22; /* [21:0] */ + u32 ngpcs_indir_len : 5; /* [26:22] */ + u32 ngpcs_indir_cnt_car : 1; /* [27] */ + u32 ngpcs_indir_stat : 2; /* [29:28] */ + u32 ngpcs_indir_mode : 1; /* [30] */ + u32 ngpcs_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_ngpcs_indir_ctrl_u; + +/* Define the union csr_apb2ff_ngpcs_indir_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ngpcs_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_ngpcs_indir_timeout_u; + +/* Define the union csr_apb2ff_ngpcs_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ngpcs_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_ngpcs_indir_data_u; + +/* Define the union csr_apb2ff_ngpcs_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb2ff_ngpcs_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_ngpcs_version_u; + +/* Define the union csr_apb2ff_antring_indir_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 antring_indir_addr : 22; /* [21:0] */ + u32 antring_indir_len : 5; /* [26:22] */ + u32 antring_indir_cnt_car : 1; /* [27] */ + u32 antring_indir_stat : 2; /* [29:28] */ + u32 antring_indir_mode : 1; /* [30] */ + u32 antring_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_antring_indir_ctrl_u; + +/* Define the union csr_apb2ff_antring_indir_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 antring_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_antring_indir_timeout_u; + +/* Define the union csr_apb2ff_antring_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 antring_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_antring_indir_data_u; + +/* Define the union csr_apb2ff_antring_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb2ff_antring_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apb2ff_antring_version_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_apb2ff_fic_indir_ctrl_u apb2ff_fic_indir_ctrl; /* 100 */ + volatile csr_apb2ff_fic_indir_timeout_u apb2ff_fic_indir_timeout; /* 104 */ + volatile csr_apb2ff_fic_indir_data_u apb2ff_fic_indir_data[32]; /* 108 */ + volatile csr_apb2ff_fic_version_u apb2ff_fic_version; /* 188 */ + volatile csr_apb2ff_mag_indir_ctrl_u apb2ff_mag_indir_ctrl; /* 400 */ + volatile csr_apb2ff_mag_indir_timeout_u apb2ff_mag_indir_timeout; /* 404 */ + volatile csr_apb2ff_mag_indir_data_u apb2ff_mag_indir_data[32]; /* 408 */ + volatile csr_apb2ff_mag_version_u apb2ff_mag_version; /* 488 */ + volatile csr_apb2ff_ngpcs_indir_ctrl_u apb2ff_ngpcs_indir_ctrl; /* 700 */ + volatile csr_apb2ff_ngpcs_indir_timeout_u apb2ff_ngpcs_indir_timeout; /* 704 */ + volatile csr_apb2ff_ngpcs_indir_data_u apb2ff_ngpcs_indir_data[32]; /* 708 */ + volatile csr_apb2ff_ngpcs_version_u apb2ff_ngpcs_version; /* 788 */ + volatile csr_apb2ff_antring_indir_ctrl_u apb2ff_antring_indir_ctrl; /* A00 */ + volatile csr_apb2ff_antring_indir_timeout_u apb2ff_antring_indir_timeout; /* A04 */ + volatile csr_apb2ff_antring_indir_data_u apb2ff_antring_indir_data; /* A08 */ + volatile csr_apb2ff_antring_version_u apb2ff_antring_version; /* A0C */ +} S_apb2ff_csr_REGS_TYPE; + +/* Declare the struct pointor of the module apb2ff_csr */ +extern volatile S_apb2ff_csr_REGS_TYPE *gopapb2ff_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAPB2FF_FIC_INDIR_CTRL_fic_indir_addr(unsigned int ufic_indir_addr); +int iSetAPB2FF_FIC_INDIR_CTRL_fic_indir_len(unsigned int ufic_indir_len); +int iSetAPB2FF_FIC_INDIR_CTRL_fic_indir_cnt_car(unsigned int ufic_indir_cnt_car); +int iSetAPB2FF_FIC_INDIR_CTRL_fic_indir_stat(unsigned int ufic_indir_stat); +int iSetAPB2FF_FIC_INDIR_CTRL_fic_indir_mode(unsigned int ufic_indir_mode); +int iSetAPB2FF_FIC_INDIR_CTRL_fic_indir_vld(unsigned int ufic_indir_vld); +int iSetAPB2FF_FIC_INDIR_TIMEOUT_fic_indir_timeout(unsigned int ufic_indir_timeout); +int iSetAPB2FF_FIC_INDIR_DATA_fic_indir_data(unsigned int ufic_indir_data); +int iSetAPB2FF_FIC_VERSION_apb2ff_fic_version(unsigned int uapb2ff_fic_version); +int iSetAPB2FF_MAG_INDIR_CTRL_mag_indir_addr(unsigned int umag_indir_addr); +int iSetAPB2FF_MAG_INDIR_CTRL_mag_indir_len(unsigned int umag_indir_len); +int iSetAPB2FF_MAG_INDIR_CTRL_mag_indir_cnt_car(unsigned int umag_indir_cnt_car); +int iSetAPB2FF_MAG_INDIR_CTRL_mag_indir_stat(unsigned int umag_indir_stat); +int iSetAPB2FF_MAG_INDIR_CTRL_mag_indir_mode(unsigned int umag_indir_mode); +int iSetAPB2FF_MAG_INDIR_CTRL_mag_indir_vld(unsigned int umag_indir_vld); +int iSetAPB2FF_MAG_INDIR_TIMEOUT_mag_indir_timeout(unsigned int umag_indir_timeout); +int iSetAPB2FF_MAG_INDIR_DATA_mag_indir_data(unsigned int umag_indir_data); +int iSetAPB2FF_MAG_VERSION_apb2ff_mag_version(unsigned int uapb2ff_mag_version); +int iSetAPB2FF_NGPCS_INDIR_CTRL_ngpcs_indir_addr(unsigned int ungpcs_indir_addr); +int iSetAPB2FF_NGPCS_INDIR_CTRL_ngpcs_indir_len(unsigned int ungpcs_indir_len); +int iSetAPB2FF_NGPCS_INDIR_CTRL_ngpcs_indir_cnt_car(unsigned int ungpcs_indir_cnt_car); +int iSetAPB2FF_NGPCS_INDIR_CTRL_ngpcs_indir_stat(unsigned int ungpcs_indir_stat); +int iSetAPB2FF_NGPCS_INDIR_CTRL_ngpcs_indir_mode(unsigned int ungpcs_indir_mode); +int iSetAPB2FF_NGPCS_INDIR_CTRL_ngpcs_indir_vld(unsigned int ungpcs_indir_vld); +int iSetAPB2FF_NGPCS_INDIR_TIMEOUT_ngpcs_indir_timeout(unsigned int ungpcs_indir_timeout); +int iSetAPB2FF_NGPCS_INDIR_DATA_ngpcs_indir_data(unsigned int ungpcs_indir_data); +int iSetAPB2FF_NGPCS_VERSION_apb2ff_ngpcs_version(unsigned int uapb2ff_ngpcs_version); +int iSetAPB2FF_ANTRING_INDIR_CTRL_antring_indir_addr(unsigned int uantring_indir_addr); +int iSetAPB2FF_ANTRING_INDIR_CTRL_antring_indir_len(unsigned int uantring_indir_len); +int iSetAPB2FF_ANTRING_INDIR_CTRL_antring_indir_cnt_car(unsigned int uantring_indir_cnt_car); +int iSetAPB2FF_ANTRING_INDIR_CTRL_antring_indir_stat(unsigned int uantring_indir_stat); +int iSetAPB2FF_ANTRING_INDIR_CTRL_antring_indir_mode(unsigned int uantring_indir_mode); +int iSetAPB2FF_ANTRING_INDIR_CTRL_antring_indir_vld(unsigned int uantring_indir_vld); +int iSetAPB2FF_ANTRING_INDIR_TIMEOUT_antring_indir_timeout(unsigned int uantring_indir_timeout); +int iSetAPB2FF_ANTRING_INDIR_DATA_antring_indir_data(unsigned int uantring_indir_data); +int iSetAPB2FF_ANTRING_VERSION_apb2ff_antring_version(unsigned int uapb2ff_antring_version); + + +#endif // MPU_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_harden_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_harden_c_union_define.h new file mode 100644 index 000000000..9270ae689 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_harden_c_union_define.h @@ -0,0 +1,795 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : mpu_harden_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2021/06/26 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2021/06/26 17:53:27 Create file +// ****************************************************************************** + +#ifndef MPU_HARDEN_C_UNION_DEFINE_H +#define MPU_HARDEN_C_UNION_DEFINE_H + +/* Define the union csr_crg_cfg_mpu_harden_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dp_clk_en_mpu_harden : 1; /* [0] */ + u32 itf_clk_en_mpu_harden : 1; /* [1] */ + u32 sys_ncsi_clk_en_mpu_harden : 1; /* [2] */ + u32 sys_pie_clk_en_mpu_harden : 1; /* [3] */ + u32 sys_spi_clk_en_mpu_harden : 1; /* [4] */ + u32 ncsi_clk_en_mpu_harden : 1; /* [5] */ + u32 cp_clk_en_mpu_harden : 1; /* [6] */ + u32 ncsi_mac_clk_en_mpu_harden : 1; /* [7] */ + u32 hiss_sc_icg_en_emu_mpu_harden : 1; /* [8] */ + u32 dp_rst_req_mpu_harden : 1; /* [9] */ + u32 itf_rst_req_mpu_harden : 1; /* [10] */ + u32 sys_ncsi_rst_req_mpu_harden : 1; /* [11] */ + u32 sys_pie_rst_req_mpu_harden : 1; /* [12] */ + u32 sys_spi_rst_req_mpu_harden : 1; /* [13] */ + u32 spi_rst_req_mpu_harden : 1; /* [14] */ + u32 ncsi_rst_req_mpu_harden : 1; /* [15] */ + u32 cp_rst_req_mpu_harden : 1; /* [16] */ + u32 ncsi_mac_rst_req_mpu_harden : 1; /* [17] */ + u32 srst_req_nace_mpu_harden : 1; /* [18] */ + u32 hiss_sc_srst_req_emu_mpu_harden : 1; /* [19] */ + u32 hiss_sc_srst_req_emu_power_mpu_harden : 1; /* [20] */ + u32 hiss_sc_srst_req_status_mpu_harden : 1; /* [21] */ + u32 mpu_sys_clk_sel_mpu_harden : 1; /* [22] */ + u32 mpu_ncsi_mac_clk_sel_mpu_harden : 1; /* [23] */ + u32 a5x_clk_sel_mpu_harden : 1; /* [24] */ + u32 clkoff_gic_mpu_harden : 1; /* [25] */ + u32 rsv_0 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mpu_harden_0_u; + +/* Define the union csr_crg_cfg_mpu_harden_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_i2c : 5; /* [4:0] */ + u32 icg_en_smb : 1; /* [5] */ + u32 icg_en_uart : 1; /* [6] */ + u32 icg_en_mdio : 5; /* [11:7] */ + u32 icg_en_gpio : 4; /* [15:12] */ + u32 icg_en_ssi : 1; /* [16] */ + u32 icg_en_ckd : 2; /* [18:17] */ + u32 srst_req_ckd : 2; /* [20:19] */ + u32 srst_req_i2c : 5; /* [25:21] */ + u32 srst_req_smb : 1; /* [26] */ + u32 srst_req_uart : 1; /* [27] */ + u32 icg_en_wdg : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mpu_harden_1_u; + +/* Define the union csr_crg_cfg_mpu_harden_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_gpio : 4; /* [3:0] */ + u32 srst_req_ssi : 1; /* [4] */ + u32 srst_req_dbg_i2c : 1; /* [5] */ + u32 srst_req_mpu_apb : 1; /* [6] */ + u32 srst_req_cp_ring : 1; /* [7] */ + u32 srst_req_mdio : 5; /* [12:8] */ + u32 up_peri_sys_clk_sel : 1; /* [13] */ + u32 sc_all_scan_disable : 1; /* [14] */ + u32 srst_req_hva_cpi : 1; /* [15] */ + u32 srst_req_its : 1; /* [16] */ + u32 srst_req_mbigen : 1; /* [17] */ + u32 srst_req_djtag : 1; /* [18] */ + u32 srst_req_dcip : 1; /* [19] */ + u32 icg_en_hiss_axi : 1; /* [20] */ + u32 icg_en_hiss_apb : 1; /* [21] */ + u32 icg_en_hiss_ahb : 1; /* [22] */ + u32 icg_en_hva_cpi : 1; /* [23] */ + u32 icg_en_its : 1; /* [24] */ + u32 icg_en_mbigen : 1; /* [25] */ + u32 icg_en_smmu : 1; /* [26] */ + u32 icg_en_smmu_trans : 1; /* [27] */ + u32 icg_en_djtag : 1; /* [28] */ + u32 icg_en_dcip : 1; /* [29] */ + u32 djtag_clk_sel : 1; /* [30] */ + u32 rsv_2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mpu_harden_2_u; + +/* Define the union csr_crg_cfg_pcie_rc_harden_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_smmu_pcie_rc_harden : 1; /* [0] */ + u32 icg_en_smmu_trans_pcie_rc_harden : 1; /* [1] */ + u32 icg_en_mclk_pcie_rc_harden : 2; /* [3:2] */ + u32 icg_en_rxoclk_pcie_rc_harden : 4; /* [7:4] */ + u32 icg_en_sds4_pma_tx_pcie_rc_harden : 1; /* [8] */ + u32 icg_en_sds4_pma_rx_pcie_rc_harden : 2; /* [10:9] */ + u32 icg_en_sds5_pma_tx_pcie_rc_harden : 1; /* [11] */ + u32 icg_en_sds5_pma_rx_pcie_rc_harden : 2; /* [13:12] */ + u32 icg_en_pipe_pcie_rc_harden : 4; /* [17:14] */ + u32 icg_en_hipciec_tl_dl_pcie_rc_harden : 2; /* [19:18] */ + u32 icg_en_pcs_rx_pcie_rc_harden : 4; /* [23:20] */ + u32 icg_en_pcs_tx_pcie_rc_harden : 4; /* [27:24] */ + u32 icg_en_pcs_local_pcie_rc_harden : 1; /* [28] */ + u32 icg_en_apb_pcie_rc_harden : 1; /* [29] */ + u32 icg_en_axi_pcie_rc_harden : 1; /* [30] */ + u32 rsv_3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_pcie_rc_harden_0_u; + +/* Define the union csr_crg_cfg_pcie_rc_harden_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_sds4_pma_tx_pcie_rc_harden : 1; /* [0] */ + u32 srst_req_sds4_pma_rx_pcie_rc_harden : 2; /* [2:1] */ + u32 srst_req_sds5_pma_tx_pcie_rc_harden : 1; /* [3] */ + u32 srst_req_sds5_pma_rx_pcie_rc_harden : 2; /* [5:4] */ + u32 srst_req_cfg_bus_pcie_rc_harden : 1; /* [6] */ + u32 pcie_rc_sys_clk_sel_pcie_rc_harden : 1; /* [7] */ + u32 soft_rst_req_pcie_port_pcie_rc_harden : 2; /* [9:8] */ + u32 soft_rst_req_pcie_axi_pcie_rc_harden : 1; /* [10] */ + u32 soft_rst_req_pcie_apb_pcie_rc_harden : 1; /* [11] */ + u32 soft_rst_req_pcie_pcie_rc_harden : 1; /* [12] */ + u32 srst_ras_req_pcie_rc_harden : 1; /* [13] */ + u32 func_mbist_clk_sel_pcie_rc_harden : 1; /* [14] */ + u32 icg_en_probe_pcie_rc_harden : 1; /* [15] */ + u32 sds_rc_mclk_icg_en_sel_pcie_rc_harden : 2; /* [17:16] */ + u32 rsv_4 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_pcie_rc_harden_1_u; + +/* Define the union csr_pcie_rc_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rc_pwr_on : 1; /* [0] */ + u32 pcie_rc_iso_en : 1; /* [1] */ + u32 rsv_5 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rc_power_cfg_u; + +/* Define the union csr_pcie_rc_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rc_pwr_ack : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rc_power_ack_u; + +/* Define the union csr_crg_cfg_lcam_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_lcam_cp_lcam_harden : 1; /* [0] */ + u32 icg_en_lcam_lcam_harden : 5; /* [5:1] */ + u32 icg_en_lcam_common_lcam_harden : 1; /* [6] */ + u32 icg_en_ring_lcam_harden : 1; /* [7] */ + u32 srst_req_lcam_cp_lcam_harden : 1; /* [8] */ + u32 srst_req_lcam_lcam_harden : 5; /* [13:9] */ + u32 srst_req_lcam_common_lcam_harden : 1; /* [14] */ + u32 srst_req_ring_lcam_harden : 1; /* [15] */ + u32 lcam_clk_div_sel : 2; /* [17:16] */ + u32 rsv_7 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_lcam_harden_u; + +/* Define the union csr_ring_sta_mpu_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_mpu_harden : 10; /* [9:0] */ + u32 rsv_8 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_mpu_harden_u; + +/* Define the union csr_ring_sta_lcam_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_lcam_harden : 10; /* [9:0] */ + u32 rsv_9 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_lcam_harden_u; + +/* Define the union csr_dcip_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_enable : 3; /* [2:0] */ + u32 clk_div_cfg : 2; /* [4:3] */ + u32 detect_period : 2; /* [6:5] */ + u32 dff_ignore : 14; /* [20:7] */ + u32 rsv_10 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dcip_cfg_0_u; + +/* Define the union csr_dcip_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dff_limit : 14; /* [13:0] */ + u32 dff_test_e : 1; /* [14] */ + u32 dff_tsel : 3; /* [17:15] */ + u32 dc_tsel : 2; /* [19:18] */ + u32 bypass_enable : 1; /* [20] */ + u32 force_err_enable : 1; /* [21] */ + u32 test_in : 8; /* [29:22] */ + u32 rsv_11 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dcip_cfg_1_u; + +/* Define the union csr_dcip_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inner_flag : 1; /* [0] */ + u32 inner_flag_now : 1; /* [1] */ + u32 outer_flag : 1; /* [2] */ + u32 outer_flag_now : 1; /* [3] */ + u32 mid_flag : 1; /* [4] */ + u32 mid_flag_now : 1; /* [5] */ + u32 dff_location : 14; /* [19:6] */ + u32 dff_state : 2; /* [21:20] */ + u32 test_out : 8; /* [29:22] */ + u32 rsv_12 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dcip_status_u; + +/* Define the union csr_pad_in_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 test_mode0 : 1; /* [0] */ + u32 test_mode1 : 1; /* [1] */ + u32 test_mode2 : 1; /* [2] */ + u32 boot_sel0 : 1; /* [3] */ + u32 boot_sel1 : 1; /* [4] */ + u32 i2c_slv_addr0 : 1; /* [5] */ + u32 i2c_slv_addr1 : 1; /* [6] */ + u32 boot_mode : 1; /* [7] */ + u32 ncsi_nc_package0 : 1; /* [8] */ + u32 ncsi_nc_package1 : 1; /* [9] */ + u32 ncsi_nc_package2 : 1; /* [10] */ + u32 rsv_13 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pad_in_status_u; + +/* Define the union csr_dft_mpu_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 funcmbist_reset_n : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dft_mpu_u; + +/* Define the union csr_hiss_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_sc_corepreq : 1; /* [0] */ + u32 hiss_sc_corepastate : 1; /* [1] */ + u32 hiss_dgback_hiss_mask : 1; /* [2] */ + u32 hiss_sc_enable : 1; /* [3] */ + u32 hiss_sc_isolate_cpu : 1; /* [4] */ + u32 hiss_sc_idle_isolate_bypass : 1; /* [5] */ + u32 rsv_15 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hiss_ctrl_u; + +/* Define the union csr_hiss_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hiss_sc_corepaccept : 1; /* [0] */ + u32 hiss_sc_corepactive : 2; /* [2:1] */ + u32 hiss_sc_corepdeny : 1; /* [3] */ + u32 hiss_sc_core_idle : 1; /* [4] */ + u32 hiss_sc_corepowerdown : 1; /* [5] */ + u32 hiss_sc_debug_info : 7; /* [12:6] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hiss_ctrl_status_u; + +/* Define the union csr_tile_jtag_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_jtag_en : 8; /* [7:0] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_jtag_en_u; + +/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mpu_mem_ctrl_0 : 13; /* [12:0] */ + u32 cfg_mpu_mem_ctrl_1 : 15; /* [27:13] */ + u32 rsv_18 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_0_u; + +/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mpu_mem_ctrl_2 : 13; /* [12:0] */ + u32 cfg_mpu_mem_ctrl_3 : 13; /* [25:13] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_1_u; + +/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mpu_mem_ctrl_4 : 13; /* [12:0] */ + u32 cfg_mpu_mem_ctrl_5 : 13; /* [25:13] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_2_u; + +/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mpu_mem_ctrl_6 : 15; /* [14:0] */ + u32 cfg_mpu_mem_ctrl_7 : 13; /* [27:15] */ + u32 rsv_21 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_3_u; + +/* Define the union csr_cfg_mpu_cpl_icl_mem_ctrl_bus_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mpu_mem_ctrl_8 : 13; /* [12:0] */ + u32 cfg_mpu_mem_ctrl_9 : 13; /* [25:13] */ + u32 rsv_22 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mpu_cpl_icl_mem_ctrl_bus_4_u; + +/* Define the union csr_efuse_die_id_2k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 efuse_die_id_2k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_efuse_die_id_2k_u; + +/* Define the union csr_efuse_die_id_4k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 efuse_die_id_4k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_efuse_die_id_4k_u; + +/* Define the union csr_djtag_clk_div_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 djtag_clk_div_num : 4; /* [3:0] */ + u32 rsv_23 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_djtag_clk_div_num_u; + +/* Define the union csr_icg_en_kisdon_tap_tck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_kisdon_tap_tck : 8; /* [7:0] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icg_en_kisdon_tap_tck_u; + +/* Define the union csr_sfc_dq3_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfc_dq3_ctrl_en : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sfc_dq3_ctrl_u; + +/* Define the union csr_node_apb_pslverr_pad_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 node_apb_pslverr_pad_cfg : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_node_apb_pslverr_pad_cfg_u; + +/* Define the union csr_jtag_auth_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc2ja_selftest_enb : 1; /* [0] */ + u32 sc2ja_emsa_pss_sel : 1; /* [1] */ + u32 hi_1280e_die_sel : 1; /* [2] */ + u32 ja2jalite_auth_res : 1; /* [3] */ + u32 jtag_auth_result_en : 1; /* [4] */ + u32 rsv_27 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_jtag_auth_ctrl_u; + +/* Define the union csr_jtag_auth_result_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 jtag_auth_result : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_jtag_auth_result_u; + +/* Define the union csr_jtag_heart_beat_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 jtag_heart_beat_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_jtag_heart_beat_num_u; + +/* Define the union csr_efuse_sw_rst_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 efuse_4k_rst : 1; /* [0] */ + u32 efuse_2k_rst : 1; /* [1] */ + u32 rsv_28 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_efuse_sw_rst_n_u; + +/* Define the union csr_efuse_repair_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 efuse_4k_repair_done : 1; /* [0] */ + u32 efuse_2k_repair_done : 1; /* [1] */ + u32 efuse_dft_repair_done : 1; /* [2] */ + u32 efuse_repair_done_all : 1; /* [3] */ + u32 rsv_29 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_efuse_repair_done_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_crg_cfg_mpu_harden_0_u crg_cfg_mpu_harden_0; /* 0 */ + volatile csr_crg_cfg_mpu_harden_1_u crg_cfg_mpu_harden_1; /* 4 */ + volatile csr_crg_cfg_mpu_harden_2_u crg_cfg_mpu_harden_2; /* 8 */ + volatile csr_crg_cfg_pcie_rc_harden_0_u crg_cfg_pcie_rc_harden_0; /* C */ + volatile csr_crg_cfg_pcie_rc_harden_1_u crg_cfg_pcie_rc_harden_1; /* 10 */ + volatile csr_pcie_rc_power_cfg_u pcie_rc_power_cfg; /* 14 */ + volatile csr_pcie_rc_power_ack_u pcie_rc_power_ack; /* 18 */ + volatile csr_crg_cfg_lcam_harden_u crg_cfg_lcam_harden; /* 1C */ + volatile csr_ring_sta_mpu_harden_u ring_sta_mpu_harden; /* 20 */ + volatile csr_ring_sta_lcam_harden_u ring_sta_lcam_harden; /* 24 */ + volatile csr_dcip_cfg_0_u dcip_cfg_0; /* 28 */ + volatile csr_dcip_cfg_1_u dcip_cfg_1; /* 2C */ + volatile csr_dcip_status_u dcip_status; /* 30 */ + volatile csr_pad_in_status_u pad_in_status; /* 34 */ + volatile csr_dft_mpu_u dft_mpu; /* 38 */ + volatile csr_hiss_ctrl_u hiss_ctrl; /* 3C */ + volatile csr_hiss_ctrl_status_u hiss_ctrl_status; /* 40 */ + volatile csr_tile_jtag_en_u tile_jtag_en; /* 44 */ + volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_0_u cfg_mpu_cpl_icl_mem_ctrl_bus_0; /* 48 */ + volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_1_u cfg_mpu_cpl_icl_mem_ctrl_bus_1; /* 4C */ + volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_2_u cfg_mpu_cpl_icl_mem_ctrl_bus_2; /* 50 */ + volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_3_u cfg_mpu_cpl_icl_mem_ctrl_bus_3; /* 54 */ + volatile csr_cfg_mpu_cpl_icl_mem_ctrl_bus_4_u cfg_mpu_cpl_icl_mem_ctrl_bus_4; /* 58 */ + volatile csr_efuse_die_id_2k_u efuse_die_id_2k[64]; /* 200 */ + volatile csr_efuse_die_id_4k_u efuse_die_id_4k[128]; /* 300 */ + volatile csr_djtag_clk_div_num_u djtag_clk_div_num; /* 500 */ + volatile csr_icg_en_kisdon_tap_tck_u icg_en_kisdon_tap_tck; /* 504 */ + volatile csr_sfc_dq3_ctrl_u sfc_dq3_ctrl; /* 508 */ + volatile csr_node_apb_pslverr_pad_cfg_u node_apb_pslverr_pad_cfg; /* 50C */ + volatile csr_jtag_auth_ctrl_u jtag_auth_ctrl; /* 510 */ + volatile csr_jtag_auth_result_u jtag_auth_result[2]; /* 514 */ + volatile csr_jtag_heart_beat_num_u jtag_heart_beat_num; /* 51C */ + volatile csr_efuse_sw_rst_n_u efuse_sw_rst_n; /* 520 */ + volatile csr_efuse_repair_done_u efuse_repair_done; /* 524 */ +} S_mpu_harden_node_csr_REGS_TYPE; + +/* Declare the struct pointor of the module mpu_harden_node_csr */ +extern volatile S_mpu_harden_node_csr_REGS_TYPE *gopmpu_harden_node_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCRG_CFG_MPU_HARDEN_0_dp_clk_en_mpu_harden(unsigned int udp_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_itf_clk_en_mpu_harden(unsigned int uitf_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_sys_ncsi_clk_en_mpu_harden(unsigned int usys_ncsi_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_sys_pie_clk_en_mpu_harden(unsigned int usys_pie_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_sys_spi_clk_en_mpu_harden(unsigned int usys_spi_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_ncsi_clk_en_mpu_harden(unsigned int uncsi_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_cp_clk_en_mpu_harden(unsigned int ucp_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_ncsi_mac_clk_en_mpu_harden(unsigned int uncsi_mac_clk_en_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_icg_en_emu_mpu_harden(unsigned int uhiss_sc_icg_en_emu_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_dp_rst_req_mpu_harden(unsigned int udp_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_itf_rst_req_mpu_harden(unsigned int uitf_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_sys_ncsi_rst_req_mpu_harden(unsigned int usys_ncsi_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_sys_pie_rst_req_mpu_harden(unsigned int usys_pie_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_sys_spi_rst_req_mpu_harden(unsigned int usys_spi_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_spi_rst_req_mpu_harden(unsigned int uspi_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_ncsi_rst_req_mpu_harden(unsigned int uncsi_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_cp_rst_req_mpu_harden(unsigned int ucp_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_ncsi_mac_rst_req_mpu_harden(unsigned int uncsi_mac_rst_req_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_srst_req_nace_mpu_harden(unsigned int usrst_req_nace_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_srst_req_emu_mpu_harden(unsigned int uhiss_sc_srst_req_emu_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_srst_req_emu_power_mpu_harden(unsigned int uhiss_sc_srst_req_emu_power_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_hiss_sc_srst_req_status_mpu_harden(unsigned int uhiss_sc_srst_req_status_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_mpu_sys_clk_sel_mpu_harden(unsigned int umpu_sys_clk_sel_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_mpu_ncsi_mac_clk_sel_mpu_harden(unsigned int umpu_ncsi_mac_clk_sel_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_a5x_clk_sel_mpu_harden(unsigned int ua5x_clk_sel_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_0_clkoff_gic_mpu_harden(unsigned int uclkoff_gic_mpu_harden); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_i2c(unsigned int uicg_en_i2c); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_smb(unsigned int uicg_en_smb); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_uart(unsigned int uicg_en_uart); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_mdio(unsigned int uicg_en_mdio); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_gpio(unsigned int uicg_en_gpio); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_ssi(unsigned int uicg_en_ssi); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_ckd(unsigned int uicg_en_ckd); +int iSetCRG_CFG_MPU_HARDEN_1_srst_req_ckd(unsigned int usrst_req_ckd); +int iSetCRG_CFG_MPU_HARDEN_1_srst_req_i2c(unsigned int usrst_req_i2c); +int iSetCRG_CFG_MPU_HARDEN_1_srst_req_smb(unsigned int usrst_req_smb); +int iSetCRG_CFG_MPU_HARDEN_1_srst_req_uart(unsigned int usrst_req_uart); +int iSetCRG_CFG_MPU_HARDEN_1_icg_en_wdg(unsigned int uicg_en_wdg); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_gpio(unsigned int usrst_req_gpio); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_ssi(unsigned int usrst_req_ssi); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_dbg_i2c(unsigned int usrst_req_dbg_i2c); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_mpu_apb(unsigned int usrst_req_mpu_apb); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_cp_ring(unsigned int usrst_req_cp_ring); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_mdio(unsigned int usrst_req_mdio); +int iSetCRG_CFG_MPU_HARDEN_2_up_peri_sys_clk_sel(unsigned int uup_peri_sys_clk_sel); +int iSetCRG_CFG_MPU_HARDEN_2_sc_all_scan_disable(unsigned int usc_all_scan_disable); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_hva_cpi(unsigned int usrst_req_hva_cpi); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_its(unsigned int usrst_req_its); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_mbigen(unsigned int usrst_req_mbigen); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_djtag(unsigned int usrst_req_djtag); +int iSetCRG_CFG_MPU_HARDEN_2_srst_req_dcip(unsigned int usrst_req_dcip); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hiss_axi(unsigned int uicg_en_hiss_axi); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hiss_apb(unsigned int uicg_en_hiss_apb); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hiss_ahb(unsigned int uicg_en_hiss_ahb); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_hva_cpi(unsigned int uicg_en_hva_cpi); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_its(unsigned int uicg_en_its); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_mbigen(unsigned int uicg_en_mbigen); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_smmu(unsigned int uicg_en_smmu); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_smmu_trans(unsigned int uicg_en_smmu_trans); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_djtag(unsigned int uicg_en_djtag); +int iSetCRG_CFG_MPU_HARDEN_2_icg_en_dcip(unsigned int uicg_en_dcip); +int iSetCRG_CFG_MPU_HARDEN_2_djtag_clk_sel(unsigned int udjtag_clk_sel); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_smmu_pcie_rc_harden(unsigned int uicg_en_smmu_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_smmu_trans_pcie_rc_harden(unsigned int uicg_en_smmu_trans_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_mclk_pcie_rc_harden(unsigned int uicg_en_mclk_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_rxoclk_pcie_rc_harden(unsigned int uicg_en_rxoclk_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds4_pma_tx_pcie_rc_harden(unsigned int uicg_en_sds4_pma_tx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds4_pma_rx_pcie_rc_harden(unsigned int uicg_en_sds4_pma_rx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds5_pma_tx_pcie_rc_harden(unsigned int uicg_en_sds5_pma_tx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_sds5_pma_rx_pcie_rc_harden(unsigned int uicg_en_sds5_pma_rx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pipe_pcie_rc_harden(unsigned int uicg_en_pipe_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_hipciec_tl_dl_pcie_rc_harden(unsigned int uicg_en_hipciec_tl_dl_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pcs_rx_pcie_rc_harden(unsigned int uicg_en_pcs_rx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pcs_tx_pcie_rc_harden(unsigned int uicg_en_pcs_tx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_pcs_local_pcie_rc_harden(unsigned int uicg_en_pcs_local_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_apb_pcie_rc_harden(unsigned int uicg_en_apb_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_0_icg_en_axi_pcie_rc_harden(unsigned int uicg_en_axi_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds4_pma_tx_pcie_rc_harden(unsigned int usrst_req_sds4_pma_tx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds4_pma_rx_pcie_rc_harden(unsigned int usrst_req_sds4_pma_rx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds5_pma_tx_pcie_rc_harden(unsigned int usrst_req_sds5_pma_tx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_sds5_pma_rx_pcie_rc_harden(unsigned int usrst_req_sds5_pma_rx_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_req_cfg_bus_pcie_rc_harden(unsigned int usrst_req_cfg_bus_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_pcie_rc_sys_clk_sel_pcie_rc_harden(unsigned int upcie_rc_sys_clk_sel_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_port_pcie_rc_harden( + unsigned int usoft_rst_req_pcie_port_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_axi_pcie_rc_harden( + unsigned int usoft_rst_req_pcie_axi_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_apb_pcie_rc_harden( + unsigned int usoft_rst_req_pcie_apb_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_soft_rst_req_pcie_pcie_rc_harden(unsigned int usoft_rst_req_pcie_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_srst_ras_req_pcie_rc_harden(unsigned int usrst_ras_req_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_func_mbist_clk_sel_pcie_rc_harden(unsigned int ufunc_mbist_clk_sel_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_icg_en_probe_pcie_rc_harden(unsigned int uicg_en_probe_pcie_rc_harden); +int iSetCRG_CFG_PCIE_RC_HARDEN_1_sds_rc_mclk_icg_en_sel_pcie_rc_harden( + unsigned int usds_rc_mclk_icg_en_sel_pcie_rc_harden); +int iSetPCIE_RC_POWER_CFG_pcie_rc_pwr_on(unsigned int upcie_rc_pwr_on); +int iSetPCIE_RC_POWER_CFG_pcie_rc_iso_en(unsigned int upcie_rc_iso_en); +int iSetPCIE_RC_POWER_ACK_pcie_rc_pwr_ack(unsigned int upcie_rc_pwr_ack); +int iSetCRG_CFG_LCAM_HARDEN_icg_en_lcam_cp_lcam_harden(unsigned int uicg_en_lcam_cp_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_icg_en_lcam_lcam_harden(unsigned int uicg_en_lcam_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_icg_en_lcam_common_lcam_harden(unsigned int uicg_en_lcam_common_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_icg_en_ring_lcam_harden(unsigned int uicg_en_ring_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_srst_req_lcam_cp_lcam_harden(unsigned int usrst_req_lcam_cp_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_srst_req_lcam_lcam_harden(unsigned int usrst_req_lcam_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_srst_req_lcam_common_lcam_harden(unsigned int usrst_req_lcam_common_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_srst_req_ring_lcam_harden(unsigned int usrst_req_ring_lcam_harden); +int iSetCRG_CFG_LCAM_HARDEN_lcam_clk_div_sel(unsigned int ulcam_clk_div_sel); +int iSetRING_STA_MPU_HARDEN_rs_nd_pe_crdt_sta_mpu_harden(unsigned int urs_nd_pe_crdt_sta_mpu_harden); +int iSetRING_STA_LCAM_HARDEN_rs_nd_pe_crdt_sta_lcam_harden(unsigned int urs_nd_pe_crdt_sta_lcam_harden); +int iSetDCIP_CFG_0_detect_enable(unsigned int udetect_enable); +int iSetDCIP_CFG_0_clk_div_cfg(unsigned int uclk_div_cfg); +int iSetDCIP_CFG_0_detect_period(unsigned int udetect_period); +int iSetDCIP_CFG_0_dff_ignore(unsigned int udff_ignore); +int iSetDCIP_CFG_1_dff_limit(unsigned int udff_limit); +int iSetDCIP_CFG_1_dff_test_e(unsigned int udff_test_e); +int iSetDCIP_CFG_1_dff_tsel(unsigned int udff_tsel); +int iSetDCIP_CFG_1_dc_tsel(unsigned int udc_tsel); +int iSetDCIP_CFG_1_bypass_enable(unsigned int ubypass_enable); +int iSetDCIP_CFG_1_force_err_enable(unsigned int uforce_err_enable); +int iSetDCIP_CFG_1_test_in(unsigned int utest_in); +int iSetDCIP_STATUS_inner_flag(unsigned int uinner_flag); +int iSetDCIP_STATUS_inner_flag_now(unsigned int uinner_flag_now); +int iSetDCIP_STATUS_outer_flag(unsigned int uouter_flag); +int iSetDCIP_STATUS_outer_flag_now(unsigned int uouter_flag_now); +int iSetDCIP_STATUS_mid_flag(unsigned int umid_flag); +int iSetDCIP_STATUS_mid_flag_now(unsigned int umid_flag_now); +int iSetDCIP_STATUS_dff_location(unsigned int udff_location); +int iSetDCIP_STATUS_dff_state(unsigned int udff_state); +int iSetDCIP_STATUS_test_out(unsigned int utest_out); +int iSetPAD_IN_STATUS_test_mode0(unsigned int utest_mode0); +int iSetPAD_IN_STATUS_test_mode1(unsigned int utest_mode1); +int iSetPAD_IN_STATUS_test_mode2(unsigned int utest_mode2); +int iSetPAD_IN_STATUS_boot_sel0(unsigned int uboot_sel0); +int iSetPAD_IN_STATUS_boot_sel1(unsigned int uboot_sel1); +int iSetPAD_IN_STATUS_i2c_slv_addr0(unsigned int ui2c_slv_addr0); +int iSetPAD_IN_STATUS_i2c_slv_addr1(unsigned int ui2c_slv_addr1); +int iSetPAD_IN_STATUS_boot_mode(unsigned int uboot_mode); +int iSetPAD_IN_STATUS_ncsi_nc_package0(unsigned int uncsi_nc_package0); +int iSetPAD_IN_STATUS_ncsi_nc_package1(unsigned int uncsi_nc_package1); +int iSetPAD_IN_STATUS_ncsi_nc_package2(unsigned int uncsi_nc_package2); +int iSetDFT_MPU_funcmbist_reset_n(unsigned int ufuncmbist_reset_n); +int iSetHISS_CTRL_hiss_sc_corepreq(unsigned int uhiss_sc_corepreq); +int iSetHISS_CTRL_hiss_sc_corepastate(unsigned int uhiss_sc_corepastate); +int iSetHISS_CTRL_hiss_dgback_hiss_mask(unsigned int uhiss_dgback_hiss_mask); +int iSetHISS_CTRL_hiss_sc_enable(unsigned int uhiss_sc_enable); +int iSetHISS_CTRL_hiss_sc_isolate_cpu(unsigned int uhiss_sc_isolate_cpu); +int iSetHISS_CTRL_hiss_sc_idle_isolate_bypass(unsigned int uhiss_sc_idle_isolate_bypass); +int iSetHISS_CTRL_STATUS_hiss_sc_corepaccept(unsigned int uhiss_sc_corepaccept); +int iSetHISS_CTRL_STATUS_hiss_sc_corepactive(unsigned int uhiss_sc_corepactive); +int iSetHISS_CTRL_STATUS_hiss_sc_corepdeny(unsigned int uhiss_sc_corepdeny); +int iSetHISS_CTRL_STATUS_hiss_sc_core_idle(unsigned int uhiss_sc_core_idle); +int iSetHISS_CTRL_STATUS_hiss_sc_corepowerdown(unsigned int uhiss_sc_corepowerdown); +int iSetHISS_CTRL_STATUS_hiss_sc_debug_info(unsigned int uhiss_sc_debug_info); +int iSetTILE_JTAG_EN_tile_jtag_en(unsigned int utile_jtag_en); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_0_cfg_mpu_mem_ctrl_0(unsigned int ucfg_mpu_mem_ctrl_0); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_0_cfg_mpu_mem_ctrl_1(unsigned int ucfg_mpu_mem_ctrl_1); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_1_cfg_mpu_mem_ctrl_2(unsigned int ucfg_mpu_mem_ctrl_2); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_1_cfg_mpu_mem_ctrl_3(unsigned int ucfg_mpu_mem_ctrl_3); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_2_cfg_mpu_mem_ctrl_4(unsigned int ucfg_mpu_mem_ctrl_4); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_2_cfg_mpu_mem_ctrl_5(unsigned int ucfg_mpu_mem_ctrl_5); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_3_cfg_mpu_mem_ctrl_6(unsigned int ucfg_mpu_mem_ctrl_6); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_3_cfg_mpu_mem_ctrl_7(unsigned int ucfg_mpu_mem_ctrl_7); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_4_cfg_mpu_mem_ctrl_8(unsigned int ucfg_mpu_mem_ctrl_8); +int iSetCFG_MPU_CPL_ICL_MEM_CTRL_BUS_4_cfg_mpu_mem_ctrl_9(unsigned int ucfg_mpu_mem_ctrl_9); +int iSetEFUSE_DIE_ID_2K_efuse_die_id_2k(unsigned int uefuse_die_id_2k); +int iSetEFUSE_DIE_ID_4K_efuse_die_id_4k(unsigned int uefuse_die_id_4k); +int iSetDJTAG_CLK_DIV_NUM_djtag_clk_div_num(unsigned int udjtag_clk_div_num); +int iSetICG_EN_KISDON_TAP_TCK_icg_en_kisdon_tap_tck(unsigned int uicg_en_kisdon_tap_tck); +int iSetSFC_DQ3_CTRL_sfc_dq3_ctrl_en(unsigned int usfc_dq3_ctrl_en); +int iSetNODE_APB_PSLVERR_PAD_CFG_node_apb_pslverr_pad_cfg(unsigned int unode_apb_pslverr_pad_cfg); +int iSetJTAG_AUTH_CTRL_sc2ja_selftest_enb(unsigned int usc2ja_selftest_enb); +int iSetJTAG_AUTH_CTRL_sc2ja_emsa_pss_sel(unsigned int usc2ja_emsa_pss_sel); +int iSetJTAG_AUTH_CTRL_hi_1280e_die_sel(unsigned int uhi_1280e_die_sel); +int iSetJTAG_AUTH_CTRL_ja2jalite_auth_res(unsigned int uja2jalite_auth_res); +int iSetJTAG_AUTH_CTRL_jtag_auth_result_en(unsigned int ujtag_auth_result_en); +int iSetJTAG_AUTH_RESULT_jtag_auth_result(unsigned int ujtag_auth_result); +int iSetJTAG_HEART_BEAT_NUM_jtag_heart_beat_num(unsigned int ujtag_heart_beat_num); +int iSetEFUSE_SW_RST_N_efuse_4k_rst(unsigned int uefuse_4k_rst); +int iSetEFUSE_SW_RST_N_efuse_2k_rst(unsigned int uefuse_2k_rst); +int iSetEFUSE_REPAIR_DONE_efuse_4k_repair_done(unsigned int uefuse_4k_repair_done); +int iSetEFUSE_REPAIR_DONE_efuse_2k_repair_done(unsigned int uefuse_2k_repair_done); +int iSetEFUSE_REPAIR_DONE_efuse_dft_repair_done(unsigned int uefuse_dft_repair_done); +int iSetEFUSE_REPAIR_DONE_efuse_repair_done_all(unsigned int uefuse_repair_done_all); + + +#endif // __CSR_C_UNION_DEFINE_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_harden_reg_offset.h new file mode 100644 index 000000000..c51731780 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_harden_reg_offset.h @@ -0,0 +1,461 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : mpu_harden_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2021/06/26 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2021/06/26 17:53:27 Create file +// ****************************************************************************** + +#ifndef MPU_HARDEN_REG_OFFSET_H +#define MPU_HARDEN_REG_OFFSET_H + +/* MPU_HARDEN_NODE_CSR Base address of Module's Register */ +#define CSR_MPU_HARDEN_NODE_CSR_BASE (0x21F90000) + +/* **************************************************************************** */ +/* MPU_HARDEN_NODE_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MPU_HARDEN_NODE_CSR_CRG_CFG_MPU_HARDEN_0_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x0) /* MPU_HARDEN CRG的控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_CRG_CFG_MPU_HARDEN_1_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4) /* MPU_HARDEN CRG的控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_CRG_CFG_MPU_HARDEN_2_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x8) /* MPU_HARDEN CRG的控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_CRG_CFG_PCIE_RC_HARDEN_0_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0xC) /* PCIE_RC_HARDEN CRG的控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_CRG_CFG_PCIE_RC_HARDEN_1_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x10) /* PCIE_RC_HARDEN CRG的控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_PCIE_RC_POWER_CFG_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x14) /* PCIE_RC power控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_PCIE_RC_POWER_ACK_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x18) /* PCIE_RC power ACK状态寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_CRG_CFG_LCAM_HARDEN_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x1C) /* LCAM_HARDEN CRG的控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_RING_STA_MPU_HARDEN_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x20) /* RING_CRDT_STA */ +#define CSR_MPU_HARDEN_NODE_CSR_RING_STA_LCAM_HARDEN_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x24) /* RING_CRDT_STA */ +#define CSR_MPU_HARDEN_NODE_CSR_DCIP_CFG_0_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x28) /* DCIP的config寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_DCIP_CFG_1_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2C) /* DCIP的config寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_DCIP_STATUS_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x30) /* DCIP的状态寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_PAD_IN_STATUS_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x34) /* pad的一些关键配置信号状态 \ + */ +#define CSR_MPU_HARDEN_NODE_CSR_DFT_MPU_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x38) /* MPU DFT相关配置信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_HISS_CTRL_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3C) /* HISS 相关控制信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_HISS_CTRL_STATUS_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x40) /* HISS 相关状态信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_TILE_JTAG_EN_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x44) /* tile_jtag_en使能信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_CFG_MPU_CPL_ICL_MEM_CTRL_BUS_0_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x48) /* mem ctrl bus 信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_CFG_MPU_CPL_ICL_MEM_CTRL_BUS_1_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4C) /* mem ctrl bus 信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_CFG_MPU_CPL_ICL_MEM_CTRL_BUS_2_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x50) /* mem ctrl bus 信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_CFG_MPU_CPL_ICL_MEM_CTRL_BUS_3_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x54) /* mem ctrl bus 信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_CFG_MPU_CPL_ICL_MEM_CTRL_BUS_4_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x58) /* mem ctrl bus 信号 */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_0_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x200) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_1_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x204) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_2_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x208) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_3_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x20C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_4_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x210) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_5_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x214) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_6_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x218) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_7_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x21C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_8_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x220) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_9_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x224) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_10_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x228) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_11_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x22C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_12_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x230) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_13_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x234) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_14_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x238) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_15_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x23C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_16_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x240) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_17_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x244) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_18_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x248) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_19_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x24C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_20_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x250) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_21_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x254) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_22_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x258) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_23_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x25C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_24_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x260) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_25_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x264) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_26_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x268) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_27_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x26C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_28_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x270) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_29_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x274) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_30_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x278) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_31_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x27C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_32_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x280) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_33_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x284) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_34_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x288) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_35_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x28C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_36_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x290) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_37_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x294) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_38_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x298) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_39_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x29C) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_40_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2A0) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_41_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2A4) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_42_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2A8) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_43_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2AC) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_44_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2B0) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_45_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2B4) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_46_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2B8) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_47_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2BC) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_48_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2C0) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_49_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2C4) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_50_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2C8) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_51_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2CC) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_52_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2D0) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_53_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2D4) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_54_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2D8) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_55_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2DC) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_56_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2E0) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_57_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2E4) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_58_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2E8) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_59_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2EC) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_60_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2F0) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_61_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2F4) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_62_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2F8) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_2K_63_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x2FC) /* efuse 2k die id[2047:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_0_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x300) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_1_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x304) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_2_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x308) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_3_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x30C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_4_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x310) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_5_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x314) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_6_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x318) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_7_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x31C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_8_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x320) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_9_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x324) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_10_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x328) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_11_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x32C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_12_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x330) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_13_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x334) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_14_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x338) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_15_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x33C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_16_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x340) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_17_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x344) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_18_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x348) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_19_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x34C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_20_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x350) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_21_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x354) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_22_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x358) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_23_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x35C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_24_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x360) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_25_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x364) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_26_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x368) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_27_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x36C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_28_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x370) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_29_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x374) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_30_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x378) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_31_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x37C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_32_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x380) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_33_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x384) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_34_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x388) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_35_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x38C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_36_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x390) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_37_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x394) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_38_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x398) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_39_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x39C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_40_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3A0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_41_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3A4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_42_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3A8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_43_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3AC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_44_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3B0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_45_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3B4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_46_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3B8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_47_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3BC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_48_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3C0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_49_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3C4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_50_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3C8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_51_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3CC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_52_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3D0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_53_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3D4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_54_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3D8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_55_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3DC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_56_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3E0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_57_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3E4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_58_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3E8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_59_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3EC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_60_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3F0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_61_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3F4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_62_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3F8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_63_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x3FC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_64_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x400) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_65_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x404) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_66_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x408) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_67_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x40C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_68_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x410) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_69_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x414) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_70_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x418) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_71_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x41C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_72_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x420) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_73_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x424) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_74_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x428) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_75_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x42C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_76_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x430) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_77_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x434) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_78_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x438) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_79_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x43C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_80_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x440) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_81_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x444) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_82_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x448) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_83_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x44C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_84_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x450) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_85_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x454) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_86_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x458) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_87_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x45C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_88_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x460) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_89_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x464) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_90_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x468) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_91_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x46C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_92_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x470) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_93_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x474) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_94_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x478) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_95_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x47C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_96_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x480) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_97_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x484) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_98_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x488) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_99_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x48C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_100_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x490) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_101_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x494) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_102_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x498) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_103_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x49C) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_104_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4A0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_105_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4A4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_106_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4A8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_107_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4AC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_108_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4B0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_109_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4B4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_110_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4B8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_111_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4BC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_112_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4C0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_113_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4C4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_114_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4C8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_115_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4CC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_116_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4D0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_117_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4D4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_118_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4D8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_119_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4DC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_120_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4E0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_121_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4E4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_122_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4E8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_123_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4EC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_124_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4F0) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_125_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4F4) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_126_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4F8) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_DIE_ID_4K_127_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x4FC) /* efuse 4k die id[4095:0] */ +#define CSR_MPU_HARDEN_NODE_CSR_DJTAG_CLK_DIV_NUM_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x500) /* djtag clk分频寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_ICG_EN_KISDON_TAP_TCK_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x504) /* kisdon tap tck icg en使能寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_SFC_DQ3_CTRL_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x508) /* sfc dq3引脚控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_NODE_APB_PSLVERR_PAD_CFG_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x50C) /* apb pslverr 控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_JTAG_AUTH_CTRL_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x510) /* JTAG_AUTH控制寄存器 */ +#define CSR_MPU_HARDEN_NODE_CSR_JTAG_AUTH_RESULT_0_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x514) /* JTAG_AUTH_RESULT */ +#define CSR_MPU_HARDEN_NODE_CSR_JTAG_AUTH_RESULT_1_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x518) /* JTAG_AUTH_RESULT */ +#define CSR_MPU_HARDEN_NODE_CSR_JTAG_HEART_BEAT_NUM_REG (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x51C) /* JTAG_HEART_BEAT_NUM \ + */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_SW_RST_N_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x520) /* func efuse software reset */ +#define CSR_MPU_HARDEN_NODE_CSR_EFUSE_REPAIR_DONE_REG \ + (CSR_MPU_HARDEN_NODE_CSR_BASE + 0x524) /* efuse repair done stauts */ + +#endif // __CSR_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_reg_offset.h new file mode 100644 index 000000000..797fb8340 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/mpu/mpu_reg_offset.h @@ -0,0 +1,2115 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : mpu_reg_offset.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Version : V100 +// Date : +// Description : Hi 1823is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V5.1 History : 2021/01/25 14:24:23 Create +// file +// ****************************************************************************** + +#ifndef MPU_REG_OFFSET_H +#define MPU_REG_OFFSET_H + +/* ncsi_sys_csr Base address of Module's Register */ +#define CSR_NCSI_SYS_CSR_BASE (0x1833000) + +/* **************************************************************************** */ +/* ncsi_sys_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_NCSI_SYS_CSR_NCSI_SYS_VERSION_REG (CSR_NCSI_SYS_CSR_BASE + 0x0) /* NCSI版本寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_L_0_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x100) /* NCSI旁路报文的源MAC低32bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_L_1_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x104) /* NCSI旁路报文的源MAC低32bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_L_2_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x108) /* NCSI旁路报文的源MAC低32bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_L_3_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x10C) /* NCSI旁路报文的源MAC低32bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_H_0_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x110) /* NCSI旁路报文的源MAC高16bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_H_1_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x114) /* NCSI旁路报文的源MAC高16bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_H_2_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x118) /* NCSI旁路报文的源MAC高16bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_SMAC_H_3_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x11C) /* NCSI旁路报文的源MAC高16bit地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_CTRL_0_REG (CSR_NCSI_SYS_CSR_BASE + 0x120) /* NCSI旁路报文转发目的端口控制寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_CTRL_1_REG (CSR_NCSI_SYS_CSR_BASE + 0x124) /* NCSI旁路报文转发目的端口控制寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_CTRL_2_REG (CSR_NCSI_SYS_CSR_BASE + 0x128) /* NCSI旁路报文转发目的端口控制寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CHNL_CTRL_3_REG (CSR_NCSI_SYS_CSR_BASE + 0x12C) /* NCSI旁路报文转发目的端口控制寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_APP_BD_EMPTY_INTERVAL_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x130) /* 获取BD失败后，等待重新尝试读取BD的时钟周期个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_CTRL_CHKSUM_CFG_REG (CSR_NCSI_SYS_CSR_BASE + 0x134) /* 控制帧Checksum域检测配置寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_MAX_FRAME_SIZE_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x138) /* NCSI的发送报文支持的最大Size长度 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_MIN_FRAME_SIZE_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x13C) /* NCSI的发送报文支持的最小Size长度 */ +#define CSR_NCSI_SYS_CSR_NCSI_RAM_SYS_ECC_ERR_INSR_REG (CSR_NCSI_SYS_CSR_BASE + 0x140) /* RAM ECC错误注入使能信号 */ +#define CSR_NCSI_SYS_CSR_NCSI_TCMD_AFIFO_LEVEL_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x144) /* 发送命令异步FIFO的将满水线寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TXBD_FIFO_LEVEL_REG (CSR_NCSI_SYS_CSR_BASE + 0x148) /* NCSI_TXBD_FIFO的将满水线寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_WR_ACC_MAX_REG (CSR_NCSI_SYS_CSR_BASE + 0x14C) /* NCSI写OutStanding最大能力配置寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RD_ACC_MAX_REG (CSR_NCSI_SYS_CSR_BASE + 0x150) /* NCSI读OutStanding最大能力配置寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_BD_DST_MODE_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x154) /* NCSI接收到Pass-Through转发上报MPU选择寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_BD_WRD0_REG (CSR_NCSI_SYS_CSR_BASE + 0x200) /* NCSI的报文发送BD接口寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_BD_WRD1_REG (CSR_NCSI_SYS_CSR_BASE + 0x204) /* NCSI的报文发送BD接口寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_BD_WRD2_REG (CSR_NCSI_SYS_CSR_BASE + 0x208) /* NCSI的报文发送BD接口寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_BD_WRD3_REG (CSR_NCSI_SYS_CSR_BASE + 0x20C) /* NCSI的报文发送BD接口寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_APP_BD_EN_REG (CSR_NCSI_SYS_CSR_BASE + 0x210) /* NCSI向PIE预申请BD使能寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RLS_BD_ADDR_REG (CSR_NCSI_SYS_CSR_BASE + 0x214) /* NCSI向PIE释放BD的接口起始地址寄存器 \ + */ +#define CSR_NCSI_SYS_CSR_NCSI_ADD_BD_ADDR_REG (CSR_NCSI_SYS_CSR_BASE + 0x218) /* NCSI向PIE更新BD的接口起始地址寄存器 \ + */ +#define CSR_NCSI_SYS_CSR_NCSI_APP_PT_BD_ADDR_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x21C) /* NCSI向PIE申请Pass-Through报文BD起始地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_APP_CTRL_BD_ADDR_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x220) /* NCSI向PIE申请控制报文BD起始地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_LONG_LATENCY_CFG_REG (CSR_NCSI_SYS_CSR_BASE + 0x224) /* NCSI板级超长走线适配控制寄存器 \ + */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_ADD_PAD_REG (CSR_NCSI_SYS_CSR_BASE + 0x228) /* NCSI发送报文添加Pad使能寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RAM_SYS_CERR_REG (CSR_NCSI_SYS_CSR_BASE + 0x300) /* RAM ECC1bit 错误寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RAM4_ECC_ERR_ADDR_REG (CSR_NCSI_SYS_CSR_BASE + 0x304) /* RAM4 ECC错误地址寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TXBD_FIFO_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x308) /* NCSI_TXBD_FIFO的BD数据量实时值寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TXBD_FIFO_FLOW_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x30C) /* NCSI_TXBD_FIFO的上下溢标志位寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TCMD_AFIFO_OF_REG (CSR_NCSI_SYS_CSR_BASE + 0x310) /* 发送命令异步FIFO上溢标识寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TCMD_AFIFO_WCNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x314) /* 发送命令异步FIFO当前存储数据个数寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_AFIFO_WCNT_REG (CSR_NCSI_SYS_CSR_BASE + 0x318) /* TX异步FIFO当前存储数据个数寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_AFIFO_OF_REG (CSR_NCSI_SYS_CSR_BASE + 0x31C) /* TX异步FIFO上溢标识寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_PT_BD_FIFO_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x320) /* NCSI_PT_BD_FIFO的BD数据量实时值寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_PT_BD_FIFO_FLOW_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x324) /* NCSI_PT_BD_FIFO的上下溢标志位寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CTRL_BD_FIFO_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x328) /* NCSI_CTRL_BD_FIFO的BD数据量实时值寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_CTRL_BD_FIFO_FLOW_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x32C) /* NCSI_CTRL_BD_FIFO的上下溢标志位寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_AXI_OTD_CNT_REG (CSR_NCSI_SYS_CSR_BASE + 0x330) /* AXI读写Outstanding实时值寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_APP_BD_CNT_REG (CSR_NCSI_SYS_CSR_BASE + 0x400) /* 向PIE申请BD成功的描述符个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_ADD_BD_CNT_REG (CSR_NCSI_SYS_CSR_BASE + 0x404) /* 向PIE写入的待调度BD个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_TXBD_CNT_REG (CSR_NCSI_SYS_CSR_BASE + 0x408) /* 接收到的待发送BD报文个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_TXBD_EMPTY_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x40C) /* 接收到的待发送BD的empty域异常BD个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_TXBD_CODE_ERR_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x410) /* 接收到的待发送BD的Error CODE域异常BD个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_TXBD_MIN_FRAME_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x414) /* 接收到的待发送BD帧长度太小，丢弃的BD个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_TXBD_MAX_FRAME_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x418) /* 接收到的待发送BD帧长度超长，丢弃的BD个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RLS_BD_CNT_REG (CSR_NCSI_SYS_CSR_BASE + 0x41C) /* 向PIE释放BD描述符的次数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_PKT_CNT_LOW_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x420) /* 接收到Pass-Through Packet 低32bit 统计寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_PKT_CNT_HIGH_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x424) /* 接收到Pass-Through Packet 高16bit 统计寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_PKT_DISC_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x428) /* 丢弃的Pass-Through Packet统计寄存器(包括SA域匹配失败的帧、RAM ECC \ + 2bit不可纠、BD Size太小的帧、MAC层传输的FCS异常或帧长度超长的帧) */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_ERR_CNT_0_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x42C) /* 接收到的Pass-Through帧的源MAC匹配成功，但对应Channel未使能的Pass-Through帧个数（不包括MAC层传输的FCS异常或超长帧，不包括MAC层过滤的超短帧，也不包括BD \ + Size太小的帧） */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_ERR_CNT_1_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x430) /* 接收到的Pass-Through帧的源MAC匹配成功，但对应Channel未使能的Pass-Through帧个数（不包括MAC层传输的FCS异常或超长帧，不包括MAC层过滤的超短帧，也不包括BD \ + Size太小的帧） */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_ERR_CNT_2_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x434) /* 接收到的Pass-Through帧的源MAC匹配成功，但对应Channel未使能的Pass-Through帧个数（不包括MAC层传输的FCS异常或超长帧，不包括MAC层过滤的超短帧，也不包括BD \ + Size太小的帧） */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_ERR_CNT_3_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x438) /* 接收到的Pass-Through帧的源MAC匹配成功，但对应Channel未使能的Pass-Through帧个数（不包括MAC层传输的FCS异常或超长帧，不包括MAC层过滤的超短帧，也不包括BD \ + Size太小的帧） */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_PT_PKT_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + \ + 0x43C) /* 发送Pass-Through Packet统计寄存器（正确的发送给异步输出FIFO的Pass-Through报文） */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_CTRL_OK_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x440) /* 接收到正确控制帧个数统计寄存器（不包括Checksum校验错误的个数） */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_CTRL_DISC_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + \ + 0x444) /* 丢弃的控制帧个数统计寄存器（包括RAM ECC 2bit不可纠导致丢弃的帧、BD \ + Size太小的帧、MAC层传输的FCS异常或帧长度异常的帧，不包括Checksum校验错误的个数） */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_CTRL_CHKSUM_ERR_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + \ + 0x448) /* 控制帧CheckSum校验错误的个数统计寄存器（包括CheckSum域校验错误，不包括Payload Length域错误） */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_CTRL_PKT_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x44C) /* 发送控制帧统计寄存器（仅统计正确的发送给异步输出FIFO的） */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_CTRL_LEN_MISMATCH_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x450) /* 接收到的控制帧帧头指示域计算的长度与BD中的指示长度不一致，丢弃的BD个数（不包括发送BD \ + empty域异常、ERROR Code异常、帧超长/超短异常的帧） */ +#define CSR_NCSI_SYS_CSR_NCSI_TX_CTRL_LEN_SHORT_REG \ + (CSR_NCSI_SYS_CSR_BASE + \ + 0x454) /* 接收到控制帧BD信息中指示的BD长度太短，无法正确解析到Payload Length域的BD个数（不包括发送BD \ + empty域异常、ERROR Code异常、帧超长/超短异常的帧） */ +#define CSR_NCSI_SYS_CSR_NCSI_BD_BUSY_STAT_REG (CSR_NCSI_SYS_CSR_BASE + 0x458) /* 从PIE申请的BD等待被成功使用寄存器 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_OK_CNT_0_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x45C) /* 接收到的Pass-Through帧的源MAC匹配成功，且对应Channel使能的Pass-Through帧个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_OK_CNT_1_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x460) /* 接收到的Pass-Through帧的源MAC匹配成功，且对应Channel使能的Pass-Through帧个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_OK_CNT_2_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x464) /* 接收到的Pass-Through帧的源MAC匹配成功，且对应Channel使能的Pass-Through帧个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_PT_CH_OK_CNT_3_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x468) /* 接收到的Pass-Through帧的源MAC匹配成功，且对应Channel使能的Pass-Through帧个数 */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_CTRL_PAYLOAD_LEN_ERR_CNT_REG \ + (CSR_NCSI_SYS_CSR_BASE + 0x46C) /* 接收到的控制帧中payload_len域非法（或者无法获取到payload_len域的短帧），计算出来的帧长超过报文有效长度，无法计算checksum的控制帧个数（checksum使能时统计） \ + */ +#define CSR_NCSI_SYS_CSR_NCSI_RX_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x500) /* rx_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_APP_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x504) /* app_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_WSHM_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x508) /* wshm_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_ADD_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x50C) /* add_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_RSHM_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x510) /* rshm_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_RLS_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x514) /* rls_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_AXI_RCH_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x518) /* axi_rch_cur_st状态机 */ +#define CSR_NCSI_SYS_CSR_NCSI_AXI_WCH_CUR_ST_REG (CSR_NCSI_SYS_CSR_BASE + 0x51C) /* axi_wch_cur_st状态机 */ + +/* ncsi_csr Base address of Module's Register */ +#define CSR_NCSI_CSR_BASE (0x1832000) + +/* **************************************************************************** */ +/* ncsi_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_NCSI_CSR_NCSI_VERSION_REG (CSR_NCSI_CSR_BASE + 0x0) /* NCSI版本寄存器 */ +#define CSR_NCSI_CSR_NCSI_HW_ARB_BPS_REG (CSR_NCSI_CSR_BASE + 0x100) /* hardware仲裁器旁路工作模式寄存器 */ +#define CSR_NCSI_CSR_NCSI_PAUSE_EN_REG (CSR_NCSI_CSR_BASE + 0x104) /* NCSI硬件仲裁模块流控使能寄存器。 */ +#define CSR_NCSI_CSR_NCSI_HW_ARB_IPG_REG \ + (CSR_NCSI_CSR_BASE + 0x108) /* hardware仲裁器支持OP-CODE的最大帧间隙配置寄存器 */ +#define CSR_NCSI_CSR_NCSI_SEND_TOKEN_TIME_GAP_REG \ + (CSR_NCSI_CSR_BASE + 0x10C) /* hardware仲裁器完成包发送到发送TOKEN OP-CODE的时钟周期个数寄存器 */ +#define CSR_NCSI_CSR_NCSI_TR_PKT_TIMEOUT_REG \ + (CSR_NCSI_CSR_BASE + 0x110) /* 数据包准备好，等待TOKEN的最大时钟周期个数寄存器 */ +#define CSR_NCSI_CSR_NCSI_XOFF_TIMEOUT_REG \ + (CSR_NCSI_CSR_BASE + 0x114) /* NCSI发送XOFF操作码之后，即将超时等待时间寄存器 */ +#define CSR_NCSI_CSR_NCSI_PKG_ID_REG (CSR_NCSI_CSR_BASE + 0x118) /* 当前网络控制器的Package ID */ +#define CSR_NCSI_CSR_NCSI_ARB_MSTR_EVENT_REG \ + (CSR_NCSI_CSR_BASE + 0x11C) /* 启动当前网络控制器的ARB_Master分配流程控制寄存器 */ +#define CSR_NCSI_CSR_NCSI_ARB_PKG_ID_MSB_REG \ + (CSR_NCSI_CSR_BASE + 0x120) /* 当前网络控制器的Package ID发送字节序控制寄存器 */ +#define CSR_NCSI_CSR_NCSI_RCVD_LOWER_FLUSH_MODE_REG \ + (CSR_NCSI_CSR_BASE + \ + 0x124) /* 当前网络控制器在NORMAL或者XFER状态下接收到小于自身PackageID的FLUSH操作码时的处理方法控制寄存器 */ +#define CSR_NCSI_CSR_NCSI_WAIT_IDLE_RCVD_PAUSE_MODE_REG \ + (CSR_NCSI_CSR_BASE + \ + 0x128) /* 当前网络控制器在FLUSH期间WAIT_IDLE状态下出现拥塞或者接收到XON/XOFF操作码时的处理方法控制寄存器 */ +#define CSR_NCSI_CSR_NCSI_PAD_EXT_PULLDOWN_REG \ + (CSR_NCSI_CSR_BASE + 0x12C) /* 在1驱1场景下，NCSI输出PAD的对接器件外部下拉控制寄存器 */ +#define CSR_NCSI_CSR_NCSI_CODE_SYNC_REG (CSR_NCSI_CSR_BASE + 0x500) /* code_sync_cur_st状态机 */ +#define CSR_NCSI_CSR_NCSI_RX_CODE_REG (CSR_NCSI_CSR_BASE + 0x504) /* rx_code_cur_st状态机 */ +#define CSR_NCSI_CSR_NCSI_ARB_REG (CSR_NCSI_CSR_BASE + 0x508) /* arb_cur_st状态机 */ +#define CSR_NCSI_CSR_NCSI_TOKEN_REG (CSR_NCSI_CSR_BASE + 0x50C) /* token_cur_st状态机 */ +#define CSR_NCSI_CSR_NCSI_PAUSE_REG (CSR_NCSI_CSR_BASE + 0x510) /* pause_cur_st状态机 */ +#define CSR_NCSI_CSR_NCSI_TX_OP_CODE_REG (CSR_NCSI_CSR_BASE + 0x514) /* 硬件仲裁器当前输出的操作码状态 */ + +/* ncsi_mac_csr Base address of Module's Register */ +#define CSR_NCSI_MAC_CSR_BASE (0x1831000) + +/* **************************************************************************** */ +/* ncsi_mac_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_NCSI_MAC_CSR_NCSI_MAC_VERSION_REG (CSR_NCSI_MAC_CSR_BASE + 0x0) /* NCSI版本寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_INT_STATUS_REG (CSR_NCSI_MAC_CSR_BASE + 0x10) /* NCSI中断状态寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_INT_EN_REG (CSR_NCSI_MAC_CSR_BASE + 0x14) /* NCSI中断使能寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_INT_SET_REG (CSR_NCSI_MAC_CSR_BASE + 0x18) /* NCSI软件模拟中断寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_INT_RAW_STATUS_REG (CSR_NCSI_MAC_CSR_BASE + 0x1C) /* NCSI原始中断状态寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_TP_RAM_TMOD_REG (CSR_NCSI_MAC_CSR_BASE + 0x100) /* RAM模式寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_MEM_POWER_MODE_REG (CSR_NCSI_MAC_CSR_BASE + 0x104) /* RAM低功耗控制寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM_ECC_BYPASS_REG (CSR_NCSI_MAC_CSR_BASE + 0x108) /* RAM ECC功能旁路寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_HW_ARB_BPS_MAC_REG (CSR_NCSI_MAC_CSR_BASE + 0x10C) /* hardware仲裁器旁路工作模式寄存器 \ + */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_XOFF_LEN_REG (CSR_NCSI_MAC_CSR_BASE + 0x110) /* NCSI发送XON/XOFF Frame的长度 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_0_REG (CSR_NCSI_MAC_CSR_BASE + 0x114) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_1_REG (CSR_NCSI_MAC_CSR_BASE + 0x118) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_2_REG (CSR_NCSI_MAC_CSR_BASE + 0x11C) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_3_REG (CSR_NCSI_MAC_CSR_BASE + 0x120) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_4_REG (CSR_NCSI_MAC_CSR_BASE + 0x124) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_5_REG (CSR_NCSI_MAC_CSR_BASE + 0x128) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_6_REG (CSR_NCSI_MAC_CSR_BASE + 0x12C) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_7_REG (CSR_NCSI_MAC_CSR_BASE + 0x130) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_8_REG (CSR_NCSI_MAC_CSR_BASE + 0x134) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_9_REG (CSR_NCSI_MAC_CSR_BASE + 0x138) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_10_REG (CSR_NCSI_MAC_CSR_BASE + 0x13C) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_11_REG (CSR_NCSI_MAC_CSR_BASE + 0x140) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_12_REG (CSR_NCSI_MAC_CSR_BASE + 0x144) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_13_REG (CSR_NCSI_MAC_CSR_BASE + 0x148) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_14_REG (CSR_NCSI_MAC_CSR_BASE + 0x14C) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XON_FRAME_15_REG (CSR_NCSI_MAC_CSR_BASE + 0x150) /* NCSI发送XON数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_0_REG (CSR_NCSI_MAC_CSR_BASE + 0x154) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_1_REG (CSR_NCSI_MAC_CSR_BASE + 0x158) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_2_REG (CSR_NCSI_MAC_CSR_BASE + 0x15C) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_3_REG (CSR_NCSI_MAC_CSR_BASE + 0x160) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_4_REG (CSR_NCSI_MAC_CSR_BASE + 0x164) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_5_REG (CSR_NCSI_MAC_CSR_BASE + 0x168) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_6_REG (CSR_NCSI_MAC_CSR_BASE + 0x16C) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_7_REG (CSR_NCSI_MAC_CSR_BASE + 0x170) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_8_REG (CSR_NCSI_MAC_CSR_BASE + 0x174) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_9_REG (CSR_NCSI_MAC_CSR_BASE + 0x178) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_10_REG (CSR_NCSI_MAC_CSR_BASE + 0x17C) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_11_REG (CSR_NCSI_MAC_CSR_BASE + 0x180) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_12_REG (CSR_NCSI_MAC_CSR_BASE + 0x184) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_13_REG (CSR_NCSI_MAC_CSR_BASE + 0x188) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_14_REG (CSR_NCSI_MAC_CSR_BASE + 0x18C) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_XOFF_FRAME_15_REG (CSR_NCSI_MAC_CSR_BASE + 0x190) /* NCSI发送XOFF数据帧的数据域 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM_ECC_ERR_INSR_REG (CSR_NCSI_MAC_CSR_BASE + 0x194) /* RAM ECC错误注入使能信号 */ +#define CSR_NCSI_MAC_CSR_NCSI_RX_AFIFO_LEVEL_REG (CSR_NCSI_MAC_CSR_BASE + 0x198) /* RX异步FIFO的将满水线寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RX_AFIFO_AFULL_TH_REG (CSR_NCSI_MAC_CSR_BASE + 0x19C) /* RX异步FIFO的将满水线寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RCMD_AFIFO_LEVEL_REG (CSR_NCSI_MAC_CSR_BASE + 0x1A0) /* RCMD异步FIFO的将满水线寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_AFIFO_LEVEL_REG (CSR_NCSI_MAC_CSR_BASE + 0x1A4) /* TX异步FIFO的将满水线寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_DOMAIN_CHK_CNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x1A8) /* 参考时钟50M检查同步计数器周期寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_DOMAIN_STAT_REG (CSR_NCSI_MAC_CSR_BASE + 0x1AC) /* 参考50M时钟域时钟状态寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_DOMAIN_SELF_SHIELD_MODE_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x1B0) /* 参考50M时钟域时钟状态检查APB口保护模式寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM_CERR_REG (CSR_NCSI_MAC_CSR_BASE + 0x300) /* RAM ECC单比特错误寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM0_ECC_ERR_ADDR_REG (CSR_NCSI_MAC_CSR_BASE + 0x304) /* RAM0 ECC错误地址寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM1_ECC_ERR_ADDR_REG (CSR_NCSI_MAC_CSR_BASE + 0x308) /* RAM1 ECC错误地址寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM2_ECC_ERR_ADDR_REG (CSR_NCSI_MAC_CSR_BASE + 0x30C) /* RAM2 ECC错误地址寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RAM3_ECC_ERR_ADDR_REG (CSR_NCSI_MAC_CSR_BASE + 0x310) /* RAM3 ECC错误地址寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RX_AFIFO_OF_REG (CSR_NCSI_MAC_CSR_BASE + 0x314) /* RX异步FIFO上溢标识寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RX_AFIFO_RCNT_REG (CSR_NCSI_MAC_CSR_BASE + 0x318) /* RX异步FIFO当前存储数据个数寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RCMD_AFIFO_OF_REG (CSR_NCSI_MAC_CSR_BASE + 0x31C) /* RCMD异步FIFO上溢标识寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_RCMD_AFIFO_RCNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x320) /* RCMD异步FIFO当前存储数据个数寄存器 */ +#define CSR_NCSI_MAC_CSR_NCSI_DOMAIN_ERR_REG (CSR_NCSI_MAC_CSR_BASE + 0x324) /* 参考50M时钟域时钟不稳定指示状态寄存器 \ + */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_FRM_CNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x400) /* 向MAC_CORE发送的正常报文个数（不包括XON/XOFF帧） */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_FRM_ERR_CNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + \ + 0x404) /* 向MAC_CORE发送异常报文的个数（不包括XON/XOFF帧，包括Memory UNC及发送帧被截断的帧） */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_XON_CNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x408) /* 向MAC_CORE发送XON帧的个数（不包括异常的XON帧） */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_XOFF_CNT_REG (CSR_NCSI_MAC_CSR_BASE + 0x40C) /* 向MAC_CORE发送XOFF帧的个数 */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_XON_ERR_CNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x410) /* 向MAC_CORE发送异常XON帧的个数（FCS域异常） */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_EMPTY_ERR_CNT_REG \ + (CSR_NCSI_MAC_CSR_BASE + 0x414) /* NCSI向MAC发送数据时，AXI未及时返回数据，出现丢帧，FCS标识异常状态数据帧个数 */ +#define CSR_NCSI_MAC_CSR_NCSI_TX_CUR_ST_REG (CSR_NCSI_MAC_CSR_BASE + 0x500) /* tx_cur_st状态机 */ +#define CSR_NCSI_MAC_CSR_NCSI_PAUSE_FRM_CUR_ST_REG (CSR_NCSI_MAC_CSR_BASE + 0x504) /* pause_frm_cur_st状态机 */ + +/* ncsi_mac_core Base address of Module's Register */ +#define CSR_NCSI_MAC_CORE_BASE (0x1830000) + +/* **************************************************************************** */ +/* ncsi_mac_core Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_NCSI_MAC_CORE_DUPLEX_TYPE_REG (CSR_NCSI_MAC_CORE_BASE + 0x8) /* 全双工半双工模式寄存器 */ +#define CSR_NCSI_MAC_CORE_FD_FC_TYPE_REG (CSR_NCSI_MAC_CORE_BASE + 0xC) /* FD_FC_TYPE为流控帧类型域寄存器。 */ +#define CSR_NCSI_MAC_CORE_FC_TX_TIMER_REG (CSR_NCSI_MAC_CORE_BASE + 0x1C) /* FC_TX_TIMER为流控时间参数寄存器。 */ +#define CSR_NCSI_MAC_CORE_FD_FC_ADDR_LOW_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x20) /* FD_FC_ADDR_LOW为流控帧目的地址寄存器1。 */ +#define CSR_NCSI_MAC_CORE_FD_FC_ADDR_HIGH_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x24) /* FD_FC_ADDR_HIGH为流控帧目的地址寄存器2。 */ +#define CSR_NCSI_MAC_CORE_IPG_TX_TIMER_REG (CSR_NCSI_MAC_CORE_BASE + 0x30) /* IPG_TX_TIMER为发送帧间隙寄存器。 */ +#define CSR_NCSI_MAC_CORE_PAUSE_THR_REG (CSR_NCSI_MAC_CORE_BASE + 0x38) /* PAUSE_THR为发送流控帧间隙寄存器。 */ +#define CSR_NCSI_MAC_CORE_MAX_FRM_SIZE_REG (CSR_NCSI_MAC_CORE_BASE + 0x3C) /* MAX_FRM_SIZE为最大帧长寄存器。 */ +#define CSR_NCSI_MAC_CORE_PORT_MODE_REG (CSR_NCSI_MAC_CORE_BASE + 0x40) /* PORT_MODE为端口状态寄存器。 */ +#define CSR_NCSI_MAC_CORE_PORT_EN_REG (CSR_NCSI_MAC_CORE_BASE + 0x44) /* PORT_EN为通道使能寄存器。 */ +#define CSR_NCSI_MAC_CORE_PAUSE_EN_REG (CSR_NCSI_MAC_CORE_BASE + 0x48) /* PAUSE_EN为流控使能寄存器。 */ +#define CSR_NCSI_MAC_CORE_SHORT_RUNTS_THR_REG (CSR_NCSI_MAC_CORE_BASE + 0x50) /* SHORT_RUNTS_THR为超短帧界限寄存器。 \ + */ +#define CSR_NCSI_MAC_CORE_AN_NEG_STATE_REG (CSR_NCSI_MAC_CORE_BASE + 0x58) /* SGMII自协商状态寄存器 */ +#define CSR_NCSI_MAC_CORE_TX_LOCAL_PAGE_REG (CSR_NCSI_MAC_CORE_BASE + 0x5C) /* 自协商本地配置寄存器 */ +#define CSR_NCSI_MAC_CORE_TRANSMIT_CONTROL_REG (CSR_NCSI_MAC_CORE_BASE + 0x60) /* TRANSMIT_CONTROL为常用配置寄存器。 \ + */ +#define CSR_NCSI_MAC_CORE_REC_FILT_CONTROL_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x64) /* REC_FILT_CONTROL为接收帧过滤控制寄存器。 */ +#define CSR_NCSI_MAC_CORE_PTP_CONFIG_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x74) /* 发送方向IPV6的1588报文CHCECKSUM使能和1588的修正域最高位置0使能 */ +#define CSR_NCSI_MAC_CORE_RX_OCTETS_TOTAL_OK_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x80) /* RX_OCTETS_TOTAL_OK为接收有效帧的字节统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_OCTETS_BAD_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x84) /* RX_OCTETS_BAD为接收错误帧字节统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_UC_PKTS_REG (CSR_NCSI_MAC_CORE_BASE + 0x88) /* RX_UC_PKTS为MAC接收单播帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_MC_PKTS_REG (CSR_NCSI_MAC_CORE_BASE + 0x8C) /* RX_MC_PKTS为接收多播帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_BC_PKTS_REG (CSR_NCSI_MAC_CORE_BASE + 0x90) /* RX_BC_PKTS为接收的广播帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_64OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x94) /* RX_PKTS_64OCTETS为接收到帧长为64byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_65TO127OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x98) /* RX_PKTS_65TO127OCTETS为接收到帧长为65～127byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_128TO255OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x9C) /* RX_PKTS_128TO255OCTETS为接收到帧长为128～255byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_255TO511OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xA0) /* RX_PKTS_255TO511OCTETS为接收到帧长为256～511byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_512TO1023OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xA4) /* RX_PKTS_512TO1023OCTETS为接收到帧长为512～1023byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_1024TO1518OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xA8) /* RX_PKTS_1024TO1518OCTETS为接收帧长为1024～1518byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_PKTS_1519TOMAXOCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xAC) /* RX_PKTS_1519TOMAXOCTETS为接收到帧长为1519～最大byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_FCS_ERRORS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xB0) /* RX_FCS_ERRORS为接收CRC检验错误的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_TAGGED_REG (CSR_NCSI_MAC_CORE_BASE + 0xB4) /* RX_TAGGED为接收带TAG的帧统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_DATA_ERR_REG (CSR_NCSI_MAC_CORE_BASE + 0xB8) /* RX_DATA_ERR为接收数据错误帧统计寄存器。 \ + */ +#define CSR_NCSI_MAC_CORE_RX_ALIGN_ERRORS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xBC) /* RX_ALIGN_ERRORS为接收数据非字节对齐错误帧统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_LONG_ERRORS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xC0) /* RX_LONG_ERRORS为接收帧长大于允许的最大长度的帧数统计寄存器1。 */ +#define CSR_NCSI_MAC_CORE_RX_JABBER_ERRORS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xC4) /* RX_JABBER_ERRORS为接收帧长大于允许的最大长度的帧数统计寄存器2。 */ +#define CSR_NCSI_MAC_CORE_RX_PAUSE_MACCONTROL_FRAMCOUNTER_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xC8) /* RX_PAUSE_MACCONTROL_FRAMCOUNTER为接收到的流控帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_UNKNOWN_MACCONTROL_FRAMCOUNTER_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xCC) /* RX_UNKNOWN_MACCONTROL_FRAMCOUNTER为MAC接收到的非流控控制帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_VERY_LONG_ERR_CNT_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xD0) /* RX_VERY_LONG_ERR_CNT为接收到超长帧统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_RUNT_ERR_CNT_REG \ + (CSR_NCSI_MAC_CORE_BASE + \ + 0xD4) /* RX_RUNT_ERR_CNT为接收到帧长小于64byte大于等于short_runts_thr 字节的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_SHORT_ERR_CNT_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0xD8) /* RX_SHORT_ERR_CNT为接收帧长小于short_runts_thr字节的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_FILT_PKT_CNT_REG (CSR_NCSI_MAC_CORE_BASE + 0xE8) /* 接收方向过滤掉的包统计 */ +#define CSR_NCSI_MAC_CORE_RX_OCTETS_TOTAL_FILT_REG (CSR_NCSI_MAC_CORE_BASE + 0xEC) /* 接收方向过滤掉的字节统计 */ +#define CSR_NCSI_MAC_CORE_OCTETS_TRANSMITTED_OK_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x100) /* OCTETS_TRANSMITTED_OK为发送成功的好包字节数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_OCTETS_TRANSMITTED_BAD_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x104) /* OCTETS_TRANSMITTED_BAD为发送成功的坏包字节数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_UC_PKTS_REG (CSR_NCSI_MAC_CORE_BASE + 0x108) /* TX_UC_PKTS为发送的单播帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_MC_PKTS_REG (CSR_NCSI_MAC_CORE_BASE + 0x10C) /* TX_MC_PKTS为发送的多播帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_BC_PKTS_REG (CSR_NCSI_MAC_CORE_BASE + 0x110) /* TX_BC_PKTS为发送的广播帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_64OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x114) /* TX_PKTS_64OCTETS为发送帧长为64byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_65TO127OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x118) /* TX_PKTS_65TO127OCTETS为发送帧长为65～127byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_128TO255OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x11C) /* TX_PKTS_128TO255OCTETS为发送帧长为128～255byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_255TO511OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x120) /* TX_PKTS_255TO511OCTETS为发送帧长为256～511byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_512TO1023OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x124) /* TX_PKTS_512TO1023OCTETS为发送帧长为512～1023byte节的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_1024TO1518OCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x128) /* TX_PKTS_1024TO1518OCTETS为发送帧长为1024～1518byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PKTS_1519TOMAXOCTETS_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x12C) /* TX_PKTS_1519TOMAXOCTETS为发送帧长大于1519byte的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_UNDERRUN_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x150) /* TX_UNDERRUN为帧发送过程中发生内部错误而导致发送失败的次数统计。 */ +#define CSR_NCSI_MAC_CORE_TX_TAGGED_REG (CSR_NCSI_MAC_CORE_BASE + 0x154) /* TX_TAGGED为发送的VLAN帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_CRC_ERROR_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x158) /* TX_CRC_ERROR为发送帧长正确CRC错误的帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_TX_PAUSE_FRAMES_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x15C) /* TX_PAUSE_FRAMES为发送PAUSE帧数统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_LINE_LOOP_BACK_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x1A8) /* LINE_LOOP_BACK为MAC线路侧环回寄存器。 */ +#define CSR_NCSI_MAC_CORE_CF_CRC_STRIP_REG (CSR_NCSI_MAC_CORE_BASE + 0x1B0) /* CF_CRC_STRIP为CRC剥离使能寄存器。 */ +#define CSR_NCSI_MAC_CORE_MODE_CHANGE_EN_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x1B4) /* MODE_CHANGE_EN为端口模式改变使能寄存器。 */ +#define CSR_NCSI_MAC_CORE_LOOP_REG_REG (CSR_NCSI_MAC_CORE_BASE + 0x1DC) /* LOOP_REG为环回补充寄存器。 */ +#define CSR_NCSI_MAC_CORE_RECV_CONTROL_REG (CSR_NCSI_MAC_CORE_BASE + 0x1E0) /* RECV_CONTROL为接收控制寄存器。 */ +#define CSR_NCSI_MAC_CORE_VLAN_CODE_REG (CSR_NCSI_MAC_CORE_BASE + 0x1E8) /* VLAN_CODE为VLAN Code寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_OVERRUN_CNT_REG (CSR_NCSI_MAC_CORE_BASE + 0x1EC) /* RX_OVERRUN_CNT为FIFO溢出统计寄存器。 \ + */ +#define CSR_NCSI_MAC_CORE_RX_LENGTHFIELD_ERR_CNT_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x1F4) /* RX_LENGTHFIELD_ERR_CNT为含PAD帧统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_RX_FAIL_COMMA_CNT_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x1F8) /* RX_FAIL_COMMA_CNT为字节定界COMMA统计寄存器。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_0_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x200) /* STATION_ADDR_LOW为本机MAC地址0寄存器1。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_0_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x204) /* STATION_ADDR_HIGH为本机MAC地址0寄存器2。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_1_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x208) /* STATION_ADDR_LOW为本机MAC地址1寄存器1。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_1_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x20C) /* STATION_ADDR_HIGH为本机MAC地址1寄存器2。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_2_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x210) /* STATION_ADDR_LOW为本机MAC地址2寄存器1。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_2_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x214) /* STATION_ADDR_HIGH为本机MAC地址2寄存器2。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_3_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x218) /* STATION_ADDR_LOW为本机MAC地址3寄存器1。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_3_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x21C) /* STATION_ADDR_HIGH为本机MAC地址3寄存器2。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_4_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x220) /* STATION_ADDR_LOW为本机MAC地址4寄存器1。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_4_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x224) /* STATION_ADDR_HIGH为本机MAC地址4寄存器2。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_5_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x228) /* STATION_ADDR_LOW为本机MAC地址5寄存器1。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_5_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x22C) /* STATION_ADDR_HIGH为本机MAC地址5寄存器2。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_MSK_0_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x230) /* STATION_ADDR_LOW为本机MAC地址0寄存器1的掩码。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_MSK_0_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x234) /* STATION_ADDR_HIGH为本机MAC地址0寄存器2的掩码。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_LOW_MSK_1_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x238) /* STATION_ADDR_LOW为本机MAC地址1寄存器1的掩码。 */ +#define CSR_NCSI_MAC_CORE_STATION_ADDR_HIGH_MSK_1_REG \ + (CSR_NCSI_MAC_CORE_BASE + 0x23C) /* STATION_ADDR_HIGH为本机MAC地址1寄存器2的掩码。 */ +#define CSR_NCSI_MAC_CORE_MAC_SKIP_LEN_REG (CSR_NCSI_MAC_CORE_BASE + 0x240) /* SKIP_LEN为报文头不解析字段长度。 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_0_REG (CSR_NCSI_MAC_CORE_BASE + 0x244) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_1_REG (CSR_NCSI_MAC_CORE_BASE + 0x248) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_2_REG (CSR_NCSI_MAC_CORE_BASE + 0x24C) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_3_REG (CSR_NCSI_MAC_CORE_BASE + 0x250) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_4_REG (CSR_NCSI_MAC_CORE_BASE + 0x254) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_5_REG (CSR_NCSI_MAC_CORE_BASE + 0x258) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_6_REG (CSR_NCSI_MAC_CORE_BASE + 0x25C) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_7_REG (CSR_NCSI_MAC_CORE_BASE + 0x260) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_8_REG (CSR_NCSI_MAC_CORE_BASE + 0x264) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_9_REG (CSR_NCSI_MAC_CORE_BASE + 0x268) /* 1588发送方向debug时，抓到包的数据 */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_10_REG (CSR_NCSI_MAC_CORE_BASE + 0x26C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_11_REG (CSR_NCSI_MAC_CORE_BASE + 0x270) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_12_REG (CSR_NCSI_MAC_CORE_BASE + 0x274) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_13_REG (CSR_NCSI_MAC_CORE_BASE + 0x278) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_14_REG (CSR_NCSI_MAC_CORE_BASE + 0x27C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_15_REG (CSR_NCSI_MAC_CORE_BASE + 0x280) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_16_REG (CSR_NCSI_MAC_CORE_BASE + 0x284) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_17_REG (CSR_NCSI_MAC_CORE_BASE + 0x288) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_18_REG (CSR_NCSI_MAC_CORE_BASE + 0x28C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_19_REG (CSR_NCSI_MAC_CORE_BASE + 0x290) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_20_REG (CSR_NCSI_MAC_CORE_BASE + 0x294) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_21_REG (CSR_NCSI_MAC_CORE_BASE + 0x298) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_22_REG (CSR_NCSI_MAC_CORE_BASE + 0x29C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_23_REG (CSR_NCSI_MAC_CORE_BASE + 0x2A0) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_24_REG (CSR_NCSI_MAC_CORE_BASE + 0x2A4) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_25_REG (CSR_NCSI_MAC_CORE_BASE + 0x2A8) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_26_REG (CSR_NCSI_MAC_CORE_BASE + 0x2AC) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_27_REG (CSR_NCSI_MAC_CORE_BASE + 0x2B0) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_28_REG (CSR_NCSI_MAC_CORE_BASE + 0x2B4) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_29_REG (CSR_NCSI_MAC_CORE_BASE + 0x2B8) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_30_REG (CSR_NCSI_MAC_CORE_BASE + 0x2BC) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_31_REG (CSR_NCSI_MAC_CORE_BASE + 0x2C0) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_32_REG (CSR_NCSI_MAC_CORE_BASE + 0x2C4) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_33_REG (CSR_NCSI_MAC_CORE_BASE + 0x2C8) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_34_REG (CSR_NCSI_MAC_CORE_BASE + 0x2CC) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_35_REG (CSR_NCSI_MAC_CORE_BASE + 0x2D0) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_36_REG (CSR_NCSI_MAC_CORE_BASE + 0x2D4) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_37_REG (CSR_NCSI_MAC_CORE_BASE + 0x2D8) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_38_REG (CSR_NCSI_MAC_CORE_BASE + 0x2DC) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_39_REG (CSR_NCSI_MAC_CORE_BASE + 0x2E0) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_40_REG (CSR_NCSI_MAC_CORE_BASE + 0x2E4) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_41_REG (CSR_NCSI_MAC_CORE_BASE + 0x2E8) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_42_REG (CSR_NCSI_MAC_CORE_BASE + 0x2EC) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_43_REG (CSR_NCSI_MAC_CORE_BASE + 0x2F0) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_44_REG (CSR_NCSI_MAC_CORE_BASE + 0x2F4) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_45_REG (CSR_NCSI_MAC_CORE_BASE + 0x2F8) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_46_REG (CSR_NCSI_MAC_CORE_BASE + 0x2FC) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_47_REG (CSR_NCSI_MAC_CORE_BASE + 0x300) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_48_REG (CSR_NCSI_MAC_CORE_BASE + 0x304) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_49_REG (CSR_NCSI_MAC_CORE_BASE + 0x308) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_50_REG (CSR_NCSI_MAC_CORE_BASE + 0x30C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_51_REG (CSR_NCSI_MAC_CORE_BASE + 0x310) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_52_REG (CSR_NCSI_MAC_CORE_BASE + 0x314) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_53_REG (CSR_NCSI_MAC_CORE_BASE + 0x318) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_54_REG (CSR_NCSI_MAC_CORE_BASE + 0x31C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_55_REG (CSR_NCSI_MAC_CORE_BASE + 0x320) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_56_REG (CSR_NCSI_MAC_CORE_BASE + 0x324) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_57_REG (CSR_NCSI_MAC_CORE_BASE + 0x328) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_58_REG (CSR_NCSI_MAC_CORE_BASE + 0x32C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_59_REG (CSR_NCSI_MAC_CORE_BASE + 0x330) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_60_REG (CSR_NCSI_MAC_CORE_BASE + 0x334) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_61_REG (CSR_NCSI_MAC_CORE_BASE + 0x338) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_62_REG (CSR_NCSI_MAC_CORE_BASE + 0x33C) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_RD_DATA_63_REG (CSR_NCSI_MAC_CORE_BASE + 0x340) /* 1588发送方向debug时，抓到包的数据 \ + */ +#define CSR_NCSI_MAC_CORE_DEBUG_PKT_PTR_REG (CSR_NCSI_MAC_CORE_BASE + 0x344) /* 报文指针寄存器 */ +#define CSR_NCSI_MAC_CORE_DEBUG_EN_REG (CSR_NCSI_MAC_CORE_BASE + 0x348) /* 捕获使能 */ +#define CSR_NCSI_MAC_CORE_INTR_STATE_REG (CSR_NCSI_MAC_CORE_BASE + 0x34C) /* 中断状态 */ +#define CSR_NCSI_MAC_CORE_INTR_CLR_REG (CSR_NCSI_MAC_CORE_BASE + 0x350) /* 中断清除寄存器 */ +#define CSR_NCSI_MAC_CORE_INTR_MSK_REG (CSR_NCSI_MAC_CORE_BASE + 0x354) /* 中断屏蔽寄存器 */ +#define CSR_NCSI_MAC_CORE_SEQ_ID_REG (CSR_NCSI_MAC_CORE_BASE + 0x358) /* 捕获的sequence ID和时间戳的[79:64] */ +#define CSR_NCSI_MAC_CORE_STP_63_TO_32_REG (CSR_NCSI_MAC_CORE_BASE + 0x35C) /* 上报时间戳的[63:32] */ +#define CSR_NCSI_MAC_CORE_STP_31_TO_0_REG (CSR_NCSI_MAC_CORE_BASE + 0x360) /* 上报时间戳的[31:0] */ +#define CSR_NCSI_MAC_CORE_DBG_GRP0_VLD_WORDS_REG (CSR_NCSI_MAC_CORE_BASE + 0x364) /* 第一组RAM中捕获的有效字数 */ +#define CSR_NCSI_MAC_CORE_DBG_GRP1_VLD_WORDS_REG (CSR_NCSI_MAC_CORE_BASE + 0x368) /* 第二组RAM中捕获的有效字数 */ + +/* CLK_DET0 Base address of Module's Register */ +#define CSR_CLK_DET0_BASE (0x1829000) + +/* **************************************************************************** */ +/* CLK_DET0 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CLK_DET0_CKD_INT_STA_REG (CSR_CLK_DET0_BASE + 0x10) /* 时钟中断状态寄存器 */ +#define CSR_CLK_DET0_PLL_INT_STA_REG (CSR_CLK_DET0_BASE + 0x14) /* PLL中断状态寄存器 */ +#define CSR_CLK_DET0_CKD_INT_MASK_REG (CSR_CLK_DET0_BASE + 0x20) /* 时钟错误中断屏蔽寄存器 */ +#define CSR_CLK_DET0_CKD_PLL_INT_MASK_REG (CSR_CLK_DET0_BASE + 0x24) /* PLL中断屏蔽寄存器 */ +#define CSR_CLK_DET0_CKD_INT_SET_REG (CSR_CLK_DET0_BASE + 0x30) /* 软件模拟时钟错误中断 */ +#define CSR_CLK_DET0_CKD_PLL_INT_SET_REG (CSR_CLK_DET0_BASE + 0x34) /* 软件模拟PLL中断 */ +#define CSR_CLK_DET0_CKD_ERR_STA_REG (CSR_CLK_DET0_BASE + 0x40) /* 时钟错误状态寄存器 */ +#define CSR_CLK_DET0_PLL_LOCK_STA_REG (CSR_CLK_DET0_BASE + 0x44) /* PLL 丢锁状态寄存器 */ +#define CSR_CLK_DET0_CKD_OK_INT_STA_REG (CSR_CLK_DET0_BASE + 0x48) /* 时钟恢复中断状态寄存器 */ +#define CSR_CLK_DET0_CKD_OK_INT_MASK_REG (CSR_CLK_DET0_BASE + 0x4C) /* 时钟恢复中断屏蔽寄存器 */ +#define CSR_CLK_DET0_CKD_OK_INT_SET_REG (CSR_CLK_DET0_BASE + 0x50) /* 软件模拟时钟恢复中断 */ +#define CSR_CLK_DET0_CKD_CLK_OK_STA_REG (CSR_CLK_DET0_BASE + 0x54) /* 时钟恢复状态寄存器 */ +#define CSR_CLK_DET0_DET_CLK_EN_REG (CSR_CLK_DET0_BASE + 0xA0) /* 时钟检查使能寄存器 */ +#define CSR_CLK_DET0_DET_PLL_EN_REG (CSR_CLK_DET0_BASE + 0xA4) /* PLL锁定检查使能寄存器 */ +#define CSR_CLK_DET0_DET_CLK_OK_EN_REG (CSR_CLK_DET0_BASE + 0xA8) /* PLL锁定检查使能寄存器 */ +#define CSR_CLK_DET0_DET_CLK_OK_CNT_REG (CSR_CLK_DET0_BASE + 0xAC) /* 时钟恢复正常次数 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_0_REG (CSR_CLK_DET0_BASE + 0xB0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_1_REG (CSR_CLK_DET0_BASE + 0xB4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_2_REG (CSR_CLK_DET0_BASE + 0xB8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_3_REG (CSR_CLK_DET0_BASE + 0xBC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_4_REG (CSR_CLK_DET0_BASE + 0xC0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_5_REG (CSR_CLK_DET0_BASE + 0xC4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_6_REG (CSR_CLK_DET0_BASE + 0xC8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_7_REG (CSR_CLK_DET0_BASE + 0xCC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_8_REG (CSR_CLK_DET0_BASE + 0xD0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_9_REG (CSR_CLK_DET0_BASE + 0xD4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_10_REG (CSR_CLK_DET0_BASE + 0xD8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_11_REG (CSR_CLK_DET0_BASE + 0xDC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_12_REG (CSR_CLK_DET0_BASE + 0xE0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_13_REG (CSR_CLK_DET0_BASE + 0xE4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_14_REG (CSR_CLK_DET0_BASE + 0xE8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_15_REG (CSR_CLK_DET0_BASE + 0xEC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_16_REG (CSR_CLK_DET0_BASE + 0xF0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_17_REG (CSR_CLK_DET0_BASE + 0xF4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_18_REG (CSR_CLK_DET0_BASE + 0xF8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_19_REG (CSR_CLK_DET0_BASE + 0xFC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_20_REG (CSR_CLK_DET0_BASE + 0x100) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_21_REG (CSR_CLK_DET0_BASE + 0x104) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_22_REG (CSR_CLK_DET0_BASE + 0x108) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_23_REG (CSR_CLK_DET0_BASE + 0x10C) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_24_REG (CSR_CLK_DET0_BASE + 0x110) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_25_REG (CSR_CLK_DET0_BASE + 0x114) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_26_REG (CSR_CLK_DET0_BASE + 0x118) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_27_REG (CSR_CLK_DET0_BASE + 0x11C) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_28_REG (CSR_CLK_DET0_BASE + 0x120) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_29_REG (CSR_CLK_DET0_BASE + 0x124) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_30_REG (CSR_CLK_DET0_BASE + 0x128) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET0_DET_CLK_MIN_WIDTH_31_REG (CSR_CLK_DET0_BASE + 0x12C) /* 时钟最小宽度配置寄存器 */ + +/* CLK_DET1 Base address of Module's Register */ +#define CSR_CLK_DET1_BASE (0x182B000) + +/* **************************************************************************** */ +/* CLK_DET1 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CLK_DET1_CKD_INT_STA_REG (CSR_CLK_DET1_BASE + 0x10) /* 时钟中断状态寄存器 */ +#define CSR_CLK_DET1_PLL_INT_STA_REG (CSR_CLK_DET1_BASE + 0x14) /* PLL中断状态寄存器 */ +#define CSR_CLK_DET1_CKD_INT_MASK_REG (CSR_CLK_DET1_BASE + 0x20) /* 时钟错误中断屏蔽寄存器 */ +#define CSR_CLK_DET1_CKD_PLL_INT_MASK_REG (CSR_CLK_DET1_BASE + 0x24) /* PLL中断屏蔽寄存器 */ +#define CSR_CLK_DET1_CKD_INT_SET_REG (CSR_CLK_DET1_BASE + 0x30) /* 软件模拟时钟错误中断 */ +#define CSR_CLK_DET1_CKD_PLL_INT_SET_REG (CSR_CLK_DET1_BASE + 0x34) /* 软件模拟PLL中断 */ +#define CSR_CLK_DET1_CKD_ERR_STA_REG (CSR_CLK_DET1_BASE + 0x40) /* 时钟错误状态寄存器 */ +#define CSR_CLK_DET1_PLL_LOCK_STA_REG (CSR_CLK_DET1_BASE + 0x44) /* PLL 丢锁状态寄存器 */ +#define CSR_CLK_DET1_CKD_OK_INT_STA_REG (CSR_CLK_DET1_BASE + 0x48) /* 时钟恢复中断状态寄存器 */ +#define CSR_CLK_DET1_CKD_OK_INT_MASK_REG (CSR_CLK_DET1_BASE + 0x4C) /* 时钟恢复中断屏蔽寄存器 */ +#define CSR_CLK_DET1_CKD_OK_INT_SET_REG (CSR_CLK_DET1_BASE + 0x50) /* 软件模拟时钟恢复中断 */ +#define CSR_CLK_DET1_CKD_CLK_OK_STA_REG (CSR_CLK_DET1_BASE + 0x54) /* 时钟恢复状态寄存器 */ +#define CSR_CLK_DET1_DET_CLK_EN_REG (CSR_CLK_DET1_BASE + 0xA0) /* 时钟检查使能寄存器 */ +#define CSR_CLK_DET1_DET_PLL_EN_REG (CSR_CLK_DET1_BASE + 0xA4) /* PLL锁定检查使能寄存器 */ +#define CSR_CLK_DET1_DET_CLK_OK_EN_REG (CSR_CLK_DET1_BASE + 0xA8) /* PLL锁定检查使能寄存器 */ +#define CSR_CLK_DET1_DET_CLK_OK_CNT_REG (CSR_CLK_DET1_BASE + 0xAC) /* 时钟恢复正常次数 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_0_REG (CSR_CLK_DET1_BASE + 0xB0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_1_REG (CSR_CLK_DET1_BASE + 0xB4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_2_REG (CSR_CLK_DET1_BASE + 0xB8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_3_REG (CSR_CLK_DET1_BASE + 0xBC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_4_REG (CSR_CLK_DET1_BASE + 0xC0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_5_REG (CSR_CLK_DET1_BASE + 0xC4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_6_REG (CSR_CLK_DET1_BASE + 0xC8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_7_REG (CSR_CLK_DET1_BASE + 0xCC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_8_REG (CSR_CLK_DET1_BASE + 0xD0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_9_REG (CSR_CLK_DET1_BASE + 0xD4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_10_REG (CSR_CLK_DET1_BASE + 0xD8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_11_REG (CSR_CLK_DET1_BASE + 0xDC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_12_REG (CSR_CLK_DET1_BASE + 0xE0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_13_REG (CSR_CLK_DET1_BASE + 0xE4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_14_REG (CSR_CLK_DET1_BASE + 0xE8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_15_REG (CSR_CLK_DET1_BASE + 0xEC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_16_REG (CSR_CLK_DET1_BASE + 0xF0) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_17_REG (CSR_CLK_DET1_BASE + 0xF4) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_18_REG (CSR_CLK_DET1_BASE + 0xF8) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_19_REG (CSR_CLK_DET1_BASE + 0xFC) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_20_REG (CSR_CLK_DET1_BASE + 0x100) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_21_REG (CSR_CLK_DET1_BASE + 0x104) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_22_REG (CSR_CLK_DET1_BASE + 0x108) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_23_REG (CSR_CLK_DET1_BASE + 0x10C) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_24_REG (CSR_CLK_DET1_BASE + 0x110) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_25_REG (CSR_CLK_DET1_BASE + 0x114) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_26_REG (CSR_CLK_DET1_BASE + 0x118) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_27_REG (CSR_CLK_DET1_BASE + 0x11C) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_28_REG (CSR_CLK_DET1_BASE + 0x120) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_29_REG (CSR_CLK_DET1_BASE + 0x124) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_30_REG (CSR_CLK_DET1_BASE + 0x128) /* 时钟最小宽度配置寄存器 */ +#define CSR_CLK_DET1_DET_CLK_MIN_WIDTH_31_REG (CSR_CLK_DET1_BASE + 0x12C) /* 时钟最小宽度配置寄存器 */ + +/* I2C2AXI Base address of Module's Register */ +#define CSR_I2C2AXI_BASE (0x0) + +/* **************************************************************************** */ +/* I2C2AXI Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_I2C2AXI_I2C_AWADDR0_REG (CSR_I2C2AXI_BASE + 0x0) /* AWADDR[7:0] */ +#define CSR_I2C2AXI_I2C_AWADDR1_REG (CSR_I2C2AXI_BASE + 0x1) /* AWADDR[15:8] */ +#define CSR_I2C2AXI_I2C_AWADDR2_REG (CSR_I2C2AXI_BASE + 0x2) /* AWADDR[23:16] */ +#define CSR_I2C2AXI_I2C_AWADDR3_REG (CSR_I2C2AXI_BASE + 0x3) /* AWADDR[31:24] */ +#define CSR_I2C2AXI_I2C_WDATA0_REG (CSR_I2C2AXI_BASE + 0x4) /* WDATA[7:0] */ +#define CSR_I2C2AXI_I2C_WDATA1_REG (CSR_I2C2AXI_BASE + 0x5) /* WDATA[15:8] */ +#define CSR_I2C2AXI_I2C_WDATA2_REG (CSR_I2C2AXI_BASE + 0x6) /* WDATA[23:16] */ +#define CSR_I2C2AXI_I2C_WDATA3_REG (CSR_I2C2AXI_BASE + 0x7) /* WDATA[31:24] */ +#define CSR_I2C2AXI_I2C_WDATA4_REG (CSR_I2C2AXI_BASE + 0x8) /* WDATA[39:32] */ +#define CSR_I2C2AXI_I2C_WDATA5_REG (CSR_I2C2AXI_BASE + 0x9) /* WDATA[47:40] */ +#define CSR_I2C2AXI_I2C_WDATA6_REG (CSR_I2C2AXI_BASE + 0xA) /* WDATA[55:48] */ +#define CSR_I2C2AXI_I2C_WDATA7_REG (CSR_I2C2AXI_BASE + 0xB) /* WDATA[63:56] */ +#define CSR_I2C2AXI_I2C_WSTRB_REG (CSR_I2C2AXI_BASE + 0xC) /* 寄存WSTRB[7:0]信号 */ +#define CSR_I2C2AXI_I2C_AWSIZE_REG (CSR_I2C2AXI_BASE + 0xD) /* 低3位寄存AWSIZE[2:0] */ +#define CSR_I2C2AXI_I2C_AWID_REG (CSR_I2C2AXI_BASE + 0xE) /* 低4位寄存AWID[3:0] */ +#define CSR_I2C2AXI_I2C_AWLOCK_REG (CSR_I2C2AXI_BASE + 0xF) /* 低2位寄存AWLOCK[1:0] */ +#define CSR_I2C2AXI_I2C_AWCACHE_REG (CSR_I2C2AXI_BASE + 0x10) /* 低4位寄存AWCACHE[3:0] */ +#define CSR_I2C2AXI_I2C_AWPROT_REG (CSR_I2C2AXI_BASE + 0x11) /* 低3位寄存AWPORT[2:0]，高5位禁用。 */ +#define CSR_I2C2AXI_I2C_ARADDR0_REG (CSR_I2C2AXI_BASE + 0x30) /* 寄存ARADDR[31:0]的0~7bit，即ARADDR[7:0]。 */ +#define CSR_I2C2AXI_I2C_ARADDR1_REG (CSR_I2C2AXI_BASE + 0x31) /* 寄存ARADDR[31:0]的8~15bit，即ARADDR[15:8]。 */ +#define CSR_I2C2AXI_I2C_ARADDR2_REG (CSR_I2C2AXI_BASE + 0x32) /* 寄存ARADDR[31:0]的16~23bit，即ARADDR[23:16]。 */ +#define CSR_I2C2AXI_I2C_ARADDR3_REG (CSR_I2C2AXI_BASE + 0x33) /* 寄存ARADDR[31:0]的24~31bit，即ARADDR[31:24]。 */ +#define CSR_I2C2AXI_I2C_ARSIZE_REG (CSR_I2C2AXI_BASE + 0x34) /* 低3位寄存ARSIZE[2:0] ，高5位禁用。 */ +#define CSR_I2C2AXI_I2C_ARID_REG (CSR_I2C2AXI_BASE + 0x35) /* 低4位寄存ARID[3:0]，高4位禁用。 */ +#define CSR_I2C2AXI_I2C_ARLOCK_REG (CSR_I2C2AXI_BASE + 0x36) /* 低2位寄存ARLOCK[1:0] ，高6位禁用。 */ +#define CSR_I2C2AXI_I2C_ARCACHE_REG (CSR_I2C2AXI_BASE + 0x37) /* 低4位寄存ARCACHE[3:0]，高4位禁用。 */ +#define CSR_I2C2AXI_I2C_ARPROT_REG (CSR_I2C2AXI_BASE + 0x38) /* 低3位寄存ARPORT[2:0] ，高5位禁用。 */ +#define CSR_I2C2AXI_AXI_BRESP_REG (CSR_I2C2AXI_BASE + 0x60) /* 低2位寄存BRESP[1:0] */ +#define CSR_I2C2AXI_AXI_BID_REG (CSR_I2C2AXI_BASE + 0x61) /* 寄存AXI master写应答ID */ +#define CSR_I2C2AXI_AXI_RRESP_REG (CSR_I2C2AXI_BASE + 0x70) /* 低2位寄存RRESP[1:0] */ +#define CSR_I2C2AXI_AXI_RDATA0_REG (CSR_I2C2AXI_BASE + 0x71) /* RDATA[7:0] */ +#define CSR_I2C2AXI_AXI_RDATA1_REG (CSR_I2C2AXI_BASE + 0x72) /* RDATA[15:8] */ +#define CSR_I2C2AXI_AXI_RDATA2_REG (CSR_I2C2AXI_BASE + 0x73) /* RDATA[23:16] */ +#define CSR_I2C2AXI_AXI_RDATA3_REG (CSR_I2C2AXI_BASE + 0x74) /* RDATA[31:24] */ +#define CSR_I2C2AXI_AXI_RDATA4_REG (CSR_I2C2AXI_BASE + 0x75) /* RDATA[39:32] */ +#define CSR_I2C2AXI_AXI_RDATA5_REG (CSR_I2C2AXI_BASE + 0x76) /* RDATA[47:40] */ +#define CSR_I2C2AXI_AXI_RDATA6_REG (CSR_I2C2AXI_BASE + 0x77) /* RDATA[55:48] */ +#define CSR_I2C2AXI_AXI_RDATA7_REG (CSR_I2C2AXI_BASE + 0x78) /* RDATA[63:56] */ +#define CSR_I2C2AXI_AXI_RID_REG (CSR_I2C2AXI_BASE + 0x79) /* 寄存AXI master读数据ID */ +#define CSR_I2C2AXI_WR_RD_CMD_REG \ + (CSR_I2C2AXI_BASE + 0x80) /* AXI master读/写操作选择存器，0xAA表示读操作，0x55表示写操作 */ +#define CSR_I2C2AXI_VERSION_NUMBER_REG (CSR_I2C2AXI_BASE + 0x90) /* 版本号寄存器 */ + +/* SPI2AXI Base address of Module's Register */ +#define CSR_SPI2AXI_BASE (0x1806000) + +/* **************************************************************************** */ +/* SPI2AXI Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SPI2AXI_SPI_RX_ST_REG (CSR_SPI2AXI_BASE + 0x0) /* 写操作剩余空间状态。（Slave Command Status0） */ +#define CSR_SPI2AXI_SPI_TX_ST_REG (CSR_SPI2AXI_BASE + 0x4) /* 读操作有效数据状态。（Slave Command Status1） */ +#define CSR_SPI2AXI_SPI_BUF_SIZE_REG (CSR_SPI2AXI_BASE + 0x8) /* SPI内部每个Buffer 的大小。（Slave Command Status2） \ + */ +#define CSR_SPI2AXI_INT_ST_REG (CSR_SPI2AXI_BASE + 0x10) /* 中断状态 */ +#define CSR_SPI2AXI_INT_CTL_REG (CSR_SPI2AXI_BASE + 0x14) /* 中断控制寄存器。 */ +#define CSR_SPI2AXI_INT_COLL_REG (CSR_SPI2AXI_BASE + 0x18) /* 中断聚合配置寄存器。 */ +#define CSR_SPI2AXI_SPI_INTR_REG (CSR_SPI2AXI_BASE + 0x1C) /* 外部中断置位寄存器。 */ +#define CSR_SPI2AXI_SPI_BD_BA_REG (CSR_SPI2AXI_BASE + 0x20) /* RX/TX的缓存的基地址。 */ +#define CSR_SPI2AXI_SPI_RXBD_POOL_REG (CSR_SPI2AXI_BASE + 0x30) /* 接收方向BD资源池 */ +#define CSR_SPI2AXI_SPI_TXBD_POOL_REG (CSR_SPI2AXI_BASE + 0x34) /* 发送方向BD资源池 */ +#define CSR_SPI2AXI_SPI_RXBD_IF_REG (CSR_SPI2AXI_BASE + 0x38) /* 接收方向BD读取接口 */ +#define CSR_SPI2AXI_SPI_TXBD_IF_REG (CSR_SPI2AXI_BASE + 0x3C) /* 发送方向BD发送接口 */ +#define CSR_SPI2AXI_SPI_BD_ST_REG (CSR_SPI2AXI_BASE + 0x40) /* BD的相关状态 */ +#define CSR_SPI2AXI_SPI_ERR_ST_REG (CSR_SPI2AXI_BASE + 0x44) /* SPI错误状态指示寄存器。该寄存器写操作清除所有状态。 */ + +/* ring2axi_csr Base address of Module's Register */ +#define CSR_RING2AXI_CSR_BASE (0x181A000) + +/* **************************************************************************** */ +/* ring2axi_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_RING2AXI_CSR_RING2AXI_INT_STATUS_REG (CSR_RING2AXI_CSR_BASE + 0x10) /* RING2AXI中断状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_INT_EN_REG (CSR_RING2AXI_CSR_BASE + 0x20) /* RING2AXI中断使能寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_INT_SET_REG (CSR_RING2AXI_CSR_BASE + 0x30) /* RING2AXI软件模拟中断寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_INT_RAW_STATUS_REG (CSR_RING2AXI_CSR_BASE + 0x40) /* RING2AXI原始中断状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_MODE_REG (CSR_RING2AXI_CSR_BASE + 0xA0) /* RING Buffer功能寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_BA_REG (CSR_RING2AXI_CSR_BASE + 0xA4) /* Ring Buffer基地址 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_CI_REG (CSR_RING2AXI_CSR_BASE + 0xA8) /* Ring Buffer的CI指针寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_AFULL_TH_REG \ + (CSR_RING2AXI_CSR_BASE + 0xAC) /* Ring Buffer的将满置1水线寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_AFULL_CLR_TH_REG \ + (CSR_RING2AXI_CSR_BASE + 0xB0) /* Ring Buffer的将满清零水线寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_TIMEOUT_REG \ + (CSR_RING2AXI_CSR_BASE + 0xB4) /* Ring Buffer非空超时配置寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MSGBUF_TIMEOUT_CLR_REG \ + (CSR_RING2AXI_CSR_BASE + 0xB8) /* Ring Buffer非空超时计时器清零寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_MEM_API_ENDIAN_SEL_REG \ + (CSR_RING2AXI_CSR_BASE + 0xBC) /* Store/Load mpu Memory API命令大小端选择寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_API_MAX_INDEX_REG \ + (CSR_RING2AXI_CSR_BASE + 0xC0) /* RING侧发送API命令允许访问的最大地址 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_BW_REG \ + (CSR_RING2AXI_CSR_BASE + 0xC4) /* AXI Master的读、写Outstanding最大能力寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_API_FLIT_CNT_INIT_REG \ + (CSR_RING2AXI_CSR_BASE + 0xC8) /* RING侧接收、发送DFX统计计数器的工作模式选择寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_RX_DISC_FLIT_CNT_CLR_REG \ + (CSR_RING2AXI_CSR_BASE + 0xCC) /* 丢弃的Flit个数统计计数器清零寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_CFG_RX_DEALED_FLIT_CNT_CLR_REG \ + (CSR_RING2AXI_CSR_BASE + 0xD0) /* 接收到正常发起了AXI操作的API的Flit个数统计计数器清零寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_FIFO_CFG_REG (CSR_RING2AXI_CSR_BASE + 0xD4) /* 接口FIFO将满水线配置寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_MSGBUF_PI_REG (CSR_RING2AXI_CSR_BASE + 0x200) /* Ring Buffer的PI指针 */ +#define CSR_RING2AXI_CSR_RING2AXI_MSGBUF_STAT_REG (CSR_RING2AXI_CSR_BASE + 0x204) /* Ring Buffer状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_MSGBUF_OF_UF_REG (CSR_RING2AXI_CSR_BASE + 0x208) /* Ring Buffer上、下溢寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_INNER_BUF_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x20C) /* 内部计算PrintMsg地址缓存状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_INNER_BUF_OF_REG \ + (CSR_RING2AXI_CSR_BASE + 0x210) /* 内部计算PrintMsg地址缓存上溢寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_RX_API_FLIT_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x214) /* 接收到API或者Flit个数统计寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_TX_API_FLIT_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x218) /* 发送API或者Flit个数统计寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_RD_LATENCY_REG \ + (CSR_RING2AXI_CSR_BASE + 0x21C) /* AXI master最后1个Burst读延时实时值寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_WR_LATENCY_REG \ + (CSR_RING2AXI_CSR_BASE + 0x220) /* AXI master最后1个Burst写延时实时值寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_RD_LATENCY_MIN_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x224) /* AXI master的burst读延迟的最小值 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_WR_LATENCY_MIN_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x228) /* AXI master的burst写延迟的最小值 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_RD_LATENCY_MAX_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x22C) /* AXI master的burst读延迟的最大值 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_WR_LATENCY_MAX_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x230) /* AXI master的burst写延迟的最大值 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_RD_OTD_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x234) /* AXI master的读outstanding数量计数器 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_WR_OTD_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x238) /* AXI master的写outstanding数量计数器 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_RD_OTD_MAX_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x23C) /* AXI master读outstanding数量历史最大值 */ +#define CSR_RING2AXI_CSR_RING2AXI_AXI_WR_OTD_MAX_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x240) /* AXI master写outstanding数量历史最大值 */ +#define CSR_RING2AXI_CSR_RING2AXI_FSM_STAT_REG (CSR_RING2AXI_CSR_BASE + 0x244) /* 内部状态机状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_FIFO_ERR_FLAG_REG (CSR_RING2AXI_CSR_BASE + 0x248) /* 内部FIFO上溢下溢标志 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_LEGAL_EFIFO_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x24C) /* store_legal_efifo状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_LOAD_LEGAL_EFIFO_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x250) /* load_legal_efifo状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_LOAD_ADDR_FIFO_STAT_REG (CSR_RING2AXI_CSR_BASE + 0x254) /* load_addr_fifo状态寄存器 \ + */ +#define CSR_RING2AXI_CSR_RING2AXI_LOAD_CMD_FIFO_STAT_REG (CSR_RING2AXI_CSR_BASE + 0x258) /* load_cmd_fifo状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_CSR_ADDR_FIFO_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x25C) /* store_csr_addr_fifo状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_MEM_CMD_FIFO_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x260) /* store_mem_cmd_fifo状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_CSR_CMD_FIFO_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x264) /* store_csr_cmd_fifo状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_CSR_MEM_FIFO0_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x268) /* store_csr_mem_seq_fifo0状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_CSR_MEM_FIFO1_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x26C) /* store_csr_mem_seq_fifo1状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_IF_FIFO_CNT_REG (CSR_RING2AXI_CSR_BASE + 0x270) /* RING2AXI接口FIFO实时值状态寄存器 \ + */ +#define CSR_RING2AXI_CSR_RING2AXI_EJECTION_CRDT_CNT_REG (CSR_RING2AXI_CSR_BASE + 0x274) /* RING2AXI上RING的可用信用值 \ + */ +#define CSR_RING2AXI_CSR_RING2AXI_ILLEGAL_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x278) /* RING2AXI接收到的异常命令DFX状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_STORE_MEM_API_STAT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x27C) /* RING2AXI接收到的STORE_MEM_API状态寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_RX_DISC_FLIT_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x400) /* 接收方向丢弃的Flit统计寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_RX_DEALED_FLIT_CNT_REG \ + (CSR_RING2AXI_CSR_BASE + 0x404) /* 接收方向发起了AXI操作的正确API的Flit/API统计寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_UP_FILT_CNT_REG (CSR_RING2AXI_CSR_BASE + 0x410) /* linkup filt 滤波周期配置寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_DN_FILT_CNT_REG (CSR_RING2AXI_CSR_BASE + 0x414) /* linkdn filt 滤波周期配置寄存器 */ +#define CSR_RING2AXI_CSR_RING2AXI_VERSION_REG (CSR_RING2AXI_CSR_BASE + 0x500) /* RING2AXI ECO预留寄存器 */ + +/* DMAC Base address of Module's Register */ +#define CSR_DMAC_BASE (0x1809000) + +/* **************************************************************************** */ +/* DMAC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DMAC_INT_STAT_REG (CSR_DMAC_BASE + 0x0) /* 处理器X的中断状态寄存器。 */ +#define CSR_DMAC_INT_TC1_REG (CSR_DMAC_BASE + 0x4) /* 处理器X的通道传输完成中断状态寄存器。 */ +#define CSR_DMAC_INT_TC2_REG (CSR_DMAC_BASE + 0x8) /* 处理器X的链表节点传输完成中断状态寄存器。 */ +#define CSR_DMAC_INT_ERR1_REG (CSR_DMAC_BASE + 0xC) /* 处理器X的配置错误中断状态寄存器。 */ +#define CSR_DMAC_INT_ERR2_REG (CSR_DMAC_BASE + 0x10) /* 处理器X的数据传输错误中断状态寄存器。 */ +#define CSR_DMAC_INT_ERR3_REG (CSR_DMAC_BASE + 0x14) /* 处理器X的读链表错误中断状态寄存器。 */ +#define CSR_DMAC_INT_TC1_MASK_REG (CSR_DMAC_BASE + 0x18) /* 处理器X的通道传输完成中断屏蔽寄存器。 */ +#define CSR_DMAC_INT_TC2_MASK_REG (CSR_DMAC_BASE + 0x1C) /* 处理器X的链表节点传输完成中断屏蔽寄存器。 */ +#define CSR_DMAC_INT_ERR1_MASK_REG (CSR_DMAC_BASE + 0x20) /* 处理器X的配置错误中断屏蔽寄存器。 */ +#define CSR_DMAC_INT_ERR2_MASK_REG (CSR_DMAC_BASE + 0x24) /* 处理器X的数据传输错误中断屏蔽寄存器。 */ +#define CSR_DMAC_INT_ERR3_MASK_REG (CSR_DMAC_BASE + 0x28) /* 处理器X的链表读取错误中断屏蔽寄存器。 */ +#define CSR_DMAC_INT_TC1_RAW_REG (CSR_DMAC_BASE + 0x600) /* 原始通道传输完成中断状态寄存器。 */ +#define CSR_DMAC_INT_TC2_RAW_REG (CSR_DMAC_BASE + 0x608) /* 原始链表节点传输完成中断状态寄存器。 */ +#define CSR_DMAC_INT_ERR1_RAW_REG (CSR_DMAC_BASE + 0x610) /* 原始配置错误中断状态寄存器。 */ +#define CSR_DMAC_INT_ERR2_RAW_REG (CSR_DMAC_BASE + 0x618) /* 原始数据传输错误中断状态寄存器。 */ +#define CSR_DMAC_INT_ERR3_RAW_REG (CSR_DMAC_BASE + 0x620) /* 原始链表读取错误中断状态寄存器。 */ +#define CSR_DMAC_SREQ_REG (CSR_DMAC_BASE + 0x660) /* 单传输请求寄存器。 */ +#define CSR_DMAC_LSREQ_REG (CSR_DMAC_BASE + 0x664) /* 末次单传输请求寄存器。 */ +#define CSR_DMAC_BREQ_REG (CSR_DMAC_BASE + 0x668) /* 突发传输请求寄存器。 */ +#define CSR_DMAC_LBREQ_REG (CSR_DMAC_BASE + 0x66C) /* 末次突发传输请求寄存器。 */ +#define CSR_DMAC_FREQ_REG (CSR_DMAC_BASE + 0x670) /* 批量传输请求寄存器。 */ +#define CSR_DMAC_LFREQ_REG (CSR_DMAC_BASE + 0x674) /* 末次批量传输请求寄存器。 */ +#define CSR_DMAC_CH_PRI_REG (CSR_DMAC_BASE + 0x688) /* 优先级控制寄存器。 */ +#define CSR_DMAC_CH_STAT_REG (CSR_DMAC_BASE + 0x690) /* 全局DMA状态寄存器。 */ +#define CSR_DMAC_DMA_CTRL_REG (CSR_DMAC_BASE + 0x698) /* DMA全局控制寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_0_REG (CSR_DMAC_BASE + 0x700) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_1_REG (CSR_DMAC_BASE + 0x710) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_2_REG (CSR_DMAC_BASE + 0x720) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_3_REG (CSR_DMAC_BASE + 0x730) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_4_REG (CSR_DMAC_BASE + 0x740) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_5_REG (CSR_DMAC_BASE + 0x750) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_6_REG (CSR_DMAC_BASE + 0x760) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_7_REG (CSR_DMAC_BASE + 0x770) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_8_REG (CSR_DMAC_BASE + 0x780) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_9_REG (CSR_DMAC_BASE + 0x790) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_10_REG (CSR_DMAC_BASE + 0x7A0) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_11_REG (CSR_DMAC_BASE + 0x7B0) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_12_REG (CSR_DMAC_BASE + 0x7C0) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_13_REG (CSR_DMAC_BASE + 0x7D0) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_14_REG (CSR_DMAC_BASE + 0x7E0) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT1_15_REG (CSR_DMAC_BASE + 0x7F0) /* 通道X的三维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_0_REG (CSR_DMAC_BASE + 0x704) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_1_REG (CSR_DMAC_BASE + 0x714) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_2_REG (CSR_DMAC_BASE + 0x724) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_3_REG (CSR_DMAC_BASE + 0x734) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_4_REG (CSR_DMAC_BASE + 0x744) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_5_REG (CSR_DMAC_BASE + 0x754) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_6_REG (CSR_DMAC_BASE + 0x764) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_7_REG (CSR_DMAC_BASE + 0x774) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_8_REG (CSR_DMAC_BASE + 0x784) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_9_REG (CSR_DMAC_BASE + 0x794) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_10_REG (CSR_DMAC_BASE + 0x7A4) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_11_REG (CSR_DMAC_BASE + 0x7B4) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_12_REG (CSR_DMAC_BASE + 0x7C4) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_13_REG (CSR_DMAC_BASE + 0x7D4) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_14_REG (CSR_DMAC_BASE + 0x7E4) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_CNT0_15_REG (CSR_DMAC_BASE + 0x7F4) /* 通道X的一、二维传输剩余size状态寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_0_REG (CSR_DMAC_BASE + 0x708) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_1_REG (CSR_DMAC_BASE + 0x718) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_2_REG (CSR_DMAC_BASE + 0x728) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_3_REG (CSR_DMAC_BASE + 0x738) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_4_REG (CSR_DMAC_BASE + 0x748) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_5_REG (CSR_DMAC_BASE + 0x758) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_6_REG (CSR_DMAC_BASE + 0x768) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_7_REG (CSR_DMAC_BASE + 0x778) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_8_REG (CSR_DMAC_BASE + 0x788) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_9_REG (CSR_DMAC_BASE + 0x798) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_10_REG (CSR_DMAC_BASE + 0x7A8) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_11_REG (CSR_DMAC_BASE + 0x7B8) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_12_REG (CSR_DMAC_BASE + 0x7C8) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_13_REG (CSR_DMAC_BASE + 0x7D8) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_14_REG (CSR_DMAC_BASE + 0x7E8) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_SRC_ADDR_15_REG (CSR_DMAC_BASE + 0x7F8) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_0_REG (CSR_DMAC_BASE + 0x70C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_1_REG (CSR_DMAC_BASE + 0x71C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_2_REG (CSR_DMAC_BASE + 0x72C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_3_REG (CSR_DMAC_BASE + 0x73C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_4_REG (CSR_DMAC_BASE + 0x74C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_5_REG (CSR_DMAC_BASE + 0x75C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_6_REG (CSR_DMAC_BASE + 0x76C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_7_REG (CSR_DMAC_BASE + 0x77C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_8_REG (CSR_DMAC_BASE + 0x78C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_9_REG (CSR_DMAC_BASE + 0x79C) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_10_REG (CSR_DMAC_BASE + 0x7AC) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_11_REG (CSR_DMAC_BASE + 0x7BC) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_12_REG (CSR_DMAC_BASE + 0x7CC) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_13_REG (CSR_DMAC_BASE + 0x7DC) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_14_REG (CSR_DMAC_BASE + 0x7EC) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CURR_DES_ADDR_15_REG (CSR_DMAC_BASE + 0x7FC) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_LLI_0_REG (CSR_DMAC_BASE + 0x800) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_1_REG (CSR_DMAC_BASE + 0x840) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_2_REG (CSR_DMAC_BASE + 0x880) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_3_REG (CSR_DMAC_BASE + 0x8C0) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_4_REG (CSR_DMAC_BASE + 0x900) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_5_REG (CSR_DMAC_BASE + 0x940) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_6_REG (CSR_DMAC_BASE + 0x980) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_7_REG (CSR_DMAC_BASE + 0x9C0) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_8_REG (CSR_DMAC_BASE + 0xA00) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_9_REG (CSR_DMAC_BASE + 0xA40) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_10_REG (CSR_DMAC_BASE + 0xA80) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_11_REG (CSR_DMAC_BASE + 0xAC0) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_12_REG (CSR_DMAC_BASE + 0xB00) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_13_REG (CSR_DMAC_BASE + 0xB40) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_14_REG (CSR_DMAC_BASE + 0xB80) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_LLI_15_REG (CSR_DMAC_BASE + 0xBC0) /* 通道X的链表地址寄存器。 */ +#define CSR_DMAC_CX_BINDX_0_REG (CSR_DMAC_BASE + 0x804) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_1_REG (CSR_DMAC_BASE + 0x844) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_2_REG (CSR_DMAC_BASE + 0x884) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_3_REG (CSR_DMAC_BASE + 0x8C4) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_4_REG (CSR_DMAC_BASE + 0x904) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_5_REG (CSR_DMAC_BASE + 0x944) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_6_REG (CSR_DMAC_BASE + 0x984) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_7_REG (CSR_DMAC_BASE + 0x9C4) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_8_REG (CSR_DMAC_BASE + 0xA04) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_9_REG (CSR_DMAC_BASE + 0xA44) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_10_REG (CSR_DMAC_BASE + 0xA84) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_11_REG (CSR_DMAC_BASE + 0xAC4) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_12_REG (CSR_DMAC_BASE + 0xB04) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_13_REG (CSR_DMAC_BASE + 0xB44) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_14_REG (CSR_DMAC_BASE + 0xB84) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_BINDX_15_REG (CSR_DMAC_BASE + 0xBC4) /* 通道X的二维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_0_REG (CSR_DMAC_BASE + 0x808) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_1_REG (CSR_DMAC_BASE + 0x848) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_2_REG (CSR_DMAC_BASE + 0x888) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_3_REG (CSR_DMAC_BASE + 0x8C8) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_4_REG (CSR_DMAC_BASE + 0x908) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_5_REG (CSR_DMAC_BASE + 0x948) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_6_REG (CSR_DMAC_BASE + 0x988) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_7_REG (CSR_DMAC_BASE + 0x9C8) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_8_REG (CSR_DMAC_BASE + 0xA08) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_9_REG (CSR_DMAC_BASE + 0xA48) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_10_REG (CSR_DMAC_BASE + 0xA88) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_11_REG (CSR_DMAC_BASE + 0xAC8) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_12_REG (CSR_DMAC_BASE + 0xB08) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_13_REG (CSR_DMAC_BASE + 0xB48) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_14_REG (CSR_DMAC_BASE + 0xB88) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CINDX_15_REG (CSR_DMAC_BASE + 0xBC8) /* 通道X的三维地址偏移量配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_0_REG (CSR_DMAC_BASE + 0x80C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_1_REG (CSR_DMAC_BASE + 0x84C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_2_REG (CSR_DMAC_BASE + 0x88C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_3_REG (CSR_DMAC_BASE + 0x8CC) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_4_REG (CSR_DMAC_BASE + 0x90C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_5_REG (CSR_DMAC_BASE + 0x94C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_6_REG (CSR_DMAC_BASE + 0x98C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_7_REG (CSR_DMAC_BASE + 0x9CC) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_8_REG (CSR_DMAC_BASE + 0xA0C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_9_REG (CSR_DMAC_BASE + 0xA4C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_10_REG (CSR_DMAC_BASE + 0xA8C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_11_REG (CSR_DMAC_BASE + 0xACC) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_12_REG (CSR_DMAC_BASE + 0xB0C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_13_REG (CSR_DMAC_BASE + 0xB4C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_14_REG (CSR_DMAC_BASE + 0xB8C) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT1_15_REG (CSR_DMAC_BASE + 0xBCC) /* 通道X的传输长度1配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_0_REG (CSR_DMAC_BASE + 0x810) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_1_REG (CSR_DMAC_BASE + 0x850) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_2_REG (CSR_DMAC_BASE + 0x890) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_3_REG (CSR_DMAC_BASE + 0x8D0) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_4_REG (CSR_DMAC_BASE + 0x910) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_5_REG (CSR_DMAC_BASE + 0x950) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_6_REG (CSR_DMAC_BASE + 0x990) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_7_REG (CSR_DMAC_BASE + 0x9D0) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_8_REG (CSR_DMAC_BASE + 0xA10) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_9_REG (CSR_DMAC_BASE + 0xA50) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_10_REG (CSR_DMAC_BASE + 0xA90) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_11_REG (CSR_DMAC_BASE + 0xAD0) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_12_REG (CSR_DMAC_BASE + 0xB10) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_13_REG (CSR_DMAC_BASE + 0xB50) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_14_REG (CSR_DMAC_BASE + 0xB90) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_CNT0_15_REG (CSR_DMAC_BASE + 0xBD0) /* 通道X的传输长度配置寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_0_REG (CSR_DMAC_BASE + 0x814) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_1_REG (CSR_DMAC_BASE + 0x854) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_2_REG (CSR_DMAC_BASE + 0x894) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_3_REG (CSR_DMAC_BASE + 0x8D4) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_4_REG (CSR_DMAC_BASE + 0x914) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_5_REG (CSR_DMAC_BASE + 0x954) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_6_REG (CSR_DMAC_BASE + 0x994) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_7_REG (CSR_DMAC_BASE + 0x9D4) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_8_REG (CSR_DMAC_BASE + 0xA14) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_9_REG (CSR_DMAC_BASE + 0xA54) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_10_REG (CSR_DMAC_BASE + 0xA94) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_11_REG (CSR_DMAC_BASE + 0xAD4) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_12_REG (CSR_DMAC_BASE + 0xB14) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_13_REG (CSR_DMAC_BASE + 0xB54) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_14_REG (CSR_DMAC_BASE + 0xB94) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_SRC_ADDR_15_REG (CSR_DMAC_BASE + 0xBD4) /* 通道X的源地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_0_REG (CSR_DMAC_BASE + 0x818) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_1_REG (CSR_DMAC_BASE + 0x858) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_2_REG (CSR_DMAC_BASE + 0x898) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_3_REG (CSR_DMAC_BASE + 0x8D8) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_4_REG (CSR_DMAC_BASE + 0x918) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_5_REG (CSR_DMAC_BASE + 0x958) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_6_REG (CSR_DMAC_BASE + 0x998) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_7_REG (CSR_DMAC_BASE + 0x9D8) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_8_REG (CSR_DMAC_BASE + 0xA18) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_9_REG (CSR_DMAC_BASE + 0xA58) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_10_REG (CSR_DMAC_BASE + 0xA98) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_11_REG (CSR_DMAC_BASE + 0xAD8) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_12_REG (CSR_DMAC_BASE + 0xB18) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_13_REG (CSR_DMAC_BASE + 0xB58) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_14_REG (CSR_DMAC_BASE + 0xB98) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_DES_ADDR_15_REG (CSR_DMAC_BASE + 0xBD8) /* 通道X的目的地址寄存器。 */ +#define CSR_DMAC_CX_CONFIG_0_REG (CSR_DMAC_BASE + 0x81C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_1_REG (CSR_DMAC_BASE + 0x85C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_2_REG (CSR_DMAC_BASE + 0x89C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_3_REG (CSR_DMAC_BASE + 0x8DC) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_4_REG (CSR_DMAC_BASE + 0x91C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_5_REG (CSR_DMAC_BASE + 0x95C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_6_REG (CSR_DMAC_BASE + 0x99C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_7_REG (CSR_DMAC_BASE + 0x9DC) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_8_REG (CSR_DMAC_BASE + 0xA1C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_9_REG (CSR_DMAC_BASE + 0xA5C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_10_REG (CSR_DMAC_BASE + 0xA9C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_11_REG (CSR_DMAC_BASE + 0xADC) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_12_REG (CSR_DMAC_BASE + 0xB1C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_13_REG (CSR_DMAC_BASE + 0xB5C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_14_REG (CSR_DMAC_BASE + 0xB9C) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_CONFIG_15_REG (CSR_DMAC_BASE + 0xBDC) /* 通道X的配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_0_REG (CSR_DMAC_BASE + 0x820) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_1_REG (CSR_DMAC_BASE + 0x860) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_2_REG (CSR_DMAC_BASE + 0x8A0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_3_REG (CSR_DMAC_BASE + 0x8E0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_4_REG (CSR_DMAC_BASE + 0x920) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_5_REG (CSR_DMAC_BASE + 0x960) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_6_REG (CSR_DMAC_BASE + 0x9A0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_7_REG (CSR_DMAC_BASE + 0x9E0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_8_REG (CSR_DMAC_BASE + 0xA20) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_9_REG (CSR_DMAC_BASE + 0xA60) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_10_REG (CSR_DMAC_BASE + 0xAA0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_11_REG (CSR_DMAC_BASE + 0xAE0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_12_REG (CSR_DMAC_BASE + 0xB20) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_13_REG (CSR_DMAC_BASE + 0xB60) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_14_REG (CSR_DMAC_BASE + 0xBA0) /* 通道X的AXI特殊操作配置寄存器。 */ +#define CSR_DMAC_CX_AXI_CONF_15_REG (CSR_DMAC_BASE + 0xBE0) /* 通道X的AXI特殊操作配置寄存器。 */ + +/* SYSCTRL_CSR0 Base address of Module's Register */ +#define CSR_SYSCTRL_CSR0_BASE (0x1804000) + +/* **************************************************************************** */ +/* SYSCTRL_CSR0 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SYSCTRL_CSR0_RSV_REG (CSR_SYSCTRL_CSR0_BASE + 0x24) /* 保留 */ +#define CSR_SYSCTRL_CSR0_SC_TEST0_REG (CSR_SYSCTRL_CSR0_BASE + 0x100) /* 芯片本次前的复位原因 */ +#define CSR_SYSCTRL_CSR0_SC_TEST1_REG (CSR_SYSCTRL_CSR0_BASE + 0x104) /* mpu init调试使能寄存器 */ +#define CSR_SYSCTRL_CSR0_SC_TEST2_REG (CSR_SYSCTRL_CSR0_BASE + 0x108) /* MPU&SMU写log互斥寄存器 */ +#define CSR_SYSCTRL_CSR0_SC_TEST3_REG (CSR_SYSCTRL_CSR0_BASE + 0x10C) /* 软件测试寄存器3。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST4_REG (CSR_SYSCTRL_CSR0_BASE + 0x110) /* 芯片软复位时间低位 */ +#define CSR_SYSCTRL_CSR0_SC_TEST5_REG (CSR_SYSCTRL_CSR0_BASE + 0x114) /* 芯片软复位时间高位 */ +#define CSR_SYSCTRL_CSR0_SC_TEST6_REG (CSR_SYSCTRL_CSR0_BASE + 0x118) /* 软件测试寄存器6。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST7_REG (CSR_SYSCTRL_CSR0_BASE + 0x11C) /* 软件测试寄存器7。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST8_REG (CSR_SYSCTRL_CSR0_BASE + 0x120) /* 软件测试寄存器8。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST9_REG (CSR_SYSCTRL_CSR0_BASE + 0x124) /* 软件测试寄存器9。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST10_REG (CSR_SYSCTRL_CSR0_BASE + 0x128) /* 软件测试寄存器10。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST11_REG (CSR_SYSCTRL_CSR0_BASE + 0x12C) /* mpu镜像修复标识 */ +#define CSR_SYSCTRL_CSR0_SC_TEST12_REG (CSR_SYSCTRL_CSR0_BASE + 0x130) /* hi32镜像修复标识 */ +#define CSR_SYSCTRL_CSR0_SC_TEST13_REG (CSR_SYSCTRL_CSR0_BASE + 0x134) /* mpu镜像启动主备区标识 */ +#define CSR_SYSCTRL_CSR0_SC_TEST14_REG (CSR_SYSCTRL_CSR0_BASE + 0x138) /* hi32镜像启动主备标识 */ +#define CSR_SYSCTRL_CSR0_SC_TEST15_REG (CSR_SYSCTRL_CSR0_BASE + 0x13C) /* 软件测试寄存器15。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST16_REG (CSR_SYSCTRL_CSR0_BASE + 0x140) /* 软件测试寄存器16。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST17_REG (CSR_SYSCTRL_CSR0_BASE + 0x144) /* 软件测试寄存器17。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST18_REG (CSR_SYSCTRL_CSR0_BASE + 0x148) /* 软件测试寄存器18。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST19_REG (CSR_SYSCTRL_CSR0_BASE + 0x14C) /* 软件测试寄存器19。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST20_REG (CSR_SYSCTRL_CSR0_BASE + 0x150) /* MPU&SMU UART互斥寄存器 */ +#define CSR_SYSCTRL_CSR0_SC_TEST21_REG (CSR_SYSCTRL_CSR0_BASE + 0x154) /* 软件测试寄存器21。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST22_REG (CSR_SYSCTRL_CSR0_BASE + 0x158) /* 安全启动调测使能寄存器 */ +#define CSR_SYSCTRL_CSR0_SC_TEST23_REG (CSR_SYSCTRL_CSR0_BASE + 0x15C) /* 软件测试寄存器23。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST24_REG (CSR_SYSCTRL_CSR0_BASE + 0x160) /* 软件测试寄存器24。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST25_REG (CSR_SYSCTRL_CSR0_BASE + 0x164) /* 软件测试寄存器25。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST26_REG (CSR_SYSCTRL_CSR0_BASE + 0x168) /* 软件测试寄存器26。 */ +#define CSR_SYSCTRL_CSR0_SC_TEST27_REG (CSR_SYSCTRL_CSR0_BASE + 0x16C) /* mpu&spu调试寄存器 */ +#define CSR_SYSCTRL_CSR0_SC_TEST28_REG (CSR_SYSCTRL_CSR0_BASE + 0x170) /* spu调试寄存器0(可做它用) */ +#define CSR_SYSCTRL_CSR0_SC_TEST29_REG (CSR_SYSCTRL_CSR0_BASE + 0x174) /* spu调试寄存器1(可做它用) */ +#define CSR_SYSCTRL_CSR0_SC_TEST30_REG (CSR_SYSCTRL_CSR0_BASE + 0x178) /* mmu使能寄存器 */ +#define CSR_SYSCTRL_CSR0_SC_TEST31_REG (CSR_SYSCTRL_CSR0_BASE + 0x17C) /* spu调试寄存器1(可做它用) */ + +/* SYSCTRL_CSR1 Base address of Module's Register */ +#define CSR_SYSCTRL_CSR1_BASE (0x1804000) + +/* **************************************************************************** */ +/* SYSCTRL_CSR1 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_0_REG (CSR_SYSCTRL_CSR1_BASE + 0x800) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_1_REG (CSR_SYSCTRL_CSR1_BASE + 0x804) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_2_REG (CSR_SYSCTRL_CSR1_BASE + 0x808) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_3_REG (CSR_SYSCTRL_CSR1_BASE + 0x80C) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_4_REG (CSR_SYSCTRL_CSR1_BASE + 0x810) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_5_REG (CSR_SYSCTRL_CSR1_BASE + 0x814) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_6_REG (CSR_SYSCTRL_CSR1_BASE + 0x818) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_7_REG (CSR_SYSCTRL_CSR1_BASE + 0x81C) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_8_REG (CSR_SYSCTRL_CSR1_BASE + 0x820) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_9_REG (CSR_SYSCTRL_CSR1_BASE + 0x824) /* MPU 使能 Tile bitmap寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_10_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x828) /* MPU 使能 Tile bitmap寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_11_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x82C) /* MPU 使能 Tile bitmap寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_12_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x830) /* MPU 使能 Tile bitmap寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_UP_TILE_BITMAP_EN_13_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x834) /* MPU 使能 Tile bitmap寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_0_REG (CSR_SYSCTRL_CSR1_BASE + 0x838) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_1_REG (CSR_SYSCTRL_CSR1_BASE + 0x83C) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_2_REG (CSR_SYSCTRL_CSR1_BASE + 0x840) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_3_REG (CSR_SYSCTRL_CSR1_BASE + 0x844) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_4_REG (CSR_SYSCTRL_CSR1_BASE + 0x848) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_5_REG (CSR_SYSCTRL_CSR1_BASE + 0x84C) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_6_REG (CSR_SYSCTRL_CSR1_BASE + 0x850) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_7_REG (CSR_SYSCTRL_CSR1_BASE + 0x854) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_8_REG (CSR_SYSCTRL_CSR1_BASE + 0x858) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_9_REG (CSR_SYSCTRL_CSR1_BASE + 0x85C) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_10_REG (CSR_SYSCTRL_CSR1_BASE + 0x860) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_11_REG (CSR_SYSCTRL_CSR1_BASE + 0x864) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_12_REG (CSR_SYSCTRL_CSR1_BASE + 0x868) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_STAT_13_REG (CSR_SYSCTRL_CSR1_BASE + 0x86C) /* Tile bitmap 寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_0_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x870) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_1_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x874) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_2_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x878) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_3_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x87C) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_4_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x880) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_5_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x884) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_6_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x888) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_7_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x88C) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_8_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x890) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_9_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x894) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_10_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x898) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_11_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x89C) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_12_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x8A0) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_SC_TILE_BITMAP_SET_13_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0x8A4) /* 线程置位SC_TILE_BITMAP_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_0_REG (CSR_SYSCTRL_CSR1_BASE + 0x8B8) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_1_REG (CSR_SYSCTRL_CSR1_BASE + 0x8BC) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_2_REG (CSR_SYSCTRL_CSR1_BASE + 0x8C0) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_3_REG (CSR_SYSCTRL_CSR1_BASE + 0x8C4) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_4_REG (CSR_SYSCTRL_CSR1_BASE + 0x8C8) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_5_REG (CSR_SYSCTRL_CSR1_BASE + 0x8CC) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_6_REG (CSR_SYSCTRL_CSR1_BASE + 0x8D0) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_7_REG (CSR_SYSCTRL_CSR1_BASE + 0x8D4) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_8_REG (CSR_SYSCTRL_CSR1_BASE + 0x8D8) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_9_REG (CSR_SYSCTRL_CSR1_BASE + 0x8DC) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_10_REG (CSR_SYSCTRL_CSR1_BASE + 0x8E0) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_11_REG (CSR_SYSCTRL_CSR1_BASE + 0x8E4) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_12_REG (CSR_SYSCTRL_CSR1_BASE + 0x8E8) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_13_REG (CSR_SYSCTRL_CSR1_BASE + 0x8EC) /* 核间状态寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_0_REG (CSR_SYSCTRL_CSR1_BASE + 0x8F0) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_1_REG (CSR_SYSCTRL_CSR1_BASE + 0x8F4) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_2_REG (CSR_SYSCTRL_CSR1_BASE + 0x8F8) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_3_REG (CSR_SYSCTRL_CSR1_BASE + 0x8FC) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_4_REG (CSR_SYSCTRL_CSR1_BASE + 0x900) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_5_REG (CSR_SYSCTRL_CSR1_BASE + 0x904) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_6_REG (CSR_SYSCTRL_CSR1_BASE + 0x908) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_7_REG (CSR_SYSCTRL_CSR1_BASE + 0x90C) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_8_REG (CSR_SYSCTRL_CSR1_BASE + 0x910) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_9_REG (CSR_SYSCTRL_CSR1_BASE + 0x914) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_10_REG (CSR_SYSCTRL_CSR1_BASE + 0x918) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_11_REG (CSR_SYSCTRL_CSR1_BASE + 0x91C) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_12_REG (CSR_SYSCTRL_CSR1_BASE + 0x920) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MCORE_STAT_SET_13_REG (CSR_SYSCTRL_CSR1_BASE + 0x924) /* 线程置位MOCRE_STAT控制寄存器0~13 */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_0_REG (CSR_SYSCTRL_CSR1_BASE + 0x928) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_1_REG (CSR_SYSCTRL_CSR1_BASE + 0x92C) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_2_REG (CSR_SYSCTRL_CSR1_BASE + 0x930) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_3_REG (CSR_SYSCTRL_CSR1_BASE + 0x934) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_4_REG (CSR_SYSCTRL_CSR1_BASE + 0x938) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_5_REG (CSR_SYSCTRL_CSR1_BASE + 0x93C) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_6_REG (CSR_SYSCTRL_CSR1_BASE + 0x940) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_7_REG (CSR_SYSCTRL_CSR1_BASE + 0x944) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_8_REG (CSR_SYSCTRL_CSR1_BASE + 0x948) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_9_REG (CSR_SYSCTRL_CSR1_BASE + 0x94C) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_10_REG (CSR_SYSCTRL_CSR1_BASE + 0x950) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_11_REG (CSR_SYSCTRL_CSR1_BASE + 0x954) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_12_REG (CSR_SYSCTRL_CSR1_BASE + 0x958) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_MPU_MCORE_STAT_SET_13_REG (CSR_SYSCTRL_CSR1_BASE + 0x95C) /* MPU清零MOCRE_STAT控制寄存器0~13 \ + */ +#define CSR_SYSCTRL_CSR1_C2J_MBIST_CTRL_REG (CSR_SYSCTRL_CSR1_BASE + 0x974) /* 保留寄存器 */ +#define CSR_SYSCTRL_CSR1_C2J_MBIST_DATAIN_REG (CSR_SYSCTRL_CSR1_BASE + 0x978) /* 保留寄存器 */ +#define CSR_SYSCTRL_CSR1_C2J_MBIST_DATAOUT_REG (CSR_SYSCTRL_CSR1_BASE + 0x97C) /* 保留寄存器 */ +#define CSR_SYSCTRL_CSR1_A55_SUB_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x980) /* A55_SUB中断状态寄存器 */ +#define CSR_SYSCTRL_CSR1_A55_SUB_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0x984) /* A55_SUB中断使能寄存器 */ +#define CSR_SYSCTRL_CSR1_A55_SUB_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0x988) /* A55_SUB软件模拟中断寄存器 */ +#define CSR_SYSCTRL_CSR1_A55_SUB_INT_RAW_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x98C) /* A55_SUB中断写清寄存器 */ +#define CSR_SYSCTRL_CSR1_R52_WFI_WFE_STAT_REG (CSR_SYSCTRL_CSR1_BASE + 0x990) /* 保留寄存器 */ +#define CSR_SYSCTRL_CSR1_NCSI_FUNC_MBIST_CLK_SEL_REG (CSR_SYSCTRL_CSR1_BASE + 0x994) /* 保留寄存器 */ +#define CSR_SYSCTRL_CSR1_WOL_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9A0) /* WOL LP_ENTRY中断状态寄存器 */ +#define CSR_SYSCTRL_CSR1_WOL_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0x9A4) /* WOL中断使能寄存器 */ +#define CSR_SYSCTRL_CSR1_WOL_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0x9A8) /* WOL软件模拟中断寄存器 */ +#define CSR_SYSCTRL_CSR1_WOL_INT_RAW_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9AC) /* WOL中断写清寄存器 */ +#define CSR_SYSCTRL_CSR1_WOL_CTL_REG (CSR_SYSCTRL_CSR1_BASE + 0x9B0) /* WOL控制断寄存器 */ +#define CSR_SYSCTRL_CSR1_LP_INTSET0_REG (CSR_SYSCTRL_CSR1_BASE + 0x9B4) /* 低功耗请求置位寄存器 */ +#define CSR_SYSCTRL_CSR1_LP_INTSET1_REG (CSR_SYSCTRL_CSR1_BASE + 0x9B8) /* 低功耗请求置位寄存器 */ +#define CSR_SYSCTRL_CSR1_LP_INTSET2_REG (CSR_SYSCTRL_CSR1_BASE + 0x9BC) /* 低功耗请求置位寄存器 */ +#define CSR_SYSCTRL_CSR1_LP_INTSET3_REG (CSR_SYSCTRL_CSR1_BASE + 0x9C0) /* 低功耗请求置位寄存器 */ +#define CSR_SYSCTRL_CSR1_LP_READY_REG (CSR_SYSCTRL_CSR1_BASE + 0x9C4) /* LP READY寄存器 */ +#define CSR_SYSCTRL_CSR1_PERSTN_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9C8) /* PERSTN中断状态寄存器 */ +#define CSR_SYSCTRL_CSR1_PERSTN_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0x9CC) /* PERSTN中断使能寄存器 */ +#define CSR_SYSCTRL_CSR1_PERSTN_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0x9D0) /* PERSTN软件模拟中断寄存器 */ +#define CSR_SYSCTRL_CSR1_PERSTN_INT_RAW_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9D4) /* PERSTNL中断写清寄存器 */ +#define CSR_SYSCTRL_CSR1_UP_UNCRT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0x9D8) /* UP_UNCRT_EN寄存器 */ +#define CSR_SYSCTRL_CSR1_AXI_BRESP_MON_REG (CSR_SYSCTRL_CSR1_BASE + 0x9DC) /* AXI BRSP历史状态寄存器 */ +#define CSR_SYSCTRL_CSR1_AXI_RRESP_MON_REG (CSR_SYSCTRL_CSR1_BASE + 0x9E0) /* AXI RRSP历史状态寄存器 */ +#define CSR_SYSCTRL_CSR1_AXI_RESP_MASK_REG (CSR_SYSCTRL_CSR1_BASE + 0x9E4) /* AXI RESP MASK寄存器 */ +#define CSR_SYSCTRL_CSR1_PERSTN_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9E8) /* PERSTN管脚状态寄存器 */ +#define CSR_SYSCTRL_CSR1_PERSTN_HISS_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9EC) /* PERSTN 送给HISS中断状态寄存器 \ + */ +#define CSR_SYSCTRL_CSR1_PERSTN_HISS_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0x9F0) /* PERSTN 送给HISS中断使能寄存器 */ +#define CSR_SYSCTRL_CSR1_AXI4TOAXI3_BYPASS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9F4) /* AXI4TOAXI3 BYPASS控制寄存器 */ +#define CSR_SYSCTRL_CSR1_AXI4TOAXI3_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0x9F8) /* AXI4TOAXI3 BYPASS状态寄存器 */ +#define CSR_SYSCTRL_CSR1_SMB_DW_APB_I2C_DEBUG_REG (CSR_SYSCTRL_CSR1_BASE + 0x9FC) /* SMB_DW DEBUG寄存器 */ +#define CSR_SYSCTRL_CSR1_A55_FCM_CLUSTER_CONFIG0_REG (CSR_SYSCTRL_CSR1_BASE + 0xA04) +#define CSR_SYSCTRL_CSR1_A55_FCM_CLUSTER_CONFIG1_REG (CSR_SYSCTRL_CSR1_BASE + 0xA08) +#define CSR_SYSCTRL_CSR1_A55_RVBARADDRY_CFG_L_REG (CSR_SYSCTRL_CSR1_BASE + 0xA0C) +#define CSR_SYSCTRL_CSR1_A55_RVBARADDRY_CFG_H_REG (CSR_SYSCTRL_CSR1_BASE + 0xA10) +#define CSR_SYSCTRL_CSR1_A55_BROADCAST_CFG_REG (CSR_SYSCTRL_CSR1_BASE + 0xA14) +#define CSR_SYSCTRL_CSR1_A55_DEBUG_CFG_REG (CSR_SYSCTRL_CSR1_BASE + 0xA18) +#define CSR_SYSCTRL_CSR1_A55_FCM_CLUSTER_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xA1C) +#define CSR_SYSCTRL_CSR1_A55_PMU_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xA20) +#define CSR_SYSCTRL_CSR1_DBG_BLOCK_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xA24) +#define CSR_SYSCTRL_CSR1_GIC600_CFG_REG (CSR_SYSCTRL_CSR1_BASE + 0xA28) +#define CSR_SYSCTRL_CSR1_GIC600_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xA2C) +#define CSR_SYSCTRL_CSR1_CRG_CLK_DIV_SEL_REG (CSR_SYSCTRL_CSR1_BASE + 0xA30) +#define CSR_SYSCTRL_CSR1_CRG_CLKOFF_REG (CSR_SYSCTRL_CSR1_BASE + 0xA34) +#define CSR_SYSCTRL_CSR1_CRG_SRST_REG (CSR_SYSCTRL_CSR1_BASE + 0xA38) +#define CSR_SYSCTRL_CSR1_SPI_SSP_SEL_REG (CSR_SYSCTRL_CSR1_BASE + 0xA3C) +#define CSR_SYSCTRL_CSR1_A55_CORE_PCHL_STAT_REG (CSR_SYSCTRL_CSR1_BASE + 0xA40) +#define CSR_SYSCTRL_CSR1_A55_CORE_PCHL_REQ_REG (CSR_SYSCTRL_CSR1_BASE + 0xA44) +#define CSR_SYSCTRL_CSR1_A55_CLUSTER_PCHL_STAT_REG (CSR_SYSCTRL_CSR1_BASE + 0xA48) +#define CSR_SYSCTRL_CSR1_A55_CLUSTER_PCHL_REQ_REG (CSR_SYSCTRL_CSR1_BASE + 0xA4C) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR0_REG (CSR_SYSCTRL_CSR1_BASE + 0xB00) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR1_REG (CSR_SYSCTRL_CSR1_BASE + 0xB04) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR2_REG (CSR_SYSCTRL_CSR1_BASE + 0xB08) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR3_REG (CSR_SYSCTRL_CSR1_BASE + 0xB0C) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR4_REG (CSR_SYSCTRL_CSR1_BASE + 0xB10) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR5_REG (CSR_SYSCTRL_CSR1_BASE + 0xB14) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR6_REG (CSR_SYSCTRL_CSR1_BASE + 0xB18) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR7_REG (CSR_SYSCTRL_CSR1_BASE + 0xB1C) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR8_REG (CSR_SYSCTRL_CSR1_BASE + 0xB20) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR9_REG (CSR_SYSCTRL_CSR1_BASE + 0xB24) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR10_REG (CSR_SYSCTRL_CSR1_BASE + 0xB28) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR11_REG (CSR_SYSCTRL_CSR1_BASE + 0xB2C) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR12_REG (CSR_SYSCTRL_CSR1_BASE + 0xB30) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR13_REG (CSR_SYSCTRL_CSR1_BASE + 0xB34) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR14_REG (CSR_SYSCTRL_CSR1_BASE + 0xB38) +#define CSR_SYSCTRL_CSR1_SC_MPU_MAP_ADDR15_REG (CSR_SYSCTRL_CSR1_BASE + 0xB3C) +#define CSR_SYSCTRL_CSR1_SC_SPU_AXUSER_NO_CTRL_REG (CSR_SYSCTRL_CSR1_BASE + 0xB40) /* SPU AXUSER NO域控制其寄存器 */ +#define CSR_SYSCTRL_CSR1_SC_MPU_AXUSER_31_0_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0xB44) /* SC_MPU_AXUSER_31_0为IMPU AXI对外总线的USER控制信号的31:0寄存器。 */ +#define CSR_SYSCTRL_CSR1_SC_MPU_AXUSER_63_32_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0xB48) /* SC_MPU_AXUSER_63_32为MPU AXI对外总线的USER控制信号的63:32寄存器。 */ +#define CSR_SYSCTRL_CSR1_SC_MPU_AXUSER_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0xB4C) /* SC_MPU_AXUSER_63_32为MPU AXI对外总线的USER控制信号的67:64寄存器。 */ +#define CSR_SYSCTRL_CSR1_SC_MPU_AXUSER_NS_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0xB50) /* SC_MPU_AXUSER_NS为IMU mpu AXI对外总线的USER控制信号的安全要求寄存器。 */ +#define CSR_SYSCTRL_CSR1_SC_MPU_AXUSER_NS_CTRL_REG \ + (CSR_SYSCTRL_CSR1_BASE + 0xB54) /* SC_MPU_AXUSER_NS_CTRL为MPU AXUSER_NS控制寄存器。 */ +#define CSR_SYSCTRL_CSR1_SC_MPU_LPBX_CTRL_REG (CSR_SYSCTRL_CSR1_BASE + 0xB58) /* MPU到SPU的LPBX桥控制 */ +#define CSR_SYSCTRL_CSR1_A55_TO_R52_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xC00) /* A55 给R52 的软件中断状态。 */ +#define CSR_SYSCTRL_CSR1_A55_TO_R52_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0xC04) /* A55 给R52 的软件中断状态使能。 */ +#define CSR_SYSCTRL_CSR1_A55_TO_R52_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0xC08) /* A55 给R52 的软件中断状态置位。 */ +#define CSR_SYSCTRL_CSR1_R52_TO_A55_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xC0C) /* R52 给A55 的软件中断状态。 */ +#define CSR_SYSCTRL_CSR1_R52_TO_A55_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0xC10) /* R52 给A55 的软件中断状态使能。 */ +#define CSR_SYSCTRL_CSR1_R52_TO_A55_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0xC14) /* R52 给A55 的软件中断状态置位。 */ +#define CSR_SYSCTRL_CSR1_A55_R52_INT_SEL_REG (CSR_SYSCTRL_CSR1_BASE + 0xC18) +#define CSR_SYSCTRL_CSR1_CPI_MPU_LPBX_CTRL_REG (CSR_SYSCTRL_CSR1_BASE + 0xC1C) /* CPI LPBX控制信号 */ +#define CSR_SYSCTRL_CSR1_RING2AXI_MPU_LPBX_CTRL_REG (CSR_SYSCTRL_CSR1_BASE + 0xC20) /* RING2AXI LPBX控制信号 */ +#define CSR_SYSCTRL_CSR1_CRG_WDG_CTRL_REG (CSR_SYSCTRL_CSR1_BASE + 0xC24) /* A55看门狗控制使能信号 */ +#define CSR_SYSCTRL_CSR1_CRG_WDG_CNT_CONFIG_REG (CSR_SYSCTRL_CSR1_BASE + 0xC28) /* A55看门狗配置计数器 */ +#define CSR_SYSCTRL_CSR1_CRG_WDG_FEED_REG (CSR_SYSCTRL_CSR1_BASE + 0xC2C) /* A55看门狗喂狗寄存器 */ +#define CSR_SYSCTRL_CSR1_WDG_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xC30) /* A55看门狗中断状态寄存器 */ +#define CSR_SYSCTRL_CSR1_WDG_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0xC34) /* A55看门狗中断使能寄存器 */ +#define CSR_SYSCTRL_CSR1_WDG_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0xC38) /* A55看门狗软件模拟中断寄存器 */ +#define CSR_SYSCTRL_CSR1_WDG_INT_RAW_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xC3C) /* A55看门狗中断写清寄存器 */ +#define CSR_SYSCTRL_CSR1_HISS_UNC_INT_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xC40) /* HISS UNC 中断状态寄存器 */ +#define CSR_SYSCTRL_CSR1_HISS_UNC_INT_EN_REG (CSR_SYSCTRL_CSR1_BASE + 0xC44) /* HISS UNC 中断使能寄存器 */ +#define CSR_SYSCTRL_CSR1_HISS_UNC_INT_SET_REG (CSR_SYSCTRL_CSR1_BASE + 0xC48) /* HISS UNC 软件模拟中断寄存器 */ +#define CSR_SYSCTRL_CSR1_HISS_UNC_INT_RAW_STATUS_REG (CSR_SYSCTRL_CSR1_BASE + 0xC4C) /* HISS UNC 原始中断状态寄存器 */ + +/* c2j Base address of Module's Register */ +#define CSR_C2J_BASE (0x1F02000) + +/* **************************************************************************** */ +/* c2j Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_C2J_C2J_CTRL_REG (CSR_C2J_BASE + 0x0) /* C2J 控制寄存器。 */ +#define CSR_C2J_C2J_STATUS_REG (CSR_C2J_BASE + 0x4) /* C2J 状态寄存器。 */ +#define CSR_C2J_C2J_DATAIN_REG (CSR_C2J_BASE + 0x8) /* C2J 输入数据寄存器。 */ +#define CSR_C2J_C2J_DATAOUT_REG (CSR_C2J_BASE + 0xC) /* C2J 数据输出寄存器。 */ +#define CSR_C2J_C2J_DR_START_REG (CSR_C2J_BASE + 0x10) /* C2J 数据移位起始寄存器。 */ +#define CSR_C2J_C2J_IR_START_REG (CSR_C2J_BASE + 0x14) /* C2J 指令移位起始寄存器。 */ + +/* MDIO Base address of Module's Register */ +#define CSR_MDIO_BASE (0x1900000) + +/* **************************************************************************** */ +/* MDIO Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MDIO_MDIO_COMMAND_REG_REG (CSR_MDIO_BASE + 0x0) /* MDIO控制寄存器 */ +#define CSR_MDIO_MDIO_ADDR_REG_REG (CSR_MDIO_BASE + 0x4) /* MDIO间接地址寄存器 */ +#define CSR_MDIO_MDIO_WDATA_REG_REG (CSR_MDIO_BASE + 0x8) /* MDIO写数据寄存器 */ +#define CSR_MDIO_MDIO_RDATA_REG_REG (CSR_MDIO_BASE + 0xC) /* MDIO读数据寄存器 */ +#define CSR_MDIO_MDIO_STA_REG_REG (CSR_MDIO_BASE + 0x10) /* MDIO访问状态寄存器 */ + +/* I2C Base address of Module's Register */ +#define CSR_I2C_BASE (0x1824000) + +/* **************************************************************************** */ +/* I2C Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_I2C_I2C_CON_REG \ + (CSR_I2C_BASE + 0x0) /* I2C控制寄存器。I2C_CON寄存器只允许在I2C配置为关闭（I2C_ENABLE [0]配置为0）时配置。 */ +#define CSR_I2C_I2C_TAR_REG (CSR_I2C_BASE + 0x4) /* I2C访问从设备地址寄存器。 */ +#define CSR_I2C_I2C_SAR_REG (CSR_I2C_BASE + 0x8) /* I2C作为从设备地址寄存器。 */ +#define CSR_I2C_I2C_HS_MADDR_REG (CSR_I2C_BASE + 0xC) /* I2C高速MASTER模式编码地址寄存器。 */ +#define CSR_I2C_I2C_DATA_CMD_REG (CSR_I2C_BASE + 0x10) /* I2C数据通道寄存器。 */ +#define CSR_I2C_I2C_SS_SCL_HCNT_REG (CSR_I2C_BASE + 0x14) /* 标准模式SCL高电平时间配置寄存器。 */ +#define CSR_I2C_I2C_SS_SCL_LCNT_REG (CSR_I2C_BASE + 0x18) /* 标准模式SCL低电平时间配置寄存器。 */ +#define CSR_I2C_I2C_FS_SCL_HCNT_REG (CSR_I2C_BASE + 0x1C) /* 快速模式SCL高电平时间配置寄存器。 */ +#define CSR_I2C_I2C_FS_SCL_LCNT_REG (CSR_I2C_BASE + 0x20) /* 快速模式SCL低电平时间配置寄存器。 */ +#define CSR_I2C_I2C_HS_SCL_HCNT_REG (CSR_I2C_BASE + 0x24) /* 高速模式SCL高电平时间配置寄存器。 */ +#define CSR_I2C_I2C_HS_SCL_LCNT_REG (CSR_I2C_BASE + 0x28) /* 高速模式SCL低电平时间配置寄存器。 */ +#define CSR_I2C_I2C_INTR_STAT_REG (CSR_I2C_BASE + 0x2C) /* 中断状态寄存器。 */ +#define CSR_I2C_I2C_INTR_MASK_REG (CSR_I2C_BASE + 0x30) /* 中断屏蔽寄存器。 */ +#define CSR_I2C_I2C_RAW_INTR_STAT_REG (CSR_I2C_BASE + 0x34) /* 原始中断状态寄存器。 */ +#define CSR_I2C_I2C_RX_TL_REG (CSR_I2C_BASE + 0x38) /* 接收FIFO的水线配置寄存器。 */ +#define CSR_I2C_I2C_TX_TL_REG (CSR_I2C_BASE + 0x3C) /* 发送FIFO的水线配置寄存器。 */ +#define CSR_I2C_I2C_CLR_INTR_REG (CSR_I2C_BASE + 0x40) /* 所有中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_RX_UNDER_REG (CSR_I2C_BASE + 0x44) /* RX_UNDER中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_RX_OVER_REG (CSR_I2C_BASE + 0x48) /* RX_OVER中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_TX_OVER_REG (CSR_I2C_BASE + 0x4C) /* TX_OVER中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_RD_REQ_REG (CSR_I2C_BASE + 0x50) /* RD_REQ中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_TX_ABRT_REG (CSR_I2C_BASE + 0x54) /* ABRT中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_RX_DONE_REG (CSR_I2C_BASE + 0x58) /* RX_DONE中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_ACTIVITY_REG (CSR_I2C_BASE + 0x5C) /* ACTIVITY状态寄存器。 */ +#define CSR_I2C_I2C_CLR_STOP_DET_REG (CSR_I2C_BASE + 0x60) /* STOP_DET中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_START_DET_REG (CSR_I2C_BASE + 0x64) /* START_DET中断清除寄存器。 */ +#define CSR_I2C_I2C_CLR_GEN_CALL_REG (CSR_I2C_BASE + 0x68) /* GEN_CALL中断清除寄存器。 */ +#define CSR_I2C_I2C_ENABLE_REG (CSR_I2C_BASE + 0x6C) /* I2C工作模式使能寄存器。 */ +#define CSR_I2C_I2C_STATUS_REG (CSR_I2C_BASE + 0x70) /* I2C状态寄存器。 */ +#define CSR_I2C_I2C_TXFLR_REG (CSR_I2C_BASE + 0x74) /* TX_FIFO中数据个数指示寄存器。 */ +#define CSR_I2C_I2C_RXFLR_REG (CSR_I2C_BASE + 0x78) /* RX_FIFO中数据个数指示寄存器。 */ +#define CSR_I2C_I2C_SDA_HOLD_REG (CSR_I2C_BASE + 0x7C) /* I2C SDA Hold Time Length寄存器。 */ +#define CSR_I2C_I2C_TX_ABRT_SOURCE_REG (CSR_I2C_BASE + 0x80) /* TX_ABRT的源头中断寄存器。 */ +#define CSR_I2C_I2C_SLV_DATA_NACK_ONLY_REG (CSR_I2C_BASE + 0x84) /* I2C SLAVE响应控制寄存器。 */ +#define CSR_I2C_I2C_DMA_CR_REG (CSR_I2C_BASE + 0x88) /* I2C DMA通道开启控制寄存器。 */ +#define CSR_I2C_I2C_DMA_TDLR_REG (CSR_I2C_BASE + 0x8C) /* 发送FIFO DMA操作水线配置寄存器。 */ +#define CSR_I2C_I2C_DMA_RDLR_REG (CSR_I2C_BASE + 0x90) /* RX_FIFO DMA操作水线配置寄存器。 */ +#define CSR_I2C_I2C_SDA_SETUP_REG (CSR_I2C_BASE + 0x94) /* SDA setup参数寄存器。 */ +#define CSR_I2C_I2C_ACK_GENERAL_CALL_REG (CSR_I2C_BASE + 0x98) /* ACK General CALL寄存器。 */ +#define CSR_I2C_I2C_ENABLE_STATUS_REG (CSR_I2C_BASE + 0x9C) /* 使能状态寄存器。 */ +#define CSR_I2C_I2C_COMP_PARAM_1_REG (CSR_I2C_BASE + 0xF4) /* I2C配置参数寄存器。 */ +#define CSR_I2C_I2C_COMP_VERSION_REG (CSR_I2C_BASE + 0xF8) /* I2C版本ID寄存器。 */ +#define CSR_I2C_I2C_COMP_TYPE_REG (CSR_I2C_BASE + 0xFC) /* I2C类型寄存器。 */ + +/* COUNTER Base address of Module's Register */ +#define CSR_COUNTER_BASE (0x182C000) + +/* **************************************************************************** */ +/* COUNTER Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_COUNTER_CNTCR_REG (CSR_COUNTER_BASE + 0x0) /* COUNTER控制寄存器。 */ +#define CSR_COUNTER_CNTSR_REG (CSR_COUNTER_BASE + 0x4) /* COUNTER状态寄存器。 */ +#define CSR_COUNTER_CNTCVL_REG (CSR_COUNTER_BASE + 0x8) /* COUNTER低位计数值寄存器。 */ +#define CSR_COUNTER_CNTCVH_REG (CSR_COUNTER_BASE + 0xC) /* COUNTER高位计数值寄存器。 */ +#define CSR_COUNTER_CNTFID0_REG (CSR_COUNTER_BASE + 0x20) /* COUNTER基准频率ID0寄存器。 */ +#define CSR_COUNTER_CNTFID1_REG (CSR_COUNTER_BASE + 0x24) /* COUNTER频率升级ID1寄存器。 */ +#define CSR_COUNTER_CNTFID2_REG (CSR_COUNTER_BASE + 0x28) /* COUNTER频率升级ID2寄存器。 */ +#define CSR_COUNTER_CNTCVL_NS_REG (CSR_COUNTER_BASE + 0x1008) /* COUNTER非安全低位计数值寄存器。 */ +#define CSR_COUNTER_CNTCVH_NS_REG (CSR_COUNTER_BASE + 0x100C) /* COUNTER非安全高位计数值寄存器。 */ + +/* TIMER64 Base address of Module's Register */ +#define CSR_TIMER64_BASE (0x182A000) + +/* **************************************************************************** */ +/* TIMER64 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TIMER64_TIMER0_LOAD_L_REG (CSR_TIMER64_BASE + 0x0) /* Timer0_LOAD为Timer0计数初值寄存器低32位。 */ +#define CSR_TIMER64_TIMER0_LOAD_H_REG (CSR_TIMER64_BASE + 0x4) /* Timer0_LOAD为Timer0计数初值寄存器高32位。 */ +#define CSR_TIMER64_TIMER0_VALUE_L_REG (CSR_TIMER64_BASE + 0x8) /* Timer0_VALUE为Timer0当前计数值寄存器低32位。 */ +#define CSR_TIMER64_TIMER0_VALUE_H_REG (CSR_TIMER64_BASE + 0xC) /* Timer0_VALUE为Timer0当前计数值寄存器高32位。 */ +#define CSR_TIMER64_TIMER0_CONTROL_REG (CSR_TIMER64_BASE + 0x10) /* Timer0_CONTROL为Timer0控制寄存器。 */ +#define CSR_TIMER64_TIMER0_INTCLR_REG \ + (CSR_TIMER64_BASE + 0x14) /* Timer0_INTCLR为Timer0中断清除寄存器。注意：本寄存器是只写寄存器，写进去任意值，都会引起Timer清中断，内部并不记忆写入的值，无复位值。 \ + */ +#define CSR_TIMER64_TIMER0_RIS_REG (CSR_TIMER64_BASE + 0x18) /* Timer0_RIS为Timer0原始中断状态寄存器。 */ +#define CSR_TIMER64_TIMER0_MIS_REG (CSR_TIMER64_BASE + 0x1C) /* Timer0_MIS为Timer0屏蔽后中断状态寄存器。 */ +#define CSR_TIMER64_TIMER0_BGLOAD_L_REG \ + (CSR_TIMER64_BASE + 0x20) /* Timer0_BGLOAD为Timer0循环模式计数初值寄存器低32位。 */ +#define CSR_TIMER64_TIMER0_BGLOAD_H_REG \ + (CSR_TIMER64_BASE + 0x24) /* Timer0_BGLOAD为Timer0循环模式计数初值寄存器高32位。 */ +#define CSR_TIMER64_TIMER1_LOAD_L_REG (CSR_TIMER64_BASE + 0x40) /* Timer1_LOAD为Timer1计数初值寄存器低32位。 */ +#define CSR_TIMER64_TIMER1_LOAD_H_REG (CSR_TIMER64_BASE + 0x44) /* Timer1_LOAD为Timer1计数初值寄存器高32位。 */ +#define CSR_TIMER64_TIMER1_VALUE_L_REG (CSR_TIMER64_BASE + 0x48) /* Timer1_VALUE为Timer1当前计数值寄存器低32位。 */ +#define CSR_TIMER64_TIMER1_VALUE_H_REG (CSR_TIMER64_BASE + 0x4C) /* Timer1_VALUE为Timer1当前计数值寄存器高32位。 */ +#define CSR_TIMER64_TIMER1_CONTROL_REG (CSR_TIMER64_BASE + 0x50) /* Timer1_CONTROL为Timer1控制寄存器。 */ +#define CSR_TIMER64_TIMER1_INTCLR_REG \ + (CSR_TIMER64_BASE + 0x54) /* Timer1_INTCLR为Timer1中断清除寄存器。注意：本寄存器是只写寄存器，写进去任意值，都会引起Timer清中断，内部并不记忆写入的值，无复位值。 \ + */ +#define CSR_TIMER64_TIMER1_RIS_REG (CSR_TIMER64_BASE + 0x58) /* Timer1_RIS为Timer1原始中断状态寄存器。 */ +#define CSR_TIMER64_TIMER1_MIS_REG (CSR_TIMER64_BASE + 0x5C) /* Timer1_MIS为Timer1屏蔽后中断状态寄存器。 */ +#define CSR_TIMER64_TIMER1_BGLOAD_L_REG \ + (CSR_TIMER64_BASE + 0x60) /* Timer1_BGLOAD为Timer1循环模式计数初值寄存器低32位。 */ +#define CSR_TIMER64_TIMER1_BGLOAD_H_REG \ + (CSR_TIMER64_BASE + 0x64) /* Timer1_BGLOAD为Timer1循环模式计数初值寄存器高32位。 */ + +/* GPIO Base address of Module's Register */ +#define CSR_GPIO_BASE (0x1820000) + +/* **************************************************************************** */ +/* GPIO Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_GPIO_GPIO_DATA_REG (CSR_GPIO_BASE + 0x0) /* 数据寄存器。 */ +#define CSR_GPIO_GPIO_DIRECTION_REG (CSR_GPIO_BASE + 0x4) /* 数据方向寄存器。 */ +#define CSR_GPIO_GPIO_CTL_REG (CSR_GPIO_BASE + 0x8) /* 工作模式寄存器。 */ +#define CSR_GPIO_GPIO_INTEN_REG (CSR_GPIO_BASE + 0x30) /* 中断使能寄存器。 */ +#define CSR_GPIO_GPIO_INTMASK_REG (CSR_GPIO_BASE + 0x34) /* 中断屏蔽寄存器。 */ +#define CSR_GPIO_GPIO_INTTYPE_LEVEL_REG (CSR_GPIO_BASE + 0x38) /* 中断类型选择寄存器。 */ +#define CSR_GPIO_GPIO_INT_POLARITY_REG (CSR_GPIO_BASE + 0x3C) /* 中断信号极性选择寄存器。 */ +#define CSR_GPIO_GPIO_INTSTATUS_REG (CSR_GPIO_BASE + 0x40) /* 中断状态寄存器。 */ +#define CSR_GPIO_GPIO_RAWINTSTATUS_REG (CSR_GPIO_BASE + 0x44) /* 原始中断状态寄存器。 */ +#define CSR_GPIO_GPIO_DEBOUNCE_REG (CSR_GPIO_BASE + 0x48) /* 外接信号去毛刺寄存器。 */ +#define CSR_GPIO_GPIO_PORTA_EOI_REG (CSR_GPIO_BASE + 0x4C) /* 清除中断指示寄存器。 */ +#define CSR_GPIO_GPIO_EXT_PORTA_REG (CSR_GPIO_BASE + 0x50) /* 外部端口值寄存器。 */ +#define CSR_GPIO_GPIO_LS_SYNC_REG (CSR_GPIO_BASE + 0x60) /* 外接信号同步选择寄存器。 */ +#define CSR_GPIO_GPIO_ID_CODE_REG (CSR_GPIO_BASE + 0x64) /* ID编码寄存器。 */ +#define CSR_GPIO_GPIO_COMP_VER_REG (CSR_GPIO_BASE + 0x6C) /* 器件版本寄存器。 */ + +/* UART Base address of Module's Register */ +#define CSR_UART_BASE (0x181D000) + +/* **************************************************************************** */ +/* UART Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_UART_THR_RBR_DLL_REG (CSR_UART_BASE + 0x0) /* 发送/接收数据缓存寄存器/低位分频因子寄存器。 */ +#define CSR_UART_IER_REG (CSR_UART_BASE + 0x4) /* 中断使能/高位分频因子寄存器。 */ +#define CSR_UART_FCR_REG (CSR_UART_BASE + 0x8) /* FIFO控制/中断状态寄存器。 */ +#define CSR_UART_LCR_REG (CSR_UART_BASE + 0xC) /* 线性控制寄存器。 */ +#define CSR_UART_MCR_REG (CSR_UART_BASE + 0x10) /* MODEM控制寄存器。 */ +#define CSR_UART_LSR_REG (CSR_UART_BASE + 0x14) /* 线性状态寄存器。 */ +#define CSR_UART_SCR_REG (CSR_UART_BASE + 0x1C) /* 暂存寄存器。 */ +#define CSR_UART_FAR_REG (CSR_UART_BASE + 0x70) /* FIFO访问控制寄存器。 */ +#define CSR_UART_TFR_REG (CSR_UART_BASE + 0x74) /* 发送FIFO读寄存器。 */ +#define CSR_UART_RFW_REG (CSR_UART_BASE + 0x78) /* 接收FIFO写寄存器。 */ +#define CSR_UART_USR_REG (CSR_UART_BASE + 0x7C) /* UART状态寄存器。 */ +#define CSR_UART_TFL_REG (CSR_UART_BASE + 0x80) /* 发送FIFO水线寄存器。 */ +#define CSR_UART_RFL_REG (CSR_UART_BASE + 0x84) /* 接收FIFO水线寄存器。 */ +#define CSR_UART_HTX_REG (CSR_UART_BASE + 0xA4) /* 暂停发送寄存器。 */ +#define CSR_UART_DMASA_REG (CSR_UART_BASE + 0xA8) /* DMA软件响应寄存器。 */ +#define CSR_UART_CPR_REG (CSR_UART_BASE + 0xF4) /* 参数配置寄存器。 */ +#define CSR_UART_UCV_REG (CSR_UART_BASE + 0xF8) /* 版本寄存器。 */ +#define CSR_UART_CTR_REG (CSR_UART_BASE + 0xFC) /* 类型寄存器。 */ + +/* SMBUS Base address of Module's Register */ +#define CSR_SMBUS_BASE (0x181C000) + +/* **************************************************************************** */ +/* SMBUS Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMBUS_I2C_CON_REG (CSR_SMBUS_BASE + 0x0) /* I2C控制寄存器。 */ +#define CSR_SMBUS_I2C_TAR_REG (CSR_SMBUS_BASE + 0x4) /* I2C访问Slave地址寄存器。 */ +#define CSR_SMBUS_I2C_SAR_REG (CSR_SMBUS_BASE + 0x8) /* I2C作为Slave时的地址寄存器。 */ +#define CSR_SMBUS_I2C_DATA_CMD_REG (CSR_SMBUS_BASE + 0x10) /* I2C数据操作寄存器。 */ +#define CSR_SMBUS_I2C_SS_SCL_HCNT_REG (CSR_SMBUS_BASE + 0x14) /* I2C标准速度模式SCL高电平配置寄存器。 */ +#define CSR_SMBUS_I2C_SS_SCL_LCNT_REG (CSR_SMBUS_BASE + 0x18) /* I2C标准速度模式SCL低电平配置寄存器。 */ +#define CSR_SMBUS_I2C_FS_SCL_HCNT_REG (CSR_SMBUS_BASE + 0x1C) /* I2C快速模式SCL高电平配置寄存器。 */ +#define CSR_SMBUS_I2C_FS_SCL_LCNT_REG (CSR_SMBUS_BASE + 0x20) /* I2C快速模式SCL低电平配置寄存器。 */ +#define CSR_SMBUS_I2C_INTR_STAT_REG (CSR_SMBUS_BASE + 0x2C) /* I2C使能后中断状态寄存器。 */ +#define CSR_SMBUS_I2C_INTR_EN_REG (CSR_SMBUS_BASE + 0x30) /* I2C中断使能寄存器。 */ +#define CSR_SMBUS_I2C_INTR_RAW_REG (CSR_SMBUS_BASE + 0x34) /* I2C原始中断状态寄存器。 */ +#define CSR_SMBUS_I2C_RX_TL_REG (CSR_SMBUS_BASE + 0x38) /* RX_FIFO水线设置寄存器。 */ +#define CSR_SMBUS_I2C_TX_TL_REG (CSR_SMBUS_BASE + 0x3C) /* TX_FIFO水线设置寄存器。 */ +#define CSR_SMBUS_I2C_ENABLE_REG (CSR_SMBUS_BASE + 0x6C) /* I2C工作使能寄存器。 */ +#define CSR_SMBUS_I2C_STATUS_REG (CSR_SMBUS_BASE + 0x70) /* I2C状态寄存器。 */ +#define CSR_SMBUS_I2C_TXFLR_REG (CSR_SMBUS_BASE + 0x74) /* TX_FIFO有效数据指示寄存器。 */ +#define CSR_SMBUS_I2C_RXFLR_REG (CSR_SMBUS_BASE + 0x78) /* RX_FIFO有效数据指示寄存器。 */ +#define CSR_SMBUS_I2C_SDA_HOLD_REG (CSR_SMBUS_BASE + 0x7C) /* SDA保持时间配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_ABRT_SRC_REG (CSR_SMBUS_BASE + 0x80) /* I2C发送失败中断源寄存器。 */ +#define CSR_SMBUS_I2C_SDA_SETUP_REG (CSR_SMBUS_BASE + 0x94) /* SDA建立时间配置寄存器。 */ +#define CSR_SMBUS_I2C_ACK_GENERAL_CALL_REG (CSR_SMBUS_BASE + 0x98) /* General Call应答设置寄存器。 */ +#define CSR_SMBUS_I2C_ENABLE_STATUS_REG (CSR_SMBUS_BASE + 0x9C) /* I2C状态寄存器。 */ +#define CSR_SMBUS_I2C_SCL_SWITCH_REG (CSR_SMBUS_BASE + 0xA0) /* I2C防挂死SCL使能寄存器。 */ +#define CSR_SMBUS_I2C_SCL_SIM_REG (CSR_SMBUS_BASE + 0xA4) /* I2C防挂死SCL模拟寄存器。 */ +#define CSR_SMBUS_I2C_LPIF_STATE_REG (CSR_SMBUS_BASE + 0xA8) /* I2C低功耗状态机状态寄存器。 */ +#define CSR_SMBUS_I2C_LOCK_REG (CSR_SMBUS_BASE + 0xAC) /* I2C lock寄存器。 */ +#define CSR_SMBUS_I2C_SDA_SWITCH_REG (CSR_SMBUS_BASE + 0xB0) /* I2C防挂死SDA使能寄存器。 */ +#define CSR_SMBUS_I2C_SDA_SIM_REG (CSR_SMBUS_BASE + 0xB4) /* I2C防挂死SDA模拟寄存器。 */ +#define CSR_SMBUS_I2C_SAR_MASK_REG (CSR_SMBUS_BASE + 0x100) /* Slave地址屏蔽寄存器。 */ +#define CSR_SMBUS_I2C_PMBUS_CTRL_REG (CSR_SMBUS_BASE + 0x104) /* PMBUS全局控制寄存器。 */ +#define CSR_SMBUS_I2C_LOW_TIMEOUT_REG (CSR_SMBUS_BASE + 0x108) /* SCL低电平超时值配置寄存器。 */ +#define CSR_SMBUS_I2C_HIGH_TIMEOUT_REG (CSR_SMBUS_BASE + 0x10C) /* SCL高电平超时值配置寄存器。 */ +#define CSR_SMBUS_I2C_SLV_ALERT_SET_REG (CSR_SMBUS_BASE + 0x110) /* Slave模式下Alert输出配置寄存器。 */ +#define CSR_SMBUS_I2C_MST_ALERT_DO_REG (CSR_SMBUS_BASE + 0x114) /* Master模式下Alert命令触发寄存器。 */ +#define CSR_SMBUS_I2C_ACK_RESP_REG (CSR_SMBUS_BASE + 0x118) /* Slave模式下响应寄存器。 */ +#define CSR_SMBUS_I2C_PEC_INFO_REG (CSR_SMBUS_BASE + 0x11C) /* PEC信息寄存器。 */ +#define CSR_SMBUS_I2C_ADDR_RECEIVE_REG (CSR_SMBUS_BASE + 0x120) /* Slave收到的地址查询寄存器。 */ +#define CSR_SMBUS_I2C_MANU_ACK_CNT_REG (CSR_SMBUS_BASE + 0x124) /* Slave配置手动响应ACK/NACK次数寄存器。 */ +#define CSR_SMBUS_I2C_GRP_CMD_REG (CSR_SMBUS_BASE + 0x128) /* PMBUS group command使能寄存器。 */ +#define CSR_SMBUS_I2C_PMBUS_SCL_DET_REG (CSR_SMBUS_BASE + 0x12C) /* PMBUS SCL检测寄存器。 */ +#define CSR_SMBUS_I2C_PMBUS_IDLECNT_REG (CSR_SMBUS_BASE + 0x130) /* SCL高电平空闲值配置寄存器。 */ +#define CSR_SMBUS_I2C_PMBUS_RST_REG (CSR_SMBUS_BASE + 0x134) /* 软件复位配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_0_REG (CSR_SMBUS_BASE + 0x138) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_1_REG (CSR_SMBUS_BASE + 0x13C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_2_REG (CSR_SMBUS_BASE + 0x140) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_3_REG (CSR_SMBUS_BASE + 0x144) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_4_REG (CSR_SMBUS_BASE + 0x148) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_5_REG (CSR_SMBUS_BASE + 0x14C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_6_REG (CSR_SMBUS_BASE + 0x150) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_7_REG (CSR_SMBUS_BASE + 0x154) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_8_REG (CSR_SMBUS_BASE + 0x158) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_9_REG (CSR_SMBUS_BASE + 0x15C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_10_REG (CSR_SMBUS_BASE + 0x160) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_11_REG (CSR_SMBUS_BASE + 0x164) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_12_REG (CSR_SMBUS_BASE + 0x168) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_13_REG (CSR_SMBUS_BASE + 0x16C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_14_REG (CSR_SMBUS_BASE + 0x170) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_15_REG (CSR_SMBUS_BASE + 0x174) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_16_REG (CSR_SMBUS_BASE + 0x178) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_17_REG (CSR_SMBUS_BASE + 0x17C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_18_REG (CSR_SMBUS_BASE + 0x180) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_19_REG (CSR_SMBUS_BASE + 0x184) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_20_REG (CSR_SMBUS_BASE + 0x188) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_21_REG (CSR_SMBUS_BASE + 0x18C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_22_REG (CSR_SMBUS_BASE + 0x190) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_23_REG (CSR_SMBUS_BASE + 0x194) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_24_REG (CSR_SMBUS_BASE + 0x198) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_25_REG (CSR_SMBUS_BASE + 0x19C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_26_REG (CSR_SMBUS_BASE + 0x1A0) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_27_REG (CSR_SMBUS_BASE + 0x1A4) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_28_REG (CSR_SMBUS_BASE + 0x1A8) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_29_REG (CSR_SMBUS_BASE + 0x1AC) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_30_REG (CSR_SMBUS_BASE + 0x1B0) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_31_REG (CSR_SMBUS_BASE + 0x1B4) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_32_REG (CSR_SMBUS_BASE + 0x1B8) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_33_REG (CSR_SMBUS_BASE + 0x1BC) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_34_REG (CSR_SMBUS_BASE + 0x1C0) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_35_REG (CSR_SMBUS_BASE + 0x1C4) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_36_REG (CSR_SMBUS_BASE + 0x1C8) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_37_REG (CSR_SMBUS_BASE + 0x1CC) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_38_REG (CSR_SMBUS_BASE + 0x1D0) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_39_REG (CSR_SMBUS_BASE + 0x1D4) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_40_REG (CSR_SMBUS_BASE + 0x1D8) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_41_REG (CSR_SMBUS_BASE + 0x1DC) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_42_REG (CSR_SMBUS_BASE + 0x1E0) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_43_REG (CSR_SMBUS_BASE + 0x1E4) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_44_REG (CSR_SMBUS_BASE + 0x1E8) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_45_REG (CSR_SMBUS_BASE + 0x1EC) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_46_REG (CSR_SMBUS_BASE + 0x1F0) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_47_REG (CSR_SMBUS_BASE + 0x1F4) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_48_REG (CSR_SMBUS_BASE + 0x1F8) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_49_REG (CSR_SMBUS_BASE + 0x1FC) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_50_REG (CSR_SMBUS_BASE + 0x200) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_51_REG (CSR_SMBUS_BASE + 0x204) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_52_REG (CSR_SMBUS_BASE + 0x208) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_53_REG (CSR_SMBUS_BASE + 0x20C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_54_REG (CSR_SMBUS_BASE + 0x210) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_55_REG (CSR_SMBUS_BASE + 0x214) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_56_REG (CSR_SMBUS_BASE + 0x218) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_57_REG (CSR_SMBUS_BASE + 0x21C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_58_REG (CSR_SMBUS_BASE + 0x220) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_59_REG (CSR_SMBUS_BASE + 0x224) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_60_REG (CSR_SMBUS_BASE + 0x228) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_61_REG (CSR_SMBUS_BASE + 0x22C) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_62_REG (CSR_SMBUS_BASE + 0x230) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_INFO_63_REG (CSR_SMBUS_BASE + 0x234) /* I2C发送配置寄存器。 */ +#define CSR_SMBUS_I2C_TX_CNT_REG (CSR_SMBUS_BASE + 0x238) /* I2C发送数据个数配置寄存器 */ +#define CSR_SMBUS_I2C_TRIGGER_EN_REG (CSR_SMBUS_BASE + 0x23C) /* I2C发送出发使能配置寄存器。 */ +#define CSR_SMBUS_SMB_UDID_0_REG (CSR_SMBUS_BASE + 0x240) /* UDID配置寄存器 */ +#define CSR_SMBUS_SMB_UDID_1_REG (CSR_SMBUS_BASE + 0x244) /* UDID配置寄存器 */ +#define CSR_SMBUS_SMB_UDID_2_REG (CSR_SMBUS_BASE + 0x248) /* UDID配置寄存器 */ +#define CSR_SMBUS_SMB_UDID_3_REG (CSR_SMBUS_BASE + 0x24C) /* UDID配置寄存器 */ +#define CSR_SMBUS_SMB_ARP_ADDR_REG (CSR_SMBUS_BASE + 0x250) /* ARP地址分配寄存器 */ +#define CSR_SMBUS_SMB_PSA_REG (CSR_SMBUS_BASE + 0x254) /* PSA地址分配寄存器 */ +#define CSR_SMBUS_SMB_NOTIFY_DO_REG (CSR_SMBUS_BASE + 0x258) /* Slave模式下启动发送"Notify ARP master"触发寄存器 */ +#define CSR_SMBUS_SMB_ARP_INFO_REG (CSR_SMBUS_BASE + 0x25C) /* ARP信息寄存器 */ + +/* SMBUS_NEW_CFG Base address of Module's Register */ +#define CSR_SMBUS_NEW_BASE (0x2181B000) + +/* **************************************************************************** */ +/* SMBUS_NEW_CFG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMBUS_NEW_IC_CON_REG \ + (CSR_SMBUS_NEW_BASE + 0x0) /* I2C控制寄存器。注意：只在I2C被禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_TAR_REG \ + (CSR_SMBUS_NEW_BASE + 0x4) /* I2C访问Slave地址寄存器。注意：只在I2C被禁止（即I2C_ENABLE[enable]为0）时才可配置。 \ + */ +#define CSR_SMBUS_NEW_IC_SAR_REG \ + (CSR_SMBUS_NEW_BASE + 0x8) /* I2C访问源设备地址寄存器。注意：只在I2C被禁止（即I2C_ENABLE[enable]为0）时才可配置。 \ + */ +#define CSR_SMBUS_NEW_IC_HS_MADDR_REG \ + (CSR_SMBUS_NEW_BASE + 0xC) /* HS模式下Mater地址注意：只在I2C被禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_DATA_CMD_REG (CSR_SMBUS_NEW_BASE + 0x10) /* I2C数据通道寄存器。 */ +#define CSR_SMBUS_NEW_IC_SS_SCL_HCNT_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x14) /* 标准速度下的SCL时钟高电平时间寄存器。注意：只在I2C被禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_SS_SCL_LCNT_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x18) /* 标准速度下的SCL时钟低电平时间寄存器。注意：只在I2C禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_FS_SCL_HCNT_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x1C) /* 快速速度下的SCL 时钟高电平时间寄存器。注意：只在I2C禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_FS_SCL_LCNT_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x20) /* 快速速度下的SCL \ + 时钟低电平时间寄存器。I2C_FS_SCL_LCNT只在I2C禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_HS_SCL_HCNT_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x24) /* 高速模式下SCL时钟高电平时间配置寄存器注意：只在I2C禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_HS_SCL_LCNT_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x28) /* 高速模式下SCL时钟低电平时间配置寄存器注意：只在I2C禁止（即I2C_ENABLE[enable]为0）时才可配置。 */ +#define CSR_SMBUS_NEW_IC_INTR_STAT_REG (CSR_SMBUS_NEW_BASE + 0x2C) /* I2C中断状态寄存器。 */ +#define CSR_SMBUS_NEW_IC_INTR_MASK_REG (CSR_SMBUS_NEW_BASE + 0x30) /* I2C中断屏蔽寄存器。 */ +#define CSR_SMBUS_NEW_IC_RAW_INTR_STAT_REG (CSR_SMBUS_NEW_BASE + 0x34) /* I2C原始中断状态寄存器。 */ +#define CSR_SMBUS_NEW_IC_RX_TL_REG (CSR_SMBUS_NEW_BASE + 0x38) /* RX_FIFO阈值寄存器。 */ +#define CSR_SMBUS_NEW_IC_TX_TL_REG (CSR_SMBUS_NEW_BASE + 0x3C) /* TX_FIFO阈值寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_INTR_REG (CSR_SMBUS_NEW_BASE + 0x40) /* I2C组合及独立中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_RX_UNDER_REG (CSR_SMBUS_NEW_BASE + 0x44) /* RX_UNDER中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_RX_OVER_REG (CSR_SMBUS_NEW_BASE + 0x48) /* RX_OVER中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_TX_OVER_REG (CSR_SMBUS_NEW_BASE + 0x4C) /* TX_OVER中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_RD_REQ_REG (CSR_SMBUS_NEW_BASE + 0x50) /* RD_REQ中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_TX_ABRT_REG (CSR_SMBUS_NEW_BASE + 0x54) /* TX_ABRT中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_RX_DONE_REG (CSR_SMBUS_NEW_BASE + 0x58) /* RX_DONE中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_ACTIVITY_REG (CSR_SMBUS_NEW_BASE + 0x5C) /* activity状态寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_STOP_DET_REG (CSR_SMBUS_NEW_BASE + 0x60) /* STOP_DET中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_START_DET_REG (CSR_SMBUS_NEW_BASE + 0x64) /* START_DET中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_CLR_GEN_CALL_REG (CSR_SMBUS_NEW_BASE + 0x68) /* General Call中断清除寄存器。 */ +#define CSR_SMBUS_NEW_IC_ENABLE_REG (CSR_SMBUS_NEW_BASE + 0x6C) /* I2C工作模式使能寄存器。 */ +#define CSR_SMBUS_NEW_IC_STATUS_REG (CSR_SMBUS_NEW_BASE + 0x70) /* I2C状态寄存器。 */ +#define CSR_SMBUS_NEW_IC_TXFLR_REG (CSR_SMBUS_NEW_BASE + 0x74) /* TX_FIFO中的数据个数指示寄存器。 */ +#define CSR_SMBUS_NEW_IC_RXFLR_REG (CSR_SMBUS_NEW_BASE + 0x78) /* RX_FIFO中的数据个数指示寄存器。 */ +#define CSR_SMBUS_NEW_IC_SDA_HOLD_REG \ + (CSR_SMBUS_NEW_BASE + 0x7C) /* I2C_SDA_HOLD为SDA信号在SCL的下降沿后的hold延迟时间。 */ +#define CSR_SMBUS_NEW_IC_TX_ABRT_SOURCE_REG \ + (CSR_SMBUS_NEW_BASE + \ + 0x80) /* 发送失败中断源头寄存器。读I2C_CLR_INTR或I2C_CLR_TX_ABRT时，I2C_TX_ABRT_SOURCE清零。 */ +#define CSR_SMBUS_NEW_IC_SLV_DATA_ONLY_REG (CSR_SMBUS_NEW_BASE + 0x84) /* slave数据NACK产生控制寄存器。 */ +#define CSR_SMBUS_NEW_IC_SDA_SETUP_REG (CSR_SMBUS_NEW_BASE + 0x94) /* SDA建立时间设置寄存器。 */ +#define CSR_SMBUS_NEW_IC_ACK_GENERAL_CALL_REG (CSR_SMBUS_NEW_BASE + 0x98) /* General Call应答设置寄存器。 */ +#define CSR_SMBUS_NEW_IC_ENABLE_STATUS_REG (CSR_SMBUS_NEW_BASE + 0x9C) /* I2C状态寄存器。 */ +#define CSR_SMBUS_NEW_IC_FS_SPKLEN_REG (CSR_SMBUS_NEW_BASE + 0xA0) /* I2C时钟频率调整寄存器。 */ +#define CSR_SMBUS_NEW_IC_SCL_STUCK_AT_LOW_TIMEOUT_REG (CSR_SMBUS_NEW_BASE + 0xAC) /* SCL STUCK AT Low的Timeout门限 */ +#define CSR_SMBUS_NEW_IC_SDA_STUCK_AT_LOW_TIMEOUT_REG (CSR_SMBUS_NEW_BASE + 0xB0) /* SDA STUCK AT Low的Timeout门限 */ +#define CSR_SMBUS_NEW_IC_CLR_SCL_STUCK_DET_REG (CSR_SMBUS_NEW_BASE + 0xB4) /* 清除SCL STUCK AT Low中断 */ +#define CSR_SMBUS_NEW_IC_SMBUS_CLK_LOW_SEXT_REG (CSR_SMBUS_NEW_BASE + 0xBC) /* CLK_LOW_SEXT_TIMEOUT门限 */ +#define CSR_SMBUS_NEW_IC_SMBUS_CLK_LOW_MEXT_REG (CSR_SMBUS_NEW_BASE + 0xC0) /* CLK_LOW_MEXT_TIMEOUT门限 */ +#define CSR_SMBUS_NEW_IC_SMBUS_THIGH_MAX_IDLE_COUNT_REG (CSR_SMBUS_NEW_BASE + 0xC4) /* THIGH_MAX_BUS_IDLE_CNT门限 */ +#define CSR_SMBUS_NEW_IC_SMBUS_INTR_STAT_REG (CSR_SMBUS_NEW_BASE + 0xC8) /* SMBUS中断状态 */ +#define CSR_SMBUS_NEW_IC_SMBUS_INTR_MASK_REG (CSR_SMBUS_NEW_BASE + 0xCC) /* SMBus中断mask */ +#define CSR_SMBUS_NEW_IC_SMBUS_RAW_INTR_STAT_REG (CSR_SMBUS_NEW_BASE + 0xD0) /* SMBUS原始中断状态 */ +#define CSR_SMBUS_NEW_IC_CLR_SMBUS_INTR_REG (CSR_SMBUS_NEW_BASE + 0xD4) /* SMBus中断清除寄存器 */ +#define CSR_SMBUS_NEW_IC_SMBUS_UDID_LSB_REG (CSR_SMBUS_NEW_BASE + 0xDC) /* SMBUS UDID BIT31:0 */ +#define CSR_SMBUS_NEW_IC_COMP_PARAM_1_REG (CSR_SMBUS_NEW_BASE + 0xF4) /* COMP参数 */ +#define CSR_SMBUS_NEW_IC_COMP_VERSION_REG (CSR_SMBUS_NEW_BASE + 0xF8) /* COMP版本 */ +#define CSR_SMBUS_NEW_IC_COMP_TYPE_REG (CSR_SMBUS_NEW_BASE + 0xFC) /* COMP类型 */ +#define CSR_SMBUS_NEW_IC_SMBUS_UDID_MSB0_REG (CSR_SMBUS_NEW_BASE + 0xE0) /* SMBUS UDID BIT63:32 */ +#define CSR_SMBUS_NEW_IC_SMBUS_UDID_MSB1_REG (CSR_SMBUS_NEW_BASE + 0xE4) /* SMBUS UDID BIT95:64 */ +#define CSR_SMBUS_NEW_IC_SMBUS_UDID_MSB2_REG (CSR_SMBUS_NEW_BASE + 0xE8) /* SMBUS UDID BIT127:96 */ + +/* SHM_CSR Base address of Module's Register */ +#define CSR_SHM_CSR_BASE (0x1807000) + +/* **************************************************************************** */ +/* SHM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SHM_CSR_SHM_INIT_CHK_MODE_REG (CSR_SHM_CSR_BASE + 0x0) /* SHM初始化自检模式配置寄存器 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_START_REG (CSR_SHM_CSR_BASE + 0x4) /* SHM初始化自检启动脉冲产生寄存器 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_STAT_REG (CSR_SHM_CSR_BASE + 0x8) /* SHM初始化自检完成状态寄存器 */ +#define CSR_SHM_CSR_SHM_INT_STAT_REG (CSR_SHM_CSR_BASE + 0x20) /* SHM中断状态寄存器 */ +#define CSR_SHM_CSR_SHM_INT_EN_REG (CSR_SHM_CSR_BASE + 0x30) /* SHM中断使能寄存器 */ +#define CSR_SHM_CSR_SHM_INT_SET_REG (CSR_SHM_CSR_BASE + 0x34) /* SHM中断置位寄存器 */ +#define CSR_SHM_CSR_SHM_RAW_STAT_REG (CSR_SHM_CSR_BASE + 0x38) /* SHM原始中断状态寄存器 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_SADDR_REG (CSR_SHM_CSR_BASE + 0xA0) /* SHM初始化自检起始地址 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_LEN_REG (CSR_SHM_CSR_BASE + 0xA4) /* SHM初始化自检长度 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_LDATA_REG (CSR_SHM_CSR_BASE + 0xA8) /* 数据初始化自检写入数据低32bit */ +#define CSR_SHM_CSR_SHM_INIT_CHK_HDATA_REG (CSR_SHM_CSR_BASE + 0xAC) /* 数据初始化自检写入数据高32bit */ +#define CSR_SHM_CSR_SHM_ECC_BYPASS_REG (CSR_SHM_CSR_BASE + 0xB0) /* SHM ECC功能使能寄存器 */ +#define CSR_SHM_CSR_SHM_ECC_INSR_REG (CSR_SHM_CSR_BASE + 0xB4) /* SHM ECC错误注入寄存器 */ +#define CSR_SHM_CSR_SHM_ECC_RST_REG (CSR_SHM_CSR_BASE + 0xB8) /* SHM ECC信息复位寄存器 */ +#define CSR_SHM_CSR_SHM_PW_MODE_REG (CSR_SHM_CSR_BASE + 0xBC) /* 软件控制SHM进入低功耗模式寄存器 */ +#define CSR_SHM_CSR_SHM_TMOD_REG (CSR_SHM_CSR_BASE + 0xC0) +#define CSR_SHM_CSR_SHM_STATUS_REG (CSR_SHM_CSR_BASE + 0xC4) /* SHM状态寄存器 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_ERR_REG (CSR_SHM_CSR_BASE + 0xC8) /* 初始化自检错误状态记录寄存器 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_ERR_ADDR_REG (CSR_SHM_CSR_BASE + 0xCC) /* 初始化自检时发生错误的单元地址 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_ERR_LDATA_REG (CSR_SHM_CSR_BASE + 0xD0) /* 初始化自检发生错误时的错误数据 */ +#define CSR_SHM_CSR_SHM_INIT_CHK_ERR_HDATA_REG (CSR_SHM_CSR_BASE + 0xD4) /* 初始化自检发生错误时的错误数据 */ +#define CSR_SHM_CSR_SHM_SERR_CNT_REG (CSR_SHM_CSR_BASE + 0xD8) /* 1bit ECC错误计数器 */ +#define CSR_SHM_CSR_SHM_MERR_CNT_REG (CSR_SHM_CSR_BASE + 0xDC) /* 2bit ECC错误计数器 */ +#define CSR_SHM_CSR_SHM_SERR_ADDR_REG (CSR_SHM_CSR_BASE + 0xF0) /* 最近一次ECC 1bit错误的SRAM地址 */ +#define CSR_SHM_CSR_SHM_MERR_ADDR_REG (CSR_SHM_CSR_BASE + 0xF4) /* 最近一次ECC 2bit错误的SRAM地址 */ + +/* PIE Base address of Module's Register */ +#define CSR_PIE_BASE (0x1808000) + +/* **************************************************************************** */ +/* PIE Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PIE_ECO_RSVD_REG (CSR_PIE_BASE + 0x0) /* ECO保留寄存器 */ +#define CSR_PIE_PIE_INT_RAW_STATUS_REG (CSR_PIE_BASE + 0x10) /* PIE模块错误中断状态寄存器 */ +#define CSR_PIE_PIE_INT_EN_REG (CSR_PIE_BASE + 0x20) /* PIE模块中断屏蔽寄存器 */ +#define CSR_PIE_PIE_INT_SET_REG (CSR_PIE_BASE + 0x30) /* PIE模块软件模拟中断寄存器 */ +#define CSR_PIE_PIE_INT_STATUS_REG (CSR_PIE_BASE + 0x40) /* PIE模块中断状态指示寄存器 */ +#define CSR_PIE_CSR_POOL_FUN_REG (CSR_PIE_BASE + 0xA0) /* pool功能配置寄存器 */ +#define CSR_PIE_CSR_POOL_DEPTH0_REG (CSR_PIE_BASE + 0xA4) /* FIFO 7到FIFO 4深度配置寄存器 */ +#define CSR_PIE_CSR_POOL_DEPTH1_REG (CSR_PIE_BASE + 0xA8) /* FIFO 3到FIFO 0深度配置寄存器 */ +#define CSR_PIE_CSR_PT_PKT_TYPE_REG (CSR_PIE_BASE + 0xAC) /* pass-through报文配置寄存器 */ +#define CSR_PIE_MAX_FRAME_LEN_REG (CSR_PIE_BASE + 0xB0) /* 报文最大长度 */ +#define CSR_PIE_MIN_FRAME_LEN_REG (CSR_PIE_BASE + 0xB4) /* 报文最小长度 */ +#define CSR_PIE_CSR_PEIF_FUN_REG (CSR_PIE_BASE + 0xB8) /* PE接口配置寄存器 */ +#define CSR_PIE_CSR_QM_FUN_REG (CSR_PIE_BASE + 0xBC) /* IQ和OQ的配置寄存器 */ +#define CSR_PIE_DMA_OTD_CNT_REG (CSR_PIE_BASE + 0xC0) /* RxDMA和TxDMA中AXI配置寄存器 */ +#define CSR_PIE_CSR_TXBD_ADDR_REG (CSR_PIE_BASE + 0xC4) /* NCSI的TxBD接口地址寄存器 */ +#define CSR_PIE_CSR_BD2UP_TIME_REG (CSR_PIE_BASE + 0xC8) /* mpu报文处理中断聚合配置寄存器 */ +#define CSR_PIE_CSR_SGL_TIME_REG (CSR_PIE_BASE + 0xCC) /* SGL报文发送完成中断聚合配置寄存器 */ +#define CSR_PIE_CSR_MEM_TMOD_REG (CSR_PIE_BASE + 0xD0) /* MEM的TMOD配置寄存器 */ +#define CSR_PIE_CSR_MEM_DFT_POWER_REG (CSR_PIE_BASE + 0xD4) /* MEM的DFT以及低功耗配置寄存器 */ +#define CSR_PIE_CSR_BD_IF0_WRD0_REG (CSR_PIE_BASE + 0x100) /* FIFO 0配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF0_WRD1_REG (CSR_PIE_BASE + 0x104) /* FIFO 0配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF0_WRD2_REG (CSR_PIE_BASE + 0x108) /* FIFO 0配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF0_WRD3_REG (CSR_PIE_BASE + 0x10C) /* FIFO 0配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF1_WRD0_REG (CSR_PIE_BASE + 0x110) /* FIFO 1配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF1_WRD1_REG (CSR_PIE_BASE + 0x114) /* FIFO 1配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF1_WRD2_REG (CSR_PIE_BASE + 0x118) /* FIFO 1配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF1_WRD3_REG (CSR_PIE_BASE + 0x11C) /* FIFO 1配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF2_WRD0_REG (CSR_PIE_BASE + 0x120) /* FIFO 2配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF2_WRD1_REG (CSR_PIE_BASE + 0x124) /* FIFO 2配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF2_WRD2_REG (CSR_PIE_BASE + 0x128) /* FIFO 2配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF2_WRD3_REG (CSR_PIE_BASE + 0x12C) /* FIFO 2配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF3_WRD0_REG (CSR_PIE_BASE + 0x130) /* FIFO 3配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF3_WRD1_REG (CSR_PIE_BASE + 0x134) /* FIFO 3配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF3_WRD2_REG (CSR_PIE_BASE + 0x138) /* FIFO 3配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF3_WRD3_REG (CSR_PIE_BASE + 0x13C) /* FIFO 3配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF4_WRD0_REG (CSR_PIE_BASE + 0x140) /* FIFO 4配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF4_WRD1_REG (CSR_PIE_BASE + 0x144) /* FIFO 4配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF4_WRD2_REG (CSR_PIE_BASE + 0x148) /* FIFO 4配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF4_WRD3_REG (CSR_PIE_BASE + 0x14C) /* FIFO 4配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF5_WRD0_REG (CSR_PIE_BASE + 0x150) /* FIFO 5配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF5_WRD1_REG (CSR_PIE_BASE + 0x154) /* FIFO 5配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF5_WRD2_REG (CSR_PIE_BASE + 0x158) /* FIFO 5配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF5_WRD3_REG (CSR_PIE_BASE + 0x15C) /* FIFO 5配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF6_WRD0_REG (CSR_PIE_BASE + 0x160) /* FIFO 6配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF6_WRD1_REG (CSR_PIE_BASE + 0x164) /* FIFO 6配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF6_WRD2_REG (CSR_PIE_BASE + 0x168) /* FIFO 6配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF6_WRD3_REG (CSR_PIE_BASE + 0x16C) /* FIFO 6配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF7_WRD0_REG (CSR_PIE_BASE + 0x170) /* FIFO 7配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF7_WRD1_REG (CSR_PIE_BASE + 0x174) /* FIFO 7配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF7_WRD2_REG (CSR_PIE_BASE + 0x178) /* FIFO 7配置接口寄存器 */ +#define CSR_PIE_CSR_BD_IF7_WRD3_REG (CSR_PIE_BASE + 0x17C) /* FIFO 7配置接口寄存器 */ +#define CSR_PIE_RLS_BD_IF0_WRD0_REG (CSR_PIE_BASE + 0x180) /* μP释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF0_WRD1_REG (CSR_PIE_BASE + 0x184) /* μP释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF0_WRD2_REG (CSR_PIE_BASE + 0x188) /* μP释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF0_WRD3_REG (CSR_PIE_BASE + 0x18C) /* μP释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF1_WRD0_REG (CSR_PIE_BASE + 0x190) /* NCSI释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF1_WRD1_REG (CSR_PIE_BASE + 0x194) /* NCSI释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF1_WRD2_REG (CSR_PIE_BASE + 0x198) /* NCSI释放BD接口寄存器 */ +#define CSR_PIE_RLS_BD_IF1_WRD3_REG (CSR_PIE_BASE + 0x19C) /* NCSI释放BD接口寄存器 */ +#define CSR_PIE_ADD_BD_IF0_WRD0_REG (CSR_PIE_BASE + 0x200) /* μP更新BD接口寄存器,SGL模式下写接口寄存器 */ +#define CSR_PIE_ADD_BD_IF0_WRD1_REG (CSR_PIE_BASE + 0x204) /* μP更新BD接口寄存器,SGL模式下写接口寄存器 */ +#define CSR_PIE_ADD_BD_IF0_WRD2_REG (CSR_PIE_BASE + 0x208) /* μP更新BD接口寄存器,SGL模式下写接口寄存器 */ +#define CSR_PIE_ADD_BD_IF0_WRD3_REG (CSR_PIE_BASE + 0x20C) /* μP更新BD接口寄存器,SGL模式下写接口寄存器 */ +#define CSR_PIE_ADD_BD_IF1_WRD0_REG (CSR_PIE_BASE + 0x210) /* NCSI更新BD接口寄存器 */ +#define CSR_PIE_ADD_BD_IF1_WRD1_REG (CSR_PIE_BASE + 0x214) /* NCSI更新BD接口寄存器 */ +#define CSR_PIE_ADD_BD_IF1_WRD2_REG (CSR_PIE_BASE + 0x218) /* NCSI更新BD接口寄存器 */ +#define CSR_PIE_ADD_BD_IF1_WRD3_REG (CSR_PIE_BASE + 0x21C) /* NCSI更新BD接口寄存器 */ +#define CSR_PIE_OQ2UP_BD_IF_WRD0_REG (CSR_PIE_BASE + 0x220) /* 中断读取BD接口寄存器 */ +#define CSR_PIE_OQ2UP_BD_IF_WRD1_REG (CSR_PIE_BASE + 0x224) /* 中断读取BD接口寄存器 */ +#define CSR_PIE_OQ2UP_BD_IF_WRD2_REG (CSR_PIE_BASE + 0x228) /* 中断读取BD接口寄存器 */ +#define CSR_PIE_OQ2UP_BD_IF_WRD3_REG (CSR_PIE_BASE + 0x22C) /* 中断读取BD接口寄存器 */ +#define CSR_PIE_CSR_AXI_MSR_INF_REG (CSR_PIE_BASE + 0x240) /* AXI的master接口配置寄存器 */ +#define CSR_PIE_BD_ERR_STATUS_REG (CSR_PIE_BASE + 0x300) /* BD配置错误状态寄存器 */ +#define CSR_PIE_BM_READ0_CNT_REG (CSR_PIE_BASE + 0x308) /* FIFO0的读BD计数器 */ +#define CSR_PIE_BM_READ1_CNT_REG (CSR_PIE_BASE + 0x30C) /* FIFO1的读BD计数器 */ +#define CSR_PIE_BM_READ2_CNT_REG (CSR_PIE_BASE + 0x310) /* FIFO2的读BD计数器 */ +#define CSR_PIE_BM_READ3_CNT_REG (CSR_PIE_BASE + 0x314) /* FIFO3的读BD计数器 */ +#define CSR_PIE_BM_READ4_CNT_REG (CSR_PIE_BASE + 0x318) /* FIFO4的读BD计数器 */ +#define CSR_PIE_BM_READ5_CNT_REG (CSR_PIE_BASE + 0x31C) /* FIFO5的读BD计数器 */ +#define CSR_PIE_BM_READ6_CNT_REG (CSR_PIE_BASE + 0x320) /* FIFO6的读BD计数器 */ +#define CSR_PIE_BM_READ7_CNT_REG (CSR_PIE_BASE + 0x324) /* FIFO7的读BD计数器 */ +#define CSR_PIE_BM_WRITE0_CNT_REG (CSR_PIE_BASE + 0x328) /* FIFO0的写BD计数器 */ +#define CSR_PIE_BM_WRITE1_CNT_REG (CSR_PIE_BASE + 0x32C) /* FIFO1的写BD计数器 */ +#define CSR_PIE_BM_WRITE2_CNT_REG (CSR_PIE_BASE + 0x330) /* FIFO2的写BD计数器 */ +#define CSR_PIE_BM_WRITE3_CNT_REG (CSR_PIE_BASE + 0x334) /* FIFO3的写BD计数器 */ +#define CSR_PIE_BM_WRITE4_CNT_REG (CSR_PIE_BASE + 0x338) /* FIFO4的写BD计数器 */ +#define CSR_PIE_BM_WRITE5_CNT_REG (CSR_PIE_BASE + 0x33C) /* FIFO5的写BD计数器 */ +#define CSR_PIE_BM_WRITE6_CNT_REG (CSR_PIE_BASE + 0x340) /* FIFO6的写BD计数器 */ +#define CSR_PIE_BM_WRITE7_CNT_REG (CSR_PIE_BASE + 0x344) /* FIFO7的写BD计数器 */ +#define CSR_PIE_BM_FIFO0X1_STATUS_REG (CSR_PIE_BASE + 0x348) /* FIFO 0与FIFO 1状态寄存器 */ +#define CSR_PIE_BM_FIFO2X3_STATUS_REG (CSR_PIE_BASE + 0x34C) /* FIFO 2与FIFO 3状态寄存器 */ +#define CSR_PIE_BM_FIFO4X5_STATUS_REG (CSR_PIE_BASE + 0x350) /* FIFO 4与FIFO 5状态寄存器 */ +#define CSR_PIE_BM_FIFO6X7_STATUS_REG (CSR_PIE_BASE + 0x354) /* FIFO 6与FIFO 7状态寄存器 */ +#define CSR_PIE_BM_READ0_EMP_CNT_REG (CSR_PIE_BASE + 0x358) /* FIFO 0的读空次数计数器 */ +#define CSR_PIE_BM_READ1_EMP_CNT_REG (CSR_PIE_BASE + 0x35C) /* FIFO 1的读空次数计数器 */ +#define CSR_PIE_BM_READ2_EMP_CNT_REG (CSR_PIE_BASE + 0x360) /* FIFO 2的读空次数计数器 */ +#define CSR_PIE_BM_READ3_EMP_CNT_REG (CSR_PIE_BASE + 0x364) /* FIFO 3的读空次数计数器 */ +#define CSR_PIE_BM_READ4_EMP_CNT_REG (CSR_PIE_BASE + 0x368) /* FIFO 4的读空次数计数器 */ +#define CSR_PIE_BM_READ5_EMP_CNT_REG (CSR_PIE_BASE + 0x36C) /* FIFO 5的读空次数计数器 */ +#define CSR_PIE_BM_READ6_EMP_CNT_REG (CSR_PIE_BASE + 0x370) /* FIFO 6的读空次数计数器 */ +#define CSR_PIE_BM_READ7_EMP_CNT_REG (CSR_PIE_BASE + 0x374) /* FIFO 7的读空次数计数器 */ +#define CSR_PIE_RX_PKT_STATUS_REG (CSR_PIE_BASE + 0x378) /* PE发送报文状态寄存器 */ +#define CSR_PIE_NCSI_BPR_CNT_REG (CSR_PIE_BASE + 0x37C) /* NCSI反压次数计数器 */ +#define CSR_PIE_IQ_BD_STATUS_REG (CSR_PIE_BASE + 0x380) /* IQ状态寄存器 */ +#define CSR_PIE_OQ_BD2UP_STATUS_REG (CSR_PIE_BASE + 0x384) /* OQ中BD2UP队列状态寄存器 */ +#define CSR_PIE_OQ_BD2NCSI_STATUS_REG (CSR_PIE_BASE + 0x388) /* OQ中BD2NCSI队列状态寄存器 */ +#define CSR_PIE_OQ_BD2IPSU_STATUS_REG (CSR_PIE_BASE + 0x38C) /* OQ中BD2IPSU队列状态寄存器 */ +#define CSR_PIE_OUT2UP_BD_CNT_REG (CSR_PIE_BASE + 0x390) /* OUT2UP队列发送BD计数器 */ +#define CSR_PIE_OUT2IPSU_BD_CNT_REG (CSR_PIE_BASE + 0x394) /* OUT2IPSU队列发送BD计数器 */ +#define CSR_PIE_OUT2NCSI_BD_CNT_REG (CSR_PIE_BASE + 0x398) /* OUT2NCSI队列发送BD计数器 */ +#define CSR_PIE_OQ_ECCS_CNT_REG (CSR_PIE_BASE + 0x39C) /* OQ队列发生1bit的ECC错误次数统计计数器 */ +#define CSR_PIE_OQ_ECCM_CNT_REG (CSR_PIE_BASE + 0x4A0) /* OQ队列发生2bit的ECC错误次数统计计数器 */ +#define CSR_PIE_AXI_RD_LATENCY_AVG_CNT_REG (CSR_PIE_BASE + 0x4A4) /* AXI master的burst读延迟的平均值 */ +#define CSR_PIE_AXI_WR_LATENCY_AVG_CNT_REG (CSR_PIE_BASE + 0x4A8) /* AXI master的burst写延迟的平均值 */ +#define CSR_PIE_AXI_RD_LATENCY_MAX_CNT_REG (CSR_PIE_BASE + 0x4AC) /* AXI master的burst读延迟的最大值 */ +#define CSR_PIE_AXI_WR_LATENCY_MAX_CNT_REG (CSR_PIE_BASE + 0x4B0) /* AXI master的burst写延迟的最大值 */ +#define CSR_PIE_AXI_RD_ACC_CNT_REG (CSR_PIE_BASE + 0x4B4) /* AXI master的读outstanding总数 */ +#define CSR_PIE_AXI_WR_ACC_CNT_REG (CSR_PIE_BASE + 0x4B8) /* AXI master的写outstanding总数 */ +#define CSR_PIE_AXI_RD_OTD_CNT_REG (CSR_PIE_BASE + 0x4BC) /* AXI读outstanding计数器 */ +#define CSR_PIE_AXI_WR_OTD_CNT_REG (CSR_PIE_BASE + 0x4C0) /* AXI写outstanding计数器 */ +#define CSR_PIE_TXDMA_DAT_FF_TH_REG (CSR_PIE_BASE + 0x4D0) /* TXDMA报文数据存储fifo水线配置寄存器 */ +#define CSR_PIE_TXDMA_DAT_FF_STA_REG (CSR_PIE_BASE + 0x4D4) /* TXDMA报文数据存储fifo状态显示寄存器 */ +#define CSR_PIE_TXDMA_INF_FF_TH_REG (CSR_PIE_BASE + 0x4D8) /* TXDMA报文信息存储fifo水线配置寄存器 */ +#define CSR_PIE_TXDMA_INF_FF_STA_REG (CSR_PIE_BASE + 0x4DC) /* TXDMA报文信息存储fifo状态显示寄存器 */ +#define CSR_PIE_IPSUIF_FF_TH_REG (CSR_PIE_BASE + 0x4E0) /* IPSUIF数据存储fifo水线配置寄存器 */ +#define CSR_PIE_IPSUIF_FF_STA_REG (CSR_PIE_BASE + 0x4E4) /* IPSUIF数据存储fifo状态显示寄存器 */ +#define CSR_PIE_BM_READ0_FUL_CNT_REG (CSR_PIE_BASE + 0x4E8) /* FIFO 0的写满次数计数器 */ +#define CSR_PIE_BM_READ1_FUL_CNT_REG (CSR_PIE_BASE + 0x4EC) /* FIFO 1的写满次数计数器 */ +#define CSR_PIE_BM_READ2_FUL_CNT_REG (CSR_PIE_BASE + 0x4F0) /* FIFO 2的写满次数计数器 */ +#define CSR_PIE_BM_READ3_FUL_CNT_REG (CSR_PIE_BASE + 0x4F4) /* FIFO 3的写满次数计数器 */ +#define CSR_PIE_BM_READ4_FUL_CNT_REG (CSR_PIE_BASE + 0x4F8) /* FIFO 4的写满次数计数器 */ +#define CSR_PIE_BM_READ5_FUL_CNT_REG (CSR_PIE_BASE + 0x4FC) /* FIFO 5的写满次数计数器 */ +#define CSR_PIE_BM_READ6_FUL_CNT_REG (CSR_PIE_BASE + 0x500) /* FIFO 6的写满次数计数器 */ +#define CSR_PIE_BM_READ7_FUL_CNT_REG (CSR_PIE_BASE + 0x504) /* FIFO 7的写满次数计数器 */ +#define CSR_PIE_RX_PARITY_ERR_CNT_REG (CSR_PIE_BASE + 0x508) /* RXDMA中出现的parity校验错误统计计数器 */ +#define CSR_PIE_TX_PARITY_ERR_CNT_REG (CSR_PIE_BASE + 0x50C) /* TXDMA中出现的parity校验错误统计计数器 */ +#define CSR_PIE_TX_MINLEN_ERR_CNT_REG (CSR_PIE_BASE + 0x510) /* TXDMA中长度小于16字节的报文统计计数器 */ +#define CSR_PIE_TX_BDSIZE_ERR_CNT_REG (CSR_PIE_BASE + 0x514) /* TXDMA中长度大于BD SIZE的报文统计计数器 */ +#define CSR_PIE_TX_BDCODE_ERR_CNT_REG (CSR_PIE_BASE + 0x518) /* TXDMA中BDCODE的ERR域中包含错误信息的报文统计计数器 */ +#define CSR_PIE_TX_SGL_CI_TH_REG (CSR_PIE_BASE + 0x51C) /* TXDMA中sgl模型下ci指针计数阈值 */ +#define CSR_PIE_TX_SGL_CI_CNT_REG (CSR_PIE_BASE + 0x520) /* TXDMA中sgl模型下ci指针计数值 */ +#define CSR_PIE_QM_ECC_ERR_ADDR_REG (CSR_PIE_BASE + 0x524) /* QM中ecc错误地址 */ +#define CSR_PIE_PIE_ECC_BYPASS_REG (CSR_PIE_BASE + 0x528) /* PIE中memory的ecc bypass信号 */ +#define CSR_PIE_PEIF_FIFO_STA_REG (CSR_PIE_BASE + 0x52C) /* PEIF中异步fifo的状态信号 */ +#define CSR_PIE_QM_RAM_ECC_INSR_REG (CSR_PIE_BASE + 0x530) /* QM模块内RAM的ECC插错寄存器 */ +#define CSR_PIE_PIE_INITIAL_END_REG (CSR_PIE_BASE + 0x534) /* PIE初始化完成标志寄存器 */ +#define CSR_PIE_TX_RX_RAM_ECC_INSR_REG (CSR_PIE_BASE + 0x538) /* TxDMA与RxDMA内RAM的ECC插错寄存器 */ +#define CSR_PIE_RX_CERR_CNT_REG (CSR_PIE_BASE + 0x53C) /* RxDMA发生1bit的ECC错误次数统计计数器 */ +#define CSR_PIE_RX_UCERR_CNT_REG (CSR_PIE_BASE + 0x540) /* RxDMA发生2bit的ECC错误次数统计计数器 */ +#define CSR_PIE_TX_CERR_CNT_REG (CSR_PIE_BASE + 0x544) /* TxDMA发生1bit的ECC错误次数统计计数器 */ +#define CSR_PIE_TX_UCERR_CNT_REG (CSR_PIE_BASE + 0x548) /* TxDMA发生2bit的ECC错误次数统计计数器 */ +#define CSR_PIE_RX_ECC_ERR_ADDR_REG (CSR_PIE_BASE + 0x54C) /* RxDMA的ECC错误地址 */ +#define CSR_PIE_TX_ECC_ERR_ADDR_REG (CSR_PIE_BASE + 0x550) /* TxDMA的ECC错误地址 */ + +/* MPU_ICL_SUBCTRL Base address of Module's Register */ +#define CSR_MPU_ICL_SUBCTRL_BASE (0x1040000) + +/* **************************************************************************** */ +/* MPU_ICL_SUBCTRL Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MPU_ICL_SUBCTRL_SC_CHAIN_ERR_INT_STATUS_REG \ + (CSR_MPU_ICL_SUBCTRL_BASE + 0x0) /* CFG_BUS CHAIN ERR中断状态寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_CHAIN_ERR_INT_EN_REG \ + (CSR_MPU_ICL_SUBCTRL_BASE + 0x4) /* CFG_BUS CHAIN ERR中断使能寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_CHAIN_ERR_INT_SET_REG \ + (CSR_MPU_ICL_SUBCTRL_BASE + 0x8) /* CFG_BUS CHAIN ERR软件模拟中断寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_CHAIN_ERR_INT_RAW_STATUS_REG \ + (CSR_MPU_ICL_SUBCTRL_BASE + 0xC) /* CFG_BUS CHAIN ERR原始中断状态寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_SAW_ERRRSP_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x10) /* 三级译码的ERR响应类型控制寄存器。 \ + */ +#define CSR_MPU_ICL_SUBCTRL_SC_CFG_SMMU_BDF_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x14) /* SC_CFG_SMMU_BDF控制寄存器。 */ +#define CSR_MPU_ICL_SUBCTRL_SC_CFG_MBIX_DIDBA_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x18) /* SC_CFG_MBIGEN_BDF控制寄存器。 \ + */ +#define CSR_MPU_ICL_SUBCTRL_SC_SMMU_EVENT_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x1C) /* SC_SMMU_EVENT控制寄存器。 */ +#define CSR_MPU_ICL_SUBCTRL_SC_MPU_CTRL_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x20) /* MPU控制寄存器。 */ +#define CSR_MPU_ICL_SUBCTRL_SC_CFG_BUS_CTRL_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x24) /* CFG_BUS_CTRL控制寄存器。 */ +#define CSR_MPU_ICL_SUBCTRL_SC_CMD_DELY_DEFINE_REG \ + (CSR_MPU_ICL_SUBCTRL_BASE + 0x28) /* CFG_BUS 命令之间访问延迟配置寄存器。 */ +#define CSR_MPU_ICL_SUBCTRL_SC_REG_RES_0_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x2C) /* 备用寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_REG_RES_1_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x30) /* 备用寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_REG_RES_2_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x34) /* 备用寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_SC_REG_RES_3_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x38) /* 备用寄存器 */ +#define CSR_MPU_ICL_SUBCTRL_NC_REG_RES_0_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x3C) /* SPU到R52的事务请求中断 */ +#define CSR_MPU_ICL_SUBCTRL_NC_REG_RES_1_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x40) /* SPU到R52的事务应答中断 */ +#define CSR_MPU_ICL_SUBCTRL_NC_REG_RES_2_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x44) /* R52到SPU的事务请求中断 */ +#define CSR_MPU_ICL_SUBCTRL_NC_REG_RES_3_REG (CSR_MPU_ICL_SUBCTRL_BASE + 0x48) /* R52到SPU的事务应答中断 */ + +/* apb2ff_csr Base address of Module's Register */ +#define CSR_APB2FF_CSR_BASE (0x1F03000) + +/* **************************************************************************** */ +/* apb2ff_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_CTRL_REG (CSR_APB2FF_CSR_BASE + 0x100) /* FIC的间接寻址控制寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_TIMEOUT_REG (CSR_APB2FF_CSR_BASE + 0x104) /* FIC的间接寻址最大允许时间寄存器 \ + */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_0_REG (CSR_APB2FF_CSR_BASE + 0x108) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_1_REG (CSR_APB2FF_CSR_BASE + 0x10C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_2_REG (CSR_APB2FF_CSR_BASE + 0x110) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_3_REG (CSR_APB2FF_CSR_BASE + 0x114) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_4_REG (CSR_APB2FF_CSR_BASE + 0x118) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_5_REG (CSR_APB2FF_CSR_BASE + 0x11C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_6_REG (CSR_APB2FF_CSR_BASE + 0x120) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_7_REG (CSR_APB2FF_CSR_BASE + 0x124) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_8_REG (CSR_APB2FF_CSR_BASE + 0x128) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_9_REG (CSR_APB2FF_CSR_BASE + 0x12C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_10_REG (CSR_APB2FF_CSR_BASE + 0x130) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_11_REG (CSR_APB2FF_CSR_BASE + 0x134) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_12_REG (CSR_APB2FF_CSR_BASE + 0x138) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_13_REG (CSR_APB2FF_CSR_BASE + 0x13C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_14_REG (CSR_APB2FF_CSR_BASE + 0x140) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_15_REG (CSR_APB2FF_CSR_BASE + 0x144) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_16_REG (CSR_APB2FF_CSR_BASE + 0x148) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_17_REG (CSR_APB2FF_CSR_BASE + 0x14C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_18_REG (CSR_APB2FF_CSR_BASE + 0x150) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_19_REG (CSR_APB2FF_CSR_BASE + 0x154) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_20_REG (CSR_APB2FF_CSR_BASE + 0x158) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_21_REG (CSR_APB2FF_CSR_BASE + 0x15C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_22_REG (CSR_APB2FF_CSR_BASE + 0x160) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_23_REG (CSR_APB2FF_CSR_BASE + 0x164) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_24_REG (CSR_APB2FF_CSR_BASE + 0x168) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_25_REG (CSR_APB2FF_CSR_BASE + 0x16C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_26_REG (CSR_APB2FF_CSR_BASE + 0x170) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_27_REG (CSR_APB2FF_CSR_BASE + 0x174) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_28_REG (CSR_APB2FF_CSR_BASE + 0x178) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_29_REG (CSR_APB2FF_CSR_BASE + 0x17C) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_30_REG (CSR_APB2FF_CSR_BASE + 0x180) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_INDIR_DATA_31_REG (CSR_APB2FF_CSR_BASE + 0x184) /* FIC的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_FIC_VERSION_REG (CSR_APB2FF_CSR_BASE + 0x188) /* APB2FF模块FIC预留ECO寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_CTRL_REG (CSR_APB2FF_CSR_BASE + 0x400) /* MAG的间接寻址控制寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_TIMEOUT_REG (CSR_APB2FF_CSR_BASE + 0x404) /* MAG的间接寻址最大允许时间寄存器 \ + */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_0_REG (CSR_APB2FF_CSR_BASE + 0x408) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_1_REG (CSR_APB2FF_CSR_BASE + 0x40C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_2_REG (CSR_APB2FF_CSR_BASE + 0x410) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_3_REG (CSR_APB2FF_CSR_BASE + 0x414) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_4_REG (CSR_APB2FF_CSR_BASE + 0x418) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_5_REG (CSR_APB2FF_CSR_BASE + 0x41C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_6_REG (CSR_APB2FF_CSR_BASE + 0x420) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_7_REG (CSR_APB2FF_CSR_BASE + 0x424) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_8_REG (CSR_APB2FF_CSR_BASE + 0x428) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_9_REG (CSR_APB2FF_CSR_BASE + 0x42C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_10_REG (CSR_APB2FF_CSR_BASE + 0x430) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_11_REG (CSR_APB2FF_CSR_BASE + 0x434) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_12_REG (CSR_APB2FF_CSR_BASE + 0x438) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_13_REG (CSR_APB2FF_CSR_BASE + 0x43C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_14_REG (CSR_APB2FF_CSR_BASE + 0x440) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_15_REG (CSR_APB2FF_CSR_BASE + 0x444) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_16_REG (CSR_APB2FF_CSR_BASE + 0x448) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_17_REG (CSR_APB2FF_CSR_BASE + 0x44C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_18_REG (CSR_APB2FF_CSR_BASE + 0x450) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_19_REG (CSR_APB2FF_CSR_BASE + 0x454) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_20_REG (CSR_APB2FF_CSR_BASE + 0x458) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_21_REG (CSR_APB2FF_CSR_BASE + 0x45C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_22_REG (CSR_APB2FF_CSR_BASE + 0x460) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_23_REG (CSR_APB2FF_CSR_BASE + 0x464) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_24_REG (CSR_APB2FF_CSR_BASE + 0x468) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_25_REG (CSR_APB2FF_CSR_BASE + 0x46C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_26_REG (CSR_APB2FF_CSR_BASE + 0x470) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_27_REG (CSR_APB2FF_CSR_BASE + 0x474) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_28_REG (CSR_APB2FF_CSR_BASE + 0x478) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_29_REG (CSR_APB2FF_CSR_BASE + 0x47C) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_30_REG (CSR_APB2FF_CSR_BASE + 0x480) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_INDIR_DATA_31_REG (CSR_APB2FF_CSR_BASE + 0x484) /* MAG的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_MAG_VERSION_REG (CSR_APB2FF_CSR_BASE + 0x488) /* APB2FF模块MAG预留ECO寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_CTRL_REG (CSR_APB2FF_CSR_BASE + 0x700) /* NGPCS的间接寻址控制寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_TIMEOUT_REG \ + (CSR_APB2FF_CSR_BASE + 0x704) /* NGPCS的间接寻址最大允许时间寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_0_REG (CSR_APB2FF_CSR_BASE + 0x708) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_1_REG (CSR_APB2FF_CSR_BASE + 0x70C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_2_REG (CSR_APB2FF_CSR_BASE + 0x710) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_3_REG (CSR_APB2FF_CSR_BASE + 0x714) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_4_REG (CSR_APB2FF_CSR_BASE + 0x718) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_5_REG (CSR_APB2FF_CSR_BASE + 0x71C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_6_REG (CSR_APB2FF_CSR_BASE + 0x720) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_7_REG (CSR_APB2FF_CSR_BASE + 0x724) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_8_REG (CSR_APB2FF_CSR_BASE + 0x728) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_9_REG (CSR_APB2FF_CSR_BASE + 0x72C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_10_REG (CSR_APB2FF_CSR_BASE + 0x730) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_11_REG (CSR_APB2FF_CSR_BASE + 0x734) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_12_REG (CSR_APB2FF_CSR_BASE + 0x738) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_13_REG (CSR_APB2FF_CSR_BASE + 0x73C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_14_REG (CSR_APB2FF_CSR_BASE + 0x740) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_15_REG (CSR_APB2FF_CSR_BASE + 0x744) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_16_REG (CSR_APB2FF_CSR_BASE + 0x748) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_17_REG (CSR_APB2FF_CSR_BASE + 0x74C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_18_REG (CSR_APB2FF_CSR_BASE + 0x750) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_19_REG (CSR_APB2FF_CSR_BASE + 0x754) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_20_REG (CSR_APB2FF_CSR_BASE + 0x758) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_21_REG (CSR_APB2FF_CSR_BASE + 0x75C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_22_REG (CSR_APB2FF_CSR_BASE + 0x760) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_23_REG (CSR_APB2FF_CSR_BASE + 0x764) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_24_REG (CSR_APB2FF_CSR_BASE + 0x768) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_25_REG (CSR_APB2FF_CSR_BASE + 0x76C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_26_REG (CSR_APB2FF_CSR_BASE + 0x770) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_27_REG (CSR_APB2FF_CSR_BASE + 0x774) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_28_REG (CSR_APB2FF_CSR_BASE + 0x778) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_29_REG (CSR_APB2FF_CSR_BASE + 0x77C) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_30_REG (CSR_APB2FF_CSR_BASE + 0x780) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_INDIR_DATA_31_REG (CSR_APB2FF_CSR_BASE + 0x784) /* NGPCS的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_NGPCS_VERSION_REG (CSR_APB2FF_CSR_BASE + 0x788) /* APB2FF模块NGPCS预留ECO寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_ANTRING_INDIR_CTRL_REG (CSR_APB2FF_CSR_BASE + 0xA00) /* ANTRING的间接寻址控制寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_ANTRING_INDIR_TIMEOUT_REG \ + (CSR_APB2FF_CSR_BASE + 0xA04) /* ANTRING的间接寻址最大允许时间寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_ANTRING_INDIR_DATA_REG (CSR_APB2FF_CSR_BASE + 0xA08) /* ANTRING的间接寻址数据寄存器 */ +#define CSR_APB2FF_CSR_APB2FF_ANTRING_VERSION_REG (CSR_APB2FF_CSR_BASE + 0xA0C) /* APB2FF模块ANTRING预留ECO寄存器 */ + +#endif // MPU_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/hva_peh_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/hva_peh_c_union_define.h new file mode 100644 index 000000000..0ea273948 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/hva_peh_c_union_define.h @@ -0,0 +1,3236 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : hva_peh_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2021/04/08 19:34:52 Create file +// ****************************************************************************** + +#ifndef HVA_PEH_C_UNION_DEFINE_H +#define HVA_PEH_C_UNION_DEFINE_H + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_vendor_id : 16; /* [15:0] */ + u32 hdr_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_io_space_en : 1; /* [0] */ + u32 hdr_mem_space_en : 1; /* [1] */ + u32 hdr_bus_master_en : 1; /* [2] */ + u32 hdr_special_cycle_en : 1; /* [3] */ + u32 hdr_mem_wr_invld_en : 1; /* [4] */ + u32 hdr_vga_snoop_en : 1; /* [5] */ + u32 hdr_parity_err_resp : 1; /* [6] */ + u32 hdr_idsel_stepping : 1; /* [7] */ + u32 hdr_serr_en : 1; /* [8] */ + u32 hdr_fast_b2b_en : 1; /* [9] */ + u32 hdr_intx_disable : 1; /* [10] */ + u32 hdr_rved : 8; /* [18:11] */ + u32 hdr_intx_status : 1; /* [19] */ + u32 hdr_cap_list : 1; /* [20] */ + u32 hdr_66mhz_cap : 1; /* [21] */ + u32 hdr_0reserved : 1; /* [22] */ + u32 hdr_fastb2b_cap : 1; /* [23] */ + u32 hdr_mdata_par_err : 1; /* [24] */ + u32 hdr_devsel_timing : 2; /* [26:25] */ + u32 hdr_sig_target_abort : 1; /* [27] */ + u32 hdr_rx_target_abort : 1; /* [28] */ + u32 hdr_rx_master_abort : 1; /* [29] */ + u32 hdr_rx_sys_err : 1; /* [30] */ + u32 hdr_deteted_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_revision_id : 8; /* [7:0] */ + u32 hdr_program_inf : 8; /* [15:8] */ + u32 hdr_sub_class_code : 8; /* [23:16] */ + u32 hdr_base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_cachlie_size : 8; /* [7:0] */ + u32 hdr_latency_timer : 8; /* [15:8] */ + u32 hdr_header_type : 7; /* [22:16] */ + u32 hdr_multfunc_dev : 1; /* [23] */ + u32 hdr_bist_result : 4; /* [27:24] */ + u32 hdr_1reserved : 2; /* [29:28] */ + u32 hdr_start_bist : 1; /* [30] */ + u32 hdr_bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_bar0_type : 1; /* [0] */ + u32 hdr_bar0_reserved : 1; /* [1] */ + u32 hdr_bar0_width : 1; /* [2] */ + u32 hdr_bar0_prefetch_en : 1; /* [3] */ + u32 hdr_2reserved : 9; /* [12:4] */ + u32 hdr_bar0_addr : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_bar1_type : 1; /* [0] */ + u32 hdr_bar1_reserved : 1; /* [1] */ + u32 hdr_bar1_width : 1; /* [2] */ + u32 hdr_bar1_prefetch_en : 1; /* [3] */ + u32 hdr_bar1_2reserved : 19; /* [22:4] */ + u32 hdr_bar1_addr : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_bar2_type : 1; /* [0] */ + u32 hdr_bar2_reserved : 1; /* [1] */ + u32 hdr_bar2_width : 1; /* [2] */ + u32 hdr_bar2_prefetch_en : 1; /* [3] */ + u32 hdr_bar2_2reserved : 13; /* [16:4] */ + u32 hdr_bar2_addr : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_bar3_type : 1; /* [0] */ + u32 hdr_bar3_reserved : 1; /* [1] */ + u32 hdr_bar3_width : 1; /* [2] */ + u32 hdr_bar3_prefetch_en : 1; /* [3] */ + u32 hdr_bar3_2reserved : 14; /* [17:4] */ + u32 hdr_bar3_addr : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_bar4_type : 1; /* [0] */ + u32 hdr_bar4_reserved : 1; /* [1] */ + u32 hdr_bar4_width : 1; /* [2] */ + u32 hdr_bar4_prefetch_en : 1; /* [3] */ + u32 hdr_bar4_2reserved : 18; /* [21:4] */ + u32 hdr_bar4_addr : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_sys_vendor_id : 16; /* [15:0] */ + u32 hdr_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprwm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_ext_rom_enable : 1; /* [0] */ + u32 hdr_6reserved : 10; /* [10:1] */ + u32 hdr_ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_exprwm_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_cap_ptr : 8; /* [7:0] */ + u32 hdr_7reserved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_8reserved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hdr_int_line : 8; /* [7:0] */ + u32 hdr_int_pin : 8; /* [15:8] */ + u32 hdr_3creserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcihdr_int_u; + +/* Define the union csr_pcie_capability_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_pci_capid : 8; /* [7:0] */ + u32 pcap_nxt_ptr : 8; /* [15:8] */ + u32 pcap_pci_cap_ver : 4; /* [19:16] */ + u32 pcap_port_type : 4; /* [23:20] */ + u32 pcap_slot_implement : 1; /* [24] */ + u32 pcap_int_msg_num : 5; /* [29:25] */ + u32 pcap_15reserved : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_capability_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_max_payload_size_support : 3; /* [2:0] */ + u32 pcap_phanotom_fun_sup : 2; /* [4:3] */ + u32 pcap_ext_tag_sup : 1; /* [5] */ + u32 pcap_ep_l0s_accept_lat : 3; /* [8:6] */ + u32 pcap_ep_l1_accept_lat : 3; /* [11:9] */ + u32 pcap_undefine_04 : 3; /* [14:12] */ + u32 pcap_ro_base_err_rpt : 1; /* [15] */ + u32 pcap_0reserved : 2; /* [17:16] */ + u32 pcap_cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 pcap_cap_slot_pwr_sca : 2; /* [27:26] */ + u32 pcap_flr_cap : 1; /* [28] */ + u32 pcap_16reserved : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_cor_err_rpt_en : 1; /* [0] */ + u32 pcap_non_fat_rpt_en : 1; /* [1] */ + u32 pcap_fat_err_rpt_en : 1; /* [2] */ + u32 pcap_ur_rpt_en : 1; /* [3] */ + u32 pcap_relax_order_en : 1; /* [4] */ + u32 pcap_max_payload_size : 3; /* [7:5] */ + u32 pcap_extend_tag_en : 1; /* [8] */ + u32 pcap_phatom_func_en : 1; /* [9] */ + u32 pcap_aux_pwr_pm_en : 1; /* [10] */ + u32 pcap_no_snoop_en : 1; /* [11] */ + u32 pcap_max_read_req_size : 3; /* [14:12] */ + u32 pcap_init_flr_reset_rwwo : 1; /* [15] */ + u32 pcap_cor_err_detect : 1; /* [16] */ + u32 pcap_non_fata_detect : 1; /* [17] */ + u32 pcap_fat_err_detect : 1; /* [18] */ + u32 pcap_ur_detect : 1; /* [19] */ + u32 pcap_aux_pwr_detect : 1; /* [20] */ + u32 pcap_tlp_pending : 1; /* [21] */ + u32 pcap_1reserved : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_max_link_speed : 4; /* [3:0] */ + u32 pcap_max_link_width : 6; /* [9:4] */ + u32 pcap_aspm_sup : 2; /* [11:10] */ + u32 pcap_l0_exit_lat : 3; /* [14:12] */ + u32 pcap_l1_exit_lat : 3; /* [17:15] */ + u32 pcap_clock_pm : 1; /* [18] */ + u32 pcap_surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 pcap_dl_link_act_rpt_cap : 1; /* [20] */ + u32 pcap_link_band_notice_cap : 1; /* [21] */ + u32 pcap_aspm_opt_compliance : 1; /* [22] */ + u32 pcap_1reserved : 1; /* [23] */ + u32 pcap_port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_aspm_ctrl : 2; /* [1:0] */ + u32 pcap_4reserved : 1; /* [2] */ + u32 pcap_rcb : 1; /* [3] */ + u32 pcap_link_disable : 1; /* [4] */ + u32 pcap_retrain_link : 1; /* [5] */ + u32 pcap_common_clk_cfg : 1; /* [6] */ + u32 pcap_extended_sync : 1; /* [7] */ + u32 pcap_clock_pm_en : 1; /* [8] */ + u32 pcap_hw_auto_width_dis : 1; /* [9] */ + u32 pcap_link_band_int_en : 1; /* [10] */ + u32 pcap_link_auto_band_int_en : 1; /* [11] */ + u32 pcap_3reserved : 4; /* [15:12] */ + u32 pcap_mac_cur_link_spped : 4; /* [19:16] */ + u32 pcap_mac_cur_link_width : 6; /* [25:20] */ + u32 pcap_undefined_12 : 1; /* [26] */ + u32 pcap_link_training : 1; /* [27] */ + u32 pcap_slot_clk_cfg : 1; /* [28] */ + u32 pcap_dl_cfg_link_active : 1; /* [29] */ + u32 pcap_link_band_status : 1; /* [30] */ + u32 pcap_link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_att_button_pre : 1; /* [0] */ + u32 pcap_pwr_ctrl_pre : 1; /* [1] */ + u32 pcap_msl_sensor_pre : 1; /* [2] */ + u32 pcap_att_indecator_pre : 1; /* [3] */ + u32 pcap_pwr_indicator_pre : 1; /* [4] */ + u32 pcap_hot_plug_surprise : 1; /* [5] */ + u32 pcap_hot_plug_cap : 1; /* [6] */ + u32 pcap_slot_pwr_limit_val : 8; /* [14:7] */ + u32 pcap_slot_pwr_limit_scale : 2; /* [16:15] */ + u32 pcap_elec_interlock_pre : 1; /* [17] */ + u32 pcap_no_comman_cpled_sup : 1; /* [18] */ + u32 pcap_physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_att_buttom_pre_en : 1; /* [0] */ + u32 pcap_pwr_fault_det_en : 1; /* [1] */ + u32 pcap_mrl_sensor_change_en : 1; /* [2] */ + u32 pcap_presence_det_change_en : 1; /* [3] */ + u32 pcap_command_cpled_int_en : 1; /* [4] */ + u32 pcap_hot_plug_int_en : 1; /* [5] */ + u32 pcap_att_indicator_ctrl : 2; /* [7:6] */ + u32 pcap_pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pcap_pwr_ctrled_ctrl : 1; /* [10] */ + u32 pcap_elec_interlock_ctrl : 1; /* [11] */ + u32 pcap_dl_state_change_en : 1; /* [12] */ + u32 pcap_6reserved : 3; /* [15:13] */ + u32 pcap_attention_button : 1; /* [16] */ + u32 pcap_pwr_fault_det : 1; /* [17] */ + u32 pcap_mrl_sensor_change : 1; /* [18] */ + u32 pcap_presencd_det_change : 1; /* [19] */ + u32 pcap_command_cpled : 1; /* [20] */ + u32 pcap_mrl_sensor_st : 1; /* [21] */ + u32 pcap_presencd_det_st : 1; /* [22] */ + u32 pcap_elec_interlock_st : 1; /* [23] */ + u32 pcap_dl_state_change : 1; /* [24] */ + u32 pcap_5reserved : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_7reserved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_pme_rid : 16; /* [15:0] */ + u32 pcap_pme_status : 1; /* [16] */ + u32 pcap_pme_pending : 1; /* [17] */ + u32 pcap_8reserved : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_cpl_timeout_range : 4; /* [3:0] */ + u32 pcap_cpl_timeout_disable_sup : 1; /* [4] */ + u32 pcap_ari_fwd_sup : 1; /* [5] */ + u32 pcap_atomicop_route_sup : 1; /* [6] */ + u32 pcap_atomic_32bit_cpl_sup : 1; /* [7] */ + u32 pcap_atomic_64bit_cpl_sup : 1; /* [8] */ + u32 pcap_cas_128bit_cpl_sup : 1; /* [9] */ + u32 pcap_no_roen_prpr_pass : 1; /* [10] */ + u32 pcap_ltr_mech_sup : 1; /* [11] */ + u32 pcap_tph_cpl_sup : 2; /* [13:12] */ + u32 pcap_ln_sys_cls : 2; /* [15:14] */ + u32 pcap_sup_10bit_cpl_tag : 1; /* [16] */ + u32 pcap_sup_10bit_req_tag : 1; /* [17] */ + u32 pcap_obff_sup : 2; /* [19:18] */ + u32 pcap_ext_fmt_sup : 1; /* [20] */ + u32 pcap_end_end_pfx_sup : 1; /* [21] */ + u32 pcap_max_end_end_pfx : 2; /* [23:22] */ + u32 pcap_9reserved : 7; /* [30:24] */ + u32 pcap_frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_cpl_timeout_value : 4; /* [3:0] */ + u32 pcap_cpl_timeout_dis : 1; /* [4] */ + u32 pcap_ari_fwd_en : 1; /* [5] */ + u32 pcap_atomicop_req_en : 1; /* [6] */ + u32 pcap_atomicop_egress_blk : 1; /* [7] */ + u32 pcap_ido_req_en : 1; /* [8] */ + u32 pcap_ido_cpl_en : 1; /* [9] */ + u32 pcap_ltr_mech_en : 1; /* [10] */ + u32 pcap_en_10bit_req_tag : 1; /* [11] */ + u32 pcap_11reserved : 1; /* [12] */ + u32 pcap_obff_en : 2; /* [14:13] */ + u32 pcap_end_end_pfx_blk : 1; /* [15] */ + u32 pcap_10reserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_13reserved : 1; /* [0] */ + u32 pcap_link_speed_sup : 7; /* [7:1] */ + u32 pcap_cross_link_sup : 1; /* [8] */ + u32 pcap_cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 pcap_cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 pcap_retimer_presence_detect : 1; /* [23] */ + u32 pcap_retimer2_presence_detect : 1; /* [24] */ + u32 pcap_12reserved : 6; /* [30:25] */ + u32 pcap_drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_target_link_speed : 4; /* [3:0] */ + u32 pcap_enter_compliance : 1; /* [4] */ + u32 pcap_hw_auto_speed_dis : 1; /* [5] */ + u32 pcap_selectable_de_emphasis : 1; /* [6] */ + u32 pcap_transmit_margin : 3; /* [9:7] */ + u32 pcap_enter_mod_compliance : 1; /* [10] */ + u32 pcap_compliance_sos : 1; /* [11] */ + u32 pcap_compliance_preset_deemp : 4; /* [15:12] */ + u32 pcap_cur_deemp_level : 1; /* [16] */ + u32 pcap_eq_8g_complete : 1; /* [17] */ + u32 pcap_eq_8g_phase1_success : 1; /* [18] */ + u32 pcap_eq_8g_phase2_success : 1; /* [19] */ + u32 pcap_eq_8g_phase3_success : 1; /* [20] */ + u32 pcap_link_8g_eq_req : 1; /* [21] */ + u32 pcap_retimer_presence_detect : 1; /* [22] */ + u32 pcap_retimer2_presence_detect : 1; /* [23] */ + u32 pcap_14reserved : 4; /* [27:24] */ + u32 pcap_dwstm_component_presence : 1; /* [28] */ + u32 pcap_drs_msg_recved : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcap_slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msicap_capability_id : 8; /* [7:0] */ + u32 msicap_nxt_ptr : 8; /* [15:8] */ + u32 msicap_enable : 1; /* [16] */ + u32 msicap_mmc : 3; /* [19:17] */ + u32 msicap_mme : 3; /* [22:20] */ + u32 msicap_c64 : 1; /* [23] */ + u32 msicap_pvm : 1; /* [24] */ + u32 msicap_support : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_cap_header_u; + +/* Define the union csr_msi_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msicap_0reserved : 2; /* [1:0] */ + u32 msicap_addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_addr_u; + +/* Define the union csr_msi_up_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msicap_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_up_addr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msicap_data : 16; /* [15:0] */ + u32 msicap_1reserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msicap_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msicap_pend : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msixcap_capability_id : 8; /* [7:0] */ + u32 msixcap_nxt_ptr : 8; /* [15:8] */ + u32 msixcap_table_size : 11; /* [26:16] */ + u32 msixcap_0reserved : 3; /* [29:27] */ + u32 msixcap_func_mask : 1; /* [30] */ + u32 msixcap_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_cap_header_u; + +/* Define the union csr_msix_table_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msixcap_table_bir : 3; /* [2:0] */ + u32 msixcap_table_ofset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_table_u; + +/* Define the union csr_msix_pba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msixcap_pba_bir : 3; /* [2:0] */ + u32 msixcap_pba_ofset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_pba_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmcap_capability_id : 8; /* [7:0] */ + u32 pmcap_nxt_ptr : 8; /* [15:8] */ + u32 pmcap_version : 3; /* [18:16] */ + u32 pmcap_clk : 1; /* [19] */ + u32 pmcap_0reserved : 1; /* [20] */ + u32 pmcap_device_spec_ini : 1; /* [21] */ + u32 pmcap_aux_current : 3; /* [24:22] */ + u32 pmcap_d1_support : 1; /* [25] */ + u32 pmcap_d2_support : 1; /* [26] */ + u32 pmcap_pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pme_cap_header_u; + +/* Define the union csr_pme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmcap_pwr_state : 2; /* [1:0] */ + u32 pmcap_3reserved : 1; /* [2] */ + u32 pmcap_no_soft_reset : 1; /* [3] */ + u32 pmcap_2reserved : 4; /* [7:4] */ + u32 pmcap_pme_en : 1; /* [8] */ + u32 pmcap_data_sel : 4; /* [12:9] */ + u32 pmcap_data_scale : 2; /* [14:13] */ + u32 pmcap_pme_status : 1; /* [15] */ + u32 pmcap_1reserved : 6; /* [21:16] */ + u32 pmcap_b2_b3_n : 1; /* [22] */ + u32 pmcap_bpcc_en : 1; /* [23] */ + u32 pmcap_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pme_ctrl_status_u; + +/* Define the union csr_acs_extended_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acscap_id : 16; /* [15:0] */ + u32 acscap_version : 4; /* [19:16] */ + u32 acscap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_acs_extended_cap_header_u; + +/* Define the union csr_acs_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acscap_sv : 1; /* [0] */ + u32 acscap_tb : 1; /* [1] */ + u32 acscap_prr : 1; /* [2] */ + u32 acscap_pcr : 1; /* [3] */ + u32 acscap_uf : 1; /* [4] */ + u32 acscap_pec : 1; /* [5] */ + u32 acscap_dtp : 1; /* [6] */ + u32 acscap_1reserved : 1; /* [7] */ + u32 acscap_ecvs : 8; /* [15:8] */ + u32 acscap_sv_en : 1; /* [16] */ + u32 acscap_tb_en : 1; /* [17] */ + u32 acscap_prr_en : 1; /* [18] */ + u32 acscap_pcr_en : 1; /* [19] */ + u32 acscap_uf_en : 1; /* [20] */ + u32 acscap_pec_en : 1; /* [21] */ + u32 acscap_dtp_en : 1; /* [22] */ + u32 acscap_0reserved : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_acs_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_id : 16; /* [15:0] */ + u32 sriovcap_version : 4; /* [19:16] */ + u32 sriovcap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_vf_mig_cap : 1; /* [0] */ + u32 sriovcap_ari_cap_hier_pres : 1; /* [1] */ + u32 sriovcap_0reserved : 19; /* [20:2] */ + u32 sriovcap_vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_vf_en : 1; /* [0] */ + u32 sriovcap_vf_mig_en : 1; /* [1] */ + u32 sriovcap_vf_mig_int_en : 1; /* [2] */ + u32 sriovcap_vf_mse : 1; /* [3] */ + u32 sriovcap_ari_cap_hier : 1; /* [4] */ + u32 sriovcap_2reserved : 11; /* [15:5] */ + u32 sriovcap_vf_mig_status : 1; /* [16] */ + u32 sriovcap_1reserved : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_initial_vf : 16; /* [15:0] */ + u32 sriovcap_totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_num_of_vf : 16; /* [15:0] */ + u32 sriovcap_func_depen_link : 8; /* [23:16] */ + u32 sriovcap_3reserved : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_vf_offset : 16; /* [15:0] */ + u32 sriovcap_vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_4reserved : 16; /* [15:0] */ + u32 sriovcap_vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_5reserved : 2; /* [1:0] */ + u32 sriovcap_vf_bar0_width : 1; /* [2] */ + u32 sriovcap_vf_bar0_prefetch_en : 1; /* [3] */ + u32 sriovcap_resvd : 12; /* [15:4] */ + u32 sriovcap_vf_bar0_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_vf_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_7reserved : 2; /* [1:0] */ + u32 sriovcap_vf_bar2_width : 1; /* [2] */ + u32 sriovcap_vf_bar2_prefetch_en : 1; /* [3] */ + u32 sriovcap_resv : 16; /* [19:4] */ + u32 sriovcap_vf_bar2_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_vf_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_9reserved : 2; /* [1:0] */ + u32 sriovcap_vf_bar4_width : 1; /* [2] */ + u32 sriovcap_vf_bar4_prefetch_en : 1; /* [3] */ + u32 sriovcap_vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_10reserved : 3; /* [2:0] */ + u32 sriovcap_vf_bar5_prefetch_en : 1; /* [3] */ + u32 sriovcap_vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcap_vf_mig_state_bir : 3; /* [2:0] */ + u32 sriovcap_vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_mig_state_array_u; + +/* Define the union csr_tph_extended_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tphcap_id : 16; /* [15:0] */ + u32 tphcap_version : 4; /* [19:16] */ + u32 tphcap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tph_extended_cap_header_u; + +/* Define the union csr_tph_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tphcap_nsms : 1; /* [0] */ + u32 tphcap_ivms : 1; /* [1] */ + u32 tphcap_sdms : 1; /* [2] */ + u32 tphcap_resvdp0 : 5; /* [7:3] */ + u32 tphcap_etrs : 1; /* [8] */ + u32 tphcap_stl : 2; /* [10:9] */ + u32 tphcap_resvdp1 : 5; /* [15:11] */ + u32 tphcap_st_tbl_size : 11; /* [26:16] */ + u32 tphcap_resvdp2 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tph_ctrl_u; + +/* Define the union csr_tph_egress_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tphcap_sms : 3; /* [2:0] */ + u32 tphcap_resvdp3 : 5; /* [7:3] */ + u32 tphcap_tre : 1; /* [8] */ + u32 tphcap_resvdp4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tph_egress_ctrl0_u; + +/* Define the union csr_pasid_extended_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasidcap_id : 16; /* [15:0] */ + u32 pasidcap_version : 4; /* [19:16] */ + u32 pasidcap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pasid_extended_cap_header_u; + +/* Define the union csr_pasid_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasidcap_resvp0 : 1; /* [0] */ + u32 pasidcap_eps : 1; /* [1] */ + u32 pasidcap_pms : 1; /* [2] */ + u32 pasidcap_resvp1 : 5; /* [7:3] */ + u32 pasidcap_mpw : 5; /* [12:8] */ + u32 pasidcap_resvp2 : 3; /* [15:13] */ + u32 pasidcap_pasid_en : 1; /* [16] */ + u32 pasidcap_epe : 1; /* [17] */ + u32 pasidcap_pme : 1; /* [18] */ + u32 pasidcap_resvp3 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pasid_ctrl_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_id : 16; /* [15:0] */ + u32 aercap_version : 4; /* [19:16] */ + u32 aercap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_undefined_4 : 1; /* [0] */ + u32 aercap_2reserved : 3; /* [3:1] */ + u32 aercap_dl_protocal_err_st : 1; /* [4] */ + u32 aercap_sur_down_err_st : 1; /* [5] */ + u32 aercap_1reserved : 6; /* [11:6] */ + u32 aercap_poisoned_tlp_st : 1; /* [12] */ + u32 aercap_fc_protocol_err_st : 1; /* [13] */ + u32 aercap_cpl_timeeout_st : 1; /* [14] */ + u32 aercap_cpl_abort_st : 1; /* [15] */ + u32 aercap_unexp_cpl_st : 1; /* [16] */ + u32 aercap_rcv_overflow_st : 1; /* [17] */ + u32 aercap_mal_tlp_st : 1; /* [18] */ + u32 aercap_ecrc_err_st : 1; /* [19] */ + u32 aercap_ur_err_st : 1; /* [20] */ + u32 aercap_acs_vio_st : 1; /* [21] */ + u32 aercap_ue_internal_st : 1; /* [22] */ + u32 aercap_mc_blk_st : 1; /* [23] */ + u32 aercap_atomicop_eg_blk_st : 1; /* [24] */ + u32 aercap_tlp_pfx_blk_err_st : 1; /* [25] */ + u32 aercap_0reserved : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_undefined_8 : 1; /* [0] */ + u32 aercap_5reserved : 3; /* [3:1] */ + u32 aercap_dl_protocal_err_mask : 1; /* [4] */ + u32 aercap_sur_down_err_mask : 1; /* [5] */ + u32 aercap_4reserved : 6; /* [11:6] */ + u32 aercap_poisoned_tlp_mask : 1; /* [12] */ + u32 aercap_fc_protocol_err_mask : 1; /* [13] */ + u32 aercap_cpl_timeeout_mask : 1; /* [14] */ + u32 aercap_cpl_abort_mask : 1; /* [15] */ + u32 aercap_unexp_cpl_mask : 1; /* [16] */ + u32 aercap_rcv_overflow_mask : 1; /* [17] */ + u32 aercap_mal_tlp_mask : 1; /* [18] */ + u32 aercap_ecrc_err_mask : 1; /* [19] */ + u32 aercap_ur_err_mask : 1; /* [20] */ + u32 aercap_acs_vio_mask : 1; /* [21] */ + u32 aercap_uncor_int_err_mask : 1; /* [22] */ + u32 aercap_mc_blk_mask : 1; /* [23] */ + u32 aercap_atomicop_eg_blk_mask : 1; /* [24] */ + u32 aercap_tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 aercap_3reserved : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_undefined_c : 1; /* [0] */ + u32 aercap_8reserved : 3; /* [3:1] */ + u32 aercap_dl_protocal_err_ser : 1; /* [4] */ + u32 aercap_sur_down_err_ser : 1; /* [5] */ + u32 aercap_7reserved : 6; /* [11:6] */ + u32 aercap_poisoned_tlp_ser : 1; /* [12] */ + u32 aercap_fc_protocol_err_ser : 1; /* [13] */ + u32 aercap_cpl_timeeout_ser : 1; /* [14] */ + u32 aercap_cpl_abort_ser : 1; /* [15] */ + u32 aercap_unexp_cpl_ser : 1; /* [16] */ + u32 aercap_rcv_overflow_ser : 1; /* [17] */ + u32 aercap_mal_tlp_ser : 1; /* [18] */ + u32 aercap_ecrc_err_ser : 1; /* [19] */ + u32 aercap_ur_err_ser : 1; /* [20] */ + u32 aercap_acs_vio_ser : 1; /* [21] */ + u32 aercap_uncor_int_err_ser : 1; /* [22] */ + u32 aercap_mc_blk_ser : 1; /* [23] */ + u32 aercap_atomicop_eg_blk_ser : 1; /* [24] */ + u32 aercap_tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 aercap_6reserved : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_rx_err_st : 1; /* [0] */ + u32 aercap_11reserved : 5; /* [5:1] */ + u32 aercap_bad_tlp_st : 1; /* [6] */ + u32 aercap_bad_dllp_st : 1; /* [7] */ + u32 aercap_reply_num_rollover_st : 1; /* [8] */ + u32 aercap_10reserved : 3; /* [11:9] */ + u32 aercap_reply_timer_timout_st : 1; /* [12] */ + u32 aercap_adv_non_fatal_err_st : 1; /* [13] */ + u32 aercap_cor_int_err_st : 1; /* [14] */ + u32 aercap_header_log_overflow_st : 1; /* [15] */ + u32 aercap_9reserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_rx_err_mask : 1; /* [0] */ + u32 aercap_14reserved : 5; /* [5:1] */ + u32 aercap_bad_tlp_mask : 1; /* [6] */ + u32 aercap_bad_dllp_mask : 1; /* [7] */ + u32 aercap_reply_num_rollover_mask : 1; /* [8] */ + u32 aercap_13reserved : 3; /* [11:9] */ + u32 aercap_reply_timer_timout_mask : 1; /* [12] */ + u32 aercap_adv_non_fatal_err_mask : 1; /* [13] */ + u32 aercap_cor_int_err_mask : 1; /* [14] */ + u32 aercap_header_log_overflow_mask : 1; /* [15] */ + u32 aercap_12reserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_first_err_ptr : 5; /* [4:0] */ + u32 aercap_ecrc_gen_cap : 1; /* [5] */ + u32 aercap_ecrc_gen_en : 1; /* [6] */ + u32 aercap_ecrc_check_cap : 1; /* [7] */ + u32 aercap_ecrc_check_en : 1; /* [8] */ + u32 aercap_multi_hdr_rec_cap : 1; /* [9] */ + u32 aercap_multi_hdr_rec_enable : 1; /* [10] */ + u32 aercap_tlp_prefix_lor_pre : 1; /* [11] */ + u32 aercap_15reserved : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_four_header_log_u; + +/* Define the union csr_rwot_errwr_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_cor_err_en : 1; /* [0] */ + u32 aercap_non_fatal_err_en : 1; /* [1] */ + u32 aercap_fatal_err_en : 1; /* [2] */ + u32 aercap_16reserved : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rwot_errwr_command_u; + +/* Define the union csr_rwot_errwr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_core_err_rcv : 1; /* [0] */ + u32 aercap_multi_cor_err_rcv : 1; /* [1] */ + u32 aercap_uncor_err_rcv : 1; /* [2] */ + u32 aercap_multi_uncor_err_rcv : 1; /* [3] */ + u32 aercap_first_uncor_err : 1; /* [4] */ + u32 aercap_non_fatal_msg_rcv : 1; /* [5] */ + u32 aercap_fatal_msg_rcv : 1; /* [6] */ + u32 aercap_17reserved : 20; /* [26:7] */ + u32 aercap_aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rwot_errwr_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_err_cor_source : 16; /* [15:0] */ + u32 aercap_err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercap_four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricap_id : 16; /* [15:0] */ + u32 aricap_version : 4; /* [19:16] */ + u32 aricap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricap_mfvc_func_grp_cap : 1; /* [0] */ + u32 aricap_acs_func_grp_cap : 1; /* [1] */ + u32 aricap_2reserved : 6; /* [7:2] */ + u32 aricap_nxt_func_num : 8; /* [15:8] */ + u32 aricap_mfvc_func_grp_en : 1; /* [16] */ + u32 aricap_acs_func_grp_en : 1; /* [17] */ + u32 aricap_1reserved : 2; /* [19:18] */ + u32 aricap_func_group : 3; /* [22:20] */ + u32 aricap_0reserved : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ari_ctrl_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_pcihdr_id_u pcihdr_id; /* 0 */ + volatile csr_pcihdr_cmdsts_u pcihdr_cmdsts; /* 4 */ + volatile csr_pcihdr_clsrev_u pcihdr_clsrev; /* 8 */ + volatile csr_pcihdr_misc_u pcihdr_misc; /* C */ + volatile csr_pcihdr_bar0_u pcihdr_bar0; /* 10 */ + volatile csr_pcihdr_bar1_u pcihdr_bar1; /* 14 */ + volatile csr_pcihdr_bar2_u pcihdr_bar2; /* 18 */ + volatile csr_pcihdr_bar3_u pcihdr_bar3; /* 1C */ + volatile csr_pcihdr_bar4_u pcihdr_bar4; /* 20 */ + volatile csr_pcihdr_bar5_u pcihdr_bar5; /* 24 */ + volatile csr_pcihdr_cbus_ptr_u pcihdr_cbus_ptr; /* 28 */ + volatile csr_pcihdr_subsys_u pcihdr_subsys; /* 2C */ + volatile csr_pcihdr_exprwm_u pcihdr_exprwm; /* 30 */ + volatile csr_pcihdr_capptr_u pcihdr_capptr; /* 34 */ + volatile csr_pci_rsvd_u pci_rsvd; /* 38 */ + volatile csr_pcihdr_int_u pcihdr_int; /* 3C */ + volatile csr_pcie_capability_header_u pcie_capability_header; /* 40 */ + volatile csr_device_capbility_u device_capbility; /* 44 */ + volatile csr_device_ctrl_status_u device_ctrl_status; /* 48 */ + volatile csr_link_capbility_u link_capbility; /* 4C */ + volatile csr_link_ctrl_status_u link_ctrl_status; /* 50 */ + volatile csr_slot_capability_u slot_capability; /* 54 */ + volatile csr_slot_ctrl_status_u slot_ctrl_status; /* 58 */ + volatile csr_root_ctrl_status_u root_ctrl_status; /* 5C */ + volatile csr_root_status_u root_status; /* 60 */ + volatile csr_device_capability2_u device_capability2; /* 64 */ + volatile csr_device_ctrl2_u device_ctrl2; /* 68 */ + volatile csr_link_capability2_u link_capability2; /* 6C */ + volatile csr_link_ctrl_status2_u link_ctrl_status2; /* 70 */ + volatile csr_slot_cap_2_u slot_cap_2; /* 74 */ + volatile csr_slot_ctrl_2_u slot_ctrl_2; /* 78 */ + volatile csr_msi_cap_header_u msi_cap_header; /* 80 */ + volatile csr_msi_addr_u msi_addr; /* 84 */ + volatile csr_msi_up_addr_u msi_up_addr; /* 88 */ + volatile csr_msi_data_u msi_data; /* 8C */ + volatile csr_msi_mask_u msi_mask; /* 90 */ + volatile csr_msi_pending_u msi_pending; /* 94 */ + volatile csr_msix_cap_header_u msix_cap_header; /* A0 */ + volatile csr_msix_table_u msix_table; /* A4 */ + volatile csr_msix_pba_u msix_pba; /* A8 */ + volatile csr_pme_cap_header_u pme_cap_header; /* B0 */ + volatile csr_pme_ctrl_status_u pme_ctrl_status; /* B4 */ + volatile csr_acs_extended_cap_header_u acs_extended_cap_header; /* 100 */ + volatile csr_acs_ctrl_u acs_ctrl; /* 104 */ + volatile csr_sriov_cap_header_u sriov_cap_header; /* 200 */ + volatile csr_sriov_cap_u sriov_cap; /* 204 */ + volatile csr_sriov_ctrl_u sriov_ctrl; /* 208 */ + volatile csr_init_vf_number_u init_vf_number; /* 20C */ + volatile csr_func_dep_vf_num_u func_dep_vf_num; /* 210 */ + volatile csr_vf_rid_setting_u vf_rid_setting; /* 214 */ + volatile csr_vf_device_id_u vf_device_id; /* 218 */ + volatile csr_vf_page_size_u vf_page_size; /* 21C */ + volatile csr_system_page_size_u system_page_size; /* 220 */ + volatile csr_vf_bar0_u vf_bar0; /* 224 */ + volatile csr_vf_bar1_u vf_bar1; /* 228 */ + volatile csr_vf_bar2_u vf_bar2; /* 22C */ + volatile csr_vf_bar3_u vf_bar3; /* 230 */ + volatile csr_vf_bar4_u vf_bar4; /* 234 */ + volatile csr_vf_bar5_u vf_bar5; /* 238 */ + volatile csr_vf_mig_state_array_u vf_mig_state_array; /* 23C */ + volatile csr_tph_extended_cap_header_u tph_extended_cap_header; /* 300 */ + volatile csr_tph_ctrl_u tph_ctrl; /* 304 */ + volatile csr_tph_egress_ctrl0_u tph_egress_ctrl0; /* 308 */ + volatile csr_pasid_extended_cap_header_u pasid_extended_cap_header; /* 320 */ + volatile csr_pasid_ctrl_u pasid_ctrl; /* 324 */ + volatile csr_aer_cap_header_u aer_cap_header; /* 400 */ + volatile csr_uncr_err_status_u uncr_err_status; /* 404 */ + volatile csr_uncr_err_mask_u uncr_err_mask; /* 408 */ + volatile csr_uncr_err_severity_u uncr_err_severity; /* 40C */ + volatile csr_cor_err_status_u cor_err_status; /* 410 */ + volatile csr_cor_err_mask_u cor_err_mask; /* 414 */ + volatile csr_advacd_cap_ctrl_u advacd_cap_ctrl; /* 418 */ + volatile csr_first_header_log_u first_header_log; /* 41C */ + volatile csr_second_header_log_u second_header_log; /* 420 */ + volatile csr_third_header_log_u third_header_log; /* 424 */ + volatile csr_four_header_log_u four_header_log; /* 428 */ + volatile csr_rwot_errwr_command_u rwot_errwr_command; /* 42C */ + volatile csr_rwot_errwr_status_u rwot_errwr_status; /* 430 */ + volatile csr_err_source_iden_u err_source_iden; /* 434 */ + volatile csr_first_prefix_log_u first_prefix_log; /* 438 */ + volatile csr_second_prefix_log_u second_prefix_log; /* 43C */ + volatile csr_third_prefix_log_u third_prefix_log; /* 440 */ + volatile csr_four_prefix_log_u four_prefix_log; /* 444 */ + volatile csr_ari_cap_header_u ari_cap_header; /* 450 */ + volatile csr_ari_ctrl_u ari_ctrl; /* 454 */ +} S_peh_pf_regs_REGS_TYPE; + +/* Declare the struct pointor of the module peh_pf_regs */ +extern volatile S_peh_pf_regs_REGS_TYPE *goppeh_pf_regsAllReg; + +/* Declare the functions that set the member value */ +int iSetPCIHDR_ID_hdr_vendor_id(unsigned int uhdr_vendor_id); +int iSetPCIHDR_ID_hdr_device_id(unsigned int uhdr_device_id); +int iSetPCIHDR_CMDSTS_hdr_io_space_en(unsigned int uhdr_io_space_en); +int iSetPCIHDR_CMDSTS_hdr_mem_space_en(unsigned int uhdr_mem_space_en); +int iSetPCIHDR_CMDSTS_hdr_bus_master_en(unsigned int uhdr_bus_master_en); +int iSetPCIHDR_CMDSTS_hdr_special_cycle_en(unsigned int uhdr_special_cycle_en); +int iSetPCIHDR_CMDSTS_hdr_mem_wr_invld_en(unsigned int uhdr_mem_wr_invld_en); +int iSetPCIHDR_CMDSTS_hdr_vga_snoop_en(unsigned int uhdr_vga_snoop_en); +int iSetPCIHDR_CMDSTS_hdr_parity_err_resp(unsigned int uhdr_parity_err_resp); +int iSetPCIHDR_CMDSTS_hdr_idsel_stepping(unsigned int uhdr_idsel_stepping); +int iSetPCIHDR_CMDSTS_hdr_serr_en(unsigned int uhdr_serr_en); +int iSetPCIHDR_CMDSTS_hdr_fast_b2b_en(unsigned int uhdr_fast_b2b_en); +int iSetPCIHDR_CMDSTS_hdr_intx_disable(unsigned int uhdr_intx_disable); +int iSetPCIHDR_CMDSTS_hdr_rved(unsigned int uhdr_rved); +int iSetPCIHDR_CMDSTS_hdr_intx_status(unsigned int uhdr_intx_status); +int iSetPCIHDR_CMDSTS_hdr_cap_list(unsigned int uhdr_cap_list); +int iSetPCIHDR_CMDSTS_hdr_66mhz_cap(unsigned int uhdr_66mhz_cap); +int iSetPCIHDR_CMDSTS_hdr_0reserved(unsigned int uhdr_0reserved); +int iSetPCIHDR_CMDSTS_hdr_fastb2b_cap(unsigned int uhdr_fastb2b_cap); +int iSetPCIHDR_CMDSTS_hdr_mdata_par_err(unsigned int uhdr_mdata_par_err); +int iSetPCIHDR_CMDSTS_hdr_devsel_timing(unsigned int uhdr_devsel_timing); +int iSetPCIHDR_CMDSTS_hdr_sig_target_abort(unsigned int uhdr_sig_target_abort); +int iSetPCIHDR_CMDSTS_hdr_rx_target_abort(unsigned int uhdr_rx_target_abort); +int iSetPCIHDR_CMDSTS_hdr_rx_master_abort(unsigned int uhdr_rx_master_abort); +int iSetPCIHDR_CMDSTS_hdr_rx_sys_err(unsigned int uhdr_rx_sys_err); +int iSetPCIHDR_CMDSTS_hdr_deteted_par_err(unsigned int uhdr_deteted_par_err); +int iSetPCIHDR_CLSREV_hdr_revision_id(unsigned int uhdr_revision_id); +int iSetPCIHDR_CLSREV_hdr_program_inf(unsigned int uhdr_program_inf); +int iSetPCIHDR_CLSREV_hdr_sub_class_code(unsigned int uhdr_sub_class_code); +int iSetPCIHDR_CLSREV_hdr_base_class_code(unsigned int uhdr_base_class_code); +int iSetPCIHDR_MISC_hdr_cachlie_size(unsigned int uhdr_cachlie_size); +int iSetPCIHDR_MISC_hdr_latency_timer(unsigned int uhdr_latency_timer); +int iSetPCIHDR_MISC_hdr_header_type(unsigned int uhdr_header_type); +int iSetPCIHDR_MISC_hdr_multfunc_dev(unsigned int uhdr_multfunc_dev); +int iSetPCIHDR_MISC_hdr_bist_result(unsigned int uhdr_bist_result); +int iSetPCIHDR_MISC_hdr_1reserved(unsigned int uhdr_1reserved); +int iSetPCIHDR_MISC_hdr_start_bist(unsigned int uhdr_start_bist); +int iSetPCIHDR_MISC_hdr_bist_cap(unsigned int uhdr_bist_cap); +int iSetPCIHDR_BAR0_hdr_bar0_type(unsigned int uhdr_bar0_type); +int iSetPCIHDR_BAR0_hdr_bar0_reserved(unsigned int uhdr_bar0_reserved); +int iSetPCIHDR_BAR0_hdr_bar0_width(unsigned int uhdr_bar0_width); +int iSetPCIHDR_BAR0_hdr_bar0_prefetch_en(unsigned int uhdr_bar0_prefetch_en); +int iSetPCIHDR_BAR0_hdr_2reserved(unsigned int uhdr_2reserved); +int iSetPCIHDR_BAR0_hdr_bar0_addr(unsigned int uhdr_bar0_addr); +int iSetPCIHDR_BAR1_hdr_bar1_type(unsigned int uhdr_bar1_type); +int iSetPCIHDR_BAR1_hdr_bar1_reserved(unsigned int uhdr_bar1_reserved); +int iSetPCIHDR_BAR1_hdr_bar1_width(unsigned int uhdr_bar1_width); +int iSetPCIHDR_BAR1_hdr_bar1_prefetch_en(unsigned int uhdr_bar1_prefetch_en); +int iSetPCIHDR_BAR1_hdr_bar1_2reserved(unsigned int uhdr_bar1_2reserved); +int iSetPCIHDR_BAR1_hdr_bar1_addr(unsigned int uhdr_bar1_addr); +int iSetPCIHDR_BAR2_hdr_bar2_type(unsigned int uhdr_bar2_type); +int iSetPCIHDR_BAR2_hdr_bar2_reserved(unsigned int uhdr_bar2_reserved); +int iSetPCIHDR_BAR2_hdr_bar2_width(unsigned int uhdr_bar2_width); +int iSetPCIHDR_BAR2_hdr_bar2_prefetch_en(unsigned int uhdr_bar2_prefetch_en); +int iSetPCIHDR_BAR2_hdr_bar2_2reserved(unsigned int uhdr_bar2_2reserved); +int iSetPCIHDR_BAR2_hdr_bar2_addr(unsigned int uhdr_bar2_addr); +int iSetPCIHDR_BAR3_hdr_bar3_type(unsigned int uhdr_bar3_type); +int iSetPCIHDR_BAR3_hdr_bar3_reserved(unsigned int uhdr_bar3_reserved); +int iSetPCIHDR_BAR3_hdr_bar3_width(unsigned int uhdr_bar3_width); +int iSetPCIHDR_BAR3_hdr_bar3_prefetch_en(unsigned int uhdr_bar3_prefetch_en); +int iSetPCIHDR_BAR3_hdr_bar3_2reserved(unsigned int uhdr_bar3_2reserved); +int iSetPCIHDR_BAR3_hdr_bar3_addr(unsigned int uhdr_bar3_addr); +int iSetPCIHDR_BAR4_hdr_bar4_type(unsigned int uhdr_bar4_type); +int iSetPCIHDR_BAR4_hdr_bar4_reserved(unsigned int uhdr_bar4_reserved); +int iSetPCIHDR_BAR4_hdr_bar4_width(unsigned int uhdr_bar4_width); +int iSetPCIHDR_BAR4_hdr_bar4_prefetch_en(unsigned int uhdr_bar4_prefetch_en); +int iSetPCIHDR_BAR4_hdr_bar4_2reserved(unsigned int uhdr_bar4_2reserved); +int iSetPCIHDR_BAR4_hdr_bar4_addr(unsigned int uhdr_bar4_addr); +int iSetPCIHDR_BAR5_hdr_bar5_addr(unsigned int uhdr_bar5_addr); +int iSetPCIHDR_CBUS_PTR_hdr_carbus_cis_ptr(unsigned int uhdr_carbus_cis_ptr); +int iSetPCIHDR_SUBSYS_hdr_sys_vendor_id(unsigned int uhdr_sys_vendor_id); +int iSetPCIHDR_SUBSYS_hdr_sub_sys_id(unsigned int uhdr_sub_sys_id); +int iSetPCIHDR_EXPRWM_hdr_ext_rom_enable(unsigned int uhdr_ext_rom_enable); +int iSetPCIHDR_EXPRWM_hdr_6reserved(unsigned int uhdr_6reserved); +int iSetPCIHDR_EXPRWM_hdr_ext_rom_base_addr(unsigned int uhdr_ext_rom_base_addr); +int iSetPCIHDR_CAPPTR_hdr_cap_ptr(unsigned int uhdr_cap_ptr); +int iSetPCIHDR_CAPPTR_hdr_7reserved(unsigned int uhdr_7reserved); +int iSetPCI_RSVD_hdr_8reserved(unsigned int uhdr_8reserved); +int iSetPCIHDR_INT_hdr_int_line(unsigned int uhdr_int_line); +int iSetPCIHDR_INT_hdr_int_pin(unsigned int uhdr_int_pin); +int iSetPCIHDR_INT_hdr_3creserved(unsigned int uhdr_3creserved); +int iSetPCIE_CAPABILITY_HEADER_pcap_pci_capid(unsigned int upcap_pci_capid); +int iSetPCIE_CAPABILITY_HEADER_pcap_nxt_ptr(unsigned int upcap_nxt_ptr); +int iSetPCIE_CAPABILITY_HEADER_pcap_pci_cap_ver(unsigned int upcap_pci_cap_ver); +int iSetPCIE_CAPABILITY_HEADER_pcap_port_type(unsigned int upcap_port_type); +int iSetPCIE_CAPABILITY_HEADER_pcap_slot_implement(unsigned int upcap_slot_implement); +int iSetPCIE_CAPABILITY_HEADER_pcap_int_msg_num(unsigned int upcap_int_msg_num); +int iSetPCIE_CAPABILITY_HEADER_pcap_15reserved(unsigned int upcap_15reserved); +int iSetDEVICE_CAPBILITY_pcap_max_payload_size_support(unsigned int upcap_max_payload_size_support); +int iSetDEVICE_CAPBILITY_pcap_phanotom_fun_sup(unsigned int upcap_phanotom_fun_sup); +int iSetDEVICE_CAPBILITY_pcap_ext_tag_sup(unsigned int upcap_ext_tag_sup); +int iSetDEVICE_CAPBILITY_pcap_ep_l0s_accept_lat(unsigned int upcap_ep_l0s_accept_lat); +int iSetDEVICE_CAPBILITY_pcap_ep_l1_accept_lat(unsigned int upcap_ep_l1_accept_lat); +int iSetDEVICE_CAPBILITY_pcap_undefine_04(unsigned int upcap_undefine_04); +int iSetDEVICE_CAPBILITY_pcap_ro_base_err_rpt(unsigned int upcap_ro_base_err_rpt); +int iSetDEVICE_CAPBILITY_pcap_0reserved(unsigned int upcap_0reserved); +int iSetDEVICE_CAPBILITY_pcap_cap_slot_pwr_limit_val(unsigned int upcap_cap_slot_pwr_limit_val); +int iSetDEVICE_CAPBILITY_pcap_cap_slot_pwr_sca(unsigned int upcap_cap_slot_pwr_sca); +int iSetDEVICE_CAPBILITY_pcap_flr_cap(unsigned int upcap_flr_cap); +int iSetDEVICE_CAPBILITY_pcap_16reserved(unsigned int upcap_16reserved); +int iSetDEVICE_CTRL_STATUS_pcap_cor_err_rpt_en(unsigned int upcap_cor_err_rpt_en); +int iSetDEVICE_CTRL_STATUS_pcap_non_fat_rpt_en(unsigned int upcap_non_fat_rpt_en); +int iSetDEVICE_CTRL_STATUS_pcap_fat_err_rpt_en(unsigned int upcap_fat_err_rpt_en); +int iSetDEVICE_CTRL_STATUS_pcap_ur_rpt_en(unsigned int upcap_ur_rpt_en); +int iSetDEVICE_CTRL_STATUS_pcap_relax_order_en(unsigned int upcap_relax_order_en); +int iSetDEVICE_CTRL_STATUS_pcap_max_payload_size(unsigned int upcap_max_payload_size); +int iSetDEVICE_CTRL_STATUS_pcap_extend_tag_en(unsigned int upcap_extend_tag_en); +int iSetDEVICE_CTRL_STATUS_pcap_phatom_func_en(unsigned int upcap_phatom_func_en); +int iSetDEVICE_CTRL_STATUS_pcap_aux_pwr_pm_en(unsigned int upcap_aux_pwr_pm_en); +int iSetDEVICE_CTRL_STATUS_pcap_no_snoop_en(unsigned int upcap_no_snoop_en); +int iSetDEVICE_CTRL_STATUS_pcap_max_read_req_size(unsigned int upcap_max_read_req_size); +int iSetDEVICE_CTRL_STATUS_pcap_init_flr_reset_rwwo(unsigned int upcap_init_flr_reset_rwwo); +int iSetDEVICE_CTRL_STATUS_pcap_cor_err_detect(unsigned int upcap_cor_err_detect); +int iSetDEVICE_CTRL_STATUS_pcap_non_fata_detect(unsigned int upcap_non_fata_detect); +int iSetDEVICE_CTRL_STATUS_pcap_fat_err_detect(unsigned int upcap_fat_err_detect); +int iSetDEVICE_CTRL_STATUS_pcap_ur_detect(unsigned int upcap_ur_detect); +int iSetDEVICE_CTRL_STATUS_pcap_aux_pwr_detect(unsigned int upcap_aux_pwr_detect); +int iSetDEVICE_CTRL_STATUS_pcap_tlp_pending(unsigned int upcap_tlp_pending); +int iSetDEVICE_CTRL_STATUS_pcap_1reserved(unsigned int upcap_1reserved); +int iSetLINK_CAPBILITY_pcap_max_link_speed(unsigned int upcap_max_link_speed); +int iSetLINK_CAPBILITY_pcap_max_link_width(unsigned int upcap_max_link_width); +int iSetLINK_CAPBILITY_pcap_aspm_sup(unsigned int upcap_aspm_sup); +int iSetLINK_CAPBILITY_pcap_l0_exit_lat(unsigned int upcap_l0_exit_lat); +int iSetLINK_CAPBILITY_pcap_l1_exit_lat(unsigned int upcap_l1_exit_lat); +int iSetLINK_CAPBILITY_pcap_clock_pm(unsigned int upcap_clock_pm); +int iSetLINK_CAPBILITY_pcap_surprise_dn_err_rpt_cap(unsigned int upcap_surprise_dn_err_rpt_cap); +int iSetLINK_CAPBILITY_pcap_dl_link_act_rpt_cap(unsigned int upcap_dl_link_act_rpt_cap); +int iSetLINK_CAPBILITY_pcap_link_band_notice_cap(unsigned int upcap_link_band_notice_cap); +int iSetLINK_CAPBILITY_pcap_aspm_opt_compliance(unsigned int upcap_aspm_opt_compliance); +int iSetLINK_CAPBILITY_pcap_1reserved(unsigned int upcap_1reserved); +int iSetLINK_CAPBILITY_pcap_port_num(unsigned int upcap_port_num); +int iSetLINK_CTRL_STATUS_pcap_aspm_ctrl(unsigned int upcap_aspm_ctrl); +int iSetLINK_CTRL_STATUS_pcap_4reserved(unsigned int upcap_4reserved); +int iSetLINK_CTRL_STATUS_pcap_rcb(unsigned int upcap_rcb); +int iSetLINK_CTRL_STATUS_pcap_link_disable(unsigned int upcap_link_disable); +int iSetLINK_CTRL_STATUS_pcap_retrain_link(unsigned int upcap_retrain_link); +int iSetLINK_CTRL_STATUS_pcap_common_clk_cfg(unsigned int upcap_common_clk_cfg); +int iSetLINK_CTRL_STATUS_pcap_extended_sync(unsigned int upcap_extended_sync); +int iSetLINK_CTRL_STATUS_pcap_clock_pm_en(unsigned int upcap_clock_pm_en); +int iSetLINK_CTRL_STATUS_pcap_hw_auto_width_dis(unsigned int upcap_hw_auto_width_dis); +int iSetLINK_CTRL_STATUS_pcap_link_band_int_en(unsigned int upcap_link_band_int_en); +int iSetLINK_CTRL_STATUS_pcap_link_auto_band_int_en(unsigned int upcap_link_auto_band_int_en); +int iSetLINK_CTRL_STATUS_pcap_3reserved(unsigned int upcap_3reserved); +int iSetLINK_CTRL_STATUS_pcap_mac_cur_link_spped(unsigned int upcap_mac_cur_link_spped); +int iSetLINK_CTRL_STATUS_pcap_mac_cur_link_width(unsigned int upcap_mac_cur_link_width); +int iSetLINK_CTRL_STATUS_pcap_undefined_12(unsigned int upcap_undefined_12); +int iSetLINK_CTRL_STATUS_pcap_link_training(unsigned int upcap_link_training); +int iSetLINK_CTRL_STATUS_pcap_slot_clk_cfg(unsigned int upcap_slot_clk_cfg); +int iSetLINK_CTRL_STATUS_pcap_dl_cfg_link_active(unsigned int upcap_dl_cfg_link_active); +int iSetLINK_CTRL_STATUS_pcap_link_band_status(unsigned int upcap_link_band_status); +int iSetLINK_CTRL_STATUS_pcap_link_auto_band_status(unsigned int upcap_link_auto_band_status); +int iSetSLOT_CAPABILITY_pcap_att_button_pre(unsigned int upcap_att_button_pre); +int iSetSLOT_CAPABILITY_pcap_pwr_ctrl_pre(unsigned int upcap_pwr_ctrl_pre); +int iSetSLOT_CAPABILITY_pcap_msl_sensor_pre(unsigned int upcap_msl_sensor_pre); +int iSetSLOT_CAPABILITY_pcap_att_indecator_pre(unsigned int upcap_att_indecator_pre); +int iSetSLOT_CAPABILITY_pcap_pwr_indicator_pre(unsigned int upcap_pwr_indicator_pre); +int iSetSLOT_CAPABILITY_pcap_hot_plug_surprise(unsigned int upcap_hot_plug_surprise); +int iSetSLOT_CAPABILITY_pcap_hot_plug_cap(unsigned int upcap_hot_plug_cap); +int iSetSLOT_CAPABILITY_pcap_slot_pwr_limit_val(unsigned int upcap_slot_pwr_limit_val); +int iSetSLOT_CAPABILITY_pcap_slot_pwr_limit_scale(unsigned int upcap_slot_pwr_limit_scale); +int iSetSLOT_CAPABILITY_pcap_elec_interlock_pre(unsigned int upcap_elec_interlock_pre); +int iSetSLOT_CAPABILITY_pcap_no_comman_cpled_sup(unsigned int upcap_no_comman_cpled_sup); +int iSetSLOT_CAPABILITY_pcap_physical_slot_num(unsigned int upcap_physical_slot_num); +int iSetSLOT_CTRL_STATUS_pcap_att_buttom_pre_en(unsigned int upcap_att_buttom_pre_en); +int iSetSLOT_CTRL_STATUS_pcap_pwr_fault_det_en(unsigned int upcap_pwr_fault_det_en); +int iSetSLOT_CTRL_STATUS_pcap_mrl_sensor_change_en(unsigned int upcap_mrl_sensor_change_en); +int iSetSLOT_CTRL_STATUS_pcap_presence_det_change_en(unsigned int upcap_presence_det_change_en); +int iSetSLOT_CTRL_STATUS_pcap_command_cpled_int_en(unsigned int upcap_command_cpled_int_en); +int iSetSLOT_CTRL_STATUS_pcap_hot_plug_int_en(unsigned int upcap_hot_plug_int_en); +int iSetSLOT_CTRL_STATUS_pcap_att_indicator_ctrl(unsigned int upcap_att_indicator_ctrl); +int iSetSLOT_CTRL_STATUS_pcap_pwr_indicator_ctrl(unsigned int upcap_pwr_indicator_ctrl); +int iSetSLOT_CTRL_STATUS_pcap_pwr_ctrled_ctrl(unsigned int upcap_pwr_ctrled_ctrl); +int iSetSLOT_CTRL_STATUS_pcap_elec_interlock_ctrl(unsigned int upcap_elec_interlock_ctrl); +int iSetSLOT_CTRL_STATUS_pcap_dl_state_change_en(unsigned int upcap_dl_state_change_en); +int iSetSLOT_CTRL_STATUS_pcap_6reserved(unsigned int upcap_6reserved); +int iSetSLOT_CTRL_STATUS_pcap_attention_button(unsigned int upcap_attention_button); +int iSetSLOT_CTRL_STATUS_pcap_pwr_fault_det(unsigned int upcap_pwr_fault_det); +int iSetSLOT_CTRL_STATUS_pcap_mrl_sensor_change(unsigned int upcap_mrl_sensor_change); +int iSetSLOT_CTRL_STATUS_pcap_presencd_det_change(unsigned int upcap_presencd_det_change); +int iSetSLOT_CTRL_STATUS_pcap_command_cpled(unsigned int upcap_command_cpled); +int iSetSLOT_CTRL_STATUS_pcap_mrl_sensor_st(unsigned int upcap_mrl_sensor_st); +int iSetSLOT_CTRL_STATUS_pcap_presencd_det_st(unsigned int upcap_presencd_det_st); +int iSetSLOT_CTRL_STATUS_pcap_elec_interlock_st(unsigned int upcap_elec_interlock_st); +int iSetSLOT_CTRL_STATUS_pcap_dl_state_change(unsigned int upcap_dl_state_change); +int iSetSLOT_CTRL_STATUS_pcap_5reserved(unsigned int upcap_5reserved); +int iSetROOT_CTRL_STATUS_pcap_7reserved(unsigned int upcap_7reserved); +int iSetROOT_STATUS_pcap_pme_rid(unsigned int upcap_pme_rid); +int iSetROOT_STATUS_pcap_pme_status(unsigned int upcap_pme_status); +int iSetROOT_STATUS_pcap_pme_pending(unsigned int upcap_pme_pending); +int iSetROOT_STATUS_pcap_8reserved(unsigned int upcap_8reserved); +int iSetDEVICE_CAPABILITY2_pcap_cpl_timeout_range(unsigned int upcap_cpl_timeout_range); +int iSetDEVICE_CAPABILITY2_pcap_cpl_timeout_disable_sup(unsigned int upcap_cpl_timeout_disable_sup); +int iSetDEVICE_CAPABILITY2_pcap_ari_fwd_sup(unsigned int upcap_ari_fwd_sup); +int iSetDEVICE_CAPABILITY2_pcap_atomicop_route_sup(unsigned int upcap_atomicop_route_sup); +int iSetDEVICE_CAPABILITY2_pcap_atomic_32bit_cpl_sup(unsigned int upcap_atomic_32bit_cpl_sup); +int iSetDEVICE_CAPABILITY2_pcap_atomic_64bit_cpl_sup(unsigned int upcap_atomic_64bit_cpl_sup); +int iSetDEVICE_CAPABILITY2_pcap_cas_128bit_cpl_sup(unsigned int upcap_cas_128bit_cpl_sup); +int iSetDEVICE_CAPABILITY2_pcap_no_roen_prpr_pass(unsigned int upcap_no_roen_prpr_pass); +int iSetDEVICE_CAPABILITY2_pcap_ltr_mech_sup(unsigned int upcap_ltr_mech_sup); +int iSetDEVICE_CAPABILITY2_pcap_tph_cpl_sup(unsigned int upcap_tph_cpl_sup); +int iSetDEVICE_CAPABILITY2_pcap_ln_sys_cls(unsigned int upcap_ln_sys_cls); +int iSetDEVICE_CAPABILITY2_pcap_sup_10bit_cpl_tag(unsigned int upcap_sup_10bit_cpl_tag); +int iSetDEVICE_CAPABILITY2_pcap_sup_10bit_req_tag(unsigned int upcap_sup_10bit_req_tag); +int iSetDEVICE_CAPABILITY2_pcap_obff_sup(unsigned int upcap_obff_sup); +int iSetDEVICE_CAPABILITY2_pcap_ext_fmt_sup(unsigned int upcap_ext_fmt_sup); +int iSetDEVICE_CAPABILITY2_pcap_end_end_pfx_sup(unsigned int upcap_end_end_pfx_sup); +int iSetDEVICE_CAPABILITY2_pcap_max_end_end_pfx(unsigned int upcap_max_end_end_pfx); +int iSetDEVICE_CAPABILITY2_pcap_9reserved(unsigned int upcap_9reserved); +int iSetDEVICE_CAPABILITY2_pcap_frs_sup(unsigned int upcap_frs_sup); +int iSetDEVICE_CTRL2_pcap_cpl_timeout_value(unsigned int upcap_cpl_timeout_value); +int iSetDEVICE_CTRL2_pcap_cpl_timeout_dis(unsigned int upcap_cpl_timeout_dis); +int iSetDEVICE_CTRL2_pcap_ari_fwd_en(unsigned int upcap_ari_fwd_en); +int iSetDEVICE_CTRL2_pcap_atomicop_req_en(unsigned int upcap_atomicop_req_en); +int iSetDEVICE_CTRL2_pcap_atomicop_egress_blk(unsigned int upcap_atomicop_egress_blk); +int iSetDEVICE_CTRL2_pcap_ido_req_en(unsigned int upcap_ido_req_en); +int iSetDEVICE_CTRL2_pcap_ido_cpl_en(unsigned int upcap_ido_cpl_en); +int iSetDEVICE_CTRL2_pcap_ltr_mech_en(unsigned int upcap_ltr_mech_en); +int iSetDEVICE_CTRL2_pcap_en_10bit_req_tag(unsigned int upcap_en_10bit_req_tag); +int iSetDEVICE_CTRL2_pcap_11reserved(unsigned int upcap_11reserved); +int iSetDEVICE_CTRL2_pcap_obff_en(unsigned int upcap_obff_en); +int iSetDEVICE_CTRL2_pcap_end_end_pfx_blk(unsigned int upcap_end_end_pfx_blk); +int iSetDEVICE_CTRL2_pcap_10reserved(unsigned int upcap_10reserved); +int iSetLINK_CAPABILITY2_pcap_13reserved(unsigned int upcap_13reserved); +int iSetLINK_CAPABILITY2_pcap_link_speed_sup(unsigned int upcap_link_speed_sup); +int iSetLINK_CAPABILITY2_pcap_cross_link_sup(unsigned int upcap_cross_link_sup); +int iSetLINK_CAPABILITY2_pcap_cfg_tx_lower_skp_cap(unsigned int upcap_cfg_tx_lower_skp_cap); +int iSetLINK_CAPABILITY2_pcap_cfg_rx_lower_skp_cap(unsigned int upcap_cfg_rx_lower_skp_cap); +int iSetLINK_CAPABILITY2_pcap_retimer_presence_detect(unsigned int upcap_retimer_presence_detect); +int iSetLINK_CAPABILITY2_pcap_retimer2_presence_detect(unsigned int upcap_retimer2_presence_detect); +int iSetLINK_CAPABILITY2_pcap_12reserved(unsigned int upcap_12reserved); +int iSetLINK_CAPABILITY2_pcap_drs_sup(unsigned int upcap_drs_sup); +int iSetLINK_CTRL_STATUS2_pcap_target_link_speed(unsigned int upcap_target_link_speed); +int iSetLINK_CTRL_STATUS2_pcap_enter_compliance(unsigned int upcap_enter_compliance); +int iSetLINK_CTRL_STATUS2_pcap_hw_auto_speed_dis(unsigned int upcap_hw_auto_speed_dis); +int iSetLINK_CTRL_STATUS2_pcap_selectable_de_emphasis(unsigned int upcap_selectable_de_emphasis); +int iSetLINK_CTRL_STATUS2_pcap_transmit_margin(unsigned int upcap_transmit_margin); +int iSetLINK_CTRL_STATUS2_pcap_enter_mod_compliance(unsigned int upcap_enter_mod_compliance); +int iSetLINK_CTRL_STATUS2_pcap_compliance_sos(unsigned int upcap_compliance_sos); +int iSetLINK_CTRL_STATUS2_pcap_compliance_preset_deemp(unsigned int upcap_compliance_preset_deemp); +int iSetLINK_CTRL_STATUS2_pcap_cur_deemp_level(unsigned int upcap_cur_deemp_level); +int iSetLINK_CTRL_STATUS2_pcap_eq_8g_complete(unsigned int upcap_eq_8g_complete); +int iSetLINK_CTRL_STATUS2_pcap_eq_8g_phase1_success(unsigned int upcap_eq_8g_phase1_success); +int iSetLINK_CTRL_STATUS2_pcap_eq_8g_phase2_success(unsigned int upcap_eq_8g_phase2_success); +int iSetLINK_CTRL_STATUS2_pcap_eq_8g_phase3_success(unsigned int upcap_eq_8g_phase3_success); +int iSetLINK_CTRL_STATUS2_pcap_link_8g_eq_req(unsigned int upcap_link_8g_eq_req); +int iSetLINK_CTRL_STATUS2_pcap_retimer_presence_detect(unsigned int upcap_retimer_presence_detect); +int iSetLINK_CTRL_STATUS2_pcap_retimer2_presence_detect(unsigned int upcap_retimer2_presence_detect); +int iSetLINK_CTRL_STATUS2_pcap_14reserved(unsigned int upcap_14reserved); +int iSetLINK_CTRL_STATUS2_pcap_dwstm_component_presence(unsigned int upcap_dwstm_component_presence); +int iSetLINK_CTRL_STATUS2_pcap_drs_msg_recved(unsigned int upcap_drs_msg_recved); +int iSetSLOT_CAP_2_pcap_slot_cap_2(unsigned int upcap_slot_cap_2); +int iSetSLOT_CTRL_2_pcap_slot_ctrl_2(unsigned int upcap_slot_ctrl_2); +int iSetMSI_CAP_HEADER_msicap_capability_id(unsigned int umsicap_capability_id); +int iSetMSI_CAP_HEADER_msicap_nxt_ptr(unsigned int umsicap_nxt_ptr); +int iSetMSI_CAP_HEADER_msicap_enable(unsigned int umsicap_enable); +int iSetMSI_CAP_HEADER_msicap_mmc(unsigned int umsicap_mmc); +int iSetMSI_CAP_HEADER_msicap_mme(unsigned int umsicap_mme); +int iSetMSI_CAP_HEADER_msicap_c64(unsigned int umsicap_c64); +int iSetMSI_CAP_HEADER_msicap_pvm(unsigned int umsicap_pvm); +int iSetMSI_CAP_HEADER_msicap_support(unsigned int umsicap_support); +int iSetMSI_ADDR_msicap_0reserved(unsigned int umsicap_0reserved); +int iSetMSI_ADDR_msicap_addr(unsigned int umsicap_addr); +int iSetMSI_UP_ADDR_msicap_uaddr(unsigned int umsicap_uaddr); +int iSetMSI_DATA_msicap_data(unsigned int umsicap_data); +int iSetMSI_DATA_msicap_1reserved(unsigned int umsicap_1reserved); +int iSetMSI_MASK_msicap_mask(unsigned int umsicap_mask); +int iSetMSI_PENDING_msicap_pend(unsigned int umsicap_pend); +int iSetMSIX_CAP_HEADER_msixcap_capability_id(unsigned int umsixcap_capability_id); +int iSetMSIX_CAP_HEADER_msixcap_nxt_ptr(unsigned int umsixcap_nxt_ptr); +int iSetMSIX_CAP_HEADER_msixcap_table_size(unsigned int umsixcap_table_size); +int iSetMSIX_CAP_HEADER_msixcap_0reserved(unsigned int umsixcap_0reserved); +int iSetMSIX_CAP_HEADER_msixcap_func_mask(unsigned int umsixcap_func_mask); +int iSetMSIX_CAP_HEADER_msixcap_enable(unsigned int umsixcap_enable); +int iSetMSIX_TABLE_msixcap_table_bir(unsigned int umsixcap_table_bir); +int iSetMSIX_TABLE_msixcap_table_ofset(unsigned int umsixcap_table_ofset); +int iSetMSIX_PBA_msixcap_pba_bir(unsigned int umsixcap_pba_bir); +int iSetMSIX_PBA_msixcap_pba_ofset(unsigned int umsixcap_pba_ofset); +int iSetPME_CAP_HEADER_pmcap_capability_id(unsigned int upmcap_capability_id); +int iSetPME_CAP_HEADER_pmcap_nxt_ptr(unsigned int upmcap_nxt_ptr); +int iSetPME_CAP_HEADER_pmcap_version(unsigned int upmcap_version); +int iSetPME_CAP_HEADER_pmcap_clk(unsigned int upmcap_clk); +int iSetPME_CAP_HEADER_pmcap_0reserved(unsigned int upmcap_0reserved); +int iSetPME_CAP_HEADER_pmcap_device_spec_ini(unsigned int upmcap_device_spec_ini); +int iSetPME_CAP_HEADER_pmcap_aux_current(unsigned int upmcap_aux_current); +int iSetPME_CAP_HEADER_pmcap_d1_support(unsigned int upmcap_d1_support); +int iSetPME_CAP_HEADER_pmcap_d2_support(unsigned int upmcap_d2_support); +int iSetPME_CAP_HEADER_pmcap_pme_support(unsigned int upmcap_pme_support); +int iSetPME_CTRL_STATUS_pmcap_pwr_state(unsigned int upmcap_pwr_state); +int iSetPME_CTRL_STATUS_pmcap_3reserved(unsigned int upmcap_3reserved); +int iSetPME_CTRL_STATUS_pmcap_no_soft_reset(unsigned int upmcap_no_soft_reset); +int iSetPME_CTRL_STATUS_pmcap_2reserved(unsigned int upmcap_2reserved); +int iSetPME_CTRL_STATUS_pmcap_pme_en(unsigned int upmcap_pme_en); +int iSetPME_CTRL_STATUS_pmcap_data_sel(unsigned int upmcap_data_sel); +int iSetPME_CTRL_STATUS_pmcap_data_scale(unsigned int upmcap_data_scale); +int iSetPME_CTRL_STATUS_pmcap_pme_status(unsigned int upmcap_pme_status); +int iSetPME_CTRL_STATUS_pmcap_1reserved(unsigned int upmcap_1reserved); +int iSetPME_CTRL_STATUS_pmcap_b2_b3_n(unsigned int upmcap_b2_b3_n); +int iSetPME_CTRL_STATUS_pmcap_bpcc_en(unsigned int upmcap_bpcc_en); +int iSetPME_CTRL_STATUS_pmcap_data(unsigned int upmcap_data); +int iSetACS_EXTENDED_CAP_HEADER_acscap_id(unsigned int uacscap_id); +int iSetACS_EXTENDED_CAP_HEADER_acscap_version(unsigned int uacscap_version); +int iSetACS_EXTENDED_CAP_HEADER_acscap_nxt_ptr(unsigned int uacscap_nxt_ptr); +int iSetACS_CTRL_acscap_sv(unsigned int uacscap_sv); +int iSetACS_CTRL_acscap_tb(unsigned int uacscap_tb); +int iSetACS_CTRL_acscap_prr(unsigned int uacscap_prr); +int iSetACS_CTRL_acscap_pcr(unsigned int uacscap_pcr); +int iSetACS_CTRL_acscap_uf(unsigned int uacscap_uf); +int iSetACS_CTRL_acscap_pec(unsigned int uacscap_pec); +int iSetACS_CTRL_acscap_dtp(unsigned int uacscap_dtp); +int iSetACS_CTRL_acscap_1reserved(unsigned int uacscap_1reserved); +int iSetACS_CTRL_acscap_ecvs(unsigned int uacscap_ecvs); +int iSetACS_CTRL_acscap_sv_en(unsigned int uacscap_sv_en); +int iSetACS_CTRL_acscap_tb_en(unsigned int uacscap_tb_en); +int iSetACS_CTRL_acscap_prr_en(unsigned int uacscap_prr_en); +int iSetACS_CTRL_acscap_pcr_en(unsigned int uacscap_pcr_en); +int iSetACS_CTRL_acscap_uf_en(unsigned int uacscap_uf_en); +int iSetACS_CTRL_acscap_pec_en(unsigned int uacscap_pec_en); +int iSetACS_CTRL_acscap_dtp_en(unsigned int uacscap_dtp_en); +int iSetACS_CTRL_acscap_0reserved(unsigned int uacscap_0reserved); +int iSetSRIOV_CAP_HEADER_sriovcap_id(unsigned int usriovcap_id); +int iSetSRIOV_CAP_HEADER_sriovcap_version(unsigned int usriovcap_version); +int iSetSRIOV_CAP_HEADER_sriovcap_nxt_ptr(unsigned int usriovcap_nxt_ptr); +int iSetSRIOV_CAP_sriovcap_vf_mig_cap(unsigned int usriovcap_vf_mig_cap); +int iSetSRIOV_CAP_sriovcap_ari_cap_hier_pres(unsigned int usriovcap_ari_cap_hier_pres); +int iSetSRIOV_CAP_sriovcap_0reserved(unsigned int usriovcap_0reserved); +int iSetSRIOV_CAP_sriovcap_vf_mig_int(unsigned int usriovcap_vf_mig_int); +int iSetSRIOV_CTRL_sriovcap_vf_en(unsigned int usriovcap_vf_en); +int iSetSRIOV_CTRL_sriovcap_vf_mig_en(unsigned int usriovcap_vf_mig_en); +int iSetSRIOV_CTRL_sriovcap_vf_mig_int_en(unsigned int usriovcap_vf_mig_int_en); +int iSetSRIOV_CTRL_sriovcap_vf_mse(unsigned int usriovcap_vf_mse); +int iSetSRIOV_CTRL_sriovcap_ari_cap_hier(unsigned int usriovcap_ari_cap_hier); +int iSetSRIOV_CTRL_sriovcap_2reserved(unsigned int usriovcap_2reserved); +int iSetSRIOV_CTRL_sriovcap_vf_mig_status(unsigned int usriovcap_vf_mig_status); +int iSetSRIOV_CTRL_sriovcap_1reserved(unsigned int usriovcap_1reserved); +int iSetINIT_VF_NUMBER_sriovcap_initial_vf(unsigned int usriovcap_initial_vf); +int iSetINIT_VF_NUMBER_sriovcap_totl_vfs(unsigned int usriovcap_totl_vfs); +int iSetFUNC_DEP_VF_NUM_sriovcap_num_of_vf(unsigned int usriovcap_num_of_vf); +int iSetFUNC_DEP_VF_NUM_sriovcap_func_depen_link(unsigned int usriovcap_func_depen_link); +int iSetFUNC_DEP_VF_NUM_sriovcap_3reserved(unsigned int usriovcap_3reserved); +int iSetVF_RID_SETTING_sriovcap_vf_offset(unsigned int usriovcap_vf_offset); +int iSetVF_RID_SETTING_sriovcap_vf_stride(unsigned int usriovcap_vf_stride); +int iSetVF_DEVICE_ID_sriovcap_4reserved(unsigned int usriovcap_4reserved); +int iSetVF_DEVICE_ID_sriovcap_vf_device_id(unsigned int usriovcap_vf_device_id); +int iSetVF_PAGE_SIZE_sriovcap_support_page_size(unsigned int usriovcap_support_page_size); +int iSetSYSTEM_PAGE_SIZE_sriovcap_sys_page_size(unsigned int usriovcap_sys_page_size); +int iSetVF_BAR0_sriovcap_5reserved(unsigned int usriovcap_5reserved); +int iSetVF_BAR0_sriovcap_vf_bar0_width(unsigned int usriovcap_vf_bar0_width); +int iSetVF_BAR0_sriovcap_vf_bar0_prefetch_en(unsigned int usriovcap_vf_bar0_prefetch_en); +int iSetVF_BAR0_sriovcap_resvd(unsigned int usriovcap_resvd); +int iSetVF_BAR0_sriovcap_vf_bar0_addr(unsigned int usriovcap_vf_bar0_addr); +int iSetVF_BAR1_sriovcap_vf_bar1_addr(unsigned int usriovcap_vf_bar1_addr); +int iSetVF_BAR2_sriovcap_7reserved(unsigned int usriovcap_7reserved); +int iSetVF_BAR2_sriovcap_vf_bar2_width(unsigned int usriovcap_vf_bar2_width); +int iSetVF_BAR2_sriovcap_vf_bar2_prefetch_en(unsigned int usriovcap_vf_bar2_prefetch_en); +int iSetVF_BAR2_sriovcap_resv(unsigned int usriovcap_resv); +int iSetVF_BAR2_sriovcap_vf_bar2_addr(unsigned int usriovcap_vf_bar2_addr); +int iSetVF_BAR3_sriovcap_vf_bar3_addr(unsigned int usriovcap_vf_bar3_addr); +int iSetVF_BAR4_sriovcap_9reserved(unsigned int usriovcap_9reserved); +int iSetVF_BAR4_sriovcap_vf_bar4_width(unsigned int usriovcap_vf_bar4_width); +int iSetVF_BAR4_sriovcap_vf_bar4_prefetch_en(unsigned int usriovcap_vf_bar4_prefetch_en); +int iSetVF_BAR4_sriovcap_vf_bar4_addr(unsigned int usriovcap_vf_bar4_addr); +int iSetVF_BAR5_sriovcap_10reserved(unsigned int usriovcap_10reserved); +int iSetVF_BAR5_sriovcap_vf_bar5_prefetch_en(unsigned int usriovcap_vf_bar5_prefetch_en); +int iSetVF_BAR5_sriovcap_vf_bar5_addr(unsigned int usriovcap_vf_bar5_addr); +int iSetVF_MIG_STATE_ARRAY_sriovcap_vf_mig_state_bir(unsigned int usriovcap_vf_mig_state_bir); +int iSetVF_MIG_STATE_ARRAY_sriovcap_vf_mig_state_offset(unsigned int usriovcap_vf_mig_state_offset); +int iSetTPH_EXTENDED_CAP_HEADER_tphcap_id(unsigned int utphcap_id); +int iSetTPH_EXTENDED_CAP_HEADER_tphcap_version(unsigned int utphcap_version); +int iSetTPH_EXTENDED_CAP_HEADER_tphcap_nxt_ptr(unsigned int utphcap_nxt_ptr); +int iSetTPH_CTRL_tphcap_nsms(unsigned int utphcap_nsms); +int iSetTPH_CTRL_tphcap_ivms(unsigned int utphcap_ivms); +int iSetTPH_CTRL_tphcap_sdms(unsigned int utphcap_sdms); +int iSetTPH_CTRL_tphcap_resvdp0(unsigned int utphcap_resvdp0); +int iSetTPH_CTRL_tphcap_etrs(unsigned int utphcap_etrs); +int iSetTPH_CTRL_tphcap_stl(unsigned int utphcap_stl); +int iSetTPH_CTRL_tphcap_resvdp1(unsigned int utphcap_resvdp1); +int iSetTPH_CTRL_tphcap_st_tbl_size(unsigned int utphcap_st_tbl_size); +int iSetTPH_CTRL_tphcap_resvdp2(unsigned int utphcap_resvdp2); +int iSetTPH_EGRESS_CTRL0_tphcap_sms(unsigned int utphcap_sms); +int iSetTPH_EGRESS_CTRL0_tphcap_resvdp3(unsigned int utphcap_resvdp3); +int iSetTPH_EGRESS_CTRL0_tphcap_tre(unsigned int utphcap_tre); +int iSetTPH_EGRESS_CTRL0_tphcap_resvdp4(unsigned int utphcap_resvdp4); +int iSetPASID_EXTENDED_CAP_HEADER_pasidcap_id(unsigned int upasidcap_id); +int iSetPASID_EXTENDED_CAP_HEADER_pasidcap_version(unsigned int upasidcap_version); +int iSetPASID_EXTENDED_CAP_HEADER_pasidcap_nxt_ptr(unsigned int upasidcap_nxt_ptr); +int iSetPASID_CTRL_pasidcap_resvp0(unsigned int upasidcap_resvp0); +int iSetPASID_CTRL_pasidcap_eps(unsigned int upasidcap_eps); +int iSetPASID_CTRL_pasidcap_pms(unsigned int upasidcap_pms); +int iSetPASID_CTRL_pasidcap_resvp1(unsigned int upasidcap_resvp1); +int iSetPASID_CTRL_pasidcap_mpw(unsigned int upasidcap_mpw); +int iSetPASID_CTRL_pasidcap_resvp2(unsigned int upasidcap_resvp2); +int iSetPASID_CTRL_pasidcap_pasid_en(unsigned int upasidcap_pasid_en); +int iSetPASID_CTRL_pasidcap_epe(unsigned int upasidcap_epe); +int iSetPASID_CTRL_pasidcap_pme(unsigned int upasidcap_pme); +int iSetPASID_CTRL_pasidcap_resvp3(unsigned int upasidcap_resvp3); +int iSetAER_CAP_HEADER_aercap_id(unsigned int uaercap_id); +int iSetAER_CAP_HEADER_aercap_version(unsigned int uaercap_version); +int iSetAER_CAP_HEADER_aercap_nxt_ptr(unsigned int uaercap_nxt_ptr); +int iSetUNCR_ERR_STATUS_aercap_undefined_4(unsigned int uaercap_undefined_4); +int iSetUNCR_ERR_STATUS_aercap_2reserved(unsigned int uaercap_2reserved); +int iSetUNCR_ERR_STATUS_aercap_dl_protocal_err_st(unsigned int uaercap_dl_protocal_err_st); +int iSetUNCR_ERR_STATUS_aercap_sur_down_err_st(unsigned int uaercap_sur_down_err_st); +int iSetUNCR_ERR_STATUS_aercap_1reserved(unsigned int uaercap_1reserved); +int iSetUNCR_ERR_STATUS_aercap_poisoned_tlp_st(unsigned int uaercap_poisoned_tlp_st); +int iSetUNCR_ERR_STATUS_aercap_fc_protocol_err_st(unsigned int uaercap_fc_protocol_err_st); +int iSetUNCR_ERR_STATUS_aercap_cpl_timeeout_st(unsigned int uaercap_cpl_timeeout_st); +int iSetUNCR_ERR_STATUS_aercap_cpl_abort_st(unsigned int uaercap_cpl_abort_st); +int iSetUNCR_ERR_STATUS_aercap_unexp_cpl_st(unsigned int uaercap_unexp_cpl_st); +int iSetUNCR_ERR_STATUS_aercap_rcv_overflow_st(unsigned int uaercap_rcv_overflow_st); +int iSetUNCR_ERR_STATUS_aercap_mal_tlp_st(unsigned int uaercap_mal_tlp_st); +int iSetUNCR_ERR_STATUS_aercap_ecrc_err_st(unsigned int uaercap_ecrc_err_st); +int iSetUNCR_ERR_STATUS_aercap_ur_err_st(unsigned int uaercap_ur_err_st); +int iSetUNCR_ERR_STATUS_aercap_acs_vio_st(unsigned int uaercap_acs_vio_st); +int iSetUNCR_ERR_STATUS_aercap_ue_internal_st(unsigned int uaercap_ue_internal_st); +int iSetUNCR_ERR_STATUS_aercap_mc_blk_st(unsigned int uaercap_mc_blk_st); +int iSetUNCR_ERR_STATUS_aercap_atomicop_eg_blk_st(unsigned int uaercap_atomicop_eg_blk_st); +int iSetUNCR_ERR_STATUS_aercap_tlp_pfx_blk_err_st(unsigned int uaercap_tlp_pfx_blk_err_st); +int iSetUNCR_ERR_STATUS_aercap_0reserved(unsigned int uaercap_0reserved); +int iSetUNCR_ERR_MASK_aercap_undefined_8(unsigned int uaercap_undefined_8); +int iSetUNCR_ERR_MASK_aercap_5reserved(unsigned int uaercap_5reserved); +int iSetUNCR_ERR_MASK_aercap_dl_protocal_err_mask(unsigned int uaercap_dl_protocal_err_mask); +int iSetUNCR_ERR_MASK_aercap_sur_down_err_mask(unsigned int uaercap_sur_down_err_mask); +int iSetUNCR_ERR_MASK_aercap_4reserved(unsigned int uaercap_4reserved); +int iSetUNCR_ERR_MASK_aercap_poisoned_tlp_mask(unsigned int uaercap_poisoned_tlp_mask); +int iSetUNCR_ERR_MASK_aercap_fc_protocol_err_mask(unsigned int uaercap_fc_protocol_err_mask); +int iSetUNCR_ERR_MASK_aercap_cpl_timeeout_mask(unsigned int uaercap_cpl_timeeout_mask); +int iSetUNCR_ERR_MASK_aercap_cpl_abort_mask(unsigned int uaercap_cpl_abort_mask); +int iSetUNCR_ERR_MASK_aercap_unexp_cpl_mask(unsigned int uaercap_unexp_cpl_mask); +int iSetUNCR_ERR_MASK_aercap_rcv_overflow_mask(unsigned int uaercap_rcv_overflow_mask); +int iSetUNCR_ERR_MASK_aercap_mal_tlp_mask(unsigned int uaercap_mal_tlp_mask); +int iSetUNCR_ERR_MASK_aercap_ecrc_err_mask(unsigned int uaercap_ecrc_err_mask); +int iSetUNCR_ERR_MASK_aercap_ur_err_mask(unsigned int uaercap_ur_err_mask); +int iSetUNCR_ERR_MASK_aercap_acs_vio_mask(unsigned int uaercap_acs_vio_mask); +int iSetUNCR_ERR_MASK_aercap_uncor_int_err_mask(unsigned int uaercap_uncor_int_err_mask); +int iSetUNCR_ERR_MASK_aercap_mc_blk_mask(unsigned int uaercap_mc_blk_mask); +int iSetUNCR_ERR_MASK_aercap_atomicop_eg_blk_mask(unsigned int uaercap_atomicop_eg_blk_mask); +int iSetUNCR_ERR_MASK_aercap_tlp_pfx_blk_err_mask(unsigned int uaercap_tlp_pfx_blk_err_mask); +int iSetUNCR_ERR_MASK_aercap_3reserved(unsigned int uaercap_3reserved); +int iSetUNCR_ERR_SEVERITY_aercap_undefined_c(unsigned int uaercap_undefined_c); +int iSetUNCR_ERR_SEVERITY_aercap_8reserved(unsigned int uaercap_8reserved); +int iSetUNCR_ERR_SEVERITY_aercap_dl_protocal_err_ser(unsigned int uaercap_dl_protocal_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_sur_down_err_ser(unsigned int uaercap_sur_down_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_7reserved(unsigned int uaercap_7reserved); +int iSetUNCR_ERR_SEVERITY_aercap_poisoned_tlp_ser(unsigned int uaercap_poisoned_tlp_ser); +int iSetUNCR_ERR_SEVERITY_aercap_fc_protocol_err_ser(unsigned int uaercap_fc_protocol_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_cpl_timeeout_ser(unsigned int uaercap_cpl_timeeout_ser); +int iSetUNCR_ERR_SEVERITY_aercap_cpl_abort_ser(unsigned int uaercap_cpl_abort_ser); +int iSetUNCR_ERR_SEVERITY_aercap_unexp_cpl_ser(unsigned int uaercap_unexp_cpl_ser); +int iSetUNCR_ERR_SEVERITY_aercap_rcv_overflow_ser(unsigned int uaercap_rcv_overflow_ser); +int iSetUNCR_ERR_SEVERITY_aercap_mal_tlp_ser(unsigned int uaercap_mal_tlp_ser); +int iSetUNCR_ERR_SEVERITY_aercap_ecrc_err_ser(unsigned int uaercap_ecrc_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_ur_err_ser(unsigned int uaercap_ur_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_acs_vio_ser(unsigned int uaercap_acs_vio_ser); +int iSetUNCR_ERR_SEVERITY_aercap_uncor_int_err_ser(unsigned int uaercap_uncor_int_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_mc_blk_ser(unsigned int uaercap_mc_blk_ser); +int iSetUNCR_ERR_SEVERITY_aercap_atomicop_eg_blk_ser(unsigned int uaercap_atomicop_eg_blk_ser); +int iSetUNCR_ERR_SEVERITY_aercap_tlp_pfx_blk_err_ser(unsigned int uaercap_tlp_pfx_blk_err_ser); +int iSetUNCR_ERR_SEVERITY_aercap_6reserved(unsigned int uaercap_6reserved); +int iSetCOR_ERR_STATUS_aercap_rx_err_st(unsigned int uaercap_rx_err_st); +int iSetCOR_ERR_STATUS_aercap_11reserved(unsigned int uaercap_11reserved); +int iSetCOR_ERR_STATUS_aercap_bad_tlp_st(unsigned int uaercap_bad_tlp_st); +int iSetCOR_ERR_STATUS_aercap_bad_dllp_st(unsigned int uaercap_bad_dllp_st); +int iSetCOR_ERR_STATUS_aercap_reply_num_rollover_st(unsigned int uaercap_reply_num_rollover_st); +int iSetCOR_ERR_STATUS_aercap_10reserved(unsigned int uaercap_10reserved); +int iSetCOR_ERR_STATUS_aercap_reply_timer_timout_st(unsigned int uaercap_reply_timer_timout_st); +int iSetCOR_ERR_STATUS_aercap_adv_non_fatal_err_st(unsigned int uaercap_adv_non_fatal_err_st); +int iSetCOR_ERR_STATUS_aercap_cor_int_err_st(unsigned int uaercap_cor_int_err_st); +int iSetCOR_ERR_STATUS_aercap_header_log_overflow_st(unsigned int uaercap_header_log_overflow_st); +int iSetCOR_ERR_STATUS_aercap_9reserved(unsigned int uaercap_9reserved); +int iSetCOR_ERR_MASK_aercap_rx_err_mask(unsigned int uaercap_rx_err_mask); +int iSetCOR_ERR_MASK_aercap_14reserved(unsigned int uaercap_14reserved); +int iSetCOR_ERR_MASK_aercap_bad_tlp_mask(unsigned int uaercap_bad_tlp_mask); +int iSetCOR_ERR_MASK_aercap_bad_dllp_mask(unsigned int uaercap_bad_dllp_mask); +int iSetCOR_ERR_MASK_aercap_reply_num_rollover_mask(unsigned int uaercap_reply_num_rollover_mask); +int iSetCOR_ERR_MASK_aercap_13reserved(unsigned int uaercap_13reserved); +int iSetCOR_ERR_MASK_aercap_reply_timer_timout_mask(unsigned int uaercap_reply_timer_timout_mask); +int iSetCOR_ERR_MASK_aercap_adv_non_fatal_err_mask(unsigned int uaercap_adv_non_fatal_err_mask); +int iSetCOR_ERR_MASK_aercap_cor_int_err_mask(unsigned int uaercap_cor_int_err_mask); +int iSetCOR_ERR_MASK_aercap_header_log_overflow_mask(unsigned int uaercap_header_log_overflow_mask); +int iSetCOR_ERR_MASK_aercap_12reserved(unsigned int uaercap_12reserved); +int iSetADVACD_CAP_CTRL_aercap_first_err_ptr(unsigned int uaercap_first_err_ptr); +int iSetADVACD_CAP_CTRL_aercap_ecrc_gen_cap(unsigned int uaercap_ecrc_gen_cap); +int iSetADVACD_CAP_CTRL_aercap_ecrc_gen_en(unsigned int uaercap_ecrc_gen_en); +int iSetADVACD_CAP_CTRL_aercap_ecrc_check_cap(unsigned int uaercap_ecrc_check_cap); +int iSetADVACD_CAP_CTRL_aercap_ecrc_check_en(unsigned int uaercap_ecrc_check_en); +int iSetADVACD_CAP_CTRL_aercap_multi_hdr_rec_cap(unsigned int uaercap_multi_hdr_rec_cap); +int iSetADVACD_CAP_CTRL_aercap_multi_hdr_rec_enable(unsigned int uaercap_multi_hdr_rec_enable); +int iSetADVACD_CAP_CTRL_aercap_tlp_prefix_lor_pre(unsigned int uaercap_tlp_prefix_lor_pre); +int iSetADVACD_CAP_CTRL_aercap_15reserved(unsigned int uaercap_15reserved); +int iSetFIRST_HEADER_LOG_aercap_first_header_log(unsigned int uaercap_first_header_log); +int iSetSECOND_HEADER_LOG_aercap_second_header_log(unsigned int uaercap_second_header_log); +int iSetTHIRD_HEADER_LOG_aercap_third_header_log(unsigned int uaercap_third_header_log); +int iSetFOUR_HEADER_LOG_aercap_four_header_log(unsigned int uaercap_four_header_log); +int iSetRWOT_ERRWR_COMMAND_aercap_cor_err_en(unsigned int uaercap_cor_err_en); +int iSetRWOT_ERRWR_COMMAND_aercap_non_fatal_err_en(unsigned int uaercap_non_fatal_err_en); +int iSetRWOT_ERRWR_COMMAND_aercap_fatal_err_en(unsigned int uaercap_fatal_err_en); +int iSetRWOT_ERRWR_COMMAND_aercap_16reserved(unsigned int uaercap_16reserved); +int iSetRWOT_ERRWR_STATUS_aercap_core_err_rcv(unsigned int uaercap_core_err_rcv); +int iSetRWOT_ERRWR_STATUS_aercap_multi_cor_err_rcv(unsigned int uaercap_multi_cor_err_rcv); +int iSetRWOT_ERRWR_STATUS_aercap_uncor_err_rcv(unsigned int uaercap_uncor_err_rcv); +int iSetRWOT_ERRWR_STATUS_aercap_multi_uncor_err_rcv(unsigned int uaercap_multi_uncor_err_rcv); +int iSetRWOT_ERRWR_STATUS_aercap_first_uncor_err(unsigned int uaercap_first_uncor_err); +int iSetRWOT_ERRWR_STATUS_aercap_non_fatal_msg_rcv(unsigned int uaercap_non_fatal_msg_rcv); +int iSetRWOT_ERRWR_STATUS_aercap_fatal_msg_rcv(unsigned int uaercap_fatal_msg_rcv); +int iSetRWOT_ERRWR_STATUS_aercap_17reserved(unsigned int uaercap_17reserved); +int iSetRWOT_ERRWR_STATUS_aercap_aer_int_number(unsigned int uaercap_aer_int_number); +int iSetERR_SOURCE_IDEN_aercap_err_cor_source(unsigned int uaercap_err_cor_source); +int iSetERR_SOURCE_IDEN_aercap_err_non_cir_source(unsigned int uaercap_err_non_cir_source); +int iSetFIRST_PREFIX_LOG_aercap_first_prefix_log(unsigned int uaercap_first_prefix_log); +int iSetSECOND_PREFIX_LOG_aercap_second_prefix_log(unsigned int uaercap_second_prefix_log); +int iSetTHIRD_PREFIX_LOG_aercap_third_prefix_log(unsigned int uaercap_third_prefix_log); +int iSetFOUR_PREFIX_LOG_aercap_four_prefix_log(unsigned int uaercap_four_prefix_log); +int iSetARI_CAP_HEADER_aricap_id(unsigned int uaricap_id); +int iSetARI_CAP_HEADER_aricap_version(unsigned int uaricap_version); +int iSetARI_CAP_HEADER_aricap_nxt_ptr(unsigned int uaricap_nxt_ptr); +int iSetARI_CTRL_aricap_mfvc_func_grp_cap(unsigned int uaricap_mfvc_func_grp_cap); +int iSetARI_CTRL_aricap_acs_func_grp_cap(unsigned int uaricap_acs_func_grp_cap); +int iSetARI_CTRL_aricap_2reserved(unsigned int uaricap_2reserved); +int iSetARI_CTRL_aricap_nxt_func_num(unsigned int uaricap_nxt_func_num); +int iSetARI_CTRL_aricap_mfvc_func_grp_en(unsigned int uaricap_mfvc_func_grp_en); +int iSetARI_CTRL_aricap_acs_func_grp_en(unsigned int uaricap_acs_func_grp_en); +int iSetARI_CTRL_aricap_1reserved(unsigned int uaricap_1reserved); +int iSetARI_CTRL_aricap_func_group(unsigned int uaricap_func_group); +int iSetARI_CTRL_aricap_0reserved(unsigned int uaricap_0reserved); + +/* Define the union csr_vf_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_vendor_id : 16; /* [15:0] */ + u32 vf_hdr_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_id_u; + +/* Define the union csr_vf_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_io_space_en : 1; /* [0] */ + u32 vf_hdr_mem_space_en : 1; /* [1] */ + u32 vf_hdr_bus_master_en : 1; /* [2] */ + u32 vf_hdr_special_cycle_en : 1; /* [3] */ + u32 vf_hdr_mem_wr_invld_en : 1; /* [4] */ + u32 vf_hdr_vga_snoop_en : 1; /* [5] */ + u32 vf_hdr_parity_err_resp : 1; /* [6] */ + u32 vf_hdr_idsel_stepping : 1; /* [7] */ + u32 vf_hdr_serr_en : 1; /* [8] */ + u32 vf_hdr_fast_b2b_en : 1; /* [9] */ + u32 vf_hdr_intx_disable : 1; /* [10] */ + u32 vf_hdr_rved : 8; /* [18:11] */ + u32 vf_hdr_intx_status : 1; /* [19] */ + u32 vf_hdr_cap_list : 1; /* [20] */ + u32 vf_hdr_66mhz_cap : 1; /* [21] */ + u32 vf_hdr_0reserved : 1; /* [22] */ + u32 vf_hdr_fastb2b_cap : 1; /* [23] */ + u32 vf_hdr_mdata_par_err : 1; /* [24] */ + u32 vf_hdr_devsel_timing : 2; /* [26:25] */ + u32 vf_hdr_sig_target_abort : 1; /* [27] */ + u32 vf_hdr_rx_target_abort : 1; /* [28] */ + u32 vf_hdr_rx_master_abort : 1; /* [29] */ + u32 vf_hdr_rx_sys_err : 1; /* [30] */ + u32 vf_hdr_deteted_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_cmdsts_u; + +/* Define the union csr_vf_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_revision_id : 8; /* [7:0] */ + u32 vf_hdr_program_inf : 8; /* [15:8] */ + u32 vf_hdr_sub_class_code : 8; /* [23:16] */ + u32 vf_hdr_base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_clsrev_u; + +/* Define the union csr_vf_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_cachlie_size : 8; /* [7:0] */ + u32 vf_hdr_latency_timer : 8; /* [15:8] */ + u32 vf_hdr_header_type : 7; /* [22:16] */ + u32 vf_hdr_multfunc_dev : 1; /* [23] */ + u32 vf_hdr_bist_result : 4; /* [27:24] */ + u32 vf_hdr_1reserved : 2; /* [29:28] */ + u32 vf_hdr_start_bist : 1; /* [30] */ + u32 vf_hdr_bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_misc_u; + +/* Define the union csr_vf_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_bar0_type : 1; /* [0] */ + u32 vf_hdr_3reserved : 1; /* [1] */ + u32 vf_hdr_bar0_width : 1; /* [2] */ + u32 vf_hdr_bar0_prefetch_en : 1; /* [3] */ + u32 vf_hdr_2reserved : 12; /* [15:4] */ + u32 vf_hdr_bar0_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_bar0_u; + +/* Define the union csr_vf_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_bar1_u; + +/* Define the union csr_vf_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_bar2_type : 1; /* [0] */ + u32 vf_hdr_4reserved : 1; /* [1] */ + u32 vf_hdr_bar2_width : 1; /* [2] */ + u32 vf_hdr_bar2_prefetch_en : 1; /* [3] */ + u32 vf_hdr_bar2reserved : 16; /* [19:4] */ + u32 vf_hdr_bar2_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_bar2_u; + +/* Define the union csr_vf_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_bar3_u; + +/* Define the union csr_vf_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_bar4_u; + +/* Define the union csr_vf_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_bar5_type : 1; /* [0] */ + u32 vf_hdr_bar5_reserved1 : 1; /* [1] */ + u32 vf_hdr_bar5_width : 1; /* [2] */ + u32 vf_hdr_bar5_prefetch_en : 1; /* [3] */ + u32 vf_hdr_bar5reserved : 12; /* [15:4] */ + u32 vf_hdr_bar5_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_bar5_u; + +/* Define the union csr_vf_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_cbus_ptr_u; + +/* Define the union csr_vf_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_sys_vendor_id : 16; /* [15:0] */ + u32 vf_hdr_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_subsys_u; + +/* Define the union csr_vf_pcihdr_exprwm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_ext_rom_enable : 1; /* [0] */ + u32 vf_hdr_6reserved : 10; /* [10:1] */ + u32 vf_hdr_ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_exprwm_u; + +/* Define the union csr_vf_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_cap_ptr : 8; /* [7:0] */ + u32 vf_hdr_7reserved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_capptr_u; + +/* Define the union csr_vf_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_8reserved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pci_rsvd_u; + +/* Define the union csr_vf_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_hdr_int_line : 8; /* [7:0] */ + u32 vf_hdr_int_pin : 8; /* [15:8] */ + u32 vf_hdr_3creserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcihdr_int_u; + +/* Define the union csr_vf_pcie_capability_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_pci_capid : 8; /* [7:0] */ + u32 vf_pcap_nxt_ptr : 8; /* [15:8] */ + u32 vf_pcap_pci_cap_ver : 4; /* [19:16] */ + u32 vf_pcap_port_type : 4; /* [23:20] */ + u32 vf_pcap_slot_implement : 1; /* [24] */ + u32 vf_pcap_int_msg_num : 5; /* [29:25] */ + u32 vf_pcap_15reserved : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pcie_capability_header_u; + +/* Define the union csr_vf_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_max_payload_size_support : 3; /* [2:0] */ + u32 vf_pcap_phanotom_fun_sup : 2; /* [4:3] */ + u32 vf_pcap_ext_tag_sup : 1; /* [5] */ + u32 vf_pcap_ep_l0s_accept_lat : 3; /* [8:6] */ + u32 vf_pcap_ep_l1_accept_lat : 3; /* [11:9] */ + u32 vf_pcap_undefine_04 : 3; /* [14:12] */ + u32 vf_pcap_ro_base_err_rpt : 1; /* [15] */ + u32 vf_pcap_0reserved : 2; /* [17:16] */ + u32 vf_pcap_cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 vf_pcap_cap_slot_pwr_sca : 2; /* [27:26] */ + u32 vf_pcap_flr_cap : 1; /* [28] */ + u32 vf_pcap_16reserved : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_device_capbility_u; + +/* Define the union csr_vf_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_cor_err_rpt_en : 1; /* [0] */ + u32 vf_pcap_non_fat_rpt_en : 1; /* [1] */ + u32 vf_pcap_fat_err_rpt_en : 1; /* [2] */ + u32 vf_pcap_ur_rpt_en : 1; /* [3] */ + u32 vf_pcap_relax_order_en : 1; /* [4] */ + u32 vf_pcap_max_payload_size : 3; /* [7:5] */ + u32 vf_pcap_extend_tag_en : 1; /* [8] */ + u32 vf_pcap_phatom_func_en : 1; /* [9] */ + u32 vf_pcap_aux_pwr_pm_en : 1; /* [10] */ + u32 vf_pcap_no_snoop_en : 1; /* [11] */ + u32 vf_pcap_max_read_req_size : 3; /* [14:12] */ + u32 vf_pcap_init_flr_reset_rwwo : 1; /* [15] */ + u32 vf_pcap_cor_err_detect : 1; /* [16] */ + u32 vf_pcap_non_fata_detect : 1; /* [17] */ + u32 vf_pcap_fat_err_detect : 1; /* [18] */ + u32 vf_pcap_ur_detect : 1; /* [19] */ + u32 vf_pcap_aux_pwr_detect : 1; /* [20] */ + u32 vf_pcap_tlp_pending : 1; /* [21] */ + u32 vf_pcap_1reserved : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_device_ctrl_status_u; + +/* Define the union csr_vf_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_max_link_speed : 4; /* [3:0] */ + u32 vf_pcap_max_link_width : 6; /* [9:4] */ + u32 vf_pcap_aspm_sup : 2; /* [11:10] */ + u32 vf_pcap_l0_exit_lat : 3; /* [14:12] */ + u32 vf_pcap_l1_exit_lat : 3; /* [17:15] */ + u32 vf_pcap_clock_pm : 1; /* [18] */ + u32 vf_pcap_surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 vf_pcap_dl_link_act_rpt_cap : 1; /* [20] */ + u32 vf_pcap_link_band_notice_cap : 1; /* [21] */ + u32 vf_pcap_aspm_opt_compliance : 1; /* [22] */ + u32 vf_pcap_1reserved : 1; /* [23] */ + u32 vf_pcap_port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_link_capbility_u; + +/* Define the union csr_vf_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_aspm_ctrl : 2; /* [1:0] */ + u32 vf_pcap_4reserved : 1; /* [2] */ + u32 vf_pcap_rcb : 1; /* [3] */ + u32 vf_pcap_link_disable : 1; /* [4] */ + u32 vf_pcap_retrain_link : 1; /* [5] */ + u32 vf_pcap_common_clk_cfg : 1; /* [6] */ + u32 vf_pcap_extended_sync : 1; /* [7] */ + u32 vf_pcap_clock_pm_en : 1; /* [8] */ + u32 vf_pcap_hw_auto_width_dis : 1; /* [9] */ + u32 vf_pcap_link_band_int_en : 1; /* [10] */ + u32 vf_pcap_link_auto_band_int_en : 1; /* [11] */ + u32 vf_pcap_3reserved : 4; /* [15:12] */ + u32 vf_pcap_mac_cur_link_spped : 4; /* [19:16] */ + u32 vf_pcap_mac_cur_link_width : 6; /* [25:20] */ + u32 vf_pcap_undefined_12 : 1; /* [26] */ + u32 vf_pcap_link_training : 1; /* [27] */ + u32 vf_pcap_slot_clk_cfg : 1; /* [28] */ + u32 vf_pcap_dl_cfg_link_active : 1; /* [29] */ + u32 vf_pcap_link_band_status : 1; /* [30] */ + u32 vf_pcap_link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_link_ctrl_status_u; + +/* Define the union csr_vf_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_att_button_pre : 1; /* [0] */ + u32 vf_pcap_pwr_ctrl_pre : 1; /* [1] */ + u32 vf_pcap_msl_sensor_pre : 1; /* [2] */ + u32 vf_pcap_att_indecator_pre : 1; /* [3] */ + u32 vf_pcap_pwr_indicator_pre : 1; /* [4] */ + u32 vf_pcap_hot_plug_surprise : 1; /* [5] */ + u32 vf_pcap_hot_plug_cap : 1; /* [6] */ + u32 vf_pcap_slot_pwr_limit_val : 8; /* [14:7] */ + u32 vf_pcap_slot_pwr_limit_scale : 2; /* [16:15] */ + u32 vf_pcap_elec_interlock_pre : 1; /* [17] */ + u32 vf_pcap_no_comman_cpled_sup : 1; /* [18] */ + u32 vf_pcap_physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_slot_capability_u; + +/* Define the union csr_vf_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_att_buttom_pre_en : 1; /* [0] */ + u32 vf_pcap_pwr_fault_det_en : 1; /* [1] */ + u32 vf_pcap_mrl_sensor_change_en : 1; /* [2] */ + u32 vf_pcap_presence_det_change_en : 1; /* [3] */ + u32 vf_pcap_command_cpled_int_en : 1; /* [4] */ + u32 vf_pcap_hot_plug_int_en : 1; /* [5] */ + u32 vf_pcap_att_indicator_ctrl : 2; /* [7:6] */ + u32 vf_pcap_pwr_indicator_ctrl : 2; /* [9:8] */ + u32 vf_pcap_pwr_ctrled_ctrl : 1; /* [10] */ + u32 vf_pcap_elec_interlock_ctrl : 1; /* [11] */ + u32 vf_pcap_dl_state_change_en : 1; /* [12] */ + u32 vf_pcap_6reserved : 3; /* [15:13] */ + u32 vf_pcap_attention_button : 1; /* [16] */ + u32 vf_pcap_pwr_fault_det : 1; /* [17] */ + u32 vf_pcap_mrl_sensor_change : 1; /* [18] */ + u32 vf_pcap_presencd_det_change : 1; /* [19] */ + u32 vf_pcap_command_cpled : 1; /* [20] */ + u32 vf_pcap_mrl_sensor_st : 1; /* [21] */ + u32 vf_pcap_presencd_det_st : 1; /* [22] */ + u32 vf_pcap_elec_interlock_st : 1; /* [23] */ + u32 vf_pcap_dl_state_change : 1; /* [24] */ + u32 vf_pcap_5reserved : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_slot_ctrl_status_u; + +/* Define the union csr_vf_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_7reserved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_root_ctrl_status_u; + +/* Define the union csr_vf_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_pme_rid : 16; /* [15:0] */ + u32 vf_pcap_pme_status : 1; /* [16] */ + u32 vf_pcap_pme_pending : 1; /* [17] */ + u32 vf_pcap_8reserved : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_root_status_u; + +/* Define the union csr_vf_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_cpl_timeout_range : 4; /* [3:0] */ + u32 vf_pcap_cpl_timeout_disable_sup : 1; /* [4] */ + u32 vf_pcap_ari_fwd_sup : 1; /* [5] */ + u32 vf_pcap_atomicop_route_sup : 1; /* [6] */ + u32 vf_pcap_atomic_32bit_cpl_sup : 1; /* [7] */ + u32 vf_pcap_atomic_64bit_cpl_sup : 1; /* [8] */ + u32 vf_pcap_cas_128bit_cpl_sup : 1; /* [9] */ + u32 vf_pcap_no_roen_prpr_pass : 1; /* [10] */ + u32 vf_pcap_ltr_mech_sup : 1; /* [11] */ + u32 vf_pcap_tph_cpl_sup : 2; /* [13:12] */ + u32 vf_pcap_ln_sys_cls : 2; /* [15:14] */ + u32 vf_pcap_sup_10bit_cpl_tag : 1; /* [16] */ + u32 vf_pcap_sup_10bit_req_tag : 1; /* [17] */ + u32 vf_pcap_obff_sup : 2; /* [19:18] */ + u32 vf_pcap_ext_fmt_sup : 1; /* [20] */ + u32 vf_pcap_end_end_pfx_sup : 1; /* [21] */ + u32 vf_pcap_max_end_end_pfx : 2; /* [23:22] */ + u32 vf_pcap_9reserved : 7; /* [30:24] */ + u32 vf_pcap_frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_device_capability2_u; + +/* Define the union csr_vf_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_cpl_timeout_value : 4; /* [3:0] */ + u32 vf_pcap_cpl_timeout_dis : 1; /* [4] */ + u32 vf_pcap_ari_fwd_en : 1; /* [5] */ + u32 vf_pcap_atomicop_req_en : 1; /* [6] */ + u32 vf_pcap_atomicop_egress_blk : 1; /* [7] */ + u32 vf_pcap_ido_req_en : 1; /* [8] */ + u32 vf_pcap_ido_cpl_en : 1; /* [9] */ + u32 vf_pcap_ltr_mech_en : 1; /* [10] */ + u32 vf_pcap_en_10bit_req_tag : 1; /* [11] */ + u32 vf_pcap_11reserved : 1; /* [12] */ + u32 vf_pcap_obff_en : 2; /* [14:13] */ + u32 vf_pcap_end_end_pfx_blk : 1; /* [15] */ + u32 vf_pcap_10reserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_device_ctrl2_u; + +/* Define the union csr_vf_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_13reserved : 1; /* [0] */ + u32 vf_pcap_link_speed_sup : 7; /* [7:1] */ + u32 vf_pcap_cross_link_sup : 1; /* [8] */ + u32 vf_pcap_cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 vf_pcap_cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 vf_pcap_retimer_presence_detect : 1; /* [23] */ + u32 vf_pcap_retimer2_presence_detect : 1; /* [24] */ + u32 vf_pcap_12reserved : 6; /* [30:25] */ + u32 vf_pcap_drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_link_capability2_u; + +/* Define the union csr_vf_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_target_link_speed : 4; /* [3:0] */ + u32 vf_pcap_enter_compliance : 1; /* [4] */ + u32 vf_pcap_hw_auto_speed_dis : 1; /* [5] */ + u32 vf_pcap_selectable_de_emphasis : 1; /* [6] */ + u32 vf_pcap_transmit_margin : 3; /* [9:7] */ + u32 vf_pcap_enter_mod_compliance : 1; /* [10] */ + u32 vf_pcap_compliance_sos : 1; /* [11] */ + u32 vf_pcap_compliance_preset_deemp : 4; /* [15:12] */ + u32 vf_pcap_cur_deemp_level : 1; /* [16] */ + u32 vf_pcap_eq_8g_complete : 1; /* [17] */ + u32 vf_pcap_eq_8g_phase1_success : 1; /* [18] */ + u32 vf_pcap_eq_8g_phase2_success : 1; /* [19] */ + u32 vf_pcap_eq_8g_phase3_success : 1; /* [20] */ + u32 vf_pcap_link_8g_eq_req : 1; /* [21] */ + u32 vf_pcap_retimer_presence_detect : 1; /* [22] */ + u32 vf_pcap_retimer2_presence_detect : 1; /* [23] */ + u32 vf_pcap_14reserved : 4; /* [27:24] */ + u32 vf_pcap_dwstm_component_presence : 1; /* [28] */ + u32 vf_pcap_drs_msg_recved : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_link_ctrl_status2_u; + +/* Define the union csr_vf_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_slot_cap_2_u; + +/* Define the union csr_vf_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pcap_slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_slot_ctrl_2_u; + +/* Define the union csr_vf_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msicap_capability_id : 8; /* [7:0] */ + u32 vf_msicap_nxt_ptr : 8; /* [15:8] */ + u32 vf_msicap_enable : 1; /* [16] */ + u32 vf_msicap_mmc : 3; /* [19:17] */ + u32 vf_msicap_mme : 3; /* [22:20] */ + u32 vf_msicap_c64 : 1; /* [23] */ + u32 vf_msicap_pvm : 1; /* [24] */ + u32 vf_msicap_support : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msi_cap_header_u; + +/* Define the union csr_vf_msi_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msicap_0reserved : 2; /* [1:0] */ + u32 vf_msicap_addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msi_addr_u; + +/* Define the union csr_vf_msi_up_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msicap_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msi_up_addr_u; + +/* Define the union csr_vf_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msicap_data : 16; /* [15:0] */ + u32 vf_msicap_1reserved : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msi_data_u; + +/* Define the union csr_vf_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msicap_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msi_mask_u; + +/* Define the union csr_vf_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msicap_pend : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msi_pending_u; + +/* Define the union csr_vf_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msixcap_capability_id : 8; /* [7:0] */ + u32 vf_msixcap_nxt_ptr : 8; /* [15:8] */ + u32 vf_msixcap_table_size : 11; /* [26:16] */ + u32 vf_msixcap_0reserved : 3; /* [29:27] */ + u32 vf_msixcap_func_mask : 1; /* [30] */ + u32 vf_msixcap_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msix_cap_header_u; + +/* Define the union csr_vf_msix_table_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msixcap_table_bir : 3; /* [2:0] */ + u32 vf_msixcap_table_ofset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msix_table_u; + +/* Define the union csr_vf_msix_pba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_msixcap_pba_bir : 3; /* [2:0] */ + u32 vf_msixcap_pba_ofset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_msix_pba_u; + +/* Define the union csr_vf_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pmcap_capability_id : 8; /* [7:0] */ + u32 vf_pmcap_nxt_ptr : 8; /* [15:8] */ + u32 vf_pmcap_version : 3; /* [18:16] */ + u32 vf_pmcap_clk : 1; /* [19] */ + u32 vf_pmcap_0reserved : 1; /* [20] */ + u32 vf_pmcap_device_spec_ini : 1; /* [21] */ + u32 vf_pmcap_aux_current : 3; /* [24:22] */ + u32 vf_pmcap_d1_support : 1; /* [25] */ + u32 vf_pmcap_d2_support : 1; /* [26] */ + u32 vf_pmcap_pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pme_cap_header_u; + +/* Define the union csr_vf_pme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_pmcap_pwr_status : 2; /* [1:0] */ + u32 vf_pmcap_3reserved : 1; /* [2] */ + u32 vf_pmcap_no_soft_reset : 1; /* [3] */ + u32 vf_pmcap_2reserved : 4; /* [7:4] */ + u32 vf_pmcap_pme_en : 1; /* [8] */ + u32 vf_pmcap_data_sel : 4; /* [12:9] */ + u32 vf_pmcap_data_scale : 2; /* [14:13] */ + u32 vf_pmcap_pme_status : 1; /* [15] */ + u32 vf_pmcap_1reserved : 6; /* [21:16] */ + u32 vf_pmcap_b2_b3_n : 1; /* [22] */ + u32 vf_pmcap_bpcc_en : 1; /* [23] */ + u32 vf_pmcap_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_pme_ctrl_status_u; + +/* Define the union csr_vf_acs_extended_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_acscap_id : 16; /* [15:0] */ + u32 vf_acscap_version : 4; /* [19:16] */ + u32 vf_acscap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_acs_extended_cap_header_u; + +/* Define the union csr_vf_acs_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_acscap_sv : 1; /* [0] */ + u32 vf_acscap_tb : 1; /* [1] */ + u32 vf_acscap_prr : 1; /* [2] */ + u32 vf_acscap_pcr : 1; /* [3] */ + u32 vf_acscap_uf : 1; /* [4] */ + u32 vf_acscap_pec : 1; /* [5] */ + u32 vf_acscap_dtp : 1; /* [6] */ + u32 vf_acscap_1reserved : 1; /* [7] */ + u32 vf_acscap_ecvs : 8; /* [15:8] */ + u32 vf_acscap_sv_en : 1; /* [16] */ + u32 vf_acscap_tb_en : 1; /* [17] */ + u32 vf_acscap_prr_en : 1; /* [18] */ + u32 vf_acscap_pcr_en : 1; /* [19] */ + u32 vf_acscap_uf_en : 1; /* [20] */ + u32 vf_acscap_pec_en : 1; /* [21] */ + u32 vf_acscap_dtp_en : 1; /* [22] */ + u32 vf_acscap_0reserved : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_acs_ctrl_u; + +/* Define the union csr_vf_tph_extended_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_tphcap_id : 16; /* [15:0] */ + u32 vf_tphcap_version : 4; /* [19:16] */ + u32 vf_tphcap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_tph_extended_cap_header_u; + +/* Define the union csr_vf_tph_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_tphcap_nsms : 1; /* [0] */ + u32 vf_tphcap_ivms : 1; /* [1] */ + u32 vf_tphcap_sdms : 1; /* [2] */ + u32 vf_tphcap_resvdp0 : 5; /* [7:3] */ + u32 vf_tphcap_etrs : 1; /* [8] */ + u32 vf_tphcap_stl : 2; /* [10:9] */ + u32 vf_tphcap_resvdp1 : 5; /* [15:11] */ + u32 vf_tphcap_st_tbl_size : 11; /* [26:16] */ + u32 vf_tphcap_resvdp2 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_tph_ctrl_u; + +/* Define the union csr_vf_tph_egress_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_tphcap_sms : 3; /* [2:0] */ + u32 vf_tphcap_resvdp3 : 5; /* [7:3] */ + u32 vf_tphcap_tre : 1; /* [8] */ + u32 vf_tphcap_resvdp4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_tph_egress_ctrl0_u; + +/* Define the union csr_vf_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_aricap_id : 16; /* [15:0] */ + u32 vf_aricap_version : 4; /* [19:16] */ + u32 vf_aricap_nxt_ptr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_ari_cap_header_u; + +/* Define the union csr_vf_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_aricap_mfvc_func_grp_cap : 1; /* [0] */ + u32 vf_aricap_acs_func_grp_cap : 1; /* [1] */ + u32 vf_aricap_2reserved : 6; /* [7:2] */ + u32 vf_aricap_nxt_func_num : 8; /* [15:8] */ + u32 vf_aricap_mfvc_func_grp_en : 1; /* [16] */ + u32 vf_aricap_acs_func_grp_en : 1; /* [17] */ + u32 vf_aricap_1reserved : 2; /* [19:18] */ + u32 vf_aricap_func_group : 3; /* [22:20] */ + u32 vf_aricap_0reserved : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_ari_ctrl_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_vf_pcihdr_id_u vf_pcihdr_id; /* 0 */ + volatile csr_vf_pcihdr_cmdsts_u vf_pcihdr_cmdsts; /* 4 */ + volatile csr_vf_pcihdr_clsrev_u vf_pcihdr_clsrev; /* 8 */ + volatile csr_vf_pcihdr_misc_u vf_pcihdr_misc; /* C */ + volatile csr_vf_pcihdr_bar0_u vf_pcihdr_bar0; /* 10 */ + volatile csr_vf_pcihdr_bar1_u vf_pcihdr_bar1; /* 14 */ + volatile csr_vf_pcihdr_bar2_u vf_pcihdr_bar2; /* 18 */ + volatile csr_vf_pcihdr_bar3_u vf_pcihdr_bar3; /* 1C */ + volatile csr_vf_pcihdr_bar4_u vf_pcihdr_bar4; /* 20 */ + volatile csr_vf_pcihdr_bar5_u vf_pcihdr_bar5; /* 24 */ + volatile csr_vf_pcihdr_cbus_ptr_u vf_pcihdr_cbus_ptr; /* 28 */ + volatile csr_vf_pcihdr_subsys_u vf_pcihdr_subsys; /* 2C */ + volatile csr_vf_pcihdr_exprwm_u vf_pcihdr_exprwm; /* 30 */ + volatile csr_vf_pcihdr_capptr_u vf_pcihdr_capptr; /* 34 */ + volatile csr_vf_pci_rsvd_u vf_pci_rsvd; /* 38 */ + volatile csr_vf_pcihdr_int_u vf_pcihdr_int; /* 3C */ + volatile csr_vf_pcie_capability_header_u vf_pcie_capability_header; /* 40 */ + volatile csr_vf_device_capbility_u vf_device_capbility; /* 44 */ + volatile csr_vf_device_ctrl_status_u vf_device_ctrl_status; /* 48 */ + volatile csr_vf_link_capbility_u vf_link_capbility; /* 4C */ + volatile csr_vf_link_ctrl_status_u vf_link_ctrl_status; /* 50 */ + volatile csr_vf_slot_capability_u vf_slot_capability; /* 54 */ + volatile csr_vf_slot_ctrl_status_u vf_slot_ctrl_status; /* 58 */ + volatile csr_vf_root_ctrl_status_u vf_root_ctrl_status; /* 5C */ + volatile csr_vf_root_status_u vf_root_status; /* 60 */ + volatile csr_vf_device_capability2_u vf_device_capability2; /* 64 */ + volatile csr_vf_device_ctrl2_u vf_device_ctrl2; /* 68 */ + volatile csr_vf_link_capability2_u vf_link_capability2; /* 6C */ + volatile csr_vf_link_ctrl_status2_u vf_link_ctrl_status2; /* 70 */ + volatile csr_vf_slot_cap_2_u vf_slot_cap_2; /* 74 */ + volatile csr_vf_slot_ctrl_2_u vf_slot_ctrl_2; /* 78 */ + volatile csr_vf_msi_cap_header_u vf_msi_cap_header; /* 80 */ + volatile csr_vf_msi_addr_u vf_msi_addr; /* 84 */ + volatile csr_vf_msi_up_addr_u vf_msi_up_addr; /* 88 */ + volatile csr_vf_msi_data_u vf_msi_data; /* 8C */ + volatile csr_vf_msi_mask_u vf_msi_mask; /* 90 */ + volatile csr_vf_msi_pending_u vf_msi_pending; /* 94 */ + volatile csr_vf_msix_cap_header_u vf_msix_cap_header; /* A0 */ + volatile csr_vf_msix_table_u vf_msix_table; /* A4 */ + volatile csr_vf_msix_pba_u vf_msix_pba; /* A8 */ + volatile csr_vf_pme_cap_header_u vf_pme_cap_header; /* B0 */ + volatile csr_vf_pme_ctrl_status_u vf_pme_ctrl_status; /* B4 */ + volatile csr_vf_acs_extended_cap_header_u vf_acs_extended_cap_header; /* 100 */ + volatile csr_vf_acs_ctrl_u vf_acs_ctrl; /* 104 */ + volatile csr_vf_tph_extended_cap_header_u vf_tph_extended_cap_header; /* 300 */ + volatile csr_vf_tph_ctrl_u vf_tph_ctrl; /* 304 */ + volatile csr_vf_tph_egress_ctrl0_u vf_tph_egress_ctrl0; /* 308 */ + volatile csr_vf_ari_cap_header_u vf_ari_cap_header; /* 450 */ + volatile csr_vf_ari_ctrl_u vf_ari_ctrl; /* 454 */ +} S_peh_vf_regs_REGS_TYPE; + +/* Declare the struct pointor of the module peh_vf_regs */ +extern volatile S_peh_vf_regs_REGS_TYPE *goppeh_vf_regsAllReg; + +/* Declare the functions that set the member value */ +int iSetVF_PCIHDR_ID_vf_hdr_vendor_id(unsigned int uvf_hdr_vendor_id); +int iSetVF_PCIHDR_ID_vf_hdr_device_id(unsigned int uvf_hdr_device_id); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_io_space_en(unsigned int uvf_hdr_io_space_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_mem_space_en(unsigned int uvf_hdr_mem_space_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_bus_master_en(unsigned int uvf_hdr_bus_master_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_special_cycle_en(unsigned int uvf_hdr_special_cycle_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_mem_wr_invld_en(unsigned int uvf_hdr_mem_wr_invld_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_vga_snoop_en(unsigned int uvf_hdr_vga_snoop_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_parity_err_resp(unsigned int uvf_hdr_parity_err_resp); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_idsel_stepping(unsigned int uvf_hdr_idsel_stepping); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_serr_en(unsigned int uvf_hdr_serr_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_fast_b2b_en(unsigned int uvf_hdr_fast_b2b_en); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_intx_disable(unsigned int uvf_hdr_intx_disable); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_rved(unsigned int uvf_hdr_rved); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_intx_status(unsigned int uvf_hdr_intx_status); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_cap_list(unsigned int uvf_hdr_cap_list); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_66mhz_cap(unsigned int uvf_hdr_66mhz_cap); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_0reserved(unsigned int uvf_hdr_0reserved); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_fastb2b_cap(unsigned int uvf_hdr_fastb2b_cap); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_mdata_par_err(unsigned int uvf_hdr_mdata_par_err); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_devsel_timing(unsigned int uvf_hdr_devsel_timing); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_sig_target_abort(unsigned int uvf_hdr_sig_target_abort); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_rx_target_abort(unsigned int uvf_hdr_rx_target_abort); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_rx_master_abort(unsigned int uvf_hdr_rx_master_abort); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_rx_sys_err(unsigned int uvf_hdr_rx_sys_err); +int iSetVF_PCIHDR_CMDSTS_vf_hdr_deteted_par_err(unsigned int uvf_hdr_deteted_par_err); +int iSetVF_PCIHDR_CLSREV_vf_hdr_revision_id(unsigned int uvf_hdr_revision_id); +int iSetVF_PCIHDR_CLSREV_vf_hdr_program_inf(unsigned int uvf_hdr_program_inf); +int iSetVF_PCIHDR_CLSREV_vf_hdr_sub_class_code(unsigned int uvf_hdr_sub_class_code); +int iSetVF_PCIHDR_CLSREV_vf_hdr_base_class_code(unsigned int uvf_hdr_base_class_code); +int iSetVF_PCIHDR_MISC_vf_hdr_cachlie_size(unsigned int uvf_hdr_cachlie_size); +int iSetVF_PCIHDR_MISC_vf_hdr_latency_timer(unsigned int uvf_hdr_latency_timer); +int iSetVF_PCIHDR_MISC_vf_hdr_header_type(unsigned int uvf_hdr_header_type); +int iSetVF_PCIHDR_MISC_vf_hdr_multfunc_dev(unsigned int uvf_hdr_multfunc_dev); +int iSetVF_PCIHDR_MISC_vf_hdr_bist_result(unsigned int uvf_hdr_bist_result); +int iSetVF_PCIHDR_MISC_vf_hdr_1reserved(unsigned int uvf_hdr_1reserved); +int iSetVF_PCIHDR_MISC_vf_hdr_start_bist(unsigned int uvf_hdr_start_bist); +int iSetVF_PCIHDR_MISC_vf_hdr_bist_cap(unsigned int uvf_hdr_bist_cap); +int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_type(unsigned int uvf_hdr_bar0_type); +int iSetVF_PCIHDR_BAR0_vf_hdr_3reserved(unsigned int uvf_hdr_3reserved); +int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_width(unsigned int uvf_hdr_bar0_width); +int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_prefetch_en(unsigned int uvf_hdr_bar0_prefetch_en); +int iSetVF_PCIHDR_BAR0_vf_hdr_2reserved(unsigned int uvf_hdr_2reserved); +int iSetVF_PCIHDR_BAR0_vf_hdr_bar0_addr(unsigned int uvf_hdr_bar0_addr); +int iSetVF_PCIHDR_BAR1_vf_hdr_bar1_addr(unsigned int uvf_hdr_bar1_addr); +int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_type(unsigned int uvf_hdr_bar2_type); +int iSetVF_PCIHDR_BAR2_vf_hdr_4reserved(unsigned int uvf_hdr_4reserved); +int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_width(unsigned int uvf_hdr_bar2_width); +int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_prefetch_en(unsigned int uvf_hdr_bar2_prefetch_en); +int iSetVF_PCIHDR_BAR2_vf_hdr_bar2reserved(unsigned int uvf_hdr_bar2reserved); +int iSetVF_PCIHDR_BAR2_vf_hdr_bar2_addr(unsigned int uvf_hdr_bar2_addr); +int iSetVF_PCIHDR_BAR3_vf_hdr_bar3_addr(unsigned int uvf_hdr_bar3_addr); +int iSetVF_PCIHDR_BAR4_vf_hdr_bar4_addr(unsigned int uvf_hdr_bar4_addr); +int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_type(unsigned int uvf_hdr_bar5_type); +int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_reserved1(unsigned int uvf_hdr_bar5_reserved1); +int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_width(unsigned int uvf_hdr_bar5_width); +int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_prefetch_en(unsigned int uvf_hdr_bar5_prefetch_en); +int iSetVF_PCIHDR_BAR5_vf_hdr_bar5reserved(unsigned int uvf_hdr_bar5reserved); +int iSetVF_PCIHDR_BAR5_vf_hdr_bar5_addr(unsigned int uvf_hdr_bar5_addr); +int iSetVF_PCIHDR_CBUS_PTR_vf_hdr_carbus_cis_ptr(unsigned int uvf_hdr_carbus_cis_ptr); +int iSetVF_PCIHDR_SUBSYS_vf_hdr_sys_vendor_id(unsigned int uvf_hdr_sys_vendor_id); +int iSetVF_PCIHDR_SUBSYS_vf_hdr_sub_sys_id(unsigned int uvf_hdr_sub_sys_id); +int iSetVF_PCIHDR_EXPRWM_vf_hdr_ext_rom_enable(unsigned int uvf_hdr_ext_rom_enable); +int iSetVF_PCIHDR_EXPRWM_vf_hdr_6reserved(unsigned int uvf_hdr_6reserved); +int iSetVF_PCIHDR_EXPRWM_vf_hdr_ext_rom_base_addr(unsigned int uvf_hdr_ext_rom_base_addr); +int iSetVF_PCIHDR_CAPPTR_vf_hdr_cap_ptr(unsigned int uvf_hdr_cap_ptr); +int iSetVF_PCIHDR_CAPPTR_vf_hdr_7reserved(unsigned int uvf_hdr_7reserved); +int iSetVF_PCI_RSVD_vf_hdr_8reserved(unsigned int uvf_hdr_8reserved); +int iSetVF_PCIHDR_INT_vf_hdr_int_line(unsigned int uvf_hdr_int_line); +int iSetVF_PCIHDR_INT_vf_hdr_int_pin(unsigned int uvf_hdr_int_pin); +int iSetVF_PCIHDR_INT_vf_hdr_3creserved(unsigned int uvf_hdr_3creserved); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_pci_capid(unsigned int uvf_pcap_pci_capid); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_nxt_ptr(unsigned int uvf_pcap_nxt_ptr); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_pci_cap_ver(unsigned int uvf_pcap_pci_cap_ver); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_port_type(unsigned int uvf_pcap_port_type); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_slot_implement(unsigned int uvf_pcap_slot_implement); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_int_msg_num(unsigned int uvf_pcap_int_msg_num); +int iSetVF_PCIE_CAPABILITY_HEADER_vf_pcap_15reserved(unsigned int uvf_pcap_15reserved); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_max_payload_size_support(unsigned int uvf_pcap_max_payload_size_support); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_phanotom_fun_sup(unsigned int uvf_pcap_phanotom_fun_sup); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_ext_tag_sup(unsigned int uvf_pcap_ext_tag_sup); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_ep_l0s_accept_lat(unsigned int uvf_pcap_ep_l0s_accept_lat); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_ep_l1_accept_lat(unsigned int uvf_pcap_ep_l1_accept_lat); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_undefine_04(unsigned int uvf_pcap_undefine_04); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_ro_base_err_rpt(unsigned int uvf_pcap_ro_base_err_rpt); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_0reserved(unsigned int uvf_pcap_0reserved); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_cap_slot_pwr_limit_val(unsigned int uvf_pcap_cap_slot_pwr_limit_val); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_cap_slot_pwr_sca(unsigned int uvf_pcap_cap_slot_pwr_sca); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_flr_cap(unsigned int uvf_pcap_flr_cap); +int iSetVF_DEVICE_CAPBILITY_vf_pcap_16reserved(unsigned int uvf_pcap_16reserved); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_cor_err_rpt_en(unsigned int uvf_pcap_cor_err_rpt_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_non_fat_rpt_en(unsigned int uvf_pcap_non_fat_rpt_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_fat_err_rpt_en(unsigned int uvf_pcap_fat_err_rpt_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_ur_rpt_en(unsigned int uvf_pcap_ur_rpt_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_relax_order_en(unsigned int uvf_pcap_relax_order_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_max_payload_size(unsigned int uvf_pcap_max_payload_size); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_extend_tag_en(unsigned int uvf_pcap_extend_tag_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_phatom_func_en(unsigned int uvf_pcap_phatom_func_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_aux_pwr_pm_en(unsigned int uvf_pcap_aux_pwr_pm_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_no_snoop_en(unsigned int uvf_pcap_no_snoop_en); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_max_read_req_size(unsigned int uvf_pcap_max_read_req_size); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_init_flr_reset_rwwo(unsigned int uvf_pcap_init_flr_reset_rwwo); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_cor_err_detect(unsigned int uvf_pcap_cor_err_detect); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_non_fata_detect(unsigned int uvf_pcap_non_fata_detect); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_fat_err_detect(unsigned int uvf_pcap_fat_err_detect); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_ur_detect(unsigned int uvf_pcap_ur_detect); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_aux_pwr_detect(unsigned int uvf_pcap_aux_pwr_detect); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_tlp_pending(unsigned int uvf_pcap_tlp_pending); +int iSetVF_DEVICE_CTRL_STATUS_vf_pcap_1reserved(unsigned int uvf_pcap_1reserved); +int iSetVF_LINK_CAPBILITY_vf_pcap_max_link_speed(unsigned int uvf_pcap_max_link_speed); +int iSetVF_LINK_CAPBILITY_vf_pcap_max_link_width(unsigned int uvf_pcap_max_link_width); +int iSetVF_LINK_CAPBILITY_vf_pcap_aspm_sup(unsigned int uvf_pcap_aspm_sup); +int iSetVF_LINK_CAPBILITY_vf_pcap_l0_exit_lat(unsigned int uvf_pcap_l0_exit_lat); +int iSetVF_LINK_CAPBILITY_vf_pcap_l1_exit_lat(unsigned int uvf_pcap_l1_exit_lat); +int iSetVF_LINK_CAPBILITY_vf_pcap_clock_pm(unsigned int uvf_pcap_clock_pm); +int iSetVF_LINK_CAPBILITY_vf_pcap_surprise_dn_err_rpt_cap(unsigned int uvf_pcap_surprise_dn_err_rpt_cap); +int iSetVF_LINK_CAPBILITY_vf_pcap_dl_link_act_rpt_cap(unsigned int uvf_pcap_dl_link_act_rpt_cap); +int iSetVF_LINK_CAPBILITY_vf_pcap_link_band_notice_cap(unsigned int uvf_pcap_link_band_notice_cap); +int iSetVF_LINK_CAPBILITY_vf_pcap_aspm_opt_compliance(unsigned int uvf_pcap_aspm_opt_compliance); +int iSetVF_LINK_CAPBILITY_vf_pcap_1reserved(unsigned int uvf_pcap_1reserved); +int iSetVF_LINK_CAPBILITY_vf_pcap_port_num(unsigned int uvf_pcap_port_num); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_aspm_ctrl(unsigned int uvf_pcap_aspm_ctrl); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_4reserved(unsigned int uvf_pcap_4reserved); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_rcb(unsigned int uvf_pcap_rcb); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_disable(unsigned int uvf_pcap_link_disable); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_retrain_link(unsigned int uvf_pcap_retrain_link); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_common_clk_cfg(unsigned int uvf_pcap_common_clk_cfg); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_extended_sync(unsigned int uvf_pcap_extended_sync); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_clock_pm_en(unsigned int uvf_pcap_clock_pm_en); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_hw_auto_width_dis(unsigned int uvf_pcap_hw_auto_width_dis); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_band_int_en(unsigned int uvf_pcap_link_band_int_en); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_auto_band_int_en(unsigned int uvf_pcap_link_auto_band_int_en); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_3reserved(unsigned int uvf_pcap_3reserved); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_mac_cur_link_spped(unsigned int uvf_pcap_mac_cur_link_spped); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_mac_cur_link_width(unsigned int uvf_pcap_mac_cur_link_width); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_undefined_12(unsigned int uvf_pcap_undefined_12); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_training(unsigned int uvf_pcap_link_training); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_slot_clk_cfg(unsigned int uvf_pcap_slot_clk_cfg); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_dl_cfg_link_active(unsigned int uvf_pcap_dl_cfg_link_active); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_band_status(unsigned int uvf_pcap_link_band_status); +int iSetVF_LINK_CTRL_STATUS_vf_pcap_link_auto_band_status(unsigned int uvf_pcap_link_auto_band_status); +int iSetVF_SLOT_CAPABILITY_vf_pcap_att_button_pre(unsigned int uvf_pcap_att_button_pre); +int iSetVF_SLOT_CAPABILITY_vf_pcap_pwr_ctrl_pre(unsigned int uvf_pcap_pwr_ctrl_pre); +int iSetVF_SLOT_CAPABILITY_vf_pcap_msl_sensor_pre(unsigned int uvf_pcap_msl_sensor_pre); +int iSetVF_SLOT_CAPABILITY_vf_pcap_att_indecator_pre(unsigned int uvf_pcap_att_indecator_pre); +int iSetVF_SLOT_CAPABILITY_vf_pcap_pwr_indicator_pre(unsigned int uvf_pcap_pwr_indicator_pre); +int iSetVF_SLOT_CAPABILITY_vf_pcap_hot_plug_surprise(unsigned int uvf_pcap_hot_plug_surprise); +int iSetVF_SLOT_CAPABILITY_vf_pcap_hot_plug_cap(unsigned int uvf_pcap_hot_plug_cap); +int iSetVF_SLOT_CAPABILITY_vf_pcap_slot_pwr_limit_val(unsigned int uvf_pcap_slot_pwr_limit_val); +int iSetVF_SLOT_CAPABILITY_vf_pcap_slot_pwr_limit_scale(unsigned int uvf_pcap_slot_pwr_limit_scale); +int iSetVF_SLOT_CAPABILITY_vf_pcap_elec_interlock_pre(unsigned int uvf_pcap_elec_interlock_pre); +int iSetVF_SLOT_CAPABILITY_vf_pcap_no_comman_cpled_sup(unsigned int uvf_pcap_no_comman_cpled_sup); +int iSetVF_SLOT_CAPABILITY_vf_pcap_physical_slot_num(unsigned int uvf_pcap_physical_slot_num); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_att_buttom_pre_en(unsigned int uvf_pcap_att_buttom_pre_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_fault_det_en(unsigned int uvf_pcap_pwr_fault_det_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_mrl_sensor_change_en(unsigned int uvf_pcap_mrl_sensor_change_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_presence_det_change_en(unsigned int uvf_pcap_presence_det_change_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_command_cpled_int_en(unsigned int uvf_pcap_command_cpled_int_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_hot_plug_int_en(unsigned int uvf_pcap_hot_plug_int_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_att_indicator_ctrl(unsigned int uvf_pcap_att_indicator_ctrl); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_indicator_ctrl(unsigned int uvf_pcap_pwr_indicator_ctrl); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_ctrled_ctrl(unsigned int uvf_pcap_pwr_ctrled_ctrl); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_elec_interlock_ctrl(unsigned int uvf_pcap_elec_interlock_ctrl); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_dl_state_change_en(unsigned int uvf_pcap_dl_state_change_en); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_6reserved(unsigned int uvf_pcap_6reserved); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_attention_button(unsigned int uvf_pcap_attention_button); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_pwr_fault_det(unsigned int uvf_pcap_pwr_fault_det); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_mrl_sensor_change(unsigned int uvf_pcap_mrl_sensor_change); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_presencd_det_change(unsigned int uvf_pcap_presencd_det_change); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_command_cpled(unsigned int uvf_pcap_command_cpled); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_mrl_sensor_st(unsigned int uvf_pcap_mrl_sensor_st); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_presencd_det_st(unsigned int uvf_pcap_presencd_det_st); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_elec_interlock_st(unsigned int uvf_pcap_elec_interlock_st); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_dl_state_change(unsigned int uvf_pcap_dl_state_change); +int iSetVF_SLOT_CTRL_STATUS_vf_pcap_5reserved(unsigned int uvf_pcap_5reserved); +int iSetVF_ROOT_CTRL_STATUS_vf_pcap_7reserved(unsigned int uvf_pcap_7reserved); +int iSetVF_ROOT_STATUS_vf_pcap_pme_rid(unsigned int uvf_pcap_pme_rid); +int iSetVF_ROOT_STATUS_vf_pcap_pme_status(unsigned int uvf_pcap_pme_status); +int iSetVF_ROOT_STATUS_vf_pcap_pme_pending(unsigned int uvf_pcap_pme_pending); +int iSetVF_ROOT_STATUS_vf_pcap_8reserved(unsigned int uvf_pcap_8reserved); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_cpl_timeout_range(unsigned int uvf_pcap_cpl_timeout_range); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_cpl_timeout_disable_sup(unsigned int uvf_pcap_cpl_timeout_disable_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ari_fwd_sup(unsigned int uvf_pcap_ari_fwd_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_atomicop_route_sup(unsigned int uvf_pcap_atomicop_route_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_atomic_32bit_cpl_sup(unsigned int uvf_pcap_atomic_32bit_cpl_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_atomic_64bit_cpl_sup(unsigned int uvf_pcap_atomic_64bit_cpl_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_cas_128bit_cpl_sup(unsigned int uvf_pcap_cas_128bit_cpl_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_no_roen_prpr_pass(unsigned int uvf_pcap_no_roen_prpr_pass); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ltr_mech_sup(unsigned int uvf_pcap_ltr_mech_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_tph_cpl_sup(unsigned int uvf_pcap_tph_cpl_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ln_sys_cls(unsigned int uvf_pcap_ln_sys_cls); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_sup_10bit_cpl_tag(unsigned int uvf_pcap_sup_10bit_cpl_tag); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_sup_10bit_req_tag(unsigned int uvf_pcap_sup_10bit_req_tag); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_obff_sup(unsigned int uvf_pcap_obff_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_ext_fmt_sup(unsigned int uvf_pcap_ext_fmt_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_end_end_pfx_sup(unsigned int uvf_pcap_end_end_pfx_sup); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_max_end_end_pfx(unsigned int uvf_pcap_max_end_end_pfx); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_9reserved(unsigned int uvf_pcap_9reserved); +int iSetVF_DEVICE_CAPABILITY2_vf_pcap_frs_sup(unsigned int uvf_pcap_frs_sup); +int iSetVF_DEVICE_CTRL2_vf_pcap_cpl_timeout_value(unsigned int uvf_pcap_cpl_timeout_value); +int iSetVF_DEVICE_CTRL2_vf_pcap_cpl_timeout_dis(unsigned int uvf_pcap_cpl_timeout_dis); +int iSetVF_DEVICE_CTRL2_vf_pcap_ari_fwd_en(unsigned int uvf_pcap_ari_fwd_en); +int iSetVF_DEVICE_CTRL2_vf_pcap_atomicop_req_en(unsigned int uvf_pcap_atomicop_req_en); +int iSetVF_DEVICE_CTRL2_vf_pcap_atomicop_egress_blk(unsigned int uvf_pcap_atomicop_egress_blk); +int iSetVF_DEVICE_CTRL2_vf_pcap_ido_req_en(unsigned int uvf_pcap_ido_req_en); +int iSetVF_DEVICE_CTRL2_vf_pcap_ido_cpl_en(unsigned int uvf_pcap_ido_cpl_en); +int iSetVF_DEVICE_CTRL2_vf_pcap_ltr_mech_en(unsigned int uvf_pcap_ltr_mech_en); +int iSetVF_DEVICE_CTRL2_vf_pcap_en_10bit_req_tag(unsigned int uvf_pcap_en_10bit_req_tag); +int iSetVF_DEVICE_CTRL2_vf_pcap_11reserved(unsigned int uvf_pcap_11reserved); +int iSetVF_DEVICE_CTRL2_vf_pcap_obff_en(unsigned int uvf_pcap_obff_en); +int iSetVF_DEVICE_CTRL2_vf_pcap_end_end_pfx_blk(unsigned int uvf_pcap_end_end_pfx_blk); +int iSetVF_DEVICE_CTRL2_vf_pcap_10reserved(unsigned int uvf_pcap_10reserved); +int iSetVF_LINK_CAPABILITY2_vf_pcap_13reserved(unsigned int uvf_pcap_13reserved); +int iSetVF_LINK_CAPABILITY2_vf_pcap_link_speed_sup(unsigned int uvf_pcap_link_speed_sup); +int iSetVF_LINK_CAPABILITY2_vf_pcap_cross_link_sup(unsigned int uvf_pcap_cross_link_sup); +int iSetVF_LINK_CAPABILITY2_vf_pcap_cfg_tx_lower_skp_cap(unsigned int uvf_pcap_cfg_tx_lower_skp_cap); +int iSetVF_LINK_CAPABILITY2_vf_pcap_cfg_rx_lower_skp_cap(unsigned int uvf_pcap_cfg_rx_lower_skp_cap); +int iSetVF_LINK_CAPABILITY2_vf_pcap_retimer_presence_detect(unsigned int uvf_pcap_retimer_presence_detect); +int iSetVF_LINK_CAPABILITY2_vf_pcap_retimer2_presence_detect(unsigned int uvf_pcap_retimer2_presence_detect); +int iSetVF_LINK_CAPABILITY2_vf_pcap_12reserved(unsigned int uvf_pcap_12reserved); +int iSetVF_LINK_CAPABILITY2_vf_pcap_drs_sup(unsigned int uvf_pcap_drs_sup); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_target_link_speed(unsigned int uvf_pcap_target_link_speed); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_enter_compliance(unsigned int uvf_pcap_enter_compliance); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_hw_auto_speed_dis(unsigned int uvf_pcap_hw_auto_speed_dis); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_selectable_de_emphasis(unsigned int uvf_pcap_selectable_de_emphasis); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_transmit_margin(unsigned int uvf_pcap_transmit_margin); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_enter_mod_compliance(unsigned int uvf_pcap_enter_mod_compliance); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_compliance_sos(unsigned int uvf_pcap_compliance_sos); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_compliance_preset_deemp(unsigned int uvf_pcap_compliance_preset_deemp); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_cur_deemp_level(unsigned int uvf_pcap_cur_deemp_level); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_complete(unsigned int uvf_pcap_eq_8g_complete); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_phase1_success(unsigned int uvf_pcap_eq_8g_phase1_success); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_phase2_success(unsigned int uvf_pcap_eq_8g_phase2_success); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_eq_8g_phase3_success(unsigned int uvf_pcap_eq_8g_phase3_success); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_link_8g_eq_req(unsigned int uvf_pcap_link_8g_eq_req); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_retimer_presence_detect(unsigned int uvf_pcap_retimer_presence_detect); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_retimer2_presence_detect(unsigned int uvf_pcap_retimer2_presence_detect); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_14reserved(unsigned int uvf_pcap_14reserved); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_dwstm_component_presence(unsigned int uvf_pcap_dwstm_component_presence); +int iSetVF_LINK_CTRL_STATUS2_vf_pcap_drs_msg_recved(unsigned int uvf_pcap_drs_msg_recved); +int iSetVF_SLOT_CAP_2_vf_pcap_slot_cap_2(unsigned int uvf_pcap_slot_cap_2); +int iSetVF_SLOT_CTRL_2_vf_pcap_slot_ctrl_2(unsigned int uvf_pcap_slot_ctrl_2); +int iSetVF_MSI_CAP_HEADER_vf_msicap_capability_id(unsigned int uvf_msicap_capability_id); +int iSetVF_MSI_CAP_HEADER_vf_msicap_nxt_ptr(unsigned int uvf_msicap_nxt_ptr); +int iSetVF_MSI_CAP_HEADER_vf_msicap_enable(unsigned int uvf_msicap_enable); +int iSetVF_MSI_CAP_HEADER_vf_msicap_mmc(unsigned int uvf_msicap_mmc); +int iSetVF_MSI_CAP_HEADER_vf_msicap_mme(unsigned int uvf_msicap_mme); +int iSetVF_MSI_CAP_HEADER_vf_msicap_c64(unsigned int uvf_msicap_c64); +int iSetVF_MSI_CAP_HEADER_vf_msicap_pvm(unsigned int uvf_msicap_pvm); +int iSetVF_MSI_CAP_HEADER_vf_msicap_support(unsigned int uvf_msicap_support); +int iSetVF_MSI_ADDR_vf_msicap_0reserved(unsigned int uvf_msicap_0reserved); +int iSetVF_MSI_ADDR_vf_msicap_addr(unsigned int uvf_msicap_addr); +int iSetVF_MSI_UP_ADDR_vf_msicap_uaddr(unsigned int uvf_msicap_uaddr); +int iSetVF_MSI_DATA_vf_msicap_data(unsigned int uvf_msicap_data); +int iSetVF_MSI_DATA_vf_msicap_1reserved(unsigned int uvf_msicap_1reserved); +int iSetVF_MSI_MASK_vf_msicap_mask(unsigned int uvf_msicap_mask); +int iSetVF_MSI_PENDING_vf_msicap_pend(unsigned int uvf_msicap_pend); +int iSetVF_MSIX_CAP_HEADER_vf_msixcap_capability_id(unsigned int uvf_msixcap_capability_id); +int iSetVF_MSIX_CAP_HEADER_vf_msixcap_nxt_ptr(unsigned int uvf_msixcap_nxt_ptr); +int iSetVF_MSIX_CAP_HEADER_vf_msixcap_table_size(unsigned int uvf_msixcap_table_size); +int iSetVF_MSIX_CAP_HEADER_vf_msixcap_0reserved(unsigned int uvf_msixcap_0reserved); +int iSetVF_MSIX_CAP_HEADER_vf_msixcap_func_mask(unsigned int uvf_msixcap_func_mask); +int iSetVF_MSIX_CAP_HEADER_vf_msixcap_enable(unsigned int uvf_msixcap_enable); +int iSetVF_MSIX_TABLE_vf_msixcap_table_bir(unsigned int uvf_msixcap_table_bir); +int iSetVF_MSIX_TABLE_vf_msixcap_table_ofset(unsigned int uvf_msixcap_table_ofset); +int iSetVF_MSIX_PBA_vf_msixcap_pba_bir(unsigned int uvf_msixcap_pba_bir); +int iSetVF_MSIX_PBA_vf_msixcap_pba_ofset(unsigned int uvf_msixcap_pba_ofset); +int iSetVF_PME_CAP_HEADER_vf_pmcap_capability_id(unsigned int uvf_pmcap_capability_id); +int iSetVF_PME_CAP_HEADER_vf_pmcap_nxt_ptr(unsigned int uvf_pmcap_nxt_ptr); +int iSetVF_PME_CAP_HEADER_vf_pmcap_version(unsigned int uvf_pmcap_version); +int iSetVF_PME_CAP_HEADER_vf_pmcap_clk(unsigned int uvf_pmcap_clk); +int iSetVF_PME_CAP_HEADER_vf_pmcap_0reserved(unsigned int uvf_pmcap_0reserved); +int iSetVF_PME_CAP_HEADER_vf_pmcap_device_spec_ini(unsigned int uvf_pmcap_device_spec_ini); +int iSetVF_PME_CAP_HEADER_vf_pmcap_aux_current(unsigned int uvf_pmcap_aux_current); +int iSetVF_PME_CAP_HEADER_vf_pmcap_d1_support(unsigned int uvf_pmcap_d1_support); +int iSetVF_PME_CAP_HEADER_vf_pmcap_d2_support(unsigned int uvf_pmcap_d2_support); +int iSetVF_PME_CAP_HEADER_vf_pmcap_pme_support(unsigned int uvf_pmcap_pme_support); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_pwr_status(unsigned int uvf_pmcap_pwr_status); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_3reserved(unsigned int uvf_pmcap_3reserved); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_no_soft_reset(unsigned int uvf_pmcap_no_soft_reset); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_2reserved(unsigned int uvf_pmcap_2reserved); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_pme_en(unsigned int uvf_pmcap_pme_en); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_data_sel(unsigned int uvf_pmcap_data_sel); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_data_scale(unsigned int uvf_pmcap_data_scale); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_pme_status(unsigned int uvf_pmcap_pme_status); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_1reserved(unsigned int uvf_pmcap_1reserved); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_b2_b3_n(unsigned int uvf_pmcap_b2_b3_n); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_bpcc_en(unsigned int uvf_pmcap_bpcc_en); +int iSetVF_PME_CTRL_STATUS_vf_pmcap_data(unsigned int uvf_pmcap_data); +int iSetVF_ACS_EXTENDED_CAP_HEADER_vf_acscap_id(unsigned int uvf_acscap_id); +int iSetVF_ACS_EXTENDED_CAP_HEADER_vf_acscap_version(unsigned int uvf_acscap_version); +int iSetVF_ACS_EXTENDED_CAP_HEADER_vf_acscap_nxt_ptr(unsigned int uvf_acscap_nxt_ptr); +int iSetVF_ACS_CTRL_vf_acscap_sv(unsigned int uvf_acscap_sv); +int iSetVF_ACS_CTRL_vf_acscap_tb(unsigned int uvf_acscap_tb); +int iSetVF_ACS_CTRL_vf_acscap_prr(unsigned int uvf_acscap_prr); +int iSetVF_ACS_CTRL_vf_acscap_pcr(unsigned int uvf_acscap_pcr); +int iSetVF_ACS_CTRL_vf_acscap_uf(unsigned int uvf_acscap_uf); +int iSetVF_ACS_CTRL_vf_acscap_pec(unsigned int uvf_acscap_pec); +int iSetVF_ACS_CTRL_vf_acscap_dtp(unsigned int uvf_acscap_dtp); +int iSetVF_ACS_CTRL_vf_acscap_1reserved(unsigned int uvf_acscap_1reserved); +int iSetVF_ACS_CTRL_vf_acscap_ecvs(unsigned int uvf_acscap_ecvs); +int iSetVF_ACS_CTRL_vf_acscap_sv_en(unsigned int uvf_acscap_sv_en); +int iSetVF_ACS_CTRL_vf_acscap_tb_en(unsigned int uvf_acscap_tb_en); +int iSetVF_ACS_CTRL_vf_acscap_prr_en(unsigned int uvf_acscap_prr_en); +int iSetVF_ACS_CTRL_vf_acscap_pcr_en(unsigned int uvf_acscap_pcr_en); +int iSetVF_ACS_CTRL_vf_acscap_uf_en(unsigned int uvf_acscap_uf_en); +int iSetVF_ACS_CTRL_vf_acscap_pec_en(unsigned int uvf_acscap_pec_en); +int iSetVF_ACS_CTRL_vf_acscap_dtp_en(unsigned int uvf_acscap_dtp_en); +int iSetVF_ACS_CTRL_vf_acscap_0reserved(unsigned int uvf_acscap_0reserved); +int iSetVF_TPH_EXTENDED_CAP_HEADER_vf_tphcap_id(unsigned int uvf_tphcap_id); +int iSetVF_TPH_EXTENDED_CAP_HEADER_vf_tphcap_version(unsigned int uvf_tphcap_version); +int iSetVF_TPH_EXTENDED_CAP_HEADER_vf_tphcap_nxt_ptr(unsigned int uvf_tphcap_nxt_ptr); +int iSetVF_TPH_CTRL_vf_tphcap_nsms(unsigned int uvf_tphcap_nsms); +int iSetVF_TPH_CTRL_vf_tphcap_ivms(unsigned int uvf_tphcap_ivms); +int iSetVF_TPH_CTRL_vf_tphcap_sdms(unsigned int uvf_tphcap_sdms); +int iSetVF_TPH_CTRL_vf_tphcap_resvdp0(unsigned int uvf_tphcap_resvdp0); +int iSetVF_TPH_CTRL_vf_tphcap_etrs(unsigned int uvf_tphcap_etrs); +int iSetVF_TPH_CTRL_vf_tphcap_stl(unsigned int uvf_tphcap_stl); +int iSetVF_TPH_CTRL_vf_tphcap_resvdp1(unsigned int uvf_tphcap_resvdp1); +int iSetVF_TPH_CTRL_vf_tphcap_st_tbl_size(unsigned int uvf_tphcap_st_tbl_size); +int iSetVF_TPH_CTRL_vf_tphcap_resvdp2(unsigned int uvf_tphcap_resvdp2); +int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_sms(unsigned int uvf_tphcap_sms); +int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_resvdp3(unsigned int uvf_tphcap_resvdp3); +int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_tre(unsigned int uvf_tphcap_tre); +int iSetVF_TPH_EGRESS_CTRL0_vf_tphcap_resvdp4(unsigned int uvf_tphcap_resvdp4); +int iSetVF_ARI_CAP_HEADER_vf_aricap_id(unsigned int uvf_aricap_id); +int iSetVF_ARI_CAP_HEADER_vf_aricap_version(unsigned int uvf_aricap_version); +int iSetVF_ARI_CAP_HEADER_vf_aricap_nxt_ptr(unsigned int uvf_aricap_nxt_ptr); +int iSetVF_ARI_CTRL_vf_aricap_mfvc_func_grp_cap(unsigned int uvf_aricap_mfvc_func_grp_cap); +int iSetVF_ARI_CTRL_vf_aricap_acs_func_grp_cap(unsigned int uvf_aricap_acs_func_grp_cap); +int iSetVF_ARI_CTRL_vf_aricap_2reserved(unsigned int uvf_aricap_2reserved); +int iSetVF_ARI_CTRL_vf_aricap_nxt_func_num(unsigned int uvf_aricap_nxt_func_num); +int iSetVF_ARI_CTRL_vf_aricap_mfvc_func_grp_en(unsigned int uvf_aricap_mfvc_func_grp_en); +int iSetVF_ARI_CTRL_vf_aricap_acs_func_grp_en(unsigned int uvf_aricap_acs_func_grp_en); +int iSetVF_ARI_CTRL_vf_aricap_1reserved(unsigned int uvf_aricap_1reserved); +int iSetVF_ARI_CTRL_vf_aricap_func_group(unsigned int uvf_aricap_func_group); +int iSetVF_ARI_CTRL_vf_aricap_0reserved(unsigned int uvf_aricap_0reserved); + + +#endif // __HVA_PEH_C_UNION_DEFINE_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/hva_peh_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/hva_peh_reg_offset.h new file mode 100644 index 000000000..622299d75 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/hva_peh_reg_offset.h @@ -0,0 +1,214 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : hva_peh_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2021/04/08 19:34:52 Create file +// ****************************************************************************** + +#ifndef HVA_PEH_REG_OFFSET_H +#define HVA_PEH_REG_OFFSET_H + +/* PEH_PF_REGS Base address of Module's Register */ +#define CSR_PEH_PF_REGS_BASE (0x43FF000) + +/* **************************************************************************** */ +/* PEH_PF_REGS Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PEH_PF_REGS_PCIHDR_ID_REG \ + (CSR_PEH_PF_REGS_BASE + 0x0) /* This register specify the register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_CMDSTS_REG \ + (CSR_PEH_PF_REGS_BASE + 0x4) /* This register specify the register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_CLSREV_REG \ + (CSR_PEH_PF_REGS_BASE + 0x8) /* This register specify the register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_MISC_REG \ + (CSR_PEH_PF_REGS_BASE + 0xC) /* This register specify the register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_BAR0_REG \ + (CSR_PEH_PF_REGS_BASE + 0x10) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_BAR1_REG \ + (CSR_PEH_PF_REGS_BASE + 0x14) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_BAR2_REG \ + (CSR_PEH_PF_REGS_BASE + 0x18) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_BAR3_REG \ + (CSR_PEH_PF_REGS_BASE + 0x1C) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_BAR4_REG \ + (CSR_PEH_PF_REGS_BASE + 0x20) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_BAR5_REG \ + (CSR_PEH_PF_REGS_BASE + 0x24) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_CBUS_PTR_REG \ + (CSR_PEH_PF_REGS_BASE + 0x28) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_SUBSYS_REG \ + (CSR_PEH_PF_REGS_BASE + 0x2C) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_EXPRWM_REG \ + (CSR_PEH_PF_REGS_BASE + 0x30) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIHDR_CAPPTR_REG \ + (CSR_PEH_PF_REGS_BASE + 0x34) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCI_RSVD_REG (CSR_PEH_PF_REGS_BASE + 0x38) /* reserved */ +#define CSR_PEH_PF_REGS_PCIHDR_INT_REG \ + (CSR_PEH_PF_REGS_BASE + 0x3C) /* This register specify the base address register of config space. */ +#define CSR_PEH_PF_REGS_PCIE_CAPABILITY_HEADER_REG \ + (CSR_PEH_PF_REGS_BASE + 0x40) /* This is the pcie capability header register */ +#define CSR_PEH_PF_REGS_DEVICE_CAPBILITY_REG \ + (CSR_PEH_PF_REGS_BASE + 0x44) /* This register describe the device capability */ +#define CSR_PEH_PF_REGS_DEVICE_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x48) /* device control status register */ +#define CSR_PEH_PF_REGS_LINK_CAPBILITY_REG (CSR_PEH_PF_REGS_BASE + 0x4C) /* Link capability register */ +#define CSR_PEH_PF_REGS_LINK_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x50) /* Link control register */ +#define CSR_PEH_PF_REGS_SLOT_CAPABILITY_REG (CSR_PEH_PF_REGS_BASE + 0x54) /* Slot capability register */ +#define CSR_PEH_PF_REGS_SLOT_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x58) /* Slot control and status register */ +#define CSR_PEH_PF_REGS_ROOT_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x5C) /* Root control status */ +#define CSR_PEH_PF_REGS_ROOT_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x60) /* Root status register */ +#define CSR_PEH_PF_REGS_DEVICE_CAPABILITY2_REG (CSR_PEH_PF_REGS_BASE + 0x64) /* device capability 2 register */ +#define CSR_PEH_PF_REGS_DEVICE_CTRL2_REG (CSR_PEH_PF_REGS_BASE + 0x68) /* Device control register 2 */ +#define CSR_PEH_PF_REGS_LINK_CAPABILITY2_REG (CSR_PEH_PF_REGS_BASE + 0x6C) /* Link capability 2 */ +#define CSR_PEH_PF_REGS_LINK_CTRL_STATUS2_REG (CSR_PEH_PF_REGS_BASE + 0x70) /* Link control and status 2 */ +#define CSR_PEH_PF_REGS_SLOT_CAP_2_REG (CSR_PEH_PF_REGS_BASE + 0x74) /* Slot Capabilities 2 Register */ +#define CSR_PEH_PF_REGS_SLOT_CTRL_2_REG (CSR_PEH_PF_REGS_BASE + 0x78) /* Slot Control 2 Register */ +#define CSR_PEH_PF_REGS_MSI_CAP_HEADER_REG \ + (CSR_PEH_PF_REGS_BASE + 0x80) /* MSI Capability Header and Message Control register */ +#define CSR_PEH_PF_REGS_MSI_ADDR_REG (CSR_PEH_PF_REGS_BASE + 0x84) /* Message Address Register for MSI */ +#define CSR_PEH_PF_REGS_MSI_UP_ADDR_REG (CSR_PEH_PF_REGS_BASE + 0x88) /* Message Upper Address Register for MSI */ +#define CSR_PEH_PF_REGS_MSI_DATA_REG (CSR_PEH_PF_REGS_BASE + 0x8C) /* Message Data Register for MSI */ +#define CSR_PEH_PF_REGS_MSI_MASK_REG (CSR_PEH_PF_REGS_BASE + 0x90) /* Mask Bits Register for MSI */ +#define CSR_PEH_PF_REGS_MSI_PENDING_REG (CSR_PEH_PF_REGS_BASE + 0x94) /* Pending Bits Register for MSI */ +#define CSR_PEH_PF_REGS_MSIX_CAP_HEADER_REG \ + (CSR_PEH_PF_REGS_BASE + 0xA0) /* MSI-X Capability Header and Message Control register */ +#define CSR_PEH_PF_REGS_MSIX_TABLE_REG (CSR_PEH_PF_REGS_BASE + 0xA4) /* Table Offset/Table BIR Register for MSI-X */ +#define CSR_PEH_PF_REGS_MSIX_PBA_REG (CSR_PEH_PF_REGS_BASE + 0xA8) /* PBA Offset/PBA BIR Register for MSI-X */ +#define CSR_PEH_PF_REGS_PME_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0xB0) /* PME capability header and PME control */ +#define CSR_PEH_PF_REGS_PME_CTRL_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0xB4) /* Power management status register */ +#define CSR_PEH_PF_REGS_ACS_EXTENDED_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x100) /* ACS Extended capability header \ + */ +#define CSR_PEH_PF_REGS_ACS_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x104) /* ACS Control Register */ +#define CSR_PEH_PF_REGS_SRIOV_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x200) /* SRIOV capability header */ +#define CSR_PEH_PF_REGS_SRIOV_CAP_REG (CSR_PEH_PF_REGS_BASE + 0x204) /* SRIOV capability */ +#define CSR_PEH_PF_REGS_SRIOV_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x208) /* SRIOV control register */ +#define CSR_PEH_PF_REGS_INIT_VF_NUMBER_REG (CSR_PEH_PF_REGS_BASE + 0x20C) /* Initial VF and Totla VF */ +#define CSR_PEH_PF_REGS_FUNC_DEP_VF_NUM_REG (CSR_PEH_PF_REGS_BASE + 0x210) /* Function dependency link and VF NUMBER \ + */ +#define CSR_PEH_PF_REGS_VF_RID_SETTING_REG (CSR_PEH_PF_REGS_BASE + 0x214) /* First offset and Stride register */ +#define CSR_PEH_PF_REGS_VF_DEVICE_ID_REG (CSR_PEH_PF_REGS_BASE + 0x218) /* VF device ID */ +#define CSR_PEH_PF_REGS_VF_PAGE_SIZE_REG (CSR_PEH_PF_REGS_BASE + 0x21C) /* supported Page Size */ +#define CSR_PEH_PF_REGS_SYSTEM_PAGE_SIZE_REG (CSR_PEH_PF_REGS_BASE + 0x220) /* System page size */ +#define CSR_PEH_PF_REGS_VF_BAR0_REG (CSR_PEH_PF_REGS_BASE + 0x224) /* Virtual function Base address 0 register */ +#define CSR_PEH_PF_REGS_VF_BAR1_REG (CSR_PEH_PF_REGS_BASE + 0x228) /* Virtual function Base address 1 register */ +#define CSR_PEH_PF_REGS_VF_BAR2_REG (CSR_PEH_PF_REGS_BASE + 0x22C) /* Virtual function Base address 2 register */ +#define CSR_PEH_PF_REGS_VF_BAR3_REG (CSR_PEH_PF_REGS_BASE + 0x230) /* Virtual function Base address 3 register */ +#define CSR_PEH_PF_REGS_VF_BAR4_REG (CSR_PEH_PF_REGS_BASE + 0x234) /* Virtual function Base address 4 register */ +#define CSR_PEH_PF_REGS_VF_BAR5_REG (CSR_PEH_PF_REGS_BASE + 0x238) /* Virtual function Base address 5 register */ +#define CSR_PEH_PF_REGS_VF_MIG_STATE_ARRAY_REG (CSR_PEH_PF_REGS_BASE + 0x23C) /* VF Migration state array offset */ +#define CSR_PEH_PF_REGS_TPH_EXTENDED_CAP_HEADER_REG \ + (CSR_PEH_PF_REGS_BASE + 0x300) /* TPH Requester Extended Capability Header */ +#define CSR_PEH_PF_REGS_TPH_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x304) /* TPH Requester Capability Register */ +#define CSR_PEH_PF_REGS_TPH_EGRESS_CTRL0_REG (CSR_PEH_PF_REGS_BASE + 0x308) /* TPH Requester Control Register */ +#define CSR_PEH_PF_REGS_PASID_EXTENDED_CAP_HEADER_REG \ + (CSR_PEH_PF_REGS_BASE + 0x320) /* PASID Requester Extended Capability Header */ +#define CSR_PEH_PF_REGS_PASID_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x324) /* PASID Requester Capability Register */ +#define CSR_PEH_PF_REGS_AER_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x400) /* Advance Error Report capability header */ +#define CSR_PEH_PF_REGS_UNCR_ERR_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x404) /* uncorrectable error status */ +#define CSR_PEH_PF_REGS_UNCR_ERR_MASK_REG (CSR_PEH_PF_REGS_BASE + 0x408) /* uncorrectable error mask */ +#define CSR_PEH_PF_REGS_UNCR_ERR_SEVERITY_REG (CSR_PEH_PF_REGS_BASE + 0x40C) /* uncorrectable error serverity */ +#define CSR_PEH_PF_REGS_COR_ERR_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x410) /* Correctable error status */ +#define CSR_PEH_PF_REGS_COR_ERR_MASK_REG (CSR_PEH_PF_REGS_BASE + 0x414) /* correctable error mask */ +#define CSR_PEH_PF_REGS_ADVACD_CAP_CTRL_REG \ + (CSR_PEH_PF_REGS_BASE + 0x418) /* advanced error capabilities and control register */ +#define CSR_PEH_PF_REGS_FIRST_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x41C) /* First DW header log */ +#define CSR_PEH_PF_REGS_SECOND_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x420) /* Second DW header log */ +#define CSR_PEH_PF_REGS_THIRD_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x424) /* Third DW header log */ +#define CSR_PEH_PF_REGS_FOUR_HEADER_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x428) /* Forth DW header log */ +#define CSR_PEH_PF_REGS_RWOT_ERRWR_COMMAND_REG (CSR_PEH_PF_REGS_BASE + 0x42C) /* Root error report command */ +#define CSR_PEH_PF_REGS_RWOT_ERRWR_STATUS_REG (CSR_PEH_PF_REGS_BASE + 0x430) /* Roor Error status */ +#define CSR_PEH_PF_REGS_ERR_SOURCE_IDEN_REG (CSR_PEH_PF_REGS_BASE + 0x434) /* Erorr soure identification register */ +#define CSR_PEH_PF_REGS_FIRST_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x438) /* First DW prefix log */ +#define CSR_PEH_PF_REGS_SECOND_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x43C) /* Second DW prefix log */ +#define CSR_PEH_PF_REGS_THIRD_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x440) /* Third DW prefix log */ +#define CSR_PEH_PF_REGS_FOUR_PREFIX_LOG_REG (CSR_PEH_PF_REGS_BASE + 0x444) /* Forth DW prefix log */ +#define CSR_PEH_PF_REGS_ARI_CAP_HEADER_REG (CSR_PEH_PF_REGS_BASE + 0x450) /* ARI capability header */ +#define CSR_PEH_PF_REGS_ARI_CTRL_REG (CSR_PEH_PF_REGS_BASE + 0x454) /* ARI control and capability */ + +/* PEH_VF_REGS Base address of Module's Register */ +#define CSR_PEH_VF_REGS_BASE (0x0) + +/* **************************************************************************** */ +/* PEH_VF_REGS Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PEH_VF_REGS_VF_PCIHDR_ID_REG \ + (CSR_PEH_VF_REGS_BASE + 0x0) /* This register specify the register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_CMDSTS_REG \ + (CSR_PEH_VF_REGS_BASE + 0x4) /* This register specify the register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_CLSREV_REG \ + (CSR_PEH_VF_REGS_BASE + 0x8) /* This register specify the register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_MISC_REG \ + (CSR_PEH_VF_REGS_BASE + 0xC) /* This register specify the register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR0_REG \ + (CSR_PEH_VF_REGS_BASE + 0x10) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR1_REG \ + (CSR_PEH_VF_REGS_BASE + 0x14) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR2_REG \ + (CSR_PEH_VF_REGS_BASE + 0x18) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR3_REG \ + (CSR_PEH_VF_REGS_BASE + 0x1C) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR4_REG \ + (CSR_PEH_VF_REGS_BASE + 0x20) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_BAR5_REG \ + (CSR_PEH_VF_REGS_BASE + 0x24) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_CBUS_PTR_REG \ + (CSR_PEH_VF_REGS_BASE + 0x28) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_SUBSYS_REG \ + (CSR_PEH_VF_REGS_BASE + 0x2C) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_EXPRWM_REG \ + (CSR_PEH_VF_REGS_BASE + 0x30) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_CAPPTR_REG \ + (CSR_PEH_VF_REGS_BASE + 0x34) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCI_RSVD_REG (CSR_PEH_VF_REGS_BASE + 0x38) /* reserved */ +#define CSR_PEH_VF_REGS_VF_PCIHDR_INT_REG \ + (CSR_PEH_VF_REGS_BASE + 0x3C) /* This register specify the base address register of config space. */ +#define CSR_PEH_VF_REGS_VF_PCIE_CAPABILITY_HEADER_REG \ + (CSR_PEH_VF_REGS_BASE + 0x40) /* This is the pcie capability header register */ +#define CSR_PEH_VF_REGS_VF_DEVICE_CAPBILITY_REG \ + (CSR_PEH_VF_REGS_BASE + 0x44) /* This register describe the device capability */ +#define CSR_PEH_VF_REGS_VF_DEVICE_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x48) /* device control status register */ +#define CSR_PEH_VF_REGS_VF_LINK_CAPBILITY_REG (CSR_PEH_VF_REGS_BASE + 0x4C) /* Link capability register */ +#define CSR_PEH_VF_REGS_VF_LINK_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x50) /* Link control register */ +#define CSR_PEH_VF_REGS_VF_SLOT_CAPABILITY_REG (CSR_PEH_VF_REGS_BASE + 0x54) /* Slot capability register */ +#define CSR_PEH_VF_REGS_VF_SLOT_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x58) /* Slot control and status register */ +#define CSR_PEH_VF_REGS_VF_ROOT_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x5C) /* Roor control status */ +#define CSR_PEH_VF_REGS_VF_ROOT_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0x60) /* Root status register */ +#define CSR_PEH_VF_REGS_VF_DEVICE_CAPABILITY2_REG (CSR_PEH_VF_REGS_BASE + 0x64) /* device capability 2 register */ +#define CSR_PEH_VF_REGS_VF_DEVICE_CTRL2_REG (CSR_PEH_VF_REGS_BASE + 0x68) /* Device control register 2 */ +#define CSR_PEH_VF_REGS_VF_LINK_CAPABILITY2_REG (CSR_PEH_VF_REGS_BASE + 0x6C) /* Link capability 2 */ +#define CSR_PEH_VF_REGS_VF_LINK_CTRL_STATUS2_REG (CSR_PEH_VF_REGS_BASE + 0x70) /* Link control and status 2 */ +#define CSR_PEH_VF_REGS_VF_SLOT_CAP_2_REG (CSR_PEH_VF_REGS_BASE + 0x74) /* Slot Capabilities 2 Register */ +#define CSR_PEH_VF_REGS_VF_SLOT_CTRL_2_REG (CSR_PEH_VF_REGS_BASE + 0x78) /* Slot Control 2 Register */ +#define CSR_PEH_VF_REGS_VF_MSI_CAP_HEADER_REG \ + (CSR_PEH_VF_REGS_BASE + 0x80) /* MSI Capability Header and Message Control register */ +#define CSR_PEH_VF_REGS_VF_MSI_ADDR_REG (CSR_PEH_VF_REGS_BASE + 0x84) /* Message Address Register for MSI */ +#define CSR_PEH_VF_REGS_VF_MSI_UP_ADDR_REG (CSR_PEH_VF_REGS_BASE + 0x88) /* Message Upper Address Register for MSI */ +#define CSR_PEH_VF_REGS_VF_MSI_DATA_REG (CSR_PEH_VF_REGS_BASE + 0x8C) /* Message Data Register for MSI */ +#define CSR_PEH_VF_REGS_VF_MSI_MASK_REG (CSR_PEH_VF_REGS_BASE + 0x90) /* Mask Bits Register for MSI */ +#define CSR_PEH_VF_REGS_VF_MSI_PENDING_REG (CSR_PEH_VF_REGS_BASE + 0x94) /* Pending Bits Register for MSI */ +#define CSR_PEH_VF_REGS_VF_MSIX_CAP_HEADER_REG \ + (CSR_PEH_VF_REGS_BASE + 0xA0) /* MSI-X Capability Header and Message Control register */ +#define CSR_PEH_VF_REGS_VF_MSIX_TABLE_REG (CSR_PEH_VF_REGS_BASE + 0xA4) /* Table Offset/Table BIR Register for MSI-X \ + */ +#define CSR_PEH_VF_REGS_VF_MSIX_PBA_REG (CSR_PEH_VF_REGS_BASE + 0xA8) /* PBA Offset/PBA BIR Register for MSI-X */ +#define CSR_PEH_VF_REGS_VF_PME_CAP_HEADER_REG (CSR_PEH_VF_REGS_BASE + 0xB0) /* PME capability header and PME control \ + */ +#define CSR_PEH_VF_REGS_VF_PME_CTRL_STATUS_REG (CSR_PEH_VF_REGS_BASE + 0xB4) /* Power management status register */ +#define CSR_PEH_VF_REGS_VF_ACS_EXTENDED_CAP_HEADER_REG \ + (CSR_PEH_VF_REGS_BASE + 0x100) /* ACS Extended capability header */ +#define CSR_PEH_VF_REGS_VF_ACS_CTRL_REG (CSR_PEH_VF_REGS_BASE + 0x104) /* ACS Control Register */ +#define CSR_PEH_VF_REGS_VF_TPH_EXTENDED_CAP_HEADER_REG \ + (CSR_PEH_VF_REGS_BASE + 0x300) /* TPH Requester Extended Capability Header */ +#define CSR_PEH_VF_REGS_VF_TPH_CTRL_REG (CSR_PEH_VF_REGS_BASE + 0x304) /* TPH Requester Capability Register */ +#define CSR_PEH_VF_REGS_VF_TPH_EGRESS_CTRL0_REG (CSR_PEH_VF_REGS_BASE + 0x308) /* TPH Requester Control Register */ +#define CSR_PEH_VF_REGS_VF_ARI_CAP_HEADER_REG (CSR_PEH_VF_REGS_BASE + 0x450) /* ARI capability header */ +#define CSR_PEH_VF_REGS_VF_ARI_CTRL_REG (CSR_PEH_VF_REGS_BASE + 0x454) /* ARI control and capability */ + +#endif // HVA_PEH_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_ap_addr_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_ap_addr_define.h new file mode 100644 index 000000000..66565cf2e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_ap_addr_define.h @@ -0,0 +1,40529 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : pcie5_ap_addr_define.h + * Project line : Platform And Key Technologies Development + * Department : CAD Development Department + * Version : 1.0 + * Date : + * Description : The description of xxx project + * Others : Generated automatically by nManager V5.1 + * History : 2021/01/12 16:18:01 Create file + */ + +#ifndef PCIE5_AP_ADDR_DEFINE_H +#define PCIE5_AP_ADDR_DEFINE_H + +/* HIPCIEC50_AP_IOB_TX_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_BASE (0x0) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_IOB_TX_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_0_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x0) /* IOB TX address translation unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_0_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x20) /* IOB TX address translation unit control register0.Common information. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_0_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x40) /* IOB TX address translation unit control register0.Common information. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_0_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x60) /* IOB TX address translation unit control register0.Common information. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_0_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x80) /* IOB TX address translation unit control register0.Common information. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_0_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0xA0) /* IOB TX address translation unit control register0.Common information. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_2_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x8) /* IOB TX address translation unit control information register2.Extend the IOB_TXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_2_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x28) /* IOB TX address translation unit control information register2.Extend the IOB_TXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_2_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x48) /* IOB TX address translation unit control information register2.Extend the IOB_TXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_2_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x68) /* IOB TX address translation unit control information register2.Extend the IOB_TXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_2_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x88) /* IOB TX address translation unit control information register2.Extend the IOB_TXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_CONTROL_2_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0xA8) /* IOB TX address translation unit control information register2.Extend the IOB_TXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_REGION_SIZE_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC) /* IOB TX address translation unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_REGION_SIZE_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C) /* IOB TX address translation unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_REGION_SIZE_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x4C) /* IOB TX address translation unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_REGION_SIZE_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x6C) /* IOB TX address translation unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_REGION_SIZE_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8C) /* IOB TX address translation unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_REGION_SIZE_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xAC) /* IOB TX address translation unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_L_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x10) /* IOB TX address translation unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_L_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x30) /* IOB TX address translation unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_L_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x50) /* IOB TX address translation unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_L_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x70) /* IOB TX address translation unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_L_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x90) /* IOB TX address translation unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_L_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0xB0) /* IOB TX address translation unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_H_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x14) /* IOB TX address translation unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_H_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x34) /* IOB TX address translation unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_H_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x54) /* IOB TX address translation unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_H_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x74) /* IOB TX address translation unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_H_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x94) /* IOB TX address translation unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_BASE_ADDR_H_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xB4) /* IOB TX address translation unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_L_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x18) /* IOB TX address translation unit target address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_L_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x38) /* IOB TX address translation unit target address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_L_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x58) /* IOB TX address translation unit target address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_L_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x78) /* IOB TX address translation unit target address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_L_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x98) /* IOB TX address translation unit target address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_L_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0xB8) /* IOB TX address translation unit target address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_H_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1C) /* IOB TX address translation unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_H_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3C) /* IOB TX address translation unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_H_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x5C) /* IOB TX address translation unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_H_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x7C) /* IOB TX address translation unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_H_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x9C) /* IOB TX address translation unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TXATU_TAR_ADDR_H_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xBC) /* IOB TX address translation unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_ECAM_CONTROL0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x600) /* IOB TX ECAM control register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_ECAM_CONTROL1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x604) /* IOB TX ECAM control register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_ECAM_BASE_ADDR_L_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x608) /* IOB TX ECAM base address low 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_ECAM_BASE_ADDR_H_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x60C) /* IOB TX ECAM base address high 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_BASE_BUS_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x610) /* IOB TX BASE BUS for CXL Device RCiEP CfgSpace */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_BASE_BUS_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x630) /* IOB TX BASE BUS for CXL Device RCiEP CfgSpace */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_RCRB_BASE_L_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x614) /* IOB TX CXL RCRB BASE ADDR low 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_RCRB_BASE_L_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x634) /* IOB TX CXL RCRB BASE ADDR low 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_RCRB_BASE_H_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x618) /* IOB TX CXL RCRB BASE ADDR high 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_RCRB_BASE_H_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x638) /* IOB TX CXL RCRB BASE ADDR high 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_DP_MEMBAR_MASK_L_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x61C) /* IOB TX CXL DP MEMBAR0 mask register low 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_DP_MEMBAR_MASK_L_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x63C) /* IOB TX CXL DP MEMBAR0 mask register low 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_DP_MEMBAR_MASK_H_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x620) /* IOB TX CXL DP MEMBAR0 mask register high 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CXL_DP_MEMBAR_MASK_H_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x640) /* IOB TX CXL DP MEMBAR0 mask register high 32bit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_EP_REMAP_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x680) /* IOB TX EP Address remap control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_MSK0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x800) /* IOB_TX interrupt mask register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_MSK1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x804) /* IOB_TX interrupt mask register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_MSK2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x808) /* IOB_TX interrupt mask register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_MSK3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x80C) /* IOB_TX interrupt mask register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_STATUS0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x820) /* IOB_TX interrupt status register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_STATUS1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x824) /* IOB_TX interrupt status register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_STATUS2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x828) /* IOB_TX interrupt status register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_STATUS3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x82C) /* IOB_TX interrupt status register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x840) /* IOB_TX interrupt read only status register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x844) /* IOB_TX interrupt read only status register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x848) /* IOB_TX interrupt read only status register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x84C) /* IOB_TX interrupt read only status register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SET0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x860) /* IOB_TX interrupt set register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SET1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x864) /* IOB_TX interrupt set register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SET2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x868) /* IOB_TX interrupt set register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SET3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x86C) /* IOB_TX interrupt set register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SEVERITY0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x880) /* IOB TX interrupt severity register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SEVERITY1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x884) /* IOB TX interrupt severity register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SEVERITY2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x888) /* IOB TX interrupt severity register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_SEVERITY3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x88C) /* IOB TX interrupt severity register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_CE0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8A0) /* IOB_TX correctable error interrupt read only status register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_CE1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8A4) /* IOB_TX correctable error interrupt read only status register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_CE2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8A8) /* IOB_TX correctable error interrupt read only status register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_CE3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8AC) /* IOB_TX correctable error interrupt read only status register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_NFE0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8C0) /* IOB_TX nonfatal error interrupt read only status register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_NFE1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8C4) /* IOB_TX nonfatal error interrupt read only status register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_NFE2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8C8) /* IOB_TX nonfatal error interrupt read only status register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_NFE3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8CC) /* IOB_TX nonfatal error interrupt read only status register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_FE0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8E0) /* IOB_TX fatal error interrupt read only status register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_FE1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8E4) /* IOB_TX fatal error interrupt read only status register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_FE2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8E8) /* IOB_TX fatal error interrupt read only status register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_INT_RO_FE3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x8EC) /* IOB_TX fatal error interrupt read only status register3 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_REQ_TOUT_NOTIFY_MSK_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x980) /* IOB TX request timeout notify the Physical Layer mask register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DAT_BUF_ECC_ERR_INJECT_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xA00) /* IOB TX data buffer ecc injection register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DAT_BUF_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xA04) /* IOB TX data buffer ecc error address register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DAT_BUF_ECC_ERR_CNT_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xA08) /* IOB TX data buffer ecc error counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_AXIS_CONTROL0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC00) /* iob_tx_axis_control_0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_AXIS_CONTROL1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC04) /* iob_tx_axis_control_1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_AXIS_CONTROL2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC08) /* iob_tx_axis_control_2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_AXIS_CREDIT_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC10) /* axis credit cnt control */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_AXIS_CREDIT_TH_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC14) /* axis credit cnt width */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_AXIS_RPLC_DATA_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0xC20) /* axis repair rdata for unusual cpl */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_P_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1000) /* The start and end address of P private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_P_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1010) /* The start and end address of P private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_P_PRI_RGN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1020) /* The start and end address of P private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_P_PRI_RGN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1030) /* The start and end address of P private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_NP_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1004) /* The start and end address of NP private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_NP_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1014) /* The start and end address of NP private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_NP_PRI_RGN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1024) /* The start and end address of NP private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_NP_PRI_RGN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1034) /* The start and end address of NP private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_CPL_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1008) /* The start and end address of CPL private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_CPL_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1018) /* The start and end address of CPL private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_CPL_PRI_RGN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1028) /* The start and end address of CPL private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_CPL_PRI_RGN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1038) /* The start and end address of CPL private space for port region n(n=0~3) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_ALL_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1080) /* The start address and end address of all shared space in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_P_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1084) /* The start and end address of P shared space in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_NP_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1088) /* The start and end address of NP shared space in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_CPL_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x108C) /* The start and end address of CPL shared space in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_SRC_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x10A0) /* The start and end address of source private region n(n=0~15) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_DBUF_SRC_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x10A4) /* The start and end address of source private region n(n=0~15) in data buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_P_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1100) /* The start and end address of P private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_P_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1110) /* The start and end address of P private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_P_PRI_RGN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1120) /* The start and end address of P private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_P_PRI_RGN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1130) /* The start and end address of P private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_NP_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1104) /* The start and end address of NP private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_NP_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1114) /* The start and end address of NP private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_NP_PRI_RGN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1124) /* The start and end address of NP private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_NP_PRI_RGN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1134) /* The start and end address of NP private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_CPL_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1108) /* The start and end address of CPL private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_CPL_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1118) /* The start and end address of CPL private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_CPL_PRI_RGN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1128) /* The start and end address of CPL private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_CPL_PRI_RGN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1138) /* The start and end address of CPL private space for port region n(n=0~3) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_ALL_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1180) /* The start address and end address of all shared space in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_P_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1184) /* The start and end address of P shared space in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_NP_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1188) /* The start and end address of NP shared space in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_CPL_SHR_RGN_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x118C) /* The start and end address of CPL shared space in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_SRC_PRI_RGN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x11A0) /* The start and end address of source private region n(n=0~15) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_HBUF_SRC_PRI_RGN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x11A4) /* The start and end address of source private region n(n=0~15) in header buffer. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_ALC_BUF_REQ_WRR_WGT_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1200) /* allocation buffer requests wrr weight register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_REQ_QUE_RETRY_TH_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1204) /* the water level of request queue. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_REQ_QUE_TIMEOUT_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1208) /* request queue timeout control register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_SRC_PRI_RGN_MAP_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x120C) /* source private region mapping register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_REQ_TIMER_CFG_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1300) /* TQM Request timeout timer threshold */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_REQ_TIMER_UNIT_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1340) /* TQM Request timeout timer unit */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TLP_CDT_CLR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1400) /* TQM TLP credit clear register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TLP_CDT_CLR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1410) /* TQM TLP credit clear register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TLP_CDT_CLR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1420) /* TQM TLP credit clear register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TLP_CDT_CLR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1430) /* TQM TLP credit clear register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CFG0_CDT_CLR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1440) /* TQM Cfg0 credit clear register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_CDT_ACTIVE_MSK_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1444) /* TQM credit mask register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_BA_TIMER_CFG_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1800) /* TCS Buffer Allocate timeout release timer threshold */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_BA_COUNTER_CFG_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1804) /* TCS Buffer Allocate pre allocate times threshold */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_BA_PRE_SIZE_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1808) /* TCS pre allocate buf control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_BA_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x180C) /* TCS avaliable allocated buffer threshold register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_REQ_HALT_TIMER_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1810) /* TCS request halt timer register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_LINK_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1820) /* TCS CHI interface link interaction control register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_DEC_ERR_INFO_L_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1840) /* TCS decode error information register low 32bit register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_DEC_ERR_INFO_H_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1844) /* TCS decode error information register high 32bit register.. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_ETH_PORT_NUM_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1850) /* TCS Through Port Number register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_BT_TH_SRICD_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1858) /* TCS BT Through srcdi regsiter. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_ORDER_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1860) /* TCS ordering control regsiter */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_RESP_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x1880) /* CHI bus return Compdata or Comp Flit RespErr field control register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_RESP_VID_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1884) /* CfgRd read vendor ID behavior control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_RDATA_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1888) /* CHI Bus return CompData data payload control register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_RPLC_DATA_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x188C) /* CHI Bus return CompData replaced data payload. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_POISON_FORWARD_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1890) /* CHI Bus return CompData poison bit control register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_POISON_CTRL_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x18A0) /* CHI Bus receive Poisoned DataFlit behavior control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_POISON_CTRL_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x18B0) /* CHI Bus receive Poisoned DataFlit behavior control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_POISON_CTRL_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x18C0) /* CHI Bus receive Poisoned DataFlit behavior control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_POISON_CTRL_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x18D0) /* CHI Bus receive Poisoned DataFlit behavior control register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_MISC_CTRL0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1900) /* TCS misc ctrl0 register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_IOB_TX_TCS_MISC_CTRL1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x1904) /* TCS misc ctrl1 register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_IDLE_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2000) /* AP_IOB_TX idle status */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_WR_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2400) /* DFX iob_tx_axis wr counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_WR_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2404) /* DFX iob_tx_axis wr counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_WR_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2408) /* DFX iob_tx_axis wr counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_WR_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x240C) /* DFX iob_tx_axis wr counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_WR_CNT_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2410) /* DFX iob_tx_axis wr counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_WR_CNT_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2414) /* DFX iob_tx_axis wr counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_RD_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2440) /* DFX iob_tx_axis rd counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_RD_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2444) /* DFX iob_tx_axis rd counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_STATUS0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2480) /* DFX iob_tx_axis debug info register0 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_STATUS1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2484) /* DFX iob_tx_axis debug info register1 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_STATUS2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2488) /* DFX iob_tx_axis debug info register2 */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_ABNORMAL_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2500) /* DFX iob_tx_axis abnormal counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_ABNORMAL_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2504) /* DFX iob_tx_axis abnormal counter registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_AXIS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2580) /* DFX iob_tx_axis control registers */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_P_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2800) /* The statistic DFX of Post TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_P_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2804) /* The statistic DFX of Post TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_NP_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2880) /* The statistic DFX of NonPost TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_NP_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2884) /* The statistic DFX of NonPost TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_NP_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2888) /* The statistic DFX of NonPost TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_NP_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x288C) /* The statistic DFX of NonPost TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_NP_CNT_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2890) /* The statistic DFX of NonPost TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_NP_CNT_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2894) /* The statistic DFX of NonPost TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_CPL_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2900) /* The statistic DFX of Completion TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_CPL_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2904) /* The statistic DFX of Completion TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_CPL_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2908) /* The statistic DFX of Completion TLP */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_REQ_CNT_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x2980) /* The statistic DFX of Post and NonPost in TypeA interface data channel */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29A0) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29A4) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29A8) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29AC) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29B0) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29B4) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_6_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29B8) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_7_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29BC) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAR_CNT_8_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29C0) /* The statistic DFX of source allocation buffer request and release buffer request. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29D0) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29D4) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29D8) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29DC) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29E0) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29E4) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_6_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29E8) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_7_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29EC) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ARR_CNT_8_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + \ + 0x29F0) /* The statistic DFX of source allocation buffer response and retried. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_STATUS0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A00) /* The status0 of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_STATUS1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A04) /* The status1 of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_STATUS2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A08) /* The status2 of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_STATUS3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A0C) /* The status3 of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_STATUS4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A10) /* The status4 of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_STATUS5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A14) /* The status5 of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_FIFO_STATUS_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2A80) /* The FIFO status of TQM */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAS_STATUS0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2B00) /* The status 0 of BAS. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAS_STATUS1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2B04) /* The status 1 of BAS. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAS_STATUS2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2B08) /* The status 2 of BAS. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ABNORMAL_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C00) /* The statistic of abnormal event. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ABNORMAL_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C04) /* The statistic of abnormal event. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ABNORMAL_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C08) /* The statistic of abnormal event. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ABNORMAL_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C0C) /* The statistic of abnormal event. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ERROR0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C80) /* The error indication of the TQM. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_ERROR1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2C84) /* The error indication of the TQM. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_CTRL0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2E00) /* The DFX control0 register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_CTRL1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2E04) /* The DFX control1 register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_BAS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x2E10) /* The DFX control register of BAS. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3000) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3004) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3008) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x300C) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3010) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3014) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_6_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3018) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_7_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x301C) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_8_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3020) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_9_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3024) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_10_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3028) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_11_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x302C) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_12_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3030) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_13_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3034) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_14_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3038) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_NORMAL_CNT_15_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x303C) /* The TCS DFX normal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3080) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3084) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3088) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_3_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x308C) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_4_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3090) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_5_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3094) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_6_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3098) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_P2P_CNT_7_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x309C) /* The TCS DFX P2P counter register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_ARNORAML_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3100) /* The TCS DFX abnormal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_ARNORAML_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3104) /* The TCS DFX abnormal counter register. */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_ERROR_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3180) /* The TCS DFX error status */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_STATUS0_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3200) /* The TCS DFX status0 register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_STATUS1_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3204) /* The TCS DFX status1 register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_STATUS2_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3208) /* The TCS DFX status2 register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_IDLE_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3240) /* The TCS Idle register */ +#define CSR_HIPCIEC50_AP_IOB_TX_REG_DFX_IOB_TX_TCS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_TX_REG_BASE + 0x3300) /* The TCS DFX control */ + +/* HIPCIEC50_AP_IOB_RX_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_BASE (0x4000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_IOB_RX_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_0_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x0) /* IOB RX address transition unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_0_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x20) /* IOB RX address transition unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_0_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x40) /* IOB RX address transition unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_0_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x60) /* IOB RX address transition unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_0_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x80) /* IOB RX address transition unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_0_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xA0) /* IOB RX address transition unit control register0.Common information. \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_1_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_1_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x24) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_1_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x44) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_1_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x64) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_1_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x84) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_1_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0xA4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_2_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_2_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x28) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_2_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x48) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_2_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x68) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_2_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0x88) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_CONTROL_2_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + \ + 0xA8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_REGION_SIZE_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_REGION_SIZE_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_REGION_SIZE_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x4C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_REGION_SIZE_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x6C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_REGION_SIZE_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x8C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_REGION_SIZE_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xAC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_L_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x10) /* IOB RX address transition unit base address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_L_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x30) /* IOB RX address transition unit base address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_L_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x50) /* IOB RX address transition unit base address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_L_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x70) /* IOB RX address transition unit base address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_L_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x90) /* IOB RX address transition unit base address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_L_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xB0) /* IOB RX address transition unit base address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_H_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x14) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_H_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x34) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_H_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x54) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_H_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x74) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_H_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x94) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_BASE_ADDR_H_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xB4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_L_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x18) /* IOB RX address transition unit target address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_L_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x38) /* IOB RX address transition unit target address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_L_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x58) /* IOB RX address transition unit target address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_L_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x78) /* IOB RX address transition unit target address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_L_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x98) /* IOB RX address transition unit target address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_L_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xB8) /* IOB RX address transition unit target address low 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_H_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_H_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x3C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_H_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x5C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_H_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x7C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_H_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x9C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RXATU_TAR_ADDR_H_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xBC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_CFG_IB_BAR_DISP_SEL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xE04) /* Forward config based on BAR_NUM */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_FILTER_MODE_EP_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xE10) /* IB Filter mode control in EP mode */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_NVME_REG_REMAP_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xE20) /* NVME Register Access remap control 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_NVME_REG_REMAP_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xE24) /* NVME Register Access remap control 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_DMA_REG_REMAP_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xE30) /* DMA Register Access remap control 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_DMA_REG_REMAP_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0xE34) /* DMA Register Access remap control 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AXICACHE_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1000) /* AXI CACHE Control */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_ORDER_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1020) /* Ordering control in AP IOB_RX */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_POST_POISON_FORWARD_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1030) /* Poison posted request forward control register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_POISON_FORWARD_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1034) /* Poison request forward control register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_INT_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1040) /* Received MSI/MSIX Interrrupt contorl */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_INT_ADDR_HIGH_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1044) /* Received MSI/MSIX Interrrupt Address Window high */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_INT_ADDR_LOW_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1048) /* Received MSI/MSIX Interrrupt Address Window low */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_INT_PROT_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x10E0) /* MSI/MSIX Interrupt protect control */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_ITF_CRD_ATU_ACTIVE_DISABLE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x10E4) /* Disable control for the active signal of the interface */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_RC_ATU_ADDR_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x10E8) /* IOB RX address transition unit base address/target addr in RC mode \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_DATA_BUFFER_SIZE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x10EC) /* inbound data buffer size */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_RX_REQ_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1500) /* DFX counter for RX received request from TL */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_LOC_REQ_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1504) /* DFX counter for local request from inner module */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_SEND_AM_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1510) /* DFX counter of the request sent to AXI Master */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_SEND_LOC_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1514) /* DFX counter of the request not sent to AXI Master */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_DMA_CPL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1518) /* DFX counter of the CPL belong to DMA */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_RESP_RX_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1540) /* DFX counter of the response to TL */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_RESP_LOC_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1544) /* DFX counter of the response to inner module */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_RESP_RECV_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1550) /* DFX counter of the response from several destination */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_CNT_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x15F0) /* DFX conter control for IOB_RX */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_MSK_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1700) /* IOB_RX interrupt mask register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_STATUS_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1704) /* IOB_RX interrupt status register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_RO_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1708) /* IOB_RX interrupt read only status register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_SET_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x170C) /* IOB_RX interrupt set register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_SEVERITY_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1710) /* IOB_RX interrupt severity register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_RO_CE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1714) /* IOB_RX correctable error interrupt read only status register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_RO_NFE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1718) /* IOB_RX non-fatal error interrupt read only status register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_INT_RO_FE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x171C) /* IOB_RX fatal error interrupt read only status register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_GLOBAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1800) /* Global Control of IOB_RX AML */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_MAX_TRANS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1804) /* MAX outstanding control */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_QOS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1810) /* QOS control for AXI Master Request */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_WR_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1820) /* Write channel control of IOB_RX AML */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_RD_CTRL_REG (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1840) +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_ERR_RESP_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x18E0) /* AXI Error response control */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_ERR_WDATA_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x18E4) /* Error WDATA control */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_IDLE_STATE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A00) /* Idle state of the IOB_RX AML */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_MAX_TRANS_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A04) /* Max outstanding number */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_ITF_STS_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A08) /* State of the AXI Master Interface */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_TBL_PTR_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A10) /* Pointer of the ID table */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_WR_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A20) /* DFX counter 0 of the wirte operation */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_WR_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A24) /* DFX counter 1 of the write operation */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_RD_CNT_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A28) /* DFX counter of the read operation */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_AW_LAT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A40) /* Write request latency DFX 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_AW_LAT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A44) /* Write request latency DFX 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_AR_LAT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A48) /* Read request latency DFX 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_AR_LAT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A4C) /* Read request latency DFX 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_ERR_STS_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A60) /* Error state of the AML */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_WR_ID_STS_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A80) /* Write request ID state 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_WR_ID_STS_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A84) /* Write request ID state 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_RD_ID_STS_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A90) /* Read request ID state 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AML_RD_ID_STS_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A94) /* Read request ID state 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_STRMID_RD_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A98) /* IOB_RX_AML_STRMID */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_STRMID_WR_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1A9C) /* IOB_RX_AML_STRMID */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_AXUSER_CTRL1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1AA0) /* IOB_RX_AML_AXUSER */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_AXUSER_CTRL2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1AA4) /* IOB_RX_AML_AXUSER */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_AXUSER_CTRL3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1AA8) /* IOB_RX_AML_STASH */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AML_SNOOP_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1AAC) /* IOB_RX_AML_SNOOP */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_GLOBAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C00) /* Global Control Register of AXI Master Bridge */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_MAX_TRANS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C04) /* Maximum transaction outstanding control Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_QOS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C08) /* QOS control Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_ATOP_ENDIAN_FORMAT_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C10) /* Endian Format Control of inbound atomic operation */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_SAFETY_LEVEL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C14) /* Safety level control for AXI transaction */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_ARUSER_MODE_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C20) /* AXIM aruser mode control for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_ARUSER_SET_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C24) /* AXIM aruser value control 0 for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_ARUSER_SET_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C28) /* AXIM aruser value control 1 for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_ARUSER_SET_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C2C) /* AXIM aruser value control 2 for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_AWUSER_MODE_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C30) /* AXIM awuser mode control for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_AWUSER_SET_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C34) /* AXIM awuser value control 0 for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_AWUSER_SET_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C38) /* AXIM awuser value control 1 for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_AWUSER_SET_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1C3C) /* AXIM awuser value control 2 for AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_ERR_RESP_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1CE0) /* Error response control Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_AMB_ERR_WDATA_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1CE4) /* Error write data control */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_CNT_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E00) /* DFX counter control in AMB */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_WR_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E20) /* Counter 0 of write transaction */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_WR_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E24) /* Counter 1 of write transaction */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_RD_CNT_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E28) /* Counter 0 of read transaction */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_RD_CNT_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E2C) /* Counter 1 of read transaction */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_ATOP_CNT_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E30) /* Counter for atomic operation */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_INT_NUM_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E34) /* Counter for MSI/MSI-X Interrupt */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_DFX_IOB_RX_AMB_INT_RATE_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x1E38) /* MSI/MSI-X Interrupt rate */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_PAB_GLOBAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2000) /* PA Buffer global control register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_PAB_SMMU_BYPASS_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2004) /* smmu bypass enable for each port configuration register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_PAB_P2P_CTRL_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2020) /* P2P control register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_CTRL_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2200) /* MSI/MSI-X Interrupt Address Window Contol Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_CTRL_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2210) /* MSI/MSI-X Interrupt Address Window Contol Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_CTRL_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2220) /* MSI/MSI-X Interrupt Address Window Contol Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_CTRL_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2230) /* MSI/MSI-X Interrupt Address Window Contol Register */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2204) /* MSI/MSI-X Interrupt Address Configuration Register 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2214) /* MSI/MSI-X Interrupt Address Configuration Register 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2224) /* MSI/MSI-X Interrupt Address Configuration Register 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_HIGH_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2234) /* MSI/MSI-X Interrupt Address Configuration Register 0 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_LOW_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2208) /* MSI/MSI-X Interrupt Address Configuration Register 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_LOW_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2218) /* MSI/MSI-X Interrupt Address Configuration Register 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_LOW_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2228) /* MSI/MSI-X Interrupt Address Configuration Register 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MSI_MSIX_ADDR_LOW_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2238) /* MSI/MSI-X Interrupt Address Configuration Register 1 */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2300) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2310) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2320) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2330) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2340) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2350) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_6_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2360) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_EN_7_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2370) /* Enable control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2304) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2314) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2324) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2334) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2344) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2354) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_6_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2364) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ATTR_7_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2374) /* Cache attribute configuration for memory attribute address window \ + */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2308) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2318) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2328) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2338) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2348) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2358) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_6_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2368) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_ADDR_7_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x2378) /* Address configuration for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_0_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x230C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_1_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x231C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_2_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x232C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_3_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x233C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_4_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x234C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_5_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x235C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_6_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x236C) /* Mask control for memory attribute address window */ +#define CSR_HIPCIEC50_AP_IOB_RX_REG_IOB_RX_MEMATTR_WIN_MASK_7_REG \ + (CSR_HIPCIEC50_AP_IOB_RX_REG_BASE + 0x237C) /* Mask control for memory attribute address window */ + +/* HIPCIEC50_AP_P2P_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_BASE (0xC0000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_P2P_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_0_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_2_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_3_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_4_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x104) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_5_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x144) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_6_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x184) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_7_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_8_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x204) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_9_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x244) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_10_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x284) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_11_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_12_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x304) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_13_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x344) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_14_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x384) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_15_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_16_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x404) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_17_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x444) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_18_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x484) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_19_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_20_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x504) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_21_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x544) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_22_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x584) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_23_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_24_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x604) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_25_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x644) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_26_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x684) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_27_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_28_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x704) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_29_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x744) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_30_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x784) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_31_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_32_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x804) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_33_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x844) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_34_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x884) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_35_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_36_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x904) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_37_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x944) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_38_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x984) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_39_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_40_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA04) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_41_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_42_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_43_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_44_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB04) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_45_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_46_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_47_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_48_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC04) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_49_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_50_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_51_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_52_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD04) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_53_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_54_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_55_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_56_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE04) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_57_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_58_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_59_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_60_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF04) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_61_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF44) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_62_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF84) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_63_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_64_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1004) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_65_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1044) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_66_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1084) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_67_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_68_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1104) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_69_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1144) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_70_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1184) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_71_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_72_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1204) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_73_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1244) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_74_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1284) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_75_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_76_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1304) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_77_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1344) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_78_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1384) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_79_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_80_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1404) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_81_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1444) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_82_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1484) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_83_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_84_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1504) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_85_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1544) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_86_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1584) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_87_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_88_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1604) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_89_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1644) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_90_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1684) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_91_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_92_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1704) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_93_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1744) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_94_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1784) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_95_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_96_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1804) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_97_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1844) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_98_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1884) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_99_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18C4) /* Command Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_100_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_101_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_102_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_103_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_104_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_105_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_106_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_107_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_108_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_109_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_110_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_111_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_112_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_113_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_114_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_115_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_116_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_117_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_118_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_119_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_120_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_121_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_122_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_123_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_124_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_125_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_126_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_127_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_128_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_129_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_130_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_131_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_132_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_133_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_134_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_135_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_136_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_137_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_138_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_139_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_140_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_141_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_142_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_143_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_144_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_145_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_146_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_147_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_148_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_149_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_150_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_151_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_152_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_153_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_154_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_155_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_156_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_157_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_158_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_159_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_160_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_161_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_162_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_163_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_164_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_165_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_166_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_167_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_168_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_169_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_170_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_171_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_172_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_173_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_174_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_175_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_176_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_177_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_178_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_179_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_180_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_181_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_182_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_183_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_184_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_185_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_186_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_187_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_188_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_189_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_190_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_191_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_192_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_193_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_194_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_195_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_196_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_197_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_198_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_199_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_200_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_201_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_202_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_203_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_204_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_205_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_206_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_207_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_208_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_209_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_210_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_211_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_212_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_213_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_214_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_215_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_216_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_217_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_218_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_219_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_220_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_221_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_222_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_223_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_224_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_225_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_226_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_227_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_228_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_229_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_230_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_231_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_232_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_233_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_234_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_235_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_236_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_237_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_238_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_239_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_240_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_241_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_242_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_243_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_244_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_245_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_246_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_247_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_248_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_249_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_250_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_251_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_252_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_253_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_254_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_255_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_256_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_257_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_258_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_259_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_260_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_261_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_262_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_263_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_264_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_265_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_266_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_267_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_268_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_269_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_270_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_271_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_272_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_273_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_274_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_275_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_276_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_277_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_278_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_279_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_280_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_281_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_282_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_283_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_284_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_285_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_286_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_287_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_288_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_289_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_290_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_291_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_292_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_293_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_294_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_295_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_296_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_297_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_298_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_299_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_300_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_301_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_302_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_303_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_304_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_305_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_306_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_307_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_308_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_309_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_310_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_311_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_312_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_313_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_314_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_315_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_316_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_317_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_318_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_319_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_320_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_321_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_322_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_323_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_324_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_325_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_326_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_327_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_328_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_329_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_330_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_331_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_332_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_333_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_334_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_335_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_336_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_337_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_338_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_339_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_340_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_341_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_342_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_343_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_344_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_345_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_346_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_347_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_348_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_349_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_350_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_351_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_352_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_353_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_354_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_355_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_356_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_357_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_358_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_359_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_360_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_361_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_362_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_363_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_364_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_365_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_366_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_367_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_368_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_369_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_370_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_371_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_372_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_373_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_374_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_375_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_376_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_377_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_378_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_379_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_380_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_381_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_382_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_383_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_384_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_385_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_386_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_387_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_388_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_389_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_390_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_391_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_392_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_393_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_394_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_395_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_396_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_397_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_398_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_399_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_400_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_401_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_402_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_403_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_404_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_405_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_406_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_407_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_408_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_409_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_410_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_411_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_412_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_413_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_414_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_415_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_416_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_417_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_418_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_419_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_420_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_421_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_422_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_423_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_424_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_425_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_426_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_427_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_428_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_429_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_430_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_431_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_432_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_433_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_434_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_435_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_436_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_437_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_438_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_439_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_440_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_441_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_442_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_443_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_444_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_445_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_446_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_447_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_448_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_449_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_450_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_451_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_452_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_453_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_454_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_455_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_456_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_457_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_458_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_459_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_460_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_461_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_462_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_463_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_464_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_465_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_466_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_467_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_468_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_469_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_470_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_471_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_472_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_473_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_474_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_475_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_476_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_477_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_478_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_479_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_480_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_481_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_482_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_483_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_484_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_485_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_486_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_487_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_488_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_489_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_490_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_491_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_492_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_493_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_494_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_495_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_496_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_497_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_498_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_499_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_500_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_501_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_502_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_503_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_504_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_505_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_506_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_507_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_508_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_509_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_510_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_511_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_512_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_513_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_514_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_515_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_516_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_517_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_518_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_519_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_520_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_521_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_522_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_523_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_524_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_525_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_526_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_527_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_528_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_529_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_530_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_531_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_532_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_533_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_534_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_535_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_536_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_537_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_538_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_539_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_540_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_541_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_542_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_543_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_544_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_545_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_546_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_547_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_548_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_549_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_550_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_551_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_552_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_553_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_554_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_555_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_556_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_557_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_558_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_559_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_560_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_561_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_562_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_563_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_564_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_565_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_566_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_567_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_568_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_569_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_570_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_571_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_572_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_573_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_574_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_575_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_576_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_577_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_578_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_579_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_580_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_581_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_582_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_583_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_584_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_585_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_586_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_587_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_588_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_589_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_590_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_591_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_592_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_593_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_594_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_595_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_596_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_597_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_598_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_599_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_600_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_601_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_602_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_603_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_604_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_605_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_606_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_607_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_608_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_609_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_610_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_611_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_612_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_613_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_614_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_615_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_616_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_617_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_618_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_619_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_620_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_621_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_622_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_623_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_624_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_625_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_626_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_627_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_628_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_629_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_630_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_631_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_632_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_633_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_634_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_635_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_636_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_637_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_638_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_639_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_640_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_641_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_642_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_643_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_644_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_645_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_646_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_647_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_648_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_649_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_650_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_651_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_652_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_653_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_654_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_655_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_656_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_657_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_658_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_659_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_660_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_661_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_662_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_663_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_664_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_665_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_666_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_667_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_668_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_669_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_670_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_671_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_672_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_673_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_674_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_675_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_676_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_677_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_678_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_679_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_680_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_681_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_682_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_683_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_684_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_685_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_686_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_687_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_688_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_689_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_690_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_691_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_692_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_693_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_694_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_695_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_696_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_697_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_698_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_699_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_700_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_701_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_702_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_703_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_704_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_705_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_706_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_707_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_708_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_709_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_710_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_711_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_712_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_713_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_714_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_715_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_716_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_717_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_718_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_719_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_720_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_721_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_722_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_723_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_724_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_725_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_726_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_727_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_728_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_729_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_730_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_731_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_732_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_733_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_734_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_735_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_736_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_737_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_738_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_739_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_740_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_741_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_742_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_743_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_744_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_745_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_746_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_747_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_748_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_749_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_750_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_751_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_752_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_753_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_754_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_755_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_756_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_757_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_758_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_759_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_760_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_761_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_762_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_763_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_764_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_765_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_766_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_767_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_768_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_769_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_770_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_771_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_772_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_773_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_774_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_775_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_776_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_777_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_778_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_779_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_780_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_781_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_782_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_783_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_784_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_785_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_786_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_787_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_788_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_789_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_790_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_791_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_792_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_793_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_794_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_795_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_796_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_797_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_798_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_799_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_800_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_801_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_802_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_803_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_804_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_805_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_806_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_807_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_808_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_809_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_810_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_811_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_812_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_813_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_814_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_815_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_816_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_817_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_818_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_819_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_820_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_821_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_822_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_823_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_824_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_825_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_826_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_827_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_828_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_829_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_830_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_831_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_832_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_833_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_834_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_835_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_836_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_837_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_838_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_839_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_840_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_841_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_842_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_843_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_844_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_845_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_846_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_847_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_848_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_849_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_850_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_851_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_852_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_853_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_854_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_855_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_856_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_857_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_858_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_859_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_860_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_861_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_862_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_863_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_864_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_865_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_866_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_867_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_868_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_869_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_870_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_871_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_872_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_873_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_874_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_875_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_876_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_877_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_878_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_879_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_880_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_881_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_882_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_883_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_884_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_885_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_886_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_887_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_888_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_889_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_890_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_891_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_892_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_893_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_894_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_895_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_896_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_897_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_898_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_899_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_900_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_901_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_902_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_903_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_904_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_905_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_906_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_907_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_908_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_909_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_910_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_911_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_912_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_913_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_914_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_915_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_916_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_917_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_918_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_919_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_920_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_921_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_922_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_923_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_924_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_925_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_926_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_927_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_928_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_929_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_930_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_931_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_932_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_933_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_934_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_935_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_936_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_937_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_938_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_939_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_940_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_941_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_942_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_943_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_944_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_945_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_946_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_947_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_948_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_949_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_950_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_951_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_952_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_953_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_954_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_955_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_956_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_957_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_958_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_959_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_960_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF004) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_961_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF044) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_962_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF084) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_963_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_964_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF104) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_965_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF144) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_966_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF184) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_967_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_968_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF204) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_969_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF244) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_970_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF284) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_971_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_972_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF304) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_973_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF344) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_974_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF384) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_975_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_976_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF404) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_977_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF444) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_978_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF484) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_979_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_980_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF504) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_981_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF544) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_982_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF584) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_983_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_984_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF604) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_985_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF644) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_986_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF684) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_987_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_988_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF704) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_989_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF744) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_990_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF784) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_991_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_992_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF804) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_993_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF844) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_994_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF884) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_995_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_996_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF904) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_997_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF944) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_998_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF984) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_999_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9C4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1000_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1001_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1002_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1003_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1004_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1005_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1006_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1007_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1008_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1009_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1010_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1011_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1012_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1013_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1014_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1015_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1016_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1017_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1018_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1019_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1020_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF04) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1021_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF44) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1022_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF84) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_COMMAND_1023_REG (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFC4) /* Command Register \ + */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9ED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF018) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF058) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF098) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF118) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF158) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF198) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF218) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF258) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF298) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF318) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF358) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF398) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF418) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF458) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF498) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF518) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF558) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF598) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF618) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF658) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF698) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF718) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF758) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF798) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF818) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF858) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF898) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF918) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF958) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF998) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9D8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFED8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF18) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF58) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF98) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_BUS_NUMBER_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFD8) /* Bus Number Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x101C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x105C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x109C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x111C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x115C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x119C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x121C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x125C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x129C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x131C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x135C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x139C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x141C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x145C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x149C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x151C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x155C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x159C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x161C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x165C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x169C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x171C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x175C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x179C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x181C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x185C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x189C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x191C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x195C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x199C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x201C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x205C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x209C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x211C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x215C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x219C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x221C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x225C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x229C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x231C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x235C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x239C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x241C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x245C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x249C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x251C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x255C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x259C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x261C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x265C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x269C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x271C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x275C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x279C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x281C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x285C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x289C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x291C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x295C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x299C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x301C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x305C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x309C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x311C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x315C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x319C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x321C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x325C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x329C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x331C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x335C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x339C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x341C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x345C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x349C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x351C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x355C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x359C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x361C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x365C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x369C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x371C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x375C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x379C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x381C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x385C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x389C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x391C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x395C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x399C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x401C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x405C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x409C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x411C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x415C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x419C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x421C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x425C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x429C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x431C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x435C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x439C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x441C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x445C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x449C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x451C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x455C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x459C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x461C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x465C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x469C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x471C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x475C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x479C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x481C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x485C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x489C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x491C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x495C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x499C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x501C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x505C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x509C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x511C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x515C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x519C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x521C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x525C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x529C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x531C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x535C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x539C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x541C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x545C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x549C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x551C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x555C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x559C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x561C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x565C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x569C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x571C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x575C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x579C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x581C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x585C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x589C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x591C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x595C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x599C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x601C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x605C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x609C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x611C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x615C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x619C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x621C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x625C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x629C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x631C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x635C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x639C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x641C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x645C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x649C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x651C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x655C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x659C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x661C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x665C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x669C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x671C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x675C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x679C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x681C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x685C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x689C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x691C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x695C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x699C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x701C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x705C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x709C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x711C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x715C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x719C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x721C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x725C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x729C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x731C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x735C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x739C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x741C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x745C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x749C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x751C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x755C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x759C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x761C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x765C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x769C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x771C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x775C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x779C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x781C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x785C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x789C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x791C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x795C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x799C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x801C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x805C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x809C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x811C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x815C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x819C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x821C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x825C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x829C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x831C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x835C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x839C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x841C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x845C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x849C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x851C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x855C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x859C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x861C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x865C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x869C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x871C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x875C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x879C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x881C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x885C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x889C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x891C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x895C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x899C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x901C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x905C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x909C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x911C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x915C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x919C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x921C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x925C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x929C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x931C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x935C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x939C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x941C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x945C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x949C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x951C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x955C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x959C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x961C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x965C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x969C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x971C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x975C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x979C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x981C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x985C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x989C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x991C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x995C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x999C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9ADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA01C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA05C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA09C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB01C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB05C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB09C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC01C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC05C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC09C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD01C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD05C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD09C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE01C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE05C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE09C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF01C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF05C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF09C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF11C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF15C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF19C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF21C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF25C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF29C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF31C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF35C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF39C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF41C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF45C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF49C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF51C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF55C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF59C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF61C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF65C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF69C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF71C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF75C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF79C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF81C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF85C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF89C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF91C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF95C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF99C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9DC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFADC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF1C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF5C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF9C) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_IO_RANGE_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFDC) /* I/O Address Range Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF020) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF060) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF120) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF160) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF220) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF260) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF320) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF360) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF420) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF460) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF520) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF560) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF620) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF660) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF720) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF760) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF820) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF860) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF920) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF960) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9A0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9E0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF20) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF60) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFA0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_MEM_RANGE_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFE0) /* Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF024) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF064) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF124) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF164) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF224) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF264) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF324) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF364) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF424) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF464) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF524) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF564) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF624) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF664) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF724) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF764) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF824) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF864) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF924) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF964) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9A4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9E4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF24) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF64) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFA4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_RANGE_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFE4) /* Prefetchable Memory Address Range Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF028) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF068) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF128) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF168) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF228) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF268) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF328) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF368) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF428) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF468) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF528) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF568) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF628) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF668) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF728) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF768) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF828) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF868) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF928) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF968) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9A8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9E8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF28) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF68) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFA8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_BASE_UPPER_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFE8) /* Prefetchable Base Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x102C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x106C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x112C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x116C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x122C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x126C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x132C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x136C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x142C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x146C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x152C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x156C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x162C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x166C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x172C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x176C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x182C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x186C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x192C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x196C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x202C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x206C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x212C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x216C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x222C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x226C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x232C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x236C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x242C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x246C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x252C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x256C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x262C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x266C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x272C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x276C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x282C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x286C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x292C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x296C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x302C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x306C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x312C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x316C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x322C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x326C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x332C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x336C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x342C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x346C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x352C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x356C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x362C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x366C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x372C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x376C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x382C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x386C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x392C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x396C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x402C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x406C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x412C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x416C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x422C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x426C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x432C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x436C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x442C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x446C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x452C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x456C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x462C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x466C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x472C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x476C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x482C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x486C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x492C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x496C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x502C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x506C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x512C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x516C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x522C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x526C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x532C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x536C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x542C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x546C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x552C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x556C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x562C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x566C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x572C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x576C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x582C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x586C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x592C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x596C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x602C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x606C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x612C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x616C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x622C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x626C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x632C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x636C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x642C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x646C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x652C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x656C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x662C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x666C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x672C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x676C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x682C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x686C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x692C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x696C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x702C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x706C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x712C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x716C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x722C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x726C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x732C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x736C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x742C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x746C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x752C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x756C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x762C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x766C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x772C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x776C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x782C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x786C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x792C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x796C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x802C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x806C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x812C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x816C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x822C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x826C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x832C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x836C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x842C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x846C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x852C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x856C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x862C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x866C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x872C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x876C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x882C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x886C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x892C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x896C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x902C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x906C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x912C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x916C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x922C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x926C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x932C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x936C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x942C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x946C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x952C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x956C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x962C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x966C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x972C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x976C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x982C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x986C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x992C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x996C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA02C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA06C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB02C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB06C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC02C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC06C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD02C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD06C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE02C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE06C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF02C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF06C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF12C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF16C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF22C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF26C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF32C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF36C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF42C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF46C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF52C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF56C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF62C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF66C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF72C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF76C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF82C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF86C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF92C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF96C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9AC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9EC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF2C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF6C) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFAC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IB_P2P_PREF_MEM_LIMIT_UPPER_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFEC) /* Prefetchable Limit Memory Upper Address Register */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_0_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_2_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_3_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_4_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_5_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_6_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_7_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_8_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_9_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_10_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_11_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_12_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_13_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_14_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_15_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_16_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_17_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_18_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_19_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_20_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_21_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_22_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_23_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_24_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_25_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_26_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_27_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_28_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_29_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_30_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_31_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_32_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_33_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_34_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_35_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_36_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_37_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_38_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_39_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_40_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_41_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_42_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_43_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_44_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_45_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_46_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_47_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_48_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_49_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_50_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_51_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_52_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_53_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_54_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_55_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_56_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_57_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_58_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_59_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_60_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_61_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_62_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_63_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_64_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_65_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_66_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_67_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x10F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_68_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_69_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_70_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_71_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x11F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_72_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_73_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_74_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_75_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x12F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_76_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_77_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_78_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_79_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x13F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_80_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_81_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_82_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_83_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x14F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_84_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_85_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_86_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_87_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x15F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_88_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_89_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_90_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_91_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x16F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_92_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_93_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_94_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_95_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x17F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_96_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_97_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_98_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_99_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x18F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_100_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_101_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_102_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_103_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x19F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_104_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_105_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_106_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_107_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_108_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_109_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_110_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_111_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_112_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_113_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_114_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_115_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_116_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_117_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_118_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_119_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_120_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_121_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_122_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_123_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_124_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_125_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_126_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_127_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x1FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_128_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_129_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_130_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_131_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x20F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_132_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_133_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_134_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_135_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x21F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_136_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_137_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_138_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_139_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x22F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_140_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_141_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_142_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_143_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x23F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_144_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_145_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_146_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_147_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x24F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_148_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_149_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_150_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_151_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x25F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_152_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_153_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_154_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_155_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x26F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_156_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_157_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_158_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_159_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x27F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_160_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_161_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_162_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_163_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x28F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_164_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_165_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_166_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_167_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x29F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_168_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_169_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_170_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_171_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_172_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_173_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_174_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_175_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_176_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_177_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_178_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_179_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_180_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_181_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_182_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_183_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_184_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_185_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_186_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_187_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_188_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_189_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_190_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_191_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x2FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_192_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_193_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_194_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_195_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x30F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_196_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_197_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_198_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_199_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x31F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_200_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_201_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_202_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_203_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x32F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_204_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_205_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_206_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_207_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x33F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_208_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_209_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_210_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_211_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x34F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_212_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_213_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_214_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_215_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x35F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_216_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_217_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_218_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_219_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x36F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_220_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_221_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_222_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_223_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x37F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_224_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_225_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_226_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_227_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x38F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_228_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_229_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_230_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_231_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x39F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_232_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_233_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_234_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_235_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_236_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_237_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_238_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_239_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_240_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_241_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_242_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_243_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_244_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_245_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_246_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_247_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_248_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_249_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_250_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_251_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_252_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_253_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_254_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_255_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x3FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_256_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_257_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_258_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_259_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x40F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_260_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_261_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_262_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_263_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x41F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_264_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_265_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_266_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_267_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x42F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_268_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_269_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_270_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_271_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x43F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_272_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_273_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_274_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_275_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x44F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_276_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_277_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_278_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_279_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x45F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_280_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_281_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_282_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_283_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x46F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_284_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_285_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_286_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_287_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x47F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_288_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_289_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_290_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_291_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x48F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_292_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_293_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_294_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_295_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x49F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_296_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_297_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_298_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_299_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_300_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_301_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_302_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_303_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_304_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_305_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_306_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_307_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_308_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_309_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_310_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_311_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_312_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_313_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_314_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_315_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_316_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_317_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_318_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_319_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x4FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_320_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_321_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_322_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_323_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x50F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_324_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_325_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_326_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_327_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x51F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_328_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_329_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_330_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_331_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x52F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_332_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_333_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_334_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_335_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x53F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_336_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_337_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_338_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_339_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x54F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_340_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_341_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_342_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_343_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x55F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_344_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_345_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_346_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_347_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x56F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_348_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_349_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_350_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_351_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x57F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_352_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_353_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_354_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_355_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x58F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_356_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_357_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_358_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_359_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x59F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_360_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_361_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_362_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_363_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_364_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_365_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_366_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_367_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_368_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_369_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_370_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_371_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_372_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_373_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_374_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_375_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_376_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_377_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_378_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_379_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_380_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_381_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_382_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_383_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x5FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_384_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_385_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_386_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_387_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x60F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_388_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_389_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_390_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_391_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x61F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_392_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_393_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_394_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_395_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x62F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_396_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_397_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_398_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_399_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x63F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_400_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_401_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_402_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_403_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x64F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_404_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_405_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_406_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_407_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x65F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_408_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_409_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_410_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_411_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x66F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_412_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_413_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_414_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_415_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x67F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_416_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_417_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_418_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_419_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x68F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_420_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_421_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_422_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_423_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x69F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_424_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_425_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_426_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_427_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_428_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_429_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_430_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_431_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_432_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_433_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_434_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_435_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_436_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_437_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_438_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_439_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_440_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_441_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_442_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_443_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_444_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_445_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_446_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_447_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x6FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_448_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_449_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_450_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_451_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x70F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_452_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_453_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_454_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_455_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x71F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_456_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_457_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_458_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_459_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x72F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_460_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_461_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_462_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_463_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x73F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_464_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_465_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_466_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_467_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x74F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_468_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_469_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_470_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_471_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x75F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_472_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_473_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_474_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_475_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x76F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_476_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_477_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_478_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_479_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x77F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_480_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_481_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_482_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_483_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x78F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_484_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_485_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_486_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_487_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x79F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_488_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_489_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_490_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_491_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_492_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_493_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_494_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_495_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_496_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_497_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_498_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_499_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_500_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_501_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_502_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_503_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_504_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_505_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_506_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_507_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_508_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_509_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_510_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_511_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x7FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_512_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_513_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_514_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_515_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x80F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_516_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_517_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_518_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_519_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x81F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_520_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_521_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_522_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_523_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x82F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_524_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_525_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_526_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_527_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x83F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_528_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_529_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_530_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_531_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x84F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_532_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_533_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_534_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_535_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x85F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_536_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_537_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_538_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_539_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x86F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_540_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_541_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_542_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_543_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x87F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_544_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_545_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_546_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_547_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x88F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_548_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_549_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_550_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_551_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x89F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_552_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_553_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_554_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_555_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_556_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_557_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_558_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_559_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_560_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_561_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_562_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_563_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_564_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_565_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_566_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_567_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_568_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_569_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_570_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_571_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_572_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_573_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_574_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_575_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x8FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_576_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_577_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_578_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_579_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x90F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_580_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_581_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_582_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_583_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x91F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_584_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_585_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_586_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_587_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x92F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_588_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_589_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_590_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_591_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x93F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_592_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_593_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_594_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_595_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x94F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_596_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_597_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_598_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_599_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x95F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_600_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_601_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_602_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_603_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x96F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_604_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_605_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_606_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_607_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x97F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_608_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_609_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_610_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_611_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x98F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_612_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_613_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_614_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_615_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x99F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_616_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_617_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9A70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_618_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_619_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9AF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_620_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_621_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9B70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_622_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_623_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9BF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_624_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_625_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9C70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_626_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_627_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9CF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_628_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_629_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9D70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_630_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_631_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9DF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_632_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_633_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9E70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_634_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_635_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9EF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_636_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_637_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9F70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_638_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_639_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0x9FF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_640_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_641_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_642_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_643_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA0F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_644_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_645_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_646_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_647_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_648_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_649_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_650_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_651_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_652_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_653_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_654_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_655_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_656_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_657_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_658_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_659_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_660_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_661_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_662_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_663_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_664_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_665_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_666_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_667_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_668_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_669_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_670_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_671_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_672_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_673_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_674_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_675_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_676_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_677_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_678_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_679_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xA9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_680_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_681_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_682_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_683_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_684_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_685_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_686_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_687_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xABF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_688_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_689_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_690_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_691_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xACF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_692_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_693_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAD70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_694_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_695_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xADF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_696_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_697_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_698_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_699_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_700_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_701_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_702_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_703_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xAFF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_704_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_705_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_706_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_707_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB0F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_708_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_709_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_710_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_711_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_712_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_713_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_714_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_715_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_716_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_717_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_718_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_719_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_720_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_721_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_722_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_723_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_724_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_725_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_726_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_727_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_728_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_729_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_730_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_731_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_732_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_733_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_734_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_735_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_736_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_737_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_738_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_739_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_740_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_741_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_742_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_743_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xB9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_744_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_745_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_746_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_747_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_748_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_749_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_750_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_751_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBBF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_752_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_753_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_754_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_755_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBCF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_756_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_757_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBD70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_758_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_759_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBDF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_760_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_761_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_762_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_763_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_764_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_765_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_766_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_767_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xBFF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_768_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_769_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_770_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_771_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC0F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_772_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_773_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_774_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_775_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_776_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_777_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_778_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_779_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_780_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_781_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_782_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_783_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_784_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_785_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_786_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_787_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_788_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_789_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_790_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_791_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_792_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_793_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_794_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_795_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_796_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_797_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_798_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_799_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_800_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_801_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_802_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_803_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_804_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_805_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_806_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_807_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xC9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_808_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_809_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_810_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_811_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_812_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_813_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_814_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_815_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCBF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_816_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_817_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_818_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_819_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCCF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_820_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_821_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCD70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_822_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_823_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCDF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_824_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_825_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_826_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_827_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_828_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_829_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_830_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_831_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xCFF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_832_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_833_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_834_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_835_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD0F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_836_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_837_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_838_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_839_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_840_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_841_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_842_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_843_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_844_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_845_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_846_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_847_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_848_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_849_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_850_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_851_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_852_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_853_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_854_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_855_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_856_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_857_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_858_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_859_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_860_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_861_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_862_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_863_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_864_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_865_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_866_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_867_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_868_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_869_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_870_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_871_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xD9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_872_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_873_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_874_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_875_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_876_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_877_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_878_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_879_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDBF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_880_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_881_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_882_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_883_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDCF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_884_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_885_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDD70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_886_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_887_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDDF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_888_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_889_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_890_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_891_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_892_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_893_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_894_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_895_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xDFF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_896_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_897_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_898_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_899_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE0F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_900_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_901_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_902_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_903_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_904_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_905_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_906_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_907_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_908_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_909_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_910_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_911_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_912_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_913_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_914_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_915_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_916_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_917_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_918_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_919_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_920_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_921_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_922_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_923_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_924_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_925_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_926_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_927_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_928_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_929_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_930_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_931_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_932_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_933_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_934_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_935_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xE9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_936_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_937_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_938_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_939_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_940_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_941_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_942_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_943_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEBF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_944_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_945_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_946_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_947_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xECF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_948_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_949_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xED70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_950_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_951_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEDF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_952_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_953_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_954_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_955_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_956_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_957_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_958_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_959_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xEFF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_960_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF030) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_961_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF070) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_962_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_963_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF0F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_964_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF130) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_965_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF170) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_966_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_967_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF1F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_968_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF230) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_969_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF270) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_970_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_971_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF2F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_972_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF330) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_973_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF370) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_974_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_975_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF3F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_976_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF430) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_977_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF470) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_978_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_979_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF4F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_980_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF530) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_981_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF570) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_982_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_983_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF5F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_984_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF630) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_985_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF670) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_986_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_987_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF6F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_988_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF730) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_989_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF770) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_990_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_991_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF7F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_992_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF830) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_993_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF870) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_994_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_995_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF8F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_996_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF930) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_997_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF970) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_998_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9B0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_999_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xF9F0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1000_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1001_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFA70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1002_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1003_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFAF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1004_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1005_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFB70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1006_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1007_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFBF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1008_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1009_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFC70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1010_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1011_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFCF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1012_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1013_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFD70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1014_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1015_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFDF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1016_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1017_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFE70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1018_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1019_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFEF0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1020_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF30) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1021_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFF70) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1022_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFB0) /* I/O Upper Address Register(optional) */ +#define CSR_HIPCIEC50_AP_P2P_REG_IO_P2P_IO_UPPER_1023_REG \ + (CSR_HIPCIEC50_AP_P2P_REG_BASE + 0xFFF0) /* I/O Upper Address Register(optional) */ + +/* HIPCIEC50_AP_APAT_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_APAT_REG_BASE (0x7000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_APAT_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_BUF_ALLOC_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x0) /* APAT allocates tx buffer mode */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_BUF_ALLOC_FIFO_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x4) /* APAT allocates tx buffer depth configration */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_TRANSLATION_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x8) /* Control the TLB lookup request behaviour */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_ATS_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x10) /* To set parameters used by ATS transaltion */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_REQID_PASID_PRI_EXC_MODE_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1D0) /* PASID/PRI/EXC select mode */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_0_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1D8) /* APAT ATS PASID config #0 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_1_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1DC) /* APAT ATS PASID config #1 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_2_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1E0) /* APAT ATS PASID config #2 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_3_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1E4) /* APAT ATS PASID config #3 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_4_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1E8) /* priv/exec bit config #0 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_5_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1EC) /* priv/exec bit config #1 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_6_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1F0) /* priv/exec bit config #2 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_XILINX_HOOK_PASID_CFG_7_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1F4) /* priv/exec bit config #3 for Xilinx Hook Test */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_REQID_PASID_PRI_EXC_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x1F8) /* PASID/PRI/EXC configure according to the request ID matched or not */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_REQID_PASID_PRI_EXC_RD_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + \ + 0x1FC) /* PASID/PRI/EXC read from the buffer according to the request ID matched or not */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INV_PRI_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x210) /* To set parameters used by ATS invalidation and PRI */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INV_TIMEOUT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x214) /* ATC Invalidation timeout value config */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INV_PRI_CREDIT_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x21C) /* APAT credit flow ctrl for message */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_RO_CE_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x400) /* APAT interrupt read only status for correctable error */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_RO_NFE_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x404) /* APAT interrupt read only status for non-fatal error */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_RO_FE_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x408) /* APAT interrupt read only status for fatal error */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_SEVERITY_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x40C) /* APAT interrupt severity configure */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_SET_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x410) /* APAT interrupt set configure */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_MASK_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x414) /* APAT interrupt mask configure */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_STATUS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x418) /* APAT interrupt status */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_INT_RO_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x41C) /* APAT interrupt read only status */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_RAM_ECC_ERR_INJ_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x420) /* RAM ECC inject control */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_RAM_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x424) /* RAM ECC err addr */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_RAM_ECC_1BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x428) /* RAM ECC 1bit err cnt */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_RAM_ECC_2BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x42C) /* RAM ECC 2bit err cnt */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_IDLE_SET_CFG_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x800) /* APAT idle status force set configure */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_ATS_REQUEST_IDLE_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x804) /* APAT ATS request idle indication */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_PRI_REQUEST_IDLE_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x808) /* APAT PRI request idle indication */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_TRS_STATUS0_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x80C) /* ATS translate status dfx0 */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_TRS_STATUS1_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x810) /* ATS translate status dfx1 */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_INV_STATUS_L_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x814) /* ATS invalidate status dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_INV_STATUS_H_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x818) /* ATS invalidate status dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_INV_LKDN_CLR_L_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x81C) /* APAT ATS invalidation clear status when linkdown occurs */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_INV_LKDN_CLR_H_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x820) /* APAT ATS invalidation clear status when linkdown occurs */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_INV_PRI_STATUS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x824) /* ATS INV PRI status dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_CMD_PORT_MISS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x828) /* SMMU CMD port miss info */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_RX_INV_CP_MISS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x82C) /* invalidate completion Itag miss info */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_HDR_ENTRY_RD_IDX_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x830) /* APAT ATS request hdr entry index for read */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_DATA_ENTRY_RD_IDX_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x834) /* APAT ATS request data entry index for read */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_HDR_ENTRY_RDATA0_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x838) /* APAT ATS request hdr entry read data0 */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_HDR_ENTRY_RDATA1_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x83C) /* APAT ATS request hdr entry read data1 */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_DATA_ENTRY_RDATA1_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x840) /* APAT ATS request data entry read data[31:0] */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ALLOC_BUF_STATUS0_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x850) /* APAT BUF ALLOC module status dfx0 */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ALLOC_BUF_STATUS1_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x854) /* APAT BUF ALLOC module status dfx1 */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_REQ_SCH_STATUS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0x85C) /* ATS REQ SCH status dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_IB_LKUP_REQ_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC00) /* Ib memory translation request counter */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_TLB_LKUP_REQ_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC04) /* TLB lookup request counter */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_TLB_RETRIED_REQ_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC08) /* TLB lookup retry request counter */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_TLB_RSP_SUCCESS_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC0C) /* TLB response success counter */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_TLB_RSP_FAULT_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC10) /* TLB response fault counter */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_TRS_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC14) /* ATS translate request and completion counter dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_INV_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC18) /* ATS invalidate request and completion counter dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ATS_PRI_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC1C) /* ATS PRI request and response counter dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_SMMU_INV_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC20) /* SMMU invalidate request and completion counter dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_SMMU_PRI_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC24) /* SMMU PRI request and response counter dfx */ +#define CSR_HIPCIEC50_AP_APAT_REG_DFX_APAT_ALLOC_BUF_CNT_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC30) /* APAT allocates tx buffer count */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_PCIE2TBU_REQ_PORT_SEL_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC34) /* Instruct SMMU to use which CHI channel to look up the table. */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_PCIE2TBU_REQ_QOS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC38) /* APAT_PCIE2TBU_REQ_QOS */ +#define CSR_HIPCIEC50_AP_APAT_REG_APAT_PCIE2TBU_REQ_NS_REG \ + (CSR_HIPCIEC50_AP_APAT_REG_BASE + 0xC3C) /* APAT_PCIE2TBU_REQ_NS */ + +/* HIPCIEC50_AP_GLOBAL_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_BASE (0x8000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_GLOBAL_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_ERR_MAPPING_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + \ + 0x0) /* CE(ERR_COR)/UNF(ERR_NONFATAL)/UF(ERR_FATAL)/NI(NORMAL_INT) mapping to ERI/FHI/SPI0/SPI1 */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x8) /* CE(ERR_COR) interrupt enable of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC) /* CE(ERR_COR) interrupt mask of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_UNF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x10) /* UNF(ERR_NONFATAL) interrupt enable of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_UNF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x14) /* UNF(ERR_NONFATAL) interrupt mask of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_UF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x18) /* UF(ERR_FATAL) interrupt enable of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_UF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1C) /* UF(ERR_FATAL) interrupt mask of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x20) /* CE(ERR_COR) interrupt status of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_UNF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x28) /* UNF(ERR_NONFATAL) interrupt status of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_UF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x30) /* UF(ERR_FATAL) interrupt status of each port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_PORT_CFG_0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x40) /* 16-bit CE(ERR_COR) counter register for the source port_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_PORT_CFG_1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x60) /* 16-bit CE(ERR_COR) counter register for the source port_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_PORT_CFG_2_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x80) /* 16-bit CE(ERR_COR) counter register for the source port_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_PORT_CFG_3_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xA0) /* 16-bit CE(ERR_COR) counter register for the source port_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_LOCAL_CFG_0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC0) /* 16-bit CE(ERR_COR) counter register for the source local_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_LOCAL_CFG_1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC8) /* 16-bit CE(ERR_COR) counter register for the source local_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_LOCAL_CFG_2_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xD0) /* 16-bit CE(ERR_COR) counter register for the source local_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CE_CNT_LOCAL_CFG_3_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xD8) /* 16-bit CE(ERR_COR) counter register for the source local_ras_idx */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_MSI_MASK_REG (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF4) /* MSI interrupt mask \ + */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_MSI_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF8) /* MSI interrupt status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_NI_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x100) /* NI(NORMAL_INT) interrupt enable of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_CE_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x104) /* CE(ERR_COR) interrupt enable of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_UNF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x108) /* UNF(ERR_NONFATAL) interrupt enable of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_UF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x10C) /* UF(ERR_FATAL) interrupt enable of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_NI_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x110) /* NI(NORMAL_INT) interrupt mask of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_CE_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x114) /* CE(ERR_COR) interrupt mask of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_UNF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x118) /* UNF(ERR_NONFATAL) interrupt mask of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_UF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x11C) /* UF(ERR_FATAL) interrupt mask of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_NI_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x120) /* NI(NORAML_INT) interrupt status of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_CE_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x124) /* CE(ERR_COR) interrupt status of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_UNF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x128) /* UNF(ERR_NONFATAL) interrupt status of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_COMMON_UF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x12C) /* UF(ERR_FATAL) interrupt status of AP common source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_NI_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x130) /* NI(NORMAL_INT) interrupt enable of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_CE_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x134) /* CE(ERR_COR) interrupt enable of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_UNF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x138) /* UNF(ERR_NONFATAL) interrupt enable of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_UF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x13C) /* UF(ERR_FATAL) interrupt enable of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_NI_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x140) /* NI(NORMAL_INT) interrupt mask of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_CE_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x144) /* CE(ERR_COR) interrupt mask of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_UNF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x148) /* UNF(ERR_NONFATAL) interrupt mask of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_UF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x14C) /* UF(ERR_FATAL) interrupt mask of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_NI_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x150) /* NI(NORAML_INT) interrupt status of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_CE_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x154) /* CE(ERR_COR) interrupt status of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_UNF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x158) /* UNF(ERR_NONFATAL) interrupt status of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_AP_EP_UF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x15C) /* UF(ERR_FATAL) interrupt status of AP EP source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_NI_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x160) /* NI(NORMAL_INT) interrupt enable of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_CE_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x164) /* CE(ERR_COR) interrupt enable of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_UNF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x168) /* UNF(ERR_NONFATAL) interrupt enable of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_UF_ENA_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x16C) /* UF(ERR_FATAL) interrupt enable of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_NI_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x170) /* NI(NORMAL_INT) interrupt mask of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_CE_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x174) /* CE(ERR_COR) interrupt mask of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_UNF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x178) /* UNF(ERR_NONFATAL) interrupt mask of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_UF_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x17C) /* UF(ERR_FATAL) interrupt mask of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_NI_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x180) /* NI(NORAML_INT) interrupt status of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_CE_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x184) /* CE(ERR_COR) interrupt status of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_UNF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x188) /* UNF(ERR_NONFATAL) interrupt status of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PCIE_CORE_UF_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x18C) /* UF(ERR_FATAL) interrupt status of CORE. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PORT_INTX_MAPPING_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + \ + 0x1A0) /* INTx assert/deassert interrupt mapping to INTA/INTB/INTC/INTD/SPI0/SPI1 */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PORT_INTX_INTERRUPT_MODE_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1A4) /* INTx assert/deassert interrupt mode */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PORT_INTX_ASSERT_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1B0) /* INTx assert interrupt mask of each port */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PORT_INTX_DEASSERT_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1B4) /* INTx deassert interrupt mask of each port */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PORT_INTX_ASSERT_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1B8) /* INTx assert interrupt status of each port */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_PORT_INTX_DEASSERT_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1BC) /* INTx deassert interrupt status of each port */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_INTX_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x3F8) /* INTA/B/C/D interrupt mask */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_INTX_LINKDOWN_CLR_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x3FC) /* Config the INTx clear enable of each Port when linkdown. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_INTX_CLR_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x400) /* Config the INTx clear of each Port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_INTX_DEASSERT_MODE_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x404) /* Config the INTx deassert mode of each Port. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_ODR_DISP_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x408) /* IOB RX dispatch dfx select control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_PORT_ERR_CLR_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x40C) /* the clear enable of the ni/ce/ufe/fe counter of each source. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_MSI_AER_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x410) /* MSI tlp abnormal error control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_CFG_INT_TYPE_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x414) /* interrupt type control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_1US_TIMER_THRSH_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x7FC) /* AP 1us timer threshold register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_PORT_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x800) /* AP Port Enable register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_SHUT_DOWN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x808) /* AP Enable register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_APB_SYN_RST_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x810) /* AP APB synchronous reset register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_AXI_SYN_RST_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x814) /* AP AXI synchronous reset register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_APB_FUNC_SYN_RST_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x818) /* AP APB function synchronous reset register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_AXI_FUNC_SYN_RST_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x81C) /* AP AXI function synchronous reset register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_CFGSPACE_RST_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x820) /* AP Capture CfgSpace reset */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_CAP_TL_REG_RST_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x828) /* AP Capture TL Reg reset */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_APB_ICG_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x840) /* AP APB ICG enable register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_AXI_ICG_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x848) /* AP AXI ICG enable register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_SUB_APB_ICG_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x850) /* AP submodule APB ICG enable register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_SUB_AXI_ICG_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x854) /* AP submodule AXI ICG enable register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_SUB_ICG_EN_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x85C) /* The global enable of AP submodule AXI and APB ICG register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_PORT_IDLE_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC00) /* AP port idle status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_IDLE_REG (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC08) /* port idle status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_LINKDOWN_MASK_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC10) /* AP linkdown indication mask register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_LINKDOWN_FORCE_IDLE_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC18) /* AP linkdown force idle register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_WAIT_IDLE_TIMER_CFG_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xC20) /* AP wait idle timer configuration register. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_AP_RESET_CFG_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xD00) /* AP captured cfgspace linkdown reset enable register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_CFG_NORMAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE00) /* RCP control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_CFG_ERR_RSP_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE04) /* RCP abnormal error control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_PCIE_PF_MAP0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE40) /* PCIE PF number used by network */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_COMMON_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE70) /* Network thourgh sync common control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_ECAM_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE74) /* Network thourgh sync ECAM control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_REQUEST_ID_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE78) /* Requester ID for Network through RX. */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_PF_CTRL_0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE80) /* Network thourgh sync control register for PF */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_PF_CTRL_1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE84) /* Network thourgh sync control register for PF */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_PF_CTRL_2_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE88) /* Network thourgh sync control register for PF */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RCP_NET_PF_CTRL_3_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xE8C) /* Network thourgh sync control register for PF */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RBD_CFG_P_ODR_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF00) /* RBD module Posted Request ordering control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RBD_CFG_CREDIT_CLR_CTRL0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF04) /* RBD data credit counter clear ctrl */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RBD_CFG_CREDIT_CLR_CTRL1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF08) /* RBD head credit counter clear ctrl */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RBD_CFG_CREDIT_DIS_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF0C) /* RBD credit active disable ctrl */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_RBD_CFG_ERR_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0xF10) /* RBD abnormal error control register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_INTX_PENDING_CNT_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1000) /* INTx Pending Conute DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_CORE_INTX_CNT_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1004) /* INTx Conute DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_ERR_CNT0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1010) /* NI and CE conuter DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_ERR_CNT1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1014) /* NFE and FE counter DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RAS_IDLE_STS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1020) /* RAS module idle status register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_INTA_STS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1030) /* INTA status DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_INTB_STS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1034) /* INTB status DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_INTC_STS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1038) /* INTC status DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_PORT_INTD_STS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x103C) /* INTD status DFX register */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_CAPT_TL_REG_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1200) /* The DFX control register for Captured TL registers */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_ACC_CTRL_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1210) /* The DFX control register for AP captured cfgspace */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_ACC_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x12F0) /* The DFX status register for AP captured cfgspace */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RCP_STATUS0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1300) /* The DFX status 0 for RCP */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RCP_STATUS1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1304) /* The DFX status 1 for RCP */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RCP_STATUS2_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1308) /* The DFX status 2 for RCP */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RCP_TLP_ERR_CNT_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1340) /* The DFX tlp error coutner for RCP */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RCP_NET_TH_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1320) /* The DFX tlp error coutner for RCP */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1400) /* RBD module status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_ACK_FIFO_STATUS_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1404) /* RBD module hed ack fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1410) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1414) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_2_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1418) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_3_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x141C) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_4_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1420) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_5_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1424) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_6_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1428) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_7_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x142C) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_CDT_CNT_8_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1430) /* RBD module credit counter */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_0_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1440) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_1_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1444) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_2_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1448) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_3_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x144C) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_4_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1450) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_5_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1454) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_6_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1458) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_7_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x145C) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_8_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1460) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_9_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1464) /* RBD module ptr fifo status */ +#define CSR_HIPCIEC50_AP_GLOBAL_REG_DFX_RBD_PTR_FIFO_STATUS_10_REG \ + (CSR_HIPCIEC50_AP_GLOBAL_REG_BASE + 0x1468) /* RBD module ptr fifo status */ + +/* HIPCIEC50_PMT_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_PMT_REG_BASE (0xD0000) + +/* **************************************************************************** */ +/* HIPCIEC50_PMT_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_GLOBAL_CTRL_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x0) /* PMU global ctrl register \ + */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x10) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x18) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x20) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x28) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x30) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x38) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x40) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_L_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x48) /* PMU common ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x14) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1C) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x24) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x2C) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x34) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x3C) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x44) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_CTRL_H_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x4C) /* PMU common ctrl register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x90) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x98) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xA0) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xA8) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xB0) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xB8) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xC0) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_L_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xC8) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x94) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x9C) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xA4) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xAC) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xB4) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xBC) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xC4) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_COUNTER_H_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0xCC) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x110) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x118) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x120) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x128) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x130) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x138) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x140) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_L_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x148) /* PMU event statistic register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x114) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x11C) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x124) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x12C) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x134) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x13C) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x144) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_EXT_COUNTER_H_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x14C) /* PMU event statistic register high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x150) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x158) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x160) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x168) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x170) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x178) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x180) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_STATUS_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x188) /* PMU common interrupt status register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x154) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x15C) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x164) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x16C) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_4_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x174) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_5_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x17C) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_6_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x184) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_COMMON_MASK_7_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x18C) /* PMU common interrupt mask register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_MAILBOX_0_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0xFE0) /* PMU maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_MAILBOX_1_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0xFE4) /* PMU maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_MAILBOX_2_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0xFE8) /* PMU maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_MAILBOX_3_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0xFEC) /* PMU maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_MAILBOX_4_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0xFF0) /* PMU maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PMU_MAILBOX_5_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0xFF4) /* PMU maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TUNING_CTRL_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1000) /* PTT tuning ctrl register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TUNING_DATA_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1004) /* PTT tuning data register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_SIZE_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1800) /* PTT trace buffer size */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_L_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1810) /* PTT trace buffer base addr low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_L_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1818) /* PTT trace buffer base addr low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_L_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1820) /* PTT trace buffer base addr low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_L_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1828) /* PTT trace buffer base addr low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_H_0_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1814) /* PTT trace buffer base addr high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_H_1_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x181C) /* PTT trace buffer base addr high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_H_2_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1824) /* PTT trace buffer base addr high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_ADDR_BASE_H_3_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x182C) /* PTT trace buffer base addr high 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_CTRL_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1850) /* PTT trace ctrl register low 32bit */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_INT_STATUS_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1890) /* PTT trace buffer full interrupt status */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_INT_MASK_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x1894) /* PTT trace buffer full interrupt mask */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_WR_STS_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x18A0) /* PTT trace buffer write pointer */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_STS_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x18B0) /* PTT trace module dfx status */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_CFG_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x18F0) /* PTT trace module mode configuration register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_RAM_ECC_INJ_REG \ + (CSR_HIPCIEC50_PMT_REG_BASE + 0x18F4) /* PTT trace RAM ECC inject control */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_TRACE_DFX_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x18FC) /* PTT trace dfx */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_MAILBOX_0_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x1FE0) /* PTT maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_MAILBOX_1_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x1FE4) /* PTT maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_MAILBOX_2_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x1FE8) /* PTT maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_MAILBOX_3_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x1FEC) /* PTT maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_MAILBOX_4_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x1FF0) /* PTT maibox register */ +#define CSR_HIPCIEC50_PMT_REG_PCIE_PTT_MAILBOX_5_REG (CSR_HIPCIEC50_PMT_REG_BASE + 0x1FF4) /* PTT maibox register */ + +/* HIPCIEC50_AP_MCTP_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_BASE (0xA000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_MCTP_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_QUEUE_CTRL_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x0) /* MCTP Top Control Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_QUEUE_CTRL_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x80) /* MCTP Top Control Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_QUEUE_CTRL_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x100) /* MCTP Top Control Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_QUEUE_CTRL_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x180) /* MCTP Top Control Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x4) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x84) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x104) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_HIGH_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x184) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_LOW_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x8) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_LOW_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x88) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_LOW_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x108) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_BASE_ADDR_LOW_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x188) /* RX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_DEPTH_0_REG (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xC) /* RX Queue Depth. \ + */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_DEPTH_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x8C) /* RX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_DEPTH_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x10C) /* RX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_DEPTH_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x18C) /* RX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_AFULL_THRESHOLD_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x10) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_AFULL_THRESHOLD_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x90) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_AFULL_THRESHOLD_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x110) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_AFULL_THRESHOLD_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x190) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_HEAD_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x14) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_HEAD_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x94) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_HEAD_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x114) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_HEAD_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x194) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_TAIL_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x18) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_TAIL_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x98) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_TAIL_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x118) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_QUEUE_TAIL_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x198) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1C) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x9C) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x11C) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_HIGH_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x19C) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_LOW_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x20) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_LOW_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA0) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_LOW_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x120) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_BASE_ADDR_LOW_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1A0) /* TX Queue base address register. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_DEPTH_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x24) /* TX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_DEPTH_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA4) /* TX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_DEPTH_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x124) /* TX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_DEPTH_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1A4) /* TX Queue Depth. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_HEAD_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x28) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_HEAD_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA8) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_HEAD_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x128) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_HEAD_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1A8) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_TAIL_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x2C) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_TAIL_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xAC) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_TAIL_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x12C) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_QUEUE_TAIL_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1AC) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INT_MAPPING_0_REG (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x30) /* Interrupt mapping \ + */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INT_MAPPING_1_REG (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB0) /* Interrupt mapping \ + */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INT_MAPPING_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x130) /* Interrupt mapping */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INT_MAPPING_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1B0) /* Interrupt mapping */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_STA_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x34) /* Interrupt Status Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_STA_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB4) /* Interrupt Status Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_STA_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x134) /* Interrupt Status Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_STA_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1B4) /* Interrupt Status Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SET_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x38) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SET_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB8) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SET_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x138) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SET_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1B8) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x3C) /* Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBC) /* Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x13C) /* Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1BC) /* Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SOURCE_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x40) /* Interrupt Source Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SOURCE_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xC0) /* Interrupt Source Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SOURCE_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x140) /* Interrupt Source Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_INTRPT_SOURCE_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1C0) /* Interrupt Source Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_SEND_HED_CTRL_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x44) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_SEND_HED_CTRL_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xC4) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_SEND_HED_CTRL_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x144) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_SEND_HED_CTRL_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1C4) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_SEND_HED_CTRL_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x48) /* NP header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_SEND_HED_CTRL_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xC8) /* NP header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_SEND_HED_CTRL_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x148) /* NP header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_SEND_HED_CTRL_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1C8) /* NP header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_HED_CHECK_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x4C) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_HED_CHECK_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xCC) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_HED_CHECK_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x14C) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_HED_CHECK_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x1CC) /* P header control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_COMMON_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x800) /* MCTP Control Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_COAL_CNT_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x804) /* RX interrupt coalescing control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_RX_COAL_TIME_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x808) /* RX interrupt coalescing control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_COAL_CNT_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x80C) /* TX interrupt coalescing control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_TX_COAL_TIME_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x810) /* TX interrupt coalescing control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_MCTP_ACK_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0x814) /* MCTP ack control register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_STATUS_REG (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA00) /* FSM Status Register \ + */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_PORT_IDLE_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA04) /* PORT IDLE Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_OST_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA10) /* FSM Status Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_CDT_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA14) /* MCTP credit remaind counter */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_CDT_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA18) /* MCTP credit remaind counter */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_REC_CDT_GAP_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA1C) /* MCTP received credit gap counter */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_SENT_CDT_GAP_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA20) /* MCTP sent credit gap counter */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_CDT_GAP_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA24) /* MCTP credit gap counter */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_AXI_ERR_ADDR_HIGH_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA80) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_AXI_ERR_ADDR_LOW_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA84) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_COMMON_ERR_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xA88) /* Common error DFX register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_STAT_CTRL_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB00) /* Statistics Controling Register */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_ERR_PKT_CNT_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB04) /* MCTP ERR Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_PKT_NUM_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB80) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_PKT_NUM_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBA0) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_PKT_NUM_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBC0) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_PKT_NUM_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBE0) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_PKT_NUM_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB84) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_PKT_NUM_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBA4) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_PKT_NUM_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBC4) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_PKT_NUM_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBE4) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_QUEUE_FSM_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB88) /* MCTP Queue FSM STATE */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_QUEUE_FSM_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBA8) /* MCTP Queue FSM STATE */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_QUEUE_FSM_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBC8) /* MCTP Queue FSM STATE */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_QUEUE_FSM_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBE8) /* MCTP Queue FSM STATE */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_QUEUE_STA_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB8C) /* MCTP RX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_QUEUE_STA_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBAC) /* MCTP RX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_QUEUE_STA_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBCC) /* MCTP RX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_RX_QUEUE_STA_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBEC) /* MCTP RX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_QUEUE_STA_0_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xB90) /* MCTP TX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_QUEUE_STA_1_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBB0) /* MCTP TX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_QUEUE_STA_2_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBD0) /* MCTP TX queue state */ +#define CSR_HIPCIEC50_AP_MCTP_REG_DFX_MCTP_TX_QUEUE_STA_3_REG \ + (CSR_HIPCIEC50_AP_MCTP_REG_BASE + 0xBF0) /* MCTP TX queue state */ + +/* HIPCIEC50_AP_ENGINE_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_BASE (0xB000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_ENGINE_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_MSK_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x0) /* interrupt mask register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_STATUS_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x4) /* interrupt status register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_RO_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x8) /* interrupt read only status register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_SET_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xC) /* interrupt set register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_SEVERITY_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x10) /* interrupt severity register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_RO_CE_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x14) /* correctable error interrupt read only status register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_RO_NFE_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x18) /* non-fatal error interrupt read only status register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INT_RO_FE_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x1C) /* fatal error interrupt read only status register */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_DMA_SMMU_BYPASS_CFG_REG (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x20) +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_0_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x24) /* high 16bit of DMA DAW 0 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_0_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x28) /* low 32bit of DMA DAW 0 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_1_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x2C) /* high 16bit of DMA DAW 1 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_1_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x30) /* low 32bit of DMA DAW 1 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_2_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x34) /* high 16bit of DMA DAW 2 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_2_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x38) /* low 32bit of DMA DAW 2 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_3_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x3C) /* high 16bit of DMA DAW 3 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_3_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x40) /* low 32bit of DMA DAW 3 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_4_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x44) /* high 16bit of DMA DAW 4 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_4_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x48) /* low 32bit of DMA DAW 4 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_5_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x4C) /* high 16bit of DMA DAW 5 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_5_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x50) /* low 32bit of DMA DAW 5 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_6_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x54) /* high 16bit of DMA DAW 6 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_6_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x58) /* low 32bit of DMA DAW 6 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LL_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x5C) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LH_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x60) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HL_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x64) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HH_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x68) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LL_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x6C) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LH_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x70) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HL_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x74) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HH_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x78) /* the MCTP cache/snp configuration DAW 1 */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_0_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x7C) /* high 16bit of DAW 0 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_0_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x80) /* low 32bit of DAW 0 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_1_H_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x84) /* high 16bit of DAW 1 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_1_L_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x88) /* low 32bit of DAW 1 upper address */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_ATTR_1_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x8C) /* the memory attribute control of DMA */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_ATTR_2_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x90) /* the memory attribute control of DMA */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_IEP_CFG_ATTR_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x94) /* the cache/snp attribute control of IEP config reqeust */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_RCP_ATTR_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x98) /* the cache/snp attribute control of RCP transaction */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_NVME_ATTR_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x9C) /* the cache/snp attribute control of NVMe transaction */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_MCTP_ATTR0_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xA0) /* the cache/snp attribute control of MCTP transaction */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_MCTP_ATTR1_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xA4) /* the cache/snp attribute control of MCTP transaction */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_SDI_MCTP_ATTR2_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xA8) /* the cache/snp attribute control of MCTP transaction */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_WEIGHT_CFG_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xAC) /* weight for WRR arbitration */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_ACTIVE_CFG_REG (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xB0) /* active cfg */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_RCP_DEEP_CFG_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xB4) /* rcp table depth cfg */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_NVME_DEEP_CFG_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xB8) /* nvme table depth cfg */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_MODE_CFG_REG (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0xBC) /* rba mode cfg */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_HEAD_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x800) /* dfx_rba_cnt_head */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_ERR_HEAD_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x804) /* dfx_rba_cnt_err_head */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USEDDEEP_MCTP_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x808) /* dfx_rba_buffer_used */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USEDDEEP_OTHER_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x80C) /* dfx_rba_buffer_used */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_ARBITER_EN_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x810) /* dfx_rba_arbiter_en */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_DFX_RBA_IDLE_REG (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x81C) /* dfx_rba_idle */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_ERR_INJ_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x820) /* RAM ECC inject control */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x824) /* RAM ECC err addr */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_1BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x828) /* RAM ECC 1bit err cnt */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_2BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x82C) /* RAM ECC 2bit err cnt */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_CE_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x830) /* rba interrupt read only status for correctable error */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_NFE_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x834) /* rba interrupt read only status for non-fatal error */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_FE_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x838) /* rba interrupt read only status for fatal error */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_SET_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x840) /* rba interrupt set configure */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_MASK_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x844) /* rba interrupt mask configure */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_STATUS_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x848) /* rba interrupt status */ +#define CSR_HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_REG \ + (CSR_HIPCIEC50_AP_ENGINE_REG_BASE + 0x84C) /* rba interrupt read only status */ + +/* HIPCIEC50_AP_INT_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_INT_REG_BASE (0xC000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_INT_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_INT_REG_INT_VECTOR_NUM_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x0) /* Vector Number */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_CFG_ACS_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x4) /* INT register access ctrling Register */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_COAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x10) /* MSIX Vector Coal Control Register */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_COAL_EVENT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x14) /* MSIX Coal Event Register */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_MSG_ADDR_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x20) /* MSIX Message Address */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_MSG_UP_ADDR_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x24) /* MSIX Message up Address */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_MSG_DATA_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x28) /* MSIX Message Data */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_VECTOR_CTRL_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x2C) /* MSIX Vector Control */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_TBL_FUNC_NUM_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x30) /* Function number field in MSIX TBL */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_TBL_INT_SRC_IDX_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x34) /* Interrupt sourse index field in MSIX TBL */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_PENDING_BIT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x4C) /* MSIX Pending Bits */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_SRAM_INIT_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x50) /* AP_INT sram initial controling register */ +#define CSR_HIPCIEC50_AP_INT_REG_INIT_PTR_TBL_DATA_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x60) /* PTR_TBL initialed data */ +#define CSR_HIPCIEC50_AP_INT_REG_MSI_COAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x70) /* MSI Vector Coal Control Register */ +#define CSR_HIPCIEC50_AP_INT_REG_MSI_COAL_EVENT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x74) /* MSI Coal Event Register \ + */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_REQ_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA0) /* Send interrupt request control register */ +#define CSR_HIPCIEC50_AP_INT_REG_RAS_INT_LEVEL_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA8) /* RAS interrupt level */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xAC) /* Ctrling signal of INTX/MSI/MSIX. */ +#define CSR_HIPCIEC50_AP_INT_REG_ALLOCATE_BUF_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xB0) /* Control registers of allocating buffer */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_CTRL_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xB4) /* Ctrling signal of TLP. */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_0_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xB8) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_1_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xBC) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_2_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xC0) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_3_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xC4) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_4_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xC8) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_5_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xCC) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_6_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xD0) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_TLP_FIELD_SET_7_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xD4) /* Set fields in TLP message */ +#define CSR_HIPCIEC50_AP_INT_REG_LOCAL_CE_INT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x400) /* msix ce ro register */ +#define CSR_HIPCIEC50_AP_INT_REG_LOCAL_NFE_INT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x404) /* msix nfe ro register */ +#define CSR_HIPCIEC50_AP_INT_REG_LOCAL_FE_INT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x408) /* msix fe ro register */ +#define CSR_HIPCIEC50_AP_INT_REG_ABNORMAL_INT_STS_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x500) /* interrupt status of INT abnormal */ +#define CSR_HIPCIEC50_AP_INT_REG_ABNORMAL_INT_MASK_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x504) /* interrupt mask of INT abnormal */ +#define CSR_HIPCIEC50_AP_INT_REG_ABNORMAL_INT_SET_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x508) /* setting interrupt */ +#define CSR_HIPCIEC50_AP_INT_REG_ABNORMAL_INT_RO_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x50C) /* interrupt indicater of INT abnormal */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_SRC0_ERR_FUNC_VEC_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x580) /* interrupt source0 function or vector access error register */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_SRC1_ERR_FUNC_VEC_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x584) /* interrupt source1 function or vector access error register */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_SRC2_ERR_FUNC_VEC_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x588) /* interrupt source1 function or vector access error register */ +#define CSR_HIPCIEC50_AP_INT_REG_INT_SRC3_ERR_FUNC_VEC_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x58C) /* interrupt source1 function or vector access error register */ +#define CSR_HIPCIEC50_AP_INT_REG_ECC_ERR_SET_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x600) /* set msix interrupt */ +#define CSR_HIPCIEC50_AP_INT_REG_ECC_ERR_INT_SRC_STS_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x604) /* ECC error int src \ + */ +#define CSR_HIPCIEC50_AP_INT_REG_ECC_ERR_MASK_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x608) /* ECC Error Mask */ +#define CSR_HIPCIEC50_AP_INT_REG_ECC_ERR_INT_STS_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x60C) /* ECC error int sts */ +#define CSR_HIPCIEC50_AP_INT_REG_ECC_ERR_INJECT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x610) /* ECC Error inject */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_TBL_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x614) /* msix tbl ECC error address */ +#define CSR_HIPCIEC50_AP_INT_REG_MSIX_COAL_TBL_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x618) /* coal tbl ECC error address */ +#define CSR_HIPCIEC50_AP_INT_REG_PTR_TBL_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x61C) /* ptr tbl ECC error address */ +#define CSR_HIPCIEC50_AP_INT_REG_MSI_COAL_TBL_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x620) /* coal tbl ECC error address */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_TLP_CNT_CFG_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x800) /* Tlp count configure */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_HOST_NP_CNT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x804) /* Host NP Count */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_HOST_P_CNT_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x808) /* Host P Count */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_OUTPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x80C) /* Interrupt output count */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC0_INPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x810) /* Interrupt source0 input packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC0_OUTPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x814) /* Interrupt source0 output put packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC1_INPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x818) /* Interrupt source1 input packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC1_OUTPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x81C) /* Interrupt source1 output put packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC2_INPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x820) /* Interrupt source2 input packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC2_OUTPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x824) /* Interrupt source2 output put packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC3_INPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x828) /* Interrupt source3 input packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRC3_OUTPUT_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x82C) /* Interrupt source3 output put packet counter. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_ERR_FUNC_VEC_CNT0_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x840) /* Record how much times of function error and vector error occurs. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_ERR_FUNC_VEC_CNT1_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x844) /* Record how much times of function error and vector error occurs. */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_ECC_ERR_CNT0_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0x850) /* ECC Error counter */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INT_SRAM_INIT_STATUS_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA00) /* AP_INT sram initial status */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_FSM_STATUS0_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA04) /* fsm status */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_INTX_WIRE_STATUS_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA10) /* Link down idle status */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_PORT_STATUS_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA20) /* Link down idle status \ + */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_BUF_REMAIN_CNT_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xA24) /* Remain allocated buffer counter */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_CAPT_REG_ADDR_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xB00) /* Captured register address */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_CAPT_REG_DATA_REG \ + (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xB04) /* Captured register data */ +#define CSR_HIPCIEC50_AP_INT_REG_DFX_SDI_ECO_REGISTER_REG (CSR_HIPCIEC50_AP_INT_REG_BASE + 0xC00) /* ECO register */ + +/* HIPCIEC50_AP_DMA_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_BASE (0x10000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_DMA_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ECC_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x0) /* ECC inject register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4) /* ECC err address register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ECC_ECC_CNT_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x14) /* ECC err cnt register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ECO_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18) /* DMA ECO REG */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_EP_INT_SET_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x20) /* DMA_EP_INT_SET */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_EP_INT_MSK_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x24) /* DMA_EP_INT_MSK */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_EP_INT_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x28) /* DMA_EP_INT */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_EP_INT_STS_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C) /* DMA_EP_INT_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_COMMON_AND_CH_ERR_STS_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x30) /* COMMON_AND_CH_ERR_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ERR_MASK_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x34) /* DMA_ERR_MASK */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_CTRL_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x38) /* ATOMIC_CTRL */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_HEADER_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C) /* ATOMIC_HEADER_0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_HEADER_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x40) /* ATOMIC_HEADER_1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_HEADER_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x44) /* ATOMIC_HEADER_2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_HEADER_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x48) /* ATOMIC_HEADER_3 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4C) /* ATOMIC_DATA_0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x50) /* ATOMIC_DATA_1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x54) /* ATOMIC_DATA_2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x58) /* ATOMIC_DATA_3 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x5C) /* ATOMIC_DATA_4 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x60) /* ATOMIC_DATA_5 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x64) /* ATOMIC_DATA_6 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_DATA_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x68) /* ATOMIC_DATA_7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x6C) /* ATOMIC_RESP_DATA_0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x70) /* ATOMIC_RESP_DATA_1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x74) /* ATOMIC_RESP_DATA_2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x78) /* ATOMIC_RESP_DATA_3 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x7C) /* ATOMIC_RESP_DATA_4 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x80) /* ATOMIC_RESP_DATA_5 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x84) /* ATOMIC_RESP_DATA_6 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x88) /* ATOMIC_RESP_DATA_7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_RESP_DATA_ST_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0xDC) /* ATOMIC_RESP_DATA_ST */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_PREFIX_INF_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x144) /* ATOMIC_PREFIX_INF */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_ATOMIC_PF_VF_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x14C) /* ATOMIC_PF_VF */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_IDLE_STS_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x150) /* PORT_IDLE_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_GLOBAL_CTRL_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x180) /* DMA global contrl register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_RAS_LEVEL_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x184) /* DMA ch err ras level \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CM_RAS_LEVEL_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x188) /* DMA common err ras level */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_INT_MODE_SEL_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18C) /* DMA interrupt mode select */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CM_CE_RO_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x244) /* DMA_CM_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CM_NFE_RO_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x248) /* DMA_CM_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CM_FE_RO_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x24C) /* DMA_CM_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_VF_REG_QUAT_EN_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D8) /* DMA_QUEUE_VF_REG_QUARANTINE_ENABLE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E0) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E4) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E8) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2EC) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F0) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F4) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F8) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2FC) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x300) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x304) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x308) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x30C) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x310) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x314) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x318) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_DONE_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x31C) /* DMA channel done status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x320) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x324) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x328) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x32C) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x330) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x334) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x338) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x33C) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x340) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x344) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x348) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x34C) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x350) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x354) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x358) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_CH_ERR_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x35C) /* DMA channel error status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_EP_RESET_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x360) /* DMA_EP_RESET */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_SQ_PREFETCH_BUF_REL_TO_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x364) /* DMA_SQ_PREFETCH_BUF_REL_TO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x800) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x820) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x840) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x860) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x880) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8A0) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8C0) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8E0) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x900) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x920) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x940) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x960) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x980) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9A0) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9C0) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CFG0_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9E0) /* DMA_PORT_CFG0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x804) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x824) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x844) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x864) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x884) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8A4) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8C4) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8E4) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x904) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x924) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x944) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x964) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x984) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9A4) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9C4) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_CE_RO_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9E4) /* DMA_PORT_CE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x808) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x828) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x848) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x868) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x888) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8A8) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8C8) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8E8) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x908) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x928) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x948) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x968) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x988) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9A8) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9C8) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_NFE_RO_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9E8) /* DMA_PORT_NFE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x80C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x82C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x84C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x86C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x88C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8AC) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8CC) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x8EC) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x90C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x92C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x94C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x96C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x98C) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9AC) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9CC) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_PORT_FE_RO_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x9EC) /* DMA_PORT_FE_RO */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_FLR_DISABLE_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0xA00) /* DMA_FLR_DISABLE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_RP_PORT_REQ_ID_CFG_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0xA04) /* DMA_RP_PORT_REQ_ID_CFG */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_EP_PORT_REQ_ID_CFG_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0xA08) /* DMA_EP_PORT_REQ_ID_CFG */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1800) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1804) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1808) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x180C) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1810) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1814) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1818) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x181C) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1820) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1824) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1828) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x182C) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1830) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1834) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1838) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_ID_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x183C) /* LOCAL_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1840) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1844) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1848) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x184C) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1850) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1854) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1858) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x185C) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1860) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1864) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1868) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x186C) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1870) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1874) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1878) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_ID_STS_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x187C) /* LOCAL_P_ID_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1880) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1884) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1888) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x188C) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1890) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1894) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1898) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x189C) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18A0) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18A4) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18A8) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18AC) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18B0) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18B4) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18B8) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_ID_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18BC) /* REMOTE_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18C0) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18C4) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18C8) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18CC) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18D0) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18D4) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18D8) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18DC) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18E0) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18E4) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18E8) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18EC) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18F0) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18F4) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18F8) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_ID_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x18FC) /* REMOTE_P_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1900) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1904) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1908) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x190C) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1910) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1914) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1918) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x191C) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1920) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1924) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1928) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x192C) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1930) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1934) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1938) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_ID_STS_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x193C) /* SQ_NP_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1940) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1944) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1948) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x194C) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1950) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1954) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1958) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x195C) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1960) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1964) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1968) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x196C) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1970) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1974) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1978) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_ID_STS_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x197C) /* PA_REQ_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1980) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1984) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1988) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x198C) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1990) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1994) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1998) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x199C) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19A0) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19A4) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19A8) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19AC) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19B0) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19B4) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19B8) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALLOCATE_ID_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19BC) /* BUF_ALLOCATE_ID_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19C0) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19C4) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19C8) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19CC) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19D0) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19D4) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19D8) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19DC) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19E0) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19E4) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19E8) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19EC) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19F0) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19F4) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19F8) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CMTB_ENTRY_STS_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x19FC) /* CMTB_ENTRY_STS \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A00) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A04) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A08) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A0C) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A10) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A14) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A18) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A1C) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A20) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A24) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A28) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A2C) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A30) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A34) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A38) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PREBUF_ENTRY_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A3C) /* PREBUF_ENTRY_STS */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_INF_BACK_PRESS_STS0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A40) /* DMA_INF_BACK_PRESS_STS0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_INF_BACK_PRESS_STS1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A44) /* DMA_INF_BACK_PRESS_STS1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_INF_BACK_PRESS_STS2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A48) /* DMA_INF_BACK_PRESS_STS1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_WRR_DISABLE_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1A4C) /* DFX_DMA_WRR_DISABLE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_REQ_TLP_NUM_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C00) /* PA_REQ_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_BACK_TLP_NUM_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C04) /* PA_BACK_TLP_NUM \ + */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_PA_RELEASE_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C08) /* PA_RELEASE_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_NP_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C0C) /* LOCAL_NP_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_CPL_HEAD_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C10) /* LOCAL_CPL_HEAD_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_CPL_DATA_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C14) /* LOCAL_CPL_DATA_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_CPL_EXT_DATA_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C18) /* LOCAL_CPL_EXT_DATA_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_HEAD_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C1C) /* LOCAL_P_HEAD_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LOCAL_P_DATA_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C20) /* LOCAL_P_DATA_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALOC_PORT_REQ_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C24) /* BUF_ALOC_PORT_REQ_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALOC_PORT_RESULT_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C28) /* BUF_ALOC_PORT_RESULT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALOC_PORT_RELEASE_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C2C) /* BUF_ALOC_PORT_RELEASE_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_ALOC_SIZE_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C30) /* BUF_ALOC_SIZE_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_NP_RELEASE_SIZE_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C34) /* BUF_NP_RELEASE_SIZE_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_P_RELEASE_SIZE_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C38) /* BUF_P_RELEASE_SIZE_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_BUF_PORT_RELEASE_SIZE_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C3C) /* BUF_PORT_RELEASE_SIZE_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_HEAD_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C40) /* REMOTE_NP_HEAD_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_NP_DATA_TLP_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C44) /* REMOTE_NP_DATA_TLP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_CPL_HEAD_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C48) /* REMOTE_CPL_HEAD_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_CPL_DATA_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C4C) /* REMOTE_CPL_DATA_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_HEAD_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C50) /* REMOTE_P_HEAD_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_DATA_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C54) /* REMOTE_P_DATA_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_REMOTE_P_EXT_DATA_NUM_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C58) /* REMOTE_P_EXT_DATA_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_NP_NUM_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C5C) /* SQ_NP_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_CPL_NUM_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C60) /* SQ_CPL_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_CQ_P_NUM_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C64) /* CQ_P_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C68) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C6C) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C70) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C74) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C78) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C7C) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C80) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C84) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C88) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C8C) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C90) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C94) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C98) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1C9C) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1CA0) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_LINK_DOWN_EVENT_NUM_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x1CA4) /* LINK_DOWN_EVENT_NUM */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2000) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2100) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2200) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2300) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2400) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2500) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2600) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2700) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2800) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2900) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3000) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3100) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3200) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3300) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3400) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3500) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3600) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3700) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3800) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3900) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F00) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4000) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4100) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4200) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4300) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4400) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4500) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4600) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4700) /* DMA Queue SQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2004) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2104) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2204) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2304) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2404) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2504) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2604) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2704) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2804) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2904) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3004) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3104) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3204) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3304) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3404) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3504) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3604) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3704) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3804) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3904) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F04) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4004) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4104) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4204) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4304) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4404) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4504) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4604) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4704) /* DMA Queue SQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2008) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2108) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2208) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2308) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2408) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2508) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2608) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2708) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2808) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2908) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3008) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3108) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3208) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3308) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3408) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3508) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3608) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3708) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3808) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3908) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F08) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4008) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4108) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4208) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4308) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4408) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4508) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4608) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4708) /* DMA Queue SQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x200C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x210C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x220C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x230C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x240C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x250C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x260C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x270C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x280C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x290C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x300C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x310C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x320C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x330C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x340C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x350C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x360C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x370C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x380C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x390C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F0C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x400C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x410C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x420C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x430C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x440C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x450C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x460C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x470C) /* DMA Queue SQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2010) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2110) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2210) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2310) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2410) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2510) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2610) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2710) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2810) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2910) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3010) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3110) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3210) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3310) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3410) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3510) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3610) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3710) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3810) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3910) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F10) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4010) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4110) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4210) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4310) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4410) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4510) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4610) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4710) /* DMA Queue CQ Base Address Low Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2014) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2114) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2214) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2314) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2414) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2514) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2614) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2714) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2814) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2914) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3014) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3114) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3214) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3314) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3414) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3514) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3614) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3714) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3814) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3914) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F14) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4014) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4114) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4214) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4314) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4414) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4514) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4614) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4714) /* DMA Queue CQ Base Address High Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2018) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2118) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2218) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2318) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2418) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2518) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2618) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2718) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2818) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2918) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3018) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3118) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3218) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3318) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3418) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3518) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3618) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3718) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3818) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3918) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F18) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4018) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4118) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4218) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4318) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4418) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4518) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4618) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4718) /* DMA Queue CQ Depth */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x201C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x211C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x221C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x231C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x241C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x251C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x261C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x271C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x281C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x291C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x301C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x311C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x321C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x331C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x341C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x351C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x361C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x371C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x381C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x391C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F1C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x401C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x411C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x421C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x431C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x441C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x451C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x461C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x471C) /* DMA Queue CQ Head Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2020) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2120) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2220) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2320) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2420) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2520) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2620) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2720) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2820) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2920) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3020) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3120) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3220) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3320) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3420) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3520) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3620) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3720) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3820) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3920) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F20) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4020) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4120) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4220) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4320) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4420) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4520) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4620) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL0_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4720) /* DMA Queue control Register 0 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2024) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2124) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2224) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2324) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2424) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2524) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2624) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2724) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2824) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2924) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3024) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3124) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3224) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3324) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3424) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3524) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3624) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3724) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3824) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3924) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F24) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4024) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4124) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4224) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4324) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4424) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4524) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4624) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL1_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4724) /* DMA Queue control Register 1 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2030) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2130) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2230) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2330) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2430) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2530) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2630) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2730) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2830) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2930) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3030) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3130) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3230) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3330) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3430) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3530) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3630) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3730) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3830) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3930) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F30) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4030) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4130) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4230) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4330) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4430) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4530) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4630) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_FSM_STS_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4730) /* DMA Queue FSM Status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2034) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2134) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2234) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2334) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2434) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2534) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2634) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2734) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2834) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2934) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3034) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3134) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3234) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3334) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3434) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3534) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3634) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3734) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3834) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3934) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F34) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4034) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4134) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4234) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4334) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4434) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4534) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4634) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_SQ_STS_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4734) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x203C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x213C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x223C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x233C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x243C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x253C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x263C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x273C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x283C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x293C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x303C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x313C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x323C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x333C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x343C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x353C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x363C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x373C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x383C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x393C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F3C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x403C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x413C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x423C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x433C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x443C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x453C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x463C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x473C) /* DMA Queue CQ Tail Pointer Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2040) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2140) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2240) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2340) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2440) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2540) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2640) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2740) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2840) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2940) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3040) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3140) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3240) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3340) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3440) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3540) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3640) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3740) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3840) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3940) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F40) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4040) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4140) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4240) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4340) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4440) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4540) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4640) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_STS_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4740) /* DMA Queue Interrupt Status */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2044) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2144) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2244) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2344) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2444) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2544) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2644) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2744) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2844) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2944) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3044) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3144) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3244) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3344) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3444) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3544) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3644) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3744) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3844) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3944) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F44) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4044) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4144) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4244) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4344) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4444) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4544) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4644) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_MSK_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4744) /* DMA Queue Interrupt Mask Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2068) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2168) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2268) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2368) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2468) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2568) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2668) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2768) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2868) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2968) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3068) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3168) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3268) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3368) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3468) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3568) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3668) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3768) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3868) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3968) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F68) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4068) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4168) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4268) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4368) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4468) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4568) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4668) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_SQ_READ_ERR_PTR_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4768) /* The ptr address of SQ read err */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x206C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x216C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x226C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x236C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x246C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x256C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x266C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x276C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x286C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x296C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x306C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x316C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x326C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x336C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x346C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x356C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x366C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x376C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x386C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x396C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F6C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x406C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x416C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x426C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x436C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x446C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x456C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x466C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_RO_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x476C) /* DMA Queue Interrupt RO Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2070) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2170) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2270) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2370) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2470) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2570) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2670) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2770) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2870) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2970) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3070) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3170) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3270) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3370) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3470) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3570) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3670) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3770) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3870) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3970) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F70) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4070) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4170) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4270) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4370) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4470) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4570) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4670) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_INT_SET_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4770) /* DMA Queue Interrupt SET Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2084) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2184) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2284) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2384) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2484) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2584) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2684) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2784) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2884) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2984) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3084) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3184) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3284) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3384) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3484) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3584) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3684) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3784) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3884) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3984) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F84) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4084) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4184) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4284) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4384) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4484) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4584) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4684) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM0_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4784) /* The statistics number for dma_queu_err0~7 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2088) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2188) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2288) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2388) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2488) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2588) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2688) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2788) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2888) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2988) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3088) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3188) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3288) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3388) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3488) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3588) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3688) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3788) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3888) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3988) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F88) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4088) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4188) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4288) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4388) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4488) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4588) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4688) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM1_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x4788) /* The statistics number for dma_queu_err8~15 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x208C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x218C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x228C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x238C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x248C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x258C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x268C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x278C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x288C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x298C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x308C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x318C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x328C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x338C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x348C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x358C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x368C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x378C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x388C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x398C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F8C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x408C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x418C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x428C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x438C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x448C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x458C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x468C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_ERR_INT_NUM2_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x478C) /* The statistics number for dma_queu_err16~17 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x209C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x219C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x229C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x239C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x249C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x259C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x269C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x279C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x289C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x299C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2A9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2B9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2C9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2D9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2E9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2F9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x309C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x319C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x329C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x339C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x349C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x359C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x369C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x379C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x389C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x399C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3A9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3B9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3C9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3D9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3E9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3F9C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x409C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x419C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x429C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x439C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x449C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x459C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x469C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DMA_QUEUE_CTRL2_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x479C) /* DMA Queue control Register 2 */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_0_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x20A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_1_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x21A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_2_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x22A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_3_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x23A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_4_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x24A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_5_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x25A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_6_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x26A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_7_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x27A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_8_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x28A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_9_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x29A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_10_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2AA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_11_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2BA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_12_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2CA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_13_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2DA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_14_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2EA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_15_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2FA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_16_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x30A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_17_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x31A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_18_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x32A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_19_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x33A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_20_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x34A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_21_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x35A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_22_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x36A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_23_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x37A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_24_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x38A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_25_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x39A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_26_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3AA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_27_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3BA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_28_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3CA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_29_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3DA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_30_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3EA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_31_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3FA0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_32_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x40A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_33_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x41A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_34_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x42A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_35_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x43A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_36_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x44A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_37_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x45A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_38_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x46A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DONE_INT_MERGE_39_REG (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x47A0) /* DONE_INT_MERGE */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_0_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x20A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_1_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x21A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_2_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x22A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_3_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x23A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_4_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x24A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_5_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x25A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_6_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x26A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_7_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x27A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_8_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x28A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_9_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x29A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_10_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2AA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_11_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2BA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_12_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2CA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_13_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2DA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_14_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2EA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_15_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x2FA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_16_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x30A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_17_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x31A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_18_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x32A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_19_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x33A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_20_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x34A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_21_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x35A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_22_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x36A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_23_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x37A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_24_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x38A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_25_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x39A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_26_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3AA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_27_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3BA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_28_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3CA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_29_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3DA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_30_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3EA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_31_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x3FA4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_32_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x40A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_33_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x41A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_34_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x42A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_35_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x43A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_36_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x44A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_37_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x45A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_38_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x46A4) /* DMA Queue SQ and CQ status Register */ +#define CSR_HIPCIEC50_AP_DMA_REG_DFX_DMA_QUEUE_SQ_STS2_39_REG \ + (CSR_HIPCIEC50_AP_DMA_REG_BASE + 0x47A4) /* DMA Queue SQ and CQ status Register */ + +/* HIPCIEC50_AP_NVME_PF_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_BASE (0x200000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_NVME_PF_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_CAP_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x0) /* NVMe Controller Capabilities Low */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_CAP_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x4) /* NVMe Controller Capabilities High */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_VS_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x8) /* NVMe Controller Version */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_INTMS_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0xC) /* NVMe Controller Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_INTMC_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10) /* NVMe Controller Interrupt Clear */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_CONFIG_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14) /* NVMe Controller Configuration */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_CTRL_STATUS_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C) /* NVMe Controller Status */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_NVME_SUBSYS_RST_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20) /* NVMe subsystem Reset */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_AQA_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24) /* NVMe Admin Queue Attributes */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_ASQB_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28) /* NVMe Admin Submission Queue Base Addrss low */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_ASQB_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C) /* NVMe Admin Submission Queue Base Addrss high */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_ACQB_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x30) /* NVMe Admin Completion Queue Base Address low */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_ACQB_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x34) /* NVMe Admin Completion Queue Base Address high */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CMBLOC_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x38) /* NVMe Controller Memory Buffer Location */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CMBSZ_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x3C) /* NVMe Controller Memory Buffer Size */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CMBMSC_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x50) /* NVME ARM Driver Updata Low */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CMBMSC_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x54) /* NVME ARM Driver Updata Low */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CMBSTS_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x58) /* Controller Memory Buffer Status */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_PMRCAP_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0xE00) /* Persistent Memory Region Capabilities */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_PMRMSC_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0xE14) /* Persistent Memory Region Memory Space Control */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_PMRMSC_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0xE18) /* Persistent Memory Region Memory Space Control */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_ARM_DRV_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0xEFC) /* NVME ARM Driver Updata */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_0_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1000) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1008) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_2_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1010) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_3_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1018) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_4_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1020) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_5_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1028) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_6_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1030) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_7_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1038) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_8_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1040) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_9_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1048) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_10_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1050) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_11_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1058) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_12_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1060) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_13_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1068) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_14_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1070) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_15_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1078) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_16_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1080) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_17_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1088) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_18_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1090) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_19_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1098) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_20_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_21_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_22_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_23_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_24_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_25_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_26_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_27_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_28_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_29_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_30_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_31_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_32_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1100) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_33_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1108) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_34_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1110) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_35_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1118) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_36_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1120) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_37_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1128) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_38_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1130) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_39_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1138) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_40_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1140) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_41_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1148) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_42_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1150) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_43_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1158) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_44_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1160) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_45_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1168) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_46_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1170) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_47_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1178) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_48_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1180) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_49_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1188) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_50_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1190) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_51_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1198) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_52_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_53_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_54_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_55_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_56_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_57_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_58_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_59_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_60_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_61_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_62_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_63_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_64_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1200) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_65_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1208) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_66_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1210) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_67_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1218) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_68_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1220) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_69_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1228) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_70_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1230) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_71_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1238) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_72_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1240) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_73_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1248) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_74_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1250) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_75_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1258) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_76_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1260) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_77_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1268) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_78_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1270) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_79_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1278) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_80_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1280) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_81_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1288) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_82_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1290) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_83_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1298) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_84_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_85_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_86_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_87_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_88_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_89_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_90_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_91_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_92_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_93_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_94_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_95_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_96_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1300) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_97_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1308) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_98_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1310) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_99_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1318) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_100_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1320) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_101_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1328) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_102_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1330) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_103_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1338) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_104_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1340) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_105_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1348) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_106_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1350) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_107_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1358) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_108_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1360) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_109_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1368) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_110_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1370) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_111_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1378) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_112_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1380) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_113_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1388) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_114_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1390) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_115_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1398) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_116_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_117_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_118_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_119_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_120_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_121_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_122_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_123_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_124_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_125_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_126_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_127_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_128_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1400) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_129_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1408) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_130_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1410) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_131_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1418) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_132_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1420) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_133_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1428) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_134_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1430) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_135_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1438) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_136_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1440) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_137_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1448) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_138_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1450) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_139_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1458) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_140_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1460) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_141_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1468) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_142_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1470) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_143_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1478) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_144_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1480) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_145_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1488) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_146_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1490) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_147_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1498) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_148_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_149_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_150_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_151_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_152_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_153_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_154_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_155_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_156_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_157_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_158_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_159_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_160_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1500) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_161_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1508) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_162_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1510) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_163_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1518) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_164_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1520) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_165_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1528) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_166_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1530) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_167_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1538) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_168_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1540) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_169_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1548) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_170_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1550) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_171_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1558) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_172_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1560) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_173_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1568) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_174_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1570) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_175_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1578) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_176_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1580) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_177_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1588) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_178_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1590) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_179_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1598) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_180_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_181_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_182_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_183_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_184_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_185_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_186_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_187_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_188_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_189_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_190_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_191_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_192_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1600) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_193_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1608) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_194_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1610) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_195_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1618) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_196_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1620) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_197_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1628) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_198_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1630) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_199_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1638) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_200_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1640) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_201_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1648) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_202_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1650) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_203_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1658) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_204_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1660) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_205_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1668) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_206_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1670) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_207_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1678) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_208_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1680) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_209_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1688) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_210_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1690) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_211_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1698) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_212_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_213_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_214_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_215_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_216_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_217_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_218_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_219_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_220_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_221_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_222_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_223_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_224_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1700) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_225_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1708) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_226_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1710) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_227_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1718) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_228_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1720) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_229_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1728) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_230_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1730) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_231_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1738) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_232_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1740) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_233_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1748) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_234_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1750) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_235_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1758) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_236_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1760) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_237_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1768) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_238_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1770) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_239_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1778) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_240_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1780) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_241_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1788) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_242_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1790) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_243_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1798) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_244_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_245_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_246_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_247_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_248_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_249_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_250_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_251_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_252_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_253_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_254_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_255_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_256_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1800) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_257_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1808) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_258_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1810) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_259_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1818) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_260_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1820) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_261_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1828) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_262_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1830) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_263_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1838) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_264_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1840) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_265_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1848) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_266_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1850) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_267_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1858) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_268_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1860) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_269_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1868) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_270_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1870) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_271_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1878) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_272_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1880) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_273_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1888) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_274_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1890) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_275_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1898) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_276_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_277_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_278_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_279_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_280_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_281_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_282_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_283_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_284_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_285_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_286_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_287_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_288_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1900) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_289_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1908) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_290_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1910) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_291_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1918) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_292_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1920) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_293_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1928) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_294_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1930) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_295_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1938) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_296_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1940) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_297_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1948) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_298_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1950) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_299_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1958) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_300_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1960) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_301_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1968) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_302_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1970) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_303_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1978) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_304_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1980) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_305_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1988) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_306_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1990) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_307_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1998) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_308_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_309_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_310_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_311_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_312_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_313_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_314_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_315_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_316_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_317_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_318_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_319_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_320_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_321_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_322_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_323_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_324_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_325_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_326_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_327_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_328_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_329_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_330_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_331_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_332_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_333_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_334_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_335_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_336_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_337_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_338_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_339_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_340_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_341_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_342_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_343_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_344_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_345_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_346_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_347_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_348_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_349_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_350_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_351_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_352_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_353_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_354_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_355_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_356_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_357_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_358_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_359_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_360_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_361_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_362_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_363_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_364_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_365_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_366_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_367_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_368_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_369_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_370_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_371_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_372_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_373_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_374_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_375_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_376_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_377_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_378_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_379_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_380_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_381_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_382_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_383_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_384_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_385_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_386_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_387_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_388_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_389_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_390_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_391_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_392_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_393_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_394_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_395_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_396_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_397_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_398_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_399_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_400_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_401_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_402_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_403_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_404_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_405_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_406_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_407_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_408_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_409_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_410_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_411_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_412_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_413_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_414_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_415_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_416_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_417_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_418_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_419_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_420_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_421_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_422_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_423_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_424_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_425_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_426_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_427_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_428_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_429_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_430_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_431_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_432_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_433_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_434_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_435_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_436_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_437_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_438_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_439_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_440_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_441_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_442_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_443_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_444_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_445_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_446_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_447_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_448_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_449_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_450_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_451_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_452_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_453_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_454_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_455_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_456_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_457_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_458_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_459_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_460_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_461_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_462_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_463_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_464_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_465_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_466_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_467_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_468_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_469_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_470_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_471_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_472_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_473_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_474_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ED0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_475_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ED8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_476_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_477_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_478_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_479_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_480_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_481_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_482_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_483_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_484_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_485_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_486_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_487_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_488_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_489_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_490_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_491_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_492_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_493_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_494_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_495_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_496_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_497_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_498_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_499_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_500_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_501_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_502_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_503_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_504_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_505_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_506_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_507_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_508_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_509_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_510_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_511_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_512_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2000) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_513_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2008) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_514_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2010) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_515_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2018) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_516_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2020) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_517_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2028) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_518_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2030) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_519_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2038) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_520_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2040) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_521_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2048) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_522_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2050) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_523_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2058) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_524_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2060) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_525_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2068) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_526_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2070) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_527_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2078) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_528_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2080) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_529_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2088) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_530_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2090) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_531_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2098) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_532_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_533_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_534_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_535_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_536_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_537_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_538_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_539_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_540_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_541_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_542_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_543_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_544_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2100) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_545_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2108) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_546_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2110) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_547_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2118) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_548_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2120) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_549_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2128) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_550_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2130) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_551_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2138) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_552_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2140) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_553_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2148) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_554_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2150) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_555_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2158) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_556_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2160) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_557_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2168) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_558_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2170) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_559_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2178) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_560_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2180) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_561_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2188) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_562_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2190) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_563_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2198) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_564_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_565_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_566_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_567_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_568_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_569_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_570_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_571_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_572_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_573_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_574_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_575_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_576_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2200) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_577_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2208) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_578_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2210) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_579_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2218) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_580_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2220) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_581_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2228) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_582_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2230) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_583_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2238) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_584_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2240) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_585_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2248) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_586_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2250) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_587_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2258) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_588_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2260) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_589_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2268) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_590_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2270) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_591_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2278) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_592_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2280) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_593_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2288) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_594_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2290) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_595_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2298) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_596_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_597_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_598_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_599_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_600_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_601_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_602_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_603_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_604_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_605_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_606_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_607_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_608_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2300) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_609_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2308) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_610_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2310) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_611_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2318) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_612_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2320) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_613_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2328) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_614_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2330) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_615_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2338) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_616_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2340) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_617_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2348) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_618_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2350) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_619_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2358) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_620_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2360) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_621_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2368) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_622_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2370) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_623_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2378) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_624_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2380) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_625_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2388) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_626_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2390) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_627_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2398) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_628_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_629_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_630_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_631_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_632_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_633_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_634_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_635_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_636_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_637_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_638_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_639_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_640_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2400) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_641_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2408) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_642_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2410) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_643_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2418) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_644_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2420) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_645_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2428) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_646_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2430) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_647_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2438) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_648_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2440) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_649_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2448) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_650_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2450) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_651_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2458) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_652_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2460) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_653_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2468) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_654_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2470) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_655_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2478) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_656_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2480) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_657_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2488) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_658_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2490) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_659_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2498) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_660_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_661_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_662_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_663_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_664_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_665_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_666_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_667_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_668_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_669_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_670_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_671_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_672_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2500) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_673_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2508) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_674_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2510) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_675_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2518) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_676_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2520) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_677_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2528) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_678_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2530) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_679_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2538) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_680_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2540) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_681_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2548) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_682_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2550) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_683_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2558) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_684_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2560) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_685_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2568) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_686_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2570) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_687_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2578) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_688_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2580) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_689_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2588) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_690_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2590) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_691_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2598) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_692_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_693_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_694_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_695_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_696_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_697_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_698_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_699_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_700_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_701_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_702_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_703_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_704_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2600) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_705_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2608) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_706_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2610) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_707_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2618) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_708_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2620) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_709_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2628) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_710_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2630) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_711_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2638) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_712_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2640) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_713_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2648) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_714_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2650) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_715_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2658) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_716_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2660) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_717_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2668) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_718_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2670) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_719_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2678) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_720_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2680) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_721_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2688) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_722_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2690) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_723_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2698) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_724_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_725_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_726_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_727_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_728_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_729_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_730_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_731_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_732_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_733_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_734_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_735_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_736_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2700) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_737_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2708) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_738_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2710) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_739_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2718) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_740_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2720) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_741_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2728) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_742_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2730) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_743_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2738) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_744_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2740) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_745_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2748) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_746_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2750) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_747_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2758) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_748_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2760) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_749_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2768) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_750_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2770) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_751_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2778) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_752_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2780) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_753_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2788) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_754_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2790) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_755_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2798) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_756_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_757_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_758_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_759_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_760_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_761_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_762_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_763_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_764_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_765_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_766_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_767_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_768_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2800) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_769_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2808) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_770_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2810) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_771_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2818) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_772_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2820) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_773_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2828) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_774_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2830) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_775_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2838) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_776_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2840) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_777_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2848) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_778_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2850) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_779_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2858) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_780_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2860) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_781_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2868) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_782_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2870) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_783_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2878) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_784_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2880) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_785_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2888) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_786_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2890) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_787_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2898) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_788_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_789_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_790_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_791_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_792_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_793_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_794_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_795_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_796_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_797_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_798_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_799_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_800_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2900) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_801_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2908) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_802_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2910) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_803_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2918) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_804_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2920) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_805_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2928) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_806_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2930) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_807_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2938) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_808_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2940) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_809_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2948) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_810_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2950) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_811_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2958) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_812_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2960) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_813_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2968) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_814_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2970) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_815_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2978) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_816_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2980) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_817_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2988) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_818_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2990) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_819_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2998) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_820_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_821_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_822_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_823_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_824_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_825_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_826_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_827_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_828_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_829_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_830_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_831_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_832_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_833_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_834_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_835_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_836_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_837_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_838_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_839_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_840_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_841_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_842_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_843_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_844_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_845_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_846_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_847_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_848_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_849_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_850_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_851_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_852_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_853_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_854_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_855_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_856_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_857_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_858_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_859_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_860_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_861_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_862_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_863_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_864_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_865_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_866_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_867_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_868_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_869_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_870_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_871_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_872_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_873_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_874_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_875_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_876_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_877_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_878_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_879_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_880_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_881_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_882_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_883_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_884_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_885_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_886_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_887_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_888_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_889_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_890_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_891_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_892_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_893_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_894_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_895_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_896_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_897_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_898_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_899_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_900_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_901_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_902_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_903_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_904_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_905_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_906_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_907_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_908_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_909_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_910_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_911_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_912_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_913_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_914_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_915_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_916_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_917_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_918_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_919_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_920_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_921_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_922_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_923_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_924_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_925_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_926_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_927_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_928_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_929_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_930_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_931_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_932_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_933_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_934_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_935_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_936_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_937_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_938_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_939_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_940_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_941_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_942_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_943_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_944_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_945_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_946_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_947_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_948_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_949_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_950_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_951_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_952_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_953_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_954_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_955_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_956_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_957_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_958_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_959_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_960_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_961_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_962_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_963_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_964_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_965_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_966_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_967_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_968_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_969_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_970_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_971_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_972_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_973_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_974_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_975_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_976_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_977_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_978_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_979_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_980_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_981_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_982_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_983_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_984_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_985_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_986_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ED0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_987_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ED8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_988_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_989_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_990_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_991_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_992_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_993_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_994_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_995_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_996_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_997_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_998_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_999_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_SQTDBL_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_0_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1004) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x100C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_2_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1014) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_3_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x101C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_4_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1024) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_5_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x102C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_6_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1034) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_7_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x103C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_8_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1044) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_9_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x104C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_10_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1054) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_11_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x105C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_12_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1064) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_13_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x106C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_14_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1074) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_15_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x107C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_16_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1084) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_17_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x108C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_18_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1094) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_19_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x109C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_20_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_21_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_22_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_23_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_24_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_25_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_26_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_27_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_28_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_29_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_30_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_31_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x10FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_32_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1104) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_33_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x110C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_34_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1114) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_35_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x111C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_36_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1124) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_37_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x112C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_38_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1134) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_39_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x113C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_40_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1144) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_41_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x114C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_42_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1154) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_43_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x115C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_44_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1164) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_45_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x116C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_46_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1174) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_47_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x117C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_48_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1184) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_49_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x118C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_50_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1194) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_51_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x119C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_52_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_53_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_54_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_55_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_56_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_57_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_58_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_59_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_60_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_61_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_62_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_63_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x11FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_64_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1204) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_65_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x120C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_66_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1214) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_67_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x121C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_68_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1224) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_69_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x122C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_70_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1234) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_71_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x123C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_72_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1244) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_73_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x124C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_74_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1254) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_75_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x125C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_76_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1264) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_77_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x126C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_78_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1274) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_79_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x127C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_80_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1284) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_81_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x128C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_82_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1294) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_83_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x129C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_84_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_85_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_86_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_87_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_88_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_89_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_90_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_91_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_92_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_93_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_94_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_95_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x12FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_96_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1304) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_97_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x130C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_98_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1314) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_99_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x131C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_100_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1324) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_101_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x132C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_102_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1334) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_103_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x133C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_104_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1344) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_105_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x134C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_106_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1354) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_107_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x135C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_108_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1364) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_109_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x136C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_110_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1374) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_111_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x137C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_112_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1384) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_113_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x138C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_114_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1394) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_115_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x139C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_116_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_117_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_118_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_119_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_120_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_121_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_122_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_123_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_124_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_125_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_126_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_127_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x13FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_128_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1404) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_129_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x140C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_130_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1414) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_131_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x141C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_132_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1424) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_133_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x142C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_134_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1434) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_135_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x143C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_136_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1444) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_137_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x144C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_138_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1454) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_139_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x145C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_140_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1464) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_141_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x146C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_142_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1474) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_143_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x147C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_144_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1484) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_145_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x148C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_146_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1494) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_147_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x149C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_148_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_149_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_150_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_151_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_152_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_153_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_154_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_155_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_156_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_157_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_158_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_159_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x14FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_160_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1504) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_161_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x150C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_162_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1514) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_163_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x151C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_164_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1524) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_165_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x152C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_166_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1534) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_167_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x153C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_168_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1544) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_169_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x154C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_170_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1554) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_171_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x155C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_172_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1564) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_173_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x156C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_174_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1574) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_175_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x157C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_176_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1584) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_177_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x158C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_178_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1594) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_179_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x159C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_180_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_181_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_182_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_183_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_184_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_185_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_186_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_187_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_188_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_189_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_190_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_191_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x15FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_192_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1604) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_193_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x160C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_194_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1614) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_195_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x161C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_196_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1624) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_197_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x162C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_198_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1634) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_199_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x163C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_200_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1644) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_201_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x164C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_202_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1654) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_203_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x165C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_204_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1664) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_205_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x166C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_206_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1674) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_207_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x167C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_208_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1684) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_209_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x168C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_210_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1694) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_211_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x169C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_212_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_213_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_214_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_215_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_216_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_217_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_218_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_219_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_220_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_221_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_222_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_223_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x16FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_224_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1704) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_225_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x170C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_226_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1714) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_227_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x171C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_228_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1724) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_229_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x172C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_230_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1734) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_231_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x173C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_232_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1744) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_233_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x174C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_234_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1754) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_235_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x175C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_236_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1764) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_237_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x176C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_238_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1774) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_239_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x177C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_240_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1784) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_241_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x178C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_242_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1794) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_243_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x179C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_244_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_245_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_246_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_247_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_248_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_249_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_250_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_251_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_252_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_253_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_254_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_255_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x17FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_256_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1804) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_257_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x180C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_258_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1814) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_259_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x181C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_260_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1824) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_261_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x182C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_262_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1834) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_263_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x183C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_264_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1844) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_265_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x184C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_266_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1854) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_267_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x185C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_268_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1864) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_269_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x186C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_270_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1874) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_271_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x187C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_272_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1884) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_273_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x188C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_274_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1894) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_275_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x189C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_276_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_277_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_278_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_279_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_280_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_281_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_282_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_283_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_284_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_285_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_286_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_287_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x18FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_288_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1904) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_289_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x190C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_290_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1914) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_291_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x191C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_292_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1924) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_293_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x192C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_294_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1934) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_295_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x193C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_296_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1944) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_297_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x194C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_298_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1954) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_299_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x195C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_300_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1964) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_301_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x196C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_302_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1974) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_303_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x197C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_304_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1984) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_305_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x198C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_306_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1994) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_307_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x199C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_308_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_309_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_310_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_311_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_312_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_313_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_314_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_315_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_316_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_317_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_318_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_319_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x19FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_320_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_321_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_322_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_323_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_324_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_325_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_326_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_327_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_328_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_329_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_330_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_331_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_332_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_333_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_334_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_335_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_336_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_337_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_338_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_339_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1A9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_340_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_341_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_342_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_343_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ABC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_344_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_345_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ACC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_346_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_347_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ADC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_348_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_349_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_350_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_351_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1AFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_352_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_353_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_354_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_355_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_356_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_357_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_358_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_359_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_360_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_361_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_362_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_363_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_364_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_365_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_366_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_367_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_368_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_369_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_370_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_371_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1B9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_372_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_373_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_374_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_375_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_376_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_377_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_378_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_379_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_380_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_381_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_382_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_383_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1BFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_384_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_385_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_386_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_387_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_388_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_389_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_390_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_391_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_392_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_393_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_394_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_395_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_396_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_397_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_398_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_399_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_400_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_401_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_402_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_403_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1C9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_404_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_405_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_406_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_407_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_408_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_409_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_410_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_411_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_412_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_413_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_414_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_415_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1CFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_416_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_417_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_418_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_419_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_420_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_421_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_422_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_423_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_424_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_425_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_426_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_427_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_428_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_429_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_430_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_431_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_432_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_433_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_434_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_435_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1D9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_436_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_437_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_438_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_439_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_440_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_441_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_442_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_443_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_444_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_445_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_446_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_447_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1DFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_448_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_449_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_450_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_451_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_452_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_453_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_454_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_455_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_456_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_457_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_458_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_459_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_460_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_461_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_462_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_463_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_464_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_465_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_466_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_467_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1E9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_468_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_469_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_470_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_471_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_472_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_473_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ECC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_474_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1ED4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_475_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_476_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_477_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_478_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_479_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1EFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_480_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_481_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_482_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_483_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_484_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_485_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_486_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_487_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_488_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_489_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_490_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_491_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_492_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_493_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_494_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_495_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_496_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_497_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_498_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_499_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1F9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_500_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_501_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_502_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_503_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_504_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_505_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_506_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_507_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_508_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_509_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_510_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_511_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x1FFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_512_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2004) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_513_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x200C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_514_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2014) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_515_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x201C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_516_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2024) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_517_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x202C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_518_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2034) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_519_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x203C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_520_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2044) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_521_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x204C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_522_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2054) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_523_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x205C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_524_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2064) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_525_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x206C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_526_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2074) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_527_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x207C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_528_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2084) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_529_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x208C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_530_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2094) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_531_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x209C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_532_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_533_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_534_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_535_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_536_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_537_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_538_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_539_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_540_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_541_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_542_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_543_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x20FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_544_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2104) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_545_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x210C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_546_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2114) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_547_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x211C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_548_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2124) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_549_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x212C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_550_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2134) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_551_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x213C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_552_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2144) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_553_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x214C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_554_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2154) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_555_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x215C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_556_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2164) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_557_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x216C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_558_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2174) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_559_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x217C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_560_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2184) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_561_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x218C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_562_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2194) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_563_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x219C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_564_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_565_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_566_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_567_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_568_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_569_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_570_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_571_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_572_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_573_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_574_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_575_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x21FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_576_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2204) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_577_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x220C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_578_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2214) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_579_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x221C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_580_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2224) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_581_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x222C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_582_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2234) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_583_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x223C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_584_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2244) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_585_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x224C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_586_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2254) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_587_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x225C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_588_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2264) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_589_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x226C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_590_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2274) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_591_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x227C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_592_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2284) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_593_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x228C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_594_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2294) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_595_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x229C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_596_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_597_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_598_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_599_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_600_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_601_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_602_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_603_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_604_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_605_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_606_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_607_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x22FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_608_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2304) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_609_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x230C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_610_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2314) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_611_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x231C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_612_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2324) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_613_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x232C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_614_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2334) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_615_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x233C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_616_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2344) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_617_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x234C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_618_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2354) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_619_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x235C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_620_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2364) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_621_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x236C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_622_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2374) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_623_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x237C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_624_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2384) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_625_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x238C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_626_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2394) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_627_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x239C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_628_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_629_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_630_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_631_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_632_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_633_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_634_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_635_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_636_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_637_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_638_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_639_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x23FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_640_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2404) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_641_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x240C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_642_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2414) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_643_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x241C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_644_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2424) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_645_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x242C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_646_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2434) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_647_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x243C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_648_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2444) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_649_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x244C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_650_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2454) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_651_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x245C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_652_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2464) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_653_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x246C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_654_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2474) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_655_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x247C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_656_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2484) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_657_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x248C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_658_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2494) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_659_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x249C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_660_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_661_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_662_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_663_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_664_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_665_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_666_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_667_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_668_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_669_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_670_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_671_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x24FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_672_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2504) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_673_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x250C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_674_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2514) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_675_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x251C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_676_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2524) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_677_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x252C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_678_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2534) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_679_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x253C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_680_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2544) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_681_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x254C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_682_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2554) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_683_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x255C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_684_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2564) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_685_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x256C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_686_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2574) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_687_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x257C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_688_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2584) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_689_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x258C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_690_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2594) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_691_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x259C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_692_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_693_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_694_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_695_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_696_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_697_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_698_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_699_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_700_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_701_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_702_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_703_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x25FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_704_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2604) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_705_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x260C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_706_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2614) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_707_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x261C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_708_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2624) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_709_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x262C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_710_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2634) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_711_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x263C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_712_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2644) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_713_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x264C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_714_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2654) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_715_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x265C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_716_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2664) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_717_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x266C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_718_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2674) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_719_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x267C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_720_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2684) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_721_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x268C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_722_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2694) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_723_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x269C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_724_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_725_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_726_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_727_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_728_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_729_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_730_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_731_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_732_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_733_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_734_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_735_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x26FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_736_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2704) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_737_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x270C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_738_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2714) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_739_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x271C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_740_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2724) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_741_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x272C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_742_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2734) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_743_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x273C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_744_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2744) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_745_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x274C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_746_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2754) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_747_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x275C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_748_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2764) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_749_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x276C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_750_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2774) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_751_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x277C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_752_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2784) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_753_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x278C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_754_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2794) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_755_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x279C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_756_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_757_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_758_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_759_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_760_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_761_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_762_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_763_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_764_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_765_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_766_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_767_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x27FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_768_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2804) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_769_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x280C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_770_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2814) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_771_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x281C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_772_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2824) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_773_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x282C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_774_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2834) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_775_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x283C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_776_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2844) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_777_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x284C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_778_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2854) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_779_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x285C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_780_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2864) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_781_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x286C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_782_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2874) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_783_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x287C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_784_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2884) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_785_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x288C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_786_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2894) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_787_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x289C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_788_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_789_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_790_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_791_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_792_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_793_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_794_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_795_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_796_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_797_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_798_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_799_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x28FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_800_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2904) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_801_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x290C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_802_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2914) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_803_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x291C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_804_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2924) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_805_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x292C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_806_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2934) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_807_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x293C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_808_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2944) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_809_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x294C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_810_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2954) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_811_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x295C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_812_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2964) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_813_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x296C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_814_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2974) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_815_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x297C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_816_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2984) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_817_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x298C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_818_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2994) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_819_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x299C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_820_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_821_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_822_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_823_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_824_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_825_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_826_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_827_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_828_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_829_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_830_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_831_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x29FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_832_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_833_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_834_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_835_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_836_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_837_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_838_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_839_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_840_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_841_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_842_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_843_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_844_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_845_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_846_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_847_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_848_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_849_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_850_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_851_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2A9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_852_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_853_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_854_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_855_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ABC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_856_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_857_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ACC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_858_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_859_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ADC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_860_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_861_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_862_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_863_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2AFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_864_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_865_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_866_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_867_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_868_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_869_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_870_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_871_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_872_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_873_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_874_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_875_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_876_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_877_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_878_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_879_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_880_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_881_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_882_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_883_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2B9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_884_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_885_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_886_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_887_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_888_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_889_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_890_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_891_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_892_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_893_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_894_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_895_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2BFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_896_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_897_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_898_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_899_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_900_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_901_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_902_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_903_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_904_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_905_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_906_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_907_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_908_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_909_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_910_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_911_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_912_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_913_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_914_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_915_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2C9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_916_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_917_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_918_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_919_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_920_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_921_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_922_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_923_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_924_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_925_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_926_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_927_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2CFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_928_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_929_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_930_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_931_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_932_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_933_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_934_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_935_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_936_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_937_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_938_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_939_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_940_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_941_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_942_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_943_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_944_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_945_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_946_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_947_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2D9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_948_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_949_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_950_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_951_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_952_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_953_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_954_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_955_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_956_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_957_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_958_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_959_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2DFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_960_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_961_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_962_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_963_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_964_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_965_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_966_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_967_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_968_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_969_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_970_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_971_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_972_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_973_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_974_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_975_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_976_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_977_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_978_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_979_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2E9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_980_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_981_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_982_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_983_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_984_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_985_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ECC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_986_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2ED4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_987_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_988_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_989_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_990_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_991_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2EFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_992_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_993_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_994_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_995_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_996_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_997_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_998_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_999_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2F9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_PF_REG_CQHDBL_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_PF_REG_BASE + 0x2FFC) /* CQ Ring head doorbell */ + +/* HIPCIEC50_AP_NVME_VF_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_BASE (0x240000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_NVME_VF_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_CAP_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x0) /* NVMe Controller Capabilities Low */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_CAP_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x4) /* NVMe Controller Capabilities High */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_VS_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x8) /* NVMe Controller Version */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_INTMS_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0xC) /* NVMe Controller Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_INTMC_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10) /* NVMe Controller Interrupt Clear */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_CONFIG_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14) /* NVMe Controller Configuration */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_CTRL_STATUS_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C) /* NVMe Controller Status */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_NVME_SUBSYS_RST_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20) /* NVMe subsystem Reset */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_AQA_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24) /* NVMe Admin Queue Attributes */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_ASQB_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28) /* NVMe Admin Submission Queue Base Addrss low */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_ASQB_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C) /* NVMe Admin Submission Queue Base Addrss high */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_ACQB_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x30) /* NVMe Admin Completion Queue Base Address low */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_ACQB_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x34) /* NVMe Admin Completion Queue Base Address high */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CMBLOC_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x38) /* NVMe Controller Memory Buffer Location */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CMBSZ_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x3C) /* NVMe Controller Memory Buffer Size */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CMBMSC_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x50) /* NVME ARM Driver Updata Low */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CMBMSC_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x54) /* NVME ARM Driver Updata Low */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CMBSTS_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x58) /* Controller Memory Buffer Status */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_PMRCAP_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0xE00) /* Persistent Memory Region Capabilities */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_PMRMSC_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0xE14) /* Persistent Memory Region Memory Space Control */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_PMRMSC_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0xE18) /* Persistent Memory Region Memory Space Control */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_ARM_DRV_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0xEFC) /* NVME ARM Driver Updata */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_0_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1000) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1008) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_2_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1010) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_3_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1018) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_4_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1020) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_5_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1028) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_6_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1030) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_7_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1038) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_8_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1040) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_9_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1048) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_10_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1050) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_11_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1058) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_12_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1060) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_13_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1068) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_14_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1070) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_15_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1078) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_16_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1080) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_17_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1088) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_18_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1090) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_19_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1098) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_20_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_21_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_22_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_23_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_24_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_25_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_26_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_27_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_28_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_29_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_30_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_31_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_32_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1100) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_33_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1108) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_34_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1110) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_35_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1118) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_36_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1120) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_37_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1128) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_38_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1130) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_39_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1138) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_40_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1140) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_41_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1148) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_42_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1150) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_43_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1158) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_44_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1160) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_45_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1168) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_46_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1170) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_47_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1178) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_48_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1180) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_49_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1188) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_50_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1190) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_51_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1198) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_52_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_53_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_54_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_55_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_56_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_57_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_58_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_59_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_60_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_61_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_62_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_63_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_64_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1200) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_65_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1208) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_66_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1210) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_67_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1218) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_68_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1220) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_69_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1228) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_70_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1230) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_71_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1238) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_72_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1240) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_73_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1248) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_74_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1250) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_75_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1258) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_76_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1260) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_77_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1268) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_78_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1270) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_79_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1278) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_80_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1280) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_81_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1288) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_82_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1290) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_83_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1298) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_84_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_85_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_86_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_87_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_88_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_89_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_90_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_91_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_92_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_93_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_94_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_95_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_96_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1300) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_97_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1308) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_98_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1310) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_99_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1318) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_100_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1320) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_101_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1328) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_102_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1330) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_103_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1338) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_104_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1340) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_105_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1348) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_106_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1350) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_107_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1358) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_108_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1360) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_109_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1368) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_110_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1370) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_111_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1378) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_112_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1380) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_113_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1388) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_114_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1390) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_115_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1398) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_116_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_117_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_118_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_119_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_120_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_121_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_122_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_123_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_124_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_125_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_126_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_127_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_128_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1400) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_129_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1408) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_130_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1410) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_131_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1418) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_132_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1420) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_133_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1428) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_134_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1430) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_135_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1438) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_136_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1440) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_137_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1448) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_138_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1450) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_139_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1458) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_140_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1460) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_141_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1468) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_142_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1470) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_143_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1478) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_144_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1480) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_145_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1488) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_146_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1490) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_147_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1498) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_148_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_149_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_150_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_151_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_152_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_153_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_154_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_155_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_156_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_157_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_158_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_159_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_160_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1500) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_161_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1508) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_162_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1510) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_163_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1518) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_164_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1520) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_165_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1528) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_166_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1530) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_167_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1538) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_168_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1540) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_169_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1548) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_170_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1550) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_171_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1558) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_172_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1560) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_173_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1568) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_174_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1570) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_175_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1578) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_176_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1580) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_177_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1588) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_178_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1590) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_179_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1598) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_180_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_181_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_182_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_183_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_184_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_185_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_186_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_187_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_188_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_189_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_190_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_191_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_192_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1600) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_193_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1608) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_194_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1610) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_195_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1618) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_196_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1620) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_197_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1628) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_198_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1630) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_199_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1638) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_200_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1640) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_201_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1648) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_202_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1650) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_203_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1658) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_204_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1660) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_205_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1668) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_206_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1670) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_207_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1678) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_208_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1680) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_209_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1688) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_210_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1690) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_211_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1698) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_212_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_213_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_214_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_215_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_216_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_217_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_218_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_219_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_220_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_221_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_222_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_223_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_224_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1700) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_225_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1708) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_226_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1710) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_227_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1718) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_228_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1720) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_229_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1728) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_230_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1730) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_231_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1738) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_232_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1740) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_233_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1748) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_234_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1750) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_235_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1758) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_236_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1760) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_237_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1768) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_238_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1770) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_239_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1778) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_240_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1780) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_241_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1788) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_242_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1790) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_243_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1798) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_244_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_245_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_246_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_247_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_248_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_249_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_250_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_251_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_252_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_253_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_254_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_255_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_256_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1800) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_257_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1808) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_258_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1810) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_259_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1818) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_260_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1820) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_261_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1828) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_262_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1830) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_263_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1838) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_264_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1840) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_265_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1848) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_266_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1850) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_267_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1858) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_268_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1860) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_269_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1868) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_270_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1870) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_271_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1878) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_272_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1880) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_273_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1888) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_274_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1890) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_275_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1898) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_276_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_277_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_278_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_279_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_280_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_281_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_282_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_283_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_284_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_285_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_286_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_287_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_288_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1900) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_289_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1908) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_290_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1910) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_291_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1918) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_292_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1920) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_293_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1928) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_294_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1930) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_295_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1938) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_296_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1940) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_297_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1948) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_298_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1950) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_299_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1958) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_300_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1960) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_301_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1968) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_302_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1970) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_303_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1978) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_304_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1980) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_305_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1988) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_306_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1990) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_307_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1998) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_308_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_309_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_310_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_311_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_312_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_313_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_314_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_315_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_316_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_317_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_318_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_319_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_320_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_321_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_322_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_323_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_324_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_325_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_326_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_327_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_328_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_329_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_330_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_331_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_332_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_333_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_334_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_335_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_336_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_337_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_338_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_339_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_340_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_341_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_342_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_343_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_344_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_345_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_346_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_347_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_348_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_349_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_350_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_351_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_352_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_353_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_354_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_355_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_356_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_357_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_358_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_359_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_360_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_361_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_362_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_363_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_364_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_365_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_366_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_367_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_368_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_369_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_370_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_371_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_372_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_373_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_374_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_375_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_376_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_377_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_378_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_379_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_380_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_381_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_382_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_383_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_384_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_385_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_386_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_387_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_388_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_389_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_390_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_391_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_392_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_393_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_394_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_395_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_396_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_397_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_398_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_399_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_400_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_401_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_402_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_403_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_404_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_405_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_406_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_407_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_408_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_409_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_410_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_411_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_412_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_413_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_414_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_415_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_416_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_417_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_418_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_419_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_420_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_421_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_422_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_423_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_424_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_425_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_426_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_427_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_428_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_429_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_430_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_431_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_432_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_433_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_434_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_435_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_436_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_437_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_438_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_439_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_440_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_441_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_442_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_443_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_444_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_445_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_446_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_447_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_448_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_449_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_450_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_451_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_452_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_453_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_454_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_455_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_456_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_457_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_458_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_459_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_460_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_461_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_462_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_463_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_464_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_465_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_466_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_467_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_468_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_469_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_470_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_471_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_472_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_473_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_474_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ED0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_475_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ED8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_476_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_477_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_478_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_479_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_480_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_481_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_482_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_483_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_484_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_485_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_486_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_487_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_488_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_489_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_490_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_491_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_492_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_493_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_494_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_495_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_496_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_497_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_498_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_499_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_500_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_501_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_502_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_503_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_504_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_505_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_506_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_507_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_508_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_509_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_510_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_511_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_512_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2000) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_513_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2008) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_514_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2010) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_515_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2018) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_516_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2020) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_517_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2028) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_518_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2030) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_519_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2038) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_520_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2040) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_521_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2048) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_522_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2050) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_523_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2058) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_524_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2060) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_525_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2068) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_526_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2070) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_527_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2078) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_528_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2080) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_529_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2088) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_530_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2090) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_531_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2098) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_532_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_533_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_534_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_535_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_536_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_537_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_538_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_539_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_540_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_541_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_542_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_543_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_544_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2100) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_545_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2108) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_546_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2110) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_547_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2118) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_548_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2120) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_549_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2128) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_550_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2130) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_551_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2138) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_552_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2140) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_553_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2148) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_554_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2150) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_555_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2158) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_556_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2160) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_557_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2168) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_558_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2170) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_559_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2178) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_560_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2180) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_561_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2188) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_562_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2190) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_563_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2198) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_564_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_565_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_566_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_567_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_568_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_569_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_570_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_571_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_572_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_573_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_574_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_575_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_576_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2200) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_577_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2208) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_578_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2210) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_579_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2218) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_580_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2220) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_581_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2228) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_582_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2230) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_583_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2238) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_584_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2240) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_585_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2248) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_586_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2250) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_587_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2258) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_588_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2260) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_589_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2268) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_590_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2270) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_591_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2278) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_592_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2280) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_593_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2288) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_594_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2290) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_595_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2298) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_596_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_597_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_598_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_599_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_600_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_601_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_602_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_603_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_604_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_605_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_606_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_607_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_608_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2300) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_609_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2308) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_610_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2310) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_611_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2318) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_612_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2320) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_613_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2328) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_614_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2330) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_615_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2338) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_616_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2340) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_617_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2348) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_618_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2350) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_619_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2358) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_620_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2360) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_621_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2368) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_622_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2370) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_623_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2378) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_624_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2380) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_625_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2388) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_626_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2390) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_627_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2398) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_628_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_629_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_630_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_631_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_632_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_633_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_634_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_635_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_636_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_637_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_638_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_639_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_640_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2400) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_641_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2408) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_642_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2410) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_643_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2418) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_644_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2420) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_645_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2428) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_646_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2430) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_647_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2438) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_648_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2440) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_649_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2448) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_650_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2450) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_651_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2458) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_652_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2460) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_653_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2468) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_654_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2470) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_655_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2478) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_656_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2480) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_657_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2488) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_658_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2490) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_659_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2498) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_660_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_661_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_662_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_663_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_664_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_665_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_666_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_667_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_668_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_669_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_670_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_671_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_672_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2500) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_673_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2508) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_674_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2510) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_675_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2518) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_676_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2520) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_677_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2528) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_678_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2530) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_679_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2538) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_680_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2540) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_681_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2548) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_682_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2550) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_683_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2558) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_684_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2560) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_685_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2568) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_686_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2570) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_687_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2578) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_688_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2580) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_689_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2588) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_690_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2590) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_691_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2598) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_692_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_693_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_694_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_695_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_696_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_697_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_698_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_699_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_700_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_701_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_702_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_703_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_704_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2600) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_705_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2608) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_706_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2610) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_707_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2618) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_708_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2620) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_709_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2628) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_710_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2630) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_711_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2638) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_712_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2640) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_713_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2648) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_714_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2650) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_715_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2658) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_716_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2660) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_717_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2668) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_718_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2670) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_719_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2678) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_720_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2680) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_721_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2688) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_722_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2690) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_723_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2698) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_724_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_725_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_726_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_727_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_728_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_729_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_730_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_731_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_732_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_733_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_734_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_735_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_736_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2700) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_737_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2708) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_738_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2710) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_739_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2718) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_740_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2720) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_741_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2728) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_742_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2730) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_743_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2738) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_744_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2740) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_745_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2748) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_746_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2750) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_747_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2758) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_748_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2760) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_749_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2768) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_750_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2770) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_751_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2778) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_752_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2780) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_753_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2788) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_754_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2790) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_755_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2798) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_756_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_757_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_758_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_759_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_760_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_761_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_762_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_763_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_764_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_765_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_766_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_767_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_768_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2800) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_769_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2808) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_770_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2810) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_771_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2818) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_772_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2820) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_773_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2828) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_774_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2830) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_775_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2838) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_776_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2840) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_777_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2848) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_778_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2850) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_779_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2858) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_780_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2860) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_781_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2868) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_782_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2870) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_783_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2878) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_784_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2880) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_785_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2888) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_786_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2890) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_787_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2898) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_788_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_789_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_790_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_791_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_792_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_793_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_794_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_795_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_796_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_797_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_798_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_799_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_800_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2900) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_801_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2908) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_802_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2910) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_803_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2918) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_804_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2920) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_805_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2928) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_806_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2930) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_807_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2938) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_808_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2940) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_809_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2948) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_810_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2950) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_811_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2958) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_812_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2960) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_813_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2968) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_814_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2970) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_815_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2978) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_816_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2980) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_817_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2988) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_818_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2990) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_819_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2998) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_820_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29A0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_821_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29A8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_822_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29B0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_823_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29B8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_824_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29C0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_825_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29C8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_826_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29D0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_827_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29D8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_828_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29E0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_829_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29E8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_830_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29F0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_831_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29F8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_832_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_833_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_834_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_835_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_836_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_837_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_838_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_839_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_840_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_841_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_842_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_843_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_844_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_845_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_846_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_847_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_848_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_849_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_850_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_851_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_852_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_853_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_854_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_855_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_856_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_857_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_858_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_859_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_860_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_861_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_862_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_863_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_864_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_865_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_866_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_867_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_868_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_869_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_870_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_871_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_872_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_873_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_874_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_875_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_876_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_877_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_878_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_879_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_880_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_881_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_882_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_883_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_884_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_885_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_886_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_887_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_888_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_889_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_890_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_891_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_892_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_893_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_894_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_895_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_896_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_897_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_898_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_899_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_900_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_901_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_902_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_903_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_904_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_905_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_906_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_907_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_908_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_909_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_910_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_911_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_912_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_913_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_914_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_915_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_916_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_917_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_918_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_919_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_920_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_921_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_922_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_923_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_924_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_925_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_926_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_927_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_928_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_929_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_930_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_931_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_932_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_933_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_934_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_935_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_936_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_937_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_938_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_939_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_940_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_941_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_942_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_943_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_944_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_945_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_946_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_947_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_948_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_949_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_950_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_951_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_952_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_953_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_954_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_955_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_956_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_957_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_958_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_959_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_960_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_961_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_962_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_963_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_964_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_965_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_966_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_967_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_968_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_969_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_970_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_971_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_972_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_973_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_974_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_975_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_976_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_977_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_978_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_979_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_980_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_981_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_982_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_983_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_984_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_985_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_986_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ED0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_987_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ED8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_988_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_989_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_990_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_991_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_992_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F00) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_993_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F08) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_994_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F10) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_995_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F18) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_996_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F20) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_997_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F28) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_998_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F30) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_999_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F38) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F40) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F48) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F50) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F58) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F60) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F68) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F70) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F78) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F80) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F88) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F90) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F98) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FA0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FA8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FB0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FB8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FC0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FC8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FD0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FD8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FE0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FE8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FF0) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_SQTDBL_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FF8) /* SQ Ring tail doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_0_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1004) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x100C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_2_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1014) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_3_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x101C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_4_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1024) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_5_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x102C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_6_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1034) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_7_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x103C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_8_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1044) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_9_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x104C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_10_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1054) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_11_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x105C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_12_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1064) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_13_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x106C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_14_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1074) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_15_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x107C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_16_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1084) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_17_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x108C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_18_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1094) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_19_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x109C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_20_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_21_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_22_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_23_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_24_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_25_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_26_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_27_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_28_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_29_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_30_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_31_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x10FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_32_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1104) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_33_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x110C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_34_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1114) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_35_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x111C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_36_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1124) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_37_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x112C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_38_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1134) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_39_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x113C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_40_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1144) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_41_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x114C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_42_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1154) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_43_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x115C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_44_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1164) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_45_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x116C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_46_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1174) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_47_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x117C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_48_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1184) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_49_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x118C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_50_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1194) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_51_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x119C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_52_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_53_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_54_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_55_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_56_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_57_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_58_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_59_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_60_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_61_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_62_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_63_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x11FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_64_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1204) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_65_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x120C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_66_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1214) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_67_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x121C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_68_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1224) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_69_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x122C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_70_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1234) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_71_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x123C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_72_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1244) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_73_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x124C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_74_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1254) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_75_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x125C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_76_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1264) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_77_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x126C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_78_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1274) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_79_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x127C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_80_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1284) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_81_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x128C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_82_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1294) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_83_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x129C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_84_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_85_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_86_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_87_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_88_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_89_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_90_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_91_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_92_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_93_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_94_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_95_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x12FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_96_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1304) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_97_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x130C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_98_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1314) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_99_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x131C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_100_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1324) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_101_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x132C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_102_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1334) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_103_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x133C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_104_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1344) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_105_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x134C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_106_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1354) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_107_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x135C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_108_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1364) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_109_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x136C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_110_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1374) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_111_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x137C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_112_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1384) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_113_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x138C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_114_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1394) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_115_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x139C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_116_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_117_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_118_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_119_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_120_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_121_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_122_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_123_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_124_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_125_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_126_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_127_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x13FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_128_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1404) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_129_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x140C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_130_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1414) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_131_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x141C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_132_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1424) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_133_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x142C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_134_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1434) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_135_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x143C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_136_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1444) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_137_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x144C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_138_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1454) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_139_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x145C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_140_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1464) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_141_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x146C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_142_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1474) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_143_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x147C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_144_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1484) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_145_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x148C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_146_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1494) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_147_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x149C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_148_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_149_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_150_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_151_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_152_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_153_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_154_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_155_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_156_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_157_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_158_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_159_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x14FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_160_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1504) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_161_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x150C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_162_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1514) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_163_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x151C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_164_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1524) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_165_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x152C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_166_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1534) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_167_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x153C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_168_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1544) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_169_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x154C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_170_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1554) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_171_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x155C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_172_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1564) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_173_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x156C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_174_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1574) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_175_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x157C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_176_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1584) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_177_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x158C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_178_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1594) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_179_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x159C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_180_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_181_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_182_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_183_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_184_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_185_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_186_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_187_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_188_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_189_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_190_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_191_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x15FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_192_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1604) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_193_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x160C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_194_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1614) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_195_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x161C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_196_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1624) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_197_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x162C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_198_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1634) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_199_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x163C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_200_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1644) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_201_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x164C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_202_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1654) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_203_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x165C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_204_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1664) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_205_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x166C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_206_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1674) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_207_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x167C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_208_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1684) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_209_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x168C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_210_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1694) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_211_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x169C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_212_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_213_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_214_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_215_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_216_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_217_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_218_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_219_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_220_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_221_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_222_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_223_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x16FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_224_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1704) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_225_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x170C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_226_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1714) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_227_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x171C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_228_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1724) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_229_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x172C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_230_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1734) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_231_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x173C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_232_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1744) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_233_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x174C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_234_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1754) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_235_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x175C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_236_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1764) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_237_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x176C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_238_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1774) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_239_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x177C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_240_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1784) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_241_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x178C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_242_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1794) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_243_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x179C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_244_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_245_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_246_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_247_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_248_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_249_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_250_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_251_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_252_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_253_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_254_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_255_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x17FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_256_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1804) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_257_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x180C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_258_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1814) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_259_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x181C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_260_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1824) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_261_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x182C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_262_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1834) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_263_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x183C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_264_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1844) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_265_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x184C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_266_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1854) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_267_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x185C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_268_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1864) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_269_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x186C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_270_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1874) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_271_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x187C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_272_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1884) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_273_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x188C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_274_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1894) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_275_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x189C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_276_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_277_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_278_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_279_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_280_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_281_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_282_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_283_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_284_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_285_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_286_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_287_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x18FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_288_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1904) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_289_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x190C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_290_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1914) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_291_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x191C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_292_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1924) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_293_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x192C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_294_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1934) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_295_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x193C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_296_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1944) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_297_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x194C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_298_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1954) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_299_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x195C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_300_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1964) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_301_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x196C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_302_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1974) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_303_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x197C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_304_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1984) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_305_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x198C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_306_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1994) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_307_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x199C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_308_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_309_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_310_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_311_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_312_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_313_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_314_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_315_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_316_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_317_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_318_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_319_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x19FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_320_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_321_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_322_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_323_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_324_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_325_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_326_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_327_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_328_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_329_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_330_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_331_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_332_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_333_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_334_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_335_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_336_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_337_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_338_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_339_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1A9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_340_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_341_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_342_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_343_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ABC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_344_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_345_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ACC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_346_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_347_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ADC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_348_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_349_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_350_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_351_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1AFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_352_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_353_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_354_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_355_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_356_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_357_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_358_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_359_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_360_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_361_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_362_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_363_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_364_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_365_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_366_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_367_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_368_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_369_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_370_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_371_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1B9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_372_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_373_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_374_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_375_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_376_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_377_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_378_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_379_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_380_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_381_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_382_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_383_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1BFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_384_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_385_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_386_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_387_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_388_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_389_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_390_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_391_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_392_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_393_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_394_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_395_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_396_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_397_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_398_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_399_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_400_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_401_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_402_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_403_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1C9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_404_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_405_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_406_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_407_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_408_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_409_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_410_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_411_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_412_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_413_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_414_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_415_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1CFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_416_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_417_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_418_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_419_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_420_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_421_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_422_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_423_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_424_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_425_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_426_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_427_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_428_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_429_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_430_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_431_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_432_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_433_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_434_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_435_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1D9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_436_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_437_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_438_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_439_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_440_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_441_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_442_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_443_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_444_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_445_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_446_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_447_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1DFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_448_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_449_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_450_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_451_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_452_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_453_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_454_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_455_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_456_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_457_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_458_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_459_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_460_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_461_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_462_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_463_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_464_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_465_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_466_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_467_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1E9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_468_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_469_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_470_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_471_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_472_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_473_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ECC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_474_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1ED4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_475_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_476_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_477_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_478_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_479_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1EFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_480_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_481_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_482_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_483_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_484_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_485_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_486_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_487_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_488_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_489_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_490_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_491_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_492_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_493_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_494_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_495_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_496_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_497_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_498_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_499_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1F9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_500_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_501_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_502_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_503_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_504_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_505_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_506_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_507_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_508_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_509_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_510_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_511_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x1FFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_512_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2004) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_513_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x200C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_514_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2014) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_515_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x201C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_516_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2024) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_517_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x202C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_518_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2034) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_519_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x203C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_520_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2044) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_521_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x204C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_522_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2054) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_523_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x205C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_524_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2064) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_525_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x206C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_526_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2074) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_527_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x207C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_528_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2084) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_529_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x208C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_530_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2094) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_531_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x209C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_532_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_533_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_534_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_535_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_536_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_537_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_538_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_539_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_540_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_541_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_542_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_543_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x20FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_544_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2104) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_545_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x210C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_546_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2114) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_547_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x211C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_548_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2124) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_549_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x212C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_550_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2134) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_551_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x213C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_552_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2144) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_553_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x214C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_554_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2154) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_555_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x215C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_556_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2164) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_557_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x216C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_558_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2174) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_559_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x217C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_560_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2184) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_561_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x218C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_562_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2194) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_563_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x219C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_564_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_565_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_566_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_567_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_568_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_569_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_570_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_571_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_572_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_573_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_574_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_575_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x21FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_576_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2204) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_577_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x220C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_578_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2214) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_579_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x221C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_580_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2224) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_581_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x222C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_582_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2234) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_583_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x223C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_584_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2244) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_585_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x224C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_586_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2254) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_587_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x225C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_588_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2264) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_589_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x226C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_590_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2274) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_591_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x227C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_592_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2284) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_593_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x228C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_594_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2294) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_595_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x229C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_596_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_597_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_598_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_599_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_600_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_601_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_602_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_603_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_604_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_605_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_606_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_607_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x22FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_608_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2304) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_609_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x230C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_610_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2314) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_611_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x231C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_612_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2324) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_613_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x232C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_614_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2334) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_615_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x233C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_616_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2344) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_617_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x234C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_618_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2354) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_619_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x235C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_620_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2364) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_621_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x236C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_622_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2374) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_623_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x237C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_624_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2384) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_625_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x238C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_626_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2394) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_627_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x239C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_628_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_629_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_630_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_631_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_632_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_633_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_634_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_635_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_636_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_637_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_638_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_639_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x23FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_640_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2404) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_641_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x240C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_642_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2414) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_643_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x241C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_644_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2424) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_645_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x242C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_646_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2434) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_647_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x243C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_648_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2444) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_649_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x244C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_650_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2454) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_651_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x245C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_652_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2464) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_653_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x246C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_654_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2474) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_655_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x247C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_656_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2484) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_657_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x248C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_658_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2494) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_659_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x249C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_660_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_661_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_662_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_663_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_664_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_665_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_666_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_667_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_668_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_669_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_670_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_671_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x24FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_672_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2504) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_673_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x250C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_674_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2514) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_675_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x251C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_676_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2524) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_677_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x252C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_678_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2534) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_679_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x253C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_680_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2544) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_681_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x254C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_682_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2554) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_683_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x255C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_684_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2564) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_685_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x256C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_686_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2574) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_687_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x257C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_688_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2584) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_689_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x258C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_690_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2594) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_691_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x259C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_692_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_693_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_694_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_695_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_696_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_697_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_698_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_699_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_700_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_701_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_702_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_703_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x25FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_704_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2604) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_705_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x260C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_706_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2614) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_707_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x261C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_708_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2624) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_709_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x262C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_710_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2634) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_711_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x263C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_712_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2644) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_713_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x264C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_714_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2654) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_715_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x265C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_716_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2664) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_717_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x266C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_718_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2674) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_719_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x267C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_720_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2684) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_721_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x268C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_722_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2694) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_723_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x269C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_724_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_725_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_726_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_727_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_728_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_729_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_730_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_731_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_732_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_733_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_734_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_735_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x26FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_736_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2704) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_737_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x270C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_738_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2714) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_739_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x271C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_740_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2724) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_741_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x272C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_742_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2734) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_743_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x273C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_744_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2744) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_745_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x274C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_746_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2754) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_747_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x275C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_748_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2764) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_749_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x276C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_750_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2774) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_751_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x277C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_752_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2784) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_753_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x278C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_754_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2794) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_755_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x279C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_756_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_757_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_758_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_759_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_760_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_761_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_762_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_763_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_764_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_765_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_766_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_767_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x27FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_768_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2804) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_769_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x280C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_770_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2814) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_771_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x281C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_772_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2824) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_773_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x282C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_774_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2834) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_775_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x283C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_776_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2844) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_777_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x284C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_778_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2854) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_779_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x285C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_780_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2864) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_781_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x286C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_782_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2874) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_783_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x287C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_784_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2884) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_785_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x288C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_786_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2894) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_787_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x289C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_788_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_789_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_790_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_791_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_792_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_793_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_794_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_795_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_796_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_797_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_798_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_799_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x28FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_800_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2904) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_801_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x290C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_802_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2914) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_803_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x291C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_804_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2924) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_805_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x292C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_806_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2934) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_807_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x293C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_808_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2944) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_809_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x294C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_810_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2954) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_811_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x295C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_812_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2964) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_813_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x296C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_814_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2974) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_815_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x297C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_816_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2984) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_817_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x298C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_818_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2994) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_819_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x299C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_820_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29A4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_821_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29AC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_822_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29B4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_823_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29BC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_824_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29C4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_825_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29CC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_826_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29D4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_827_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29DC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_828_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29E4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_829_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29EC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_830_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29F4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_831_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x29FC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_832_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_833_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_834_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_835_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_836_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_837_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_838_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_839_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_840_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_841_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_842_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_843_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_844_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_845_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_846_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_847_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_848_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_849_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_850_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_851_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2A9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_852_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_853_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_854_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_855_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ABC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_856_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_857_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ACC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_858_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_859_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ADC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_860_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_861_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_862_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_863_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2AFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_864_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_865_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_866_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_867_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_868_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_869_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_870_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_871_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_872_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_873_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_874_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_875_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_876_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_877_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_878_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_879_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_880_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_881_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_882_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_883_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2B9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_884_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_885_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_886_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_887_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_888_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_889_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_890_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_891_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_892_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_893_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_894_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_895_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2BFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_896_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_897_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_898_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_899_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_900_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_901_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_902_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_903_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_904_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_905_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_906_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_907_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_908_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_909_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_910_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_911_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_912_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_913_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_914_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_915_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2C9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_916_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_917_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_918_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_919_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_920_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_921_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_922_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_923_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_924_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_925_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_926_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_927_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2CFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_928_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_929_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_930_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_931_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_932_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_933_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_934_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_935_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_936_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_937_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_938_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_939_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_940_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_941_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_942_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_943_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_944_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_945_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_946_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_947_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2D9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_948_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_949_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_950_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_951_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_952_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_953_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_954_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_955_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_956_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_957_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_958_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_959_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2DFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_960_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_961_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_962_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_963_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_964_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_965_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_966_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_967_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_968_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_969_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_970_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_971_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_972_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_973_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_974_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_975_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_976_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_977_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_978_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_979_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2E9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_980_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_981_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_982_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_983_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_984_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_985_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ECC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_986_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2ED4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_987_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_988_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_989_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_990_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_991_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2EFC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_992_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F04) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_993_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F0C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_994_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F14) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_995_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F1C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_996_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F24) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_997_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F2C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_998_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F34) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_999_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F3C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F44) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F4C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F54) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F5C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F64) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F6C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F74) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F7C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F84) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F8C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F94) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2F9C) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FA4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FAC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FB4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FBC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FC4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FCC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FD4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FDC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FE4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FEC) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FF4) /* CQ Ring head doorbell */ +#define CSR_HIPCIEC50_AP_NVME_VF_REG_CQHDBL_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_VF_REG_BASE + 0x2FFC) /* CQ Ring head doorbell */ + +/* HIPCIEC50_AP_NVME_GLOBAL_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE (0x2C0000) + +/* **************************************************************************** */ +/* HIPCIEC50_AP_NVME_GLOBAL_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x100) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x180) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x200) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x280) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x300) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x380) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x400) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x480) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x500) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x580) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x600) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x680) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x700) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x780) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x800) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x880) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x900) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x980) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA00) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB00) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC00) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD00) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE00) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF00) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF80) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x104) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x184) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x204) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x284) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x304) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x384) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x404) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x484) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x504) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x584) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x604) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x684) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x704) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x784) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x804) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x884) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x904) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x984) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA04) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB04) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC04) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD04) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE04) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF04) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF84) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x108) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x188) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x208) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x288) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x308) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x388) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x408) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x488) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x508) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x588) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x608) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x688) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x708) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x788) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x808) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x888) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x908) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x988) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA08) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB08) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC08) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD08) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE08) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF08) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF88) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x18C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x20C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x28C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x30C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x38C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x40C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x48C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x50C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x58C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x60C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x68C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x70C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x78C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x88C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD0C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE0C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF0C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_CTRL_REG_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF8C) /* Write Controller Register Interrupt Ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x110) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x190) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x210) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x290) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x310) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x390) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x410) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x490) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x510) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x590) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x610) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x690) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x710) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x790) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x810) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x890) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x910) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x990) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF10) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_IEP_INT_MODE_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF90) /* pf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x114) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x194) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x214) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x294) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x314) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x394) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x414) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x494) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x514) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x594) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x614) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x694) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x714) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x794) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x814) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x894) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x914) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x994) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF14) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_QUEUE_NUM_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF94) /* nvme queue number in pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x118) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x198) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x218) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x298) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x318) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x398) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x418) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x498) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x518) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x598) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x618) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x698) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x718) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x798) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x818) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x898) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x918) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x998) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF18) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_QUEUE_NUM_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF98) /* nvme queue num in vf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x19C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x21C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x29C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x31C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x39C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x41C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x49C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x51C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x59C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x61C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x69C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x71C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x79C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x81C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x89C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF1C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_STRD_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF9C) /* doorbell strd for pf and vfs of pf */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x120) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x220) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x2A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x320) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x3A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x420) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x4A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x520) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x620) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x720) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x7A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x820) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x920) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xDA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xEA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF20) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_LOW_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xFA0) /* PF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x124) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x224) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x2A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x324) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x3A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x424) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x4A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x524) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x624) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x724) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x7A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x824) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x924) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xDA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xEA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF24) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_BAR0_DB_ATU_HIGH_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xFA4) /* PF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x128) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x228) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x2A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x328) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x3A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x428) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x4A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x528) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x628) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x728) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x7A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x828) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x928) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xDA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xEA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF28) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_LOW_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xFA8) /* PF VF BAR0 doorbell ATU Register Low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x22C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x2AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x32C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x3AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x42C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x4AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x52C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x62C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x72C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x7AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x82C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xD2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xDAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xE2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xEAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xF2C) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VF_BAR0_DB_ATU_HIGH_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xFAC) /* PF VF BAR0 doorbell ATU Register High */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1000) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1020) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1040) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1060) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1080) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1100) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1120) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1140) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1160) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1180) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1200) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1220) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1240) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1260) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1280) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1300) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1320) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1340) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1360) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1380) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1400) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1420) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1440) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1460) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1480) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1500) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1520) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1540) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1560) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1580) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1600) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1620) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1640) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1660) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1680) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1700) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1720) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1740) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1760) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1780) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17A0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17C0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_MASK_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17E0) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1004) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1024) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1044) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1064) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1084) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1104) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1124) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1144) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1164) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1184) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1204) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1224) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1244) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1264) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1284) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1304) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1324) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1344) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1364) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1384) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1404) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1424) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1444) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1464) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1484) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1504) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1524) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1544) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1564) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1584) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1604) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1624) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1644) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1664) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1684) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1704) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1724) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1744) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1764) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1784) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17A4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17C4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_STS_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17E4) /* Write Controller Register Interrupt Status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1008) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1028) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1048) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1068) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1088) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1108) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1128) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1148) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1168) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1188) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1208) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1228) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1248) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1268) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1288) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1308) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1328) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1348) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1368) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1388) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1408) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1428) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1448) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1468) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1488) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1508) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1528) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1548) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1568) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1588) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1608) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1628) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1648) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1668) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1688) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1708) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1728) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1748) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1768) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1788) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17A8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17C8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_SET_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17E8) /* Write Controller Register Interrupt Set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x100C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x102C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x104C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x106C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x108C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x110C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x112C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x114C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x116C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x118C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x120C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x122C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x124C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x126C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x128C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x130C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x132C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x134C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x136C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x138C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x140C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x142C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x144C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x146C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x148C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x150C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x152C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x154C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x156C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x158C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x160C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x162C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x164C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x166C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x168C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x170C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x172C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x174C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x176C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x178C) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17AC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17CC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_CTRL_REG_INT_RO_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17EC) /* Write Controller Register Interrupt Mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1010) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1030) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1050) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1070) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1090) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x10F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1110) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1130) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1150) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1170) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1190) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x11F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1210) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1230) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1250) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1270) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1290) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x12F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1310) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1330) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1350) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1370) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1390) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x13F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1410) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1430) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1450) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1470) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1490) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x14F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1510) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1530) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1550) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1570) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1590) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x15F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1610) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1630) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1650) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1670) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1690) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x16F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1710) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1730) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1750) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1770) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x1790) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17B0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17D0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_IEP_INT_MODE_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x17F0) /* vf_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5000) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5004) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5008) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x500C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5010) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5014) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5018) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x501C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5020) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5024) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5028) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x502C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5030) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5034) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5038) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x503C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5040) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5044) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5048) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x504C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5050) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5054) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5058) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x505C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5060) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5064) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5068) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x506C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5070) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5074) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5078) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x507C) /* cqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5100) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5104) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5108) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x510C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5110) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5114) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5118) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x511C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5120) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5124) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5128) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x512C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5130) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5134) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5138) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x513C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5140) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5144) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5148) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x514C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5150) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5154) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5158) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x515C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5160) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5164) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5168) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x516C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5170) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5174) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5178) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x517C) /* cqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5200) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5204) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5208) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x520C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5210) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5214) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5218) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x521C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5220) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5224) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5228) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x522C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5230) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5234) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5238) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x523C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5240) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5244) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5248) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x524C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5250) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5254) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5258) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x525C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5260) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5264) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5268) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x526C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5270) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5274) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5278) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x527C) /* cqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5300) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5304) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5308) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x530C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5310) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5314) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5318) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x531C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5320) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5324) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5328) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x532C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5330) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5334) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5338) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x533C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5340) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5344) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5348) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x534C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5350) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5354) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5358) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x535C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5360) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5364) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5368) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x536C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5370) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5374) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5378) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQDB_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x537C) /* cqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5400) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5404) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5408) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x540C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5410) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5414) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5418) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x541C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5420) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5424) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5428) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x542C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5430) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5434) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5438) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x543C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5440) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5444) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5448) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x544C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5450) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5454) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5458) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x545C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5460) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5464) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5468) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x546C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5470) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5474) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5478) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x547C) /* sqdb_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5500) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5504) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5508) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x550C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5510) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5514) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5518) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x551C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5520) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5524) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5528) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x552C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5530) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5534) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5538) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x553C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5540) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5544) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5548) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x554C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5550) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5554) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5558) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x555C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5560) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5564) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5568) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x556C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5570) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5574) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5578) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x557C) /* sqdb_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5600) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5604) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5608) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x560C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5610) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5614) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5618) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x561C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5620) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5624) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5628) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x562C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5630) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5634) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5638) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x563C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5640) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5644) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5648) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x564C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5650) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5654) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5658) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x565C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5660) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5664) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5668) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x566C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5670) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5674) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5678) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x567C) /* sqdb_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5700) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5704) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5708) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x570C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5710) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5714) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5718) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x571C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5720) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5724) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5728) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x572C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5730) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5734) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5738) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x573C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5740) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5744) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5748) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x574C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5750) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5754) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5758) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x575C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5760) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5764) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5768) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x576C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5770) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5774) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5778) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQDB_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x577C) /* sqdb_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5800) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5804) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5808) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x580C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5810) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5814) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5818) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x581C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5820) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5824) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5828) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x582C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5830) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5834) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5838) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x583C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5840) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5844) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5848) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x584C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5850) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5854) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5858) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x585C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5860) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5864) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5868) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x586C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5870) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5874) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5878) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x587C) /* wrptr_int mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5900) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5904) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5908) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x590C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5910) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5914) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5918) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x591C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5920) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5924) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5928) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x592C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5930) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5934) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5938) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x593C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5940) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5944) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5948) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x594C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5950) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5954) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5958) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x595C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5960) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5964) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5968) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x596C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5970) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5974) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5978) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x597C) /* wrptr_int sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A00) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A04) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A08) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A0C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A10) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A14) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A18) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A1C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A20) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A24) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A28) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A2C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A30) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A34) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A38) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A3C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A40) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A44) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A48) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A4C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A50) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A54) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A58) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A5C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A60) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A64) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A68) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A6C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A70) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A74) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A78) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5A7C) /* wrptr_int set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B00) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B04) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B08) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B0C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B10) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B14) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B18) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B1C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B20) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B24) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B28) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B2C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B30) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B34) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B38) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B3C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B40) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B44) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B48) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B4C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B50) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B54) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B58) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B5C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B60) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B64) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B68) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B6C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B70) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B74) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B78) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5B7C) /* wrptr_int ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C00) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C04) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C08) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C0C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C10) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C14) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C18) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C1C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C20) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C24) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C28) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C2C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C30) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C34) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C38) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C3C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C40) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C44) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C48) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C4C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C50) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C54) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C58) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C5C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C60) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C64) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C68) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C6C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C70) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C74) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C78) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5C7C) /* cq_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D00) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D04) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D08) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D0C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D10) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D14) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D18) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D1C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D20) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D24) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D28) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D2C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D30) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D34) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D38) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D3C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D40) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D44) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D48) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D4C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D50) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D54) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D58) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D5C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D60) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D64) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D68) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D6C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D70) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D74) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D78) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5D7C) /* cq_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E00) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E04) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E08) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E0C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E10) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E14) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E18) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E1C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E20) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E24) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E28) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E2C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E30) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E34) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E38) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E3C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E40) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E44) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E48) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E4C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E50) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E54) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E58) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E5C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E60) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E64) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E68) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E6C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E70) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E74) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E78) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5E7C) /* cq_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F00) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F04) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F08) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F0C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F10) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F14) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F18) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F1C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F20) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F24) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F28) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F2C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F30) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F34) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F38) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F3C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F40) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F44) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F48) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F4C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F50) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F54) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F58) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F5C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F60) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F64) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F68) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F6C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F70) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F74) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F78) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CQ_ERR_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x5F7C) /* cq_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6000) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6004) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6008) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x600C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6010) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6014) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6018) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x601C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6020) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6024) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6028) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x602C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6030) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6034) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6038) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x603C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6040) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6044) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6048) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x604C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6050) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6054) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6058) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x605C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6060) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6064) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6068) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x606C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6070) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6074) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6078) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x607C) /* rba_ack_err_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6100) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6104) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6108) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x610C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6110) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6114) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6118) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x611C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6120) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6124) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6128) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x612C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6130) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6134) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6138) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x613C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6140) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6144) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6148) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x614C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6150) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6154) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6158) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x615C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6160) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6164) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6168) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x616C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6170) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6174) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6178) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x617C) /* rba_ack_err_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6200) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6204) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6208) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x620C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6210) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6214) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6218) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x621C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6220) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6224) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6228) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x622C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6230) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6234) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6238) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x623C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6240) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6244) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6248) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x624C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6250) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6254) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6258) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x625C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6260) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6264) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6268) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x626C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6270) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6274) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6278) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_SET_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x627C) /* rba_ack_err_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6300) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6304) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6308) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x630C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6310) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6314) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6318) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x631C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6320) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6324) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6328) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x632C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6330) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6334) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6338) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x633C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6340) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6344) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6348) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x634C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6350) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6354) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6358) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x635C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6360) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6364) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6368) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x636C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6370) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6374) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6378) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_ACK_ERR_INT_RO_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x637C) /* rba_ack_err_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6400) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6404) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6408) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x640C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6410) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6414) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6418) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x641C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6420) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6424) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6428) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x642C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6430) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6434) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6438) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x643C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6440) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6444) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6448) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x644C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6450) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6454) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6458) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x645C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6460) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6464) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6468) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x646C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6470) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6474) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6478) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_COAL_MASK_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x647C) /* queue int coal mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6500) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6504) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6508) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x650C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6510) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6514) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6518) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x651C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6520) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6524) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6528) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x652C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6530) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6534) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6538) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x653C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6540) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6544) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6548) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x654C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6550) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6554) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6558) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x655C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6560) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6564) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6568) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x656C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6570) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6574) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6578) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_IEP_INT_MODE_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x657C) /* nvme_iep_int_mode */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6600) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6604) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6608) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x660C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6610) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6614) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6618) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x661C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6620) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6624) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6628) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x662C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6630) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6634) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6638) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x663C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6640) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6644) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6648) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x664C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6650) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6654) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6658) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x665C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6660) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6664) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6668) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x666C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6670) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6674) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6678) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_EN_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x667C) /* queue_en */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6700) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6704) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6708) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x670C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6710) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6714) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6718) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x671C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6720) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6724) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6728) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x672C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6730) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6734) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6738) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x673C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6740) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6744) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6748) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x674C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6750) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6754) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6758) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x675C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6760) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6764) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6768) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x676C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6770) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6774) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6778) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_DELETE_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x677C) /* queue_delete */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6800) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6804) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6808) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x680C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6810) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6814) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6818) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x681C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6820) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6824) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6828) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x682C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6830) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6834) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6838) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x683C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6840) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6844) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6848) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x684C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6850) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6854) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6858) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x685C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6860) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6864) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6868) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x686C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6870) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6874) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x6878) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_STS_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x687C) /* queue_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_NORMAL_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8000) /* nvme ep port normal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_NORMAL_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8040) /* nvme ep port normal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_NORMAL_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8080) /* nvme ep port normal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_NORMAL_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80C0) /* nvme ep port normal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ABNORMAL_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8004) /* nvme ep port abnormal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ABNORMAL_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8044) /* nvme ep port abnormal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ABNORMAL_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8084) /* nvme ep port abnormal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ABNORMAL_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80C4) /* nvme ep port abnormal int */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_STS_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8008) /* abnormal_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_STS_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8048) /* abnormal_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_STS_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8088) /* abnormal_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_STS_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80C8) /* abnormal_int_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_MASK_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x800C) /* abnormal_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_MASK_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x804C) /* abnormal_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_MASK_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x808C) /* abnormal_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_MASK_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80CC) /* abnormal_int_mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_SET_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8010) /* abnormal_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_SET_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8050) /* abnormal_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_SET_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8090) /* abnormal_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_SET_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80D0) /* abnormal_int_set */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_RO_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8014) /* abnormal_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_RO_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8054) /* abnormal_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_RO_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8094) /* abnormal_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_EP_ERR_INT_RO_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x80D4) /* abnormal_int_ro */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VECTOR_PENDING_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8400) /* interrupt vector pending status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VECTOR_MASK_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8404) /* nvme interrupt vector mask */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_INT_REQ_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8408) /* int req register */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_CTRL_MISC_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x840C) /* NVMe Local Misc Control */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_INT_COAL_TIME_UNIT_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8410) /* Doorbell Interrupt Coal Timer Count Unit */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DB_INT_COAL_AGGRE_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8414) /* Doorbell Interrupt Coal Aggre Cfg */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_ENGINE_SEL_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8418) /* nvme description engine work mode select */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_ACK_MODE_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x841C) /* nvme2rbd_tlp_ack mode sel */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DDR_STRD_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8420) /* doorbell stride in DDR */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQE_RD_MAX_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8424) /* the max number of SQE read back in one sq descrbiton */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RAM_INITIAL_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8428) /* port nvme ram initial */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_LINK_DOWN_PROC_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x842C) /* nvme link down processs */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_FLR_STS_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8430) /* nvme FLR request */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_DMA_CQ_ERR_INITIAL_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8434) /* nvme DMACQ err sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RO_CFG_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8438) /* nvme_sq_order_cfg */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SOFT_RST_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x843C) /* nvme_soft_rst */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_INT_MOD_SEL_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8440) /* nvme int mode select */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_INT_LEVEL_SEL_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8444) /* nvme int_levlel_cfg */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBA_CREDIT_CLR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8448) /* crdit cnt clear */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_RBD_CREDIT_CLR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x844C) /* crdit cnt clear */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_VF_SIZE_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8450) /* vf size in cpu memory */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_WRPTR_BASE_ADDDR_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8454) /* low 32 bit of nvme wr_ptr base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NMME_WRPTR_BASE_ADDDR_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8458) /* high 32 bit of nvme wr_ptr base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_MEM_BASE_ADDDR_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x845C) /* low 32 bit of nvme memory base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_MEM_BASE_ADDDR_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8460) /* high 32 bit of nvme memory base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_MEM_SPACE_LOW_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8464) /* low 32 bit of nvme memoryspace for a SQ */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_MEM_SPACE_HIGH_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8468) /* high 32 bit of nvme memoryspace for a SQ */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_IDLE_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x846C) /* nvme idle status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_PF_VLD_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8470) /* nvme global pf vld */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_RAM_ECC_INJECT_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8600) /* nvme ram ecc inject */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_REG_RAM_ECC_CNT_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8604) /* queue_reg_ram_ecc_cnt */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_QUEUE_REG_RAM_ECC_ADDR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8608) /* queue_reg_ram_ecc_addr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_ECC_CNT_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x860C) /* sq_des_ram_ecc_cnt */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_ECC_ADDR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8610) /* sq_des_ram_ecc_addr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_PREF_FIFO_RAM_ECC_CNT_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8614) /* pref_fifo_ram_ecc_cnt */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_PREF_FIFO_RAM_ECC_ADDR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8618) /* pref_fifo_ram_ecc_addr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_FCTON_REGS_RAM_ECC_CNT_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x861C) /* fcton_regs_ram_ecc_cnt */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_FCTON_REGS_RAM_ECC_ADDR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8620) /* fcton_regs_ram_ecc_addr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_HEAD_ERR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8624) /* nvme_sqdb_head_err */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_TAIL_ERR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8628) /* nvme_sqdb_tail_err */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_RBD_TLP_ERR_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x862C) /* rbd_tlp_err_type */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_DMA_CQ_ERR_STATUS_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8630) /* nvme DMACQ err status */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_CFG_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8634) /* nvme_sq_des_ctrl_ram_dfx_cfg */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_WDAT_L_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8638) /* nvme_sq_des_ctrl_ram_wr_data_low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_WDAT_H_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x863C) /* nvme_sq_des_ctrl_ram_wr_data_high */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_RDAT_L_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8640) /* nvme_sq_des_ctrl_ram_rd_data_low */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_SQ_DES_RAM_RDAT_H_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8644) /* nvme_sq_des_ctrl_ram_rd_data_high */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_NVME_FIFO_STS_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8648) /* nvme_fifo_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_NVME_QUEUE_REG_RAM_FSM_STS_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x864C) /* nvme_queue_reg_ram_fsm_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_NVME_FLOW_STS0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8650) /* nvme_flow_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_DFX_NVME_FLOW_STS1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x8654) /* nvme_flow_sts */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9000) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9010) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9020) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9030) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9040) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9050) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9060) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9070) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9080) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9090) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9100) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9110) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9120) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9130) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9140) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9150) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9160) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9170) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9180) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9190) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9200) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9210) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9220) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9230) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9240) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9250) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9260) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9270) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9280) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9290) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9300) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9310) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9320) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9330) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9340) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9350) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9360) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9370) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9380) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9390) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_64_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9400) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_65_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9410) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_66_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9420) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_67_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9430) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_68_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9440) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_69_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9450) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_70_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9460) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_71_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9470) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_72_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9480) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_73_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9490) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_74_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_75_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_76_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_77_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_78_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_79_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_80_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9500) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_81_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9510) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_82_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9520) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_83_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9530) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_84_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9540) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_85_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9550) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_86_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9560) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_87_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9570) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_88_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9580) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_89_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9590) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_90_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_91_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_92_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_93_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_94_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_95_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_96_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9600) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_97_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9610) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_98_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9620) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_99_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9630) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_100_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9640) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_101_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9650) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_102_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9660) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_103_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9670) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_104_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9680) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_105_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9690) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_106_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_107_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_108_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_109_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_110_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_111_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_112_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9700) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_113_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9710) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_114_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9720) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_115_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9730) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_116_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9740) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_117_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9750) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_118_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9760) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_119_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9770) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_120_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9780) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_121_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9790) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_122_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_123_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_124_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_125_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_126_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_127_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_128_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9800) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_129_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9810) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_130_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9820) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_131_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9830) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_132_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9840) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_133_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9850) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_134_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9860) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_135_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9870) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_136_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9880) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_137_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9890) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_138_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_139_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_140_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_141_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_142_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_143_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_144_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9900) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_145_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9910) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_146_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9920) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_147_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9930) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_148_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9940) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_149_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9950) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_150_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9960) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_151_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9970) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_152_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9980) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_153_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9990) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_154_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_155_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_156_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_157_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_158_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_159_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_160_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_161_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_162_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_163_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_164_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_165_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_166_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_167_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_168_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_169_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_170_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_171_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_172_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_173_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_174_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_175_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_176_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_177_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_178_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_179_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_180_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_181_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_182_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_183_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_184_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_185_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_186_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_187_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_188_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_189_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_190_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_191_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_192_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_193_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_194_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_195_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_196_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_197_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_198_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_199_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_200_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_201_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_202_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_203_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_204_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_205_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_206_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_207_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_208_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_209_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_210_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_211_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_212_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_213_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_214_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_215_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_216_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_217_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_218_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_219_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_220_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_221_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_222_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_223_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_224_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_225_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_226_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_227_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_228_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_229_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_230_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_231_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_232_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_233_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_234_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_235_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_236_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_237_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ED0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_238_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_239_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_240_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_241_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_242_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_243_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_244_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_245_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_246_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_247_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_248_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_249_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_250_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_251_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_252_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_253_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_254_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_255_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_256_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA000) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_257_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA010) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_258_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA020) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_259_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA030) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_260_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA040) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_261_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA050) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_262_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA060) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_263_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA070) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_264_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA080) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_265_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA090) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_266_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_267_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_268_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_269_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_270_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_271_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_272_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA100) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_273_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA110) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_274_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA120) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_275_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA130) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_276_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA140) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_277_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA150) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_278_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA160) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_279_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA170) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_280_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA180) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_281_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA190) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_282_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_283_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_284_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_285_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_286_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_287_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_288_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA200) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_289_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA210) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_290_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA220) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_291_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA230) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_292_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA240) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_293_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA250) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_294_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA260) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_295_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA270) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_296_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA280) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_297_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA290) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_298_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_299_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_300_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_301_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_302_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_303_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_304_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA300) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_305_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA310) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_306_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA320) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_307_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA330) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_308_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA340) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_309_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA350) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_310_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA360) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_311_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA370) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_312_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA380) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_313_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA390) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_314_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_315_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_316_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_317_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_318_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_319_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_320_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA400) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_321_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA410) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_322_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA420) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_323_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA430) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_324_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA440) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_325_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA450) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_326_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA460) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_327_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA470) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_328_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA480) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_329_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA490) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_330_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_331_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_332_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_333_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_334_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_335_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_336_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA500) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_337_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA510) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_338_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA520) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_339_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA530) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_340_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA540) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_341_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA550) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_342_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA560) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_343_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA570) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_344_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA580) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_345_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA590) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_346_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_347_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_348_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_349_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_350_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_351_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_352_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA600) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_353_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA610) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_354_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA620) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_355_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA630) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_356_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA640) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_357_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA650) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_358_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA660) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_359_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA670) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_360_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA680) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_361_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA690) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_362_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_363_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_364_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_365_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_366_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_367_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_368_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA700) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_369_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA710) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_370_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA720) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_371_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA730) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_372_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA740) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_373_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA750) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_374_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA760) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_375_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA770) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_376_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA780) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_377_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA790) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_378_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_379_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_380_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_381_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_382_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_383_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_384_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA800) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_385_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA810) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_386_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA820) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_387_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA830) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_388_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA840) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_389_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA850) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_390_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA860) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_391_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA870) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_392_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA880) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_393_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA890) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_394_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_395_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_396_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_397_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_398_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_399_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_400_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA900) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_401_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA910) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_402_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA920) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_403_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA930) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_404_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA940) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_405_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA950) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_406_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA960) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_407_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA970) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_408_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA980) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_409_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA990) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_410_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_411_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_412_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_413_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_414_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_415_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_416_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_417_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_418_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_419_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_420_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_421_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_422_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_423_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_424_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_425_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_426_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_427_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_428_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_429_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_430_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_431_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_432_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_433_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_434_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_435_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_436_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_437_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_438_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_439_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_440_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_441_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_442_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_443_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_444_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_445_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_446_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_447_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_448_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_449_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_450_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_451_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_452_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_453_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_454_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_455_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_456_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_457_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_458_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_459_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_460_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_461_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_462_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_463_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_464_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_465_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_466_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_467_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_468_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_469_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_470_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_471_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_472_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_473_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_474_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_475_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_476_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_477_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_478_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_479_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_480_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_481_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_482_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_483_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_484_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_485_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_486_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_487_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_488_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_489_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_490_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_491_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_492_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_493_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAED0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_494_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_495_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_496_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_497_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_498_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_499_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_500_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_501_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_502_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_503_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_504_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_505_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_506_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_507_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_508_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_509_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_510_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_511_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_512_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB000) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_513_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB010) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_514_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB020) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_515_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB030) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_516_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB040) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_517_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB050) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_518_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB060) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_519_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB070) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_520_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB080) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_521_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB090) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_522_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_523_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_524_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_525_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_526_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_527_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_528_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB100) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_529_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB110) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_530_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB120) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_531_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB130) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_532_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB140) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_533_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB150) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_534_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB160) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_535_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB170) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_536_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB180) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_537_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB190) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_538_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_539_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_540_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_541_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_542_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_543_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_544_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB200) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_545_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB210) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_546_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB220) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_547_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB230) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_548_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB240) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_549_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB250) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_550_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB260) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_551_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB270) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_552_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB280) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_553_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB290) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_554_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_555_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_556_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_557_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_558_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_559_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_560_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB300) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_561_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB310) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_562_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB320) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_563_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB330) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_564_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB340) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_565_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB350) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_566_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB360) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_567_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB370) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_568_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB380) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_569_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB390) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_570_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_571_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_572_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_573_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_574_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_575_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_576_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB400) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_577_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB410) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_578_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB420) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_579_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB430) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_580_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB440) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_581_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB450) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_582_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB460) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_583_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB470) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_584_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB480) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_585_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB490) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_586_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_587_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_588_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_589_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_590_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_591_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_592_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB500) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_593_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB510) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_594_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB520) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_595_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB530) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_596_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB540) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_597_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB550) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_598_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB560) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_599_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB570) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_600_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB580) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_601_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB590) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_602_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_603_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_604_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_605_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_606_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_607_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_608_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB600) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_609_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB610) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_610_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB620) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_611_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB630) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_612_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB640) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_613_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB650) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_614_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB660) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_615_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB670) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_616_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB680) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_617_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB690) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_618_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_619_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_620_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_621_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_622_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_623_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_624_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB700) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_625_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB710) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_626_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB720) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_627_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB730) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_628_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB740) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_629_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB750) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_630_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB760) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_631_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB770) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_632_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB780) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_633_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB790) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_634_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_635_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_636_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_637_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_638_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_639_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_640_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB800) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_641_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB810) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_642_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB820) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_643_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB830) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_644_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB840) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_645_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB850) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_646_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB860) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_647_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB870) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_648_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB880) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_649_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB890) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_650_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_651_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_652_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_653_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_654_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_655_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_656_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB900) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_657_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB910) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_658_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB920) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_659_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB930) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_660_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB940) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_661_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB950) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_662_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB960) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_663_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB970) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_664_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB980) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_665_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB990) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_666_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_667_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_668_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_669_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_670_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_671_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_672_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_673_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_674_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_675_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_676_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_677_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_678_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_679_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_680_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_681_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_682_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_683_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_684_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_685_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_686_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_687_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_688_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_689_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_690_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_691_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_692_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_693_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_694_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_695_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_696_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_697_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_698_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_699_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_700_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_701_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_702_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_703_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_704_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_705_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_706_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_707_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_708_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_709_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_710_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_711_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_712_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_713_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_714_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_715_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_716_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_717_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_718_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_719_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_720_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_721_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_722_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_723_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_724_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_725_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_726_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_727_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_728_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_729_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_730_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_731_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_732_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_733_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_734_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_735_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_736_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_737_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_738_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_739_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_740_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_741_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_742_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_743_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_744_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_745_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_746_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_747_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_748_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_749_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBED0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_750_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_751_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_752_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_753_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_754_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_755_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_756_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_757_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_758_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_759_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_760_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_761_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_762_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_763_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_764_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_765_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_766_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_767_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_768_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC000) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_769_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC010) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_770_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC020) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_771_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC030) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_772_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC040) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_773_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC050) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_774_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC060) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_775_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC070) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_776_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC080) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_777_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC090) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_778_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_779_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_780_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_781_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_782_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_783_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_784_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC100) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_785_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC110) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_786_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC120) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_787_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC130) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_788_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC140) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_789_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC150) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_790_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC160) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_791_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC170) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_792_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC180) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_793_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC190) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_794_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_795_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_796_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_797_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_798_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_799_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_800_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC200) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_801_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC210) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_802_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC220) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_803_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC230) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_804_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC240) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_805_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC250) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_806_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC260) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_807_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC270) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_808_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC280) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_809_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC290) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_810_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_811_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_812_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_813_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_814_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_815_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_816_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC300) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_817_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC310) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_818_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC320) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_819_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC330) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_820_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC340) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_821_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC350) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_822_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC360) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_823_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC370) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_824_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC380) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_825_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC390) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_826_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_827_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_828_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_829_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_830_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_831_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_832_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC400) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_833_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC410) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_834_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC420) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_835_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC430) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_836_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC440) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_837_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC450) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_838_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC460) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_839_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC470) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_840_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC480) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_841_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC490) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_842_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_843_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_844_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_845_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_846_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_847_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_848_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC500) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_849_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC510) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_850_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC520) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_851_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC530) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_852_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC540) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_853_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC550) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_854_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC560) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_855_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC570) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_856_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC580) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_857_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC590) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_858_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_859_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_860_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_861_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_862_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_863_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_864_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC600) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_865_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC610) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_866_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC620) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_867_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC630) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_868_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC640) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_869_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC650) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_870_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC660) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_871_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC670) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_872_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC680) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_873_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC690) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_874_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_875_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_876_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_877_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_878_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_879_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_880_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC700) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_881_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC710) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_882_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC720) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_883_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC730) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_884_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC740) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_885_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC750) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_886_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC760) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_887_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC770) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_888_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC780) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_889_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC790) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_890_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_891_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_892_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_893_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_894_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_895_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_896_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC800) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_897_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC810) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_898_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC820) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_899_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC830) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_900_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC840) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_901_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC850) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_902_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC860) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_903_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC870) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_904_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC880) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_905_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC890) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_906_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_907_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_908_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_909_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_910_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_911_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_912_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC900) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_913_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC910) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_914_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC920) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_915_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC930) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_916_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC940) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_917_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC950) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_918_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC960) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_919_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC970) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_920_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC980) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_921_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC990) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_922_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9A0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_923_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9B0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_924_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9C0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_925_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9D0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_926_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9E0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_927_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9F0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_928_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_929_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_930_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_931_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_932_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_933_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_934_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_935_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_936_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_937_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_938_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_939_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_940_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_941_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_942_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_943_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_944_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_945_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_946_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_947_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_948_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_949_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_950_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_951_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_952_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_953_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_954_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_955_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_956_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_957_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_958_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_959_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_960_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_961_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_962_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_963_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_964_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_965_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_966_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_967_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_968_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_969_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_970_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_971_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_972_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_973_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_974_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_975_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_976_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_977_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_978_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_979_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_980_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_981_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_982_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_983_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_984_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_985_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_986_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_987_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_988_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_989_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_990_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_991_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_992_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_993_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_994_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_995_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_996_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_997_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_998_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_999_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCED0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF00) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF10) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF20) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF30) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF40) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF50) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF60) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF70) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF80) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF90) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFA0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFB0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFC0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFD0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFE0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_QUEUE_SIZE_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFF0) /* depth of NVME SQ/CQ Ring */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9004) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9014) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9024) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9034) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9044) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9054) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9064) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9074) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9084) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9094) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9104) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9114) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9124) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9134) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9144) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9154) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9164) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9174) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9184) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9194) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9204) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9214) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9224) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9234) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9244) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9254) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9264) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9274) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9284) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9294) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9304) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9314) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9324) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9334) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9344) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9354) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9364) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9374) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9384) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9394) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_64_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9404) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_65_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9414) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_66_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9424) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_67_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9434) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_68_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9444) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_69_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9454) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_70_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9464) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_71_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9474) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_72_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9484) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_73_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9494) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_74_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_75_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_76_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_77_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_78_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_79_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_80_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9504) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_81_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9514) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_82_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9524) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_83_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9534) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_84_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9544) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_85_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9554) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_86_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9564) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_87_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9574) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_88_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9584) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_89_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9594) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_90_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_91_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_92_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_93_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_94_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_95_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_96_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9604) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_97_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9614) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_98_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9624) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_99_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9634) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_100_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9644) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_101_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9654) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_102_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9664) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_103_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9674) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_104_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9684) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_105_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9694) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_106_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_107_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_108_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_109_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_110_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_111_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_112_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9704) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_113_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9714) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_114_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9724) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_115_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9734) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_116_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9744) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_117_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9754) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_118_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9764) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_119_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9774) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_120_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9784) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_121_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9794) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_122_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_123_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_124_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_125_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_126_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_127_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_128_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9804) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_129_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9814) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_130_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9824) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_131_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9834) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_132_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9844) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_133_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9854) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_134_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9864) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_135_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9874) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_136_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9884) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_137_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9894) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_138_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_139_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_140_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_141_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_142_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_143_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_144_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9904) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_145_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9914) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_146_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9924) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_147_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9934) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_148_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9944) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_149_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9954) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_150_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9964) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_151_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9974) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_152_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9984) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_153_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9994) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_154_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_155_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_156_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_157_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_158_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_159_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_160_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_161_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_162_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_163_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_164_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_165_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_166_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_167_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_168_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_169_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_170_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_171_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_172_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_173_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_174_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_175_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_176_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_177_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_178_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_179_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_180_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_181_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_182_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_183_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_184_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_185_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_186_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_187_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_188_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_189_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_190_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_191_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_192_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_193_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_194_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_195_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_196_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_197_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_198_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_199_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_200_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_201_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_202_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_203_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_204_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_205_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_206_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_207_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_208_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_209_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_210_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_211_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_212_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_213_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_214_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_215_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_216_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_217_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_218_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_219_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_220_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_221_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_222_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_223_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_224_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_225_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_226_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_227_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_228_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_229_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_230_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_231_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_232_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_233_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_234_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_235_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_236_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_237_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ED4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_238_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_239_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_240_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_241_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_242_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_243_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_244_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_245_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_246_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_247_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_248_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_249_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_250_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_251_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_252_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_253_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_254_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_255_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_256_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA004) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_257_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA014) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_258_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA024) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_259_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA034) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_260_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA044) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_261_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA054) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_262_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA064) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_263_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA074) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_264_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA084) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_265_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA094) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_266_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_267_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_268_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_269_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_270_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_271_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_272_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA104) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_273_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA114) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_274_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA124) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_275_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA134) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_276_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA144) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_277_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA154) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_278_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA164) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_279_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA174) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_280_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA184) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_281_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA194) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_282_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_283_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_284_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_285_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_286_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_287_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_288_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA204) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_289_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA214) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_290_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA224) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_291_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA234) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_292_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA244) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_293_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA254) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_294_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA264) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_295_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA274) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_296_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA284) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_297_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA294) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_298_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_299_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_300_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_301_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_302_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_303_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_304_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA304) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_305_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA314) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_306_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA324) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_307_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA334) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_308_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA344) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_309_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA354) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_310_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA364) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_311_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA374) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_312_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA384) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_313_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA394) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_314_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_315_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_316_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_317_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_318_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_319_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_320_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA404) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_321_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA414) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_322_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA424) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_323_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA434) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_324_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA444) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_325_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA454) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_326_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA464) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_327_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA474) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_328_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA484) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_329_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA494) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_330_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_331_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_332_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_333_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_334_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_335_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_336_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA504) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_337_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA514) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_338_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA524) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_339_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA534) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_340_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA544) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_341_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA554) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_342_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA564) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_343_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA574) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_344_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA584) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_345_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA594) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_346_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_347_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_348_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_349_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_350_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_351_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_352_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA604) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_353_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA614) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_354_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA624) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_355_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA634) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_356_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA644) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_357_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA654) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_358_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA664) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_359_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA674) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_360_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA684) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_361_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA694) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_362_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_363_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_364_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_365_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_366_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_367_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_368_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA704) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_369_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA714) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_370_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA724) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_371_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA734) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_372_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA744) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_373_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA754) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_374_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA764) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_375_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA774) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_376_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA784) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_377_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA794) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_378_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_379_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_380_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_381_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_382_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_383_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_384_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA804) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_385_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA814) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_386_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA824) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_387_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA834) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_388_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA844) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_389_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA854) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_390_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA864) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_391_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA874) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_392_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA884) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_393_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA894) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_394_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_395_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_396_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_397_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_398_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_399_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_400_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA904) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_401_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA914) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_402_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA924) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_403_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA934) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_404_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA944) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_405_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA954) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_406_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA964) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_407_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA974) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_408_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA984) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_409_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA994) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_410_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_411_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_412_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_413_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_414_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_415_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_416_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_417_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_418_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_419_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_420_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_421_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_422_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_423_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_424_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_425_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_426_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_427_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_428_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_429_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_430_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_431_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_432_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_433_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_434_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_435_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_436_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_437_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_438_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_439_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_440_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_441_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_442_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_443_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_444_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_445_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_446_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_447_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_448_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_449_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_450_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_451_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_452_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_453_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_454_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_455_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_456_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_457_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_458_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_459_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_460_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_461_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_462_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_463_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_464_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_465_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_466_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_467_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_468_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_469_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_470_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_471_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_472_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_473_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_474_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_475_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_476_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_477_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_478_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_479_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_480_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_481_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_482_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_483_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_484_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_485_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_486_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_487_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_488_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_489_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_490_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_491_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_492_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_493_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAED4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_494_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_495_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_496_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_497_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_498_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_499_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_500_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_501_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_502_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_503_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_504_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_505_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_506_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_507_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_508_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_509_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_510_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_511_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_512_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB004) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_513_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB014) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_514_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB024) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_515_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB034) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_516_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB044) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_517_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB054) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_518_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB064) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_519_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB074) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_520_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB084) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_521_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB094) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_522_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_523_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_524_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_525_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_526_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_527_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_528_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB104) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_529_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB114) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_530_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB124) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_531_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB134) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_532_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB144) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_533_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB154) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_534_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB164) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_535_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB174) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_536_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB184) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_537_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB194) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_538_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_539_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_540_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_541_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_542_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_543_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_544_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB204) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_545_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB214) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_546_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB224) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_547_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB234) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_548_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB244) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_549_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB254) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_550_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB264) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_551_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB274) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_552_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB284) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_553_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB294) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_554_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_555_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_556_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_557_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_558_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_559_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_560_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB304) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_561_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB314) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_562_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB324) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_563_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB334) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_564_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB344) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_565_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB354) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_566_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB364) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_567_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB374) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_568_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB384) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_569_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB394) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_570_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_571_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_572_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_573_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_574_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_575_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_576_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB404) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_577_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB414) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_578_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB424) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_579_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB434) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_580_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB444) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_581_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB454) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_582_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB464) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_583_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB474) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_584_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB484) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_585_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB494) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_586_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_587_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_588_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_589_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_590_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_591_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_592_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB504) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_593_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB514) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_594_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB524) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_595_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB534) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_596_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB544) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_597_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB554) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_598_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB564) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_599_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB574) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_600_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB584) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_601_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB594) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_602_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_603_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_604_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_605_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_606_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_607_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_608_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB604) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_609_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB614) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_610_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB624) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_611_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB634) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_612_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB644) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_613_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB654) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_614_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB664) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_615_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB674) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_616_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB684) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_617_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB694) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_618_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_619_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_620_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_621_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_622_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_623_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_624_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB704) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_625_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB714) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_626_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB724) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_627_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB734) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_628_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB744) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_629_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB754) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_630_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB764) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_631_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB774) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_632_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB784) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_633_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB794) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_634_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_635_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_636_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_637_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_638_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_639_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_640_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB804) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_641_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB814) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_642_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB824) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_643_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB834) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_644_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB844) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_645_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB854) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_646_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB864) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_647_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB874) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_648_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB884) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_649_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB894) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_650_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_651_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_652_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_653_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_654_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_655_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_656_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB904) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_657_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB914) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_658_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB924) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_659_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB934) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_660_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB944) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_661_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB954) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_662_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB964) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_663_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB974) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_664_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB984) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_665_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB994) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_666_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_667_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_668_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_669_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_670_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_671_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_672_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_673_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_674_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_675_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_676_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_677_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_678_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_679_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_680_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_681_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_682_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_683_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_684_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_685_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_686_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_687_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_688_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_689_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_690_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_691_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_692_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_693_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_694_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_695_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_696_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_697_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_698_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_699_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_700_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_701_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_702_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_703_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_704_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_705_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_706_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_707_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_708_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_709_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_710_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_711_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_712_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_713_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_714_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_715_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_716_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_717_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_718_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_719_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_720_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_721_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_722_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_723_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_724_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_725_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_726_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_727_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_728_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_729_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_730_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_731_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_732_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_733_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_734_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_735_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_736_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_737_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_738_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_739_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_740_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_741_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_742_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_743_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_744_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_745_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_746_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_747_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_748_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_749_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBED4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_750_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_751_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_752_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_753_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_754_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_755_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_756_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_757_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_758_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_759_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_760_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_761_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_762_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_763_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_764_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_765_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_766_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_767_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_768_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC004) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_769_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC014) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_770_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC024) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_771_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC034) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_772_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC044) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_773_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC054) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_774_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC064) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_775_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC074) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_776_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC084) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_777_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC094) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_778_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_779_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_780_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_781_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_782_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_783_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_784_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC104) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_785_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC114) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_786_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC124) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_787_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC134) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_788_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC144) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_789_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC154) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_790_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC164) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_791_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC174) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_792_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC184) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_793_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC194) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_794_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_795_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_796_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_797_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_798_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_799_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_800_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC204) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_801_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC214) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_802_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC224) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_803_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC234) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_804_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC244) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_805_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC254) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_806_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC264) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_807_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC274) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_808_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC284) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_809_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC294) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_810_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_811_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_812_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_813_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_814_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_815_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_816_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC304) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_817_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC314) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_818_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC324) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_819_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC334) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_820_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC344) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_821_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC354) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_822_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC364) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_823_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC374) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_824_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC384) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_825_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC394) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_826_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_827_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_828_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_829_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_830_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_831_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_832_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC404) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_833_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC414) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_834_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC424) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_835_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC434) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_836_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC444) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_837_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC454) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_838_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC464) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_839_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC474) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_840_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC484) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_841_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC494) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_842_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_843_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_844_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_845_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_846_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_847_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_848_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC504) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_849_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC514) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_850_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC524) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_851_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC534) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_852_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC544) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_853_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC554) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_854_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC564) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_855_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC574) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_856_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC584) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_857_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC594) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_858_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_859_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_860_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_861_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_862_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_863_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_864_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC604) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_865_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC614) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_866_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC624) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_867_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC634) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_868_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC644) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_869_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC654) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_870_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC664) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_871_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC674) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_872_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC684) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_873_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC694) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_874_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_875_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_876_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_877_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_878_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_879_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_880_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC704) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_881_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC714) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_882_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC724) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_883_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC734) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_884_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC744) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_885_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC754) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_886_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC764) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_887_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC774) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_888_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC784) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_889_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC794) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_890_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_891_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_892_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_893_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_894_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_895_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_896_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC804) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_897_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC814) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_898_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC824) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_899_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC834) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_900_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC844) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_901_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC854) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_902_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC864) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_903_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC874) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_904_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC884) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_905_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC894) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_906_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_907_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_908_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_909_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_910_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_911_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_912_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC904) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_913_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC914) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_914_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC924) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_915_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC934) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_916_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC944) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_917_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC954) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_918_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC964) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_919_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC974) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_920_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC984) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_921_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC994) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_922_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9A4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_923_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9B4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_924_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9C4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_925_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9D4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_926_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9E4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_927_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9F4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_928_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_929_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_930_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_931_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_932_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_933_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_934_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_935_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_936_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_937_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_938_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_939_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_940_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_941_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_942_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_943_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_944_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_945_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_946_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_947_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_948_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_949_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_950_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_951_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_952_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_953_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_954_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_955_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_956_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_957_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_958_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_959_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_960_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_961_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_962_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_963_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_964_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_965_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_966_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_967_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_968_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_969_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_970_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_971_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_972_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_973_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_974_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_975_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_976_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_977_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_978_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_979_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_980_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_981_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_982_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_983_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_984_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_985_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_986_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_987_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_988_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_989_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_990_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_991_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_992_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_993_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_994_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_995_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_996_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_997_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_998_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_999_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCED4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF04) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF14) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF24) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF34) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF44) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF54) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF64) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF74) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF84) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF94) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFA4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFB4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFC4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFD4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFE4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_LOW_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFF4) /* low 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9008) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9018) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9028) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9038) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9048) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9058) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9068) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9078) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9088) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9098) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9108) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9118) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9128) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9138) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9148) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9158) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9168) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9178) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9188) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9198) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9208) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9218) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9228) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9238) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9248) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9258) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9268) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9278) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9288) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9298) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9308) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9318) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9328) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9338) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9348) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9358) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9368) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9378) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9388) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9398) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_64_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9408) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_65_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9418) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_66_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9428) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_67_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9438) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_68_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9448) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_69_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9458) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_70_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9468) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_71_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9478) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_72_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9488) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_73_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9498) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_74_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_75_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_76_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_77_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_78_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_79_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_80_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9508) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_81_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9518) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_82_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9528) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_83_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9538) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_84_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9548) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_85_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9558) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_86_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9568) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_87_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9578) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_88_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9588) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_89_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9598) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_90_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_91_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_92_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_93_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_94_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_95_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_96_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9608) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_97_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9618) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_98_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9628) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_99_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9638) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_100_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9648) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_101_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9658) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_102_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9668) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_103_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9678) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_104_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9688) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_105_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9698) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_106_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_107_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_108_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_109_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_110_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_111_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_112_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9708) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_113_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9718) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_114_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9728) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_115_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9738) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_116_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9748) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_117_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9758) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_118_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9768) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_119_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9778) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_120_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9788) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_121_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9798) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_122_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_123_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_124_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_125_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_126_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_127_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_128_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9808) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_129_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9818) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_130_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9828) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_131_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9838) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_132_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9848) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_133_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9858) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_134_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9868) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_135_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9878) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_136_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9888) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_137_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9898) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_138_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_139_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_140_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_141_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_142_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_143_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_144_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9908) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_145_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9918) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_146_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9928) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_147_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9938) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_148_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9948) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_149_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9958) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_150_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9968) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_151_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9978) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_152_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9988) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_153_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9998) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_154_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_155_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_156_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_157_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_158_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_159_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_160_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_161_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_162_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_163_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_164_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_165_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_166_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_167_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_168_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_169_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_170_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_171_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_172_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_173_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_174_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_175_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_176_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_177_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_178_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_179_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_180_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_181_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_182_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_183_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_184_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_185_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_186_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_187_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_188_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_189_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_190_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_191_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_192_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_193_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_194_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_195_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_196_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_197_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_198_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_199_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_200_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_201_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_202_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_203_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_204_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_205_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_206_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_207_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_208_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_209_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_210_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_211_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_212_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_213_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_214_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_215_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_216_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_217_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_218_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_219_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_220_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_221_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_222_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_223_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_224_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_225_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_226_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_227_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_228_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_229_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_230_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_231_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_232_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_233_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_234_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_235_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_236_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_237_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ED8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_238_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_239_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_240_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_241_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_242_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_243_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_244_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_245_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_246_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_247_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_248_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_249_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_250_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_251_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_252_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_253_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_254_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_255_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_256_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA008) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_257_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA018) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_258_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA028) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_259_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA038) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_260_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA048) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_261_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA058) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_262_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA068) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_263_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA078) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_264_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA088) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_265_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA098) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_266_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_267_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_268_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_269_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_270_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_271_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_272_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA108) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_273_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA118) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_274_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA128) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_275_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA138) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_276_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA148) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_277_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA158) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_278_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA168) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_279_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA178) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_280_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA188) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_281_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA198) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_282_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_283_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_284_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_285_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_286_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_287_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_288_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA208) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_289_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA218) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_290_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA228) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_291_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA238) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_292_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA248) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_293_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA258) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_294_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA268) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_295_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA278) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_296_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA288) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_297_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA298) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_298_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_299_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_300_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_301_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_302_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_303_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_304_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA308) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_305_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA318) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_306_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA328) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_307_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA338) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_308_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA348) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_309_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA358) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_310_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA368) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_311_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA378) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_312_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA388) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_313_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA398) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_314_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_315_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_316_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_317_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_318_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_319_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_320_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA408) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_321_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA418) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_322_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA428) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_323_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA438) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_324_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA448) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_325_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA458) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_326_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA468) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_327_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA478) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_328_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA488) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_329_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA498) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_330_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_331_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_332_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_333_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_334_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_335_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_336_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA508) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_337_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA518) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_338_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA528) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_339_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA538) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_340_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA548) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_341_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA558) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_342_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA568) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_343_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA578) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_344_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA588) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_345_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA598) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_346_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_347_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_348_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_349_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_350_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_351_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_352_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA608) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_353_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA618) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_354_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA628) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_355_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA638) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_356_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA648) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_357_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA658) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_358_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA668) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_359_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA678) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_360_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA688) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_361_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA698) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_362_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_363_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_364_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_365_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_366_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_367_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_368_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA708) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_369_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA718) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_370_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA728) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_371_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA738) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_372_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA748) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_373_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA758) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_374_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA768) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_375_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA778) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_376_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA788) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_377_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA798) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_378_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_379_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_380_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_381_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_382_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_383_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_384_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA808) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_385_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA818) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_386_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA828) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_387_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA838) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_388_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA848) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_389_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA858) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_390_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA868) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_391_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA878) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_392_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA888) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_393_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA898) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_394_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_395_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_396_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_397_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_398_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_399_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_400_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA908) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_401_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA918) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_402_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA928) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_403_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA938) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_404_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA948) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_405_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA958) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_406_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA968) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_407_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA978) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_408_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA988) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_409_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA998) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_410_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_411_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_412_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_413_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_414_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_415_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_416_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_417_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_418_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_419_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_420_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_421_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_422_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_423_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_424_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_425_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_426_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_427_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_428_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_429_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_430_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_431_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_432_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_433_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_434_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_435_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_436_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_437_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_438_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_439_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_440_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_441_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_442_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_443_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_444_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_445_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_446_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_447_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_448_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_449_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_450_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_451_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_452_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_453_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_454_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_455_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_456_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_457_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_458_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_459_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_460_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_461_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_462_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_463_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_464_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_465_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_466_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_467_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_468_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_469_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_470_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_471_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_472_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_473_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_474_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_475_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_476_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_477_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_478_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_479_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_480_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_481_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_482_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_483_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_484_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_485_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_486_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_487_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_488_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_489_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_490_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_491_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_492_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_493_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAED8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_494_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_495_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_496_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_497_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_498_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_499_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_500_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_501_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_502_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_503_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_504_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_505_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_506_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_507_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_508_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_509_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_510_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_511_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_512_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB008) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_513_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB018) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_514_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB028) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_515_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB038) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_516_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB048) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_517_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB058) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_518_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB068) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_519_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB078) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_520_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB088) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_521_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB098) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_522_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_523_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_524_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_525_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_526_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_527_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_528_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB108) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_529_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB118) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_530_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB128) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_531_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB138) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_532_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB148) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_533_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB158) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_534_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB168) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_535_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB178) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_536_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB188) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_537_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB198) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_538_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_539_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_540_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_541_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_542_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_543_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_544_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB208) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_545_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB218) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_546_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB228) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_547_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB238) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_548_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB248) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_549_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB258) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_550_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB268) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_551_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB278) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_552_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB288) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_553_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB298) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_554_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_555_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_556_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_557_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_558_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_559_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_560_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB308) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_561_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB318) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_562_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB328) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_563_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB338) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_564_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB348) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_565_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB358) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_566_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB368) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_567_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB378) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_568_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB388) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_569_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB398) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_570_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_571_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_572_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_573_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_574_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_575_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_576_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB408) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_577_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB418) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_578_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB428) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_579_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB438) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_580_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB448) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_581_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB458) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_582_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB468) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_583_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB478) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_584_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB488) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_585_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB498) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_586_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_587_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_588_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_589_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_590_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_591_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_592_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB508) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_593_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB518) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_594_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB528) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_595_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB538) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_596_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB548) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_597_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB558) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_598_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB568) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_599_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB578) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_600_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB588) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_601_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB598) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_602_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_603_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_604_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_605_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_606_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_607_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_608_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB608) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_609_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB618) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_610_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB628) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_611_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB638) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_612_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB648) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_613_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB658) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_614_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB668) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_615_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB678) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_616_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB688) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_617_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB698) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_618_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_619_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_620_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_621_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_622_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_623_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_624_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB708) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_625_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB718) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_626_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB728) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_627_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB738) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_628_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB748) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_629_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB758) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_630_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB768) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_631_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB778) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_632_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB788) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_633_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB798) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_634_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_635_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_636_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_637_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_638_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_639_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_640_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB808) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_641_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB818) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_642_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB828) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_643_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB838) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_644_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB848) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_645_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB858) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_646_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB868) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_647_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB878) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_648_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB888) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_649_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB898) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_650_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_651_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_652_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_653_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_654_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_655_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_656_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB908) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_657_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB918) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_658_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB928) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_659_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB938) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_660_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB948) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_661_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB958) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_662_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB968) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_663_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB978) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_664_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB988) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_665_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB998) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_666_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_667_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_668_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_669_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_670_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_671_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_672_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_673_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_674_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_675_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_676_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_677_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_678_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_679_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_680_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_681_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_682_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_683_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_684_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_685_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_686_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_687_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_688_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_689_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_690_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_691_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_692_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_693_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_694_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_695_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_696_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_697_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_698_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_699_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_700_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_701_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_702_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_703_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_704_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_705_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_706_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_707_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_708_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_709_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_710_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_711_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_712_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_713_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_714_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_715_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_716_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_717_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_718_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_719_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_720_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_721_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_722_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_723_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_724_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_725_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_726_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_727_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_728_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_729_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_730_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_731_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_732_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_733_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_734_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_735_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_736_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_737_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_738_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_739_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_740_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_741_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_742_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_743_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_744_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_745_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_746_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_747_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_748_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_749_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBED8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_750_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_751_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_752_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_753_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_754_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_755_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_756_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_757_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_758_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_759_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_760_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_761_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_762_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_763_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_764_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_765_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_766_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_767_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_768_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC008) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_769_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC018) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_770_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC028) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_771_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC038) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_772_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC048) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_773_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC058) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_774_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC068) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_775_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC078) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_776_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC088) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_777_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC098) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_778_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_779_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_780_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_781_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_782_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_783_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_784_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC108) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_785_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC118) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_786_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC128) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_787_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC138) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_788_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC148) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_789_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC158) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_790_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC168) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_791_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC178) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_792_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC188) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_793_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC198) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_794_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_795_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_796_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_797_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_798_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_799_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_800_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC208) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_801_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC218) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_802_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC228) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_803_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC238) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_804_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC248) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_805_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC258) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_806_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC268) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_807_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC278) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_808_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC288) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_809_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC298) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_810_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_811_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_812_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_813_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_814_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_815_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_816_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC308) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_817_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC318) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_818_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC328) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_819_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC338) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_820_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC348) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_821_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC358) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_822_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC368) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_823_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC378) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_824_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC388) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_825_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC398) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_826_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_827_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_828_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_829_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_830_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_831_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_832_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC408) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_833_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC418) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_834_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC428) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_835_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC438) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_836_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC448) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_837_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC458) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_838_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC468) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_839_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC478) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_840_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC488) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_841_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC498) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_842_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_843_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_844_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_845_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_846_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_847_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_848_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC508) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_849_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC518) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_850_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC528) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_851_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC538) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_852_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC548) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_853_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC558) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_854_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC568) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_855_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC578) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_856_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC588) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_857_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC598) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_858_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_859_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_860_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_861_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_862_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_863_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_864_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC608) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_865_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC618) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_866_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC628) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_867_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC638) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_868_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC648) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_869_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC658) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_870_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC668) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_871_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC678) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_872_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC688) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_873_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC698) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_874_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_875_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_876_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_877_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_878_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_879_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_880_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC708) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_881_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC718) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_882_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC728) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_883_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC738) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_884_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC748) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_885_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC758) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_886_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC768) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_887_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC778) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_888_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC788) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_889_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC798) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_890_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_891_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_892_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_893_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_894_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_895_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_896_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC808) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_897_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC818) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_898_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC828) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_899_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC838) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_900_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC848) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_901_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC858) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_902_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC868) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_903_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC878) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_904_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC888) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_905_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC898) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_906_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_907_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_908_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_909_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_910_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_911_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_912_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC908) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_913_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC918) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_914_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC928) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_915_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC938) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_916_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC948) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_917_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC958) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_918_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC968) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_919_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC978) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_920_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC988) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_921_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC998) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_922_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9A8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_923_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9B8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_924_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9C8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_925_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9D8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_926_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9E8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_927_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9F8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_928_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_929_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_930_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_931_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_932_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_933_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_934_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_935_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_936_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_937_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_938_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_939_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_940_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_941_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_942_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_943_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_944_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_945_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_946_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_947_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_948_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_949_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_950_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_951_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_952_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_953_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_954_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_955_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_956_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_957_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_958_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_959_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_960_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_961_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_962_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_963_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_964_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_965_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_966_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_967_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_968_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_969_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_970_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_971_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_972_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_973_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_974_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_975_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_976_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_977_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_978_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_979_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_980_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_981_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_982_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_983_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_984_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_985_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_986_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_987_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_988_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_989_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_990_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_991_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_992_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_993_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_994_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_995_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_996_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_997_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_998_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_999_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCED8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF08) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF18) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF28) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF38) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF48) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF58) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF68) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF78) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF88) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF98) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFA8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFB8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFC8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFD8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFE8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQ_BASE_ADDR_HIGH_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFF8) /* high 32 bit of nvme SQ Ring base address */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_0_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x900C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x901C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_2_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x902C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_3_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x903C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_4_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x904C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_5_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x905C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_6_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x906C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_7_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x907C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_8_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x908C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_9_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x909C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_10_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_11_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_12_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_13_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_14_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_15_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x90FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_16_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x910C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_17_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x911C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_18_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x912C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_19_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x913C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_20_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x914C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_21_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x915C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_22_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x916C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_23_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x917C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_24_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x918C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_25_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x919C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_26_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_27_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_28_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_29_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_30_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_31_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x91FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_32_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x920C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_33_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x921C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_34_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x922C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_35_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x923C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_36_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x924C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_37_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x925C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_38_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x926C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_39_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x927C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_40_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x928C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_41_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x929C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_42_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_43_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_44_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_45_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_46_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_47_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x92FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_48_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x930C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_49_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x931C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_50_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x932C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_51_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x933C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_52_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x934C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_53_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x935C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_54_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x936C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_55_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x937C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_56_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x938C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_57_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x939C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_58_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_59_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_60_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_61_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_62_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_63_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x93FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_64_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x940C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_65_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x941C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_66_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x942C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_67_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x943C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_68_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x944C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_69_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x945C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_70_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x946C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_71_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x947C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_72_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x948C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_73_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x949C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_74_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_75_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_76_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_77_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_78_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_79_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x94FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_80_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x950C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_81_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x951C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_82_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x952C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_83_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x953C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_84_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x954C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_85_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x955C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_86_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x956C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_87_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x957C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_88_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x958C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_89_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x959C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_90_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_91_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_92_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_93_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_94_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_95_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x95FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_96_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x960C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_97_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x961C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_98_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x962C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_99_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x963C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_100_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x964C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_101_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x965C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_102_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x966C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_103_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x967C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_104_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x968C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_105_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x969C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_106_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_107_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_108_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_109_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_110_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_111_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x96FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_112_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x970C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_113_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x971C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_114_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x972C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_115_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x973C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_116_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x974C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_117_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x975C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_118_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x976C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_119_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x977C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_120_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x978C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_121_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x979C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_122_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_123_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_124_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_125_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_126_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_127_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x97FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_128_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x980C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_129_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x981C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_130_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x982C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_131_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x983C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_132_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x984C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_133_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x985C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_134_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x986C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_135_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x987C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_136_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x988C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_137_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x989C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_138_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_139_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_140_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_141_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_142_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_143_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x98FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_144_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x990C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_145_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x991C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_146_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x992C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_147_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x993C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_148_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x994C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_149_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x995C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_150_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x996C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_151_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x997C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_152_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x998C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_153_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x999C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_154_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_155_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_156_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_157_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_158_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_159_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x99FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_160_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_161_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_162_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_163_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_164_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_165_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_166_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_167_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_168_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_169_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9A9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_170_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_171_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ABC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_172_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ACC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_173_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ADC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_174_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_175_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9AFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_176_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_177_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_178_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_179_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_180_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_181_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_182_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_183_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_184_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_185_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9B9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_186_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_187_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_188_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_189_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_190_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_191_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9BFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_192_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_193_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_194_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_195_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_196_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_197_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_198_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_199_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_200_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_201_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9C9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_202_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_203_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_204_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_205_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_206_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_207_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9CFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_208_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_209_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_210_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_211_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_212_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_213_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_214_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_215_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_216_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_217_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9D9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_218_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_219_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_220_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_221_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_222_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_223_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9DFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_224_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_225_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_226_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_227_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_228_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_229_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_230_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_231_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_232_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_233_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9E9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_234_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_235_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_236_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9ECC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_237_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_238_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_239_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9EFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_240_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_241_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_242_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_243_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_244_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_245_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_246_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_247_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_248_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_249_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9F9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_250_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_251_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_252_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_253_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_254_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_255_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0x9FFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_256_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA00C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_257_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA01C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_258_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA02C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_259_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA03C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_260_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA04C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_261_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA05C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_262_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA06C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_263_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA07C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_264_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA08C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_265_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA09C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_266_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_267_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_268_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_269_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_270_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_271_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA0FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_272_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA10C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_273_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA11C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_274_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA12C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_275_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA13C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_276_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA14C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_277_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA15C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_278_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA16C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_279_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA17C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_280_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA18C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_281_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA19C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_282_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_283_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_284_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_285_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_286_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_287_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA1FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_288_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA20C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_289_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA21C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_290_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA22C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_291_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA23C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_292_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA24C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_293_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA25C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_294_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA26C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_295_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA27C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_296_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA28C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_297_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA29C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_298_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_299_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_300_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_301_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_302_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_303_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA2FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_304_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA30C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_305_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA31C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_306_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA32C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_307_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA33C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_308_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA34C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_309_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA35C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_310_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA36C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_311_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA37C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_312_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA38C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_313_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA39C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_314_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_315_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_316_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_317_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_318_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_319_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA3FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_320_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA40C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_321_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA41C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_322_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA42C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_323_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA43C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_324_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA44C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_325_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA45C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_326_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA46C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_327_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA47C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_328_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA48C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_329_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA49C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_330_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_331_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_332_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_333_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_334_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_335_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA4FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_336_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA50C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_337_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA51C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_338_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA52C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_339_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA53C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_340_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA54C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_341_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA55C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_342_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA56C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_343_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA57C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_344_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA58C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_345_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA59C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_346_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_347_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_348_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_349_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_350_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_351_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA5FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_352_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA60C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_353_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA61C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_354_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA62C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_355_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA63C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_356_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA64C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_357_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA65C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_358_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA66C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_359_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA67C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_360_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA68C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_361_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA69C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_362_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_363_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_364_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_365_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_366_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_367_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA6FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_368_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA70C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_369_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA71C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_370_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA72C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_371_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA73C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_372_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA74C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_373_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA75C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_374_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA76C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_375_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA77C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_376_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA78C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_377_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA79C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_378_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_379_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_380_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_381_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_382_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_383_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA7FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_384_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA80C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_385_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA81C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_386_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA82C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_387_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA83C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_388_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA84C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_389_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA85C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_390_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA86C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_391_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA87C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_392_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA88C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_393_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA89C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_394_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_395_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_396_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_397_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_398_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_399_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA8FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_400_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA90C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_401_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA91C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_402_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA92C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_403_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA93C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_404_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA94C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_405_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA95C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_406_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA96C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_407_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA97C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_408_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA98C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_409_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA99C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_410_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_411_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_412_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_413_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_414_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_415_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xA9FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_416_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_417_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_418_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_419_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_420_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_421_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_422_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_423_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_424_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_425_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAA9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_426_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_427_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAABC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_428_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAACC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_429_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAADC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_430_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_431_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAAFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_432_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_433_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_434_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_435_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_436_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_437_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_438_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_439_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_440_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_441_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAB9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_442_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_443_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_444_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_445_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_446_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_447_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xABFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_448_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_449_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_450_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_451_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_452_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_453_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_454_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_455_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_456_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_457_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAC9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_458_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_459_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_460_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_461_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_462_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_463_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xACFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_464_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_465_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_466_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_467_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_468_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_469_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_470_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_471_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_472_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_473_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAD9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_474_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_475_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_476_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_477_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_478_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_479_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xADFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_480_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_481_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_482_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_483_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_484_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_485_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_486_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_487_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_488_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_489_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAE9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_490_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_491_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_492_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAECC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_493_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_494_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_495_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAEFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_496_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_497_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_498_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_499_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_500_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_501_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_502_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_503_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_504_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_505_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAF9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_506_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_507_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_508_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_509_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_510_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_511_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xAFFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_512_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB00C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_513_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB01C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_514_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB02C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_515_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB03C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_516_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB04C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_517_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB05C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_518_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB06C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_519_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB07C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_520_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB08C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_521_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB09C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_522_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_523_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_524_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_525_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_526_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_527_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB0FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_528_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB10C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_529_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB11C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_530_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB12C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_531_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB13C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_532_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB14C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_533_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB15C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_534_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB16C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_535_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB17C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_536_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB18C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_537_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB19C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_538_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_539_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_540_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_541_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_542_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_543_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB1FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_544_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB20C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_545_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB21C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_546_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB22C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_547_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB23C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_548_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB24C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_549_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB25C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_550_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB26C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_551_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB27C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_552_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB28C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_553_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB29C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_554_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_555_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_556_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_557_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_558_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_559_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB2FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_560_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB30C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_561_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB31C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_562_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB32C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_563_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB33C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_564_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB34C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_565_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB35C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_566_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB36C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_567_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB37C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_568_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB38C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_569_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB39C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_570_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_571_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_572_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_573_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_574_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_575_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB3FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_576_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB40C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_577_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB41C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_578_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB42C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_579_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB43C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_580_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB44C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_581_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB45C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_582_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB46C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_583_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB47C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_584_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB48C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_585_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB49C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_586_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_587_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_588_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_589_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_590_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_591_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB4FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_592_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB50C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_593_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB51C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_594_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB52C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_595_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB53C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_596_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB54C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_597_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB55C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_598_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB56C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_599_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB57C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_600_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB58C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_601_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB59C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_602_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_603_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_604_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_605_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_606_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_607_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB5FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_608_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB60C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_609_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB61C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_610_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB62C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_611_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB63C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_612_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB64C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_613_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB65C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_614_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB66C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_615_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB67C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_616_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB68C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_617_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB69C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_618_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_619_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_620_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_621_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_622_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_623_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB6FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_624_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB70C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_625_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB71C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_626_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB72C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_627_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB73C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_628_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB74C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_629_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB75C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_630_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB76C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_631_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB77C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_632_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB78C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_633_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB79C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_634_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_635_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_636_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_637_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_638_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_639_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB7FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_640_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB80C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_641_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB81C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_642_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB82C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_643_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB83C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_644_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB84C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_645_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB85C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_646_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB86C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_647_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB87C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_648_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB88C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_649_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB89C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_650_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_651_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_652_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_653_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_654_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_655_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB8FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_656_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB90C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_657_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB91C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_658_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB92C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_659_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB93C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_660_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB94C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_661_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB95C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_662_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB96C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_663_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB97C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_664_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB98C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_665_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB99C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_666_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_667_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_668_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_669_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_670_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_671_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xB9FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_672_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_673_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_674_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_675_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_676_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_677_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_678_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_679_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_680_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_681_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBA9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_682_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_683_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBABC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_684_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBACC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_685_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBADC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_686_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_687_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBAFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_688_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_689_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_690_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_691_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_692_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_693_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_694_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_695_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_696_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_697_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBB9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_698_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_699_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_700_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_701_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_702_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_703_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBBFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_704_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_705_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_706_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_707_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_708_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_709_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_710_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_711_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_712_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_713_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBC9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_714_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_715_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_716_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_717_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_718_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_719_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBCFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_720_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_721_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_722_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_723_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_724_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_725_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_726_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_727_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_728_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_729_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBD9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_730_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_731_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_732_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_733_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_734_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_735_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBDFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_736_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_737_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_738_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_739_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_740_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_741_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_742_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_743_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_744_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_745_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBE9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_746_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_747_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_748_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBECC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_749_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_750_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_751_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBEFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_752_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_753_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_754_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_755_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_756_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_757_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_758_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_759_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_760_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_761_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBF9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_762_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_763_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_764_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_765_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_766_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_767_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xBFFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_768_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC00C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_769_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC01C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_770_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC02C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_771_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC03C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_772_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC04C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_773_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC05C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_774_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC06C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_775_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC07C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_776_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC08C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_777_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC09C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_778_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_779_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_780_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_781_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_782_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_783_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC0FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_784_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC10C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_785_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC11C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_786_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC12C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_787_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC13C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_788_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC14C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_789_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC15C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_790_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC16C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_791_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC17C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_792_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC18C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_793_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC19C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_794_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_795_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_796_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_797_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_798_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_799_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC1FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_800_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC20C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_801_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC21C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_802_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC22C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_803_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC23C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_804_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC24C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_805_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC25C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_806_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC26C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_807_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC27C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_808_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC28C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_809_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC29C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_810_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_811_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_812_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_813_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_814_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_815_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC2FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_816_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC30C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_817_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC31C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_818_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC32C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_819_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC33C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_820_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC34C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_821_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC35C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_822_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC36C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_823_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC37C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_824_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC38C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_825_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC39C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_826_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_827_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_828_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_829_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_830_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_831_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC3FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_832_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC40C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_833_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC41C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_834_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC42C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_835_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC43C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_836_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC44C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_837_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC45C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_838_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC46C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_839_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC47C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_840_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC48C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_841_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC49C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_842_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_843_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_844_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_845_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_846_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_847_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC4FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_848_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC50C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_849_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC51C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_850_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC52C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_851_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC53C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_852_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC54C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_853_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC55C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_854_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC56C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_855_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC57C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_856_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC58C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_857_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC59C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_858_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_859_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_860_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_861_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_862_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_863_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC5FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_864_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC60C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_865_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC61C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_866_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC62C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_867_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC63C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_868_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC64C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_869_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC65C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_870_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC66C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_871_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC67C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_872_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC68C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_873_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC69C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_874_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_875_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_876_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_877_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_878_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_879_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC6FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_880_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC70C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_881_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC71C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_882_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC72C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_883_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC73C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_884_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC74C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_885_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC75C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_886_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC76C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_887_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC77C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_888_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC78C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_889_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC79C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_890_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_891_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_892_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_893_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_894_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_895_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC7FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_896_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC80C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_897_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC81C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_898_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC82C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_899_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC83C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_900_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC84C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_901_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC85C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_902_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC86C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_903_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC87C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_904_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC88C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_905_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC89C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_906_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_907_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_908_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_909_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_910_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_911_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC8FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_912_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC90C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_913_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC91C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_914_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC92C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_915_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC93C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_916_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC94C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_917_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC95C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_918_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC96C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_919_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC97C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_920_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC98C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_921_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC99C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_922_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9AC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_923_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9BC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_924_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9CC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_925_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9DC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_926_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9EC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_927_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xC9FC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_928_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_929_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_930_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_931_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_932_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_933_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_934_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_935_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_936_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_937_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCA9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_938_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_939_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCABC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_940_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCACC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_941_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCADC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_942_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_943_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCAFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_944_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_945_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_946_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_947_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_948_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_949_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_950_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_951_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_952_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_953_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCB9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_954_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_955_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_956_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_957_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_958_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_959_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCBFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_960_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_961_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_962_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_963_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_964_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_965_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_966_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_967_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_968_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_969_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCC9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_970_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_971_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_972_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_973_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_974_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_975_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCCFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_976_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_977_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_978_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_979_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_980_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_981_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_982_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_983_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_984_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_985_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCD9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_986_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_987_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_988_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_989_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_990_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_991_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCDFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_992_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_993_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_994_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_995_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_996_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_997_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_998_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_999_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1000_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1001_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCE9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1002_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1003_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1004_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCECC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1005_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1006_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1007_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCEFC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1008_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF0C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1009_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF1C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1010_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF2C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1011_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF3C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1012_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF4C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1013_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF5C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1014_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF6C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1015_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF7C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1016_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF8C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1017_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCF9C) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1018_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFAC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1019_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFBC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1020_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFCC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1021_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFDC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1022_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFEC) /* local CPU memory rdptr */ +#define CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_NVME_SQR_MEM_RDPTR_1023_REG \ + (CSR_HIPCIEC50_AP_NVME_GLOBAL_REG_BASE + 0xCFFC) /* local CPU memory rdptr */ + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_ap_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_ap_typedef.h new file mode 100644 index 000000000..041081808 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_ap_typedef.h @@ -0,0 +1,42419 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : pcie5_ap_typedef.h + * Project line : Platform And Key Technologies Development + * Department : CAD Development Department + * Author : xxx + * Version : 1.0 + * Date : + * Description : The description of xxx project + * Others : Generated automatically by nManager V5.1 + * History : xxx 2021/01/12 16:17:59 Create file + */ + +#ifndef PCIE5_AP_TYPEDEF_H +#define PCIE5_AP_TYPEDEF_H + +/* Define the union csr_iob_txatu_control_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_txatu_en : 1; /* [0] */ + u32 iob_txatu_work_mode : 1; /* [1] */ + u32 iob_txatu_type_trans_mode : 1; /* [2] */ + u32 iob_txatu_ep_remap_en : 1; /* [3] */ + u32 iob_txatu_ep_num : 2; /* [5:4] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 iob_txatu_pf_num : 5; /* [12:8] */ + u32 iob_txatu_cxl : 1; /* [13] */ + u32 rsv_1 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_control_0_u; + +/* Define the union csr_iob_txatu_control_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_txatu_ext_region_size : 20; /* [19:0] */ + u32 rsv_2 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_control_2_u; + +/* Define the union csr_iob_txatu_region_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 12; /* [11:0] */ + u32 iob_txatu_region_size : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_region_size_u; + +/* Define the union csr_iob_txatu_base_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_4 : 12; /* [11:0] */ + u32 iob_txatu_base_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_base_addr_l_u; + +/* Define the union csr_iob_txatu_base_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_txatu_base_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_base_addr_h_u; + +/* Define the union csr_iob_txatu_tar_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 12; /* [11:0] */ + u32 iob_txatu_tar_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_tar_addr_l_u; + +/* Define the union csr_iob_txatu_tar_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_txatu_tar_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_txatu_tar_addr_h_u; + +/* Define the union csr_iob_tx_ecam_control0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_ecam_start_bus : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_ecam_control0_u; + +/* Define the union csr_iob_tx_ecam_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_ecam_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_ecam_control1_u; + +/* Define the union csr_iob_tx_ecam_base_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_ecam_base_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_ecam_base_addr_l_u; + +/* Define the union csr_iob_tx_ecam_base_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_ecam_base_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_ecam_base_addr_h_u; + +/* Define the union csr_iob_tx_cxl_base_bus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_cxl_base_bus : 8; /* [7:0] */ + u32 iob_tx_cxl_base_bus_en : 1; /* [8] */ + u32 rsv_7 : 7; /* [15:9] */ + u32 iob_tx_cxl_dev_func_mask : 8; /* [23:16] */ + u32 rsv_8 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cxl_base_bus_u; + +/* Define the union csr_iob_tx_cxl_rcrb_base_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_cxl_rcrb_base_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cxl_rcrb_base_l_u; + +/* Define the union csr_iob_tx_cxl_rcrb_base_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_cxl_rcrb_base_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cxl_rcrb_base_h_u; + +/* Define the union csr_iob_tx_cxl_dp_membar_mask_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 16; /* [15:0] */ + u32 iob_tx_cxl_dp_membar0_mask_l : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cxl_dp_membar_mask_l_u; + +/* Define the union csr_iob_tx_cxl_dp_membar_mask_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_cxl_dp_membar0_mask_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cxl_dp_membar_mask_h_u; + +/* Define the union csr_iob_tx_ep_remap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_vf_field_vld : 16; /* [15:0] */ + u32 iob_tx_vf_start_idx : 4; /* [19:16] */ + u32 rsv_10 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_ep_remap_ctrl_u; + +/* Define the union csr_iob_tx_int_msk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_msk0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_msk0_u; + +/* Define the union csr_iob_tx_int_msk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_msk1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_msk1_u; + +/* Define the union csr_iob_tx_int_msk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_msk2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_msk2_u; + +/* Define the union csr_iob_tx_int_msk3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_msk3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_msk3_u; + +/* Define the union csr_iob_tx_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_status0_u; + +/* Define the union csr_iob_tx_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_status1_u; + +/* Define the union csr_iob_tx_int_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_status2_u; + +/* Define the union csr_iob_tx_int_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_status3_u; + +/* Define the union csr_iob_tx_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro0_u; + +/* Define the union csr_iob_tx_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro1_u; + +/* Define the union csr_iob_tx_int_ro2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro2_u; + +/* Define the union csr_iob_tx_int_ro3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro3_u; + +/* Define the union csr_iob_tx_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_set0_u; + +/* Define the union csr_iob_tx_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_set1_u; + +/* Define the union csr_iob_tx_int_set2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_set2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_set2_u; + +/* Define the union csr_iob_tx_int_set3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_set3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_set3_u; + +/* Define the union csr_iob_tx_int_severity0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_severity0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_severity0_u; + +/* Define the union csr_iob_tx_int_severity1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_severity1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_severity1_u; + +/* Define the union csr_iob_tx_int_severity2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_severity2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_severity2_u; + +/* Define the union csr_iob_tx_int_severity3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_severity3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_severity3_u; + +/* Define the union csr_iob_tx_int_ro_ce0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_ce0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_ce0_u; + +/* Define the union csr_iob_tx_int_ro_ce1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_ce1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_ce1_u; + +/* Define the union csr_iob_tx_int_ro_ce2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_ce2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_ce2_u; + +/* Define the union csr_iob_tx_int_ro_ce3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_ce3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_ce3_u; + +/* Define the union csr_iob_tx_int_ro_nfe0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_nfe0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_nfe0_u; + +/* Define the union csr_iob_tx_int_ro_nfe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_nfe1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_nfe1_u; + +/* Define the union csr_iob_tx_int_ro_nfe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_nfe2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_nfe2_u; + +/* Define the union csr_iob_tx_int_ro_nfe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_nfe3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_nfe3_u; + +/* Define the union csr_iob_tx_int_ro_fe0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_fe0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_fe0_u; + +/* Define the union csr_iob_tx_int_ro_fe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_fe1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_fe1_u; + +/* Define the union csr_iob_tx_int_ro_fe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_fe2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_fe2_u; + +/* Define the union csr_iob_tx_int_ro_fe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_int_ro_fe3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_int_ro_fe3_u; + +/* Define the union csr_iob_tx_req_tout_notify_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_req_tout_notify_msk : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_req_tout_notify_msk_u; + +/* Define the union csr_iob_tx_dat_buf_ecc_err_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dat_buf_ecc_inject_en : 2; /* [1:0] */ + u32 iob_tx_dat_buf_ecc_inject_mode : 1; /* [2] */ + u32 rsv_12 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dat_buf_ecc_err_inject_u; + +/* Define the union csr_iob_tx_dat_buf_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dat_buf_1bit_ecc_err_addr : 16; /* [15:0] */ + u32 iob_tx_dat_buf_2bit_ecc_err_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dat_buf_ecc_err_addr_u; + +/* Define the union csr_iob_tx_dat_buf_ecc_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dat_buf_1bit_ecc_err_cnt : 4; /* [3:0] */ + u32 iob_tx_dat_buf_2bit_ecc_err_cnt : 4; /* [7:4] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dat_buf_ecc_err_cnt_u; + +/* Define the union csr_iob_tx_axis_control0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_axis_control_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_axis_control0_u; + +/* Define the union csr_iob_tx_axis_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_axis_control_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_axis_control1_u; + +/* Define the union csr_iob_tx_axis_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_axis_control_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_axis_control2_u; + +/* Define the union csr_iob_tx_axis_credit_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_axis_credit_ctrl : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_axis_credit_ctrl_u; + +/* Define the union csr_iob_tx_axis_credit_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_axis_credit_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_axis_credit_th_u; + +/* Define the union csr_iob_tx_axis_rplc_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_axis_rplc_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_axis_rplc_data_u; + +/* Define the union csr_iob_tx_dbuf_p_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_p_pri_start_addr : 10; /* [9:0] */ + u32 rsv_15 : 6; /* [15:10] */ + u32 iob_tx_dbuf_p_pri_end_addr : 10; /* [25:16] */ + u32 rsv_16 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_p_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_np_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_np_pri_start_addr : 10; /* [9:0] */ + u32 rsv_17 : 6; /* [15:10] */ + u32 iob_tx_dbuf_np_pri_end_addr : 10; /* [25:16] */ + u32 rsv_18 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_np_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_cpl_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_cpl_pri_start_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 iob_tx_dbuf_cpl_pri_end_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_cpl_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_all_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_all_shr_start_addr : 10; /* [9:0] */ + u32 rsv_21 : 6; /* [15:10] */ + u32 iob_tx_dbuf_all_shr_end_addr : 10; /* [25:16] */ + u32 rsv_22 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_all_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_p_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_p_shr_start_addr : 10; /* [9:0] */ + u32 rsv_23 : 6; /* [15:10] */ + u32 iob_tx_dbuf_p_shr_end_addr : 10; /* [25:16] */ + u32 rsv_24 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_p_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_np_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_np_shr_start_addr : 10; /* [9:0] */ + u32 rsv_25 : 6; /* [15:10] */ + u32 iob_tx_dbuf_np_shr_end_addr : 10; /* [25:16] */ + u32 rsv_26 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_np_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_cpl_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_cpl_shr_start_addr : 10; /* [9:0] */ + u32 rsv_27 : 6; /* [15:10] */ + u32 iob_tx_dbuf_cpl_shr_end_addr : 10; /* [25:16] */ + u32 rsv_28 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_cpl_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_dbuf_src_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_dbuf_src_pri_start_addr : 10; /* [9:0] */ + u32 rsv_29 : 6; /* [15:10] */ + u32 iob_tx_dbuf_src_pri_end_addr : 10; /* [25:16] */ + u32 rsv_30 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_dbuf_src_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_p_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_p_pri_start_addr : 10; /* [9:0] */ + u32 rsv_31 : 6; /* [15:10] */ + u32 iob_tx_hbuf_p_pri_end_addr : 10; /* [25:16] */ + u32 rsv_32 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_p_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_np_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_np_pri_start_addr : 10; /* [9:0] */ + u32 rsv_33 : 6; /* [15:10] */ + u32 iob_tx_hbuf_np_pri_end_addr : 10; /* [25:16] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_np_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_cpl_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_cpl_pri_start_addr : 10; /* [9:0] */ + u32 rsv_35 : 6; /* [15:10] */ + u32 iob_tx_hbuf_cpl_pri_end_addr : 10; /* [25:16] */ + u32 rsv_36 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_cpl_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_all_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_all_shr_start_addr : 10; /* [9:0] */ + u32 rsv_37 : 6; /* [15:10] */ + u32 iob_tx_hbuf_all_shr_end_addr : 10; /* [25:16] */ + u32 rsv_38 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_all_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_p_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_p_shr_start_addr : 10; /* [9:0] */ + u32 rsv_39 : 6; /* [15:10] */ + u32 iob_tx_hbuf_p_shr_end_addr : 10; /* [25:16] */ + u32 rsv_40 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_p_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_np_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_np_shr_start_addr : 10; /* [9:0] */ + u32 rsv_41 : 6; /* [15:10] */ + u32 iob_tx_hbuf_np_shr_end_addr : 10; /* [25:16] */ + u32 rsv_42 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_np_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_cpl_shr_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_cpl_shr_start_addr : 10; /* [9:0] */ + u32 rsv_43 : 6; /* [15:10] */ + u32 iob_tx_hbuf_cpl_shr_end_addr : 10; /* [25:16] */ + u32 rsv_44 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_cpl_shr_rgn_addr_u; + +/* Define the union csr_iob_tx_hbuf_src_pri_rgn_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_hbuf_src_pri_start_addr : 10; /* [9:0] */ + u32 rsv_45 : 6; /* [15:10] */ + u32 iob_tx_hbuf_src_pri_end_addr : 10; /* [25:16] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_hbuf_src_pri_rgn_addr_u; + +/* Define the union csr_iob_tx_alc_buf_req_wrr_wgt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_alc_buf_req_wrr_wgt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_alc_buf_req_wrr_wgt_u; + +/* Define the union csr_iob_tx_req_que_retry_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_req_que_retry_th : 6; /* [5:0] */ + u32 rsv_47 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_req_que_retry_th_u; + +/* Define the union csr_iob_tx_req_que_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_req_que_timeout_en : 1; /* [0] */ + u32 rsv_48 : 3; /* [3:1] */ + u32 iob_tx_req_que_timeout_th : 12; /* [15:4] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_req_que_timeout_ctrl_u; + +/* Define the union csr_iob_tx_src_pri_rgn_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_src_pri_rgn_map : 16; /* [15:0] */ + u32 rsv_50 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_src_pri_rgn_map_u; + +/* Define the union csr_iob_tx_req_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_req_timer_cfg : 8; /* [7:0] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_req_timer_cfg_u; + +/* Define the union csr_iob_tx_req_timer_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_req_timer_unit : 2; /* [1:0] */ + u32 rsv_52 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_req_timer_unit_u; + +/* Define the union csr_iob_tx_tlp_cdt_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_p_cdt_clr : 1; /* [0] */ + u32 iob_tx_np_cdt_clr : 1; /* [1] */ + u32 iob_tx_cpl_cdt_clr : 1; /* [2] */ + u32 rsv_53 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tlp_cdt_clr_u; + +/* Define the union csr_iob_tx_cfg0_cdt_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_cfg0_cdt_clr : 1; /* [0] */ + u32 rsv_54 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cfg0_cdt_clr_u; + +/* Define the union csr_iob_tx_cdt_active_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_cdt_active_msk : 17; /* [16:0] */ + u32 rsv_55 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_cdt_active_msk_u; + +/* Define the union csr_iob_tx_tcs_ba_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_ba_timer_cfg : 16; /* [15:0] */ + u32 iob_tx_tcs_ba_timer_unit : 2; /* [17:16] */ + u32 rsv_56 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_ba_timer_cfg_u; + +/* Define the union csr_iob_tx_tcs_ba_counter_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_ba_counter_cfg : 16; /* [15:0] */ + u32 iob_tx_tcs_ba_counter_unit : 2; /* [17:16] */ + u32 rsv_57 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_ba_counter_cfg_u; + +/* Define the union csr_iob_tx_tcs_ba_pre_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_ba_pre_size : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_ba_pre_size_u; + +/* Define the union csr_iob_tx_tcs_ba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_ba_ava_th : 16; /* [15:0] */ + u32 iob_tx_tcs_ba_allshare_th : 4; /* [19:16] */ + u32 rsv_59 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_ba_ctrl_u; + +/* Define the union csr_iob_tx_tcs_req_halt_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_req_halt_timer : 8; /* [7:0] */ + u32 rsv_60 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_req_halt_timer_u; + +/* Define the union csr_iob_tx_tcs_link_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_link_ctrl : 4; /* [3:0] */ + u32 rsv_61 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_link_ctrl_u; + +/* Define the union csr_iob_tx_tcs_dec_err_info_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_err_info_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_dec_err_info_l_u; + +/* Define the union csr_iob_tx_tcs_dec_err_info_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_err_info_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_dec_err_info_h_u; + +/* Define the union csr_iob_tx_tcs_eth_port_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_eth_port_num : 8; /* [7:0] */ + u32 rsv_62 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_eth_port_num_u; + +/* Define the union csr_iob_tx_tcs_bt_th_sricd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_bt_th_srcid : 12; /* [11:0] */ + u32 rsv_63 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_bt_th_sricd_u; + +/* Define the union csr_iob_tx_tcs_order_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_order_ctrl : 12; /* [11:0] */ + u32 rsv_64 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_order_ctrl_u; + +/* Define the union csr_iob_tx_tcs_resp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_resp_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_resp_ctrl_u; + +/* Define the union csr_iob_tx_tcs_resp_vid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_resp_vid : 8; /* [7:0] */ + u32 rsv_65 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_resp_vid_u; + +/* Define the union csr_iob_tx_tcs_rdata_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_rdata_ctrl : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_rdata_ctrl_u; + +/* Define the union csr_iob_tx_tcs_rplc_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_rplc_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_rplc_data_u; + +/* Define the union csr_iob_tx_tcs_poison_forward_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_poison_forward : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_poison_forward_u; + +/* Define the union csr_iob_tx_tcs_poison_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_poison_ctrl : 4; /* [3:0] */ + u32 rsv_68 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_poison_ctrl_u; + +/* Define the union csr_iob_tx_tcs_misc_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_misc_ctrl0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_misc_ctrl0_u; + +/* Define the union csr_iob_tx_tcs_misc_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_tx_tcs_misc_ctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_iob_tx_tcs_misc_ctrl1_u; + +/* Define the union csr_dfx_iob_tx_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_idle : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_idle_u; + +/* Define the union csr_dfx_iob_tx_axis_wr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_wr_cnt_u; + +/* Define the union csr_dfx_iob_tx_axis_rd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_rd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_rd_cnt_u; + +/* Define the union csr_dfx_iob_tx_axis_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_status0_u; + +/* Define the union csr_dfx_iob_tx_axis_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_status1_u; + +/* Define the union csr_dfx_iob_tx_axis_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_status2_u; + +/* Define the union csr_dfx_iob_tx_axis_abnormal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_abnormal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_abnormal_cnt_u; + +/* Define the union csr_dfx_iob_tx_axis_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_axis_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_axis_ctrl_u; + +/* Define the union csr_dfx_iob_tx_p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_p_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_p_cnt_u; + +/* Define the union csr_dfx_iob_tx_np_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_np_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_np_cnt_u; + +/* Define the union csr_dfx_iob_tx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_cpl_cnt_u; + +/* Define the union csr_dfx_iob_tx_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_req_cnt_u; + +/* Define the union csr_dfx_iob_tx_bar_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_bar_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_bar_cnt_u; + +/* Define the union csr_dfx_iob_tx_arr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_arr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_arr_cnt_u; + +/* Define the union csr_dfx_iob_tx_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_status0_u; + +/* Define the union csr_dfx_iob_tx_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_status1_u; + +/* Define the union csr_dfx_iob_tx_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_status2_u; + +/* Define the union csr_dfx_iob_tx_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_status3_u; + +/* Define the union csr_dfx_iob_tx_status4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_status4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_status4_u; + +/* Define the union csr_dfx_iob_tx_status5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_status5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_status5_u; + +/* Define the union csr_dfx_iob_tx_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_fifo_status_u; + +/* Define the union csr_dfx_iob_tx_bas_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_bas_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_bas_status0_u; + +/* Define the union csr_dfx_iob_tx_bas_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_bas_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_bas_status1_u; + +/* Define the union csr_dfx_iob_tx_bas_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_bas_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_bas_status2_u; + +/* Define the union csr_dfx_iob_tx_abnormal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_abnormal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_abnormal_cnt_u; + +/* Define the union csr_dfx_iob_tx_error0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_error0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_error0_u; + +/* Define the union csr_dfx_iob_tx_error1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_error1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_error1_u; + +/* Define the union csr_dfx_iob_tx_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_ctrl0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_ctrl0_u; + +/* Define the union csr_dfx_iob_tx_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_ctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_ctrl1_u; + +/* Define the union csr_dfx_iob_tx_bas_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_bas_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_bas_ctrl_u; + +/* Define the union csr_dfx_iob_tx_tcs_normal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_nor_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_normal_cnt_u; + +/* Define the union csr_dfx_iob_tx_tcs_p2p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_p2p_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_p2p_cnt_u; + +/* Define the union csr_dfx_iob_tx_tcs_arnoraml_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_abnor_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_arnoraml_cnt_u; + +/* Define the union csr_dfx_iob_tx_tcs_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_error : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_error_u; + +/* Define the union csr_dfx_iob_tx_tcs_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_status0_u; + +/* Define the union csr_dfx_iob_tx_tcs_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_status1_u; + +/* Define the union csr_dfx_iob_tx_tcs_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_status2_u; + +/* Define the union csr_dfx_iob_tx_tcs_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_idle : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_idle_u; + +/* Define the union csr_dfx_iob_tx_tcs_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_tx_tcs_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_tx_reg_dfx_iob_tx_tcs_ctrl_u; + +/* Define the union csr_iob_rxatu_control_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_en : 1; /* [0] */ + u32 iob_rxatu_func_mode : 1; /* [1] */ + u32 rsv_0 : 2; /* [3:2] */ + u32 iob_rxatu_cache : 4; /* [7:4] */ + u32 iob_rxatu_snoop : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_control_0_u; + +/* Define the union csr_iob_rxatu_control_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_bar_num : 3; /* [2:0] */ + u32 iob_rxatu_pf_num : 5; /* [7:3] */ + u32 iob_rxatu_vf_start_num : 8; /* [15:8] */ + u32 iob_rxatu_vf_end_num : 8; /* [23:16] */ + u32 iob_rxatu_port_num : 4; /* [27:24] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_control_1_u; + +/* Define the union csr_iob_rxatu_control_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_ext_region_size : 20; /* [19:0] */ + u32 rsv_3 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_control_2_u; + +/* Define the union csr_iob_rxatu_region_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_4 : 8; /* [7:0] */ + u32 iob_rxatu_region_size : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_region_size_u; + +/* Define the union csr_iob_rxatu_base_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 8; /* [7:0] */ + u32 iob_rxatu_base_addr_l : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_base_addr_l_u; + +/* Define the union csr_iob_rxatu_base_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_base_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_base_addr_h_u; + +/* Define the union csr_iob_rxatu_tar_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 8; /* [7:0] */ + u32 iob_rxatu_tar_addr_l : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_tar_addr_l_u; + +/* Define the union csr_iob_rxatu_tar_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_tar_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rxatu_tar_addr_h_u; + +/* Define the union csr_cfg_ib_bar_disp_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ib_bar_disp_sel : 6; /* [5:0] */ + u32 rsv_7 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_cfg_ib_bar_disp_sel_u; + +/* Define the union csr_iob_rx_filter_mode_ep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_atu_abort_mode : 1; /* [0] */ + u32 cfg_rom_hit_filter : 1; /* [1] */ + u32 cfg_native_poison_filter : 1; /* [2] */ + u32 cfg_msix_tbl_poison_filter : 1; /* [3] */ + u32 cfg_nvme_reg_poison_filter : 1; /* [4] */ + u32 cfg_dma_reg_poison_filter : 1; /* [5] */ + u32 rsv_8 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_filter_mode_ep_u; + +/* Define the union csr_iob_rx_nvme_reg_remap_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_nvme_mode : 1; /* [0] */ + u32 rsv_9 : 3; /* [3:1] */ + u32 cfg_sdi_nvme_addr_size : 4; /* [7:4] */ + u32 cfg_sdi_nvme_bar : 3; /* [10:8] */ + u32 rsv_10 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_nvme_reg_remap_0_u; + +/* Define the union csr_iob_rx_nvme_reg_remap_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_nvme_pf_hit_en : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_nvme_reg_remap_1_u; + +/* Define the union csr_iob_rx_dma_reg_remap_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_dma_addr_base : 4; /* [3:0] */ + u32 cfg_sdi_dma_addr_size : 4; /* [7:4] */ + u32 cfg_sdi_dma_bar : 3; /* [10:8] */ + u32 rsv_12 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_dma_reg_remap_0_u; + +/* Define the union csr_iob_rx_dma_reg_remap_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_dma_pf_hit_en : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_dma_reg_remap_1_u; + +/* Define the union csr_iob_rx_axicache_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_axicache_wr_snp : 4; /* [3:0] */ + u32 iob_rx_axisnp_wr_snp : 1; /* [4] */ + u32 rsv_14 : 3; /* [7:5] */ + u32 iob_rx_axicache_wr_nosnp : 4; /* [11:8] */ + u32 iob_rx_axisnp_wr_nosnp : 1; /* [12] */ + u32 rsv_15 : 3; /* [15:13] */ + u32 iob_rx_axicache_rd_snp : 4; /* [19:16] */ + u32 iob_rx_axisnp_rd_snp : 1; /* [20] */ + u32 rsv_16 : 3; /* [23:21] */ + u32 iob_rx_axicache_rd_nosnp : 4; /* [27:24] */ + u32 iob_rx_axisnp_rd_nosnp : 1; /* [28] */ + u32 rsv_17 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_axicache_ctrl_u; + +/* Define the union csr_iob_rx_order_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_order_ctrl_am_pass_loc : 1; /* [0] */ + u32 iob_rx_order_ctrl_loc_pass_am : 1; /* [1] */ + u32 iob_rx_order_ctrl_msi_pass_all : 1; /* [2] */ + u32 iob_rx_order_ctrl_all_pass_msi : 1; /* [3] */ + u32 cfg_rx_order_ctrl_am_with_loc : 1; /* [4] */ + u32 cfg_rx_order_ctrl_loc_with_am : 1; /* [5] */ + u32 cfg_tl_ro : 1; /* [6] */ + u32 cfg_iob_rx_rdt_timeout : 16; /* [22:7] */ + u32 rsv_18 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_order_ctrl_u; + +/* Define the union csr_iob_rx_post_poison_forward_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_post_poison_forward : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_post_poison_forward_u; + +/* Define the union csr_iob_rx_poison_forward_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_poison_forward : 1; /* [0] */ + u32 cfg_atop_poison_forward : 1; /* [1] */ + u32 cfg_msg_poison_forward : 1; /* [2] */ + u32 cfg_local_poison_forward : 1; /* [3] */ + u32 rsv_20 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_poison_forward_u; + +/* Define the union csr_iob_rx_msi_int_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_msi_int_enable : 1; /* [0] */ + u32 iob_rx_msi_int_path : 1; /* [1] */ + u32 rsv_21 : 2; /* [3:2] */ + u32 iob_rx_msi_int_axicache : 4; /* [7:4] */ + u32 iob_rx_msi_int_axisnp : 1; /* [8] */ + u32 rsv_22 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_int_ctrl_u; + +/* Define the union csr_iob_rx_msi_int_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_msi_int_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_int_addr_high_u; + +/* Define the union csr_iob_rx_msi_int_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_msi_int_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_int_addr_low_u; + +/* Define the union csr_iob_rx_msi_int_prot_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_msi_int_prot_en : 1; /* [0] */ + u32 iob_rx_msi_int_prot_aer_ca : 1; /* [1] */ + u32 iob_rx_msi_int_prot_filter_poison : 1; /* [2] */ + u32 iob_rx_msi_int_poison_err_level : 2; /* [4:3] */ + u32 rsv_23 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_int_prot_ctrl_u; + +/* Define the union csr_iob_rx_itf_crd_atu_active_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_itf_crd_active_output_disable : 1; /* [0] */ + u32 iob_rx_itf_crd_active_input_disable : 1; /* [1] */ + u32 iob_rx_crd_number : 6; /* [7:2] */ + u32 iob_rx_port0_atu_en : 1; /* [8] */ + u32 rsv_24 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_itf_crd_atu_active_disable_u; + +/* Define the union csr_iob_rx_rc_atu_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_rc_atu_base_addr : 16; /* [15:0] */ + u32 iob_rx_rc_atu_tar_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_rc_atu_addr_u; + +/* Define the union csr_iob_rx_data_buffer_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_data_size_b : 5; /* [4:0] */ + u32 cfg_data_size_s : 5; /* [9:5] */ + u32 cfg_buffer_en : 1; /* [10] */ + u32 cfg_hed_size : 2; /* [12:11] */ + u32 cfg_timeout : 16; /* [28:13] */ + u32 cfg_not_only_use_small : 1; /* [29] */ + u32 rsv_25 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_data_buffer_size_u; + +/* Define the union csr_dfx_iob_rx_cnt_rx_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_rx_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_rx_req_u; + +/* Define the union csr_dfx_iob_rx_cnt_loc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_loc_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_loc_req_u; + +/* Define the union csr_dfx_iob_rx_cnt_send_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_send_am : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_send_am_u; + +/* Define the union csr_dfx_iob_rx_cnt_send_loc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_send_loc : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_send_loc_u; + +/* Define the union csr_dfx_iob_rx_cnt_dma_cpl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_dma_cpl : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_dma_cpl_u; + +/* Define the union csr_dfx_iob_rx_cnt_resp_rx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_resp_rx : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_resp_rx_u; + +/* Define the union csr_dfx_iob_rx_cnt_resp_loc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_resp_loc : 16; /* [15:0] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_resp_loc_u; + +/* Define the union csr_dfx_iob_rx_cnt_resp_recv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_resp_recv_am : 8; /* [7:0] */ + u32 dfx_iob_rx_cnt_resp_recv_loc : 8; /* [15:8] */ + u32 dfx_iob_rx_cnt_resp_recv_dma_cpl : 8; /* [23:16] */ + u32 dfx_iob_rx_cnt_zerowr_req : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_resp_recv_u; + +/* Define the union csr_dfx_iob_rx_cnt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_cnt_rdclr_en : 1; /* [0] */ + u32 dfx_iob_rx_cnt_disable : 1; /* [1] */ + u32 rsv_31 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_cnt_ctrl_u; + +/* Define the union csr_iob_rx_int_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_msk : 5; /* [4:0] */ + u32 rsv_32 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_msk_u; + +/* Define the union csr_iob_rx_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_status : 5; /* [4:0] */ + u32 rsv_33 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_status_u; + +/* Define the union csr_iob_rx_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_ro : 5; /* [4:0] */ + u32 rsv_34 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_ro_u; + +/* Define the union csr_iob_rx_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_set : 5; /* [4:0] */ + u32 rsv_35 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_set_u; + +/* Define the union csr_iob_rx_int_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_severity : 5; /* [4:0] */ + u32 rsv_36 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_severity_u; + +/* Define the union csr_iob_rx_int_ro_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_ro_ce : 5; /* [4:0] */ + u32 rsv_37 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_ro_ce_u; + +/* Define the union csr_iob_rx_int_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_ro_nfe : 5; /* [4:0] */ + u32 rsv_38 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_ro_nfe_u; + +/* Define the union csr_iob_rx_int_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_int_ro_fe : 5; /* [4:0] */ + u32 rsv_39 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_int_ro_fe_u; + +/* Define the union csr_iob_rx_aml_global_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_shutdown_req : 1; /* [0] */ + u32 iob_rx_aml_not_care_tble_vld : 1; /* [1] */ + u32 iob_rx_aml_aw_lat_en : 1; /* [2] */ + u32 iob_rx_aml_ar_lat_en : 1; /* [3] */ + u32 rsv_40 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_global_ctrl_u; + +/* Define the union csr_iob_rx_aml_max_trans_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_max_wr_trans : 8; /* [7:0] */ + u32 iob_rx_aml_max_rd_trans : 8; /* [15:8] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_max_trans_ctrl_u; + +/* Define the union csr_iob_rx_aml_qos_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_qos_wr : 4; /* [3:0] */ + u32 iob_rx_aml_qos_rd : 4; /* [7:4] */ + u32 iob_rx_aml_timeout : 10; /* [17:8] */ + u32 iob_rx_aml_dfx_max_trans_clear : 1; /* [18] */ + u32 rsv_42 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_qos_ctrl_u; + +/* Define the union csr_iob_rx_aml_wr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_same_awid : 1; /* [0] */ + u32 rsv_43 : 3; /* [3:1] */ + u32 iob_rx_aml_wdata_sync : 1; /* [4] */ + u32 rsv_44 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_wr_ctrl_u; + +/* Define the union csr_iob_rx_aml_rd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_same_arid : 1; /* [0] */ + u32 rsv_45 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_rd_ctrl_u; + +/* Define the union csr_iob_rx_aml_err_resp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_err_resp_wr_ctrl : 2; /* [1:0] */ + u32 rsv_46 : 2; /* [3:2] */ + u32 iob_rx_aml_err_resp_rd_ctrl : 2; /* [5:4] */ + u32 rsv_47 : 2; /* [7:6] */ + u32 iob_rx_aml_err_data_rd_ctrl : 2; /* [9:8] */ + u32 rsv_48 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_err_resp_ctrl_u; + +/* Define the union csr_iob_rx_aml_err_wdata_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_err_wdata_mode : 1; /* [0] */ + u32 rsv_49 : 3; /* [3:1] */ + u32 iob_rx_aml_err_wdata_resp : 2; /* [5:4] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_err_wdata_ctrl_u; + +/* Define the union csr_dfx_iob_rx_aml_idle_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_wr_idle : 1; /* [0] */ + u32 dfx_iob_rx_aml_rd_idle : 1; /* [1] */ + u32 dfx_iob_rx_idle : 1; /* [2] */ + u32 rsv_51 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_idle_state_u; + +/* Define the union csr_dfx_iob_rx_aml_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_max_trans_wr : 8; /* [7:0] */ + u32 dfx_iob_rx_aml_max_trans_rd : 8; /* [15:8] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_max_trans_u; + +/* Define the union csr_dfx_iob_rx_aml_itf_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_itf_sts : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_itf_sts_u; + +/* Define the union csr_dfx_iob_rx_aml_tbl_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_tbl_ptr_wr_free : 8; /* [7:0] */ + u32 dfx_iob_rx_aml_tbl_ptr_wr_resp : 8; /* [15:8] */ + u32 dfx_iob_rx_aml_tbl_ptr_rd_free : 8; /* [23:16] */ + u32 dfx_iob_rx_aml_tbl_ptr_rd_resp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_tbl_ptr_u; + +/* Define the union csr_dfx_iob_rx_aml_wr_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_aw_cnt : 16; /* [15:0] */ + u32 dfx_iob_rx_aml_b_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_wr_cnt_0_u; + +/* Define the union csr_dfx_iob_rx_aml_wr_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_w_cnt : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_wr_cnt_1_u; + +/* Define the union csr_dfx_iob_rx_aml_rd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_arlen_cnt : 16; /* [15:0] */ + u32 dfx_iob_rx_aml_r_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_rd_cnt_u; + +/* Define the union csr_dfx_iob_rx_aml_aw_lat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_aw_lat_last : 16; /* [15:0] */ + u32 dfx_iob_rx_aml_aw_lat_avg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_aw_lat_0_u; + +/* Define the union csr_dfx_iob_rx_aml_aw_lat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_aw_lat_max : 16; /* [15:0] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_aw_lat_1_u; + +/* Define the union csr_dfx_iob_rx_aml_ar_lat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_ar_lat_last : 16; /* [15:0] */ + u32 dfx_iob_rx_aml_ar_lat_avg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_ar_lat_0_u; + +/* Define the union csr_dfx_iob_rx_aml_ar_lat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_ar_lat_max : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_ar_lat_1_u; + +/* Define the union csr_dfx_iob_rx_aml_err_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_57 : 1; /* [0] */ + u32 dfx_iob_rx_aml_bresp_error_sts_1 : 1; /* [1] */ + u32 dfx_iob_rx_aml_bresp_error_sts_2 : 1; /* [2] */ + u32 dfx_iob_rx_aml_bresp_error_sts_3 : 1; /* [3] */ + u32 rsv_58 : 1; /* [4] */ + u32 dfx_iob_rx_aml_rresp_error_sts_1 : 1; /* [5] */ + u32 dfx_iob_rx_aml_rresp_error_sts_2 : 1; /* [6] */ + u32 dfx_iob_rx_aml_rresp_error_sts_3 : 1; /* [7] */ + u32 dfx_iob_rx_aml_rdata_error_sts : 1; /* [8] */ + u32 dfx_iob_rx_aml_wdata_error_sts : 1; /* [9] */ + u32 rsv_59 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_err_sts_u; + +/* Define the union csr_dfx_iob_rx_aml_wr_id_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_wr_id_sts_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_wr_id_sts_0_u; + +/* Define the union csr_dfx_iob_rx_aml_wr_id_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_wr_id_sts_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_wr_id_sts_1_u; + +/* Define the union csr_dfx_iob_rx_aml_rd_id_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_rd_id_sts_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_rd_id_sts_0_u; + +/* Define the union csr_dfx_iob_rx_aml_rd_id_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_iob_rx_aml_rd_id_sts_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_aml_rd_id_sts_1_u; + +/* Define the union csr_iob_rx_aml_strmid_rd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_strmid_rd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_strmid_rd_u; + +/* Define the union csr_iob_rx_aml_strmid_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_strmid_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_strmid_wr_u; + +/* Define the union csr_iob_rx_aml_axuser_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_fa_wr_en : 1; /* [0] */ + u32 iob_rx_aml_fa_rd_en : 1; /* [1] */ + u32 iob_rx_aml_fna_wr_en : 1; /* [2] */ + u32 iob_rx_aml_fna_rd_en : 1; /* [3] */ + u32 iob_rx_aml_cleaninvalid_en : 1; /* [4] */ + u32 iob_rx_aml_fp_en : 1; /* [5] */ + u32 iob_rx_aml_no_rd : 1; /* [6] */ + u32 iob_rx_aml_no_wr : 1; /* [7] */ + u32 iob_rx_aml_lock_rd : 1; /* [8] */ + u32 iob_rx_aml_lock_wr : 1; /* [9] */ + u32 iob_rx_aml_unlock_rd : 1; /* [10] */ + u32 iob_rx_aml_unlock_wr : 1; /* [11] */ + u32 iob_rx_aml_type_rd_en : 1; /* [12] */ + u32 iob_rx_aml_type_wr_en : 1; /* [13] */ + u32 iob_rx_aml_strmid_rd_en : 1; /* [14] */ + u32 iob_rx_aml_strmid_wr_en : 1; /* [15] */ + u32 iob_rx_aml_rd_ssv_en : 1; /* [16] */ + u32 iob_rx_aml_wr_ssv_en : 1; /* [17] */ + u32 iob_rx_aml_rd_ssv : 1; /* [18] */ + u32 iob_rx_aml_wr_ssv : 1; /* [19] */ + u32 iob_rx_aml_fa_wr : 1; /* [20] */ + u32 iob_rx_aml_fa_wr_msi : 1; /* [21] */ + u32 iob_rx_aml_fa_rd : 1; /* [22] */ + u32 iob_rx_aml_fa_rd_thrld : 4; /* [26:23] */ + u32 iob_rx_aml_fa_wr_thrld : 4; /* [30:27] */ + u32 iob_rx_aml_fp : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_axuser_ctrl1_u; + +/* Define the union csr_iob_rx_aml_axuser_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_fna_wr : 1; /* [0] */ + u32 iob_rx_aml_fna_wr_msi : 1; /* [1] */ + u32 iob_rx_aml_fna_rd : 1; /* [2] */ + u32 iob_rx_aml_fna_rd_thrld : 4; /* [6:3] */ + u32 iob_rx_aml_fna_wr_thrld : 4; /* [10:7] */ + u32 iob_rx_aml_cleaninvalid : 1; /* [11] */ + u32 iob_rx_aml_cleaninvalid_thrld : 4; /* [15:12] */ + u32 iob_rx_aml_type_rd : 2; /* [17:16] */ + u32 iob_rx_aml_type_wr : 2; /* [19:18] */ + u32 iob_rx_aml_type_rd_thrld : 4; /* [23:20] */ + u32 iob_rx_aml_type_wr_thrld : 4; /* [27:24] */ + u32 iob_rx_aml_th_rd : 1; /* [28] */ + u32 iob_rx_aml_th_wr : 1; /* [29] */ + u32 iob_rx_aml_so_rd : 1; /* [30] */ + u32 iob_rx_aml_so_wr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_axuser_ctrl2_u; + +/* Define the union csr_iob_rx_aml_axuser_ctrl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_stash_rd : 1; /* [0] */ + u32 iob_rx_aml_stash_wr : 1; /* [1] */ + u32 iob_rx_aml_stashlpid_rd : 8; /* [9:2] */ + u32 iob_rx_aml_stashlpid_wr : 8; /* [17:10] */ + u32 iob_rx_aml_stashlpidvalid_rd : 1; /* [18] */ + u32 iob_rx_aml_stashlpidvalid_wr : 1; /* [19] */ + u32 iob_rx_aml_stashnid_rd : 1; /* [20] */ + u32 iob_rx_aml_stashnid_wr : 1; /* [21] */ + u32 iob_rx_aml_soid_rd : 3; /* [24:22] */ + u32 iob_rx_aml_soid_wr : 3; /* [27:25] */ + u32 iob_rx_aml_soid_rd_en : 1; /* [28] */ + u32 iob_rx_aml_soid_wr_en : 1; /* [29] */ + u32 rsv_60 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_axuser_ctrl3_u; + +/* Define the union csr_iob_rx_aml_snoop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rx_aml_th_direct_en : 1; /* [0] */ + u32 iob_rx_aml_th_direct : 2; /* [2:1] */ + u32 iob_rx_aml_cmd_type_rd : 3; /* [5:3] */ + u32 iob_rx_aml_cmd_type_wr : 3; /* [8:6] */ + u32 iob_rx_aml_ato_type_rd : 2; /* [10:9] */ + u32 iob_rx_aml_ato_type_wr : 2; /* [12:11] */ + u32 iob_rx_aml_snoop_rd : 1; /* [13] */ + u32 iob_rx_aml_snoop_wr : 1; /* [14] */ + u32 iob_rx_aml_snoop_wr_msi : 1; /* [15] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_aml_snoop_u; + +/* Define the union csr_iob_rx_amb_global_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_shutdown_req : 1; /* [0] */ + u32 ctrl_en_256byte_wr : 1; /* [1] */ + u32 ctrl_en_256byte_rd : 1; /* [2] */ + u32 ctrl_pcie_at_check : 1; /* [3] */ + u32 ctrl_timeout_thres : 4; /* [7:4] */ + u32 rsv_62 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_global_ctrl_u; + +/* Define the union csr_iob_rx_amb_max_trans_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_max_trans_wr : 8; /* [7:0] */ + u32 ctrl_max_trans_rd : 8; /* [15:8] */ + u32 rsv_63 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_max_trans_ctrl_u; + +/* Define the union csr_iob_rx_amb_qos_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_qos_wr : 4; /* [3:0] */ + u32 ctrl_mem_qos_rd : 4; /* [7:4] */ + u32 ctrl_p2p_qos : 4; /* [11:8] */ + u32 rsv_64 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_qos_ctrl_u; + +/* Define the union csr_iob_rx_atop_endian_format_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_atop_endian_format : 1; /* [0] */ + u32 rsv_65 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_atop_endian_format_u; + +/* Define the union csr_iob_rx_safety_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_safety_level : 3; /* [2:0] */ + u32 rsv_66 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_safety_level_u; + +/* Define the union csr_iob_rx_amb_aruser_mode_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_aruser_strmid_mode : 1; /* [0] */ + u32 ctrl_aruser_ssv_mode : 1; /* [1] */ + u32 rsv_67 : 3; /* [4:2] */ + u32 ctrl_aruser_cleaninvalid_mode : 1; /* [5] */ + u32 rsv_68 : 2; /* [7:6] */ + u32 ctrl_aruser_type_mode : 2; /* [9:8] */ + u32 ctrl_aruser_so_mode : 1; /* [10] */ + u32 rsv_69 : 1; /* [11] */ + u32 ctrl_aruser_fa_mode : 2; /* [13:12] */ + u32 ctrl_aruser_fna_mode : 2; /* [15:14] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_aruser_mode_ctrl_u; + +/* Define the union csr_iob_rx_amb_aruser_set_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_aruser_strmid_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_aruser_set_0_u; + +/* Define the union csr_iob_rx_amb_aruser_set_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_aruser_ssv_set : 1; /* [0] */ + u32 rsv_71 : 3; /* [3:1] */ + u32 ctrl_aruser_so_set : 4; /* [7:4] */ + u32 rsv_72 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_aruser_set_1_u; + +/* Define the union csr_iob_rx_amb_aruser_set_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_readclean_threshold : 4; /* [3:0] */ + u32 ctrl_rd_type_threshond : 4; /* [7:4] */ + u32 ctrl_rd_fna_threshond : 4; /* [11:8] */ + u32 ctrl_rd_fa_threshold : 4; /* [15:12] */ + u32 rsv_73 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_aruser_set_2_u; + +/* Define the union csr_iob_rx_amb_awuser_mode_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_awuser_strmid_mode : 1; /* [0] */ + u32 ctrl_awuser_ssv_mode : 1; /* [1] */ + u32 rsv_74 : 4; /* [5:2] */ + u32 ctrl_awuser_fp_mode : 1; /* [6] */ + u32 rsv_75 : 1; /* [7] */ + u32 ctrl_awuser_type_mode : 2; /* [9:8] */ + u32 ctrl_awuser_so_mode : 1; /* [10] */ + u32 ctrl_awuser_stash_mode : 1; /* [11] */ + u32 ctrl_awuser_fa_mode : 2; /* [13:12] */ + u32 ctrl_awuser_fna_mode : 2; /* [15:14] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_awuser_mode_ctrl_u; + +/* Define the union csr_iob_rx_amb_awuser_set_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_awuser_strmid_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_awuser_set_0_u; + +/* Define the union csr_iob_rx_amb_awuser_set_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_awuser_ssv_set : 1; /* [0] */ + u32 rsv_77 : 3; /* [3:1] */ + u32 ctrl_awuser_so_set : 4; /* [7:4] */ + u32 rsv_78 : 4; /* [11:8] */ + u32 ctrl_awuser_stash_set : 3; /* [14:12] */ + u32 rsv_79 : 1; /* [15] */ + u32 ctrl_awuser_stash_lpid_set : 13; /* [28:16] */ + u32 rsv_80 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_awuser_set_1_u; + +/* Define the union csr_iob_rx_amb_awuser_set_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_81 : 1; /* [0] */ + u32 ctrl_int_so_optimize : 1; /* [1] */ + u32 rsv_82 : 2; /* [3:2] */ + u32 ctrl_wr_type_threshold : 4; /* [7:4] */ + u32 ctrl_wr_fna_threshond : 4; /* [11:8] */ + u32 ctrl_wr_fa_threshold : 4; /* [15:12] */ + u32 ctrl_wr_so_violate_threshold : 4; /* [19:16] */ + u32 rsv_83 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_awuser_set_2_u; + +/* Define the union csr_iob_rx_amb_err_resp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_err_resp_wr : 2; /* [1:0] */ + u32 rsv_84 : 2; /* [3:2] */ + u32 ctrl_err_resp_rd : 2; /* [5:4] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 ctrl_err_data_rd : 2; /* [9:8] */ + u32 rsv_86 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_err_resp_ctrl_u; + +/* Define the union csr_iob_rx_amb_err_wdata_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_err_wdata_mode : 1; /* [0] */ + u32 rsv_87 : 3; /* [3:1] */ + u32 ctrl_err_data_wr : 2; /* [5:4] */ + u32 rsv_88 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_amb_err_wdata_ctrl_u; + +/* Define the union csr_dfx_iob_rx_amb_cnt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_amb_cnt_enable : 1; /* [0] */ + u32 dfx_amb_cnt_clear : 1; /* [1] */ + u32 rsv_89 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_cnt_ctrl_u; + +/* Define the union csr_dfx_iob_rx_amb_wr_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_req_num_wr : 16; /* [15:0] */ + u32 dfx_trans_resp_num_wr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_wr_cnt_0_u; + +/* Define the union csr_dfx_iob_rx_amb_wr_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_awack_num : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_wr_cnt_1_u; + +/* Define the union csr_dfx_iob_rx_amb_rd_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_req_num_rdlen : 16; /* [15:0] */ + u32 dfx_trans_resp_num_rd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_rd_cnt_0_u; + +/* Define the union csr_dfx_iob_rx_amb_rd_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_req_num_rd : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_rd_cnt_1_u; + +/* Define the union csr_dfx_iob_rx_amb_atop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_atop_num : 16; /* [15:0] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_atop_cnt_u; + +/* Define the union csr_dfx_iob_rx_amb_int_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_int_num : 16; /* [15:0] */ + u32 rsv_93 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_int_num_u; + +/* Define the union csr_dfx_iob_rx_amb_int_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trans_int_rate : 12; /* [11:0] */ + u32 rsv_94 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_dfx_iob_rx_amb_int_rate_u; + +/* Define the union csr_iob_rx_pab_global_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pab_default_memattr : 4; /* [3:0] */ + u32 cfg_pab_default_snoop : 1; /* [4] */ + u32 rsv_95 : 3; /* [7:5] */ + u32 cfg_pab_disable_inbound_nosnoop : 1; /* [8] */ + u32 cfg_pab_disable_pasid : 1; /* [9] */ + u32 cfg_pab_pa_range_check : 1; /* [10] */ + u32 rsv_96 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_pab_global_ctrl_u; + +/* Define the union csr_iob_rx_pab_smmu_bypass_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_smmu_bypass : 16; /* [15:0] */ + u32 rsv_97 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_pab_smmu_bypass_ctrl_u; + +/* Define the union csr_iob_rx_pab_p2p_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pab_p2p_enable : 1; /* [0] */ + u32 rsv_98 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_pab_p2p_ctrl_u; + +/* Define the union csr_iob_rx_msi_msix_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_msix_enable : 1; /* [0] */ + u32 rsv_99 : 3; /* [3:1] */ + u32 msi_msix_axicache : 4; /* [7:4] */ + u32 msi_msix_snpattr : 1; /* [8] */ + u32 rsv_100 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_msix_ctrl_u; + +/* Define the union csr_iob_rx_msi_msix_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_msix_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_msix_addr_high_u; + +/* Define the union csr_iob_rx_msi_msix_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 3; /* [2:0] */ + u32 msi_msix_addr_low : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_msi_msix_addr_low_u; + +/* Define the union csr_iob_rx_memattr_win_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_en : 1; /* [0] */ + u32 rsv_102 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_memattr_win_en_u; + +/* Define the union csr_iob_rx_memattr_win_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_attr_rd : 5; /* [4:0] */ + u32 rsv_103 : 3; /* [7:5] */ + u32 cfg_memattr_win_attr_wr : 5; /* [12:8] */ + u32 rsv_104 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_memattr_win_attr_u; + +/* Define the union csr_iob_rx_memattr_win_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_memattr_win_addr_u; + +/* Define the union csr_iob_rx_memattr_win_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_iob_rx_reg_iob_rx_memattr_win_mask_u; + +/* Define the union csr_ib_p2p_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 io_space_enable : 1; /* [0] */ + u32 memory_space_enable : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_command_u; + +/* Define the union csr_ib_p2p_bus_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_1 : 8; /* [7:0] */ + u32 sec_bus_num : 8; /* [15:8] */ + u32 sub_bus_num : 8; /* [23:16] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_bus_number_u; + +/* Define the union csr_ib_p2p_io_range_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 io_base : 8; /* [7:0] */ + u32 io_limit : 8; /* [15:8] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_io_range_u; + +/* Define the union csr_ib_p2p_mem_range_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_base : 16; /* [15:0] */ + u32 mem_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_mem_range_u; + +/* Define the union csr_ib_p2p_pref_mem_range_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pref_mem_base : 16; /* [15:0] */ + u32 pref_mem_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_pref_mem_range_u; + +/* Define the union csr_ib_p2p_pref_mem_base_upper_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pref_mem_base_upper : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_pref_mem_base_upper_u; + +/* Define the union csr_ib_p2p_pref_mem_limit_upper_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pref_mem_limit_upper : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_ib_p2p_pref_mem_limit_upper_u; + +/* Define the union csr_io_p2p_io_upper_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 io_base_upper : 16; /* [15:0] */ + u32 io_limit_upper : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_p2p_reg_io_p2p_io_upper_u; + +/* Define the union csr_apat_buf_alloc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_index_reg_tout_thrsh : 15; /* [14:0] */ + u32 cfg_index_fifo_tout_thrsh : 15; /* [29:15] */ + u32 cfg_apat_pre_alloc_buf_en : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_buf_alloc_cfg_u; + +/* Define the union csr_apat_buf_alloc_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cpl_index_fifo_aful_cnt : 5; /* [4:0] */ + u32 rsv_0 : 3; /* [7:5] */ + u32 cfg_p_index_fifo_aful_cnt : 5; /* [12:8] */ + u32 rsv_1 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_buf_alloc_fifo_cfg_u; + +/* Define the union csr_apat_translation_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ptw_port_sel : 2; /* [1:0] */ + u32 rsv_2 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_translation_cfg_u; + +/* Define the union csr_apat_ats_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ats_trs_mode : 2; /* [1:0] */ + u32 cfg_ats_stu : 5; /* [6:2] */ + u32 cfg_ats_req_max_num : 10; /* [16:7] */ + u32 rsv_3 : 3; /* [19:17] */ + u32 cfg_ats_cpl_mem_attr : 1; /* [20] */ + u32 cfg_ats_cpl_ido : 1; /* [21] */ + u32 cfg_ats_cpl_ro : 1; /* [22] */ + u32 cfg_ats_cpl_attr : 2; /* [24:23] */ + u32 cfg_ats_cpl_untranslated : 1; /* [25] */ + u32 cfg_ats_cpl_global : 1; /* [26] */ + u32 cfg_ats_cpl_w : 1; /* [27] */ + u32 cfg_ats_cpl_fault_mode : 1; /* [28] */ + u32 cfg_ats_cpl_fault_pri : 1; /* [29] */ + u32 cfg_ats_aer_en : 1; /* [30] */ + u32 cfg_ats_cpl_err_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_ats_cfg_u; + +/* Define the union csr_apat_reqid_pasid_pri_exc_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ats_prefix_sel : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_reqid_pasid_pri_exc_mode_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stream_id_0 : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_0_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stream_id_1 : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_1_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stream_id_2 : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_2_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stream_id_3 : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_3_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sub_stream_id_0 : 20; /* [19:0] */ + u32 cfg_execute_bit_0 : 1; /* [20] */ + u32 cfg_priviledge_bit_0 : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_4_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sub_stream_id_1 : 20; /* [19:0] */ + u32 cfg_execute_bit_1 : 1; /* [20] */ + u32 cfg_priviledge_bit_1 : 1; /* [21] */ + u32 rsv_10 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_5_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sub_stream_id_2 : 20; /* [19:0] */ + u32 cfg_execute_bit_2 : 1; /* [20] */ + u32 cfg_priviledge_bit_2 : 1; /* [21] */ + u32 rsv_11 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_6_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sub_stream_id_3 : 20; /* [19:0] */ + u32 cfg_execute_bit_3 : 1; /* [20] */ + u32 cfg_priviledge_bit_3 : 1; /* [21] */ + u32 rsv_12 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_xilinx_hook_pasid_cfg_7_u; + +/* Define the union csr_apat_reqid_pasid_pri_exc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_apat_reqid_pasid_pri_exc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_reqid_pasid_pri_exc_cfg_u; + +/* Define the union csr_apat_reqid_pasid_pri_exc_rd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_apat_reqid_pasid_pri_exc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_reqid_pasid_pri_exc_rd_u; + +/* Define the union csr_apat_inv_pri_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_inv_req_flush_pri_en : 1; /* [0] */ + u32 cfg_inv_timeout_status : 1; /* [1] */ + u32 cfg_inv_comp_lkdn_sta : 1; /* [2] */ + u32 cfg_pri_req_odr_mode : 1; /* [3] */ + u32 cfg_pri_rsp_attr : 2; /* [5:4] */ + u32 cfg_pri_rsp_prefix_mask : 16; /* [21:6] */ + u32 cfg_inv_aer_en : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_inv_pri_cfg_u; + +/* Define the union csr_apat_inv_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_inv_timeout_thrsh : 30; /* [29:0] */ + u32 rsv_14 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_inv_timeout_u; + +/* Define the union csr_apat_inv_pri_credit_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_apat_cdt_active_dis : 1; /* [0] */ + u32 cfg_apat_cdt_cnt_clr : 1; /* [1] */ + u32 rsv_15 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_inv_pri_credit_cfg_u; + +/* Define the union csr_apat_int_ro_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_int_ro_ce : 1; /* [0] */ + u32 rsv_16 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_ro_ce_u; + +/* Define the union csr_apat_int_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_int_ro_nfe : 2; /* [1:0] */ + u32 rsv_17 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_ro_nfe_u; + +/* Define the union csr_apat_int_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_int_ro_fe : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_ro_fe_u; + +/* Define the union csr_apat_int_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_int_severity : 2; /* [1:0] */ + u32 rsv_19 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_severity_u; + +/* Define the union csr_apat_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_int_set : 2; /* [1:0] */ + u32 rsv_20 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_set_u; + +/* Define the union csr_apat_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_int_mask : 2; /* [1:0] */ + u32 rsv_21 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_mask_u; + +/* Define the union csr_apat_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int_status : 2; /* [1:0] */ + u32 rsv_22 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_status_u; + +/* Define the union csr_apat_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int_ro : 2; /* [1:0] */ + u32 rsv_23 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_int_ro_u; + +/* Define the union csr_apat_ram_ecc_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_err_inject : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_ram_ecc_err_inj_u; + +/* Define the union csr_apat_ram_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ecc_1bit_err_addr : 16; /* [15:0] */ + u32 ram_ecc_2bit_err_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_ram_ecc_err_addr_u; + +/* Define the union csr_apat_ram_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ecc_1bit_cnt : 5; /* [4:0] */ + u32 rsv_25 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_ram_ecc_1bit_err_cnt_u; + +/* Define the union csr_apat_ram_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ecc_2bit_cnt : 5; /* [4:0] */ + u32 rsv_26 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_ram_ecc_2bit_err_cnt_u; + +/* Define the union csr_apat_idle_set_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_apat_idle_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_idle_set_cfg_u; + +/* Define the union csr_apat_ats_request_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ats_idle : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_ats_request_idle_u; + +/* Define the union csr_apat_pri_request_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_pri_idle : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_pri_request_idle_u; + +/* Define the union csr_dfx_apat_ats_trs_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_trs_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_trs_status0_u; + +/* Define the union csr_dfx_apat_ats_trs_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_trs_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_trs_status1_u; + +/* Define the union csr_dfx_apat_ats_inv_status_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_inv_timeout_sts_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_inv_status_l_u; + +/* Define the union csr_dfx_apat_ats_inv_status_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_inv_timeout_sts_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_inv_status_h_u; + +/* Define the union csr_dfx_apat_ats_inv_lkdn_clr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_inv_lkdn_clr_sts_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_inv_lkdn_clr_l_u; + +/* Define the union csr_dfx_apat_ats_inv_lkdn_clr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_inv_lkdn_clr_sts_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_inv_lkdn_clr_h_u; + +/* Define the union csr_dfx_apat_ats_inv_pri_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pri_req_fifo_wr_of : 1; /* [0] */ + u32 dfx_inv_pri_status : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_inv_pri_status_u; + +/* Define the union csr_dfx_apat_cmd_port_miss_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cmd_port_miss_info : 18; /* [17:0] */ + u32 rsv_30 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_cmd_port_miss_u; + +/* Define the union csr_dfx_apat_rx_inv_cp_miss_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_inv_cp_miss_info : 17; /* [16:0] */ + u32 rsv_31 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_rx_inv_cp_miss_u; + +/* Define the union csr_dfx_apat_hdr_entry_rd_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_hdr_entry_rd_idx : 16; /* [15:0] */ + u32 rsv_32 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_hdr_entry_rd_idx_u; + +/* Define the union csr_dfx_apat_data_entry_rd_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_data_entry_rd_idx : 16; /* [15:0] */ + u32 rsv_33 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_data_entry_rd_idx_u; + +/* Define the union csr_dfx_apat_hdr_entry_rdata0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hdr_entry_rd_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_hdr_entry_rdata0_u; + +/* Define the union csr_dfx_apat_hdr_entry_rdata1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hdr_entry_rd_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_hdr_entry_rdata1_u; + +/* Define the union csr_dfx_apat_data_entry_rdata1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_data_entry_rd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_data_entry_rdata1_u; + +/* Define the union csr_dfx_apat_alloc_buf_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_buf_alloc_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_alloc_buf_status0_u; + +/* Define the union csr_dfx_apat_alloc_buf_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_buf_alloc_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_alloc_buf_status1_u; + +/* Define the union csr_dfx_apat_req_sch_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_req_retry_fifo_wr_of : 1; /* [0] */ + u32 dfx_req_sch_status : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_req_sch_status_u; + +/* Define the union csr_dfx_apat_ib_lkup_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_lkup_cnt : 16; /* [15:0] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ib_lkup_req_cnt_u; + +/* Define the union csr_dfx_apat_tlb_lkup_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tlb_lkup_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_tlb_lkup_req_cnt_u; + +/* Define the union csr_dfx_apat_tlb_retried_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tlb_retried_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_tlb_retried_req_cnt_u; + +/* Define the union csr_dfx_apat_tlb_rsp_success_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tlb_rsp_suc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_tlb_rsp_success_cnt_u; + +/* Define the union csr_dfx_apat_tlb_rsp_fault_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tlb_rsp_fault_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_tlb_rsp_fault_cnt_u; + +/* Define the union csr_dfx_apat_ats_trs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_trs_req_cnt : 16; /* [15:0] */ + u32 dfx_ats_trs_cpl_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_trs_cnt_u; + +/* Define the union csr_dfx_apat_ats_inv_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_inv_req_cnt : 16; /* [15:0] */ + u32 dfx_ats_inv_cp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_inv_cnt_u; + +/* Define the union csr_dfx_apat_ats_pri_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_pri_req_cnt : 16; /* [15:0] */ + u32 dfx_ats_pri_rsp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_ats_pri_cnt_u; + +/* Define the union csr_dfx_apat_smmu_inv_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_smmu_inv_req_cnt : 16; /* [15:0] */ + u32 dfx_smmu_inv_cp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_smmu_inv_cnt_u; + +/* Define the union csr_dfx_apat_smmu_pri_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_smmu_pri_req_cnt : 16; /* [15:0] */ + u32 dfx_smmu_pri_rsp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_smmu_pri_cnt_u; + +/* Define the union csr_dfx_apat_alloc_buf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_alloc_buf_ost_cnt : 5; /* [4:0] */ + u32 dfx_p_alloc_buf_ost_cnt : 5; /* [9:5] */ + u32 rsv_35 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_dfx_apat_alloc_buf_cnt_u; + +/* Define the union csr_apat_pcie2tbu_req_port_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie2tbu_req_port_sel : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_pcie2tbu_req_port_sel_u; + +/* Define the union csr_apat_pcie2tbu_req_qos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_req_payload_qos : 4; /* [3:0] */ + u32 cfg_pri_req_payload_qos : 4; /* [7:4] */ + u32 rsv_37 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_pcie2tbu_req_qos_u; + +/* Define the union csr_apat_pcie2tbu_req_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcie2tbu_req_axprot_ns : 1; /* [0] */ + u32 cfg_pcie2tbu_req_ns : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_apat_reg_apat_pcie2tbu_req_ns_u; + +/* Define the union csr_pcie_err_mapping_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_err_mapping : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_err_mapping_u; + +/* Define the union csr_pcie_ce_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_ce_ena : 16; /* [15:0] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ce_ena_u; + +/* Define the union csr_pcie_ce_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_ce_mask : 16; /* [15:0] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ce_mask_u; + +/* Define the union csr_pcie_unf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_unf_ena : 16; /* [15:0] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_unf_ena_u; + +/* Define the union csr_pcie_unf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_unf_mask : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_unf_mask_u; + +/* Define the union csr_pcie_uf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_uf_ena : 16; /* [15:0] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_uf_ena_u; + +/* Define the union csr_pcie_uf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_uf_mask : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_uf_mask_u; + +/* Define the union csr_pcie_ce_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_ce_status : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ce_status_u; + +/* Define the union csr_pcie_unf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_unf_status : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_unf_status_u; + +/* Define the union csr_pcie_uf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_uf_status : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_uf_status_u; + +/* Define the union csr_pcie_ce_cnt_port_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ce_cnt_port_cfg : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ce_cnt_port_cfg_u; + +/* Define the union csr_pcie_ce_cnt_local_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ce_cnt_local_cfg : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ce_cnt_local_cfg_u; + +/* Define the union csr_pcie_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_msi_mask_u; + +/* Define the union csr_pcie_msi_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_msi_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_msi_status_u; + +/* Define the union csr_pcie_ap_common_ni_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_ni_ena : 1; /* [0] */ + u32 rsv_11 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_ni_ena_u; + +/* Define the union csr_pcie_ap_common_ce_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_ce_ena : 1; /* [0] */ + u32 rsv_12 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_ce_ena_u; + +/* Define the union csr_pcie_ap_common_unf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_unf_ena : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_unf_ena_u; + +/* Define the union csr_pcie_ap_common_uf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_uf_ena : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_uf_ena_u; + +/* Define the union csr_pcie_ap_common_ni_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_ni_mask : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_ni_mask_u; + +/* Define the union csr_pcie_ap_common_ce_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_ce_mask : 1; /* [0] */ + u32 rsv_16 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_ce_mask_u; + +/* Define the union csr_pcie_ap_common_unf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_unf_mask : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_unf_mask_u; + +/* Define the union csr_pcie_ap_common_uf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_uf_mask : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_uf_mask_u; + +/* Define the union csr_pcie_ap_common_ni_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_ni_status : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_ni_status_u; + +/* Define the union csr_pcie_ap_common_ce_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_ce_status : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_ce_status_u; + +/* Define the union csr_pcie_ap_common_unf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_unf_status : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_unf_status_u; + +/* Define the union csr_pcie_ap_common_uf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ap_uf_status : 1; /* [0] */ + u32 rsv_22 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_common_uf_status_u; + +/* Define the union csr_pcie_ap_ep_ni_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_ni_ena : 1; /* [0] */ + u32 rsv_23 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_ni_ena_u; + +/* Define the union csr_pcie_ap_ep_ce_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_ce_ena : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_ce_ena_u; + +/* Define the union csr_pcie_ap_ep_unf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_unf_ena : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_unf_ena_u; + +/* Define the union csr_pcie_ap_ep_uf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_uf_ena : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_uf_ena_u; + +/* Define the union csr_pcie_ap_ep_ni_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_ni_mask : 1; /* [0] */ + u32 rsv_27 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_ni_mask_u; + +/* Define the union csr_pcie_ap_ep_ce_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_ce_mask : 1; /* [0] */ + u32 rsv_28 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_ce_mask_u; + +/* Define the union csr_pcie_ap_ep_unf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_unf_mask : 1; /* [0] */ + u32 rsv_29 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_unf_mask_u; + +/* Define the union csr_pcie_ap_ep_uf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_uf_mask : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_uf_mask_u; + +/* Define the union csr_pcie_ap_ep_ni_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_ni_status : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_ni_status_u; + +/* Define the union csr_pcie_ap_ep_ce_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_ce_status : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_ce_status_u; + +/* Define the union csr_pcie_ap_ep_unf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_unf_status : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_unf_status_u; + +/* Define the union csr_pcie_ap_ep_uf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_uf_status : 1; /* [0] */ + u32 rsv_34 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_ap_ep_uf_status_u; + +/* Define the union csr_pcie_core_ni_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_ni_ena : 1; /* [0] */ + u32 rsv_35 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_ni_ena_u; + +/* Define the union csr_pcie_core_ce_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_ce_ena : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_ce_ena_u; + +/* Define the union csr_pcie_core_unf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_unf_ena : 1; /* [0] */ + u32 rsv_37 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_unf_ena_u; + +/* Define the union csr_pcie_core_uf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_uf_ena : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_uf_ena_u; + +/* Define the union csr_pcie_core_ni_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_ni_mask : 1; /* [0] */ + u32 rsv_39 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_ni_mask_u; + +/* Define the union csr_pcie_core_ce_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_ce_mask : 1; /* [0] */ + u32 rsv_40 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_ce_mask_u; + +/* Define the union csr_pcie_core_unf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_unf_mask : 1; /* [0] */ + u32 rsv_41 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_unf_mask_u; + +/* Define the union csr_pcie_core_uf_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_uf_mask : 1; /* [0] */ + u32 rsv_42 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_uf_mask_u; + +/* Define the union csr_pcie_core_ni_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_ni_status : 1; /* [0] */ + u32 rsv_43 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_ni_status_u; + +/* Define the union csr_pcie_core_ce_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_ce_status : 1; /* [0] */ + u32 rsv_44 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_ce_status_u; + +/* Define the union csr_pcie_core_unf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_unf_status : 1; /* [0] */ + u32 rsv_45 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_unf_status_u; + +/* Define the union csr_pcie_core_uf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_core_uf_status : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_pcie_core_uf_status_u; + +/* Define the union csr_port_intx_mapping_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_intx_mapping : 12; /* [11:0] */ + u32 rsv_47 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_port_intx_mapping_u; + +/* Define the union csr_port_intx_interrupt_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ap_sys_intx_en : 1; /* [0] */ + u32 cfg_ap_intx_local_en : 1; /* [1] */ + u32 rsv_48 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_port_intx_interrupt_mode_u; + +/* Define the union csr_port_intx_assert_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_intx_assert_mask : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_port_intx_assert_mask_u; + +/* Define the union csr_port_intx_deassert_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_intx_deassert_mask : 16; /* [15:0] */ + u32 rsv_50 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_port_intx_deassert_mask_u; + +/* Define the union csr_port_intx_assert_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_intx_assert_status : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_port_intx_assert_status_u; + +/* Define the union csr_port_intx_deassert_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_intx_deassert_status : 16; /* [15:0] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_port_intx_deassert_status_u; + +/* Define the union csr_cfg_intx_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_inta_mask : 1; /* [0] */ + u32 port_intb_mask : 1; /* [1] */ + u32 port_intc_mask : 1; /* [2] */ + u32 port_intd_mask : 1; /* [3] */ + u32 rsv_53 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_intx_mask_u; + +/* Define the union csr_cfg_intx_linkdown_clr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_intx_linkdown_clr_en : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_intx_linkdown_clr_en_u; + +/* Define the union csr_cfg_intx_clr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_intx_clr_en : 16; /* [15:0] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_intx_clr_en_u; + +/* Define the union csr_cfg_intx_deassert_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_intx_deassert_mode : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_intx_deassert_mode_u; + +/* Define the union csr_cfg_odr_disp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_odr_disp_ctrl : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_odr_disp_ctrl_u; + +/* Define the union csr_cfg_port_err_clr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_err_clr_en : 20; /* [19:0] */ + u32 rsv_58 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_port_err_clr_en_u; + +/* Define the union csr_cfg_msi_aer_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msi_data_err_aer_en : 1; /* [0] */ + u32 cfg_msi_data_err_aer_st : 1; /* [1] */ + u32 rsv_59 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_msi_aer_ctrl_u; + +/* Define the union csr_cfg_int_type_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_type_ctrl : 1; /* [0] */ + u32 cfg_int_ext_ctrl : 2; /* [2:1] */ + u32 rsv_60 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_cfg_int_type_ctrl_u; + +/* Define the union csr_ap_1us_timer_thrsh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_1us_timer_thrsh : 11; /* [10:0] */ + u32 rsv_61 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_1us_timer_thrsh_u; + +/* Define the union csr_ap_port_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_port_en : 16; /* [15:0] */ + u32 rsv_62 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_port_en_u; + +/* Define the union csr_ap_shut_down_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_shut_down : 1; /* [0] */ + u32 rsv_63 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_shut_down_u; + +/* Define the union csr_ap_apb_syn_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_apb_syn_rst : 1; /* [0] */ + u32 rsv_64 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_apb_syn_rst_u; + +/* Define the union csr_ap_axi_syn_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_axi_syn_rst : 1; /* [0] */ + u32 rsv_65 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_axi_syn_rst_u; + +/* Define the union csr_ap_apb_func_syn_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_apb_func_syn_rst : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_apb_func_syn_rst_u; + +/* Define the union csr_ap_axi_func_syn_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_axi_func_syn_rst : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_axi_func_syn_rst_u; + +/* Define the union csr_ap_cfgspace_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_cfgspace_rst : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_cfgspace_rst_u; + +/* Define the union csr_ap_cap_tl_reg_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_cap_tl_reg_rst : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_cap_tl_reg_rst_u; + +/* Define the union csr_ap_apb_icg_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_apb_icg_en : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_apb_icg_en_u; + +/* Define the union csr_ap_axi_icg_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_axi_icg_en : 16; /* [15:0] */ + u32 rsv_71 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_axi_icg_en_u; + +/* Define the union csr_ap_sub_apb_icg_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_apb_iob_rx_icg_en : 1; /* [0] */ + u32 cfg_apb_iob_tx_icg_en : 1; /* [1] */ + u32 rsv_72 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_sub_apb_icg_en_u; + +/* Define the union csr_ap_sub_axi_icg_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ap_iob_rx_icg_en : 1; /* [0] */ + u32 cfg_ap_iob_tx_icg_en : 3; /* [3:1] */ + u32 cfg_ap_global_icg_en : 1; /* [4] */ + u32 rsv_73 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_sub_axi_icg_en_u; + +/* Define the union csr_ap_sub_icg_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ap_sub_icg_en : 1; /* [0] */ + u32 rsv_74 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_sub_icg_en_u; + +/* Define the union csr_ap_port_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_port_idle : 16; /* [15:0] */ + u32 rsv_75 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_port_idle_u; + +/* Define the union csr_ap_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_idle : 1; /* [0] */ + u32 rsv_76 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_idle_u; + +/* Define the union csr_ap_linkdown_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_linkdown_mask : 16; /* [15:0] */ + u32 rsv_77 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_linkdown_mask_u; + +/* Define the union csr_ap_linkdown_force_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_linkdown_force_idle : 16; /* [15:0] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_linkdown_force_idle_u; + +/* Define the union csr_ap_wait_idle_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_wait_idle_timer_trsh : 12; /* [11:0] */ + u32 rsv_79 : 4; /* [15:12] */ + u32 ap_wait_idle_timer_unit : 2; /* [17:16] */ + u32 rsv_80 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_wait_idle_timer_cfg_u; + +/* Define the union csr_ap_reset_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_linkdown_rst_en : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_ap_reset_cfg_u; + +/* Define the union csr_rcp_cfg_normal_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rcp_cdt_active_en : 1; /* [0] */ + u32 cfg_rcp_alc_buf_en : 1; /* [1] */ + u32 cfg_rcp_timeout_rls_en : 1; /* [2] */ + u32 rsv_82 : 1; /* [3] */ + u32 cfg_rcp_timeout_val : 8; /* [11:4] */ + u32 rsv_83 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_cfg_normal_ctrl_u; + +/* Define the union csr_rcp_cfg_err_rsp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rcp_tlp_err_cpl_en : 1; /* [0] */ + u32 cfg_rcp_tlp_err_aer_en : 1; /* [1] */ + u32 cfg_rcp_tlp_err_cs : 2; /* [3:2] */ + u32 cfg_rcp_tlp_rd_err_cpl_en : 1; /* [4] */ + u32 cfg_rcp_tlp_rd_err_aer_en : 1; /* [5] */ + u32 cfg_rcp_tlp_rd_err_cs : 2; /* [7:6] */ + u32 cfg_rcp_tlp_ep_err_aer_en : 1; /* [8] */ + u32 cfg_rcp_tlp_ep_err_cs : 2; /* [10:9] */ + u32 rsv_84 : 20; /* [30:11] */ + u32 cfg_rcp_tlp_mix_err_rsp_sel : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_cfg_err_rsp_ctrl_u; + +/* Define the union csr_rcp_net_pcie_pf_map0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_pcie_pf_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_net_pcie_pf_map0_u; + +/* Define the union csr_rcp_net_common_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_active_en_disable : 1; /* [0] */ + u32 net_p_data_cdt_clr : 1; /* [1] */ + u32 net_p_hed_cdt_clr : 1; /* [2] */ + u32 rsv_85 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_net_common_ctrl_u; + +/* Define the union csr_rcp_net_ecam_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_ecam_bus_num : 8; /* [7:0] */ + u32 net_ecam_base : 20; /* [27:8] */ + u32 rsv_86 : 3; /* [30:28] */ + u32 net_th_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_net_ecam_ctrl_u; + +/* Define the union csr_rcp_net_request_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_request_id : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_net_request_id_u; + +/* Define the union csr_rcp_net_pf_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_net_pf_num : 5; /* [4:0] */ + u32 net_pf_vf_first_num : 11; /* [15:5] */ + u32 net_pf_vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rcp_net_pf_ctrl_u; + +/* Define the union csr_rbd_cfg_p_odr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rbd_p_odr : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rbd_cfg_p_odr_ctrl_u; + +/* Define the union csr_rbd_cfg_credit_clr_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dat_cdt_cnt_clr : 9; /* [8:0] */ + u32 rsv_89 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rbd_cfg_credit_clr_ctrl0_u; + +/* Define the union csr_rbd_cfg_credit_clr_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_hed_cdt_cnt_clr : 9; /* [8:0] */ + u32 rsv_90 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rbd_cfg_credit_clr_ctrl1_u; + +/* Define the union csr_rbd_cfg_credit_dis_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdt_active_dis : 8; /* [7:0] */ + u32 rsv_91 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rbd_cfg_credit_dis_ctrl_u; + +/* Define the union csr_rbd_cfg_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rbd_aer_en : 1; /* [0] */ + u32 cfg_rbd_aer_ca : 1; /* [1] */ + u32 rsv_92 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_rbd_cfg_err_ctrl_u; + +/* Define the union csr_dfx_port_intx_pending_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_intx_pending_cnt : 16; /* [15:0] */ + u32 rsv_93 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_intx_pending_cnt_u; + +/* Define the union csr_dfx_core_intx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_core_intx_cnt : 16; /* [15:0] */ + u32 rsv_94 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_core_intx_cnt_u; + +/* Define the union csr_dfx_port_err_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_ce_cnt : 16; /* [15:0] */ + u32 dfx_port_ni_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_err_cnt0_u; + +/* Define the union csr_dfx_port_err_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_fe_cnt : 16; /* [15:0] */ + u32 dfx_port_nfe_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_err_cnt1_u; + +/* Define the union csr_dfx_ras_idle_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ras_idle : 1; /* [0] */ + u32 rsv_95 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_ras_idle_sts_u; + +/* Define the union csr_dfx_port_inta_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_inta_sts : 16; /* [15:0] */ + u32 rsv_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_inta_sts_u; + +/* Define the union csr_dfx_port_intb_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_intb_sts : 16; /* [15:0] */ + u32 rsv_97 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_intb_sts_u; + +/* Define the union csr_dfx_port_intc_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_intc_sts : 16; /* [15:0] */ + u32 rsv_98 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_intc_sts_u; + +/* Define the union csr_dfx_port_intd_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_intd_sts : 16; /* [15:0] */ + u32 rsv_99 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_port_intd_sts_u; + +/* Define the union csr_dfx_capt_tl_reg_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_capt_tl_reg_rdback_en : 1; /* [0] */ + u32 rsv_100 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_capt_tl_reg_ctrl_u; + +/* Define the union csr_dfx_acc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_acc_rdback_en : 1; /* [0] */ + u32 rsv_101 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_acc_ctrl_u; + +/* Define the union csr_dfx_acc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_acc_status : 4; /* [3:0] */ + u32 rsv_102 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_acc_status_u; + +/* Define the union csr_dfx_rcp_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rcp_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rcp_status0_u; + +/* Define the union csr_dfx_rcp_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rcp_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rcp_status1_u; + +/* Define the union csr_dfx_rcp_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rcp_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rcp_status2_u; + +/* Define the union csr_dfx_rcp_tlp_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rcp_tlp_hed_err_cnt : 8; /* [7:0] */ + u32 dfx_rcp_tlp_wdat_err_cnt : 8; /* [15:8] */ + u32 dfx_rcp_tlp_ep_err_cnt : 8; /* [23:16] */ + u32 dfx_rcp_tlp_rdat_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rcp_tlp_err_cnt_u; + +/* Define the union csr_dfx_rcp_net_th_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_net_th_err_resp : 1; /* [0] */ + u32 dfx_net_th_fsm_st : 2; /* [2:1] */ + u32 rsv_103 : 5; /* [7:3] */ + u32 dfx_net_th_sync_cnt : 8; /* [15:8] */ + u32 rsv_104 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rcp_net_th_status_u; + +/* Define the union csr_dfx_rbd_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rbd_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rbd_status_u; + +/* Define the union csr_dfx_rbd_ack_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rbd_ack_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rbd_ack_fifo_status_u; + +/* Define the union csr_dfx_rbd_cdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rbd_cdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rbd_cdt_cnt_u; + +/* Define the union csr_dfx_rbd_ptr_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rbd_ptr_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_global_reg_dfx_rbd_ptr_fifo_status_u; + +/* Define the union csr_pcie_pmu_global_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_global_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_global_ctrl_u; + +/* Define the union csr_pcie_pmu_common_ctrl_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_common_ctrl_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_ctrl_l_u; + +/* Define the union csr_pcie_pmu_common_ctrl_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_common_ctrl_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_ctrl_h_u; + +/* Define the union csr_pcie_pmu_common_counter_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_common_cnt_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_counter_l_u; + +/* Define the union csr_pcie_pmu_common_counter_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_common_cnt_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_counter_h_u; + +/* Define the union csr_pcie_pmu_common_ext_counter_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_common_ext_cnt_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_ext_counter_l_u; + +/* Define the union csr_pcie_pmu_common_ext_counter_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_common_ext_cnt_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_ext_counter_h_u; + +/* Define the union csr_pcie_pmu_common_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_overflow_status : 1; /* [0] */ + u32 pmu_timer_int_status : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_status_u; + +/* Define the union csr_pcie_pmu_common_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_overflow_mask : 1; /* [0] */ + u32 pmu_timer_int_mask : 1; /* [1] */ + u32 rsv_1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_common_mask_u; + +/* Define the union csr_pcie_pmu_mailbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmu_mailbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_pmu_mailbox_u; + +/* Define the union csr_pcie_ptt_tuning_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_tuning_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_tuning_ctrl_u; + +/* Define the union csr_pcie_ptt_tuning_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_tuning_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_tuning_data_u; + +/* Define the union csr_pcie_ptt_trace_addr_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_trace_addr_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_addr_size_u; + +/* Define the union csr_pcie_ptt_trace_addr_base_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_trace_addr_base_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_addr_base_l_u; + +/* Define the union csr_pcie_ptt_trace_addr_base_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_trace_addr_base_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_addr_base_h_u; + +/* Define the union csr_pcie_ptt_trace_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_trace_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_ctrl_u; + +/* Define the union csr_pcie_ptt_trace_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_buffer_full_status : 4; /* [3:0] */ + u32 rsv_2 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_int_status_u; + +/* Define the union csr_pcie_ptt_trace_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_buffer_full_mask : 4; /* [3:0] */ + u32 rsv_3 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_int_mask_u; + +/* Define the union csr_pcie_ptt_trace_wr_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_buffer_wr_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_wr_sts_u; + +/* Define the union csr_pcie_ptt_trace_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_idle : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_sts_u; + +/* Define the union csr_pcie_ptt_trace_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_hed_cdt_mode : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_cfg_u; + +/* Define the union csr_pcie_ptt_trace_ram_ecc_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ecc_err_inject : 3; /* [2:0] */ + u32 rsv_6 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_ram_ecc_inj_u; + +/* Define the union csr_pcie_ptt_trace_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tout_dump_hed_ind : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_trace_dfx_u; + +/* Define the union csr_pcie_ptt_mailbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptt_mailbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pmt_reg_pcie_ptt_mailbox_u; + +/* Define the union csr_mctp_queue_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_en : 1; /* [0] */ + u32 mctp_rx_en : 1; /* [1] */ + u32 mctp_tx_reset : 1; /* [2] */ + u32 mctp_rx_reset : 1; /* [3] */ + u32 mctp_tx_coal_en : 1; /* [4] */ + u32 mctp_rx_coal_en : 1; /* [5] */ + u32 mctp_queue_work_mode : 1; /* [6] */ + u32 mctp_queue_msg_type : 3; /* [9:7] */ + u32 mctp_queue_ep_mapping : 4; /* [13:10] */ + u32 rsv_0 : 2; /* [15:14] */ + u32 mctp_queue_unit : 2; /* [17:16] */ + u32 rsv_1 : 1; /* [18] */ + u32 mctp_rx_buffer_full_drop_en : 1; /* [19] */ + u32 rsv_2 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_queue_ctrl_u; + +/* Define the union csr_mctp_rx_base_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_base_addr_high_u; + +/* Define the union csr_mctp_rx_base_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_base_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_base_addr_low_u; + +/* Define the union csr_mctp_rx_queue_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_depth : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_queue_depth_u; + +/* Define the union csr_mctp_rx_afull_threshold_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_afull_threshold : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_afull_threshold_u; + +/* Define the union csr_mctp_rx_queue_head_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_head : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_queue_head_u; + +/* Define the union csr_mctp_rx_queue_tail_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_tail : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_queue_tail_u; + +/* Define the union csr_mctp_tx_base_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_base_addr_high_u; + +/* Define the union csr_mctp_tx_base_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_base_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_base_addr_low_u; + +/* Define the union csr_mctp_tx_queue_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_depth : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_queue_depth_u; + +/* Define the union csr_mctp_tx_queue_head_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_head : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_queue_head_u; + +/* Define the union csr_mctp_tx_queue_tail_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_tail : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_queue_tail_u; + +/* Define the union csr_mctp_int_mapping_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_map : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_map : 1; /* [1] */ + u32 mctp_rx_other_msg_cpl_int_map : 1; /* [2] */ + u32 mctp_rx_buffer_afull_int_map : 1; /* [3] */ + u32 mctp_tx_len_err_drop_int_map : 1; /* [4] */ + u32 mctp_tx_alloc_buff_fail_drop_int_map : 1; /* [5] */ + u32 mctp_rx_tlp_err_drop_int_map : 1; /* [6] */ + u32 mctp_rx_buff_full_drop_int_map : 1; /* [7] */ + u32 mctp_tx_axi_err_int_map : 1; /* [8] */ + u32 mctp_rx_axi_err_int_map : 1; /* [9] */ + u32 rsv_10 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_int_mapping_u; + +/* Define the union csr_mctp_intrpt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_sts : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_sts : 1; /* [1] */ + u32 mctp_rx_other_msg_cpl_int_sts : 1; /* [2] */ + u32 mctp_rx_buffer_afull_int_sts : 1; /* [3] */ + u32 mctp_tx_len_err_drop_int_sts : 1; /* [4] */ + u32 mctp_tx_alloc_buff_fail_drop_int_sts : 1; /* [5] */ + u32 mctp_rx_tlp_err_drop_int_sts : 1; /* [6] */ + u32 mctp_rx_buff_full_drop_int_sts : 1; /* [7] */ + u32 mctp_tx_axi_err_int_sts : 1; /* [8] */ + u32 mctp_rx_axi_err_int_sts : 1; /* [9] */ + u32 rsv_11 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_intrpt_sta_u; + +/* Define the union csr_mctp_intrpt_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_set : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_set : 1; /* [1] */ + u32 mctp_rx_other_msg_cpl_int_set : 1; /* [2] */ + u32 mctp_rx_buffer_afull_int_set : 1; /* [3] */ + u32 mctp_tx_len_err_drop_int_set : 1; /* [4] */ + u32 mctp_tx_alloc_buff_fail_drop_int_set : 1; /* [5] */ + u32 mctp_rx_tlp_err_drop_int_set : 1; /* [6] */ + u32 mctp_rx_buff_full_drop_int_set : 1; /* [7] */ + u32 mctp_tx_axi_err_int_set : 1; /* [8] */ + u32 mctp_rx_axi_err_int_set : 1; /* [9] */ + u32 rsv_12 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_intrpt_set_u; + +/* Define the union csr_mctp_intrpt_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_mask : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_mask : 1; /* [1] */ + u32 mctp_rx_other_msg_cpl_int_mask : 1; /* [2] */ + u32 mctp_rx_buffer_afull_int_mask : 1; /* [3] */ + u32 mctp_tx_len_err_drop_int_mask : 1; /* [4] */ + u32 mctp_tx_alloc_buff_fail_drop_int_mask : 1; /* [5] */ + u32 mctp_rx_tlp_err_drop_int_mask : 1; /* [6] */ + u32 mctp_rx_buff_full_drop_int_mask : 1; /* [7] */ + u32 mctp_tx_axi_err_int_mask : 1; /* [8] */ + u32 mctp_rx_axi_err_int_mask : 1; /* [9] */ + u32 rsv_13 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_intrpt_mask_u; + +/* Define the union csr_mctp_intrpt_source_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_src : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_src : 1; /* [1] */ + u32 mctp_rx_other_msg_cpl_int_src : 1; /* [2] */ + u32 mctp_rx_buff_afull_int_src : 1; /* [3] */ + u32 mctp_tx_len_err_drop_int_src : 1; /* [4] */ + u32 mctp_tx_alloc_buff_fail_drop_int_src : 1; /* [5] */ + u32 mctp_rx_tlp_err_drop_int_src : 1; /* [6] */ + u32 mctp_rx_buff_full_drop_int_src : 1; /* [7] */ + u32 mctp_tx_axi_err_int_src : 1; /* [8] */ + u32 mctp_rx_axi_err_int_src : 1; /* [9] */ + u32 rsv_14 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_intrpt_source_u; + +/* Define the union csr_mctp_rx_send_hed_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_strmid : 16; /* [15:0] */ + u32 mctp_rx_attr : 3; /* [18:16] */ + u32 rsv_15 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_send_hed_ctrl_u; + +/* Define the union csr_mctp_tx_send_hed_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_strmid : 16; /* [15:0] */ + u32 mctp_tx_attr : 3; /* [18:16] */ + u32 rsv_16 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_send_hed_ctrl_u; + +/* Define the union csr_mctp_hed_check_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_hdr_vdid_field : 16; /* [15:0] */ + u32 mctp_rx_msg_code : 8; /* [23:16] */ + u32 mctp_hdr_vdm_field : 4; /* [27:24] */ + u32 rsv_17 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_hed_check_u; + +/* Define the union csr_mctp_common_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 broadcast_ctrl : 1; /* [0] */ + u32 tx_active_en_disable : 1; /* [1] */ + u32 rx_active_en_disable : 1; /* [2] */ + u32 tx_np_hed_cdt_clr : 1; /* [3] */ + u32 rx_p_data_cdt_clr : 1; /* [4] */ + u32 rx_p_hed_cdt_clr : 1; /* [5] */ + u32 int_type_ctrl : 1; /* [6] */ + u32 int_pulse_exp_ctrl : 2; /* [8:7] */ + u32 rsv_18 : 2; /* [10:9] */ + u32 request_id_field_ctrl : 1; /* [11] */ + u32 rsv_19 : 4; /* [15:12] */ + u32 tqm_fail_cnt_th : 4; /* [19:16] */ + u32 rsv_20 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_common_ctrl_u; + +/* Define the union csr_mctp_rx_coal_cnt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_multi_th : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_coal_cnt_ctrl_u; + +/* Define the union csr_mctp_rx_coal_time_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_coal_time : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_rx_coal_time_ctrl_u; + +/* Define the union csr_mctp_tx_coal_cnt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_multi_th : 8; /* [7:0] */ + u32 rsv_23 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_coal_cnt_ctrl_u; + +/* Define the union csr_mctp_tx_coal_time_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_coal_time : 8; /* [7:0] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_tx_coal_time_ctrl_u; + +/* Define the union csr_mctp_ack_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 p_ack_mode : 1; /* [0] */ + u32 rx_drop_p_ack_user : 4; /* [4:1] */ + u32 rsv_25 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_mctp_ack_ctrl_u; + +/* Define the union csr_dfx_mctp_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_if_fsm_st : 4; /* [3:0] */ + u32 rsv_26 : 1; /* [4] */ + u32 mctp_rx_if_fsm_st : 4; /* [8:5] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 mctp_tx_idle : 1; /* [16] */ + u32 mctp_rx_idle : 1; /* [17] */ + u32 rsv_28 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_status_u; + +/* Define the union csr_dfx_mctp_port_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_port_idle : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_port_idle_u; + +/* Define the union csr_dfx_mctp_ost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_outstanding_cnt : 8; /* [7:0] */ + u32 rsv_30 : 8; /* [15:8] */ + u32 mctp_rx_outstanding_cnt : 8; /* [23:16] */ + u32 rsv_31 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_ost_cnt_u; + +/* Define the union csr_dfx_mctp_rx_cdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_remaind_p_hed_cdt_cnt : 8; /* [7:0] */ + u32 rsv_32 : 8; /* [15:8] */ + u32 rx_remaind_p_data_cdt_cnt : 12; /* [27:16] */ + u32 rsv_33 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_cdt_cnt_u; + +/* Define the union csr_dfx_mctp_tx_cdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_remaind_np_hed_cdt_cnt : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_tx_cdt_cnt_u; + +/* Define the union csr_dfx_mctp_rx_rec_cdt_gap_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_rec_hed_cdt_gap_cnt : 8; /* [7:0] */ + u32 rsv_35 : 8; /* [15:8] */ + u32 rx_rec_data_cdt_gap_cnt : 12; /* [27:16] */ + u32 rsv_36 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_rec_cdt_gap_cnt_u; + +/* Define the union csr_dfx_mctp_rx_sent_cdt_gap_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_sent_hed_cdt_gap_cnt : 8; /* [7:0] */ + u32 rsv_37 : 8; /* [15:8] */ + u32 rx_sent_data_cdt_gap_cnt : 12; /* [27:16] */ + u32 rsv_38 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_sent_cdt_gap_cnt_u; + +/* Define the union csr_dfx_mctp_tx_cdt_gap_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_rec_hed_cdt_gap_cnt : 8; /* [7:0] */ + u32 rsv_39 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_tx_cdt_gap_cnt_u; + +/* Define the union csr_dfx_mctp_rx_axi_err_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_axi_err_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_axi_err_addr_high_u; + +/* Define the union csr_dfx_mctp_rx_axi_err_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_axi_err_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_axi_err_addr_low_u; + +/* Define the union csr_dfx_mctp_common_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_route_err_drop : 1; /* [0] */ + u32 mctp_rx_route_err_drop_msg_port : 4; /* [4:1] */ + u32 rsv_40 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_common_err_u; + +/* Define the union csr_dfx_mctp_stat_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_stat_mode : 1; /* [0] */ + u32 mctp_stat_queue_num : 5; /* [5:1] */ + u32 rsv_41 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_stat_ctrl_u; + +/* Define the union csr_dfx_mctp_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_err_msg_cnt : 16; /* [15:0] */ + u32 mctp_rx_err_msg_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_err_pkt_cnt_u; + +/* Define the union csr_dfx_mctp_tx_pkt_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_num : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_tx_pkt_num_u; + +/* Define the union csr_dfx_mctp_rx_pkt_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_other_msg_num : 16; /* [15:0] */ + u32 mctp_rx_mctp_msg_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_pkt_num_u; + +/* Define the union csr_dfx_mctp_queue_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_fsm_st : 4; /* [3:0] */ + u32 rsv_43 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_queue_fsm_u; + +/* Define the union csr_dfx_mctp_rx_queue_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_idle : 1; /* [0] */ + u32 rsv_44 : 7; /* [7:1] */ + u32 mctp_rx_queue_ost_cnt : 7; /* [14:8] */ + u32 rsv_45 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_rx_queue_sta_u; + +/* Define the union csr_dfx_mctp_tx_queue_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_idle : 1; /* [0] */ + u32 rsv_46 : 7; /* [7:1] */ + u32 mctp_tx_queue_shared_ost_cnt : 7; /* [14:8] */ + u32 rsv_47 : 1; /* [15] */ + u32 mctp_tx_queue_owned_ost_cnt : 4; /* [19:16] */ + u32 rsv_48 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_mctp_reg_dfx_mctp_tx_queue_sta_u; + +/* Define the union csr_rba_int_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_msk : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_msk_u; + +/* Define the union csr_rba_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_status : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_status_u; + +/* Define the union csr_rba_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_ro : 6; /* [5:0] */ + u32 rsv_2 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_ro_u; + +/* Define the union csr_rba_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_set : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_set_u; + +/* Define the union csr_rba_int_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_severity : 6; /* [5:0] */ + u32 cfg_ram_ecc_int_severity : 2; /* [7:6] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_severity_u; + +/* Define the union csr_rba_int_ro_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_ro_ce : 6; /* [5:0] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_ro_ce_u; + +/* Define the union csr_rba_int_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_ro_nfe : 6; /* [5:0] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_ro_nfe_u; + +/* Define the union csr_rba_int_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_int_ro_fe : 6; /* [5:0] */ + u32 rsv_7 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_int_ro_fe_u; + +/* Define the union csr_rba_dma_smmu_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_smmu_bypass_cfg : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_dma_smmu_bypass_cfg_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_0_h : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_0_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_0_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_0_l_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_1_h : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_1_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_1_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_1_l_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_2_h : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_2_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_2_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_2_l_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_3_h : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_3_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_3_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_3_l_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_4_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_4_h : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_4_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_4_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_4_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_4_l_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_5_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_5_h : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_5_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_5_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_5_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_5_l_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_6_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_daw_6_h : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_6_h_u; + +/* Define the union csr_rba_ctrl_dma_mem_daw_6_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_mem_dat_6_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_mem_daw_6_l_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_0_ll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_0_ll : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_0_ll_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_0_lh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_0_lh : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_0_lh_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_0_hl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_0_hl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_0_hl_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_0_hh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_0_hh : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_0_hh_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_1_ll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_1_ll : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_1_ll_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_1_lh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_1_lh : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_1_lh_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_1_hl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_1_hl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_1_hl_u; + +/* Define the union csr_rba_ctrl_mctp_mem_daw_1_hh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_mem_daw_1_hh : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_mctp_mem_daw_1_hh_u; + +/* Define the union csr_rba_ctrl_iep_mem_daw_0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_iep_mem_daw_0_h : 16; /* [15:0] */ + u32 rsv_20 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_iep_mem_daw_0_h_u; + +/* Define the union csr_rba_ctrl_iep_mem_daw_0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_iep_mem_dat_0_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_iep_mem_daw_0_l_u; + +/* Define the union csr_rba_ctrl_iep_mem_daw_1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_iep_mem_daw_1_h : 16; /* [15:0] */ + u32 rsv_21 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_iep_mem_daw_1_h_u; + +/* Define the union csr_rba_ctrl_iep_mem_daw_1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_iep_mem_dat_1_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_iep_mem_daw_1_l_u; + +/* Define the union csr_rba_ctrl_dma_attr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_cache_0 : 4; /* [3:0] */ + u32 rba_ctrl_dma_snpattr_0 : 1; /* [4] */ + u32 rsv_22 : 3; /* [7:5] */ + u32 rba_ctrl_dma_cache_1 : 4; /* [11:8] */ + u32 rba_ctrl_dma_snpattr_1 : 1; /* [12] */ + u32 rsv_23 : 3; /* [15:13] */ + u32 rba_ctrl_dma_cache_2 : 4; /* [19:16] */ + u32 rba_ctrl_dma_snpattr_2 : 1; /* [20] */ + u32 rsv_24 : 3; /* [23:21] */ + u32 rba_ctrl_dma_cache_3 : 4; /* [27:24] */ + u32 rba_ctrl_dma_snpattr_3 : 1; /* [28] */ + u32 rsv_25 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_attr_1_u; + +/* Define the union csr_rba_ctrl_dma_attr_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_dma_cache_4 : 4; /* [3:0] */ + u32 rba_ctrl_dma_snpattr_4 : 1; /* [4] */ + u32 rsv_26 : 3; /* [7:5] */ + u32 rba_ctrl_dma_cache_5 : 4; /* [11:8] */ + u32 rba_ctrl_dma_snpattr_5 : 1; /* [12] */ + u32 rsv_27 : 3; /* [15:13] */ + u32 rba_ctrl_dma_cache_6 : 4; /* [19:16] */ + u32 rba_ctrl_dma_snpattr_6 : 1; /* [20] */ + u32 rsv_28 : 3; /* [23:21] */ + u32 rba_ctrl_dma_cache_7 : 4; /* [27:24] */ + u32 rba_ctrl_dma_snpattr_7 : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_dma_attr_2_u; + +/* Define the union csr_rba_ctrl_sdi_iep_cfg_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_iep_cfg_cache : 4; /* [3:0] */ + u32 rba_ctrl_iep_cfg_snpattr : 1; /* [4] */ + u32 rsv_30 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_sdi_iep_cfg_attr_u; + +/* Define the union csr_rba_ctrl_sdi_rcp_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_rcp_cache : 4; /* [3:0] */ + u32 rba_ctrl_rcp_snpattr : 1; /* [4] */ + u32 rsv_31 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_sdi_rcp_attr_u; + +/* Define the union csr_rba_ctrl_sdi_nvme_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_nvme_cache : 4; /* [3:0] */ + u32 rba_ctrl_nvme_snpattr : 1; /* [4] */ + u32 rsv_32 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_sdi_nvme_attr_u; + +/* Define the union csr_rba_ctrl_sdi_mctp_attr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_cache0 : 4; /* [3:0] */ + u32 rba_ctrl_mctp_snpattr0 : 1; /* [4] */ + u32 rsv_33 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_sdi_mctp_attr0_u; + +/* Define the union csr_rba_ctrl_sdi_mctp_attr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_cache1 : 4; /* [3:0] */ + u32 rba_ctrl_mctp_snpattr1 : 1; /* [4] */ + u32 rsv_34 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_sdi_mctp_attr1_u; + +/* Define the union csr_rba_ctrl_sdi_mctp_attr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ctrl_mctp_cache2 : 4; /* [3:0] */ + u32 rba_ctrl_mctp_snpattr2 : 1; /* [4] */ + u32 rsv_35 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ctrl_sdi_mctp_attr2_u; + +/* Define the union csr_rba_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_weight_cfg : 30; /* [29:0] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_weight_cfg_u; + +/* Define the union csr_rba_active_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba2mctp_active_cfg : 1; /* [0] */ + u32 rba2rcp_active_cfg : 1; /* [1] */ + u32 rba2nvme_active_cfg : 1; /* [2] */ + u32 rba2iep_active_cfg : 1; /* [3] */ + u32 rba2mctp_np_active_cfg : 1; /* [4] */ + u32 rsv_37 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_active_cfg_u; + +/* Define the union csr_rba_rcp_deep_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rcp_end_cfg : 2; /* [1:0] */ + u32 deep_wr_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_rcp_deep_cfg_u; + +/* Define the union csr_rba_nvme_deep_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_end_cfg : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_nvme_deep_cfg_u; + +/* Define the union csr_rba_mode_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 order_cfg : 1; /* [0] */ + u32 iep_so_cfg : 1; /* [1] */ + u32 iep_bypass : 1; /* [2] */ + u32 mctp_protect : 1; /* [3] */ + u32 rsv_40 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_mode_cfg_u; + +/* Define the union csr_dfx_rba_cnt_head_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rba_cnt_head : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_dfx_rba_cnt_head_u; + +/* Define the union csr_dfx_rba_cnt_err_head_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rba_cnt_err_head : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_dfx_rba_cnt_err_head_u; + +/* Define the union csr_dfx_rba_buffer_useddeep_mctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rba_buffer_used_wr : 8; /* [7:0] */ + u32 dfx_rba_buffer_used_rd : 8; /* [15:8] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_dfx_rba_buffer_useddeep_mctp_u; + +/* Define the union csr_dfx_rba_buffer_useddeep_other_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rba_buffer_used_rcp : 2; /* [1:0] */ + u32 dfx_rba_buffer_used_nvme : 2; /* [3:2] */ + u32 dfx_rba_buffer_used_iep : 4; /* [7:4] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_dfx_rba_buffer_useddeep_other_u; + +/* Define the union csr_dfx_rba_arbiter_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rba_arbiter_en : 1; /* [0] */ + u32 rsv_45 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_dfx_rba_arbiter_en_u; + +/* Define the union csr_dfx_rba_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_idle : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_dfx_rba_idle_u; + +/* Define the union csr_rba_ram_ecc_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_err_inject : 3; /* [2:0] */ + u32 rsv_47 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ram_ecc_err_inj_u; + +/* Define the union csr_rba_ram_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ecc_1bit_err_addr : 16; /* [15:0] */ + u32 ram_ecc_2bit_err_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ram_ecc_err_addr_u; + +/* Define the union csr_rba_ram_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ecc_1bit_cnt : 5; /* [4:0] */ + u32 rsv_48 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ram_ecc_1bit_err_cnt_u; + +/* Define the union csr_rba_ram_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_ecc_2bit_cnt : 5; /* [4:0] */ + u32 rsv_49 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_ram_ecc_2bit_err_cnt_u; + +/* Define the union csr_rba_intecc_ro_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_intecc_ro_ce : 1; /* [0] */ + u32 rsv_50 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_ro_ce_u; + +/* Define the union csr_rba_intecc_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_intecc_ro_nfe : 2; /* [1:0] */ + u32 rsv_51 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_ro_nfe_u; + +/* Define the union csr_rba_intecc_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_intecc_ro_fe : 1; /* [0] */ + u32 rsv_52 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_ro_fe_u; + +/* Define the union csr_rba_intecc_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_int_set : 2; /* [1:0] */ + u32 rsv_53 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_set_u; + +/* Define the union csr_rba_intecc_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ram_ecc_int_mask : 2; /* [1:0] */ + u32 rsv_54 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_mask_u; + +/* Define the union csr_rba_intecc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ram_ecc_int_status : 2; /* [1:0] */ + u32 rsv_55 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_status_u; + +/* Define the union csr_rba_intecc_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ram_ecc_int_ro : 2; /* [1:0] */ + u32 rsv_56 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_engine_reg_rba_intecc_ro_u; + +/* Define the union csr_int_vector_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector : 11; /* [10:0] */ + u32 rsv_0 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_vector_num_u; + +/* Define the union csr_int_cfg_acs_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_func_sel : 10; /* [9:0] */ + u32 rsv_1 : 6; /* [15:10] */ + u32 cfg_pf_vf_sel : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_cfg_acs_ctrl_u; + +/* Define the union csr_msix_coal_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aggre_thr : 8; /* [7:0] */ + u32 aggre_time : 8; /* [15:8] */ + u32 timeout_cnt : 8; /* [23:16] */ + u32 round : 1; /* [24] */ + u32 coal_en : 1; /* [25] */ + u32 rsv_3 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_coal_ctrl_u; + +/* Define the union csr_msix_coal_event_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending_event_cnt : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_coal_event_u; + +/* Define the union csr_msix_msg_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_addr_low_2bit : 2; /* [1:0] */ + u32 msg_addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_msg_addr_u; + +/* Define the union csr_msix_msg_up_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_up_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_msg_up_addr_u; + +/* Define the union csr_msix_msg_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_msg_data_u; + +/* Define the union csr_msix_vector_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mask : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_vector_ctrl_u; + +/* Define the union csr_msix_tbl_func_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_pf_num : 5; /* [4:0] */ + u32 rsv_6 : 11; /* [15:5] */ + u32 msix_tbl_vf_num : 8; /* [23:16] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_tbl_func_num_u; + +/* Define the union csr_msix_tbl_int_src_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_int_src_idx : 2; /* [1:0] */ + u32 rsv_8 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_tbl_int_src_idx_u; + +/* Define the union csr_msix_pending_bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_pending_bit_u; + +/* Define the union csr_int_sram_init_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_msix_tbl : 1; /* [0] */ + u32 init_msix_coal_tbl : 1; /* [1] */ + u32 init_msix_ptr_tbl : 1; /* [2] */ + u32 init_msi_coal_tbl : 1; /* [3] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_sram_init_ctrl_u; + +/* Define the union csr_init_ptr_tbl_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pt_ptr : 16; /* [15:0] */ + u32 pt_pf_num : 5; /* [20:16] */ + u32 pt_tbl_size : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_init_ptr_tbl_data_u; + +/* Define the union csr_msi_coal_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aggre_thr : 8; /* [7:0] */ + u32 aggre_time : 8; /* [15:8] */ + u32 timeout_cnt : 8; /* [23:16] */ + u32 round : 1; /* [24] */ + u32 coal_en : 1; /* [25] */ + u32 rsv_11 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msi_coal_ctrl_u; + +/* Define the union csr_msi_coal_event_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending_event_cnt : 8; /* [7:0] */ + u32 rsv_12 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msi_coal_event_u; + +/* Define the union csr_int_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_req_set : 1; /* [0] */ + u32 int_req_vector : 11; /* [11:1] */ + u32 int_req_deassert : 1; /* [12] */ + u32 rsv_13 : 3; /* [15:13] */ + u32 int_req_vf_num : 8; /* [23:16] */ + u32 rsv_14 : 2; /* [25:24] */ + u32 int_req_pf_num : 5; /* [30:26] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_req_ctrl_u; + +/* Define the union csr_ras_int_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_int_level : 1; /* [0] */ + u32 ecc_2bit_int_level : 1; /* [1] */ + u32 src0_func_vec_err_int_level : 1; /* [2] */ + u32 src1_func_vec_err_int_level : 1; /* [3] */ + u32 src2_func_vec_err_int_level : 1; /* [4] */ + u32 src3_func_vec_err_int_level : 1; /* [5] */ + u32 rsv_16 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ras_int_level_u; + +/* Define the union csr_int_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data_sel : 1; /* [0] */ + u32 pending_event_clr : 1; /* [1] */ + u32 rsv_17 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_ctrl_u; + +/* Define the union csr_allocate_buf_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pre_req_buff_size : 3; /* [2:0] */ + u32 rsv_18 : 13; /* [15:3] */ + u32 buff_rls_timer_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_allocate_buf_ctrl_u; + +/* Define the union csr_int_tlp_field_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_field_bypass_ctrl : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_tlp_field_ctrl_u; + +/* Define the union csr_int_tlp_field_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_ns : 1; /* [0] */ + u32 int_ro : 1; /* [1] */ + u32 int_idbo : 1; /* [2] */ + u32 int_th : 1; /* [3] */ + u32 int_st : 8; /* [11:4] */ + u32 int_ph : 2; /* [13:12] */ + u32 rsv_20 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_tlp_field_set_u; + +/* Define the union csr_local_ce_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_ce : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 msix_coal_tbl_ecc_err_1bit_ce : 1; /* [2] */ + u32 rsv_22 : 1; /* [3] */ + u32 ptr_tbl_ecc_err_1bit_ce : 1; /* [4] */ + u32 rsv_23 : 1; /* [5] */ + u32 msi_coal_tbl_ecc_err_1bit_ce : 1; /* [6] */ + u32 rsv_24 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_local_ce_int_u; + +/* Define the union csr_local_nfe_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_nfe : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_nfe : 1; /* [1] */ + u32 msix_coal_tbl_ecc_err_1bit_nfe : 1; /* [2] */ + u32 msix_coal_tbl_ecc_err_2bit_nfe : 1; /* [3] */ + u32 ptr_tbl_ecc_err_1bit_nfe : 1; /* [4] */ + u32 ptr_tbl_ecc_err_2bit_nfe : 1; /* [5] */ + u32 msi_coal_tbl_ecc_err_1bit_nfe : 1; /* [6] */ + u32 msi_coal_tbl_ecc_err_2bit_nfe : 1; /* [7] */ + u32 rsv_25 : 8; /* [15:8] */ + u32 src0_func_vec_err_nfe : 1; /* [16] */ + u32 src1_func_vec_err_nfe : 1; /* [17] */ + u32 src2_func_vec_err_nfe : 1; /* [18] */ + u32 src3_func_vec_err_nfe : 1; /* [19] */ + u32 rsv_26 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_local_nfe_int_u; + +/* Define the union csr_local_fe_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_27 : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_fe : 1; /* [1] */ + u32 rsv_28 : 1; /* [2] */ + u32 msix_coal_tbl_ecc_err_2bit_fe : 1; /* [3] */ + u32 rsv_29 : 1; /* [4] */ + u32 ptr_tbl_ecc_err_2bit_fe : 1; /* [5] */ + u32 rsv_30 : 1; /* [6] */ + u32 msi_coal_tbl_ecc_err_2bit_fe : 1; /* [7] */ + u32 rsv_31 : 8; /* [15:8] */ + u32 src0_func_vec_err_fe : 1; /* [16] */ + u32 src1_func_vec_err_fe : 1; /* [17] */ + u32 src2_func_vec_err_fe : 1; /* [18] */ + u32 src3_func_vec_err_fe : 1; /* [19] */ + u32 rsv_32 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_local_fe_int_u; + +/* Define the union csr_abnormal_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_func_vec_err_sts : 1; /* [0] */ + u32 int_src1_func_vec_err_sts : 1; /* [1] */ + u32 int_src2_func_vec_err_sts : 1; /* [2] */ + u32 int_src3_func_vec_err_sts : 1; /* [3] */ + u32 rsv_33 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_abnormal_int_sts_u; + +/* Define the union csr_abnormal_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_func_vec_err_mask : 1; /* [0] */ + u32 int_src1_func_vec_err_mask : 1; /* [1] */ + u32 int_src2_func_vec_err_mask : 1; /* [2] */ + u32 int_src3_func_vec_err_mask : 1; /* [3] */ + u32 rsv_34 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_abnormal_int_mask_u; + +/* Define the union csr_abnormal_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_func_vec_err_set : 1; /* [0] */ + u32 int_src1_func_vec_err_set : 1; /* [1] */ + u32 int_src2_func_vec_err_set : 1; /* [2] */ + u32 int_src3_func_vec_err_set : 1; /* [3] */ + u32 rsv_35 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_abnormal_int_set_u; + +/* Define the union csr_abnormal_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_func_vec_err_ro : 1; /* [0] */ + u32 int_src1_func_vec_err_ro : 1; /* [1] */ + u32 int_src2_func_vec_err_ro : 1; /* [2] */ + u32 int_src3_func_vec_err_ro : 1; /* [3] */ + u32 rsv_36 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_abnormal_int_ro_u; + +/* Define the union csr_int_src0_err_func_vec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_err_pf_num : 5; /* [4:0] */ + u32 rsv_37 : 1; /* [5] */ + u32 int_src0_err_vf_num : 8; /* [13:6] */ + u32 rsv_38 : 4; /* [17:14] */ + u32 int_src0_err_port : 1; /* [18] */ + u32 int_src0_err_vector : 11; /* [29:19] */ + u32 rsv_39 : 1; /* [30] */ + u32 int_src0_int_null : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_src0_err_func_vec_u; + +/* Define the union csr_int_src1_err_func_vec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src1_err_pf_num : 5; /* [4:0] */ + u32 rsv_40 : 1; /* [5] */ + u32 int_src1_err_vf_num : 8; /* [13:6] */ + u32 rsv_41 : 4; /* [17:14] */ + u32 int_src1_err_port : 1; /* [18] */ + u32 int_src1_err_vector : 11; /* [29:19] */ + u32 rsv_42 : 1; /* [30] */ + u32 int_src1_int_null : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_src1_err_func_vec_u; + +/* Define the union csr_int_src2_err_func_vec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src2_err_pf_num : 5; /* [4:0] */ + u32 rsv_43 : 1; /* [5] */ + u32 int_src2_err_vf_num : 8; /* [13:6] */ + u32 rsv_44 : 4; /* [17:14] */ + u32 int_src2_err_port : 1; /* [18] */ + u32 int_src2_err_vector : 11; /* [29:19] */ + u32 rsv_45 : 1; /* [30] */ + u32 int_src2_int_null : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_src2_err_func_vec_u; + +/* Define the union csr_int_src3_err_func_vec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src3_err_pf_num : 5; /* [4:0] */ + u32 rsv_46 : 1; /* [5] */ + u32 int_src3_err_vf_num : 8; /* [13:6] */ + u32 rsv_47 : 4; /* [17:14] */ + u32 int_src3_err_port : 1; /* [18] */ + u32 int_src3_err_vector : 11; /* [29:19] */ + u32 rsv_48 : 1; /* [30] */ + u32 int_src3_int_null : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_int_src3_err_func_vec_u; + +/* Define the union csr_ecc_err_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 set_msix_tbl_ecc_1bit : 1; /* [0] */ + u32 set_msix_tbl_ecc_2bit : 1; /* [1] */ + u32 set_msix_coal_tbl_ecc_1bit : 1; /* [2] */ + u32 set_msix_coal_tbl_ecc_2bit : 1; /* [3] */ + u32 set_ptr_tbl_ecc_1bit : 1; /* [4] */ + u32 set_ptr_tbl_ecc_2bit : 1; /* [5] */ + u32 set_msi_coal_tbl_ecc_1bit : 1; /* [6] */ + u32 set_msi_coal_tbl_ecc_2bit : 1; /* [7] */ + u32 rsv_49 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ecc_err_set_u; + +/* Define the union csr_ecc_err_int_src_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit : 1; /* [1] */ + u32 msix_coal_tbl_ecc_err_1bit : 1; /* [2] */ + u32 msix_coal_tbl_ecc_err_2bit : 1; /* [3] */ + u32 ptr_tbl_ecc_err_1bit : 1; /* [4] */ + u32 ptr_tbl_ecc_err_2bit : 1; /* [5] */ + u32 msi_coal_tbl_ecc_err_1bit : 1; /* [6] */ + u32 msi_coal_tbl_ecc_err_2bit : 1; /* [7] */ + u32 rsv_50 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ecc_err_int_src_sts_u; + +/* Define the union csr_ecc_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_mask : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_mask : 1; /* [1] */ + u32 msix_coal_tbl_ecc_err_1bit_mask : 1; /* [2] */ + u32 msix_coal_tbl_ecc_err_2bit_mask : 1; /* [3] */ + u32 ptr_tbl_ecc_err_1bit_mask : 1; /* [4] */ + u32 ptr_tbl_ecc_err_2bit_mask : 1; /* [5] */ + u32 msi_coal_tbl_ecc_err_1bit_mask : 1; /* [6] */ + u32 msi_coal_tbl_ecc_err_2bit_mask : 1; /* [7] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ecc_err_mask_u; + +/* Define the union csr_ecc_err_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_sts : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_sts : 1; /* [1] */ + u32 msix_coal_tbl_ecc_err_1bit_sts : 1; /* [2] */ + u32 msix_coal_tbl_ecc_err_2bit_sts : 1; /* [3] */ + u32 ptr_tbl_ecc_err_1bit_sts : 1; /* [4] */ + u32 ptr_tbl_ecc_err_2bit_sts : 1; /* [5] */ + u32 msi_coal_tbl_ecc_err_1bit_sts : 1; /* [6] */ + u32 msi_coal_tbl_ecc_err_2bit_sts : 1; /* [7] */ + u32 rsv_52 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ecc_err_int_sts_u; + +/* Define the union csr_ecc_err_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_inject : 2; /* [1:0] */ + u32 msix_coal_tbl_ecc_err_inject : 2; /* [3:2] */ + u32 ptr_tbl_ecc_err_inject : 2; /* [5:4] */ + u32 msi_coal_tbl_ecc_err_inject : 2; /* [7:6] */ + u32 rsv_53 : 8; /* [15:8] */ + u32 msix_tbl_ecc_err_inject_mode : 1; /* [16] */ + u32 msix_coal_tbl_ecc_err_inject_mode : 1; /* [17] */ + u32 ptr_tbl_ecc_err_inject_mode : 1; /* [18] */ + u32 msi_coal_tbl_ecc_err_inject_mode : 1; /* [19] */ + u32 rsv_54 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ecc_err_inject_u; + +/* Define the union csr_msix_tbl_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_55 : 6; /* [15:10] */ + u32 msix_tbl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_56 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_tbl_ecc_err_addr_u; + +/* Define the union csr_msix_coal_tbl_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_coal_tbl_ecc_1biterr_addr : 10; /* [9:0] */ + u32 rsv_57 : 6; /* [15:10] */ + u32 msix_coal_tbl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_58 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msix_coal_tbl_ecc_err_addr_u; + +/* Define the union csr_ptr_tbl_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptr_tbl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_59 : 6; /* [15:10] */ + u32 ptr_tbl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_60 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_ptr_tbl_ecc_err_addr_u; + +/* Define the union csr_msi_coal_tbl_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_coal_tbl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_61 : 6; /* [15:10] */ + u32 msi_coal_tbl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_62 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_msi_coal_tbl_ecc_err_addr_u; + +/* Define the union csr_dfx_tlp_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_cnt_mode : 1; /* [0] */ + u32 tlp_cnt_pf_num : 5; /* [5:1] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 tlp_cnt_vf_num : 8; /* [23:16] */ + u32 rsv_64 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_tlp_cnt_cfg_u; + +/* Define the union csr_dfx_host_np_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_np_mem_pkt_cnt : 16; /* [15:0] */ + u32 rx_np_cfg_pkt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_host_np_cnt_u; + +/* Define the union csr_dfx_host_p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_p_pkt_cnt : 16; /* [15:0] */ + u32 rsv_65 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_host_p_cnt_u; + +/* Define the union csr_dfx_int_output_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_output_cnt : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_output_cnt_u; + +/* Define the union csr_dfx_int_src0_input_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_input_cnt : 16; /* [15:0] */ + u32 int_src0_deassert_input_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src0_input_cnt_u; + +/* Define the union csr_dfx_int_src0_output_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_output_cnt : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src0_output_cnt_u; + +/* Define the union csr_dfx_int_src1_input_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src1_input_cnt : 16; /* [15:0] */ + u32 int_src1_deassert_input_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src1_input_cnt_u; + +/* Define the union csr_dfx_int_src1_output_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src1_output_cnt : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src1_output_cnt_u; + +/* Define the union csr_dfx_int_src2_input_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src2_input_cnt : 16; /* [15:0] */ + u32 int_src2_deassert_input_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src2_input_cnt_u; + +/* Define the union csr_dfx_int_src2_output_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src2_output_cnt : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src2_output_cnt_u; + +/* Define the union csr_dfx_int_src3_input_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src3_input_cnt : 16; /* [15:0] */ + u32 int_src3_deassert_input_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src3_input_cnt_u; + +/* Define the union csr_dfx_int_src3_output_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src3_output_cnt : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_src3_output_cnt_u; + +/* Define the union csr_dfx_err_func_vec_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src0_err_func_vec_cnt : 16; /* [15:0] */ + u32 int_src1_err_func_vec_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_err_func_vec_cnt0_u; + +/* Define the union csr_dfx_err_func_vec_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src2_err_func_vec_cnt : 16; /* [15:0] */ + u32 int_src3_err_func_vec_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_err_func_vec_cnt1_u; + +/* Define the union csr_dfx_ecc_err_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_1bit_cnt : 4; /* [3:0] */ + u32 msix_tbl_ecc_2bit_cnt : 4; /* [7:4] */ + u32 msix_coal_tbl_ecc_1bit_cnt : 4; /* [11:8] */ + u32 msix_coal_tbl_ecc_2bit_cnt : 4; /* [15:12] */ + u32 ptr_tbl_ecc_1bit_cnt : 4; /* [19:16] */ + u32 ptr_tbl_ecc_2bit_cnt : 4; /* [23:20] */ + u32 msi_coal_tbl_ecc_1bit_cnt : 4; /* [27:24] */ + u32 msi_coal_tbl_ecc_2bit_cnt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_ecc_err_cnt0_u; + +/* Define the union csr_dfx_int_sram_init_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_init_done : 1; /* [0] */ + u32 msix_coal_tbl_init_done : 1; /* [1] */ + u32 ptr_tbl_init_done : 1; /* [2] */ + u32 msi_coal_tbl_init_done : 1; /* [3] */ + u32 rsv_71 : 27; /* [30:4] */ + u32 ptr_tbl_init_sel : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_int_sram_init_status_u; + +/* Define the union csr_dfx_fsm_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_coal_fsm_st : 3; /* [2:0] */ + u32 rsv_72 : 2; /* [4:3] */ + u32 curr_new_int_st : 2; /* [6:5] */ + u32 rsv_73 : 2; /* [8:7] */ + u32 curr_regif_st : 4; /* [12:9] */ + u32 rsv_74 : 2; /* [14:13] */ + u32 curr_flr_st : 4; /* [18:15] */ + u32 rsv_75 : 1; /* [19] */ + u32 curr_func_mask_st : 2; /* [21:20] */ + u32 rsv_76 : 1; /* [22] */ + u32 msi_coal_fsm_st : 3; /* [25:23] */ + u32 rsv_77 : 2; /* [27:26] */ + u32 tx_buf_ctrl_fsm_st : 3; /* [30:28] */ + u32 rsv_78 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_fsm_status0_u; + +/* Define the union csr_dfx_intx_wire_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intx_wire_status : 4; /* [3:0] */ + u32 rsv_79 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_intx_wire_status_u; + +/* Define the union csr_dfx_port_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle : 1; /* [0] */ + u32 rsv_80 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_port_status_u; + +/* Define the union csr_dfx_buf_remain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_remain_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_buf_remain_cnt_u; + +/* Define the union csr_dfx_capt_reg_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_capt_reg_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_capt_reg_addr_u; + +/* Define the union csr_dfx_capt_reg_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_capt_reg_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_capt_reg_data_u; + +/* Define the union csr_dfx_sdi_eco_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sdi_eco_register : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_int_reg_dfx_sdi_eco_register_u; + +/* Define the union csr_dma_ecc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_inject : 1; /* [0] */ + u32 ecc_2bit_inject : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ecc_u; + +/* Define the union csr_dma_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 16; /* [15:0] */ + u32 ecc_2bit_err_addr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ecc_err_addr_u; + +/* Define the union csr_dma_ecc_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_cnt : 16; /* [15:0] */ + u32 ecc_2bit_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ecc_ecc_cnt_u; + +/* Define the union csr_dma_eco_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_eco_reg : 8; /* [7:0] */ + u32 rsv_1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_eco_u; + +/* Define the union csr_dma_ep_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_int_set : 1; /* [0] */ + u32 ecc_2bit_err_int_set : 1; /* [1] */ + u32 rsv_2 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ep_int_set_u; + +/* Define the union csr_dma_ep_int_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_int_msk : 1; /* [0] */ + u32 ecc_2bit_err_int_msk : 1; /* [1] */ + u32 rsv_3 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ep_int_msk_u; + +/* Define the union csr_dma_ep_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_int : 1; /* [0] */ + u32 ecc_2bit_err_int : 1; /* [1] */ + u32 rsv_4 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ep_int_u; + +/* Define the union csr_dma_ep_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_st : 1; /* [0] */ + u32 ecc_2bit_err_st : 1; /* [1] */ + u32 rsv_5 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ep_int_sts_u; + +/* Define the union csr_common_and_ch_err_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cm_err_sts : 1; /* [0] */ + u32 dma_queue_err_sts : 1; /* [1] */ + u32 rsv_6 : 14; /* [15:2] */ + u32 dma_sram_init_done : 1; /* [16] */ + u32 rsv_7 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_common_and_ch_err_sts_u; + +/* Define the union csr_dma_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_err_mask : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_err_mask_u; + +/* Define the union csr_dma_atomic_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_ctrl : 1; /* [0] */ + u32 rsv_9 : 7; /* [7:1] */ + u32 atomic_port_num : 4; /* [11:8] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_ctrl_u; + +/* Define the union csr_dma_atomic_header_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_header_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_header_0_u; + +/* Define the union csr_dma_atomic_header_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_header_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_header_1_u; + +/* Define the union csr_dma_atomic_header_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_header_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_header_2_u; + +/* Define the union csr_dma_atomic_header_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_header_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_header_3_u; + +/* Define the union csr_dma_atomic_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_0_u; + +/* Define the union csr_dma_atomic_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_1_u; + +/* Define the union csr_dma_atomic_data_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_2_u; + +/* Define the union csr_dma_atomic_data_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_3_u; + +/* Define the union csr_dma_atomic_data_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_4_u; + +/* Define the union csr_dma_atomic_data_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_5_u; + +/* Define the union csr_dma_atomic_data_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_6_u; + +/* Define the union csr_dma_atomic_data_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_data_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_data_7_u; + +/* Define the union csr_dma_atomic_resp_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_0_u; + +/* Define the union csr_dma_atomic_resp_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_1_u; + +/* Define the union csr_dma_atomic_resp_data_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_2_u; + +/* Define the union csr_dma_atomic_resp_data_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_3_u; + +/* Define the union csr_dma_atomic_resp_data_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_4_u; + +/* Define the union csr_dma_atomic_resp_data_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_5_u; + +/* Define the union csr_dma_atomic_resp_data_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_6_u; + +/* Define the union csr_dma_atomic_resp_data_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_7_u; + +/* Define the union csr_dma_atomic_resp_data_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_resp_data_vld : 1; /* [0] */ + u32 rsv_11 : 1; /* [1] */ + u32 atomic_resp_data_err : 1; /* [2] */ + u32 rsv_12 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_resp_data_st_u; + +/* Define the union csr_dma_atomic_prefix_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_pasid : 20; /* [19:0] */ + u32 atomic_prfx_er : 1; /* [20] */ + u32 atomic_prfx_pmr : 1; /* [21] */ + u32 atomic_prfx_dwen : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_prefix_inf_u; + +/* Define the union csr_dma_atomic_pf_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic_vf : 8; /* [7:0] */ + u32 atomic_pf : 5; /* [12:8] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_atomic_pf_vf_u; + +/* Define the union csr_dma_port_idle_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_sts_idle : 1; /* [0] */ + u32 port1_sts_idle : 1; /* [1] */ + u32 port2_sts_idle : 1; /* [2] */ + u32 port3_sts_idle : 1; /* [3] */ + u32 port4_sts_idle : 1; /* [4] */ + u32 port5_sts_idle : 1; /* [5] */ + u32 port6_sts_idle : 1; /* [6] */ + u32 port7_sts_idle : 1; /* [7] */ + u32 port8_sts_idle : 1; /* [8] */ + u32 port9_sts_idle : 1; /* [9] */ + u32 port10_sts_idle : 1; /* [10] */ + u32 port11_sts_idle : 1; /* [11] */ + u32 port12_sts_idle : 1; /* [12] */ + u32 port13_sts_idle : 1; /* [13] */ + u32 port14_sts_idle : 1; /* [14] */ + u32 port15_sts_idle : 1; /* [15] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_port_idle_sts_u; + +/* Define the union csr_dma_global_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clk_frequency : 12; /* [11:0] */ + u32 mps_in_rc_mode : 3; /* [14:12] */ + u32 rsv_16 : 2; /* [16:15] */ + u32 mrrs_in_rc_mode : 3; /* [19:17] */ + u32 mps_in_loc_usr : 3; /* [22:20] */ + u32 rsv_17 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_global_ctrl_u; + +/* Define the union csr_dma_ch_ras_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 1; /* [0] */ + u32 dma_queue_sts_err00_level : 1; /* [1] */ + u32 dma_queue_sts_err01_level : 1; /* [2] */ + u32 dma_queue_sts_err02_level : 1; /* [3] */ + u32 dma_queue_sts_err03_level : 1; /* [4] */ + u32 rsv_19 : 1; /* [5] */ + u32 dma_queue_sts_err05_level : 1; /* [6] */ + u32 dma_queue_sts_err06_level : 1; /* [7] */ + u32 dma_queue_sts_err07_level : 1; /* [8] */ + u32 dma_queue_sts_err08_level : 1; /* [9] */ + u32 dma_queue_sts_err09_level : 1; /* [10] */ + u32 dma_queue_sts_err10_level : 1; /* [11] */ + u32 dma_queue_sts_err11_level : 1; /* [12] */ + u32 dma_queue_sts_err12_level : 1; /* [13] */ + u32 dma_queue_sts_err13_level : 1; /* [14] */ + u32 dma_queue_sts_err14_level : 1; /* [15] */ + u32 dma_queue_sts_err15_level : 1; /* [16] */ + u32 dma_queue_sts_err16_level : 1; /* [17] */ + u32 dma_queue_sts_err17_level : 1; /* [18] */ + u32 rsv_20 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ch_ras_level_u; + +/* Define the union csr_dma_cm_ras_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_st_level : 1; /* [0] */ + u32 ecc_2bit_err_st_level : 1; /* [1] */ + u32 rsv_21 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_cm_ras_level_u; + +/* Define the union csr_dma_int_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_mode_sel_normal : 1; /* [0] */ + u32 int_mode_sel_abnormal : 1; /* [1] */ + u32 rsv_22 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_int_mode_sel_u; + +/* Define the union csr_dma_cm_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_st_ce : 1; /* [0] */ + u32 rsv_23 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_cm_ce_ro_u; + +/* Define the union csr_dma_cm_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_st_nfe : 1; /* [0] */ + u32 ecc_2bit_err_st_nfe : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_cm_nfe_ro_u; + +/* Define the union csr_dma_cm_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_25 : 1; /* [0] */ + u32 ecc_2bit_err_st_fe : 1; /* [1] */ + u32 rsv_26 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_cm_fe_ro_u; + +/* Define the union csr_dma_ch_vf_reg_quat_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_reg_quat_en : 1; /* [0] */ + u32 dma_ep_reg_quat_en : 2; /* [2:1] */ + u32 dma_pf_vf_quat_en : 1; /* [3] */ + u32 rsv_27 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ch_vf_reg_quat_en_u; + +/* Define the union csr_dma_ch_done_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_chanel_done_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ch_done_sts_u; + +/* Define the union csr_dma_ch_err_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_chanel_error_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ch_err_sts_u; + +/* Define the union csr_dma_ep_reset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ep_reset : 1; /* [0] */ + u32 rsv_28 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ep_reset_u; + +/* Define the union csr_dma_sq_prefetch_buf_rel_to_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_sq_prefetch_buf_release_time_out_thr : 3; /* [2:0] */ + u32 rsv_29 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_sq_prefetch_buf_rel_to_u; + +/* Define the union csr_dma_port_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_tlp_p_st_cfg : 8; /* [7:0] */ + u32 local_tlp_p_ph_cfg : 2; /* [9:8] */ + u32 rsv_30 : 6; /* [15:10] */ + u32 link_down_mask : 1; /* [16] */ + u32 rsv_31 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_port_cfg0_u; + +/* Define the union csr_dma_port_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_32 : 1; /* [0] */ + u32 dma_queue_sts_err00_ce : 1; /* [1] */ + u32 dma_queue_sts_err01_ce : 1; /* [2] */ + u32 dma_queue_sts_err02_ce : 1; /* [3] */ + u32 dma_queue_sts_err03_ce : 1; /* [4] */ + u32 rsv_33 : 6; /* [10:5] */ + u32 dma_queue_sts_err10_ce : 1; /* [11] */ + u32 rsv_34 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_port_ce_ro_u; + +/* Define the union csr_dma_port_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_35 : 1; /* [0] */ + u32 dma_queue_sts_err00_nfe : 1; /* [1] */ + u32 dma_queue_sts_err01_nfe : 1; /* [2] */ + u32 dma_queue_sts_err02_nfe : 1; /* [3] */ + u32 dma_queue_sts_err03_nfe : 1; /* [4] */ + u32 rsv_36 : 1; /* [5] */ + u32 dma_queue_sts_err05_nfe : 1; /* [6] */ + u32 dma_queue_sts_err06_nfe : 1; /* [7] */ + u32 dma_queue_sts_err07_nfe : 1; /* [8] */ + u32 dma_queue_sts_err08_nfe : 1; /* [9] */ + u32 dma_queue_sts_err09_nfe : 1; /* [10] */ + u32 dma_queue_sts_err10_nfe : 1; /* [11] */ + u32 dma_queue_sts_err11_nfe : 1; /* [12] */ + u32 dma_queue_sts_err12_nfe : 1; /* [13] */ + u32 dma_queue_sts_err13_nfe : 1; /* [14] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_port_nfe_ro_u; + +/* Define the union csr_dma_port_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_38 : 5; /* [4:0] */ + u32 rsv_39 : 1; /* [5] */ + u32 dma_queue_sts_err05_fe : 1; /* [6] */ + u32 dma_queue_sts_err06_fe : 1; /* [7] */ + u32 dma_queue_sts_err07_fe : 1; /* [8] */ + u32 dma_queue_sts_err08_fe : 1; /* [9] */ + u32 dma_queue_sts_err09_fe : 1; /* [10] */ + u32 rsv_40 : 1; /* [11] */ + u32 dma_queue_sts_err11_fe : 1; /* [12] */ + u32 dma_queue_sts_err12_fe : 1; /* [13] */ + u32 dma_queue_sts_err13_fe : 1; /* [14] */ + u32 rsv_41 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_port_fe_ro_u; + +/* Define the union csr_dma_flr_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_flr_disable : 1; /* [0] */ + u32 rsv_42 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_flr_disable_u; + +/* Define the union csr_dma_rp_port_req_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_rp_port_req_id_cfg : 16; /* [15:0] */ + u32 dma_rp_port_req_id_sel : 1; /* [16] */ + u32 rsv_43 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_rp_port_req_id_cfg_u; + +/* Define the union csr_dma_ep_port_req_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ep_port_req_id_cfg : 16; /* [15:0] */ + u32 dma_ep_port_req_id_sel : 1; /* [16] */ + u32 rsv_44 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_ep_port_req_id_cfg_u; + +/* Define the union csr_dfx_local_np_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_np_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_np_id_sts_u; + +/* Define the union csr_dfx_local_p_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_p_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_p_id_sts_u; + +/* Define the union csr_dfx_remote_np_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_np_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_np_id_sts_u; + +/* Define the union csr_dfx_remote_p_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_p_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_p_id_sts_u; + +/* Define the union csr_dfx_sq_np_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_np_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_sq_np_id_sts_u; + +/* Define the union csr_dfx_pa_req_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_addr_request_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_pa_req_id_sts_u; + +/* Define the union csr_dfx_buf_allocate_id_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buffer_allocate_tag_id_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_allocate_id_sts_u; + +/* Define the union csr_dfx_cmtb_entry_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_table_entry_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_cmtb_entry_sts_u; + +/* Define the union csr_dfx_prebuf_entry_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prebuffer_entry_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_prebuf_entry_sts_u; + +/* Define the union csr_dfx_inf_back_press_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pa_lkp_req_bkpr : 1; /* [0] */ + u32 pa_resp_bkpr : 1; /* [1] */ + u32 pa_release_bkpr : 1; /* [2] */ + u32 loc_sq_cpl_last_bkpr : 1; /* [3] */ + u32 loc_sq_cpl_bkpr : 1; /* [4] */ + u32 loc_np_head_bkpr : 1; /* [5] */ + u32 loc_cpl_head_bkpr : 1; /* [6] */ + u32 loc_cpl_data_bkpr : 1; /* [7] */ + u32 loc_cpl_ext_data_bkpr : 1; /* [8] */ + u32 loc_cpl_last_bkpr : 1; /* [9] */ + u32 loc_p_head_bkpr : 1; /* [10] */ + u32 loc_p_head_ack_bkpr : 1; /* [11] */ + u32 loc_p_data_req_bkpr : 1; /* [12] */ + u32 loc_p_data_ack_bkpr : 1; /* [13] */ + u32 loc_sq_head_bkpr : 1; /* [14] */ + u32 rsv_45 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_inf_back_press_sts0_u; + +/* Define the union csr_dfx_inf_back_press_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 allocate_req_bkpr : 1; /* [0] */ + u32 allocate_result_bkpr : 1; /* [1] */ + u32 allocate_release_bkpr : 1; /* [2] */ + u32 remote_np_head_bkpr : 1; /* [3] */ + u32 remote_np_data_bkpr : 1; /* [4] */ + u32 remote_np_last_bkpr : 1; /* [5] */ + u32 remote_sq_cpl_hed_bkpr : 1; /* [6] */ + u32 remote_sq_cpl_dat_bkpr : 1; /* [7] */ + u32 remote_sq_cpl_end_bkpr : 1; /* [8] */ + u32 remote_cpl_head_bkpr : 1; /* [9] */ + u32 remote_cpl_ack_bkpr : 1; /* [10] */ + u32 remote_cpl_data_bkpr : 1; /* [11] */ + u32 remote_p_head_bkpr : 1; /* [12] */ + u32 remote_p_ack_bkpr : 1; /* [13] */ + u32 remote_p_data_bkpr : 1; /* [14] */ + u32 remote_p_ext_data_bkpr : 1; /* [15] */ + u32 remote_p_last_bkpr : 1; /* [16] */ + u32 remote_msi_interrupt_bkpr : 1; /* [17] */ + u32 rsv_46 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_inf_back_press_sts1_u; + +/* Define the union csr_dfx_inf_back_press_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 private_ch0_sq_bkpr : 1; /* [0] */ + u32 private_ch0_cq_bkpr : 1; /* [1] */ + u32 private_ch1_sq_bkpr : 1; /* [2] */ + u32 private_ch1_cq_bkpr : 1; /* [3] */ + u32 rsv_47 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_inf_back_press_sts2_u; + +/* Define the union csr_dfx_dma_wrr_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_wrr_disable : 1; /* [0] */ + u32 rsv_48 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_dma_wrr_disable_u; + +/* Define the union csr_dfx_pa_req_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pa_req_cnt : 8; /* [7:0] */ + u32 rsv_49 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_pa_req_tlp_num_u; + +/* Define the union csr_dfx_pa_back_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pa_back_cnt : 8; /* [7:0] */ + u32 rsv_50 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_pa_back_tlp_num_u; + +/* Define the union csr_dfx_pa_release_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pa_release_cnt : 8; /* [7:0] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_pa_release_tlp_num_u; + +/* Define the union csr_dfx_local_np_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_np_cnt : 8; /* [7:0] */ + u32 rsv_52 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_np_tlp_num_u; + +/* Define the union csr_dfx_local_cpl_head_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_cpl_head_cnt : 8; /* [7:0] */ + u32 rsv_53 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_cpl_head_tlp_num_u; + +/* Define the union csr_dfx_local_cpl_data_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_cpl_data_cnt : 8; /* [7:0] */ + u32 rsv_54 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_cpl_data_tlp_num_u; + +/* Define the union csr_dfx_local_cpl_ext_data_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_55 : 8; /* [7:0] */ + u32 rsv_56 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_cpl_ext_data_tlp_num_u; + +/* Define the union csr_dfx_local_p_head_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_p_head_cnt : 8; /* [7:0] */ + u32 rsv_57 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_p_head_tlp_num_u; + +/* Define the union csr_dfx_local_p_data_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_p_data_cnt : 8; /* [7:0] */ + u32 rsv_58 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_local_p_data_tlp_num_u; + +/* Define the union csr_dfx_buf_aloc_port_req_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_aloc_port_req_cnt : 8; /* [7:0] */ + u32 rsv_59 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_aloc_port_req_num_u; + +/* Define the union csr_dfx_buf_aloc_port_result_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_aloc_port_result_cnt : 8; /* [7:0] */ + u32 rsv_60 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_aloc_port_result_num_u; + +/* Define the union csr_dfx_buf_aloc_port_release_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_61 : 8; /* [7:0] */ + u32 rsv_62 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_aloc_port_release_num_u; + +/* Define the union csr_dfx_buf_aloc_size_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_aloc_data_size_cnt : 8; /* [7:0] */ + u32 buf_aloc_head_size_cnt : 8; /* [15:8] */ + u32 rsv_63 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_aloc_size_num_u; + +/* Define the union csr_dfx_buf_np_release_size_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_np_data_release_size_cnt : 8; /* [7:0] */ + u32 buf_np_head_release_size_cnt : 8; /* [15:8] */ + u32 rsv_64 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_np_release_size_num_u; + +/* Define the union csr_dfx_buf_p_release_size_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 buf_p_data_release_size_cnt : 8; /* [7:0] */ + u32 buf_p_head_release_size_cnt : 8; /* [15:8] */ + u32 rsv_65 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_p_release_size_num_u; + +/* Define the union csr_dfx_buf_port_release_size_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 8; /* [7:0] */ + u32 rsv_67 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_buf_port_release_size_num_u; + +/* Define the union csr_dfx_remote_np_head_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_np_head_tlp_cnt : 8; /* [7:0] */ + u32 rsv_68 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_np_head_tlp_num_u; + +/* Define the union csr_dfx_remote_np_data_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_np_data_tlp_cnt : 8; /* [7:0] */ + u32 rsv_69 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_np_data_tlp_num_u; + +/* Define the union csr_dfx_remote_cpl_head_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_cpl_head_cnt : 8; /* [7:0] */ + u32 rsv_70 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_cpl_head_num_u; + +/* Define the union csr_dfx_remote_cpl_data_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_71 : 8; /* [7:0] */ + u32 rsv_72 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_cpl_data_num_u; + +/* Define the union csr_dfx_remote_p_head_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_p_head_cnt : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_p_head_num_u; + +/* Define the union csr_dfx_remote_p_data_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_p_data_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_p_data_num_u; + +/* Define the union csr_dfx_remote_p_ext_data_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_75 : 8; /* [7:0] */ + u32 rsv_76 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_remote_p_ext_data_num_u; + +/* Define the union csr_dfx_sq_np_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_np_cnt : 8; /* [7:0] */ + u32 rsv_77 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_sq_np_num_u; + +/* Define the union csr_dfx_sq_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_cpl_cnt : 8; /* [7:0] */ + u32 rsv_78 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_sq_cpl_num_u; + +/* Define the union csr_dfx_cq_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 8; /* [7:0] */ + u32 rsv_80 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_cq_p_num_u; + +/* Define the union csr_dfx_link_down_event_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_down_event_cnt : 8; /* [7:0] */ + u32 rsv_81 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_link_down_event_num_u; + +/* Define the union csr_dma_queue_sq_base_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sq_base_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_sq_base_l_u; + +/* Define the union csr_dma_queue_sq_base_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sq_base_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_sq_base_h_u; + +/* Define the union csr_dma_queue_sq_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sq_depth : 16; /* [15:0] */ + u32 rsv_82 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_sq_depth_u; + +/* Define the union csr_dma_queue_sq_tail_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sq_tail_ptr : 16; /* [15:0] */ + u32 rsv_83 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_sq_tail_ptr_u; + +/* Define the union csr_dma_queue_cq_base_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_cq_base_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_cq_base_l_u; + +/* Define the union csr_dma_queue_cq_base_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_cq_base_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_cq_base_h_u; + +/* Define the union csr_dma_queue_cq_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_cq_depth : 16; /* [15:0] */ + u32 rsv_84 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_cq_depth_u; + +/* Define the union csr_dma_queue_cq_head_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_cq_head_ptr : 16; /* [15:0] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_cq_head_ptr_u; + +/* Define the union csr_dma_queue_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_en : 1; /* [0] */ + u32 rsv_86 : 1; /* [1] */ + u32 rsv_87 : 1; /* [2] */ + u32 rsv_88 : 1; /* [3] */ + u32 dma_queue_pause : 1; /* [4] */ + u32 rsv_89 : 3; /* [7:5] */ + u32 dma_queue_arb_weight : 8; /* [15:8] */ + u32 rsv_90 : 1; /* [16] */ + u32 rsv_91 : 1; /* [17] */ + u32 rsv_92 : 1; /* [18] */ + u32 dma_queue_cq_mrg_en : 1; /* [19] */ + u32 dma_queue_cq_mrg_time : 2; /* [21:20] */ + u32 dma_queue_local_err_done_int_en : 1; /* [22] */ + u32 dma_queue_remote_err_done_int_en : 1; /* [23] */ + u32 rsv_93 : 1; /* [24] */ + u32 dma_queue_cq_full_disable : 1; /* [25] */ + u32 dma_queue_cq_drct_sel : 1; /* [26] */ + u32 dma_queue_sq_drct_sel : 1; /* [27] */ + u32 dma_queue_sq_pa_lkp_err_abort_en : 1; /* [28] */ + u32 dma_queue_sq_proc_err_abort_en : 1; /* [29] */ + u32 dma_queue_sq_drop_err_abort_en : 1; /* [30] */ + u32 dma_queue_sq_cfg_err_abort_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_ctrl0_u; + +/* Define the union csr_dma_queue_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_reset : 1; /* [0] */ + u32 dma_queue_abort_exit : 1; /* [1] */ + u32 dma_va_enable : 1; /* [2] */ + u32 rsv_94 : 1; /* [3] */ + u32 dma_queue_port_num : 4; /* [7:4] */ + u32 dma_queue_remote_msi_x_mask : 1; /* [8] */ + u32 rsv_95 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_ctrl1_u; + +/* Define the union csr_dma_queue_fsm_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sts : 4; /* [3:0] */ + u32 dma_queue_not_work : 1; /* [4] */ + u32 dma_queue_wait_spd_data_sts : 1; /* [5] */ + u32 rsv_96 : 2; /* [7:6] */ + u32 dma_queue_sub_fsm_sts : 3; /* [10:8] */ + u32 rsv_97 : 1; /* [11] */ + u32 dma_queue_sq_prefetch_fsm : 3; /* [14:12] */ + u32 rsv_98 : 1; /* [15] */ + u32 dma_queue_dscptor_aloc_fsm : 3; /* [18:16] */ + u32 rsv_99 : 1; /* [19] */ + u32 dma_queue_dscptor_pa_req_fsm : 3; /* [22:20] */ + u32 rsv_100 : 1; /* [23] */ + u32 dma_queue_cq_wrbk_fsm : 3; /* [26:24] */ + u32 rsv_101 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_fsm_sts_u; + +/* Define the union csr_dma_queue_sq_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sq_head_ptr : 16; /* [15:0] */ + u32 rsv_102 : 8; /* [23:16] */ + u32 rsv_103 : 1; /* [24] */ + u32 rsv_104 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_sq_sts_u; + +/* Define the union csr_dma_queue_cq_tail_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_cq_tail_ptr : 16; /* [15:0] */ + u32 dma_queue_sqhd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_cq_tail_ptr_u; + +/* Define the union csr_dma_queue_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_done_int_sts : 1; /* [0] */ + u32 dma_queue_err00_int_sts : 1; /* [1] */ + u32 dma_queue_err01_int_sts : 1; /* [2] */ + u32 dma_queue_err02_int_sts : 1; /* [3] */ + u32 dma_queue_err03_int_sts : 1; /* [4] */ + u32 rsv_105 : 1; /* [5] */ + u32 dma_queue_err05_int_sts : 1; /* [6] */ + u32 dma_queue_err06_int_sts : 1; /* [7] */ + u32 dma_queue_err07_int_sts : 1; /* [8] */ + u32 dma_queue_err08_int_sts : 1; /* [9] */ + u32 dma_queue_err09_int_sts : 1; /* [10] */ + u32 dma_queue_err10_int_sts : 1; /* [11] */ + u32 dma_queue_err11_int_sts : 1; /* [12] */ + u32 dma_queue_err12_int_sts : 1; /* [13] */ + u32 dma_queue_err13_int_sts : 1; /* [14] */ + u32 dma_queue_err14_int_sts : 1; /* [15] */ + u32 dma_queue_err15_int_sts : 1; /* [16] */ + u32 dma_queue_err16_int_sts : 1; /* [17] */ + u32 dma_queue_err17_int_sts : 1; /* [18] */ + u32 rsv_106 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_int_sts_u; + +/* Define the union csr_dma_queue_int_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_done_int_msk : 1; /* [0] */ + u32 dma_queue_err00_int_msk : 1; /* [1] */ + u32 dma_queue_err01_int_msk : 1; /* [2] */ + u32 dma_queue_err02_int_msk : 1; /* [3] */ + u32 dma_queue_err03_int_msk : 1; /* [4] */ + u32 rsv_107 : 1; /* [5] */ + u32 dma_queue_err05_int_msk : 1; /* [6] */ + u32 dma_queue_err06_int_msk : 1; /* [7] */ + u32 dma_queue_err07_int_msk : 1; /* [8] */ + u32 dma_queue_err08_int_msk : 1; /* [9] */ + u32 dma_queue_err09_int_msk : 1; /* [10] */ + u32 dma_queue_err10_int_msk : 1; /* [11] */ + u32 dma_queue_err11_int_msk : 1; /* [12] */ + u32 dma_queue_err12_int_msk : 1; /* [13] */ + u32 dma_queue_err13_int_msk : 1; /* [14] */ + u32 dma_queue_err14_int_msk : 1; /* [15] */ + u32 dma_queue_err15_int_msk : 1; /* [16] */ + u32 dma_queue_err16_int_msk : 1; /* [17] */ + u32 dma_queue_err17_int_msk : 1; /* [18] */ + u32 rsv_108 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_int_msk_u; + +/* Define the union csr_dfx_sq_read_err_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_err_ptr : 16; /* [15:0] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_sq_read_err_ptr_u; + +/* Define the union csr_dma_queue_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sts_done : 1; /* [0] */ + u32 dma_queue_sts_err00 : 1; /* [1] */ + u32 dma_queue_sts_err01 : 1; /* [2] */ + u32 dma_queue_sts_err02 : 1; /* [3] */ + u32 dma_queue_sts_err03 : 1; /* [4] */ + u32 rsv_110 : 1; /* [5] */ + u32 dma_queue_sts_err05 : 1; /* [6] */ + u32 dma_queue_sts_err06 : 1; /* [7] */ + u32 dma_queue_sts_err07 : 1; /* [8] */ + u32 dma_queue_sts_err08 : 1; /* [9] */ + u32 dma_queue_sts_err09 : 1; /* [10] */ + u32 dma_queue_sts_err10 : 1; /* [11] */ + u32 dma_queue_sts_err11 : 1; /* [12] */ + u32 dma_queue_sts_err12 : 1; /* [13] */ + u32 dma_queue_sts_err13 : 1; /* [14] */ + u32 dma_queue_sts_err14 : 1; /* [15] */ + u32 dma_queue_sts_err15 : 1; /* [16] */ + u32 dma_queue_sts_err16 : 1; /* [17] */ + u32 dma_queue_sts_err17 : 1; /* [18] */ + u32 rsv_111 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_int_ro_u; + +/* Define the union csr_dma_queue_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_done_int_set : 1; /* [0] */ + u32 dma_queue_err00_int_set : 1; /* [1] */ + u32 dma_queue_err01_int_set : 1; /* [2] */ + u32 dma_queue_err02_int_set : 1; /* [3] */ + u32 dma_queue_err03_int_set : 1; /* [4] */ + u32 rsv_112 : 1; /* [5] */ + u32 dma_queue_err05_int_set : 1; /* [6] */ + u32 dma_queue_err06_int_set : 1; /* [7] */ + u32 dma_queue_err07_int_set : 1; /* [8] */ + u32 dma_queue_err08_int_set : 1; /* [9] */ + u32 dma_queue_err09_int_set : 1; /* [10] */ + u32 dma_queue_err10_int_set : 1; /* [11] */ + u32 dma_queue_err11_int_set : 1; /* [12] */ + u32 dma_queue_err12_int_set : 1; /* [13] */ + u32 dma_queue_err13_int_set : 1; /* [14] */ + u32 dma_queue_err14_int_set : 1; /* [15] */ + u32 dma_queue_err15_int_set : 1; /* [16] */ + u32 dma_queue_err16_int_set : 1; /* [17] */ + u32 dma_queue_err17_int_set : 1; /* [18] */ + u32 rsv_113 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_int_set_u; + +/* Define the union csr_dfx_dma_err_int_num0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_err00_num : 4; /* [3:0] */ + u32 dma_queue_err01_num : 4; /* [7:4] */ + u32 dma_queue_err02_num : 4; /* [11:8] */ + u32 dma_queue_err03_num : 4; /* [15:12] */ + u32 dma_queue_err04_num : 4; /* [19:16] */ + u32 dma_queue_err05_num : 4; /* [23:20] */ + u32 dma_queue_err06_num : 4; /* [27:24] */ + u32 dma_queue_err07_num : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_dma_err_int_num0_u; + +/* Define the union csr_dfx_dma_err_int_num1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_err08_num : 4; /* [3:0] */ + u32 dma_queue_err09_num : 4; /* [7:4] */ + u32 dma_queue_err10_num : 4; /* [11:8] */ + u32 dma_queue_err11_num : 4; /* [15:12] */ + u32 dma_queue_err12_num : 4; /* [19:16] */ + u32 dma_queue_err13_num : 4; /* [23:20] */ + u32 dma_queue_err14_num : 4; /* [27:24] */ + u32 dma_queue_err15_num : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_dma_err_int_num1_u; + +/* Define the union csr_dfx_dma_err_int_num2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_err16_num : 4; /* [3:0] */ + u32 dma_queue_err17_num : 4; /* [7:4] */ + u32 rsv_114 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_dma_err_int_num2_u; + +/* Define the union csr_dma_queue_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_rmt_pf_cfg : 5; /* [4:0] */ + u32 rsv_115 : 11; /* [15:5] */ + u32 dma_queue_rmt_vf_cfg : 8; /* [23:16] */ + u32 rsv_116 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dma_queue_ctrl2_u; + +/* Define the union csr_done_int_merge_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_int_merge_time : 16; /* [15:0] */ + u32 dma_done_int_merge_en : 1; /* [16] */ + u32 rsv_117 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_done_int_merge_u; + +/* Define the union csr_dfx_dma_queue_sq_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_queue_sq_clean_buf : 1; /* [0] */ + u32 dma_queue_sq_clean_ot : 1; /* [1] */ + u32 rsv_118 : 1; /* [2] */ + u32 rsv_119 : 1; /* [3] */ + u32 dma_queue_barrier_wd_wst : 1; /* [4] */ + u32 dma_queue_barrier_rd_wst : 1; /* [5] */ + u32 dma_queue_cmtb_full : 1; /* [6] */ + u32 dma_queue_loc_np_ostb_full : 1; /* [7] */ + u32 dma_queue_rmt_np_ostb_full : 1; /* [8] */ + u32 dma_queue_loc_sq_ostb_full : 1; /* [9] */ + u32 rsv_120 : 6; /* [15:10] */ + u32 dma_queue_prebuf_resource : 12; /* [27:16] */ + u32 rsv_121 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_dma_reg_dfx_dma_queue_sq_sts2_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_0_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_1_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_2_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_3_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_4_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_5_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_6_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_7_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_8_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_9_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_10_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_11_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_12_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_13_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_14_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_15_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_16_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_17_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_18_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_19_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_20_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_21_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_22_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_23_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_24_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_25_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_26_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_27_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_28_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_29_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_30_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_pf_reg_31_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_0_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_1_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_2_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_3_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_4_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_5_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_6_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_7_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_8_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_9_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_10_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_11_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_12_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_13_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_14_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_15_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_16_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_17_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_18_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_19_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_20_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_21_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_22_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_23_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_24_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_25_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_26_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_27_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_28_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_29_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_30_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_31_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_32_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_33_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_34_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_35_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_36_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_37_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_38_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_39_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_40_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_41_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_42_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_43_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_44_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_45_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_46_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_47_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_48_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_49_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_50_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_51_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_52_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_53_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_54_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_55_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_56_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_57_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_58_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_59_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_60_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_61_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_62_cqhdbl_u; + +/* Define the union csr_nvme_ctrl_cap_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqes : 16; /* [15:0] */ + u32 cqr : 1; /* [16] */ + u32 ams : 2; /* [18:17] */ + u32 rsv_0 : 5; /* [23:19] */ + u32 timeout : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_cap_low_u; + +/* Define the union csr_nvme_ctrl_cap_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dstrd : 4; /* [3:0] */ + u32 nssrs : 1; /* [4] */ + u32 css : 8; /* [12:5] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 mpsmin : 4; /* [19:16] */ + u32 mpsmax : 4; /* [23:20] */ + u32 pmrs : 1; /* [24] */ + u32 cmbs : 1; /* [25] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_cap_high_u; + +/* Define the union csr_nvme_ctrl_vs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ter : 8; /* [7:0] */ + u32 mnr : 8; /* [15:8] */ + u32 mjr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_vs_u; + +/* Define the union csr_nvme_ctrl_intms_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intms : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_intms_u; + +/* Define the union csr_nvme_ctrl_intmc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intmc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_intmc_u; + +/* Define the union csr_nvme_ctrl_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enable : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 css : 3; /* [6:4] */ + u32 mps : 4; /* [10:7] */ + u32 ams : 3; /* [13:11] */ + u32 shn : 2; /* [15:14] */ + u32 iosqes : 4; /* [19:16] */ + u32 iocqes : 4; /* [23:20] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_config_u; + +/* Define the union csr_nvme_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 cfs : 1; /* [1] */ + u32 shst : 2; /* [3:2] */ + u32 nssro : 1; /* [4] */ + u32 pp : 1; /* [5] */ + u32 rsv_5 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_ctrl_status_u; + +/* Define the union csr_nvme_subsys_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nssrc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_nvme_subsys_rst_u; + +/* Define the union csr_aqa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqs : 16; /* [15:0] */ + u32 acqs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_aqa_u; + +/* Define the union csr_asqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_asqb_low_u; + +/* Define the union csr_asqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 asqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_asqb_high_u; + +/* Define the union csr_acqb_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 12; /* [11:0] */ + u32 acqb_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_acqb_low_u; + +/* Define the union csr_acqb_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acqb_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_acqb_high_u; + +/* Define the union csr_cmbloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bir : 3; /* [2:0] */ + u32 cqmms : 1; /* [3] */ + u32 cqpds : 1; /* [4] */ + u32 cdpmls : 1; /* [5] */ + u32 cdpcils : 1; /* [6] */ + u32 cdmmms : 1; /* [7] */ + u32 cqda : 1; /* [8] */ + u32 rsv_7 : 3; /* [11:9] */ + u32 offset : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_cmbloc_u; + +/* Define the union csr_cmbsz_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqs : 1; /* [0] */ + u32 cqs : 1; /* [1] */ + u32 lists : 1; /* [2] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 szu : 4; /* [11:8] */ + u32 sz : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_cmbsz_u; + +/* Define the union csr_cmbmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cre : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_9 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_cmbmsc_low_u; + +/* Define the union csr_cmbmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_cmbmsc_high_u; + +/* Define the union csr_cmbsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbai : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_cmbsts_u; + +/* Define the union csr_pmrcap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 3; /* [2:0] */ + u32 rds : 1; /* [3] */ + u32 wds : 1; /* [4] */ + u32 bir : 3; /* [7:5] */ + u32 pmrtu : 2; /* [9:8] */ + u32 pmrwbm : 4; /* [13:10] */ + u32 rsv_12 : 2; /* [15:14] */ + u32 pmrto : 8; /* [23:16] */ + u32 cmss : 1; /* [24] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_pmrcap_u; + +/* Define the union csr_pmrmsc_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_14 : 1; /* [0] */ + u32 cmse : 1; /* [1] */ + u32 rsv_15 : 10; /* [11:2] */ + u32 cba_low : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_pmrmsc_low_u; + +/* Define the union csr_pmrmsc_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cba_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_pmrmsc_high_u; + +/* Define the union csr_arm_drv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 arm_drv : 4; /* [3:0] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_arm_drv_u; + +/* Define the union csr_sqtdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqtdbl : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_sqtdbl_u; + +/* Define the union csr_cqhdbl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqhdbl : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_vf_reg_63_cqhdbl_u; + +/* Define the union csr_nvme_pf_ctrl_reg_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_mask : 1; /* [0] */ + u32 wr_aqa_int_mask : 1; /* [1] */ + u32 wr_cc_int_mask : 1; /* [2] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_ctrl_reg_int_mask_u; + +/* Define the union csr_nvme_pf_ctrl_reg_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_sts : 1; /* [0] */ + u32 wr_aqa_int_sts : 1; /* [1] */ + u32 wr_cc_int_sts : 1; /* [2] */ + u32 rsv_1 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_ctrl_reg_int_sts_u; + +/* Define the union csr_nvme_pf_ctrl_reg_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_set : 1; /* [0] */ + u32 wr_aqa_int_set : 1; /* [1] */ + u32 wr_cc_int_set : 1; /* [2] */ + u32 rsv_2 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_ctrl_reg_int_set_u; + +/* Define the union csr_nvme_pf_ctrl_reg_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_ro : 1; /* [0] */ + u32 wr_aqa_int_ro : 1; /* [1] */ + u32 wr_cc_int_ro : 1; /* [2] */ + u32 rsv_3 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_ctrl_reg_int_ro_u; + +/* Define the union csr_nvme_pf_iep_int_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_iep_int_mode : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_iep_int_mode_u; + +/* Define the union csr_nvme_pf_queue_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 12; /* [11:0] */ + u32 pf_queue_num : 11; /* [22:12] */ + u32 rsv_6 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_queue_num_u; + +/* Define the union csr_nvme_pf_vf_queue_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_vf_queue_num : 10; /* [9:0] */ + u32 rsv_7 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_vf_queue_num_u; + +/* Define the union csr_nvme_db_strd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_vf_strd : 4; /* [3:0] */ + u32 pf_strd : 4; /* [7:4] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_db_strd_u; + +/* Define the union csr_nvme_pf_bar0_db_atu_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_bar0_db_atu_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_bar0_db_atu_low_u; + +/* Define the union csr_nvme_pf_bar0_db_atu_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_bar0_db_atu_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_bar0_db_atu_high_u; + +/* Define the union csr_nvme_pf_vf_bar0_db_atu_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_vf_bar0_db_atu_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_vf_bar0_db_atu_low_u; + +/* Define the union csr_nvme_pf_vf_bar0_db_atu_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_vf_bar0_db_atu_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_vf_bar0_db_atu_high_u; + +/* Define the union csr_nvme_vf_ctrl_reg_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_mask : 1; /* [0] */ + u32 wr_aqa_int_mask : 1; /* [1] */ + u32 wr_cc_int_mask : 1; /* [2] */ + u32 rsv_9 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vf_ctrl_reg_int_mask_u; + +/* Define the union csr_nvme_vf_ctrl_reg_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_sts : 1; /* [0] */ + u32 wr_aqa_int_sts : 1; /* [1] */ + u32 wr_cc_int_sts : 1; /* [2] */ + u32 rsv_10 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vf_ctrl_reg_int_sts_u; + +/* Define the union csr_nvme_vf_ctrl_reg_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_set : 1; /* [0] */ + u32 wr_aqa_int_set : 1; /* [1] */ + u32 wr_cc_int_set : 1; /* [2] */ + u32 rsv_11 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vf_ctrl_reg_int_set_u; + +/* Define the union csr_nvme_vf_ctrl_reg_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_asq_int_ro : 1; /* [0] */ + u32 wr_aqa_int_ro : 1; /* [1] */ + u32 wr_cc_int_ro : 1; /* [2] */ + u32 rsv_12 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vf_ctrl_reg_int_ro_u; + +/* Define the union csr_nvme_vf_iep_int_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_iep_int_mode : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vf_iep_int_mode_u; + +/* Define the union csr_nvme_cqdb_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_doorbell_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cqdb_int_mask_u; + +/* Define the union csr_nvme_cqdb_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_doorbell_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cqdb_int_sts_u; + +/* Define the union csr_nvme_cqdb_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_doorbell_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cqdb_int_set_u; + +/* Define the union csr_nvme_cqdb_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_doorbell_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cqdb_int_ro_u; + +/* Define the union csr_nvme_sqdb_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_doorbell_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sqdb_int_mask_u; + +/* Define the union csr_nvme_sqdb_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_doorbell_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sqdb_int_sts_u; + +/* Define the union csr_nvme_sqdb_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_doorbell_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sqdb_int_set_u; + +/* Define the union csr_nvme_sqdb_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_doorbell_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sqdb_int_ro_u; + +/* Define the union csr_nvme_wrptr_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrptr_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_wrptr_int_mask_u; + +/* Define the union csr_nvme_wrptr_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrptr_int_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_wrptr_int_sts_u; + +/* Define the union csr_nvme_wrptr_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrptr_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_wrptr_int_set_u; + +/* Define the union csr_nvme_wrptr_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrptr_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_wrptr_int_ro_u; + +/* Define the union csr_nvme_cq_err_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_err_int_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cq_err_int_sts_u; + +/* Define the union csr_nvme_cq_err_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_err_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cq_err_int_mask_u; + +/* Define the union csr_nvme_cq_err_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_err_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cq_err_int_set_u; + +/* Define the union csr_nvme_cq_err_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_err_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_cq_err_int_ro_u; + +/* Define the union csr_nvme_rba_ack_err_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ack_err_int_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_rba_ack_err_int_sts_u; + +/* Define the union csr_nvme_rba_ack_err_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ack_err_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_rba_ack_err_int_mask_u; + +/* Define the union csr_nvme_rba_ack_err_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ack_err_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_rba_ack_err_int_set_u; + +/* Define the union csr_nvme_rba_ack_err_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ack_err_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_rba_ack_err_int_ro_u; + +/* Define the union csr_nvme_queue_coal_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_coal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_queue_coal_mask_u; + +/* Define the union csr_nvme_queue_iep_int_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_iep_int_mode : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_queue_iep_int_mode_u; + +/* Define the union csr_nvme_queue_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_queue_en_u; + +/* Define the union csr_nvme_queue_delete_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_delete : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_queue_delete_u; + +/* Define the union csr_dfx_queue_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_queue_sts_u; + +/* Define the union csr_nvme_ep_normal_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrptr_int_ro : 1; /* [0] */ + u32 sq_db_int_ro : 1; /* [1] */ + u32 cq_db_int_ro : 1; /* [2] */ + u32 vf_ctrl_int_ro : 1; /* [3] */ + u32 pf_ctrl_int_ro : 1; /* [4] */ + u32 rsv_14 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ep_normal_int_ro_u; + +/* Define the union csr_nvme_ep_abnormal_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_ack_err_int_ro : 1; /* [0] */ + u32 cq_err_err_int_ro : 1; /* [1] */ + u32 abnormal_int_ro : 1; /* [2] */ + u32 rsv_15 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ep_abnormal_int_ro_u; + +/* Define the union csr_nvme_ep_err_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rbd_tlp_err_int_sts : 1; /* [0] */ + u32 sq_tl_err_int_sts : 1; /* [1] */ + u32 sq_hd_err_int_sts : 1; /* [2] */ + u32 fcton_regs_ram_ecc_2bit_int_sts : 1; /* [3] */ + u32 fcton_regs_ram_ecc_1bit_int_sts : 1; /* [4] */ + u32 pref_fifo_ram_ecc_2bit_int_sts : 1; /* [5] */ + u32 pref_fifo_ram_ecc_1bit_int_sts : 1; /* [6] */ + u32 sq_des_ram_ecc_2bit_int_sts : 1; /* [7] */ + u32 sq_des_ram_ecc_1bit_int_sts : 1; /* [8] */ + u32 queue_reg_ram_ecc_2bit_int_sts : 1; /* [9] */ + u32 queue_reg_ram_ecc_1bit_int_sts : 1; /* [10] */ + u32 rsv_16 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ep_err_int_sts_u; + +/* Define the union csr_nvme_ep_err_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rbd_tlp_err_int_mask : 1; /* [0] */ + u32 sq_tl_err_int_mask : 1; /* [1] */ + u32 sq_hd_err_int_mask : 1; /* [2] */ + u32 fcton_regs_ram_ecc_2bit_int_mask : 1; /* [3] */ + u32 fcton_regs_ram_ecc_1bit_int_mask : 1; /* [4] */ + u32 pref_fifo_ram_ecc_2bit_int_mask : 1; /* [5] */ + u32 pref_fifo_ram_ecc_1bit_int_mask : 1; /* [6] */ + u32 sq_des_ram_ecc_2bit_int_mask : 1; /* [7] */ + u32 sq_des_ram_ecc_1bit_int_mask : 1; /* [8] */ + u32 queue_reg_ram_ecc_2bit_int_mask : 1; /* [9] */ + u32 queue_reg_ram_ecc_1bit_int_mask : 1; /* [10] */ + u32 rsv_17 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ep_err_int_mask_u; + +/* Define the union csr_nvme_ep_err_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rbd_tlp_err_int_set : 1; /* [0] */ + u32 sq_tl_err_int_set : 1; /* [1] */ + u32 sq_hd_err_int_set : 1; /* [2] */ + u32 fcton_regs_ram_ecc_2bit_int_set : 1; /* [3] */ + u32 fcton_regs_ram_ecc_1bit_int_set : 1; /* [4] */ + u32 pref_fifo_ram_ecc_2bit_int_set : 1; /* [5] */ + u32 pref_fifo_ram_ecc_1bit_int_set : 1; /* [6] */ + u32 sq_des_ram_ecc_2bit_int_set : 1; /* [7] */ + u32 sq_des_ram_ecc_1bit_int_set : 1; /* [8] */ + u32 queue_reg_ram_ecc_2bit_int_set : 1; /* [9] */ + u32 queue_reg_ram_ecc_1bit_int_set : 1; /* [10] */ + u32 rsv_18 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ep_err_int_set_u; + +/* Define the union csr_nvme_ep_err_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rbd_tlp_err_int_ro : 1; /* [0] */ + u32 sq_tl_err_int_ro : 1; /* [1] */ + u32 sq_hd_err_int_ro : 1; /* [2] */ + u32 fcton_regs_ram_ecc_2bit_int_ro : 1; /* [3] */ + u32 fcton_regs_ram_ecc_1bit_int_ro : 1; /* [4] */ + u32 pref_fifo_ram_ecc_2bit_int_ro : 1; /* [5] */ + u32 pref_fifo_ram_ecc_1bit_int_ro : 1; /* [6] */ + u32 sq_des_ram_ecc_2bit_int_ro : 1; /* [7] */ + u32 sq_des_ram_ecc_1bit_int_ro : 1; /* [8] */ + u32 queue_reg_ram_ecc_2bit_int_ro : 1; /* [9] */ + u32 queue_reg_ram_ecc_1bit_int_ro : 1; /* [10] */ + u32 rsv_19 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ep_err_int_ro_u; + +/* Define the union csr_nvme_vector_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iep0_vector_pending : 16; /* [15:0] */ + u32 iep1_vector_pending : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vector_pending_u; + +/* Define the union csr_nvme_vector_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iep0_vector_mask : 16; /* [15:0] */ + u32 iep1_vector_mask : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vector_mask_u; + +/* Define the union csr_nvme_int_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_set : 1; /* [0] */ + u32 int_deassert : 1; /* [1] */ + u32 int_vector : 11; /* [12:2] */ + u32 rsv_20 : 4; /* [16:13] */ + u32 vf_num : 8; /* [24:17] */ + u32 pf_num : 5; /* [29:25] */ + u32 ep_num : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_int_req_u; + +/* Define the union csr_nvme_ctrl_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_coal_en : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ctrl_misc_u; + +/* Define the union csr_nvme_db_int_coal_time_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 time_cnt_unit : 16; /* [15:0] */ + u32 rsv_22 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_db_int_coal_time_unit_u; + +/* Define the union csr_nvme_db_int_coal_aggre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_aggre_thr : 8; /* [7:0] */ + u32 int_aggre_time : 8; /* [15:8] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_db_int_coal_aggre_u; + +/* Define the union csr_nvme_engine_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eng_work_mode_sel : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_engine_sel_u; + +/* Define the union csr_nvme_ack_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_ack_mode : 1; /* [0] */ + u32 tlp_ack_user_sel : 1; /* [1] */ + u32 tlp_ack_user_poison : 4; /* [5:2] */ + u32 tlp_ack_user_err : 4; /* [9:6] */ + u32 rsv_25 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ack_mode_u; + +/* Define the union csr_nvme_ddr_strd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_wrptr_strd : 4; /* [3:0] */ + u32 rsv_26 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ddr_strd_u; + +/* Define the union csr_nvme_sqe_rd_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqe_rd_max : 3; /* [2:0] */ + u32 rsv_27 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sqe_rd_max_u; + +/* Define the union csr_nvme_ram_initial_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_initial : 3; /* [2:0] */ + u32 rsv_28 : 13; /* [15:3] */ + u32 ram_inital_done : 3; /* [18:16] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ram_initial_u; + +/* Define the union csr_nvme_link_down_proc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_link_down_prt_initial : 1; /* [0] */ + u32 rsv_30 : 15; /* [15:1] */ + u32 ep0_link_up_sts : 1; /* [16] */ + u32 ep1_link_up_sts : 1; /* [17] */ + u32 ep2_link_up_sts : 1; /* [18] */ + u32 ep3_link_up_sts : 1; /* [19] */ + u32 rsv_31 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_link_down_proc_u; + +/* Define the union csr_nvme_flr_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_flr_ptr_inital : 1; /* [0] */ + u32 nvme_flr_proc_cmpl : 1; /* [1] */ + u32 rsv_32 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_flr_sts_u; + +/* Define the union csr_nvme_dma_cq_err_initial_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_cq_err_ptr_initial : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_dma_cq_err_initial_u; + +/* Define the union csr_nvme_ro_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep0_wrptr_ro_cfg : 3; /* [2:0] */ + u32 ep1_wrptr_ro_cfg : 3; /* [5:3] */ + u32 ep2_wrptr_ro_cfg : 3; /* [8:6] */ + u32 ep3_wrptr_ro_cfg : 3; /* [11:9] */ + u32 rsv_34 : 4; /* [15:12] */ + u32 ep0_sq_des_ro_cfg : 3; /* [18:16] */ + u32 ep1_sq_des_ro_cfg : 3; /* [21:19] */ + u32 ep2_sq_des_ro_cfg : 3; /* [24:22] */ + u32 ep3_sq_des_ro_cfg : 3; /* [27:25] */ + u32 rsv_35 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_ro_cfg_u; + +/* Define the union csr_nvme_soft_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_soft_rst : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_soft_rst_u; + +/* Define the union csr_nvme_int_mod_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_abnormal_int_mode : 1; /* [0] */ + u32 nvme_nomral_int_mode : 1; /* [1] */ + u32 abnormal_iep_int_mode : 2; /* [3:2] */ + u32 rsv_37 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_int_mod_sel_u; + +/* Define the union csr_nvme_int_level_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_cq_err_int_level_cfg : 1; /* [0] */ + u32 nvme_1bit_ecc_level_cfg : 1; /* [1] */ + u32 nvme_2bit_ecc_level_cfg : 1; /* [2] */ + u32 nvme_sq_err_level_cfg : 1; /* [3] */ + u32 nvme_rba_ack_err_level_cfg : 1; /* [4] */ + u32 nvme_rbd_tlp_err_level_cfg : 1; /* [5] */ + u32 rsv_38 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_int_level_sel_u; + +/* Define the union csr_nvme_rba_credit_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rba_data_cdt_cnt_clr : 1; /* [0] */ + u32 rba_hed_cdt_cnt_clr : 1; /* [1] */ + u32 rba_cdt_active_dis : 1; /* [2] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_rba_credit_clr_u; + +/* Define the union csr_nvme_rbd_credit_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rbd_data_cdt_cnt_clr : 1; /* [0] */ + u32 rbd_hed_cdt_cnt_clr : 1; /* [1] */ + u32 rbd_cdt_active_dis : 1; /* [2] */ + u32 rsv_40 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_rbd_credit_clr_u; + +/* Define the union csr_nvme_vf_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_size : 6; /* [5:0] */ + u32 rsv_41 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_vf_size_u; + +/* Define the union csr_nvme_wrptr_base_adddr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_42 : 2; /* [1:0] */ + u32 wr_ptr_base_addr_low : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_wrptr_base_adddr_low_u; + +/* Define the union csr_nmme_wrptr_base_adddr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_ptr_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nmme_wrptr_base_adddr_high_u; + +/* Define the union csr_nvme_mem_base_adddr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_43 : 6; /* [5:0] */ + u32 memory_base_addr_low : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_mem_base_adddr_low_u; + +/* Define the union csr_nvme_mem_base_adddr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memory_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_mem_base_adddr_high_u; + +/* Define the union csr_nvme_mem_space_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memory_space_low : 4; /* [3:0] */ + u32 rsv_44 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_mem_space_low_u; + +/* Define the union csr_nvme_mem_space_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_45 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_mem_space_high_u; + +/* Define the union csr_nvme_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_idle : 1; /* [0] */ + u32 nvme_ep0_idle : 1; /* [1] */ + u32 nvme_ep1_idle : 1; /* [2] */ + u32 nvme_ep2_idle : 1; /* [3] */ + u32 nvme_ep3_idle : 1; /* [4] */ + u32 rsv_46 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_idle_u; + +/* Define the union csr_nvme_pf_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_pf_vld : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_pf_vld_u; + +/* Define the union csr_dfx_ram_ecc_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcton_regs_ram_ecc_inject : 4; /* [3:0] */ + u32 pref_fifo_ram_ecc_inject : 4; /* [7:4] */ + u32 sq_des_ram_ecc_inject : 4; /* [11:8] */ + u32 queue_reg_ram_ecc_inject : 4; /* [15:12] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_ram_ecc_inject_u; + +/* Define the union csr_dfx_queue_reg_ram_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_reg_ram_1bit_ecc_cnt : 8; /* [7:0] */ + u32 rsv_48 : 8; /* [15:8] */ + u32 queue_reg_ram_2bit_ecc_cnt : 8; /* [23:16] */ + u32 rsv_49 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_queue_reg_ram_ecc_cnt_u; + +/* Define the union csr_dfx_queue_reg_ram_ecc_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_reg_ram_1bit_ecc_addr : 10; /* [9:0] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 queue_reg_ram_2bit_ecc_addr : 10; /* [25:16] */ + u32 rsv_51 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_queue_reg_ram_ecc_addr_u; + +/* Define the union csr_dfx_sq_des_ram_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ram_1bit_ecc_cnt : 8; /* [7:0] */ + u32 rsv_52 : 8; /* [15:8] */ + u32 sq_des_ram_2bit_ecc_cnt : 8; /* [23:16] */ + u32 rsv_53 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_ecc_cnt_u; + +/* Define the union csr_dfx_sq_des_ram_ecc_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ram_1bit_ecc_addr : 10; /* [9:0] */ + u32 rsv_54 : 6; /* [15:10] */ + u32 sq_des_ram_2bit_ecc_addr : 10; /* [25:16] */ + u32 rsv_55 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_ecc_addr_u; + +/* Define the union csr_dfx_pref_fifo_ram_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pref_fifo_ram_1bit_ecc_cnt : 8; /* [7:0] */ + u32 rsv_56 : 8; /* [15:8] */ + u32 pref_fifo_ram_2bit_ecc_cnt : 8; /* [23:16] */ + u32 rsv_57 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_pref_fifo_ram_ecc_cnt_u; + +/* Define the union csr_dfx_pref_fifo_ram_ecc_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pref_fifo_ram_1bit_ecc_addr : 10; /* [9:0] */ + u32 rsv_58 : 6; /* [15:10] */ + u32 pref_fifo_ram_2bit_ecc_addr : 10; /* [25:16] */ + u32 rsv_59 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_pref_fifo_ram_ecc_addr_u; + +/* Define the union csr_dfx_fcton_regs_ram_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcton_regs_ram_1bit_ecc_cnt : 8; /* [7:0] */ + u32 rsv_60 : 8; /* [15:8] */ + u32 fcton_regs_ram_2bit_ecc_cnt : 8; /* [23:16] */ + u32 rsv_61 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_fcton_regs_ram_ecc_cnt_u; + +/* Define the union csr_dfx_fcton_regs_ram_ecc_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcton_regs_ram_1bit_ecc_addr : 10; /* [9:0] */ + u32 rsv_62 : 6; /* [15:10] */ + u32 fcton_regs_ram_2bit_ecc_addr : 10; /* [25:16] */ + u32 rsv_63 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_fcton_regs_ram_ecc_addr_u; + +/* Define the union csr_dfx_sq_head_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_head_err_ptr : 16; /* [15:0] */ + u32 sq_head_err_queue_num : 10; /* [25:16] */ + u32 rsv_64 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_head_err_u; + +/* Define the union csr_dfx_sq_tail_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_tail_err_ptr : 16; /* [15:0] */ + u32 sq_tail_err_queue_num : 10; /* [25:16] */ + u32 rsv_65 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_tail_err_u; + +/* Define the union csr_dfx_rbd_tlp_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rbd_tlp_err_type : 5; /* [4:0] */ + u32 rsv_66 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_rbd_tlp_err_u; + +/* Define the union csr_dfx_dma_cq_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_cq_err_sts : 12; /* [11:0] */ + u32 rsv_67 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_dma_cq_err_status_u; + +/* Define the union csr_dfx_sq_des_ram_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ctrl_ram_addr : 10; /* [9:0] */ + u32 rsv_68 : 20; /* [29:10] */ + u32 sq_des_ctrl_ram_rd : 1; /* [30] */ + u32 sq_des_ctrl_ram_wr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_cfg_u; + +/* Define the union csr_dfx_sq_des_ram_wdat_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ram_wr_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_wdat_l_u; + +/* Define the union csr_dfx_sq_des_ram_wdat_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ram_hd_ptr : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_wdat_h_u; + +/* Define the union csr_dfx_sq_des_ram_rdat_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ram_wr_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_rdat_l_u; + +/* Define the union csr_dfx_sq_des_ram_rdat_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_des_ram_hd_ptr : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_sq_des_ram_rdat_h_u; + +/* Define the union csr_dfx_nvme_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_71 : 4; /* [3:0] */ + u32 sq_des_ctrl_fifo_empty : 1; /* [4] */ + u32 sq_des_ctrl_fifo_full : 1; /* [5] */ + u32 rsv_72 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_nvme_fifo_sts_u; + +/* Define the union csr_dfx_nvme_queue_reg_ram_fsm_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_queue_reg_ram_fsm_sts : 2; /* [1:0] */ + u32 rsv_73 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_nvme_queue_reg_ram_fsm_sts_u; + +/* Define the union csr_dfx_nvme_flow_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cq_cnt : 16; /* [15:0] */ + u32 sq_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_nvme_flow_sts0_u; + +/* Define the union csr_dfx_nvme_flow_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrptr_bresp_cnt : 16; /* [15:0] */ + u32 wrptr_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_dfx_nvme_flow_sts1_u; + +/* Define the union csr_nvme_queue_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 submission_queue_size : 16; /* [15:0] */ + u32 completion_queue_size : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_queue_size_u; + +/* Define the union csr_nvme_sq_base_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqr_base_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sq_base_addr_low_u; + +/* Define the union csr_nvme_sq_base_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sqr_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sq_base_addr_high_u; + +/* Define the union csr_nvme_sqr_mem_rdptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memory_rd_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_ap_nvme_global_reg_nvme_sqr_mem_rdptr_u; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_core_addr_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_core_addr_define.h new file mode 100644 index 000000000..6e3bad6fa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_core_addr_define.h @@ -0,0 +1,3233 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : pcie5_core_addr_define.h + * Project line : Platform And Technologies Development + * Department : CAD Development Department + * Version : 1.0 + * Date : + * Description : PCIE Controller 5.0 Version 200 + * Others : Generated automatically by nManager V5.1 + * History : 2021/01/07 09:08:21 Create file + */ + +#ifndef PCIE5_CORE_ADDR_DEFINE_H +#define PCIE5_CORE_ADDR_DEFINE_H + +/* HIPCIEC50_TOP_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TOP_REG_BASE (0x5C000) + +/* **************************************************************************** */ +/* HIPCIEC50_TOP_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_SET_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x0) /* apb timeout interrupt set \ + */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_MASK_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x4) /* apb timeout interrupt mask */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_STATUS_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x8) /* apb timeout interrupt status */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INT_RO_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0xC) /* apb timeout interrupt status */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_NI_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x10) /* pcie top local interrupt selection for ni */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_CE_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x14) /* pcie top local interrupt selection for ce */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_NFE_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x18) /* pcie top local interrupt selection for nfe */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_TOP_LOCAL_INT_EN_FE_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x1C) /* pcie top local interrupt selection for fe */ +#define CSR_HIPCIEC50_TOP_REG_APB_WR_LAST_ADD_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x20) /* APB WRITE LAST ADDR */ +#define CSR_HIPCIEC50_TOP_REG_APB_WR_TIMES_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x24) /* APB WRITE NUMBERS */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIMER_CTRL_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x30) /* apb timeout timer control */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_INFO_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x34) /* apb timeout status */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIME_OUT_NUM_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x38) /* apb timeout number */ +#define CSR_HIPCIEC50_TOP_REG_APB_TIMEOUT_RDATA_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x3C) /* APB rdata for timeout */ +#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x100) /* IEP axi user */ +#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x104) /* IEP axi user */ +#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x108) /* IEP axi user */ +#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x10C) /* IEP axi user */ +#define CSR_HIPCIEC50_TOP_REG_PEH_AXI_USER_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x110) /* IEP axi user */ +#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x120) /* iep tlp tc_id */ +#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x124) /* iep tlp tc_id */ +#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x128) /* iep tlp tc_id */ +#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x12C) /* iep tlp tc_id */ +#define CSR_HIPCIEC50_TOP_REG_IEP_TC_ID_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x130) /* iep tlp tc_id */ +#define CSR_HIPCIEC50_TOP_REG_IEP_CREDIT_CLR_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x140) /* crdit cnt clear */ +#define CSR_HIPCIEC50_TOP_REG_IEP_REG_ON_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x144) /* peh cfgspace enable */ +#define CSR_HIPCIEC50_TOP_REG_APB_RESERVE_RDATA_REG \ + (CSR_HIPCIEC50_TOP_REG_BASE + 0x148) /* apb access reserve addr , return rdata */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x800) /* peh MSI dfx0 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x810) /* peh MSI dfx0 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x820) /* peh MSI dfx0 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x830) /* peh MSI dfx0 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX0_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x840) /* peh MSI dfx0 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x804) /* peh MSI dfx1 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x814) /* peh MSI dfx1 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x824) /* peh MSI dfx1 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x834) /* peh MSI dfx1 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX1_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x844) /* peh MSI dfx1 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x808) /* peh MSI dfx2 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x818) /* peh MSI dfx2 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x828) /* peh MSI dfx2 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x838) /* peh MSI dfx2 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX2_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x848) /* peh MSI dfx2 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_0_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x80C) /* peh MSI dfx3 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_1_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x81C) /* peh MSI dfx3 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_2_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x82C) /* peh MSI dfx3 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_3_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x83C) /* peh MSI dfx3 info */ +#define CSR_HIPCIEC50_TOP_REG_PCIE_PEH_MSI_DFX3_4_REG (CSR_HIPCIEC50_TOP_REG_BASE + 0x84C) /* peh MSI dfx3 info */ + +/* HIPCIEC50_CORE_CLKRST_CTRL_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE (0x5E000) + +/* **************************************************************************** */ +/* HIPCIEC50_CORE_CLKRST_CTRL_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PORT_RESET_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x0) /* port reset */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PHY_RESET_REG (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x4) /* phy reset \ + */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_CORE_CLK_FLG_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x8) /* dfx core clk exist flag */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCS_SOFT_REST_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0xC) /* PCS and axi soft reset */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_AP_AXI_SFT_RST_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x10) /* ap or axi soft reset */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_CORE_TL_COM_SFT_RST_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x14) /* tl common soft reset */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_CORE_PHY_COM_SFT_RST_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x18) /* phy common soft reset */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_ICG_EN_PIPE_LANE_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x1C) /* pcie_icg_en_pipe_lane */ +#define CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_PCIE_ICG_EN_CORE_PHY_LANE_REG \ + (CSR_HIPCIEC50_CORE_CLKRST_CTRL_REG_BASE + 0x20) /* pcie_icg_en_core_phy_lane */ + +/* HIPCIEC50_CORE_CTRL_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_BASE (0x5E000) + +/* **************************************************************************** */ +/* HIPCIEC50_CORE_CTRL_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT_EN_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x400) /* port enable */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT_RESET_CFG_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x404) /* port reset */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_TURBO_SIM_SEL_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x408) /* turbo sim selection */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_LOCAL_LOOPBACK_MODE_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x40C) /* local loopback mode selection */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x410) /* PCIE SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x414) /* PCIE SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_2_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x418) /* PCIE SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_3_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x41C) /* PCIE SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_TIMING_CFG_4_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x420) /* PCIE SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_CTRL_BUS_SP_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x424) /* PCIE SP SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SRAM_CTRL_BUS_TP_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x428) /* PCIE TP SRAM timing config register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_GLB_SRAM_CTRL_BUS_EN_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x42C) /* select the value in register output to control bus */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_INSERT_SKP_DATA_PARITY_ERR_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x430) /* insert skp data parity error in scramble module */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_GLB_PCIEC_MODE_SEL_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x434) /* select pcie to up or dp and also can select pcie to rc or ep */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_RELEASE_I_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x500) /* pcie release info */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_VERSION_I_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x504) /* pcie version info */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_APB_ECO_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x50C) /* apb eco register */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT07_LINK_MODE_REG (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x510) /* port link mode \ + */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT815_LINK_MODE_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x514) /* port link mode */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PORT_RST_DLY_CNT_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x518) /* port soft reset or linkdown reset delay count */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_SET_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x51C) /* hilink interrupt set */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_MASK_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x520) /* hilink interrupt mask */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_RO_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x524) /* hilink interrupt ro */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_STATUS_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x528) /* hilink interrupt status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_HILINK_INT_SEL_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x52C) /* hilink interrupt type configure */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_SET_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x530) /* CORE interrupt set ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_MSK_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x534) /* CORE interrupt mask ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_STATUS_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x538) /* CORE interrupt status ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_RO_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x53C) /* CORE interrupt RO ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_SET_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x540) /* CORE interrupt set ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_MSK_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x544) /* CORE interrupt mask ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_STATUS_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x548) /* CORE interrupt status ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NI_RO_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x54C) /* CORE interrupt RO ni */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_SET_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x550) /* CORE interrupt set ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_MSK_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x554) /* CORE interrupt mask ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_STATUS_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x558) /* CORE interrupt status ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_RO_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x55C) /* CORE interrupt RO ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_SET_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x560) /* CORE interrupt set ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_MSK_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x564) /* CORE interrupt mask ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_STATUS_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x568) /* CORE interrupt status ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_CE_RO_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x56C) /* CORE interrupt RO ce */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_SET_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x570) /* CORE interrupt set nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_MSK_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x574) /* CORE interrupt mask nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_STATUS_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x578) /* CORE interrupt status nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_RO_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x57C) /* CORE interrupt RO nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_SET_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x580) /* CORE interrupt set nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_MSK_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x584) /* CORE interrupt mask nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_STATUS_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x588) /* CORE interrupt status nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_NFE_RO_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x58C) /* CORE interrupt RO nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_SET_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x590) /* CORE interrupt set nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_MSK_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x594) /* CORE interrupt mask nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_STATUS_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x598) /* CORE interrupt status nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_RO_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x59C) /* CORE interrupt RO nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_SET_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5A0) /* CORE interrupt set nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_MSK_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5A4) /* CORE interrupt mask nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_STATUS_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5A8) /* CORE interrupt status nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_INT_FE_RO_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x5AC) /* CORE interrupt RO nfe */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_CORE_GLB_MISC_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x700) /* phy mode and txbuf mode */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_DPTX_FIFO_THRES_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x704) /* mac cdc module tx data path fifo thres */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_0_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x708) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_1_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x70C) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_2_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x710) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_3_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x714) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_4_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x718) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_5_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x71C) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_6_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x720) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_7_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x724) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_8_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x728) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_9_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x72C) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_10_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x730) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_11_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x734) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_12_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x738) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_13_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x73C) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_14_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x740) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_STATUS_15_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x744) /* mac cdc module status */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_MAC_CDC_CONFIG_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x74C) /* configure register for mac-cdc */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_LINKDOWN_RST_REG_ERN_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x750) /* linkdown_rst_reg_en */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SDS_CS_CALIB_DONE_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x754) /* pcie_sds_cs_calib_done */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_SDS_PRBS_ERR_ST_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x758) /* pcie_sds_prbs_err_st */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_LINK_DOWN_RST_EN_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x75C) /* linkdown_rst_en */ +#define CSR_HIPCIEC50_CORE_CTRL_REG_PCIE_LINK_DOWN_CLR_PORT_EN_REG \ + (CSR_HIPCIEC50_CORE_CTRL_REG_BASE + 0x760) /* linkdown_clr_port_en */ + +/* HIPCIEC50_DL_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_DL_REG_BASE (0x60000) + +/* **************************************************************************** */ +/* HIPCIEC50_DL_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_DL_REG_TX_FC_INIT_CYCLE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x0) /* the initial fc DLLP frequency \ + */ +#define CSR_HIPCIEC50_DL_REG_FC_INIT_TIMEOUT_LIMIT_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x4) /* the limit value of initial FC in all time */ +#define CSR_HIPCIEC50_DL_REG_VC_FC_INIT_ALLTIMEOUT_HANDING_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x8) /* the VC initializtion timeout handing */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0xC) /* the ack transmission latency limit for 2.5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x10) /* the ack transmission latency limit for 5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G3_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x14) /* the ack transmission latency limit for 8GT/s mod */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G4_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x18) /* the ack transmission latency limit for 16GT/s mod */ +#define CSR_HIPCIEC50_DL_REG_ACK_NAKD_TLP_NUM_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x1C) /* the limit value of received number of not acknowledged TLP. */ +#define CSR_HIPCIEC50_DL_REG_DFX_DUP_ACK_NUM_LIMIT_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x20) /* duplicate TLP received num limit. */ +#define CSR_HIPCIEC50_DL_REG_DFX_NAK_TIME_LIMIT_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + \ + 0x24) /* the limit value between transimitted a NAK DLLP to received the last ACK DLLP. */ +#define CSR_HIPCIEC50_DL_REG_CREDIT_NULL_FOR_SET_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x28) /* set credit null enable,count timer limit value. */ +#define CSR_HIPCIEC50_DL_REG_REPLAY_CYCLE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x2C) /* the replay time cycle for all mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x30) /* the update timer for 2.5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x34) /* the update timer for 5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G3_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x38) /* the update timer for 8GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G4_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x3C) /* the update timer for 16GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_RX_FC_UPDATE_TIME_LIMIT_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x40) /* update DLLP timeout error vaules */ +#define CSR_HIPCIEC50_DL_REG_ECC_ERR_CNT_1BIT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x44) /* ECC error occur count */ +#define CSR_HIPCIEC50_DL_REG_ECC_ERR_CNT_2BIT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x48) /* ECC error occur count */ +#define CSR_HIPCIEC50_DL_REG_DATA_RAM0_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x4C) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_DFX_LCRC_ERR_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x50) /* the lcrc error number */ +#define CSR_HIPCIEC50_DL_REG_DFX_DCRC_ERR_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x54) /* the crc error clear signal */ +#define CSR_HIPCIEC50_DL_REG_DFX_FSM_STATE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x58) /* DFX signal of FSM state */ +#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_STR_SEQ_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x5C) /* DFX the Seq_Num of start retry TLP */ +#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_STATUS_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x60) /* DFX signal of retry buffer read/write pointer */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_CTRL_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x64) /* apb read retry buffer address & start signal */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA0_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x68) /* apb read retry bufferdata DW0 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x6C) /* apb read retry bufferdata DW1 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x70) /* apb read retry bufferdata DW2 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA3_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x74) /* apb read retry bufferdata DW3 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA4_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x78) /* apb read retry bufferdata DW4 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA5_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x7C) /* apb read retry bufferdata DW5 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA6_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x80) /* apb read retry bufferdata DW6 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA7_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x84) /* apb read retry bufferdata DW7 */ +#define CSR_HIPCIEC50_DL_REG_DL_INT_STATUS_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x88) /* data link original intrrrupt */ +#define CSR_HIPCIEC50_DL_REG_DL_INT_MASK_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x8C) /* data link intrrrupt mask reg */ +#define CSR_HIPCIEC50_DL_REG_DL_INT_RO_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x90) /* DL block common interrupt after mask \ + */ +#define CSR_HIPCIEC50_DL_REG_DL_INT_SET_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x94) /* DL block common interrupt config by CPU */ +#define CSR_HIPCIEC50_DL_REG_INFINITE_CREDIT_EN_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x98) /* when the vc initial is infinite credit,whether send UpdateFC DLLP. */ +#define CSR_HIPCIEC50_DL_REG_TX_VEDNDOR_DLLP_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x9C) /* whether send vendor DLLP */ +#define CSR_HIPCIEC50_DL_REG_RX_VENDOR_DLLP_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xA0) +#define CSR_HIPCIEC50_DL_REG_SRAM_ECC_CFG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xA4) /* sram ecc configuration */ +#define CSR_HIPCIEC50_DL_REG_DFX_APB_READ_RETRY_DONE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0xA8) /* dl_dfx_apb_read_retry_done */ +#define CSR_HIPCIEC50_DL_REG_DFX_UPDATE_TIME_CYCLE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0xAC) /* dfx for update long req not gnt */ +#define CSR_HIPCIEC50_DL_REG_DFX_CRC_INSERT_ERROR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xB0) /* insert crc error for tx */ +#define CSR_HIPCIEC50_DL_REG_DFX_MAC_BP_TIMER_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0xB4) /* how long for mac give rdy when vld is high */ +#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_CNT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xB8) /* count retry timer */ +#define CSR_HIPCIEC50_DL_REG_FC_PH_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xBC) /* ph credit increasegap */ +#define CSR_HIPCIEC50_DL_REG_FC_PD_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xC0) /* pd credit increasegap */ +#define CSR_HIPCIEC50_DL_REG_FC_NPH_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xC4) /* nph credit increasegap */ +#define CSR_HIPCIEC50_DL_REG_FC_NPD_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xC8) /* npd credit increasegap */ +#define CSR_HIPCIEC50_DL_REG_FC_CPLH_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xCC) /* cplh credit increasegap */ +#define CSR_HIPCIEC50_DL_REG_FC_CPLD_CNT_CONFIG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xD0) /* cpld credit increasegap */ +#define CSR_HIPCIEC50_DL_REG_DL_MAC_RETRAIN_CNT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xD4) /* count retrain */ +#define CSR_HIPCIEC50_DL_REG_DL_MAC_RETRAIN_LIMIT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xD8) /* retrain limit */ +#define CSR_HIPCIEC50_DL_REG_INIT_FC_SEND_EN_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xDC) /* init fc send enable */ +#define CSR_HIPCIEC50_DL_REG_DFX_DLLP_RX_COUNT_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xE0) /* count rx dllp number */ +#define CSR_HIPCIEC50_DL_REG_DFX_DLLP_TX_COUNT_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xE4) /* count tx dllp number */ +#define CSR_HIPCIEC50_DL_REG_DFX_SEND_EN_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xE8) /* tx send enable */ +#define CSR_HIPCIEC50_DL_REG_DFX_SEQ_NUM_CHANGE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0xEC) /* is may change seqence number */ +#define CSR_HIPCIEC50_DL_REG_DFX_DLLP_TYPE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xF0) /* config dllp type */ +#define CSR_HIPCIEC50_DL_REG_DFX_RX_UPDATE_EN_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xF4) /* rx update dllp enable */ +#define CSR_HIPCIEC50_DL_REG_DFX_RX_NAK_COUNT_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xF8) /* count rx nak number */ +#define CSR_HIPCIEC50_DL_REG_DFX_RX_BAD_DLLP_TYPE_REG (CSR_HIPCIEC50_DL_REG_BASE + 0xFC) /* bad dllp type indicate */ +#define CSR_HIPCIEC50_DL_REG_DFX_ACKD_SEQ_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x100) /* indicate ackd_seq */ +#define CSR_HIPCIEC50_DL_REG_DFX_NEXT_TRANSMIT_SEQ_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x104) /* indicate next_transmit_seq */ +#define CSR_HIPCIEC50_DL_REG_DFX_NEXT_RCV_SEQ_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x108) /* indicate next_rcv_seq */ +#define CSR_HIPCIEC50_DL_REG_ECO_DL_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x118) /* add eco register */ +#define CSR_HIPCIEC50_DL_REG_TX_FEATURE_TIMER_CFG_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x11C) /* send feature dllp timeout */ +#define CSR_HIPCIEC50_DL_REG_DL_CORRECT_ERR_CNT_CFG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x120) /* correct error count */ +#define CSR_HIPCIEC50_DL_REG_DL_FC_UPDATE_MODE_SEL_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x124) /* dl_fc_update_mode_sel */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x128) /* the update timer for 2.5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x12C) /* the update timer for 5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G3_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x130) /* the update timer for 8GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G4_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x134) /* the update timer for 16GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x138) /* the update timer for 2.5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x13C) /* the update timer for 5GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G3_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x140) /* the update timer for 8GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G4_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x144) /* the update timer for 16GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_DL_INT_CE_NFE_SEL_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x148) /* Select the CE or NFE Type for Interrupt */ +#define CSR_HIPCIEC50_DL_REG_DL_NI_INT_RO_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x14C) /* The normal interrupt status for DL */ +#define CSR_HIPCIEC50_DL_REG_DL_FE_INT_RO_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x150) /* The fatal Error interrupt status for DL */ +#define CSR_HIPCIEC50_DL_REG_DL_CE_INT_RO_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x154) /* The correctable Error interrupt status for DL */ +#define CSR_HIPCIEC50_DL_REG_DL_NFE_INT_RO_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x158) /* The nonfatal Error interrupt status for DL */ +#define CSR_HIPCIEC50_DL_REG_DL_FC_INIT_ERR_STATUS_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x15C) /* data link layer fc init timeout err status */ +#define CSR_HIPCIEC50_DL_REG_DFX_RETRY_DATA_BUFFER_STATUS_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x160) /* DFX signal of retry buffer read/write pointer */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_G5_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x164) /* the ack transmission latency limit for 32GT/s mod */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_20G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x168) /* the ack transmission latency limit for 20GT/s mod */ +#define CSR_HIPCIEC50_DL_REG_ACK_LATENCY_CYCLE_25G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x16C) /* the ack transmission latency limit for 25GT/s mod */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_G5_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x170) /* the update timer for 32GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_20G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x174) /* the update timer for 20GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_25G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x178) /* the update timer for 25GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_G5_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x17C) /* the update timer for 32GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_20G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x180) /* the update timer for 20GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_25G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x184) /* the update timer for 25GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_G5_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x188) /* the update timer for 32GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_20G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x18C) /* the update timer for 20GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_25G_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x190) /* the update timer for 25GT/s mode */ +#define CSR_HIPCIEC50_DL_REG_DFX_DLCMSM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x194) /* dlcmsm dfx register */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA8_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x19C) /* apb read retry bufferdata DW8 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA9_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x200) /* apb read retry bufferdata DW9 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA10_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x204) /* apb read retry bufferdata DW10 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA11_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x208) /* apb read retry bufferdata DW11 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA12_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x20C) /* apb read retry bufferdata DW12 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA13_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x210) /* apb read retry bufferdata DW13 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA14_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x214) /* apb read retry bufferdata DW14 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_RETRY_DATA15_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x218) /* apb read retry bufferdata DW15 */ +#define CSR_HIPCIEC50_DL_REG_DFX_APB_READ_CONTEXT_DONE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x21C) /* dl_dfx_apb_read_context_done */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_CTRL_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x220) /* apb read context buffer address & start signal */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_DATA0_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x224) /* apb read context buffer data DW0 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_DATA1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x228) /* apb read context buffer data DW1 */ +#define CSR_HIPCIEC50_DL_REG_APB_READ_CONTEXT_DATA2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x22C) /* apb read context buffer data DW2 */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_SRAM_ECC_CFG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x230) /* sram ecc configuration */ +#define CSR_HIPCIEC50_DL_REG_DATA_RAM1_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x234) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_DATA_RAM2_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x238) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_DATA_RAM3_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x23C) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM_ECC_ERR_CNT_1BIT_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x240) /* ECC error occur count */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM_ECC_ERR_CNT_2BIT_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x244) /* ECC error occur count */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM0_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x248) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM1_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x24C) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM2_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x250) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_CONTEXT_RAM3_ECC_ERR_ADDR_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x254) /* ECC error address */ +#define CSR_HIPCIEC50_DL_REG_RAM_ECC_ERR_INT_SEL_IND_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x258) /* ecc error ram select \ + */ +#define CSR_HIPCIEC50_DL_REG_INSERT_IDLE_FSM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x25C) /* insert idle fsm state */ +#define CSR_HIPCIEC50_DL_REG_DFX_MAC_ERR_NUM_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x260) /* the mac2dl error number */ +#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X1_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x264) /* retry buffer full waterline control */ +#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X2_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x268) /* retry buffer full waterline control */ +#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X4_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x26C) /* retry buffer full waterline control */ +#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X8_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x270) /* retry buffer full waterline control */ +#define CSR_HIPCIEC50_DL_REG_RETRY_BUFFER_WATERLINE_X16_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x274) /* retry buffer full waterline control */ +#define CSR_HIPCIEC50_DL_REG_DFX_ACK_FFFH_INITAL_MASK_DISABLE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x278) /* disable ack_fffh_inital_mask */ +#define CSR_HIPCIEC50_DL_REG_DFX_TX_DLLPG_REG (CSR_HIPCIEC50_DL_REG_BASE + 0x27C) /* dfx for TX_DLLPG */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_P_CYCLE_IDLE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x280) /* tx fc update p cycle idle */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_NP_CYCLE_IDLE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x284) /* tx fc update np cycle idle */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CPL_CYCLE_IDLE_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x288) /* tx fc update cpl cycle idle */ +#define CSR_HIPCIEC50_DL_REG_TX_FC_UPDATE_CYCLE_ALL_IDLE_EN_REG \ + (CSR_HIPCIEC50_DL_REG_BASE + 0x28C) /* tx fc update cycle all idle en */ + +/* HIPCIEC50_MAC_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_MAC_REG_BASE (0x70000) + +/* **************************************************************************** */ +/* HIPCIEC50_MAC_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_EIOS_TO_ELEIDLE_DELAY_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x0) /* Receive EIOS to phy_eleidle delay */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ENTER_LOOPBACK_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4) /* LTSSM enter loopback mode enable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RETRAIN_LINK_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x8) /* retrain link enable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_TX_LINK_NUM_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0xC) /* setting TX Link number advertising to Link parter when being as DS port. */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_SCRAMBLE_DISABLE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x10) /* scramble disable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVAL_SRIS_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x14) /* SKP interval in SRIS mode */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DC_BALANCE_DISABLE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x18) /* DC balance funciton disanle */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_DISABLE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x1C) /* TX EQ function disable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SUPPORTED_TX_PRESET_BM_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x20) /* TX EQ supported tx preset bit map */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_8G_PHY_EQ_FB_SEL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x24) /* PHY 8G TX EQ feedback mode sel */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_TX_COEFF_MAP_MODE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x28) /* TX coeff mapping mode */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_PHASE23_CONV_STEP_ADDR_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + \ + 0x2C) /* TX EQ convergence steps reqired when in TX_EQ2 (US port) or TX_EQ3 (DS port) */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_PHASE23_TIMEOUT_VAL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x30) /* TX EQ timeout value for TX_EQ phase2 and phase3, unit (ms) */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVAL_SRNS_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x34) /* SKP interval in SRNS mode */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_N_FTS_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x38) /* number of FTS need to be transmit during L0s back to L0 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PHYSTATUS_DET_TIMEOUT_VAL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C) /* phystatus detection timeout value */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RDN_CROSS_TIMEOUT_VAL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x40) /* Random cross timeout value */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SEL_DEEMPH_US_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x44) /* sel_deemph for Upstream port */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TX_COMP_RCV_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x48) /* transmit complaince receive */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TXSWING_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4C) /* Tx swing selection */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_INPUT_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x50) /* LTSSM tracer input */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_STATUS_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x54) /* Interrupt status */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_MASK_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x58) /* interrupt mask */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TEST_COUNTER_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x5C) /* test counter set */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LINK_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x60) /* mac link information */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x64) /* debug PIPE signal set1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x68) /* debug PIPE signal set2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x6C) /* debug PIPE signal set3 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x70) /* debug PIPE signal set4 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_RXDLI_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x74) /* debug RXDLI signal */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x78) /* debug_link_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x7C) /* debug_lane_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_TXDLI_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x80) /* debug TXDLI */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_OUTPUT_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x84) /* LTSSM tracer output */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_LAST_ADDR_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x88) /* LTSSM tracer last write address */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SYMBOL_UNLOCL_COUNTER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x8C) /* symbol_unlock_counter */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_RO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x90) /* Interrupt status RO */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_MAC_INT_SET_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x94) /* interrupt sets */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ENTER_L1L2_TIMEOUT_VAL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x98) /* enter L1L2 state timeout */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_FIX_LP_TX_PRESET_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x9C) /* Tx EQ pahse fix link partner preset */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ADJ_HILINK_MODE_EN_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0xA0) /* adjust hilink SERDES function mode enable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN3_TX_PRESET_P1_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0xA4) /* tx preset value latched in GEN3 P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_OPT_TX_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0xA8) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LOOPBACK_PRESET_TIMEOUT_VAL_ADDR_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0xAC) /* P2 or P3 wait for tx preset loopback timeout value */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_COMP_OPTION_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xB0) /* Compliance option */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PHY_RXDATA_TS_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xB4) /* PIPE RX data */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ECO_RSV0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xB8) /* ECO reserve register 0 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ECO_RSV1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xBC) /* ECO reserve register 1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REGEQ_TRACE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xC0) /* mac_eq_trace_reg */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_TIMEOUT_SET_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xC4) /* mac_eq_timeout_reg */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_EQ_INIT_COEFF_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0xC8) /* eq_init_coeff_cfg \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_WAIT_LINK_NUM_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0xCC) /* mac_wait_link_num_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x100) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x104) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x108) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_3_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x10C) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_4_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x110) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_5_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x114) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_6_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x118) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_1_7_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x11C) /* Lane0～lane7 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x200) /* Preset0 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x204) /* Preset1 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x208) /* Preset2 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x20C) /* Preset3 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x210) /* Preset4 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET5_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x214) /* Preset5 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET6_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x218) /* Preset6 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET7_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x21C) /* Preset7 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET8_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x220) /* Preset8 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET9_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x224) /* Preset9 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET10_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x228) /* Preset10 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET11_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x22C) /* Preset11 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET12_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x230) /* Preset12 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET13_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x234) /* Preset13 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET14_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x238) /* Preset14 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PRESET15_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x23C) /* Preset15 coeff for Lane */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE5_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x240) /* debug PIPE signal set5 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE6_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x244) /* debug PIPE signal set6 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE7_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x248) /* debug PIPE signal set7 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE8_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x24C) /* debug PIPE signal set8 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE9_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x250) /* debug PIPE signal set9 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE10_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x254) /* debug PIPE signal set10 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_PIPE11_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x258) /* debug PIPE signal set11 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_RXDLI_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x25C) /* debug RXDLI signal */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x260) /* debug_link_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x264) /* debug_link_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LINK_NUM_4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x268) /* debug_link_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x26C) /* debug_lane_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x270) /* debug_lane_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DEBUG_LANE_NUM_4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x274) /* debug_lane_num */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN3_TX_PRESET_P1_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x278) /* tx preset value latched in GEN3 P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_EQ_OPT_TX_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x27C) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x280) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x284) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x288) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_3_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x28C) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_4_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x290) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_5_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x294) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_6_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x298) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LANE_COEFF_2_7_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x29C) /* Lane 8 ～ lane 15 Transmitter equalizer coeff */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_OUTPUT_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2A0) /* LTSSM tracer output */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_OUTPUT_OK_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2A4) /* LTSSM tracer output */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_SRAM_ECC_INSERT_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2A8) /* LTSSM tracer output */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACER_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2AC) /* LTSSM tracer output */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_COEFF_SEARCH_TRACER_OUTPUT_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2B0) /* COEFF_SEARCH tracer output */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_REMOTE_FS_LF_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2B4) /* REMOTE_PHY_FS_LF */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LOOP_LINK_DATA_ERR_COUNT_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2B8) /* loopback_link_data_err_count */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PCS_RX_ERR_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2BC) /* pcs_rx_err_cnt */ +#define CSR_HIPCIEC50_MAC_REG_MAC_UP_MAX_AUTO_REDO_NUM_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2C0) /* up_max_auto_redo_number */ +#define CSR_HIPCIEC50_MAC_REG_MAC_WAIT_LANE_NUM_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2C4) /* mac_wait_lane_num_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LANE_NUM_WAIT_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2C8) /* mac_lane_num_wait_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LANE_NUM_ACC_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2CC) /* mac_lane_num_acc_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LNW_TO_LNA_1MS_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2D0) /* mac_lnw_to_lna_1ms_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_EQ_LTSMM_HOLD_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2D4) /* mac_eq_ltssm_hold_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_CRTL_INFER_ELECIDLE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2D8) /* mac_ltssm_ctrl_infer_elecidle */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_TRACER_CFG0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2DC) /* mac_ltssm_tracer_cfg0 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_TRACER_CFG1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2E0) /* mac_ltssm_tracer_cfg1 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CMP_LOOP_SENT_EQTS1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2E8) /* mac_cmp_loop_sent_eq_ts */ +#define CSR_HIPCIEC50_MAC_REG_MAC_ENTER_LPBK_DISABLE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2EC) /* mac_enter_lpbk_disable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PRESET_TABLE0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2F0) /* mac_preset_table0 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PRESET_TABLE1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2F4) /* mac_preset_table1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_TRACERADDR_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x2F8) /* LTSSM tracer addr \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_COMPLETE_TIMER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x2FC) /* maccfg_complete_timer */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_COMP_ERRATA_DISABLE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x300) /* comp_errata_disable */ +#define CSR_HIPCIEC50_MAC_REG_MAC_RX_ERR_CHECK_EN_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x304) /* mac_rx_error_check_en */ +#define CSR_HIPCIEC50_MAC_REG_MAC_TRACE_2BIT_ECC_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x308) /* mac_ecc_2bit_er_cnt \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_TRACE_1BIT_ECC_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x30C) /* mac_ecc_1bit_er_cnt \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_HOLD_EN_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x310) /* mac_rcv_hold_en */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_LOCK_HOLD_TIME_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x314) /* mac_rcv_lock_hold_time */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_CFG_HOLD_TIME_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x318) /* mac_rcv_cfg_hold_time */ +#define CSR_HIPCIEC50_MAC_REG_MAC_CFG_RCV_IDLE_HOLD_TIME_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x31C) /* mac_rcv_idle_hold_time */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_INT_STATUS_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x320) /* mac_ltssm_int_match_state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_DESKEW_SYMBOL_UNLOCK_RCV_MASK_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x324) /* mac_deskew_symbol_unlock_recovery_mask */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_OPT_TX_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x328) /* TX GNE4 EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_OPT_TX_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x32C) /* TX GEN4 EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN4_TX_PRESET_P1_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x330) /* tx preset value latched in GEN4 P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LP_GEN4_TX_PRESET_P1_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x334) /* tx preset value latched in GEN4 P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LPBK_DATA_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x338) /* Tx data in loopback state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_RX_MARGIN_SELF_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x33C) /* mac_reg_margn_sel_ctrl */ +#define CSR_HIPCIEC50_MAC_REG_MAC_RX_MARGIN_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x340) /* mac_rx_margin_cfg */ +#define CSR_HIPCIEC50_MAC_REG_GEN4_RX_MARGIN_CPA0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x344) /* gen4_rx_margin_cap0 */ +#define CSR_HIPCIEC50_MAC_REG_GEN4_RX_MARGIN_CPA1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x348) /* gen4_rx_margin_cap1 */ +#define CSR_HIPCIEC50_MAC_REG_GEN4_RX_MARGIN_RSV_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x34C) /* resvered for rx margin */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_EQ_FIX_TX_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x350) /* TX GNE3 EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN3_EQ_FIX_TX_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x354) /* TX GNE3 EQ fix TX PRESETvalue2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_FIX_TX_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x358) /* TX GNE4 EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_GEN4_EQ_FIX_TX_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x35C) /* TX GNE4 EQ fix TX PRESETvalue2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x360) /* MAC_REG_PHASE01_COARSETUNE_START_TM_VALUE */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LTSSM_TIMEOUT_ENABLE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x364) /* LTSSM_TIMEOUT_ENABLE */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LOOPBACK_EC_VALUE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x368) /* MAC_LOOPBACK_EC_VALUE \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LANE_REVERSE_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x36C) /* MAC_LANE_REVERSE_CFG */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x370) /* MAC_PIPE_SRIS_EN_CFG */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_EBUF_MODE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x374) /* MAC_PIPE_EBUF_MODE_CFG */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x378) /* MAC_EBUF_DEPTH_CFG0 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x37C) /* MAC_EBUF_DEPTH_CFG1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x380) /* MAC_EBUF_DEPTH_CFG2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PIPE_SRIS_EN3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x384) /* MAC_EBUF_DEPTH_CFG3 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_FRAMING_ERR_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x39C) /* MAC_FRAMING_ERR_CNT */ +#define CSR_HIPCIEC50_MAC_REG_MAC_FRAMING_ERR_CTRL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3A0) /* MAC_FRAMING_ERR_CTRL */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LINKDOWN_REQ_MASK_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3A4) /* MAC_LINKDOWN_REQ_MASK \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_INT_TYPE_SEL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3A8) /* MAC_INT_TYPE_SEL */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REQ_COEFF_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3AC) /* MAC_REQ_COEFF_INFO */ +#define CSR_HIPCIEC50_MAC_REG_MAC_RX_COEFF_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3B0) /* MAC_RX_COEFF_INFO */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LEAVE_L0_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3B4) /* MAC_LEAVE_L0_INFO */ +#define CSR_HIPCIEC50_MAC_REG_MAC_GEN4_LOW_SKP_CFG_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3B8) /* MAC_GEN4_LOW_SKP_CFG */ +#define CSR_HIPCIEC50_MAC_REG_DFX_APB_LANE_ERROR_STATUS_0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3BC) /* DFX_APB_LANE_ERROR_STATUS_0 */ +#define CSR_HIPCIEC50_MAC_REG_DFX_APB_LANE_ERROR_STATUS_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C0) /* DFX_APB_LANE_ERROR_STATUS_1 */ +#define CSR_HIPCIEC50_MAC_REG_REG_FIX_LP_8G_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C4) /* REG_FIX_LP_8G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_REG_FIX_LP_16G_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3C8) /* REG_FIX_LP_16G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_REG_RXIDLE_DELAY_TIME_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x3CC) /* REG_RXIDLE_DELAY_TIME \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_16G_PHY_EQ_FB_SEL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3D0) /* PHY 16G TX EQ feedback mode sel */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TX_MARGIN_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3D4) /* mac_reg_tx_margin_ctrl */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_8GT_EQTS2_PRESET_0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3D8) /* TX PRESET value in UP 8GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_8GT_EQTS2_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3DC) /* TX PRESET value in UP 8GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_REG_RXVALID_DELAY_TIME_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3E0) /* REG_RXVALID_DELAY_TIME */ +#define CSR_HIPCIEC50_MAC_REG_MAC_INT_CE_NFE_SEL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3E4) /* Select the CE or NFE Type for Interrupt */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_NI_INT_RO_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3E8) /* The normal interrupt status for MAC */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FE_INT_RO_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3EC) /* The fatal Error interrupt status for MAC */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_CE_INT_RO_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3F0) /* The correctable Error interrupt status for MAC */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_NFE_INT_RO_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3F4) /* The nonfatal Error interrupt status for MAC */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_16G_EQTS2_PRESET_0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x3FC) /* TX PRESET value in UP 16GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_16G_EQTS2_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x400) /* TX PRESET value in UP 16GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_20G_EQTS2_PRESET0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x404) /* TX PRESET value in UP ESM_20GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_20G_EQTS2_PRESET1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x408) /* TX PRESET value in UP USM_20GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_25G_EQTS2_PRESET0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x40C) /* TX PRESET value in UP USM_25GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_UP_TX_ESM_25G_EQTS2_PRESET1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x410) /* TX PRESET value in UP USM_25GT EQ TS2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_20G_TX_PRESET_VALUE0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x414) /* TX ESM_20G EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_20G_TX_PRESET_VALUE1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x418) /* TX ESM_20G EQ fix TX PRESET value2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_25G_TX_PRESET_VALUE0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x41C) /* TX ESM_25G EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_ESM_25G_TX_PRESET_VALUE1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x420) /* TX ESM_25G EQ fix TX PRESET value2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_32G_TX_PRESET_VALUE0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x424) /* TX 32G EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_32G_TX_PRESET_VALUE1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x428) /* TX 32G EQ fix TX PRESET value2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_56G_TX_PRESET_VALUE0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x42C) /* TX 56G EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_56G_TX_PRESET_VALUE1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x430) /* TX 56G EQ fix TX PRESET value2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_64G_TX_PRESET_VALUE0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x434) /* TX 64G EQ fix TX PRESET value1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_FIX_64G_TX_PRESET_VALUE1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x438) /* TX 64G EQ fix TX PRESET value2 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVL_GEN5_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x43C) /* GEN5 SKP interval in SRNS and SRIS mode */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVL_GEN6_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x440) /* GEN6 SKP interval in SRNS and SRIS mode */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_SKP_INTVL_GEN7_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x444) /* GEN7 SKP interval in SRNS and SRIS mode */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_20G_EQ_FIX_LP_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x448) /* REG_FIX_LP_ESM_20G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_25G_EQ_FIX_LP_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x44C) /* REG_FIX_LP_ESM_25G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_32G_EQFIX_LP_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x450) /* REG_FIX_LP_32G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_56G_EQ_FIX_LP_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x454) /* REG_FIX_LP_56G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_64G_EQ_FIX_LP_TX_COEFF_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x458) /* REG_FIX_LP_64G_TX_COEFF */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_20G_LINK_EQ_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x45C) /* MAC REG LINK EQ CTRL in ESM_20GT/s */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_25G_LINK_EQ_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x460) /* MAC REG LINK EQ CTRL in ESM_25GT/s */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_32G_LINK_EQ_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x464) /* MAC REG LINK EQ CTRL in 32GT/s */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_56G_LINK_EQ_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x468) /* MAC REG LINK EQ CTRL in 56GT/s */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_64G_LINK_EQ_CTRL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x46C) /* MAC REG LINK EQ CTRL in 64GT/s */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_20G_EQ_FIX_LP_TX_PRESET_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x470) /* Tx EQ pahse fix link partner preset */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_25G_EQ_FIX_LP_TX_PRESET_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x474) /* Tx EQ pahse fix link partner preset */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_32G_EQ_FIX_LP_TX_PRESET_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x478) /* Tx EQ pahse fix link partner preset */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_56G_EQ_FIX_LP_TX_PRESET_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x47C) /* Tx EQ pahse fix link partner preset */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ESM_64G_EQ_FIX_LP_TX_PRESET_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x480) /* Tx EQ pahse fix link partner preset */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_20G_TX_PRESET_P1_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x484) /* tx preset value latched in ESM_20G P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_20G_TX_PRESET_P1_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x488) /* tx preset value latched in ESM_20G P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_25G_TX_PRESET_P1_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x48C) /* tx preset value latched in ESM_25G P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LP_ESM_25G_TX_PRESET_P1_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x490) /* tx preset value latched in ESM_25G P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LP_GEN5_TX_PRESET_P1_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x494) /* tx preset value latched in GEN5 P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_LP_GEN5_TX_PRESET_P1_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x498) /* tx preset value latched in GEN5 P1 state */ +#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_20G_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4A4) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_20G_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4A8) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_25G_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4AC) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_ESM_25G_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4B0) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_GEN5_PRESET_1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4B4) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_OPT_GEN5_PRESET_2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4B8) /* TX EQ opimal TX PRESET result */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_DFX_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4D0) /* LTSSM DFX */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_ALTERNATE_PROTOL_VENDER_ID_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4D4) /* VENDER ID FOR ALTERNATE_PROTOL */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_TS_MESSAGE_VENDER_ID_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4D8) /* VENDER ID FOR TS_MESSAGE */ +#define CSR_HIPCIEC50_MAC_REG_MAC_HILINK_INFO_DFX_1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4DC) +#define CSR_HIPCIEC50_MAC_REG_MAC_HILINK_INFO_DFX_2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4E0) +#define CSR_HIPCIEC50_MAC_REG_MAC_HILINK_INFO_DFX_3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4E4) +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PLL_CTRL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x4E8) /* MAC PLL CTRL */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_USE_FIX_CORE_CLK_EN_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4EC) /* MAC CORE CLK SELECT FROM PLL OR HILINK MCLK32B */ +#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4F8) /* EBUFFER_UPDATE_FREQUENCY FOR LANE0~LANE3 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x4FC) /* EBUFFER_UPDATE_FREQUENCY FOR LANE4~LANE7 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY2_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x500) /* EBUFFER_UPDATE_FREQUENCY FOR LANE8~LANE11 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_EBUFFER_UPDATE_FREQUENCY3_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x504) /* EBUFFER_UPDATE_FREQUENCY FOR LANE12~LANE15 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_PIPE_MODE_SEL_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x508) /* PIPE MODE SEL MESSAGEBUS OR PIN */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_DFX_LANE_ID_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x50C) /* RPT MBUS DFX LANE ID */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_DFX0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x510) /* MBUS DFX0 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_DFX1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x514) /* MBUS DFX1 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RPT_MBUS_ERR_CNT_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x518) /* MBUS ERR CNT */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LCFSLF_USE_TXSTATUS_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x51C) /* LOCAL FS/LF USE TXSTATUS OR RXSTATUS */ +#define CSR_HIPCIEC50_MAC_REG_MAC_PRECODING_CTRL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x520) +#define CSR_HIPCIEC50_MAC_REG_MAC_RX_TERMATION_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x524) +#define CSR_HIPCIEC50_MAC_REG_MAC_POWERDOWN_VALUE_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x528) +#define CSR_HIPCIEC50_MAC_REG_MAC_CLK_SW_TM_VAL_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x52C) +#define CSR_HIPCIEC50_MAC_REG_MAC_TXELEIDLE_TM_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x530) +#define CSR_HIPCIEC50_MAC_REG_MAC_TARGET_LINK_WIDTH_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x534) +#define CSR_HIPCIEC50_MAC_REG_MAC_LPBK_WAIT_TIME_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x538) +#define CSR_HIPCIEC50_MAC_REG_MAC_LPBK_DFX_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x53C) +#define CSR_HIPCIEC50_MAC_REG_TX_DLI_DEBUG_INFO_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x540) +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_DESKEW_UNLOCL_COUNTER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x544) /* deskew_unlock_counter */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_RX_TSBUF_RESET_COUNTER_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x548) /* rxts_buf_reset_counter */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE0_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x54C) /* ltssm_internal_value0 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x550) /* ltssm_internal_value1 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE2_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x554) /* ltssm_internal_value2 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE3_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x558) /* ltssm_internal_value3 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE4_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x55C) /* ltssm_internal_value4 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE5_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x560) /* ltssm_internal_value5 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE6_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x564) /* ltssm_internal_value6 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE7_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x568) /* ltssm_internal_value7 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE8_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x56C) /* ltssm_internal_value8 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE9_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x570) /* ltssm_internal_value9 \ + */ +#define CSR_HIPCIEC50_MAC_REG_MAC_REG_LTSSM_VALUE10_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x574) /* ltssm_internal_value10 */ +#define CSR_HIPCIEC50_MAC_REG_MAC_P10_COEFF_HALF_RATE_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x578) /* mac_p10_coeff_half_rate */ +#define CSR_HIPCIEC50_MAC_REG_MAC_RCV_EIOS_TO_ELEIDLE_DLY_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x57C) /* mac_rcv_eios_to_eleidle_delay */ +#define CSR_HIPCIEC50_MAC_REG_GEN5_PHY_CAP_REG0_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x580) /* Gen5 Transmitted modify TS Data1 register */ +#define CSR_HIPCIEC50_MAC_REG_GEN5_PHY_CAP_REG1_REG \ + (CSR_HIPCIEC50_MAC_REG_BASE + 0x584) /* Gen5 Transmitted modify TS Data2 register */ +#define CSR_HIPCIEC50_MAC_REG_MAC_COEFF_TRACER_CFG1_REG (CSR_HIPCIEC50_MAC_REG_BASE + 0x588) /* mac_coeff_tracer_cfg1 \ + */ + +/* HIPCIEC50_TL_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TL_REG_BASE (0x20000) + +/* **************************************************************************** */ +/* HIPCIEC50_TL_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_TL_REG_TL_TX_CTRL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x0) /* Transaction Layer transmission control */ +#define CSR_HIPCIEC50_TL_REG_TL_ENGIEN_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x4) /* tl tx status registers */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CHECK_EN_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x8) /* Error detct optional checker enable */ +#define CSR_HIPCIEC50_TL_REG_LTR_REQUIRE_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xC) /* device LTR require */ +#define CSR_HIPCIEC50_TL_REG_LTR_MSG_CTRL_STATUS_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x10) /* LTR message transmit control and status */ +#define CSR_HIPCIEC50_TL_REG_TX_CRD_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x14) /* TL_TX credit control signals */ +#define CSR_HIPCIEC50_TL_REG_PM_NPD_CDT_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x1C) /* PM NPD credit control */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_WRR_WEIGHT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x24) /* TL_TX P/NP/CPL transmission weight in WRR arbiter */ +#define CSR_HIPCIEC50_TL_REG_TL_PORT_IDLE_CTRL_STATUS_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x28) /* TL port idle control and staus */ +#define CSR_HIPCIEC50_TL_REG_TL_CFG_ACCESS_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xFC) /* Cfgspace APB access ctrl \ + */ +#define CSR_HIPCIEC50_TL_REG_TL_ASPM_IDLE_CNT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x100) /* ASPM self-launch control register */ +#define CSR_HIPCIEC50_TL_REG_TL_ASPM_IDLE_EN_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x104) /* ASPM self-launch control register */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_DC_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x108) /* Power management DC control */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_STATE_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x10C) /* Power management state */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_UC_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x114) /* Power management RX control */ +#define CSR_HIPCIEC50_TL_REG_TL_ENTER_L0_CTRL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x118) /* Power management wake up control */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_TIMEOUT_CTRL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x11C) /* Power management timeout control */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_CTRL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x120) /* PM L1 substate control registers */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_TIME_CFG0_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x124) /* The TIMEOUT VALUE configuration of L1 substate */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_TIME_CFG1_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x128) /* DFE timeout value of PM */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_ODR_CTRL_MODE_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x200) /* TL_RX ODR_CTRL_MODE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PFX_FILTER_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x210) /* Filter prefix in error detect */ +#define CSR_HIPCIEC50_TL_REG_SYSTEM_ERR_OVERRIDE_CONTROL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x4E4) /* SYSTEM ERROR CONTROL REGISTER FOR ROOT PORT */ +#define CSR_HIPCIEC50_TL_REG_TL_CFG_HCK_EN_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x4E8) /* Control the RW/RO attributes of HCK warning register */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_STATUS0_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x56C) /* TL interrupt status0 */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_STATUS1_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x570) /* TL interrupt status1 */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_MASK0_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x574) /* transaction layer tx interrupt mask */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_SET0_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x578) /* transaction layer tx interrupt set register */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_RO0_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x57C) /* transaction layer tx interrupt indicater status */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_MASK1_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x580) /* transaction layer tx interrupt mask */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_SET1_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x584) /* transaction layer tx interrupt set register */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_RO1_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0x588) /* transaction layer tx interrupt indicater status */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_SEL0_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x590) /* CE and NFE select signal */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_CE_RO_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x594) /* CE interrupt status */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_NFE_RO_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x598) /* NFE interrupt status */ +#define CSR_HIPCIEC50_TL_REG_TL_INT_FE_RO_REG (CSR_HIPCIEC50_TL_REG_BASE + 0x59C) /* FE interrupt status */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_DFX_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA00) /* TL_TX DFX ontrol signals */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_SYNC_FIFO_ST_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA04) /* TL TX SYNC FIFO Status */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_WHOLE_TLP_HED_VLD_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA08) /* TL TX SYNC FIFO Status */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_UR_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA0C) /* TL TX UR error counter */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC0_P_FC_LEFT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA10) /* VC0 P header and data flow credit left valud */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC0_NP_FC_LEFT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA14) /* VC0 NP header and data flow credit left valud */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC0_CPL_FC_LEFT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA18) /* VC0 CPL header and data flow credit left valud */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC1_P_FC_LEFT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA1C) /* CCIX VC P header and data flow credit left valud */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_TC_MAPERR_TC_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA20) /* when TC map VC is error, remembor the error TLP's TC. */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_CC_SCAL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA24) /* TL_TX flow control credit consume and scale */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_INF_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA28) /* TL_TX flow control infinite credit indicator */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_ORDER_P_NUM_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA2C) /* TL_TX ordering P TLP range number and send number */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_ORDER_NP_CPL_NUM_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA30) /* TL_TX ordering NP or CPL TLP range number and P TLP send number */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_NP_CPL_CRD_USED_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA34) /* TL_TX CPL credit used counter */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_LOC_CRD_LIMIT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA38) /* P/NP/CPL header and data local credit limit */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_VC_COM_CRD_CC_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA3C) /* P/NP/CPL header and data link and local credit consume */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_TAG_USED_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA40) /* PORT tag used counter */ +#define CSR_HIPCIEC50_TL_REG_TL_CFGSPACE_BDF_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA44) /* TL CFGSPACE BUS NUMBER AND DEVICE NUMBER */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_LTR_MSG_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xA48) /* TL TX UR error counter */ +#define CSR_HIPCIEC50_TL_REG_TL_TX_SYNC_FIFO_OVERFLOW_STS_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xA4C) /* TLTX SYNC FIFO OVERFLOW */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_VC0_POST_CREDIT_LEFT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB00) /* VC0_POST_CREDIT */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_VC0_NONPOST_CREDIT_LEFT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB04) /* VC0_NONPOST_CREDIT */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_VC0_CPL_CREDIT_LEFT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB08) /* VC0_CPL_CREDIT */ +#define CSR_HIPCIEC50_TL_REG_RX_RX_BUFFER_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB18) /* RX BUFFER FIFO STATUS */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_POSTED_CREDIT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB1C) /* TL RX CREDIT POSTED TLP INITIAL SIZE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_NON_POSTED_CREDIT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB20) /* TL RX CREDIT NON_POSTED TLP INITIAL SIZE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CREDIT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB24) /* TL RX CREDIT CPL TLP INITIAL SIZE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CDT_INI_UP_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB28) /* TL RX CREDIT reconfigure enable */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_ERR_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB2C) /* RX Error counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_NULL_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB30) /* RX null/dl Error counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_UR_TLP_CNT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB34) /* RX received tlp is UR counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_TOTAL_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB38) /* RX received total tlp counter \ + */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_TOTAL_TR_CNT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB3C) /* RX total sending tlps counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_DROP_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB40) /* RX drop tlps counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_POST_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB44) /* RX post tlp counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_NONPOST_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB48) /* RX non-post tlp counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB4C) /* RX completion tlp counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_LOC_TLP_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB50) /* RX Local hit TLP counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX0_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB58) /* TL RX DFX 0 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX1_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB5C) /* TL RX DFX 1 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX2_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB60) /* TL RX DFX 2 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX3_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB64) /* TL RX DFX 3 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX4_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB68) /* TL RX DFX 4 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX5_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB6C) /* TL RX DFX 5 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX6_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB70) /* TL RX DFX 6 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX7_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB74) /* TL RX DFX 7 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_PORT_DFX8_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB78) /* TL RX DFX 8 */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_POSTED_CREDIT_DF_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB88) /* TL RX CREDIT POSTED TLP INITIAL SIZE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_NON_POSTED_CREDIT_DF_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB8C) /* TL RX CREDIT NON_POSTED TLP INITIAL SIZE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CREDIT_DF_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB90) /* TL RX CREDIT CPL TLP INITIAL SIZE */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CDT_INI_UP_DF_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB94) /* TL RX CREDIT reconfigure enable */ +#define CSR_HIPCIEC50_TL_REG_RX_ASYN_STONE_FIFO_STATUS_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xB98) /* The asyn and stone fifo of tl rx */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_ERR_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xB9C) /* TL RX ERROR STATUS */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_ECC_ERROR_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBA0) /* tl rx ecc error status \ + */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_BP_CTRL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBA4) /* tl rx back preture signal */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_ECC_1BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBA8) /* TL RX 1bit ECC Error counter */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_ECC_1BIT_ERR_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBAC) /* TL ecc 1bit error report */ +#define CSR_HIPCIEC50_TL_REG_TL_ECC_2BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBB0) /* RX buffer 2bit ECC Error counter */ +#define CSR_HIPCIEC50_TL_REG_TL_ECC_2BIT_ERR_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBB4) /* tl rx buffer ecc 2bit error report */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_INSERT_ECC_ERR_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBB8) /* tl rx insert ECC error */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_POSTED_CREDIT_WATERLINE_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBBC) /* tl rx credit waterline configuration */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_NPOSTED_CREDIT_WATERLINE_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBC0) /* tl rx credit waterline configuration */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CPL_CREDIT_WATERLINE_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBC4) /* tl rx credit waterline configuration */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_DL_L2_GNT_TIME_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBC8) /* The TIMEOUT VALUE configuration of L2 for dl response gnt */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_DL_L1_GNT_TIME_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBCC) /* The TIMEOUT VALUE configuration of L1 for dl response gnt */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_DL_L0S_GNT_TIME_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBD0) /* The TIMEOUT VALUE configuration of L0S for dl response gnt */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_L1SUBSTATE_REFCLK_STABEL_TIME_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBD4) /* The reclk stable TIME VALUE for L1 substate */ +#define CSR_HIPCIEC50_TL_REG_PM_STATUS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBD8) /* power management dfx */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_LASTACK_TIME_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBDC) /* The TIMEOUT VALUE configuration for dl clean retry_buffer */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_LTR_LATTENCY_RCV_DFX_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBE0) /* the LTR latency VALUE received in RC mode for DFX */ +#define CSR_HIPCIEC50_TL_REG_PM_STATUS_FIFO_CONTROL_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBE4) /* the fifo control of pm state */ +#define CSR_HIPCIEC50_TL_REG_PM_STATUS1_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xBE8) /* power management dfx */ +#define CSR_HIPCIEC50_TL_REG_PM_CLKCHANGE_REQ_TIME_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBEC) /* the time value that the pm2crg_clkchange_req must be stay in valid */ +#define CSR_HIPCIEC50_TL_REG_PM_CLKCHANGE_GNT_TIME_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBF0) /* the max time value that the clk must be change from low freq to normal \ + freq after the negedge of pm2crg_clkchange_req */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_BLK_TLP_GNT_TIME_CFG_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBF4) /* The TIMEOUT VALUE configuration of blk tlp for tl response gnt */ +#define CSR_HIPCIEC50_TL_REG_DOE_CAP_CRS_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBF8) /* DOE capability control status register */ +#define CSR_HIPCIEC50_TL_REG_DOE_CAP_RD_DAT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xBFC) /* Local cpu read message from DOE capability */ +#define CSR_HIPCIEC50_TL_REG_DOE_CAP_WR_DAT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC00) /* Local cpu write response message into this register */ +#define CSR_HIPCIEC50_TL_REG_TL_PM_L10_WAIT_ACK_TIMEOUT_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC04) /* the timeout configuration of the pm state l10_wait_ack to l1n_wait_ack */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_TRACE_CMP_EN_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC10) /* trace spcify info enable,and inbound or outbound select */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW0_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC14) /* reference header DW0 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW1_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC18) /* reference header DW1 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW2_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC1C) /* reference header DW2 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_REF_HEADER_DW3_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC20) /* reference header DW3 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW0_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC24) /* captured header DW0 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW1_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC28) /* captured header DW1 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW2_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC2C) /* captured header DW2 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_CAP_HEADER_DW3_REG \ + (CSR_HIPCIEC50_TL_REG_BASE + 0xC30) /* captured header DW3 for TL_RX trace. */ +#define CSR_HIPCIEC50_TL_REG_TL_RX_TRACT_TLP_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xC34) /* CAPTURED TLP counter */ +#define CSR_HIPCIEC50_TL_REG_TL_CFG_DOE_CNT_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xE00) /* DOE cap counter */ +#define CSR_HIPCIEC50_TL_REG_TL_CFG_DOE_STS_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xE04) /* DOE cap status */ +#define CSR_HIPCIEC50_TL_REG_ECO_TL_REG (CSR_HIPCIEC50_TL_REG_BASE + 0xFFC) /* Add some registers for eco. */ + +/* HIPCIEC50_TL_CORE_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TL_CORE_REG_BASE (0x30000) + +/* **************************************************************************** */ +/* HIPCIEC50_TL_CORE_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_TL_CORE_REG_APTL_ASYN_FIFO_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x0) /* AP to TL asynchrous FIFO control */ +#define CSR_HIPCIEC50_TL_CORE_REG_CORE_TL_TX_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x4) /* Transaction Layer transmission control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_CHECK_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x8) /* TL_TX completion context check control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TX_CRD_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xC) /* TL_TX credit control signals */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_REG_CFG_ACCESS_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x10) /* TL_REG_CFG_access ctrl signals */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x20) /* Software postTLP generater */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x24) /* tlp header DW0 \ + */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x28) /* tlp header DW1 \ + */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x2C) /* tlp header DW2 \ + */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_HEADER3_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x30) /* tlp header DW3 \ + */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TLP_FUN_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x34) /* message function selection */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x38) /* Payload DW 0 */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x3C) /* Payload DW 1 */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x40) /* Payload DW 2 */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_INSERT_TLP_DATA3_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x44) /* Payload DW 3 */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG01_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x48) /* TL_TX completion timeout registers of default value. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG23_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x4C) /* TL_TX completion timeout registers of default value. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG45_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x50) /* TL_TX completion timeout registers of default value. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG67_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x54) /* TL_TX completion timeout registers of default value. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_CPL_TIMER_CFG8_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x58) /* TL_TX completion timeout registers of default value. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_WAIT_IDLE_TIMER_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x100) /* TL wait idle timer configuration register. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_PORT_IDLE_TOUT_TIMER_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x104) /* TL wait idle timer configuration register. */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_CDT_CFG_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x500) /* TL RX Credit (with AP/CPI) configuration */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_ATOMIC_DROP_CFG_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x504) /* TL atomic Drop configuration */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_MISC_CFG_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x508) /* TL RX MISC configuration */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_HIDX_FIFO_TH_VALUE_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x50C) /* TL RX HIDX FIFO threshold Value configuration */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_CPLH_FIFO_TH_VALUE_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x510) /* TL RX CPL FIFO threshold Value configuration */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_MSI_ADDR_WINDOW_L_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x514) /* TL RX MSI low 32 bit addr match window */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_RX_MSI_ADDR_WINDOW_H_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x518) /* TL RX MSI high 32 bit addr match window */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_STATUS_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x800) /* cfgspace VPD interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x804) /* cfgspace VPD interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_SET_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x808) /* cfgspace VPD interrupt set register */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_VPD_INT_RO_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x80C) /* cfgspace VPD interrupt RO status */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_FLR_INT_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x810) /* Where the FLR interrupt is report. To IEP or CORE interrupt line */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_STATUS0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x814) /* TL Core interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_MASK0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x818) /* TL CORE interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_SET0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x81C) /* TL_CORE interrupt set register */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_RO0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x820) /* TL_CORE interrupt indicater status */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_INT_SEL0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x824) /* CE and NFE select signal */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CFG_CTRL_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x900) /* tl cfgspace control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CFG_PF_EN_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x904) /* PF SUPPORT ENABLE */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_PORT_USED_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x908) /* PORT used indicator */ +#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x910) /* port physical function start number */ +#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX1_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x914) /* port physical function start number */ +#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX2_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x918) /* port physical function start number */ +#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX3_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x91C) /* port physical function start number */ +#define CSR_HIPCIEC50_TL_CORE_REG_PN_PF_STR_IDX4_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x920) /* port physical function start number */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_PF_VF_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x924) /* Cfgspace PF and VF control register */ +#define CSR_HIPCIEC50_TL_CORE_REG_PF_FLR_INT_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x940) /* PF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_REG_PF_FLR_INT_STATUS_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x944) /* PF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_REG_PF_FLR_EN_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x948) /* Enable PF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x94C) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x950) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x954) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID3_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x958) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID4_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x95C) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID5_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x960) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID6_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x964) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_DEVICE_ID7_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x968) /* vf virtio device id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_VENDOR_ID0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x96C) /* vf virtio vendor id */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_VENDOR_ID1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x970) /* reserved */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_CLASS_CODE0_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x974) /* vf nvme class code */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_CLASS_CODE1_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x978) /* reserved */ +#define CSR_HIPCIEC50_TL_CORE_REG_VF_CLASS_CODE2_REG (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x97C) /* reserved */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_FLR_DISABLE_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0x980) /* CFGSPACE CAP disable FLR reset */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_0_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA00) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_1_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA04) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_2_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA08) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_3_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA0C) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_4_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA10) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_5_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA14) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_6_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA18) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_7_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA1C) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_8_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA20) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_9_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA24) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_10_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA28) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_11_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA2C) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_12_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA30) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_13_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA34) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_14_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA38) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_TX_TAG_CTRL_15_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA3C) /* TL_TX tag management control */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_PFN_VF_ONLINE_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA40) /* PFN vf enable interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_REG_CFG_PFN_VF_OFFLINE_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xA44) /* PFN vf disable interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_REG_TL_CORE_ECO_REG \ + (CSR_HIPCIEC50_TL_CORE_REG_BASE + 0xFFC) /* Add some registers for eco. */ + +/* HIPCIEC50_TL_CORE_PF_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_BASE (0x31000) + +/* **************************************************************************** */ +/* HIPCIEC50_TL_CORE_PF_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_TL_CORE_PF_REG_TL_CFG_PF_FUNC_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x0) /* PF Function select 0 */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_TL_CFGSPACE_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x4) /* Select CFGSPACE Function */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_TL_PF_VF_CFGSPACE_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x8) /* Select VF or PF CFGSPACE Function */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR0_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x10) /* Physical function n BAR0 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR1_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x14) /* Physical function n BAR1 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR2_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x18) /* Physical function n BAR2 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR3_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x1C) /* Physical function n BAR3 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR4_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x20) /* Physical function n BAR4 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BAR5_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x24) /* Physical function n BAR5 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_ROM_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x28) /* Physical function n extended ROM mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_BARN_ENABLE_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x2C) /* Physical function n BAR enable */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR0_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x30) /* Virtual function n BAR0 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR1_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x34) /* Virtual function n BAR1 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR2_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x38) /* Virtual function n BAR2 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR3_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x3C) /* Virtual function n BAR3 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR4_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x40) /* Virtual function n BAR4 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BAR5_MASK_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x44) /* Virtual function n BAR5 mask */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_VFN_BARN_ENABLE_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x48) /* Virtual function n BAR enable */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_MSIX_CONTROL_REG_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x50) /* MSIX CONTROL REGISTER */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_MSIX_OFFSET_BIR_REG_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x54) /* MSIX OFFSET AND BIR REGISTER */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PBA_OFFSET_BIR_REG_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x58) /* PBA OFFSET AND BIR REGISTER */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_ARI_NEXT_ADDR_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x60) /* PF0 and PF1 VF ARI next address */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_VF_VENDOR_ID_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x64) /* VF Vendor ID of PF0 and PF1 */ +#define CSR_HIPCIEC50_TL_CORE_PF_REG_PFN_VF_TPH_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_PF_REG_BASE + 0x68) /* VF TPH CAP st_mode_sel、st_table_size fields */ + +/* HIPCIEC50_TL_CORE_VF_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_BASE (0x3A000) + +/* **************************************************************************** */ +/* HIPCIEC50_TL_CORE_VF_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_0_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_1_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_2_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_3_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_4_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x10) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_5_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x14) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_6_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x18) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_7_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_8_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x20) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_9_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x24) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_10_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x28) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_11_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x2C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_12_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x30) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_13_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x34) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_14_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x38) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_15_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x3C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_16_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x40) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_17_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x44) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_18_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x48) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_19_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_20_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x50) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_21_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x54) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_22_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x58) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_23_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_24_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x60) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_25_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x64) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_26_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x68) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_27_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x6C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_28_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x70) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_29_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x74) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_30_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x78) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_31_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x7C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_32_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x80) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_33_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x84) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_34_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x88) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_35_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_36_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x90) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_37_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x94) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_38_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x98) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_39_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_40_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xA0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_41_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xA4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_42_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xA8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_43_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xAC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_44_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xB0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_45_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xB4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_46_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xB8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_47_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xBC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_48_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_49_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_50_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xC8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_51_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xCC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_52_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xD0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_53_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xD4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_54_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xD8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_55_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xDC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_56_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xE0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_57_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xE4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_58_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xE8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_59_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xEC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_60_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xF0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_61_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xF4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_62_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xF8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_63_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0xFC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_64_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x100) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_65_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x104) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_66_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x108) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_67_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x10C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_68_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x110) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_69_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x114) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_70_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x118) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_71_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x11C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_72_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x120) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_73_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x124) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_74_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x128) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_75_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x12C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_76_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x130) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_77_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x134) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_78_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x138) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_79_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x13C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_80_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x140) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_81_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x144) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_82_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x148) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_83_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x14C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_84_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x150) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_85_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x154) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_86_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x158) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_87_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x15C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_88_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x160) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_89_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x164) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_90_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x168) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_91_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x16C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_92_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x170) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_93_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x174) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_94_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x178) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_95_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x17C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_96_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x180) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_97_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x184) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_98_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x188) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_99_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x18C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_100_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x190) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_101_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x194) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_102_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x198) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_103_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x19C) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_104_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1A0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_105_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1A4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_106_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1A8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_107_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1AC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_108_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1B0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_109_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1B4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_110_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1B8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_111_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1BC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_112_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_113_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_114_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1C8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_115_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1CC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_116_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1D0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_117_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1D4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_118_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1D8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_119_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1DC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_120_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1E0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_121_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1E4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_122_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1E8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_123_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1EC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_124_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1F0) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_125_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1F4) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_126_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1F8) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_MASK_127_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x1FC) /* VF FLR occur interrupt mask */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_0_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x400) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_1_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x404) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_2_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x408) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_3_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x40C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_4_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x410) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_5_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x414) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_6_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x418) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_7_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x41C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_8_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x420) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_9_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x424) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_10_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x428) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_11_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x42C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_12_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x430) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_13_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x434) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_14_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x438) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_15_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x43C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_16_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x440) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_17_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x444) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_18_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x448) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_19_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x44C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_20_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x450) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_21_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x454) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_22_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x458) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_23_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x45C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_24_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x460) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_25_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x464) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_26_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x468) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_27_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x46C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_28_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x470) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_29_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x474) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_30_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x478) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_31_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x47C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_32_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x480) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_33_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x484) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_34_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x488) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_35_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x48C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_36_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x490) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_37_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x494) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_38_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x498) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_39_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x49C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_40_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4A0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_41_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4A4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_42_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4A8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_43_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4AC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_44_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4B0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_45_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4B4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_46_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4B8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_47_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4BC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_48_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_49_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_50_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4C8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_51_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4CC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_52_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4D0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_53_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4D4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_54_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4D8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_55_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4DC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_56_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4E0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_57_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4E4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_58_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4E8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_59_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4EC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_60_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4F0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_61_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4F4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_62_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4F8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_63_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x4FC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_64_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x500) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_65_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x504) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_66_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x508) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_67_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x50C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_68_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x510) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_69_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x514) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_70_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x518) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_71_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x51C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_72_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x520) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_73_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x524) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_74_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x528) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_75_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x52C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_76_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x530) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_77_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x534) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_78_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x538) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_79_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x53C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_80_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x540) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_81_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x544) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_82_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x548) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_83_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x54C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_84_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x550) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_85_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x554) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_86_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x558) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_87_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x55C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_88_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x560) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_89_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x564) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_90_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x568) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_91_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x56C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_92_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x570) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_93_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x574) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_94_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x578) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_95_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x57C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_96_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x580) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_97_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x584) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_98_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x588) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_99_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x58C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_100_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x590) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_101_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x594) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_102_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x598) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_103_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x59C) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_104_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5A0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_105_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5A4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_106_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5A8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_107_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5AC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_108_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5B0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_109_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5B4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_110_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5B8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_111_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5BC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_112_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_113_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_114_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5C8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_115_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5CC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_116_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5D0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_117_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5D4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_118_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5D8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_119_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5DC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_120_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5E0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_121_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5E4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_122_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5E8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_123_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5EC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_124_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5F0) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_125_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5F4) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_126_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5F8) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_INT_STATUS_127_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x5FC) /* VF FLR occur interrupt status */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_0_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x800) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_1_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x804) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_2_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x808) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_3_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x80C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_4_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x810) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_5_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x814) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_6_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x818) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_7_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x81C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_8_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x820) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_9_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x824) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_10_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x828) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_11_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x82C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_12_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x830) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_13_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x834) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_14_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x838) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_15_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x83C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_16_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x840) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_17_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x844) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_18_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x848) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_19_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x84C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_20_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x850) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_21_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x854) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_22_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x858) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_23_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x85C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_24_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x860) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_25_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x864) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_26_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x868) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_27_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x86C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_28_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x870) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_29_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x874) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_30_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x878) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_31_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x87C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_32_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x880) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_33_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x884) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_34_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x888) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_35_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x88C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_36_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x890) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_37_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x894) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_38_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x898) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_39_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x89C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_40_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8A0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_41_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8A4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_42_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8A8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_43_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8AC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_44_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8B0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_45_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8B4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_46_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8B8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_47_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8BC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_48_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_49_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_50_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8C8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_51_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8CC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_52_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8D0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_53_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8D4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_54_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8D8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_55_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8DC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_56_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8E0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_57_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8E4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_58_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8E8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_59_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8EC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_60_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8F0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_61_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8F4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_62_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8F8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_63_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x8FC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_64_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x900) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_65_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x904) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_66_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x908) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_67_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x90C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_68_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x910) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_69_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x914) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_70_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x918) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_71_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x91C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_72_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x920) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_73_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x924) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_74_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x928) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_75_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x92C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_76_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x930) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_77_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x934) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_78_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x938) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_79_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x93C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_80_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x940) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_81_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x944) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_82_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x948) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_83_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x94C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_84_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x950) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_85_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x954) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_86_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x958) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_87_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x95C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_88_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x960) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_89_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x964) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_90_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x968) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_91_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x96C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_92_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x970) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_93_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x974) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_94_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x978) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_95_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x97C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_96_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x980) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_97_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x984) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_98_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x988) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_99_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x98C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_100_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x990) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_101_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x994) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_102_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x998) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_103_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x99C) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_104_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9A0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_105_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9A4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_106_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9A8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_107_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9AC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_108_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9B0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_109_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9B4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_110_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9B8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_111_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9BC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_112_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_113_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_114_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9C8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_115_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9CC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_116_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9D0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_117_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9D4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_118_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9D8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_119_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9DC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_120_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9E0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_121_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9E4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_122_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9E8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_123_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9EC) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_124_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9F0) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_125_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9F4) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_126_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9F8) /* Enable VF level reset as SPEC description */ +#define CSR_HIPCIEC50_TL_CORE_VF_REG_VF_FLR_EN_127_REG \ + (CSR_HIPCIEC50_TL_CORE_VF_REG_BASE + 0x9FC) /* Enable VF level reset as SPEC description */ + +/* HIPCIEC50_TL_CORE_CC_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TL_CORE_CC_REG_BASE (0x3C000) + +/* **************************************************************************** */ +/* HIPCIEC50_TL_CORE_CC_REG Registers' Definitions */ +/* **************************************************************************** */ + + +/* HIPCIEC50_TL_CORE_DFX_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE (0x3E000) + +/* **************************************************************************** */ +/* HIPCIEC50_TL_CORE_DFX_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ASYN_FIFO_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x0) /* TL TX asynchronous FIFO Status */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_INGRESS_EGRESS_CNT_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x4) /* TL TX ingress and egress TLP count control */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_INGRESS_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x8) /* TL_TX CH0 receive TLP counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CTRL_EGRESS_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xC) /* TL_TX CTRL transmit TLP counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_SCH_FIFO_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x10) /* TL TX_ST FIFO status */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CTRL_HS_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x14) /* TL TX_CTRL with DL handshake status */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_CFG_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x30) /* TL TX SRAM ECC configure */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x34) /* TL TX SRAM ECC error, the SRAM address */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_1BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x38) /* TL TX 1bit ECC Error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECC_2BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x3C) /* TL TX 2bit ECC Error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ERR_ERROR_STATUS_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x40) /* TL TX ERR ERROR STATUS */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CNT_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x50) /* Traffic monitor control */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ECRC_ERR_INSERT_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x54) /* TL_TX ECRC error insert counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CNT_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x58) /* Traffic monitor status */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x60) /* TL TX capture or insert field in TLP, The DW0 field of header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x64) /* TL TX capture or insert field in TLP, The DW1 field of header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x68) /* TL TX capture or insert field in TLP, The DW2 field of header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x6C) /* TL TX capture or insert field in TLP, The DW3 field of header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x70) /* TL TX capture or insert field in TLP, The DW0 field mask of header \ + */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x74) /* TL TX capture or insert field in TLP, The DW1 field mask of header \ + */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x78) /* TL TX capture or insert field in TLP, The DW2 field mask of header \ + */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_FIELD_MAP_3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x7C) /* TL TX capture or insert field in TLP, The DW3 field mask of header \ + */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x80) /* TL TX have capture header DW0 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x84) /* TL TX have capture header DW1 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x88) /* TL TX have capture header DW2 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CAPTU_HED_3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x8C) /* TL TX have capture header DW3 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CFG_FIFO_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x98) /* TL_TX CFG FIFO read counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_MEM_RD_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x9C) /* TL TX memory read counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_MEM_WR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xA0) /* TL TX memory write counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_IO_RD_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xA4) /* TL TX IO read counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_IO_WR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xA8) /* TL TX IO write counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_MSG_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xAC) /* TL TX message counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xB0) /* TL TX CPL counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ATOMIC_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xB8) /* TL TX atomic counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_P2P_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xBC) /* TL TX peer2peer TLP counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_GEN_CPL_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xC0) /* TL TX native gen CPL counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ATOMIC_BLK_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xC8) /* TL TX atomic block error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_PFX_BLK_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xCC) /* TL TX prefix block error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_POISON_BLK_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xD0) /* TL TX poison block error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FUN_TLP_TLP_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xD4) /* TL TX function TLP number counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FUN_PAYLOAD_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xD8) /* TL TX function TLP payload counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FUN_ALL_DW_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xDC) /* TL TX function TLP ALL DW counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_FIFO_STS_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0xE4) /* TL TX FIFO empty and full */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_DFX_CTRL_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x100) /* TL_TX_CONTEXT DFX control signals */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x104) /* TL_TX_CONTEXT entry DW 0 info */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x108) /* TL_TX_CONTEXT entry DW 0 info */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x10C) /* TL_TX_CONTEXT entry DW 0 info */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x110) /* TL_TX_CONTEXT entry DW 0 info */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_DW4_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x114) /* TL_TX_CONTEXT entry DW 0 info */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_ERR_INFO_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x118) /* TL_TX_CONTEXT entry err info */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_ENTRY_ERR_STATUS_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x11C) /* TL_TX_CONTEXT DFX control signals */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECH_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x120) /* TL_TX_CONTEXT check request counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECK_UC_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x124) /* TL_TX_CONTEXT check UC counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECK_MALFORM_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x128) /* TL_TX_CONTEXT check malform counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_CHECK_MERGE_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x12C) /* TL_TX_CONTEXT check merge counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_CONTEXT_TOUT_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x130) /* TL_TX_CONTEXT CPL timeout counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x300) /* TL RX ODR_CTRL ptr DFX of port select */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x304) /* TL RX ODR_CTRL ptr DFX of port0 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x308) /* TL RX ODR_CTRL ptr DFX of port1 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x30C) /* TL RX ODR_CTRL ptr DFX of port2 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x310) /* TL RX ODR_CTRL ptr DFX of port3 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P4_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x314) /* TL RX ODR_CTRL ptr DFX of port4 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P5_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x318) /* TL RX ODR_CTRL ptr DFX of port5 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P6_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x31C) /* TL RX ODR_CTRL ptr DFX of port6 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P7_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x320) /* TL RX ODR_CTRL ptr DFX of port7 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P8_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x324) /* TL RX ODR_CTRL ptr DFX of port8 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P9_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x328) /* TL RX ODR_CTRL ptr DFX of port9 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P10_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x32C) /* TL RX ODR_CTRL ptr DFX of port10 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P11_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x330) /* TL RX ODR_CTRL ptr DFX of port11 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P12_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x334) /* TL RX ODR_CTRL ptr DFX of port12 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P13_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x338) /* TL RX ODR_CTRL ptr DFX of port13 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P14_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x33C) /* TL RX ODR_CTRL ptr DFX of port14 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_PTR_P15_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x340) /* TL RX ODR_CTRL ptr DFX of port15 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_CTRL_IDLE_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x344) /* TL_RX_DFX_ODR_CTRL_IDLE */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P0P3_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x348) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P4P7_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x34C) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P8P11_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x350) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_ODR_QUEUE_IDLE_P12P15_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x354) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_SDAP_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x380) /* RX and AP interface tlp counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_CNT_DFX0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x384) /* TL RX COUNTER0 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_CNT_DFX1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x388) /* TL RX COUNTER1 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x400) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x404) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x408) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x40C) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_4_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x410) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_5_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x414) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_6_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x418) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_7_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x41C) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_8_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x420) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_9_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x424) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_10_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x428) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_11_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x42C) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_12_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x430) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_13_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x434) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_14_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x438) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_15_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x43C) /* TL RX_BUF DFX */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_BUF_PTR_DFX_SEL_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x440) /* TL RX_BUF PTR type select */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_16_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x444) /* TL_RX_DFX_BUF_16 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_17_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x448) /* TL_RX_DFX_BUF_17 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_18_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x44C) /* TL_RX_DFX_BUF_18 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_DFX_BUF_19_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x450) /* TL_RX_DFX_BUF_19 */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_ERR_INJECT_CFG_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x500) /* TL RX ECC insert error configuration */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x504) /* TL_RX_ECC_ERR_ADDR */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_1BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x508) /* TL RX ECC 1bit error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_ECC_2BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x50C) /* TL RX ECC 2bit error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_INSERT_UNCOR_ERR_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x600) /* tl aer insert uncorable error */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_INSERT_COR_ERR_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x604) /* tl aer insert corable error */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x608) /* The information of tl AER insert DW0 header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW1_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x60C) /* The information of tl AER insert DW1 header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW2_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x610) /* The information of tl AER insert DW2 header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_HEADER_DW3_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x614) /* The information of tl AER insert DW3 header */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_AER_FUN_NUM_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x618) /* The function number of tl aer insert tlp */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_CFG_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x640) /* TL CFGSPACE SRAM ECC configure */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_ADDR_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x644) /* TL TX SRAM ECC 1bit error, the SRAM address */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_1BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x648) /* CFGSPCE_1bit ECC Error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_2BIT_ERR_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x64C) /* CFGSPACE 2bit ECC Error counter */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_TYPE_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x650) /* CFGSPACE ECC ERROR SRAM SEL */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_ECC_ERR_ST_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x654) /* CGFSPACE ECC ERR STATUS */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_CFGSPACE_HDK_STATUS_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x658) /* CFGSPACE access handshake status */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CFG_PF_DFX_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x65C) /* CFGSPACE access global pf number and port number map */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CFG_PORTN_NUM0_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x660) /* CFGSPACE port number map to pf */ +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_CFG_PF_AER_DFX_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x66C) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_TLP_GEN_CPL_CACHE_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x670) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_TLP_GEN_P_CACHE_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x674) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_RX_TX_UR_FIFO_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x678) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_UR_FIFO_STS_REG (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x67C) +#define CSR_HIPCIEC50_TL_CORE_DFX_REG_TL_TX_ASYN_FIFO_CNT_REG \ + (CSR_HIPCIEC50_TL_CORE_DFX_REG_BASE + 0x680) /* AP2TX ASYN FIFO CNT */ + +/* HIPCIEC_EPF_CFGSPACE Base address of Module's Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_BASE (0x40000) + +/* **************************************************************************** */ +/* HIPCIEC_EPF_CFGSPACE Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_ID_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x0) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CMDSTS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CLSREV_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_MISC_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR0_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x10) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR1_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x14) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x18) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR3_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR4_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x20) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_BAR5_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x24) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CBUS_PTR_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x28) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_SUBSYS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_EXPROM_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x30) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_CAPPTR_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x34) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCI_RSVD_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x38) /* reserved */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIHDR_INT_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PCIE_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x40) /* This is the pcie capability header register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CAPBILITY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x44) /* This register describe the device capability */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x48) /* device control status register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CAPBILITY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4C) /* Link capability register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CTRL_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x50) /* Link control register \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CAPABILITY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x54) /* Slot capability register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x58) /* Slot control and status register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_CTRL_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x5C) /* Root control status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x60) /* Root status register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CAPABILITY2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x64) /* device capability 2 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_CTRL2_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x68) /* Device control register 2 \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CAPABILITY2_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x6C) /* Link capability 2 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CTRL_STATUS2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x70) /* Link control and status 2 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CAP_2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x74) /* Slot Capabilities 2 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SLOT_CTRL_2_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x78) /* Slot Control 2 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x80) /* MSI control and ID regisiter */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_LADDR_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x84) /* MSI low address */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_HADDR_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x88) /* MSI uppr address */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_DATA_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8C) /* MSI data register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_MASK_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x90) /* MSI mask register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSI_PENDING_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x94) /* MSI pending register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VPD_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x98) /* VPD address and ID regisiter */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VPD_CAP_DATA_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x9C) /* VPD data */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSIX_CAP_HEADER_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xA0) /* MSIX control register \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSIX_TABLE_CTRL_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xA4) /* MSIX table control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_MSIX_PBA_CTRL_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xA8) /* MSIX pending bit array control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PME_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xB0) /* PME capability header and PME control */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PME_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xB4) /* Power management status register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xB8) /* Virtio Common capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_BAR_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xBC) /* Virtio Common configuration structure BAR indicator */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_OFFSET_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC0) /* Virtio Common configuration structure offset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_COMMON_LENGTH_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC4) /* Virtio Common configuration structure length */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xC8) /* Virtio Notify capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_BAR_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xCC) /* Virtio Notification structure BAR indicator */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_OFFSET_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xD0) /* Virtio Notification structure offset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_LENGTH_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xD4) /* Virtio Notification structure length */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_NOTIFY_OFF_MULTIPLIER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xD8) /* Virtio Notification structure off multiplier */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xDC) /* Virtio ISR capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_BAR_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xE0) /* Virtio ISR status structure BAR indicator */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_OFFSET_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xE4) /* Virtio ISR status structure offset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_ISR_LENGTH_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xE8) /* Virtio ISR status structure length */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xEC) /* Virtio Device Specify capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_BAR_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xF0) /* Virtio Device Specify configuration structure BAR indicator */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_OFFSET_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xF4) /* Virtio Device Specify configuration structure offset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VIRTIO_DEVICE_LENGTH_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0xF8) /* Virtio Device Specify configuration structure length */ +#define CSR_HIPCIEC_EPF_CFGSPACE_AER_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x104) /* uncorrectable error status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_MASK_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */ +#define CSR_HIPCIEC_EPF_CFGSPACE_UNCR_ERR_SEVERITY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */ +#define CSR_HIPCIEC_EPF_CFGSPACE_COR_ERR_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x110) /* Correctable error status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_COR_ERR_MASK_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x114) /* correctable error mask */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ADVACD_CAP_CTRL_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_FIRST_HEADER_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x11C) /* First DW header log \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SECOND_HEADER_LOG_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x120) /* Second DW header log */ +#define CSR_HIPCIEC_EPF_CFGSPACE_THIRD_HEADER_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x124) /* Third DW header log \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_FOUR_HEADER_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x128) /* Forth DW header log */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_ERROR_COMMAND_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x12C) /* Root error report command */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ROOT_ERROR_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x130) /* Roor Error status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ERR_SOURCE_IDEN_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x134) /* Erorr soure identification register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_FIRST_PREFIX_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x138) /* First DW prefix log \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SECOND_PREFIX_LOG_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x13C) /* Second DW prefix log */ +#define CSR_HIPCIEC_EPF_CFGSPACE_THIRD_PREFIX_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x140) /* Third DW prefix log \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_FOUR_PREFIX_LOG_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x144) /* Forth DW prefix log */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ARI_CAP_HEADER_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x150) /* ARI capability header \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ARI_CTRL_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x154) /* ARI control and capability */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_HED_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1A0) /* PCI Express Extend CAP Header \ + */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_CAP_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1A4) /* DOE capability */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_CTRL_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1A8) /* DOE Control Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DOE_STATUS_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1AC) /* DOE Status Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_WR_DATA_MBOX_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1B0) /* write data malibox */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RD_DATA_MBOX_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x1B4) /* read data mailbox */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SRIOV_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x200) /* SRROIOV capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SRIOV_CAP_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x204) /* SRROIOV capability */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SRIOV_CTRL_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x208) /* SRROIOV control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_INIT_VF_NUMBER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x20C) /* Initial VF and Totla VF */ +#define CSR_HIPCIEC_EPF_CFGSPACE_FUNC_DEP_VF_NUM_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x210) /* Function dependency link and VF NUMBER */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_RID_SETTING_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x214) /* First offset and Stride register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_DEVICE_ID_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x218) /* VF device ID */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_PAGE_SIZE_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x21C) /* supported Page Size */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SYSTEM_PAGE_SIZE_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x220) /* System page size */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR0_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x224) /* Virtual function Base address 0 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR1_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x228) /* Virtual function Base address 1 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x22C) /* Virtual function Base address 2 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR3_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x230) /* Virtual function Base address 3 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR4_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x234) /* Virtual function Base address 4 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_BAR5_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x238) /* Virtual function Base address 5 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_VF_MIG_STATE_ARRAY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x23C) /* VF Migration state array offset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ATS_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x260) /* Address translation service capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ATS_CAP_CTRL_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x264) /* ATS capability and control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PR_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x280) /* Page Request capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PR_CAP_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x284) /* Page Request capability control and status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PR_OUT_REQ_CAP_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x288) /* outstanding page request capability */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PR_OUT_REQ_ALC_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x28C) /* outstanding page request capability */ +#define CSR_HIPCIEC_EPF_CFGSPACE_TPH_EXTEND_CAP_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_TPH_REQ_CAP_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A4) /* tph request capability register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_TPH_REQ_CTRL_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2A8) /* tph requester control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PASID_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C0) /* PASID capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_PASID_CAP_CTRL_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x2C4) /* PASID capability and control */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SECONDARY_PCIE_EXT_CAP_HED_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x310) /* Secondary PCI Express Extended Capability Header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x314) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LANE_ERROR_STATUS_REG_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x318) /* Lane Error Status Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER01_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x31C) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER23_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x320) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER45_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x324) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER67_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x328) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER89_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x32C) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1011_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x330) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1213_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x334) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LINK_CONTROL3_REGISTER1415_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x338) /* Link Control 3 Register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C0) /* L1 PM substates extended capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CAPABILITY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C4) /* L1 PM substates capability register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CONTROL1_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3C8) /* L1 PM substates control 1 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_CONTROL2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3CC) /* L1 PM substates control 2 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_L1PM_STATUS_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x3D0) /* L1 PM substates status register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DEVICE_SERIAL_NUMBER_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E0) /* device serial number extended capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SERIAL_LNUM_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E4) /* serial low number register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_SERIAL_HNUM_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x4E8) /* serial high number register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x500) /* Extend capability register 00 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X04_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x504) /* Extend capability register 04 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X08_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x508) /* Extend capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X0C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x50C) /* Extend capability register 0c */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X10_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x510) /* Extend capability register 10 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X14_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x514) /* Extend capability register 14 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X18_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x518) /* Extend capability register 18 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DUMMY_CAP_0X1C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x51C) /* Extend capability register 1c */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ACS_CAP_0X00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x630) /* ACS capability register 00 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_ACS_CAP_0X04_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x634) /* ACS capability register 04 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LTR_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x6D0) /* LTR extended capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_LTR_MAX_LATENCY_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x6D4) /* LTR MAX snoop/no snoop latency register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x700) /* DL feature capability register 00 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG04_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x704) /* DL feature capability register 04 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_DL_FEATURE_CAP_REG08_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x708) /* DL feature capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x70C) /* RX Margin capability register 00 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG04_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x710) /* RX Margin capability register 04 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_0_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x714) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_1_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x718) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_2_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x71C) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_3_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x720) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_4_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x724) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_5_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x728) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_6_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x72C) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_7_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x730) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_8_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x734) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_9_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x738) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_10_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x73C) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_11_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x740) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_12_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x744) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_13_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x748) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_14_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x74C) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_RXMARGIN_CAP_REG08_15_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x750) /* RX Margin capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x780) /* Gen5 phy capability header */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG04_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x784) /* Gen5 capability register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG08_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x788) /* Gen5 Control register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG0C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x78C) /* Gen5 Status register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG10_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x790) /* Gen5 Received modify TS Data1 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG14_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x794) /* Gen5 Received modify TS Data2 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG18_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x798) /* Gen5 Transmitted modify TS Data1 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG1C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x79C) /* Gen5 Transmitted modify TS Data2 register */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG20_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7A0) /* Gen5 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG24_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7A4) /* Gen5 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG28_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7A8) /* Gen5 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN5_PHY_CAP_REG2C_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x7AC) /* Gen5 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x800) /* CCIX transport capability register 00 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG04_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x804) /* CCIX transport capability register 04 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG08_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x808) /* CCIX transport capability register 08 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG0C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x80C) /* CCIX transport capability register 0C */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG10_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x810) /* CCIX transport capability register 10 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG14_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x814) /* CCIX transport capability register 14 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG18_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x818) /* CCIX transport capability register 18 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG1C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x81C) /* CCIX transport capability register 1C */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG20_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x820) /* CCIX transport capability register 20 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG24_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x824) /* CCIX transport capability register 24 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG28_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x828) /* CCIX transport capability register 28 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG2C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x82C) /* CCIX transport capability register 2C */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG30_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x830) /* CCIX transport capability register 30 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG34_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x834) /* CCIX transport capability register 34 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG38_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x838) /* CCIX transport capability register 38 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG3C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x83C) /* CCIX transport capability register 3C */ +#define CSR_HIPCIEC_EPF_CFGSPACE_CCIX_TS_CAP_REG40_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x840) /* CCIX transport capability register 40 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG00_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x880) /* Gen4 phy txpreset capability register 00 */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG04_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x884) /* reserved */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG08_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x888) /* reserved */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG0C_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x88C) /* gen4 equalization req and status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG10_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x890) /* local link data parity status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG14_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x894) /* retimer link data parity status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG18_REG \ + (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x898) /* second retimer link data parity status */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG1C_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x89C) /* reserved */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG20_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A0) /* Gen4 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG24_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A4) /* Gen4 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG28_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8A8) /* Gen4 tx preset */ +#define CSR_HIPCIEC_EPF_CFGSPACE_GEN4_PHY_CAP_REG2C_REG (CSR_HIPCIEC_EPF_CFGSPACE_BASE + 0x8AC) /* Gen4 tx preset */ + +/* HIPCIEC_EPFN_CFGSPACE Base address of Module's Register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_BASE (0x40000) + +/* **************************************************************************** */ +/* HIPCIEC_EPFN_CFGSPACE Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_ID_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x0) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CMDSTS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CLSREV_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x8) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_MISC_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR0_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x10) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR1_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x14) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR2_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x18) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR3_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x1C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR4_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x20) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_BAR5_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x24) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CBUS_PTR_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x28) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_SUBSYS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_EXPROM_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x30) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_CAPPTR_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x34) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCI_RSVD_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x38) /* reserved */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIHDR_INT_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x3C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PCIE_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x40) /* This is the pcie capability header register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CAPBILITY_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x44) /* This register describe the device capability */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x48) /* device control status register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CAPBILITY_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4C) /* Link capability register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x50) /* Link control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CAPABILITY_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x54) /* Slot capability register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x58) /* Slot control and status register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_CTRL_STATUS_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x5C) /* Root control status \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_STATUS_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x60) /* Root status register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CAPABILITY2_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x64) /* device capability 2 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_CTRL2_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x68) /* Device control register 2 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CAPABILITY2_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x6C) /* Link capability 2 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_LINK_CTRL_STATUS2_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x70) /* Link control and status 2 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CAP_2_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x74) /* Slot Capabilities 2 Register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SLOT_CTRL_2_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x78) /* Slot Control 2 Register \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x80) /* MSI control and ID regisiter */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_LADDR_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x84) /* MSI low address */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_HADDR_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x88) /* MSI uppr address */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_DATA_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x8C) /* MSI data register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_MASK_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x90) /* MSI mask register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSI_PENDING_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x94) /* MSI pending register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VPD_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x98) /* VPD address and ID regisiter */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VPD_CAP_DATA_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x9C) /* VPD data */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSIX_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xA0) /* MSIX control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSIX_TABLE_CTRL_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xA4) /* MSIX table control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_MSIX_PBA_CTRL_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xA8) /* MSIX pending bit array control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PME_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xB0) /* PME capability header and PME control */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PME_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xB4) /* Power management status register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xB8) /* Virtio Common capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_BAR_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xBC) /* Virtio Common configuration structure BAR indicator */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_OFFSET_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC0) /* Virtio Common configuration structure offset */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_COMMON_LENGTH_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC4) /* Virtio Common configuration structure length */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xC8) /* Virtio Notify capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_BAR_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xCC) /* Virtio Notification structure BAR indicator */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_OFFSET_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xD0) /* Virtio Notification structure offset */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_LENGTH_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xD4) /* Virtio Notification structure length */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_NOTIFY_OFF_MULTIPLIER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xD8) /* Virtio Notification structure off multiplier */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xDC) /* Virtio ISR capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_BAR_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xE0) /* Virtio ISR status structure BAR indicator */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_OFFSET_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xE4) /* Virtio ISR status structure offset */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_ISR_LENGTH_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xE8) /* Virtio ISR status structure length */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xEC) /* Virtio Device Specify capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_BAR_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xF0) /* Virtio Device Specify configuration structure BAR indicator */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_OFFSET_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xF4) /* Virtio Device Specify configuration structure offset */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VIRTIO_DEVICE_LENGTH_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0xF8) /* Virtio Device Specify configuration structure length */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_AER_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_UNCR_ERR_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x104) /* uncorrectable error status */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_UNCR_ERR_MASK_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_UNCR_ERR_SEVERITY_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_COR_ERR_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x110) /* Correctable error status */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_COR_ERR_MASK_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x114) /* correctable error mask \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ADVACD_CAP_CTRL_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_FIRST_HEADER_LOG_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x11C) /* First DW header log */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SECOND_HEADER_LOG_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x120) /* Second DW header log */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_THIRD_HEADER_LOG_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x124) /* Third DW header log */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_FOUR_HEADER_LOG_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x128) /* Forth DW header log \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_ERROR_COMMAND_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x12C) /* Root error report command */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ROOT_ERROR_STATUS_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x130) /* Roor Error status \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ERR_SOURCE_IDEN_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x134) /* Erorr soure identification register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_FIRST_PREFIX_LOG_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x138) /* First DW prefix log */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SECOND_PREFIX_LOG_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x13C) /* Second DW prefix log */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_THIRD_PREFIX_LOG_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x140) /* Third DW prefix log */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_FOUR_PREFIX_LOG_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x144) /* Forth DW prefix log \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ARI_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x150) /* ARI capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ARI_CTRL_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x154) /* ARI control and capability \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SRIOV_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x200) /* SRROIOV capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SRIOV_CAP_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x204) /* SRROIOV capability */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SRIOV_CTRL_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x208) /* SRROIOV control register \ + */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_INIT_VF_NUMBER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x20C) /* Initial VF and Totla VF */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_FUNC_DEP_VF_NUM_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x210) /* Function dependency link and VF NUMBER */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_RID_SETTING_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x214) /* First offset and Stride register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_DEVICE_ID_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x218) /* VF device ID */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_PAGE_SIZE_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x21C) /* supported Page Size */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SYSTEM_PAGE_SIZE_REG (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x220) /* System page size */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR0_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x224) /* Virtual function Base address 0 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR1_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x228) /* Virtual function Base address 1 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR2_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x22C) /* Virtual function Base address 2 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR3_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x230) /* Virtual function Base address 3 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR4_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x234) /* Virtual function Base address 4 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_BAR5_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x238) /* Virtual function Base address 5 register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_VF_MIG_STATE_ARRAY_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x23C) /* VF Migration state array offset */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ATS_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x260) /* Address translation service capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ATS_CAP_CTRL_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x264) /* ATS capability and control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x280) /* Page Request capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_CAP_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x284) /* Page Request capability control and status */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_OUT_REQ_CAP_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x288) /* outstanding page request capability */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PR_OUT_REQ_ALC_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x28C) /* outstanding page request capability */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_TPH_EXTEND_CAP_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_TPH_REQ_CAP_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2A4) /* tph request capability register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_TPH_REQ_CTRL_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2A8) /* tph requester control register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PASID_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2C0) /* PASID capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_PASID_CAP_CTRL_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x2C4) /* PASID capability and control */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DEVICE_SERIAL_NUMBER_CAP_HEADER_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4E0) /* device serial number extended capability header */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SERIAL_LNUM_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4E4) /* serial low number register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_SERIAL_HNUM_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x4E8) /* serial high number register */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X00_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x500) /* Extend capability register 00 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X04_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x504) /* Extend capability register 04 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X08_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x508) /* Extend capability register 08 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X0C_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x50C) /* Extend capability register 0c */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X10_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x510) /* Extend capability register 10 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X14_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x514) /* Extend capability register 14 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X18_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x518) /* Extend capability register 18 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DUMMY_CAP_0X1C_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x51C) /* Extend capability register 1c */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ACS_CAP_0X00_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x630) /* ACS capability register 00 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_ACS_CAP_0X04_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x634) /* ACS capability register 04 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DL_FEATURE_CAP_REG00_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x700) /* DL feature capability register 00 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DL_FEATURE_CAP_REG04_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x704) /* DL feature capability register 04 */ +#define CSR_HIPCIEC_EPFN_CFGSPACE_DL_FEATURE_CAP_REG08_REG \ + (CSR_HIPCIEC_EPFN_CFGSPACE_BASE + 0x708) /* DL feature capability register 08 */ + +/* HIPCIEC_EVF_CFGSPACE Base address of Module's Register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_BASE (0x40000) + +/* **************************************************************************** */ +/* HIPCIEC_EVF_CFGSPACE Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_ID_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x0) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CMDSTS_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x4) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CLSREV_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x8) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_MISC_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC) /* This register specify the register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR0_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x10) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR1_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x14) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR2_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x18) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR3_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x1C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR4_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x20) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_BAR5_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x24) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CBUS_PTR_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x28) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_SUBSYS_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_EXPROM_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x30) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_CAPPTR_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x34) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCI_RSVD_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x38) /* reserved */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIHDR_INT_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x3C) /* This register specify the base address register of config space. */ +#define CSR_HIPCIEC_EVF_CFGSPACE_PCIE_CAP_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x40) /* This is the pcie capability header register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CAPBILITY_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x44) /* This register describe the device capability */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x48) /* device control status register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CAPBILITY_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x4C) /* Link capability register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CTRL_STATUS_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x50) /* Link control register \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CAPABILITY_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x54) /* Slot capability register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CTRL_STATUS_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x58) /* Slot control and status register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ROOT_CTRL_STATUS_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x5C) /* Roor control status */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ROOT_STATUS_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x60) /* Root status register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CAPABILITY2_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x64) /* device capability 2 register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DEVICE_CTRL2_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x68) /* Device control register 2 \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CAPABILITY2_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x6C) /* Link capability 2 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_LINK_CTRL_STATUS2_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x70) /* Link control and status 2 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CAP_2_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x74) /* Slot Capabilities 2 Register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_SLOT_CTRL_2_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x78) /* Slot Control 2 Register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_CAP_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x80) /* MSI control and ID regisiter */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_LADDR_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x84) /* MSI low address */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_HADDR_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x88) /* MSI uppr address */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_DATA_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x8C) /* MSI data register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_MASK_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x90) /* MSI mask register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSI_PENDING_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x94) /* MSI pending register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSIX_CAP_HEADER_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xA0) /* MSIX control register \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSIX_TABLE_CTRL_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xA4) /* MSIX table control register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_MSIX_PBA_CTRL_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xA8) /* MSIX pending bit array control register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xB8) /* Virtio Common capability header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_BAR_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xBC) /* Virtio Common configuration structure BAR indicator */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_OFFSET_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC0) /* Virtio Common configuration structure offset */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_COMMON_LENGTH_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC4) /* Virtio Common configuration structure length */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xC8) /* Virtio Notify capability header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_BAR_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xCC) /* Virtio Notification structure BAR indicator */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_OFFSET_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xD0) /* Virtio Notification structure offset */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_LENGTH_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xD4) /* Virtio Notification structure length */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_NOTIFY_OFF_MULTIPLIER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xD8) /* Virtio Notification structure off multiplier */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xDC) /* Virtio ISR capability header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_BAR_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xE0) /* Virtio ISR status structure BAR indicator */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_OFFSET_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xE4) /* Virtio ISR status structure offset */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_ISR_LENGTH_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xE8) /* Virtio ISR status structure length */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xEC) /* Virtio Device Specify capability header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_BAR_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xF0) /* Virtio Device Specify configuration structure BAR indicator */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_OFFSET_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xF4) /* Virtio Device Specify configuration structure offset */ +#define CSR_HIPCIEC_EVF_CFGSPACE_VIRTIO_DEVICE_LENGTH_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0xF8) /* Virtio Device Specify configuration structure length */ +#define CSR_HIPCIEC_EVF_CFGSPACE_AER_CAP_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x100) /* Advance Error Report capability header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_UNCR_ERR_STATUS_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x104) /* uncorrectable error status */ +#define CSR_HIPCIEC_EVF_CFGSPACE_UNCR_ERR_MASK_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x108) /* uncorrectable error mask */ +#define CSR_HIPCIEC_EVF_CFGSPACE_UNCR_ERR_SEVERITY_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x10C) /* uncorrectable error serverity */ +#define CSR_HIPCIEC_EVF_CFGSPACE_COR_ERR_STATUS_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x110) /* Correctable error status */ +#define CSR_HIPCIEC_EVF_CFGSPACE_COR_ERR_MASK_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x114) /* correctable error mask */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ADVACD_CAP_CTRL_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x118) /* advanced error capabilities and control register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_FIRST_HEADER_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x11C) /* First DW header log \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_SECOND_HEADER_LOG_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x120) /* Second DW header log */ +#define CSR_HIPCIEC_EVF_CFGSPACE_THIRD_HEADER_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x124) /* Third DW header log \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_FOUR_HEADER_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x128) /* Forth DW header log */ +#define CSR_HIPCIEC_EVF_CFGSPACE_FIRST_PREFIX_LOG_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x138) /* First DW prefix log \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ARI_CAP_HEADER_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x150) /* ARI capability header \ + */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ARI_CTRL_REG (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x154) /* ARI control and capability */ +#define CSR_HIPCIEC_EVF_CFGSPACE_TPH_EXTEND_CAP_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2A0) /* pcie tph extended capability header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_TPH_REQ_CAP_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2A4) /* tph request capability register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_TPH_REQ_CTRL_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x2A8) /* tph requester control register */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X00_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x500) /* Extend capability register 00 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X04_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x504) /* Extend capability register 04 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X08_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x508) /* Extend capability register 08 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X0C_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x50C) /* Extend capability register 0c */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X10_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x510) /* Extend capability register 10 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X14_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x514) /* Extend capability register 14 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X18_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x518) /* Extend capability register 18 */ +#define CSR_HIPCIEC_EVF_CFGSPACE_DUMMY_CAP_0X1C_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x51C) /* Extend capability register 1c */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ACS_EXT_CAP_HEADER_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x630) /* ACS Extended Capability Header */ +#define CSR_HIPCIEC_EVF_CFGSPACE_ACS_CAPABILITY_REG \ + (CSR_HIPCIEC_EVF_CFGSPACE_BASE + 0x634) /* ACS Capability Register */ + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_core_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_core_typedef.h new file mode 100644 index 000000000..a3d9f2626 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_core_typedef.h @@ -0,0 +1,118101 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : pcie5_core_typedef.h + * Project line : Platform And Technologies Development + * Department : CAD Development Department + * Version : 1.0 + * Date : + * Description : PCIE Controller 5.0 Version 200 + * Others : Generated automatically by nManager V5.1 + * History : 2021/01/07 09:08:20 Create file + */ + +#ifndef PCIE5_CORE_TYPEDEF_H +#define PCIE5_CORE_TYPEDEF_H + +/* Define the union csr_apb_timeout_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_int_set : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timeout_int_set_u; + +/* Define the union csr_apb_timeout_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_int_mask : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timeout_int_mask_u; + +/* Define the union csr_apb_timeout_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_int_sts : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timeout_int_status_u; + +/* Define the union csr_apb_timeout_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_int_ro : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timeout_int_ro_u; + +/* Define the union csr_pcie_top_local_int_en_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 top_int_ni_en : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_top_local_int_en_ni_u; + +/* Define the union csr_pcie_top_local_int_en_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 top_int_ce_en : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_top_local_int_en_ce_u; + +/* Define the union csr_pcie_top_local_int_en_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 top_int_nfe_en : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_top_local_int_en_nfe_u; + +/* Define the union csr_pcie_top_local_int_en_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 top_int_fe_en : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_top_local_int_en_fe_u; + +/* Define the union csr_apb_wr_last_add_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_last_waddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_wr_last_add_u; + +/* Define the union csr_apb_wr_times_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_wr_times : 28; /* [27:0] */ + u32 rsv_8 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_wr_times_u; + +/* Define the union csr_apb_timer_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_interval : 28; /* [27:0] */ + u32 rsv_9 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timer_ctrl_u; + +/* Define the union csr_apb_timeout_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_int_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timeout_info_u; + +/* Define the union csr_apb_time_out_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timeout_num : 8; /* [7:0] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_time_out_num_u; + +/* Define the union csr_apb_timeout_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_timetou_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_timeout_rdata_u; + +/* Define the union csr_peh_axi_user_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axuser_fp : 1; /* [0] */ + u32 axuser_type : 4; /* [4:1] */ + u32 axuser_cleaninv : 1; /* [5] */ + u32 axuser_fna : 1; /* [6] */ + u32 axuser_fa : 1; /* [7] */ + u32 axuser_requestid : 16; /* [23:8] */ + u32 axuser_cmdtype : 3; /* [26:24] */ + u32 rsv_11 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_peh_axi_user_u; + +/* Define the union csr_iep_tc_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iep_tc_id : 3; /* [2:0] */ + u32 rsv_12 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_iep_tc_id_u; + +/* Define the union csr_iep_credit_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iep_data_cdt_cnt_clr : 1; /* [0] */ + u32 iep_hed_cdt_cnt_clr : 1; /* [1] */ + u32 iep_cdt_active_dis : 1; /* [2] */ + u32 rsv_13 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_iep_credit_clr_u; + +/* Define the union csr_iep_reg_on_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iep_reg_on : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_iep_reg_on_u; + +/* Define the union csr_apb_reserve_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_rsv_rdata : 1; /* [0] */ + u32 rsv_15 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_apb_reserve_rdata_u; + +/* Define the union csr_pcie_peh_msi_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 peh_msi_info0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_peh_msi_dfx0_u; + +/* Define the union csr_pcie_peh_msi_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 peh_msi_info1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_peh_msi_dfx1_u; + +/* Define the union csr_pcie_peh_msi_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 peh_msi_info2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_peh_msi_dfx2_u; + +/* Define the union csr_pcie_peh_msi_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 peh_msi_info3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_top_reg_pcie_peh_msi_dfx3_u; + +/* Define the union csr_port_reset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sft_rst : 16; /* [15:0] */ + u32 port_ctrl_sft_rst : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_port_reset_u; + +/* Define the union csr_phy_reset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sticky_sft_rst : 16; /* [15:0] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_phy_reset_u; + +/* Define the union csr_core_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_coreclk_detect : 16; /* [15:0] */ + u32 dfx_coreclk_exist : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_core_clk_flg_u; + +/* Define the union csr_pcs_soft_rest_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_lane_sft_rst : 16; /* [15:0] */ + u32 pcs_sft_rst : 8; /* [23:16] */ + u32 pcs_com_sft_rst : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_pcs_soft_rest_u; + +/* Define the union csr_pcie_ap_axi_sft_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_axi_sft_rst : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_pcie_ap_axi_sft_rst_u; + +/* Define the union csr_pcie_core_tl_com_sft_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_tl_com_sft_rst : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_pcie_core_tl_com_sft_rst_u; + +/* Define the union csr_pcie_core_phy_com_sft_rst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_phy_com_sft_rst : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_pcie_core_phy_com_sft_rst_u; + +/* Define the union csr_pcie_icg_en_pipe_lane_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_icg_en_pipe_lane : 16; /* [15:0] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_pcie_icg_en_pipe_lane_u; + +/* Define the union csr_pcie_icg_en_core_phy_lane_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_icg_en_core_phy_lane : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_clkrst_ctrl_reg_pcie_icg_en_core_phy_lane_u; + +/* Define the union csr_port_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_en : 16; /* [15:0] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_port_en_u; + +/* Define the union csr_port_reset_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkdown_rst_num : 16; /* [15:0] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_port_reset_cfg_u; + +/* Define the union csr_turbo_sim_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 turbo_sim : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_turbo_sim_sel_u; + +/* Define the union csr_local_loopback_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_loopback_mode : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_local_loopback_mode_u; + +/* Define the union csr_pcie_sram_timing_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_timing_cfg_svt_sramdp : 13; /* [12:0] */ + u32 rsv_4 : 3; /* [15:13] */ + u32 ram_timing_cfg_svt_srambp : 15; /* [30:16] */ + u32 rsv_5 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_timing_cfg_0_u; + +/* Define the union csr_pcie_sram_timing_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_timing_cfg_svt_sramtp : 13; /* [12:0] */ + u32 rsv_6 : 3; /* [15:13] */ + u32 ram_timing_cfg_svt_sramhd : 13; /* [28:16] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_timing_cfg_1_u; + +/* Define the union csr_pcie_sram_timing_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_timing_cfg_svt_sramhc : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 ram_timing_cfg_lvt_sramdp : 13; /* [28:16] */ + u32 rsv_9 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_timing_cfg_2_u; + +/* Define the union csr_pcie_sram_timing_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_timing_cfg_lvt_srambp : 15; /* [14:0] */ + u32 rsv_10 : 1; /* [15] */ + u32 ram_timing_cfg_lvt_sramtp : 13; /* [28:16] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_timing_cfg_3_u; + +/* Define the union csr_pcie_sram_timing_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_timing_cfg_lvt_sramhd : 13; /* [12:0] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 ram_timing_cfg_lvt_sramhc : 13; /* [28:16] */ + u32 rsv_13 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_timing_cfg_4_u; + +/* Define the union csr_pcie_sram_ctrl_bus_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sram_ctrl_bus_sp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_ctrl_bus_sp_u; + +/* Define the union csr_pcie_sram_ctrl_bus_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sram_ctrl_bus_tp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sram_ctrl_bus_tp_u; + +/* Define the union csr_glb_sram_ctrl_bus_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sram_ctrl_bus_en : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_glb_sram_ctrl_bus_en_u; + +/* Define the union csr_insert_skp_data_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 skp_data_parity_err_inject_en : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_insert_skp_data_parity_err_u; + +/* Define the union csr_glb_pciec_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pciec_mode_sel : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_glb_pciec_mode_sel_u; + +/* Define the union csr_pcie_release_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_release_date : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_release_i_u; + +/* Define the union csr_pcie_version_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_version_i_u; + +/* Define the union csr_apb_eco_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_regif : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_apb_eco_u; + +/* Define the union csr_port07_link_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_link_mode : 3; /* [2:0] */ + u32 rsv_18 : 1; /* [3] */ + u32 port1_link_mode : 3; /* [6:4] */ + u32 rsv_19 : 1; /* [7] */ + u32 port2_link_mode : 3; /* [10:8] */ + u32 rsv_20 : 1; /* [11] */ + u32 port3_link_mode : 3; /* [14:12] */ + u32 rsv_21 : 1; /* [15] */ + u32 port4_link_mode : 3; /* [18:16] */ + u32 rsv_22 : 1; /* [19] */ + u32 port5_link_mode : 3; /* [22:20] */ + u32 rsv_23 : 1; /* [23] */ + u32 port6_link_mode : 3; /* [26:24] */ + u32 rsv_24 : 1; /* [27] */ + u32 port7_link_mode : 3; /* [30:28] */ + u32 rsv_25 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_port07_link_mode_u; + +/* Define the union csr_port815_link_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port8_link_mode : 3; /* [2:0] */ + u32 rsv_26 : 1; /* [3] */ + u32 port9_link_mode : 3; /* [6:4] */ + u32 rsv_27 : 1; /* [7] */ + u32 port10_link_mode : 3; /* [10:8] */ + u32 rsv_28 : 1; /* [11] */ + u32 port11_link_mode : 3; /* [14:12] */ + u32 rsv_29 : 1; /* [15] */ + u32 port12_link_mode : 3; /* [18:16] */ + u32 rsv_30 : 1; /* [19] */ + u32 port13_link_mode : 3; /* [22:20] */ + u32 rsv_31 : 1; /* [23] */ + u32 port14_link_mode : 3; /* [26:24] */ + u32 rsv_32 : 1; /* [27] */ + u32 port15_link_mode : 3; /* [30:28] */ + u32 rsv_33 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_port815_link_mode_u; + +/* Define the union csr_port_rst_dly_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rst_dly_cnt : 16; /* [15:0] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_port_rst_dly_cnt_u; + +/* Define the union csr_hilink_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hlk_int_set : 20; /* [19:0] */ + u32 rsv_35 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_hilink_int_set_u; + +/* Define the union csr_hilink_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hlk_int_mask : 20; /* [19:0] */ + u32 rsv_36 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_hilink_int_mask_u; + +/* Define the union csr_hilink_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hlk_int_ro : 20; /* [19:0] */ + u32 rsv_37 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_hilink_int_ro_u; + +/* Define the union csr_hilink_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hlk_int_status : 20; /* [19:0] */ + u32 rsv_38 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_hilink_int_status_u; + +/* Define the union csr_hilink_int_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hlk_int_ni_en : 1; /* [0] */ + u32 hlk_int_ce_en : 1; /* [1] */ + u32 hlk_int_nfe_en : 1; /* [2] */ + u32 hlk_int_fe_en : 1; /* [3] */ + u32 rsv_39 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_hilink_int_sel_u; + +/* Define the union csr_core_int_ni_set_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_set_0 : 24; /* [23:0] */ + u32 rsv_40 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_set_0_u; + +/* Define the union csr_core_int_ni_msk_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_mask_0 : 24; /* [23:0] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_msk_0_u; + +/* Define the union csr_core_int_ni_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_status_0 : 24; /* [23:0] */ + u32 rsv_42 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_status_0_u; + +/* Define the union csr_core_int_ni_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_ro_0 : 24; /* [23:0] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_ro_0_u; + +/* Define the union csr_core_int_ni_set_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_set_1 : 27; /* [26:0] */ + u32 rsv_44 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_set_1_u; + +/* Define the union csr_core_int_ni_msk_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_mask_1 : 27; /* [26:0] */ + u32 rsv_45 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_msk_1_u; + +/* Define the union csr_core_int_ni_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_status_1 : 27; /* [26:0] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_status_1_u; + +/* Define the union csr_core_int_ni_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ni_ro_1 : 27; /* [26:0] */ + u32 rsv_47 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ni_ro_1_u; + +/* Define the union csr_core_int_ce_set_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_set_0 : 24; /* [23:0] */ + u32 rsv_48 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_set_0_u; + +/* Define the union csr_core_int_ce_msk_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_mask_0 : 24; /* [23:0] */ + u32 rsv_49 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_msk_0_u; + +/* Define the union csr_core_int_ce_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_status_0 : 24; /* [23:0] */ + u32 rsv_50 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_status_0_u; + +/* Define the union csr_core_int_ce_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_ro_0 : 24; /* [23:0] */ + u32 rsv_51 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_ro_0_u; + +/* Define the union csr_core_int_ce_set_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_set_1 : 27; /* [26:0] */ + u32 rsv_52 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_set_1_u; + +/* Define the union csr_core_int_ce_msk_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_mask_1 : 27; /* [26:0] */ + u32 rsv_53 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_msk_1_u; + +/* Define the union csr_core_int_ce_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_status_1 : 27; /* [26:0] */ + u32 rsv_54 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_status_1_u; + +/* Define the union csr_core_int_ce_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_ce_ro_1 : 27; /* [26:0] */ + u32 rsv_55 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_ce_ro_1_u; + +/* Define the union csr_core_int_nfe_set_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_set_0 : 24; /* [23:0] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_set_0_u; + +/* Define the union csr_core_int_nfe_msk_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_mask_0 : 24; /* [23:0] */ + u32 rsv_57 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_msk_0_u; + +/* Define the union csr_core_int_nfe_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_status_0 : 24; /* [23:0] */ + u32 rsv_58 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_status_0_u; + +/* Define the union csr_core_int_nfe_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_ro_0 : 24; /* [23:0] */ + u32 rsv_59 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_ro_0_u; + +/* Define the union csr_core_int_nfe_set_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_set_1 : 27; /* [26:0] */ + u32 rsv_60 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_set_1_u; + +/* Define the union csr_core_int_nfe_msk_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_mask_1 : 27; /* [26:0] */ + u32 rsv_61 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_msk_1_u; + +/* Define the union csr_core_int_nfe_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_status_1 : 27; /* [26:0] */ + u32 rsv_62 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_status_1_u; + +/* Define the union csr_core_int_nfe_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_nfe_ro_1 : 27; /* [26:0] */ + u32 rsv_63 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_nfe_ro_1_u; + +/* Define the union csr_core_int_fe_set_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_set_0 : 24; /* [23:0] */ + u32 rsv_64 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_set_0_u; + +/* Define the union csr_core_int_fe_msk_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_mask_0 : 24; /* [23:0] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_msk_0_u; + +/* Define the union csr_core_int_fe_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_status_0 : 24; /* [23:0] */ + u32 rsv_66 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_status_0_u; + +/* Define the union csr_core_int_fe_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_ro_0 : 24; /* [23:0] */ + u32 rsv_67 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_ro_0_u; + +/* Define the union csr_core_int_fe_set_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_set_1 : 27; /* [26:0] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_set_1_u; + +/* Define the union csr_core_int_fe_msk_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_mask_1 : 27; /* [26:0] */ + u32 rsv_69 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_msk_1_u; + +/* Define the union csr_core_int_fe_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_status_1 : 27; /* [26:0] */ + u32 rsv_70 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_status_1_u; + +/* Define the union csr_core_int_fe_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_int_fe_ro_1 : 27; /* [26:0] */ + u32 rsv_71 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_int_fe_ro_1_u; + +/* Define the union csr_core_glb_misc_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hipciec_phy_mode : 1; /* [0] */ + u32 rsv_72 : 15; /* [15:1] */ + u32 cfg_txbuf_mode : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_core_glb_misc_0_u; + +/* Define the union csr_mac_cdc_dptx_fifo_thres_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_dptx_syncbuf_ae_th : 2; /* [1:0] */ + u32 rsv_73 : 6; /* [7:2] */ + u32 cfg_cdc_dptx_syncbuf_af_th : 2; /* [9:8] */ + u32 rsv_74 : 6; /* [15:10] */ + u32 cfg_cdc_dptx_asynbuf_ae_th : 5; /* [20:16] */ + u32 rsv_75 : 3; /* [23:21] */ + u32 cfg_cdc_dptx_asynbuf_af_th : 5; /* [28:24] */ + u32 rsv_76 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_mac_cdc_dptx_fifo_thres_u; + +/* Define the union csr_mac_cdc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cdc_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_mac_cdc_status_u; + +/* Define the union csr_mac_cdc_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 global2cdc_dfx_lane_sel : 16; /* [15:0] */ + u32 cfg_cdc_dp_txbuf_protect_cnt_th : 3; /* [18:16] */ + u32 global2cdc_dfx_sel : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_mac_cdc_config_u; + +/* Define the union csr_linkdown_rst_reg_ern_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkdown_rst_reg_en : 16; /* [15:0] */ + u32 rsv_77 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_linkdown_rst_reg_ern_u; + +/* Define the union csr_pcie_sds_cs_calib_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sds_cs_calib_done : 16; /* [15:0] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sds_cs_calib_done_u; + +/* Define the union csr_pcie_sds_prbs_err_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sds_prbs_err_status : 16; /* [15:0] */ + u32 rsv_79 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_sds_prbs_err_st_u; + +/* Define the union csr_pcie_link_down_rst_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkdown_rst_en : 16; /* [15:0] */ + u32 rsv_80 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_link_down_rst_en_u; + +/* Define the union csr_pcie_link_down_clr_port_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkdown_clr_port_en : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_core_ctrl_reg_pcie_link_down_clr_port_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_0_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_1_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_2_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_3_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_4_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_5_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_6_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_tx_fc_init_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_init_cycle : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_init_cycle_u; + +/* Define the union csr_fc_init_timeout_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_init_alltime_limit : 12; /* [11:0] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_init_timeout_limit_u; + +/* Define the union csr_vc_fc_init_alltimeout_handing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_init_alltime_retrain_en : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_vc_fc_init_alltimeout_handing_u; + +/* Define the union csr_ack_latency_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g1 : 13; /* [12:0] */ + u32 rsv_3 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_g1_u; + +/* Define the union csr_ack_latency_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g2 : 13; /* [12:0] */ + u32 rsv_4 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_g2_u; + +/* Define the union csr_ack_latency_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g3 : 13; /* [12:0] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_g3_u; + +/* Define the union csr_ack_latency_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g4 : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_g4_u; + +/* Define the union csr_ack_nakd_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_nakd_tlp_num_limit : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_nakd_tlp_num_u; + +/* Define the union csr_dfx_dup_ack_num_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dup_ack_num_limit : 8; /* [7:0] */ + u32 dl_dup_ack_num_limit_en : 1; /* [8] */ + u32 rsv_8 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_dup_ack_num_limit_u; + +/* Define the union csr_dfx_nak_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nak_time_limit : 13; /* [12:0] */ + u32 dl_nak_time_limit_en : 1; /* [13] */ + u32 rsv_9 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_nak_time_limit_u; + +/* Define the union csr_credit_null_for_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_cr_null_time_limit : 17; /* [16:0] */ + u32 tl_dl_cr_null_time_limit_en : 1; /* [17] */ + u32 rsv_10 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_credit_null_for_set_u; + +/* Define the union csr_replay_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_replay_cycle : 13; /* [12:0] */ + u32 dl_replay_cycle_extended : 15; /* [27:13] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_replay_cycle_u; + +/* Define the union csr_tx_fc_update_p_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g1 : 13; /* [12:0] */ + u32 rsv_12 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_g1_u; + +/* Define the union csr_tx_fc_update_p_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g2 : 13; /* [12:0] */ + u32 rsv_13 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_g2_u; + +/* Define the union csr_tx_fc_update_p_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g3 : 13; /* [12:0] */ + u32 rsv_14 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_g3_u; + +/* Define the union csr_tx_fc_update_p_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g4 : 13; /* [12:0] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_g4_u; + +/* Define the union csr_rx_fc_update_time_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_rx_fc_update_time_limit : 12; /* [11:0] */ + u32 dl_rx_fc_update_time_limit_en : 1; /* [12] */ + u32 rsv_16 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_rx_fc_update_time_limit_u; + +/* Define the union csr_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_17 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ecc_err_cnt_1bit_u; + +/* Define the union csr_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 data_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 data_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 data_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_18 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ecc_err_cnt_2bit_u; + +/* Define the union csr_data_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_19 : 6; /* [15:10] */ + u32 data_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_data_ram0_ecc_err_addr_u; + +/* Define the union csr_dfx_lcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_lcrc_err_num : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_lcrc_err_num_u; + +/* Define the union csr_dfx_dcrc_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dcrc_err_num : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_dcrc_err_num_u; + +/* Define the union csr_dfx_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dlcmsm_state : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 dl_vc0_init_fc_state : 3; /* [6:4] */ + u32 dl_vc1_init_fc_state : 3; /* [9:7] */ + u32 dl_vc2_init_fc_state : 3; /* [12:10] */ + u32 dl_vc3_init_fc_state : 3; /* [15:13] */ + u32 dl_vc4_init_fc_state : 3; /* [18:16] */ + u32 dl_vc5_init_fc_state : 3; /* [21:19] */ + u32 dl_vc6_init_fc_state : 3; /* [24:22] */ + u32 dl_vc7_init_fc_state : 3; /* [27:25] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_fsm_state_u; + +/* Define the union csr_dfx_retry_str_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_start_seq : 12; /* [11:0] */ + u32 dl_retry_start_seq_en : 1; /* [12] */ + u32 rsv_25 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_retry_str_seq_u; + +/* Define the union csr_dfx_retry_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_retry_fifo_w_ptr : 14; /* [13:0] */ + u32 rsv_26 : 2; /* [15:14] */ + u32 dl_retry_fifo_r_ptr : 14; /* [29:16] */ + u32 dl_retry_fifo_full : 1; /* [30] */ + u32 dl_retry_fifo_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_retry_status_u; + +/* Define the union csr_apb_read_retry_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_address : 10; /* [9:0] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_ctrl_u; + +/* Define the union csr_apb_read_retry_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data0_u; + +/* Define the union csr_apb_read_retry_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data1_u; + +/* Define the union csr_apb_read_retry_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data2_u; + +/* Define the union csr_apb_read_retry_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data3_u; + +/* Define the union csr_apb_read_retry_data4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data4_u; + +/* Define the union csr_apb_read_retry_data5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data5_u; + +/* Define the union csr_apb_read_retry_data6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data6_u; + +/* Define the union csr_apb_read_retry_data7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data7_u; + +/* Define the union csr_dl_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_status : 1; /* [0] */ + u32 ecc_1b_err_dl_int_status : 1; /* [1] */ + u32 ecc_2b_err_dl_int_status : 1; /* [2] */ + u32 retrain_dl_int_status : 1; /* [3] */ + u32 link_fail_dl_int_status : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_status : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_status : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_status : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_status : 1; /* [8] */ + u32 rx_fc_update_timeout_int_status : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_status : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_status : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_status : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_status : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_status : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_status : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_status : 1; /* [16] */ + u32 dl_down_int_status : 1; /* [17] */ + u32 dl_up_int_status : 1; /* [18] */ + u32 rsv_28 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_int_status_u; + +/* Define the union csr_dl_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_msk : 1; /* [0] */ + u32 ecc_1b_err_dl_int_msk : 1; /* [1] */ + u32 ecc_2b_err_dl_int_msk : 1; /* [2] */ + u32 retrain_dl_int_msk : 1; /* [3] */ + u32 link_fail_dl_int_msk : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_msk : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_msk : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_msk : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_msk : 1; /* [8] */ + u32 rx_fc_update_timeout_int_msk : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_msk : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_msk : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_msk : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_msk : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_msk : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_msk : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_msk : 1; /* [16] */ + u32 dl_down_int_mask : 1; /* [17] */ + u32 dl_up_int_mask : 1; /* [18] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_int_mask_u; + +/* Define the union csr_dl_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_ro : 1; /* [0] */ + u32 ecc_1b_err_dl_int_ro : 1; /* [1] */ + u32 ecc_2b_err_dl_int_ro : 1; /* [2] */ + u32 retrain_dl_int_ro : 1; /* [3] */ + u32 link_fail_dl_int_ro : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_ro : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_ro : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_ro : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_ro : 1; /* [8] */ + u32 rx_fc_update_timeout_int_ro : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_ro : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_ro : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_ro : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_ro : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_ro : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_ro : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_ro : 1; /* [16] */ + u32 dl_down_int_ro : 1; /* [17] */ + u32 dl_up_int_ro : 1; /* [18] */ + u32 rsv_30 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_int_ro_u; + +/* Define the union csr_dl_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_timeout_dl_int_set : 1; /* [0] */ + u32 ecc_1b_err_dl_int_set : 1; /* [1] */ + u32 ecc_2b_err_dl_int_set : 1; /* [2] */ + u32 retrain_dl_int_set : 1; /* [3] */ + u32 link_fail_dl_int_set : 1; /* [4] */ + u32 dl_dup_tlp_ack_cnt_rollover_int_set : 1; /* [5] */ + u32 dl_nak_timer_timeout_int_set : 1; /* [6] */ + u32 tl_dl_credit_null_timeout_int_set : 1; /* [7] */ + u32 dl_mac_retrain_cnt_over_int_set : 1; /* [8] */ + u32 rx_fc_update_timeout_int_set : 1; /* [9] */ + u32 dl_correct_err_cnt_timeout_int_set : 1; /* [10] */ + u32 rx_fc_vc0_update_timeout_p_int_set : 1; /* [11] */ + u32 rx_fc_vc0_update_timeout_np_int_set : 1; /* [12] */ + u32 rx_fc_vc0_update_timeout_cpl_int_set : 1; /* [13] */ + u32 rx_fc_vc1_update_timeout_p_int_set : 1; /* [14] */ + u32 rx_fc_vc1_update_timeout_np_int_set : 1; /* [15] */ + u32 rx_fc_vc1_update_timeout_cpl_int_set : 1; /* [16] */ + u32 dl_down_int_set : 1; /* [17] */ + u32 dl_up_int_set : 1; /* [18] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_int_set_u; + +/* Define the union csr_infinite_credit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_infinite_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_infinite_credit_en_u; + +/* Define the union csr_tx_vedndor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_vendor_dllp_data : 24; /* [23:0] */ + u32 tx_vendor_dllp_req : 1; /* [24] */ + u32 tx_vendor_dllp_done : 1; /* [25] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_vedndor_dllp_u; + +/* Define the union csr_rx_vendor_dllp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_vendor_dllp_data : 24; /* [23:0] */ + u32 rx_vendor_dllp_vld : 1; /* [24] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_rx_vendor_dllp_u; + +/* Define the union csr_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram0_allow_correct_n : 1; /* [0] */ + u32 ram0_insert_1bit_err : 1; /* [1] */ + u32 ram0_insert_2bit_err : 1; /* [2] */ + u32 ram1_allow_correct_n : 1; /* [3] */ + u32 ram1_insert_1bit_err : 1; /* [4] */ + u32 ram1_insert_2bit_err : 1; /* [5] */ + u32 ram2_allow_correct_n : 1; /* [6] */ + u32 ram2_insert_1bit_err : 1; /* [7] */ + u32 ram2_insert_2bit_err : 1; /* [8] */ + u32 ram3_allow_correct_n : 1; /* [9] */ + u32 ram3_insert_1bit_err : 1; /* [10] */ + u32 ram3_insert_2bit_err : 1; /* [11] */ + u32 ram0_insert_err_mode : 1; /* [12] */ + u32 ram1_insert_err_mode : 1; /* [13] */ + u32 ram2_insert_err_mode : 1; /* [14] */ + u32 ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_sram_ecc_cfg_u; + +/* Define the union csr_dfx_apb_read_retry_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_done : 1; /* [0] */ + u32 rsv_36 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_apb_read_retry_done_u; + +/* Define the union csr_dfx_update_time_cycle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_update_time_cycle : 12; /* [11:0] */ + u32 rsv_37 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_update_time_cycle_u; + +/* Define the union csr_dfx_crc_insert_error_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_dcrc_insert_err_en : 1; /* [0] */ + u32 dfx_lcrc_insert_err_en : 1; /* [1] */ + u32 rsv_38 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_crc_insert_error_u; + +/* Define the union csr_dfx_mac_bp_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_bp_timer : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_mac_bp_timer_u; + +/* Define the union csr_dfx_retry_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_retry_cnt_u; + +/* Define the union csr_fc_ph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_ph_cnt_config : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_ph_cnt_config_u; + +/* Define the union csr_fc_pd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_pd_cnt_config : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_pd_cnt_config_u; + +/* Define the union csr_fc_nph_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_nph_cnt_config : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_nph_cnt_config_u; + +/* Define the union csr_fc_npd_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_npd_cnt_config : 12; /* [11:0] */ + u32 rsv_44 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_npd_cnt_config_u; + +/* Define the union csr_fc_cplh_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cplh_cnt_config : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_cplh_cnt_config_u; + +/* Define the union csr_fc_cpld_cnt_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fc_cpld_cnt_config : 12; /* [11:0] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_fc_cpld_cnt_config_u; + +/* Define the union csr_dl_mac_retrain_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_cnt : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_mac_retrain_cnt_u; + +/* Define the union csr_dl_mac_retrain_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_mac_retrain_limit : 8; /* [7:0] */ + u32 dl_mac_retrain_linkdown_en : 1; /* [8] */ + u32 rsv_48 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_mac_retrain_limit_u; + +/* Define the union csr_init_fc_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_fc_send_en : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_init_fc_send_en_u; + +/* Define the union csr_dfx_dllp_rx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_rx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_dllp_rx_count_num_u; + +/* Define the union csr_dfx_dllp_tx_count_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_tx_count_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_dllp_tx_count_num_u; + +/* Define the union csr_dfx_send_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 send_ack_en : 1; /* [0] */ + u32 send_nak_en : 1; /* [1] */ + u32 send_update_en : 1; /* [2] */ + u32 send_retry_en : 1; /* [3] */ + u32 dl_err_cor_bad_dllp_mask : 1; /* [4] */ + u32 dl_err_fatal_protocol_error_mask : 1; /* [5] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_send_en_u; + +/* Define the union csr_dfx_seq_num_change_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 seq_num_change_en : 1; /* [0] */ + u32 seq_num_change : 12; /* [12:1] */ + u32 rsv_51 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_seq_num_change_u; + +/* Define the union csr_dfx_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dllp_type : 8; /* [7:0] */ + u32 dl_dfx_rx_dllp_type_mask : 15; /* [22:8] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_dllp_type_u; + +/* Define the union csr_dfx_rx_update_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_p_update_en : 1; /* [0] */ + u32 vc0_np_update_en : 1; /* [1] */ + u32 vc0_cpl_update_en : 1; /* [2] */ + u32 vc1_p_update_en : 1; /* [3] */ + u32 vc1_np_update_en : 1; /* [4] */ + u32 vc1_cpl_update_en : 1; /* [5] */ + u32 rsv_53 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_rx_update_en_u; + +/* Define the union csr_dfx_rx_nak_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nak_count : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_rx_nak_count_u; + +/* Define the union csr_dfx_rx_bad_dllp_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_dllp_type : 8; /* [7:0] */ + u32 rx_bad_dllp : 1; /* [8] */ + u32 rsv_55 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_rx_bad_dllp_type_u; + +/* Define the union csr_dfx_ackd_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ackd_seq : 12; /* [11:0] */ + u32 rsv_56 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_ackd_seq_u; + +/* Define the union csr_dfx_next_transmit_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_transmit_seq : 12; /* [11:0] */ + u32 rsv_57 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_next_transmit_seq_u; + +/* Define the union csr_dfx_next_rcv_seq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 next_rcv_seq : 12; /* [11:0] */ + u32 rsv_58 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_next_rcv_seq_u; + +/* Define the union csr_eco_dl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_up_config : 1; /* [0] */ + u32 reg_ignore_dllp_type_bit4 : 1; /* [1] */ + u32 reg_sent_one_pm_ack_en : 1; /* [2] */ + u32 eco_dl : 13; /* [15:3] */ + u32 rsv_59 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_eco_dl_u; + +/* Define the union csr_tx_feature_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_feature_timer_cfg : 11; /* [10:0] */ + u32 rsv_60 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_feature_timer_cfg_u; + +/* Define the union csr_dl_correct_err_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_correct_err_cnt_cfg_en : 1; /* [0] */ + u32 dl_correct_err_cnt_cfg : 15; /* [15:1] */ + u32 rsv_61 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_correct_err_cnt_cfg_u; + +/* Define the union csr_dl_fc_update_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fc_update_mode_sel : 1; /* [0] */ + u32 rsv_62 : 3; /* [3:1] */ + u32 dl_tx_fc_update_timer_shift : 2; /* [5:4] */ + u32 rsv_63 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_fc_update_mode_sel_u; + +/* Define the union csr_tx_fc_update_np_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g1 : 13; /* [12:0] */ + u32 rsv_64 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_g1_u; + +/* Define the union csr_tx_fc_update_np_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g2 : 13; /* [12:0] */ + u32 rsv_65 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_g2_u; + +/* Define the union csr_tx_fc_update_np_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g3 : 13; /* [12:0] */ + u32 rsv_66 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_g3_u; + +/* Define the union csr_tx_fc_update_np_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g4 : 13; /* [12:0] */ + u32 rsv_67 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_g4_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g1 : 13; /* [12:0] */ + u32 rsv_68 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_g1_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g2 : 13; /* [12:0] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_g2_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g3 : 13; /* [12:0] */ + u32 rsv_70 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_g3_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g4 : 13; /* [12:0] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_g4_u; + +/* Define the union csr_dl_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_int_ce_nfe_sel : 18; /* [17:0] */ + u32 rsv_72 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_int_ce_nfe_sel_u; + +/* Define the union csr_dl_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_ni_int_ro_u; + +/* Define the union csr_dl_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_fe_int_ro_u; + +/* Define the union csr_dl_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_ce_int_ro_u; + +/* Define the union csr_dl_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_nfe_int_ro_u; + +/* Define the union csr_dl_fc_init_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_vcx_fc_init_timeout_status : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dl_fc_init_err_status_u; + +/* Define the union csr_dfx_retry_data_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_data_buffer_w_ptr : 10; /* [9:0] */ + u32 dl_data_buffer_r_ptr : 10; /* [19:10] */ + u32 dl_data_buffer_full : 1; /* [20] */ + u32 dl_data_buffer_empty : 1; /* [21] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_retry_data_buffer_status_u; + +/* Define the union csr_ack_latency_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_g5 : 13; /* [12:0] */ + u32 rsv_75 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_g5_u; + +/* Define the union csr_ack_latency_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_20g : 13; /* [12:0] */ + u32 rsv_76 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_20g_u; + +/* Define the union csr_ack_latency_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_ack_latency_cycle_25g : 13; /* [12:0] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ack_latency_cycle_25g_u; + +/* Define the union csr_tx_fc_update_p_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_g5 : 13; /* [12:0] */ + u32 rsv_78 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_g5_u; + +/* Define the union csr_tx_fc_update_p_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_20g : 13; /* [12:0] */ + u32 rsv_79 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_20g_u; + +/* Define the union csr_tx_fc_update_p_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_p_cycle_25g : 13; /* [12:0] */ + u32 rsv_80 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_25g_u; + +/* Define the union csr_tx_fc_update_np_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_g5 : 13; /* [12:0] */ + u32 rsv_81 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_g5_u; + +/* Define the union csr_tx_fc_update_np_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_20g : 13; /* [12:0] */ + u32 rsv_82 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_20g_u; + +/* Define the union csr_tx_fc_update_np_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_np_cycle_25g : 13; /* [12:0] */ + u32 rsv_83 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_25g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_g5 : 13; /* [12:0] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_g5_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_20g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_20g : 13; /* [12:0] */ + u32 rsv_85 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_20g_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_25g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_tx_fc_update_cpl_cycle_25g : 13; /* [12:0] */ + u32 rsv_86 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_25g_u; + +/* Define the union csr_dfx_dlcmsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ignore_fc_done : 1; /* [0] */ + u32 dfx_receive_feature_en : 1; /* [1] */ + u32 dfx_fc_send_en_ignore_speed : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_dlcmsm_u; + +/* Define the union csr_apb_read_retry_data8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data8_u; + +/* Define the union csr_apb_read_retry_data9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data9_u; + +/* Define the union csr_apb_read_retry_data10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data10_u; + +/* Define the union csr_apb_read_retry_data11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data11_u; + +/* Define the union csr_apb_read_retry_data12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data12_u; + +/* Define the union csr_apb_read_retry_data13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data13_u; + +/* Define the union csr_apb_read_retry_data14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data14_u; + +/* Define the union csr_apb_read_retry_data15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_retry_data_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_retry_data15_u; + +/* Define the union csr_dfx_apb_read_context_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_done : 1; /* [0] */ + u32 rsv_88 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_apb_read_context_done_u; + +/* Define the union csr_apb_read_context_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_dfx_apb_read_context_address : 10; /* [9:0] */ + u32 rsv_89 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_context_ctrl_u; + +/* Define the union csr_apb_read_context_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_len : 11; /* [10:0] */ + u32 apb_read_retry_str_addr : 10; /* [20:11] */ + u32 apb_read_retry_end_addr : 10; /* [30:21] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_context_data0_u; + +/* Define the union csr_apb_read_context_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_str_offset : 4; /* [3:0] */ + u32 apb_read_end_offset : 4; /* [7:4] */ + u32 apb_read_retry_tx_prefix_en : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_context_data1_u; + +/* Define the union csr_apb_read_context_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_read_retry_tx_prefix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_apb_read_context_data2_u; + +/* Define the union csr_context_sram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_allow_correct_n : 1; /* [0] */ + u32 context_ram0_insert_1bit_err : 1; /* [1] */ + u32 context_ram0_insert_2bit_err : 1; /* [2] */ + u32 context_ram1_allow_correct_n : 1; /* [3] */ + u32 context_ram1_insert_1bit_err : 1; /* [4] */ + u32 context_ram1_insert_2bit_err : 1; /* [5] */ + u32 context_ram2_allow_correct_n : 1; /* [6] */ + u32 context_ram2_insert_1bit_err : 1; /* [7] */ + u32 context_ram2_insert_2bit_err : 1; /* [8] */ + u32 context_ram3_allow_correct_n : 1; /* [9] */ + u32 context_ram3_insert_1bit_err : 1; /* [10] */ + u32 context_ram3_insert_2bit_err : 1; /* [11] */ + u32 context_ram0_insert_err_mode : 1; /* [12] */ + u32 context_ram1_insert_err_mode : 1; /* [13] */ + u32 context_ram2_insert_err_mode : 1; /* [14] */ + u32 context_ram3_insert_err_mode : 1; /* [15] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_sram_ecc_cfg_u; + +/* Define the union csr_data_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_93 : 6; /* [15:10] */ + u32 data_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_94 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_data_ram1_ecc_err_addr_u; + +/* Define the union csr_data_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_95 : 6; /* [15:10] */ + u32 data_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_96 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_data_ram2_ecc_err_addr_u; + +/* Define the union csr_data_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_97 : 6; /* [15:10] */ + u32 data_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_98 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_data_ram3_ecc_err_addr_u; + +/* Define the union csr_context_ram_ecc_err_cnt_1bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_1bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_1bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_1bit_err_cnt : 5; /* [19:15] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_ram_ecc_err_cnt_1bit_u; + +/* Define the union csr_context_ram_ecc_err_cnt_2bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_2bit_err_cnt : 5; /* [4:0] */ + u32 context_ram1_dl_ecc_2bit_err_cnt : 5; /* [9:5] */ + u32 context_ram2_dl_ecc_2bit_err_cnt : 5; /* [14:10] */ + u32 context_ram3_dl_ecc_2bit_err_cnt : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_ram_ecc_err_cnt_2bit_u; + +/* Define the union csr_context_ram0_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram0_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_101 : 6; /* [15:10] */ + u32 context_ram0_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_102 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_ram0_ecc_err_addr_u; + +/* Define the union csr_context_ram1_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram1_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_103 : 6; /* [15:10] */ + u32 context_ram1_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_104 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_ram1_ecc_err_addr_u; + +/* Define the union csr_context_ram2_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram2_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_105 : 6; /* [15:10] */ + u32 context_ram2_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_106 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_ram2_ecc_err_addr_u; + +/* Define the union csr_context_ram3_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 context_ram3_dl_ecc_1bit_err_addr : 10; /* [9:0] */ + u32 rsv_107 : 6; /* [15:10] */ + u32 context_ram3_dl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_108 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_context_ram3_ecc_err_addr_u; + +/* Define the union csr_ram_ecc_err_int_sel_ind_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_ram_1bit_ecc_err_status : 4; /* [3:0] */ + u32 data_ram_2bit_ecc_err_status : 4; /* [7:4] */ + u32 context_ram_1bit_ecc_err_status : 4; /* [11:8] */ + u32 context_ram_2bit_ecc_err_status : 4; /* [15:12] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_ram_ecc_err_int_sel_ind_u; + +/* Define the union csr_insert_idle_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 insert_idle_state : 3; /* [2:0] */ + u32 rsv_110 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_insert_idle_fsm_u; + +/* Define the union csr_dfx_mac_err_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_err_num : 8; /* [7:0] */ + u32 rsv_111 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_mac_err_num_u; + +/* Define the union csr_retry_buffer_waterline_x1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x1 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x1 : 9; /* [17:9] */ + u32 rsv_112 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_retry_buffer_waterline_x1_u; + +/* Define the union csr_retry_buffer_waterline_x2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x2 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x2 : 9; /* [17:9] */ + u32 rsv_113 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_retry_buffer_waterline_x2_u; + +/* Define the union csr_retry_buffer_waterline_x4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x4 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x4 : 9; /* [17:9] */ + u32 rsv_114 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_retry_buffer_waterline_x4_u; + +/* Define the union csr_retry_buffer_waterline_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x8 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x8 : 9; /* [17:9] */ + u32 rsv_115 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_retry_buffer_waterline_x8_u; + +/* Define the union csr_retry_buffer_waterline_x16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_retry_context_table_waterline_x16 : 9; /* [8:0] */ + u32 dfx_retry_data_buffer_waterline_x16 : 9; /* [17:9] */ + u32 rsv_116 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_retry_buffer_waterline_x16_u; + +/* Define the union csr_dfx_ack_fffh_inital_mask_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ack_fffh_inital_mask_disable : 1; /* [0] */ + u32 clear_data_buffer_str_addr_sel : 1; /* [1] */ + u32 clear_data_buffer_when_naklast_disable : 1; /* [2] */ + u32 rsv_117 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_ack_fffh_inital_mask_disable_u; + +/* Define the union csr_dfx_tx_dllpg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_ack_block_dllp_disable : 1; /* [0] */ + u32 dllp_pm_req_frequently_disable : 1; /* [1] */ + u32 insert_acknak_disable : 1; /* [2] */ + u32 l1_object_block_dllp_disable : 1; /* [3] */ + u32 block_dllp_when_skp_x16 : 1; /* [4] */ + u32 disable_block_skp_when_dllp_exist : 1; /* [5] */ + u32 vld_dllp_req_sch_en_delay_disable : 1; /* [6] */ + u32 rsv_118 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_dfx_tx_dllpg_u; + +/* Define the union csr_tx_fc_update_p_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_p_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_p_cycel_idle_en : 1; /* [13] */ + u32 rsv_119 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_p_cycle_idle_u; + +/* Define the union csr_tx_fc_update_np_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_np_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_np_cycel_idle_en : 1; /* [13] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_np_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cpl_cycle_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cpl_cycel_idle : 13; /* [12:0] */ + u32 tx_fc_update_cpl_cycel_idle_en : 1; /* [13] */ + u32 rsv_121 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cpl_cycle_idle_u; + +/* Define the union csr_tx_fc_update_cycle_all_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fc_update_cycel_all_idle_en : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_dl_reg_7_tx_fc_update_cycle_all_idle_en_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_0_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_1_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_2_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_3_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_4_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_5_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_6_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_mac_req_eios_to_eleidle_delay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eios_to_eleidle_delay : 6; /* [5:0] */ + u32 rsv_0 : 2; /* [7:6] */ + u32 reg_symbol_unlock_counter_value : 8; /* [15:8] */ + u32 enter_low_power_delay_value : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_req_eios_to_eleidle_delay_u; + +/* Define the union csr_mac_reg_enter_loopback_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_loopback : 1; /* [0] */ + u32 reg_loopback_check_en : 1; /* [1] */ + u32 loopback_sent_eieos_en : 1; /* [2] */ + u32 reg_ds_l0_loopback_en : 1; /* [3] */ + u32 dis_hotrst_sent_eieos_en : 1; /* [4] */ + u32 reg_linkdown_clr_esm_enable_en : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 loopback_master_check_st : 2; /* [9:8] */ + u32 enter_loop_con : 1; /* [10] */ + u32 mac_loc_preset_sigle : 4; /* [14:11] */ + u32 rsv_3 : 1; /* [15] */ + u32 reg_loopback_wait_time : 10; /* [25:16] */ + u32 reg_lpbk_to_eq_en : 1; /* [26] */ + u32 reg_ingnore_link_lanenum_en : 1; /* [27] */ + u32 reg_lpbk_linklane_num_pad : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_enter_loopback_u; + +/* Define the union csr_mac_reg_retrain_link_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_retrain_pulse : 1; /* [0] */ + u32 reg_req_tx_eq : 1; /* [1] */ + u32 max_dp_hw_req_redo_num : 4; /* [5:2] */ + u32 reg_auto_eq_af_eq_fail_mask : 1; /* [6] */ + u32 rsv_5 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_retrain_link_u; + +/* Define the union csr_mac_req_tx_link_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_link_num : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_req_tx_link_num_u; + +/* Define the union csr_mac_req_scramble_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_scramble_disable_gen12 : 1; /* [0] */ + u32 reg_scramble_disable_gen3 : 1; /* [1] */ + u32 reg_rxprecoding_disable : 1; /* [2] */ + u32 reg_txprecoding_disable : 1; /* [3] */ + u32 reg_rxprecoding_force_enable : 1; /* [4] */ + u32 reg_txprecoding_force_enable : 1; /* [5] */ + u32 reg_loopback_use_rx_precoding_en : 1; /* [6] */ + u32 reg_no_eq_use_old_precoding_value : 1; /* [7] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_req_scramble_disable_u; + +/* Define the union csr_mac_reg_skp_intval_sris_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen12 : 13; /* [12:0] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 reg_skp_intvl_sris_gen3 : 9; /* [24:16] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_skp_intval_sris_u; + +/* Define the union csr_mac_reg_dc_balance_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dc_balance_disable : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_dc_balance_disable_u; + +/* Define the union csr_mac_reg_eq_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_equalization_disable : 1; /* [0] */ + u32 reg_ds_eq_p23_disable : 1; /* [1] */ + u32 rsv_11 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_disable_u; + +/* Define the union csr_mac_reg_supported_tx_preset_bm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_supported_tx_preset_bit_map : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_supported_tx_preset_bm_u; + +/* Define the union csr_mac_reg_8g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_8g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_8g_polling_preset_mode : 1; /* [6] */ + u32 cfg_8g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_8g_merit_step : 6; /* [13:8] */ + u32 cfg_8g_reset_eieos : 1; /* [14] */ + u32 rsv_13 : 1; /* [15] */ + u32 reg_8g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_8g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_8g_coeff_post_resolution : 2; /* [21:20] */ + u32 rsv_14 : 2; /* [23:22] */ + u32 reg_8g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_8g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_gen3_tx_coeff_map_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_gen3_tx_coeff_map_mode : 2; /* [1:0] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen3_tx_coeff_map_mode_u; + +/* Define the union csr_mac_reg_eq_phase23_conv_step_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase23_conv_step : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_phase23_conv_step_addr_u; + +/* Define the union csr_mac_reg_eq_phase23_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_eq_phase2_timeout_val : 8; /* [7:0] */ + u32 reg_eq_phase3_timeout_val : 8; /* [15:8] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_phase23_timeout_val_u; + +/* Define the union csr_mac_reg_skp_intval_srns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_srns_gen12 : 13; /* [12:0] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 reg_skp_intvl_srns_gen3 : 9; /* [24:16] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_skp_intval_srns_u; + +/* Define the union csr_mac_reg_n_fts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_n_fts_gen1 : 8; /* [7:0] */ + u32 reg_n_fts_gen2 : 8; /* [15:8] */ + u32 reg_n_fts_gen3 : 8; /* [23:16] */ + u32 rsv_21 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_n_fts_u; + +/* Define the union csr_mac_reg_phystatus_det_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phystatus_det_timeout_val : 10; /* [9:0] */ + u32 rsv_22 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_phystatus_det_timeout_val_u; + +/* Define the union csr_mac_reg_rdn_cross_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_random_cross_timeout_val : 9; /* [8:0] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_rdn_cross_timeout_val_u; + +/* Define the union csr_mac_reg_sel_deemph_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sel_deemph_us : 1; /* [0] */ + u32 reg_no_deemph : 1; /* [1] */ + u32 rsv_24 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_sel_deemph_us_u; + +/* Define the union csr_mac_reg_tx_comp_rcv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_compliance_rcv : 1; /* [0] */ + u32 reg_tx_modify_comp_in_lpbk : 1; /* [1] */ + u32 reg_turn_off_not_test_lane : 1; /* [2] */ + u32 rsv_25 : 13; /* [15:3] */ + u32 reg_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_tx_comp_rcv_u; + +/* Define the union csr_mac_reg_txswing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_txswing : 1; /* [0] */ + u32 rsv_26 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_txswing_u; + +/* Define the union csr_mac_reg_ltssm_tracer_input_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_recap : 1; /* [0] */ + u32 reg_ltssm_tracer_cap_mode : 1; /* [1] */ + u32 rsv_27 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_input_u; + +/* Define the union csr_mac_reg_mac_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status : 1; /* [0] */ + u32 reg_linkdown_intr_status : 1; /* [1] */ + u32 reg_enter_l0_intr_status : 1; /* [2] */ + u32 reg_leave_l0_intr_status : 1; /* [3] */ + u32 reg_enter_disable_intr_status : 1; /* [4] */ + u32 reg_leave_disable_intr_status : 1; /* [5] */ + u32 reg_hot_reset_intr_status : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status : 1; /* [17] */ + u32 pl_eco_rsv_intr_status : 4; /* [21:18] */ + u32 ltssm_tracer_sram_ecc_1bit_err : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status : 1; /* [26] */ + u32 reg_ltssm_intr_status : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status : 1; /* [29] */ + u32 rsv_28 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_mac_int_status_u; + +/* Define the union csr_mac_reg_mac_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_intr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_mac_int_mask_u; + +/* Define the union csr_mac_reg_test_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_counter : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_test_counter_u; + +/* Define the union csr_mac_reg_link_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_cur_link_width : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rxl0s_st : 2; /* [13:12] */ + u32 rx_eval_st : 2; /* [15:14] */ + u32 mac_link_up : 1; /* [16] */ + u32 is_upstream_port_ltssm : 1; /* [17] */ + u32 mac_descramble_disable : 1; /* [18] */ + u32 lane_reverse : 1; /* [19] */ + u32 req_ending_txdata_en : 1; /* [20] */ + u32 rsv_31 : 3; /* [23:21] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rx_deskew_st : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_link_info_u; + +/* Define the union csr_mac_reg_debug_pipe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txdetrx_loopbk : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_32 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe1_u; + +/* Define the union csr_mac_reg_debug_pipe2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_33 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe2_u; + +/* Define the union csr_mac_reg_debug_pipe3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_phystatus : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe3_u; + +/* Define the union csr_mac_reg_debug_pipe4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rate : 2; /* [1:0] */ + u32 rsv_35 : 1; /* [2] */ + u32 rx_link_speed : 5; /* [7:3] */ + u32 mac_ltssm_st : 6; /* [13:8] */ + u32 skp_acc_counter : 5; /* [18:14] */ + u32 txdli_pkt_end : 1; /* [19] */ + u32 txdli_data_fifo_cnt : 3; /* [22:20] */ + u32 txdli_tx_buf_byte_cnt : 6; /* [28:23] */ + u32 txdli_tx_buf_start : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe4_u; + +/* Define the union csr_mac_reg_debug_rxdli_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_str : 16; /* [15:0] */ + u32 mac_rx_end : 8; /* [23:16] */ + u32 mac_rx_err : 4; /* [27:24] */ + u32 mac_rx_null : 2; /* [29:28] */ + u32 mac_rx_data_enable : 1; /* [30] */ + u32 rxdli_st : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_rxdli_1_u; + +/* Define the union csr_mac_reg_debug_link_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_link_num_1_u; + +/* Define the union csr_mac_reg_debug_lane_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_lane_num_1_u; + +/* Define the union csr_mac_reg_debug_txdli_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_fsm : 2; /* [1:0] */ + u32 block_symbol_count : 4; /* [5:2] */ + u32 rxdli_str_offset : 6; /* [11:6] */ + u32 rxdli_tlp_indicator : 1; /* [12] */ + u32 rxdli_cur_state : 2; /* [14:13] */ + u32 rsv_37 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_txdli_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_st : 6; /* [5:0] */ + u32 duration_counter : 4; /* [9:6] */ + u32 mac_rate_1_0 : 2; /* [11:10] */ + u32 train_bit_map : 8; /* [19:12] */ + u32 mac_rate_3_2 : 2; /* [21:20] */ + u32 any_change_pipe_req : 1; /* [22] */ + u32 rcv_eios : 1; /* [23] */ + u32 dl_retrain : 1; /* [24] */ + u32 all_phy_rxeleidle_or_rx_skp_interval_timeout : 1; /* [25] */ + u32 directed_speed_change : 1; /* [26] */ + u32 any_det_eieos_ts : 1; /* [27] */ + u32 rxl0s_to_recovery : 1; /* [28] */ + u32 any_lane_rcv_speed_change : 1; /* [29] */ + u32 changed_speed_recovery : 1; /* [30] */ + u32 suceessful_speed_negotiation : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_output_1_u; + +/* Define the union csr_mac_reg_ltssm_tracer_last_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_last_waddr : 6; /* [5:0] */ + u32 ltssm_tracer_addr_rollback : 1; /* [6] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_last_addr_u; + +/* Define the union csr_mac_reg_symbol_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_counter : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_symbol_unlocl_counter_u; + +/* Define the union csr_mac_reg_mac_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_ro : 1; /* [0] */ + u32 reg_linkdown_intr_status_ro : 1; /* [1] */ + u32 reg_enter_l0_intr_status_ro : 1; /* [2] */ + u32 reg_leave_l0_intr_status_ro : 1; /* [3] */ + u32 reg_enter_disable_intr_status_ro : 1; /* [4] */ + u32 reg_leave_disable_intr_status_ro : 1; /* [5] */ + u32 reg_hot_reset_intr_status_ro : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_ro : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_ro : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_ro : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_ro : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_ro : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_ro : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_ro : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_ro : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_ro : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_ro : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_ro : 1; /* [17] */ + u32 reg_eco_int_0 : 1; /* [18] */ + u32 reg_eco_int_1 : 1; /* [19] */ + u32 reg_eco_int_2 : 1; /* [20] */ + u32 reg_eco_int_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_status_ro : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_status_ro : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_status_ro : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_status_ro : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_status_ro : 1; /* [26] */ + u32 reg_ltssm_intr_status_ro : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_status_ro : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_status_ro : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_status_ro : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_status_ro : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_mac_int_ro_u; + +/* Define the union csr_mac_reg_mac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_linkup_intr_status_set : 1; /* [0] */ + u32 reg_linkdown_intr_status_set : 1; /* [1] */ + u32 reg_enter_l0_intr_status_set : 1; /* [2] */ + u32 reg_leave_l0_intr_status_set : 1; /* [3] */ + u32 reg_enter_disable_intr_status_set : 1; /* [4] */ + u32 reg_leave_disable_intr_status_set : 1; /* [5] */ + u32 reg_hot_reset_intr_status_set : 1; /* [6] */ + u32 rxl0s_to_recovery_intr_status_set : 1; /* [7] */ + u32 reg_phystatus_timeout_intr_status_set : 1; /* [8] */ + u32 reg_deskew_unlock_intr_status_set : 1; /* [9] */ + u32 reg_symbol_unlock_intr_status_set : 1; /* [10] */ + u32 reg_loopback_unlock_intr_status_set : 1; /* [11] */ + u32 reg_deskew_fifo_overflow_intr_status_set : 1; /* [12] */ + u32 reg_enter_l1_timeout_intr_status_set : 1; /* [13] */ + u32 reg_enter_l2_timeout_intr_status_set : 1; /* [14] */ + u32 reg_enter_recovery_lock_intr_status_set : 1; /* [15] */ + u32 reg_enter_recovery_cfg_intr_status_set : 1; /* [16] */ + u32 reg_enter_eq_p3_intr_status_set : 1; /* [17] */ + u32 eco_int_set_0 : 1; /* [18] */ + u32 eco_int_set_1 : 1; /* [19] */ + u32 eco_int_set_2 : 1; /* [20] */ + u32 eco_int_set_3 : 1; /* [21] */ + u32 ltssm_tracer_sram_ecc_1bit_err_intr_set : 1; /* [22] */ + u32 ltssm_tracer_sram_ecc_2bit_err_intr_set : 1; /* [23] */ + u32 reg_enter_g1_recovery_speed_intr_set : 1; /* [24] */ + u32 reg_enter_g2_recovery_speed_intr_set : 1; /* [25] */ + u32 reg_enter_g3_recovery_speed_intr_set : 1; /* [26] */ + u32 reg_ltssm_intr_set : 1; /* [27] */ + u32 reg_enter_lpbk_lock_intr_set : 1; /* [28] */ + u32 reg_enter_g4_recovery_speed_intr_set : 1; /* [29] */ + u32 reg_enter_2025g_recovery_speed_intr_set : 1; /* [30] */ + u32 reg_enter_g5_recovery_speed_intr_set : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_mac_int_set_u; + +/* Define the union csr_mac_reg_enter_l1l2_timeout_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_l1l2_timeout_val : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 reg_wait_beacon_handshake_tm_value : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_enter_l1l2_timeout_val_u; + +/* Define the union csr_mac_reg_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_16g_eq_fix_lp_tx_preset : 4; /* [7:4] */ + u32 reg_comp_lpbk_remote_8g_tx_preset : 4; /* [11:8] */ + u32 reg_comp_lpbk_remote_16g_tx_preset : 4; /* [15:12] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_adj_hilink_mode_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_hilink_mode_en : 6; /* [5:0] */ + u32 gen3_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [6] */ + u32 rcv_speed_pull_up_rx_preset_en : 4; /* [10:7] */ + u32 gen3_eq_phase23_ctle_apt_en : 1; /* [11] */ + u32 rcv_lock_hold_rate : 4; /* [15:12] */ + u32 reg_switch_eq_mode_mask : 1; /* [16] */ + u32 gen4_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [17] */ + u32 gen4_eq_phase23_ctle_apt_en : 1; /* [18] */ + u32 gen3_eq_phase01_ctle_apt_en : 1; /* [19] */ + u32 gen4_eq_phase01_ctle_apt_en : 1; /* [20] */ + u32 gen3_eq_phase23_ffe_ctle_adj_en : 1; /* [21] */ + u32 gen4_eq_phase23_ffe_ctle_adj_en : 1; /* [22] */ + u32 rsv_43 : 1; /* [23] */ + u32 reg_16g_hilink_mode_en : 6; /* [29:24] */ + u32 reg_16g_ds_use_rx_preset_en : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_adj_hilink_mode_en_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lp_gen3_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_loopback_preset_timeout_val_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_loopback_preset_timeout_val : 11; /* [10:0] */ + u32 rsv_45 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_loopback_preset_timeout_val_addr_u; + +/* Define the union csr_mac_reg_comp_option_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_option_en : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_comp_option_u; + +/* Define the union csr_mac_reg_phy_rxdata_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_phy_rxdata_ts_u; + +/* Define the union csr_mac_reg_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eco_rsv0_u; + +/* Define the union csr_mac_reg_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pm_irs_empty_mask : 1; /* [0] */ + u32 reg_mac_enter_l2_clk_rxdata_en_mask : 1; /* [1] */ + u32 mac_eco_rsv1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eco_rsv1_u; + +/* Define the union csr_mac_regeq_trace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_search_tracer_recap : 1; /* [0] */ + u32 coeff_search_tracer_cap_mode : 1; /* [1] */ + u32 coeff_search_tracer_mode : 2; /* [3:2] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 coeff_search_tracer_raddr : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 coeff_search_tracer_last_waddr : 6; /* [21:16] */ + u32 coeff_search_tracer_addr_rollback : 1; /* [22] */ + u32 rsv_49 : 1; /* [23] */ + u32 coeff_search_tracer_lane_num : 4; /* [27:24] */ + u32 rsv_50 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_regeq_trace_u; + +/* Define the union csr_mac_reg_eq_timeout_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_coeff_search_22ms_timeout : 8; /* [7:0] */ + u32 cfg_coeff_req_timeout_val : 11; /* [18:8] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_timeout_set_u; + +/* Define the union csr_mac_reg_eq_init_coeff_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_init_coeff : 18; /* [17:0] */ + u32 rsv_52 : 6; /* [23:18] */ + u32 preset_coeff_maping_table_index : 4; /* [27:24] */ + u32 preset_coeff_table_mode_sel : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_eq_init_coeff_cfg_u; + +/* Define the union csr_mac_reg_wait_link_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wait_link_num_timer_dp : 11; /* [10:0] */ + u32 rsv_53 : 5; /* [15:11] */ + u32 wait_ts1_num : 6; /* [21:16] */ + u32 rsv_54 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_wait_link_num_timer_u; + +/* Define the union csr_mac_reg_lane_coeff_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_1_lane_cm1 : 6; /* [5:0] */ + u32 rsv_55 : 2; /* [7:6] */ + u32 reg_1_lane_c0 : 6; /* [13:8] */ + u32 rsv_56 : 2; /* [15:14] */ + u32 reg_1_lane_c1 : 6; /* [21:16] */ + u32 rsv_57 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lane_coeff_1_u; + +/* Define the union csr_mac_reg_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset0_cm1 : 6; /* [5:0] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 reg_preset0_c0 : 6; /* [13:8] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 reg_preset0_c1 : 6; /* [21:16] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset0_u; + +/* Define the union csr_mac_reg_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset1_cm1 : 6; /* [5:0] */ + u32 rsv_61 : 2; /* [7:6] */ + u32 reg_preset1_c0 : 6; /* [13:8] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 reg_preset1_c1 : 6; /* [21:16] */ + u32 rsv_63 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset1_u; + +/* Define the union csr_mac_reg_preset2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset2_cm1 : 6; /* [5:0] */ + u32 rsv_64 : 2; /* [7:6] */ + u32 reg_preset2_c0 : 6; /* [13:8] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 reg_preset2_c1 : 6; /* [21:16] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset2_u; + +/* Define the union csr_mac_reg_preset3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset3_cm1 : 6; /* [5:0] */ + u32 rsv_67 : 2; /* [7:6] */ + u32 reg_preset3_c0 : 6; /* [13:8] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 reg_preset3_c1 : 6; /* [21:16] */ + u32 rsv_69 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset3_u; + +/* Define the union csr_mac_reg_preset4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset4_cm1 : 6; /* [5:0] */ + u32 rsv_70 : 2; /* [7:6] */ + u32 reg_preset4_c0 : 6; /* [13:8] */ + u32 rsv_71 : 2; /* [15:14] */ + u32 reg_preset4_c1 : 6; /* [21:16] */ + u32 rsv_72 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset4_u; + +/* Define the union csr_mac_reg_preset5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset5_cm1 : 6; /* [5:0] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 reg_preset5_c0 : 6; /* [13:8] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 reg_preset5_c1 : 6; /* [21:16] */ + u32 rsv_75 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset5_u; + +/* Define the union csr_mac_reg_preset6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset6_cm1 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 reg_preset6_c0 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 reg_preset6_c1 : 6; /* [21:16] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset6_u; + +/* Define the union csr_mac_reg_preset7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset7_cm1 : 6; /* [5:0] */ + u32 rsv_79 : 2; /* [7:6] */ + u32 reg_preset7_c0 : 6; /* [13:8] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 reg_preset7_c1 : 6; /* [21:16] */ + u32 rsv_81 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset7_u; + +/* Define the union csr_mac_reg_preset8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset8_cm1 : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 reg_preset8_c0 : 6; /* [13:8] */ + u32 rsv_83 : 2; /* [15:14] */ + u32 reg_preset8_c1 : 6; /* [21:16] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset8_u; + +/* Define the union csr_mac_reg_preset9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset9_cm1 : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 reg_preset9_c0 : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 reg_preset9_c1 : 6; /* [21:16] */ + u32 rsv_87 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset9_u; + +/* Define the union csr_mac_reg_preset10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset10_cm1 : 6; /* [5:0] */ + u32 rsv_88 : 2; /* [7:6] */ + u32 reg_preset10_c0 : 6; /* [13:8] */ + u32 rsv_89 : 2; /* [15:14] */ + u32 reg_preset10_c1 : 6; /* [21:16] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset10_u; + +/* Define the union csr_mac_reg_preset11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset11_cm1 : 6; /* [5:0] */ + u32 rsv_91 : 2; /* [7:6] */ + u32 reg_preset11_c0 : 6; /* [13:8] */ + u32 rsv_92 : 2; /* [15:14] */ + u32 reg_preset11_c1 : 6; /* [21:16] */ + u32 rsv_93 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset11_u; + +/* Define the union csr_mac_reg_preset12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset12_cm1 : 6; /* [5:0] */ + u32 rsv_94 : 2; /* [7:6] */ + u32 reg_preset12_c0 : 6; /* [13:8] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 reg_preset12_c1 : 6; /* [21:16] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset12_u; + +/* Define the union csr_mac_reg_preset13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset13_cm1 : 6; /* [5:0] */ + u32 rsv_97 : 2; /* [7:6] */ + u32 reg_preset13_c0 : 6; /* [13:8] */ + u32 rsv_98 : 2; /* [15:14] */ + u32 reg_preset13_c1 : 6; /* [21:16] */ + u32 rsv_99 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset13_u; + +/* Define the union csr_mac_reg_preset14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset14_cm1 : 6; /* [5:0] */ + u32 rsv_100 : 2; /* [7:6] */ + u32 reg_preset14_c0 : 6; /* [13:8] */ + u32 rsv_101 : 2; /* [15:14] */ + u32 reg_preset14_c1 : 6; /* [21:16] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset14_u; + +/* Define the union csr_mac_reg_preset15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_preset15_cm1 : 6; /* [5:0] */ + u32 rsv_103 : 2; /* [7:6] */ + u32 reg_preset15_c0 : 6; /* [13:8] */ + u32 rsv_104 : 2; /* [15:14] */ + u32 reg_preset15_c1 : 6; /* [21:16] */ + u32 rsv_105 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_preset15_u; + +/* Define the union csr_mac_reg_debug_pipe5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_txeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe5_u; + +/* Define the union csr_mac_reg_debug_pipe6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rxpolarity : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe6_u; + +/* Define the union csr_mac_reg_debug_pipe7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_powerdown_1 : 24; /* [23:0] */ + u32 mac_ltssm_st : 6; /* [29:24] */ + u32 rsv_108 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe7_u; + +/* Define the union csr_mac_reg_debug_pipe8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_txdetrx : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_109 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe8_u; + +/* Define the union csr_mac_reg_debug_pipe9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxeleidle : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe9_u; + +/* Define the union csr_mac_reg_debug_pipe10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxdata_valid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_111 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe10_u; + +/* Define the union csr_mac_reg_debug_pipe11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_rxvalid : 16; /* [15:0] */ + u32 mac_ltssm_st : 6; /* [21:16] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_pipe11_u; + +/* Define the union csr_mac_reg_debug_rxdli_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rx_seq : 24; /* [23:0] */ + u32 rsv_113 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_rxdli_2_u; + +/* Define the union csr_mac_reg_debug_link_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_link_num_2_u; + +/* Define the union csr_mac_reg_debug_link_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_link_num_3_u; + +/* Define the union csr_mac_reg_debug_link_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_link_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_link_num_4_u; + +/* Define the union csr_mac_reg_debug_lane_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_lane_num_2_u; + +/* Define the union csr_mac_reg_debug_lane_num_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_lane_num_3_u; + +/* Define the union csr_mac_reg_debug_lane_num_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_tx_lane_num_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_debug_lane_num_4_u; + +/* Define the union csr_mac_reg_lp_gen3_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen3_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lp_gen3_tx_preset_p1_2_u; + +/* Define the union csr_mac_reg_gen3_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen3_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen3_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lane_coeff_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_2_lane_cm1 : 6; /* [5:0] */ + u32 rsv_114 : 2; /* [7:6] */ + u32 reg_2_lane_c0 : 6; /* [13:8] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 reg_2_lane_c1 : 6; /* [21:16] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lane_coeff_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 train_bit_map : 16; /* [15:0] */ + u32 txdetrx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_output_2_u; + +/* Define the union csr_mac_reg_ltssm_tracer_output_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_data_ok : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_output_ok_u; + +/* Define the union csr_mac_reg_ltssm_tracer_sram_ecc_insert_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_tracer_sram_ecc_insert : 2; /* [1:0] */ + u32 ltssm_tracer_sram_ecc_insert_mode : 1; /* [2] */ + u32 rsv_118 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_sram_ecc_insert_u; + +/* Define the union csr_mac_reg_ltssm_tracer_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_addr : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 ecc_2bit_err_addr : 6; /* [13:8] */ + u32 rsv_120 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_tracer_ecc_err_addr_u; + +/* Define the union csr_mac_reg_coeff_search_tracer_output_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 total_search_num : 6; /* [5:0] */ + u32 fsm_curr_search_state : 3; /* [8:6] */ + u32 rsv_121 : 3; /* [11:9] */ + u32 fig_merit_feedback : 8; /* [19:12] */ + u32 req_cur_coeff : 6; /* [25:20] */ + u32 req_pre_cur_coeff : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_coeff_search_tracer_output_u; + +/* Define the union csr_mac_reg_remote_fs_lf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_lf : 6; /* [5:0] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 remote_fs : 6; /* [13:8] */ + u32 rsv_123 : 2; /* [15:14] */ + u32 local_lf : 6; /* [21:16] */ + u32 rsv_124 : 2; /* [23:22] */ + u32 local_fs : 6; /* [29:24] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_remote_fs_lf_u; + +/* Define the union csr_mac_loop_link_data_err_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loop_back_link_data_err_cnt : 16; /* [15:0] */ + u32 rsv_126 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_loop_link_data_err_count_u; + +/* Define the union csr_mac_pcs_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_rx_err_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pcs_rx_err_cnt_u; + +/* Define the union csr_mac_up_max_auto_redo_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_eq_problem_cant_redo : 1; /* [0] */ + u32 req_set_hw_req_eq_af_count_full : 1; /* [1] */ + u32 permit_up_redo_eq : 1; /* [2] */ + u32 req_dp_redo_eq_gnt_mask : 1; /* [3] */ + u32 req_look_eq_gnt_en : 1; /* [4] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 req_rx_req_eq_ts_count : 6; /* [13:8] */ + u32 rsv_129 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_up_max_auto_redo_num_u; + +/* Define the union csr_mac_wait_lane_num_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wait_lane_num_timer_dp : 11; /* [10:0] */ + u32 rsv_130 : 5; /* [15:11] */ + u32 cfg_wait_lane_ts1_num : 6; /* [21:16] */ + u32 rsv_131 : 2; /* [23:22] */ + u32 cfg_lnacc_wait_lane_ts1_num : 6; /* [29:24] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_wait_lane_num_timer_u; + +/* Define the union csr_mac_lane_num_wait_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_wait_timer : 11; /* [10:0] */ + u32 rsv_133 : 5; /* [15:11] */ + u32 wait_link_num_timer_up : 11; /* [26:16] */ + u32 rsv_134 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lane_num_wait_timer_u; + +/* Define the union csr_mac_lane_num_acc_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_num_acc_timer : 11; /* [10:0] */ + u32 rsv_135 : 5; /* [15:11] */ + u32 cfg_wait_lane_num_timer_up : 11; /* [26:16] */ + u32 rsv_136 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lane_num_acc_timer_u; + +/* Define the union csr_mac_lnw_to_lna_1ms_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lnw_to_lna_1ms_timer : 11; /* [10:0] */ + u32 rsv_137 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lnw_to_lna_1ms_timer_u; + +/* Define the union csr_mac_eq_ltsmm_hold_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_phase23_hold_timer : 8; /* [7:0] */ + u32 cfg_rcv_lock_hold_timer : 7; /* [14:8] */ + u32 rsv_138 : 1; /* [15] */ + u32 cfg_phase0_hold_timer : 6; /* [21:16] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_eq_ltsmm_hold_timer_u; + +/* Define the union csr_mac_ltssm_crtl_infer_elecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_elecidle_infer_interval_timout_mask : 1; /* [0] */ + u32 set_rx_elecidle_infer : 1; /* [1] */ + u32 reg_use_any_lane_infer_eleidle : 1; /* [2] */ + u32 reg_mask_datapath_rxelecidle : 1; /* [3] */ + u32 reg_lane_num_mask : 1; /* [4] */ + u32 reg_rcvlock2cfg_ts_cfg : 1; /* [5] */ + u32 rsv_140 : 2; /* [7:6] */ + u32 reg_stand_by_disable : 4; /* [11:8] */ + u32 rsv_141 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ltssm_crtl_infer_elecidle_u; + +/* Define the union csr_mac_ltssm_tracer_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_signal_mask : 6; /* [5:0] */ + u32 rsv_142 : 2; /* [7:6] */ + u32 ltssm_trace_timer_clk_sel : 2; /* [9:8] */ + u32 ltssm_trace_clear_err_count_en : 6; /* [15:10] */ + u32 ltssm_trace_lane_num : 4; /* [19:16] */ + u32 cfg_sel_trace_record_frequency : 4; /* [23:20] */ + u32 sel_trace_rx_data_mode : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ltssm_tracer_cfg0_u; + +/* Define the union csr_mac_ltssm_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_143 : 5; /* [15:11] */ + u32 ltssm_trace_state : 6; /* [21:16] */ + u32 rsv_144 : 1; /* [22] */ + u32 clr_ltssm_trace_timer : 1; /* [23] */ + u32 ltssm_trace_speed : 4; /* [27:24] */ + u32 rsv_145 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ltssm_tracer_cfg1_u; + +/* Define the union csr_mac_cmp_loop_sent_eqts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_tx_sent_eq_ts1 : 1; /* [0] */ + u32 reg_mac_reject_eq_ts2_en : 1; /* [1] */ + u32 rsv_146 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cmp_loop_sent_eqts1_u; + +/* Define the union csr_mac_enter_lpbk_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 disable_enter_loopback : 3; /* [2:0] */ + u32 disable_enter_disable : 3; /* [5:3] */ + u32 disable_enter_hotreset : 1; /* [6] */ + u32 auto_speed_disable_mask : 1; /* [7] */ + u32 first_auto_speed_change_en : 1; /* [8] */ + u32 auto_speed_change_en : 1; /* [9] */ + u32 disable_enter_compliance : 1; /* [10] */ + u32 rsv_147 : 1; /* [11] */ + u32 reg_disable_ctrl_skp : 1; /* [12] */ + u32 reg_new_gen4_eieos_en : 1; /* [13] */ + u32 disable_scramber_disable : 1; /* [14] */ + u32 reg_new_esm_20g_25g_eieos_en : 1; /* [15] */ + u32 reg_pipe_data_width_sel : 8; /* [23:16] */ + u32 reg_core_clk_frequency : 4; /* [27:24] */ + u32 reg_txdata_valid_mode : 1; /* [28] */ + u32 reg_new_gen5_eieos_en : 1; /* [29] */ + u32 reg_modify_ts_disable : 1; /* [30] */ + u32 reg_req_bypass_disable_assert : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_enter_lpbk_disable_u; + +/* Define the union csr_mac_preset_table0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_preset_table0_u; + +/* Define the union csr_mac_preset_table1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_preset_table1 : 12; /* [11:0] */ + u32 rsv_148 : 4; /* [15:12] */ + u32 reg_preset_num : 4; /* [19:16] */ + u32 rsv_149 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_preset_table1_u; + +/* Define the union csr_mac_reg_ltssm_traceraddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_tracer_raddr : 6; /* [5:0] */ + u32 rsv_150 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_traceraddr_u; + +/* Define the union csr_mac_cfg_complete_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_clp_to_idle_timer : 11; /* [10:0] */ + u32 rsv_151 : 5; /* [15:11] */ + u32 cfg_clp_to_idle_tm_enable : 1; /* [16] */ + u32 rsv_152 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cfg_complete_timer_u; + +/* Define the union csr_mac_cfg_comp_errata_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_comp_errata_disable : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cfg_comp_errata_disable_u; + +/* Define the union csr_mac_rx_err_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_rx_err_check_en : 16; /* [15:0] */ + u32 rsv_154 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_rx_err_check_en_u; + +/* Define the union csr_mac_trace_2bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_er_cnt : 5; /* [4:0] */ + u32 rsv_155 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_trace_2bit_ecc_cnt_u; + +/* Define the union csr_mac_trace_1bit_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_er_cnt : 5; /* [4:0] */ + u32 rsv_156 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_trace_1bit_ecc_cnt_u; + +/* Define the union csr_mac_cfg_rcv_hold_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_en : 1; /* [0] */ + u32 reg_rcv_cfg_hold_en : 1; /* [1] */ + u32 reg_rcv_idle_hold_en : 1; /* [2] */ + u32 lw_str_wait_full_width_en : 1; /* [3] */ + u32 lw_acc_wait_full_width_en : 1; /* [4] */ + u32 ln_wait_wait_full_width_en : 1; /* [5] */ + u32 ln_acc_wait_full_width_en : 1; /* [6] */ + u32 rsv_157 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cfg_rcv_hold_en_u; + +/* Define the union csr_mac_cfg_rcv_lock_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_lock_hold_time : 16; /* [15:0] */ + u32 poling_act_hold_timer : 8; /* [23:16] */ + u32 poling_cfg_hold_timer : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cfg_rcv_lock_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_cfg_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_hold_time : 16; /* [15:0] */ + u32 reg_extended_ts_number : 12; /* [27:16] */ + u32 rsv_158 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cfg_rcv_cfg_hold_time_u; + +/* Define the union csr_mac_cfg_rcv_idle_hold_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_idle_hold_time : 16; /* [15:0] */ + u32 reg_detect_wait_time : 10; /* [25:16] */ + u32 rsv_159 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_cfg_rcv_idle_hold_time_u; + +/* Define the union csr_mac_ltssm_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_int_match_state : 6; /* [5:0] */ + u32 rsv_160 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ltssm_int_status_u; + +/* Define the union csr_mac_deskew_symbol_unlock_rcv_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_symbol_numlock_err_rcv_mask : 1; /* [0] */ + u32 reg_deskew_numlock_err_rcv_mask : 1; /* [1] */ + u32 reg_deskew_det_skp_unalign_en : 1; /* [2] */ + u32 reg_relock_deskew_in_rcv_en : 1; /* [3] */ + u32 rsv_161 : 1; /* [4] */ + u32 rsv_162 : 3; /* [7:5] */ + u32 reg_skp_not_detect_th : 6; /* [13:8] */ + u32 rsv_163 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_deskew_symbol_unlock_rcv_mask_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen4_eq_opt_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_opt_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen4_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen4_eq_opt_tx_preset_2_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lp_gen4_tx_preset_p1_1_u; + +/* Define the union csr_mac_reg_lp_gen4_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen4_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lp_gen4_tx_preset_p1_2_u; + +/* Define the union csr_mac_lpbk_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lpbk_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lpbk_data_u; + +/* Define the union csr_mac_rx_margin_self_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_dfe_disable_cfg_en : 1; /* [0] */ + u32 reg_dfe_cfg_value : 1; /* [1] */ + u32 margin_eco_reserved0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_rx_margin_self_ctrl_u; + +/* Define the union csr_mac_rx_margin_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved2 : 8; /* [7:0] */ + u32 reg_margin_vender_define_cmd_payload : 8; /* [15:8] */ + u32 margin_eco_reserved1 : 15; /* [30:16] */ + u32 reg_margin_global_disable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_rx_margin_cfg_u; + +/* Define the union csr_gen4_rx_margin_cpa0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_timing_steps : 6; /* [5:0] */ + u32 indleft_right_timing_support : 1; /* [6] */ + u32 voltage_support : 1; /* [7] */ + u32 max_timing_offset : 6; /* [13:8] */ + u32 ind_up_down_voltage_support : 1; /* [14] */ + u32 margin_eco_reserved4 : 1; /* [15] */ + u32 num_voltage_steps : 8; /* [23:16] */ + u32 max_voltage_offset : 7; /* [30:24] */ + u32 margin_eco_reserved3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_gen4_rx_margin_cpa0_u; + +/* Define the union csr_gen4_rx_margin_cpa1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_eco_reserved7 : 7; /* [6:0] */ + u32 max_lane_support : 5; /* [11:7] */ + u32 margin_eco_reserved6 : 4; /* [15:12] */ + u32 sample_rate_timing : 6; /* [21:16] */ + u32 ind_error_sample : 1; /* [22] */ + u32 sample_reporting_method : 1; /* [23] */ + u32 margin_eco_reserved5 : 2; /* [25:24] */ + u32 sample_rate_voltage : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_gen4_rx_margin_cpa1_u; + +/* Define the union csr_gen4_rx_margin_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_margin_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_gen4_rx_margin_rsv_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen3_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen3_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_8g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen3_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen4_eq_fix_tx_preset_1_u; + +/* Define the union csr_mac_reg_gen4_eq_fix_tx_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_fix_16g_tx_preset_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_gen4_eq_fix_tx_preset_2_u; + +/* Define the union csr_mac_reg_phase01_coarsetune_start_tm_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_phase01_coarsetune_start_tm : 11; /* [10:0] */ + u32 reg_coarsetune_start_use_rxidle_en : 1; /* [11] */ + u32 reg_coarsetune_start_use_rxvalid_en : 1; /* [12] */ + u32 reg_8g_ignore_ctle_done : 1; /* [13] */ + u32 reg_16g_ignore_ctle_done : 1; /* [14] */ + u32 reg_8g_phase01_timeout_skip_en : 1; /* [15] */ + u32 reg_16g_phase01_timeout_skip_en : 1; /* [16] */ + u32 reg_up_8g_phase1_hold_en : 1; /* [17] */ + u32 reg_up_16g_phase1_hold_en : 1; /* [18] */ + u32 rsv_164 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_phase01_coarsetune_start_tm_value_u; + +/* Define the union csr_mac_ltssm_timeout_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_timeout_en : 8; /* [7:0] */ + u32 rsv_165 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ltssm_timeout_enable_u; + +/* Define the union csr_mac_loopback_ec_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 loopback_ec_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_loopback_ec_value_u; + +/* Define the union csr_mac_lane_reverse_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lane_reverse_mux_value : 4; /* [3:0] */ + u32 reg_lane_reverse_mux_cfg_en : 1; /* [4] */ + u32 reg_compliance_mode : 1; /* [5] */ + u32 reg_unused_lane_turn_off_en : 1; /* [6] */ + u32 reg_poweroff_lane_in_detect : 1; /* [7] */ + u32 lane0_number : 4; /* [11:8] */ + u32 rsv_166 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lane_reverse_cfg_u; + +/* Define the union csr_mac_pipe_sris_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_sris_en : 16; /* [15:0] */ + u32 rsv_167 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pipe_sris_en_u; + +/* Define the union csr_mac_pipe_ebuf_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac2phy_ebuf_mode : 16; /* [15:0] */ + u32 rsv_168 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pipe_ebuf_mode_u; + +/* Define the union csr_mac_pipe_sris_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pipe_sris_en0_u; + +/* Define the union csr_mac_pipe_sris_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth47 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pipe_sris_en1_u; + +/* Define the union csr_mac_pipe_sris_en2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth811 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pipe_sris_en2_u; + +/* Define the union csr_mac_pipe_sris_en3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ebuff_depth1216 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_pipe_sris_en3_u; + +/* Define the union csr_mac_framing_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_count : 16; /* [15:0] */ + u32 rsv_169 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_framing_err_cnt_u; + +/* Define the union csr_mac_framing_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_framing_err_retrain_en : 1; /* [0] */ + u32 reg_framing_err_rpt_en : 1; /* [1] */ + u32 reg_pcs_decode_err_retrain_en : 1; /* [2] */ + u32 reg_reveive_err_rpt_en : 1; /* [3] */ + u32 rsv_170 : 4; /* [7:4] */ + u32 reg_framing_mask : 8; /* [15:8] */ + u32 skp_data_parity_mask : 4; /* [19:16] */ + u32 rsv_171 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_framing_err_ctrl_u; + +/* Define the union csr_mac_linkdown_req_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_linkdown_req_mask : 3; /* [2:0] */ + u32 rsv_172 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_linkdown_req_mask_u; + +/* Define the union csr_mac_int_type_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_int_type_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_int_type_sel_u; + +/* Define the union csr_mac_req_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fig_merit_feedback : 8; /* [7:0] */ + u32 req_cur_coeff : 6; /* [13:8] */ + u32 rsv_173 : 2; /* [15:14] */ + u32 req_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_174 : 2; /* [23:22] */ + u32 tx_preset : 4; /* [27:24] */ + u32 rsv_175 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_req_coeff_info_u; + +/* Define the union csr_mac_rx_coeff_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_post_cur_coeff : 6; /* [5:0] */ + u32 rx_use_preset : 1; /* [6] */ + u32 rx_reject : 1; /* [7] */ + u32 rx_cur_coeff : 6; /* [13:8] */ + u32 rx_ec : 2; /* [15:14] */ + u32 rx_pre_cur_coeff : 6; /* [21:16] */ + u32 rsv_176 : 2; /* [23:22] */ + u32 rx_xmt_preset : 4; /* [27:24] */ + u32 rsv_177 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_rx_coeff_info_u; + +/* Define the union csr_mac_leave_l0_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_retrain_redo_req : 1; /* [0] */ + u32 dp_redp_eq_enter_rcv : 1; /* [1] */ + u32 cfg_link_disable : 1; /* [2] */ + u32 enter_loop_back : 1; /* [3] */ + u32 framing_err_retrain : 1; /* [4] */ + u32 dl_retran : 1; /* [5] */ + u32 skp_infter_idle_timeout : 1; /* [6] */ + u32 hot_reset : 1; /* [7] */ + u32 cfg_retrain_req : 1; /* [8] */ + u32 reg_retrain_req : 1; /* [9] */ + u32 det_eieos_128b130b : 1; /* [10] */ + u32 det_ts_train : 1; /* [11] */ + u32 direct_speed_change : 1; /* [12] */ + u32 tl_ap_req_link_down : 1; /* [13] */ + u32 dl_req_link_down : 1; /* [14] */ + u32 enter_l2_req : 1; /* [15] */ + u32 enter_l1_req : 1; /* [16] */ + u32 enter_l0s_req : 1; /* [17] */ + u32 enter_l1l2_timeout : 1; /* [18] */ + u32 rcv_eios : 1; /* [19] */ + u32 rsv_178 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_leave_l0_info_u; + +/* Define the union csr_mac_gen4_low_skp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen4 : 9; /* [8:0] */ + u32 rsv_179 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen4 : 9; /* [24:16] */ + u32 rsv_180 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_gen4_low_skp_cfg_u; + +/* Define the union csr_dfx_apb_lane_error_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 symbol_unlock_err_status : 16; /* [15:0] */ + u32 pcs_rcv_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_dfx_apb_lane_error_status_0_u; + +/* Define the union csr_dfx_apb_lane_error_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 phy_lane_err_status : 16; /* [15:0] */ + u32 loopback_link_data_err_status : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_dfx_apb_lane_error_status_1_u; + +/* Define the union csr_reg_fix_lp_8g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_8g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_181 : 13; /* [30:18] */ + u32 reg_8g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_reg_fix_lp_8g_tx_coeff_u; + +/* Define the union csr_reg_fix_lp_16g_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_182 : 13; /* [30:18] */ + u32 reg_16g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_reg_fix_lp_16g_tx_coeff_u; + +/* Define the union csr_reg_rxidle_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxeleidle_delay_time : 8; /* [7:0] */ + u32 reg_rxeleidle_2pm_debounce_en : 1; /* [8] */ + u32 reg_rxeleidle_2pm_mode_sel : 1; /* [9] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_reg_rxidle_delay_time_u; + +/* Define the union csr_mac_reg_16g_phy_eq_fb_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_16g_phy_eq_fb_sel : 2; /* [1:0] */ + u32 reg_16g_coeff_search_len : 4; /* [5:2] */ + u32 cfg_16g_polling_preset_mode : 1; /* [6] */ + u32 cfg_16g_polling_preset_use_program_table : 1; /* [7] */ + u32 cfg_16g_merit_step : 6; /* [13:8] */ + u32 cfg_16g_reset_eieos : 1; /* [14] */ + u32 reg_up_8g_eqts2_sent_en : 1; /* [15] */ + u32 reg_16g_mac_rxeqeval_eye_type : 2; /* [17:16] */ + u32 reg_16g_coeff_pre_resolution : 2; /* [19:18] */ + u32 reg_16g_coeff_post_resolution : 2; /* [21:20] */ + u32 reg_up_tx_16g_eqts2_en : 1; /* [22] */ + u32 rsv_184 : 1; /* [23] */ + u32 reg_16g_ntimes_start_check : 3; /* [26:24] */ + u32 rsv_185 : 1; /* [27] */ + u32 reg_up_tx_gen1_eqts2_en : 1; /* [28] */ + u32 rsv_186 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_16g_phy_eq_fb_sel_u; + +/* Define the union csr_mac_reg_tx_margin_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_tx_margin_mask_value : 3; /* [2:0] */ + u32 rsv_187 : 1; /* [3] */ + u32 reg_tx_margin_mask : 1; /* [4] */ + u32 rsv_188 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_tx_margin_ctrl_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_8gt_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_8gt_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_up_8gt_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_8gt_eqts2_preset_1_u; + +/* Define the union csr_reg_rxvalid_delay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxvalid_delay_time : 8; /* [7:0] */ + u32 rsv_189 : 8; /* [15:8] */ + u32 reg_detect_wait_time_1 : 10; /* [25:16] */ + u32 rsv_190 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_reg_rxvalid_delay_time_u; + +/* Define the union csr_mac_int_ce_nfe_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_int_ce_nfe_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_int_ce_nfe_sel_u; + +/* Define the union csr_mac_reg_ni_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ni_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ni_int_ro_u; + +/* Define the union csr_mac_reg_fe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_fe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fe_int_ro_u; + +/* Define the union csr_mac_reg_ce_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ce_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ce_int_ro_u; + +/* Define the union csr_mac_reg_nfe_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_nfe_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_nfe_int_ro_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_tx_16g_eqts2_preset_0_u; + +/* Define the union csr_mac_reg_up_tx_16g_eqts2_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_16g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_tx_16g_eqts2_preset_1_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_tx_esm_20g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_20g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_20g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_tx_esm_20g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_tx_esm_25g_eqts2_preset0_u; + +/* Define the union csr_mac_reg_up_tx_esm_25g_eqts2_preset1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_up_tx_esm_25g_eqts2_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_up_tx_esm_25g_eqts2_preset1_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_esm_20g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_20g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_20g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_esm_20g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_esm_25g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_esm_25g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_esm_25g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_esm_25g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_32g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_32g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_32g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_32g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_56g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_56g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_56g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_56g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_64g_tx_preset_value0_u; + +/* Define the union csr_mac_reg_fix_64g_tx_preset_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_reg_fix_64g_tx_preset_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_fix_64g_tx_preset_value1_u; + +/* Define the union csr_mac_reg_skp_intvl_gen5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_skp_intvl_sris_gen5 : 9; /* [8:0] */ + u32 rsv_191 : 7; /* [15:9] */ + u32 reg_skp_intvl_srns_gen5 : 9; /* [24:16] */ + u32 rsv_192 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_skp_intvl_gen5_u; + +/* Define the union csr_mac_reg_skp_intvl_gen6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_193 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_skp_intvl_gen6_u; + +/* Define the union csr_mac_reg_skp_intvl_gen7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_194 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_skp_intvl_gen7_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_195 : 13; /* [30:18] */ + u32 reg_esm_20g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_20g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_196 : 13; /* [30:18] */ + u32 reg_esm_25g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_25g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_32g_eqfix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_eq_fix_lp_tx_coeff : 18; /* [17:0] */ + u32 rsv_197 : 13; /* [30:18] */ + u32 reg_32g_eq_fix_lp_tx_use_preset : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_32g_eqfix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_56g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_56g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_64g_eq_fix_lp_tx_coeff_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_coeff : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_64g_eq_fix_lp_tx_coeff_u; + +/* Define the union csr_mac_reg_esm_20g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_198 : 2; /* [7:6] */ + u32 esm_20g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_20g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_20g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_20g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_20g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_20g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_20g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_20g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_20g_reset_eieos : 1; /* [17] */ + u32 reg_esm_20g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_20g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_20g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_20g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_20g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_20g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_20g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_20g_eq_req : 1; /* [30] */ + u32 rsv_199 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_20g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_25g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_200 : 2; /* [7:6] */ + u32 esm_25g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 esm_25g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 esm_25g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 esm_25g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_esm_25g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_esm_25g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_esm_25g_polling_preset_mode : 1; /* [15] */ + u32 cfg_esm_25g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_esm_25g_reset_eieos : 1; /* [17] */ + u32 reg_esm_25g_ignore_ctle_done : 1; /* [18] */ + u32 reg_esm_25g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_esm_25g_phase1_hold_en : 1; /* [20] */ + u32 reg_esm_25g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_esm_25g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_esm_25g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_esm_25g_ntimes_start_check : 3; /* [29:27] */ + u32 mac_hw_link_esm_25g_eq_req : 1; /* [30] */ + u32 rsv_201 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_25g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_32g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_32g_hilink_mode_en : 6; /* [5:0] */ + u32 rsv_202 : 2; /* [7:6] */ + u32 reg_32g_eq_rcv_lock_af_phase13_ctle_apt_en : 1; /* [8] */ + u32 reg_32g_eq_phase23_ctle_apt_en : 1; /* [9] */ + u32 reg_32g_eq_hpase01_ctle_apt_en : 1; /* [10] */ + u32 reg_32g_eq_phase23_ffe_ctle_adj_en : 1; /* [11] */ + u32 reg_32g_ds_use_rx_preset_en : 1; /* [12] */ + u32 reg_32g_phy_eq_fb_sel : 2; /* [14:13] */ + u32 cfg_32g_polling_preset_mode : 1; /* [15] */ + u32 cfg_32g_polling_preset_use_program_table : 1; /* [16] */ + u32 cfg_32g_reset_eieos : 1; /* [17] */ + u32 reg_32g_ignore_ctle_done : 1; /* [18] */ + u32 reg_32g_phase01_timeout_skip_en : 1; /* [19] */ + u32 reg_up_32g_phase1_hold_en : 1; /* [20] */ + u32 reg_32g_mac_rxeqeval_eye_type : 2; /* [22:21] */ + u32 reg_32g_coeff_pre_resolution : 2; /* [24:23] */ + u32 reg_32g_coeff_post_resolution : 2; /* [26:25] */ + u32 reg_32g_ntimes_start_check : 3; /* [29:27] */ + u32 rsv_203 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_32g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_56g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_204 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_56g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_64g_link_eq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_205 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_64g_link_eq_ctrl_u; + +/* Define the union csr_mac_reg_esm_20g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_20g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_20g_tx_preset : 4; /* [7:4] */ + u32 rsv_206 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_20g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_25g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_25_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_25g_tx_preset : 4; /* [7:4] */ + u32 rsv_207 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_25g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_32g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_esm_32g_eq_fix_lp_tx_preset : 4; /* [3:0] */ + u32 reg_comp_lpbk_remote_esm_32g_tx_preset : 4; /* [7:4] */ + u32 rsv_208 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_32g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_56g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_56g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_56g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_reg_esm_64g_eq_fix_lp_tx_preset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_64g_eq_fix_lp_tx_preset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_esm_64g_eq_fix_lp_tx_preset_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lp_esm_20g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_20g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_20g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lp_esm_20g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lp_esm_25g_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_esm_25g_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_esm_25g_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lp_esm_25g_tx_preset_p1_2_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lp_gen5_tx_preset_p1_1_u; + +/* Define the union csr_mac_lp_gen5_tx_preset_p1_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_gen5_tx_preset_p1_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lp_gen5_tx_preset_p1_2_u; + +/* Define the union csr_mac_opt_esm_20g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_opt_esm_20g_preset_1_u; + +/* Define the union csr_mac_opt_esm_20g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_20g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_opt_esm_20g_preset_2_u; + +/* Define the union csr_mac_opt_esm_25g_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_opt_esm_25g_preset_1_u; + +/* Define the union csr_mac_opt_esm_25g_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_esm_25g_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_opt_esm_25g_preset_2_u; + +/* Define the union csr_mac_opt_gen5_preset_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_opt_gen5_preset_1_u; + +/* Define the union csr_mac_opt_gen5_preset_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_gen5_preset_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_opt_gen5_preset_2_u; + +/* Define the union csr_mac_reg_ltssm_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ltssm_variable_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_dfx_u; + +/* Define the union csr_mac_reg_alternate_protol_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_alternate_protol_vender_id : 16; /* [15:0] */ + u32 rsv_209 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_alternate_protol_vender_id_u; + +/* Define the union csr_mac_reg_ts_message_vender_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_ts_message_vender_id : 16; /* [15:0] */ + u32 rsv_210 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ts_message_vender_id_u; + +/* Define the union csr_mac_hilink_info_dfx_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 hilink_dir_search_info_7_0 : 8; /* [15:8] */ + u32 hilink_dir_search_info_13_8 : 6; /* [21:16] */ + u32 rsv_211 : 2; /* [23:22] */ + u32 hilink_dir_search_info_19_14 : 6; /* [29:24] */ + u32 rsv_212 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_hilink_info_dfx_1_u; + +/* Define the union csr_mac_hilink_info_dfx_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_ltssm_st : 6; /* [5:0] */ + u32 rsv_213 : 2; /* [7:6] */ + u32 mac_cur_link_speed : 4; /* [11:8] */ + u32 rsv_214 : 4; /* [15:12] */ + u32 hilink_dir_search_info_7_0 : 8; /* [23:16] */ + u32 hilink_dir_search_state_8_5 : 4; /* [27:24] */ + u32 rsv_215 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_hilink_info_dfx_2_u; + +/* Define the union csr_mac_hilink_info_dfx_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hilink_dir_search_state_3_0 : 4; /* [3:0] */ + u32 mac_cur_link_speed : 4; /* [7:4] */ + u32 preset_search_info_7_0 : 8; /* [15:8] */ + u32 preset_search_info_15_8 : 8; /* [23:16] */ + u32 preset_search_info_19_16 : 4; /* [27:24] */ + u32 rsv_216 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_hilink_info_dfx_3_u; + +/* Define the union csr_mac_reg_pll_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_powerdown_pll0_en : 5; /* [4:0] */ + u32 reg_powerdown_pll1_en : 2; /* [6:5] */ + u32 rsv_217 : 1; /* [7] */ + u32 reg_pll1_status_ctrl : 2; /* [9:8] */ + u32 reg_pll0_status_ctrl : 2; /* [11:10] */ + u32 reg_set_mac_pll_calib_rate_sel : 1; /* [12] */ + u32 reg_clr_mac_pll_calib_rate_sel : 1; /* [13] */ + u32 phy_pll_calib_status : 1; /* [14] */ + u32 mac_pll_calib_rate_sel : 1; /* [15] */ + u32 reg_dete_scramble_disable_poling : 1; /* [16] */ + u32 phy_pll_pwrsq_down_status : 1; /* [17] */ + u32 hilink_pll_status : 4; /* [21:18] */ + u32 rsv_218 : 1; /* [22] */ + u32 reg_advertise_higest_rate_en : 1; /* [23] */ + u32 reg_low_power_change_speed_en : 1; /* [24] */ + u32 reg_phy_pll_pwrsq_down_mask : 1; /* [25] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_pll_ctrl_u; + +/* Define the union csr_mac_reg_use_fix_core_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_use_fix_core_clk_en : 1; /* [0] */ + u32 rsv_220 : 7; /* [7:1] */ + u32 reg_core_clk_frequency_low_power : 8; /* [15:8] */ + u32 rsv_221 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_use_fix_core_clk_en_u; + +/* Define the union csr_mac_ebuffer_update_frequency0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ebuffer_update_frequency0_u; + +/* Define the union csr_mac_ebuffer_update_frequency1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ebuffer_update_frequency1_u; + +/* Define the union csr_mac_ebuffer_update_frequency2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ebuffer_update_frequency2_u; + +/* Define the union csr_mac_ebuffer_update_frequency3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuffer_update_frequency3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_ebuffer_update_frequency3_u; + +/* Define the union csr_mac_reg_pipe_mode_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_pipe_mode_txmargin_sel : 1; /* [0] */ + u32 reg_pipe_mode_locfsloclf_sel : 1; /* [1] */ + u32 reg_pipe_mode_rxeqeval_sel : 1; /* [2] */ + u32 reg_pipe_mode_txdeemp_sel : 1; /* [3] */ + u32 reg_pipe_mode_rxpolarity_sel : 1; /* [4] */ + u32 reg_pipe_mode_ebuffer_mode_sel : 1; /* [5] */ + u32 reg_pipe_mode_rxblockalign_sel : 1; /* [6] */ + u32 reg_pipe_mode_lt_fbtypsel_sel : 1; /* [7] */ + u32 rsv_222 : 8; /* [15:8] */ + u32 reg_lt_remote_reject_update_mask : 1; /* [16] */ + u32 reg_lt_remote_coeff_init_update_mask : 1; /* [17] */ + u32 rsv_223 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_pipe_mode_sel_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx_lane_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rpt_mbus_dfx_lane_id : 4; /* [3:0] */ + u32 rsv_224 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_rpt_mbus_dfx_lane_id_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_rpt_mbus_dfx0_u; + +/* Define the union csr_mac_reg_rpt_mbus_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_dfx_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_rpt_mbus_dfx1_u; + +/* Define the union csr_mac_reg_rpt_mbus_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rpt_mbus_err_counter : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_rpt_mbus_err_cnt_u; + +/* Define the union csr_mac_reg_lcfslf_use_txstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_lcfslf_use_txstatus : 1; /* [0] */ + u32 rsv_225 : 7; /* [7:1] */ + u32 reg_gen3_eq_feedback_done_addr : 2; /* [9:8] */ + u32 reg_gen4_eq_feedback_done_addr : 2; /* [11:10] */ + u32 reg_gen5_eq_feedback_done_addr : 2; /* [13:12] */ + u32 reg_20g_eq_feedback_done_addr : 2; /* [15:14] */ + u32 reg_25g_eq_feedback_done_addr : 2; /* [17:16] */ + u32 rsv_226 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_lcfslf_use_txstatus_u; + +/* Define the union csr_mac_precoding_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_precoding_req : 16; /* [15:0] */ + u32 mac_rx_precoding_enable : 1; /* [16] */ + u32 mac_tx_precoding_enable : 1; /* [17] */ + u32 bypass_g3g4_eq_en : 1; /* [18] */ + u32 rsv_227 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_precoding_ctrl_u; + +/* Define the union csr_mac_rx_termation_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rxtermation_en : 1; /* [0] */ + u32 reg_clr_rxtermination_linkdown_en : 1; /* [1] */ + u32 rsv_228 : 14; /* [15:2] */ + u32 reg_rxtermation : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_rx_termation_u; + +/* Define the union csr_mac_powerdown_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_powerdown_value_p0 : 4; /* [3:0] */ + u32 reg_mac_powerdown_value_p0s : 4; /* [7:4] */ + u32 reg_mac_powerdown_value_p1 : 4; /* [11:8] */ + u32 reg_mac_powerdown_value_p11 : 4; /* [15:12] */ + u32 reg_mac_powerdown_value_p12 : 4; /* [19:16] */ + u32 reg_mac_powerdown_value_p2 : 4; /* [23:20] */ + u32 reg_mac_powerdown_value_disable_p1 : 4; /* [27:24] */ + u32 reg_mac_powerdown_close_lane : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_powerdown_value_u; + +/* Define the union csr_mac_clk_sw_tm_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_wait_clk_switch_tm_val : 10; /* [9:0] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_clk_sw_tm_val_u; + +/* Define the union csr_mac_txeleidle_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_rcv_cfg_txidle_tm_val : 8; /* [7:0] */ + u32 rsv_230 : 16; /* [23:8] */ + u32 reg_rcv_cfg_txidle_en : 1; /* [24] */ + u32 rsv_231 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_txeleidle_tm_u; + +/* Define the union csr_mac_target_link_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_mac_target_link_width : 6; /* [5:0] */ + u32 rsv_232 : 2; /* [7:6] */ + u32 reg_upconfig_pad_pad_timeout_val : 11; /* [18:8] */ + u32 rsv_233 : 5; /* [23:19] */ + u32 reg_lp_upconfig_cap_mask : 1; /* [24] */ + u32 rsv_234 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_target_link_width_u; + +/* Define the union csr_mac_lpbk_wait_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_enter_lpbk_master_wait_time : 8; /* [7:0] */ + u32 rsv_235 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lpbk_wait_time_u; + +/* Define the union csr_mac_lpbk_dfx_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_tx_modify_comp_in_lpbk : 16; /* [15:0] */ + u32 gen5_loopback_lane_under_test : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_lpbk_dfx_info_u; + +/* Define the union csr_tx_dli_debug_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_dli_debug_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_tx_dli_debug_info_u; + +/* Define the union csr_mac_reg_deskew_unlocl_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deskew_unlock_counter : 16; /* [15:0] */ + u32 rsv_236 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_deskew_unlocl_counter_u; + +/* Define the union csr_mac_reg_rx_tsbuf_reset_counter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxts_buf_reset_counter : 16; /* [15:0] */ + u32 rsv_237 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_rx_tsbuf_reset_counter_u; + +/* Define the union csr_mac_reg_ltssm_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value0_u; + +/* Define the union csr_mac_reg_ltssm_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value1_u; + +/* Define the union csr_mac_reg_ltssm_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value2_u; + +/* Define the union csr_mac_reg_ltssm_value3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value3_u; + +/* Define the union csr_mac_reg_ltssm_value4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value4_u; + +/* Define the union csr_mac_reg_ltssm_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value5_u; + +/* Define the union csr_mac_reg_ltssm_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value6_u; + +/* Define the union csr_mac_reg_ltssm_value7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value7_u; + +/* Define the union csr_mac_reg_ltssm_value8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value8_u; + +/* Define the union csr_mac_reg_ltssm_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value9_u; + +/* Define the union csr_mac_reg_ltssm_value10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltssm_internal_value10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_reg_ltssm_value10_u; + +/* Define the union csr_mac_p10_coeff_half_rate_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_preset10_coeff_half_rate_value : 18; /* [17:0] */ + u32 rsv_238 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_p10_coeff_half_rate_u; + +/* Define the union csr_mac_rcv_eios_to_eleidle_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mac_rcv_eios_to_eleidle_value : 8; /* [7:0] */ + u32 rsv_239 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_rcv_eios_to_eleidle_dly_u; + +/* Define the union csr_gen5_phy_cap_reg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_240 : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_gen5_phy_cap_reg0_u; + +/* Define the union csr_gen5_phy_cap_reg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 rsv_241 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_gen5_phy_cap_reg1_u; + +/* Define the union csr_mac_coeff_tracer_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coeff_trace_trigger_timer : 11; /* [10:0] */ + u32 rsv_242 : 5; /* [15:11] */ + u32 coeff_trace_state : 6; /* [21:16] */ + u32 rsv_243 : 1; /* [22] */ + u32 clr_coeff_trace_timer : 1; /* [23] */ + u32 coeff_trace_speed : 4; /* [27:24] */ + u32 coeff_trace_clk_sel : 2; /* [29:28] */ + u32 rsv_244 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_mac_reg_7_mac_coeff_tracer_cfg1_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_0_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_1_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_2_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_3_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_4_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_5_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_6_eco_tl_u; + +/* Define the union csr_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_nond0_stop_en : 1; /* [0] */ + u32 tl_tx_protect_for_down : 1; /* [1] */ + u32 tl_tx_ccix_vc_sp_en : 1; /* [2] */ + u32 tl_tx_rr_sche_mask : 1; /* [3] */ + u32 rsv_0 : 1; /* [4] */ + u32 tl_tx_fcp_err_rpt_en : 1; /* [5] */ + u32 rsv_1 : 1; /* [6] */ + u32 rsv_2 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_ctrl_u; + +/* Define the union csr_tl_engien_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_3 : 1; /* [0] */ + u32 rsv_4 : 6; /* [6:1] */ + u32 rsv_5 : 1; /* [7] */ + u32 tl_sft_dl_down_en : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_engien_status_u; + +/* Define the union csr_tl_rx_check_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_4kb_check_en : 1; /* [0] */ + u32 tl_cdt_ovf_check_en : 1; /* [1] */ + u32 tl_rx_ecrc_np_cpl_ctrl : 1; /* [2] */ + u32 tl_rx_ecrc_report_adv_en : 1; /* [3] */ + u32 rsv_7 : 4; /* [7:4] */ + u32 tl_rcb_check_en : 1; /* [8] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 tl_cfgreq_check_en : 1; /* [16] */ + u32 tl_ioreq_check_en : 1; /* [17] */ + u32 rsv_9 : 5; /* [22:18] */ + u32 tl_rx_poison_cpl_advn_en : 1; /* [23] */ + u32 tl_rx_poison_forwarding_en : 1; /* [24] */ + u32 tl_rx_vdm0_forwarding_en : 1; /* [25] */ + u32 tl_rx_ats_trans_len_check_en : 1; /* [26] */ + u32 rsv_10 : 1; /* [27] */ + u32 tl_rx_vdm1_forwarding_en : 1; /* [28] */ + u32 rsv_11 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_check_en_u; + +/* Define the union csr_ltr_require_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_sloop_value : 10; /* [9:0] */ + u32 ltr_sloop_scale : 3; /* [12:10] */ + u32 rsv_12 : 2; /* [14:13] */ + u32 ltr_sloop_require : 1; /* [15] */ + u32 ltr_nosloop_value : 10; /* [25:16] */ + u32 ltr_nosloop_scale : 3; /* [28:26] */ + u32 rsv_13 : 2; /* [30:29] */ + u32 ltr_nosloop_require : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_ltr_require_u; + +/* Define the union csr_ltr_msg_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_transmit_req : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 ltr_transmit_finish : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_ltr_msg_ctrl_status_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_crd_without_link : 1; /* [0] */ + u32 tx_crd_active_cfg : 1; /* [1] */ + u32 tx_crd_active_sel : 1; /* [2] */ + u32 rsv_16 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tx_crd_ctrl_u; + +/* Define the union csr_pm_npd_cdt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_npd_cdt_sel : 1; /* [0] */ + u32 rsv_17 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_pm_npd_cdt_ctrl_u; + +/* Define the union csr_tl_tx_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_wrr_p_weight : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 tlreg_wrr_np_weight : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 tlreg_wrr_cpl_weight : 6; /* [21:16] */ + u32 rsv_20 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_wrr_weight_u; + +/* Define the union csr_tl_port_idle_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle_tout_en : 1; /* [0] */ + u32 rsv_21 : 1; /* [1] */ + u32 rsv_22 : 14; /* [15:2] */ + u32 ap_port_idle_st : 1; /* [16] */ + u32 tl_rx_port_idle_st : 1; /* [17] */ + u32 tl_tx_port_idle_st : 1; /* [18] */ + u32 pcie_port_idle_st : 1; /* [19] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_port_idle_ctrl_status_u; + +/* Define the union csr_tl_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_num : 8; /* [7:0] */ + u32 cfg_pf_num : 5; /* [12:8] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_cfg_access_ctrl_u; + +/* Define the union csr_tl_aspm_idle_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_l0s_enter_cnt : 16; /* [15:0] */ + u32 tl_aspm_l1_enter_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_aspm_idle_cnt_u; + +/* Define the union csr_tl_aspm_idle_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_idlecnt_en : 2; /* [1:0] */ + u32 rsv_25 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_aspm_idle_en_u; + +/* Define the union csr_tl_pm_dc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dc_aspm_enter_l0s_en : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 tl_dc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_27 : 7; /* [15:9] */ + u32 tl_dc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_28 : 7; /* [23:17] */ + u32 tl_dc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_dc_pcipm_l1_auto_enter : 1; /* [25] */ + u32 tl_dc_l2_pme2ack_direct_en : 1; /* [26] */ + u32 tl_aspml1_idle_fc_credit_dllp_chk : 1; /* [27] */ + u32 tl_dc_aspm_dstate_ari_chk : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_dc_ctrl_u; + +/* Define the union csr_tl_pm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_state : 6; /* [5:0] */ + u32 pm_pme_state : 2; /* [7:6] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_state_u; + +/* Define the union csr_tl_pm_uc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_uc_aspm_enter_l1_nak_en : 1; /* [0] */ + u32 rsv_31 : 5; /* [5:1] */ + u32 tl_uc_aspm_l1_nak_auto_reply : 1; /* [6] */ + u32 tl_uc_aspm_l1_ack_auto_reply : 1; /* [7] */ + u32 tl_uc_aspm_enter_l1_en : 1; /* [8] */ + u32 rsv_32 : 7; /* [15:9] */ + u32 tl_uc_pcipm_enter_l1_en : 1; /* [16] */ + u32 rsv_33 : 7; /* [23:17] */ + u32 tl_uc_pcipm_enter_l2_en : 1; /* [24] */ + u32 tl_uc_turnoff_msg_req : 1; /* [25] */ + u32 rsv_34 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_uc_ctrl_u; + +/* Define the union csr_tl_enter_l0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_enter_l0_en : 1; /* [0] */ + u32 tl_retrain_link_en : 1; /* [1] */ + u32 rsv_35 : 6; /* [7:2] */ + u32 tl_aspm_stop : 1; /* [8] */ + u32 rsv_36 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_enter_l0_ctrl_u; + +/* Define the union csr_tl_pm_timeout_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_timeout_en : 1; /* [0] */ + u32 rsv_37 : 7; /* [7:1] */ + u32 tl_pm_timeout_value : 16; /* [23:8] */ + u32 tl_pm_pme_timeout_value : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_timeout_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_tx_commonmode_en : 1; /* [0] */ + u32 tl_pm_rx_eidetect_en : 1; /* [1] */ + u32 tl_pm_power_off_en : 1; /* [2] */ + u32 rsv_38 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_l1substate_ctrl_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_l11_exit_time_value : 8; /* [7:0] */ + u32 tl_l12_time_value : 8; /* [15:8] */ + u32 tl_poweroff_time_value : 8; /* [23:16] */ + u32 tl_l10_exit_timeout_en : 1; /* [24] */ + u32 tl_l11_exit_timeout_en : 1; /* [25] */ + u32 tl_l12_timeout_en : 1; /* [26] */ + u32 tl_poweroff_timeout_en : 1; /* [27] */ + u32 tl_poweron_timeout_en : 1; /* [28] */ + u32 rsv_39 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_l1substate_time_cfg0_u; + +/* Define the union csr_tl_pm_l1substate_time_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pm_dfe_time_value : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_l1substate_time_cfg1_u; + +/* Define the union csr_tl_rx_odr_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_odr_ctrl_mode : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_odr_ctrl_mode_u; + +/* Define the union csr_tl_rx_pfx_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg2tl_pfx_filter : 4; /* [3:0] */ + u32 rsv_42 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_pfx_filter_u; + +/* Define the union csr_system_err_override_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 override_system_err_en : 3; /* [2:0] */ + u32 system_err_int_disable : 1; /* [3] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 rppio_system_err_en : 2; /* [9:8] */ + u32 rppio_uncor_err_type : 2; /* [11:10] */ + u32 system_dpc_cor_err_en : 1; /* [12] */ + u32 system_dpc_int_disable : 1; /* [13] */ + u32 rsv_44 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_system_err_override_control_u; + +/* Define the union csr_tl_cfg_hck_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_hck_attr_en : 1; /* [0] */ + u32 tl_cfg_hck_rw_en : 1; /* [1] */ + u32 pcie_30version_set : 1; /* [2] */ + u32 lower_skp_gen_flr_disable : 1; /* [3] */ + u32 pcie_nvme_mode : 1; /* [4] */ + u32 tl_cfg_tph_ctrl : 1; /* [5] */ + u32 tl_cfg_mc_aer_en : 1; /* [6] */ + u32 tl_cfg_acs_aer_en : 1; /* [7] */ + u32 tl_cfgcpl_crs_en : 1; /* [8] */ + u32 tl_cfgcpl_crs_return : 1; /* [9] */ + u32 tl_apb_trigger_slot_msg : 1; /* [10] */ + u32 rsv_45 : 1; /* [11] */ + u32 rsv_46 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_cfg_hck_en_u; + +/* Define the union csr_tl_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_error_int_rvd_0 : 1; /* [0] */ + u32 tl_error_int_rvd_1 : 1; /* [1] */ + u32 tl_rx_aer_err : 1; /* [2] */ + u32 tl_rx_cpl_credit_ovf : 1; /* [3] */ + u32 rsv_47 : 1; /* [4] */ + u32 tl_tx_bus_master_en_err : 1; /* [5] */ + u32 tl_tx_vc0_p_tc_map_err : 1; /* [6] */ + u32 tl_tx_vc0_np_tc_map_err : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_map_err : 1; /* [8] */ + u32 tl_tx_vc1_p_tc_map_err : 1; /* [9] */ + u32 tl_tx_rp_pf_vf_err : 1; /* [10] */ + u32 tl_rx_opt_ccix_err : 1; /* [11] */ + u32 tl_rx_buf_wr_full_err : 1; /* [12] */ + u32 dpc_trig_err : 1; /* [13] */ + u32 tl_cfg_doe_ep_err : 1; /* [14] */ + u32 tl_cfg_doe_rdy_tout : 1; /* [15] */ + u32 tl_error_int_rvd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_status0_u; + +/* Define the union csr_tl_int_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aspm_dc_enter_l1_int : 1; /* [0] */ + u32 tl_pcipm_dc_enter_l1_int : 1; /* [1] */ + u32 tl_pcipm_uc_enter_l1_int : 1; /* [2] */ + u32 tl_aspm_uc_enter_l1_int : 1; /* [3] */ + u32 pme_state_chg_int : 1; /* [4] */ + u32 tl_pcipm_dc_enter_l2_int : 1; /* [5] */ + u32 tl_pcipm_uc_enter_l2_int : 1; /* [6] */ + u32 tl_pcipm_dc_ready_l2_int : 1; /* [7] */ + u32 tl_first_cfgwr_ready : 1; /* [8] */ + u32 tl_cfg_vf_online : 1; /* [9] */ + u32 tl_cfg_vf_offline : 1; /* [10] */ + u32 tl_cfg_bdf_change : 1; /* [11] */ + u32 tl_pcipm_uc_rx_pme2ack : 1; /* [12] */ + u32 tl_cfg_doe_fifo_int : 1; /* [13] */ + u32 tl_cfg_doe_go_int : 1; /* [14] */ + u32 tl_reg_doe_abort_int : 1; /* [15] */ + u32 tl_normal_int_rvd2 : 1; /* [16] */ + u32 att_indicator_ctrl_chge : 1; /* [17] */ + u32 pwr_indicator_ctrl_chge : 1; /* [18] */ + u32 pwr_ctrler_ctrl_chge : 1; /* [19] */ + u32 tl_pm_bord_wakeup_int : 1; /* [20] */ + u32 tl_pm_l1ss_link_active_int : 1; /* [21] */ + u32 tl_tx_context_cpl_tout : 1; /* [22] */ + u32 tl_pm_dl_l2_gnt_timeout_int : 1; /* [23] */ + u32 tl_pm_dl_l1_gnt_timeout_int : 1; /* [24] */ + u32 tl_pm_dl_l0s_gnt_timeout_int : 1; /* [25] */ + u32 tl_pm_blk_tlp_timeout_int : 1; /* [26] */ + u32 tl_pm_lastack_timeout_int : 1; /* [27] */ + u32 tl_cfg_dfx_doe_empty_rd : 1; /* [28] */ + u32 tl_cfg_dfx_doe_full_wr : 1; /* [29] */ + u32 tl_nomal_int_rvd : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_status1_u; + +/* Define the union csr_tl_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_mask0_u; + +/* Define the union csr_tl_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_set0_u; + +/* Define the union csr_tl_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_ro0_u; + +/* Define the union csr_tl_int_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_mask1_u; + +/* Define the union csr_tl_int_set1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_set1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_set1_u; + +/* Define the union csr_tl_int_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ro1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_ro1_u; + +/* Define the union csr_tl_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_sel0_u; + +/* Define the union csr_tl_int_ce_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_ce_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_ce_ro_u; + +/* Define the union csr_tl_int_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_nfe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_nfe_ro_u; + +/* Define the union csr_tl_int_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_int_fe_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_int_fe_ro_u; + +/* Define the union csr_tl_tx_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_sel : 2; /* [1:0] */ + u32 rsv_48 : 2; /* [3:2] */ + u32 dfx_order_np_cpl_sel : 1; /* [4] */ + u32 rsv_49 : 4; /* [8:5] */ + u32 left_cdt_captu_en : 1; /* [9] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 tl_tx_order_pass : 1; /* [16] */ + u32 tl_tx_range_order : 1; /* [17] */ + u32 tl_tx_np_ro_order_pass : 1; /* [18] */ + u32 tl_tx_cpl_ro_order_pass : 1; /* [19] */ + u32 rsv_51 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_dfx_ctrl_u; + +/* Define the union csr_tl_tx_sync_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_full : 1; /* [0] */ + u32 tx_sync_np_dat0_full : 1; /* [1] */ + u32 tx_sync_np_dat1_full : 1; /* [2] */ + u32 tx_sync_np_dat2_full : 1; /* [3] */ + u32 tx_sync_np_dat3_full : 1; /* [4] */ + u32 tx_sync_p_hed_full : 1; /* [5] */ + u32 tx_sync_p_dat0_full : 1; /* [6] */ + u32 tx_sync_p_dat1_full : 1; /* [7] */ + u32 tx_sync_p_dat2_full : 1; /* [8] */ + u32 tx_sync_p_dat3_full : 1; /* [9] */ + u32 tx_sync_cpl_hed_full : 1; /* [10] */ + u32 tx_sync_cpl_dat0_full : 1; /* [11] */ + u32 tx_sync_cpl_dat1_full : 1; /* [12] */ + u32 tx_sync_cpl_dat2_full : 1; /* [13] */ + u32 tx_sync_cpl_dat3_full : 1; /* [14] */ + u32 rsv_52 : 1; /* [15] */ + u32 tx_sync_np_hed_empty : 1; /* [16] */ + u32 tx_sync_np_dat0_empty : 1; /* [17] */ + u32 tx_sync_np_dat1_empty : 1; /* [18] */ + u32 tx_sync_np_dat2_empty : 1; /* [19] */ + u32 tx_sync_np_dat3_empty : 1; /* [20] */ + u32 tx_sync_p_hed_empty : 1; /* [21] */ + u32 tx_sync_p_dat0_empty : 1; /* [22] */ + u32 tx_sync_p_dat1_empty : 1; /* [23] */ + u32 tx_sync_p_dat2_empty : 1; /* [24] */ + u32 tx_sync_p_dat3_empty : 1; /* [25] */ + u32 tx_sync_cpl_hed_empty : 1; /* [26] */ + u32 tx_sync_cpl_dat0_empty : 1; /* [27] */ + u32 tx_sync_cpl_dat1_empty : 1; /* [28] */ + u32 tx_sync_cpl_dat2_empty : 1; /* [29] */ + u32 tx_sync_cpl_dat3_empty : 1; /* [30] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_sync_fifo_st_u; + +/* Define the union csr_tl_tx_whole_tlp_hed_vld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_whole_tlp_np_hed_vld : 1; /* [0] */ + u32 tx_whole_tlp_p_hed_vld : 1; /* [1] */ + u32 tx_whole_tlp_cpl_hed_vld : 1; /* [2] */ + u32 rsv_54 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_whole_tlp_hed_vld_u; + +/* Define the union csr_tl_tx_ur_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ur_cnt : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_ur_cnt_u; + +/* Define the union csr_tl_tx_vc0_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_ph_fc_left : 12; /* [11:0] */ + u32 rsv_56 : 4; /* [15:12] */ + u32 tl_tx_vc0_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc0_p_fc_left_u; + +/* Define the union csr_tl_tx_vc0_np_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_nph_fc_left : 12; /* [11:0] */ + u32 rsv_57 : 4; /* [15:12] */ + u32 tl_tx_vc0_npd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc0_np_fc_left_u; + +/* Define the union csr_tl_tx_vc0_cpl_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_cplh_fc_left : 12; /* [11:0] */ + u32 rsv_58 : 4; /* [15:12] */ + u32 tl_tx_vc0_cpld_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc0_cpl_fc_left_u; + +/* Define the union csr_tl_tx_vc1_p_fc_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc1_ph_fc_left : 12; /* [11:0] */ + u32 rsv_59 : 4; /* [15:12] */ + u32 tl_tx_vc1_pd_fc_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc1_p_fc_left_u; + +/* Define the union csr_tl_tx_tc_maperr_tc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_vc0_p_tc_maperr_tc : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 tl_tx_vc0_np_tc_maperr_tc : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 tl_tx_vc0_cpl_tc_maperr_tc : 3; /* [10:8] */ + u32 rsv_62 : 1; /* [11] */ + u32 tl_tx_vc1_p_tc_maperr_tc : 3; /* [14:12] */ + u32 rsv_63 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_tc_maperr_tc_u; + +/* Define the union csr_tl_tx_vc_cc_scal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_vc_d_cc : 16; /* [15:0] */ + u32 dfx_vc_h_cc : 12; /* [27:16] */ + u32 dfx_vc_d_scale : 2; /* [29:28] */ + u32 dfx_vc_h__scale : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc_cc_scal_u; + +/* Define the union csr_tl_tx_vc_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_d_inf : 1; /* [0] */ + u32 dfx_vc_h_inf : 1; /* [1] */ + u32 rsv_64 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc_inf_u; + +/* Define the union csr_tl_tx_order_p_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_p_rang_num : 11; /* [10:0] */ + u32 rsv_65 : 5; /* [15:11] */ + u32 dfx_p_send_num : 11; /* [26:16] */ + u32 rsv_66 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_order_p_num_u; + +/* Define the union csr_tl_tx_order_np_cpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dft_np_cpl_range_num : 11; /* [10:0] */ + u32 rsv_67 : 5; /* [15:11] */ + u32 dfx_np_cpl_p_num : 11; /* [26:16] */ + u32 rsv_68 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_order_np_cpl_num_u; + +/* Define the union csr_tl_tx_np_cpl_crd_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 np_cpl_hed_crd_used_cnt : 12; /* [11:0] */ + u32 rsv_69 : 4; /* [15:12] */ + u32 np_cpl_dat_crd_used_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_np_cpl_crd_used_u; + +/* Define the union csr_tl_tx_vc_loc_crd_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_loc_crd_limit : 12; /* [11:0] */ + u32 rsv_70 : 4; /* [15:12] */ + u32 dfx_vc_d_loc_crd_limit : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc_loc_crd_limit_u; + +/* Define the union csr_tl_tx_vc_com_crd_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_vc_h_com_crd_cc : 12; /* [11:0] */ + u32 rsv_71 : 4; /* [15:12] */ + u32 dfx_vc_d_com_crd_cc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_vc_com_crd_cc_u; + +/* Define the union csr_tl_tx_tag_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_tag_used_cnt : 10; /* [9:0] */ + u32 rsv_72 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_tag_used_u; + +/* Define the union csr_tl_cfgspace_bdf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_bus_num : 8; /* [7:0] */ + u32 tl_cfg_dev_num : 5; /* [12:8] */ + u32 rsv_73 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_cfgspace_bdf_u; + +/* Define the union csr_tl_tx_ltr_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ltr_msg_cnt : 8; /* [7:0] */ + u32 rsv_74 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_ltr_msg_cnt_u; + +/* Define the union csr_tl_tx_sync_fifo_overflow_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_sync_np_hed_overflow : 1; /* [0] */ + u32 tx_sync_np_dat0_overflow : 1; /* [1] */ + u32 tx_sync_np_dat1_overflow : 1; /* [2] */ + u32 tx_sync_np_dat2_overflow : 1; /* [3] */ + u32 tx_sync_np_dat3_overflow : 1; /* [4] */ + u32 tx_sync_p_hed_overflow : 1; /* [5] */ + u32 tx_sync_p_dat0_overflow : 1; /* [6] */ + u32 tx_sync_p_dat1_overflow : 1; /* [7] */ + u32 tx_sync_p_dat2_overflow : 1; /* [8] */ + u32 tx_sync_p_dat3_overflow : 1; /* [9] */ + u32 tx_sync_cpl_hed_overflow : 1; /* [10] */ + u32 tx_sync_cpl_dat0_overflow : 1; /* [11] */ + u32 tx_sync_cpl_dat1_overflow : 1; /* [12] */ + u32 tx_sync_cpl_dat2_overflow : 1; /* [13] */ + u32 tx_sync_cpl_dat3_overflow : 1; /* [14] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_tx_sync_fifo_overflow_sts_u; + +/* Define the union csr_tl_rx_vc0_post_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_ph_credit_left : 12; /* [11:0] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 tl_rx_vc0_pd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_vc0_post_credit_left_u; + +/* Define the union csr_tl_rx_vc0_nonpost_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_nph_credit_left : 12; /* [11:0] */ + u32 rsv_77 : 4; /* [15:12] */ + u32 tl_rx_vc0_npd_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_vc0_nonpost_credit_left_u; + +/* Define the union csr_tl_rx_vc0_cpl_credit_left_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_vc0_cplh_credit_left : 12; /* [11:0] */ + u32 rsv_78 : 4; /* [15:12] */ + u32 tl_rx_vc0_cpld_credit_left : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_vc0_cpl_credit_left_u; + +/* Define the union csr_rx_rx_buffer_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_79 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_rx_rx_buffer_status_u; + +/* Define the union csr_tl_rx_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_80 : 4; /* [15:12] */ + u32 tl_pd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_posted_credit_u; + +/* Define the union csr_tl_rx_non_posted_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt : 12; /* [11:0] */ + u32 rsv_81 : 4; /* [15:12] */ + u32 tl_npd_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_non_posted_credit_u; + +/* Define the union csr_tl_rx_cpl_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt : 12; /* [11:0] */ + u32 rsv_82 : 4; /* [15:12] */ + u32 tl_cpld_vc0_cdt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cpl_credit_u; + +/* Define the union csr_tl_rx_cdt_ini_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up : 1; /* [0] */ + u32 rsv_83 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cdt_ini_up_u; + +/* Define the union csr_tl_rx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_aer_cnt : 4; /* [3:0] */ + u32 rsv_84 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_err_cnt_u; + +/* Define the union csr_tl_rx_null_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplchk_null_cnt : 4; /* [3:0] */ + u32 tl_rx_dect_null_cnt : 4; /* [7:4] */ + u32 tl_rx_dl_null_cnt : 4; /* [11:8] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 tl_rx_drop_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_null_cnt_u; + +/* Define the union csr_tl_rx_ur_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ur_p_cnt : 4; /* [3:0] */ + u32 tl_rx_ur_np_cnt : 4; /* [7:4] */ + u32 tl_rx_ur_cpl_cnt : 4; /* [11:8] */ + u32 rsv_86 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ur_tlp_cnt_u; + +/* Define the union csr_tl_rx_total_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_total_tlp_cnt : 16; /* [15:0] */ + u32 rsv_87 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_total_cnt_u; + +/* Define the union csr_tl_rx_total_tr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_p_cnt : 16; /* [15:0] */ + u32 tl_rx_buf_o_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_total_tr_cnt_u; + +/* Define the union csr_tl_rx_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_o_cpl_cnt : 16; /* [15:0] */ + u32 rsv_88 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_drop_cnt_u; + +/* Define the union csr_tl_rx_post_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_p_cnt : 16; /* [15:0] */ + u32 rsv_89 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_post_cnt_u; + +/* Define the union csr_tl_rx_nonpost_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_np_cnt : 16; /* [15:0] */ + u32 rsv_90 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_nonpost_cnt_u; + +/* Define the union csr_tl_rx_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_91 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cpl_cnt_u; + +/* Define the union csr_tl_rx_loc_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_loc_np_cnt : 8; /* [7:0] */ + u32 tl_rx_loc_p_cnt : 8; /* [15:8] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_loc_tlp_cnt_u; + +/* Define the union csr_tl_rx_port_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx0_u; + +/* Define the union csr_tl_rx_port_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx1_u; + +/* Define the union csr_tl_rx_port_dfx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx2_u; + +/* Define the union csr_tl_rx_port_dfx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx3_u; + +/* Define the union csr_tl_rx_port_dfx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx4_u; + +/* Define the union csr_tl_rx_port_dfx5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx5_u; + +/* Define the union csr_tl_rx_port_dfx6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx6_u; + +/* Define the union csr_tl_rx_port_dfx7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx7_u; + +/* Define the union csr_tl_rx_port_dfx8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_port_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_port_dfx8_u; + +/* Define the union csr_tl_rx_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_pd_vc0_scale : 2; /* [13:12] */ + u32 tl_ph_vc0_scale : 2; /* [15:14] */ + u32 tl_pd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_posted_credit_df_u; + +/* Define the union csr_tl_rx_non_posted_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_nph_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_npd_vc0_scale : 2; /* [13:12] */ + u32 tl_nph_vc0_scale : 2; /* [15:14] */ + u32 tl_npd_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_non_posted_credit_df_u; + +/* Define the union csr_tl_rx_cpl_credit_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cplh_vc0_cdt_df : 12; /* [11:0] */ + u32 tl_cpld_vc0_scale : 2; /* [13:12] */ + u32 tl_cplh_vc0_scale : 2; /* [15:14] */ + u32 tl_cpld_vc0_cdt_df : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cpl_credit_df_u; + +/* Define the union csr_tl_rx_cdt_ini_up_df_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cdt_ini_up_df : 1; /* [0] */ + u32 rsv_93 : 7; /* [7:1] */ + u32 tl_cpl_cdt_infi_en : 1; /* [8] */ + u32 rsv_94 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cdt_ini_up_df_u; + +/* Define the union csr_rx_asyn_stone_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_95 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_rx_asyn_stone_fifo_status_u; + +/* Define the union csr_tl_rx_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ep_err : 1; /* [0] */ + u32 tl_rx_ecrc_err : 1; /* [1] */ + u32 tl_rx_mal_err : 1; /* [2] */ + u32 tl_rx_ur_err : 1; /* [3] */ + u32 tl_rx_uc_err : 1; /* [4] */ + u32 tl_rx_port_fifo0_ovfl : 1; /* [5] */ + u32 tl_rx_port_fifo1_ovfl : 1; /* [6] */ + u32 tl_rx_port_fifo2_ovfl : 1; /* [7] */ + u32 tl_rx_port_fifo3_ovfl : 1; /* [8] */ + u32 tl_rx_len_short_err : 1; /* [9] */ + u32 tl_rx_len_long_err : 1; /* [10] */ + u32 tl_rx_port_fifo4_ovfl : 1; /* [11] */ + u32 tl_rx_port_fifo5_ovfl : 1; /* [12] */ + u32 tl_rx_port_fifo6_ovfl : 1; /* [13] */ + u32 tl_rx_port_fifo7_ovfl : 1; /* [14] */ + u32 tl_rx_port_fifo8_ovfl : 1; /* [15] */ + u32 tl_rx_port_fifo9_ovfl : 1; /* [16] */ + u32 tl_rx_port_fifo10_ovfl : 1; /* [17] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_err_status_u; + +/* Define the union csr_tl_rx_ecc_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_97 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ecc_error_status_u; + +/* Define the union csr_tl_rx_bp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_98 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_bp_ctrl_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_99 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ecc_1bit_err_u; + +/* Define the union csr_tl_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_101 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_ecc_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_102 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_ecc_2bit_err_u; + +/* Define the union csr_tl_rx_insert_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_103 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_insert_ecc_err_u; + +/* Define the union csr_tl_rx_posted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_104 : 4; /* [15:12] */ + u32 tl_rx_pd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_posted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_nposted_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_nph_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_105 : 4; /* [15:12] */ + u32 tl_rx_npd_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_nposted_credit_waterline_cfg_u; + +/* Define the union csr_tl_rx_cpl_credit_waterline_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cplh_vc0_cdt_wl_cfg : 12; /* [11:0] */ + u32 rsv_106 : 4; /* [15:12] */ + u32 tl_rx_cpld_vc0_cdt_wl_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cpl_credit_waterline_cfg_u; + +/* Define the union csr_tl_pm_dl_l2_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l2_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l2_gnt_timeout_en : 1; /* [16] */ + u32 rsv_107 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_dl_l2_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l1_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l1_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l1_gnt_timeout_en : 1; /* [16] */ + u32 rsv_108 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_dl_l1_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_dl_l0s_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_l0s_gnt_time_value : 16; /* [15:0] */ + u32 tl_dl_l0s_gnt_timeout_en : 1; /* [16] */ + u32 rsv_109 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_dl_l0s_gnt_time_cfg_u; + +/* Define the union csr_tl_pm_l1substate_refclk_stabel_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_refclk_stable_l11_time_value : 16; /* [15:0] */ + u32 tl_refclk_stable_l12_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_l1substate_refclk_stabel_time_cfg_u; + +/* Define the union csr_pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_pm_status_u; + +/* Define the union csr_tl_pm_lastack_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_dl_lastack_time_value : 16; /* [15:0] */ + u32 tl_dl_lastack_timeout_en : 1; /* [16] */ + u32 rsv_111 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_lastack_time_cfg_u; + +/* Define the union csr_tl_pm_ltr_lattency_rcv_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_uc_rx_nosoop_time_value : 16; /* [15:0] */ + u32 dfx_pm_uc_rx_soop_time_value : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_ltr_lattency_rcv_dfx_u; + +/* Define the union csr_pm_status_fifo_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_recap : 1; /* [0] */ + u32 dfx_pm_tracer_cap_mode : 1; /* [1] */ + u32 dfx_pm_tracer_ren : 1; /* [2] */ + u32 dfx_pm_tracer_raddr : 5; /* [7:3] */ + u32 dfx_pm_tracer_last_waddr : 6; /* [13:8] */ + u32 dfx_pm_func_en : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_pm_status_fifo_control_u; + +/* Define the union csr_pm_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pm_tracer_out_info : 15; /* [14:0] */ + u32 rsv_112 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_pm_status1_u; + +/* Define the union csr_pm_clkchange_req_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_req_hold_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_pm_clkchange_req_time_u; + +/* Define the union csr_pm_clkchange_gnt_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_clkchange_gnt_ack_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_pm_clkchange_gnt_time_u; + +/* Define the union csr_tl_pm_blk_tlp_gnt_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_blk_tlp_timeout_value : 16; /* [15:0] */ + u32 tl_blk_tlp_timeout_en : 1; /* [16] */ + u32 rsv_113 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_blk_tlp_gnt_time_cfg_u; + +/* Define the union csr_doe_cap_crs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_fifo_empty : 1; /* [0] */ + u32 msg_fifo_full : 1; /* [1] */ + u32 msg_last_word : 1; /* [2] */ + u32 rsv_114 : 1; /* [3] */ + u32 rdy_timeout_val : 13; /* [16:4] */ + u32 rsv_115 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_doe_cap_crs_u; + +/* Define the union csr_doe_cap_rd_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_rd_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_doe_cap_rd_dat_u; + +/* Define the union csr_doe_cap_wr_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_cap_wr_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_doe_cap_wr_dat_u; + +/* Define the union csr_tl_pm_l10_wait_ack_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l10_wait_ack_timeout_value : 20; /* [19:0] */ + u32 l10_wait_ack_timeout_en : 1; /* [20] */ + u32 rsv_116 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_pm_l10_wait_ack_timeout_u; + +/* Define the union csr_tl_rx_trace_cmp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_cmp_en : 21; /* [20:0] */ + u32 tl_rx_trace_tlp_sel : 1; /* [21] */ + u32 tl_rx_trace_tlp_en : 1; /* [22] */ + u32 rsv_117 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_trace_cmp_en_u; + +/* Define the union csr_tl_rx_ref_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ref_header_dw0_u; + +/* Define the union csr_tl_rx_ref_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ref_header_dw1_u; + +/* Define the union csr_tl_rx_ref_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ref_header_dw2_u; + +/* Define the union csr_tl_rx_ref_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ref_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_ref_header_dw3_u; + +/* Define the union csr_tl_rx_cap_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cap_header_dw0_u; + +/* Define the union csr_tl_rx_cap_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cap_header_dw1_u; + +/* Define the union csr_tl_rx_cap_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cap_header_dw2_u; + +/* Define the union csr_tl_rx_cap_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cap_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_cap_header_dw3_u; + +/* Define the union csr_tl_rx_tract_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_trace_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_rx_tract_tlp_cnt_u; + +/* Define the union csr_tl_cfg_doe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st1_wr_cnt : 8; /* [7:0] */ + u32 tl_cfg_dfx_fifo_st1_rd_cnt : 8; /* [15:8] */ + u32 tl_cfg_dfx_fifo_st0_wr_cnt : 8; /* [23:16] */ + u32 tl_cfg_dfx_fifo_st0_rd_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_cfg_doe_cnt_u; + +/* Define the union csr_tl_cfg_doe_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfg_dfx_fifo_st : 1; /* [0] */ + u32 tl_cfg_dfx_fifo_cnt : 3; /* [3:1] */ + u32 tl_cfg_dfx_finish_clr_pos : 1; /* [4] */ + u32 tl_cfg_dfx_finish_clr_neg : 1; /* [5] */ + u32 rsv_118 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_tl_cfg_doe_sts_u; + +/* Define the union csr_eco_tl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl : 16; /* [15:0] */ + u32 rsv_119 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_reg_7_eco_tl_u; + +/* Define the union csr_aptl_asyn_fifo_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_out_th : 5; /* [4:0] */ + u32 rsv_0 : 3; /* [7:5] */ + u32 tl_tx_out_mode : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_aptl_asyn_fifo_ctrl_u; + +/* Define the union csr_core_tl_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_pcie_whole_tlp_mode : 1; /* [0] */ + u32 tl_tx_ccix_whole_tlp_mode : 1; /* [1] */ + u32 rsv_2 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_core_tl_tx_ctrl_u; + +/* Define the union csr_tl_tx_cpl_check_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_cpl_ctxt_check_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_cpl_check_ctrl_u; + +/* Define the union csr_tx_crd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_cfg0_crd_active_cfg : 1; /* [0] */ + u32 rp_cfg0_crd_active_sel : 1; /* [1] */ + u32 rsv_3 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tx_crd_ctrl_u; + +/* Define the union csr_tl_reg_cfg_access_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ap_rdata_sel : 2; /* [1:0] */ + u32 rsv_4 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_reg_cfg_access_ctrl_u; + +/* Define the union csr_tl_insert_tlp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_req : 1; /* [0] */ + u32 rsv_5 : 7; /* [7:1] */ + u32 tlp_req_finish : 1; /* [8] */ + u32 rsv_6 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_ctrl_u; + +/* Define the union csr_tl_insert_tlp_header0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_header0_u; + +/* Define the union csr_tl_insert_tlp_header1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_header1_u; + +/* Define the union csr_tl_insert_tlp_header2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_header2_u; + +/* Define the union csr_tl_insert_tlp_header3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_header3_u; + +/* Define the union csr_tl_tlp_fun_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_pf_num : 5; /* [4:0] */ + u32 rsv_7 : 3; /* [7:5] */ + u32 tlp_vf_num : 8; /* [15:8] */ + u32 tlp_port_num : 4; /* [19:16] */ + u32 rsv_8 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tlp_fun_sel_u; + +/* Define the union csr_tl_insert_tlp_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_data_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_data0_u; + +/* Define the union csr_tl_insert_tlp_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_data_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_data1_u; + +/* Define the union csr_tl_insert_tlp_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_data_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_data2_u; + +/* Define the union csr_tl_insert_tlp_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_data_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_insert_tlp_data3_u; + +/* Define the union csr_tl_tx_cpl_timer_cfg01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cpl_timer_cfg0 : 16; /* [15:0] */ + u32 tl_tx_cpl_timer_cfg1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_cpl_timer_cfg01_u; + +/* Define the union csr_tl_tx_cpl_timer_cfg23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cpl_timer_cfg2 : 16; /* [15:0] */ + u32 tl_tx_cpl_timer_cfg3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_cpl_timer_cfg23_u; + +/* Define the union csr_tl_tx_cpl_timer_cfg45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cpl_timer_cfg4 : 16; /* [15:0] */ + u32 tl_tx_cpl_timer_cfg5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_cpl_timer_cfg45_u; + +/* Define the union csr_tl_tx_cpl_timer_cfg67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cpl_timer_cfg6 : 16; /* [15:0] */ + u32 tl_tx_cpl_timer_cfg7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_cpl_timer_cfg67_u; + +/* Define the union csr_tl_tx_cpl_timer_cfg8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cpl_timer_cfg8 : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_cpl_timer_cfg8_u; + +/* Define the union csr_tl_wait_idle_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_wait_idle_timer_cfg : 12; /* [11:0] */ + u32 rsv_10 : 4; /* [15:12] */ + u32 tl_wait_idle_timer_unit : 2; /* [17:16] */ + u32 rsv_11 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_wait_idle_timer_u; + +/* Define the union csr_tl_port_idle_tout_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_port_idle_tout_timer_cfg : 12; /* [11:0] */ + u32 rsv_12 : 4; /* [15:12] */ + u32 tl_port_idle_tout_timer_unit : 2; /* [17:16] */ + u32 rsv_13 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_port_idle_tout_timer_u; + +/* Define the union csr_tl_rx_cdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_itf_active_dfx_cfg : 4; /* [3:0] */ + u32 tlreg_rx_itf_cdt_dfx_cfg : 4; /* [7:4] */ + u32 tlreg_rx_1st_cdt_en : 4; /* [11:8] */ + u32 tlreg_rx_1st_cnt_clr_en : 4; /* [15:12] */ + u32 tlreg_rx_cdt_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_cdt_cfg_u; + +/* Define the union csr_tl_rx_atomic_drop_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_p2p_atomic_drop_en : 1; /* [0] */ + u32 tlreg_rx_nonp2p_0_atomic_drop_en : 1; /* [1] */ + u32 tlreg_rx_nonp2p_1_atomic_drop_en : 1; /* [2] */ + u32 tlreg_rx_nonp2p_2_atomic_drop_en : 1; /* [3] */ + u32 rsv_14 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_atomic_drop_cfg_u; + +/* Define the union csr_tl_rx_misc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_misc_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_misc_cfg_u; + +/* Define the union csr_tl_rx_hidx_fifo_th_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_p_hidx_buf_aful_th : 4; /* [3:0] */ + u32 tlreg_rx_np0_hidx_buf_aful_th : 4; /* [7:4] */ + u32 tlreg_rx_np1_hidx_buf_aful_th : 4; /* [11:8] */ + u32 tlreg_rx_cpl1_hidx_buf_aful_th : 4; /* [15:12] */ + u32 tlreg_rx_cpl2_hidx_buf_aful_th : 4; /* [19:16] */ + u32 tlreg_rx_cpl0_hidx_buf_aful_th : 6; /* [25:20] */ + u32 tlreg_rx_cpl3_hidx_buf_aful_th : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_hidx_fifo_th_value_u; + +/* Define the union csr_tl_rx_cplh_fifo_th_value_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_glb_cplh_buf_aful_th : 4; /* [3:0] */ + u32 tlreg_rx_port_cplh_buf_aful_th : 4; /* [7:4] */ + u32 tlreg_rx_port_cpld_buf_aful_th : 4; /* [11:8] */ + u32 rsv_15 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_cplh_fifo_th_value_u; + +/* Define the union csr_tl_rx_msi_addr_window_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_msi_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_msi_addr_window_l_u; + +/* Define the union csr_tl_rx_msi_addr_window_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_rx_msi_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_rx_msi_addr_window_h_u; + +/* Define the union csr_cfg_vpd_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_int : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_vpd_int_status_u; + +/* Define the union csr_cfg_vpd_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_int_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_vpd_int_mask_u; + +/* Define the union csr_cfg_vpd_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_int_set : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_vpd_int_set_u; + +/* Define the union csr_cfg_vpd_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_int_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_vpd_int_ro_u; + +/* Define the union csr_cfg_flr_int_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_flr_int_sel : 1; /* [0] */ + u32 tl_vpd_int_sel : 1; /* [1] */ + u32 rsv_16 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_flr_int_sel_u; + +/* Define the union csr_tl_core_int_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_ecc_1bit_err : 1; /* [0] */ + u32 tl_ecc_2bit_err : 1; /* [1] */ + u32 tl_rx_fifo_ovfl0 : 1; /* [2] */ + u32 tl_rx_fifo_ovfl1 : 1; /* [3] */ + u32 tl_rx_fifo_ovfl2 : 1; /* [4] */ + u32 tl_rx_fifo_ovfl3 : 1; /* [5] */ + u32 tl_rx_fifo_ovfl4 : 1; /* [6] */ + u32 tl_rx_fifo_ovfl5 : 1; /* [7] */ + u32 tl_rx_fifo_ovfl6 : 1; /* [8] */ + u32 tl_rx_fifo_ovfl7 : 1; /* [9] */ + u32 tl_rx_fifo_ovfl8 : 1; /* [10] */ + u32 tl_rx_fifo_ovfl9 : 1; /* [11] */ + u32 tl_rx_fifo_ovfl10 : 1; /* [12] */ + u32 tl_rx_fifo_ovfl11 : 1; /* [13] */ + u32 tl_rx_fifo_ovfl12 : 1; /* [14] */ + u32 tl_rx_fifo_ovfl13 : 1; /* [15] */ + u32 tl_rx_fifo_ovfl14 : 1; /* [16] */ + u32 tl_rx_fifo_ovfl15 : 1; /* [17] */ + u32 tl_rx_fifo_ovfl16 : 1; /* [18] */ + u32 tl_rx_fifo_ovfl17 : 1; /* [19] */ + u32 tl_rx_fifo_ovfl18 : 1; /* [20] */ + u32 tl_core_error_int_rvd : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_core_int_status0_u; + +/* Define the union csr_tl_core_int_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_core_int_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_core_int_mask0_u; + +/* Define the union csr_tl_core_int_set0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_core_int_set0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_core_int_set0_u; + +/* Define the union csr_tl_core_int_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_core_int_ro0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_core_int_ro0_u; + +/* Define the union csr_tl_core_int_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_core_int_sel0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_core_int_sel0_u; + +/* Define the union csr_tl_cfg_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sram_ini : 1; /* [0] */ + u32 rsv_17 : 15; /* [15:1] */ + u32 tl_cfgspace_sram_ini_finish : 1; /* [16] */ + u32 rsv_18 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_cfg_ctrl_u; + +/* Define the union csr_tl_cfg_pf_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pf_support_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_cfg_pf_en_u; + +/* Define the union csr_tl_port_used_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_port_used : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_port_used_u; + +/* Define the union csr_pn_pf_str_idx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_pf_str_idx : 5; /* [4:0] */ + u32 rsv_19 : 3; /* [7:5] */ + u32 port1_pf_str_idx : 5; /* [12:8] */ + u32 rsv_20 : 3; /* [15:13] */ + u32 port2_pf_str_idx : 5; /* [20:16] */ + u32 rsv_21 : 3; /* [23:21] */ + u32 port3_pf_str_idx : 5; /* [28:24] */ + u32 rsv_22 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pn_pf_str_idx0_u; + +/* Define the union csr_pn_pf_str_idx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port4_pf_str_idx : 5; /* [4:0] */ + u32 rsv_23 : 3; /* [7:5] */ + u32 port5_pf_str_idx : 5; /* [12:8] */ + u32 rsv_24 : 3; /* [15:13] */ + u32 port6_pf_str_idx : 5; /* [20:16] */ + u32 rsv_25 : 3; /* [23:21] */ + u32 port7_pf_str_idx : 5; /* [28:24] */ + u32 rsv_26 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pn_pf_str_idx1_u; + +/* Define the union csr_pn_pf_str_idx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port8_pf_str_idx : 5; /* [4:0] */ + u32 rsv_27 : 3; /* [7:5] */ + u32 port9_pf_str_idx : 5; /* [12:8] */ + u32 rsv_28 : 3; /* [15:13] */ + u32 port10_pf_str_idx : 5; /* [20:16] */ + u32 rsv_29 : 3; /* [23:21] */ + u32 port11_pf_str_idx : 5; /* [28:24] */ + u32 rsv_30 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pn_pf_str_idx2_u; + +/* Define the union csr_pn_pf_str_idx3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port12_pf_str_idx : 5; /* [4:0] */ + u32 rsv_31 : 3; /* [7:5] */ + u32 port13_pf_str_idx : 5; /* [12:8] */ + u32 rsv_32 : 3; /* [15:13] */ + u32 port14_pf_str_idx : 5; /* [20:16] */ + u32 rsv_33 : 3; /* [23:21] */ + u32 port15_pf_str_idx : 5; /* [28:24] */ + u32 rsv_34 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pn_pf_str_idx3_u; + +/* Define the union csr_pn_pf_str_idx4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_pf_str_idx : 5; /* [4:0] */ + u32 rsv_35 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pn_pf_str_idx4_u; + +/* Define the union csr_cfg_pf_vf_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pf_vf_map_mode : 3; /* [2:0] */ + u32 rsv_36 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_pf_vf_ctrl_u; + +/* Define the union csr_pf_flr_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_cfg_flr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pf_flr_int_mask_u; + +/* Define the union csr_pf_flr_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_cfg_flr_int_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pf_flr_int_status_u; + +/* Define the union csr_pf_flr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_flr_rst : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_pf_flr_en_u; + +/* Define the union csr_vf_device_id0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id0 : 16; /* [15:0] */ + u32 vf_device_id1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id0_u; + +/* Define the union csr_vf_device_id1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id2 : 16; /* [15:0] */ + u32 vf_device_id3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id1_u; + +/* Define the union csr_vf_device_id2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id4 : 16; /* [15:0] */ + u32 vf_device_id5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id2_u; + +/* Define the union csr_vf_device_id3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id6 : 16; /* [15:0] */ + u32 vf_device_id7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id3_u; + +/* Define the union csr_vf_device_id4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id8 : 16; /* [15:0] */ + u32 vf_device_id9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id4_u; + +/* Define the union csr_vf_device_id5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id10 : 16; /* [15:0] */ + u32 vf_device_id11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id5_u; + +/* Define the union csr_vf_device_id6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id12 : 16; /* [15:0] */ + u32 vf_device_id13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id6_u; + +/* Define the union csr_vf_device_id7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_device_id14 : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_device_id7_u; + +/* Define the union csr_vf_vendor_id0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_vendor_id0 : 16; /* [15:0] */ + u32 vf_vendor_id1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_vendor_id0_u; + +/* Define the union csr_vf_vendor_id1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_vendor_id2 : 16; /* [15:0] */ + u32 rsv_38 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_vendor_id1_u; + +/* Define the union csr_vf_class_code0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_class_code0 : 24; /* [23:0] */ + u32 rsv_39 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_class_code0_u; + +/* Define the union csr_vf_class_code1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_class_code1 : 24; /* [23:0] */ + u32 rsv_40 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_class_code1_u; + +/* Define the union csr_vf_class_code2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_class_code2 : 24; /* [23:0] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_vf_class_code2_u; + +/* Define the union csr_cfg_flr_disable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_flr_disable : 1; /* [0] */ + u32 tl_flr_rst_en : 1; /* [1] */ + u32 rsv_42 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_flr_disable_u; + +/* Define the union csr_tl_tx_tag_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlreg_max_tag_div4 : 8; /* [7:0] */ + u32 tlreg_tag_rls : 1; /* [8] */ + u32 rsv_43 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_tx_tag_ctrl_u; + +/* Define the union csr_cfg_pfn_vf_online_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_online_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_pfn_vf_online_st_u; + +/* Define the union csr_cfg_pfn_vf_offline_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_vf_offline_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_cfg_pfn_vf_offline_st_u; + +/* Define the union csr_tl_core_eco_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_tl_core : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_reg_tl_core_eco_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_0_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_1_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_2_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_3_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_4_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_5_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_6_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_7_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_8_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_9_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_10_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_11_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_12_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_13_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_14_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_15_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_16_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_17_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_18_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_19_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_20_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_21_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_22_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_23_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_24_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_25_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_26_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_27_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_28_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_29_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_30_pfn_vf_tph_st_u; + +/* Define the union csr_tl_cfg_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_func_sel : 3; /* [2:0] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_tl_cfg_pf_func_sel_u; + +/* Define the union csr_tl_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_cfgspace_sel : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_tl_cfgspace_sel_u; + +/* Define the union csr_tl_pf_vf_cfgspace_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfgspace_sel : 16; /* [15:0] */ + u32 pf_cfgspace_sel2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_tl_pf_vf_cfgspace_sel_u; + +/* Define the union csr_pfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_bar0_mask_u; + +/* Define the union csr_pfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_bar1_mask_u; + +/* Define the union csr_pfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_bar2_mask_u; + +/* Define the union csr_pfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_bar3_mask_u; + +/* Define the union csr_pfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_bar4_mask_u; + +/* Define the union csr_pfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_bar5_mask_u; + +/* Define the union csr_pfn_rom_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_rom_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_rom_mask_u; + +/* Define the union csr_pfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_bar_enable : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 pfn_rom_bar_enable : 1; /* [8] */ + u32 rsv_2 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_barn_enable_u; + +/* Define the union csr_vfn_bar0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_bar0_mask_u; + +/* Define the union csr_vfn_bar1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar1_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_bar1_mask_u; + +/* Define the union csr_vfn_bar2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar2_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_bar2_mask_u; + +/* Define the union csr_vfn_bar3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar3_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_bar3_mask_u; + +/* Define the union csr_vfn_bar4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar4_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_bar4_mask_u; + +/* Define the union csr_vfn_bar5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar5_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_bar5_mask_u; + +/* Define the union csr_vfn_barn_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfn_bar_enable : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_vfn_barn_enable_u; + +/* Define the union csr_msix_control_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_size : 11; /* [10:0] */ + u32 rsv_4 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_msix_control_reg_u; + +/* Define the union csr_msix_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_msix_table_bir : 3; /* [2:0] */ + u32 tl_msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_msix_offset_bir_reg_u; + +/* Define the union csr_pba_offset_bir_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_pba_table_bir : 3; /* [2:0] */ + u32 tl_pba_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pba_offset_bir_reg_u; + +/* Define the union csr_pfn_ari_next_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_ari_next_addr : 12; /* [11:0] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_ari_next_addr_u; + +/* Define the union csr_pfn_vf_vendor_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pfn_vf_vendor_id : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_vf_vendor_id_u; + +/* Define the union csr_pfn_vf_tph_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_sup : 1; /* [0] */ + u32 int_vector_mode_sup : 1; /* [1] */ + u32 device_spc_mode_sup : 1; /* [2] */ + u32 st_table_location : 2; /* [4:3] */ + u32 st_table_size : 11; /* [15:5] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_pf_reg_31_pfn_vf_tph_st_u; + +/* Define the union csr_vf_flr_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfg_flr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_vf_reg_vf_flr_int_mask_u; + +/* Define the union csr_vf_flr_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_cfg_flr_int_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_vf_reg_vf_flr_int_status_u; + +/* Define the union csr_vf_flr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flr_rst : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_vf_reg_vf_flr_en_u; + + +/* Define the union csr_tl_tx_asyn_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap2tl_tx_grp0_fifo_full : 1; /* [0] */ + u32 ap2tl_tx_grp1_fifo_full : 1; /* [1] */ + u32 tltx2ap_crd_fifo_full : 1; /* [2] */ + u32 tl2ap_cfg_tx_fifo_full : 1; /* [3] */ + u32 ap2tl_cfg_rx_fifo_full : 1; /* [4] */ + u32 tl2ap_misc_fifo_full : 1; /* [5] */ + u32 cpi2tl_tx_grp0_fifo_full : 1; /* [6] */ + u32 cpi2tl_tx_grp1_fifo_full : 1; /* [7] */ + u32 tltx2cpi_crd_fifo_full : 1; /* [8] */ + u32 cpi2tl_err_rpt_fifo_full : 1; /* [9] */ + u32 tl2cpi_cfg_tx_fifo_full : 1; /* [10] */ + u32 cpi2tl_cfg_rx_fifo_full : 1; /* [11] */ + u32 tl2cpi_misc_tx_fifo_full : 1; /* [12] */ + u32 tl2cpi_misc_rx_fifo_full : 1; /* [13] */ + u32 rsv_0 : 2; /* [15:14] */ + u32 ap2tl_tx_grp0_fifo_empty : 1; /* [16] */ + u32 ap2tl_tx_grp1_fifo_empty : 1; /* [17] */ + u32 tltx2ap_crd_fifo_empty : 1; /* [18] */ + u32 tl2ap_cfg_tx_fifo_empty : 1; /* [19] */ + u32 ap2tl_cfg_rx_fifo_empty : 1; /* [20] */ + u32 tl2ap_misc_fifo_empty : 1; /* [21] */ + u32 cpi2tl_tx_grp0_fifo_empty : 1; /* [22] */ + u32 cpi2tl_tx_grp1_fifo_empty : 1; /* [23] */ + u32 tltx2cpi_crd_fifo_empty : 1; /* [24] */ + u32 cpi2tl_err_rpt_fifo_empty : 1; /* [25] */ + u32 tl2cpi_cfg_tx_fifo_empty : 1; /* [26] */ + u32 cpi2tl_cfg_rx_fifo_empty : 1; /* [27] */ + u32 tl2cpi_misc_tx_fifo_empty : 1; /* [28] */ + u32 tl2cpi_misc_rx_fifo_empty : 1; /* [29] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_asyn_fifo_st_u; + +/* Define the union csr_tl_tx_ingress_egress_cnt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ingress_tlp_type : 8; /* [7:0] */ + u32 ingress_tlp_map_en : 1; /* [8] */ + u32 rsv_2 : 7; /* [15:9] */ + u32 egress_lane_map : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ingress_egress_cnt_ctrl_u; + +/* Define the union csr_tl_tx_ingress_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ingress_cnt : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ingress_cnt_u; + +/* Define the union csr_tl_tx_ctrl_egress_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ctrl_egress_cnt : 16; /* [15:0] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ctrl_egress_cnt_u; + +/* Define the union csr_tl_tx_sch_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_sch_fifo_hed_full : 4; /* [3:0] */ + u32 tl_tx_sch_fifo_dat_full : 4; /* [7:4] */ + u32 rsv_5 : 8; /* [15:8] */ + u32 tl_tx_sch_fifo_hed_empty : 4; /* [19:16] */ + u32 tl_tx_sch_fifo_dat_empty : 4; /* [23:20] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_sch_fifo_st_u; + +/* Define the union csr_tl_tx_ctrl_hs_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tl2dl_tx_vld : 16; /* [15:0] */ + u32 dfx_dl2tl_tx_rdy : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ctrl_hs_st_u; + +/* Define the union csr_tl_tx_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ecc_cfg : 4; /* [3:0] */ + u32 rsv_7 : 24; /* [27:4] */ + u32 tl_tx_ecc_type : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ecc_cfg_u; + +/* Define the union csr_tl_tx_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ecc_1bit_err_st : 4; /* [3:0] */ + u32 tl_tx_ecc_1bit_err_addr : 10; /* [13:4] */ + u32 rsv_8 : 2; /* [15:14] */ + u32 tl_tx_ecc_2bit_err_st : 4; /* [19:16] */ + u32 tl_tx_ecc_2bit_err_addr : 10; /* [29:20] */ + u32 rsv_9 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ecc_err_addr_u; + +/* Define the union csr_tl_tx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ecc_1bit_err_cnt : 8; /* [7:0] */ + u32 rsv_10 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_tx_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ecc_2bit_err_cnt : 8; /* [7:0] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_tx_err_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_p_dat0_ecc_1bit_err : 1; /* [0] */ + u32 tl_tx_p_dat1_ecc_1bit_err : 1; /* [1] */ + u32 tl_tx_p_dat2_ecc_1bit_err : 1; /* [2] */ + u32 tl_tx_p_dat3_ecc_1bit_err : 1; /* [3] */ + u32 tl_tx_cpl_dat0_ecc_1bit_err : 1; /* [4] */ + u32 tl_tx_cpl_dat1_ecc_1bit_err : 1; /* [5] */ + u32 tl_tx_cpl_dat2_ecc_1bit_err : 1; /* [6] */ + u32 tl_tx_cpl_dat3_ecc_1bit_err : 1; /* [7] */ + u32 tl_tx_p_dat0_ecc_2bit_err : 1; /* [8] */ + u32 tl_tx_p_dat1_ecc_2bit_err : 1; /* [9] */ + u32 tl_tx_p_dat2_ecc_2bit_err : 1; /* [10] */ + u32 tl_tx_p_dat3_ecc_2bit_err : 1; /* [11] */ + u32 tl_tx_cpl_dat0_ecc_2bit_err : 1; /* [12] */ + u32 tl_tx_cpl_dat1_ecc_2bit_err : 1; /* [13] */ + u32 tl_tx_cpl_dat2_ecc_2bit_err : 1; /* [14] */ + u32 tl_tx_cpl_dat3_ecc_2bit_err : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_err_error_status_u; + +/* Define the union csr_tl_cnt_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_flow_cnt_en : 1; /* [0] */ + u32 tl_tx_err_cnt_en : 1; /* [1] */ + u32 tl_tx_nat_cpl_cnt_en : 1; /* [2] */ + u32 tl_tx_fun_en : 1; /* [3] */ + u32 tl_tx_flow_cnt_time : 12; /* [15:4] */ + u32 rsv_13 : 3; /* [18:16] */ + u32 tl_tx_dl_bp_en : 1; /* [19] */ + u32 tl_tx_fun_vf_num : 8; /* [27:20] */ + u32 tl_tx_hed_captu_en : 1; /* [28] */ + u32 tl_tx_insert_captu_en : 1; /* [29] */ + u32 tl_tx_ecrc_insert_en : 1; /* [30] */ + u32 rsv_14 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_cnt_ctrl_u; + +/* Define the union csr_tl_tx_ecrc_err_insert_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_ecrc_err_cnt : 6; /* [5:0] */ + u32 rsv_15 : 2; /* [7:6] */ + u32 tl_tx_ecrc_port_num : 4; /* [11:8] */ + u32 tl_tx_insert_captu_port_num : 4; /* [15:12] */ + u32 tl_tx_tlp_cnt_port_num : 4; /* [19:16] */ + u32 tl_tx_captu_point : 1; /* [20] */ + u32 tl_tx_fun_pf_num : 5; /* [25:21] */ + u32 rsv_16 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ecrc_err_insert_cnt_u; + +/* Define the union csr_tl_tx_cnt_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_flow_cnt_done : 1; /* [0] */ + u32 tl_tx_insert_hed_done : 1; /* [1] */ + u32 tl_tx_captu_hed_done : 1; /* [2] */ + u32 tl_tx_ecrc_insert_done : 1; /* [3] */ + u32 rsv_17 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_cnt_st_u; + +/* Define the union csr_tl_tx_captu_field_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_0_u; + +/* Define the union csr_tl_tx_captu_field_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_1_u; + +/* Define the union csr_tl_tx_captu_field_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_2_u; + +/* Define the union csr_tl_tx_captu_field_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_3_u; + +/* Define the union csr_tl_tx_captu_field_map_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_map_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_map_0_u; + +/* Define the union csr_tl_tx_captu_field_map_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_map_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_map_1_u; + +/* Define the union csr_tl_tx_captu_field_map_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_map_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_map_2_u; + +/* Define the union csr_tl_tx_captu_field_map_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_field_map_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_field_map_3_u; + +/* Define the union csr_tl_tx_captu_hed_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_hed_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_hed_0_u; + +/* Define the union csr_tl_tx_captu_hed_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_hed_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_hed_1_u; + +/* Define the union csr_tl_tx_captu_hed_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_hed_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_hed_2_u; + +/* Define the union csr_tl_tx_captu_hed_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_captu_hed_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_captu_hed_3_u; + +/* Define the union csr_tl_tx_cfg_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cfg_fifo_cnt : 8; /* [7:0] */ + u32 rsv_18 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_cfg_fifo_cnt_u; + +/* Define the union csr_tl_tx_mem_rd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_mrd_cnt : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_mem_rd_cnt_u; + +/* Define the union csr_tl_tx_mem_wr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_mwr_cnt : 16; /* [15:0] */ + u32 rsv_20 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_mem_wr_cnt_u; + +/* Define the union csr_tl_tx_io_rd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_iord_cnt : 16; /* [15:0] */ + u32 rsv_21 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_io_rd_cnt_u; + +/* Define the union csr_tl_tx_io_wr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_iowr_cnt : 16; /* [15:0] */ + u32 rsv_22 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_io_wr_cnt_u; + +/* Define the union csr_tl_tx_msg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_msg_cnt : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_msg_cnt_u; + +/* Define the union csr_tl_tx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_cpl_cnt : 16; /* [15:0] */ + u32 rsv_24 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_err_cnt_u; + +/* Define the union csr_tl_tx_atomic_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_atomic_cnt : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_atomic_cnt_u; + +/* Define the union csr_tl_tx_p2p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_p2p_cnt : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_p2p_cnt_u; + +/* Define the union csr_tl_tx_gen_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_gen_cpl_cnt : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_gen_cpl_cnt_u; + +/* Define the union csr_tl_tx_atomic_blk_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_atomic_blk_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_atomic_blk_cnt_u; + +/* Define the union csr_tl_tx_pfx_blk_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_pfx_blk_cnt : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_pfx_blk_cnt_u; + +/* Define the union csr_tl_tx_poison_blk_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_poison_blk_cnt : 8; /* [7:0] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_poison_blk_cnt_u; + +/* Define the union csr_tl_tx_fun_tlp_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_fun_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_fun_tlp_tlp_cnt_u; + +/* Define the union csr_tl_tx_fun_payload_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_fun_payload_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_fun_payload_cnt_u; + +/* Define the union csr_tl_tx_fun_all_dw_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx_fun_all_dw_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_fun_all_dw_cnt_u; + +/* Define the union csr_tl_tx_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_fifo_sts_u; + +/* Define the union csr_tl_tx_context_dfx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_query_en : 1; /* [0] */ + u32 tx_context_entry_captu_en : 1; /* [1] */ + u32 rsv_32 : 6; /* [7:2] */ + u32 tx_context_entry_idx : 10; /* [17:8] */ + u32 rsv_33 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_dfx_ctrl_u; + +/* Define the union csr_tl_tx_context_entry_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_info_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_dw0_u; + +/* Define the union csr_tl_tx_context_entry_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_info_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_dw1_u; + +/* Define the union csr_tl_tx_context_entry_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_info_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_dw2_u; + +/* Define the union csr_tl_tx_context_entry_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_info_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_dw3_u; + +/* Define the union csr_tl_tx_context_entry_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_info_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_dw4_u; + +/* Define the union csr_tl_tx_context_entry_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_cpl_check_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_err_info_u; + +/* Define the union csr_tl_tx_context_entry_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_entry_captu_finish : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 tx_context_entry_err_chn : 4; /* [7:4] */ + u32 rsv_35 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_entry_err_status_u; + +/* Define the union csr_tl_tx_context_chech_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_check_cnt : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_chech_cnt_u; + +/* Define the union csr_tl_tx_context_check_uc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_uc_cnt : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_check_uc_cnt_u; + +/* Define the union csr_tl_tx_context_check_malform_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_malform_cnt : 16; /* [15:0] */ + u32 rsv_38 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_check_malform_cnt_u; + +/* Define the union csr_tl_tx_context_check_merge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_merge_cnt : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_check_merge_cnt_u; + +/* Define the union csr_tl_tx_context_tout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_context_tout_cnt : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_context_tout_cnt_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_ptr_sel : 4; /* [3:0] */ + u32 rsv_41 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_sel_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p0_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p1_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p2_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p3_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p4_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p5_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p6_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p7_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p8_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p9_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p10_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p11_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p12_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p13_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p14_u; + +/* Define the union csr_tl_rx_dfx_odr_ptr_p15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_qlite_ptr_p15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ptr_p15_u; + +/* Define the union csr_tl_rx_dfx_odr_ctrl_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_ctrl_idle : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_ctrl_idle_u; + +/* Define the union csr_tl_rx_dfx_odr_queue_idle_p0p3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_queue_idle_p0 : 8; /* [7:0] */ + u32 tl_rx_dfx_odr_queue_idle_p1 : 8; /* [15:8] */ + u32 tl_rx_dfx_odr_queue_idle_p2 : 8; /* [23:16] */ + u32 tl_rx_dfx_odr_queue_idle_p3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_queue_idle_p0p3_u; + +/* Define the union csr_tl_rx_dfx_odr_queue_idle_p4p7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_queue_idle_p4 : 8; /* [7:0] */ + u32 tl_rx_dfx_odr_queue_idle_p5 : 8; /* [15:8] */ + u32 tl_rx_dfx_odr_queue_idle_p6 : 8; /* [23:16] */ + u32 tl_rx_dfx_odr_queue_idle_p7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_queue_idle_p4p7_u; + +/* Define the union csr_tl_rx_dfx_odr_queue_idle_p8p11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_queue_idle_p8 : 8; /* [7:0] */ + u32 tl_rx_dfx_odr_queue_idle_p9 : 8; /* [15:8] */ + u32 tl_rx_dfx_odr_queue_idle_p10 : 8; /* [23:16] */ + u32 tl_rx_dfx_odr_queue_idle_p11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_queue_idle_p8p11_u; + +/* Define the union csr_tl_rx_dfx_odr_queue_idle_p12p15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_dfx_odr_queue_idle_p12 : 8; /* [7:0] */ + u32 tl_rx_dfx_odr_queue_idle_p13 : 8; /* [15:8] */ + u32 tl_rx_dfx_odr_queue_idle_p14 : 8; /* [23:16] */ + u32 tl_rx_dfx_odr_queue_idle_p15 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_odr_queue_idle_p12p15_u; + +/* Define the union csr_tl_rx_sdap_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_sdap_1st_tlp : 8; /* [7:0] */ + u32 tl_rx_sdap_2nd_tlp : 8; /* [15:8] */ + u32 tl_rx_apbk_nor_resp : 8; /* [23:16] */ + u32 tl_rx_apbk_err_resp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_sdap_cnt_u; + +/* Define the union csr_tl_rx_cnt_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cnt_dfx0 : 8; /* [7:0] */ + u32 tl_rx_cnt_dfx1 : 8; /* [15:8] */ + u32 tl_rx_cnt_dfx2 : 8; /* [23:16] */ + u32 tl_rx_cnt_dfx3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_cnt_dfx0_u; + +/* Define the union csr_tl_rx_cnt_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_cnt_dfx6 : 16; /* [15:0] */ + u32 tl_rx_cnt_dfx5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_cnt_dfx1_u; + +/* Define the union csr_tl_rx_dfx_buf_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_0_u; + +/* Define the union csr_tl_rx_dfx_buf_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_1_u; + +/* Define the union csr_tl_rx_dfx_buf_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_2_u; + +/* Define the union csr_tl_rx_dfx_buf_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_3_u; + +/* Define the union csr_tl_rx_dfx_buf_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_4_u; + +/* Define the union csr_tl_rx_dfx_buf_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_5_u; + +/* Define the union csr_tl_rx_dfx_buf_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_6_u; + +/* Define the union csr_tl_rx_dfx_buf_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_7_u; + +/* Define the union csr_tl_rx_dfx_buf_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_8_u; + +/* Define the union csr_tl_rx_dfx_buf_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_9_u; + +/* Define the union csr_tl_rx_dfx_buf_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_10_u; + +/* Define the union csr_tl_rx_dfx_buf_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_11_u; + +/* Define the union csr_tl_rx_dfx_buf_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_12_u; + +/* Define the union csr_tl_rx_dfx_buf_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_13_u; + +/* Define the union csr_tl_rx_dfx_buf_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_14_u; + +/* Define the union csr_tl_rx_dfx_buf_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_15_u; + +/* Define the union csr_tl_rx_buf_ptr_dfx_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_ptr_dfx_sel : 3; /* [2:0] */ + u32 rsv_43 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_buf_ptr_dfx_sel_u; + +/* Define the union csr_tl_rx_dfx_buf_16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_16_u; + +/* Define the union csr_tl_rx_dfx_buf_17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_17_u; + +/* Define the union csr_tl_rx_dfx_buf_18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_18_u; + +/* Define the union csr_tl_rx_dfx_buf_19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_buf_dfx19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_dfx_buf_19_u; + +/* Define the union csr_tl_rx_ecc_err_inject_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ecc_cfg : 4; /* [3:0] */ + u32 tl_rx_ecc_cfg_ram_sel : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_ecc_err_inject_cfg_u; + +/* Define the union csr_tl_rx_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ecc_1bit_err_addr : 11; /* [10:0] */ + u32 tl_rx_ecc_1bit_err_ram : 5; /* [15:11] */ + u32 tl_rx_ecc_2bit_err_addr : 11; /* [26:16] */ + u32 tl_rx_ecc_2bit_err_ram : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_ecc_err_addr_u; + +/* Define the union csr_tl_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ecc_1bit_err_pluse : 5; /* [4:0] */ + u32 rsv_44 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_tl_rx_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_ecc_2bit_err_pluse : 5; /* [4:0] */ + u32 rsv_45 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_ecc_2bit_err_cnt_u; + +/* Define the union csr_tl_aer_insert_uncor_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_46 : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 tl_dl_protocal_err_st : 1; /* [4] */ + u32 tl_sur_down_err_st : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 tl_poisoned_tlp_st : 1; /* [12] */ + u32 tl_fc_protocol_err_st : 1; /* [13] */ + u32 tl_cpl_timeeout_st : 1; /* [14] */ + u32 tl_cpl_abort_st : 1; /* [15] */ + u32 tl_unexp_cpl_st : 1; /* [16] */ + u32 tl_rcv_overflow_st : 1; /* [17] */ + u32 tl_mal_tlp_st : 1; /* [18] */ + u32 tl_ecrc_err_st : 1; /* [19] */ + u32 tl_ur_err_st : 1; /* [20] */ + u32 tl_acs_vio_st : 1; /* [21] */ + u32 tl_uncor_int_err_st : 1; /* [22] */ + u32 tl_mc_blk_st : 1; /* [23] */ + u32 tl_atomicop_eg_blk_st : 1; /* [24] */ + u32 tl_tlp_pfx_blk_err_st : 1; /* [25] */ + u32 tl_poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_insert_uncor_err_u; + +/* Define the union csr_tl_aer_insert_cor_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 tl_bad_tlp_st : 1; /* [6] */ + u32 tl_bad_dllp_st : 1; /* [7] */ + u32 tl_reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 tl_reply_timer_timout_st : 1; /* [12] */ + u32 tl_advisory_non_fatal_err_st : 1; /* [13] */ + u32 tl_cor_int_err_st : 1; /* [14] */ + u32 tl_header_log_overflow_st : 1; /* [15] */ + u32 tl_aer_insert_adv_ind : 1; /* [16] */ + u32 tl_aer_insert_port_level : 1; /* [17] */ + u32 rsv_52 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_insert_cor_err_u; + +/* Define the union csr_tl_aer_header_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aer_insert_header_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_header_dw0_u; + +/* Define the union csr_tl_aer_header_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aer_insert_header_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_header_dw1_u; + +/* Define the union csr_tl_aer_header_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aer_insert_header_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_header_dw2_u; + +/* Define the union csr_tl_aer_header_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aer_insert_header_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_header_dw3_u; + +/* Define the union csr_tl_aer_fun_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_aer_insert_vf_num : 12; /* [11:0] */ + u32 tl_aer_insert_pf_num : 5; /* [16:12] */ + u32 tl_aer_insert_port_num : 4; /* [20:17] */ + u32 rsv_53 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_aer_fun_num_u; + +/* Define the union csr_cfgspace_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfgspace_ecc_cfg : 4; /* [3:0] */ + u32 rsv_54 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_ecc_cfg_u; + +/* Define the union csr_cfgspace_ecc_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfgspace_ecc_1bit_err_addr : 12; /* [11:0] */ + u32 rsv_55 : 4; /* [15:12] */ + u32 cfgspace_ecc_2bit_err_addr : 12; /* [27:16] */ + u32 rsv_56 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_ecc_addr_u; + +/* Define the union csr_cfgspace_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfgspce_ecc_1bit_err_cnt : 8; /* [7:0] */ + u32 rsv_57 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_ecc_1bit_err_cnt_u; + +/* Define the union csr_cfgspace_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfgspace_ecc_2bit_err_cnt : 8; /* [7:0] */ + u32 rsv_58 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_ecc_2bit_err_cnt_u; + +/* Define the union csr_cfgspace_ecc_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfgspace_ecc_type : 1; /* [0] */ + u32 rsv_59 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_ecc_type_u; + +/* Define the union csr_cfgspace_ecc_err_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfgspace_ecc_1bit_err_st : 2; /* [1:0] */ + u32 rsv_60 : 14; /* [15:2] */ + u32 cfgspace_ecc_2bit_err_st : 2; /* [17:16] */ + u32 rsv_61 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_ecc_err_st_u; + +/* Define the union csr_cfgspace_hdk_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_access_ecam_rd_hdk : 1; /* [0] */ + u32 cfg_access_ecam_wr_hdk : 1; /* [1] */ + u32 cfg_access_apb_rd_hdk : 1; /* [2] */ + u32 cfg_access_apb_wr_hdk : 1; /* [3] */ + u32 tl2ap_cfg_ecam_rd_hdk : 1; /* [4] */ + u32 tl2ap_cfg_ecam_wr_hdk : 1; /* [5] */ + u32 tl2ap_cfg_apb_rd_hdk : 1; /* [6] */ + u32 tl2ap_cfg_apb_wr_hdk : 1; /* [7] */ + u32 tl_cfg_tx_cpl_hdk : 1; /* [8] */ + u32 tl_cfg_rx_cpl_hdk : 1; /* [9] */ + u32 tl_regif_rd_hdk : 1; /* [10] */ + u32 tl_regif_wr_hdk : 1; /* [11] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_cfgspace_hdk_status_u; + +/* Define the union csr_tl_cfg_pf_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_base_dfx : 5; /* [4:0] */ + u32 x_cfg_pf_num_dfx : 5; /* [9:5] */ + u32 rsv_63 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_cfg_pf_dfx_u; + +/* Define the union csr_tl_cfg_portn_num0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portn_num_hit_pf_dfx : 16; /* [15:0] */ + u32 portn_num_pf_dfx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_cfg_portn_num0_u; + +/* Define the union csr_tl_cfg_pf_aer_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxbuf_err_pf_num_dfx : 5; /* [4:0] */ + u32 rx_cfg_err_pf_num_dfx : 5; /* [9:5] */ + u32 tl_tx_err_pf_num_dfx : 5; /* [14:10] */ + u32 rsv_64 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_cfg_pf_aer_dfx_u; + +/* Define the union csr_tl_tx_tlp_gen_cpl_cache_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen_cpl_cache_full : 16; /* [15:0] */ + u32 gen_cpl_cache_empty : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_tlp_gen_cpl_cache_sts_u; + +/* Define the union csr_tl_tx_tlp_gen_p_cache_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen_p_cache_full : 16; /* [15:0] */ + u32 gen_p_cache_empty : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_tlp_gen_p_cache_sts_u; + +/* Define the union csr_tl_rx_tx_ur_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_ur_fifo_full : 16; /* [15:0] */ + u32 rx_ur_fifo_empty : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_rx_tx_ur_fifo_sts_u; + +/* Define the union csr_tl_tx_ur_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ur_fifo_full : 16; /* [15:0] */ + u32 ur_fifo_empty : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_ur_fifo_sts_u; + +/* Define the union csr_tl_tx_asyn_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_tx2ap_crd_fifo_cnt : 5; /* [4:0] */ + u32 ap2tl_tx_grp1_fifo_cnt : 5; /* [9:5] */ + u32 ap2tl_tx_grp0_fifo_cnt : 5; /* [14:10] */ + u32 rsv_65 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_tl_core_dfx_reg_tl_tx_asyn_fifo_cnt_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_0_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_1_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_2_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_3_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_4_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_5_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_6_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ari_ctrl_u; + +/* Define the union csr_doe_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_id : 16; /* [15:0] */ + u32 cap_version : 4; /* [19:16] */ + u32 next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_doe_hed_u; + +/* Define the union csr_doe_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_int_sup : 1; /* [0] */ + u32 doe_int_msg_num : 11; /* [11:1] */ + u32 rsv_62 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_doe_cap_u; + +/* Define the union csr_doe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_abort : 1; /* [0] */ + u32 doe_int_en : 1; /* [1] */ + u32 rsv_63 : 29; /* [30:2] */ + u32 doe_go : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_doe_ctrl_u; + +/* Define the union csr_doe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doe_busy : 1; /* [0] */ + u32 doe_int_status : 1; /* [1] */ + u32 doe_error : 1; /* [2] */ + u32 rsv_64 : 28; /* [30:3] */ + u32 doe_ready : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_doe_status_u; + +/* Define the union csr_wr_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_wr_data_mbox_u; + +/* Define the union csr_rd_data_mbox_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_mbox : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_rd_data_mbox_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_65 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_66 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_68 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_69 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_70 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_71 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_72 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_73 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_74 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_76 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_77 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_79 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_80 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_81 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_82 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_83 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_pasid_cap_ctrl_u; + +/* Define the union csr_secondary_pcie_ext_cap_hed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_ext_cap_id : 16; /* [15:0] */ + u32 sec_pcie_cap_version : 4; /* [19:16] */ + u32 sec_pcie_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_secondary_pcie_ext_cap_hed_u; + +/* Define the union csr_link_control3_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_perform_equaliz : 1; /* [0] */ + u32 sec_pcie_link_equaliz_req_int_en : 1; /* [1] */ + u32 rsv_84 : 7; /* [8:2] */ + u32 sec_pcie_lower_skp_en : 7; /* [15:9] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register_u; + +/* Define the union csr_lane_error_status_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_lane_err_staus : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_lane_error_status_reg_u; + +/* Define the union csr_link_control3_register01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln0_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln0_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 sec_pcie_8g_ln0_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln0_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_88 : 1; /* [15] */ + u32 sec_pcie_8g_ln1_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln1_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_89 : 1; /* [23] */ + u32 sec_pcie_8g_ln1_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln1_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_90 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register01_u; + +/* Define the union csr_link_control3_register23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln2_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln2_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_91 : 1; /* [7] */ + u32 sec_pcie_8g_ln2_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln2_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_92 : 1; /* [15] */ + u32 sec_pcie_8g_ln3_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln3_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_93 : 1; /* [23] */ + u32 sec_pcie_8g_ln3_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln3_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register23_u; + +/* Define the union csr_link_control3_register45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln4_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln4_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_95 : 1; /* [7] */ + u32 sec_pcie_8g_ln4_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln4_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_96 : 1; /* [15] */ + u32 sec_pcie_8g_ln5_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln5_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_97 : 1; /* [23] */ + u32 sec_pcie_8g_ln5_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln5_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register45_u; + +/* Define the union csr_link_control3_register67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln6_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln6_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_99 : 1; /* [7] */ + u32 sec_pcie_8g_ln6_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln6_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_100 : 1; /* [15] */ + u32 sec_pcie_8g_ln7_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln7_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_101 : 1; /* [23] */ + u32 sec_pcie_8g_ln7_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln7_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_102 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register67_u; + +/* Define the union csr_link_control3_register89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln8_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln8_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_103 : 1; /* [7] */ + u32 sec_pcie_8g_ln8_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln8_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_104 : 1; /* [15] */ + u32 sec_pcie_8g_ln9_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln9_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_105 : 1; /* [23] */ + u32 sec_pcie_8g_ln9_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln9_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_106 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register89_u; + +/* Define the union csr_link_control3_register1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln10_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln10_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_107 : 1; /* [7] */ + u32 sec_pcie_8g_ln10_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln10_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_108 : 1; /* [15] */ + u32 sec_pcie_8g_ln11_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln11_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_109 : 1; /* [23] */ + u32 sec_pcie_8g_ln11_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln11_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_110 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register1011_u; + +/* Define the union csr_link_control3_register1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln12_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln12_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_111 : 1; /* [7] */ + u32 sec_pcie_8g_ln12_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln12_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_112 : 1; /* [15] */ + u32 sec_pcie_8g_ln13_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln13_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 sec_pcie_8g_ln13_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln13_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_114 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register1213_u; + +/* Define the union csr_link_control3_register1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_pcie_8g_ln14_dp_tx_preset : 4; /* [3:0] */ + u32 sec_pcie_8g_ln14_dp_rx_preset_hint : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 sec_pcie_8g_ln14_up_tx_preset : 4; /* [11:8] */ + u32 sec_pcie_8g_ln14_up_rx_preset_hint : 3; /* [14:12] */ + u32 rsv_116 : 1; /* [15] */ + u32 sec_pcie_8g_ln15_dp_tx_preset : 4; /* [19:16] */ + u32 sec_pcie_8g_ln15_dp_rx_preset_hint : 3; /* [22:20] */ + u32 rsv_117 : 1; /* [23] */ + u32 sec_pcie_8g_ln15_up_tx_preset : 4; /* [27:24] */ + u32 sec_pcie_8g_ln15_up_rx_preset_hint : 3; /* [30:28] */ + u32 rsv_118 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_link_control3_register1415_u; + +/* Define the union csr_l1pm_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l1pm_cap_id : 16; /* [15:0] */ + u32 l1pm_cap_version : 4; /* [19:16] */ + u32 l1pm_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_l1pm_cap_header_u; + +/* Define the union csr_l1pm_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_support : 1; /* [0] */ + u32 pcipm_l1_1_support : 1; /* [1] */ + u32 aspm_l1_2_support : 1; /* [2] */ + u32 aspm_l1_1_support : 1; /* [3] */ + u32 l1pm_sub_support : 1; /* [4] */ + u32 link_active_support : 1; /* [5] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 port_com_mode_restore_time : 8; /* [15:8] */ + u32 port_t_power_on_scale : 2; /* [17:16] */ + u32 rsv_120 : 1; /* [18] */ + u32 port_t_power_on_value : 5; /* [23:19] */ + u32 rsv_121 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_l1pm_capability_u; + +/* Define the union csr_l1pm_control1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcipm_l1_2_en : 1; /* [0] */ + u32 pcipm_l1_1_en : 1; /* [1] */ + u32 aspm_l1_2_en : 1; /* [2] */ + u32 aspm_l1_1_en : 1; /* [3] */ + u32 link_active_int_en : 1; /* [4] */ + u32 link_active_ctrl : 1; /* [5] */ + u32 rsv_122 : 2; /* [7:6] */ + u32 com_mode_restore_time : 8; /* [15:8] */ + u32 ltr_l1_2_thre_value : 10; /* [25:16] */ + u32 rsv_123 : 3; /* [28:26] */ + u32 ltr_l1_2_thre_scale : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_l1pm_control1_u; + +/* Define the union csr_l1pm_control2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 t_power_on_scale : 2; /* [1:0] */ + u32 rsv_124 : 1; /* [2] */ + u32 t_power_on_value : 5; /* [7:3] */ + u32 rsv_125 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_l1pm_control2_u; + +/* Define the union csr_l1pm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_active_status : 1; /* [0] */ + u32 rsv_126 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_l1pm_status_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_127 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_128 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_acs_cap_0x04_u; + +/* Define the union csr_ltr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_ext_cap_id : 16; /* [15:0] */ + u32 ltr_cap_version : 4; /* [19:16] */ + u32 ltr_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ltr_cap_header_u; + +/* Define the union csr_ltr_max_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ltr_max_snoop_lat_value : 10; /* [9:0] */ + u32 ltr_max_snoop_lat_scale : 3; /* [12:10] */ + u32 rsv_129 : 3; /* [15:13] */ + u32 ltr_max_no_snoop_lat_value : 10; /* [25:16] */ + u32 ltr_max_no_snoop_lat_scale : 3; /* [28:26] */ + u32 rsv_130 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ltr_max_latency_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_131 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_132 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_dl_feature_cap_reg08_u; + +/* Define the union csr_rxmargin_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_capid : 16; /* [15:0] */ + u32 rxmargin_cap_version : 4; /* [19:16] */ + u32 rxmargin_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_rxmargin_cap_reg00_u; + +/* Define the union csr_rxmargin_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 margin_use_driver_soft : 1; /* [0] */ + u32 rsv_133 : 15; /* [15:1] */ + u32 margin_ready : 1; /* [16] */ + u32 margin_soft_ready : 1; /* [17] */ + u32 rsv_134 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_rxmargin_cap_reg04_u; + +/* Define the union csr_rxmargin_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 receiver_num : 3; /* [2:0] */ + u32 margin_type : 3; /* [5:3] */ + u32 usage_model : 1; /* [6] */ + u32 rsvdp_bit7 : 1; /* [7] */ + u32 margin_payload : 8; /* [15:8] */ + u32 receiver_num_status : 3; /* [18:16] */ + u32 margin_type_status : 3; /* [21:19] */ + u32 usage_model_status : 1; /* [22] */ + u32 rsvdp_bit23 : 1; /* [23] */ + u32 margin_payload_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_rxmargin_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_phy_capid : 16; /* [15:0] */ + u32 gen5_phy_cap_version : 4; /* [19:16] */ + u32 gen5_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg00_u; + +/* Define the union csr_gen5_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_support : 1; /* [0] */ + u32 no_eq_need_support : 1; /* [1] */ + u32 rsv_135 : 6; /* [7:2] */ + u32 modify_ts_usage_mode0_support : 1; /* [8] */ + u32 modify_ts_usage_mode1_support : 1; /* [9] */ + u32 modify_ts_usage_mode2_support : 1; /* [10] */ + u32 modify_ts_usage_mode_rsv : 5; /* [15:11] */ + u32 rsv_136 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg04_u; + +/* Define the union csr_gen5_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eq_bypass_to_highest_rate_disable : 1; /* [0] */ + u32 no_eq_need_disable : 1; /* [1] */ + u32 rsv_137 : 6; /* [7:2] */ + u32 modify_ts_usage_mode_sel : 3; /* [10:8] */ + u32 rsv_138 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg08_u; + +/* Define the union csr_gen5_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_32q_eq_complete : 1; /* [0] */ + u32 i_32g_eq_ph1_success : 1; /* [1] */ + u32 i_32g_eq_ph2_success : 1; /* [2] */ + u32 i_32g_eq_ph3_success : 1; /* [3] */ + u32 gen5_link_equalization_req : 1; /* [4] */ + u32 rx_modify_ts_r : 1; /* [5] */ + u32 i_rx_enhans_link_control : 2; /* [7:6] */ + u32 i_rx_transmitter_precoding_on : 1; /* [8] */ + u32 tx_precoding_req : 1; /* [9] */ + u32 rsv_139 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg0c_u; + +/* Define the union csr_gen5_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 i_rx_modify_ts_data1_info : 13; /* [15:3] */ + u32 i_rx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg10_u; + +/* Define the union csr_gen5_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 i_rx_modify_ts_data2_info : 24; /* [23:0] */ + u32 i_rx_alernate_protol_negatation_stauts : 2; /* [25:24] */ + u32 rsv_140 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg14_u; + +/* Define the union csr_gen5_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_usage_mode : 3; /* [2:0] */ + u32 tx_modify_ts_data1_info : 13; /* [15:3] */ + u32 tx_modify_ts_vender_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg18_u; + +/* Define the union csr_gen5_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_modify_ts_data2_info : 24; /* [23:0] */ + u32 tx_alernate_protol_negatation_status : 2; /* [25:24] */ + u32 rsv_141 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg1c_u; + +/* Define the union csr_gen5_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg20_u; + +/* Define the union csr_gen5_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg24_u; + +/* Define the union csr_gen5_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg28_u; + +/* Define the union csr_gen5_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen5_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen5_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen5_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen5_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen5_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen5_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen5_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen5_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen5_phy_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ccix_ts_capid : 16; /* [15:0] */ + u32 ccix_ts_cap_version : 4; /* [19:16] */ + u32 ccix_ts_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg00_u; + +/* Define the union csr_ccix_ts_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_vendor_id : 16; /* [15:0] */ + u32 dvsec_version : 4; /* [19:16] */ + u32 dvsec_length : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg04_u; + +/* Define the union csr_ccix_ts_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dvsec_id : 16; /* [15:0] */ + u32 esm_mode_sup : 1; /* [16] */ + u32 esm_phy_reach_len_cap : 2; /* [18:17] */ + u32 esm_recali_need_rate_update : 1; /* [19] */ + u32 esm_cali_timeout : 3; /* [22:20] */ + u32 rsv_142 : 1; /* [23] */ + u32 esm_quick_eq_timeout : 3; /* [26:24] */ + u32 rsv_143 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg08_u; + +/* Define the union csr_ccix_ts_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_support_rate : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg0c_u; + +/* Define the union csr_ccix_ts_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg10_u; + +/* Define the union csr_ccix_ts_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_cur_data_rate : 7; /* [6:0] */ + u32 esm_cali_done : 1; /* [7] */ + u32 rsv_145 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg14_u; + +/* Define the union csr_ccix_ts_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_data_rate0 : 7; /* [6:0] */ + u32 esm_perform_eq : 1; /* [7] */ + u32 esm_data_rate1 : 7; /* [14:8] */ + u32 esm_enable : 1; /* [15] */ + u32 esm_exteq_ph2_timeout : 3; /* [18:16] */ + u32 esm_compliance : 1; /* [19] */ + u32 esm_exteq_ph3_timeout : 3; /* [22:20] */ + u32 rsv_146 : 1; /* [23] */ + u32 link_reach_target : 1; /* [24] */ + u32 rsv_147 : 1; /* [25] */ + u32 quick_eq_timeout : 3; /* [28:26] */ + u32 rsv_148 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg18_u; + +/* Define the union csr_ccix_ts_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg1c_u; + +/* Define the union csr_ccix_ts_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg20_u; + +/* Define the union csr_ccix_ts_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg24_u; + +/* Define the union csr_ccix_ts_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_20g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_20g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_20g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_20g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_20g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_20g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_20g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_20g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg28_u; + +/* Define the union csr_ccix_ts_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane0 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane0 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane1 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane1 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane2 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane2 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane3 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane3 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg2c_u; + +/* Define the union csr_ccix_ts_cap_reg30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane4 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane4 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane5 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane5 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane6 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane6 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane7 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg30_u; + +/* Define the union csr_ccix_ts_cap_reg34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane8 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane8 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane9 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane9 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane10 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane10 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane11 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg34_u; + +/* Define the union csr_ccix_ts_cap_reg38_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esm_dp_25g_txpreset_lane12 : 4; /* [3:0] */ + u32 esm_up_25g_txpreset_lane12 : 4; /* [7:4] */ + u32 esm_dp_25g_txpreset_lane13 : 4; /* [11:8] */ + u32 esm_up_25g_txpreset_lane13 : 4; /* [15:12] */ + u32 esm_dp_25g_txpreset_lane14 : 4; /* [19:16] */ + u32 esm_up_25g_txpreset_lane14 : 4; /* [23:20] */ + u32 esm_dp_25g_txpreset_lane15 : 4; /* [27:24] */ + u32 esm_up_25g_txpreset_lane15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg38_u; + +/* Define the union csr_ccix_ts_cap_reg3c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_sup : 1; /* [0] */ + u32 rsv_149 : 7; /* [7:1] */ + u32 ccix_vc_index : 3; /* [10:8] */ + u32 rsv_150 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg3c_u; + +/* Define the union csr_ccix_ts_cap_reg40_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opt_tlp_format_en : 1; /* [0] */ + u32 tlp_length_chk_en : 1; /* [1] */ + u32 rsv_151 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_ccix_ts_cap_reg40_u; + +/* Define the union csr_gen4_phy_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_phy_capid : 16; /* [15:0] */ + u32 gen4_phy_cap_version : 4; /* [19:16] */ + u32 gen4_phy_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg00_u; + +/* Define the union csr_gen4_phy_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_152 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg04_u; + +/* Define the union csr_gen4_phy_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg08_u; + +/* Define the union csr_gen4_phy_cap_reg0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_eq_complete : 1; /* [0] */ + u32 gen4_eq_phase1_succ : 1; /* [1] */ + u32 gen4_eq_phase2_succ : 1; /* [2] */ + u32 gen4_eq_phase3_succ : 1; /* [3] */ + u32 gen4_link_equalization_req : 1; /* [4] */ + u32 rsv_154 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg0c_u; + +/* Define the union csr_gen4_phy_cap_reg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_data_parity_err : 16; /* [15:0] */ + u32 rsv_155 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg10_u; + +/* Define the union csr_gen4_phy_cap_reg14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer_data_parity_err : 16; /* [15:0] */ + u32 rsv_156 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg14_u; + +/* Define the union csr_gen4_phy_cap_reg18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 retimer2_data_parity_err : 16; /* [15:0] */ + u32 rsv_157 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg18_u; + +/* Define the union csr_gen4_phy_cap_reg1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_158 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg1c_u; + +/* Define the union csr_gen4_phy_cap_reg20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane0_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane0_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane1_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane1_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane2_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane2_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane3_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane3_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg20_u; + +/* Define the union csr_gen4_phy_cap_reg24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane4_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane4_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane5_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane5_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane6_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane6_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane7_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane7_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg24_u; + +/* Define the union csr_gen4_phy_cap_reg28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane8_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane8_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane9_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane9_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane10_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane10_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane11_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane11_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg28_u; + +/* Define the union csr_gen4_phy_cap_reg2c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen4_lane12_dp_tx_preset : 4; /* [3:0] */ + u32 gen4_lane12_up_tx_preset : 4; /* [7:4] */ + u32 gen4_lane13_dp_tx_preset : 4; /* [11:8] */ + u32 gen4_lane13_up_tx_preset : 4; /* [15:12] */ + u32 gen4_lane14_dp_tx_preset : 4; /* [19:16] */ + u32 gen4_lane14_up_tx_preset : 4; /* [23:20] */ + u32 gen4_lane15_dp_tx_preset : 4; /* [27:24] */ + u32 gen4_lane15_up_tx_preset : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epf_cfgspace_7_gen4_phy_cap_reg2c_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_0_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_1_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_2_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_3_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_4_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_5_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_6_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 5; /* [15:11] */ + u32 immediate_readiness : 1; /* [16] */ + u32 rsv_1 : 2; /* [18:17] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_2 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cachlie_size : 8; /* [7:0] */ + u32 cfg_latency_timer : 8; /* [15:8] */ + u32 cfg_header_type : 7; /* [22:16] */ + u32 multi_func_deivce : 1; /* [23] */ + u32 bist_result : 4; /* [27:24] */ + u32 rsv_3 : 2; /* [29:28] */ + u32 start_bist : 1; /* [30] */ + u32 bist_cap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_type : 1; /* [0] */ + u32 rsv_4 : 1; /* [1] */ + u32 cfg_bar0_width : 1; /* [2] */ + u32 cfg_bar0_prefetch_en : 1; /* [3] */ + u32 cfg_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_type : 1; /* [0] */ + u32 cfg_bar1_width : 2; /* [2:1] */ + u32 cfg_bar1_prefetch_en : 1; /* [3] */ + u32 cfg_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_type : 1; /* [0] */ + u32 rsv_5 : 1; /* [1] */ + u32 cfg_bar2_width : 1; /* [2] */ + u32 cfg_bar2_prefetch_en : 1; /* [3] */ + u32 cfg_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_type : 1; /* [0] */ + u32 cfg_bar3_width : 2; /* [2:1] */ + u32 cfg_bar3_prefetch_en : 1; /* [3] */ + u32 cfg_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_type : 1; /* [0] */ + u32 rsv_6 : 1; /* [1] */ + u32 cfg_bar4_width : 1; /* [2] */ + u32 cfg_bar4_prefetch_en : 1; /* [3] */ + u32 cfg_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_type : 1; /* [0] */ + u32 cfg_bar5_width : 2; /* [2:1] */ + u32 cfg_bar5_prefetch_en : 1; /* [3] */ + u32 cfg_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_enable : 1; /* [0] */ + u32 rsv_7 : 10; /* [10:1] */ + u32 ext_rom_base_addr : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_int_line : 8; /* [7:0] */ + u32 cfg_int_pin : 8; /* [15:8] */ + u32 cfg_min_gnt : 8; /* [23:16] */ + u32 cfg_max_lat : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phantom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 ecs_capable : 1; /* [16] */ + u32 rsv_11 : 1; /* [17] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phantom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 emergency_pwr_reduce_det : 1; /* [22] */ + u32 rsv_13 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_14 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aspm_ctrl : 2; /* [1:0] */ + u32 rsv_15 : 1; /* [2] */ + u32 rcb : 1; /* [3] */ + u32 link_disable : 1; /* [4] */ + u32 retrain_link : 1; /* [5] */ + u32 common_clk_cfg : 1; /* [6] */ + u32 extended_sync : 1; /* [7] */ + u32 clock_pm_en : 1; /* [8] */ + u32 hw_auto_width_dis : 1; /* [9] */ + u32 link_band_int_en : 1; /* [10] */ + u32 link_auto_band_int_en : 1; /* [11] */ + u32 rsv_16 : 2; /* [13:12] */ + u32 drs_signal_ctrl : 2; /* [15:14] */ + u32 mac_cur_link_speed : 4; /* [19:16] */ + u32 mac_cur_link_width : 6; /* [25:20] */ + u32 undefined_12 : 1; /* [26] */ + u32 link_training : 1; /* [27] */ + u32 slot_clk_cfg : 1; /* [28] */ + u32 dl_cfg_link_active : 1; /* [29] */ + u32 link_band_status : 1; /* [30] */ + u32 link_auto_band_status : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_button_pre : 1; /* [0] */ + u32 pwr_ctrl_pre : 1; /* [1] */ + u32 msl_sensor_pre : 1; /* [2] */ + u32 att_indecator_pre : 1; /* [3] */ + u32 pwr_indicator_pre : 1; /* [4] */ + u32 hot_plug_surprise : 1; /* [5] */ + u32 hot_plug_cap : 1; /* [6] */ + u32 slot_pwr_limit_val : 8; /* [14:7] */ + u32 slot_pwr_limit_scale : 2; /* [16:15] */ + u32 elec_interlock_pre : 1; /* [17] */ + u32 no_comman_cpled_sup : 1; /* [18] */ + u32 physical_slot_num : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 att_buttom_pre_en : 1; /* [0] */ + u32 pwr_fault_det_en : 1; /* [1] */ + u32 mrl_sensor_change_en : 1; /* [2] */ + u32 presence_det_change_en : 1; /* [3] */ + u32 command_cpled_int_en : 1; /* [4] */ + u32 hot_plug_int_en : 1; /* [5] */ + u32 att_indicator_ctrl : 2; /* [7:6] */ + u32 pwr_indicator_ctrl : 2; /* [9:8] */ + u32 pwr_ctrled_ctrl : 1; /* [10] */ + u32 elec_interlock_ctrl : 1; /* [11] */ + u32 dl_state_change_en : 1; /* [12] */ + u32 auto_slot_plmt_disable : 1; /* [13] */ + u32 rsv_17 : 2; /* [15:14] */ + u32 attention_button : 1; /* [16] */ + u32 pwr_fault_det : 1; /* [17] */ + u32 mrl_sensor_change : 1; /* [18] */ + u32 presencd_det_change : 1; /* [19] */ + u32 command_cpled : 1; /* [20] */ + u32 mrl_sensor_st : 1; /* [21] */ + u32 presencd_det_st : 1; /* [22] */ + u32 elec_interlock_st : 1; /* [23] */ + u32 dl_state_change : 1; /* [24] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_err_on_cor_err_en : 1; /* [0] */ + u32 sys_err_on_non_fat_en : 1; /* [1] */ + u32 sys_err_on_fat_err_en : 1; /* [2] */ + u32 pme_int_en : 1; /* [3] */ + u32 crs_sw_visibility_en : 1; /* [4] */ + u32 rsv_19 : 11; /* [15:5] */ + u32 crs_sw_visibility : 1; /* [16] */ + u32 rsv_20 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_rid : 16; /* [15:0] */ + u32 pme_status_rt : 1; /* [16] */ + u32 pme_pending : 1; /* [17] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_range : 4; /* [3:0] */ + u32 cpl_timeout_disable_sup : 1; /* [4] */ + u32 ari_fwd_sup : 1; /* [5] */ + u32 atomicop_route_sup : 1; /* [6] */ + u32 atomic_32bit_cpl_sup : 1; /* [7] */ + u32 atomic_64bit_cpl_sup : 1; /* [8] */ + u32 cas_128bit_cpl_sup : 1; /* [9] */ + u32 no_roen_prpr_pass : 1; /* [10] */ + u32 ltr_mech_sup : 1; /* [11] */ + u32 tph_cpl_sup : 2; /* [13:12] */ + u32 ln_sys_cls : 2; /* [15:14] */ + u32 sup_10bit_cpl_tag : 1; /* [16] */ + u32 sup_10bit_req_tag : 1; /* [17] */ + u32 obff_sup : 2; /* [19:18] */ + u32 ext_fmt_sup : 1; /* [20] */ + u32 end_end_pfx_sup : 1; /* [21] */ + u32 max_end_end_pfx : 2; /* [23:22] */ + u32 emergency_pwr_reduce_sup : 2; /* [25:24] */ + u32 emergency_pwr_reduce_init_req : 1; /* [26] */ + u32 rsv_22 : 4; /* [30:27] */ + u32 frs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_timeout_value : 4; /* [3:0] */ + u32 cpl_timeout_dis : 1; /* [4] */ + u32 ari_fwd_en : 1; /* [5] */ + u32 atomicop_req_en : 1; /* [6] */ + u32 atomicop_egress_blk : 1; /* [7] */ + u32 ido_req_en : 1; /* [8] */ + u32 ido_cpl_en : 1; /* [9] */ + u32 ltr_mech_en : 1; /* [10] */ + u32 emergency_pwr_reduce_req : 1; /* [11] */ + u32 en_10bit_req_tag : 1; /* [12] */ + u32 obff_en : 2; /* [14:13] */ + u32 end_end_pfx_blk : 1; /* [15] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 1; /* [0] */ + u32 link_speed_sup : 7; /* [7:1] */ + u32 cross_link_sup : 1; /* [8] */ + u32 cfg_tx_lower_skp_cap : 7; /* [15:9] */ + u32 cfg_rx_lower_skp_cap : 7; /* [22:16] */ + u32 retimer_presence_detect_sup : 1; /* [23] */ + u32 retimer2_presence_detect_sup : 1; /* [24] */ + u32 rsv_25 : 6; /* [30:25] */ + u32 drs_sup : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 target_link_speed : 4; /* [3:0] */ + u32 enter_compliance : 1; /* [4] */ + u32 hw_auto_speed_dis : 1; /* [5] */ + u32 selectable_de_emphasis : 1; /* [6] */ + u32 transmit_margin : 3; /* [9:7] */ + u32 enter_mod_compliance : 1; /* [10] */ + u32 compliance_sos : 1; /* [11] */ + u32 compliance_preset_deemp : 4; /* [15:12] */ + u32 cur_deemp_level : 1; /* [16] */ + u32 eq_8g_complete : 1; /* [17] */ + u32 eq_8g_phase1_success : 1; /* [18] */ + u32 eq_8g_phase2_success : 1; /* [19] */ + u32 eq_8g_phase3_success : 1; /* [20] */ + u32 link_8g_eq_req : 1; /* [21] */ + u32 retimer_presence_detect : 1; /* [22] */ + u32 retimer2_presence_detect : 1; /* [23] */ + u32 crosslink_resolution : 2; /* [25:24] */ + u32 rsv_26 : 2; /* [27:26] */ + u32 downstream_component_presence : 3; /* [30:28] */ + u32 drs_msg_recved : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_27 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_28 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msi_pending_u; + +/* Define the union csr_vpd_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_cap_id : 8; /* [7:0] */ + u32 vpd_next_cap_addr : 8; /* [15:8] */ + u32 vpd_addr : 15; /* [30:16] */ + u32 vpd_flag : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vpd_cap_header_u; + +/* Define the union csr_vpd_cap_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vpd_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vpd_cap_data_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_29 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_msix_pba_ctrl_u; + +/* Define the union csr_pme_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pme_capability_id : 8; /* [7:0] */ + u32 pme_next_ptr : 8; /* [15:8] */ + u32 pme_vesion : 3; /* [18:16] */ + u32 pme_clk : 1; /* [19] */ + u32 immediate_rn_return_d0 : 1; /* [20] */ + u32 device_spec_ini : 1; /* [21] */ + u32 aux_current : 3; /* [24:22] */ + u32 d1_support : 1; /* [25] */ + u32 d2_support : 1; /* [26] */ + u32 pme_support : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pme_cap_header_u; + +/* Define the union csr_pme_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwr_status : 2; /* [1:0] */ + u32 rsv_30 : 1; /* [2] */ + u32 no_soft_reset : 1; /* [3] */ + u32 rsv_31 : 4; /* [7:4] */ + u32 pme_en : 1; /* [8] */ + u32 data_sel : 4; /* [12:9] */ + u32 data_scale : 2; /* [14:13] */ + u32 pme_status : 1; /* [15] */ + u32 rsv_32 : 6; /* [21:16] */ + u32 b2_b3_n : 1; /* [22] */ + u32 bpcc_en : 1; /* [23] */ + u32 pme_data : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pme_status_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_33 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_37 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_39 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_41 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_42 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_43 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_44 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_45 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_47 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_48 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_49 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_50 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_51 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_mask : 1; /* [0] */ + u32 rsv_53 : 5; /* [5:1] */ + u32 bad_tlp_mask : 1; /* [6] */ + u32 bad_dllp_mask : 1; /* [7] */ + u32 reply_num_rollover_mask : 1; /* [8] */ + u32 rsv_54 : 3; /* [11:9] */ + u32 reply_timer_timout_mask : 1; /* [12] */ + u32 advisory_non_fatal_err_mask : 1; /* [13] */ + u32 cor_int_err_mask : 1; /* [14] */ + u32 header_log_overflow_mask : 1; /* [15] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_err_ptr : 5; /* [4:0] */ + u32 ecrc_gen_cap : 1; /* [5] */ + u32 ecrc_gen_en : 1; /* [6] */ + u32 ecrc_check_cap : 1; /* [7] */ + u32 ecrc_check_en : 1; /* [8] */ + u32 multi_hdr_rec_cap : 1; /* [9] */ + u32 multi_hdr_rec_enable : 1; /* [10] */ + u32 tlp_prefix_log_pre : 1; /* [11] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_56 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_four_header_log_u; + +/* Define the union csr_root_error_command_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_en : 1; /* [0] */ + u32 non_fatal_err_en : 1; /* [1] */ + u32 fatal_err_en : 1; /* [2] */ + u32 rsv_57 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_root_error_command_u; + +/* Define the union csr_root_error_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_err_rcv : 1; /* [0] */ + u32 multi_cor_err_rcv : 1; /* [1] */ + u32 uncor_err_rcv : 1; /* [2] */ + u32 multi_uncor_err_rcv : 1; /* [3] */ + u32 first_uncor_err : 1; /* [4] */ + u32 non_fatal_msg_rcv : 1; /* [5] */ + u32 fatal_msg_rcv : 1; /* [6] */ + u32 rsv_58 : 20; /* [26:7] */ + u32 aer_int_number : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_root_error_status_u; + +/* Define the union csr_err_source_iden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_cor_source : 16; /* [15:0] */ + u32 err_non_cir_source : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_err_source_iden_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_first_prefix_log_u; + +/* Define the union csr_second_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_second_prefix_log_u; + +/* Define the union csr_third_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_third_prefix_log_u; + +/* Define the union csr_four_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_four_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_59 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_60 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_ari_ctrl_u; + +/* Define the union csr_sriov_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sriovcapabilityid : 16; /* [15:0] */ + u32 sriovcapabilityversion : 4; /* [19:16] */ + u32 sriov_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_sriov_cap_header_u; + +/* Define the union csr_sriov_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_cap : 1; /* [0] */ + u32 ari_cap_hier_pres : 1; /* [1] */ + u32 vf_10bit_tag_sup : 1; /* [2] */ + u32 rsv_62 : 18; /* [20:3] */ + u32 vf_mig_int : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_sriov_cap_u; + +/* Define the union csr_sriov_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 1; /* [0] */ + u32 vf_mig_en : 1; /* [1] */ + u32 vf_mig_int_en : 1; /* [2] */ + u32 vf_mse : 1; /* [3] */ + u32 ari_cap_hier : 1; /* [4] */ + u32 vf_10bit_tag_en : 1; /* [5] */ + u32 rsv_63 : 10; /* [15:6] */ + u32 vf_mig_status : 1; /* [16] */ + u32 rsv_64 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_sriov_ctrl_u; + +/* Define the union csr_init_vf_number_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 initial_vf : 16; /* [15:0] */ + u32 totl_vfs : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_init_vf_number_u; + +/* Define the union csr_func_dep_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_of_vf : 16; /* [15:0] */ + u32 func_depen_link : 8; /* [23:16] */ + u32 rsv_65 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_func_dep_vf_num_u; + +/* Define the union csr_vf_rid_setting_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_offset : 16; /* [15:0] */ + u32 vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_rid_setting_u; + +/* Define the union csr_vf_device_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_66 : 16; /* [15:0] */ + u32 vf_device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_device_id_u; + +/* Define the union csr_vf_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 support_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_page_size_u; + +/* Define the union csr_system_page_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sys_page_size : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_system_page_size_u; + +/* Define the union csr_vf_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar0_reserved : 2; /* [1:0] */ + u32 vf_bar0_width : 1; /* [2] */ + u32 vf_bar0_prefetch_en : 1; /* [3] */ + u32 vf_bar0_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_bar0_u; + +/* Define the union csr_vf_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar1_reserved : 3; /* [2:0] */ + u32 vf_bar1_prefetch_en : 1; /* [3] */ + u32 vf_bar1_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_bar1_u; + +/* Define the union csr_vf_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar2_reserved : 2; /* [1:0] */ + u32 vf_bar2_width : 1; /* [2] */ + u32 vf_bar2_prefetch_en : 1; /* [3] */ + u32 vf_bar2_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_bar2_u; + +/* Define the union csr_vf_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar3_reserved : 3; /* [2:0] */ + u32 vf_bar3_prefetch_en : 1; /* [3] */ + u32 vf_bar3_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_bar3_u; + +/* Define the union csr_vf_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar4_reserved : 2; /* [1:0] */ + u32 vf_bar4_width : 1; /* [2] */ + u32 vf_bar4_prefetch_en : 1; /* [3] */ + u32 vf_bar4_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_bar4_u; + +/* Define the union csr_vf_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_bar5_reserved : 3; /* [2:0] */ + u32 vf_bar5_prefetch_en : 1; /* [3] */ + u32 vf_bar5_addr : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_bar5_u; + +/* Define the union csr_vf_mig_state_array_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_mig_state_bit : 3; /* [2:0] */ + u32 vf_mig_state_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_vf_mig_state_array_u; + +/* Define the union csr_ats_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atscapabilityid : 16; /* [15:0] */ + u32 atscapabilityversion : 4; /* [19:16] */ + u32 ats_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_ats_cap_header_u; + +/* Define the union csr_ats_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 invalid_q_depth : 5; /* [4:0] */ + u32 page_aligned_request : 1; /* [5] */ + u32 global_invalidate_sup : 1; /* [6] */ + u32 rsv_67 : 9; /* [15:7] */ + u32 stu : 5; /* [20:16] */ + u32 rsv_68 : 10; /* [30:21] */ + u32 ats_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_ats_cap_ctrl_u; + +/* Define the union csr_pr_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_cap_id : 16; /* [15:0] */ + u32 pr_cap_version : 4; /* [19:16] */ + u32 pr_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pr_cap_header_u; + +/* Define the union csr_pr_cap_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_req_en : 1; /* [0] */ + u32 pr_req_rst : 1; /* [1] */ + u32 rsv_69 : 14; /* [15:2] */ + u32 pr_resp_fail : 1; /* [16] */ + u32 pr_uprgi_rcv : 1; /* [17] */ + u32 rsv_70 : 6; /* [23:18] */ + u32 pr_stopped : 1; /* [24] */ + u32 rsv_71 : 6; /* [30:25] */ + u32 pr_res_pasid_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pr_cap_ctrl_status_u; + +/* Define the union csr_pr_out_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_cap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pr_out_req_cap_u; + +/* Define the union csr_pr_out_req_alc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pr_outstand_req_alc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pr_out_req_alc_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_72 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_73 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_75 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_76 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_tph_req_ctrl_u; + +/* Define the union csr_pasid_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pasid_cap_id : 16; /* [15:0] */ + u32 pasid_cap_version : 4; /* [19:16] */ + u32 pasid_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pasid_cap_header_u; + +/* Define the union csr_pasid_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_77 : 1; /* [0] */ + u32 execute_perm_support : 1; /* [1] */ + u32 privlgd_mode_support : 1; /* [2] */ + u32 rsv_78 : 5; /* [7:3] */ + u32 max_pasid_width : 5; /* [12:8] */ + u32 rsv_79 : 3; /* [15:13] */ + u32 pasid_en : 1; /* [16] */ + u32 execute_perm_en : 1; /* [17] */ + u32 privlgd_mode_en : 1; /* [18] */ + u32 rsv_80 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_pasid_cap_ctrl_u; + +/* Define the union csr_device_serial_number_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_extend_cap : 16; /* [15:0] */ + u32 dsn_cap_version : 4; /* [19:16] */ + u32 dsn_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_device_serial_number_cap_header_u; + +/* Define the union csr_serial_lnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_1st_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_serial_lnum_u; + +/* Define the union csr_serial_hnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dsn_2nd_dw : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_serial_hnum_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dummy_cap_0x1c_u; + +/* Define the union csr_acs_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_capid : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_acs_cap_0x00_u; + +/* Define the union csr_acs_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_81 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_82 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_acs_cap_0x04_u; + +/* Define the union csr_dl_feature_cap_reg00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dl_feature_capid : 16; /* [15:0] */ + u32 dl_feature_cap_version : 4; /* [19:16] */ + u32 dl_feature_cap_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dl_feature_cap_reg00_u; + +/* Define the union csr_dl_feature_cap_reg04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 local_scale_fc_support : 1; /* [0] */ + u32 local_future_feature_support : 22; /* [22:1] */ + u32 rsv_83 : 8; /* [30:23] */ + u32 feature_exchange_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dl_feature_cap_reg04_u; + +/* Define the union csr_dl_feature_cap_reg08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 remote_scale_fc_support : 1; /* [0] */ + u32 remote_future_feature_support : 22; /* [22:1] */ + u32 rsv_84 : 8; /* [30:23] */ + u32 remote_feature_sup_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_epfn_cfgspace_7_dl_feature_cap_reg08_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_0_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_1_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_2_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_3_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_4_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_5_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_6_acs_capability_u; + +/* Define the union csr_pcihdr_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vendor_id : 16; /* [15:0] */ + u32 device_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_id_u; + +/* Define the union csr_pcihdr_cmdsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_io_space_en : 1; /* [0] */ + u32 cfg_mem_space_en : 1; /* [1] */ + u32 cfg_master_en : 1; /* [2] */ + u32 cfg_special_cycle_en : 1; /* [3] */ + u32 cfg_mem_wr_invld_en : 1; /* [4] */ + u32 cfg_vga_snoop_en : 1; /* [5] */ + u32 cfg_parity_err_resp : 1; /* [6] */ + u32 idsel_stepping : 1; /* [7] */ + u32 cfg_serr_en : 1; /* [8] */ + u32 cfg_fast_b2b_en : 1; /* [9] */ + u32 cfg_intx_disable : 1; /* [10] */ + u32 rsv_0 : 8; /* [18:11] */ + u32 cfg_intx_status : 1; /* [19] */ + u32 cfg_cap_list : 1; /* [20] */ + u32 cfg_66mhz_cap : 1; /* [21] */ + u32 rsv_1 : 1; /* [22] */ + u32 cfg_fastb2b_cap : 1; /* [23] */ + u32 cfg_mdata_par_err : 1; /* [24] */ + u32 cfg_devsel_timing : 2; /* [26:25] */ + u32 cfg_sig_target_abort : 1; /* [27] */ + u32 cfg_rx_target_abort : 1; /* [28] */ + u32 cfg_rx_master_abort : 1; /* [29] */ + u32 cfg_rx_sys_err : 1; /* [30] */ + u32 cfg_delete_par_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_cmdsts_u; + +/* Define the union csr_pcihdr_clsrev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 revision_id : 8; /* [7:0] */ + u32 program_inf : 8; /* [15:8] */ + u32 sub_class_code : 8; /* [23:16] */ + u32 base_class_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_clsrev_u; + +/* Define the union csr_pcihdr_misc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 23; /* [22:0] */ + u32 multi_func_idt : 1; /* [23] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_misc_u; + +/* Define the union csr_pcihdr_bar0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar0_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_bar0_u; + +/* Define the union csr_pcihdr_bar1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar1_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_bar1_u; + +/* Define the union csr_pcihdr_bar2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar2_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_bar2_u; + +/* Define the union csr_pcihdr_bar3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar3_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_bar3_u; + +/* Define the union csr_pcihdr_bar4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_bar4_u; + +/* Define the union csr_pcihdr_bar5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_bar5_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_bar5_u; + +/* Define the union csr_pcihdr_cbus_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 carbus_cis_ptr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_cbus_ptr_u; + +/* Define the union csr_pcihdr_subsys_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sys_vendor_id : 16; /* [15:0] */ + u32 cfg_sub_sys_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_subsys_u; + +/* Define the union csr_pcihdr_exprom_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ext_rom_base_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_exprom_u; + +/* Define the union csr_pcihdr_capptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cap_ptr : 8; /* [7:0] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_capptr_u; + +/* Define the union csr_pci_rsvd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pci_rsvd_u; + +/* Define the union csr_pcihdr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_lat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcihdr_int_u; + +/* Define the union csr_pcie_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pci_capid : 8; /* [7:0] */ + u32 pcie_next_cap_addr : 8; /* [15:8] */ + u32 pci_cap_ver : 4; /* [19:16] */ + u32 port_type : 4; /* [23:20] */ + u32 slot_implement : 1; /* [24] */ + u32 int_msg_num : 5; /* [29:25] */ + u32 undefine_00 : 1; /* [30] */ + u32 rsv_6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_pcie_cap_header_u; + +/* Define the union csr_device_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_payload_size_support : 3; /* [2:0] */ + u32 phanotom_fun_sup : 2; /* [4:3] */ + u32 ext_tag_sup : 1; /* [5] */ + u32 ep_l0s_accept_lat : 3; /* [8:6] */ + u32 ep_l1_accept_lat : 3; /* [11:9] */ + u32 undefine_04 : 3; /* [14:12] */ + u32 ro_base_err_rpt : 1; /* [15] */ + u32 rsv_7 : 2; /* [17:16] */ + u32 cap_slot_pwr_limit_val : 8; /* [25:18] */ + u32 cap_slot_pwr_sca : 2; /* [27:26] */ + u32 flr_cap : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_device_capbility_u; + +/* Define the union csr_device_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cor_err_rpt_en : 1; /* [0] */ + u32 non_fat_rpt_en : 1; /* [1] */ + u32 fat_err_rpt_en : 1; /* [2] */ + u32 ur_rpt_en : 1; /* [3] */ + u32 relax_order_en : 1; /* [4] */ + u32 max_payload_size : 3; /* [7:5] */ + u32 extend_tag_en : 1; /* [8] */ + u32 phatom_func_en : 1; /* [9] */ + u32 aux_pwr_pm_en : 1; /* [10] */ + u32 no_snoop_en : 1; /* [11] */ + u32 max_read_req_size : 3; /* [14:12] */ + u32 init_flr_reset : 1; /* [15] */ + u32 cor_err_detect : 1; /* [16] */ + u32 non_fata_detect : 1; /* [17] */ + u32 fat_err_detect : 1; /* [18] */ + u32 ur_detect : 1; /* [19] */ + u32 aux_pwr_detect : 1; /* [20] */ + u32 tlp_pending : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_device_ctrl_status_u; + +/* Define the union csr_link_capbility_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_link_speed : 4; /* [3:0] */ + u32 max_link_width : 6; /* [9:4] */ + u32 aspm_sup : 2; /* [11:10] */ + u32 l0_exit_lat : 3; /* [14:12] */ + u32 l1_exit_lat : 3; /* [17:15] */ + u32 clock_pm : 1; /* [18] */ + u32 surprise_dn_err_rpt_cap : 1; /* [19] */ + u32 dl_link_act_rpt_cap : 1; /* [20] */ + u32 link_band_notice_cap : 1; /* [21] */ + u32 aspm_opt_compliance : 1; /* [22] */ + u32 rsv_10 : 1; /* [23] */ + u32 port_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_link_capbility_u; + +/* Define the union csr_link_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_status_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_link_ctrl_status_u; + +/* Define the union csr_slot_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 physical_slot_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_slot_capability_u; + +/* Define the union csr_slot_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_slot_ctrl_status_u; + +/* Define the union csr_root_ctrl_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_root_ctrl_status_u; + +/* Define the union csr_root_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_root_status_u; + +/* Define the union csr_device_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap2_1 : 12; /* [11:0] */ + u32 tph_cpl_sup_r : 2; /* [13:12] */ + u32 device_cap2_2 : 3; /* [16:14] */ + u32 tag_10bit_req_sup : 1; /* [17] */ + u32 device_cap2_3 : 13; /* [30:18] */ + u32 frs : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_device_capability2_u; + +/* Define the union csr_device_ctrl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_ctrl2_28 : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_device_ctrl2_u; + +/* Define the union csr_link_capability2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_lower_skp_cap : 31; /* [30:0] */ + u32 rsv_15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_link_capability2_u; + +/* Define the union csr_link_ctrl_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_link_ctrl_status2_u; + +/* Define the union csr_slot_cap_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_cap_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_slot_cap_2_u; + +/* Define the union csr_slot_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slot_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_slot_ctrl_2_u; + +/* Define the union csr_msi_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_cap_id : 8; /* [7:0] */ + u32 msi_next_cap_addr : 8; /* [15:8] */ + u32 msi_enable : 1; /* [16] */ + u32 msi_mult_msg_cap : 3; /* [19:17] */ + u32 msi_mult_msg_enable : 3; /* [22:20] */ + u32 msi_64bit_enable : 1; /* [23] */ + u32 msi_pvm_enable : 1; /* [24] */ + u32 msi_ext_data_capable : 1; /* [25] */ + u32 msi_ext_data_enable : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msi_cap_header_u; + +/* Define the union csr_msi_laddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 2; /* [1:0] */ + u32 msi_laddr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msi_laddr_u; + +/* Define the union csr_msi_haddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_uaddr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msi_haddr_u; + +/* Define the union csr_msi_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data : 16; /* [15:0] */ + u32 msi_ext_data : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msi_data_u; + +/* Define the union csr_msi_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msi_mask_u; + +/* Define the union csr_msi_pending_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_pending : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msi_pending_u; + +/* Define the union csr_msix_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_cap_id : 8; /* [7:0] */ + u32 msix_next_cap_addr : 8; /* [15:8] */ + u32 msix_table_size : 11; /* [26:16] */ + u32 rsv_19 : 3; /* [29:27] */ + u32 msix_func_mask : 1; /* [30] */ + u32 msix_enable : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msix_cap_header_u; + +/* Define the union csr_msix_table_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_table_bir : 3; /* [2:0] */ + u32 msix_table_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msix_table_ctrl_u; + +/* Define the union csr_msix_pba_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_pba_bir : 3; /* [2:0] */ + u32 msix_pba_offset : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_msix_pba_ctrl_u; + +/* Define the union csr_virtio_common_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_cap_vndr : 8; /* [7:0] */ + u32 common_cap_next : 8; /* [15:8] */ + u32 common_cap_len : 8; /* [23:16] */ + u32 common_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_common_header_u; + +/* Define the union csr_virtio_common_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_bar : 3; /* [2:0] */ + u32 rsv_20 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_common_bar_u; + +/* Define the union csr_virtio_common_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_common_offset_u; + +/* Define the union csr_virtio_common_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 common_length : 8; /* [7:0] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_common_length_u; + +/* Define the union csr_virtio_notify_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_cap_vndr : 8; /* [7:0] */ + u32 notify_cap_next : 8; /* [15:8] */ + u32 notify_cap_len : 8; /* [23:16] */ + u32 notify_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_notify_header_u; + +/* Define the union csr_virtio_notify_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_bar : 3; /* [2:0] */ + u32 rsv_22 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_notify_bar_u; + +/* Define the union csr_virtio_notify_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_notify_offset_u; + +/* Define the union csr_virtio_notify_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_length : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_notify_length_u; + +/* Define the union csr_virtio_notify_off_multiplier_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 notify_off_multiplier : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_notify_off_multiplier_u; + +/* Define the union csr_virtio_isr_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_cap_vndr : 8; /* [7:0] */ + u32 isr_cap_next : 8; /* [15:8] */ + u32 isr_cap_len : 8; /* [23:16] */ + u32 isr_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_isr_header_u; + +/* Define the union csr_virtio_isr_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_bar : 3; /* [2:0] */ + u32 rsv_24 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_isr_bar_u; + +/* Define the union csr_virtio_isr_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_isr_offset_u; + +/* Define the union csr_virtio_isr_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 isr_length : 8; /* [7:0] */ + u32 rsv_25 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_isr_length_u; + +/* Define the union csr_virtio_device_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_cap_vndr : 8; /* [7:0] */ + u32 device_cap_next : 8; /* [15:8] */ + u32 device_cap_len : 8; /* [23:16] */ + u32 device_cfg_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_device_header_u; + +/* Define the union csr_virtio_device_bar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_bar : 3; /* [2:0] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_device_bar_u; + +/* Define the union csr_virtio_device_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_device_offset_u; + +/* Define the union csr_virtio_device_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 device_length : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_virtio_device_length_u; + +/* Define the union csr_aer_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aercapabilityid : 16; /* [15:0] */ + u32 aercapabilityversion : 4; /* [19:16] */ + u32 aer_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_aer_cap_header_u; + +/* Define the union csr_uncr_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_4 : 1; /* [0] */ + u32 rsv_28 : 3; /* [3:1] */ + u32 dl_protocal_err_st : 1; /* [4] */ + u32 sur_down_err_st : 1; /* [5] */ + u32 rsv_29 : 6; /* [11:6] */ + u32 poisoned_tlp_st : 1; /* [12] */ + u32 fc_protocol_err_st : 1; /* [13] */ + u32 cpl_timeeout_st : 1; /* [14] */ + u32 cpl_abort_st : 1; /* [15] */ + u32 unexp_cpl_st : 1; /* [16] */ + u32 rcv_overflow_st : 1; /* [17] */ + u32 mal_tlp_st : 1; /* [18] */ + u32 ecrc_err_st : 1; /* [19] */ + u32 ur_err_st : 1; /* [20] */ + u32 acs_vio_st : 1; /* [21] */ + u32 uncor_int_err_st : 1; /* [22] */ + u32 mc_blk_st : 1; /* [23] */ + u32 atomicop_eg_blk_st : 1; /* [24] */ + u32 tlp_pfx_blk_err_st : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_st : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_uncr_err_status_u; + +/* Define the union csr_uncr_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_8 : 1; /* [0] */ + u32 rsv_31 : 3; /* [3:1] */ + u32 dl_protocal_err_mask : 1; /* [4] */ + u32 sur_down_err_mask : 1; /* [5] */ + u32 rsv_32 : 6; /* [11:6] */ + u32 poisoned_tlp_mask : 1; /* [12] */ + u32 fc_protocol_err_mask : 1; /* [13] */ + u32 cpl_timeeout_mask : 1; /* [14] */ + u32 cpl_abort_mask : 1; /* [15] */ + u32 unexp_cpl_mask : 1; /* [16] */ + u32 rcv_overflow_mask : 1; /* [17] */ + u32 mal_tlp_mask : 1; /* [18] */ + u32 ecrc_err_mask : 1; /* [19] */ + u32 ur_err_mask : 1; /* [20] */ + u32 acs_vio_mask : 1; /* [21] */ + u32 uncor_int_err_mask : 1; /* [22] */ + u32 mc_blk_mask : 1; /* [23] */ + u32 atomicop_eg_blk_mask : 1; /* [24] */ + u32 tlp_pfx_blk_err_mask : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_mask : 1; /* [26] */ + u32 rsv_33 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_uncr_err_mask_u; + +/* Define the union csr_uncr_err_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 undefined_c : 1; /* [0] */ + u32 rsv_34 : 3; /* [3:1] */ + u32 dl_protocal_err_ser : 1; /* [4] */ + u32 sur_down_err_ser : 1; /* [5] */ + u32 rsv_35 : 6; /* [11:6] */ + u32 poisoned_tlp_ser : 1; /* [12] */ + u32 fc_protocol_err_ser : 1; /* [13] */ + u32 cpl_timeeout_ser : 1; /* [14] */ + u32 cpl_abort_ser : 1; /* [15] */ + u32 unexp_cpl_ser : 1; /* [16] */ + u32 rcv_overflow_ser : 1; /* [17] */ + u32 mal_tlp_ser : 1; /* [18] */ + u32 ecrc_err_ser : 1; /* [19] */ + u32 ur_err_ser : 1; /* [20] */ + u32 acs_vio_ser : 1; /* [21] */ + u32 uncor_int_err_ser : 1; /* [22] */ + u32 mc_blk_ser : 1; /* [23] */ + u32 atomicop_eg_blk_ser : 1; /* [24] */ + u32 tlp_pfx_blk_err_ser : 1; /* [25] */ + u32 poisoned_tlp_egress_blk_err_ser : 1; /* [26] */ + u32 rsv_36 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_uncr_err_severity_u; + +/* Define the union csr_cor_err_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_err_st : 1; /* [0] */ + u32 rsv_37 : 5; /* [5:1] */ + u32 bad_tlp_st : 1; /* [6] */ + u32 bad_dllp_st : 1; /* [7] */ + u32 reply_num_rollover_st : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 reply_timer_timout_st : 1; /* [12] */ + u32 advisory_non_fatal_err_st : 1; /* [13] */ + u32 cor_int_err_st : 1; /* [14] */ + u32 header_log_overflow_st : 1; /* [15] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_cor_err_status_u; + +/* Define the union csr_cor_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_40 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_cor_err_mask_u; + +/* Define the union csr_advacd_cap_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_uncor_err_ptr : 5; /* [4:0] */ + u32 rsv_41 : 7; /* [11:5] */ + u32 cmp_timeout_log_cap : 1; /* [12] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_advacd_cap_ctrl_u; + +/* Define the union csr_first_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_first_header_log_u; + +/* Define the union csr_second_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 second_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_second_header_log_u; + +/* Define the union csr_third_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 third_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_third_header_log_u; + +/* Define the union csr_four_header_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 four_header_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_four_header_log_u; + +/* Define the union csr_first_prefix_log_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 first_prefix_log : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_first_prefix_log_u; + +/* Define the union csr_ari_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aricapabilityid : 16; /* [15:0] */ + u32 aricapabilityversion : 4; /* [19:16] */ + u32 ari_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_ari_cap_header_u; + +/* Define the union csr_ari_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mfvc_func_grp_cap : 1; /* [0] */ + u32 acs_func_grp_cap : 1; /* [1] */ + u32 rsv_43 : 6; /* [7:2] */ + u32 next_func_num : 8; /* [15:8] */ + u32 mfvc_func_grp_en : 1; /* [16] */ + u32 acs_func_grp_en : 1; /* [17] */ + u32 rsv_44 : 2; /* [19:18] */ + u32 func_group : 3; /* [22:20] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_ari_ctrl_u; + +/* Define the union csr_tph_extend_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tph_extend_cap_id : 16; /* [15:0] */ + u32 tph_cap_version : 4; /* [19:16] */ + u32 tph_next_cap_offset : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_tph_extend_cap_u; + +/* Define the union csr_tph_req_cap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 no_st_mode_support : 1; /* [0] */ + u32 int_vector_mode_support : 1; /* [1] */ + u32 device_spc_mode_support : 1; /* [2] */ + u32 rsv_46 : 5; /* [7:3] */ + u32 extend_tph_req_support : 1; /* [8] */ + u32 st_table_location : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 st_table_size : 11; /* [26:16] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_tph_req_cap_u; + +/* Define the union csr_tph_req_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 st_mode_sel : 3; /* [2:0] */ + u32 rsv_49 : 5; /* [7:3] */ + u32 tph_req_enable : 2; /* [9:8] */ + u32 rsv_50 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_tph_req_ctrl_u; + +/* Define the union csr_dummy_cap_0x00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x00_u; + +/* Define the union csr_dummy_cap_0x04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x04_u; + +/* Define the union csr_dummy_cap_0x08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x08_u; + +/* Define the union csr_dummy_cap_0x0c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x0c_u; + +/* Define the union csr_dummy_cap_0x10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x10_u; + +/* Define the union csr_dummy_cap_0x14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x14_u; + +/* Define the union csr_dummy_cap_0x18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x18_u; + +/* Define the union csr_dummy_cap_0x1c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 extend_capability_dw7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_dummy_cap_0x1c_u; + +/* Define the union csr_acs_ext_cap_header_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_ext_cap_id : 16; /* [15:0] */ + u32 acs_cap_version : 4; /* [19:16] */ + u32 acs_next_cap_addr : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_acs_ext_cap_header_u; + +/* Define the union csr_acs_capability_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acs_src_vld : 1; /* [0] */ + u32 acs_tx_block : 1; /* [1] */ + u32 acs_p2p_req_redirect : 1; /* [2] */ + u32 acs_p2p_cpl_redirect : 1; /* [3] */ + u32 acs_up_forward : 1; /* [4] */ + u32 acs_p2p_egress_ctrl : 1; /* [5] */ + u32 acs_direct_tx_p2p : 1; /* [6] */ + u32 rsv_51 : 1; /* [7] */ + u32 acs_ctrl_vec_size : 8; /* [15:8] */ + u32 acs_src_vld_en : 1; /* [16] */ + u32 acs_tx_block_en : 1; /* [17] */ + u32 acs_p2p_req_redirect_en : 1; /* [18] */ + u32 acs_p2p_cpl_redirect_en : 1; /* [19] */ + u32 acs_up_forward_en : 1; /* [20] */ + u32 acs_p2p_egress_ctrl_en : 1; /* [21] */ + u32 acs_direct_tx_p2p_en : 1; /* [22] */ + u32 rsv_52 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec_evf_cfgspace_7_acs_capability_u; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_pcs_addr_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_pcs_addr_define.h new file mode 100644 index 000000000..aca2d4755 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_pcs_addr_define.h @@ -0,0 +1,286 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : pcie5_pcs_addr_define.h + * Project line : Platform And Key Technologies Development + * Department : CAD Development Department + * Version : 1.0 + * Date : + * Description : The description of HIPCIECTRL30V200 project + * Others : Generated automatically by nManager V5.1 + * History : 2021/01/07 09:57:53 Create file + */ + +#ifndef PCIE5_PCS_ADDR_DEFINE_H +#define PCIE5_PCS_ADDR_DEFINE_H + +/* HIPCIEC50_PCS_GLB_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_PCS_GLB_REG_BASE (0x5A000) + +/* **************************************************************************** */ +/* HIPCIEC50_PCS_GLB_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_PCS_GLB_REG_RATE_CHANGE_TIME_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x0) /* rate change time config. */ +#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHANGE_1US_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x4) /* power change time config. */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_A_LINE_ERR_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x8) /* Error inject line-A high 31bit */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_B_LINE_ERR_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xC) /* Error inject line-B high 31bit */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_C_LINE_ERR_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x10) /* Error inject line-C high 31bit */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PWR_STAY_TIME_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x18) /* power stay mini-time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_MASK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x20) /* Trace trigger mask */ +#define CSR_HIPCIEC50_PCS_GLB_REG_APB_WR_NUM_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x24) /* apb write counter */ +#define CSR_HIPCIEC50_PCS_GLB_REG_M_PCS_IN18_CFG_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x28) /* pipe selection and bist data */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x2C) /* trace0 config. */ +#define CSR_HIPCIEC50_PCS_GLB_REG_M_PCS_EQEVAL_CFG_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x30) /* power change time and eqeval enable */ +#define CSR_HIPCIEC50_PCS_GLB_REG_ELBUF_EMPTY_PARA_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x34) /* elbuf empty line */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RECDET_TIMEOUT_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x38) /* receive detect time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RECDET_INTERVAL_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C) /* receive detect interval time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RATE_TIME_OUT_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x40) /* rate change timeout time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHANGE_TIME_OUT_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x44) /* power change timeout time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_EQEVAL_TIMEOUT_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x48) /* eqeval timeout time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RX_ELECIDLE_PROTECT_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x54) /* elbuf low latency mode */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x58) /* eco register0 */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x5C) /* eco register1 */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x60) /* eco register2 */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCIE_PCS_ECO_RSV3_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x64) /* eco register3 */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PWR_CHGE_60US_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x68) /* power change time config and ske remove param */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x84) /* Trace data out */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x88) /* trace4 config. */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT8_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x8C) /* trace8 config. */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_TRACE_PORT12_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x90) /* trace12 config. */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x94) /* Trace data out */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT8_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x98) /* s */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_DATA_PORT12_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x9C) /* Trace data */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_CTRL_AND_ECC_0_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xA0) /* trace0 or 4 read enable */ +#define CSR_HIPCIEC50_PCS_GLB_REG_TRACE_CTRL_AND_ECC_1_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xA4) /* trace8 or 12 read enable */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_STATUS_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xA8) /* PCS CE interrupt source */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_SET_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xAC) /* PCS CE interrupt set */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_MSK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xB0) /* PCS CE interrupt mask */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_RO_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xB4) /* PCS CE interrupt status \ + */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RX_ELECEIDLE_PRT_NUM_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xB8) /* LOS protect cycle */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RX_RCV_EIOS_WIDTH_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0xBC) /* pcs2sds_rcv_eios width configuration */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RXVALID_PROTECNTION_PARA_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x120) /* rxvalid protect num */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INJECT_1BIT_ERROR_NUM_S_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x124) /* 1bit error insert times */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INJECT_2BIT_ERROR_NUM_S_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x128) /* 2bit error insert times */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INJECT_1CYCLE_ERROR_NUM_S_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x12C) /* 1 clock cycle error insert times */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RX_MARGIN_EN_PARA_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x130) /* rxmargin_en protect cycle */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RX_MARGIN_RDY_PARA_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x134) /* rxmargin_rdy timeout cycle */ +#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x378) /* FS average calculation */ +#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x37C) /* FS average calculation timeout */ +#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_STATUS_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x380) /* FS average calculation statue */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_STATUS_REN_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x384) /* all status read enable */ +#define CSR_HIPCIEC50_PCS_GLB_REG_RXTX_STATUS_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x388) /* rxtx_status protect time */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_VERSION_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x38C) /* PCS version */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_RELEASE_DATE_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x390) /* PCS release date */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_PORT_LINK_MODE_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x394) /* port link mode just for PCS */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_A_LINE_L_ERR_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x398) /* Error inject line-A low 23bit */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_B_LINE_L_ERR_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x39C) /* Error inject line-B low 23bit */ +#define CSR_HIPCIEC50_PCS_GLB_REG_CFG_C_LINE_L_ERR_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3A0) /* Error inject line-C low 23bit */ +#define CSR_HIPCIEC50_PCS_GLB_REG_FS_CALC_RDY_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3A4) /* serdes to pcs tx fs ready */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_RXEQ_DFX_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3A8) /* PCS to SerDes txdeemph \ + */ +#define CSR_HIPCIEC50_PCS_GLB_REG_SERDES_DFX_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3AC) /* prbs error and cs calib done */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_CE_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3B0) /* pcs interrupt type selection for ce */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_NFE_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3B4) /* pcs interrupt type selection for nfe */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_FE_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3B8) /* pcs interrupt type selection for fe */ +#define CSR_HIPCIEC50_PCS_GLB_REG_INT_TYPE_SEL_NI_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3BC) /* pcs interrupt type selection for ni */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_STATUS_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C0) /* PCS NFE interrupt source */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_SET_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C4) /* PCS NFE interrupt set */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_MSK_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3C8) /* PCS NFE interrupt mask */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NFE_RO_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3CC) /* PCS NFE interrupt status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_STATUS_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3D0) /* PCS FE interrupt source */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_SET_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3D4) /* PCS FE interrupt set */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_MSK_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3D8) /* PCS FE interrupt mask */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_FE_RO_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3DC) /* PCS FE interrupt status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_STATUS_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3E0) /* PCS NI interrupt source */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_SET_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3E4) /* PCS NI interrupt set */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_MSK_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3E8) /* PCS NI interrupt mask */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_INTR_NI_RO_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3EC) /* PCS NI interrupt status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHGE_PRT_MODE_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3F4) /* power change protect mode */ +#define CSR_HIPCIEC50_PCS_GLB_REG_POWER_CHGE_WAIT_IDLE_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3F8) /* power change wait idle */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_DPTX_FIFO_THRES_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x3FC) /* pcs cdc module tx data path fifo thres */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_LANE2MACRO_MAP_0_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x400) /* pcs lane2macro mapping */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_LANE2MACRO_MAP_1_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x404) /* pcs lane2macro mapping */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS0_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x408) /* pcs cdc module global status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS1_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x40C) /* pcs cdc module global status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS2_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x410) /* pcs cdc module global status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_STATUS3_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x414) /* pcs cdc module global status */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_GLOBAL_CFG_REG \ + (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x418) /* pcs cdc module global configure */ +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x41C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x420) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G3_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x424) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x428) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_TH_G5_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x42C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_PROC_EN_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x430) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_SKP_REQ_DLY_TH_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x434) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CDC_TX_ELE_EXIT_PROTECT_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x438) +#define CSR_HIPCIEC50_PCS_GLB_REG_RETIMER_FUNCTION_SWITCH_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x43C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PWRCHGE_PHYSTS_DLY_PARAM_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x440) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_PARA_0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x444) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_PARA_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x448) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_PARA_2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x44C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x450) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x454) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x458) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_3_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x45C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_4_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x460) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_0_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x464) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_1_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x468) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_2_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x46C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_3_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x470) +#define CSR_HIPCIEC50_PCS_GLB_REG_PMA_CMD_STS_4_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x474) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CLK_ICG_EN_0_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x478) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_CLK_ICG_EN_1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x47C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_TIMER_CFG_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x480) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_EIOS_CLR_LOCK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x484) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_P0S_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x488) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_P1_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x48C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_P2_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x490) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_RXL0S_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x494) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_MODE_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x498) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_SERIAL_INTVE_TIME_REFCLK_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x49C) +#define CSR_HIPCIEC50_PCS_GLB_REG_PCS_REFCLK_STATUS_REG (CSR_HIPCIEC50_PCS_GLB_REG_BASE + 0x4A0) + +/* HIPCIEC50_PCS_LANE_REG Base address of Module's Register */ +#define CSR_HIPCIEC50_PCS_LANE_REG_BASE (0x5B000) + +/* **************************************************************************** */ +/* HIPCIEC50_PCS_LANE_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_IN13_CFG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x0) /* PMA bypass config. */ +#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_IN14_CFG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x4) /* PMA bypass config. */ +#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_IN15_CFG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x8) /* PMA bypass config. */ +#define CSR_HIPCIEC50_PCS_LANE_REG_MUX_LOS_ALOS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0xC) /* PMA bypass config. */ +#define CSR_HIPCIEC50_PCS_LANE_REG_SDS_CFG_REG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x10) /* PIPE bypass config. */ +#define CSR_HIPCIEC50_PCS_LANE_REG_M_PCS_RPT_REG_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x14) /* rx status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_SERDES_STATUS_RPT_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x18) /* PMA status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_TIME_OUT_RPT_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x1C) /* skp add or rem status \ + */ +#define CSR_HIPCIEC50_PCS_LANE_REG_POLARITY_RXVALID_RXELECIDLE_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x20) /* PIPE bypass config. */ +#define CSR_HIPCIEC50_PCS_LANE_REG_STATUS_CLR_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x24) /* error counter clear */ +#define CSR_HIPCIEC50_PCS_LANE_REG_EBUF_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x28) /* ebuf status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_GEN3_DEC_ENC_STATUS_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x2C) /* 128B130B encode status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_WAKE_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x30) /* wake control status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RECV_DET_OR_PWR_CHAGE_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x34) /* receiver detect or power change status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_EQEVAL_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x38) /* eyediag test status \ + */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RATE_CHGE_STATUS0_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x3C) /* rate change status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x40) /* PCS lane interrupt status CE */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_SET_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x44) /* PCS lane interrupt set */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_MASK_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x48) /* PCS lane interrupt mask */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_STATUS_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x4C) /* PCS lane interrupt source */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_EBUF_PARA_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x50) /* PCS lane elbuf water line */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RX_MARGIN_STATUS_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x54) /* RXMARGIN status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RX_MARGIN_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x58) /* RXMARGIN timeout counter */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RXEQ_COARSETUNE_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x5C) /* coarsetune timeout counter */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RXEQ_FINETUNE_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x60) /* finetune timeout counter */ +#define CSR_HIPCIEC50_PCS_LANE_REG_DETECT_CLK_FLG_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x64) /* dfx tx/rxclk exist flag */ +#define CSR_HIPCIEC50_PCS_LANE_REG_MSG_BUS_DFX_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x68) /* message bus fsm state \ + */ +#define CSR_HIPCIEC50_PCS_LANE_REG_RXEQ_START_CTRL_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x6C) /* PCS to SERDES rxeq control */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_NFE_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x70) /* PCS lane interrupt status NFE */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_FE_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x74) /* PCS lane interrupt status FE */ +#define CSR_HIPCIEC50_PCS_LANE_REG_LANE_INTR_RO_NI_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x78) /* PCS lane interrupt status NI */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PHY2MAC_MSG_STATUS_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x7C) /* phy2mac message bus status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_MSG_PIN_EN_REG (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x800) /* message bus status \ + */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_MSG_TIME_PROTECT_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x804) /* message bus timeout para */ +#define CSR_HIPCIEC50_PCS_LANE_REG_TXBEACON_RXL0S_TIMEOUT_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x808) /* rxl0s and txbeacon timeout para */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_MISC_CTRL_PARA_0_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x80C) /* misc ctrl signal */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_BEACON_RXL0S_STATUS_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x810) /* beacon and rxl0s status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS0_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x814) /* pcs cdc module lane status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS1_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x818) /* pcs cdc module lane status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS2_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x81C) /* pcs cdc module lane status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_CDC_LANE_STATUS3_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x820) /* pcs cdc module lane status */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_RXTX_STATUS_IN_LOW_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x824) /* rxtx-status stay in low time */ +#define CSR_HIPCIEC50_PCS_LANE_REG_PCS_PWRCHGE_CNT_REG \ + (CSR_HIPCIEC50_PCS_LANE_REG_BASE + 0x828) /* the time of power change in PIPE */ + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_pcs_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_pcs_typedef.h new file mode 100644 index 000000000..eefe84541 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/pcie/pcie5_pcs_typedef.h @@ -0,0 +1,11995 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : pcie5_pcs_typedef.h + * Project line : Platform And Key Technologies Development + * Department : CAD Development Department + * Version : 1.0 + * Date : + * Description : The description of HIPCIECTRL30V200 project + * Others : Generated automatically by nManager V5.1 + * History : 2021/01/07 09:57:53 Create file + */ + +#ifndef PCIE5_PCS_TYPEDEF_H +#define PCIE5_PCS_TYPEDEF_H + +/* Define the union csr_rate_change_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 5; /* [4:0] */ + u32 cfg_rate_out_time : 5; /* [9:5] */ + u32 rsv_1 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rate_change_time_u; + +/* Define the union csr_power_change_1us_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_1us : 22; /* [21:0] */ + u32 cfg_txdetrx_loopbk : 1; /* [22] */ + u32 cfg_txdetrx_loopbk_en : 1; /* [23] */ + u32 cfg_txelecidle_dly_num : 4; /* [27:24] */ + u32 cfg_sigdet_rst_rx_msk : 1; /* [28] */ + u32 cfg_ebuf_rst_rx_en : 1; /* [29] */ + u32 cfg_blkaln_lpbk_slv_msk : 1; /* [30] */ + u32 cfg_update_fs_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_power_change_1us_u; + +/* Define the union csr_cfg_a_line_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_a_line : 31; /* [30:0] */ + u32 rsv_2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_a_line_err_u; + +/* Define the union csr_cfg_b_line_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_b_line : 31; /* [30:0] */ + u32 rsv_3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_b_line_err_u; + +/* Define the union csr_cfg_c_line_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_c_line : 31; /* [30:0] */ + u32 rsv_4 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_c_line_err_u; + +/* Define the union csr_pwr_stay_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_min_time : 8; /* [7:0] */ + u32 cfg_g12_dec_err_relock_num : 12; /* [19:8] */ + u32 cfg_g12_dec_err_relock_en : 1; /* [20] */ + u32 rsv_5 : 4; /* [24:21] */ + u32 rsv_6 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pwr_stay_time_u; + +/* Define the union csr_trace_data_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_trace_data_mask : 22; /* [21:0] */ + u32 rsv_7 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_mask_u; + +/* Define the union csr_apb_wr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apb_wr_times : 10; /* [9:0] */ + u32 rsv_8 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_apb_wr_num_u; + +/* Define the union csr_m_pcs_in18_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_user_bist_data : 20; /* [19:0] */ + u32 cfg_sel_pipe : 1; /* [20] */ + u32 rsv_9 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_m_pcs_in18_cfg_u; + +/* Define the union csr_cfg_trace_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_trace_sel_p0 : 2; /* [1:0] */ + u32 cfg_trace_recap_p0 : 1; /* [2] */ + u32 cfg_trace_cap_mode_p0 : 1; /* [3] */ + u32 cfg_trace_raddr_p0 : 6; /* [9:4] */ + u32 rsv_10 : 2; /* [11:10] */ + u32 trace_last_waddr_p0 : 7; /* [18:12] */ + u32 rsv_11 : 1; /* [19] */ + u32 cfg_trace_en : 1; /* [20] */ + u32 rsv_12 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port0_u; + +/* Define the union csr_m_pcs_eqeval_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_eqeval_en : 1; /* [0] */ + u32 rsv_13 : 20; /* [20:1] */ + u32 cfg_p2_phystatus_time : 5; /* [25:21] */ + u32 rsv_14 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_m_pcs_eqeval_cfg_u; + +/* Define the union csr_elbuf_empty_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_force_skp_add : 1; /* [0] */ + u32 cfg_force_skp_rem : 1; /* [1] */ + u32 cfg_empty_thres : 4; /* [5:2] */ + u32 apb_last_waddr : 13; /* [18:6] */ + u32 rsv_15 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_elbuf_empty_para_u; + +/* Define the union csr_recdet_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rec_det_time : 20; /* [19:0] */ + u32 rsv_16 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_recdet_timeout_u; + +/* Define the union csr_recdet_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rec_det_interval_time : 14; /* [13:0] */ + u32 rsv_17 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_recdet_interval_u; + +/* Define the union csr_rate_time_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_datarate_chge_time : 22; /* [21:0] */ + u32 rsv_18 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rate_time_out_u; + +/* Define the union csr_power_change_time_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_1ms : 22; /* [21:0] */ + u32 rsv_19 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_power_change_time_out_u; + +/* Define the union csr_eqeval_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_eqeval_time : 20; /* [19:0] */ + u32 rsv_20 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_eqeval_timeout_u; + +/* Define the union csr_rx_elecidle_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_21 : 20; /* [19:0] */ + u32 cfg_rx_sigdet_sel : 1; /* [20] */ + u32 rsv_22 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rx_elecidle_protect_u; + +/* Define the union csr_pcie_pcs_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcie_pcs_eco_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv0_u; + +/* Define the union csr_pcie_pcs_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcie_pcs_eco_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv1_u; + +/* Define the union csr_pcie_pcs_eco_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcie_pcs_eco_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv2_u; + +/* Define the union csr_pcie_pcs_eco_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pcie_pcs_eco_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv3_u; + +/* Define the union csr_pwr_chge_60us_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_60us : 22; /* [21:0] */ + u32 rsv_23 : 2; /* [23:22] */ + u32 cfg_g3g4_skp_rem_num : 4; /* [27:24] */ + u32 rsv_24 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pwr_chge_60us_timeout_u; + +/* Define the union csr_trace_data_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_out_p0 : 31; /* [30:0] */ + u32 rsv_25 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port0_u; + +/* Define the union csr_cfg_trace_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_trace_sel_p4 : 2; /* [1:0] */ + u32 cfg_trace_recap_p4 : 1; /* [2] */ + u32 cfg_trace_cap_mode_p4 : 1; /* [3] */ + u32 cfg_trace_raddr_p4 : 6; /* [9:4] */ + u32 rsv_26 : 2; /* [11:10] */ + u32 trace_last_waddr_p4 : 7; /* [18:12] */ + u32 rsv_27 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port4_u; + +/* Define the union csr_cfg_trace_port8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_trace_sel_p8 : 2; /* [1:0] */ + u32 cfg_trace_recap_p8 : 1; /* [2] */ + u32 cfg_trace_cap_mode_p8 : 1; /* [3] */ + u32 cfg_trace_raddr_p8 : 6; /* [9:4] */ + u32 rsv_28 : 2; /* [11:10] */ + u32 trace_last_waddr_p8 : 7; /* [18:12] */ + u32 rsv_29 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port8_u; + +/* Define the union csr_cfg_trace_port12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_trace_sel_p12 : 2; /* [1:0] */ + u32 cfg_trace_recap_p12 : 1; /* [2] */ + u32 cfg_trace_cap_mode_p12 : 1; /* [3] */ + u32 cfg_trace_raddr_p12 : 6; /* [9:4] */ + u32 rsv_30 : 2; /* [11:10] */ + u32 trace_last_waddr_p12 : 7; /* [18:12] */ + u32 rsv_31 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port12_u; + +/* Define the union csr_trace_data_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_out_p4 : 31; /* [30:0] */ + u32 rsv_32 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port4_u; + +/* Define the union csr_trace_data_port8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_out_p8 : 31; /* [30:0] */ + u32 rsv_33 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port8_u; + +/* Define the union csr_trace_data_port12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trace_out_p12 : 31; /* [30:0] */ + u32 rsv_34 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port12_u; + +/* Define the union csr_trace_ctrl_and_ecc_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_35 : 28; /* [27:0] */ + u32 cfg_trace_ren_p0 : 1; /* [28] */ + u32 cfg_trace_ren_p4 : 1; /* [29] */ + u32 trace_data_ok_p0 : 1; /* [30] */ + u32 trace_data_ok_p4 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_ctrl_and_ecc_0_u; + +/* Define the union csr_trace_ctrl_and_ecc_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_36 : 28; /* [27:0] */ + u32 cfg_trace_ren_p8 : 1; /* [28] */ + u32 cfg_trace_ren_p12 : 1; /* [29] */ + u32 trace_data_ok_p8 : 1; /* [30] */ + u32 trace_data_ok_p12 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_trace_ctrl_and_ecc_1_u; + +/* Define the union csr_pcs_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_ind : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_status_u; + +/* Define the union csr_pcs_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_set : 16; /* [15:0] */ + u32 rsv_38 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_set_u; + +/* Define the union csr_pcs_intr_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_mask : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_msk_u; + +/* Define the union csr_pcs_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_ro : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ro_u; + +/* Define the union csr_rx_eleceidle_prt_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxelecidle_protect_num : 20; /* [19:0] */ + u32 rsv_41 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rx_eleceidle_prt_num_u; + +/* Define the union csr_rx_rcv_eios_width_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_rcv_eios_width : 12; /* [11:0] */ + u32 rsv_42 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rx_rcv_eios_width_u; + +/* Define the union csr_rxvalid_protecntion_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_43 : 2; /* [1:0] */ + u32 cfg_rxvalid_prt_num : 24; /* [25:2] */ + u32 rsv_44 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rxvalid_protecntion_para_u; + +/* Define the union csr_inject_1bit_error_num_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inject_1bit_err_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_inject_1bit_error_num_s_u; + +/* Define the union csr_inject_2bit_error_num_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inject_2bit_err_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_inject_2bit_error_num_s_u; + +/* Define the union csr_inject_1cycle_error_num_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inject_1cycle_err_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_inject_1cycle_error_num_s_u; + +/* Define the union csr_rx_margin_en_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxmargin_en_time : 29; /* [28:0] */ + u32 rsv_45 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rx_margin_en_para_u; + +/* Define the union csr_rx_margin_rdy_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxmargin_rdy_time : 26; /* [25:0] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rx_margin_rdy_para_u; + +/* Define the union csr_fs_calc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_47 : 1; /* [0] */ + u32 cfg_tx_fs_en : 1; /* [1] */ + u32 cfg_tx_fs : 6; /* [7:2] */ + u32 cfg_tx_fs_final_sel : 3; /* [10:8] */ + u32 rsv_48 : 1; /* [11] */ + u32 adpt_status_clr_en : 1; /* [12] */ + u32 rsv_49 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_u; + +/* Define the union csr_fs_calc_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_tx_fs_timeout : 30; /* [29:0] */ + u32 rsv_50 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_timeout_u; + +/* Define the union csr_fs_calc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_xport_status : 28; /* [27:0] */ + u32 rsv_51 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_status_u; + +/* Define the union csr_pcs_status_ren_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wake_status_ren : 1; /* [0] */ + u32 cfg_main_status_ren : 1; /* [1] */ + u32 cfg_eqeval_status_ren : 1; /* [2] */ + u32 cfg_pwr_chge_status_ren : 1; /* [3] */ + u32 cfg_recv_det_status_ren : 1; /* [4] */ + u32 cfg_rxmargin_status_ren : 1; /* [5] */ + u32 cfg_g12_dec_err_cnt_ren : 1; /* [6] */ + u32 cfg_g12_align_status_ren : 1; /* [7] */ + u32 cfg_g34_align_status_ren : 1; /* [8] */ + u32 cfg_ebuf_status_ren : 1; /* [9] */ + u32 cfg_bist_status_ren : 1; /* [10] */ + u32 cfg_g34_enc_status_ren : 1; /* [11] */ + u32 rsv_52 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_status_ren_u; + +/* Define the union csr_rxtx_status_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxtx_status_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_rxtx_status_timeout_u; + +/* Define the union csr_pcs_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_version_u; + +/* Define the union csr_pcs_release_date_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_release_date : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_release_date_u; + +/* Define the union csr_pcs_port_link_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port0_mode : 3; /* [2:0] */ + u32 rsv_53 : 1; /* [3] */ + u32 cfg_port2_mode : 3; /* [6:4] */ + u32 rsv_54 : 1; /* [7] */ + u32 cfg_port4_mode : 3; /* [10:8] */ + u32 rsv_55 : 1; /* [11] */ + u32 cfg_port6_mode : 3; /* [14:12] */ + u32 rsv_56 : 1; /* [15] */ + u32 cfg_port8_mode : 3; /* [18:16] */ + u32 rsv_57 : 1; /* [19] */ + u32 cfg_port10_mode : 3; /* [22:20] */ + u32 rsv_58 : 1; /* [23] */ + u32 cfg_port12_mode : 3; /* [26:24] */ + u32 rsv_59 : 1; /* [27] */ + u32 cfg_port14_mode : 3; /* [30:28] */ + u32 rsv_60 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_port_link_mode_u; + +/* Define the union csr_cfg_a_line_l_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_a_line_l : 23; /* [22:0] */ + u32 rsv_61 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_a_line_l_err_u; + +/* Define the union csr_cfg_b_line_l_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_b_line_l : 23; /* [22:0] */ + u32 rsv_62 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_b_line_l_err_u; + +/* Define the union csr_cfg_c_line_l_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_c_line_l : 23; /* [22:0] */ + u32 rsv_63 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_cfg_c_line_l_err_u; + +/* Define the union csr_fs_calc_rdy_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sds2pcs_tx_fs_rdy : 16; /* [15:0] */ + u32 rsv_64 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_rdy_u; + +/* Define the union csr_pma_rxeq_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_txdeemph_mux : 18; /* [17:0] */ + u32 rsv_65 : 2; /* [19:18] */ + u32 cfg_pma_txdeemph_lane_sel : 4; /* [23:20] */ + u32 cfg_pma_txdeemph_rd_en : 1; /* [24] */ + u32 rsv_66 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_rxeq_dfx_u; + +/* Define the union csr_serdes_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 serdes_dfx_status : 24; /* [23:0] */ + u32 rsv_67 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_serdes_dfx_u; + +/* Define the union csr_int_type_sel_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ce_int_sel : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_ce_u; + +/* Define the union csr_int_type_sel_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfe_int_sel : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_nfe_u; + +/* Define the union csr_int_type_sel_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fe_int_sel : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_fe_u; + +/* Define the union csr_int_type_sel_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ni_int_sel : 16; /* [15:0] */ + u32 rsv_71 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_ni_u; + +/* Define the union csr_pcs_intr_nfe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_nfe_ind : 16; /* [15:0] */ + u32 rsv_72 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_status_u; + +/* Define the union csr_pcs_intr_nfe_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_nfe_set : 16; /* [15:0] */ + u32 rsv_73 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_set_u; + +/* Define the union csr_pcs_intr_nfe_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_nfe_mask : 16; /* [15:0] */ + u32 rsv_74 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_msk_u; + +/* Define the union csr_pcs_intr_nfe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_nfe_ro : 16; /* [15:0] */ + u32 rsv_75 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_ro_u; + +/* Define the union csr_pcs_intr_fe_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_fe_ind : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_status_u; + +/* Define the union csr_pcs_intr_fe_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_fe_set : 16; /* [15:0] */ + u32 rsv_77 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_set_u; + +/* Define the union csr_pcs_intr_fe_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_fe_mask : 16; /* [15:0] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_msk_u; + +/* Define the union csr_pcs_intr_fe_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_fe_ro : 16; /* [15:0] */ + u32 rsv_79 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_ro_u; + +/* Define the union csr_pcs_intr_ni_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_ni_ind : 16; /* [15:0] */ + u32 rsv_80 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_status_u; + +/* Define the union csr_pcs_intr_ni_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_ni_set : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_set_u; + +/* Define the union csr_pcs_intr_ni_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_ni_mask : 16; /* [15:0] */ + u32 rsv_82 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_msk_u; + +/* Define the union csr_pcs_intr_ni_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_int_ni_ro : 16; /* [15:0] */ + u32 rsv_83 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_ro_u; + +/* Define the union csr_power_chge_prt_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_protect_mode_p0s : 4; /* [3:0] */ + u32 cfg_protect_mode_p1 : 4; /* [7:4] */ + u32 cfg_protect_mode_p2 : 4; /* [11:8] */ + u32 cfg_protect_mode_rxl0s : 4; /* [15:12] */ + u32 rsv_84 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_power_chge_prt_mode_u; + +/* Define the union csr_power_chge_wait_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p0s_wait_p1p2_idle_dis : 1; /* [0] */ + u32 cfg_p1_wait_p2_idle_dis : 1; /* [1] */ + u32 cfg_mclk0_always_on : 1; /* [2] */ + u32 cfg_pll0_never_calib : 1; /* [3] */ + u32 cfg_ccix_25g_20bit_mode : 1; /* [4] */ + u32 cfg_rxtx_status_dly : 11; /* [15:5] */ + u32 cfg_pcs_cdc_txbuf_mode : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_power_chge_wait_idle_u; + +/* Define the union csr_pcs_cdc_dptx_fifo_thres_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_dptx_syncbuf_ae_th : 6; /* [5:0] */ + u32 rsv_85 : 2; /* [7:6] */ + u32 cfg_cdc_dptx_syncbuf_af_th : 6; /* [13:8] */ + u32 rsv_86 : 2; /* [15:14] */ + u32 cfg_cdc_dptx_asynbuf_ae_th : 6; /* [21:16] */ + u32 rsv_87 : 2; /* [23:22] */ + u32 cfg_cdc_dptx_asynbuf_af_th : 6; /* [29:24] */ + u32 cfg_glbcfg_from_bus : 1; /* [30] */ + u32 rsv_88 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_dptx_fifo_thres_u; + +/* Define the union csr_pcs_lane2macro_map_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane2macro_mapping_m0 : 16; /* [15:0] */ + u32 cfg_lane2macro_mapping_m1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_lane2macro_map_0_u; + +/* Define the union csr_pcs_lane2macro_map_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane2macro_mapping_m2 : 16; /* [15:0] */ + u32 cfg_lane2macro_mapping_m3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_lane2macro_map_1_u; + +/* Define the union csr_pcs_cdc_global_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_global_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status0_u; + +/* Define the union csr_pcs_cdc_global_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_global_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status1_u; + +/* Define the union csr_pcs_cdc_global_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_global_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status2_u; + +/* Define the union csr_pcs_cdc_global_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_global_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status3_u; + +/* Define the union csr_pcs_cdc_global_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_global_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_cfg_u; + +/* Define the union csr_pcs_cdc_skp_th_g1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skpadd_th_g1 : 13; /* [12:0] */ + u32 rsv_89 : 3; /* [15:13] */ + u32 cfg_cdc_skprem_th_g1 : 13; /* [28:16] */ + u32 rsv_90 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g1_u; + +/* Define the union csr_pcs_cdc_skp_th_g2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skpadd_th_g2 : 13; /* [12:0] */ + u32 rsv_91 : 3; /* [15:13] */ + u32 cfg_cdc_skprem_th_g2 : 13; /* [28:16] */ + u32 rsv_92 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g2_u; + +/* Define the union csr_pcs_cdc_skp_th_g3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skpadd_th_g3 : 13; /* [12:0] */ + u32 rsv_93 : 3; /* [15:13] */ + u32 cfg_cdc_skprem_th_g3 : 13; /* [28:16] */ + u32 rsv_94 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g3_u; + +/* Define the union csr_pcs_cdc_skp_th_g4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skpadd_th_g4 : 13; /* [12:0] */ + u32 rsv_95 : 3; /* [15:13] */ + u32 cfg_cdc_skprem_th_g4 : 13; /* [28:16] */ + u32 rsv_96 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g4_u; + +/* Define the union csr_pcs_cdc_skp_th_g5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skpadd_th_g5 : 13; /* [12:0] */ + u32 rsv_97 : 3; /* [15:13] */ + u32 cfg_cdc_skprem_th_g5 : 13; /* [28:16] */ + u32 rsv_98 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g5_u; + +/* Define the union csr_pcs_cdc_skp_proc_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skp_add_en : 1; /* [0] */ + u32 cfg_cdc_skp_rem_en : 1; /* [1] */ + u32 rsv_99 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_proc_en_u; + +/* Define the union csr_pcs_cdc_skp_req_dly_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_skp_req_dly_th : 7; /* [6:0] */ + u32 rsv_100 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_req_dly_th_u; + +/* Define the union csr_pcs_cdc_tx_ele_exit_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cdc_tx_exit_ele_protect_value : 3; /* [2:0] */ + u32 cfg_cdc_tx_exit_ele_protect_en : 1; /* [3] */ + u32 rsv_101 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_tx_ele_exit_protect_u; + +/* Define the union csr_retimer_function_switch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_retimer_fw_symbol_unlock_en : 1; /* [0] */ + u32 cfg_retimer_fw_dec_err_replace_en : 1; /* [1] */ + u32 cfg_retimer_udfl_data_replace_en : 1; /* [2] */ + u32 rsv_102 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_retimer_function_switch_u; + +/* Define the union csr_pwrchge_physts_dly_param_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwrchge_physts_dly_param : 26; /* [25:0] */ + u32 cfg_ratechge_in_px : 5; /* [30:26] */ + u32 rsv_103 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pwrchge_physts_dly_param_u; + +/* Define the union csr_pma_cmd_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwrchge_lane_timeout_p0s : 12; /* [11:0] */ + u32 cfg_rx_sync_head : 2; /* [13:12] */ + u32 rsv_104 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_para_0_u; + +/* Define the union csr_pma_cmd_para_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwrchge_lane_timeout_p1 : 12; /* [11:0] */ + u32 rsv_105 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_para_1_u; + +/* Define the union csr_pma_cmd_para_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwrchge_lane_timeout_p2 : 12; /* [11:0] */ + u32 rsv_106 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_para_2_u; + +/* Define the union csr_pma_cmd_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_p0s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_0_u; + +/* Define the union csr_pma_cmd_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_p1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_1_u; + +/* Define the union csr_pma_cmd_sts_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_p2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_2_u; + +/* Define the union csr_pma_cmd_sts_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_txbeacon : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_3_u; + +/* Define the union csr_pma_cmd_sts_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_rxl0s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_4_u; + +/* Define the union csr_pma_cmd_sts_0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_p0s_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_0_1_u; + +/* Define the union csr_pma_cmd_sts_1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_p1_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_1_1_u; + +/* Define the union csr_pma_cmd_sts_2_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_p2_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_2_1_u; + +/* Define the union csr_pma_cmd_sts_3_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_txbeacon_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_3_1_u; + +/* Define the union csr_pma_cmd_sts_4_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pma_cmd_sts_rxl0s_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_4_1_u; + +/* Define the union csr_pcs_clk_icg_en_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_pcs_logic : 16; /* [15:0] */ + u32 icg_en_pcs_logic_div : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_clk_icg_en_0_u; + +/* Define the union csr_pcs_clk_icg_en_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_pcs_tx : 16; /* [15:0] */ + u32 icg_en_pcs_rx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_clk_icg_en_1_u; + +/* Define the union csr_pcs_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_100ns_timer : 8; /* [7:0] */ + u32 cfg_1us_timer : 12; /* [19:8] */ + u32 rsv_107 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_timer_cfg_u; + +/* Define the union csr_pcs_eios_clr_lock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_eios_clr_lock_en : 1; /* [0] */ + u32 cfg_2skp_rem_dis : 1; /* [1] */ + u32 rsv_108 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_eios_clr_lock_u; + +/* Define the union csr_pcs_serial_intve_time_p0s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane_interval_time_p0s : 24; /* [23:0] */ + u32 rsv_109 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_p0s_u; + +/* Define the union csr_pcs_serial_intve_time_p1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane_interval_time_p1 : 24; /* [23:0] */ + u32 rsv_110 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_p1_u; + +/* Define the union csr_pcs_serial_intve_time_p2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane_interval_time_p2 : 24; /* [23:0] */ + u32 rsv_111 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_p2_u; + +/* Define the union csr_pcs_serial_intve_time_rxl0s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane_interval_time_rxl0s : 24; /* [23:0] */ + u32 rsv_112 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_rxl0s_u; + +/* Define the union csr_pcs_serial_intve_time_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lane_timer_mode_p0s : 1; /* [0] */ + u32 rsv_113 : 3; /* [3:1] */ + u32 cfg_lane_timer_mode_p1 : 1; /* [4] */ + u32 rsv_114 : 3; /* [7:5] */ + u32 cfg_lane_timer_mode_p2 : 1; /* [8] */ + u32 rsv_115 : 3; /* [11:9] */ + u32 cfg_lane_timer_mode_rxl0s : 1; /* [12] */ + u32 rsv_116 : 3; /* [15:13] */ + u32 cfg_refclk_serial_en : 1; /* [16] */ + u32 cfg_refclk_timer_mode : 1; /* [17] */ + u32 cfg_refclk_timeout_cnt_clr : 1; /* [18] */ + u32 rsv_117 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_mode_u; + +/* Define the union csr_pcs_serial_intve_time_refclk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_refclk_interval_time : 24; /* [23:0] */ + u32 rsv_118 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_refclk_u; + +/* Define the union csr_pcs_refclk_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 refclk_ctrl_status : 20; /* [19:0] */ + u32 rsv_119 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_glb_reg_pcs_refclk_status_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_pwrchge_cnt_u; + +/* Define the union csr_m_pcs_in13_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 3; /* [2:0] */ + u32 cfg_rx_sigdet : 1; /* [3] */ + u32 cfg_pll_lock : 1; /* [4] */ + u32 cfg_bist_en : 1; /* [5] */ + u32 cfg_bist_rst_n : 1; /* [6] */ + u32 cfg_bist_insert_error : 1; /* [7] */ + u32 cfg_bist_mode : 4; /* [11:8] */ + u32 cfg_osi_en : 1; /* [12] */ + u32 rsv_1 : 1; /* [13] */ + u32 rsv_2 : 1; /* [14] */ + u32 cfg_rx_sigdet_en : 1; /* [15] */ + u32 cfg_txswing : 1; /* [16] */ + u32 cfg_pll_lock_en : 1; /* [17] */ + u32 cfg_txmargin : 3; /* [20:18] */ + u32 cfg_data_rate_en : 1; /* [21] */ + u32 rsv_3 : 2; /* [23:22] */ + u32 cfg_loopback_mode : 3; /* [26:24] */ + u32 rsv_4 : 1; /* [27] */ + u32 cfg_data_rate : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_in13_cfg_u; + +/* Define the union csr_m_pcs_in14_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_loc_lf : 6; /* [5:0] */ + u32 cfg_loc_fs : 6; /* [11:6] */ + u32 cfg_loc_lf_fs_en : 1; /* [12] */ + u32 cfg_dir_feedbk : 6; /* [18:13] */ + u32 cfg_fom_feedbk : 8; /* [26:19] */ + u32 cfg_eye_feedbk_en : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_in14_cfg_u; + +/* Define the union csr_m_pcs_in15_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 7; /* [6:0] */ + u32 cfg_tx_deemph : 18; /* [24:7] */ + u32 cfg_pcs_sim_en : 1; /* [25] */ + u32 cfg_rx_sigdet_reverse : 1; /* [26] */ + u32 cfg_no_sds : 1; /* [27] */ + u32 cfg_rate : 2; /* [29:28] */ + u32 cfg_rate_en : 1; /* [30] */ + u32 rsv_7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_in15_cfg_u; + +/* Define the union csr_mux_los_alos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_los_alos_sel : 1; /* [0] */ + u32 cfg_rxtx_status_en : 1; /* [1] */ + u32 cfg_rxtx_status : 1; /* [2] */ + u32 cfg_eyediag_done_en : 1; /* [3] */ + u32 cfg_eyediag_done : 1; /* [4] */ + u32 cfg_detectrx_rdy_en : 1; /* [5] */ + u32 cfg_detectrx_rdy : 1; /* [6] */ + u32 cfg_far_end_serial_lp : 1; /* [7] */ + u32 rsv_8 : 1; /* [8] */ + u32 cfg_bist_dwidth : 2; /* [10:9] */ + u32 cfg_blockalign_en : 1; /* [11] */ + u32 cfg_blockalign : 1; /* [12] */ + u32 cfg_g3_head_chk_en : 2; /* [14:13] */ + u32 cfg_blockalign_state_sel : 1; /* [15] */ + u32 cfg_eios_mask_dec_err : 2; /* [17:16] */ + u32 cfg_rxmargin_en : 1; /* [18] */ + u32 cfg_rxmargin_sel : 1; /* [19] */ + u32 cfg_gen3_8bit_mode : 1; /* [20] */ + u32 cfg_low_latency_ebuf : 1; /* [21] */ + u32 cfg_eieos_sel : 1; /* [22] */ + u32 rsv_9 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_mux_los_alos_u; + +/* Define the union csr_sds_cfg_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rx_preset_hint : 3; /* [2:0] */ + u32 cfg_rx_preset_hint_en : 1; /* [3] */ + u32 cfg_detectrx_out_en : 1; /* [4] */ + u32 cfg_detectrx_out : 1; /* [5] */ + u32 cfg_powerstate_en : 1; /* [6] */ + u32 rsv_10 : 3; /* [9:7] */ + u32 cfg_txeleidle_en : 1; /* [10] */ + u32 cfg_txeleidle : 1; /* [11] */ + u32 rsv_11 : 2; /* [13:12] */ + u32 cfg_rxvalid_en : 1; /* [14] */ + u32 cfg_rxvalid : 1; /* [15] */ + u32 rsv_12 : 2; /* [17:16] */ + u32 cfg_powerdown_en : 1; /* [18] */ + u32 rsv_13 : 1; /* [19] */ + u32 cfg_powerdown : 4; /* [23:20] */ + u32 cfg_powerstate : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_sds_cfg_reg_u; + +/* Define the union csr_m_pcs_rpt_reg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_bist_sync_done : 1; /* [0] */ + u32 ch_bist_err_cnt : 10; /* [10:1] */ + u32 rsv_15 : 1; /* [11] */ + u32 ch_bist_check_err : 1; /* [12] */ + u32 rsv_16 : 1; /* [13] */ + u32 ch_rxeqeval : 1; /* [14] */ + u32 rxstatus : 3; /* [17:15] */ + u32 g3_align_state : 3; /* [20:18] */ + u32 g12_align_state : 3; /* [23:21] */ + u32 rsv_17 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_rpt_reg_u; + +/* Define the union csr_serdes_status_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ch_rx_sigdet : 1; /* [0] */ + u32 ch_rx_asigdet : 1; /* [1] */ + u32 ch_rxtx_status : 1; /* [2] */ + u32 ch_eyediag_done : 1; /* [3] */ + u32 ch_detectrx_ready : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_serdes_status_rpt_u; + +/* Define the union csr_time_out_rpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 4; /* [3:0] */ + u32 ch_skp_add : 1; /* [4] */ + u32 ch_skp_rem : 1; /* [5] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_time_out_rpt_u; + +/* Define the union csr_polarity_rxvalid_rxelecidle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeleidle_prot_en : 1; /* [0] */ + u32 cfg_rxvalid_out_en : 1; /* [1] */ + u32 cfg_rxpolarity : 1; /* [2] */ + u32 cfg_rxpolarity_en : 1; /* [3] */ + u32 cfg_inject_err : 1; /* [4] */ + u32 cfg_inject_err_tx : 1; /* [5] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_polarity_rxvalid_rxelecidle_u; + +/* Define the union csr_status_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pwr_chge_timeout_clr : 1; /* [0] */ + u32 cfg_rec_det_timeout_clr : 1; /* [1] */ + u32 cfg_pll_loss_lock_clr : 1; /* [2] */ + u32 cfg_rate_chge_timeout_clr : 1; /* [3] */ + u32 cfg_eqeval_timeout_clr : 1; /* [4] */ + u32 cfg_gen3_blk_err_clr : 1; /* [5] */ + u32 cfg_gen3_h_err_clr : 1; /* [6] */ + u32 cfg_ebuf_ovrflow_err_clr : 1; /* [7] */ + u32 cfg_ebuf_undflow_err_clr : 1; /* [8] */ + u32 cfg_g3_dec_h_err_clr : 1; /* [9] */ + u32 cfg_g12_loss_alg_cnt_clr : 1; /* [10] */ + u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */ + u32 rsv_22 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_status_clr_u; + +/* Define the union csr_ebuf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebuf_status : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_ebuf_status_u; + +/* Define the union csr_gen3_dec_enc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gen3_enc_status : 16; /* [15:0] */ + u32 g3_dec_h_err_num : 8; /* [23:16] */ + u32 main_status : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_gen3_dec_enc_status_u; + +/* Define the union csr_wake_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wake_status : 24; /* [23:0] */ + u32 gen12_loss_aln_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_wake_status_u; + +/* Define the union csr_recv_det_or_pwr_chage_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 recv_det_status : 12; /* [11:0] */ + u32 pwr_chge_status : 12; /* [23:12] */ + u32 gen12_decode_err_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_recv_det_or_pwr_chage_u; + +/* Define the union csr_eqeval_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqeval_status : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_eqeval_status_u; + +/* Define the union csr_rate_chge_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rate_chge_status : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_rate_chge_status0_u; + +/* Define the union csr_lane_intr_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_u; + +/* Define the union csr_lane_intr_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_set : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_set_u; + +/* Define the union csr_lane_intr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_mask : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_mask_u; + +/* Define the union csr_lane_intr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_status : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_status_u; + +/* Define the union csr_lane_ebuf_para_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g12_rd_thres : 5; /* [4:0] */ + u32 cfg_g34_rd_thres : 5; /* [9:5] */ + u32 cfg_afull_off_thres : 5; /* [14:10] */ + u32 cfg_afull_on_thres : 5; /* [19:15] */ + u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */ + u32 cfg_sds_rximpedance_en : 1; /* [21] */ + u32 cfg_sds_rximpedance : 1; /* [22] */ + u32 cfg_fiber_en : 1; /* [23] */ + u32 cfg_pma_rxdetect_dis : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_ebuf_para_u; + +/* Define the union csr_rx_margin_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmargin_status : 15; /* [14:0] */ + u32 rsv_31 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_rx_margin_status_u; + +/* Define the union csr_rx_margin_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */ + u32 rsv_32 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_rx_margin_timeout_u; + +/* Define the union csr_rxeq_coarsetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_coarsetune_timeout : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_rxeq_coarsetune_timeout_u; + +/* Define the union csr_rxeq_finetune_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxeq_finetune_timeout : 8; /* [7:0] */ + u32 rsv_34 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_rxeq_finetune_timeout_u; + +/* Define the union csr_detect_clk_flg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tclk_detect_req : 1; /* [0] */ + u32 dfx_tclk_exist : 1; /* [1] */ + u32 rsv_35 : 2; /* [3:2] */ + u32 dfx_rclk_detect_req : 1; /* [4] */ + u32 dfx_rclk_exist : 1; /* [5] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_detect_clk_flg_u; + +/* Define the union csr_msg_bus_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status : 10; /* [9:0] */ + u32 rsv_37 : 2; /* [11:10] */ + u32 eq_adpt_status : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_msg_bus_dfx_u; + +/* Define the union csr_rxeq_start_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rxeq_ft_start : 1; /* [0] */ + u32 cfg_rxeq_ft_start_en : 1; /* [1] */ + u32 cfg_rxeq_ct_start : 1; /* [2] */ + u32 cfg_rxeq_ct_start_en : 1; /* [3] */ + u32 cfg_lane_off_pma_px : 4; /* [7:4] */ + u32 cfg_lane_off_pma_px_en : 1; /* [8] */ + u32 rsv_38 : 3; /* [11:9] */ + u32 cfg_lane_off_pipe_px : 4; /* [15:12] */ + u32 cfg_lane_off_pipe_px_en : 1; /* [16] */ + u32 rsv_39 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_rxeq_start_ctrl_u; + +/* Define the union csr_lane_intr_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_nfe : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_nfe_u; + +/* Define the union csr_lane_intr_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_fe : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_fe_u; + +/* Define the union csr_lane_intr_ro_ni_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lane_int_ro_ni : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_ni_u; + +/* Define the union csr_phy2mac_msg_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_bus_status_p2m : 16; /* [15:0] */ + u32 msg_bus_status_m2p : 4; /* [19:16] */ + u32 msg_bus_m2p_fifo_overflow : 2; /* [21:20] */ + u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */ + u32 msg_bus_p2m_fifo_overflow : 2; /* [25:24] */ + u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */ + u32 rsv_43 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_phy2mac_msg_status_u; + +/* Define the union csr_pcs_msg_pin_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_pin_sel : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_msg_pin_en_u; + +/* Define the union csr_pcs_msg_time_protect_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_msg_prot_para : 20; /* [19:0] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */ + u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */ + u32 rsv_46 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_msg_time_protect_u; + +/* Define the union csr_txbeacon_rxl0s_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */ + u32 rsv_47 : 4; /* [15:12] */ + u32 cfg_rxl0s_timeout_para : 12; /* [27:16] */ + u32 rsv_48 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_txbeacon_rxl0s_timeout_u; + +/* Define the union csr_pcs_misc_ctrl_para_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_g5_eieos_mux : 1; /* [0] */ + u32 cfg_g25_eieos_mux : 1; /* [1] */ + u32 cfg_g20_eieos_mux : 1; /* [2] */ + u32 cfg_g5_align_2eieos_en : 1; /* [3] */ + u32 cfg_rcv_eios_mask : 1; /* [4] */ + u32 cfg_elbuf_mode_vendor : 1; /* [5] */ + u32 cfg_elbuf_depth_vendor : 1; /* [6] */ + u32 cfg_lpbk_slv_delay_en : 1; /* [7] */ + u32 cfg_tx_polarity_revert : 1; /* [8] */ + u32 cfg_rx_beacon_det_msk : 1; /* [9] */ + u32 rsv_49 : 1; /* [10] */ + u32 cfg_g3_high_txidle_delay_en : 1; /* [11] */ + u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */ + u32 cfg_fix_rxdatavld_high_msk : 1; /* [13] */ + u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1; /* [14] */ + u32 cfg_lpbk_slv_flush_dis : 1; /* [15] */ + u32 cfg_lane0_location : 1; /* [16] */ + u32 cfg_lane0_location_en : 1; /* [17] */ + u32 rsv_50 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_misc_ctrl_para_0_u; + +/* Define the union csr_pcs_beacon_rxl0s_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_beacon_status : 4; /* [3:0] */ + u32 rxl0s_status : 4; /* [7:4] */ + u32 tx_beacon_timeout : 2; /* [9:8] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_beacon_rxl0s_status_u; + +/* Define the union csr_pcs_cdc_lane_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status0_u; + +/* Define the union csr_pcs_cdc_lane_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status1_u; + +/* Define the union csr_pcs_cdc_lane_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status2_u; + +/* Define the union csr_pcs_cdc_lane_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcs_cdc_lane_status3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status3_u; + +/* Define the union csr_pcs_rxtx_status_in_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtx_status_stay_low_time : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_rxtx_status_in_low_u; + +/* Define the union csr_pcs_pwrchge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pwrchge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_pwrchge_cnt_u; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/rxtx/apb2ff_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/rxtx/apb2ff_reg_offset.h new file mode 100644 index 000000000..4ef9255f0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/rxtx/apb2ff_reg_offset.h @@ -0,0 +1,68 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : apb2ff_reg_offset.h +// Project line : +// Department : +// Version : 1.0 +// Date : 2021/01/06 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2021/01/06 14:27:03 Create file +// ****************************************************************************** + +#ifndef APB2FF_REG_OFFSET_H +#define APB2FF_REG_OFFSET_H + +/* INDIR_CSR Base address of Module's Register */ +#define CSR_INDIR_CSR_BASE 0x22100000 + +/* **************************************************************************** */ +/* INDIR_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_CTRL_REG (CSR_INDIR_CSR_BASE + 0xC000) /* AN_LT的间接寻址控制寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_TIMEOUT_REG (CSR_INDIR_CSR_BASE + 0xC004) /* AN_LT的间接寻址最大允许时间寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_0_REG (CSR_INDIR_CSR_BASE + 0xC008) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_1_REG (CSR_INDIR_CSR_BASE + 0xC00C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_2_REG (CSR_INDIR_CSR_BASE + 0xC010) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_3_REG (CSR_INDIR_CSR_BASE + 0xC014) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_4_REG (CSR_INDIR_CSR_BASE + 0xC018) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_5_REG (CSR_INDIR_CSR_BASE + 0xC01C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_6_REG (CSR_INDIR_CSR_BASE + 0xC020) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_7_REG (CSR_INDIR_CSR_BASE + 0xC024) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_8_REG (CSR_INDIR_CSR_BASE + 0xC028) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_9_REG (CSR_INDIR_CSR_BASE + 0xC02C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_10_REG (CSR_INDIR_CSR_BASE + 0xC030) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_11_REG (CSR_INDIR_CSR_BASE + 0xC034) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_12_REG (CSR_INDIR_CSR_BASE + 0xC038) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_13_REG (CSR_INDIR_CSR_BASE + 0xC03C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_14_REG (CSR_INDIR_CSR_BASE + 0xC040) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_15_REG (CSR_INDIR_CSR_BASE + 0xC044) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_16_REG (CSR_INDIR_CSR_BASE + 0xC048) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_17_REG (CSR_INDIR_CSR_BASE + 0xC04C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_18_REG (CSR_INDIR_CSR_BASE + 0xC050) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_19_REG (CSR_INDIR_CSR_BASE + 0xC054) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_20_REG (CSR_INDIR_CSR_BASE + 0xC058) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_21_REG (CSR_INDIR_CSR_BASE + 0xC05C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_22_REG (CSR_INDIR_CSR_BASE + 0xC060) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_23_REG (CSR_INDIR_CSR_BASE + 0xC064) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_24_REG (CSR_INDIR_CSR_BASE + 0xC068) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_25_REG (CSR_INDIR_CSR_BASE + 0xC06C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_26_REG (CSR_INDIR_CSR_BASE + 0xC070) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_27_REG (CSR_INDIR_CSR_BASE + 0xC074) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_28_REG (CSR_INDIR_CSR_BASE + 0xC078) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_29_REG (CSR_INDIR_CSR_BASE + 0xC07C) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_30_REG (CSR_INDIR_CSR_BASE + 0xC080) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_INDIR_DATA_31_REG (CSR_INDIR_CSR_BASE + 0xC084) /* AN_LT的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_VERSION_REG (CSR_INDIR_CSR_BASE + 0xC088) /* APB2FF模块AN_LT预留ECO寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_CNT_CAR_REG (CSR_INDIR_CSR_BASE + 0xC08C) /* AN_LT间接寻址读清零寄存器操作选择寄存器 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_PAR_ERR_CNT_REG (CSR_INDIR_CSR_BASE + 0xC090) /* AN_LT返回的数据奇偶校验错误统计 */ +#define CSR_INDIR_CSR_APB2FF_AN_LT_GRACE_TIME_REG (CSR_INDIR_CSR_BASE + 0xC094) /* AN_LT访问超时后，最大等待时间寄存器 */ +#define CSR_INDIR_CSR_APB2FF_HIMAC_INDIR_CTRL_REG (CSR_INDIR_CSR_BASE + 0xC400) /* HIMAC的间接寻址控制寄存器 */ +#define CSR_INDIR_CSR_APB2FF_HIMAC_INDIR_TIMEOUT_REG (CSR_INDIR_CSR_BASE + 0xC404) /* HIMAC的间接寻址最大允许时间寄存器 */ +#define CSR_INDIR_CSR_APB2FF_HIMAC_INDIR_DATA_0_REG (CSR_INDIR_CSR_BASE + 0xC408) /* HIMAC的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_HIMAC_INDIR_DATA_1_REG (CSR_INDIR_CSR_BASE + 0xC40C) /* HIMAC的间接寻址数据寄存器 */ +#define CSR_INDIR_CSR_APB2FF_HIMAC_VERSION_REG (CSR_INDIR_CSR_BASE + 0xC410) /* APB2FF模块HIMAC预留ECO寄存器 */ +#define CSR_INDIR_CSR_APB2FF_HIMAC_CLK_GATE_EN_REG (CSR_INDIR_CSR_BASE + 0xC414) /* T接口的CLK_GATE_EN配置寄存器 */ + +#endif // APB2FF_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/rxtx/c_union_define_apb2ff.h b/drivers/infiniband/hw/hiroce3/include/hw/register/rxtx/c_union_define_apb2ff.h new file mode 100644 index 000000000..e20ffb3a2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/rxtx/c_union_define_apb2ff.h @@ -0,0 +1,82 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2016, Hisilicon Technologies Co. Ltd. +// File name : c_union_define_APB2FF.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Version : V100 +// Date : 2014/5/8 +// Description : Hi 1822 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V4.0.2.5 History : 姚晋鹏 2016/04/12 15:12:21 +// Create file +// ****************************************************************************** + +#ifndef C_UNION_DEFINE_APB2FF_H +#define C_UNION_DEFINE_APB2FF_H + +/* Define the union u_apb2ff_fic_indir_ctrl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int fic_indir_addr : 22; /* [21..0] */ + unsigned int fic_indir_len : 5; /* [26..22] */ + unsigned int fic_indir_cnt_car : 1; /* [27] */ + unsigned int fic_indir_stat : 2; /* [29..28] */ + unsigned int fic_indir_mode : 1; /* [30] */ + unsigned int fic_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_apb2ff_fic_indir_ctrl; + +/* Define the union u_apb2ff_mag_indir_ctrl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int mag_indir_addr : 22; /* [21..0] */ + unsigned int mag_indir_len : 5; /* [26..22] */ + unsigned int mag_indir_cnt_car : 1; /* [27] */ + unsigned int mag_indir_stat : 2; /* [29..28] */ + unsigned int mag_indir_mode : 1; /* [30] */ + unsigned int mag_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_apb2ff_mag_indir_ctrl; + +/* Define the union u_apb2ff_ngpcs_indir_ctrl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int ngpcs_indir_addr : 22; /* [21..0] */ + unsigned int ngpcs_indir_len : 5; /* [26..22] */ + unsigned int ngpcs_indir_cnt_car : 1; /* [27] */ + unsigned int ngpcs_indir_stat : 2; /* [29..28] */ + unsigned int ngpcs_indir_mode : 1; /* [30] */ + unsigned int ngpcs_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_apb2ff_ngpcs_indir_ctrl; + +/* Define the union u_apb2ff_antring_indir_ctrl */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int antring_indir_addr : 22; /* [21..0] */ + unsigned int antring_indir_len : 5; /* [26..22] */ + unsigned int antring_indir_cnt_car : 1; /* [27] */ + unsigned int antring_indir_stat : 2; /* [29..28] */ + unsigned int antring_indir_mode : 1; /* [30] */ + unsigned int antring_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + unsigned int val32; +} u_apb2ff_antring_indir_ctrl; + + +#endif /* C_UNION_DEFINE_APB2FF_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/mag_harden_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/mag_harden_c_union_define.h new file mode 100644 index 000000000..c6be4c6a5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/mag_harden_c_union_define.h @@ -0,0 +1,484 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved. + * Description: mag_harden_c_union_define.h + * Author: Generated automatically by nManager V5.1 + * Create: 2021-09-13 + */ + +#ifndef MAG_HARDEN_C_UNION_DEFINE_H +#define MAG_HARDEN_C_UNION_DEFINE_H + +/* Define the union csr_pll2_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_cfg0 : 16; /* [15:0] */ + u32 pll2_cfg1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_0_u; + +/* Define the union csr_pll2_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_cfg2 : 16; /* [15:0] */ + u32 pll2_cfg3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_1_u; + +/* Define the union csr_pll2_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_cfg4 : 16; /* [15:0] */ + u32 pll2_cfg5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_2_u; + +/* Define the union csr_pll2_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_cfg6 : 16; /* [15:0] */ + u32 pll2_cfg7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_3_u; + +/* Define the union csr_pll2_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_cfg8 : 16; /* [15:0] */ + u32 pll2_cfg9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_4_u; + +/* Define the union csr_pll2_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_cfg10 : 16; /* [15:0] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_5_u; + +/* Define the union csr_pll2_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pllfctrl0_refdiv : 6; /* [5:0] */ + u32 pllfctrl0_fbdiv : 12; /* [17:6] */ + u32 pllfctrl0_postdiv1 : 3; /* [20:18] */ + u32 pllfctrl0_postdiv2 : 3; /* [23:21] */ + u32 pllfctrl0_bypass : 1; /* [24] */ + u32 pllfctrl0_pd : 1; /* [25] */ + u32 pllfctrl0_mode : 1; /* [26] */ + u32 pllfctrl0_fout4phased : 1; /* [27] */ + u32 pllfctrl0_foutpostdivpd : 1; /* [28] */ + u32 pllfctrl0_fout2xpd : 1; /* [29] */ + u32 reserved : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_6_u; + +/* Define the union csr_pll2_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_pllfctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_cfg_7_u; + +/* Define the union csr_pll2_state_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_state0 : 16; /* [15:0] */ + u32 pll2_state1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_state_0_u; + +/* Define the union csr_pll2_state_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_lock : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll2_state_1_u; + +/* Define the union csr_pll3_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_cfg0 : 16; /* [15:0] */ + u32 pll3_cfg1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_0_u; + +/* Define the union csr_pll3_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_cfg2 : 16; /* [15:0] */ + u32 pll3_cfg3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_1_u; + +/* Define the union csr_pll3_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_cfg4 : 16; /* [15:0] */ + u32 pll3_cfg5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_2_u; + +/* Define the union csr_pll3_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_cfg6 : 16; /* [15:0] */ + u32 pll3_cfg7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_3_u; + +/* Define the union csr_pll3_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_cfg8 : 16; /* [15:0] */ + u32 pll3_cfg9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_4_u; + +/* Define the union csr_pll3_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_cfg10 : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_5_u; + +/* Define the union csr_pll3_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pllfctrl0_refdiv : 6; /* [5:0] */ + u32 pllfctrl0_fbdiv : 12; /* [17:6] */ + u32 pllfctrl0_postdiv1 : 3; /* [20:18] */ + u32 pllfctrl0_postdiv2 : 3; /* [23:21] */ + u32 pllfctrl0_bypass : 1; /* [24] */ + u32 pllfctrl0_pd : 1; /* [25] */ + u32 pllfctrl0_mode : 1; /* [26] */ + u32 pllfctrl0_fout4phased : 1; /* [27] */ + u32 pllfctrl0_foutpostdivpd : 1; /* [28] */ + u32 pllfctrl0_fout2xpd : 1; /* [29] */ + u32 reserved : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_6_u; + +/* Define the union csr_pll3_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_pllfctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_cfg_7_u; + +/* Define the union csr_pll3_state_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_state0 : 16; /* [15:0] */ + u32 pll3_state1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_state_0_u; + +/* Define the union csr_pll3_state_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll3_lock : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll3_state_1_u; + +/* Define the union csr_pll4_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_cfg0 : 16; /* [15:0] */ + u32 pll4_cfg1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_0_u; + +/* Define the union csr_pll4_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_cfg2 : 16; /* [15:0] */ + u32 pll4_cfg3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_1_u; + +/* Define the union csr_pll4_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_cfg4 : 16; /* [15:0] */ + u32 pll4_cfg5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_2_u; + +/* Define the union csr_pll4_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_cfg6 : 16; /* [15:0] */ + u32 pll4_cfg7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_3_u; + +/* Define the union csr_pll4_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_cfg8 : 16; /* [15:0] */ + u32 pll4_cfg9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_4_u; + +/* Define the union csr_pll4_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_cfg10 : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_5_u; + +/* Define the union csr_pll4_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pllfctrl0_refdiv : 6; /* [5:0] */ + u32 pllfctrl0_fbdiv : 12; /* [17:6] */ + u32 pllfctrl0_postdiv1 : 3; /* [20:18] */ + u32 pllfctrl0_postdiv2 : 3; /* [23:21] */ + u32 pllfctrl0_bypass : 1; /* [24] */ + u32 pllfctrl0_pd : 1; /* [25] */ + u32 pllfctrl0_mode : 1; /* [26] */ + u32 pllfctrl0_fout4phased : 1; /* [27] */ + u32 pllfctrl0_foutpostdivpd : 1; /* [28] */ + u32 pllfctrl0_fout2xpd : 1; /* [29] */ + u32 reserved : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_6_u; + +/* Define the union csr_pll4_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_pllfctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_cfg_7_u; + +/* Define the union csr_pll4_state_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_state0 : 16; /* [15:0] */ + u32 pll4_state1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_state_0_u; + +/* Define the union csr_pll4_state_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll4_lock : 1; /* [0] */ + u32 rsv_11 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll4_state_1_u; + +/* Define the union csr_pll234_com_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dll_en_pll2 : 1; /* [0] */ + u32 probe_mode_pll2 : 1; /* [1] */ + u32 icg_en_probe_pll2 : 1; /* [2] */ + u32 rsv_15 : 1; /* [3] */ + u32 dll_en_pll3 : 1; /* [4] */ + u32 probe_mode_pll3 : 1; /* [5] */ + u32 icg_en_probe_pll3 : 1; /* [6] */ + u32 rsv_16 : 1; /* [7] */ + u32 dll_en_pll4 : 1; /* [8] */ + u32 probe_mode_pll4 : 1; /* [9] */ + u32 icg_en_probe_pll4 : 1; /* [10] */ + u32 rsv_17 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll234_com_cfg_0_u; + +/* Define the union csr_pll234_com_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_peri_mode : 1; /* [0] */ + u32 pll3_peri_mode : 1; /* [1] */ + u32 pll4_peri_mode : 1; /* [2] */ + u32 rsv_19 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll234_com_cfg_1_u; + +/* Define the union csr_pll234_com_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll2_bypass_external_n : 1; /* [0] */ + u32 pll3_bypass_external_n : 1; /* [1] */ + u32 pll4_bypass_external_n : 1; /* [2] */ + u32 rsv_21 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll234_com_cfg_2_u; + +/* Define the union csr_tsensor_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_temp_ctl : 14; /* [13:0] */ + u32 rsv_23 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tsensor_cfg_0_u; + +/* Define the union csr_tsensor_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor_temp_low_lvl : 10; /* [9:0] */ + u32 tsensor_temp_high_lvl : 10; /* [19:10] */ + u32 tsensor_int_en : 2; /* [21:20] */ + u32 rsv_25 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tsensor_cfg_1_u; + +/* Define the union csr_tsensor_satus_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 temp_val : 10; /* [9:0] */ + u32 temp_val_vld : 1; /* [10] */ + u32 rsv_27 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tsensor_satus_0_u; + +#endif // MAG_HARDEN_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/mag_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/mag_harden_reg_offset.h new file mode 100644 index 000000000..d70861f06 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/mag_harden_reg_offset.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved. + * Description: mag_harden_reg_offset.h + * Author: Generated automatically by nManager V5.1 + * Create: 2021-09-13 + */ + +#ifndef MAG_HARDEN_REG_OFFSET_H +#define MAG_HARDEN_REG_OFFSET_H + +/* MAG_HARDEN_CSR Base address of Module's Register */ +#define CSR_MAG_HARDEN_CSR_BASE (0x22100000) + +/******************************************************************************/ +/* MAG_HARDEN_CSR Registers' Definitions */ +/******************************************************************************/ + +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD000) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD004) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_2_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD008) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_3_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD00C) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_4_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD010) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_5_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD014) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_6_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD018) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_CFG_7_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD01C) /* PLL2的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_STATE_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD024) /* PLL2的状态寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL2_STATE_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD028) /* PLL2的状态寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD02C) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD030) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_2_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD034) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_3_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD038) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_4_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD03C) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_5_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD040) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_6_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD044) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_CFG_7_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD048) /* PLL3的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_STATE_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD050) /* PLL3的状态寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL3_STATE_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD054) /* PLL3的状态寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD058) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD05C) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_2_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD060) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_3_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD064) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_4_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD068) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_5_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD06C) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_6_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD070) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_CFG_7_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD074) /* PLL4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_STATE_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD07C) /* PLL4的状态寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL4_STATE_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD080) /* PLL4的状态寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL234_COM_CFG_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD084) /* PLL2/3/4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL234_COM_CFG_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD088) /* PLL2/3/4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_PLL234_COM_CFG_2_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD08C) /* PLL2/3/4的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_TSENSOR_CFG_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD100) /* TSENSOR IP的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_TSENSOR_CFG_1_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD104) /* TSENSOR IP的config寄存器 */ +#define CSR_MAG_HARDEN_CSR_TSENSOR_SATUS_0_REG (CSR_MAG_HARDEN_CSR_BASE + 0xD108) /* TSENSOR IP的状态寄存器 */ + +#endif // MAG_HARDEN_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/pcie_harden_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/pcie_harden_c_union_define.h new file mode 100644 index 000000000..c973c49b8 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/pcie_harden_c_union_define.h @@ -0,0 +1,738 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : pcie_harden_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2021/06/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2021/06/28 19:30:26 Create file +// ****************************************************************************** + +#ifndef PCIE_HARDEN_C_UNION_DEFINE_H +#define PCIE_HARDEN_C_UNION_DEFINE_H + +/* Define the union csr_rst_cfg_pcie_harden_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_icg_en_pcie50_clk_apb_pcie_harden : 1; /* [0] */ + u32 sc_icg_en_pcie50_clk_ap_axi_pcie_harden : 1; /* [1] */ + u32 icg_en_apb_pcie_harden : 5; /* [6:2] */ + u32 icg_en_mclk_pcie_harden : 4; /* [10:7] */ + u32 icg_en_rxoclk_pcie_harden : 16; /* [26:11] */ + u32 rsv_0 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_0_u; + +/* Define the union csr_rst_cfg_pcie_harden_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_sds0_pma_tx_pcie_harden : 1; /* [0] */ + u32 icg_en_sds1_pma_tx_pcie_harden : 1; /* [1] */ + u32 icg_en_sds2_pma_tx_pcie_harden : 1; /* [2] */ + u32 icg_en_sds3_pma_tx_pcie_harden : 1; /* [3] */ + u32 icg_en_sds0_pma_rx_pcie_harden : 4; /* [7:4] */ + u32 icg_en_sds1_pma_rx_pcie_harden : 4; /* [11:8] */ + u32 icg_en_sds2_pma_rx_pcie_harden : 4; /* [15:12] */ + u32 icg_en_sds3_pma_rx_pcie_harden : 4; /* [19:16] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_1_u; + +/* Define the union csr_rst_cfg_pcie_harden_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_apb_pcie_harden : 5; /* [4:0] */ + u32 srst_req_sds0_pma_tx_pcie_harden : 1; /* [5] */ + u32 srst_req_sds1_pma_tx_pcie_harden : 1; /* [6] */ + u32 srst_req_sds2_pma_tx_pcie_harden : 1; /* [7] */ + u32 srst_req_sds3_pma_tx_pcie_harden : 1; /* [8] */ + u32 srst_req_sds0_pma_rx_pcie_harden : 4; /* [12:9] */ + u32 srst_req_sds1_pma_rx_pcie_harden : 4; /* [16:13] */ + u32 srst_req_sds2_pma_rx_pcie_harden : 4; /* [20:17] */ + u32 srst_req_sds3_pma_rx_pcie_harden : 4; /* [24:21] */ + u32 rsv_2 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_2_u; + +/* Define the union csr_rst_cfg_pcie_harden_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ep_sys_clk_sel_pcie_harden : 1; /* [0] */ + u32 func_mbist_clk_sel_pcie_harden : 1; /* [1] */ + u32 icg_en_probe : 1; /* [2] */ + u32 sds_mclk_icg_en_sel : 4; /* [6:3] */ + u32 pcie_perstn_enable : 4; /* [10:7] */ + u32 pcie_perstn_clear : 4; /* [14:11] */ + u32 probe_mode : 1; /* [15] */ + u32 probe_sds_ep_sel : 1; /* [16] */ + u32 sds_mclk_ckd_icg_en_sel : 4; /* [20:17] */ + u32 mclk_ckd_div_cfg : 4; /* [24:21] */ + u32 icg_en_mclk_ckd : 4; /* [28:25] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_3_u; + +/* Define the union csr_clkreq_h_filter_pcie_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bord2pm_refclk_req_filter_hwid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_clkreq_h_filter_pcie_harden_u; + +/* Define the union csr_clkreq_l_filter_pcie_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bord2pm_refclk_req_filter_lwid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_clkreq_l_filter_pcie_harden_u; + +/* Define the union csr_rst_cfg_sml2_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_sml_sml2_harden : 1; /* [0] */ + u32 icg_en_sml_div2_sml2_harden : 1; /* [1] */ + u32 icg_en_smeg_sml2_harden : 1; /* [2] */ + u32 icg_en_ring_sml2_harden : 1; /* [3] */ + u32 srst_req_sml_sml2_harden : 1; /* [4] */ + u32 srst_req_sml_div2_sml2_harden : 1; /* [5] */ + u32 srst_req_smeg_sml2_harden : 1; /* [6] */ + u32 srst_req_ring_sml2_harden : 1; /* [7] */ + u32 rsv_4 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_sml2_harden_u; + +/* Define the union csr_rst_cfg_sml3_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_sml_sml3_harden : 1; /* [0] */ + u32 icg_en_sml_div2_sml3_harden : 1; /* [1] */ + u32 icg_en_smeg_sml3_harden : 1; /* [2] */ + u32 icg_en_ring_sml3_harden : 1; /* [3] */ + u32 srst_req_sml_sml3_harden : 1; /* [4] */ + u32 srst_req_sml_div2_sml3_harden : 1; /* [5] */ + u32 srst_req_smeg_sml3_harden : 1; /* [6] */ + u32 srst_req_ring_sml3_harden : 1; /* [7] */ + u32 rsv_5 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_sml3_harden_u; + +/* Define the union csr_sml2_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_iso_en_sml2_harden : 1; /* [0] */ + u32 sml_mtcmos_pwr_on_sml2_harden : 1; /* [1] */ + u32 srst_req_wol_por_sml2_harden : 1; /* [2] */ + u32 srst_req_wol_comb_sml2_harden : 1; /* [3] */ + u32 wol_rst_sel_sml2_harden : 1; /* [4] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml2_power_cfg_u; + +/* Define the union csr_sml2_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_mtcmos_pwr_ack_sml2_harden : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml2_power_ack_u; + +/* Define the union csr_sml3_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_iso_en_sml3_harden : 1; /* [0] */ + u32 sml_mtcmos_pwr_on_sml3_harden : 1; /* [1] */ + u32 srst_req_wol_por_sml3_harden : 1; /* [2] */ + u32 srst_req_wol_comb_sml3_harden : 1; /* [3] */ + u32 wol_rst_sel_sml3_harden : 1; /* [4] */ + u32 rsv_8 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml3_power_cfg_u; + +/* Define the union csr_sml3_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_mtcmos_pwr_ack_sml3_harden : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml3_power_ack_u; + +/* Define the union csr_rst_cfg_cpi_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_cpi_octl_harden : 1; /* [0] */ + u32 icg_en_cpi_dma_harden : 1; /* [1] */ + u32 icg_en_ring_cpi_ctrl_harden : 1; /* [2] */ + u32 icg_en_hva_cpi_ctrl_harden : 1; /* [3] */ + u32 icg_en_cpi_div2_cpi_ctrl_harden : 1; /* [4] */ + u32 icg_en_hva_apb_cpi_ctrl_harden : 1; /* [5] */ + u32 icg_en_axi_cpi_ctrl_harden : 1; /* [6] */ + u32 icg_en_1588_cpi_ctrl_harden : 1; /* [7] */ + u32 icg_en_cpi_ctrl_harden : 1; /* [8] */ + u32 srst_req_cpi_octl_harden : 1; /* [9] */ + u32 srst_req_cpi_dma_harden : 1; /* [10] */ + u32 srst_req_ring_cpi_ctrl_harden : 1; /* [11] */ + u32 srst_req_hva_cpi_ctrl_harden : 1; /* [12] */ + u32 srst_req_cpi_div2_cpi_ctrl_harden : 1; /* [13] */ + u32 srst_req_hva_apb_cpi_ctrl_harden : 1; /* [14] */ + u32 srst_req_axi_cpi_ctrl_harden : 1; /* [15] */ + u32 srst_req_1588_cpi_ctrl_harden : 1; /* [16] */ + u32 srst_req_cpi_ctrl_harden : 1; /* [17] */ + u32 icg_en_cpi_500m : 1; /* [18] */ + u32 srst_req_cpi_500m : 1; /* [19] */ + u32 rsv_10 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_cpi_harden_u; + +/* Define the union csr_rst_cfg_ipsutx_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ipsutx_ipsutx_harden : 1; /* [0] */ + u32 icg_en_ring_ipsutx_harden : 1; /* [1] */ + u32 srst_req_ipsutx_ipsutx_harden : 1; /* [2] */ + u32 srst_req_ring_ipsutx_harden : 1; /* [3] */ + u32 rsv_11 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_ipsutx_harden_u; + +/* Define the union csr_rst_cfg_perx_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_perx_perx_harden : 1; /* [0] */ + u32 srst_req_perx_perx_harden : 1; /* [1] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_perx_harden_u; + +/* Define the union csr_ring_sta_ipsutx_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_13 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_ipsutx_harden_u; + +/* Define the union csr_ring_sta_sml2_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml2_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_14 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_sml2_harden_u; + +/* Define the union csr_ring_sta_sml3_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml3_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_15 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_sml3_harden_u; + +/* Define the union csr_ring_sta_cpi_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_16 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_cpi_harden_u; + +/* Define the union csr_pll1_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_cfg0 : 16; /* [15:0] */ + u32 pll1_cfg1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_0_u; + +/* Define the union csr_pll1_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_cfg2 : 16; /* [15:0] */ + u32 pll1_cfg3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_1_u; + +/* Define the union csr_pll1_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_cfg4 : 16; /* [15:0] */ + u32 pll1_cfg5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_2_u; + +/* Define the union csr_pll1_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_cfg6 : 16; /* [15:0] */ + u32 pll1_cfg7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_3_u; + +/* Define the union csr_pll1_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_cfg8 : 16; /* [15:0] */ + u32 pll1_cfg9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_4_u; + +/* Define the union csr_pll1_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_cfg10 : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_5_u; + +/* Define the union csr_pll1_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_pllfctrl0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_6_u; + +/* Define the union csr_pll1_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_pllfctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_7_u; + +/* Define the union csr_pll1_cfg_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_bypass_external_n : 1; /* [0] */ + u32 pll1_peri_mode : 1; /* [1] */ + u32 dll_en_pll1 : 1; /* [2] */ + u32 probe_mode_pll1 : 1; /* [3] */ + u32 icg_en_probe_pll1 : 1; /* [4] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_cfg_8_u; + +/* Define the union csr_pll1_state_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_state0 : 16; /* [15:0] */ + u32 pll1_state1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_state_0_u; + +/* Define the union csr_pll1_state_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll1_lock : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll1_state_1_u; + +/* Define the union csr_tsensor_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_temp_ctl : 14; /* [13:0] */ + u32 rsv_20 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tsensor_cfg_0_u; + +/* Define the union csr_tsensor_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor_temp_low_lvl : 10; /* [9:0] */ + u32 tsensor_temp_high_lvl : 10; /* [19:10] */ + u32 tsensor_int_en : 2; /* [21:20] */ + u32 rsv_21 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tsensor_cfg_1_u; + +/* Define the union csr_tsensor_satus_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 temp_val : 10; /* [9:0] */ + u32 temp_val_vld : 1; /* [10] */ + u32 rsv_22 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tsensor_satus_0_u; + +/* Define the union csr_rst_cfg_pcie_harden_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_icg_en_pcie50_clk_apb : 2; /* [1:0] */ + u32 sc_icg_en_pcie50_clk_ap_axi : 5; /* [6:2] */ + u32 sc_icg_en_pcie50_clk_tl_axi : 1; /* [7] */ + u32 sc_icg_en_pcie50_clk_core_tl_port : 4; /* [11:8] */ + u32 sc_icg_en_pcie50_clk_core_tl_port_div : 4; /* [15:12] */ + u32 sc_icg_en_pcie50_clk_core_tl_common : 1; /* [16] */ + u32 sc_icg_en_pcie50_clk_core_phy_port : 4; /* [20:17] */ + u32 sc_icg_en_pcie50_clk_core_phy_port_div : 4; /* [24:21] */ + u32 sc_icg_en_pcie50_clk_core_phy_common : 1; /* [25] */ + u32 sc_icg_en_pcie50_clk_pcs_logic_common : 1; /* [26] */ + u32 sc_icg_en_pcie50_clk_pcs_apb : 1; /* [27] */ + u32 rsv_23 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_4_u; + +/* Define the union csr_rst_cfg_pcie_harden_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_icg_en_pcie50_clk_core_phy_lane : 16; /* [15:0] */ + u32 sc_icg_en_pcie50_clk_pipe_lane : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_5_u; + +/* Define the union csr_rst_cfg_pcie_harden_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_icg_en_pcie50_clk_pcs_logic : 16; /* [15:0] */ + u32 sc_icg_en_pcie50_clk_pcs_logic_div : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_6_u; + +/* Define the union csr_rst_cfg_pcie_harden_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_icg_en_pcie50_clk_pcs_tx : 16; /* [15:0] */ + u32 sc_icg_en_pcie50_clk_pcs_rx : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_pcie_harden_7_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_rst_cfg_pcie_harden_0_u rst_cfg_pcie_harden_0; /* 0 */ + volatile csr_rst_cfg_pcie_harden_1_u rst_cfg_pcie_harden_1; /* 4 */ + volatile csr_rst_cfg_pcie_harden_2_u rst_cfg_pcie_harden_2; /* 8 */ + volatile csr_rst_cfg_pcie_harden_3_u rst_cfg_pcie_harden_3; /* C */ + volatile csr_clkreq_h_filter_pcie_harden_u clkreq_h_filter_pcie_harden; /* 10 */ + volatile csr_clkreq_l_filter_pcie_harden_u clkreq_l_filter_pcie_harden; /* 14 */ + volatile csr_rst_cfg_sml2_harden_u rst_cfg_sml2_harden; /* 18 */ + volatile csr_rst_cfg_sml3_harden_u rst_cfg_sml3_harden; /* 1C */ + volatile csr_sml2_power_cfg_u sml2_power_cfg; /* 20 */ + volatile csr_sml2_power_ack_u sml2_power_ack; /* 24 */ + volatile csr_sml3_power_cfg_u sml3_power_cfg; /* 28 */ + volatile csr_sml3_power_ack_u sml3_power_ack; /* 2C */ + volatile csr_rst_cfg_cpi_harden_u rst_cfg_cpi_harden; /* 30 */ + volatile csr_rst_cfg_ipsutx_harden_u rst_cfg_ipsutx_harden; /* 34 */ + volatile csr_rst_cfg_perx_harden_u rst_cfg_perx_harden; /* 38 */ + volatile csr_ring_sta_ipsutx_harden_u ring_sta_ipsutx_harden; /* 3C */ + volatile csr_ring_sta_sml2_harden_u ring_sta_sml2_harden; /* 40 */ + volatile csr_ring_sta_sml3_harden_u ring_sta_sml3_harden; /* 44 */ + volatile csr_ring_sta_cpi_harden_u ring_sta_cpi_harden; /* 48 */ + volatile csr_pll1_cfg_0_u pll1_cfg_0; /* 4C */ + volatile csr_pll1_cfg_1_u pll1_cfg_1; /* 50 */ + volatile csr_pll1_cfg_2_u pll1_cfg_2; /* 54 */ + volatile csr_pll1_cfg_3_u pll1_cfg_3; /* 58 */ + volatile csr_pll1_cfg_4_u pll1_cfg_4; /* 5C */ + volatile csr_pll1_cfg_5_u pll1_cfg_5; /* 60 */ + volatile csr_pll1_cfg_6_u pll1_cfg_6; /* 64 */ + volatile csr_pll1_cfg_7_u pll1_cfg_7; /* 68 */ + volatile csr_pll1_cfg_8_u pll1_cfg_8; /* 6C */ + volatile csr_pll1_state_0_u pll1_state_0; /* 70 */ + volatile csr_pll1_state_1_u pll1_state_1; /* 74 */ + volatile csr_tsensor_cfg_0_u tsensor_cfg_0; /* 78 */ + volatile csr_tsensor_cfg_1_u tsensor_cfg_1; /* 7C */ + volatile csr_tsensor_satus_0_u tsensor_satus_0; /* 80 */ + volatile csr_rst_cfg_pcie_harden_4_u rst_cfg_pcie_harden_4; /* 84 */ + volatile csr_rst_cfg_pcie_harden_5_u rst_cfg_pcie_harden_5; /* 88 */ + volatile csr_rst_cfg_pcie_harden_6_u rst_cfg_pcie_harden_6; /* 8C */ + volatile csr_rst_cfg_pcie_harden_7_u rst_cfg_pcie_harden_7; /* 90 */ +} S_pcie_harden_REGS_TYPE; + +/* Declare the struct pointor of the module pcie_harden */ +extern volatile S_pcie_harden_REGS_TYPE *goppcie_hardenAllReg; + +/* Declare the functions that set the member value */ +int iSetRST_CFG_PCIE_HARDEN_0_sc_icg_en_pcie50_clk_apb_pcie_harden(unsigned int usc_icg_en_pcie50_clk_apb_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_0_sc_icg_en_pcie50_clk_ap_axi_pcie_harden( + unsigned int usc_icg_en_pcie50_clk_ap_axi_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_0_icg_en_apb_pcie_harden(unsigned int uicg_en_apb_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_0_icg_en_mclk_pcie_harden(unsigned int uicg_en_mclk_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_0_icg_en_rxoclk_pcie_harden(unsigned int uicg_en_rxoclk_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds0_pma_tx_pcie_harden(unsigned int uicg_en_sds0_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds1_pma_tx_pcie_harden(unsigned int uicg_en_sds1_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds2_pma_tx_pcie_harden(unsigned int uicg_en_sds2_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds3_pma_tx_pcie_harden(unsigned int uicg_en_sds3_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds0_pma_rx_pcie_harden(unsigned int uicg_en_sds0_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds1_pma_rx_pcie_harden(unsigned int uicg_en_sds1_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds2_pma_rx_pcie_harden(unsigned int uicg_en_sds2_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_1_icg_en_sds3_pma_rx_pcie_harden(unsigned int uicg_en_sds3_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_apb_pcie_harden(unsigned int usrst_req_apb_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds0_pma_tx_pcie_harden(unsigned int usrst_req_sds0_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds1_pma_tx_pcie_harden(unsigned int usrst_req_sds1_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds2_pma_tx_pcie_harden(unsigned int usrst_req_sds2_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds3_pma_tx_pcie_harden(unsigned int usrst_req_sds3_pma_tx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds0_pma_rx_pcie_harden(unsigned int usrst_req_sds0_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds1_pma_rx_pcie_harden(unsigned int usrst_req_sds1_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds2_pma_rx_pcie_harden(unsigned int usrst_req_sds2_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_2_srst_req_sds3_pma_rx_pcie_harden(unsigned int usrst_req_sds3_pma_rx_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_3_pcie_ep_sys_clk_sel_pcie_harden(unsigned int upcie_ep_sys_clk_sel_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_3_func_mbist_clk_sel_pcie_harden(unsigned int ufunc_mbist_clk_sel_pcie_harden); +int iSetRST_CFG_PCIE_HARDEN_3_icg_en_probe(unsigned int uicg_en_probe); +int iSetRST_CFG_PCIE_HARDEN_3_sds_mclk_icg_en_sel(unsigned int usds_mclk_icg_en_sel); +int iSetRST_CFG_PCIE_HARDEN_3_pcie_perstn_enable(unsigned int upcie_perstn_enable); +int iSetRST_CFG_PCIE_HARDEN_3_pcie_perstn_clear(unsigned int upcie_perstn_clear); +int iSetRST_CFG_PCIE_HARDEN_3_probe_mode(unsigned int uprobe_mode); +int iSetRST_CFG_PCIE_HARDEN_3_probe_sds_ep_sel(unsigned int uprobe_sds_ep_sel); +int iSetRST_CFG_PCIE_HARDEN_3_sds_mclk_ckd_icg_en_sel(unsigned int usds_mclk_ckd_icg_en_sel); +int iSetRST_CFG_PCIE_HARDEN_3_mclk_ckd_div_cfg(unsigned int umclk_ckd_div_cfg); +int iSetRST_CFG_PCIE_HARDEN_3_icg_en_mclk_ckd(unsigned int uicg_en_mclk_ckd); +int iSetCLKREQ_H_FILTER_PCIE_HARDEN_bord2pm_refclk_req_filter_hwid(unsigned int ubord2pm_refclk_req_filter_hwid); +int iSetCLKREQ_L_FILTER_PCIE_HARDEN_bord2pm_refclk_req_filter_lwid(unsigned int ubord2pm_refclk_req_filter_lwid); +int iSetRST_CFG_SML2_HARDEN_icg_en_sml_sml2_harden(unsigned int uicg_en_sml_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_icg_en_sml_div2_sml2_harden(unsigned int uicg_en_sml_div2_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_icg_en_smeg_sml2_harden(unsigned int uicg_en_smeg_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_icg_en_ring_sml2_harden(unsigned int uicg_en_ring_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_srst_req_sml_sml2_harden(unsigned int usrst_req_sml_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_srst_req_sml_div2_sml2_harden(unsigned int usrst_req_sml_div2_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_srst_req_smeg_sml2_harden(unsigned int usrst_req_smeg_sml2_harden); +int iSetRST_CFG_SML2_HARDEN_srst_req_ring_sml2_harden(unsigned int usrst_req_ring_sml2_harden); +int iSetRST_CFG_SML3_HARDEN_icg_en_sml_sml3_harden(unsigned int uicg_en_sml_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_icg_en_sml_div2_sml3_harden(unsigned int uicg_en_sml_div2_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_icg_en_smeg_sml3_harden(unsigned int uicg_en_smeg_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_icg_en_ring_sml3_harden(unsigned int uicg_en_ring_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_srst_req_sml_sml3_harden(unsigned int usrst_req_sml_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_srst_req_sml_div2_sml3_harden(unsigned int usrst_req_sml_div2_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_srst_req_smeg_sml3_harden(unsigned int usrst_req_smeg_sml3_harden); +int iSetRST_CFG_SML3_HARDEN_srst_req_ring_sml3_harden(unsigned int usrst_req_ring_sml3_harden); +int iSetSML2_POWER_CFG_sml_iso_en_sml2_harden(unsigned int usml_iso_en_sml2_harden); +int iSetSML2_POWER_CFG_sml_mtcmos_pwr_on_sml2_harden(unsigned int usml_mtcmos_pwr_on_sml2_harden); +int iSetSML2_POWER_CFG_srst_req_wol_por_sml2_harden(unsigned int usrst_req_wol_por_sml2_harden); +int iSetSML2_POWER_CFG_srst_req_wol_comb_sml2_harden(unsigned int usrst_req_wol_comb_sml2_harden); +int iSetSML2_POWER_CFG_wol_rst_sel_sml2_harden(unsigned int uwol_rst_sel_sml2_harden); +int iSetSML2_POWER_ACK_sml_mtcmos_pwr_ack_sml2_harden(unsigned int usml_mtcmos_pwr_ack_sml2_harden); +int iSetSML3_POWER_CFG_sml_iso_en_sml3_harden(unsigned int usml_iso_en_sml3_harden); +int iSetSML3_POWER_CFG_sml_mtcmos_pwr_on_sml3_harden(unsigned int usml_mtcmos_pwr_on_sml3_harden); +int iSetSML3_POWER_CFG_srst_req_wol_por_sml3_harden(unsigned int usrst_req_wol_por_sml3_harden); +int iSetSML3_POWER_CFG_srst_req_wol_comb_sml3_harden(unsigned int usrst_req_wol_comb_sml3_harden); +int iSetSML3_POWER_CFG_wol_rst_sel_sml3_harden(unsigned int uwol_rst_sel_sml3_harden); +int iSetSML3_POWER_ACK_sml_mtcmos_pwr_ack_sml3_harden(unsigned int usml_mtcmos_pwr_ack_sml3_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_octl_harden(unsigned int uicg_en_cpi_octl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_dma_harden(unsigned int uicg_en_cpi_dma_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_ring_cpi_ctrl_harden(unsigned int uicg_en_ring_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_hva_cpi_ctrl_harden(unsigned int uicg_en_hva_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_div2_cpi_ctrl_harden(unsigned int uicg_en_cpi_div2_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_hva_apb_cpi_ctrl_harden(unsigned int uicg_en_hva_apb_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_axi_cpi_ctrl_harden(unsigned int uicg_en_axi_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_1588_cpi_ctrl_harden(unsigned int uicg_en_1588_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_ctrl_harden(unsigned int uicg_en_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_octl_harden(unsigned int usrst_req_cpi_octl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_dma_harden(unsigned int usrst_req_cpi_dma_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_ring_cpi_ctrl_harden(unsigned int usrst_req_ring_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_hva_cpi_ctrl_harden(unsigned int usrst_req_hva_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_div2_cpi_ctrl_harden(unsigned int usrst_req_cpi_div2_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_hva_apb_cpi_ctrl_harden(unsigned int usrst_req_hva_apb_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_axi_cpi_ctrl_harden(unsigned int usrst_req_axi_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_1588_cpi_ctrl_harden(unsigned int usrst_req_1588_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_ctrl_harden(unsigned int usrst_req_cpi_ctrl_harden); +int iSetRST_CFG_CPI_HARDEN_icg_en_cpi_500m(unsigned int uicg_en_cpi_500m); +int iSetRST_CFG_CPI_HARDEN_srst_req_cpi_500m(unsigned int usrst_req_cpi_500m); +int iSetRST_CFG_IPSUTX_HARDEN_icg_en_ipsutx_ipsutx_harden(unsigned int uicg_en_ipsutx_ipsutx_harden); +int iSetRST_CFG_IPSUTX_HARDEN_icg_en_ring_ipsutx_harden(unsigned int uicg_en_ring_ipsutx_harden); +int iSetRST_CFG_IPSUTX_HARDEN_srst_req_ipsutx_ipsutx_harden(unsigned int usrst_req_ipsutx_ipsutx_harden); +int iSetRST_CFG_IPSUTX_HARDEN_srst_req_ring_ipsutx_harden(unsigned int usrst_req_ring_ipsutx_harden); +int iSetRST_CFG_PERX_HARDEN_icg_en_perx_perx_harden(unsigned int uicg_en_perx_perx_harden); +int iSetRST_CFG_PERX_HARDEN_srst_req_perx_perx_harden(unsigned int usrst_req_perx_perx_harden); +int iSetRING_STA_IPSUTX_HARDEN_ipsutx_harden_rs_nd_pe_crdt_sta(unsigned int uipsutx_harden_rs_nd_pe_crdt_sta); +int iSetRING_STA_SML2_HARDEN_sml2_harden_rs_nd_pe_crdt_sta(unsigned int usml2_harden_rs_nd_pe_crdt_sta); +int iSetRING_STA_SML3_HARDEN_sml3_harden_rs_nd_pe_crdt_sta(unsigned int usml3_harden_rs_nd_pe_crdt_sta); +int iSetRING_STA_CPI_HARDEN_cpi_harden_rs_nd_pe_crdt_sta(unsigned int ucpi_harden_rs_nd_pe_crdt_sta); +int iSetPLL1_CFG_0_pll1_cfg0(unsigned int upll1_cfg0); +int iSetPLL1_CFG_0_pll1_cfg1(unsigned int upll1_cfg1); +int iSetPLL1_CFG_1_pll1_cfg2(unsigned int upll1_cfg2); +int iSetPLL1_CFG_1_pll1_cfg3(unsigned int upll1_cfg3); +int iSetPLL1_CFG_2_pll1_cfg4(unsigned int upll1_cfg4); +int iSetPLL1_CFG_2_pll1_cfg5(unsigned int upll1_cfg5); +int iSetPLL1_CFG_3_pll1_cfg6(unsigned int upll1_cfg6); +int iSetPLL1_CFG_3_pll1_cfg7(unsigned int upll1_cfg7); +int iSetPLL1_CFG_4_pll1_cfg8(unsigned int upll1_cfg8); +int iSetPLL1_CFG_4_pll1_cfg9(unsigned int upll1_cfg9); +int iSetPLL1_CFG_5_pll1_cfg10(unsigned int upll1_cfg10); +int iSetPLL1_CFG_6_pll1_pllfctrl0(unsigned int upll1_pllfctrl0); +int iSetPLL1_CFG_7_pll1_pllfctrl1(unsigned int upll1_pllfctrl1); +int iSetPLL1_CFG_8_pll1_bypass_external_n(unsigned int upll1_bypass_external_n); +int iSetPLL1_CFG_8_pll1_peri_mode(unsigned int upll1_peri_mode); +int iSetPLL1_CFG_8_dll_en_pll1(unsigned int udll_en_pll1); +int iSetPLL1_CFG_8_probe_mode_pll1(unsigned int uprobe_mode_pll1); +int iSetPLL1_CFG_8_icg_en_probe_pll1(unsigned int uicg_en_probe_pll1); +int iSetPLL1_STATE_0_pll1_state0(unsigned int upll1_state0); +int iSetPLL1_STATE_0_pll1_state1(unsigned int upll1_state1); +int iSetPLL1_STATE_1_pll1_lock(unsigned int upll1_lock); +int iSetTSENSOR_CFG_0_sc_temp_ctl(unsigned int usc_temp_ctl); +int iSetTSENSOR_CFG_1_tsensor_temp_low_lvl(unsigned int utsensor_temp_low_lvl); +int iSetTSENSOR_CFG_1_tsensor_temp_high_lvl(unsigned int utsensor_temp_high_lvl); +int iSetTSENSOR_CFG_1_tsensor_int_en(unsigned int utsensor_int_en); +int iSetTSENSOR_SATUS_0_temp_val(unsigned int utemp_val); +int iSetTSENSOR_SATUS_0_temp_val_vld(unsigned int utemp_val_vld); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_apb(unsigned int usc_icg_en_pcie50_clk_apb); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_ap_axi(unsigned int usc_icg_en_pcie50_clk_ap_axi); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_tl_axi(unsigned int usc_icg_en_pcie50_clk_tl_axi); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_tl_port(unsigned int usc_icg_en_pcie50_clk_core_tl_port); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_tl_port_div( + unsigned int usc_icg_en_pcie50_clk_core_tl_port_div); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_tl_common(unsigned int usc_icg_en_pcie50_clk_core_tl_common); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_phy_port(unsigned int usc_icg_en_pcie50_clk_core_phy_port); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_phy_port_div( + unsigned int usc_icg_en_pcie50_clk_core_phy_port_div); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_core_phy_common(unsigned int usc_icg_en_pcie50_clk_core_phy_common); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_pcs_logic_common( + unsigned int usc_icg_en_pcie50_clk_pcs_logic_common); +int iSetRST_CFG_PCIE_HARDEN_4_sc_icg_en_pcie50_clk_pcs_apb(unsigned int usc_icg_en_pcie50_clk_pcs_apb); +int iSetRST_CFG_PCIE_HARDEN_5_sc_icg_en_pcie50_clk_core_phy_lane(unsigned int usc_icg_en_pcie50_clk_core_phy_lane); +int iSetRST_CFG_PCIE_HARDEN_5_sc_icg_en_pcie50_clk_pipe_lane(unsigned int usc_icg_en_pcie50_clk_pipe_lane); +int iSetRST_CFG_PCIE_HARDEN_6_sc_icg_en_pcie50_clk_pcs_logic(unsigned int usc_icg_en_pcie50_clk_pcs_logic); +int iSetRST_CFG_PCIE_HARDEN_6_sc_icg_en_pcie50_clk_pcs_logic_div(unsigned int usc_icg_en_pcie50_clk_pcs_logic_div); +int iSetRST_CFG_PCIE_HARDEN_7_sc_icg_en_pcie50_clk_pcs_tx(unsigned int usc_icg_en_pcie50_clk_pcs_tx); +int iSetRST_CFG_PCIE_HARDEN_7_sc_icg_en_pcie50_clk_pcs_rx(unsigned int usc_icg_en_pcie50_clk_pcs_rx); + + +#endif // PCIE_HARDEN_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/pcie_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/pcie_harden_reg_offset.h new file mode 100644 index 000000000..c2c42025a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/pcie_harden_reg_offset.h @@ -0,0 +1,65 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : pcie_harden_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2021/06/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2021/06/28 19:30:26 Create file +// ****************************************************************************** + +#ifndef PCIE_HARDEN_REG_OFFSET_H +#define PCIE_HARDEN_REG_OFFSET_H + +/* PCIE_HARDEN Base address of Module's Register */ +#define CSR_PCIE_HARDEN_BASE (0x21FC0000) + +/* **************************************************************************** */ +/* PCIE_HARDEN Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_0_REG (CSR_PCIE_HARDEN_BASE + 0x0) /* PCIE_HARDEN_CRG的ICG_EN控制寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_1_REG (CSR_PCIE_HARDEN_BASE + 0x4) /* PCIE_HARDEN_CRG控制寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_2_REG (CSR_PCIE_HARDEN_BASE + 0x8) /* PCIE_HARDEN_CRG的SRST_REQ控制寄存器 \ + */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_3_REG (CSR_PCIE_HARDEN_BASE + 0xC) /* PCIE_HARDEN_CRG控制寄存器 */ +#define CSR_PCIE_HARDEN_CLKREQ_H_FILTER_PCIE_HARDEN_REG \ + (CSR_PCIE_HARDEN_BASE + 0x10) /* PCIE HARDEN CLKREQ的高电平消抖持续时间配置 */ +#define CSR_PCIE_HARDEN_CLKREQ_L_FILTER_PCIE_HARDEN_REG \ + (CSR_PCIE_HARDEN_BASE + 0x14) /* PCIE HARDEN CLKREQ的低电平消抖持续时间配置 */ +#define CSR_PCIE_HARDEN_RST_CFG_SML2_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x18) /* SML2_HARDEN的crg控制 */ +#define CSR_PCIE_HARDEN_RST_CFG_SML3_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x1C) /* SML3_HARDEN的crg控制 */ +#define CSR_PCIE_HARDEN_SML2_POWER_CFG_REG (CSR_PCIE_HARDEN_BASE + 0x20) /* SML2 power控制寄存器 */ +#define CSR_PCIE_HARDEN_SML2_POWER_ACK_REG (CSR_PCIE_HARDEN_BASE + 0x24) /* SML2 power ACK状态寄存器 */ +#define CSR_PCIE_HARDEN_SML3_POWER_CFG_REG (CSR_PCIE_HARDEN_BASE + 0x28) /* SML3 power控制寄存器 */ +#define CSR_PCIE_HARDEN_SML3_POWER_ACK_REG (CSR_PCIE_HARDEN_BASE + 0x2C) /* SML3 power ACK状态寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_CPI_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x30) /* CPI_HARDEN的crg控制 */ +#define CSR_PCIE_HARDEN_RST_CFG_IPSUTX_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x34) /* IPSUTX_HARDEN的crg控制 */ +#define CSR_PCIE_HARDEN_RST_CFG_PERX_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x38) /* PERX_HARDEN的crg控制 */ +#define CSR_PCIE_HARDEN_RING_STA_IPSUTX_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x3C) /* RING_CRDT_STA */ +#define CSR_PCIE_HARDEN_RING_STA_SML2_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x40) /* RING_CRDT_STA */ +#define CSR_PCIE_HARDEN_RING_STA_SML3_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x44) /* RING_CRDT_STA */ +#define CSR_PCIE_HARDEN_RING_STA_CPI_HARDEN_REG (CSR_PCIE_HARDEN_BASE + 0x48) /* RING_CRDT_STA */ +#define CSR_PCIE_HARDEN_PLL1_CFG_0_REG (CSR_PCIE_HARDEN_BASE + 0x4C) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_1_REG (CSR_PCIE_HARDEN_BASE + 0x50) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_2_REG (CSR_PCIE_HARDEN_BASE + 0x54) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_3_REG (CSR_PCIE_HARDEN_BASE + 0x58) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_4_REG (CSR_PCIE_HARDEN_BASE + 0x5C) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_5_REG (CSR_PCIE_HARDEN_BASE + 0x60) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_6_REG (CSR_PCIE_HARDEN_BASE + 0x64) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_7_REG (CSR_PCIE_HARDEN_BASE + 0x68) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_CFG_8_REG (CSR_PCIE_HARDEN_BASE + 0x6C) /* PLL1的config寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_STATE_0_REG (CSR_PCIE_HARDEN_BASE + 0x70) /* PLL1状态寄存器 */ +#define CSR_PCIE_HARDEN_PLL1_STATE_1_REG (CSR_PCIE_HARDEN_BASE + 0x74) /* PLL1状态寄存器 */ +#define CSR_PCIE_HARDEN_TSENSOR_CFG_0_REG (CSR_PCIE_HARDEN_BASE + 0x78) /* TSENSOR IP的配置寄存器 */ +#define CSR_PCIE_HARDEN_TSENSOR_CFG_1_REG (CSR_PCIE_HARDEN_BASE + 0x7C) /* TSENSOR IP的配置寄存器 */ +#define CSR_PCIE_HARDEN_TSENSOR_SATUS_0_REG (CSR_PCIE_HARDEN_BASE + 0x80) /* TSENSOR IP的状态寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_4_REG (CSR_PCIE_HARDEN_BASE + 0x84) /* PCIE_HARDEN_CRG控制寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_5_REG (CSR_PCIE_HARDEN_BASE + 0x88) /* PCIE_HARDEN_CRG控制寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_6_REG (CSR_PCIE_HARDEN_BASE + 0x8C) /* PCIE_HARDEN_CRG控制寄存器 */ +#define CSR_PCIE_HARDEN_RST_CFG_PCIE_HARDEN_7_REG (CSR_PCIE_HARDEN_BASE + 0x90) /* PCIE_HARDEN_CRG控制寄存器 */ + +#endif // PCIE_HARDEN_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/smf0_harden_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/smf0_harden_c_union_define.h new file mode 100644 index 000000000..8eab998aa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/smf0_harden_c_union_define.h @@ -0,0 +1,1611 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : smf0_harden_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/12/25 10:33:43 Create file +// ****************************************************************************** + +#ifndef SMF0_HARDEN_C_UNION_DEFINE_H +#define SMF0_HARDEN_C_UNION_DEFINE_H + +/* Define the union csr_crg_cfg_smf0_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ring_smf0_harden : 1; /* [0] */ + u32 icg_en_smf_smf0_harden : 1; /* [1] */ + u32 icg_en_smf_div2_smf0_harden : 1; /* [2] */ + u32 icg_en_virtio_core_smf0_harden : 1; /* [3] */ + u32 icg_en_smeg_smf0_harden : 1; /* [4] */ + u32 srst_req_ring_smf0_harden : 1; /* [5] */ + u32 srst_req_smf_smf0_harden : 1; /* [6] */ + u32 srst_req_virtio_core_smf0_harden : 1; /* [7] */ + u32 srst_req_smf_div2_smf0_harden : 1; /* [8] */ + u32 srst_req_smeg_smf0_harden : 1; /* [9] */ + u32 rsv_1 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_smf0_harden_u; + +/* Define the union csr_crg_cfg_smf1_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ring_smf1_harden : 1; /* [0] */ + u32 icg_en_smf_smf1_harden : 1; /* [1] */ + u32 icg_en_smf_div2_smf1_harden : 1; /* [2] */ + u32 icg_en_virtio_core_smf1_harden : 1; /* [3] */ + u32 icg_en_smeg_smf1_harden : 1; /* [4] */ + u32 srst_req_ring_smf1_harden : 1; /* [5] */ + u32 srst_req_smf_smf1_harden : 1; /* [6] */ + u32 srst_req_virtio_core_smf1_harden : 1; /* [7] */ + u32 srst_req_smf_div2_smf1_harden : 1; /* [8] */ + u32 srst_req_smeg_smf1_harden : 1; /* [9] */ + u32 rsv_3 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_smf1_harden_u; + +/* Define the union csr_crg_cfg_stftile0_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_qcm_stftile0_harden : 1; /* [0] */ + u32 icg_en_tile_stftile0_harden : 1; /* [1] */ + u32 icg_en_tile_div2_stftile0_harden : 1; /* [2] */ + u32 icg_en_ring_stftile0_harden : 1; /* [3] */ + u32 srst_req_cnb_stftile0_harden : 1; /* [4] */ + u32 srst_req_l2i_stftile0_harden : 1; /* [5] */ + u32 srst_req_mbist_stftile0_harden : 1; /* [6] */ + u32 srst_req_mtc_stftile0_harden : 1; /* [7] */ + u32 srst_req_qcm_stftile0_harden : 1; /* [8] */ + u32 srst_req_rep_stftile0_harden : 1; /* [9] */ + u32 srst_req_ring_stftile0_harden : 1; /* [10] */ + u32 srst_req_tiu_stftile0_harden : 1; /* [11] */ + u32 srst_req_tou_stftile0_harden : 1; /* [12] */ + u32 tile_sys_clk_sel_stftile0_harden : 1; /* [13] */ + u32 rsv_5 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_stftile0_harden_u; + +/* Define the union csr_crg_cfg_stftile1_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_qcm_stftile1_harden : 1; /* [0] */ + u32 icg_en_tile_stftile1_harden : 1; /* [1] */ + u32 icg_en_tile_div2_stftile1_harden : 1; /* [2] */ + u32 icg_en_ring_stftile1_harden : 1; /* [3] */ + u32 srst_req_cnb_stftile1_harden : 1; /* [4] */ + u32 srst_req_l2i_stftile1_harden : 1; /* [5] */ + u32 srst_req_mbist_stftile1_harden : 1; /* [6] */ + u32 srst_req_mtc_stftile1_harden : 1; /* [7] */ + u32 srst_req_qcm_stftile1_harden : 1; /* [8] */ + u32 srst_req_rep_stftile1_harden : 1; /* [9] */ + u32 srst_req_ring_stftile1_harden : 1; /* [10] */ + u32 srst_req_tiu_stftile1_harden : 1; /* [11] */ + u32 srst_req_tou_stftile1_harden : 1; /* [12] */ + u32 tile_sys_clk_sel_stftile1_harden : 1; /* [13] */ + u32 rsv_7 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_stftile1_harden_u; + +/* Define the union csr_crg_cfg_ipsurx_petx_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ring_ipsurx_petx_harden : 1; /* [0] */ + u32 icg_en_dp_network_ipsurx_petx_harden : 1; /* [1] */ + u32 srst_req_ring_ipsurx_petx_harden : 1; /* [2] */ + u32 srst_req_dp_network_ipsurx_petx_harden : 1; /* [3] */ + u32 rsv_9 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_ipsurx_petx_harden_u; + +/* Define the union csr_crg_cfg_ts_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ring_ts_harden : 1; /* [0] */ + u32 icg_en_ts_ts_harden : 1; /* [1] */ + u32 icg_en_cnb2apb_ts_harden : 1; /* [2] */ + u32 srst_req_ring_ts_harden : 1; /* [3] */ + u32 srst_req_ts_ts_harden : 1; /* [4] */ + u32 srst_req_cnb2apb_ts_harden : 1; /* [5] */ + u32 rsv_11 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_ts_harden_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_apb_chain_mag_fc_sds_harden : 1; /* [0] */ + u32 icg_en_mag_mag_fc_sds_harden : 1; /* [1] */ + u32 icg_en_mac_core_mag_fc_sds_harden : 1; /* [2] */ + u32 icg_en_mac_ptp_mag_fc_sds_harden : 1; /* [3] */ + u32 icg_en_an_lt_cfg_mag_fc_sds_harden : 1; /* [4] */ + u32 icg_en_led_mag_fc_sds_harden : 1; /* [5] */ + u32 icg_en_serdes6_mag_rx_su_mag_fc_sds_harden : 1; /* [6] */ + u32 icg_en_serdes7_mag_rx_su_mag_fc_sds_harden : 1; /* [7] */ + u32 icg_en_an_core_mag_fc_sds_harden : 8; /* [15:8] */ + u32 icg_en_serdes6_mclk_mag_fc_sds_harden : 1; /* [16] */ + u32 icg_en_serdes7_mclk_mag_fc_sds_harden : 1; /* [17] */ + u32 icg_en_fc_apb_mag_fc_sds_harden : 1; /* [18] */ + u32 icg_en_dp_com_mag_fc_sds_harden : 1; /* [19] */ + u32 icg_en_p01_rx_pma_mag_fc_sds_harden : 1; /* [20] */ + u32 icg_en_p23_rx_pma_mag_fc_sds_harden : 1; /* [21] */ + u32 rsv_13 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_0_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_apb_chain_mag_fc_sds_harden : 1; /* [0] */ + u32 srst_req_mag_mag_fc_sds_harden : 1; /* [1] */ + u32 srst_req_mac_core_mag_fc_sds_harden : 1; /* [2] */ + u32 srst_req_mac_t_mag_fc_sds_harden : 1; /* [3] */ + u32 srst_req_mac_ptp_mag_fc_sds_harden : 1; /* [4] */ + u32 srst_req_an_lt_cfg_mag_fc_sds_harden : 1; /* [5] */ + u32 srst_req_led_mag_fc_sds_harden : 1; /* [6] */ + u32 srst_req_mac_logic_mag_fc_sds_harden : 1; /* [7] */ + u32 srst_req_an_core_mag_fc_sds_harden : 8; /* [15:8] */ + u32 srst_req_fc_apb_mag_fc_sds_harden : 1; /* [16] */ + u32 srst_req_dp_com_mag_fc_sds_harden : 1; /* [17] */ + u32 srst_req_p01_rx_pma_mag_fc_sds_harden : 1; /* [18] */ + u32 srst_req_p23_rx_pma_mag_fc_sds_harden : 1; /* [19] */ + u32 rsv_15 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_1_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_serdes6_txo_mag_fc_sds_harden : 4; /* [3:0] */ + u32 icg_en_serdes7_txo_mag_fc_sds_harden : 4; /* [7:4] */ + u32 icg_en_serdes6_rxo_mag_fc_sds_harden : 4; /* [11:8] */ + u32 icg_en_serdes7_rxo_mag_fc_sds_harden : 4; /* [15:12] */ + u32 icg_en_serdes6_pma_tx_mag_fc_sds_harden : 4; /* [19:16] */ + u32 icg_en_serdes7_pma_tx_mag_fc_sds_harden : 4; /* [23:20] */ + u32 icg_en_serdes6_pma_rx_mag_fc_sds_harden : 4; /* [27:24] */ + u32 icg_en_serdes7_pma_rx_mag_fc_sds_harden : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_2_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_serdes6_spi_mag_fc_sds_harden : 4; /* [3:0] */ + u32 icg_en_serdes7_spi_mag_fc_sds_harden : 4; /* [7:4] */ + u32 icg_en_lt_spi_mag_fc_sds_harden : 8; /* [15:8] */ + u32 icg_en_serdes6_mac_rx_mag_fc_sds_harden : 8; /* [23:16] */ + u32 icg_en_serdes7_mac_rx_mag_fc_sds_harden : 4; /* [27:24] */ + u32 rsv_17 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_3_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_serdes6_an_rx_mag_fc_sds_harden : 4; /* [3:0] */ + u32 icg_en_serdes7_an_rx_mag_fc_sds_harden : 4; /* [7:4] */ + u32 icg_en_serdes6_lt_rx_mag_fc_sds_harden : 4; /* [11:8] */ + u32 icg_en_serdes7_lt_rx_mag_fc_sds_harden : 4; /* [15:12] */ + u32 icg_en_serdes6_mac_tx_mag_fc_sds_harden : 4; /* [19:16] */ + u32 icg_en_serdes7_mac_tx_mag_fc_sds_harden : 4; /* [23:20] */ + u32 icg_en_serdes6_an_tx_mag_fc_sds_harden : 4; /* [27:24] */ + u32 icg_en_serdes7_an_tx_mag_fc_sds_harden : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_4_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_serdes6_lt_tx_mag_fc_sds_harden : 4; /* [3:0] */ + u32 icg_en_serdes7_lt_tx_mag_fc_sds_harden : 4; /* [7:4] */ + u32 icg_en_serdes6_rxaux_mag_fc_sds_harden : 2; /* [9:8] */ + u32 icg_en_serdes7_rxaux_mag_fc_sds_harden : 2; /* [11:10] */ + u32 rsv_19 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_5_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_serdes6_pma_tx_mag_fc_sds_harden : 4; /* [3:0] */ + u32 srst_req_serdes7_pma_tx_mag_fc_sds_harden : 4; /* [7:4] */ + u32 srst_req_serdes6_pma_rx_mag_fc_sds_harden : 4; /* [11:8] */ + u32 srst_req_serdes7_pma_rx_mag_fc_sds_harden : 4; /* [15:12] */ + u32 srst_req_serdes6_spi_mag_fc_sds_harden : 4; /* [19:16] */ + u32 srst_req_serdes7_spi_mag_fc_sds_harden : 4; /* [23:20] */ + u32 srst_req_lt_spi_mag_fc_sds_harden : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_6_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_serdes6_mac_rx_mag_fc_sds_harden : 4; /* [3:0] */ + u32 srst_req_serdes7_mac_rx_mag_fc_sds_harden : 4; /* [7:4] */ + u32 srst_req_serdes6_an_rx_mag_fc_sds_harden : 4; /* [11:8] */ + u32 srst_req_serdes7_an_rx_mag_fc_sds_harden : 4; /* [15:12] */ + u32 srst_req_serdes6_lt_rx_mag_fc_sds_harden : 4; /* [19:16] */ + u32 srst_req_serdes7_lt_rx_mag_fc_sds_harden : 4; /* [23:20] */ + u32 srst_req_serdes6_mac_tx_mag_fc_sds_harden : 4; /* [27:24] */ + u32 srst_req_serdes7_mac_tx_mag_fc_sds_harden : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_7_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_serdes6_an_tx_mag_fc_sds_harden : 4; /* [3:0] */ + u32 srst_req_serdes7_an_tx_mag_fc_sds_harden : 4; /* [7:4] */ + u32 srst_req_serdes6_lt_tx_mag_fc_sds_harden : 4; /* [11:8] */ + u32 srst_req_serdes7_lt_tx_mag_fc_sds_harden : 4; /* [15:12] */ + u32 srst_req_an_rs_mag_fc_sds_harden : 8; /* [23:16] */ + u32 srst_req_lt_rs_mag_fc_sds_harden : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_8_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_phy_rx_logic_mag_fc_sds_harden : 8; /* [7:0] */ + u32 srst_req_port_rx_logic_mag_fc_sds_harden : 8; /* [15:8] */ + u32 srst_req_phy_tx_logic_mag_fc_sds_harden : 8; /* [23:16] */ + u32 srst_req_port_tx_logic_mag_fc_sds_harden : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_9_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 func_mbist_clk_sel_mag_fc_sds_harden : 1; /* [0] */ + u32 serdes6_pma_rx_su_clk_sel_mag_fc_sds_harden : 1; /* [1] */ + u32 serdes7_pma_rx_su_clk_sel_mag_fc_sds_harden : 1; /* [2] */ + u32 p01_pma_rx_clk_sel_mag_fc_sds_harden : 1; /* [3] */ + u32 p23_pma_rx_clk_sel_mag_fc_sds_harden : 1; /* [4] */ + u32 rsv_21 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_10_u; + +/* Define the union csr_crg_cfg_mag_fc_sds_harden_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 12; /* [11:0] */ + u32 probe_sds_mag_sel_mag_fc_sds_harden : 1; /* [12] */ + u32 icg_en_probe_mag_fc_sds_harden : 1; /* [13] */ + u32 probe_mode_mag_fc_sds_harden : 1; /* [14] */ + u32 sds_fc_mclk_icg_en_sel_mag_fc_sds_harden : 2; /* [16:15] */ + u32 mag_fc_hclk_clk_sel_mag_fc_sds_harden : 1; /* [17] */ + u32 rsv_25 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_mag_fc_sds_harden_11_u; + +/* Define the union csr_icg_en_mag_fc_sds_harden_p0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_fc_ua_p0_mag_fc_sds_harden : 1; /* [0] */ + u32 icg_en_dp_p0_mag_fc_sds_harden : 1; /* [1] */ + u32 icg_en_tts_pma_tx_p0_mag_fc_sds_harden : 1; /* [2] */ + u32 icg_en_fc_h_64b_tx_p0_mag_fc_sds_harden : 1; /* [3] */ + u32 icg_en_fc_l_8g_tx_p0_mag_fc_sds_harden : 1; /* [4] */ + u32 icg_en_fc_l_16g_tx_p0_mag_fc_sds_harden : 1; /* [5] */ + u32 icg_en_tts_tx_p0_mag_fc_sds_harden : 1; /* [6] */ + u32 icg_en_fc_h_tx_p0_mag_fc_sds_harden : 1; /* [7] */ + u32 icg_en_endec_tx_p0_mag_fc_sds_harden : 1; /* [8] */ + u32 icg_en_tts_pma_rx_p0_mag_fc_sds_harden : 1; /* [9] */ + u32 icg_en_fc_h_64b_rx_p0_mag_fc_sds_harden : 1; /* [10] */ + u32 icg_en_fc_l_8g_rx_p0_mag_fc_sds_harden : 1; /* [11] */ + u32 icg_en_fc_l_16g_rx_p0_mag_fc_sds_harden : 1; /* [12] */ + u32 icg_en_tts_rx_p0_mag_fc_sds_harden : 1; /* [13] */ + u32 icg_en_fc_h_rx_p0_mag_fc_sds_harden : 1; /* [14] */ + u32 icg_en_endec_rx_p0_mag_fc_sds_harden : 1; /* [15] */ + u32 icg_en_lpsm_p0_mag_fc_sds_harden : 1; /* [16] */ + u32 icg_en_bm8g_p0_mag_fc_sds_harden : 1; /* [17] */ + u32 icg_en_psm_p0_mag_fc_sds_harden : 1; /* [18] */ + u32 icg_en_bm_p0_mag_fc_sds_harden : 1; /* [19] */ + u32 fc_p0_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */ + u32 fc_p0_mclk_sel_mag_fc_sds_harden : 1; /* [21] */ + u32 fc_p0_bufman_p2p_mode_mag_fc_sds_harden : 1; /* [22] */ + u32 fc_p0_mode_mag_fc_sds_harden : 3; /* [25:23] */ + u32 rsv_27 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icg_en_mag_fc_sds_harden_p0_u; + +/* Define the union csr_srst_req_mag_fc_sds_harden_p0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_fc_ua_p0_mag_fc_sds_harden : 1; /* [0] */ + u32 srst_req_dp_p0_mag_fc_sds_harden : 1; /* [1] */ + u32 srst_req_tts_pma_tx_p0_mag_fc_sds_harden : 1; /* [2] */ + u32 srst_req_fc_h_64b_tx_p0_mag_fc_sds_harden : 1; /* [3] */ + u32 srst_req_fc_l_8g_tx_p0_mag_fc_sds_harden : 1; /* [4] */ + u32 srst_req_fc_l_16g_tx_p0_mag_fc_sds_harden : 1; /* [5] */ + u32 srst_req_tts_tx_p0_mag_fc_sds_harden : 1; /* [6] */ + u32 srst_req_fc_h_tx_p0_mag_fc_sds_harden : 1; /* [7] */ + u32 srst_req_endec_tx_p0_mag_fc_sds_harden : 1; /* [8] */ + u32 srst_req_tts_pma_rx_p0_mag_fc_sds_harden : 1; /* [9] */ + u32 srst_req_fc_h_64b_rx_p0_mag_fc_sds_harden : 1; /* [10] */ + u32 srst_req_fc_l_8g_rx_p0_mag_fc_sds_harden : 1; /* [11] */ + u32 srst_req_fc_l_16g_rx_p0_mag_fc_sds_harden : 1; /* [12] */ + u32 srst_req_tts_rx_p0_mag_fc_sds_harden : 1; /* [13] */ + u32 srst_req_fc_h_rx_p0_mag_fc_sds_harden : 1; /* [14] */ + u32 srst_req_endec_rx_p0_mag_fc_sds_harden : 1; /* [15] */ + u32 srst_req_lpsm_p0_mag_fc_sds_harden : 1; /* [16] */ + u32 srst_req_bm8g_p0_mag_fc_sds_harden : 1; /* [17] */ + u32 srst_req_psm_p0_mag_fc_sds_harden : 1; /* [18] */ + u32 srst_req_bm_p0_mag_fc_sds_harden : 1; /* [19] */ + u32 rsv_29 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_srst_req_mag_fc_sds_harden_p0_u; + +/* Define the union csr_icg_en_mag_fc_sds_harden_p1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_fc_ua_p1_mag_fc_sds_harden : 1; /* [0] */ + u32 icg_en_dp_p1_mag_fc_sds_harden : 1; /* [1] */ + u32 icg_en_tts_pma_tx_p1_mag_fc_sds_harden : 1; /* [2] */ + u32 icg_en_fc_h_64b_tx_p1_mag_fc_sds_harden : 1; /* [3] */ + u32 icg_en_fc_l_8g_tx_p1_mag_fc_sds_harden : 1; /* [4] */ + u32 icg_en_fc_l_16g_tx_p1_mag_fc_sds_harden : 1; /* [5] */ + u32 icg_en_tts_tx_p1_mag_fc_sds_harden : 1; /* [6] */ + u32 icg_en_fc_h_tx_p1_mag_fc_sds_harden : 1; /* [7] */ + u32 icg_en_endec_tx_p1_mag_fc_sds_harden : 1; /* [8] */ + u32 icg_en_tts_pma_rx_p1_mag_fc_sds_harden : 1; /* [9] */ + u32 icg_en_fc_h_64b_rx_p1_mag_fc_sds_harden : 1; /* [10] */ + u32 icg_en_fc_l_8g_rx_p1_mag_fc_sds_harden : 1; /* [11] */ + u32 icg_en_fc_l_16g_rx_p1_mag_fc_sds_harden : 1; /* [12] */ + u32 icg_en_tts_rx_p1_mag_fc_sds_harden : 1; /* [13] */ + u32 icg_en_fc_h_rx_p1_mag_fc_sds_harden : 1; /* [14] */ + u32 icg_en_endec_rx_p1_mag_fc_sds_harden : 1; /* [15] */ + u32 icg_en_lpsm_p1_mag_fc_sds_harden : 1; /* [16] */ + u32 icg_en_bm8g_p1_mag_fc_sds_harden : 1; /* [17] */ + u32 icg_en_psm_p1_mag_fc_sds_harden : 1; /* [18] */ + u32 icg_en_bm_p1_mag_fc_sds_harden : 1; /* [19] */ + u32 fc_p1_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */ + u32 fc_p1_mclk_sel_mag_fc_sds_harden : 1; /* [21] */ + u32 fc_p1_bufman_p2p_mode_mag_fc_sds_harden : 1; /* [22] */ + u32 fc_p1_mode_mag_fc_sds_harden : 3; /* [25:23] */ + u32 rsv_31 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icg_en_mag_fc_sds_harden_p1_u; + +/* Define the union csr_srst_req_mag_fc_sds_harden_p1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_fc_ua_p1_mag_fc_sds_harden : 1; /* [0] */ + u32 srst_req_dp_p1_mag_fc_sds_harden : 1; /* [1] */ + u32 srst_req_tts_pma_tx_p1_mag_fc_sds_harden : 1; /* [2] */ + u32 srst_req_fc_h_64b_tx_p1_mag_fc_sds_harden : 1; /* [3] */ + u32 srst_req_fc_l_8g_tx_p1_mag_fc_sds_harden : 1; /* [4] */ + u32 srst_req_fc_l_16g_tx_p1_mag_fc_sds_harden : 1; /* [5] */ + u32 srst_req_tts_tx_p1_mag_fc_sds_harden : 1; /* [6] */ + u32 srst_req_fc_h_tx_p1_mag_fc_sds_harden : 1; /* [7] */ + u32 srst_req_endec_tx_p1_mag_fc_sds_harden : 1; /* [8] */ + u32 srst_req_tts_pma_rx_p1_mag_fc_sds_harden : 1; /* [9] */ + u32 srst_req_fc_h_64b_rx_p1_mag_fc_sds_harden : 1; /* [10] */ + u32 srst_req_fc_l_8g_rx_p1_mag_fc_sds_harden : 1; /* [11] */ + u32 srst_req_fc_l_16g_rx_p1_mag_fc_sds_harden : 1; /* [12] */ + u32 srst_req_tts_rx_p1_mag_fc_sds_harden : 1; /* [13] */ + u32 srst_req_fc_h_rx_p1_mag_fc_sds_harden : 1; /* [14] */ + u32 srst_req_endec_rx_p1_mag_fc_sds_harden : 1; /* [15] */ + u32 srst_req_lpsm_p1_mag_fc_sds_harden : 1; /* [16] */ + u32 srst_req_bm8g_p1_mag_fc_sds_harden : 1; /* [17] */ + u32 srst_req_psm_p1_mag_fc_sds_harden : 1; /* [18] */ + u32 srst_req_bm_p1_mag_fc_sds_harden : 1; /* [19] */ + u32 rsv_33 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_srst_req_mag_fc_sds_harden_p1_u; + +/* Define the union csr_icg_en_mag_fc_sds_harden_p2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_fc_ua_p2_mag_fc_sds_harden : 1; /* [0] */ + u32 icg_en_dp_p2_mag_fc_sds_harden : 1; /* [1] */ + u32 icg_en_tts_pma_tx_p2_mag_fc_sds_harden : 1; /* [2] */ + u32 icg_en_fc_h_64b_tx_p2_mag_fc_sds_harden : 1; /* [3] */ + u32 icg_en_fc_l_8g_tx_p2_mag_fc_sds_harden : 1; /* [4] */ + u32 icg_en_fc_l_16g_tx_p2_mag_fc_sds_harden : 1; /* [5] */ + u32 icg_en_tts_tx_p2_mag_fc_sds_harden : 1; /* [6] */ + u32 icg_en_fc_h_tx_p2_mag_fc_sds_harden : 1; /* [7] */ + u32 icg_en_endec_tx_p2_mag_fc_sds_harden : 1; /* [8] */ + u32 icg_en_tts_pma_rx_p2_mag_fc_sds_harden : 1; /* [9] */ + u32 icg_en_fc_h_64b_rx_p2_mag_fc_sds_harden : 1; /* [10] */ + u32 icg_en_fc_l_8g_rx_p2_mag_fc_sds_harden : 1; /* [11] */ + u32 icg_en_fc_l_16g_rx_p2_mag_fc_sds_harden : 1; /* [12] */ + u32 icg_en_tts_rx_p2_mag_fc_sds_harden : 1; /* [13] */ + u32 icg_en_fc_h_rx_p2_mag_fc_sds_harden : 1; /* [14] */ + u32 icg_en_endec_rx_p2_mag_fc_sds_harden : 1; /* [15] */ + u32 icg_en_lpsm_p2_mag_fc_sds_harden : 1; /* [16] */ + u32 icg_en_bm8g_p2_mag_fc_sds_harden : 1; /* [17] */ + u32 icg_en_psm_p2_mag_fc_sds_harden : 1; /* [18] */ + u32 icg_en_bm_p2_mag_fc_sds_harden : 1; /* [19] */ + u32 fc_p2_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */ + u32 fc_p2_mclk_sel_mag_fc_sds_harden : 1; /* [21] */ + u32 fc_p2_bufman_p2p_mode_mag_fc_sds_harden : 1; /* [22] */ + u32 fc_p2_mode_mag_fc_sds_harden : 3; /* [25:23] */ + u32 rsv_35 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icg_en_mag_fc_sds_harden_p2_u; + +/* Define the union csr_srst_req_mag_fc_sds_harden_p2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_fc_ua_p2_mag_fc_sds_harden : 1; /* [0] */ + u32 srst_req_dp_p2_mag_fc_sds_harden : 1; /* [1] */ + u32 srst_req_tts_pma_tx_p2_mag_fc_sds_harden : 1; /* [2] */ + u32 srst_req_fc_h_64b_tx_p2_mag_fc_sds_harden : 1; /* [3] */ + u32 srst_req_fc_l_8g_tx_p2_mag_fc_sds_harden : 1; /* [4] */ + u32 srst_req_fc_l_16g_tx_p2_mag_fc_sds_harden : 1; /* [5] */ + u32 srst_req_tts_tx_p2_mag_fc_sds_harden : 1; /* [6] */ + u32 srst_req_fc_h_tx_p2_mag_fc_sds_harden : 1; /* [7] */ + u32 srst_req_endec_tx_p2_mag_fc_sds_harden : 1; /* [8] */ + u32 srst_req_tts_pma_rx_p2_mag_fc_sds_harden : 1; /* [9] */ + u32 srst_req_fc_h_64b_rx_p2_mag_fc_sds_harden : 1; /* [10] */ + u32 srst_req_fc_l_8g_rx_p2_mag_fc_sds_harden : 1; /* [11] */ + u32 srst_req_fc_l_16g_rx_p2_mag_fc_sds_harden : 1; /* [12] */ + u32 srst_req_tts_rx_p2_mag_fc_sds_harden : 1; /* [13] */ + u32 srst_req_fc_h_rx_p2_mag_fc_sds_harden : 1; /* [14] */ + u32 srst_req_endec_rx_p2_mag_fc_sds_harden : 1; /* [15] */ + u32 srst_req_lpsm_p2_mag_fc_sds_harden : 1; /* [16] */ + u32 srst_req_bm8g_p2_mag_fc_sds_harden : 1; /* [17] */ + u32 srst_req_psm_p2_mag_fc_sds_harden : 1; /* [18] */ + u32 srst_req_bm_p2_mag_fc_sds_harden : 1; /* [19] */ + u32 rsv_37 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_srst_req_mag_fc_sds_harden_p2_u; + +/* Define the union csr_icg_en_mag_fc_sds_harden_p3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_fc_ua_p3_mag_fc_sds_harden : 1; /* [0] */ + u32 icg_en_dp_p3_mag_fc_sds_harden : 1; /* [1] */ + u32 icg_en_tts_pma_tx_p3_mag_fc_sds_harden : 1; /* [2] */ + u32 icg_en_fc_h_64b_tx_p3_mag_fc_sds_harden : 1; /* [3] */ + u32 icg_en_fc_l_8g_tx_p3_mag_fc_sds_harden : 1; /* [4] */ + u32 icg_en_fc_l_16g_tx_p3_mag_fc_sds_harden : 1; /* [5] */ + u32 icg_en_tts_tx_p3_mag_fc_sds_harden : 1; /* [6] */ + u32 icg_en_fc_h_tx_p3_mag_fc_sds_harden : 1; /* [7] */ + u32 icg_en_endec_tx_p3_mag_fc_sds_harden : 1; /* [8] */ + u32 icg_en_tts_pma_rx_p3_mag_fc_sds_harden : 1; /* [9] */ + u32 icg_en_fc_h_64b_rx_p3_mag_fc_sds_harden : 1; /* [10] */ + u32 icg_en_fc_l_8g_rx_p3_mag_fc_sds_harden : 1; /* [11] */ + u32 icg_en_fc_l_16g_rx_p3_mag_fc_sds_harden : 1; /* [12] */ + u32 icg_en_tts_rx_p3_mag_fc_sds_harden : 1; /* [13] */ + u32 icg_en_fc_h_rx_p3_mag_fc_sds_harden : 1; /* [14] */ + u32 icg_en_endec_rx_p3_mag_fc_sds_harden : 1; /* [15] */ + u32 icg_en_lpsm_p3_mag_fc_sds_harden : 1; /* [16] */ + u32 icg_en_bm8g_p3_mag_fc_sds_harden : 1; /* [17] */ + u32 icg_en_psm_p3_mag_fc_sds_harden : 1; /* [18] */ + u32 icg_en_bm_p3_mag_fc_sds_harden : 1; /* [19] */ + u32 fc_p3_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */ + u32 fc_p3_mclk_sel_mag_fc_sds_harden : 1; /* [21] */ + u32 fc_p3_bufman_p2p_mode_mag_fc_sds_harden : 1; /* [22] */ + u32 fc_p3_mode_mag_fc_sds_harden : 3; /* [25:23] */ + u32 rsv_39 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icg_en_mag_fc_sds_harden_p3_u; + +/* Define the union csr_srst_req_mag_fc_sds_harden_p3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_fc_ua_p3_mag_fc_sds_harden : 1; /* [0] */ + u32 srst_req_dp_p3_mag_fc_sds_harden : 1; /* [1] */ + u32 srst_req_tts_pma_tx_p3_mag_fc_sds_harden : 1; /* [2] */ + u32 srst_req_fc_h_64b_tx_p3_mag_fc_sds_harden : 1; /* [3] */ + u32 srst_req_fc_l_8g_tx_p3_mag_fc_sds_harden : 1; /* [4] */ + u32 srst_req_fc_l_16g_tx_p3_mag_fc_sds_harden : 1; /* [5] */ + u32 srst_req_tts_tx_p3_mag_fc_sds_harden : 1; /* [6] */ + u32 srst_req_fc_h_tx_p3_mag_fc_sds_harden : 1; /* [7] */ + u32 srst_req_endec_tx_p3_mag_fc_sds_harden : 1; /* [8] */ + u32 srst_req_tts_pma_rx_p3_mag_fc_sds_harden : 1; /* [9] */ + u32 srst_req_fc_h_64b_rx_p3_mag_fc_sds_harden : 1; /* [10] */ + u32 srst_req_fc_l_8g_rx_p3_mag_fc_sds_harden : 1; /* [11] */ + u32 srst_req_fc_l_16g_rx_p3_mag_fc_sds_harden : 1; /* [12] */ + u32 srst_req_tts_rx_p3_mag_fc_sds_harden : 1; /* [13] */ + u32 srst_req_fc_h_rx_p3_mag_fc_sds_harden : 1; /* [14] */ + u32 srst_req_endec_rx_p3_mag_fc_sds_harden : 1; /* [15] */ + u32 srst_req_lpsm_p3_mag_fc_sds_harden : 1; /* [16] */ + u32 srst_req_bm8g_p3_mag_fc_sds_harden : 1; /* [17] */ + u32 srst_req_psm_p3_mag_fc_sds_harden : 1; /* [18] */ + u32 srst_req_bm_p3_mag_fc_sds_harden : 1; /* [19] */ + u32 rsv_41 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_srst_req_mag_fc_sds_harden_p3_u; + +/* Define the union csr_ring_sta_smf0_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_smf0_harden : 10; /* [9:0] */ + u32 qpc_rs_nd_pe_crdt_sta_smf0_harden : 10; /* [19:10] */ + u32 rsv_43 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_smf0_harden_u; + +/* Define the union csr_ring_sta_smf1_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_smf1_harden : 10; /* [9:0] */ + u32 qpc_rs_nd_pe_crdt_sta_smf1_harden : 10; /* [19:10] */ + u32 rsv_45 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_smf1_harden_u; + +/* Define the union csr_ring_sta_stftile0_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_stftile0_harden : 10; /* [9:0] */ + u32 qpc_rs_nd_pe_crdt_sta_stftile0_harden : 10; /* [19:10] */ + u32 rsv_47 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_stftile0_harden_u; + +/* Define the union csr_ring_sta_stftile1_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_stftile1_harden : 10; /* [9:0] */ + u32 qpc_rs_nd_pe_crdt_sta_stftile1_harden : 10; /* [19:10] */ + u32 rsv_49 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_stftile1_harden_u; + +/* Define the union csr_ring_sta_ipsurxpetx_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_ipsurx_petx_harden : 10; /* [9:0] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_ipsurxpetx_harden_u; + +/* Define the union csr_ring_sta_ts_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rs_nd_pe_crdt_sta_ts_harden : 10; /* [9:0] */ + u32 rsv_53 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_ts_harden_u; + +/* Define the union csr_smf0_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_iso_en_smf0_harden : 1; /* [0] */ + u32 smf_mtcmos_pwr_on_smf0_harden : 1; /* [1] */ + u32 srst_req_wol_por_smf0_harden : 1; /* [2] */ + u32 srst_req_wol_comb_smf0_harden : 1; /* [3] */ + u32 wol_rst_sel_smf0_harden : 1; /* [4] */ + u32 rsv_55 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf0_power_cfg_u; + +/* Define the union csr_smf0_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_mtcmos_pwr_ack_smf0_harden : 1; /* [0] */ + u32 rsv_57 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf0_power_ack_u; + +/* Define the union csr_smf1_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_iso_en_smf1_harden : 1; /* [0] */ + u32 smf_mtcmos_pwr_on_smf1_harden : 1; /* [1] */ + u32 srst_req_wol_por_smf1_harden : 1; /* [2] */ + u32 srst_req_wol_comb_smf1_harden : 1; /* [3] */ + u32 wol_rst_sel_smf1_harden : 1; /* [4] */ + u32 rsv_59 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf1_power_cfg_u; + +/* Define the union csr_smf1_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_mtcmos_pwr_ack_smf1_harden : 1; /* [0] */ + u32 rsv_61 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf1_power_ack_u; + +/* Define the union csr_ts_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ts_harden_iso_en : 1; /* [0] */ + u32 ts_harden_mtcmos_pwr_on : 1; /* [1] */ + u32 ts_harden_srst_req_wol_por : 1; /* [2] */ + u32 ts_harden_srst_req_wol_comb : 1; /* [3] */ + u32 ts_harden_wol_rst_sel : 1; /* [4] */ + u32 rsv_63 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ts_power_cfg_u; + +/* Define the union csr_ts_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ts_harden_pwr_ack : 1; /* [0] */ + u32 rsv_65 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ts_power_ack_u; + +/* Define the union csr_stftile0_power_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_pd0_wrap_iso_en_stftile0 : 1; /* [0] */ + u32 tile_pd0_wrap_mtcmos_pwr_on_stftile0 : 1; /* [1] */ + u32 tile_pd1_wrap_iso_en_stftile0 : 1; /* [2] */ + u32 tile_pd1_wrap_mtcmos_pwr_on_stftile0 : 1; /* [3] */ + u32 tile_pd2_wrap_iso_en_stftile0 : 1; /* [4] */ + u32 tile_pd2_wrap_mtcmos_pwr_on_stftile0 : 1; /* [5] */ + u32 tile_pd3_wrap_iso_en_stftile0 : 1; /* [6] */ + u32 tile_pd3_wrap_mtcmos_pwr_on_stftile0 : 1; /* [7] */ + u32 tile_pd4_wrap_iso_en_stftile0 : 1; /* [8] */ + u32 tile_pd4_wrap_mtcmos_pwr_on_stftile0 : 1; /* [9] */ + u32 tile_pd5_wrap_iso_en_stftile0 : 1; /* [10] */ + u32 tile_pd5_wrap_mtcmos_pwr_on_stftile0 : 1; /* [11] */ + u32 tile_qcm_bypass_stftile0 : 6; /* [17:12] */ + u32 rsv_67 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stftile0_power_cfg_0_u; + +/* Define the union csr_stftile0_power_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_wol_por_stftile0_qcm0 : 1; /* [0] */ + u32 srst_req_wol_comb_stftile0_qcm0 : 1; /* [1] */ + u32 wol_rst_sel_stftile0_qcm0 : 1; /* [2] */ + u32 srst_req_wol_por_stftile0_qcm1 : 1; /* [3] */ + u32 srst_req_wol_comb_stftile0_qcm1 : 1; /* [4] */ + u32 wol_rst_sel_stftile0_qcm1 : 1; /* [5] */ + u32 srst_req_wol_por_stftile0_qcm2 : 1; /* [6] */ + u32 srst_req_wol_comb_stftile0_qcm2 : 1; /* [7] */ + u32 wol_rst_sel_stftile0_qcm2 : 1; /* [8] */ + u32 srst_req_wol_por_stftile0_qcm3 : 1; /* [9] */ + u32 srst_req_wol_comb_stftile0_qcm3 : 1; /* [10] */ + u32 wol_rst_sel_stftile0_qcm3 : 1; /* [11] */ + u32 srst_req_wol_por_stftile0_qcm4 : 1; /* [12] */ + u32 srst_req_wol_comb_stftile0_qcm4 : 1; /* [13] */ + u32 wol_rst_sel_stftile0_qcm4 : 1; /* [14] */ + u32 srst_req_wol_por_stftile0_qcm5 : 1; /* [15] */ + u32 srst_req_wol_comb_stftile0_qcm5 : 1; /* [16] */ + u32 wol_rst_sel_stftile0_qcm5 : 1; /* [17] */ + u32 rsv_69 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stftile0_power_cfg_1_u; + +/* Define the union csr_stftile0_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_pd0_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [0] */ + u32 tile_pd1_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [1] */ + u32 tile_pd2_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [2] */ + u32 tile_pd3_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [3] */ + u32 tile_pd4_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [4] */ + u32 tile_pd5_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [5] */ + u32 rsv_71 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stftile0_power_ack_u; + +/* Define the union csr_stftile1_power_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_pd0_wrap_iso_en_stftile1 : 1; /* [0] */ + u32 tile_pd0_wrap_mtcmos_pwr_on_stftile1 : 1; /* [1] */ + u32 tile_pd1_wrap_iso_en_stftile1 : 1; /* [2] */ + u32 tile_pd1_wrap_mtcmos_pwr_on_stftile1 : 1; /* [3] */ + u32 tile_pd2_wrap_iso_en_stftile1 : 1; /* [4] */ + u32 tile_pd2_wrap_mtcmos_pwr_on_stftile1 : 1; /* [5] */ + u32 tile_pd3_wrap_iso_en_stftile1 : 1; /* [6] */ + u32 tile_pd3_wrap_mtcmos_pwr_on_stftile1 : 1; /* [7] */ + u32 tile_pd4_wrap_iso_en_stftile1 : 1; /* [8] */ + u32 tile_pd4_wrap_mtcmos_pwr_on_stftile1 : 1; /* [9] */ + u32 tile_pd5_wrap_iso_en_stftile1 : 1; /* [10] */ + u32 tile_pd5_wrap_mtcmos_pwr_on_stftile1 : 1; /* [11] */ + u32 tile_qcm_bypass_stftile1 : 6; /* [17:12] */ + u32 rsv_73 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stftile1_power_cfg_0_u; + +/* Define the union csr_stftile1_power_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_wol_por_stftile1_qcm0 : 1; /* [0] */ + u32 srst_req_wol_comb_stftile1_qcm0 : 1; /* [1] */ + u32 wol_rst_sel_stftile1_qcm0 : 1; /* [2] */ + u32 srst_req_wol_por_stftile1_qcm1 : 1; /* [3] */ + u32 srst_req_wol_comb_stftile1_qcm1 : 1; /* [4] */ + u32 wol_rst_sel_stftile1_qcm1 : 1; /* [5] */ + u32 srst_req_wol_por_stftile1_qcm2 : 1; /* [6] */ + u32 srst_req_wol_comb_stftile1_qcm2 : 1; /* [7] */ + u32 wol_rst_sel_stftile1_qcm2 : 1; /* [8] */ + u32 srst_req_wol_por_stftile1_qcm3 : 1; /* [9] */ + u32 srst_req_wol_comb_stftile1_qcm3 : 1; /* [10] */ + u32 wol_rst_sel_stftile1_qcm3 : 1; /* [11] */ + u32 srst_req_wol_por_stftile1_qcm4 : 1; /* [12] */ + u32 srst_req_wol_comb_stftile1_qcm4 : 1; /* [13] */ + u32 wol_rst_sel_stftile1_qcm4 : 1; /* [14] */ + u32 srst_req_wol_por_stftile1_qcm5 : 1; /* [15] */ + u32 srst_req_wol_comb_stftile1_qcm5 : 1; /* [16] */ + u32 wol_rst_sel_stftile1_qcm5 : 1; /* [17] */ + u32 rsv_75 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stftile1_power_cfg_1_u; + +/* Define the union csr_stftile1_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_pd0_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [0] */ + u32 tile_pd1_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [1] */ + u32 tile_pd2_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [2] */ + u32 tile_pd3_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [3] */ + u32 tile_pd4_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [4] */ + u32 tile_pd5_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [5] */ + u32 rsv_77 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stftile1_power_ack_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_crg_cfg_smf0_harden_u crg_cfg_smf0_harden; /* 0 */ + volatile csr_crg_cfg_smf1_harden_u crg_cfg_smf1_harden; /* 4 */ + volatile csr_crg_cfg_stftile0_harden_u crg_cfg_stftile0_harden; /* 8 */ + volatile csr_crg_cfg_stftile1_harden_u crg_cfg_stftile1_harden; /* C */ + volatile csr_crg_cfg_ipsurx_petx_harden_u crg_cfg_ipsurx_petx_harden; /* 10 */ + volatile csr_crg_cfg_ts_harden_u crg_cfg_ts_harden; /* 14 */ + volatile csr_crg_cfg_mag_fc_sds_harden_0_u crg_cfg_mag_fc_sds_harden_0; /* 18 */ + volatile csr_crg_cfg_mag_fc_sds_harden_1_u crg_cfg_mag_fc_sds_harden_1; /* 1C */ + volatile csr_crg_cfg_mag_fc_sds_harden_2_u crg_cfg_mag_fc_sds_harden_2; /* 20 */ + volatile csr_crg_cfg_mag_fc_sds_harden_3_u crg_cfg_mag_fc_sds_harden_3; /* 24 */ + volatile csr_crg_cfg_mag_fc_sds_harden_4_u crg_cfg_mag_fc_sds_harden_4; /* 28 */ + volatile csr_crg_cfg_mag_fc_sds_harden_5_u crg_cfg_mag_fc_sds_harden_5; /* 2C */ + volatile csr_crg_cfg_mag_fc_sds_harden_6_u crg_cfg_mag_fc_sds_harden_6; /* 30 */ + volatile csr_crg_cfg_mag_fc_sds_harden_7_u crg_cfg_mag_fc_sds_harden_7; /* 34 */ + volatile csr_crg_cfg_mag_fc_sds_harden_8_u crg_cfg_mag_fc_sds_harden_8; /* 38 */ + volatile csr_crg_cfg_mag_fc_sds_harden_9_u crg_cfg_mag_fc_sds_harden_9; /* 3C */ + volatile csr_crg_cfg_mag_fc_sds_harden_10_u crg_cfg_mag_fc_sds_harden_10; /* 40 */ + volatile csr_crg_cfg_mag_fc_sds_harden_11_u crg_cfg_mag_fc_sds_harden_11; /* 44 */ + volatile csr_icg_en_mag_fc_sds_harden_p0_u icg_en_mag_fc_sds_harden_p0; /* 48 */ + volatile csr_srst_req_mag_fc_sds_harden_p0_u srst_req_mag_fc_sds_harden_p0; /* 4C */ + volatile csr_icg_en_mag_fc_sds_harden_p1_u icg_en_mag_fc_sds_harden_p1; /* 50 */ + volatile csr_srst_req_mag_fc_sds_harden_p1_u srst_req_mag_fc_sds_harden_p1; /* 54 */ + volatile csr_icg_en_mag_fc_sds_harden_p2_u icg_en_mag_fc_sds_harden_p2; /* 58 */ + volatile csr_srst_req_mag_fc_sds_harden_p2_u srst_req_mag_fc_sds_harden_p2; /* 5C */ + volatile csr_icg_en_mag_fc_sds_harden_p3_u icg_en_mag_fc_sds_harden_p3; /* 60 */ + volatile csr_srst_req_mag_fc_sds_harden_p3_u srst_req_mag_fc_sds_harden_p3; /* 64 */ + volatile csr_ring_sta_smf0_harden_u ring_sta_smf0_harden; /* 68 */ + volatile csr_ring_sta_smf1_harden_u ring_sta_smf1_harden; /* 6C */ + volatile csr_ring_sta_stftile0_harden_u ring_sta_stftile0_harden; /* 70 */ + volatile csr_ring_sta_stftile1_harden_u ring_sta_stftile1_harden; /* 74 */ + volatile csr_ring_sta_ipsurxpetx_harden_u ring_sta_ipsurxpetx_harden; /* 78 */ + volatile csr_ring_sta_ts_harden_u ring_sta_ts_harden; /* 7C */ + volatile csr_smf0_power_cfg_u smf0_power_cfg; /* 80 */ + volatile csr_smf0_power_ack_u smf0_power_ack; /* 84 */ + volatile csr_smf1_power_cfg_u smf1_power_cfg; /* 88 */ + volatile csr_smf1_power_ack_u smf1_power_ack; /* 8C */ + volatile csr_ts_power_cfg_u ts_power_cfg; /* 90 */ + volatile csr_ts_power_ack_u ts_power_ack; /* 94 */ + volatile csr_stftile0_power_cfg_0_u stftile0_power_cfg_0; /* 98 */ + volatile csr_stftile0_power_cfg_1_u stftile0_power_cfg_1; /* 9C */ + volatile csr_stftile0_power_ack_u stftile0_power_ack; /* A0 */ + volatile csr_stftile1_power_cfg_0_u stftile1_power_cfg_0; /* A4 */ + volatile csr_stftile1_power_cfg_1_u stftile1_power_cfg_1; /* A8 */ + volatile csr_stftile1_power_ack_u stftile1_power_ack; /* AC */ +} S_smf0_harden_node_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smf0_harden_node_csr */ +extern volatile S_smf0_harden_node_csr_REGS_TYPE *gopsmf0_harden_node_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCRG_CFG_SMF0_HARDEN_icg_en_ring_smf0_harden(unsigned int uicg_en_ring_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_icg_en_smf_smf0_harden(unsigned int uicg_en_smf_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_icg_en_smf_div2_smf0_harden(unsigned int uicg_en_smf_div2_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_icg_en_virtio_core_smf0_harden(unsigned int uicg_en_virtio_core_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_icg_en_smeg_smf0_harden(unsigned int uicg_en_smeg_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_srst_req_ring_smf0_harden(unsigned int usrst_req_ring_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_srst_req_smf_smf0_harden(unsigned int usrst_req_smf_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_srst_req_virtio_core_smf0_harden(unsigned int usrst_req_virtio_core_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_srst_req_smf_div2_smf0_harden(unsigned int usrst_req_smf_div2_smf0_harden); +int iSetCRG_CFG_SMF0_HARDEN_srst_req_smeg_smf0_harden(unsigned int usrst_req_smeg_smf0_harden); +int iSetCRG_CFG_SMF1_HARDEN_icg_en_ring_smf1_harden(unsigned int uicg_en_ring_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_icg_en_smf_smf1_harden(unsigned int uicg_en_smf_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_icg_en_smf_div2_smf1_harden(unsigned int uicg_en_smf_div2_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_icg_en_virtio_core_smf1_harden(unsigned int uicg_en_virtio_core_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_icg_en_smeg_smf1_harden(unsigned int uicg_en_smeg_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_srst_req_ring_smf1_harden(unsigned int usrst_req_ring_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_srst_req_smf_smf1_harden(unsigned int usrst_req_smf_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_srst_req_virtio_core_smf1_harden(unsigned int usrst_req_virtio_core_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_srst_req_smf_div2_smf1_harden(unsigned int usrst_req_smf_div2_smf1_harden); +int iSetCRG_CFG_SMF1_HARDEN_srst_req_smeg_smf1_harden(unsigned int usrst_req_smeg_smf1_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_qcm_stftile0_harden(unsigned int uicg_en_qcm_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_tile_stftile0_harden(unsigned int uicg_en_tile_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_tile_div2_stftile0_harden(unsigned int uicg_en_tile_div2_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_ring_stftile0_harden(unsigned int uicg_en_ring_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_cnb_stftile0_harden(unsigned int usrst_req_cnb_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_l2i_stftile0_harden(unsigned int usrst_req_l2i_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_mbist_stftile0_harden(unsigned int usrst_req_mbist_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_mtc_stftile0_harden(unsigned int usrst_req_mtc_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_qcm_stftile0_harden(unsigned int usrst_req_qcm_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_rep_stftile0_harden(unsigned int usrst_req_rep_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_ring_stftile0_harden(unsigned int usrst_req_ring_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_tiu_stftile0_harden(unsigned int usrst_req_tiu_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_tou_stftile0_harden(unsigned int usrst_req_tou_stftile0_harden); +int iSetCRG_CFG_STFTILE0_HARDEN_tile_sys_clk_sel_stftile0_harden(unsigned int utile_sys_clk_sel_stftile0_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_qcm_stftile1_harden(unsigned int uicg_en_qcm_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_tile_stftile1_harden(unsigned int uicg_en_tile_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_tile_div2_stftile1_harden(unsigned int uicg_en_tile_div2_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_ring_stftile1_harden(unsigned int uicg_en_ring_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_cnb_stftile1_harden(unsigned int usrst_req_cnb_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_l2i_stftile1_harden(unsigned int usrst_req_l2i_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_mbist_stftile1_harden(unsigned int usrst_req_mbist_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_mtc_stftile1_harden(unsigned int usrst_req_mtc_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_qcm_stftile1_harden(unsigned int usrst_req_qcm_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_rep_stftile1_harden(unsigned int usrst_req_rep_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_ring_stftile1_harden(unsigned int usrst_req_ring_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_tiu_stftile1_harden(unsigned int usrst_req_tiu_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_tou_stftile1_harden(unsigned int usrst_req_tou_stftile1_harden); +int iSetCRG_CFG_STFTILE1_HARDEN_tile_sys_clk_sel_stftile1_harden(unsigned int utile_sys_clk_sel_stftile1_harden); +int iSetCRG_CFG_IPSURX_PETX_HARDEN_icg_en_ring_ipsurx_petx_harden(unsigned int uicg_en_ring_ipsurx_petx_harden); +int iSetCRG_CFG_IPSURX_PETX_HARDEN_icg_en_dp_network_ipsurx_petx_harden( + unsigned int uicg_en_dp_network_ipsurx_petx_harden); +int iSetCRG_CFG_IPSURX_PETX_HARDEN_srst_req_ring_ipsurx_petx_harden(unsigned int usrst_req_ring_ipsurx_petx_harden); +int iSetCRG_CFG_IPSURX_PETX_HARDEN_srst_req_dp_network_ipsurx_petx_harden( + unsigned int usrst_req_dp_network_ipsurx_petx_harden); +int iSetCRG_CFG_TS_HARDEN_icg_en_ring_ts_harden(unsigned int uicg_en_ring_ts_harden); +int iSetCRG_CFG_TS_HARDEN_icg_en_ts_ts_harden(unsigned int uicg_en_ts_ts_harden); +int iSetCRG_CFG_TS_HARDEN_icg_en_cnb2apb_ts_harden(unsigned int uicg_en_cnb2apb_ts_harden); +int iSetCRG_CFG_TS_HARDEN_srst_req_ring_ts_harden(unsigned int usrst_req_ring_ts_harden); +int iSetCRG_CFG_TS_HARDEN_srst_req_ts_ts_harden(unsigned int usrst_req_ts_ts_harden); +int iSetCRG_CFG_TS_HARDEN_srst_req_cnb2apb_ts_harden(unsigned int usrst_req_cnb2apb_ts_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_apb_chain_mag_fc_sds_harden( + unsigned int uicg_en_apb_chain_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_mag_mag_fc_sds_harden(unsigned int uicg_en_mag_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_mac_core_mag_fc_sds_harden(unsigned int uicg_en_mac_core_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_mac_ptp_mag_fc_sds_harden(unsigned int uicg_en_mac_ptp_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_an_lt_cfg_mag_fc_sds_harden( + unsigned int uicg_en_an_lt_cfg_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_led_mag_fc_sds_harden(unsigned int uicg_en_led_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes6_mag_rx_su_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_mag_rx_su_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes7_mag_rx_su_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_mag_rx_su_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_an_core_mag_fc_sds_harden(unsigned int uicg_en_an_core_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes6_mclk_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_mclk_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes7_mclk_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_mclk_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_fc_apb_mag_fc_sds_harden(unsigned int uicg_en_fc_apb_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_dp_com_mag_fc_sds_harden(unsigned int uicg_en_dp_com_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_p01_rx_pma_mag_fc_sds_harden( + unsigned int uicg_en_p01_rx_pma_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_p23_rx_pma_mag_fc_sds_harden( + unsigned int uicg_en_p23_rx_pma_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_apb_chain_mag_fc_sds_harden( + unsigned int usrst_req_apb_chain_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mag_mag_fc_sds_harden(unsigned int usrst_req_mag_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_core_mag_fc_sds_harden( + unsigned int usrst_req_mac_core_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_t_mag_fc_sds_harden(unsigned int usrst_req_mac_t_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_ptp_mag_fc_sds_harden( + unsigned int usrst_req_mac_ptp_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_an_lt_cfg_mag_fc_sds_harden( + unsigned int usrst_req_an_lt_cfg_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_led_mag_fc_sds_harden(unsigned int usrst_req_led_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_logic_mag_fc_sds_harden( + unsigned int usrst_req_mac_logic_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_an_core_mag_fc_sds_harden( + unsigned int usrst_req_an_core_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_fc_apb_mag_fc_sds_harden(unsigned int usrst_req_fc_apb_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_dp_com_mag_fc_sds_harden(unsigned int usrst_req_dp_com_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_p01_rx_pma_mag_fc_sds_harden( + unsigned int usrst_req_p01_rx_pma_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_p23_rx_pma_mag_fc_sds_harden( + unsigned int usrst_req_p23_rx_pma_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_txo_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_txo_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_txo_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_txo_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_rxo_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_rxo_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_rxo_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_rxo_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_pma_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_pma_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_pma_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_pma_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_pma_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_pma_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_pma_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_pma_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes6_spi_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_spi_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes7_spi_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_spi_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_lt_spi_mag_fc_sds_harden(unsigned int uicg_en_lt_spi_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes6_mac_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_mac_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes7_mac_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_mac_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_an_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_an_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_an_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_an_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_lt_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_lt_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_lt_rx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_lt_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_mac_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_mac_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_mac_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_mac_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_an_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_an_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_an_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_an_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes6_lt_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_lt_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes7_lt_tx_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_lt_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes6_rxaux_mag_fc_sds_harden( + unsigned int uicg_en_serdes6_rxaux_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes7_rxaux_mag_fc_sds_harden( + unsigned int uicg_en_serdes7_rxaux_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes6_pma_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_pma_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes7_pma_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_pma_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes6_pma_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_pma_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes7_pma_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_pma_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes6_spi_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_spi_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes7_spi_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_spi_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_lt_spi_mag_fc_sds_harden(unsigned int usrst_req_lt_spi_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_mac_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_mac_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_mac_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_mac_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_an_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_an_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_an_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_an_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_lt_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_lt_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_lt_rx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_lt_rx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_mac_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_mac_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_mac_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_mac_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes6_an_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_an_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes7_an_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_an_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes6_lt_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes6_lt_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes7_lt_tx_mag_fc_sds_harden( + unsigned int usrst_req_serdes7_lt_tx_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_an_rs_mag_fc_sds_harden(unsigned int usrst_req_an_rs_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_lt_rs_mag_fc_sds_harden(unsigned int usrst_req_lt_rs_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_phy_rx_logic_mag_fc_sds_harden( + unsigned int usrst_req_phy_rx_logic_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_port_rx_logic_mag_fc_sds_harden( + unsigned int usrst_req_port_rx_logic_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_phy_tx_logic_mag_fc_sds_harden( + unsigned int usrst_req_phy_tx_logic_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_port_tx_logic_mag_fc_sds_harden( + unsigned int usrst_req_port_tx_logic_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_func_mbist_clk_sel_mag_fc_sds_harden( + unsigned int ufunc_mbist_clk_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_serdes6_pma_rx_su_clk_sel_mag_fc_sds_harden( + unsigned int userdes6_pma_rx_su_clk_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_serdes7_pma_rx_su_clk_sel_mag_fc_sds_harden( + unsigned int userdes7_pma_rx_su_clk_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_p01_pma_rx_clk_sel_mag_fc_sds_harden( + unsigned int up01_pma_rx_clk_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_p23_pma_rx_clk_sel_mag_fc_sds_harden( + unsigned int up23_pma_rx_clk_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_probe_sds_mag_sel_mag_fc_sds_harden( + unsigned int uprobe_sds_mag_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_icg_en_probe_mag_fc_sds_harden(unsigned int uicg_en_probe_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_probe_mode_mag_fc_sds_harden(unsigned int uprobe_mode_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_sds_fc_mclk_icg_en_sel_mag_fc_sds_harden( + unsigned int usds_fc_mclk_icg_en_sel_mag_fc_sds_harden); +int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_mag_fc_hclk_clk_sel_mag_fc_sds_harden( + unsigned int umag_fc_hclk_clk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_ua_p0_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_dp_p0_mag_fc_sds_harden(unsigned int uicg_en_dp_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_pma_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_64b_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_8g_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_16g_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_tts_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_endec_tx_p0_mag_fc_sds_harden( + unsigned int uicg_en_endec_tx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_pma_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_64b_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_8g_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_16g_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_tts_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_endec_rx_p0_mag_fc_sds_harden( + unsigned int uicg_en_endec_rx_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_lpsm_p0_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_bm8g_p0_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_psm_p0_mag_fc_sds_harden(unsigned int uicg_en_psm_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_bm_p0_mag_fc_sds_harden(unsigned int uicg_en_bm_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_bufman_16g_clk_sel_mag_fc_sds_harden( + unsigned int ufc_p0_bufman_16g_clk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p0_mclk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_bufman_p2p_mode_mag_fc_sds_harden( + unsigned int ufc_p0_bufman_p2p_mode_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_mode_mag_fc_sds_harden(unsigned int ufc_p0_mode_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_ua_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_ua_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_dp_p0_mag_fc_sds_harden(unsigned int usrst_req_dp_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_pma_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_64b_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_8g_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_16g_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_tts_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_endec_tx_p0_mag_fc_sds_harden( + unsigned int usrst_req_endec_tx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_pma_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_64b_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_8g_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_16g_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_tts_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_endec_rx_p0_mag_fc_sds_harden( + unsigned int usrst_req_endec_rx_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_lpsm_p0_mag_fc_sds_harden( + unsigned int usrst_req_lpsm_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_bm8g_p0_mag_fc_sds_harden( + unsigned int usrst_req_bm8g_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_psm_p0_mag_fc_sds_harden( + unsigned int usrst_req_psm_p0_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_bm_p0_mag_fc_sds_harden(unsigned int usrst_req_bm_p0_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_ua_p1_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_dp_p1_mag_fc_sds_harden(unsigned int uicg_en_dp_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_pma_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_64b_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_8g_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_16g_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_tts_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_endec_tx_p1_mag_fc_sds_harden( + unsigned int uicg_en_endec_tx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_pma_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_64b_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_8g_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_16g_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_tts_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_endec_rx_p1_mag_fc_sds_harden( + unsigned int uicg_en_endec_rx_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_lpsm_p1_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_bm8g_p1_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_psm_p1_mag_fc_sds_harden(unsigned int uicg_en_psm_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_bm_p1_mag_fc_sds_harden(unsigned int uicg_en_bm_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_bufman_16g_clk_sel_mag_fc_sds_harden( + unsigned int ufc_p1_bufman_16g_clk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p1_mclk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_bufman_p2p_mode_mag_fc_sds_harden( + unsigned int ufc_p1_bufman_p2p_mode_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_mode_mag_fc_sds_harden(unsigned int ufc_p1_mode_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_ua_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_ua_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_dp_p1_mag_fc_sds_harden(unsigned int usrst_req_dp_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_pma_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_64b_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_8g_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_16g_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_tts_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_endec_tx_p1_mag_fc_sds_harden( + unsigned int usrst_req_endec_tx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_pma_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_64b_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_8g_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_16g_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_tts_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_endec_rx_p1_mag_fc_sds_harden( + unsigned int usrst_req_endec_rx_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_lpsm_p1_mag_fc_sds_harden( + unsigned int usrst_req_lpsm_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_bm8g_p1_mag_fc_sds_harden( + unsigned int usrst_req_bm8g_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_psm_p1_mag_fc_sds_harden( + unsigned int usrst_req_psm_p1_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_bm_p1_mag_fc_sds_harden(unsigned int usrst_req_bm_p1_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_ua_p2_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_dp_p2_mag_fc_sds_harden(unsigned int uicg_en_dp_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_pma_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_64b_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_8g_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_16g_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_tts_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_endec_tx_p2_mag_fc_sds_harden( + unsigned int uicg_en_endec_tx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_pma_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_64b_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_8g_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_16g_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_tts_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_endec_rx_p2_mag_fc_sds_harden( + unsigned int uicg_en_endec_rx_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_lpsm_p2_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_bm8g_p2_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_psm_p2_mag_fc_sds_harden(unsigned int uicg_en_psm_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_bm_p2_mag_fc_sds_harden(unsigned int uicg_en_bm_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_bufman_16g_clk_sel_mag_fc_sds_harden( + unsigned int ufc_p2_bufman_16g_clk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p2_mclk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_bufman_p2p_mode_mag_fc_sds_harden( + unsigned int ufc_p2_bufman_p2p_mode_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_mode_mag_fc_sds_harden(unsigned int ufc_p2_mode_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_ua_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_ua_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_dp_p2_mag_fc_sds_harden(unsigned int usrst_req_dp_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_pma_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_64b_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_8g_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_16g_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_tts_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_endec_tx_p2_mag_fc_sds_harden( + unsigned int usrst_req_endec_tx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_pma_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_64b_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_8g_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_16g_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_tts_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_endec_rx_p2_mag_fc_sds_harden( + unsigned int usrst_req_endec_rx_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_lpsm_p2_mag_fc_sds_harden( + unsigned int usrst_req_lpsm_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_bm8g_p2_mag_fc_sds_harden( + unsigned int usrst_req_bm8g_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_psm_p2_mag_fc_sds_harden( + unsigned int usrst_req_psm_p2_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_bm_p2_mag_fc_sds_harden(unsigned int usrst_req_bm_p2_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_ua_p3_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_dp_p3_mag_fc_sds_harden(unsigned int uicg_en_dp_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_pma_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_64b_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_8g_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_16g_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_tts_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_endec_tx_p3_mag_fc_sds_harden( + unsigned int uicg_en_endec_tx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_pma_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_tts_pma_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_64b_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_64b_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_8g_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_8g_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_16g_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_l_16g_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_tts_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_fc_h_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_endec_rx_p3_mag_fc_sds_harden( + unsigned int uicg_en_endec_rx_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_lpsm_p3_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_bm8g_p3_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_psm_p3_mag_fc_sds_harden(unsigned int uicg_en_psm_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_bm_p3_mag_fc_sds_harden(unsigned int uicg_en_bm_p3_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_bufman_16g_clk_sel_mag_fc_sds_harden( + unsigned int ufc_p3_bufman_16g_clk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p3_mclk_sel_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_bufman_p2p_mode_mag_fc_sds_harden( + unsigned int ufc_p3_bufman_p2p_mode_mag_fc_sds_harden); +int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_mode_mag_fc_sds_harden(unsigned int ufc_p3_mode_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_ua_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_ua_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_dp_p3_mag_fc_sds_harden(unsigned int usrst_req_dp_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_pma_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_64b_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_8g_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_16g_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_tts_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_endec_tx_p3_mag_fc_sds_harden( + unsigned int usrst_req_endec_tx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_pma_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_tts_pma_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_64b_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_64b_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_8g_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_8g_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_16g_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_l_16g_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_tts_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_fc_h_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_endec_rx_p3_mag_fc_sds_harden( + unsigned int usrst_req_endec_rx_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_lpsm_p3_mag_fc_sds_harden( + unsigned int usrst_req_lpsm_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_bm8g_p3_mag_fc_sds_harden( + unsigned int usrst_req_bm8g_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_psm_p3_mag_fc_sds_harden( + unsigned int usrst_req_psm_p3_mag_fc_sds_harden); +int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_bm_p3_mag_fc_sds_harden(unsigned int usrst_req_bm_p3_mag_fc_sds_harden); +int iSetRING_STA_SMF0_HARDEN_rs_nd_pe_crdt_sta_smf0_harden(unsigned int urs_nd_pe_crdt_sta_smf0_harden); +int iSetRING_STA_SMF0_HARDEN_qpc_rs_nd_pe_crdt_sta_smf0_harden(unsigned int uqpc_rs_nd_pe_crdt_sta_smf0_harden); +int iSetRING_STA_SMF1_HARDEN_rs_nd_pe_crdt_sta_smf1_harden(unsigned int urs_nd_pe_crdt_sta_smf1_harden); +int iSetRING_STA_SMF1_HARDEN_qpc_rs_nd_pe_crdt_sta_smf1_harden(unsigned int uqpc_rs_nd_pe_crdt_sta_smf1_harden); +int iSetRING_STA_STFTILE0_HARDEN_rs_nd_pe_crdt_sta_stftile0_harden(unsigned int urs_nd_pe_crdt_sta_stftile0_harden); +int iSetRING_STA_STFTILE0_HARDEN_qpc_rs_nd_pe_crdt_sta_stftile0_harden( + unsigned int uqpc_rs_nd_pe_crdt_sta_stftile0_harden); +int iSetRING_STA_STFTILE1_HARDEN_rs_nd_pe_crdt_sta_stftile1_harden(unsigned int urs_nd_pe_crdt_sta_stftile1_harden); +int iSetRING_STA_STFTILE1_HARDEN_qpc_rs_nd_pe_crdt_sta_stftile1_harden( + unsigned int uqpc_rs_nd_pe_crdt_sta_stftile1_harden); +int iSetRING_STA_IPSURXPETX_HARDEN_rs_nd_pe_crdt_sta_ipsurx_petx_harden( + unsigned int urs_nd_pe_crdt_sta_ipsurx_petx_harden); +int iSetRING_STA_TS_HARDEN_rs_nd_pe_crdt_sta_ts_harden(unsigned int urs_nd_pe_crdt_sta_ts_harden); +int iSetSMF0_POWER_CFG_smf_iso_en_smf0_harden(unsigned int usmf_iso_en_smf0_harden); +int iSetSMF0_POWER_CFG_smf_mtcmos_pwr_on_smf0_harden(unsigned int usmf_mtcmos_pwr_on_smf0_harden); +int iSetSMF0_POWER_CFG_srst_req_wol_por_smf0_harden(unsigned int usrst_req_wol_por_smf0_harden); +int iSetSMF0_POWER_CFG_srst_req_wol_comb_smf0_harden(unsigned int usrst_req_wol_comb_smf0_harden); +int iSetSMF0_POWER_CFG_wol_rst_sel_smf0_harden(unsigned int uwol_rst_sel_smf0_harden); +int iSetSMF0_POWER_ACK_smf_mtcmos_pwr_ack_smf0_harden(unsigned int usmf_mtcmos_pwr_ack_smf0_harden); +int iSetSMF1_POWER_CFG_smf_iso_en_smf1_harden(unsigned int usmf_iso_en_smf1_harden); +int iSetSMF1_POWER_CFG_smf_mtcmos_pwr_on_smf1_harden(unsigned int usmf_mtcmos_pwr_on_smf1_harden); +int iSetSMF1_POWER_CFG_srst_req_wol_por_smf1_harden(unsigned int usrst_req_wol_por_smf1_harden); +int iSetSMF1_POWER_CFG_srst_req_wol_comb_smf1_harden(unsigned int usrst_req_wol_comb_smf1_harden); +int iSetSMF1_POWER_CFG_wol_rst_sel_smf1_harden(unsigned int uwol_rst_sel_smf1_harden); +int iSetSMF1_POWER_ACK_smf_mtcmos_pwr_ack_smf1_harden(unsigned int usmf_mtcmos_pwr_ack_smf1_harden); +int iSetTS_POWER_CFG_ts_harden_iso_en(unsigned int uts_harden_iso_en); +int iSetTS_POWER_CFG_ts_harden_mtcmos_pwr_on(unsigned int uts_harden_mtcmos_pwr_on); +int iSetTS_POWER_CFG_ts_harden_srst_req_wol_por(unsigned int uts_harden_srst_req_wol_por); +int iSetTS_POWER_CFG_ts_harden_srst_req_wol_comb(unsigned int uts_harden_srst_req_wol_comb); +int iSetTS_POWER_CFG_ts_harden_wol_rst_sel(unsigned int uts_harden_wol_rst_sel); +int iSetTS_POWER_ACK_ts_harden_pwr_ack(unsigned int uts_harden_pwr_ack); +int iSetSTFTILE0_POWER_CFG_0_tile_pd0_wrap_iso_en_stftile0(unsigned int utile_pd0_wrap_iso_en_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd0_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd0_wrap_mtcmos_pwr_on_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd1_wrap_iso_en_stftile0(unsigned int utile_pd1_wrap_iso_en_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd1_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd1_wrap_mtcmos_pwr_on_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd2_wrap_iso_en_stftile0(unsigned int utile_pd2_wrap_iso_en_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd2_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd2_wrap_mtcmos_pwr_on_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd3_wrap_iso_en_stftile0(unsigned int utile_pd3_wrap_iso_en_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd3_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd3_wrap_mtcmos_pwr_on_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd4_wrap_iso_en_stftile0(unsigned int utile_pd4_wrap_iso_en_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd4_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd4_wrap_mtcmos_pwr_on_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd5_wrap_iso_en_stftile0(unsigned int utile_pd5_wrap_iso_en_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_pd5_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd5_wrap_mtcmos_pwr_on_stftile0); +int iSetSTFTILE0_POWER_CFG_0_tile_qcm_bypass_stftile0(unsigned int utile_qcm_bypass_stftile0); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm0(unsigned int usrst_req_wol_por_stftile0_qcm0); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm0(unsigned int usrst_req_wol_comb_stftile0_qcm0); +int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm0(unsigned int uwol_rst_sel_stftile0_qcm0); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm1(unsigned int usrst_req_wol_por_stftile0_qcm1); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm1(unsigned int usrst_req_wol_comb_stftile0_qcm1); +int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm1(unsigned int uwol_rst_sel_stftile0_qcm1); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm2(unsigned int usrst_req_wol_por_stftile0_qcm2); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm2(unsigned int usrst_req_wol_comb_stftile0_qcm2); +int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm2(unsigned int uwol_rst_sel_stftile0_qcm2); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm3(unsigned int usrst_req_wol_por_stftile0_qcm3); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm3(unsigned int usrst_req_wol_comb_stftile0_qcm3); +int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm3(unsigned int uwol_rst_sel_stftile0_qcm3); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm4(unsigned int usrst_req_wol_por_stftile0_qcm4); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm4(unsigned int usrst_req_wol_comb_stftile0_qcm4); +int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm4(unsigned int uwol_rst_sel_stftile0_qcm4); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm5(unsigned int usrst_req_wol_por_stftile0_qcm5); +int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm5(unsigned int usrst_req_wol_comb_stftile0_qcm5); +int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm5(unsigned int uwol_rst_sel_stftile0_qcm5); +int iSetSTFTILE0_POWER_ACK_tile_pd0_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd0_wrap_mtcmos_pwr_ack_stftile0); +int iSetSTFTILE0_POWER_ACK_tile_pd1_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd1_wrap_mtcmos_pwr_ack_stftile0); +int iSetSTFTILE0_POWER_ACK_tile_pd2_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd2_wrap_mtcmos_pwr_ack_stftile0); +int iSetSTFTILE0_POWER_ACK_tile_pd3_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd3_wrap_mtcmos_pwr_ack_stftile0); +int iSetSTFTILE0_POWER_ACK_tile_pd4_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd4_wrap_mtcmos_pwr_ack_stftile0); +int iSetSTFTILE0_POWER_ACK_tile_pd5_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd5_wrap_mtcmos_pwr_ack_stftile0); +int iSetSTFTILE1_POWER_CFG_0_tile_pd0_wrap_iso_en_stftile1(unsigned int utile_pd0_wrap_iso_en_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd0_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd0_wrap_mtcmos_pwr_on_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd1_wrap_iso_en_stftile1(unsigned int utile_pd1_wrap_iso_en_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd1_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd1_wrap_mtcmos_pwr_on_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd2_wrap_iso_en_stftile1(unsigned int utile_pd2_wrap_iso_en_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd2_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd2_wrap_mtcmos_pwr_on_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd3_wrap_iso_en_stftile1(unsigned int utile_pd3_wrap_iso_en_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd3_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd3_wrap_mtcmos_pwr_on_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd4_wrap_iso_en_stftile1(unsigned int utile_pd4_wrap_iso_en_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd4_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd4_wrap_mtcmos_pwr_on_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd5_wrap_iso_en_stftile1(unsigned int utile_pd5_wrap_iso_en_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_pd5_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd5_wrap_mtcmos_pwr_on_stftile1); +int iSetSTFTILE1_POWER_CFG_0_tile_qcm_bypass_stftile1(unsigned int utile_qcm_bypass_stftile1); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm0(unsigned int usrst_req_wol_por_stftile1_qcm0); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm0(unsigned int usrst_req_wol_comb_stftile1_qcm0); +int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm0(unsigned int uwol_rst_sel_stftile1_qcm0); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm1(unsigned int usrst_req_wol_por_stftile1_qcm1); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm1(unsigned int usrst_req_wol_comb_stftile1_qcm1); +int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm1(unsigned int uwol_rst_sel_stftile1_qcm1); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm2(unsigned int usrst_req_wol_por_stftile1_qcm2); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm2(unsigned int usrst_req_wol_comb_stftile1_qcm2); +int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm2(unsigned int uwol_rst_sel_stftile1_qcm2); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm3(unsigned int usrst_req_wol_por_stftile1_qcm3); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm3(unsigned int usrst_req_wol_comb_stftile1_qcm3); +int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm3(unsigned int uwol_rst_sel_stftile1_qcm3); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm4(unsigned int usrst_req_wol_por_stftile1_qcm4); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm4(unsigned int usrst_req_wol_comb_stftile1_qcm4); +int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm4(unsigned int uwol_rst_sel_stftile1_qcm4); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm5(unsigned int usrst_req_wol_por_stftile1_qcm5); +int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm5(unsigned int usrst_req_wol_comb_stftile1_qcm5); +int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm5(unsigned int uwol_rst_sel_stftile1_qcm5); +int iSetSTFTILE1_POWER_ACK_tile_pd0_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd0_wrap_mtcmos_pwr_ack_stftile1); +int iSetSTFTILE1_POWER_ACK_tile_pd1_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd1_wrap_mtcmos_pwr_ack_stftile1); +int iSetSTFTILE1_POWER_ACK_tile_pd2_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd2_wrap_mtcmos_pwr_ack_stftile1); +int iSetSTFTILE1_POWER_ACK_tile_pd3_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd3_wrap_mtcmos_pwr_ack_stftile1); +int iSetSTFTILE1_POWER_ACK_tile_pd4_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd4_wrap_mtcmos_pwr_ack_stftile1); +int iSetSTFTILE1_POWER_ACK_tile_pd5_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd5_wrap_mtcmos_pwr_ack_stftile1); + + +#endif // SMF0_HARDEN_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/smf0_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/smf0_harden_reg_offset.h new file mode 100644 index 000000000..d343930c2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/smf0_harden_reg_offset.h @@ -0,0 +1,69 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : smf0_harden_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/12/25 10:33:43 Create file +// ****************************************************************************** + +#ifndef SMF0_HARDEN_REG_OFFSET_H +#define SMF0_HARDEN_REG_OFFSET_H + +/* SMF0_HARDEN_NODE_CSR Base address of Module's Register */ +#define CSR_SMF0_HARDEN_NODE_CSR_BASE (0x21F10000) + +/******************************************************************************/ +/* SMF0_HARDEN_NODE_CSR Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_SMF0_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x0) /* SMF0_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_SMF1_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x4) /* SMF1_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_STFTILE0_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x8) /* STFTILE0_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_STFTILE1_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0xC) /* STFTILE1_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_IPSURX_PETX_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x10) /* IPSURX_PETX_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_TS_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x14) /* TS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_0_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x18) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_1_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x1C) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_2_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x20) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_3_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x24) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_4_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x28) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_5_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x2C) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_6_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x30) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_7_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x34) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_8_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x38) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_9_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x3C) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_10_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x40) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_CRG_CFG_MAG_FC_SDS_HARDEN_11_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x44) /* MAG_FC_SDS_HARDEN CRG的控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_ICG_EN_MAG_FC_SDS_HARDEN_P0_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x48) /* FC PORT0 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_SRST_REQ_MAG_FC_SDS_HARDEN_P0_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x4C) /* FC PORT0 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_ICG_EN_MAG_FC_SDS_HARDEN_P1_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x50) /* FC PORT1 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_SRST_REQ_MAG_FC_SDS_HARDEN_P1_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x54) /* FC PORT1 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_ICG_EN_MAG_FC_SDS_HARDEN_P2_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x58) /* FC PORT2 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_SRST_REQ_MAG_FC_SDS_HARDEN_P2_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x5C) /* FC PORT2 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_ICG_EN_MAG_FC_SDS_HARDEN_P3_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x60) /* FC PORT3 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_SRST_REQ_MAG_FC_SDS_HARDEN_P3_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x64) /* FC PORT3 cfg */ +#define CSR_SMF0_HARDEN_NODE_CSR_RING_STA_SMF0_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x68) /* RING_CRDT_STA */ +#define CSR_SMF0_HARDEN_NODE_CSR_RING_STA_SMF1_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x6C) /* RING_CRDT_STA */ +#define CSR_SMF0_HARDEN_NODE_CSR_RING_STA_STFTILE0_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x70) /* RING_CRDT_STA */ +#define CSR_SMF0_HARDEN_NODE_CSR_RING_STA_STFTILE1_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x74) /* RING_CRDT_STA */ +#define CSR_SMF0_HARDEN_NODE_CSR_RING_STA_IPSURXPETX_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x78) /* RING_CRDT_STA */ +#define CSR_SMF0_HARDEN_NODE_CSR_RING_STA_TS_HARDEN_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x7C) /* RING_CRDT_STA */ +#define CSR_SMF0_HARDEN_NODE_CSR_SMF0_POWER_CFG_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x80) /* SMF0 power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_SMF0_POWER_ACK_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x84) /* SMF0 power ACK状态寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_SMF1_POWER_CFG_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x88) /* SMF1 power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_SMF1_POWER_ACK_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x8C) /* SMF1 power ACK状态寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_TS_POWER_CFG_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x90) /* TS power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_TS_POWER_ACK_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x94) /* TS power ACK状态寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_STFTILE0_POWER_CFG_0_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x98) /* STFTILE0 power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_STFTILE0_POWER_CFG_1_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0x9C) /* STFTILE0 power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_STFTILE0_POWER_ACK_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0xA0) /* STFTILE0 power ACK状态寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_STFTILE1_POWER_CFG_0_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0xA4) /* STFTILE1 power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_STFTILE1_POWER_CFG_1_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0xA8) /* STFTILE1 power控制寄存器 */ +#define CSR_SMF0_HARDEN_NODE_CSR_STFTILE1_POWER_ACK_REG (CSR_SMF0_HARDEN_NODE_CSR_BASE + 0xAC) /* STFTILE1 power ACK状态寄存器 */ + +#endif // SMF0_HARDEN_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/stlqu_harden_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/stlqu_harden_c_union_define.h new file mode 100644 index 000000000..1b4082587 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/stlqu_harden_c_union_define.h @@ -0,0 +1,662 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stlqu_harden_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/07 21:45:40 Create file +// ****************************************************************************** + +#ifndef STLQU_HARDEN_C_UNION_DEFINE_H +#define STLQU_HARDEN_C_UNION_DEFINE_H + +/* Define the union csr_crg_cfg_stlqu_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ring_stlqu_harden : 2; /* [1:0] */ + u32 icg_en_cp_stlqu_harden : 1; /* [2] */ + u32 srst_req_ring_stlqu_harden : 2; /* [4:3] */ + u32 srst_req_grs_ring_stlqu_harden : 1; /* [5] */ + u32 srst_req_lrs_ring_stlqu_harden : 1; /* [6] */ + u32 srst_req_cp_stlqu_harden : 1; /* [7] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crg_cfg_stlqu_harden_u; + +/* Define the union csr_rst_cfg_sml0_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_sml_sml0_harden : 1; /* [0] */ + u32 icg_en_sml_div2_sml0_harden : 1; /* [1] */ + u32 icg_en_smeg_sml0_harden : 1; /* [2] */ + u32 icg_en_ring_sml0_harden : 1; /* [3] */ + u32 srst_req_sml_sml0_harden : 1; /* [4] */ + u32 srst_req_sml_div2_sml0_harden : 1; /* [5] */ + u32 srst_req_smeg_sml0_harden : 1; /* [6] */ + u32 srst_req_ring_sml0_harden : 1; /* [7] */ + u32 rsv_1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_sml0_harden_u; + +/* Define the union csr_rst_cfg_sml1_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_sml_sml1_harden : 1; /* [0] */ + u32 icg_en_sml_div2_sml1_harden : 1; /* [1] */ + u32 icg_en_smeg_sml1_harden : 1; /* [2] */ + u32 icg_en_ring_sml1_harden : 1; /* [3] */ + u32 srst_req_sml_sml1_harden : 1; /* [4] */ + u32 srst_req_sml_div2_sml1_harden : 1; /* [5] */ + u32 srst_req_smeg_sml1_harden : 1; /* [6] */ + u32 srst_req_ring_sml1_harden : 1; /* [7] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_cfg_sml1_harden_u; + +/* Define the union csr_ring_sta_sml0_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml0_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_3 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_sml0_harden_u; + +/* Define the union csr_ring_sta_sml1_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml1_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_sml1_harden_u; + +/* Define the union csr_ring_sta_stlqu_harden_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlqu_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_5 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ring_sta_stlqu_harden_u; + +/* Define the union csr_rst_comb_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_sft_rstn_enable : 1; /* [0] */ + u32 glb_srst_req : 1; /* [1] */ + u32 rsv_6 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_comb_cfg_0_u; + +/* Define the union csr_rst_comb_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 time_wait_efuse_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_comb_cfg_1_u; + +/* Define the union csr_rst_comb_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_bypass_icg_en_pll : 1; /* [0] */ + u32 srst_req_efuse_membst : 12; /* [12:1] */ + u32 rsv_7 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_comb_cfg_2_u; + +/* Define the union csr_pll0_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_cfg0 : 16; /* [15:0] */ + u32 pll0_cfg1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_0_u; + +/* Define the union csr_pll0_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_cfg2 : 16; /* [15:0] */ + u32 pll0_cfg3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_1_u; + +/* Define the union csr_pll0_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_cfg4 : 16; /* [15:0] */ + u32 pll0_cfg5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_2_u; + +/* Define the union csr_pll0_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_cfg6 : 16; /* [15:0] */ + u32 pll0_cfg7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_3_u; + +/* Define the union csr_pll0_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_cfg8 : 16; /* [15:0] */ + u32 pll0_cfg9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_4_u; + +/* Define the union csr_pll0_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_cfg10 : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_5_u; + +/* Define the union csr_pll0_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_pllfctrl0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_6_u; + +/* Define the union csr_pll0_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_pllfctrl1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_7_u; + +/* Define the union csr_pll0_cfg_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_bypass_external_n : 1; /* [0] */ + u32 pll0_peri_mode : 1; /* [1] */ + u32 dll_en_pll0 : 1; /* [2] */ + u32 probe_mode_pll0 : 1; /* [3] */ + u32 icg_en_probe_pll0 : 1; /* [4] */ + u32 rsv_9 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_cfg_8_u; + +/* Define the union csr_pll0_state_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_state0 : 16; /* [15:0] */ + u32 pll0_state1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_state_0_u; + +/* Define the union csr_pll0_state_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_lock : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pll0_state_1_u; + +/* Define the union csr_sml0_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_iso_en_sml0_harden : 1; /* [0] */ + u32 sml_mtcmos_pwr_on_sml0_harden : 1; /* [1] */ + u32 srst_req_wol_por_sml0_harden : 1; /* [2] */ + u32 srst_req_wol_comb_sml0_harden : 1; /* [3] */ + u32 wol_rst_sel_sml0_harden : 1; /* [4] */ + u32 rsv_11 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml0_power_cfg_u; + +/* Define the union csr_sml0_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_mtcmos_pwr_ack_sml0_harden : 1; /* [0] */ + u32 rsv_12 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml0_power_ack_u; + +/* Define the union csr_sml1_power_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_iso_en_sml1_harden : 1; /* [0] */ + u32 sml_mtcmos_pwr_on_sml1_harden : 1; /* [1] */ + u32 srst_req_wol_por_sml1_harden : 1; /* [2] */ + u32 srst_req_wol_comb_sml1_harden : 1; /* [3] */ + u32 wol_rst_sel_sml1_harden : 1; /* [4] */ + u32 rsv_13 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml1_power_cfg_u; + +/* Define the union csr_sml1_power_ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sml_mtcmos_pwr_ack_sml1_harden : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sml1_power_ack_u; + +/* Define the union csr_chip_uncrt_err_en_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_uncrt_err_en : 1; /* [0] */ + u32 pqm_uncrt_err_en : 1; /* [1] */ + u32 mqm_uncrt_err_en : 1; /* [2] */ + u32 stlqu_uncrt_err_en : 1; /* [3] */ + u32 smf0_uncrt_err_en : 1; /* [4] */ + u32 smf1_uncrt_err_en : 1; /* [5] */ + u32 smf2_uncrt_err_en : 1; /* [6] */ + u32 smf3_uncrt_err_en : 1; /* [7] */ + u32 sml0_uncrt_err_en : 1; /* [8] */ + u32 sml1_uncrt_err_en : 1; /* [9] */ + u32 sml2_uncrt_err_en : 1; /* [10] */ + u32 sml3_uncrt_err_en : 1; /* [11] */ + u32 stftile0_uncrt_err_en : 1; /* [12] */ + u32 stftile1_uncrt_err_en : 1; /* [13] */ + u32 stftile2_uncrt_err_en : 1; /* [14] */ + u32 stftile3_uncrt_err_en : 1; /* [15] */ + u32 stltile0_uncrt_err_en : 1; /* [16] */ + u32 stltile1_uncrt_err_en : 1; /* [17] */ + u32 stltile2_uncrt_err_en : 1; /* [18] */ + u32 stltile3_uncrt_err_en : 1; /* [19] */ + u32 mpu_uncrt_err_en : 1; /* [20] */ + u32 cpi_uncrt_err_en : 1; /* [21] */ + u32 lcam_uncrt_err_en : 1; /* [22] */ + u32 ipsutx_uncrt_err_en : 1; /* [23] */ + u32 perx_uncrt_err_en : 1; /* [24] */ + u32 ipsurx_uncrt_err_en : 1; /* [25] */ + u32 petx_uncrt_err_en : 1; /* [26] */ + u32 cpb_uncrt_err_en : 1; /* [27] */ + u32 ckd_err_int0_en : 1; /* [28] */ + u32 ckd_err_int1_en : 1; /* [29] */ + u32 pcie_uncrt_err_en : 1; /* [30] */ + u32 cryptorx_uncrt_err_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chip_uncrt_err_en_0_u; + +/* Define the union csr_chip_uncrt_err_en_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_uncrt_err_en : 1; /* [0] */ + u32 ts_uncrt_err_en : 1; /* [1] */ + u32 mag_uncrt_err_en : 1; /* [2] */ + u32 fc_uncrt_err_en : 1; /* [3] */ + u32 hva_uncrt_err_en : 1; /* [4] */ + u32 rsv_15 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chip_uncrt_err_en_1_u; + +/* Define the union csr_chip_uncrt_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_uncrt_err : 1; /* [0] */ + u32 pqm_uncrt_err : 1; /* [1] */ + u32 mqm_uncrt_err : 1; /* [2] */ + u32 stlqu_uncrt_err : 1; /* [3] */ + u32 smf0_uncrt_err : 1; /* [4] */ + u32 smf1_uncrt_err : 1; /* [5] */ + u32 smf2_uncrt_err : 1; /* [6] */ + u32 smf3_uncrt_err : 1; /* [7] */ + u32 sml0_uncrt_err : 1; /* [8] */ + u32 sml1_uncrt_err : 1; /* [9] */ + u32 sml2_uncrt_err : 1; /* [10] */ + u32 sml3_uncrt_err : 1; /* [11] */ + u32 stftile0_uncrt_err : 1; /* [12] */ + u32 stftile1_uncrt_err : 1; /* [13] */ + u32 stftile2_uncrt_err : 1; /* [14] */ + u32 stftile3_uncrt_err : 1; /* [15] */ + u32 stltile0_uncrt_err : 1; /* [16] */ + u32 stltile1_uncrt_err : 1; /* [17] */ + u32 stltile2_uncrt_err : 1; /* [18] */ + u32 stltile3_uncrt_err : 1; /* [19] */ + u32 mpu_uncrt_err : 1; /* [20] */ + u32 cpi_uncrt_err : 1; /* [21] */ + u32 lcam_uncrt_err : 1; /* [22] */ + u32 ipsutx_uncrt_err : 1; /* [23] */ + u32 perx_uncrt_err : 1; /* [24] */ + u32 ipsurx_uncrt_err : 1; /* [25] */ + u32 petx_uncrt_err : 1; /* [26] */ + u32 cpb_uncrt_err : 1; /* [27] */ + u32 ckd_err_int0 : 1; /* [28] */ + u32 ckd_err_int1 : 1; /* [29] */ + u32 pcie_uncrt_err : 1; /* [30] */ + u32 cryptorx_uncrt_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chip_uncrt_err_0_u; + +/* Define the union csr_chip_uncrt_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_uncrt_err : 1; /* [0] */ + u32 ts_uncrt_err : 1; /* [1] */ + u32 mag_uncrt_err : 1; /* [2] */ + u32 fc_uncrt_err : 1; /* [3] */ + u32 hva_uncrt_err : 1; /* [4] */ + u32 rsv_16 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chip_uncrt_err_1_u; + +/* Define the union csr_pcie_waken_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie0_waken : 1; /* [0] */ + u32 pcie1_waken : 1; /* [1] */ + u32 pcie2_waken : 1; /* [2] */ + u32 pcie3_waken : 1; /* [3] */ + u32 rsv_17 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_waken_u; + +/* Define the union csr_rst_comb_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reset_type : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rst_comb_status_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_crg_cfg_stlqu_harden_u crg_cfg_stlqu_harden; /* 0 */ + volatile csr_rst_cfg_sml0_harden_u rst_cfg_sml0_harden; /* 4 */ + volatile csr_rst_cfg_sml1_harden_u rst_cfg_sml1_harden; /* 8 */ + volatile csr_ring_sta_sml0_harden_u ring_sta_sml0_harden; /* C */ + volatile csr_ring_sta_sml1_harden_u ring_sta_sml1_harden; /* 10 */ + volatile csr_ring_sta_stlqu_harden_u ring_sta_stlqu_harden; /* 14 */ + volatile csr_rst_comb_cfg_0_u rst_comb_cfg_0; /* 18 */ + volatile csr_rst_comb_cfg_1_u rst_comb_cfg_1; /* 1C */ + volatile csr_rst_comb_cfg_2_u rst_comb_cfg_2; /* 20 */ + volatile csr_pll0_cfg_0_u pll0_cfg_0; /* 24 */ + volatile csr_pll0_cfg_1_u pll0_cfg_1; /* 28 */ + volatile csr_pll0_cfg_2_u pll0_cfg_2; /* 2C */ + volatile csr_pll0_cfg_3_u pll0_cfg_3; /* 30 */ + volatile csr_pll0_cfg_4_u pll0_cfg_4; /* 34 */ + volatile csr_pll0_cfg_5_u pll0_cfg_5; /* 38 */ + volatile csr_pll0_cfg_6_u pll0_cfg_6; /* 3C */ + volatile csr_pll0_cfg_7_u pll0_cfg_7; /* 40 */ + volatile csr_pll0_cfg_8_u pll0_cfg_8; /* 44 */ + volatile csr_pll0_state_0_u pll0_state_0; /* 48 */ + volatile csr_pll0_state_1_u pll0_state_1; /* 4C */ + volatile csr_sml0_power_cfg_u sml0_power_cfg; /* 50 */ + volatile csr_sml0_power_ack_u sml0_power_ack; /* 54 */ + volatile csr_sml1_power_cfg_u sml1_power_cfg; /* 58 */ + volatile csr_sml1_power_ack_u sml1_power_ack; /* 5C */ + volatile csr_chip_uncrt_err_en_0_u chip_uncrt_err_en_0; /* 60 */ + volatile csr_chip_uncrt_err_en_1_u chip_uncrt_err_en_1; /* 64 */ + volatile csr_chip_uncrt_err_0_u chip_uncrt_err_0; /* 68 */ + volatile csr_chip_uncrt_err_1_u chip_uncrt_err_1; /* 6C */ + volatile csr_pcie_waken_u pcie_waken; /* 70 */ + volatile csr_rst_comb_status_u rst_comb_status; /* 74 */ +} S_stlqu_harden_node_csr_REGS_TYPE; + +/* Declare the struct pointor of the module stlqu_harden_node_csr */ +extern volatile S_stlqu_harden_node_csr_REGS_TYPE *gopstlqu_harden_node_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCRG_CFG_STLQU_HARDEN_icg_en_ring_stlqu_harden(unsigned int uicg_en_ring_stlqu_harden); +int iSetCRG_CFG_STLQU_HARDEN_icg_en_cp_stlqu_harden(unsigned int uicg_en_cp_stlqu_harden); +int iSetCRG_CFG_STLQU_HARDEN_srst_req_ring_stlqu_harden(unsigned int usrst_req_ring_stlqu_harden); +int iSetCRG_CFG_STLQU_HARDEN_srst_req_grs_ring_stlqu_harden(unsigned int usrst_req_grs_ring_stlqu_harden); +int iSetCRG_CFG_STLQU_HARDEN_srst_req_lrs_ring_stlqu_harden(unsigned int usrst_req_lrs_ring_stlqu_harden); +int iSetCRG_CFG_STLQU_HARDEN_srst_req_cp_stlqu_harden(unsigned int usrst_req_cp_stlqu_harden); +int iSetRST_CFG_SML0_HARDEN_icg_en_sml_sml0_harden(unsigned int uicg_en_sml_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_icg_en_sml_div2_sml0_harden(unsigned int uicg_en_sml_div2_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_icg_en_smeg_sml0_harden(unsigned int uicg_en_smeg_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_icg_en_ring_sml0_harden(unsigned int uicg_en_ring_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_srst_req_sml_sml0_harden(unsigned int usrst_req_sml_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_srst_req_sml_div2_sml0_harden(unsigned int usrst_req_sml_div2_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_srst_req_smeg_sml0_harden(unsigned int usrst_req_smeg_sml0_harden); +int iSetRST_CFG_SML0_HARDEN_srst_req_ring_sml0_harden(unsigned int usrst_req_ring_sml0_harden); +int iSetRST_CFG_SML1_HARDEN_icg_en_sml_sml1_harden(unsigned int uicg_en_sml_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_icg_en_sml_div2_sml1_harden(unsigned int uicg_en_sml_div2_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_icg_en_smeg_sml1_harden(unsigned int uicg_en_smeg_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_icg_en_ring_sml1_harden(unsigned int uicg_en_ring_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_srst_req_sml_sml1_harden(unsigned int usrst_req_sml_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_srst_req_sml_div2_sml1_harden(unsigned int usrst_req_sml_div2_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_srst_req_smeg_sml1_harden(unsigned int usrst_req_smeg_sml1_harden); +int iSetRST_CFG_SML1_HARDEN_srst_req_ring_sml1_harden(unsigned int usrst_req_ring_sml1_harden); +int iSetRING_STA_SML0_HARDEN_sml0_harden_rs_nd_pe_crdt_sta(unsigned int usml0_harden_rs_nd_pe_crdt_sta); +int iSetRING_STA_SML1_HARDEN_sml1_harden_rs_nd_pe_crdt_sta(unsigned int usml1_harden_rs_nd_pe_crdt_sta); +int iSetRING_STA_STLQU_HARDEN_stlqu_harden_rs_nd_pe_crdt_sta(unsigned int ustlqu_harden_rs_nd_pe_crdt_sta); +int iSetRST_COMB_CFG_0_glb_sft_rstn_enable(unsigned int uglb_sft_rstn_enable); +int iSetRST_COMB_CFG_0_glb_srst_req(unsigned int uglb_srst_req); +int iSetRST_COMB_CFG_1_time_wait_efuse_done(unsigned int utime_wait_efuse_done); +int iSetRST_COMB_CFG_2_sc_bypass_icg_en_pll(unsigned int usc_bypass_icg_en_pll); +int iSetRST_COMB_CFG_2_srst_req_efuse_membst(unsigned int usrst_req_efuse_membst); +int iSetPLL0_CFG_0_pll0_cfg0(unsigned int upll0_cfg0); +int iSetPLL0_CFG_0_pll0_cfg1(unsigned int upll0_cfg1); +int iSetPLL0_CFG_1_pll0_cfg2(unsigned int upll0_cfg2); +int iSetPLL0_CFG_1_pll0_cfg3(unsigned int upll0_cfg3); +int iSetPLL0_CFG_2_pll0_cfg4(unsigned int upll0_cfg4); +int iSetPLL0_CFG_2_pll0_cfg5(unsigned int upll0_cfg5); +int iSetPLL0_CFG_3_pll0_cfg6(unsigned int upll0_cfg6); +int iSetPLL0_CFG_3_pll0_cfg7(unsigned int upll0_cfg7); +int iSetPLL0_CFG_4_pll0_cfg8(unsigned int upll0_cfg8); +int iSetPLL0_CFG_4_pll0_cfg9(unsigned int upll0_cfg9); +int iSetPLL0_CFG_5_pll0_cfg10(unsigned int upll0_cfg10); +int iSetPLL0_CFG_6_pll0_pllfctrl0(unsigned int upll0_pllfctrl0); +int iSetPLL0_CFG_7_pll0_pllfctrl1(unsigned int upll0_pllfctrl1); +int iSetPLL0_CFG_8_pll0_bypass_external_n(unsigned int upll0_bypass_external_n); +int iSetPLL0_CFG_8_pll0_peri_mode(unsigned int upll0_peri_mode); +int iSetPLL0_CFG_8_dll_en_pll0(unsigned int udll_en_pll0); +int iSetPLL0_CFG_8_probe_mode_pll0(unsigned int uprobe_mode_pll0); +int iSetPLL0_CFG_8_icg_en_probe_pll0(unsigned int uicg_en_probe_pll0); +int iSetPLL0_STATE_0_pll0_state0(unsigned int upll0_state0); +int iSetPLL0_STATE_0_pll0_state1(unsigned int upll0_state1); +int iSetPLL0_STATE_1_pll0_lock(unsigned int upll0_lock); +int iSetSML0_POWER_CFG_sml_iso_en_sml0_harden(unsigned int usml_iso_en_sml0_harden); +int iSetSML0_POWER_CFG_sml_mtcmos_pwr_on_sml0_harden(unsigned int usml_mtcmos_pwr_on_sml0_harden); +int iSetSML0_POWER_CFG_srst_req_wol_por_sml0_harden(unsigned int usrst_req_wol_por_sml0_harden); +int iSetSML0_POWER_CFG_srst_req_wol_comb_sml0_harden(unsigned int usrst_req_wol_comb_sml0_harden); +int iSetSML0_POWER_CFG_wol_rst_sel_sml0_harden(unsigned int uwol_rst_sel_sml0_harden); +int iSetSML0_POWER_ACK_sml_mtcmos_pwr_ack_sml0_harden(unsigned int usml_mtcmos_pwr_ack_sml0_harden); +int iSetSML1_POWER_CFG_sml_iso_en_sml1_harden(unsigned int usml_iso_en_sml1_harden); +int iSetSML1_POWER_CFG_sml_mtcmos_pwr_on_sml1_harden(unsigned int usml_mtcmos_pwr_on_sml1_harden); +int iSetSML1_POWER_CFG_srst_req_wol_por_sml1_harden(unsigned int usrst_req_wol_por_sml1_harden); +int iSetSML1_POWER_CFG_srst_req_wol_comb_sml1_harden(unsigned int usrst_req_wol_comb_sml1_harden); +int iSetSML1_POWER_CFG_wol_rst_sel_sml1_harden(unsigned int uwol_rst_sel_sml1_harden); +int iSetSML1_POWER_ACK_sml_mtcmos_pwr_ack_sml1_harden(unsigned int usml_mtcmos_pwr_ack_sml1_harden); +int iSetCHIP_UNCRT_ERR_EN_0_stfqu_uncrt_err_en(unsigned int ustfqu_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_pqm_uncrt_err_en(unsigned int upqm_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_mqm_uncrt_err_en(unsigned int umqm_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stlqu_uncrt_err_en(unsigned int ustlqu_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_smf0_uncrt_err_en(unsigned int usmf0_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_smf1_uncrt_err_en(unsigned int usmf1_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_smf2_uncrt_err_en(unsigned int usmf2_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_smf3_uncrt_err_en(unsigned int usmf3_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_sml0_uncrt_err_en(unsigned int usml0_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_sml1_uncrt_err_en(unsigned int usml1_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_sml2_uncrt_err_en(unsigned int usml2_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_sml3_uncrt_err_en(unsigned int usml3_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stftile0_uncrt_err_en(unsigned int ustftile0_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stftile1_uncrt_err_en(unsigned int ustftile1_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stftile2_uncrt_err_en(unsigned int ustftile2_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stftile3_uncrt_err_en(unsigned int ustftile3_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stltile0_uncrt_err_en(unsigned int ustltile0_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stltile1_uncrt_err_en(unsigned int ustltile1_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stltile2_uncrt_err_en(unsigned int ustltile2_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_stltile3_uncrt_err_en(unsigned int ustltile3_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_mpu_uncrt_err_en(unsigned int umpu_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_cpi_uncrt_err_en(unsigned int ucpi_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_lcam_uncrt_err_en(unsigned int ulcam_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_ipsutx_uncrt_err_en(unsigned int uipsutx_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_perx_uncrt_err_en(unsigned int uperx_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_ipsurx_uncrt_err_en(unsigned int uipsurx_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_petx_uncrt_err_en(unsigned int upetx_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_cpb_uncrt_err_en(unsigned int ucpb_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_ckd_err_int0_en(unsigned int uckd_err_int0_en); +int iSetCHIP_UNCRT_ERR_EN_0_ckd_err_int1_en(unsigned int uckd_err_int1_en); +int iSetCHIP_UNCRT_ERR_EN_0_pcie_uncrt_err_en(unsigned int upcie_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_0_cryptorx_uncrt_err_en(unsigned int ucryptorx_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_1_cryptotx_uncrt_err_en(unsigned int ucryptotx_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_1_ts_uncrt_err_en(unsigned int uts_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_1_mag_uncrt_err_en(unsigned int umag_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_1_fc_uncrt_err_en(unsigned int ufc_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_EN_1_hva_uncrt_err_en(unsigned int uhva_uncrt_err_en); +int iSetCHIP_UNCRT_ERR_0_stfqu_uncrt_err(unsigned int ustfqu_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_pqm_uncrt_err(unsigned int upqm_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_mqm_uncrt_err(unsigned int umqm_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stlqu_uncrt_err(unsigned int ustlqu_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_smf0_uncrt_err(unsigned int usmf0_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_smf1_uncrt_err(unsigned int usmf1_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_smf2_uncrt_err(unsigned int usmf2_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_smf3_uncrt_err(unsigned int usmf3_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_sml0_uncrt_err(unsigned int usml0_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_sml1_uncrt_err(unsigned int usml1_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_sml2_uncrt_err(unsigned int usml2_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_sml3_uncrt_err(unsigned int usml3_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stftile0_uncrt_err(unsigned int ustftile0_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stftile1_uncrt_err(unsigned int ustftile1_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stftile2_uncrt_err(unsigned int ustftile2_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stftile3_uncrt_err(unsigned int ustftile3_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stltile0_uncrt_err(unsigned int ustltile0_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stltile1_uncrt_err(unsigned int ustltile1_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stltile2_uncrt_err(unsigned int ustltile2_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_stltile3_uncrt_err(unsigned int ustltile3_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_mpu_uncrt_err(unsigned int umpu_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_cpi_uncrt_err(unsigned int ucpi_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_lcam_uncrt_err(unsigned int ulcam_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_ipsutx_uncrt_err(unsigned int uipsutx_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_perx_uncrt_err(unsigned int uperx_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_ipsurx_uncrt_err(unsigned int uipsurx_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_petx_uncrt_err(unsigned int upetx_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_cpb_uncrt_err(unsigned int ucpb_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_ckd_err_int0(unsigned int uckd_err_int0); +int iSetCHIP_UNCRT_ERR_0_ckd_err_int1(unsigned int uckd_err_int1); +int iSetCHIP_UNCRT_ERR_0_pcie_uncrt_err(unsigned int upcie_uncrt_err); +int iSetCHIP_UNCRT_ERR_0_cryptorx_uncrt_err(unsigned int ucryptorx_uncrt_err); +int iSetCHIP_UNCRT_ERR_1_cryptotx_uncrt_err(unsigned int ucryptotx_uncrt_err); +int iSetCHIP_UNCRT_ERR_1_ts_uncrt_err(unsigned int uts_uncrt_err); +int iSetCHIP_UNCRT_ERR_1_mag_uncrt_err(unsigned int umag_uncrt_err); +int iSetCHIP_UNCRT_ERR_1_fc_uncrt_err(unsigned int ufc_uncrt_err); +int iSetCHIP_UNCRT_ERR_1_hva_uncrt_err(unsigned int uhva_uncrt_err); +int iSetPCIE_WAKEN_pcie0_waken(unsigned int upcie0_waken); +int iSetPCIE_WAKEN_pcie1_waken(unsigned int upcie1_waken); +int iSetPCIE_WAKEN_pcie2_waken(unsigned int upcie2_waken); +int iSetPCIE_WAKEN_pcie3_waken(unsigned int upcie3_waken); +int iSetRST_COMB_STATUS_reset_type(unsigned int ureset_type); + + +#endif // STLQU_HARDEN_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/stlqu_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/stlqu_harden_reg_offset.h new file mode 100644 index 000000000..ed74f2caa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/stlqu_harden_reg_offset.h @@ -0,0 +1,69 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : stlqu_harden_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/07 21:45:40 Create file +// ****************************************************************************** + +#ifndef STLQU_HARDEN_REG_OFFSET_H +#define STLQU_HARDEN_REG_OFFSET_H + +/* STLQU_HARDEN_NODE_CSR Base address of Module's Register */ +#define CSR_STLQU_HARDEN_NODE_CSR_BASE (0x21FD0000) + +/* **************************************************************************** */ +/* STLQU_HARDEN_NODE_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_STLQU_HARDEN_NODE_CSR_CRG_CFG_STLQU_HARDEN_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x0) /* STLQU_HARDEN CRG的控制寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_RST_CFG_SML0_HARDEN_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x4) /* SML0_HARDEN的crg控制 */ +#define CSR_STLQU_HARDEN_NODE_CSR_RST_CFG_SML1_HARDEN_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x8) /* SML1_HARDEN的crg控制 */ +#define CSR_STLQU_HARDEN_NODE_CSR_RING_STA_SML0_HARDEN_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0xC) /* RING_CRDT_STA */ +#define CSR_STLQU_HARDEN_NODE_CSR_RING_STA_SML1_HARDEN_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x10) /* RING_CRDT_STA */ +#define CSR_STLQU_HARDEN_NODE_CSR_RING_STA_STLQU_HARDEN_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x14) /* RING_CRDT_STA \ + */ +#define CSR_STLQU_HARDEN_NODE_CSR_RST_COMB_CFG_0_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x18) /* glb srst req */ +#define CSR_STLQU_HARDEN_NODE_CSR_RST_COMB_CFG_1_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x1C) /* time wait efuse done \ + */ +#define CSR_STLQU_HARDEN_NODE_CSR_RST_COMB_CFG_2_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x20) /* rst_comb config */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_0_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x24) /* PLL10的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_1_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x28) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_2_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x2C) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_3_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x30) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_4_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x34) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_5_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x38) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_6_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x3C) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_7_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x40) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_CFG_8_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x44) /* PLL0的config寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_STATE_0_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x48) /* PLL0状态寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PLL0_STATE_1_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x4C) /* PLL0状态寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_SML0_POWER_CFG_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x50) /* SML0 power控制寄存器 \ + */ +#define CSR_STLQU_HARDEN_NODE_CSR_SML0_POWER_ACK_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x54) /* SML0 power ACK状态寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_SML1_POWER_CFG_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x58) /* SML1 power控制寄存器 \ + */ +#define CSR_STLQU_HARDEN_NODE_CSR_SML1_POWER_ACK_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x5C) /* SML1 power ACK状态寄存器 */ +#define CSR_STLQU_HARDEN_NODE_CSR_CHIP_UNCRT_ERR_EN_0_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x60) /* 各模块的uncrt_err的生效使能0 */ +#define CSR_STLQU_HARDEN_NODE_CSR_CHIP_UNCRT_ERR_EN_1_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x64) /* 各模块的uncrt_err的生效使能1 */ +#define CSR_STLQU_HARDEN_NODE_CSR_CHIP_UNCRT_ERR_0_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x68) /* 各模块的uncrt_err状态寄存器0 */ +#define CSR_STLQU_HARDEN_NODE_CSR_CHIP_UNCRT_ERR_1_REG \ + (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x6C) /* 各模块的uncrt_err状态寄存器1 */ +#define CSR_STLQU_HARDEN_NODE_CSR_PCIE_WAKEN_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x70) /* pcie的WAKEN控制输出 */ +#define CSR_STLQU_HARDEN_NODE_CSR_RST_COMB_STATUS_REG (CSR_STLQU_HARDEN_NODE_CSR_BASE + 0x74) /* rst_comb 状态寄存器 \ + */ + +#endif // STLQU_HARDEN_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_cpb_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_cpb_harden_reg_offset.h new file mode 100644 index 000000000..14f3b53b5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_cpb_harden_reg_offset.h @@ -0,0 +1,42 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : top_cpb_harden_reg_offset.h + * Project line : Platform And Key Technologies Development + * Department : CAD Development Department + * Author : xxx + * Version : 1.0 + * Date : 2021/9/22 + * Description : The description of xxx project + * Others : Generated automatically by nManager V5.1 + * History : xxx 2021/09/22 10:45:50 Create file + */ + +#ifndef TOP_CPB_HARDEN_REG_OFFSET_H +#define TOP_CPB_HARDEN_REG_OFFSET_H + +/* CPB_HARDEN_NODE_CSR Base address of Module's Register */ +#define CSR_CPB_HARDEN_NODE_CSR_BASE (0x21F40000) + +/******************************************************************************/ +/* CPB_HARDEN_NODE_CSR Registers' Definitions */ +/******************************************************************************/ + +#define CSR_CPB_HARDEN_NODE_CSR_CRG_CFG_CPB_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x0) /* CPB_HARDEN CRG的控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_CRG_CFG_STFQU_COL_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x4) /* STFQU_COL CRG的控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_CRG_CFG_STFQU_NML_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x8) /* STFQU_NML CRG的控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_CRG_CFG_STLTILE0_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0xC) /* STLTILE0_HARDEN CRG的控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_CRG_CFG_STLTILE1_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x10) /* STLTILE1_HARDEN CRG的控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_CRG_CFG_SLLC_SIOE_UP_WRAP_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x14) /* SLLC_SIOE_UP_WRAP CRG的控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_RING_STA_STFQU_COL_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x18) /* RING_CRDT_STA */ +#define CSR_CPB_HARDEN_NODE_CSR_RING_STA_STFQU_NML_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x1C) /* RING_CRDT_STA */ +#define CSR_CPB_HARDEN_NODE_CSR_RING_STA_CPB_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x20) /* RING_CRDT_STA */ +#define CSR_CPB_HARDEN_NODE_CSR_RING_STA_STLTILE0_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x24) /* RING_CRDT_STA */ +#define CSR_CPB_HARDEN_NODE_CSR_RING_STA_STLTILE1_HARDEN_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x28) /* RING_CRDT_STA */ +#define CSR_CPB_HARDEN_NODE_CSR_STLTILE0_POWER_CFG_0_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x2C) /* STLTILE0 power控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_STLTILE0_POWER_CFG_1_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x30) /* STLTILE0 power控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_STLTILE0_POWER_ACK_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x34) /* STLTILE0 power ACK状态寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_STLTILE1_POWER_CFG_0_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x38) /* STLTILE1 power控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_STLTILE1_POWER_CFG_1_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x3C) /* STLTILE1 power控制寄存器 */ +#define CSR_CPB_HARDEN_NODE_CSR_STLTILE1_POWER_ACK_REG (CSR_CPB_HARDEN_NODE_CSR_BASE + 0x40) /* STLTILE1 power ACK状态寄存器 */ + +#endif // TOP_CPB_HARDEN_REG_OFFSET_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_encryp_decryp_harden_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_encryp_decryp_harden_c_union_define.h new file mode 100644 index 000000000..da86e2285 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_encryp_decryp_harden_c_union_define.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved. + * Description: mag_harden_c_union_define.h + * Author: Generated automatically by nManager V5.1 + * Create: 2021-09-13 + */ + +#ifndef TOP_ENTRYP_DECRYP_HARDEN_C_UNION_DEFINE_H +#define TOP_ENTRYP_DECRYP_HARDEN_C_UNION_DEFINE_H + +typedef union { + struct { + u32 refdiv : 6; + u32 fbdiv : 12; + u32 postdiv1 : 3; + u32 postdiv2 : 3; + u32 bypass : 1; + u32 pd : 1; + u32 mode : 1; + u32 fout4phasepd : 1; + u32 foutpostdivpd : 1; + u32 fou2xpd : 1; + u32 reserved : 2; + } bits; + u32 value; +} csr_pll_cfg_6_u; + +typedef union { + struct { + u32 pll_bypass_external_n : 1; + u32 pll_peri_mode : 1; + u32 dll_en_pll : 1; + u32 probe_mode_pll : 1; + u32 icg_en_probe_pll : 1; + u32 reserved : 27; + } bits; + u32 value; +} csr_pll_cfg_8_u; + +typedef union { + struct { + u32 pll_lock : 1; + u32 reserved : 31; + } bits; + u32 value; +} csr_pll_state_1_u; + +#endif // TOP_ENTRYP_DECRYP_HARDEN_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_encryp_decryp_harden_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_encryp_decryp_harden_reg_offset.h new file mode 100644 index 000000000..23f3e552f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_encryp_decryp_harden_reg_offset.h @@ -0,0 +1,73 @@ +/* + * Copyright : Copyright (C) 2021, Huawei Technologies Co. Ltd. + * File name : top_encryp_decryp_harden_reg_offset.h + * Project line : Platform And Key Technologies Development + * Department : CAD Development Department + * Author : xxx + * Version : 1.0 + * Date : 2021/9/22 + * Description : The description of xxx project + * Others : Generated automatically by nManager V5.1 + * History : xxx 2021/09/22 10:48:26 Create file + */ + +#ifndef TOP_ENCRYP_DECRYP_HARDEN_REG_OFFSET_H +#define TOP_ENCRYP_DECRYP_HARDEN_REG_OFFSET_H + +/* ENCRYP_DECRYP_HARDEN_NODE_CSR Base address of Module's Register */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE (0x21F70000) + +/******************************************************************************/ +/* ENCRYP_DECRYP_HARDEN_NODE_CSR Registers' Definitions */ +/******************************************************************************/ + +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_ENCRYP_DECRYP_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x0) /* ENCRYP_DECRYP_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_MQM_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x4) /* MQM_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_SMF2_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x8) /* SMF2_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_SMF3_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xC) /* SMF3_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_STFTILE2_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x10) /* STFTILE2_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_STFTILE3_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x14) /* STFTILE3_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_STLTILE2_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x18) /* STLTILE2_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_STLTILE3_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x1C) /* STLTILE3_HARDEN CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_SLLC_SIOE_DN_WRAP_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x20) /* SLLC_SIOE_DN_WRAP CRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_CRG_CFG_HVA_RING_MN_WRAP_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x24) /* HVA_RING_MN_WRAPCRG的控制寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_SMF2_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x28) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_SMF3_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x2C) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_STFTILE2_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x30) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_STFTILE3_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x34) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_STLTILE2_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x38) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_STLTILE3_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x3C) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_MQM_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x40) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_RING_STA_ENCRYP_DECRYP_HARDEN_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x44) /* RING_CRDT_STA */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x48) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x4C) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_2_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x50) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_3_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x54) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_4_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x58) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_5_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x5C) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_6_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x60) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_7_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x64) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_CFG_8_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x68) /* PLL的config寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_STATE_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x6C) /* PLL状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_PLL_STATE_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x70) /* PLL状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_SMF2_POWER_CFG_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x74) /* SMF2 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_SMF2_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x78) /* SMF2 power ACK状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_SMF3_POWER_CFG_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x7C) /* SMF3 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_SMF3_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x80) /* SMF3 power ACK状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STFTILE2_POWER_CFG_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x84) /* STFTILE2 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STFTILE2_POWER_CFG_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x88) /* STFTILE2 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STFTILE2_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x8C) /* STFTILE2 power ACK状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STFTILE3_POWER_CFG_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x90) /* STFTILE3 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STFTILE3_POWER_CFG_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x94) /* STFTILE3 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STFTILE3_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x98) /* STFTILE3 power ACK状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STLTILE2_POWER_CFG_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0x9C) /* STLTILE2 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STLTILE2_POWER_CFG_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xA0) /* STLTILE2 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STLTILE2_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xA4) /* STLTILE2 power ACK状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STLTILE3_POWER_CFG_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xA8) /* STLTILE3 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STLTILE3_POWER_CFG_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xAC) /* STLTILE3 power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_STLTILE3_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xB0) /* STLTILE3 power ACK状�?�寄存器 */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_ENCRYP_DECRYP_POWER_CFG_0_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xB4) /* ENCRYP_DECRYP power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_ENCRYP_DECRYP_POWER_CFG_1_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xB8) /* ENCRYP_DECRYP power控制寄存�? */ +#define CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_ENCRYP_DECRYP_POWER_ACK_REG (CSR_ENCRYP_DECRYP_HARDEN_NODE_CSR_BASE + 0xBC) /* ENCRYP_DECRYP power ACK状�?�寄存器 */ + +#endif // TOP_ENCRYP_DECRYP_HARDEN_REG_OFFSET_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_iocfg_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_iocfg_reg_offset.h new file mode 100644 index 000000000..734492786 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/top/top_iocfg_reg_offset.h @@ -0,0 +1,81 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2021, Hisilicon Technologies Co. Ltd. +// File name : top_iocfg_reg_offset.h +// Version : V100 +// Date : 2021��11��26�� +// ****************************************************************************** + +#ifndef TOP_IOCFG_REG_OFFSET_H +#define TOP_IOCFG_REG_OFFSET_H + +/* MPU_HARDEN_IOCFG Base address of Module's Register */ +#define SMF0_HARDEN_IOCFG_BASE (0x1F20000) + +/* **************************************************************************** */ +/* SMF0_HARDEN_IOCFG Registers' Definitions */ +/* **************************************************************************** */ +#define SMF0_HARDEN_PORT5_LED1_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x2000) /* GPIO16 */ +#define SMF0_HARDEN_PORT5_LED2_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x2004) /* GPIO17 */ +#define SMF0_HARDEN_PORT6_LED0_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x2008) /* GPIO18 */ +#define SMF0_HARDEN_PORT6_LED1_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x200C) /* GPIO19 */ +#define SMF0_HARDEN_PORT6_LED2_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x2010) /* GPIO20 */ +#define SMF0_HARDEN_PORT7_LED0_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x2014) /* GPIO21 */ +#define SMF0_HARDEN_PORT7_LED1_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x2018) /* GPIO22 */ +#define SMF0_HARDEN_PORT7_LED2_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x201C) /* GPIO23 */ +#define SMF0_HARDEN_CHIP_UNCRT_ERR_IOCFG_REG (SMF0_HARDEN_IOCFG_BASE + 0x203C) /* GPIO31 */ + +/* MPU_HARDEN_IOCFG Base address of Module's Register */ +#define MPU_HARDEN_IOCFG_BASE (0x1FA0000) + +/* **************************************************************************** */ +/* MPU_HARDEN_IOCFG Registers' Definitions */ +/* **************************************************************************** */ + +#define MPU_HARDEN_NCSI_TXD0_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x01C) /* GPIO109 */ +#define MPU_HARDEN_NCSI_TXD1_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x020) /* GPIO110 */ +#define MPU_HARDEN_NCSI_CRS_DV_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x024) /* GPIO111 */ +#define MPU_HARDEN_NCSI_RXD0_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x028) /* GPIO112 */ +#define MPU_HARDEN_NCSI_RXD1_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x02C) /* GPIO113 */ +#define MPU_HARDEN_NCSI_ARB_IN_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x030) /* GPIO114 */ +#define MPU_HARDEN_NCSI_ARB_OUT_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x034) /* GPIO115 */ +#define MPU_HARDEN_SMB_CLK_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x038) /* smb_clk or smb_new_clk */ +#define MPU_HARDEN_SMB_DAT_IOCFG_REG (MPU_HARDEN_IOCFG_BASE + 0x03C) /* smb_dat or smb_new_dat */ + +/* STLQU_HARDEN_IOCFG Base address of Module's Register */ +#define STLQU_HARDEN_IOCFG_BASE (0x1FE0000) + +/* **************************************************************************** */ +/* STLQU_HARDEN_IOCFG Registers' Definitions */ +/* **************************************************************************** */ + +#define STLQU_HARDEN_UART_RXD_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1000) /* GPIO107 */ +#define STLQU_HARDEN_UART_TXD_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1004) /* GPIO108 */ +#define STLQU_HARDEN_I2C_MDIO_SCL0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1008) /* GPIO116 */ +#define STLQU_HARDEN_I2C_MDIO_SDA0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x100C) /* GPIO117 */ +#define STLQU_HARDEN_I2C_MDIO_SCL1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1010) /* GPIO118 */ +#define STLQU_HARDEN_I2C_MDIO_SDA1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1014) /* GPIO119 */ +#define STLQU_HARDEN_I2C_MDIO_SCL2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1018) /* GPIO120 */ +#define STLQU_HARDEN_I2C_MDIO_SDA2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x101C) /* GPIO121 */ +#define STLQU_HARDEN_I2C_MDIO_SCL3_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1020) /* GPIO122 */ +#define STLQU_HARDEN_I2C_MDIO_SDA3_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1024) /* GPIO123 */ +#define STLQU_HARDEN_I2C_MDIO_SCL4_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1028) /* GPIO124 */ +#define STLQU_HARDEN_I2C_MDIO_SDA4_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x102C) /* GPIO125 */ + +#define STLQU_HARDEN_PORT0_LED0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1030) /* GPIO126 */ +#define STLQU_HARDEN_PORT0_LED1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1034) /* GPIO126 */ +#define STLQU_HARDEN_PORT0_LED2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1038) /* GPIO126 */ +#define STLQU_HARDEN_PORT1_LED0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x103C) /* GPIO126 */ +#define STLQU_HARDEN_PORT1_LED1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1040) /* GPIO126 */ +#define STLQU_HARDEN_PORT1_LED2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1044) /* GPIO126 */ +#define STLQU_HARDEN_PORT2_LED0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1048) /* GPIO126 */ +#define STLQU_HARDEN_PORT2_LED1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x104C) /* GPIO126 */ +#define STLQU_HARDEN_PORT2_LED2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1050) /* GPIO126 */ +#define STLQU_HARDEN_PORT3_LED0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1054) /* GPIO126 */ +#define STLQU_HARDEN_PORT3_LED1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1058) /* GPIO126 */ +#define STLQU_HARDEN_PORT3_LED2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x105C) /* GPIO126 */ +#define STLQU_HARDEN_PORT4_LED0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1060) /* GPIO126 */ +#define STLQU_HARDEN_PORT4_LED1_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1064) /* GPIO126 */ +#define STLQU_HARDEN_PORT4_LED2_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x1068) /* GPIO126 */ +#define STLQU_HARDEN_PORT5_LED0_IOCFG_REG (STLQU_HARDEN_IOCFG_BASE + 0x106C) /* GPIO126 */ + +#endif // TOP_IOCFG_REG_OFFSET_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/arm_ras_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/arm_ras_c_union_define.h new file mode 100644 index 000000000..48b7f3d40 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/arm_ras_c_union_define.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : arm_ras_c_union_define.h + * Description : SPU ram_ras 相关寄存器结构体定义 + * History : 2023/04/19 11:05:46 Create file + */ + +#ifndef __ARM_RAS_C_UNION_DEFINE_H__ +#define __ARM_RAS_C_UNION_DEFINE_H__ + +#include "common.h" + +/* Define the union csr_arer_err_fr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_fr_ed : 2 ; /* [1:0] */ + u32 rsv_0 : 2 ; /* [3:2] */ + u32 err_fr_ui : 2 ; /* [5:4] */ + u32 err_fr_fi : 2 ; /* [7:6] */ + u32 err_fr_ue : 2 ; /* [9:8] */ + u32 err_fr_cfi : 2 ; /* [11:10] */ + u32 err_fr_cec : 3 ; /* [14:12] */ + u32 err_fr_rp : 1 ; /* [15] */ + u32 err_fr_dui : 2 ; /* [17:16] */ + u32 err_fr_ceo : 2 ; /* [19:18] */ + u32 rsv_1 : 12 ; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_fr_l_u; + +/* Define the union csr_arer_err_fr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_fr_h_u; + +/* Define the union csr_arer_err_ctrl_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_ctrl_ed : 1 ; /* [0] */ + u32 rsv_3 : 1 ; /* [1] */ + u32 err_ctrl_ui : 1 ; /* [2] */ + u32 err_ctrl_fi : 1 ; /* [3] */ + u32 err_ctrl_ue : 1 ; /* [4] */ + u32 rsv_4 : 3 ; /* [7:5] */ + u32 err_ctrl_cfi : 1 ; /* [8] */ + u32 rsv_5 : 1 ; /* [9] */ + u32 err_ctrl_dui : 1 ; /* [10] */ + u32 rsv_6 : 21 ; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_ctrl_l_u; + +/* Define the union csr_arer_err_ctlr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_ctlr_h_u; + +/* Define the union csr_arer_err_status_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_status_serr : 8 ; /* [7:0] */ + u32 err_status_ierr : 8 ; /* [15:8] */ + u32 rsv_8 : 4 ; /* [19:16] */ + u32 err_status_uet : 2 ; /* [21:20] */ + u32 err_status_pn : 1 ; /* [22] */ + u32 err_status_de : 1 ; /* [23] */ + u32 err_status_ce : 2 ; /* [25:24] */ + u32 err_status_mv : 1 ; /* [26] */ + u32 err_status_of : 1 ; /* [27] */ + u32 err_status_er : 1 ; /* [28] */ + u32 err_status_ue : 1 ; /* [29] */ + u32 err_status_v : 1 ; /* [30] */ + u32 err_status_av : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_status_l_u; + +/* Define the union csr_arer_err_status_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_status_h_u; + +/* Define the union csr_arer_err_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 column : 18; + u32 row_l : 14; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_addr_l_u; + +/* Define the union csr_arer_err_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 row_h : 4; // 0~3 + u32 bank : 4; // 4~7 + u32 lg_rnk : 3; // 8~10 + u32 rank : 2; // 11~12 + u32 dimm : 1; // 13 + u32 zero : 10; // + u32 rsv_10 : 5; + u32 err_addr_ai : 1; + u32 err_addr_si : 1; + u32 err_addr_ns : 1; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_addr_h_u; + +/* Define the union csr_arer_err_misc0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_misc0_l_u; + +/* Define the union csr_arer_err_misc0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_misc0_h_u; + +/* Define the union csr_arer_err_misc1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rank : 4 ; /* [3:0] */ + u32 bank : 4 ; /* [7:4] */ + u32 device : 5 ; /* [12:8] */ + u32 rsv_13 : 2 ; /* [14:13] */ + u32 busy : 1 ; /* [15] */ + u32 dev_lvl_err_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_misc1_l_u; + +/* Define the union csr_arer_err_misc1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rank_lvl_err_cnt : 16 ; /* [15:0] */ + u32 bank_lvl_err_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_arer_err_misc1_h_u; + +#endif // __ARM_RAS_C_UNION_DEFINE_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/avs_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/avs_reg_offset.h new file mode 100644 index 000000000..d01528964 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/avs_reg_offset.h @@ -0,0 +1,875 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : avs_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of AVS module +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/21 11:09:50 Create file +// ****************************************************************************** + +#ifndef __AVS_REG_OFFSET_H__ +#define __AVS_REG_OFFSET_H__ + +#define PM_REG_BASE_ADDR (0x94180000ULL) /* 电源管理 */ + +/* AVFS_REG_GEN Base address of Module's Register */ +#define CSR_AVFS_REG_GEN_BASE (PM_REG_BASE_ADDR + 0x0) + +/******************************************************************************/ +/* AVFS_REG_GEN Registers' Definitions */ +/******************************************************************************/ + +#define CSR_AVFS_REG_GEN_AVFS_ID_REG (CSR_AVFS_REG_GEN_BASE + 0xF00) /* AVFS的ID寄存器。 */ +#define CSR_AVFS_REG_GEN_AVFS_WR_OPEN_REG (CSR_AVFS_REG_GEN_BASE + 0xF04) /* AVFS全局参数保护寄存器。 */ +#define CSR_AVFS_REG_GEN_AVFS_SEL_REG (CSR_AVFS_REG_GEN_BASE + 0xF08) /* 选择AVFS寄存器 */ +#define CSR_AVFS_REG_GEN_AVFS_INT_MASK_REG (CSR_AVFS_REG_GEN_BASE + 0xF0C) /* AVFS中断屏蔽寄存器 */ +#define CSR_AVFS_REG_GEN_AVFS_INT_CLR_REG (CSR_AVFS_REG_GEN_BASE + 0xF10) /* AVFS中断清除寄存器 */ +#define CSR_AVFS_REG_GEN_AVFS_INT_REG (CSR_AVFS_REG_GEN_BASE + 0xF14) /* AVFS中断上报寄存器 */ +#define CSR_AVFS_REG_GEN_AVFS_INT_RAW_REG (CSR_AVFS_REG_GEN_BASE + 0xF18) /* AVFS中断原始上报寄存器 */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_0_REG (CSR_AVFS_REG_GEN_BASE + 0xF24) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_1_REG (CSR_AVFS_REG_GEN_BASE + 0xF2C) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_2_REG (CSR_AVFS_REG_GEN_BASE + 0xF34) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_3_REG (CSR_AVFS_REG_GEN_BASE + 0xF3C) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_4_REG (CSR_AVFS_REG_GEN_BASE + 0xF44) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_5_REG (CSR_AVFS_REG_GEN_BASE + 0xF4C) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_6_REG (CSR_AVFS_REG_GEN_BASE + 0xF54) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_7_REG (CSR_AVFS_REG_GEN_BASE + 0xF5C) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_FREQ_UPDATE_TYPE_8_REG (CSR_AVFS_REG_GEN_BASE + 0xF64) /* AVFS频率调整寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_0_REG (CSR_AVFS_REG_GEN_BASE + 0xF28) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_1_REG (CSR_AVFS_REG_GEN_BASE + 0xF30) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_2_REG (CSR_AVFS_REG_GEN_BASE + 0xF38) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_3_REG (CSR_AVFS_REG_GEN_BASE + 0xF40) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_4_REG (CSR_AVFS_REG_GEN_BASE + 0xF48) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_5_REG (CSR_AVFS_REG_GEN_BASE + 0xF50) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_6_REG (CSR_AVFS_REG_GEN_BASE + 0xF58) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_7_REG (CSR_AVFS_REG_GEN_BASE + 0xF60) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_TRIGGER_8_REG (CSR_AVFS_REG_GEN_BASE + 0xF68) /* AVFS频率调整触发寄存器(从低到高，电压域编号从0依次递增) */ +#define CSR_AVFS_REG_GEN_AVFS_RPT_REG (CSR_AVFS_REG_GEN_BASE + 0xF68) /* AVFS状态上报寄存器 */ + +/* AVS_DRES_REG Base address of Module's Register */ +#define CSR_AVS_DRES_REG_BASE (PM_REG_BASE_ADDR + 0x1000) + +/******************************************************************************/ +/* AVS_DRES_REG Registers' Definitions */ +/******************************************************************************/ + +#define CSR_AVS_DRES_REG_AVFSCTRL_REG (CSR_AVS_DRES_REG_BASE + 0x0) /* AVFS Instance Control */ +#define CSR_AVS_DRES_REG_AVFSSTAT_REG (CSR_AVS_DRES_REG_BASE + 0x4) /* AVFS Instance Status */ +#define CSR_AVS_DRES_REG_PMICPRESC_REG (CSR_AVS_DRES_REG_BASE + 0x8) /* PMIC Clock Prescaler */ +#define CSR_AVS_DRES_REG_HPMIFPRESC_REG (CSR_AVS_DRES_REG_BASE + 0xC) /* HPM IF Clock Prescaler */ +#define CSR_AVS_DRES_REG_PBSTCTRL_REG (CSR_AVS_DRES_REG_BASE + 0x10) /* PMBus Status and Control */ +#define CSR_AVS_DRES_REG_PMICWDT_REG (CSR_AVS_DRES_REG_BASE + 0x14) /* Watchdog Timer Value */ +#define CSR_AVS_DRES_REG_PBTOL_REG (CSR_AVS_DRES_REG_BASE + 0x18) /* PMBus Access Timeout [low] */ +#define CSR_AVS_DRES_REG_PBTOH_REG (CSR_AVS_DRES_REG_BASE + 0x1C) /* PMBus Access Timeout [high] */ +#define CSR_AVS_DRES_REG_PBRET_REG (CSR_AVS_DRES_REG_BASE + 0x20) /* PMBus Access Retries */ +#define CSR_AVS_DRES_REG_GPBCTRL_REG (CSR_AVS_DRES_REG_BASE + 0x24) /* Generic Access PMBus Control */ +#define CSR_AVS_DRES_REG_AVFSTIML_REG (CSR_AVS_DRES_REG_BASE + 0x28) /* AVFS timer value [low] */ +#define CSR_AVS_DRES_REG_AVFSTIMH_REG (CSR_AVS_DRES_REG_BASE + 0x2C) /* AVFS timer value [high] */ +#define CSR_AVS_DRES_REG_AVFSTIMPRE_REG (CSR_AVS_DRES_REG_BASE + 0x30) /* AVFS timer prescaler value */ +#define CSR_AVS_DRES_REG_PMICTIML_REG (CSR_AVS_DRES_REG_BASE + 0x34) /* PMIC VID Timer Value [low] */ +#define CSR_AVS_DRES_REG_PMICTIMH_REG (CSR_AVS_DRES_REG_BASE + 0x38) /* PMIC VID Timer Value [high] */ +#define CSR_AVS_DRES_REG_GPBST_REG (CSR_AVS_DRES_REG_BASE + 0x3C) /* Generic Access PMBus Status */ +#define CSR_AVS_DRES_REG_GPBTX_0_REG (CSR_AVS_DRES_REG_BASE + 0x400) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_1_REG (CSR_AVS_DRES_REG_BASE + 0x404) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_2_REG (CSR_AVS_DRES_REG_BASE + 0x408) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_3_REG (CSR_AVS_DRES_REG_BASE + 0x40C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_4_REG (CSR_AVS_DRES_REG_BASE + 0x410) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_5_REG (CSR_AVS_DRES_REG_BASE + 0x414) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_6_REG (CSR_AVS_DRES_REG_BASE + 0x418) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_7_REG (CSR_AVS_DRES_REG_BASE + 0x41C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_8_REG (CSR_AVS_DRES_REG_BASE + 0x420) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_9_REG (CSR_AVS_DRES_REG_BASE + 0x424) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_10_REG (CSR_AVS_DRES_REG_BASE + 0x428) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_11_REG (CSR_AVS_DRES_REG_BASE + 0x42C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_12_REG (CSR_AVS_DRES_REG_BASE + 0x430) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_13_REG (CSR_AVS_DRES_REG_BASE + 0x434) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_14_REG (CSR_AVS_DRES_REG_BASE + 0x438) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_15_REG (CSR_AVS_DRES_REG_BASE + 0x43C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_16_REG (CSR_AVS_DRES_REG_BASE + 0x440) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_17_REG (CSR_AVS_DRES_REG_BASE + 0x444) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_18_REG (CSR_AVS_DRES_REG_BASE + 0x448) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_19_REG (CSR_AVS_DRES_REG_BASE + 0x44C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_20_REG (CSR_AVS_DRES_REG_BASE + 0x450) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_21_REG (CSR_AVS_DRES_REG_BASE + 0x454) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_22_REG (CSR_AVS_DRES_REG_BASE + 0x458) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_23_REG (CSR_AVS_DRES_REG_BASE + 0x45C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_24_REG (CSR_AVS_DRES_REG_BASE + 0x460) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_25_REG (CSR_AVS_DRES_REG_BASE + 0x464) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_26_REG (CSR_AVS_DRES_REG_BASE + 0x468) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_27_REG (CSR_AVS_DRES_REG_BASE + 0x46C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_28_REG (CSR_AVS_DRES_REG_BASE + 0x470) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_29_REG (CSR_AVS_DRES_REG_BASE + 0x474) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_30_REG (CSR_AVS_DRES_REG_BASE + 0x478) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_31_REG (CSR_AVS_DRES_REG_BASE + 0x47C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_32_REG (CSR_AVS_DRES_REG_BASE + 0x480) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_33_REG (CSR_AVS_DRES_REG_BASE + 0x484) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_34_REG (CSR_AVS_DRES_REG_BASE + 0x488) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_35_REG (CSR_AVS_DRES_REG_BASE + 0x48C) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBTX_36_REG (CSR_AVS_DRES_REG_BASE + 0x490) /* Generic Access PMBus TX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_0_REG (CSR_AVS_DRES_REG_BASE + 0x500) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_1_REG (CSR_AVS_DRES_REG_BASE + 0x504) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_2_REG (CSR_AVS_DRES_REG_BASE + 0x508) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_3_REG (CSR_AVS_DRES_REG_BASE + 0x50C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_4_REG (CSR_AVS_DRES_REG_BASE + 0x510) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_5_REG (CSR_AVS_DRES_REG_BASE + 0x514) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_6_REG (CSR_AVS_DRES_REG_BASE + 0x518) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_7_REG (CSR_AVS_DRES_REG_BASE + 0x51C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_8_REG (CSR_AVS_DRES_REG_BASE + 0x520) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_9_REG (CSR_AVS_DRES_REG_BASE + 0x524) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_10_REG (CSR_AVS_DRES_REG_BASE + 0x528) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_11_REG (CSR_AVS_DRES_REG_BASE + 0x52C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_12_REG (CSR_AVS_DRES_REG_BASE + 0x530) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_13_REG (CSR_AVS_DRES_REG_BASE + 0x534) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_14_REG (CSR_AVS_DRES_REG_BASE + 0x538) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_15_REG (CSR_AVS_DRES_REG_BASE + 0x53C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_16_REG (CSR_AVS_DRES_REG_BASE + 0x540) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_17_REG (CSR_AVS_DRES_REG_BASE + 0x544) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_18_REG (CSR_AVS_DRES_REG_BASE + 0x548) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_19_REG (CSR_AVS_DRES_REG_BASE + 0x54C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_20_REG (CSR_AVS_DRES_REG_BASE + 0x550) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_21_REG (CSR_AVS_DRES_REG_BASE + 0x554) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_22_REG (CSR_AVS_DRES_REG_BASE + 0x558) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_23_REG (CSR_AVS_DRES_REG_BASE + 0x55C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_24_REG (CSR_AVS_DRES_REG_BASE + 0x560) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_25_REG (CSR_AVS_DRES_REG_BASE + 0x564) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_26_REG (CSR_AVS_DRES_REG_BASE + 0x568) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_27_REG (CSR_AVS_DRES_REG_BASE + 0x56C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_28_REG (CSR_AVS_DRES_REG_BASE + 0x570) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_29_REG (CSR_AVS_DRES_REG_BASE + 0x574) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_30_REG (CSR_AVS_DRES_REG_BASE + 0x578) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_31_REG (CSR_AVS_DRES_REG_BASE + 0x57C) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_32_REG (CSR_AVS_DRES_REG_BASE + 0x580) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_GPBRX_33_REG (CSR_AVS_DRES_REG_BASE + 0x584) /* Generic Access PMBus RX-Buffer */ +#define CSR_AVS_DRES_REG_PMICSTCTRL_REG (CSR_AVS_DRES_REG_BASE + 0x800) /* PMIC Status and Control */ +#define CSR_AVS_DRES_REG_AVFSVDDCTRL_REG (CSR_AVS_DRES_REG_BASE + 0x804) /* AVFS domain specific control */ +#define CSR_AVS_DRES_REG_PMICADDR_REG (CSR_AVS_DRES_REG_BASE + 0x808) /* PMIC PMBus address */ +#define CSR_AVS_DRES_REG_PMICPAGE_REG (CSR_AVS_DRES_REG_BASE + 0x80C) /* PMIC PMBus Page */ +#define CSR_AVS_DRES_REG_PMICVMINL_REG (CSR_AVS_DRES_REG_BASE + 0x810) /* Domain minimum output voltage [low] / VID */ +#define CSR_AVS_DRES_REG_PMICVMINH_REG (CSR_AVS_DRES_REG_BASE + 0x814) /* Domain minimum output voltage [high] / VID Timer Offset */ +#define CSR_AVS_DRES_REG_PMICVMAXL_REG (CSR_AVS_DRES_REG_BASE + 0x818) /* Domain maximum output voltage [low] / VID */ +#define CSR_AVS_DRES_REG_PMICVMAXH_REG (CSR_AVS_DRES_REG_BASE + 0x81C) /* Domain maximum output voltage [high] / VID6 Strobe Time */ +#define CSR_AVS_DRES_REG_PMICVTOL_REG (CSR_AVS_DRES_REG_BASE + 0x820) /* Domain output voltage tolerance */ +#define CSR_AVS_DRES_REG_PMICVCURL_REG (CSR_AVS_DRES_REG_BASE + 0x824) /* Domain current voltage [low] / VID */ +#define CSR_AVS_DRES_REG_PMICVCURH_REG (CSR_AVS_DRES_REG_BASE + 0x828) /* Domain current voltage [high] */ +#define CSR_AVS_DRES_REG_PMICVSTEPS_REG (CSR_AVS_DRES_REG_BASE + 0x82C) /* Domain Voltage/VID step for small error */ +#define CSR_AVS_DRES_REG_PMICVSTEPL_REG (CSR_AVS_DRES_REG_BASE + 0x830) /* Domain Voltage/VID step for large error */ +#define CSR_AVS_DRES_REG_HPMVSTEPTH_REG (CSR_AVS_DRES_REG_BASE + 0x834) /* HPM voltage step threshold */ +#define CSR_AVS_DRES_REG_HPMINFO_REG (CSR_AVS_DRES_REG_BASE + 0x838) /* Availability and Communication status of HPMs in that VDD domain */ +#define CSR_AVS_DRES_REG_HPMDIVM_0_REG (CSR_AVS_DRES_REG_BASE + 0xC00) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_1_REG (CSR_AVS_DRES_REG_BASE + 0xC40) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_2_REG (CSR_AVS_DRES_REG_BASE + 0xC80) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_3_REG (CSR_AVS_DRES_REG_BASE + 0xCC0) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_4_REG (CSR_AVS_DRES_REG_BASE + 0xD00) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_5_REG (CSR_AVS_DRES_REG_BASE + 0xD40) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_6_REG (CSR_AVS_DRES_REG_BASE + 0xD80) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVM_7_REG (CSR_AVS_DRES_REG_BASE + 0xDC0) /* HPM Core Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_0_REG (CSR_AVS_DRES_REG_BASE + 0xC04) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_1_REG (CSR_AVS_DRES_REG_BASE + 0xC44) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_2_REG (CSR_AVS_DRES_REG_BASE + 0xC84) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_3_REG (CSR_AVS_DRES_REG_BASE + 0xCC4) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_4_REG (CSR_AVS_DRES_REG_BASE + 0xD04) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_5_REG (CSR_AVS_DRES_REG_BASE + 0xD44) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_6_REG (CSR_AVS_DRES_REG_BASE + 0xD84) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMDIVN_7_REG (CSR_AVS_DRES_REG_BASE + 0xDC4) /* HPM DCO Clock Divider Value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_0_REG (CSR_AVS_DRES_REG_BASE + 0xC08) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_1_REG (CSR_AVS_DRES_REG_BASE + 0xC48) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_2_REG (CSR_AVS_DRES_REG_BASE + 0xC88) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_3_REG (CSR_AVS_DRES_REG_BASE + 0xCC8) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_4_REG (CSR_AVS_DRES_REG_BASE + 0xD08) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_5_REG (CSR_AVS_DRES_REG_BASE + 0xD48) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_6_REG (CSR_AVS_DRES_REG_BASE + 0xD88) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMIRQTH_7_REG (CSR_AVS_DRES_REG_BASE + 0xDC8) /* HPM Interrupt threshold value */ +#define CSR_AVS_DRES_REG_HPMLMIN_0_REG (CSR_AVS_DRES_REG_BASE + 0xC0C) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_1_REG (CSR_AVS_DRES_REG_BASE + 0xC4C) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_2_REG (CSR_AVS_DRES_REG_BASE + 0xC8C) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_3_REG (CSR_AVS_DRES_REG_BASE + 0xCCC) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_4_REG (CSR_AVS_DRES_REG_BASE + 0xD0C) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_5_REG (CSR_AVS_DRES_REG_BASE + 0xD4C) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_6_REG (CSR_AVS_DRES_REG_BASE + 0xD8C) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMLMIN_7_REG (CSR_AVS_DRES_REG_BASE + 0xDCC) /* HPM DCO minimum chain length */ +#define CSR_AVS_DRES_REG_HPMCAL_0_REG (CSR_AVS_DRES_REG_BASE + 0xC10) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_1_REG (CSR_AVS_DRES_REG_BASE + 0xC50) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_2_REG (CSR_AVS_DRES_REG_BASE + 0xC90) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_3_REG (CSR_AVS_DRES_REG_BASE + 0xCD0) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_4_REG (CSR_AVS_DRES_REG_BASE + 0xD10) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_5_REG (CSR_AVS_DRES_REG_BASE + 0xD50) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_6_REG (CSR_AVS_DRES_REG_BASE + 0xD90) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCAL_7_REG (CSR_AVS_DRES_REG_BASE + 0xDD0) /* HPM isoline calibration register */ +#define CSR_AVS_DRES_REG_HPMCREF_0_REG (CSR_AVS_DRES_REG_BASE + 0xC14) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_1_REG (CSR_AVS_DRES_REG_BASE + 0xC54) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_2_REG (CSR_AVS_DRES_REG_BASE + 0xC94) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_3_REG (CSR_AVS_DRES_REG_BASE + 0xCD4) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_4_REG (CSR_AVS_DRES_REG_BASE + 0xD14) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_5_REG (CSR_AVS_DRES_REG_BASE + 0xD54) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_6_REG (CSR_AVS_DRES_REG_BASE + 0xD94) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCREF_7_REG (CSR_AVS_DRES_REG_BASE + 0xDD4) /* HPM reference value */ +#define CSR_AVS_DRES_REG_HPMCTRL_0_REG (CSR_AVS_DRES_REG_BASE + 0xC18) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_1_REG (CSR_AVS_DRES_REG_BASE + 0xC58) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_2_REG (CSR_AVS_DRES_REG_BASE + 0xC98) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_3_REG (CSR_AVS_DRES_REG_BASE + 0xCD8) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_4_REG (CSR_AVS_DRES_REG_BASE + 0xD18) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_5_REG (CSR_AVS_DRES_REG_BASE + 0xD58) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_6_REG (CSR_AVS_DRES_REG_BASE + 0xD98) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCTRL_7_REG (CSR_AVS_DRES_REG_BASE + 0xDD8) /* HPM Control Register */ +#define CSR_AVS_DRES_REG_HPMCOUT_0_REG (CSR_AVS_DRES_REG_BASE + 0xC1C) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_1_REG (CSR_AVS_DRES_REG_BASE + 0xC5C) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_2_REG (CSR_AVS_DRES_REG_BASE + 0xC9C) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_3_REG (CSR_AVS_DRES_REG_BASE + 0xCDC) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_4_REG (CSR_AVS_DRES_REG_BASE + 0xD1C) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_5_REG (CSR_AVS_DRES_REG_BASE + 0xD5C) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_6_REG (CSR_AVS_DRES_REG_BASE + 0xD9C) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMCOUT_7_REG (CSR_AVS_DRES_REG_BASE + 0xDDC) /* HPM output value */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_0_REG (CSR_AVS_DRES_REG_BASE + 0xC20) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_1_REG (CSR_AVS_DRES_REG_BASE + 0xC60) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_2_REG (CSR_AVS_DRES_REG_BASE + 0xCA0) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_3_REG (CSR_AVS_DRES_REG_BASE + 0xCE0) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_4_REG (CSR_AVS_DRES_REG_BASE + 0xD20) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_5_REG (CSR_AVS_DRES_REG_BASE + 0xD60) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_6_REG (CSR_AVS_DRES_REG_BASE + 0xDA0) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVMPRED_7_REG (CSR_AVS_DRES_REG_BASE + 0xDE0) /* HPM Core Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_0_REG (CSR_AVS_DRES_REG_BASE + 0xC24) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_1_REG (CSR_AVS_DRES_REG_BASE + 0xC64) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_2_REG (CSR_AVS_DRES_REG_BASE + 0xCA4) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_3_REG (CSR_AVS_DRES_REG_BASE + 0xCE4) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_4_REG (CSR_AVS_DRES_REG_BASE + 0xD24) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_5_REG (CSR_AVS_DRES_REG_BASE + 0xD64) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_6_REG (CSR_AVS_DRES_REG_BASE + 0xDA4) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMDIVNPRED_7_REG (CSR_AVS_DRES_REG_BASE + 0xDE4) /* HPM DCO Clock Divider Value in prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_0_REG (CSR_AVS_DRES_REG_BASE + 0xC28) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_1_REG (CSR_AVS_DRES_REG_BASE + 0xC68) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_2_REG (CSR_AVS_DRES_REG_BASE + 0xCA8) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_3_REG (CSR_AVS_DRES_REG_BASE + 0xCE8) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_4_REG (CSR_AVS_DRES_REG_BASE + 0xD28) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_5_REG (CSR_AVS_DRES_REG_BASE + 0xD68) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_6_REG (CSR_AVS_DRES_REG_BASE + 0xDA8) /* HPM Control Register for prediction mode */ +#define CSR_AVS_DRES_REG_HPMPRED_7_REG (CSR_AVS_DRES_REG_BASE + 0xDE8) /* HPM Control Register for prediction mode */ + +/* AVS_REG_GEN Base address of Module's Register */ +#define CSR_AVS_REG_GEN_BASE (PM_REG_BASE_ADDR + 0x0) + +/******************************************************************************/ +/* AVS_REG_GEN Registers' Definitions */ +/******************************************************************************/ + +#define CSR_AVS_REG_GEN_AVS_ID_REG (CSR_AVS_REG_GEN_BASE + 0x0) /* AVS的ID寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_WR_OPEN_REG (CSR_AVS_REG_GEN_BASE + 0x4) /* AVS全局参数保护寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_INT_STATUS_REG (CSR_AVS_REG_GEN_BASE + 0x8) /* AVS中断状态寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_ERROR_INT_STATUS_REG (CSR_AVS_REG_GEN_BASE + 0xC) /* AVS错误告警中断状态寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PARITY_INT_STATUS_REG (CSR_AVS_REG_GEN_BASE + 0x10) /* AVS奇偶校验告警中断状态寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_INT_RAW_STATUS_REG (CSR_AVS_REG_GEN_BASE + 0x14) /* AVS中断原始状态寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_ERROR_INT_RAW_STATUS_REG (CSR_AVS_REG_GEN_BASE + 0x18) /* AVS错误告警原始中断状态寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PARITY_INT_RAW_STATUS_REG (CSR_AVS_REG_GEN_BASE + 0x1C) /* AVS奇偶校验告警原始中断状态寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_INT_CLEAR_REG (CSR_AVS_REG_GEN_BASE + 0x20) /* AVS中断清除寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_ERROR_INT_CLEAR_REG (CSR_AVS_REG_GEN_BASE + 0x24) /* AVS错误告警中断清除寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PARITY_INT_CLR_REG (CSR_AVS_REG_GEN_BASE + 0x28) /* AVS奇偶校验告警中断清除寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PC_ENABLE_REG (CSR_AVS_REG_GEN_BASE + 0x30) /* AVS静态参数奇偶校验使能寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_INT_MASK_REG (CSR_AVS_REG_GEN_BASE + 0x34) /* AVS中断屏蔽寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_ERROR_INT_MASK_REG (CSR_AVS_REG_GEN_BASE + 0x38) /* AVS错误告警中断屏蔽寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PARITY_INT_MASK_REG (CSR_AVS_REG_GEN_BASE + 0x3C) /* AVS奇偶校验告警中断屏蔽寄存器。 */ +#define CSR_AVS_REG_GEN_PMU_CFG_0_REG (CSR_AVS_REG_GEN_BASE + 0x40) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_1_REG (CSR_AVS_REG_GEN_BASE + 0xBC) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_2_REG (CSR_AVS_REG_GEN_BASE + 0x138) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_3_REG (CSR_AVS_REG_GEN_BASE + 0x1B4) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_4_REG (CSR_AVS_REG_GEN_BASE + 0x230) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_5_REG (CSR_AVS_REG_GEN_BASE + 0x2AC) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_6_REG (CSR_AVS_REG_GEN_BASE + 0x328) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_7_REG (CSR_AVS_REG_GEN_BASE + 0x3A4) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_PMU_CFG_8_REG (CSR_AVS_REG_GEN_BASE + 0x420) /* PMU相关配置寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_0_REG (CSR_AVS_REG_GEN_BASE + 0x44) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_1_REG (CSR_AVS_REG_GEN_BASE + 0xC0) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_2_REG (CSR_AVS_REG_GEN_BASE + 0x13C) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_3_REG (CSR_AVS_REG_GEN_BASE + 0x1B8) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_4_REG (CSR_AVS_REG_GEN_BASE + 0x234) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_5_REG (CSR_AVS_REG_GEN_BASE + 0x2B0) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_6_REG (CSR_AVS_REG_GEN_BASE + 0x32C) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_7_REG (CSR_AVS_REG_GEN_BASE + 0x3A8) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_ENABLE_AND_DVFS_VOL_LMT_8_REG (CSR_AVS_REG_GEN_BASE + 0x424) /* 使能和DVFS配置的电压门限寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_0_REG (CSR_AVS_REG_GEN_BASE + 0x48) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_1_REG (CSR_AVS_REG_GEN_BASE + 0xC4) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_2_REG (CSR_AVS_REG_GEN_BASE + 0x140) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_3_REG (CSR_AVS_REG_GEN_BASE + 0x1BC) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_4_REG (CSR_AVS_REG_GEN_BASE + 0x238) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_5_REG (CSR_AVS_REG_GEN_BASE + 0x2B4) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_6_REG (CSR_AVS_REG_GEN_BASE + 0x330) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_7_REG (CSR_AVS_REG_GEN_BASE + 0x3AC) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_DVFS_NEXT_VOL_8_REG (CSR_AVS_REG_GEN_BASE + 0x428) /* DVFS请求输出的电压值寄存器 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_0_REG (CSR_AVS_REG_GEN_BASE + 0x4C) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_1_REG (CSR_AVS_REG_GEN_BASE + 0xC8) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_2_REG (CSR_AVS_REG_GEN_BASE + 0x144) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_3_REG (CSR_AVS_REG_GEN_BASE + 0x1C0) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_4_REG (CSR_AVS_REG_GEN_BASE + 0x23C) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_5_REG (CSR_AVS_REG_GEN_BASE + 0x2B8) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_6_REG (CSR_AVS_REG_GEN_BASE + 0x334) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_7_REG (CSR_AVS_REG_GEN_BASE + 0x3B0) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_CHECK_CFG_8_REG (CSR_AVS_REG_GEN_BASE + 0x42C) /* AVS检测相关寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_0_REG (CSR_AVS_REG_GEN_BASE + 0x50) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_1_REG (CSR_AVS_REG_GEN_BASE + 0xCC) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_2_REG (CSR_AVS_REG_GEN_BASE + 0x148) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_3_REG (CSR_AVS_REG_GEN_BASE + 0x1C4) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_4_REG (CSR_AVS_REG_GEN_BASE + 0x240) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_5_REG (CSR_AVS_REG_GEN_BASE + 0x2BC) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_6_REG (CSR_AVS_REG_GEN_BASE + 0x338) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_7_REG (CSR_AVS_REG_GEN_BASE + 0x3B4) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_DONE_INTERVAL_8_REG (CSR_AVS_REG_GEN_BASE + 0x430) /* AVS调整稳定后的检测间隔 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_0_REG (CSR_AVS_REG_GEN_BASE + 0x54) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_1_REG (CSR_AVS_REG_GEN_BASE + 0xD0) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_2_REG (CSR_AVS_REG_GEN_BASE + 0x14C) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_3_REG (CSR_AVS_REG_GEN_BASE + 0x1C8) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_4_REG (CSR_AVS_REG_GEN_BASE + 0x244) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_5_REG (CSR_AVS_REG_GEN_BASE + 0x2C0) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_6_REG (CSR_AVS_REG_GEN_BASE + 0x33C) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_7_REG (CSR_AVS_REG_GEN_BASE + 0x3B8) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_MISCELL_8_REG (CSR_AVS_REG_GEN_BASE + 0x434) /* AVS其它配置寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0x58) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0xD4) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x150) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x1CC) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x248) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x2C4) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x340) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x3BC) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x438) /* HPM0相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0x5C) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0xD8) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x154) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x1D0) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x24C) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x2C8) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x344) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x3C0) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x43C) /* HPM0相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0x60) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0xDC) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x158) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x1D4) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x250) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x2CC) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x348) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x3C4) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x440) /* HPM0相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0x64) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0xE0) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x15C) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x1D8) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x254) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x2D0) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x34C) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x3C8) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x444) /* HPM1相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0x68) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0xE4) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x160) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x1DC) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x258) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x2D4) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x350) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x3CC) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x448) /* HPM1相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0x6C) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0xE8) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x164) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x1E0) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x25C) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x2D8) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x354) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x3D0) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x44C) /* HPM1相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0x70) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0xEC) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x168) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x1E4) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x260) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x2DC) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x358) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x3D4) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x450) /* HPM2相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0x74) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0xF0) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x16C) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x1E8) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x264) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x2E0) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x35C) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x3D8) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x454) /* HPM2相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0x78) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0xF4) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x170) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x1EC) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x268) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x2E4) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x360) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x3DC) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x458) /* HPM2相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0x7C) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0xF8) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x174) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x1F0) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x26C) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x2E8) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x364) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x3E0) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x45C) /* HPM3相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0x80) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0xFC) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x178) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x1F4) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x270) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x2EC) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x368) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x3E4) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x460) /* HPM3相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0x84) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0x100) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x17C) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x1F8) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x274) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x2F0) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x36C) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x3E8) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x464) /* HPM3相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0x88) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0x104) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x180) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x1FC) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x278) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x2F4) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x370) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x3EC) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x468) /* HPM4相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0x8C) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0x108) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x184) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x200) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x27C) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x2F8) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x374) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x3F0) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x46C) /* HPM4相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0x90) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0x10C) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x188) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x204) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x280) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x2FC) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x378) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x3F4) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x470) /* HPM4相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0x94) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0x110) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x18C) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x208) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x284) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x300) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x37C) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x3F8) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x474) /* HPM5相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0x98) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0x114) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x190) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x20C) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x288) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x304) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x380) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x3FC) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x478) /* HPM5相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0x9C) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0x118) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x194) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x210) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x28C) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x308) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x384) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x400) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x47C) /* HPM5相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0xA0) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0x11C) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x198) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x214) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x290) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x30C) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x388) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x404) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x480) /* HPM6相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0xA4) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0x120) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x19C) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x218) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x294) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x310) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x38C) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x408) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x484) /* HPM6相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0xA8) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0x124) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x1A0) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x21C) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x298) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x314) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x390) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x40C) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x488) /* HPM6相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_0_REG (CSR_AVS_REG_GEN_BASE + 0xAC) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_1_REG (CSR_AVS_REG_GEN_BASE + 0x128) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_2_REG (CSR_AVS_REG_GEN_BASE + 0x1A4) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_3_REG (CSR_AVS_REG_GEN_BASE + 0x220) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_4_REG (CSR_AVS_REG_GEN_BASE + 0x29C) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_5_REG (CSR_AVS_REG_GEN_BASE + 0x318) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_6_REG (CSR_AVS_REG_GEN_BASE + 0x394) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_7_REG (CSR_AVS_REG_GEN_BASE + 0x410) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG0_8_REG (CSR_AVS_REG_GEN_BASE + 0x48C) /* HPM7相关配置0寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_0_REG (CSR_AVS_REG_GEN_BASE + 0xB0) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_1_REG (CSR_AVS_REG_GEN_BASE + 0x12C) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_2_REG (CSR_AVS_REG_GEN_BASE + 0x1A8) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_3_REG (CSR_AVS_REG_GEN_BASE + 0x224) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_4_REG (CSR_AVS_REG_GEN_BASE + 0x2A0) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_5_REG (CSR_AVS_REG_GEN_BASE + 0x31C) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_6_REG (CSR_AVS_REG_GEN_BASE + 0x398) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_7_REG (CSR_AVS_REG_GEN_BASE + 0x414) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG1_8_REG (CSR_AVS_REG_GEN_BASE + 0x490) /* HPM7相关配置1寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_0_REG (CSR_AVS_REG_GEN_BASE + 0xB4) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_1_REG (CSR_AVS_REG_GEN_BASE + 0x130) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_2_REG (CSR_AVS_REG_GEN_BASE + 0x1AC) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_3_REG (CSR_AVS_REG_GEN_BASE + 0x228) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_4_REG (CSR_AVS_REG_GEN_BASE + 0x2A4) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_5_REG (CSR_AVS_REG_GEN_BASE + 0x320) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_6_REG (CSR_AVS_REG_GEN_BASE + 0x39C) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_7_REG (CSR_AVS_REG_GEN_BASE + 0x418) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_RELATED_CFG2_8_REG (CSR_AVS_REG_GEN_BASE + 0x494) /* HPM7相关配置2寄存器 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_0_REG (CSR_AVS_REG_GEN_BASE + 0xB8) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_1_REG (CSR_AVS_REG_GEN_BASE + 0x134) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_2_REG (CSR_AVS_REG_GEN_BASE + 0x1B0) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_3_REG (CSR_AVS_REG_GEN_BASE + 0x22C) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_4_REG (CSR_AVS_REG_GEN_BASE + 0x2A8) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_5_REG (CSR_AVS_REG_GEN_BASE + 0x324) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_6_REG (CSR_AVS_REG_GEN_BASE + 0x3A0) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_7_REG (CSR_AVS_REG_GEN_BASE + 0x41C) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_TRIGGER_CFG_8_REG (CSR_AVS_REG_GEN_BASE + 0x498) /* DVFS和AVS启动寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_0_REG (CSR_AVS_REG_GEN_BASE + 0x500) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_1_REG (CSR_AVS_REG_GEN_BASE + 0x52C) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_2_REG (CSR_AVS_REG_GEN_BASE + 0x558) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_3_REG (CSR_AVS_REG_GEN_BASE + 0x584) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5B0) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5DC) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_6_REG (CSR_AVS_REG_GEN_BASE + 0x608) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_7_REG (CSR_AVS_REG_GEN_BASE + 0x634) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_DVFS_PMUCTRL_RPT_8_REG (CSR_AVS_REG_GEN_BASE + 0x660) /* DVFS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_0_REG (CSR_AVS_REG_GEN_BASE + 0x504) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_1_REG (CSR_AVS_REG_GEN_BASE + 0x530) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_2_REG (CSR_AVS_REG_GEN_BASE + 0x55C) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_3_REG (CSR_AVS_REG_GEN_BASE + 0x588) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5B4) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5E0) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_6_REG (CSR_AVS_REG_GEN_BASE + 0x60C) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_7_REG (CSR_AVS_REG_GEN_BASE + 0x638) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_AVS_PMUCTRL_RPT_8_REG (CSR_AVS_REG_GEN_BASE + 0x664) /* AVS和PMUCTRL模块的状态上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_0_REG (CSR_AVS_REG_GEN_BASE + 0x508) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_1_REG (CSR_AVS_REG_GEN_BASE + 0x534) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_2_REG (CSR_AVS_REG_GEN_BASE + 0x560) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_3_REG (CSR_AVS_REG_GEN_BASE + 0x58C) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5B8) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5E4) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_6_REG (CSR_AVS_REG_GEN_BASE + 0x610) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_7_REG (CSR_AVS_REG_GEN_BASE + 0x63C) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM_TIMEOUT_RPT_8_REG (CSR_AVS_REG_GEN_BASE + 0x668) /* HPM超时告警寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x50C) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x538) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x564) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x590) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5BC) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5E8) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x614) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x640) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x66C) /* HPM0检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x510) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x53C) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x568) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x594) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5C0) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5EC) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x618) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x644) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM1_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x670) /* HPM1检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x514) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x540) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x56C) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x598) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5C4) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5F0) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x61C) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x648) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM2_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x674) /* HPM2检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x518) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x544) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x570) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x59C) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5C8) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5F4) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x620) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x64C) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM3_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x678) /* HPM3检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x51C) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x548) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x574) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x5A0) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5CC) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5F8) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x624) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x650) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM4_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x67C) /* HPM4检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x520) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x54C) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x578) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x5A4) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5D0) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x5FC) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x628) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x654) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM5_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x680) /* HPM5检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x524) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x550) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x57C) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x5A8) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5D4) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x600) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x62C) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x658) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM6_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x684) /* HPM6检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x528) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x554) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x580) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x5AC) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x5D8) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x604) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x630) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x65C) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM7_SAMPLE_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x688) /* HPM7检测结果上报寄存器。 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x700) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x720) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x740) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x760) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x780) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7A0) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7C0) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7E0) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x800) /* HPM0运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x704) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x724) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x744) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x764) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x784) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7A4) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7C4) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7E4) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x804) /* HPM1运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x708) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x728) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x748) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x768) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x788) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7A8) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7C8) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7E8) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x808) /* HPM2运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x70C) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x72C) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x74C) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x76C) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x78C) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7AC) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7CC) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7EC) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x80C) /* HPM3运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x710) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x730) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x750) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x770) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x790) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7B0) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7D0) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7F0) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x810) /* HPM4运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x714) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x734) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x754) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x774) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x794) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7B4) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7D4) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7F4) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x814) /* HPM5运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x718) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x738) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x758) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x778) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x798) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7B8) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7D8) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7F8) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x818) /* HPM6运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_0_REG (CSR_AVS_REG_GEN_BASE + 0x71C) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_1_REG (CSR_AVS_REG_GEN_BASE + 0x73C) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_2_REG (CSR_AVS_REG_GEN_BASE + 0x75C) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_3_REG (CSR_AVS_REG_GEN_BASE + 0x77C) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_4_REG (CSR_AVS_REG_GEN_BASE + 0x79C) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_5_REG (CSR_AVS_REG_GEN_BASE + 0x7BC) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_6_REG (CSR_AVS_REG_GEN_BASE + 0x7DC) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_7_REG (CSR_AVS_REG_GEN_BASE + 0x7FC) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_CAL_RESULT_8_REG (CSR_AVS_REG_GEN_BASE + 0x81C) /* HPM7运算结果上报寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x700) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x720) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x740) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x760) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x780) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7A0) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7C0) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7E0) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM0_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x800) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x704) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x724) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x744) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x764) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x784) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7A4) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7C4) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7E4) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM1_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x804) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x708) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x728) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x748) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x768) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x788) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7A8) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7C8) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7E8) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM2_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x808) /* FPGA测试时HPM0的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x70C) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x72C) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x74C) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x76C) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x78C) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7AC) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7CC) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7EC) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM3_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x80C) /* FPGA测试时HPM3的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x710) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x730) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x750) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x770) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x790) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7B0) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7D0) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7F0) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM4_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x810) /* FPGA测试时HPM4的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x714) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x734) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x754) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x774) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x794) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7B4) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7D4) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7F4) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM5_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x814) /* FPGA测试时HPM5的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x718) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x738) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x758) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x778) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x798) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7B8) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7D8) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7F8) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM6_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x818) /* FPGA测试时HPM6的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_0_REG (CSR_AVS_REG_GEN_BASE + 0x71C) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_1_REG (CSR_AVS_REG_GEN_BASE + 0x73C) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_2_REG (CSR_AVS_REG_GEN_BASE + 0x75C) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_3_REG (CSR_AVS_REG_GEN_BASE + 0x77C) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_4_REG (CSR_AVS_REG_GEN_BASE + 0x79C) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_5_REG (CSR_AVS_REG_GEN_BASE + 0x7BC) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_6_REG (CSR_AVS_REG_GEN_BASE + 0x7DC) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_7_REG (CSR_AVS_REG_GEN_BASE + 0x7FC) /* FPGA测试时HPM7的结果寄存器 */ +#define CSR_AVS_REG_GEN_HPM7_FPGA_DATA_8_REG (CSR_AVS_REG_GEN_BASE + 0x81C) /* FPGA测试时HPM7的结果寄存器 */ + +/* PMBUSIF_REG_GEN Base address of Module's Register */ +#define CSR_PMBUSIF_REG_GEN_BASE (PM_REG_BASE_ADDR + 0x800) + +/******************************************************************************/ +/* PMBUSIF_REG_GEN Registers' Definitions */ +/******************************************************************************/ + +#define CSR_PMBUSIF_REG_GEN_I2C_CON_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x0) /* I2C控制寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_TAR_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x4) /* I2C访问Slave地址寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_DATA_CMD_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x10) /* I2C数据操作寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SS_SCL_HCNT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x14) /* I2C标准速度模式SCL高电平配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SS_SCL_LCNT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x18) /* I2C标准速度模式SCL低电平配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_FS_SCL_HCNT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x1C) /* I2C快速模式SCL高电平配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_FS_SCL_LCNT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x20) /* I2C快速模式SCL低电平配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_INTR_STAT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x2C) /* I2C屏蔽后中断状态寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_INTR_MASK_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x30) /* I2C中断屏蔽寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_INTR_RAW_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x34) /* I2C原始中断状态寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_RX_TL_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x38) /* RX_FIFO水线设置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_TX_TL_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x3C) /* RX_FIFO水线设置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_ENABLE_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x6C) /* I2C工作使能寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_STATUS_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x70) /* I2C状态寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_TXFLR_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x74) /* TX_FIFO有效数据指示寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_RXFLR_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x78) /* RX_FIFO有效数据指示寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SDA_HOLD_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x7C) /* SDA保持时间配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_TX_ABRT_SRC_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x80) /* I2C发送失败中断源寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_ENABLE_STATUS_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x9C) /* I2C状态寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SCL_SWITCH_REG (CSR_PMBUSIF_REG_GEN_BASE + 0xA0) /* I2C防挂死SCL使能寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SCL_SIM_REG (CSR_PMBUSIF_REG_GEN_BASE + 0xA4) /* I2C防挂死SCL模拟寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_LOCK_REG (CSR_PMBUSIF_REG_GEN_BASE + 0xAC) /* I2C lock寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SDA_SWITCH_REG (CSR_PMBUSIF_REG_GEN_BASE + 0xB0) /* I2C防挂死SDA使能寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_SDA_SIM_REG (CSR_PMBUSIF_REG_GEN_BASE + 0xB4) /* I2C防挂死SDA模拟寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_PMBUS_CTRL_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x104) /* PMBUS全局控制寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_LOW_TIMEOUT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x108) /* SCL低电平超时值配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_MST_ALERT_DO_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x114) /* Master模式下Alert命令触发寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_PEC_INFO_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x11C) /* PEC信息寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_GRP_CMD_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x128) /* PMBUS group command使能寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_PMBUS_SCL_DET_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x12C) /* PMBUS SCL检测寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_PMBUS_IDLECNT_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x130) /* SCL高电平空闲值配置寄存器。 */ +#define CSR_PMBUSIF_REG_GEN_I2C_PMBUS_RST_REG (CSR_PMBUSIF_REG_GEN_BASE + 0x134) /* 软件复位配置寄存器。 */ + +/* PMBUS_PROC_REG_GEN Base address of Module's Register */ +#define CSR_PMBUS_PROC_REG_GEN_BASE (PM_REG_BASE_ADDR + 0xA00) + +/******************************************************************************/ +/* PMBUS_PROC_REG_GEN Registers' Definitions */ +/******************************************************************************/ + +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_ID_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x0) /* PMBUS的ID寄存器。 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_WR_OPEN_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x4) /* PMBUS全局参数保护寄存器。 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_INT_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x8) /* PMBUS中断上报寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_INT_RAW_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0xC) /* PMBUS中断原始上报寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_INT_CLR_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x10) /* PMBUS中断清除寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_PC_ENABLE_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x14) /* PMBUS模块静态参数奇偶校验使能寄存器。 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_INT_MASK_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x18) /* PMBUS中断屏蔽寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_PROC_TIMEOUT_TH_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x1C) /* PMBUS硬件调压流程超时门限值寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_VOLTAGE_STABLE_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x20) /* PMBUS电压稳定时延寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_RESEND_CMD_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x24) /* 重新发送命令等待间隔寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_READ_VOUD_INTERVAL_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x28) /* 重新发送READ_VOUT命令间隔寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_PMBUS_OTHER_CFG_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x2C) /* PMBUS其它相关配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_0_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x30) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_1_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x38) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_2_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x40) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_3_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x48) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_4_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x50) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_5_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x58) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_6_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x60) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_7_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x68) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_ADDR_CFG_8_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x70) /* 电压域相关的地址等配置寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_0_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x34) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_1_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x3C) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_2_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x44) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_3_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x4C) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_4_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x54) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_5_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x5C) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_6_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x64) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_7_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x6C) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_VOLTAGE_CONVERT_CFG_8_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0x74) /* 电压域的电压值转换相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_SOFT_WR_FAIL_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0xA0) /* 软件写第一个字节失败告警上报寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_STATUS_RPT_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0xA4) /* 状态上报相关寄存器 */ +#define CSR_PMBUS_PROC_REG_GEN_STATUS_ERR_RPT_REG (CSR_PMBUS_PROC_REG_GEN_BASE + 0xA8) /* 硬件调压异常状态上报相关寄存器 */ + +#endif // __AVS_REG_OFFSET_H__ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_arm_ras_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_arm_ras_reg_offset.h new file mode 100644 index 000000000..6f9d0602e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_arm_ras_reg_offset.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : ddrc_arm_ras_reg_offset.h + * Description : SPU DDRC ram_ras 相关寄存器偏移 + * History : 2023/04/19 11:05:46 Create file + */ + +#ifndef __DDRC_ARM_RAS_REG_OFFSET_H__ +#define __DDRC_ARM_RAS_REG_OFFSET_H__ + +/* ARM_RAS Base address of Module's Register */ +#define CSR_ARM_RAS_BASE (0x2000) + +/******************************************************************************/ +/* ARM_RAS Registers' Definitions */ +/******************************************************************************/ + +#define ARER_ERR_FR_L_REG (CSR_ARM_RAS_BASE + 0x0) +#define ARER_ERR_FR_H_REG (CSR_ARM_RAS_BASE + 0x4) +#define ARER_ERR_CTLR_L_REG (CSR_ARM_RAS_BASE + 0x8) +#define ARER_ERR_CTLR_H_REG (CSR_ARM_RAS_BASE + 0xC) +#define ARER_ERR_STATUS_L_REG (CSR_ARM_RAS_BASE + 0x10) +#define ARER_ERR_STATUS_H_REG (CSR_ARM_RAS_BASE + 0x14) +#define ARER_ERR_ADDR_L_REG (CSR_ARM_RAS_BASE + 0x18) +#define ARER_ERR_ADDR_H_REG (CSR_ARM_RAS_BASE + 0x1C) +#define ARER_ERR_MISC0_L_REG (CSR_ARM_RAS_BASE + 0x20) +#define ARER_ERR_MISC0_H_REG (CSR_ARM_RAS_BASE + 0x24) +#define ARER_ERR_MISC1_L_REG (CSR_ARM_RAS_BASE + 0x28) +#define ARER_ERR_MISC1_H_REG (CSR_ARM_RAS_BASE + 0x2C) + +#endif // __DDRC_ARM_RAS_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_dmc_c_union_def.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_dmc_c_union_def.h new file mode 100644 index 000000000..dc8a3c6f3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_dmc_c_union_def.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : ddrc_dmc_c_union_def.h + * Description : SPU DDRC DMC 相关寄存器结构体定义 + * History : 2023/04/19 11:05:46 Create file + */ + +#ifndef DDRC_DMC_C_UNION_DEFINE_H +#define DDRC_DMC_C_UNION_DEFINE_H + +/* Define the union csr_ddrc_cfg_workmode3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tdbi : 4 ; /* [3:0] */ + u32 tpl : 4 ; /* [7:4] */ + u32 tcal : 4 ; /* [11:8] */ + u32 twrcslat : 4 ; /* [15:12] */ + u32 trdcslat : 4 ; /* [19:16] */ + u32 rank_isolate : 8 ; /* [27:20] */ + u32 rank_intlv_gran : 2 ; /* [29:28] */ + u32 rsv_31 : 2 ; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ddrc_cfg_workmode3_u; + +/* Define the union csr_ddrc_cfg_ddrmode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dram_type : 4 ; /* [3:0] */ + u32 mem_width : 2 ; /* [5:4] */ + u32 ddr4_3ds_en : 1 ; /* [6] */ + u32 brstlen2 : 1 ; /* [7] */ + u32 brstlen : 1 ; /* [8] */ + u32 wr_2t_pre : 1 ; /* [9] */ + u32 rd_2t_pre : 1 ; /* [10] */ + u32 cmd_2t_en : 1 ; /* [11] */ + u32 bc_en : 1 ; /* [12] */ + u32 lpddr4_bl32 : 1 ; /* [13] */ + u32 scramb_en : 1 ; /* [14] */ + u32 crc_en : 1 ; /* [15] */ + u32 zqc_en : 1 ; /* [16] */ + u32 odt_on : 1 ; /* [17] */ + u32 rank_mode : 2 ; /* [19:18] */ + u32 ras_dev_x8_x4 : 1 ; /* [20] */ + u32 cs_2t_pos : 1 ; /* [21] */ + u32 sref_zqc_en : 1 ; /* [22] */ + u32 asref_zqc_en : 1 ; /* [23] */ + u32 bank_xor : 3 ; /* [26:24] */ + u32 bc_inv_tie1 : 1 ; /* [27] */ + u32 bank_mode : 4 ; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ddrc_cfg_ddrmode_u; + +/* Define the union csr_ddrc_cfg_dimm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 1 ; /* [0] */ + u32 rsv_34 : 3 ; /* [3:1] */ + u32 parity_en : 1 ; /* [4] */ + u32 rsv_35 : 3 ; /* [7:5] */ + u32 cke_share_map : 2 ; /* [9:8] */ + u32 rsv_36 : 2 ; /* [11:10] */ + u32 par_dly : 1 ; /* [12] */ + u32 rsv_37 : 3 ; /* [15:13] */ + u32 rnk_grp_pos : 4 ; /* [19:16] */ + u32 dimm_sch_gap_wr : 6 ; /* [25:20] */ + u32 dimm_sch_gap_rd : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ddrc_cfg_dimm_u; + +/* Define the union csr_ddrc_cfg_rnkvol_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_col : 3 ; /* [2:0] */ + u32 rsv_41 : 1 ; /* [3] */ + u32 mem_row : 3 ; /* [6:4] */ + u32 rsv_42 : 1 ; /* [7] */ + u32 mem_bank : 2 ; /* [9:8] */ + u32 mem_bankgroup : 2 ; /* [11:10] */ + u32 lg_rank : 2 ; /* [13:12] */ + u32 rank : 2 ; /* [15:14] */ + u32 total_vol : 10 ; /* [25:16] */ + u32 rsv_43 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ddrc_cfg_rnkvol_u; + +#endif // __DDRC_DMC_C_UNION_DEFINE_H__ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_dmc_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_dmc_reg_offset.h new file mode 100644 index 000000000..fe5d0da94 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_dmc_reg_offset.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : ddrc_dmc_reg_offset.h + * Description : SPU DDRC DMC 寄存器偏移 + * History : 2023/04/19 11:17:48 Create file + */ + +#ifndef __DDRC_DMC_REG_OFFSET_H__ +#define __DDRC_DMC_REG_OFFSET_H__ + +/* DMC Base address of Module's Register */ +#define CSR_DMC_BASE (0x0) + +/******************************************************************************/ +/* DMC Registers' Definitions */ +/******************************************************************************/ + +#define DDRC_CTRL_SREF_REG (CSR_DMC_BASE + 0x0) /* DDRC自刷新控制寄存器。 */ +#define DDRC_CTRL_INIT_REG (CSR_DMC_BASE + 0x4) /* DDRC初始化控制寄存器。 */ +#define DDRC_CTRL_DDRRST_REG (CSR_DMC_BASE + 0x8) /* 复位控制寄存器。 */ +#define DDRC_CTRL_SFC_REG (CSR_DMC_BASE + 0xC) /* DDRC软件配置DDR命令启动寄存器。 */ +#define DDRC_CTRL_PERF_REG (CSR_DMC_BASE + 0x10) /* DDRC性能统计使能寄存器。 */ +#define DDRC_CTRL_MTEST_REG (CSR_DMC_BASE + 0x14) /* DDRC软件配置EXMBIST启动寄存器。 */ +#define DDRC_CFG_LP_REG (CSR_DMC_BASE + 0x1C) /* dfi的lp接口的相关配置寄存器。 */ +#define DDRC_CFG_SREF_REG (CSR_DMC_BASE + 0x20) /* DDR自刷新配置寄存器。 */ +#define DDRC_CFG_PD_REG (CSR_DMC_BASE + 0x28) /* DDR低功耗PowerDown状态配置寄存器。 */ +#define DDRC_CFG_AREF_REG (CSR_DMC_BASE + 0x2C) /* DDRC自动刷新模式配置寄存器。 */ +#define DDRC_CFG_ECC_REG (CSR_DMC_BASE + 0x30) /* DDRC ECC配置寄存器。 */ +#define DDRC_CFG_ERRINJ_REG (CSR_DMC_BASE + 0x34) /* DDRC ECC错误注入配置寄存器。 */ +#define DDRC_CFG_FIFO_ERRINJ_REG (CSR_DMC_BASE + 0x38) /* DDRC ECC错误注入模式配置寄存器。 */ +#define DDRC_CFG_OPENPAGE_REG (CSR_DMC_BASE + 0x3C) /* DDRC的动态page策略控制寄存器。 */ +#define DDRC_CFG_WORKMODE_REG (CSR_DMC_BASE + 0x40) /* DDRC工作模式配置寄存器。 */ +#define DDRC_CFG_WORKMODE2_REG (CSR_DMC_BASE + 0x44) /* DDRC工作模式配置寄存器。 */ +#define DDRC_CFG_WORKMODE3_REG (CSR_DMC_BASE + 0x48) /* DDRC工作模式配置寄存器。 */ +#define DDRC_CFG_OPENPAGE2_REG (CSR_DMC_BASE + 0x4C) /* DDR动态Page策略状态寄存器 */ +#define DDRC_CFG_DDRMODE_REG (CSR_DMC_BASE + 0x50) /* DDR工作模式配置寄存器。 */ +#define DDRC_CFG_DIMM_REG (CSR_DMC_BASE + 0x54) /* 对接DIMM时工作模式配置寄存器。 */ +#define DDRC_CFG_SCRAMB_REG (CSR_DMC_BASE + 0x58) /* DDR数据加扰配置寄存器。 */ +#define DDRC_CFG_RNKVOL_0_REG (CSR_DMC_BASE + 0x60) /* DDRC控制的每个RANK的DDR容量配置寄存器。 */ +#define DDRC_CFG_RNKVOL_1_REG (CSR_DMC_BASE + 0x64) /* DDRC控制的每个RANK的DDR容量配置寄存器。 */ +#define DDRC_CFG_ODT_0_REG (CSR_DMC_BASE + 0xA0) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_1_REG (CSR_DMC_BASE + 0xA4) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_2_REG (CSR_DMC_BASE + 0xA8) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_3_REG (CSR_DMC_BASE + 0xAC) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_4_REG (CSR_DMC_BASE + 0xB0) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_5_REG (CSR_DMC_BASE + 0xB4) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_6_REG (CSR_DMC_BASE + 0xB8) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_ODT_7_REG (CSR_DMC_BASE + 0xBC) /* DDR的ODT特性配置寄存器。 */ +#define DDRC_CFG_CA_ODT_REG (CSR_DMC_BASE + 0xE0) /* LPDDR4的CA_ODT的配置寄存器。 */ +#define DDRC_CFG_TIMING0_REG (CSR_DMC_BASE + 0x100) /* DDRC的时序参数寄存器0。 */ +#define DDRC_CFG_TIMING1_REG (CSR_DMC_BASE + 0x104) /* DDRC的时序参数寄存器1。 */ +#define DDRC_CFG_TIMING2_REG (CSR_DMC_BASE + 0x108) /* DDRC的时序参数寄存器2。 */ +#define DDRC_CFG_TIMING3_REG (CSR_DMC_BASE + 0x10C) /* DDRC的时序参数寄存器3。 */ +#define DDRC_CFG_TIMING4_REG (CSR_DMC_BASE + 0x110) /* DDRC的时序参数寄存器4。 */ +#define DDRC_CFG_TIMING5_REG (CSR_DMC_BASE + 0x114) /* DDRC的时序参数寄存器5。 */ +#define DDRC_CFG_TIMING6_REG (CSR_DMC_BASE + 0x118) /* DDRC的时序参数寄存器6。 */ +#define DDRC_CFG_TIMING7_REG (CSR_DMC_BASE + 0x11C) /* DDRC的时序参数寄存器7。 */ +#define DDRC_CFG_TIMING8_REG (CSR_DMC_BASE + 0x120) /* DDRC的时序参数寄存器8。 */ +#define DDRC_CFG_NXT_TIMING0_REG (CSR_DMC_BASE + 0x124) /* 用于频率切换DDRC的时序参数寄存器0。 */ +#define DDRC_CFG_NXT_TIMING1_REG (CSR_DMC_BASE + 0x128) /* 用于频率切换的DDRC的时序参数寄存器1。 */ +#define DDRC_CFG_NXT_TIMING2_REG (CSR_DMC_BASE + 0x12C) /* 用于频率切换的DDRC的时序参数寄存器2。 */ +#define DDRC_CFG_NXT_TIMING3_REG (CSR_DMC_BASE + 0x130) /* 用于频率切换的DDRC的时序参数寄存器3。 */ +#define DDRC_CFG_NXT_TIMING4_REG (CSR_DMC_BASE + 0x134) /* 用于频率切换的DDRC的时序参数寄存器4。 */ +#define DDRC_CFG_NXT_TIMING5_REG (CSR_DMC_BASE + 0x138) /* 用于频率切换的DDRC的时序参数寄存器5。 */ +#define DDRC_CFG_NXT_TIMING6_REG (CSR_DMC_BASE + 0x13C) /* 用于频率切换的DDRC的时序参数寄存器6。 */ +#define DDRC_CFG_NXT_TIMING7_REG (CSR_DMC_BASE + 0x140) /* 用于频率切换的DDRC的时序参数寄存器7。 */ +#define DDRC_CFG_NXT_TIMING8_REG (CSR_DMC_BASE + 0x144) /* DDRC的时序参数寄存器8。 */ +#define DDRC_CFG_BLDATA_REG (CSR_DMC_BASE + 0x148) /* DDRC写数据预接收写数据配置寄存器。 */ +#define DDRC_CFG_DMCLVL_REG (CSR_DMC_BASE + 0x14C) /* DDR控制器命令队列深度水线配置寄存器。 */ +#define DDRC_CFG_TIMEOUT_REG (CSR_DMC_BASE + 0x150) /* 命令TIMEOUT配置寄存器。 */ +#define DDRC_CFG_QOS_REG (CSR_DMC_BASE + 0x154) /* 命令QOS配置寄存器。 */ +#define DDRC_CFG_EXMBIST_CMD_REG (CSR_DMC_BASE + 0x158) /* EXMBIST模块的命令配置寄存器。 */ +#define DDRC_CFG_EXMBIST_DAT_REG (CSR_DMC_BASE + 0x15C) /* DDRC_CFG_EXMBIST_DAT模块的数据DIN数据配置寄存器。 */ +#define DDRC_CFG_MBIST_REG (CSR_DMC_BASE + 0x160) /* MBIST的rank配置寄存器。 */ +#define DDRC_CFG_EXMBIST_CLK_MODE_REG (CSR_DMC_BASE + 0x164) /* EXMBIST时钟模式设置 */ +#define DDRC_CFG_OSC_PRD_REG (CSR_DMC_BASE + 0x178) /* Oscillator的读取间隔配置寄存器。 */ +#define DDRC_CFG_OSC_CFG_REG (CSR_DMC_BASE + 0x17C) /* Oacillator的配置寄存器。 */ +#define DDRC_CFG_TRAIN_REG (CSR_DMC_BASE + 0x180) /* DDRC训练寄存器。 */ +#define DDRC_CFG_DFI_LAT0_REG (CSR_DMC_BASE + 0x184) /* dfi接口时序配置寄存器. */ +#define DDRC_CFG_DFI_LAT1_REG (CSR_DMC_BASE + 0x188) /* dfi接口时序配置寄存器. */ +#define DDRC_CFG_REC0_REG (CSR_DMC_BASE + 0x190) /* DDR4错误恢复配置寄存器0。 */ +#define DDRC_CFG_REC1_REG (CSR_DMC_BASE + 0x194) /* DDR4错误恢复配置寄存器1。 */ +#define DDRC_CFG_CRC_REG (CSR_DMC_BASE + 0x198) /* DDR4 CRC配置寄存器。 */ +#define DDRC_CFG_CRC_ERRINJ0_REG (CSR_DMC_BASE + 0x1A0) /* CRC错误注入配置寄存器0。 */ +#define DDRC_CFG_CRC_ERRINJ1_REG (CSR_DMC_BASE + 0x1A4) /* CRC错误注入配置寄存器1。 */ +#define DDRC_CFG_PAR_ERRINJ0_REG (CSR_DMC_BASE + 0x1A8) /* PAR错误注入配置寄存器0。 */ +#define DDRC_CFG_PAR_ERRINJ1_REG (CSR_DMC_BASE + 0x1AC) /* PAR错误注入配置寄存器1。 */ +#define DDRC_CFG_DDRPHY_REG (CSR_DMC_BASE + 0x200) /* DDR IO配置寄存器。 */ +#define DDRC_CFG_AGING_REG (CSR_DMC_BASE + 0x204) /* DDRC_CFG_AGING是PHY的防老化配置寄存器。 */ +#define DDRC_CFG_SFC_TIM_REG (CSR_DMC_BASE + 0x20C) /* DDRC软件配置DDR命令的时序寄存器。 */ +#define DDRC_CFG_SFC_REG (CSR_DMC_BASE + 0x210) /* DDRC软件配置DDR命令属性命令。 */ +#define DDRC_CFG_SFC_ADDR0_REG (CSR_DMC_BASE + 0x214) /* SFC命令Que的配置寄存器。 */ +#define DDRC_CFG_SFC_ADDR1_REG (CSR_DMC_BASE + 0x218) /* SFC读写DRAM地址配置寄存器。 */ +#define DDRC_CFG_SFC_WDATA_REG (CSR_DMC_BASE + 0x21C) /* SFC写数据配置寄存器。 */ +#define DDRC_CFG_SFC_WCTRL_REG (CSR_DMC_BASE + 0x220) /* SFC写数据配置寄存器。 */ +#define DDRC_CFG_SFC_MASK0_REG (CSR_DMC_BASE + 0x224) /* DDRC软件配置DDR命令MASK寄存器。 */ +#define DDRC_CFG_SFC_MASK1_REG (CSR_DMC_BASE + 0x228) /* DDRC软件配置DDR命令MASK寄存器。 */ +#define DDRC_CFG_TMON_REG (CSR_DMC_BASE + 0x240) /* LPDDR2/LPDDR3器件温度检测周期配置寄存器。 */ +#define DDRC_CFG_TMON_RANK_REG (CSR_DMC_BASE + 0x244) /* LPDDR2/LPDDR3器件温度检测RANK配置寄存器。 */ +#define DDRC_CFG_TMON_AREF_REG (CSR_DMC_BASE + 0x248) /* LPDDR2/LPDDR3器件温度检测刷新配置寄存器。 */ +#define DDRC_CFG_EXRESP_REG (CSR_DMC_BASE + 0x24C) /* 返回额外的系统响应配置寄存器。 */ +#define DDRC_CFG_MRR_MAP_REG (CSR_DMC_BASE + 0x250) /* 单板连接重映射配置寄存器。 */ +#define DDRC_CFG_STADAT_REG (CSR_DMC_BASE + 0x254) /* DDRC数据统计使能寄存器。 */ +#define DDRC_CFG_DATMIN_REG (CSR_DMC_BASE + 0x258) /* DMC数据计数的最小阀值寄存器。 */ +#define DDRC_CFG_DATMAX_REG (CSR_DMC_BASE + 0x25C) /* DMC数据计数的最大阀值寄存器。 */ +#define DDRC_CFG_STACMD_REG (CSR_DMC_BASE + 0x260) /* DDRC性能统计使能寄存器。 */ +#define DDRC_CFG_CMDMIN_REG (CSR_DMC_BASE + 0x264) /* DMC命令计数的最小阀值寄存器。 */ +#define DDRC_CFG_CMDMAX_REG (CSR_DMC_BASE + 0x268) /* DMC命令计数的最大阀值寄存器。 */ +#define DDRC_CFG_PERF_REG (CSR_DMC_BASE + 0x26C) /* DDR性能统计的模式配置寄存器。 */ +#define DDRC_CFG_STAID_REG (CSR_DMC_BASE + 0x270) /* DDR性能统计的命令ID配置寄存器。 */ +#define DDRC_CFG_STAIDMSK_REG (CSR_DMC_BASE + 0x274) /* DDR性能统计的命令ID MASK配置寄存器。 */ +#define DDRC_CFG_DUM_EN_REG (CSR_DMC_BASE + 0x278) /* DDR的dummy read开关控制寄存器。 */ +#define DDRC_CFG_DUM_CFG_REG (CSR_DMC_BASE + 0x27C) /* DDR的dummy read功能的配置寄存器。 */ +#define DDRC_INTMSK_REG (CSR_DMC_BASE + 0x280) /* DDRC中断屏蔽寄存器。 */ +#define DDRC_RINT_REG (CSR_DMC_BASE + 0x284) /* DDRC原始中断寄存器。 */ +#define DDRC_INTSTS_REG (CSR_DMC_BASE + 0x288) /* DDRC中断状态寄存器。 */ +#define DDRC_CURR_STATUS_REG (CSR_DMC_BASE + 0x290) /* DDRC状态寄存器。 */ +#define DDRC_CURR_FUNC_REG (CSR_DMC_BASE + 0x294) /* DDRC FUNC模块状态寄存器。 */ +#define DDRC_CURR_FUNC2_REG (CSR_DMC_BASE + 0x298) /* DDRC FUNC模块状态寄存器。 */ +#define DDRC_CURR_FUNC3_REG (CSR_DMC_BASE + 0x29C) /* DDRC FUNC模块状态寄存器。 */ +#define DDRC_CURR_EXECST_REG (CSR_DMC_BASE + 0x2A0) /* DDRC命令状态机状态。 */ +#define DDRC_CURR_WGFIFOST_REG (CSR_DMC_BASE + 0x2A4) /* DDRC写FIFO空满状态寄存器。 */ +#define DDRC_CFG_ECC_CTRL_REG (CSR_DMC_BASE + 0x2A8) /* DDRC单/多比特第一次和最后一次结果读取控制寄存器。 */ +#define DDRC_HIS_SERR_ID_REG (CSR_DMC_BASE + 0x2AC) /* DDRC EC单比特错误ID寄存器。 */ +#define DDRC_HIS_SERR_ADR0_REG (CSR_DMC_BASE + 0x2D0) /* DDRC ECC单比特错误低位地址状态寄存器0。 */ +#define DDRC_HIS_SERR_ADR1_REG (CSR_DMC_BASE + 0x2D4) /* DDRC ECC单比特错误高位地址状态寄存器1。 */ +#define DDRC_HIS_SERR_RDATA0_REG (CSR_DMC_BASE + 0x2D8) /* DDR ECC单比特错误读数据0。 */ +#define DDRC_HIS_SERR_RDATA1_REG (CSR_DMC_BASE + 0x2DC) /* DDR ECC单比特错误读数据1。 */ +#define DDRC_HIS_SERR_RDATA2_REG (CSR_DMC_BASE + 0x2E0) /* DDR ECC单比特错误读数据2。 */ +#define DDRC_HIS_SERR_RDATA3_REG (CSR_DMC_BASE + 0x2E4) /* DDR ECC单比特错误读数据3。 */ +#define DDRC_HIS_SERR_RDATA4_REG (CSR_DMC_BASE + 0x2E8) /* DDR ECC单比特错误读数据4。 */ +#define DDRC_HIS_SERR_RDATA5_REG (CSR_DMC_BASE + 0x2EC) /* DDR ECC单比特错误读数据5。 */ +#define DDRC_HIS_SERR_RDATA6_REG (CSR_DMC_BASE + 0x2F0) /* DDR ECC单比特错误读数据6。 */ +#define DDRC_HIS_SERR_RDATA7_REG (CSR_DMC_BASE + 0x2F4) /* DDR ECC单比特错误读数据7。 */ +#define DDRC_HIS_SERR_RDATA8_REG (CSR_DMC_BASE + 0x2F8) /* DDR ECC单比特错误读数据8。 */ +#define DDRC_HIS_SERR_EXPDATA0_REG (CSR_DMC_BASE + 0x2FC) /* DDR ECC单比特错误时期望的正确读数据0。 */ +#define DDRC_HIS_SERR_EXPDATA1_REG (CSR_DMC_BASE + 0x300) /* DDR ECC单比特错误时期望的正确读数据1。 */ +#define DDRC_HIS_SERR_EXPDATA2_REG (CSR_DMC_BASE + 0x304) /* DDR ECC单比特错误时期望的正确读数据2。 */ +#define DDRC_HIS_SERR_EXPDATA3_REG (CSR_DMC_BASE + 0x308) /* DDR ECC单比特错误时期望的正确读数据3。 */ +#define DDRC_HIS_SERR_EXPDATA4_REG (CSR_DMC_BASE + 0x30C) /* DDR ECC单比特错误时期望的正确读数据4。 */ +#define DDRC_HIS_SERR_EXPDATA5_REG (CSR_DMC_BASE + 0x310) /* DDR ECC单比特错误时期望的正确读数据5。 */ +#define DDRC_HIS_SERR_EXPDATA6_REG (CSR_DMC_BASE + 0x314) /* DDR ECC单比特错误时期望的正确读数据6。 */ +#define DDRC_HIS_SERR_EXPDATA7_REG (CSR_DMC_BASE + 0x318) /* DDR ECC单比特错误时期望的正确读数据7。 */ +#define DDRC_HIS_SERR_EXPDATA8_REG (CSR_DMC_BASE + 0x31C) /* DDR ECC单比特错误时期望的正确读数据8。 */ +#define DDRC_HIS_MERR_ADR0_REG (CSR_DMC_BASE + 0x320) /* DDRC ECC多比特错误低位地址状态寄存器0。 */ +#define DDRC_HIS_MERR_ADR1_REG (CSR_DMC_BASE + 0x324) /* DDRC ECC多比特错误高位地址状态寄存器1。 */ +#define DDRC_HIS_MERR_ID_REG (CSR_DMC_BASE + 0x328) /* DDRC ECC多比特错误ID寄存器。 */ +#define DDRC_HIS_MERR_RDATA0_REG (CSR_DMC_BASE + 0x330) /* DDR ECC多比特错误读数据0。 */ +#define DDRC_HIS_MERR_RDATA1_REG (CSR_DMC_BASE + 0x334) /* DDR ECC多比特错误读数据1。 */ +#define DDRC_HIS_MERR_RDATA2_REG (CSR_DMC_BASE + 0x338) /* DDR ECC多比特错误读数据2。 */ +#define DDRC_HIS_MERR_RDATA3_REG (CSR_DMC_BASE + 0x33C) /* DDR ECC多比特错误读数据3。 */ +#define DDRC_HIS_MERR_RDATA4_REG (CSR_DMC_BASE + 0x340) /* DDR ECC多比特错误读数据4。 */ +#define DDRC_HIS_MERR_RDATA5_REG (CSR_DMC_BASE + 0x344) /* DDR ECC多比特错误读数据5。 */ +#define DDRC_HIS_MERR_RDATA6_REG (CSR_DMC_BASE + 0x348) /* DDR ECC多比特错误读数据6。 */ +#define DDRC_HIS_MERR_RDATA7_REG (CSR_DMC_BASE + 0x34C) /* DDR ECC多比特错误读数据7。 */ +#define DDRC_HIS_MERR_RDATA8_REG (CSR_DMC_BASE + 0x350) /* DDR ECC多比特错误读数据8。 */ +#define DDRC_HIS_MERR_EXPDATA0_REG (CSR_DMC_BASE + 0x354) /* DDR ECC多比特错误时期望的正确读数据0。 */ +#define DDRC_HIS_MERR_EXPDATA1_REG (CSR_DMC_BASE + 0x358) /* DDR ECC多比特错误时期望的正确读数据1。 */ +#define DDRC_HIS_MERR_EXPDATA2_REG (CSR_DMC_BASE + 0x35C) /* DDR ECC多比特错误时期望的正确读数据2。 */ +#define DDRC_HIS_MERR_EXPDATA3_REG (CSR_DMC_BASE + 0x360) /* DDR ECC多比特错误时期望的正确读数据3。 */ +#define DDRC_HIS_MERR_EXPDATA4_REG (CSR_DMC_BASE + 0x364) /* DDR ECC多比特错误时期望的正确读数据4。 */ +#define DDRC_HIS_MERR_EXPDATA5_REG (CSR_DMC_BASE + 0x368) /* DDR ECC多比特错误时期望的正确读数据5。 */ +#define DDRC_HIS_MERR_EXPDATA6_REG (CSR_DMC_BASE + 0x36C) /* DDR ECC多比特错误时期望的正确读数据6。 */ +#define DDRC_HIS_MERR_EXPDATA7_REG (CSR_DMC_BASE + 0x370) /* DDR ECC多比特错误时期望的正确读数据7。 */ +#define DDRC_HIS_MERR_EXPDATA8_REG (CSR_DMC_BASE + 0x374) /* DDR ECC多比特错误时期望的正确读数据8。 */ +#define DDRC_HIS_SERRCNT_REG (CSR_DMC_BASE + 0x378) /* DDRC的ECC错误统计寄存器。 */ +#define DDRC_HIS_MERRCNT_REG (CSR_DMC_BASE + 0x37C) /* DDRC的ECC错误统计寄存器。 */ +#define DDRC_HIS_FLUX_WR_REG (CSR_DMC_BASE + 0x380) /* DDRC所有写命令流量统计寄存器。 */ +#define DDRC_HIS_FLUX_RD_REG (CSR_DMC_BASE + 0x384) /* DDRC所有读命令流量统计寄存器。 */ +#define DDRC_HIS_FLUX_WCMD_REG (CSR_DMC_BASE + 0x388) /* DDRC所有写命令数目。 */ +#define DDRC_HIS_FLUX_RCMD_REG (CSR_DMC_BASE + 0x38C) /* DDRC所有读命令数目。 */ +#define DDRC_HIS_FLUXID_WR_REG (CSR_DMC_BASE + 0x390) /* DDRC指定ID写流量统计寄存器。 */ +#define DDRC_HIS_FLUXID_RD_REG (CSR_DMC_BASE + 0x394) /* DDRC指定ID读流量统计寄存器。 */ +#define DDRC_HIS_FLUXID_WCMD_REG (CSR_DMC_BASE + 0x398) /* DDRC指定ID所有写命令数目。 */ +#define DDRC_HIS_FLUXID_RCMD_REG (CSR_DMC_BASE + 0x39C) /* DDRC指定ID所有读命令数目。 */ +#define DDRC_HIS_WLATCNT0_REG (CSR_DMC_BASE + 0x3A0) /* DDRC指定ID的写命令Latency统计寄存器0。 */ +#define DDRC_HIS_WLATCNT1_REG (CSR_DMC_BASE + 0x3A4) /* DDRC指定ID的写命令Latency统计寄存器1。 */ +#define DDRC_HIS_RLATCNT0_REG (CSR_DMC_BASE + 0x3A8) /* DDRC指定ID的读命令Latency统计寄存器0。 */ +#define DDRC_HIS_RLATCNT1_REG (CSR_DMC_BASE + 0x3AC) /* DDRC指定ID的读命令Latency统计寄存器1。 */ +#define DDRC_HIS_INHERE_RLAT_CNT_REG (CSR_DMC_BASE + 0x3B0) /* 读通道固有延时寄存器。 */ +#define DDRC_STAT_RPT_REG (CSR_DMC_BASE + 0x3B4) /* DMC命令计数的累积寄存器的读指针。 */ +#define DDRC_HIS_CMD_SUM_REG (CSR_DMC_BASE + 0x3B8) /* DMC命令计数的累积寄存器。 */ +#define DDRC_HIS_DAT_SUM_REG (CSR_DMC_BASE + 0x3BC) /* DMC数据计数的累积寄存器。 */ +#define DDRC_HIS_PRE_CMD_REG (CSR_DMC_BASE + 0x3C0) /* DDRC所有统计的PRECHARGE命令个数。 */ +#define DDRC_HIS_ACT_CMD_REG (CSR_DMC_BASE + 0x3C4) /* DDRC所有统计的ACTIVE命令个数。 */ +#define DDRC_HIS_BNK_CHG_REG (CSR_DMC_BASE + 0x3C8) /* DDRC所有统计的BANK切换次数。 */ +#define DDRC_HIS_RNK_CHG_REG (CSR_DMC_BASE + 0x3CC) /* DDRC所有统计的读写命令片选切换次数。 */ +#define DDRC_HIS_RW_CHG_REG (CSR_DMC_BASE + 0x3D0) /* DDRC所有统计的读写命令切换次数。 */ +#define DDRC_HIS_TMON_ERR_REG (CSR_DMC_BASE + 0x3E0) /* DMC循环读取LPDDR2/LPDDR3温度的错误状态寄存器。 */ +#define DDRC_HIS_RERR_ADDRL_REG (CSR_DMC_BASE + 0x3F0) /* 访问DMC禁止的RANK错误低位地址寄存器。 */ +#define DDRC_HIS_RERR_ADDRH_REG (CSR_DMC_BASE + 0x3F4) /* 访问DMC禁止的RANK错误高位地址寄存器。 */ +#define DDRC_HIS_RERR_ID_REG (CSR_DMC_BASE + 0x3F8) /* 访问DMC禁止的RANK错误ID寄存器。 */ +#define DDRC_HIS_RERR_CNT_REG (CSR_DMC_BASE + 0x3FC) /* 访问DMC禁止的RANK累积错误个数寄存器。 */ +#define DDRC_HIS_REC_ERR0_REG (CSR_DMC_BASE + 0x400) /* DMC错误恢复过程中错误信息寄存器0。 */ +#define DDRC_HIS_REC_ERR1_REG (CSR_DMC_BASE + 0x404) /* DMC错误恢复过程中错误信息寄存器1。 */ +#define DDRC_HIS_EXMBIST_STATUS_REG (CSR_DMC_BASE + 0x40C) /* EXMBIST模块的状态寄存器。 */ +#define DDRC_HIS_SFC_RDATA_REG (CSR_DMC_BASE + 0x4A8) /* SFC读数据寄存器。 */ +#define DDRC_SFC_RCTRL_REG (CSR_DMC_BASE + 0x4AC) /* SFC读数据指针寄存器。 */ +#define DDRC_HIS_SFC_RDATA0_DBI_REG (CSR_DMC_BASE + 0x4C8) /* 读数据对应的DBI寄存器。 */ +#define DDRC_HIS_SFC_RDATA1_DBI_REG (CSR_DMC_BASE + 0x4CC) /* 读数据对应的DBI寄存器。 */ +#define DDRC_HIS_SFC_RDATA_ECC_DBI_REG (CSR_DMC_BASE + 0x4D0) /* 读ECC数据对应的DBI寄存器。 */ +#define DDRC_FUNC_STAT0_REG (CSR_DMC_BASE + 0x4D4) /* fun的握手状态寄存器0。 */ +#define DDRC_FUNC_STAT1_REG (CSR_DMC_BASE + 0x4D8) /* fun的握手状态寄存器1。 */ +#define DDRC_FUNC_STAT2_REG (CSR_DMC_BASE + 0x4DC) /* fun的握手状态寄存器2。 */ +#define DDRC_FUNC_STAT3_REG (CSR_DMC_BASE + 0x4E0) /* fun的握手状态寄存器3。 */ +#define DDRC_FUNC_STAT4_REG (CSR_DMC_BASE + 0x4E4) /* fun的握手状态寄存器4。 */ +#define DDRC_FUNC_STAT5_REG (CSR_DMC_BASE + 0x4E8) /* fun的握手状态寄存器5。 */ +#define DDRC_FUNC_STAT6_REG (CSR_DMC_BASE + 0x4EC) /* fun的握手状态寄存器6。 */ +#define DDRC_FUNC_STAT7_REG (CSR_DMC_BASE + 0x4F0) /* fun的握手状态寄存器7。 */ +#define DDRC_FUNC_STAT8_REG (CSR_DMC_BASE + 0x4F4) /* fun的握手状态寄存器8。 */ +#define DDRC_FUNC_STAT9_REG (CSR_DMC_BASE + 0x4F8) /* fun的握手状态寄存器9。 */ +#define DDRC_FUNC_STAT10_REG (CSR_DMC_BASE + 0x4FC) /* fun的握手状态寄存器10。 */ +#define DDRC_FUNC_STAT11_REG (CSR_DMC_BASE + 0x500) /* fun的握手状态寄存器11。 */ +#define DDRC_DMC_STAT12_REG (CSR_DMC_BASE + 0x504) /* fun的握手状态寄存器12。 */ +#define DDRC_TEST_RAM_TMOD_REG (CSR_DMC_BASE + 0x508) /* DDR 中RAM的测试模式配置寄存器。 */ +#define DDRC_TEST_RTL_CFG0_REG (CSR_DMC_BASE + 0x510) /* DDRC RTL参数信息寄存器0。 */ +#define DDRC_TEST_RTL_CFG1_REG (CSR_DMC_BASE + 0x514) /* DDRC RTL参数信息寄存器1。 */ +#define DDRC_TEST_RTL_CFG2_REG (CSR_DMC_BASE + 0x518) /* DDRC RTL参数信息寄存器2。 */ +#define DDRC_OSC_COUNT_0_REG (CSR_DMC_BASE + 0x520) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_1_REG (CSR_DMC_BASE + 0x524) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_2_REG (CSR_DMC_BASE + 0x528) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_3_REG (CSR_DMC_BASE + 0x52C) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_4_REG (CSR_DMC_BASE + 0x530) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_5_REG (CSR_DMC_BASE + 0x534) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_6_REG (CSR_DMC_BASE + 0x538) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_OSC_COUNT_7_REG (CSR_DMC_BASE + 0x53C) /* Oscillator回读的值及基准寄存器的值。 */ +#define DDRC_EDXN_DQMAP_0_REG (CSR_DMC_BASE + 0x580) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_1_REG (CSR_DMC_BASE + 0x588) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_2_REG (CSR_DMC_BASE + 0x590) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_3_REG (CSR_DMC_BASE + 0x598) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_4_REG (CSR_DMC_BASE + 0x5A0) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_5_REG (CSR_DMC_BASE + 0x5A8) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_6_REG (CSR_DMC_BASE + 0x5B0) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_7_REG (CSR_DMC_BASE + 0x5B8) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_EDXN_DQMAP_8_REG (CSR_DMC_BASE + 0x5C0) /* 偶数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_0_REG (CSR_DMC_BASE + 0x584) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_1_REG (CSR_DMC_BASE + 0x58C) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_2_REG (CSR_DMC_BASE + 0x594) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_3_REG (CSR_DMC_BASE + 0x59C) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_4_REG (CSR_DMC_BASE + 0x5A4) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_5_REG (CSR_DMC_BASE + 0x5AC) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_6_REG (CSR_DMC_BASE + 0x5B4) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_7_REG (CSR_DMC_BASE + 0x5BC) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_ODXN_DQMAP_8_REG (CSR_DMC_BASE + 0x5C4) /* 奇数rank的DQ MAP寄存器。 */ +#define DDRC_CFG_SFC_EXTCMD_CTRL_REG (CSR_DMC_BASE + 0x600) /* SFC扩展命令控制寄存器。 */ +#define DDRC_CFG_SFC_LOOP_CTRL_REG (CSR_DMC_BASE + 0x604) /* SFC命令序列执行循环次数设置。 */ +#define DDRC_CFG_SFC_BER_RD_RPT_REG (CSR_DMC_BASE + 0x608) /* BER测试连续读命令循环次数设置。 */ +#define DDRC_CFG_SFC_HEAD_TAIL_CUT_REG (CSR_DMC_BASE + 0x60C) /* BER测试掐头去尾设置。 */ +#define DDRC_CFG_SFC_PAT_PRD_REG (CSR_DMC_BASE + 0x610) /* SFC pattern周期设置寄存器。 */ +#define DDRC_CFG_SFC_WL_CTRL_REG (CSR_DMC_BASE + 0x614) /* SFC write leveling脉冲配置寄存器 */ +#define DDRC_CFG_SFC_ADDR2_REG (CSR_DMC_BASE + 0x618) /* SFC地址配置寄存器2 */ +#define DDRC_CFG_SFC_ADDR3_REG (CSR_DMC_BASE + 0x61C) /* SFC地址配置寄存器3 */ +#define DDRC_CFG_SFC_PAT_SEL_REG (CSR_DMC_BASE + 0x620) /* SFC pattern选择配置寄存器 */ +#define DDRC_CFG_SFC_PAT_SEL_PTR_REG (CSR_DMC_BASE + 0x624) /* SFC pattern选择配置指针 */ +#define DDRC_CFG_SFC_CMP_MASK_REG (CSR_DMC_BASE + 0x628) /* 读数据比对mask设置 */ +#define DDRC_CFG_SFC_CMP_MASK_PTR_REG (CSR_DMC_BASE + 0x62C) /* 读数据比对mask指针 */ +#define DDRC_CFG_SFC_TIM2_REG (CSR_DMC_BASE + 0x630) /* SFC rank切换保留时序参数。 */ +#define DDRC_CFG_SFC_INIT_SEED_REG (CSR_DMC_BASE + 0x634) /* SFC PRBS序列初始种子 */ +#define DDRC_CFG_SFC_INIT_SEED1_REG (CSR_DMC_BASE + 0x638) /* SFC PRBS序列初始种子1 */ +#define DDRC_CFG_SFC_INIT_SEED2_REG (CSR_DMC_BASE + 0x63C) /* SFC PRBS序列初始种子2 */ +#define DDRC_CFG_SFC_INIT_SEED3_REG (CSR_DMC_BASE + 0x640) /* SFC PRBS序列初始种子3 */ +#define DDRC_CFG_SFC_INIT_SEED4_REG (CSR_DMC_BASE + 0x644) /* SFC PRBS序列初始种子4 */ +#define DDRC_CFG_SFC_INIT_SEED5_REG (CSR_DMC_BASE + 0x648) /* SFC PRBS序列初始种子5 */ +#define DDRC_CFG_SFC_INIT_SEED6_REG (CSR_DMC_BASE + 0x64C) /* SFC PRBS序列初始种子6 */ +#define DDRC_CFG_SFC_INIT_SEED7_REG (CSR_DMC_BASE + 0x650) /* SFC PRBS序列初始种子7 */ +#define DDRC_HIS_SFC_DQS_POS_ERR_0_REG (CSR_DMC_BASE + 0x654) /* SFC DQS posedge错误状态信息。 */ +#define DDRC_HIS_SFC_DQS_POS_ERR_1_REG (CSR_DMC_BASE + 0x658) /* SFC DQS posedge错误状态信息。 */ +#define DDRC_HIS_SFC_DQS_POS_ERR_2_REG (CSR_DMC_BASE + 0x65C) /* SFC DQS posedge错误状态信息。 */ +#define DDRC_HIS_SFC_DQS_NEG_ERR_0_REG (CSR_DMC_BASE + 0x660) /* SFC DQS negedge错误状态信息。 */ +#define DDRC_HIS_SFC_DQS_NEG_ERR_1_REG (CSR_DMC_BASE + 0x664) /* SFC DQS negedge错误状态信息。 */ +#define DDRC_HIS_SFC_DQS_NEG_ERR_2_REG (CSR_DMC_BASE + 0x668) /* SFC DQS negedge错误状态信息。 */ +#define DDRC_HIS_SFC_PER_NIB_ERR_REG (CSR_DMC_BASE + 0x66C) /* SFC per-nibble错误状态信息。 */ +#define DDRC_HIS_SFC_PER_BYTE_ERR_REG (CSR_DMC_BASE + 0x670) /* SFC per-byte错误状态信息。 */ +#define DDRC_HIS_SFC_ANY_ERR_REG (CSR_DMC_BASE + 0x674) /* SFC写读循环有读数据错误。 */ +#define DDRC_HIS_SFC_QUE_CUR_PTR_REG (CSR_DMC_BASE + 0x678) /* SFC命令队列当前指针。 */ +#define DDRC_HIS_SFC_ERR_NUM_REG (CSR_DMC_BASE + 0x67C) /* SFC读数据错误计数。 */ +#define DDRC_CFG_AC_ISI_PAT_REG (CSR_DMC_BASE + 0x680) /* 恶化AC line码间干扰pattern。 */ +#define DDRC_CFG_AC_ISI_PTR_REG (CSR_DMC_BASE + 0x684) /* 恶化AC line码间干扰pattern配置指针。 */ +#define DDRC_HIS_BG_CHG_REG (CSR_DMC_BASE + 0x688) /* DDRC所有统计的BG切换次数。 */ +#define DDRC_CURR_EXEC_STATE_REG (CSR_DMC_BASE + 0x68C) /* DMC_EXEC状态机当前状态。 */ +#define DDRC_PHYUPD_REQ_CNT_REG (CSR_DMC_BASE + 0x690) /* dfi_phyupd_req拉高时间统计。 */ +#define DDRC_PHYUPD_EXIT_WAIT_REG (CSR_DMC_BASE + 0x694) /* PHY UPD退出时间配置 */ +#define DDRC_CFG_TIMING9_REG (CSR_DMC_BASE + 0x698) /* 时序参数设置寄存器9。 */ +#define DDRC_CFG_NXT_TIMING9_REG (CSR_DMC_BASE + 0x69C) /* 用于频率切换的DDRC的时序参数寄存器9。 */ +#define DDRC_CFG_CE_CNT_TH_REG (CSR_DMC_BASE + 0x6A0) /* DMC CE错误计数器门限设置。 */ +#define DDRC_CFG_FUNNEL_CTRL_REG (CSR_DMC_BASE + 0x6A4) /* CE错误漏斗计数控制寄存器。 */ +#define DDRC_CFG_FUNNEL_BASE_REG (CSR_DMC_BASE + 0x6A8) /* CE错误漏斗计数器单位计数。 */ +#define DDRC_CFG_FUNNEL_TH_REG (CSR_DMC_BASE + 0x6AC) /* CE错误漏斗计数器门限设置。 */ +#define DDRC_HIS_SRAM_CE_CNT_REG (CSR_DMC_BASE + 0x6B0) /* SRAM ECC CE错误个数。 */ +#define DDRC_HIS_DP_CE_CNT_REG (CSR_DMC_BASE + 0x6B4) /* 数据通路ECC CE错误个数。 */ +#define DDRC_CFG_AC_PIPE_REG (CSR_DMC_BASE + 0x6B8) /* AC信号pipeline级数设置 */ +#define DDRC_HIS_AREF_PSTPND_CNT_REG (CSR_DMC_BASE + 0x6BC) /* AREF postponed计数器当前值。 */ +#define DDRC_PERF_EVENT_EN_REG (CSR_DMC_BASE + 0x6C0) /* 性能统计事件的使能控制配置 */ +#define DDRC_PERF_INTR_REG (CSR_DMC_BASE + 0x6C4) /* 性能统计事件溢出原始中断状态寄存器 */ +#define DDRC_PERF_INTM_REG (CSR_DMC_BASE + 0x6C8) /* 性能统计事件溢出中断屏蔽寄存器 */ +#define DDRC_PERF_INTS_REG (CSR_DMC_BASE + 0x6CC) /* 性能统计事件溢出中断状态寄存器 */ +#define DDRC_PERF_INTC_REG (CSR_DMC_BASE + 0x6D0) /* 性能统计实际溢出中断清除寄存器 */ +#define DDRC_SRAM_ERR_ADDR0_REG (CSR_DMC_BASE + 0x6D4) /* SRAM ECC错误地址记录0 */ +#define DDRC_SRAM_ERR_ADDR1_REG (CSR_DMC_BASE + 0x6D8) /* SRAM ECC错误地址记录1 */ +#define DDRC_SRAM_ERR_ADDR2_REG (CSR_DMC_BASE + 0x6DC) /* SRAM ECC错误地址记录2 */ +#define DDRC_CFG_IN_RANK_MIRROR_REG (CSR_DMC_BASE + 0x6E0) /* In Rank Mirror功能配置寄存器 */ +#define DDRC_CFG_CH_SYNC_AREF_REG (CSR_DMC_BASE + 0x6E4) /* 通道间同步刷新功能配置寄存器 */ +#define DDRC_CFG_RES0_REG (CSR_DMC_BASE + 0x700) /* DMC保留寄存器0。 */ +#define DDRC_CFG_RES1_REG (CSR_DMC_BASE + 0x704) /* DMC保留寄存器1。 */ +#define DDRC_CFG_RES2_REG (CSR_DMC_BASE + 0x708) /* DMC保留寄存器2。 */ +#define DDRC_CFG_RES3_REG (CSR_DMC_BASE + 0x70C) /* DMC保留寄存器3。 */ +#define DDRC_CFG_RES4_REG (CSR_DMC_BASE + 0x710) /* DMC保留寄存器4。 */ +#define DDRC_CFG_RES5_REG (CSR_DMC_BASE + 0x714) /* DMC保留寄存器5。 */ +#define DDRC_CFG_RES6_REG (CSR_DMC_BASE + 0x718) /* DMC保留寄存器6。 */ +#define DDRC_CFG_RES7_REG (CSR_DMC_BASE + 0x71C) /* DMC保留寄存器7。 */ +#define DDRC_CFG_MAGIC_WORD_REG (CSR_DMC_BASE + 0x7F0) /* DMC magic word。 */ +#define DDRC_CFG_VERSION_REG (CSR_DMC_BASE + 0xC10) /* DMC版本寄存器。 */ + +#endif // __DDRC_DMC_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_rasc_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_rasc_c_union_define.h new file mode 100644 index 000000000..092343cdf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_rasc_c_union_define.h @@ -0,0 +1,1411 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : ddrc_rasc_reg_offset.h + * Description : SPU DDRC rasc 结构体定义 + * History : 2023/04/19 11:22:23 Create file + */ + +#ifndef __DDRC_RASC_C_UNION_DEFINE_H__ +#define __DDRC_RASC_C_UNION_DEFINE_H__ + +/* Define the union csr_rasc_ctrl_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ras_en : 1 ; /* [0] */ + u32 poison_en : 1 ; /* [1] */ + u32 ds_en : 1 ; /* [2] */ + u32 rd_chk_bys : 1 ; /* [3] */ + u32 sw_chk_type : 1 ; /* [4] */ + u32 rsv_0 : 27 ; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_mode_u; + +/* Define the union csr_rasc_ctrl_adddc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 adddc_region0_start : 1 ; /* [0] */ + u32 adddc_region1_start : 1 ; /* [1] */ + u32 virtual_lockstep_en : 1 ; /* [2] */ + u32 rsv_1 : 29 ; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_adddc_u; + +/* Define the union csr_rasc_ctrl_pascrub_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pascrub_en : 1 ; /* [0] */ + u32 rsv_2 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_pascrub_u; + +/* Define the union csr_rasc_ctrl_sparing_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rnksp_start : 1 ; /* [0] */ + u32 devsp_start : 1 ; /* [1] */ + u32 rsv_3 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_sparing_u; + +/* Define the union csr_rasc_ctrl_flush_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flush_en : 1 ; /* [0] */ + u32 rsv_4 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_flush_u; + +/* Define the union csr_rasc_ctrl_errinj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_start : 1 ; /* [0] */ + u32 rsv_5 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_errinj_u; + +/* Define the union csr_rasc_ctrl_funnel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 funnel_en : 1 ; /* [0] */ + u32 rsv_6 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_ctrl_funnel_u; + +/* Define the union csr_rasc_cfg_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dev_width : 1 ; /* [0] */ + u32 dev_3ds : 1 ; /* [1] */ + u32 mem_rankgroup : 2 ; /* [3:2] */ + u32 ras_clkon : 1 ; /* [4] */ + u32 rsv_7 : 3 ; /* [7:5] */ + u32 rsv_8 : 8 ; /* [15:8] */ + u32 dram_type : 4 ; /* [19:16] */ + u32 rsv_9 : 12 ; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_mode_u; + +/* Define the union csr_rasc_cfg_rankmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_col : 3 ; /* [2:0] */ + u32 rsv_10 : 1 ; /* [3] */ + u32 mem_row : 3 ; /* [6:4] */ + u32 rsv_11 : 1 ; /* [7] */ + u32 mem_bank : 2 ; /* [9:8] */ + u32 rsv_12 : 2 ; /* [11:10] */ + u32 mem_logic_rank : 2 ; /* [13:12] */ + u32 rsv_13 : 2 ; /* [15:14] */ + u32 mem_rank : 2 ; /* [17:16] */ + u32 rsv_14 : 2 ; /* [19:18] */ + u32 mem_bg : 2 ; /* [21:20] */ + u32 rsv_15 : 10 ; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rankmap_u; + +/* Define the union csr_rasc_cfg_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 all_errcnt_clr : 1 ; /* [0] */ + u32 ha_errcnt_clr : 1 ; /* [1] */ + u32 vls_errcnt_clr : 1 ; /* [2] */ + u32 rvls_errcnt_clr : 1 ; /* [3] */ + u32 pa_errcnt_clr : 1 ; /* [4] */ + u32 sp_errcnt_clr : 1 ; /* [5] */ + u32 sp_rberrcnt_clr : 1 ; /* [6] */ + u32 rsv_16 : 1 ; /* [7] */ + u32 corr_errcnt_clr : 1 ; /* [8] */ + u32 uncorr_errcnt_clr : 1 ; /* [9] */ + u32 rsv_17 : 22 ; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_clr_u; + +/* Define the union csr_rasc_cfg_info_rnk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 idx_rnk : 4 ; /* [3:0] */ + u32 rnk_sel_mode : 1 ; /* [4] */ + u32 rsv_18 : 27 ; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_info_rnk_u; + +/* Define the union csr_rasc_cfg_info_devidx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dev_idx_search_en : 1 ; /* [0] */ + u32 dev_search_offset_en : 1 ; /* [1] */ + u32 rsv_19 : 2 ; /* [3:2] */ + u32 dev_idx_rank : 4 ; /* [7:4] */ + u32 dev_idx_device : 5 ; /* [12:8] */ + u32 rsv_20 : 19 ; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_info_devidx_u; + +/* Define the union csr_rasc_cfg_info_bnkidx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bnk_idx_search_en : 1 ; /* [0] */ + u32 bnk_search_offset_en : 1 ; /* [1] */ + u32 rsv_21 : 2 ; /* [3:2] */ + u32 bnkidx_rnk : 4 ; /* [7:4] */ + u32 bnkidx_dev : 5 ; /* [12:8] */ + u32 rsv_22 : 3 ; /* [15:13] */ + u32 bnkidx_bnk : 4 ; /* [19:16] */ + u32 rsv_23 : 12 ; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_info_bnkidx_u; + +/* Define the union csr_rasc_cfg_pastart_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dimm_start_rank : 2 ; /* [1:0] */ + u32 rsv_24 : 2 ; /* [3:2] */ + u32 dimm_start_bank : 4 ; /* [7:4] */ + u32 dimm_start_row : 18 ; /* [25:8] */ + u32 dimm_start_lgrank : 3 ; /* [28:26] */ + u32 rsv_25 : 3 ; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_pastart_u; + +/* Define the union csr_rasc_cfg_paend_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dimm_end_rank : 2 ; /* [1:0] */ + u32 rsv_26 : 2 ; /* [3:2] */ + u32 dimm_end_bank : 4 ; /* [7:4] */ + u32 dimm_end_row : 18 ; /* [25:8] */ + u32 dimm_end_lgrank : 3 ; /* [28:26] */ + u32 rsv_27 : 3 ; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_paend_u; + +/* Define the union csr_rasc_cfg_ps_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rcmd_num : 4 ; /* [3:0] */ + u32 interval_time : 24 ; /* [27:4] */ + u32 ps_type : 2 ; /* [29:28] */ + u32 rsv_28 : 2 ; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_ps_u; + +/* Define the union csr_rasc_cfg_adddc_region0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 region0_enable : 1 ; /* [0] */ + u32 region0_size : 2 ; /* [2:1] */ + u32 rsv_29 : 2 ; /* [4:3] */ + u32 region0_fail_dev : 5 ; /* [9:5] */ + u32 region0_fail_rnk : 4 ; /* [13:10] */ + u32 region0_fail_bnk : 4 ; /* [17:14] */ + u32 region0_buddy_rnk : 4 ; /* [21:18] */ + u32 region0_buddy_bnk : 4 ; /* [25:22] */ + u32 rsv_30 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_adddc_region0_u; + +/* Define the union csr_rasc_cfg_adddc_region1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 region1_enable : 1 ; /* [0] */ + u32 region1_size : 2 ; /* [2:1] */ + u32 region1_vls_type : 2 ; /* [4:3] */ + u32 region1_fail_dev : 5 ; /* [9:5] */ + u32 region1_fail_rnk : 4 ; /* [13:10] */ + u32 region1_fail_bnk : 4 ; /* [17:14] */ + u32 region1_buddy_rnk : 4 ; /* [21:18] */ + u32 region1_buddy_bnk : 4 ; /* [25:22] */ + u32 rsv_31 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_adddc_region1_u; + +/* Define the union csr_rasc_cfg_adddc_rvls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 region1_buddy0_rnk : 4 ; /* [3:0] */ + u32 region1_buddy0_bnk : 4 ; /* [7:4] */ + u32 region1_buddy1_rnk : 4 ; /* [11:8] */ + u32 region1_buddy1_bnk : 4 ; /* [15:12] */ + u32 rsv_32 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_adddc_rvls_u; + +/* Define the union csr_rasc_cfg_vls_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vls_addr_window : 8 ; /* [7:0] */ + u32 vls_interval_time : 8 ; /* [15:8] */ + u32 vls_cmd_num : 5 ; /* [20:16] */ + u32 rsv_33 : 11 ; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_vls_interval_u; + +/* Define the union csr_rasc_cfg_vls_x8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x8_buddy_rank_0 : 4 ; /* [3:0] */ + u32 x8_buddy_rank_1 : 4 ; /* [7:4] */ + u32 x8_buddy_rank_2 : 4 ; /* [11:8] */ + u32 x8_buddy_rank_3 : 4 ; /* [15:12] */ + u32 x8_buddy_rank_4 : 4 ; /* [19:16] */ + u32 x8_buddy_rank_5 : 4 ; /* [23:20] */ + u32 x8_buddy_rank_6 : 4 ; /* [27:24] */ + u32 x8_buddy_rank_7 : 4 ; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_vls_x8_u; + +/* Define the union csr_rasc_cfg_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 backup_rnk : 4 ; /* [3:0] */ + u32 source_rnk : 4 ; /* [7:4] */ + u32 sp_region_sel : 1 ; /* [8] */ + u32 rd_retry_en : 1 ; /* [9] */ + u32 rdback_en : 1 ; /* [10] */ + u32 rsv_34 : 1 ; /* [11] */ + u32 source_dev : 5 ; /* [16:12] */ + u32 rsv_35 : 15 ; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_sp_u; + +/* Define the union csr_rasc_cfg_spr_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_addr_window : 8 ; /* [7:0] */ + u32 sp_interval_time : 8 ; /* [15:8] */ + u32 rsv_36 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_spr_interval_u; + +/* Define the union csr_rasc_cfg_spr_outstanding_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_cmd_outstanding : 5 ; /* [4:0] */ + u32 rsv_37 : 27 ; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_spr_outstanding_u; + +/* Define the union csr_rasc_cfg_ce_lvl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ce_err_lvl : 16 ; /* [15:0] */ + u32 rsv_38 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_ce_lvl_u; + +/* Define the union csr_rasc_cfg_funnel_base_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 funnel_cntr_base : 16 ; /* [15:0] */ + u32 rsv_39 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_funnel_base_u; + +/* Define the union csr_rasc_cfg_funnel_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 funnel_cntr_th : 24 ; /* [23:0] */ + u32 funnel_th_cnt_mode : 1 ; /* [24] */ + u32 ps_corr_funnel : 1 ; /* [25] */ + u32 rsv_40 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_funnel_th_u; + +/* Define the union csr_rasc_cfg_errinjmode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_en : 1 ; /* [0] */ + u32 errinj_mode : 3 ; /* [3:1] */ + u32 errinj_wr : 1 ; /* [4] */ + u32 rsv_41 : 27 ; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_errinjmode_u; + +/* Define the union csr_rasc_cfg_errinj_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_addr_col : 14 ; /* [13:0] */ + u32 errinj_addr_row : 18 ; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_errinj_addr_l_u; + +/* Define the union csr_rasc_cfg_errinj_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_addr_bank : 4 ; /* [3:0] */ + u32 errinj_addr_lgrnk : 3 ; /* [6:4] */ + u32 rsv_42 : 1 ; /* [7] */ + u32 errinj_addr_rank : 4 ; /* [11:8] */ + u32 rsv_43 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_errinj_addr_h_u; + +/* Define the union csr_rasc_cfg_errinj_addrmsk_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_addr_col_msk : 14 ; /* [13:0] */ + u32 errinj_addr_row_msk : 18 ; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_errinj_addrmsk_l_u; + +/* Define the union csr_rasc_cfg_errinj_addrmsk_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_addr_bank_msk : 4 ; /* [3:0] */ + u32 errinj_addr_lgrnk_msk : 3 ; /* [6:4] */ + u32 rsv_44 : 1 ; /* [7] */ + u32 errinj_addr_rank_msk : 4 ; /* [11:8] */ + u32 rsv_45 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_errinj_addrmsk_h_u; + +/* Define the union csr_rasc_cfg_err_buf_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_buf_sel : 1 ; /* [0] */ + u32 rsv_46 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_err_buf_sel_u; + +/* Define the union csr_rasc_cfg_errinj_dmsk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_dmsk : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_errinj_dmsk_u; + +/* Define the union csr_rasc_cfg_poison_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poison_chk_type : 1 ; /* [0] */ + u32 rsv_47 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_poison_u; + +/* Define the union csr_rasc_cfg_ram_errinj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_48 : 4 ; /* [3:0] */ + u32 bram_errinj : 2 ; /* [5:4] */ + u32 rsv_49 : 26 ; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_ram_errinj_u; + +/* Define the union csr_rasc_cfg_ram_tmod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_tmod : 10 ; /* [9:0] */ + u32 rsv_50 : 22 ; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_ram_tmod_u; + +/* Define the union csr_rasc_cfg_corr_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_corr_th : 16 ; /* [15:0] */ + u32 rsv_51 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_corr_th_u; + +/* Define the union csr_rasc_cfg_rh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_en : 1 ; /* [0] */ + u32 rsv_52 : 7 ; /* [7:1] */ + u32 rh_mac : 10 ; /* [17:8] */ + u32 rsv_53 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_u; + +/* Define the union csr_rasc_cfg_rh_adja_op_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_op_up_lv1 : 3 ; /* [2:0] */ + u32 rsv_54 : 1 ; /* [3] */ + u32 rh_adja_op_up_lv2 : 3 ; /* [6:4] */ + u32 rsv_55 : 1 ; /* [7] */ + u32 rh_adja_op_up_lv3 : 3 ; /* [10:8] */ + u32 rsv_56 : 1 ; /* [11] */ + u32 rh_adja_op_up_lv4 : 3 ; /* [14:12] */ + u32 rsv_57 : 1 ; /* [15] */ + u32 rh_adja_op_down_lv1 : 3 ; /* [18:16] */ + u32 rsv_58 : 1 ; /* [19] */ + u32 rh_adja_op_down_lv2 : 3 ; /* [22:20] */ + u32 rsv_59 : 1 ; /* [23] */ + u32 rh_adja_op_down_lv3 : 3 ; /* [26:24] */ + u32 rsv_60 : 1 ; /* [27] */ + u32 rh_adja_op_down_lv4 : 3 ; /* [30:28] */ + u32 rsv_61 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_op_u; + +/* Define the union csr_rasc_cfg_rh_adja_up_lv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_up_lv1 : 18 ; /* [17:0] */ + u32 rsv_62 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_up_lv1_u; + +/* Define the union csr_rasc_cfg_rh_adja_up_lv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_up_lv2 : 18 ; /* [17:0] */ + u32 rsv_63 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_up_lv2_u; + +/* Define the union csr_rasc_cfg_rh_adja_up_lv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_up_lv3 : 18 ; /* [17:0] */ + u32 rsv_64 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_up_lv3_u; + +/* Define the union csr_rasc_cfg_rh_adja_up_lv4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_up_lv4 : 18 ; /* [17:0] */ + u32 rsv_65 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_up_lv4_u; + +/* Define the union csr_rasc_cfg_rh_adja_down_lv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_down_lv1 : 18 ; /* [17:0] */ + u32 rsv_66 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_down_lv1_u; + +/* Define the union csr_rasc_cfg_rh_adja_down_lv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_down_lv2 : 18 ; /* [17:0] */ + u32 rsv_67 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_down_lv2_u; + +/* Define the union csr_rasc_cfg_rh_adja_down_lv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_down_lv3 : 18 ; /* [17:0] */ + u32 rsv_68 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_down_lv3_u; + +/* Define the union csr_rasc_cfg_rh_adja_down_lv4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_adja_down_lv4 : 18 ; /* [17:0] */ + u32 rsv_69 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_adja_down_lv4_u; + +/* Define the union csr_rasc_cfg_rh_scram_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_scram_up_lv1 : 5 ; /* [4:0] */ + u32 rsv_70 : 3 ; /* [7:5] */ + u32 rh_scram_up_lv2 : 5 ; /* [12:8] */ + u32 rsv_71 : 3 ; /* [15:13] */ + u32 rh_scram_up_lv3 : 5 ; /* [20:16] */ + u32 rsv_72 : 3 ; /* [23:21] */ + u32 rh_scram_up_lv4 : 5 ; /* [28:24] */ + u32 rsv_73 : 3 ; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_scram_up_u; + +/* Define the union csr_rasc_cfg_rh_scram_down_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_scram_down_lv1 : 5 ; /* [4:0] */ + u32 rsv_74 : 3 ; /* [7:5] */ + u32 rh_scram_down_lv2 : 5 ; /* [12:8] */ + u32 rsv_75 : 3 ; /* [15:13] */ + u32 rh_scram_down_lv3 : 5 ; /* [20:16] */ + u32 rsv_76 : 3 ; /* [23:21] */ + u32 rh_scram_down_lv4 : 5 ; /* [28:24] */ + u32 rsv_77 : 3 ; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_scram_down_u; + +/* Define the union csr_rasc_cfg_rh_scram_msk_lv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_scram_msk_lv1 : 18 ; /* [17:0] */ + u32 rsv_78 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_scram_msk_lv1_u; + +/* Define the union csr_rasc_cfg_rh_scram_msk_lv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_scram_msk_lv2 : 18 ; /* [17:0] */ + u32 rsv_79 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_scram_msk_lv2_u; + +/* Define the union csr_rasc_cfg_rh_scram_msk_lv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_scram_msk_lv3 : 18 ; /* [17:0] */ + u32 rsv_80 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_scram_msk_lv3_u; + +/* Define the union csr_rasc_cfg_rh_scram_msk_lv4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_scram_msk_lv4 : 18 ; /* [17:0] */ + u32 rsv_81 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_scram_msk_lv4_u; + +/* Define the union csr_rasc_cfg_rh_tcal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_tcal : 4 ; /* [3:0] */ + u32 rsv_82 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_tcal_u; + +/* Define the union csr_rasc_cfg_rh_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_row_dir : 1 ; /* [0] */ + u32 rsv_83 : 3 ; /* [3:1] */ + u32 rh_row_sel : 18 ; /* [21:4] */ + u32 rsv_84 : 10 ; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_status0_u; + +/* Define the union csr_rasc_cfg_rh_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rh_row_ori : 18 ; /* [17:0] */ + u32 rsv_85 : 14 ; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_rh_status1_u; + +/* Define the union csr_rasc_cfg_res0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_res0 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_res0_u; + +/* Define the union csr_rasc_cfg_res1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_res1 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_res1_u; + +/* Define the union csr_rasc_cfg_res2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_res2 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_res2_u; + +/* Define the union csr_rasc_cfg_res3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_res3 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_cfg_res3_u; + +/* Define the union csr_rasc_intmsk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_corr_int_mask : 1 ; /* [0] */ + u32 ha_uncorr_int_mask : 1 ; /* [1] */ + u32 ha_corr_alarm_int_mask : 1 ; /* [2] */ + u32 rsv_86 : 1 ; /* [3] */ + u32 pa_corr_int_mask : 1 ; /* [4] */ + u32 pa_uncorr_int_mask : 1 ; /* [5] */ + u32 rsv_87 : 2 ; /* [7:6] */ + u32 sp_dev_int_mask : 1 ; /* [8] */ + u32 sp_rnk_int_mask : 1 ; /* [9] */ + u32 sp_corr_int_mask : 1 ; /* [10] */ + u32 sp_uncorr_int_mask : 1 ; /* [11] */ + u32 sp_rb_err_int_mask : 1 ; /* [12] */ + u32 rsv_88 : 3 ; /* [15:13] */ + u32 vls_int_mask : 1 ; /* [16] */ + u32 vls_corr_int_mask : 1 ; /* [17] */ + u32 vls_uncorr_int_mask : 1 ; /* [18] */ + u32 rvls_corr_int_mask : 1 ; /* [19] */ + u32 rvls_uncorr_int_mask : 1 ; /* [20] */ + u32 rsv_89 : 5 ; /* [25:21] */ + u32 ebram_serr_int_mask : 1 ; /* [26] */ + u32 ebram_merr_int_mask : 1 ; /* [27] */ + u32 rsv_90 : 4 ; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_intmsk_u; + +/* Define the union csr_rasc_rint_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_corr_rint : 1 ; /* [0] */ + u32 ha_uncorr_rint : 1 ; /* [1] */ + u32 ha_corr_alarm_rint : 1 ; /* [2] */ + u32 rsv_91 : 1 ; /* [3] */ + u32 pa_corr_rint : 1 ; /* [4] */ + u32 pa_uncorr_rint : 1 ; /* [5] */ + u32 rsv_92 : 2 ; /* [7:6] */ + u32 sp_dev_rint : 1 ; /* [8] */ + u32 sp_rnk_rint : 1 ; /* [9] */ + u32 sp_corr_rint : 1 ; /* [10] */ + u32 sp_uncorr_rint : 1 ; /* [11] */ + u32 sp_rb_err_rint : 1 ; /* [12] */ + u32 rsv_93 : 3 ; /* [15:13] */ + u32 vls_int_rint : 1 ; /* [16] */ + u32 vls_corr_rint : 1 ; /* [17] */ + u32 vls_uncorr_rint : 1 ; /* [18] */ + u32 rvls_corr_rint : 1 ; /* [19] */ + u32 rvls_uncorr_rint : 1 ; /* [20] */ + u32 rsv_94 : 5 ; /* [25:21] */ + u32 ebram_serr_rint : 1 ; /* [26] */ + u32 ebram_merr_rint : 1 ; /* [27] */ + u32 rsv_95 : 4 ; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_rint_u; + +/* Define the union csr_rasc_intsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_corr_intsts : 1 ; /* [0] */ + u32 ha_uncorr_intsts : 1 ; /* [1] */ + u32 ha_corr_alarm_intsts : 1 ; /* [2] */ + u32 rsv_96 : 1 ; /* [3] */ + u32 pa_corr_intsts : 1 ; /* [4] */ + u32 pa_uncorr_intsts : 1 ; /* [5] */ + u32 rsv_97 : 2 ; /* [7:6] */ + u32 sp_dev_intsts : 1 ; /* [8] */ + u32 sp_rnk_intsts : 1 ; /* [9] */ + u32 sp_corr_intsts : 1 ; /* [10] */ + u32 sp_uncorr_intsts : 1 ; /* [11] */ + u32 sp_rb_err_intsts : 1 ; /* [12] */ + u32 rsv_98 : 3 ; /* [15:13] */ + u32 vls_int_intsts : 1 ; /* [16] */ + u32 vls_corr_int_intsts : 1 ; /* [17] */ + u32 vls_uncorr_int_intsts : 1 ; /* [18] */ + u32 rvls_corr_int_intsts : 1 ; /* [19] */ + u32 rvls_uncorr_int_intsts : 1 ; /* [20] */ + u32 rsv_99 : 5 ; /* [25:21] */ + u32 ebram_serr_intsts : 1 ; /* [26] */ + u32 ebram_merr_intsts : 1 ; /* [27] */ + u32 rsv_100 : 4 ; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_intsts_u; + +/* Define the union csr_rasc_sram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ebram_err_addr : 16 ; /* [15:0] */ + u32 rsv_101 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_sram_err_addr_u; + +/* Define the union csr_rasc_curr_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_busy : 1 ; /* [0] */ + u32 rsv_102 : 3 ; /* [3:1] */ + u32 vls_busy : 1 ; /* [4] */ + u32 rvls_busy : 1 ; /* [5] */ + u32 rvls_vls0_busy : 1 ; /* [6] */ + u32 rvls_vls1_busy : 1 ; /* [7] */ + u32 rsv_103 : 4 ; /* [11:8] */ + u32 pa_busy : 1 ; /* [12] */ + u32 rsv_104 : 3 ; /* [15:13] */ + u32 sp_dev_busy : 1 ; /* [16] */ + u32 sp_rnk_busy : 1 ; /* [17] */ + u32 rsv_105 : 2 ; /* [19:18] */ + u32 wdata_busy : 1 ; /* [20] */ + u32 rsv_106 : 3 ; /* [23:21] */ + u32 rdata_busy : 1 ; /* [24] */ + u32 cmd_busy : 1 ; /* [25] */ + u32 rsv_107 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_status_u; + +/* Define the union csr_rasc_curr_errstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_err : 1 ; /* [0] */ + u32 rsv_108 : 3 ; /* [3:1] */ + u32 uncorr_err : 1 ; /* [4] */ + u32 rsv_109 : 27 ; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_errstatus_u; + +/* Define the union csr_rasc_curr_sprnk_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sprnk : 4 ; /* [3:0] */ + u32 sprnk_vld : 1 ; /* [4] */ + u32 rsv_110 : 27 ; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_sprnk_sta_u; + +/* Define the union csr_rasc_curr_spdev_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spdev_vld : 8 ; /* [7:0] */ + u32 rsv_111 : 8 ; /* [15:8] */ + u32 spdev_dev0 : 10 ; /* [25:16] */ + u32 rsv_112 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_spdev_sta_u; + +/* Define the union csr_rasc_curr_spdev_dev1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spdev_dev1 : 30 ; /* [29:0] */ + u32 rsv_113 : 2 ; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_spdev_dev1_u; + +/* Define the union csr_rasc_curr_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_cnt : 8 ; /* [7:0] */ + u32 rsv_114 : 24 ; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_cmd_cnt_u; + +/* Define the union csr_rasc_curr_adddc_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 region0_done : 1 ; /* [0] */ + u32 rsv_115 : 15 ; /* [15:1] */ + u32 region1_vls_done : 1 ; /* [16] */ + u32 region1_rvls_done : 1 ; /* [17] */ + u32 region1_rvls_vls_done : 1 ; /* [18] */ + u32 rsv_116 : 13 ; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_curr_adddc_sta_u; + +/* Define the union csr_rasc_his_uncorr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 uncorr_cnt : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_uncorr_cnt_u; + +/* Define the union csr_rasc_his_corr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_cnt : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_cnt_u; + +/* Define the union csr_rasc_his_haerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_corr_cnt : 16 ; /* [15:0] */ + u32 ha_uncorr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_haerr_cnt_u; + +/* Define the union csr_rasc_his_paerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pa_corr_cnt : 16 ; /* [15:0] */ + u32 pa_uncorr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_paerr_cnt_u; + +/* Define the union csr_rasc_his_sperr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_corr_cnt : 16 ; /* [15:0] */ + u32 sp_uncorr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_sperr_cnt_u; + +/* Define the union csr_rasc_his_sprberr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sp_rberr_cnt : 16 ; /* [15:0] */ + u32 rsv_117 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_sprberr_cnt_u; + +/* Define the union csr_rasc_his_vlserr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vls_corr_cnt : 16 ; /* [15:0] */ + u32 vls_uncorr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_vlserr_cnt_u; + +/* Define the union csr_rasc_his_rvlserr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rvls_corr_cnt : 16 ; /* [15:0] */ + u32 rvls_uncorr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_rvlserr_cnt_u; + +/* Define the union csr_rasc_his_rankcnt_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rnk_corr_cnt : 16 ; /* [15:0] */ + u32 rnk_uncorr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_rankcnt_inf_u; + +/* Define the union csr_rasc_his_ha_rankcnt_inf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ha_rnk_funnel_corr_cnt : 16 ; /* [15:0] */ + u32 ha_rnk_corr_cnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_ha_rankcnt_inf_u; + +/* Define the union csr_rasc_his_rank_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rnk_corr_vld : 8 ; /* [7:0] */ + u32 rsv_118 : 24 ; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_rank_err_u; + +/* Define the union csr_rasc_his_offset_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dev_offset_errcnt : 16 ; /* [15:0] */ + u32 bank_offset_errcnt : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_offset_err_u; + +/* Define the union csr_rasc_his_seg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 search_errcnt_l : 16 ; /* [15:0] */ + u32 search_errcnt_h : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_seg_err_u; + +/* Define the union csr_rasc_his_worst_dev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wst_dev_cnt : 16 ; /* [15:0] */ + u32 wst_dev_rnk : 4 ; /* [19:16] */ + u32 wst_dev_idx : 5 ; /* [24:20] */ + u32 rsv_119 : 7 ; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_worst_dev_u; + +/* Define the union csr_rasc_his_worst_bnk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wst_bnk_cnt : 16 ; /* [15:0] */ + u32 wst_bnk_dev : 8 ; /* [23:16] */ + u32 rsv_120 : 1 ; /* [24] */ + u32 wst_bnk_bnk : 4 ; /* [28:25] */ + u32 rsv_121 : 3 ; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_worst_bnk_u; + +/* Define the union csr_rasc_his_rcdtyp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_int_record : 5 ; /* [4:0] */ + u32 rsv_122 : 3 ; /* [7:5] */ + u32 uncorr_int_record : 6 ; /* [13:8] */ + u32 rsv_123 : 18 ; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_rcdtyp_u; + +/* Define the union csr_rasc_his_uncorr_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 uncorr_addr_col : 14 ; /* [13:0] */ + u32 uncorr_addr_row : 18 ; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_uncorr_addr_l_u; + +/* Define the union csr_rasc_his_uncorr_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 uncorr_addr_bank : 4 ; /* [3:0] */ + u32 uncorr_addr_lgrnk : 3 ; /* [6:4] */ + u32 rsv_124 : 1 ; /* [7] */ + u32 uncorr_addr_rnk : 4 ; /* [11:8] */ + u32 uncorr_addr_pos : 1 ; /* [12] */ + u32 rsv_125 : 19 ; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_uncorr_addr_h_u; + +/* Define the union csr_rasc_his_uncorr_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 uncorr_rdata : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_uncorr_rdata_u; + +/* Define the union csr_rasc_his_uncorr_rdata_cwh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 uncorr_rdata_cwh : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_uncorr_rdata_cwh_u; + +/* Define the union csr_rasc_his_corr_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_addr_col : 14 ; /* [13:0] */ + u32 corr_addr_row : 18 ; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_addr_l_u; + +/* Define the union csr_rasc_his_corr_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_addr_bank : 4 ; /* [3:0] */ + u32 corr_addr_lgrnk : 3 ; /* [6:4] */ + u32 rsv_126 : 1 ; /* [7] */ + u32 corr_addr_rnk : 4 ; /* [11:8] */ + u32 corr_addr_pos : 1 ; /* [12] */ + u32 rsv_127 : 19 ; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_addr_h_u; + +/* Define the union csr_rasc_his_corr_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_rdata : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_rdata_u; + +/* Define the union csr_rasc_his_corr_rdata_cwh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_rdata_cwh : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_rdata_cwh_u; + +/* Define the union csr_rasc_his_corr_expdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_expdata : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_expdata_u; + +/* Define the union csr_rasc_his_corr_expdata_cwh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 corr_expdata_cwh : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_corr_expdata_cwh_u; + +/* Define the union csr_rasc_his_errinj_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinj_cnt : 16 ; /* [15:0] */ + u32 rsv_128 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rasc_his_errinj_cnt_u; + +#endif // __DDRC_RASC_C_UNION_DEFINE_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_rasc_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_rasc_reg_offset.h new file mode 100644 index 000000000..0d43735af --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ddrc_rasc_reg_offset.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : ddrc_rasc_reg_offset.h + * Description : SPU DDRC rasc 寄存器偏移信息 + * History : 2023/04/19 11:22:23 Create file + */ + +#ifndef __DDRC_RASC_REG_OFFSET_H__ +#define __DDRC_RASC_REG_OFFSET_H__ + +/* RASC Base address of Module's Register */ +#define CSR_RASC_BASE (0x1800) + +/******************************************************************************/ +/* RASC Registers' Definitions */ +/******************************************************************************/ + +#define RASC_CTRL_MODE_REG (CSR_RASC_BASE + 0x0) /* RASC_CTRL_MODE是RASC工作模式启动寄存器 */ +#define RASC_CTRL_ADDDC_REG (CSR_RASC_BASE + 0x4) /* RASC_CTRL_VLS是RASC virtual lockstep功能配置寄存器 */ +#define RASC_CTRL_PASCRUB_REG (CSR_RASC_BASE + 0x8) /* RASC_CTRL_PASCRUB是RASC Patrol Scrub功能配置寄存器 */ +#define RASC_CTRL_SPARING_REG (CSR_RASC_BASE + 0xC) /* RASC_CTRL_SPARING是RASC Sparing功能配置寄存器 */ +#define RASC_CTRL_FLUSH_REG (CSR_RASC_BASE + 0x10) /* RASC_CTRL_FLUSH时RASC排空请求寄存器 */ +#define RASC_CTRL_ERRINJ_REG (CSR_RASC_BASE + 0x14) /* RASC_CTRL_ERRINJ是RASC错误注入功能配置寄存器 */ +#define RASC_CTRL_FUNNEL_REG (CSR_RASC_BASE + 0x18) /* RASC_CTRL_FUNNEL是RASC错误统计漏斗功能寄存器 */ +#define RASC_CFG_MODE_REG (CSR_RASC_BASE + 0x20) /* RASC_CFG_MODE是RASC模式配置寄存器 */ +#define RASC_CFG_RANKMAP_0_REG (CSR_RASC_BASE + 0x30) /* RASC_CFG_RANKMAP是RASC Rank映射寄存器 */ +#define RASC_CFG_RANKMAP_1_REG (CSR_RASC_BASE + 0x34) /* RASC_CFG_RANKMAP是RASC Rank映射寄存器 */ +#define RASC_CFG_CLR_REG (CSR_RASC_BASE + 0x54) /* RASC_CFG_CLR是RASC的错误统计计数器清零配置寄存器 */ +#define RASC_CFG_INFO_RNK_REG (CSR_RASC_BASE + 0x58) /* RASC_CFG_INFOIDX是RASC的读取基于Rank统计信息配置寄存器 */ +#define RASC_CFG_INFO_DEVIDX_REG (CSR_RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX是RASC的读取基于device的Rank统计信息配置寄存器 */ +#define RASC_CFG_INFO_BNKIDX_REG (CSR_RASC_BASE + 0x60) /* RASC_CFG_INFOIDX是RASC的读取Rank统计基于bank的信息配置寄存器 */ +#define RASC_CFG_PASTART_0_REG (CSR_RASC_BASE + 0x70) /* RASC的Patrol Scrub RankGroupN的起始地址配置寄存器 */ +#define RASC_CFG_PASTART_1_REG (CSR_RASC_BASE + 0x74) /* RASC的Patrol Scrub RankGroupN的起始地址配置寄存器 */ +#define RASC_CFG_PAEND_0_REG (CSR_RASC_BASE + 0x80) /* RASC的Patrol Scrub RankGroupN的起始结束配置寄存器 */ +#define RASC_CFG_PAEND_1_REG (CSR_RASC_BASE + 0x84) /* RASC的Patrol Scrub RankGroupN的起始结束配置寄存器 */ +#define RASC_CFG_PS_REG (CSR_RASC_BASE + 0x90) /* RASC_CFG_PS是RASC的Patrol Scrub命令下发控制寄存器 */ +#define RASC_CFG_ADDDC_REGION0_REG (CSR_RASC_BASE + 0xA0) /* RASC_CFG_ADDDC_REGIN0是ADDDC第一个错误区域处理配置寄存器 */ +#define RASC_CFG_ADDDC_REGION1_REG (CSR_RASC_BASE + 0xA4) /* RASC_CFG_ADDDC_REGIN1是ADDDC第二个错误区域处理配置寄存器 */ +#define RASC_CFG_ADDDC_RVLS_REG (CSR_RASC_BASE + 0xA8) /* RASC_CFG_ADDDC_RVLS是ADDDC进行重组数据还原操作配置寄存器 */ +#define RASC_CFG_VLS_INTERVAL_REG (CSR_RASC_BASE + 0xAC) /* RASC_CFG_VLS_INTERVAL是RASC的虚拟LOCKSTEP命令下发控制寄存器 */ +#define RASC_CFG_VLS_X8_REG (CSR_RASC_BASE + 0xB0) /* RASC_CFG_VLS_X8是用于配置X8器件SDDC控制寄存器。 */ +#define RASC_CFG_SP_REG (CSR_RASC_BASE + 0xC0) /* RASC_CFG_SP是RASC的备份配置寄存器 */ +#define RASC_CFG_SPR_INTERVAL_REG (CSR_RASC_BASE + 0xC4) /* RASC_CFG_SPR_INTERVAL是sparing操作命令间插寄存器。 */ +#define RASC_CFG_SPR_OUTSTANDING_REG (CSR_RASC_BASE + 0xC8) /* 配置一次sparing操作的outstandign深度 */ +#define RASC_CFG_CE_LVL_REG (CSR_RASC_BASE + 0xD4) /* RASC_CFG_CE_LVL是RASC的可纠正错误水线配置寄存器 */ +#define RASC_CFG_FUNNEL_BASE_REG (CSR_RASC_BASE + 0xE0) /* RASC_CFG_FUNNEL_TH_BASE是可纠正错误漏斗时间刻度配置寄存器 */ +#define RASC_CFG_FUNNEL_TH_REG (CSR_RASC_BASE + 0xE4) /* RASC_CFG_FUNNEL_TH_CNT是可纠正错误漏斗时间阈值配置寄存器 */ +#define RASC_CFG_ERRINJMODE_REG (CSR_RASC_BASE + 0xF0) /* RASC_CFG_ERRINJMODE是RASC的错误注入模式配置寄存器 */ +#define RASC_CFG_ERRINJ_ADDR_L_REG (CSR_RASC_BASE + 0xF4) /* RASC_CFG_ERRINJ_ADDR_L是RASC的错误注入低位地址配置寄存器 */ +#define RASC_CFG_ERRINJ_ADDR_H_REG (CSR_RASC_BASE + 0xF8) /* RASC_CFG_ERRINJ_ADDR_H是RASC的错误注入高位地址配置寄存器 */ +#define RASC_CFG_ERRINJ_ADDRMSK_L_REG (CSR_RASC_BASE + 0xFC) /* RASC_CFG_ERRINJ_ADDRMSK_L是RASC的错误注入低位地址屏蔽配置寄存器 */ +#define RASC_CFG_ERRINJ_ADDRMSK_H_REG (CSR_RASC_BASE + 0x100) /* RASC_CFG_ERRINJ_ADDRMSK_H是RASC的错误注入高位地址屏蔽配置寄存器 */ +#define RASC_CFG_ERR_BUF_SEL_REG (CSR_RASC_BASE + 0x104) /* RASC_CFG_ERR_BUF_SEL是RASC中错误选择读取寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_0_REG (CSR_RASC_BASE + 0x110) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_1_REG (CSR_RASC_BASE + 0x114) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_2_REG (CSR_RASC_BASE + 0x118) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_3_REG (CSR_RASC_BASE + 0x11C) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_4_REG (CSR_RASC_BASE + 0x120) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_5_REG (CSR_RASC_BASE + 0x124) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_6_REG (CSR_RASC_BASE + 0x128) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_7_REG (CSR_RASC_BASE + 0x12C) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_8_REG (CSR_RASC_BASE + 0x130) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_ERRINJ_DMSK_9_REG (CSR_RASC_BASE + 0x134) /* RASC_CFG_ERRINJ_DMSK是RASC错误注入数据配置寄存器 */ +#define RASC_CFG_POISON_REG (CSR_RASC_BASE + 0x140) /* RASC_CFG_POISON是poison功能配置寄存器。 */ +#define RASC_CFG_RAM_ERRINJ_REG (CSR_RASC_BASE + 0x150) /* RASC_CFG_RAM_ERRINJ是RASC片内RAM的ECC错误注入模式配置寄存器。 */ +#define RASC_CFG_RAM_TMOD_REG (CSR_RASC_BASE + 0x154) /* RASC_CFG_RAM_TMOD是RASC中RAM的测试模式配置寄存器 */ +#define RASC_CFG_CORR_TH_REG (CSR_RASC_BASE + 0x160) /* RASC_CFG_CORR_TH是RASC中HA读数据可纠错告警中断阈值寄存器 */ +#define RASC_CFG_RH_REG (CSR_RASC_BASE + 0x164) /* Row hammer配置寄存器。 */ +#define RASC_CFG_RH_ADJA_OP_REG (CSR_RASC_BASE + 0x168) /* Row hammer相邻行计算操作码。 */ +#define RASC_CFG_RH_ADJA_UP_LV1_REG (CSR_RASC_BASE + 0x16C) /* Row hammer上一相邻行计算第1级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_UP_LV2_REG (CSR_RASC_BASE + 0x170) /* Row hammer上一相邻行计算第2级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_UP_LV3_REG (CSR_RASC_BASE + 0x174) /* Row hammer上一相邻行计算第3级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_UP_LV4_REG (CSR_RASC_BASE + 0x178) /* Row hammer上一相邻行计算第4级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_DOWN_LV1_REG (CSR_RASC_BASE + 0x17C) /* Row hammer下一相邻行计算第1级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_DOWN_LV2_REG (CSR_RASC_BASE + 0x180) /* Row hammer下一相邻行计算第2级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_DOWN_LV3_REG (CSR_RASC_BASE + 0x184) /* Row hammer下一相邻行计算第3级偏移地址设置。 */ +#define RASC_CFG_RH_ADJA_DOWN_LV4_REG (CSR_RASC_BASE + 0x188) /* Row hammer下一相邻行计算第4级偏移地址设置。 */ +#define RASC_CFG_RH_SCRAM_UP_REG (CSR_RASC_BASE + 0x18C) /* 上一相邻行Row scramble偏移地址设置。 */ +#define RASC_CFG_RH_SCRAM_DOWN_REG (CSR_RASC_BASE + 0x190) /* 下一相邻行Row scramble偏移地址设置。 */ +#define RASC_CFG_RH_SCRAM_MSK_LV1_REG (CSR_RASC_BASE + 0x194) /* 第1级Row scramble mask设置。 */ +#define RASC_CFG_RH_SCRAM_MSK_LV2_REG (CSR_RASC_BASE + 0x198) /* 第2级Row scramble mask设置。 */ +#define RASC_CFG_RH_SCRAM_MSK_LV3_REG (CSR_RASC_BASE + 0x19C) /* 第3级Row scramble mask设置。 */ +#define RASC_CFG_RH_SCRAM_MSK_LV4_REG (CSR_RASC_BASE + 0x1A0) /* 第4级Row scramble mask设置。 */ +#define RASC_CFG_RH_TCAL_REG (CSR_RASC_BASE + 0x1A4) /* row hammer tCAL设置。 */ +#define RASC_CFG_RH_STATUS0_REG (CSR_RASC_BASE + 0x1A8) /* row hammer row地址映射状态0 */ +#define RASC_CFG_RH_STATUS1_REG (CSR_RASC_BASE + 0x1AC) /* row hammer row地址映射状态0 */ +#define RASC_CFG_RES0_REG (CSR_RASC_BASE + 0x1F0) /* RASC保留寄存器0 */ +#define RASC_CFG_RES1_REG (CSR_RASC_BASE + 0x1F4) /* RASC保留寄存器1 */ +#define RASC_CFG_RES2_REG (CSR_RASC_BASE + 0x1F8) /* RASC保留寄存器2 */ +#define RASC_CFG_RES3_REG (CSR_RASC_BASE + 0x1FC) /* RASC保留寄存器3 */ +#define RASC_INTMSK_REG (CSR_RASC_BASE + 0x200) /* RASC_INTMSK是RASC中断屏蔽寄存器 */ +#define RASC_RINT_REG (CSR_RASC_BASE + 0x204) /* RASC_RINT是RASC原始中断寄存器 */ +#define RASC_INTSTS_REG (CSR_RASC_BASE + 0x208) /* RASC_INTSTS是RASC中断状态寄存器 */ +#define RASC_SRAM_ERR_ADDR_REG (CSR_RASC_BASE + 0x20C) /* RASC_SRAM_ERR_ADDR是RASC的SRAM出现ECC错误的地址寄存器 */ +#define RASC_CURR_STATUS_REG (CSR_RASC_BASE + 0x220) /* RASC_CURR_STATUS是RASC当前状态寄存器 */ +#define RASC_CURR_ERRSTATUS_REG (CSR_RASC_BASE + 0x224) /* RASC_CURR_ERRSTATUS是RASC当前错误数据寄存器 */ +#define RASC_CURR_SPRNK_STA_REG (CSR_RASC_BASE + 0x228) /* RASC_CURR_SPRNK_STA是RASC当前Rank Sparing状态寄存器。 */ +#define RASC_CURR_SPDEV_STA_REG (CSR_RASC_BASE + 0x22C) /* RASC_CURR_SPDEV_STA是RASC当前Device Sparing状态寄存器。 */ +#define RASC_CURR_SPDEV_DEV1_REG (CSR_RASC_BASE + 0x230) /* RASC中device sparing操作过的device编号寄存器。 */ +#define RASC_CURR_CMD_CNT_REG (CSR_RASC_BASE + 0x234) /* RASC_CURR_CMD_CNT是RASC输出命令执行状态寄存器。 */ +#define RASC_CURR_ADDDC_STA_REG (CSR_RASC_BASE + 0x238) /* RASC_CURR_ADDDC_STA是RASC当前虚拟lockstep操作状态寄存器 */ +#define RASC_HIS_UNCORR_CNT_REG (CSR_RASC_BASE + 0x240) /* RASC_HIS_UNCORR_CNT是RASC不可纠正错误统计寄存器 */ +#define RASC_HIS_CORR_CNT_REG (CSR_RASC_BASE + 0x244) /* RASC_HIS_CORR_CNT是RASC可纠正错误统计寄存器 */ +#define RASC_HIS_HAERR_CNT_REG (CSR_RASC_BASE + 0x250) /* RASC_HIS_HA_CNT是RASC HA命令统计寄存器 */ +#define RASC_HIS_PAERR_CNT_REG (CSR_RASC_BASE + 0x258) /* RASC_HIS_PAERR_CNT是RASC PatrolScrub命令统计寄存器 */ +#define RASC_HIS_SPERR_CNT_REG (CSR_RASC_BASE + 0x25C) /* RASC_HIS_SPERR_CNT是RASC Sparing读错误统计寄存器 */ +#define RASC_HIS_SPRBERR_CNT_REG (CSR_RASC_BASE + 0x260) /* RASC_HIS_SPERR_CNT是RASC Sparing回读错误统计寄存器 */ +#define RASC_HIS_VLSERR_CNT_REG (CSR_RASC_BASE + 0x264) /* RASC Virtual Lockstep数据重组读错误统计寄存器 */ +#define RASC_HIS_RVLSERR_CNT_REG (CSR_RASC_BASE + 0x268) /* RASC Virtual Lockstep数据还原读错误统计寄存器 */ +#define RASC_HIS_RANKCNT_INF_REG (CSR_RASC_BASE + 0x280) /* RASC_HIS_RANKCNT_INF是RASC 指定Rank的错误统计寄存器 */ +#define RASC_HIS_HA_RANKCNT_INF_REG (CSR_RASC_BASE + 0x284) /* RASC_HIS_HA_RANKCNT_INF是HA接口指定Rank可纠正错误统计寄存器 */ +#define RASC_HIS_RANK_ERR_REG (CSR_RASC_BASE + 0x28C) /* RASC发现基于rank统计的错误数达到阈值状态寄存器 */ +#define RASC_HIS_OFFSET_ERR_REG (CSR_RASC_BASE + 0x290) /* RASC_HIS_OFFSET_ERRF是RASC指定具体位置错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_0_REG (CSR_RASC_BASE + 0x2A0) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_1_REG (CSR_RASC_BASE + 0x2A4) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_2_REG (CSR_RASC_BASE + 0x2A8) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_3_REG (CSR_RASC_BASE + 0x2AC) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_4_REG (CSR_RASC_BASE + 0x2B0) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_5_REG (CSR_RASC_BASE + 0x2B4) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_6_REG (CSR_RASC_BASE + 0x2B8) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_7_REG (CSR_RASC_BASE + 0x2BC) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_SEG_ERR_8_REG (CSR_RASC_BASE + 0x2C0) /* RASC_HIS_SEG_INF是RASC指定 某个区域错误统计寄存器 */ +#define RASC_HIS_WORST_DEV_REG (CSR_RASC_BASE + 0x2D4) /* RASC_HIS_WORST_DEV是RASC错误最多的Device统计 */ +#define RASC_HIS_WORST_BNK_REG (CSR_RASC_BASE + 0x2D8) /* RASC_HIS_WORST_RNK是RASC错误最多的bank统计 */ +#define RASC_HIS_RCDTYP_REG (CSR_RASC_BASE + 0x300) /* RASC_HIS_RCDTYP是RASC错误数据类型寄存器 */ +#define RASC_HIS_UNCORR_ADDR_L_REG (CSR_RASC_BASE + 0x310) /* RASC_HIS_UNCORR_ADDR_L是RASC不可纠正错误数据低位地址寄存器 */ +#define RASC_HIS_UNCORR_ADDR_H_REG (CSR_RASC_BASE + 0x314) /* RASC_HIS_UNCORR_ADDR_H是RASC不可纠正错误数据高位地址寄存器 */ +#define RASC_HIS_UNCORR_RDATA_0_REG (CSR_RASC_BASE + 0x320) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_1_REG (CSR_RASC_BASE + 0x324) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_2_REG (CSR_RASC_BASE + 0x328) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_3_REG (CSR_RASC_BASE + 0x32C) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_4_REG (CSR_RASC_BASE + 0x330) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_5_REG (CSR_RASC_BASE + 0x334) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_6_REG (CSR_RASC_BASE + 0x338) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_7_REG (CSR_RASC_BASE + 0x33C) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_8_REG (CSR_RASC_BASE + 0x340) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_9_REG (CSR_RASC_BASE + 0x344) /* RASC_HIS_UNCORR_RDATA是RASC不可纠正错误原始读数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_0_REG (CSR_RASC_BASE + 0x350) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_1_REG (CSR_RASC_BASE + 0x354) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_2_REG (CSR_RASC_BASE + 0x358) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_3_REG (CSR_RASC_BASE + 0x35C) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_4_REG (CSR_RASC_BASE + 0x360) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_5_REG (CSR_RASC_BASE + 0x364) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_6_REG (CSR_RASC_BASE + 0x368) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_7_REG (CSR_RASC_BASE + 0x36C) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_8_REG (CSR_RASC_BASE + 0x370) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_UNCORR_RDATA_CWH_9_REG (CSR_RASC_BASE + 0x374) /* RASC不可纠正错误原始高一半cacheline数据寄存器 */ +#define RASC_HIS_CORR_ADDR_L_REG (CSR_RASC_BASE + 0x380) /* RASC_HIS_CORR_ADDR_L是RASC可纠正错误数据低位地址寄存器 */ +#define RASC_HIS_CORR_ADDR_H_REG (CSR_RASC_BASE + 0x384) /* RASC_HIS_CORR_ADDR_H是RASC可纠正错误数据高位地址寄存器 */ +#define RASC_HIS_CORR_RDATA_0_REG (CSR_RASC_BASE + 0x390) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_1_REG (CSR_RASC_BASE + 0x394) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_2_REG (CSR_RASC_BASE + 0x398) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_3_REG (CSR_RASC_BASE + 0x39C) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_4_REG (CSR_RASC_BASE + 0x3A0) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_5_REG (CSR_RASC_BASE + 0x3A4) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_6_REG (CSR_RASC_BASE + 0x3A8) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_7_REG (CSR_RASC_BASE + 0x3AC) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_8_REG (CSR_RASC_BASE + 0x3B0) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_9_REG (CSR_RASC_BASE + 0x3B4) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_0_REG (CSR_RASC_BASE + 0x3C0) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_1_REG (CSR_RASC_BASE + 0x3C4) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_2_REG (CSR_RASC_BASE + 0x3C8) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_3_REG (CSR_RASC_BASE + 0x3CC) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_4_REG (CSR_RASC_BASE + 0x3D0) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_5_REG (CSR_RASC_BASE + 0x3D4) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_6_REG (CSR_RASC_BASE + 0x3D8) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_7_REG (CSR_RASC_BASE + 0x3DC) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_8_REG (CSR_RASC_BASE + 0x3E0) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_RDATA_CWH_9_REG (CSR_RASC_BASE + 0x3E4) /* RASC_HIS_CORR_RDATA0是RASC可纠正错误原始数据高cacheline寄存器 */ +#define RASC_HIS_CORR_EXPDATA_0_REG (CSR_RASC_BASE + 0x400) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_1_REG (CSR_RASC_BASE + 0x404) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_2_REG (CSR_RASC_BASE + 0x408) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_3_REG (CSR_RASC_BASE + 0x40C) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_4_REG (CSR_RASC_BASE + 0x410) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_5_REG (CSR_RASC_BASE + 0x414) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_6_REG (CSR_RASC_BASE + 0x418) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_7_REG (CSR_RASC_BASE + 0x41C) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_8_REG (CSR_RASC_BASE + 0x420) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_9_REG (CSR_RASC_BASE + 0x424) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_0_REG (CSR_RASC_BASE + 0x430) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_1_REG (CSR_RASC_BASE + 0x434) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_2_REG (CSR_RASC_BASE + 0x438) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_3_REG (CSR_RASC_BASE + 0x43C) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_4_REG (CSR_RASC_BASE + 0x440) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_5_REG (CSR_RASC_BASE + 0x444) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_6_REG (CSR_RASC_BASE + 0x448) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_7_REG (CSR_RASC_BASE + 0x44C) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_8_REG (CSR_RASC_BASE + 0x450) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_CORR_EXPDATA_CWH_9_REG (CSR_RASC_BASE + 0x454) /* RASC_HIS_CORR_EXPDATA是RASC可纠正错误期望高cacheline数据寄存器 */ +#define RASC_HIS_ERRINJ_CNT_REG (CSR_RASC_BASE + 0x460) /* RASC_HIS_ERRINJ_CNT是RASC错误注入数据统计寄存器 */ + +#endif // __DDRC_RASC_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/efuse_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/efuse_reg_offset.h new file mode 100644 index 000000000..959633a46 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/efuse_reg_offset.h @@ -0,0 +1,125 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : hi1823e_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/21 14:49:24 Create file +// ****************************************************************************** + +#ifndef __EFUSE_REG_OFFSET_H__ +#define __EFUSE_REG_OFFSET_H__ + +/* EFUSE_CFG Base address of Module's Register */ +#define CSR_EFUSE_CFG_BASE (0x90380000ULL) + +/******************************************************************************/ +/* EFUSE_CFG Registers' Definitions */ +/******************************************************************************/ + +#define CSR_EFUSE_CFG_SC_TSENSOR1_TRIM_REG (CSR_EFUSE_CFG_BASE + 0x60D8) /* eFuse中tsensor1的校准值 */ +#define CSR_EFUSE_CFG_SC_TSENSOR0_TRIM_REG (CSR_EFUSE_CFG_BASE + 0x60DC) /* eFuse中tsensor0的校准值 */ +#define CSR_EFUSE_CFG_SC_EFUSE_IDDQ_REG (CSR_EFUSE_CFG_BASE + 0xE000) /* 高温IDDQ */ +#define CSR_EFUSE_CFG_SC_EFUSE_SPEED_GRADE_REG (CSR_EFUSE_CFG_BASE + 0xE004) /* 芯片速度等级和者常温IDDQ */ +#define CSR_EFUSE_CFG_SC_EFUSE_SUBSTRATE_LAYER_NUM_REG (CSR_EFUSE_CFG_BASE + 0xE008) /* 芯片芯片基板层数 */ +#define CSR_EFUSE_CFG_SC_EFUSE_ALL_SCAN_REG (CSR_EFUSE_CFG_BASE + 0xE00C) /* 芯片ALL-SCAN指示 */ +#define CSR_EFUSE_CFG_SC_EFUSE_POWER_GRADE_REG (CSR_EFUSE_CFG_BASE + 0xE010) /* Totem功耗等级 */ +#define CSR_EFUSE_CFG_SC_EFUSE_PKG_VERSION_REG (CSR_EFUSE_CFG_BASE + 0xE014) /* 芯片合封模式 */ +#define CSR_EFUSE_CFG_SC_EFUSE_TR5_AVS_ID_REG (CSR_EFUSE_CFG_BASE + 0xE018) /* TR5前实验室阶段使用的测试信息 */ +#define CSR_EFUSE_CFG_SC_EFUSE_PARTIAL_GOOD0_REG (CSR_EFUSE_CFG_BASE + 0xE020) /* Partial Good测试标志位0 */ +#define CSR_EFUSE_CFG_SC_EFUSE_PARTIAL_GOOD1_REG (CSR_EFUSE_CFG_BASE + 0xE024) /* Partial Good测试标志位1 */ +#define CSR_EFUSE_CFG_SC_EFUSE_PARTIAL_GOOD2_REG (CSR_EFUSE_CFG_BASE + 0xE028) /* CPU Cluster Partial Good信息 */ +#define CSR_EFUSE_CFG_SC_EFUSE_PARTIAL_GOOD3_REG (CSR_EFUSE_CFG_BASE + 0xE02C) /* L3D Partial Good信息 */ +#define CSR_EFUSE_CFG_SC_EFUSE_PARTIAL_GOOD4_REG (CSR_EFUSE_CFG_BASE + 0xE030) /* CPU Cluster与L3D的组合Partial Good信息 */ +#define CSR_EFUSE_CFG_SC_EFUSE_SECURE_INFO_REG (CSR_EFUSE_CFG_BASE + 0xE050) /* EFUSE中的安全访问查询 */ +#define CSR_EFUSE_CFG_SC_EFUSE_NS_FORBID_REG (CSR_EFUSE_CFG_BASE + 0xE080) /* 非安全启动禁止位 */ +#define CSR_EFUSE_CFG_SC_EFUSE_BOOTROM_REG (CSR_EFUSE_CFG_BASE + 0xE084) /* BOOTROM启动指示 */ +#define CSR_EFUSE_CFG_SC_EFUSE_SIOE_IO_MIRROR_REG (CSR_EFUSE_CFG_BASE + 0xE090) +#define CSR_EFUSE_CFG_EFUSE_CFG_VERSION0_REG (CSR_EFUSE_CFG_BASE + 0xE0A0) /* VERSION寄存器0 */ +#define CSR_EFUSE_CFG_EFUSE_CFG_MAGIC_WORD_REG (CSR_EFUSE_CFG_BASE + 0xE0A4) /* EFUSE_CFG 版本号锁定寄存器 */ +#define CSR_EFUSE_CFG_EFUSE_CFG_ECO_CFG0_REG (CSR_EFUSE_CFG_BASE + 0xE0A8) /* 用于ECO的冗余配置寄存器1 */ +#define CSR_EFUSE_CFG_EFUSE_CFG_ECO_CFG1_REG (CSR_EFUSE_CFG_BASE + 0xE0AC) /* 用于ECO的冗余配置寄存器1 */ +#define CSR_EFUSE_CFG_EFUSE_CFG_ECO_CFG2_REG (CSR_EFUSE_CFG_BASE + 0xE0B0) /* 用于ECO的冗余配置寄存器2 */ +#define CSR_EFUSE_CFG_EFUSE_CFG_ECO_CFG3_REG (CSR_EFUSE_CFG_BASE + 0xE0B4) /* 用于ECO的冗余配置寄存器3 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_INFO_REG (CSR_EFUSE_CFG_BASE + 0xE100) /* AVS信息 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM0_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE110) /* 第一次校准，HPM0中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM1_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE114) /* 第一次校准，HPM1中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM2_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE118) /* 第一次校准，HPM2中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM3_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE11C) /* 第一次校准，HPM3中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM4_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE120) /* 第一次校准，HPM4中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM5_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE124) /* 第一次校准，HPM5中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM6_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE128) /* 第一次校准，HPM6中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM7_1ST_REG (CSR_EFUSE_CFG_BASE + 0xE12C) /* 第一次校准，HPM7中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM0_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE130) /* 第二次校准，HPM0中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM1_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE134) /* 第二次校准，HPM1中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM2_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE138) /* 第二次校准，HPM2中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM3_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE13C) /* 第二次校准，HPM3中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM4_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE140) /* 第二次校准，HPM4中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM5_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE144) /* 第二次校准，HPM5中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM6_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE148) /* 第二次校准，HPM6中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_AVS0_HPM7_2ED_REG (CSR_EFUSE_CFG_BASE + 0xE14C) /* 第二次校准，HPM7中RINGOSC0和RINGOSC0数据 */ +#define CSR_EFUSE_CFG_SC_EFUSE_SEC_LOCK_REG (CSR_EFUSE_CFG_BASE + 0xE150) +#define CSR_EFUSE_CFG_SC_EFUSE_PD_INFO_REG (CSR_EFUSE_CFG_BASE + 0xE160) /* EFUSE L3 PD寄存器 */ +#define CSR_EFUSE_CFG_SC_EFUSE_NS_FORBID_INITIAL_REG (CSR_EFUSE_CFG_BASE + 0xE170) /* EFUSE_NS_FORBID原始码值 */ +#define CSR_EFUSE_CFG_SC_EFUSE_NS_FORBID_CODE_REG (CSR_EFUSE_CFG_BASE + 0xE180) /* EFUSE_NS_FORBID映射后码值 */ +#define CSR_EFUSE_CFG_SC_DIE_ID0_REG (CSR_EFUSE_CFG_BASE + 0xE200) /* EFUSE DIE ID寄存器[31:0] */ +#define CSR_EFUSE_CFG_SC_DIE_ID1_REG (CSR_EFUSE_CFG_BASE + 0xE204) /* EFUSE DIE ID寄存器[63:32] */ +#define CSR_EFUSE_CFG_SC_DIE_ID2_REG (CSR_EFUSE_CFG_BASE + 0xE208) /* EFUSE DIE ID寄存器[95:64] */ +#define CSR_EFUSE_CFG_SC_DIE_ID3_REG (CSR_EFUSE_CFG_BASE + 0xE20C) /* EFUSE DIE ID寄存器[127:96] */ +#define CSR_EFUSE_CFG_SC_DIE_ID4_REG (CSR_EFUSE_CFG_BASE + 0xE210) /* EFUSE DIE ID寄存器[159:128] */ +#define CSR_EFUSE_CFG_SC_DIE_ID5_REG (CSR_EFUSE_CFG_BASE + 0xE214) /* EFUSE DIE ID寄存器[191:160] */ +#define CSR_EFUSE_CFG_SC_DIE_ID6_REG (CSR_EFUSE_CFG_BASE + 0xE218) /* EFUSE DIE ID寄存器[223:192] */ +#define CSR_EFUSE_CFG_SC_DIE_ID7_REG (CSR_EFUSE_CFG_BASE + 0xE21C) /* EFUSE DIE ID寄存器[255:224] */ +#define CSR_EFUSE_CFG_SC_DIE_ID8_REG (CSR_EFUSE_CFG_BASE + 0xE220) /* EFUSE DIE ID寄存器[287:256] */ +#define CSR_EFUSE_CFG_SC_DIE_ID9_REG (CSR_EFUSE_CFG_BASE + 0xE224) /* EFUSE DIE ID寄存器[319:288] */ +#define CSR_EFUSE_CFG_SC_DIE_ID10_REG (CSR_EFUSE_CFG_BASE + 0xE228) /* EFUSE DIE ID寄存器[351:320] */ +#define CSR_EFUSE_CFG_SC_DIE_ID11_REG (CSR_EFUSE_CFG_BASE + 0xE22C) /* EFUSE DIE ID寄存器[383:352] */ +#define CSR_EFUSE_CFG_SC_DIE_ID12_REG (CSR_EFUSE_CFG_BASE + 0xE230) /* EFUSE DIE ID寄存器[415:384] */ +#define CSR_EFUSE_CFG_SC_DIE_ID13_REG (CSR_EFUSE_CFG_BASE + 0xE234) /* EFUSE DIE ID寄存器[447:416] */ +#define CSR_EFUSE_CFG_SC_DIE_ID14_REG (CSR_EFUSE_CFG_BASE + 0xE238) /* EFUSE DIE ID寄存器[479:448] */ +#define CSR_EFUSE_CFG_SC_DIE_ID15_REG (CSR_EFUSE_CFG_BASE + 0xE23C) /* EFUSE DIE ID寄存器[511:480] */ +#define CSR_EFUSE_CFG_SC_DIE_ID16_REG (CSR_EFUSE_CFG_BASE + 0xE240) /* EFUSE DIE ID寄存器[543:512] */ +#define CSR_EFUSE_CFG_SC_DIE_ID17_REG (CSR_EFUSE_CFG_BASE + 0xE244) /* EFUSE DIE ID寄存器[575:544] */ +#define CSR_EFUSE_CFG_SC_DIE_ID18_REG (CSR_EFUSE_CFG_BASE + 0xE248) /* EFUSE DIE ID寄存器[607:576] */ +#define CSR_EFUSE_CFG_SC_DIE_ID19_REG (CSR_EFUSE_CFG_BASE + 0xE24C) /* EFUSE DIE ID寄存器[639:608] */ +#define CSR_EFUSE_CFG_SC_DIE_ID20_REG (CSR_EFUSE_CFG_BASE + 0xE250) /* EFUSE DIE ID寄存器[671:640] */ +#define CSR_EFUSE_CFG_SC_DIE_ID21_REG (CSR_EFUSE_CFG_BASE + 0xE254) /* EFUSE DIE ID寄存器[703:672] */ +#define CSR_EFUSE_CFG_SC_DIE_ID22_REG (CSR_EFUSE_CFG_BASE + 0xE258) /* EFUSE DIE ID寄存器[735:704] */ +#define CSR_EFUSE_CFG_SC_DIE_ID23_REG (CSR_EFUSE_CFG_BASE + 0xE25C) /* EFUSE DIE ID寄存器[767:736] */ +#define CSR_EFUSE_CFG_SC_DIE_ID24_REG (CSR_EFUSE_CFG_BASE + 0xE260) /* EFUSE DIE ID寄存器[799:768] */ +#define CSR_EFUSE_CFG_SC_DIE_ID25_REG (CSR_EFUSE_CFG_BASE + 0xE264) /* EFUSE DIE ID寄存器[831:800] */ +#define CSR_EFUSE_CFG_SC_DIE_ID26_REG (CSR_EFUSE_CFG_BASE + 0xE268) /* EFUSE DIE ID寄存器[863:832] */ +#define CSR_EFUSE_CFG_SC_DIE_ID27_REG (CSR_EFUSE_CFG_BASE + 0xE26C) /* EFUSE DIE ID寄存器[895:864] */ +#define CSR_EFUSE_CFG_SC_DIE_ID28_REG (CSR_EFUSE_CFG_BASE + 0xE270) /* EFUSE DIE ID寄存器[927:896] */ +#define CSR_EFUSE_CFG_SC_DIE_ID29_REG (CSR_EFUSE_CFG_BASE + 0xE274) /* EFUSE DIE ID寄存器[959:928] */ +#define CSR_EFUSE_CFG_SC_DIE_ID30_REG (CSR_EFUSE_CFG_BASE + 0xE278) /* EFUSE DIE ID寄存器[991:960] */ +#define CSR_EFUSE_CFG_SC_DIE_ID31_REG (CSR_EFUSE_CFG_BASE + 0xE27C) /* EFUSE DIE ID寄存器[1023:992] */ +#define CSR_EFUSE_CFG_SC_DIE_ID32_REG (CSR_EFUSE_CFG_BASE + 0xE280) /* EFUSE DIE ID寄存器[1055:1024] */ +#define CSR_EFUSE_CFG_SC_DIE_ID33_REG (CSR_EFUSE_CFG_BASE + 0xE284) /* EFUSE DIE ID寄存器[1087:1056] */ +#define CSR_EFUSE_CFG_SC_DIE_ID34_REG (CSR_EFUSE_CFG_BASE + 0xE288) /* EFUSE DIE ID寄存器[1119:1088] */ +#define CSR_EFUSE_CFG_SC_DIE_ID35_REG (CSR_EFUSE_CFG_BASE + 0xE28C) /* EFUSE DIE ID寄存器[1151:1120] */ +#define CSR_EFUSE_CFG_SC_DIE_ID36_REG (CSR_EFUSE_CFG_BASE + 0xE290) /* EFUSE DIE ID寄存器[1183:1152] */ +#define CSR_EFUSE_CFG_SC_DIE_ID37_REG (CSR_EFUSE_CFG_BASE + 0xE294) /* EFUSE DIE ID寄存器[1215:1184] */ +#define CSR_EFUSE_CFG_SC_DIE_ID38_REG (CSR_EFUSE_CFG_BASE + 0xE298) /* EFUSE DIE ID寄存器[1247:1216] */ +#define CSR_EFUSE_CFG_SC_DIE_ID39_REG (CSR_EFUSE_CFG_BASE + 0xE29C) /* EFUSE DIE ID寄存器[1279:1248] */ +#define CSR_EFUSE_CFG_SC_DIE_ID40_REG (CSR_EFUSE_CFG_BASE + 0xE2A0) /* EFUSE DIE ID寄存器[1311:1280] */ +#define CSR_EFUSE_CFG_SC_DIE_ID41_REG (CSR_EFUSE_CFG_BASE + 0xE2A4) /* EFUSE DIE ID寄存器[1343:1312] */ +#define CSR_EFUSE_CFG_SC_DIE_ID42_REG (CSR_EFUSE_CFG_BASE + 0xE2A8) /* EFUSE DIE ID寄存器[1375:1344] */ +#define CSR_EFUSE_CFG_SC_DIE_ID43_REG (CSR_EFUSE_CFG_BASE + 0xE2AC) /* EFUSE DIE ID寄存器[1407:1376] */ +#define CSR_EFUSE_CFG_SC_DIE_ID44_REG (CSR_EFUSE_CFG_BASE + 0xE2B0) /* EFUSE DIE ID寄存器[1439:1408] */ +#define CSR_EFUSE_CFG_SC_DIE_ID45_REG (CSR_EFUSE_CFG_BASE + 0xE2B4) /* EFUSE DIE ID寄存器[1471:1440] */ +#define CSR_EFUSE_CFG_SC_DIE_ID46_REG (CSR_EFUSE_CFG_BASE + 0xE2B8) /* EFUSE DIE ID寄存器[1503:1472] */ +#define CSR_EFUSE_CFG_SC_SYSCTRL_LOCK_REG (CSR_EFUSE_CFG_BASE + 0xF100) /* 系统控制器锁定寄存器。（注意：1，此寄存器空间必须是安全访问才能成功） */ +#define CSR_EFUSE_CFG_SC_SYSCTRL_UNLOCK_REG (CSR_EFUSE_CFG_BASE + 0xF110) /* 系统控制器解锁寄存器。（注意：1，此寄存器空间必须是安全访问才能成功） */ +#define CSR_EFUSE_CFG_SC_PG_INFO_INPUT_REG (CSR_EFUSE_CFG_BASE + 0xF120) /* Partial Good info输入寄存器 */ +#define CSR_EFUSE_CFG_SC_PG_INFO_CTRL_REG (CSR_EFUSE_CFG_BASE + 0xF124) /* Partial Good info控制寄存器 */ +#define CSR_EFUSE_CFG_SC_ECO_RSV0_REG (CSR_EFUSE_CFG_BASE + 0xFF04) /* ECO 寄存器1 */ +#define CSR_EFUSE_CFG_SC_ECO_RSV1_REG (CSR_EFUSE_CFG_BASE + 0xFF08) /* ECO 寄存器2 */ +#define CSR_EFUSE_CFG_SC_ECO_RSV2_REG (CSR_EFUSE_CFG_BASE + 0xFF0C) /* ECO 寄存器3 */ +#define CSR_EFUSE_CFG_SC_ECO_RSV4_REG (CSR_EFUSE_CFG_BASE + 0xFF10) /* ECO 寄存器4 */ +#define CSR_EFUSE_CFG_SC_ECO_RSV5_REG (CSR_EFUSE_CFG_BASE + 0xFF14) /* ECO 寄存器5 */ +#define CSR_EFUSE_CFG_FPGA_VER_REG (CSR_EFUSE_CFG_BASE + 0xFFFC) /* FPGA版本寄存器 */ + +#endif // __HI1823E_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/fabric_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/fabric_c_union_define.h new file mode 100644 index 000000000..9eec57a7c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/fabric_c_union_define.h @@ -0,0 +1,1629 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : fabric_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/21 14:21:49 Create file +// ****************************************************************************** + +#ifndef __FABRIC_C_UNION_DEFINE_H__ +#define __FABRIC_C_UNION_DEFINE_H__ + +/* Define the union csr_sc_pllfctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_refdiv : 6 ; /* [5:0] */ + u32 pll0_fbdiv : 12 ; /* [17:6] */ + u32 pll0_postdiv1 : 3 ; /* [20:18] */ + u32 pll0_postdiv2 : 3 ; /* [23:21] */ + u32 pll0_bypass : 1 ; /* [24] */ + u32 pll0_en : 1 ; /* [25] */ + u32 pll0_dsmen : 1 ; /* [26] */ + u32 pll0_dacen : 1 ; /* [27] */ + u32 pll0_fout4phaseen : 1 ; /* [28] */ + u32 pll0_foutpostdiven : 1 ; /* [29] */ + u32 pll0_foutvcoen : 1 ; /* [30] */ + u32 rsv_1 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pllfctrl0_u; + +/* Define the union csr_sc_pllfctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_frac : 26 ; /* [25:0] */ + u32 rsv_3 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pllfctrl1_u; + +/* Define the union csr_sc_pll_clk_bypass0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_bypass_external_n : 1 ; /* [0] */ + u32 rsv_5 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll_clk_bypass0_u; + +/* Define the union csr_sc_switch_clk_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 switch_div_sel_kernel_ultrasoc : 1 ; /* [0] */ + u32 switch_div_sel_gic : 1 ; /* [1] */ + u32 switch_div_sel_poe : 1 ; /* [2] */ + u32 rsv_7 : 29 ; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_switch_clk_sel_u; + +/* Define the union csr_sc_pll_lp_clk_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lp_clk_sel : 3 ; /* [2:0] */ + u32 rsv_9 : 29 ; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll_lp_clk_sel_u; + +/* Define the union csr_sc_l3d_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_l3d0 : 1 ; /* [0] */ + u32 icg_en_l3d1 : 1 ; /* [1] */ + u32 icg_en_l3d2 : 1 ; /* [2] */ + u32 icg_en_l3d3 : 1 ; /* [3] */ + u32 rsv_11 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3d_clk_en_u; + +/* Define the union csr_sc_l3d_clk_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_dis_l3d0 : 1 ; /* [0] */ + u32 icg_dis_l3d1 : 1 ; /* [1] */ + u32 icg_dis_l3d2 : 1 ; /* [2] */ + u32 icg_dis_l3d3 : 1 ; /* [3] */ + u32 rsv_13 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3d_clk_dis_u; + +/* Define the union csr_sc_hha_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_hha0 : 1 ; /* [0] */ + u32 icg_en_hha1 : 1 ; /* [1] */ + u32 rsv_15 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_clk_en_u; + +/* Define the union csr_sc_hha_clk_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_dis_hha0 : 1 ; /* [0] */ + u32 icg_dis_hha1 : 1 ; /* [1] */ + u32 rsv_17 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_clk_dis_u; + +/* Define the union csr_sc_mn_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_mn : 1 ; /* [0] */ + u32 rsv_19 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_mn_clk_en_u; + +/* Define the union csr_sc_mn_clk_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_dis_mn : 1 ; /* [0] */ + u32 rsv_21 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_mn_clk_dis_u; + +/* Define the union csr_sc_l3_mbist_clk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_mbist_l3d0 : 1 ; /* [0] */ + u32 icg_en_mbist_l3d1 : 1 ; /* [1] */ + u32 icg_en_mbist_l3d2 : 1 ; /* [2] */ + u32 icg_en_mbist_l3d3 : 1 ; /* [3] */ + u32 icg_en_mbist_l3t0 : 1 ; /* [4] */ + u32 icg_en_mbist_l3t1 : 1 ; /* [5] */ + u32 icg_en_mbist_l3t2 : 1 ; /* [6] */ + u32 icg_en_mbist_l3t3 : 1 ; /* [7] */ + u32 icg_en_mbist_l3t4 : 1 ; /* [8] */ + u32 icg_en_mbist_l3t5 : 1 ; /* [9] */ + u32 icg_en_mbist_l3t6 : 1 ; /* [10] */ + u32 icg_en_mbist_l3t7 : 1 ; /* [11] */ + u32 rsv_23 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3_mbist_clk_en_u; + +/* Define the union csr_sc_l3_mbist_clk_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_dis_mbist_l3d0 : 1 ; /* [0] */ + u32 icg_dis_mbist_l3d1 : 1 ; /* [1] */ + u32 icg_dis_mbist_l3d2 : 1 ; /* [2] */ + u32 icg_dis_mbist_l3d3 : 1 ; /* [3] */ + u32 icg_dis_mbist_l3t0 : 1 ; /* [4] */ + u32 icg_dis_mbist_l3t1 : 1 ; /* [5] */ + u32 icg_dis_mbist_l3t2 : 1 ; /* [6] */ + u32 icg_dis_mbist_l3t3 : 1 ; /* [7] */ + u32 icg_dis_mbist_l3t4 : 1 ; /* [8] */ + u32 icg_dis_mbist_l3t5 : 1 ; /* [9] */ + u32 icg_dis_mbist_l3t6 : 1 ; /* [10] */ + u32 icg_dis_mbist_l3t7 : 1 ; /* [11] */ + u32 rsv_25 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3_mbist_clk_dis_u; + +/* Define the union csr_sc_l3d_reset_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_l3d0 : 1 ; /* [0] */ + u32 srst_req_l3d1 : 1 ; /* [1] */ + u32 srst_req_l3d2 : 1 ; /* [2] */ + u32 srst_req_l3d3 : 1 ; /* [3] */ + u32 rsv_27 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3d_reset_req_u; + +/* Define the union csr_sc_l3d_reset_dreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_dreq_l3d0 : 1 ; /* [0] */ + u32 srst_dreq_l3d1 : 1 ; /* [1] */ + u32 srst_dreq_l3d2 : 1 ; /* [2] */ + u32 srst_dreq_l3d3 : 1 ; /* [3] */ + u32 rsv_29 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3d_reset_dreq_u; + +/* Define the union csr_sc_hha_reset_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_hha0 : 1 ; /* [0] */ + u32 srst_req_hha1 : 1 ; /* [1] */ + u32 rsv_31 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_reset_req_u; + +/* Define the union csr_sc_hha_reset_dreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_dreq_hha0 : 1 ; /* [0] */ + u32 srst_dreq_hha1 : 1 ; /* [1] */ + u32 rsv_33 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_reset_dreq_u; + +/* Define the union csr_sc_mn_reset_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_mn : 1 ; /* [0] */ + u32 rsv_35 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_mn_reset_req_u; + +/* Define the union csr_sc_mn_reset_dreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_dreq_mn : 1 ; /* [0] */ + u32 rsv_37 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_mn_reset_dreq_u; + +/* Define the union csr_sc_cpm_reset_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_cpm : 1 ; /* [0] */ + u32 rsv_39 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpm_reset_req_u; + +/* Define the union csr_sc_cpm_reset_dreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_dreq_cpm : 1 ; /* [0] */ + u32 rsv_41 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpm_reset_dreq_u; + +/* Define the union csr_sc_ffs_reset_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_ffs : 1 ; /* [0] */ + u32 rsv_43 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_ffs_reset_req_u; + +/* Define the union csr_sc_ffs_reset_dreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_dreq_ffs : 1 ; /* [0] */ + u32 rsv_45 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_ffs_reset_dreq_u; + +/* Define the union csr_sc_hha_mbist_reset_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_req_mbist_l3d0 : 1 ; /* [0] */ + u32 srst_req_mbist_l3d1 : 1 ; /* [1] */ + u32 srst_req_mbist_l3d2 : 1 ; /* [2] */ + u32 srst_req_mbist_l3d3 : 1 ; /* [3] */ + u32 srst_req_mbist_l3t0 : 1 ; /* [4] */ + u32 srst_req_mbist_l3t1 : 1 ; /* [5] */ + u32 srst_req_mbist_l3t2 : 1 ; /* [6] */ + u32 srst_req_mbist_l3t3 : 1 ; /* [7] */ + u32 srst_req_mbist_l3t4 : 1 ; /* [8] */ + u32 srst_req_mbist_l3t5 : 1 ; /* [9] */ + u32 srst_req_mbist_l3t6 : 1 ; /* [10] */ + u32 srst_req_mbist_l3t7 : 1 ; /* [11] */ + u32 rsv_47 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_mbist_reset_req_u; + +/* Define the union csr_sc_hha_mbist_reset_dreq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_dreq_mbist_l3d0 : 1 ; /* [0] */ + u32 srst_dreq_mbist_l3d1 : 1 ; /* [1] */ + u32 srst_dreq_mbist_l3d2 : 1 ; /* [2] */ + u32 srst_dreq_mbist_l3d3 : 1 ; /* [3] */ + u32 srst_dreq_mbist_l3t0 : 1 ; /* [4] */ + u32 srst_dreq_mbist_l3t1 : 1 ; /* [5] */ + u32 srst_dreq_mbist_l3t2 : 1 ; /* [6] */ + u32 srst_dreq_mbist_l3t3 : 1 ; /* [7] */ + u32 srst_dreq_mbist_l3t4 : 1 ; /* [8] */ + u32 srst_dreq_mbist_l3t5 : 1 ; /* [9] */ + u32 srst_dreq_mbist_l3t6 : 1 ; /* [10] */ + u32 srst_dreq_mbist_l3t7 : 1 ; /* [11] */ + u32 rsv_49 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_mbist_reset_dreq_u; + +/* Define the union csr_sc_ts_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_ts_en : 1 ; /* [0] */ + u32 rsv_51 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_ts_en_u; + +/* Define the union csr_sc_tsensor0_alarm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_low : 10 ; /* [9:0] */ + u32 rsv_54 : 6 ; /* [15:10] */ + u32 tsensor0_high : 10 ; /* [25:16] */ + u32 rsv_55 : 6 ; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_alarm_u; + +/* Define the union csr_sc_tsensor0_sample_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_sample_shift_num : 4 ; /* [3:0] */ + u32 rsv_57 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_sample_num_u; + +/* Define the union csr_sc_tsensor0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_temp_en : 1 ; /* [0] */ + u32 tsensor0_temp_calib : 1 ; /* [1] */ + u32 rsv_60 : 10 ; /* [11:2] */ + u32 tsensor0_temp_ct_sel : 2 ; /* [13:12] */ + u32 rsv_61 : 18 ; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_ctrl_u; + +/* Define the union csr_sc_tsensor0_vcalib_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_temp_ready_sel : 1 ; /* [0] */ + u32 tsensor0_temp_cfg : 8 ; /* [8:1] */ + u32 rsv_63 : 23 ; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_vcalib_u; + +/* Define the union csr_sc_poe_smmu_enent_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_poe_smmu_event_en : 1 ; /* [0] */ + u32 rsv_65 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_poe_smmu_enent_en_u; + +/* Define the union csr_sc_port_ctrl_ring_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 close_port_gic : 1 ; /* [0] */ + u32 close_port_l3dright3 : 1 ; /* [1] */ + u32 close_port_l3dright2 : 1 ; /* [2] */ + u32 close_port_l3dright1 : 1 ; /* [3] */ + u32 close_port_l3dright0 : 1 ; /* [4] */ + u32 close_port_l3dleft3 : 1 ; /* [5] */ + u32 close_port_l3dleft2 : 1 ; /* [6] */ + u32 close_port_l3dleft1 : 1 ; /* [7] */ + u32 close_port_l3dleft0 : 1 ; /* [8] */ + u32 close_port_l3t7 : 1 ; /* [9] */ + u32 close_port_l3t6 : 1 ; /* [10] */ + u32 close_port_l3t5 : 1 ; /* [11] */ + u32 close_port_l3t4 : 1 ; /* [12] */ + u32 close_port_l3t3 : 1 ; /* [13] */ + u32 close_port_l3t2 : 1 ; /* [14] */ + u32 close_port_l3t1 : 1 ; /* [15] */ + u32 close_port_l3t0 : 1 ; /* [16] */ + u32 close_port_hha3 : 1 ; /* [17] */ + u32 close_port_hha2 : 1 ; /* [18] */ + u32 close_port_hha1 : 1 ; /* [19] */ + u32 close_port_hha0 : 1 ; /* [20] */ + u32 close_port_mn : 1 ; /* [21] */ + u32 close_port_peri : 1 ; /* [22] */ + u32 close_port_poe : 1 ; /* [23] */ + u32 close_port_sllc3 : 1 ; /* [24] */ + u32 close_port_sllc2 : 1 ; /* [25] */ + u32 close_port_sllc1 : 1 ; /* [26] */ + u32 close_port_sllc0 : 1 ; /* [27] */ + u32 rsv_67 : 4 ; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_port_ctrl_ring_u; + +/* Define the union csr_sc_acg_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acg_enable_sel : 8 ; /* [7:0] */ + u32 acg_off_mod : 1 ; /* [8] */ + u32 acg_off_time_step : 1 ; /* [9] */ + u32 acg_trim : 2 ; /* [11:10] */ + u32 acg_glitch_test : 1 ; /* [12] */ + u32 acg_div64_en : 1 ; /* [13] */ + u32 acg_test_ffs : 2 ; /* [15:14] */ + u32 acg_enable_mod : 2 ; /* [17:16] */ + u32 acg_d_rate : 2 ; /* [19:18] */ + u32 rsv_69 : 12 ; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_acg_cfg0_u; + +/* Define the union csr_sc_acg_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acg_test_cpm : 8 ; /* [7:0] */ + u32 rsv_71 : 6 ; /* [13:8] */ + u32 acg_cpm_period : 1 ; /* [14] */ + u32 acg_edge_sel : 1 ; /* [15] */ + u32 acg_data_mod : 2 ; /* [17:16] */ + u32 acg_data_limit_e : 1 ; /* [18] */ + u32 acg_cpm_threshold_r : 6 ; /* [24:19] */ + u32 acg_threshold_f : 6 ; /* [30:25] */ + u32 acg_pulse_width_sel : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_acg_cfg1_u; + +/* Define the union csr_sc_acg_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acg_svt_sl : 4 ; /* [3:0] */ + u32 acg_svt_ll : 4 ; /* [7:4] */ + u32 acg_lvt_sl : 4 ; /* [11:8] */ + u32 acg_lvt_ll : 4 ; /* [15:12] */ + u32 rsv_73 : 16 ; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_acg_cfg2_u; + +/* Define the union csr_sc_acg_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acg_bypass : 1 ; /* [0] */ + u32 rsv_75 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_acg_bypass_u; + +/* Define the union csr_sc_pll_src_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_unlock : 1 ; /* [0] */ + u32 rsv_77 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll_src_int_u; + +/* Define the union csr_sc_pll_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_unlock_int_mask : 1 ; /* [0] */ + u32 rsv_79 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll_int_mask_u; + +/* Define the union csr_sc_pll0_out_clk_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll_out_clk_sel : 1 ; /* [0] */ + u32 rsv_81 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll0_out_clk_sel_u; + +/* Define the union csr_sc_tsensor0_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_under : 1 ; /* [0] */ + u32 tsensor0_over : 1 ; /* [1] */ + u32 rsv_83 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_int_u; + +/* Define the union csr_sc_tsensor0_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_under_int_mask : 1 ; /* [0] */ + u32 tsensor0_over_int_mask : 1 ; /* [1] */ + u32 rsv_85 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_int_mask_u; + +/* Define the union csr_sc_cfg_power_down_l3d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_power_down_l3d0 : 6 ; /* [5:0] */ + u32 rsv_90 : 2 ; /* [7:6] */ + u32 cfg_power_down_l3d1 : 6 ; /* [13:8] */ + u32 rsv_91 : 2 ; /* [15:14] */ + u32 cfg_power_down_l3d2 : 6 ; /* [21:16] */ + u32 rsv_92 : 2 ; /* [23:22] */ + u32 cfg_power_down_l3d3 : 6 ; /* [29:24] */ + u32 rsv_93 : 2 ; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cfg_power_down_l3d_u; + +/* Define the union csr_sc_cpu_stanbywfe_cfg_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpu_standbywfe_other_die_cpu0 : 1 ; /* [0] */ + u32 cpu_standbywfe_other_die_cpu1 : 1 ; /* [1] */ + u32 cpu_standbywfe_other_die_cpu2 : 1 ; /* [2] */ + u32 cpu_standbywfe_other_die_cpu3 : 1 ; /* [3] */ + u32 cpu_standbywfe_other_die_cpu4 : 1 ; /* [4] */ + u32 cpu_standbywfe_other_die_cpu5 : 1 ; /* [5] */ + u32 cpu_standbywfe_other_die_cpu6 : 1 ; /* [6] */ + u32 cpu_standbywfe_other_die_cpu7 : 1 ; /* [7] */ + u32 cpu_standbywfe_other_die_cpu8 : 1 ; /* [8] */ + u32 cpu_standbywfe_other_die_cpu9 : 1 ; /* [9] */ + u32 cpu_standbywfe_other_die_cpu10 : 1 ; /* [10] */ + u32 cpu_standbywfe_other_die_cpu11 : 1 ; /* [11] */ + u32 cpu_standbywfe_other_die_cpu12 : 1 ; /* [12] */ + u32 cpu_standbywfe_other_die_cpu13 : 1 ; /* [13] */ + u32 cpu_standbywfe_other_die_cpu14 : 1 ; /* [14] */ + u32 cpu_standbywfe_other_die_cpu15 : 1 ; /* [15] */ + u32 cpu_standbywfe_other_die_cpu16 : 1 ; /* [16] */ + u32 cpu_standbywfe_other_die_cpu17 : 1 ; /* [17] */ + u32 cpu_standbywfe_other_die_cpu18 : 1 ; /* [18] */ + u32 cpu_standbywfe_other_die_cpu19 : 1 ; /* [19] */ + u32 cpu_standbywfe_other_die_cpu20 : 1 ; /* [20] */ + u32 cpu_standbywfe_other_die_cpu21 : 1 ; /* [21] */ + u32 cpu_standbywfe_other_die_cpu22 : 1 ; /* [22] */ + u32 cpu_standbywfe_other_die_cpu23 : 1 ; /* [23] */ + u32 cpu_standbywfe_other_die_cpu24 : 1 ; /* [24] */ + u32 cpu_standbywfe_other_die_cpu25 : 1 ; /* [25] */ + u32 cpu_standbywfe_other_die_cpu26 : 1 ; /* [26] */ + u32 cpu_standbywfe_other_die_cpu27 : 1 ; /* [27] */ + u32 cpu_standbywfe_other_die_cpu28 : 1 ; /* [28] */ + u32 cpu_standbywfe_other_die_cpu29 : 1 ; /* [29] */ + u32 cpu_standbywfe_other_die_cpu30 : 1 ; /* [30] */ + u32 cpu_standbywfe_other_die_cpu31 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpu_stanbywfe_cfg_set_u; + +/* Define the union csr_sc_cpu_stanbywfe_cfg_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpu_not_standbywfe_other_die_cpu0 : 1 ; /* [0] */ + u32 cpu_not_standbywfe_other_die_cpu1 : 1 ; /* [1] */ + u32 cpu_not_standbywfe_other_die_cpu2 : 1 ; /* [2] */ + u32 cpu_not_standbywfe_other_die_cpu3 : 1 ; /* [3] */ + u32 cpu_not_standbywfe_other_die_cpu4 : 1 ; /* [4] */ + u32 cpu_not_standbywfe_other_die_cpu5 : 1 ; /* [5] */ + u32 cpu_not_standbywfe_other_die_cpu6 : 1 ; /* [6] */ + u32 cpu_not_standbywfe_other_die_cpu7 : 1 ; /* [7] */ + u32 cpu_not_standbywfe_other_die_cpu8 : 1 ; /* [8] */ + u32 cpu_not_standbywfe_other_die_cpu9 : 1 ; /* [9] */ + u32 cpu_not_standbywfe_other_die_cpu10 : 1 ; /* [10] */ + u32 cpu_not_standbywfe_other_die_cpu11 : 1 ; /* [11] */ + u32 cpu_not_standbywfe_other_die_cpu12 : 1 ; /* [12] */ + u32 cpu_not_standbywfe_other_die_cpu13 : 1 ; /* [13] */ + u32 cpu_not_standbywfe_other_die_cpu14 : 1 ; /* [14] */ + u32 cpu_not_standbywfe_other_die_cpu15 : 1 ; /* [15] */ + u32 cpu_not_standbywfe_other_die_cpu16 : 1 ; /* [16] */ + u32 cpu_not_standbywfe_other_die_cpu17 : 1 ; /* [17] */ + u32 cpu_not_standbywfe_other_die_cpu18 : 1 ; /* [18] */ + u32 cpu_not_standbywfe_other_die_cpu19 : 1 ; /* [19] */ + u32 cpu_not_standbywfe_other_die_cpu20 : 1 ; /* [20] */ + u32 cpu_not_standbywfe_other_die_cpu21 : 1 ; /* [21] */ + u32 cpu_not_standbywfe_other_die_cpu22 : 1 ; /* [22] */ + u32 cpu_not_standbywfe_other_die_cpu23 : 1 ; /* [23] */ + u32 cpu_not_standbywfe_other_die_cpu24 : 1 ; /* [24] */ + u32 cpu_not_standbywfe_other_die_cpu25 : 1 ; /* [25] */ + u32 cpu_not_standbywfe_other_die_cpu26 : 1 ; /* [26] */ + u32 cpu_not_standbywfe_other_die_cpu27 : 1 ; /* [27] */ + u32 cpu_not_standbywfe_other_die_cpu28 : 1 ; /* [28] */ + u32 cpu_not_standbywfe_other_die_cpu29 : 1 ; /* [29] */ + u32 cpu_not_standbywfe_other_die_cpu30 : 1 ; /* [30] */ + u32 cpu_not_standbywfe_other_die_cpu31 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpu_stanbywfe_cfg_clr_u; + +/* Define the union csr_sc_cpu_stanbywfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_cpu_standwfe : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpu_stanbywfe_u; + +/* Define the union csr_sc_cpu_stanbywfe_origin_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_cpu_standwfe_origin : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpu_stanbywfe_origin_u; + +/* Define the union csr_sc_pll_lock_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_lock : 1 ; /* [0] */ + u32 rsv_95 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll_lock_status_u; + +/* Define the union csr_sc_l3d_clk_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_st_l3d0 : 1 ; /* [0] */ + u32 icg_st_l3d1 : 1 ; /* [1] */ + u32 icg_st_l3d2 : 1 ; /* [2] */ + u32 icg_st_l3d3 : 1 ; /* [3] */ + u32 rsv_97 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3d_clk_st_u; + +/* Define the union csr_sc_hha_clk_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_st_hha0 : 1 ; /* [0] */ + u32 icg_st_hha1 : 1 ; /* [1] */ + u32 rsv_99 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_clk_st_u; + +/* Define the union csr_sc_mn_clk_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_st_mn : 1 ; /* [0] */ + u32 rsv_101 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_mn_clk_st_u; + +/* Define the union csr_sc_l3_mbist_clk_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_st_mbist_l3d0 : 1 ; /* [0] */ + u32 icg_st_mbist_l3d1 : 1 ; /* [1] */ + u32 icg_st_mbist_l3d2 : 1 ; /* [2] */ + u32 icg_st_mbist_l3d3 : 1 ; /* [3] */ + u32 icg_st_mbist_l3t0 : 1 ; /* [4] */ + u32 icg_st_mbist_l3t1 : 1 ; /* [5] */ + u32 icg_st_mbist_l3t2 : 1 ; /* [6] */ + u32 icg_st_mbist_l3t3 : 1 ; /* [7] */ + u32 icg_st_mbist_l3t4 : 1 ; /* [8] */ + u32 icg_st_mbist_l3t5 : 1 ; /* [9] */ + u32 icg_st_mbist_l3dt6 : 1 ; /* [10] */ + u32 icg_st_mbist_l3t7 : 1 ; /* [11] */ + u32 rsv_103 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3_mbist_clk_st_u; + +/* Define the union csr_sc_l3d_reset_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l3d0_srst_st : 1 ; /* [0] */ + u32 l3d1_srst_st : 1 ; /* [1] */ + u32 l3d2_srst_st : 1 ; /* [2] */ + u32 l3d3_srst_st : 1 ; /* [3] */ + u32 rsv_105 : 28 ; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3d_reset_st_u; + +/* Define the union csr_sc_hha_reset_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hha0_srst_st : 1 ; /* [0] */ + u32 hha1_srst_st : 1 ; /* [1] */ + u32 rsv_107 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_hha_reset_st_u; + +/* Define the union csr_sc_mn_reset_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mn_srst_st : 1 ; /* [0] */ + u32 rsv_109 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_mn_reset_st_u; + +/* Define the union csr_sc_cpm_reset_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpm_srst_st : 1 ; /* [0] */ + u32 rsv_111 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpm_reset_st_u; + +/* Define the union csr_sc_ffs_reset_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ffs_srst_st : 1 ; /* [0] */ + u32 rsv_113 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_ffs_reset_st_u; + +/* Define the union csr_sc_l3_mbsit_reset_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srst_st_mbist_l3d0 : 1 ; /* [0] */ + u32 srst_st_mbist_l3d1 : 1 ; /* [1] */ + u32 srst_st_mbist_l3d2 : 1 ; /* [2] */ + u32 srst_st_mbist_l3d3 : 1 ; /* [3] */ + u32 srst_st_mbist_l3t0 : 1 ; /* [4] */ + u32 srst_st_mbist_l3t1 : 1 ; /* [5] */ + u32 srst_st_mbist_l3t2 : 1 ; /* [6] */ + u32 srst_st_mbist_l3t3 : 1 ; /* [7] */ + u32 srst_st_mbist_l3t4 : 1 ; /* [8] */ + u32 srst_st_mbist_l3t5 : 1 ; /* [9] */ + u32 srst_st_mbist_l3dt6 : 1 ; /* [10] */ + u32 srst_st_mbist_l3t7 : 1 ; /* [11] */ + u32 rsv_115 : 20 ; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_l3_mbsit_reset_st_u; + +/* Define the union csr_sc_tsensor0_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_temp_out : 10 ; /* [9:0] */ + u32 rsv_118 : 2 ; /* [11:10] */ + u32 tsensor0_temp_ready : 1 ; /* [12] */ + u32 rsv_119 : 19 ; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_st_u; + +/* Define the union csr_sc_tsensor0_temp_sample_average_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor0_sample : 10 ; /* [9:0] */ + u32 rsv_121 : 21 ; /* [30:10] */ + u32 tsensor0_valid : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor0_temp_sample_average_u; + +/* Define the union csr_sc_cpu_stanbywfe_cfg_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpu_standbywfe_st_other_die_cpu0 : 1 ; /* [0] */ + u32 cpu_standbywfe_st_other_die_cpu1 : 1 ; /* [1] */ + u32 cpu_standbywfe_st_other_die_cpu2 : 1 ; /* [2] */ + u32 cpu_standbywfe_st_other_die_cpu3 : 1 ; /* [3] */ + u32 cpu_standbywfe_st_other_die_cpu4 : 1 ; /* [4] */ + u32 cpu_standbywfe_st_other_die_cpu5 : 1 ; /* [5] */ + u32 cpu_standbywfe_st_other_die_cpu6 : 1 ; /* [6] */ + u32 cpu_standbywfe_st_other_die_cpu7 : 1 ; /* [7] */ + u32 cpu_standbywfe_st_other_die_cpu8 : 1 ; /* [8] */ + u32 cpu_standbywfe_st_other_die_cpu9 : 1 ; /* [9] */ + u32 cpu_standbywfe_st_other_die_cpu10 : 1 ; /* [10] */ + u32 cpu_standbywfe_st_other_die_cpu11 : 1 ; /* [11] */ + u32 cpu_standbywfe_st_other_die_cpu12 : 1 ; /* [12] */ + u32 cpu_standbywfe_st_other_die_cpu13 : 1 ; /* [13] */ + u32 cpu_standbywfe_st_other_die_cpu14 : 1 ; /* [14] */ + u32 cpu_standbywfe_st_other_die_cpu15 : 1 ; /* [15] */ + u32 cpu_standbywfe_st_other_die_cpu16 : 1 ; /* [16] */ + u32 cpu_standbywfe_st_other_die_cpu17 : 1 ; /* [17] */ + u32 cpu_standbywfe_st_other_die_cpu18 : 1 ; /* [18] */ + u32 cpu_standbywfe_st_other_die_cpu19 : 1 ; /* [19] */ + u32 cpu_standbywfe_st_other_die_cpu20 : 1 ; /* [20] */ + u32 cpu_standbywfe_st_other_die_cpu21 : 1 ; /* [21] */ + u32 cpu_standbywfe_st_other_die_cpu22 : 1 ; /* [22] */ + u32 cpu_standbywfe_st_other_die_cpu23 : 1 ; /* [23] */ + u32 cpu_standbywfe_st_other_die_cpu24 : 1 ; /* [24] */ + u32 cpu_standbywfe_st_other_die_cpu25 : 1 ; /* [25] */ + u32 cpu_standbywfe_st_other_die_cpu26 : 1 ; /* [26] */ + u32 cpu_standbywfe_st_other_die_cpu27 : 1 ; /* [27] */ + u32 cpu_standbywfe_st_other_die_cpu28 : 1 ; /* [28] */ + u32 cpu_standbywfe_st_other_die_cpu29 : 1 ; /* [29] */ + u32 cpu_standbywfe_st_other_die_cpu30 : 1 ; /* [30] */ + u32 cpu_standbywfe_st_other_die_cpu31 : 1 ; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_cpu_stanbywfe_cfg_st_u; + +/* Define the union csr_sc_acg_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acg_lock : 1 ; /* [0] */ + u32 acg_glitch_result : 1 ; /* [1] */ + u32 acg_test_out_ffs : 4 ; /* [5:2] */ + u32 rsv_123 : 26 ; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_acg_st0_u; + +/* Define the union csr_sc_acg_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 acg_cpm_data : 16 ; /* [15:0] */ + u32 rsv_126 : 4 ; /* [19:16] */ + u32 acg_test_out_cpm : 4 ; /* [23:20] */ + u32 rsv_127 : 8 ; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_acg_st1_u; + +/* Define the union csr_sc_pll_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pll0_unlock_int_status : 1 ; /* [0] */ + u32 rsv_129 : 31 ; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_pll_int_status_u; + +/* Define the union csr_sc_tsensor_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tsensor_under_int_status : 1 ; /* [0] */ + u32 tsensor_over_int_status : 1 ; /* [1] */ + u32 rsv_131 : 30 ; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_tsensor_int_status_u; + +/* Define the union csr_fabric_cfg_version0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fabric_cfg_version0 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fabric_cfg_version0_u; + +/* Define the union csr_fabric_cfg_magic_word_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fabric_cfg_magic_word : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fabric_cfg_magic_word_u; + +/* Define the union csr_fabric_cfg_eco_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fabric_cfg_eco_cfg0 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fabric_cfg_eco_cfg0_u; + +/* Define the union csr_fabric_cfg_eco_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fabric_cfg_eco_cfg1 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fabric_cfg_eco_cfg1_u; + +/* Define the union csr_fabric_cfg_eco_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fabric_cfg_eco_cfg2 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fabric_cfg_eco_cfg2_u; + +/* Define the union csr_fabric_cfg_eco_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fabric_cfg_eco_cfg3 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fabric_cfg_eco_cfg3_u; + +/* Define the union csr_sc_sysctrl_lock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysctrl_lock : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_sysctrl_lock_u; + +/* Define the union csr_sc_sysctrl_unlock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysctrl_unlock : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_sysctrl_unlock_u; + +/* Define the union csr_sc_eco_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_rsv0 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_eco_rsv0_u; + +/* Define the union csr_sc_eco_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_rsv1 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_eco_rsv1_u; + +/* Define the union csr_sc_eco_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_rsv2 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_eco_rsv2_u; + +/* Define the union csr_sc_eco_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eco_rsv3 : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_eco_rsv3_u; + +/* Define the union csr_sc_eco_rsv4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prototype_clk : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_eco_rsv4_u; + +/* Define the union csr_sc_eco_rsv5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prototype_rst_n : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_sc_eco_rsv5_u; + +/* Define the union csr_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fpga_veri_num : 32 ; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +}csr_fpga_ver_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_sc_pllfctrl0_u sc_pllfctrl0 ; /* 0 */ + volatile csr_sc_pllfctrl1_u sc_pllfctrl1 ; /* 4 */ + volatile csr_sc_pll_clk_bypass0_u sc_pll_clk_bypass0 ; /* A0 */ + volatile csr_sc_switch_clk_sel_u sc_switch_clk_sel ; /* 110 */ + volatile csr_sc_pll_lp_clk_sel_u sc_pll_lp_clk_sel ; /* 160 */ + volatile csr_sc_l3d_clk_en_u sc_l3d_clk_en ; /* 330 */ + volatile csr_sc_l3d_clk_dis_u sc_l3d_clk_dis ; /* 334 */ + volatile csr_sc_hha_clk_en_u sc_hha_clk_en ; /* 350 */ + volatile csr_sc_hha_clk_dis_u sc_hha_clk_dis ; /* 354 */ + volatile csr_sc_mn_clk_en_u sc_mn_clk_en ; /* 358 */ + volatile csr_sc_mn_clk_dis_u sc_mn_clk_dis ; /* 35C */ + volatile csr_sc_l3_mbist_clk_en_u sc_l3_mbist_clk_en ; /* 680 */ + volatile csr_sc_l3_mbist_clk_dis_u sc_l3_mbist_clk_dis ; /* 684 */ + volatile csr_sc_l3d_reset_req_u sc_l3d_reset_req ; /* A20 */ + volatile csr_sc_l3d_reset_dreq_u sc_l3d_reset_dreq ; /* A24 */ + volatile csr_sc_hha_reset_req_u sc_hha_reset_req ; /* A40 */ + volatile csr_sc_hha_reset_dreq_u sc_hha_reset_dreq ; /* A44 */ + volatile csr_sc_mn_reset_req_u sc_mn_reset_req ; /* A48 */ + volatile csr_sc_mn_reset_dreq_u sc_mn_reset_dreq ; /* A4C */ + volatile csr_sc_cpm_reset_req_u sc_cpm_reset_req ; /* A50 */ + volatile csr_sc_cpm_reset_dreq_u sc_cpm_reset_dreq ; /* A54 */ + volatile csr_sc_ffs_reset_req_u sc_ffs_reset_req ; /* A58 */ + volatile csr_sc_ffs_reset_dreq_u sc_ffs_reset_dreq ; /* A5C */ + volatile csr_sc_hha_mbist_reset_req_u sc_hha_mbist_reset_req ; /* D80 */ + volatile csr_sc_hha_mbist_reset_dreq_u sc_hha_mbist_reset_dreq ; /* D84 */ + volatile csr_sc_ts_en_u sc_ts_en ; /* 2010 */ + volatile csr_sc_tsensor0_alarm_u sc_tsensor0_alarm ; /* 20C0 */ + volatile csr_sc_tsensor0_sample_num_u sc_tsensor0_sample_num ; /* 20C4 */ + volatile csr_sc_tsensor0_ctrl_u sc_tsensor0_ctrl ; /* 20D0 */ + volatile csr_sc_tsensor0_vcalib_u sc_tsensor0_vcalib ; /* 20D4 */ + volatile csr_sc_poe_smmu_enent_en_u sc_poe_smmu_enent_en ; /* 20F0 */ + volatile csr_sc_port_ctrl_ring_u sc_port_ctrl_ring ; /* 2100 */ + volatile csr_sc_acg_cfg0_u sc_acg_cfg0 ; /* 3600 */ + volatile csr_sc_acg_cfg1_u sc_acg_cfg1 ; /* 3604 */ + volatile csr_sc_acg_cfg2_u sc_acg_cfg2 ; /* 3608 */ + volatile csr_sc_acg_bypass_u sc_acg_bypass ; /* 3650 */ + volatile csr_sc_pll_src_int_u sc_pll_src_int ; /* 4000 */ + volatile csr_sc_pll_int_mask_u sc_pll_int_mask ; /* 4004 */ + volatile csr_sc_pll0_out_clk_sel_u sc_pll0_out_clk_sel ; /* 4008 */ + volatile csr_sc_tsensor0_int_u sc_tsensor0_int ; /* 4010 */ + volatile csr_sc_tsensor0_int_mask_u sc_tsensor0_int_mask ; /* 4014 */ + volatile csr_sc_cfg_power_down_l3d_u sc_cfg_power_down_l3d ; /* 4020 */ + volatile csr_sc_cpu_stanbywfe_cfg_set_u sc_cpu_stanbywfe_cfg_set ; /* 4800 */ + volatile csr_sc_cpu_stanbywfe_cfg_clr_u sc_cpu_stanbywfe_cfg_clr ; /* 4804 */ + volatile csr_sc_cpu_stanbywfe_u sc_cpu_stanbywfe ; /* 4810 */ + volatile csr_sc_cpu_stanbywfe_origin_u sc_cpu_stanbywfe_origin ; /* 4814 */ + volatile csr_sc_pll_lock_status_u sc_pll_lock_status ; /* 5000 */ + volatile csr_sc_l3d_clk_st_u sc_l3d_clk_st ; /* 5330 */ + volatile csr_sc_hha_clk_st_u sc_hha_clk_st ; /* 5350 */ + volatile csr_sc_mn_clk_st_u sc_mn_clk_st ; /* 5358 */ + volatile csr_sc_l3_mbist_clk_st_u sc_l3_mbist_clk_st ; /* 5680 */ + volatile csr_sc_l3d_reset_st_u sc_l3d_reset_st ; /* 5A20 */ + volatile csr_sc_hha_reset_st_u sc_hha_reset_st ; /* 5A40 */ + volatile csr_sc_mn_reset_st_u sc_mn_reset_st ; /* 5A48 */ + volatile csr_sc_cpm_reset_st_u sc_cpm_reset_st ; /* 5A50 */ + volatile csr_sc_ffs_reset_st_u sc_ffs_reset_st ; /* 5A58 */ + volatile csr_sc_l3_mbsit_reset_st_u sc_l3_mbsit_reset_st ; /* 5D80 */ + volatile csr_sc_tsensor0_st_u sc_tsensor0_st ; /* 60D0 */ + volatile csr_sc_tsensor0_temp_sample_average_u sc_tsensor0_temp_sample_average ; /* 60D4 */ + volatile csr_sc_cpu_stanbywfe_cfg_st_u sc_cpu_stanbywfe_cfg_st ; /* 6200 */ + volatile csr_sc_acg_st0_u sc_acg_st0 ; /* 6600 */ + volatile csr_sc_acg_st1_u sc_acg_st1 ; /* 6604 */ + volatile csr_sc_pll_int_status_u sc_pll_int_status ; /* 8000 */ + volatile csr_sc_tsensor_int_status_u sc_tsensor_int_status ; /* 8010 */ + volatile csr_fabric_cfg_version0_u fabric_cfg_version0 ; /* E0A0 */ + volatile csr_fabric_cfg_magic_word_u fabric_cfg_magic_word ; /* E0A4 */ + volatile csr_fabric_cfg_eco_cfg0_u fabric_cfg_eco_cfg0 ; /* E0A8 */ + volatile csr_fabric_cfg_eco_cfg1_u fabric_cfg_eco_cfg1 ; /* E0AC */ + volatile csr_fabric_cfg_eco_cfg2_u fabric_cfg_eco_cfg2 ; /* E0B0 */ + volatile csr_fabric_cfg_eco_cfg3_u fabric_cfg_eco_cfg3 ; /* E0B4 */ + volatile csr_sc_sysctrl_lock_u sc_sysctrl_lock ; /* F100 */ + volatile csr_sc_sysctrl_unlock_u sc_sysctrl_unlock ; /* F110 */ + volatile csr_sc_eco_rsv0_u sc_eco_rsv0 ; /* FF00 */ + volatile csr_sc_eco_rsv1_u sc_eco_rsv1 ; /* FF04 */ + volatile csr_sc_eco_rsv2_u sc_eco_rsv2 ; /* FF08 */ + volatile csr_sc_eco_rsv3_u sc_eco_rsv3 ; /* FF0C */ + volatile csr_sc_eco_rsv4_u sc_eco_rsv4 ; /* FF10 */ + volatile csr_sc_eco_rsv5_u sc_eco_rsv5 ; /* FF14 */ + volatile csr_fpga_ver_u fpga_ver ; /* FFFC */ +} S_fabric_top_cfg_REGS_TYPE; + +/* Declare the struct pointor of the module fabric_top_cfg */ +extern volatile S_fabric_top_cfg_REGS_TYPE *gopfabric_top_cfgAllReg; + +/* Declare the functions that set the member value */ +int iSetSC_PLLFCTRL0_pll0_refdiv(unsigned int upll0_refdiv); +int iSetSC_PLLFCTRL0_pll0_fbdiv(unsigned int upll0_fbdiv); +int iSetSC_PLLFCTRL0_pll0_postdiv1(unsigned int upll0_postdiv1); +int iSetSC_PLLFCTRL0_pll0_postdiv2(unsigned int upll0_postdiv2); +int iSetSC_PLLFCTRL0_pll0_bypass(unsigned int upll0_bypass); +int iSetSC_PLLFCTRL0_pll0_en(unsigned int upll0_en); +int iSetSC_PLLFCTRL0_pll0_dsmen(unsigned int upll0_dsmen); +int iSetSC_PLLFCTRL0_pll0_dacen(unsigned int upll0_dacen); +int iSetSC_PLLFCTRL0_pll0_fout4phaseen(unsigned int upll0_fout4phaseen); +int iSetSC_PLLFCTRL0_pll0_foutpostdiven(unsigned int upll0_foutpostdiven); +int iSetSC_PLLFCTRL0_pll0_foutvcoen(unsigned int upll0_foutvcoen); +int iSetSC_PLLFCTRL1_pll0_frac(unsigned int upll0_frac); +int iSetSC_PLL_CLK_BYPASS0_pll0_bypass_external_n(unsigned int upll0_bypass_external_n); +int iSetSC_SWITCH_CLK_SEL_switch_div_sel_kernel_ultrasoc(unsigned int uswitch_div_sel_kernel_ultrasoc); +int iSetSC_SWITCH_CLK_SEL_switch_div_sel_gic(unsigned int uswitch_div_sel_gic); +int iSetSC_SWITCH_CLK_SEL_switch_div_sel_poe(unsigned int uswitch_div_sel_poe); +int iSetSC_PLL_LP_CLK_SEL_lp_clk_sel(unsigned int ulp_clk_sel); +int iSetSC_L3D_CLK_EN_icg_en_l3d0(unsigned int uicg_en_l3d0); +int iSetSC_L3D_CLK_EN_icg_en_l3d1(unsigned int uicg_en_l3d1); +int iSetSC_L3D_CLK_EN_icg_en_l3d2(unsigned int uicg_en_l3d2); +int iSetSC_L3D_CLK_EN_icg_en_l3d3(unsigned int uicg_en_l3d3); +int iSetSC_L3D_CLK_DIS_icg_dis_l3d0(unsigned int uicg_dis_l3d0); +int iSetSC_L3D_CLK_DIS_icg_dis_l3d1(unsigned int uicg_dis_l3d1); +int iSetSC_L3D_CLK_DIS_icg_dis_l3d2(unsigned int uicg_dis_l3d2); +int iSetSC_L3D_CLK_DIS_icg_dis_l3d3(unsigned int uicg_dis_l3d3); +int iSetSC_HHA_CLK_EN_icg_en_hha0(unsigned int uicg_en_hha0); +int iSetSC_HHA_CLK_EN_icg_en_hha1(unsigned int uicg_en_hha1); +int iSetSC_HHA_CLK_DIS_icg_dis_hha0(unsigned int uicg_dis_hha0); +int iSetSC_HHA_CLK_DIS_icg_dis_hha1(unsigned int uicg_dis_hha1); +int iSetSC_MN_CLK_EN_icg_en_mn(unsigned int uicg_en_mn); +int iSetSC_MN_CLK_DIS_icg_dis_mn(unsigned int uicg_dis_mn); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3d0(unsigned int uicg_en_mbist_l3d0); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3d1(unsigned int uicg_en_mbist_l3d1); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3d2(unsigned int uicg_en_mbist_l3d2); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3d3(unsigned int uicg_en_mbist_l3d3); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t0(unsigned int uicg_en_mbist_l3t0); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t1(unsigned int uicg_en_mbist_l3t1); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t2(unsigned int uicg_en_mbist_l3t2); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t3(unsigned int uicg_en_mbist_l3t3); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t4(unsigned int uicg_en_mbist_l3t4); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t5(unsigned int uicg_en_mbist_l3t5); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t6(unsigned int uicg_en_mbist_l3t6); +int iSetSC_L3_MBIST_CLK_EN_icg_en_mbist_l3t7(unsigned int uicg_en_mbist_l3t7); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3d0(unsigned int uicg_dis_mbist_l3d0); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3d1(unsigned int uicg_dis_mbist_l3d1); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3d2(unsigned int uicg_dis_mbist_l3d2); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3d3(unsigned int uicg_dis_mbist_l3d3); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t0(unsigned int uicg_dis_mbist_l3t0); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t1(unsigned int uicg_dis_mbist_l3t1); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t2(unsigned int uicg_dis_mbist_l3t2); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t3(unsigned int uicg_dis_mbist_l3t3); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t4(unsigned int uicg_dis_mbist_l3t4); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t5(unsigned int uicg_dis_mbist_l3t5); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t6(unsigned int uicg_dis_mbist_l3t6); +int iSetSC_L3_MBIST_CLK_DIS_icg_dis_mbist_l3t7(unsigned int uicg_dis_mbist_l3t7); +int iSetSC_L3D_RESET_REQ_srst_req_l3d0(unsigned int usrst_req_l3d0); +int iSetSC_L3D_RESET_REQ_srst_req_l3d1(unsigned int usrst_req_l3d1); +int iSetSC_L3D_RESET_REQ_srst_req_l3d2(unsigned int usrst_req_l3d2); +int iSetSC_L3D_RESET_REQ_srst_req_l3d3(unsigned int usrst_req_l3d3); +int iSetSC_L3D_RESET_DREQ_srst_dreq_l3d0(unsigned int usrst_dreq_l3d0); +int iSetSC_L3D_RESET_DREQ_srst_dreq_l3d1(unsigned int usrst_dreq_l3d1); +int iSetSC_L3D_RESET_DREQ_srst_dreq_l3d2(unsigned int usrst_dreq_l3d2); +int iSetSC_L3D_RESET_DREQ_srst_dreq_l3d3(unsigned int usrst_dreq_l3d3); +int iSetSC_HHA_RESET_REQ_srst_req_hha0(unsigned int usrst_req_hha0); +int iSetSC_HHA_RESET_REQ_srst_req_hha1(unsigned int usrst_req_hha1); +int iSetSC_HHA_RESET_DREQ_srst_dreq_hha0(unsigned int usrst_dreq_hha0); +int iSetSC_HHA_RESET_DREQ_srst_dreq_hha1(unsigned int usrst_dreq_hha1); +int iSetSC_MN_RESET_REQ_srst_req_mn(unsigned int usrst_req_mn); +int iSetSC_MN_RESET_DREQ_srst_dreq_mn(unsigned int usrst_dreq_mn); +int iSetSC_CPM_RESET_REQ_srst_req_cpm(unsigned int usrst_req_cpm); +int iSetSC_CPM_RESET_DREQ_srst_dreq_cpm(unsigned int usrst_dreq_cpm); +int iSetSC_FFS_RESET_REQ_srst_req_ffs(unsigned int usrst_req_ffs); +int iSetSC_FFS_RESET_DREQ_srst_dreq_ffs(unsigned int usrst_dreq_ffs); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3d0(unsigned int usrst_req_mbist_l3d0); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3d1(unsigned int usrst_req_mbist_l3d1); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3d2(unsigned int usrst_req_mbist_l3d2); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3d3(unsigned int usrst_req_mbist_l3d3); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t0(unsigned int usrst_req_mbist_l3t0); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t1(unsigned int usrst_req_mbist_l3t1); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t2(unsigned int usrst_req_mbist_l3t2); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t3(unsigned int usrst_req_mbist_l3t3); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t4(unsigned int usrst_req_mbist_l3t4); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t5(unsigned int usrst_req_mbist_l3t5); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t6(unsigned int usrst_req_mbist_l3t6); +int iSetSC_HHA_MBIST_RESET_REQ_srst_req_mbist_l3t7(unsigned int usrst_req_mbist_l3t7); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3d0(unsigned int usrst_dreq_mbist_l3d0); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3d1(unsigned int usrst_dreq_mbist_l3d1); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3d2(unsigned int usrst_dreq_mbist_l3d2); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3d3(unsigned int usrst_dreq_mbist_l3d3); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t0(unsigned int usrst_dreq_mbist_l3t0); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t1(unsigned int usrst_dreq_mbist_l3t1); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t2(unsigned int usrst_dreq_mbist_l3t2); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t3(unsigned int usrst_dreq_mbist_l3t3); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t4(unsigned int usrst_dreq_mbist_l3t4); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t5(unsigned int usrst_dreq_mbist_l3t5); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t6(unsigned int usrst_dreq_mbist_l3t6); +int iSetSC_HHA_MBIST_RESET_DREQ_srst_dreq_mbist_l3t7(unsigned int usrst_dreq_mbist_l3t7); +int iSetSC_TS_EN_sc_ts_en(unsigned int usc_ts_en); +int iSetSC_TSENSOR0_ALARM_tsensor0_low(unsigned int utsensor0_low); +int iSetSC_TSENSOR0_ALARM_tsensor0_high(unsigned int utsensor0_high); +int iSetSC_TSENSOR0_SAMPLE_NUM_tsensor0_sample_shift_num(unsigned int utsensor0_sample_shift_num); +int iSetSC_TSENSOR0_CTRL_tsensor0_temp_en(unsigned int utsensor0_temp_en); +int iSetSC_TSENSOR0_CTRL_tsensor0_temp_calib(unsigned int utsensor0_temp_calib); +int iSetSC_TSENSOR0_CTRL_tsensor0_temp_ct_sel(unsigned int utsensor0_temp_ct_sel); +int iSetSC_TSENSOR0_VCALIB_tsensor0_temp_ready_sel(unsigned int utsensor0_temp_ready_sel); +int iSetSC_TSENSOR0_VCALIB_tsensor0_temp_cfg(unsigned int utsensor0_temp_cfg); +int iSetSC_POE_SMMU_ENENT_EN_sc_poe_smmu_event_en(unsigned int usc_poe_smmu_event_en); +int iSetSC_PORT_CTRL_RING_close_port_gic(unsigned int uclose_port_gic); +int iSetSC_PORT_CTRL_RING_close_port_l3dright3(unsigned int uclose_port_l3dright3); +int iSetSC_PORT_CTRL_RING_close_port_l3dright2(unsigned int uclose_port_l3dright2); +int iSetSC_PORT_CTRL_RING_close_port_l3dright1(unsigned int uclose_port_l3dright1); +int iSetSC_PORT_CTRL_RING_close_port_l3dright0(unsigned int uclose_port_l3dright0); +int iSetSC_PORT_CTRL_RING_close_port_l3dleft3(unsigned int uclose_port_l3dleft3); +int iSetSC_PORT_CTRL_RING_close_port_l3dleft2(unsigned int uclose_port_l3dleft2); +int iSetSC_PORT_CTRL_RING_close_port_l3dleft1(unsigned int uclose_port_l3dleft1); +int iSetSC_PORT_CTRL_RING_close_port_l3dleft0(unsigned int uclose_port_l3dleft0); +int iSetSC_PORT_CTRL_RING_close_port_l3t7(unsigned int uclose_port_l3t7); +int iSetSC_PORT_CTRL_RING_close_port_l3t6(unsigned int uclose_port_l3t6); +int iSetSC_PORT_CTRL_RING_close_port_l3t5(unsigned int uclose_port_l3t5); +int iSetSC_PORT_CTRL_RING_close_port_l3t4(unsigned int uclose_port_l3t4); +int iSetSC_PORT_CTRL_RING_close_port_l3t3(unsigned int uclose_port_l3t3); +int iSetSC_PORT_CTRL_RING_close_port_l3t2(unsigned int uclose_port_l3t2); +int iSetSC_PORT_CTRL_RING_close_port_l3t1(unsigned int uclose_port_l3t1); +int iSetSC_PORT_CTRL_RING_close_port_l3t0(unsigned int uclose_port_l3t0); +int iSetSC_PORT_CTRL_RING_close_port_hha3(unsigned int uclose_port_hha3); +int iSetSC_PORT_CTRL_RING_close_port_hha2(unsigned int uclose_port_hha2); +int iSetSC_PORT_CTRL_RING_close_port_hha1(unsigned int uclose_port_hha1); +int iSetSC_PORT_CTRL_RING_close_port_hha0(unsigned int uclose_port_hha0); +int iSetSC_PORT_CTRL_RING_close_port_mn(unsigned int uclose_port_mn); +int iSetSC_PORT_CTRL_RING_close_port_peri(unsigned int uclose_port_peri); +int iSetSC_PORT_CTRL_RING_close_port_poe(unsigned int uclose_port_poe); +int iSetSC_PORT_CTRL_RING_close_port_sllc3(unsigned int uclose_port_sllc3); +int iSetSC_PORT_CTRL_RING_close_port_sllc2(unsigned int uclose_port_sllc2); +int iSetSC_PORT_CTRL_RING_close_port_sllc1(unsigned int uclose_port_sllc1); +int iSetSC_PORT_CTRL_RING_close_port_sllc0(unsigned int uclose_port_sllc0); +int iSetSC_ACG_CFG0_acg_enable_sel(unsigned int uacg_enable_sel); +int iSetSC_ACG_CFG0_acg_off_mod(unsigned int uacg_off_mod); +int iSetSC_ACG_CFG0_acg_off_time_step(unsigned int uacg_off_time_step); +int iSetSC_ACG_CFG0_acg_trim(unsigned int uacg_trim); +int iSetSC_ACG_CFG0_acg_glitch_test(unsigned int uacg_glitch_test); +int iSetSC_ACG_CFG0_acg_div64_en(unsigned int uacg_div64_en); +int iSetSC_ACG_CFG0_acg_test_ffs(unsigned int uacg_test_ffs); +int iSetSC_ACG_CFG0_acg_enable_mod(unsigned int uacg_enable_mod); +int iSetSC_ACG_CFG0_acg_d_rate(unsigned int uacg_d_rate); +int iSetSC_ACG_CFG1_acg_test_cpm(unsigned int uacg_test_cpm); +int iSetSC_ACG_CFG1_acg_cpm_period(unsigned int uacg_cpm_period); +int iSetSC_ACG_CFG1_acg_edge_sel(unsigned int uacg_edge_sel); +int iSetSC_ACG_CFG1_acg_data_mod(unsigned int uacg_data_mod); +int iSetSC_ACG_CFG1_acg_data_limit_e(unsigned int uacg_data_limit_e); +int iSetSC_ACG_CFG1_acg_cpm_threshold_r(unsigned int uacg_cpm_threshold_r); +int iSetSC_ACG_CFG1_acg_threshold_f(unsigned int uacg_threshold_f); +int iSetSC_ACG_CFG1_acg_pulse_width_sel(unsigned int uacg_pulse_width_sel); +int iSetSC_ACG_CFG2_acg_svt_sl(unsigned int uacg_svt_sl); +int iSetSC_ACG_CFG2_acg_svt_ll(unsigned int uacg_svt_ll); +int iSetSC_ACG_CFG2_acg_lvt_sl(unsigned int uacg_lvt_sl); +int iSetSC_ACG_CFG2_acg_lvt_ll(unsigned int uacg_lvt_ll); +int iSetSC_ACG_BYPASS_acg_bypass(unsigned int uacg_bypass); +int iSetSC_PLL_SRC_INT_pll0_unlock(unsigned int upll0_unlock); +int iSetSC_PLL_INT_MASK_pll0_unlock_int_mask(unsigned int upll0_unlock_int_mask); +int iSetSC_PLL0_OUT_CLK_SEL_pll_out_clk_sel(unsigned int upll_out_clk_sel); +int iSetSC_TSENSOR0_INT_tsensor0_under(unsigned int utsensor0_under); +int iSetSC_TSENSOR0_INT_tsensor0_over(unsigned int utsensor0_over); +int iSetSC_TSENSOR0_INT_MASK_tsensor0_under_int_mask(unsigned int utsensor0_under_int_mask); +int iSetSC_TSENSOR0_INT_MASK_tsensor0_over_int_mask(unsigned int utsensor0_over_int_mask); +int iSetSC_CFG_POWER_DOWN_L3D_cfg_power_down_l3d0(unsigned int ucfg_power_down_l3d0); +int iSetSC_CFG_POWER_DOWN_L3D_cfg_power_down_l3d1(unsigned int ucfg_power_down_l3d1); +int iSetSC_CFG_POWER_DOWN_L3D_cfg_power_down_l3d2(unsigned int ucfg_power_down_l3d2); +int iSetSC_CFG_POWER_DOWN_L3D_cfg_power_down_l3d3(unsigned int ucfg_power_down_l3d3); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu0(unsigned int ucpu_standbywfe_other_die_cpu0); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu1(unsigned int ucpu_standbywfe_other_die_cpu1); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu2(unsigned int ucpu_standbywfe_other_die_cpu2); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu3(unsigned int ucpu_standbywfe_other_die_cpu3); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu4(unsigned int ucpu_standbywfe_other_die_cpu4); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu5(unsigned int ucpu_standbywfe_other_die_cpu5); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu6(unsigned int ucpu_standbywfe_other_die_cpu6); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu7(unsigned int ucpu_standbywfe_other_die_cpu7); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu8(unsigned int ucpu_standbywfe_other_die_cpu8); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu9(unsigned int ucpu_standbywfe_other_die_cpu9); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu10(unsigned int ucpu_standbywfe_other_die_cpu10); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu11(unsigned int ucpu_standbywfe_other_die_cpu11); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu12(unsigned int ucpu_standbywfe_other_die_cpu12); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu13(unsigned int ucpu_standbywfe_other_die_cpu13); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu14(unsigned int ucpu_standbywfe_other_die_cpu14); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu15(unsigned int ucpu_standbywfe_other_die_cpu15); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu16(unsigned int ucpu_standbywfe_other_die_cpu16); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu17(unsigned int ucpu_standbywfe_other_die_cpu17); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu18(unsigned int ucpu_standbywfe_other_die_cpu18); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu19(unsigned int ucpu_standbywfe_other_die_cpu19); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu20(unsigned int ucpu_standbywfe_other_die_cpu20); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu21(unsigned int ucpu_standbywfe_other_die_cpu21); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu22(unsigned int ucpu_standbywfe_other_die_cpu22); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu23(unsigned int ucpu_standbywfe_other_die_cpu23); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu24(unsigned int ucpu_standbywfe_other_die_cpu24); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu25(unsigned int ucpu_standbywfe_other_die_cpu25); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu26(unsigned int ucpu_standbywfe_other_die_cpu26); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu27(unsigned int ucpu_standbywfe_other_die_cpu27); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu28(unsigned int ucpu_standbywfe_other_die_cpu28); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu29(unsigned int ucpu_standbywfe_other_die_cpu29); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu30(unsigned int ucpu_standbywfe_other_die_cpu30); +int iSetSC_CPU_STANBYWFE_CFG_SET_cpu_standbywfe_other_die_cpu31(unsigned int ucpu_standbywfe_other_die_cpu31); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu0(unsigned int ucpu_not_standbywfe_other_die_cpu0); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu1(unsigned int ucpu_not_standbywfe_other_die_cpu1); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu2(unsigned int ucpu_not_standbywfe_other_die_cpu2); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu3(unsigned int ucpu_not_standbywfe_other_die_cpu3); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu4(unsigned int ucpu_not_standbywfe_other_die_cpu4); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu5(unsigned int ucpu_not_standbywfe_other_die_cpu5); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu6(unsigned int ucpu_not_standbywfe_other_die_cpu6); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu7(unsigned int ucpu_not_standbywfe_other_die_cpu7); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu8(unsigned int ucpu_not_standbywfe_other_die_cpu8); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu9(unsigned int ucpu_not_standbywfe_other_die_cpu9); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu10(unsigned int ucpu_not_standbywfe_other_die_cpu10); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu11(unsigned int ucpu_not_standbywfe_other_die_cpu11); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu12(unsigned int ucpu_not_standbywfe_other_die_cpu12); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu13(unsigned int ucpu_not_standbywfe_other_die_cpu13); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu14(unsigned int ucpu_not_standbywfe_other_die_cpu14); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu15(unsigned int ucpu_not_standbywfe_other_die_cpu15); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu16(unsigned int ucpu_not_standbywfe_other_die_cpu16); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu17(unsigned int ucpu_not_standbywfe_other_die_cpu17); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu18(unsigned int ucpu_not_standbywfe_other_die_cpu18); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu19(unsigned int ucpu_not_standbywfe_other_die_cpu19); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu20(unsigned int ucpu_not_standbywfe_other_die_cpu20); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu21(unsigned int ucpu_not_standbywfe_other_die_cpu21); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu22(unsigned int ucpu_not_standbywfe_other_die_cpu22); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu23(unsigned int ucpu_not_standbywfe_other_die_cpu23); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu24(unsigned int ucpu_not_standbywfe_other_die_cpu24); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu25(unsigned int ucpu_not_standbywfe_other_die_cpu25); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu26(unsigned int ucpu_not_standbywfe_other_die_cpu26); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu27(unsigned int ucpu_not_standbywfe_other_die_cpu27); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu28(unsigned int ucpu_not_standbywfe_other_die_cpu28); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu29(unsigned int ucpu_not_standbywfe_other_die_cpu29); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu30(unsigned int ucpu_not_standbywfe_other_die_cpu30); +int iSetSC_CPU_STANBYWFE_CFG_CLR_cpu_not_standbywfe_other_die_cpu31(unsigned int ucpu_not_standbywfe_other_die_cpu31); +int iSetSC_CPU_STANBYWFE_sc_cpu_standwfe(unsigned int usc_cpu_standwfe); +int iSetSC_CPU_STANBYWFE_ORIGIN_sc_cpu_standwfe_origin(unsigned int usc_cpu_standwfe_origin); +int iSetSC_PLL_LOCK_STATUS_pll0_lock(unsigned int upll0_lock); +int iSetSC_L3D_CLK_ST_icg_st_l3d0(unsigned int uicg_st_l3d0); +int iSetSC_L3D_CLK_ST_icg_st_l3d1(unsigned int uicg_st_l3d1); +int iSetSC_L3D_CLK_ST_icg_st_l3d2(unsigned int uicg_st_l3d2); +int iSetSC_L3D_CLK_ST_icg_st_l3d3(unsigned int uicg_st_l3d3); +int iSetSC_HHA_CLK_ST_icg_st_hha0(unsigned int uicg_st_hha0); +int iSetSC_HHA_CLK_ST_icg_st_hha1(unsigned int uicg_st_hha1); +int iSetSC_MN_CLK_ST_icg_st_mn(unsigned int uicg_st_mn); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3d0(unsigned int uicg_st_mbist_l3d0); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3d1(unsigned int uicg_st_mbist_l3d1); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3d2(unsigned int uicg_st_mbist_l3d2); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3d3(unsigned int uicg_st_mbist_l3d3); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t0(unsigned int uicg_st_mbist_l3t0); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t1(unsigned int uicg_st_mbist_l3t1); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t2(unsigned int uicg_st_mbist_l3t2); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t3(unsigned int uicg_st_mbist_l3t3); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t4(unsigned int uicg_st_mbist_l3t4); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t5(unsigned int uicg_st_mbist_l3t5); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3dt6(unsigned int uicg_st_mbist_l3dt6); +int iSetSC_L3_MBIST_CLK_ST_icg_st_mbist_l3t7(unsigned int uicg_st_mbist_l3t7); +int iSetSC_L3D_RESET_ST_l3d0_srst_st(unsigned int ul3d0_srst_st); +int iSetSC_L3D_RESET_ST_l3d1_srst_st(unsigned int ul3d1_srst_st); +int iSetSC_L3D_RESET_ST_l3d2_srst_st(unsigned int ul3d2_srst_st); +int iSetSC_L3D_RESET_ST_l3d3_srst_st(unsigned int ul3d3_srst_st); +int iSetSC_HHA_RESET_ST_hha0_srst_st(unsigned int uhha0_srst_st); +int iSetSC_HHA_RESET_ST_hha1_srst_st(unsigned int uhha1_srst_st); +int iSetSC_MN_RESET_ST_mn_srst_st(unsigned int umn_srst_st); +int iSetSC_CPM_RESET_ST_cpm_srst_st(unsigned int ucpm_srst_st); +int iSetSC_FFS_RESET_ST_ffs_srst_st(unsigned int uffs_srst_st); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3d0(unsigned int usrst_st_mbist_l3d0); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3d1(unsigned int usrst_st_mbist_l3d1); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3d2(unsigned int usrst_st_mbist_l3d2); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3d3(unsigned int usrst_st_mbist_l3d3); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t0(unsigned int usrst_st_mbist_l3t0); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t1(unsigned int usrst_st_mbist_l3t1); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t2(unsigned int usrst_st_mbist_l3t2); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t3(unsigned int usrst_st_mbist_l3t3); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t4(unsigned int usrst_st_mbist_l3t4); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t5(unsigned int usrst_st_mbist_l3t5); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3dt6(unsigned int usrst_st_mbist_l3dt6); +int iSetSC_L3_MBSIT_RESET_ST_srst_st_mbist_l3t7(unsigned int usrst_st_mbist_l3t7); +int iSetSC_TSENSOR0_ST_tsensor0_temp_out(unsigned int utsensor0_temp_out); +int iSetSC_TSENSOR0_ST_tsensor0_temp_ready(unsigned int utsensor0_temp_ready); +int iSetSC_TSENSOR0_TEMP_SAMPLE_AVERAGE_tsensor0_sample(unsigned int utsensor0_sample); +int iSetSC_TSENSOR0_TEMP_SAMPLE_AVERAGE_tsensor0_valid(unsigned int utsensor0_valid); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu0(unsigned int ucpu_standbywfe_st_other_die_cpu0); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu1(unsigned int ucpu_standbywfe_st_other_die_cpu1); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu2(unsigned int ucpu_standbywfe_st_other_die_cpu2); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu3(unsigned int ucpu_standbywfe_st_other_die_cpu3); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu4(unsigned int ucpu_standbywfe_st_other_die_cpu4); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu5(unsigned int ucpu_standbywfe_st_other_die_cpu5); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu6(unsigned int ucpu_standbywfe_st_other_die_cpu6); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu7(unsigned int ucpu_standbywfe_st_other_die_cpu7); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu8(unsigned int ucpu_standbywfe_st_other_die_cpu8); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu9(unsigned int ucpu_standbywfe_st_other_die_cpu9); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu10(unsigned int ucpu_standbywfe_st_other_die_cpu10); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu11(unsigned int ucpu_standbywfe_st_other_die_cpu11); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu12(unsigned int ucpu_standbywfe_st_other_die_cpu12); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu13(unsigned int ucpu_standbywfe_st_other_die_cpu13); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu14(unsigned int ucpu_standbywfe_st_other_die_cpu14); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu15(unsigned int ucpu_standbywfe_st_other_die_cpu15); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu16(unsigned int ucpu_standbywfe_st_other_die_cpu16); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu17(unsigned int ucpu_standbywfe_st_other_die_cpu17); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu18(unsigned int ucpu_standbywfe_st_other_die_cpu18); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu19(unsigned int ucpu_standbywfe_st_other_die_cpu19); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu20(unsigned int ucpu_standbywfe_st_other_die_cpu20); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu21(unsigned int ucpu_standbywfe_st_other_die_cpu21); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu22(unsigned int ucpu_standbywfe_st_other_die_cpu22); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu23(unsigned int ucpu_standbywfe_st_other_die_cpu23); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu24(unsigned int ucpu_standbywfe_st_other_die_cpu24); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu25(unsigned int ucpu_standbywfe_st_other_die_cpu25); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu26(unsigned int ucpu_standbywfe_st_other_die_cpu26); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu27(unsigned int ucpu_standbywfe_st_other_die_cpu27); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu28(unsigned int ucpu_standbywfe_st_other_die_cpu28); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu29(unsigned int ucpu_standbywfe_st_other_die_cpu29); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu30(unsigned int ucpu_standbywfe_st_other_die_cpu30); +int iSetSC_CPU_STANBYWFE_CFG_ST_cpu_standbywfe_st_other_die_cpu31(unsigned int ucpu_standbywfe_st_other_die_cpu31); +int iSetSC_ACG_ST0_acg_lock(unsigned int uacg_lock); +int iSetSC_ACG_ST0_acg_glitch_result(unsigned int uacg_glitch_result); +int iSetSC_ACG_ST0_acg_test_out_ffs(unsigned int uacg_test_out_ffs); +int iSetSC_ACG_ST1_acg_cpm_data(unsigned int uacg_cpm_data); +int iSetSC_ACG_ST1_acg_test_out_cpm(unsigned int uacg_test_out_cpm); +int iSetSC_PLL_INT_STATUS_pll0_unlock_int_status(unsigned int upll0_unlock_int_status); +int iSetSC_TSENSOR_INT_STATUS_tsensor_under_int_status(unsigned int utsensor_under_int_status); +int iSetSC_TSENSOR_INT_STATUS_tsensor_over_int_status(unsigned int utsensor_over_int_status); +int iSetFABRIC_CFG_VERSION0_fabric_cfg_version0(unsigned int ufabric_cfg_version0); +int iSetFABRIC_CFG_MAGIC_WORD_fabric_cfg_magic_word(unsigned int ufabric_cfg_magic_word); +int iSetFABRIC_CFG_ECO_CFG0_fabric_cfg_eco_cfg0(unsigned int ufabric_cfg_eco_cfg0); +int iSetFABRIC_CFG_ECO_CFG1_fabric_cfg_eco_cfg1(unsigned int ufabric_cfg_eco_cfg1); +int iSetFABRIC_CFG_ECO_CFG2_fabric_cfg_eco_cfg2(unsigned int ufabric_cfg_eco_cfg2); +int iSetFABRIC_CFG_ECO_CFG3_fabric_cfg_eco_cfg3(unsigned int ufabric_cfg_eco_cfg3); +int iSetSC_SYSCTRL_LOCK_sysctrl_lock(unsigned int usysctrl_lock); +int iSetSC_SYSCTRL_UNLOCK_sysctrl_unlock(unsigned int usysctrl_unlock); +int iSetSC_ECO_RSV0_eco_rsv0(unsigned int ueco_rsv0); +int iSetSC_ECO_RSV1_eco_rsv1(unsigned int ueco_rsv1); +int iSetSC_ECO_RSV2_eco_rsv2(unsigned int ueco_rsv2); +int iSetSC_ECO_RSV3_eco_rsv3(unsigned int ueco_rsv3); +int iSetSC_ECO_RSV4_prototype_clk(unsigned int uprototype_clk); +int iSetSC_ECO_RSV5_prototype_rst_n(unsigned int uprototype_rst_n); +int iSetFPGA_VER_fpga_veri_num(unsigned int ufpga_veri_num); + +#endif // __HI1823E_C_UNION_DEFINE_H__ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/fabric_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/fabric_reg_offset.h new file mode 100644 index 000000000..31a9ca0ac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/fabric_reg_offset.h @@ -0,0 +1,102 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : hi1823e_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/21 14:21:49 Create file +// ****************************************************************************** + +#ifndef __FABRIC_REG_OFFSET_H__ +#define __FABRIC_REG_OFFSET_H__ + +/* FABRIC_TOP_CFG Base address of Module's Register */ +#define CSR_FABRIC_TOP_CFG_BASE (0x90340000ULL) + +/******************************************************************************/ +/* FABRIC_TOP_CFG Registers' Definitions */ +/******************************************************************************/ + +#define CSR_FABRIC_TOP_CFG_SC_PLLFCTRL0_REG (CSR_FABRIC_TOP_CFG_BASE + 0x0) /* SC_PLLFCTRL0为CDIE_CRG的PLL0控制寄存器0。 */ +#define CSR_FABRIC_TOP_CFG_SC_PLLFCTRL1_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4) /* SC_PLLFCTRL1为CDIE_CRG的PLL0控制寄存器1。 */ +#define CSR_FABRIC_TOP_CFG_SC_PLL_CLK_BYPASS0_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA0) /* SC_PLL_CLK_BYPASS0为CDIE_CRG的PLL相关工作时钟选择。 */ +#define CSR_FABRIC_TOP_CFG_SC_SWITCH_CLK_SEL_REG (CSR_FABRIC_TOP_CFG_BASE + 0x110) /* 总线时钟的分频选择寄存器。三个寄存器必须配置成一样的分频系数 */ +#define CSR_FABRIC_TOP_CFG_SC_PLL_LP_CLK_SEL_REG (CSR_FABRIC_TOP_CFG_BASE + 0x160) /* 快速切频选择 */ +#define CSR_FABRIC_TOP_CFG_SC_L3D_CLK_EN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x330) /* SC_L3D_CLK_EN为L3D的时钟使能寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_L3D_CLK_DIS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x334) /* SC_L3D_CLK_DIS为L3D的时钟禁止寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_CLK_EN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x350) /* SC_HHA_CLK_EN表示HHA逻辑时钟使能配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_CLK_DIS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x354) /* SC_HHA_CLK_DIS表示HHA逻辑时钟禁止使能配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_MN_CLK_EN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x358) /* SC_MN_CLK_EN表示MN逻辑时钟使能配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_MN_CLK_DIS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x35C) /* SC_MN_CLK_DIS表示MN逻辑时钟禁止使能配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_L3_MBIST_CLK_EN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x680) /* L3 mbsit时钟使能寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_L3_MBIST_CLK_DIS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x684) /* L3 mbsit时钟禁止寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_L3D_RESET_REQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA20) /* SC_L3D_RESET_REQ为CDIE内L3D软复位请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_L3D_RESET_DREQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA24) /* SC_L3D_RESET_DREQ为CDIE内L3D软复位去请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_RESET_REQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA40) /* SC_HHA_RESET_REQ为HHA软复位请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_RESET_DREQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA44) /* SC_HHA_RESET_DREQ为HHA软复位去请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_MN_RESET_REQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA48) /* SC_MN_RESET_REQ为MN软复位请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_MN_RESET_DREQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA4C) /* SC_MN_RESET_DREQ为MN软复位去请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_CPM_RESET_REQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA50) /* SC_CPM_RESET_REQ为CPM软复位请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_CPM_RESET_DREQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA54) /* SC_CPM_RESET_DREQ为CPM软复位去请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_FFS_RESET_REQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA58) /* SC_FFS_RESET_REQ为ACG FFS软复位请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_FFS_RESET_DREQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xA5C) /* SC_FFS_RESET_DREQ为ACG软复位去请求控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_MBIST_RESET_REQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xD80) /* SC_HHA_MBIST_SRST_REQ表示逻辑复位请求寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_MBIST_RESET_DREQ_REG (CSR_FABRIC_TOP_CFG_BASE + 0xD84) /* SC_HHA_MBISST_SRST_DREQ表示逻辑复位去请求寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_TS_EN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x2010) /* TSVACLEB技术使能配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_ALARM_REG (CSR_FABRIC_TOP_CFG_BASE + 0x20C0) /* 片上温度传感器温度门限配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_SAMPLE_NUM_REG (CSR_FABRIC_TOP_CFG_BASE + 0x20C4) /* 硬件连读Tsensor温度值后取平均的配置寄存器（禁止配置为0x0和0x1） */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_CTRL_REG (CSR_FABRIC_TOP_CFG_BASE + 0x20D0) /* 片上温度传感器Tsensor0工作参数配置。 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_VCALIB_REG (CSR_FABRIC_TOP_CFG_BASE + 0x20D4) /* Tsensor0配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_POE_SMMU_ENENT_EN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x20F0) /* POE SMMU EVENT使能寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_PORT_CTRL_RING_REG (CSR_FABRIC_TOP_CFG_BASE + 0x2100) /* RING PORT CTRL控制寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_ACG_CFG0_REG (CSR_FABRIC_TOP_CFG_BASE + 0x3600) /* ACG中ACG的配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_ACG_CFG1_REG (CSR_FABRIC_TOP_CFG_BASE + 0x3604) /* ACG中CPM的配置寄存器0 */ +#define CSR_FABRIC_TOP_CFG_SC_ACG_CFG2_REG (CSR_FABRIC_TOP_CFG_BASE + 0x3608) /* ACG中CPM的配置寄存器1 */ +#define CSR_FABRIC_TOP_CFG_SC_ACG_BYPASS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x3650) +#define CSR_FABRIC_TOP_CFG_SC_PLL_SRC_INT_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4000) /* PLL中断源寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_PLL_INT_MASK_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4004) /* PLL中断屏蔽寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_PLL0_OUT_CLK_SEL_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4008) /* PLL0输出时钟选择寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_INT_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4010) /* TSENSOR中断源寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_INT_MASK_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4014) /* TSENSOR中断屏蔽寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_CFG_POWER_DOWN_L3D_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4020) /* L3D POWER CFG配置寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_CPU_STANBYWFE_CFG_SET_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4800) /* 另外一个CPU DIE的STANDBYWFE状态配置置位 */ +#define CSR_FABRIC_TOP_CFG_SC_CPU_STANBYWFE_CFG_CLR_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4804) /* 另外一个CPU DIE的STANDBYWFE状态配置清零 */ +#define CSR_FABRIC_TOP_CFG_SC_CPU_STANBYWFE_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4810) /* CPU_STANDWFE状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_CPU_STANBYWFE_ORIGIN_REG (CSR_FABRIC_TOP_CFG_BASE + 0x4814) /* CPU_STANDWFE原始状态寄存器，未经过Partial Good逻辑(DFX寄存器) */ +#define CSR_FABRIC_TOP_CFG_SC_PLL_LOCK_STATUS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5000) /* PLL锁定状态寄存器。 */ +#define CSR_FABRIC_TOP_CFG_SC_L3D_CLK_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5330) /* SC_L3D_CLK_ST为L3D的时钟状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_CLK_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5350) /* SC_HHA_CLK_ST表示HHA逻辑时钟状态 */ +#define CSR_FABRIC_TOP_CFG_SC_MN_CLK_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5358) /* SC_MN_CLK_ST表示MN逻辑时钟状态 */ +#define CSR_FABRIC_TOP_CFG_SC_L3_MBIST_CLK_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5680) /* SC_L3_MBIST_CLK_ST表示DCIP的时钟状态。（Hi1620s禁止使用） */ +#define CSR_FABRIC_TOP_CFG_SC_L3D_RESET_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5A20) /* SC_L3D_RESET_ST为CDIE内L3D软复位状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_HHA_RESET_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5A40) /* SC_HHA_SRST_ST表示HHA逻辑复位状态 */ +#define CSR_FABRIC_TOP_CFG_SC_MN_RESET_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5A48) /* SC_MN_SRST_ST表示MN逻辑复位状态 */ +#define CSR_FABRIC_TOP_CFG_SC_CPM_RESET_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5A50) /* SC_CPM_SRST_ST表示CPM逻辑复位状态 */ +#define CSR_FABRIC_TOP_CFG_SC_FFS_RESET_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5A58) /* SC_FFS_SRST_ST表示ACG逻辑复位状态 */ +#define CSR_FABRIC_TOP_CFG_SC_L3_MBSIT_RESET_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x5D80) /* SC_L3_MBSIT_RESET_ST表示相关逻辑复位状态 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x60D0) /* tsensor系统状态寄存器。 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR0_TEMP_SAMPLE_AVERAGE_REG (CSR_FABRIC_TOP_CFG_BASE + 0x60D4) /* 芯片温度采样值 */ +#define CSR_FABRIC_TOP_CFG_SC_CPU_STANBYWFE_CFG_ST_REG (CSR_FABRIC_TOP_CFG_BASE + 0x6200) /* 另外一个CPU DIE的STANDBYWFE状态查询 */ +#define CSR_FABRIC_TOP_CFG_SC_ACG_ST0_REG (CSR_FABRIC_TOP_CFG_BASE + 0x6600) /* ACG状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_ACG_ST1_REG (CSR_FABRIC_TOP_CFG_BASE + 0x6604) /* ACG中CPM的状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_PLL_INT_STATUS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x8000) /* PLL中断状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_SC_TSENSOR_INT_STATUS_REG (CSR_FABRIC_TOP_CFG_BASE + 0x8010) /* TSENSOR中断状态寄存器 */ +#define CSR_FABRIC_TOP_CFG_FABRIC_CFG_VERSION0_REG (CSR_FABRIC_TOP_CFG_BASE + 0xE0A0) /* VERSION寄存器0 */ +#define CSR_FABRIC_TOP_CFG_FABRIC_CFG_MAGIC_WORD_REG (CSR_FABRIC_TOP_CFG_BASE + 0xE0A4) /* FABRIC_CFG 版本号锁定寄存器 */ +#define CSR_FABRIC_TOP_CFG_FABRIC_CFG_ECO_CFG0_REG (CSR_FABRIC_TOP_CFG_BASE + 0xE0A8) /* 用于ECO的冗余配置寄存器1 */ +#define CSR_FABRIC_TOP_CFG_FABRIC_CFG_ECO_CFG1_REG (CSR_FABRIC_TOP_CFG_BASE + 0xE0AC) /* 用于ECO的冗余配置寄存器1 */ +#define CSR_FABRIC_TOP_CFG_FABRIC_CFG_ECO_CFG2_REG (CSR_FABRIC_TOP_CFG_BASE + 0xE0B0) /* 用于ECO的冗余配置寄存器2 */ +#define CSR_FABRIC_TOP_CFG_FABRIC_CFG_ECO_CFG3_REG (CSR_FABRIC_TOP_CFG_BASE + 0xE0B4) /* 用于ECO的冗余配置寄存器3 */ +#define CSR_FABRIC_TOP_CFG_SC_SYSCTRL_LOCK_REG (CSR_FABRIC_TOP_CFG_BASE + 0xF100) /* 系统控制器锁定寄存器。（注意：1，此寄存器空间必须是安全访问才能成功） */ +#define CSR_FABRIC_TOP_CFG_SC_SYSCTRL_UNLOCK_REG (CSR_FABRIC_TOP_CFG_BASE + 0xF110) /* 系统控制器解锁寄存器。（注意：1，此寄存器空间必须是安全访问才能成功） */ +#define CSR_FABRIC_TOP_CFG_SC_ECO_RSV0_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFF00) /* ECO 寄存器0 */ +#define CSR_FABRIC_TOP_CFG_SC_ECO_RSV1_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFF04) /* ECO 寄存器1 */ +#define CSR_FABRIC_TOP_CFG_SC_ECO_RSV2_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFF08) /* ECO 寄存器2 */ +#define CSR_FABRIC_TOP_CFG_SC_ECO_RSV3_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFF0C) /* ECO 寄存器3 */ +#define CSR_FABRIC_TOP_CFG_SC_ECO_RSV4_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFF10) /* ECO 寄存器4 */ +#define CSR_FABRIC_TOP_CFG_SC_ECO_RSV5_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFF14) /* ECO 寄存器5 */ +#define CSR_FABRIC_TOP_CFG_FPGA_VER_REG (CSR_FABRIC_TOP_CFG_BASE + 0xFFFC) /* FPGA版本寄存器 */ + +#endif // __HI1823E_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hha_c_union_def.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hha_c_union_def.h new file mode 100644 index 000000000..3da5b1662 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hha_c_union_def.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * File name : hha_c_union_def.h + * Description : hha 相关寄存器结构体定义 + * History : 2023/05/04 11:05:46 Create file + */ + +#ifndef HHA_C_UNION_DEFINE_H +#define HHA_C_UNION_DEFINE_H + +/* HHA Register Field Segment Union definitions */ +typedef union { + struct { + u32 ddr_intlv_baseaddr : 20; // [19..0] + u32 ddr_intlv_size : 4; // [23..20] + u32 ddr_intlv_ch : 3; // [26..24] + u32 ddr_intlv_die : 1; // [27] + u32 ddr_nonintlv_die_tgt : 1; // [28] + u32 ddr_intlv_skt : 2; // [30..29] + u32 msd_en : 1; // [31] + } bits; + u32 value; +} csr_hha_msdx_ctrl_u; + +typedef union { + struct { + u32 totem_a_remap0 : 2; // [1..0] + u32 totem_a_remap1 : 2; // [3..2] + u32 totem_a_remap2 : 2; // [5..4] + u32 totem_a_remap3 : 2; // [7..6] + u32 totem_a_remap4 : 2; // [9..8] + u32 totem_a_remap5 : 2; // [11..10] + u32 totem_b_remap0 : 2; // [13..12] + u32 totem_b_remap1 : 2; // [15..14] + u32 totem_b_remap2 : 2; // [17..16] + u32 totem_b_remap3 : 2; // [19..18] + u32 totem_b_remap4 : 2; // [21..20] + u32 totem_b_remap5 : 2; // [22..23] + u32 skt_remap0 : 2; // [25..24] + u32 skt_remap1 : 2; // [27..26] + u32 skt_remap2 : 2; // [29..28] + u32 skt_remap3 : 2; // [31..30] + } bits; + u32 value; +} csr_hha_msdx_map_u; + +typedef union { + struct { + u32 dmc_intlv_addr_set_sel : 3; // [2..0] + u32 dmc_intlv_addr_set_sel_xor : 1; // [3] + u32 hha_intlv_addr_set_sel : 3; // [6..4] + u32 hha_intlv_addr_set_sel_xor : 1; // [7] + u32 die_intlv_addr_set_sel : 3; // [10..8] + u32 die_intlv_addr_set_sel_xor : 1; // [11] + u32 skt_intlv_addr_set_sel : 3; // [14:12] + u32 skt_intlv_addr_set_sel_xor : 1; // [15] + u32 Reserved_0 : 16; // [31..16] + } bits; + u32 value; +} csr_hha_ddrintlv_addr_u; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_c_union_define.h new file mode 100644 index 000000000..0b933668d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_c_union_define.h @@ -0,0 +1,1287 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hva_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : HVA +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// ****************************************************************************** + +#ifndef HVA_C_UNION_DEFINE_H +#define HVA_C_UNION_DEFINE_H + +/* Define the union csr_hva_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_fpga_ver_u; + +/* Define the union csr_hva_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_emu_ver_u; + +/* Define the union csr_hva_mem_attr_win0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win0_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win0_l_u; + +/* Define the union csr_hva_mem_attr_win0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win0_h : 4; /* [3:0] */ + u32 rsv_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win0_h_u; + +/* Define the union csr_hva_mem_attr_win1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win1_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win1_l_u; + +/* Define the union csr_hva_mem_attr_win1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win1_h : 4; /* [3:0] */ + u32 rsv_1 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win1_h_u; + +/* Define the union csr_hva_mem_attr_win2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win2_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win2_l_u; + +/* Define the union csr_hva_mem_attr_win2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win2_h : 4; /* [3:0] */ + u32 rsv_2 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win2_h_u; + +/* Define the union csr_hva_mem_attr_win3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win3_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win3_l_u; + +/* Define the union csr_hva_mem_attr_win3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_win3_h : 4; /* [3:0] */ + u32 rsv_3 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_win3_h_u; + +/* Define the union csr_hva_mem_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_mem_attr_rd : 5; /* [4:0] */ + u32 rsv_4 : 3; /* [7:5] */ + u32 hva_mem_attr_wr : 5; /* [12:8] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_mem_attr_u; + +/* Define the union csr_hva_ar_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_arqos_set : 4; /* [3:0] */ + u32 cfg_arssv_set : 1; /* [4] */ + u32 cfg_arstrmid_mode : 1; /* [5] */ + u32 rsv_6 : 2; /* [7:6] */ + u32 cfg_rdcln_thrld : 4; /* [11:8] */ + u32 cfg_rdfna_thrld : 4; /* [15:12] */ + u32 cfg_rdtype_thrld : 4; /* [19:16] */ + u32 cfg_rdfa_thrld : 4; /* [23:20] */ + u32 cfg_rd_fa_mode : 2; /* [25:24] */ + u32 cfg_rd_fna_mode : 2; /* [27:26] */ + u32 cfg_rd_cln_mode : 1; /* [28] */ + u32 cfg_rd_type_mode : 1; /* [29] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_ar_cfg_u; + +/* Define the union csr_hva_wr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_awqos_set : 4; /* [3:0] */ + u32 cfg_awssv_set : 1; /* [4] */ + u32 cfg_awstrmid_mode : 1; /* [5] */ + u32 rsv_8 : 2; /* [7:6] */ + u32 cfg_wr_so_set : 4; /* [11:8] */ + u32 cfg_wrfna_thrld : 4; /* [15:12] */ + u32 cfg_wrtype_thrld : 4; /* [19:16] */ + u32 cfg_wrfa_thrld : 4; /* [23:20] */ + u32 cfg_wr_fa_mode : 2; /* [25:24] */ + u32 cfg_wr_fna_mode : 2; /* [27:26] */ + u32 cfg_wr_fp_mode : 2; /* [29:28] */ + u32 cfg_wr_type_mode : 1; /* [30] */ + u32 cfg_wr_so_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_wr_cfg_u; + +/* Define the union csr_hva_arstrmid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_rd_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_arstrmid_u; + +/* Define the union csr_hva_awstrmid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_wr_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_awstrmid_u; + +/* Define the union csr_hva_peh_enum_bar0_wr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_enum_bar0_wr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_enum_bar0_wr_mask_u; + +/* Define the union csr_hva_peh_enum_bar1_wr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_enum_bar1_wr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_enum_bar1_wr_mask_u; + +/* Define the union csr_hva_peh_enum_bar2_wr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_enum_bar2_wr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_enum_bar2_wr_mask_u; + +/* Define the union csr_hva_peh_enum_bar3_wr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_enum_bar3_wr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_enum_bar3_wr_mask_u; + +/* Define the union csr_hva_peh_enum_bar4_wr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_enum_bar4_wr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_enum_bar4_wr_mask_u; + +/* Define the union csr_hva_peh_enum_bar5_wr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_enum_bar5_wr_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_enum_bar5_wr_mask_u; + +/* Define the union csr_hva_peh_feature_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_peh_feature_en : 16; /* [15:0] */ + u32 hva_flr_done : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_peh_feature_en_u; + +/* Define the union csr_hva_pf_cmd_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_pf_cmd_type : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_pf_cmd_type_u; + +/* Define the union csr_hva_int_starus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_ov_int_status : 1; /* [0] */ + u32 hva_npq_uf_int_status : 1; /* [1] */ + u32 hva_npq_send_empty_int_status : 1; /* [2] */ + u32 hva_pq_ov_int_status : 1; /* [3] */ + u32 hva_pq_uf_int_status : 1; /* [4] */ + u32 hva_pq_send_empty_int_status : 1; /* [5] */ + u32 hva_1bit_ecc_int_status : 1; /* [6] */ + u32 hva_2bit_ecc_int_status : 1; /* [7] */ + u32 hva_flr_int_status : 1; /* [8] */ + u32 rsv_10 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_int_starus_u; + +/* Define the union csr_hva_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_ov_int_en : 1; /* [0] */ + u32 hva_npq_uf_int_en : 1; /* [1] */ + u32 hva_npq_send_empty_int_en : 1; /* [2] */ + u32 hva_pq_ov_int_en : 1; /* [3] */ + u32 hva_pq_uf_int_en : 1; /* [4] */ + u32 hva_pq_send_empty_int_en : 1; /* [5] */ + u32 hva_1bit_ecc_int_en : 1; /* [6] */ + u32 hva_2bit_ecc_int_en : 1; /* [7] */ + u32 hva_flr_int_en : 1; /* [8] */ + u32 rsv_11 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_int_en_u; + +/* Define the union csr_hva_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_ov_int_set : 1; /* [0] */ + u32 hva_npq_uf_int_set : 1; /* [1] */ + u32 hva_npq_send_empty_int_set : 1; /* [2] */ + u32 hva_pq_ov_int_set : 1; /* [3] */ + u32 hva_pq_uf_int_set : 1; /* [4] */ + u32 hva_pq_send_empty_int_set : 1; /* [5] */ + u32 hva_1bit_ecc_int_set : 1; /* [6] */ + u32 hva_2bit_ecc_int_set : 1; /* [7] */ + u32 hva_flr_int_set : 1; /* [8] */ + u32 rsv_12 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_int_set_u; + +/* Define the union csr_hva_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_ov_int_raw_status : 1; /* [0] */ + u32 hva_npq_uf_int_raw_status : 1; /* [1] */ + u32 hva_npq_send_empty_int_raw_status : 1; /* [2] */ + u32 hva_pq_ov_int_raw_status : 1; /* [3] */ + u32 hva_pq_uf_int_raw_status : 1; /* [4] */ + u32 hva_pq_send_empty_int_raw_status : 1; /* [5] */ + u32 hva_1bit_ecc_int_raw_status : 1; /* [6] */ + u32 hva_2bit_ecc_int_raw_status : 1; /* [7] */ + u32 hva_flr_int_raw_status : 1; /* [8] */ + u32 rsv_13 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_int_raw_status_u; + +/* Define the union csr_hva_axi_err_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_axi_err_msk : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_axi_err_msk_u; + +/* Define the union csr_hva_axi_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rd_max_trans : 8; /* [7:0] */ + u32 cfg_wr_max_trans : 8; /* [15:8] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_axi_max_trans_u; + +/* Define the union csr_hva_cpi_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_cpi_10bit_tag_req_en : 1; /* [0] */ + u32 hva_cpi_10bit_tag_cpl_en : 1; /* [1] */ + u32 hva_cpi_extended_tag_en : 1; /* [2] */ + u32 hva_cpi_cpl_timeout_dis : 1; /* [3] */ + u32 hva_cpi_cpl_timeout_value : 4; /* [7:4] */ + u32 hva_cpi_cfg_mrrs : 3; /* [10:8] */ + u32 rsv_16 : 1; /* [11] */ + u32 hva_cpi_cfg_mps : 3; /* [14:12] */ + u32 rsv_17 : 1; /* [15] */ + u32 hva_link_down : 1; /* [16] */ + u32 hva_cpi_tx_crd_active_en : 1; /* [17] */ + u32 rsv_18 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_cpi_cfg_u; + +/* Define the union csr_hva_cpi_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_cpi_p_hed_crdt : 8; /* [7:0] */ + u32 hva_cpi_p_dat_crdt : 8; /* [15:8] */ + u32 hva_cpi_np_hed_crdt : 8; /* [23:16] */ + u32 rsv_19 : 7; /* [30:24] */ + u32 hva_cpi_crdt_init : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_cpi_crdt_cfg_u; + +/* Define the union csr_hva_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_ram_err_chk_bypass : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_ram_ecc_bypass_u; + +/* Define the union csr_hva_ram_ecc_err_ins_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_db_ram_cerr_ins_req : 1; /* [0] */ + u32 hva_npq_db_ram_ucerr_ins_req : 1; /* [1] */ + u32 hva_pq_db_ram_cerr_ins_req : 1; /* [2] */ + u32 hva_pq_db_ram_ucerr_ins_req : 1; /* [3] */ + u32 hva_npq_entry_ram_cerr_ins_req : 1; /* [4] */ + u32 hva_npq_entry_ram_ucerr_ins_req : 1; /* [5] */ + u32 hva_pq_entry_ram_cerr_ins_req : 1; /* [6] */ + u32 hva_pq_entry_ram_ucerr_ins_req : 1; /* [7] */ + u32 rsv_21 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_ram_ecc_err_ins_u; + +/* Define the union csr_hva_fatal_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_db_ram_ucerr_fatal_en : 1; /* [0] */ + u32 hva_pq_db_ram_ucerr_fatal_en : 1; /* [1] */ + u32 hva_npq_entry_ram_ucerr_fatal_en : 1; /* [2] */ + u32 hva_pq_entry_ram_ucerr_fatal_en : 1; /* [3] */ + u32 hva_npq_ov_fatal_en : 1; /* [4] */ + u32 hva_npq_uf_fatal_en : 1; /* [5] */ + u32 hva_npq_send_empty_fatal_en : 1; /* [6] */ + u32 hva_pq_ov_fatal_en : 1; /* [7] */ + u32 hva_pq_uf_fatal_en : 1; /* [8] */ + u32 hva_pq_send_empty_fatal_en : 1; /* [9] */ + u32 rsv_22 : 21; /* [30:10] */ + u32 hva_fatal_err_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_fatal_err_ctrl_u; + +/* Define the union csr_hva_inner_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_inner_cpl_data_crdt : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 hva_inner_send_npq_crdt : 3; /* [6:4] */ + u32 rsv_24 : 1; /* [7] */ + u32 hva_inner_send_pq_crdt : 3; /* [10:8] */ + u32 rsv_25 : 20; /* [30:11] */ + u32 hva_inner_crdt_init : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_inner_crdt_u; + +/* Define the union csr_hva_fifo_af_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_pq_sdata_fifo_af_th : 4; /* [3:0] */ + u32 rsv_26 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_fifo_af_cfg_u; + +/* Define the union csr_hva_bd_cfg_pf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_cfg_pf_num : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_bd_cfg_pf_num_u; + +/* Define the union csr_hva_flr_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_flr_sta : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_flr_sta_u; + +/* Define the union csr_hva_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_cpl_stat_en : 1; /* [0] */ + u32 dfx_tx_cpl_stat_clr : 1; /* [1] */ + u32 dfx_tx_cpl_cnt_clr : 1; /* [2] */ + u32 dfx_hva_get_cpi_p_cnt_clr : 1; /* [3] */ + u32 dfx_tx_p_stat_en : 1; /* [4] */ + u32 dfx_tx_p_stat_clr : 1; /* [5] */ + u32 hva_dfx_ucerr_cnt_clr : 1; /* [6] */ + u32 hva_dfx_cerr_cnt_clr : 1; /* [7] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_cfg_u; + +/* Define the union csr_hva_dfx_cpl_bw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_cpl_bw_curr : 16; /* [15:0] */ + u32 dfx_tx_cpl_bw_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_cpl_bw0_u; + +/* Define the union csr_hva_dfx_cpl_bw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_cpl_bw_ava : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_cpl_bw1_u; + +/* Define the union csr_hva_dfx_npq_db_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_npq_db_state : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_npq_db_state_u; + +/* Define the union csr_hva_dfx_tx_cpl_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_cpl_dat_err_cnt : 16; /* [15:0] */ + u32 dfx_tx_cpl_unsuccess_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_tx_cpl_cnt0_u; + +/* Define the union csr_hva_dfx_tx_cpl_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_tx_cpl_cnt1_u; + +/* Define the union csr_hva_npq_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_npq_send_ptr : 8; /* [7:0] */ + u32 dfx_npq_free_ptr : 8; /* [15:8] */ + u32 dfx_npq_rls_ptr : 8; /* [23:16] */ + u32 dfx_npq_free_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_npq_ptr_u; + +/* Define the union csr_hva_dfx_p_bw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_p_bw_curr : 16; /* [15:0] */ + u32 dfx_tx_p_bw_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_p_bw0_u; + +/* Define the union csr_hva_dfx_p_bw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_tx_p_bw_ava : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_p_bw1_u; + +/* Define the union csr_hva_dfx_p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_get_cpi_p_cnt : 16; /* [15:0] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_p_cnt_u; + +/* Define the union csr_hva_dfx_pq_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pq_send_ptr : 8; /* [7:0] */ + u32 dfx_pq_free_ptr : 8; /* [15:8] */ + u32 dfx_pq_rls_ptr : 8; /* [23:16] */ + u32 dfx_pq_free_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_pq_ptr_u; + +/* Define the union csr_hva_dfx_pq_wr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_31 : 16; /* [15:0] */ + u32 dfx_pq_wr_err_abresp : 1; /* [16] */ + u32 dfx_pq_wr_err : 1; /* [17] */ + u32 dfx_pq_wr_err_clr : 1; /* [18] */ + u32 rsv_32 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_pq_wr_err_u; + +/* Define the union csr_hva_dfx_pq_wr_err_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pq_wr_err_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_pq_wr_err_addr_h_u; + +/* Define the union csr_hva_dfx_pq_wr_err_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pq_wr_err_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_pq_wr_err_addr_l_u; + +/* Define the union csr_hva_dfx_tlp_zero_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pq_zero_write : 1; /* [0] */ + u32 dfx_npq_zero_read : 1; /* [1] */ + u32 rsv_33 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_tlp_zero_len_u; + +/* Define the union csr_hva_dfx_axi_bid_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_bid_err : 1; /* [0] */ + u32 rsv_34 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_axi_bid_err_u; + +/* Define the union csr_hva_dfx_db_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_dfx_pq_db_ecc_err_addr : 5; /* [4:0] */ + u32 rsv_35 : 11; /* [15:5] */ + u32 hva_dfx_npq_db_ecc_err_addr : 9; /* [24:16] */ + u32 rsv_36 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_db_ecc_err_addr_u; + +/* Define the union csr_hva_dfx_entry_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_dfx_pq_entry_ecc_err_addr : 7; /* [6:0] */ + u32 rsv_37 : 1; /* [7] */ + u32 hva_dfx_npq_entry_ecc_err_addr : 7; /* [14:8] */ + u32 rsv_38 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_entry_ecc_err_addr_u; + +/* Define the union csr_hva_dfx_mem_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_dfx_mem_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_mem_cerr_cnt_u; + +/* Define the union csr_hva_dfx_mem_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_dfx_mem_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_mem_ucerr_cnt_u; + +/* Define the union csr_hva_dfx_ecc_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_npq_db_ram_cerr : 1; /* [0] */ + u32 hva_npq_db_ram_ucerr : 1; /* [1] */ + u32 hva_pq_db_ram_cerr : 1; /* [2] */ + u32 hva_pq_db_ram_ucerr : 1; /* [3] */ + u32 hva_npq_entry_ram_cerr : 1; /* [4] */ + u32 hva_npq_entry_ram_ucerr : 1; /* [5] */ + u32 hva_pq_entry_ram_cerr : 1; /* [6] */ + u32 hva_pq_entry_ram_ucerr : 1; /* [7] */ + u32 rsv_39 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_dfx_ecc_sta_u; + +/* Define the union csr_hva_op_bar_addr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rd_bar_add_err : 1; /* [0] */ + u32 dfx_wr_bar_add_err : 1; /* [1] */ + u32 rsv_40 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_op_bar_addr_err_u; + +/* Define the union csr_hva_op_bar_addr_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rd_bar_add_err_cnt : 16; /* [15:0] */ + u32 dfx_wr_bar_add_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_op_bar_addr_err_cnt_u; + +/* Define the union csr_cpi_hva_req_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpi_hva_p_cnt : 16; /* [15:0] */ + u32 dfx_cpi_hva_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_hva_req_tlp_num_u; + +/* Define the union csr_hva_cpi_req_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_cpi_p_cnt : 16; /* [15:0] */ + u32 dfx_hva_cpi_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_cpi_req_tlp_num_u; + +/* Define the union csr_cpl_tlp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpi_hva_cpl_cnt : 16; /* [15:0] */ + u32 dfx_hva_cpi_cpl_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_tlp_num_u; + +/* Define the union csr_hva_smmu_axi_rd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_smmu_hva_rl_cnt : 16; /* [15:0] */ + u32 dfx_hva_smmu_ar_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smmu_axi_rd_num_u; + +/* Define the union csr_hva_smmu_axi_wr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_smmu_wl_cnt : 16; /* [15:0] */ + u32 dfx_hva_smmu_aw_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smmu_axi_wr_num_u; + +/* Define the union csr_hva_axi_b_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_disp_b_cnt : 16; /* [15:0] */ + u32 dfx_smmu_hva_b_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_axi_b_num_u; + +/* Define the union csr_disp_hva_axi_rd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_disp_rl_cnt : 16; /* [15:0] */ + u32 dfx_disp_hva_ar_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_disp_hva_axi_rd_num_u; + +/* Define the union csr_disp_hva_axi_wr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_disp_hva_wl_cnt : 16; /* [15:0] */ + u32 dfx_disp_hva_aw_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_disp_hva_axi_wr_num_u; + +/* Define the union csr_hva_cpi_cpl_tnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_cpi_cpl_tcnt : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_cpi_cpl_tnum_u; + +/* Define the union csr_msi_len_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_msi_len_err : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_len_err_u; + +/* Define the union csr_hva_lat_sts_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lat_stat_clr : 1; /* [0] */ + u32 cfg_lat_stat_en : 1; /* [1] */ + u32 rsv_41 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_lat_sts_cfg_u; + +/* Define the union csr_hva_wr_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wr_bp_clr_th : 16; /* [15:0] */ + u32 cfg_wr_bp_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_wr_bp_cfg_u; + +/* Define the union csr_hva_rd_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rd_bp_clr_th : 16; /* [15:0] */ + u32 cfg_rd_bp_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_rd_bp_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hva_fpga_ver_u hva_fpga_ver; /* 0 */ + volatile csr_hva_emu_ver_u hva_emu_ver; /* 4 */ + volatile csr_hva_mem_attr_win0_l_u hva_mem_attr_win0_l; /* C */ + volatile csr_hva_mem_attr_win0_h_u hva_mem_attr_win0_h; /* 10 */ + volatile csr_hva_mem_attr_win1_l_u hva_mem_attr_win1_l; /* 14 */ + volatile csr_hva_mem_attr_win1_h_u hva_mem_attr_win1_h; /* 18 */ + volatile csr_hva_mem_attr_win2_l_u hva_mem_attr_win2_l; /* 1C */ + volatile csr_hva_mem_attr_win2_h_u hva_mem_attr_win2_h; /* 20 */ + volatile csr_hva_mem_attr_win3_l_u hva_mem_attr_win3_l; /* 24 */ + volatile csr_hva_mem_attr_win3_h_u hva_mem_attr_win3_h; /* 28 */ + volatile csr_hva_mem_attr_u hva_mem_attr[5]; /* 30 */ + volatile csr_hva_ar_cfg_u hva_ar_cfg; /* 50 */ + volatile csr_hva_wr_cfg_u hva_wr_cfg; /* 54 */ + volatile csr_hva_arstrmid_u hva_arstrmid; /* 58 */ + volatile csr_hva_awstrmid_u hva_awstrmid; /* 5C */ + volatile csr_hva_peh_enum_bar0_wr_mask_u hva_peh_enum_bar0_wr_mask; /* 60 */ + volatile csr_hva_peh_enum_bar1_wr_mask_u hva_peh_enum_bar1_wr_mask; /* 64 */ + volatile csr_hva_peh_enum_bar2_wr_mask_u hva_peh_enum_bar2_wr_mask; /* 68 */ + volatile csr_hva_peh_enum_bar3_wr_mask_u hva_peh_enum_bar3_wr_mask; /* 6C */ + volatile csr_hva_peh_enum_bar4_wr_mask_u hva_peh_enum_bar4_wr_mask; /* 70 */ + volatile csr_hva_peh_enum_bar5_wr_mask_u hva_peh_enum_bar5_wr_mask; /* 74 */ + volatile csr_hva_peh_feature_en_u hva_peh_feature_en; /* 78 */ + volatile csr_hva_pf_cmd_type_u hva_pf_cmd_type; /* 7C */ + volatile csr_hva_int_starus_u hva_int_starus; /* 80 */ + volatile csr_hva_int_en_u hva_int_en; /* 84 */ + volatile csr_hva_int_set_u hva_int_set; /* 88 */ + volatile csr_hva_int_raw_status_u hva_int_raw_status; /* 8C */ + volatile csr_hva_axi_err_msk_u hva_axi_err_msk; /* 90 */ + volatile csr_hva_axi_max_trans_u hva_axi_max_trans; /* A0 */ + volatile csr_hva_cpi_cfg_u hva_cpi_cfg; /* B0 */ + volatile csr_hva_cpi_crdt_cfg_u hva_cpi_crdt_cfg; /* B4 */ + volatile csr_hva_ram_ecc_bypass_u hva_ram_ecc_bypass; /* B8 */ + volatile csr_hva_ram_ecc_err_ins_u hva_ram_ecc_err_ins; /* BC */ + volatile csr_hva_fatal_err_ctrl_u hva_fatal_err_ctrl; /* C0 */ + volatile csr_hva_inner_crdt_u hva_inner_crdt; /* C4 */ + volatile csr_hva_fifo_af_cfg_u hva_fifo_af_cfg; /* C8 */ + volatile csr_hva_bd_cfg_pf_num_u hva_bd_cfg_pf_num; /* CC */ + volatile csr_hva_flr_sta_u hva_flr_sta; /* D0 */ + volatile csr_hva_dfx_cfg_u hva_dfx_cfg; /* 200 */ + volatile csr_hva_dfx_cpl_bw0_u hva_dfx_cpl_bw0; /* 210 */ + volatile csr_hva_dfx_cpl_bw1_u hva_dfx_cpl_bw1; /* 220 */ + volatile csr_hva_dfx_npq_db_state_u hva_dfx_npq_db_state; /* 230 */ + volatile csr_hva_dfx_tx_cpl_cnt0_u hva_dfx_tx_cpl_cnt0; /* 240 */ + volatile csr_hva_dfx_tx_cpl_cnt1_u hva_dfx_tx_cpl_cnt1; /* 250 */ + volatile csr_hva_npq_ptr_u hva_npq_ptr; /* 260 */ + volatile csr_hva_dfx_p_bw0_u hva_dfx_p_bw0; /* 270 */ + volatile csr_hva_dfx_p_bw1_u hva_dfx_p_bw1; /* 280 */ + volatile csr_hva_dfx_p_cnt_u hva_dfx_p_cnt; /* 290 */ + volatile csr_hva_dfx_pq_ptr_u hva_dfx_pq_ptr; /* 2A0 */ + volatile csr_hva_dfx_pq_wr_err_u hva_dfx_pq_wr_err; /* 2B0 */ + volatile csr_hva_dfx_pq_wr_err_addr_h_u hva_dfx_pq_wr_err_addr_h; /* 2C0 */ + volatile csr_hva_dfx_pq_wr_err_addr_l_u hva_dfx_pq_wr_err_addr_l; /* 2D0 */ + volatile csr_hva_dfx_tlp_zero_len_u hva_dfx_tlp_zero_len; /* 2E0 */ + volatile csr_hva_dfx_axi_bid_err_u hva_dfx_axi_bid_err; /* 2F0 */ + volatile csr_hva_dfx_db_ecc_err_addr_u hva_dfx_db_ecc_err_addr; /* 300 */ + volatile csr_hva_dfx_entry_ecc_err_addr_u hva_dfx_entry_ecc_err_addr; /* 310 */ + volatile csr_hva_dfx_mem_cerr_cnt_u hva_dfx_mem_cerr_cnt; /* 320 */ + volatile csr_hva_dfx_mem_ucerr_cnt_u hva_dfx_mem_ucerr_cnt; /* 324 */ + volatile csr_hva_dfx_ecc_sta_u hva_dfx_ecc_sta; /* 330 */ + volatile csr_hva_op_bar_addr_err_u hva_op_bar_addr_err; /* 3A0 */ + volatile csr_hva_op_bar_addr_err_cnt_u hva_op_bar_addr_err_cnt; /* 3A4 */ + volatile csr_cpi_hva_req_tlp_num_u cpi_hva_req_tlp_num; /* 3A8 */ + volatile csr_hva_cpi_req_tlp_num_u hva_cpi_req_tlp_num; /* 3AC */ + volatile csr_cpl_tlp_num_u cpl_tlp_num; /* 3B0 */ + volatile csr_hva_smmu_axi_rd_num_u hva_smmu_axi_rd_num; /* 3B4 */ + volatile csr_hva_smmu_axi_wr_num_u hva_smmu_axi_wr_num; /* 3B8 */ + volatile csr_hva_axi_b_num_u hva_axi_b_num; /* 3BC */ + volatile csr_disp_hva_axi_rd_num_u disp_hva_axi_rd_num; /* 3C0 */ + volatile csr_disp_hva_axi_wr_num_u disp_hva_axi_wr_num; /* 3C4 */ + volatile csr_hva_cpi_cpl_tnum_u hva_cpi_cpl_tnum; /* 3C8 */ + volatile csr_msi_len_err_u msi_len_err; /* 3CC */ + volatile csr_hva_lat_sts_cfg_u hva_lat_sts_cfg; /* 400 */ + volatile csr_hva_wr_bp_cfg_u hva_wr_bp_cfg; /* 404 */ + volatile csr_hva_rd_bp_cfg_u hva_rd_bp_cfg; /* 408 */ +} S_hva_reg_REGS_TYPE; + +/* Declare the struct pointor of the module hva_reg */ +extern volatile S_hva_reg_REGS_TYPE *gophva_regAllReg; + +/* Declare the functions that set the member value */ +int iSetHVA_FPGA_VER_hva_fpga_ver(unsigned int uhva_fpga_ver); +int iSetHVA_EMU_VER_hva_emu_ver(unsigned int uhva_emu_ver); +int iSetHVA_MEM_ATTR_WIN0_L_hva_mem_attr_win0_l(unsigned int uhva_mem_attr_win0_l); +int iSetHVA_MEM_ATTR_WIN0_H_hva_mem_attr_win0_h(unsigned int uhva_mem_attr_win0_h); +int iSetHVA_MEM_ATTR_WIN1_L_hva_mem_attr_win1_l(unsigned int uhva_mem_attr_win1_l); +int iSetHVA_MEM_ATTR_WIN1_H_hva_mem_attr_win1_h(unsigned int uhva_mem_attr_win1_h); +int iSetHVA_MEM_ATTR_WIN2_L_hva_mem_attr_win2_l(unsigned int uhva_mem_attr_win2_l); +int iSetHVA_MEM_ATTR_WIN2_H_hva_mem_attr_win2_h(unsigned int uhva_mem_attr_win2_h); +int iSetHVA_MEM_ATTR_WIN3_L_hva_mem_attr_win3_l(unsigned int uhva_mem_attr_win3_l); +int iSetHVA_MEM_ATTR_WIN3_H_hva_mem_attr_win3_h(unsigned int uhva_mem_attr_win3_h); +int iSetHVA_MEM_ATTR_hva_mem_attr_rd(unsigned int uhva_mem_attr_rd); +int iSetHVA_MEM_ATTR_hva_mem_attr_wr(unsigned int uhva_mem_attr_wr); +int iSetHVA_AR_CFG_cfg_arqos_set(unsigned int ucfg_arqos_set); +int iSetHVA_AR_CFG_cfg_arssv_set(unsigned int ucfg_arssv_set); +int iSetHVA_AR_CFG_cfg_arstrmid_mode(unsigned int ucfg_arstrmid_mode); +int iSetHVA_AR_CFG_cfg_rdcln_thrld(unsigned int ucfg_rdcln_thrld); +int iSetHVA_AR_CFG_cfg_rdfna_thrld(unsigned int ucfg_rdfna_thrld); +int iSetHVA_AR_CFG_cfg_rdtype_thrld(unsigned int ucfg_rdtype_thrld); +int iSetHVA_AR_CFG_cfg_rdfa_thrld(unsigned int ucfg_rdfa_thrld); +int iSetHVA_AR_CFG_cfg_rd_fa_mode(unsigned int ucfg_rd_fa_mode); +int iSetHVA_AR_CFG_cfg_rd_fna_mode(unsigned int ucfg_rd_fna_mode); +int iSetHVA_AR_CFG_cfg_rd_cln_mode(unsigned int ucfg_rd_cln_mode); +int iSetHVA_AR_CFG_cfg_rd_type_mode(unsigned int ucfg_rd_type_mode); +int iSetHVA_WR_CFG_cfg_awqos_set(unsigned int ucfg_awqos_set); +int iSetHVA_WR_CFG_cfg_awssv_set(unsigned int ucfg_awssv_set); +int iSetHVA_WR_CFG_cfg_awstrmid_mode(unsigned int ucfg_awstrmid_mode); +int iSetHVA_WR_CFG_cfg_wr_so_set(unsigned int ucfg_wr_so_set); +int iSetHVA_WR_CFG_cfg_wrfna_thrld(unsigned int ucfg_wrfna_thrld); +int iSetHVA_WR_CFG_cfg_wrtype_thrld(unsigned int ucfg_wrtype_thrld); +int iSetHVA_WR_CFG_cfg_wrfa_thrld(unsigned int ucfg_wrfa_thrld); +int iSetHVA_WR_CFG_cfg_wr_fa_mode(unsigned int ucfg_wr_fa_mode); +int iSetHVA_WR_CFG_cfg_wr_fna_mode(unsigned int ucfg_wr_fna_mode); +int iSetHVA_WR_CFG_cfg_wr_fp_mode(unsigned int ucfg_wr_fp_mode); +int iSetHVA_WR_CFG_cfg_wr_type_mode(unsigned int ucfg_wr_type_mode); +int iSetHVA_WR_CFG_cfg_wr_so_mode(unsigned int ucfg_wr_so_mode); +int iSetHVA_ARSTRMID_hva_rd_strmid(unsigned int uhva_rd_strmid); +int iSetHVA_AWSTRMID_hva_wr_strmid(unsigned int uhva_wr_strmid); +int iSetHVA_PEH_ENUM_BAR0_WR_MASK_hva_peh_enum_bar0_wr_mask(unsigned int uhva_peh_enum_bar0_wr_mask); +int iSetHVA_PEH_ENUM_BAR1_WR_MASK_hva_peh_enum_bar1_wr_mask(unsigned int uhva_peh_enum_bar1_wr_mask); +int iSetHVA_PEH_ENUM_BAR2_WR_MASK_hva_peh_enum_bar2_wr_mask(unsigned int uhva_peh_enum_bar2_wr_mask); +int iSetHVA_PEH_ENUM_BAR3_WR_MASK_hva_peh_enum_bar3_wr_mask(unsigned int uhva_peh_enum_bar3_wr_mask); +int iSetHVA_PEH_ENUM_BAR4_WR_MASK_hva_peh_enum_bar4_wr_mask(unsigned int uhva_peh_enum_bar4_wr_mask); +int iSetHVA_PEH_ENUM_BAR5_WR_MASK_hva_peh_enum_bar5_wr_mask(unsigned int uhva_peh_enum_bar5_wr_mask); +int iSetHVA_PEH_FEATURE_EN_hva_peh_feature_en(unsigned int uhva_peh_feature_en); +int iSetHVA_PEH_FEATURE_EN_hva_flr_done(unsigned int uhva_flr_done); +int iSetHVA_PF_CMD_TYPE_cfg_pf_cmd_type(unsigned int ucfg_pf_cmd_type); +int iSetHVA_INT_STARUS_hva_npq_ov_int_status(unsigned int uhva_npq_ov_int_status); +int iSetHVA_INT_STARUS_hva_npq_uf_int_status(unsigned int uhva_npq_uf_int_status); +int iSetHVA_INT_STARUS_hva_npq_send_empty_int_status(unsigned int uhva_npq_send_empty_int_status); +int iSetHVA_INT_STARUS_hva_pq_ov_int_status(unsigned int uhva_pq_ov_int_status); +int iSetHVA_INT_STARUS_hva_pq_uf_int_status(unsigned int uhva_pq_uf_int_status); +int iSetHVA_INT_STARUS_hva_pq_send_empty_int_status(unsigned int uhva_pq_send_empty_int_status); +int iSetHVA_INT_STARUS_hva_1bit_ecc_int_status(unsigned int uhva_1bit_ecc_int_status); +int iSetHVA_INT_STARUS_hva_2bit_ecc_int_status(unsigned int uhva_2bit_ecc_int_status); +int iSetHVA_INT_STARUS_hva_flr_int_status(unsigned int uhva_flr_int_status); +int iSetHVA_INT_EN_hva_npq_ov_int_en(unsigned int uhva_npq_ov_int_en); +int iSetHVA_INT_EN_hva_npq_uf_int_en(unsigned int uhva_npq_uf_int_en); +int iSetHVA_INT_EN_hva_npq_send_empty_int_en(unsigned int uhva_npq_send_empty_int_en); +int iSetHVA_INT_EN_hva_pq_ov_int_en(unsigned int uhva_pq_ov_int_en); +int iSetHVA_INT_EN_hva_pq_uf_int_en(unsigned int uhva_pq_uf_int_en); +int iSetHVA_INT_EN_hva_pq_send_empty_int_en(unsigned int uhva_pq_send_empty_int_en); +int iSetHVA_INT_EN_hva_1bit_ecc_int_en(unsigned int uhva_1bit_ecc_int_en); +int iSetHVA_INT_EN_hva_2bit_ecc_int_en(unsigned int uhva_2bit_ecc_int_en); +int iSetHVA_INT_EN_hva_flr_int_en(unsigned int uhva_flr_int_en); +int iSetHVA_INT_SET_hva_npq_ov_int_set(unsigned int uhva_npq_ov_int_set); +int iSetHVA_INT_SET_hva_npq_uf_int_set(unsigned int uhva_npq_uf_int_set); +int iSetHVA_INT_SET_hva_npq_send_empty_int_set(unsigned int uhva_npq_send_empty_int_set); +int iSetHVA_INT_SET_hva_pq_ov_int_set(unsigned int uhva_pq_ov_int_set); +int iSetHVA_INT_SET_hva_pq_uf_int_set(unsigned int uhva_pq_uf_int_set); +int iSetHVA_INT_SET_hva_pq_send_empty_int_set(unsigned int uhva_pq_send_empty_int_set); +int iSetHVA_INT_SET_hva_1bit_ecc_int_set(unsigned int uhva_1bit_ecc_int_set); +int iSetHVA_INT_SET_hva_2bit_ecc_int_set(unsigned int uhva_2bit_ecc_int_set); +int iSetHVA_INT_SET_hva_flr_int_set(unsigned int uhva_flr_int_set); +int iSetHVA_INT_RAW_STATUS_hva_npq_ov_int_raw_status(unsigned int uhva_npq_ov_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_npq_uf_int_raw_status(unsigned int uhva_npq_uf_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_npq_send_empty_int_raw_status(unsigned int uhva_npq_send_empty_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_pq_ov_int_raw_status(unsigned int uhva_pq_ov_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_pq_uf_int_raw_status(unsigned int uhva_pq_uf_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_pq_send_empty_int_raw_status(unsigned int uhva_pq_send_empty_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_1bit_ecc_int_raw_status(unsigned int uhva_1bit_ecc_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_2bit_ecc_int_raw_status(unsigned int uhva_2bit_ecc_int_raw_status); +int iSetHVA_INT_RAW_STATUS_hva_flr_int_raw_status(unsigned int uhva_flr_int_raw_status); +int iSetHVA_AXI_ERR_MSK_hva_axi_err_msk(unsigned int uhva_axi_err_msk); +int iSetHVA_AXI_MAX_TRANS_cfg_rd_max_trans(unsigned int ucfg_rd_max_trans); +int iSetHVA_AXI_MAX_TRANS_cfg_wr_max_trans(unsigned int ucfg_wr_max_trans); +int iSetHVA_CPI_CFG_hva_cpi_10bit_tag_req_en(unsigned int uhva_cpi_10bit_tag_req_en); +int iSetHVA_CPI_CFG_hva_cpi_10bit_tag_cpl_en(unsigned int uhva_cpi_10bit_tag_cpl_en); +int iSetHVA_CPI_CFG_hva_cpi_extended_tag_en(unsigned int uhva_cpi_extended_tag_en); +int iSetHVA_CPI_CFG_hva_cpi_cpl_timeout_dis(unsigned int uhva_cpi_cpl_timeout_dis); +int iSetHVA_CPI_CFG_hva_cpi_cpl_timeout_value(unsigned int uhva_cpi_cpl_timeout_value); +int iSetHVA_CPI_CFG_hva_cpi_cfg_mrrs(unsigned int uhva_cpi_cfg_mrrs); +int iSetHVA_CPI_CFG_hva_cpi_cfg_mps(unsigned int uhva_cpi_cfg_mps); +int iSetHVA_CPI_CFG_hva_link_down(unsigned int uhva_link_down); +int iSetHVA_CPI_CFG_hva_cpi_tx_crd_active_en(unsigned int uhva_cpi_tx_crd_active_en); +int iSetHVA_CPI_CRDT_CFG_hva_cpi_p_hed_crdt(unsigned int uhva_cpi_p_hed_crdt); +int iSetHVA_CPI_CRDT_CFG_hva_cpi_p_dat_crdt(unsigned int uhva_cpi_p_dat_crdt); +int iSetHVA_CPI_CRDT_CFG_hva_cpi_np_hed_crdt(unsigned int uhva_cpi_np_hed_crdt); +int iSetHVA_CPI_CRDT_CFG_hva_cpi_crdt_init(unsigned int uhva_cpi_crdt_init); +int iSetHVA_RAM_ECC_BYPASS_hva_ram_err_chk_bypass(unsigned int uhva_ram_err_chk_bypass); +int iSetHVA_RAM_ECC_ERR_INS_hva_npq_db_ram_cerr_ins_req(unsigned int uhva_npq_db_ram_cerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_npq_db_ram_ucerr_ins_req(unsigned int uhva_npq_db_ram_ucerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_pq_db_ram_cerr_ins_req(unsigned int uhva_pq_db_ram_cerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_pq_db_ram_ucerr_ins_req(unsigned int uhva_pq_db_ram_ucerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_npq_entry_ram_cerr_ins_req(unsigned int uhva_npq_entry_ram_cerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_npq_entry_ram_ucerr_ins_req(unsigned int uhva_npq_entry_ram_ucerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_pq_entry_ram_cerr_ins_req(unsigned int uhva_pq_entry_ram_cerr_ins_req); +int iSetHVA_RAM_ECC_ERR_INS_hva_pq_entry_ram_ucerr_ins_req(unsigned int uhva_pq_entry_ram_ucerr_ins_req); +int iSetHVA_FATAL_ERR_CTRL_hva_npq_db_ram_ucerr_fatal_en(unsigned int uhva_npq_db_ram_ucerr_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_pq_db_ram_ucerr_fatal_en(unsigned int uhva_pq_db_ram_ucerr_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_npq_entry_ram_ucerr_fatal_en(unsigned int uhva_npq_entry_ram_ucerr_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_pq_entry_ram_ucerr_fatal_en(unsigned int uhva_pq_entry_ram_ucerr_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_npq_ov_fatal_en(unsigned int uhva_npq_ov_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_npq_uf_fatal_en(unsigned int uhva_npq_uf_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_npq_send_empty_fatal_en(unsigned int uhva_npq_send_empty_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_pq_ov_fatal_en(unsigned int uhva_pq_ov_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_pq_uf_fatal_en(unsigned int uhva_pq_uf_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_pq_send_empty_fatal_en(unsigned int uhva_pq_send_empty_fatal_en); +int iSetHVA_FATAL_ERR_CTRL_hva_fatal_err_en(unsigned int uhva_fatal_err_en); +int iSetHVA_INNER_CRDT_hva_inner_cpl_data_crdt(unsigned int uhva_inner_cpl_data_crdt); +int iSetHVA_INNER_CRDT_hva_inner_send_npq_crdt(unsigned int uhva_inner_send_npq_crdt); +int iSetHVA_INNER_CRDT_hva_inner_send_pq_crdt(unsigned int uhva_inner_send_pq_crdt); +int iSetHVA_INNER_CRDT_hva_inner_crdt_init(unsigned int uhva_inner_crdt_init); +int iSetHVA_FIFO_AF_CFG_hva_pq_sdata_fifo_af_th(unsigned int uhva_pq_sdata_fifo_af_th); +int iSetHVA_BD_CFG_PF_NUM_bd_cfg_pf_num(unsigned int ubd_cfg_pf_num); +int iSetHVA_FLR_STA_hva_flr_sta(unsigned int uhva_flr_sta); +int iSetHVA_DFX_CFG_dfx_tx_cpl_stat_en(unsigned int udfx_tx_cpl_stat_en); +int iSetHVA_DFX_CFG_dfx_tx_cpl_stat_clr(unsigned int udfx_tx_cpl_stat_clr); +int iSetHVA_DFX_CFG_dfx_tx_cpl_cnt_clr(unsigned int udfx_tx_cpl_cnt_clr); +int iSetHVA_DFX_CFG_dfx_hva_get_cpi_p_cnt_clr(unsigned int udfx_hva_get_cpi_p_cnt_clr); +int iSetHVA_DFX_CFG_dfx_tx_p_stat_en(unsigned int udfx_tx_p_stat_en); +int iSetHVA_DFX_CFG_dfx_tx_p_stat_clr(unsigned int udfx_tx_p_stat_clr); +int iSetHVA_DFX_CFG_hva_dfx_ucerr_cnt_clr(unsigned int uhva_dfx_ucerr_cnt_clr); +int iSetHVA_DFX_CFG_hva_dfx_cerr_cnt_clr(unsigned int uhva_dfx_cerr_cnt_clr); +int iSetHVA_DFX_CPL_BW0_dfx_tx_cpl_bw_curr(unsigned int udfx_tx_cpl_bw_curr); +int iSetHVA_DFX_CPL_BW0_dfx_tx_cpl_bw_max(unsigned int udfx_tx_cpl_bw_max); +int iSetHVA_DFX_CPL_BW1_dfx_tx_cpl_bw_ava(unsigned int udfx_tx_cpl_bw_ava); +int iSetHVA_DFX_NPQ_DB_STATE_dfx_npq_db_state(unsigned int udfx_npq_db_state); +int iSetHVA_DFX_TX_CPL_CNT0_dfx_tx_cpl_dat_err_cnt(unsigned int udfx_tx_cpl_dat_err_cnt); +int iSetHVA_DFX_TX_CPL_CNT0_dfx_tx_cpl_unsuccess_cnt(unsigned int udfx_tx_cpl_unsuccess_cnt); +int iSetHVA_DFX_TX_CPL_CNT1_dfx_tx_cpl_cnt(unsigned int udfx_tx_cpl_cnt); +int iSetHVA_NPQ_PTR_dfx_npq_send_ptr(unsigned int udfx_npq_send_ptr); +int iSetHVA_NPQ_PTR_dfx_npq_free_ptr(unsigned int udfx_npq_free_ptr); +int iSetHVA_NPQ_PTR_dfx_npq_rls_ptr(unsigned int udfx_npq_rls_ptr); +int iSetHVA_NPQ_PTR_dfx_npq_free_cnt(unsigned int udfx_npq_free_cnt); +int iSetHVA_DFX_P_BW0_dfx_tx_p_bw_curr(unsigned int udfx_tx_p_bw_curr); +int iSetHVA_DFX_P_BW0_dfx_tx_p_bw_max(unsigned int udfx_tx_p_bw_max); +int iSetHVA_DFX_P_BW1_dfx_tx_p_bw_ava(unsigned int udfx_tx_p_bw_ava); +int iSetHVA_DFX_P_CNT_dfx_hva_get_cpi_p_cnt(unsigned int udfx_hva_get_cpi_p_cnt); +int iSetHVA_DFX_PQ_PTR_dfx_pq_send_ptr(unsigned int udfx_pq_send_ptr); +int iSetHVA_DFX_PQ_PTR_dfx_pq_free_ptr(unsigned int udfx_pq_free_ptr); +int iSetHVA_DFX_PQ_PTR_dfx_pq_rls_ptr(unsigned int udfx_pq_rls_ptr); +int iSetHVA_DFX_PQ_PTR_dfx_pq_free_cnt(unsigned int udfx_pq_free_cnt); +int iSetHVA_DFX_PQ_WR_ERR_dfx_pq_wr_err_abresp(unsigned int udfx_pq_wr_err_abresp); +int iSetHVA_DFX_PQ_WR_ERR_dfx_pq_wr_err(unsigned int udfx_pq_wr_err); +int iSetHVA_DFX_PQ_WR_ERR_dfx_pq_wr_err_clr(unsigned int udfx_pq_wr_err_clr); +int iSetHVA_DFX_PQ_WR_ERR_ADDR_H_dfx_pq_wr_err_addr_h(unsigned int udfx_pq_wr_err_addr_h); +int iSetHVA_DFX_PQ_WR_ERR_ADDR_L_dfx_pq_wr_err_addr_l(unsigned int udfx_pq_wr_err_addr_l); +int iSetHVA_DFX_TLP_ZERO_LEN_dfx_pq_zero_write(unsigned int udfx_pq_zero_write); +int iSetHVA_DFX_TLP_ZERO_LEN_dfx_npq_zero_read(unsigned int udfx_npq_zero_read); +int iSetHVA_DFX_AXI_BID_ERR_dfx_hva_bid_err(unsigned int udfx_hva_bid_err); +int iSetHVA_DFX_DB_ECC_ERR_ADDR_hva_dfx_pq_db_ecc_err_addr(unsigned int uhva_dfx_pq_db_ecc_err_addr); +int iSetHVA_DFX_DB_ECC_ERR_ADDR_hva_dfx_npq_db_ecc_err_addr(unsigned int uhva_dfx_npq_db_ecc_err_addr); +int iSetHVA_DFX_ENTRY_ECC_ERR_ADDR_hva_dfx_pq_entry_ecc_err_addr(unsigned int uhva_dfx_pq_entry_ecc_err_addr); +int iSetHVA_DFX_ENTRY_ECC_ERR_ADDR_hva_dfx_npq_entry_ecc_err_addr(unsigned int uhva_dfx_npq_entry_ecc_err_addr); +int iSetHVA_DFX_MEM_CERR_CNT_hva_dfx_mem_cerr_cnt(unsigned int uhva_dfx_mem_cerr_cnt); +int iSetHVA_DFX_MEM_UCERR_CNT_hva_dfx_mem_ucerr_cnt(unsigned int uhva_dfx_mem_ucerr_cnt); +int iSetHVA_DFX_ECC_STA_hva_npq_db_ram_cerr(unsigned int uhva_npq_db_ram_cerr); +int iSetHVA_DFX_ECC_STA_hva_npq_db_ram_ucerr(unsigned int uhva_npq_db_ram_ucerr); +int iSetHVA_DFX_ECC_STA_hva_pq_db_ram_cerr(unsigned int uhva_pq_db_ram_cerr); +int iSetHVA_DFX_ECC_STA_hva_pq_db_ram_ucerr(unsigned int uhva_pq_db_ram_ucerr); +int iSetHVA_DFX_ECC_STA_hva_npq_entry_ram_cerr(unsigned int uhva_npq_entry_ram_cerr); +int iSetHVA_DFX_ECC_STA_hva_npq_entry_ram_ucerr(unsigned int uhva_npq_entry_ram_ucerr); +int iSetHVA_DFX_ECC_STA_hva_pq_entry_ram_cerr(unsigned int uhva_pq_entry_ram_cerr); +int iSetHVA_DFX_ECC_STA_hva_pq_entry_ram_ucerr(unsigned int uhva_pq_entry_ram_ucerr); +int iSetHVA_OP_BAR_ADDR_ERR_dfx_rd_bar_add_err(unsigned int udfx_rd_bar_add_err); +int iSetHVA_OP_BAR_ADDR_ERR_dfx_wr_bar_add_err(unsigned int udfx_wr_bar_add_err); +int iSetHVA_OP_BAR_ADDR_ERR_CNT_dfx_rd_bar_add_err_cnt(unsigned int udfx_rd_bar_add_err_cnt); +int iSetHVA_OP_BAR_ADDR_ERR_CNT_dfx_wr_bar_add_err_cnt(unsigned int udfx_wr_bar_add_err_cnt); +int iSetCPI_HVA_REQ_TLP_NUM_dfx_cpi_hva_p_cnt(unsigned int udfx_cpi_hva_p_cnt); +int iSetCPI_HVA_REQ_TLP_NUM_dfx_cpi_hva_np_cnt(unsigned int udfx_cpi_hva_np_cnt); +int iSetHVA_CPI_REQ_TLP_NUM_dfx_hva_cpi_p_cnt(unsigned int udfx_hva_cpi_p_cnt); +int iSetHVA_CPI_REQ_TLP_NUM_dfx_hva_cpi_np_cnt(unsigned int udfx_hva_cpi_np_cnt); +int iSetCPL_TLP_NUM_dfx_cpi_hva_cpl_cnt(unsigned int udfx_cpi_hva_cpl_cnt); +int iSetCPL_TLP_NUM_dfx_hva_cpi_cpl_cnt(unsigned int udfx_hva_cpi_cpl_cnt); +int iSetHVA_SMMU_AXI_RD_NUM_dfx_smmu_hva_rl_cnt(unsigned int udfx_smmu_hva_rl_cnt); +int iSetHVA_SMMU_AXI_RD_NUM_dfx_hva_smmu_ar_cnt(unsigned int udfx_hva_smmu_ar_cnt); +int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_wl_cnt(unsigned int udfx_hva_smmu_wl_cnt); +int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_aw_cnt(unsigned int udfx_hva_smmu_aw_cnt); +int iSetHVA_AXI_B_NUM_dfx_hva_disp_b_cnt(unsigned int udfx_hva_disp_b_cnt); +int iSetHVA_AXI_B_NUM_dfx_smmu_hva_b_cnt(unsigned int udfx_smmu_hva_b_cnt); +int iSetDISP_HVA_AXI_RD_NUM_dfx_hva_disp_rl_cnt(unsigned int udfx_hva_disp_rl_cnt); +int iSetDISP_HVA_AXI_RD_NUM_dfx_disp_hva_ar_cnt(unsigned int udfx_disp_hva_ar_cnt); +int iSetDISP_HVA_AXI_WR_NUM_dfx_disp_hva_wl_cnt(unsigned int udfx_disp_hva_wl_cnt); +int iSetDISP_HVA_AXI_WR_NUM_dfx_disp_hva_aw_cnt(unsigned int udfx_disp_hva_aw_cnt); +int iSetHVA_CPI_CPL_TNUM_dfx_hva_cpi_cpl_tcnt(unsigned int udfx_hva_cpi_cpl_tcnt); +int iSetMSI_LEN_ERR_dfx_msi_len_err(unsigned int udfx_msi_len_err); +int iSetHVA_LAT_STS_CFG_cfg_lat_stat_clr(unsigned int ucfg_lat_stat_clr); +int iSetHVA_LAT_STS_CFG_cfg_lat_stat_en(unsigned int ucfg_lat_stat_en); +int iSetHVA_WR_BP_CFG_cfg_wr_bp_clr_th(unsigned int ucfg_wr_bp_clr_th); +int iSetHVA_WR_BP_CFG_cfg_wr_bp_th(unsigned int ucfg_wr_bp_th); +int iSetHVA_RD_BP_CFG_cfg_rd_bp_clr_th(unsigned int ucfg_rd_bp_clr_th); +int iSetHVA_RD_BP_CFG_cfg_rd_bp_th(unsigned int ucfg_rd_bp_th); + + +#endif // HI1823_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_reg_offset.h new file mode 100644 index 000000000..6e83f56d3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_reg_offset.h @@ -0,0 +1,110 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hva_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : HVA +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// ****************************************************************************** + +#ifndef HVA_REG_OFFSET_H +#define HVA_REG_OFFSET_H + +/* HVA_REG Base address of Module's Register */ +#define CSR_HVA_REG_BASE (0x43FE000) + +/* **************************************************************************** */ +/* HVA_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HVA_REG_HVA_FPGA_VER_REG (CSR_HVA_REG_BASE + 0x0) /* HVA FPGA版本寄存器 */ +#define CSR_HVA_REG_HVA_EMU_VER_REG (CSR_HVA_REG_BASE + 0x4) /* HVA EMU版本寄存器 */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN0_L_REG (CSR_HVA_REG_BASE + 0xC) /* Memory 属性配置窗口，第一个窗口上限的低32bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN0_H_REG (CSR_HVA_REG_BASE + 0x10) /* Memory 属性配置窗口，第一个窗口上限的高4bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN1_L_REG (CSR_HVA_REG_BASE + 0x14) /* Memory 属性配置窗口，第二个窗口上限的低32bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN1_H_REG (CSR_HVA_REG_BASE + 0x18) /* Memory 属性配置窗口，第二个窗口上限的高4bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN2_L_REG (CSR_HVA_REG_BASE + 0x1C) /* Memory 属性配置窗口，第三个窗口上限的低32bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN2_H_REG (CSR_HVA_REG_BASE + 0x20) /* Memory 属性配置窗口，第三个窗口上限的高4bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN3_L_REG (CSR_HVA_REG_BASE + 0x24) /* Memory 属性配置窗口，第四个窗口上限的低32bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_WIN3_H_REG (CSR_HVA_REG_BASE + 0x28) /* Memory 属性配置窗口，第四个窗口上限的高4bit \ + */ +#define CSR_HVA_REG_HVA_MEM_ATTR_0_REG (CSR_HVA_REG_BASE + 0x30) /* Memory 属性配置 */ +#define CSR_HVA_REG_HVA_MEM_ATTR_1_REG (CSR_HVA_REG_BASE + 0x34) /* Memory 属性配置 */ +#define CSR_HVA_REG_HVA_MEM_ATTR_2_REG (CSR_HVA_REG_BASE + 0x38) /* Memory 属性配置 */ +#define CSR_HVA_REG_HVA_MEM_ATTR_3_REG (CSR_HVA_REG_BASE + 0x3C) /* Memory 属性配置 */ +#define CSR_HVA_REG_HVA_MEM_ATTR_4_REG (CSR_HVA_REG_BASE + 0x40) /* Memory 属性配置 */ +#define CSR_HVA_REG_HVA_AR_CFG_REG (CSR_HVA_REG_BASE + 0x50) /* AXIM 读控制模式 */ +#define CSR_HVA_REG_HVA_WR_CFG_REG (CSR_HVA_REG_BASE + 0x54) /* AXIM 写控制模式 */ +#define CSR_HVA_REG_HVA_ARSTRMID_REG (CSR_HVA_REG_BASE + 0x58) /* ARUSER中STRMID寄存器配置值 */ +#define CSR_HVA_REG_HVA_AWSTRMID_REG (CSR_HVA_REG_BASE + 0x5C) /* AWUSER中STRMID寄存器配置值 */ +#define CSR_HVA_REG_HVA_PEH_ENUM_BAR0_WR_MASK_REG (CSR_HVA_REG_BASE + 0x60) /* 枚举时BAR0写屏蔽信号 */ +#define CSR_HVA_REG_HVA_PEH_ENUM_BAR1_WR_MASK_REG (CSR_HVA_REG_BASE + 0x64) /* 枚举时BAR1写屏蔽信号 */ +#define CSR_HVA_REG_HVA_PEH_ENUM_BAR2_WR_MASK_REG (CSR_HVA_REG_BASE + 0x68) /* 枚举时BAR2写屏蔽信号 */ +#define CSR_HVA_REG_HVA_PEH_ENUM_BAR3_WR_MASK_REG (CSR_HVA_REG_BASE + 0x6C) /* 枚举时BAR3写屏蔽信号 */ +#define CSR_HVA_REG_HVA_PEH_ENUM_BAR4_WR_MASK_REG (CSR_HVA_REG_BASE + 0x70) /* 枚举时BAR4写屏蔽信号 */ +#define CSR_HVA_REG_HVA_PEH_ENUM_BAR5_WR_MASK_REG (CSR_HVA_REG_BASE + 0x74) /* 枚举时BAR5写屏蔽信号 */ +#define CSR_HVA_REG_HVA_PEH_FEATURE_EN_REG (CSR_HVA_REG_BASE + 0x78) /* PEH feature 配置 */ +#define CSR_HVA_REG_HVA_PF_CMD_TYPE_REG (CSR_HVA_REG_BASE + 0x7C) /* 对应PFSMMU USER中CMD_TYPE的配置寄存器 */ +#define CSR_HVA_REG_HVA_INT_STARUS_REG (CSR_HVA_REG_BASE + 0x80) /* HVA中断状态寄存器 */ +#define CSR_HVA_REG_HVA_INT_EN_REG (CSR_HVA_REG_BASE + 0x84) /* HVA中断使能寄存器 */ +#define CSR_HVA_REG_HVA_INT_SET_REG (CSR_HVA_REG_BASE + 0x88) /* HVA软件模拟中断寄存器 */ +#define CSR_HVA_REG_HVA_INT_RAW_STATUS_REG (CSR_HVA_REG_BASE + 0x8C) /* HVA原始中断状态寄存器 */ +#define CSR_HVA_REG_HVA_AXI_ERR_MSK_REG (CSR_HVA_REG_BASE + 0x90) /* HVA模块AXI总线返回错误屏蔽 */ +#define CSR_HVA_REG_HVA_AXI_MAX_TRANS_REG (CSR_HVA_REG_BASE + 0xA0) /* HVA模块能够发出去AXI transaction的最大数量 */ +#define CSR_HVA_REG_HVA_CPI_CFG_REG (CSR_HVA_REG_BASE + 0xB0) /* HVA配置CPI Function属性 */ +#define CSR_HVA_REG_HVA_CPI_CRDT_CFG_REG (CSR_HVA_REG_BASE + 0xB4) /* HVA接收CPI TLP报文的信用配置 */ +#define CSR_HVA_REG_HVA_RAM_ECC_BYPASS_REG (CSR_HVA_REG_BASE + 0xB8) /* HVA RAM ECC校验bypass配置寄存器 */ +#define CSR_HVA_REG_HVA_RAM_ECC_ERR_INS_REG (CSR_HVA_REG_BASE + 0xBC) /* HVA RAM ECC注错 */ +#define CSR_HVA_REG_HVA_FATAL_ERR_CTRL_REG (CSR_HVA_REG_BASE + 0xC0) /* HVA 致命错误控制 */ +#define CSR_HVA_REG_HVA_INNER_CRDT_REG (CSR_HVA_REG_BASE + 0xC4) /* HVA内部信用配置 */ +#define CSR_HVA_REG_HVA_FIFO_AF_CFG_REG (CSR_HVA_REG_BASE + 0xC8) /* HVA内部将满水线配置寄存器 */ +#define CSR_HVA_REG_HVA_BD_CFG_PF_NUM_REG (CSR_HVA_REG_BASE + 0xCC) /* 后面配置ECAM空间的Function号 */ +#define CSR_HVA_REG_HVA_FLR_STA_REG (CSR_HVA_REG_BASE + 0xD0) /* HVA FLR装态寄存器 */ +#define CSR_HVA_REG_HVA_DFX_CFG_REG (CSR_HVA_REG_BASE + 0x200) /* DFX配置寄存器 */ +#define CSR_HVA_REG_HVA_DFX_CPL_BW0_REG (CSR_HVA_REG_BASE + 0x210) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_REG_HVA_DFX_CPL_BW1_REG (CSR_HVA_REG_BASE + 0x220) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_REG_HVA_DFX_NPQ_DB_STATE_REG (CSR_HVA_REG_BASE + 0x230) /* NPQ databuffer状态寄存器 */ +#define CSR_HVA_REG_HVA_DFX_TX_CPL_CNT0_REG (CSR_HVA_REG_BASE + 0x240) /* HVA返回完成包数量统计 */ +#define CSR_HVA_REG_HVA_DFX_TX_CPL_CNT1_REG (CSR_HVA_REG_BASE + 0x250) /* HVA返回完成包数量统计 */ +#define CSR_HVA_REG_HVA_NPQ_PTR_REG (CSR_HVA_REG_BASE + 0x260) /* HVA NPQ的指针信息 */ +#define CSR_HVA_REG_HVA_DFX_P_BW0_REG (CSR_HVA_REG_BASE + 0x270) /* P报文带宽统计寄存器 */ +#define CSR_HVA_REG_HVA_DFX_P_BW1_REG (CSR_HVA_REG_BASE + 0x280) /* P报文带宽统计寄存器 */ +#define CSR_HVA_REG_HVA_DFX_P_CNT_REG (CSR_HVA_REG_BASE + 0x290) /* 接收P报文数量统计 */ +#define CSR_HVA_REG_HVA_DFX_PQ_PTR_REG (CSR_HVA_REG_BASE + 0x2A0) /* HVA PQ的指针信息 */ +#define CSR_HVA_REG_HVA_DFX_PQ_WR_ERR_REG (CSR_HVA_REG_BASE + 0x2B0) /* HVA PQ转换为AXI写返回错误 */ +#define CSR_HVA_REG_HVA_DFX_PQ_WR_ERR_ADDR_H_REG (CSR_HVA_REG_BASE + 0x2C0) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_REG_HVA_DFX_PQ_WR_ERR_ADDR_L_REG (CSR_HVA_REG_BASE + 0x2D0) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_REG_HVA_DFX_TLP_ZERO_LEN_REG (CSR_HVA_REG_BASE + 0x2E0) /* HVA接收到ZERO LENGTH操作的TLP报文 */ +#define CSR_HVA_REG_HVA_DFX_AXI_BID_ERR_REG (CSR_HVA_REG_BASE + 0x2F0) /* HVA接收到一个非法的bid */ +#define CSR_HVA_REG_HVA_DFX_DB_ECC_ERR_ADDR_REG (CSR_HVA_REG_BASE + 0x300) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_REG_HVA_DFX_ENTRY_ECC_ERR_ADDR_REG (CSR_HVA_REG_BASE + 0x310) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_REG_HVA_DFX_MEM_CERR_CNT_REG (CSR_HVA_REG_BASE + 0x320) /* HVA中memory发生可纠错误的次数统计 */ +#define CSR_HVA_REG_HVA_DFX_MEM_UCERR_CNT_REG (CSR_HVA_REG_BASE + 0x324) /* HVA中memory发生不可纠错误的次数统计 */ +#define CSR_HVA_REG_HVA_DFX_ECC_STA_REG (CSR_HVA_REG_BASE + 0x330) /* HVA中memory ECC错误状态 */ +#define CSR_HVA_REG_HVA_OP_BAR_ADDR_ERR_REG (CSR_HVA_REG_BASE + 0x3A0) /* 访问BAR的地址出错 */ +#define CSR_HVA_REG_HVA_OP_BAR_ADDR_ERR_CNT_REG (CSR_HVA_REG_BASE + 0x3A4) /* 访问BAR的地址出错次数统计 */ +#define CSR_HVA_REG_CPI_HVA_REQ_TLP_NUM_REG (CSR_HVA_REG_BASE + 0x3A8) /* CPI送给HVA请求TLP数量统计 */ +#define CSR_HVA_REG_HVA_CPI_REQ_TLP_NUM_REG (CSR_HVA_REG_BASE + 0x3AC) /* HVA送给CPI请求TLP数量统计 */ +#define CSR_HVA_REG_CPL_TLP_NUM_REG (CSR_HVA_REG_BASE + 0x3B0) /* 完成包数量统计 */ +#define CSR_HVA_REG_HVA_SMMU_AXI_RD_NUM_REG (CSR_HVA_REG_BASE + 0x3B4) /* HVA与SMMU之间AXI读请求及其返回数量统计 */ +#define CSR_HVA_REG_HVA_SMMU_AXI_WR_NUM_REG (CSR_HVA_REG_BASE + 0x3B8) /* HVA与SMMU之间AXI写请求数量统计 */ +#define CSR_HVA_REG_HVA_AXI_B_NUM_REG (CSR_HVA_REG_BASE + 0x3BC) /* AXI写响应数量统计 */ +#define CSR_HVA_REG_DISP_HVA_AXI_RD_NUM_REG (CSR_HVA_REG_BASE + 0x3C0) /* HVA与Dispatch之间AXI读请求及其返回数量统计 \ + */ +#define CSR_HVA_REG_DISP_HVA_AXI_WR_NUM_REG (CSR_HVA_REG_BASE + 0x3C4) /* HVA与Dispatch之间AXI写请求数量统计 */ +#define CSR_HVA_REG_HVA_CPI_CPL_TNUM_REG (CSR_HVA_REG_BASE + 0x3C8) /* HVA返回CPI完成包数量统计 */ +#define CSR_HVA_REG_MSI_LEN_ERR_REG (CSR_HVA_REG_BASE + 0x3CC) /* CPI送给HVA的MSI/MSIX报文的长度或者DW_BE填充错误 */ +#define CSR_HVA_REG_HVA_LAT_STS_CFG_REG (CSR_HVA_REG_BASE + 0x400) /* 时延检测控制寄存器 */ +#define CSR_HVA_REG_HVA_WR_BP_CFG_REG (CSR_HVA_REG_BASE + 0x404) /* 写报文延时反压阈值配置寄存器 */ +#define CSR_HVA_REG_HVA_RD_BP_CFG_REG (CSR_HVA_REG_BASE + 0x408) /* 读报文延时反压阈值配置寄存器 */ + +#endif // HI1823_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_sm23_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_sm23_c_union_define.h new file mode 100644 index 000000000..2c0a47b06 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_sm23_c_union_define.h @@ -0,0 +1,43 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hva_sm23_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : V100 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/04/28 10:26:56 Create file +// ****************************************************************************** + +#ifndef HVA_SM23_C_UNION_DEFINE_H +#define HVA_SM23_C_UNION_DEFINE_H + +/* Define the union csr_disp_ecam_daw0_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int disp_ecam_daw0_pcie_dev_id : 8; /* [7:0] */ + unsigned int disp_ecam_daw0_pcie_bus_id : 8; /* [15:8] */ + unsigned int disp_ecam_daw0_size : 5; /* [20:16] */ + unsigned int rsv_0 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + unsigned int value; +} csr_disp_ecam_daw0_addr_u; + +/* Define the union csr_disp_ecam_daw0_did_u */ +typedef union { + /* Define the struct bits */ + struct { + unsigned int disp_ecam_daw0_did : 3; /* [2:0] */ + unsigned int rsv_1 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + unsigned int value; +} csr_disp_ecam_daw0_did_u; + +#endif // HVA_SM23_C_UNION_DEFINE_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_sm23_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_sm23_reg_offset.h new file mode 100644 index 000000000..2fda55735 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_sm23_reg_offset.h @@ -0,0 +1,37 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hva_sm23_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : V100 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/04/27 22:45:56 Create file +// ****************************************************************************** + +#ifndef HVA_SM23_REG_OFFSET_H +#define HVA_SM23_REG_OFFSET_H + +/* NIMBUS Base address of Module's Register */ +#define DISP_HVA_SM23_BASE (0x0) + +/* **************************************************************************** */ +/* Phosphor NIMBUS Registers' Definitions */ +/* **************************************************************************** */ + +#define DISP_DEF_EP_RC0 (DISP_HVA_SM23_BASE + 0x4) /* ��PBU(ֱ��EP)Default��DID��Ϣ���üĴ��� */ +#define DISP_DEF_EP_RC1 (DISP_HVA_SM23_BASE + 0x8) /* ��PBU(ֱ��EP)Default��DID��Ϣ���üĴ��� */ + +#define DISP_DAW_VF_CTRL (DISP_HVA_SM23_BASE + 0xc0) /* DAW��VF���ÿ��ƼĴ��� */ + +#define DISP_RC0_BASE_ADDR (DISP_HVA_SM23_BASE + 0x400) /* PCIE RC0 DAW��ʼ��ַ���� */ +#define DISP_RC0_LIMIT_ADDR (DISP_HVA_SM23_BASE + 0x404) /* PCIE RC0 DAW ������ַ���� */ +#define DISP_RC1_BASE_ADDR (DISP_HVA_SM23_BASE + 0x408) /* PCIE RC1 DAW��ʼ��ַ���� */ +#define DISP_RC1_LIMIT_ADDR (DISP_HVA_SM23_BASE + 0x40c) /* PCIE RC1 DAW ������ַ���� */ + +#define DISP_ECAM_DAW0_ADDR_REG (DISP_HVA_SM23_BASE + 0x500) /* ����PCIE���豸ECAM�ռ�DAW0���ڵ�ַ�Ĵ��� */ +#define DISP_ECAM_DAW0_DID_REG (DISP_HVA_SM23_BASE + 0x504) /* ����PCIE���豸ECAM�ռ�DAW0����DID���üĴ��� */ + +#endif // HVA_SM23_REG_OFFSET_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_smf_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_smf_c_union_define.h new file mode 100644 index 000000000..14f4bce00 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_smf_c_union_define.h @@ -0,0 +1,1194 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hva_smf_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : HVA_SMF +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// ****************************************************************************** + +#ifndef HVA_SMF_C_UNION_DEFINE_H +#define HVA_SMF_C_UNION_DEFINE_H + +/* Define the union csr_hva_smf_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_fpga_ver_u; + +/* Define the union csr_hva_smf_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_emu_ver_u; + +/* Define the union csr_hva_smf_mem_attr_win0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win0_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win0_l_u; + +/* Define the union csr_hva_smf_mem_attr_win0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win0_h : 4; /* [3:0] */ + u32 rsv_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win0_h_u; + +/* Define the union csr_hva_smf_mem_attr_win1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win1_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win1_l_u; + +/* Define the union csr_hva_smf_mem_attr_win1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win1_h : 4; /* [3:0] */ + u32 rsv_1 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win1_h_u; + +/* Define the union csr_hva_smf_mem_attr_win2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win2_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win2_l_u; + +/* Define the union csr_hva_smf_mem_attr_win2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win2_h : 4; /* [3:0] */ + u32 rsv_2 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win2_h_u; + +/* Define the union csr_hva_smf_mem_attr_win3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win3_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win3_l_u; + +/* Define the union csr_hva_smf_mem_attr_win3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_win3_h : 4; /* [3:0] */ + u32 rsv_3 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_win3_h_u; + +/* Define the union csr_hva_smf_mem_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_attr_rd : 5; /* [4:0] */ + u32 rsv_4 : 3; /* [7:5] */ + u32 hva_smf_mem_attr_wr : 5; /* [12:8] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_attr_u; + +/* Define the union csr_hva_smf_ar_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_cfg_arqos_set : 4; /* [3:0] */ + u32 hva_smf_cfg_arssv_set : 1; /* [4] */ + u32 hva_smf_cfg_arstrmid_mode : 1; /* [5] */ + u32 rsv_6 : 2; /* [7:6] */ + u32 hva_smf_cfg_rdcln_thrld : 4; /* [11:8] */ + u32 hva_smf_cfg_rdfna_thrld : 4; /* [15:12] */ + u32 hva_smf_cfg_rdtype_thrld : 4; /* [19:16] */ + u32 hva_smf_cfg_rdfa_thrld : 4; /* [23:20] */ + u32 hva_smf_cfg_rd_fa_mode : 2; /* [25:24] */ + u32 hva_smf_cfg_rd_fna_mode : 2; /* [27:26] */ + u32 hva_smf_cfg_rd_cln_mode : 1; /* [28] */ + u32 hva_smf_cfg_rd_type_mode : 1; /* [29] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_ar_cfg_u; + +/* Define the union csr_hva_smf_wr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_cfg_awqos_set : 4; /* [3:0] */ + u32 hva_smf_cfg_awssv_set : 1; /* [4] */ + u32 hva_smf_cfg_awstrmid_mode : 1; /* [5] */ + u32 rsv_8 : 2; /* [7:6] */ + u32 hva_smf_cfg_wr_so_set : 4; /* [11:8] */ + u32 hva_smf_cfg_wrfna_thrld : 4; /* [15:12] */ + u32 hva_smf_cfg_wrtype_thrld : 4; /* [19:16] */ + u32 hva_smf_cfg_wrfa_thrld : 4; /* [23:20] */ + u32 hva_smf_cfg_wr_fa_mode : 2; /* [25:24] */ + u32 hva_smf_cfg_wr_fna_mode : 2; /* [27:26] */ + u32 hva_smf_cfg_wr_fp_mode : 2; /* [29:28] */ + u32 hva_smf_cfg_wr_type_mode : 1; /* [30] */ + u32 hva_smf_cfg_wr_so_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_wr_cfg_u; + +/* Define the union csr_hva_smf_arstrmid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_rd_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_arstrmid_u; + +/* Define the union csr_hva_smf_awstrmid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_wr_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_awstrmid_u; + +/* Define the union csr_hva_smf_pf_cmd_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_cfg_pf_cmd_type : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_pf_cmd_type_u; + +/* Define the union csr_hva_smf_int_starus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_ov_int_status : 1; /* [0] */ + u32 hva_smf_npq_uf_int_status : 1; /* [1] */ + u32 hva_smf_npq_send_empty_int_status : 1; /* [2] */ + u32 hva_smf_pq_ov_int_status : 1; /* [3] */ + u32 hva_smf_pq_uf_int_status : 1; /* [4] */ + u32 hva_smf_pq_send_empty_int_status : 1; /* [5] */ + u32 hva_smf_1bit_ecc_int_status : 1; /* [6] */ + u32 hva_smf_2bit_ecc_int_status : 1; /* [7] */ + u32 hva_cpth_fifo_ov_int_status : 1; /* [8] */ + u32 rsv_10 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_int_starus_u; + +/* Define the union csr_hva_smf_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_ov_int_en : 1; /* [0] */ + u32 hva_smf_npq_uf_int_en : 1; /* [1] */ + u32 hva_smf_npq_send_empty_int_en : 1; /* [2] */ + u32 hva_smf_pq_ov_int_en : 1; /* [3] */ + u32 hva_smf_pq_uf_int_en : 1; /* [4] */ + u32 hva_smf_pq_send_empty_int_en : 1; /* [5] */ + u32 hva_smf_1bit_ecc_int_en : 1; /* [6] */ + u32 hva_smf_2bit_ecc_int_en : 1; /* [7] */ + u32 hva_cpth_fifo_ov_int_en : 1; /* [8] */ + u32 rsv_11 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_int_en_u; + +/* Define the union csr_hva_smf_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_ov_int_set : 1; /* [0] */ + u32 hva_smf_npq_uf_int_set : 1; /* [1] */ + u32 hva_smf_npq_send_empty_int_set : 1; /* [2] */ + u32 hva_smf_pq_ov_int_set : 1; /* [3] */ + u32 hva_smf_pq_uf_int_set : 1; /* [4] */ + u32 hva_smf_pq_send_empty_int_set : 1; /* [5] */ + u32 hva_smf_1bit_ecc_int_set : 1; /* [6] */ + u32 hva_smf_2bit_ecc_int_set : 1; /* [7] */ + u32 hva_cpth_fifo_ov_int_set : 1; /* [8] */ + u32 rsv_12 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_int_set_u; + +/* Define the union csr_hva_smf_int_raw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_ov_int_raw_status : 1; /* [0] */ + u32 hva_smf_npq_uf_int_raw_status : 1; /* [1] */ + u32 hva_smf_npq_send_empty_int_raw_status : 1; /* [2] */ + u32 hva_smf_pq_ov_int_raw_status : 1; /* [3] */ + u32 hva_smf_pq_uf_int_raw_status : 1; /* [4] */ + u32 hva_smf_pq_send_empty_int_raw_status : 1; /* [5] */ + u32 hva_smf_1bit_ecc_int_raw_status : 1; /* [6] */ + u32 hva_smf_2bit_ecc_int_raw_status : 1; /* [7] */ + u32 hva_cpth_fifo_ov_int_raw_status : 1; /* [8] */ + u32 rsv_13 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_int_raw_status_u; + +/* Define the union csr_hva_icl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sc_dispatch_errrsp : 1; /* [0] */ + u32 rsv_14 : 15; /* [15:1] */ + u32 hva_icl_smmu_bdf : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_icl_cfg_u; + +/* Define the union csr_hva_smf_axi_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_cfg_rd_max_trans : 8; /* [7:0] */ + u32 hva_smf_cfg_wr_max_trans : 8; /* [15:8] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_axi_max_trans_u; + +/* Define the union csr_hva_smf_cpi_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_cpi_10bit_tag_req_en : 1; /* [0] */ + u32 hva_smf_cpi_10bit_tag_cpl_en : 1; /* [1] */ + u32 hva_smf_cpi_extended_tag_en : 1; /* [2] */ + u32 hva_smf_cpi_cpl_timeout_dis : 1; /* [3] */ + u32 hva_smf_cpi_cpl_timeout_value : 4; /* [7:4] */ + u32 hva_smf_cpi_cfg_mrrs : 3; /* [10:8] */ + u32 rsv_16 : 1; /* [11] */ + u32 hva_smf_cpi_cfg_mps : 3; /* [14:12] */ + u32 rsv_17 : 1; /* [15] */ + u32 hva_smf_link_down : 1; /* [16] */ + u32 hva_smf_cpi_tx_crd_active_en : 1; /* [17] */ + u32 rsv_18 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_cpi_cfg_u; + +/* Define the union csr_hva_smf_cpi_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_cpi_p_hed_crdt : 8; /* [7:0] */ + u32 hva_smf_cpi_p_dat_crdt : 8; /* [15:8] */ + u32 hva_smf_cpi_np_hed_crdt : 8; /* [23:16] */ + u32 rsv_19 : 7; /* [30:24] */ + u32 hva_smf_cpi_crdt_init : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_cpi_crdt_cfg_u; + +/* Define the union csr_hva_smf_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_ram_err_chk_bypass : 1; /* [0] */ + u32 rsv_20 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_ram_ecc_bypass_u; + +/* Define the union csr_hva_smf_ram_ecc_err_ins_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_db_ram_cerr_ins_req : 1; /* [0] */ + u32 hva_smf_npq_db_ram_ucerr_ins_req : 1; /* [1] */ + u32 hva_smf_pq_db_ram_cerr_ins_req : 1; /* [2] */ + u32 hva_smf_pq_db_ram_ucerr_ins_req : 1; /* [3] */ + u32 hva_smf_npq_entry_ram_cerr_ins_req : 1; /* [4] */ + u32 hva_smf_npq_entry_ram_ucerr_ins_req : 1; /* [5] */ + u32 hva_smf_pq_entry_ram_cerr_ins_req : 1; /* [6] */ + u32 hva_smf_pq_entry_ram_ucerr_ins_req : 1; /* [7] */ + u32 hva_cpth_fifo_ram_cerr_ins_req : 1; /* [8] */ + u32 hva_cpth_fifo_ram_ucerr_ins_req : 1; /* [9] */ + u32 rsv_21 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_ram_ecc_err_ins_u; + +/* Define the union csr_hva_smf_fatal_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_db_ram_ucerr_fatal_en : 1; /* [0] */ + u32 hva_smf_pq_db_ram_ucerr_fatal_en : 1; /* [1] */ + u32 hva_smf_npq_entry_ram_ucerr_fatal_en : 1; /* [2] */ + u32 hva_smf_pq_entry_ram_ucerr_fatal_en : 1; /* [3] */ + u32 hva_smf_npq_ov_fatal_en : 1; /* [4] */ + u32 hva_smf_npq_uf_fatal_en : 1; /* [5] */ + u32 hva_smf_npq_send_empty_fatal_en : 1; /* [6] */ + u32 hva_smf_pq_ov_fatal_en : 1; /* [7] */ + u32 hva_smf_pq_uf_fatal_en : 1; /* [8] */ + u32 hva_smf_pq_send_empty_fatal_en : 1; /* [9] */ + u32 hva_cpth_fifo_ram_ucerr_fatal_en : 1; /* [10] */ + u32 hva_cpth_fifo_ov_fatal_en : 1; /* [11] */ + u32 rsv_22 : 19; /* [30:12] */ + u32 hva_smf_fatal_err_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_fatal_err_ctrl_u; + +/* Define the union csr_hva_smf_inner_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_inner_cpl_data_crdt : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 hva_smf_inner_send_npq_crdt : 3; /* [6:4] */ + u32 rsv_24 : 1; /* [7] */ + u32 hva_smf_inner_send_pq_crdt : 3; /* [10:8] */ + u32 rsv_25 : 20; /* [30:11] */ + u32 hva_smf_inner_crdt_init : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_inner_crdt_u; + +/* Define the union csr_hva_smf_fifo_af_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_pq_sdata_fifo_af_th : 4; /* [3:0] */ + u32 rsv_26 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_fifo_af_cfg_u; + +/* Define the union csr_hva_smf_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_rsp_crdt : 5; /* [4:0] */ + u32 rsv_27 : 3; /* [7:5] */ + u32 hva_smf_cpl_crdt : 3; /* [10:8] */ + u32 rsv_28 : 5; /* [15:11] */ + u32 hva_smf_crdt_init : 1; /* [16] */ + u32 rsv_29 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_crdt_u; + +/* Define the union csr_hva_smf_pnp_odr_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_cpth_pnp_odr_dis : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_pnp_odr_dis_u; + +/* Define the union csr_hva_smf_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_cpl_stat_en : 1; /* [0] */ + u32 hva_smf_dfx_tx_cpl_stat_clr : 1; /* [1] */ + u32 hva_smf_dfx_tx_cpl_cnt_clr : 1; /* [2] */ + u32 hva_smf_dfx_hva_get_cpi_p_cnt_clr : 1; /* [3] */ + u32 hva_smf_dfx_tx_p_stat_en : 1; /* [4] */ + u32 hva_smf_dfx_tx_p_stat_clr : 1; /* [5] */ + u32 hva_smf_dfx_ucerr_cnt_clr : 1; /* [6] */ + u32 hva_smf_dfx_cerr_cnt_clr : 1; /* [7] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_cfg_u; + +/* Define the union csr_hva_smf_dfx_cpl_bw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_cpl_bw_curr : 16; /* [15:0] */ + u32 hva_smf_dfx_tx_cpl_bw_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_cpl_bw0_u; + +/* Define the union csr_hva_smf_dfx_cpl_bw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_cpl_bw_ava : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_cpl_bw1_u; + +/* Define the union csr_hva_smf_dfx_npq_db_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_npq_db_state : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_npq_db_state_u; + +/* Define the union csr_hva_smf_dfx_tx_cpl_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_cpl_dat_err_cnt : 16; /* [15:0] */ + u32 hva_smf_dfx_tx_cpl_unsuccess_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_tx_cpl_cnt0_u; + +/* Define the union csr_hva_smf_dfx_tx_cpl_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_tx_cpl_cnt1_u; + +/* Define the union csr_hva_smf_npq_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_npq_send_ptr : 8; /* [7:0] */ + u32 hva_smf_dfx_npq_free_ptr : 8; /* [15:8] */ + u32 hva_smf_dfx_npq_rls_ptr : 8; /* [23:16] */ + u32 hva_smf_dfx_npq_free_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_npq_ptr_u; + +/* Define the union csr_hva_smf_dfx_p_bw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_p_bw_curr : 16; /* [15:0] */ + u32 hva_smf_dfx_tx_p_bw_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_p_bw0_u; + +/* Define the union csr_hva_smf_dfx_p_bw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_tx_p_bw_ava : 16; /* [15:0] */ + u32 rsv_32 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_p_bw1_u; + +/* Define the union csr_hva_smf_dfx_p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_hva_get_cpi_p_cnt : 16; /* [15:0] */ + u32 rsv_33 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_p_cnt_u; + +/* Define the union csr_hva_smf_dfx_pq_ptr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_pq_send_ptr : 8; /* [7:0] */ + u32 hva_smf_dfx_pq_free_ptr : 8; /* [15:8] */ + u32 hva_smf_dfx_pq_rls_ptr : 8; /* [23:16] */ + u32 hva_smf_dfx_pq_free_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_pq_ptr_u; + +/* Define the union csr_hva_smf_dfx_pq_wr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_34 : 16; /* [15:0] */ + u32 hva_smf_dfx_pq_wr_err_abresp : 1; /* [16] */ + u32 hva_smf_dfx_pq_wr_err : 1; /* [17] */ + u32 hva_smf_dfx_pq_wr_err_clr : 1; /* [18] */ + u32 rsv_35 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_pq_wr_err_u; + +/* Define the union csr_hva_smf_dfx_pq_wr_err_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_pq_wr_err_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_pq_wr_err_addr_h_u; + +/* Define the union csr_hva_smf_dfx_pq_wr_err_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_pq_wr_err_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_pq_wr_err_addr_l_u; + +/* Define the union csr_hva_smf_dfx_tlp_zero_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_pq_zero_write : 1; /* [0] */ + u32 hva_smf_dfx_npq_zero_read : 1; /* [1] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_tlp_zero_len_u; + +/* Define the union csr_hva_smf_dfx_axi_bid_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_hva_bid_err : 1; /* [0] */ + u32 rsv_37 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_axi_bid_err_u; + +/* Define the union csr_hva_smf_dfx_db_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_pq_db_ecc_err_addr : 5; /* [4:0] */ + u32 rsv_38 : 11; /* [15:5] */ + u32 hva_smf_dfx_npq_db_ecc_err_addr : 9; /* [24:16] */ + u32 rsv_39 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_db_ecc_err_addr_u; + +/* Define the union csr_hva_smf_dfx_entry_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_pq_entry_ecc_err_addr : 7; /* [6:0] */ + u32 rsv_40 : 1; /* [7] */ + u32 hva_smf_dfx_npq_entry_ecc_err_addr : 7; /* [14:8] */ + u32 rsv_41 : 1; /* [15] */ + u32 hva_smf_dfx_cpth_fifo_ecc_err_addr : 6; /* [21:16] */ + u32 rsv_42 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_entry_ecc_err_addr_u; + +/* Define the union csr_hva_smf_dfx_mem_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_mem_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_mem_cerr_cnt_u; + +/* Define the union csr_hva_smf_dfx_mem_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_dfx_mem_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_mem_ucerr_cnt_u; + +/* Define the union csr_hva_smf_dfx_ecc_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_npq_db_ram_cerr : 1; /* [0] */ + u32 hva_smf_npq_db_ram_ucerr : 1; /* [1] */ + u32 hva_smf_pq_db_ram_cerr : 1; /* [2] */ + u32 hva_smf_pq_db_ram_ucerr : 1; /* [3] */ + u32 hva_smf_npq_entry_ram_cerr : 1; /* [4] */ + u32 hva_smf_npq_entry_ram_ucerr : 1; /* [5] */ + u32 hva_smf_pq_entry_ram_cerr : 1; /* [6] */ + u32 hva_smf_pq_entry_ram_ucerr : 1; /* [7] */ + u32 hva_cpth_fifo_ram_cerr : 1; /* [8] */ + u32 hva_cpth_fifo_ram_ucerr : 1; /* [9] */ + u32 rsv_43 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_dfx_ecc_sta_u; + +/* Define the union csr_hva_smf_mem_ctrl_bus_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_ctrl_bus_0_u; + +/* Define the union csr_hva_smf_mem_ctrl_bus_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_ctrl_bus_1_u; + +/* Define the union csr_hva_smf_mem_ctrl_bus_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_ctrl_bus_2_u; + +/* Define the union csr_hva_smf_mem_ctrl_bus_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_ctrl_bus_3_u; + +/* Define the union csr_hva_smf_mem_ctrl_bus_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_smf_mem_ctrl_bus_4 : 6; /* [5:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_mem_ctrl_bus_4_u; + +/* Define the union csr_smf_hva_req_api_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_smf_hva_wr_requs_cnt : 16; /* [15:0] */ + u32 dfx_smf_hva_rd_requs_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_hva_req_api_num_u; + +/* Define the union csr_hva_smf_rsp_api_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_smf_rd_rsp_cnt : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_rsp_api_num_u; + +/* Define the union csr_hva_smf_smmu_axi_rd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_smmu_hva_rl_cnt : 16; /* [15:0] */ + u32 dfx_hva_smmu_ar_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_smmu_axi_rd_num_u; + +/* Define the union csr_hva_smf_smmu_axi_wr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_hva_smmu_wl_cnt : 16; /* [15:0] */ + u32 dfx_hva_smmu_aw_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_smmu_axi_wr_num_u; + +/* Define the union csr_smmu_hva_axi_b_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_smmu_hva_b_cnt : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_hva_axi_b_num_u; + +/* Define the union csr_hva_smf_lat_sts_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lat_stat_clr : 1; /* [0] */ + u32 cfg_lat_stat_en : 1; /* [1] */ + u32 rsv_44 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_lat_sts_cfg_u; + +/* Define the union csr_hva_smf_wr_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_wr_bp_clr_th : 16; /* [15:0] */ + u32 cfg_wr_bp_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_wr_bp_cfg_u; + +/* Define the union csr_hva_smf_rd_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rd_bp_clr_th : 16; /* [15:0] */ + u32 cfg_rd_bp_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_smf_rd_bp_cfg_u; + +/* Define the union csr_hva_jam_time_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_jam_bp_bus_timer : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hva_jam_time_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hva_smf_fpga_ver_u hva_smf_fpga_ver; /* 0 */ + volatile csr_hva_smf_emu_ver_u hva_smf_emu_ver; /* 4 */ + volatile csr_hva_smf_mem_attr_win0_l_u hva_smf_mem_attr_win0_l; /* C */ + volatile csr_hva_smf_mem_attr_win0_h_u hva_smf_mem_attr_win0_h; /* 10 */ + volatile csr_hva_smf_mem_attr_win1_l_u hva_smf_mem_attr_win1_l; /* 14 */ + volatile csr_hva_smf_mem_attr_win1_h_u hva_smf_mem_attr_win1_h; /* 18 */ + volatile csr_hva_smf_mem_attr_win2_l_u hva_smf_mem_attr_win2_l; /* 1C */ + volatile csr_hva_smf_mem_attr_win2_h_u hva_smf_mem_attr_win2_h; /* 20 */ + volatile csr_hva_smf_mem_attr_win3_l_u hva_smf_mem_attr_win3_l; /* 24 */ + volatile csr_hva_smf_mem_attr_win3_h_u hva_smf_mem_attr_win3_h; /* 28 */ + volatile csr_hva_smf_mem_attr_u hva_smf_mem_attr[5]; /* 30 */ + volatile csr_hva_smf_ar_cfg_u hva_smf_ar_cfg; /* 50 */ + volatile csr_hva_smf_wr_cfg_u hva_smf_wr_cfg; /* 54 */ + volatile csr_hva_smf_arstrmid_u hva_smf_arstrmid; /* 58 */ + volatile csr_hva_smf_awstrmid_u hva_smf_awstrmid; /* 5C */ + volatile csr_hva_smf_pf_cmd_type_u hva_smf_pf_cmd_type; /* 7C */ + volatile csr_hva_smf_int_starus_u hva_smf_int_starus; /* 80 */ + volatile csr_hva_smf_int_en_u hva_smf_int_en; /* 84 */ + volatile csr_hva_smf_int_set_u hva_smf_int_set; /* 88 */ + volatile csr_hva_smf_int_raw_status_u hva_smf_int_raw_status; /* 8C */ + volatile csr_hva_icl_cfg_u hva_icl_cfg; /* 90 */ + volatile csr_hva_smf_axi_max_trans_u hva_smf_axi_max_trans; /* A0 */ + volatile csr_hva_smf_cpi_cfg_u hva_smf_cpi_cfg; /* B0 */ + volatile csr_hva_smf_cpi_crdt_cfg_u hva_smf_cpi_crdt_cfg; /* B4 */ + volatile csr_hva_smf_ram_ecc_bypass_u hva_smf_ram_ecc_bypass; /* B8 */ + volatile csr_hva_smf_ram_ecc_err_ins_u hva_smf_ram_ecc_err_ins; /* BC */ + volatile csr_hva_smf_fatal_err_ctrl_u hva_smf_fatal_err_ctrl; /* C0 */ + volatile csr_hva_smf_inner_crdt_u hva_smf_inner_crdt; /* C4 */ + volatile csr_hva_smf_fifo_af_cfg_u hva_smf_fifo_af_cfg; /* C8 */ + volatile csr_hva_smf_crdt_u hva_smf_crdt; /* CC */ + volatile csr_hva_smf_pnp_odr_dis_u hva_smf_pnp_odr_dis; /* D0 */ + volatile csr_hva_smf_dfx_cfg_u hva_smf_dfx_cfg; /* 200 */ + volatile csr_hva_smf_dfx_cpl_bw0_u hva_smf_dfx_cpl_bw0[4]; /* 210 */ + volatile csr_hva_smf_dfx_cpl_bw1_u hva_smf_dfx_cpl_bw1[4]; /* 220 */ + volatile csr_hva_smf_dfx_npq_db_state_u hva_smf_dfx_npq_db_state[4]; /* 230 */ + volatile csr_hva_smf_dfx_tx_cpl_cnt0_u hva_smf_dfx_tx_cpl_cnt0[4]; /* 240 */ + volatile csr_hva_smf_dfx_tx_cpl_cnt1_u hva_smf_dfx_tx_cpl_cnt1[4]; /* 250 */ + volatile csr_hva_smf_npq_ptr_u hva_smf_npq_ptr[4]; /* 260 */ + volatile csr_hva_smf_dfx_p_bw0_u hva_smf_dfx_p_bw0[4]; /* 270 */ + volatile csr_hva_smf_dfx_p_bw1_u hva_smf_dfx_p_bw1[4]; /* 280 */ + volatile csr_hva_smf_dfx_p_cnt_u hva_smf_dfx_p_cnt[4]; /* 290 */ + volatile csr_hva_smf_dfx_pq_ptr_u hva_smf_dfx_pq_ptr[4]; /* 2A0 */ + volatile csr_hva_smf_dfx_pq_wr_err_u hva_smf_dfx_pq_wr_err[4]; /* 2B0 */ + volatile csr_hva_smf_dfx_pq_wr_err_addr_h_u hva_smf_dfx_pq_wr_err_addr_h[4]; /* 2C0 */ + volatile csr_hva_smf_dfx_pq_wr_err_addr_l_u hva_smf_dfx_pq_wr_err_addr_l[4]; /* 2D0 */ + volatile csr_hva_smf_dfx_tlp_zero_len_u hva_smf_dfx_tlp_zero_len; /* 2E0 */ + volatile csr_hva_smf_dfx_axi_bid_err_u hva_smf_dfx_axi_bid_err; /* 2F0 */ + volatile csr_hva_smf_dfx_db_ecc_err_addr_u hva_smf_dfx_db_ecc_err_addr[4]; /* 300 */ + volatile csr_hva_smf_dfx_entry_ecc_err_addr_u hva_smf_dfx_entry_ecc_err_addr[4]; /* 310 */ + volatile csr_hva_smf_dfx_mem_cerr_cnt_u hva_smf_dfx_mem_cerr_cnt[4]; /* 320 */ + volatile csr_hva_smf_dfx_mem_ucerr_cnt_u hva_smf_dfx_mem_ucerr_cnt[4]; /* 330 */ + volatile csr_hva_smf_dfx_ecc_sta_u hva_smf_dfx_ecc_sta[4]; /* 340 */ + volatile csr_hva_smf_mem_ctrl_bus_0_u hva_smf_mem_ctrl_bus_0; /* 350 */ + volatile csr_hva_smf_mem_ctrl_bus_1_u hva_smf_mem_ctrl_bus_1; /* 354 */ + volatile csr_hva_smf_mem_ctrl_bus_2_u hva_smf_mem_ctrl_bus_2; /* 358 */ + volatile csr_hva_smf_mem_ctrl_bus_3_u hva_smf_mem_ctrl_bus_3; /* 35C */ + volatile csr_hva_smf_mem_ctrl_bus_4_u hva_smf_mem_ctrl_bus_4; /* 360 */ + volatile csr_smf_hva_req_api_num_u smf_hva_req_api_num[4]; /* 370 */ + volatile csr_hva_smf_rsp_api_num_u hva_smf_rsp_api_num[4]; /* 380 */ + volatile csr_hva_smf_smmu_axi_rd_num_u hva_smf_smmu_axi_rd_num; /* 390 */ + volatile csr_hva_smf_smmu_axi_wr_num_u hva_smf_smmu_axi_wr_num; /* 394 */ + volatile csr_smmu_hva_axi_b_num_u smmu_hva_axi_b_num; /* 398 */ + volatile csr_hva_smf_lat_sts_cfg_u hva_smf_lat_sts_cfg; /* 400 */ + volatile csr_hva_smf_wr_bp_cfg_u hva_smf_wr_bp_cfg; /* 404 */ + volatile csr_hva_smf_rd_bp_cfg_u hva_smf_rd_bp_cfg; /* 408 */ + volatile csr_hva_jam_time_cfg_u hva_jam_time_cfg; /* 40C */ +} S_hva_smf_reg_REGS_TYPE; + +/* Declare the struct pointor of the module hva_smf_reg */ +extern volatile S_hva_smf_reg_REGS_TYPE *gophva_smf_regAllReg; + +/* Declare the functions that set the member value */ +int iSetHVA_SMF_FPGA_VER_hva_smf_fpga_ver(unsigned int uhva_smf_fpga_ver); +int iSetHVA_SMF_EMU_VER_hva_smf_emu_ver(unsigned int uhva_smf_emu_ver); +int iSetHVA_SMF_MEM_ATTR_WIN0_L_hva_smf_mem_attr_win0_l(unsigned int uhva_smf_mem_attr_win0_l); +int iSetHVA_SMF_MEM_ATTR_WIN0_H_hva_smf_mem_attr_win0_h(unsigned int uhva_smf_mem_attr_win0_h); +int iSetHVA_SMF_MEM_ATTR_WIN1_L_hva_smf_mem_attr_win1_l(unsigned int uhva_smf_mem_attr_win1_l); +int iSetHVA_SMF_MEM_ATTR_WIN1_H_hva_smf_mem_attr_win1_h(unsigned int uhva_smf_mem_attr_win1_h); +int iSetHVA_SMF_MEM_ATTR_WIN2_L_hva_smf_mem_attr_win2_l(unsigned int uhva_smf_mem_attr_win2_l); +int iSetHVA_SMF_MEM_ATTR_WIN2_H_hva_smf_mem_attr_win2_h(unsigned int uhva_smf_mem_attr_win2_h); +int iSetHVA_SMF_MEM_ATTR_WIN3_L_hva_smf_mem_attr_win3_l(unsigned int uhva_smf_mem_attr_win3_l); +int iSetHVA_SMF_MEM_ATTR_WIN3_H_hva_smf_mem_attr_win3_h(unsigned int uhva_smf_mem_attr_win3_h); +int iSetHVA_SMF_MEM_ATTR_hva_smf_mem_attr_rd(unsigned int uhva_smf_mem_attr_rd); +int iSetHVA_SMF_MEM_ATTR_hva_smf_mem_attr_wr(unsigned int uhva_smf_mem_attr_wr); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_arqos_set(unsigned int uhva_smf_cfg_arqos_set); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_arssv_set(unsigned int uhva_smf_cfg_arssv_set); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_arstrmid_mode(unsigned int uhva_smf_cfg_arstrmid_mode); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdcln_thrld(unsigned int uhva_smf_cfg_rdcln_thrld); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdfna_thrld(unsigned int uhva_smf_cfg_rdfna_thrld); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdtype_thrld(unsigned int uhva_smf_cfg_rdtype_thrld); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdfa_thrld(unsigned int uhva_smf_cfg_rdfa_thrld); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_fa_mode(unsigned int uhva_smf_cfg_rd_fa_mode); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_fna_mode(unsigned int uhva_smf_cfg_rd_fna_mode); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_cln_mode(unsigned int uhva_smf_cfg_rd_cln_mode); +int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_type_mode(unsigned int uhva_smf_cfg_rd_type_mode); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_awqos_set(unsigned int uhva_smf_cfg_awqos_set); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_awssv_set(unsigned int uhva_smf_cfg_awssv_set); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_awstrmid_mode(unsigned int uhva_smf_cfg_awstrmid_mode); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_so_set(unsigned int uhva_smf_cfg_wr_so_set); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wrfna_thrld(unsigned int uhva_smf_cfg_wrfna_thrld); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wrtype_thrld(unsigned int uhva_smf_cfg_wrtype_thrld); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wrfa_thrld(unsigned int uhva_smf_cfg_wrfa_thrld); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_fa_mode(unsigned int uhva_smf_cfg_wr_fa_mode); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_fna_mode(unsigned int uhva_smf_cfg_wr_fna_mode); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_fp_mode(unsigned int uhva_smf_cfg_wr_fp_mode); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_type_mode(unsigned int uhva_smf_cfg_wr_type_mode); +int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_so_mode(unsigned int uhva_smf_cfg_wr_so_mode); +int iSetHVA_SMF_ARSTRMID_hva_smf_rd_strmid(unsigned int uhva_smf_rd_strmid); +int iSetHVA_SMF_AWSTRMID_hva_smf_wr_strmid(unsigned int uhva_smf_wr_strmid); +int iSetHVA_SMF_PF_CMD_TYPE_hva_smf_cfg_pf_cmd_type(unsigned int uhva_smf_cfg_pf_cmd_type); +int iSetHVA_SMF_INT_STARUS_hva_smf_npq_ov_int_status(unsigned int uhva_smf_npq_ov_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_npq_uf_int_status(unsigned int uhva_smf_npq_uf_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_npq_send_empty_int_status(unsigned int uhva_smf_npq_send_empty_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_pq_ov_int_status(unsigned int uhva_smf_pq_ov_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_pq_uf_int_status(unsigned int uhva_smf_pq_uf_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_pq_send_empty_int_status(unsigned int uhva_smf_pq_send_empty_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_1bit_ecc_int_status(unsigned int uhva_smf_1bit_ecc_int_status); +int iSetHVA_SMF_INT_STARUS_hva_smf_2bit_ecc_int_status(unsigned int uhva_smf_2bit_ecc_int_status); +int iSetHVA_SMF_INT_STARUS_hva_cpth_fifo_ov_int_status(unsigned int uhva_cpth_fifo_ov_int_status); +int iSetHVA_SMF_INT_EN_hva_smf_npq_ov_int_en(unsigned int uhva_smf_npq_ov_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_npq_uf_int_en(unsigned int uhva_smf_npq_uf_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_npq_send_empty_int_en(unsigned int uhva_smf_npq_send_empty_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_pq_ov_int_en(unsigned int uhva_smf_pq_ov_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_pq_uf_int_en(unsigned int uhva_smf_pq_uf_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_pq_send_empty_int_en(unsigned int uhva_smf_pq_send_empty_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_1bit_ecc_int_en(unsigned int uhva_smf_1bit_ecc_int_en); +int iSetHVA_SMF_INT_EN_hva_smf_2bit_ecc_int_en(unsigned int uhva_smf_2bit_ecc_int_en); +int iSetHVA_SMF_INT_EN_hva_cpth_fifo_ov_int_en(unsigned int uhva_cpth_fifo_ov_int_en); +int iSetHVA_SMF_INT_SET_hva_smf_npq_ov_int_set(unsigned int uhva_smf_npq_ov_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_npq_uf_int_set(unsigned int uhva_smf_npq_uf_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_npq_send_empty_int_set(unsigned int uhva_smf_npq_send_empty_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_pq_ov_int_set(unsigned int uhva_smf_pq_ov_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_pq_uf_int_set(unsigned int uhva_smf_pq_uf_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_pq_send_empty_int_set(unsigned int uhva_smf_pq_send_empty_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_1bit_ecc_int_set(unsigned int uhva_smf_1bit_ecc_int_set); +int iSetHVA_SMF_INT_SET_hva_smf_2bit_ecc_int_set(unsigned int uhva_smf_2bit_ecc_int_set); +int iSetHVA_SMF_INT_SET_hva_cpth_fifo_ov_int_set(unsigned int uhva_cpth_fifo_ov_int_set); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_npq_ov_int_raw_status(unsigned int uhva_smf_npq_ov_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_npq_uf_int_raw_status(unsigned int uhva_smf_npq_uf_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_npq_send_empty_int_raw_status( + unsigned int uhva_smf_npq_send_empty_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_pq_ov_int_raw_status(unsigned int uhva_smf_pq_ov_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_pq_uf_int_raw_status(unsigned int uhva_smf_pq_uf_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_pq_send_empty_int_raw_status(unsigned int uhva_smf_pq_send_empty_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_1bit_ecc_int_raw_status(unsigned int uhva_smf_1bit_ecc_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_2bit_ecc_int_raw_status(unsigned int uhva_smf_2bit_ecc_int_raw_status); +int iSetHVA_SMF_INT_RAW_STATUS_hva_cpth_fifo_ov_int_raw_status(unsigned int uhva_cpth_fifo_ov_int_raw_status); +int iSetHVA_ICL_CFG_sc_dispatch_errrsp(unsigned int usc_dispatch_errrsp); +int iSetHVA_ICL_CFG_hva_icl_smmu_bdf(unsigned int uhva_icl_smmu_bdf); +int iSetHVA_SMF_AXI_MAX_TRANS_hva_smf_cfg_rd_max_trans(unsigned int uhva_smf_cfg_rd_max_trans); +int iSetHVA_SMF_AXI_MAX_TRANS_hva_smf_cfg_wr_max_trans(unsigned int uhva_smf_cfg_wr_max_trans); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_10bit_tag_req_en(unsigned int uhva_smf_cpi_10bit_tag_req_en); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_10bit_tag_cpl_en(unsigned int uhva_smf_cpi_10bit_tag_cpl_en); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_extended_tag_en(unsigned int uhva_smf_cpi_extended_tag_en); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cpl_timeout_dis(unsigned int uhva_smf_cpi_cpl_timeout_dis); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cpl_timeout_value(unsigned int uhva_smf_cpi_cpl_timeout_value); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cfg_mrrs(unsigned int uhva_smf_cpi_cfg_mrrs); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cfg_mps(unsigned int uhva_smf_cpi_cfg_mps); +int iSetHVA_SMF_CPI_CFG_hva_smf_link_down(unsigned int uhva_smf_link_down); +int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_tx_crd_active_en(unsigned int uhva_smf_cpi_tx_crd_active_en); +int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_p_hed_crdt(unsigned int uhva_smf_cpi_p_hed_crdt); +int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_p_dat_crdt(unsigned int uhva_smf_cpi_p_dat_crdt); +int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_np_hed_crdt(unsigned int uhva_smf_cpi_np_hed_crdt); +int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_crdt_init(unsigned int uhva_smf_cpi_crdt_init); +int iSetHVA_SMF_RAM_ECC_BYPASS_hva_smf_ram_err_chk_bypass(unsigned int uhva_smf_ram_err_chk_bypass); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_db_ram_cerr_ins_req(unsigned int uhva_smf_npq_db_ram_cerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_db_ram_ucerr_ins_req(unsigned int uhva_smf_npq_db_ram_ucerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_db_ram_cerr_ins_req(unsigned int uhva_smf_pq_db_ram_cerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_db_ram_ucerr_ins_req(unsigned int uhva_smf_pq_db_ram_ucerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_entry_ram_cerr_ins_req(unsigned int uhva_smf_npq_entry_ram_cerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_entry_ram_ucerr_ins_req(unsigned int uhva_smf_npq_entry_ram_ucerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_entry_ram_cerr_ins_req(unsigned int uhva_smf_pq_entry_ram_cerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_entry_ram_ucerr_ins_req(unsigned int uhva_smf_pq_entry_ram_ucerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_cpth_fifo_ram_cerr_ins_req(unsigned int uhva_cpth_fifo_ram_cerr_ins_req); +int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_cpth_fifo_ram_ucerr_ins_req(unsigned int uhva_cpth_fifo_ram_ucerr_ins_req); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_db_ram_ucerr_fatal_en(unsigned int uhva_smf_npq_db_ram_ucerr_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_db_ram_ucerr_fatal_en(unsigned int uhva_smf_pq_db_ram_ucerr_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_entry_ram_ucerr_fatal_en(unsigned int uhva_smf_npq_entry_ram_ucerr_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_entry_ram_ucerr_fatal_en(unsigned int uhva_smf_pq_entry_ram_ucerr_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_ov_fatal_en(unsigned int uhva_smf_npq_ov_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_uf_fatal_en(unsigned int uhva_smf_npq_uf_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_send_empty_fatal_en(unsigned int uhva_smf_npq_send_empty_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_ov_fatal_en(unsigned int uhva_smf_pq_ov_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_uf_fatal_en(unsigned int uhva_smf_pq_uf_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_send_empty_fatal_en(unsigned int uhva_smf_pq_send_empty_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_cpth_fifo_ram_ucerr_fatal_en(unsigned int uhva_cpth_fifo_ram_ucerr_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_cpth_fifo_ov_fatal_en(unsigned int uhva_cpth_fifo_ov_fatal_en); +int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_fatal_err_en(unsigned int uhva_smf_fatal_err_en); +int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_cpl_data_crdt(unsigned int uhva_smf_inner_cpl_data_crdt); +int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_send_npq_crdt(unsigned int uhva_smf_inner_send_npq_crdt); +int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_send_pq_crdt(unsigned int uhva_smf_inner_send_pq_crdt); +int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_crdt_init(unsigned int uhva_smf_inner_crdt_init); +int iSetHVA_SMF_FIFO_AF_CFG_hva_smf_pq_sdata_fifo_af_th(unsigned int uhva_smf_pq_sdata_fifo_af_th); +int iSetHVA_SMF_CRDT_hva_smf_rsp_crdt(unsigned int uhva_smf_rsp_crdt); +int iSetHVA_SMF_CRDT_hva_smf_cpl_crdt(unsigned int uhva_smf_cpl_crdt); +int iSetHVA_SMF_CRDT_hva_smf_crdt_init(unsigned int uhva_smf_crdt_init); +int iSetHVA_SMF_PNP_ODR_DIS_hva_cpth_pnp_odr_dis(unsigned int uhva_cpth_pnp_odr_dis); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_cpl_stat_en(unsigned int uhva_smf_dfx_tx_cpl_stat_en); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_cpl_stat_clr(unsigned int uhva_smf_dfx_tx_cpl_stat_clr); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_cpl_cnt_clr(unsigned int uhva_smf_dfx_tx_cpl_cnt_clr); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_hva_get_cpi_p_cnt_clr(unsigned int uhva_smf_dfx_hva_get_cpi_p_cnt_clr); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_p_stat_en(unsigned int uhva_smf_dfx_tx_p_stat_en); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_p_stat_clr(unsigned int uhva_smf_dfx_tx_p_stat_clr); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_ucerr_cnt_clr(unsigned int uhva_smf_dfx_ucerr_cnt_clr); +int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_cerr_cnt_clr(unsigned int uhva_smf_dfx_cerr_cnt_clr); +int iSetHVA_SMF_DFX_CPL_BW0_hva_smf_dfx_tx_cpl_bw_curr(unsigned int uhva_smf_dfx_tx_cpl_bw_curr); +int iSetHVA_SMF_DFX_CPL_BW0_hva_smf_dfx_tx_cpl_bw_max(unsigned int uhva_smf_dfx_tx_cpl_bw_max); +int iSetHVA_SMF_DFX_CPL_BW1_hva_smf_dfx_tx_cpl_bw_ava(unsigned int uhva_smf_dfx_tx_cpl_bw_ava); +int iSetHVA_SMF_DFX_NPQ_DB_STATE_hva_smf_dfx_npq_db_state(unsigned int uhva_smf_dfx_npq_db_state); +int iSetHVA_SMF_DFX_TX_CPL_CNT0_hva_smf_dfx_tx_cpl_dat_err_cnt(unsigned int uhva_smf_dfx_tx_cpl_dat_err_cnt); +int iSetHVA_SMF_DFX_TX_CPL_CNT0_hva_smf_dfx_tx_cpl_unsuccess_cnt(unsigned int uhva_smf_dfx_tx_cpl_unsuccess_cnt); +int iSetHVA_SMF_DFX_TX_CPL_CNT1_hva_smf_dfx_tx_cpl_cnt(unsigned int uhva_smf_dfx_tx_cpl_cnt); +int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_send_ptr(unsigned int uhva_smf_dfx_npq_send_ptr); +int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_free_ptr(unsigned int uhva_smf_dfx_npq_free_ptr); +int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_rls_ptr(unsigned int uhva_smf_dfx_npq_rls_ptr); +int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_free_cnt(unsigned int uhva_smf_dfx_npq_free_cnt); +int iSetHVA_SMF_DFX_P_BW0_hva_smf_dfx_tx_p_bw_curr(unsigned int uhva_smf_dfx_tx_p_bw_curr); +int iSetHVA_SMF_DFX_P_BW0_hva_smf_dfx_tx_p_bw_max(unsigned int uhva_smf_dfx_tx_p_bw_max); +int iSetHVA_SMF_DFX_P_BW1_hva_smf_dfx_tx_p_bw_ava(unsigned int uhva_smf_dfx_tx_p_bw_ava); +int iSetHVA_SMF_DFX_P_CNT_hva_smf_dfx_hva_get_cpi_p_cnt(unsigned int uhva_smf_dfx_hva_get_cpi_p_cnt); +int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_send_ptr(unsigned int uhva_smf_dfx_pq_send_ptr); +int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_free_ptr(unsigned int uhva_smf_dfx_pq_free_ptr); +int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_rls_ptr(unsigned int uhva_smf_dfx_pq_rls_ptr); +int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_free_cnt(unsigned int uhva_smf_dfx_pq_free_cnt); +int iSetHVA_SMF_DFX_PQ_WR_ERR_hva_smf_dfx_pq_wr_err_abresp(unsigned int uhva_smf_dfx_pq_wr_err_abresp); +int iSetHVA_SMF_DFX_PQ_WR_ERR_hva_smf_dfx_pq_wr_err(unsigned int uhva_smf_dfx_pq_wr_err); +int iSetHVA_SMF_DFX_PQ_WR_ERR_hva_smf_dfx_pq_wr_err_clr(unsigned int uhva_smf_dfx_pq_wr_err_clr); +int iSetHVA_SMF_DFX_PQ_WR_ERR_ADDR_H_hva_smf_dfx_pq_wr_err_addr_h(unsigned int uhva_smf_dfx_pq_wr_err_addr_h); +int iSetHVA_SMF_DFX_PQ_WR_ERR_ADDR_L_hva_smf_dfx_pq_wr_err_addr_l(unsigned int uhva_smf_dfx_pq_wr_err_addr_l); +int iSetHVA_SMF_DFX_TLP_ZERO_LEN_hva_smf_dfx_pq_zero_write(unsigned int uhva_smf_dfx_pq_zero_write); +int iSetHVA_SMF_DFX_TLP_ZERO_LEN_hva_smf_dfx_npq_zero_read(unsigned int uhva_smf_dfx_npq_zero_read); +int iSetHVA_SMF_DFX_AXI_BID_ERR_hva_smf_dfx_hva_bid_err(unsigned int uhva_smf_dfx_hva_bid_err); +int iSetHVA_SMF_DFX_DB_ECC_ERR_ADDR_hva_smf_dfx_pq_db_ecc_err_addr(unsigned int uhva_smf_dfx_pq_db_ecc_err_addr); +int iSetHVA_SMF_DFX_DB_ECC_ERR_ADDR_hva_smf_dfx_npq_db_ecc_err_addr(unsigned int uhva_smf_dfx_npq_db_ecc_err_addr); +int iSetHVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_hva_smf_dfx_pq_entry_ecc_err_addr( + unsigned int uhva_smf_dfx_pq_entry_ecc_err_addr); +int iSetHVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_hva_smf_dfx_npq_entry_ecc_err_addr( + unsigned int uhva_smf_dfx_npq_entry_ecc_err_addr); +int iSetHVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_hva_smf_dfx_cpth_fifo_ecc_err_addr( + unsigned int uhva_smf_dfx_cpth_fifo_ecc_err_addr); +int iSetHVA_SMF_DFX_MEM_CERR_CNT_hva_smf_dfx_mem_cerr_cnt(unsigned int uhva_smf_dfx_mem_cerr_cnt); +int iSetHVA_SMF_DFX_MEM_UCERR_CNT_hva_smf_dfx_mem_ucerr_cnt(unsigned int uhva_smf_dfx_mem_ucerr_cnt); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_db_ram_cerr(unsigned int uhva_smf_npq_db_ram_cerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_db_ram_ucerr(unsigned int uhva_smf_npq_db_ram_ucerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_db_ram_cerr(unsigned int uhva_smf_pq_db_ram_cerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_db_ram_ucerr(unsigned int uhva_smf_pq_db_ram_ucerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_entry_ram_cerr(unsigned int uhva_smf_npq_entry_ram_cerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_entry_ram_ucerr(unsigned int uhva_smf_npq_entry_ram_ucerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_entry_ram_cerr(unsigned int uhva_smf_pq_entry_ram_cerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_entry_ram_ucerr(unsigned int uhva_smf_pq_entry_ram_ucerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_cpth_fifo_ram_cerr(unsigned int uhva_cpth_fifo_ram_cerr); +int iSetHVA_SMF_DFX_ECC_STA_hva_cpth_fifo_ram_ucerr(unsigned int uhva_cpth_fifo_ram_ucerr); +int iSetHVA_SMF_MEM_CTRL_BUS_0_hva_smf_mem_ctrl_bus_0(unsigned int uhva_smf_mem_ctrl_bus_0); +int iSetHVA_SMF_MEM_CTRL_BUS_1_hva_smf_mem_ctrl_bus_1(unsigned int uhva_smf_mem_ctrl_bus_1); +int iSetHVA_SMF_MEM_CTRL_BUS_2_hva_smf_mem_ctrl_bus_2(unsigned int uhva_smf_mem_ctrl_bus_2); +int iSetHVA_SMF_MEM_CTRL_BUS_3_hva_smf_mem_ctrl_bus_3(unsigned int uhva_smf_mem_ctrl_bus_3); +int iSetHVA_SMF_MEM_CTRL_BUS_4_hva_smf_mem_ctrl_bus_4(unsigned int uhva_smf_mem_ctrl_bus_4); +int iSetSMF_HVA_REQ_API_NUM_dfx_smf_hva_wr_requs_cnt(unsigned int udfx_smf_hva_wr_requs_cnt); +int iSetSMF_HVA_REQ_API_NUM_dfx_smf_hva_rd_requs_cnt(unsigned int udfx_smf_hva_rd_requs_cnt); +int iSetHVA_SMF_RSP_API_NUM_dfx_hva_smf_rd_rsp_cnt(unsigned int udfx_hva_smf_rd_rsp_cnt); +int iSetHVA_SMMU_AXI_RD_NUM_dfx_smmu_hva_rl_cnt(unsigned int udfx_smmu_hva_rl_cnt); +int iSetHVA_SMMU_AXI_RD_NUM_dfx_hva_smmu_ar_cnt(unsigned int udfx_hva_smmu_ar_cnt); +int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_wl_cnt(unsigned int udfx_hva_smmu_wl_cnt); +int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_aw_cnt(unsigned int udfx_hva_smmu_aw_cnt); +int iSetSMMU_HVA_AXI_B_NUM_dfx_smmu_hva_b_cnt(unsigned int udfx_smmu_hva_b_cnt); +int iSetHVA_LAT_STS_CFG_cfg_lat_stat_clr(unsigned int ucfg_lat_stat_clr); +int iSetHVA_LAT_STS_CFG_cfg_lat_stat_en(unsigned int ucfg_lat_stat_en); +int iSetHVA_WR_BP_CFG_cfg_wr_bp_clr_th(unsigned int ucfg_wr_bp_clr_th); +int iSetHVA_WR_BP_CFG_cfg_wr_bp_th(unsigned int ucfg_wr_bp_th); +int iSetHVA_RD_BP_CFG_cfg_rd_bp_clr_th(unsigned int ucfg_rd_bp_clr_th); +int iSetHVA_RD_BP_CFG_cfg_rd_bp_th(unsigned int ucfg_rd_bp_th); +int iSetHVA_JAM_TIME_CFG_cfg_jam_bp_bus_timer(unsigned int ucfg_jam_bp_bus_timer); + + +#endif // HI1823_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_smf_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_smf_reg_offset.h new file mode 100644 index 000000000..5f0b10050 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/hva_smf_reg_offset.h @@ -0,0 +1,189 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hva_smf_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : HVA_SMF +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// ****************************************************************************** + +#ifndef HVA_SMF_REG_OFFSET_H +#define HVA_SMF_REG_OFFSET_H + +/* HVA_SMF_REG Base address of Module's Register */ +#define CSR_HVA_SMF_REG_BASE (0x0) + +/* **************************************************************************** */ +/* HVA_SMF_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HVA_SMF_REG_HVA_SMF_FPGA_VER_REG (CSR_HVA_SMF_REG_BASE + 0x0) /* HVA FPGA版本寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_EMU_VER_REG (CSR_HVA_SMF_REG_BASE + 0x4) /* HVA EMU版本寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN0_L_REG \ + (CSR_HVA_SMF_REG_BASE + 0xC) /* Memory 属性配置窗口，第一个窗口上限的低32bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN0_H_REG \ + (CSR_HVA_SMF_REG_BASE + 0x10) /* Memory 属性配置窗口，第一个窗口上限的高4bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN1_L_REG \ + (CSR_HVA_SMF_REG_BASE + 0x14) /* Memory 属性配置窗口，第二个窗口上限的低32bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN1_H_REG \ + (CSR_HVA_SMF_REG_BASE + 0x18) /* Memory 属性配置窗口，第二个窗口上限的高4bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN2_L_REG \ + (CSR_HVA_SMF_REG_BASE + 0x1C) /* Memory 属性配置窗口，第三个窗口上限的低32bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN2_H_REG \ + (CSR_HVA_SMF_REG_BASE + 0x20) /* Memory 属性配置窗口，第三个窗口上限的高4bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN3_L_REG \ + (CSR_HVA_SMF_REG_BASE + 0x24) /* Memory 属性配置窗口，第四个窗口上限的低32bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_WIN3_H_REG \ + (CSR_HVA_SMF_REG_BASE + 0x28) /* Memory 属性配置窗口，第四个窗口上限的高4bit */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_0_REG (CSR_HVA_SMF_REG_BASE + 0x30) /* Memory 属性配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_1_REG (CSR_HVA_SMF_REG_BASE + 0x34) /* Memory 属性配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_2_REG (CSR_HVA_SMF_REG_BASE + 0x38) /* Memory 属性配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_3_REG (CSR_HVA_SMF_REG_BASE + 0x3C) /* Memory 属性配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_ATTR_4_REG (CSR_HVA_SMF_REG_BASE + 0x40) /* Memory 属性配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_AR_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x50) /* AXIM 读控制模式 */ +#define CSR_HVA_SMF_REG_HVA_SMF_WR_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x54) /* AXIM 写控制模式 */ +#define CSR_HVA_SMF_REG_HVA_SMF_ARSTRMID_REG (CSR_HVA_SMF_REG_BASE + 0x58) /* ARUSER中STRMID寄存器配置值 */ +#define CSR_HVA_SMF_REG_HVA_SMF_AWSTRMID_REG (CSR_HVA_SMF_REG_BASE + 0x5C) /* AWUSER中STRMID寄存器配置值 */ +#define CSR_HVA_SMF_REG_HVA_SMF_PF_CMD_TYPE_REG \ + (CSR_HVA_SMF_REG_BASE + 0x7C) /* 对应PFSMMU USER中CMD_TYPE的配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_INT_STARUS_REG (CSR_HVA_SMF_REG_BASE + 0x80) /* HVA中断状态寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_INT_EN_REG (CSR_HVA_SMF_REG_BASE + 0x84) /* HVA中断使能寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_INT_SET_REG (CSR_HVA_SMF_REG_BASE + 0x88) /* HVA软件模拟中断寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_INT_RAW_STATUS_REG (CSR_HVA_SMF_REG_BASE + 0x8C) /* HVA原始中断状态寄存器 */ +#define CSR_HVA_SMF_REG_HVA_ICL_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x90) /* HVA_ICL中控制寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_AXI_MAX_TRANS_REG \ + (CSR_HVA_SMF_REG_BASE + 0xA0) /* HVA模块能够发出去AXI transaction的最大数量 */ +#define CSR_HVA_SMF_REG_HVA_SMF_CPI_CFG_REG (CSR_HVA_SMF_REG_BASE + 0xB0) /* HVA配置CPI Function属性 */ +#define CSR_HVA_SMF_REG_HVA_SMF_CPI_CRDT_CFG_REG (CSR_HVA_SMF_REG_BASE + 0xB4) /* HVA接收CPI TLP报文的信用配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_RAM_ECC_BYPASS_REG (CSR_HVA_SMF_REG_BASE + 0xB8) /* HVA RAM ECC校验bypass配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_RAM_ECC_ERR_INS_REG (CSR_HVA_SMF_REG_BASE + 0xBC) /* HVA RAM ECC注错 */ +#define CSR_HVA_SMF_REG_HVA_SMF_FATAL_ERR_CTRL_REG (CSR_HVA_SMF_REG_BASE + 0xC0) /* HVA 致命错误控制 */ +#define CSR_HVA_SMF_REG_HVA_SMF_INNER_CRDT_REG (CSR_HVA_SMF_REG_BASE + 0xC4) /* HVA内部信用配置 */ +#define CSR_HVA_SMF_REG_HVA_SMF_FIFO_AF_CFG_REG (CSR_HVA_SMF_REG_BASE + 0xC8) /* HVA内部将满水线配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_CRDT_REG (CSR_HVA_SMF_REG_BASE + 0xCC) /* 信用配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_PNP_ODR_DIS_REG (CSR_HVA_SMF_REG_BASE + 0xD0) /* SMF读写保序控制寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x200) /* DFX配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW0_0_REG (CSR_HVA_SMF_REG_BASE + 0x210) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW0_1_REG (CSR_HVA_SMF_REG_BASE + 0x214) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW0_2_REG (CSR_HVA_SMF_REG_BASE + 0x218) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW0_3_REG (CSR_HVA_SMF_REG_BASE + 0x21C) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW1_0_REG (CSR_HVA_SMF_REG_BASE + 0x220) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW1_1_REG (CSR_HVA_SMF_REG_BASE + 0x224) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW1_2_REG (CSR_HVA_SMF_REG_BASE + 0x228) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_CPL_BW1_3_REG (CSR_HVA_SMF_REG_BASE + 0x22C) /* NPQ完成包的带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_NPQ_DB_STATE_0_REG (CSR_HVA_SMF_REG_BASE + 0x230) /* NPQ databuffer状态寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_NPQ_DB_STATE_1_REG (CSR_HVA_SMF_REG_BASE + 0x234) /* NPQ databuffer状态寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_NPQ_DB_STATE_2_REG (CSR_HVA_SMF_REG_BASE + 0x238) /* NPQ databuffer状态寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_NPQ_DB_STATE_3_REG (CSR_HVA_SMF_REG_BASE + 0x23C) /* NPQ databuffer状态寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT0_0_REG (CSR_HVA_SMF_REG_BASE + 0x240) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT0_1_REG (CSR_HVA_SMF_REG_BASE + 0x244) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT0_2_REG (CSR_HVA_SMF_REG_BASE + 0x248) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT0_3_REG (CSR_HVA_SMF_REG_BASE + 0x24C) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT1_0_REG (CSR_HVA_SMF_REG_BASE + 0x250) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT1_1_REG (CSR_HVA_SMF_REG_BASE + 0x254) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT1_2_REG (CSR_HVA_SMF_REG_BASE + 0x258) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TX_CPL_CNT1_3_REG (CSR_HVA_SMF_REG_BASE + 0x25C) /* HVA返回完成包数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_NPQ_PTR_0_REG (CSR_HVA_SMF_REG_BASE + 0x260) /* HVA NPQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_NPQ_PTR_1_REG (CSR_HVA_SMF_REG_BASE + 0x264) /* HVA NPQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_NPQ_PTR_2_REG (CSR_HVA_SMF_REG_BASE + 0x268) /* HVA NPQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_NPQ_PTR_3_REG (CSR_HVA_SMF_REG_BASE + 0x26C) /* HVA NPQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW0_0_REG (CSR_HVA_SMF_REG_BASE + 0x270) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW0_1_REG (CSR_HVA_SMF_REG_BASE + 0x274) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW0_2_REG (CSR_HVA_SMF_REG_BASE + 0x278) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW0_3_REG (CSR_HVA_SMF_REG_BASE + 0x27C) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW1_0_REG (CSR_HVA_SMF_REG_BASE + 0x280) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW1_1_REG (CSR_HVA_SMF_REG_BASE + 0x284) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW1_2_REG (CSR_HVA_SMF_REG_BASE + 0x288) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_BW1_3_REG (CSR_HVA_SMF_REG_BASE + 0x28C) /* P报文带宽统计寄存器 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_CNT_0_REG (CSR_HVA_SMF_REG_BASE + 0x290) /* 接收P报文数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_CNT_1_REG (CSR_HVA_SMF_REG_BASE + 0x294) /* 接收P报文数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_CNT_2_REG (CSR_HVA_SMF_REG_BASE + 0x298) /* 接收P报文数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_P_CNT_3_REG (CSR_HVA_SMF_REG_BASE + 0x29C) /* 接收P报文数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_PTR_0_REG (CSR_HVA_SMF_REG_BASE + 0x2A0) /* HVA PQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_PTR_1_REG (CSR_HVA_SMF_REG_BASE + 0x2A4) /* HVA PQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_PTR_2_REG (CSR_HVA_SMF_REG_BASE + 0x2A8) /* HVA PQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_PTR_3_REG (CSR_HVA_SMF_REG_BASE + 0x2AC) /* HVA PQ的指针信息 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_0_REG (CSR_HVA_SMF_REG_BASE + 0x2B0) /* HVA PQ转换为AXI写返回错误 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_1_REG (CSR_HVA_SMF_REG_BASE + 0x2B4) /* HVA PQ转换为AXI写返回错误 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_2_REG (CSR_HVA_SMF_REG_BASE + 0x2B8) /* HVA PQ转换为AXI写返回错误 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_3_REG (CSR_HVA_SMF_REG_BASE + 0x2BC) /* HVA PQ转换为AXI写返回错误 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_H_0_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2C0) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_H_1_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2C4) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_H_2_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2C8) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_H_3_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2CC) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_L_0_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2D0) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_L_1_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2D4) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_L_2_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2D8) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_PQ_WR_ERR_ADDR_L_3_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2DC) /* HVA PQ转换为AXI写返回错误地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_TLP_ZERO_LEN_REG \ + (CSR_HVA_SMF_REG_BASE + 0x2E0) /* HVA接收到ZERO LENGTH操作的TLP报文 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_AXI_BID_ERR_REG (CSR_HVA_SMF_REG_BASE + 0x2F0) /* HVA接收到一个非法的bid */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_DB_ECC_ERR_ADDR_0_REG \ + (CSR_HVA_SMF_REG_BASE + 0x300) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_DB_ECC_ERR_ADDR_1_REG \ + (CSR_HVA_SMF_REG_BASE + 0x304) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_DB_ECC_ERR_ADDR_2_REG \ + (CSR_HVA_SMF_REG_BASE + 0x308) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_DB_ECC_ERR_ADDR_3_REG \ + (CSR_HVA_SMF_REG_BASE + 0x30C) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_0_REG \ + (CSR_HVA_SMF_REG_BASE + 0x310) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_1_REG \ + (CSR_HVA_SMF_REG_BASE + 0x314) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_2_REG \ + (CSR_HVA_SMF_REG_BASE + 0x318) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_3_REG \ + (CSR_HVA_SMF_REG_BASE + 0x31C) /* HVA memory发生ECC错误的地址 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_CERR_CNT_0_REG \ + (CSR_HVA_SMF_REG_BASE + 0x320) /* HVA中memory发生可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_CERR_CNT_1_REG \ + (CSR_HVA_SMF_REG_BASE + 0x324) /* HVA中memory发生可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_CERR_CNT_2_REG \ + (CSR_HVA_SMF_REG_BASE + 0x328) /* HVA中memory发生可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_CERR_CNT_3_REG \ + (CSR_HVA_SMF_REG_BASE + 0x32C) /* HVA中memory发生可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_UCERR_CNT_0_REG \ + (CSR_HVA_SMF_REG_BASE + 0x330) /* HVA中memory发生不可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_UCERR_CNT_1_REG \ + (CSR_HVA_SMF_REG_BASE + 0x334) /* HVA中memory发生不可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_UCERR_CNT_2_REG \ + (CSR_HVA_SMF_REG_BASE + 0x338) /* HVA中memory发生不可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_MEM_UCERR_CNT_3_REG \ + (CSR_HVA_SMF_REG_BASE + 0x33C) /* HVA中memory发生不可纠错误的次数统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ECC_STA_0_REG (CSR_HVA_SMF_REG_BASE + 0x340) /* HVA中memory ECC错误状态 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ECC_STA_1_REG (CSR_HVA_SMF_REG_BASE + 0x344) /* HVA中memory ECC错误状态 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ECC_STA_2_REG (CSR_HVA_SMF_REG_BASE + 0x348) /* HVA中memory ECC错误状态 */ +#define CSR_HVA_SMF_REG_HVA_SMF_DFX_ECC_STA_3_REG (CSR_HVA_SMF_REG_BASE + 0x34C) /* HVA中memory ECC错误状态 */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_CTRL_BUS_0_REG (CSR_HVA_SMF_REG_BASE + 0x350) /* HVA_SMF memory ctrl_bus */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_CTRL_BUS_1_REG (CSR_HVA_SMF_REG_BASE + 0x354) /* HVA_SMF memory ctrl_bus */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_CTRL_BUS_2_REG (CSR_HVA_SMF_REG_BASE + 0x358) /* HVA_SMF memory ctrl_bus */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_CTRL_BUS_3_REG (CSR_HVA_SMF_REG_BASE + 0x35C) /* HVA_SMF memory ctrl_bus */ +#define CSR_HVA_SMF_REG_HVA_SMF_MEM_CTRL_BUS_4_REG (CSR_HVA_SMF_REG_BASE + 0x360) /* HVA_SMF memory ctrl_bus */ +#define CSR_HVA_SMF_REG_SMF_HVA_REQ_API_NUM_0_REG (CSR_HVA_SMF_REG_BASE + 0x370) /* SMF发送到HVA请求数量统计 */ +#define CSR_HVA_SMF_REG_SMF_HVA_REQ_API_NUM_1_REG (CSR_HVA_SMF_REG_BASE + 0x374) /* SMF发送到HVA请求数量统计 */ +#define CSR_HVA_SMF_REG_SMF_HVA_REQ_API_NUM_2_REG (CSR_HVA_SMF_REG_BASE + 0x378) /* SMF发送到HVA请求数量统计 */ +#define CSR_HVA_SMF_REG_SMF_HVA_REQ_API_NUM_3_REG (CSR_HVA_SMF_REG_BASE + 0x37C) /* SMF发送到HVA请求数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_RSP_API_NUM_0_REG (CSR_HVA_SMF_REG_BASE + 0x380) /* HVA发送到SMF相应数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_RSP_API_NUM_1_REG (CSR_HVA_SMF_REG_BASE + 0x384) /* HVA发送到SMF相应数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_RSP_API_NUM_2_REG (CSR_HVA_SMF_REG_BASE + 0x388) /* HVA发送到SMF相应数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMF_RSP_API_NUM_3_REG (CSR_HVA_SMF_REG_BASE + 0x38C) /* HVA发送到SMF相应数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMMU_AXI_RD_NUM_REG \ + (CSR_HVA_SMF_REG_BASE + 0x390) /* HVA与SMMU之间AXI读请求及其返回数量统计 */ +#define CSR_HVA_SMF_REG_HVA_SMMU_AXI_WR_NUM_REG (CSR_HVA_SMF_REG_BASE + 0x394) /* AXI写响应数量统计 */ +#define CSR_HVA_SMF_REG_SMMU_HVA_AXI_B_NUM_REG (CSR_HVA_SMF_REG_BASE + 0x398) /* HVA发送到SMF相应数量统计 */ +#define CSR_HVA_SMF_REG_HVA_LAT_STS_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x400) /* 时延检测控制寄存器 */ +#define CSR_HVA_SMF_REG_HVA_WR_BP_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x404) /* 写报文延时反压阈值配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_RD_BP_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x408) /* 读报文延时反压阈值配置寄存器 */ +#define CSR_HVA_SMF_REG_HVA_JAM_TIME_CFG_REG (CSR_HVA_SMF_REG_BASE + 0x40C) /* JAM时间配置寄存器 */ + +#endif // HI1823_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/mbigen_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/mbigen_c_union_define.h new file mode 100644 index 000000000..311f05be6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/mbigen_c_union_define.h @@ -0,0 +1,643 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : mbigen_c_union_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : 项目描述信息 +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/28 16:32:59 Create file +// ****************************************************************************** + +#ifndef MBIGEN_C_UNION_DEFINE_H +#define MBIGEN_C_UNION_DEFINE_H + +/* Define the union csr_mbix_ctlr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctlr_enable : 2; /* [1:0] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_ctlr_u; + +/* Define the union csr_mbix_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_timeout_cfg : 24; /* [23:0] */ + u32 mbi_type : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_cfg_u; + +/* Define the union csr_mbix_its_ta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 its_ta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_its_ta_u; + +/* Define the union csr_mbix_gicd_ta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gicd_ta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_gicd_ta_u; + +/* Define the union csr_mbix_axim_user_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 user_requestid : 16; /* [15:0] */ + u32 user_snapattr : 2; /* [17:16] */ + u32 rsv_1 : 7; /* [24:18] */ + u32 user_fa : 1; /* [25] */ + u32 user_fna : 1; /* [26] */ + u32 user_cleaninv : 1; /* [27] */ + u32 user_type : 2; /* [29:28] */ + u32 user_fp : 1; /* [30] */ + u32 rsv_2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_axim_user_u; + +/* Define the union csr_mbix_dfx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_int_id : 10; /* [9:0] */ + u32 rsv_3 : 2; /* [11:10] */ + u32 tx_int_did : 19; /* [30:12] */ + u32 rsv_4 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_dfx_int_vector_u; + +/* Define the union csr_mbix_dfx_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_st : 12; /* [11:0] */ + u32 msi_wr_st : 1; /* [12] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_dfx_st_u; + +/* Define the union csr_mbix_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 snap_en : 1; /* [1] */ + u32 rsv_6 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_cnt_clr_ce_u; + +/* Define the union csr_mbix_dfx_irq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spiset_cnt : 8; /* [7:0] */ + u32 spiclr_cnt : 8; /* [15:8] */ + u32 lpiset_cnt : 8; /* [23:16] */ + u32 tout_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_dfx_irq_cnt_u; + +/* Define the union csr_mbix_dfx_wr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_wr_req_cnt : 1; /* [0] */ + u32 mbix_wr_ack_cnt : 1; /* [1] */ + u32 mbix_wr_bresp_cnt : 1; /* [2] */ + u32 rsv_7 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_dfx_wr_cnt_u; + +/* Define the union csr_mbix_imu_gicd_ta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 imu_gicd_ta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_imu_gicd_ta_u; + +/* Define the union csr_mbix_intx_gicd_ta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intx_gicd_ta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_intx_gicd_ta_u; + +/* Define the union csr_mbix_iidr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 implement : 12; /* [11:0] */ + u32 revision : 4; /* [15:12] */ + u32 variant : 4; /* [19:16] */ + u32 rsv_8 : 4; /* [23:20] */ + u32 productid : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_iidr_u; + +/* Define the union csr_mbix_bdoor_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bdoor : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_bdoor_u; + +/* Define the union csr_mbix_typer0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type0 : 1; /* [0] */ + u32 mbix_last0 : 1; /* [1] */ + u32 rsv_9 : 2; /* [3:2] */ + u32 mbix_vector_type0 : 4; /* [7:4] */ + u32 mbix_size0 : 4; /* [11:8] */ + u32 rsv_10 : 19; /* [30:12] */ + u32 mbix_valid0 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer0_u; + +/* Define the union csr_mbix_typer1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type1 : 1; /* [0] */ + u32 mbix_last1 : 1; /* [1] */ + u32 rsv_11 : 2; /* [3:2] */ + u32 mbix_vector_type1 : 4; /* [7:4] */ + u32 mbix_size1 : 4; /* [11:8] */ + u32 rsv_12 : 19; /* [30:12] */ + u32 mbix_valid1 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer1_u; + +/* Define the union csr_mbix_typer2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type2 : 1; /* [0] */ + u32 mbix_last2 : 1; /* [1] */ + u32 rsv_13 : 2; /* [3:2] */ + u32 mbix_vector_type2 : 4; /* [7:4] */ + u32 mbix_size2 : 4; /* [11:8] */ + u32 rsv_14 : 19; /* [30:12] */ + u32 mbix_valid2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer2_u; + +/* Define the union csr_mbix_typer3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type3 : 1; /* [0] */ + u32 mbix_last3 : 1; /* [1] */ + u32 rsv_15 : 2; /* [3:2] */ + u32 mbix_vector_type3 : 4; /* [7:4] */ + u32 mbix_size3 : 4; /* [11:8] */ + u32 rsv_16 : 19; /* [30:12] */ + u32 mbix_valid3 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer3_u; + +/* Define the union csr_mbix_typer4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type4 : 1; /* [0] */ + u32 mbix_last4 : 1; /* [1] */ + u32 rsv_17 : 2; /* [3:2] */ + u32 mbix_vector_type4 : 4; /* [7:4] */ + u32 mbix_size4 : 4; /* [11:8] */ + u32 rsv_18 : 19; /* [30:12] */ + u32 mbix_valid4 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer4_u; + +/* Define the union csr_mbix_typer5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type5 : 1; /* [0] */ + u32 mbix_last5 : 1; /* [1] */ + u32 rsv_19 : 2; /* [3:2] */ + u32 mbix_vector_type5 : 4; /* [7:4] */ + u32 mbix_size5 : 4; /* [11:8] */ + u32 rsv_20 : 19; /* [30:12] */ + u32 mbix_valid5 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer5_u; + +/* Define the union csr_mbix_typer6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type6 : 1; /* [0] */ + u32 mbix_last6 : 1; /* [1] */ + u32 rsv_21 : 2; /* [3:2] */ + u32 mbix_vector_type6 : 4; /* [7:4] */ + u32 mbix_size6 : 4; /* [11:8] */ + u32 rsv_22 : 19; /* [30:12] */ + u32 mbix_valid6 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer6_u; + +/* Define the union csr_mbix_typer7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type7 : 1; /* [0] */ + u32 mbix_last7 : 1; /* [1] */ + u32 rsv_23 : 2; /* [3:2] */ + u32 mbix_vector_type7 : 4; /* [7:4] */ + u32 mbix_size7 : 4; /* [11:8] */ + u32 rsv_24 : 19; /* [30:12] */ + u32 mbix_valid7 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer7_u; + +/* Define the union csr_mbix_typer8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type8 : 1; /* [0] */ + u32 mbix_last8 : 1; /* [1] */ + u32 rsv_25 : 2; /* [3:2] */ + u32 mbix_vector_type8 : 4; /* [7:4] */ + u32 mbix_size8 : 4; /* [11:8] */ + u32 rsv_26 : 19; /* [30:12] */ + u32 mbix_valid8 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer8_u; + +/* Define the union csr_mbix_typer9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type9 : 1; /* [0] */ + u32 mbix_last9 : 1; /* [1] */ + u32 rsv_27 : 2; /* [3:2] */ + u32 mbix_vector_type9 : 4; /* [7:4] */ + u32 mbix_size9 : 4; /* [11:8] */ + u32 rsv_28 : 19; /* [30:12] */ + u32 mbix_valid9 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer9_u; + +/* Define the union csr_mbix_typer10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix_type10 : 1; /* [0] */ + u32 mbix_last10 : 1; /* [1] */ + u32 rsv_29 : 2; /* [3:2] */ + u32 mbix_vector_type10 : 4; /* [7:4] */ + u32 mbix_size10 : 4; /* [11:8] */ + u32 rsv_30 : 19; /* [30:12] */ + u32 mbix_valid10 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_typer10_u; + +/* Define the union csr_mbix0_trig_typer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix0_trig_type : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix0_trig_typer_u; + +/* Define the union csr_mbix0_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix0_spiid : 10; /* [9:0] */ + u32 mbix_spi_type : 2; /* [11:10] */ + u32 mbix0_spi_ns : 1; /* [12] */ + u32 rsv_31 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix0_vector_u; + +/* Define the union csr_mbix5_trig_typer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix5_trig_type : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix5_trig_typer_u; + +/* Define the union csr_mbix5_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix5_local_did : 12; /* [11:0] */ + u32 mbix5_eventid : 10; /* [21:12] */ + u32 rsv_32 : 2; /* [23:22] */ + u32 rsv_33 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix5_vector_u; + +/* Define the union csr_mbix6_trig_typer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix6_trig_type : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix6_trig_typer_u; + +/* Define the union csr_mbix6_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix6_local_did : 12; /* [11:0] */ + u32 mbix6_eventid : 10; /* [21:12] */ + u32 rsv_34 : 2; /* [23:22] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix6_vector_u; + +/* Define the union csr_mbix7_trige_typer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix7_trig_type : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix7_trige_typer_u; + +/* Define the union csr_mbix7_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mbix7_local_did : 12; /* [11:0] */ + u32 mbix7_eventid : 10; /* [21:12] */ + u32 rsv_36 : 2; /* [23:22] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix7_vector_u; + +/* Define the union csr_mbix_int_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irq_clear : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mbix_int_clr_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mbix_ctlr_u mbix_ctlr; /* 0 */ + volatile csr_mbix_cfg_u mbix_cfg; /* 4 */ + volatile csr_mbix_its_ta_u mbix_its_ta; /* 8 */ + volatile csr_mbix_gicd_ta_u mbix_gicd_ta; /* C */ + volatile csr_mbix_axim_user_u mbix_axim_user; /* 10 */ + volatile csr_mbix_dfx_int_vector_u mbix_dfx_int_vector; /* 14 */ + volatile csr_mbix_dfx_st_u mbix_dfx_st; /* 18 */ + volatile csr_mbix_cnt_clr_ce_u mbix_cnt_clr_ce; /* 1C */ + volatile csr_mbix_dfx_irq_cnt_u mbix_dfx_irq_cnt; /* 20 */ + volatile csr_mbix_dfx_wr_cnt_u mbix_dfx_wr_cnt; /* 24 */ + volatile csr_mbix_imu_gicd_ta_u mbix_imu_gicd_ta; /* 28 */ + volatile csr_mbix_intx_gicd_ta_u mbix_intx_gicd_ta; /* 2C */ + volatile csr_mbix_iidr_u mbix_iidr; /* 30 */ + volatile csr_mbix_bdoor_u mbix_bdoor; /* 100 */ + volatile csr_mbix_typer0_u mbix_typer0; /* 40 */ + volatile csr_mbix_typer1_u mbix_typer1; /* 44 */ + volatile csr_mbix_typer2_u mbix_typer2; /* 48 */ + volatile csr_mbix_typer3_u mbix_typer3; /* 4C */ + volatile csr_mbix_typer4_u mbix_typer4; /* 50 */ + volatile csr_mbix_typer5_u mbix_typer5; /* 54 */ + volatile csr_mbix_typer6_u mbix_typer6; /* 58 */ + volatile csr_mbix_typer7_u mbix_typer7; /* 5C */ + volatile csr_mbix_typer8_u mbix_typer8; /* 60 */ + volatile csr_mbix_typer9_u mbix_typer9; /* 64 */ + volatile csr_mbix_typer10_u mbix_typer10; /* 68 */ + volatile csr_mbix0_trig_typer_u mbix0_trig_typer[2]; /* 400 */ + volatile csr_mbix0_vector_u mbix0_vector[64]; /* 500 */ + volatile csr_mbix5_trig_typer_u mbix5_trig_typer[4]; /* 5000 */ + volatile csr_mbix5_vector_u mbix5_vector[128]; /* 5200 */ + volatile csr_mbix6_trig_typer_u mbix6_trig_typer[4]; /* 6000 */ + volatile csr_mbix6_vector_u mbix6_vector[128]; /* 6200 */ + volatile csr_mbix7_trige_typer_u mbix7_trige_typer[4]; /* 7000 */ + volatile csr_mbix7_vector_u mbix7_vector[128]; /* 7200 */ + volatile csr_mbix_int_clr_u mbix_int_clr[30]; /* A000 */ +} S_mbix_cfg_REGS_TYPE; + +/* Declare the struct pointor of the module mbix_cfg */ +extern volatile S_mbix_cfg_REGS_TYPE *gopmbix_cfgAllReg; + +/* Declare the functions that set the member value */ +int iSetMBIX_CTLR_ctlr_enable(unsigned int uctlr_enable); +int iSetMBIX_CFG_mbix_timeout_cfg(unsigned int umbix_timeout_cfg); +int iSetMBIX_CFG_mbi_type(unsigned int umbi_type); +int iSetMBIX_ITS_TA_its_ta(unsigned int uits_ta); +int iSetMBIX_GICD_TA_gicd_ta(unsigned int ugicd_ta); +int iSetMBIX_AXIM_USER_user_requestid(unsigned int uuser_requestid); +int iSetMBIX_AXIM_USER_user_snapattr(unsigned int uuser_snapattr); +int iSetMBIX_AXIM_USER_user_fa(unsigned int uuser_fa); +int iSetMBIX_AXIM_USER_user_fna(unsigned int uuser_fna); +int iSetMBIX_AXIM_USER_user_cleaninv(unsigned int uuser_cleaninv); +int iSetMBIX_AXIM_USER_user_type(unsigned int uuser_type); +int iSetMBIX_AXIM_USER_user_fp(unsigned int uuser_fp); +int iSetMBIX_DFX_INT_VECTOR_tx_int_id(unsigned int utx_int_id); +int iSetMBIX_DFX_INT_VECTOR_tx_int_did(unsigned int utx_int_did); +int iSetMBIX_DFX_ST_mbix_st(unsigned int umbix_st); +int iSetMBIX_DFX_ST_msi_wr_st(unsigned int umsi_wr_st); +int iSetMBIX_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce); +int iSetMBIX_CNT_CLR_CE_snap_en(unsigned int usnap_en); +int iSetMBIX_DFX_IRQ_CNT_spiset_cnt(unsigned int uspiset_cnt); +int iSetMBIX_DFX_IRQ_CNT_spiclr_cnt(unsigned int uspiclr_cnt); +int iSetMBIX_DFX_IRQ_CNT_lpiset_cnt(unsigned int ulpiset_cnt); +int iSetMBIX_DFX_IRQ_CNT_tout_cnt(unsigned int utout_cnt); +int iSetMBIX_DFX_WR_CNT_mbix_wr_req_cnt(unsigned int umbix_wr_req_cnt); +int iSetMBIX_DFX_WR_CNT_mbix_wr_ack_cnt(unsigned int umbix_wr_ack_cnt); +int iSetMBIX_DFX_WR_CNT_mbix_wr_bresp_cnt(unsigned int umbix_wr_bresp_cnt); +int iSetMBIX_IMU_GICD_TA_imu_gicd_ta(unsigned int uimu_gicd_ta); +int iSetMBIX_INTX_GICD_TA_intx_gicd_ta(unsigned int uintx_gicd_ta); +int iSetMBIX_IIDR_implement(unsigned int uimplement); +int iSetMBIX_IIDR_revision(unsigned int urevision); +int iSetMBIX_IIDR_variant(unsigned int uvariant); +int iSetMBIX_IIDR_productid(unsigned int uproductid); +int iSetMBIX_BDOOR_bdoor(unsigned int ubdoor); +int iSetMBIX_TYPER0_mbix_type0(unsigned int umbix_type0); +int iSetMBIX_TYPER0_mbix_last0(unsigned int umbix_last0); +int iSetMBIX_TYPER0_mbix_vector_type0(unsigned int umbix_vector_type0); +int iSetMBIX_TYPER0_mbix_size0(unsigned int umbix_size0); +int iSetMBIX_TYPER0_mbix_valid0(unsigned int umbix_valid0); +int iSetMBIX_TYPER1_mbix_type1(unsigned int umbix_type1); +int iSetMBIX_TYPER1_mbix_last1(unsigned int umbix_last1); +int iSetMBIX_TYPER1_mbix_vector_type1(unsigned int umbix_vector_type1); +int iSetMBIX_TYPER1_mbix_size1(unsigned int umbix_size1); +int iSetMBIX_TYPER1_mbix_valid1(unsigned int umbix_valid1); +int iSetMBIX_TYPER2_mbix_type2(unsigned int umbix_type2); +int iSetMBIX_TYPER2_mbix_last2(unsigned int umbix_last2); +int iSetMBIX_TYPER2_mbix_vector_type2(unsigned int umbix_vector_type2); +int iSetMBIX_TYPER2_mbix_size2(unsigned int umbix_size2); +int iSetMBIX_TYPER2_mbix_valid2(unsigned int umbix_valid2); +int iSetMBIX_TYPER3_mbix_type3(unsigned int umbix_type3); +int iSetMBIX_TYPER3_mbix_last3(unsigned int umbix_last3); +int iSetMBIX_TYPER3_mbix_vector_type3(unsigned int umbix_vector_type3); +int iSetMBIX_TYPER3_mbix_size3(unsigned int umbix_size3); +int iSetMBIX_TYPER3_mbix_valid3(unsigned int umbix_valid3); +int iSetMBIX_TYPER4_mbix_type4(unsigned int umbix_type4); +int iSetMBIX_TYPER4_mbix_last4(unsigned int umbix_last4); +int iSetMBIX_TYPER4_mbix_vector_type4(unsigned int umbix_vector_type4); +int iSetMBIX_TYPER4_mbix_size4(unsigned int umbix_size4); +int iSetMBIX_TYPER4_mbix_valid4(unsigned int umbix_valid4); +int iSetMBIX_TYPER5_mbix_type5(unsigned int umbix_type5); +int iSetMBIX_TYPER5_mbix_last5(unsigned int umbix_last5); +int iSetMBIX_TYPER5_mbix_vector_type5(unsigned int umbix_vector_type5); +int iSetMBIX_TYPER5_mbix_size5(unsigned int umbix_size5); +int iSetMBIX_TYPER5_mbix_valid5(unsigned int umbix_valid5); +int iSetMBIX_TYPER6_mbix_type6(unsigned int umbix_type6); +int iSetMBIX_TYPER6_mbix_last6(unsigned int umbix_last6); +int iSetMBIX_TYPER6_mbix_vector_type6(unsigned int umbix_vector_type6); +int iSetMBIX_TYPER6_mbix_size6(unsigned int umbix_size6); +int iSetMBIX_TYPER6_mbix_valid6(unsigned int umbix_valid6); +int iSetMBIX_TYPER7_mbix_type7(unsigned int umbix_type7); +int iSetMBIX_TYPER7_mbix_last7(unsigned int umbix_last7); +int iSetMBIX_TYPER7_mbix_vector_type7(unsigned int umbix_vector_type7); +int iSetMBIX_TYPER7_mbix_size7(unsigned int umbix_size7); +int iSetMBIX_TYPER7_mbix_valid7(unsigned int umbix_valid7); +int iSetMBIX_TYPER8_mbix_type8(unsigned int umbix_type8); +int iSetMBIX_TYPER8_mbix_last8(unsigned int umbix_last8); +int iSetMBIX_TYPER8_mbix_vector_type8(unsigned int umbix_vector_type8); +int iSetMBIX_TYPER8_mbix_size8(unsigned int umbix_size8); +int iSetMBIX_TYPER8_mbix_valid8(unsigned int umbix_valid8); +int iSetMBIX_TYPER9_mbix_type9(unsigned int umbix_type9); +int iSetMBIX_TYPER9_mbix_last9(unsigned int umbix_last9); +int iSetMBIX_TYPER9_mbix_vector_type9(unsigned int umbix_vector_type9); +int iSetMBIX_TYPER9_mbix_size9(unsigned int umbix_size9); +int iSetMBIX_TYPER9_mbix_valid9(unsigned int umbix_valid9); +int iSetMBIX_TYPER10_mbix_type10(unsigned int umbix_type10); +int iSetMBIX_TYPER10_mbix_last10(unsigned int umbix_last10); +int iSetMBIX_TYPER10_mbix_vector_type10(unsigned int umbix_vector_type10); +int iSetMBIX_TYPER10_mbix_size10(unsigned int umbix_size10); +int iSetMBIX_TYPER10_mbix_valid10(unsigned int umbix_valid10); +int iSetMBIX0_TRIG_TYPER_mbix0_trig_type(unsigned int umbix0_trig_type); +int iSetMBIX0_VECTOR_mbix0_spiid(unsigned int umbix0_spiid); +int iSetMBIX0_VECTOR_mbix_spi_type(unsigned int umbix_spi_type); +int iSetMBIX0_VECTOR_mbix0_spi_ns(unsigned int umbix0_spi_ns); +int iSetMBIX5_TRIG_TYPER_mbix5_trig_type(unsigned int umbix5_trig_type); +int iSetMBIX5_VECTOR_mbix5_local_did(unsigned int umbix5_local_did); +int iSetMBIX5_VECTOR_mbix5_eventid(unsigned int umbix5_eventid); +int iSetMBIX6_TRIG_TYPER_mbix6_trig_type(unsigned int umbix6_trig_type); +int iSetMBIX6_VECTOR_mbix6_local_did(unsigned int umbix6_local_did); +int iSetMBIX6_VECTOR_mbix6_eventid(unsigned int umbix6_eventid); +int iSetMBIX7_TRIGE_TYPER_mbix7_trig_type(unsigned int umbix7_trig_type); +int iSetMBIX7_VECTOR_mbix7_local_did(unsigned int umbix7_local_did); +int iSetMBIX7_VECTOR_mbix7_eventid(unsigned int umbix7_eventid); +int iSetMBIX_INT_CLR_irq_clear(unsigned int uirq_clear); + + +#endif // MBIGEN_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/mbigen_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/mbigen_reg_offset.h new file mode 100644 index 000000000..741632446 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/mbigen_reg_offset.h @@ -0,0 +1,956 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : mbigen_reg_offset.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : 项目描述信息 +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/28 16:32:59 Create file +// ****************************************************************************** + +#ifndef MBIGEN_REG_OFFSET_H +#define MBIGEN_REG_OFFSET_H + +/* MBIX_CFG Base address of Module's Register */ +#define CSR_MBIX_CFG_BASE (0x0) + +/* **************************************************************************** */ +/* MBIX_CFG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MBIX_CFG_MBIX_CTLR_REG (CSR_MBIX_CFG_BASE + 0x0) /* mbix控制寄存器 */ +#define CSR_MBIX_CFG_MBIX_CFG_REG (CSR_MBIX_CFG_BASE + 0x4) /* MBIX配置 */ +#define CSR_MBIX_CFG_MBIX_ITS_TA_REG (CSR_MBIX_CFG_BASE + 0x8) /* MBI发送的LPI中断目标地址 */ +#define CSR_MBIX_CFG_MBIX_GICD_TA_REG (CSR_MBIX_CFG_BASE + 0xC) /* MBI发送的SPI中断目标地址 */ +#define CSR_MBIX_CFG_MBIX_AXIM_USER_REG (CSR_MBIX_CFG_BASE + 0x10) /* AXIM USER控制寄存器 */ +#define CSR_MBIX_CFG_MBIX_DFX_INT_VECTOR_REG (CSR_MBIX_CFG_BASE + 0x14) /* DFX寄存器 */ +#define CSR_MBIX_CFG_MBIX_DFX_ST_REG (CSR_MBIX_CFG_BASE + 0x18) /* DFX状态机 */ +#define CSR_MBIX_CFG_MBIX_CNT_CLR_CE_REG (CSR_MBIX_CFG_BASE + 0x1C) /* CNT_CYC类型寄存器读清控制信号 */ +#define CSR_MBIX_CFG_MBIX_DFX_IRQ_CNT_REG (CSR_MBIX_CFG_BASE + 0x20) /* ITS中断收发统计计数器 */ +#define CSR_MBIX_CFG_MBIX_DFX_WR_CNT_REG (CSR_MBIX_CFG_BASE + 0x24) /* MBIX_WR总线操作计数器 */ +#define CSR_MBIX_CFG_MBIX_IMU_GICD_TA_REG (CSR_MBIX_CFG_BASE + 0x28) /* MBI发送的SPI中断目标地址 */ +#define CSR_MBIX_CFG_MBIX_INTX_GICD_TA_REG (CSR_MBIX_CFG_BASE + 0x2C) /* PCIE INTX MSG发送的SPI中断目标地址 */ +#define CSR_MBIX_CFG_MBIX_IIDR_REG (CSR_MBIX_CFG_BASE + 0x30) /* MBIX身份寄存器 */ +#define CSR_MBIX_CFG_MBIX_BACKDOOR_REG (CSR_MBIX_CFG_BASE + 0x100) /* MBIX自定义寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER0_REG (CSR_MBIX_CFG_BASE + 0x40) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER1_REG (CSR_MBIX_CFG_BASE + 0x44) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER2_REG (CSR_MBIX_CFG_BASE + 0x48) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER3_REG (CSR_MBIX_CFG_BASE + 0x4C) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER4_REG (CSR_MBIX_CFG_BASE + 0x50) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER5_REG (CSR_MBIX_CFG_BASE + 0x54) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER6_REG (CSR_MBIX_CFG_BASE + 0x58) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER7_REG (CSR_MBIX_CFG_BASE + 0x5C) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER8_REG (CSR_MBIX_CFG_BASE + 0x60) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER9_REG (CSR_MBIX_CFG_BASE + 0x64) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX_TYPER10_REG (CSR_MBIX_CFG_BASE + 0x68) /* MBIXn规格描述寄存器 */ +#define CSR_MBIX_CFG_MBIX0_TRIG_TYPER_0_REG (CSR_MBIX_CFG_BASE + 0x400) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX0_TRIG_TYPER_1_REG (CSR_MBIX_CFG_BASE + 0x404) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_0_REG (CSR_MBIX_CFG_BASE + 0x500) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_1_REG (CSR_MBIX_CFG_BASE + 0x504) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_2_REG (CSR_MBIX_CFG_BASE + 0x508) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_3_REG (CSR_MBIX_CFG_BASE + 0x50C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_4_REG (CSR_MBIX_CFG_BASE + 0x510) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_5_REG (CSR_MBIX_CFG_BASE + 0x514) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_6_REG (CSR_MBIX_CFG_BASE + 0x518) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_7_REG (CSR_MBIX_CFG_BASE + 0x51C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_8_REG (CSR_MBIX_CFG_BASE + 0x520) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_9_REG (CSR_MBIX_CFG_BASE + 0x524) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_10_REG (CSR_MBIX_CFG_BASE + 0x528) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_11_REG (CSR_MBIX_CFG_BASE + 0x52C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_12_REG (CSR_MBIX_CFG_BASE + 0x530) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_13_REG (CSR_MBIX_CFG_BASE + 0x534) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_14_REG (CSR_MBIX_CFG_BASE + 0x538) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_15_REG (CSR_MBIX_CFG_BASE + 0x53C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_16_REG (CSR_MBIX_CFG_BASE + 0x540) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_17_REG (CSR_MBIX_CFG_BASE + 0x544) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_18_REG (CSR_MBIX_CFG_BASE + 0x548) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_19_REG (CSR_MBIX_CFG_BASE + 0x54C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_20_REG (CSR_MBIX_CFG_BASE + 0x550) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_21_REG (CSR_MBIX_CFG_BASE + 0x554) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_22_REG (CSR_MBIX_CFG_BASE + 0x558) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_23_REG (CSR_MBIX_CFG_BASE + 0x55C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_24_REG (CSR_MBIX_CFG_BASE + 0x560) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_25_REG (CSR_MBIX_CFG_BASE + 0x564) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_26_REG (CSR_MBIX_CFG_BASE + 0x568) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_27_REG (CSR_MBIX_CFG_BASE + 0x56C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_28_REG (CSR_MBIX_CFG_BASE + 0x570) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_29_REG (CSR_MBIX_CFG_BASE + 0x574) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_30_REG (CSR_MBIX_CFG_BASE + 0x578) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_31_REG (CSR_MBIX_CFG_BASE + 0x57C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_32_REG (CSR_MBIX_CFG_BASE + 0x580) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_33_REG (CSR_MBIX_CFG_BASE + 0x584) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_34_REG (CSR_MBIX_CFG_BASE + 0x588) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_35_REG (CSR_MBIX_CFG_BASE + 0x58C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_36_REG (CSR_MBIX_CFG_BASE + 0x590) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_37_REG (CSR_MBIX_CFG_BASE + 0x594) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_38_REG (CSR_MBIX_CFG_BASE + 0x598) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_39_REG (CSR_MBIX_CFG_BASE + 0x59C) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_40_REG (CSR_MBIX_CFG_BASE + 0x5A0) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_41_REG (CSR_MBIX_CFG_BASE + 0x5A4) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_42_REG (CSR_MBIX_CFG_BASE + 0x5A8) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_43_REG (CSR_MBIX_CFG_BASE + 0x5AC) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_44_REG (CSR_MBIX_CFG_BASE + 0x5B0) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_45_REG (CSR_MBIX_CFG_BASE + 0x5B4) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_46_REG (CSR_MBIX_CFG_BASE + 0x5B8) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_47_REG (CSR_MBIX_CFG_BASE + 0x5BC) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_48_REG (CSR_MBIX_CFG_BASE + 0x5C0) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_49_REG (CSR_MBIX_CFG_BASE + 0x5C4) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_50_REG (CSR_MBIX_CFG_BASE + 0x5C8) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_51_REG (CSR_MBIX_CFG_BASE + 0x5CC) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_52_REG (CSR_MBIX_CFG_BASE + 0x5D0) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_53_REG (CSR_MBIX_CFG_BASE + 0x5D4) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_54_REG (CSR_MBIX_CFG_BASE + 0x5D8) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_55_REG (CSR_MBIX_CFG_BASE + 0x5DC) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_56_REG (CSR_MBIX_CFG_BASE + 0x5E0) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_57_REG (CSR_MBIX_CFG_BASE + 0x5E4) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_58_REG (CSR_MBIX_CFG_BASE + 0x5E8) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_59_REG (CSR_MBIX_CFG_BASE + 0x5EC) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_60_REG (CSR_MBIX_CFG_BASE + 0x5F0) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_61_REG (CSR_MBIX_CFG_BASE + 0x5F4) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_62_REG (CSR_MBIX_CFG_BASE + 0x5F8) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX0_VECTOR_63_REG (CSR_MBIX_CFG_BASE + 0x5FC) /* SPI管脚对应的中断配置寄存器spi_num{63,0} */ +#define CSR_MBIX_CFG_MBIX5_TRIG_TYPER_0_REG (CSR_MBIX_CFG_BASE + 0x5000) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX5_TRIG_TYPER_1_REG (CSR_MBIX_CFG_BASE + 0x5004) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX5_TRIG_TYPER_2_REG (CSR_MBIX_CFG_BASE + 0x5008) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX5_TRIG_TYPER_3_REG (CSR_MBIX_CFG_BASE + 0x500C) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_0_REG \ + (CSR_MBIX_CFG_BASE + 0x5200) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_1_REG \ + (CSR_MBIX_CFG_BASE + 0x5204) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_2_REG \ + (CSR_MBIX_CFG_BASE + 0x5208) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_3_REG \ + (CSR_MBIX_CFG_BASE + 0x520C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_4_REG \ + (CSR_MBIX_CFG_BASE + 0x5210) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_5_REG \ + (CSR_MBIX_CFG_BASE + 0x5214) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_6_REG \ + (CSR_MBIX_CFG_BASE + 0x5218) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_7_REG \ + (CSR_MBIX_CFG_BASE + 0x521C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_8_REG \ + (CSR_MBIX_CFG_BASE + 0x5220) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_9_REG \ + (CSR_MBIX_CFG_BASE + 0x5224) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_10_REG \ + (CSR_MBIX_CFG_BASE + 0x5228) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_11_REG \ + (CSR_MBIX_CFG_BASE + 0x522C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_12_REG \ + (CSR_MBIX_CFG_BASE + 0x5230) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_13_REG \ + (CSR_MBIX_CFG_BASE + 0x5234) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_14_REG \ + (CSR_MBIX_CFG_BASE + 0x5238) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_15_REG \ + (CSR_MBIX_CFG_BASE + 0x523C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_16_REG \ + (CSR_MBIX_CFG_BASE + 0x5240) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_17_REG \ + (CSR_MBIX_CFG_BASE + 0x5244) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_18_REG \ + (CSR_MBIX_CFG_BASE + 0x5248) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_19_REG \ + (CSR_MBIX_CFG_BASE + 0x524C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_20_REG \ + (CSR_MBIX_CFG_BASE + 0x5250) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_21_REG \ + (CSR_MBIX_CFG_BASE + 0x5254) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_22_REG \ + (CSR_MBIX_CFG_BASE + 0x5258) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_23_REG \ + (CSR_MBIX_CFG_BASE + 0x525C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_24_REG \ + (CSR_MBIX_CFG_BASE + 0x5260) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_25_REG \ + (CSR_MBIX_CFG_BASE + 0x5264) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_26_REG \ + (CSR_MBIX_CFG_BASE + 0x5268) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_27_REG \ + (CSR_MBIX_CFG_BASE + 0x526C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_28_REG \ + (CSR_MBIX_CFG_BASE + 0x5270) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_29_REG \ + (CSR_MBIX_CFG_BASE + 0x5274) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_30_REG \ + (CSR_MBIX_CFG_BASE + 0x5278) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_31_REG \ + (CSR_MBIX_CFG_BASE + 0x527C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_32_REG \ + (CSR_MBIX_CFG_BASE + 0x5280) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_33_REG \ + (CSR_MBIX_CFG_BASE + 0x5284) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_34_REG \ + (CSR_MBIX_CFG_BASE + 0x5288) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_35_REG \ + (CSR_MBIX_CFG_BASE + 0x528C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_36_REG \ + (CSR_MBIX_CFG_BASE + 0x5290) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_37_REG \ + (CSR_MBIX_CFG_BASE + 0x5294) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_38_REG \ + (CSR_MBIX_CFG_BASE + 0x5298) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_39_REG \ + (CSR_MBIX_CFG_BASE + 0x529C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_40_REG \ + (CSR_MBIX_CFG_BASE + 0x52A0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_41_REG \ + (CSR_MBIX_CFG_BASE + 0x52A4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_42_REG \ + (CSR_MBIX_CFG_BASE + 0x52A8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_43_REG \ + (CSR_MBIX_CFG_BASE + 0x52AC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_44_REG \ + (CSR_MBIX_CFG_BASE + 0x52B0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_45_REG \ + (CSR_MBIX_CFG_BASE + 0x52B4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_46_REG \ + (CSR_MBIX_CFG_BASE + 0x52B8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_47_REG \ + (CSR_MBIX_CFG_BASE + 0x52BC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_48_REG \ + (CSR_MBIX_CFG_BASE + 0x52C0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_49_REG \ + (CSR_MBIX_CFG_BASE + 0x52C4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_50_REG \ + (CSR_MBIX_CFG_BASE + 0x52C8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_51_REG \ + (CSR_MBIX_CFG_BASE + 0x52CC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_52_REG \ + (CSR_MBIX_CFG_BASE + 0x52D0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_53_REG \ + (CSR_MBIX_CFG_BASE + 0x52D4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_54_REG \ + (CSR_MBIX_CFG_BASE + 0x52D8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_55_REG \ + (CSR_MBIX_CFG_BASE + 0x52DC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_56_REG \ + (CSR_MBIX_CFG_BASE + 0x52E0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_57_REG \ + (CSR_MBIX_CFG_BASE + 0x52E4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_58_REG \ + (CSR_MBIX_CFG_BASE + 0x52E8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_59_REG \ + (CSR_MBIX_CFG_BASE + 0x52EC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_60_REG \ + (CSR_MBIX_CFG_BASE + 0x52F0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_61_REG \ + (CSR_MBIX_CFG_BASE + 0x52F4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_62_REG \ + (CSR_MBIX_CFG_BASE + 0x52F8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_63_REG \ + (CSR_MBIX_CFG_BASE + 0x52FC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_64_REG \ + (CSR_MBIX_CFG_BASE + 0x5300) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_65_REG \ + (CSR_MBIX_CFG_BASE + 0x5304) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_66_REG \ + (CSR_MBIX_CFG_BASE + 0x5308) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_67_REG \ + (CSR_MBIX_CFG_BASE + 0x530C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_68_REG \ + (CSR_MBIX_CFG_BASE + 0x5310) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_69_REG \ + (CSR_MBIX_CFG_BASE + 0x5314) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_70_REG \ + (CSR_MBIX_CFG_BASE + 0x5318) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_71_REG \ + (CSR_MBIX_CFG_BASE + 0x531C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_72_REG \ + (CSR_MBIX_CFG_BASE + 0x5320) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_73_REG \ + (CSR_MBIX_CFG_BASE + 0x5324) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_74_REG \ + (CSR_MBIX_CFG_BASE + 0x5328) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_75_REG \ + (CSR_MBIX_CFG_BASE + 0x532C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_76_REG \ + (CSR_MBIX_CFG_BASE + 0x5330) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_77_REG \ + (CSR_MBIX_CFG_BASE + 0x5334) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_78_REG \ + (CSR_MBIX_CFG_BASE + 0x5338) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_79_REG \ + (CSR_MBIX_CFG_BASE + 0x533C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_80_REG \ + (CSR_MBIX_CFG_BASE + 0x5340) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_81_REG \ + (CSR_MBIX_CFG_BASE + 0x5344) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_82_REG \ + (CSR_MBIX_CFG_BASE + 0x5348) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_83_REG \ + (CSR_MBIX_CFG_BASE + 0x534C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_84_REG \ + (CSR_MBIX_CFG_BASE + 0x5350) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_85_REG \ + (CSR_MBIX_CFG_BASE + 0x5354) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_86_REG \ + (CSR_MBIX_CFG_BASE + 0x5358) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_87_REG \ + (CSR_MBIX_CFG_BASE + 0x535C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_88_REG \ + (CSR_MBIX_CFG_BASE + 0x5360) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_89_REG \ + (CSR_MBIX_CFG_BASE + 0x5364) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_90_REG \ + (CSR_MBIX_CFG_BASE + 0x5368) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_91_REG \ + (CSR_MBIX_CFG_BASE + 0x536C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_92_REG \ + (CSR_MBIX_CFG_BASE + 0x5370) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_93_REG \ + (CSR_MBIX_CFG_BASE + 0x5374) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_94_REG \ + (CSR_MBIX_CFG_BASE + 0x5378) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_95_REG \ + (CSR_MBIX_CFG_BASE + 0x537C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_96_REG \ + (CSR_MBIX_CFG_BASE + 0x5380) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_97_REG \ + (CSR_MBIX_CFG_BASE + 0x5384) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_98_REG \ + (CSR_MBIX_CFG_BASE + 0x5388) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_99_REG \ + (CSR_MBIX_CFG_BASE + 0x538C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_100_REG \ + (CSR_MBIX_CFG_BASE + 0x5390) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_101_REG \ + (CSR_MBIX_CFG_BASE + 0x5394) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_102_REG \ + (CSR_MBIX_CFG_BASE + 0x5398) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_103_REG \ + (CSR_MBIX_CFG_BASE + 0x539C) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_104_REG \ + (CSR_MBIX_CFG_BASE + 0x53A0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_105_REG \ + (CSR_MBIX_CFG_BASE + 0x53A4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_106_REG \ + (CSR_MBIX_CFG_BASE + 0x53A8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_107_REG \ + (CSR_MBIX_CFG_BASE + 0x53AC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_108_REG \ + (CSR_MBIX_CFG_BASE + 0x53B0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_109_REG \ + (CSR_MBIX_CFG_BASE + 0x53B4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_110_REG \ + (CSR_MBIX_CFG_BASE + 0x53B8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_111_REG \ + (CSR_MBIX_CFG_BASE + 0x53BC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_112_REG \ + (CSR_MBIX_CFG_BASE + 0x53C0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_113_REG \ + (CSR_MBIX_CFG_BASE + 0x53C4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_114_REG \ + (CSR_MBIX_CFG_BASE + 0x53C8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_115_REG \ + (CSR_MBIX_CFG_BASE + 0x53CC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_116_REG \ + (CSR_MBIX_CFG_BASE + 0x53D0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_117_REG \ + (CSR_MBIX_CFG_BASE + 0x53D4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_118_REG \ + (CSR_MBIX_CFG_BASE + 0x53D8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_119_REG \ + (CSR_MBIX_CFG_BASE + 0x53DC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_120_REG \ + (CSR_MBIX_CFG_BASE + 0x53E0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_121_REG \ + (CSR_MBIX_CFG_BASE + 0x53E4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_122_REG \ + (CSR_MBIX_CFG_BASE + 0x53E8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_123_REG \ + (CSR_MBIX_CFG_BASE + 0x53EC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_124_REG \ + (CSR_MBIX_CFG_BASE + 0x53F0) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_125_REG \ + (CSR_MBIX_CFG_BASE + 0x53F4) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_126_REG \ + (CSR_MBIX_CFG_BASE + 0x53F8) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX5_VECTOR_127_REG \ + (CSR_MBIX_CFG_BASE + 0x53FC) /* MBIG5的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_TRIG_TYPER_0_REG (CSR_MBIX_CFG_BASE + 0x6000) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX6_TRIG_TYPER_1_REG (CSR_MBIX_CFG_BASE + 0x6004) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX6_TRIG_TYPER_2_REG (CSR_MBIX_CFG_BASE + 0x6008) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX6_TRIG_TYPER_3_REG (CSR_MBIX_CFG_BASE + 0x600C) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_0_REG \ + (CSR_MBIX_CFG_BASE + 0x6200) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_1_REG \ + (CSR_MBIX_CFG_BASE + 0x6204) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_2_REG \ + (CSR_MBIX_CFG_BASE + 0x6208) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_3_REG \ + (CSR_MBIX_CFG_BASE + 0x620C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_4_REG \ + (CSR_MBIX_CFG_BASE + 0x6210) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_5_REG \ + (CSR_MBIX_CFG_BASE + 0x6214) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_6_REG \ + (CSR_MBIX_CFG_BASE + 0x6218) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_7_REG \ + (CSR_MBIX_CFG_BASE + 0x621C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_8_REG \ + (CSR_MBIX_CFG_BASE + 0x6220) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_9_REG \ + (CSR_MBIX_CFG_BASE + 0x6224) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_10_REG \ + (CSR_MBIX_CFG_BASE + 0x6228) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_11_REG \ + (CSR_MBIX_CFG_BASE + 0x622C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_12_REG \ + (CSR_MBIX_CFG_BASE + 0x6230) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_13_REG \ + (CSR_MBIX_CFG_BASE + 0x6234) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_14_REG \ + (CSR_MBIX_CFG_BASE + 0x6238) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_15_REG \ + (CSR_MBIX_CFG_BASE + 0x623C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_16_REG \ + (CSR_MBIX_CFG_BASE + 0x6240) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_17_REG \ + (CSR_MBIX_CFG_BASE + 0x6244) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_18_REG \ + (CSR_MBIX_CFG_BASE + 0x6248) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_19_REG \ + (CSR_MBIX_CFG_BASE + 0x624C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_20_REG \ + (CSR_MBIX_CFG_BASE + 0x6250) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_21_REG \ + (CSR_MBIX_CFG_BASE + 0x6254) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_22_REG \ + (CSR_MBIX_CFG_BASE + 0x6258) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_23_REG \ + (CSR_MBIX_CFG_BASE + 0x625C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_24_REG \ + (CSR_MBIX_CFG_BASE + 0x6260) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_25_REG \ + (CSR_MBIX_CFG_BASE + 0x6264) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_26_REG \ + (CSR_MBIX_CFG_BASE + 0x6268) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_27_REG \ + (CSR_MBIX_CFG_BASE + 0x626C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_28_REG \ + (CSR_MBIX_CFG_BASE + 0x6270) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_29_REG \ + (CSR_MBIX_CFG_BASE + 0x6274) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_30_REG \ + (CSR_MBIX_CFG_BASE + 0x6278) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_31_REG \ + (CSR_MBIX_CFG_BASE + 0x627C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_32_REG \ + (CSR_MBIX_CFG_BASE + 0x6280) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_33_REG \ + (CSR_MBIX_CFG_BASE + 0x6284) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_34_REG \ + (CSR_MBIX_CFG_BASE + 0x6288) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_35_REG \ + (CSR_MBIX_CFG_BASE + 0x628C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_36_REG \ + (CSR_MBIX_CFG_BASE + 0x6290) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_37_REG \ + (CSR_MBIX_CFG_BASE + 0x6294) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_38_REG \ + (CSR_MBIX_CFG_BASE + 0x6298) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_39_REG \ + (CSR_MBIX_CFG_BASE + 0x629C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_40_REG \ + (CSR_MBIX_CFG_BASE + 0x62A0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_41_REG \ + (CSR_MBIX_CFG_BASE + 0x62A4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_42_REG \ + (CSR_MBIX_CFG_BASE + 0x62A8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_43_REG \ + (CSR_MBIX_CFG_BASE + 0x62AC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_44_REG \ + (CSR_MBIX_CFG_BASE + 0x62B0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_45_REG \ + (CSR_MBIX_CFG_BASE + 0x62B4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_46_REG \ + (CSR_MBIX_CFG_BASE + 0x62B8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_47_REG \ + (CSR_MBIX_CFG_BASE + 0x62BC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_48_REG \ + (CSR_MBIX_CFG_BASE + 0x62C0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_49_REG \ + (CSR_MBIX_CFG_BASE + 0x62C4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_50_REG \ + (CSR_MBIX_CFG_BASE + 0x62C8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_51_REG \ + (CSR_MBIX_CFG_BASE + 0x62CC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_52_REG \ + (CSR_MBIX_CFG_BASE + 0x62D0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_53_REG \ + (CSR_MBIX_CFG_BASE + 0x62D4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_54_REG \ + (CSR_MBIX_CFG_BASE + 0x62D8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_55_REG \ + (CSR_MBIX_CFG_BASE + 0x62DC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_56_REG \ + (CSR_MBIX_CFG_BASE + 0x62E0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_57_REG \ + (CSR_MBIX_CFG_BASE + 0x62E4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_58_REG \ + (CSR_MBIX_CFG_BASE + 0x62E8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_59_REG \ + (CSR_MBIX_CFG_BASE + 0x62EC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_60_REG \ + (CSR_MBIX_CFG_BASE + 0x62F0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_61_REG \ + (CSR_MBIX_CFG_BASE + 0x62F4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_62_REG \ + (CSR_MBIX_CFG_BASE + 0x62F8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_63_REG \ + (CSR_MBIX_CFG_BASE + 0x62FC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_64_REG \ + (CSR_MBIX_CFG_BASE + 0x6300) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_65_REG \ + (CSR_MBIX_CFG_BASE + 0x6304) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_66_REG \ + (CSR_MBIX_CFG_BASE + 0x6308) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_67_REG \ + (CSR_MBIX_CFG_BASE + 0x630C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_68_REG \ + (CSR_MBIX_CFG_BASE + 0x6310) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_69_REG \ + (CSR_MBIX_CFG_BASE + 0x6314) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_70_REG \ + (CSR_MBIX_CFG_BASE + 0x6318) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_71_REG \ + (CSR_MBIX_CFG_BASE + 0x631C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_72_REG \ + (CSR_MBIX_CFG_BASE + 0x6320) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_73_REG \ + (CSR_MBIX_CFG_BASE + 0x6324) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_74_REG \ + (CSR_MBIX_CFG_BASE + 0x6328) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_75_REG \ + (CSR_MBIX_CFG_BASE + 0x632C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_76_REG \ + (CSR_MBIX_CFG_BASE + 0x6330) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_77_REG \ + (CSR_MBIX_CFG_BASE + 0x6334) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_78_REG \ + (CSR_MBIX_CFG_BASE + 0x6338) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_79_REG \ + (CSR_MBIX_CFG_BASE + 0x633C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_80_REG \ + (CSR_MBIX_CFG_BASE + 0x6340) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_81_REG \ + (CSR_MBIX_CFG_BASE + 0x6344) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_82_REG \ + (CSR_MBIX_CFG_BASE + 0x6348) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_83_REG \ + (CSR_MBIX_CFG_BASE + 0x634C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_84_REG \ + (CSR_MBIX_CFG_BASE + 0x6350) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_85_REG \ + (CSR_MBIX_CFG_BASE + 0x6354) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_86_REG \ + (CSR_MBIX_CFG_BASE + 0x6358) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_87_REG \ + (CSR_MBIX_CFG_BASE + 0x635C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_88_REG \ + (CSR_MBIX_CFG_BASE + 0x6360) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_89_REG \ + (CSR_MBIX_CFG_BASE + 0x6364) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_90_REG \ + (CSR_MBIX_CFG_BASE + 0x6368) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_91_REG \ + (CSR_MBIX_CFG_BASE + 0x636C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_92_REG \ + (CSR_MBIX_CFG_BASE + 0x6370) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_93_REG \ + (CSR_MBIX_CFG_BASE + 0x6374) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_94_REG \ + (CSR_MBIX_CFG_BASE + 0x6378) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_95_REG \ + (CSR_MBIX_CFG_BASE + 0x637C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_96_REG \ + (CSR_MBIX_CFG_BASE + 0x6380) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_97_REG \ + (CSR_MBIX_CFG_BASE + 0x6384) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_98_REG \ + (CSR_MBIX_CFG_BASE + 0x6388) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_99_REG \ + (CSR_MBIX_CFG_BASE + 0x638C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_100_REG \ + (CSR_MBIX_CFG_BASE + 0x6390) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_101_REG \ + (CSR_MBIX_CFG_BASE + 0x6394) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_102_REG \ + (CSR_MBIX_CFG_BASE + 0x6398) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_103_REG \ + (CSR_MBIX_CFG_BASE + 0x639C) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_104_REG \ + (CSR_MBIX_CFG_BASE + 0x63A0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_105_REG \ + (CSR_MBIX_CFG_BASE + 0x63A4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_106_REG \ + (CSR_MBIX_CFG_BASE + 0x63A8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_107_REG \ + (CSR_MBIX_CFG_BASE + 0x63AC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_108_REG \ + (CSR_MBIX_CFG_BASE + 0x63B0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_109_REG \ + (CSR_MBIX_CFG_BASE + 0x63B4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_110_REG \ + (CSR_MBIX_CFG_BASE + 0x63B8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_111_REG \ + (CSR_MBIX_CFG_BASE + 0x63BC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_112_REG \ + (CSR_MBIX_CFG_BASE + 0x63C0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_113_REG \ + (CSR_MBIX_CFG_BASE + 0x63C4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_114_REG \ + (CSR_MBIX_CFG_BASE + 0x63C8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_115_REG \ + (CSR_MBIX_CFG_BASE + 0x63CC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_116_REG \ + (CSR_MBIX_CFG_BASE + 0x63D0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_117_REG \ + (CSR_MBIX_CFG_BASE + 0x63D4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_118_REG \ + (CSR_MBIX_CFG_BASE + 0x63D8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_119_REG \ + (CSR_MBIX_CFG_BASE + 0x63DC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_120_REG \ + (CSR_MBIX_CFG_BASE + 0x63E0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_121_REG \ + (CSR_MBIX_CFG_BASE + 0x63E4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_122_REG \ + (CSR_MBIX_CFG_BASE + 0x63E8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_123_REG \ + (CSR_MBIX_CFG_BASE + 0x63EC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_124_REG \ + (CSR_MBIX_CFG_BASE + 0x63F0) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_125_REG \ + (CSR_MBIX_CFG_BASE + 0x63F4) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_126_REG \ + (CSR_MBIX_CFG_BASE + 0x63F8) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX6_VECTOR_127_REG \ + (CSR_MBIX_CFG_BASE + 0x63FC) /* MBIG6的LPI管脚对应的中断配置寄存器lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_TRIGE_TYPER_0_REG (CSR_MBIX_CFG_BASE + 0x7000) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX7_TRIGE_TYPER_1_REG (CSR_MBIX_CFG_BASE + 0x7004) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX7_TRIGE_TYPER_2_REG (CSR_MBIX_CFG_BASE + 0x7008) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX7_TRIGE_TYPER_3_REG (CSR_MBIX_CFG_BASE + 0x700C) /* 中断触发类型配置寄存器 */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_0_REG \ + (CSR_MBIX_CFG_BASE + 0x7200) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_1_REG \ + (CSR_MBIX_CFG_BASE + 0x7204) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_2_REG \ + (CSR_MBIX_CFG_BASE + 0x7208) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_3_REG \ + (CSR_MBIX_CFG_BASE + 0x720C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_4_REG \ + (CSR_MBIX_CFG_BASE + 0x7210) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_5_REG \ + (CSR_MBIX_CFG_BASE + 0x7214) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_6_REG \ + (CSR_MBIX_CFG_BASE + 0x7218) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_7_REG \ + (CSR_MBIX_CFG_BASE + 0x721C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_8_REG \ + (CSR_MBIX_CFG_BASE + 0x7220) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_9_REG \ + (CSR_MBIX_CFG_BASE + 0x7224) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_10_REG \ + (CSR_MBIX_CFG_BASE + 0x7228) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_11_REG \ + (CSR_MBIX_CFG_BASE + 0x722C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_12_REG \ + (CSR_MBIX_CFG_BASE + 0x7230) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_13_REG \ + (CSR_MBIX_CFG_BASE + 0x7234) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_14_REG \ + (CSR_MBIX_CFG_BASE + 0x7238) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_15_REG \ + (CSR_MBIX_CFG_BASE + 0x723C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_16_REG \ + (CSR_MBIX_CFG_BASE + 0x7240) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_17_REG \ + (CSR_MBIX_CFG_BASE + 0x7244) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_18_REG \ + (CSR_MBIX_CFG_BASE + 0x7248) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_19_REG \ + (CSR_MBIX_CFG_BASE + 0x724C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_20_REG \ + (CSR_MBIX_CFG_BASE + 0x7250) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_21_REG \ + (CSR_MBIX_CFG_BASE + 0x7254) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_22_REG \ + (CSR_MBIX_CFG_BASE + 0x7258) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_23_REG \ + (CSR_MBIX_CFG_BASE + 0x725C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_24_REG \ + (CSR_MBIX_CFG_BASE + 0x7260) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_25_REG \ + (CSR_MBIX_CFG_BASE + 0x7264) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_26_REG \ + (CSR_MBIX_CFG_BASE + 0x7268) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_27_REG \ + (CSR_MBIX_CFG_BASE + 0x726C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_28_REG \ + (CSR_MBIX_CFG_BASE + 0x7270) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_29_REG \ + (CSR_MBIX_CFG_BASE + 0x7274) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_30_REG \ + (CSR_MBIX_CFG_BASE + 0x7278) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_31_REG \ + (CSR_MBIX_CFG_BASE + 0x727C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_32_REG \ + (CSR_MBIX_CFG_BASE + 0x7280) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_33_REG \ + (CSR_MBIX_CFG_BASE + 0x7284) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_34_REG \ + (CSR_MBIX_CFG_BASE + 0x7288) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_35_REG \ + (CSR_MBIX_CFG_BASE + 0x728C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_36_REG \ + (CSR_MBIX_CFG_BASE + 0x7290) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_37_REG \ + (CSR_MBIX_CFG_BASE + 0x7294) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_38_REG \ + (CSR_MBIX_CFG_BASE + 0x7298) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_39_REG \ + (CSR_MBIX_CFG_BASE + 0x729C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_40_REG \ + (CSR_MBIX_CFG_BASE + 0x72A0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_41_REG \ + (CSR_MBIX_CFG_BASE + 0x72A4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_42_REG \ + (CSR_MBIX_CFG_BASE + 0x72A8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_43_REG \ + (CSR_MBIX_CFG_BASE + 0x72AC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_44_REG \ + (CSR_MBIX_CFG_BASE + 0x72B0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_45_REG \ + (CSR_MBIX_CFG_BASE + 0x72B4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_46_REG \ + (CSR_MBIX_CFG_BASE + 0x72B8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_47_REG \ + (CSR_MBIX_CFG_BASE + 0x72BC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_48_REG \ + (CSR_MBIX_CFG_BASE + 0x72C0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_49_REG \ + (CSR_MBIX_CFG_BASE + 0x72C4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_50_REG \ + (CSR_MBIX_CFG_BASE + 0x72C8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_51_REG \ + (CSR_MBIX_CFG_BASE + 0x72CC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_52_REG \ + (CSR_MBIX_CFG_BASE + 0x72D0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_53_REG \ + (CSR_MBIX_CFG_BASE + 0x72D4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_54_REG \ + (CSR_MBIX_CFG_BASE + 0x72D8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_55_REG \ + (CSR_MBIX_CFG_BASE + 0x72DC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_56_REG \ + (CSR_MBIX_CFG_BASE + 0x72E0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_57_REG \ + (CSR_MBIX_CFG_BASE + 0x72E4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_58_REG \ + (CSR_MBIX_CFG_BASE + 0x72E8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_59_REG \ + (CSR_MBIX_CFG_BASE + 0x72EC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_60_REG \ + (CSR_MBIX_CFG_BASE + 0x72F0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_61_REG \ + (CSR_MBIX_CFG_BASE + 0x72F4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_62_REG \ + (CSR_MBIX_CFG_BASE + 0x72F8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_63_REG \ + (CSR_MBIX_CFG_BASE + 0x72FC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_64_REG \ + (CSR_MBIX_CFG_BASE + 0x7300) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_65_REG \ + (CSR_MBIX_CFG_BASE + 0x7304) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_66_REG \ + (CSR_MBIX_CFG_BASE + 0x7308) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_67_REG \ + (CSR_MBIX_CFG_BASE + 0x730C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_68_REG \ + (CSR_MBIX_CFG_BASE + 0x7310) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_69_REG \ + (CSR_MBIX_CFG_BASE + 0x7314) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_70_REG \ + (CSR_MBIX_CFG_BASE + 0x7318) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_71_REG \ + (CSR_MBIX_CFG_BASE + 0x731C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_72_REG \ + (CSR_MBIX_CFG_BASE + 0x7320) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_73_REG \ + (CSR_MBIX_CFG_BASE + 0x7324) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_74_REG \ + (CSR_MBIX_CFG_BASE + 0x7328) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_75_REG \ + (CSR_MBIX_CFG_BASE + 0x732C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_76_REG \ + (CSR_MBIX_CFG_BASE + 0x7330) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_77_REG \ + (CSR_MBIX_CFG_BASE + 0x7334) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_78_REG \ + (CSR_MBIX_CFG_BASE + 0x7338) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_79_REG \ + (CSR_MBIX_CFG_BASE + 0x733C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_80_REG \ + (CSR_MBIX_CFG_BASE + 0x7340) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_81_REG \ + (CSR_MBIX_CFG_BASE + 0x7344) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_82_REG \ + (CSR_MBIX_CFG_BASE + 0x7348) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_83_REG \ + (CSR_MBIX_CFG_BASE + 0x734C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_84_REG \ + (CSR_MBIX_CFG_BASE + 0x7350) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_85_REG \ + (CSR_MBIX_CFG_BASE + 0x7354) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_86_REG \ + (CSR_MBIX_CFG_BASE + 0x7358) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_87_REG \ + (CSR_MBIX_CFG_BASE + 0x735C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_88_REG \ + (CSR_MBIX_CFG_BASE + 0x7360) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_89_REG \ + (CSR_MBIX_CFG_BASE + 0x7364) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_90_REG \ + (CSR_MBIX_CFG_BASE + 0x7368) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_91_REG \ + (CSR_MBIX_CFG_BASE + 0x736C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_92_REG \ + (CSR_MBIX_CFG_BASE + 0x7370) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_93_REG \ + (CSR_MBIX_CFG_BASE + 0x7374) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_94_REG \ + (CSR_MBIX_CFG_BASE + 0x7378) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_95_REG \ + (CSR_MBIX_CFG_BASE + 0x737C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_96_REG \ + (CSR_MBIX_CFG_BASE + 0x7380) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_97_REG \ + (CSR_MBIX_CFG_BASE + 0x7384) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_98_REG \ + (CSR_MBIX_CFG_BASE + 0x7388) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_99_REG \ + (CSR_MBIX_CFG_BASE + 0x738C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_100_REG \ + (CSR_MBIX_CFG_BASE + 0x7390) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_101_REG \ + (CSR_MBIX_CFG_BASE + 0x7394) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_102_REG \ + (CSR_MBIX_CFG_BASE + 0x7398) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_103_REG \ + (CSR_MBIX_CFG_BASE + 0x739C) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_104_REG \ + (CSR_MBIX_CFG_BASE + 0x73A0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_105_REG \ + (CSR_MBIX_CFG_BASE + 0x73A4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_106_REG \ + (CSR_MBIX_CFG_BASE + 0x73A8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_107_REG \ + (CSR_MBIX_CFG_BASE + 0x73AC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_108_REG \ + (CSR_MBIX_CFG_BASE + 0x73B0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_109_REG \ + (CSR_MBIX_CFG_BASE + 0x73B4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_110_REG \ + (CSR_MBIX_CFG_BASE + 0x73B8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_111_REG \ + (CSR_MBIX_CFG_BASE + 0x73BC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_112_REG \ + (CSR_MBIX_CFG_BASE + 0x73C0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_113_REG \ + (CSR_MBIX_CFG_BASE + 0x73C4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_114_REG \ + (CSR_MBIX_CFG_BASE + 0x73C8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_115_REG \ + (CSR_MBIX_CFG_BASE + 0x73CC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_116_REG \ + (CSR_MBIX_CFG_BASE + 0x73D0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_117_REG \ + (CSR_MBIX_CFG_BASE + 0x73D4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_118_REG \ + (CSR_MBIX_CFG_BASE + 0x73D8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_119_REG \ + (CSR_MBIX_CFG_BASE + 0x73DC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_120_REG \ + (CSR_MBIX_CFG_BASE + 0x73E0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_121_REG \ + (CSR_MBIX_CFG_BASE + 0x73E4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_122_REG \ + (CSR_MBIX_CFG_BASE + 0x73E8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_123_REG \ + (CSR_MBIX_CFG_BASE + 0x73EC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_124_REG \ + (CSR_MBIX_CFG_BASE + 0x73F0) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_125_REG \ + (CSR_MBIX_CFG_BASE + 0x73F4) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_126_REG \ + (CSR_MBIX_CFG_BASE + 0x73F8) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX7_VECTOR_127_REG \ + (CSR_MBIX_CFG_BASE + 0x73FC) /* MBIG7的LPI管脚对应的中断配置寄存器。lpi_num{127,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_0_REG (CSR_MBIX_CFG_BASE + 0xA000) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_1_REG (CSR_MBIX_CFG_BASE + 0xA004) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_2_REG (CSR_MBIX_CFG_BASE + 0xA008) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_3_REG (CSR_MBIX_CFG_BASE + 0xA00C) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_4_REG (CSR_MBIX_CFG_BASE + 0xA010) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_5_REG (CSR_MBIX_CFG_BASE + 0xA014) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_6_REG (CSR_MBIX_CFG_BASE + 0xA018) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_7_REG (CSR_MBIX_CFG_BASE + 0xA01C) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_8_REG (CSR_MBIX_CFG_BASE + 0xA020) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_9_REG (CSR_MBIX_CFG_BASE + 0xA024) /* MBIX中断active状态清除寄存器。int_group{29,0} \ + */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_10_REG \ + (CSR_MBIX_CFG_BASE + 0xA028) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_11_REG \ + (CSR_MBIX_CFG_BASE + 0xA02C) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_12_REG \ + (CSR_MBIX_CFG_BASE + 0xA030) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_13_REG \ + (CSR_MBIX_CFG_BASE + 0xA034) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_14_REG \ + (CSR_MBIX_CFG_BASE + 0xA038) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_15_REG \ + (CSR_MBIX_CFG_BASE + 0xA03C) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_16_REG \ + (CSR_MBIX_CFG_BASE + 0xA040) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_17_REG \ + (CSR_MBIX_CFG_BASE + 0xA044) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_18_REG \ + (CSR_MBIX_CFG_BASE + 0xA048) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_19_REG \ + (CSR_MBIX_CFG_BASE + 0xA04C) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_20_REG \ + (CSR_MBIX_CFG_BASE + 0xA050) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_21_REG \ + (CSR_MBIX_CFG_BASE + 0xA054) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_22_REG \ + (CSR_MBIX_CFG_BASE + 0xA058) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_23_REG \ + (CSR_MBIX_CFG_BASE + 0xA05C) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_24_REG \ + (CSR_MBIX_CFG_BASE + 0xA060) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_25_REG \ + (CSR_MBIX_CFG_BASE + 0xA064) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_26_REG \ + (CSR_MBIX_CFG_BASE + 0xA068) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_27_REG \ + (CSR_MBIX_CFG_BASE + 0xA06C) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_28_REG \ + (CSR_MBIX_CFG_BASE + 0xA070) /* MBIX中断active状态清除寄存器。int_group{29,0} */ +#define CSR_MBIX_CFG_MBIX_INT_CLR_29_REG \ + (CSR_MBIX_CFG_BASE + 0xA074) /* MBIX中断active状态清除寄存器。int_group{29,0} */ + +#endif // MBIGEN_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/pcie4_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/pcie4_c_union_define.h new file mode 100644 index 000000000..a93eff36b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/pcie4_c_union_define.h @@ -0,0 +1,5992 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : pcie4_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/29 22:14:57 Create file +// ****************************************************************************** + +#ifndef PCIE4_C_UNION_DEFINE_H +#define PCIE4_C_UNION_DEFINE_H + +/* Define the union csr_iob_rxatu_control_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_en : 1; /* [0] */ + u32 iob_rxatu_func_mode : 1; /* [1] */ + u32 rsv_0 : 2; /* [3:2] */ + u32 iob_rxatu_cache : 4; /* [7:4] */ + u32 iob_rxatu_snoop : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_control_0_u; + +/* Define the union csr_iob_rxatu_control_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_bar_num : 3; /* [2:0] */ + u32 iob_rxatu_pf_num : 3; /* [5:3] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 iob_rxatu_vf_start_num : 8; /* [15:8] */ + u32 iob_rxatu_vf_end_num : 8; /* [23:16] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_control_1_u; + +/* Define the union csr_iob_rxatu_control_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_ext_region_size : 20; /* [19:0] */ + u32 rsv_4 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_control_2_u; + +/* Define the union csr_iob_rxatu_region_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_5 : 8; /* [7:0] */ + u32 iob_rxatu_region_size : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_region_size_u; + +/* Define the union csr_iob_rxatu_base_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 8; /* [7:0] */ + u32 iob_rxatu_base_addr_l : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_base_addr_l_u; + +/* Define the union csr_iob_rxatu_base_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_base_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_base_addr_h_u; + +/* Define the union csr_iob_rxatu_tar_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 8; /* [7:0] */ + u32 iob_rxatu_tar_addr_l : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_tar_addr_l_u; + +/* Define the union csr_iob_rxatu_tar_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iob_rxatu_tar_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rxatu_tar_addr_h_u; + +/* Define the union csr_iob_rx_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 snap_en : 1; /* [1] */ + u32 rsv_8 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_cnt_clr_ce_u; + +/* Define the union csr_iob_rx_tlp_cnt_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_np : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_np_u; + +/* Define the union csr_iob_rx_tlp_cnt_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_p_u; + +/* Define the union csr_iob_rx_tlp_cnt_cpl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_cpl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_cpl_u; + +/* Define the union csr_iob_rx_tlp_cnt_msix_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_msix : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_msix_u; + +/* Define the union csr_iob_rx_tlp_cnt_np_p2p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_np_p2p : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_np_p2p_u; + +/* Define the union csr_iob_rx_tlp_cnt_p_p2p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_p_p2p : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_p_p2p_u; + +/* Define the union csr_iob_rx_tlp_cnt_cpl_p2p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_cpl_p2p : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_cpl_p2p_u; + +/* Define the union csr_iob_rx_tlp_cnt_np_odr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_np_odr : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_np_odr_u; + +/* Define the union csr_iob_rx_tlp_cnt_p_odr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_p_odr : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_p_odr_u; + +/* Define the union csr_iob_rx_tlp_cnt_haq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_haq : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_haq_u; + +/* Define the union csr_iob_rx_tlp_cnt_np_aer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_np_aer : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_np_aer_u; + +/* Define the union csr_iob_rx_tlp_cnt_p_aer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cnt_p_aer : 8; /* [7:0] */ + u32 rsv_16 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_tlp_cnt_p_aer_u; + +/* Define the union csr_iob_rx_pre_err_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_pre_err_sts : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_pre_err_sts_u; + +/* Define the union csr_iob_rx_np_pkt_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_np_pkt_num : 24; /* [23:0] */ + u32 rsv_18 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_np_pkt_num_u; + +/* Define the union csr_iob_rx_p_pkt_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_p_pkt_num : 24; /* [23:0] */ + u32 rsv_19 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_p_pkt_num_u; + +/* Define the union csr_iob_rx_cpl_pkt_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_cpl_pkt_num : 24; /* [23:0] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_cpl_pkt_num_u; + +/* Define the union csr_apat_dfx_ats_inv_lkdn_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_inv_lkdn_clr_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_ats_inv_lkdn_clr_u; + +/* Define the union csr_apat_dfx_sync_wait_rls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sync_wait_rls_entry_num : 9; /* [8:0] */ + u32 rsv_21 : 3; /* [11:9] */ + u32 dfx_sync_bypass_inv_num : 5; /* [16:12] */ + u32 rsv_22 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_sync_wait_rls_u; + +/* Define the union csr_apat_idle_set_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_idle_set_cfg : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_idle_set_cfg_u; + +/* Define the union csr_apat_req_entry_rd_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_entry_rd_idx : 8; /* [7:0] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_req_entry_rd_idx_u; + +/* Define the union csr_apat_req_entry_rd_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_entry_rd_done : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_req_entry_rd_done_u; + +/* Define the union csr_apat_req_entry_rdata0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_entry_atc : 1; /* [0] */ + u32 req_entry_nosnoop : 1; /* [1] */ + u32 req_entry_va_31_2 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_req_entry_rdata0_u; + +/* Define the union csr_apat_req_entry_rdata1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_entry_va_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_req_entry_rdata1_u; + +/* Define the union csr_apat_req_entry_rdata2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_entry_sid : 16; /* [15:0] */ + u32 req_entry_ssid : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_req_entry_rdata2_u; + +/* Define the union csr_apat_req_entry_rdata3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_entry_ssv : 1; /* [0] */ + u32 req_entry_pri : 1; /* [1] */ + u32 req_entry_exe : 1; /* [2] */ + u32 req_entry_isatomic : 1; /* [3] */ + u32 req_entry_txnid : 7; /* [10:4] */ + u32 req_entry_np : 1; /* [11] */ + u32 req_entry_nw : 1; /* [12] */ + u32 req_entry_core_num : 2; /* [14:13] */ + u32 req_entry_sync_clr_flag : 1; /* [15] */ + u32 req_entry_tlbi_flag : 1; /* [16] */ + u32 reg_entry_vmid : 4; /* [20:17] */ + u32 req_entry_page_size : 2; /* [22:21] */ + u32 req_entry_issue_no_rslt : 1; /* [23] */ + u32 req_entry_issue : 1; /* [24] */ + u32 req_entry_times : 1; /* [25] */ + u32 req_entry_wait_rls : 1; /* [26] */ + u32 rsv_26 : 1; /* [27] */ + u32 req_entry_retry : 1; /* [28] */ + u32 req_entry_write : 1; /* [29] */ + u32 req_entry_atc_vld : 1; /* [30] */ + u32 req_entry_iob_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_req_entry_rdata3_u; + +/* Define the union csr_apat_ats_translation_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ats_rx_np_idle : 20; /* [19:0] */ + u32 rsv_27 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ats_translation_idle_u; + +/* Define the union csr_apat_ats_pri_idle_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ats_rx_cp_idle : 20; /* [19:0] */ + u32 rsv_28 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ats_pri_idle_u; + +/* Define the union csr_apat_int_ro_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_int_ro_ce : 1; /* [0] */ + u32 rsv_29 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_ro_ce_u; + +/* Define the union csr_apat_int_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_int_ro_nfe : 2; /* [1:0] */ + u32 rsv_30 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_ro_nfe_u; + +/* Define the union csr_apat_int_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_int_ro_fe : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_ro_fe_u; + +/* Define the union csr_apat_int_severity_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int_severity_cfg : 2; /* [1:0] */ + u32 rsv_32 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_severity_u; + +/* Define the union csr_apat_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int_set_cfg : 2; /* [1:0] */ + u32 rsv_33 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_set_u; + +/* Define the union csr_apat_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int_mask_cfg : 2; /* [1:0] */ + u32 rsv_34 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_mask_u; + +/* Define the union csr_apat_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int_status : 2; /* [1:0] */ + u32 rsv_35 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_status_u; + +/* Define the union csr_apat_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_int : 2; /* [1:0] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_int_ro_u; + +/* Define the union csr_apat_translation_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_apat_tlb_predictor_off : 1; /* [0] */ + u32 cfg_apat_forbid_tlb_lock : 1; /* [1] */ + u32 cfg_apat_forbid_tlb_invalidate : 1; /* [2] */ + u32 cfg_apat_core0_ptw_chnl : 1; /* [3] */ + u32 cfg_apat_core1_ptw_chnl : 1; /* [4] */ + u32 cfg_apat_core2_ptw_chnl : 1; /* [5] */ + u32 cfg_apat_keep_src_hint : 1; /* [6] */ + u32 cfg_apat_regen_retry_hint : 1; /* [7] */ + u32 cfg_apat_req_inval_0 : 1; /* [8] */ + u32 cfg_apat_req_inval_1 : 1; /* [9] */ + u32 cfg_apat_req_inval_2 : 1; /* [10] */ + u32 cfg_apat_req_inval_3 : 1; /* [11] */ + u32 cfg_apat_req_retry_inval : 4; /* [15:12] */ + u32 cfg_apat_nopasid_pri : 1; /* [16] */ + u32 cfg_apat_nopasid_exe : 1; /* [17] */ + u32 cfg_apat_disable_inboud_nosnoop : 1; /* [18] */ + u32 cfg_apat_disable_pasid : 1; /* [19] */ + u32 cfg_apat_unaddr_exe_wr_ur : 1; /* [20] */ + u32 cfg_sync_clr_all_stale_entry : 1; /* [21] */ + u32 cfg_sync_clr_all_no_rsp_entry : 1; /* [22] */ + u32 cfg_ats_pasid_mode : 1; /* [23] */ + u32 cfg_apat_default_memattr : 4; /* [27:24] */ + u32 cfg_apat_default_snoop : 1; /* [28] */ + u32 cfg_apat_enable_nc_atomic : 1; /* [29] */ + u32 cfg_conf_inv_all_rsp_entry : 1; /* [30] */ + u32 cfg_tlb_inv_all_rsp_entry : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_translation_cfg_u; + +/* Define the union csr_apat_translation_retry_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_apat_max_retry_req_num : 8; /* [7:0] */ + u32 cfg_apat_max_ptw_req_num : 8; /* [15:8] */ + u32 cfg_apat_ptw_req_glitch_filter : 4; /* [19:16] */ + u32 cfg_req_entry_rls_mode : 1; /* [20] */ + u32 cfg_inv_record_mode : 1; /* [21] */ + u32 cfg_apat_tlbi_vav_disable : 1; /* [22] */ + u32 cfg_ats_global_rsp_en : 1; /* [23] */ + u32 cfg_lkup_bypass_en : 4; /* [27:24] */ + u32 cfg_pri_ovackflg_mode : 1; /* [28] */ + u32 cfg_pri_ovflg_up_mode : 1; /* [29] */ + u32 cfg_pri_ovflg_init_value : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_translation_retry_u; + +/* Define the union csr_apat_sync_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_sync_timeout_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_sync_timeout_u; + +/* Define the union csr_apat_lkup_stats_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_stats_src_busnum : 8; /* [7:0] */ + u32 cfg_tlb_lkup_rsp_only_ur : 1; /* [8] */ + u32 cfg_req_va_legal_chk : 1; /* [9] */ + u32 cfg_smmuen_prefix_chk : 1; /* [10] */ + u32 cfg_req_at_res_is_ur : 1; /* [11] */ + u32 rsv_37 : 4; /* [15:12] */ + u32 cfg_event_fault_pop_timeout : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_lkup_stats_cfg_u; + +/* Define the union csr_apat_lkup_req_pct_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_tlb_lkup_consective_req_num : 16; /* [15:0] */ + u32 apat_tlp_lkup_src_retry_in_64k : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_lkup_req_pct_u; + +/* Define the union csr_apat_lkup_req_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_tlp_p_stat_req_num : 12; /* [11:0] */ + u32 apat_tlp_p_stat_total_dwlen : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_lkup_req_length_u; + +/* Define the union csr_apat_np_lkup_req_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_tlp_np_stat_req_num : 12; /* [11:0] */ + u32 apat_tlp_np_stat_total_dwlen : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_np_lkup_req_length_u; + +/* Define the union csr_apat_np_lkup_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_tlb_np_lkup_max_lat : 16; /* [15:0] */ + u32 apat_tlb_np_lkup_ava_lat : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_np_lkup_latency_u; + +/* Define the union csr_apat_p_lkup_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_tlb_p_lkup_max_lat : 16; /* [15:0] */ + u32 apat_tlb_p_lkup_ava_lat : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_p_lkup_latency_u; + +/* Define the union csr_apat_tlb_predictor_hint_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg_va_af_dma_no_less_than_pg_sz_hint_sel : 1; /* [0] */ + u32 cur_dma_len_more_than_rem_pg_sz_half_hint_sel : 1; /* [1] */ + u32 dma_len_equal_4k_hint_sel : 1; /* [2] */ + u32 req_last_be_hint_sel : 1; /* [3] */ + u32 dma_len_not_4dw_times_hint_sel : 1; /* [4] */ + u32 tlp_req_read_hint_cfg : 1; /* [5] */ + u32 page_size_aging_time : 10; /* [15:6] */ + u32 lock_hint_aging_time : 10; /* [25:16] */ + u32 lock_hint_aging_en : 1; /* [26] */ + u32 rsv_38 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_hint_cfg_u; + +/* Define the union csr_apat_tlb_predictor_fifo_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lkup_fifo_full_flag : 1; /* [0] */ + u32 lkup_fifo_empty_flag : 1; /* [1] */ + u32 lkup_fifo_af_flag : 1; /* [2] */ + u32 lkup_fifo_ae_flag : 1; /* [3] */ + u32 lkup_fifo_overf_flag : 1; /* [4] */ + u32 lkup_fifo_fill : 7; /* [11:5] */ + u32 lock_aging_fifo_full_flag : 1; /* [12] */ + u32 lock_aging_fifo_empty_flag : 1; /* [13] */ + u32 lock_aging_fifo_af_flag : 1; /* [14] */ + u32 lock_aging_fifo_ae_flag : 1; /* [15] */ + u32 lock_aging_fifo_overf_flag : 1; /* [16] */ + u32 lock_aging_fifo_fill : 5; /* [21:17] */ + u32 rsv_39 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_fifo_dfx_u; + +/* Define the union csr_apat_tlb_predictor_page_size_cache_performance_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ratio_n4k_page_size_cache_hit : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 ratio_n4k_page_size_cache_miss : 10; /* [25:16] */ + u32 rsv_41 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_page_size_cache_performance_0_u; + +/* Define the union csr_apat_tlb_predictor_page_size_cache_performance_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ratio_n4k_page_size_cache_evict : 10; /* [9:0] */ + u32 rsv_42 : 6; /* [15:10] */ + u32 ratio_n4k_page_size_cache_no_rep : 10; /* [25:16] */ + u32 rsv_43 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_page_size_cache_performance_1_u; + +/* Define the union csr_apat_tlb_predictor_lock_cache_performance_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ratio_lock_aging_cache_hit : 10; /* [9:0] */ + u32 rsv_44 : 6; /* [15:10] */ + u32 ratio_lock_aging_cache_miss : 10; /* [25:16] */ + u32 rsv_45 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_lock_cache_performance_0_u; + +/* Define the union csr_apat_tlb_predictor_lock_cache_performance_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ratio_lock_aging_cache_evict : 10; /* [9:0] */ + u32 rsv_46 : 6; /* [15:10] */ + u32 ratio_lock_aging_cache_no_rep : 10; /* [25:16] */ + u32 rsv_47 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_lock_cache_performance_1_u; + +/* Define the union csr_apat_tlb_predictor_ram_parity_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lkup_ram_parity_o : 1; /* [0] */ + u32 n4k_page_size_ram_parity_o : 1; /* [1] */ + u32 lock_aging_ram_parity_o : 1; /* [2] */ + u32 rsv_48 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_tlb_predictor_ram_parity_dfx_u; + +/* Define the union csr_apat_cnxt_ram_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ram_ecc_err_inj_cfg : 2; /* [1:0] */ + u32 rsv_49 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnxt_ram_ecc_cfg_u; + +/* Define the union csr_apat_cnxt_ram_ecc_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_entry_cnxt_ram_ecc_1bit : 5; /* [4:0] */ + u32 cnt_entry_cnxt_ram_ecc_2bit : 5; /* [9:5] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 entry_cnxt_ram_ecc_info : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnxt_ram_ecc_sts_u; + +/* Define the union csr_apat_dfx_fst_rsp_fault_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_fst_rsp_fault_substrmid : 16; /* [15:0] */ + u32 dfx_fst_rsp_fault_strmid : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_fst_rsp_fault_0_u; + +/* Define the union csr_apat_dfx_fst_rsp_fault_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_fst_rsp_fault_va_low32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_fst_rsp_fault_1_u; + +/* Define the union csr_apat_dfx_fst_rsp_fault_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_fst_rsp_fault_va_high32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_fst_rsp_fault_2_u; + +/* Define the union csr_apat_dfx_fst_rsp_fault_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_fst_rsp_fault_atc : 1; /* [0] */ + u32 dfx_fst_rsp_fault_ssv : 1; /* [1] */ + u32 dfx_fst_rsp_fault_type : 8; /* [9:2] */ + u32 rsv_51 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_fst_rsp_fault_3_u; + +/* Define the union csr_apat_dfx_cnt_invalid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_tlb_inv : 16; /* [15:0] */ + u32 dfx_cnt_cfg_inv : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cnt_invalid_u; + +/* Define the union csr_apat_dfx_cmd_sync_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_cmd_sync : 16; /* [15:0] */ + u32 dfx_sync_timeout_wait_rls_num : 9; /* [24:16] */ + u32 dfx_sync_timeout_bypass_inv_num : 5; /* [29:25] */ + u32 dfx_sync_timeout : 1; /* [30] */ + u32 rsv_52 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cmd_sync_sts_u; + +/* Define the union csr_apat_dfx_sync_max_time_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sync_max_time_interval : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_sync_max_time_u; + +/* Define the union csr_apat_ats_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ats_disable : 1; /* [0] */ + u32 ats_np_prefix_sel : 1; /* [1] */ + u32 cfg_pri_req_ots_mode : 1; /* [2] */ + u32 cfg_ats_pri_stop_mk : 1; /* [3] */ + u32 cfg_ats_request_inval : 4; /* [7:4] */ + u32 apat_req_cxnt_atc_req_max_num : 8; /* [15:8] */ + u32 ats_reg_control : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ats_cfg_u; + +/* Define the union csr_apat_ats_timeout_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ats_reg_timeout_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ats_timeout_l_u; + +/* Define the union csr_apat_ats_timeout_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ats_reg_timeout_h : 8; /* [7:0] */ + u32 cfg_pri_rsp_prefix_mask : 20; /* [27:8] */ + u32 cfg_ats_invcp_linkdown_sta : 1; /* [28] */ + u32 rsv_53 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ats_timeout_h_u; + +/* Define the union csr_apat_ats_priq_irpt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_ats_priq_irpt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ats_priq_irpt_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 substream_id_cfg_0 : 16; /* [15:0] */ + u32 stream_id_cfg_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_0_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 substream_id_cfg_1 : 16; /* [15:0] */ + u32 stream_id_cfg_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_1_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 substream_id_cfg_2 : 16; /* [15:0] */ + u32 stream_id_cfg_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_2_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 substream_id_cfg_3 : 16; /* [15:0] */ + u32 stream_id_cfg_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_3_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 execute_bit_cfg_0 : 1; /* [0] */ + u32 priviledge_bit_cfg_0 : 1; /* [1] */ + u32 rsv_54 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_4_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 execute_bit_cfg_1 : 1; /* [0] */ + u32 priviledge_bit_cfg_1 : 1; /* [1] */ + u32 rsv_55 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_5_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 execute_bit_cfg_2 : 1; /* [0] */ + u32 priviledge_bit_cfg_2 : 1; /* [1] */ + u32 rsv_56 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_6_u; + +/* Define the union csr_apat_xilinx_hook_pasid_cfg_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 execute_bit_cfg_3 : 1; /* [0] */ + u32 priviledge_bit_cfg_3 : 1; /* [1] */ + u32 rsv_57 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_xilinx_hook_pasid_cfg_7_u; + +/* Define the union csr_apat_reqid_pasid_pri_exc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_reqid_pasid_pri_exc_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_reqid_pasid_pri_exc_cfg_u; + +/* Define the union csr_apat_reqid_pasid_pri_exc_rd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_reqid_pasid_pri_exc_rd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_reqid_pasid_pri_exc_rd_u; + +/* Define the union csr_apat_cnt_tlb_lkup_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_tlb_lkup_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_tlb_lkup_req_u; + +/* Define the union csr_apat_cnt_tlb_retried_request_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_tlb_retried_request : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_tlb_retried_request_u; + +/* Define the union csr_apat_cnt_tlb_rsp_success_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_tlb_rsp_success : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_tlb_rsp_success_u; + +/* Define the union csr_apat_cnt_tlb_rsp_fault_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_tlb_rsp_fault : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_tlb_rsp_fault_u; + +/* Define the union csr_apat_cnt_sch_noreissue_request_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_sch_noreissue_request : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_sch_noreissue_request_u; + +/* Define the union csr_apat_cnt_sch_reissue_request_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_sch_reissue_request : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_sch_reissue_request_u; + +/* Define the union csr_apat_cnt_tlb_lkup_aging_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_tlb_lkup_aging_request : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_tlb_lkup_aging_req_u; + +/* Define the union csr_apat_cnt_tlb_aging_req_retried_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_tlb_aging_req_retried : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_cnt_tlb_aging_req_retried_u; + +/* Define the union csr_apat_dfx_ats_trs_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_trs_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_ats_trs_sts_u; + +/* Define the union csr_apat_dfx_ats_inv_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ats_inv_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_ats_inv_sts_u; + +/* Define the union csr_apat_dfx_ats_pri_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_ots_rx_cpl : 7; /* [6:0] */ + u32 cnt_ots_rx_cpl_uf : 1; /* [7] */ + u32 cnt_ots_rx_cpl_of : 1; /* [8] */ + u32 cnt_ots_pri_req : 7; /* [15:9] */ + u32 cnt_ots_pri_req_uf : 1; /* [16] */ + u32 cnt_ots_pri_req_of : 1; /* [17] */ + u32 cnt_ots_brsp_wr_up : 7; /* [24:18] */ + u32 cnt_ots_brsp_wr_up_uf : 1; /* [25] */ + u32 cnt_ots_brsp_wr_up_of : 1; /* [26] */ + u32 priq_emptry : 1; /* [27] */ + u32 priq_full : 1; /* [28] */ + u32 priq_ovflg_disc : 1; /* [29] */ + u32 rsv_58 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_ats_pri_sts_u; + +/* Define the union csr_apat_dfx_cnt_ats_trs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_ats_trs_req : 16; /* [15:0] */ + u32 dfx_cnt_ats_trs_cpl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cnt_ats_trs_u; + +/* Define the union csr_apat_dfx_cnt_ats_inv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_ats_inv_req : 16; /* [15:0] */ + u32 dfx_cnt_ats_inv_cpl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cnt_ats_inv_u; + +/* Define the union csr_apat_dfx_cnt_ats_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_ats_pri_req : 16; /* [15:0] */ + u32 dfx_cnt_ats_pri_cpl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cnt_ats_pri_u; + +/* Define the union csr_apat_dfx_cnt_smmu_inv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_smmu_ats_inv_req : 16; /* [15:0] */ + u32 dfx_cnt_smmu_ats_inv_cpl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cnt_smmu_inv_u; + +/* Define the union csr_apat_dfx_cnt_smmu_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt_smmu_ats_pri_req : 16; /* [15:0] */ + u32 dfx_cnt_smmu_ats_pri_rsp : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_dfx_cnt_smmu_pri_u; + +/* Define the union csr_apat_ib_trig_glb_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_global_mode : 2; /* [1:0] */ + u32 rsv_59 : 2; /* [3:2] */ + u32 apat_trig_status : 1; /* [4] */ + u32 rsv_60 : 3; /* [7:5] */ + u32 apat_trig_traffic_sample_intval : 6; /* [13:8] */ + u32 rsv_61 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_glb_ctrl_u; + +/* Define the union csr_apat_ib_trig_seq_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_tlp_type : 2; /* [1:0] */ + u32 apat_trig_tlp_ro : 1; /* [2] */ + u32 apat_trig_tlp_ep : 1; /* [3] */ + u32 apat_trig_tlp_at : 2; /* [5:4] */ + u32 apat_trig_tlp_length : 10; /* [15:6] */ + u32 apat_trig_tlp_reqid : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_seq_l_u; + +/* Define the union csr_apat_ib_trig_seq_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_tlp_ido : 1; /* [0] */ + u32 apat_trig_tlp_th : 1; /* [1] */ + u32 apat_trig_tlp_ph : 2; /* [3:2] */ + u32 apat_ib_trig_seq_h_res : 1; /* [4] */ + u32 apat_trig_addr26_2 : 25; /* [29:5] */ + u32 apat_trig_addr33_32 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_seq_h_u; + +/* Define the union csr_apat_ib_trig_seq_pasid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_tlp_pasid : 16; /* [15:0] */ + u32 apat_ib_trig_seq_pasid_res_21_16 : 6; /* [21:16] */ + u32 apat_trig_tlp_pasid_exe : 1; /* [22] */ + u32 apat_trig_tlp_pasid_pri : 1; /* [23] */ + u32 apat_ib_trig_seq_pasid_res_31_24 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_seq_pasid_u; + +/* Define the union csr_apat_ib_trig_seq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_tlp_type_en : 1; /* [0] */ + u32 apat_trig_tlp_ro_en : 1; /* [1] */ + u32 apat_trig_tlp_ep_en : 1; /* [2] */ + u32 apat_trig_tlp_at_en : 1; /* [3] */ + u32 apat_trig_tlp_length_en : 1; /* [4] */ + u32 apat_trig_tlp_reqid_en : 1; /* [5] */ + u32 apat_trig_tlp_ido_en : 1; /* [6] */ + u32 apat_trig_tlp_th_en : 1; /* [7] */ + u32 apat_trig_tlp_ph_en : 1; /* [8] */ + u32 apat_trig_tlp_pasid_en : 1; /* [9] */ + u32 apat_trig_tlp_addr_match_style : 3; /* [12:10] */ + u32 apat_ib_trig_seq_ctrl_res_30_13 : 18; /* [30:13] */ + u32 apat_trig_entry_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_seq_ctrl_u; + +/* Define the union csr_apat_ib_trig_rslt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_rslt_tlp_type : 2; /* [1:0] */ + u32 apat_trig_rslt_tlp_ro : 1; /* [2] */ + u32 apat_trig_rslt_tlp_ep : 1; /* [3] */ + u32 apat_trig_rslt_tlp_at : 2; /* [5:4] */ + u32 apat_trig_rslt_tlp_length : 10; /* [15:6] */ + u32 apat_trig_rslt_tlp_reqid : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_rslt_l_u; + +/* Define the union csr_apat_ib_trig_rslt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_rslt_tlp_ido : 1; /* [0] */ + u32 apat_trig_rslt_tlp_th : 1; /* [1] */ + u32 apat_trig_rslt_tlp_ph : 2; /* [3:2] */ + u32 rsv_62 : 1; /* [4] */ + u32 apat_trig_rslt_addr26_2 : 25; /* [29:5] */ + u32 apat_trig_rslt_addr33_32 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_rslt_h_u; + +/* Define the union csr_apat_ib_trig_rslt_pasid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apat_trig_rslt_tlp_pasid : 16; /* [15:0] */ + u32 rsv_63 : 6; /* [21:16] */ + u32 apat_trig_rslt_tlp_pasid_exe : 1; /* [22] */ + u32 apat_trig_rslt_tlp_pasid_pri : 1; /* [23] */ + u32 rsv_64 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apat_ib_trig_rslt_pasid_u; + +/* Define the union csr_am_msi_msix_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_msix_enable : 1; /* [0] */ + u32 rsv_65 : 3; /* [3:1] */ + u32 msi_msix_axicache : 4; /* [7:4] */ + u32 msi_msix_snpattr : 1; /* [8] */ + u32 rsv_66 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_msi_msix_ctrl_u; + +/* Define the union csr_am_msi_msix_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_msix_addr_high : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_msi_msix_addr_high_u; + +/* Define the union csr_am_msi_msix_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_msix_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_msi_msix_addr_low_u; + +/* Define the union csr_ib_smmu_bypass_port_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_smmu_bypass : 20; /* [19:0] */ + u32 rsv_68 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_smmu_bypass_port_en_u; + +/* Define the union csr_ib_atop_endian_format_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_atop_endian_format : 1; /* [0] */ + u32 rsv_69 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_atop_endian_format_u; + +/* Define the union csr_ib_rx_filter_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_atu_abort_mode : 1; /* [0] */ + u32 cfg_msi_msix_prot_abort_mode : 1; /* [1] */ + u32 cfg_msi_msix_prot_mode : 1; /* [2] */ + u32 cfg_rom_hit_filter : 1; /* [3] */ + u32 cfg_prefix_filter : 4; /* [7:4] */ + u32 cfg_vdm_msg_p2p_filter : 1; /* [8] */ + u32 cfg_mctp_msg_p2p_filter : 1; /* [9] */ + u32 cfg_haq_abort_mode : 1; /* [10] */ + u32 cfg_msix_poison_filter : 1; /* [11] */ + u32 cfg_msg_poison_forward : 1; /* [12] */ + u32 cfg_ats_filter_mode : 1; /* [13] */ + u32 cfg_native_poison_filter : 1; /* [14] */ + u32 rsv_70 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_rx_filter_mode_u; + +/* Define the union csr_ib_smmu_bypass_memattr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_smmu_bypass_memattr : 4; /* [3:0] */ + u32 cfg_smmu_bypass_snp : 1; /* [4] */ + u32 rsv_71 : 3; /* [7:5] */ + u32 cfg_disable_req_nosnoop : 1; /* [8] */ + u32 rsv_72 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_smmu_bypass_memattr_u; + +/* Define the union csr_ib_sdi_reg_remap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_nvme_pf_hit_en : 4; /* [3:0] */ + u32 cfg_sdi_nvme_addr_size : 2; /* [5:4] */ + u32 rsv_73 : 2; /* [7:6] */ + u32 cfg_sdi_dma_pf_hit_en : 4; /* [11:8] */ + u32 cfg_sdi_dma_addr_size : 2; /* [13:12] */ + u32 rsv_74 : 2; /* [15:14] */ + u32 cfg_sdi_dma_addr_base : 3; /* [18:16] */ + u32 rsv_75 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_sdi_reg_remap_u; + +/* Define the union csr_cfg_ib_poison_pr_forward_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ib_poison_pr_forward_en : 20; /* [19:0] */ + u32 rsv_76 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_ib_poison_pr_forward_en_u; + +/* Define the union csr_cfg_ib_bar_disp_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ib_bar_disp_sel : 6; /* [5:0] */ + u32 rsv_77 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_ib_bar_disp_sel_u; + +/* Define the union csr_cfg_sdi_pf_func_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_pf0_func_sel : 3; /* [2:0] */ + u32 cfg_sdi_pf1_func_sel : 3; /* [5:3] */ + u32 cfg_sdi_pf2_func_sel : 3; /* [8:6] */ + u32 cfg_sdi_pf3_func_sel : 3; /* [11:9] */ + u32 rsv_78 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_pf_func_sel_u; + +/* Define the union csr_cfg_ib_eco_reg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_at_trans_bypass : 1; /* [0] */ + u32 cfg_cas_eco_disable : 1; /* [1] */ + u32 cfg_eco_reg_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_ib_eco_reg_0_u; + +/* Define the union csr_cfg_ib_eco_reg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_eco_reg_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_ib_eco_reg_1_u; + +/* Define the union csr_cfg_sdi_th_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_th_enable : 3; /* [2:0] */ + u32 rsv_79 : 1; /* [3] */ + u32 cfg_sdi_th_mode : 1; /* [4] */ + u32 rsv_80 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_th_ctrl_u; + +/* Define the union csr_cfg_sdi_th_addr_filter_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_th_addr_mask : 16; /* [15:0] */ + u32 cfg_sdi_th_addr_comp : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_th_addr_filter_u; + +/* Define the union csr_cfg_sdi_th_pf_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_th_pf_en : 4; /* [3:0] */ + u32 rsv_81 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_th_pf_en_u; + +/* Define the union csr_cfg_sdi_th_pf_remap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_th_pf0_remap : 8; /* [7:0] */ + u32 cfg_sdi_th_pf1_remap : 8; /* [15:8] */ + u32 cfg_sdi_th_pf2_remap : 8; /* [23:16] */ + u32 cfg_sdi_th_pf3_remap : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_th_pf_remap_u; + +/* Define the union csr_cfg_sdi_th_pf_vf_start_fun_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_th_pf0_vf_start_fun : 8; /* [7:0] */ + u32 cfg_sdi_th_pf1_vf_start_fun : 8; /* [15:8] */ + u32 cfg_sdi_th_pf2_vf_start_fun : 8; /* [23:16] */ + u32 cfg_sdi_th_pf3_vf_start_fun : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_th_pf_vf_start_fun_u; + +/* Define the union csr_cfg_sdi_th_pf_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_sdi_th_pf0_vf_num : 8; /* [7:0] */ + u32 cfg_sdi_th_pf1_vf_num : 8; /* [15:8] */ + u32 cfg_sdi_th_pf2_vf_num : 8; /* [23:16] */ + u32 cfg_sdi_th_pf3_vf_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_sdi_th_pf_vf_num_u; + +/* Define the union csr_cfg_memattr_win_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_en : 1; /* [0] */ + u32 rsv_82 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_memattr_win_en_u; + +/* Define the union csr_cfg_memattr_win_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_attr_rd : 5; /* [4:0] */ + u32 rsv_83 : 3; /* [7:5] */ + u32 cfg_memattr_win_attr_wr : 5; /* [12:8] */ + u32 rsv_84 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_memattr_win_attr_u; + +/* Define the union csr_cfg_memattr_win_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_memattr_win_addr_u; + +/* Define the union csr_cfg_memattr_win_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_memattr_win_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_memattr_win_mask_u; + +/* Define the union csr_iob_rx_np_delay_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_iob_rx_np_delay : 16; /* [15:0] */ + u32 cfg_iob_rx_np_delay_en : 1; /* [16] */ + u32 rsv_85 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_np_delay_ctrl_u; + +/* Define the union csr_iob_rx_p_delay_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_iob_rx_p_delay : 16; /* [15:0] */ + u32 cfg_iob_rx_p_delay_en : 1; /* [16] */ + u32 rsv_86 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_p_delay_ctrl_u; + +/* Define the union csr_iob_rx_cpl_delay_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_iob_rx_cpl_delay : 16; /* [15:0] */ + u32 cfg_iob_rx_cpl_delay_en : 1; /* [16] */ + u32 rsv_87 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iob_rx_cpl_delay_ctrl_u; + +/* Define the union csr_ib_p2p_space_base_addr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_88 : 4; /* [3:0] */ + u32 cfg_p2p_dest_base_addr_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_base_addr_0_u; + +/* Define the union csr_ib_p2p_space_size_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_dest_offset_0 : 5; /* [4:0] */ + u32 rsv_89 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_size_0_u; + +/* Define the union csr_ib_p2p_space_base_addr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_90 : 4; /* [3:0] */ + u32 cfg_p2p_dest_base_addr_1 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_base_addr_1_u; + +/* Define the union csr_ib_p2p_space_size_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_dest_offset_1 : 5; /* [4:0] */ + u32 rsv_91 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_size_1_u; + +/* Define the union csr_ib_p2p_space_base_addr_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_92 : 4; /* [3:0] */ + u32 cfg_p2p_dest_base_addr_2 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_base_addr_2_u; + +/* Define the union csr_ib_p2p_space_size_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_dest_offset_2 : 5; /* [4:0] */ + u32 rsv_93 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_size_2_u; + +/* Define the union csr_ib_p2p_space_base_addr_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_94 : 4; /* [3:0] */ + u32 cfg_p2p_dest_base_addr_3 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_base_addr_3_u; + +/* Define the union csr_ib_p2p_space_size_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_dest_offset_3 : 5; /* [4:0] */ + u32 rsv_95 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_space_size_3_u; + +/* Define the union csr_ib_p2p_br_dst_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_br_dst_start : 8; /* [7:0] */ + u32 cfg_p2p_br_dst_end : 8; /* [15:8] */ + u32 rsv_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_br_dst_u; + +/* Define the union csr_ib_p2p_dest_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_dst_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_dest_addr_u; + +/* Define the union csr_ib_p2p_route_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_route_dst_enable : 1; /* [0] */ + u32 cfg_p2p_br_enable : 1; /* [1] */ + u32 cfg_p2p_space_0_enable : 1; /* [2] */ + u32 cfg_p2p_space_1_enable : 1; /* [3] */ + u32 cfg_p2p_space_2_enable : 1; /* [4] */ + u32 cfg_p2p_space_3_enable : 1; /* [5] */ + u32 rsv_97 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_route_control_u; + +/* Define the union csr_ib_p2p_attr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_mem_attr_replace_en : 1; /* [0] */ + u32 rsv_98 : 3; /* [3:1] */ + u32 cfg_p2p_mem_attr : 4; /* [7:4] */ + u32 cfg_p2p_snp_attr : 1; /* [8] */ + u32 rsv_99 : 3; /* [11:9] */ + u32 cfg_p2p_mem_attr_pr : 4; /* [15:12] */ + u32 cfg_p2p_snp_attr_pr : 1; /* [16] */ + u32 rsv_100 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_attr_ctrl_u; + +/* Define the union csr_ib_p2p_credit_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_credit_num : 6; /* [5:0] */ + u32 cfg_p2p_credit_ctrl_enable : 1; /* [6] */ + u32 cfg_p2p_credit_adjust_enable : 1; /* [7] */ + u32 cfg_p2p_block_threshold_l : 5; /* [12:8] */ + u32 rsv_101 : 3; /* [15:13] */ + u32 cfg_p2p_block_threshold_h : 5; /* [20:16] */ + u32 rsv_102 : 3; /* [23:21] */ + u32 cfg_p2p_block_threshold_cpl : 5; /* [28:24] */ + u32 rsv_103 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_p2p_credit_ctrl_u; + +/* Define the union csr_haq_global_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_enable : 1; /* [0] */ + u32 rsv_104 : 3; /* [3:1] */ + u32 cfg_haq_msg_len_ch0 : 2; /* [5:4] */ + u32 cfg_haq_msg_len_ch1 : 2; /* [7:6] */ + u32 cfg_haq_msg_mem_attr : 5; /* [12:8] */ + u32 rsv_105 : 3; /* [15:13] */ + u32 cfg_haq_msg_len_ch2 : 2; /* [17:16] */ + u32 cfg_haq_msg_len_ch3 : 2; /* [19:18] */ + u32 rsv_106 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_global_ctrl_u; + +/* Define the union csr_haq_msg_ch_01_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_0_id : 8; /* [7:0] */ + u32 cfg_haq_msg_ch_0_ost : 8; /* [15:8] */ + u32 cfg_haq_msg_ch_1_id : 8; /* [23:16] */ + u32 cfg_haq_msg_ch_1_ost : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_01_attr_u; + +/* Define the union csr_haq_msg_ch_23_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_2_id : 8; /* [7:0] */ + u32 cfg_haq_msg_ch_2_ost : 8; /* [15:8] */ + u32 cfg_haq_msg_ch_3_id : 8; /* [23:16] */ + u32 cfg_haq_msg_ch_3_ost : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_23_attr_u; + +/* Define the union csr_haq_msg_ch_0_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_0_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_0_addr_l_u; + +/* Define the union csr_haq_msg_ch_0_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_0_addr_h : 16; /* [15:0] */ + u32 rsv_107 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_0_addr_h_u; + +/* Define the union csr_haq_msg_ch_1_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_1_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_1_addr_l_u; + +/* Define the union csr_haq_msg_ch_1_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_1_addr_h : 16; /* [15:0] */ + u32 rsv_108 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_1_addr_h_u; + +/* Define the union csr_haq_msg_ch_2_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_2_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_2_addr_l_u; + +/* Define the union csr_haq_msg_ch_2_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_2_addr_h : 16; /* [15:0] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_2_addr_h_u; + +/* Define the union csr_haq_msg_ch_3_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_3_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_3_addr_l_u; + +/* Define the union csr_haq_msg_ch_3_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_msg_ch_3_addr_h : 16; /* [15:0] */ + u32 rsv_110 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_msg_ch_3_addr_h_u; + +/* Define the union csr_haq_cfg_win_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_cfg_win_sel : 5; /* [4:0] */ + u32 rsv_111 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_cfg_win_sel_u; + +/* Define the union csr_haq_win_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_win_enable : 1; /* [0] */ + u32 rsv_112 : 3; /* [3:1] */ + u32 cfg_haq_split_len : 2; /* [5:4] */ + u32 cfg_haq_msg_ch : 2; /* [7:6] */ + u32 rsv_113 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_win_ctrl_0_u; + +/* Define the union csr_haq_win_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_win_size : 5; /* [4:0] */ + u32 rsv_114 : 3; /* [7:5] */ + u32 cfg_haq_sub_win_size : 5; /* [12:8] */ + u32 rsv_115 : 3; /* [15:13] */ + u32 cfg_haq_sub_win_num : 10; /* [25:16] */ + u32 rsv_116 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_win_ctrl_1_u; + +/* Define the union csr_haq_win_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_poe_qid_base : 10; /* [9:0] */ + u32 rsv_117 : 2; /* [11:10] */ + u32 cfg_haq_msg_seg_id : 2; /* [13:12] */ + u32 rsv_118 : 2; /* [15:14] */ + u32 cfg_haq_msg_type : 4; /* [19:16] */ + u32 rsv_119 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_win_ctrl_2_u; + +/* Define the union csr_haq_win_base_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_120 : 10; /* [9:0] */ + u32 cfg_haq_win_base_l : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_win_base_l_u; + +/* Define the union csr_haq_win_base_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_haq_win_base_h : 16; /* [15:0] */ + u32 rsv_121 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_haq_win_base_h_u; + +/* Define the union csr_ib_tph_stash_tbl_rd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stash_tbl_rd : 1; /* [0] */ + u32 rsv_122 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_stash_tbl_rd_u; + +/* Define the union csr_ib_tph_stash_tbl_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stash_tbl_wr : 1; /* [0] */ + u32 rsv_123 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_stash_tbl_wr_u; + +/* Define the union csr_ib_tph_stash_tbl_stidx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stash_tbl_stidx : 10; /* [9:0] */ + u32 rsv_124 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_stash_tbl_stidx_u; + +/* Define the union csr_ib_tph_stash_tbl_wdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stash_tbl_wdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_stash_tbl_wdata_u; + +/* Define the union csr_ib_tph_stash_tbl_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stash_tbl_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_stash_tbl_rdata_u; + +/* Define the union csr_ib_tph_bypass_port_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_tph_bypass : 20; /* [19:0] */ + u32 rsv_125 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_bypass_port_en_u; + +/* Define the union csr_ib_tph_replace_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_tph_replace_info_0 : 12; /* [11:0] */ + u32 cfg_tph_replace_info_1 : 12; /* [23:12] */ + u32 rsv_126 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_tph_replace_ctrl_u; + +/* Define the union csr_ib_axim_arb_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ib_axim_arb_weight_axim_c1 : 4; /* [3:0] */ + u32 cfg_ib_axim_arb_weight_axim_c2 : 4; /* [7:4] */ + u32 cfg_b_axim_arb_weight_axim_sdi : 4; /* [11:8] */ + u32 rsv_127 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_weight_u; + +/* Define the union csr_ib_axim_arb_rate_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_rd_ost_ctrl_enable : 1; /* [0] */ + u32 cfg_latency_tune_enable : 1; /* [1] */ + u32 rsv_128 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_rate_ctrl_u; + +/* Define the union csr_ib_axim_arb_rd_ost_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_notback_threshold : 8; /* [7:0] */ + u32 rsv_129 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_rd_ost_num_u; + +/* Define the union csr_ib_axim_arb_target_lat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_target_latency_rd : 10; /* [9:0] */ + u32 rsv_130 : 6; /* [15:10] */ + u32 cfg_target_latency_wr : 10; /* [25:16] */ + u32 rsv_131 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_target_lat_u; + +/* Define the union csr_ib_axim_arb_lat_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_lat_sel : 2; /* [1:0] */ + u32 rsv_132 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_lat_sel_u; + +/* Define the union csr_ib_axim_arb_p2p_rdy_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_p2p_rdy_ctrl : 1; /* [0] */ + u32 rsv_133 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_p2p_rdy_ctrl_u; + +/* Define the union csr_ib_axim_arb_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_arb_state : 22; /* [21:0] */ + u32 rsv_134 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_state_u; + +/* Define the union csr_ib_axim_arb_m0_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m0_arlen_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m0_r_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m0_cnt_0_u; + +/* Define the union csr_ib_axim_arb_m0_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m0_aw_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m0_b_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m0_cnt_1_u; + +/* Define the union csr_ib_axim_arb_m1_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m1_arlen_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m1_r_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m1_cnt_0_u; + +/* Define the union csr_ib_axim_arb_m1_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m1_aw_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m1_b_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m1_cnt_1_u; + +/* Define the union csr_ib_axim_arb_m0_ar_lat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m0_arlat_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m0_arlat_curr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m0_ar_lat_0_u; + +/* Define the union csr_ib_axim_arb_m0_ar_lat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m0_arlat_avg : 16; /* [15:0] */ + u32 dfx_ib_axim_m0_arlat_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m0_ar_lat_1_u; + +/* Define the union csr_ib_axim_arb_m0_aw_lat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m0_awlat_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m0_awlat_curr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m0_aw_lat_0_u; + +/* Define the union csr_ib_axim_arb_m0_aw_lat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m0_awlat_avg : 16; /* [15:0] */ + u32 dfx_ib_axim_m0_awlat_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m0_aw_lat_1_u; + +/* Define the union csr_ib_axim_arb_m1_ar_lat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m1_arlat_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m1_arlat_curr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m1_ar_lat_0_u; + +/* Define the union csr_ib_axim_arb_m1_ar_lat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m1_arlat_avg : 16; /* [15:0] */ + u32 dfx_ib_axim_m1_arlat_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m1_ar_lat_1_u; + +/* Define the union csr_ib_axim_arb_m1_aw_lat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m1_awlat_cnt : 16; /* [15:0] */ + u32 dfx_ib_axim_m1_awlat_curr : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m1_aw_lat_0_u; + +/* Define the union csr_ib_axim_arb_m1_aw_lat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ib_axim_m1_awlat_avg : 16; /* [15:0] */ + u32 dfx_ib_axim_m1_awlat_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_m1_aw_lat_1_u; + +/* Define the union csr_ib_axim_arb_haq_curr_seq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_seq_num_0 : 8; /* [7:0] */ + u32 dfx_haq_seq_num_1 : 8; /* [15:8] */ + u32 dfx_haq_seq_num_2 : 8; /* [23:16] */ + u32 dfx_haq_seq_num_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_curr_seq_num_u; + +/* Define the union csr_ib_axim_arb_haq_trans_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_msg_cnt_0 : 16; /* [15:0] */ + u32 dfx_haq_msg_cnt_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_trans_cnt_0_u; + +/* Define the union csr_ib_axim_arb_haq_seq_num_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_seq_num_sts_0 : 24; /* [23:0] */ + u32 rsv_135 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_seq_num_sts_0_u; + +/* Define the union csr_ib_axim_arb_haq_seq_num_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_seq_num_sts_1 : 24; /* [23:0] */ + u32 rsv_136 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_seq_num_sts_1_u; + +/* Define the union csr_ib_axim_arb_haq_trans_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_msg_cnt_2 : 16; /* [15:0] */ + u32 dfx_haq_msg_cnt_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_trans_cnt_1_u; + +/* Define the union csr_ib_axim_arb_haq_seq_num_sts_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_seq_num_sts_2 : 24; /* [23:0] */ + u32 rsv_137 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_seq_num_sts_2_u; + +/* Define the union csr_ib_axim_arb_haq_seq_num_sts_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_haq_seq_num_sts_3 : 24; /* [23:0] */ + u32 rsv_138 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_haq_seq_num_sts_3_u; + +/* Define the union csr_ib_axim_arb_p2p_seq_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_p2p_seq_sts0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_p2p_seq_sts0_u; + +/* Define the union csr_ib_axim_arb_p2p_seq_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_p2p_seq_sts1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_p2p_seq_sts1_u; + +/* Define the union csr_ib_axim_arb_p2p_seq_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_p2p_seq_sts2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_p2p_seq_sts2_u; + +/* Define the union csr_ib_axim_arb_p2p_seq_sts3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_p2p_seq_sts3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_p2p_seq_sts3_u; + +/* Define the union csr_ib_axim_arb_p2p_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_p2p_seq_ptr : 5; /* [4:0] */ + u32 rsv_139 : 3; /* [7:5] */ + u32 dfx_p2p_rls_ptr : 5; /* [12:8] */ + u32 rsv_140 : 3; /* [15:13] */ + u32 dfx_p2p_crd_num : 6; /* [21:16] */ + u32 rsv_141 : 2; /* [23:22] */ + u32 dfx_crd_adj_dec : 5; /* [28:24] */ + u32 dfx_p2p_crd_full_err : 1; /* [29] */ + u32 dfx_p2p_seq_req_err : 1; /* [30] */ + u32 rsv_142 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_axim_arb_p2p_sts_u; + +/* Define the union csr_ib_cfg_stash_table_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stash_lpid : 8; /* [7:0] */ + u32 stash_valid : 1; /* [8] */ + u32 stash_lpid_valid : 1; /* [9] */ + u32 stash_nid_valid : 1; /* [10] */ + u32 rsv_143 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_stash_table_u; + +/* Define the union csr_ib_cfg_tph_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_stat_tlp_unit : 8; /* [7:0] */ + u32 cfg_stat_tlp_time : 3; /* [10:8] */ + u32 cfg_stat_tlp_clr : 1; /* [11] */ + u32 cfg_stash_enable : 1; /* [12] */ + u32 cfg_tph_mode : 2; /* [14:13] */ + u32 cfg_latency_axim_sel : 2; /* [16:15] */ + u32 cfg_stash_adjust_step : 2; /* [18:17] */ + u32 cfg_stash_exceed_stat_omit : 1; /* [19] */ + u32 cfg_ref_latency_lev : 5; /* [24:20] */ + u32 rsv_144 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_tph_u; + +/* Define the union csr_ib_cfg_tph_bandwidth_exceed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_tph_bw_exceed : 30; /* [29:0] */ + u32 rsv_145 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_tph_bandwidth_exceed_u; + +/* Define the union csr_ib_cfg_ph_map_to_target_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ph_wr_target : 4; /* [3:0] */ + u32 cfg_ph_rd_target : 4; /* [7:4] */ + u32 rsv_146 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_ph_map_to_target_u; + +/* Define the union csr_ib_cfg_stash_data_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_data_type_stash_enable : 3; /* [2:0] */ + u32 rsv_147 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_stash_data_type_u; + +/* Define the union csr_ib_cfg_data_type_descriptor_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_data_type_descriptor_lower : 8; /* [7:0] */ + u32 cfg_data_type_descriptor_upper : 8; /* [15:8] */ + u32 rsv_148 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_data_type_descriptor_u; + +/* Define the union csr_ib_cfg_data_type_packet_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_data_type_head_lower : 8; /* [7:0] */ + u32 cfg_data_type_head_upper : 8; /* [15:8] */ + u32 cfg_data_type_data_lower : 8; /* [23:16] */ + u32 cfg_data_type_data_upper : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_cfg_data_type_packet_u; + +/* Define the union csr_ib_wr_adjust_bw_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ib_wr_adjust_bw_limit : 22; /* [21:0] */ + u32 rsv_149 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_wr_adjust_bw_limit_u; + +/* Define the union csr_ib_stat_tlp_bw_average_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ib_stat_tlp_bw_average : 22; /* [21:0] */ + u32 rsv_150 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_stat_tlp_bw_average_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_iob_rxatu_control_0_u iob_rxatu_control_0[34]; /* 0 */ + volatile csr_iob_rxatu_control_1_u iob_rxatu_control_1[34]; /* 4 */ + volatile csr_iob_rxatu_control_2_u iob_rxatu_control_2[34]; /* 8 */ + volatile csr_iob_rxatu_region_size_u iob_rxatu_region_size[34]; /* C */ + volatile csr_iob_rxatu_base_addr_l_u iob_rxatu_base_addr_l[34]; /* 10 */ + volatile csr_iob_rxatu_base_addr_h_u iob_rxatu_base_addr_h[34]; /* 14 */ + volatile csr_iob_rxatu_tar_addr_l_u iob_rxatu_tar_addr_l[34]; /* 18 */ + volatile csr_iob_rxatu_tar_addr_h_u iob_rxatu_tar_addr_h[34]; /* 1C */ + volatile csr_iob_rx_cnt_clr_ce_u iob_rx_cnt_clr_ce; /* A00 */ + volatile csr_iob_rx_tlp_cnt_np_u iob_rx_tlp_cnt_np[3]; /* A40 */ + volatile csr_iob_rx_tlp_cnt_p_u iob_rx_tlp_cnt_p[3]; /* A44 */ + volatile csr_iob_rx_tlp_cnt_cpl_u iob_rx_tlp_cnt_cpl[3]; /* A48 */ + volatile csr_iob_rx_tlp_cnt_msix_u iob_rx_tlp_cnt_msix[3]; /* A4C */ + volatile csr_iob_rx_tlp_cnt_np_p2p_u iob_rx_tlp_cnt_np_p2p[3]; /* A50 */ + volatile csr_iob_rx_tlp_cnt_p_p2p_u iob_rx_tlp_cnt_p_p2p[3]; /* A54 */ + volatile csr_iob_rx_tlp_cnt_cpl_p2p_u iob_rx_tlp_cnt_cpl_p2p[3]; /* A58 */ + volatile csr_iob_rx_tlp_cnt_np_odr_u iob_rx_tlp_cnt_np_odr[3]; /* A60 */ + volatile csr_iob_rx_tlp_cnt_p_odr_u iob_rx_tlp_cnt_p_odr[3]; /* A64 */ + volatile csr_iob_rx_tlp_cnt_haq_u iob_rx_tlp_cnt_haq[3]; /* A68 */ + volatile csr_iob_rx_tlp_cnt_np_aer_u iob_rx_tlp_cnt_np_aer[3]; /* A70 */ + volatile csr_iob_rx_tlp_cnt_p_aer_u iob_rx_tlp_cnt_p_aer[3]; /* A74 */ + volatile csr_iob_rx_pre_err_sts_u iob_rx_pre_err_sts[3]; /* B80 */ + volatile csr_iob_rx_np_pkt_num_u iob_rx_np_pkt_num[3]; /* B90 */ + volatile csr_iob_rx_p_pkt_num_u iob_rx_p_pkt_num[3]; /* B94 */ + volatile csr_iob_rx_cpl_pkt_num_u iob_rx_cpl_pkt_num[3]; /* B98 */ + volatile csr_apat_dfx_ats_inv_lkdn_clr_u apat_dfx_ats_inv_lkdn_clr; /* 10B0 */ + volatile csr_apat_dfx_sync_wait_rls_u apat_dfx_sync_wait_rls; /* 10B4 */ + volatile csr_apat_idle_set_cfg_u apat_idle_set_cfg; /* 10BC */ + volatile csr_apat_req_entry_rd_idx_u apat_req_entry_rd_idx; /* 10C0 */ + volatile csr_apat_req_entry_rd_done_u apat_req_entry_rd_done; /* 10C4 */ + volatile csr_apat_req_entry_rdata0_u apat_req_entry_rdata0; /* 10C8 */ + volatile csr_apat_req_entry_rdata1_u apat_req_entry_rdata1; /* 10CC */ + volatile csr_apat_req_entry_rdata2_u apat_req_entry_rdata2; /* 10D0 */ + volatile csr_apat_req_entry_rdata3_u apat_req_entry_rdata3; /* 10D4 */ + volatile csr_apat_ats_translation_idle_u apat_ats_translation_idle; /* 10D8 */ + volatile csr_apat_ats_pri_idle_u apat_ats_pri_idle; /* 10DC */ + volatile csr_apat_int_ro_ce_u apat_int_ro_ce; /* 10E0 */ + volatile csr_apat_int_ro_nfe_u apat_int_ro_nfe; /* 10E4 */ + volatile csr_apat_int_ro_fe_u apat_int_ro_fe; /* 10E8 */ + volatile csr_apat_int_severity_u apat_int_severity; /* 10EC */ + volatile csr_apat_int_set_u apat_int_set; /* 10F0 */ + volatile csr_apat_int_mask_u apat_int_mask; /* 10F4 */ + volatile csr_apat_int_status_u apat_int_status; /* 10F8 */ + volatile csr_apat_int_ro_u apat_int_ro; /* 10FC */ + volatile csr_apat_translation_cfg_u apat_translation_cfg; /* 1100 */ + volatile csr_apat_translation_retry_u apat_translation_retry; /* 1104 */ + volatile csr_apat_sync_timeout_u apat_sync_timeout; /* 1108 */ + volatile csr_apat_lkup_stats_cfg_u apat_lkup_stats_cfg; /* 1110 */ + volatile csr_apat_lkup_req_pct_u apat_lkup_req_pct; /* 1114 */ + volatile csr_apat_lkup_req_length_u apat_lkup_req_length; /* 1118 */ + volatile csr_apat_np_lkup_req_length_u apat_np_lkup_req_length; /* 111C */ + volatile csr_apat_np_lkup_latency_u apat_np_lkup_latency; /* 1120 */ + volatile csr_apat_p_lkup_latency_u apat_p_lkup_latency; /* 1124 */ + volatile csr_apat_tlb_predictor_hint_cfg_u apat_tlb_predictor_hint_cfg; /* 1140 */ + volatile csr_apat_tlb_predictor_fifo_dfx_u apat_tlb_predictor_fifo_dfx; /* 1144 */ + volatile csr_apat_tlb_predictor_page_size_cache_performance_0_u + apat_tlb_predictor_page_size_cache_performance_0; /* 1148 */ + volatile csr_apat_tlb_predictor_page_size_cache_performance_1_u + apat_tlb_predictor_page_size_cache_performance_1; /* 114C */ + volatile csr_apat_tlb_predictor_lock_cache_performance_0_u apat_tlb_predictor_lock_cache_performance_0; /* 1150 */ + volatile csr_apat_tlb_predictor_lock_cache_performance_1_u apat_tlb_predictor_lock_cache_performance_1; /* 1154 */ + volatile csr_apat_tlb_predictor_ram_parity_dfx_u apat_tlb_predictor_ram_parity_dfx; /* 1158 */ + volatile csr_apat_cnxt_ram_ecc_cfg_u apat_cnxt_ram_ecc_cfg; /* 115C */ + volatile csr_apat_cnxt_ram_ecc_sts_u apat_cnxt_ram_ecc_sts; /* 1160 */ + volatile csr_apat_dfx_fst_rsp_fault_0_u apat_dfx_fst_rsp_fault_0; /* 1164 */ + volatile csr_apat_dfx_fst_rsp_fault_1_u apat_dfx_fst_rsp_fault_1; /* 1168 */ + volatile csr_apat_dfx_fst_rsp_fault_2_u apat_dfx_fst_rsp_fault_2; /* 116C */ + volatile csr_apat_dfx_fst_rsp_fault_3_u apat_dfx_fst_rsp_fault_3; /* 1170 */ + volatile csr_apat_dfx_cnt_invalid_u apat_dfx_cnt_invalid; /* 1174 */ + volatile csr_apat_dfx_cmd_sync_sts_u apat_dfx_cmd_sync_sts; /* 1178 */ + volatile csr_apat_dfx_sync_max_time_u apat_dfx_sync_max_time; /* 117C */ + volatile csr_apat_ats_cfg_u apat_ats_cfg; /* 1180 */ + volatile csr_apat_ats_timeout_l_u apat_ats_timeout_l; /* 1184 */ + volatile csr_apat_ats_timeout_h_u apat_ats_timeout_h; /* 1188 */ + volatile csr_apat_ats_priq_irpt_u apat_ats_priq_irpt; /* 118C */ + volatile csr_apat_xilinx_hook_pasid_cfg_0_u apat_xilinx_hook_pasid_cfg_0; /* 1190 */ + volatile csr_apat_xilinx_hook_pasid_cfg_1_u apat_xilinx_hook_pasid_cfg_1; /* 1194 */ + volatile csr_apat_xilinx_hook_pasid_cfg_2_u apat_xilinx_hook_pasid_cfg_2; /* 1198 */ + volatile csr_apat_xilinx_hook_pasid_cfg_3_u apat_xilinx_hook_pasid_cfg_3; /* 119C */ + volatile csr_apat_xilinx_hook_pasid_cfg_4_u apat_xilinx_hook_pasid_cfg_4; /* 11A0 */ + volatile csr_apat_xilinx_hook_pasid_cfg_5_u apat_xilinx_hook_pasid_cfg_5; /* 11A4 */ + volatile csr_apat_xilinx_hook_pasid_cfg_6_u apat_xilinx_hook_pasid_cfg_6; /* 11A8 */ + volatile csr_apat_xilinx_hook_pasid_cfg_7_u apat_xilinx_hook_pasid_cfg_7; /* 11AC */ + volatile csr_apat_reqid_pasid_pri_exc_cfg_u apat_reqid_pasid_pri_exc_cfg; /* 11B0 */ + volatile csr_apat_reqid_pasid_pri_exc_rd_u apat_reqid_pasid_pri_exc_rd; /* 11B4 */ + volatile csr_apat_cnt_tlb_lkup_req_u apat_cnt_tlb_lkup_req; /* 11C0 */ + volatile csr_apat_cnt_tlb_retried_request_u apat_cnt_tlb_retried_request; /* 11C4 */ + volatile csr_apat_cnt_tlb_rsp_success_u apat_cnt_tlb_rsp_success; /* 11C8 */ + volatile csr_apat_cnt_tlb_rsp_fault_u apat_cnt_tlb_rsp_fault; /* 11CC */ + volatile csr_apat_cnt_sch_noreissue_request_u apat_cnt_sch_noreissue_request; /* 11D0 */ + volatile csr_apat_cnt_sch_reissue_request_u apat_cnt_sch_reissue_request; /* 11D4 */ + volatile csr_apat_cnt_tlb_lkup_aging_req_u apat_cnt_tlb_lkup_aging_req; /* 11D8 */ + volatile csr_apat_cnt_tlb_aging_req_retried_u apat_cnt_tlb_aging_req_retried; /* 11DC */ + volatile csr_apat_dfx_ats_trs_sts_u apat_dfx_ats_trs_sts; /* 11E0 */ + volatile csr_apat_dfx_ats_inv_sts_u apat_dfx_ats_inv_sts; /* 11E4 */ + volatile csr_apat_dfx_ats_pri_sts_u apat_dfx_ats_pri_sts; /* 11E8 */ + volatile csr_apat_dfx_cnt_ats_trs_u apat_dfx_cnt_ats_trs; /* 11EC */ + volatile csr_apat_dfx_cnt_ats_inv_u apat_dfx_cnt_ats_inv; /* 11F0 */ + volatile csr_apat_dfx_cnt_ats_pri_u apat_dfx_cnt_ats_pri; /* 11F4 */ + volatile csr_apat_dfx_cnt_smmu_inv_u apat_dfx_cnt_smmu_inv; /* 11F8 */ + volatile csr_apat_dfx_cnt_smmu_pri_u apat_dfx_cnt_smmu_pri; /* 11FC */ + volatile csr_apat_ib_trig_glb_ctrl_u apat_ib_trig_glb_ctrl; /* 1200 */ + volatile csr_apat_ib_trig_seq_l_u apat_ib_trig_seq_l[10]; /* 1210 */ + volatile csr_apat_ib_trig_seq_h_u apat_ib_trig_seq_h[10]; /* 1214 */ + volatile csr_apat_ib_trig_seq_pasid_u apat_ib_trig_seq_pasid[10]; /* 1218 */ + volatile csr_apat_ib_trig_seq_ctrl_u apat_ib_trig_seq_ctrl[10]; /* 12B0 */ + volatile csr_apat_ib_trig_rslt_l_u apat_ib_trig_rslt_l[10]; /* 12E0 */ + volatile csr_apat_ib_trig_rslt_h_u apat_ib_trig_rslt_h[10]; /* 12E4 */ + volatile csr_apat_ib_trig_rslt_pasid_u apat_ib_trig_rslt_pasid[10]; /* 12E8 */ + volatile csr_am_msi_msix_ctrl_u am_msi_msix_ctrl[16]; /* 1500 */ + volatile csr_am_msi_msix_addr_high_u am_msi_msix_addr_high[16]; /* 1504 */ + volatile csr_am_msi_msix_addr_low_u am_msi_msix_addr_low[16]; /* 1508 */ + volatile csr_ib_smmu_bypass_port_en_u ib_smmu_bypass_port_en; /* 1800 */ + volatile csr_ib_atop_endian_format_u ib_atop_endian_format; /* 1804 */ + volatile csr_ib_rx_filter_mode_u ib_rx_filter_mode; /* 1808 */ + volatile csr_ib_smmu_bypass_memattr_u ib_smmu_bypass_memattr; /* 180C */ + volatile csr_ib_sdi_reg_remap_u ib_sdi_reg_remap; /* 1810 */ + volatile csr_cfg_ib_poison_pr_forward_en_u cfg_ib_poison_pr_forward_en; /* 1814 */ + volatile csr_cfg_ib_bar_disp_sel_u cfg_ib_bar_disp_sel; /* 1818 */ + volatile csr_cfg_sdi_pf_func_sel_u cfg_sdi_pf_func_sel; /* 181C */ + volatile csr_cfg_ib_eco_reg_0_u cfg_ib_eco_reg_0; /* 1820 */ + volatile csr_cfg_ib_eco_reg_1_u cfg_ib_eco_reg_1; /* 1824 */ + volatile csr_cfg_sdi_th_ctrl_u cfg_sdi_th_ctrl; /* 1830 */ + volatile csr_cfg_sdi_th_addr_filter_u cfg_sdi_th_addr_filter; /* 1834 */ + volatile csr_cfg_sdi_th_pf_en_u cfg_sdi_th_pf_en; /* 1840 */ + volatile csr_cfg_sdi_th_pf_remap_u cfg_sdi_th_pf_remap; /* 1844 */ + volatile csr_cfg_sdi_th_pf_vf_start_fun_u cfg_sdi_th_pf_vf_start_fun; /* 1848 */ + volatile csr_cfg_sdi_th_pf_vf_num_u cfg_sdi_th_pf_vf_num; /* 184C */ + volatile csr_cfg_memattr_win_en_u cfg_memattr_win_en[8]; /* 1880 */ + volatile csr_cfg_memattr_win_attr_u cfg_memattr_win_attr[8]; /* 1884 */ + volatile csr_cfg_memattr_win_addr_u cfg_memattr_win_addr[8]; /* 1888 */ + volatile csr_cfg_memattr_win_mask_u cfg_memattr_win_mask[8]; /* 188C */ + volatile csr_iob_rx_np_delay_ctrl_u iob_rx_np_delay_ctrl[3]; /* 1940 */ + volatile csr_iob_rx_p_delay_ctrl_u iob_rx_p_delay_ctrl[3]; /* 1950 */ + volatile csr_iob_rx_cpl_delay_ctrl_u iob_rx_cpl_delay_ctrl[3]; /* 1960 */ + volatile csr_ib_p2p_space_base_addr_0_u ib_p2p_space_base_addr_0[4]; /* 1A00 */ + volatile csr_ib_p2p_space_size_0_u ib_p2p_space_size_0[4]; /* 1A04 */ + volatile csr_ib_p2p_space_base_addr_1_u ib_p2p_space_base_addr_1[4]; /* 1A08 */ + volatile csr_ib_p2p_space_size_1_u ib_p2p_space_size_1[4]; /* 1A0C */ + volatile csr_ib_p2p_space_base_addr_2_u ib_p2p_space_base_addr_2[4]; /* 1A10 */ + volatile csr_ib_p2p_space_size_2_u ib_p2p_space_size_2[4]; /* 1A14 */ + volatile csr_ib_p2p_space_base_addr_3_u ib_p2p_space_base_addr_3[4]; /* 1A18 */ + volatile csr_ib_p2p_space_size_3_u ib_p2p_space_size_3[4]; /* 1A1C */ + volatile csr_ib_p2p_br_dst_u ib_p2p_br_dst[4]; /* 1A30 */ + volatile csr_ib_p2p_dest_addr_u ib_p2p_dest_addr[4]; /* 1A34 */ + volatile csr_ib_p2p_route_control_u ib_p2p_route_control[4]; /* 1A38 */ + volatile csr_ib_p2p_attr_ctrl_u ib_p2p_attr_ctrl[4]; /* 1A3C */ + volatile csr_ib_p2p_credit_ctrl_u ib_p2p_credit_ctrl[4]; /* 1A40 */ + volatile csr_haq_global_ctrl_u haq_global_ctrl; /* 1E00 */ + volatile csr_haq_msg_ch_01_attr_u haq_msg_ch_01_attr; /* 1E04 */ + volatile csr_haq_msg_ch_23_attr_u haq_msg_ch_23_attr; /* 1E08 */ + volatile csr_haq_msg_ch_0_addr_l_u haq_msg_ch_0_addr_l; /* 1E10 */ + volatile csr_haq_msg_ch_0_addr_h_u haq_msg_ch_0_addr_h; /* 1E14 */ + volatile csr_haq_msg_ch_1_addr_l_u haq_msg_ch_1_addr_l; /* 1E18 */ + volatile csr_haq_msg_ch_1_addr_h_u haq_msg_ch_1_addr_h; /* 1E1C */ + volatile csr_haq_msg_ch_2_addr_l_u haq_msg_ch_2_addr_l; /* 1E20 */ + volatile csr_haq_msg_ch_2_addr_h_u haq_msg_ch_2_addr_h; /* 1E24 */ + volatile csr_haq_msg_ch_3_addr_l_u haq_msg_ch_3_addr_l; /* 1E28 */ + volatile csr_haq_msg_ch_3_addr_h_u haq_msg_ch_3_addr_h; /* 1E2C */ + volatile csr_haq_cfg_win_sel_u haq_cfg_win_sel; /* 1E30 */ + volatile csr_haq_win_ctrl_0_u haq_win_ctrl_0; /* 1E40 */ + volatile csr_haq_win_ctrl_1_u haq_win_ctrl_1; /* 1E44 */ + volatile csr_haq_win_ctrl_2_u haq_win_ctrl_2; /* 1E48 */ + volatile csr_haq_win_base_l_u haq_win_base_l; /* 1E50 */ + volatile csr_haq_win_base_h_u haq_win_base_h; /* 1E54 */ + volatile csr_ib_tph_stash_tbl_rd_u ib_tph_stash_tbl_rd; /* 1F00 */ + volatile csr_ib_tph_stash_tbl_wr_u ib_tph_stash_tbl_wr; /* 1F04 */ + volatile csr_ib_tph_stash_tbl_stidx_u ib_tph_stash_tbl_stidx; /* 1F08 */ + volatile csr_ib_tph_stash_tbl_wdata_u ib_tph_stash_tbl_wdata; /* 1F0C */ + volatile csr_ib_tph_stash_tbl_rdata_u ib_tph_stash_tbl_rdata; /* 1F10 */ + volatile csr_ib_tph_bypass_port_en_u ib_tph_bypass_port_en; /* 1F14 */ + volatile csr_ib_tph_replace_ctrl_u ib_tph_replace_ctrl[10]; /* 1F20 */ + volatile csr_ib_axim_arb_weight_u ib_axim_arb_weight; /* 2300 */ + volatile csr_ib_axim_arb_rate_ctrl_u ib_axim_arb_rate_ctrl; /* 2304 */ + volatile csr_ib_axim_arb_rd_ost_num_u ib_axim_arb_rd_ost_num; /* 2308 */ + volatile csr_ib_axim_arb_target_lat_u ib_axim_arb_target_lat; /* 230C */ + volatile csr_ib_axim_arb_lat_sel_u ib_axim_arb_lat_sel; /* 2310 */ + volatile csr_ib_axim_arb_p2p_rdy_ctrl_u ib_axim_arb_p2p_rdy_ctrl; /* 2314 */ + volatile csr_ib_axim_arb_state_u ib_axim_arb_state; /* 2340 */ + volatile csr_ib_axim_arb_m0_cnt_0_u ib_axim_arb_m0_cnt_0; /* 2360 */ + volatile csr_ib_axim_arb_m0_cnt_1_u ib_axim_arb_m0_cnt_1; /* 2364 */ + volatile csr_ib_axim_arb_m1_cnt_0_u ib_axim_arb_m1_cnt_0; /* 2368 */ + volatile csr_ib_axim_arb_m1_cnt_1_u ib_axim_arb_m1_cnt_1; /* 236C */ + volatile csr_ib_axim_arb_m0_ar_lat_0_u ib_axim_arb_m0_ar_lat_0; /* 2380 */ + volatile csr_ib_axim_arb_m0_ar_lat_1_u ib_axim_arb_m0_ar_lat_1; /* 2384 */ + volatile csr_ib_axim_arb_m0_aw_lat_0_u ib_axim_arb_m0_aw_lat_0; /* 2388 */ + volatile csr_ib_axim_arb_m0_aw_lat_1_u ib_axim_arb_m0_aw_lat_1; /* 238C */ + volatile csr_ib_axim_arb_m1_ar_lat_0_u ib_axim_arb_m1_ar_lat_0; /* 2390 */ + volatile csr_ib_axim_arb_m1_ar_lat_1_u ib_axim_arb_m1_ar_lat_1; /* 2394 */ + volatile csr_ib_axim_arb_m1_aw_lat_0_u ib_axim_arb_m1_aw_lat_0; /* 2398 */ + volatile csr_ib_axim_arb_m1_aw_lat_1_u ib_axim_arb_m1_aw_lat_1; /* 239C */ + volatile csr_ib_axim_arb_haq_curr_seq_num_u ib_axim_arb_haq_curr_seq_num; /* 23A0 */ + volatile csr_ib_axim_arb_haq_trans_cnt_0_u ib_axim_arb_haq_trans_cnt_0; /* 23A4 */ + volatile csr_ib_axim_arb_haq_seq_num_sts_0_u ib_axim_arb_haq_seq_num_sts_0; /* 23A8 */ + volatile csr_ib_axim_arb_haq_seq_num_sts_1_u ib_axim_arb_haq_seq_num_sts_1; /* 23AC */ + volatile csr_ib_axim_arb_haq_trans_cnt_1_u ib_axim_arb_haq_trans_cnt_1; /* 23B0 */ + volatile csr_ib_axim_arb_haq_seq_num_sts_2_u ib_axim_arb_haq_seq_num_sts_2; /* 23B4 */ + volatile csr_ib_axim_arb_haq_seq_num_sts_3_u ib_axim_arb_haq_seq_num_sts_3; /* 23B8 */ + volatile csr_ib_axim_arb_p2p_seq_sts0_u ib_axim_arb_p2p_seq_sts0; /* 23C0 */ + volatile csr_ib_axim_arb_p2p_seq_sts1_u ib_axim_arb_p2p_seq_sts1; /* 23C4 */ + volatile csr_ib_axim_arb_p2p_seq_sts2_u ib_axim_arb_p2p_seq_sts2; /* 23C8 */ + volatile csr_ib_axim_arb_p2p_seq_sts3_u ib_axim_arb_p2p_seq_sts3; /* 23CC */ + volatile csr_ib_axim_arb_p2p_sts_u ib_axim_arb_p2p_sts[4]; /* 23D0 */ + volatile csr_ib_cfg_stash_table_u ib_cfg_stash_table[64]; /* 0 */ + volatile csr_ib_cfg_tph_u ib_cfg_tph; /* 200 */ + volatile csr_ib_cfg_tph_bandwidth_exceed_u ib_cfg_tph_bandwidth_exceed; /* 203 */ + volatile csr_ib_cfg_ph_map_to_target_u ib_cfg_ph_map_to_target; /* 204 */ + volatile csr_ib_cfg_stash_data_type_u ib_cfg_stash_data_type; /* 205 */ + volatile csr_ib_cfg_data_type_descriptor_u ib_cfg_data_type_descriptor; /* 206 */ + volatile csr_ib_cfg_data_type_packet_u ib_cfg_data_type_packet; /* 207 */ + volatile csr_ib_wr_adjust_bw_limit_u ib_wr_adjust_bw_limit; /* 208 */ + volatile csr_ib_stat_tlp_bw_average_u ib_stat_tlp_bw_average; /* 209 */ +} S_hipciec_ap_iob_rx_com_reg_REGS_TYPE; + +/* Declare the struct pointor of the module hipciec_ap_iob_rx_com_reg */ +extern volatile S_hipciec_ap_iob_rx_com_reg_REGS_TYPE *gophipciec_ap_iob_rx_com_regAllReg; + +/* Declare the functions that set the member value */ +int iSetIOB_RXATU_CONTROL_0_iob_rxatu_en(unsigned int uiob_rxatu_en); +int iSetIOB_RXATU_CONTROL_0_iob_rxatu_func_mode(unsigned int uiob_rxatu_func_mode); +int iSetIOB_RXATU_CONTROL_0_iob_rxatu_cache(unsigned int uiob_rxatu_cache); +int iSetIOB_RXATU_CONTROL_0_iob_rxatu_snoop(unsigned int uiob_rxatu_snoop); +int iSetIOB_RXATU_CONTROL_1_iob_rxatu_bar_num(unsigned int uiob_rxatu_bar_num); +int iSetIOB_RXATU_CONTROL_1_iob_rxatu_pf_num(unsigned int uiob_rxatu_pf_num); +int iSetIOB_RXATU_CONTROL_1_iob_rxatu_vf_start_num(unsigned int uiob_rxatu_vf_start_num); +int iSetIOB_RXATU_CONTROL_1_iob_rxatu_vf_end_num(unsigned int uiob_rxatu_vf_end_num); +int iSetIOB_RXATU_CONTROL_2_iob_rxatu_ext_region_size(unsigned int uiob_rxatu_ext_region_size); +int iSetIOB_RXATU_REGION_SIZE_iob_rxatu_region_size(unsigned int uiob_rxatu_region_size); +int iSetIOB_RXATU_BASE_ADDR_L_iob_rxatu_base_addr_l(unsigned int uiob_rxatu_base_addr_l); +int iSetIOB_RXATU_BASE_ADDR_H_iob_rxatu_base_addr_h(unsigned int uiob_rxatu_base_addr_h); +int iSetIOB_RXATU_TAR_ADDR_L_iob_rxatu_tar_addr_l(unsigned int uiob_rxatu_tar_addr_l); +int iSetIOB_RXATU_TAR_ADDR_H_iob_rxatu_tar_addr_h(unsigned int uiob_rxatu_tar_addr_h); +int iSetIOB_RX_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce); +int iSetIOB_RX_CNT_CLR_CE_snap_en(unsigned int usnap_en); +int iSetIOB_RX_TLP_CNT_NP_dfx_rx_cnt_np(unsigned int udfx_rx_cnt_np); +int iSetIOB_RX_TLP_CNT_P_dfx_rx_cnt_p(unsigned int udfx_rx_cnt_p); +int iSetIOB_RX_TLP_CNT_CPL_dfx_rx_cnt_cpl(unsigned int udfx_rx_cnt_cpl); +int iSetIOB_RX_TLP_CNT_MSIX_dfx_rx_cnt_msix(unsigned int udfx_rx_cnt_msix); +int iSetIOB_RX_TLP_CNT_NP_P2P_dfx_rx_cnt_np_p2p(unsigned int udfx_rx_cnt_np_p2p); +int iSetIOB_RX_TLP_CNT_P_P2P_dfx_rx_cnt_p_p2p(unsigned int udfx_rx_cnt_p_p2p); +int iSetIOB_RX_TLP_CNT_CPL_P2P_dfx_rx_cnt_cpl_p2p(unsigned int udfx_rx_cnt_cpl_p2p); +int iSetIOB_RX_TLP_CNT_NP_ODR_dfx_rx_cnt_np_odr(unsigned int udfx_rx_cnt_np_odr); +int iSetIOB_RX_TLP_CNT_P_ODR_dfx_rx_cnt_p_odr(unsigned int udfx_rx_cnt_p_odr); +int iSetIOB_RX_TLP_CNT_HAQ_dfx_rx_cnt_haq(unsigned int udfx_rx_cnt_haq); +int iSetIOB_RX_TLP_CNT_NP_AER_dfx_rx_cnt_np_aer(unsigned int udfx_rx_cnt_np_aer); +int iSetIOB_RX_TLP_CNT_P_AER_dfx_rx_cnt_p_aer(unsigned int udfx_rx_cnt_p_aer); +int iSetIOB_RX_PRE_ERR_STS_dfx_rx_pre_err_sts(unsigned int udfx_rx_pre_err_sts); +int iSetIOB_RX_NP_PKT_NUM_dfx_rx_np_pkt_num(unsigned int udfx_rx_np_pkt_num); +int iSetIOB_RX_P_PKT_NUM_dfx_rx_p_pkt_num(unsigned int udfx_rx_p_pkt_num); +int iSetIOB_RX_CPL_PKT_NUM_dfx_rx_cpl_pkt_num(unsigned int udfx_rx_cpl_pkt_num); +int iSetAPAT_DFX_ATS_INV_LKDN_CLR_dfx_ats_inv_lkdn_clr_sta(unsigned int udfx_ats_inv_lkdn_clr_sta); +int iSetAPAT_DFX_SYNC_WAIT_RLS_dfx_sync_wait_rls_entry_num(unsigned int udfx_sync_wait_rls_entry_num); +int iSetAPAT_DFX_SYNC_WAIT_RLS_dfx_sync_bypass_inv_num(unsigned int udfx_sync_bypass_inv_num); +int iSetAPAT_IDLE_SET_CFG_apat_idle_set_cfg(unsigned int uapat_idle_set_cfg); +int iSetAPAT_REQ_ENTRY_RD_IDX_req_entry_rd_idx(unsigned int ureq_entry_rd_idx); +int iSetAPAT_REQ_ENTRY_RD_DONE_req_entry_rd_done(unsigned int ureq_entry_rd_done); +int iSetAPAT_REQ_ENTRY_RDATA0_req_entry_atc(unsigned int ureq_entry_atc); +int iSetAPAT_REQ_ENTRY_RDATA0_req_entry_nosnoop(unsigned int ureq_entry_nosnoop); +int iSetAPAT_REQ_ENTRY_RDATA0_req_entry_va_31_2(unsigned int ureq_entry_va_31_2); +int iSetAPAT_REQ_ENTRY_RDATA1_req_entry_va_63_32(unsigned int ureq_entry_va_63_32); +int iSetAPAT_REQ_ENTRY_RDATA2_req_entry_sid(unsigned int ureq_entry_sid); +int iSetAPAT_REQ_ENTRY_RDATA2_req_entry_ssid(unsigned int ureq_entry_ssid); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_ssv(unsigned int ureq_entry_ssv); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_pri(unsigned int ureq_entry_pri); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_exe(unsigned int ureq_entry_exe); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_isatomic(unsigned int ureq_entry_isatomic); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_txnid(unsigned int ureq_entry_txnid); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_np(unsigned int ureq_entry_np); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_nw(unsigned int ureq_entry_nw); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_core_num(unsigned int ureq_entry_core_num); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_sync_clr_flag(unsigned int ureq_entry_sync_clr_flag); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_tlbi_flag(unsigned int ureq_entry_tlbi_flag); +int iSetAPAT_REQ_ENTRY_RDATA3_reg_entry_vmid(unsigned int ureg_entry_vmid); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_page_size(unsigned int ureq_entry_page_size); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_issue_no_rslt(unsigned int ureq_entry_issue_no_rslt); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_issue(unsigned int ureq_entry_issue); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_times(unsigned int ureq_entry_times); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_wait_rls(unsigned int ureq_entry_wait_rls); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_retry(unsigned int ureq_entry_retry); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_write(unsigned int ureq_entry_write); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_atc_vld(unsigned int ureq_entry_atc_vld); +int iSetAPAT_REQ_ENTRY_RDATA3_req_entry_iob_vld(unsigned int ureq_entry_iob_vld); +int iSetAPAT_ATS_TRANSLATION_IDLE_ats_rx_np_idle(unsigned int uats_rx_np_idle); +int iSetAPAT_ATS_PRI_IDLE_ats_rx_cp_idle(unsigned int uats_rx_cp_idle); +int iSetAPAT_INT_RO_CE_apat_int_ro_ce(unsigned int uapat_int_ro_ce); +int iSetAPAT_INT_RO_NFE_apat_int_ro_nfe(unsigned int uapat_int_ro_nfe); +int iSetAPAT_INT_RO_FE_apat_int_ro_fe(unsigned int uapat_int_ro_fe); +int iSetAPAT_INT_SEVERITY_apat_ram_ecc_int_severity_cfg(unsigned int uapat_ram_ecc_int_severity_cfg); +int iSetAPAT_INT_SET_apat_ram_ecc_int_set_cfg(unsigned int uapat_ram_ecc_int_set_cfg); +int iSetAPAT_INT_MASK_apat_ram_ecc_int_mask_cfg(unsigned int uapat_ram_ecc_int_mask_cfg); +int iSetAPAT_INT_STATUS_apat_ram_ecc_int_status(unsigned int uapat_ram_ecc_int_status); +int iSetAPAT_INT_RO_apat_ram_ecc_int(unsigned int uapat_ram_ecc_int); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_tlb_predictor_off(unsigned int ucfg_apat_tlb_predictor_off); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_forbid_tlb_lock(unsigned int ucfg_apat_forbid_tlb_lock); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_forbid_tlb_invalidate(unsigned int ucfg_apat_forbid_tlb_invalidate); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_core0_ptw_chnl(unsigned int ucfg_apat_core0_ptw_chnl); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_core1_ptw_chnl(unsigned int ucfg_apat_core1_ptw_chnl); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_core2_ptw_chnl(unsigned int ucfg_apat_core2_ptw_chnl); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_keep_src_hint(unsigned int ucfg_apat_keep_src_hint); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_regen_retry_hint(unsigned int ucfg_apat_regen_retry_hint); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_req_inval_0(unsigned int ucfg_apat_req_inval_0); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_req_inval_1(unsigned int ucfg_apat_req_inval_1); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_req_inval_2(unsigned int ucfg_apat_req_inval_2); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_req_inval_3(unsigned int ucfg_apat_req_inval_3); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_req_retry_inval(unsigned int ucfg_apat_req_retry_inval); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_nopasid_pri(unsigned int ucfg_apat_nopasid_pri); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_nopasid_exe(unsigned int ucfg_apat_nopasid_exe); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_disable_inboud_nosnoop(unsigned int ucfg_apat_disable_inboud_nosnoop); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_disable_pasid(unsigned int ucfg_apat_disable_pasid); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_unaddr_exe_wr_ur(unsigned int ucfg_apat_unaddr_exe_wr_ur); +int iSetAPAT_TRANSLATION_CFG_cfg_sync_clr_all_stale_entry(unsigned int ucfg_sync_clr_all_stale_entry); +int iSetAPAT_TRANSLATION_CFG_cfg_sync_clr_all_no_rsp_entry(unsigned int ucfg_sync_clr_all_no_rsp_entry); +int iSetAPAT_TRANSLATION_CFG_cfg_ats_pasid_mode(unsigned int ucfg_ats_pasid_mode); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_default_memattr(unsigned int ucfg_apat_default_memattr); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_default_snoop(unsigned int ucfg_apat_default_snoop); +int iSetAPAT_TRANSLATION_CFG_cfg_apat_enable_nc_atomic(unsigned int ucfg_apat_enable_nc_atomic); +int iSetAPAT_TRANSLATION_CFG_cfg_conf_inv_all_rsp_entry(unsigned int ucfg_conf_inv_all_rsp_entry); +int iSetAPAT_TRANSLATION_CFG_cfg_tlb_inv_all_rsp_entry(unsigned int ucfg_tlb_inv_all_rsp_entry); +int iSetAPAT_TRANSLATION_RETRY_cfg_apat_max_retry_req_num(unsigned int ucfg_apat_max_retry_req_num); +int iSetAPAT_TRANSLATION_RETRY_cfg_apat_max_ptw_req_num(unsigned int ucfg_apat_max_ptw_req_num); +int iSetAPAT_TRANSLATION_RETRY_cfg_apat_ptw_req_glitch_filter(unsigned int ucfg_apat_ptw_req_glitch_filter); +int iSetAPAT_TRANSLATION_RETRY_cfg_req_entry_rls_mode(unsigned int ucfg_req_entry_rls_mode); +int iSetAPAT_TRANSLATION_RETRY_cfg_inv_record_mode(unsigned int ucfg_inv_record_mode); +int iSetAPAT_TRANSLATION_RETRY_cfg_apat_tlbi_vav_disable(unsigned int ucfg_apat_tlbi_vav_disable); +int iSetAPAT_TRANSLATION_RETRY_cfg_ats_global_rsp_en(unsigned int ucfg_ats_global_rsp_en); +int iSetAPAT_TRANSLATION_RETRY_cfg_lkup_bypass_en(unsigned int ucfg_lkup_bypass_en); +int iSetAPAT_TRANSLATION_RETRY_cfg_pri_ovackflg_mode(unsigned int ucfg_pri_ovackflg_mode); +int iSetAPAT_TRANSLATION_RETRY_cfg_pri_ovflg_up_mode(unsigned int ucfg_pri_ovflg_up_mode); +int iSetAPAT_TRANSLATION_RETRY_cfg_pri_ovflg_init_value(unsigned int ucfg_pri_ovflg_init_value); +int iSetAPAT_SYNC_TIMEOUT_apat_sync_timeout_cfg(unsigned int uapat_sync_timeout_cfg); +int iSetAPAT_LKUP_STATS_CFG_apat_stats_src_busnum(unsigned int uapat_stats_src_busnum); +int iSetAPAT_LKUP_STATS_CFG_cfg_tlb_lkup_rsp_only_ur(unsigned int ucfg_tlb_lkup_rsp_only_ur); +int iSetAPAT_LKUP_STATS_CFG_cfg_req_va_legal_chk(unsigned int ucfg_req_va_legal_chk); +int iSetAPAT_LKUP_STATS_CFG_cfg_smmuen_prefix_chk(unsigned int ucfg_smmuen_prefix_chk); +int iSetAPAT_LKUP_STATS_CFG_cfg_req_at_res_is_ur(unsigned int ucfg_req_at_res_is_ur); +int iSetAPAT_LKUP_STATS_CFG_cfg_event_fault_pop_timeout(unsigned int ucfg_event_fault_pop_timeout); +int iSetAPAT_LKUP_REQ_PCT_apat_tlb_lkup_consective_req_num(unsigned int uapat_tlb_lkup_consective_req_num); +int iSetAPAT_LKUP_REQ_PCT_apat_tlp_lkup_src_retry_in_64k(unsigned int uapat_tlp_lkup_src_retry_in_64k); +int iSetAPAT_LKUP_REQ_LENGTH_apat_tlp_p_stat_req_num(unsigned int uapat_tlp_p_stat_req_num); +int iSetAPAT_LKUP_REQ_LENGTH_apat_tlp_p_stat_total_dwlen(unsigned int uapat_tlp_p_stat_total_dwlen); +int iSetAPAT_NP_LKUP_REQ_LENGTH_apat_tlp_np_stat_req_num(unsigned int uapat_tlp_np_stat_req_num); +int iSetAPAT_NP_LKUP_REQ_LENGTH_apat_tlp_np_stat_total_dwlen(unsigned int uapat_tlp_np_stat_total_dwlen); +int iSetAPAT_NP_LKUP_LATENCY_apat_tlb_np_lkup_max_lat(unsigned int uapat_tlb_np_lkup_max_lat); +int iSetAPAT_NP_LKUP_LATENCY_apat_tlb_np_lkup_ava_lat(unsigned int uapat_tlb_np_lkup_ava_lat); +int iSetAPAT_P_LKUP_LATENCY_apat_tlb_p_lkup_max_lat(unsigned int uapat_tlb_p_lkup_max_lat); +int iSetAPAT_P_LKUP_LATENCY_apat_tlb_p_lkup_ava_lat(unsigned int uapat_tlb_p_lkup_ava_lat); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_pg_va_af_dma_no_less_than_pg_sz_hint_sel( + unsigned int upg_va_af_dma_no_less_than_pg_sz_hint_sel); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_cur_dma_len_more_than_rem_pg_sz_half_hint_sel( + unsigned int ucur_dma_len_more_than_rem_pg_sz_half_hint_sel); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_dma_len_equal_4k_hint_sel(unsigned int udma_len_equal_4k_hint_sel); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_req_last_be_hint_sel(unsigned int ureq_last_be_hint_sel); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_dma_len_not_4dw_times_hint_sel(unsigned int udma_len_not_4dw_times_hint_sel); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_tlp_req_read_hint_cfg(unsigned int utlp_req_read_hint_cfg); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_page_size_aging_time(unsigned int upage_size_aging_time); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_lock_hint_aging_time(unsigned int ulock_hint_aging_time); +int iSetAPAT_TLB_PREDICTOR_HINT_CFG_lock_hint_aging_en(unsigned int ulock_hint_aging_en); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lkup_fifo_full_flag(unsigned int ulkup_fifo_full_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lkup_fifo_empty_flag(unsigned int ulkup_fifo_empty_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lkup_fifo_af_flag(unsigned int ulkup_fifo_af_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lkup_fifo_ae_flag(unsigned int ulkup_fifo_ae_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lkup_fifo_overf_flag(unsigned int ulkup_fifo_overf_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lkup_fifo_fill(unsigned int ulkup_fifo_fill); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lock_aging_fifo_full_flag(unsigned int ulock_aging_fifo_full_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lock_aging_fifo_empty_flag(unsigned int ulock_aging_fifo_empty_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lock_aging_fifo_af_flag(unsigned int ulock_aging_fifo_af_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lock_aging_fifo_ae_flag(unsigned int ulock_aging_fifo_ae_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lock_aging_fifo_overf_flag(unsigned int ulock_aging_fifo_overf_flag); +int iSetAPAT_TLB_PREDICTOR_FIFO_DFX_lock_aging_fifo_fill(unsigned int ulock_aging_fifo_fill); +int iSetAPAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_0_ratio_n4k_page_size_cache_hit( + unsigned int uratio_n4k_page_size_cache_hit); +int iSetAPAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_0_ratio_n4k_page_size_cache_miss( + unsigned int uratio_n4k_page_size_cache_miss); +int iSetAPAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_1_ratio_n4k_page_size_cache_evict( + unsigned int uratio_n4k_page_size_cache_evict); +int iSetAPAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_1_ratio_n4k_page_size_cache_no_rep( + unsigned int uratio_n4k_page_size_cache_no_rep); +int iSetAPAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_0_ratio_lock_aging_cache_hit( + unsigned int uratio_lock_aging_cache_hit); +int iSetAPAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_0_ratio_lock_aging_cache_miss( + unsigned int uratio_lock_aging_cache_miss); +int iSetAPAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_1_ratio_lock_aging_cache_evict( + unsigned int uratio_lock_aging_cache_evict); +int iSetAPAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_1_ratio_lock_aging_cache_no_rep( + unsigned int uratio_lock_aging_cache_no_rep); +int iSetAPAT_TLB_PREDICTOR_RAM_PARITY_DFX_lkup_ram_parity_o(unsigned int ulkup_ram_parity_o); +int iSetAPAT_TLB_PREDICTOR_RAM_PARITY_DFX_n4k_page_size_ram_parity_o(unsigned int un4k_page_size_ram_parity_o); +int iSetAPAT_TLB_PREDICTOR_RAM_PARITY_DFX_lock_aging_ram_parity_o(unsigned int ulock_aging_ram_parity_o); +int iSetAPAT_CNXT_RAM_ECC_CFG_apat_ram_ecc_err_inj_cfg(unsigned int uapat_ram_ecc_err_inj_cfg); +int iSetAPAT_CNXT_RAM_ECC_STS_cnt_entry_cnxt_ram_ecc_1bit(unsigned int ucnt_entry_cnxt_ram_ecc_1bit); +int iSetAPAT_CNXT_RAM_ECC_STS_cnt_entry_cnxt_ram_ecc_2bit(unsigned int ucnt_entry_cnxt_ram_ecc_2bit); +int iSetAPAT_CNXT_RAM_ECC_STS_entry_cnxt_ram_ecc_info(unsigned int uentry_cnxt_ram_ecc_info); +int iSetAPAT_DFX_FST_RSP_FAULT_0_dfx_fst_rsp_fault_substrmid(unsigned int udfx_fst_rsp_fault_substrmid); +int iSetAPAT_DFX_FST_RSP_FAULT_0_dfx_fst_rsp_fault_strmid(unsigned int udfx_fst_rsp_fault_strmid); +int iSetAPAT_DFX_FST_RSP_FAULT_1_dfx_fst_rsp_fault_va_low32(unsigned int udfx_fst_rsp_fault_va_low32); +int iSetAPAT_DFX_FST_RSP_FAULT_2_dfx_fst_rsp_fault_va_high32(unsigned int udfx_fst_rsp_fault_va_high32); +int iSetAPAT_DFX_FST_RSP_FAULT_3_dfx_fst_rsp_fault_atc(unsigned int udfx_fst_rsp_fault_atc); +int iSetAPAT_DFX_FST_RSP_FAULT_3_dfx_fst_rsp_fault_ssv(unsigned int udfx_fst_rsp_fault_ssv); +int iSetAPAT_DFX_FST_RSP_FAULT_3_dfx_fst_rsp_fault_type(unsigned int udfx_fst_rsp_fault_type); +int iSetAPAT_DFX_CNT_INVALID_dfx_cnt_tlb_inv(unsigned int udfx_cnt_tlb_inv); +int iSetAPAT_DFX_CNT_INVALID_dfx_cnt_cfg_inv(unsigned int udfx_cnt_cfg_inv); +int iSetAPAT_DFX_CMD_SYNC_STS_dfx_cnt_cmd_sync(unsigned int udfx_cnt_cmd_sync); +int iSetAPAT_DFX_CMD_SYNC_STS_dfx_sync_timeout_wait_rls_num(unsigned int udfx_sync_timeout_wait_rls_num); +int iSetAPAT_DFX_CMD_SYNC_STS_dfx_sync_timeout_bypass_inv_num(unsigned int udfx_sync_timeout_bypass_inv_num); +int iSetAPAT_DFX_CMD_SYNC_STS_dfx_sync_timeout(unsigned int udfx_sync_timeout); +int iSetAPAT_DFX_SYNC_MAX_TIME_dfx_sync_max_time_interval(unsigned int udfx_sync_max_time_interval); +int iSetAPAT_ATS_CFG_cfg_ats_disable(unsigned int ucfg_ats_disable); +int iSetAPAT_ATS_CFG_ats_np_prefix_sel(unsigned int uats_np_prefix_sel); +int iSetAPAT_ATS_CFG_cfg_pri_req_ots_mode(unsigned int ucfg_pri_req_ots_mode); +int iSetAPAT_ATS_CFG_cfg_ats_pri_stop_mk(unsigned int ucfg_ats_pri_stop_mk); +int iSetAPAT_ATS_CFG_cfg_ats_request_inval(unsigned int ucfg_ats_request_inval); +int iSetAPAT_ATS_CFG_apat_req_cxnt_atc_req_max_num(unsigned int uapat_req_cxnt_atc_req_max_num); +int iSetAPAT_ATS_CFG_ats_reg_control(unsigned int uats_reg_control); +int iSetAPAT_ATS_TIMEOUT_L_ats_reg_timeout_l(unsigned int uats_reg_timeout_l); +int iSetAPAT_ATS_TIMEOUT_H_ats_reg_timeout_h(unsigned int uats_reg_timeout_h); +int iSetAPAT_ATS_TIMEOUT_H_cfg_pri_rsp_prefix_mask(unsigned int ucfg_pri_rsp_prefix_mask); +int iSetAPAT_ATS_TIMEOUT_H_cfg_ats_invcp_linkdown_sta(unsigned int ucfg_ats_invcp_linkdown_sta); +int iSetAPAT_ATS_PRIQ_IRPT_apat_ats_priq_irpt(unsigned int uapat_ats_priq_irpt); +int iSetAPAT_XILINX_HOOK_PASID_CFG_0_substream_id_cfg_0(unsigned int usubstream_id_cfg_0); +int iSetAPAT_XILINX_HOOK_PASID_CFG_0_stream_id_cfg_0(unsigned int ustream_id_cfg_0); +int iSetAPAT_XILINX_HOOK_PASID_CFG_1_substream_id_cfg_1(unsigned int usubstream_id_cfg_1); +int iSetAPAT_XILINX_HOOK_PASID_CFG_1_stream_id_cfg_1(unsigned int ustream_id_cfg_1); +int iSetAPAT_XILINX_HOOK_PASID_CFG_2_substream_id_cfg_2(unsigned int usubstream_id_cfg_2); +int iSetAPAT_XILINX_HOOK_PASID_CFG_2_stream_id_cfg_2(unsigned int ustream_id_cfg_2); +int iSetAPAT_XILINX_HOOK_PASID_CFG_3_substream_id_cfg_3(unsigned int usubstream_id_cfg_3); +int iSetAPAT_XILINX_HOOK_PASID_CFG_3_stream_id_cfg_3(unsigned int ustream_id_cfg_3); +int iSetAPAT_XILINX_HOOK_PASID_CFG_4_execute_bit_cfg_0(unsigned int uexecute_bit_cfg_0); +int iSetAPAT_XILINX_HOOK_PASID_CFG_4_priviledge_bit_cfg_0(unsigned int upriviledge_bit_cfg_0); +int iSetAPAT_XILINX_HOOK_PASID_CFG_5_execute_bit_cfg_1(unsigned int uexecute_bit_cfg_1); +int iSetAPAT_XILINX_HOOK_PASID_CFG_5_priviledge_bit_cfg_1(unsigned int upriviledge_bit_cfg_1); +int iSetAPAT_XILINX_HOOK_PASID_CFG_6_execute_bit_cfg_2(unsigned int uexecute_bit_cfg_2); +int iSetAPAT_XILINX_HOOK_PASID_CFG_6_priviledge_bit_cfg_2(unsigned int upriviledge_bit_cfg_2); +int iSetAPAT_XILINX_HOOK_PASID_CFG_7_execute_bit_cfg_3(unsigned int uexecute_bit_cfg_3); +int iSetAPAT_XILINX_HOOK_PASID_CFG_7_priviledge_bit_cfg_3(unsigned int upriviledge_bit_cfg_3); +int iSetAPAT_REQID_PASID_PRI_EXC_CFG_apat_reqid_pasid_pri_exc_cfg(unsigned int uapat_reqid_pasid_pri_exc_cfg); +int iSetAPAT_REQID_PASID_PRI_EXC_RD_apat_reqid_pasid_pri_exc_rd(unsigned int uapat_reqid_pasid_pri_exc_rd); +int iSetAPAT_CNT_TLB_LKUP_REQ_cnt_tlb_lkup_req(unsigned int ucnt_tlb_lkup_req); +int iSetAPAT_CNT_TLB_RETRIED_REQUEST_cnt_tlb_retried_request(unsigned int ucnt_tlb_retried_request); +int iSetAPAT_CNT_TLB_RSP_SUCCESS_cnt_tlb_rsp_success(unsigned int ucnt_tlb_rsp_success); +int iSetAPAT_CNT_TLB_RSP_FAULT_cnt_tlb_rsp_fault(unsigned int ucnt_tlb_rsp_fault); +int iSetAPAT_CNT_SCH_NOREISSUE_REQUEST_cnt_sch_noreissue_request(unsigned int ucnt_sch_noreissue_request); +int iSetAPAT_CNT_SCH_REISSUE_REQUEST_cnt_sch_reissue_request(unsigned int ucnt_sch_reissue_request); +int iSetAPAT_CNT_TLB_LKUP_AGING_REQ_cnt_tlb_lkup_aging_request(unsigned int ucnt_tlb_lkup_aging_request); +int iSetAPAT_CNT_TLB_AGING_REQ_RETRIED_cnt_tlb_aging_req_retried(unsigned int ucnt_tlb_aging_req_retried); +int iSetAPAT_DFX_ATS_TRS_STS_dfx_ats_trs_sts(unsigned int udfx_ats_trs_sts); +int iSetAPAT_DFX_ATS_INV_STS_dfx_ats_inv_sts(unsigned int udfx_ats_inv_sts); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_rx_cpl(unsigned int ucnt_ots_rx_cpl); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_rx_cpl_uf(unsigned int ucnt_ots_rx_cpl_uf); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_rx_cpl_of(unsigned int ucnt_ots_rx_cpl_of); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_pri_req(unsigned int ucnt_ots_pri_req); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_pri_req_uf(unsigned int ucnt_ots_pri_req_uf); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_pri_req_of(unsigned int ucnt_ots_pri_req_of); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_brsp_wr_up(unsigned int ucnt_ots_brsp_wr_up); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_brsp_wr_up_uf(unsigned int ucnt_ots_brsp_wr_up_uf); +int iSetAPAT_DFX_ATS_PRI_STS_cnt_ots_brsp_wr_up_of(unsigned int ucnt_ots_brsp_wr_up_of); +int iSetAPAT_DFX_ATS_PRI_STS_priq_emptry(unsigned int upriq_emptry); +int iSetAPAT_DFX_ATS_PRI_STS_priq_full(unsigned int upriq_full); +int iSetAPAT_DFX_ATS_PRI_STS_priq_ovflg_disc(unsigned int upriq_ovflg_disc); +int iSetAPAT_DFX_CNT_ATS_TRS_dfx_cnt_ats_trs_req(unsigned int udfx_cnt_ats_trs_req); +int iSetAPAT_DFX_CNT_ATS_TRS_dfx_cnt_ats_trs_cpl(unsigned int udfx_cnt_ats_trs_cpl); +int iSetAPAT_DFX_CNT_ATS_INV_dfx_cnt_ats_inv_req(unsigned int udfx_cnt_ats_inv_req); +int iSetAPAT_DFX_CNT_ATS_INV_dfx_cnt_ats_inv_cpl(unsigned int udfx_cnt_ats_inv_cpl); +int iSetAPAT_DFX_CNT_ATS_PRI_dfx_cnt_ats_pri_req(unsigned int udfx_cnt_ats_pri_req); +int iSetAPAT_DFX_CNT_ATS_PRI_dfx_cnt_ats_pri_cpl(unsigned int udfx_cnt_ats_pri_cpl); +int iSetAPAT_DFX_CNT_SMMU_INV_dfx_cnt_smmu_ats_inv_req(unsigned int udfx_cnt_smmu_ats_inv_req); +int iSetAPAT_DFX_CNT_SMMU_INV_dfx_cnt_smmu_ats_inv_cpl(unsigned int udfx_cnt_smmu_ats_inv_cpl); +int iSetAPAT_DFX_CNT_SMMU_PRI_dfx_cnt_smmu_ats_pri_req(unsigned int udfx_cnt_smmu_ats_pri_req); +int iSetAPAT_DFX_CNT_SMMU_PRI_dfx_cnt_smmu_ats_pri_rsp(unsigned int udfx_cnt_smmu_ats_pri_rsp); +int iSetAPAT_IB_TRIG_GLB_CTRL_apat_trig_global_mode(unsigned int uapat_trig_global_mode); +int iSetAPAT_IB_TRIG_GLB_CTRL_apat_trig_status(unsigned int uapat_trig_status); +int iSetAPAT_IB_TRIG_GLB_CTRL_apat_trig_traffic_sample_intval(unsigned int uapat_trig_traffic_sample_intval); +int iSetAPAT_IB_TRIG_SEQ_L_apat_trig_tlp_type(unsigned int uapat_trig_tlp_type); +int iSetAPAT_IB_TRIG_SEQ_L_apat_trig_tlp_ro(unsigned int uapat_trig_tlp_ro); +int iSetAPAT_IB_TRIG_SEQ_L_apat_trig_tlp_ep(unsigned int uapat_trig_tlp_ep); +int iSetAPAT_IB_TRIG_SEQ_L_apat_trig_tlp_at(unsigned int uapat_trig_tlp_at); +int iSetAPAT_IB_TRIG_SEQ_L_apat_trig_tlp_length(unsigned int uapat_trig_tlp_length); +int iSetAPAT_IB_TRIG_SEQ_L_apat_trig_tlp_reqid(unsigned int uapat_trig_tlp_reqid); +int iSetAPAT_IB_TRIG_SEQ_H_apat_trig_tlp_ido(unsigned int uapat_trig_tlp_ido); +int iSetAPAT_IB_TRIG_SEQ_H_apat_trig_tlp_th(unsigned int uapat_trig_tlp_th); +int iSetAPAT_IB_TRIG_SEQ_H_apat_trig_tlp_ph(unsigned int uapat_trig_tlp_ph); +int iSetAPAT_IB_TRIG_SEQ_H_apat_ib_trig_seq_h_res(unsigned int uapat_ib_trig_seq_h_res); +int iSetAPAT_IB_TRIG_SEQ_H_apat_trig_addr26_2(unsigned int uapat_trig_addr26_2); +int iSetAPAT_IB_TRIG_SEQ_H_apat_trig_addr33_32(unsigned int uapat_trig_addr33_32); +int iSetAPAT_IB_TRIG_SEQ_PASID_apat_trig_tlp_pasid(unsigned int uapat_trig_tlp_pasid); +int iSetAPAT_IB_TRIG_SEQ_PASID_apat_ib_trig_seq_pasid_res_21_16(unsigned int uapat_ib_trig_seq_pasid_res_21_16); +int iSetAPAT_IB_TRIG_SEQ_PASID_apat_trig_tlp_pasid_exe(unsigned int uapat_trig_tlp_pasid_exe); +int iSetAPAT_IB_TRIG_SEQ_PASID_apat_trig_tlp_pasid_pri(unsigned int uapat_trig_tlp_pasid_pri); +int iSetAPAT_IB_TRIG_SEQ_PASID_apat_ib_trig_seq_pasid_res_31_24(unsigned int uapat_ib_trig_seq_pasid_res_31_24); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_type_en(unsigned int uapat_trig_tlp_type_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_ro_en(unsigned int uapat_trig_tlp_ro_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_ep_en(unsigned int uapat_trig_tlp_ep_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_at_en(unsigned int uapat_trig_tlp_at_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_length_en(unsigned int uapat_trig_tlp_length_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_reqid_en(unsigned int uapat_trig_tlp_reqid_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_ido_en(unsigned int uapat_trig_tlp_ido_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_th_en(unsigned int uapat_trig_tlp_th_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_ph_en(unsigned int uapat_trig_tlp_ph_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_pasid_en(unsigned int uapat_trig_tlp_pasid_en); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_tlp_addr_match_style(unsigned int uapat_trig_tlp_addr_match_style); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_ib_trig_seq_ctrl_res_30_13(unsigned int uapat_ib_trig_seq_ctrl_res_30_13); +int iSetAPAT_IB_TRIG_SEQ_CTRL_apat_trig_entry_vld(unsigned int uapat_trig_entry_vld); +int iSetAPAT_IB_TRIG_RSLT_L_apat_trig_rslt_tlp_type(unsigned int uapat_trig_rslt_tlp_type); +int iSetAPAT_IB_TRIG_RSLT_L_apat_trig_rslt_tlp_ro(unsigned int uapat_trig_rslt_tlp_ro); +int iSetAPAT_IB_TRIG_RSLT_L_apat_trig_rslt_tlp_ep(unsigned int uapat_trig_rslt_tlp_ep); +int iSetAPAT_IB_TRIG_RSLT_L_apat_trig_rslt_tlp_at(unsigned int uapat_trig_rslt_tlp_at); +int iSetAPAT_IB_TRIG_RSLT_L_apat_trig_rslt_tlp_length(unsigned int uapat_trig_rslt_tlp_length); +int iSetAPAT_IB_TRIG_RSLT_L_apat_trig_rslt_tlp_reqid(unsigned int uapat_trig_rslt_tlp_reqid); +int iSetAPAT_IB_TRIG_RSLT_H_apat_trig_rslt_tlp_ido(unsigned int uapat_trig_rslt_tlp_ido); +int iSetAPAT_IB_TRIG_RSLT_H_apat_trig_rslt_tlp_th(unsigned int uapat_trig_rslt_tlp_th); +int iSetAPAT_IB_TRIG_RSLT_H_apat_trig_rslt_tlp_ph(unsigned int uapat_trig_rslt_tlp_ph); +int iSetAPAT_IB_TRIG_RSLT_H_apat_trig_rslt_addr26_2(unsigned int uapat_trig_rslt_addr26_2); +int iSetAPAT_IB_TRIG_RSLT_H_apat_trig_rslt_addr33_32(unsigned int uapat_trig_rslt_addr33_32); +int iSetAPAT_IB_TRIG_RSLT_PASID_apat_trig_rslt_tlp_pasid(unsigned int uapat_trig_rslt_tlp_pasid); +int iSetAPAT_IB_TRIG_RSLT_PASID_apat_trig_rslt_tlp_pasid_exe(unsigned int uapat_trig_rslt_tlp_pasid_exe); +int iSetAPAT_IB_TRIG_RSLT_PASID_apat_trig_rslt_tlp_pasid_pri(unsigned int uapat_trig_rslt_tlp_pasid_pri); +int iSetAM_MSI_MSIX_CTRL_msi_msix_enable(unsigned int umsi_msix_enable); +int iSetAM_MSI_MSIX_CTRL_msi_msix_axicache(unsigned int umsi_msix_axicache); +int iSetAM_MSI_MSIX_CTRL_msi_msix_snpattr(unsigned int umsi_msix_snpattr); +int iSetAM_MSI_MSIX_ADDR_HIGH_msi_msix_addr_high(unsigned int umsi_msix_addr_high); +int iSetAM_MSI_MSIX_ADDR_LOW_msi_msix_addr_low(unsigned int umsi_msix_addr_low); +int iSetIB_SMMU_BYPASS_PORT_EN_cfg_port_smmu_bypass(unsigned int ucfg_port_smmu_bypass); +int iSetIB_ATOP_ENDIAN_FORMAT_cfg_atop_endian_format(unsigned int ucfg_atop_endian_format); +int iSetIB_RX_FILTER_MODE_cfg_atu_abort_mode(unsigned int ucfg_atu_abort_mode); +int iSetIB_RX_FILTER_MODE_cfg_msi_msix_prot_abort_mode(unsigned int ucfg_msi_msix_prot_abort_mode); +int iSetIB_RX_FILTER_MODE_cfg_msi_msix_prot_mode(unsigned int ucfg_msi_msix_prot_mode); +int iSetIB_RX_FILTER_MODE_cfg_rom_hit_filter(unsigned int ucfg_rom_hit_filter); +int iSetIB_RX_FILTER_MODE_cfg_prefix_filter(unsigned int ucfg_prefix_filter); +int iSetIB_RX_FILTER_MODE_cfg_vdm_msg_p2p_filter(unsigned int ucfg_vdm_msg_p2p_filter); +int iSetIB_RX_FILTER_MODE_cfg_mctp_msg_p2p_filter(unsigned int ucfg_mctp_msg_p2p_filter); +int iSetIB_RX_FILTER_MODE_cfg_haq_abort_mode(unsigned int ucfg_haq_abort_mode); +int iSetIB_RX_FILTER_MODE_cfg_msix_poison_filter(unsigned int ucfg_msix_poison_filter); +int iSetIB_RX_FILTER_MODE_cfg_msg_poison_forward(unsigned int ucfg_msg_poison_forward); +int iSetIB_RX_FILTER_MODE_cfg_ats_filter_mode(unsigned int ucfg_ats_filter_mode); +int iSetIB_RX_FILTER_MODE_cfg_native_poison_filter(unsigned int ucfg_native_poison_filter); +int iSetIB_SMMU_BYPASS_MEMATTR_cfg_smmu_bypass_memattr(unsigned int ucfg_smmu_bypass_memattr); +int iSetIB_SMMU_BYPASS_MEMATTR_cfg_smmu_bypass_snp(unsigned int ucfg_smmu_bypass_snp); +int iSetIB_SMMU_BYPASS_MEMATTR_cfg_disable_req_nosnoop(unsigned int ucfg_disable_req_nosnoop); +int iSetIB_SDI_REG_REMAP_cfg_sdi_nvme_pf_hit_en(unsigned int ucfg_sdi_nvme_pf_hit_en); +int iSetIB_SDI_REG_REMAP_cfg_sdi_nvme_addr_size(unsigned int ucfg_sdi_nvme_addr_size); +int iSetIB_SDI_REG_REMAP_cfg_sdi_dma_pf_hit_en(unsigned int ucfg_sdi_dma_pf_hit_en); +int iSetIB_SDI_REG_REMAP_cfg_sdi_dma_addr_size(unsigned int ucfg_sdi_dma_addr_size); +int iSetIB_SDI_REG_REMAP_cfg_sdi_dma_addr_base(unsigned int ucfg_sdi_dma_addr_base); +int iSetCFG_IB_POISON_PR_FORWARD_EN_cfg_ib_poison_pr_forward_en(unsigned int ucfg_ib_poison_pr_forward_en); +int iSetCFG_IB_BAR_DISP_SEL_cfg_ib_bar_disp_sel(unsigned int ucfg_ib_bar_disp_sel); +int iSetCFG_SDI_PF_FUNC_SEL_cfg_sdi_pf0_func_sel(unsigned int ucfg_sdi_pf0_func_sel); +int iSetCFG_SDI_PF_FUNC_SEL_cfg_sdi_pf1_func_sel(unsigned int ucfg_sdi_pf1_func_sel); +int iSetCFG_SDI_PF_FUNC_SEL_cfg_sdi_pf2_func_sel(unsigned int ucfg_sdi_pf2_func_sel); +int iSetCFG_SDI_PF_FUNC_SEL_cfg_sdi_pf3_func_sel(unsigned int ucfg_sdi_pf3_func_sel); +int iSetCFG_IB_ECO_REG_0_cfg_at_trans_bypass(unsigned int ucfg_at_trans_bypass); +int iSetCFG_IB_ECO_REG_0_cfg_cas_eco_disable(unsigned int ucfg_cas_eco_disable); +int iSetCFG_IB_ECO_REG_0_cfg_eco_reg_0(unsigned int ucfg_eco_reg_0); +int iSetCFG_IB_ECO_REG_1_cfg_eco_reg_1(unsigned int ucfg_eco_reg_1); +int iSetCFG_SDI_TH_CTRL_cfg_sdi_th_enable(unsigned int ucfg_sdi_th_enable); +int iSetCFG_SDI_TH_CTRL_cfg_sdi_th_mode(unsigned int ucfg_sdi_th_mode); +int iSetCFG_SDI_TH_ADDR_FILTER_cfg_sdi_th_addr_mask(unsigned int ucfg_sdi_th_addr_mask); +int iSetCFG_SDI_TH_ADDR_FILTER_cfg_sdi_th_addr_comp(unsigned int ucfg_sdi_th_addr_comp); +int iSetCFG_SDI_TH_PF_EN_cfg_sdi_th_pf_en(unsigned int ucfg_sdi_th_pf_en); +int iSetCFG_SDI_TH_PF_REMAP_cfg_sdi_th_pf0_remap(unsigned int ucfg_sdi_th_pf0_remap); +int iSetCFG_SDI_TH_PF_REMAP_cfg_sdi_th_pf1_remap(unsigned int ucfg_sdi_th_pf1_remap); +int iSetCFG_SDI_TH_PF_REMAP_cfg_sdi_th_pf2_remap(unsigned int ucfg_sdi_th_pf2_remap); +int iSetCFG_SDI_TH_PF_REMAP_cfg_sdi_th_pf3_remap(unsigned int ucfg_sdi_th_pf3_remap); +int iSetCFG_SDI_TH_PF_VF_START_FUN_cfg_sdi_th_pf0_vf_start_fun(unsigned int ucfg_sdi_th_pf0_vf_start_fun); +int iSetCFG_SDI_TH_PF_VF_START_FUN_cfg_sdi_th_pf1_vf_start_fun(unsigned int ucfg_sdi_th_pf1_vf_start_fun); +int iSetCFG_SDI_TH_PF_VF_START_FUN_cfg_sdi_th_pf2_vf_start_fun(unsigned int ucfg_sdi_th_pf2_vf_start_fun); +int iSetCFG_SDI_TH_PF_VF_START_FUN_cfg_sdi_th_pf3_vf_start_fun(unsigned int ucfg_sdi_th_pf3_vf_start_fun); +int iSetCFG_SDI_TH_PF_VF_NUM_cfg_sdi_th_pf0_vf_num(unsigned int ucfg_sdi_th_pf0_vf_num); +int iSetCFG_SDI_TH_PF_VF_NUM_cfg_sdi_th_pf1_vf_num(unsigned int ucfg_sdi_th_pf1_vf_num); +int iSetCFG_SDI_TH_PF_VF_NUM_cfg_sdi_th_pf2_vf_num(unsigned int ucfg_sdi_th_pf2_vf_num); +int iSetCFG_SDI_TH_PF_VF_NUM_cfg_sdi_th_pf3_vf_num(unsigned int ucfg_sdi_th_pf3_vf_num); +int iSetCFG_MEMATTR_WIN_EN_cfg_memattr_win_en(unsigned int ucfg_memattr_win_en); +int iSetCFG_MEMATTR_WIN_ATTR_cfg_memattr_win_attr_rd(unsigned int ucfg_memattr_win_attr_rd); +int iSetCFG_MEMATTR_WIN_ATTR_cfg_memattr_win_attr_wr(unsigned int ucfg_memattr_win_attr_wr); +int iSetCFG_MEMATTR_WIN_ADDR_cfg_memattr_win_addr(unsigned int ucfg_memattr_win_addr); +int iSetCFG_MEMATTR_WIN_MASK_cfg_memattr_win_mask(unsigned int ucfg_memattr_win_mask); +int iSetIOB_RX_NP_DELAY_CTRL_cfg_iob_rx_np_delay(unsigned int ucfg_iob_rx_np_delay); +int iSetIOB_RX_NP_DELAY_CTRL_cfg_iob_rx_np_delay_en(unsigned int ucfg_iob_rx_np_delay_en); +int iSetIOB_RX_P_DELAY_CTRL_cfg_iob_rx_p_delay(unsigned int ucfg_iob_rx_p_delay); +int iSetIOB_RX_P_DELAY_CTRL_cfg_iob_rx_p_delay_en(unsigned int ucfg_iob_rx_p_delay_en); +int iSetIOB_RX_CPL_DELAY_CTRL_cfg_iob_rx_cpl_delay(unsigned int ucfg_iob_rx_cpl_delay); +int iSetIOB_RX_CPL_DELAY_CTRL_cfg_iob_rx_cpl_delay_en(unsigned int ucfg_iob_rx_cpl_delay_en); +int iSetIB_P2P_SPACE_BASE_ADDR_0_cfg_p2p_dest_base_addr_0(unsigned int ucfg_p2p_dest_base_addr_0); +int iSetIB_P2P_SPACE_SIZE_0_cfg_p2p_dest_offset_0(unsigned int ucfg_p2p_dest_offset_0); +int iSetIB_P2P_SPACE_BASE_ADDR_1_cfg_p2p_dest_base_addr_1(unsigned int ucfg_p2p_dest_base_addr_1); +int iSetIB_P2P_SPACE_SIZE_1_cfg_p2p_dest_offset_1(unsigned int ucfg_p2p_dest_offset_1); +int iSetIB_P2P_SPACE_BASE_ADDR_2_cfg_p2p_dest_base_addr_2(unsigned int ucfg_p2p_dest_base_addr_2); +int iSetIB_P2P_SPACE_SIZE_2_cfg_p2p_dest_offset_2(unsigned int ucfg_p2p_dest_offset_2); +int iSetIB_P2P_SPACE_BASE_ADDR_3_cfg_p2p_dest_base_addr_3(unsigned int ucfg_p2p_dest_base_addr_3); +int iSetIB_P2P_SPACE_SIZE_3_cfg_p2p_dest_offset_3(unsigned int ucfg_p2p_dest_offset_3); +int iSetIB_P2P_BR_DST_cfg_p2p_br_dst_start(unsigned int ucfg_p2p_br_dst_start); +int iSetIB_P2P_BR_DST_cfg_p2p_br_dst_end(unsigned int ucfg_p2p_br_dst_end); +int iSetIB_P2P_DEST_ADDR_cfg_p2p_dst_addr(unsigned int ucfg_p2p_dst_addr); +int iSetIB_P2P_ROUTE_CONTROL_cfg_p2p_route_dst_enable(unsigned int ucfg_p2p_route_dst_enable); +int iSetIB_P2P_ROUTE_CONTROL_cfg_p2p_br_enable(unsigned int ucfg_p2p_br_enable); +int iSetIB_P2P_ROUTE_CONTROL_cfg_p2p_space_0_enable(unsigned int ucfg_p2p_space_0_enable); +int iSetIB_P2P_ROUTE_CONTROL_cfg_p2p_space_1_enable(unsigned int ucfg_p2p_space_1_enable); +int iSetIB_P2P_ROUTE_CONTROL_cfg_p2p_space_2_enable(unsigned int ucfg_p2p_space_2_enable); +int iSetIB_P2P_ROUTE_CONTROL_cfg_p2p_space_3_enable(unsigned int ucfg_p2p_space_3_enable); +int iSetIB_P2P_ATTR_CTRL_cfg_p2p_mem_attr_replace_en(unsigned int ucfg_p2p_mem_attr_replace_en); +int iSetIB_P2P_ATTR_CTRL_cfg_p2p_mem_attr(unsigned int ucfg_p2p_mem_attr); +int iSetIB_P2P_ATTR_CTRL_cfg_p2p_snp_attr(unsigned int ucfg_p2p_snp_attr); +int iSetIB_P2P_ATTR_CTRL_cfg_p2p_mem_attr_pr(unsigned int ucfg_p2p_mem_attr_pr); +int iSetIB_P2P_ATTR_CTRL_cfg_p2p_snp_attr_pr(unsigned int ucfg_p2p_snp_attr_pr); +int iSetIB_P2P_CREDIT_CTRL_cfg_p2p_credit_num(unsigned int ucfg_p2p_credit_num); +int iSetIB_P2P_CREDIT_CTRL_cfg_p2p_credit_ctrl_enable(unsigned int ucfg_p2p_credit_ctrl_enable); +int iSetIB_P2P_CREDIT_CTRL_cfg_p2p_credit_adjust_enable(unsigned int ucfg_p2p_credit_adjust_enable); +int iSetIB_P2P_CREDIT_CTRL_cfg_p2p_block_threshold_l(unsigned int ucfg_p2p_block_threshold_l); +int iSetIB_P2P_CREDIT_CTRL_cfg_p2p_block_threshold_h(unsigned int ucfg_p2p_block_threshold_h); +int iSetIB_P2P_CREDIT_CTRL_cfg_p2p_block_threshold_cpl(unsigned int ucfg_p2p_block_threshold_cpl); +int iSetHAQ_GLOBAL_CTRL_cfg_haq_enable(unsigned int ucfg_haq_enable); +int iSetHAQ_GLOBAL_CTRL_cfg_haq_msg_len_ch0(unsigned int ucfg_haq_msg_len_ch0); +int iSetHAQ_GLOBAL_CTRL_cfg_haq_msg_len_ch1(unsigned int ucfg_haq_msg_len_ch1); +int iSetHAQ_GLOBAL_CTRL_cfg_haq_msg_mem_attr(unsigned int ucfg_haq_msg_mem_attr); +int iSetHAQ_GLOBAL_CTRL_cfg_haq_msg_len_ch2(unsigned int ucfg_haq_msg_len_ch2); +int iSetHAQ_GLOBAL_CTRL_cfg_haq_msg_len_ch3(unsigned int ucfg_haq_msg_len_ch3); +int iSetHAQ_MSG_CH_01_ATTR_cfg_haq_msg_ch_0_id(unsigned int ucfg_haq_msg_ch_0_id); +int iSetHAQ_MSG_CH_01_ATTR_cfg_haq_msg_ch_0_ost(unsigned int ucfg_haq_msg_ch_0_ost); +int iSetHAQ_MSG_CH_01_ATTR_cfg_haq_msg_ch_1_id(unsigned int ucfg_haq_msg_ch_1_id); +int iSetHAQ_MSG_CH_01_ATTR_cfg_haq_msg_ch_1_ost(unsigned int ucfg_haq_msg_ch_1_ost); +int iSetHAQ_MSG_CH_23_ATTR_cfg_haq_msg_ch_2_id(unsigned int ucfg_haq_msg_ch_2_id); +int iSetHAQ_MSG_CH_23_ATTR_cfg_haq_msg_ch_2_ost(unsigned int ucfg_haq_msg_ch_2_ost); +int iSetHAQ_MSG_CH_23_ATTR_cfg_haq_msg_ch_3_id(unsigned int ucfg_haq_msg_ch_3_id); +int iSetHAQ_MSG_CH_23_ATTR_cfg_haq_msg_ch_3_ost(unsigned int ucfg_haq_msg_ch_3_ost); +int iSetHAQ_MSG_CH_0_ADDR_L_cfg_haq_msg_ch_0_addr_l(unsigned int ucfg_haq_msg_ch_0_addr_l); +int iSetHAQ_MSG_CH_0_ADDR_H_cfg_haq_msg_ch_0_addr_h(unsigned int ucfg_haq_msg_ch_0_addr_h); +int iSetHAQ_MSG_CH_1_ADDR_L_cfg_haq_msg_ch_1_addr_l(unsigned int ucfg_haq_msg_ch_1_addr_l); +int iSetHAQ_MSG_CH_1_ADDR_H_cfg_haq_msg_ch_1_addr_h(unsigned int ucfg_haq_msg_ch_1_addr_h); +int iSetHAQ_MSG_CH_2_ADDR_L_cfg_haq_msg_ch_2_addr_l(unsigned int ucfg_haq_msg_ch_2_addr_l); +int iSetHAQ_MSG_CH_2_ADDR_H_cfg_haq_msg_ch_2_addr_h(unsigned int ucfg_haq_msg_ch_2_addr_h); +int iSetHAQ_MSG_CH_3_ADDR_L_cfg_haq_msg_ch_3_addr_l(unsigned int ucfg_haq_msg_ch_3_addr_l); +int iSetHAQ_MSG_CH_3_ADDR_H_cfg_haq_msg_ch_3_addr_h(unsigned int ucfg_haq_msg_ch_3_addr_h); +int iSetHAQ_CFG_WIN_SEL_cfg_haq_cfg_win_sel(unsigned int ucfg_haq_cfg_win_sel); +int iSetHAQ_WIN_CTRL_0_cfg_haq_win_enable(unsigned int ucfg_haq_win_enable); +int iSetHAQ_WIN_CTRL_0_cfg_haq_split_len(unsigned int ucfg_haq_split_len); +int iSetHAQ_WIN_CTRL_0_cfg_haq_msg_ch(unsigned int ucfg_haq_msg_ch); +int iSetHAQ_WIN_CTRL_1_cfg_haq_win_size(unsigned int ucfg_haq_win_size); +int iSetHAQ_WIN_CTRL_1_cfg_haq_sub_win_size(unsigned int ucfg_haq_sub_win_size); +int iSetHAQ_WIN_CTRL_1_cfg_haq_sub_win_num(unsigned int ucfg_haq_sub_win_num); +int iSetHAQ_WIN_CTRL_2_cfg_haq_poe_qid_base(unsigned int ucfg_haq_poe_qid_base); +int iSetHAQ_WIN_CTRL_2_cfg_haq_msg_seg_id(unsigned int ucfg_haq_msg_seg_id); +int iSetHAQ_WIN_CTRL_2_cfg_haq_msg_type(unsigned int ucfg_haq_msg_type); +int iSetHAQ_WIN_BASE_L_cfg_haq_win_base_l(unsigned int ucfg_haq_win_base_l); +int iSetHAQ_WIN_BASE_H_cfg_haq_win_base_h(unsigned int ucfg_haq_win_base_h); +int iSetIB_TPH_STASH_TBL_RD_cfg_stash_tbl_rd(unsigned int ucfg_stash_tbl_rd); +int iSetIB_TPH_STASH_TBL_WR_cfg_stash_tbl_wr(unsigned int ucfg_stash_tbl_wr); +int iSetIB_TPH_STASH_TBL_STIDX_cfg_stash_tbl_stidx(unsigned int ucfg_stash_tbl_stidx); +int iSetIB_TPH_STASH_TBL_WDATA_cfg_stash_tbl_wdata(unsigned int ucfg_stash_tbl_wdata); +int iSetIB_TPH_STASH_TBL_RDATA_cfg_stash_tbl_rdata(unsigned int ucfg_stash_tbl_rdata); +int iSetIB_TPH_BYPASS_PORT_EN_cfg_port_tph_bypass(unsigned int ucfg_port_tph_bypass); +int iSetIB_TPH_REPLACE_CTRL_cfg_tph_replace_info_0(unsigned int ucfg_tph_replace_info_0); +int iSetIB_TPH_REPLACE_CTRL_cfg_tph_replace_info_1(unsigned int ucfg_tph_replace_info_1); +int iSetIB_AXIM_ARB_WEIGHT_cfg_ib_axim_arb_weight_axim_c1(unsigned int ucfg_ib_axim_arb_weight_axim_c1); +int iSetIB_AXIM_ARB_WEIGHT_cfg_ib_axim_arb_weight_axim_c2(unsigned int ucfg_ib_axim_arb_weight_axim_c2); +int iSetIB_AXIM_ARB_WEIGHT_cfg_b_axim_arb_weight_axim_sdi(unsigned int ucfg_b_axim_arb_weight_axim_sdi); +int iSetIB_AXIM_ARB_RATE_CTRL_cfg_rd_ost_ctrl_enable(unsigned int ucfg_rd_ost_ctrl_enable); +int iSetIB_AXIM_ARB_RATE_CTRL_cfg_latency_tune_enable(unsigned int ucfg_latency_tune_enable); +int iSetIB_AXIM_ARB_RD_OST_NUM_cfg_notback_threshold(unsigned int ucfg_notback_threshold); +int iSetIB_AXIM_ARB_TARGET_LAT_cfg_target_latency_rd(unsigned int ucfg_target_latency_rd); +int iSetIB_AXIM_ARB_TARGET_LAT_cfg_target_latency_wr(unsigned int ucfg_target_latency_wr); +int iSetIB_AXIM_ARB_LAT_SEL_cfg_lat_sel(unsigned int ucfg_lat_sel); +int iSetIB_AXIM_ARB_P2P_RDY_CTRL_cfg_p2p_rdy_ctrl(unsigned int ucfg_p2p_rdy_ctrl); +int iSetIB_AXIM_ARB_STATE_dfx_ib_axim_arb_state(unsigned int udfx_ib_axim_arb_state); +int iSetIB_AXIM_ARB_M0_CNT_0_dfx_ib_axim_m0_arlen_cnt(unsigned int udfx_ib_axim_m0_arlen_cnt); +int iSetIB_AXIM_ARB_M0_CNT_0_dfx_ib_axim_m0_r_cnt(unsigned int udfx_ib_axim_m0_r_cnt); +int iSetIB_AXIM_ARB_M0_CNT_1_dfx_ib_axim_m0_aw_cnt(unsigned int udfx_ib_axim_m0_aw_cnt); +int iSetIB_AXIM_ARB_M0_CNT_1_dfx_ib_axim_m0_b_cnt(unsigned int udfx_ib_axim_m0_b_cnt); +int iSetIB_AXIM_ARB_M1_CNT_0_dfx_ib_axim_m1_arlen_cnt(unsigned int udfx_ib_axim_m1_arlen_cnt); +int iSetIB_AXIM_ARB_M1_CNT_0_dfx_ib_axim_m1_r_cnt(unsigned int udfx_ib_axim_m1_r_cnt); +int iSetIB_AXIM_ARB_M1_CNT_1_dfx_ib_axim_m1_aw_cnt(unsigned int udfx_ib_axim_m1_aw_cnt); +int iSetIB_AXIM_ARB_M1_CNT_1_dfx_ib_axim_m1_b_cnt(unsigned int udfx_ib_axim_m1_b_cnt); +int iSetIB_AXIM_ARB_M0_AR_LAT_0_dfx_ib_axim_m0_arlat_cnt(unsigned int udfx_ib_axim_m0_arlat_cnt); +int iSetIB_AXIM_ARB_M0_AR_LAT_0_dfx_ib_axim_m0_arlat_curr(unsigned int udfx_ib_axim_m0_arlat_curr); +int iSetIB_AXIM_ARB_M0_AR_LAT_1_dfx_ib_axim_m0_arlat_avg(unsigned int udfx_ib_axim_m0_arlat_avg); +int iSetIB_AXIM_ARB_M0_AR_LAT_1_dfx_ib_axim_m0_arlat_max(unsigned int udfx_ib_axim_m0_arlat_max); +int iSetIB_AXIM_ARB_M0_AW_LAT_0_dfx_ib_axim_m0_awlat_cnt(unsigned int udfx_ib_axim_m0_awlat_cnt); +int iSetIB_AXIM_ARB_M0_AW_LAT_0_dfx_ib_axim_m0_awlat_curr(unsigned int udfx_ib_axim_m0_awlat_curr); +int iSetIB_AXIM_ARB_M0_AW_LAT_1_dfx_ib_axim_m0_awlat_avg(unsigned int udfx_ib_axim_m0_awlat_avg); +int iSetIB_AXIM_ARB_M0_AW_LAT_1_dfx_ib_axim_m0_awlat_max(unsigned int udfx_ib_axim_m0_awlat_max); +int iSetIB_AXIM_ARB_M1_AR_LAT_0_dfx_ib_axim_m1_arlat_cnt(unsigned int udfx_ib_axim_m1_arlat_cnt); +int iSetIB_AXIM_ARB_M1_AR_LAT_0_dfx_ib_axim_m1_arlat_curr(unsigned int udfx_ib_axim_m1_arlat_curr); +int iSetIB_AXIM_ARB_M1_AR_LAT_1_dfx_ib_axim_m1_arlat_avg(unsigned int udfx_ib_axim_m1_arlat_avg); +int iSetIB_AXIM_ARB_M1_AR_LAT_1_dfx_ib_axim_m1_arlat_max(unsigned int udfx_ib_axim_m1_arlat_max); +int iSetIB_AXIM_ARB_M1_AW_LAT_0_dfx_ib_axim_m1_awlat_cnt(unsigned int udfx_ib_axim_m1_awlat_cnt); +int iSetIB_AXIM_ARB_M1_AW_LAT_0_dfx_ib_axim_m1_awlat_curr(unsigned int udfx_ib_axim_m1_awlat_curr); +int iSetIB_AXIM_ARB_M1_AW_LAT_1_dfx_ib_axim_m1_awlat_avg(unsigned int udfx_ib_axim_m1_awlat_avg); +int iSetIB_AXIM_ARB_M1_AW_LAT_1_dfx_ib_axim_m1_awlat_max(unsigned int udfx_ib_axim_m1_awlat_max); +int iSetIB_AXIM_ARB_HAQ_CURR_SEQ_NUM_dfx_haq_seq_num_0(unsigned int udfx_haq_seq_num_0); +int iSetIB_AXIM_ARB_HAQ_CURR_SEQ_NUM_dfx_haq_seq_num_1(unsigned int udfx_haq_seq_num_1); +int iSetIB_AXIM_ARB_HAQ_CURR_SEQ_NUM_dfx_haq_seq_num_2(unsigned int udfx_haq_seq_num_2); +int iSetIB_AXIM_ARB_HAQ_CURR_SEQ_NUM_dfx_haq_seq_num_3(unsigned int udfx_haq_seq_num_3); +int iSetIB_AXIM_ARB_HAQ_TRANS_CNT_0_dfx_haq_msg_cnt_0(unsigned int udfx_haq_msg_cnt_0); +int iSetIB_AXIM_ARB_HAQ_TRANS_CNT_0_dfx_haq_msg_cnt_1(unsigned int udfx_haq_msg_cnt_1); +int iSetIB_AXIM_ARB_HAQ_SEQ_NUM_STS_0_dfx_haq_seq_num_sts_0(unsigned int udfx_haq_seq_num_sts_0); +int iSetIB_AXIM_ARB_HAQ_SEQ_NUM_STS_1_dfx_haq_seq_num_sts_1(unsigned int udfx_haq_seq_num_sts_1); +int iSetIB_AXIM_ARB_HAQ_TRANS_CNT_1_dfx_haq_msg_cnt_2(unsigned int udfx_haq_msg_cnt_2); +int iSetIB_AXIM_ARB_HAQ_TRANS_CNT_1_dfx_haq_msg_cnt_3(unsigned int udfx_haq_msg_cnt_3); +int iSetIB_AXIM_ARB_HAQ_SEQ_NUM_STS_2_dfx_haq_seq_num_sts_2(unsigned int udfx_haq_seq_num_sts_2); +int iSetIB_AXIM_ARB_HAQ_SEQ_NUM_STS_3_dfx_haq_seq_num_sts_3(unsigned int udfx_haq_seq_num_sts_3); +int iSetIB_AXIM_ARB_P2P_SEQ_STS0_dfx_p2p_seq_sts0(unsigned int udfx_p2p_seq_sts0); +int iSetIB_AXIM_ARB_P2P_SEQ_STS1_dfx_p2p_seq_sts1(unsigned int udfx_p2p_seq_sts1); +int iSetIB_AXIM_ARB_P2P_SEQ_STS2_dfx_p2p_seq_sts2(unsigned int udfx_p2p_seq_sts2); +int iSetIB_AXIM_ARB_P2P_SEQ_STS3_dfx_p2p_seq_sts3(unsigned int udfx_p2p_seq_sts3); +int iSetIB_AXIM_ARB_P2P_STS_dfx_p2p_seq_ptr(unsigned int udfx_p2p_seq_ptr); +int iSetIB_AXIM_ARB_P2P_STS_dfx_p2p_rls_ptr(unsigned int udfx_p2p_rls_ptr); +int iSetIB_AXIM_ARB_P2P_STS_dfx_p2p_crd_num(unsigned int udfx_p2p_crd_num); +int iSetIB_AXIM_ARB_P2P_STS_dfx_crd_adj_dec(unsigned int udfx_crd_adj_dec); +int iSetIB_AXIM_ARB_P2P_STS_dfx_p2p_crd_full_err(unsigned int udfx_p2p_crd_full_err); +int iSetIB_AXIM_ARB_P2P_STS_dfx_p2p_seq_req_err(unsigned int udfx_p2p_seq_req_err); +int iSetIB_CFG_STASH_TABLE_stash_lpid(unsigned int ustash_lpid); +int iSetIB_CFG_STASH_TABLE_stash_valid(unsigned int ustash_valid); +int iSetIB_CFG_STASH_TABLE_stash_lpid_valid(unsigned int ustash_lpid_valid); +int iSetIB_CFG_STASH_TABLE_stash_nid_valid(unsigned int ustash_nid_valid); +int iSetIB_CFG_TPH_cfg_stat_tlp_unit(unsigned int ucfg_stat_tlp_unit); +int iSetIB_CFG_TPH_cfg_stat_tlp_time(unsigned int ucfg_stat_tlp_time); +int iSetIB_CFG_TPH_cfg_stat_tlp_clr(unsigned int ucfg_stat_tlp_clr); +int iSetIB_CFG_TPH_cfg_stash_enable(unsigned int ucfg_stash_enable); +int iSetIB_CFG_TPH_cfg_tph_mode(unsigned int ucfg_tph_mode); +int iSetIB_CFG_TPH_cfg_latency_axim_sel(unsigned int ucfg_latency_axim_sel); +int iSetIB_CFG_TPH_cfg_stash_adjust_step(unsigned int ucfg_stash_adjust_step); +int iSetIB_CFG_TPH_cfg_stash_exceed_stat_omit(unsigned int ucfg_stash_exceed_stat_omit); +int iSetIB_CFG_TPH_cfg_ref_latency_lev(unsigned int ucfg_ref_latency_lev); +int iSetIB_CFG_TPH_BANDWIDTH_EXCEED_cfg_tph_bw_exceed(unsigned int ucfg_tph_bw_exceed); +int iSetIB_CFG_PH_MAP_TO_TARGET_cfg_ph_wr_target(unsigned int ucfg_ph_wr_target); +int iSetIB_CFG_PH_MAP_TO_TARGET_cfg_ph_rd_target(unsigned int ucfg_ph_rd_target); +int iSetIB_CFG_STASH_DATA_TYPE_cfg_data_type_stash_enable(unsigned int ucfg_data_type_stash_enable); +int iSetIB_CFG_DATA_TYPE_DESCRIPTOR_cfg_data_type_descriptor_lower(unsigned int ucfg_data_type_descriptor_lower); +int iSetIB_CFG_DATA_TYPE_DESCRIPTOR_cfg_data_type_descriptor_upper(unsigned int ucfg_data_type_descriptor_upper); +int iSetIB_CFG_DATA_TYPE_PACKET_cfg_data_type_head_lower(unsigned int ucfg_data_type_head_lower); +int iSetIB_CFG_DATA_TYPE_PACKET_cfg_data_type_head_upper(unsigned int ucfg_data_type_head_upper); +int iSetIB_CFG_DATA_TYPE_PACKET_cfg_data_type_data_lower(unsigned int ucfg_data_type_data_lower); +int iSetIB_CFG_DATA_TYPE_PACKET_cfg_data_type_data_upper(unsigned int ucfg_data_type_data_upper); +int iSetIB_WR_ADJUST_BW_LIMIT_ib_wr_adjust_bw_limit(unsigned int uib_wr_adjust_bw_limit); +int iSetIB_STAT_TLP_BW_AVERAGE_ib_stat_tlp_bw_average(unsigned int uib_stat_tlp_bw_average); + +/* Define the union csr_pcie_err_mapping_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_err_mapping : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_err_mapping_u; + +/* Define the union csr_pcie_ce_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ce_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_ce_ena_u; + +/* Define the union csr_pcie_unf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_unf_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_unf_ena_u; + +/* Define the union csr_pcie_uf_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_uf_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_uf_ena_u; + +/* Define the union csr_pcie_ce_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ce_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_ce_status_u; + +/* Define the union csr_pcie_unf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_unf_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_unf_status_u; + +/* Define the union csr_pcie_uf_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_uf_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_uf_status_u; + +/* Define the union csr_pcie_ni_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ni_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_ni_ena_u; + +/* Define the union csr_pcie_ni_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ni_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_ni_status_u; + +/* Define the union csr_pcie_ce_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_ce_cnt_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_ce_cnt_cfg_u; + +/* Define the union csr_cfg_intx_clr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_intx_clr_en : 20; /* [19:0] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_intx_clr_en_u; + +/* Define the union csr_cfg_intx_deassert_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_intx_deassert_mode : 20; /* [19:0] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_intx_deassert_mode_u; + +/* Define the union csr_cfg_odr_disp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_odr_disp_ctrl : 12; /* [11:0] */ + u32 rsv_2 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_odr_disp_ctrl_u; + +/* Define the union csr_cfg_port_err_clr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_err_clr_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_port_err_clr_en_u; + +/* Define the union csr_cfg_odr_disp_misc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_odr_disp_misc_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_odr_disp_misc_ctrl_u; + +/* Define the union csr_dfx_port_intx_pending_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_intx_pending_cnt : 9; /* [8:0] */ + u32 rsv_3 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_port_intx_pending_cnt_u; + +/* Define the union csr_dfx_core_intx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_core_intx_cnt : 16; /* [15:0] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_core_intx_cnt_u; + +/* Define the union csr_dfx_port_err_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_ce_cnt : 16; /* [15:0] */ + u32 dfx_port_ni_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_port_err_cnt0_u; + +/* Define the union csr_dfx_port_err_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_port_fe_cnt : 16; /* [15:0] */ + u32 dfx_port_nfe_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_port_err_cnt1_u; + +/* Define the union csr_dfx_odr_p_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_odr_p_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_odr_p_cnt_u; + +/* Define the union csr_dfx_odr_np_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_odr_np_cnt : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_odr_np_cnt_u; + +/* Define the union csr_ap_ram_timing_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_ram_timing_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ap_ram_timing_cfg_u; + +/* Define the union csr_mctp_top_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 work_mode : 2; /* [1:0] */ + u32 rsv_6 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_top_ctrl_u; + +/* Define the union csr_mctp_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_if_en : 1; /* [0] */ + u32 mctp_tx_en : 1; /* [1] */ + u32 mctp_rx_if_en : 1; /* [2] */ + u32 mctp_rx_en : 1; /* [3] */ + u32 mctp_cfg_check_en : 1; /* [4] */ + u32 mctp_cfg_queue_unit : 3; /* [7:5] */ + u32 max_payload_size : 10; /* [17:8] */ + u32 mctp_substitute_drop_en : 2; /* [19:18] */ + u32 mctp_rsvd_port_num : 5; /* [24:20] */ + u32 mctp_rx_drop_en : 2; /* [26:25] */ + u32 mctp_tx_reset : 1; /* [27] */ + u32 mctp_rx_reset : 1; /* [28] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_ctrl_u; + +/* Define the union csr_mctp_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rsv0_u; + +/* Define the union csr_mctp_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rsv1_u; + +/* Define the union csr_mctp_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rsv2_u; + +/* Define the union csr_mctp_int_mapping_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mctp_msg_cpl_mapping_0 : 2; /* [1:0] */ + u32 rx_pri_msg_cpl_mapping_0 : 2; /* [3:2] */ + u32 rx_other_msg_cpl_mapping_0 : 2; /* [5:4] */ + u32 tx_msg_cpl_mapping_0 : 2; /* [7:6] */ + u32 rx_mctp_msg_drop_mapping_0 : 2; /* [9:8] */ + u32 rx_pri_msg_drop_mapping_0 : 2; /* [11:10] */ + u32 rx_other_msg_drop_mapping_0 : 2; /* [13:12] */ + u32 err_mapping_0 : 2; /* [15:14] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_int_mapping_0_u; + +/* Define the union csr_mctp_int_mapping_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mctp_msg_cpl_mapping_1 : 2; /* [1:0] */ + u32 rx_pri_msg_cpl_mapping_1 : 2; /* [3:2] */ + u32 rx_other_msg_cpl_mapping_1 : 2; /* [5:4] */ + u32 tx_msg_cpl_mapping_1 : 2; /* [7:6] */ + u32 rx_mctp_msg_drop_mapping_1 : 2; /* [9:8] */ + u32 rx_pri_msg_drop_mapping_1 : 2; /* [11:10] */ + u32 rx_other_msg_drop_mapping_1 : 2; /* [13:12] */ + u32 err_mapping_1 : 2; /* [15:14] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_int_mapping_1_u; + +/* Define the union csr_mctp_int_mapping_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mctp_msg_cpl_mapping_2 : 2; /* [1:0] */ + u32 rx_pri_msg_cpl_mapping_2 : 2; /* [3:2] */ + u32 rx_other_msg_cpl_mapping_2 : 2; /* [5:4] */ + u32 tx_msg_cpl_mapping_2 : 2; /* [7:6] */ + u32 rx_mctp_msg_drop_mapping_2 : 2; /* [9:8] */ + u32 rx_pri_msg_drop_mapping_2 : 2; /* [11:10] */ + u32 rx_other_msg_drop_mapping_2 : 2; /* [13:12] */ + u32 err_mapping_2 : 2; /* [15:14] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_int_mapping_2_u; + +/* Define the union csr_mctp_intrpt_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_sts : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_sts : 1; /* [1] */ + u32 mctp_rx_invld_pri_msg_cpl_int_sts : 1; /* [2] */ + u32 mctp_rx_other_msg_cpl_int_sts : 1; /* [3] */ + u32 mctp_rx_queue_pempty_int_sts : 1; /* [4] */ + u32 mctp_tx_check_fail_int_sts : 1; /* [5] */ + u32 mctp_rx_check_fail_int_sts : 1; /* [6] */ + u32 mctp_tx_msg_drop_int_sts : 1; /* [7] */ + u32 mctp_rx_mctp_msg_drop_int_sts : 1; /* [8] */ + u32 mctp_rx_invld_pri_msg_drop_int_sts : 1; /* [9] */ + u32 mctp_rx_other_msg_drop_int_sts : 1; /* [10] */ + u32 mctp_tx_axi_err_int_sts : 1; /* [11] */ + u32 mctp_rx_axi_err_int_sts : 1; /* [12] */ + u32 mctp_tx_2bit_ecc_err_int_sts : 1; /* [13] */ + u32 mctp_rx_2bit_ecc_err_int_sts : 1; /* [14] */ + u32 rsv_11 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_intrpt_stat_u; + +/* Define the union csr_mctp_intrpt_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_set : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_set : 1; /* [1] */ + u32 mctp_rx_invld_pri_msg_cpl_int_set : 1; /* [2] */ + u32 mctp_rx_other_msg_cpl_int_set : 1; /* [3] */ + u32 mctp_rx_queue_pempty_int_set : 1; /* [4] */ + u32 mctp_tx_check_fail_int_set : 1; /* [5] */ + u32 mctp_rx_check_fail_int_set : 1; /* [6] */ + u32 mctp_tx_msg_drop_int_set : 1; /* [7] */ + u32 mctp_rx_mctp_msg_drop_int_set : 1; /* [8] */ + u32 mctp_rx_invld_pri_msg_drop_int_set : 1; /* [9] */ + u32 mctp_rx_other_msg_drop_int_set : 1; /* [10] */ + u32 mctp_tx_axi_err_int_set : 1; /* [11] */ + u32 mctp_rx_axi_err_int_set : 1; /* [12] */ + u32 mctp_tx_2bit_ecc_err_int_set : 1; /* [13] */ + u32 mctp_rx_2bit_ecc_err_int_set : 1; /* [14] */ + u32 rsv_12 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_intrpt_set_u; + +/* Define the union csr_mctp_intrpt_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_msk : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_msk : 1; /* [1] */ + u32 mctp_rx_invld_pri_msg_cpl_int_msk : 1; /* [2] */ + u32 mctp_rx_other_msg_cpl_int_msk : 1; /* [3] */ + u32 mctp_rx_queue_pempty_int_msk : 1; /* [4] */ + u32 mctp_tx_check_fail_int_msk : 1; /* [5] */ + u32 mctp_rx_check_fail_int_msk : 1; /* [6] */ + u32 mctp_tx_msg_drop_int_msk : 1; /* [7] */ + u32 mctp_rx_mctp_msg_drop_int_msk : 1; /* [8] */ + u32 mctp_rx_invld_pri_msg_drop_int_msk : 1; /* [9] */ + u32 mctp_rx_other_msg_drop_int_msk : 1; /* [10] */ + u32 mctp_tx_axi_err_int_msk : 1; /* [11] */ + u32 mctp_rx_axi_err_int_msk : 1; /* [12] */ + u32 mctp_tx_2bit_ecc_err_int_msk : 1; /* [13] */ + u32 mctp_rx_2bit_ecc_err_int_msk : 1; /* [14] */ + u32 rsv_13 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_intrpt_mask_u; + +/* Define the union csr_mctp_intrpt_source_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_msg_cpl_int_src : 1; /* [0] */ + u32 mctp_rx_mctp_msg_cpl_int_src : 1; /* [1] */ + u32 mctp_rx_invld_pri_msg_cpl_int_src : 1; /* [2] */ + u32 mctp_rx_other_msg_cpl_int_src : 1; /* [3] */ + u32 mctp_rx_queue_pempty_int_src : 1; /* [4] */ + u32 mctp_tx_check_fail_int_src : 1; /* [5] */ + u32 mctp_rx_check_fail_int_src : 1; /* [6] */ + u32 mctp_tx_msg_drop_int_src : 1; /* [7] */ + u32 mctp_rx_mctp_msg_drop_int_src : 1; /* [8] */ + u32 mctp_rx_invld_pri_msg_drop_int_src : 1; /* [9] */ + u32 mctp_rx_other_msg_drop_int_src : 1; /* [10] */ + u32 mctp_tx_axi_err_int_src : 1; /* [11] */ + u32 mctp_rx_axi_err_int_src : 1; /* [12] */ + u32 mctp_tx_2bit_ecc_err_int_src : 1; /* [13] */ + u32 mctp_rx_2bit_ecc_err_int_src : 1; /* [14] */ + u32 rsv_14 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_intrpt_source_u; + +/* Define the union csr_mctp_rx_int_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_multi_th_other : 8; /* [7:0] */ + u32 mctp_rx_multi_th_pri : 8; /* [15:8] */ + u32 mctp_rx_multi_th : 8; /* [23:16] */ + u32 rsv_15 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_int_ctrl_0_u; + +/* Define the union csr_mctp_rx_pempty_threshold_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_pempty_threshold : 8; /* [7:0] */ + u32 rsv_16 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_pempty_threshold_u; + +/* Define the union csr_mctp_rx_int_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_timeout_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_int_ctrl_1_u; + +/* Define the union csr_mctp_rx_int_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_timeout_cfg_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_int_ctrl_2_u; + +/* Define the union csr_mctp_rx_int_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_timeout_cfg_other : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_int_ctrl_3_u; + +/* Define the union csr_mctp_rx_base_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_base_addr_high_u; + +/* Define the union csr_mctp_rx_base_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_base_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_base_addr_low_u; + +/* Define the union csr_mctp_rx_queue_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_depth : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_queue_depth_u; + +/* Define the union csr_mctp_rx_queue_head_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_head : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_queue_head_u; + +/* Define the union csr_mctp_rx_queue_tail_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_queue_tail : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_queue_tail_u; + +/* Define the union csr_mctp_tx_base_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_base_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_base_addr_high_u; + +/* Define the union csr_mctp_tx_base_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_base_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_base_addr_low_u; + +/* Define the union csr_mctp_tx_queue_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_depth : 16; /* [15:0] */ + u32 rsv_20 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_queue_depth_u; + +/* Define the union csr_mctp_tx_queue_head_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_head : 16; /* [15:0] */ + u32 rsv_21 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_queue_head_u; + +/* Define the union csr_mctp_tx_queue_tail_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_queue_tail : 16; /* [15:0] */ + u32 rsv_22 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_queue_tail_u; + +/* Define the union csr_mctp_rx_axi_err_addr_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_axi_err_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_axi_err_addr_high_u; + +/* Define the union csr_mctp_rx_axi_err_addr_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_axi_err_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_axi_err_addr_low_u; + +/* Define the union csr_mctp_hdr_check0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_hdr_len_field : 10; /* [9:0] */ + u32 mctp_hdr_at_field : 2; /* [11:10] */ + u32 mctp_hdr_attr10_field : 2; /* [13:12] */ + u32 mctp_hdr_ep_field : 1; /* [14] */ + u32 mctp_hdr_td_field : 1; /* [15] */ + u32 mctp_hdr_th_field : 1; /* [16] */ + u32 mctp_hdr_rsv_field0 : 1; /* [17] */ + u32 mctp_hdr_attr2_field : 1; /* [18] */ + u32 mctp_hdr_t8_field : 1; /* [19] */ + u32 mctp_hdr_tc_field : 3; /* [22:20] */ + u32 mctp_hdr_t9_field : 1; /* [23] */ + u32 mctp_hdr_type_field : 5; /* [28:24] */ + u32 mctp_hdr_fmt_field : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_hdr_check0_u; + +/* Define the union csr_mctp_hdr_check1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_hdr_mc_field : 8; /* [7:0] */ + u32 mctp_hdr_vdm_field : 4; /* [11:8] */ + u32 mctp_hdr_padlen_field : 2; /* [13:12] */ + u32 mctp_hdr_rsv_field1 : 2; /* [15:14] */ + u32 mctp_hdr_rid_field : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_hdr_check1_u; + +/* Define the union csr_mctp_hdr_check2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_hdr_vdid_field : 16; /* [15:0] */ + u32 mctp_hdr_tid_field : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_hdr_check2_u; + +/* Define the union csr_mctp_tx_err_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_err_msg_cnt : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_err_cnt_0_u; + +/* Define the union csr_mctp_tx_err_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mcpt_tx_err_msg_axi : 16; /* [15:0] */ + u32 rsv_24 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_err_cnt_1_u; + +/* Define the union csr_mctp_rx_err_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_err_msg_check : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_err_cnt_0_u; + +/* Define the union csr_mctp_rx_err_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mcpt_rx_err_msg_tl : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_err_cnt_1_u; + +/* Define the union csr_mctp_data_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_dfifo_empty : 1; /* [0] */ + u32 mctp_rx_dfifo_pfull : 1; /* [1] */ + u32 mctp_rx_dfifo_full : 1; /* [2] */ + u32 mctp_rx_dfifo_pop_underflow : 1; /* [3] */ + u32 mctp_rx_dfifo_push_overflow : 1; /* [4] */ + u32 mctp_rx_ctrl_fifo_empty : 1; /* [5] */ + u32 mctp_rx_ctrl_fifo_full : 1; /* [6] */ + u32 mctp_rx_ctrl_fifo_error : 1; /* [7] */ + u32 mctp_rx_tail_fifo_empty : 1; /* [8] */ + u32 mctp_rx_tail_fifo_full : 1; /* [9] */ + u32 mctp_rx_tail_fifo_error : 1; /* [10] */ + u32 mctp_rx_tag_fifo_empty : 1; /* [11] */ + u32 mctp_rx_tag_fifo_full : 1; /* [12] */ + u32 mctp_rx_tag_fifo_error : 1; /* [13] */ + u32 mctp_rx_wr_fifo_empty : 1; /* [14] */ + u32 mctp_rx_wr_fifo_full : 1; /* [15] */ + u32 mctp_rx_wr_fifo_error : 1; /* [16] */ + u32 mctp_rx_p_resp_fifo_empty : 1; /* [17] */ + u32 mctp_rx_p_resp_fifo_full : 1; /* [18] */ + u32 mctp_rx_p_resp_fifo_error : 1; /* [19] */ + u32 mctp_tx_dfifo_empty : 1; /* [20] */ + u32 mctp_tx_dfifo_pfull : 1; /* [21] */ + u32 mctp_tx_dfifo_full : 1; /* [22] */ + u32 mctp_tx_dfifo_pop_underflow : 1; /* [23] */ + u32 mctp_tx_dfifo_push_overflow : 1; /* [24] */ + u32 mctp_tx_ctrl_fifo_empty : 1; /* [25] */ + u32 mctp_tx_ctrl_fifo_full : 1; /* [26] */ + u32 mctp_tx_ctrl_fifo_error : 1; /* [27] */ + u32 mctp_tx_wr_fifo_empty : 1; /* [28] */ + u32 mctp_tx_wr_fifo_full : 1; /* [29] */ + u32 mctp_tx_wr_fifo_error : 1; /* [30] */ + u32 rsv_27 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_data_fifo_status_u; + +/* Define the union csr_mctp_rx_drop_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_drop_th : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_drop_th_u; + +/* Define the union csr_mctp_rx_drop_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_fifo_overflow_pkt_num : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_drop_cnt_0_u; + +/* Define the union csr_mctp_tx_routing_err_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_mctp_routing_err_cnt : 16; /* [15:0] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_routing_err_cnt_0_u; + +/* Define the union csr_mctp_tx_routing_err_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_other_routing_err_cnt : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_routing_err_cnt_1_u; + +/* Define the union csr_mctp_tx_pkt_num_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_mctp_msg_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_pkt_num_0_u; + +/* Define the union csr_mctp_tx_pkt_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_invld_pri_msg_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_pkt_num_1_u; + +/* Define the union csr_mctp_tx_pkt_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_other_msg_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_pkt_num_2_u; + +/* Define the union csr_mctp_rx_pkt_num_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_mctp_msg_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_pkt_num_0_u; + +/* Define the union csr_mctp_rx_pkt_num_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_invld_pri_msg_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_pkt_num_1_u; + +/* Define the union csr_mctp_rx_pkt_num_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_other_msg_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_pkt_num_2_u; + +/* Define the union csr_mctp_debug_fsm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_fsm_state : 7; /* [6:0] */ + u32 mctp_rx_fsm_state : 5; /* [11:7] */ + u32 mctp_tx_outstanding_cnt : 4; /* [15:12] */ + u32 mctp_rx_outstanding_cnt : 4; /* [19:16] */ + u32 rsv_32 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_debug_fsm_u; + +/* Define the union csr_mctp_hdr_match_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_vdid_unmat : 1; /* [0] */ + u32 mctp_tx_mc_unmat : 1; /* [1] */ + u32 mctp_tx_vdm_unmat : 1; /* [2] */ + u32 mctp_tx_type_unmat : 1; /* [3] */ + u32 mctp_tx_fmt_unmat : 1; /* [4] */ + u32 mctp_rx_len_unmat : 1; /* [5] */ + u32 mctp_tx_len_unmat : 1; /* [6] */ + u32 rsv_33 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_hdr_match_stat_u; + +/* Define the union csr_mctp_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_inf_dfx_en : 1; /* [0] */ + u32 mctp_lpb_en : 1; /* [1] */ + u32 rsv_34 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_dfx_u; + +/* Define the union csr_mctp_ecc_err_injection_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_data_fifo_ecc_2bit_inject : 1; /* [0] */ + u32 mctp_tx_data_fifo_ecc_1bit_inject : 1; /* [1] */ + u32 mctp_rx_data_fifo_ecc_2bit_inject : 1; /* [2] */ + u32 mctp_rx_data_fifo_ecc_1bit_inject : 1; /* [3] */ + u32 rsv_35 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_ecc_err_injection_u; + +/* Define the union csr_mctp_rx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_ecc_1bit_err_cnt : 16; /* [15:0] */ + u32 mctp_rx_ecc_1bit_err_addr : 5; /* [20:16] */ + u32 rsv_36 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_ecc_1bit_err_cnt_u; + +/* Define the union csr_mctp_rx_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_ecc_2bit_err_cnt : 16; /* [15:0] */ + u32 mctp_rx_ecc_2bit_err_addr : 5; /* [20:16] */ + u32 rsv_37 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_ecc_2bit_err_cnt_u; + +/* Define the union csr_mctp_tx_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_ecc_1bit_err_cnt : 16; /* [15:0] */ + u32 mctp_tx_ecc_1bit_err_addr : 5; /* [20:16] */ + u32 rsv_38 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_ecc_1bit_err_cnt_u; + +/* Define the union csr_mctp_tx_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_ecc_2bit_err_cnt : 16; /* [15:0] */ + u32 mctp_tx_ecc_2bit_err_addr : 5; /* [20:16] */ + u32 rsv_39 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_ecc_2bit_err_cnt_u; + +/* Define the union csr_mctp_rx_drop_hdr_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_drop_hdr_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_drop_hdr_dw0_u; + +/* Define the union csr_mctp_rx_drop_hdr_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_drop_hdr_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_drop_hdr_dw1_u; + +/* Define the union csr_mctp_rx_drop_hdr_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_drop_hdr_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_drop_hdr_dw2_u; + +/* Define the union csr_mctp_rx_drop_hdr_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_drop_hdr_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_drop_hdr_dw3_u; + +/* Define the union csr_mctp_axuser_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_attr : 3; /* [2:0] */ + u32 mctp_rx_attr : 3; /* [5:3] */ + u32 rsv_40 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_axuser_u; + +/* Define the union csr_mctp_rx_strmid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_strmid_u; + +/* Define the union csr_mctp_tx_strmid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_strmid_u; + +/* Define the union csr_mctp_tx_broadcast_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tx_broadcast_err_cnt : 16; /* [15:0] */ + u32 mctp_tx_broadcast_fifo_empty : 1; /* [16] */ + u32 mctp_tx_broadcast_fifo_full : 1; /* [17] */ + u32 mctp_tx_broadcast_fifo_error : 1; /* [18] */ + u32 rsv_41 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_tx_broadcast_dfx_u; + +/* Define the union csr_mctp_rx_dispatch_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_unsupported_cnt : 16; /* [15:0] */ + u32 mctp_rx_dispatch_p_resp_fifo_empty : 1; /* [16] */ + u32 mctp_rx_dispatch_p_resp_fifo_full : 1; /* [17] */ + u32 mctp_rx_dispatch_p_resp_fifo_error : 1; /* [18] */ + u32 rsv_42 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mctp_rx_dispatch_dfx_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_pcie_err_mapping_u pcie_err_mapping; /* 0 */ + volatile csr_pcie_ce_ena_u pcie_ce_ena; /* 8 */ + volatile csr_pcie_unf_ena_u pcie_unf_ena; /* 10 */ + volatile csr_pcie_uf_ena_u pcie_uf_ena; /* 18 */ + volatile csr_pcie_ce_status_u pcie_ce_status; /* 20 */ + volatile csr_pcie_unf_status_u pcie_unf_status; /* 28 */ + volatile csr_pcie_uf_status_u pcie_uf_status; /* 30 */ + volatile csr_pcie_ni_ena_u pcie_ni_ena; /* 38 */ + volatile csr_pcie_ni_status_u pcie_ni_status; /* 3C */ + volatile csr_pcie_ce_cnt_cfg_u pcie_ce_cnt_cfg[27]; /* 40 */ + volatile csr_cfg_intx_clr_en_u cfg_intx_clr_en; /* 400 */ + volatile csr_cfg_intx_deassert_mode_u cfg_intx_deassert_mode; /* 404 */ + volatile csr_cfg_odr_disp_ctrl_u cfg_odr_disp_ctrl; /* 408 */ + volatile csr_cfg_port_err_clr_en_u cfg_port_err_clr_en; /* 40C */ + volatile csr_cfg_odr_disp_misc_ctrl_u cfg_odr_disp_misc_ctrl; /* 410 */ + volatile csr_dfx_port_intx_pending_cnt_u dfx_port_intx_pending_cnt; /* 500 */ + volatile csr_dfx_core_intx_cnt_u dfx_core_intx_cnt; /* 504 */ + volatile csr_dfx_port_err_cnt0_u dfx_port_err_cnt0; /* 510 */ + volatile csr_dfx_port_err_cnt1_u dfx_port_err_cnt1; /* 514 */ + volatile csr_dfx_odr_p_cnt_u dfx_odr_p_cnt; /* 520 */ + volatile csr_dfx_odr_np_cnt_u dfx_odr_np_cnt; /* 524 */ + volatile csr_ap_ram_timing_cfg_u ap_ram_timing_cfg; /* 800 */ + volatile csr_mctp_top_ctrl_u mctp_top_ctrl; /* 1000 */ + volatile csr_mctp_ctrl_u mctp_ctrl[3]; /* 1004 */ + volatile csr_mctp_rsv0_u mctp_rsv0[3]; /* 1008 */ + volatile csr_mctp_rsv1_u mctp_rsv1[3]; /* 100C */ + volatile csr_mctp_rsv2_u mctp_rsv2[3]; /* 1010 */ + volatile csr_mctp_int_mapping_0_u mctp_int_mapping_0; /* 1014 */ + volatile csr_mctp_int_mapping_1_u mctp_int_mapping_1; /* 1214 */ + volatile csr_mctp_int_mapping_2_u mctp_int_mapping_2; /* 1414 */ + volatile csr_mctp_intrpt_stat_u mctp_intrpt_stat[3]; /* 1018 */ + volatile csr_mctp_intrpt_set_u mctp_intrpt_set[3]; /* 101C */ + volatile csr_mctp_intrpt_mask_u mctp_intrpt_mask[3]; /* 1020 */ + volatile csr_mctp_intrpt_source_u mctp_intrpt_source[3]; /* 1024 */ + volatile csr_mctp_rx_int_ctrl_0_u mctp_rx_int_ctrl_0[3]; /* 1028 */ + volatile csr_mctp_rx_pempty_threshold_u mctp_rx_pempty_threshold[3]; /* 1030 */ + volatile csr_mctp_rx_int_ctrl_1_u mctp_rx_int_ctrl_1[3]; /* 1034 */ + volatile csr_mctp_rx_int_ctrl_2_u mctp_rx_int_ctrl_2[3]; /* 1038 */ + volatile csr_mctp_rx_int_ctrl_3_u mctp_rx_int_ctrl_3[3]; /* 103C */ + volatile csr_mctp_rx_base_addr_high_u mctp_rx_base_addr_high[3]; /* 1040 */ + volatile csr_mctp_rx_base_addr_low_u mctp_rx_base_addr_low[3]; /* 1044 */ + volatile csr_mctp_rx_queue_depth_u mctp_rx_queue_depth[3]; /* 1048 */ + volatile csr_mctp_rx_queue_head_u mctp_rx_queue_head[3]; /* 1050 */ + volatile csr_mctp_rx_queue_tail_u mctp_rx_queue_tail[3]; /* 1054 */ + volatile csr_mctp_tx_base_addr_high_u mctp_tx_base_addr_high[3]; /* 1060 */ + volatile csr_mctp_tx_base_addr_low_u mctp_tx_base_addr_low[3]; /* 1064 */ + volatile csr_mctp_tx_queue_depth_u mctp_tx_queue_depth[3]; /* 1068 */ + volatile csr_mctp_tx_queue_head_u mctp_tx_queue_head[3]; /* 1070 */ + volatile csr_mctp_tx_queue_tail_u mctp_tx_queue_tail[3]; /* 1074 */ + volatile csr_mctp_rx_axi_err_addr_high_u mctp_rx_axi_err_addr_high[3]; /* 1080 */ + volatile csr_mctp_rx_axi_err_addr_low_u mctp_rx_axi_err_addr_low[3]; /* 1084 */ + volatile csr_mctp_hdr_check0_u mctp_hdr_check0[3]; /* 10A0 */ + volatile csr_mctp_hdr_check1_u mctp_hdr_check1[3]; /* 10A4 */ + volatile csr_mctp_hdr_check2_u mctp_hdr_check2[3]; /* 10A8 */ + volatile csr_mctp_tx_err_cnt_0_u mctp_tx_err_cnt_0[3]; /* 10B0 */ + volatile csr_mctp_tx_err_cnt_1_u mctp_tx_err_cnt_1[3]; /* 10B4 */ + volatile csr_mctp_rx_err_cnt_0_u mctp_rx_err_cnt_0[3]; /* 10B8 */ + volatile csr_mctp_rx_err_cnt_1_u mctp_rx_err_cnt_1[3]; /* 10BC */ + volatile csr_mctp_data_fifo_status_u mctp_data_fifo_status[3]; /* 10C0 */ + volatile csr_mctp_rx_drop_th_u mctp_rx_drop_th[3]; /* 10C4 */ + volatile csr_mctp_rx_drop_cnt_0_u mctp_rx_drop_cnt_0[3]; /* 10C8 */ + volatile csr_mctp_tx_routing_err_cnt_0_u mctp_tx_routing_err_cnt_0[3]; /* 10CC */ + volatile csr_mctp_tx_routing_err_cnt_1_u mctp_tx_routing_err_cnt_1[3]; /* 10D0 */ + volatile csr_mctp_tx_pkt_num_0_u mctp_tx_pkt_num_0[3]; /* 10D4 */ + volatile csr_mctp_tx_pkt_num_1_u mctp_tx_pkt_num_1[3]; /* 10D8 */ + volatile csr_mctp_tx_pkt_num_2_u mctp_tx_pkt_num_2[3]; /* 10DC */ + volatile csr_mctp_rx_pkt_num_0_u mctp_rx_pkt_num_0[3]; /* 10E0 */ + volatile csr_mctp_rx_pkt_num_1_u mctp_rx_pkt_num_1[3]; /* 10E4 */ + volatile csr_mctp_rx_pkt_num_2_u mctp_rx_pkt_num_2[3]; /* 10E8 */ + volatile csr_mctp_debug_fsm_u mctp_debug_fsm[3]; /* 10EC */ + volatile csr_mctp_hdr_match_stat_u mctp_hdr_match_stat[3]; /* 10F0 */ + volatile csr_mctp_dfx_u mctp_dfx[3]; /* 10F4 */ + volatile csr_mctp_ecc_err_injection_u mctp_ecc_err_injection[3]; /* 10F8 */ + volatile csr_mctp_rx_ecc_1bit_err_cnt_u mctp_rx_ecc_1bit_err_cnt[3]; /* 10FC */ + volatile csr_mctp_rx_ecc_2bit_err_cnt_u mctp_rx_ecc_2bit_err_cnt[3]; /* 1110 */ + volatile csr_mctp_tx_ecc_1bit_err_cnt_u mctp_tx_ecc_1bit_err_cnt[3]; /* 1114 */ + volatile csr_mctp_tx_ecc_2bit_err_cnt_u mctp_tx_ecc_2bit_err_cnt[3]; /* 1118 */ + volatile csr_mctp_rx_drop_hdr_dw0_u mctp_rx_drop_hdr_dw0[3]; /* 111C */ + volatile csr_mctp_rx_drop_hdr_dw1_u mctp_rx_drop_hdr_dw1[3]; /* 1120 */ + volatile csr_mctp_rx_drop_hdr_dw2_u mctp_rx_drop_hdr_dw2[3]; /* 1124 */ + volatile csr_mctp_rx_drop_hdr_dw3_u mctp_rx_drop_hdr_dw3[3]; /* 1128 */ + volatile csr_mctp_axuser_u mctp_axuser[3]; /* 112C */ + volatile csr_mctp_rx_strmid_u mctp_rx_strmid[3]; /* 1130 */ + volatile csr_mctp_tx_strmid_u mctp_tx_strmid[3]; /* 1134 */ + volatile csr_mctp_tx_broadcast_dfx_u mctp_tx_broadcast_dfx; /* 2018 */ + volatile csr_mctp_rx_dispatch_dfx_u mctp_rx_dispatch_dfx; /* 201C */ +} S_hipciec_ap_mg_reg_REGS_TYPE; + +/* Declare the struct pointor of the module hipciec_ap_mg_reg */ +extern volatile S_hipciec_ap_mg_reg_REGS_TYPE *gophipciec_ap_mg_regAllReg; + +/* Declare the functions that set the member value */ +int iSetPCIE_ERR_MAPPING_pcie_err_mapping(unsigned int upcie_err_mapping); +int iSetPCIE_CE_ENA_pcie_ce_ena(unsigned int upcie_ce_ena); +int iSetPCIE_UNF_ENA_pcie_unf_ena(unsigned int upcie_unf_ena); +int iSetPCIE_UF_ENA_pcie_uf_ena(unsigned int upcie_uf_ena); +int iSetPCIE_CE_STATUS_pcie_ce_status(unsigned int upcie_ce_status); +int iSetPCIE_UNF_STATUS_pcie_unf_status(unsigned int upcie_unf_status); +int iSetPCIE_UF_STATUS_pcie_uf_status(unsigned int upcie_uf_status); +int iSetPCIE_NI_ENA_pcie_ni_ena(unsigned int upcie_ni_ena); +int iSetPCIE_NI_STATUS_pcie_ni_status(unsigned int upcie_ni_status); +int iSetPCIE_CE_CNT_CFG_pcie_ce_cnt_cfg(unsigned int upcie_ce_cnt_cfg); +int iSetCFG_INTX_CLR_EN_cfg_intx_clr_en(unsigned int ucfg_intx_clr_en); +int iSetCFG_INTX_DEASSERT_MODE_cfg_intx_deassert_mode(unsigned int ucfg_intx_deassert_mode); +int iSetCFG_ODR_DISP_CTRL_cfg_odr_disp_ctrl(unsigned int ucfg_odr_disp_ctrl); +int iSetCFG_PORT_ERR_CLR_EN_cfg_port_err_clr_en(unsigned int ucfg_port_err_clr_en); +int iSetCFG_ODR_DISP_MISC_CTRL_cfg_odr_disp_misc_ctrl(unsigned int ucfg_odr_disp_misc_ctrl); +int iSetDFX_PORT_INTX_PENDING_CNT_dfx_port_intx_pending_cnt(unsigned int udfx_port_intx_pending_cnt); +int iSetDFX_CORE_INTX_CNT_dfx_core_intx_cnt(unsigned int udfx_core_intx_cnt); +int iSetDFX_PORT_ERR_CNT0_dfx_port_ce_cnt(unsigned int udfx_port_ce_cnt); +int iSetDFX_PORT_ERR_CNT0_dfx_port_ni_cnt(unsigned int udfx_port_ni_cnt); +int iSetDFX_PORT_ERR_CNT1_dfx_port_fe_cnt(unsigned int udfx_port_fe_cnt); +int iSetDFX_PORT_ERR_CNT1_dfx_port_nfe_cnt(unsigned int udfx_port_nfe_cnt); +int iSetDFX_ODR_P_CNT_dfx_odr_p_cnt(unsigned int udfx_odr_p_cnt); +int iSetDFX_ODR_NP_CNT_dfx_odr_np_cnt(unsigned int udfx_odr_np_cnt); +int iSetAP_RAM_TIMING_CFG_ap_ram_timing_cfg(unsigned int uap_ram_timing_cfg); +int iSetMCTP_TOP_CTRL_work_mode(unsigned int uwork_mode); +int iSetMCTP_CTRL_mctp_tx_if_en(unsigned int umctp_tx_if_en); +int iSetMCTP_CTRL_mctp_tx_en(unsigned int umctp_tx_en); +int iSetMCTP_CTRL_mctp_rx_if_en(unsigned int umctp_rx_if_en); +int iSetMCTP_CTRL_mctp_rx_en(unsigned int umctp_rx_en); +int iSetMCTP_CTRL_mctp_cfg_check_en(unsigned int umctp_cfg_check_en); +int iSetMCTP_CTRL_mctp_cfg_queue_unit(unsigned int umctp_cfg_queue_unit); +int iSetMCTP_CTRL_max_payload_size(unsigned int umax_payload_size); +int iSetMCTP_CTRL_mctp_substitute_drop_en(unsigned int umctp_substitute_drop_en); +int iSetMCTP_CTRL_mctp_rsvd_port_num(unsigned int umctp_rsvd_port_num); +int iSetMCTP_CTRL_mctp_rx_drop_en(unsigned int umctp_rx_drop_en); +int iSetMCTP_CTRL_mctp_tx_reset(unsigned int umctp_tx_reset); +int iSetMCTP_CTRL_mctp_rx_reset(unsigned int umctp_rx_reset); +int iSetMCTP_RSV0_mctp_rsv0(unsigned int umctp_rsv0); +int iSetMCTP_RSV1_mctp_rsv1(unsigned int umctp_rsv1); +int iSetMCTP_RSV2_mctp_rsv2(unsigned int umctp_rsv2); +int iSetMCTP_INT_MAPPING_0_rx_mctp_msg_cpl_mapping_0(unsigned int urx_mctp_msg_cpl_mapping_0); +int iSetMCTP_INT_MAPPING_0_rx_pri_msg_cpl_mapping_0(unsigned int urx_pri_msg_cpl_mapping_0); +int iSetMCTP_INT_MAPPING_0_rx_other_msg_cpl_mapping_0(unsigned int urx_other_msg_cpl_mapping_0); +int iSetMCTP_INT_MAPPING_0_tx_msg_cpl_mapping_0(unsigned int utx_msg_cpl_mapping_0); +int iSetMCTP_INT_MAPPING_0_rx_mctp_msg_drop_mapping_0(unsigned int urx_mctp_msg_drop_mapping_0); +int iSetMCTP_INT_MAPPING_0_rx_pri_msg_drop_mapping_0(unsigned int urx_pri_msg_drop_mapping_0); +int iSetMCTP_INT_MAPPING_0_rx_other_msg_drop_mapping_0(unsigned int urx_other_msg_drop_mapping_0); +int iSetMCTP_INT_MAPPING_0_err_mapping_0(unsigned int uerr_mapping_0); +int iSetMCTP_INT_MAPPING_1_rx_mctp_msg_cpl_mapping_1(unsigned int urx_mctp_msg_cpl_mapping_1); +int iSetMCTP_INT_MAPPING_1_rx_pri_msg_cpl_mapping_1(unsigned int urx_pri_msg_cpl_mapping_1); +int iSetMCTP_INT_MAPPING_1_rx_other_msg_cpl_mapping_1(unsigned int urx_other_msg_cpl_mapping_1); +int iSetMCTP_INT_MAPPING_1_tx_msg_cpl_mapping_1(unsigned int utx_msg_cpl_mapping_1); +int iSetMCTP_INT_MAPPING_1_rx_mctp_msg_drop_mapping_1(unsigned int urx_mctp_msg_drop_mapping_1); +int iSetMCTP_INT_MAPPING_1_rx_pri_msg_drop_mapping_1(unsigned int urx_pri_msg_drop_mapping_1); +int iSetMCTP_INT_MAPPING_1_rx_other_msg_drop_mapping_1(unsigned int urx_other_msg_drop_mapping_1); +int iSetMCTP_INT_MAPPING_1_err_mapping_1(unsigned int uerr_mapping_1); +int iSetMCTP_INT_MAPPING_2_rx_mctp_msg_cpl_mapping_2(unsigned int urx_mctp_msg_cpl_mapping_2); +int iSetMCTP_INT_MAPPING_2_rx_pri_msg_cpl_mapping_2(unsigned int urx_pri_msg_cpl_mapping_2); +int iSetMCTP_INT_MAPPING_2_rx_other_msg_cpl_mapping_2(unsigned int urx_other_msg_cpl_mapping_2); +int iSetMCTP_INT_MAPPING_2_tx_msg_cpl_mapping_2(unsigned int utx_msg_cpl_mapping_2); +int iSetMCTP_INT_MAPPING_2_rx_mctp_msg_drop_mapping_2(unsigned int urx_mctp_msg_drop_mapping_2); +int iSetMCTP_INT_MAPPING_2_rx_pri_msg_drop_mapping_2(unsigned int urx_pri_msg_drop_mapping_2); +int iSetMCTP_INT_MAPPING_2_rx_other_msg_drop_mapping_2(unsigned int urx_other_msg_drop_mapping_2); +int iSetMCTP_INT_MAPPING_2_err_mapping_2(unsigned int uerr_mapping_2); +int iSetMCTP_INTRPT_STAT_mctp_tx_msg_cpl_int_sts(unsigned int umctp_tx_msg_cpl_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_mctp_msg_cpl_int_sts(unsigned int umctp_rx_mctp_msg_cpl_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_invld_pri_msg_cpl_int_sts(unsigned int umctp_rx_invld_pri_msg_cpl_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_other_msg_cpl_int_sts(unsigned int umctp_rx_other_msg_cpl_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_queue_pempty_int_sts(unsigned int umctp_rx_queue_pempty_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_tx_check_fail_int_sts(unsigned int umctp_tx_check_fail_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_check_fail_int_sts(unsigned int umctp_rx_check_fail_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_tx_msg_drop_int_sts(unsigned int umctp_tx_msg_drop_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_mctp_msg_drop_int_sts(unsigned int umctp_rx_mctp_msg_drop_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_invld_pri_msg_drop_int_sts(unsigned int umctp_rx_invld_pri_msg_drop_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_other_msg_drop_int_sts(unsigned int umctp_rx_other_msg_drop_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_tx_axi_err_int_sts(unsigned int umctp_tx_axi_err_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_axi_err_int_sts(unsigned int umctp_rx_axi_err_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_tx_2bit_ecc_err_int_sts(unsigned int umctp_tx_2bit_ecc_err_int_sts); +int iSetMCTP_INTRPT_STAT_mctp_rx_2bit_ecc_err_int_sts(unsigned int umctp_rx_2bit_ecc_err_int_sts); +int iSetMCTP_INTRPT_SET_mctp_tx_msg_cpl_int_set(unsigned int umctp_tx_msg_cpl_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_mctp_msg_cpl_int_set(unsigned int umctp_rx_mctp_msg_cpl_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_invld_pri_msg_cpl_int_set(unsigned int umctp_rx_invld_pri_msg_cpl_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_other_msg_cpl_int_set(unsigned int umctp_rx_other_msg_cpl_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_queue_pempty_int_set(unsigned int umctp_rx_queue_pempty_int_set); +int iSetMCTP_INTRPT_SET_mctp_tx_check_fail_int_set(unsigned int umctp_tx_check_fail_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_check_fail_int_set(unsigned int umctp_rx_check_fail_int_set); +int iSetMCTP_INTRPT_SET_mctp_tx_msg_drop_int_set(unsigned int umctp_tx_msg_drop_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_mctp_msg_drop_int_set(unsigned int umctp_rx_mctp_msg_drop_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_invld_pri_msg_drop_int_set(unsigned int umctp_rx_invld_pri_msg_drop_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_other_msg_drop_int_set(unsigned int umctp_rx_other_msg_drop_int_set); +int iSetMCTP_INTRPT_SET_mctp_tx_axi_err_int_set(unsigned int umctp_tx_axi_err_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_axi_err_int_set(unsigned int umctp_rx_axi_err_int_set); +int iSetMCTP_INTRPT_SET_mctp_tx_2bit_ecc_err_int_set(unsigned int umctp_tx_2bit_ecc_err_int_set); +int iSetMCTP_INTRPT_SET_mctp_rx_2bit_ecc_err_int_set(unsigned int umctp_rx_2bit_ecc_err_int_set); +int iSetMCTP_INTRPT_MASK_mctp_tx_msg_cpl_int_msk(unsigned int umctp_tx_msg_cpl_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_mctp_msg_cpl_int_msk(unsigned int umctp_rx_mctp_msg_cpl_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_invld_pri_msg_cpl_int_msk(unsigned int umctp_rx_invld_pri_msg_cpl_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_other_msg_cpl_int_msk(unsigned int umctp_rx_other_msg_cpl_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_queue_pempty_int_msk(unsigned int umctp_rx_queue_pempty_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_tx_check_fail_int_msk(unsigned int umctp_tx_check_fail_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_check_fail_int_msk(unsigned int umctp_rx_check_fail_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_tx_msg_drop_int_msk(unsigned int umctp_tx_msg_drop_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_mctp_msg_drop_int_msk(unsigned int umctp_rx_mctp_msg_drop_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_invld_pri_msg_drop_int_msk(unsigned int umctp_rx_invld_pri_msg_drop_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_other_msg_drop_int_msk(unsigned int umctp_rx_other_msg_drop_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_tx_axi_err_int_msk(unsigned int umctp_tx_axi_err_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_axi_err_int_msk(unsigned int umctp_rx_axi_err_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_tx_2bit_ecc_err_int_msk(unsigned int umctp_tx_2bit_ecc_err_int_msk); +int iSetMCTP_INTRPT_MASK_mctp_rx_2bit_ecc_err_int_msk(unsigned int umctp_rx_2bit_ecc_err_int_msk); +int iSetMCTP_INTRPT_SOURCE_mctp_tx_msg_cpl_int_src(unsigned int umctp_tx_msg_cpl_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_mctp_msg_cpl_int_src(unsigned int umctp_rx_mctp_msg_cpl_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_invld_pri_msg_cpl_int_src(unsigned int umctp_rx_invld_pri_msg_cpl_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_other_msg_cpl_int_src(unsigned int umctp_rx_other_msg_cpl_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_queue_pempty_int_src(unsigned int umctp_rx_queue_pempty_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_tx_check_fail_int_src(unsigned int umctp_tx_check_fail_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_check_fail_int_src(unsigned int umctp_rx_check_fail_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_tx_msg_drop_int_src(unsigned int umctp_tx_msg_drop_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_mctp_msg_drop_int_src(unsigned int umctp_rx_mctp_msg_drop_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_invld_pri_msg_drop_int_src(unsigned int umctp_rx_invld_pri_msg_drop_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_other_msg_drop_int_src(unsigned int umctp_rx_other_msg_drop_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_tx_axi_err_int_src(unsigned int umctp_tx_axi_err_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_axi_err_int_src(unsigned int umctp_rx_axi_err_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_tx_2bit_ecc_err_int_src(unsigned int umctp_tx_2bit_ecc_err_int_src); +int iSetMCTP_INTRPT_SOURCE_mctp_rx_2bit_ecc_err_int_src(unsigned int umctp_rx_2bit_ecc_err_int_src); +int iSetMCTP_RX_INT_CTRL_0_mctp_rx_multi_th_other(unsigned int umctp_rx_multi_th_other); +int iSetMCTP_RX_INT_CTRL_0_mctp_rx_multi_th_pri(unsigned int umctp_rx_multi_th_pri); +int iSetMCTP_RX_INT_CTRL_0_mctp_rx_multi_th(unsigned int umctp_rx_multi_th); +int iSetMCTP_RX_PEMPTY_THRESHOLD_mctp_rx_pempty_threshold(unsigned int umctp_rx_pempty_threshold); +int iSetMCTP_RX_INT_CTRL_1_mctp_rx_timeout_cfg(unsigned int umctp_rx_timeout_cfg); +int iSetMCTP_RX_INT_CTRL_2_mctp_rx_timeout_cfg_pri(unsigned int umctp_rx_timeout_cfg_pri); +int iSetMCTP_RX_INT_CTRL_3_mctp_rx_timeout_cfg_other(unsigned int umctp_rx_timeout_cfg_other); +int iSetMCTP_RX_BASE_ADDR_HIGH_mctp_rx_base_addr_high(unsigned int umctp_rx_base_addr_high); +int iSetMCTP_RX_BASE_ADDR_LOW_mctp_rx_base_addr_low(unsigned int umctp_rx_base_addr_low); +int iSetMCTP_RX_QUEUE_DEPTH_mctp_rx_queue_depth(unsigned int umctp_rx_queue_depth); +int iSetMCTP_RX_QUEUE_HEAD_mctp_rx_queue_head(unsigned int umctp_rx_queue_head); +int iSetMCTP_RX_QUEUE_TAIL_mctp_rx_queue_tail(unsigned int umctp_rx_queue_tail); +int iSetMCTP_TX_BASE_ADDR_HIGH_mctp_tx_base_addr_high(unsigned int umctp_tx_base_addr_high); +int iSetMCTP_TX_BASE_ADDR_LOW_mctp_tx_base_addr_low(unsigned int umctp_tx_base_addr_low); +int iSetMCTP_TX_QUEUE_DEPTH_mctp_tx_queue_depth(unsigned int umctp_tx_queue_depth); +int iSetMCTP_TX_QUEUE_HEAD_mctp_tx_queue_head(unsigned int umctp_tx_queue_head); +int iSetMCTP_TX_QUEUE_TAIL_mctp_tx_queue_tail(unsigned int umctp_tx_queue_tail); +int iSetMCTP_RX_AXI_ERR_ADDR_HIGH_mctp_rx_axi_err_addr_high(unsigned int umctp_rx_axi_err_addr_high); +int iSetMCTP_RX_AXI_ERR_ADDR_LOW_mctp_rx_axi_err_addr_low(unsigned int umctp_rx_axi_err_addr_low); +int iSetMCTP_HDR_CHECK0_mctp_hdr_len_field(unsigned int umctp_hdr_len_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_at_field(unsigned int umctp_hdr_at_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_attr10_field(unsigned int umctp_hdr_attr10_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_ep_field(unsigned int umctp_hdr_ep_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_td_field(unsigned int umctp_hdr_td_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_th_field(unsigned int umctp_hdr_th_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_rsv_field0(unsigned int umctp_hdr_rsv_field0); +int iSetMCTP_HDR_CHECK0_mctp_hdr_attr2_field(unsigned int umctp_hdr_attr2_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_t8_field(unsigned int umctp_hdr_t8_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_tc_field(unsigned int umctp_hdr_tc_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_t9_field(unsigned int umctp_hdr_t9_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_type_field(unsigned int umctp_hdr_type_field); +int iSetMCTP_HDR_CHECK0_mctp_hdr_fmt_field(unsigned int umctp_hdr_fmt_field); +int iSetMCTP_HDR_CHECK1_mctp_hdr_mc_field(unsigned int umctp_hdr_mc_field); +int iSetMCTP_HDR_CHECK1_mctp_hdr_vdm_field(unsigned int umctp_hdr_vdm_field); +int iSetMCTP_HDR_CHECK1_mctp_hdr_padlen_field(unsigned int umctp_hdr_padlen_field); +int iSetMCTP_HDR_CHECK1_mctp_hdr_rsv_field1(unsigned int umctp_hdr_rsv_field1); +int iSetMCTP_HDR_CHECK1_mctp_hdr_rid_field(unsigned int umctp_hdr_rid_field); +int iSetMCTP_HDR_CHECK2_mctp_hdr_vdid_field(unsigned int umctp_hdr_vdid_field); +int iSetMCTP_HDR_CHECK2_mctp_hdr_tid_field(unsigned int umctp_hdr_tid_field); +int iSetMCTP_TX_ERR_CNT_0_mctp_tx_err_msg_cnt(unsigned int umctp_tx_err_msg_cnt); +int iSetMCTP_TX_ERR_CNT_1_mcpt_tx_err_msg_axi(unsigned int umcpt_tx_err_msg_axi); +int iSetMCTP_RX_ERR_CNT_0_mctp_rx_err_msg_check(unsigned int umctp_rx_err_msg_check); +int iSetMCTP_RX_ERR_CNT_1_mcpt_rx_err_msg_tl(unsigned int umcpt_rx_err_msg_tl); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_dfifo_empty(unsigned int umctp_rx_dfifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_dfifo_pfull(unsigned int umctp_rx_dfifo_pfull); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_dfifo_full(unsigned int umctp_rx_dfifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_dfifo_pop_underflow(unsigned int umctp_rx_dfifo_pop_underflow); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_dfifo_push_overflow(unsigned int umctp_rx_dfifo_push_overflow); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_ctrl_fifo_empty(unsigned int umctp_rx_ctrl_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_ctrl_fifo_full(unsigned int umctp_rx_ctrl_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_ctrl_fifo_error(unsigned int umctp_rx_ctrl_fifo_error); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_tail_fifo_empty(unsigned int umctp_rx_tail_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_tail_fifo_full(unsigned int umctp_rx_tail_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_tail_fifo_error(unsigned int umctp_rx_tail_fifo_error); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_tag_fifo_empty(unsigned int umctp_rx_tag_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_tag_fifo_full(unsigned int umctp_rx_tag_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_tag_fifo_error(unsigned int umctp_rx_tag_fifo_error); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_wr_fifo_empty(unsigned int umctp_rx_wr_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_wr_fifo_full(unsigned int umctp_rx_wr_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_wr_fifo_error(unsigned int umctp_rx_wr_fifo_error); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_p_resp_fifo_empty(unsigned int umctp_rx_p_resp_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_p_resp_fifo_full(unsigned int umctp_rx_p_resp_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_rx_p_resp_fifo_error(unsigned int umctp_rx_p_resp_fifo_error); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_dfifo_empty(unsigned int umctp_tx_dfifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_dfifo_pfull(unsigned int umctp_tx_dfifo_pfull); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_dfifo_full(unsigned int umctp_tx_dfifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_dfifo_pop_underflow(unsigned int umctp_tx_dfifo_pop_underflow); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_dfifo_push_overflow(unsigned int umctp_tx_dfifo_push_overflow); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_ctrl_fifo_empty(unsigned int umctp_tx_ctrl_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_ctrl_fifo_full(unsigned int umctp_tx_ctrl_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_ctrl_fifo_error(unsigned int umctp_tx_ctrl_fifo_error); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_wr_fifo_empty(unsigned int umctp_tx_wr_fifo_empty); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_wr_fifo_full(unsigned int umctp_tx_wr_fifo_full); +int iSetMCTP_DATA_FIFO_STATUS_mctp_tx_wr_fifo_error(unsigned int umctp_tx_wr_fifo_error); +int iSetMCTP_RX_DROP_TH_mctp_rx_drop_th(unsigned int umctp_rx_drop_th); +int iSetMCTP_RX_DROP_CNT_0_mctp_fifo_overflow_pkt_num(unsigned int umctp_fifo_overflow_pkt_num); +int iSetMCTP_TX_ROUTING_ERR_CNT_0_mctp_tx_mctp_routing_err_cnt(unsigned int umctp_tx_mctp_routing_err_cnt); +int iSetMCTP_TX_ROUTING_ERR_CNT_1_mctp_tx_other_routing_err_cnt(unsigned int umctp_tx_other_routing_err_cnt); +int iSetMCTP_TX_PKT_NUM_0_mctp_tx_mctp_msg_num(unsigned int umctp_tx_mctp_msg_num); +int iSetMCTP_TX_PKT_NUM_1_mctp_tx_invld_pri_msg_num(unsigned int umctp_tx_invld_pri_msg_num); +int iSetMCTP_TX_PKT_NUM_2_mctp_tx_other_msg_num(unsigned int umctp_tx_other_msg_num); +int iSetMCTP_RX_PKT_NUM_0_mctp_rx_mctp_msg_num(unsigned int umctp_rx_mctp_msg_num); +int iSetMCTP_RX_PKT_NUM_1_mctp_rx_invld_pri_msg_num(unsigned int umctp_rx_invld_pri_msg_num); +int iSetMCTP_RX_PKT_NUM_2_mctp_rx_other_msg_num(unsigned int umctp_rx_other_msg_num); +int iSetMCTP_DEBUG_FSM_mctp_tx_fsm_state(unsigned int umctp_tx_fsm_state); +int iSetMCTP_DEBUG_FSM_mctp_rx_fsm_state(unsigned int umctp_rx_fsm_state); +int iSetMCTP_DEBUG_FSM_mctp_tx_outstanding_cnt(unsigned int umctp_tx_outstanding_cnt); +int iSetMCTP_DEBUG_FSM_mctp_rx_outstanding_cnt(unsigned int umctp_rx_outstanding_cnt); +int iSetMCTP_HDR_MATCH_STAT_mctp_tx_vdid_unmat(unsigned int umctp_tx_vdid_unmat); +int iSetMCTP_HDR_MATCH_STAT_mctp_tx_mc_unmat(unsigned int umctp_tx_mc_unmat); +int iSetMCTP_HDR_MATCH_STAT_mctp_tx_vdm_unmat(unsigned int umctp_tx_vdm_unmat); +int iSetMCTP_HDR_MATCH_STAT_mctp_tx_type_unmat(unsigned int umctp_tx_type_unmat); +int iSetMCTP_HDR_MATCH_STAT_mctp_tx_fmt_unmat(unsigned int umctp_tx_fmt_unmat); +int iSetMCTP_HDR_MATCH_STAT_mctp_rx_len_unmat(unsigned int umctp_rx_len_unmat); +int iSetMCTP_HDR_MATCH_STAT_mctp_tx_len_unmat(unsigned int umctp_tx_len_unmat); +int iSetMCTP_DFX_mctp_inf_dfx_en(unsigned int umctp_inf_dfx_en); +int iSetMCTP_DFX_mctp_lpb_en(unsigned int umctp_lpb_en); +int iSetMCTP_ECC_ERR_INJECTION_mctp_tx_data_fifo_ecc_2bit_inject(unsigned int umctp_tx_data_fifo_ecc_2bit_inject); +int iSetMCTP_ECC_ERR_INJECTION_mctp_tx_data_fifo_ecc_1bit_inject(unsigned int umctp_tx_data_fifo_ecc_1bit_inject); +int iSetMCTP_ECC_ERR_INJECTION_mctp_rx_data_fifo_ecc_2bit_inject(unsigned int umctp_rx_data_fifo_ecc_2bit_inject); +int iSetMCTP_ECC_ERR_INJECTION_mctp_rx_data_fifo_ecc_1bit_inject(unsigned int umctp_rx_data_fifo_ecc_1bit_inject); +int iSetMCTP_RX_ECC_1BIT_ERR_CNT_mctp_rx_ecc_1bit_err_cnt(unsigned int umctp_rx_ecc_1bit_err_cnt); +int iSetMCTP_RX_ECC_1BIT_ERR_CNT_mctp_rx_ecc_1bit_err_addr(unsigned int umctp_rx_ecc_1bit_err_addr); +int iSetMCTP_RX_ECC_2BIT_ERR_CNT_mctp_rx_ecc_2bit_err_cnt(unsigned int umctp_rx_ecc_2bit_err_cnt); +int iSetMCTP_RX_ECC_2BIT_ERR_CNT_mctp_rx_ecc_2bit_err_addr(unsigned int umctp_rx_ecc_2bit_err_addr); +int iSetMCTP_TX_ECC_1BIT_ERR_CNT_mctp_tx_ecc_1bit_err_cnt(unsigned int umctp_tx_ecc_1bit_err_cnt); +int iSetMCTP_TX_ECC_1BIT_ERR_CNT_mctp_tx_ecc_1bit_err_addr(unsigned int umctp_tx_ecc_1bit_err_addr); +int iSetMCTP_TX_ECC_2BIT_ERR_CNT_mctp_tx_ecc_2bit_err_cnt(unsigned int umctp_tx_ecc_2bit_err_cnt); +int iSetMCTP_TX_ECC_2BIT_ERR_CNT_mctp_tx_ecc_2bit_err_addr(unsigned int umctp_tx_ecc_2bit_err_addr); +int iSetMCTP_RX_DROP_HDR_DW0_mctp_rx_drop_hdr_dw0(unsigned int umctp_rx_drop_hdr_dw0); +int iSetMCTP_RX_DROP_HDR_DW1_mctp_rx_drop_hdr_dw1(unsigned int umctp_rx_drop_hdr_dw1); +int iSetMCTP_RX_DROP_HDR_DW2_mctp_rx_drop_hdr_dw2(unsigned int umctp_rx_drop_hdr_dw2); +int iSetMCTP_RX_DROP_HDR_DW3_mctp_rx_drop_hdr_dw3(unsigned int umctp_rx_drop_hdr_dw3); +int iSetMCTP_AXUSER_mctp_tx_attr(unsigned int umctp_tx_attr); +int iSetMCTP_AXUSER_mctp_rx_attr(unsigned int umctp_rx_attr); +int iSetMCTP_RX_STRMID_mctp_rx_strmid(unsigned int umctp_rx_strmid); +int iSetMCTP_TX_STRMID_mctp_tx_strmid(unsigned int umctp_tx_strmid); +int iSetMCTP_TX_BROADCAST_DFX_mctp_tx_broadcast_err_cnt(unsigned int umctp_tx_broadcast_err_cnt); +int iSetMCTP_TX_BROADCAST_DFX_mctp_tx_broadcast_fifo_empty(unsigned int umctp_tx_broadcast_fifo_empty); +int iSetMCTP_TX_BROADCAST_DFX_mctp_tx_broadcast_fifo_full(unsigned int umctp_tx_broadcast_fifo_full); +int iSetMCTP_TX_BROADCAST_DFX_mctp_tx_broadcast_fifo_error(unsigned int umctp_tx_broadcast_fifo_error); +int iSetMCTP_RX_DISPATCH_DFX_mctp_rx_unsupported_cnt(unsigned int umctp_rx_unsupported_cnt); +int iSetMCTP_RX_DISPATCH_DFX_mctp_rx_dispatch_p_resp_fifo_empty(unsigned int umctp_rx_dispatch_p_resp_fifo_empty); +int iSetMCTP_RX_DISPATCH_DFX_mctp_rx_dispatch_p_resp_fifo_full(unsigned int umctp_rx_dispatch_p_resp_fifo_full); +int iSetMCTP_RX_DISPATCH_DFX_mctp_rx_dispatch_p_resp_fifo_error(unsigned int umctp_rx_dispatch_p_resp_fifo_error); + +/* Define the union csr_msix_vector_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector : 11; /* [10:0] */ + u32 rsv_0 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_vector_num_u; + +/* Define the union csr_msix_coal_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aggre_thr : 8; /* [7:0] */ + u32 aggre_time : 8; /* [15:8] */ + u32 timeout_cnt : 8; /* [23:16] */ + u32 round : 1; /* [24] */ + u32 coal_en : 1; /* [25] */ + u32 rsv_1 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_coal_ctrl_u; + +/* Define the union csr_msix_coal_event_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending_event_cnt : 8; /* [7:0] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_coal_event_u; + +/* Define the union csr_msix_coal_time_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coal_time_unit : 17; /* [16:0] */ + u32 rsv_3 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_coal_time_unit_u; + +/* Define the union csr_msix_msg_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_addr_low_2bit : 2; /* [1:0] */ + u32 msg_addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_msg_addr_u; + +/* Define the union csr_msix_msg_up_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_up_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_msg_up_addr_u; + +/* Define the union csr_msix_msg_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msg_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_msg_data_u; + +/* Define the union csr_msix_vector_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mask : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_vector_ctrl_u; + +/* Define the union csr_msix_pending_bit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_pending_bit_u; + +/* Define the union csr_msix_sram_init_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_init_done : 1; /* [0] */ + u32 coal_table_init_done : 1; /* [1] */ + u32 init_msix_tbl : 1; /* [2] */ + u32 init_msix_coal_tbl : 1; /* [3] */ + u32 rsv_6 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_sram_init_status_u; + +/* Define the union csr_sdi_eco_register_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sdi_eco_register : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sdi_eco_register_u; + +/* Define the union csr_msix_misc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf0_int_ro : 1; /* [0] */ + u32 pf1_int_ro : 1; /* [1] */ + u32 pf2_int_ro : 1; /* [2] */ + u32 pf3_int_ro : 1; /* [3] */ + u32 rsv_7 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_misc_ctrl_u; + +/* Define the union csr_ras_int_level_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_int_level : 1; /* [0] */ + u32 ecc_2bit_int_level : 1; /* [1] */ + u32 dma_func_vec_err_int_level : 1; /* [2] */ + u32 nvme_func_vec_err_int_level : 1; /* [3] */ + u32 rsv_8 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ras_int_level_u; + +/* Define the union csr_host_access_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_cpl_idle : 1; /* [0] */ + u32 p_tlp_input_idle : 1; /* [1] */ + u32 np_tlp_input_idle : 1; /* [2] */ + u32 rsv_9 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_access_status_u; + +/* Define the union csr_tlp_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_cnt_mode : 1; /* [0] */ + u32 tlp_cnt_pf_num : 3; /* [3:1] */ + u32 tlp_cnt_vf_num : 8; /* [11:4] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tlp_cnt_cfg_u; + +/* Define the union csr_host_tlp_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_mem_cpl_pkt_cnt : 8; /* [7:0] */ + u32 tx_cfg_cpl_pkt_cnt : 8; /* [15:8] */ + u32 rx_np_mem_pkt_cnt : 8; /* [23:16] */ + u32 rx_np_cfg_pkt_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_tlp_cnt_0_u; + +/* Define the union csr_host_tlp_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_p_pkt_cnt : 8; /* [7:0] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_tlp_cnt_1_u; + +/* Define the union csr_dma_input_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_input_idle : 1; /* [0] */ + u32 dma_input_pkt_type : 3; /* [3:1] */ + u32 dma_data_input_cnt : 8; /* [11:4] */ + u32 dma_int_input_cnt : 8; /* [19:12] */ + u32 dma_p_cpl_cnt : 8; /* [27:20] */ + u32 rsv_12 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_input_status_u; + +/* Define the union csr_dma_output_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_output_idle : 1; /* [0] */ + u32 dma_output_pkt_type : 3; /* [3:1] */ + u32 dma_data_output_cnt : 8; /* [11:4] */ + u32 dma_int_output_cnt : 8; /* [19:12] */ + u32 rsv_13 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_output_status_u; + +/* Define the union csr_nvme_input_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_input_idle : 1; /* [0] */ + u32 nvme_input_pkt_type : 3; /* [3:1] */ + u32 nvme_data_input_cnt : 8; /* [11:4] */ + u32 nvme_int_input_cnt : 8; /* [19:12] */ + u32 nvme_p_cpl_cnt : 8; /* [27:20] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_input_status_u; + +/* Define the union csr_nvme_output_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_output_idle : 1; /* [0] */ + u32 nvme_output_pkt_type : 3; /* [3:1] */ + u32 nvme_data_output_cnt : 8; /* [11:4] */ + u32 nvme_int_output_cnt : 8; /* [19:12] */ + u32 rsv_15 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_output_status_u; + +/* Define the union csr_fsm_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_host_state : 2; /* [1:0] */ + u32 curr_coal_tbl_state : 3; /* [4:2] */ + u32 curr_cpl_rw_st : 3; /* [7:5] */ + u32 curr_wr_tbl_st : 3; /* [10:8] */ + u32 rsv_16 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fsm_status_u; + +/* Define the union csr_link_down_idle_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_idle : 1; /* [0] */ + u32 ap_int_tx_cpl_blk : 1; /* [1] */ + u32 ap_int_tx_np_blk : 1; /* [2] */ + u32 ap_int_tx_p_blk : 1; /* [3] */ + u32 pf0_intx_wire_status : 1; /* [4] */ + u32 pf1_intx_wire_status : 1; /* [5] */ + u32 pf2_intx_wire_status : 1; /* [6] */ + u32 pf3_intx_wire_status : 1; /* [7] */ + u32 rsv_17 : 8; /* [15:8] */ + u32 dma_int_p_ot_num : 8; /* [23:16] */ + u32 nvme_int_p_ot_num : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_down_idle_status_u; + +/* Define the union csr_ecc_err_int_src_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit : 1; /* [1] */ + u32 coal_tbl_ecc_err_1bit : 1; /* [2] */ + u32 coal_tbl_ecc_err_2bit : 1; /* [3] */ + u32 rsv_18 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecc_err_int_src_sts_u; + +/* Define the union csr_ecc_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_mask : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_mask : 1; /* [1] */ + u32 coal_tbl_ecc_err_1bit_mask : 1; /* [2] */ + u32 coal_tbl_ecc_err_2bit_mask : 1; /* [3] */ + u32 rsv_19 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecc_err_mask_u; + +/* Define the union csr_ecc_err_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_sts : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_sts : 1; /* [1] */ + u32 coal_tbl_ecc_err_1bit_sts : 1; /* [2] */ + u32 coal_tbl_ecc_err_2bit_sts : 1; /* [3] */ + u32 rsv_20 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecc_err_int_sts_u; + +/* Define the union csr_ecc_err_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_inject : 2; /* [1:0] */ + u32 coal_tbl_ecc_err_inject : 2; /* [3:2] */ + u32 rsv_21 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecc_err_inject_u; + +/* Define the union csr_ecc_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_1bit_cnt : 4; /* [3:0] */ + u32 msix_tbl_ecc_2bit_cnt : 4; /* [7:4] */ + u32 coal_tbl_ecc_1bit_cnt : 4; /* [11:8] */ + u32 coal_tbl_ecc_2bit_cnt : 4; /* [15:12] */ + u32 rsv_22 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ecc_err_cnt_u; + +/* Define the union csr_msix_tbl_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_1biterr_addr : 10; /* [9:0] */ + u32 rsv_23 : 6; /* [15:10] */ + u32 msix_tbl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_24 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_tbl_ecc_err_addr_u; + +/* Define the union csr_coal_tbl_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 coal_tbl_ecc_1biterr_addr : 10; /* [9:0] */ + u32 rsv_25 : 6; /* [15:10] */ + u32 coal_tbl_ecc_2bit_err_addr : 10; /* [25:16] */ + u32 rsv_26 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coal_tbl_ecc_err_addr_u; + +/* Define the union csr_msix_ro_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_ce : 1; /* [0] */ + u32 rsv_27 : 1; /* [1] */ + u32 coal_tbl_ecc_err_1bit_ce : 1; /* [2] */ + u32 rsv_28 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_ro_ce_u; + +/* Define the union csr_msix_ro_nfe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_tbl_ecc_err_1bit_nfe : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_nfe : 1; /* [1] */ + u32 coal_tbl_ecc_err_1bit_nfe : 1; /* [2] */ + u32 coal_tbl_ecc_err_2bit_nfe : 1; /* [3] */ + u32 dma_func_vec_err_nfe : 1; /* [4] */ + u32 nvme_func_vec_err_nfe : 1; /* [5] */ + u32 rsv_29 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_ro_nfe_u; + +/* Define the union csr_msix_ro_fe_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_30 : 1; /* [0] */ + u32 msix_tbl_ecc_err_2bit_fe : 1; /* [1] */ + u32 rsv_31 : 1; /* [2] */ + u32 coal_tbl_ecc_err_2bit_fe : 1; /* [3] */ + u32 dma_func_vec_err_fe : 1; /* [4] */ + u32 nvme_func_vec_err_fe : 1; /* [5] */ + u32 rsv_32 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msix_ro_fe_u; + +/* Define the union csr_set_msix_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 set_msix_tbl_ecc_1bit : 1; /* [0] */ + u32 set_msix_tbl_ecc_2bit : 1; /* [1] */ + u32 set_coal_tbl_ecc_1bit : 1; /* [2] */ + u32 set_coal_tbl_ecc_2bit : 1; /* [3] */ + u32 rsv_33 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_set_msix_int_u; + +/* Define the union csr_abnormal_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_func_vec_err_sts : 1; /* [0] */ + u32 nvme_func_vec_err_sts : 1; /* [1] */ + u32 rsv_34 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_abnormal_int_sts_u; + +/* Define the union csr_abnormal_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_func_vec_err_mask : 1; /* [0] */ + u32 nvme_func_vec_err_mask : 1; /* [1] */ + u32 rsv_35 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_abnormal_int_mask_u; + +/* Define the union csr_abnormal_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_func_vec_err_set : 1; /* [0] */ + u32 nvme_func_vec_err_set : 1; /* [1] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_abnormal_int_set_u; + +/* Define the union csr_abnormal_int_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_func_vec_err_ro : 1; /* [0] */ + u32 nvme_func_vec_err_ro : 1; /* [1] */ + u32 rsv_37 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_abnormal_int_ro_u; + +/* Define the union csr_dma_err_func_vec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_dma_pf_num : 3; /* [2:0] */ + u32 rsv_38 : 3; /* [5:3] */ + u32 err_dma_vf_num : 8; /* [13:6] */ + u32 rsv_39 : 5; /* [18:14] */ + u32 err_dma_vector : 11; /* [29:19] */ + u32 rsv_40 : 1; /* [30] */ + u32 dma_int_null : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_err_func_vec_u; + +/* Define the union csr_nvme_err_func_vec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_nvme_pf_num : 3; /* [2:0] */ + u32 rsv_41 : 3; /* [5:3] */ + u32 err_nvme_vf_num : 8; /* [13:6] */ + u32 rsv_42 : 5; /* [18:14] */ + u32 err_nvme_vector : 11; /* [29:19] */ + u32 rsv_43 : 1; /* [30] */ + u32 nvme_int_null : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_err_func_vec_u; + +/* Define the union csr_int_idbo_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf0_int_idbo : 1; /* [0] */ + u32 pf1_int_idbo : 1; /* [1] */ + u32 pf2_int_idbo : 1; /* [2] */ + u32 pf3_int_idbo : 1; /* [3] */ + u32 rsv_44 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_idbo_ctrl_u; + +/* Define the union csr_int_ns_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf0_int_ns : 1; /* [0] */ + u32 pf1_int_ns : 1; /* [1] */ + u32 pf2_int_ns : 1; /* [2] */ + u32 pf3_int_ns : 1; /* [3] */ + u32 rsv_45 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_ns_ctrl_u; + +/* Define the union csr_tl_reg_dfx_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_reg_dfx_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_reg_dfx_addr_u; + +/* Define the union csr_tl_reg_dfx_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl_reg_dfx_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_reg_dfx_data_u; + +/* Define the union csr_err_func_vec_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_err_func_vec_cnt : 16; /* [15:0] */ + u32 nvme_err_func_vec_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_err_func_vec_cnt_u; + +/* Define the union csr_int_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_data_sel : 1; /* [0] */ + u32 pending_event_clr : 1; /* [1] */ + u32 rsv_46 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_ctrl_u; + +/* Define the union csr_int_tph_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf0_int_th : 1; /* [0] */ + u32 pf0_int_st : 8; /* [8:1] */ + u32 pf0_int_ph : 2; /* [10:9] */ + u32 rsv_47 : 5; /* [15:11] */ + u32 pf1_int_th : 1; /* [16] */ + u32 pf1_int_st : 8; /* [24:17] */ + u32 pf1_int_ph : 2; /* [26:25] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tph_ctrl0_u; + +/* Define the union csr_int_tph_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf2_int_th : 1; /* [0] */ + u32 pf2_int_st : 8; /* [8:1] */ + u32 pf2_int_ph : 2; /* [10:9] */ + u32 rsv_49 : 5; /* [15:11] */ + u32 pf3_int_th : 1; /* [16] */ + u32 pf3_int_st : 8; /* [24:17] */ + u32 pf3_int_ph : 2; /* [26:25] */ + u32 rsv_50 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_tph_ctrl1_u; + +/* Define the union csr_net_ecam_bus_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_ecam_bus_num : 8; /* [7:0] */ + u32 net_th_enable : 1; /* [8] */ + u32 rsv_51 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_net_ecam_bus_num_u; + +/* Define the union csr_net_pf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_1st_pf_num : 3; /* [2:0] */ + u32 net_2nd_pf_num : 3; /* [5:3] */ + u32 rsv_52 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_net_pf_num_u; + +/* Define the union csr_net_first_vf_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_pf0_vf_first_num : 16; /* [15:0] */ + u32 net_pf1_vf_first_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_net_first_vf_num_u; + +/* Define the union csr_net_vf_stride_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_pf0_vf_stride : 16; /* [15:0] */ + u32 net_pf1_vf_stride : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_net_vf_stride_u; + +/* Define the union csr_net_ecam_base_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 net_ecam_base : 20; /* [19:0] */ + u32 rsv_53 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_net_ecam_base_u; + +/* Define the union csr_err_response_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_resp : 2; /* [1:0] */ + u32 clr_err_resp : 1; /* [2] */ + u32 port_idle : 1; /* [3] */ + u32 rsv_54 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_err_response_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msix_vector_num_u msix_vector_num; /* 0 */ + volatile csr_msix_coal_ctrl_u msix_coal_ctrl; /* 4 */ + volatile csr_msix_coal_event_u msix_coal_event; /* 8 */ + volatile csr_msix_coal_time_unit_u msix_coal_time_unit; /* C */ + volatile csr_msix_msg_addr_u msix_msg_addr; /* 10 */ + volatile csr_msix_msg_up_addr_u msix_msg_up_addr; /* 14 */ + volatile csr_msix_msg_data_u msix_msg_data; /* 18 */ + volatile csr_msix_vector_ctrl_u msix_vector_ctrl; /* 1C */ + volatile csr_msix_pending_bit_u msix_pending_bit; /* 20 */ + volatile csr_msix_sram_init_status_u msix_sram_init_status; /* 24 */ + volatile csr_sdi_eco_register_u sdi_eco_register; /* 28 */ + volatile csr_msix_misc_ctrl_u msix_misc_ctrl; /* 2C */ + volatile csr_ras_int_level_u ras_int_level; /* 30 */ + volatile csr_host_access_status_u host_access_status; /* 50 */ + volatile csr_tlp_cnt_cfg_u tlp_cnt_cfg; /* 54 */ + volatile csr_host_tlp_cnt_0_u host_tlp_cnt_0; /* 58 */ + volatile csr_host_tlp_cnt_1_u host_tlp_cnt_1; /* 5C */ + volatile csr_dma_input_status_u dma_input_status; /* 60 */ + volatile csr_dma_output_status_u dma_output_status; /* 64 */ + volatile csr_nvme_input_status_u nvme_input_status; /* 68 */ + volatile csr_nvme_output_status_u nvme_output_status; /* 6C */ + volatile csr_fsm_status_u fsm_status; /* 70 */ + volatile csr_link_down_idle_status_u link_down_idle_status; /* 74 */ + volatile csr_ecc_err_int_src_sts_u ecc_err_int_src_sts; /* 78 */ + volatile csr_ecc_err_mask_u ecc_err_mask; /* 7C */ + volatile csr_ecc_err_int_sts_u ecc_err_int_sts; /* 80 */ + volatile csr_ecc_err_inject_u ecc_err_inject; /* 84 */ + volatile csr_ecc_err_cnt_u ecc_err_cnt; /* 88 */ + volatile csr_msix_tbl_ecc_err_addr_u msix_tbl_ecc_err_addr; /* 8C */ + volatile csr_coal_tbl_ecc_err_addr_u coal_tbl_ecc_err_addr; /* 90 */ + volatile csr_msix_ro_ce_u msix_ro_ce; /* 94 */ + volatile csr_msix_ro_nfe_u msix_ro_nfe; /* 98 */ + volatile csr_msix_ro_fe_u msix_ro_fe; /* 9C */ + volatile csr_set_msix_int_u set_msix_int; /* A0 */ + volatile csr_abnormal_int_sts_u abnormal_int_sts; /* A4 */ + volatile csr_abnormal_int_mask_u abnormal_int_mask; /* A8 */ + volatile csr_abnormal_int_set_u abnormal_int_set; /* AC */ + volatile csr_abnormal_int_ro_u abnormal_int_ro; /* B0 */ + volatile csr_dma_err_func_vec_u dma_err_func_vec; /* B4 */ + volatile csr_nvme_err_func_vec_u nvme_err_func_vec; /* B8 */ + volatile csr_int_idbo_ctrl_u int_idbo_ctrl; /* BC */ + volatile csr_int_ns_ctrl_u int_ns_ctrl; /* C0 */ + volatile csr_tl_reg_dfx_addr_u tl_reg_dfx_addr; /* C4 */ + volatile csr_tl_reg_dfx_data_u tl_reg_dfx_data; /* C8 */ + volatile csr_err_func_vec_cnt_u err_func_vec_cnt; /* CC */ + volatile csr_int_ctrl_u int_ctrl; /* D0 */ + volatile csr_int_tph_ctrl0_u int_tph_ctrl0; /* E0 */ + volatile csr_int_tph_ctrl1_u int_tph_ctrl1; /* E4 */ + volatile csr_net_ecam_bus_num_u net_ecam_bus_num; /* 100 */ + volatile csr_net_pf_num_u net_pf_num; /* 104 */ + volatile csr_net_first_vf_num_u net_first_vf_num; /* 108 */ + volatile csr_net_vf_stride_u net_vf_stride; /* 10C */ + volatile csr_net_ecam_base_u net_ecam_base; /* 110 */ + volatile csr_err_response_u err_response; /* 114 */ +} S_hipciec_ap_int_reg_0_REGS_TYPE; + +/* Declare the struct pointor of the module hipciec_ap_int_reg_0 */ +extern volatile S_hipciec_ap_int_reg_0_REGS_TYPE *gophipciec_ap_int_reg_0AllReg; + +/* Declare the functions that set the member value */ +int iSetMSIX_VECTOR_NUM_vector(unsigned int uvector); +int iSetMSIX_COAL_CTRL_aggre_thr(unsigned int uaggre_thr); +int iSetMSIX_COAL_CTRL_aggre_time(unsigned int uaggre_time); +int iSetMSIX_COAL_CTRL_timeout_cnt(unsigned int utimeout_cnt); +int iSetMSIX_COAL_CTRL_round(unsigned int uround); +int iSetMSIX_COAL_CTRL_coal_en(unsigned int ucoal_en); +int iSetMSIX_COAL_EVENT_pending_event_cnt(unsigned int upending_event_cnt); +int iSetMSIX_COAL_TIME_UNIT_coal_time_unit(unsigned int ucoal_time_unit); +int iSetMSIX_MSG_ADDR_msg_addr_low_2bit(unsigned int umsg_addr_low_2bit); +int iSetMSIX_MSG_ADDR_msg_addr(unsigned int umsg_addr); +int iSetMSIX_MSG_UP_ADDR_msg_up_addr(unsigned int umsg_up_addr); +int iSetMSIX_MSG_DATA_msg_data(unsigned int umsg_data); +int iSetMSIX_VECTOR_CTRL_mask(unsigned int umask); +int iSetMSIX_PENDING_BIT_pending(unsigned int upending); +int iSetMSIX_SRAM_INIT_STATUS_msix_tbl_init_done(unsigned int umsix_tbl_init_done); +int iSetMSIX_SRAM_INIT_STATUS_coal_table_init_done(unsigned int ucoal_table_init_done); +int iSetMSIX_SRAM_INIT_STATUS_init_msix_tbl(unsigned int uinit_msix_tbl); +int iSetMSIX_SRAM_INIT_STATUS_init_msix_coal_tbl(unsigned int uinit_msix_coal_tbl); +int iSetSDI_ECO_REGISTER_sdi_eco_register(unsigned int usdi_eco_register); +int iSetMSIX_MISC_CTRL_pf0_int_ro(unsigned int upf0_int_ro); +int iSetMSIX_MISC_CTRL_pf1_int_ro(unsigned int upf1_int_ro); +int iSetMSIX_MISC_CTRL_pf2_int_ro(unsigned int upf2_int_ro); +int iSetMSIX_MISC_CTRL_pf3_int_ro(unsigned int upf3_int_ro); +int iSetRAS_INT_LEVEL_ecc_1bit_int_level(unsigned int uecc_1bit_int_level); +int iSetRAS_INT_LEVEL_ecc_2bit_int_level(unsigned int uecc_2bit_int_level); +int iSetRAS_INT_LEVEL_dma_func_vec_err_int_level(unsigned int udma_func_vec_err_int_level); +int iSetRAS_INT_LEVEL_nvme_func_vec_err_int_level(unsigned int unvme_func_vec_err_int_level); +int iSetHOST_ACCESS_STATUS_tx_cpl_idle(unsigned int utx_cpl_idle); +int iSetHOST_ACCESS_STATUS_p_tlp_input_idle(unsigned int up_tlp_input_idle); +int iSetHOST_ACCESS_STATUS_np_tlp_input_idle(unsigned int unp_tlp_input_idle); +int iSetTLP_CNT_CFG_tlp_cnt_mode(unsigned int utlp_cnt_mode); +int iSetTLP_CNT_CFG_tlp_cnt_pf_num(unsigned int utlp_cnt_pf_num); +int iSetTLP_CNT_CFG_tlp_cnt_vf_num(unsigned int utlp_cnt_vf_num); +int iSetHOST_TLP_CNT_0_tx_mem_cpl_pkt_cnt(unsigned int utx_mem_cpl_pkt_cnt); +int iSetHOST_TLP_CNT_0_tx_cfg_cpl_pkt_cnt(unsigned int utx_cfg_cpl_pkt_cnt); +int iSetHOST_TLP_CNT_0_rx_np_mem_pkt_cnt(unsigned int urx_np_mem_pkt_cnt); +int iSetHOST_TLP_CNT_0_rx_np_cfg_pkt_cnt(unsigned int urx_np_cfg_pkt_cnt); +int iSetHOST_TLP_CNT_1_rx_p_pkt_cnt(unsigned int urx_p_pkt_cnt); +int iSetDMA_INPUT_STATUS_dma_input_idle(unsigned int udma_input_idle); +int iSetDMA_INPUT_STATUS_dma_input_pkt_type(unsigned int udma_input_pkt_type); +int iSetDMA_INPUT_STATUS_dma_data_input_cnt(unsigned int udma_data_input_cnt); +int iSetDMA_INPUT_STATUS_dma_int_input_cnt(unsigned int udma_int_input_cnt); +int iSetDMA_INPUT_STATUS_dma_p_cpl_cnt(unsigned int udma_p_cpl_cnt); +int iSetDMA_OUTPUT_STATUS_dma_output_idle(unsigned int udma_output_idle); +int iSetDMA_OUTPUT_STATUS_dma_output_pkt_type(unsigned int udma_output_pkt_type); +int iSetDMA_OUTPUT_STATUS_dma_data_output_cnt(unsigned int udma_data_output_cnt); +int iSetDMA_OUTPUT_STATUS_dma_int_output_cnt(unsigned int udma_int_output_cnt); +int iSetNVME_INPUT_STATUS_nvme_input_idle(unsigned int unvme_input_idle); +int iSetNVME_INPUT_STATUS_nvme_input_pkt_type(unsigned int unvme_input_pkt_type); +int iSetNVME_INPUT_STATUS_nvme_data_input_cnt(unsigned int unvme_data_input_cnt); +int iSetNVME_INPUT_STATUS_nvme_int_input_cnt(unsigned int unvme_int_input_cnt); +int iSetNVME_INPUT_STATUS_nvme_p_cpl_cnt(unsigned int unvme_p_cpl_cnt); +int iSetNVME_OUTPUT_STATUS_nvme_output_idle(unsigned int unvme_output_idle); +int iSetNVME_OUTPUT_STATUS_nvme_output_pkt_type(unsigned int unvme_output_pkt_type); +int iSetNVME_OUTPUT_STATUS_nvme_data_output_cnt(unsigned int unvme_data_output_cnt); +int iSetNVME_OUTPUT_STATUS_nvme_int_output_cnt(unsigned int unvme_int_output_cnt); +int iSetFSM_STATUS_curr_host_state(unsigned int ucurr_host_state); +int iSetFSM_STATUS_curr_coal_tbl_state(unsigned int ucurr_coal_tbl_state); +int iSetFSM_STATUS_curr_cpl_rw_st(unsigned int ucurr_cpl_rw_st); +int iSetFSM_STATUS_curr_wr_tbl_st(unsigned int ucurr_wr_tbl_st); +int iSetLINK_DOWN_IDLE_STATUS_port_idle(unsigned int uport_idle); +int iSetLINK_DOWN_IDLE_STATUS_ap_int_tx_cpl_blk(unsigned int uap_int_tx_cpl_blk); +int iSetLINK_DOWN_IDLE_STATUS_ap_int_tx_np_blk(unsigned int uap_int_tx_np_blk); +int iSetLINK_DOWN_IDLE_STATUS_ap_int_tx_p_blk(unsigned int uap_int_tx_p_blk); +int iSetLINK_DOWN_IDLE_STATUS_pf0_intx_wire_status(unsigned int upf0_intx_wire_status); +int iSetLINK_DOWN_IDLE_STATUS_pf1_intx_wire_status(unsigned int upf1_intx_wire_status); +int iSetLINK_DOWN_IDLE_STATUS_pf2_intx_wire_status(unsigned int upf2_intx_wire_status); +int iSetLINK_DOWN_IDLE_STATUS_pf3_intx_wire_status(unsigned int upf3_intx_wire_status); +int iSetLINK_DOWN_IDLE_STATUS_dma_int_p_ot_num(unsigned int udma_int_p_ot_num); +int iSetLINK_DOWN_IDLE_STATUS_nvme_int_p_ot_num(unsigned int unvme_int_p_ot_num); +int iSetECC_ERR_INT_SRC_STS_msix_tbl_ecc_err_1bit(unsigned int umsix_tbl_ecc_err_1bit); +int iSetECC_ERR_INT_SRC_STS_msix_tbl_ecc_err_2bit(unsigned int umsix_tbl_ecc_err_2bit); +int iSetECC_ERR_INT_SRC_STS_coal_tbl_ecc_err_1bit(unsigned int ucoal_tbl_ecc_err_1bit); +int iSetECC_ERR_INT_SRC_STS_coal_tbl_ecc_err_2bit(unsigned int ucoal_tbl_ecc_err_2bit); +int iSetECC_ERR_MASK_msix_tbl_ecc_err_1bit_mask(unsigned int umsix_tbl_ecc_err_1bit_mask); +int iSetECC_ERR_MASK_msix_tbl_ecc_err_2bit_mask(unsigned int umsix_tbl_ecc_err_2bit_mask); +int iSetECC_ERR_MASK_coal_tbl_ecc_err_1bit_mask(unsigned int ucoal_tbl_ecc_err_1bit_mask); +int iSetECC_ERR_MASK_coal_tbl_ecc_err_2bit_mask(unsigned int ucoal_tbl_ecc_err_2bit_mask); +int iSetECC_ERR_INT_STS_msix_tbl_ecc_err_1bit_sts(unsigned int umsix_tbl_ecc_err_1bit_sts); +int iSetECC_ERR_INT_STS_msix_tbl_ecc_err_2bit_sts(unsigned int umsix_tbl_ecc_err_2bit_sts); +int iSetECC_ERR_INT_STS_coal_tbl_ecc_err_1bit_sts(unsigned int ucoal_tbl_ecc_err_1bit_sts); +int iSetECC_ERR_INT_STS_coal_tbl_ecc_err_2bit_sts(unsigned int ucoal_tbl_ecc_err_2bit_sts); +int iSetECC_ERR_INJECT_msix_tbl_ecc_err_inject(unsigned int umsix_tbl_ecc_err_inject); +int iSetECC_ERR_INJECT_coal_tbl_ecc_err_inject(unsigned int ucoal_tbl_ecc_err_inject); +int iSetECC_ERR_CNT_msix_tbl_ecc_1bit_cnt(unsigned int umsix_tbl_ecc_1bit_cnt); +int iSetECC_ERR_CNT_msix_tbl_ecc_2bit_cnt(unsigned int umsix_tbl_ecc_2bit_cnt); +int iSetECC_ERR_CNT_coal_tbl_ecc_1bit_cnt(unsigned int ucoal_tbl_ecc_1bit_cnt); +int iSetECC_ERR_CNT_coal_tbl_ecc_2bit_cnt(unsigned int ucoal_tbl_ecc_2bit_cnt); +int iSetMSIX_TBL_ECC_ERR_ADDR_msix_tbl_ecc_1biterr_addr(unsigned int umsix_tbl_ecc_1biterr_addr); +int iSetMSIX_TBL_ECC_ERR_ADDR_msix_tbl_ecc_2bit_err_addr(unsigned int umsix_tbl_ecc_2bit_err_addr); +int iSetCOAL_TBL_ECC_ERR_ADDR_coal_tbl_ecc_1biterr_addr(unsigned int ucoal_tbl_ecc_1biterr_addr); +int iSetCOAL_TBL_ECC_ERR_ADDR_coal_tbl_ecc_2bit_err_addr(unsigned int ucoal_tbl_ecc_2bit_err_addr); +int iSetMSIX_RO_CE_msix_tbl_ecc_err_1bit_ce(unsigned int umsix_tbl_ecc_err_1bit_ce); +int iSetMSIX_RO_CE_coal_tbl_ecc_err_1bit_ce(unsigned int ucoal_tbl_ecc_err_1bit_ce); +int iSetMSIX_RO_NFE_msix_tbl_ecc_err_1bit_nfe(unsigned int umsix_tbl_ecc_err_1bit_nfe); +int iSetMSIX_RO_NFE_msix_tbl_ecc_err_2bit_nfe(unsigned int umsix_tbl_ecc_err_2bit_nfe); +int iSetMSIX_RO_NFE_coal_tbl_ecc_err_1bit_nfe(unsigned int ucoal_tbl_ecc_err_1bit_nfe); +int iSetMSIX_RO_NFE_coal_tbl_ecc_err_2bit_nfe(unsigned int ucoal_tbl_ecc_err_2bit_nfe); +int iSetMSIX_RO_NFE_dma_func_vec_err_nfe(unsigned int udma_func_vec_err_nfe); +int iSetMSIX_RO_NFE_nvme_func_vec_err_nfe(unsigned int unvme_func_vec_err_nfe); +int iSetMSIX_RO_FE_msix_tbl_ecc_err_2bit_fe(unsigned int umsix_tbl_ecc_err_2bit_fe); +int iSetMSIX_RO_FE_coal_tbl_ecc_err_2bit_fe(unsigned int ucoal_tbl_ecc_err_2bit_fe); +int iSetMSIX_RO_FE_dma_func_vec_err_fe(unsigned int udma_func_vec_err_fe); +int iSetMSIX_RO_FE_nvme_func_vec_err_fe(unsigned int unvme_func_vec_err_fe); +int iSetSET_MSIX_INT_set_msix_tbl_ecc_1bit(unsigned int uset_msix_tbl_ecc_1bit); +int iSetSET_MSIX_INT_set_msix_tbl_ecc_2bit(unsigned int uset_msix_tbl_ecc_2bit); +int iSetSET_MSIX_INT_set_coal_tbl_ecc_1bit(unsigned int uset_coal_tbl_ecc_1bit); +int iSetSET_MSIX_INT_set_coal_tbl_ecc_2bit(unsigned int uset_coal_tbl_ecc_2bit); +int iSetABNORMAL_INT_STS_dma_func_vec_err_sts(unsigned int udma_func_vec_err_sts); +int iSetABNORMAL_INT_STS_nvme_func_vec_err_sts(unsigned int unvme_func_vec_err_sts); +int iSetABNORMAL_INT_MASK_dma_func_vec_err_mask(unsigned int udma_func_vec_err_mask); +int iSetABNORMAL_INT_MASK_nvme_func_vec_err_mask(unsigned int unvme_func_vec_err_mask); +int iSetABNORMAL_INT_SET_dma_func_vec_err_set(unsigned int udma_func_vec_err_set); +int iSetABNORMAL_INT_SET_nvme_func_vec_err_set(unsigned int unvme_func_vec_err_set); +int iSetABNORMAL_INT_RO_dma_func_vec_err_ro(unsigned int udma_func_vec_err_ro); +int iSetABNORMAL_INT_RO_nvme_func_vec_err_ro(unsigned int unvme_func_vec_err_ro); +int iSetDMA_ERR_FUNC_VEC_err_dma_pf_num(unsigned int uerr_dma_pf_num); +int iSetDMA_ERR_FUNC_VEC_err_dma_vf_num(unsigned int uerr_dma_vf_num); +int iSetDMA_ERR_FUNC_VEC_err_dma_vector(unsigned int uerr_dma_vector); +int iSetDMA_ERR_FUNC_VEC_dma_int_null(unsigned int udma_int_null); +int iSetNVME_ERR_FUNC_VEC_err_nvme_pf_num(unsigned int uerr_nvme_pf_num); +int iSetNVME_ERR_FUNC_VEC_err_nvme_vf_num(unsigned int uerr_nvme_vf_num); +int iSetNVME_ERR_FUNC_VEC_err_nvme_vector(unsigned int uerr_nvme_vector); +int iSetNVME_ERR_FUNC_VEC_nvme_int_null(unsigned int unvme_int_null); +int iSetINT_IDBO_CTRL_pf0_int_idbo(unsigned int upf0_int_idbo); +int iSetINT_IDBO_CTRL_pf1_int_idbo(unsigned int upf1_int_idbo); +int iSetINT_IDBO_CTRL_pf2_int_idbo(unsigned int upf2_int_idbo); +int iSetINT_IDBO_CTRL_pf3_int_idbo(unsigned int upf3_int_idbo); +int iSetINT_NS_CTRL_pf0_int_ns(unsigned int upf0_int_ns); +int iSetINT_NS_CTRL_pf1_int_ns(unsigned int upf1_int_ns); +int iSetINT_NS_CTRL_pf2_int_ns(unsigned int upf2_int_ns); +int iSetINT_NS_CTRL_pf3_int_ns(unsigned int upf3_int_ns); +int iSetTL_REG_DFX_ADDR_tl_reg_dfx_addr(unsigned int utl_reg_dfx_addr); +int iSetTL_REG_DFX_DATA_tl_reg_dfx_data(unsigned int utl_reg_dfx_data); +int iSetERR_FUNC_VEC_CNT_dma_err_func_vec_cnt(unsigned int udma_err_func_vec_cnt); +int iSetERR_FUNC_VEC_CNT_nvme_err_func_vec_cnt(unsigned int unvme_err_func_vec_cnt); +int iSetINT_CTRL_msi_data_sel(unsigned int umsi_data_sel); +int iSetINT_CTRL_pending_event_clr(unsigned int upending_event_clr); +int iSetINT_TPH_CTRL0_pf0_int_th(unsigned int upf0_int_th); +int iSetINT_TPH_CTRL0_pf0_int_st(unsigned int upf0_int_st); +int iSetINT_TPH_CTRL0_pf0_int_ph(unsigned int upf0_int_ph); +int iSetINT_TPH_CTRL0_pf1_int_th(unsigned int upf1_int_th); +int iSetINT_TPH_CTRL0_pf1_int_st(unsigned int upf1_int_st); +int iSetINT_TPH_CTRL0_pf1_int_ph(unsigned int upf1_int_ph); +int iSetINT_TPH_CTRL1_pf2_int_th(unsigned int upf2_int_th); +int iSetINT_TPH_CTRL1_pf2_int_st(unsigned int upf2_int_st); +int iSetINT_TPH_CTRL1_pf2_int_ph(unsigned int upf2_int_ph); +int iSetINT_TPH_CTRL1_pf3_int_th(unsigned int upf3_int_th); +int iSetINT_TPH_CTRL1_pf3_int_st(unsigned int upf3_int_st); +int iSetINT_TPH_CTRL1_pf3_int_ph(unsigned int upf3_int_ph); +int iSetNET_ECAM_BUS_NUM_net_ecam_bus_num(unsigned int unet_ecam_bus_num); +int iSetNET_ECAM_BUS_NUM_net_th_enable(unsigned int unet_th_enable); +int iSetNET_PF_NUM_net_1st_pf_num(unsigned int unet_1st_pf_num); +int iSetNET_PF_NUM_net_2nd_pf_num(unsigned int unet_2nd_pf_num); +int iSetNET_FIRST_VF_NUM_net_pf0_vf_first_num(unsigned int unet_pf0_vf_first_num); +int iSetNET_FIRST_VF_NUM_net_pf1_vf_first_num(unsigned int unet_pf1_vf_first_num); +int iSetNET_VF_STRIDE_net_pf0_vf_stride(unsigned int unet_pf0_vf_stride); +int iSetNET_VF_STRIDE_net_pf1_vf_stride(unsigned int unet_pf1_vf_stride); +int iSetNET_ECAM_BASE_net_ecam_base(unsigned int unet_ecam_base); +int iSetERR_RESPONSE_err_resp(unsigned int uerr_resp); +int iSetERR_RESPONSE_clr_err_resp(unsigned int uclr_err_resp); +int iSetERR_RESPONSE_port_idle(unsigned int uport_idle); + + +#endif // PCIE4_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/pcie4_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/pcie4_reg_offset.h new file mode 100644 index 000000000..06178704f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/pcie4_reg_offset.h @@ -0,0 +1,2240 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : pcie4_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/29 22:14:57 Create file +// ****************************************************************************** + +#ifndef PCIE4_REG_OFFSET_H +#define PCIE4_REG_OFFSET_H + +/* HIPCIEC_AP_IOB_RX_COM_REG Base address of Module's Register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE (0x4000) + +/* **************************************************************************** */ +/* HIPCIEC_AP_IOB_RX_COM_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x20) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x40) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x60) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x80) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xA0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xC0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xE0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x100) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x120) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x140) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x160) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x180) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1A0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1C0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1E0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x200) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x220) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x240) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x260) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x280) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2A0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2C0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2E0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x300) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x320) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x340) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x360) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x380) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3A0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3C0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3E0) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x400) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_0_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x420) /* IOB RX address transition unit control register0.Common information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x24) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x44) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x64) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x84) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xA4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xC4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xE4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x104) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x124) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x144) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x164) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x184) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1A4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1C4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1E4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x204) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x224) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x244) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x264) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x284) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2A4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2C4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2E4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x304) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x324) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x344) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x364) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x384) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3A4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3C4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3E4) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x404) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_1_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x424) /* IOB RX address transition unit control information register1.TLP information. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x28) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x48) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x68) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x88) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xA8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xC8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xE8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x108) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x128) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x148) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x168) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x188) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1A8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1C8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1E8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x208) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x228) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x248) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x268) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x288) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2A8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2C8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2E8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x308) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x328) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x348) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x368) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x388) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3A8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3C8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3E8) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x408) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_CONTROL_2_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x428) /* IOB RX address transition unit control information register2.Extend the IOB_RXATU_REGION_SIZE. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x6C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xCC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xEC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x16C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1CC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1EC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x22C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x26C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2AC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2CC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2EC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x32C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x36C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3AC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3CC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3EC) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_REGION_SIZE_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x42C) /* IOB RX address transition unit region size low 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x10) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x30) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x50) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x70) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x90) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xB0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xD0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xF0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x110) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x130) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x150) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x170) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x190) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1B0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1D0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1F0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x210) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x230) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x250) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x270) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x290) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2B0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2D0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2F0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x310) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x330) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x350) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x370) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x390) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3B0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3D0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3F0) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x410) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_L_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x430) /* IOB RX address transition unit base address low 32bit.the address is align to 4KByte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x54) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x74) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x94) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x114) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x134) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x154) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x174) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x194) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1D4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x214) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x234) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x254) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x274) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x294) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2B4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2D4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2F4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x314) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x334) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x354) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x374) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x394) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3B4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3D4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3F4) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x414) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_BASE_ADDR_H_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x434) /* IOB RX address transition unit base address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x18) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x38) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x58) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x78) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x98) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xB8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xD8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0xF8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x118) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x138) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x158) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x178) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x198) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1B8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1D8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x1F8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x218) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x238) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x258) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x278) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x298) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2B8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2D8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x2F8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x318) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x338) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x358) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x378) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x398) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3B8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3D8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x3F8) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x418) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_L_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x438) /* IOB RX address transition unit target address low 32bit.the address is align to 4Byte. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x5C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x7C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x9C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xDC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xFC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x13C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x17C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x19C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1DC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1FC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x21C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x25C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x27C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x29C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2BC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2DC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2FC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x31C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x33C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x35C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x37C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x39C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3BC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3DC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3FC) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x41C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RXATU_TAR_ADDR_H_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x43C) /* IOB RX address transition unit target address high 32bit. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CNT_CLR_CE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA00) /* counter type control register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA40) /* Counter of RX received NP */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA80) /* Counter of RX received NP */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC0) /* Counter of RX received NP */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA44) /* Counter of RX Received P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA84) /* Counter of RX Received P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC4) /* Counter of RX Received P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA48) /* Counter of RX Received CPL */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA88) /* Counter of RX Received CPL */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC8) /* Counter of RX Received CPL */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_MSIX_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4C) /* Counter of RX MSI/MSI-X interrupt */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_MSIX_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8C) /* Counter of RX MSI/MSI-X interrupt */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_MSIX_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xACC) /* Counter of RX MSI/MSI-X interrupt */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_P2P_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA50) /* Counter of RX Received NP for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_P2P_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA90) /* Counter of RX Received NP for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_P2P_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD0) /* Counter of RX Received NP for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_P2P_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA54) /* Counter of RX Received P for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_P2P_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA94) /* Counter of RX Received P for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_P2P_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD4) /* Counter of RX Received P for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_P2P_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA58) /* Counter of RX Received CPL for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_P2P_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA98) /* Counter of RX Received CPL for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_CPL_P2P_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAD8) /* Counter of RX Received CPL for P2P */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_ODR_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA60) /* Counter of RX Received NP to ODR channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_ODR_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA0) /* Counter of RX Received NP to ODR channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_ODR_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE0) /* Counter of RX Received NP to ODR channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_ODR_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA64) /* Counter of RX Received P to ODR channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_ODR_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA4) /* Counter of RX Received P to ODR channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_ODR_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE4) /* Counter of RX Received P to ODR channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_HAQ_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA68) /* Counter of HAQ operation */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_HAQ_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAA8) /* Counter of HAQ operation */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_HAQ_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAE8) /* Counter of HAQ operation */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_AER_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA70) /* Counter of RX Error to AER */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_AER_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB0) /* Counter of RX Error to AER */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_NP_AER_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF0) /* Counter of RX Error to AER */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_AER_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA74) /* Counter of RX Error to AER */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_AER_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAB4) /* Counter of RX Error to AER */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_TLP_CNT_P_AER_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAF4) /* Counter of RX Error to AER */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PRE_ERR_STS_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB80) /* Error status of IOB_RX preprocess */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PRE_ERR_STS_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB84) /* Error status of IOB_RX preprocess */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_PRE_ERR_STS_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB88) /* Error status of IOB_RX preprocess */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_PKT_NUM_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB90) /* Current pkt_num of RX_NP Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_PKT_NUM_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBA0) /* Current pkt_num of RX_NP Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_PKT_NUM_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBB0) /* Current pkt_num of RX_NP Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_PKT_NUM_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB94) /* Current pkt_num of RX_P Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_PKT_NUM_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBA4) /* Current pkt_num of RX_P Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_PKT_NUM_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBB4) /* Current pkt_num of RX_P Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_PKT_NUM_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB98) /* Current pkt_num of RX_CPL Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_PKT_NUM_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBA8) /* Current pkt_num of RX_CPL Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_PKT_NUM_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBB8) /* Current pkt_num of RX_CPL Request */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_INV_LKDN_CLR_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10B0) /* APAT ATS invalidate clear status when linkdown occurs */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_SYNC_WAIT_RLS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x10B4) /* APAT entry number waiting to be release when the cmd_sync request received */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IDLE_SET_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10BC) /* APAT IDLE status force set configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RD_IDX_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C0) /* APAT request entry index for read */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RD_DONE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C4) /* APAT request entry read finish */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10C8) /* APAT request entry read data [31:0] */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10CC) /* APAT request entry read data [63:32] */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10D0) /* APAT request entry read data [95:64] */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQ_ENTRY_RDATA3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10D4) /* APAT request entry read data [127:96] */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_TRANSLATION_IDLE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10D8) /* APAT ATS translation idle indication */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_PRI_IDLE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10DC) /* APAT ATS PRI service idle indication */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_CE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E0) /* APAT interrupt read only status for correctable error */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_NFE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E4) /* APAT interrupt read only status for non-fatal error */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_FE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10E8) /* APAT interrupt read only status for fatal error */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_SEVERITY_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10EC) /* APAT interrupt severity configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_SET_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F0) /* APAT interrupt set configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_MASK_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F4) /* APAT interrupt mask configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_STATUS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10F8) /* APAT interrupt status */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_INT_RO_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10FC) /* APAT interrupt read only status */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TRANSLATION_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1100) /* Control some behaviours of the inbound request translatioin */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TRANSLATION_RETRY_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1104) /* Control the TLB lookup request retry behaviour */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_SYNC_TIMEOUT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1108) /* SYNC response time out threshold */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_LKUP_STATS_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1110) /* Config parameters that are used by performance profiling */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_LKUP_REQ_PCT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1114) /* APAT lookup request DFX */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_LKUP_REQ_LENGTH_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1118) /* APAT lookup request statistics */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_NP_LKUP_REQ_LENGTH_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x111C) /* APAT NP lookup request length */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_NP_LKUP_LATENCY_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1120) /* APAT NP lookup latency */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_P_LKUP_LATENCY_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1124) /* APAT P lookup latency */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_HINT_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1140) /* Hint generated config */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_FIFO_DFX_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1144) /* TLB predictor FIFO DFx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1148) /* 16KB/64KB/2MB page size cache hit and miss ratio */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_PAGE_SIZE_CACHE_PERFORMANCE_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x114C) /* 16KB/64KB/2MB page size cache evict and not_replace ratio */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1150) /* LOCK hint cache hit and miss ratio */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_LOCK_CACHE_PERFORMANCE_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1154) /* LOCK hint cache evict and not_replace ratio */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_TLB_PREDICTOR_RAM_PARITY_DFX_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1158) /* RAM parity check DFX */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNXT_RAM_ECC_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x115C) /* RAM ECC inject control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNXT_RAM_ECC_STS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1160) /* RAM ECC status */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1164) /* first response fault from SMMU recorder #0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1168) /* first response fault from SMMU recorder #1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x116C) /* first response fault from SMMU recorder #2 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_FST_RSP_FAULT_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1170) /* first response fault from SMMU recorder #3 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_INVALID_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1174) /* counter of TLB invalidate and configure invalidate */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CMD_SYNC_STS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1178) /* cmd_sync counter and timeout indication */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_SYNC_MAX_TIME_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x117C) /* cmd_sync max time interval between request and response */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1180) /* To set parameters used by ATS module */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_TIMEOUT_L_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1184) /* ATC Invalidation timeout value config */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_TIMEOUT_H_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1188) /* ATC Invalidation timeout value config */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_ATS_PRIQ_IRPT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x118C) /* ATS PRI queue interrupt aggregation configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1190) /* APAT ATS PASID config #0 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1194) /* APAT ATS PASID config #1 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1198) /* APAT ATS PASID config #2 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x119C) /* APAT ATS PASID config #3 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A0) /* priv/exec bit config #0 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A4) /* priv/exec bit config #1 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11A8) /* priv/exec bit config #2 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_XILINX_HOOK_PASID_CFG_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11AC) /* priv/exec bit config #3 for Xilinx Hook Test */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQID_PASID_PRI_EXC_CFG_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x11B0) /* PASID/PRI/EXC configure according to the request ID matched or not */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_REQID_PASID_PRI_EXC_RD_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + \ + 0x11B4) /* PASID/PRI/EXC read from the buffer according to the request ID matched or not */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_LKUP_REQ_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C0) /* TLB lookup request counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_RETRIED_REQUEST_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C4) /* TLB lookup retry request counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_RSP_SUCCESS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11C8) /* TLB response success counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_RSP_FAULT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11CC) /* TLB response fault counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_SCH_NOREISSUE_REQUEST_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11D0) /* No reissue request schedule counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_SCH_REISSUE_REQUEST_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11D4) /* Reissue request schedule counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_LKUP_AGING_REQ_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11D8) /* TLB lookup prediction aging request counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_CNT_TLB_AGING_REQ_RETRIED_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11DC) /* TLB lookup prediction aging request retry counter */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_TRS_STS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11E0) /* ATS translate status dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_INV_STS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11E4) /* ATS invalidate status dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_ATS_PRI_STS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11E8) /* ATS PRI status dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_ATS_TRS_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11EC) /* ATS translate request and completion counter dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_ATS_INV_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11F0) /* ATS invalidate request and completion counter dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_ATS_PRI_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11F4) /* ATS PRI request and response counter dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_SMMU_INV_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11F8) /* SMMU invalidate request and completion counter dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_DFX_CNT_SMMU_PRI_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x11FC) /* SMMU PRI request and response counter dfx */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_GLB_CTRL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1200) /* Global control the trigger behaviour */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1210) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1220) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1230) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1240) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1250) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1260) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1270) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1280) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1290) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_L_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12A0) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1214) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1224) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1234) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1244) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1254) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1264) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1274) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1284) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1294) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_H_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12A4) /* The inbound traffic trigger sequence0 pattern high part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1218) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1228) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1238) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1248) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1258) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1268) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1278) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1288) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1298) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_PASID_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12A8) /* APAT trig TLP configure */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12B0) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12B4) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12B8) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12BC) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C0) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C4) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12C8) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12CC) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12D0) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_SEQ_CTRL_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12D4) /* The inbound traffic trigger sequence0 pattern low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12E0) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12F0) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1300) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1310) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1320) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1330) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1340) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1350) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1360) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_L_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1370) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12E4) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12F4) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1304) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1314) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1324) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1334) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1344) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1354) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1364) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_H_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1374) /* The inbound traffic trigger result low part */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12E8) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x12F8) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1308) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1318) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1328) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1338) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1348) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1358) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1368) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_APAT_IB_TRIG_RSLT_PASID_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1378) /* APAT trig result prefix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1500) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1510) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1520) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1530) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1540) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1550) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1560) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1570) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1580) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1590) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A0) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B0) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C0) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D0) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E0) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_CTRL_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F0) /* MSI/MSIX control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1504) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1514) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1524) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1534) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1544) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1554) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1564) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1574) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1584) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1594) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A4) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B4) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C4) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D4) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E4) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_HIGH_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F4) /* MSI/MSIX address high 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1508) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1518) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1528) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1538) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1548) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1558) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1568) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1578) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1588) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1598) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15A8) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15B8) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15C8) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15D8) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15E8) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_AM_MSI_MSIX_ADDR_LOW_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x15F8) /* MSI/MSIX address low 32bits */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_SMMU_BYPASS_PORT_EN_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1800) /* smmu bypass enable for each port configuration register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_ATOP_ENDIAN_FORMAT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1804) /* Endian Format Control of inbound atomic operation */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_RX_FILTER_MODE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1808) /* IB Filter mode control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_SMMU_BYPASS_MEMATTR_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x180C) /* SNP/MEM_ATTR configuration for SMMU BYPASS */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_SDI_REG_REMAP_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1810) /* SDI NVME/DMA config register address remap */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_POISON_PR_FORWARD_EN_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1814) /* Poison posted request forward control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_BAR_DISP_SEL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1818) /* Forward config based on BAR_NUM */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_PF_FUNC_SEL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x181C) /* PF Function select */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_ECO_REG_0_REG (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1820) /* ECO REG 0 \ + */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_IB_ECO_REG_1_REG (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1824) /* ECO REG 1 \ + */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_CTRL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1830) /* Global control for SDI_THROUGH */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_ADDR_FILTER_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1834) /* Address filter control for SDI_THROUGH */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_EN_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1840) /* PF Remap Enable for SDI_THROUGH */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_REMAP_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1844) /* PF Remap control for SDI_THROUGH */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_VF_START_FUN_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1848) /* Start function number configuration of PF for SDI_THROUGH */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_SDI_TH_PF_VF_NUM_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x184C) /* Number of VF for each PF */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1880) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1890) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18A0) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18B0) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C0) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18D0) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E0) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_EN_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18F0) /* Enable control for address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1884) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1894) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18A4) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18B4) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C4) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18D4) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E4) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ATTR_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18F4) /* Memory attribute control of address window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1888) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1898) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18A8) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18B8) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18C8) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18D8) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18E8) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_ADDR_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18F8) /* Address window control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x188C) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x189C) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18AC) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18BC) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18CC) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18DC) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18EC) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_CFG_MEMATTR_WIN_MASK_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18FC) /* Address mask control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1940) /* IOB RX NPR delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1944) /* IOB RX NPR delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_NP_DELAY_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1948) /* IOB RX NPR delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1950) /* IOB RX PR delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1954) /* IOB RX PR delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_P_DELAY_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1958) /* IOB RX PR delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1960) /* IOB RX CPL delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1964) /* IOB RX CPL delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IOB_RX_CPL_DELAY_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1968) /* IOB RX CPL delay control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A00) /* Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A80) /* Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B00) /* Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_0_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B80) /* Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A04) /* Space Size for Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A84) /* Space Size for Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B04) /* Space Size for Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_0_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B84) /* Space Size for Base address 0 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A08) /* Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A88) /* Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B08) /* Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_1_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B88) /* Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A0C) /* Space Size for Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A8C) /* Space Size for Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B0C) /* Space Size for Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_1_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B8C) /* Space Size for Base address 1 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A10) /* Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A90) /* Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B10) /* Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_2_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B90) /* Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A14) /* Space Size for Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A94) /* Space Size for Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B14) /* Space Size for Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_2_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B94) /* Space Size for Base address 2 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A18) /* Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A98) /* Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B18) /* Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_BASE_ADDR_3_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B98) /* Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A1C) /* Space Size for Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A9C) /* Space Size for Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B1C) /* Space Size for Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_SPACE_SIZE_3_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B9C) /* Space Size for Base address 3 of the P2P Memory space */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A30) /* For the inbound completion and message, uses the host bridge bus \ + range to determine the target Peer2Peer host bridge */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB0) /* For the inbound completion and message, uses the host bridge bus \ + range to determine the target Peer2Peer host bridge */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B30) /* For the inbound completion and message, uses the host bridge bus \ + range to determine the target Peer2Peer host bridge */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_BR_DST_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BB0) /* For the inbound completion and message, uses the host bridge bus \ + range to determine the target Peer2Peer host bridge */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A34) /* P2P Destiantion id route address[47:16] configuration */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB4) /* P2P Destiantion id route address[47:16] configuration */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B34) /* P2P Destiantion id route address[47:16] configuration */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_DEST_ADDR_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BB4) /* P2P Destiantion id route address[47:16] configuration */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A38) /* P2P Route control register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AB8) /* P2P Route control register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B38) /* P2P Route control register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ROUTE_CONTROL_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BB8) /* P2P Route control register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A3C) /* P2P Memory Attribute Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1ABC) /* P2P Memory Attribute Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B3C) /* P2P Memory Attribute Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_ATTR_CTRL_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BBC) /* P2P Memory Attribute Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1A40) /* P2P credit Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1AC0) /* P2P credit Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1B40) /* P2P credit Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_P2P_CREDIT_CTRL_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1BC0) /* P2P credit Control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_GLOBAL_CTRL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E00) /* Global control of HAQ */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_01_ATTR_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E04) /* Attribute of HAQ Message Channel 0/1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_23_ATTR_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E08) /* Attribute of HAQ Message Channel 2/3 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_0_ADDR_L_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E10) /* Low address for message channel 0 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_0_ADDR_H_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E14) /* High address for message channel 0 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_1_ADDR_L_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E18) /* Low address for message channel 1 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_1_ADDR_H_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E1C) /* High address for message channel 1 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_2_ADDR_L_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E20) /* Low address for message channel 2 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_2_ADDR_H_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E24) /* High address for message channel 2 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_3_ADDR_L_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E28) /* Low address for message channel 3 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_MSG_CH_3_ADDR_H_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E2C) /* High address for message channel 3 to POE */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_CFG_WIN_SEL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E30) /* Config window select control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E40) /* Queue window Contorl register 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E44) /* Queue window Contorl register 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E48) /* Queue window Contorl register 2 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_BASE_L_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E50) /* Base address of Queue window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_HAQ_WIN_BASE_H_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1E54) /* Base address of Queue window */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_RD_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F00) /* tph stash table read */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_WR_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F04) /* tph stash table write */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_STIDX_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F08) /* stash table r/w stdix */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_WDATA_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F0C) /* stash tabel write data */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_STASH_TBL_RDATA_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F10) /* stash table read data */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_BYPASS_PORT_EN_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F14) /* TPH bypass enable for each port configuration register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F20) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F24) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F28) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F2C) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F30) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F34) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F38) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F3C) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F40) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_TPH_REPLACE_CTRL_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1F44) /* tph replace control for each request port */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_WEIGHT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2300) /* AXIM_ARB arbitration weight. */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_RATE_CTRL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2304) /* AXIM_ARB request rate control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_RD_OST_NUM_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2308) /* AXIM_ARB read outstanding number threshold */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_TARGET_LAT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x230C) /* AXIM_ARB target latency */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_LAT_SEL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2310) /* AXIM_ARB latency dfx control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_RDY_CTRL_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2314) /* AXIM_ARB latency dfx control */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_STATE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2340) /* State of AXIM_ARB */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_CNT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2360) /* counter of AXIM_M0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_CNT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2364) /* counter of AXIM_M0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_CNT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2368) /* counter of AXIM_M1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_CNT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x236C) /* counter of AXIM_M1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AR_LAT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2380) /* AXI AR latency 0 of Master 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AR_LAT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2384) /* AXI AR latency 1 of Master 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AW_LAT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2388) /* AXI AW latency 0 of Master 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M0_AW_LAT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x238C) /* AXI AW latency 1 of Master 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AR_LAT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2390) /* AXI AR latency 0 of Master 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AR_LAT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2394) /* AXI AR latency 1 of Master 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AW_LAT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2398) /* AXI AW latency 0 of Master 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_M1_AW_LAT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x239C) /* AXI AW latency 1 of Master 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_CURR_SEQ_NUM_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23A0) /* Current sequence number of HAQ message channel */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_TRANS_CNT_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23A4) /* Counter 0 of HAQ packet */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23A8) /* Sequence number state of haq channel 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23AC) /* Sequence number state of haq channel 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_TRANS_CNT_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23B0) /* Counter 1 of HAQ packet */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23B4) /* Sequence number state of haq channel 2 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_HAQ_SEQ_NUM_STS_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23B8) /* Sequence number state of haq channel 3 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C0) /* P2P Sequence number Status for hostbridge 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C4) /* P2P Sequence number Status for hostbridge 1 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23C8) /* P2P Sequence number Status for hostbridge 2 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_SEQ_STS3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23CC) /* P2P Sequence number Status for hostbridge 3 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23D0) /* P2P dfx status for hostbridge 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23D4) /* P2P dfx status for hostbridge 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23D8) /* P2P dfx status for hostbridge 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_AXIM_ARB_P2P_STS_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x23DC) /* P2P dfx status for hostbridge 0 */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_0_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_1_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_2_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_3_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_4_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x10) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_5_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x14) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_6_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x18) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_7_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x1C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_8_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x20) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_9_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x24) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_10_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x28) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_11_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x2C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_12_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x30) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_13_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x34) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_14_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x38) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_15_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x3C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_16_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x40) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_17_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x44) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_18_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x48) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_19_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x4C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_20_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x50) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_21_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x54) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_22_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x58) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_23_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x5C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_24_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x60) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_25_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x64) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_26_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x68) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_27_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x6C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_28_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x70) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_29_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x74) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_30_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x78) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_31_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x7C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_32_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x80) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_33_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x84) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_34_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x88) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_35_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x8C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_36_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x90) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_37_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x94) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_38_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x98) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_39_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x9C) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_40_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_41_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_42_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xA8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_43_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xAC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_44_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_45_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_46_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xB8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_47_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xBC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_48_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_49_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_50_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xC8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_51_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xCC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_52_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_53_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_54_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xD8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_55_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xDC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_56_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_57_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_58_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xE8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_59_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xEC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_60_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF0) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_61_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF4) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_62_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xF8) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_TABLE_63_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0xFC) /* configure the stash table */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_TPH_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x200) /* configure the tph mode register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_TPH_BANDWIDTH_EXCEED_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x203) /* configure tph bandwidth filter register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_PH_MAP_TO_TARGET_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x204) /* configure ph mapping register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_STASH_DATA_TYPE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x205) /* configure ph mapping register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_DATA_TYPE_DESCRIPTOR_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x206) /* configure ph mapping register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_CFG_DATA_TYPE_PACKET_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x207) /* configure ph mapping register */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_WR_ADJUST_BW_LIMIT_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x208) /* write after latency adjust bandwidth limit result */ +#define CSR_HIPCIEC_AP_IOB_RX_COM_REG_IB_STAT_TLP_BW_AVERAGE_REG \ + (CSR_HIPCIEC_AP_IOB_RX_COM_REG_BASE + 0x209) /* average tlp bandwidth result */ + +/* HIPCIEC_AP_MG_REG Base address of Module's Register */ +#define CSR_HIPCIEC_AP_MG_REG_BASE (0x8000) + +/* **************************************************************************** */ +/* HIPCIEC_AP_MG_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC_AP_MG_REG_PCIE_ERR_MAPPING_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + \ + 0x0) /* CE(ERR_COR)/UNF(ERR_NONFATAL)/UF(ERR_FATAL)/NI(NORMAL_INT) mapping to ERI/FHI/SPI0/SPI1 */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_ENA_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x8) /* CE(ERR_COR) interrupt enable of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_UNF_ENA_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10) /* UNF(ERR_NONFATAL) interrupt enable of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_UF_ENA_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x18) /* UF(ERR_FATAL) interrupt enable of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_STATUS_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x20) /* CE(ERR_COR) interrupt status of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_UNF_STATUS_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x28) /* UNF(ERR_NONFATAL) interrupt status of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_UF_STATUS_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x30) /* UF(ERR_FATAL) interrupt status of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_NI_ENA_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x38) /* NI(NORMAL_INT) interrupt enable of each source */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_NI_STATUS_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x3C) /* NI(NORAML_INT) interrupt status of each source */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x40) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x48) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x50) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_3_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x58) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_4_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x60) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_5_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x68) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_6_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x70) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_7_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x78) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_8_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x80) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_9_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x88) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_10_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x90) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_11_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x98) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_12_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xA0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_13_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xA8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_14_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xB0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_15_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xB8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_16_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xC0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_17_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xC8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_18_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xD0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_19_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xD8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_20_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xE0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_21_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xE8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_22_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xF0) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_23_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0xF8) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_24_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x100) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_25_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x108) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_PCIE_CE_CNT_CFG_26_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x110) /* 16-bit CE(ERR_COR) counter register for the source ras_idx */ +#define CSR_HIPCIEC_AP_MG_REG_CFG_INTX_CLR_EN_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x400) /* Config the INTx clear of each Port. */ +#define CSR_HIPCIEC_AP_MG_REG_CFG_INTX_DEASSERT_MODE_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x404) /* Config the INTx deassert mode of each Port. */ +#define CSR_HIPCIEC_AP_MG_REG_CFG_ODR_DISP_CTRL_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x408) /* IOB RX dispatch dfx select control register */ +#define CSR_HIPCIEC_AP_MG_REG_CFG_PORT_ERR_CLR_EN_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x40C) /* the clear enable of the ni/ce/ufe/fe counter of each source. */ +#define CSR_HIPCIEC_AP_MG_REG_CFG_ODR_DISP_MISC_CTRL_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x410) /* IOB_RX_DISP bdoor register. */ +#define CSR_HIPCIEC_AP_MG_REG_DFX_PORT_INTX_PENDING_CNT_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x500) /* INTx Pending Conute DFX register */ +#define CSR_HIPCIEC_AP_MG_REG_DFX_CORE_INTX_CNT_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x504) /* INTx Conute DFX register \ + */ +#define CSR_HIPCIEC_AP_MG_REG_DFX_PORT_ERR_CNT0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x510) /* NI and CE conuter DFX register */ +#define CSR_HIPCIEC_AP_MG_REG_DFX_PORT_ERR_CNT1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x514) /* NFE and FE counter DFX register */ +#define CSR_HIPCIEC_AP_MG_REG_DFX_ODR_P_CNT_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x520) /* Odr channel post tlp counter register */ +#define CSR_HIPCIEC_AP_MG_REG_DFX_ODR_NP_CNT_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x524) /* Odr channel non post tlp counter register */ +#define CSR_HIPCIEC_AP_MG_REG_AP_RAM_TIMING_CFG_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x800) /* sram timing config for all of the SRAM in AP module */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TOP_CTRL_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1000) /* MCTP Top Control Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_CTRL_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1004) /* MCTP Control Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_CTRL_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1204) /* MCTP Control Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_CTRL_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1404) /* MCTP Control Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV0_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1008) /* MCTP Reserved Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV0_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1208) /* MCTP Reserved Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV0_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1408) /* MCTP Reserved Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV1_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x100C) /* MCTP Reserved Register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV1_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x120C) /* MCTP Reserved Register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV1_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x140C) /* MCTP Reserved Register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV2_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1010) /* MCTP Reserved Register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV2_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1210) /* MCTP Reserved Register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RSV2_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1410) /* MCTP Reserved Register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1014) /* Interrupt mapping 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1214) /* Interrupt mapping 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INT_MAPPING_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1414) /* Interrupt mapping 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1018) /* Interrupt Status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1218) /* Interrupt Status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_STAT_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1418) /* Interrupt Status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SET_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x101C) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SET_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x121C) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SET_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x141C) /* Interrupt Set-Enable Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1020) /* Interrupt Mask Register \ + */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1220) /* Interrupt Mask Register \ + */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_MASK_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1420) /* Interrupt Mask Register \ + */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SOURCE_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1024) /* Interrupt Source Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SOURCE_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1224) /* Interrupt Source Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_INTRPT_SOURCE_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1424) /* Interrupt Source Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1028) /* RX interrupt control register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1228) /* RX interrupt control register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1428) /* RX interrupt control register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1030) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1230) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PEMPTY_THRESHOLD_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1430) /* RX Queue Pempty Threshold Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1034) /* RX interrupt control register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1234) /* RX interrupt control register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1434) /* RX interrupt control register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1038) /* RX interrupt control register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1238) /* RX interrupt control register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_2_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1438) /* RX interrupt control register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_3_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x103C) /* RX interrupt control register 3 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_3_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x123C) /* RX interrupt control register 3 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_INT_CTRL_3_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x143C) /* RX interrupt control register 3 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1040) /* RX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1240) /* RX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1440) /* RX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1044) /* RX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1244) /* RX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_BASE_ADDR_LOW_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1444) /* RX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1048) /* RX Queue Depth. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1248) /* RX Queue Depth. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_DEPTH_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1448) /* RX Queue Depth. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1050) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1250) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_HEAD_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1450) /* RX Queue Head Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1054) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1254) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_QUEUE_TAIL_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1454) /* RX Queue Tail Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1060) /* TX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1260) /* TX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1460) /* TX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1064) /* TX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1264) /* TX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BASE_ADDR_LOW_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1464) /* TX Queue base address register. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1068) /* TX Queue Depth. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1268) /* TX Queue Depth. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_DEPTH_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1468) /* TX Queue Depth. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1070) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1270) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_HEAD_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1470) /* TX Queue Head Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1074) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1274) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_QUEUE_TAIL_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1474) /* TX Queue Tail Pointer. */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1080) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1280) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_HIGH_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1480) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1084) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1284) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_AXI_ERR_ADDR_LOW_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1484) /* RX AXI Write Error Address */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10A0) /* TLP Header Check Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12A0) /* TLP Header Check Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14A0) /* TLP Header Check Register 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10A4) /* TLP Header Check Register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12A4) /* TLP Header Check Register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14A4) /* TLP Header Check Register 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10A8) /* TLP Header Check Register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12A8) /* TLP Header Check Register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_CHECK2_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14A8) /* TLP Header Check Register 2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10B0) /* Counter for error tx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12B0) /* Counter for error tx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14B0) /* Counter for error tx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10B4) /* Counter for error tx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12B4) /* Counter for error tx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ERR_CNT_1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14B4) /* Counter for error tx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10B8) /* Counter for error rx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12B8) /* Counter for error rx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14B8) /* Counter for error rx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10BC) /* Counter for error rx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12BC) /* Counter for error rx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ERR_CNT_1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14BC) /* Counter for error rx message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10C0) /* FIFO status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12C0) /* FIFO status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DATA_FIFO_STATUS_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14C0) /* FIFO status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10C4) /* Threshold to drop RX message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12C4) /* Threshold to drop RX message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_TH_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14C4) /* Threshold to drop RX message */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10C8) /* RX dropped message counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12C8) /* RX dropped message counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_CNT_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14C8) /* RX dropped message counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10CC) /* MCTP TX Routing Error Counter 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12CC) /* MCTP TX Routing Error Counter 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14CC) /* MCTP TX Routing Error Counter 0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10D0) /* MCTP TX Routing Error Counter 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12D0) /* MCTP TX Routing Error Counter 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ROUTING_ERR_CNT_1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14D0) /* MCTP TX Routing Error Counter 1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10D4) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12D4) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14D4) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10D8) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12D8) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14D8) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10DC) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12DC) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_PKT_NUM_2_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14DC) /* MCTP TX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10E0) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12E0) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14E0) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10E4) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12E4) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14E4) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10E8) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12E8) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_PKT_NUM_2_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14E8) /* MCTP RX Packet Statistic */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10EC) /* FSM Status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12EC) /* FSM Status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DEBUG_FSM_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14EC) /* FSM Status Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10F0) /* MCTP Header Match Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12F0) /* MCTP Header Match Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_HDR_MATCH_STAT_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14F0) /* MCTP Header Match Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DFX_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10F4) /* MCTP DFX Control Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DFX_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12F4) /* MCTP DFX Control Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_DFX_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14F4) /* MCTP DFX Control Register */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10F8) /* MCTP ECC Error Injection */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12F8) /* MCTP ECC Error Injection */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_ECC_ERR_INJECTION_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14F8) /* MCTP ECC Error Injection */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x10FC) /* MCTP RX 1-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x12FC) /* MCTP RX 1-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_1BIT_ERR_CNT_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x14FC) /* MCTP RX 1-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1110) /* MCTP RX 2-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1310) /* MCTP RX 2-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_ECC_2BIT_ERR_CNT_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1510) /* MCTP RX 2-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1114) /* MCTP TX 1-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1314) /* MCTP TX 1-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_1BIT_ERR_CNT_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1514) /* MCTP TX 1-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1118) /* MCTP TX 2-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1318) /* MCTP TX 2-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_ECC_2BIT_ERR_CNT_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1518) /* MCTP TX 2-bit ECC Error Counter */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x111C) /* MCTP Dropped Header DW0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x131C) /* MCTP Dropped Header DW0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW0_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x151C) /* MCTP Dropped Header DW0 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1120) /* MCTP Dropped Header DW1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1320) /* MCTP Dropped Header DW1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW1_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1520) /* MCTP Dropped Header DW1 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1124) /* MCTP Dropped Header DW2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1324) /* MCTP Dropped Header DW2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW2_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1524) /* MCTP Dropped Header DW2 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1128) /* MCTP Dropped Header DW3 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1328) /* MCTP Dropped Header DW3 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DROP_HDR_DW3_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1528) /* MCTP Dropped Header DW3 */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_AXUSER_0_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x112C) /* MCTP AXUSER */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_AXUSER_1_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x132C) /* MCTP AXUSER */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_AXUSER_2_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x152C) /* MCTP AXUSER */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1130) /* MCTP RX memory write request Stream ID */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1330) /* MCTP RX memory write request Stream ID */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_STRMID_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1530) /* MCTP RX memory write request Stream ID */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_0_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1134) /* MCTP TX memory read request Stream ID */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_1_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1334) /* MCTP TX memory read request Stream ID */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_STRMID_2_REG \ + (CSR_HIPCIEC_AP_MG_REG_BASE + 0x1534) /* MCTP TX memory read request Stream ID */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_TX_BROADCAST_DFX_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x2018) /* MCTP_RC BC */ +#define CSR_HIPCIEC_AP_MG_REG_MCTP_RX_DISPATCH_DFX_REG (CSR_HIPCIEC_AP_MG_REG_BASE + 0x201C) /* MCTP RX Dispatch */ + +/* HIPCIEC_AP_INT_REG Base address of Module's Register */ +#define CSR_HIPCIEC_AP_INT_REG_BASE (0x10000) + +/* **************************************************************************** */ +/* HIPCIEC_AP_INT_REG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HIPCIEC_AP_INT_REG_MSIX_VECTOR_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x0) /* MSIX Vector Number */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_COAL_CTRL_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0x4) /* MSIX Vector Coal Control Register */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_COAL_EVENT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x8) /* MSIX Coal Event Register */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_COAL_TIME_UNIT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC) /* MSIX Coal Time Unit */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_MSG_ADDR_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x10) /* MSIX Message Address */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_MSG_UP_ADDR_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x14) /* MSIX Message up Address */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_MSG_DATA_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x18) /* MSIX Message Data */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_VECTOR_CTRL_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x1C) /* MSIX Vector Control */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_PENDING_BIT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x20) /* MSIX Pending Bits */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_SRAM_INIT_STATUS_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0x24) /* MSIX sram initial status */ +#define CSR_HIPCIEC_AP_INT_REG_SDI_ECO_REGISTER_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x28) /* ECO register */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_MISC_CTRL_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0x2C) /* Set Relaxed Ordering fields in MSI/MSIX message */ +#define CSR_HIPCIEC_AP_INT_REG_RAS_INT_LEVEL_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x30) /* RAS interrupt level */ +#define CSR_HIPCIEC_AP_INT_REG_HOST_ACCESS_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x50) /* Host access tlp status \ + */ +#define CSR_HIPCIEC_AP_INT_REG_TLP_CNT_CFG_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x54) /* Tlp count configure */ +#define CSR_HIPCIEC_AP_INT_REG_HOST_TLP_CNT_0_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x58) /* Host TLP Count0 */ +#define CSR_HIPCIEC_AP_INT_REG_HOST_TLP_CNT_1_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x5C) /* Host TLP Count1 */ +#define CSR_HIPCIEC_AP_INT_REG_DMA_INPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x60) /* dma input status */ +#define CSR_HIPCIEC_AP_INT_REG_DMA_OUTPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x64) /* dma output status */ +#define CSR_HIPCIEC_AP_INT_REG_NVME_INPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x68) /* nvme input status */ +#define CSR_HIPCIEC_AP_INT_REG_NVME_OUTPUT_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x6C) /* nvme output status */ +#define CSR_HIPCIEC_AP_INT_REG_FSM_STATUS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x70) /* fsm status */ +#define CSR_HIPCIEC_AP_INT_REG_LINK_DOWN_IDLE_STATUS_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0x74) /* Link down idle status */ +#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_INT_SRC_STS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x78) /* ECC error int src */ +#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_MASK_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x7C) /* ECC Error Mask */ +#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_INT_STS_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x80) /* ECC error int sts */ +#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_INJECT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x84) /* ECC Error inject */ +#define CSR_HIPCIEC_AP_INT_REG_ECC_ERR_CNT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x88) /* ECC Error counter */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_TBL_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0x8C) /* msix tbl ECC error address */ +#define CSR_HIPCIEC_AP_INT_REG_COAL_TBL_ECC_ERR_ADDR_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0x90) /* coal tbl ECC error address */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_RO_CE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x94) /* msix ce ro register */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_RO_NFE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x98) /* msix nfe ro register */ +#define CSR_HIPCIEC_AP_INT_REG_MSIX_RO_FE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x9C) /* msix fe ro register */ +#define CSR_HIPCIEC_AP_INT_REG_SET_MSIX_INT_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xA0) /* set msix interrupt */ +#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_STS_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xA4) /* interrupt status of INT abnormal */ +#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_MASK_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xA8) /* interrupt mask of INT abnormal */ +#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_SET_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xAC) /* setting interrupt */ +#define CSR_HIPCIEC_AP_INT_REG_ABNORMAL_INT_RO_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xB0) /* interrupt indicater of INT abnormal */ +#define CSR_HIPCIEC_AP_INT_REG_DMA_ERR_FUNC_VEC_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xB4) /* DMA function or vector access error register */ +#define CSR_HIPCIEC_AP_INT_REG_NVME_ERR_FUNC_VEC_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xB8) /* NVME function or vector access error register */ +#define CSR_HIPCIEC_AP_INT_REG_INT_IDBO_CTRL_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xBC) /* Set ID-Based Ordering fields in MSI/MSIX message */ +#define CSR_HIPCIEC_AP_INT_REG_INT_NS_CTRL_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC0) /* Set No Snoop fields in MSI/MSIX message */ +#define CSR_HIPCIEC_AP_INT_REG_TL_REG_DFX_ADDR_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC4) /* TL_REG DFX address */ +#define CSR_HIPCIEC_AP_INT_REG_TL_REG_DFX_DATA_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xC8) /* TL_REG DFX data */ +#define CSR_HIPCIEC_AP_INT_REG_ERR_FUNC_VEC_CNT_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xCC) /* Record how much times of function error and vector error occurs. */ +#define CSR_HIPCIEC_AP_INT_REG_INT_CTRL_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0xD0) /* Ctrling signal of INTX/MSI/MSIX. \ + */ +#define CSR_HIPCIEC_AP_INT_REG_INT_TPH_CTRL0_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xE0) /* Set TH/ST/PH fields in MSI/MSIX message of PF0 and PF1 */ +#define CSR_HIPCIEC_AP_INT_REG_INT_TPH_CTRL1_REG \ + (CSR_HIPCIEC_AP_INT_REG_BASE + 0xE4) /* Set TH/ST/PH fields in MSI/MSIX message of PF2 and PF3 */ +#define CSR_HIPCIEC_AP_INT_REG_NET_ECAM_BUS_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x100) /* Network ECAM Bus number \ + */ +#define CSR_HIPCIEC_AP_INT_REG_NET_PF_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x104) /* Network PF Number */ +#define CSR_HIPCIEC_AP_INT_REG_NET_FIRST_VF_NUM_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x108) /* Network VF First Number \ + */ +#define CSR_HIPCIEC_AP_INT_REG_NET_VF_STRIDE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x10C) /* Network VF Stride */ +#define CSR_HIPCIEC_AP_INT_REG_NET_ECAM_BASE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x110) /* Network ECAM BASE */ +#define CSR_HIPCIEC_AP_INT_REG_ERR_RESPONSE_REG (CSR_HIPCIEC_AP_INT_REG_BASE + 0x114) /* Sync error response */ + +#endif // PCIE4_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/phosphor_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/phosphor_c_union_define.h new file mode 100644 index 000000000..3f1bba518 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/phosphor_c_union_define.h @@ -0,0 +1,2841 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : phosphor_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : V680 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/04/28 23:05:45 Create file +// ****************************************************************************** + +#ifndef PHOSPHOR_C_UNION_DEFINE_H +#define PHOSPHOR_C_UNION_DEFINE_H + +/* Define the union csr_com_cache_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 4; /* [3:0] */ + u32 l3_intlv_mode : 1; /* [4] */ + u32 rsv_1 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_cache_mode_u; + +/* Define the union csr_com_ddrintlv_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmc_intlv_addr_set_sel : 3; /* [2:0] */ + u32 dmc_intlv_addr_set_sel_xor : 1; /* [3] */ + u32 hha_intlv_addr_set_sel : 3; /* [6:4] */ + u32 hha_intlv_addr_set_sel_xor : 1; /* [7] */ + u32 die_intlv_addr_set_sel : 3; /* [10:8] */ + u32 die_intlv_addr_set_sel_xor : 1; /* [11] */ + u32 skt_intlv_addr_set_sel : 3; /* [14:12] */ + u32 skt_intlv_addr_set_sel_xor : 1; /* [15] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_ddrintlv_addr_u; + +/* Define the union csr_com_partid_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 partid_mode_nc : 2; /* [1:0] */ + u32 partid_mode_c : 2; /* [3:2] */ + u32 rsv_3 : 4; /* [7:4] */ + u32 pmg_qos_switch_en : 1; /* [8] */ + u32 rsv_4 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_partid_mode_u; + +/* Define the union csr_com_dec_l3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bypass_l3_wu : 1; /* [0] */ + u32 bypass_l3_skt : 1; /* [1] */ + u32 nca_enable : 1; /* [2] */ + u32 stash_hha_en : 1; /* [3] */ + u32 bypass_l3_ro : 1; /* [4] */ + u32 bypass_nonsnp : 1; /* [5] */ + u32 stash_local_l3_en : 1; /* [6] */ + u32 csp_en : 1; /* [7] */ + u32 inter_atomic_bypass_en : 1; /* [8] */ + u32 todef_pcie_dispatch_en : 1; /* [9] */ + u32 ro2hha_force_nca_en : 1; /* [10] */ + u32 ext_defslv_tgtid_cfg : 7; /* [17:11] */ + u32 reg_davinci_en : 1; /* [18] */ + u32 virtruvian_en : 1; /* [19] */ + u32 intra_atomic_bypass_en : 1; /* [20] */ + u32 rsv_5 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_dec_l3_u; + +/* Define the union csr_com_sramintlv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sram_intlv_en : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_sramintlv_u; + +/* Define the union csr_com_pg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg_intlv_en : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_pg_u; + +/* Define the union csr_com_ccix_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpa_tgtid_en : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_ccix_u; + +/* Define the union csr_com_daw_msd_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 daw_msd_reset_n : 1; /* [0] */ + u32 daw_msd_cfg_en : 1; /* [1] */ + u32 rsv_9 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw_msd_ctrl_u; + +/* Define the union csr_com_daw_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw_en_u; + +/* Define the union csr_com_vf_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_reset_n : 1; /* [0] */ + u32 vf_cfg_en : 1; /* [1] */ + u32 vf_func_en : 1; /* [2] */ + u32 rsv_10 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf_ctrl_u; + +/* Define the union csr_com_vf_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf_en_u; + +/* Define the union csr_com_vf_baseaddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 base_addr : 24; /* [23:0] */ + u32 rsv_11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf_baseaddr_u; + +/* Define the union csr_com_daw0_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_12 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw0_addr_u; + +/* Define the union csr_com_daw0_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_13 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_14 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_15 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_16 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw0_size_id_u; + +/* Define the union csr_com_daw1_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_17 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw1_addr_u; + +/* Define the union csr_com_daw1_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_18 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_19 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_20 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_21 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw1_size_id_u; + +/* Define the union csr_com_daw2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_22 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw2_addr_u; + +/* Define the union csr_com_daw2_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_23 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_24 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_25 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_26 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw2_size_id_u; + +/* Define the union csr_com_daw3_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_27 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw3_addr_u; + +/* Define the union csr_com_daw3_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_28 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_29 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_30 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_31 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw3_size_id_u; + +/* Define the union csr_com_daw4_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_32 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw4_addr_u; + +/* Define the union csr_com_daw4_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_33 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_34 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_35 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_36 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw4_size_id_u; + +/* Define the union csr_com_daw5_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_37 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw5_addr_u; + +/* Define the union csr_com_daw5_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_38 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_39 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_40 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_41 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw5_size_id_u; + +/* Define the union csr_com_daw6_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_42 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw6_addr_u; + +/* Define the union csr_com_daw6_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_43 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_44 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_45 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_46 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw6_size_id_u; + +/* Define the union csr_com_daw7_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_47 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw7_addr_u; + +/* Define the union csr_com_daw7_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_48 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_49 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_50 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_51 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw7_size_id_u; + +/* Define the union csr_com_daw8_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_52 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw8_addr_u; + +/* Define the union csr_com_daw8_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_53 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_54 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_55 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_56 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw8_size_id_u; + +/* Define the union csr_com_daw9_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_57 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw9_addr_u; + +/* Define the union csr_com_daw9_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_58 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_59 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_61 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw9_size_id_u; + +/* Define the union csr_com_daw10_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_62 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw10_addr_u; + +/* Define the union csr_com_daw10_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_63 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_64 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_65 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_66 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw10_size_id_u; + +/* Define the union csr_com_daw11_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_67 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw11_addr_u; + +/* Define the union csr_com_daw11_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_68 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_69 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_70 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_71 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw11_size_id_u; + +/* Define the union csr_com_daw12_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_72 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw12_addr_u; + +/* Define the union csr_com_daw12_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_73 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_74 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_75 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_76 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw12_size_id_u; + +/* Define the union csr_com_daw13_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_77 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw13_addr_u; + +/* Define the union csr_com_daw13_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_78 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_79 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_81 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw13_size_id_u; + +/* Define the union csr_com_daw14_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_82 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw14_addr_u; + +/* Define the union csr_com_daw14_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_83 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_84 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_85 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_86 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw14_size_id_u; + +/* Define the union csr_com_daw15_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_87 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw15_addr_u; + +/* Define the union csr_com_daw15_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_88 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_89 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_90 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_91 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw15_size_id_u; + +/* Define the union csr_com_daw16_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_92 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw16_addr_u; + +/* Define the union csr_com_daw16_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_93 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_94 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_95 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_96 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw16_size_id_u; + +/* Define the union csr_com_daw17_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_97 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw17_addr_u; + +/* Define the union csr_com_daw17_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_98 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_99 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_100 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_101 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw17_size_id_u; + +/* Define the union csr_com_daw18_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_102 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw18_addr_u; + +/* Define the union csr_com_daw18_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_103 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_104 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_105 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_106 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw18_size_id_u; + +/* Define the union csr_com_daw19_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_107 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw19_addr_u; + +/* Define the union csr_com_daw19_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_108 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_109 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_110 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_111 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw19_size_id_u; + +/* Define the union csr_com_daw20_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_112 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw20_addr_u; + +/* Define the union csr_com_daw20_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_113 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_114 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_115 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_116 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw20_size_id_u; + +/* Define the union csr_com_daw21_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_117 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw21_addr_u; + +/* Define the union csr_com_daw21_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_118 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_119 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_120 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_121 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw21_size_id_u; + +/* Define the union csr_com_daw22_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_122 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw22_addr_u; + +/* Define the union csr_com_daw22_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_123 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_124 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_125 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_126 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw22_size_id_u; + +/* Define the union csr_com_daw23_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_127 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw23_addr_u; + +/* Define the union csr_com_daw23_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_128 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_129 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_130 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_131 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw23_size_id_u; + +/* Define the union csr_com_daw24_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_132 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw24_addr_u; + +/* Define the union csr_com_daw24_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_133 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_134 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_135 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_136 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw24_size_id_u; + +/* Define the union csr_com_daw25_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_137 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw25_addr_u; + +/* Define the union csr_com_daw25_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_138 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_139 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_140 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_141 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw25_size_id_u; + +/* Define the union csr_com_daw26_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_142 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw26_addr_u; + +/* Define the union csr_com_daw26_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_143 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_144 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_145 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_146 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw26_size_id_u; + +/* Define the union csr_com_daw27_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_147 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw27_addr_u; + +/* Define the union csr_com_daw27_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_148 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_149 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_150 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_151 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw27_size_id_u; + +/* Define the union csr_com_daw28_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_152 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw28_addr_u; + +/* Define the union csr_com_daw28_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_153 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_154 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_155 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_156 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw28_size_id_u; + +/* Define the union csr_com_daw29_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_157 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw29_addr_u; + +/* Define the union csr_com_daw29_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_158 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_159 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_160 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_161 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw29_size_id_u; + +/* Define the union csr_com_daw30_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_162 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw30_addr_u; + +/* Define the union csr_com_daw30_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_163 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_164 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_165 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_166 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw30_size_id_u; + +/* Define the union csr_com_daw31_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_addr : 28; /* [27:0] */ + u32 rsv_167 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw31_addr_u; + +/* Define the union csr_com_daw31_size_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sysdaw_portid : 5; /* [4:0] */ + u32 rsv_168 : 3; /* [7:5] */ + u32 sysdaw_dieid : 2; /* [9:8] */ + u32 rsv_169 : 2; /* [11:10] */ + u32 sysdaw_sktid : 2; /* [13:12] */ + u32 rsv_170 : 2; /* [15:14] */ + u32 sysdaw_size : 5; /* [20:16] */ + u32 rsv_171 : 6; /* [26:21] */ + u32 sysdaw_cpa_four_chip : 1; /* [27] */ + u32 sysdaw_cpa_two_chip : 1; /* [28] */ + u32 sysdaw_four_chip : 1; /* [29] */ + u32 sysdaw_two_chip : 1; /* [30] */ + u32 hole_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_daw31_size_id_u; + +/* Define the union csr_com_vf00_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_172 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_173 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf00_id_u; + +/* Define the union csr_com_vf01_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_174 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_175 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf01_id_u; + +/* Define the union csr_com_vf02_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_176 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_177 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf02_id_u; + +/* Define the union csr_com_vf03_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_178 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_179 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf03_id_u; + +/* Define the union csr_com_vf04_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_180 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_181 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf04_id_u; + +/* Define the union csr_com_vf05_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_182 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_183 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf05_id_u; + +/* Define the union csr_com_vf06_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_184 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_185 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf06_id_u; + +/* Define the union csr_com_vf07_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_186 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_187 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf07_id_u; + +/* Define the union csr_com_vf08_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_188 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_189 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf08_id_u; + +/* Define the union csr_com_vf09_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_190 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_191 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf09_id_u; + +/* Define the union csr_com_vf10_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_192 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_193 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf10_id_u; + +/* Define the union csr_com_vf11_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_194 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_195 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf11_id_u; + +/* Define the union csr_com_vf12_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_196 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_197 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf12_id_u; + +/* Define the union csr_com_vf13_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_198 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_199 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf13_id_u; + +/* Define the union csr_com_vf14_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_200 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_201 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf14_id_u; + +/* Define the union csr_com_vf15_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_202 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_203 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf15_id_u; + +/* Define the union csr_com_vf16_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_204 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_205 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf16_id_u; + +/* Define the union csr_com_vf17_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_206 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_207 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf17_id_u; + +/* Define the union csr_com_vf18_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_208 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_209 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf18_id_u; + +/* Define the union csr_com_vf19_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_210 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_211 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf19_id_u; + +/* Define the union csr_com_vf20_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_212 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_213 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf20_id_u; + +/* Define the union csr_com_vf21_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_214 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_215 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf21_id_u; + +/* Define the union csr_com_vf22_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_216 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_217 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf22_id_u; + +/* Define the union csr_com_vf23_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_218 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_219 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf23_id_u; + +/* Define the union csr_com_vf24_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_220 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_221 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf24_id_u; + +/* Define the union csr_com_vf25_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_222 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_223 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf25_id_u; + +/* Define the union csr_com_vf26_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_224 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_225 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf26_id_u; + +/* Define the union csr_com_vf27_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_226 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_227 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf27_id_u; + +/* Define the union csr_com_vf28_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_228 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_229 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf28_id_u; + +/* Define the union csr_com_vf29_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_230 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_231 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf29_id_u; + +/* Define the union csr_com_vf30_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_232 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_233 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf30_id_u; + +/* Define the union csr_com_vf31_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_id : 5; /* [4:0] */ + u32 rsv_234 : 3; /* [7:5] */ + u32 die_id : 2; /* [9:8] */ + u32 rsv_235 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_vf31_id_u; + +/* Define the union csr_com_msd0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd0_ctrl_u; + +/* Define the union csr_com_msd1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd1_ctrl_u; + +/* Define the union csr_com_msd2_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd2_ctrl_u; + +/* Define the union csr_com_msd3_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd3_ctrl_u; + +/* Define the union csr_com_msd4_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd4_ctrl_u; + +/* Define the union csr_com_msd5_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd5_ctrl_u; + +/* Define the union csr_com_msd6_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd6_ctrl_u; + +/* Define the union csr_com_msd7_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ddr_intlv_baseaddr : 20; /* [19:0] */ + u32 ddr_intlv_size : 4; /* [23:20] */ + u32 ddr_intlv_ch : 3; /* [26:24] */ + u32 ddr_intlv_die : 1; /* [27] */ + u32 ddr_nonintlv_die_tgt : 1; /* [28] */ + u32 ddr_intlv_skt : 2; /* [30:29] */ + u32 msd_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd7_ctrl_u; + +/* Define the union csr_com_msd0_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd0_map_u; + +/* Define the union csr_com_msd1_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd1_map_u; + +/* Define the union csr_com_msd2_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd2_map_u; + +/* Define the union csr_com_msd3_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd3_map_u; + +/* Define the union csr_com_msd4_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd4_map_u; + +/* Define the union csr_com_msd5_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd5_map_u; + +/* Define the union csr_com_msd6_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd6_map_u; + +/* Define the union csr_com_msd7_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 totem_a_remap0 : 2; /* [1:0] */ + u32 totem_a_remap1 : 2; /* [3:2] */ + u32 totem_a_remap2 : 2; /* [5:4] */ + u32 totem_a_remap3 : 2; /* [7:6] */ + u32 totem_a_remap4 : 2; /* [9:8] */ + u32 totem_a_remap5 : 2; /* [11:10] */ + u32 totem_b_remap0 : 2; /* [13:12] */ + u32 totem_b_remap1 : 2; /* [15:14] */ + u32 totem_b_remap2 : 2; /* [17:16] */ + u32 totem_b_remap3 : 2; /* [19:18] */ + u32 totem_b_remap4 : 2; /* [21:20] */ + u32 totem_b_remap5 : 2; /* [23:22] */ + u32 skt_remap0 : 2; /* [25:24] */ + u32 skt_remap1 : 2; /* [27:26] */ + u32 skt_remap2 : 2; /* [29:28] */ + u32 skt_remap3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_com_msd7_map_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_com_cache_mode_u com_cache_mode; /* 88 */ + volatile csr_com_ddrintlv_addr_u com_ddrintlv_addr; /* 8C */ + volatile csr_com_partid_mode_u com_partid_mode; /* 90 */ + volatile csr_com_dec_l3_u com_dec_l3; /* 94 */ + volatile csr_com_sramintlv_u com_sramintlv; /* 98 */ + volatile csr_com_pg_u com_pg; /* A0 */ + volatile csr_com_ccix_u com_ccix; /* A8 */ + volatile csr_com_daw_msd_ctrl_u com_daw_msd_ctrl; /* C0 */ + volatile csr_com_daw_en_u com_daw_en; /* D0 */ + volatile csr_com_vf_ctrl_u com_vf_ctrl; /* E0 */ + volatile csr_com_vf_en_u com_vf_en; /* F0 */ + volatile csr_com_vf_baseaddr_u com_vf_baseaddr; /* F8 */ + volatile csr_com_daw0_addr_u com_daw0_addr; /* 100 */ + volatile csr_com_daw0_size_id_u com_daw0_size_id; /* 104 */ + volatile csr_com_daw1_addr_u com_daw1_addr; /* 110 */ + volatile csr_com_daw1_size_id_u com_daw1_size_id; /* 114 */ + volatile csr_com_daw2_addr_u com_daw2_addr; /* 120 */ + volatile csr_com_daw2_size_id_u com_daw2_size_id; /* 124 */ + volatile csr_com_daw3_addr_u com_daw3_addr; /* 130 */ + volatile csr_com_daw3_size_id_u com_daw3_size_id; /* 134 */ + volatile csr_com_daw4_addr_u com_daw4_addr; /* 140 */ + volatile csr_com_daw4_size_id_u com_daw4_size_id; /* 144 */ + volatile csr_com_daw5_addr_u com_daw5_addr; /* 150 */ + volatile csr_com_daw5_size_id_u com_daw5_size_id; /* 154 */ + volatile csr_com_daw6_addr_u com_daw6_addr; /* 160 */ + volatile csr_com_daw6_size_id_u com_daw6_size_id; /* 164 */ + volatile csr_com_daw7_addr_u com_daw7_addr; /* 170 */ + volatile csr_com_daw7_size_id_u com_daw7_size_id; /* 174 */ + volatile csr_com_daw8_addr_u com_daw8_addr; /* 180 */ + volatile csr_com_daw8_size_id_u com_daw8_size_id; /* 184 */ + volatile csr_com_daw9_addr_u com_daw9_addr; /* 190 */ + volatile csr_com_daw9_size_id_u com_daw9_size_id; /* 194 */ + volatile csr_com_daw10_addr_u com_daw10_addr; /* 1A0 */ + volatile csr_com_daw10_size_id_u com_daw10_size_id; /* 1A4 */ + volatile csr_com_daw11_addr_u com_daw11_addr; /* 1B0 */ + volatile csr_com_daw11_size_id_u com_daw11_size_id; /* 1B4 */ + volatile csr_com_daw12_addr_u com_daw12_addr; /* 1C0 */ + volatile csr_com_daw12_size_id_u com_daw12_size_id; /* 1C4 */ + volatile csr_com_daw13_addr_u com_daw13_addr; /* 1D0 */ + volatile csr_com_daw13_size_id_u com_daw13_size_id; /* 1D4 */ + volatile csr_com_daw14_addr_u com_daw14_addr; /* 1E0 */ + volatile csr_com_daw14_size_id_u com_daw14_size_id; /* 1E4 */ + volatile csr_com_daw15_addr_u com_daw15_addr; /* 1F0 */ + volatile csr_com_daw15_size_id_u com_daw15_size_id; /* 1F4 */ + volatile csr_com_daw16_addr_u com_daw16_addr; /* 200 */ + volatile csr_com_daw16_size_id_u com_daw16_size_id; /* 204 */ + volatile csr_com_daw17_addr_u com_daw17_addr; /* 210 */ + volatile csr_com_daw17_size_id_u com_daw17_size_id; /* 214 */ + volatile csr_com_daw18_addr_u com_daw18_addr; /* 220 */ + volatile csr_com_daw18_size_id_u com_daw18_size_id; /* 224 */ + volatile csr_com_daw19_addr_u com_daw19_addr; /* 230 */ + volatile csr_com_daw19_size_id_u com_daw19_size_id; /* 234 */ + volatile csr_com_daw20_addr_u com_daw20_addr; /* 240 */ + volatile csr_com_daw20_size_id_u com_daw20_size_id; /* 244 */ + volatile csr_com_daw21_addr_u com_daw21_addr; /* 250 */ + volatile csr_com_daw21_size_id_u com_daw21_size_id; /* 254 */ + volatile csr_com_daw22_addr_u com_daw22_addr; /* 260 */ + volatile csr_com_daw22_size_id_u com_daw22_size_id; /* 264 */ + volatile csr_com_daw23_addr_u com_daw23_addr; /* 270 */ + volatile csr_com_daw23_size_id_u com_daw23_size_id; /* 274 */ + volatile csr_com_daw24_addr_u com_daw24_addr; /* 280 */ + volatile csr_com_daw24_size_id_u com_daw24_size_id; /* 284 */ + volatile csr_com_daw25_addr_u com_daw25_addr; /* 290 */ + volatile csr_com_daw25_size_id_u com_daw25_size_id; /* 294 */ + volatile csr_com_daw26_addr_u com_daw26_addr; /* 2A0 */ + volatile csr_com_daw26_size_id_u com_daw26_size_id; /* 2A4 */ + volatile csr_com_daw27_addr_u com_daw27_addr; /* 2B0 */ + volatile csr_com_daw27_size_id_u com_daw27_size_id; /* 2B4 */ + volatile csr_com_daw28_addr_u com_daw28_addr; /* 2C0 */ + volatile csr_com_daw28_size_id_u com_daw28_size_id; /* 2C4 */ + volatile csr_com_daw29_addr_u com_daw29_addr; /* 2D0 */ + volatile csr_com_daw29_size_id_u com_daw29_size_id; /* 2D4 */ + volatile csr_com_daw30_addr_u com_daw30_addr; /* 2E0 */ + volatile csr_com_daw30_size_id_u com_daw30_size_id; /* 2E4 */ + volatile csr_com_daw31_addr_u com_daw31_addr; /* 2F0 */ + volatile csr_com_daw31_size_id_u com_daw31_size_id; /* 2F4 */ + volatile csr_com_vf00_id_u com_vf00_id; /* 300 */ + volatile csr_com_vf01_id_u com_vf01_id; /* 304 */ + volatile csr_com_vf02_id_u com_vf02_id; /* 308 */ + volatile csr_com_vf03_id_u com_vf03_id; /* 30C */ + volatile csr_com_vf04_id_u com_vf04_id; /* 310 */ + volatile csr_com_vf05_id_u com_vf05_id; /* 314 */ + volatile csr_com_vf06_id_u com_vf06_id; /* 318 */ + volatile csr_com_vf07_id_u com_vf07_id; /* 31C */ + volatile csr_com_vf08_id_u com_vf08_id; /* 320 */ + volatile csr_com_vf09_id_u com_vf09_id; /* 324 */ + volatile csr_com_vf10_id_u com_vf10_id; /* 328 */ + volatile csr_com_vf11_id_u com_vf11_id; /* 32C */ + volatile csr_com_vf12_id_u com_vf12_id; /* 330 */ + volatile csr_com_vf13_id_u com_vf13_id; /* 334 */ + volatile csr_com_vf14_id_u com_vf14_id; /* 338 */ + volatile csr_com_vf15_id_u com_vf15_id; /* 33C */ + volatile csr_com_vf16_id_u com_vf16_id; /* 340 */ + volatile csr_com_vf17_id_u com_vf17_id; /* 344 */ + volatile csr_com_vf18_id_u com_vf18_id; /* 348 */ + volatile csr_com_vf19_id_u com_vf19_id; /* 34C */ + volatile csr_com_vf20_id_u com_vf20_id; /* 350 */ + volatile csr_com_vf21_id_u com_vf21_id; /* 354 */ + volatile csr_com_vf22_id_u com_vf22_id; /* 358 */ + volatile csr_com_vf23_id_u com_vf23_id; /* 35C */ + volatile csr_com_vf24_id_u com_vf24_id; /* 360 */ + volatile csr_com_vf25_id_u com_vf25_id; /* 364 */ + volatile csr_com_vf26_id_u com_vf26_id; /* 368 */ + volatile csr_com_vf27_id_u com_vf27_id; /* 36C */ + volatile csr_com_vf28_id_u com_vf28_id; /* 370 */ + volatile csr_com_vf29_id_u com_vf29_id; /* 374 */ + volatile csr_com_vf30_id_u com_vf30_id; /* 378 */ + volatile csr_com_vf31_id_u com_vf31_id; /* 37C */ + volatile csr_com_msd0_ctrl_u com_msd0_ctrl; /* 380 */ + volatile csr_com_msd1_ctrl_u com_msd1_ctrl; /* 384 */ + volatile csr_com_msd2_ctrl_u com_msd2_ctrl; /* 388 */ + volatile csr_com_msd3_ctrl_u com_msd3_ctrl; /* 38C */ + volatile csr_com_msd4_ctrl_u com_msd4_ctrl; /* 390 */ + volatile csr_com_msd5_ctrl_u com_msd5_ctrl; /* 394 */ + volatile csr_com_msd6_ctrl_u com_msd6_ctrl; /* 398 */ + volatile csr_com_msd7_ctrl_u com_msd7_ctrl; /* 39C */ + volatile csr_com_msd0_map_u com_msd0_map; /* 3A0 */ + volatile csr_com_msd1_map_u com_msd1_map; /* 3A4 */ + volatile csr_com_msd2_map_u com_msd2_map; /* 3A8 */ + volatile csr_com_msd3_map_u com_msd3_map; /* 3AC */ + volatile csr_com_msd4_map_u com_msd4_map; /* 3B0 */ + volatile csr_com_msd5_map_u com_msd5_map; /* 3B4 */ + volatile csr_com_msd6_map_u com_msd6_map; /* 3B8 */ + volatile csr_com_msd7_map_u com_msd7_map; /* 3BC */ +} S_nimbus_REGS_TYPE; + +/* Declare the struct pointor of the module nimbus */ +extern volatile S_nimbus_REGS_TYPE *gopnimbusAllReg; + +/* Declare the functions that set the member value */ +int iSetCOM_CACHE_MODE_l3_intlv_mode(unsigned int ul3_intlv_mode); +int iSetCOM_DDRINTLV_ADDR_dmc_intlv_addr_set_sel(unsigned int udmc_intlv_addr_set_sel); +int iSetCOM_DDRINTLV_ADDR_dmc_intlv_addr_set_sel_xor(unsigned int udmc_intlv_addr_set_sel_xor); +int iSetCOM_DDRINTLV_ADDR_hha_intlv_addr_set_sel(unsigned int uhha_intlv_addr_set_sel); +int iSetCOM_DDRINTLV_ADDR_hha_intlv_addr_set_sel_xor(unsigned int uhha_intlv_addr_set_sel_xor); +int iSetCOM_DDRINTLV_ADDR_die_intlv_addr_set_sel(unsigned int udie_intlv_addr_set_sel); +int iSetCOM_DDRINTLV_ADDR_die_intlv_addr_set_sel_xor(unsigned int udie_intlv_addr_set_sel_xor); +int iSetCOM_DDRINTLV_ADDR_skt_intlv_addr_set_sel(unsigned int uskt_intlv_addr_set_sel); +int iSetCOM_DDRINTLV_ADDR_skt_intlv_addr_set_sel_xor(unsigned int uskt_intlv_addr_set_sel_xor); +int iSetCOM_PARTID_MODE_partid_mode_nc(unsigned int upartid_mode_nc); +int iSetCOM_PARTID_MODE_partid_mode_c(unsigned int upartid_mode_c); +int iSetCOM_PARTID_MODE_pmg_qos_switch_en(unsigned int upmg_qos_switch_en); +int iSetCOM_DEC_L3_bypass_l3_wu(unsigned int ubypass_l3_wu); +int iSetCOM_DEC_L3_bypass_l3_skt(unsigned int ubypass_l3_skt); +int iSetCOM_DEC_L3_nca_enable(unsigned int unca_enable); +int iSetCOM_DEC_L3_stash_hha_en(unsigned int ustash_hha_en); +int iSetCOM_DEC_L3_bypass_l3_ro(unsigned int ubypass_l3_ro); +int iSetCOM_DEC_L3_bypass_nonsnp(unsigned int ubypass_nonsnp); +int iSetCOM_DEC_L3_stash_local_l3_en(unsigned int ustash_local_l3_en); +int iSetCOM_DEC_L3_csp_en(unsigned int ucsp_en); +int iSetCOM_DEC_L3_inter_atomic_bypass_en(unsigned int uinter_atomic_bypass_en); +int iSetCOM_DEC_L3_todef_pcie_dispatch_en(unsigned int utodef_pcie_dispatch_en); +int iSetCOM_DEC_L3_ro2hha_force_nca_en(unsigned int uro2hha_force_nca_en); +int iSetCOM_DEC_L3_ext_defslv_tgtid_cfg(unsigned int uext_defslv_tgtid_cfg); +int iSetCOM_DEC_L3_reg_davinci_en(unsigned int ureg_davinci_en); +int iSetCOM_DEC_L3_virtruvian_en(unsigned int uvirtruvian_en); +int iSetCOM_DEC_L3_intra_atomic_bypass_en(unsigned int uintra_atomic_bypass_en); +int iSetCOM_SRAMINTLV_sram_intlv_en(unsigned int usram_intlv_en); +int iSetCOM_PG_pg_intlv_en(unsigned int upg_intlv_en); +int iSetCOM_CCIX_cpa_tgtid_en(unsigned int ucpa_tgtid_en); +int iSetCOM_DAW_MSD_CTRL_daw_msd_reset_n(unsigned int udaw_msd_reset_n); +int iSetCOM_DAW_MSD_CTRL_daw_msd_cfg_en(unsigned int udaw_msd_cfg_en); +int iSetCOM_DAW_EN_sysdaw_en(unsigned int usysdaw_en); +int iSetCOM_VF_CTRL_vf_reset_n(unsigned int uvf_reset_n); +int iSetCOM_VF_CTRL_vf_cfg_en(unsigned int uvf_cfg_en); +int iSetCOM_VF_CTRL_vf_func_en(unsigned int uvf_func_en); +int iSetCOM_VF_EN_vf_en(unsigned int uvf_en); +int iSetCOM_VF_BASEADDR_base_addr(unsigned int ubase_addr); +int iSetCOM_DAW0_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW0_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW0_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW0_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW0_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW0_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW0_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW0_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW0_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW0_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW1_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW1_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW1_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW1_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW1_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW1_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW1_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW1_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW1_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW1_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW2_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW2_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW2_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW2_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW2_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW2_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW2_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW2_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW2_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW2_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW3_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW3_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW3_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW3_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW3_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW3_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW3_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW3_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW3_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW3_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW4_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW4_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW4_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW4_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW4_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW4_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW4_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW4_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW4_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW4_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW5_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW5_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW5_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW5_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW5_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW5_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW5_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW5_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW5_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW5_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW6_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW6_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW6_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW6_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW6_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW6_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW6_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW6_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW6_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW6_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW7_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW7_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW7_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW7_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW7_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW7_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW7_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW7_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW7_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW7_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW8_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW8_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW8_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW8_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW8_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW8_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW8_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW8_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW8_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW8_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW9_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW9_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW9_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW9_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW9_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW9_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW9_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW9_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW9_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW9_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW10_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW10_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW10_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW10_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW10_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW10_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW10_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW10_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW10_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW10_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW11_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW11_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW11_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW11_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW11_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW11_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW11_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW11_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW11_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW11_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW12_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW12_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW12_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW12_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW12_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW12_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW12_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW12_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW12_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW12_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW13_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW13_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW13_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW13_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW13_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW13_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW13_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW13_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW13_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW13_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW14_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW14_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW14_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW14_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW14_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW14_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW14_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW14_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW14_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW14_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW15_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW15_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW15_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW15_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW15_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW15_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW15_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW15_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW15_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW15_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW16_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW16_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW16_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW16_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW16_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW16_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW16_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW16_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW16_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW16_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW17_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW17_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW17_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW17_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW17_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW17_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW17_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW17_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW17_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW17_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW18_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW18_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW18_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW18_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW18_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW18_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW18_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW18_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW18_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW18_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW19_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW19_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW19_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW19_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW19_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW19_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW19_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW19_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW19_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW19_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW20_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW20_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW20_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW20_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW20_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW20_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW20_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW20_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW20_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW20_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW21_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW21_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW21_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW21_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW21_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW21_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW21_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW21_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW21_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW21_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW22_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW22_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW22_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW22_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW22_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW22_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW22_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW22_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW22_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW22_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW23_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW23_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW23_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW23_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW23_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW23_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW23_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW23_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW23_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW23_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW24_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW24_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW24_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW24_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW24_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW24_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW24_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW24_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW24_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW24_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW25_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW25_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW25_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW25_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW25_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW25_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW25_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW25_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW25_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW25_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW26_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW26_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW26_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW26_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW26_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW26_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW26_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW26_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW26_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW26_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW27_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW27_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW27_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW27_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW27_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW27_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW27_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW27_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW27_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW27_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW28_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW28_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW28_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW28_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW28_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW28_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW28_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW28_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW28_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW28_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW29_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW29_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW29_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW29_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW29_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW29_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW29_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW29_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW29_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW29_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW30_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW30_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW30_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW30_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW30_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW30_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW30_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW30_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW30_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW30_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_DAW31_ADDR_sysdaw_addr(unsigned int usysdaw_addr); +int iSetCOM_DAW31_SIZE_ID_sysdaw_portid(unsigned int usysdaw_portid); +int iSetCOM_DAW31_SIZE_ID_sysdaw_dieid(unsigned int usysdaw_dieid); +int iSetCOM_DAW31_SIZE_ID_sysdaw_sktid(unsigned int usysdaw_sktid); +int iSetCOM_DAW31_SIZE_ID_sysdaw_size(unsigned int usysdaw_size); +int iSetCOM_DAW31_SIZE_ID_sysdaw_cpa_four_chip(unsigned int usysdaw_cpa_four_chip); +int iSetCOM_DAW31_SIZE_ID_sysdaw_cpa_two_chip(unsigned int usysdaw_cpa_two_chip); +int iSetCOM_DAW31_SIZE_ID_sysdaw_four_chip(unsigned int usysdaw_four_chip); +int iSetCOM_DAW31_SIZE_ID_sysdaw_two_chip(unsigned int usysdaw_two_chip); +int iSetCOM_DAW31_SIZE_ID_hole_en(unsigned int uhole_en); +int iSetCOM_VF00_ID_port_id(unsigned int uport_id); +int iSetCOM_VF00_ID_die_id(unsigned int udie_id); +int iSetCOM_VF01_ID_port_id(unsigned int uport_id); +int iSetCOM_VF01_ID_die_id(unsigned int udie_id); +int iSetCOM_VF02_ID_port_id(unsigned int uport_id); +int iSetCOM_VF02_ID_die_id(unsigned int udie_id); +int iSetCOM_VF03_ID_port_id(unsigned int uport_id); +int iSetCOM_VF03_ID_die_id(unsigned int udie_id); +int iSetCOM_VF04_ID_port_id(unsigned int uport_id); +int iSetCOM_VF04_ID_die_id(unsigned int udie_id); +int iSetCOM_VF05_ID_port_id(unsigned int uport_id); +int iSetCOM_VF05_ID_die_id(unsigned int udie_id); +int iSetCOM_VF06_ID_port_id(unsigned int uport_id); +int iSetCOM_VF06_ID_die_id(unsigned int udie_id); +int iSetCOM_VF07_ID_port_id(unsigned int uport_id); +int iSetCOM_VF07_ID_die_id(unsigned int udie_id); +int iSetCOM_VF08_ID_port_id(unsigned int uport_id); +int iSetCOM_VF08_ID_die_id(unsigned int udie_id); +int iSetCOM_VF09_ID_port_id(unsigned int uport_id); +int iSetCOM_VF09_ID_die_id(unsigned int udie_id); +int iSetCOM_VF10_ID_port_id(unsigned int uport_id); +int iSetCOM_VF10_ID_die_id(unsigned int udie_id); +int iSetCOM_VF11_ID_port_id(unsigned int uport_id); +int iSetCOM_VF11_ID_die_id(unsigned int udie_id); +int iSetCOM_VF12_ID_port_id(unsigned int uport_id); +int iSetCOM_VF12_ID_die_id(unsigned int udie_id); +int iSetCOM_VF13_ID_port_id(unsigned int uport_id); +int iSetCOM_VF13_ID_die_id(unsigned int udie_id); +int iSetCOM_VF14_ID_port_id(unsigned int uport_id); +int iSetCOM_VF14_ID_die_id(unsigned int udie_id); +int iSetCOM_VF15_ID_port_id(unsigned int uport_id); +int iSetCOM_VF15_ID_die_id(unsigned int udie_id); +int iSetCOM_VF16_ID_port_id(unsigned int uport_id); +int iSetCOM_VF16_ID_die_id(unsigned int udie_id); +int iSetCOM_VF17_ID_port_id(unsigned int uport_id); +int iSetCOM_VF17_ID_die_id(unsigned int udie_id); +int iSetCOM_VF18_ID_port_id(unsigned int uport_id); +int iSetCOM_VF18_ID_die_id(unsigned int udie_id); +int iSetCOM_VF19_ID_port_id(unsigned int uport_id); +int iSetCOM_VF19_ID_die_id(unsigned int udie_id); +int iSetCOM_VF20_ID_port_id(unsigned int uport_id); +int iSetCOM_VF20_ID_die_id(unsigned int udie_id); +int iSetCOM_VF21_ID_port_id(unsigned int uport_id); +int iSetCOM_VF21_ID_die_id(unsigned int udie_id); +int iSetCOM_VF22_ID_port_id(unsigned int uport_id); +int iSetCOM_VF22_ID_die_id(unsigned int udie_id); +int iSetCOM_VF23_ID_port_id(unsigned int uport_id); +int iSetCOM_VF23_ID_die_id(unsigned int udie_id); +int iSetCOM_VF24_ID_port_id(unsigned int uport_id); +int iSetCOM_VF24_ID_die_id(unsigned int udie_id); +int iSetCOM_VF25_ID_port_id(unsigned int uport_id); +int iSetCOM_VF25_ID_die_id(unsigned int udie_id); +int iSetCOM_VF26_ID_port_id(unsigned int uport_id); +int iSetCOM_VF26_ID_die_id(unsigned int udie_id); +int iSetCOM_VF27_ID_port_id(unsigned int uport_id); +int iSetCOM_VF27_ID_die_id(unsigned int udie_id); +int iSetCOM_VF28_ID_port_id(unsigned int uport_id); +int iSetCOM_VF28_ID_die_id(unsigned int udie_id); +int iSetCOM_VF29_ID_port_id(unsigned int uport_id); +int iSetCOM_VF29_ID_die_id(unsigned int udie_id); +int iSetCOM_VF30_ID_port_id(unsigned int uport_id); +int iSetCOM_VF30_ID_die_id(unsigned int udie_id); +int iSetCOM_VF31_ID_port_id(unsigned int uport_id); +int iSetCOM_VF31_ID_die_id(unsigned int udie_id); +int iSetCOM_MSD0_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD0_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD0_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD0_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD0_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD0_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD0_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD1_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD1_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD1_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD1_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD1_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD1_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD1_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD2_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD2_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD2_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD2_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD2_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD2_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD2_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD3_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD3_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD3_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD3_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD3_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD3_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD3_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD4_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD4_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD4_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD4_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD4_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD4_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD4_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD5_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD5_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD5_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD5_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD5_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD5_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD5_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD6_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD6_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD6_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD6_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD6_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD6_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD6_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD7_CTRL_ddr_intlv_baseaddr(unsigned int uddr_intlv_baseaddr); +int iSetCOM_MSD7_CTRL_ddr_intlv_size(unsigned int uddr_intlv_size); +int iSetCOM_MSD7_CTRL_ddr_intlv_ch(unsigned int uddr_intlv_ch); +int iSetCOM_MSD7_CTRL_ddr_intlv_die(unsigned int uddr_intlv_die); +int iSetCOM_MSD7_CTRL_ddr_nonintlv_die_tgt(unsigned int uddr_nonintlv_die_tgt); +int iSetCOM_MSD7_CTRL_ddr_intlv_skt(unsigned int uddr_intlv_skt); +int iSetCOM_MSD7_CTRL_msd_en(unsigned int umsd_en); +int iSetCOM_MSD0_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD0_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD0_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD0_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD0_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD0_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD0_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD0_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD0_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD0_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD0_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD0_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD0_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD0_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD0_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD0_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD1_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD1_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD1_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD1_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD1_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD1_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD1_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD1_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD1_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD1_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD1_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD1_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD1_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD1_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD1_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD1_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD2_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD2_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD2_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD2_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD2_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD2_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD2_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD2_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD2_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD2_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD2_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD2_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD2_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD2_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD2_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD2_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD3_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD3_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD3_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD3_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD3_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD3_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD3_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD3_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD3_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD3_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD3_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD3_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD3_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD3_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD3_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD3_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD4_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD4_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD4_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD4_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD4_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD4_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD4_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD4_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD4_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD4_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD4_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD4_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD4_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD4_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD4_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD4_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD5_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD5_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD5_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD5_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD5_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD5_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD5_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD5_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD5_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD5_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD5_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD5_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD5_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD5_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD5_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD5_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD6_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD6_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD6_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD6_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD6_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD6_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD6_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD6_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD6_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD6_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD6_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD6_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD6_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD6_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD6_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD6_MAP_skt_remap3(unsigned int uskt_remap3); +int iSetCOM_MSD7_MAP_totem_a_remap0(unsigned int utotem_a_remap0); +int iSetCOM_MSD7_MAP_totem_a_remap1(unsigned int utotem_a_remap1); +int iSetCOM_MSD7_MAP_totem_a_remap2(unsigned int utotem_a_remap2); +int iSetCOM_MSD7_MAP_totem_a_remap3(unsigned int utotem_a_remap3); +int iSetCOM_MSD7_MAP_totem_a_remap4(unsigned int utotem_a_remap4); +int iSetCOM_MSD7_MAP_totem_a_remap5(unsigned int utotem_a_remap5); +int iSetCOM_MSD7_MAP_totem_b_remap0(unsigned int utotem_b_remap0); +int iSetCOM_MSD7_MAP_totem_b_remap1(unsigned int utotem_b_remap1); +int iSetCOM_MSD7_MAP_totem_b_remap2(unsigned int utotem_b_remap2); +int iSetCOM_MSD7_MAP_totem_b_remap3(unsigned int utotem_b_remap3); +int iSetCOM_MSD7_MAP_totem_b_remap4(unsigned int utotem_b_remap4); +int iSetCOM_MSD7_MAP_totem_b_remap5(unsigned int utotem_b_remap5); +int iSetCOM_MSD7_MAP_skt_remap0(unsigned int uskt_remap0); +int iSetCOM_MSD7_MAP_skt_remap1(unsigned int uskt_remap1); +int iSetCOM_MSD7_MAP_skt_remap2(unsigned int uskt_remap2); +int iSetCOM_MSD7_MAP_skt_remap3(unsigned int uskt_remap3); + + +#endif // PHOSPHOR_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/phosphor_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/phosphor_reg_offset.h new file mode 100644 index 000000000..4b6ea8cbf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/phosphor_reg_offset.h @@ -0,0 +1,149 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : phosphor_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : V680 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/04/28 23:05:45 Create file +// ****************************************************************************** + +#ifndef PHOSPHOR_REG_OFFSET_H +#define PHOSPHOR_REG_OFFSET_H + +/* NIMBUS Base address of Module's Register */ +#define CSR_NIMBUS_BASE (0x0) + +/* **************************************************************************** */ +/* NIMBUS Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_NIMBUS_COM_CACHE_MODE_REG (CSR_NIMBUS_BASE + 0x88) /* Cache交织模式选择寄存器。 */ +#define CSR_NIMBUS_COM_DDRINTLV_ADDR_REG (CSR_NIMBUS_BASE + 0x8C) /* 各DDR交织模式选取的地址段配置寄存器。 */ +#define CSR_NIMBUS_COM_PARTID_MODE_REG (CSR_NIMBUS_BASE + 0x90) /* PARTID生成模式配置寄存器。 */ +#define CSR_NIMBUS_COM_DEC_L3_REG (CSR_NIMBUS_BASE + 0x94) /* 与L3相关的译码控制寄存器。 */ +#define CSR_NIMBUS_COM_SRAMINTLV_REG (CSR_NIMBUS_BASE + 0x98) /* L3D作为SRAM使用时的交织控制寄存器。 */ +#define CSR_NIMBUS_COM_PG_REG (CSR_NIMBUS_BASE + 0xA0) /* Partial Good相关的控制寄存器。 */ +#define CSR_NIMBUS_COM_CCIX_REG (CSR_NIMBUS_BASE + 0xA8) /* CCIX相关的控制寄存器。 */ +#define CSR_NIMBUS_COM_DAW_MSD_CTRL_REG (CSR_NIMBUS_BASE + 0xC0) /* DAW和MSD配置控制寄存器。 */ +#define CSR_NIMBUS_COM_DAW_EN_REG (CSR_NIMBUS_BASE + 0xD0) /* DAW窗口使能寄存器。 */ +#define CSR_NIMBUS_COM_VF_CTRL_REG (CSR_NIMBUS_BASE + 0xE0) /* VF配置控制寄存器。 */ +#define CSR_NIMBUS_COM_VF_EN_REG (CSR_NIMBUS_BASE + 0xF0) /* VF空间使能配置寄存器。 */ +#define CSR_NIMBUS_COM_VF_BASEADDR_REG (CSR_NIMBUS_BASE + 0xF8) /* VF空间基地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW0_ADDR_REG (CSR_NIMBUS_BASE + 0x100) /* 一级DAW0起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW0_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x104) /* 一级DAW0窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW1_ADDR_REG (CSR_NIMBUS_BASE + 0x110) /* 一级DAW1起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW1_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x114) /* 一级DAW1窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW2_ADDR_REG (CSR_NIMBUS_BASE + 0x120) /* 一级DAW2起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW2_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x124) /* 一级DAW2窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW3_ADDR_REG (CSR_NIMBUS_BASE + 0x130) /* 一级DAW3起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW3_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x134) /* 一级DAW3窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW4_ADDR_REG (CSR_NIMBUS_BASE + 0x140) /* 一级DAW4起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW4_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x144) /* 一级DAW4窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW5_ADDR_REG (CSR_NIMBUS_BASE + 0x150) /* 一级DAW5起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW5_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x154) /* 一级DAW5窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW6_ADDR_REG (CSR_NIMBUS_BASE + 0x160) /* 一级DAW6起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW6_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x164) /* 一级DAW6窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW7_ADDR_REG (CSR_NIMBUS_BASE + 0x170) /* 一级DAW7起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW7_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x174) /* 一级DAW7窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW8_ADDR_REG (CSR_NIMBUS_BASE + 0x180) /* 一级DAW8起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW8_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x184) /* 一级DAW8窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW9_ADDR_REG (CSR_NIMBUS_BASE + 0x190) /* 一级DAW9起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW9_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x194) /* 一级DAW9窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW10_ADDR_REG (CSR_NIMBUS_BASE + 0x1A0) /* 一级DAW10起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW10_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x1A4) /* 一级DAW10窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW11_ADDR_REG (CSR_NIMBUS_BASE + 0x1B0) /* 一级DAW11起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW11_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x1B4) /* 一级DAW11窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW12_ADDR_REG (CSR_NIMBUS_BASE + 0x1C0) /* 一级DAW12起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW12_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x1C4) /* 一级DAW12窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW13_ADDR_REG (CSR_NIMBUS_BASE + 0x1D0) /* 一级DAW13起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW13_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x1D4) /* 一级DAW13窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW14_ADDR_REG (CSR_NIMBUS_BASE + 0x1E0) /* 一级DAW14起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW14_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x1E4) /* 一级DAW14窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW15_ADDR_REG (CSR_NIMBUS_BASE + 0x1F0) /* 一级DAW15起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW15_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x1F4) /* 一级DAW15窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW16_ADDR_REG (CSR_NIMBUS_BASE + 0x200) /* 一级DAW16起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW16_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x204) /* 一级DAW16窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW17_ADDR_REG (CSR_NIMBUS_BASE + 0x210) /* 一级DAW17起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW17_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x214) /* 一级DAW17窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW18_ADDR_REG (CSR_NIMBUS_BASE + 0x220) /* 一级DAW18起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW18_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x224) /* 一级DAW18窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW19_ADDR_REG (CSR_NIMBUS_BASE + 0x230) /* 一级DAW19起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW19_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x234) /* 一级DAW19窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW20_ADDR_REG (CSR_NIMBUS_BASE + 0x240) /* 一级DAW20起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW20_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x244) /* 一级DAW20窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW21_ADDR_REG (CSR_NIMBUS_BASE + 0x250) /* 一级DAW21起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW21_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x254) /* 一级DAW21窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW22_ADDR_REG (CSR_NIMBUS_BASE + 0x260) /* 一级DAW22起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW22_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x264) /* 一级DAW22窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW23_ADDR_REG (CSR_NIMBUS_BASE + 0x270) /* 一级DAW23起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW23_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x274) /* 一级DAW23窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW24_ADDR_REG (CSR_NIMBUS_BASE + 0x280) /* 一级DAW24起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW24_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x284) /* 一级DAW24窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW25_ADDR_REG (CSR_NIMBUS_BASE + 0x290) /* 一级DAW25起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW25_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x294) /* 一级DAW25窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW26_ADDR_REG (CSR_NIMBUS_BASE + 0x2A0) /* 一级DAW26起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW26_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x2A4) /* 一级DAW26窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW27_ADDR_REG (CSR_NIMBUS_BASE + 0x2B0) /* 一级DAW27起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW27_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x2B4) /* 一级DAW27窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW28_ADDR_REG (CSR_NIMBUS_BASE + 0x2C0) /* 一级DAW28起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW28_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x2C4) /* 一级DAW28窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW29_ADDR_REG (CSR_NIMBUS_BASE + 0x2D0) /* 一级DAW29起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW29_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x2D4) /* 一级DAW29窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW30_ADDR_REG (CSR_NIMBUS_BASE + 0x2E0) /* 一级DAW30起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW30_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x2E4) /* 一级DAW30窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW31_ADDR_REG (CSR_NIMBUS_BASE + 0x2F0) /* 一级DAW31起始地址配置寄存器。 */ +#define CSR_NIMBUS_COM_DAW31_SIZE_ID_REG (CSR_NIMBUS_BASE + 0x2F4) /* 一级DAW31窗口大小和目的配置寄存器。 */ +#define CSR_NIMBUS_COM_VF00_ID_REG (CSR_NIMBUS_BASE + 0x300) /* VF00所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF01_ID_REG (CSR_NIMBUS_BASE + 0x304) /* VF01所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF02_ID_REG (CSR_NIMBUS_BASE + 0x308) /* VF02所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF03_ID_REG (CSR_NIMBUS_BASE + 0x30C) /* VF03所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF04_ID_REG (CSR_NIMBUS_BASE + 0x310) /* VF04所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF05_ID_REG (CSR_NIMBUS_BASE + 0x314) /* VF05所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF06_ID_REG (CSR_NIMBUS_BASE + 0x318) /* VF06所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF07_ID_REG (CSR_NIMBUS_BASE + 0x31C) /* VF07所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF08_ID_REG (CSR_NIMBUS_BASE + 0x320) /* VF08所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF09_ID_REG (CSR_NIMBUS_BASE + 0x324) /* VF09所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF10_ID_REG (CSR_NIMBUS_BASE + 0x328) /* VF10所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF11_ID_REG (CSR_NIMBUS_BASE + 0x32C) /* VF11所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF12_ID_REG (CSR_NIMBUS_BASE + 0x330) /* VF12所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF13_ID_REG (CSR_NIMBUS_BASE + 0x334) /* VF13所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF14_ID_REG (CSR_NIMBUS_BASE + 0x338) /* VF14所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF15_ID_REG (CSR_NIMBUS_BASE + 0x33C) /* VF15所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF16_ID_REG (CSR_NIMBUS_BASE + 0x340) /* VF16所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF17_ID_REG (CSR_NIMBUS_BASE + 0x344) /* VF17所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF18_ID_REG (CSR_NIMBUS_BASE + 0x348) /* VF18所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF19_ID_REG (CSR_NIMBUS_BASE + 0x34C) /* VF19所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF20_ID_REG (CSR_NIMBUS_BASE + 0x350) /* VF20所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF21_ID_REG (CSR_NIMBUS_BASE + 0x354) /* VF21所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF22_ID_REG (CSR_NIMBUS_BASE + 0x358) /* VF22所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF23_ID_REG (CSR_NIMBUS_BASE + 0x35C) /* VF23所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF24_ID_REG (CSR_NIMBUS_BASE + 0x360) /* VF24所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF25_ID_REG (CSR_NIMBUS_BASE + 0x364) /* VF25所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF26_ID_REG (CSR_NIMBUS_BASE + 0x368) /* VF26所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF27_ID_REG (CSR_NIMBUS_BASE + 0x36C) /* VF27所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF28_ID_REG (CSR_NIMBUS_BASE + 0x370) /* VF28所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF29_ID_REG (CSR_NIMBUS_BASE + 0x374) /* VF29所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF30_ID_REG (CSR_NIMBUS_BASE + 0x378) /* VF30所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_VF31_ID_REG (CSR_NIMBUS_BASE + 0x37C) /* VF31所属子系统的ID配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD0_CTRL_REG (CSR_NIMBUS_BASE + 0x380) /* MSD0配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD1_CTRL_REG (CSR_NIMBUS_BASE + 0x384) /* MSD1配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD2_CTRL_REG (CSR_NIMBUS_BASE + 0x388) /* MSD2配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD3_CTRL_REG (CSR_NIMBUS_BASE + 0x38C) /* MSD3配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD4_CTRL_REG (CSR_NIMBUS_BASE + 0x390) /* MSD4配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD5_CTRL_REG (CSR_NIMBUS_BASE + 0x394) /* MSD5配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD6_CTRL_REG (CSR_NIMBUS_BASE + 0x398) /* MSD6配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD7_CTRL_REG (CSR_NIMBUS_BASE + 0x39C) /* MSD7配置寄存器。 */ +#define CSR_NIMBUS_COM_MSD0_MAP_REG (CSR_NIMBUS_BASE + 0x3A0) /* MSD0地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD1_MAP_REG (CSR_NIMBUS_BASE + 0x3A4) /* MSD1地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD2_MAP_REG (CSR_NIMBUS_BASE + 0x3A8) /* MSD2地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD3_MAP_REG (CSR_NIMBUS_BASE + 0x3AC) /* MSD3地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD4_MAP_REG (CSR_NIMBUS_BASE + 0x3B0) /* MSD4地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD5_MAP_REG (CSR_NIMBUS_BASE + 0x3B4) /* MSD5地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD6_MAP_REG (CSR_NIMBUS_BASE + 0x3B8) /* MSD6地址段重映射寄存器。 */ +#define CSR_NIMBUS_COM_MSD7_MAP_REG (CSR_NIMBUS_BASE + 0x3BC) /* MSD7地址段重映射寄存器。 */ + +#endif // PHOSPHOR_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/plat_efuse.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/plat_efuse.h new file mode 100644 index 000000000..6fee796a5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/plat_efuse.h @@ -0,0 +1,368 @@ +/* +* Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. +* Description :Component description file about platform efuse. +* Author : Huawei +* Create : 2023/04/12 +*/ + +#ifndef __PLAT_EFUSE_H__ +#define __PLAT_EFUSE_H__ + +#define PLAT_TOTEM_DIE_ID_TOTAL 23 +#define PLAT_NIMBUS_DIE_ID_TOTAL 64 +#define PLAT_NIMBUS_S_DIE_ID_TOTAL 17 + +#define PLAT_EFUSE_1620CS_VERISON_0 0 +#define PLAT_EFUSE_1620_S_VERISON_0 1 + +#define PLAT_EFUSE_VERSION PLAT_EFUSE_1620_VERISON_0 + +#if (PLAT_EFUSE_VERSION == PLAT_EFUSE_1620CS_VERISON_0) + #define PLAT_EFUSE_CHIP_TOTAL 1721 + #define PLAT_EFUSE_INFO_COLUMN 41 + #define PLAT_EFUSE_CLUSTER_TOTAL 16 + + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER0_CH0 9 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER1_CH0 10 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER2_CH0 11 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER3_CH0 12 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER4_CH0 13 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER5_CH0 14 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER6_CH0 15 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER7_CH0 16 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER0_CH1 17 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER1_CH1 18 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER2_CH1 19 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER3_CH1 20 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER4_CH1 21 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER5_CH1 22 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER6_CH1 23 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER7_CH1 24 + +#elif (PLAT_EFUSE_VERSION == PLAT_EFUSE_1620_S_VERISON_0) + #define PLAT_EFUSE_CHIP_TOTAL 1743 + #define PLAT_EFUSE_INFO_COLUMN 25 + #define PLAT_EFUSE_CLUSTER_TOTAL 8 + + + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER0_CH0 9 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER1_CH0 10 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER2_CH0 11 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER3_CH0 12 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER4_CH0 13 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER5_CH0 14 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER6_CH0 15 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER7_CH0 16 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER0_CH1 17 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER1_CH1 18 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER2_CH1 19 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER3_CH1 20 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER4_CH1 21 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER5_CH1 22 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER6_CH1 23 + #define PLAT_EFUSE_TABLE_INDEX_TA_CLUSTER7_CH1 24 + +#endif + +typedef union totem_die_id0 { + // Define the struct bits + struct { + unsigned int dieid_std_ver : 3; // [2..0] + unsigned int mr_flag : 1; // [3] + unsigned int ltidsum_27_0 : 28; // [31..4] + } bits; + + unsigned int value; +} totem_die_id0_t; + +typedef union totem_die_id1 { + // Define the struct bits + struct { + unsigned int ltidsum_35_28 : 8; // [7..0] [39..32] + unsigned int waferid : 5; // [12..8] [44..40] + unsigned int die_x : 8; // [20..13] [52..45] + unsigned int die_y : 8; // [28..21] [60..53] + unsigned int passflag_rt_cp : 1; // [29] [61] + unsigned int failflag_all : 2; // [31..30] [63..62] + } bits; + + unsigned int value; +} totem_die_id1_t; + +typedef union totem_die_id2 { + // Define the struct bits + struct { + unsigned int year : 6; // [5..0] [69..64] + unsigned int mon : 4; // [9..6] [73..70] + unsigned int day : 5; // [14..10] [78..74] + unsigned int hour : 5; // [19..15] [83..79] + unsigned int min : 6; // [25..20] [89..84] + unsigned int sec : 6; // [31..26] [95..90] + } bits; + + unsigned int value; +} totem_die_id2_t; + +typedef union totem_die_id3 { + // Define the struct bits + struct { + unsigned int ipaddrsum : 32; // [31..0] [127..96] + } bits; + + unsigned int value; +} totem_die_id3_t; + +typedef union totem_die_id4 { + // Define the struct bits + struct { + unsigned int passflag_rt_ft : 1; // [0] [128] + unsigned int passflag_ht_ft : 1; // [1] [129] + unsigned int burnin_flag : 1; // [2] [130] + unsigned int passflag_rt_bi_ft : 1; // [3] [131] + unsigned int passflag_ht_bi_ft : 1; // [4] [132] + unsigned int site_num_ft : 4; // [8..5] [136..133] + unsigned int ec_ver : 3; // [11..9] [139..137] + unsigned int pkg_info : 4; // [15..12] [143..140] + unsigned int img_ver : 4; // [19..16] [147..144] + unsigned int passflag_lt_cp : 1; // [20] [148] + unsigned int project_efuse_map_ver : 3; // [23..21] [151..149] + unsigned int crc8_cp_dieid : 8; // [31..24] [159..152] + } bits; + + unsigned int value; +} totem_die_id4_t; + +typedef union totem_die_id5 { + // Define the struct bits + struct { + unsigned int slt_ver : 8; // [7..0] [167..160] + unsigned int cp_ver : 8; // [15..8] [175..168] + unsigned int ft_ver : 8; // [23..16] [183..176] + unsigned int foundry_id : 4; // [27..24] [187..184] + unsigned int chip_loc_3_0 : 4; // [31..28] [191..188] + } bits; + + unsigned int value; +} totem_die_id5_t; + +typedef union totem_die_id6 { + // Define the struct bits + struct { + unsigned int chip_loc_36_4 : 32; // [31..0] [223..192] + } bits; + + unsigned int value; +} totem_die_id6_t; + +typedef union totem_die_id7 { + // Define the struct bits + struct { + unsigned int chip_loc_59_37 : 24; // [23..0] [247..224] + unsigned int passflag_rt_ftb : 1; // [24] [248] + unsigned int passflag_rt_bi_ftb : 1; // [25] [249] + unsigned int passflag_ht_ftb : 1; // [26] [250] + unsigned int passflag_ht_bi_ftb : 1; // [27] [251] + unsigned int passflag_rt_ftc : 1; // [28] [252] + unsigned int passflag_rt_bi_ftc : 1; // [29] [253] + unsigned int passflag_ht_ftc : 1; // [30] [254] + unsigned int passflag_ht_bi_ftc : 1; // [31] [255] + } bits; + + unsigned int value; +} totem_die_id7_t; + +typedef union totem_die_id8 { + // Define the struct bits + struct { + unsigned int ht_iddq : 19; // [18..0] [274..256] + unsigned int nt_iddq_12_0 : 13; // [31..19] [287..275] + } bits; + + unsigned int value; +} totem_die_id8_t; + +typedef union totem_die_id9 { + // Define the struct bits + struct { + unsigned int nt_iddq_16_13 : 4; // [3..0] [291..288] + unsigned int speed_grade : 4; // [7..4] [295..292] + unsigned int bb_layers : 4; // [11..8] [299..296] + unsigned int pkg_mode : 4; // [15..12] [303..300] + unsigned int power_grade : 8; // [23..16] [311..304] + unsigned int tr5_avs_id_7_0 : 8; // [31..24] [319..312] + } bits; + + unsigned int value; +} totem_die_id9_t; + +typedef union totem_die_id10 { + // Define the struct bits + struct { + unsigned int tr5_avs_id_19_8 : 12; // [11..0] [331..320] + unsigned int tsensor0_trim_19_0 : 20; // [31..12] [351..332] + } bits; + + unsigned int value; +} totem_die_id10_t; + +typedef union totem_die_id11 { + // Define the struct bits + struct { + unsigned int tsensor0_trim_21_20 : 2; // [1..0] [353..352] + unsigned int tsensor1_trim_21_0 : 22; // [23..2] [375..354] + unsigned int ddr_2933_flag : 1; // [24] [376] + unsigned int ddr_2933_flag_ht : 1; // [25] [377] + unsigned int reserved : 6; // [31..26] [383..378] + } bits; + + unsigned int value; +} totem_die_id11_t; + +typedef union totem_die_id12 { + // Define the struct bits + struct { + unsigned int reserved : 32; // [31..0] [415..384] + } bits; + + unsigned int value; +} totem_die_id12_t; + +typedef union totem_die_id13 { + // Define the struct bits + struct { + unsigned int core_test_flag : 32; // [31..0] [447..416] + } bits; + + unsigned int value; +} totem_die_id13_t; + +typedef union totem_die_id14 { + // Define the struct bits + struct { + unsigned int l3d_mem_grp_test_flag : 20; // [19..0] [467..448] + unsigned int pg_pd_flag : 8; // [27..20] [475..468] + unsigned int pg_pd_sel : 1; // [28] [476] + unsigned int reserved : 3; // [31..29] [479..477] + } bits; + + unsigned int value; +} totem_die_id14_t; + +typedef union totem_die_id15 { + // Define the struct bits + struct { + unsigned int dvs : 2; // [1..0] [481..480] + unsigned int reserved : 30; // [31..2] [511..482] + } bits; + + unsigned int value; +} totem_die_id15_t; + +typedef union totem_die_id16 { + // Define the struct bits + struct { + unsigned int reserved : 32; // [31..0] [543..512] + } bits; + + unsigned int value; +} totem_die_id16_t; + +typedef union totem_die_id17 { + // Define the struct bits + struct { + unsigned int avs_domain_num : 4; // [3..0] [547..544] + unsigned int avs_stage_bit : 8; // [11..4] [555..548] + unsigned int avs0_vmin_valid : 2; // [13..12] [557..556] + unsigned int avs0_rcc_valid : 2; // [15..14] [559..558] + unsigned int avs0_valid : 2; // [17..16] [561..560] + unsigned int avs0_hpm_num : 4; // [21..18] [565..562] + unsigned int avs0_hpm0_1st_9_0 : 10; // [31..22] [575..566] + } bits; + + unsigned int value; +} totem_die_id17_t; + +typedef union totem_die_id18 { + // Define the struct bits + struct { + unsigned int avs0_hpm0_1st_19_10 : 10; // [9..0] [585..576] + unsigned int avs0_hpm1_1st : 20; // [29..10] [605..586] + unsigned int avs0_hpm2_1st_1_0 : 2; // [31..30] [607..606] + } bits; + + unsigned int value; +} totem_die_id18_t; + +typedef union totem_die_id19 { + // Define the struct bits + struct { + unsigned int avs0_hpm2_1st_19_2 : 18; // [17..0] [625..608] + unsigned int avs0_hpm3_1st_13_0 : 14; // [31..18] [639..626] + } bits; + + unsigned int value; +} totem_die_id19_t; + +typedef union totem_die_id20 { + // Define the struct bits + struct { + unsigned int avs0_hpm3_1st_19_14 : 6; // [5..0] [645..640] + unsigned int avs0_hpm4_1st : 20; // [25..6] [665..646] + unsigned int avs0_hpm5_1st_5_0 : 6; // [31..26] [671..666] + } bits; + + unsigned int value; +} totem_die_id20_t; + +typedef union totem_die_id21 { + // Define the struct bits + struct { + unsigned int avs0_hpm5_1st_19_6 : 14; // [13..0] [685..673] + unsigned int avs0_hpm6_1st_17_0 : 18; // [31..14] [703..686] + } bits; + + unsigned int value; +} totem_die_id21_t; + +typedef union totem_die_id22 { + // Define the struct bits + struct { + unsigned int avs0_hpm6_1st_19_18 : 2; // [1..0] [705..704] + unsigned int avs0_hpm7_1st : 20; // [21..2] [725..706] + unsigned int avs0_hpm0_2nd_9_0 : 10; // [31..22] [735..726] + } bits; + + unsigned int value; +} totem_die_id22_t; + +typedef union totem_die_id { + struct { + totem_die_id0_t die_id0; + totem_die_id1_t die_id1; + totem_die_id2_t die_id2; + totem_die_id3_t die_id3; + totem_die_id4_t die_id4; + totem_die_id5_t die_id5; + totem_die_id6_t die_id6; + totem_die_id7_t die_id7; + totem_die_id8_t die_id8; + totem_die_id9_t die_id9; + totem_die_id10_t die_id10; + totem_die_id11_t die_id11; + totem_die_id12_t die_id12; + totem_die_id13_t die_id13; + totem_die_id14_t die_id14; + totem_die_id15_t die_id15; + totem_die_id16_t die_id16; + totem_die_id17_t die_id17; + totem_die_id18_t die_id18; + totem_die_id19_t die_id19; + totem_die_id20_t die_id20; + totem_die_id21_t die_id21; + totem_die_id22_t die_id22; + } die_id_bits; + + unsigned int die_id[PLAT_TOTEM_DIE_ID_TOTAL]; +} totem_die_id_t; +#endif + diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ras_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ras_c_union_define.h new file mode 100644 index 000000000..66ddeb518 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ras_c_union_define.h @@ -0,0 +1,295 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : ras_c_union_define.h +// Project line : ICT +// Department : ICT Processor +// Version : V100 +// Date : +// Description : The description of P680 project +// Others : Generated automatically by nManager V5.1 +// ****************************************************************************** + +#ifndef RAS_C_UNION_DEFINE_H +#define RAS_C_UNION_DEFINE_H + +/* Define the union csr_err_mapping_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ0_map_to_fhi_en : 1; /* [0] */ + u32 int_typ0_map_to_eri_en : 1; /* [1] */ + u32 int_typ1_map_to_fhi_en : 1; /* [2] */ + u32 int_typ1_map_to_eri_en : 1; /* [3] */ + u32 int_typ2_map_to_fhi_en : 1; /* [4] */ + u32 int_typ2_map_to_eri_en : 1; /* [5] */ + u32 to_gic_fhi_en : 1; /* [6] */ + u32 rsv_0 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_err_mapping_u; + +/* Define the union csr_int_typ0_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ0_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ0_ena_u; + +/* Define the union csr_int_typ0_ena_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ0_ena_h : 26; /* [25:0] */ + u32 rsv_1 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ0_ena_h_u; + +/* Define the union csr_int_typ1_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ1_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ1_ena_u; + +/* Define the union csr_int_typ1_ena_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ1_ena_h : 26; /* [25:0] */ + u32 rsv_2 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ1_ena_h_u; + +/* Define the union csr_int_typ2_ena_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ2_ena : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ2_ena_u; + +/* Define the union csr_int_typ2_ena_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ2_ena_h : 26; /* [25:0] */ + u32 rsv_3 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ2_ena_h_u; + +/* Define the union csr_int_typ0_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ0_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ0_status_u; + +/* Define the union csr_int_typ0_status_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ0_status_h : 26; /* [25:0] */ + u32 rsv_4 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ0_status_h_u; + +/* Define the union csr_int_typ1_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ1_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ1_status_u; + +/* Define the union csr_int_typ1_status_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ1_status_h : 26; /* [25:0] */ + u32 rsv_5 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ1_status_h_u; + +/* Define the union csr_int_typ2_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ2_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ2_status_u; + +/* Define the union csr_int_typ2_status_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_typ2_status_h : 26; /* [25:0] */ + u32 rsv_6 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_typ2_status_h_u; + +/* Define the union csr_int_node_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_node_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_node_num_u; + +/* Define the union csr_ej_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ej_ctrl_en : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ej_ctrl_u; + +/* Define the union csr_ce_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_ce_cnt_cfg : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ce_cnt_cfg_u; + +/* Define the union csr_int_src_trigger_type_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src_trigger_type_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_src_trigger_type_l_u; + +/* Define the union csr_int_src_trigger_type_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_src_trigger_type_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_src_trigger_type_h_u; + +/* Define the union csr_ras_ctrl_iid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ras_ctrl_iid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ras_ctrl_iid_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_err_mapping_u err_mapping; /* 0 */ + volatile csr_int_typ0_ena_u int_typ0_ena; /* 8 */ + volatile csr_int_typ0_ena_h_u int_typ0_ena_h; /* C */ + volatile csr_int_typ1_ena_u int_typ1_ena; /* 10 */ + volatile csr_int_typ1_ena_h_u int_typ1_ena_h; /* 14 */ + volatile csr_int_typ2_ena_u int_typ2_ena; /* 18 */ + volatile csr_int_typ2_ena_h_u int_typ2_ena_h; /* 1C */ + volatile csr_int_typ0_status_u int_typ0_status; /* 20 */ + volatile csr_int_typ0_status_h_u int_typ0_status_h; /* 24 */ + volatile csr_int_typ1_status_u int_typ1_status; /* 28 */ + volatile csr_int_typ1_status_h_u int_typ1_status_h; /* 2C */ + volatile csr_int_typ2_status_u int_typ2_status; /* 30 */ + volatile csr_int_typ2_status_h_u int_typ2_status_h; /* 34 */ + volatile csr_int_node_num_u int_node_num; /* 38 */ + volatile csr_ej_ctrl_u ej_ctrl; /* 3C */ + volatile csr_ce_cnt_cfg_u ce_cnt_cfg[58]; /* 40 */ + volatile csr_int_src_trigger_type_l_u int_src_trigger_type_l; /* 200 */ + volatile csr_int_src_trigger_type_h_u int_src_trigger_type_h; /* 204 */ + volatile csr_ras_ctrl_iid_u ras_ctrl_iid; /* 210 */ +} S_ras_int_coalesce_REGS_TYPE; + +/* Declare the struct pointor of the module ras_int_coalesce */ +extern volatile S_ras_int_coalesce_REGS_TYPE *gopras_int_coalesceAllReg; + +/* Declare the functions that set the member value */ +int iSetERR_MAPPING_int_typ0_map_to_fhi_en(unsigned int uint_typ0_map_to_fhi_en); +int iSetERR_MAPPING_int_typ0_map_to_eri_en(unsigned int uint_typ0_map_to_eri_en); +int iSetERR_MAPPING_int_typ1_map_to_fhi_en(unsigned int uint_typ1_map_to_fhi_en); +int iSetERR_MAPPING_int_typ1_map_to_eri_en(unsigned int uint_typ1_map_to_eri_en); +int iSetERR_MAPPING_int_typ2_map_to_fhi_en(unsigned int uint_typ2_map_to_fhi_en); +int iSetERR_MAPPING_int_typ2_map_to_eri_en(unsigned int uint_typ2_map_to_eri_en); +int iSetERR_MAPPING_to_gic_fhi_en(unsigned int uto_gic_fhi_en); +int iSetINT_TYP0_ENA_int_typ0_ena(unsigned int uint_typ0_ena); +int iSetINT_TYP0_ENA_H_int_typ0_ena_h(unsigned int uint_typ0_ena_h); +int iSetINT_TYP1_ENA_int_typ1_ena(unsigned int uint_typ1_ena); +int iSetINT_TYP1_ENA_H_int_typ1_ena_h(unsigned int uint_typ1_ena_h); +int iSetINT_TYP2_ENA_int_typ2_ena(unsigned int uint_typ2_ena); +int iSetINT_TYP2_ENA_H_int_typ2_ena_h(unsigned int uint_typ2_ena_h); +int iSetINT_TYP0_STATUS_int_typ0_status(unsigned int uint_typ0_status); +int iSetINT_TYP0_STATUS_H_int_typ0_status_h(unsigned int uint_typ0_status_h); +int iSetINT_TYP1_STATUS_int_typ1_status(unsigned int uint_typ1_status); +int iSetINT_TYP1_STATUS_H_int_typ1_status_h(unsigned int uint_typ1_status_h); +int iSetINT_TYP2_STATUS_int_typ2_status(unsigned int uint_typ2_status); +int iSetINT_TYP2_STATUS_H_int_typ2_status_h(unsigned int uint_typ2_status_h); +int iSetINT_NODE_NUM_int_node_num(unsigned int uint_node_num); +int iSetEJ_CTRL_ej_ctrl_en(unsigned int uej_ctrl_en); +int iSetCE_CNT_CFG_int_ce_cnt_cfg(unsigned int uint_ce_cnt_cfg); +int iSetINT_SRC_TRIGGER_TYPE_L_int_src_trigger_type_l(unsigned int uint_src_trigger_type_l); +int iSetINT_SRC_TRIGGER_TYPE_H_int_src_trigger_type_h(unsigned int uint_src_trigger_type_h); +int iSetRAS_CTRL_IID_ras_ctrl_iid(unsigned int uras_ctrl_iid); + + +#endif // RAS_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ras_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ras_reg_offset.h new file mode 100644 index 000000000..19ecfe234 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/ras_reg_offset.h @@ -0,0 +1,110 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : ras_reg_offset.h +// Project line : ICT +// Department : ICT Processor +// Version : V100 +// Date : +// Description : The description of P680 project +// Others : Generated automatically by nManager V5.1 +// ****************************************************************************** + +#ifndef RAS_REG_OFFSET_H +#define RAS_REG_OFFSET_H + +/* ras_int_coalesce Base address of Module's Register */ +#define CSR_RAS_INT_COALESCE_BASE (0x0) + +/* **************************************************************************** */ +/* ras_int_coalesce Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_RAS_INT_COALESCE_ERR_MAPPING_REG (CSR_RAS_INT_COALESCE_BASE + 0x0) /* 故障输入类型与输出中断的映射 */ +#define CSR_RAS_INT_COALESCE_INT_TYP0_ENA_REG (CSR_RAS_INT_COALESCE_BASE + 0x8) /* 节点31-0的故障输入类型0使能控制 */ +#define CSR_RAS_INT_COALESCE_INT_TYP0_ENA_H_REG (CSR_RAS_INT_COALESCE_BASE + 0xC) /* 节点63-32的故障输入类型0使能控制 \ + */ +#define CSR_RAS_INT_COALESCE_INT_TYP1_ENA_REG (CSR_RAS_INT_COALESCE_BASE + 0x10) /* 节点31-0的故障输入类型1使能控制 */ +#define CSR_RAS_INT_COALESCE_INT_TYP1_ENA_H_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x14) /* 节点63-32的故障输入类型1使能控制 */ +#define CSR_RAS_INT_COALESCE_INT_TYP2_ENA_REG (CSR_RAS_INT_COALESCE_BASE + 0x18) /* 节点31-0的故障输入类型2使能控制 */ +#define CSR_RAS_INT_COALESCE_INT_TYP2_ENA_H_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x1C) /* 节点63-32的故障输入类型2使能控制 */ +#define CSR_RAS_INT_COALESCE_INT_TYP0_STATUS_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x20) /* 节点31-0的故障输入类型0状态标识 */ +#define CSR_RAS_INT_COALESCE_INT_TYP0_STATUS_H_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x24) /* 节点63-32的故障输入类型0状态标识 */ +#define CSR_RAS_INT_COALESCE_INT_TYP1_STATUS_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x28) /* 节点31-0的故障输入类型1状态标识 */ +#define CSR_RAS_INT_COALESCE_INT_TYP1_STATUS_H_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x2C) /* 节点63-32的故障输入类型1状态标识 */ +#define CSR_RAS_INT_COALESCE_INT_TYP2_STATUS_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x30) /* 节点31-0的故障输入类型2状态标识 */ +#define CSR_RAS_INT_COALESCE_INT_TYP2_STATUS_H_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x34) /* 节点63-32的故障输入类型2状态标识 */ +#define CSR_RAS_INT_COALESCE_INT_NODE_NUM_REG (CSR_RAS_INT_COALESCE_BASE + 0x38) /* 节点个数 */ +#define CSR_RAS_INT_COALESCE_EJ_CTRL_REG (CSR_RAS_INT_COALESCE_BASE + 0x3C) /* 故障注入控制 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_0_REG (CSR_RAS_INT_COALESCE_BASE + 0x40) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_1_REG (CSR_RAS_INT_COALESCE_BASE + 0x44) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_2_REG (CSR_RAS_INT_COALESCE_BASE + 0x48) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_3_REG (CSR_RAS_INT_COALESCE_BASE + 0x4C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_4_REG (CSR_RAS_INT_COALESCE_BASE + 0x50) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_5_REG (CSR_RAS_INT_COALESCE_BASE + 0x54) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_6_REG (CSR_RAS_INT_COALESCE_BASE + 0x58) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_7_REG (CSR_RAS_INT_COALESCE_BASE + 0x5C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_8_REG (CSR_RAS_INT_COALESCE_BASE + 0x60) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_9_REG (CSR_RAS_INT_COALESCE_BASE + 0x64) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_10_REG (CSR_RAS_INT_COALESCE_BASE + 0x68) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_11_REG (CSR_RAS_INT_COALESCE_BASE + 0x6C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_12_REG (CSR_RAS_INT_COALESCE_BASE + 0x70) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_13_REG (CSR_RAS_INT_COALESCE_BASE + 0x74) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_14_REG (CSR_RAS_INT_COALESCE_BASE + 0x78) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_15_REG (CSR_RAS_INT_COALESCE_BASE + 0x7C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_16_REG (CSR_RAS_INT_COALESCE_BASE + 0x80) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_17_REG (CSR_RAS_INT_COALESCE_BASE + 0x84) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_18_REG (CSR_RAS_INT_COALESCE_BASE + 0x88) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_19_REG (CSR_RAS_INT_COALESCE_BASE + 0x8C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_20_REG (CSR_RAS_INT_COALESCE_BASE + 0x90) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_21_REG (CSR_RAS_INT_COALESCE_BASE + 0x94) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_22_REG (CSR_RAS_INT_COALESCE_BASE + 0x98) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_23_REG (CSR_RAS_INT_COALESCE_BASE + 0x9C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_24_REG (CSR_RAS_INT_COALESCE_BASE + 0xA0) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_25_REG (CSR_RAS_INT_COALESCE_BASE + 0xA4) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_26_REG (CSR_RAS_INT_COALESCE_BASE + 0xA8) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_27_REG (CSR_RAS_INT_COALESCE_BASE + 0xAC) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_28_REG (CSR_RAS_INT_COALESCE_BASE + 0xB0) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_29_REG (CSR_RAS_INT_COALESCE_BASE + 0xB4) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_30_REG (CSR_RAS_INT_COALESCE_BASE + 0xB8) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_31_REG (CSR_RAS_INT_COALESCE_BASE + 0xBC) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_32_REG (CSR_RAS_INT_COALESCE_BASE + 0xC0) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_33_REG (CSR_RAS_INT_COALESCE_BASE + 0xC4) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_34_REG (CSR_RAS_INT_COALESCE_BASE + 0xC8) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_35_REG (CSR_RAS_INT_COALESCE_BASE + 0xCC) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_36_REG (CSR_RAS_INT_COALESCE_BASE + 0xD0) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_37_REG (CSR_RAS_INT_COALESCE_BASE + 0xD4) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_38_REG (CSR_RAS_INT_COALESCE_BASE + 0xD8) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_39_REG (CSR_RAS_INT_COALESCE_BASE + 0xDC) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_40_REG (CSR_RAS_INT_COALESCE_BASE + 0xE0) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_41_REG (CSR_RAS_INT_COALESCE_BASE + 0xE4) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_42_REG (CSR_RAS_INT_COALESCE_BASE + 0xE8) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_43_REG (CSR_RAS_INT_COALESCE_BASE + 0xEC) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_44_REG (CSR_RAS_INT_COALESCE_BASE + 0xF0) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_45_REG (CSR_RAS_INT_COALESCE_BASE + 0xF4) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_46_REG (CSR_RAS_INT_COALESCE_BASE + 0xF8) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_47_REG (CSR_RAS_INT_COALESCE_BASE + 0xFC) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_48_REG (CSR_RAS_INT_COALESCE_BASE + 0x100) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_49_REG (CSR_RAS_INT_COALESCE_BASE + 0x104) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_50_REG (CSR_RAS_INT_COALESCE_BASE + 0x108) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_51_REG (CSR_RAS_INT_COALESCE_BASE + 0x10C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_52_REG (CSR_RAS_INT_COALESCE_BASE + 0x110) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_53_REG (CSR_RAS_INT_COALESCE_BASE + 0x114) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_54_REG (CSR_RAS_INT_COALESCE_BASE + 0x118) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_55_REG (CSR_RAS_INT_COALESCE_BASE + 0x11C) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_56_REG (CSR_RAS_INT_COALESCE_BASE + 0x120) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_CE_CNT_CFG_57_REG (CSR_RAS_INT_COALESCE_BASE + 0x124) /* 可纠正错计数阈值 */ +#define CSR_RAS_INT_COALESCE_INT_SRC_TRIGGER_TYPE_L_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x200) /* 节点31-0中断源触发类型控制 */ +#define CSR_RAS_INT_COALESCE_INT_SRC_TRIGGER_TYPE_H_REG \ + (CSR_RAS_INT_COALESCE_BASE + 0x204) /* 节点63-32中断源触发类型控制 */ +#define CSR_RAS_INT_COALESCE_RAS_CTRL_IID_REG (CSR_RAS_INT_COALESCE_BASE + 0x210) /* 版本寄存器 */ + +#endif // RAS_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sioe_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sioe_reg_offset.h new file mode 100644 index 000000000..3964ee3a4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sioe_reg_offset.h @@ -0,0 +1,426 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : sioe_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/24 17:39:48 Create file +// ****************************************************************************** + +#ifndef __SIOE_REG_OFFSET_H__ +#define __SIOE_REG_OFFSET_H__ + +#define SIOE_CFG_BASE_ADDR (0x90AC0000ULL) + +/* sioe_cfg_cio Base address of Module's Register */ +#define CSR_SIOE_CFG_CIO_BASE (SIOE_CFG_BASE_ADDR + 0x800) + +/******************************************************************************/ +/* sioe_cfg_cio Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CFG_CIO_CIO_ATB_SEL_REG (CSR_SIOE_CFG_CIO_BASE + 0x0) /* ATB TEST的选择设置 */ +#define CSR_SIOE_CFG_CIO_CIO_TEST_IN_REG (CSR_SIOE_CFG_CIO_BASE + 0x4) /* 预留配置信号 */ +#define CSR_SIOE_CFG_CIO_CIO_TEST_OUT_REG (CSR_SIOE_CFG_CIO_BASE + 0x8) /* 预留输出信号 */ +#define CSR_SIOE_CFG_CIO_CIO_CALIBRATION_EN_REG (CSR_SIOE_CFG_CIO_BASE + 0xC) /* 校准使能 */ +#define CSR_SIOE_CFG_CIO_CIO_CALIBRATION_MODE_REG (CSR_SIOE_CFG_CIO_BASE + 0x10) /* 校准模式选择 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_DRVN_REG (CSR_SIOE_CFG_CIO_BASE + 0x14) /* 高电平输出阻抗手动配置校准字 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_DRVP_REG (CSR_SIOE_CFG_CIO_BASE + 0x18) /* 低电平输出阻抗手动配置校准字 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_ODTN_REG (CSR_SIOE_CFG_CIO_BASE + 0x1C) /* ODT下拉电阻手动配置校准字 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_ODTP_REG (CSR_SIOE_CFG_CIO_BASE + 0x20) /* ODT上拉电阻手动配置校准字 */ +#define CSR_SIOE_CFG_CIO_CIO_CALIBRATION_STEP_REG (CSR_SIOE_CFG_CIO_BASE + 0x24) /* 校准每步等待时间 */ +#define CSR_SIOE_CFG_CIO_CIO_CALIBRATION_INTERVAL_REG (CSR_SIOE_CFG_CIO_BASE + 0x28) /* 定期校准时间 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_DRVN_STABLE_REG (CSR_SIOE_CFG_CIO_BASE + 0x2C) /* 高电平输出阻抗校准值 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_DRVP_STABLE_REG (CSR_SIOE_CFG_CIO_BASE + 0x30) /* 低电平输出阻抗校准值 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_ODTN_STABLE_REG (CSR_SIOE_CFG_CIO_BASE + 0x34) /* ODT下拉电阻校准值 */ +#define CSR_SIOE_CFG_CIO_CIO_CODE_ODTP_STABLE_REG (CSR_SIOE_CFG_CIO_BASE + 0x38) /* ODT上拉电阻校准值 */ +#define CSR_SIOE_CFG_CIO_CIO_CALIBRATION_STATE_REG (CSR_SIOE_CFG_CIO_BASE + 0x3C) /* 校准状态 */ +#define CSR_SIOE_CFG_CIO_CIO_CFG_REG (CSR_SIOE_CFG_CIO_BASE + 0x40) /* 校准软件配置结束标记寄存器 */ +#define CSR_SIOE_CFG_CIO_CIO_STATUS_REG (CSR_SIOE_CFG_CIO_BASE + 0x44) /* 标准配置结束状态指示 */ + +/* sioe_cfg_phy_rx Base address of Module's Register */ +#define CSR_SIOE_CFG_PHY_RX_BASE (SIOE_CFG_BASE_ADDR + 0x500) + +/******************************************************************************/ +/* sioe_cfg_phy_rx Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CFG_PHY_RX_RX_RST_N_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x0) /* DLL软件复位 */ +#define CSR_SIOE_CFG_PHY_RX_RX_LOCK_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x4) /* DLL锁定指示 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DLL_LF_LIMIT_SET_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x8) /* DLL_LF设置 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DLL_LF_LIMIT_OUT_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0xC) /* DLL_LF输出 */ +#define CSR_SIOE_CFG_PHY_RX_RX_ATB_SEL_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x10) /* ATEST的选择设置 */ +#define CSR_SIOE_CFG_PHY_RX_RX_TEST_IN_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x14) /* 预留配置信号 */ +#define CSR_SIOE_CFG_PHY_RX_RX_TEST_OUT_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x18) /* 预留输出信号 */ +#define CSR_SIOE_CFG_PHY_RX_RX_TRIM_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x1C) /* charge pump电流大小 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_COARSE_EN_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x20) /* DESKEW自动校准使能 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_COARSE_STATUS_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x24) /* DESKEW自动校准结果 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_SET_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x28) /* DESKWE配置使能 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_IO_SEL_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x2C) /* DESKEW选择信号 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_IN_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x30) /* 手动配置IO delay调节值 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_PN_SEL_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x34) /* DESKEW输出码字选择 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DESKEW_OUT_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x38) /* DESKEW输出码字 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CP_TEST_IN_DATA_0_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x3C) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CP_TEST_IN_DATA_1_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x40) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CP_TEST_IN_DATA_2_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x44) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CP_TEST_IN_DATA_3_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x48) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_RX_RX_PHYIO_SWITCH_EN_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x4C) /* IO输出使能 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CPM_CFG_0_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x50) /* CPM电路配置寄存器 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CPM_CFG_1_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x54) /* CPM电路配置寄存器 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CPM_CODE_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x58) /* CPM码值输出寄存器 */ +#define CSR_SIOE_CFG_PHY_RX_RX_EYE_TEST_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x5C) /* 眼图测试寄存器 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CIO_CFG_DRVP_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x60) /* CIO接收ODT校准P管结果配置 */ +#define CSR_SIOE_CFG_PHY_RX_RX_CIO_CFG_DRVN_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x64) /* CIO接收ODT校准N管结果配置 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DDR_SEL_MANUAL_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x68) /* TX PHY DDR模型控制使能 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DLL90_NUM_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x6C) /* RX_DLL 90度相位统计周期配置 */ +#define CSR_SIOE_CFG_PHY_RX_RX_DLL90_CNT_REG (CSR_SIOE_CFG_PHY_RX_BASE + 0x70) /* RX_DLL 90度相位统计结果 */ + +/* sioe_cfg_phy_tx Base address of Module's Register */ +#define CSR_SIOE_CFG_PHY_TX_BASE (SIOE_CFG_BASE_ADDR + 0x100) + +/******************************************************************************/ +/* sioe_cfg_phy_tx Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CFG_PHY_TX_TX_RST_N_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x0) /* DLL软件复位 */ +#define CSR_SIOE_CFG_PHY_TX_TX_LOCK_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x4) /* DLL锁定指示 */ +#define CSR_SIOE_CFG_PHY_TX_TX_DLL_MODE_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x8) /* TX DLL工作模式配置寄存器 */ +#define CSR_SIOE_CFG_PHY_TX_TX_DLL_TEST_OUT_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0xC) /* TX侧DLL输出 */ +#define CSR_SIOE_CFG_PHY_TX_TX_DLL_LF_LIMIT_SET_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x10) /* DLL_LF设置 */ +#define CSR_SIOE_CFG_PHY_TX_TX_DLL_LF_LIMIT_OUT_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x14) /* DLL_LF输出 */ +#define CSR_SIOE_CFG_PHY_TX_TX_ATB_SEL_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x18) /* ATE的选择设置 */ +#define CSR_SIOE_CFG_PHY_TX_TX_TEST_IN_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x1C) /* 预留配置信号 */ +#define CSR_SIOE_CFG_PHY_TX_TX_TEST_OUT_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x20) /* 预留输出信号 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CLK_DLY_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x24) /* 发送时钟向后延时大小 */ +#define CSR_SIOE_CFG_PHY_TX_RX_CLK_DLY_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x28) /* 接收时钟向后延时大小 */ +#define CSR_SIOE_CFG_PHY_TX_TX_FOSC_EN_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x2C) /* 发送侧OSC震荡使能 */ +#define CSR_SIOE_CFG_PHY_TX_TX_FOSC_NUM_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x30) /* 分频周期配置寄存器 */ +#define CSR_SIOE_CFG_PHY_TX_TX_FOSC_CNT_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x34) /* 数字分频计数 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CPM_CFG_0_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x38) /* CPM电路配置寄存器 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CPM_CFG_1_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x3C) /* CPM电路配置寄存器 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CPM_CODE_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x40) /* CPM码值输出寄存器 */ +#define CSR_SIOE_CFG_PHY_TX_TX_TRIM_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x44) /* charge pump电流大小 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_L_0_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x48) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_L_1_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x4C) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_L_2_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x50) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_L_3_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x54) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_P2C_DATA_GATING_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x58) /* CP路径gating使能开关 */ +#define CSR_SIOE_CFG_PHY_TX_TX_PHYIO_SWITCH_EN_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x5C) /* 输出信号开关使能 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CIO_CFG_DRVP_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x60) /* CIO发送输出阻搞校准P管结果配置 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CIO_CFG_DRVN_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x64) /* CIO发送输出阻搞校准N管结果配置 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_H_0_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x68) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_H_1_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x6C) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_H_2_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x70) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_CP_TEST_OUT_DATA_H_3_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x74) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_PHY_TX_TX_DDR_SEL_MANUAL_REG (CSR_SIOE_CFG_PHY_TX_BASE + 0x78) /* TX PHY DDR模型控制使能 */ + +/* sioe_cfg_rx Base address of Module's Register */ +#define CSR_SIOE_CFG_RX_BASE (SIOE_CFG_BASE_ADDR + 0x300) + +/******************************************************************************/ +/* sioe_cfg_rx Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CFG_RX_RX_PATTERN_SEL_REG (CSR_SIOE_CFG_RX_BASE + 0x0) /* 测试码型选择 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD3_H_REG (CSR_SIOE_CFG_RX_BASE + 0x4) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD3_L_REG (CSR_SIOE_CFG_RX_BASE + 0x8) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD2_H_REG (CSR_SIOE_CFG_RX_BASE + 0xC) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD2_L_REG (CSR_SIOE_CFG_RX_BASE + 0x10) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD1_H_REG (CSR_SIOE_CFG_RX_BASE + 0x14) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD1_L_REG (CSR_SIOE_CFG_RX_BASE + 0x18) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD0_H_REG (CSR_SIOE_CFG_RX_BASE + 0x1C) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_REG_TEST_WD0_L_REG (CSR_SIOE_CFG_RX_BASE + 0x20) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_RX_RX_TEST_EN_REG (CSR_SIOE_CFG_RX_BASE + 0x24) /* 测试使能 */ +#define CSR_SIOE_CFG_RX_RX_CFG_DESKEW_REG (CSR_SIOE_CFG_RX_BASE + 0x28) /* DESKEW自动校准使能 */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_L_0_REG (CSR_SIOE_CFG_RX_BASE + 0x2C) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_L_1_REG (CSR_SIOE_CFG_RX_BASE + 0x30) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_L_2_REG (CSR_SIOE_CFG_RX_BASE + 0x34) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_L_3_REG (CSR_SIOE_CFG_RX_BASE + 0x38) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_H_0_REG (CSR_SIOE_CFG_RX_BASE + 0x3C) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_H_1_REG (CSR_SIOE_CFG_RX_BASE + 0x40) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_H_2_REG (CSR_SIOE_CFG_RX_BASE + 0x44) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_DATA_MASK_H_3_REG (CSR_SIOE_CFG_RX_BASE + 0x48) /* 数据位MASK */ +#define CSR_SIOE_CFG_RX_RX_VALID_SEL_REG (CSR_SIOE_CFG_RX_BASE + 0x4C) /* RX端valid IO选择 */ +#define CSR_SIOE_CFG_RX_RX_REQ_ACK_CNT_REG (CSR_SIOE_CFG_RX_BASE + 0x50) /* RX端req、ack握手次数 */ +#define CSR_SIOE_CFG_RX_RX_FSM_STATE_REG (CSR_SIOE_CFG_RX_BASE + 0x54) /* RX端状态信号 */ +#define CSR_SIOE_CFG_RX_RX_REQ_DLY_TIME_REG (CSR_SIOE_CFG_RX_BASE + 0x58) /* RX端对req信号打拍延时 */ +#define CSR_SIOE_CFG_RX_RX_DLL_MODE_SEL_REG (CSR_SIOE_CFG_RX_BASE + 0x5C) /* DLL LOCK检测配置 */ +#define CSR_SIOE_CFG_RX_RX_RST_DLL_CFG_REG (CSR_SIOE_CFG_RX_BASE + 0x60) /* 切频期间DLL复位控制 */ +#define CSR_SIOE_CFG_RX_RX_LOCK_DLL_CFG_REG (CSR_SIOE_CFG_RX_BASE + 0x64) /* 等待RX DLL LOCK时间 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_LSB_0_REG (CSR_SIOE_CFG_RX_BASE + 0x68) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_LSB_1_REG (CSR_SIOE_CFG_RX_BASE + 0x6C) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_LSB_2_REG (CSR_SIOE_CFG_RX_BASE + 0x70) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_LSB_3_REG (CSR_SIOE_CFG_RX_BASE + 0x74) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_MSB_0_REG (CSR_SIOE_CFG_RX_BASE + 0x78) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_MSB_1_REG (CSR_SIOE_CFG_RX_BASE + 0x7C) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_MSB_2_REG (CSR_SIOE_CFG_RX_BASE + 0x80) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_L_MSB_3_REG (CSR_SIOE_CFG_RX_BASE + 0x84) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_LSB_0_REG (CSR_SIOE_CFG_RX_BASE + 0x168) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_LSB_1_REG (CSR_SIOE_CFG_RX_BASE + 0x16C) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_LSB_2_REG (CSR_SIOE_CFG_RX_BASE + 0x170) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_LSB_3_REG (CSR_SIOE_CFG_RX_BASE + 0x174) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_MSB_0_REG (CSR_SIOE_CFG_RX_BASE + 0x178) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_MSB_1_REG (CSR_SIOE_CFG_RX_BASE + 0x17C) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_MSB_2_REG (CSR_SIOE_CFG_RX_BASE + 0x180) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_DATA_H_MSB_3_REG (CSR_SIOE_CFG_RX_BASE + 0x184) /* RX CP测试输出端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_IN_CMD_REG (CSR_SIOE_CFG_RX_BASE + 0x88) /* RX CP测试输入端数据 */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_OUT_CMD_REG (CSR_SIOE_CFG_RX_BASE + 0x8C) /* RX CP测试输出端命令IO */ +#define CSR_SIOE_CFG_RX_RX_CP_TEST_EN_REG (CSR_SIOE_CFG_RX_BASE + 0x90) /* RX CP测试使能 */ +#define CSR_SIOE_CFG_RX_RX_TSVIO_SWITCH_EN_REG (CSR_SIOE_CFG_RX_BASE + 0x94) /* IO输出使能 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CFG_0_0_REG (CSR_SIOE_CFG_RX_BASE + 0x98) /* 接收Training配置寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CFG_0_1_REG (CSR_SIOE_CFG_RX_BASE + 0x9C) /* 接收Training配置寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CFG_0_2_REG (CSR_SIOE_CFG_RX_BASE + 0xA0) /* 接收Training配置寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CFG_0_3_REG (CSR_SIOE_CFG_RX_BASE + 0xA4) /* 接收Training配置寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_0_0_REG (CSR_SIOE_CFG_RX_BASE + 0xB4) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_0_1_REG (CSR_SIOE_CFG_RX_BASE + 0xBC) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_0_2_REG (CSR_SIOE_CFG_RX_BASE + 0xC4) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_0_3_REG (CSR_SIOE_CFG_RX_BASE + 0xCC) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_1_0_REG (CSR_SIOE_CFG_RX_BASE + 0xB8) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_1_1_REG (CSR_SIOE_CFG_RX_BASE + 0xC0) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_1_2_REG (CSR_SIOE_CFG_RX_BASE + 0xC8) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_REF_DATA_1_3_REG (CSR_SIOE_CFG_RX_BASE + 0xD0) /* TRAIN测试出错时的参考数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_0_0_REG (CSR_SIOE_CFG_RX_BASE + 0xD4) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_0_1_REG (CSR_SIOE_CFG_RX_BASE + 0xDC) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_0_2_REG (CSR_SIOE_CFG_RX_BASE + 0xE4) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_0_3_REG (CSR_SIOE_CFG_RX_BASE + 0xEC) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_1_0_REG (CSR_SIOE_CFG_RX_BASE + 0xD8) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_1_1_REG (CSR_SIOE_CFG_RX_BASE + 0xE0) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_1_2_REG (CSR_SIOE_CFG_RX_BASE + 0xE8) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CHK_DATA_1_3_REG (CSR_SIOE_CFG_RX_BASE + 0xF0) /* TRAIN测试出错时的错误数据 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_0_0_REG (CSR_SIOE_CFG_RX_BASE + 0xF4) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_0_1_REG (CSR_SIOE_CFG_RX_BASE + 0xFC) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_0_2_REG (CSR_SIOE_CFG_RX_BASE + 0x104) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_0_3_REG (CSR_SIOE_CFG_RX_BASE + 0x10C) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_1_0_REG (CSR_SIOE_CFG_RX_BASE + 0xF8) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_1_1_REG (CSR_SIOE_CFG_RX_BASE + 0x100) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_1_2_REG (CSR_SIOE_CFG_RX_BASE + 0x108) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_DATA_1_3_REG (CSR_SIOE_CFG_RX_BASE + 0x110) /* TRAIN测试出错数据记录 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_CNT_0_REG (CSR_SIOE_CFG_RX_BASE + 0x114) /* TRAIN测试出错次数寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_CNT_1_REG (CSR_SIOE_CFG_RX_BASE + 0x118) /* TRAIN测试出错次数寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_CNT_2_REG (CSR_SIOE_CFG_RX_BASE + 0x11C) /* TRAIN测试出错次数寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_CNT_3_REG (CSR_SIOE_CFG_RX_BASE + 0x120) /* TRAIN测试出错次数寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_TIME_0_REG (CSR_SIOE_CFG_RX_BASE + 0x124) /* TRAIN测试出错时间指示timer */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_TIME_1_REG (CSR_SIOE_CFG_RX_BASE + 0x128) /* TRAIN测试出错时间指示timer */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_TIME_2_REG (CSR_SIOE_CFG_RX_BASE + 0x12C) /* TRAIN测试出错时间指示timer */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_TEST_ERR_TIME_3_REG (CSR_SIOE_CFG_RX_BASE + 0x130) /* TRAIN测试出错时间指示timer */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_STATUS_0_REG (CSR_SIOE_CFG_RX_BASE + 0x134) /* TRAIN测试结果 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_STATUS_1_REG (CSR_SIOE_CFG_RX_BASE + 0x138) /* TRAIN测试结果 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_STATUS_2_REG (CSR_SIOE_CFG_RX_BASE + 0x13C) /* TRAIN测试结果 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_STATUS_3_REG (CSR_SIOE_CFG_RX_BASE + 0x140) /* TRAIN测试结果 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CNT_0_REG (CSR_SIOE_CFG_RX_BASE + 0x144) /* 接收Training次数统计寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CNT_1_REG (CSR_SIOE_CFG_RX_BASE + 0x148) /* 接收Training次数统计寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CNT_2_REG (CSR_SIOE_CFG_RX_BASE + 0x14C) /* 接收Training次数统计寄存器 */ +#define CSR_SIOE_CFG_RX_RX_TRAIN_CNT_3_REG (CSR_SIOE_CFG_RX_BASE + 0x150) /* 接收Training次数统计寄存器 */ +#define CSR_SIOE_CFG_RX_RX_CMD_CFG_LOAD_EN_REG (CSR_SIOE_CFG_RX_BASE + 0x158) /* RX CMD寄存器配置Load使能 */ + +/* sioe_cfg_tx Base address of Module's Register */ +#define CSR_SIOE_CFG_TX_BASE (SIOE_CFG_BASE_ADDR + 0x0) + +/******************************************************************************/ +/* sioe_cfg_tx Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CFG_TX_TX_PATTERN_SEL_REG (CSR_SIOE_CFG_TX_BASE + 0x0) /* 测试码型选择 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_NUM_H_REG (CSR_SIOE_CFG_TX_BASE + 0x4) /* 寄存器码型测试次数 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_NUM_L_REG (CSR_SIOE_CFG_TX_BASE + 0x8) /* 寄存器码型测试次数 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD3_H_REG (CSR_SIOE_CFG_TX_BASE + 0xC) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD3_L_REG (CSR_SIOE_CFG_TX_BASE + 0x10) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD2_H_REG (CSR_SIOE_CFG_TX_BASE + 0x14) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD2_L_REG (CSR_SIOE_CFG_TX_BASE + 0x18) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD1_H_REG (CSR_SIOE_CFG_TX_BASE + 0x1C) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD1_L_REG (CSR_SIOE_CFG_TX_BASE + 0x20) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD0_H_REG (CSR_SIOE_CFG_TX_BASE + 0x24) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_REG_TEST_WD0_L_REG (CSR_SIOE_CFG_TX_BASE + 0x28) /* 寄存器码型测试数据 */ +#define CSR_SIOE_CFG_TX_TX_TEST_EN_REG (CSR_SIOE_CFG_TX_BASE + 0x2C) /* 测试使能 */ +#define CSR_SIOE_CFG_TX_TX_TEST_DONE_REG (CSR_SIOE_CFG_TX_BASE + 0x30) /* 测试结束标示 */ +#define CSR_SIOE_CFG_TX_TX_BACKPRESS_SLLC_REG (CSR_SIOE_CFG_TX_BASE + 0x34) /* 手动反压SLLC TX */ +#define CSR_SIOE_CFG_TX_TX_TEST_VALID_NUM_REG (CSR_SIOE_CFG_TX_BASE + 0x38) /* valid高低电平持续周期数 */ +#define CSR_SIOE_CFG_TX_TX_DESKEW_EN_REG (CSR_SIOE_CFG_TX_BASE + 0x3C) /* DESKEW操作使能 */ +#define CSR_SIOE_CFG_TX_TX_DESKEW_LENGTH_REG (CSR_SIOE_CFG_TX_BASE + 0x40) /* deskew序列长度 */ +#define CSR_SIOE_CFG_TX_TX_DESKEW_INTERVAL_REG (CSR_SIOE_CFG_TX_BASE + 0x44) /* 间插deskew间隔时间 */ +#define CSR_SIOE_CFG_TX_TX_DESKEW_CODE_REG (CSR_SIOE_CFG_TX_BASE + 0x48) /* deskew码型数据 */ +#define CSR_SIOE_CFG_TX_TX_SLLC_FIFO_EMPTY_TIME_REG (CSR_SIOE_CFG_TX_BASE + 0x4C) /* 等待sllc内部fifo为空 */ +#define CSR_SIOE_CFG_TX_TX_CRG_SWITCH_TIME_REG (CSR_SIOE_CFG_TX_BASE + 0x50) /* sioe发出切换DLL命令后到告诉CRG切频的时间 */ +#define CSR_SIOE_CFG_TX_TX_DLL_MODE_SEL_REG (CSR_SIOE_CFG_TX_BASE + 0x54) /* DLL模式选择开关与DLL LOCK检测配置 */ +#define CSR_SIOE_CFG_TX_TX_RST_DLL_CFG_REG (CSR_SIOE_CFG_TX_BASE + 0x58) /* 切频期间DLL复位控制 */ +#define CSR_SIOE_CFG_TX_TX_LOCK_DLL_CFG_REG (CSR_SIOE_CFG_TX_BASE + 0x5C) /* 手动配置等待DLL LOCK时间 */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_L_0_REG (CSR_SIOE_CFG_TX_BASE + 0x60) /* 数据位MASK */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_L_1_REG (CSR_SIOE_CFG_TX_BASE + 0x64) /* 数据位MASK */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_L_2_REG (CSR_SIOE_CFG_TX_BASE + 0x68) /* 数据位MASK */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_L_3_REG (CSR_SIOE_CFG_TX_BASE + 0x6C) /* 数据位MASK */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_H_0_REG (CSR_SIOE_CFG_TX_BASE + 0x70) /* 保留寄存器 */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_H_1_REG (CSR_SIOE_CFG_TX_BASE + 0x74) /* 保留寄存器 */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_H_2_REG (CSR_SIOE_CFG_TX_BASE + 0x78) /* 保留寄存器 */ +#define CSR_SIOE_CFG_TX_TX_DATA_MASK_H_3_REG (CSR_SIOE_CFG_TX_BASE + 0x7C) /* 保留寄存器 */ +#define CSR_SIOE_CFG_TX_TX_VALID_SEL_REG (CSR_SIOE_CFG_TX_BASE + 0x80) /* valid IO选择、valid 统计选择 */ +#define CSR_SIOE_CFG_TX_TX_REQ_ACK_CNT_REG (CSR_SIOE_CFG_TX_BASE + 0x84) /* TX端req-ack握手次数 */ +#define CSR_SIOE_CFG_TX_TX_FSM_STATE_REG (CSR_SIOE_CFG_TX_BASE + 0x88) /* TX端所有状态机状态 */ +#define CSR_SIOE_CFG_TX_TX_BACKPRESS_FLAG_REG (CSR_SIOE_CFG_TX_BASE + 0x8C) /* TX端反压信号 */ +#define CSR_SIOE_CFG_TX_TX_CRG_SWITCH_EN_REG (CSR_SIOE_CFG_TX_BASE + 0x90) /* 手动配置CRG开关使能 */ +#define CSR_SIOE_CFG_TX_TX_CRG_CFG_REG (CSR_SIOE_CFG_TX_BASE + 0x94) /* CRG时钟切换配置寄存器 */ +#define CSR_SIOE_CFG_TX_TX_CRG_STATUS_REG (CSR_SIOE_CFG_TX_BASE + 0x98) /* CRG时钟切换状态寄存器 */ +#define CSR_SIOE_CFG_TX_TX_MODE_STATUS_REG (CSR_SIOE_CFG_TX_BASE + 0x9C) /* 发送模式切换状态寄存器 */ +#define CSR_SIOE_CFG_TX_TX_CP_TEST_OUT_CMD_REG (CSR_SIOE_CFG_TX_BASE + 0xA0) /* TX CP测试输出端命令IO */ +#define CSR_SIOE_CFG_TX_TX_CP_TEST_IN_CMD_REG (CSR_SIOE_CFG_TX_BASE + 0xA4) /* TX CP测试输入端数据 */ +#define CSR_SIOE_CFG_TX_TX_CP_TEST_IN_DATA_L_REG (CSR_SIOE_CFG_TX_BASE + 0xA8) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_TX_TX_CP_TEST_IN_DATA_H_REG (CSR_SIOE_CFG_TX_BASE + 0xAC) /* TX CP测试输出端数据 */ +#define CSR_SIOE_CFG_TX_TX_CP_TEST_EN_REG (CSR_SIOE_CFG_TX_BASE + 0xB0) /* TX CP测试使能 */ +#define CSR_SIOE_CFG_TX_TX_TSVIO_SWITCH_EN_REG (CSR_SIOE_CFG_TX_BASE + 0xB4) /* 输出信号开关使能 */ +#define CSR_SIOE_CFG_TX_TX_PACKAGE_MODE_REG (CSR_SIOE_CFG_TX_BASE + 0xB8) /* 封装模式选择 */ +#define CSR_SIOE_CFG_TX_TX_TRAIN_CFG_0_REG (CSR_SIOE_CFG_TX_BASE + 0xBC) /* 发送Training配置寄存器 */ +#define CSR_SIOE_CFG_TX_TX_TRAIN_CFG_1_REG (CSR_SIOE_CFG_TX_BASE + 0xC0) /* 发送Training配置寄存器 */ +#define CSR_SIOE_CFG_TX_TX_TRAIN_STATUS_REG (CSR_SIOE_CFG_TX_BASE + 0xCC) /* 发送Training状态寄存器 */ +#define CSR_SIOE_CFG_TX_TX_TRAIN_CNT_REG (CSR_SIOE_CFG_TX_BASE + 0xD0) /* 发送Training次数统计寄存器 */ +#define CSR_SIOE_CFG_TX_TX_CFG_DESKEW_OVERTIME_REG (CSR_SIOE_CFG_TX_BASE + 0xD8) /* 发送deskew命令超时配置寄存器 */ +#define CSR_SIOE_CFG_TX_TX_CFG_FREQCH_OVERTIME_REG (CSR_SIOE_CFG_TX_BASE + 0xDC) /* 发送切频命令超时配置寄存器 */ +#define CSR_SIOE_CFG_TX_SIOE_INT_SRC_REG (CSR_SIOE_CFG_TX_BASE + 0xE0) /* 中断源寄存器 */ +#define CSR_SIOE_CFG_TX_SIOE_INT_MASK_REG (CSR_SIOE_CFG_TX_BASE + 0xE4) /* 中断屏蔽寄存器 */ +#define CSR_SIOE_CFG_TX_SIOE_INT_STS_REG (CSR_SIOE_CFG_TX_BASE + 0xE8) /* 中断状态寄存器 */ +#define CSR_SIOE_CFG_TX_SIOE_INT_CLR_REG (CSR_SIOE_CFG_TX_BASE + 0xEC) /* 中断源清除寄存器 */ +#define CSR_SIOE_CFG_TX_SIOE_SYS_MAGIC_WORD_REG (CSR_SIOE_CFG_TX_BASE + 0x7F0) /* SIOE_SYS_MAGIC_WORD动态配置 */ +#define CSR_SIOE_CFG_TX_SIOE_ECO0_REG (CSR_SIOE_CFG_TX_BASE + 0xC00) /* ECO寄存器0 */ +#define CSR_SIOE_CFG_TX_SIOE_ECO1_REG (CSR_SIOE_CFG_TX_BASE + 0xC04) /* ECO寄存器1 */ +#define CSR_SIOE_CFG_TX_SIOE_ECO2_REG (CSR_SIOE_CFG_TX_BASE + 0xC08) /* ECO寄存器2 */ +#define CSR_SIOE_CFG_TX_SIOE_ECO3_REG (CSR_SIOE_CFG_TX_BASE + 0xC0C) /* ECO寄存器3 */ +#define CSR_SIOE_CFG_TX_SIOE_SYS_VERSION_REG (CSR_SIOE_CFG_TX_BASE + 0xC10) /* SIOE_SYS_VERSION */ + +/* sioe_cnt_cio Base address of Module's Register */ +#define CSR_SIOE_CNT_CIO_BASE (SIOE_CFG_BASE_ADDR + 0xD00) + +/******************************************************************************/ +/* sioe_cnt_cio Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CNT_CIO_CIO_CALIBRATION_FAIL_REG (CSR_SIOE_CNT_CIO_BASE + 0x0) /* 校准状态 */ + +/* sioe_cnt_rx Base address of Module's Register */ +#define CSR_SIOE_CNT_RX_BASE (SIOE_CFG_BASE_ADDR + 0xB00) + +/******************************************************************************/ +/* sioe_cnt_rx Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_LSB_0_REG (CSR_SIOE_CNT_RX_BASE + 0x0) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_LSB_1_REG (CSR_SIOE_CNT_RX_BASE + 0x4) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_LSB_2_REG (CSR_SIOE_CNT_RX_BASE + 0x8) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_LSB_3_REG (CSR_SIOE_CNT_RX_BASE + 0xC) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_MSB_0_REG (CSR_SIOE_CNT_RX_BASE + 0x10) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_MSB_1_REG (CSR_SIOE_CNT_RX_BASE + 0x14) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_MSB_2_REG (CSR_SIOE_CNT_RX_BASE + 0x18) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_L_MSB_3_REG (CSR_SIOE_CNT_RX_BASE + 0x1C) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_LSB_0_REG (CSR_SIOE_CNT_RX_BASE + 0x300) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_LSB_1_REG (CSR_SIOE_CNT_RX_BASE + 0x304) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_LSB_2_REG (CSR_SIOE_CNT_RX_BASE + 0x308) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_LSB_3_REG (CSR_SIOE_CNT_RX_BASE + 0x30C) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_MSB_0_REG (CSR_SIOE_CNT_RX_BASE + 0x310) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_MSB_1_REG (CSR_SIOE_CNT_RX_BASE + 0x314) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_MSB_2_REG (CSR_SIOE_CNT_RX_BASE + 0x318) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_DATA_H_MSB_3_REG (CSR_SIOE_CNT_RX_BASE + 0x31C) /* BIST测试数据错误指示位 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0x20) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0x28) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0x30) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0x38) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0x24) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0x2C) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0x34) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_CNT_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0x3C) /* BIST测试数据错误包个数 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_SEL_0_REG (CSR_SIOE_CNT_RX_BASE + 0x40) /* 打印BIST测试错误数据选择 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_SEL_1_REG (CSR_SIOE_CNT_RX_BASE + 0x44) /* 打印BIST测试错误数据选择 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_SEL_2_REG (CSR_SIOE_CNT_RX_BASE + 0x48) /* 打印BIST测试错误数据选择 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_SEL_3_REG (CSR_SIOE_CNT_RX_BASE + 0x4C) /* 打印BIST测试错误数据选择 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0x50) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0x58) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0x60) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0x68) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0x54) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0x5C) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0x64) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_L_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0x6C) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0x350) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0x358) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0x360) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0x368) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0x354) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0x35C) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0x364) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_REF_DATA_H_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0x36C) /* BIST测试参考数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0x70) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0x78) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0x80) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0x88) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0x74) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0x7C) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0x84) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_L_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0x8C) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0x172) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0x17A) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0x182) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0x18A) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0x374) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0x37C) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0x384) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_CHK_DATA_H_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0x38C) /* 接收到的BIST测试数据 */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0x90) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0x98) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0xA0) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0xA8) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0x94) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0x9C) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0xA4) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_BIST_TEST_ERR_TIME_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0xAC) /* BIST测试出错时间指示timer */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_0_0_REG (CSR_SIOE_CNT_RX_BASE + 0xB0) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_0_1_REG (CSR_SIOE_CNT_RX_BASE + 0xB8) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_0_2_REG (CSR_SIOE_CNT_RX_BASE + 0xC0) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_0_3_REG (CSR_SIOE_CNT_RX_BASE + 0xC8) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_1_0_REG (CSR_SIOE_CNT_RX_BASE + 0xB4) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_1_1_REG (CSR_SIOE_CNT_RX_BASE + 0xBC) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_1_2_REG (CSR_SIOE_CNT_RX_BASE + 0xC4) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_VALID_CNT_1_3_REG (CSR_SIOE_CNT_RX_BASE + 0xCC) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_RX_RX_DLL_LOCK_CNT_REG (CSR_SIOE_CNT_RX_BASE + 0xD0) /* 接收DLL Lock锁定次数统计 */ +#define CSR_SIOE_CNT_RX_RX_DLL_UNLOCK_CNT_REG (CSR_SIOE_CNT_RX_BASE + 0xD4) /* 接收DLL UnLock锁定次数统计 */ +#define CSR_SIOE_CNT_RX_RX_DLL_LOCK_DET_CNT_REG (CSR_SIOE_CNT_RX_BASE + 0xD8) /* 接收DLL Lock时间检测 */ +#define CSR_SIOE_CNT_RX_RX_DLL_LOCK_DET_STATE_REG (CSR_SIOE_CNT_RX_BASE + 0xDC) /* 接收DLL Lock检测状态指示 */ +#define CSR_SIOE_CNT_RX_RX_CNT_CLR_CE_REG (CSR_SIOE_CNT_RX_BASE + 0xF0) /* CNT_CYC类型寄存器读清控制信号 */ + +/* sioe_cnt_tx Base address of Module's Register */ +#define CSR_SIOE_CNT_TX_BASE (SIOE_CFG_BASE_ADDR + 0x900) + +/******************************************************************************/ +/* sioe_cnt_tx Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_0_0_REG (CSR_SIOE_CNT_TX_BASE + 0x0) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_0_1_REG (CSR_SIOE_CNT_TX_BASE + 0x8) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_0_2_REG (CSR_SIOE_CNT_TX_BASE + 0x10) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_0_3_REG (CSR_SIOE_CNT_TX_BASE + 0x18) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_1_0_REG (CSR_SIOE_CNT_TX_BASE + 0x4) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_1_1_REG (CSR_SIOE_CNT_TX_BASE + 0xC) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_1_2_REG (CSR_SIOE_CNT_TX_BASE + 0x14) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_VALID_CNT_1_3_REG (CSR_SIOE_CNT_TX_BASE + 0x1C) /* valid数量统计计数器 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_START_CNT_0_REG (CSR_SIOE_CNT_TX_BASE + 0x20) /* 间插deskew启动次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_START_CNT_1_REG (CSR_SIOE_CNT_TX_BASE + 0x24) /* 间插deskew启动次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_START_CNT_2_REG (CSR_SIOE_CNT_TX_BASE + 0x28) /* 间插deskew启动次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_START_CNT_3_REG (CSR_SIOE_CNT_TX_BASE + 0x2C) /* 间插deskew启动次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_END_CNT_0_REG (CSR_SIOE_CNT_TX_BASE + 0x30) /* 间插deskew结束次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_END_CNT_1_REG (CSR_SIOE_CNT_TX_BASE + 0x34) /* 间插deskew结束次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_END_CNT_2_REG (CSR_SIOE_CNT_TX_BASE + 0x38) /* 间插deskew结束次数 */ +#define CSR_SIOE_CNT_TX_TX_DESKEW_END_CNT_3_REG (CSR_SIOE_CNT_TX_BASE + 0x3C) /* 间插deskew结束次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_START_CNT_0_REG (CSR_SIOE_CNT_TX_BASE + 0x40) /* 自动切频操作启动次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_START_CNT_1_REG (CSR_SIOE_CNT_TX_BASE + 0x44) /* 自动切频操作启动次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_START_CNT_2_REG (CSR_SIOE_CNT_TX_BASE + 0x48) /* 自动切频操作启动次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_START_CNT_3_REG (CSR_SIOE_CNT_TX_BASE + 0x4C) /* 自动切频操作启动次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_END_CNT_0_REG (CSR_SIOE_CNT_TX_BASE + 0x50) /* 自动切频操作结束次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_END_CNT_1_REG (CSR_SIOE_CNT_TX_BASE + 0x54) /* 自动切频操作结束次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_END_CNT_2_REG (CSR_SIOE_CNT_TX_BASE + 0x58) /* 自动切频操作结束次数 */ +#define CSR_SIOE_CNT_TX_TX_FREQ_END_CNT_3_REG (CSR_SIOE_CNT_TX_BASE + 0x5C) /* 自动切频操作结束次数 */ +#define CSR_SIOE_CNT_TX_TX_MODE_REG (CSR_SIOE_CNT_TX_BASE + 0x60) /* TX工作模式选择 */ +#define CSR_SIOE_CNT_TX_TX_SLOW_MODE_EN_REG (CSR_SIOE_CNT_TX_BASE + 0x64) /* 保留寄存器 */ +#define CSR_SIOE_CNT_TX_TX_DLL_LOCK_CNT_REG (CSR_SIOE_CNT_TX_BASE + 0x68) /* 发送DLL Lock锁定次数统计 */ +#define CSR_SIOE_CNT_TX_TX_DLL_UNLOCK_CNT_REG (CSR_SIOE_CNT_TX_BASE + 0x6C) /* 发送DLL UnLock锁定次数统计 */ +#define CSR_SIOE_CNT_TX_TX_DLL_LOCK_DET_CNT_REG (CSR_SIOE_CNT_TX_BASE + 0x70) /* 发送DLL Lock时间检测 */ +#define CSR_SIOE_CNT_TX_TX_DLL_LOCK_DET_STATE_REG (CSR_SIOE_CNT_TX_BASE + 0x74) /* 发送DLL Lock检测状态指示 */ +#define CSR_SIOE_CNT_TX_TX_CNT_CLR_CE_REG (CSR_SIOE_CNT_TX_BASE + 0xF0) /* CNT_CYC类型寄存器读清控制信号 */ + +#endif // __HI1823E_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sllc_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sllc_reg_offset.h new file mode 100644 index 000000000..19a1f5623 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sllc_reg_offset.h @@ -0,0 +1,150 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : sllc_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/24 17:39:48 Create file +// ****************************************************************************** + +#ifndef __SLLC_REG_OFFSET_H__ +#define __SLLC_REG_OFFSET_H__ + +#define SLLC_CFG_BASE_ADDR (0x90A80000ULL) + +/* sllc_core_regs Base address of Module's Register */ +#define CSR_SLLC_CORE_REGS_BASE (SLLC_CFG_BASE_ADDR) + +/******************************************************************************/ +/* sllc_core_regs Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SLLC_CORE_REGS_SLLC_LINK_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x0) /* SLLC断链配置静态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_FLITPEND_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x100) /* SLLC调度配置（是否看flitpend提前调度） */ +#define CSR_SLLC_CORE_REGS_SLLC_SCH_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x200) /* SLLC PHY Tx进行Flit调度时，各个通道的权重配置动态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_CRD_RET_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x480) /* 控制本端SLLC返还credit给对端SLLC静态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_FLITPEND_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x600) /* 强行拉高Skyros Tx的flitpend */ +#define CSR_SLLC_CORE_REGS_SLLC_PG_ID_TRANS_EN_REG (CSR_SLLC_CORE_REGS_BASE + 0x680) /* 对于去本Totem L3T/L3D的req pkt，配置是否对tgtid进行partial good转换 */ +#define CSR_SLLC_CORE_REGS_SLLC_THROTTLE_CONTINUOUS_TH_LOW_REG (CSR_SLLC_CORE_REGS_BASE + 0x700) /* THROTTLE_CONTINUOUS低水线配置（SLLC接收来自Ring的报文的能力低于低水线，触发Ring的持续反压）静态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_THROTTLE_CONTINUOUS_TH_HIGH_REG (CSR_SLLC_CORE_REGS_BASE + 0x704) /* THROTTLE_CONTINUOUS高水线配置（SLLC接收来自Ring的报文的能力高于高水线，解除Ring的持续反压）静态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_THROTTLE_PERIODIC_TH_LOW_REG (CSR_SLLC_CORE_REGS_BASE + 0x708) /* THROTTLE_PERIODIC低水线配置（SLLC缓存发往Ring的报文的能力低于低水线，触发Ring的周期性反压）静态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_THROTTLE_PERIODIC_TH_HIGH_REG (CSR_SLLC_CORE_REGS_BASE + 0x70C) /* THROTTLE_PERIODIC高水线配置（SLLC缓存发往Ring的报文的能力高于高水线，解除Ring的周期性反压）静态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_MSG_CFG0_REG (CSR_SLLC_CORE_REGS_BASE + 0x780) /* SLLC消息传递配置0动态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_MSG_CFG1_REG (CSR_SLLC_CORE_REGS_BASE + 0x784) /* SLLC消息传递配置1动态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_SYS_MAGIC_WORD_REG (CSR_SLLC_CORE_REGS_BASE + 0x7F0) /* SLLC_SYS_MAGIC_WORD动态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_INT0_SRC_REG (CSR_SLLC_CORE_REGS_BASE + 0x800) /* 原始中断状态（屏蔽前）此处的中断都认为是致命错误，即FE中断（除了int_phy_rx_flit_1bit_ecc_err是可恢复错误，即CE中断）。 */ +#define CSR_SLLC_CORE_REGS_SLLC_INT0_MSK_REG (CSR_SLLC_CORE_REGS_BASE + 0x804) /* 中断屏蔽动态配置软件在上电复位后，请先清中断，再关闭中断屏蔽。 */ +#define CSR_SLLC_CORE_REGS_SLLC_INT0_ST_REG (CSR_SLLC_CORE_REGS_BASE + 0x808) /* 中断状态（屏蔽后） */ +#define CSR_SLLC_CORE_REGS_SLLC_INT0_CLR_REG (CSR_SLLC_CORE_REGS_BASE + 0x80C) /* 中断清除动态写1清零软件在上电复位后，请先清中断。 */ +#define CSR_SLLC_CORE_REGS_SLLC_ECO0_REG (CSR_SLLC_CORE_REGS_BASE + 0xC00) /* ECO寄存器0 */ +#define CSR_SLLC_CORE_REGS_SLLC_ECO1_REG (CSR_SLLC_CORE_REGS_BASE + 0xC04) /* ECO寄存器1 */ +#define CSR_SLLC_CORE_REGS_SLLC_ECO2_REG (CSR_SLLC_CORE_REGS_BASE + 0xC08) /* ECO寄存器2注意：Hi1383 Infinite SLLC中此寄存器有特殊作用。 */ +#define CSR_SLLC_CORE_REGS_SLLC_ECO3_REG (CSR_SLLC_CORE_REGS_BASE + 0xC0C) /* ECO寄存器3 */ +#define CSR_SLLC_CORE_REGS_SLLC_SYS_VERSION_REG (CSR_SLLC_CORE_REGS_BASE + 0xC10) /* SLLC_SYS_VERSION */ +#define CSR_SLLC_CORE_REGS_SLLC_CORE_CNT_EN_REG (CSR_SLLC_CORE_REGS_BASE + 0x1040) /* DFX配置动态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_CORE_CNT_CLR_REG (CSR_SLLC_CORE_REGS_BASE + 0x1044) /* DFX配置（该寄存器只在样片定位时使用，其他时候请不要配置）动态配置 */ +#define CSR_SLLC_CORE_REGS_SLLC_LINK_ST_REG (CSR_SLLC_CORE_REGS_BASE + 0x1100) /* SLLC断链状态 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_CRD_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1240) /* SLLC Skyros Rx的L-Credit数量 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_FIFO_POS_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1244) /* SLLC Skyros Rx的的FIFO空位 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_FIFO_ST_REG (CSR_SLLC_CORE_REGS_BASE + 0x1248) /* SLLC Skyros Rx中，缓存Skyros Packet的同步FIFO（来自Ring Skyros Tx） */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_REQ_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1280) /* SLLC Skyros Rx接收Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_SNP_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1288) /* SLLC Skyros Rx接收Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_RSP_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1290) /* SLLC Skyros Rx接收Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_DAT_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1298) /* SLLC Skyros Rx接收Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_REQ_FIFO_FULL_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x12A0) /* SLLC Skyros Rx缓存Ring Packet的FIFO的写满计数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满终止 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_SNP_FIFO_FULL_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x12A8) /* SLLC Skyros Rx缓存Ring Packet的FIFO的写满计数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_RSP_FIFO_FULL_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x12B0) /* SLLC Skyros Rx缓存Ring Packet的FIFO的写满计数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_RX_DAT_FIFO_FULL_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x12B8) /* SLLC Skyros Rx缓存Ring Packet的FIFO的写满计数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_TX_CRD_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1440) /* SLLC PHY Tx的credit数量 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_TX_REQ_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1480) /* PHY Tx发送Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_TX_SNP_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1488) /* PHY Tx发送Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_TX_RSP_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1490) /* PHY Tx发送Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_TX_DAT_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1498) /* PHY Tx发送Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_TX_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x14A0) /* PHY Tx发送Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_CRD_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1540) /* SLLC PHY Rx的credit数量 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_REQ_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1580) /* PHY Rx接收Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_SNP_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1588) /* PHY Rx接收Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_RSP_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1590) /* PHY Rx接收Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_DAT_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1598) /* PHY Rx接收Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_FLIT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x15A0) /* PHY Rx接收Flit计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_PHY_RX_FLIT_1BIT_ECC_ERR_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x15E0) /* PHY Rx接收Flit中出现1bit ECC的次数不受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_RING_CRD_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1740) /* SLLC Skyros Tx的L-Credit数量（上ring环） */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_FASTJUMP_CRD_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1744) /* SLLC Skyros Tx的L-Credit数量（不上ring环，快跳到另一个sllc） */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_FIFO_POS_NUM_REG (CSR_SLLC_CORE_REGS_BASE + 0x1748) /* SLLC Skyros Tx的FIFO空位 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_FIFO_ST_REG (CSR_SLLC_CORE_REGS_BASE + 0x174C) /* SLLC Skyros Tx中，缓存Skyros Packet的同步FIFO（发往Ring Skyros Tx） */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_REQ_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1780) /* SLLC Skyros Tx发送Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_SNP_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1788) /* SLLC Skyros Tx发送Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_RSP_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1790) /* SLLC Skyros Tx发送Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_SKY_TX_DAT_PKT_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1798) /* SLLC Skyros Tx发送Packet计数器受sllc_core_cnt_en控制不受sllc_core_cnt_clr控制溢出卷绕 */ +#define CSR_SLLC_CORE_REGS_SLLC_REQ_THROTTLE_CONTINUOUS_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1880) /* SLLC指示本DIE的RING进行持续VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_SNP_THROTTLE_CONTINUOUS_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1888) /* SLLC指示本DIE的RING进行持续VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_RSP_THROTTLE_CONTINUOUS_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1890) /* SLLC指示本DIE的RING进行持续VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_DAT_THROTTLE_CONTINUOUS_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1898) /* SLLC指示本DIE的RING进行持续VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_REQ_THROTTLE_PERIODIC_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x18A0) /* SLLC指示本DIE的RING进行周期性VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_SNP_THROTTLE_PERIODIC_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x18A8) /* SLLC指示本DIE的RING进行周期性VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_RSP_THROTTLE_PERIODIC_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x18B0) /* SLLC指示本DIE的RING进行周期性VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_SLLC_DAT_THROTTLE_PERIODIC_CNT_REG (CSR_SLLC_CORE_REGS_BASE + 0x18B8) /* SLLC指示本DIE的RING进行周期性VC反压的次数受sllc_core_cnt_en控制受sllc_core_cnt_clr控制计满保持 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_EN_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A00) /* RingBIST 发送使能 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_NUM_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A04) /* RingBIST发包数量寄存器低32位 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_NUM_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A08) /* RingBIST发包数量寄存器高32位 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_CTRL_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A0C) /* RingBIST发包控制寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_FLIT_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A10) /* RingBIST发包FlIT控制寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_FINISH_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A14) /* RingBIST发包结束指示寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_REQ_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A18) /* RingBIST REQ通道未发送低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_REQ_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A1C) /* RingBIST REQ通道未发送高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_RSP_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A20) /* RingBIST RSP通道未发送低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_RSP_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A24) /* RingBIST RSP通道未发送高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_SNP_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A28) /* RingBIST SNP通道未发送低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_SNP_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A2C) /* RingBIST SNP通道未发送高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_DAT_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A30) /* RingBIST DAT通道未发送低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_SEND_DAT_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A34) /* RingBIST DAT通道未发送高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_EN_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A38) /* RingBIST接收使能寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_NUM_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A3C) /* RingBIST收包数量寄存器低32位 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_NUM_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A40) /* RingBIST收包数量寄存器高32位 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_CTRL_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A44) /* RingBIST收包控制寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_FLIT_CFG_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A48) /* RingBIST收到FLIT控制寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_RESULT_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A4C) /* RingBIST收包比对结果寄存器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_REQ_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A50) /* RingBIST REQ通道未接收低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_REQ_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A54) /* RingBIST REQ通道未接收高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_RSP_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A58) /* RingBIST RSP通道未接收低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_RSP_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A5C) /* RingBIST RSP通道未接收高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_SNP_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A60) /* RingBIST SNP通道未接收低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_SNP_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A64) /* RingBIST SNP通道未接收高位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_DAT_CNT_L_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A68) /* RingBIST DAT通道未接收低位计数器 */ +#define CSR_SLLC_CORE_REGS_RING_BIST_RCV_DAT_CNT_H_REG (CSR_SLLC_CORE_REGS_BASE + 0x1A6C) /* RingBIST DAT通道未接收高位计数器 */ + +/* sllc_phy_regs Base address of Module's Register */ +#define CSR_SLLC_PHY_REGS_BASE (SLLC_CFG_BASE_ADDR) + +/******************************************************************************/ +/* sllc_phy_regs Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_ASYNC_MODE_CFG_REG (CSR_SLLC_PHY_REGS_BASE + 0x4400) /* SLLC PHY Rx异步处理模式配置动态配置（请参考FS中的流程说明） */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_ASYNC_MODE_SWITCH_PERIOD_REG (CSR_SLLC_PHY_REGS_BASE + 0x4404) /* SLLC PHY Rx异步处理模式切换时间配置静态配置 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_CFG0_REG (CSR_SLLC_PHY_REGS_BASE + 0x4500) /* SLLC PHY Rx源同步FIFO相关配置动态配置（请参考FS中的流程说明）注意：如果SLLC PHY RX工作在“源同步FIFO模式”，禁止重复配置phy_rx_train_start为1。 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_CFG1_REG (CSR_SLLC_PHY_REGS_BASE + 0x4504) /* SLLC PHY Rx源同步FIFO工作模式配置静态配置 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_CFG2_REG (CSR_SLLC_PHY_REGS_BASE + 0x4508) /* SLLC PHY Rx源同步FIFO工作模式配置静态配置 */ +#define CSR_SLLC_PHY_REGS_SLLC_INT1_SRC_REG (CSR_SLLC_PHY_REGS_BASE + 0x4810) /* 原始中断状态（屏蔽前）此处的中断都认为是致命错误（FE中断）。 */ +#define CSR_SLLC_PHY_REGS_SLLC_INT1_MSK_REG (CSR_SLLC_PHY_REGS_BASE + 0x4814) /* 中断屏蔽动态配置软件在上电复位后，请先清中断，再关闭中断屏蔽。 */ +#define CSR_SLLC_PHY_REGS_SLLC_INT1_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x4818) /* 中断状态（屏蔽后） */ +#define CSR_SLLC_PHY_REGS_SLLC_INT1_CLR_REG (CSR_SLLC_PHY_REGS_BASE + 0x481C) /* 中断清除动态写1清零软件在上电复位后，请先清中断。 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_CNT_EN_REG (CSR_SLLC_PHY_REGS_BASE + 0x5040) /* DFX配置动态配置 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_CNT_CLR_REG (CSR_SLLC_PHY_REGS_BASE + 0x5044) /* DFX配置（该寄存器只在样片定位时使用，其他时候请不要配置）动态配置 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_DATA_SEL_REG (CSR_SLLC_PHY_REGS_BASE + 0x5400) /* SLLC PHY Rx相关状态 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_TX_ASYNC_FIFO_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5444) /* SLLC PHY Tx中，低带宽模式下用于异步转换的异步FIFO */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5500) /* SLLC PHY Rx相关状态 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_ASYNC_FIFO_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5544) /* SLLC PHY Rx中，异步FIFO模式下用于异步转换的异步FIFO，分别对应4条Lane。 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_ALIGN_FIFO_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5548) /* SLLC PHY Rx中，源同步FIFO模式下用于Per Lane Deskew的Align FIFO，分别对应4条Lane。 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_LANE0_VALID_ERR_CNT_REG (CSR_SLLC_PHY_REGS_BASE + 0x55C0) /* PHY Rx Lane0中的3bit valid出现异常的次数不受sllc_phy_cnt_en控制受sllc_phy_cnt_clr控制计满保持 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_LANE1_VALID_ERR_CNT_REG (CSR_SLLC_PHY_REGS_BASE + 0x55C8) /* PHY Rx Lane1中的3bit valid出现异常的次数不受sllc_phy_cnt_en控制受sllc_phy_cnt_clr控制计满保持 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_LANE2_VALID_ERR_CNT_REG (CSR_SLLC_PHY_REGS_BASE + 0x55D0) /* PHY Rx Lane2中的3bit valid出现异常的次数不受sllc_phy_cnt_en控制受sllc_phy_cnt_clr控制计满保持 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_LANE3_VALID_ERR_CNT_REG (CSR_SLLC_PHY_REGS_BASE + 0x55D8) /* PHY Rx Lane3中的3bit valid出现异常的次数不受sllc_phy_cnt_en控制受sllc_phy_cnt_clr控制计满保持 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5600) /* SLLC PHY Rx源同步FIFO相关状态 */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_SYNC_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5604) /* SLLC PHY Rx源同步FIFO相关状态（读时钟域对sync信号的周期计数） */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_LATENCY_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x5608) /* SLLC PHY Rx源同步FIFO相关状态（LATENCY相关） */ +#define CSR_SLLC_PHY_REGS_SLLC_PHY_RX_TRAIN_STALL_ST_REG (CSR_SLLC_PHY_REGS_BASE + 0x560C) /* SLLC PHY Rx源同步FIFO相关状态（STALL相关） */ + +#endif // __HI1823E_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/smmu_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/smmu_c_union_define.h new file mode 100644 index 000000000..ca0f66556 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/smmu_c_union_define.h @@ -0,0 +1,2448 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2023, Hisilicon Technologies Co. Ltd. +// File name : smmu_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2023/06/15 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2023/06/15 15:17:49 Create file +// ****************************************************************************** + +#ifndef __SMMU_C_UNION_DEFINE_H__ +#define __SMMU_C_UNION_DEFINE_H__ + +/* Define the union csr_smmu_idr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 s2p : 1; /* [0] */ + u32 s1p : 1; /* [1] */ + u32 ttf : 2; /* [3:2] */ + u32 cohacc : 1; /* [4] */ + u32 btm : 1; /* [5] */ + u32 httu : 2; /* [7:6] */ + u32 dormhint : 1; /* [8] */ + u32 hyp : 1; /* [9] */ + u32 ats : 1; /* [10] */ + u32 ns1ats : 1; /* [11] */ + u32 asid16 : 1; /* [12] */ + u32 msi : 1; /* [13] */ + u32 sev : 1; /* [14] */ + u32 atos : 1; /* [15] */ + u32 pri : 1; /* [16] */ + u32 vmw : 1; /* [17] */ + u32 vmid16 : 1; /* [18] */ + u32 cd2l : 1; /* [19] */ + u32 vatos : 1; /* [20] */ + u32 ttendian : 2; /* [22:21] */ + u32 rsv_0 : 1; /* [23] */ + u32 stall_model : 2; /* [25:24] */ + u32 term_model : 1; /* [26] */ + u32 st_level : 2; /* [28:27] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_idr0_u; + +/* Define the union csr_smmu_idr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sidsize : 6; /* [5:0] */ + u32 ssidsize : 5; /* [10:6] */ + u32 priqs : 5; /* [15:11] */ + u32 eventqs : 5; /* [20:16] */ + u32 cmdqs : 5; /* [25:21] */ + u32 attr_perms_ovr : 1; /* [26] */ + u32 attr_types_ovr : 1; /* [27] */ + u32 rel : 1; /* [28] */ + u32 queues_preset : 1; /* [29] */ + u32 tables_preset : 1; /* [30] */ + u32 rsv_2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_idr1_u; + +/* Define the union csr_smmu_idr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ba_vatos : 10; /* [9:0] */ + u32 rsv_3 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_idr2_u; + +/* Define the union csr_smmu_idr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_4 : 2; /* [1:0] */ + u32 had : 1; /* [2] */ + u32 pbha : 1; /* [3] */ + u32 xnx : 1; /* [4] */ + u32 pps : 1; /* [5] */ + u32 rsv_5 : 1; /* [6] */ + u32 mpam : 1; /* [7] */ + u32 fwb : 1; /* [8] */ + u32 stt : 1; /* [9] */ + u32 ril : 1; /* [10] */ + u32 bbml : 2; /* [12:11] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_idr3_u; + +/* Define the union csr_smmu_idr4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_idr4_u; + +/* Define the union csr_smmu_idr5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oas : 3; /* [2:0] */ + u32 rsv_8 : 1; /* [3] */ + u32 gran4k : 1; /* [4] */ + u32 gran16k : 1; /* [5] */ + u32 gran64k : 1; /* [6] */ + u32 rsv_9 : 3; /* [9:7] */ + u32 vax : 2; /* [11:10] */ + u32 rsv_10 : 4; /* [15:12] */ + u32 stall_max : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_idr5_u; + +/* Define the union csr_smmu_iidr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 implementer : 12; /* [11:0] */ + u32 revision : 4; /* [15:12] */ + u32 variant : 4; /* [19:16] */ + u32 productid : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_iidr_u; + +/* Define the union csr_smmu_aidr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 archminorrev : 4; /* [3:0] */ + u32 archmajorrev : 4; /* [7:4] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_aidr_u; + +/* Define the union csr_smmu_cr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmuen : 1; /* [0] */ + u32 priqen : 1; /* [1] */ + u32 eventqen : 1; /* [2] */ + u32 cmdqen : 1; /* [3] */ + u32 atschk : 1; /* [4] */ + u32 rsv_12 : 1; /* [5] */ + u32 vmw : 3; /* [8:6] */ + u32 rsv_13 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cr0_u; + +/* Define the union csr_smmu_cr0ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmuen : 1; /* [0] */ + u32 priqen : 1; /* [1] */ + u32 eventqen : 1; /* [2] */ + u32 cmdqen : 1; /* [3] */ + u32 atschk : 1; /* [4] */ + u32 rsv_14 : 1; /* [5] */ + u32 vmw : 3; /* [8:6] */ + u32 rsv_15 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cr0ack_u; + +/* Define the union csr_smmu_cr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_ic : 2; /* [1:0] */ + u32 queue_oc : 2; /* [3:2] */ + u32 queue_sh : 2; /* [5:4] */ + u32 table_ic : 2; /* [7:6] */ + u32 table_oc : 2; /* [9:8] */ + u32 table_sh : 2; /* [11:10] */ + u32 rsv_16 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cr1_u; + +/* Define the union csr_smmu_cr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 e2h : 1; /* [0] */ + u32 recinvsid : 1; /* [1] */ + u32 ptm : 1; /* [2] */ + u32 rsv_17 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cr2_u; + +/* Define the union csr_smmu_statusr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dormant : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_statusr_u; + +/* Define the union csr_smmu_gbpa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 mtcfg : 1; /* [4] */ + u32 rsv_19 : 3; /* [7:5] */ + u32 alloccfg : 4; /* [11:8] */ + u32 shcfg : 2; /* [13:12] */ + u32 rsv_20 : 2; /* [15:14] */ + u32 privcfg : 2; /* [17:16] */ + u32 instcfg : 2; /* [19:18] */ + u32 abort : 1; /* [20] */ + u32 rsv_21 : 10; /* [30:21] */ + u32 updating : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gbpa_u; + +/* Define the union csr_smmu_agbpa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 mtcfg : 1; /* [4] */ + u32 rsv_22 : 3; /* [7:5] */ + u32 alloccfg : 4; /* [11:8] */ + u32 shcfg : 2; /* [13:12] */ + u32 rsv_23 : 2; /* [15:14] */ + u32 privcfg : 2; /* [17:16] */ + u32 instcfg : 2; /* [19:18] */ + u32 abort : 1; /* [20] */ + u32 rsv_24 : 10; /* [30:21] */ + u32 updating : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_agbpa_u; + +/* Define the union csr_smmu_irq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gerror_irqen : 1; /* [0] */ + u32 priq_irqen : 1; /* [1] */ + u32 eventq_irqen : 1; /* [2] */ + u32 rsv_25 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_irq_ctrl_u; + +/* Define the union csr_smmu_irq_ctrlack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gerror_irqen : 1; /* [0] */ + u32 priq_irqen : 1; /* [1] */ + u32 eventq_irqen : 1; /* [2] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_irq_ctrlack_u; + +/* Define the union csr_smmu_gerror_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmdq_err : 1; /* [0] */ + u32 rsv_27 : 1; /* [1] */ + u32 eventq_abt_err : 1; /* [2] */ + u32 priq_abt_err : 1; /* [3] */ + u32 msi_cmdq_abt_err : 1; /* [4] */ + u32 msi_eventq_abt_err : 1; /* [5] */ + u32 msi_priq_abt_err : 1; /* [6] */ + u32 msi_gerror_abt_err : 1; /* [7] */ + u32 sfm_err : 1; /* [8] */ + u32 rsv_28 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gerror_u; + +/* Define the union csr_smmu_gerrorn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmdq_err : 1; /* [0] */ + u32 rsv_29 : 1; /* [1] */ + u32 eventq_abt_err : 1; /* [2] */ + u32 priq_abt_err : 1; /* [3] */ + u32 msi_cmdq_abt_err : 1; /* [4] */ + u32 msi_eventq_abt_err : 1; /* [5] */ + u32 msi_priq_abt_err : 1; /* [6] */ + u32 msi_gerror_abt_err : 1; /* [7] */ + u32 sfm_err : 1; /* [8] */ + u32 rsv_30 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gerrorn_u; + +/* Define the union csr_smmu_gerror_irq_cfg0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_31 : 2; /* [1:0] */ + u32 addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gerror_irq_cfg0_0_u; + +/* Define the union csr_smmu_gerror_irq_cfg0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 reserverd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gerror_irq_cfg0_1_u; + +/* Define the union csr_smmu_gerror_irq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gerror_irq_cfg1_u; + +/* Define the union csr_smmu_gerror_irq_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 sh : 2; /* [5:4] */ + u32 rsv_32 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_gerror_irq_cfg2_u; + +/* Define the union csr_smmu_strtab_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 6; /* [5:0] */ + u32 addr : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_strtab_base0_u; + +/* Define the union csr_smmu_strtab_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 rsv_34 : 14; /* [29:16] */ + u32 ra : 1; /* [30] */ + u32 rsv_35 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_strtab_base1_u; + +/* Define the union csr_smmu_strtab_base_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 6; /* [5:0] */ + u32 split : 5; /* [10:6] */ + u32 rsv_36 : 5; /* [15:11] */ + u32 fmt : 2; /* [17:16] */ + u32 rsv_37 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_strtab_base_cfg_u; + +/* Define the union csr_smmu_cmdq_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 5; /* [4:0] */ + u32 addr : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cmdq_base0_u; + +/* Define the union csr_smmu_cmdq_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 20; /* [19:0] */ + u32 rsv_38 : 10; /* [29:20] */ + u32 ra : 1; /* [30] */ + u32 rsv_39 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cmdq_base1_u; + +/* Define the union csr_smmu_cmdq_prod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr : 19; /* [18:0] */ + u32 wr_wrap : 1; /* [19] */ + u32 rsv_40 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cmdq_prod_u; + +/* Define the union csr_smmu_cmdq_cons_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd : 19; /* [18:0] */ + u32 rd_wrap : 1; /* [19] */ + u32 rsv_41 : 4; /* [23:20] */ + u32 err : 7; /* [30:24] */ + u32 rsv_42 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_cmdq_cons_u; + +/* Define the union csr_smmu_eventq_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 5; /* [4:0] */ + u32 addr : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_base0_u; + +/* Define the union csr_smmu_eventq_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 20; /* [19:0] */ + u32 rsv_43 : 10; /* [29:20] */ + u32 wa : 1; /* [30] */ + u32 rsv_44 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_base1_u; + +/* Define the union csr_smmu_eventq_prod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr : 19; /* [18:0] */ + u32 wr_wrap : 1; /* [19] */ + u32 rsv_45 : 11; /* [30:20] */ + u32 ovflg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_prod_u; + +/* Define the union csr_smmu_eventq_cons_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd : 19; /* [18:0] */ + u32 rd_wrap : 1; /* [19] */ + u32 rsv_46 : 11; /* [30:20] */ + u32 ovackflg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_cons_u; + +/* Define the union csr_smmu_eventq_irq_cfg0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_47 : 2; /* [1:0] */ + u32 addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_irq_cfg0_0_u; + +/* Define the union csr_smmu_eventq_irq_cfg0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_irq_cfg0_1_u; + +/* Define the union csr_smmu_eventq_irq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_irq_cfg1_u; + +/* Define the union csr_smmu_eventq_irq_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 sh : 2; /* [5:4] */ + u32 rsv_49 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_eventq_irq_cfg2_u; + +/* Define the union csr_smmu_priq_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 5; /* [4:0] */ + u32 addr : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_base0_u; + +/* Define the union csr_smmu_priq_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 20; /* [19:0] */ + u32 rsv_50 : 10; /* [29:20] */ + u32 wa : 1; /* [30] */ + u32 rsv_51 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_base1_u; + +/* Define the union csr_smmu_priq_prod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr : 19; /* [18:0] */ + u32 wr_wrap : 1; /* [19] */ + u32 rsv_52 : 11; /* [30:20] */ + u32 ovflg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_prod_u; + +/* Define the union csr_smmu_priq_cons_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd : 19; /* [18:0] */ + u32 rd_wrap : 1; /* [19] */ + u32 rsv_53 : 11; /* [30:20] */ + u32 ovackflg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_cons_u; + +/* Define the union csr_smmu_priq_irq_cfg0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_54 : 2; /* [1:0] */ + u32 addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_irq_cfg0_0_u; + +/* Define the union csr_smmu_priq_irq_cfg0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_irq_cfg0_1_u; + +/* Define the union csr_smmu_priq_irq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_irq_cfg1_u; + +/* Define the union csr_smmu_priq_irq_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 sh : 2; /* [5:4] */ + u32 rsv_56 : 25; /* [30:6] */ + u32 lo : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_priq_irq_cfg2_u; + +/* Define the union csr_smmu_s_idr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_57 : 13; /* [12:0] */ + u32 msi : 1; /* [13] */ + u32 rsv_58 : 10; /* [23:14] */ + u32 stall_model : 2; /* [25:24] */ + u32 rsv_59 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_idr0_u; + +/* Define the union csr_smmu_s_idr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 s_sidsize : 6; /* [5:0] */ + u32 rsv_60 : 23; /* [28:6] */ + u32 sel2 : 1; /* [29] */ + u32 rsv_61 : 1; /* [30] */ + u32 secure_impl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_idr1_u; + +/* Define the union csr_smmu_s_idr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ba_s_vatos : 10; /* [9:0] */ + u32 rsv_62 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_idr2_u; + +/* Define the union csr_smmu_s_idr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_63 : 6; /* [5:0] */ + u32 sams : 1; /* [6] */ + u32 rsv_64 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_idr3_u; + +/* Define the union csr_smmu_s_cr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmuen : 1; /* [0] */ + u32 rsv_65 : 1; /* [1] */ + u32 eventqen : 1; /* [2] */ + u32 cmdqen : 1; /* [3] */ + u32 rsv_66 : 1; /* [4] */ + u32 sif : 1; /* [5] */ + u32 vmw : 3; /* [8:6] */ + u32 nsstalld : 1; /* [9] */ + u32 rsv_67 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cr0_u; + +/* Define the union csr_smmu_s_cr0ack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmuen : 1; /* [0] */ + u32 rsv_68 : 1; /* [1] */ + u32 eventqen : 1; /* [2] */ + u32 cmdqen : 1; /* [3] */ + u32 rsv_69 : 1; /* [4] */ + u32 sif : 1; /* [5] */ + u32 vmw : 3; /* [8:6] */ + u32 nsstalld : 1; /* [9] */ + u32 rsv_70 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cr0ack_u; + +/* Define the union csr_smmu_s_cr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 queue_ic : 2; /* [1:0] */ + u32 queue_oc : 2; /* [3:2] */ + u32 queue_sh : 2; /* [5:4] */ + u32 table_ic : 2; /* [7:6] */ + u32 table_oc : 2; /* [9:8] */ + u32 table_sh : 2; /* [11:10] */ + u32 rsv_71 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cr1_u; + +/* Define the union csr_smmu_s_cr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 e2h : 1; /* [0] */ + u32 recinvsid : 1; /* [1] */ + u32 ptm : 1; /* [2] */ + u32 rsv_72 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cr2_u; + +/* Define the union csr_smmu_s_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inv_all : 1; /* [0] */ + u32 rsv_73 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_init_u; + +/* Define the union csr_smmu_s_gbpa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 mtcfg : 1; /* [4] */ + u32 rsv_74 : 3; /* [7:5] */ + u32 alloccfg : 4; /* [11:8] */ + u32 shcfg : 2; /* [13:12] */ + u32 nscfg : 2; /* [15:14] */ + u32 privcfg : 2; /* [17:16] */ + u32 instcfg : 2; /* [19:18] */ + u32 abort : 1; /* [20] */ + u32 rsv_75 : 10; /* [30:21] */ + u32 updating : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gbpa_u; + +/* Define the union csr_smmu_s_agbpa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 mtcfg : 1; /* [4] */ + u32 rsv_76 : 3; /* [7:5] */ + u32 alloccfg : 4; /* [11:8] */ + u32 shcfg : 2; /* [13:12] */ + u32 nscfg : 2; /* [15:14] */ + u32 privcfg : 2; /* [17:16] */ + u32 instcfg : 2; /* [19:18] */ + u32 abort : 1; /* [20] */ + u32 rsv_77 : 10; /* [30:21] */ + u32 updating : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_agbpa_u; + +/* Define the union csr_smmu_s_irq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gerror_irqen_s : 1; /* [0] */ + u32 rsv_78 : 1; /* [1] */ + u32 eventq_irqen_s : 1; /* [2] */ + u32 rsv_79 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_irq_ctrl_u; + +/* Define the union csr_smmu_s_irq_ctrlack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gerror_irqen_s : 1; /* [0] */ + u32 rsv_80 : 1; /* [1] */ + u32 eventq_irqen_s : 1; /* [2] */ + u32 rsv_81 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_irq_ctrlack_u; + +/* Define the union csr_smmu_s_gerror_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmdq_err : 1; /* [0] */ + u32 rsv_82 : 1; /* [1] */ + u32 eventq_abt_err : 1; /* [2] */ + u32 rsv_83 : 1; /* [3] */ + u32 msi_cmdq_abt_err : 1; /* [4] */ + u32 msi_eventq_abt_err : 1; /* [5] */ + u32 rsv_84 : 1; /* [6] */ + u32 msi_gerror_abt_err : 1; /* [7] */ + u32 sfm_err : 1; /* [8] */ + u32 rsv_85 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gerror_u; + +/* Define the union csr_smmu_s_gerrorn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmdq_err : 1; /* [0] */ + u32 rsv_86 : 1; /* [1] */ + u32 eventq_abt_err : 1; /* [2] */ + u32 rsv_87 : 1; /* [3] */ + u32 msi_cmdq_abt_err : 1; /* [4] */ + u32 msi_eventq_abt_err : 1; /* [5] */ + u32 rsv_88 : 1; /* [6] */ + u32 msi_gerror_abt_err : 1; /* [7] */ + u32 sfm_err : 1; /* [8] */ + u32 rsv_89 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gerrorn_u; + +/* Define the union csr_smmu_s_gerror_irq_cfg0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_90 : 2; /* [1:0] */ + u32 addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gerror_irq_cfg0_0_u; + +/* Define the union csr_smmu_s_gerror_irq_cfg0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 reserverd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gerror_irq_cfg0_1_u; + +/* Define the union csr_smmu_s_gerror_irq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gerror_irq_cfg1_u; + +/* Define the union csr_smmu_s_gerror_irq_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 sh : 2; /* [5:4] */ + u32 rsv_91 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_gerror_irq_cfg2_u; + +/* Define the union csr_smmu_s_strtab_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_92 : 6; /* [5:0] */ + u32 addr : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_strtab_base0_u; + +/* Define the union csr_smmu_s_strtab_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 rsv_93 : 14; /* [29:16] */ + u32 ra : 1; /* [30] */ + u32 rsv_94 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_strtab_base1_u; + +/* Define the union csr_smmu_s_strtab_base_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 6; /* [5:0] */ + u32 split : 5; /* [10:6] */ + u32 rsv_95 : 5; /* [15:11] */ + u32 fmt : 2; /* [17:16] */ + u32 rsv_96 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_strtab_base_cfg_u; + +/* Define the union csr_smmu_s_cmdq_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 5; /* [4:0] */ + u32 addr : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cmdq_base0_u; + +/* Define the union csr_smmu_s_cmdq_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 20; /* [19:0] */ + u32 rsv_97 : 10; /* [29:20] */ + u32 ra : 1; /* [30] */ + u32 rsv_98 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cmdq_base1_u; + +/* Define the union csr_smmu_s_cmdq_prod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr : 19; /* [18:0] */ + u32 wr_wrap : 1; /* [19] */ + u32 rsv_99 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cmdq_prod_u; + +/* Define the union csr_smmu_s_cmdq_cons_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd : 19; /* [18:0] */ + u32 rd_wrap : 1; /* [19] */ + u32 rsv_100 : 4; /* [23:20] */ + u32 err : 7; /* [30:24] */ + u32 rsv_101 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_cmdq_cons_u; + +/* Define the union csr_smmu_s_eventq_base0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 log2size : 5; /* [4:0] */ + u32 addr : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_base0_u; + +/* Define the union csr_smmu_s_eventq_base1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 20; /* [19:0] */ + u32 rsv_102 : 10; /* [29:20] */ + u32 wa : 1; /* [30] */ + u32 rsv_103 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_base1_u; + +/* Define the union csr_smmu_s_eventq_prod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr : 19; /* [18:0] */ + u32 wr_wrap : 1; /* [19] */ + u32 rsv_104 : 11; /* [30:20] */ + u32 ovflg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_prod_u; + +/* Define the union csr_smmu_s_eventq_cons_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd : 19; /* [18:0] */ + u32 rd_wrap : 1; /* [19] */ + u32 rsv_105 : 11; /* [30:20] */ + u32 ovackflg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_cons_u; + +/* Define the union csr_smmu_s_eventq_irq_cfg0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_106 : 2; /* [1:0] */ + u32 addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_irq_cfg0_0_u; + +/* Define the union csr_smmu_s_eventq_irq_cfg0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 16; /* [15:0] */ + u32 rsv_107 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_irq_cfg0_1_u; + +/* Define the union csr_smmu_s_eventq_irq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_irq_cfg1_u; + +/* Define the union csr_smmu_s_eventq_irq_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 sh : 2; /* [5:4] */ + u32 rsv_108 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_s_eventq_irq_cfg2_u; + +/* Define the union csr_smmu_user_config0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2_tlb_en : 1; /* [0] */ + u32 cmd_ots_en : 1; /* [1] */ + u32 walk_cache_en : 1; /* [2] */ + u32 page_cache_en : 1; /* [3] */ + u32 l2_tlb_gs_set : 4; /* [7:4] */ + u32 sky_bypass_en : 1; /* [8] */ + u32 sky_bypass_wr_force : 1; /* [9] */ + u32 sky_bypass_rd_force : 1; /* [10] */ + u32 l2_allocate_l1_en : 1; /* [11] */ + u32 stream_req_opt : 8; /* [19:12] */ + u32 ste_bypass_allocate_tlb_en : 1; /* [20] */ + u32 readonce_makeinvalid : 1; /* [21] */ + u32 stream_write_mode_sp : 1; /* [22] */ + u32 writeback_spill_en : 1; /* [23] */ + u32 stash_dieid0 : 2; /* [25:24] */ + u32 stash_dieid1 : 2; /* [27:26] */ + u32 stream_write_mode_tp : 1; /* [28] */ + u32 l2_tlb_index_mode : 1; /* [29] */ + u32 mpam_en : 1; /* [30] */ + u32 pcie_invld_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_user_config0_u; + +/* Define the union csr_smmu_user_config1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 master0_gs : 2; /* [1:0] */ + u32 master1_gs : 2; /* [3:2] */ + u32 master2_gs : 2; /* [5:4] */ + u32 master3_gs : 2; /* [7:6] */ + u32 master4_gs : 2; /* [9:8] */ + u32 master5_gs : 2; /* [11:10] */ + u32 master6_gs : 2; /* [13:12] */ + u32 master7_gs : 2; /* [15:14] */ + u32 rsv_109 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_user_config1_u; + +/* Define the union csr_smmu_veri_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 version_id : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_veri_id_u; + +/* Define the union csr_smmu_prod_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 implementer : 12; /* [11:0] */ + u32 revision : 4; /* [15:12] */ + u32 variant : 4; /* [19:16] */ + u32 productid : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_prod_info_u; + +/* Define the union csr_smmu_user_config2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inv_all_ns : 1; /* [0] */ + u32 rsv_110 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_user_config2_u; + +/* Define the union csr_smmu_pcie_irpt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irpt_topcie_en : 1; /* [0] */ + u32 rsv_111 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pcie_irpt_en_u; + +/* Define the union csr_smmu_pcie_irpt_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irpt_topcie_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pcie_irpt_addr_u; + +/* Define the union csr_smmu_pcie_irpt_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irpt_topcie_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pcie_irpt_data_u; + +/* Define the union csr_smmu_user_config3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ptw_qos : 4; /* [3:0] */ + u32 stash_die_mode : 1; /* [4] */ + u32 tocpa_en : 1; /* [5] */ + u32 ptw_invld_mode : 1; /* [6] */ + u32 iocache_comp_mode : 1; /* [7] */ + u32 reg_pri_mode : 1; /* [8] */ + u32 reg_ats_mode : 1; /* [9] */ + u32 reg_inv_va_disable : 1; /* [10] */ + u32 reg_l2_inv_va_mode : 1; /* [11] */ + u32 reg_sky_not_block : 1; /* [12] */ + u32 reg_sky_not_block_int : 1; /* [13] */ + u32 reg_add_stash : 1; /* [14] */ + u32 reg_queue_nca_en : 1; /* [15] */ + u32 reg_sync_nowait : 1; /* [16] */ + u32 reg_sync_nowait_read : 1; /* [17] */ + u32 reg_eventq_stash_en : 1; /* [18] */ + u32 reg_long_atomic_en : 1; /* [19] */ + u32 reg_hyp_mode : 1; /* [20] */ + u32 reg_wc_hit_mode : 1; /* [21] */ + u32 reg_single_totem_mode : 1; /* [22] */ + u32 reg_relax_order : 1; /* [23] */ + u32 reg_atc_ots_en : 1; /* [24] */ + u32 reg_irpt_en : 1; /* [25] */ + u32 reg_range_invld_en : 1; /* [26] */ + u32 reg_tlb_ns_only : 1; /* [27] */ + u32 reg_sync_nowait_notrans : 1; /* [28] */ + u32 reg_wc_invall_mode : 1; /* [29] */ + u32 rsv_112 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_user_config3_u; + +/* Define the union csr_smmu_user_config4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_range_invld_cnt : 4; /* [3:0] */ + u32 rsv_113 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_user_config4_u; + +/* Define the union csr_dfx_cmd_ns_cons_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_114 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cmd_ns_cons_cnt0_u; + +/* Define the union csr_dfx_cmd_ns_cons_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_115 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cmd_ns_cons_cnt1_u; + +/* Define the union csr_smmu_sky_queue_pointer_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_id : 8; /* [7:0] */ + u32 rsv_116 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_pointer_sp_u; + +/* Define the union csr_smmu_sky_queue_addr_low_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_addr_low_sp_u; + +/* Define the union csr_smmu_sky_queue_addr_high_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_addr_high_sp_u; + +/* Define the union csr_smmu_sky_queue_stat0_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_stat : 16; /* [15:0] */ + u32 dfx_sky_queue_probe_txnid : 8; /* [23:16] */ + u32 dfx_sky_queue_probe_mstid : 3; /* [26:24] */ + u32 rsv_117 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_stat0_sp_u; + +/* Define the union csr_smmu_sky_queue_stat1_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_stat1_sp_u; + +/* Define the union csr_smmu_sky_queue_pointer_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_id : 8; /* [7:0] */ + u32 rsv_118 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_pointer_tp_u; + +/* Define the union csr_smmu_sky_queue_addr_low_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_addr_low_tp_u; + +/* Define the union csr_smmu_sky_queue_addr_high_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_addr_high : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_addr_high_tp_u; + +/* Define the union csr_smmu_sky_queue_stat0_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_stat : 16; /* [15:0] */ + u32 dfx_sky_queue_probe_txnid : 8; /* [23:16] */ + u32 dfx_sky_queue_probe_mstid : 3; /* [26:24] */ + u32 rsv_119 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_stat0_tp_u; + +/* Define the union csr_smmu_sky_queue_stat1_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_probe_strmid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_sky_queue_stat1_tp_u; + +/* Define the union csr_smmu_dfx_cmd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmd_num_sp : 8; /* [7:0] */ + u32 cmd_num_tp : 8; /* [15:8] */ + u32 rsv_120 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_cmd_num_u; + +/* Define the union csr_smmu_dfx_cmd_queue_stat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cmd_queue_stat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_cmd_queue_stat0_u; + +/* Define the union csr_smmu_dfx_fault_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fault_cnt : 30; /* [29:0] */ + u32 dfx_stall_irpt_sp : 1; /* [30] */ + u32 dfx_stall_irpt_tp : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_fault_num_u; + +/* Define the union csr_smmu_dfx_test_monitor_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_valud_num : 8; /* [7:0] */ + u32 block_axi_mst_num : 8; /* [15:8] */ + u32 block_axi_wr_order : 1; /* [16] */ + u32 block_axi_rd_order : 1; /* [17] */ + u32 block_axi_wr_norder : 1; /* [18] */ + u32 block_axi_rd_norder : 1; /* [19] */ + u32 block_axi_wr_norder_long : 1; /* [20] */ + u32 block_axi_rd_norder_long : 1; /* [21] */ + u32 rsv_121 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_test_monitor_sp_u; + +/* Define the union csr_smmu_dfx_test_monitor_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_valud_num : 8; /* [7:0] */ + u32 block_axi_mst_num : 8; /* [15:8] */ + u32 block_axi_wr_order : 1; /* [16] */ + u32 block_axi_rd_order : 1; /* [17] */ + u32 block_axi_wr_norder : 1; /* [18] */ + u32 block_axi_rd_norder : 1; /* [19] */ + u32 block_axi_wr_norder_long : 1; /* [20] */ + u32 block_axi_rd_norder_long : 1; /* [21] */ + u32 rsv_122 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_test_monitor_tp_u; + +/* Define the union csr_smmu_dfx_ecc_monitor_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2_ecc_cnt : 8; /* [7:0] */ + u32 cntxt_cache_ecc_cnt : 8; /* [15:8] */ + u32 axi_ecc_err_sp_cnt : 8; /* [23:16] */ + u32 axi_ecc_err_tp_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_ecc_monitor_u; + +/* Define the union csr_smmu_stall_queue_stat0_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_stall_strmid : 25; /* [24:0] */ + u32 rsv_123 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_stall_queue_stat0_sp_u; + +/* Define the union csr_smmu_stall_queue_stat1_sp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_stall_txnid : 8; /* [7:0] */ + u32 dfx_sky_queue_stall_ns : 1; /* [8] */ + u32 rsv_124 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_stall_queue_stat1_sp_u; + +/* Define the union csr_smmu_stall_queue_stat0_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_stall_strmid : 25; /* [24:0] */ + u32 rsv_125 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_stall_queue_stat0_tp_u; + +/* Define the union csr_smmu_stall_queue_stat1_tp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_sky_queue_stall_txnid : 8; /* [7:0] */ + u32 dfx_sky_queue_stall_ns : 1; /* [8] */ + u32 rsv_126 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_stall_queue_stat1_tp_u; + +/* Define the union csr_smmu_ecc_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inject_1bit_sel : 8; /* [7:0] */ + u32 inject_2bit_sel : 8; /* [15:8] */ + u32 inject_axi_en : 1; /* [16] */ + u32 inject_tbu_en : 1; /* [17] */ + u32 inject_tcu_en : 1; /* [18] */ + u32 inject_2bit_en : 1; /* [19] */ + u32 rsv_127 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_ecc_inject_u; + +/* Define the union csr_smmu_ptw_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ptw_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_ptw_status_u; + +/* Define the union csr_smmu_ptw_status_s2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ptw_status_s2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_ptw_status_s2_u; + +/* Define the union csr_smmu_dfx_cmd_queue_stat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cmd_queue_stat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_dfx_cmd_queue_stat1_u; + +/* Define the union csr_smmu_pmcg_evcntrn_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 evcnt_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_evcntrn_0_u; + +/* Define the union csr_smmu_pmcg_evcntrn_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 evcnt_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_evcntrn_1_u; + +/* Define the union csr_smmu_pmcg_evtypern_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pmcg_event : 16; /* [15:0] */ + u32 rsv_128 : 13; /* [28:16] */ + u32 filter_sid_span : 1; /* [29] */ + u32 filter_sec_sid : 1; /* [30] */ + u32 ovfcap : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_evtypern_u; + +/* Define the union csr_smmu_pmcg_svrn_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 svr0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_svrn_0_u; + +/* Define the union csr_smmu_pmcg_svrn_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 svr1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_svrn_1_u; + +/* Define the union csr_smmu_pmcg_smrn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 streamid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_smrn_u; + +/* Define the union csr_smmu_pmcg_cntenset0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnten : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cntenset0_0_u; + +/* Define the union csr_smmu_pmcg_cntenset0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnten : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cntenset0_1_u; + +/* Define the union csr_smmu_pmcg_cntenclr0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cntclr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cntenclr0_0_u; + +/* Define the union csr_smmu_pmcg_cntenclr0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cntclr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cntenclr0_1_u; + +/* Define the union csr_smmu_pmcg_intenset0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inten : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_intenset0_0_u; + +/* Define the union csr_smmu_pmcg_intenset0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inten : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_intenset0_1_u; + +/* Define the union csr_smmu_pmcg_intenclr0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intclr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_intenclr0_0_u; + +/* Define the union csr_smmu_pmcg_intenclr0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intclr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_intenclr0_1_u; + +/* Define the union csr_smmu_pmcg_ovsclr0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ovs : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ovsclr0_0_u; + +/* Define the union csr_smmu_pmcg_ovsclr0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ovs : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ovsclr0_1_u; + +/* Define the union csr_smmu_pmcg_ovsset0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ovs : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ovsset0_0_u; + +/* Define the union csr_smmu_pmcg_ovsset0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ovs : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ovsset0_1_u; + +/* Define the union csr_smmu_pmcg_capr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture : 1; /* [0] */ + u32 rsv_129 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_capr_u; + +/* Define the union csr_smmu_pmcg_scr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 so : 1; /* [0] */ + u32 nsra : 1; /* [1] */ + u32 nsmsi : 1; /* [2] */ + u32 rsv_130 : 28; /* [30:3] */ + u32 readone : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_scr_u; + +/* Define the union csr_smmu_pmcg_cfgr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nctr : 6; /* [5:0] */ + u32 rsv_131 : 2; /* [7:6] */ + u32 pmcg_size : 6; /* [13:8] */ + u32 rsv_132 : 6; /* [19:14] */ + u32 reloc_ctrs : 1; /* [20] */ + u32 msi : 1; /* [21] */ + u32 capture : 1; /* [22] */ + u32 sid_filter_type : 1; /* [23] */ + u32 mpam : 1; /* [24] */ + u32 rsv_133 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cfgr_u; + +/* Define the union csr_smmu_pmcg_cr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 e : 1; /* [0] */ + u32 rsv_134 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cr_u; + +/* Define the union csr_smmu_pmcg_ceid0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 event_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ceid0_0_u; + +/* Define the union csr_smmu_pmcg_ceid0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 event_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ceid0_1_u; + +/* Define the union csr_smmu_pmcg_ceid1_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 event_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ceid1_0_u; + +/* Define the union csr_smmu_pmcg_ceid1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 event_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_ceid1_1_u; + +/* Define the union csr_smmu_pmcg_irq_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqen : 1; /* [0] */ + u32 rsv_135 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_ctrl_u; + +/* Define the union csr_smmu_pmcg_irq_ctrlack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irqen : 1; /* [0] */ + u32 rsv_136 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_ctrlack_u; + +/* Define the union csr_smmu_pmcg_irq_cfg0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_137 : 2; /* [1:0] */ + u32 addr : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_cfg0_0_u; + +/* Define the union csr_smmu_pmcg_irq_cfg0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addr : 20; /* [19:0] */ + u32 rsv_138 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_cfg0_1_u; + +/* Define the union csr_smmu_pmcg_irq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_cfg1_u; + +/* Define the union csr_smmu_pmcg_irq_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memattr : 4; /* [3:0] */ + u32 sh : 2; /* [5:4] */ + u32 rsv_139 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_cfg2_u; + +/* Define the union csr_smmu_pmcg_irq_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 irq_abt : 1; /* [0] */ + u32 rsv_140 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_irq_status_u; + +/* Define the union csr_smmu_pmcg_aidr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 archminorrev : 4; /* [3:0] */ + u32 archmajorrev : 4; /* [7:4] */ + u32 rsv_141 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_aidr_u; + +/* Define the union csr_smmu_pmcg_cidr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 preamble : 8; /* [7:0] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cidr0_u; + +/* Define the union csr_smmu_pmcg_cidr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 preamble : 4; /* [3:0] */ + u32 pmcg_class : 4; /* [7:4] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cidr1_u; + +/* Define the union csr_smmu_pmcg_cidr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 preamble : 8; /* [7:0] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cidr2_u; + +/* Define the union csr_smmu_pmcg_cidr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 preamble : 8; /* [7:0] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_cidr3_u; + +/* Define the union csr_smmu_pmcg_pidr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 part_0 : 8; /* [7:0] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr0_u; + +/* Define the union csr_smmu_pmcg_pidr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 part_1 : 4; /* [3:0] */ + u32 des_0 : 4; /* [7:4] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr1_u; + +/* Define the union csr_smmu_pmcg_pidr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_1 : 3; /* [2:0] */ + u32 jedec_assigned_value : 1; /* [3] */ + u32 revision : 4; /* [7:4] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr2_u; + +/* Define the union csr_smmu_pmcg_pidr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmod : 4; /* [3:0] */ + u32 revand : 4; /* [7:4] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr3_u; + +/* Define the union csr_smmu_pmcg_pidr4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_2 : 4; /* [3:0] */ + u32 pmcg_size : 4; /* [7:4] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr4_u; + +/* Define the union csr_smmu_pmcg_pidr5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reseved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr5_u; + +/* Define the union csr_smmu_pmcg_pidr6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reseved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr6_u; + +/* Define the union csr_smmu_pmcg_pidr7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reseved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pidr7_u; + +/* Define the union csr_smmu_pmcg_pmauthstatus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reseved : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pmauthstatus_u; + +/* Define the union csr_smmu_pmcg_pmdevarch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 archid : 16; /* [15:0] */ + u32 revision : 4; /* [19:16] */ + u32 present : 1; /* [20] */ + u32 architect : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pmdevarch_u; + +/* Define the union csr_smmu_pmcg_pmdevtype_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pm_dev_type_low : 4; /* [3:0] */ + u32 pm_dev_type_high : 4; /* [7:4] */ + u32 reseved : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_pmcg_pmdevtype_u; + +/* Define the union csr_smmu_err_fr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ed : 2; /* [1:0] */ + u32 rsv_142 : 2; /* [3:2] */ + u32 ui : 2; /* [5:4] */ + u32 fi : 2; /* [7:6] */ + u32 ue : 2; /* [9:8] */ + u32 cfi : 2; /* [11:10] */ + u32 cec : 3; /* [14:12] */ + u32 rp : 1; /* [15] */ + u32 dui : 2; /* [17:16] */ + u32 ceo : 2; /* [19:18] */ + u32 rsv_143 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_fr_0_u; + +/* Define the union csr_smmu_err_fr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_144 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_fr_1_u; + +/* Define the union csr_smmu_err_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ed : 1; /* [0] */ + u32 rsv_145 : 1; /* [1] */ + u32 ui : 1; /* [2] */ + u32 fi : 1; /* [3] */ + u32 ue : 1; /* [4] */ + u32 rsv_146 : 3; /* [7:5] */ + u32 cfi : 1; /* [8] */ + u32 rsv_147 : 1; /* [9] */ + u32 dui : 1; /* [10] */ + u32 rsv_148 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_ctrl_0_u; + +/* Define the union csr_smmu_err_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_149 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_ctrl_1_u; + +/* Define the union csr_smmu_err_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 serr : 8; /* [7:0] */ + u32 ierr : 8; /* [15:8] */ + u32 rsv_150 : 4; /* [19:16] */ + u32 uet : 2; /* [21:20] */ + u32 pn : 1; /* [22] */ + u32 de : 1; /* [23] */ + u32 ce : 2; /* [25:24] */ + u32 mv : 1; /* [26] */ + u32 of : 1; /* [27] */ + u32 er : 1; /* [28] */ + u32 ue : 1; /* [29] */ + u32 v : 1; /* [30] */ + u32 av : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_status_0_u; + +/* Define the union csr_smmu_err_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_151 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_status_1_u; + +/* Define the union csr_smmu_err_addr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_addr_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_addr_0_u; + +/* Define the union csr_smmu_err_addr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_addr_high : 16; /* [15:0] */ + u32 rsv_152 : 13; /* [28:16] */ + u32 addr_ai : 1; /* [29] */ + u32 nsv : 1; /* [30] */ + u32 addr_ns : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_addr_1_u; + +/* Define the union csr_smmu_err_misc0_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_153 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_misc0_0_u; + +/* Define the union csr_smmu_err_misc0_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_err_cnt : 7; /* [6:0] */ + u32 ecc_err_ovflow : 1; /* [7] */ + u32 rsv_154 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_misc0_1_u; + +/* Define the union csr_smmu_err_misc1_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_155 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_misc1_0_u; + +/* Define the union csr_smmu_err_misc1_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_156 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmu_err_misc1_1_u; + + +#endif // __SMMU_C_UNION_DEFINE_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/smmu_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/smmu_reg_offset.h new file mode 100644 index 000000000..29b953268 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/smmu_reg_offset.h @@ -0,0 +1,256 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2023, Hisilicon Technologies Co. Ltd. +// File name : smmu_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2023/06/15 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2023/06/15 15:17:49 Create file +// ****************************************************************************** + +#ifndef __SMMU_REG_OFFSET_H__ +#define __SMMU_REG_OFFSET_H__ + +/* SMMU Base address of Module's Register */ +#define CSR_SMMU_BASE (0x0000) + +/* **************************************************************************** */ +/* SMMU Registers' Definitions */ +/* **************************************************************************** */ + +#define SMMU_IDR0_REG (CSR_SMMU_BASE + 0x0) /* SMMU标志0寄存器。 */ +#define SMMU_IDR1_REG (CSR_SMMU_BASE + 0x4) /* SMMU标志1寄存器。 */ +#define SMMU_IDR2_REG (CSR_SMMU_BASE + 0x8) /* SMMU标志2寄存器。 */ +#define SMMU_IDR3_REG (CSR_SMMU_BASE + 0xC) /* SMMU标志3寄存器。 */ +#define SMMU_IDR4_REG (CSR_SMMU_BASE + 0x10) /* SMMU标志4寄存器。 */ +#define SMMU_IDR5_REG (CSR_SMMU_BASE + 0x14) /* SMMU标志5寄存器。 */ +#define SMMU_IIDR_REG (CSR_SMMU_BASE + 0x18) /* SMMU版本标志0寄存器。 */ +#define SMMU_AIDR_REG (CSR_SMMU_BASE + 0x1C) /* SMMU版本标志1寄存器。 */ +#define SMMU_CR0_REG (CSR_SMMU_BASE + 0x20) /* SMMU全局配置0寄存器。 */ +#define SMMU_CR0ACK_REG (CSR_SMMU_BASE + 0x24) /* SMMU全局配置ack寄存器。 */ +#define SMMU_CR1_REG (CSR_SMMU_BASE + 0x28) /* SMMU全局配置1寄存器。 */ +#define SMMU_CR2_REG (CSR_SMMU_BASE + 0x2C) /* SMMU全局配置2寄存器。 */ +#define SMMU_STATUSR_REG (CSR_SMMU_BASE + 0x40) /* SMMU Cache状态寄存器。 */ +#define SMMU_GBPA_REG (CSR_SMMU_BASE + 0x44) /* SMMU全局属性寄存器。 */ +#define SMMU_AGBPA_REG (CSR_SMMU_BASE + 0x48) /* SMMU全局属性辅助寄存器。 */ +#define SMMU_IRQ_CTRL_REG (CSR_SMMU_BASE + 0x50) /* SMMU全局中断使能寄存器。 */ +#define SMMU_IRQ_CTRLACK_REG (CSR_SMMU_BASE + 0x54) /* SMMU全局中断使能ACK寄存器。 */ +#define SMMU_GERROR_REG (CSR_SMMU_BASE + 0x60) /* SMMU全局fault寄存器。 */ +#define SMMU_GERRORN_REG (CSR_SMMU_BASE + 0x64) /* SMMU全局fault镜像寄存器。 */ +#define SMMU_GERROR_IRQ_CFG0_0_REG (CSR_SMMU_BASE + 0x68) /* SMMU全局中断MSI地址配置0寄存器。 */ +#define SMMU_GERROR_IRQ_CFG0_1_REG (CSR_SMMU_BASE + 0x6C) /* SMMU全局中断MSI地址配置1寄存器。 */ +#define SMMU_GERROR_IRQ_CFG1_REG (CSR_SMMU_BASE + 0x70) /* SMMU全局中断MSI数据配置寄存器。 */ +#define SMMU_GERROR_IRQ_CFG2_REG (CSR_SMMU_BASE + 0x74) /* SMMU全局中断MSI属性配置寄存器。 */ +#define SMMU_STRTAB_BASE0_REG (CSR_SMMU_BASE + 0x80) /* SMMU STE基地址低位寄存器。 */ +#define SMMU_STRTAB_BASE1_REG (CSR_SMMU_BASE + 0x84) /* SMMU STE基地址高位寄存器。 */ +#define SMMU_STRTAB_BASE_CFG_REG (CSR_SMMU_BASE + 0x88) /* SMMU STE配置寄存器。 */ +#define SMMU_CMDQ_BASE0_REG (CSR_SMMU_BASE + 0x90) /* SMMU CMD queue基地址低位寄存器。 */ +#define SMMU_CMDQ_BASE1_REG (CSR_SMMU_BASE + 0x94) /* SMMU CMD queue基地址高位寄存器。 */ +#define SMMU_CMDQ_PROD_REG (CSR_SMMU_BASE + 0x98) /* SMMU CMD queue producer寄存器。 */ +#define SMMU_CMDQ_CONS_REG (CSR_SMMU_BASE + 0x9C) /* SMMU CMD queue consumer寄存器。 */ +#define SMMU_EVENTQ_BASE0_REG (CSR_SMMU_BASE + 0xA0) /* SMMU EVENT queue基地址低位寄存器。 */ +#define SMMU_EVENTQ_BASE1_REG (CSR_SMMU_BASE + 0xA4) /* SMMU EVENT queue基地址高位寄存器。 */ +#define SMMU_EVENTQ_PROD_REG (CSR_SMMU_BASE + 0x100A8) /* SMMU EVENT queue producer寄存器。 */ +#define SMMU_EVENTQ_CONS_REG (CSR_SMMU_BASE + 0x100AC) /* SMMU EVENT queue cosumer 寄存器。 */ +#define SMMU_EVENTQ_IRQ_CFG0_0_REG (CSR_SMMU_BASE + 0xB0) /* SMMU EVENT queue MSI中断地址低位配置寄存器。 */ +#define SMMU_EVENTQ_IRQ_CFG0_1_REG (CSR_SMMU_BASE + 0xB4) /* SMMU EVENT queue MSI中断地址高位配置寄存器。 */ +#define SMMU_EVENTQ_IRQ_CFG1_REG (CSR_SMMU_BASE + 0xB8) /* SMMU EVENT queue MSI中断数据配置寄存器。 */ +#define SMMU_EVENTQ_IRQ_CFG2_REG (CSR_SMMU_BASE + 0xBC) /* SMMU EVENT queue MSI中断属性配置寄存器。 */ +#define SMMU_PRIQ_BASE0_REG (CSR_SMMU_BASE + 0xC0) /* SMMU PRIQ基地址低位寄存器。 */ +#define SMMU_PRIQ_BASE1_REG (CSR_SMMU_BASE + 0xC4) /* SMMU PRIQ基地址高位寄存器。 */ +#define SMMU_PRIQ_PROD_REG (CSR_SMMU_BASE + 0x100C8) /* SMMU PRIQ producer寄存器。 */ +#define SMMU_PRIQ_CONS_REG (CSR_SMMU_BASE + 0x100CC) /* SMMU PRIQ consumer寄存器。 */ +#define SMMU_PRIQ_IRQ_CFG0_0_REG (CSR_SMMU_BASE + 0xD0) /* SMMU PRIQ MSI中断地址低位配置寄存器。 */ +#define SMMU_PRIQ_IRQ_CFG0_1_REG (CSR_SMMU_BASE + 0xD4) /* SMMU PRIQ MSI中断地址高位配置寄存器。 */ +#define SMMU_PRIQ_IRQ_CFG1_REG (CSR_SMMU_BASE + 0xD8) /* SMMU PRIQ MSI中断数据配置寄存器。 */ +#define SMMU_PRIQ_IRQ_CFG2_REG (CSR_SMMU_BASE + 0xDC) /* SMMU PRIQ MSI中断属性配置寄存器。 */ +#define SMMU_S_IDR0_REG (CSR_SMMU_BASE + 0x8000) /* 安全状态下SMMU标志0寄存器。 */ +#define SMMU_S_IDR1_REG (CSR_SMMU_BASE + 0x8004) /* 安全状态下SMMU标志1寄存器。 */ +#define SMMU_S_IDR2_REG (CSR_SMMU_BASE + 0x8008) /* 安全状态下SMMU标志2寄存器。 */ +#define SMMU_S_IDR3_REG (CSR_SMMU_BASE + 0x800C) /* 安全状态下SMMU标志3寄存器。 */ +#define SMMU_S_CR0_REG (CSR_SMMU_BASE + 0x8020) /* 安全状态下SMMU全局配置0寄存器。 */ +#define SMMU_S_CR0ACK_REG (CSR_SMMU_BASE + 0x8024) /* 安全状态下SMMU全局配置ACK寄存器。 */ +#define SMMU_S_CR1_REG (CSR_SMMU_BASE + 0x8028) /* 安全状态下SMMU全局配置1寄存器。 */ +#define SMMU_S_CR2_REG (CSR_SMMU_BASE + 0x802C) /* 安全状态下SMMU全局配置2寄存器。 */ +#define SMMU_S_INIT_REG (CSR_SMMU_BASE + 0x803C) /* 安全状态下SMMU无效化cache寄存器。 */ +#define SMMU_S_GBPA_REG (CSR_SMMU_BASE + 0x8044) /* 安全状态下SMMU全局属性寄存器。 */ +#define SMMU_S_AGBPA_REG (CSR_SMMU_BASE + 0x8048) /* 安全状态下SMMU全局属性辅助寄存器。 */ +#define SMMU_S_IRQ_CTRL_REG (CSR_SMMU_BASE + 0x8050) /* 安全状态下SMMU全局中断使能寄存器。 */ +#define SMMU_S_IRQ_CTRLACK_REG (CSR_SMMU_BASE + 0x8054) /* 安全状态下SMMU全局中断使能ACK寄存器。 */ +#define SMMU_S_GERROR_REG (CSR_SMMU_BASE + 0x8060) /* 安全状态下SMMU全局fault寄存器。 */ +#define SMMU_S_GERRORN_REG (CSR_SMMU_BASE + 0x8064) /* 安全状态下SMMU全局fault镜像寄存器。 */ +#define SMMU_S_GERROR_IRQ_CFG0_0_REG (CSR_SMMU_BASE + 0x8068) /* 安全状态下SMMU全局中断MSI地址低位配置寄存器。 */ +#define SMMU_S_GERROR_IRQ_CFG0_1_REG (CSR_SMMU_BASE + 0x806C) /* 安全状态下SMMU全局中断MSI地址高位配置寄存器。 */ +#define SMMU_S_GERROR_IRQ_CFG1_REG (CSR_SMMU_BASE + 0x8070) /* 安全状态下SMMU全局中断MSI数据配置寄存器。 */ +#define SMMU_S_GERROR_IRQ_CFG2_REG (CSR_SMMU_BASE + 0x8074) /* 安全状态下SMMU全局中断MSI属性配置寄存器。 */ +#define SMMU_S_STRTAB_BASE0_REG (CSR_SMMU_BASE + 0x8080) /* 安全状态下SMMU STE基地址低位寄存器。 */ +#define SMMU_S_STRTAB_BASE1_REG (CSR_SMMU_BASE + 0x8084) /* 安全状态下SMMU STE基地址高位寄存器。 */ +#define SMMU_S_STRTAB_BASE_CFG_REG (CSR_SMMU_BASE + 0x8088) /* 安全状态下SMMU STE配置寄存器。 */ +#define SMMU_S_CMDQ_BASE0_REG (CSR_SMMU_BASE + 0x8090) /* 安全状态下SMMU CMD queue基地址低位寄存器。 */ +#define SMMU_S_CMDQ_BASE1_REG (CSR_SMMU_BASE + 0x8094) /* 安全状态下SMMU CMD queue基地址高位寄存器。 */ +#define SMMU_S_CMDQ_PROD_REG (CSR_SMMU_BASE + 0x8098) /* 安全状态下SMMU CMD queue producer寄存器。 */ +#define SMMU_S_CMDQ_CONS_REG (CSR_SMMU_BASE + 0x809C) /* 安全状态下SMMU CMD queue consumer寄存器。 */ +#define SMMU_S_EVENTQ_BASE0_REG (CSR_SMMU_BASE + 0x80A0) /* 安全状态下SMMU EVENT queue基地址低位寄存器。 */ +#define SMMU_S_EVENTQ_BASE1_REG (CSR_SMMU_BASE + 0x80A4) /* 安全状态下SMMU EVENT queue基地址高位寄存器。 */ +#define SMMU_S_EVENTQ_PROD_REG (CSR_SMMU_BASE + 0x80A8) /* 安全状态下SMMU EVENT queue producer寄存器。 */ +#define SMMU_S_EVENTQ_CONS_REG (CSR_SMMU_BASE + 0x80AC) /* 安全状态下SMMU EVENT queue cosumer 寄存器。 */ +#define SMMU_S_EVENTQ_IRQ_CFG0_0_REG \ + (CSR_SMMU_BASE + 0x80B0) /* 安全状态下SMMU EVENT queue MSI中断地址低位配置寄存器。 */ +#define SMMU_S_EVENTQ_IRQ_CFG0_1_REG \ + (CSR_SMMU_BASE + 0x80B4) /* 安全状态下SMMU EVENT queue MSI中断地址高位配置寄存器。 */ +#define SMMU_S_EVENTQ_IRQ_CFG1_REG (CSR_SMMU_BASE + 0x80B8) /* 安全状态下SMMU EVENT queue MSI中断数据配置寄存器。 */ +#define SMMU_S_EVENTQ_IRQ_CFG2_REG (CSR_SMMU_BASE + 0x80BC) /* 安全状态下SMMU EVENT queue MSI中断属性配置寄存器。 */ +#define SMMU_USER_CONFIG0_REG (CSR_SMMU_BASE + 0xE00) /* SMMU USER配置0寄存器。 */ +#define SMMU_USER_CONFIG1_REG (CSR_SMMU_BASE + 0xE04) /* SMMU USER配置1寄存器。 */ +#define SMMU_VERI_ID_REG (CSR_SMMU_BASE + 0xE08) /* SMMU 验证版本寄存器。 */ +#define SMMU_PROD_INFO_REG (CSR_SMMU_BASE + 0xE0C) /* SMMU版本标志寄存器。 */ +#define SMMU_USER_CONFIG2_REG (CSR_SMMU_BASE + 0xE10) /* SMMU USER配置2寄存器。 */ +#define SMMU_PCIE_IRPT_EN_REG (CSR_SMMU_BASE + 0xE14) /* SMMU 向PCIE发MSI中断使能寄存器。 */ +#define SMMU_PCIE_IRPT_ADDR_REG (CSR_SMMU_BASE + 0xE18) /* SMMU 向PCIE发MSI中断地址寄存器。 */ +#define SMMU_PCIE_IRPT_DATA_REG (CSR_SMMU_BASE + 0xE1C) /* SMMU 向PCIE发MSI中断数据寄存器。 */ +#define SMMU_USER_CONFIG3_REG (CSR_SMMU_BASE + 0xE20) /* SMMU USER配置3寄存器。 */ +#define SMMU_USER_CONFIG4_REG (CSR_SMMU_BASE + 0xE24) /* SMMU USER配置4寄存器。 */ +#define DFX_CMD_NS_CONS_CNT0_REG (CSR_SMMU_BASE + 0xE28) /* 保留寄存器 */ +#define DFX_CMD_NS_CONS_CNT1_REG (CSR_SMMU_BASE + 0xE2C) /* 保留寄存器 */ +#define SMMU_SKY_QUEUE_POINTER_SP_REG (CSR_SMMU_BASE + 0xE30) /* SMMU SKY QUEUE查询指针寄存器。 */ +#define SMMU_SKY_QUEUE_ADDR_LOW_SP_REG (CSR_SMMU_BASE + 0xE34) /* SMMU SKY QUEUE查询命令地址(低位)寄存器。 */ +#define SMMU_SKY_QUEUE_ADDR_HIGH_SP_REG (CSR_SMMU_BASE + 0xE38) /* SMMU SKY QUEUE查询命令地址(高位)寄存器。 */ +#define SMMU_SKY_QUEUE_STAT0_SP_REG (CSR_SMMU_BASE + 0xE3C) /* SMMU SKY QUEUE查询命令状态0寄存器。 */ +#define SMMU_SKY_QUEUE_STAT1_SP_REG (CSR_SMMU_BASE + 0xE40) /* SMMU SKY QUEUE查询命令状态1寄存器。 */ +#define SMMU_SKY_QUEUE_POINTER_TP_REG (CSR_SMMU_BASE + 0xE50) /* SMMU SKY QUEUE查询指针寄存器。 */ +#define SMMU_SKY_QUEUE_ADDR_LOW_TP_REG (CSR_SMMU_BASE + 0xE54) /* SMMU SKY QUEUE查询命令地址(低位)寄存器。 */ +#define SMMU_SKY_QUEUE_ADDR_HIGH_TP_REG (CSR_SMMU_BASE + 0xE58) /* SMMU SKY QUEUE查询命令地址(高位)寄存器。 */ +#define SMMU_SKY_QUEUE_STAT0_TP_REG (CSR_SMMU_BASE + 0xE5C) /* SMMU SKY QUEUE查询命令状态0寄存器。 */ +#define SMMU_SKY_QUEUE_STAT1_TP_REG (CSR_SMMU_BASE + 0xE60) /* SMMU SKY QUEUE查询命令状态1寄存器。 */ +#define SMMU_DFX_CMD_NUM_REG (CSR_SMMU_BASE + 0xE70) /* SMMU正在处理命令个数统计寄存器。 */ +#define SMMU_DFX_CMD_QUEUE_STAT0_REG (CSR_SMMU_BASE + 0xE74) /* SMMU Command命令统计寄存器0。 */ +#define SMMU_DFX_FAULT_NUM_REG (CSR_SMMU_BASE + 0xE78) /* SMMU发生Fault个数统计寄存器。 */ +#define SMMU_DFX_TEST_MONITOR_SP_REG (CSR_SMMU_BASE + 0xE7C) /* SP接口测试监控寄存器。 */ +#define SMMU_DFX_TEST_MONITOR_TP_REG (CSR_SMMU_BASE + 0xE80) /* TP接口测试监控寄存器。 */ +#define SMMU_DFX_ECC_MONITOR_REG (CSR_SMMU_BASE + 0xE84) /* ECC ERR监控寄存器。 */ +#define SMMU_STALL_QUEUE_STAT0_SP_REG (CSR_SMMU_BASE + 0xE90) /* SMMU SP端口STALL命令状态0寄存器。 */ +#define SMMU_STALL_QUEUE_STAT1_SP_REG (CSR_SMMU_BASE + 0xE94) /* SMMU SP端口STALL命令状态1寄存器。 */ +#define SMMU_STALL_QUEUE_STAT0_TP_REG (CSR_SMMU_BASE + 0xE98) /* SMMU TP端口STALL命令状态0寄存器。 */ +#define SMMU_STALL_QUEUE_STAT1_TP_REG (CSR_SMMU_BASE + 0xE9C) /* SMMU TP端STALL命令状态1寄存器。 */ +#define SMMU_ECC_INJECT_REG (CSR_SMMU_BASE + 0xEA0) /* SMMU ECC错误注入寄存器。 */ +#define SMMU_PTW_STATUS_0_REG (CSR_SMMU_BASE + 0xEA4) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_1_REG (CSR_SMMU_BASE + 0xEA8) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_2_REG (CSR_SMMU_BASE + 0xEAC) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_3_REG (CSR_SMMU_BASE + 0xEB0) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_S2_0_REG (CSR_SMMU_BASE + 0xEB4) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_S2_1_REG (CSR_SMMU_BASE + 0xEB8) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_S2_2_REG (CSR_SMMU_BASE + 0xEBC) /* SMMU PTW状态寄存器。 */ +#define SMMU_PTW_STATUS_S2_3_REG (CSR_SMMU_BASE + 0xEC0) /* SMMU PTW状态寄存器。 */ +#define SMMU_DFX_CMD_QUEUE_STAT1_REG (CSR_SMMU_BASE + 0xEC4) /* SMMU Command命令统计寄存器1。 */ +#define SMMU_PMCG_EVCNTRN_0_0_REG (CSR_SMMU_BASE + 0x20000) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_1_REG (CSR_SMMU_BASE + 0x20008) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_2_REG (CSR_SMMU_BASE + 0x20010) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_3_REG (CSR_SMMU_BASE + 0x20018) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_4_REG (CSR_SMMU_BASE + 0x20020) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_5_REG (CSR_SMMU_BASE + 0x20028) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_6_REG (CSR_SMMU_BASE + 0x20030) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_0_7_REG (CSR_SMMU_BASE + 0x20038) /* Performance Monitor计数器低位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_0_REG (CSR_SMMU_BASE + 0x20004) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_1_REG (CSR_SMMU_BASE + 0x2000C) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_2_REG (CSR_SMMU_BASE + 0x20014) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_3_REG (CSR_SMMU_BASE + 0x2001C) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_4_REG (CSR_SMMU_BASE + 0x20024) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_5_REG (CSR_SMMU_BASE + 0x2002C) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_6_REG (CSR_SMMU_BASE + 0x20034) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVCNTRN_1_7_REG (CSR_SMMU_BASE + 0x2003C) /* Performance Monitor计数器高位寄存器。 */ +#define SMMU_PMCG_EVTYPERN_0_REG (CSR_SMMU_BASE + 0x20400) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_1_REG (CSR_SMMU_BASE + 0x20404) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_2_REG (CSR_SMMU_BASE + 0x20408) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_3_REG (CSR_SMMU_BASE + 0x2040C) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_4_REG (CSR_SMMU_BASE + 0x20410) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_5_REG (CSR_SMMU_BASE + 0x20414) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_6_REG (CSR_SMMU_BASE + 0x20418) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_EVTYPERN_7_REG (CSR_SMMU_BASE + 0x2041C) /* Performance Monitor配置event type寄存器。 */ +#define SMMU_PMCG_SVRN_0_0_REG (CSR_SMMU_BASE + 0x20600) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_1_REG (CSR_SMMU_BASE + 0x20608) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_2_REG (CSR_SMMU_BASE + 0x20610) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_3_REG (CSR_SMMU_BASE + 0x20618) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_4_REG (CSR_SMMU_BASE + 0x20620) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_5_REG (CSR_SMMU_BASE + 0x20628) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_6_REG (CSR_SMMU_BASE + 0x20630) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_0_7_REG (CSR_SMMU_BASE + 0x20638) /* shadow value low 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_0_REG (CSR_SMMU_BASE + 0x20604) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_1_REG (CSR_SMMU_BASE + 0x2060C) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_2_REG (CSR_SMMU_BASE + 0x20614) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_3_REG (CSR_SMMU_BASE + 0x2061C) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_4_REG (CSR_SMMU_BASE + 0x20624) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_5_REG (CSR_SMMU_BASE + 0x2062C) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_6_REG (CSR_SMMU_BASE + 0x20634) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SVRN_1_7_REG (CSR_SMMU_BASE + 0x2063C) /* shadow value high 32bit寄存器。 */ +#define SMMU_PMCG_SMRN_0_REG (CSR_SMMU_BASE + 0x20A00) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_1_REG (CSR_SMMU_BASE + 0x20A04) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_2_REG (CSR_SMMU_BASE + 0x20A08) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_3_REG (CSR_SMMU_BASE + 0x20A0C) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_4_REG (CSR_SMMU_BASE + 0x20A10) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_5_REG (CSR_SMMU_BASE + 0x20A14) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_6_REG (CSR_SMMU_BASE + 0x20A18) /* StreamID match寄存器。 */ +#define SMMU_PMCG_SMRN_7_REG (CSR_SMMU_BASE + 0x20A1C) /* StreamID match寄存器。 */ +#define SMMU_PMCG_CNTENSET0_0_REG (CSR_SMMU_BASE + 0x20C00) /* counter enable set low 32bit寄存器。 */ +#define SMMU_PMCG_CNTENSET0_1_REG (CSR_SMMU_BASE + 0x20C04) /* counter enable set high 32bit寄存器。 */ +#define SMMU_PMCG_CNTENCLR0_0_REG (CSR_SMMU_BASE + 0x20C20) /* counter enable clear low 32bit寄存器。 */ +#define SMMU_PMCG_CNTENCLR0_1_REG (CSR_SMMU_BASE + 0x20C24) /* counter enable clear high 32bit寄存器。 */ +#define SMMU_PMCG_INTENSET0_0_REG \ + (CSR_SMMU_BASE + 0x20C40) /* counter interrupt contribution enable low 32bit寄存器。 */ +#define SMMU_PMCG_INTENSET0_1_REG \ + (CSR_SMMU_BASE + 0x20C44) /* counter intterrupt contribution enable high 32bit寄存器。 */ +#define SMMU_PMCG_INTENCLR0_0_REG \ + (CSR_SMMU_BASE + 0x20C60) /* counter intterrupt contribution enable clean low 32bit寄存器。 */ +#define SMMU_PMCG_INTENCLR0_1_REG \ + (CSR_SMMU_BASE + 0x20C64) /* counter intterrupt contribution enable clean high 32bit寄存器。 */ +#define SMMU_PMCG_OVSCLR0_0_REG (CSR_SMMU_BASE + 0x20C80) /* overflow status clear low 32bit寄存器。 */ +#define SMMU_PMCG_OVSCLR0_1_REG (CSR_SMMU_BASE + 0x20C84) /* overflow status clear high 32bit寄存器。 */ +#define SMMU_PMCG_OVSSET0_0_REG (CSR_SMMU_BASE + 0x20CC0) /* overflow status set low 32bit寄存器。 */ +#define SMMU_PMCG_OVSSET0_1_REG (CSR_SMMU_BASE + 0x20CC4) /* overflow status set high 32bit寄存器。 */ +#define SMMU_PMCG_CAPR_REG (CSR_SMMU_BASE + 0x20D88) /* counter shadow value capture寄存器。 */ +#define SMMU_PMCG_SCR_REG (CSR_SMMU_BASE + 0x20DF8) /* secure control register寄存器。 */ +#define SMMU_PMCG_CFGR_REG (CSR_SMMU_BASE + 0x20E00) /* PMCG configuration information寄存器。 */ +#define SMMU_PMCG_CR_REG (CSR_SMMU_BASE + 0x20E04) /* control register寄存器。 */ +#define SMMU_PMCG_CEID0_0_REG (CSR_SMMU_BASE + 0x20E20) /* common event id bitmap寄存器。 */ +#define SMMU_PMCG_CEID0_1_REG (CSR_SMMU_BASE + 0x20E24) /* common event id bitmap寄存器。 */ +#define SMMU_PMCG_CEID1_0_REG (CSR_SMMU_BASE + 0x20E28) /* common event id bitmap寄存器。 */ +#define SMMU_PMCG_CEID1_1_REG (CSR_SMMU_BASE + 0x20E2C) /* common event id bitmap寄存器。 */ +#define SMMU_PMCG_IRQ_CTRL_REG (CSR_SMMU_BASE + 0x20E50) /* IRQ enable寄存器。 */ +#define SMMU_PMCG_IRQ_CTRLACK_REG (CSR_SMMU_BASE + 0x20E54) /* IRQ enable ack寄存器。 */ +#define SMMU_PMCG_IRQ_CFG0_0_REG (CSR_SMMU_BASE + 0x20E58) /* IRQ configuration0 low 32bit寄存器。 */ +#define SMMU_PMCG_IRQ_CFG0_1_REG (CSR_SMMU_BASE + 0x20E5C) /* IRQ configuration0 high 32bit寄存器。 */ +#define SMMU_PMCG_IRQ_CFG1_REG (CSR_SMMU_BASE + 0x20E60) /* IRQ configuration1寄存器。 */ +#define SMMU_PMCG_IRQ_CFG2_REG (CSR_SMMU_BASE + 0x20E64) /* IRQ configuration2寄存器。 */ +#define SMMU_PMCG_IRQ_STATUS_REG (CSR_SMMU_BASE + 0x20E68) /* MSI status寄存器。 */ +#define SMMU_PMCG_AIDR_REG (CSR_SMMU_BASE + 0x20E70) /* Architecture identification寄存器。 */ +#define SMMU_PMCG_CIDR0_REG (CSR_SMMU_BASE + 0x20FF0) /* Component ID0 */ +#define SMMU_PMCG_CIDR1_REG (CSR_SMMU_BASE + 0x20FF4) /* Component ID1 */ +#define SMMU_PMCG_CIDR2_REG (CSR_SMMU_BASE + 0x20FF8) /* Component ID2 */ +#define SMMU_PMCG_CIDR3_REG (CSR_SMMU_BASE + 0x20FFC) /* Component ID3 */ +#define SMMU_PMCG_PIDR0_REG (CSR_SMMU_BASE + 0x20FE0) /* Peripheral ID0 */ +#define SMMU_PMCG_PIDR1_REG (CSR_SMMU_BASE + 0x20FE4) /* Peripheral ID1 */ +#define SMMU_PMCG_PIDR2_REG (CSR_SMMU_BASE + 0x20FE8) /* Peripheral ID2 */ +#define SMMU_PMCG_PIDR3_REG (CSR_SMMU_BASE + 0x20FEC) /* Peripheral ID3 */ +#define SMMU_PMCG_PIDR4_REG (CSR_SMMU_BASE + 0x20FD0) /* Peripheral ID4 */ +#define SMMU_PMCG_PIDR5_REG (CSR_SMMU_BASE + 0x20FD4) /* Peripheral ID5 */ +#define SMMU_PMCG_PIDR6_REG (CSR_SMMU_BASE + 0x20FD8) /* Peripheral ID6 */ +#define SMMU_PMCG_PIDR7_REG (CSR_SMMU_BASE + 0x20FDC) /* Peripheral ID7 */ +#define SMMU_PMCG_PMAUTHSTATUS_REG (CSR_SMMU_BASE + 0x20FB8) /* AUTHSTATUS */ +#define SMMU_PMCG_PMDEVARCH_REG (CSR_SMMU_BASE + 0x20FBC) /* PMDEVARCH */ +#define SMMU_PMCG_PMDEVTYPE_REG (CSR_SMMU_BASE + 0x20FCC) /* PMDEVTYPE */ +#define SMMU_ERR_FR_0_REG (CSR_SMMU_BASE + 0x2000) /* RAS ERR FR0寄存器。 */ +#define SMMU_ERR_FR_1_REG (CSR_SMMU_BASE + 0x2004) /* RAS ERR FR1寄存器。 */ +#define SMMU_ERR_CTRL_0_REG (CSR_SMMU_BASE + 0x2008) /* RAS ERR CTRL0寄存器。 */ +#define SMMU_ERR_CTRL_1_REG (CSR_SMMU_BASE + 0x200C) /* RAS ERR CTRL1寄存器。 */ +#define SMMU_ERR_STATUS_0_REG (CSR_SMMU_BASE + 0x2010) /* RAS ERR STATUS0寄存器。 */ +#define SMMU_ERR_STATUS_1_REG (CSR_SMMU_BASE + 0x2014) /* RAS ERR STATUS1寄存器。 */ +#define SMMU_ERR_ADDR_0_REG (CSR_SMMU_BASE + 0x2018) /* RAS ERR ADDR0寄存器。 */ +#define SMMU_ERR_ADDR_1_REG (CSR_SMMU_BASE + 0x201C) /* RAS ERR ADDR1寄存器。 */ +#define SMMU_ERR_MISC0_0_REG (CSR_SMMU_BASE + 0x2020) /* RAS ERR MISC0寄存器。 */ +#define SMMU_ERR_MISC0_1_REG (CSR_SMMU_BASE + 0x2024) /* RAS ERR MISC0寄存器。 */ +#define SMMU_ERR_MISC1_0_REG (CSR_SMMU_BASE + 0x2028) /* RAS ERR MISC1寄存器。 */ +#define SMMU_ERR_MISC1_1_REG (CSR_SMMU_BASE + 0x202C) /* RAS ERR MISC1寄存器。 */ + +#endif // __SMMU_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sysctrl_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sysctrl_reg_offset.h new file mode 100644 index 000000000..ba77da0b9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/totem/sysctrl_reg_offset.h @@ -0,0 +1,316 @@ +// Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. +// File name : hi1823e_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/9/28 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2022/09/21 14:49:24 Create file +// ****************************************************************************** + +#ifndef __SYSCTRL_REG_OFFSET_H__ +#define __SYSCTRL_REG_OFFSET_H__ + +/* SYSCTRL_CFG Base address of Module's Register */ +#define CSR_SYSCTRL_CFG_BASE (0x94010000ULL) + +/******************************************************************************/ +/* SYSCTRL_CFG Registers' Definitions */ +/******************************************************************************/ + +#define CSR_SYSCTRL_CFG_SC_PLLFCTRL2_REG (CSR_SYSCTRL_CFG_BASE + 0x10) /* SC_PLLFCTRL2为CDIE_CRG的PLL1控制寄存器0。建议初始化是按照2660:32‘h7824_2145 配置 */ +#define CSR_SYSCTRL_CFG_SC_PLLFCTRL3_REG (CSR_SYSCTRL_CFG_BASE + 0x14) /* SC_PLLFCTRL3为CDIE_CRG的PLL1控制寄存器1。 */ +#define CSR_SYSCTRL_CFG_SC_PLLFCTRL4_REG (CSR_SYSCTRL_CFG_BASE + 0x20) /* SC_PLLFCTRL4为CDIE_CRG的PLL2控制寄存器0。建议初始化是按照2660:32‘h7824_2145 配置 */ +#define CSR_SYSCTRL_CFG_SC_PLLFCTRL5_REG (CSR_SYSCTRL_CFG_BASE + 0x24) /* SC_PLLFCTRL5为CDIE_CRG的PLL2控制寄存器1。 */ +#define CSR_SYSCTRL_CFG_SC_PLLFCTRL6_REG (CSR_SYSCTRL_CFG_BASE + 0x30) /* SC_PLLFCTRL6为CDIE_CRG的PLL3控制寄存器0。 */ +#define CSR_SYSCTRL_CFG_SC_PLLFCTRL7_REG (CSR_SYSCTRL_CFG_BASE + 0x34) /* SC_PLLFCTRL7为CIDE_CRG的PLL3控制寄存器1。 */ +#define CSR_SYSCTRL_CFG_SC_PLL_CLK_BYPASS0_REG (CSR_SYSCTRL_CFG_BASE + 0xA0) /* SC_PLL_CLK_BYPASS0为CDIE_CRG的PLL相关工作时钟选择。 */ +#define CSR_SYSCTRL_CFG_SC_PLL_CLK_BYPASS1_REG (CSR_SYSCTRL_CFG_BASE + 0xA4) /* SC_PLL_CLK_BYPASS1为CDIE_CRG的PLL相关工作时钟选择。 */ +#define CSR_SYSCTRL_CFG_SC_PLLCTRL_REG (CSR_SYSCTRL_CFG_BASE + 0xB0) /* SC_PLLCTRL为PLL控制寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_SYSMODE_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0xB4) /* SC_SYSMODE_CTRL为CDIE_CRG系统时钟工作模式控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HPM_CLK_SEL_REG (CSR_SYSCTRL_CFG_BASE + 0x104) /* HPM时钟频率选择寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_CLK_SEL_REG (CSR_SYSCTRL_CFG_BASE + 0x108) /* CPU启动MBIST时钟选择信号 */ +#define CSR_SYSCTRL_CFG_SC_TSENSORE_CLK_SEL_REG (CSR_SYSCTRL_CFG_BASE + 0x110) /* TSENSOR时钟频率选择寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_ALL_SCAN_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x150) /* SC_ALL_SCAN_CTRL为ALL_SCAN模式OCC时钟关断控制寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_SYSSOFTRST_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x200) /* SC_SYSSOFTRST_CTRL为TOTEM CRG系统软复位寄存器（无线产品应用中，请勿配置）。 */ +#define CSR_SYSCTRL_CFG_SC_WDOG_RESET_CFG_REG (CSR_SYSCTRL_CFG_BASE + 0x210) /* 看门狗溢出复位范围控制寄存器（无线产品应用中，请勿配置）。 */ +#define CSR_SYSCTRL_CFG_SC_PORN_ENABLE_REG (CSR_SYSCTRL_CFG_BASE + 0x220) /* 按键复位区分上电非上电选择 */ +#define CSR_SYSCTRL_CFG_SC_DDR_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x338) /* SC_DDR_CLK_EN为DDR的时钟使能寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDR_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x33C) /* SC_DDR_CLK_DIS为L3D的时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDR_EXMBITST_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x340) /* SC_DDR_EXMBITST_CLK_EN为DDR_EXMBITST的时钟使能寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDR_EXMBITST_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x344) /* SC_DDR_EXMBITST_CLK_DIS为DDR_EXMBITST的时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x350) /* SC_HHA_CLK_EN表示HHA逻辑时钟使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x354) /* SC_HHA_CLK_DIS表示HHA逻辑时钟禁止使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x400) /* SC_SLLC_CLK_EN表示SLLC逻辑时钟使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x404) /* SC_SLLC_CLK_DIS表示SLLC逻辑时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_RX_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x408) /* SC_sioe_RX_CLK_EN表示sioe_RX逻辑时钟使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_RX_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x40C) /* SC_sioe_RX_CLK_DIS表示sioe_RX逻辑时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x410) /* SC_SIOE_CLK_EN表示SSIOE逻辑时钟使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x414) /* SC_SIOE_CLK_DIS表示SLLC逻辑时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_TX_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x418) /* SC_SIOE_TX_CLK_EN表示SIOE_TX逻辑时钟使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_TX_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x41C) /* SC_SIOE_TX_CLK_DIS表示SIOE_TX逻辑时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_PROBE_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x480) /* PROBE时钟使能寄存器 */ +#define CSR_SYSCTRL_CFG_SC_PROBE_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x484) /* PROBE时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_REF_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x600) /* SC_REF_CLK_EN是clk_ref的时钟使能寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_REF_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x604) /* SC_REF_CLK_DIS是clk_ref时钟禁止寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_GPIO_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x608) /* SC_GPIO_CLK_EN是clk_gpio_db的时钟使能寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_GPIO_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x60C) /* SC_GPIO_CLK_DIS是clk_gpio_db时钟禁止寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x618) /* SC_DJTAG_CLKEN表示DJTAG逻辑时钟使能配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x61C) /* SC_DJTAG_CLK_DIS表示DJTAG逻辑时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_FUNC_MBIST_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x620) /* FUNC_MBIST时钟使能寄存器 */ +#define CSR_SYSCTRL_CFG_SC_FUNC_MBIST_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x624) /* FUNC_MBIST时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HPM_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x628) /* SC_HPM_CLK_EN是HPM的时钟使能寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_HPM_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x62C) /* SC_HPM_CLK_DIS是HPM时钟禁止寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x630) /* SC_SYSCNT_CLK_EN是clk_syscnt的时钟使能寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x634) /* SC_SYSCNT_CLK_DIS是clk_syscnt时钟禁止寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_ULTRASOC_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x640) /* SC_ULTRASOC_CLK_EN是ULTRASOC的时钟使能寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_ULTRASOC_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x644) /* SC_ULTRASOC_CLK_DIS是ULTRASOC时钟禁止寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_DCIP_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x650) /* SC_DCIP_CLK_EN的时钟使能寄存器。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DCIP_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x654) /* SC_DCIP_CLK_DIS是DCIP时钟禁止寄存器。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_HHA_MBIST_CLK_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x680) /* HHA mbsit时钟使能寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_MBIST_CLK_DIS_REG (CSR_SYSCTRL_CFG_BASE + 0x684) /* HHA mbsit时钟禁止寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xA28) /* SC_DDRC_RESET_REQ为CDIE内DDRC软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xA2C) /* SC_DDRC_RESET_DREQ为CDIE内DDRC软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_EXMBIST_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xA30) /* SC_DDRC_exmbist_RESET_REQ为CDIE内DDRC_exmbist软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_EXMBIST_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xA34) /* SC_ddrc_exmbist_RESET_DREQ为CDIE内ddrc_exmbist软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xA40) /* SC_HHA_RESET_REQ为HHA软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xA44) /* SC_HHA_RESET_DREQ为HHA软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB00) /* SC_SLLC_RESET_REQ表示SLLC的软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB04) /* SC_SLLC_RESET_DREQ表示SLLC的软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE0_RX_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB10) /* SLLC SIOE0 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE0_RX_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB14) /* SLLC SIOE0 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE1_RX_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB18) /* SLLC SIOE1 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE1_RX_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB1C) /* SLLC SIOE1 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE2_RX_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB20) /* SLLC SIOE2 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE2_RX_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB24) /* SLLC SIOE2 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE3_RX_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB28) /* SLLC SIOE3 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE3_RX_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB2C) /* SLLC SIOE3 RX通道软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB30) /* SC_SIOE_RESET_REQ表示SIOE的软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB34) /* SC_SIOE_RESET_DREQ表示SIOE的软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_TX_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB38) /* SC_SIOE_TX_RESET_REQ表示SIOE_TX的软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_TX_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB3C) /* SC_SIOE_TX_RESET_DREQ表示SIOE_TX的软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE_REGS_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB40) /* SLLC_SIOE_REGS软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE_REGS_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB44) /* SLLC_SIOE_REGS'的软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_REQ_PHY_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB48) /* DDR PHY软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_REQ_PHY_REGS_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB4C) /* DDR PHY的软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_ULTRASOC_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB50) /* ULTRASOC软复位请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_ULTRASOC__REGS_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xB54) /* ULTRASOC的软复位去请求控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_STATUS_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xC50) /* STATUS软复位请求信号(CPU外所有ras软复位请求）。 */ +#define CSR_SYSCTRL_CFG_SC_STATUS_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xC54) /* STATUS软复位去请求信号。 */ +#define CSR_SYSCTRL_CFG_SC_DCIP_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xC60) /* DCIPS软复位请求信号。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DCIP_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xC64) /* DCIP软复位去请求信号。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD18) /* SC_DJTAG_SRST_REQ表示DJTAG逻辑复位请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD1C) /* SC_DJTAG_SRST_DREQ表示DJTAG逻辑复位去请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_FUNC_MBIST_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD20) /* SC_FUNC_MBIST_RESET_REQ表示对当前FUNC_MBIST的RST_REQ信号的配置。 */ +#define CSR_SYSCTRL_CFG_SC_FUNC_MBIST_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD24) /* SC_FUNC_MBIST_RESET_DEREQ表示对当前FUNC_MBIST的RST_REQ信号的去复位。 */ +#define CSR_SYSCTRL_CFG_SC_HPM_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD28) /* SC_HPM_SRST_REQ表示DJTAG逻辑复位请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HPM_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD2C) /* SC_HPM_SRST_DREQ表示HPM逻辑复位去请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD30) /* SC_SYSCNT_SRST_REQ表示SYSCNT逻辑复位请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD34) /* SC_SYSCNT_SRST_DREQ表示SYSCNT逻辑复位去请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_MBIST_RESET_REQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD80) /* SC_HHA_MBIST_SRST_REQ表示逻辑复位请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_MBIST_RESET_DREQ_REG (CSR_SYSCTRL_CFG_BASE + 0xD84) /* SC_HHA_MBISST_SRST_DREQ表示逻辑复位去请求寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_CLK_SEL_REG (CSR_SYSCTRL_CFG_BASE + 0x2008) /* SYSCNT时钟选择寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_IO_MIRROR_CFG_REG (CSR_SYSCTRL_CFG_BASE + 0x2300) /* SIOE MIRROR配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DS3_CTRL_UP_REG (CSR_SYSCTRL_CFG_BASE + 0x2400) /* PAD DS3控制寄存器0 */ +#define CSR_SYSCTRL_CFG_SC_DS3_CTRL_DOWN_REG (CSR_SYSCTRL_CFG_BASE + 0x2404) /* PAD DS3控制寄存器1 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_ALARM_REG (CSR_SYSCTRL_CFG_BASE + 0x20C0) /* 片上温度传感器温度门限配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_SAMPLE_NUM_REG (CSR_SYSCTRL_CFG_BASE + 0x20C4) /* 硬件连读Tsensor温度值后取平均的配置寄存器（禁止配置为0x0和0x1） */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x20D0) /* 片上温度传感器Tsensor0工作参数配置。 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_VCALIB_REG (CSR_SYSCTRL_CFG_BASE + 0x20D4) /* Tsensor0配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DCIP_CORE_CTRL1_REG (CSR_SYSCTRL_CFG_BASE + 0x20E0) /* HIDCIP CORE控制寄存器1（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DCIP_CORE_CTRL2_REG (CSR_SYSCTRL_CFG_BASE + 0x20E4) /* HIDCIP CORE控制寄存器2（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DCIP_BIST_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x20E8) /* HIDCIP BIST控制寄存器（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_RCD_DRV_REG (CSR_SYSCTRL_CFG_BASE + 0x20F0) /* 0.8V CML信号输出驱动电流能力控制信号 */ +#define CSR_SYSCTRL_CFG_SC_RCD_SEL_REG (CSR_SYSCTRL_CFG_BASE + 0x20F4) /* 0.8V CML信号输出驱动电流能力控制信号 */ +#define CSR_SYSCTRL_CFG_SC_DBGACK_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x20FC) /* DBGACK 控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_ENABLE_REG (CSR_SYSCTRL_CFG_BASE + 0x2100) /* DDRC使用情况指示寄存器 */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_ENABLE_REG (CSR_SYSCTRL_CFG_BASE + 0x3500) /* CPU启动MBIST选择信号；芯片电路测试使用。 */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_DATAIN_REG (CSR_SYSCTRL_CFG_BASE + 0x3504) /* CPU启动MBIST，TMB电路数据和指令输入接口寄存器 */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_WRITE_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x3508) /* DFT MBIST模式下TMB电路CPU2TAP接口配置寄存器；芯片电路测试使用。 */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_SMS_FUNC_RESET_REG (CSR_SYSCTRL_CFG_BASE + 0x350C) /* CPU启动MBIST复位信号 */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_FUNC_RESET_REG (CSR_SYSCTRL_CFG_BASE + 0x3510) /* CPU启动MBIST请求信号 */ +#define CSR_SYSCTRL_CFG_SC_PLL_SRC_INT_REG (CSR_SYSCTRL_CFG_BASE + 0x4000) /* PLL中断源寄存器 */ +#define CSR_SYSCTRL_CFG_SC_PLL_INT_MASK_REG (CSR_SYSCTRL_CFG_BASE + 0x4004) /* PLL中断屏蔽寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_SRC_INT_REG (CSR_SYSCTRL_CFG_BASE + 0x4008) /* DJTAG中断源寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_INT_MASK_REG (CSR_SYSCTRL_CFG_BASE + 0x400C) /* DJTAG中断屏蔽寄存器 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_INT_REG (CSR_SYSCTRL_CFG_BASE + 0x4010) /* TSENSOR中断源寄存器 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_INT_MASK_REG (CSR_SYSCTRL_CFG_BASE + 0x4014) /* TSENSOR中断屏蔽寄存器 */ +#define CSR_SYSCTRL_CFG_SC_XTAL_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x4104) /* 晶振控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_ITCR_REG (CSR_SYSCTRL_CFG_BASE + 0x4108) /* 状态机测试使能寄存器 */ +#define CSR_SYSCTRL_CFG_SC_ITIR0_REG (CSR_SYSCTRL_CFG_BASE + 0x410C) /* 测试模式输入控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_ITOR_REG (CSR_SYSCTRL_CFG_BASE + 0x4110) /* 测试模式输出控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_CNT_DATA_CFG_REG (CSR_SYSCTRL_CFG_BASE + 0x4114) /* PLL切换COUNTER的初始值配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_CNT_STEP_RSV_CFG_REG (CSR_SYSCTRL_CFG_BASE + 0x4118) /* PLL切换COUNTER的递增配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_CNT_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x411C) /* CNT配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_IM_CTRL_REG (CSR_SYSCTRL_CFG_BASE + 0x4120) /* Intterrupt模式控制寄存器 */ +#define CSR_SYSCTRL_CFG_SC_IM_STAT_REG (CSR_SYSCTRL_CFG_BASE + 0x4124) /* Intterrupt模式状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_PROBE_SYSTEM_COUNTER_VALUE_REG (CSR_SYSCTRL_CFG_BASE + 0x4580) /* System Counter的DFX寄存器，可产生System Counter脉冲，用于多片间计数值的比对。 */ +#define CSR_SYSCTRL_CFG_SC_PROBE_SYSTEM_COUNTER_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x4584) /* System Counter的DFX寄存器，用于打开多片间计数值的比对功能。 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE0_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4600) /* SC_BROADCAST_DIE0_ADDR0表示CPU CORE EVENT广播到DIE0的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE0_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4604) /* SC_BROADCAST_DIE0_ADDR1表示CPU CORE EVENT广播到DIE0的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE1_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4610) /* SC_BROADCAST_DIE1_ADDR0表示CPU CORE EVENT广播到DIE1的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE1_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4614) /* SC_BROADCAST_DIE1_ADDR1表示CPU CORE EVENT广播到DIE1的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE2_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4620) /* SC_BROADCAST_DIE2_ADDR0表示CPU CORE EVENT广播到DIE2的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE2_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4624) /* SC_BROADCAST_DIE2_ADDR1表示CPU CORE EVENT广播到DIE2的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE3_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4630) /* SC_BROADCAST_DIE3_ADDR0表示CPU CORE EVENT广播到DIE3的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE3_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4634) /* SC_BROADCAST_DIE3_ADDR1表示CPU CORE EVENT广播到DIE3的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE4_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4640) /* SC_BROADCAST_DIE4_ADDR0表示CPU CORE EVENT广播到DIE4的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE4_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4644) /* SC_BROADCAST_DIE4_ADDR1表示CPU CORE EVENT广播到DIE4的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE5_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4650) /* SC_BROADCAST_DIE5_ADDR0表示CPU CORE EVENT广播到DIE5的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE5_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4654) /* SC_BROADCAST_DIE5_ADDR1表示CPU CORE EVENT广播到DIE5的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE6_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4660) /* SC_BROADCAST_DIE6_ADDR0表示CPU CORE EVENT广播到DIE6的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE6_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4664) /* SC_BROADCAST_DIE6_ADDR1表示CPU CORE EVENT广播到DIE6的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE7_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4670) /* SC_BROADCAST_DIE7_ADDR0表示CPU CORE EVENT广播到DIE7的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE7_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4674) /* SC_BROADCAST_DIE7_ADDR1表示CPU CORE EVENT广播到DIE7的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE8_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4680) /* SC_BROADCAST_DIE8_ADDR0表示CPU CORE EVENT广播到DIE8的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE8_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4684) /* SC_BROADCAST_DIE8_ADDR1表示CPU CORE EVENT广播到DIE8的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE9_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x4690) /* SC_BROADCAST_DIE9_ADDR0表示CPU CORE EVENT广播到DIE9的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE9_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x4694) /* SC_BROADCAST_DIE9_ADDR1表示CPU CORE EVENT广播到DIE9的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE10_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x46A0) /* SC_BROADCAST_DIE10_ADDR0表示CPU CORE EVENT广播到DIE10的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE10_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x46A4) /* SC_BROADCAST_DIE10_ADDR1表示CPU CORE EVENT广播到DIE10的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE11_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x46B0) /* SC_BROADCAST_DIE11_ADDR0表示CPU CORE EVENT广播到DIE11的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE11_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x46B4) /* SC_BROADCAST_DIE11_ADDR1表示CPU CORE EVENT广播到DIE11的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE12_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x46C0) /* SC_BROADCAST_DIE12_ADDR0表示CPU CORE EVENT广播到DIE12的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE12_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x46C4) /* SC_BROADCAST_DIE12_ADDR1表示CPU CORE EVENT广播到DIE12的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE13_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x46D0) /* SC_BROADCAST_DIE13_ADDR0表示CPU CORE EVENT广播到DIE13的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE13_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x46D4) /* SC_BROADCAST_DIE13_ADDR1表示CPU CORE EVENT广播到DIE13的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE14_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x46E0) /* SC_BROADCAST_DIE14_ADDR0表示CPU CORE EVENT广播到DIE14的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE14_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x46E4) /* SC_BROADCAST_DIE14_ADDR1表示CPU CORE EVENT广播到DIE14的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE15_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0x46F0) /* SC_BROADCAST_DIE15_ADDR0表示CPU CORE EVENT广播到DIE15的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_DIE15_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0x46F4) /* SC_BROADCAST_DIE15_ADDR1表示CPU CORE EVENT广播到DIE15的地址配置 */ +#define CSR_SYSCTRL_CFG_SC_BROADCAST_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x4700) /* SC_BROADCAST_EN表示CPU CORE EVENT_EN的broadcast使能 */ +#define CSR_SYSCTRL_CFG_SC_RECEIVE_BROADCAST_EVENT_REG (CSR_SYSCTRL_CFG_BASE + 0x4710) /* SC_RECEIVE_BROADCAST表示SYSCTRL接收来自其他CPU CORE的 EVENT广播 */ +#define CSR_SYSCTRL_CFG_SC_POE_EVENT_EN_REG (CSR_SYSCTRL_CFG_BASE + 0x4720) /* POE的Event选择使能 */ +#define CSR_SYSCTRL_CFG_SC_PLL_LOCK_STATUS_REG (CSR_SYSCTRL_CFG_BASE + 0x5000) /* PLL锁定状态寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_PLLCTRL_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5004) /* SC_PLLCTRL_ST为PLL状态寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_SYSMODE_STATUS_REG (CSR_SYSCTRL_CFG_BASE + 0x50B4) /* SC_CTRL为系统时钟工作状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_WARM_RST_ACKED_REG (CSR_SYSCTRL_CFG_BASE + 0x5200) /* SC_DDRC_WARM_RST_ACKED表示CRG检测到非上电的系统复位的warn_rst_req请求的DDRC握手信号 */ +#define CSR_SYSCTRL_CFG_SC_DDR_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5338) /* SC_DDR_CLK_ST为DDR的时钟状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDR_EXMBIST_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5340) /* SC_DDR_EXMBIST_CLK_ST为DDR_EXMBIST的时钟状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5350) /* SC_HHA_CLK_ST表示HHA逻辑时钟状态 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5400) /* SC_SLLC_CLK_ST表示SLLC的当前时钟状态 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_RX_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5408) /* SC_sioe_RX_CLK_ST表示sioe_RX的当前时钟状态 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5410) /* SC_SIOE_CLK_ST表示SLLC的当前时钟状态 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_TX_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5418) /* SC_SIOE_TX_CLK_ST表示SLLC的当前时钟状态 */ +#define CSR_SYSCTRL_CFG_SC_PROBE_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5480) /* PROBE时钟状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_REF_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5600) /* SC_REF_CLK_ST表示CDIE_CRG内ref_clk的时钟状态。 */ +#define CSR_SYSCTRL_CFG_SC_GPIO_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5608) /* SC_GPIO_CLK_ST表示CDIE_CRG内gpio_db_clk的时钟状态。 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5618) /* SC_DJTAG_CLK_ST表示DJTAG相关逻辑时钟状态 */ +#define CSR_SYSCTRL_CFG_SC_FUNC_MBIST_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5620) /* FUNC_MBIST时钟状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HPM_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5628) /* SC_HPM_CLK_ST表示CDIE_CRG内hpm_clk的时钟状态。 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5630) /* SC_SYSCNT_CLK_ST表示CDIE_CRG内syscnt_clk的时钟状态。 */ +#define CSR_SYSCTRL_CFG_SC_ULTRASOC_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5640) /* SC_ULTRASOC_CLK_ST表示ULTRASOC的时钟状态。 */ +#define CSR_SYSCTRL_CFG_SC_DCBIST_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5650) /* SC_DCBIST_CLK_ST表示DCIP的时钟状态。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_HHA_MBIST_CLK_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5680) /* SC_HHA_MBIST_CLK_ST表示DCIP的时钟状态。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DDRC_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5A28) /* SC_DDRC_RESET_ST为CDIE内DDRC软复位状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DDRC_EXMBIST_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5A30) /* SC_DDRC_EXMBIST_RESET_ST为CDIE内DDRC_EXMBIST软复位状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_HHA_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5A40) /* SC_HHA_SRST_ST表示HHA逻辑复位状态 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B00) /* SC_SLLC_RESET_STAT表示SLLC的当前软复位状态 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE0_RX_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B10) /* SLLC SIOE0 RX通道软复位状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE1_RX_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B18) /* SLLC SIOE1 RX通道软复位状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE2_RX_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B20) /* SLLC SIOE2 RX通道软复位状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE3_RX_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B28) /* SLLC SIOE3 RX通道软复位状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B30) /* SC_SIOE_RESET_STAT表示SIOE的当前软复位状态 */ +#define CSR_SYSCTRL_CFG_SC_SIOE_TX_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B38) /* SC_SIOE_TX_RESET_STAT表示SIOE_TX的当前软复位状态 */ +#define CSR_SYSCTRL_CFG_SC_SLLC_SIOE_REGS_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B40) /* SLLC_SIOE_REGS的当前软复位状态 */ +#define CSR_SYSCTRL_CFG_SC_REQ_PHY_REGS_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B48) /* DDR PHY的当前软复位状态 */ +#define CSR_SYSCTRL_CFG_SC_ULTRASOC_REGS_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5B50) /* ULTRASOC的当前软复位状态 */ +#define CSR_SYSCTRL_CFG_SC_STATUS_TRESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5C50) /* STATUS的RST_REQ信号的状态。 */ +#define CSR_SYSCTRL_CFG_SC_DCIP_TRESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5C60) /* DCIP的RST_REQ信号的状态。（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5D18) /* SC_DJTAG_SRST_ST表示DJTAG相关逻辑复位状态 */ +#define CSR_SYSCTRL_CFG_SC_FUNC_MBIST_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5D20) /* SC_FUNC_MBIST_RESET_ST表示对当前FUNC_MBIST的RST_REQ信号的状态。 */ +#define CSR_SYSCTRL_CFG_SC_HPM_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5D28) /* SC_HPM_SRST_ST表示HPM相关逻辑复位状态 */ +#define CSR_SYSCTRL_CFG_SC_SYSCNT_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5D30) /* SC_SYSCNT_SRST_ST表示DJTAG相关逻辑复位状态 */ +#define CSR_SYSCTRL_CFG_SC_HHA_MBSIT_RESET_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x5D80) /* SC_HHA_MBSIT_RESET_ST表示相关逻辑复位状态 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x60D0) /* tsensor系统状态寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR1_TEMP_SAMPLE_AVERAGE_REG (CSR_SYSCTRL_CFG_BASE + 0x60D4) /* 芯片温度采样值 */ +#define CSR_SYSCTRL_CFG_SC_DCIP_ST1_REG (CSR_SYSCTRL_CFG_BASE + 0x60E0) /* DCIP状态寄存器1（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_DCIP_ST2_REG (CSR_SYSCTRL_CFG_BASE + 0x60E4) /* DCIP状态寄存器2（Hi1620s禁止使用） */ +#define CSR_SYSCTRL_CFG_SC_MBIST_CPUI_DATAOUT_REG (CSR_SYSCTRL_CFG_BASE + 0x7500) /* DFT MBIST模式下读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_PLL_INT_STATUS_REG (CSR_SYSCTRL_CFG_BASE + 0x8000) /* PLL中断状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_INT_STATUS_REG (CSR_SYSCTRL_CFG_BASE + 0x8008) /* DJTAG中断状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_TSENSOR_INT_STATUS_REG (CSR_SYSCTRL_CFG_BASE + 0x8010) /* TSENSOR中断状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_XTAL_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x8104) +#define CSR_SYSCTRL_CFG_SC_CNT_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x8108) +#define CSR_SYSCTRL_CFG_SC_ITIR0_TEST_REG (CSR_SYSCTRL_CFG_BASE + 0x810C) +#define CSR_SYSCTRL_CFG_SC_ITOR_TEST_REG (CSR_SYSCTRL_CFG_BASE + 0x8110) +#define CSR_SYSCTRL_CFG_SC_CNT_DATA_REG (CSR_SYSCTRL_CFG_BASE + 0x8114) /* PLL切换COUNTER的值状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_AXI_ACC_ST_REG (CSR_SYSCTRL_CFG_BASE + 0x8504) +#define CSR_SYSCTRL_CFG_SC_DJTAG_SEC_ACC_EN_REG (CSR_SYSCTRL_CFG_BASE + 0xD800) /* DJTAG访问各模块内安全世界寄存器的安全访问控制使能。（注意：1，此寄存器空间必须是安全访问才能成功。） */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_MSTR_ADDR_REG (CSR_SYSCTRL_CFG_BASE + 0xD810) /* SC_DJTAG_MSTR_ADDR为DJTAG Master配置访问模块的偏移地址寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_MSTR_DATA_REG (CSR_SYSCTRL_CFG_BASE + 0xD814) /* SC_DJTAG_MSTR_DATA为DJTAG Master的写数据 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_MSTR_CFG_REG (CSR_SYSCTRL_CFG_BASE + 0xD818) /* SC_DJTAG_MSTR_CFG为DJTAG Master的配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_MSTR_START_EN_REG (CSR_SYSCTRL_CFG_BASE + 0xD81C) /* SC_DJTAG_MSTR_START_EN为DJTAG Master访问chain链的start使能 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_MSTR_PIPE_CFG_REG (CSR_SYSCTRL_CFG_BASE + 0xD820) /* DJTAG_MSTR PIPELINE配置寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_TMOUT_REG (CSR_SYSCTRL_CFG_BASE + 0xD840) /* SC_DJTAG_TMOUT为IDIE中DJTAG Master的状态机超时阈值 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_SEC_MODE_REG (CSR_SYSCTRL_CFG_BASE + 0xD844) /* DJTAG安全访问模式寄存器。 */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_SEC_ACC_EN_REG (CSR_SYSCTRL_CFG_BASE + 0xDA00) /* sysctrl内AXI Master访问DDR安全地址空间的安全访问控制使能。（注意：1，此寄存器空间必须是安全访问才能成功。） */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_USER_REG (CSR_SYSCTRL_CFG_BASE + 0xDA04) /* SC_AXI_MSTR_USER表示SYS_CTRL内AXI Master的虚拟机ID */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_DATA0_REG (CSR_SYSCTRL_CFG_BASE + 0xDA08) /* SC_AXI_MSTR_DATA0为SYS_CTRL内AXI Master的访问数据bit[31:0] */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_DATA1_REG (CSR_SYSCTRL_CFG_BASE + 0xDA0C) /* SC_AXI_MSTR_DATA1为SYS_CTRL内AXI Master的访问数据bit[63:32] */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_DATA2_REG (CSR_SYSCTRL_CFG_BASE + 0xDA10) /* SC_AXI_MSTR_DATA2为SYS_CTRL内AXI Master的访问数据bit[95:64] */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_DATA3_REG (CSR_SYSCTRL_CFG_BASE + 0xDA14) /* SC_AXI_MSTR_DATA3为SYS_CTRL内AXI Master的访问数据bit[127:96] */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_WR_USER_REG (CSR_SYSCTRL_CFG_BASE + 0xDA18) /* SC_AXI_MSTR_WR_USER为SYS_CTRL内AXI Master读写使能 */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_ADDR0_REG (CSR_SYSCTRL_CFG_BASE + 0xDA1C) /* SC_AXI_MSTR_ADDR0为SYS_CTRL内AXI Master的访问地址bit[31:0] */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_ADDR1_REG (CSR_SYSCTRL_CFG_BASE + 0xDA20) /* SC_AXI_MSTR_ADDR1为SYS_CTRL内AXI Master的访问地址bit[63:32] */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_START_EN_REG (CSR_SYSCTRL_CFG_BASE + 0xDA24) /* SC_AXI_MSTR_START_EN表示SYS_CTRL内AXI Master的start使能 */ +#define CSR_SYSCTRL_CFG_SC_EFUSE_SECURE_INFO_REG (CSR_SYSCTRL_CFG_BASE + 0xE050) /* EFUSE中的安全访问查询 */ +#define CSR_SYSCTRL_CFG_SC_BOOT_INFO_REG (CSR_SYSCTRL_CFG_BASE + 0xE088) /* SC_BOOT_CTRL_CFG_ST表示CPU启动控制信号经过配置后最终状态 */ +#define CSR_SYSCTRL_CFG_SC_PAD_INFO_REG (CSR_SYSCTRL_CFG_BASE + 0xE08C) /* 板级过来的PAD信息 */ +#define CSR_SYSCTRL_CFG_SC_LAST_RST_STATUS_REG (CSR_SYSCTRL_CFG_BASE + 0xE090) /* SC_LAST_RST_STATUS表示芯片最后一次复位的复位状态 */ +#define CSR_SYSCTRL_CFG_SC_BOARD_CFG_INFO_REG (CSR_SYSCTRL_CFG_BASE + 0xE094) /* 单板配置信息状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_EFUSE_HARD_REPAIR_DONE_REG (CSR_SYSCTRL_CFG_BASE + 0xE098) /* EFUSE的hard_repair_done查询 */ +#define CSR_SYSCTRL_CFG_SC_JTAG_AUTH_RESULT_REG (CSR_SYSCTRL_CFG_BASE + 0xE100) /* 鉴权结果寄存器 */ +#define CSR_SYSCTRL_CFG_SYSCTRL_CFG_VERSION0_REG (CSR_SYSCTRL_CFG_BASE + 0xE0A0) /* VERSION寄存器0 */ +#define CSR_SYSCTRL_CFG_SYSCTRL_CFG_MAGIC_WORD_REG (CSR_SYSCTRL_CFG_BASE + 0xE0A4) /* SYSCTRL_CFG 版本号锁定寄存器 */ +#define CSR_SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG0_REG (CSR_SYSCTRL_CFG_BASE + 0xE0A8) /* 用于ECO的冗余配置寄存器0 */ +#define CSR_SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG1_REG (CSR_SYSCTRL_CFG_BASE + 0xE0AC) /* 用于ECO的冗余配置寄存器1 */ +#define CSR_SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG2_REG (CSR_SYSCTRL_CFG_BASE + 0xE0B0) /* 用于ECO的冗余配置寄存器2 */ +#define CSR_SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG3_REG (CSR_SYSCTRL_CFG_BASE + 0xE0B4) /* 用于ECO的冗余配置寄存器3 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA0_REG (CSR_SYSCTRL_CFG_BASE + 0xE800) /* DJTAG扫描链上第一个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA1_REG (CSR_SYSCTRL_CFG_BASE + 0xE804) /* DJTAG扫描链上第二个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA2_REG (CSR_SYSCTRL_CFG_BASE + 0xE808) /* DJTAG扫描链上第三个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA3_REG (CSR_SYSCTRL_CFG_BASE + 0xE80C) /* DJTAG扫描链上第四个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA4_REG (CSR_SYSCTRL_CFG_BASE + 0xE810) /* DJTAG扫描链上第五个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA5_REG (CSR_SYSCTRL_CFG_BASE + 0xE814) /* DJTAG扫描链上第六个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA6_REG (CSR_SYSCTRL_CFG_BASE + 0xE818) /* DJTAG扫描链上第七个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA7_REG (CSR_SYSCTRL_CFG_BASE + 0xE81C) /* DJTAG扫描链上第八个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA8_REG (CSR_SYSCTRL_CFG_BASE + 0xE820) /* DJTAG扫描链上第九个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_RD_DATA9_REG (CSR_SYSCTRL_CFG_BASE + 0xE824) /* DJTAG扫描链上第十个模块读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_DJTAG_OP_ST_REG (CSR_SYSCTRL_CFG_BASE + 0xE828) /* DJTAG访问状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_AXI_RD_DATA0_REG (CSR_SYSCTRL_CFG_BASE + 0xEA00) /* AXI访问DDR的读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_AXI_RD_DATA1_REG (CSR_SYSCTRL_CFG_BASE + 0xEA04) /* AXI访问DDR的读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_AXI_RD_DATA2_REG (CSR_SYSCTRL_CFG_BASE + 0xEA08) /* AXI访问DDR的读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_AXI_RD_DATA3_REG (CSR_SYSCTRL_CFG_BASE + 0xEA0C) /* AXI访问DDR的读数据寄存器 */ +#define CSR_SYSCTRL_CFG_SC_AXI_MSTR_ST_REG (CSR_SYSCTRL_CFG_BASE + 0xEA10) /* AXI访问DDR返回状态寄存器 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_0_REG (CSR_SYSCTRL_CFG_BASE + 0xF000) /* 安全启动记录寄存器0（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_1_REG (CSR_SYSCTRL_CFG_BASE + 0xF004) /* 安全启动记录寄存器1（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_2_REG (CSR_SYSCTRL_CFG_BASE + 0xF008) /* 安全启动记录寄存器2（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_3_REG (CSR_SYSCTRL_CFG_BASE + 0xF00C) /* 安全启动记录寄存器3（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_4_REG (CSR_SYSCTRL_CFG_BASE + 0xF010) /* 安全启动记录寄存器4（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_5_REG (CSR_SYSCTRL_CFG_BASE + 0xF014) /* 安全启动记录寄存器5（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_6_REG (CSR_SYSCTRL_CFG_BASE + 0xF018) /* 安全启动记录寄存器6（寄存器无复位端）。 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_7_REG (CSR_SYSCTRL_CFG_BASE + 0xF01C) /* 无复位端寄存器7 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_8_REG (CSR_SYSCTRL_CFG_BASE + 0xF020) /* 无复位端寄存器8 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_9_REG (CSR_SYSCTRL_CFG_BASE + 0xF024) /* 无复位端寄存器9 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_10_REG (CSR_SYSCTRL_CFG_BASE + 0xF028) /* 无复位端寄存器10 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_11_REG (CSR_SYSCTRL_CFG_BASE + 0xF02C) /* 无复位端寄存器11 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_12_REG (CSR_SYSCTRL_CFG_BASE + 0xF030) /* 无复位端寄存器12 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_13_REG (CSR_SYSCTRL_CFG_BASE + 0xF034) /* 无复位端寄存器13 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_14_REG (CSR_SYSCTRL_CFG_BASE + 0xF038) /* 无复位端寄存器14 */ +#define CSR_SYSCTRL_CFG_SC_NORESET_15_REG (CSR_SYSCTRL_CFG_BASE + 0xF03C) /* 无复位端寄存器15 */ +#define CSR_SYSCTRL_CFG_SC_SYSCTRL_LOCK_REG (CSR_SYSCTRL_CFG_BASE + 0xF100) /* 系统控制器锁定寄存器。（注意：1，此寄存器空间必须是安全访问才能成功） */ +#define CSR_SYSCTRL_CFG_SC_SYSCTRL_UNLOCK_REG (CSR_SYSCTRL_CFG_BASE + 0xF110) /* 系统控制器解锁寄存器。（注意：1，此寄存器空间必须是安全访问才能成功） */ +#define CSR_SYSCTRL_CFG_SC_PROBE_MUX_SEL_REG (CSR_SYSCTRL_CFG_BASE + 0xF200) /* PROBE分组选择 */ +#define CSR_SYSCTRL_CFG_SC_ECO_RSV0_REG (CSR_SYSCTRL_CFG_BASE + 0xFF00) /* ECO 寄存器0 */ +#define CSR_SYSCTRL_CFG_SC_ECO_RSV1_REG (CSR_SYSCTRL_CFG_BASE + 0xFF04) /* ECO 寄存器1 */ +#define CSR_SYSCTRL_CFG_SC_ECO_RSV2_REG (CSR_SYSCTRL_CFG_BASE + 0xFF08) /* ECO 寄存器2 */ +#define CSR_SYSCTRL_CFG_SC_ECO_RSV3_REG (CSR_SYSCTRL_CFG_BASE + 0xFF0C) /* ECO 寄存器3 */ +#define CSR_SYSCTRL_CFG_SC_ECO_RSV4_REG (CSR_SYSCTRL_CFG_BASE + 0xFF10) /* ECO 寄存器4 */ +#define CSR_SYSCTRL_CFG_SC_ECO_RSV5_REG (CSR_SYSCTRL_CFG_BASE + 0xFF14) /* ECO 寄存器5 */ +#define CSR_SYSCTRL_CFG_SC_MONITOR_TEST0_REG (CSR_SYSCTRL_CFG_BASE + 0xFFF0) /* 测试寄存器 */ +#define CSR_SYSCTRL_CFG_SC_MONITOR_TEST1_REG (CSR_SYSCTRL_CFG_BASE + 0xFFF4) /* 测试寄存器 */ +#define CSR_SYSCTRL_CFG_FPGA_VER_REG (CSR_SYSCTRL_CFG_BASE + 0xFFFC) /* FPGA版本寄存器 */ + +#endif // __HI1823E_REG_OFFSET_H__ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/service_type_pub.h b/drivers/infiniband/hw/hiroce3/include/hw/service_type_pub.h new file mode 100644 index 000000000..3394ae3c0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/service_type_pub.h @@ -0,0 +1,135 @@ +/* ***************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2015-2022. All rights reserved. + ****************************************************************************** + File Name : service_type.h + Description : xxxxxxxx + History : + 1.date : 2015/3/9 + Modification : Creat file + +***************************************************************************** */ +#ifndef SERVICE_TYPE_PUB_H +#define SERVICE_TYPE_PUB_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/* ******** Macro Definition ******** */ +#define QU_FLUSH_SERVICETYPE_RSVD 0X1F +/* * + * Enum name : service_type_e + * @brief + * Description: is used to configure and query qpc entries. + */ +typedef enum { + SERVICE_TYPE_L2NIC = 1, + SERVICE_TYPE_ROCE = 2, + SERVICE_TYPE_CQ = 3, + SERVICE_TYPE_ROCEAA = 4, + SERVICE_TYPE_TOE, + SERVICE_TYPE_FCOE, + SERVICE_TYPE_DSWARE, + SERVICE_TYPE_FC, + SERVICE_TYPE_MIGRATE, + SERVICE_TYPE_REMOTE_DB = 15, + SERVICE_TYPE_RSVD = 15, + SERVICE_TYPE_ROCE_NOFAA = 16, + SERVICE_TYPE_ISN = 17, + SERVICE_TYPE_VROCE = 26, +} service_type_e; + +/* * + * Enum name : release_pro_type_e + * @brief xxxxxxxx + * Description: is used to indicate the protocol type when the thread is released. The protocol type must be aligned + * with the msg_pro_type and pkt_pro_type numbers. (The isch allocates threads based on the pro_type provided by the + * iq.) + */ +typedef enum { + RELEASE_PRO_TYPE_L2NIC = 0, + RELEASE_PRO_TYPE_GSO = 1, + RELEASE_PRO_TYPE_ROCE = 2, + RELEASE_PRO_TYPE_IOE = 9, + RELEASE_PRO_TYPE_TOE = 10, + RELEASE_PRO_TYPE_OVS_VXLAN = 10, + RELEASE_PRO_TYPE_FC_PARENT = 11, + RELEASE_PRO_TYPE_FC_CHILD = 11, + RELEASE_PRO_TYPE_SACL = 12, + RELEASE_PRO_TYPE_OVS = 13, + RELEASE_PRO_TYPE_CMDQ = 14, + RELEASE_PRO_TYPE_RSVD = 15, +} release_pro_type_e; + +/* * + * Enum name : msg_pro_type_e + * @brief xxxxxxxx + * Description: Indicates the protocol type (recommended for the same protocol type) and the pointer to the entry + * function when the thread is released in the msg process. Roce needs to reserve protype for subtype. + */ +typedef enum { + MSG_PRO_TYPE_L2NIC = 0, + MSG_PRO_TYPE_ROCE_ARMCQ = 0, + MSG_PRO_TYPE_GSO = 1, + MSG_PRO_TYPE_ROCE = 2, + MSG_PRO_TYPE_ROCE_RC_SEND = 3, + MSG_PRO_TYPE_ROCE_RC_SEND_IMME = 4, + MSG_PRO_TYPE_ROCE_RC_WRITE = 5, + MSG_PRO_TYPE_ROCE_RC_WRITE_IMME = 6, + MSG_PRO_TYPE_ROCE_RC_READ = 7, + MSG_PRO_TYPE_ROCE_RC_ATOMIC_CMPSWP = 8, + MSG_PRO_TYPE_ROCE_RC_ATOMIC_FETCHADD = 9, + MSG_PRO_TYPE_IWARP = 9, + MSG_PRO_TYPE_TOE = 10, + MSG_PRO_TYPE_FCOE_PARENT = 10, + MSG_PRO_TYPE_FCOE_CHILD = 11, + MSG_PRO_TYPE_ROCE_REMOTE_DB = 11, + MSG_PRO_TYPE_SACL = 12, + MSG_PRO_TYPE_OTHER_DB = 12, + MSG_PRO_TYPE_OVS = 13, + MSG_PRO_TYPE_VSW_TIMER = 13, + MSG_PRO_TYPE_ROCE_REMOTE = 14, + MSG_PRO_TYPE_IWARP_REMOTE = 14, + MSG_PRO_TYPE_FC_TASK_EVENT = 14, + MSG_PRO_TYPE_TIMER = 15, + MSG_PRO_TYPE_RSVD = 15, +} msg_pro_type_e; + +/* * + * Enum name : pkt_pro_type_e + * @brief xxxxxxxx + * Description: Indicate the protocol type and the pointer to the entry function when the thread is released in the PKT + * process. + */ +typedef enum { + PKT_PRO_TYPE_L2NIC = 0, + PKT_PRO_TYPE_GSO = 1, + PKT_PRO_TYPE_ROCE = 2, + PKT_PRO_TYPE_ROCE_RC_SEND_ONLY = 3, + PKT_PRO_TYPE_ROCE_RC_WRITE_ONLY = 4, + PKT_PRO_TYPE_ROCE_SEND_NOMAL = 5, + PKT_PRO_TYPE_ROCE_WRITE_NOMAL = 6, + PKT_PRO_TYPE_ROCE_READ = 7, + PKT_PRO_TYPE_ROCE_READ_RSP = 8, + PKT_PRO_TYPE_ROCE_ATOMIC_ACK = 8, + PKT_PRO_TYPE_ROCE_ACK = 9, + PKT_PRO_TYPE_IWARP = 9, + PKT_PRO_TYPE_TOE = 10, + PKT_PRO_TYPE_FCOE = 11, + PKT_PRO_TYPE_SACL = 12, + PKT_PRO_TYPE_OVS = 13, + PKT_PRO_TYPE_CMDQ = 14, + PKT_PRO_TYPE_RSVD = 15, +} pkt_pro_type_e; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif /* SERVICE_TYPE_PUB_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/smf_cache_type.h b/drivers/infiniband/hw/hiroce3/include/hw/smf_cache_type.h new file mode 100644 index 000000000..507257c64 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/smf_cache_type.h @@ -0,0 +1,142 @@ +/* ***************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2015-2022. All rights reserved. + ****************************************************************************** + File name: Smf_cache_type.h + Version No.: Draft + Generation date: September 1,: 2015 + Latest modification: + Function Description: Smf_cache_type.h header file + Function list: + Modification history: + 1. Date: September 1,: 2015 + Modify content: Create a file. + +***************************************************************************** */ + +#ifndef SMF_CACHE_TYPE_H +#define SMF_CACHE_TYPE_H + + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ +/* + extended API head for cache mode + 3 2 1 0 + 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | src |instance_id| op_id |A| |O|F|S|b| offset | Size| F:FI_S; b:bev + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | CID |Csi|Tag_Typ|Sub|Vcache_| Csi:Csize; Tag_Typ:Tag_Type; Sub:Sub_Type; + Vcache_:Vcache_sel + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | mem_index(Tag.data) | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | mem_index(Tag.data) | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | GPA | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | GPA | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | byte_enable | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | byte_enable | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + + extended API head for cache mode for WQE and bpc access + 3 2 1 0 + 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | src |instance_id| op_id |A| |O|F|S|b| offset | Size| F:FI_S; b:bev + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | |PCIE_Temple|Csi|Tag_Typ|Sub|Vcache_| PCIE_Temple:PCIE_Templete; Csi:Csize; + Tag_Typ:Tag_Type; Sub:Sub_Type; Vcache_:Vcache_sel + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | mem_index(Tag.data) | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | mem_index(Tag.data) | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | GPA | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | GPA | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | byte_enable | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + | byte_enable | + +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ +*/ + +/* +How to use the extended API head for cache mode: +The value of tag_type: is SMF_CACHE_TAG_TYPE_XXX. +sub_type: + If tag_type is set to SMF_CACHE_TAG_TYPE_P_CXT_RDMA, sub_type is set to SMF_CACHE_TAG_SUB_TYPE_VF_XID. + If tag_type is set to SMF_CACHE_TAG_TYPE_P_CXT_FT, sub_type is set to SMF_CACHE_TAG_SUB_TYPE_VF_XID/FP/GPA. + If tag_type is set to SMF_CACHE_TAG_TYPE_xxx_WQE, sub_type is set to SMF_CACHE_TAG_SUB_TYPE_SQ_WQE/RQ_WQE. + If tag_type is set to other values, the value of sub_type is fixed to 0. +*/ +typedef enum { + SMF_CACHE_TAG_TYPE_P_CXT_FT = 0, + SMF_CACHE_TAG_TYPE_P_CXT_RDMA = 1, + SMF_CACHE_TAG_TYPE_L2NIC_WQE = 2, + SMF_CACHE_TAG_TYPE_RDMA_WQE = 3, + + SMF_CACHE_TAG_TYPE_XOE_WQE = 4, + SMF_CACHE_TAG_TYPE_MPT = 5, + SMF_CACHE_TAG_TYPE_SRQN = 6, + SMF_CACHE_TAG_TYPE_CQN = 7, + + SMF_CACHE_TAG_TYPE_C_CXT = 8, + SMF_CACHE_TAG_TYPE_L3I = 9, + SMF_CACHE_TAG_TYPE_HASH_BUCKET = 0xA, + SMF_CACHE_TAG_TYPE_RDMA_GID = 0xB, + + SMF_CACHE_TAG_TYPE_LUN = 0xC, + SMF_CACHE_TAG_TYPE_TIMER = 0xD, + SMF_CACHE_TAG_TYPE_CID = 0xE, + SMF_CACHE_TAG_TYPE_GPA = 0xF, +} smf_cache_tag_type_e; + +typedef enum { + SMF_CACHE_TAG_SUB_TYPE_DEFAULT = 0, + + SMF_CACHE_TAG_SUB_TYPE_VF_XID = 0, + SMF_CACHE_TAG_SUB_TYPE_FP = 1, + SMF_CACHE_TAG_SUB_TYPE_GPA = 2, + + SMF_CACHE_TAG_SUB_TYPE_SQ_WQE = 0, + SMF_CACHE_TAG_SUB_TYPE_RQ_WQE = 1, +} smf_cache_tag_sub_type_e; + + +typedef enum { + SMF_RDMA_VIRTUAL_CACHE_QPC = 0, + SMF_RDMA_VIRTUAL_CACHE_MPT = 1, + SMF_RDMA_VIRTUAL_CACHE_SQ_WQE = 2, + SMF_RDMA_VIRTUAL_CACHE_RQ_WQE = 3, + + SMF_RDMA_VIRTUAL_CACHE_CQC_SRQC = 4, + SMF_RDMA_VIRTUAL_CACHE_GID = 4, // The virtual cache and CQC & SRQC of the GID are the same. + + SMF_RDMA_VIRTUAL_CACHE_RDMARC = 5, + SMF_RDMA_VIRTUAL_CACHE_DMTT = 6, + SMF_RDMA_VIRTUAL_CACHE_CMTT = 7, +} smf_rdma_virtual_cache_e; + + +typedef enum { + SMF_L2NIC_VIRTUAL_CACHE_SQ_CMDQ_WQE = 0, + SMF_L2NIC_VIRTUAL_CACHE_RQ_WQE = 1, +} smf_l2nic_virtual_cache_e; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif /* SMF_CACHE_TYPE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/smf_instance_id.h b/drivers/infiniband/hw/hiroce3/include/hw/smf_instance_id.h new file mode 100644 index 000000000..a1506eb57 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/smf_instance_id.h @@ -0,0 +1,168 @@ +/* ***************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2015-2022. All rights reserved. + ****************************************************************************** + File name: Smf_instance_id.h + Version No.: Draft + Generation date: June 29,: 2015 + Latest modification: + Function Description: Smf_instance_id.h header file + Function list: + Modification history: + 1. Date: June 29,: 2015 + Modify content: Create a file. + +***************************************************************************** */ + +#ifndef SMF_INSTANCE_ID +#define SMF_INSTANCE_ID + + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +#define SMF_MEM_BASE_FC_LT 0x100000 +#define SMF_MEM_FC_ENTRY_SIZE 128 +#define SMF_MEM_FC_TABLE_SIZE 4096 + +typedef enum { + SMF_MISC_F_FIAR_GLB_CLA = 15, // According to SMF FS, set CLA Load/Store to 1111 and instance to MISC_F. + + SMF_L2NIC_FIAR_SQ_CMDQ_WQE = 0, + SMF_L2NIC_FIAR_RQ_WQE = 1, + + SMF_HASH_F_FIAR_BKT_FLOW_TBL = 0, + SMF_HASH_F_FIAR_SHADOW_FLOW_TBL = 1, + + SMF_TIMER_FIAR_TW_SPOKE_INFO = 0, + + SMF_RDMA_FIAR_QPC = 0, + SMF_RDMA_FIAR_MPT = 1, + SMF_RDMA_FIAR_SQ_WQE = 2, + SMF_RDMA_FIAR_RQ_WQE = 3, + SMF_RDMA_FIAR_CQC_SRQC = 4, + SMF_RDMA_FIAR_RDMARC = 5, + SMF_RDMA_FIAR_DMTT = 6, + SMF_RDMA_FIAR_CMTT = 7, + SMF_RDMA_FIAR_BYPASS = 14, + + SMF_RDMA_FIAR_GID = 5, + + SMF_XOE_FIAR_QPC = 0, + SMF_XOE_FIAR_CHILD_CXT = 1, + SMF_XOE_FIAR_SQ_WQE = 2, + SMF_XOE_FIAR_RQ_SRQ_WQE = 3, + SMF_XOE_FIAR_CQC_SRQC_LUN = 4, + SMF_XOE_FIAR_L3_TMRLIST_XID2CID = 5, + SMF_XOE_FIAR_HT_BKT = 6, + SMF_XOE_FIAR_CLA = 7, + + SMF_IWARP_FIAR_QPC = 0, + SMF_IWARP_FIAR_MPT = 1, + SMF_IWARP_FIAR_SQ_WQE = 2, + SMF_IWARP_FIAR_RQ_WQE = 3, + + SMF_IWARP_FIAR_INNERQ = 5, + SMF_IWARP_FIAR_DMTT = 6, + SMF_IWARP_FIAR_CMTT = 7, + + SMF_CRYPT_FIAR_CHILD_CXT = 1, + SMF_CRYPT_FIAR_SCQC = 2, +} smf_fiar_virtual_cache_e; + +// The microcode can determine the pipeline to be accessed through the NodeID(17-20) to improve the performance. +// SMF_INST_xxx_yyy_zzz: xxx: stateful service name (RoCE, FCoE, TOE, OVS,....); +// Yyy:engine name (RDMA, TOE, HASH_F, IFOE,...) +// Zzz: Optional + + +// resvd: 0,1 + +#define SMF_INST_RSS_HASH (2) // Used by RSS hash + +#define SMF_INST_MISC_F (5) // Misc engine, used for root_cxt/bat access; global CLA update +#define SMF_INST_MISC_BANK_F (53) // Misc bank engine + +#define SMF_INST_L2NIC (6) // l2nic engine + +#define SMF_INST_TIMER (7) // timer engine + +#define SMF_INST_ROCE_RDMA (8) // rdma engine, used for roce, ---Timer(srv_typ =2 QPC, 288B); (srv_typ=3 CQC, 64) +#define SMF_INST_HASH_F_GPA (3) + +#define SMF_INST_TOE_SRQ_MANAGER 4 // SRQ Manager engine, used for toe service +#define SMF_INST_TOE_TOE 10 // TOE engine, used for toe service +#define SMF_INST_TOE_HASH_F 11 // HASH_F engine, used for toe service +#define SMF_INST_TOE_IFOE 12 // IFOE engine, used for toe service + +// IOE +#define SMF_INST_IOE_BHEAP 15 // Bheap engine, used for ioe service +#define SMF_INST_IOE_AA_FLOW_IFOE 16 // IFOE engine, used for ioe service +#define SMF_INST_IOE_HASH_F 17 // HASH_F engine, used for IOE Child Context + +// HASH_F engine, used for toe multi-host child hash, MUST be continuous +#define SMF_INST_TOE_HASH_MH0 22 // host 0 +#define SMF_INST_TOE_HASH_MH1 23 // host 1 +#define SMF_INST_TOE_HASH_MH2 24 // host 2 +#define SMF_INST_TOE_HASH_MH3 25 // host 3 + +#define SMF_INST_NVME (9) /* NVMe Egine */ +#define SMF_INST_VIRTIO SMF_INST_NVME /* virtio and nvme use the same engine with same instance id */ + +#define SMF_INST_DSW_VOLQ (43) // used for dsware volq cq_cqe_gen API and sq_fetch_wqe API + +// FC +#define SMF_INST_FC_IFOE \ + (18) // IFOE engine, used for FCoE/FC service ---Timer timer_off(96) //FCoE:parent_cxt=13; child_cxt=29; + // FC:parent_cxt=12; child_cxt=28 +#define SMF_INST_FC_HASH_F (21) // HASH_F engine, used for FCoE/FC service +#define SMF_INST_FC_BHEAP (19) // bheap engine(hierarchy), used for service +#define SMF_INST_FC_HASH_F_CHILD (31) // child hash +#define SMF_INST_FC_IFOE_SQ (14) // IFOE engine, used for FC SQ service : +#define SMF_INST_FC_SMF_LT (42) // FC used for extern child ctx + +#define SMF_INST_ROCE_NOFAA_S (20) // Bheap engine(hierarchy) Aging +// BHEAP/MISC_F + +#define SMF_INST_OVS_HASH_F_OVS_FLOW_TABLE 28 // HASH_F engine, used for OVS Flow Parent Context + +#define SMF_INST_PPA_HASH_F_FLOW_TABLE 15 /* HASH_F engine, used for ppa Flow Parent Context */ + +#define SMF_INST_VROCE_HASH_F_FLOW_TABLE (29) // HASH_F engine, used by vroce + +/* ROCE instance id */ +#define SMF_INST_ROCE_BHEAP (35) +#define SMF_INST_ROCE_DCQCN (36) +#define SMF_INST_ROCE_IPQCN (37) +#define SMF_INST_ROCE_CNT0 (38) +#define SMF_INST_ROCE_CNT1 (39) +#define SMF_INST_ROCE_DIF_TX_BHEAP (40) +#define SMF_INST_ROCE_DIF_RX_BHEAP (41) + +#define SMF_INST_ROCE_NOFAA_WQE2HOST_LT (16) // SMF_INST_IOE_IFOE +#define SMF_INST_ROCE_NOFAA_CMIDINFO_LT (17) +#define SMF_INST_ROCE_NOFAA_SQE_BHEAP 43 // SMF_INST_DSW_VOLQ +#define SMF_INST_ROCE_NOFAA_MQP_BHEAP 22 +#define SMF_INST_ROCE_ACT_HOST_BHEAP 48 +#define SMF_INST_ROCE_CCF_IP_BHEAP 51 +#define SMF_INST_ROCE_CCF_LOCK_BHEAP 52 + +#define SMF_INST_CTR_F_COUNTER_32 44 +#define SMF_INST_CTR_F_COUNTER_64 45 + +#define SMF_INST_CAR_F 50 + +#define SMF_INST_CRYPT_IPSEC 13 + +#define SMF_INST_VROCE_HASH_FLOW_TABLE 53 + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif /* SMF_INSTANCE_ID */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table.h new file mode 100644 index 000000000..9745d6aac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table.h @@ -0,0 +1,4079 @@ +/* ***************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2019. All rights reserved. + ****************************************************************************** + File Name : sml_table.h + Version : Initial Draft + Created : 2019/1/9 + Last Modified : + Description : SML table definition + Function List : + History : + 1.Date : 2019/1/9 + Modification: Created file +***************************************************************************** */ +#ifndef SML_TABLE_H +#define SML_TABLE_H + +#include "sml_table_pub.h" +#include "typedef.h" + +typedef struct tag_log_ctrl { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 mod_name : 4; + u32 log_level : 4; + u32 rsvd : 8; + u32 line_num : 16; +#else + u32 line_num : 16; + u32 rsvd : 8; + u32 log_level : 4; + u32 mod_name : 4; +#endif +} log_ctrl; + +/** + * Struct name: sml_glb_tbl_com_s + * @brief global_table structure type + * Description: global configuration table + */ +typedef struct tag_sml_glb_tbl_com_s { + /* enable and valid flag */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 master_host_id : 3; + u32 master_func_id : 5; + u32 hot_update_active_flag : 1; /* hot update flag:0-activating;1-activated */ + u32 local_switch_en : 1; /* Local switching enable bit in the container scenario. */ + u32 err_smac_check_off : 1; /* smac error packets, check_off enable (1), not drop,if 0,drop */ + u32 ipcs_err_rss_en : 1; /* IP checksum error packets, enable rss quadruple hash flag. */ + u32 lldp_fwd_en : 4; /* lldp forward enable(4 port) */ + u32 lacp_fwd_en : 4; /* lacp forward enable(4 port) */ + u32 virtio_idesc_size : 6; + u32 flex_en : 1; + u32 special_pro_to_up_flag : 1; /* 1-special protocal pkt to up; 0-to x86 */ + u32 l2nic_lb_md : 2; /* 2'b00 - NO load balance; + * 2'b01 - load balance based on queue id[0](load balance @ 2 SMF); + * 2'b10 - load balance based on queue id[1:0](load balance @ 4 SMF); + */ + u32 lbf_mode : 2; /* 0:disable;1:simple hash0(vf);2:simple hash1(qid);3:hash key */ + +#else + u32 lbf_mode : 2; /* 0:disable;1:simple hash0(vf);2:simple hash1(qid);3:hash key */ + u32 l2nic_lb_md : 2; + u32 special_pro_to_up_flag : 1; /* 1-special protocal pkt to up; 0-to x86 */ + u32 flex_en : 1; + u32 virtio_idesc_size : 6; + u32 lacp_fwd_en : 4; /* lacp forward enable(4 port) */ + u32 lldp_fwd_en : 4; /* lldp forward enable(4 port) */ + u32 ipcs_err_rss_en : 1; /* IP checksum error packets, enable rss quadruple hash flag. */ + u32 err_smac_check_off : 1; /* smac error packets, check_off enable (1), not drop,if 0,drop */ + u32 local_switch_en : 1; /* Local switching enable bit in the container scenario. */ + u32 hot_update_active_flag : 1; /* hot update flag:0-hotupdate;1-hotupdateend */ + u32 master_func_id : 5; + u32 master_host_id : 3; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 nic_id : 20; /* only nic id */ + u32 tso_mode : 1; /* 0:tso space used by software;1:L2NIC engine use tso space */ + u32 map_port_offset : 4; + u32 tso_space_size : 4; + u32 rsvd : 3; +#else + u32 rsvd : 3; + u32 tso_space_size : 4; + u32 map_port_offset : 4; + u32 tso_mode : 1; /* 0:tso space used by software;1:L2NIC engine use tso space */ + u32 nic_id : 20; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 storage_start_vf_id : 12; /* storage type virtio device start vf id£¨blk/scsi) */ + u32 lro_space_size : 4; + u32 rsvd : 2; + u32 l2nic_total_qps : 14; +#else + u32 l2nic_total_qps : 14; + u32 rsvd : 2; + u32 lro_space_size : 4; + u32 storage_start_vf_id : 12; /* storage type virtio device start vf id£¨blk/scsi) */ + +#endif + } bs; + u32 value; + } dw2; + + u8 mac_port_map[8]; /* index: mac port id, value: real port id. */ + u8 sml_id[4]; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 3; + u32 port_speed : 8; + u32 storage_multi_host : 1; + u32 storage_env : 1; + u32 port_num : 3; + u32 host_num : 3; + u32 port_mask : 2; + u32 host_mask : 2; + u32 port_shift : 2; + u32 host_shift : 2; + u32 master_func : 5; +#else + u32 master_func : 5; + u32 host_shift : 2; + u32 port_shift : 2; + u32 host_mask : 2; + u32 port_mask : 2; + u32 host_num : 3; + u32 port_num : 3; + u32 storage_env : 1; + u32 storage_multi_host : 1; + u32 port_speed : 8; + u32 rsvd : 3; +#endif + } bs; + u32 value; + } dw6; + u8 aa_lt_inst_id[4]; + u8 aa_ht_inst_id[4]; + u32 roce_tbl[6]; /* Reuse with roce_tbl. roce_tbl is only initialized and used in NPU. */ + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 roce_tbl_byte_24 : 8; /* roce_tbl[24], second last byte of roce_tbl, only use in NPU */ + u32 roce_tbl_byte_25 : 8; /* roce_tbl[25], last byte of roce_tbl, only use in NPU */ + u32 virtio_net_rq_ctrl_cos : 3; + u32 virtio_net_sq_cos : 3; + u32 virtio_storage_cos : 3; + u32 rsvd : 7; +#else + u32 rsvd : 7; + u32 virtio_storage_cos : 3; + u32 virtio_net_sq_cos : 3; + u32 virtio_net_rq_ctrl_cos : 3; + u32 roce_tbl_byte_25 : 8; /* roce_tbl[25], last byte of roce_tbl */ + u32 roce_tbl_byte_24 : 8; /* roce_tbl[24], second last byte of roce_tbl */ +#endif + } bs; + u32 value; + } dw15; +} sml_glb_tbl_com_s; + +/** + * Struct name: sml_glb_tbl_ovs_s + * Structure type of the @brief microcode ovs part information + * Data structure of the index 16 table in the Description: global configuration table + */ +typedef struct tag_sml_glb_tbl_ovs { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ovs_flow_flush_en : 1; + u32 ovs_forward_mode : 8; + u32 base_pf_id : 5; + u32 base_qpc_func : 12; + u32 qpc_pf_num : 6; +#else + u32 qpc_pf_num : 6; + u32 base_qpc_func : 12; + u32 base_pf_id : 5; + u32 ovs_forward_mode : 8; + u32 ovs_flow_flush_en : 1; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 flow_table_aging_time : 16; + u32 prefix_mac : 16; +#else + u32 prefix_mac : 16; + u32 flow_table_aging_time : 16; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ip_frag_upcall_limit_en : 1; + u32 ovs_etp_en : 2; + u32 rsvd2 : 2; + u32 ovs_fm_glb_thrd_en : 1; + u32 ovs_fm_glb_rule_en : 1; + u32 ovs_fm_glb_period_en : 1; + u32 ovs_vxlan_check_upcall : 1; + u32 host_id : 3; + u32 ppf_id : 6; + u32 bond_hash_policy : 3; + u32 bond_mode : 3; + u32 bond_id : 3; + u32 mc_offload_en : 1; + u32 rsvd : 4; +#else + u32 rsvd : 4; + u32 mc_offload_en : 1; + u32 bond_id : 3; + u32 bond_mode : 3; + u32 bond_hash_policy : 3; + u32 ppf_id : 6; + u32 host_id : 3; + u32 ovs_vxlan_check_upcall : 1; + u32 ovs_fm_glb_period_en : 1; + u32 ovs_fm_glb_rule_en : 1; + u32 ovs_fm_glb_thrd_en : 1; + u32 rsvd2 : 2; + u32 ovs_etp_en : 2; + u32 ip_frag_upcall_limit_en : 1; +#endif + } bs; + u32 value; + } dw2; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 qpc_cache_start : 12; + u32 qpc_cache_end : 12; + u32 qpc_bsize : 2; + u32 rsvd1 : 6; +#else + u32 rsvd1 : 6; + u32 qpc_bsize : 2; + u32 qpc_cache_end : 12; + u32 qpc_cache_start : 12; +#endif + } bs; + u32 value; + } dw3; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 timer_cache_start : 12; + u32 timer_cache_end : 12; + u32 timer_bsize : 2; + u32 rsvd1 : 6; + +#else + u32 rsvd1 : 6; + u32 timer_bsize : 2; + u32 timer_cache_end : 12; + u32 timer_cache_start : 12; +#endif + } bs; + u32 value; + } dw4; + + s32 mirror_session_ref_cnt; + u32 rsvd[10]; +} sml_glb_tbl_ovs_s; + +/** + * Struct name: sml_glb_tbl_ppa_s + * Structure type of the @brief microcode ppa part information + * Data structure of the index 18 table in the Description: global configuration table + */ +typedef struct tag_sml_glb_tbl_ppa { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ppa_mode_type : 1; /* 0 : XG, 1 : HG */ + u32 base_qpc_func : 13; + u32 qpc_pf_num : 6; + u32 ppf_id : 6; + u32 host_id : 2; + u32 ppa_flow_flush_en : 1; /* 0 : ppa flush disable, 1: ppa flush enable */ + u32 rsv : 3; +#else + u32 rsv : 3; + u32 ppa_flow_flush_en : 1; /* 0 : ppa flush disable, 1: ppa flush enable */ + u32 host_id : 2; + u32 ppf_id : 6; + u32 qpc_pf_num : 6; + u32 base_qpc_func : 13; + u32 ppa_mode_type : 1; /* 0 : XG, 1 : HG */ +#endif + } bs; + u32 value; + } dw0; + + u32 ppa_ipv4_table_mask; + + u32 ppa_ipv6_table_mask; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 bfilter_start_addr : 16; + u32 bfilter_length : 16; +#else + u32 bfilter_length : 16; + u32 bfilter_start_addr : 16; +#endif + } bs; + u32 value; + } dw1; + u32 rsvd[12]; +} sml_glb_tbl_ppa_s; + +/** + * Struct name: sml_glb_tbl_toe_cfg_s + * Structure type of the @brief microcode toe config information + * Data structure of the index 24 table in the Description: global configuration table + */ +typedef struct tag_sml_glb_tbl_toe_cfg { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 srq_mgr_cl_start : 10; + u32 srq_mgr_cl_end : 10; + u32 rsvd : 12; +#else + u32 rsvd : 12; + u32 srq_mgr_cl_end : 10; + u32 srq_mgr_cl_start : 10; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 wqe_cl_start : 10; + u32 wqe_cl_end : 10; + u32 rsvd : 12; +#else + u32 rsvd : 12; + u32 wqe_cl_end : 10; + u32 wqe_cl_start : 10; +#endif + } bs; + u32 value; + } dw1; + + u32 rsvd[14]; +} sml_glb_tbl_toe_cfg_s; + +/** + * Struct name: sml_glb_tbl_ucode_version_s + * Structure type of the @brief microcode version information + * Data structure of the index 1 table in the Description: global configuration table + */ +typedef struct tag_sml_glb_tbl_ucode_version { + u32 ucode_version[4]; + u32 ucode_compile_time[5]; + u32 rsvd[7]; +} sml_glb_tbl_ucode_version_s; + +/* +1.bank GPA addresses are divided based on hosts. Each host4 address has a total of 4*32B bank GPA addresses. + +2. Storage space allocation +Two global entry are allocated to store bank GPA, which are index5 and index6 respectively. (The start value of is 0.) +The 32B of the index5 stores the bank GPA of the host 0, and the 32B of the stores the bank GPA of the host 1. +The 32B of the index6 stores the bank GPA of the host 2, and the 32B of the stores the bank GPA of the host 3. +(The bank GPA data structure corresponding to each host is stored in the following format.) +*/ +typedef struct tag_sml_glb_tbl_bank_gpa { + u32 bank0_gpa_h32; + u32 bank0_gpa_l32; + + u32 bank1_gpa_h32; + u32 bank1_gpa_l32; + + u32 bank2_gpa_h32; + u32 bank2_gpa_l32; + + u32 bank3_gpa_h32; + u32 bank3_gpa_l32; + + u32 ppf_id; + u32 rsvd[7]; +} sml_glb_tbl_bank_gpa_s; + +/** + * Struct name: sml_funcfg_tbl_s + * @brief Function Configuration Table + * Description: Function configuration attribute table + dw0-dw7 public&nic&crypto + dw8-dw11 ovs&ppa&vbs + dw12-dw15 roce&toe&virtio + */ +typedef struct tag_sml_funcfg_tbl { + /* valid and enable flag */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; /* function valid: 0-invalid; 1-valid */ + u32 virtio_en : 1; + u32 ipsec_mode : 2; /* IPsec offload mode: 0-disable; 1-xfrm offload; 2-hw offload */ + u32 ovs_func_en : 1; /* ovs function enable: 0-disable; 1-enable */ + u32 roce_en : 1; + u32 toe_en : 1; + u32 drop_en : 1; /* Packet loss enable. This bit is used to discard packets when valid bit = 1 in the + function table is used. The solution to DCB dynamic configuration is extended. */ + u32 learn_en : 1; /* mac learn enable: 0-disable; 1-enable */ + u32 nic_spoofchk_en : 1; + u32 rss_en : 1; /* rss enable: 0-disable; 1-enable */ + u32 rxvlan_offload_en : 1; /* rx vlan offload enable: 0-disable; 1-enable */ + u32 vlan_filter_en : 1; + u32 lro_change : 1; + u32 lro_ipv4_en : 1; /* IPv4 LRO enable: 0-disable; 1-enable; */ + u32 lro_ipv6_en : 1; /* IPv6 LRO enable: 0-disable; 1-enable; */ + u32 icq_vld : 1; + u32 icq_mask : 5; + u32 unicast_mac_num : 2; + u32 lro_max_len : 8; +#else + u32 lro_max_len : 8; + u32 unicast_mac_num : 2; + u32 icq_mask : 5; + u32 icq_vld : 1; + u32 lro_ipv6_en : 1; /* IPv6 LRO enable: 0-disable; 1-enable; */ + u32 lro_ipv4_en : 1; /* IPv4 LRO enable: 0-disable; 1-enable; */ + u32 lro_change : 1; + u32 vlan_filter_en : 1; + u32 rxvlan_offload_en : 1; /* rx vlan offload enable: 0-disable; 1-enable */ + u32 rss_en : 1; /* rss enable: 0-disable; 1-enable */ + u32 nic_spoofchk_en : 1; + u32 learn_en : 1; /* mac learn enable: 0-disable; 1-enable */ + /* function table is used. The solution to DCB dynamic configuration is extended. */ + u32 drop_en : 1; /* Packet loss enable. This bit is used to discard packets when valid bit = 1 in the */ + u32 toe_en : 1; + u32 roce_en : 1; + u32 ovs_func_en : 1; /* ovs function enable: 0-disable; 1-enable */ + u32 ipsec_mode : 2; /* IPsec offload mode: 0-disable; 1-xfrm offload; 2-hw offload */ + u32 virtio_en : 1; + u32 valid : 1; /* function valid: 0-invalid; 1-valid */ +#endif + } bs; + + u32 value; + } dw0; + + /* common config */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 host_id : 3; /* host id: [0~3]. support up to 4 Host. */ + u32 mtu : 14; /* mtu value: [64-15500] */ + u32 vlan_mode : 1; /* vlan mode: 0-normal filter; 1-qinq filter; */ + u32 msix_occupied : 1; /* msix occupied: 0-not alloc msix for queue; 1-alloced msix for queue; */ + u32 mig_mgmt_valid : 1; /* migrate managment valid: 0-invalid; 1-valid */ + u32 vlan_id : 12; /* vlan id: [0~4095] */ +#else + u32 vlan_id : 12; /* vlan id: [0~4095] */ + u32 mig_mgmt_valid : 1; /* migrate managment valid: 0-invalid; 1-valid */ + u32 msix_occupied : 1; /* msix occupied: 0-not alloc msix for queue; 1-alloced msix for queue; */ + u32 vlan_mode : 1; /* vlan mode: 0-normal filter; 1-qinq filter; */ + u32 mtu : 14; /* mtu value: [64-15500] */ + u32 host_id : 3; /* host id: [0~3]. support up to 4 Host. */ + +#endif + } bs; + + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 nic_rx_mode : 5; /* nic_rx_mode: 0b00001: unicast mode + 0b00010: multicast mode + 0b00100: BC mode + 0b01000: all multicast mode + 0b10000: promisc mode */ + u32 def_pri : 3; /* default priority */ + u32 er_id : 4; /* edge relay id: [0~15]. support up to 16 er. */ + u32 er_fwd_type : 4; /* er forward type: 2-port; 3-fic; 4-trunk; other-unsupport */ + u32 er_fwd_id : 3; /* er forward id: fwd_type=2: forward ethernet port id + fwd_type=3: forward fic id(tb+tp) + fwd_type=4: forward trunk id */ + u32 cfg_rq_num : 9; + u32 local_switch_lro_en : 1; + u32 bond_bifur_en : 1; + u32 flow_bifur_en : 1; + u32 os_hotreplace_en : 1; +#else + u32 os_hotreplace_en : 1; + u32 flow_bifur_en : 1; + u32 bond_bifur_en : 1; + u32 local_switch_lro_en : 1; + u32 cfg_rq_num : 9; + u32 er_fwd_id : 3; + u32 er_fwd_type : 4; /* er forward type: 2-port; 3-fic; 4-trunk; other-unsupport */ + u32 er_id : 4; /* edge relay id: [0~15]. support up to 16 er. */ + u32 def_pri : 3; /* default priority */ + u32 nic_rx_mode : 5; + +#endif + } bs; + + u32 value; + } dw2; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 cfg_sq_num : 9; + u32 rss_temp_id : 12; + u32 rss_instance_id : 6; + u32 rss_node_id : 5; + +#else + u32 rss_node_id : 5; + u32 rss_instance_id : 6; + u32 rss_temp_id : 12; + u32 cfg_sq_num : 9; + +#endif + } bs; + + u32 value; + } dw3; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rx_wqe_buffer_size : 16; /* one wqe buffer size, default is 2K bytes */ + u32 smac_h16 : 16; +#else + u32 smac_h16 : 16; + u32 rx_wqe_buffer_size : 16; /* one wqe buffer size, default is 2K bytes */ +#endif + } bs; + + u32 value; + } dw4; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 smac_m16; + u16 smac_l16; +#else + u16 smac_l16; + u16 smac_m16; +#endif + } bs; + u32 smac_l32; + } dw5; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vlan_pri_map_group : 24; /* every group takes 3bits,8 group totally 24bits, group 0 mapped to the lowest + 3bits */ + u32 cfg_rq_depth : 5; + u32 round_bit : 1; + u32 fdir_tcam_enable : 1; + u32 rsvd : 1; + +#else + u32 rsvd : 1; + u32 fdir_tcam_enable : 1; + u32 round_bit : 1; + u32 cfg_rq_depth : 5; + u32 vlan_pri_map_group : 24; /* every group takes 3bits,8 group totally 24bits, group 0 mapped to the lowest + 3bits */ + +#endif + } bs; + + u32 value; + } dw6; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 bond_en : 1; + u32 bond_id : 3; + u32 bond_mode : 3; + u32 bond_hash_policy : 3; + u32 bond_active_num : 3; /* use in flow bifurcation bond send */ + u32 bond_active_bitmap : 4; /* use in flow bifurcation bond send */ + u32 base_qid : 13; + u32 rq_pri_num : 2; +#else + u32 rq_pri_num : 2; + u32 base_qid : 13; + u32 bond_active_bitmap : 4; /* use in flow bifurcation bond send */ + u32 bond_active_num : 3; /* use in flow bifurcation bond send */ + u32 bond_hash_policy : 3; + u32 bond_mode : 3; + u32 bond_id : 3; + u32 bond_en : 1; +#endif + } bs; + u32 value; + } dw7; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ovs_vm_tx_bw_en : 1; + u32 ovs_vm_tx_pps_en : 1; + u32 ovs_vm_rx_bw_en : 1; + u32 ovs_vm_rx_pps_en : 1; + u32 ovs_mc_bc_limit_en : 1; /* mc bc limit enable: 0-disable; 1-enable */ + u32 ovs_bum_limit_mode : 1; /* flow type controled by bum limit: 0-mc and bc; 1-bc */ + u32 ovs_ethtype_filter_en : 1; /* ethtype filter enable: 0-disable; 1-enable */ + u32 ovs_mac_filter_mode : 2; /* mac filter mode: 0-disable; 1-single enable;2-multi enbale;3-rsvd */ + u32 ovs_upcall_limit_port_en : 1; /* per port upcall rate limit */ + u32 ovs_etp_en : 2; + u32 ovs_capture_bond_en : 1; + u32 ovs_capture_tap_en : 1; + u32 ovs_trunk_port_en : 1; + u32 ovs_vsmall_en : 1; + u32 ovs_xtrace_en : 1; + u32 icq_base : 12; + u32 ovs_fm_period_en : 1; + u32 ovs_vport_en : 1; + u32 rsvd : 1; +#else + u32 rsvd : 1; + u32 ovs_vport_en : 1; + u32 ovs_fm_period_en : 1; + u32 icq_base : 12; + u32 ovs_xtrace_en : 1; + u32 ovs_vsmall_en : 1; + u32 ovs_trunk_port_en : 1; + u32 ovs_capture_tap_en : 1; + u32 ovs_capture_bond_en : 1; + u32 ovs_etp_en : 2; + u32 ovs_upcall_limit_port_en : 1; /* per port upcall rate limit */ + u32 ovs_mac_filter_mode : 2; /* mac filter mode: 0-disable; 1-single enable;2-multi enbale;3-rsvd */ + u32 ovs_ethtype_filter_en : 1; /* ethtype filter enable: 0-disable; 1-enable */ + u32 ovs_bum_limit_mode : 1; /* flow type controled by bum limit: 0-mc and bc; 1-bc */ + u32 ovs_mc_bc_limit_en : 1; /* mc bc limit enable: 0-disable; 1-enable */ + u32 ovs_vm_rx_pps_en : 1; + u32 ovs_vm_rx_bw_en : 1; + u32 ovs_vm_tx_pps_en : 1; + u32 ovs_vm_tx_bw_en : 1; +#endif + } ovs_bs; + + u32 value; + } dw8; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 upcall_q_num : 5; + u32 ovs_etp_index : 6; + u32 ovs_xtrace_id : 6; + u32 ovs_set_mac_flag : 1; + u32 func_rss_type_en : 1; /* ovs_bs&bs consistent */ + u32 rss_type : 8; /* ovs_bs&bs consistent */ + u32 dirty_set_en : 1; /* ovs_bs&vbs_bs&bs consistent */ + u32 dirty_set_pf_id : 4; /* ovs_bs&vbs_bs&bs consistent */ +#else + u32 dirty_set_pf_id : 4; + u32 dirty_set_en : 1; + u32 rss_type : 8; + u32 func_rss_type_en : 1; + u32 ovs_set_mac_flag : 1; + u32 ovs_xtrace_id : 6; + u32 ovs_etp_index : 6; + u32 upcall_q_num : 5; +#endif + } ovs_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 flr_seq : 3; + u32 stop_flag : 2; + u32 rsvd1 : 2; + u32 func_state : 1; /* used for sdi vsock pf */ + u32 rsvd0 : 19; + u32 dirty_set_en : 1; /* ovs_bs&vbs_bs&bs consistent */ + u32 dirty_set_pf_id : 4; /* ovs_bs&vbs_bs&bs consistent */ +#else + u32 dirty_set_pf_id : 4; + u32 dirty_set_en : 1; + u32 rsvd0 : 19; + u32 func_state : 1; /* used for sdi vsock pf */ + u32 rsvd1 : 2; + u32 stop_flag : 2; + u32 flr_seq : 3; +#endif + } vbs_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd0 : 18; + u32 func_rss_type_en : 1; + u32 rss_type : 8; + u32 dirty_set_en : 1; /* ovs_bs&vbs_bs&bs consistent */ + u32 dirty_set_pf_id : 4; /* ovs_bs&vbs_bs&bs consistent */ +#else + u32 dirty_set_pf_id : 4; + u32 dirty_set_en : 1; + u32 rss_type : 8; + u32 func_rss_type_en : 1; + u32 rsvd0 : 18; +#endif + } bs; + + u32 value; + } dw9; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 4; + u32 swpt_virtio_hdr : 4; + u32 vni : 24; +#else + u32 vni : 24; + u32 swpt_virtio_hdr : 4; + u32 rsvd : 4; +#endif + } ovs_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 5; + u32 vmio_core_num : 5; + u32 base_vmio_rq_id : 8; + u32 boot_valid : 1; + u32 boot_func_id : 5; + u32 boot_vmio_rq_id : 8; +#else + u32 boot_vmio_rq_id : 8; + u32 boot_func_id : 5; + u32 boot_valid : 1; + u32 base_vmio_rq_id : 8; + u32 vmio_core_num : 5; + u32 rsvd : 5; +#endif + } vbs_bs; + + u32 value; + } dw10; + + union { + /* ovs and roce cannot coexist */ + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ovs_mac_group_id : 7; /* ovs bum */ + u32 ovs_ethtype_group_id : 6; /* ovs bum */ + u32 vm_id : 11; + u32 mirror_qos_vm_pps_en : 1; + u32 mirror_qos_vm_bw_en : 1; + u32 rsvd1 : 6; +#else + u32 rsvd1 : 6; + u32 mirror_qos_vm_bw_en : 1; + u32 mirror_qos_vm_pps_en : 1; + u32 vm_id : 11; + u32 ovs_ethtype_group_id : 6; /* ovs bum */ + u32 ovs_mac_group_id : 7; /* ovs bum */ +#endif + } ovs_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ppa_en : 1; /* 0 : ppa disable, 1: ppa enable */ + u32 rsvd0 : 2; + u32 rsvd : 29; +#else + u32 rsvd : 29; + u32 rsvd0 : 2; + u32 ppa_en : 1; /* 0 : ppa disable, 1: ppa enable */ +#endif + } ppa_bs; + + u32 value; + } dw11; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 any_layout : 1; + u32 mrg_rxbuf : 1; + u32 rx_csum : 1; + u32 f_event : 1; + u32 f_packed : 1; + u32 f_version1 : 1; + u32 rsvd : 6; + u32 mig_entry_id : 5; /* migrate address table entry index */ + u32 glb_vqn_base : 14; + u32 host_cpu_arch : 1; +#else + u32 host_cpu_arch : 1; + u32 glb_vqn_base : 14; + u32 mig_entry_id : 5; /* migrate address table entry index */ + u32 rsvd : 6; + u32 f_version1 : 1; + u32 f_packed : 1; + u32 f_event : 1; + u32 rx_csum : 1; + u32 mrg_rxbuf : 1; + u32 any_layout : 1; +#endif + } virtio_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 roce_bond_en : 1; + u32 cpu_endian : 1; /* * 0-big endian 1-little endian */ + u32 roce_acx_en : 1; + u32 ucapture_en : 1; /* ucode capture enable: 0-disable; 1-enable */ + u32 ip_type : 1; + u32 bw_ctrl_en : 1; + u32 rsvd : 6; + u32 drcc_start_qpn : 20; +#else + u32 drcc_start_qpn : 20; + u32 rsvd : 6; + u32 bw_ctrl_en : 1; + u32 ip_type : 1; + u32 ucapture_en : 1; /* ucode capture enable: 0-disable; 1-enable */ + u32 roce_acx_en : 1; + u32 cpu_endian : 1; /* * 0-big endian 1-little endian */ + u32 roce_bond_en : 1; +#endif + } roce_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 max_lro_len : 8; + u32 toe_lro_en : 1; + u32 toe_bond_en : 1; + u32 rsvd : 22; +#else + u32 rsvd : 22; + u32 toe_bond_en : 1; + u32 toe_lro_en : 1; + u32 max_lro_len : 8; +#endif + } toe_bs; + + u32 value; + } dw12; /* RoCE/OVS/TOE cannot coexist */ + + union { + u32 virtio_driver_feature_h; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 12; + u32 max_drct : 20; +#else + u32 max_drct : 20; + u32 rsvd : 12; +#endif + } roce_bs; + + u32 value; + } dw13; + + union { + u32 virtio_driver_feature_l; + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rb_alive_p0_fwd_id : 3; + u32 rb_alive_p1_fwd_id : 3; + u32 rb_alive_p2_fwd_id : 3; + u32 rb_alive_p3_fwd_id : 3; + u32 rb_alive_p4_fwd_id : 3; + u32 rb_alive_p5_fwd_id : 3; + u32 rb_alive_p6_fwd_id : 3; + u32 rb_alive_p7_fwd_id : 3; + u32 bond_er_fwd_id : 4; + u32 rb_alive_slave_cnt : 4; +#else + u32 rb_alive_slave_cnt : 4; + u32 bond_er_fwd_id : 4; + u32 rb_alive_p7_fwd_id : 3; + u32 rb_alive_p6_fwd_id : 3; + u32 rb_alive_p5_fwd_id : 3; + u32 rb_alive_p4_fwd_id : 3; + u32 rb_alive_p3_fwd_id : 3; + u32 rb_alive_p2_fwd_id : 3; + u32 rb_alive_p1_fwd_id : 3; + u32 rb_alive_p0_fwd_id : 3; +#endif + } roce_bs; + + u32 value; + } dw14; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vmsec_entry_vld : 1; /* aka, vmsec_en */ + u32 vmsec_entry_idx : 5; + u32 rsvd : 18; + u32 tag : 2; + u32 fake_vld : 1; + u32 rsvd1 : 5; +#else + u32 rsvd1 : 5; + u32 fake_vld : 1; + u32 tag : 2; + u32 rsvd : 18; + u32 vmsec_entry_idx : 5; + u32 vmsec_entry_vld : 1; /* aka, vmsec_en */ +#endif + } roce_bs; + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 master_ctrl : 2; + u32 alive_ctrl_bmp : 4; + u32 vf_rb_bmp : 16; + u32 act_ctrl_bmp : 4; + u32 fake_vld : 1; + u32 rsvd : 1; + u32 pf_id : 4; +#else + u32 pf_id : 4; + u32 rsvd : 1; + u32 fake_vld : 1; + u32 act_ctrl_bmp : 4; + u32 vf_rb_bmp : 16; + u32 alive_ctrl_bmp : 4; + u32 master_ctrl : 2; +#endif + } nofaa; + u32 value; + } dw15; +} sml_funcfg_tbl_s; + +typedef struct sml_lacpdu_update_frame { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd0 : 16; + u32 data_len : 8; + u32 rsvd1 : 4; + u32 port_id : 2; + u32 vld : 1; + u32 busy : 1; +#else + u32 busy : 1; + u32 vld : 1; + u32 port_id : 2; + u32 rsvd1 : 4; + u32 data_len : 8; + u32 rsvd0 : 16; +#endif + } bs; + u32 value; + } dw0; + + u32 crc_value; + u8 data[LACP_MAX_SIZE]; + u32 rsvd[2]; +} sml_lacpdu_update_frame_s; + +typedef struct tag_mqp_funcfg_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; /* function valid: 0-invalid; 1-valid */ + u32 rsvd : 24; + u32 drop_en : 1; + u32 rsvd2 : 6; +#else + u32 rsvd2 : 6; + u32 drop_en : 1; + u32 rsvd : 24; + u32 valid : 1; +#endif + } bs; + + u32 value; + } dw0; + + u32 rsvd0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 8; + u32 er_id : 4; /* edge relay id: [0~15]. support up to 16 er. */ + u32 er_fwd_type : 4; /* er forward type: 2-port; 3-fic; 4-trunk; other-unsupport */ + u32 er_fwd_id : 16; /* er forward id: fwd_type=2: forward ethernet port id + fwd_type=3: forward fic id(tb+tp) + fwd_type=4: forward trunk id */ +#else + u32 er_fwd_id : 16; + u32 er_fwd_type : 4; /* er forward type: 2-port; 3-fic; 4-trunk; other-unsupport */ + u32 er_id : 4; + u32 rsvd : 8; +#endif + } bs; + + u32 value; + } dw2; + + u8 base_funcid[4]; + u32 func_num_per_host; + + u32 rsvd1; + + u32 fake_data_addr[8]; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 stub_vld : 1; + u32 stub_sw_dly : 1; + u32 hostid_vld : 1; + u32 host_id : 2; + u32 stub_sub_info : 19; + u32 stub_code : 8; +#else + u32 stub_code : 8; + u32 stub_sub_info : 19; + u32 host_id : 2; + u32 hostid_vld : 1; + u32 stub_sw_dly : 1; + u32 stub_vld : 1; +#endif + } bs; + u32 value; + } flr_stub; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 master_ctrl : 2; + u32 alive_ctrl_bmp : 4; + u32 vf_rb_bmp : 16; + u32 act_ctrl_bmp : 4; + u32 fake_vld : 1; + u32 fast_recycled_mode : 1; + u32 pf_id : 4; +#else + u32 pf_id : 4; + u32 fast_recycled_mode : 1; + u32 fake_vld : 1; + u32 act_ctrl_bmp : 4; + u32 vf_rb_bmp : 16; + u32 alive_ctrl_bmp : 4; + u32 master_ctrl : 2; +#endif + } nofaa; + u32 value; + } dw15; +} sml_mqp_funcfg_tbl_s; + +/** + * Struct name: sml_portcfg_tbl_s + * @brief Port Configuration Table + * Description: Port configuration attribute table + */ +typedef struct tag_sml_portcfg_tbl { + /* valid and enable flag */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; /* valid:0-invalid; 1-valid */ + u32 learn_en : 1; /* mac learn enable: 0-disable; 1-enable */ + u32 net_upcall_limit_flag : 1; + u32 resvd1 : 1; + u32 qcn_en : 1; /* qcn enable: 0-disable; 1-enable */ + u32 bond_port_vld : 1; /* if backup port,bond_port_vld=0; others, bond_port_vld=1 */ + u32 nic_car_en : 1; + u32 ovs_bond_en : 1; /* ovs bond enable: 0-disable; 1-enable */ + u32 roce_bond_en : 1; /* bond enable for roce */ + u32 share_plane_en : 1; + u32 bc_to_all_function : 1; + u32 ovs_capture_en : 1; + u32 flow_bifur_en : 1; + u32 nic_tx_promisc_skip : 1; /* 1:tx ignore promisc_bitmap,skip replicate to PF */ + u32 resvd : 18; +#else + u32 resvd : 18; + u32 nic_tx_promisc_skip : 1; + u32 flow_bifur_en : 1; + u32 ovs_capture_en : 1; + u32 bc_to_all_function : 1; + u32 share_plane_en : 1; + u32 roce_bond_en : 1; /* bond enable for roce */ + u32 ovs_bond_en : 1; /* ovs bond enable: 0-disable; 1-enable */ + u32 nic_car_en : 1; + u32 bond_port_vld : 1; /* if backup port,bond_port_vld=0; others, bond_port_vld=1 */ + u32 qcn_en : 1; /* qcn enable: 0-disable; 1-enable */ + u32 resvd1 : 1; + u32 net_upcall_limit_flag : 1; + u32 learn_en : 1; /* mac learn enable: 0-disable; 1-enable */ + u32 valid : 1; /* valid:0-invalid; 1-valid */ + +#endif + } bs; + u32 value; + } dw0; + + /* common config */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 def_pri : 3; /* default priority */ + u32 er_mode : 2; /* edge relay mode: 0-VEB; 1-VEPA(unsupport); 2-Multi-Channel(unsupport) */ + u32 er_id : 4; /* edge relay identifier: [0~15]. support up to 16 er. */ + u32 resvd : 23; +#else + u32 resvd : 23; + u32 er_id : 4; /* edge relay identifier: [0~15]. support up to 16 er. */ + u32 er_mode : 2; /* edge relay mode: 0-VEB; 1-VEPA(unsupport); 2-Multi-Channel(unsupport) */ + u32 def_pri : 3; /* default priority */ + +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rvsd0 : 1; + u32 ovs_etp_en : 1; + u32 mtu : 14; + u32 rvsd1 : 11; + u32 ovs_upcall_q_num : 5; +#else + u32 ovs_upcall_q_num : 5; + u32 rvsd1 : 11; + u32 mtu : 14; + u32 ovs_etp_en : 1; + u32 rvsd0 : 1; +#endif + } bs; + u32 value; + } dw2; + + /* bond config */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 toe_bond_pf_id_array : 20; + u32 toe_bond_pf_num : 3; + u32 toe_bond_en : 1; + u32 bond_id : 8; /* bond identifier: [1~4] */ +#else + u32 bond_id : 8; /* bond identifier: [1~4] */ + u32 toe_bond_en : 1; + u32 toe_bond_pf_num : 3; + u32 toe_bond_pf_id_array : 20; +#endif + } bs; + + u32 value; + } dw3; + + union { + u32 value; + } dw4; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 migrate_src_vni : 24; + u32 resvd : 8; +#else + u32 resvd : 8; + u32 migrate_src_vni : 24; + +#endif + } bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid_0 : 1; + u32 valid_1 : 1; + u32 valid_2 : 1; + u32 valid_3 : 1; + + u32 pf_id_0 : 5; + u32 pf_id_1 : 5; + u32 pf_id_2 : 5; + u32 pf_id_3 : 5; + + u32 present_0 : 1; + u32 present_1 : 1; + u32 present_2 : 1; + u32 present_3 : 1; + + u32 resvd : 4; + +#else + u32 resvd : 4; + + u32 present_3 : 1; + u32 present_2 : 1; + u32 present_1 : 1; + u32 present_0 : 1; + + u32 pf_id_3 : 5; + u32 pf_id_2 : 5; + u32 pf_id_1 : 5; + u32 pf_id_0 : 5; + + u32 valid_3 : 1; + u32 valid_2 : 1; + u32 valid_1 : 1; + u32 valid_0 : 1; +#endif + } single_ip_bs; + + u32 value; + } dw5; + + union { + u32 value; + } dw6; + + u32 pf_promiscuous_bitmap; +} sml_portcfg_tbl_s; + +typedef struct tag_sml_share_plane_tbl { + u8 share_plane_type[OVS_SP_VLAN_NUM_PER_ITEM]; +} sml_share_plane_tbl_s; + +/** + * Struct name: sml_taggedlist_tbl_s + * @brief Tagged List Table + * Description: VLAN Filtering the tagged list Table of the Trunk/Hybrid Type + */ +typedef struct tag_sml_taggedlist_tbl { + u32 bitmap[TBL_ID_TAGGEDLIST_BITMAP32_NUM]; +} sml_taggedlist_tbl_s; + +/** + * Struct name: sml_untaggedlist_tbl_s + * @brief Untagged List Table + * Description: VLAN Filtering the Untagged list Table of the Hybrid Type + */ +typedef struct tag_sml_untaggedlist_tbl { + u32 bitmap[TBL_ID_UNTAGGEDLIST_BITMAP32_NUM]; +} sml_untaggedlist_tbl_s; + +/** + * Struct name: sml_trunkfwd_tbl_s + * @brief Trunk Forward Table + * Description: port aggregation Eth-Trunk forwarding table + */ +typedef struct tag_sml_trunkfwd_tbl { + u16 fwd_id[TBL_ID_TRUNKFWD_ENTRY_ELEM_NUM]; /* dw0-dw15 */ +} sml_trunkfwd_tbl_s; + +/** + * Struct name: sml_mac_tbl_head_u + * @brief Mac table request/response head + * Hash API header in the Description: MAC table + */ +typedef union tag_sml_mac_tbl_head { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 src : 5; + u32 instance_id : 6; + u32 opid : 5; + u32 A : 1; + u32 S : 1; + u32 rsvd : 14; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 rsvd : 14; + u32 S : 1; + u32 A : 1; + u32 opid : 5; + u32 instance_id : 6; + u32 src : 5; +#endif + } req_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 code : 2; + u32 subcode : 2; + u32 rsvd : 13; + u32 node_index : 15; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 node_index : 15; + u32 rsvd : 13; + u32 subcode : 2; + u32 code : 2; +#endif + } rsp_bs; + + u32 value; +} sml_mac_tbl_head_u; + +/** + * Struct name: sml_mac_tbl_8_4_key_u + * @brief Mac Table Key + * Key of the Description: MAC table. + */ +typedef union tag_sml_mac_tbl_8_4_key { + struct { + u32 val0; + u32 val1; + } value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 er_id : 4; + u32 vlan_id : 12; + u32 mac_h16 : 16; + + u32 mac_m16 : 16; + u32 mac_l16 : 16; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 mac_h16 : 16; + u32 vlan_id : 12; + u32 er_id : 4; + + u32 mac_l16 : 16; + u32 mac_m16 : 16; +#endif + } bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 er_id : 4; + u32 vlan_id : 12; + u32 mac0 : 8; + u32 mac1 : 8; + + u32 mac2 : 8; + u32 mac3 : 8; + u32 mac4 : 8; + u32 mac5 : 8; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 mac1 : 8; + u32 mac0 : 8; + u32 vlan_id : 12; + u32 er_id : 4; + + u32 mac5 : 8; + u32 mac4 : 8; + u32 mac3 : 8; + u32 mac2 : 8; +#endif + } mac_bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 er_id : 4; + u32 func_id : 12; + u32 local_qid : 16; + u32 rsvd; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 local_qid : 16; + u32 func_id : 12; + u32 er_id : 4; + u32 rsvd; +#endif + } flex_bs; +} sml_mac_tbl_8_4_key_u; + +/** + * Struct name: sml_mac_tbl_8_4_item_u + * @brief Mac Table Item + * Description: xxxxxxxxxxxxxxx + */ +typedef union tag_sml_mac_tbl_8_4_item { + u32 value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 7; + u32 single_ip_en : 1; + u32 single_ip_srv_mode : 1; + u32 host_id : 3; + u32 fwd_type : 4; + u32 fwd_id : 16; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 fwd_id : 16; + u32 fwd_type : 4; + u32 host_id : 3; + u32 single_ip_srv_mode : 1; + u32 single_ip_en : 1; + u32 rsvd : 7; +#endif + } bs; +} sml_mac_tbl_8_4_item_u; + +/** + * Struct name: sml_mac_tbl_key_item_s + * @brief Mac Table( 8 + 4 ) + * Description: MAC table Key + Item + */ +typedef struct tag_sml_mac_tbl_8_4 { + sml_mac_tbl_head_u head; + sml_mac_tbl_8_4_key_u key; + sml_mac_tbl_8_4_item_u item; +} sml_mac_tbl_8_4_s; + +typedef union tag_sml_fdir_io_tbl_8_4_key { + struct { + u32 val0; + u32 val1; + }value; + + struct { + u32 sip; + u32 dip; + }ip_bs; +} sml_fdir_io_tbl_8_4_key_u; + +typedef union tag_sml_fdir_io_tbl_8_4_item { + u32 value; + + struct { + #if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 15; + u32 func_id : 9; + u32 fwd_qid : 8; + #elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 fwd_qid : 8; + u32 func_id : 9; + u32 rsvd : 15; + #endif + } bs; +} sml_fdir_io_tbl_8_4_item_u; + +/** + * Struct name: sml_vtep_tbl_8_4_key_s + * @brief Vtep Table Key + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vtep_tbl_8_4_key { + u32 vtep_remote_ip; + u32 rsvd; +} sml_vtep_tbl_8_4_key_s; + +/** + * Struct name: dmac_smac_u + * @brief Dmac & Smac for VxLAN encapsulation + * Description: xxxxxxxxxxxxxxx + */ +typedef union tag_dmac_smac { + u16 mac_addr[6]; + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 d_mac0 : 8; + u16 d_mac1 : 8; + u16 d_mac2 : 8; + u16 d_mac3 : 8; + + u16 d_mac4 : 8; + u16 d_mac5 : 8; + u16 s_mac0 : 8; + u16 s_mac1 : 8; + + u16 s_mac2 : 8; + u16 s_mac3 : 8; + u16 s_mac4 : 8; + u16 s_mac5 : 8; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u16 d_mac1 : 8; + u16 d_mac0 : 8; + u16 d_mac3 : 8; + u16 d_mac2 : 8; + + u16 d_mac5 : 8; + u16 d_mac4 : 8; + u16 s_mac1 : 8; + u16 s_mac0 : 8; + + u16 s_mac3 : 8; + u16 s_mac2 : 8; + u16 s_mac5 : 8; + u16 s_mac4 : 8; +#endif + } bs; +} dmac_smac_u; + +/** + * Struct name: sml_vtep_tbl_8_4_item_u + * @brief Vtep Table Item + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vtep_tbl_8_4_item { + u32 value; +} sml_vtep_tbl_8_4_item_s; + +/** + * Struct name: sml_vtep_tbl_8_4_s + * @brief Vtep Table( 8 + 20) + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vtep_tbl_8_4 { + sml_mac_tbl_head_u head; /* first 4 bytes , the same as mac tbl */ + sml_vtep_tbl_8_4_key_s key; + sml_vtep_tbl_8_4_item_s item; +} sml_vtep_tbl_8_4_s; + +/** + * Struct name: tag_sml_vxlan_udp_portcfg_4_8_key + * @brief Vtep Table Key + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vxlan_udp_portcfg_4_8_key { + u32 udp_dest_port; + u32 rsvd; +} sml_vxlan_udp_portcfg_4_8_key_s; + +/** + * Struct name: sml_vtep_tbl_8_20_item_u + * @brief Vtep Table Item + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vxlan_udp_portcfg_4_8_item { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 odp_port : 12; + u32 dp_id : 2; + u32 resvd : 20; +#else + u32 resvd : 20; + u32 dp_id : 2; + u32 odp_port : 12; +#endif + } bs; + + u32 value; + } dw0; +} sml_vxlan_udp_portcfg_4_8_item_s; + +/** + * Struct name: sml_vxlan_udp_portcfg_4_8_s + * @brief Vxlan Dest Udp Port Table( 8 + 20) + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vxlan_udp_portcfg_4_8 { + sml_mac_tbl_head_u head; /* first 4 bytes , the same as mac tbl */ + sml_vxlan_udp_portcfg_4_8_key_s key; + sml_vxlan_udp_portcfg_4_8_item_s item; +} sml_vxlan_udp_portcfg_4_8_s; + +/** + * Struct name: sml_vtep_er_info_s + * @brief Vtep Er Info Table + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_vtep_er_info { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 lli_mode : 1; + u32 er_fwd_trunk_type : 1; /* When the outbound interface of ER is bound to an Eth-Trunk, the type of the + interface is (FIC/Port). */ + u32 er_fwd_trunk_mode : 4; /* When ER is bound to an Eth-Trunk interface, the interface aggregation mode is + (Standby/LoadBalance/LACP). */ + u32 er_mode : 2; /* ER mode (VEB/VEPA) */ + u32 er_id : 4; /* As the index of the LT, er_id is also used as the entry content to facilitate service + use. */ + u32 er_fwd_type : 4; /* Type of the egress port bound to ER (Port/FIC/Eth-Trunk) */ + u32 er_fwd_id : 16; /* Indicates the ID(PortID/FICID/TrunkID) of the egress port bound to ER. */ +#else + u32 er_fwd_id : 16; + u32 er_fwd_type : 4; + u32 er_id : 4; + u32 er_mode : 2; + u32 er_fwd_trunk_mode : 4; + u32 er_fwd_trunk_type : 1; + u32 lli_mode : 1; +#endif + } bs; + + u32 value; + } dw0; +} sml_vtep_er_info_s; + +/** + * Struct name: sml_logic_port_cfg_tbl_s + * @brief Logic Port Cfg Table + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sm_logic_port_cfg { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 odp_port : 12; /* * Input switch port (or DP_MAX_PORTS). */ + u32 dp_id : 2; /* datapath id */ + u32 er_id : 4; + u32 learn_en : 1; /* logic port MAC Learning enable or disable */ + u32 resvd : 13; +#else + u32 resvd : 13; + u32 learn_en : 1; /* logic port MAC Learning enable or disable */ + u32 er_id : 4; + u32 dp_id : 2; /* datapath id */ + u32 odp_port : 12; /* * Input switch port (or DP_MAX_PORTS). */ +#endif + } bs; + + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd4 : 1; + u32 er_fwd_trunk_type : 1; + u32 er_fwd_trunk_mode : 4; + u32 er_mode : 2; + u32 er_id : 4; + u32 er_fwd_type : 4; + u32 er_fwd_id : 16; +#else + u32 er_fwd_id : 16; + u32 er_fwd_type : 4; + u32 er_id : 4; + u32 er_mode : 2; + u32 er_fwd_trunk_mode : 4; + u32 er_fwd_trunk_type : 1; + u32 rsvd4 : 1; +#endif + } bs; + + u32 value; + } dw1; +} sml_logic_port_cfg_tbl_s; + +/* vport stats counter */ +typedef struct tag_vport_stats_ctr { + u16 rx_packets; /* total packets received */ + u16 tx_packets; /* total packets transmitted */ + u16 rx_bytes; /* total bytes received */ + u16 tx_bytes; /* total bytes transmitted */ + u16 rx_errors; /* bad packets received */ + u16 tx_errors; /* packet transmit problems */ + u16 rx_dropped; /* no space in linux buffers */ + u16 tx_dropped; /* no space available in linux */ +} vport_stats_ctr_s; + +/** + * Struct name: vport_s + * @brief Datapath Cfg Table + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_vport { +#if (BYTE_ORDER == BIG_ENDIAN) + /* dw0 */ + u32 valid : 1; + u32 learn_en : 1; + u32 type : 4; + u32 dp_id : 2; + u32 mapping_type : 4; /* The type of Vport mapping port, 0:VF, 1:Logic Port */ + u32 mapping_port : 12; /* odp_port mapping on VF or ER Logic Port */ + u32 rsvd : 8; + + /* dw1 */ + u32 srctagl : 12; /* the function used by parent context */ + u32 xid : 20; /* parent context XID used to upcall missed packet to ovs-vswitchd */ + + /* dw2 */ + u32 odp_port : 12; /* on datapath port id */ + u32 cid : 20; /* parent context CID used to upcall missed packet to ovs-vswitchd */ +#else + /* dw0 */ + u32 rsvd : 8; + u32 mapping_port : 12; /* odp_port mapping on VF or ER Logic Port */ + u32 mapping_type : 4; /* The type of Vport mapping port, 0:VF, 1:Logic Port */ + u32 dp_id : 2; + u32 type : 4; + u32 learn_en : 1; + u32 valid : 1; + + /* dw1 */ + u32 xid : 20; /* parent context XID used to upcall missed packet to ovs-vswitchd */ + u32 srctagl : 12; /* the function used by parent context */ + + /* dw2 */ + u32 cid : 20; /* parent context CID used to upcall missed packet to ovs-vswitchd */ + u32 odp_port : 12; /* on datapath port id */ +#endif + + /* Dw3: Er information. This parameter is valid only for mapping_type=1(logic port). */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 lli_mode : 1; + u32 er_fwd_trunk_type : 1; /* When the outbound interface of ER is bound to an Eth-Trunk interface, the + interface type is (FIC/Port). */ + u32 er_fwd_trunk_mode : 4; /* When ER is bound to an Eth-Trunk interface, the interface aggregation mode is + (Standby/LoadBalance/LACP). */ + u32 er_mode : 2; /* ER mode (VEB/VEPA) */ + u32 er_id : 4; /* ERID */ + u32 er_fwd_type : 4; /* Type of the egress port bound to ER (Port/FIC/Eth-Trunk) */ + u32 er_fwd_id : 16; /* ID(PortID/FICID/TrunkID) of the egress port bound to ER */ +#else + u32 er_fwd_id : 16; + u32 er_fwd_type : 4; + u32 er_id : 4; + u32 er_mode : 2; + u32 er_fwd_trunk_mode : 4; + u32 er_fwd_trunk_type : 1; /* When the outbound interface of ER is Eth-Trunk, the type of the interface is + (FIC/Port). */ + u32 lli_mode : 1; +#endif + } bs; + u32 value; + } dw3; + + /* dw4~dw7 */ + vport_stats_ctr_s stats; /* vport stats counters */ +} vport_s; + +/** + * Struct name: sml_elb_tbl_elem_u + * @brief ELB Table Elem + * Description: ELB Leaf Subtable Member + */ +typedef union tag_sml_elb_tbl_elem { + struct { + u32 fwd_val; + u32 next_val; + } value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd0 : 10; + u32 qinq_cfg : 2; + u32 fwd_type : 4; + u32 fwd_id : 16; + + u32 rsvd1 : 17; + u32 elb_index_next : 15; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 fwd_id : 16; + u32 fwd_type : 4; + u32 qinq_cfg : 2; + u32 rsvd0 : 10; + + u32 elb_index_next : 15; + u32 rsvd1 : 17; +#endif + } bs; +} sml_elb_tbl_elem_u; + +/** + * Struct name: sml_elb_tbl_s + * @brief ELB Table + * Entry of the Description: ELB leaf table + */ +typedef struct tag_sml_elb_tbl { + sml_elb_tbl_elem_u elem[TBL_ID_ELB_ENTRY_ELEM_NUM]; +} sml_elb_tbl_s; + +/** + * Struct name: sml_vlan_tbl_elem_u + * @brief VLAN Table Elem + * Description: VLAN BC table member + */ +typedef union tag_sml_vlan_tbl_elem { + u16 value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 learn_en : 1; + u16 elb_index : 15; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u16 elb_index : 15; + u16 learn_en : 1; +#endif + } bs; +} sml_vlan_tbl_elem_u; + +/** + * Struct name: sml_vlan_tbl_s + * @brief VLAN Table + * Description: VLAN BC Table Entry + */ +typedef struct tag_sml_vlan_tbl { + sml_vlan_tbl_elem_u elem[TBL_ID_VLAN_ENTRY_ELEM_NUM]; +} sml_vlan_tbl_s; + +/** + * Struct name: sml_multicast_tbl_array_u + * @brief Multicast Table Elem + * Description: multicast table member + */ +typedef union tag_sml_multicast_tbl_elem { + struct { + u32 next_val; + } value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd1 : 17; + u32 elb_index : 15; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 elb_index : 15; + u32 rsvd1 : 17; +#endif + } bs; +} sml_multicast_tbl_elem_u; + +/** + * Struct name: sml_multicast_tbl_s + * @brief Multicast Table + * Description: Entry of the multicast table + */ +typedef struct tag_sml_multicast_tbl { + sml_multicast_tbl_elem_u elem[TBL_ID_MULTICAST_ENTRY_ELEM_NUM]; +} sml_multicast_tbl_s; + +/** + * Struct name: sml_observe_port_s + * @brief Observe Port Table + * Description: Observe the definition of the port entry. + */ +typedef struct tag_sml_observe_port { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; + u32 rsvd0 : 11; + u32 dst_type : 4; + u32 dst_id : 16; +#else + u32 dst_id : 16; + u32 dst_type : 4; + u32 rsvd0 : 11; + u32 valid : 1; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd1 : 4; + u32 vlan_id : 12; + u32 rsvd2 : 2; + u32 cut_len : 14; +#else + u32 cut_len : 14; + u32 rsvd2 : 2; + u32 vlan_id : 12; + u32 rsvd1 : 4; +#endif + } bs; + u32 value; + } dw1; + + u32 rsvd_pad[2]; +} sml_observe_port_s; + +/* + * Struct name: sml_ipmac_tbl_16_12_key_s + * @brief ipmac filter table key + * Description: ipmac filter key define + */ +typedef struct tag_sml_ipmac_tbl_16_12_key { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 func_id : 16; + u32 mac_h16 : 16; +#else + u32 mac_h16 : 16; + u32 func_id : 16; +#endif + +#if (BYTE_ORDER == BIG_ENDIAN) + u32 mac_m16 : 16; + u32 mac_l16 : 16; +#else + u32 mac_l16 : 16; + u32 mac_m16 : 16; +#endif + + u32 ip; + u32 rsvd; +} sml_ipmac_tbl_16_12_key_s; + +/* + * Struct name: sml_ipmac_tbl_16_12_item_s + * @brief ipmac filter table item + * Description: ipmac filter item define + */ +typedef struct tag_sml_ipmac_tbl_16_12_item { + u32 rsvd[3]; +} sml_ipmac_tbl_16_12_item_s; + +/* + * Struct name: sml_ethtype_tbl_8_4_key_s + * @brief ethtype filter table key + * Description: ethtype filter key define + */ +typedef struct tag_sml_ethtype_tbl_8_4_key { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 group_id : 16; + u32 ethtype : 16; +#else + u32 ethtype : 16; + u32 group_id : 16; +#endif + + u32 rsvd; +} sml_ethtype_tbl_8_4_key_s; + +/* + * Struct name: sml_ethtype_tbl_8_4_item_s + * @brief ethtype filter table item + * Description: ethtype filter item define + */ +typedef struct tag_sml_ethtype_tbl_8_4_item { + u32 rsvd; +} sml_ethtype_tbl_8_4_item_s; + + +/* Indicates the direction of packets recorded by the ACL in the dfx. */ +typedef enum { + ACL_PKT_TX = 0, + ACL_PKT_RX = 1 +} sml_acl_pkt_dir_e; + +/* ACL policy table item */ +typedef struct tag_sml_acl_policy_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 drop : 1; + u32 car_en : 1; + u32 car_id : 12; + u32 counter_type : 2; + u32 counter_id : 16; +#else + u32 counter_id : 16; + u32 counter_type : 2; + u32 car_id : 12; + u32 car_en : 1; + u32 drop : 1; +#endif + } bs; + + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd1 : 7; + u32 mirrior_en : 1; + u32 observer_port : 10; + u32 change_dscp : 1; + u32 new_dscp : 6; + u32 change_pkt_pri : 1; + u32 new_pkt_pri : 3; + u32 redirect_en : 3; +#else + u32 redirect_en : 3; + u32 new_pkt_pri : 3; + u32 change_pkt_pri : 1; + u32 new_dscp : 6; + u32 change_dscp : 1; + u32 observer_port : 10; + u32 mirrior_en : 1; + u32 rsvd1 : 7; +#endif + } bs; + + u32 value; + } dw1; + + u32 redirect_data; + u32 rsvd2; +} sml_acl_policy_tbl_s; + +typedef struct tag_sml_acl_ipv4_key { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 padding : 16; /* Used for alignment. The match_key_type and later fields are used to search for the key + value. */ + u32 tid0 : 2; + u32 match_key_type : 3; /* Matching type. */ + u32 rsvd : 11; /* Reserved field */ +#else + u32 rsvd : 11; + u32 match_key_type : 3; + u32 tid0 : 2; + u32 padding : 16; +#endif + } bs; + u32 value; + } dw0; + + /* dw1&dw2 */ + u32 sipv4; + u32 dipv4; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 l4_sport : 16; + u32 l4_dport : 16; +#else + u32 l4_dport : 16; + u32 l4_sport : 16; +#endif + } bs; + u32 value; + } dw3; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 l4_protocol : 8; + u32 rsvd0 : 8; + u32 seg_id : 10; + u32 rsvd1 : 6; +#else + u32 rsvd1 : 6; + u32 seg_id : 10; + u32 rsvd0 : 8; + u32 l4_protocol : 8; +#endif + } bs; + u32 value; + } dw4; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 tid1 : 2; + u32 rsvd : 14; + u32 padding : 16; +#else + u32 padding : 16; + u32 rsvd : 14; + u32 tid1 : 2; +#endif + } bs; + u32 value; + } dw5; +} sml_acl_ipv4_key_s; + +typedef struct tag_sml_acl_ipv6_key { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 padding : 16; /* Used for alignment. The match_key_type and later fields are used to search for the key + value. */ + u32 tid0 : 2; + u32 match_key_type : 3; /* Matching type. */ + u32 rsvd : 11; /* Reserved field */ +#else + u32 rsvd : 11; + u32 match_key_type : 3; + u32 tid0 : 2; + u32 padding : 16; +#endif + } bs; + u32 value; + } dw0; + + /* dw1~dw4 */ + u32 sipv6[4]; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 tid1 : 2; + u32 rsvd1 : 14; + u32 tid2 : 2; + u32 rsvd2 : 14; +#else + u32 rsvd2 : 14; + u32 tid2 : 2; + u32 rsvd1 : 14; + u32 tid1 : 2; +#endif + } bs; + u32 value; + } dw5; + + /* dw6~dw9 */ + u32 dipv6[4]; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 tid3 : 2; + u32 rsvd3 : 14; + u32 tid4 : 2; + u32 rsvd4 : 14; +#else + u32 rsvd4 : 14; + u32 tid4 : 2; + u32 rsvd3 : 14; + u32 tid3 : 2; +#endif + } bs; + u32 value; + } dw10; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 l4_sport : 16; + u32 l4_dport : 16; +#else + u32 l4_dport : 16; + u32 l4_sport : 16; +#endif + } bs; + u32 value; + } dw11; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 l4_protocol : 8; + u32 rsvd0 : 8; + u32 seg_id : 10; + u32 rsvd1 : 6; +#else + u32 rsvd1 : 6; + u32 seg_id : 10; + u32 rsvd0 : 8; + u32 l4_protocol : 8; +#endif + } bs; + u32 value; + } dw12; + + u32 dw13; + u32 dw14; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 tid5 : 2; + u32 rsvd5 : 14; + u32 tid6 : 2; + u32 rsvd6 : 14; +#else + u32 rsvd6 : 14; + u32 tid6 : 2; + u32 rsvd5 : 14; + u32 tid5 : 2; +#endif + } bs; + u32 value; + } dw15; + + u32 dw16; + u32 dw17; + u32 dw18; + u32 dw19; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 tid7 : 2; + u32 rsvd7 : 30; +#else + u32 rsvd7 : 30; + u32 tid7 : 2; +#endif + } bs; + u32 value; + } dw20; +} sml_acl_ipv6_key_s; + +/** + * Struct name: sml_fdir_cfg_tbl_s + * @brief Function FDIR cfg Table + * Description: Function FDIR control cfg + */ +typedef struct sml_fdir_cfg_tbl { + u16 packet_fdir_cfg[FDIR_CFG_TABLE_PACKET_TYPE_NUM]; /* 16 packet_type */ +} sml_fdir_cfg_tbl_s; + +/** + * Struct name: sml_voq_map_table_s + * @brief voq_map_table + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_voq_map_table { + u16 voq_base[8]; +} sml_voq_map_table_s; + +/** + * Struct name: sml_rss_context_u + * @brief rss_context + * Description: xxxxxxxxxxxxxxx + */ +typedef union tag_sml_rss_context { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 udp_ipv4 : 1; + u32 udp_ipv6 : 1; + u32 ipv4 : 1; + u32 tcp_ipv4 : 1; + u32 ipv6 : 1; + u32 tcp_ipv6 : 1; + u32 ipv6_ext : 1; + u32 tcp_ipv6_ext : 1; + u32 valid : 1; + u32 rsvd1 : 13; + u32 def_qpn : 10; +#else + u32 def_qpn : 10; + u32 rsvd1 : 13; + u32 valid : 1; + u32 tcp_ipv6_ext : 1; + u32 ipv6_ext : 1; + u32 tcp_ipv6 : 1; + u32 ipv6 : 1; + u32 tcp_ipv4 : 1; + u32 ipv4 : 1; + u32 udp_ipv6 : 1; + u32 udp_ipv4 : 1; +#endif + } bs; + + u32 value; +} sml_rss_context_u; + +typedef struct tag_sml_rss_context_tbl { + sml_rss_context_u element[TBL_ID_RSS_CONTEXT_NUM]; +} sml_rss_context_tbl_s; + +/** + * Struct name: sml_rss_hash_u + * @brief rss_hash + * Description: xxxxxxxxxxxxxxx + */ +typedef union tag_sml_rss_hash { + u8 rq_index[256]; +} sml_rss_hash_u; + +typedef struct tag_sml_rss_hash_tbl { + sml_rss_hash_u element[TBL_ID_RSS_HASH_NUM]; +} sml_rss_hash_tbl_s; + +/** + * Struct name: sml_lli_5tuple_key_s + * @brief lli_5tuple_key + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_lli_5tuple_key { + union { + struct { +/* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 src : 5; /* * Here, tile is set to Dest. */ + u32 rt : 1; + u32 key_size : 2; /* * determines which action that engine will take */ + u32 profile_id : 3; /* * indicates that requestor expect to receive a response data */ + u32 op_id : 5; + u32 a : 1; + u32 rsvd : 12; + u32 vld : 1; + u32 xy : 1; + u32 at : 1; +#else + u32 at : 1; + u32 xy : 1; + u32 vld : 1; /* * indicates that requestor expect to receive a response data */ + u32 rsvd : 12; /* * determines which action that engine will take */ + u32 a : 1; + u32 op_id : 5; + u32 profile_id : 3; + u32 key_size : 2; + u32 rt : 1; + u32 src : 5; +#endif + } bs; + + /* * Define an unsigned member */ + u32 value; + } dw0; + union { + struct { + u32 rsvd : 1; /* * Set tile to Dest. */ + u32 address : 15; + + u32 table_type : 5; + u32 ip_type : 1; + u32 func_id : 10; + } bs; + + u32 value; + } misc; + + u32 src_ip[4]; + u32 dst_ip[4]; + + u16 src_port; + u16 dst_port; + + u8 protocol; + u8 tcp_flag; + u8 fcoe_rctl; + u8 fcoe_type; + u16 eth_type; + + // If the u16 frame_size; /* range is matched, the */ is not performed temporarily. +} sml_lli_5tuple_key_s; + +/** + * Struct name: sml_lli_5tuple_rsp_s + * @brief lli_5tuple_rsp + * Description: xxxxxxxxxxxxxxx + */ +typedef struct tag_sml_lli_5tuple_rsp { + union { + struct { + u32 state : 4; + u32 rsvd : 28; + } bs; + + u32 value; + } dw0; + + u32 dw1; + + union { + struct { + u32 frame_size : 16; + u32 lli_en : 8; + u32 rsvd : 8; + } bs; + + u32 value; + } dw2; + + u32 dw3; +} sml_lli_5tuple_rsp_s; + +typedef union tag_sml_global_queue_tbl_elem { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 src_tag_l : 16; + u32 local_qid : 8; + u32 rsvd : 8; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 rsvd : 8; + u32 local_qid : 8; + u32 src_tag_l : 16; +#endif + } bs; + + u32 value; +} sml_global_queue_tbl_elem_u; + + +typedef struct tag_sml_global_queue_tbl { + sml_global_queue_tbl_elem_u element[TBL_ID_GLOBAL_QUEUE_NUM]; +} sml_global_queue_tbl_s; + +typedef struct tag_sml_dfx_log_tbl { + u32 wr_init_pc_h32; /* Initial value of write_pc */ + u32 wr_init_pc_l32; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 state : 8; + u32 func_en : 1; + u32 srctag : 12; + u32 max_num : 11; /* Maximum data block size */ +#else + u32 max_num : 11; /* Maximum data block size */ + u32 srctag : 12; + u32 func_en : 1; + u32 state : 8; +#endif + } bs; + u32 value; + } dw2; + + u32 ci_index; +} sml_dfx_log_tbl_s; + + +typedef struct tag_sml_glb_capture_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; + u32 max_num : 15; + u32 rsvd : 16; +#else + u32 rsvd : 16; + u32 max_num : 15; + u32 valid : 1; +#endif + } bs; + u32 value; + } dw0; + + u32 discard_addr_h32; + u32 discard_addr_l32; + + u32 rsvd0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; + u32 mode : 5; + u32 direct : 2; + u32 offset : 8; + u32 cos : 3; + u32 max_num : 13; +#else + u32 max_num : 13; + u32 cos : 3; + u32 offset : 8; + u32 direct : 2; + u32 mode : 5; + u32 valid : 1; +#endif + } bs; + u32 value; + } dw4; + + u32 data_vlan; + + u32 condition_addr_h32; + u32 condition_addr_l32; +} sml_glb_capture_tbl_s; + +typedef struct tag_sml_cqe_addr_tbl { + u32 cqe_first_addr_h32; + u32 cqe_first_addr_l32; + u32 cqe_last_addr_h32; + u32 cqe_last_addr_l32; +} sml_cqe_addr_tbl_s; + +/** + * Struct name: sml_ucode_exec_info_tbl_s + * @brief ucode execption info Table + * Description: microcode exception information table + */ +typedef struct tag_ucode_exec_info_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 wptr_cpb_ack_str : 4; /* Dispatch-streamout Write pointer position */ + u32 mem_cpb_ack_cnums_dma : 4; /* Number of pre-deducted cells that are actually consumed. */ + u32 mem_cpb_ack_cmd_mode : 2; /* ?? */ + u32 pr_ret_vld : 1; /* Pr_mc, 1: microcode pre-deduction, 0:OQ pre-deduction */ + u32 oeid_pd_pkt : 1; /* Check whether there are original packets in the abnormal message. */ + u32 rptr_cmd : 4; /* OEID socket read pointer */ + u32 wptr_cmd : 4; /* OEID socket write pointer */ + u32 src_tag_l : 12; /* HostID+Func_id, uP Where can I obtain??? */ +#else + u32 src_tag_l : 12; + u32 wptr_cmd : 4; + u32 rptr_cmd : 4; + u32 oeid_pd_pkt : 1; + u32 pr_ret_vld : 1; + u32 mem_cpb_ack_cmd_mode : 2; + u32 mem_cpb_ack_cnums_dma : 4; + u32 wptr_cpb_ack_str : 4; +#endif + } bs; + + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 fq : 16; /* Indicates the ID of the FQ where the OEID whose watch-dog times out is located. */ + u32 exception_type : 4; /* Exception type. If the value is 1, it indicates that the OEID is reclaimed. */ + u32 rptr_cpb_ack_str : 4; /* Dispatch-streamout Position of the read pointer */ + u32 header_oeid : 8; /* Indicates whether the header is a header OEID. */ +#else + u32 header_oeid : 8; + u32 rptr_cpb_ack_str : 4; + u32 exception_type : 4; + u32 fq : 16; +#endif + } bs; + + u32 value; + } dw1; + + u32 oeid_pd_data_l32; + u32 oeid_pd_data_m32; +} sml_ucode_exec_info_s; + +typedef struct rq_iq_mapping_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rq_bp_en : 3; + u32 rqid : 13; + u32 iqid : 8; + u32 portid : 8; +#else + u32 portid : 8; + u32 iqid : 8; + u32 rqid : 13; + u32 rq_bp_en : 3; +#endif + } bs; + u32 value; + } dw[4]; +} sml_rq_iq_mapping_tbl_s; + +typedef struct rq_iq_bp_state_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rq_id : 16; + u32 iq_mask : 8; + u32 port_id : 8; +#else + u32 port_id : 8; + u32 iq_mask : 8; + u32 rq_id : 16; +#endif + } bs; + u32 value; + } dw[4]; +} sml_rq_iq_bp_state_tbl_s; + +/* + * nic_ucode_rq_ctx table define + */ +typedef struct nic_ucode_rq_ctx { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ci : 16; + u32 pi : 16; + +#else + u32 pi : 16; + u32 ci : 16; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ceq_en : 1; + u32 int_num : 10; + u32 cqe_count : 10; + u32 rsv1_1st : 11; + +#else + u32 rsv1_1st : 11; + u32 cqe_count : 10; + u32 int_num : 10; + u32 ceq_en : 1; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 o_bit : 1; + u32 psge_valid : 1; + u32 wqe_type : 2; + u32 rsv0_1st : 8; + u32 ci_wqe_page_addr_h : 20; + +#else + u32 ci_wqe_page_addr_h : 20; + u32 rsv0_1st : 8; + u32 wqe_type : 2; + u32 psge_valid : 1; + u32 o_bit : 1; +#endif + } bs; + u32 value; + } dw2; + u32 ci_wqe_page_addr_l32; + + u32 rsvd[2]; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsv3_1st : 19; + u32 rq_id_vf : 13; + +#else + u32 rq_id_vf : 13; + u32 rsv3_1st : 19; +#endif + } bs; + u32 value; + } dw6; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsv2_1st : 2; + u32 cs_sge : 2; + u32 max_count : 10; + u32 cqe_template : 6; + u32 pkt_template : 6; + u32 wqe_template : 6; +#else + u32 wqe_template : 6; + u32 pkt_template : 6; + u32 cqe_template : 6; + u32 max_count : 10; + u32 cs_sge : 2; + u32 rsv2_1st : 2; +#endif + } bs; + u32 value; + } dw7; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 pft_min : 7; + u32 pft_max : 11; + u32 pft_thd : 14; +#else + u32 pft_thd : 14; + u32 pft_max : 11; + u32 pft_min : 7; +#endif + } bs; + u32 value; + } dw8; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsv0_2nd : 27; + u32 o_bit : 1; + u32 pft_ci_h : 4; +#else + u32 pft_ci_h : 4; + u32 o_bit : 1; + u32 rsv0_2nd : 27; +#endif + } bs; + u32 value; + } dw9; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 pft_ci_l : 12; + u32 pft_ci_page_addr_h : 20; +#else + u32 pft_ci_page_addr_h : 20; + u32 pft_ci_l : 12; +#endif + } bs; + u32 value; + } dw10; + + u32 pft_ci_page_addr_l; + + u32 pi_gpa_h; + u32 pi_gpa_l; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsv0_3rd : 9; + u32 ci_cla_addr_h : 23; +#else + u32 ci_cla_addr_h : 23; + u32 rsv0_3rd : 9; +#endif + } bs; + u32 value; + } dw14; + + u32 ci_cla_addr_l; +} nic_ucode_rq_ctx_s; + +/* + * nic_ucode_sq_ctx table define + */ +typedef struct nic_ucode_sq_ctx { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ci : 16; + u32 pi : 16; + +#else + u32 pi : 16; + u32 ci : 16; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 tso_fail_last_time : 2; + u32 rsv0_2nd : 19; + u32 err_code : 2; + u32 q_dis : 1; + u32 rsv0_1st : 5; + u32 tso_first_sge_vld : 1; + u32 drop_pkt_md : 1; + u32 sp_flag : 1; + +#else + u32 sp_flag : 1; + u32 drop_pkt_md : 1; + u32 tso_first_sge_vld : 1; + u32 rsv0_1st : 5; + u32 q_dis : 1; + u32 err_code : 2; + u32 rsv0_2nd : 19; + u32 tso_fail_last_time : 2; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 sge_num_left : 8; + u32 o_bit : 1; + u32 tso_doing : 1; + u32 processing_sge_id : 2; + u32 ci_wqe_page_addr_h : 20; + +#else + u32 ci_wqe_page_addr_h : 20; + u32 processing_sge_id : 2; + u32 tso_doing : 1; + u32 o_bit : 1; + u32 sge_num_left : 8; +#endif + } bs; + u32 value; + } dw2; + u32 ci_wqe_page_addr_l32; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsv3_1st : 24; + u32 sp_set_thd : 8; +#else + u32 sp_set_thd : 8; + u32 rsv3_1st : 24; +#endif + } bs; + u32 value; + } dw4; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 drop_pkt_off_thd : 16; + u32 drop_pkt_on_thd : 16; + +#else + u32 drop_pkt_on_thd : 16; + u32 drop_pkt_off_thd : 16; +#endif + } bs; + u32 value; + } dw5; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 pkt_template : 6; + u32 wqe_template : 6; + u32 rsv2_1st : 7; + u32 glb_sq_id : 13; +#else + u32 glb_sq_id : 13; + u32 rsv2_1st : 7; + u32 wqe_template : 6; + u32 pkt_template : 6; +#endif + } bs; + u32 value; + } dw6; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ceq_num : 8; + u32 ceq_en : 1; + u32 rsv1_1st : 2; + u32 vlan_inst_mode : 2; + u32 vlan_sel : 3; + u32 vlan_tag : 16; +#else + u32 vlan_tag : 16; + u32 vlan_sel : 3; + u32 vlan_inst_mode : 2; + u32 rsv1_1st : 2; + u32 ceq_en : 1; + u32 ceq_num : 8; +#endif + } bs; + u32 value; + } dw7; +} nic_ucode_sq_ctx_s; + + +/* mips exception info table defination */ +#define SML_MIPS_EXCP_TBL_ENTRY_NUM (256) +#define SML_MIPS_EXCP_TBL_ENTRY_SIZE (64) +typedef struct tag_sml_mips_exception_info_tbl { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 valid : 1; + u32 exception_code : 5; + u32 core_id : 6; + u32 thread_id : 2; + u32 rsvd1 : 8; + u32 io7_status : 5; + u32 io6_status : 5; +#else + u32 io6_status : 5; + u32 io7_status : 5; + u32 rsvd1 : 8; + u32 thread_id : 2; + u32 core_id : 6; + u32 exception_code : 5; + u32 valid : 1; +#endif + } bs; + + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd1 : 2; + u32 io5_status : 5; + u32 io4_status : 5; + u32 io3_status : 5; + u32 io2_status : 5; + u32 io1_status : 5; + u32 io0_status : 5; +#else + u32 io0_status : 5; + u32 io1_status : 5; + u32 io2_status : 5; + u32 io3_status : 5; + u32 io4_status : 5; + u32 io5_status : 5; + u32 rsvd1 : 2; +#endif + } bs; + + u32 value; + } dw1; + + u32 epc; + u32 status_info; + u32 push_data[4]; + u32 metadata[8]; +} sml_mips_exception_info_tbl_s; + +#define RQ_CTX_SIZE 64 +#define SQ_CTX_SIZE 64 + +/* + * ovs multi-table define + */ +typedef union tag_sml_ovs_mutil_tbl { + /* for qos store value table */ + struct { + u32 func_tx_cir; + u32 func_tx_cbs; + u32 func_tx_pir; + u32 func_tx_pbs; + + u32 func_rx_cir; + u32 func_rx_cbs; + u32 func_rx_pir; + u32 func_rx_pbs; + + u32 func_bcmc_limit; + u32 func_bcmc_burst; + + u32 upcall_cir_limit; + u32 upcall_cbs_burst; + u32 upcall_xir_limit; + u32 upcall_xbs_burst; + + u32 rsvd[2]; + } func_qos_value; + + struct { + u32 vm_tx_cir; + u32 vm_tx_cbs; + u32 vm_tx_pir; + u32 vm_tx_pbs; + + u32 vm_rx_cir; + u32 vm_rx_cbs; + u32 vm_rx_pir; + u32 vm_rx_pbs; + + u32 vm_rx_pps_limit; + u32 vm_rx_pps_burst; + + u32 vm_pps_limit; + u32 vm_pps_burst; + + u32 rsvd[4]; + } vm_qos_value; + + u32 value[16]; +} sml_ovs_mutil_tbl_u; + +/* + * ovs vlan to localtag table define + */ +#define OVS_VLAN_LOCALTAG_ITEM_NUM (4) +typedef struct tag_sml_vlan_localtag_tbl { + u32 localtag[OVS_VLAN_LOCALTAG_ITEM_NUM]; +} sml_vlan_localtag_tbl_s; + +#define OVS_VM_MAX_FUNCTION_NUM 16 + +typedef union function_valid_unit { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 func_num_h3bit : 3; /* when index=0, function_num_high_3bit; */ + u16 function_valid : 1; + u16 function_id : 12; +#else + u16 function_id : 12; + u16 function_valid : 1; + u16 func_num_h3bit : 3; +#endif + } item0; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 func_num_l3bit : 3; /* when index=1, function_num_low_3bit */ + u16 function_valid : 1; + u16 function_id : 12; +#else + u16 function_id : 12; + u16 function_valid : 1; + u16 func_num_l3bit : 3; +#endif + } item1; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 rsvd : 1; + u16 vm_bps_cfg : 1; /* only index=2, vm_bps_cfg is valid */ /* only index=3, vm_rx_bps_cfg is valid */ + u16 vm_pps_cfg : 1; /* only index=2, vm_pps_cfg is valid */ /* only index=3, vm_rx_pps_cfg is valid */ + u16 function_valid : 1; + u16 function_id : 12; +#else + u16 function_id : 12; + u16 function_valid : 1; + u16 vm_pps_cfg : 1; + u16 vm_bps_cfg : 1; + u16 rsvd : 1; +#endif + } bs; + + u16 value; +} function_valid_unit_u; + +typedef struct tag_sml_vm_mapping_tbl { + function_valid_unit_u func_vld_unit[OVS_VM_MAX_FUNCTION_NUM]; +} sml_vm_mapping_tbl_s; + +typedef struct tag_ovs_vtep_tun_info_tbl { + /* dw0~dw2 */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 dmac_h : 16; + u32 dmac_m : 16; + + u32 dmac_l : 16; + u32 smac_h : 16; + + u32 smac_m : 16; + u32 smac_l : 16; +#else + u32 dmac_m : 16; + u32 dmac_h : 16; + + u32 smac_h : 16; + u32 dmac_l : 16; + + u32 smac_l : 16; + u32 smac_m : 16; +#endif + u32 sip; + u32 dip; +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vlan_id : 16; + u32 udp_sport : 16; + + u32 rsvd : 8; + u32 vni : 24; +#else + u32 udp_sport : 16; + u32 vlan_id : 16; + + u32 vni : 24; + u32 rsvd : 8; +#endif + +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd1 : 16; + u32 output_id : 16; +#else + u32 output_id : 16; + u32 rsvd1 : 16; +#endif + + u8 tap_name[32]; +} sml_ovs_vtep_tun_info_tbl_s; + +typedef union { + u32 mac32_s[3]; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 smac_h : 16; + u32 smac_m : 16; + + u32 smac_l : 16; + u32 dmac_h : 16; + + u32 dmac_m : 16; + u32 dmac_l : 16; +#else + u32 smac_m : 16; + u32 smac_h : 16; + + u32 dmac_h : 16; + u32 smac_l : 16; + + u32 dmac_l : 16; + u32 dmac_m : 16; +#endif + } mac16_s; +} sml_ovs_cap_dmac_smac_u; + +typedef union tag_ovs_pcap_precfg { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vport_id : 16; + u32 rsvd : 6; + u32 direct_in : 1; + u32 direct_out : 1; + u32 vxlan_inner : 3; + u32 valid : 1; + u32 rule_idx : 3; + u32 all_pass : 1; +#else + u32 all_pass : 1; + u32 rule_idx : 3; + u32 valid : 1; + u32 vxlan_inner : 3; + u32 direct_out : 1; + u32 direct_in : 1; + u32 rsvd : 6; + u32 vport_id : 16; +#endif + } bs; + u32 value; +} ovs_pcap_precfg_u; + +typedef struct tag_sml_ovs_pcap_precfg_tbl { + ovs_pcap_precfg_u pcap_precfg[8]; + u32 rsvd[8]; +} sml_ovs_pcap_precfg_tbl_s; + +typedef struct tag_sml_ovs_pcap_filter_ipv6 { + u32 sipv6_0; + u32 sipv6_1; + u32 sipv6_2; + u32 sipv6_3; + + u32 dipv6_0; + u32 dipv6_1; + u32 dipv6_2; + u32 dipv6_3; + + u32 hipv6_0; + u32 hipv6_1; + u32 hipv6_2; + u32 hipv6_3; + + u32 rsvd0; + u32 rsvd1; + u32 rsvd2; + u32 rsvd3; +} sml_ovs_pcap_filter_ipv6_s; + +typedef union { + u32 mask_ipv4; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 m0 : 8; /* mask number for sipv6_0/dipv6_0/hipv6_0 */ + u32 m1 : 8; /* mask number for sipv6_1/dipv6_1/hipv6_1 */ + u32 m2 : 8; /* mask number for sipv6_2/dipv6_2/hipv6_2 */ + u32 m3 : 8; /* mask number for sipv6_3/dipv6_3/hipv6_3 */ +#else + u32 m3 : 8; + u32 m2 : 8; + u32 m1 : 8; + u32 m0 : 8; +#endif + } mask_ipv6; +} ip_mask_u; + +typedef union tag_sml_ovs_pcap_mask { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 smac_en : 1; + u16 dmac_en : 1; + u16 vlan_en : 1; + u16 eth_type_en : 1; + u16 sip_en : 1; + u16 dip_en : 1; + u16 host_ip_en : 1; + u16 dscp_en : 1; + u16 proto_en : 1; + u16 sport_en : 1; + u16 dport_en : 1; + u16 cnter_en : 1; + u16 vni_en : 1; + u16 ip_type : 1; + u16 host_port_en : 1; + u16 rsvd : 1; +#else + u16 rsvd : 1; + u16 host_port_en : 1; + u16 ip_type : 1; + u16 vni_en : 1; + u16 cnter_en : 1; + u16 dport_en : 1; + u16 sport_en : 1; + u16 proto_en : 1; + u16 dscp_en : 1; + u16 host_ip_en : 1; + u16 dip_en : 1; + u16 sip_en : 1; + u16 eth_type_en : 1; + u16 vlan_en : 1; + u16 dmac_en : 1; + u16 smac_en : 1; +#endif + } bs; + u16 value; +} sml_ovs_pcap_mask_u; + +typedef struct tag_sml_ovs_pcap_cfg_tbl { +#if (BYTE_ORDER == BIG_ENDIAN) + sml_ovs_pcap_mask_u mask; + u16 vport_id; +#else + u16 vport_id; + sml_ovs_pcap_mask_u mask; +#endif + /* filter */ + sml_ovs_cap_dmac_smac_u dmac_smac; + u32 sip; + u32 dip; + u32 host_ip; + ip_mask_u sip_mask; + ip_mask_u dip_mask; + ip_mask_u host_mask; +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vlan_id : 16; + u32 eth_type : 16; + + u32 dport : 16; + u32 sport : 16; /* multiplex with host_port */ + + u32 dscp : 8; + u32 ip_proto : 8; + u32 qid : 16; + + u32 vni : 24; + u32 pf_id : 8; +#else + u32 eth_type : 16; + u32 vlan_id : 16; + + u32 sport : 16; /* multiplex with host_port */ + u32 dport : 16; + + u32 qid : 16; + u32 ip_proto : 8; + u32 dscp : 8; + + u32 pf_id : 8; + u32 vni : 24; +#endif + u64 counter; +} sml_ovs_pcap_cfg_tbl_s; + +typedef struct tag_sml_ovs_etp_bitmap_info { + u32 bitmap[2]; + u32 rsvd[2]; +} sml_ovs_etp_bitmap_s; + +typedef struct tag_sml_ovs_etp_filter_tbl_info { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 qid : 16; + u32 vport_id : 16; + + u32 pf_id : 8; + u32 vpn_etp_drop : 1; + u32 hwc_etp_drop : 1; + u32 etp_type : 3; + u32 rsvd1 : 19; +#else + u32 vport_id : 16; + u32 qid : 16; + + u32 rsvd1 : 19; + u32 etp_type : 3; + u32 hwc_etp_drop : 1; + u32 vpn_etp_drop : 1; + u32 pf_id : 8; +#endif + u32 hwc_etp_tpid[4]; + u32 vpn_etp_tpid[4]; + u32 rsvd[2]; + sml_ovs_etp_bitmap_s etp_bitmap; // in order to save memory, reused this entry, it's only valid in the first entry +} sml_ovs_etp_filter_tbl_s; + +/* can't change, api struct export to evs */ +typedef union tag_ovs_fm_thrd_en_bitmap { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 rsvd : 9; + u16 thrd_icmp_latency_en : 1; + u16 thrd_icmp_pkt_loss_en : 1; + u16 thrd_tcp_latency_en : 1; + u16 thrd_downtime_en : 1; + u16 thrd_cnt_timeout_retrans_en : 1; + u16 thrd_cnt_retrans_en : 1; + u16 periodical_enable : 1; +#else + u16 periodical_enable : 1; + u16 thrd_cnt_retrans_en : 1; + u16 thrd_cnt_timeout_retrans_en : 1; + u16 thrd_downtime_en : 1; + u16 thrd_tcp_latency_en : 1; + u16 thrd_icmp_pkt_loss_en : 1; + u16 thrd_icmp_latency_en : 1; + u16 rsvd : 9; +#endif + } bs; + u16 value; +} ovs_fm_thrd_bitmap_u; + +/* can't change, api struct export to evs, total 7*4 bytes */ +typedef struct tag_ovs_fm_threshold { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 thrd_cnt_retrans; /* threshold for retransmission */ + ovs_fm_thrd_bitmap_u thrd_en_bitmap; + + u8 thrd_cnt_timeout_retrans; /* threshold for timeout-retransmission */ + u8 rsvd; + u16 thrd_icmp_pkt_loss; /* threshold for icmp packet loss */ +#else + ovs_fm_thrd_bitmap_u thrd_en_bitmap; + u16 thrd_cnt_retrans; + + u16 thrd_icmp_pkt_loss; + u8 rsvd; + u8 thrd_cnt_timeout_retrans; +#endif + u32 thrd_downtime; /* threshold for downtime report, uint: ms */ + u32 thrd_tcp_latency; /* threshold for tcp latency, uint: us */ + u32 thrd_icmp_latency; /* threshold for icmp latency, unit: us */ + u32 rsvd2[2]; +} ovs_fm_threshold_s; +/* can't change, api struct export to evs, total 2*4 bytes */ +typedef struct tag_ovs_fm_rule1 { +#if (BYTE_ORDER == BIG_ENDIAN) + u8 proto; /* 0x1: ICMP, 0x6:TCP */ + u8 glb_rule_id; /* max 8 rules */ + u8 rule_id; /* now support 0 & 1, max two rules one vport */ + u8 rsvd0 : 4; + u8 ip_type : 1; /* 1: ipv6, 0: ipv4 */ + u8 first_last_rule : 1; /* when add, 1 means first, others 0; when del, 1 means last, others 0. */ + u8 rule_enable : 2; /* 2:del all, 1: add, 0: del */ + + u16 vport_id; /* get by hovs_port_mgmt_add, hovs_port_mgmt_add_dynamic */ + u16 rsvd; +#else + u8 rule_enable : 2; /* 2:del all, 1: add, 0: del */ + u8 first_last_rule : 1; /* when add, 1 means first, others 0; when del, 1 means last, others 0. */ + u8 ip_type : 1; /* 1: ipv6, 0: ipv4 */ + u8 rsvd0 : 4; + u8 rule_id; /* now support 0 & 1, max two rules one vport */ + u8 glb_rule_id; /* max 8 rules */ + u8 proto; /* 0x1: ICMP, 0x6:TCP */ + + u16 rsvd; /* get by hovs_port_mgmt_add, hovs_port_mgmt_add_dynamic */ + u16 vport_id; +#endif +} ovs_fm_rule1_s; +/* can't change, api struct export to evs, total 2*4 bytes */ +typedef struct tag_ovs_fm_rule_port { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 port_src_end; + u16 port_src_start; + + u16 port_dst_end; + u16 port_dst_start; +#else + u16 port_src_start; + u16 port_src_end; + + u16 port_dst_start; + u16 port_dst_end; +#endif +} ovs_fm_rule_port_s; + +/* can't change, api struct export to evs, total 27*4 bytes */ +typedef struct tag_ovs_fm_rule { + ovs_fm_rule1_s fm_rule1; + u32 ip_src_start[4]; /* when ipv4, ip_src_start[0] is valid */ + u32 ip_src_end[4]; /* when ipv4, ip_src_end[0] is valid */ + u32 ip_dst_start[4]; /* when ipv4, ip_dst_start[0] is valid */ + u32 ip_dst_end[4]; /* when ipv4, ip_dst_end[0] is valid */ + ovs_fm_rule_port_s fm_rule_port; + ovs_fm_threshold_s fm_thrd; +} ovs_fm_rule_s; + +/* rule hint accelarate rule filter */ +typedef struct tag_rule_tbl_hint_dw { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 rule_tbl_hint_1; + u16 rule_tbl_hint_0; +#else + u16 rule_tbl_hint_0; + u16 rule_tbl_hint_1; +#endif +} rule_tbl_hint_dw_s; + +/* sml_ovs_fm_ctl_tbl_info_s use index 0 entry */ +typedef struct tag_sml_ovs_fm_ctl_tbl_info { + u32 period; /* unit is us */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 queue_id : 16; + u32 pf_id : 16; +#else + u32 pf_id : 16; + u32 queue_id : 16; +#endif + ovs_fm_threshold_s thrd; + u32 rsvd[3]; + + rule_tbl_hint_dw_s rule_tbl_hint_dw[4]; +} sml_ovs_fm_ctl_tbl_info_s; + +/* sml_ovs_fm_rule_tbl_info_s use index 1-8 entry */ +typedef struct tag_sml_ovs_fm_rule_tbl_info { + ovs_fm_rule1_s fm_rule1; + u32 ip_src_start; + u32 ip_src_end; + u32 ip_dst_start; + u32 ip_dst_end; + ovs_fm_rule_port_s fm_rule_port; + ovs_fm_threshold_s thrd; +#if (BYTE_ORDER == BIG_ENDIAN) + u16 func_id; + u16 rsvd; +#else + u16 rsvd; + u16 func_id; +#endif +} sml_ovs_fm_rule_tbl_info_s; + +/* + * Struct name: sml_tapname_tbl_16_12_key_s + * @brief migration tap_name key + * Description: migration tap_name key define + */ +typedef struct tag_sml_tapname_tbl_16_12_key { + u8 tap_name[16]; +} sml_tapname_tbl_16_12_key_s; + +/* + * Struct name: sml_tapname_tbl_16_12_item_s + * @brief migration tap_name item + * Description: migration tap_name define + */ +typedef struct tag_sml_tapname_tbl_16_12_item { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd1 : 16; + u32 func_id : 16; +#else + u32 func_id : 16; + u32 rsvd1 : 16; +#endif + u32 rsvd2; + u32 rsvd3; +} sml_tapname_tbl_16_12_item_s; + +typedef struct tag_ovs_vport_upcall_queue { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 pf_id : 3; /* local pf_id */ + u16 queue_id : 13; /* global queue id */ +#else + u16 queue_id : 13; + u16 pf_id : 3; +#endif +} ovs_vport_upcall_queue_s; + +#define OVS_MAX_UPCALL_QUEUE_CNT 16 +typedef struct tag_sml_ovs_vport_upcall_queue { + ovs_vport_upcall_queue_s upcall_q[OVS_MAX_UPCALL_QUEUE_CNT]; +} sml_ovs_vport_upcall_queue_s; + +typedef struct tag_mig_lt_header { + u32 log_buffer_size; /* dw0-total dirty size */ + u32 sge_len; /* dw1-mig dirty block size */ + u32 err_cnt; /* dw2-record err cnt for drive requirement */ + u32 rsvd; +} mig_lt_header_s; + +typedef struct tag_sml_ipsec_spv4_key { + u32 saddr; + u32 daddr; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 sport : 16; + u32 dport : 16; +#else + u32 dport : 16; + u32 sport : 16; +#endif + } bs; + u32 value; + } key_dw2; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 24; + u32 ulp_proto : 8; +#else + u32 ulp_proto : 8; + u32 rsvd : 24; +#endif + } bs; + u32 value; + } key_dw3; + + u32 key_dw4; + u32 key_dw5; + u32 key_dw6; + u32 key_dw7; +} sml_ipsec_spv4_key_s; + +typedef struct tag_sml_ipsec_spv6_key { + u32 saddr[4]; + u32 daddr[4]; +} sml_ipsec_spv6_key_s; + +typedef struct tag_sml_ht_ipsec_spd_32_20_key { + union { + sml_ipsec_spv4_key_s v4; + sml_ipsec_spv6_key_s v6; + } key; +} sml_ht_ipsec_spd_32_20_key_s; + +typedef struct tag_sml_ht_ipsec_spd_32_20_item { + u32 spi; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 10; + u32 action : 5; + u32 iptype : 1; + u32 ulp_proto : 8; + u32 ipsec_proto : 8; +#else + u32 ipsec_proto : 8; + u32 ulp_proto : 8; + u32 iptype : 1; + u32 action : 5; + u32 rsvd : 10; +#endif + } bs; + + u32 value; + } item_dw1; + u32 item_dw2; + u32 item_dw3; + u32 item_dw4; +} sml_ht_ipsec_spd_32_20_item_s; + +typedef struct tag_sml_ht_ipsec_sad_32_20_key { + u32 daddr[4]; + u32 spi; + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 24; + u32 ipsec_proto : 8; +#else + u32 ipsec_proto : 8; + u32 rsvd : 24; +#endif + } bs; + u32 value; + } key_dw5; + u32 key_dw6; + u32 key_dw7; +} sml_ht_ipsec_sad_32_20_key_s; + +typedef struct tag_sml_ht_ipsec_sad_32_20_item { + u32 exchange_id; + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ulp : 16; /* [31:16] */ + u32 auth_type : 4; /* [15:12] */ + u32 enc_type : 4; /* [11:8] */ + u32 alg_type : 2; /* [7:6] */ + u32 alg_standard : 2; /* [5:4] */ + u32 dir : 2; /* [3:2] */ + u32 iptype : 2; /* [1:0] */ +#else + u32 iptype : 2; /* [0:1] */ + u32 dir : 2; /* [2:3] */ + u32 alg_standard : 2; /* [4:5] */ + u32 alg_type : 2; /* [6:7] */ + u32 enc_type : 4; /* [8:11] */ + u32 auth_type : 4; /* [12:15] */ + u32 ulp : 16; /* [16:31] */ +#endif + } bs; + u32 value; + } item_dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 16; /* [31:16] */ + u32 funcid : 16; /* [15:0] */ +#else + u32 funcid : 16; /* [0:15] */ + u32 rsvd : 16; /* [16:31] */ +#endif + } bs; + u32 value; + } item_dw2; + + u32 item_dw3; + u32 item_dw4; +} sml_ht_ipsec_sad_32_20_item_s; + +typedef struct tag_sml_flexq_mapping_tbl_8_4_key { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 func_id : 12; + u32 local_qid : 16; + u32 rsvd : 4; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 rsvd : 4; + u32 local_qid : 16; + u32 func_id : 12; +#endif + } dw0; + + u32 dw1; +} sml_flexq_map_tbl_8_4_key_s; + +typedef struct tag_sml_flexq_tbl_8_4 { + sml_mac_tbl_head_u head; + sml_flexq_map_tbl_8_4_key_s key; + u32 item; +} sml_flexq_tbl_8_4_s; + +typedef struct tag_sml_ovs_etp_xtrace_info { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 pf_id : 8; + u32 qid : 16; + u32 proto : 8; +#else + u32 proto : 8; + u32 qid : 16; + u32 pf_id : 8; +#endif + + u32 sip; + u32 dip; + u32 sip_mask; + u32 dip_mask; + +#if (BYTE_ORDER == BIG_ENDIAN) + u32 sport_start : 16; + u32 sport_end : 16; + u32 dport_start : 16; + u32 dport_end : 16; +#else + u32 sport_end : 16; + u32 sport_start : 16; + u32 dport_end : 16; + u32 dport_start : 16; +#endif + + u32 rsvd; +} sml_ovs_etp_xtrace_info_s; + +/* safe gpa context Format start */ +typedef struct tag_sml_vmsec_ctx_gpa_tbl { + u32 gpa_addr0_hi; + u32 gpa_addr0_lo; + u32 gpa_len0; + u32 rsvd; +} sml_vmsec_ctx_gpa_tbl_s; +/* safe gpa context Format end */ + +/* pci hole gpa context Format start */ +typedef struct tag_sml_vmsec_pci_hole_gpa_tbl { + /* pci hole 32-bit region */ + u32 gpa_addr0_hi; + u32 gpa_addr0_lo; + u32 gpa_len0_hi; + u32 gpa_len0_lo; + + /* pci hole 64-bit region */ + u32 gpa_addr1_hi; + u32 gpa_addr1_lo; + u32 gpa_len1_hi; + u32 gpa_len1_lo; + + u32 domain_id; +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 21; + u32 vf_nums : 11; +#else + u32 vf_nums : 11; + u32 rsvd : 21; +#endif + u32 vroce_vf_bitmap; + u32 rsvd1[5]; +} sml_vmsec_pci_hole_gpa_tbl_s; +/* pci hole gpa context Format end */ + +typedef struct tag_sml_vroce_vf_tbl { + u32 vtep_ip; + u32 racl_id; +#if (BYTE_ORDER == BIG_ENDIAN) + u32 ctrl_pf_func_id : 16; + u32 vlan_id : 12; + u32 bond_id : 4; + + u32 vni : 24; + u32 vni_en : 8; + + u32 vtep_mac_h : 16; + u32 vtep_mac_m : 16; + + u32 vtep_mac_l : 16; + u32 default_gwmac_h : 16; + + u32 default_gwmac_m : 16; + u32 default_gwmac_l : 16; + + u32 dscp_rc : 8; + u32 dscp_ud : 8; + u32 set_flags : 8; + u32 base_id : 8; + + u32 host_id : 8; + u32 cos_num_rc : 3; + u32 cos_num_ud : 3; + u32 cos_num_xrc : 3; + u32 group_rc : 3; + u32 group_ud : 3; + u32 group_xrc : 3; + u32 dscp_xrc : 6; + + u16 rsvd0; + u16 func_id; + + u32 rsvd[2]; +#else + u32 bond_id : 4; + u32 vlan_id : 12; + u32 ctrl_pf_func_id : 16; + + u32 vni_en : 8; + u32 vni : 24; + + u32 vtep_mac_m : 16; + u32 vtep_mac_h : 16; + + u32 default_gwmac_h : 16; + u32 vtep_mac_l : 16; + + u32 default_gwmac_l : 16; + u32 default_gwmac_m : 16; + + u32 base_id : 8; + u32 set_flags : 8; + u32 dscp_ud : 8; + u32 dscp_rc : 8; + + u32 dscp_xrc : 6; + u32 group_xrc : 3; + u32 group_ud : 3; + u32 group_rc : 3; + u32 cos_num_xrc : 3; + u32 cos_num_ud : 3; + u32 cos_num_rc : 3; + u32 host_id : 8; + + u16 func_id; + u16 rsvd0; + + u32 rsvd[2]; +#endif +} sml_vroce_vf_tbl_s; + +typedef struct tag_sml_glb_tbl_roce_cfg { + u32 dw0; + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 cmtt_cl_start : 10; + u32 cmtt_cl_end : 10; + u32 cmtt_cl_size : 2; + u32 rsvd : 10; +#else + u32 rsvd : 10; + u32 cmtt_cl_size : 2; + u32 cmtt_cl_end : 10; + u32 cmtt_cl_start : 10; +#endif + }bs; + u32 value; + }dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 dmtt_cl_start : 10; + u32 dmtt_cl_end : 10; + u32 dmtt_cl_size : 2; + u32 rsvd : 10; +#else + u32 rsvd : 10; + u32 dmtt_cl_size : 2; + u32 dmtt_cl_end : 10; + u32 dmtt_cl_start : 10; +#endif + }bs; + u32 value; + }dw2; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 wqe_cl_start : 10; + u32 wqe_cl_end : 10; + u32 wqe_cl_size : 2; + u32 rsvd : 10; +#else + u32 rsvd : 10; + u32 wqe_cl_size : 2; + u32 wqe_cl_end : 10; + u32 wqe_cl_start : 10; +#endif + }bs; + u32 value; + }dw3; + + u32 rsvd[12]; +} sml_glb_tbl_roce_cfg_s; + +typedef struct tag_sml_glb_vroce { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vlan_id : 12; + u32 rsvd : 20; +#else + u32 rsvd : 20; + u32 vlan_id : 12; +#endif + } bs; + u32 value; + } dw0; + + u32 rsvd[15]; +} sml_glb_tbl_vroce_s; + +typedef struct tag_sml_vroce_filter_tbl { + u32 dst_qpn; + u32 sip; + u32 dip; + u32 sport; + u32 opcode; + u32 pos; + u32 count; + u32 set_flags; +} sml_vroce_filter_tbl_s; + +typedef struct tag_sml_ovs_mirror_vport_key { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 vport : 12; + u32 session_id : 20; +#else + u32 session_id : 20; + u32 vport : 12; +#endif + u32 rsvd; /* align to 8B */ +} sml_ovs_mirror_vtep_key_s; + +typedef struct tag_sml_ovs_mirror_vport_info { + u32 outer_vni; + u32 outer_dip; +#if (BYTE_ORDER == BIG_ENDIAN) + u8 inner_dmac[6]; + u16 rsvd0; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u8 inner_dmac3; + u8 inner_dmac2; + u8 inner_dmac1; + u8 inner_dmac0; + u16 rsvd0; + u8 inner_dmac5; + u8 inner_dmac4; +#endif + u32 rsvd1; /* align to 20B */ +} sml_ovs_mirror_vtep_info_s; + +typedef struct tag_sml_ovs_mirror_global_info { +#if (BYTE_ORDER == BIG_ENDIAN) + u8 outer_dmac[6]; + u8 outer_smac[6]; + u32 outer_sip; + u16 outer_dport; + u16 outer_vlan_id; + u8 inner_smac[6]; + u16 rsvd0; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u8 outer_dmac3; + u8 outer_dmac2; + u8 outer_dmac1; + u8 outer_dmac0; + u8 outer_smac1; + u8 outer_smac0; + u8 outer_dmac5; + u8 outer_dmac4; + u8 outer_smac5; + u8 outer_smac4; + u8 outer_smac3; + u8 outer_smac2; + u32 outer_sip; + u16 outer_vlan_id; + u16 outer_dport; + u8 inner_smac3; + u8 inner_smac2; + u8 inner_smac1; + u8 inner_smac0; + u16 rsvd0; + u8 inner_smac5; + u8 inner_smac4; +#endif + u32 rsvd[1]; /* align to 32B */ +} sml_ovs_mirror_global_info_s; + +typedef struct tag_sml_ovs_mirror_session_info { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 enabled; + u16 inner_dport; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u16 inner_dport; + u16 enabled; +#endif + u32 inner_dip; + u32 inner_vni; + u32 mirror_len; +} sml_ovs_mirror_session_info_s; + + +typedef struct tag_sml_ovs_mirror_tbl_16_36_key { + u32 rsvd[3]; + u32 session_id; +} sml_ovs_mirror_tbl_16_36_key_s; + +/** + * Struct name: sml_mac_tbl_16_12_key_u + * @brief Mac Table Key + * Key of the Description: vroce MAC table. + */ +typedef union tag_sml_mac_tbl_16_12_key { + struct { + u32 dw0; + u32 dw1; + u32 dw2; + u32 dw3; + } value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 er_id : 4; + u32 vlan_vni : 24; + u32 rvsd1 : 4; + + u32 mac_h16 : 16; + u32 mac_m16 : 16; + + u32 mac_l16 : 16; + u32 rvsd2 : 16; + + u32 rvsd3; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 rvsd1 : 4; + u32 vlan_vni : 24; + u32 er_id : 4; + + u32 mac_m16 : 16; + u32 mac_h16 : 16; + + u32 rvsd2 : 16; + u32 mac_l16 : 16; + + u32 rvsd3; +#endif + } bs; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 er_id : 4; + u32 vlan_vni : 24; + u32 rvsd0 : 4; + + u32 mac0 : 8; + u32 mac1 : 8; + u32 mac2 : 8; + u32 mac3 : 8; + + u32 mac4 : 8; + u32 mac5 : 8; + u32 rvsd1 : 16; + + u32 rvsd4; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 rvsd0 : 4; + u32 vlan_vni : 24; + u32 er_id : 4; + + u32 mac3 : 8; + u32 mac2 : 8; + u32 mac1 : 8; + u32 mac0 : 8; + + u32 rvsd1 : 16; + u32 mac5 : 8; + u32 mac4 : 8; + + u32 rvsd4; +#endif + } mac_bs; +} sml_mac_tbl_16_12_key_u; + +/** + * Struct name: sml_mac_tbl_16_12_item_u + * @brief Mac Table Item + * Description: vroce MAC table + */ +typedef union tag_sml_mac_tbl_16_12_item { + struct { + u32 dw0; + u32 dw1; + u32 dw2; + } value; + + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 7; + u32 single_ip_en : 1; + u32 single_ip_srv_mode : 1; + u32 host_id : 3; + u32 fwd_type : 4; + u32 fwd_id : 16; + + u32 rsvd1[2]; +#elif (BYTE_ORDER == LITTLE_ENDIAN) + u32 fwd_id : 16; + u32 fwd_type : 4; + u32 host_id : 3; + u32 single_ip_srv_mode : 1; + u32 single_ip_en : 1; + u32 rsvd : 7; + + u32 rsvd1[2]; +#endif + } bs; +} sml_mac_tbl_16_12_item_u; + +/** + * Struct name: sml_mac_tbl_key_item_s + * @brief Mac Table( 16 + 12 ) + * Description: vroce MAC table Key + Item + */ +typedef struct tag_sml_mac_tbl_16_12 { + sml_mac_tbl_head_u head; + sml_mac_tbl_16_12_key_u key; + sml_mac_tbl_16_12_item_u item; +} sml_mac_tbl_16_12_s; + +typedef struct tag_sml_mac_tbl_look_up_key_16 { + sml_mac_tbl_head_u head; + sml_mac_tbl_16_12_key_u key; +} sml_mac_tbl_look_up_key_16; + +typedef struct tag_sml_mac_tbl_look_up_rsp_12 { + sml_mac_tbl_head_u head; + sml_mac_tbl_16_12_item_u item; +} sml_mac_tbl_look_up_rsp_12; + +#endif /* L2_TABLE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_cloud.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_cloud.h new file mode 100644 index 000000000..85624a136 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_cloud.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: Header File, SML Table define for cloud + * Create: 2022/01/08 + */ + +#ifndef SML_TABLE_DEFINE_CLOUD_H +#define SML_TABLE_DEFINE_CLOUD_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_OVS_MAC_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MAC_FILTER_SM_INST 6 + +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_INST 7 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 8 + +#define TBL_ID_OVS_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_CAR_SM_INST 9 + +#define TBL_ID_OVS_FM_PAIR_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_FM_PAIR_CTR_SM_INST 10 + +#define TBL_ID_DSW_BASE_IOCB_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_BASE_IOCB_BHEAP_SM_INST 11 + +#define TBL_ID_DSW_VOLQ_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_VOLQ_BHEAP_SM_INST 12 + +#define TBL_ID_ROCE_DCC_FUNC_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_DCC_FUNC_SM_INST 13 + +#define TBL_ID_ROCE_RTT_REQUEST_CACHE_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_RTT_REQUEST_CACHE_SM_INST 14 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 15 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 16 + +#define TBL_ID_ROCE_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_BHEAP_SM_INST 17 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 18 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 19 + +#define TBL_ID_VSOCK_IOCB_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_VSOCK_IOCB_BHEAP_SM_INST 20 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 21 + +#define TBL_ID_FUSHION_QUEUE_VALID_MAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_FUSHION_QUEUE_VALID_MAP_SM_INST 22 + +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_INST 23 + +#define TBL_ID_VIRTIO_INTR_AGING_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_AGING_SM_INST 24 + +#define TBL_ID_BOOT_BASE_IOCB_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOOT_BASE_IOCB_BHEAP_SM_INST 25 + +#define TBL_ID_ROCE_MIG_SAFE_GPA_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_MIG_SAFE_GPA_SM_INST 26 + +#define TBL_ID_ROCE_PCI_HOLE_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_PCI_HOLE_SM_INST 27 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_ELB_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_OVS_SHARE_PLANE_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_SHARE_PLANE_SM_INST 11 + +#define TBL_ID_OVS_UPCALL_QUEUE_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_UPCALL_QUEUE_SM_INST 12 + +#define TBL_ID_CTR_DFX_OVS_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_OVS_S16_SM_INST 13 + +#define TBL_ID_DSW_EXTEND_IOCB_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_DSW_EXTEND_IOCB_BHEAP_SM_INST 14 + +#define TBL_ID_TOE_IO_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_TOE_IO_BHEAP_SM_INST 15 + +#define TBL_ID_ROCE_VFCFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_VFCFG_SM_INST 16 + +#define TBL_ID_ROCE_ONE_WINDOW_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_ONE_WINDOW_SM_INST 17 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S32_SM_INST 21 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_INST 23 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_OVS_CAPTURE_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_CAPTURE_SM_INST 4 + +#define TBL_ID_ROCE_DCC_MCODE_CTX_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DCC_MCODE_CTX_SM_INST 5 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 6 + +#define TBL_ID_ROCE_VF_PROBE_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_VF_PROBE_SM_INST 7 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 8 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 9 + +#define TBL_ID_TOE_IO_HASH_SM_NODE NODE_ID_SML2 +#define TBL_ID_TOE_IO_HASH_SM_INST 10 + +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_NODE NODE_ID_SML2 +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_INST 11 + +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_INST 12 + +#define TBL_ID_OVS_MIRROR_SESSION_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_MIRROR_SESSION_SM_INST 13 + +#define TBL_ID_OVS_VPC_INFO_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_VPC_INFO_SM_INST 14 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 + +#define TBL_ID_OVS_VM_MAPPING_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VM_MAPPING_SM_INST 3 + +#define TBL_ID_OVS_ETP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_ETP_SM_INST 4 + +#define TBL_ID_OVS_FM_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_SM_INST 5 + +#define TBL_ID_OVS_FM_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_BHEAP_SM_INST 6 + +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST 7 + +#define TBL_ID_DSW_VOLQ_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_DSW_VOLQ_HASH_SM_INST 8 + +#define TBL_ID_DSW_IOCB_SM_NODE NODE_ID_SML3 +#define TBL_ID_DSW_IOCB_SM_INST 9 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_PARAM_SM_INST 10 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_CTX_SM_INST 11 + +#define TBL_ID_DSW_VSOCK_IOCB_SM_NODE NODE_ID_SML3 +#define TBL_ID_DSW_VSOCK_IOCB_SM_INST 12 + +#define TBL_ID_OVS_XTRACE_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_XTRACE_SM_INST 13 + +#define TBL_ID_MIGRATE_ADDR_SM_NODE NODE_ID_SML3 +#define TBL_ID_MIGRATE_ADDR_SM_INST 14 + +#define TBL_ID_VIRTIO_DB_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_BHEAP_SM_INST 15 + +#define TBL_ID_VIRTIO_DB_AGING_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_AGING_SM_INST 16 + +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_INST 17 + +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_INST 18 + +#define TBL_ID_OVS_MIRROR_CAR_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_MIRROR_CAR_SM_INST 19 + +#define TBL_ID_OVS_MIRROR_VTEP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_MIRROR_VTEP_SM_INST 20 + +#define TBL_ID_VROCE_VNI_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_VROCE_VNI_MAC_SM_INST 21 + +#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_CRYPT_SPD_HASH_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SPD_HASH_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_CRYPT_SAD_HASH_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SAD_HASH_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#endif /* L2_TABLE_DEFINE_CLOUD_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_dpu.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_dpu.h new file mode 100644 index 000000000..505709c26 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_dpu.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: Header File, SML Table define for computing + * Create: 2022/01/08 + */ + +#ifndef SML_TABLE_DEFINE_COMPUTE_DPU_H +#define SML_TABLE_DEFINE_COMPUTE_DPU_H + +#include "sml_table_define_compute_standard.h" + +#endif /* L2_TABLE_DEFINE_COMPUTE_DPU_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_roce.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_roce.h new file mode 100644 index 000000000..8579b1ae5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_roce.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: SML compute_roce table macro header file + * Create: 2022/10/25 + */ +#ifndef SML_TABLE_DEFINE_COMPUTE_ROCE_H +#define SML_TABLE_DEFINE_COMPUTE_ROCE_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 6 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 10 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 11 + +#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST 12 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 13 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 14 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 15 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 12 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 14 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 15 + +#define TBL_ID_ROCE_IPQCN_DIP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_IPQCN_DIP_SM_INST 16 + +#define TBL_ID_CCF_IPQCN_SM_NODE NODE_ID_SML1 +#define TBL_ID_CCF_IPQCN_SM_INST 17 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_INST 5 + +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_INST 6 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML2 +#define TBL_ID_CTR_DFX_S32_SM_INST 4 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_PARAM_SM_INST 3 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_CTX_SM_INST 4 + +#define TBL_ID_ROCE_IP_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_HASH_SM_INST 5 + +#define TBL_ID_ROCE_QDFX_CTR_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_QDFX_CTR_SM_INST 6 + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_standard.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_standard.h new file mode 100644 index 000000000..f43ba93d6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_compute_standard.h @@ -0,0 +1,234 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2023. All rights reserved. + * Description: SML compute_standard table macro header file + * Create: 2023/8/18 + */ + +#ifndef SML_TABLE_DEFINE_COMPUTE_STANDARD_H +#define SML_TABLE_DEFINE_COMPUTE_STANDARD_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_OVS_MAC_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MAC_FILTER_SM_INST 6 + +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_INST 7 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 8 + +#define TBL_ID_OVS_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_CAR_SM_INST 9 + +#define TBL_ID_OVS_FM_PAIR_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_FM_PAIR_CTR_SM_INST 10 + +#define TBL_ID_ROCE_DCC_FUNC_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_DCC_FUNC_SM_INST 13 + +#define TBL_ID_ROCE_RTT_REQUEST_CACHE_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_RTT_REQUEST_CACHE_SM_INST 14 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 15 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 16 + +#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST 17 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 18 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 19 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 21 + +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_INST 23 + +#define TBL_ID_VIRTIO_INTR_AGING_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_AGING_SM_INST 24 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_ELB_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_OVS_SHARE_PLANE_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_SHARE_PLANE_SM_INST 11 + +#define TBL_ID_OVS_UPCALL_QUEUE_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_UPCALL_QUEUE_SM_INST 12 + +#define TBL_ID_CTR_DFX_OVS_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_OVS_S16_SM_INST 13 + +#define TBL_ID_ROCE_VFCFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_VFCFG_SM_INST 16 + +#define TBL_ID_ROCE_ONE_WINDOW_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_ONE_WINDOW_SM_INST 17 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S32_SM_INST 21 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_INST 23 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_OVS_CAPTURE_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_CAPTURE_SM_INST 4 + +#define TBL_ID_ROCE_DCC_MCODE_CTX_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DCC_MCODE_CTX_SM_INST 5 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 6 + +#define TBL_ID_ROCE_VF_PROBE_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_VF_PROBE_SM_INST 7 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 8 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 9 + +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_NODE NODE_ID_SML2 +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_INST 11 + +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_INST 12 + +#define TBL_ID_OVS_MIRROR_SESSION_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_MIRROR_SESSION_SM_INST 13 + +#define TBL_ID_OVS_VPC_INFO_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_VPC_INFO_SM_INST 14 + +#define TBL_ID_ROCE_IP_HASH_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_IP_HASH_SM_INST 15 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 + +#define TBL_ID_OVS_VM_MAPPING_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VM_MAPPING_SM_INST 3 + +#define TBL_ID_OVS_ETP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_ETP_SM_INST 4 + +#define TBL_ID_OVS_FM_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_SM_INST 5 + +#define TBL_ID_OVS_FM_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_BHEAP_SM_INST 6 + +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST 7 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_PARAM_SM_INST 10 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_CTX_SM_INST 11 + +#define TBL_ID_OVS_XTRACE_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_XTRACE_SM_INST 13 + +#define TBL_ID_MIGRATE_ADDR_SM_NODE NODE_ID_SML3 +#define TBL_ID_MIGRATE_ADDR_SM_INST 14 + +#define TBL_ID_VIRTIO_DB_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_BHEAP_SM_INST 15 + +#define TBL_ID_VIRTIO_DB_AGING_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_AGING_SM_INST 16 + +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_INST 17 + +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_INST 18 + +#define TBL_ID_OVS_MIRROR_CAR_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_MIRROR_CAR_SM_INST 19 + +#define TBL_ID_OVS_MIRROR_VTEP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_MIRROR_VTEP_SM_INST 20 + +#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_CRYPT_SPD_HASH_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SPD_HASH_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_CRYPT_SAD_HASH_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SAD_HASH_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_fpga.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_fpga.h new file mode 100644 index 000000000..c624b8f07 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_fpga.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: Header File, SML Table define for fpga + * Create: 2022/01/08 + */ + +#ifndef SML_TABLE_DEFINE_FPGA_H +#define SML_TABLE_DEFINE_FPGA_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_PORT_CFG_SM_INST 2 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_VLAN_SM_INST 3 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_MULTICAST_SM_INST 4 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 5 + +#define TBL_ID_TOE_IO_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_TOE_IO_HASH_SM_INST 6 + +#define TBL_ID_TOE_IO_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_TOE_IO_BHEAP_SM_INST 15 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 7 + +#define TBL_ID_OVS_MAC_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MAC_FILTER_SM_INST 8 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 9 + +#define TBL_ID_CTR_VSW_FUNC_MIB_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_VSW_FUNC_MIB_SM_INST 10 + +#define TBL_ID_UCODE_EXEC_INFO_SM_NODE NODE_ID_SML0 +#define TBL_ID_UCODE_EXEC_INFO_SM_INST 11 + +#define TBL_ID_DSW_VOLQ_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_VOLQ_HASH_SM_INST 12 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_MAC_SM_INST 13 + +#define TBL_ID_MAC_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_MAC_BHEAP_SM_INST 14 + +#define TBL_ID_MAC_MISC_SM_NODE NODE_ID_SML0 +#define TBL_ID_MAC_MISC_SM_INST 15 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 15 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_FUNC_CFG_SM_INST 16 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 17 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 18 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 52 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 20 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 21 + +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_INST 22 + +#define TBL_ID_OVS_VM_MAPPING_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_VM_MAPPING_SM_INST 23 + +#define TBL_ID_IOE_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_IOE_HASH_SM_INST 24 + +#define TBL_ID_ISN_VOQ_INFO_SM_NODE NODE_ID_SML0 +#define TBL_ID_ISN_VOQ_INFO_SM_INST 24 + +#define TBL_ID_ISN_VOQ_FLOW_KEY_SM_NODE NODE_ID_SML0 +#define TBL_ID_ISN_VOQ_FLOW_KEY_SM_INST 42 + +#define TBL_ID_OVS_CAPTURE_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_CAPTURE_SM_INST 50 + +#define TBL_ID_OVS_SHARE_PLANE_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_SHARE_PLANE_SM_INST 51 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 25 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 26 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 27 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 28 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 29 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_S32_SM_INST 30 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_S64_SM_INST 31 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 32 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_S16_SM_INST 56 + +#define TBL_ID_CTR_DFX_OVS_S16_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_OVS_S16_SM_INST 57 + +#define TBL_ID_OVS_UPCALL_QUEUE_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_UPCALL_QUEUE_SM_INST 34 + +#define TBL_ID_DSW_IOCB_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_IOCB_SM_INST 35 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 39 + +#define TBL_ID_MIGRATE_ADDR_SM_NODE NODE_ID_SML0 +#define TBL_ID_MIGRATE_ADDR_SM_INST 40 + +#define TBL_ID_CTR_ISN_DFX_S32_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_ISN_DFX_S32_SM_INST 41 + +#define TBL_ID_DSW_VSOCK_IOCB_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_VSOCK_IOCB_SM_INST 41 + +#define TBL_ID_OVS_ETP_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_ETP_SM_INST 42 + +#define TBL_ID_OVS_XTRACE_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_XTRACE_SM_INST 43 + +#define TBL_ID_OVS_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_CAR_SM_INST 44 + +/* TBD */ +#define TBL_ID_TOE_DLIST_SM_NODE NODE_ID_SML0 +#define TBL_ID_TOE_DLIST_SM_INST 50 + +#define TBL_ID_CRYPT_SPD_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SPD_HASH_SM_INST 19 + +#define TBL_ID_CRYPT_SAD_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SAD_HASH_SM_INST 6 + +#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST 53 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 /* for build success */ +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML1 /* for build success */ +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_MISC_RSS_HASH_SM_NODE TBL_ID_NIC_RSS_INDIRECT0_SM_NODE +#define TBL_ID_MISC_RSS_HASH_SM_INST TBL_ID_NIC_RSS_INDIRECT0_SM_INST + +#define TBL_ID_ROCE_NOFAA_HASH_0_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_NOFAA_HASH_0_SM_INST 10 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_0_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_NOFAA_SQE_LT_0_SM_INST 15 + +#define TBL_ID_ROCE_NOFAA_HASH_1_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_NOFAA_HASH_1_SM_INST 18 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_1_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_NOFAA_SQE_LT_1_SM_INST 23 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_INST 2 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_INST 2 + +#define TBL_ID_ROCE_NOFAA_HASH_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_HASH_2_SM_INST 7 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_3_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_NOFAA_SQE_LT_3_SM_INST 2 + +#define TBL_ID_ROCE_AA_MASTER_QP_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_MASTER_QP_BHEAP_SM_INST 3 + +#define TBL_ID_ROCE_AA_ACT_HOST_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_ACT_HOST_BHEAP_SM_INST 4 + +#define TBL_ID_ROCE_AA_SQE_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SQE_BHEAP_SM_INST 5 + +#define TBL_ID_ROCE_NOFAA_HASH_3_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_NOFAA_HASH_3_SM_INST 6 + +#define TBL_ID_ROCE_AA_SHARD_LT_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SHARD_LT_SM_INST 7 + +#define TBL_ID_ROCE_AA_SHARD_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SHARD_HASH_SM_INST 8 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 45 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 46 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_IP_CTX_SM_INST 47 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_PARAM_SM_INST 49 + +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_INST 54 + +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_INST 55 + +#define TBL_ID_FC_CHILD_EXTERN_TABLE_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CHILD_EXTERN_TABLE_SM_INST 3 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 14 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 15 + +#define TBL_ID_FC_AA_IO_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_AA_IO_SM_INST 32 + +#define TBL_ID_FC_HOST_ID_LT_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_HOST_ID_LT_SM_INST 33 + +#define TBL_ID_FC_CHILD_HASH_SM0_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CHILD_HASH_SM0_SM_INST 4 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 7 + +#define TBL_ID_FC_CTR_NVMe_S32_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CTR_NVMe_S32_SM_INST 34 + +#define TBL_ID_FC_CTR_NVMe_IO_S32_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CTR_NVMe_IO_S32_SM_INST 35 + +#define TBL_ID_FC_CHILD_HASH_SM1_SM_NODE NODE_ID_SML1 +#define TBL_ID_FC_CHILD_HASH_SM1_SM_INST 4 + +#define TBL_ID_FC_CHILD_HASH_SM2_SM_NODE NODE_ID_SML2 +#define TBL_ID_FC_CHILD_HASH_SM2_SM_INST 4 + +#define TBL_ID_FC_CHILD_HASH_SM3_SM_NODE NODE_ID_SML3 +#define TBL_ID_FC_CHILD_HASH_SM3_SM_INST 4 + +#define TBL_ID_OVS_FM_PAIR_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_FM_PAIR_CTR_SM_INST 63 + +#define TBL_ID_OVS_FM_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_SM_INST 63 + +#define TBL_ID_OVS_FM_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_BHEAP_SM_INST 63 + +#define TBL_ID_ROCE_IP_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_HASH_SM_INST 5 + +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_INST 15 + +#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST 12 + +#define TBL_ID_ROCE_IPQCN_DIP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_IPQCN_DIP_SM_INST 16 + +#define TBL_ID_CCF_IPQCN_SM_NODE NODE_ID_SML1 +#define TBL_ID_CCF_IPQCN_SM_INST 17 + +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_INST 23 + +#define TBL_ID_VIRTIO_INTR_AGING_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_AGING_SM_INST 24 + +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_NODE NODE_ID_SML2 +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_INST 11 + +#define TBL_ID_VIRTIO_DB_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_BHEAP_SM_INST 15 + +#define TBL_ID_VIRTIO_DB_AGING_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_AGING_SM_INST 16 + +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_INST 18 + +#define TBL_ID_OVS_MIRROR_CAR_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_MIRROR_CAR_SM_INST 19 + +#define TBL_ID_OVS_MIRROR_VTEP_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MIRROR_VTEP_SM_INST 26 + +#define TBL_ID_OVS_MIRROR_SESSION_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MIRROR_SESSION_SM_INST 27 + +#define TBL_ID_OVS_VPC_INFO_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_VPC_INFO_SM_INST 28 + +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST 7 + +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_INST 12 + +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_INST 23 + +#endif /* L2_TABLE_DEFINE_FPGA_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_llt.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_llt.h new file mode 100644 index 000000000..7935ae36c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_llt.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: Header File, SML Table define for llt + * Create: 2022/01/08 + */ + +#ifndef SML_TABLE_DEFINE_LLT_H +#define SML_TABLE_DEFINE_LLT_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_OVS_MAC_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MAC_FILTER_SM_INST 6 + +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_ETHTYPE_FILTER_SM_INST 7 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 8 + +#define TBL_ID_OVS_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_CAR_SM_INST 9 + +#define TBL_ID_OVS_FM_PAIR_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_FM_PAIR_CTR_SM_INST 10 + +#define TBL_ID_DSW_BASE_IOCB_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_BASE_IOCB_BHEAP_SM_INST 11 + +#define TBL_ID_DSW_VOLQ_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_DSW_VOLQ_BHEAP_SM_INST 12 + +#define TBL_ID_CURRENET_DCC_FUNC_SM_NODE NODE_ID_SML0 +#define TBL_ID_CURRENET_DCC_FUNC_SM_INST 13 + +#define TBL_ID_CURRENET_RTT_REQUEST_CACHE_SM_NODE NODE_ID_SML0 +#define TBL_ID_CURRENET_RTT_REQUEST_CACHE_SM_INST 14 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 15 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 15 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 16 + +#define TBL_ID_ROCE_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_BHEAP_SM_INST 17 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 18 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 19 + +#define TBL_ID_VSOCK_IOCB_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_VSOCK_IOCB_BHEAP_SM_INST 20 + +#define TBL_ID_FUSHION_QUEUE_VALID_MAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_FUSHION_QUEUE_VALID_MAP_SM_INST 22 + +#define TBL_ID_BOOT_BASE_IOCB_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOOT_BASE_IOCB_BHEAP_SM_INST 25 + +#define TBL_ID_ROCE_MIG_SAFE_GPA_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_MIG_SAFE_GPA_SM_INST 26 + +#define TBL_ID_ROCE_PCI_HOLE_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_PCI_HOLE_SM_INST 27 + +#define TBL_ID_FC_DLIST_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_DLIST_SM_INST 15 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_OVS_SHARE_PLANE_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_SHARE_PLANE_SM_INST 11 + +#define TBL_ID_OVS_UPCALL_QUEUE_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_UPCALL_QUEUE_SM_INST 12 + +#define TBL_ID_CTR_DFX_OVS_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_OVS_S16_SM_INST 13 + +#define TBL_ID_DSW_EXTEND_IOCB_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_DSW_EXTEND_IOCB_BHEAP_SM_INST 14 + +#define TBL_ID_TOE_IO_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_TOE_IO_BHEAP_SM_INST 15 + +#define TBL_ID_ROCE_VFCFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_VFCFG_SM_INST 16 + +#define TBL_ID_CURRENET_ONE_WINDOW_SM_NODE NODE_ID_SML1 +#define TBL_ID_CURRENET_ONE_WINDOW_SM_INST 17 + +#define TBL_ID_ROCE_RWLOCK_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_RWLOCK_SM_INST 18 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S32_SM_INST 21 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_ISN_VOQ_FLOW_KEY_SM_NODE NODE_ID_SML1 +#define TBL_ID_ISN_VOQ_FLOW_KEY_SM_INST 29 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_OVS_CAPTURE_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_CAPTURE_SM_INST 4 + +#define TBL_ID_CURRENET_DCC_MCODE_CTX_SM_NODE NODE_ID_SML2 +#define TBL_ID_CURRENET_DCC_MCODE_CTX_SM_INST 5 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 6 + +#define TBL_ID_CURRENET_VF_PROBE_SM_NODE NODE_ID_SML2 +#define TBL_ID_CURRENET_VF_PROBE_SM_INST 7 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 8 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 9 + +#define TBL_ID_TOE_IO_HASH_SM_NODE NODE_ID_SML2 +#define TBL_ID_TOE_IO_HASH_SM_INST 10 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_NODE_SECOND_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 + +#define TBL_ID_OVS_VM_MAPPING_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VM_MAPPING_SM_INST 3 + +#define TBL_ID_OVS_ETP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_ETP_SM_INST 4 + +#define TBL_ID_OVS_FM_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_SM_INST 5 + +#define TBL_ID_OVS_FM_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_FM_BHEAP_SM_INST 6 + +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST 7 + +#define TBL_ID_DSW_VOLQ_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_DSW_VOLQ_HASH_SM_INST 8 + +#define TBL_ID_DSW_IOCB_SM_NODE NODE_ID_SML3 +#define TBL_ID_DSW_IOCB_SM_INST 9 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_PARAM_SM_INST 10 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_CTX_SM_INST 11 + +#define TBL_ID_DSW_VSOCK_IOCB_SM_NODE NODE_ID_SML3 +#define TBL_ID_DSW_VSOCK_IOCB_SM_INST 12 + +#define TBL_ID_OVS_XTRACE_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_XTRACE_SM_INST 13 + +#define TBL_ID_PORT_CFG1_SM_NODE TBL_ID_PORT_CFG_SM_NODE +#define TBL_ID_PORT_CFG1_SM_INST TBL_ID_PORT_CFG_SM_INST + +#define TBL_ID_IOE_HASH_SM_NODE TBL_ID_TOE_IO_HASH_SM_NODE +#define TBL_ID_IOE_HASH_SM_INST TBL_ID_TOE_IO_HASH_SM_INST + +#define TBL_ID_MAC_MISC_SM_NODE TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE +#define TBL_ID_MAC_MISC_SM_INST TBL_ID_NIC_LRO_AGING_MISC1_SM_INST + +#define TBL_ID_MAC_BHEAP_SM_NODE TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE +#define TBL_ID_MAC_BHEAP_SM_INST TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST + +#define TBL_ID_MIGRATE_ADDR_SM_NODE TBL_ID_CURRENET_VF_PROBE_SM_NODE +#define TBL_ID_MIGRATE_ADDR_SM_INST TBL_ID_CURRENET_VF_PROBE_SM_INST + +#define TBL_ID_TOE_DLIST_SM_NODE TBL_ID_CURRENET_RTT_REQUEST_CACHE_SM_NODE +#define TBL_ID_TOE_DLIST_SM_INST TBL_ID_CURRENET_RTT_REQUEST_CACHE_SM_INST + +#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_CRYPT_SPD_HASH_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SPD_HASH_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_CRYPT_SAD_HASH_SM_NODE TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_NODE +#define TBL_ID_CRYPT_SAD_HASH_SM_INST TBL_ID_OVS_VPCSEC_KEY_ID_HASH_SM_INST + +#define TBL_ID_MISC_RSS_HASH_SM_NODE TBL_ID_NIC_RSS_INDIRECT0_SM_NODE +#define TBL_ID_MISC_RSS_HASH_SM_INST TBL_ID_NIC_RSS_INDIRECT0_SM_INST + +#define TBL_ID_ROCE_NOFAA_HASH_0_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_NOFAA_HASH_0_SM_INST 10 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_0_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_NOFAA_SQE_LT_0_SM_INST 15 + +#define TBL_ID_ROCE_NOFAA_HASH_1_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_NOFAA_HASH_1_SM_INST 18 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_1_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_NOFAA_SQE_LT_1_SM_INST 23 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_INST 2 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_INST 2 + +#define TBL_ID_ROCE_NOFAA_HASH_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_HASH_2_SM_INST 7 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_3_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_NOFAA_SQE_LT_3_SM_INST 2 + +#define TBL_ID_ROCE_AA_MASTER_QP_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_MASTER_QP_BHEAP_SM_INST 3 + +#define TBL_ID_ROCE_AA_ACT_HOST_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_ACT_HOST_BHEAP_SM_INST 4 + +#define TBL_ID_ROCE_AA_SQE_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SQE_BHEAP_SM_INST 5 + +#define TBL_ID_ROCE_NOFAA_HASH_3_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_NOFAA_HASH_3_SM_INST 6 + +#define TBL_ID_ROCE_AA_SHARD_LT_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SHARD_LT_SM_INST 7 + +#define TBL_ID_ROCE_AA_SHARD_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SHARD_HASH_SM_INST 8 + +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S32_SM_INST 15 + +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_INST 54 + +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_INST 55 + +#define TBL_ID_FC_CHILD_EXTERN_TABLE_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CHILD_EXTERN_TABLE_SM_INST 60 + +#define TBL_ID_FC_CHILD_HASH_SM0_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CHILD_HASH_SM0_SM_INST 61 + +#define TBL_ID_ROCE_IP_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_HASH_SM_INST 10 + +#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST 12 + +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_BHEAP_SM_INST 23 + +#define TBL_ID_VIRTIO_INTR_AGING_SM_NODE NODE_ID_SML0 +#define TBL_ID_VIRTIO_INTR_AGING_SM_INST 24 + +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_NODE NODE_ID_SML2 +#define TBL_ID_VIRTIO_DB_SUPPRESS_SM_INST 11 + +#define TBL_ID_VIRTIO_DB_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_BHEAP_SM_INST 15 + +#define TBL_ID_VIRTIO_DB_AGING_SM_NODE NODE_ID_SML3 +#define TBL_ID_VIRTIO_DB_AGING_SM_INST 16 + +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_VIRTIO_S16_SM_INST 18 + +#define TBL_ID_OVS_MIRROR_CAR_SM_NODE NODE_ID_SML3 +#define TBL_ID_OVS_MIRROR_CAR_SM_INST 19 + +#define TBL_ID_OVS_MIRROR_VTEP_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MIRROR_VTEP_SM_INST 26 + +#define TBL_ID_OVS_MIRROR_SESSION_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_MIRROR_SESSION_SM_INST 27 + +#define TBL_ID_OVS_VPC_INFO_SM_NODE NODE_ID_SML0 +#define TBL_ID_OVS_VPC_INFO_SM_INST 28 + +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_OVS_VPCSEC_BHEAP_SM_INST 12 + +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_NODE NODE_ID_SML1 +#define TBL_ID_OVS_MIRROR_CTR_PAIR_SM_INST 23 + +#define TBL_ID_FC_CHILD_HASH_SM_NODE TBL_ID_FC_CHILD_HASH_SM0_SM_NODE +#define TBL_ID_FC_CHILD_HASH_SM_INST TBL_ID_FC_CHILD_HASH_SM0_SM_INST + +#endif /* L2_TABLE_DEFINE_LLT_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_fc.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_fc.h new file mode 100644 index 000000000..3891b42aa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_fc.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: SML storage_fc table macro header file + * Create: 2022/5/12 + */ +#ifndef SML_TABLE_DEFINE_STORAGE_FC_H +#define SML_TABLE_DEFINE_STORAGE_FC_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_FC_CHILD_HASH_SM0_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_CHILD_HASH_SM0_SM_INST 12 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 18 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 19 + +#define TBL_ID_FC_DLIST_SM_NODE NODE_ID_SML0 +#define TBL_ID_FC_DLIST_SM_INST 15 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_FC_CHILD_HASH_SM1_SM_NODE NODE_ID_SML1 +#define TBL_ID_FC_CHILD_HASH_SM1_SM_INST 12 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S32_SM_INST 21 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_FC_CHILD_HASH_SM2_SM_NODE NODE_ID_SML2 +#define TBL_ID_FC_CHILD_HASH_SM2_SM_INST 12 + +#define TBL_ID_FC_CTR_NVMe_S32_SM_NODE NODE_ID_SML2 +#define TBL_ID_FC_CTR_NVMe_S32_SM_INST 34 + +#define TBL_ID_FC_CTR_NVMe_IO_S32_SM_NODE NODE_ID_SML2 +#define TBL_ID_FC_CTR_NVMe_IO_S32_SM_INST 35 + +#define TBL_ID_FC_CHILD_HASH_SM3_SM_NODE NODE_ID_SML3 +#define TBL_ID_FC_CHILD_HASH_SM3_SM_INST 12 + +#define TBL_ID_FC_AA_IO_SM_NODE NODE_ID_SML3 +#define TBL_ID_FC_AA_IO_SM_INST 10 + +#define TBL_ID_FC_HOST_ID_LT_SM_NODE NODE_ID_SML3 +#define TBL_ID_FC_HOST_ID_LT_SM_INST 11 + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_fc_adapt.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_fc_adapt.h new file mode 100644 index 000000000..e1844e684 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_fc_adapt.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: SML storage_fc table macro header file + * Create: 2022/5/12 + */ +#ifndef SML_TABLE_DEFINE_STORAGE_FC_ADAPT_H +#define SML_TABLE_DEFINE_STORAGE_FC_ADAPT_H + +#include "node_id.h" + +/* 以下宏定义FC没有使用，仅仅是为了编译通过，因为FC依赖NIC的cmdq，会编译NIC的微码 */ +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 8 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_roce.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_roce.h new file mode 100644 index 000000000..ee96c8a96 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_roce.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: SML storage_roce table macro header file + * Create: 2022/6/27 + */ +#ifndef SML_TABLE_DEFINE_STORAGE_ROCE_H +#define SML_TABLE_DEFINE_STORAGE_ROCE_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 6 + +#define TBL_ID_CRYPT_SAD_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SAD_HASH_SM_INST 8 + +#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST 9 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 10 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 11 + +#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST 12 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 13 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 14 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 15 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_CRYPT_SPD_HASH_SM_NODE NODE_ID_SML1 +#define TBL_ID_CRYPT_SPD_HASH_SM_INST 11 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 12 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 14 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 15 + +#define TBL_ID_ROCE_IPQCN_DIP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_IPQCN_DIP_SM_INST 16 + +#define TBL_ID_CCF_IPQCN_SM_NODE NODE_ID_SML1 +#define TBL_ID_CCF_IPQCN_SM_INST 17 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_CTR_DFX_OVS_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_OVS_S16_SM_INST 13 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DRC_BASE_BHEAP_SM_INST 5 + +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_DRC_QP_BHEAP_SM_INST 6 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML2 +#define TBL_ID_CTR_DFX_S32_SM_INST 4 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_PARAM_SM_INST 3 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_CTX_SM_INST 4 + +#define TBL_ID_ROCE_IP_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_HASH_SM_INST 5 + +#define TBL_ID_ROCE_QDFX_CTR_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_QDFX_CTR_SM_INST 6 + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_roceaa.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_roceaa.h new file mode 100644 index 000000000..84ca4a056 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_roceaa.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: SML storage_roceaa_4x25 table macro header file + * Create: 2022/6/27 + */ +#ifndef SML_TABLE_DEFINE_STORAGE_ROCEAA_H +#define SML_TABLE_DEFINE_STORAGE_ROCEAA_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 6 + +#define TBL_ID_ROCE_CCF_TOKEN_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_CCF_TOKEN_SM_INST 8 + +#define TBL_ID_ROCE_LOCK_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_LOCK_BHEAP_SM_INST 9 + +#define TBL_ID_ROCE_NOFAA_HASH_0_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_NOFAA_HASH_0_SM_INST 10 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 12 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 13 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 14 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_0_SM_NODE NODE_ID_SML0 +#define TBL_ID_ROCE_NOFAA_SQE_LT_0_SM_INST 15 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 3 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_ROCE_IPQCN_DIP_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_IPQCN_DIP_SM_INST 16 + +#define TBL_ID_CCF_IPQCN_SM_NODE NODE_ID_SML1 +#define TBL_ID_CCF_IPQCN_SM_INST 17 + +#define TBL_ID_ROCE_NOFAA_HASH_1_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_NOFAA_HASH_1_SM_INST 18 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S32_SM_INST 21 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_1_SM_NODE NODE_ID_SML1 +#define TBL_ID_ROCE_NOFAA_SQE_LT_1_SM_INST 23 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_SQE_LT_2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_ROCE_CCF_CTR_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_CCF_CTR_SM_INST 5 + +#define TBL_ID_ROCE_PARAM_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_PARAM_SM_INST 6 + +#define TBL_ID_ROCE_NOFAA_HASH_2_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_NOFAA_HASH_2_SM_INST 7 + +#define TBL_ID_ROCE_QDFX_CTR_SM_NODE NODE_ID_SML2 +#define TBL_ID_ROCE_QDFX_CTR_SM_INST 8 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_ROCE_NOFAA_SQE_LT_3_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_NOFAA_SQE_LT_3_SM_INST 2 + +#define TBL_ID_ROCE_AA_MASTER_QP_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_MASTER_QP_BHEAP_SM_INST 3 + +#define TBL_ID_ROCE_AA_ACT_HOST_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_ACT_HOST_BHEAP_SM_INST 4 + +#define TBL_ID_ROCE_AA_SQE_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SQE_BHEAP_SM_INST 5 + +#define TBL_ID_ROCE_NOFAA_HASH_3_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_NOFAA_HASH_3_SM_INST 6 + +#define TBL_ID_ROCE_AA_SHARD_LT_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SHARD_LT_SM_INST 7 + +#define TBL_ID_ROCE_AA_SHARD_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_AA_SHARD_HASH_SM_INST 8 + +#define TBL_ID_ROCE_IP_CTX_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_CTX_SM_INST 9 + +#define TBL_ID_ROCE_IP_HASH_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_IP_HASH_SM_INST 10 + +#define TBL_ID_ROCE_PF_PROBE_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_PF_PROBE_SM_INST 11 + +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_DIF_TX_BHEAP_SM_INST 13 + +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_NODE NODE_ID_SML3 +#define TBL_ID_ROCE_DIF_RX_BHEAP_SM_INST 14 + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_toe.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_toe.h new file mode 100644 index 000000000..665ff2cd5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_define_storage_toe.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: SML storage_toe table macro header file + * Create: 2022/3/8 + */ +#ifndef SML_TABLE_DEFINE_STORAGE_TOE_H +#define SML_TABLE_DEFINE_STORAGE_TOE_H + +#include "node_id.h" + +#define TBL_ID_GLOBAL_SM_NODE NODE_ID_SML0 +#define TBL_ID_GLOBAL_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT0_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_INDIRECT0_SM_INST 2 + +#define TBL_ID_NIC_RSS_CONTEXT_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_RSS_CONTEXT_SM_INST 3 + +#define TBL_ID_NIC_ELB_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_ELB_SM_INST 4 + +#define TBL_ID_NIC_FDIR_CFG_SM_NODE NODE_ID_SML0 +#define TBL_ID_NIC_FDIR_CFG_SM_INST 5 + +#define TBL_ID_BOND_FWD_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_FWD_SM_INST 6 + +#define TBL_ID_CRYPT_SAD_HASH_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SAD_HASH_SM_INST 8 + +#define TBL_ID_CRYPT_SAD_BHEAP_SM_NODE NODE_ID_SML0 +#define TBL_ID_CRYPT_SAD_BHEAP_SM_INST 9 + +#define TBL_ID_CAR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CAR_SM_INST 13 + +#define TBL_ID_CTR_DFX_PAIR_SM_NODE NODE_ID_SML0 +#define TBL_ID_CTR_DFX_PAIR_SM_INST 14 + +#define TBL_ID_BOND_LACPDU_SM_NODE NODE_ID_SML0 +#define TBL_ID_BOND_LACPDU_SM_INST 15 + +#define TBL_ID_PORT_CFG_SM_NODE NODE_ID_SML1 +#define TBL_ID_PORT_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_RSS_INDIRECT1_SM_INST 2 + +#define TBL_ID_NIC_VLAN_FILTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_FILTER_SM_INST 3 + +#define TBL_ID_NIC_FLEXQ_MAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_FLEXQ_MAP_SM_INST 4 + +#define TBL_ID_NIC_VLAN_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_VLAN_SM_INST 5 + +#define TBL_ID_NIC_MULTICAST_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_MULTICAST_SM_INST 6 + +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP1_SM_INST 7 + +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC1_SM_INST 8 + +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_BHEAP2_SM_INST 9 + +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_NODE NODE_ID_SML1 +#define TBL_ID_NIC_LRO_AGING_MISC2_SM_INST 10 + +#define TBL_ID_CRYPT_SPD_HASH_SM_NODE NODE_ID_SML1 +#define TBL_ID_CRYPT_SPD_HASH_SM_INST 11 + +#define TBL_ID_TOE_IO_BHEAP_SM_NODE NODE_ID_SML1 +#define TBL_ID_TOE_IO_BHEAP_SM_INST 15 + +#define TBL_ID_DFX_LOG_POINTER_SM_NODE NODE_ID_SML1 +#define TBL_ID_DFX_LOG_POINTER_SM_INST 19 + +#define TBL_ID_CTR_DFX_S64_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S64_SM_INST 20 + +#define TBL_ID_CTR_DFX_S16_SM_NODE NODE_ID_SML1 +#define TBL_ID_CTR_DFX_S16_SM_INST 22 + +#define TBL_ID_FUNC_CFG_SM_NODE NODE_ID_SML2 +#define TBL_ID_FUNC_CFG_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT2_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_RSS_INDIRECT2_SM_INST 2 + +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_NODE NODE_ID_SML2 +#define TBL_ID_NIC_GLOBAL_QUE_MAP_SM_INST 3 + +#define TBL_ID_TOE_IO_HASH_SM_NODE NODE_ID_SML2 +#define TBL_ID_TOE_IO_HASH_SM_INST 10 + +#define TBL_ID_NIC_MAC_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_MAC_SM_INST 1 + +#define TBL_ID_NIC_RSS_INDIRECT3_SM_NODE NODE_ID_SML3 +#define TBL_ID_NIC_RSS_INDIRECT3_SM_INST 2 + +#define TBL_ID_TOE_DLIST_SM_NODE NODE_ID_SML3 +#define TBL_ID_TOE_DLIST_SM_INST 15 + +#define TBL_ID_CTR_DFX_S32_SM_NODE NODE_ID_SML3 +#define TBL_ID_CTR_DFX_S32_SM_INST 21 + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/sml_table_pub.h b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_pub.h new file mode 100644 index 000000000..d1a5e32da --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/sml_table_pub.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: Header File, SML Table pub define + * Create: 2022/01/08 + */ + +#ifndef SML_TABLE_PUB_H +#define SML_TABLE_PUB_H + +#if (defined(PLATFORM_MODE_LLT) || defined(_lint)) +#include "sml_table_define_llt.h" +#else +#if defined(SML_TBL_DEFINE_CLOUD) +#include "sml_table_define_cloud.h" +#elif defined(SML_TBL_DEFINE_COMPUTE_NIC) +#include "sml_table_define_compute_standard.h" +#elif defined(SML_TBL_DEFINE_COMPUTE_DPU) +#include "sml_table_define_compute_dpu.h" +#elif defined(SML_TBL_DEFINE_COMPUTE_ROCE) +#include "sml_table_define_compute_roce.h" +#elif defined(SML_TBL_DEFINE_STORAGE_ROCE) +#include "sml_table_define_storage_roce.h" +#elif defined(SML_TBL_DEFINE_STORAGE_ROCEAA) +#include "sml_table_define_storage_roceaa.h" +#elif defined(SML_TBL_DEFINE_STORAGE_TIOE) +#include "sml_table_define_storage_toe.h" +#elif defined(SML_TBL_DEFINE_STORAGE_FC) +#include "sml_table_define_storage_fc_adapt.h" +#include "sml_table_define_storage_fc.h" +#endif +#endif + +/* rx cqe checksum err */ +#define NIC_RX_CSUM_IP_CSUM_ERR (1 << 0) +#define NIC_RX_CSUM_TCP_CSUM_ERR (1 << 1) +#define NIC_RX_CSUM_UDP_CSUM_ERR (1 << 2) +#define NIC_RX_CSUM_IGMP_CSUM_ERR (1 << 3) +#define NIC_RX_CSUM_ICMPv4_CSUM_ERR (1 << 4) +#define NIC_RX_CSUM_ICMPv6_CSUM_ERR (1 << 5) +#define NIC_RX_CSUM_SCTP_CRC_ERR (1 << 6) +#define NIC_RX_CSUM_HW_BYPASS_ERR (1 << 7) +#define NIC_RX_CSUM_IPSU_OTHER_ERR (1 << 8) + +/* ER Specification Definition */ +#define L2_ER_SPEC 8 + +/* Definition of Entry Specifications */ +#define TBL_ID_FUNC_CFG_SPEC 4096 +#define TBL_ID_PORT_CFG_SPEC 16 +#define TBL_ID_MAC_SPEC 2048 /* 2K MAC table entry */ +#define TBL_ID_VROCE_VNI_MAC_SPEC 256 +#define TBL_ID_VROCE_VNI_MAC_IDX_STEP 2 /* 32B size hash table index step is 2 */ +#define TBL_ID_MULTICAST_SPEC 2048 +#define TBL_ID_ELB_SPEC 18432 /* 18K EBL table entry */ +#define TBL_ID_FLEXQ_SPEC 8192 +#define TBL_ID_FDIR_SPEC 512 + +#define TBL_ID_IPSEC_SPD_SPEC 2048 +#define TBL_ID_IPSEC_SAD_SPEC 4096 + +/* VLAN Specification Definition */ +#define NIC_VLAN_SPEC 4096 +#define NIC_VLAN_BITNUM 12 + +/* Definition of Unicast MAC Addresses */ +#define PF_UNICAST_MAC_SPEC 2 +#define VF_UNICAST_MAC_SPEC 2 + +/* Unicast MAC address specification, fixed at 2K */ +#define GLOBLE_UNICAST_MAC_SPEC 2048 +/* Indicates the multicast MAC address specification. The value is fixed to 2K. */ +#define GLOBLE_MULTICAST_MAC_SPEC 2048 + +/* Maximum number of PFs */ +#define MAX_PF_NUM 32 + +/* Bonding use paras, update lacpdu frame to sml */ +#define LACPDU_BUSY 0x1 +#define LACPDU_IDLE 0x0 +#define LACPDU_VALID 0x1 +#define LACPDU_INVALID 0x0 +#define LACP_MAX_SIZE 128 /* LACP协议报文最大size */ +#define PER_PORT_USE_MAX_ENTRY_NUM 0x4 +#define BOND_FWDID_NOPORT 0xFFFF /* invalid Bond forward id */ + +/* + * SML Global Table Entry Divide: + * entry 0 ~ 15 common & nic + * entry 16 ~ 19 ovs + * entry 20 ~ 23 roce + * entry 24 ~ 27 toe + * entry 28 ~ 31 plog + */ +#define GLB_TBL_COM_ID0 0 +#define GLB_TBL_COM_VER_ID1 1 +#define GLB_TBL_COM_FLUSH_GPA_BASE 8 +#define GLB_TBL_COM_FLUSH_GPA_ID(host_id) (GLB_TBL_COM_FLUSH_GPA_BASE + ((host_id) & 0x7)) +#define GLB_TBL_OVS_ID16 16 +#define GLB_TBL_PPA_ID18 18 +#define GLB_TBL_ROCE_ID20 20 +#define GLB_TBL_TOE_CFG 24 +#define GLB_TBL_PLOG_NVME_ADDR_BASE 28 /* only ASIC use */ +#define GLB_TBL_PLOG_NVME_ADDR_ID(nvme_id) (GLB_TBL_PLOG_NVME_ADDR_BASE + (nvme_id)) + +/* * + * Definition of the number of elements in an entry + */ +#define TBL_ID_ELB_ENTRY_ELEM_NUM 2 +#define TBL_ID_VLAN_ENTRY_ELEM_NUM 8 +#define TBL_ID_MULTICAST_ENTRY_ELEM_NUM 4 +#define TBL_ID_TRUNKFWD_ENTRY_ELEM_NUM 32 +#define TBL_ID_TAGGEDLIST_BITMAP32_NUM 4 +#define TBL_ID_UNTAGGEDLIST_BITMAP32_NUM 4 +#define TBL_ID_GLOBAL_QUEUE_NUM 4 +#define TBL_ID_RSS_CONTEXT_NUM 4 +#define TBL_ID_RSS_HASH_NUM 4 + +#define FDIR_CFG_TABLE_PACKET_TYPE_NUM 16 + +/* * + * Maximum number of HCAR + */ +#define QOS_MAX_HCAR_NUM 12 + +/* * + * Definitions of VLAN Table, Multicast Table, and ELB Table + * Includes the indexes of Table index and sub id. + */ +#define NIC_DEFAULT_VLAN0 0 +#define INVALID_ELB_INDEX 0 + + +/* ESL/EMU/EDA supports 16ER * 4K VLAN. One entry stores eight VLANs. */ +#define GET_VLAN_TABLE_INDEX(er_id, vlan_id) ((((er_id) & 0xF) << 9) | (((vlan_id) & 0xFFF) >> 3)) + +#define GET_VLAN_ENTRY_SUBID(vlan_id) ((vlan_id) & 0x7) + +#define GET_VLAN_FLITER_INDEX(func_id, vlan_id) (((func_id) << NIC_VLAN_BITNUM) | (vlan_id)) + +#define GET_FDIR_TABLE_INDEX(func_id) (((func_id) & 0x3ff) << 4) +#define GET_FDIR_ENTRY_SUBID(packet_type) ((packet_type) & 0xf) + +#define FDIR_PKT_TYPE_EN_OFFSET 15 +#define FDIR_QID_MASK 0x1fff +#define FDIR_INVALID_QID 0xffff + +#define GET_MULTICAST_TABLE_INDEX(mc_id) ((mc_id) >> 2) +#define GET_MULTICAST_ENTRY_SUBID(mc_id) ((mc_id) & 0x3) + +#define GET_ELB_TABLE_INDEX(elb_id) ((elb_id) >> 1) +#define GET_ELB_ENTRY_SUBID(elb_id) ((elb_id) & 0x1) + +/* * + * Calculation of the Access Value Offset of taggedlist_table and untaggedlist_table + */ +#define GET_TAGLIST_TABLE_INDEX(list_id, vlan_id) (((list_id) << 5) | (((vlan_id) & 0xFFF) >> 7)) +#define GET_TAGLIST_TABLE_BITMAP_IDX(vlan_id) (((vlan_id) >> 5) & 0x3) +#define GET_TAGLIST_TABLE_VLAN_BIT(vlan_id) (0x1UL << ((vlan_id) & 0x1F)) + +#define TRUNK_FWDID_NOPORT 0xFFFF + + +/* * + * Macro definition related to OVS QOS + */ +#define CAR_TABLE_OVS_QOS_BUM_LIMIT_BASE 0 +#define CAR_TABLE_OVS_QOS_IP_FRAG_UPCALL_LIMIT_BASE 1024 +#define CAR_TABLE_OVS_QOS_UPCALL_LIMIT_BASE 1025 +#define CAR_TABLE_OVS_CAPTURE_LIMIT_BASE 1281 +#define CAR_TABLE_NIC_POLICING_BASE 1792 +#define CAR_TABLE_ROCE_CC_BASE 1920 // CAR_TABLE_NIC_POLICING_BASE + 128 + +#define OVS_QOS_BUM_LIMIT_CAR_ID(func_id) (CAR_TABLE_OVS_QOS_BUM_LIMIT_BASE + ((func_id) & 0x3ff)) +#define OVS_QOS_UPCALL_LIMIT_CAR_ID(func_id) (CAR_TABLE_OVS_QOS_UPCALL_LIMIT_BASE + ((func_id) & 0xff)) +#define OVS_CAPTURE_LIMIT_CAR_ID(index) (CAR_TABLE_OVS_CAPTURE_LIMIT_BASE + ((index) & 0x7)) +#define OVS_QOS_IP_FRAG_UPCALL_LIMIT_CAR_ID CAR_TABLE_OVS_QOS_IP_FRAG_UPCALL_LIMIT_BASE + +#define NIC_QOS_POLICING_CAR_NUM_PER_PORT 32 +#define NIC_QOS_POLICING_ICMP_CAR_NUM_PER_PORT 2 +#define NIC_CAR_ID_PER_TYPE 4 +#define NIC_CAR_ID_TYPE_MASK 0x3 + +#define NIC_QOS_POLICING_CAR_ID(port_id, index) \ + (CAR_TABLE_NIC_POLICING_BASE + (((port_id) * NIC_QOS_POLICING_CAR_NUM_PER_PORT) + (index))) + +#define NIC_QOS_POLICING_ARP_CAR_ID(port_id, index, i) \ + (CAR_TABLE_NIC_POLICING_BASE + (((port_id) * NIC_QOS_POLICING_CAR_NUM_PER_PORT) + \ + ((index) * NIC_CAR_ID_PER_TYPE) + ((i) & NIC_CAR_ID_TYPE_MASK))) + +#define OVS_SP_VLAN_NUM_PER_ITEM 16 +#define OVS_QOS_WRED_CAR_ID(index) ((index) & 0x3FF) + +/* NIC CAR */ +#define NIC_CAR_FOR_LLDP 0 +#define NIC_CAR_FOR_LACP 1 +#define NIC_CAR_FOR_ICMP 2 +#define NIC_CAR_FOR_ARP 3 + +/* * + * definition related to OVS MIRROR QOS (OVS_MIRROR_CAR_TABLE) + */ +typedef enum { + OVS_MIRROR_QOS_TYPE_BW = 0, + OVS_MIRROR_QOS_TYPE_PPS +} ovs_mirror_qos_type_e; + +#define OVS_MIRROR_CAR_TABLE_QOS_PORT_BASE 2048 +#define OVS_MIRROR_QOS_VM_CAR_ID(mirror_qos_type, vm_id) \ + ((((u32)(mirror_qos_type)) * 1024) + ((vm_id) & 0x3FF)) +#define OVS_MIRROR_QOS_PORT_CAR_ID(mirror_qos_type, index) \ + (OVS_MIRROR_CAR_TABLE_QOS_PORT_BASE + ((((u32)(mirror_qos_type)) & 0x1) << 2) + ((index) & 0x3)) + +/* set arp and icmp car parameter */ +#define ANTI_ATTACK_DEFAULT_CIR 500000 +#define ANTI_ATTACK_DEFAULT_XIR 600000 +#define ANTI_ATTACK_DEFAULT_CBS 10000000 +#define ANTI_ATTACK_DEFAULT_XBS 12000000 + +/* * + * Definition of the MAC Type + */ +typedef enum { + MAC_TYPE_UC = 0, + MAC_TYPE_BC, + MAC_TYPE_MC, + MAC_TYPE_RSV +} mac_type_e; + +/* * + * Ethernet Port Definition + */ +typedef enum { + MAG_ETH_PORT0 = 0, + MAG_ETH_PORT1, + MAG_ETH_PORT2, + MAG_ETH_PORT3, + MAG_ETH_PORT4, + MAG_ETH_PORT5, + MAG_ETH_PORT6, + MAG_ETH_PORT7, + MAG_ETH_PORT8, + MAG_ETH_PORT9 +} mag_eth_port_e; + +/* * + * Defines the VLAN filtering type. + */ +typedef enum { + NIC_VLAN_NORMAL_FILTER = 0, + NIC_VLAN_QINQ_FILTER, + NIC_VLAN_MODE_MAX +} nic_vlan_mode_e; + +/* * + * Indicates the type of the MAC table forwarding port. + */ +typedef enum { + NIC_FWD_TYPE_FUNCTION = 0, /* forward type function */ + NIC_FWD_TYPE_VMDQ, /* forward type function-queue(vmdq) */ + NIC_FWD_TYPE_PORT, /* forward type port */ + NIC_FWD_TYPE_RSVD, /* */ + NIC_FWD_TYPE_TRUNK, /* forward type trunk */ + NIC_FWD_TYPE_DP, /* forward type DP */ + NIC_FWD_TYPE_MC, /* forward type multicast */ + + /* The START: is not used and needs to be deleted. */ + NIC_FWD_TYPE_MPU, /* forward type broadcast */ + NIC_FWD_TYPE_PF, /* forward type pf */ + /* The END: is not used and needs to be deleted. */ + + NIC_FWD_TYPE_NULL /* forward type null */ +} nic_fwd_type_e; + +/* ACL key type */ +enum { + ACL_KEY_IPV4 = 0, + ACL_KEY_IPV6 +}; + +/* ACL filter action */ +enum { + ACL_ACTION_PERMIT = 0, + ACL_ACTION_DENY +}; + +/* ACL action button */ +enum { + ACL_ACTION_OFF = 0, + ACL_ACTION_ON +}; + +/* ACL statistic action */ +enum { + ACL_ACTION_NO_COUNTER = 0, + ACL_ACTION_COUNT_PKT, + ACL_ACTION_COUNT_PKT_LEN +}; + +/* ACL redirect action */ +enum { + ACL_ACTION_FORWAR_UP = 1, + ACL_ACTION_FORWAR_PORT, + ACL_ACTION_FORWAR_NEXT_HOP, + ACL_ACTION_FORWAR_OTHER +}; + +enum { + CEQ_TIMER_STOP = 0, + CEQ_TIMER_START +}; + +enum { + CEQ_API_DISPATCH = 0, + CEQ_API_NOT_DISPATCH +}; + +enum { + NO_EVENT = 0, + CEQ_MODE = 1, + INT_MODE +}; + +enum { + ER_MODE_VEB, + ER_MODE_VEPA, + ER_MODE_MULTI, + ER_MODE_NULL +}; + +#endif /* L2_TABLE_PUB_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/tile_spec.h b/drivers/infiniband/hw/hiroce3/include/hw/tile_spec.h new file mode 100644 index 000000000..7327b49e3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/tile_spec.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + * Description: tile sprc header file + * Create: 2022/5/12 + */ + +#ifndef TILE_SPEC_H +#define TILE_SPEC_H + +/* HI1823_XX is used by the driver layer, and XXX_XX is used by the logic layer. + For the logical module, use XXX_XX. */ +#define HI1823_TILE_NUM 8 +#define HI1823_STATELESS_TILE_NUM 4 +#define HI1823_STATEFUL_TILE_NUM 4 +#define HI1823_CORE_NUM_PER_TILE 24 +#define HI1823_CORE_NUM_PER_STATELESS_TILE 24 +#define HI1823_CORE_NUM_PER_STATEFUL_TILE 16 +#define HI1823_CORE_NUM_PER_QCD 4 +#define HI1823_THREAD_NUM_PER_CORE 4 +#define HI1823_TOTAL_THREAD_NUM \ + (HI1823_STATELESS_TILE_NUM * HI1823_CORE_NUM_PER_STATELESS_TILE * HI1823_THREAD_NUM_PER_CORE + \ + HI1823_STATEFUL_TILE_NUM * HI1823_CORE_NUM_PER_STATEFUL_TILE * HI1823_THREAD_NUM_PER_CORE) + +/* used for send threads init information to mpu. */ +#define MPU_BIN_CSR_ADDR 0x01804870 + + +#endif /* TILE_SPEC_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/mag/mag_mpu_cmd.h b/drivers/infiniband/hw/hiroce3/include/mag/mag_mpu_cmd.h new file mode 100644 index 000000000..475508000 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/mag/mag_mpu_cmd.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved. + * Description: serdes/mag cmd definition between driver and mpu + * Author: ETH group + * Create: 2021-07-30 + */ + +#ifndef MAG_MPU_CMD_H +#define MAG_MPU_CMD_H + +/* serdes/mag消息命令字定义 */ +enum mag_cmd { + /* serdes命令字，统一封装所有serdes命令 */ + SERDES_CMD_PROCESS = 0, /**< serdes cmd @see struct serdes_cmd_in */ + + /* mag命令字，按功能划分 */ + /* 端口配置相关 0-29 */ + MAG_CMD_SET_PORT_CFG = 1, /**< set port cfg fuction @see struct mag_cmd_set_port_cfg */ + MAG_CMD_SET_PORT_ADAPT = 2, /**< set port adapt mode @see struct mag_cmd_set_port_adapt */ + MAG_CMD_CFG_LOOPBACK_MODE = 3, /**< set port loopback mode @see struct mag_cmd_cfg_loopback_mode */ + + MAG_CMD_GET_PORT_ENABLE = 5, /**< get port enable status @see struct mag_cmd_get_port_enable */ + MAG_CMD_SET_PORT_ENABLE = 6, /**< set port enable mode @see struct mag_cmd_set_port_enable */ + MAG_CMD_GET_LINK_STATUS = 7, /**< get port link status @see struct mag_cmd_get_link_status */ + MAG_CMD_SET_LINK_FOLLOW = 8, /**< set port link_follow mode @see struct mag_cmd_set_link_follow */ + MAG_CMD_SET_PMA_ENABLE = 9, /**< set pma enable mode @see struct mag_cmd_set_pma_enable */ + MAG_CMD_CFG_FEC_MODE = 10, /**< set port fec mode @see struct mag_cmd_cfg_fec_mode */ + MAG_CMD_GET_BOND_STATUS = 11, /* reserved for future use */ + + MAG_CMD_CFG_AN_TYPE = 12, /* reserved for future use */ + MAG_CMD_CFG_LINK_TIME = 13, /**< get link time @see struct mag_cmd_get_link_time */ + + MAG_CMD_SET_PANGEA_ADAPT = 15, /**< set pangea adapt mode @see struct mag_cmd_set_pangea_adapt */ + + /* bios link配置相关 30-49 */ + MAG_CMD_CFG_BIOS_LINK_CFG = 31, /* reserved for future use */ + MAG_CMD_RESTORE_LINK_CFG = 32, /**< restore link cfg @see struct mag_cmd_restore_link_cfg */ + MAG_CMD_ACTIVATE_BIOS_LINK_CFG = 33, /**< active bios link cfg @see struct mag_cmd_activate_bios_link_cfg */ + + /* 光模块、LED、PHY等外设配置管理 50-99 */ + /* LED */ + MAG_CMD_SET_LED_CFG = 50, /**< set led cfg @see struct mag_cmd_set_led_cfg */ + + /* PHY */ + MAG_CMD_GET_PHY_INIT_STATUS = 55, /* reserved for future use */ + + /* 光模块 */ + MAG_CMD_GET_XSFP_INFO = 60, /**< get xsfp info @see struct mag_cmd_get_xsfp_info */ + MAG_CMD_SET_XSFP_ENABLE = 61, /**< set xsfp enable mode @see struct mag_cmd_set_xsfp_enable */ + MAG_CMD_GET_XSFP_PRESENT = 62, /**< get xsfp present status @see struct mag_cmd_get_xsfp_present */ + MAG_CMD_SET_XSFP_RW = 63, /**< sfp/qsfp single byte read/write, for equipment test @see struct mag_cmd_set_xsfp_rw */ + MAG_CMD_CFG_XSFP_TEMPERATURE = 64, /**< get xsfp temperature @see struct mag_cmd_sfp_temp_out_info */ + + /* 事件上报 100-149 */ + MAG_CMD_WIRE_EVENT = 100, + MAG_CMD_LINK_ERR_EVENT = 101, + + /* DFX、Counter相关 */ + MAG_CMD_EVENT_PORT_INFO = 150, /**< get port event info @see struct mag_cmd_event_port_info */ + MAG_CMD_GET_PORT_STAT = 151, /**< get port state @see struct mag_cmd_get_port_stat */ + MAG_CMD_CLR_PORT_STAT = 152, /**< clear port state @see struct mag_cmd_port_stats_info */ + MAG_CMD_GET_PORT_INFO = 153, /**< get port info @see struct mag_cmd_get_port_info */ + MAG_CMD_GET_PCS_ERR_CNT = 154, /**< pcs err count @see struct mag_cmd_event_port_info */ + MAG_CMD_GET_MAG_CNT = 155, /**< fec code count @see struct mag_cmd_get_mag_cnt */ + MAG_CMD_DUMP_ANTRAIN_INFO = 156, /**< dump anlt info @see struct mag_cmd_dump_antrain_info */ + + /* patch预留cmd */ + MAG_CMD_PATCH_RSVD_0 = 200, + MAG_CMD_PATCH_RSVD_1 = 201, + MAG_CMD_PATCH_RSVD_2 = 202, + MAG_CMD_PATCH_RSVD_3 = 203, + MAG_CMD_PATCH_RSVD_4 = 204, + + MAG_CMD_MAX = 0xFF +}; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/mag/mag_mpu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/mag/mag_mpu_cmd_defs.h new file mode 100644 index 000000000..ea49bacf0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/mag/mag_mpu_cmd_defs.h @@ -0,0 +1,928 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved. + * Description: serdes/mag cmd definition between driver and mpu + * Author: ETH group + * Create: 2023-08-30 + */ + +#ifndef MAG_MPU_CMD_DEFS_H +#define MAG_MPU_CMD_DEFS_H + +#include "mpu_cmd_base_defs.h" + +/* serdes cmd struct define */ +#define CMD_ARRAY_BUF_SIZE 64 +#define SERDES_CMD_DATA_BUF_SIZE 512 +struct serdes_in_info { + u32 chip_id : 16; + u32 macro_id : 16; + u32 start_sds_id : 16; + u32 sds_num : 16; + + u32 cmd_type : 8; /* reserved for iotype */ + u32 sub_cmd : 8; + u32 rw : 1; /* 0: read, 1: write */ + u32 rsvd : 15; + + u32 val; + union { + char field[CMD_ARRAY_BUF_SIZE]; + u32 addr; + u8 *ex_param; + }; +}; + +struct serdes_out_info { + u32 str_len; /* out_str length */ + u32 result_offset; + u32 type; /* 0:data; 1:string */ + char out_str[SERDES_CMD_DATA_BUF_SIZE]; +}; + +struct serdes_cmd_in { + struct mgmt_msg_head head; + + struct serdes_in_info serdes_in; +}; + +struct serdes_cmd_out { + struct mgmt_msg_head head; + + struct serdes_out_info serdes_out; +}; + +enum mag_cmd_port_speed { + PORT_SPEED_NOT_SET = 0, + PORT_SPEED_10MB = 1, + PORT_SPEED_100MB = 2, + PORT_SPEED_1GB = 3, + PORT_SPEED_10GB = 4, + PORT_SPEED_25GB = 5, + PORT_SPEED_40GB = 6, + PORT_SPEED_50GB = 7, + PORT_SPEED_100GB = 8, + PORT_SPEED_200GB = 9, + PORT_SPEED_UNKNOWN +}; + +enum mag_cmd_port_an { + PORT_AN_NOT_SET = 0, + PORT_CFG_AN_ON = 1, + PORT_CFG_AN_OFF = 2 +}; + +enum mag_cmd_port_adapt { + PORT_ADAPT_NOT_SET = 0, + PORT_CFG_ADAPT_ON = 1, + PORT_CFG_ADAPT_OFF = 2 +}; + +enum mag_cmd_port_sriov { + PORT_SRIOV_NOT_SET = 0, + PORT_CFG_SRIOV_ON = 1, + PORT_CFG_SRIOV_OFF = 2 +}; + +enum mag_cmd_port_fec { + PORT_FEC_NOT_SET = 0, + PORT_FEC_RSFEC = 1, + PORT_FEC_BASEFEC = 2, + PORT_FEC_NOFEC = 3, + PORT_FEC_LLRSFEC = 4, + PORT_FEC_AUTO = 5 +}; + +enum mag_cmd_port_lanes { + PORT_LANES_NOT_SET = 0, + PORT_LANES_X1 = 1, + PORT_LANES_X2 = 2, + PORT_LANES_X4 = 4, + PORT_LANES_X8 = 8 /* reserved for future use */ +}; + +enum mag_cmd_port_duplex { + PORT_DUPLEX_HALF = 0, + PORT_DUPLEX_FULL = 1 +}; + +enum mag_cmd_wire_node { + WIRE_NODE_UNDEF = 0, + CABLE_10G = 1, + FIBER_10G = 2, + CABLE_25G = 3, + FIBER_25G = 4, + CABLE_40G = 5, + FIBER_40G = 6, + CABLE_50G = 7, + FIBER_50G = 8, + CABLE_100G = 9, + FIBER_100G = 10, + CABLE_200G = 11, + FIBER_200G = 12, + WIRE_NODE_NUM +}; + +enum mag_cmd_cnt_type { + MAG_RX_RSFEC_DEC_CW_CNT = 0, + MAG_RX_RSFEC_CORR_CW_CNT = 1, + MAG_RX_RSFEC_UNCORR_CW_CNT = 2, + MAG_RX_PCS_BER_CNT = 3, + MAG_RX_PCS_ERR_BLOCK_CNT = 4, + MAG_RX_PCS_E_BLK_CNT = 5, + MAG_RX_PCS_DEC_ERR_BLK_CNT = 6, + MAG_RX_PCS_LANE_BIP_ERR_CNT = 7, + MAG_CNT_NUM +}; + +/* mag_cmd_set_port_cfg config bitmap */ +#define MAG_CMD_SET_SPEED 0x1 +#define MAG_CMD_SET_AUTONEG 0x2 +#define MAG_CMD_SET_FEC 0x4 +#define MAG_CMD_SET_LANES 0x8 +struct mag_cmd_set_port_cfg { + struct mgmt_msg_head head; + + u8 port_id; + u8 rsvd0[3]; + + u32 config_bitmap; + u8 speed; + u8 autoneg; + u8 fec; + u8 lanes; + u8 rsvd1[20]; +}; + +/* mag supported/advertised link mode bitmap */ +enum mag_cmd_link_mode { + LINK_MODE_GE = 0, + LINK_MODE_10GE_BASE_R = 1, + LINK_MODE_25GE_BASE_R = 2, + LINK_MODE_40GE_BASE_R4 = 3, + LINK_MODE_50GE_BASE_R = 4, + LINK_MODE_50GE_BASE_R2 = 5, + LINK_MODE_100GE_BASE_R = 6, + LINK_MODE_100GE_BASE_R2 = 7, + LINK_MODE_100GE_BASE_R4 = 8, + LINK_MODE_200GE_BASE_R2 = 9, + LINK_MODE_200GE_BASE_R4 = 10, + LINK_MODE_MAX_NUMBERS, + + LINK_MODE_UNKNOWN = 0xFFFF +}; + +#define LINK_MODE_GE_BIT 0x1u +#define LINK_MODE_10GE_BASE_R_BIT 0x2u +#define LINK_MODE_25GE_BASE_R_BIT 0x4u +#define LINK_MODE_40GE_BASE_R4_BIT 0x8u +#define LINK_MODE_50GE_BASE_R_BIT 0x10u +#define LINK_MODE_50GE_BASE_R2_BIT 0x20u +#define LINK_MODE_100GE_BASE_R_BIT 0x40u +#define LINK_MODE_100GE_BASE_R2_BIT 0x80u +#define LINK_MODE_100GE_BASE_R4_BIT 0x100u +#define LINK_MODE_200GE_BASE_R2_BIT 0x200u +#define LINK_MODE_200GE_BASE_R4_BIT 0x400u + +#define CABLE_10GE_BASE_R_BIT LINK_MODE_10GE_BASE_R_BIT +#define CABLE_25GE_BASE_R_BIT (LINK_MODE_25GE_BASE_R_BIT | LINK_MODE_10GE_BASE_R_BIT) +#define CABLE_40GE_BASE_R4_BIT LINK_MODE_40GE_BASE_R4_BIT +#define CABLE_50GE_BASE_R_BIT (LINK_MODE_50GE_BASE_R_BIT | LINK_MODE_25GE_BASE_R_BIT | \ + LINK_MODE_10GE_BASE_R_BIT) +#define CABLE_50GE_BASE_R2_BIT LINK_MODE_50GE_BASE_R2_BIT +#define CABLE_100GE_BASE_R2_BIT (LINK_MODE_100GE_BASE_R2_BIT | LINK_MODE_50GE_BASE_R2_BIT) +#define CABLE_100GE_BASE_R4_BIT (LINK_MODE_100GE_BASE_R4_BIT | LINK_MODE_40GE_BASE_R4_BIT) +#define CABLE_200GE_BASE_R4_BIT (LINK_MODE_200GE_BASE_R4_BIT | LINK_MODE_100GE_BASE_R4_BIT | \ + LINK_MODE_40GE_BASE_R4_BIT) + +struct mag_cmd_get_port_info { + struct mgmt_msg_head head; + + u8 port_id; + u8 rsvd0[3]; + + u8 wire_type; + u8 an_support; + u8 an_en; + u8 duplex; + + u8 speed; + u8 fec; + u8 lanes; + u8 rsvd1; + + u32 supported_mode; + u32 advertised_mode; + u8 rsvd2[8]; +}; + +#define MAG_CMD_OPCODE_GET 0 +#define MAG_CMD_OPCODE_SET 1 +struct mag_cmd_set_port_adapt { + struct mgmt_msg_head head; + + u8 port_id; + u8 opcode; /* 0:get adapt info 1:set adapt */ + u8 enable; + u8 rsvd0; + u32 speed_mode; + u32 rsvd1[3]; +}; + +#define MAG_CMD_LP_MODE_SDS_S_TX2RX 1 +#define MAG_CMD_LP_MODE_SDS_P_RX2TX 2 +#define MAG_CMD_LP_MODE_SDS_P_TX2RX 3 +#define MAG_CMD_LP_MODE_MAC_RX2TX 4 +#define MAG_CMD_LP_MODE_MAC_TX2RX 5 +#define MAG_CMD_LP_MODE_TXDP2RXDP 6 +struct mag_cmd_cfg_loopback_mode { + struct mgmt_msg_head head; + + u8 port_id; + u8 opcode; /* 0:get loopback mode 1:set loopback mode */ + u8 lp_mode; + u8 lp_en; /* 0:disable 1:enable */ + + u32 rsvd0[2]; +}; + +#define MAG_CMD_PORT_DISABLE 0x0 +#define MAG_CMD_TX_ENABLE 0x1 +#define MAG_CMD_RX_ENABLE 0x2 +/* the physical port is disable only when all pf of the port are set to down, + * if any pf is enable, the port is enable + */ +struct mag_cmd_set_port_enable { + struct mgmt_msg_head head; + + u16 function_id; /* function_id should not more than the max support pf_id(32) */ + u16 rsvd0; + + u8 state; /* bitmap bit0:tx_en bit1:rx_en */ + u8 rsvd1[3]; +}; + +struct mag_cmd_get_port_enable { + struct mgmt_msg_head head; + + u8 port; + u8 state; /* bitmap bit0:tx_en bit1:rx_en */ + u8 rsvd0[2]; +}; + +#define PMA_FOLLOW_DEFAULT 0x0 +#define PMA_FOLLOW_ENABLE 0x1 +#define PMA_FOLLOW_DISABLE 0x2 +#define PMA_FOLLOW_GET 0x4 +/* the physical port disable link follow only when all pf of the port are set to follow disable */ +struct mag_cmd_set_link_follow { + struct mgmt_msg_head head; + + u16 function_id; /* function_id should not more than the max support pf_id(32) */ + u16 rsvd0; + + u8 follow; + u8 rsvd1[3]; +}; + +/* firmware also use this cmd report link event to driver */ +struct mag_cmd_get_link_status { + struct mgmt_msg_head head; + + u8 port_id; + u8 status; /* 0:link down 1:link up */ + u8 rsvd0[2]; +}; + +/* firmware also use this cmd report bond event to driver */ +struct mag_cmd_get_bond_status { + struct mgmt_msg_head head; + + u8 status; /* 0:bond down 1:bond up */ + u8 rsvd0[3]; +}; + +struct mag_cmd_set_pma_enable { + struct mgmt_msg_head head; + + u16 function_id; /* function_id should not more than the max support pf_id(32) */ + u16 enable; +}; + +struct mag_cmd_cfg_an_type { + struct mgmt_msg_head head; + + u8 port_id; + u8 opcode; /* 0:get an type 1:set an type */ + u8 rsvd0[2]; + + u32 an_type; /* 0:ieee 1:25G/50 eth consortium */ +}; + +struct mag_cmd_get_link_time { + struct mgmt_msg_head head; + u8 port_id; + u8 rsvd0[3]; + + u32 link_up_begin; + u32 link_up_end; + u32 link_down_begin; + u32 link_down_end; +}; + +struct mag_cmd_cfg_fec_mode { + struct mgmt_msg_head head; + + u8 port_id; + u8 opcode; /* 0:get fec mode 1:set fec mode */ + u8 fec; + u8 rsvd0; +}; + +/* speed */ +#define PANGEA_ADAPT_10G_BITMAP 0xd +#define PANGEA_ADAPT_25G_BITMAP 0x72 +#define PANGEA_ADAPT_40G_BITMAP 0x680 +#define PANGEA_ADAPT_100G_BITMAP 0x1900 + +/* speed and fec */ +#define PANGEA_10G_NO_BITMAP 0x8 +#define PANGEA_10G_BASE_BITMAP 0x4 +#define PANGEA_25G_NO_BITMAP 0x10 +#define PANGEA_25G_BASE_BITMAP 0x20 +#define PANGEA_25G_RS_BITMAP 0x40 +#define PANGEA_40G_NO_BITMAP 0x400 +#define PANGEA_40G_BASE_BITMAP 0x200 +#define PANGEA_100G_NO_BITMAP 0x800 +#define PANGEA_100G_RS_BITMAP 0x1000 + +/* adapt or fec */ +#define PANGEA_ADAPT_ADAPT_BITMAP 0x183 +#define PANGEA_ADAPT_NO_BITMAP 0xc18 +#define PANGEA_ADAPT_BASE_BITMAP 0x224 +#define PANGEA_ADAPT_RS_BITMAP 0x1040 + +/* default cfg */ +#define PANGEA_ADAPT_CFG_10G_CR 0x200d +#define PANGEA_ADAPT_CFG_10G_SRLR 0xd +#define PANGEA_ADAPT_CFG_25G_CR 0x207f +#define PANGEA_ADAPT_CFG_25G_SRLR 0x72 +#define PANGEA_ADAPT_CFG_40G_CR4 0x2680 +#define PANGEA_ADAPT_CFG_40G_SRLR4 0x680 +#define PANGEA_ADAPT_CFG_100G_CR4 0x3f80 +#define PANGEA_ADAPT_CFG_100G_SRLR4 0x1900 + +typedef union { + struct { + u32 adapt_10g : 1; /* [0] adapt_10g */ + u32 adapt_25g : 1; /* [1] adapt_25g */ + u32 base_10g : 1; /* [2] base_10g */ + u32 no_10g : 1; /* [3] no_10g */ + u32 no_25g : 1; /* [4] no_25g */ + u32 base_25g : 1; /* [5] base_25g */ + u32 rs_25g : 1; /* [6] rs_25g */ + u32 adapt_40g : 1; /* [7] adapt_40g */ + u32 adapt_100g : 1; /* [8] adapt_100g */ + u32 base_40g : 1; /* [9] base_40g */ + u32 no_40g : 1; /* [10] no_40g */ + u32 no_100g : 1; /* [11] no_100g */ + u32 rs_100g : 1; /* [12] rs_100g */ + u32 auto_neg : 1; /* [13] auto_neg */ + u32 rsvd0 : 18; /* [31:14] reserved */ + } bits; + + u32 value; +} pangea_adapt_bitmap_u; + +#define PANGEA_ADAPT_GET 0x0 +#define PANGEA_ADAPT_SET 0x1 +struct mag_cmd_set_pangea_adapt { + struct mgmt_msg_head head; + + u16 port_id; + u8 opcode; /* 0:get adapt info 1:cfg adapt info */ + u8 wire_type; + + pangea_adapt_bitmap_u cfg_bitmap; + pangea_adapt_bitmap_u cur_bitmap; + u32 rsvd1[3]; +}; + +struct mag_cmd_cfg_bios_link_cfg { + struct mgmt_msg_head head; + + u8 port_id; + u8 opcode; /* 0:get bios link info 1:set bios link cfg */ + u8 clear; + u8 rsvd0; + + u32 wire_type; + u8 an_en; + u8 speed; + u8 fec; + u8 rsvd1; + u32 speed_mode; + u32 rsvd2[3]; +}; + +struct mag_cmd_restore_link_cfg { + struct mgmt_msg_head head; + + u8 port_id; + u8 rsvd[7]; +}; + +struct mag_cmd_activate_bios_link_cfg { + struct mgmt_msg_head head; + + u32 rsvd[8]; +}; + +/* led type */ +enum mag_led_type { + MAG_CMD_LED_TYPE_ALARM = 0x0, + MAG_CMD_LED_TYPE_LOW_SPEED = 0x1, + MAG_CMD_LED_TYPE_HIGH_SPEED = 0x2 +}; + +/* led mode */ +enum mag_led_mode { + MAG_CMD_LED_MODE_DEFAULT = 0x0, + MAG_CMD_LED_MODE_FORCE_ON = 0x1, + MAG_CMD_LED_MODE_FORCE_OFF = 0x2, + MAG_CMD_LED_MODE_FORCE_BLINK_1HZ = 0x3, + MAG_CMD_LED_MODE_FORCE_BLINK_2HZ = 0x4, + MAG_CMD_LED_MODE_FORCE_BLINK_4HZ = 0x5, + MAG_CMD_LED_MODE_1HZ = 0x6, + MAG_CMD_LED_MODE_2HZ = 0x7, + MAG_CMD_LED_MODE_4HZ = 0x8 +}; + +/* the led is report alarm when any pf of the port is alram */ +struct mag_cmd_set_led_cfg { + struct mgmt_msg_head head; + + u16 function_id; + u8 type; + u8 mode; +}; + +#define XSFP_INFO_MAX_SIZE 640 +/* xsfp wire type, refer to cmis protocol definition */ +enum mag_wire_type { + MAG_CMD_WIRE_TYPE_UNKNOWN = 0x0, + MAG_CMD_WIRE_TYPE_MM = 0x1, + MAG_CMD_WIRE_TYPE_SM = 0x2, + MAG_CMD_WIRE_TYPE_COPPER = 0x3, + MAG_CMD_WIRE_TYPE_ACC = 0x4, + MAG_CMD_WIRE_TYPE_BASET = 0x5, + MAG_CMD_WIRE_TYPE_AOC = 0x40, + MAG_CMD_WIRE_TYPE_ELECTRIC = 0x41, + MAG_CMD_WIRE_TYPE_BACKPLANE = 0x42 +}; + +struct mag_cmd_get_xsfp_info { + struct mgmt_msg_head head; + + u8 port_id; + u8 wire_type; + u16 out_len; + u32 rsvd; + u8 sfp_info[XSFP_INFO_MAX_SIZE]; +}; + +#define MAG_CMD_XSFP_DISABLE 0x0 +#define MAG_CMD_XSFP_ENABLE 0x1 +/* the sfp is disable only when all pf of the port are set sfp down, + * if any pf is enable, the sfp is enable + */ +struct mag_cmd_set_xsfp_enable { + struct mgmt_msg_head head; + + u32 port_id; + u32 status; /* 0:on 1:off */ +}; + +#define MAG_CMD_XSFP_PRESENT 0x0 +#define MAG_CMD_XSFP_ABSENT 0x1 +struct mag_cmd_get_xsfp_present { + struct mgmt_msg_head head; + + u8 port_id; + u8 abs_status; /* 0:present, 1:absent */ + u8 rsvd[2]; +}; + +#define MAG_CMD_XSFP_READ 0x0 +#define MAG_CMD_XSFP_WRITE 0x1 +struct mag_cmd_set_xsfp_rw { + struct mgmt_msg_head head; + + u8 port_id; + u8 operation; /* 0: read; 1: write */ + u8 value; + u8 rsvd0; + u32 devaddr; + u32 offset; + u32 rsvd1; +}; + +struct mag_cmd_cfg_xsfp_temperature { + struct mgmt_msg_head head; + + u8 opcode; /* 0:read 1:write */ + u8 rsvd0[3]; + s32 max_temp; + s32 min_temp; +}; + +struct mag_cmd_get_xsfp_temperature { + struct mgmt_msg_head head; + + s16 sfp_temp[8]; + u8 rsvd[32]; + s32 max_temp; + s32 min_temp; +}; + +/* xsfp plug event */ +struct mag_cmd_wire_event { + struct mgmt_msg_head head; + + u8 port_id; + u8 status; /* 0:present, 1:absent */ + u8 rsvd[2]; +}; + +/* link err type definition */ +#define MAG_CMD_ERR_XSFP_UNKNOWN 0x0 +struct mag_cmd_link_err_event { + struct mgmt_msg_head head; + + u8 port_id; + u8 link_err_type; + u8 rsvd[2]; +}; + +#define MAG_PARAM_TYPE_DEFAULT_CFG 0x0 +#define MAG_PARAM_TYPE_BIOS_CFG 0x1 +#define MAG_PARAM_TYPE_TOOL_CFG 0x2 +#define MAG_PARAM_TYPE_FINAL_CFG 0x3 +#define MAG_PARAM_TYPE_WIRE_INFO 0x4 +#define MAG_PARAM_TYPE_ADAPT_INFO 0x5 +#define MAG_PARAM_TYPE_MAX_CNT 0x6 +struct param_head { + u8 valid_len; + u8 info_type; + u8 rsvd[2]; +}; + +struct mag_port_link_param { + struct param_head head; + + u8 an; + u8 fec; + u8 speed; + u8 rsvd0; + + u32 used; + u32 an_fec_ability; + u32 an_speed_ability; + u32 an_pause_ability; +}; + +struct mag_port_wire_info { + struct param_head head; + + u8 status; + u8 rsvd0[3]; + + u8 wire_type; + u8 default_fec; + u8 speed; + u8 rsvd1; + u32 speed_ability; +}; + +struct mag_port_adapt_info { + struct param_head head; + + u32 adapt_en; + u32 flash_adapt; + u32 rsvd0[2]; + + u32 wire_node; + u32 an_en; + u32 speed; + u32 fec; +}; + +struct mag_port_param_info { + u8 parameter_cnt; + u8 lane_id; + u8 lane_num; + u8 rsvd0; + + struct mag_port_link_param default_cfg; + struct mag_port_link_param bios_cfg; + struct mag_port_link_param tool_cfg; + struct mag_port_link_param final_cfg; + + struct mag_port_wire_info wire_info; + struct mag_port_adapt_info adapt_info; +}; + +#define XSFP_VENDOR_NAME_LEN 16 +struct mag_cmd_event_port_info { + struct mgmt_msg_head head; + + u8 port_id; + u8 event_type; + u8 rsvd0[2]; + + // 光模块相关 + u8 vendor_name[XSFP_VENDOR_NAME_LEN]; + u32 port_type; /* fiber / copper */ + u32 port_sub_type; /* sr / lr */ + u32 cable_length; /* 1/3/5m */ + u8 cable_temp; /* 温度 */ + u8 max_speed; /* 光模块最大速率 */ + u8 sfp_type; /* sfp/qsfp */ + u8 rsvd1; + u32 power[4]; /* 光功率 */ + + u8 an_state; + u8 fec; + u16 speed; + + u8 gpio_insert; /* 0:present 1:absent */ + u8 alos; + u8 rx_los; + u8 pma_ctrl; + + u32 pma_fifo_reg; + u32 pma_signal_ok_reg; + u32 pcs_64_66b_reg; + u32 rf_lf; + u8 pcs_link; + u8 pcs_mac_link; + u8 tx_enable; + u8 rx_enable; + u32 pcs_err_cnt; + + u8 eq_data[38]; + u8 rsvd2[2]; + + u32 his_link_machine_state; + u32 cur_link_machine_state; + u8 his_machine_state_data[128]; + u8 cur_machine_state_data[128]; + u8 his_machine_state_length; + u8 cur_machine_state_length; + + struct mag_port_param_info param_info; + u8 rsvd3[360]; +}; + +struct mag_cmd_port_stats { + u64 mac_tx_fragment_pkt_num; + u64 mac_tx_undersize_pkt_num; + u64 mac_tx_undermin_pkt_num; + u64 mac_tx_64_oct_pkt_num; + u64 mac_tx_65_127_oct_pkt_num; + u64 mac_tx_128_255_oct_pkt_num; + u64 mac_tx_256_511_oct_pkt_num; + u64 mac_tx_512_1023_oct_pkt_num; + u64 mac_tx_1024_1518_oct_pkt_num; + u64 mac_tx_1519_2047_oct_pkt_num; + u64 mac_tx_2048_4095_oct_pkt_num; + u64 mac_tx_4096_8191_oct_pkt_num; + u64 mac_tx_8192_9216_oct_pkt_num; + u64 mac_tx_9217_12287_oct_pkt_num; + u64 mac_tx_12288_16383_oct_pkt_num; + u64 mac_tx_1519_max_bad_pkt_num; + u64 mac_tx_1519_max_good_pkt_num; + u64 mac_tx_oversize_pkt_num; + u64 mac_tx_jabber_pkt_num; + u64 mac_tx_bad_pkt_num; + u64 mac_tx_bad_oct_num; + u64 mac_tx_good_pkt_num; + u64 mac_tx_good_oct_num; + u64 mac_tx_total_pkt_num; + u64 mac_tx_total_oct_num; + u64 mac_tx_uni_pkt_num; + u64 mac_tx_multi_pkt_num; + u64 mac_tx_broad_pkt_num; + u64 mac_tx_pause_num; + u64 mac_tx_pfc_pkt_num; + u64 mac_tx_pfc_pri0_pkt_num; + u64 mac_tx_pfc_pri1_pkt_num; + u64 mac_tx_pfc_pri2_pkt_num; + u64 mac_tx_pfc_pri3_pkt_num; + u64 mac_tx_pfc_pri4_pkt_num; + u64 mac_tx_pfc_pri5_pkt_num; + u64 mac_tx_pfc_pri6_pkt_num; + u64 mac_tx_pfc_pri7_pkt_num; + u64 mac_tx_control_pkt_num; + u64 mac_tx_err_all_pkt_num; + u64 mac_tx_from_app_good_pkt_num; + u64 mac_tx_from_app_bad_pkt_num; + + u64 mac_rx_fragment_pkt_num; + u64 mac_rx_undersize_pkt_num; + u64 mac_rx_undermin_pkt_num; + u64 mac_rx_64_oct_pkt_num; + u64 mac_rx_65_127_oct_pkt_num; + u64 mac_rx_128_255_oct_pkt_num; + u64 mac_rx_256_511_oct_pkt_num; + u64 mac_rx_512_1023_oct_pkt_num; + u64 mac_rx_1024_1518_oct_pkt_num; + u64 mac_rx_1519_2047_oct_pkt_num; + u64 mac_rx_2048_4095_oct_pkt_num; + u64 mac_rx_4096_8191_oct_pkt_num; + u64 mac_rx_8192_9216_oct_pkt_num; + u64 mac_rx_9217_12287_oct_pkt_num; + u64 mac_rx_12288_16383_oct_pkt_num; + u64 mac_rx_1519_max_bad_pkt_num; + u64 mac_rx_1519_max_good_pkt_num; + u64 mac_rx_oversize_pkt_num; + u64 mac_rx_jabber_pkt_num; + u64 mac_rx_bad_pkt_num; + u64 mac_rx_bad_oct_num; + u64 mac_rx_good_pkt_num; + u64 mac_rx_good_oct_num; + u64 mac_rx_total_pkt_num; + u64 mac_rx_total_oct_num; + u64 mac_rx_uni_pkt_num; + u64 mac_rx_multi_pkt_num; + u64 mac_rx_broad_pkt_num; + u64 mac_rx_pause_num; + u64 mac_rx_pfc_pkt_num; + u64 mac_rx_pfc_pri0_pkt_num; + u64 mac_rx_pfc_pri1_pkt_num; + u64 mac_rx_pfc_pri2_pkt_num; + u64 mac_rx_pfc_pri3_pkt_num; + u64 mac_rx_pfc_pri4_pkt_num; + u64 mac_rx_pfc_pri5_pkt_num; + u64 mac_rx_pfc_pri6_pkt_num; + u64 mac_rx_pfc_pri7_pkt_num; + u64 mac_rx_control_pkt_num; + u64 mac_rx_sym_err_pkt_num; + u64 mac_rx_fcs_err_pkt_num; + u64 mac_rx_send_app_good_pkt_num; + u64 mac_rx_send_app_bad_pkt_num; + u64 mac_rx_unfilter_pkt_num; +}; + +struct mag_port_stats { + u64 tx_frag_pkts_port; + u64 tx_under_frame_pkts_port; + u64 tx_under_min_pkts_port; + u64 tx_64_oct_pkts_port; + u64 tx_127_oct_pkts_port; + u64 tx_255_oct_pkts_port; + u64 tx_511_oct_pkts_port; + u64 tx_1023_oct_pkts_port; + u64 tx_1518_oct_pkts_port; + u64 tx_2047_oct_pkts_port; + u64 tx_4095_oct_pkts_port; + u64 tx_8191_oct_pkts_port; + u64 tx_9216_oct_pkts_port; + u64 tx_12287_oct_pkts_port; + u64 tx_16383_oct_pkts_port; + u64 tx_1519_to_max_bad_pkts_port; + u64 tx_1519_to_max_good_pkts_port; + u64 tx_oversize_pkts_port; + u64 tx_jabber_pkts_port; + u64 tx_bad_pkts_port; + u64 tx_bad_octs_port; + u64 tx_good_pkts_port; + u64 tx_good_octs_port; + u64 tx_total_pkts_port; + u64 tx_total_octs_port; + u64 tx_unicast_pkts_port; + u64 tx_muticast_pkts_port; + u64 tx_broadcast_pkts_port; + u64 tx_pause_pkts_port; + u64 tx_pfc_pkts_port; + u64 tx_pri_0_pkts_port; + u64 tx_pri_1_pkts_port; + u64 tx_pri_2_pkts_port; + u64 tx_pri_3_pkts_port; + u64 tx_pri_4_pkts_port; + u64 tx_pri_5_pkts_port; + u64 tx_pri_6_pkts_port; + u64 tx_pri_7_pkts_port; + u64 tx_mac_control_pkts_port; + u64 tx_y1731_pkts_port; + u64 tx_1588_pkts_port; + u64 tx_error_pkts_port; + u64 tx_app_good_pkts_port; + u64 tx_app_bad_pkts_port; + u64 rx_frag_pkts_port; + u64 rx_under_frame_pkts_port; + u64 rx_under_min_pkts_port; + u64 rx_64_oct_pkts_port; + u64 rx_127_oct_pkts_port; + u64 rx_255_oct_pkts_port; + u64 rx_511_oct_pkts_port; + u64 rx_1023_oct_pkts_port; + u64 rx_1518_oct_pkts_port; + u64 rx_2047_oct_pkts_port; + u64 rx_4095_oct_pkts_port; + u64 rx_8191_oct_pkts_port; + u64 rx_9216_oct_pkts_port; + u64 rx_12287_oct_pkts_port; + u64 rx_16383_oct_pkts_port; + u64 rx_1519_to_max_bad_pkts_port; + u64 rx_1519_to_max_good_pkts_port; + u64 rx_oversize_pkts_port; + u64 rx_jabber_pkts_port; + u64 rx_bad_pkts_port; + u64 rx_bad_octs_port; + u64 rx_good_pkts_port; + u64 rx_good_octs_port; + u64 rx_total_pkts_port; + u64 rx_total_octs_port; + u64 rx_unicast_pkts_port; + u64 rx_muticast_pkts_port; + u64 rx_broadcast_pkts_port; + u64 rx_pause_pkts_port; + u64 rx_pfc_pkts_port; + u64 rx_pri_0_pkts_port; + u64 rx_pri_1_pkts_port; + u64 rx_pri_2_pkts_port; + u64 rx_pri_3_pkts_port; + u64 rx_pri_4_pkts_port; + u64 rx_pri_5_pkts_port; + u64 rx_pri_6_pkts_port; + u64 rx_pri_7_pkts_port; + u64 rx_mac_control_pkts_port; + u64 rx_y1731_pkts_port; + u64 rx_sym_err_pkts_port; + u64 rx_fcs_err_pkts_port; + u64 rx_app_good_pkts_port; + u64 rx_app_bad_pkts_port; + u64 rx_unfilter_pkts_port; +}; + +struct mag_cmd_port_stats_info { + struct mgmt_msg_head head; + + u8 port_id; + u8 rsvd0[3]; +}; + +struct mag_cmd_get_port_stat { + struct mgmt_msg_head head; + + struct mag_cmd_port_stats counter; + u64 rsvd1[15]; +}; + +struct mag_cmd_get_pcs_err_cnt { + struct mgmt_msg_head head; + + u8 port_id; + u8 rsvd0[3]; + + u32 pcs_err_cnt; +}; + +struct mag_cmd_get_mag_cnt { + struct mgmt_msg_head head; + + u8 port_id; + u8 len; + u8 rsvd0[2]; + + u32 mag_csr[128]; +}; + +struct mag_cmd_dump_antrain_info { + struct mgmt_msg_head head; + + u8 port_id; + u8 len; + u8 rsvd0[2]; + + u32 antrain_csr[256]; +}; + +#define MAG_SFP_PORT_NUM 24 +/* 芯片光模块温度结构体定义 */ +struct mag_cmd_sfp_temp_in_info { + struct mgmt_msg_head head; /* 8B */ + u8 opt_type; /* 0:read operation 1:cfg operation */ + u8 rsv[3]; + s32 max_temp; /* 芯片光模块阈值 */ + s32 min_temp; /* 芯片光模块阈值 */ +}; + +struct mag_cmd_sfp_temp_out_info { + struct mgmt_msg_head head; /* 8B */ + s16 sfp_temp_data[MAG_SFP_PORT_NUM]; /* 读出的温度 */ + s32 max_temp; /* 芯片光模块阈值 */ + s32 min_temp; /* 芯片光模块阈值 */ +}; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.c b/drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.c new file mode 100644 index 000000000..c3ddb011a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.c @@ -0,0 +1,1156 @@ +/* + * Huawei HiNIC PCI Express Linux driver + * Copyright(c) 2017 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ + +#include <linux/pci.h> +#include <linux/module.h> +#include <linux/device.h> +#include <linux/delay.h> +#include <linux/time.h> +#include <linux/timex.h> +#include <linux/rtc.h> +#include <linux/string.h> + +#include "ossl_knl.h" +#include "hinic3_hw.h" +#include "hinic3_hwdev.h" +#include "hinic3_micro_log.h" + +static bool micro_log_en; +module_param(micro_log_en, bool, 0444); +MODULE_PARM_DESC(micro_log_en, "Enable micorlog write to host - default is false"); + +static u8 log_node_id; +static u8 log_instance_id; + +char log_file_path[MAX_PATH_NAME] = "/home/microcode.log"; +char asm_file_path[MAX_PATH_NAME] = "/home/microcode.asm"; + +#define NIC_MICRO_ASM_START_ADDR 0x10000000 + +const char *micro_log_level[] = {"ERR", "WARN", "INFO", "DEBUG"}; + +const char *micro_log_mode_type[] = {"SYS", "L2NIC", "ROCE", "TOE", "IOE", + "FC", "VIRTIO", "OVS", "CRYPT", "DSW", + "PLOG", "VMIO", "MIG", "VSOCK", + "BOND", "VROCE", "USER"}; + +u8 nic_micro_log_dbg = 0; + +struct micro_log_info { + struct sdk_thread_info hinic_micro_log_task; + u64 que_addr[MICRO_LOG_VIR_PHY_ADDR][MICRO_LOG_MAX_QUEUE_NUM]; + struct nic_micro_log_statistics_info log_stati_info; + char micro_log_tmpbuf[MICRO_LOG_MAX_STRING_LEN * 8 + 1]; + u8 nic_micro_log_dbg; + u8 nic_micro_log_enable; + struct file *fp_log_file; + struct file *fp_asm_file; + char *micro_log_data_addr; + void *hwdev; + u32 all_ci; +}; + +/***************************************************************************** + Function : nic_micro_log_write_log_file + Description : �����������Ϣ������log�ļ��� + Type : + Input : u8 *buf + u8 *func_name + dfx_log_u *head_data + Output : None + Return : + Restriction : + History : + 1.Date : 2015/10/19 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +int nic_micro_log_write_log_file(struct micro_log_info *log_info, u8 *buf, u8 *func_name, dfx_log_u *head_data) +{ + struct file *fp; + u32 err = 0; + mm_segment_t old_fs; + unsigned level_num = 0; + unsigned mode_num = 0; + struct timeval txc; + struct rtc_time time; + u64 localtime; + + if (1 == nic_micro_log_dbg) { + pr_err("%s in\n", __func__); + } + + if ((NULL == buf) || (NULL == func_name) || (!head_data)) { + pr_err("%s: input buf, func_name head_data one is null.\n", __func__); + return -EFAULT; + } + if (!log_info->fp_log_file) { + pr_err("%s: fp_log_file is NULL\n", __func__); + return -EFAULT; + } + + fp = log_info->fp_log_file; + +/*lint -save -e501*/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0) + old_fs = get_fs(); + set_fs(get_ds()); +#elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + old_fs = get_fs(); + set_fs(KERNEL_DS); +#else + old_fs = force_uaccess_begin(); +#endif +/*lint -restore*/ + + level_num = head_data->log_ctrlmsg_and_data.ctrl_info.bs.type; + if (ULOG_DEBUG < level_num) { + pr_err("%s, %d: level_num(%d) err\n", + __func__, __LINE__, level_num); + level_num = ULOG_DEBUG; + } + + mode_num = head_data->log_ctrlmsg_and_data.ctrl_info.bs.feature; + if (USER_LOG_INFO < mode_num) { + pr_err("%s, %d: mode_num(%d) err\n", + __func__, __LINE__, mode_num); + mode_num = USER_LOG_INFO; + } + + /* ��ȡ��ǰ��UTCʱ�� */ + do_gettimeofday(&(txc)); + + /* ��UTCʱ�����Ϊ����ʱ�� */ + utctime_to_localtime(txc.tv_sec, &localtime); + + /* ����ʱ������. */ + localtime = TIMEZONE_ADJUSTMENT(localtime); + + /* ���ʱ���е������յ���ֵ��tm�� */ + rtc_time_to_tm(localtime, &time); + + (void)snprintf(log_info->micro_log_tmpbuf, (unsigned long)MICRO_LOG_MAX_STRING_LEN * 8, + "[%02u:%02u:%02u.%06u](tile_core_tc:%d_%d_%d)[%s, %s](%s:%d) :", + time.tm_hour, time.tm_min, time.tm_sec, (u32)txc.tv_usec % 1000000, + head_data->log_ctrlmsg_and_data.ctrl_info.bs.tile_id, + head_data->log_ctrlmsg_and_data.ctrl_info.bs.core_id, + head_data->log_ctrlmsg_and_data.ctrl_info.bs.thread_id, micro_log_level[level_num], + micro_log_mode_type[mode_num], func_name, head_data->log_ctrlmsg_and_data.line); + + err = file_write(fp, log_info->micro_log_tmpbuf, strlen(log_info->micro_log_tmpbuf)); //lint !e712 + if (err != strlen(log_info->micro_log_tmpbuf)) { + pr_err("%s: Can't write the cal data to file\n", __func__); + return -EFAULT; + } + + (void)memset(log_info->micro_log_tmpbuf, 0, sizeof(log_info->micro_log_tmpbuf)); + +/*lint -save -e668*/ + (void)snprintf(log_info->micro_log_tmpbuf, (unsigned long)MICRO_LOG_MAX_STRING_LEN * 8, (char *)buf, + head_data->log_ctrlmsg_and_data.data[0], head_data->log_ctrlmsg_and_data.data[1], + head_data->log_ctrlmsg_and_data.data[2], head_data->log_ctrlmsg_and_data.data[3], + head_data->log_ctrlmsg_and_data.data[4], head_data->log_ctrlmsg_and_data.data[5], + head_data->log_ctrlmsg_and_data.data[6], head_data->log_ctrlmsg_and_data.data[7]); +/*lint -restore*/ + err = file_write(fp, log_info->micro_log_tmpbuf, strlen(log_info->micro_log_tmpbuf)); //lint !e712 + if (err != strlen(log_info->micro_log_tmpbuf)) { + pr_err("%s: Can't write the cal data to file ERR:[0x%x]\n", __func__, err); + return -EFAULT; + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + set_fs(old_fs); +#else + force_uaccess_end(old_fs); +#endif + + if (1 == nic_micro_log_dbg) { + pr_err("%s out\n", __func__); + } + + return 0; +} +/***************************************************************************** + Function : nic_micro_log_read_asm_file + Description : ��asm�ļ� + Type : + Input : dfx_log_u *head_data + dfx_log_u *last_data + Output : None + Return : + Restriction : + History : + 1.Date : 2015/10/19 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +char *nic_micro_log_get_string_from_data(struct micro_log_info *log_info, unsigned data_addr) +{ + unsigned offset; + char * out_buf; + char * tmp_char; + + u32 i; + char err_string[] = "string has %%s\n"; + u32 err_string_len = sizeof("string has %%s\n"); + + offset = data_addr - NIC_MICRO_ASM_START_ADDR; + out_buf = (char *)(log_info->micro_log_data_addr + offset); + + tmp_char = out_buf; + for (i = 0; i < strlen((char *)out_buf); i++, tmp_char++) { + if (('%' == *tmp_char) && (('s' == *(tmp_char + 1)) || ('S' == *(tmp_char + 1)))) { + memcpy(out_buf, err_string, err_string_len); + } + } + + if (1 == nic_micro_log_dbg) { + pr_info("%s(%d): micro addr : 0x%x\n", __func__, __LINE__, data_addr); + tmp_char = out_buf; + pr_info("%s(%d)get asm data as:\n", __func__, __LINE__); + for ( i = 0; i < strlen(out_buf); i++) { + pr_info("0x%02x ", *(tmp_char + i)); + if (0 == ((i + 1) % 16)) { + pr_info("\n"); + } + } + } + + return out_buf; +} + +/***************************************************************************** + Function : nic_micro_log_read_asm_file + Description : ��asm�ļ� + Type : + Input : dfx_log_u *head_data + dfx_log_u *last_data + Output : None + Return : + Restriction : + History : + 1.Date : 2015/10/19 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +int nic_micro_log_parse_microcode_log(struct micro_log_info *log_info, dfx_log_u *head_data) +{ + int err; + + char *log_str; + char *log_file; + + if (!head_data) { + pr_err("%s(%d): input head_data is NULL!\n", __func__, __LINE__); + return -EFAULT; + } + + if (1 == nic_micro_log_dbg) { + pr_err("%s in!\n", __func__); + } + + /** �ַ�����ַ������ڵ�һ��data��ַ, ������4��������*/ + if ((NIC_MICRO_ASM_START_ADDR > head_data->log_ctrlmsg_and_data.string_addr.value) + || (NIC_MICRO_ASM_START_ADDR > head_data->log_ctrlmsg_and_data.file_name_addr)) { + pr_err("%s: string_addr[%x], func_name_addr[%x]\n", __func__, + head_data->log_ctrlmsg_and_data.string_addr.value, head_data->log_ctrlmsg_and_data.file_name_addr); + return -EFAULT; + } + + if (!log_info->micro_log_data_addr) { + pr_err("%s(%d):asm file has no data, micro_log_data_addr is NULL.\n", __func__, __LINE__); + return -EFAULT; + } + + log_str = nic_micro_log_get_string_from_data(log_info, head_data->log_ctrlmsg_and_data.string_addr.value); + log_file = nic_micro_log_get_string_from_data(log_info, head_data->log_ctrlmsg_and_data.file_name_addr); + + err = nic_micro_log_write_log_file(log_info, (u8 *)log_str, (u8 *)log_file, head_data); + if (0 != err) { + pr_err("%s, %d:write log file fail.\n", __func__, __LINE__); + return err; + } + + if (1 == nic_micro_log_dbg) { + pr_err("%s out!\n", __func__); + } + return 0; +} + +/***************************************************************************** + Function : nic_micro_log_get_asm_file_data + Description : get microcode.asm data + Type : + Input : void + Output : None + Return : + Restriction : + History : + 1.Date : 2016/3/6 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +int nic_micro_log_get_asm_file_data(struct micro_log_info *log_info) +{ + u32 i; + int read_byte; + unsigned addr; + unsigned data; + u64 datalen = 0; + mm_segment_t old_fs; + u64 file_size; + u32 file_ops = 0; + u32 all_line; + char tmpbuf[MICRO_LOG_MAX_STRING_LEN] = {0}; + + if (!log_info->fp_asm_file) { + log_info->fp_asm_file = file_open(asm_file_path); + if (IS_ERR(log_info->fp_asm_file)) { + pr_err("%s: Can't open /home/microcode.asm file\n", + __func__); + log_info->fp_asm_file = NULL; + return -EFAULT; + } + } + pr_info("%s, %d \n", __func__, __LINE__); + +/*lint -save -e501*/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0) + old_fs = get_fs(); + set_fs(get_ds()); +#elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + old_fs = get_fs(); + set_fs(KERNEL_DS); +#else + old_fs = force_uaccess_begin(); +#endif +/*lint -restore*/ + + file_size = get_file_size(log_info->fp_asm_file); + + /* asm�ļ�һ�й̶�20�ֽڣ��ļ���СΪ20���� */ + + /* asm�ļ����һ��Ϊʱ�䣬���豣���ڻ����� */ + all_line = (u32)(file_size - LINE_CHAR_NUM)/LINE_CHAR_NUM; + + /* asm�ļ���һ����Ч�ַ���Ϊ4�ֽڣ�������ڴ�ֻ��asm�ļ���1/5 */ + file_size = (file_size / LINE_CHAR_NUM) * 4; + + log_info->micro_log_data_addr = (char *)kzalloc((file_size + 1), GFP_KERNEL); + if (!log_info->micro_log_data_addr) { + pr_err("%s(%d):NIC MICRO LOG alloc reosurce fail! \n", + __FUNCTION__, __LINE__); + goto err_close_file; + } + + /*lint -save -e647*/ + set_file_position(log_info->fp_asm_file, 0 * LINE_CHAR_NUM); + /*lint -restore*/ + + /* ��ȡÿ���е�4�ֽ����� */ + for (i = 0; i < all_line; i++) { + read_byte = file_read(log_info->fp_asm_file, tmpbuf, LINE_CHAR_NUM, &file_ops); + if (read_byte < 0) { + pr_err("%s: Can't read the cal data:%d from file %d.\n", __func__, read_byte, i); + goto err_free_mem; + } + + if (read_byte < LINE_CHAR_NUM) { + pr_err("%s, %d: end file.\n", __func__, __LINE__); + break; + } + + (void)sscanf(tmpbuf, "%x : %x", &addr, &data); + + if (1 == nic_micro_log_dbg) { + pr_err("%s(%d):0x%x\r\n", __func__, __LINE__, data); + } + + (void)snprintf((char *)(log_info->micro_log_data_addr + datalen), file_size, "%c%c%c%c", + (u8)(data>>24), (u8)((data&0x00ff0000)>>16), (u8)((data&0x0000ff00)>>8), (u8)(data&0xff)); + datalen += sizeof(data); + + if (file_size < datalen) { + pr_err("%s, %d: datalen too large \n", __func__, __LINE__); + goto err_free_mem; + } + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + set_fs(old_fs); +#else + force_uaccess_end(old_fs); +#endif + + pr_info("%s, %d \n", __func__, __LINE__); + + return 0; + +err_free_mem : + + if (log_info->micro_log_data_addr) { + kfree((void *)(log_info->micro_log_data_addr)); + log_info->micro_log_data_addr = NULL; + } + +err_close_file : + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + set_fs(old_fs); +#else + force_uaccess_end(old_fs); +#endif + file_close(log_info->fp_asm_file); + log_info->fp_asm_file = NULL; + pr_err("%s(%d):close microcode.asm! \n", __FUNCTION__, __LINE__); + + pr_err("%s, %d \n", __func__, __LINE__); + return -EFAULT; +} + +/***************************************************************************** + Function : nic_micro_log_create_log_file + Description : create microlog.log file + Type : + Input : void + Output : None + Return : + Restriction : + History : + 1.Date : 2016/3/6 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +int nic_micro_log_create_log_file(struct micro_log_info *log_info) +{ + char ulog_file_time[MAX_PATH_NAME] = {0}; + struct timeval txc; + struct rtc_time time; + u64 max_time_len; + u64 path_len; + u64 localtime; + + /* ��ȡ��ǰ��UTCʱ�� */ + do_gettimeofday(&(txc)); + + /* ��UTCʱ�����Ϊ����ʱ�� */ + utctime_to_localtime(txc.tv_sec, &localtime); + + /* ���ʱ���е������յ���ֵ��tm�� */ + rtc_time_to_tm(localtime, &time); + + path_len = strlen(log_file_path) - strlen(".log"); + (void)memcpy(ulog_file_time, log_file_path, path_len); + + max_time_len = MAX_PATH_NAME - path_len; + (void)snprintf(ulog_file_time + path_len, max_time_len, + "_%s_%04d_%02d_%02d_%02d_%02d_%02d.log", + log_info->hinic_micro_log_task.name, + time.tm_year + 1900, + time.tm_mon + 1, time.tm_mday, + time.tm_hour, time.tm_min, time.tm_sec); + + if (!log_info->fp_log_file) { + log_info->fp_log_file = file_creat(ulog_file_time); + if (IS_ERR(log_info->fp_log_file)) { + pr_err("%s: Can't create %s file\n", __func__, ulog_file_time); + + return -EFAULT; + } + } + pr_info("%s: create %s file\n", __func__, ulog_file_time); + + return 0; +} + +/***************************************************************************** + Function : nic_micro_log_create_new_log_file + Description : create new microcode.log for overflow 1G + Type : + Input : void + Output : None + Return : + Restriction : + History : + 1.Date : 2016/3/6 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +int nic_micro_log_create_new_log_file(struct micro_log_info *log_info) +{ + u32 file_size; + + char ulog_file_time[MAX_PATH_NAME] = {0}; + struct timeval txc; + struct rtc_time time; + u64 max_time_len; + u64 path_len; + u64 localtime; + + if (!log_info->fp_log_file) { + pr_err("%s: fp_log_file is NULL\n", __func__); + return -EFAULT; + } + file_size = get_file_size(log_info->fp_log_file); + + if ((MAX_SIZE_OF_LOG_FILE) <= file_size) { + + if (log_info->fp_log_file) { + + file_close(log_info->fp_log_file); + log_info->fp_log_file = NULL; + } + + /* ��ȡ��ǰ��UTCʱ�� */ + do_gettimeofday(&(txc)); + + utctime_to_localtime(txc.tv_sec, &localtime); + + /* ���ʱ���е������յ���ֵ��tm�� */ + rtc_time_to_tm(localtime, &time); + + path_len = strlen(log_file_path) - strlen(".log"); + (void)memcpy(ulog_file_time, log_file_path, path_len); + + max_time_len = MAX_PATH_NAME - path_len; + (void)snprintf(ulog_file_time + path_len, max_time_len, + "_%s_%04d_%02d_%02d_%02d-%02d.log", + log_info->hinic_micro_log_task.name, + time.tm_year + 1900, + time.tm_mon + 1, time.tm_mday, + time.tm_hour, time.tm_min); + + log_info->fp_log_file = file_creat(ulog_file_time); + if (IS_ERR(log_info->fp_log_file)) { + pr_err("%s: Can't create %s file\n", __func__, ulog_file_time); + + return -EFAULT; + } + + } + + return 0; +} +int hinic3_comm_micro_log_init(struct hinic3_hwdev *hwdev) +{ + int err; + + if (!micro_log_en) + return 0; + + err = hinic3_get_sml_table_info(hwdev, TBL_ID_DFX_LOG_POINTER, + &log_node_id, &log_instance_id); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to get sml table info\n"); + return err; + } + + err = hinic3_micro_log_init(hwdev); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to initialize micro log\n"); + return err; + } + + err = hinic3_micro_log_func_en(hwdev, 1); + if (err) + sdk_warn(hwdev->dev_hdl, "Failed to enable micro log\n"); + + return 0; +} + +/***************************************************************************** + Function : hinic3_micro_log_init + Description : micro code's log init + Type : + Input : void + Output : None + Return : + Restriction : + History : + 1.Date : 2015/8/15 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +int hinic3_micro_log_init(void *hwdev) +{ + int ret = 0; + u64 v_addr = 0; + u64 p_addr = 0; + u32 i; + sml_dfx_log_tbl_s log_q_info = {0}; + struct card_node *chip_node; + struct micro_log_info *log_info; + + if (!hwdev) { + pr_err("%s(%d):handle is NULL! \n", __FUNCTION__, __LINE__); + return -EFAULT; + } + + if (hinic3_ppf_idx(hwdev) != hinic3_global_func_id(hwdev)) { + pr_info("Only PPF support micro log init! \n"); + return 0; + } + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + + log_info = chip_node->log_info; + if (log_info) { + sdk_info(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):NIC MICRO LOG has already init! \n", + __FUNCTION__, __LINE__); + return 0; + } + + log_info = kzalloc(sizeof(*log_info), GFP_KERNEL); + if (!log_info) { + sdk_info(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):alloc log info! \n", __FUNCTION__, __LINE__); + return -ENOMEM; + + } + + chip_node->log_info = log_info; + + /* ����256*64B*192 �ռ� */ + for (i = 0; i < MICRO_LOG_MAX_QUEUE_NUM; i++) { + v_addr = (u64)dma_zalloc_coherent(((struct hinic3_hwdev *)hwdev)->dev_hdl, + (unsigned long)(MICRO_LOG_MAX_QUEUE_DEPTH * MICRO_LOG_ITEM_LEN), + &p_addr, GFP_KERNEL); + if (!v_addr) { + sdk_err(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):NIC MICRO LOG alloc queue(%d) reosurce fail! \n", + __FUNCTION__, __LINE__, i); + goto err_free_mem; + } + + log_info->que_addr[MICRO_LOG_VIR_ADDR][i] = v_addr; + log_info->que_addr[MICRO_LOG_PHY_ADDR][i] = p_addr; + + /* ά�������������ϢBD */ + (void)memset((void *)&log_q_info, 0, sizeof(sml_dfx_log_tbl_s)); + + log_q_info.wr_init_pc_h32 = (u32)((p_addr >> 32) & 0xffffffff); + log_q_info.wr_init_pc_l32 = (u32)(p_addr & 0xffffffff); + + log_q_info.dw2.bs.max_num = MICRO_LOG_MAX_QUEUE_DEPTH; + log_q_info.dw2.bs.func_en = 0; + log_q_info.dw2.bs.srctag = hinic3_global_func_id(hwdev); + + if (1 == nic_micro_log_dbg) { + pr_info("%s(%d)thread %d p_addr: 0x%llx.\r\n", + __func__, __LINE__, i, p_addr); + pr_info("%s(%d)thread %d wr_init_pc_h32: 0x%08x.\r\n", + __func__, __LINE__, i, log_q_info.wr_init_pc_h32); + pr_info("%s(%d)thread %d wr_init_pc_l32: 0x%08x.\r\n", + __func__, __LINE__, i, log_q_info.wr_init_pc_l32); + pr_info("%s(%d)thread %d wr_init_dw2: 0x%08x.\r\n", + __func__, __LINE__, i, log_q_info.dw2.value); + pr_info("%s(%d)thread %d wr_init_dw3: 0x%08x.\r\n", + __func__, __LINE__, i, log_q_info.ci_index); + } + + /* ��С��ת�� */ + log_q_info.wr_init_pc_h32 = cpu_to_be32(log_q_info.wr_init_pc_h32); + log_q_info.wr_init_pc_l32 = cpu_to_be32(log_q_info.wr_init_pc_l32); + log_q_info.dw2.value = cpu_to_be32(log_q_info.dw2.value); + log_q_info.ci_index = cpu_to_be32(log_q_info.ci_index); + + /* ���¶�����Ϣ��SM�����У�����chip�ӿ� */ + ret = hinic3_dbg_lt_wr_16byte_mask(hwdev, log_node_id, + log_instance_id, i, (u8 *)&log_q_info, 0xffff); + if (ret) { + sdk_err(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):NIC MICRO LOG write table (Lt index%d)fail(%d)! \n", + __FUNCTION__, __LINE__, i, ret); + + dma_free_coherent(((struct hinic3_hwdev *)hwdev)->dev_hdl, + (unsigned long)(MICRO_LOG_MAX_QUEUE_DEPTH * MICRO_LOG_ITEM_LEN), + (void *)v_addr, p_addr); + v_addr = 0; + p_addr = 0; + log_info->que_addr[MICRO_LOG_VIR_ADDR][i] = v_addr; + log_info->que_addr[MICRO_LOG_PHY_ADDR][i] = p_addr; + goto err_free_mem; + } + + } + + memset((void *)&log_info->log_stati_info, 0, sizeof(struct nic_micro_log_statistics_info)); + + log_info->hwdev = hwdev; + + pr_warn("%s(%d):nic micro log init OK! \n", __FUNCTION__, __LINE__); + + return 0; + +err_free_mem: + if (0 == i) { + kfree(log_info); + chip_node->log_info = NULL; + return -ENOMEM; + } + /* first need i-1 */ + while (i--) { + v_addr = log_info->que_addr[MICRO_LOG_VIR_ADDR][i]; + p_addr = log_info->que_addr[MICRO_LOG_PHY_ADDR][i]; + + dma_free_coherent(((struct hinic3_hwdev *)hwdev)->dev_hdl, + (unsigned long)(MICRO_LOG_MAX_QUEUE_DEPTH * MICRO_LOG_ITEM_LEN), + (void *)v_addr, p_addr); + + v_addr = 0; + p_addr = 0; + + log_info->que_addr[MICRO_LOG_VIR_ADDR][i] = v_addr; + log_info->que_addr[MICRO_LOG_PHY_ADDR][i] = p_addr; + } + + kfree(log_info); + chip_node->log_info = NULL; + return -ENOMEM; +} + +/***************************************************************************** + Function : nic_micro_log_poll_recv + Description : poll receive micro log + Type : + Input : void + Output : None + Return : + Restriction : + History : + 1.Date : 2015/8/15 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +static void nic_micro_log_poll_recv(void *hwdev) +{ + int ret; + sml_dfx_log_tbl_s log_q_info = {0}; + struct card_node *chip_node; + struct micro_log_info *log_info; + + u32 i; + u32 lt_index; + u32 lt_offset; + + dfx_log_u *dfx_data; + dfx_log_u dfx_data_tmp; + static u32 count = 0; + u32 len= sizeof(dfx_log_u); + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + log_info = chip_node->log_info; + if (!log_info) { + pr_err("%s(%d):input param hwdev is illegal! \n", __FUNCTION__, __LINE__); + return; + } + + if (0 == log_info->nic_micro_log_enable) { + msleep(MICRO_LOG_POLLING_TIME * 1000); + return ; + } + + lt_index = (log_info->all_ci / MICRO_LOG_MAX_QUEUE_DEPTH) % MICRO_LOG_MAX_QUEUE_NUM; + lt_offset = log_info->all_ci % MICRO_LOG_MAX_QUEUE_DEPTH; + + /*lint -save -e647*/ + dfx_data = (dfx_log_u *)(log_info->que_addr[MICRO_LOG_VIR_ADDR][lt_index] + (lt_offset * MICRO_LOG_ITEM_LEN)); + /*lint -restore*/ + /*lint -save -e845 -e774*/ + memcpy(&dfx_data_tmp, dfx_data, len); + /*lint -restore*/ + /* �ȶ�ctrl��Ϣ���д�С��ת�� */ + dfx_data_tmp.log_ctrlmsg_and_data.ctrl_info.value = ntohl(dfx_data_tmp.log_ctrlmsg_and_data.ctrl_info.value); + + if ((dfx_data_tmp.log_ctrlmsg_and_data.ctrl_info.bs.CtrlFlag) ){ + do { + /* ���д�С��ת�� */ + dfx_data_tmp.log_ctrlmsg_and_data.string_addr.value = ntohl(dfx_data_tmp.log_ctrlmsg_and_data.string_addr.value); + dfx_data_tmp.log_ctrlmsg_and_data.file_name_addr = ntohl(dfx_data_tmp.log_ctrlmsg_and_data.file_name_addr); + for (i = 0; i < 8; i++) { + dfx_data_tmp.log_ctrlmsg_and_data.data[i] = ntohl(dfx_data_tmp.log_ctrlmsg_and_data.data[i]); + } + dfx_data_tmp.log_ctrlmsg_and_data.line = ntohl(dfx_data_tmp.log_ctrlmsg_and_data.line); + + if (0 == log_info->nic_micro_log_enable) { + return ; + } + + /* ������־ */ + (void)nic_micro_log_parse_microcode_log(log_info, &dfx_data_tmp); + + (void)memset((void *)dfx_data, 0, (unsigned long)MICRO_LOG_ITEM_LEN); + + log_info->all_ci++; + count++; + log_info->log_stati_info.recv_log_num++; + + if (MAX_NUM_OF_ONE_TIME_ULOG <= count) { + (void)memset((void *)&log_q_info, 0, sizeof(sml_dfx_log_tbl_s)); + /* д���е�state */ + log_q_info.dw2.bs.state = 0; + log_q_info.dw2.bs.max_num = MICRO_LOG_MAX_QUEUE_DEPTH; + log_q_info.dw2.bs.func_en = log_info->nic_micro_log_enable; + log_q_info.dw2.bs.srctag = hinic3_global_func_id(hwdev); + log_q_info.ci_index = log_info->all_ci; + /* ��С��ת�� */ + log_q_info.wr_init_pc_h32 = be32_to_cpu(log_q_info.wr_init_pc_h32); + log_q_info.wr_init_pc_l32 = be32_to_cpu(log_q_info.wr_init_pc_l32); + log_q_info.dw2.value = be32_to_cpu(log_q_info.dw2.value); + log_q_info.ci_index = be32_to_cpu(log_q_info.ci_index); + ret = hinic3_dbg_lt_wr_16byte_mask(hwdev, log_node_id, + log_instance_id, 0, (u8 *)&log_q_info, 0x8f); + if (ret) { + sdk_err(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):Write table (It index 0)fail(%d)! \n", + __FUNCTION__, __LINE__, ret); + msleep(1); + } + ret = nic_micro_log_create_new_log_file(log_info); + if (ret) { + sdk_err(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):nic_micro_log_create_new_log_file fail(%d)! \n", + __FUNCTION__, __LINE__, ret); + msleep(1); + } + count = 0; + /* change the same priority task for avoiding long time only do this task */ + msleep(0); + } + + lt_index = (log_info->all_ci / MICRO_LOG_MAX_QUEUE_DEPTH) % MICRO_LOG_MAX_QUEUE_NUM; + lt_offset = log_info->all_ci % MICRO_LOG_MAX_QUEUE_DEPTH; + /*lint -save -e647*/ + dfx_data = (dfx_log_u *)(log_info->que_addr[MICRO_LOG_VIR_ADDR][lt_index] + (lt_offset * MICRO_LOG_ITEM_LEN)); + /*lint -restore*/ + + memcpy(&dfx_data_tmp, dfx_data, len); + /**�ȶ�ctrl��Ϣ���д�С��ת��*/ + dfx_data_tmp.log_ctrlmsg_and_data.ctrl_info.value = ntohl(dfx_data_tmp.log_ctrlmsg_and_data.ctrl_info.value); + if (count && (!(count%100))) { + msleep(0); + } + }while (dfx_data_tmp.log_ctrlmsg_and_data.ctrl_info.bs.CtrlFlag); + + (void)memset((void *)&log_q_info, 0, sizeof(sml_dfx_log_tbl_s)); + log_q_info.dw2.bs.state = 0; + log_q_info.dw2.bs.max_num = MICRO_LOG_MAX_QUEUE_DEPTH; + log_q_info.dw2.bs.func_en = log_info->nic_micro_log_enable; + log_q_info.dw2.bs.srctag = hinic3_global_func_id(hwdev); + + /* д����֪CI */ + log_q_info.ci_index = log_info->all_ci; + /* ��С��ת�� */ + log_q_info.wr_init_pc_h32 = be32_to_cpu(log_q_info.wr_init_pc_h32); + log_q_info.wr_init_pc_l32 = be32_to_cpu(log_q_info.wr_init_pc_l32); + log_q_info.dw2.value = be32_to_cpu(log_q_info.dw2.value); + log_q_info.ci_index = be32_to_cpu(log_q_info.ci_index); + ret = hinic3_dbg_lt_wr_16byte_mask(hwdev, log_node_id, + log_instance_id, 0, (u8 *)&log_q_info, 0x8f); + if (ret) { + sdk_err(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):Write table (It index 0)fail(%d)! \n", + __FUNCTION__, __LINE__, ret); + return; + } + ret = nic_micro_log_create_new_log_file(log_info); + if (ret) { + sdk_err(((struct hinic3_hwdev *)hwdev)->dev_hdl, + "%s(%d):nic_micro_log_create_new_log_file fail(%d)! \n", + __FUNCTION__, __LINE__, ret); + return; + } + + count = 0; + } + + /* polling timer */ + msleep(MICRO_LOG_POLLING_TIME); + +} + +static void nic_micro_log_disable_func(void *hwdev) +{ + struct card_node *chip_node; + struct micro_log_info *log_info; + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + log_info = chip_node->log_info; + + /* ɾ��һ����ѯSM�����е��߳� */ + stop_thread(&log_info->hinic_micro_log_task); + + hinic3_micro_log_reset(hwdev); + + /* �ȴ�ѭ�������в��ڼ�¼��־������ȴ�50ms����ʱ */ + msleep(MICRO_LOG_POLLING_TIME * 50); + + if (log_info->fp_asm_file) { + file_close(log_info->fp_asm_file); + log_info->fp_asm_file = NULL; + pr_err("%s(%d):close microcode.asm! \n", __FUNCTION__, __LINE__); + } + if (log_info->micro_log_data_addr) { + kfree((void *)log_info->micro_log_data_addr); + log_info->micro_log_data_addr = NULL; + } + if (log_info->fp_log_file) { + file_close(log_info->fp_log_file); + log_info->fp_log_file = NULL; + pr_err("%s(%d):close microcode.log! \n", __FUNCTION__, __LINE__); + } +} + +int nic_micro_log_enable_func(void *hwdev) +{ + int ret; + sml_dfx_log_tbl_s log_q_info; + struct card_node *chip_node; + struct micro_log_info *log_info; + + if (!hwdev) { + pr_err("%s(%d):hwdev is NULL! \n", __FUNCTION__, __LINE__); + return -EFAULT; + } + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + log_info = chip_node->log_info; + + if (!log_info->fp_asm_file) { + ret = nic_micro_log_get_asm_file_data(log_info); + if (ret) { + pr_err("%s(%d):nic_micro_log_get_asm_file_data fail(%d)! \n", __FUNCTION__, __LINE__, ret); + log_info->nic_micro_log_enable = 0; + return ret; + } + } + + log_info->hinic_micro_log_task.name = (char*)chip_node->chip_name; + + if (!log_info->fp_log_file) { + ret = nic_micro_log_create_log_file(log_info); + if (ret) { + pr_err("%s(%d):nic_micro_log_create_new_log_file fail(%d)! \n", __FUNCTION__, __LINE__, ret); + log_info->nic_micro_log_enable = 0; + return ret; + } + } + + memset((void *)&log_q_info, 0, sizeof(sml_dfx_log_tbl_s)); + + log_q_info.dw2.bs.max_num = MICRO_LOG_MAX_QUEUE_DEPTH; + log_q_info.dw2.bs.func_en = log_info->nic_micro_log_enable; + log_q_info.dw2.bs.srctag = hinic3_global_func_id(hwdev); + log_q_info.ci_index = log_info->all_ci; + + log_q_info.dw2.value = cpu_to_be32(log_q_info.dw2.value); + log_q_info.ci_index = cpu_to_be32(log_q_info.ci_index); + + ret = hinic3_dbg_lt_wr_16byte_mask(hwdev, log_node_id, + log_instance_id, 0, (u8 *)&log_q_info, MICRO_LOG_D2_CI_MASK); + if (ret) { + pr_err("%s(%d):Write table (It index%d)fail(%d)! \n", __FUNCTION__, __LINE__, 0, ret); + return ret; + } + + log_info->hinic_micro_log_task.data = hwdev; + log_info->hinic_micro_log_task.thread_fn = nic_micro_log_poll_recv; + + ret = creat_thread(&(log_info->hinic_micro_log_task)); + if (ret) { + pr_err( "%s(%d):NIC MICRO LOG create thread fail(%d)! \n", __FUNCTION__, __LINE__, ret); + return ret; + } + + return 0; + +} + +int hinic3_micro_log_func_en(void *hwdev, u8 is_en) +{ + int ret; + struct card_node *chip_node; + struct micro_log_info *log_info; + + if (!hwdev) { + pr_err("%s(%d):handle is NULL! \n", __FUNCTION__, __LINE__); + return -EFAULT; + } + + if (1 < is_en) { + pr_err("%s(%d):is_en = %u! \n", __FUNCTION__, __LINE__, is_en); + return -EFAULT; + } + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + log_info = chip_node->log_info; + + if (!log_info) { + pr_err("%s(%d):micro log is not init! \n", __FUNCTION__, __LINE__); + return -EFAULT; + } + + if (log_info->nic_micro_log_enable == is_en) { + pr_err("%s(%d):micro log is already open or close! \n", __FUNCTION__, __LINE__); + return 0; + } + + log_info->nic_micro_log_enable = is_en; + + if (is_en) { + ret = nic_micro_log_enable_func(hwdev); + if (ret) { + pr_err("%s(%d):nic_micro_log_enable_func fail! \n", __FUNCTION__, __LINE__); + return -EFAULT; + } + } else + nic_micro_log_disable_func(hwdev); + + pr_info("micro log func is %s\n", is_en ? "enable" : "disable"); + + return 0; +} +/***************************************************************************** + Function : hinic3_micro_log_uninit + Description : nic micro code log uninit + Type : + Input : eal_handle handle + Output : None + Return : + Restriction : + History : + 1.Date : 2015/9/2 + Author : baizhijun 00284562 + Modification : Created function +*****************************************************************************/ +void hinic3_micro_log_uninit(void* hwdev) +{ + int ret; + u64 v_addr = 0; + u64 p_addr = 0; + u32 i; + sml_dfx_log_tbl_s log_q_info; + struct card_node *chip_node; + struct micro_log_info *log_info; + + if (!micro_log_en) + return; + + if (!hwdev) { + pr_err("%s(%d):handle is NULL! \n", __FUNCTION__, __LINE__); + return; + } + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + log_info = chip_node->log_info; + if (!log_info) { + pr_err("%s(%d):micro log is not init!\n", __FUNCTION__, __LINE__); + return ; + } + + if (log_info->hwdev != hwdev) + { + pr_err("%s(%d):micro log is not init in this function!\n", + __FUNCTION__, __LINE__); + return; + } + + ret = hinic3_micro_log_func_en(hwdev, 0); + if (ret) { + pr_err("%s(%d):hinic3_micro_log_func_en fail (%d)!\n", + __FUNCTION__, __LINE__, ret); + } + /* �ͷ�256*64B*192 �ռ� */ + for (i = 0; i < MICRO_LOG_MAX_QUEUE_NUM; i++) { + v_addr = log_info->que_addr[MICRO_LOG_VIR_ADDR][i]; + p_addr = log_info->que_addr[MICRO_LOG_PHY_ADDR][i]; + dma_free_coherent(((struct hinic3_hwdev *)log_info->hwdev)->dev_hdl, + (unsigned long)(MICRO_LOG_MAX_QUEUE_DEPTH * MICRO_LOG_ITEM_LEN), + (void *)v_addr, (dma_addr_t)p_addr); + log_info->que_addr[MICRO_LOG_VIR_ADDR][i] = 0; + log_info->que_addr[MICRO_LOG_PHY_ADDR][i] = 0; + + /* ά�������������ϢBD */ + (void)memset((void *)&log_q_info, 0, sizeof(sml_dfx_log_tbl_s)); + + /* ���¶�����Ϣ��SM�����У�����chip�ӿ� */ + ret = hinic3_dbg_lt_wr_16byte_mask(hwdev, log_node_id, + log_instance_id, i, (u8 *)&log_q_info, 0xffff); + if (ret) { + pr_err("%s(%d):Write table (It index%d)fail(%d)! \n", __FUNCTION__, __LINE__, i, ret); + } + + } + + kfree(log_info); + chip_node->log_info = NULL; + + return ; +} + +void hinic3_micro_log_reset(void *hwdev) +{ + int ret; + sml_dfx_log_tbl_s log_q_info; + u64 v_addr = 0; + u32 i; + struct card_node *chip_node; + struct micro_log_info *log_info; + + chip_node = (struct card_node *)(((struct hinic3_hwdev*)hwdev)->chip_node); + log_info = chip_node->log_info; + if (!log_info) { + pr_err("%s(%d):x86 micro log is not init\n", __FUNCTION__, __LINE__); + return; + } + + /* ά�������������ϢBD */ + (void)memset((void *)&log_q_info, 0, sizeof(sml_dfx_log_tbl_s)); + + log_q_info.dw2.bs.max_num = MICRO_LOG_MAX_QUEUE_DEPTH; + log_q_info.dw2.bs.func_en = log_info->nic_micro_log_enable; + log_q_info.dw2.bs.srctag = hinic3_global_func_id(hwdev); + log_q_info.ci_index = 0; + + log_q_info.dw2.value = cpu_to_be32(log_q_info.dw2.value); + log_q_info.ci_index = cpu_to_be32(log_q_info.ci_index); + + ret = hinic3_dbg_lt_wr_16byte_mask(hwdev, log_node_id, + log_instance_id, 0U, (u8 *)&log_q_info, MICRO_LOG_D2_CI_MASK); + if (ret) { + pr_err( "%s(%d):Write table (It index%d)fail(%d)! \n", + __FUNCTION__, __LINE__, 0, ret); + return ; + } + + /* ����Ϊ�ض��ķ�ʽ��ȷ��������Ч�� */ + ret = hinic3_dbg_lt_rd_16byte(hwdev, log_node_id, + log_instance_id, 0U, (u8 *)&log_q_info); + if (ret) { + pr_err("%s(%d):Read table (It index%d) fail(0x%x)! \n", + __FUNCTION__, __LINE__, 0, ret); + return ; + } + + for (i = 0; i < MICRO_LOG_MAX_QUEUE_NUM; i++) { + v_addr = log_info->que_addr[MICRO_LOG_VIR_ADDR][i]; + (void)memset((void *)v_addr, 0, (unsigned long)(MICRO_LOG_MAX_QUEUE_DEPTH * MICRO_LOG_ITEM_LEN)); + } + + log_info->all_ci = 0; + + return ; +} diff --git a/drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.h b/drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.h new file mode 100644 index 000000000..68d72089a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.h @@ -0,0 +1,169 @@ +/* + * Huawei HiNIC PCI Express Linux driver + * Copyright(c) 2017 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ + +#ifndef __NIC_MICRO_LOG_H__ +#define __NIC_MICRO_LOG_H__ + +#define MAX_PATH_NAME 256 + +#define MAX_LEN_MICRO_LOG_DATA (64*1024) + +#define MAX_NUM_OF_ONE_TIME_ULOG (16*1024) + +#define MAX_SIZE_OF_LOG_FILE (512*1024*1024) + +#define MICRO_LOG_MAX_QUEUE_NUM 256 + +#define MICRO_LOG_MAX_QUEUE_DEPTH 256 + +#define MICRO_LOG_ITEM_LEN 64 + +#define MICRO_LOG_MAX_RECV_NUM_ONE_TIME 20 + +#define MICRO_LOG_MEM_TAG MEM_TAG("MICRO_LOG_INIT") + +#define LINE_CHAR_NUM (20) + +#define MICRO_LOG_VIR_ADDR 0 + +#define MICRO_LOG_PHY_ADDR 1 + +#define MICRO_LOG_VIR_PHY_ADDR 2 + +#define MICRO_LOG_POLLING_TIME 1 + +#define MICRO_LOG_MAX_STRING_LEN (128) + +#define MICRO_LOG_Q_CI_MASK (0x000F) +#define MICRO_LOG_D2_CI_MASK (0x00FF) + +#define TBL_ID_DFX_LOG_POINTER 36 + +/* Type */ +#define ULOG_ERR 0 +#define ULOG_WARN 1 +#define ULOG_INFO 2 +#define ULOG_DEBUG 3 + +/* Feature */ +#define SYS_LOG_INFO 0 +#define L2NIC_LOG_INFO 1 +#define ROCE_LOG_INFO 2 +#define TOE_LOG_INFO 3 +#define IOE_LOG_INFO 4 +#define FC_LOG_INFO 5 +#define VIRTIO_LOG_INFO 6 +#define OVS_LOG_INFO 7 +#define CRYPT_LOG_INFO 8 +#define DSW_LOG_INFO 9 +#define PLOG_LOG_INFO 0xa +#define VMIO_LOG_INFO 0xb +#define MIG_LOG_INFO 0xc +#define VSOCK_LOG_INFO 0xd +#define BOND_LOG_INFO 0xe +#define USER_LOG_INFO 0xf /*printf*/ + +typedef union tag_dfx_log +{ + struct + { + union + { + struct + { +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned action :1; /* 1:��¼��־ 0:��ӡ */ + unsigned type :2; /* 0:err 1:trace 2:info */ + unsigned feature :5; /* 0:l2nic 1:roce 2:toe 3:ioe 4:feoe */ + unsigned core_id :6; + unsigned thread_id :2; + unsigned valid_param_num :8; /* ��Ч�IJ������� */ + unsigned tile_id :3; + unsigned CtrlFlag :1; + unsigned rsv :4; +#else + unsigned rsv :4; + unsigned CtrlFlag :1; + unsigned tile_id :3; + unsigned valid_param_num :8; /* ��Ч�IJ������� */ + unsigned thread_id :2; + unsigned core_id :6; + unsigned feature :5; /* 0:l2nic 1:roce 2:toe 3:ioe 4:feoe */ + unsigned type :2; /* 0:err 1:trace 2:info */ + unsigned action :1; /* 1:��¼��־ 0:��ӡ */ +#endif + }bs; + + unsigned value; + }ctrl_info; + + union + { + unsigned value; + }string_addr; + + unsigned data[8]; + + unsigned file_name_addr; /* �ļ���������26���ַ� */ + unsigned line; /* ��ӡλ�� */ + //char rsvd[2]; /* �ļ���������26���ַ� */ + }log_ctrlmsg_and_data; +}dfx_log_u; + +typedef struct tag_sml_dfx_log_tbl { + u32 wr_init_pc_h32; /* Initial value of write_pc */ + u32 wr_init_pc_l32; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 state : 8; + u32 func_en : 1; + u32 srctag : 12; + u32 max_num : 11; /* Maximum data block size */ +#else + u32 max_num : 11; /* Maximum data block size */ + u32 srctag : 12; + u32 func_en : 1; + u32 state : 8; +#endif + } bs; + u32 value; + } dw2; + + u32 ci_index; +} sml_dfx_log_tbl_s; + +struct nic_micro_log_statistics_info +{ + u32 recv_log_num; +}; + +int hinic3_comm_micro_log_init(struct hinic3_hwdev *hwdev); + +int hinic3_micro_log_func_en(void *hwdev, u8 is_en); + +int hinic3_micro_log_init(void * hwdev); + +void hinic3_micro_log_uninit(void * hwdev); + +void hinic3_micro_log_reset(void *hwdev); + +#define BEIJING_TIMEZONE 8 +#define SECONDS_OF_HOUR 3600 +#define TIMEZONE_ADJUSTMENT(unix_time) \ + (unix_time + (BEIJING_TIMEZONE * SECONDS_OF_HOUR)) + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/nic/nic_cfg_comm.h b/drivers/infiniband/hw/hiroce3/include/nic/nic_cfg_comm.h new file mode 100644 index 000000000..0ff3e4a78 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/nic/nic_cfg_comm.h @@ -0,0 +1,62 @@ +/* + * Copyright (C), 2001-2021, Huawei Tech. Co., Ltd. + * File Name : nic_cfg_comm.h + * Version : Initial Draft + * Description : nic config common header file + * Function List : + * History : + * Modification: Created file + */ + +#ifndef NIC_CFG_COMM_H +#define NIC_CFG_COMM_H + +/* rss */ +#define HINIC3_RSS_TYPE_VALID_SHIFT 23 +#define HINIC3_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24 +#define HINIC3_RSS_TYPE_IPV6_EXT_SHIFT 25 +#define HINIC3_RSS_TYPE_TCP_IPV6_SHIFT 26 +#define HINIC3_RSS_TYPE_IPV6_SHIFT 27 +#define HINIC3_RSS_TYPE_TCP_IPV4_SHIFT 28 +#define HINIC3_RSS_TYPE_IPV4_SHIFT 29 +#define HINIC3_RSS_TYPE_UDP_IPV6_SHIFT 30 +#define HINIC3_RSS_TYPE_UDP_IPV4_SHIFT 31 + +#define HINIC3_RSS_TYPE_SET(val, member) (((u32)(val) & 0x1) << HINIC3_RSS_TYPE_##member##_SHIFT) +#define HINIC3_RSS_TYPE_GET(val, member) (((u32)(val) >> HINIC3_RSS_TYPE_##member##_SHIFT) & 0x1) + +enum nic_rss_hash_type { + NIC_RSS_HASH_TYPE_XOR = 0, + NIC_RSS_HASH_TYPE_TOEP, + + NIC_RSS_HASH_TYPE_MAX /* MUST BE THE LAST ONE */ +}; + +#define NIC_RSS_INDIR_SIZE 256 +#define NIC_RSS_KEY_SIZE 40 + +/* * + * Definition of the NIC receiving mode + */ +#define NIC_RX_MODE_UC 0x01 +#define NIC_RX_MODE_MC 0x02 +#define NIC_RX_MODE_BC 0x04 +#define NIC_RX_MODE_MC_ALL 0x08 +#define NIC_RX_MODE_PROMISC 0x10 + +/* IEEE 802.1Qaz std */ +#define NIC_DCB_COS_MAX 0x8 +#define NIC_DCB_UP_MAX 0x8 +#define NIC_DCB_TC_MAX 0x8 +#define NIC_DCB_PG_MAX 0x8 +#define NIC_DCB_TSA_SP 0x0 +#define NIC_DCB_TSA_CBS 0x1 /* hi1822 do NOT support */ +#define NIC_DCB_TSA_ETS 0x2 +#define NIC_DCB_DSCP_NUM 0x8 +#define NIC_DCB_IP_PRI_MAX 0x40 + +#define NIC_DCB_PRIO_DWRR 0x0 +#define NIC_DCB_PRIO_STRICT 0x1 + +#define NIC_DCB_MAX_PFC_NUM 0x4 +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd.h b/drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd.h new file mode 100644 index 000000000..4dd471190 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd.h @@ -0,0 +1,147 @@ +/* + * Copyright (C), 2001-2011, Huawei Tech. Co., Ltd. + * File Name : nic_mpu_cmd.h + * Version : Initial Draft + * Created : 2019/4/25 + * Last Modified : + * Description : NIC Commands between Driver and MPU + * Function List : + */ + +#ifndef NIC_MPU_CMD_H +#define NIC_MPU_CMD_H + +/** Commands between NIC to MPU + */ +enum hinic3_nic_cmd { + HINIC3_NIC_CMD_VF_REGISTER = 0, /**< Only for PFD and VFD @see > hinic3_cmd_register_vf */ + + /** FUNC CFG */ + HINIC3_NIC_CMD_SET_FUNC_TBL = 5, /**< Set function table @see > hinic3_cmd_set_func_tbl */ + HINIC3_NIC_CMD_SET_VPORT_ENABLE, /**< Enable a vport @see > hinic3_vport_state */ + HINIC3_NIC_CMD_SET_RX_MODE, /**< Set nic rx mode. @see > hinic3_rx_mode_config */ + HINIC3_NIC_CMD_SQ_CI_ATTR_SET, /**< Set SQ CI attr @see > hinic3_cmd_cons_idx_attr */ + HINIC3_NIC_CMD_GET_VPORT_STAT, /**< Get vport stat @see > hinic3_port_stats_info, < hinic3_cmd_vport_stats */ + HINIC3_NIC_CMD_CLEAN_VPORT_STAT, /**< Clean vport stat @see > hinic3_cmd_clear_vport_stats */ + HINIC3_NIC_CMD_CLEAR_QP_RESOURCE, /**< Clean queue pair resource @see > hinic3_cmd_clear_qp_resource */ + HINIC3_NIC_CMD_CFG_FLEX_QUEUE, /**< Set flex queue @see > hinic3_cmd_cfg_qps */ + /** LRO CFG */ + HINIC3_NIC_CMD_CFG_RX_LRO, /**< Set rx LRO @see > hinic3_cmd_lro_config */ + HINIC3_NIC_CMD_CFG_LRO_TIMER, /**< Set LRO timer @see > hinic3_cmd_lro_timer */ + HINIC3_NIC_CMD_FEATURE_NEGO, /**< negotiate features @see > hinic3_cmd_feature_nego */ + HINIC3_NIC_CMD_CFG_LOCAL_LRO_STATE, /**< Configure local LRO state @see > hinic3_cmd_local_lro_state */ + + HINIC3_NIC_CMD_CACHE_OUT_QP_RES, /**< Cache out queue pair resource @see > hinic3_cmd_cache_out_qp_resource */ + + /** MAC & VLAN CFG */ + HINIC3_NIC_CMD_GET_MAC = 20, /**< Get mac address @see > hinic3_port_mac_set */ + HINIC3_NIC_CMD_SET_MAC, /**< Set mac address @see > hinic3_port_mac_set */ + HINIC3_NIC_CMD_DEL_MAC, /**< Delete mac address @see > hinic3_port_mac_set */ + HINIC3_NIC_CMD_UPDATE_MAC, /**< Update mac address @see > hinic3_port_mac_update */ + HINIC3_NIC_CMD_GET_ALL_DEFAULT_MAC, /**< Get all defualt mac address @see > cmd_mac_info_get_s */ + + HINIC3_NIC_CMD_CFG_FUNC_VLAN, /**< Configure function vlan @see > hinic3_cmd_vlan_config */ + HINIC3_NIC_CMD_SET_VLAN_FILTER_EN, /**< Enable vlan filter @see > hinic3_cmd_set_vlan_filter */ + HINIC3_NIC_CMD_SET_RX_VLAN_OFFLOAD, /**< Set rx vlan offload @see > hinic3_cmd_vlan_offload */ + HINIC3_NIC_CMD_SMAC_CHECK_STATE, + + /** SR-IOV */ + HINIC3_NIC_CMD_CFG_VF_VLAN = 40, /**< Configure vf vlan @see > hinic3_cmd_vf_vlan_config */ + HINIC3_NIC_CMD_SET_SPOOPCHK_STATE, /**< Set snoopchk state @see > hinic3_cmd_spoofchk_set */ + /* RATE LIMIT */ + HINIC3_NIC_CMD_SET_MAX_MIN_RATE, /**< Set rate limit @see > HINIC3_NIC_CMD_SET_MAX_MIN_RATE */ + + /** RSS CFG */ + HINIC3_NIC_CMD_RSS_CFG = 60, /**< Set rss config @see > hinic3_cmd_rss_config */ + HINIC3_NIC_CMD_RSS_TEMP_MGR, /**< TODO: delete after implement nego cmd */ + HINIC3_NIC_CMD_GET_RSS_CTX_TBL, /**< TODO: delete: move to ucode cmd */ + HINIC3_NIC_CMD_CFG_RSS_HASH_KEY, /**< Set rss hash key @see > hinic3_cmd_rss_hash_key */ + HINIC3_NIC_CMD_CFG_RSS_HASH_ENGINE, /**< Set rss hash engine type @see > hinic3_cmd_rss_engine_type */ + HINIC3_NIC_CMD_SET_RSS_CTX_TBL_INTO_FUNC, /**< Set rss context table info @see > hinic3_rss_context_table */ + /** IP checksum error packets, enable rss quadruple hash */ + HINIC3_NIC_CMD_IPCS_ERR_RSS_ENABLE_OP = 66, /**< Set rss config @see > hinic3_ipcs_err_rss_enable_operation_s */ + + /** PPA/FDIR */ + HINIC3_NIC_CMD_ADD_TC_FLOW = 80, /**< Add tc flow @see > nic_cmd_fdir_add_rule */ + HINIC3_NIC_CMD_DEL_TC_FLOW, /**< Delete tc flow @see > nic_cmd_fdir_del_rules */ + HINIC3_NIC_CMD_GET_TC_FLOW, /**< Get tc flow @see > nic_cmd_fdir_get_rule */ + HINIC3_NIC_CMD_FLUSH_TCAM, /**< Flush TCAM @see > nic_cmd_flush_tcam_rules */ + HINIC3_NIC_CMD_CFG_TCAM_BLOCK, /**< Configure TCAM block @see > nic_cmd_ctrl_tcam_block_out */ + HINIC3_NIC_CMD_ENABLE_TCAM, /**< Enable TCAM @see > nic_cmd_set_tcam_enable */ + HINIC3_NIC_CMD_GET_TCAM_BLOCK, /**< Get TCAM block @see > nic_cmd_dfx_fdir_tcam_block_table */ + HINIC3_NIC_CMD_CFG_PPA_TABLE_ID, /**< Configure PPA table id @see > hinic3_ppa_cfg_table_id_cmd */ + HINIC3_NIC_CMD_SET_PPA_EN = 88, /**< Set PPA enable @see > hinic3_ppa_cfg_ppa_en_cmd */ + HINIC3_NIC_CMD_CFG_PPA_MODE, /**< Configure PPA mode @see > hinic3_ppa_cfg_mode_cmd */ + HINIC3_NIC_CMD_CFG_PPA_FLUSH, /**< Configure PPA flush @see > hinic3_ppa_cfg_flush_cmd */ + HINIC3_NIC_CMD_SET_FDIR_STATUS, /**< Set FDIR status @see > hinic3_set_fdir_ethertype_rule */ + HINIC3_NIC_CMD_GET_PPA_COUNTER, /**< Get PPA counter @see > hinic3_ppa_fdir_query_cmd */ + HINIC3_NIC_CMD_SET_FUNC_FLOW_BIFUR_ENABLE, /**< Set flow bifur status @see > cmd_flow_bifur_func_handle */ + HINIC3_NIC_CMD_SET_BOND_MASK, /**< Set flow bifur bond @see > cmd_flow_bifur_bond_handle */ + HINIC3_NIC_CMD_GET_BLOCK_TC_FLOWS, /**< Get func tcam table @see > get_fdir_func_tcam_table */ + HINIC3_NIC_CMD_GET_BOND_MASK, /**< Get flow bifur bond @see > cmd_flow_bifur_bond_handle */ + + /** PORT CFG */ + HINIC3_NIC_CMD_SET_PORT_ENABLE = 100, /**< set port enable @see > hinic3_port_state */ + HINIC3_NIC_CMD_CFG_PAUSE_INFO, /**< Configure pause info @see > hinic3_cmd_pause_config */ + + HINIC3_NIC_CMD_SET_PORT_CAR, /**< Set port Car @see > hinic3_cmd_set_port_car */ + HINIC3_NIC_CMD_SET_ER_DROP_PKT, /**< Unused */ + + HINIC3_NIC_CMD_VF_COS, /**< Get vf CoS @see > hinic3_cmd_vf_dcb_state */ + HINIC3_NIC_CMD_SETUP_COS_MAPPING, /**< Unused */ + HINIC3_NIC_CMD_SET_ETS, /**< Unused */ + HINIC3_NIC_CMD_SET_PFC, /**< Unused */ + HINIC3_NIC_CMD_QOS_ETS, /**< Set QoS ETS @see > hinic3_cmd_ets_cfg */ + HINIC3_NIC_CMD_QOS_PFC, /**< Set QoS PFC @see > hinic3_cmd_set_pfc */ + HINIC3_NIC_CMD_QOS_DCB_STATE, /**< Get QoS DCB state @see > hinic3_cmd_set_dcb_state */ + HINIC3_NIC_CMD_QOS_PORT_CFG, /**< Get QoS port cfg @see > hinic3_cmd_qos_port_cfg */ + HINIC3_NIC_CMD_QOS_MAP_CFG, /**< Get QoS map cfg @see > hinic3_cmd_qos_map_cfg */ + HINIC3_NIC_CMD_FORCE_PKT_DROP, /**< Force pkt drop @see > hinic3_force_pkt_drop */ + HINIC3_NIC_CMD_CFG_TX_PROMISC_SKIP = 114, /**< Configure nic tx promisc skip @see > hinic3_tx_promisc_cfg */ + HINIC3_NIC_CMD_SET_PORT_FLOW_BIFUR_ENABLE = 117, /**< Set flow bifur port switch @see > cmd_flow_bifur_port_handle */ + HINIC3_NIC_CMD_TX_PAUSE_EXCP_NOTICE = 118, /**< Set tx pause exc notice @see > nic_cmd_tx_pause_notice */ + HINIC3_NIC_CMD_INQUIRT_PAUSE_CFG = 119, /**< Inquirt pause cfg @see > nic_cmd_pause_inquiry_cfg_s */ + + /** MISC */ + HINIC3_NIC_CMD_BIOS_CFG = 120, /**< Set QoS ETS @see > nic_cmd_bios_cfg */ + HINIC3_NIC_CMD_SET_FIRMWARE_CUSTOM_PACKETS_MSG, /**< Set QoS ETS @see > fault_msg_st */ + + /** BOND */ + HINIC3_NIC_CMD_BOND_DEV_CREATE = 134, /**< Create bond device @see > hinic3_cmd_create_bond */ + HINIC3_NIC_CMD_BOND_DEV_DELETE, /**< Delete bond device @see > hinic3_cmd_delete_bond */ + HINIC3_NIC_CMD_BOND_DEV_OPEN_CLOSE, /**< Open/close bond dev @see > hinic3_cmd_open_close_bond */ + HINIC3_NIC_CMD_BOND_INFO_GET, /**< Set QoS ETS @see > hinic3_bond_status_info */ + HINIC3_NIC_CMD_BOND_ACTIVE_INFO_GET, /**< Get bond active info @see > hinic3_bond_active_report_info */ + HINIC3_NIC_CMD_BOND_ACTIVE_NOTICE, /**< Bond active notice report @see > nic_cmd_bond_active_report_info */ + + /** DFX */ + HINIC3_NIC_CMD_GET_SM_TABLE = 140, /**< Get sm table @see > nic_cmd_dfx_sm_table */ + HINIC3_NIC_CMD_RD_LINE_TBL, /**< Set RD line table @see > nic_mpu_lt_opera, < nic_mpu_lt_opera */ + + HINIC3_NIC_CMD_SET_UCAPTURE_OPT = 160, /**< TODO: move to roce */ + HINIC3_NIC_CMD_SET_VHD_CFG, /**< Set VHD configuration @see > hinic3_set_vhd_mode */ + + /** TODO: move to HILINK */ + HINIC3_NIC_CMD_GET_PORT_STAT = 200, /**< Get port stat @see > hinic3_port_stats_info, < hinic3_port_stats */ + HINIC3_NIC_CMD_CLEAN_PORT_STAT, /**< Unused */ + HINIC3_NIC_CMD_CFG_LOOPBACK_MODE, /**< Unused */ + HINIC3_NIC_CMD_GET_SFP_QSFP_INFO, /**< Unused */ + HINIC3_NIC_CMD_SET_SFP_STATUS, /**< Unused */ + HINIC3_NIC_CMD_GET_LIGHT_MODULE_ABS, /**< Unused */ + HINIC3_NIC_CMD_GET_LINK_INFO, /**< Unused */ + HINIC3_NIC_CMD_CFG_AN_TYPE, /**< Unused */ + HINIC3_NIC_CMD_GET_PORT_INFO, /**< Get port info @see > hinic3_cmd_port_info */ + HINIC3_NIC_CMD_SET_LINK_SETTINGS, /**< Unused */ + HINIC3_NIC_CMD_ACTIVATE_BIOS_LINK_CFG, /**< Unused */ + HINIC3_NIC_CMD_RESTORE_LINK_CFG, /**< Unused */ + HINIC3_NIC_CMD_SET_LINK_FOLLOW, /**< Unused */ + HINIC3_NIC_CMD_GET_LINK_STATE, /**< Unused */ + HINIC3_NIC_CMD_LINK_STATUS_REPORT, /**< Unused */ + HINIC3_NIC_CMD_CABLE_PLUG_EVENT, /**< Unused */ + HINIC3_NIC_CMD_LINK_ERR_EVENT, /**< Unused */ + HINIC3_NIC_CMD_SET_LED_STATUS, /**< Unused */ + + HINIC3_NIC_CMD_MAX = 256, +}; + +#endif /* NIC_MPU_CMD_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd_defs.h new file mode 100644 index 000000000..8a43d0324 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd_defs.h @@ -0,0 +1,1317 @@ +/* + * Copyright (C), 2001-2011, Huawei Tech. Co., Ltd. + * File Name : nic_mpu_cmd_defs.h + * Version : Initial Draft + * Created : 2019/4/25 + * Last Modified : + * Description : NIC Commands Structure definition between Driver and MPU + * Function List : + */ + +#ifndef NIC_MPU_CMD_DEFS_H +#define NIC_MPU_CMD_DEFS_H + +#include "nic_cfg_comm.h" +#include "mpu_cmd_base_defs.h" + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +#define HINIC3_CMD_OP_SET 1 +#define HINIC3_CMD_OP_GET 0 + +#define HINIC3_CMD_OP_ADD 1 +#define HINIC3_CMD_OP_DEL 0 + +#define NIC_TCAM_BLOCK_LARGE_NUM 256 +#define NIC_TCAM_BLOCK_LARGE_SIZE 16 + +#define NIC_TCAM_FLOW_BIFUR_FLAG (1 << 0) + +#ifndef BIT +#define BIT(n) (1UL << (n)) +#endif + +enum nic_feature_cap { + NIC_F_CSUM = BIT(0), + NIC_F_SCTP_CRC = BIT(1), + NIC_F_TSO = BIT(2), + NIC_F_LRO = BIT(3), + NIC_F_UFO = BIT(4), + NIC_F_RSS = BIT(5), + NIC_F_RX_VLAN_FILTER = BIT(6), + NIC_F_RX_VLAN_STRIP = BIT(7), + NIC_F_TX_VLAN_INSERT = BIT(8), + NIC_F_VXLAN_OFFLOAD = BIT(9), + NIC_F_IPSEC_OFFLOAD = BIT(10), + NIC_F_FDIR = BIT(11), + NIC_F_PROMISC = BIT(12), + NIC_F_ALLMULTI = BIT(13), + NIC_F_XSFP_REPORT = BIT(14), + NIC_F_VF_MAC = BIT(15), + NIC_F_RATE_LIMIT = BIT(16), + NIC_F_RXQ_RECOVERY = BIT(17), +}; + +#define NIC_F_ALL_MASK 0x3FFFF /* 使能所有属性 */ + +struct hinic3_mgmt_msg_head { + u8 status; + u8 version; + u8 rsvd0[6]; +}; + +#define NIC_MAX_FEATURE_QWORD 4 +struct hinic3_cmd_feature_nego { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; /* 1: set, 0: get */ + u8 rsvd; + u64 s_feature[NIC_MAX_FEATURE_QWORD]; +}; + +struct hinic3_port_mac_set { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 vlan_id; + u16 rsvd1; + u8 mac[ETH_ALEN]; +}; + +struct hinic3_port_mac_update { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 vlan_id; + u16 rsvd1; + u8 old_mac[ETH_ALEN]; + u16 rsvd2; + u8 new_mac[ETH_ALEN]; +}; + +struct hinic3_vport_state { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; + u8 state; /* 0--disable, 1--enable */ + u8 rsvd2[3]; +}; + +struct hinic3_port_state { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; + u8 state; /* 0--disable, 1--enable */ + u8 rsvd2[3]; +}; + +#define HINIC3_SET_PORT_CAR_PROFILE 0 +#define HINIC3_SET_PORT_CAR_STATE 1 + +struct hinic3_port_car_info { + u32 cir; /* unit: kbps, range:[1,400*1000*1000], i.e. 1Kbps~400Gbps(400M*kbps) */ + u32 xir; /* unit: kbps, range:[1,400*1000*1000], i.e. 1Kbps~400Gbps(400M*kbps) */ + u32 cbs; /* unit: Byte, range:[1,320*1000*1000], i.e. 1byte~2560Mbit */ + u32 xbs; /* unit: Byte, range:[1,320*1000*1000], i.e. 1byte~2560Mbit */ +}; + +struct hinic3_cmd_set_port_car { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 opcode; /* 0--set car profile, 1--set car state */ + u8 state; /* 0--disable, 1--enable */ + u8 rsvd; + + struct hinic3_port_car_info car; +}; + +struct hinic3_cmd_clear_qp_resource { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; +}; + +struct hinic3_cmd_cache_out_qp_resource { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; +}; + +struct hinic3_port_stats_info { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; +}; + +struct hinic3_vport_stats { + u64 tx_unicast_pkts_vport; + u64 tx_unicast_bytes_vport; + u64 tx_multicast_pkts_vport; + u64 tx_multicast_bytes_vport; + u64 tx_broadcast_pkts_vport; + u64 tx_broadcast_bytes_vport; + + u64 rx_unicast_pkts_vport; + u64 rx_unicast_bytes_vport; + u64 rx_multicast_pkts_vport; + u64 rx_multicast_bytes_vport; + u64 rx_broadcast_pkts_vport; + u64 rx_broadcast_bytes_vport; + + u64 tx_discard_vport; + u64 rx_discard_vport; + u64 tx_err_vport; + u64 rx_err_vport; +}; + +struct hinic3_phy_fpga_port_stats { + u64 mac_rx_total_octs_port; + u64 mac_tx_total_octs_port; + u64 mac_rx_under_frame_pkts_port; + u64 mac_rx_frag_pkts_port; + u64 mac_rx_64_oct_pkts_port; + u64 mac_rx_127_oct_pkts_port; + u64 mac_rx_255_oct_pkts_port; + u64 mac_rx_511_oct_pkts_port; + u64 mac_rx_1023_oct_pkts_port; + u64 mac_rx_max_oct_pkts_port; + u64 mac_rx_over_oct_pkts_port; + u64 mac_tx_64_oct_pkts_port; + u64 mac_tx_127_oct_pkts_port; + u64 mac_tx_255_oct_pkts_port; + u64 mac_tx_511_oct_pkts_port; + u64 mac_tx_1023_oct_pkts_port; + u64 mac_tx_max_oct_pkts_port; + u64 mac_tx_over_oct_pkts_port; + u64 mac_rx_good_pkts_port; + u64 mac_rx_crc_error_pkts_port; + u64 mac_rx_broadcast_ok_port; + u64 mac_rx_multicast_ok_port; + u64 mac_rx_mac_frame_ok_port; + u64 mac_rx_length_err_pkts_port; + u64 mac_rx_vlan_pkts_port; + u64 mac_rx_pause_pkts_port; + u64 mac_rx_unknown_mac_frame_port; + u64 mac_tx_good_pkts_port; + u64 mac_tx_broadcast_ok_port; + u64 mac_tx_multicast_ok_port; + u64 mac_tx_underrun_pkts_port; + u64 mac_tx_mac_frame_ok_port; + u64 mac_tx_vlan_pkts_port; + u64 mac_tx_pause_pkts_port; +}; + +struct hinic3_port_stats { + struct hinic3_mgmt_msg_head msg_head; + + struct hinic3_phy_fpga_port_stats stats; +}; + +struct hinic3_cmd_vport_stats { + struct hinic3_mgmt_msg_head msg_head; + + u32 stats_size; + u32 rsvd1; + struct hinic3_vport_stats stats; + u64 rsvd2[6]; +}; + +struct hinic3_cmd_qpn { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 base_qpn; +}; + +enum hinic3_func_tbl_cfg_bitmap { + FUNC_CFG_INIT, + FUNC_CFG_RX_BUF_SIZE, + FUNC_CFG_MTU, +}; + +struct hinic3_func_tbl_cfg { + u16 rx_wqe_buf_size; + u16 mtu; + u32 rsvd[9]; +}; + +struct hinic3_cmd_set_func_tbl { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd; + + u32 cfg_bitmap; + struct hinic3_func_tbl_cfg tbl_cfg; +}; + +struct hinic3_cmd_cons_idx_attr { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_idx; + u8 dma_attr_off; + u8 pending_limit; + u8 coalescing_time; + u8 intr_en; + u16 intr_idx; + u32 l2nic_sqn; + u32 rsvd; + u64 ci_addr; +}; + +typedef union { + struct { + u32 tbl_index; + u32 cnt; + u32 total_cnt; + } mac_table_arg; + struct { + u32 er_id; + u32 vlan_id; + } vlan_elb_table_arg; + struct { + u32 func_id; + } vlan_filter_arg; + struct { + u32 mc_id; + } mc_elb_arg; + struct { + u32 func_id; + } func_tbl_arg; + struct { + u32 port_id; + } port_tbl_arg; + struct { + u32 tbl_index; + u32 cnt; + u32 total_cnt; + } fdir_io_table_arg; + struct { + u32 tbl_index; + u32 cnt; + u32 total_cnt; + } flexq_table_arg; + u32 args[4]; +} sm_tbl_args; + +#define DFX_SM_TBL_BUF_MAX (768) + +struct nic_cmd_dfx_sm_table { + struct hinic3_mgmt_msg_head msg_head; + u32 tbl_type; + sm_tbl_args args; + u8 tbl_buf[DFX_SM_TBL_BUF_MAX]; +}; + +struct hinic3_cmd_vlan_offload { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 vlan_offload; + u8 rsvd1[5]; +}; + +/* ucode capture cfg info */ +struct nic_cmd_capture_info { + struct hinic3_mgmt_msg_head msg_head; + u32 op_type; + u32 func_port; + u32 is_en_trx; /* 也作为tx_rx */ + u32 offset_cos; /* 也作为cos */ + u32 data_vlan; /* 也作为vlan */ +}; + +struct hinic3_cmd_lro_config { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; + u8 rsvd1; + u8 lro_ipv4_en; + u8 lro_ipv6_en; + u8 lro_max_pkt_len; /* unit is 1K */ + u8 resv2[13]; +}; + +struct hinic3_cmd_lro_timer { + struct hinic3_mgmt_msg_head msg_head; + + u8 opcode; /* 1: set timer value, 0: get timer value */ + u8 rsvd1; + u16 rsvd2; + u32 timer; +}; + +struct hinic3_cmd_local_lro_state { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; /* 0: get state, 1: set state */ + u8 state; /* 0: disable, 1: enable */ +}; + +struct hinic3_cmd_vf_vlan_config { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; + u8 rsvd1; + u16 vlan_id; + u8 qos; + u8 rsvd2[5]; +}; + +struct hinic3_cmd_spoofchk_set { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 state; + u8 rsvd1; +}; + +struct hinic3_cmd_tx_rate_cfg { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; + u32 min_rate; + u32 max_rate; + u8 rsvd2[8]; +}; + +struct hinic3_cmd_port_info { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 rsvd1[3]; + u8 port_type; + u8 autoneg_cap; + u8 autoneg_state; + u8 duplex; + u8 speed; + u8 fec; + u16 rsvd2; + u32 rsvd3[4]; +}; + +struct hinic3_cmd_register_vf { + struct hinic3_mgmt_msg_head msg_head; + + u8 op_register; /* 0 - unregister, 1 - register */ + u8 rsvd1[3]; + u32 support_extra_feature; + u8 rsvd2[32]; +}; + +struct hinic3_cmd_link_state { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 state; + u16 rsvd1; +}; + +struct hinic3_cmd_vlan_config { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; + u8 rsvd1; + u16 vlan_id; + u16 rsvd2; +}; + +/* set vlan filter */ +struct hinic3_cmd_set_vlan_filter { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 resvd[2]; + u32 vlan_filter_ctrl; /* bit0:vlan filter en; bit1:broadcast_filter_en */ +}; + +struct hinic3_cmd_link_ksettings_info { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 rsvd1[3]; + + u32 valid_bitmap; + u8 speed; /* enum nic_speed_level */ + u8 autoneg; /* 0 - off, 1 - on */ + u8 fec; /* 0 - RSFEC, 1 - BASEFEC, 2 - NOFEC */ + u8 rsvd2[21]; /* reserved for duplex, port, etc. */ +}; + +struct mpu_lt_info { + u8 node; + u8 inst; + u8 entry_size; + u8 rsvd; + u32 lt_index; + u32 offset; + u32 len; +}; + +struct nic_mpu_lt_opera { + struct hinic3_mgmt_msg_head msg_head; + struct mpu_lt_info net_lt_cmd; + u8 data[100]; +}; + +struct hinic3_force_pkt_drop { + struct hinic3_mgmt_msg_head msg_head; + + u8 port; + u8 rsvd1[3]; +}; +struct hinic3_rx_mode_config { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; + u32 rx_mode; +}; + +/* rss */ +struct hinic3_rss_context_table { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; + u32 context; +}; + + +struct hinic3_cmd_rss_engine_type { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; + u8 hash_engine; + u8 rsvd1[4]; +}; + + +struct hinic3_cmd_rss_hash_key { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; + u8 rsvd1; + u8 key[NIC_RSS_KEY_SIZE]; +}; + + +struct hinic3_rss_indir_table { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u16 rsvd1; + u8 indir[NIC_RSS_INDIR_SIZE]; +}; + +#define NIC_RSS_CMD_TEMP_ALLOC 0x01 +#define NIC_RSS_CMD_TEMP_FREE 0x02 + +struct hinic3_rss_template_mgmt { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 cmd; + u8 template_id; + u8 rsvd1[4]; +}; + + +struct hinic3_cmd_rss_config { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 rss_en; + u8 rq_priority_number; + u8 prio_tc[NIC_DCB_COS_MAX]; + u16 num_qps; + u16 rsvd1; +}; + +struct hinic3_dcb_state { + u8 dcb_on; + u8 default_cos; + u8 trust; + u8 rsvd1; + u8 pcp2cos[NIC_DCB_UP_MAX]; + u8 dscp2cos[64]; + u32 rsvd2[7]; +}; + +struct hinic3_cmd_vf_dcb_state { + struct hinic3_mgmt_msg_head msg_head; + + struct hinic3_dcb_state state; +}; + +struct hinic3_up_ets_cfg { /* delet */ + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 rsvd1[3]; + + u8 cos_tc[NIC_DCB_COS_MAX]; + u8 tc_bw[NIC_DCB_TC_MAX]; + u8 cos_prio[NIC_DCB_COS_MAX]; + u8 cos_bw[NIC_DCB_COS_MAX]; + u8 tc_prio[NIC_DCB_TC_MAX]; +}; + +#define CMD_QOS_ETS_COS_TC BIT(0) +#define CMD_QOS_ETS_TC_BW BIT(1) +#define CMD_QOS_ETS_COS_PRIO BIT(2) +#define CMD_QOS_ETS_COS_BW BIT(3) +#define CMD_QOS_ETS_TC_PRIO BIT(4) +struct hinic3_cmd_ets_cfg { + struct hinic3_mgmt_msg_head head; + + u8 port_id; + u8 op_code; /* 1 - set, 0 - get */ + /* bit0 - cos_tc, bit1 - tc_bw, bit2 - cos_prio, bit3 - cos_bw, bit4 - tc_prio */ + u8 cfg_bitmap; + u8 rsvd; + + u8 cos_tc[NIC_DCB_COS_MAX]; + u8 tc_bw[NIC_DCB_TC_MAX]; + u8 cos_prio[NIC_DCB_COS_MAX]; /* 0 - DWRR, 1 - STRICT */ + u8 cos_bw[NIC_DCB_COS_MAX]; + u8 tc_prio[NIC_DCB_TC_MAX]; /* 0 - DWRR, 1 - STRICT */ +}; + +struct hinic3_cmd_set_dcb_state { + struct hinic3_mgmt_msg_head head; + + u16 func_id; + u8 op_code; /* 0 - get dcb state, 1 - set dcb state */ + u8 state; /* 0 - disable, 1 - enable dcb */ + u8 port_state; /* 0 - disable, 1 - enable dcb */ + u8 rsvd[7]; +}; + +#define PFC_BIT_MAP_NUM 8 +struct hinic3_cmd_set_pfc { + struct hinic3_mgmt_msg_head head; + + u8 port_id; + u8 op_code; /* 0：get 1: set pfc_en 2: set pfc_bitmap 3: set all */ + u8 pfc_en; /* pfc_en 和 pfc_bitmap 必须同时设置 */ + u8 pfc_bitmap; + u8 rsvd[4]; +}; + +#define CMD_QOS_PORT_TRUST BIT(0) +#define CMD_QOS_PORT_DFT_COS BIT(1) +struct hinic3_cmd_qos_port_cfg { + struct hinic3_mgmt_msg_head head; + + u8 port_id; + u8 op_code; /* 0 - get, 1 - set */ + u8 cfg_bitmap; /* bit0 - trust, bit1 - dft_cos */ + u8 rsvd0; + + u8 trust; + u8 dft_cos; + u8 rsvd1[18]; +}; + +#define MAP_COS_MAX_NUM 8 +#define CMD_QOS_MAP_PCP2COS BIT(0) +#define CMD_QOS_MAP_DSCP2COS BIT(1) +struct hinic3_cmd_qos_map_cfg { + struct hinic3_mgmt_msg_head head; + + u8 op_code; + u8 cfg_bitmap; /* bit0 - pcp2cos, bit1 - dscp2cos */ + u16 rsvd0; + + u8 pcp2cos[8]; /* 必须8个一起配置 */ + /* 配置dscp2cos时，若cos值设置为0xFF，MPU则忽略此dscp优先级的配置, + * 允许一次性配置多个dscp跟cos的映射关系 + */ + u8 dscp2cos[64]; + u32 rsvd1[4]; +}; + +struct hinic3_cos_up_map { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 cos_valid_mask; /* every bit indicate index of map is valid 1 or not 0 */ + u16 rsvd1; + + /* user priority in cos(index:cos, value: up pri) */ + u8 map[NIC_DCB_UP_MAX]; +}; + +struct hinic3_cmd_pause_config { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 opcode; + u16 rsvd1; + u8 auto_neg; + u8 rx_pause; + u8 tx_pause; + u8 rsvd2[5]; +}; + +/* pfc风暴检测配置 */ +struct nic_cmd_pause_inquiry_cfg { + struct hinic3_mgmt_msg_head head; + + u32 valid; + + u32 type; /* 1: set, 2: get */ + + u32 rx_inquiry_pause_drop_pkts_en; /* rx 卸包使能 */ + u32 rx_inquiry_pause_period_ms; /* rx pause 检测周期 默认 200ms */ + u32 rx_inquiry_pause_times; /* rx pause 检测次数 默认1次 */ + /* rx pause 检测阈值 默认 PAUSE_FRAME_THD_10G/25G/40G/100 */ + u32 rx_inquiry_pause_frame_thd; + u32 rx_inquiry_tx_total_pkts; /* rx pause 检测tx收包总数 */ + + u32 tx_inquiry_pause_en; /* tx pause 检测使能 */ + u32 tx_inquiry_pause_period_ms; /* tx pause 检测周期 默认 200ms */ + u32 tx_inquiry_pause_times; /* tx pause 检测次数 默认 5次 */ + u32 tx_inquiry_pause_frame_thd; /* tx pause 检测阈值 */ + u32 tx_inquiry_rx_total_pkts; /* tx pause 检测rx收包总数 */ + + u32 rsvd[4]; +}; + +/* pfc/pause风暴tx异常上报 */ +struct nic_cmd_tx_pause_notice { + struct hinic3_mgmt_msg_head head; + + u32 tx_pause_except; /* 1: 异常，0: 正常 */ + u32 except_level; + u32 rsvd; +}; + +#define HINIC3_CMD_OP_FREE 0 +#define HINIC3_CMD_OP_ALLOC 1 + +struct hinic3_cmd_cfg_qps { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 opcode; /* 1: alloc qp, 0: free qp */ + u8 rsvd1; + u16 num_qps; + u16 rsvd2; +}; + +struct hinic3_cmd_led_config { + struct hinic3_mgmt_msg_head msg_head; + + u8 port; + u8 type; + u8 mode; + u8 rsvd1; +}; + +struct hinic3_cmd_port_loopback { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 opcode; + u8 mode; + u8 en; + u32 rsvd1[2]; +}; + +struct hinic3_cmd_get_light_module_abs { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 abs_status; /* 0:present, 1:absent */ + u8 rsv[2]; +}; + +#define STD_SFP_INFO_MAX_SIZE 640 +struct hinic3_cmd_get_std_sfp_info { + struct hinic3_mgmt_msg_head msg_head; + + u8 port_id; + u8 wire_type; + u16 eeprom_len; + u32 rsvd; + u8 sfp_info[STD_SFP_INFO_MAX_SIZE]; +}; + +struct hinic3_cable_plug_event { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 plugged; /* 0: unplugged, 1: plugged */ + u8 port_id; +}; + +/* MAC模块接口 */ +struct nic_cmd_mac_info { + struct hinic3_mgmt_msg_head head; + + u32 valid_bitmap; + u16 rsvd; + + u8 host_id[32]; + u8 port_id[32]; + u8 mac_addr[192]; +}; + +struct nic_cmd_set_tcam_enable { + struct hinic3_mgmt_msg_head head; + + u16 func_id; + u8 tcam_enable; + u8 rsvd1; + u32 rsvd2; +}; + +struct nic_cmd_set_fdir_status { + struct hinic3_mgmt_msg_head head; + + u16 func_id; + u16 rsvd1; + u8 pkt_type_en; + u8 pkt_type; + u8 qid; + u8 rsvd2; +}; + +#define HINIC3_TCAM_BLOCK_ENABLE 1 +#define HINIC3_TCAM_BLOCK_DISABLE 0 +#define HINIC3_MAX_TCAM_RULES_NUM 4096 + +/* tcam block type, according to tcam block size */ +enum { + NIC_TCAM_BLOCK_TYPE_LARGE = 0, /* block_size: 16 */ + NIC_TCAM_BLOCK_TYPE_SMALL, /* block_size: 0 */ + NIC_TCAM_BLOCK_TYPE_MAX +}; + +/* alloc tcam block input struct */ +struct nic_cmd_ctrl_tcam_block_in { + struct hinic3_mgmt_msg_head head; + + u16 func_id; /* func_id */ + u8 alloc_en; /* 0: 释放分配的tcam block, 1: 申请新的tcam block */ + /* 0: 分配16 size 的tcam block, 1: 分配0 size的tcam block, 其他预留 */ + u8 tcam_type; + u16 tcam_block_index; + /* 驱动发给uP表示驱动希望分配的block大小 + * uP返回给驱动的接口，表示uP 支持的分配的tcam block大小 + */ + u16 alloc_block_num; +}; + +/* alloc tcam block output struct */ +struct nic_cmd_ctrl_tcam_block_out { + struct hinic3_mgmt_msg_head head; + + u16 func_id; /* func_id */ + u8 alloc_en; /* 0: 释放分配的tcam block, 1: 申请新的tcam block */ + /* 0: 分配16 size 的tcam block, 1: 分配0 size的tcam block, 其他预留 */ + u8 tcam_type; + u16 tcam_block_index; + /* 驱动发给uP表示驱动希望分配的block大小 + * uP返回给驱动的接口，表示uP 支持的分配的tcam block大小 + */ + u16 mpu_alloc_block_size; +}; + +struct nic_cmd_flush_tcam_rules { + struct hinic3_mgmt_msg_head head; + + u16 func_id; /* func_id */ + u16 rsvd; +}; + +struct nic_cmd_dfx_fdir_tcam_block_table { + struct hinic3_mgmt_msg_head head; + u8 tcam_type; + u8 valid; + u16 tcam_block_index; + u16 use_function_id; + u16 rsvd; +}; + +struct tcam_result { + u32 qid; + u32 rsvd; +}; + +#define TCAM_FLOW_KEY_SIZE (44) + +struct tcam_key_x_y { + u8 x[TCAM_FLOW_KEY_SIZE]; + u8 y[TCAM_FLOW_KEY_SIZE]; +}; + +struct nic_tcam_cfg_rule { + u32 index; + struct tcam_result data; + struct tcam_key_x_y key; +}; + +#define TCAM_RULE_FDIR_TYPE 0 +#define TCAM_RULE_PPA_TYPE 1 + +struct nic_cmd_fdir_add_rule { + struct hinic3_mgmt_msg_head head; + + u16 func_id; + u8 type; + u8 fdir_ext; /* 0x1: flow bifur en bit */ + struct nic_tcam_cfg_rule rule; +}; + +struct nic_cmd_fdir_del_rules { + struct hinic3_mgmt_msg_head head; + + u16 func_id; + u8 type; + u8 rsvd; + u32 index_start; + u32 index_num; +}; + +struct nic_cmd_fdir_get_rule { + struct hinic3_mgmt_msg_head head; + + u32 index; + u8 valid; + u8 type; + u16 rsvd; + struct tcam_key_x_y key; + struct tcam_result data; + u64 packet_count; + u64 byte_count; +}; + +struct nic_cmd_fdir_get_block_rules { + struct hinic3_mgmt_msg_head head; + u8 tcam_block_type; // 目前仅有 NIC_TCAM_BLOCK_TYPE_LARGE + u8 tcam_table_type; // TCAM_RULE_PPA_TYPE 或 TCAM_RULE_FDIR_TYPE + u16 tcam_block_index; + u8 valid[NIC_TCAM_BLOCK_LARGE_SIZE]; + struct tcam_key_x_y key[NIC_TCAM_BLOCK_LARGE_SIZE]; + struct tcam_result data[NIC_TCAM_BLOCK_LARGE_SIZE]; +}; + +struct hinic3_tcam_key_ipv4_mem { + u32 rsvd1 : 4; + u32 tunnel_type : 4; + u32 ip_proto : 8; + u32 rsvd0 : 16; + u32 sipv4_h : 16; + u32 ip_type : 1; + u32 function_id : 15; + u32 dipv4_h : 16; + u32 sipv4_l : 16; + u32 vlan_id : 15; + u32 vlan_flag : 1; + u32 dipv4_l : 16; + u32 rsvd3; + u32 dport : 16; + u32 rsvd4 : 16; + u32 rsvd5 : 16; + u32 sport : 16; + u32 outer_sipv4_h : 16; + u32 rsvd6 : 16; + u32 outer_dipv4_h : 16; + u32 outer_sipv4_l : 16; + u32 vni_h : 16; + u32 outer_dipv4_l : 16; + u32 rsvd7 : 16; + u32 vni_l : 16; +}; + +typedef union hinic3_tag_tcam_ext_info { + struct { + u32 id : 16; /* id */ + u32 type : 4; /* type: 0-func, 1-vmdq, 2-port, 3-rsvd, 4-trunk, 5-dp, 6-mc */ + u32 host_id : 3; + u32 rsv : 8; + u32 ext : 1; + } bs; + u32 value; +} hinic3_tcam_ext_info_u; + + +struct hinic3_tcam_key_ipv6_mem { + u32 rsvd1 : 4; + u32 tunnel_type : 4; + u32 ip_proto : 8; + u32 rsvd0 : 16; + u32 sipv6_key0 : 16; + u32 ip_type : 1; + u32 function_id : 15; + u32 sipv6_key2 : 16; + u32 sipv6_key1 : 16; + u32 sipv6_key4 : 16; + u32 sipv6_key3 : 16; + u32 sipv6_key6 : 16; + u32 sipv6_key5 : 16; + u32 dport : 16; + u32 sipv6_key7 : 16; + u32 dipv6_key0 : 16; + u32 sport : 16; + u32 dipv6_key2 : 16; + u32 dipv6_key1 : 16; + u32 dipv6_key4 : 16; + u32 dipv6_key3 : 16; + u32 dipv6_key6 : 16; + u32 dipv6_key5 : 16; + u32 rsvd2 : 16; + u32 dipv6_key7 : 16; +}; + +struct hinic3_tcam_key_vxlan_ipv6_mem { + u32 rsvd1 : 4; + u32 tunnel_type : 4; + u32 ip_proto : 8; + u32 rsvd0 : 16; + + u32 dipv6_key0 : 16; + u32 ip_type : 1; + u32 function_id : 15; + + u32 dipv6_key2 : 16; + u32 dipv6_key1 : 16; + + u32 dipv6_key4 : 16; + u32 dipv6_key3 : 16; + + u32 dipv6_key6 : 16; + u32 dipv6_key5 : 16; + + u32 dport : 16; + u32 dipv6_key7 : 16; + + u32 rsvd2 : 16; + u32 sport : 16; + + u32 outer_sipv4_h : 16; + u32 rsvd3 : 16; + + u32 outer_dipv4_h : 16; + u32 outer_sipv4_l : 16; + + u32 vni_h : 16; + u32 outer_dipv4_l : 16; + + u32 rsvd4 : 16; + u32 vni_l : 16; +}; + +struct tag_tcam_key { + union { + struct hinic3_tcam_key_ipv4_mem key_info; + struct hinic3_tcam_key_ipv6_mem key_info_ipv6; + struct hinic3_tcam_key_vxlan_ipv6_mem key_info_vxlan_ipv6; + }; + + union { + struct hinic3_tcam_key_ipv4_mem key_mask; + struct hinic3_tcam_key_ipv6_mem key_mask_ipv6; + struct hinic3_tcam_key_vxlan_ipv6_mem key_mask_vxlan_ipv6; + }; +}; + +enum { + PPA_TABLE_ID_CLEAN_CMD = 0, + PPA_TABLE_ID_ADD_CMD, + PPA_TABLE_ID_DEL_CMD, + FDIR_TABLE_ID_ADD_CMD, + FDIR_TABLE_ID_DEL_CMD, + PPA_TABEL_ID_MAX +}; + +struct hinic3_ppa_cfg_table_id_cmd { + struct hinic3_mgmt_msg_head msg_head; + + u16 rsvd0; + u16 cmd; + u16 table_id; + u16 rsvd1; +}; + +struct hinic3_ppa_cfg_ppa_en_cmd { + struct hinic3_mgmt_msg_head msg_head; + + u16 func_id; + u8 ppa_en; + u8 rsvd; +}; + +struct hinic3_func_flow_bifur_en_cmd { + struct hinic3_mgmt_msg_head msg_head; + u16 func_id; + u8 flow_bifur_en; + u8 rsvd[5]; +}; + +struct hinic3_port_flow_bifur_en_cmd { + struct hinic3_mgmt_msg_head msg_head; + u16 port_id; + u8 flow_bifur_en; + u8 rsvd[5]; +}; + +struct hinic3_bond_mask_cmd { + struct hinic3_mgmt_msg_head msg_head; + u16 func_id; + u8 bond_mask; + u8 bond_en; + u8 func_valid; + u8 rsvd[3]; +}; + +#define HINIC3_TX_SET_PROMISC_SKIP 0 +#define HINIC3_TX_GET_PROMISC_SKIP 1 + +struct hinic3_tx_promisc_cfg { + struct hinic3_mgmt_msg_head msg_head; + u8 port_id; + u8 promisc_skip_en; /* 0: disable tx promisc replication, 1: enable tx promisc replication */ + u8 opcode; /* 0: set, 1: get */ + u8 rsvd1; +}; + +struct hinic3_ppa_cfg_mode_cmd { + struct hinic3_mgmt_msg_head msg_head; + + u16 rsvd0; + u8 ppa_mode; + u8 qpc_func_nums; + u16 base_qpc_func_id; + u16 rsvd1; +}; + +struct hinic3_ppa_flush_en_cmd { + struct hinic3_mgmt_msg_head msg_head; + + u16 rsvd0; + u8 flush_en; /* 0 flush done, 1 in flush operation */ + u8 rsvd1; +}; + +struct hinic3_ppa_fdir_query_cmd { + struct hinic3_mgmt_msg_head msg_head; + + u32 index; + u32 rsvd; + u64 pkt_nums; + u64 pkt_bytes; +}; + +/* BIOS CONF */ +enum { + NIC_NVM_DATA_SET = BIT(0), /* 1-save, 0-read */ + NIC_NVM_DATA_PXE = BIT(1), + NIC_NVM_DATA_VLAN = BIT(2), + NIC_NVM_DATA_VLAN_PRI = BIT(3), + NIC_NVM_DATA_VLAN_ID = BIT(4), + NIC_NVM_DATA_WORK_MODE = BIT(5), + NIC_NVM_DATA_PF_SPEED_LIMIT = BIT(6), + NIC_NVM_DATA_GE_MODE = BIT(7), + NIC_NVM_DATA_AUTO_NEG = BIT(8), + NIC_NVM_DATA_LINK_FEC = BIT(9), + NIC_NVM_DATA_PF_ADAPTIVE_LINK = BIT(10), + NIC_NVM_DATA_SRIOV_CONTROL = BIT(11), + NIC_NVM_DATA_EXTEND_MODE = BIT(12), + NIC_NVM_DATA_RESET = BIT(31), +}; + +#define BIOS_CFG_SIGNATURE 0x1923E518 +#define BIOS_OP_CFG_ALL(op_code_val) ((((op_code_val) >> 1) & (0xFFFFFFFF)) != 0) +#define BIOS_OP_CFG_WRITE(op_code_val) ((((op_code_val) & NIC_NVM_DATA_SET)) != 0) +#define BIOS_OP_CFG_PXE_EN(op_code_val) (((op_code_val) & NIC_NVM_DATA_PXE) != 0) +#define BIOS_OP_CFG_VLAN_EN(op_code_val) (((op_code_val) & NIC_NVM_DATA_VLAN) != 0) +#define BIOS_OP_CFG_VLAN_PRI(op_code_val) (((op_code_val) & NIC_NVM_DATA_VLAN_PRI) != 0) +#define BIOS_OP_CFG_VLAN_ID(op_code_val) (((op_code_val) & NIC_NVM_DATA_VLAN_ID) != 0) +#define BIOS_OP_CFG_WORK_MODE(op_code_val) (((op_code_val) & NIC_NVM_DATA_WORK_MODE) != 0) +#define BIOS_OP_CFG_PF_BW(op_code_val) (((op_code_val) & NIC_NVM_DATA_PF_SPEED_LIMIT) != 0) +#define BIOS_OP_CFG_GE_SPEED(op_code_val) (((op_code_val) & NIC_NVM_DATA_GE_MODE) != 0) +#define BIOS_OP_CFG_AUTO_NEG(op_code_val) (((op_code_val) & NIC_NVM_DATA_AUTO_NEG) != 0) +#define BIOS_OP_CFG_LINK_FEC(op_code_val) (((op_code_val) & NIC_NVM_DATA_LINK_FEC) != 0) +#define BIOS_OP_CFG_AUTO_ADPAT(op_code_val) (((op_code_val) & NIC_NVM_DATA_PF_ADAPTIVE_LINK) != 0) +#define BIOS_OP_CFG_SRIOV_ENABLE(op_code_val) (((op_code_val) & NIC_NVM_DATA_SRIOV_CONTROL) != 0) +#define BIOS_OP_CFG_EXTEND_MODE(op_code_val) (((op_code_val) & NIC_NVM_DATA_EXTEND_MODE) != 0) +#define BIOS_OP_CFG_RST_DEF_SET(op_code_val) (((op_code_val) & (u32)NIC_NVM_DATA_RESET) != 0) + +#define NIC_BIOS_CFG_MAX_PF_BW 100 +/* 注意:此结构必须保证4字节对齐 */ +struct nic_bios_cfg { + u32 signature; /* 签名，用于判断FLASH的内容合法性 */ + u8 pxe_en; /* PXE enable: 0 - disable 1 - enable */ + u8 extend_mode; + u8 rsvd0[2]; + u8 pxe_vlan_en; /* PXE VLAN enable: 0 - disable 1 - enable */ + u8 pxe_vlan_pri; /* PXE VLAN priority: 0-7 */ + u16 pxe_vlan_id; /* PXE VLAN ID 1-4094 */ + u32 service_mode; /* 参考CHIPIF_SERVICE_MODE_x 宏 */ + u32 pf_bw; /* PF速率，百分比 0-100 */ + u8 speed; /* enum of port speed */ + u8 auto_neg; /* 自协商开关 0 - 字段无效 1 - 开2 - 关 */ + u8 lanes; /* lane num */ + u8 fec; /* FEC模式, 参考 enum mag_cmd_port_fec */ + u8 auto_adapt; /* 自适应模式配置0 - 无效配置 1 - 开启 2 - 关闭 */ + u8 func_valid; /* 指示func_id是否有效; 0 - 无效，other - 有效 */ + u8 func_id; /* 当func_valid不为0时，该成员才有意义 */ + u8 sriov_en; /* SRIOV-EN: 0 - 无效配置， 1 - 开启， 2 - 关闭 */ +}; + +struct nic_cmd_bios_cfg { + struct hinic3_mgmt_msg_head head; + u32 op_code; /* Operation Code: Bit0[0: read 1:write, BIT1-6: cfg_mask */ + struct nic_bios_cfg bios_cfg; +}; + +struct nic_cmd_vhd_config { + struct hinic3_mgmt_msg_head head; + + u16 func_id; + u8 vhd_type; + u8 virtio_small_enable; /* 0: mergeable mode, 1: small mode */ +}; + +/* BOND */ +struct hinic3_create_bond_info { + u32 bond_id; /* bond设备号,output时有效,mpu操作成功返回时回填 */ + u32 master_slave_port_id; /* */ + u32 slave_bitmap; /* bond port id bitmap */ + u32 poll_timeout; /* bond设备链路检查时间 */ + u32 up_delay; /* 暂时预留 */ + u32 down_delay; /* 暂时预留 */ + u32 bond_mode; /* 暂时预留 */ + u32 active_pf; /* bond使用的active pf id */ + u32 active_port_max_num; /* bond活动成员口个数上限 */ + u32 active_port_min_num; /* bond活动成员口个数下限 */ + u32 xmit_hash_policy; /* hash策略，用于微码选路逻辑 */ + u32 rsvd[2]; +}; + +/* 创建bond的消息接口 */ +struct hinic3_cmd_create_bond { + struct hinic3_mgmt_msg_head head; + struct hinic3_create_bond_info create_bond_info; +}; + +struct hinic3_cmd_delete_bond { + struct hinic3_mgmt_msg_head head; + u32 bond_id; + u32 rsvd[2]; +}; + +struct hinic3_open_close_bond_info { + u32 bond_id; /* bond设备号 */ + u32 open_close_flag; /* 开启/关闭bond标识:1为open, 0为close */ + u32 rsvd[2]; +}; + +/* MPU bond的消息接口 */ +struct hinic3_cmd_open_close_bond { + struct hinic3_mgmt_msg_head head; + struct hinic3_open_close_bond_info open_close_bond_info; +}; + +/* LACPDU的port相关字段 */ +struct lacp_port_params { + u16 port_number; + u16 port_priority; + u16 key; + u16 system_priority; + u8 system[ETH_ALEN]; + u8 port_state; + u8 rsvd; +}; + +struct lacp_port_info { + u32 selected; + u32 aggregator_port_id; /* 使用的 aggregator port ID */ + + struct lacp_port_params actor; /* actor port参数 */ + struct lacp_port_params partner; /* partner port参数 */ + + u64 tx_lacp_pkts; + u64 rx_lacp_pkts; + u64 rx_8023ad_drop; + u64 tx_8023ad_drop; + u64 unknown_pkt_drop; + u64 rx_marker_pkts; + u64 tx_marker_pkts; +}; + +/* lacp 状态信息 */ +struct hinic3_bond_status_info { + struct hinic3_mgmt_msg_head head; + u32 bond_id; + u32 bon_mmi_status; /* 该bond子设备的链路状态 */ + u32 active_bitmap; /* 该bond子设备的slave port状态 */ + u32 port_count; /* 该bond子设备个数 */ + + struct lacp_port_info port_info[4]; + + u64 success_report_cnt[4]; /* 每个host成功上报lacp协商结果次数 */ + u64 fail_report_cnt[4]; /* 每个host上报lacp协商结果失败次数 */ + + u64 poll_timeout; + u64 fast_periodic_timeout; + u64 slow_periodic_timeout; + u64 short_timeout; + u64 long_timeout; + u64 aggregate_wait_timeout; + u64 tx_period_timeout; + u64 rx_marker_timer; +}; + +/* lacp协商结果更新之后向主机侧发送异步消息通知结构体 */ +struct hinic3_bond_active_report_info { + struct hinic3_mgmt_msg_head head; + u32 bond_id; + u32 bon_mmi_status; /* 该bond子设备的链路状态 */ + u32 active_bitmap; /* 该bond子设备的slave port状态 */ + + u8 rsvd[16]; +}; + +/* IP checksum error packets, enable rss quadruple hash. */ +struct hinic3_ipcs_err_rss_enable_operation_s { + struct hinic3_mgmt_msg_head head; + + u8 en_tag; + u8 type; /* 1: set 0: get */ + u8 rsvd[2]; +}; + +struct hinic3_smac_check_state { + struct hinic3_mgmt_msg_head head; + u8 smac_check_en; /* 1: enable 0: disable */ + u8 op_code; /* 1: set 0: get */ + u8 rsvd[2]; +}; + +struct hinic3_clear_log_state { + struct hinic3_mgmt_msg_head head; + u32 type; +}; + +#endif /* HINIC_MGMT_INTERFACE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd.h b/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd.h new file mode 100644 index 000000000..ac2675333 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd.h @@ -0,0 +1,31 @@ +/* + * Copyright (C), 2001-2011, Huawei Tech. Co., Ltd. + * File Name : nic_npu_cmd.h + * Version : Initial Draft + * Created : 2019/4/25 + * Last Modified : + * Description : NIC Commands between Driver and NPU + * Function List : + */ + +#ifndef NIC_NPU_CMD_H +#define NIC_NPU_CMD_H + +/* NIC CMDQ MODE */ +enum hinic3_ucode_cmd { + HINIC3_UCODE_CMD_MODIFY_QUEUE_CTX = 0, /**< Modify queue context. @see > hinic3_sq_ctxt_block */ + HINIC3_UCODE_CMD_CLEAN_QUEUE_CONTEXT, /**< Clean queue context. @see > hinic3_clean_queue_ctxt */ + HINIC3_UCODE_CMD_ARM_SQ, /**< Unused */ + HINIC3_UCODE_CMD_ARM_RQ, /**< Unused */ + HINIC3_UCODE_CMD_SET_RSS_INDIR_TABLE, /**< Set RSS indir table. @see > nic_rss_indirect_tbl */ + HINIC3_UCODE_CMD_SET_RSS_CONTEXT_TABLE, /**< Set RSS indir table. @see > nic_rss_context_tbl */ + HINIC3_UCODE_CMD_GET_RSS_INDIR_TABLE, + HINIC3_UCODE_CMD_GET_RSS_CONTEXT_TABLE, /**< Unused */ + HINIC3_UCODE_CMD_SET_IQ_ENABLE, /**< Unused */ + HINIC3_UCODE_CMD_SET_RQ_FLUSH = 10, /**< Set RQ flush. @see > hinic3_cmd_set_rq_flush */ + HINIC3_UCODE_CMD_MODIFY_VLAN_CTX, /**< Get rxq info. @see > nic_vlan_ctx */ + HINIC3_UCODE_CMD_PPA_HASH_TABLE, + HINIC3_UCODE_CMD_RXQ_INFO_GET = 13, /**< Get rxq info. @see > hinic3_rxq_hw, < rxq_check_info */ +}; + +#endif /* NIC_NPU_CMD_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd_defs.h new file mode 100644 index 000000000..23c61d5db --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd_defs.h @@ -0,0 +1,140 @@ +/* + * Copyright (C), 2001-2011, Huawei Tech. Co., Ltd. + * File Name : nic_npu_cmd_defs.h + * Version : Initial Draft + * Created : 2019/4/25 + * Last Modified : + * Description : NIC cmdq struct defines between Driver and NPU + * Function List : + */ + + +#ifndef NIC_NPU_CMD_DEFS_H +#define NIC_NPU_CMD_DEFS_H + +#include "typedef.h" +#include "nic_cfg_comm.h" + +/* + * NIC Command Queue Header + * queues context follow this header should be consecutive + */ +struct nic_cmdq_header { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + /* 0x0:SQ, 0x1:RQ */ + u16 queue_type; + /* queue number in buffer follow this header */ + u16 queue_num; +#else + u16 queue_num; + u16 queue_type; +#endif + } cmdq_ctx_dw0; + + u32 ctx_dw0; + }; + +#if (BYTE_ORDER == BIG_ENDIAN) + u16 rsvd; + u16 start_qid; +#else + u16 start_qid; + u16 rsvd; +#endif +}; + +struct nic_cmdq_context_modify_s { + struct nic_cmdq_header hdr; + u8 data[2016]; +}; + +struct nic_cmdq_clean_q_space { + /* queue_type = 0, TSO + queue_type = 1, LRO */ + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 queue_type; + u16 queue_num; +#else + u16 queue_num; + u16 queue_type; +#endif + } cmdq_space_dw0; + + u32 space_dw0; + }; + +#if (BYTE_ORDER == BIG_ENDIAN) + u16 rsvd; + u16 start_qid; +#else + u16 start_qid; + u16 rsvd; +#endif + + u32 rsvd1; +}; + +struct nic_cmdq_flush_rq_task { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 q_id; + u16 glb_rq_id; +#else + u16 glb_rq_id; + u16 q_id; +#endif + } bs; + + u32 value; + } dw0; +}; + +/* arm sq/rq */ +union nic_cmdq_arm { + struct cmdq_arm_dw0_s { +#if (BYTE_ORDER == BIG_ENDIAN) + u16 qpn; + u16 pi; +#else + u16 pi; + u16 qpn; +#endif + } dw0; + + u32 arm_dw0; +}; + + +/* rss */ +struct nic_rss_indirect_tbl { + u32 rsvd[4]; // Make sure that 16B beyond entry[] + u16 entry[NIC_RSS_INDIR_SIZE]; +}; + +struct nic_rss_glb_qid_indirect_tbl { + u32 group_index; + u32 offset; + u32 size; + u32 rsvd; /* Make sure that 16B beyond entry[] */ + u16 entry[NIC_RSS_INDIR_SIZE]; +}; + +struct nic_rss_context_tbl { + u32 rsvd[4]; + u32 ctx; +}; + +struct nic_vlan_ctx { + u32 func_id; + u32 qid; /* if qid = 0xFFFF, config current function all queue */ + u32 vlan_id; + u32 vlan_mode; + u32 vlan_sel; +}; + +#endif /* NIC_NPU_CMD_DEFS_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_wqe_defs.h b/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_wqe_defs.h new file mode 100644 index 000000000..d84c69198 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/nic/nic_npu_wqe_defs.h @@ -0,0 +1,240 @@ +/* + * Copyright (C), 2001-2011, Huawei Tech. Co., Ltd. + * File Name : nic_npu_wqe_define.h + * Version : Initial Draft + * Created : 2019/4/25 + * Last Modified : + * Description : NIC wqe define between Driver and NPU + * Function List : + */ + +#ifndef NIC_NPU_WQE_DEFINE_H +#define NIC_NPU_WQE_DEFINE_H + +#include "typedef.h" + +/* Inner/External IP type */ +typedef enum { + /* + * 00 - non ip packet or packet type is not defined by software + * 01 - ipv6 packet + * 10 - ipv4 packet with no ip checksum offload + * 11 - ipv4 packet with ip checksum offload + */ + NON_IP_TYPE = 0, + TYPE_IPV6, + TYPE_IPV4, + TYPE_IPV4_CS_OFF +} qsf_ip_type_e; + +typedef enum { + /* + * 0 - no udp / gre tunneling / no tunnel + * 1 - udp tunneling header with no cs + * 2 - udp tunneling header with cs + * 3 - gre tunneling header + */ + L4_TUNNEL_NO_TUNNEL = 0, + L4_TUNNEL_UDP_NO_CS, + L4_TUNNEL_UDP_CS, + L4_TUNNEL_GRE +} qsf_tunnel_type_e; + +typedef enum { + /* + * 00b - unknown / fragmented packet + * 01b - tcp + * 10b - sctp + * 11b - udp + */ + + L4_TYPE_UNKNOWN = 0, + L4_TYPE_TCP, + L4_TYPE_SCTP, + L4_TYPE_UDP +} qsf_l4_offload_type_e; + +/* * + * Struct name: l2nic_rx_cqe_s. + * @brief: L2nic_rx_cqe_s data structure. + * Description: + */ +typedef struct tag_l2nic_rx_cqe { + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rx_done : 1; + u32 bp_en : 1; + u32 decry_pkt : 1; /* decrypt packet flag */ + u32 flush : 1; + u32 spec_flags : 3; + u32 rsvd0 : 1; + u32 lro_num : 8; + u32 checksum_err : 16; +#else + u32 checksum_err : 16; + u32 lro_num : 8; + u32 rsvd0 : 1; + u32 spec_flags : 3; + u32 flush : 1; + u32 decry_pkt : 1; + u32 bp_en : 1; + u32 rx_done : 1; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 length : 16; + u32 vlan : 16; +#else + u32 vlan : 16; + u32 length : 16; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rss_type : 8; + u32 rsvd0 : 2; + u32 vlan_offload_en : 1; + u32 umbcast : 2; + u32 rsvd1 : 7; + u32 pkt_types : 12; +#else + u32 pkt_types : 12; + u32 rsvd1 : 7; + u32 umbcast : 2; + u32 vlan_offload_en : 1; + u32 rsvd0 : 2; + u32 rss_type : 8; +#endif + } bs; + u32 value; + } dw2; + + union { + struct { + u32 rss_hash_value; + } bs; + u32 value; + } dw3; + + /* dw4~dw7 field for nic/ovs multipexing */ + union { + struct { /* for nic */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 if_1588 : 1; + u32 if_tx_ts : 1; + u32 if_rx_ts : 1; + u32 rsvd : 1; + u32 msg_1588_type : 4; + u32 msg_1588_offset : 8; + u32 tx_ts_seq : 16; +#else + u32 tx_ts_seq : 16; + u32 msg_1588_offset : 8; + u32 msg_1588_type : 4; + u32 rsvd : 1; + u32 if_rx_ts : 1; + u32 if_tx_ts : 1; + u32 if_1588 : 1; +#endif + } bs; + + struct { /* for ovs */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 16; + u32 crypt_en : 1; + u32 sa_index : 15; +#else + u32 sa_index : 15; + u32 crypt_en : 1; + u32 rsvd : 16; +#endif + } ovs_bs; + + struct { + u32 xid; + } crypt_bs; + + u32 value; + } dw4; + + union { + struct { /* for nic */ + u32 msg_1588_ts; + } bs; + + struct { /* for ovs */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 mac_type : 2; /* for ovs. mac_type */ + u32 l3_type : 3; /* for ovs. l3_type */ + u32 l4_type : 3; /* for ovs. l4_type */ + u32 rsvd0 : 2; + u32 traffic_type : 6; /* for ovs. traffic type: 0-default l2nic pkt, 1-fallback traffic, 2-miss upcall + traffic, 2-command */ + u32 traffic_from : 16; /* for ovs. traffic from: vf_id, only support traffic_type=0(default l2nic) or 2(miss + upcall) */ +#else + u32 traffic_from : 16; + u32 traffic_type : 6; + u32 rsvd0 : 2; + u32 l4_type : 3; + u32 l3_type : 3; + u32 mac_type : 2; +#endif + } ovs_bs; + + struct { /* for crypt */ +#if (BYTE_ORDER == BIG_ENDIAN) + u32 rsvd : 16; + u32 decrypt_status : 8; + u32 esp_next_head : 8; +#else + u32 esp_next_head : 8; + u32 decrypt_status : 8; + u32 rsvd : 16; +#endif + } crypt_bs; + + u32 value; + } dw5; + + union { + struct { /* for nic */ + u32 lro_ts; + } bs; + + struct { /* for ovs */ + u32 reserved; + } ovs_bs; + + u32 value; + } dw6; + + union { + struct { /* for nic */ + // u32 reserved; + u32 first_len : 13; /* Datalen of the first or middle pkt size. */ + u32 last_len : 13; /* Data len of the last pkt size. */ + u32 pkt_num : 5; /* the number of packet. */ + u32 super_cqe_en : 1; /* only this bit = 1, other fileds in this DW is valid. */ + } bs; + + struct { /* for ovs */ + u32 localtag; + } ovs_bs; + + u32 value; + } dw7; +} l2nic_rx_cqe_s; + + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/public/npu_cmdq_base_defs.h b/drivers/infiniband/hw/hiroce3/include/public/npu_cmdq_base_defs.h new file mode 100644 index 000000000..1c4983121 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/public/npu_cmdq_base_defs.h @@ -0,0 +1,241 @@ +/****************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + ****************************************************************************** + File Name : npu_cmdq_base_defs.h + Version : Initial Draft + Description : common command queue interface + Function List : + History : + Modification: Created file + +******************************************************************************/ + +#ifndef NPU_CMDQ_BASE_DEFS_H +#define NPU_CMDQ_BASE_DEFS_H + +/* CmdQ Common subtype */ +enum comm_cmdq_cmd { + COMM_CMD_UCODE_ARM_BIT_SET = 2, + COMM_CMD_SEND_NPU_DFT_CMD, +}; + +/* Cmdq ack type */ +enum hinic3_ack_type { + HINIC3_ACK_TYPE_CMDQ, + HINIC3_ACK_TYPE_SHARE_CQN, + HINIC3_ACK_TYPE_APP_CQN, + + HINIC3_MOD_ACK_MAX = 15, +}; + +/* Defines the queue type of the set arm bit. */ +enum { + SET_ARM_BIT_FOR_CMDQ = 0, + SET_ARM_BIT_FOR_L2NIC_SQ, + SET_ARM_BIT_FOR_L2NIC_RQ, + SET_ARM_BIT_TYPE_NUM +}; + +/* Defines the type. Each function supports a maximum of eight CMDQ types. */ +enum { + CMDQ_0 = 0, + CMDQ_1 = 1, /* dedicated and non-blocking queues */ + CMDQ_NUM +}; + +/* *******************cmd common command data structure ************************ */ +// Func->ucode, which is used to set arm bit data, +// The microcode needs to perform big-endian conversion. +struct comm_info_ucode_set_arm_bit { + u32 q_type; + u32 q_id; +}; + +/* *******************WQE data structure ************************ */ +union cmdq_wqe_cs_dw0 { + struct { + u32 err_status : 29; + u32 error_code : 2; + u32 rsvd : 1; + } bs; + u32 val; +}; + +union cmdq_wqe_cs_dw1 { + struct { + u32 token : 16; // [15:0] + u32 cmd : 8; // [23:16] + u32 mod : 5; // [28:24] + u32 ack_type : 2; // [30:29] + u32 obit : 1; // [31] + } drv_wr; // This structure is used when the driver writes the wqe. + + struct { + u32 mod : 5; // [4:0] + u32 ack_type : 3; // [7:5] + u32 cmd : 8; // [15:8] + u32 arm : 1; // [16] + u32 rsvd : 14; // [30:17] + u32 obit : 1; // [31] + } wb; // The uCode writes back the structure of the CS_DW1. The driver reads and uses the structure. + u32 val; +}; + +/* CmdQ BD information or write back buffer information */ +struct cmdq_sge { + u32 pa_h; // Upper 32 bits of the physical address + u32 pa_l; // Upper 32 bits of the physical address + u32 len; // Invalid bit[31]. + u32 resv; +}; + +/* Ctrls section definition of WQE */ +struct cmdq_wqe_ctrls { + union { + struct { + u32 bdsl : 8; // [7:0] + u32 drvsl : 2; // [9:8] + u32 rsv : 4; // [13:10] + u32 wf : 1; // [14] + u32 cf : 1; // [15] + u32 tsl : 5; // [20:16] + u32 va : 1; // [21] + u32 df : 1; // [22] + u32 cr : 1; // [23] + u32 difsl : 3; // [26:24] + u32 csl : 2; // [28:27] + u32 ctrlsl : 2; // [30:29] + u32 obit : 1; // [31] + } bs; + u32 val; + } header; + u32 qsf; +}; + +/* Complete section definition of WQE */ +struct cmdq_wqe_cs { + union cmdq_wqe_cs_dw0 dw0; + union cmdq_wqe_cs_dw1 dw1; + union { + struct cmdq_sge sge; + u32 dw2_5[4]; + } ack; +}; + +/* Inline header in WQE inline, describing the length of inline data */ +union cmdq_wqe_inline_header { + struct { + u32 buf_len : 11; // [10:0] inline data len + u32 rsv : 21; // [31:11] + } bs; + u32 val; +}; + +/* Definition of buffer descriptor section in WQE */ +union cmdq_wqe_bds { + struct { + struct cmdq_sge bds_sge; + u32 rsvd[4]; /* Zwy is used to transfer the virtual address of the buffer. */ + } lcmd; /* Long command, non-inline, and SGE describe the buffer information. */ +}; + +/* Definition of CMDQ WQE */ +/* (long cmd, 64B) + * +----------------------------------------+ + * | ctrl section(8B) | + * +----------------------------------------+ + * | | + * | complete section(24B) | + * | | + * +----------------------------------------+ + * | | + * | buffer descriptor section(16B) | + * | | + * +----------------------------------------+ + * | driver section(16B) | + * +----------------------------------------+ + * + * + * (middle cmd, 128B) + * +----------------------------------------+ + * | ctrl section(8B) | + * +----------------------------------------+ + * | | + * | complete section(24B) | + * | | + * +----------------------------------------+ + * | | + * | buffer descriptor section(88B) | + * | | + * +----------------------------------------+ + * | driver section(8B) | + * +----------------------------------------+ + * + * + * (short cmd, 64B) + * +----------------------------------------+ + * | ctrl section(8B) | + * +----------------------------------------+ + * | | + * | complete section(24B) | + * | | + * +----------------------------------------+ + * | | + * | buffer descriptor section(24B) | + * | | + * +----------------------------------------+ + * | driver section(8B) | + * +----------------------------------------+ + */ +struct cmdq_wqe { + struct cmdq_wqe_ctrls ctrls; + struct cmdq_wqe_cs cs; + union cmdq_wqe_bds bds; +}; + +/* Definition of ctrls section in inline WQE */ +struct cmdq_wqe_ctrls_inline { + union { + struct { + u32 bdsl : 8; // [7:0] + u32 drvsl : 2; // [9:8] + u32 rsv : 4; // [13:10] + u32 wf : 1; // [14] + u32 cf : 1; // [15] + u32 tsl : 5; // [20:16] + u32 va : 1; // [21] + u32 df : 1; // [22] + u32 cr : 1; // [23] + u32 difsl : 3; // [26:24] + u32 csl : 2; // [28:27] + u32 ctrlsl : 2; // [30:29] + u32 obit : 1; // [31] + } bs; + u32 val; + } header; + u32 qsf; + u64 db; +}; + +/* Buffer descriptor section definition of WQE */ +union cmdq_wqe_bds_inline { + struct { + union cmdq_wqe_inline_header header; + u32 rsvd; + u8 data_inline[80]; + } mcmd; /* Middle command, inline mode */ + + struct { + union cmdq_wqe_inline_header header; + u32 rsvd; + u8 data_inline[16]; + } scmd; /* Short command, inline mode */ +}; + +struct cmdq_wqe_inline { + struct cmdq_wqe_ctrls_inline ctrls; + struct cmdq_wqe_cs cs; + union cmdq_wqe_bds_inline bds; +}; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/rdma_context_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/rdma_context_format.h new file mode 100644 index 000000000..7fa6efe0c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/rdma_context_format.h @@ -0,0 +1,4435 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA common context. + * Create: 2021-12-30 + */ + +#ifndef RDMA_CONTEXT_FORMAT_H +#define RDMA_CONTEXT_FORMAT_H + +#include "roce_hmm_context.h" +#include "rdma_ext_ctx_format.h" + + +/* Align each field with 4bytes. */ +#pragma pack(4) + +/* **************** Macro Definition ****************** */ +#define ROCE_BASE_GID_IDX 1 +#define RDMA_SGID_TBL_KEY_VFID_OFFSET (4) +#define RDMA_SGID_TBL_KEY_SGIDIDX_OFFSET (0) +#define ROCE_SPU_HOST_ID (4) +#define ROCE_SPU_OQID_HOST_ID (5) +#define ROCE_SDI_SHOST_HOST_ID 0 +#define ROCE_SDI_MHOST_HOST_ID 1 +#define QU_OQID_RW_CHANNEL 1 +#define ROCE_GET_HOST_OQID(host_id, xid) \ + ((((128U * (host_id) + ((xid) & 0x7f)) << 2) & 0x7ff) | (((host_id) & 0x7) << 11U) | (((xid) & 0x1) + 1)) +#define ROCE_GET_SPU_HOST_OQID(host_id, fid, xid) \ + (((((fid) & 0x1ff) << 2) & 0x7FF) | (((host_id) & 0x7) << 11U) | (QU_OQID_RW_CHANNEL)) + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#define ETH_ADDR_LEN (6) + +/* **************** Data Structure Definition ****************** */ +/* * QPC Format start */ + +/* Send Queue Context 64B */ +struct chip_seg_sqc { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_pd : 18; + u32 sq_inline_en : 1; + u32 sq_pi_on_chip : 1; + u32 sq_wqebb_size : 3; + u32 sq_page_size : 4; + u32 sq_size : 5; +#else + u32 sq_size : 5; /* Send WQ size is (2^sq_size)*WQEBBs; the maximum SQ size is 16K WQEs, so this field + * doesn't exceed 14. They have same configuration value: SQC.sq_size and SQAC.sq_size. + * Configured by Driver */ + + u32 sq_page_size : 4; /* Page size of SQ and RQ, equals to (2^sq_page_size)*4KB. + * The following three Page size have same configuration value: SQC.sq_page_size, + * SQAC.sq_page_size and RQC.rq_page_size. Configured by Driver */ + u32 sq_wqebb_size : 3; /* Send WQE Basic Block (WQEBB) size in bytes is 16*(2^sq_weqbb_size). + * for the SQ, this field should be fixed to 2. + * They have same configuration value: SQC.sq_wqebb_size and SQAC.sq_wqebb_size. + * Configured by Driver */ + u32 sq_pi_on_chip : 1; /* If set, the counter (PI index) of Send Queue is stored in the chip, the counter is + * absolute value. Configured by Driver */ + u32 sq_inline_en : 1; /* Indicates if the SQ supports inline data operation. + * Configured by Driver */ + u32 sq_pd : 18; /* Protection Domain. + * The following five Protection Domains have same configuration value: QCC.rc_pd, + * SQC.sq_pd, SQAC.sq_pd, RQC.rq_pd and RRWC.rrw_pd. Configured by Driver */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_so_ro : 2; + u32 sq_dma_attr_idx : 6; + u32 sq_wqecnt_rctl : 1; + u32 sq_prewqe_mode : 1; + u32 sq_pi_vld : 1; + u32 sq_wqecnt_rctl_en : 1; + u32 sq_wqecnt_lth : 4; + u32 rsvd : 16; +#else + u32 rsvd : 16; + u32 sq_wqecnt_lth : 4; /* WQE Counter Low Threshold, equals to (2^sq_wqecnt_lth). + * Configured by Driver */ + u32 sq_wqecnt_rctl_en : 1; /* If this field is equal to zero, the SQ PI updating should be not controlled by + * the "sq_wqecnt_rctl" field; else the SQ RI updating can be performed only if + * the "sq_wqecnt_rctl" is equal to one. Configured by Driver */ + u32 sq_pi_vld : 1; /* If set, the SQ should use the Index Mechanism, else the SQ uses the Owner Bit + * Mechanism. Configured by Driver */ + u32 sq_prewqe_mode : 1; /* If set,the engine just performs prefetch WQE + * processing after completing the current WQE in + * the SQ_DMA_GEN_API flow. + */ + u32 sq_wqecnt_rctl : 1; /* The hardware clear it to zero when performing a SQ PI updating, and driver set it + * to one to indicate the hardware can performing SQ PI updating. + * N/A */ + u32 sq_dma_attr_idx : 6; /* bit[05:00] It specifies the outbound PCIe TLP header attribute of the DMA + * operation. This filed is only valid when processing SQ's WQEs. The following two + * "dma_attr_idx" have same configuration value: SQC.sq_dma_attr_idx and + * SQAC.sq_dma_attr_idx. Configured by Driver */ + u32 sq_so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + * This field is only valid when processing SQ's WQEs. + * 2'b00: Strict Ordering; + * 2'b01: Relaxed Ordering; + * 2'b10: ID Based Ordering; + * 2'b11: Both Relaxed Ordering and ID Based Ordering. + * The following two "so_ro" have same configuration value: SQC.sq_so_ro and + * SQAC.sq_so_ro. Configured by Driver */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_state : 4; + u32 rsvd2 : 4; + u32 sq_rkey_en : 1; + u32 sq_wqe_check_en : 1; + u32 rsvd1 : 6; + u32 sq_pi : 16; +#else + u32 sq_pi : 16; /* The Producer Index (PI) of Send Queue (Step: WQEBB) 0x0 */ + u32 rsvd1 : 6; + u32 sq_wqe_check_en : 1; + u32 sq_rkey_en : 1; + u32 rsvd2 : 4; + u32 sq_state : 4; /* Send Queue State.0x0:ok;0x1:error;0xf:hardware has no access right.Other:reserved. + * 0x0 */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_ci : 16; + u32 rsvd : 3; + u32 dsgl_en : 1; /* Whether to work in dual sgl mode */ + u32 sq_load_pi : 1; + u32 sq_load_page_gpa : 1; + u32 sq_wqe_curt_page_vld : 1; + u32 sq_wqe_next_page_vld : 1; + u32 sq_wqe_curt_page_gpa_h : 8; +#else + u32 sq_wqe_curt_page_gpa_h : 8; /* bit[63:56] Indicates the GPA of current SQ buffer's page pointed by + "sq_ci". 0x0 */ + u32 sq_wqe_next_page_vld : 1; /* Indicates if the "sq_wqe_next_page_gpa" field is valid. */ + u32 sq_wqe_curt_page_vld : 1; /* Indicates if the "sq_wqe_curt_page_gpa" field is valid. + * 1: it is valid;0: it is invalid. + * 0x0 */ + u32 sq_load_page_gpa : 1; /* Indicates the thread is performing a prefetch for GPA of WQE page. 0x0 */ + u32 sq_load_pi : 1; /* Indicates the thread is performing a PI prefetch processing */ + u32 dsgl_en : 1; + u32 rsvd : 3; + u32 sq_ci : 16; /* bit[19:00] The CI index of Send Queue (Step: WQEBB) 0x0 */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 sq_wqe_curt_page_gpa_m; /* bit[55:24] */ + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_wqe_curt_page_gpa_l : 12; + u32 sq_wqe_next_page_gpa_h : 20; +#else + u32 sq_wqe_next_page_gpa_h : 20; /* bit[63:44] */ + u32 sq_wqe_curt_page_gpa_l : 12; /* bit[23:12] */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + u32 sq_wqe_next_page_gpa_l; /* bit[43:12] Indicates the page GPA of next SQ buffer's page pointed by "sq_ci". 0x0 */ + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_wqe_prefetch_ci : 16; + u32 rsvd : 4; + u32 sq_signature : 3; + u32 sq_wqe_prefetch_curtmax : 3; + u32 sq_wqe_prefetch_maxnum : 3; + u32 sq_wqe_prefetch_minnum : 3; +#else + u32 sq_wqe_prefetch_minnum : 3; + u32 sq_wqe_prefetch_maxnum : 3; + u32 sq_wqe_prefetch_curtmax : 3; + u32 sq_signature : 3; + u32 rsvd : 4; + u32 sq_wqe_prefetch_ci : 16; /* bit[15:00] The prefetch CI index of Send Queue (Step: WQEBB).0x0 */ +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_curt_sge_vld : 1; + u32 rsvd : 3; + u32 sq_curt_sge_lkey : 28; +#else + u32 sq_curt_sge_lkey : 28; /* bit[27:00] Indicates the L_Key of current SGE. Using sq_curt_sge_lkey[27:8] to + access the corresponding MPT. 0x0 */ + u32 rsvd : 3; + u32 sq_curt_sge_vld : 1; /* Indicates current SGE information is valid. The remaining sq_curt_sge_* field are + * only valid when the sq_curt_sge_vld is asserted.1: SGE is valid;,0: SGE is + * invalid. 0x0 */ +#endif + } bs; + u32 value; + } dw8; + + /* DW9~10 */ + union { + u64 sq_curt_sge_va; /* hi:bit[63:32],lo:bit[31:00] */ + struct { + u32 sq_curt_sge_va_hi; + u32 sq_curt_sge_va_lo; + } dw9; + }; + + /* DW11 */ + u32 sq_curt_sge_remain_len; /* bit[31:00] Indicates the remaining memory space of current SGE. 0x0 */ + + /* DW12 */ + u32 sq_curt_sge_dbuff_gpa_h; /* bit[63:32] Indicates the GPA of current data buffer page pointed by + "sq_curt_sge_va".0x0 */ + + /* DW13 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_curt_sge_dbuff_gpa_l : 20; + u32 sq_curt_sge_dbuff_gpa_vld : 1; + u32 sq_curt_sge_dsgl : 1; + u32 sq_curt_sge_used : 1; + u32 sq_curt_sge_last : 1; + u32 rsvd : 8; +#else + u32 rsvd : 8; + u32 sq_curt_sge_last : 1; /* Indicates the current SGE is the last SGE for the current WQE. 0x0 */ + u32 sq_curt_sge_used : 1; + u32 sq_curt_sge_dsgl : 1; + u32 sq_curt_sge_dbuff_gpa_vld : 1; /* Indicates if the "sq_curt_sge_dbuff_gpa" field is valid. 1: it is + valid;0:it is invalid. */ + u32 sq_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] Indicates the GPA of current data buffer page pointed by + "sq_curt_sge_va".0x0 */ +#endif + } bs; + u32 value; + } dw13; + + /* DW14 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_mtt_prefetch_cline_num : 5; + u32 sq_mtt_prefetch_cline_ptr : 6; + u32 sq_wqe_prefetch_finish : 1; + u32 rsvd : 4; + u32 sq_mtt_prefetch_wqe_ci : 16; +#else + u32 sq_mtt_prefetch_wqe_ci : 16; /* bit[15:0] Indicates the WQE index of prefetch MTTs operation */ + u32 rsvd : 4; + u32 sq_wqe_prefetch_finish : 1; + u32 sq_mtt_prefetch_cline_ptr : 6; + u32 sq_mtt_prefetch_cline_num : 5; +#endif + } bs; + u32 value; + } dw14; + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_wqe_cache_thd_sel : 2; + u32 sq_mtt_prefetch_maxlen : 3; + u32 sq_wqe_prefetch_mode : 1; + u32 sq_prefetch_one_wqe : 1; + u32 sq_curt_sge_idx : 6; + u32 rsvd : 8; + u32 sq_mtt_prefetch_sge_idx : 6; + u32 sq_load_wqe : 1; + u32 sq_load_mtt : 1; + u32 sq_load_dbuff : 1; + u32 sq_prefetch_thread_num : 2; +#else + u32 sq_prefetch_thread_num : 2; + u32 sq_load_dbuff : 1; + u32 sq_load_mtt : 1; + u32 sq_load_wqe : 1; + u32 sq_mtt_prefetch_sge_idx : 6; + u32 rsvd : 8; + u32 sq_curt_sge_idx : 6; /* The SGE index of current accessed WQE. 0x0 */ + u32 sq_prefetch_one_wqe : 1; + u32 sq_wqe_prefetch_mode : 1; + u32 sq_mtt_prefetch_maxlen : 3; + u32 sq_wqe_cache_thd_sel : 2; +#endif + } bs; + u32 value; + } dw15; +}; + +/* Send Queue ACK Context 64B */ +struct chip_seg_sqac { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_pd : 18; + u32 rsvd : 1; + u32 vbs_sqa_pi_on_chip : 1; + u32 sq_wqebb_size : 3; + u32 sq_page_size : 4; + u32 sq_size : 5; +#else + u32 sq_size : 5; /* Send WQ size is (2^sq_size)*WQEBBs; the maximum SQ size is 16K WQEs, so this field + * doesn't exceed 14. They have same configuration value: SQC.sq_size and SQAC.sq_size. + * Configured by Driver */ + + u32 sq_page_size : 4; /* Page size of SQ and RQ, equals to (2^sq_page_size)*4KB. + * The following three Page size have same configuration value: SQC.sq_page_size, + * SQAC.sq_page_size and RQC.rq_page_size. Configured by Driver */ + u32 sq_wqebb_size : 3; /* Send WQE Basic Block (WQEBB) size in bytes is 16*(2^sq_weqbb_size). + * for the SQ, this field should be fixed to 2. + * They have same configuration value: SQC.sq_wqebb_size and SQAC.sq_wqebb_size. + * Configured by Driver */ + u32 vbs_sqa_pi_on_chip : 1; + u32 rsvd : 1; + u32 sq_pd : 18; /* Protection Domain. + * The following five Protection Domains have same configuration value: QCC.rc_pd, + * SQC.sq_pd, SQAC.sq_pd, RQC.rq_pd and RRWC.rrw_pd. Configured by Driver */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_so_ro : 2; + u32 sq_dma_attr_idx : 6; + u32 rsvd2 : 1; + u32 sqa_prewqe_mode : 1; + u32 vbs_sqa_pi_vld : 1; + u32 rsvd1 : 1; + u32 sqa_cqn : 20; +#else + u32 sqa_cqn : 20; /* bit[19:00] SQ's Completion Queue Number. */ + u32 rsvd1 : 1; + u32 vbs_sqa_pi_vld : 1; + u32 sqa_prewqe_mode : 1; + u32 rsvd2 : 1; + u32 sq_dma_attr_idx : 6; /* bit[05:00] It specifies the outbound PCIe TLP header attribute of the DMA + * operation. This filed is only valid when processing SQ's WQEs. The following two + * "dma_attr_idx"have same configuration value: SQC. sq_dma_attr_idx and + * SQAC.sq_dma_attr_idx. Configured by Driver */ + u32 sq_so_ro : 2; +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_state : 4; + u32 rsvd2 : 4; + u32 sq_rkey_en : 1; + u32 sq_wqe_check_en : 1; + u32 rsvd1 : 6; + u32 sqa_wqe_index : 16; +#else + u32 sqa_wqe_index : 16; /* bit[15:00] */ + u32 rsvd1 : 6; + u32 sq_wqe_check_en : 1; + u32 sq_rkey_en : 1; + u32 rsvd2 : 4; + u32 sqa_state : 4; +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_ci : 16; + u32 rsvd1 : 3; + u32 dsgl_en : 1; + u32 rsvd : 1; + u32 sqa_load_page_gpa : 1; + u32 sqa_wqe_curt_page_vld : 1; + u32 sqa_wqe_next_page_vld : 1; + u32 sqa_wqe_curt_page_gpa_h : 8; +#else + u32 sqa_wqe_curt_page_gpa_h : 8; /* bit[63:56] */ + u32 sqa_wqe_next_page_vld : 1; + u32 sqa_wqe_curt_page_vld : 1; + u32 sqa_load_page_gpa : 1; + u32 rsvd : 1; + u32 dsgl_en : 1; + u32 rsvd1 : 3; + u32 sqa_ci : 16; /* bit[15:00] */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 sqa_wqe_curt_page_gpa_m; /* bit[55:24] */ + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_wqe_curt_page_gpa_l : 12; + u32 sqa_wqe_next_page_gpa_h : 20; +#else + u32 sqa_wqe_next_page_gpa_h : 20; /* bit[63:44] */ + u32 sqa_wqe_curt_page_gpa_l : 12; /* bit[23:12] */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + u32 sqa_wqe_next_page_gpa_l; /* bit[43:12] */ + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_wqe_prefetch_ci : 16; + u32 rsvd2 : 4; + u32 sqa_signature : 3; + u32 rsvd1 : 3; + u32 sqa_wqe_prefetch_maxnum : 3; + u32 sqa_wqe_prefetch_minnum : 3; +#else + u32 sqa_wqe_prefetch_minnum : 3; + u32 sqa_wqe_prefetch_maxnum : 3; + u32 rsvd1 : 3; + u32 sqa_signature : 3; + u32 rsvd2 : 4; + u32 sqa_wqe_prefetch_ci : 16; +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_curt_sge_vld : 1; + u32 rsvd : 3; + u32 sqa_curt_sge_lkey : 28; +#else + u32 sqa_curt_sge_lkey : 28; /* bit[27:00] */ + u32 rsvd : 3; + u32 sqa_curt_sge_vld : 1; +#endif + } bs; + u32 value; + } dw8; + + /* DW9~10 */ + union { + u64 sqa_curt_sge_va; /* hi:bit[63:32],lo:bit[31:00] */ + struct { + u32 sqa_curt_sge_va_hi; + u32 sqa_curt_sge_va_lo; + } dw9; + }; + + /* DW11 */ + u32 sqa_curt_sge_remain_len; /* bit[31:00] */ + + /* DW12 */ + u32 sqa_curt_sge_dbuff_gpa_h; /* bit[63:32] */ + + /* DW13 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_curt_sge_dbuff_gpa_l : 20; + u32 sqa_curt_sge_dbuff_gpa_vld : 1; + u32 sqa_curt_sge_dsgl : 1; + u32 sqa_curt_sge_used : 1; + u32 sqa_curt_sge_last : 1; + u32 rsvd : 8; +#else + u32 rsvd : 8; + u32 sqa_curt_sge_last : 1; + u32 sqa_curt_sge_used : 1; + u32 sqa_curt_sge_dsgl : 1; + u32 sqa_curt_sge_dbuff_gpa_vld : 1; + u32 sqa_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ +#endif + } bs; + u32 value; + } dw13; + + /* DW14 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_mtt_prefetch_cline_num : 5; + u32 sqa_mtt_prefetch_cline_ptr : 6; + u32 sqa_mtt_prefetch_finish : 1; + u32 rsvd : 4; + u32 sqa_mtt_prefetch_wqe_ci : 16; +#else + u32 sqa_mtt_prefetch_wqe_ci : 16; + u32 rsvd : 4; + u32 sqa_mtt_prefetch_finish : 1; + u32 sqa_mtt_prefetch_cline_ptr : 6; + u32 sqa_mtt_prefetch_cline_num : 5; +#endif + } bs; + u32 value; + } dw14; + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqa_wqe_cache_thd_sel : 2; + u32 sqa_mtt_prefetch_maxlen : 3; + u32 rsvd2 : 2; + u32 sqa_curt_sge_idx : 6; + u32 rsvd1 : 8; + u32 sqa_mtt_prefetch_sge_idx : 6; + u32 sqa_load_wqe : 1; + u32 sqa_load_mtt : 1; + u32 sqa_load_dbuff : 1; + u32 sqa_prefetch_thread_num : 2; +#else + u32 sqa_prefetch_thread_num : 2; + u32 sqa_load_dbuff : 1; + u32 sqa_load_mtt : 1; + u32 sqa_load_wqe : 1; + u32 sqa_mtt_prefetch_sge_idx : 6; + u32 rsvd1 : 8; + u32 sqa_curt_sge_idx : 6; + u32 rsvd2 : 2; + u32 sqa_mtt_prefetch_maxlen : 3; + u32 sqa_wqe_cache_thd_sel : 2; +#endif + } bs; + u32 value; + } dw15; +}; + +/* Receive Queue Context 64B */ +typedef struct chip_seg_rqc { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_pd : 18; + u32 rq_inline_en : 1; + u32 rq_pi_on_chip : 1; + u32 rq_wqebb_size : 3; + u32 rq_page_size : 4; + u32 rq_size : 5; +#else + u32 rq_size : 5; /* Receive Queue size, equals to (2^rq_size)*WQEBB. The maximum RQ size is 16K WQEs, + * so this field doesn't exceed 14. + * Configured by Driver */ + u32 rq_page_size : 4; /* Page size of SQ and RQ, equals to (2^rq_page_size)*4KB. + * Configured by Driver */ + u32 rq_wqebb_size : 3; /* Receive WQE Basic Block (WQEBB) size in bytes is (2^rq_wqebb_size)*16B. + * The minimum size is 16B and the values 4, 5, 6, 7 are reserved. + * Configured by Driver */ + u32 rq_pi_on_chip : 1; /* If set, the counter (PI index) of Receive Queue is stored in the chip, the counter + * is absolute value. Configured by Driver */ + u32 rq_inline_en : 1; /* If set, in-line scatter is enabled for this RQ. + * Configured by Driver */ + u32 rq_pd : 18; /* bit[17:00] Protection Domain.The following five Protection Domains have same configuration + * value: QCC.rc_pd, SQC.sq_pd, SQAC.sq_pd, RQC.rq_pd and RRWC.rrw_pd. Configured by + * Driver */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_so_ro : 2; + u32 rq_dma_attr_idx : 6; + u32 rq_rkey_en : 1; + u32 rq_signature : 3; + u32 rq_cqn : 20; +#else + u32 rq_cqn : 20; /* bit[19:00] Receive Queue completions are to be reported to this CQ number. + * Configured by Driver */ + u32 rq_signature : 3; + u32 rq_rkey_en : 1; + u32 rq_dma_attr_idx : 6; /* bit[05:00] It specifies the outbound PCIe TLP header attribute of the DMA + * operation. This filed is only valid when processing RQ's WQEs. Configured by + * Driver */ + u32 rq_so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + * This field is only valid when processing RQ's WQEs. + * 2'b00: Strict Ordering; + * 2'b01: Relaxed Ordering; + * 2'b10: ID Based Ordering; + * 2'b11: Both Relaxed Ordering and ID Based Ordering. + * Configured by Driver */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_state : 4; + u32 rsvd2 : 13; + u32 rq_wqe_cache_thd_sel : 2; + u32 rq_inlin_len : 4; + u32 rq_wqecnt_rctl : 1; + u32 rsvd1 : 2; + u32 rq_wqecnt_rctl_en : 1; + u32 rq_wqecnt_lth : 4; + u32 rq_srq_en : 1; +#else + u32 rq_srq_en : 1; /* If set, indicates it should use SRQ as the receive queue. + * Configured by Driver */ + u32 rq_wqecnt_lth : 4; /* WQE Counter Low Threshold, equals to (2^rq_wqecnt_lth). + * Configured by Driver */ + u32 rq_wqecnt_rctl_en : 1; /* If this field is equal to zero, the RQ PI updating should be not controlled by + * the "rq_wqecnt_rctl" field; else the RQ RI updating can be performed only if + * the "rq_wqecnt_rctl" is equal to one. Configured by Driver */ + u32 rsvd1 : 2; + + u32 rq_wqecnt_rctl : 1; /* The hardware clear it to zero when performing a RQ PI updating, and driver set it + * to one to indicate the hardware can performing RQ PI updating. N/A */ + u32 rq_inlin_len : 4; /* Inline Data Length, equals to (2^rq_inline_len) bytes. + * Configured by Driver */ + u32 rq_wqe_cache_thd_sel : 2; + u32 rsvd2 : 13; + u32 rq_state : 4; /* Receive Queue State.0xf: ok;0x1: error;0x0: hardware has no access right.Other: + * reserved. 0x0 */ +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_state : 4; + u32 rsvd : 2; + u32 container_en : 1; + u32 rsvd0 : 1; + u32 rq_srqn : 18; + u32 rsvd1 : 5; + u32 rq_srq_en : 1; +#else + u32 rq_srq_en : 1; + u32 rsvd1 : 5; + u32 rq_srqn : 18; + u32 rsvd0 : 1; + u32 container_en : 1; + u32 rsvd : 2; + u32 rq_state : 4; +#endif + } srq; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_state : 4; + u32 container_size : 2; + u32 container_en : 1; + u32 rsvd : 6; + u32 rq_srqn : 18; + u32 rq_srq_en : 1; +#else + u32 rq_srq_en : 1; + u32 rq_srqn : 18; + u32 rsvd : 6; + u32 container_en : 1; + u32 container_size : 2; + u32 rq_state : 4; +#endif + } srq_c; + + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_ci : 16; + u32 rsvd : 4; + u32 rq_load_pi : 1; + u32 rq_load_page_gpa : 1; + u32 rq_wqe_curt_page_vld : 1; + u32 rq_wqe_next_page_vld : 1; + u32 rq_wqe_curt_page_gpa_h : 8; +#else + u32 rq_wqe_curt_page_gpa_h : 8; /* bit[63:56] Indicates the GPA of current RQ buffer's page pointed by + * "rq_ci". 0x0 */ + u32 rq_wqe_next_page_vld : 1; /* Indicates if the "rq_wqe_curt_page_gpa" field is valid. + * 1: it is valid;0: it is invalid. + * 0x0 */ + u32 rq_wqe_curt_page_vld : 1; /* Indicates if the "rq_wqe_curt_page_gpa" field is valid. + * 1: it is valid;0: it is invalid. + * 0x0 */ + u32 rq_load_page_gpa : 1; /* Indicates the thread is performing a prefetch for GPA of WQE page. + * 0x0 */ + u32 rq_load_pi : 1; + u32 rsvd : 4; + u32 rq_ci : 16; /* bit[15:00] The CI index of Receive Queue (Step: WQEBB) 0x0 */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 rq_wqe_curt_page_gpa_m; /* bit[55:24] */ + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_wqe_curt_page_gpa_l : 12; /* bit[23:12] */ + u32 rq_wqe_next_page_gpa_h : 20; /* bit[63:44] */ +#else + u32 rq_wqe_next_page_gpa_h : 20; /* bit[63:44] */ + u32 rq_wqe_curt_page_gpa_l : 12; /* bit[23:12] */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + u32 rq_wqe_next_page_gpa_l; /* bit[43:12] */ + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_pi : 16; + u32 rq_wqe_prefetch_ci : 16; +#else + u32 rq_wqe_prefetch_ci : 16; /* bit[15:00] The prefetch CI index of Receive Queue (Step: WQEBB).0x0 */ + u32 rq_pi : 16; /* bit[15:00] The Producer Index (PI) of Receive Queue (Step: WQEBB).0x0 */ +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_curt_sge_vld : 1; + u32 rsvd : 3; + u32 rq_curt_sge_lkey : 28; +#else + u32 rq_curt_sge_lkey : 28; /* bit[27:00] Indicates the L_Key of current SGE. Using rq_curt_sge_lkey[27:8] to + access the corresponding MPT.0x0 */ + u32 rsvd : 3; + u32 rq_curt_sge_vld : 1; /* Indicates current SGE information is valid. The remaining rq_curt_sge_* field are + * only valid when the rq_curt_sge_vld is asserted.1: SGE is valid;0: SGE is + * invalid.0x0 */ +#endif + } bs; + u32 value; + } dw8; + + /* DW9~10 */ + union { + u64 rq_curt_sge_va; /* hi:bit[63:32],lo:bit[31:00] */ + struct { + u32 rq_curt_sge_va_hi; + u32 rq_curt_sge_va_lo; + } dw9; + }; + + /* DW11 */ + u32 rq_curt_sge_remain_len; /* bit[31:00] Indicates the remaining memory space of current SGE.0x0 */ + + /* DW12 */ + u32 rq_curt_sge_dbuff_gpa_h; /* bit[63:32] Indicates the GPA of current data buffer page pointed by + "rq_curt_sge_va".0x0 */ + + /* DW13 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_curt_sge_dbuff_gpa_l : 20; /* bit[51:32] */ + u32 rq_curt_sge_dbuff_gpa_vld : 1; /* Indicates if the "rq_curt_sge_dbuff_gpa" field is valid.1: it is + valid;0: it is invalid.0x0 */ + u32 rq_curt_sge_dsgl : 1; + u32 rq_curt_sge_used : 1; + u32 rq_curt_sge_last : 1; /* Indicates the current SGE is the last SGE for the current WQE.0x0 */ + u32 rq_curt_wqe_status : 1; /* Indicates the current Receive WQE's status.0: the Receive WQE don't be + * accessed; 1: the Receive WQE has been accessed.0x0 */ + u32 rsvd : 3; + u32 rq_mtt_prefetch_sge_idx : 4; +#else + u32 rq_mtt_prefetch_sge_idx : 4; + u32 rsvd : 3; + u32 rq_curt_wqe_status : 1; + u32 rq_curt_sge_last : 1; + u32 rq_curt_sge_used : 1; + u32 rq_curt_sge_dsgl : 1; + u32 rq_curt_sge_dbuff_gpa_vld : 1; + u32 rq_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_curt_sge_remain_len : 17; + u32 rq_curt_sge_meta_lkey : 3; + u32 rsvd1 : 1; + u32 rq_curt_sge_dsgl : 1; + u32 rq_curt_sge_used : 1; + u32 rq_curt_sge_last : 1; + + u32 rq_curt_meta_used : 1; + u32 rq_curt_meta_last : 1; + u32 rq_curt_meta_vld : 1; + u32 rq_prefetch_thread_num : 2; + u32 rq_curt_meta_lkey : 3; +#else + + u32 rq_curt_meta_lkey : 3; + u32 rq_prefetch_thread_num : 2; + u32 rq_curt_meta_vld : 1; + u32 rq_curt_meta_last : 1; + u32 rq_curt_meta_used : 1; + + u32 rq_curt_sge_last : 1; + u32 rq_curt_sge_used : 1; + u32 rq_curt_sge_dsgl : 1; + u32 rsvd1 : 1; + u32 rq_curt_sge_meta_lkey : 3; + u32 rq_curt_sge_remain_len : 17; +#endif + } bs_dsgl; + u32 value; + } dw13; + + /* DW14 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_prefetch_thread_num : 2; + u32 rq_mtt_prefetch_cline_num : 4; + u32 rq_mtt_prefetch_cline_ptr : 6; + u32 rq_mtt_prefetch_finish : 1; + u32 rsvd : 3; + u32 rq_mtt_prefetch_wqe_ci : 16; +#else + u32 rq_mtt_prefetch_wqe_ci : 16; + u32 rsvd : 3; + u32 rq_mtt_prefetch_finish : 1; + u32 rq_mtt_prefetch_cline_ptr : 6; + u32 rq_mtt_prefetch_cline_num : 4; + u32 rq_prefetch_thread_num : 2; +#endif + } bs; + struct { + } bc_c; + u32 value; + } dw14; + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_wqe_prefetch_maxnum : 3; + u32 rq_wqe_prefetch_minnum : 3; + u32 rq_mtt_prefetch_maxwqe : 3; + u32 rq_mtt_prefetch_maxlen0 : 2; + u32 rq_mtt_prefetch_maxlen1 : 2; + u32 rq_curt_sge_idx : 4; + u32 rsvd : 11; + u32 rq_load_next_mtt : 1; + u32 rq_load_wqe : 1; + u32 rq_load_curt_mtt : 1; + u32 rq_load_dbuff : 1; +#else + u32 rq_load_dbuff : 1; + u32 rq_load_curt_mtt : 1; + u32 rq_load_wqe : 1; + u32 rq_load_next_mtt : 1; + u32 rsvd : 11; + u32 rq_curt_sge_idx : 4; /* The SGE index of current accessed WQE.0x0 */ + u32 rq_mtt_prefetch_maxlen1 : 2; + u32 rq_mtt_prefetch_maxlen0 : 2; + u32 rq_mtt_prefetch_maxwqe : 3; + u32 rq_wqe_prefetch_minnum : 3; + u32 rq_wqe_prefetch_maxnum : 3; +#endif + } bs; + u32 value; + } dw15; +} chip_seg_rqc_s; + +/* SRQ info in QPC */ +struct chip_seg_srqc { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_pd : 18; + u32 rsvd : 2; + u32 srq_wqebb_size : 3; + u32 srq_page_size : 4; + u32 srq_size : 5; +#else + u32 srq_size : 5; + u32 srq_page_size : 4; + u32 srq_wqebb_size : 3; /* Shared Receive WQE Basic Block (WQEBB) size in bytes is + * (2^rq_srq_wqebb_size)*16B. The minimum size is 32B and + * the values 0, 4, 5, 6, 7 are reserved. + * This field is updated by SRQC.srq_wqebb_size. + * 0x0 */ + u32 rsvd : 2; + u32 srq_pd : 18; /* bit[17:00]Protection Domain. If the QP is a XRC transport service type, + * this filed should be updated by the "srq_pd" in the SRQ context + * pointed by XRCSRQ; else this field is updated by the "srq_pd" in the + * SRQ context associated with the QP. + * The following five Protection Domains have same configuration value: + * QCC.rc_pd, SQC.sq_pd, SQAC.sq_pd, RQC.rq_pd and RRWC.rrw_pd. + * 0x0 */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_so_ro : 2; + u32 srq_dma_attr_idx : 6; + u32 srq_rkey_en : 1; + u32 srq_signature : 3; + u32 srq_cqn : 20; +#else + u32 srq_cqn : 20; /* bit[19:00] Receive Queue completions are to be reported to this CQ number. + * If the QP is a XRC transport service type, this filed should be updated + * by the "srq_xrc_cqn" in the SRQ context pointed by XRCSRQ; else this + * field is configured by the driver. + * Configured by Driver */ + u32 srq_signature : 3; + u32 srq_rkey_en : 1; + u32 srq_dma_attr_idx : 6; /* bit[05:00] */ + u32 srq_so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the + * DMA operation. This field is only valid when processing SRQ's WQEs. + * 2'b00: Strict Ordering; + * 2'b01: Relaxed Ordering; + * 2'b10: ID Based Ordering; + * 2'b11: Both Relaxed Ordering and ID Based Ordering. + * This field is updated by SRQC.srq_so_ro. + * 0x0 */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_state : 4; + u32 rsvd2 : 4; + u32 srqn : 18; + u32 rsvd1 : 5; + u32 srq_en : 1; +#else + u32 srq_en : 1; /* If set, indicates it should use SRQ as the receive queue. + * Configured by Driver */ + u32 rsvd1 : 5; + u32 srqn : 18; /* SRQ number. If the QP is a XRC transport service type, this + * filed should be updated by the XRCSRQ; else this field is configured by the driver. + * Configured by Driver */ + u32 rsvd2 : 4; + u32 srq_state : 4; /* Receive Queue State. + * 0x0: hardware has no access right;0x1: error;0xf: ok.Other: reserved. + * 0x0 */ +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 state : 4; + u32 container_sz : 2; + u32 container_en : 1; + u32 ep : 3; + u32 cos : 3; + u32 rq_srqn : 18; + u32 rq_srq_en : 1; +#else + u32 rq_srq_en : 1; + u32 rq_srqn : 18; + u32 cos : 3; + u32 ep : 3; + u32 container_en : 1; + u32 container_sz : 2; + u32 state : 4; +#endif + } bs_c; + + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 srq_xrcd : 16; +#else + u32 srq_xrcd : 16; + u32 rsvd : 16; +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 rsvd_dw4; + + /* DW5 */ + u32 srq_curt_wqe_gpa_h; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_curt_wqe_gpa_l : 24; /* bit[15:00] */ + u32 rsvd : 8; +#else + u32 rsvd : 8; /* bit[15:00] */ + u32 srq_curt_wqe_gpa_l : 24; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqe_gpa : 20; + u32 gpa_vld : 1; /* bit[15:00] */ + u32 wqe_gpa_flag : 1; + u32 warth_flag : 1; + u32 last_op_wqe : 1; + u32 link_wqe : 1; + u32 rqe_cnt_th : 4; + u32 rsvd : 3; +#else + u32 rsvd : 3; + u32 rqe_cnt_th : 4; + u32 link_wqe : 1; + u32 last_op_wqe : 1; + u32 warth_flag : 1; + u32 wqe_gpa_flag : 1; + u32 gpa_vld : 1; + u32 wqe_gpa : 20; +#endif + } bs_c; + u32 value; + } dw6; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 pre_ci : 16; /* bit[15:00] */ + u32 pi : 16; +#else + u32 pi : 16; /* bit[15:00] */ + u32 pre_ci : 16; +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_curt_sge_vld : 1; + u32 srq_curt_sge_idx : 3; + u32 srq_curt_sge_lkey : 28; /* bit[27:00] */ +#else + u32 srq_curt_sge_lkey : 28; /* bit[27:00] */ + u32 srq_curt_sge_idx : 3; + u32 srq_curt_sge_vld : 1; +#endif + } bs; + u32 value; + } dw8; + + /* DW9~10 */ + union { + u64 srq_curt_sge_va; /* lo:bit[31:00],hi:bit[63:32] */ + struct { + u32 srq_curt_sge_va_hi; + u32 srq_curt_sge_va_lo; + } dw9; + }; + + /* DW11 */ + u32 srq_curt_sge_remain_len; /* bit[31:00] */ + + /* DW12 */ + u32 srq_curt_sge_dbuff_gpa_h; /* bit[63:32] */ + + /* DW13 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_curt_sge_dbuff_gpa_l : 20; + u32 srq_curt_sge_dbuff_gpa_vld : 1; + u32 srq_curt_sge_dsgl : 1; + u32 srq_curt_sge_used : 1; + u32 srq_curt_sge_last : 1; + u32 rsvd : 8; +#else + u32 rsvd : 8; + u32 srq_curt_sge_last : 1; + u32 srq_curt_sge_used : 1; + u32 srq_curt_sge_dsgl : 1; + u32 srq_curt_sge_dbuff_gpa_vld : 1; + u32 srq_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ +#endif + } bs; + u32 value; + } dw13; + + /* DW14 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_prefetch_thread_num : 2; + u32 srq_mtt_prefetch_cline_num : 4; + u32 srq_mtt_prefetch_cline_ptr : 6; + u32 srq_mtt_prefetch_finish : 1; + u32 srq_mtt_prefetch_sge_idx : 3; + u32 rsvd : 16; +#else + u32 rsvd : 16; + u32 srq_mtt_prefetch_sge_idx : 3; + u32 srq_mtt_prefetch_finish : 1; + u32 srq_mtt_prefetch_cline_ptr : 6; + u32 srq_mtt_prefetch_cline_num : 4; + u32 srq_prefetch_thread_num : 2; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 prefetch_thread_num : 2; + u32 mtt_page_size : 4; + u32 rsvd1 : 10; + u32 xrcd : 16; +#else + u32 xrcd : 16; + u32 rsvd1 : 10; + u32 mtt_page_size : 4; + u32 prefetch_thread_num : 2; +#endif + } bs_c; + + u32 value; + } dw14; + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd2 : 11; + u32 srq_mtt_prefetch_maxlen1 : 2; + u32 rsvd1 : 17; + u32 srq_load_mtt : 1; + u32 srq_load_dbuff : 1; +#else + u32 srq_load_dbuff : 1; + u32 srq_load_mtt : 1; + u32 rsvd1 : 17; + u32 srq_mtt_prefetch_maxlen1 : 2; + u32 rsvd2 : 11; +#endif + } bs; + + u32 value; + } dw15; +}; + +/* Queue Pair Common Context Format */ +typedef struct chip_seg_qpcc { + /* DW0~1 */ + union { + u64 sq_rq_l0mtt_gpa; /* hi[63:32],lo[31:03],sq_rq_gpa_sign[02:00] */ + struct { + u32 sq_rq_l0mtt_gpa_hi; + u32 sq_rq_l0mtt_gpa_lo; + } dw0; + }; + + /* DW2~3 */ + union { + u64 sq_rq_pi_record_gpa_at_hop_num; /* hi[63:32],lo[31:02],sq_rq_at_hop_num[01:00] */ + struct { + u32 sq_rq_pi_record_gpa_hi; + u32 sq_rq_pi_record_gpa_lo_at_hop_num; /* at_hop_num: bit[01:00] */ + } dw2; + }; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_base_ci : 5; + u32 rsvd : 2; + u32 rc_max_size : 3; + u32 sq_rq_mtt_page_size : 4; + u32 qp_pd : 18; +#else + u32 qp_pd : 18; + u32 sq_rq_mtt_page_size : 4; + u32 rc_max_size : 3; + u32 rsvd : 2; + u32 rq_base_ci : 5; +#endif + } bs; + u32 value; + } dw4; + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_entry_size : 2; + u32 rc_size : 4; + u32 qp_rkey_en : 1; + u32 qp_rwe : 1; + u32 qp_rae : 1; + u32 qp_rre : 1; + u32 rsvd : 1; + u32 qp_signature : 5; + u32 qp_xrcd : 16; +#else + u32 qp_xrcd : 16; + u32 qp_signature : 5; + u32 rsvd : 1; + u32 qp_rre : 1; + u32 qp_rae : 1; + u32 qp_rwe : 1; + u32 qp_rkey_en : 1; + u32 rc_size : 4; /* RDMARC table size, equals to (2^rc_size)*Entry Size. + *0x0: the depth of table is equal to 1; + *0x1: the depth of table is equal to 2; + *0x2: the depth of table is equal to 4; + *... + 0x7: the depth of table is equal to 128; + *Others: reserved. + *Configured by Driver */ + u32 rc_entry_size : 2; /* Entry size of RDMARC table in bytes is (2^rc_entry_size)*16B. + * The minimum size is 32B and the maximum size is 64B; so the values 0 and 3 are + * reserved. Configured by Driver */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_entry_prefetch_maxnum : 3; + u32 rsvd : 5; + u32 rc_page_gpa_h : 24; +#else + u32 rc_page_gpa_h : 24; /* bit[63:40] Indicates the start GPA of RDMARC table. The driver needs to allocate + * continuous physical address for the RDMARC table.Configured by Driver */ + u32 rsvd : 5; + u32 rc_entry_prefetch_maxnum : 3; /* Maximum number of prefetch Entries for RDMARC table.000: prefetch number + * equals to zero; Others: prefetch number equals to + * (2^(rc_entry_prefetch_maxnum-1)). Configured by Driver */ +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + u32 rc_page_gpa_l; /* bit[39:8] */ +} chip_seg_qpcc_s; + +/* RDMARC Context Format */ +typedef struct chip_seg_rcc { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_curt_sge_vld : 1; + u32 rsvd : 3; + u32 rc_curt_sge_rkey : 28; +#else + u32 rc_curt_sge_rkey : 28; /* bit[27:00] Indicates the R_Key of current SGE. Using rc_curt_sge_rkey[27:8] to + access the corresponding MPT.0x0 */ + u32 rsvd : 3; + u32 rc_curt_sge_vld : 1; /* Indicates current SGE information is valid. The remaining rc_curt_sge_* field are + * only valid when the rc_curt_sge_vld is asserted.1: SGE is valid;0: SGE is + * invalid. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1~2 */ + union { + u64 rc_curt_sge_va; + struct { + u32 rc_curt_sge_va_hi; + u32 rc_curt_sge_va_lo; + } dw1; + }; + + /* DW3 */ + u32 rc_curt_sge_remain_len; /* bit[31:00]Indicates the remaining memory space of current SGE.0x0 */ + + /* DW4 */ + u32 rc_curt_sge_dbuff_gpa_h; /* bit[63:32] */ + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ + u32 rc_curt_sge_dbuff_gpa_vld : 1; + u32 rc_curt_sge_dsgl : 1; + u32 rc_curt_sge_used : 1; + u32 dsgl_en : 1; + u32 rc_pi : 8; +#else + u32 rc_pi : 8; /* bit[07:00] The Producer Index (PI) of RDMARC table (Step: Entry Size).0x0 */ + u32 dsgl_en : 1; + u32 rc_curt_sge_used : 1; + u32 rc_curt_sge_dsgl : 1; + u32 rc_curt_sge_dbuff_gpa_vld : 1; /* Indicates if the "rc_curt_sge_dbuff_gpa" field is valid.1: it is + valid;0: it is invalid.0x0 */ + u32 rc_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_pd : 18; + u32 rc_signature : 3; + u32 rsvd : 3; + u32 rc_ci : 8; +#else + u32 rc_ci : 8; /* bit[07:00] The Consumer Index (CI) of RDMARC table (Step: Entry Size). */ + u32 rsvd : 3; + u32 rc_signature : 3; + u32 rc_pd : 18; /* bit[17:00] Protection Domain. If the QP is a XRC transport service type, this filed should + * be updated by the "srq_pd" in the SRQ context pointed by XRCSRQ; else this field should + * be equal to QCC.rc_pd.0x0 */ +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_state : 4; + u32 rc_rae : 1; + u32 rc_rre : 1; + u32 rsvd2 : 1; + u32 rc_mtt_prefetch_maxlen : 2; + u32 rc_prefetch_thread_num : 2; + u32 rc_load_entry : 1; + u32 rc_load_mtt : 1; + u32 rc_load_dbuff : 1; + u32 rc_mtt_prefetch_finish : 1; + u32 rc_mtt_prefetch_cline_num : 4; + u32 rsvd1 : 5; + u32 rc_prefetch_ci : 8; +#else + u32 rc_prefetch_ci : 8; + u32 rsvd1 : 5; + u32 rc_mtt_prefetch_cline_num : 4; + u32 rc_mtt_prefetch_finish : 1; + u32 rc_load_dbuff : 1; + u32 rc_load_mtt : 1; + u32 rc_load_entry : 1; + u32 rc_prefetch_thread_num : 2; + u32 rc_mtt_prefetch_maxlen : 2; + u32 rsvd2 : 1; + u32 rc_rre : 1; + u32 rc_rae : 1; + u32 rc_state : 4; +#endif + } bs; + u32 value; + } dw7; +} chip_seg_rcc_s; + +/* RQ RDMA Write Context */ +struct chip_seg_rrwc { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rrw_curt_sge_vld : 1; + u32 rsvd : 3; + u32 rrw_curt_sge_rkey : 28; +#else + u32 rrw_curt_sge_rkey : 28; /* bit[27:00] */ + u32 rsvd : 3; /* bit[30:28] */ + u32 rrw_curt_sge_vld : 1; /* bit[31] */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1~2 */ + union { + u64 rrw_curt_sge_va; /* hi:bit[63:32],lo:bit[31:00] */ + struct { + u32 rrw_curt_sge_va_hi; + u32 rrw_curt_sge_va_lo; + } dw1; + }; + + /* DW3 */ + u32 rrw_curt_sge_remain_len; /* bit[31:00] */ + + /* DW4 */ + u32 rrw_curt_sge_dbuff_gpa_h; /* bit[63:32] */ + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rrw_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ + u32 rrw_curt_sge_dbuff_gpa_vld : 1; + u32 rrw_curt_sge_dsgl : 1; + u32 rrw_curt_sge_used : 1; + u32 rsvd : 9; +#else + u32 rsvd : 9; + u32 rrw_curt_sge_used : 1; + u32 rrw_curt_sge_dsgl : 1; + u32 rrw_curt_sge_dbuff_gpa_vld : 1; + u32 rrw_curt_sge_dbuff_gpa_l : 20; /* bit[31:12] */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rrw_pd : 18; + u32 rrw_signature : 3; + u32 rsvd : 11; +#else + u32 rsvd : 11; + u32 rrw_signature : 3; + u32 rrw_pd : 18; + +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rrw_state : 4; + u32 rrw_rwe : 1; + u32 rsvd3 : 2; + u32 rrw_mtt_prefetch_maxlen : 2; + u32 rrw_prefetch_thread_num : 2; + u32 rsvd2 : 1; + u32 rrw_load_mtt : 1; + u32 rrw_load_dbuff : 1; + u32 rrw_mtt_prefetch_finish : 1; + u32 rrw_mtt_prefetch_cline_num : 4; + u32 rsvd1 : 13; +#else + u32 rsvd1 : 13; + u32 rrw_mtt_prefetch_cline_num : 4; + u32 rrw_mtt_prefetch_finish : 1; + u32 rrw_load_dbuff : 1; + u32 rrw_load_mtt : 1; + u32 rsvd2 : 1; + u32 rrw_prefetch_thread_num : 2; + u32 rrw_mtt_prefetch_maxlen : 2; + u32 rsvd3 : 2; + u32 rrw_rwe : 1; + u32 rrw_state : 4; +#endif + } bs; + u32 value; + } dw7; +}; + +/* ***************************************************************************** + Data Structure: SQPC + Description: +***************************************************************************** */ +struct chip_seg_sqpc { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_signature : 5; + u32 rsvd0 : 14; + u32 sqp_ci_on_chip : 1; + u32 sqp_wqe_size : 3; + u32 sqp_page_size : 4; + u32 sqp_size : 5; +#else + u32 sqp_size : 5; + u32 sqp_page_size : 4; + u32 sqp_wqe_size : 3; + u32 sqp_ci_on_chip : 1; + u32 rsvd0 : 14; + u32 sqp_signature : 5; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_so_ro : 2; + u32 sqp_dma_attr_idx : 6; + u32 rsvd0 : 8; + u32 sqp_ci : 16; +#else + u32 sqp_ci : 16; + u32 rsvd0 : 8; + u32 sqp_dma_attr_idx : 6; + u32 sqp_so_ro : 2; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_state : 4; + u32 rsvd0 : 12; + u32 sqp_pi : 16; +#else + u32 sqp_pi : 16; + u32 rsvd0 : 12; + u32 sqp_state : 4; +#endif + } bs; + u32 value; + } dw2; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_wqecnt_lth : 4; + u32 sqp_wqecnt_rctl_en : 1; + u32 rsvd0 : 15; + u32 sqp_load_ci : 1; + u32 sqp_load_page_gpa : 1; + u32 sqp_wqe_curt_page_vld : 1; + u32 sqp_wqe_next_page_vld : 1; + u32 sqp_wqe_curt_page_gpa_h : 8; +#else + u32 sqp_wqe_curt_page_gpa_h : 8; + u32 sqp_wqe_next_page_vld : 1; + u32 sqp_wqe_curt_page_vld : 1; + u32 sqp_load_page_gpa : 1; + u32 sqp_load_ci : 1; + u32 rsvd0 : 15; + u32 sqp_wqecnt_rctl_en : 1; + u32 sqp_wqecnt_lth : 4; +#endif + } bs; + u32 value; + } dw3; + + u32 sqp_wqe_curt_page_gpa_m; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_wqe_curt_page_gpa_l : 12; + u32 sqp_wqe_next_page_gpa_h : 20; +#else + u32 sqp_wqe_next_page_gpa_h : 20; + u32 sqp_wqe_curt_page_gpa_l : 12; +#endif + } bs; + u32 value; + } dw5; + + u32 sqp_wqe_next_page_gpa_l; + + u32 rsvd_dw7; + + u32 rsvd_dw8; + + u32 rsvd_dw9; + + u32 rsvd_dw10; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd0 : 16; + u32 sqp_prefetch_thread_num : 2; + u32 rsvd1 : 10; + u32 sqp_mtt_page_size : 4; +#else + u32 sqp_mtt_page_size : 4; + u32 rsvd1 : 10; + u32 sqp_prefetch_thread_num : 2; + u32 rsvd0 : 16; +#endif + } bs; + u32 value; + } dw11; + + u32 sqp_l0mtt_gpa_h; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_l0mtt_gpa_l : 29; + u32 sqp_gpa_sign : 3; +#else + u32 sqp_gpa_sign : 3; + u32 sqp_l0mtt_gpa_l : 29; +#endif + } bs; + u32 value; + } dw13; + + u32 sqp_pi_record_gpa_h; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sqp_pi_record_gpa_l : 30; + u32 sqp_at_hop_num : 2; +#else + u32 sqp_at_hop_num : 2; + u32 sqp_pi_record_gpa_l : 30; +#endif + } bs; + u32 value; + } dw15; +}; + +/* Queue Pair Context */ +typedef struct qpc_chip_seg { + struct chip_seg_rrwc rrwc; /* RQ RDMA Write Context (32B) */ + struct chip_seg_rcc rcc; /* RDMARDC Context (32B) */ + + struct chip_seg_sqc sqc; /* Send Queue Context (64B) */ + struct chip_seg_sqac sqac; /* Send Queue ACK Context (64B) */ + union { + struct chip_seg_rqc rqc; /* Receive Queue Context (64B) */ + struct chip_seg_srqc srqc; /* RQC Shared Receive Queue Mode(64B) */ + }; + + struct chip_seg_qpcc qpcc; /* Queue Pair Common Context (32B) */ +} qpc_chip_seg_s; + +/* Timer Section(32B) */ +struct qpc_timer_seg { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd3 : 1; + u32 tss_timer_num : 3; /* Indicate how many timers this timer section + supports:0:rsvd,X:support up to X timers */ + u32 tss_lock_flag : 1; /* Lock flag indicates whether this timer section is locked by one API or not + 1: locked 0: unlock */ + u32 tss_modify_flag : 1; /* Modify flag indicates whether this timer section has been modified by other API + without lock or not. 1: has been modified,0: has not been modified */ + u32 rsvd2 : 1; + u32 tss_close_flag : 1; /* close flag indicates this connection needs to close and this XID context will be + de-allocated by control plane; 0: not close,1: close,this timer section will be + picked off from timer wheel and issue a special time-out API to tell ucode this + context resource can be de-allocated. */ + u32 rsvd1 : 3; + u32 rsvd0 : 2; + u32 tlwi_lv : 1; /* Timer link valid, + 1: this timer section is hung in timing wheel + 0: this timer section is not hung in any timing wheel */ + u32 tlwi_timer_id : 3; /* indicate which timer is hung in timing wheel */ + u32 tlwi_wheel_id : 3; /* indicate which timing wheel this timer section is hung in */ + u32 tlwi_link_spoke : 12; /* indicate which fire spoke this timer section is hung in */ +#else + u32 tlwi_link_spoke : 12; + u32 tlwi_wheel_id : 3; + u32 tlwi_timer_id : 3; + u32 tlwi_lv : 1; + u32 rsvd0 : 2; + u32 rsvd1 : 3; + + u32 tss_cl : 1; + u32 rsvd2 : 1; + u32 tss_modify_flag : 1; + u32 tss_lock_flag : 1; + u32 tss_timer_num : 3; + u32 rsvd3 : 1; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + u32 pre_link_ptr0; /* Previous link pointer, data structure is referred to timer pointer data structure */ + + /* DW2 */ + u32 pre_link_ptr1; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 pre_link_ptr : 8; + u32 next_link_ptr : 24; +#else + u32 next_link_ptr : 24; + u32 pre_link_ptr : 8; +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 next_link_ptr1; /* Next link pointer, data structure is referred to timer pointer data structure */ + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 next_link_ptr : 16; + u32 rsvd : 16; +#else + u32 rsvd : 16; + u32 next_link_ptr : 16; +#endif + } bs; + u32 value; + } dw5; + + u32 ts_rsvd[2]; /* reserve 2DW */ +}; + +typedef union ucode_rq_last { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_last_optype : 1; + u32 rq_last_opcode : 1; + u32 rsvd : 1; + u32 atomic_aloc_fail : 1; + u32 comm_est : 1; + u32 rnr_state : 1; + u32 err_state : 1; + u32 rq_ready_n : 1; + u32 last_msn : 24; +#else + u32 last_msn : 24; + u32 rq_ready_n : 1; + u32 err_state : 1; + u32 rnr_state : 1; + u32 comm_est : 1; + u32 atomic_aloc_fail : 1; + u32 rsvd : 1; + u32 rq_last_opcode : 1; + u32 rq_last_optype : 1; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_last_op : 2; + u32 rsv_com : 30; +#else + u32 rsv_com : 30; + u32 rq_last_op : 2; +#endif + } bs1; + + u32 value; +} ucode_rq_last_u; + +/* * sq ack ctx */ +typedef struct ucode_sq_ack_ctx { + /* DW12 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 time_interval : 6; + u32 timestamp : 26; +#else + u32 timestamp : 26; + u32 time_interval : 6; // timer update interval +#endif + } bs; + u32 value; + } dw12; + + /* DW13 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 last_md_nrcv : 1; + u32 nof_sw : 1; + u32 rx_port : 3; + u32 credit_nlimit : 1; + u32 rsvd : 2; + u32 lsn : 24; +#else + u32 lsn : 24; + u32 rsvd : 2; + u32 credit_nlimit : 1; + u32 rx_port : 3; + u32 nof_sw : 1; + u32 last_md_nrcv : 1; // last metadata flag in dif +#endif + } bs; + u32 value; + } dw13; + + /* DW14 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 timer_type : 1; + u32 timer_en : 1; + u32 rnr_retry_cnt : 3; + u32 retry_cnt : 3; + u32 sq_rcv_psn : 24; +#else + u32 sq_rcv_psn : 24; + u32 retry_cnt : 3; + u32 rnr_retry_cnt : 3; + u32 timer_en : 1; + u32 timer_type : 1; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsv_com : 2; + u32 retry_reset : 6; + u32 rsv_com1 : 24; +#else + u32 rsv_com1 : 24; + u32 retry_reset : 6; + u32 rsv_com : 2; +#endif + } bs1; + u32 value; + } dw14; + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 next_rdat : 1; + u32 sq_db : 1; + u32 rnr_state : 1; + u32 retry_state : 1; + u32 rsvd : 2; + u32 err_state : 1; + u32 sqa_ready_n : 1; + u32 sq_rcv_msn : 24; +#else + u32 sq_rcv_msn : 24; + u32 sqa_ready_n : 1; + u32 err_state : 1; + u32 rsvd : 2; + u32 retry_state : 1; + u32 rnr_state : 1; + u32 sq_db : 1; + u32 next_rdat : 1; +#endif + } bs; + u32 value; + } dw15; + + /* DW16 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sra_ack_cnt : 8; + u32 wqe_first_psn : 24; +#else + u32 wqe_first_psn : 24; + u32 sra_ack_cnt : 8; +#endif + } bs; + u32 value; + } dw16; + + /* DW17 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 lcn : 8; + u32 max_fwd_psn : 24; +#else + u32 max_fwd_psn : 24; + u32 lcn : 8; +#endif + } bs; + u32 value; + } dw18; + + /* DW18 */ + u32 sq_rcv_len; + + /* DW19 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 18; + u32 task_tag : 14; +#else + u32 task_tag : 14; + u32 rsvd : 18; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqe2host_ci : 8; + u32 last_nak_psn : 24; +#else + u32 last_nak_psn : 24; + u32 wqe2host_ci : 8; +#endif + } nofaa; + u32 value; + } dw17; +} ucode_sq_ack_ctx_s; + +typedef struct ucode_sq_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sra_cnt : 8; + u32 next_send_psn : 24; +#else + u32 next_send_psn : 24; /* Initial value of the driver in BTH Packet Sequence Number(initial)RTR2RTS mode */ + u32 sra_cnt : 8; /* Initiator depth count value */ +#endif + } bs; + u32 value; + } dw8; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 lcn : 8; + u32 ssn : 24; +#else + u32 ssn : 24; + u32 lcn : 8; +#endif + } bs; + u32 value; + } dw9; + + /* DW2 */ + u32 send_left_len; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 17; + u32 last_md_nst : 1; + u32 task_tag : 14; +#else + u32 task_tag : 14; + u32 last_md_nst : 1; + u32 rsvd : 17; +#endif + } dif; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 10; + u32 dci_state : 2; + u32 drctn : 20; +#else + u32 drctn : 20; + u32 dci_state : 2; + u32 rsvd : 10; +#endif + } drc; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sticky : 1; + u32 work_queue : 2; + u32 wqe2host_pi : 8; + u32 rsvd : 21; +#else + u32 rsvd : 21; + u32 wqe2host_pi : 8; + u32 work_queue : 2; + u32 sticky : 1; +#endif + } nofaa; + u8 vbs_sq[4]; + u32 value; + } dw11; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sync : 1; + u32 credit_ignore : 1; + u32 err_state : 1; + u32 sq_ready_n : 1; + u32 sq_flush_wait : 1; + u32 port_err : 1; + u32 ud_last_time : 26; +#else + u32 ud_last_time : 26; + u32 port_err : 1; + u32 sq_flush_wait : 1; + u32 sq_ready_n : 1; + u32 err_state : 1; + u32 credit_ignore : 1; + u32 sync : 1; +#endif + } bs; + u32 value; + } dw12; + + ucode_sq_ack_ctx_s ack_ctx; +} ucode_sq_ctx_s; + +/* * rq ack ctx */ +typedef struct ucode_rq_ack_ctx { + /* DW24 */ + u32 rq_rsp_left; + + /* DW25 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rra_ack_cnt : 8; + u32 next_ack_psn : 24; +#else + u32 next_ack_psn : 24; + u32 rra_ack_cnt : 8; +#endif + } bs; + u32 value; + } dw25; + + /* DW26 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rqa_last_optype : 1; + u32 port_err : 1; + u32 nxt_rdat : 1; + u32 repeat_flag : 1; + u32 nak_rsp : 1; + u32 err_state : 1; + u32 rqa_ready_n : 1; + u32 remote_db : 1; + u32 last_ackpsn_low : 8; + u32 atomic_aloc_fail : 1; + u32 rq_flush_wait : 1; + u32 last_wqe_reached : 1; + u32 rq_recv_psn_cnt : 5; + u32 syndrome : 8; +#else + u32 syndrome : 8; + u32 rq_recv_psn_cnt : 5; + u32 last_wqe_reached : 1; + u32 rq_flush_wait : 1; + u32 atomic_aloc_fail : 1; + u32 last_ackpsn_low : 8; + u32 remote_db : 1; + u32 rqa_ready_n : 1; + u32 err_state : 1; + u32 nak_rsp : 1; + u32 repeat_flag : 1; + u32 nxt_rdat : 1; + u32 port_err : 1; + u32 rqa_last_optype : 1; +#endif + } bs; + + u32 value; + } dw26; + + /* DW27 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 1; + u32 credit : 7; + u32 msn : 24; +#else + u32 msn : 24; + u32 credit : 7; + u32 rsvd : 1; +#endif + } bs; + u32 value; + } dw27; + + /* DW28 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 32; +#else + u32 rsvd : 32; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd0 : 3; + u32 back_len : 13; + u32 last_md_nst : 1; + u32 rsvd1 : 1; + u32 task_tag : 14; +#else + u32 task_tag : 14; + u32 rsvd1 : 1; + u32 last_md_nst : 1; + u32 back_len : 13; + u32 rsvd0 : 3; +#endif + } dif; + u32 value; + } dw28; +} ucode_rq_ack_ctx_s; + +typedef struct ucode_rq_ctx { + /* DW20 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rra_cnt : 8; + u32 next_rcv_psn : 24; +#else + u32 next_rcv_psn : 24; + u32 rra_cnt : 8; +#endif + } bs; + u32 value; + } dw20; + + /* DW21 */ + union { + u32 rq_rcv_len; + } dw21; + + /* DW22 */ + ucode_rq_last_u dw22; + + /* DW23 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 last_md_nrcv : 1; + u32 rsvd : 7; + u32 mpt_index : 24; +#else + u32 mpt_index : 24; + u32 rsvd : 7; + u32 last_md_nrcv : 1; // last metadata flag in dif +#endif + } bs; + u32 value; + } dw23; + /* DW24 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 18; + u32 task_tag : 14; +#else + u32 task_tag : 14; + u32 rsvd : 18; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ctrl_rcv : 2; + u32 repeat : 1; + u32 rsvd : 29; +#else + u32 rsvd : 29; + u32 repeat : 1; + u32 ctrl_rcv : 2; +#endif + } nofaa; + u32 value; + } dw24; + /* DW24~27 */ + ucode_rq_ack_ctx_s ack_ctx; +} ucode_rq_ctx_s; + +typedef struct ucode_dcqcn_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cnp_flag : 1; + u32 f_cnt : 3; + u32 cnp_receive : 1; + u32 ai_cnt : 3; + u32 reinq_times : 12; + u32 rsvd : 2; + u32 alpha : 10; +#else + u32 alpha : 10; + u32 rsvd : 2; + u32 reinq_times : 12; + u32 ai_cnt : 3; + u32 cnp_receive : 1; + u32 f_cnt : 3; + u32 cnp_flag : 1; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 token_period : 4; + u32 rate_period : 4; + u32 cur_rate : 24; +#else + u32 cur_rate : 24; + u32 rate_period : 4; + u32 token_period : 4; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 target_rate : 24; +#else + u32 target_rate : 24; + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw2; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 token : 24; /* valid token */ +#else + u32 token : 24; + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw3; + + u32 rcnp_timestamp; /* last receive cnp */ + u32 alpha_timestamp; /* last update alpha */ + u32 rate_timestamp; /* last update rate */ +} ucode_dcqcn_ctx_s; + +typedef struct ucode_common_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsp_ready_n : 1; + u32 req_ready_n : 1; + u32 rq_flush : 1; + u32 sq_flush : 1; + u32 rsvd : 3; + u32 ccf_appid : 3; + u32 port : 2; + u32 ulp_type : 4; /* for user plugin extension */ + u32 fake : 1; + u32 cq_ovl_flag : 1; /* Cq overflow Indicates whether WQ CATAS is generated. */ + u32 sqd_event : 1; + u32 vf_id : 13; +#else + u32 vf_id : 13; + u32 sqd_event : 1; + u32 cq_ovl_flag : 1; /* Cq overflow Indicates whether WQ CATAS is generated. */ + u32 fake : 1; + u32 ulp_type : 4; + u32 port : 2; + u32 ccf_appid : 3; + u32 rsvd : 3; + u32 sq_flush : 1; + u32 rq_flush : 1; + u32 req_ready_n : 1; + u32 rsp_ready_n : 1; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 unit_time : 8; + u32 rsvd : 11; + u32 dst_vfid : 13; +#else + u32 dst_vfid : 13; + u32 rsvd : 11; + u32 unit_time : 8; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 14; + u32 pd : 18; +#else + u32 pd : 18; + u32 rsvd : 14; +#endif + } ud; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 12; + u32 drcin : 20; +#else + u32 drcin : 20; + u32 rsvd : 12; +#endif + } drct; + u32 drci_drc_key_h; + u32 value; + } dw1; + + /* DW2 */ + union { + u32 qkey; + u32 drci_drc_key_l; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cnp_tx_filter_ts : 12; + u32 rq_cqn : 20; +#else + u32 rq_cqn : 20; + u32 cnp_tx_filter_ts : 12; +#endif + } bs; + u32 value; + } dw3; +} ucode_common_ctx_s; + +typedef struct drv_ucode_all_info { + /* DW0~DW4 */ + ucode_common_ctx_s common; + + /* DW5~DW18 */ + ucode_sq_ctx_s sq_ctx; + + /* DW19~DW27 */ + ucode_rq_ctx_s rq_ctx; +} drv_ucode_all_info; + +typedef struct drv_path_info { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 bond_tx_hash_value : 16; + u32 dmac_h16 : 16; +#else + u32 dmac_h16 : 16; + u32 bond_tx_hash_value : 16; +#endif + } bs; + u32 value; + } dw0; + + u32 dmac_l32; + + /* DW2~5 */ + u8 dgid[16]; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ext_mtu : 1; + u32 ext_md : 1; + u32 rcq_lb1 : 1; + u32 scq_lb1 : 1; + u32 tclass : 8; + u32 flow_label : 20; +#else + u32 flow_label : 20; /* GRH flow lable */ + u32 tclass : 8; + u32 scq_lb1 : 1; + u32 rcq_lb1 : 1; + u32 ext_md : 1; + u32 ext_mtu : 1; +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sl : 3; + u32 loop : 1; + u32 udp_src_port : 8; + u32 rsvd : 4; + u32 base_sgid_n : 1; + u32 sgid_index : 7; + u32 hoplmt : 8; +#else + u32 hoplmt : 8; + u32 sgid_index : 7; + u32 base_sgid_n : 1; + u32 rsvd : 4; + u32 udp_src_port : 8; + u32 loop : 1; + u32 sl : 3; +#endif + } bs; + u32 value; + } dw7; +} drv_path_info_s; + +/* Driver use segment ,16B */ +typedef struct qpc_drv_seg { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 service_type : 3; + u32 fre : 1; + u32 state : 4; + u32 dest_qp : 24; +#else + u32 dest_qp : 24; /* Destination QP number, which is extended to 24 bits in consideration of interconnection + with commercial devices. */ + u32 state : 4; /* QP state 0000:RST 0001:INIT 0010:RTR 0011:RTS 0100:SQEr 0101:SQD(Drained) 0110:ERR + 0111:Draining This field is not modified for the *1XXX:Reserved driver verbs and is + modified by the microcode based on the command type. */ + u32 fre : 1; /* Indicates whether the local FRPMR is enabled. */ + u32 service_type : 3; /* Transmission Type + * 000:RC + * 001:UC + * 010:RD + * 011 UD + * 101:XRC + * Other:Reserved + */ +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_flag : 1; + u32 dif_en : 1; + u32 datagram : 1; + u32 local_trans : 1; + u32 srq_en : 1; + u32 drc : 1; + u32 vroce_en : 1; + u32 rsvd : 1; + u32 xrc_vld : 1; + u32 ep : 4; + u32 db_cos : 3; + u32 host_oqid : 16; +#else + u32 host_oqid : 16; + u32 db_cos : 3; + u32 ep : 4; + u32 xrc_vld : 1; + u32 rsvd : 1; + u32 vroce_en : 1; + u32 drc : 1; + u32 srq_en : 1; + u32 local_trans : 1; + u32 datagram : 1; + u32 dif_en : 1; + u32 rc_flag : 1; /* Reliable service : */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ack_to : 5; + u32 min_rnr_nak : 5; /* NAK code of RNR. This parameter is mandatory when INIT2RNR and + RTR2RTS\SQE2RTS\SQD2SQD\SQD2RTS is optional. */ + u32 rnr_retry_limit : 3; /* The maximum number of RNR retransmissions is 7. The value 7 indicates that the + maximum number of retransmissions is 7, and the value 0 indicates that the + retransmission is not performed. */ + u32 to_retry_limit : 3; /* Number of ACK retransmissions. The value 7 indicates unlimited times, and the + value 0 indicates no retransmission. */ + u32 ack_timer_step : 6; + u32 rsvd : 2; + u32 base_mtu_n : 1; + u32 mtu_code : 4; + u32 pmtu : 3; +#else + u32 pmtu : 3; + u32 mtu_code : 4; + u32 base_mtu_n : 1; + u32 rsvd : 2; + u32 ack_timer_step : 6; + u32 to_retry_limit : 3; + u32 rnr_retry_limit : 3; + u32 min_rnr_nak : 5; + u32 ack_to : 5; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 com_rsvd0 : 10; + u32 retry_reset : 6; + u32 com_rsvd : 16; +#else + u32 com_rsvd : 16; + u32 retry_reset : 6; + u32 com_rsvd0 : 10; +#endif + } bs1; + + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sra_max : 3; /* The maximum value of initiator depth is 128. */ + u32 rra_max : 3; /* The maximum value of responser resource is 128. */ + u32 invalid_credit : 1; /* Indicates whether the RQ disables the credit. The SRQ is disabled by default and + must be set to 1. */ + u32 ackto_overstep : 1; + u32 rsvd : 2; + u32 srq_container : 1; + u32 dsgl : 1; + u32 local_qp : 20; /* Local QP number */ +#else + u32 local_qp : 20; + u32 dsgl : 1; + u32 srq_container : 1; + u32 rsvd : 2; + u32 ackto_overstep : 1; + u32 invalid_credit : 1; + u32 rra_max : 3; + u32 sra_max : 3; +#endif + } bs; + u32 value; + } dw3; +} qpc_drv_seg_s; + +/* QPC Struct */ +typedef struct qpc_sw_seg { + /* driver seg, DW0 ~ DW3 */ + qpc_drv_seg_s drv_seg; + + /* path seg, DW4 ~ DW11 */ + drv_path_info_s path_seg; + + /* 112B(DW12~DW39) */ + drv_ucode_all_info ucode_seg; + + /* 32B(DW40~DW47) */ + ucode_ext_ctx_s ext_seg; +} qpc_sw_seg_s; + +/* QPC Struct */ +typedef struct roce_qp_context { + struct qpc_chip_seg chip_seg; + struct qpc_timer_seg timer_seg; + struct qpc_sw_seg sw_seg; +} roce_qp_context_s; + +typedef struct roce_aa_qp_context { + struct qpc_chip_seg chip_seg; + struct qpc_timer_seg timer_seg; + struct qpc_sw_seg sw_seg; + struct ucode_nofaa_ctx nofaa; +} roce_aa_qp_context_s; + +/* *QPC Format end */ + +/* * SRQC Format start */ +typedef struct roce_srq_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 pdn : 18; /* Protection Domain. */ + u32 lth_pre_en : 1; + u32 pcnt_on_chip : 1; /* If set, the producer counter of Shared Receive Queue + is stored in the chip, the counter is absolute value. */ + u32 wqebb_size : 3; /* Shared Receive WQE Basic Block (WQEBB) size in bytes is (2^rq_wqebb_size)*16B. + The minimum size is 32B and the values 0, 4, 5, 6, 7 are reserved */ + u32 page_size : 4; /* Page size of SRQ, equals to (2^srq_page_size)*4KB */ + u32 size : 5; /* Shared Receive Queue size, equals to (2^srq_size)*WQEBB, + the maximum SRQ size is 16K WQEs, so this field doesn't exceed 14. */ +#else + u32 size : 5; /* Shared Receive Queue size, equals to (2^srq_size)*WQEBB, + the maximum SRQ size is 16K WQEs, so this field doesn't exceed 14. */ + u32 page_size : 4; /* Page size of SRQ, equals to (2^srq_page_size)*4KB */ + u32 wqebb_size : 3; /* Shared Receive WQE Basic Block (WQEBB) size in bytes is (2^rq_wqebb_size)*16B. + The minimum size is 32B and the values 0, 4, 5, 6, 7 are reserved */ + u32 pcnt_on_chip : 1; /* If set, the producer counter of Shared Receive Queue + is stored in the chip, the counter is absolute value. */ + u32 lth_pre_en : 1; + u32 pdn : 18; /* Protection Domain. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + This field is only valid when processing SRQ's WQEs. + 2'b00: Strict Ordering; + 2'b01: Relaxed Ordering; + 2'b10: ID Based Ordering; + 2'b11: Both Relaxed Ordering and ID Based Ordering. */ + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + This filed is only valid when processing SRQ's WQEs. */ + u32 rkey_en : 1; + u32 srq_wqe_check_en : 1; + u32 rsvd : 2; + u32 xrc_cqn : 20; /* Completion Queue to report XRC messages directed to this SRQ (XRC only) */ +#else + u32 xrc_cqn : 20; /* Completion Queue to report XRC messages directed to this SRQ (XRC only) */ + u32 rsvd : 2; + u32 srq_wqe_check_en : 1; + u32 rkey_en : 1; + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + This filed is only valid when processing SRQ's WQEs. */ + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + This field is only valid when processing SRQ's WQEs. + 2'b00: Strict Ordering; + 2'b01: Relaxed Ordering; + 2'b10: ID Based Ordering; + 2'b11: Both Relaxed Ordering and ID Based Ordering. */ +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + This field is only valid when processing SRQ's WQEs. + 2'b00: Strict Ordering; + 2'b01: Relaxed Ordering; + 2'b10: ID Based Ordering; + 2'b11: Both Relaxed Ordering and ID Based Ordering. */ + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + This filed is only valid when processing SRQ's WQEs. */ + u32 rkey_en : 1; + u32 xrc_cqn2 : 7; + u32 ccnt : 16; +#else + u32 ccnt : 16; + u32 xrc_cqn2 : 7; + u32 rkey_en : 1; + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + This filed is only valid when processing SRQ's WQEs. */ + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + This field is only valid when processing SRQ's WQEs. + 2'b00: Strict Ordering; + 2'b01: Relaxed Ordering; + 2'b10: ID Based Ordering; + 2'b11: Both Relaxed Ordering and ID Based Ordering. */ +#endif + } bs_c; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 state : 4; /* SRQ status. + 0x0: hardware has no access right; + 0x1: error; + 0xf: ok. + Other: reserved. */ + u32 rsvd2 : 2; + u32 container_en : 1; + u32 ep : 3; + u32 cos : 3; + u32 rsvd1 : 1; + u32 srqn : 18; /* SRQ number. */ +#else + u32 srqn : 18; /* SRQ number. */ + u32 rsvd1 : 1; + u32 cos : 3; + u32 ep : 3; + u32 container_en : 1; + u32 rsvd2 : 2; + u32 state : 4; /* SRQ status. + 0x0: hardware has no access right; + 0x1: error; + 0xf: ok. + Other: reserved. */ +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 state : 4; /* SRQ status. + 0x0: hardware has no access right; + 0x1: error; + 0xf: ok. + Other: reserved. */ + u32 container_size : 2; /* 0:15 normal + 1 link wqe; 1:7 normal + 1 linkwqe 2:3normal + 1 linkwqe 3:1 + normal + 1 linkwqe */ + u32 container_en : 1; + u32 xrc_cqn1 : 3; + u32 warn_th : 4; /* warn thresthod */ + u32 srqn : 18; /* SRQ number. */ +#else + u32 srqn : 18; /* SRQ number. */ + u32 warn_th : 4; + u32 xrc_cqn1 : 3; + u32 container_en : 1; + u32 container_size : 2; /* 0:15 normal + 1 link wqe; 1:7 normal + 1 linkwqe 2:3normal + 1 linkwqe 3:1 + normal + 1 linkwqe */ + u32 state : 4; /* SRQ status. + 0x0: hardware has no access right; + 0x1: error; + 0xf: ok. + Other: reserved. */ +#endif + } bs_c; + + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 lth : 16; /* Limit Threshold. If the "srq_lth" is not zero, and the "srq_wqe_cnt" + drops below the "srq_lth" when a WQE is de-queued from the SRQ, then an SRQ + limit event is fired and the "srq_lth" is set to zero. */ + u32 xrcd : 16; /* The Scalable RC Domain. The received message can be served only if the XRC + Domain of the transport QP of received message matches this field. */ +#else + u32 xrcd : 16; /* The Scalable RC Domain. The received message can be served only if the XRC + Domain of the transport QP of received message matches this field. */ + u32 lth : 16; /* Limit Threshold. If the "srq_lth" is not zero, and the "srq_wqe_cnt" + drops below the "srq_lth" when a WQE is de-queued from the SRQ, then an SRQ + limit event is fired and the "srq_lth" is set to zero. */ +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 head_index : 16; /* Limit Threshold. If the "srq_lth" is not zero, and the "srq_wqe_cnt" + drops below the "srq_lth" when a WQE is de-queued from the SRQ, then an SRQ + limit event is fired and the "srq_lth" is set to zero. */ + u32 pcnt : 16; /* The Scalable RC Domain. The received message can be served only if the XRC + Domain of the transport QP of received message matches this field. */ +#else + u32 pcnt : 16; /* The Scalable RC Domain. The received message can be served only if the XRC + Domain of the transport QP of received message matches this field. */ + u32 head_index : 16; /* Limit Threshold. If the "srq_lth" is not zero, and the "srq_wqe_cnt" + drops below the "srq_lth" when a WQE is de-queued from the SRQ, then an SRQ + limit event is fired and the "srq_lth" is set to zero. */ +#endif + } bs_c; + + u32 value; + } dw3; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 pcnt : 16; /* A 16-bit counter incremented for each WQE posted to the SRQ. */ + u32 ccnt : 16; /* WQE count on the SRQ. */ +#else + u32 ccnt : 16; /* WQE count on the SRQ. */ + u32 pcnt : 16; /* A 16-bit counter incremented for each WQE posted to the SRQ. */ +#endif + } bs; + + u32 head_gpa; + + u32 value; + } dw4; + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqe_prefetch_ccnt : 16; + u32 next_wqe_idx : 16; /* The current WQE index; uses this field to get the corresponding WQE from SRQ. */ +#else + u32 next_wqe_idx : 16; /* The current WQE index; uses this field to get the corresponding WQE from SRQ. */ + u32 wqe_prefetch_ccnt : 16; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 head_gpa : 20; + u32 rsvd : 1; + u32 pcnt_on_chip : 1; + u32 xrc_cqn0 : 10; +#else + u32 xrc_cqn0 : 10; + u32 pcnt_on_chip : 1; + u32 rsvd : 1; + u32 head_gpa : 20; +#endif + } bs_c; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 head_gpa : 24; + u32 rsvd : 1; + u32 pcnt_on_chip : 1; + u32 resd : 6; /* The current WQE index; uses this field to get the corresponding WQE from SRQ. */ +#else + u32 resd : 6; + u32 pcnt_on_chip : 1; + u32 rsvd : 1; /* The current WQE index; uses this field to get the corresponding WQE from SRQ. */ + u32 head_gpa : 24; +#endif + } bs_osd; + + u32 value; + } dw5; + + /* DW6 */ + union { + u32 next_wqe_gpa; /* bit[63:32] */ + u32 pcnt_record_gpa_h; /* bit[63:32] */ + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 next_wqe_gpa : 20; + u32 next_wqe_gpa_vld : 1; + u32 load_wqe_gpa : 1; + u32 load_pcnt : 1; + u32 rsvd : 4; + u32 wqecnt_lth : 4; + u32 wqecnt_ctrl_en : 1; +#else + u32 wqecnt_ctrl_en : 1; + u32 wqecnt_lth : 4; + u32 rsvd : 4; + u32 load_pcnt : 1; + u32 load_wqe_gpa : 1; + u32 next_wqe_gpa_vld : 1; + u32 next_wqe_gpa : 20; + +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 pcnt_record_gpa_l : 30; + u32 rsvd : 2; +#else + u32 rsvd : 30; + u32 pcnt_record_gpa_l : 2; +#endif + } bs_c; + u32 value; + } dw7; + + /* DW8~9 */ + union { + u64 l0mtt_gpa; /* The GPA of Layer 0 MTT. It may point to the SRQ's buffer directly. + low 3bits srq_gpa_sign */ + struct { + u32 l0mtt_gpa_hi; + u32 l0mtt_gpa_lo; + } dw8; + }; + + /* DW10~11 */ + union { + u64 pcnt_record_gpa_at_hop_num; /* bit[63:2]:The GPA of stored producer counters of Shared Receive Queue. + bit[1:0]: Address translation hop numbers. + 0x0: the "srq_l0mtt_gpa" points to the buffer of SRQ directly. + 0x1: it need to perform one hop address translation to get the + buffer's address of SRQ; 0x2: there is two hop address translation to get + the buffer's address of SRQ; 0x3: reserved. */ + struct { + u32 pcnt_record_gpa_hi; + u32 pcnt_record_gpa_lo_at_hop_num; /* bit[1:0]: Address translation hop numbers. */ + } dw10; + + struct { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 xrcd : 16; +#else + u32 xrcd : 16; + u32 rsvd : 16; +#endif + } bs; + + u32 value; + } dw10; + + u32 dw11; + } dw10_container; + }; + + /* DW12 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqecnt_rctl : 1; /* The hardware clear it to zero when performing a SRQ PCnt updating, and driver + set it to one to indicate the hardware can performing SRQ PCnt updating. */ + u32 rsvd3 : 7; + u32 wqe_prefetch_max_num : 3; /* Maximum number of prefetch WQEBBs for SRQ. + 000: prefetch number equals to zero; + Others: prefetch number equals to (2^srq_wqe_prefetch_maxnum). */ + u32 wqe_prefetch_min_num : 3; /* Minimum number of prefetch WQEBBs for SRQ. + 000: prefetch number equals to zero; + Others: prefetch number equals to (2^(srq_wqe_prefetch_minnum-1)). + */ + u32 wqe_cache_thd_sel : 2; /* Maximum length of prefetch MTTs for SRQ. + 000: prefetch length equals to zero; + Others: prefetch length equals to + (2^(srq_mtt_prefetch_maxlen-1)*1KB). */ + u32 mtt_prefetch_maxlen : 2; + u32 rsvd2 : 5; + u32 mtt_page_size : 4; /* Page size of MTT for SRQ, equals to (2^srq_mtt_page_size)*4KB. */ + u32 rsvd1 : 4; + u32 load_wqe : 1; +#else + u32 load_wqe : 1; + u32 rsvd1 : 4; + u32 mtt_page_size : 4; /* Page size of MTT for SRQ, equals to (2^srq_mtt_page_size)*4KB. */ + u32 rsvd2 : 5; + u32 mtt_prefetch_maxlen : 2; + u32 wqe_cache_thd_sel : 2; + u32 wqe_prefetch_min_num : 3; /* Minimum number of prefetch WQEBBs for SRQ. + 000: prefetch number equals to zero; + Others: prefetch number equals to (2^(srq_wqe_prefetch_minnum-1)). + */ + u32 wqe_prefetch_max_num : 3; /* Maximum number of prefetch WQEBBs for SRQ. + 000: prefetch number equals to zero; + Others: prefetch number equals to (2^srq_wqe_prefetch_maxnum). */ + u32 rsvd3 : 7; + u32 wqecnt_rctl : 1; /* The hardware clear it to zero when performing a SRQ PCnt updating, and driver + set it to one to indicate the hardware can performing SRQ PCnt updating. */ +#endif + } bs; + u32 value; + } dw12; + + /* DW13 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 wqe_prefetch_idx : 16; /* The WQE index of prefetch MTTs operation. */ +#else + u32 wqe_prefetch_idx : 16; /* The WQE index of prefetch MTTs operation. */ + u32 rsvd : 16; +#endif + } bs; + u32 value; + } dw13; + + /* DW14 */ + u32 srq_prefetch_wqe_gpa_hi; /* bit[63:32] */ + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mtt_prefetch_wqe_gpa_lo : 20; + u32 srq_prefetch_wqe_gpa_vld : 1; + u32 rsvd : 9; + u32 srq_prefetch_thread_num : 2; +#else + u32 srq_prefetch_thread_num : 2; + u32 rsvd : 9; + u32 srq_prefetch_wqe_gpa_vld : 1; + u32 mtt_prefetch_wqe_gpa_lo : 20; /* bit[31:12] */ +#endif + } bs; + u32 value; + } dw15; +} roce_srq_context_s; + +/* *SRQC Format end */ + +typedef struct roce_ssgl_mpt_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 buf_page_size : 4; /* Page_size of the buffer */ + u32 mtt_layer_num : 3; /* Mtt level */ + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 rsvd2 : 4; + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 dif_mode : 1; + u32 rkey : 1; + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ +#else + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 rkey : 1; + u32 dif_mode : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 rsvd2 : 4; + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 mtt_layer_num : 3; /* Number of mtt levels */ + u32 buf_page_size : 4; /* Page_size of the buffer */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; /* Dma sequence preserving flag */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 ep : 3; + u32 qpn : 20; /* Qp bound to the mw. */ +#else + u32 qpn : 20; /* Qp bound to mw */ + u32 ep : 3; + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 so_ro : 2; /* Dma order-preserving flag */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ + u32 rsvd : 1; + u32 cos : 3; + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 pdn : 18; /* Pd bound to mr or mw */ +#else + u32 pdn : 18; /* Pd bound to mr or mw */ + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 cos : 3; + u32 rsvd : 1; + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mkey : 8; /* The index is not included. */ + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 page_mode : 1; + u32 fbo : 22; +#else + u32 fbo : 22; + u32 page_mode : 1; + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 mkey : 8; /* The index is not included. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; + + /* DW6~7 */ + union { + u64 length; /* Length of mr or mw */ + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw6; + }; + + /* DW8~9 */ + union { + u64 mtt_base_addr; /* Mtt base address (pa) */ + struct { + u32 mtt_base_addr_hi; /* Mtt base address (pa) upper 32 bits */ + u32 mtt_base_addr_lo; /* Lower 32 bits of mtt base address (pa) */ + } dw8; + }; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + u32 task_id; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 9; + u32 ext_mtu : 1; + u32 tp2_fst_sct : 1; + u32 smd_size : 1; /* metadata size[0]:0 is 512, 1'b1 is 4096 */ + u32 smd_type : 4; /* smd_type[3:2]:reserved. */ + u32 task_id : 16; /* This parameter is valid when SIG MR. */ +#else + u32 task_id : 16; /* This parameter is valid when SIG MR. */ + u32 smd_type : 4; /* This is sector metadata type: 2b'0x is 8B;2b'10 is [8B+56B];2b'11 is [56B+8B] */ + u32 smd_size : 1; /* metadata size[0]:0 is 512, 1'b1 is 4096 */ + u32 tp2_fst_sct : 1; + u32 ext_mtu : 1; + u32 rsvd : 9; +#endif + } dw10; + }; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 w_cmp_app_tag_msk : 16; + u32 m_cmp_app_tag_msk : 16; +#else + u32 m_cmp_app_tag_msk : 16; + u32 w_cmp_app_tag_msk : 16; +#endif + } bs; + u32 value; + } dw11; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 w_app_tag : 16; + u32 m_app_tag : 16; +#else + u32 m_app_tag : 16; + u32 w_app_tag : 16; +#endif + } bs; + u32 value; + } dw12; + + u32 m_ref_tag; + u32 w_ref_tag; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 w_dif_en : 1; /* Dif enable in the wire domain */ + u32 rx_w_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 rx_m_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 rx_dif_en : 1; /* IO_1ST_SCT 1 */ + u32 w_app_esc : 1; + u32 w_ref_esc : 1; + + u32 m_dif_en : 1; /* mem */ + u32 tx_m_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 tx_w_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 tx_dif_en : 1; /* IO_1ST_SCT 1 */ + u32 m_app_esc : 1; + u32 m_ref_esc : 1; + + u32 grd_verify : 1; /* Indicates whether to verify the guard. */ + u32 grd_ctrl : 2; /* guard tag ctrl */ + u32 m_bg_type : 1; /* The host memory is CRC(0) or IP CheckSum(1). */ + u32 w_bg_type : 1; /* Indicates whether the line is CRC(0) or IP CheckSum(1). */ + u32 grd_agm_ini_ctl : 3; /* GRD_AGM_INI_CTRL */ + + u32 ref_tag_verify : 1; /* Indicates whether to verify the ref_tag. */ + u32 ref_ctrl : 2; /* ref tag ctrl */ + u32 m_ref_tag_mode : 1; /* Obtained from mem.dif.ref_remap */ + u32 w_ref_tag_mode : 1; /* Obtained from wire.dif.ref_remap */ + u32 app_tag_verify : 1; /* Indicates whether to verify the app_tag. */ + u32 app_ctrl : 2; /* app tag ctrl */ +#else + u32 app_ctrl : 2; /* app tag ctrl */ + u32 app_tag_verify : 1; /* Indicates whether to verify the app_tag. */ + u32 w_ref_tag_mode : 1; /* Obtained from wire.dif.ref_remap */ + u32 m_ref_tag_mode : 1; /* Obtained from mem.dif.ref_remap */ + u32 ref_ctrl : 2; /* ref tag ctrl */ + u32 ref_tag_verify : 1; /* Indicates whether to verify the ref_tag. */ + + u32 grd_agm_ini_ctl : 3; /* GRD_AGM_INI_CTRL */ + u32 w_bg_type : 1; /* Is CRC(0) or IP CheckSum(1) on the line? */ + u32 m_bg_type : 1; /* The host memory is CRC(0) or IP CheckSum(1). */ + u32 grd_ctrl : 2; /* guard tag ctrl */ + u32 grd_verify : 1; /* Indicates whether to verify the guard. */ + + u32 m_ref_esc : 1; + u32 m_app_esc : 1; + u32 tx_dif_en : 1; /* IO_1ST_SCT 1 */ + u32 tx_w_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 tx_m_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 m_dif_en : 1; /* mem */ + + u32 w_ref_esc : 1; + u32 w_app_esc : 1; + u32 rx_dif_en : 1; /* IO_1ST_SCT 1 */ + u32 rx_m_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 rx_w_dif_type : 2; /* type 0 ~ 3,def:1 */ + u32 w_dif_en : 1; /* Indicates whether dif is enabled in the wire domain. */ +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u8 w_dif_ctl; + u8 m_dif_ctl; + u8 m_grd_ctl; + u8 m_ref_ctl; +#else + u8 m_ref_ctl; + u8 m_grd_ctl; + u8 m_dif_ctl; + u8 w_dif_ctl; +#endif + } ctrl; + u32 value; + } dw15; +} roce_ssgl_mpt_context_s; + +typedef struct roce_dsgl_mpt_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 buf_page_size : 4; /* Page_size of the buffer */ + u32 mtt_layer_num : 3; /* Number of mtt levels */ + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 signature : 4; + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 dif_mode : 1; + u32 rkey : 1; + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 access_bind : 1; /* Whether mr can be bound to mw */ +#else + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 rkey : 1; + u32 dif_mode : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 signature : 4; + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 mtt_layer_num : 3; /* Mtt level */ + u32 buf_page_size : 4; /* Page_size of the buffer */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; /* Dma order-preserving flag */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 ep : 3; + u32 qpn : 20; /* Qp bound to mw */ +#else + u32 qpn : 20; /* Qp bound to mw */ + u32 ep : 3; + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 so_ro : 2; /* Dma order-preserving flag */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ + u32 indirect_mr : 1; + u32 cos : 3; + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 pdn : 18; /* Pd bound to mr or mw */ +#else + u32 pdn : 18; /* Pd bound to mr or mw */ + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 cos : 3; + u32 indirect_mr : 1; + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mkey : 8; /* The index is not included. */ + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 page_mode : 1; + u32 sectfbo : 22; +#else + u32 sectfbo : 22; + u32 page_mode : 1; + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 mkey : 8; /* The index is not included. */ +#endif + } bs; + u32 value; + } dw3; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 4; + u32 data_mr_key : 28; +#else + u32 data_mr_key : 28; + u32 rsvd : 4; +#endif + } bs; + u32 value; + } dw4; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 4; + u32 mtt_offset : 28; +#else + u32 mtt_offset : 28; + u32 rsvd : 4; +#endif + } bs; + u32 value; + } dw5; + + /* DW6~DW9 */ + u32 rsvd[4]; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + u32 task_id; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 12; + u32 smd_type : 4; /* smd_type[3:2]:reserved. */ + u32 task_id : 16; /* This parameter is valid when SIG MR. */ +#else + + u32 task_id : 16; /* This parameter is valid when SIG MR. */ + u32 smd_type : 4; /* This is sector metadata type: 2b'0x is 8B;2b'10 is [8B+56B];2b'11 is [56B+8B] */ + u32 rsvd : 12; + +#endif + } dw10; + }; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 w_cmp_app_tag_msk : 16; + u32 m_cmp_app_tag_msk : 16; +#else + u32 m_cmp_app_tag_msk : 16; + u32 w_cmp_app_tag_msk : 16; +#endif + } bs; + u32 value; + } dw11; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 w_app_tag : 16; + u32 m_app_tag : 16; +#else + u32 m_app_tag : 16; /* TX: Verify ref tag domain + RX: Insert&replace ref tag domain */ + + u32 w_app_tag : 16; /* TX: Insert&replace ref tag domain + RX: Verify ref tag domain */ +#endif + } bs; + u32 value; + } dw12; + + u32 m_ref_tag; /* TX: Verify ref tag domain + RX: Insert&replace ref tag domain */ + + u32 w_ref_tag; /* TX: Insert&replace ref tag domain + RX: Verify ref tag domain */ + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 w_dif_en : 1; // Wire domain dif enable + u32 rx_w_dif_type : 2; // type 0 ~ 3,def:1 + u32 rx_m_dif_type : 2; // type 0 ~ 3,def:1 + u32 rx_dif_en : 1; // IO_1ST_SCT 1 + u32 w_app_esc : 1; + u32 w_ref_esc : 1; + + u32 m_dif_en : 1; // mem + u32 tx_m_dif_type : 2; // type 0 ~ 3,def:1 + u32 tx_w_dif_type : 2; // type 0 ~ 3,def:1 + u32 tx_dif_en : 1; // IO_1ST_SCT 1 + u32 m_app_esc : 1; + u32 m_ref_esc : 1; + + u32 grd_verify : 1; // Indicates whether to verify the guard. + u32 grd_ctrl : 2; // guard tag ctrl; ucode + u32 m_bg_type : 1; // The host memory is CRC(0) or IP CheckSum(1). + u32 w_bg_type : 1; // Indicates whether the line is CRC(0) or IP CheckSum(1). + u32 grd_agm_ini_ctl : 3; // GRD_AGM_INI_CTRL + + u32 ref_tag_verify : 1; // Indicates whether to verify the ref_tag. + u32 ref_ctrl : 2; // ref tag ctrl; ucode + u32 m_ref_tag_mode : 1; // Obtained from mem.dif.ref_remap + u32 w_ref_tag_mode : 1; // Obtained from wire.dif.ref_remap + u32 app_tag_verify : 1; // Indicates whether to verify the app_tag. + u32 app_ctrl : 2; // app tag ctrl; ucode +#else + /* REF APP CTRL segment */ + u32 app_ctrl : 2; // app tag ctrl + u32 app_tag_verify : 1; // Indicates whether to verify the app_tag. + u32 w_ref_tag_mode : 1; // Obtained from wire.dif.ref_remap + u32 m_ref_tag_mode : 1; // Obtained from mem.dif.ref_remap + u32 ref_ctrl : 2; // ref tag ctrl + u32 ref_tag_verify : 1; // Indicates whether to verify the ref_tag. + + /* GRD CTRL segment */ + u32 grd_agm_ini_ctl : 3; // GRD_AGM_INI_CTRL + u32 w_bg_type : 1; // Is CRC(0) or IP CheckSum(1) on the line? + u32 m_bg_type : 1; // The host memory is CRC(0) or IP CheckSum(1). + u32 grd_ctrl : 2; // guard tag ctrl + u32 grd_verify : 1; // Indicates whether to verify the guard. + + u32 m_ref_esc : 1; + u32 m_app_esc : 1; + u32 tx_dif_en : 1; // IO_1ST_SCT 1 + u32 tx_w_dif_type : 2; // type 0 ~ 3,def:1 + u32 tx_m_dif_type : 2; // type 0 ~ 3,def:1 + u32 m_dif_en : 1; // mem + + u32 w_ref_esc : 1; + u32 w_app_esc : 1; + u32 rx_dif_en : 1; // IO_1ST_SCT 1 + u32 rx_m_dif_type : 2; // type 0 ~ 3,def:1 + u32 rx_w_dif_type : 2; // type 0 ~ 3,def:1 + u32 w_dif_en : 1; // Dif enable in the wire domain +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u8 w_dif_ctl; + u8 m_dif_ctl; + u8 m_grd_ctl; + u8 m_ref_ctl; +#else + u8 m_ref_ctl; + u8 m_grd_ctl; + u8 m_dif_ctl; + u8 w_dif_ctl; + +#endif + } ctrl; + u32 value; + } dw15; +} roce_dsgl_mpt_context_s; + +typedef struct iw_mpt_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 buf_page_size : 4; /* Page_size of the buffer */ + u32 mtt_layer_num : 3; /* Mtt level */ + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 rsvd2 : 4; + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 rsvd1 : 1; + u32 rkey : 1; + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 access_bind : 1; /* Can mr be bound to mw? */ +#else + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 rkey : 1; + u32 rsvd1 : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 rsvd2 : 4; + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 mtt_layer_num : 3; /* Number of mtt levels */ + u32 buf_page_size : 4; /* Page_size of the buffer */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; /* Dma order-preserving flag */ + u32 dma_attr_idx : 6; /* Indicates the dma attribute index. */ + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 rsvd : 3; + u32 qpn : 20; /* Qp bound to mw */ +#else + u32 qpn : 20; /* Qp bound to mw */ + u32 rsvd : 3; + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 so_ro : 2; /* Dma order-preserving flag */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ + u32 rsvd : 4; + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 pdn : 18; /* Pd bound to mr or mw */ +#else + u32 pdn : 18; /* Pd bound to mr or mw */ + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 rsvd : 4; + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mkey : 8; /* The index is not included. */ + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 page_mode : 1; + u32 fbo : 22; +#else + u32 fbo : 22; + u32 page_mode : 1; + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 mkey : 8; /* The index is not included. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; + + /* DW6~7 */ + union { + u64 length; /* Length of mr or mw */ + + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw6; + }; + + /* DW8~9 */ + union { + u64 mtt_base_addr; /* Mtt base address (pa) */ + + struct { + u32 mtt_base_addr_hi; /* Upper 32 bits of the base address (pa) of mtt */ + u32 mtt_base_addr_lo; /* Lower 32 bits of mtt base address (pa) */ + } dw8; + }; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + }; + + /* DW11 */ + u32 mtt_sz; /* This parameter is valid when FRMR. */ + + /* DW12 ~ DW13 */ + u32 rsvd[2]; + + /* DW14 */ + u32 mw_base_addr_hi; + u32 mw_base_addr_lo; +} iw_mpt_context_s; + +/* * MPT Format end */ + +/* * CQC Format start */ +typedef struct roce_cq_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 signature : 5; + u32 last_solicited_pi : 9; + u32 ceqn_low : 5; + u32 ci_on_chip : 1; + u32 cqe_size : 3; + u32 page_size : 4; + u32 size : 5; +#else + u32 size : 5; /* Completion Queue size, equals to (2^cq_size)*CQE. + The maximum CQ size is 2^23 CQEs. */ + u32 page_size : 4; /* Page size of CQ, equals to (2^cq_page_size)*4KB. */ + u32 cqe_size : 3; /* Completion Queue Entry (CQE) size in bytes is (2^cq_cqe_size)*16B. + The minimum size is 32B and the values 0, 3, 4, 5, 6, 7 are reserved. */ + u32 ci_on_chip : 1; /* If set, the CI of Complete Queue is stored in the chip, + the counter is absolute value. */ + u32 ceqn_low : 5; /* Completion Event Queue, this CQ reports Completion Events to this CQE (cq_ceqn[04:00]) + */ + u32 last_solicited_pi : 9; /* bit[23:15] */ + u32 signature : 5; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; + u32 dma_attr_idx : 6; + u32 ci : 24; +#else + u32 ci : 24; /* The CI index of Receive Queue (Step: CQE). */ + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + This filed is only valid when processing CQ's CQEs. */ + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + This field is only valid when processing CQ's CQEs. + 2'b00: Strict Ordering; + 2'b01: Relaxed Ordering; + 2'b10: ID Based Ordering; + 2'b11: Both Relaxed Ordering and ID Based Ordering. */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 state : 4; + u32 rsvd : 1; + u32 ceqn_high : 3; + u32 pi : 24; +#else + u32 pi : 24; /* The PI index of Completion Queue (Step: CQE) */ + u32 ceqn_high : 3; /* Completion Event Queue, this CQ reports Completion Events to this CQE (cq_ceqn[07:05]) + */ + u32 rsvd : 1; + u32 state : 4; /* CQ status. + 0x0: hardware has no access right; + 0x1: CQ is error; + 0x2: CQ is overflow; + 0xf: ok. + Other: reserved. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cqecnt_lth : 4; + u32 cqecnt_rctl_en : 1; + u32 last_solicited_pi : 15; + u32 load_ci : 1; + u32 load_page_gpa : 1; + u32 cqe_cur_pg_vld : 1; + u32 cqe_next_pg_vld : 1; + u32 cqe_cur_pg_gpa_h : 8; +#else + u32 cqe_cur_pg_gpa_h : 8; /* curt_pg_gpa[63:56]bit */ + u32 cqe_next_pg_vld : 1; /* Indicates if the "cq_cqe_next_page_gpa" field is valid. + 1: it is valid; + 0: it is invalid. */ + u32 cqe_cur_pg_vld : 1; /* Indicates if the "cq_cqe_curt_page_gpa" field is valid. + 1: it is valid; + 0: it is invalid. */ + u32 load_page_gpa : 1; /* Indicates the thread is performing a prefetch for GPA of CQE page. */ + u32 load_ci : 1; + u32 last_solicited_pi : 15; /* bit[14:00] */ + u32 cqecnt_rctl_en : 1; + u32 cqecnt_lth : 4; +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 cqe_curt_pg_gpa_m; /* Indicates the page GPA of current CQ buffer's page pointed by "cq_pi". + curt_pg_gpa[55:24]bit */ + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cqe_curt_pg_gpa_l : 12; /* curt_pg_gpa[23:12]bit */ + u32 cqe_next_pg_gpa_h : 20; /* next_pg_gpa[63:44]bit */ +#else + u32 cqe_next_pg_gpa_h : 20; /* next_pg_gpa[63:44]bit */ + u32 cqe_curt_pg_gpa_l : 12; /* curt_pg_gpa[23:12]bit */ +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + u32 cqe_next_pg_gpa_l; /* Indicates the page GPA of next CQ buffer's page pointed by "cq_pi". + next_pg_gpa[43:12]bit */ + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 max_cnt : 16; /* Completion Event Moderation counters. + 0x0: interrupt moderation disabled. */ + u32 timeout : 16; /* Completion Event Moderation timer in microseconds. + 0x0: interrupt moderation disabled. */ +#else + u32 timeout : 16; /* Completion Event Moderation timer in microseconds. + 0x0: interrupt moderation disabled. */ + u32 max_cnt : 16; /* Completion Event Moderation counters. + 0x0: interrupt moderation disabled. */ +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cmd_sn : 2; + u32 arm_state : 2; + u32 rsvd : 12; + u32 cqe_cnt : 16; +#else + u32 cqe_cnt : 16; + u32 rsvd : 12; + u32 arm_state : 2; /* The CQ ARM State machine. + 0x0: idle state; + 0x1: solicited state; + 0x2: next state; + Others: reserved. */ + u32 cmd_sn : 2; /* The last received command sequence number. */ +#endif + } bs; + u32 value; + } dw8; + + /* DW9 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 timer_mode : 1; + u32 arm_timer_en : 1; + u32 solicited_cqe_en : 1; + u32 rsvd : 3; + u32 cnt_clear_en : 1; + u32 cnt_adjust_en : 1; + u32 last_notified_pi : 24; /* The last notified PI of CQ. */ +#else + u32 last_notified_pi : 24; /* The last notified PI of CQ. bit[23:00] */ + u32 cnt_adjust_en : 1; + u32 cnt_clear_en : 1; + u32 rsvd : 3; + u32 solicited_cqe_en : 1; + u32 arm_timer_en : 1; + u32 timer_mode : 1; +#endif + } bs; + u32 value; + } dw9; + + /* DW10 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 idle_max_count : 16; +#else + u32 idle_max_count : 16; + u32 rsvd : 16; +#endif + } bs; + u32 value; + } dw10; + + /* DW11 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cqecnt_rctl : 1; + u32 rsvd3 : 15; + u32 prefetch_thread_num : 2; + u32 rsvd2 : 6; + u32 ceqe_en : 1; + u32 arm_ceqe_en : 1; + u32 rsvd1 : 2; + u32 mtt_page_size : 4; +#else + u32 mtt_page_size : 4; + u32 rsvd1 : 2; + u32 arm_ceqe_en : 1; + u32 ceqe_en : 1; + u32 rsvd2 : 6; + u32 prefetch_thread_num : 2; + u32 rsvd3 : 15; + u32 cqecnt_rctl : 1; +#endif + } bs; + u32 value; + } dw11; + + /* DW12~13 */ + union { + u64 cqc_l0mtt_gpa; /* The GPA of Layer 0 MTT. It may point to the CQ's buffer directly. + low 3bits(cq_gpa_sign) */ + struct { + u32 cqc_l0mtt_gpa_hi; + u32 cqc_l0mtt_gpa_lo; + } dw12; + }; + + /* DW14 */ + union { + u64 ci_record_gpa_at_hop_num; /* The GPA of stored CI of Complete Queue. + * Address translation hop numbers. + 0x0: the "cq_l0mtt_gpa" points to the buffer of CQ directly. + 0x1: it need to perform one hop address translation to get the buffer's + address of CQ; 0x2: there is two hop address translation to get the buffer's + address of CQ; 0x3: reserved. */ + struct { + u32 ci_record_gpa_hi; + u32 ci_record_gpa_lo_at_hop_num; /* bit[1:0] Address translation hop numbers */ + } dw14; + }; + + /* timer seg info */ + struct qpc_timer_seg timer_seg; + + u32 rsvd[8]; /* The 32B is reserved, and the entire CQC is aligned with the 128B. */ +} roce_cq_context_s; +/* * CQC Format end */ + +/* * GID Format start */ +typedef struct roce_gid_context { + /* DW0~3 */ + u32 gid[4]; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 svlan : 12; /* outer vlan */ + u32 cvlan : 12; /* inner vlan */ + u32 is_vroce : 1; + u32 rsvd : 7; +#else + u32 rsvd : 7; + u32 is_vroce : 1; + u32 ppe_rsvd0 : 12; + u32 svlan : 12; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 svlan : 12; /* outer vlan */ + u32 cvlan : 12; /* inner vlan */ + u32 rsvd : 4; + u32 ip_ctrl_bmp : 4; +#else + u32 ip_ctrl_bmp : 4; + u32 rsvd : 4; + u32 ppe_rsvd0 : 12; + u32 svlan : 12; +#endif + } nofaa_master_gid; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 svlan : 12; /* outer vlan */ + u32 ppe_rsvd0 : 12; /* inner vlan */ + u32 rsvd : 1; + u32 master_gid_index : 7; +#else + u32 master_gid_index : 7; + u32 rsvd : 1; + u32 ppe_rsvd0 : 12; + u32 svlan : 12; +#endif + } nofaa_slave_gid; + + u32 value; + } dw4; + + /* DW5 */ + union { + u32 value; + } dw5; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 add_value : 6; + u32 gid_update : 1; + u32 ppe_rsvd3 : 1; + u32 outer_tag : 2; + u32 ppe_rsvd1 : 1; + u32 gid_type : 2; + u32 tunnel : 1; + u32 tag : 2; + u32 smac_hi16 : 16; +#else + u32 smac_hi16 : 16; + u32 tag : 2; + u32 tunnel : 1; // tunnel + u32 gid_type : 2; + u32 ppe_rsvd1 : 1; // outer_ip_type + u32 outer_tag : 2; // outer_tag + u32 ppe_rsvd3 : 1; // stag + u32 gid_update : 1; + u32 add_value : 6; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd_com : 8; + u32 outer_value : 3; + u32 misc_idx : 5; + u32 smac_hi16 : 16; +#else + u32 smac_hi16 : 16; + u32 misc_idx : 5; + u32 outer_value : 3; + u32 rsvd_com : 8; +#endif + } bs1; + u32 value; + } dw6; + + u32 smac_lo32; +} roce_gid_context_s; +/* * GID Format end */ + +/* * sqrq db Format start */ +typedef struct roce_sqrq_db { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 recieve_wqe_counter : 16; +#else + u32 recieve_wqe_counter : 16; + u32 rsvd : 16; +#endif +} roce_sqrq_db_s; +/* * sqrq db Format end */ + +/* * srq db Format start */ +typedef struct roce_srq_db { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 recieve_wqe_counter : 16; +#else + u32 recieve_wqe_counter : 16; + u32 rsvd : 16; +#endif +} roce_srq_db_s; +/* * srq db Format end */ + +/* * VTEP Format start */ +typedef struct roce_vtep_context { + u32 dmac_h32; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 dmac_l16 : 16; + u32 smac_h16 : 16; +#else + u32 smac_h16 : 16; + u32 dmac_l16 : 16; +#endif + } bs; + u32 value; + } dw1; + + u32 smac_l32; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 portid : 8; + u32 vni : 24; +#else + u32 vni : 24; + u32 portid : 8; +#endif + } bs; + u32 value; + } dw3; + + u32 sip[4]; // dw4 ~ 7 + u32 dip[4]; // dw8 ~ 11 + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 src_port : 16; + u32 dst_port : 16; +#else + u32 dst_port : 16; + u32 src_port : 16; +#endif + } bs; + u32 value; + } dw12; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 base_id : 8; /* vf cfg id */ + u32 cvlan : 12; + u32 svlan : 12; +#else + u32 svlan : 12; + u32 cvlan : 12; + u32 base_id : 8; +#endif + } bs; + u32 value; + } dw13; + + u32 racl_id; + + /* DW15 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 5; + u32 vm_dp_capture_en : 1; + u32 vm_dp_chk_en : 1; + u32 vm_dp_chk_invld : 1; + u32 dscp_rc : 8; + u32 dscp_ud : 8; + u32 dscp_xrc : 8; +#else + u32 dscp_xrc : 8; + u32 dscp_ud : 8; + u32 dscp_rc : 8; + u32 vm_dp_chk_invld : 1; + u32 vm_dp_chk_en : 1; + u32 vm_dp_capture_en : 1; + u32 rsvd : 5; +#endif + } bs; + u32 value; + } dw15; +} roce_vtep_context_s; +/* * vtep Format end */ + +typedef union tag_roce_qu_db_dw4 { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sub_type : 4; + u32 udf_3 : 12; + u32 rsvd0 : 8; + u32 pi : 8; +#else + u32 pi : 8; + u32 rsvd0 : 8; + u32 udf_3 : 12; + u32 sub_type : 4; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sub_type : 4; + u32 sgid_index : 7; + u32 mtu_shift : 3; /* 256B:0;512B:1;1024B:2;2048B:3;4096B:4 */ + u32 rsvd : 1; + u32 xrc_vld : 1; + u32 rsvd0 : 8; + u32 pi : 8; +#else + u32 pi : 8; + u32 rsvd0 : 8; + u32 xrc_vld : 1; + u32 rsvd : 1; + u32 mtu_shift : 3; + u32 sgid_index : 7; + u32 sub_type : 4; +#endif + } bs1; + u32 value; +} roce_qu_db_dw4_u; + +typedef struct tag_roce_cq_mtt_info { + u32 mtt_flags; /* Indicates whether to kick out cache. by queue (0) or VF(1). */ + u32 mtt_num; /* Number of cmtt, which needs to be assigned by the driver when the is kicked out by queue. */ + u32 mtt_cache_line_start; /* The driver needs to read the driver from the configuration file. */ + u32 mtt_cache_line_end; /* The driver needs to read the driver from the configuration file. */ + u32 mtt_cache_line_size; /* 0:256B,1:512B */ +} roce_xq_mtt_info_s; + +typedef struct tag_timer_section { + union { + u32 value; + struct { + u32 timer_num : 4; // last immeth+cmdlen + u32 rsvd : 9; + u32 lv : 1; + u32 link_timer_id : 3; + u32 link_wheel_id : 3; + u32 link_spoke : 12; + } bs; + } dw0; + + union { + u32 value; + struct { + u32 v : 1; // last immeth+cmdlen + u32 service_type : 5; + u32 rsvd : 9; + u32 instance_id : 5; + u32 vf : 12; + } bs; + } dw1; + union { + u32 value; + struct { + u32 xid : 20; + u32 cid : 12; + } bs; + } dw2; + union { + u32 value; + struct { + u32 cid : 8; + u32 v : 1; // last immeth+cmdlen + u32 service_type : 5; + u32 rsvd : 9; + u32 instance_id : 5; + u32 vf : 4; + } bs; + } dw3; + union { + u32 value; + struct { + u32 vf : 8; + u32 xid : 20; + u32 cid : 4; + } bs; + } dw4; + + u16 cid; + u16 te0; + u16 te1; + u16 te2; + u16 te3; + u16 te4; +} timer_section_s; + +typedef struct tag_spoke_info { + union { + u32 value; + struct { + u32 v : 1; + u32 rsvd : 19; + u32 vf : 12; + } bs; + } dw0; + + union { + u32 value; + struct { + u32 xid : 20; + u32 cid : 12; + } bs; + } dw1; + union { + u32 value; + struct { + u32 cid : 8; + u32 v : 1; // last immeth+cmdlen + u32 service_type : 5; + u32 rsvd : 9; + u32 instance_id : 5; + u32 vf : 4; + } bs; + } dw2; + union { + u32 value; + struct { + u32 vf : 8; + u32 xid : 20; + u32 cid : 4; + } bs; + } dw3; + + u16 cid; + u16 rsvd; + u32 total_cnt; + u32 scan_cnt; + u32 rsvd1; +} spoke_info_s; + +typedef struct racl_value_rsp { + u32 vni; + u32 vtep_ip; + u16 vf_id; + u8 mode; + u8 gw_mac[ETH_ADDR_LEN]; + u8 vm_mac[ETH_ADDR_LEN]; + u8 rsvd[1]; +} racl_value_rsp_s; + +typedef struct racl_value { + u32 vip; + u32 vni; + u32 vtep_ip; + + union { + struct { + u32 gw_mac_h : 16; + u32 gw_mac_m : 16; + } bs; + u32 value; + } dw3; + + union { + struct { + u32 gw_mac_l : 16; + u32 vf_id : 8; + u32 rsv0 : 7; + u32 mode : 1; + } bs; + u32 value; + } dw4; +} roce_racl_table_item_s; +#pragma pack(0) + +#endif // RDMA_CONTEXT_FORMAT_H diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/rdma_ext_ctx_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/rdma_ext_ctx_format.h new file mode 100644 index 000000000..bea6e8527 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/rdma_ext_ctx_format.h @@ -0,0 +1,382 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA common extended context. + * Create: 2021-12-30 + */ + +#ifndef RDMA_EXT_CTX_FORMAT_H +#define RDMA_EXT_CTX_FORMAT_H + +#include "roce_compile_macro.h" + +#include "roce_ccf_format.h" + +#ifdef ROCE_VBS_EN +#include "roce_vbs_format.h" +#endif + +#include "roce_dif_format.h" +/* Align each field with 4bytes. */ +#pragma pack(4) + + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +/***********************************/ +typedef struct ucode_dcc_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 back_token : 9; + u32 token : 13; + u32 alpha : 10; +#else + u32 alpha : 10; + u32 token : 13; + u32 back_token : 9; +#endif + } dcqcn; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 less_mtu_cnt : 2; + u32 alpha : 2; + u32 beta : 2; + u32 set_flag : 1; + u32 rsvd : 1; + u32 sw_wnd_fraction : 12; + u32 sw_wnd : 12; +#else + u32 sw_wnd : 12; + u32 sw_wnd_fraction : 12; + u32 rsvd : 1; + u32 set_flag : 1; + u32 beta : 2; + u32 alpha : 2; + u32 less_mtu_cnt : 2; +#endif + } ldcpw; + + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ccf_en : 1; + u32 cnp_receive : 1; + u32 cur_rate : 15; + u32 target_rate : 15; +#else + u32 target_rate : 15; + u32 cur_rate : 15; + u32 cnp_receive : 1; + u32 ccf_en : 1; +#endif + } dcqcn; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ccf_en : 1; + u32 dip_valid : 1; + u32 dip_index : 16; + u32 rsvd : 14; +#else + u32 rsvd : 14; + u32 dip_index : 16; + u32 dip_valid : 1; + u32 ccf_en : 1; +#endif + } ipqcn; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ccf_en : 1; + u32 mtu_thr_cnt : 2; + u32 rsvd : 3; + u32 sw_wnd_just_halve : 1; + u32 rr_wnd_just_halve : 1; + u32 rr_wnd_fraction : 12; + u32 rr_wnd : 12; +#else + u32 rr_wnd : 12; + u32 rr_wnd_fraction : 12; + u32 rr_wnd_just_halve : 1; + u32 sw_wnd_just_halve : 1; + u32 rsvd : 3; + u32 mtu_thr_cnt : 2; + u32 ccf_en : 1; +#endif + } ldcpw; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ccf_en : 1; + u32 rsvd : 31; +#else + u32 rsvd : 31; + u32 ccf_en : 1; +#endif + } cc_common; + + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_timestamp : 13; + u32 alpha_timestamp : 13; + u32 cal_token_l : 6; +#else + u32 cal_token_l : 6; + u32 alpha_timestamp : 13; + u32 rate_timestamp : 13; +#endif + } dcqcn; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sw_left_ce_num : 12; + u32 last_ack_event_timestamp : 20; +#else + u32 last_ack_event_timestamp : 20; + u32 sw_left_ce_num : 12; +#endif + } ldcpw; + + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rcnp_timestamp : 13; + u32 token_timestamp : 13; + u32 f_cnt : 4; + u32 cal_token_h : 2; +#else + u32 cal_token_h : 2; + u32 f_cnt : 4; + u32 token_timestamp : 13; + u32 rcnp_timestamp : 13; +#endif + } dcqcn; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wnd_ctrl_rtt : 16; + u32 rr_left_ce_num : 12; + u32 gamma : 2; + u32 eta : 2; +#else + u32 eta : 2; + u32 gamma : 2; + u32 rr_left_ce_num : 12; + u32 wnd_ctrl_rtt : 16; +#endif + } ldcpw; + + u32 value; + } dw3; +} ucode_dcc_ctx_s; + +/*************************************/ +typedef union ucode_ext_sq_ctx { + ucode_ccf_sq_ctx_s ccf_sq; + + u32 rsvd; +} ucode_ext_sq_ctx_s; + +typedef union ucode_ext_sqa_ctx { + ucode_ccf_sqa_ctx_s ccf_sqa; + + u32 rsvd[2]; +} ucode_ext_sqa_ctx_s; + +typedef union ucode_ext_rq_ctx { + ucode_ccf_rq_ctx_s ccf_rq; + u8 vbs_rq[4]; + u32 rsvd; +} ucode_ext_rq_ctx_s; + +typedef union ucode_ext_rqa_ctx { + ucode_ccf_rqa_ctx_s ccf_rqa; + + u32 rsvd; +} ucode_ext_rqa_ctx_s; + +typedef struct ucode_ext_ctx { + /* DW0 */ + ucode_ext_sq_ctx_s sq; + + /* DW1~2 */ + ucode_ext_sqa_ctx_s sqa; + + /* DW3 */ + ucode_ext_rq_ctx_s rq; + + /* DW4 */ + ucode_ext_rqa_ctx_s rqa; + + /* DW5~8 */ + ucode_dcc_ctx_s dcc; +} ucode_ext_ctx_s; + +typedef struct tag_nofaa_io_qpn_entry { + u32 rsvd : 8; + u32 io_qpn_2 : 12; + u32 io_qpn_1 : 12; +} nofaa_io_qpn_entry_s; + +typedef struct ucode_nofaa_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 admin_qp : 1; + u32 rts_bmp : 4; + u32 nof_bmp : 4; + u32 disconn : 1; + u32 rsvd : 6; + u32 cm_bmp : 16; +#else + u32 cm_bmp : 16; + u32 rsvd : 6; + u32 disconn : 1; + u32 nof_bmp : 4; + u32 rts_bmp : 4; + u32 admin_qp : 1; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 nof_vport : 2; + u32 gid_index_3 : 6; + u32 rsvd2 : 2; + u32 gid_index_2 : 6; + u32 rsvd1 : 2; + u32 gid_index_1 : 6; + u32 rsvd0 : 2; + u32 gid_index_0 : 6; +#else + u32 gid_index_0 : 6; + u32 rsvd0 : 2; + u32 gid_index_1 : 6; + u32 rsvd1 : 2; + u32 gid_index_2 : 6; + u32 rsvd2 : 2; + u32 gid_index_3 : 6; + u32 nof_vport : 2; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 io_qpn_2 : 12; + u32 io_qpn_1 : 12; +#else + u32 io_qpn_1 : 12; + u32 io_qpn_2 : 12; + u32 rsvd : 8; +#endif + } admin_q; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 admin_qpn : 20; + u32 rsvd : 4; + u32 qid : 8; +#else + u32 qid : 8; + u32 rsvd : 4; + u32 admin_qpn : 20; +#endif + } io_q; + u32 value; + } dw2; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 io_qpn_4 : 12; + u32 io_qpn_3 : 12; +#else + u32 io_qpn_3 : 12; + u32 io_qpn_4 : 12; + u32 rsvd : 8; +#endif + } admin_q; + struct { + u32 rsvd; + } io_q; + u32 value; + } dw3; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 io_qpn_6 : 12; + u32 io_qpn_5 : 12; +#else + u32 io_qpn_5 : 12; + u32 io_qpn_6 : 12; + u32 rsvd : 8; +#endif + } admin_q; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd; +#else + u32 rsvd; +#endif + } io_q; + u32 value; + } dw4; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 io_qpn_8 : 12; + u32 io_qpn_7 : 12; +#else + u32 io_qpn_7 : 12; + u32 io_qpn_8 : 12; + u32 rsvd : 8; +#endif + } admin_q; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd; +#else + u32 rsvd; +#endif + } io_q; + u32 value; + } dw5; + + u32 rsvd[2]; +} ucode_nofaa_ctx_s; + +#pragma pack(0) + +#endif // RDMA_EXT_CTX_FORMAT_H diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_ccf_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_ccf_format.h new file mode 100644 index 000000000..93f50f522 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_ccf_format.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA CC context. + * Create: 2021-12-30 + */ + +#ifndef ROCE_CCF_FORMAT_H +#define ROCE_CCF_FORMAT_H + +/* Align each field with 4bytes. */ +#pragma pack(4) + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +enum ROCE3_CCF_PARAM_ALGO_ID { + ROCE_CCF_ALGO_ID, + ROCE_DCQCN_ALGO_ID, + ROCE_HC3_2_0_ALGO_ID, + ROCE_LDCP_ALGO_ID, + ROCE_MIBO_ALGO_ID, + ROCE_BW_CTRL_ALGO_ID, + ROCE_CCF_PARAM_MAX_ID = 7 +}; +#define ROCE_IPQCN_ALGO_ID ROCE_DCQCN_ALGO_ID +#define ROCE_CCF_PARAM_INDEX_GET(vf_id, algo_id) (((vf_id) << 3) | (algo_id)) + +enum ROCE_CC_ALGO_E { + ROCE_CC_DISABLE = 0, + ROCE_CC_DCQCN_ALGO, + ROCE_CC_LDCP_ALGO, + ROCE_CC_IPQCN_ALGO, + ROCE_CC_MIBO_ALGO +}; + +#define CTX_TBL_WR_KEY_OFFSET 16 +#define CTX_TBL_CPY_BYTE_TYPE 48 + +/* *************************** EVENT *************************** */ +typedef enum dcc_event { + DCC_EVENT_NEW_FLOW = 0, + DCC_EVENT_DATA_TX = 1, + DCC_EVENT_RETRANSMIT, + DCC_EVENT_NACK, + DCC_EVENT_RTT_RESP, + DCC_EVENT_CNP_TX = 5, + DCC_EVENT_CNP_RX, + DCC_EVENT_ACK = 7, + DCC_EVENT_REPEAT_READ, + DCC_EVENT_NORMAL_READ, + DCC_EVENT_RSVD4 = 10, + DCC_EVENT_RSVD5, + DCC_EVENT_TIMER, + DCC_EVENT_RX, + DCC_EVENT_ACK_TX, + DCC_EVENT_ACK_DATA_TX = 15, + DCC_EVENT_ACK_DATA_RX, + DCC_EVENT_LESS_MTU_TX, + DCC_EVENT_LESS_MTU_RSPTX, + DCC_EVENT_UPDATE_TOKEN, + DCC_EVENT_VERBS_INIT = 20, + DCC_EVENT_VERBS_DEINIT, + DCC_EVENT_RSVD1, + DCC_EVENT_RSVD2, + DCC_EVENT_RSVD3, + + DCC_MATCH_RX_CTL = 25, + DCC_MOD_TX_SW, + DCC_MOD_TX_READ, + DCC_MOD_ACK_TX_ACK, + DCC_MOD_ACK_TX_RR, + DCC_CTR_AVA_WND = 30, + DCC_PKT_ACK_EXT, + DCC_PKT_DATA_EXT, + DCC_PKT_ACK_DATA_EXT, + DCC_PKT_ACK_EXT_RX, + DCC_PKT_DATA_EXT_RX = 35, + DCC_PKT_ACK_DATA_EXT_RX +} dcc_event_e; + +/* *************************** QPC *************************** */ +typedef struct ucode_ccf_sq_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 12; + u32 retrans_read_req : 1; + u32 retrans_mark : 1; + u32 sw_send_sn : 16; + u32 sw_wnd_timer_stat : 2; +#else + u32 sw_wnd_timer_stat : 2; + u32 sw_send_sn : 16; + u32 retrans_mark : 1; + u32 retrans_read_req : 1; + u32 rsvd : 12; +#endif + } ldcpw; + + u32 value; + } dw0; +} ucode_ccf_sq_ctx_s; + +typedef struct ucode_ccf_sqa_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 6; + u32 sw_zero_avail_wnd : 1; + u32 rr_zero_avail_wnd : 1; + u32 change2rqa_stg_cnt : 8; + u32 rr_rcv_sn : 16; +#else + u32 rr_rcv_sn : 16; + u32 change2rqa_stg_cnt : 8; + u32 rr_zero_avail_wnd : 1; + u32 sw_zero_avail_wnd : 1; + u32 rsvd : 6; +#endif + } ldcpw; + + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sw_ack_sn : 16; + u32 rr_ack_sn : 16; +#else + u32 rr_ack_sn : 16; + u32 sw_ack_sn : 16; +#endif + } ldcpw; + + u32 value; + } dw1; +} ucode_ccf_sqa_ctx_s; + +typedef struct ucode_ccf_rq_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sw_rcv_sn : 16; + u32 rcv_timestamp : 16; +#else + u32 rcv_timestamp : 16; + u32 sw_rcv_sn : 16; +#endif + } ldcpw; + + u32 value; + } dw0; +} ucode_ccf_rq_ctx_s; + +typedef struct ucode_ccf_rqa_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rr_send_sn : 16; + u32 rr_send_ce_sn : 11; + u32 rr_rsp_ack_cnt : 1; + u32 rcv_read_rsp : 1; + u32 ext_hdr_flip : 1; + u32 rr_wnd_timer_stat : 2; +#else + u32 rr_wnd_timer_stat : 2; + u32 ext_hdr_flip : 1; + u32 rcv_read_rsp : 1; + u32 rr_rsp_ack_cnt : 1; + u32 rr_send_ce_sn : 11; + u32 rr_send_sn : 16; +#endif + } ldcpw; + + u32 value; + } dw0; +} ucode_ccf_rqa_ctx_s; + +/* *************************** EXT TABLE *************************** */ +/* ccf common param tbl */ +typedef struct roce_ccf_param { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 np_enable : 8; + u32 rp_enable : 8; + u32 ecn_ver : 4; + u32 cnp_prio_enable : 1; + u32 ip_enable : 8; + u32 port_mode : 1; + u32 rsvd : 2; +#else + u32 rsvd : 2; + u32 port_mode : 1; + u32 ip_enable : 8; + u32 cnp_prio_enable : 1; + u32 ecn_ver : 4; + u32 rp_enable : 8; + u32 np_enable : 8; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cnp_cos : 3; + u32 cnp_prio : 3; + u32 ccf_appid : 8; + u32 rsvd : 18; +#else + u32 rsvd : 18; + u32 ccf_appid : 8; + u32 cnp_prio : 3; + u32 cnp_cos : 3; +#endif + } bs; + u32 value; + } dw1; + + u32 rsvd[2]; +} roce_ccf_param_s; + +typedef struct roce_dcqcn_param { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 18; + u32 flow_min_rate : 6; + u32 token_period : 8; +#else + u32 token_period : 8; + u32 flow_min_rate : 6; + u32 rsvd : 18; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_inc_period : 10; + u32 rsvd : 3; + u32 cnp_cnt_threshold : 4; + u32 alpha_dec_period : 10; + u32 alpha_threshold : 5; +#else + u32 alpha_threshold : 5; + u32 alpha_dec_period : 10; + u32 cnp_cnt_threshold : 4; + u32 rsvd : 3; + u32 rate_inc_period : 10; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_inc_period : 16; + u32 alpha_dec_period : 16; +#else + u32 alpha_dec_period : 16; + u32 rate_inc_period : 16; +#endif + } bs1; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_inc_ai : 8; + u32 rate_inc_hai : 8; + u32 rate_dec_period : 8; + u32 min_cnp_period : 8; +#else + u32 min_cnp_period : 8; + u32 rate_dec_period : 8; + u32 rate_inc_hai : 8; + u32 rate_inc_ai : 8; +#endif + } bs; + u32 value; + } dw2; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 factor_gita : 4; + u32 rt_clamp : 1; + u32 rsvd : 1; + u32 initial_alpha : 10; + u32 rate_first_set : 16; +#else + u32 rate_first_set : 16; + u32 initial_alpha : 10; + u32 rsvd : 1; + u32 rt_clamp : 1; + u32 factor_gita : 4; +#endif + } bs; + u32 value; + } dw3; +} roce_dcqcn_param_s; + +typedef struct roce_ipqcn_param { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 18; + u32 flow_min_rate : 6; + u32 token_period : 8; +#else + u32 token_period : 8; + u32 flow_min_rate : 6; + u32 rsvd : 18; +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_inc_period : 10; + u32 rsvd : 3; + u32 cnp_cnt_threshold : 4; + u32 alpha_dec_period : 10; + u32 alpha_threshold : 5; +#else + u32 alpha_threshold : 5; + u32 alpha_dec_period : 10; + u32 cnp_cnt_threshold : 4; + u32 rsvd : 3; + u32 rate_inc_period : 10; +#endif + } bs; + + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_inc_period : 16; + u32 alpha_dec_period : 16; +#else + u32 alpha_dec_period : 16; + u32 rate_inc_period : 16; +#endif + } bs1; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rate_inc_ai : 8; + u32 rate_inc_hai : 8; + u32 rate_dec_period : 8; + u32 min_cnp_period : 8; +#else + u32 min_cnp_period : 8; + u32 rate_dec_period : 8; + u32 rate_inc_hai : 8; + u32 rate_inc_ai : 8; +#endif + } bs; + u32 value; + } dw2; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 factor_gita : 4; + u32 rt_clamp : 1; + u32 rsvd : 1; + u32 initial_alpha : 10; + u32 rate_first_set : 16; +#else + u32 rate_first_set : 16; + u32 initial_alpha : 10; + u32 rsvd : 1; + u32 rt_clamp : 1; + u32 factor_gita : 4; +#endif + } bs; + u32 value; + } dw3; +} roce_ipqcn_param_s; + +typedef struct roce_ldcp_param { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 alpha : 2; + u32 beta : 2; + u32 gamma : 2; + u32 eta : 2; + u32 set_flag : 1; + u32 rsvd : 23; +#else + u32 rsvd : 23; + u32 set_flag : 1; + u32 eta : 2; + u32 gamma : 2; + u32 beta : 2; + u32 alpha : 2; +#endif + } bs; + u32 value; + } dw0; + + u32 rsvd1[3]; +} roce_ldcp_param_s; + +typedef struct ucode_dcc_ip_table_rate_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 alpha : 14; + u32 ip_rate : 18; /* cur_rate, unit:1M */ +#else + u32 ip_rate : 18; /* cur_rate, unit:1M */ + u32 alpha : 14; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cnp_flag : 1; + u32 rsvd : 6; + u32 cnp_receive : 1; + u32 f_cnt : 3; + u32 ai_cnt : 3; + u32 ip_target_rate : 18; +#else + u32 ip_target_rate : 18; + u32 ai_cnt : 3; + u32 f_cnt : 3; + u32 cnp_receive : 1; + u32 rsvd : 6; + u32 cnp_flag : 1; +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 alpha_timestamp : 16; + u32 rate_timestamp : 16; /* last update rate */ +#else + u32 rate_timestamp : 16; /* last update rate */ + u32 alpha_timestamp : 16; +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rcnp_timestamp : 32; +#else + u32 rcnp_timestamp : 32; +#endif + } bs; + u32 value; + } dw3; +} ucode_ip_table_rate_ctx_s; + +typedef struct ucode_dcc_bw_ctrl_ctx { + union { + struct { + u32 bw_ctrl_thd_def : 32; + }bs; + + u32 value; + } dw0; + + u32 rsvd1[3]; +} ucode_dcc_bw_ctrl_ctx_s; + +/* *************************** RC EXT TABLE *************************** */ +/* dcc ext qpc table struct */ +typedef struct ucode_ext_table_sq_ctx { + /* DW0 */ + union { + u32 ldcpw_rsvd; + + u32 value; + } dw0; + + u32 rsvd; +} ucode_ext_table_sq_ctx_s; + +typedef struct ucode_ext_table_sqa_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 21; + u32 rr_rcv_ce_sn : 11; +#else + u32 rr_rcv_ce_sn : 11; + u32 rsvd : 21; +#endif + } ldcpw; + + u32 value; + } dw0; + + u32 rsvd; +} ucode_ext_table_sqa_ctx_s; + +typedef struct ucode_ext_table_rq_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 20; + u32 sw_rcv_ce_sn : 12; +#else + u32 sw_rcv_ce_sn : 12; + u32 rsvd : 20; +#endif + } ldcpw; + + u32 value; + } dw0; + + u32 rsvd; +} ucode_ext_table_rq_ctx_s; + +typedef struct ucode_ext_table_rqa_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 20; + u32 sw_send_ce_sn : 12; +#else + u32 sw_send_ce_sn : 12; + u32 rsvd : 20; +#endif + } ldcpw; + + u32 value; + } dw0; + + u32 rsvd; +} ucode_ext_table_rqa_ctx_s; + +typedef struct ucode_ext_table_dcc_ctx { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 alpha : 12; + u32 cur_rate : 20; +#else + u32 cur_rate : 20; + u32 alpha : 12; +#endif + } hc3_1_0; + + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 target_rate : 20; + u32 ai_cnt : 3; + u32 f_cnt : 3; + u32 flow_min_rate : 6; +#else + u32 flow_min_rate : 6; + u32 f_cnt : 3; + u32 ai_cnt : 3; + u32 target_rate : 20; +#endif + } hc3_1_0; + + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 alpha_timestamp : 16; + u32 rate_timestamp : 16; +#else + u32 rate_timestamp : 16; + u32 alpha_timestamp : 16; +#endif + } hc3_1_0; + + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 14; + u32 cnp_flag : 1; + u32 cnp_receive : 1; + u32 rcnp_timestamp : 16; +#else + u32 rcnp_timestamp : 16; + u32 cnp_receive : 1; + u32 cnp_flag : 1; + u32 rsvd : 14; +#endif + } hc3_1_0; + + u32 value; + } dw3; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 token_timestamp : 16; +#else + u32 token_timestamp : 16; + u32 rsvd : 16; +#endif + } hc3_1_0; + + u32 value; + } dw4; + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 16; + u32 cnp_tx_filter_ts : 16; +#else + u32 cnp_tx_filter_ts : 16; + u32 rsvd : 16; +#endif + } hc3_1_0; + + u32 value; + } dw5; +} ucode_ext_table_dcc_ctx_s; + +typedef struct smf_rdma_dcc_ip_table { + ucode_ip_table_rate_ctx_s algo_para; // dw0-dw3 +} smf_rdma_dcc_ip_table_s; + +typedef struct ucode_ext_table_qpc_ctx { + ucode_ext_table_sq_ctx_s sq; + ucode_ext_table_sqa_ctx_s sqa; + ucode_ext_table_rq_ctx_s rq; + ucode_ext_table_rqa_ctx_s rqa; +} ucode_ext_table_qpc_ctx_s; + + +typedef struct tag_iqpcn_hash_entry { + u32 dw0; + union { + struct { + u32 rsvd_key[7]; + u8 dgid[16]; + u32 srctagl; + } bs; + u32 value[12]; + } key; + union { + struct { + u32 rsvd : 4; + u32 cnt : 28; + } bs; + u32 item; + } dw13; +} iqpcn_hash_entry; + +typedef struct tag_ipqcn_hash_value { + union { + struct { + u32 code : 2; + u32 subcode : 2; + u32 rsvd : 13; + u32 node_index : 15; + } bs; + u32 value; + } dw0; + union { + struct { + u32 w : 1; + u32 sm_id : 3; + u32 cnt : 28; + } bs; + u32 value; + } dw1; + u32 rsvd[2]; +} ipqcn_hash_value; + +#pragma pack(0) + +#endif // ROCE_CCF_FORMAT_H diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_compile_macro.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_compile_macro.h new file mode 100644 index 000000000..6e80cb6ba --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_compile_macro.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA common public macros. + * Create: 2021-12-30 + */ + +#ifndef ROCE_COMPILE_MACRO_H +#define ROCE_COMPILE_MACRO_H + +#include "node_id.h" + +/* *********************************************** */ +#ifdef PLATFORM_MODE_LLT +#define ROCE_MPATH_EXT_EN +#define ROCE_DIF_EN +#endif +#if (defined(_lint)) // || defined(PLATFORM_MODE_LLT)) +#define ROCE_MPATH_EXT_EN +#define ROCE_DIF_EN +#define ROCE_CC_EN +#define ROCE_CC_IPQCN_EN +#define NOF_ROCE_AA_MODE_EN +#define ROCE_DBG_NONE(para) (void)para +#else +#define ROCE_DBG_NONE(para) \ + do { \ + (void)(para); \ + asm volatile("nop"); \ + } while (0) +#endif + +#ifdef ROCE_LB_MODE1_EN +#define ROCE_LBF_MODE1 +#endif + +#ifdef ROCE_LB_MODE0_EN +#define ROCE_LBF_MODE0 +#endif + +#ifdef TBL_ID_ROCE_QDFX_CTR_SM_NODE +#define ROCE_SRQ_QDFX_EN +#endif + +/* ******************************************************** */ +enum ROCE_LBF_E { + ROCE_LBF_DIS = 0, + ROCE_LBF_TYPE1, + ROCE_LBF_TYPE2, +}; + +#ifdef ROCE_LB_MODE1_ECO_EN +#define ROCE_LB_XID_MASK 0x1 +#else +#define ROCE_LB_XID_MASK 0x3 +#endif + +#define ROCE_LBF_XID_INDEX(idx) (u8)((idx) & ROCE_LB_XID_MASK) +#define ROCE_LBF_GID_LB_INDEX(srctagl) (u8)((srctagl) & ROCE_LB_XID_MASK) + +#if defined(ROCE_LBF_MODE0) || defined(ROCE_LBF_MODE1) + +#ifdef ROCE_LB_MODE1_ECO_EN +#define NODE_SMF_0 NODE_ID_SMF0 +#define NODE_SMF_1 NODE_ID_SMF0 +#define NODE_SMF_2 NODE_ID_SMF2 +#define NODE_SMF_3 NODE_ID_SMF2 +#else +#define NODE_SMF_0 NODE_ID_SMF0 +#define NODE_SMF_1 NODE_ID_SMF1 +#define NODE_SMF_2 NODE_ID_SMF2 +#define NODE_SMF_3 NODE_ID_SMF3 +#endif /* ROCE_LB_MODE1_ECO_EN */ + +#define ROCE_LBF_MODE ROCE_LBF_TYPE1 +#else +#define NODE_SMF_0 NODE_ID_SMF0 +#define NODE_SMF_1 NODE_ID_SMF0 +#define NODE_SMF_2 NODE_ID_SMF0 +#define NODE_SMF_3 NODE_ID_SMF0 + +#define ROCE_LBF_MODE ROCE_LBF_DIS +#endif /* defined(ROCE_LBF_MODE0) || defined(ROCE_LBF_MODE1) */ + +#define ROCE_LBF_INLINE_SMFPG23(idx) ((0 == ((idx) & 0x2)) ? NODE_SMF_2 : NODE_SMF_3) +#define ROCE_LBF_INLINE_SMFPG01(idx) ((0 == ((idx) & 0x2)) ? NODE_SMF_0 : NODE_SMF_1) +#define ROCE_LBF_INLINE_SMFID(idx) ((0 == ((idx) & 0x1)) ? ROCE_LBF_INLINE_SMFPG01(idx) : ROCE_LBF_INLINE_SMFPG23(idx)) +/* ******************************************************** */ + +#define ROCE_FUNC_CHECK(roce_en) ((roce_en) ^ 0x1) + +#endif /* ROCE_COMPILE_MACRO_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_ctx_api.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_ctx_api.h new file mode 100644 index 000000000..80bcdb163 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_ctx_api.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA common context related macros. + * Create: 2021-12-30 + */ + +#ifndef ROCE_CTX_API_H +#define ROCE_CTX_API_H + +#include "roce_compile_macro.h" +#include "roce_wqe_format.h" +#include "roce_xqe_format.h" +#include "rdma_context_format.h" + + +enum ROCE_TIMER_ID_E { + ROCE_TIMER_ID_ACK = 0, + ROCE_TIMER_ID_DCQCN_RCNP, + ROCE_TIMER_ID_WND_LESS_THAN_MTU, + ROCE_TIMER_ID_MAX = 4, + ROCE_TIMER_ID_QP_DEL = 7 +}; + +enum roce_qpc_ulp_type { + ROCE_ULP_STD = 0, + ROCE_ULP_PLOG, + ROCE_ULP_VBS, + ROCE_ULP_OSD, + ROCE_ULP_NOFAA +}; + +enum roce_req_rsp_side { + ROCE_REQ_SIDE = 0, + ROCE_RSP_SIDE +}; + +enum roce_rq_cqe_mask { + ROCE_CQEMASK_WRITE = 0, + ROCE_CQEMASK_SEND +}; + +enum ROCE_FLOWID_E { + ROCE_FLOWID_0 = 0, + ROCE_FLOWID_1, + ROCE_FLOWID_2 +}; + +enum ROCE_STGID_E { + ROCE_STGID_0 = 0, + ROCE_STGID_1, + ROCE_STGID_2, + ROCE_STGID_3, + ROCE_STGID_4, + ROCE_STGID_5, + ROCE_STGID_6, + ROCE_STGID_7 +}; + +enum ROCE_EVENT_STG_E { + ROCE_EVENT_STG_SQ = 0, + ROCE_EVENT_STG_SQA, + ROCE_EVENT_STG_RQ, + ROCE_EVENT_STG_RQA, + ROCE_EVENT_STG_SQA_2HOST, + ROCE_EVENT_STG_DCC, + ROCE_EVENT_STG_VERBS, + ROCE_EVENT_STG_NO +}; + +#define ROCE_SQ_STGID ROCE_STGID_0 +#define ROCE_RQ_STGID ROCE_STGID_1 +#define ROCE_VERBS_STGID ROCE_STGID_2 +#define ROCE_DCC_STGID ROCE_STGID_3 +#define ROCE_RQ_ACK_STGID ROCE_STGID_4 +#define ROCE_SQ_ACK_STGID ROCE_STGID_5 +#define ROCE_SQA_2HOST_STGID ROCE_STGID_6 +#define ROCE_REBIND_STGID QU_STG_ID_RSVD + +/* *********TABLE SIZE******* */ +#define WQEBB_SIZE_SHIFT 6 // 64b +#define ROCE_GET_WQBB_NUM_PERWQE(wqe_len_8b) (BYTE8_TO_BYTES(wqe_len_8b) >> WQEBB_SIZE_SHIFT) + +#define ROCE_GID_TABLE_SIZE (32) +#define ROCE_MPT_TABLE_SIZE (64) +#define ROCE_MTT_TABLE_SIZE (8) +#define ROCE_CQC_TABLE_SIZE (128) +#define ROCE_SRQC_TABLE_SIZE (64) +#define ROCE_RDMARC_TABLE_SIZE (32) +#define ROCE_QPC_TABLE_SIZE (512) +#define ROCE_WQE_MAX_SIZE (256) +#define ROCE_CM_MAD_MEG_LEN (64) + +#define ROCE_MTT_QUERY_SIZE (16) +#define ROCE_PCNT_QUERY_SIZE (16) + +#define ROCE_CQE_LEN (64) +#define ROCE_CQE_LEN_SHIFT (6) +#define ROCE_RESIZE_CQE_LEN (64) + +#define ROCE_QPC_RRWC_SEG_SIZE (32) +#define ROCE_QPC_RCC_SEG_SIZE (32) +#define ROCE_QPC_SQPC_SEG_SIZE (64) +#define ROCE_QPC_SQC_SEG_SIZE (64) +#define ROCE_QPC_SQAC_SEG_SIZE (64) +#define ROCE_QPC_RQC_SEG_SIZE (64) +#define ROCE_QPC_QPCC_SEG_SIZE (32) +#define ROCE_QPC_HW_SEG_SIZE (ROCE_QPC_RRWC_SEG_SIZE + ROCE_QPC_RCC_SEG_SIZE + ROCE_QPC_SQC_SEG_SIZE + \ + ROCE_QPC_SQAC_SEG_SIZE + ROCE_QPC_RQC_SEG_SIZE + ROCE_QPC_QPCC_SEG_SIZE) +#define ROCE_QPC_TIMER_SEG_SIZE (32) +#define ROCE_QPC_SW_SEG_SIZE (192) +#define ROCE_QPC_SW_DCQCN_SIZE (16) +#define ROCE_QPC_SW_NOFAA_SIZE ROCE_QPC_QPCC_SEG_SIZE +#define ROCE_QPC_SW_SQC_SIZE (20) +#define ROCE_QPC_SW_SQAC_SIZE (36) +#define ROCE_QPC_SW_RQC_SIZE (20) +#define ROCE_QPC_SW_RQAC_SIZE (20) +#define ROCE_QPC_SW_STGID_SIZE (68) + +#define ROCE_QPC_EXT_SW_SEG_SIZE (32) + +#define ROCE_QPC_RRWC_DW_SIZE (8) +#define ROCE_QPC_RCC_DW_SIZE (8) +#define ROCE_QPC_SQPC_DW_SIZE (16) +#define ROCE_QPC_SQC_DW_SIZE (16) +#define ROCE_QPC_SQAC_DW_SIZE (16) +#define ROCE_QPC_RQC_DW_SIZE (16) +#define ROCE_QPC_QPCC_DW_SIZE (8) +#define ROCE_QPC_TIMER_DW_SIZE (8) +#define ROCE_QPC_SW_DW_SIZE (48) +#define ROCE_QPC_SW_DCQCN_DW_SIZE (8) +#define ROCE_QPC_SW_NOFAA_DW_SIZE ROCE_QPC_QPCC_DW_SIZE + +#define ROCE_QPC_SW_SEG_DWORD_LEN (ROCE_QPC_SW_SEG_SIZE >> 2) +#define ROCE_QPC_HW_SEG_DWORD_LEN (ROCE_QPC_HW_SEG_SIZE >> 2) +#define ROCE_QPC_SW_DCQCN_DWORD_LEN (ROCE_QPC_SW_DCQCN_SIZE >> 2) +#define ROCE_QPC_SW_NOFAA_DWORD_LEN (ROCE_QPC_SW_NOFAA_SIZE >> 2) +#define ROCE_QPC_SW_STGID_DWORD_LEN (ROCE_QPC_SW_STGID_SIZE >> 2) +#define ROCE_QPC_DWORD_LEN (ROCE_QPC_TABLE_SIZE >> 2) +#define ROCE_MPT_DWORD_LEN (ROCE_MPT_TABLE_SIZE >> 2) +#define ROCE_CQC_DWORD_LEN (ROCE_CQC_TABLE_SIZE >> 2) +#define ROCE_SRQC_DWORD_LEN (ROCE_SRQC_TABLE_SIZE >> 2) +#define ROCE_GID_DWORD_LEN (ROCE_GID_TABLE_SIZE >> 2) +#define ROCE_CM_MAD_DWORD_LEN (ROCE_CM_MAD_MEG_LEN >> 2) + +#define ROCE_RDMARC_MAX_DATA_DW_LEN (ROCE_RDMARC_TABLE_SIZE >> 2) + +#define ROCE_SQ_WQE_SEND_TASK_SEG_LEN (16) +#define ROCE_SQ_WQE_UD_SEND_TASK_SEG_LEN (64) +#define ROCE_SQ_WQE_RDMA_TASK_SEG_LEN (32) +#define ROCE_SQ_WQE_ATOMIC_TASK_SEG_LEN (32) +#define ROCE_SQ_WQE_MASK_ATOMIC_CMPSWP_TASK_SEG_LEN (48) +#define ROCE_SQ_WQE_SEND_WRITE_COM_TASK_SEG_LEN (16) + +/* ******************************************************** */ +enum ROCE_QP_CTX_OFF_E { + ROCE_CTX_RRWC_OFF = 0, + ROCE_CTX_RCC_OFF = 32, + ROCE_CTX_SQC_OFF = 64, + ROCE_CTX_SQAC_OFF = 128, + ROCE_CTX_RQC_OFF = 192, + ROCE_CTX_QPCC_OFF = 256, + ROCE_CTX_TIMER_OFF = 288, + ROCE_CTX_SW_OFF = 320, + ROCE_CTX_SW_SQC_OFF = 400, + ROCE_CTX_SW_SQAC_OFF = 416, + ROCE_CTX_SW_RQC_OFF = 448, + ROCE_CTX_SW_RQAC_OFF = 464 +}; +#define ROCE_CTX_SQPC_OFF ROCE_CTX_RRWC_OFF + +#define ROCE_MISC_RRWC_OFFSET_16B_ALIGN (ROCE_CTX_RRWC_OFF >> 4) +#define ROCE_MISC_RCC_OFFSET_16B_ALIGN (ROCE_CTX_RCC_OFF >> 4) +#define ROCE_MISC_SQC_OFFSET_16B_ALIGN (ROCE_CTX_SQC_OFF >> 4) +#define ROCE_MISC_SQAC_OFFSET_16B_ALIGN (ROCE_CTX_SQAC_OFF >> 4) +#define ROCE_MISC_RQC_OFFSET_16B_ALIGN (ROCE_CTX_RQC_OFF >> 4) +#define ROCE_MISC_QPCC_OFFSET_16B_ALIGN (ROCE_CTX_QPCC_OFF >> 4) +#define ROCE_MISC_TIMERC_OFFSET_16B_ALIGN (ROCE_CTX_TIMER_OFF >> 4) +#define ROCE_MISC_SW_OFFSET_16B_ALIGN (ROCE_CTX_SW_OFF >> 4) +#define ROCE_MISC_SW_OFFSET64_16B_ALIGN ((ROCE_CTX_SW_OFF + 64) >> 4) +#define ROCE_MISC_SW_OFFSET128_16B_ALIGN ((ROCE_CTX_SW_OFF + 128) >> 4) +#define ROCE_MISC_SQPC_OFFSET_16B_ALIGN (ROCE_CTX_SQPC_OFF >> 4) + +#ifdef NOF_ROCE_AA_MODE_EN +#define ROCE_WB_CTX_SIZE QU_WB_CTX_SIZE_224 +#else +#define ROCE_WB_CTX_SIZE QU_WB_CTX_SIZE_192 +#endif + +#define ROCE_RDMARC_ATOMIC_DATA_LEN (8) + +#define ROCE_RDMARC_ATOMIC_DATA_DW_LEN (16 >> 2) +#define ROCE_RDMARC_ATOMIC_STATUS_DW_LEN (4 >> 2) +#define ROCE_RDMARC_ATOMIC_DATA_DW_OFF (16 >> 2) +#define ROCE_RDMARC_ATOMIC_STATUS_DW_OFF (28 >> 2) +/* ************************************************* */ +#define ROCE_QPCC_RXE_DW_OFF (4) +#define ROCE_QPCC_RXE_DW_BITMASK (0X01C00000) +#define ROCE_RCC_RXE_DW_OFF (7) +#define ROCE_RRWC_RXE_DW_OFF (7) +#define ROCE_RCC_RAE_DW_BITMASK (~0X08000000) +#define ROCE_RCC_RRE_DW_BITMASK (~0X04000000) +#define ROCE_RRWC_RWE_DW_BITMASK (~0X08000000) + +#define ROCE_QP_QPCC_GPAH_DW_OFF (6) +#define ROCE_QP_QPCC_GPAH_DW_BITMASK (~0X00FFFFFF) +#define ROCE_QP_QPCC_GPAL_DW_BITMASK (~0XFFFFFFFF) + +#define ROCE_QP_RCC_RCPI_DW_OFF (5) +#define ROCE_QP_RCC_RCPI_DW_BITMASK (~0X000000FF) +#define ROCE_QP_RCC_RCCI_DW_BITMASK (~0X000000FF) + +#define ROCE_QP_COM_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_QP_RCC_STATE_DW_OFF (7) +#define ROCE_QP_RCC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_QP_SQC_STATE_DW_OFF (2) +#define ROCE_QP_SQC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_QP_SQAC_STATE_DW_OFF (2) +#define ROCE_QP_SQAC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_QP_SQAC_WQEIDX_DW_OFF (2) +#define ROCE_QP_SQAC_WQEIDX_DW_BITMASK (~0X0000ffff) + +#define ROCE_QP_RQC_STATE_DW_OFF (2) +#define ROCE_QP_RQC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_QP_RRWC_STATE_DW_OFF (7) +#define ROCE_QP_RRWC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_QP_RQC_SGEVLD_DW_OFF (0) +#define ROCE_QP_RQC_SGEVLD_DW_BITMASK (~0X80000000) + +#define ROCE_MPT_STATE_DW_OFF (2) +#define ROCE_MPT_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_MPT_MWCNT_DW_OFF (10) +#define ROCE_MPT_MWCNT_DW_BITMASK (~0Xffffffff) + +#define ROCE_SRQC_STATE_DW_OFF (2) +#define ROCE_SRQC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_CQC_STATE_DW_OFF (2) +#define ROCE_CQC_STATE_DW_BITMASK (~0Xf0000000) + +#define ROCE_CQC_TIMEOUT_DW7_OFF (7) +#define ROCE_CQC_TIMEOUT_DW7_BITMASK (~0Xffffffff) + +#define ROCE_CQC_TMR_TWID_DW10_OFF (10) +#define ROCE_CQC_TMR_TWID_DW_BITMASK (~0Xffff0000) + +#define ROCE_SRQC_ERR_STATE (0x10000000) +#define ROCE_QPC_RQ_COMM_EST_OFF (27) /* *keep the same with qpc rq DW22 */ + +#define ROCE_RRWC_SGE_VLD (0x80000000) + +/* ******************************************************** */ +#define ROCE_ULP_TYPE_PLOG(qpc) (u8)((qpc)->ucode_seg.common.dw0.bs.ulp_type == ROCE_ULP_PLOG) +#define ROCE_ULP_TYPE_VBS(qpc) (u8)((qpc)->ucode_seg.common.dw0.bs.ulp_type == ROCE_ULP_VBS) +#define VERBS_ULP_TYPE_VBS(ulp_type) (u8)((ulp_type) == ROCE_ULP_VBS) + +#define ROCE_VLAN 1 + +#endif /* ROCE_CTX_API_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_dif_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_dif_format.h new file mode 100644 index 000000000..1dc3d4333 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_dif_format.h @@ -0,0 +1,459 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA offloaded DIF context. + * Create: 2021-12-30 + */ + +#ifndef ROCE_DIF_FORMAT_H +#define ROCE_DIF_FORMAT_H + +#include "roce_wqe_format.h" +#include "roce_xqe_format.h" +#include "roce_verbs_mr_attr.h" + +typedef struct tag_roce_dif_cqe_s { + // roce_cqe_s roce_cqe; + u32 common[8]; /* dif multiplexes the first 32 Bits of standard cqe */ + u32 timestamp_h; + u32 timestamp_l; + u32 mr_lkey; + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd1 : 4; + u32 app_err : 1; + u32 ref_err : 1; + u32 grd_err : 1; + u32 rsvd2 : 17; + u32 rcv_pi_vb : 8; +#else + u32 rcv_pi_vb : 8; + u32 rsvd2 : 17; + u32 grd_err : 1; + u32 ref_err : 1; + u32 app_err : 1; + u32 rsvd1 : 4; +#endif + } bs; + u32 value; + } dw11; + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rcv_pi_h; + u32 rcv_pi_l; +#else + u32 rcv_pi_l; + u32 rcv_pi_h; +#endif + } bs; + u64 value; + } rcv_pi; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 vrf_agm_imm : 16; + u32 ri_agm_imm : 16; +#else + u32 ri_agm_imm : 16; + u32 vrf_agm_imm : 16; +#endif + } bs; + u32 value; + } dw14; + u32 rsvd3; +} roce_dif_cqe_s; + +typedef struct tag_roce_dif_com_s { + roce_dif_user_data_s *dif_data; + + u32 sd_pdu_ofs; + u32 sd_pdu_len; + + u16 difx_cnt; + u16 mss; + u16 metadata_len; + u16 sector_len; +} roce_dif_com_s; + +typedef union tag_roce_dif_misc_rx_s { + struct { + u32 rsvd : 18; + u32 fst_bt_tp : 1; + u32 fst_sector : 1; + u32 fst_bt_ofs : 12; + } bs; + u32 value; +} roce_dif_misc_rx_s; + +typedef struct tag_roce_dif_wqe_rdma_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; + + /* DW2 */ + u32 imm_data; + + /* DW3 */ + u32 rsvd1; + + /* DW4~5 */ + union { + u64 va; + struct { + u32 va_h32; + u32 va_l32; + } dw4; + }; + + /* DW6 */ + u32 rkey; + roce_dif_user_data_s dif_data; + /* DW7 */ + // u32 sig_key; +} roce_dif_wqe_rdma_tsk_seg_s; + +typedef struct tag_roce_dif_wqe_snd_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW0 */ + u32 data_len; /* Length of the data sent by the SQ WQE */ + + /* DW1 */ + u32 immdata_invkey; /* This parameter is valid for the immediate data operation or SEND invalidate. */ + + roce_dif_user_data_s dif_data; +} roce_dif_wqe_snd_tsk_seg_s; + + +/* REG SIG MR Local WQE */ +typedef struct roce_wqe_reg_sig_mr_seg { + roce_wqe_tsk_com_seg_u common; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rre : 1; /* Remote read enable */ + u32 rwe : 1; /* Remote write enable */ + u32 lwe : 1; /* Local write enable */ + u32 sgl_mode : 1; /* 0: Single SGL, 1: Dual SGL */ + u32 sector_size : 1; /* 0 : 512B, 1: 4096B */ + u32 rsvd1 : 3; + u32 block_size : 6; /* Block size, which is the same as the MPT data definition. */ + u32 rsvd2 : 18; +#else + u32 rsvd2 : 18; + u32 block_size : 6; /* Block size, which is the same as the MPT data definition. */ + u32 rsvd1 : 3; + u32 sector_size : 1; /* 0 : 512B, 1: 4096B */ + u32 sgl_mode : 1; /* 0: Single SGL, 1: Dual SGL */ + u32 lwe : 1; /* Local write enable */ + u32 rwe : 1; /* Remote write enable */ + u32 rre : 1; /* Remote read enable */ +#endif + } bs; + u32 value; + } dw0; + + u32 sig_mr_mkey; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 10; + u32 mtt_offset : 22; +#else + u32 mtt_offset : 22; + u32 rsvd : 10; +#endif + } bs; + u32 value; + } dw2; + roce_dif_user_data_s dif_data; + u32 data_mr_key; + u32 metadata_mr_key; + u32 rsvd1; +} roce_wqe_reg_sig_mr_seg_s; + + +typedef struct roce_wqe_reg_mr_dsgl_seg { + struct roce_wqe_reg_sig_mr_seg reg_mr_seg; + struct roce3_sge_info data_sge; + struct roce3_sge_info prot_sge; +} roce_wqe_reg_mr_dsgl_seg_s; + +typedef struct roce_dif_ssgl_mpt_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 buf_page_size : 4; /* Page_size of the buffer */ + u32 mtt_layer_num : 3; /* Mtt level */ + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 rsvd2 : 4; + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 rsvd1 : 1; + u32 rkey : 1; + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ +#else + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 rkey : 1; + u32 rsvd1 : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 rsvd2 : 4; + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 mtt_layer_num : 3; /* Number of mtt levels */ + u32 buf_page_size : 4; /* Page_size of the buffer */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; /* Dma sequence preserving flag */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 ep : 3; + u32 qpn : 20; /* Qp bound to the mw. */ +#else + u32 qpn : 20; /* Qp bound to mw */ + u32 ep : 3; + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 so_ro : 2; /* Dma order-preserving flag */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ + u32 indirect_mr : 1; + u32 cos : 3; + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 pdn : 18; /* Pd bound to mr or mw */ +#else + u32 pdn : 18; /* Pd bound to mr or mw */ + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 cos : 3; + u32 indirect_mr : 1; /* If set, indicates this MPT is double SGL type. */ + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mkey : 8; /* The index is not included. */ + u32 sw_dif_en : 1; /* If set, indicates dif mode. */ + u32 page_mode : 1; + u32 fbo : 22; +#else + u32 fbo : 22; + u32 page_mode : 1; + u32 sw_dif_en : 1; /* If set, indicates dif mode. */ + u32 mkey : 8; /* The index is not included. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; + + /* DW6~7 */ + union { + u64 length; /* Length of mr or mw */ + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw6; + }; + + /* DW8~9 */ + union { + u64 mtt_base_addr; /* Mtt base address (pa) */ + struct { + u32 mtt_base_addr_hi; /* Mtt base address (pa) upper 32 bits */ + u32 mtt_base_addr_lo; /* Lower 32 bits of mtt base address (pa) */ + } dw8; + }; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + }; + roce_dif_user_data_s dif_data; +} roce_dif_ssgl_mpt_context_s; + +typedef struct roce_dif_dsgl_mpt_context { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd6 : 11; + u32 signature : 4; + u32 rsvd5 : 1; + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 rsvd4 : 1; + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 rsvd3 : 1; + u32 rkey : 1; + u32 rsvd2 : 1; + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 rsvd0 : 1; + u32 rsvd1 : 1; + u32 access_bind : 1; /* Whether mr can be bound to mw */ +#else + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ + u32 rsvd0 : 1; + u32 rsvd1 : 1; + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 rsvd2 : 1; + u32 rkey : 1; + u32 rsvd3 : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 rsvd4 : 1; + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 rsvd5 : 1; + u32 signature : 4; + u32 rsvd6 : 11; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { + u32 rsvd; + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ + u32 indirect_mr : 1; /* If set, indicates this MPT is double SGL type. */ + u32 rsvd : 27; +#else + u32 rsvd : 27; + u32 indirect_mr : 1; /* If set, indicates this MPT is double SGL type. */ + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mkey : 8; /* The index is not included. */ + u32 sw_dif_en : 1; /* If set, indicates dif mode. */ + u32 rsvd : 23; +#else + u32 rsvd : 23; + u32 sw_dif_en : 1; /* If set, indicates dif mode. */ + u32 mkey : 8; /* The index is not included. */ +#endif + } bs; + u32 value; + } dw3; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 4; + u32 data_mr_key : 28; +#else + u32 data_mr_key : 28; + u32 rsvd : 4; +#endif + } bs; + u32 value; + } dw4; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 4; + u32 metadata_mr_key : 28; +#else + u32 metadata_mr_key : 28; + u32 rsvd : 4; +#endif + } bs; + u32 value; + } dw5; + + /* DW6~DW9 */ + u32 rsvd[4]; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + }; + roce_dif_user_data_s dif_data; +} roce_dif_dsgl_mpt_context_s; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_err_type.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_err_type.h new file mode 100644 index 000000000..9b2279b59 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_err_type.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA common err type. + * Create: 2021-12-30 + */ + +#ifndef ROCE_ERR_TYPE_H +#define ROCE_ERR_TYPE_H + +#include "typedef.h" +#include "roce_pub_cmd.h" +#include "roce_api.h" + + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +/* **********************macro define************************ */ +enum ROCE_ERR_STATE_E { + ROCE_AEQE_NOERR_STATE = 0, + ROCE_AEQE_ERR_STATE, +}; + +enum ROCE_QP_ERR_STATE_E { + ROCE_QP_NOERR_STATE = 0, + ROCE_QP_ERR_STATE, +}; + +/* *********ROCE_AEQE_SUBTYPE_E******* */ +enum ROCE_AEQE_SUBTYPE_E { + ROCE_AEQE_SUBTYPE_PATH_MIGRATED = 0, /* * APM */ + ROCE_AEQE_SUBTYPE_COMM_ESTABLISHED, /* *RQ RTR RCV FIRST PKT */ + ROCE_AEQE_SUBTYPE_SQ_DRAINED, /* * sq empty and change to SQ DRANNING STATE */ + ROCE_AEQE_SUBTYPE_SRQ_LIMIT_REACHED, /* *SRQ LIMIT_REACHED from RXDMA api rsp */ + ROCE_AEQE_SUBTYPE_QP_LAST_WQE_REACHED, /* *srq en & LAST_WQE_REACHED */ + ROCE_AEQE_SUBTYPE_CQ_ERR, /* *api rsp cq err */ + ROCE_AEQE_SUBTYPE_QP_FATAL, /* *LOC_WORK_QUEUE_CATASTROPHIC_ERR */ + ROCE_AEQE_SUBTYPE_QP_REQ_ERR, /* *INVALID_REQ_LOC_WORK_QUEUE_ERR */ + ROCE_AEQE_SUBTYPE_QP_ACCESS_ERR, /* *LOC_ACCESS_VIOLATION_WORK_QUEUE_ERR */ + ROCE_AEQE_SUBTYPE_PATH_MIG_ERR, + ROCE_AEQE_SUBTYPE_GID_CHANGE_EVENT, + ROCE_AEQE_SUBTYPE_CQ_OVERRUN, + ROCE_AEQE_SUBTYPE_SRQ_CATASTROPHIC_ERR, + ROCE_AEQE_SUBTYPE_CFG_ERR, + ROCE_AEQE_SUBTYPE_CHIP_ERR, + ROCE_AEQE_SUBTYPE_DIF_ERR, + ROCE_AEQE_SUBTYPE_XRC_DOMAIN_VIOLATION_ERR, + ROCE_AEQE_SUBTYPE_INVALID_XRCETH_ERR, + ROCE_AEQE_SUBTYPE_UCODE_FATAL_ERR, + ROCE_AEQE_SUBTYPE_ODP_PAGE_FAULT, + ROCE_AEQE_SUBTYPE_RSVD, +}; + +/* *********ROCE SQ ERR type******* */ +enum ROCE_COMPLETION_EVENT_ERR_TYPE_E { + ROCE_COMPLTE_EVENT_NO_ERR = 0, + ROCE_COMPLTE_EVENT_LOC_LEN_ERR = 0x1, + ROCE_COMPLTE_EVENT_LOC_QP_OPERATION_ERR, + ROCE_COMPLTE_EVENT_LOC_PROTECTION_ERR = 0x4, + ROCE_COMPLTE_EVENT_LOC_MEM_MANAGEMENT_ERR = 0x4, + ROCE_COMPLTE_EVENT_WR_FLUSH_ERR, + ROCE_COMPLTE_EVENT_MW_BIND_ERR, + ROCE_COMPLTE_EVENT_BAD_RESP_ERR = 0x10, + ROCE_COMPLTE_EVENT_LOC_ACCESS_ERR, + ROCE_COMPLTE_EVENT_REM_INV_REQ_ERR, + ROCE_COMPLTE_EVENT_REM_ACCESS_ERR, + ROCE_COMPLTE_EVENT_REM_OPERATION_ERR, + ROCE_COMPLTE_EVENT_RETRY_CTR_EXCEED_ERR, + ROCE_COMPLTE_EVENT_RNR_RETRY_CTR_EXCEED_ERR, + ROCE_COMPLTE_EVENT_REM_ABORTED_ERR = 0x22, + ROCE_COMPLTE_EVENT_XRC_VIOLATION_ERR, +}; + +enum ROCE_AEQE_EVENT_ERR_TYPE_E { + ROCE_AEQE_QP_FATAL_SQ_FETCH_WQE_STATUS_ERR = 0, + ROCE_AEQE_QP_FATAL_SQ_DMA_GEN_STATUS_ERR, + ROCE_AEQE_QP_FATAL_SQ_DMA_GEN_MPT_STATUS_ERR, + ROCE_AEQE_QP_FATAL_SQ_DMA_GEN_CQ_STATUS_ERR, + ROCE_AEQE_QP_FATAL_SQ_COMPLETE_WQE_STATUS_ERR, + ROCE_AEQE_QP_FATAL_SQ_COMPLETE_CQ_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RQ_RXDMA_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RQ_RXDMA_MPT_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RQ_RXDMA_CQ_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RQ_RXDMA_SRQ_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RQ_RDMA_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RQ_RDMA_MPT_STATUS_ERR, + ROCE_AEQE_QP_FATAL_CQ_CQE_STATUS_ERR, + ROCE_AEQE_QP_FATAL_CQ_ARM_STATUS_ERR, + ROCE_AEQE_QP_FATAL_SRQ_ARM_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RDMARC_STATUS_ERR, + ROCE_AEQE_QP_FATAL_RDMARC_RSP_PSN_ERR = 0x10, + ROCE_AEQE_QP_FATAL_MINVLD_STATUS_ERR, + ROCE_AEQE_QP_FATAL_CQ_RESIZE_STATUS_ERR, + ROCE_AEQE_QP_FATAL_CQ_OVERFLOW, + ROCE_AEQE_CFG_TYPE_STATELESS_MAC = 0x20, + ROCE_AEQE_CFG_TYPE_STATELESS_FUNC, + ROCE_AEQE_CFG_TYPE_QPC_PREFETCH_RSP_ERR, + ROCE_AEQE_CFG_TYPE_QPC_STATE_ERR, + ROCE_AEQE_CFG_TYPE_QPC_STATE_NOT_RTS, + ROCE_AEQE_CHIP_TYPE_CPB_BUF_FULL, + ROCE_AEQE_CHIP_TYPE_IPSU_RSP_ERR, + ROCE_AEQE_CHIP_TYPE_QU_QUERY_RSP_ERR, + ROCE_AEQE_LOC_QP_REQ_ERR_TOO_MANY_READ_ATOMIC = 0x30, + ROCE_AEQE_LOC_QP_REQ_ERR_OPCODE_MISMATCH, + ROCE_AEQE_LOC_QP_REQ_ERR_LEN_ERR, + ROCE_AEQE_LOC_QP_OPERATION_ERR, + ROCE_AEQE_LOC_QP_NUM_RANGE_ERR, + ROCE_AEQE_MPT_NUM_RANGE_ERR, + ROCE_AEQE_MASTER_QP_MODIFY_ERR, +}; + +#define ROCE_AEQE_EVENT(module_type, subtype, type, err_code) \ + (((u32)(module_type) << 28) | ((subtype) << 20) | ((type) << 8) | (err_code)) + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif /* ROCE_ERR_TYPE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_hmm_context.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_hmm_context.h new file mode 100644 index 000000000..84c7c78cd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_hmm_context.h @@ -0,0 +1,196 @@ +/****************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + ****************************************************************************** + File Name : roce_hmm_context.h + Version : Initial Draft + Description : common command queue interface + Function List : + History : + Modification: Created file + +******************************************************************************/ + +#ifndef ROCE_HMM_CONTEXT_H +#define ROCE_HMM_CONTEXT_H + +/* **************** Macro Definition ****************** */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +/* **************** Data Structure Definition ****************** */ +/* * MPT Format start */ +typedef struct roce_mpt_context { + /* DW0 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 access_bind : 1; /* Whether mr can be bound to mw */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 rkey : 1; + u32 dif_mode : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 signature : 4; + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 mtt_layer_num : 3; /* Mtt level */ + u32 buf_page_size : 4; /* Page_size of the buffer */ +#else + u32 buf_page_size : 4; /* Page_size of the buffer */ + u32 mtt_layer_num : 3; /* Number of mtt levels */ + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 signature : 4; + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 dif_mode : 1; + u32 rkey : 1; + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify the remote authority. */ + u32 access_bind : 1; /* Whether mr can be bound to mw */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 qpn : 20; /* Qp bound to mw */ + u32 ep : 3; + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 so_ro : 2; /* Dma order-preserving flag */ +#else + u32 so_ro : 2; /* Dma sequence preserving flag */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 ep : 3; + u32 qpn : 20; /* Qp bound to mw */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 pdn : 18; /* Pd bound to mr or mw */ + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 cos : 3; + u32 indirect_mr : 1; + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#else + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ + u32 indirect_mr : 1; /* indirect mr flag */ + u32 cos : 3; + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 pdn : 18; /* Pd bound to mr or mw */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 fbo : 22; + u32 page_mode : 1; + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 mkey : 8; /* The index is not included. */ +#else + u32 mkey : 8; /* The index is not included. */ + u32 sgl_mode : 1; /* If set, indicates this MPT is double SGL type. */ + u32 page_mode : 1; + u32 fbo : 22; +#endif + } bs; + u32 value; + } dw3; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; + + /* DW6~7 */ + union { + u64 length; /* Length of mr or mw */ + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw6; + }; + + /* DW8~9 */ + union { + u64 mtt_base_addr; /* Mtt base address (pa)hi:bit[63:32], lo:bit[31:03], gpa_sign[02:00] */ + struct { + u32 mtt_base_addr_hi; /* Mtt base address (pa) upper 32 bits */ + u32 mtt_base_addr_lo; /* Mtt base address (pa) lower 32 bits */ + } dw8; + }; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + }; + + /* DW11 */ + u32 mtt_sz; /* This parameter is valid when FRMR. */ + + /* DW12~DW13 */ + u32 rsvd[2]; + + /* DW14~15 */ + union { + u64 mw_vaddr; /* Mtt base address (pa)hi:bit[63:32], lo:bit[31:03], gpa_sign[02:00] */ + struct { + u32 mw_vaddr_hi; /* Mtt base address (pa) upper 32 bits */ + u32 mw_vaddr_lo; /* Mtt base address (pa) lower 32 bits */ + } dw14; + struct { + u32 mw_vaddr_hi; /* Mtt base address (pa) upper 32 bits */ + u32 mw_vaddr_lo; /* Mtt base address (pa) lower 32 bits */ + } dw15; + }; +} roce_mpt_context_s; + +#endif + diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_common.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_common.h new file mode 100644 index 000000000..ef5e55c9b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_common.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * Description : RoCE service common API b/w driver and MPU + * Author : / + * Create : / + * Notes : / + * History : / + */ + +#ifndef ROCE_MPU_COMMON_H +#define ROCE_MPU_COMMON_H + +#include "mpu_cmd_base_defs.h" + +enum { + /* FUNC CFG */ + ROCE_MPU_CMD_SET_FUNC_STATE = 0, + ROCE_MPU_CMD_SET_CPU_ENDIAN, + ROCE_MPU_CMD_GET_CFG_INFO, + ROCE_MPU_CMD_DEL_FUNC_RES, + ROCE_MPU_CMD_GET_FUNC_TABLE, + ROCE_MPU_CMD_ADD_MAC = 10, + ROCE_MPU_CMD_DEL_MAC, + ROCE_MPU_CMD_ADD_IPSU_MAC, + ROCE_MPU_CMD_DEL_IPSU_MAC, + ROCE_MPU_CMD_GET_MAC_VNI, + + /* BOND */ + ROCE_MPU_CMD_BOND_SET_STATE = 20, + ROCE_MPU_CMD_BOND_GET_ER_FWD_ID, + ROCE_MPU_CMD_BOND_SET_ER_FWD_ID, + ROCE_MPU_CMD_BOND_ER_FWD_ID_COMBINE, + ROCE_MPU_CMD_BOND_ER_FWD_ID_COMPACT, + ROCE_MPU_CMD_GET_GROUP_ID, + + /* CC */ + ROCE_MPU_CMD_CC_CFG_CCF_PARAM = 40, + ROCE_MPU_CMD_CC_CFG_DCQCN_PARAM, + ROCE_MPU_CMD_CC_CFG_IPQCN_PARAM, + ROCE_MPU_CMD_CC_CFG_LDCP_PARAM, + ROCE_MPU_CMD_CC_SET_BW_CTRL, + ROCE_MPU_CMD_CC_QUERY_BW_CTRL, + + /* DFX */ + ROCE_MPU_CMD_DFX_CACHE_OUT = 55, + ROCE_MPU_CMD_DFX_SET_CAP_CFG, + ROCE_MPU_CMD_DFX_GET_CAP_CFG, + ROCE_MPU_CMD_DFX_READ_CAP_CTR, + ROCE_MPU_CMD_DFX_CLEAR_CAP_CTR, + + /* ULP */ + ROCE_MPU_CMD_ULP_AA_SET_DD_CFG = 128, + ROCE_MPU_CMD_ULP_AA_CTRL_READY, + ROCE_MPU_CMD_ULP_AA_SWITCH_IO, + ROCE_MPU_CMD_ULP_AA_FAKE_DATA, + ROCE_MPU_CMD_ULP_AA_CLAER_ACT_CTRL_BMP, + + ROCE_MPU_CMD_MAX +}; + +#define MAX_ROCE_PHY_PORT 8 + +/* ********************************** Func cmd between driver and mpu ********************************** */ +typedef struct roce_set_func_state_cmd { + struct comm_info_head head; + + u16 func_id; + u8 func_en; + u8 tag; +} roce_set_func_state_cmd_s; + +typedef struct roce_get_func_table_cmd { + struct comm_info_head head; + + u16 func_id; + u8 rsvd[2]; +} roce_get_func_table_cmd_s; + +typedef struct roce_get_func_table_rsp { + struct comm_info_head head; + u32 func_tbl_value; +} roce_get_func_table_rsp_s; + +typedef struct roce_get_cfg_info_cmd { + struct comm_info_head head; + + u16 func_id; + u8 rsvd[2]; +} roce_get_cfg_info_cmd_s; + +typedef struct roce_get_cfg_info_resp { + struct comm_info_head head; + + u8 scence_id; + u8 lb_en; + u8 lb_mode; + u8 container_mode; + + u8 fake_en; + u8 pf_start_bit; + u8 pf_end_bit; + u8 page_bit; + + u8 port_num; + u8 host_num; + u16 rsvd; +} roce_get_cfg_info_resp_s; + +typedef struct roce_set_cpu_endian_cmd { + struct comm_info_head head; + + u16 func_id; + u8 cpu_endian; + u8 rsvd; +} roce_set_cpu_endian_cmd_s; + +typedef struct roce_cfg_mac_cmd { + struct comm_info_head head; + + u16 func_id; + u16 rsvd; + u16 er_fwd_id; + u8 mac[6]; + u8 vni_en; + u32 vlan_id; +} roce_cfg_mac_cmd_s; + +typedef struct roce_cfg_ipsu_mac_cmd { + struct comm_info_head head; + + u16 func_id; + u8 er_id; + u8 vni_en; /* vni enable */ + u8 mac[6]; + u8 rsvd[2]; + u32 vlanid_vni; +} roce_cfg_ipsu_mac_cmd_s; + +typedef struct vroce_mac_cfg_vni_info { + struct comm_info_head head; + u16 func_id; + u16 rsvd; + + u32 vlan_vni : 24; + u32 vni_en : 8; +} vroce_mac_cfg_vni_info_s; + +/* ********************************** Bond cmd between driver and mpu ********************************** */ +typedef struct roce_bond_cfg_state_cmd { + struct comm_info_head head; + + u16 func_id; + u8 bond_en; + u8 rsvd; +} roce_bond_cfg_state_cmd_s; + +typedef struct roce_bond_set_ipsu_mac_cmd { + struct comm_info_head head; + + u16 func_id; + u16 vlan_id; + u16 er_fwd_id; + u8 mac[6]; +} roce_bond_set_ipsu_mac_cmd_s; + +typedef struct roce_bond_cfg_er_fwd_id_cmd { + struct comm_info_head head; + + u16 func_id; + u16 er_fwd_id; + u32 bond_tbl_val; +} roce_bond_cfg_er_fwd_id_cmd_s; + +typedef struct roce_bond_combine_er_fwd_id_cmd { + struct comm_info_head head; + u16 func_id_src; + u16 func_id_dst; + u16 er_fwd_id; + u8 rsvd[2]; +} roce_bond_combine_er_fwd_id_cmd_s; + +typedef struct roce_bond_compact_er_fwd_id_cmd { + struct comm_info_head head; + + u16 func_id; + u16 rsvd; + u32 value; /* dw14 value */ +} roce_bond_compact_er_fwd_id_cmd_s; + +/* ********************************** CC cmd between driver and mpu ********************************** */ +typedef struct roce_cc_cfg_param_cmd { + struct comm_info_head head; + u16 func_id; + u16 rsvd; + u32 param[4]; +} roce_cc_cfg_param_cmd_s; + +typedef struct roce_cc_cfg_bw_ctrl_cmd { + struct comm_info_head head; + + u16 func_id; + u8 cmd; + u8 rsvd; + + u8 color_type; + u16 ptype; + u8 hw_wred_mode; + + u32 cir; + u32 pir; + u32 cbs; + u32 xbs; + u32 cnp; + u32 enable; +} roce_cc_cfg_bw_ctrl_cmd_s; + +/* ********************************** DFX cmd between driver and mpu ********************************** */ +typedef struct roce_dfx_cache_out_cmd { + struct comm_info_head head; + + u16 func_idx; + u8 cache_index; + u8 rsvd; +} roce_dfx_cache_out_cmd_s; + + +typedef struct roce_dfx_cfg_cap_param_cmd { + struct comm_info_head head; + u16 index; + u16 rsvd; + u32 param[4]; +} roce_dfx_cfg_cap_param_cmd_s; + +typedef struct roce_dfx_cap_ctr_cmd { + struct comm_info_head head; + u16 index; + u16 rsvd; + u32 value; +} roce_dfx_cap_ctr_cmd_s; + +#endif /* ROCE_MPU_COMMON_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_ulp_common.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_ulp_common.h new file mode 100644 index 000000000..9c39b4dde --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_ulp_common.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * Description : RoCE service ulp common API b/w driver and MPU + * Author : / + * Create : / + * Notes : / + * History : / + */ + +#ifndef ROCE_MPU_ULP_COMMON_H +#define ROCE_MPU_ULP_COMMON_H + +#include "roce_mpu_common.h" + +#define ROCE_MAX_DD_ID 32 +#define ROCE_MAX_DD_SIZE 4096 +#define ROCE_SET_DD_SIZE_ONCE 1024 + +/* ********************************** AA cmd between driver and mpu ********************************** */ +typedef struct roce_ulp_aa_ctrl_ready_cmd { + struct comm_info_head head; + + u16 func_id; + u8 rsvd[2]; +} roce_ulp_aa_ctrl_ready_cmd_s; + +typedef struct roce_ulp_aa_clear_act_ctrl_bmp_cmd { + struct comm_info_head head; + + u16 func_id; + u8 rsvd[2]; +} roce_ulp_aa_clear_act_ctrl_bmp_cmd_s; + +typedef struct roce_ulp_aa_set_dd_cfg_cmd { + struct comm_info_head head; + + u8 dd_id; + u8 offset; + u16 data_len; // max:4096 + + u8 data[1024]; +} roce_ulp_aa_set_dd_cfg_cmd_s; + +typedef struct roce_ulp_aa_switch_io_cmd { + struct comm_info_head head; + u16 func_id; + u8 rsvd[2]; +} roce_ulp_aa_switch_io_cmd_s; + +typedef struct roce_ulp_aa_set_fake_data_addr_cmd { + struct comm_info_head head; + u32 fake_data_gpa_h; + u32 fake_data_gpa_l; +} roce_ulp_aa_set_fake_data_addr_cmd_s; + +#endif /* ROCE_MPU_ULP_COMMON_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_pub.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_pub.h new file mode 100644 index 000000000..aead4dc80 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_pub.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA public macros. + * Create: 2021-12-30 + */ + +#ifndef ROCE_PUB_H +#define ROCE_PUB_H + +#include "rdma_context_format.h" + + +/* ********************** sync info ************************ */ +#define ROCE_SQC_RST_STATE (0x0) +#define ROCE_SQAC_RST_STATE (0x0) +#define ROCE_RQC_RST_STATE (0x0) +#define ROCE_RCC_RST_STATE (0x0) +#define ROCE_RRWC_RST_STATE (0x0) + +#define ROCE_QPC_DELED_STATE (0xCE) +#define ROCE_RC_KICKOFF_VALUE (0x5a5acece) +#define ROCE_CACHE_LINE_SIZE (0x100) + +#define ROCE_CQC_MID_STATE_VALUE (0xe) +#define ROCE_CQC_MID_STATE (0xe0000000) + +#define ROCE_CPU_ENDIAN_LITTLE 0 + +#define ROCE_MAX_ARM_SN_NUM 4 + +#define ROCE_MKEY_MPT_IDX_OFF (8) +#define ROCE_MKEY_GET_MPT_IDX(mkey) ((mkey) >> ROCE_MKEY_MPT_IDX_OFF) + +#define ROCE_PAGE_SIZE 4096 +#define ROCE_RC_ENTRY_NUM_PER_CACELINE 8 +#define ROCE_MTT_BUFLEN_TOTAL(mtt_num) ((mtt_num) << 3) + +#define ROCE_SQWQE_CI_MASK (0xffff) + +#define ROCE_GID_LEN 16 + +#define ROCE_LOCAL_DEFAULT_PMTU 5 +#define ROCE_LOCAL_DEFAULT_MTU_CODE 0xf + +enum { + ROCE_QP_ST_RC = 0x0, /* 000 */ + ROCE_QP_ST_UC = 0x1, /* 001 */ + ROCE_QP_ST_RD = 0x2, /* 010 */ + ROCE_QP_ST_UD = 0x3, /* 011 */ + ROCE_QP_ST_XRC = 0x6, /* 110 */ + ROCE_QP_ST_PRIV = 0x7 /* 111 */ +}; +/* ********************** Macro Definition ************************ */ + +enum ROCE_SERVICE_TYPE_E { + ROCE_RC_TYPE = 0, + ROCE_UC_TYPE, + ROCE_RD_TYPE, + ROCE_UD_TYPE, + ROCE_RSVD_TYPE, + ROCE_XRC_5_TYPE = 0x5, + ROCE_XRC_TYPE = 0x6, + ROCE_XRC_6_TYPE = 0x6 +}; + +enum ROCE_RC_FLAG_E { + ROCE_UC_UD = 0, + ROCE_RC_XRC +}; + +/* Description of parameters in the *********ROCE table ******* */ +/* the same with stp */ +enum ROCE_GID_TYPE_E { + ROCE_GID_TYPE_V2_IPV4 = 0, + ROCE_GID_TYPE_V2_IPV6 = 1, + ROCE_GID_TYPE_V1 = 2 +}; + +enum ROCE_SQWQE_MSGTYPE_E { + ROCE_TX_MSGTYPE_SEND = 0, + ROCE_TX_MSGTYPE_WRITE, + ROCE_TX_MSGTYPE_READ, + ROCE_TX_MSGTYPE_ATOMIC, + ROCE_TX_MSGTYPE_LOCAL, + ROCE_TX_MSGTYPE_RESIZECQ = 5, + ROCE_TX_MSGTYPE_RSVD6 = 6, + ROCE_TX_MSGTYPE_ERR = 7 +}; + +enum ROCE_SQWQE_OPTYPE_E { + ROCE_TX_SEND = 0, + ROCE_TX_SEND_INVALIDATE, + ROCE_TX_SEND_IMMEDIATE, + ROCE_TX_OPTYPE_RSVD3, + + ROCE_TX_WRITE = 4, + ROCE_TX_WRITE_IMMEDIATE, + ROCE_TX_OPTYPE_RSVD6, + ROCE_TX_OPTYPE_RSVD7, + + ROCE_TX_READ = 8, + ROCE_TX_OPTYPE_RSVD9, + ROCE_TX_OPTYPE_RSVD10, + ROCE_TX_EXT_ATOMIC_COMPARE_SWAP, + + ROCE_TX_ATOMIC_COMPARE_SWAP = 0xc, + ROCE_TX_ATOMIC_FETCH_ADD, + ROCE_TX_ATOMIC_MASKED_COMPARE_SWAP, + ROCE_TX_ATOMIC_MASKED_FETCH_ADD, + + ROCE_FAST_REG_PMR = 0x10, + ROCE_LOCAL_INVALIDATE, + ROCE_BIND_MW_TYPE1_TYPE2, + ROCE_REG_SIG_MR, + ROCE_LOCAL_EXT, + ROCE_TX_OPTYPE_RSVD15, + ROCE_RESIZE_TYPE = 0x16, + ROCE_TX_OPTYPE_RSVD17, + ROCE_TX_OPTYPE_RSVD18, + ROCE_TX_OPTYPE_RSVD19, + ROCE_TX_OPTYPE_RSVD1A, + ROCE_TX_OPTYPE_RSVD1B, + ROCE_TX_OPTYPE_RSVD1C, + ROCE_TX_OPTYPE_RSVD1D, + ROCE_ERR_TYPE = 0x1e, + ROCE_TX_OPTYPE_RSVD1F +}; + +enum ROCE_SQPC_STATE_E { + ROCE_SQPC_STATE_SW = 0, + ROCE_SQPC_STATE_ERR = 1, + ROCE_SQPC_STATE_HW = 0xF +}; + +enum ROCE_SRQC_STATE_E { + ROCE_SRQC_STATE_SW = 0, + ROCE_SRQC_STATE_ERR = 1, + ROCE_SRQC_STATE_HW = 0xF +}; + +enum ROCE_CQC_STATE_E { + ROCE_CQC_STATE_SW = 0, + ROCE_CQC_STATE_ERR = 1, + ROCE_CQC_STATE_OVERFLOW = 2, + ROCE_CQC_STATE_HW = 0xF +}; + +enum ROCE_MPT_STATE_E { + ROCE_MPT_STATE_VALID = 1, + ROCE_MPT_STATE_FREE = 3, + ROCE_MPT_STATE_ABORT = 4, + ROCE_MPT_STATE_INVALID = 0xF +}; + +enum ROCE_MPT_R_W_E { + ROCE_MPT_MW = 0, + ROCE_MPT_MR +}; + +enum ROCE_MPT_BQP_E { + ROCE_MPT_BQP_TYPE1 = 0, + ROCE_MPT_BQP_TYPE2B +}; + +enum ROCE_MPT_DIF_MODE_E { + ROCE_MPT_DIF_MODE_INS = 0, + ROCE_MPT_DIF_MODE_DEL, + ROCE_MPT_DIF_MODE_FWD +}; + +enum ROCE_MPT_SECTOR_SIZE_E { + ROCE_MPT_SECTOR_SIZE_512 = 0, + ROCE_MPT_SECTOR_SIZE_4KB +}; + +enum ROCE_MPT_METEDATA_SIZE_E { + ROCE_MPT_METEDATA_SIZE_8 = 0, + ROCE_MPT_METEDATA_SIZE_64 +}; + + +enum ROCE_MPT_SGL_MODE_E { + ROCE_MPT_SGL_MODE_SINGLE = 0, + ROCE_MPT_SGL_MODE_DOUBLE +}; + +enum ROCE_QPC_STATE_E { + ROCE_QPC_STATE_RST = 0, + ROCE_QPC_STATE_INIT, + ROCE_QPC_STATE_RTR, + ROCE_QPC_STATE_RTS, + ROCE_QPC_STATE_SQD, + ROCE_QPC_STATE_SQEr, + ROCE_QPC_STATE_ERR, + ROCE_QPC_STATE_DRAINING, + ROCE_QPC_STATE_RSV +}; + + +enum ROCE_MTT_LAYER_NUM_E { + ROCE_MTT_LAYER_NUM_0 = 0, + ROCE_MTT_LAYER_NUM_1, + ROCE_MTT_LAYER_NUM_2, + ROCE_MTT_LAYER_NUM_3, + ROCE_MTT_LAYER_NUM_RSVD +}; + +enum ROCE_CQE_TYPE_E { + /* *1-Send Completion; 0-Receive Completion */ + ROCE_RQ_CQE = 0, + ROCE_SQ_CQE +}; + +enum ROCE_CQE_SIZE_E { + ROCE_CQE_SIZE_0 = 0, /* * 4B */ + ROCE_CQE_SIZE_1 = 1, /* * 8B */ + ROCE_CQE_SIZE_2 = 2, /* * 16B */ + ROCE_CQE_SIZE_3 = 3 /* * 32B, RoCE fix 3 */ +}; + +enum ROCE_CQE_RQ_OPTYPE_E { + ROCE_CQE_RQ_OPTYPE_WRITE_IMMEDIATE = 0, + ROCE_CQE_RQ_OPTYPE_SEND, + ROCE_CQE_RQ_OPTYPE_SEND_IMMEDIATE, + ROCE_CQE_RQ_OPTYPE_SEND_INVALIDATE, + ROCE_CQE_RQ_OPTYPE_WRITE, + ROCE_CQE_RQ_OPTYPE_READ +}; + +enum ROCE_CQE_COMMON_OPTYPE_E { + ROCE_CQE_COMMON_OPTYPE_RESIZE = 0x16, + ROCE_CQE_COMMON_OPTYPE_ERR = 0x1e +}; + +enum ROCE_QPC_MTU_E { + ROCE_PMTU_256B = 1, + ROCE_PMTU_512B = 2, + ROCE_PMTU_1KB = 3, + ROCE_PMTU_2KB = 4, + ROCE_PMTU_4KB = 5 +}; + +enum { + ROCE_DB_MTU_256B_SHIFT = 0, + ROCE_DB_MTU_512B_SHIFT = 1, + ROCE_DB_MTU_1K_SHIFT = 2, + ROCE_DB_MTU_2K_SHIFT = 3, + ROCE_DB_MTU_4K_SHIFT = 4, +}; + +enum ROCE_FLOW_ID_E { + ROCE_STL_TIMER_FLOW = 0, + ROCE_PKT_FLOW = 1, + ROCE_DB_FLOW = 2, + ROCE_TIMER_FLOW = 3, + ROCE_ARM_FLOW = 4, + ROCE_CMDQ_FLOW = 5, + ROCE_NRET_FLOW = 6, + ROCE_STL2STF_FLOW = 7, +}; + +#endif /* ROCE_PUB_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_pub_cmd.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_pub_cmd.h new file mode 100644 index 000000000..8202efdf4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_pub_cmd.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA public commonds. + * Create: 2021-12-30 + */ + +#ifndef ROCE_PUB_CMD_H +#define ROCE_PUB_CMD_H + +#ifndef CQM_AEQ_BASE_T_ROCE +#define CQM_AEQ_BASE_T_ROCE 16 +#endif + +/* RoCE EVENT */ +enum { + ROCE_EVENT_TYPE_OFED_NO_DEF = (CQM_AEQ_BASE_T_ROCE + 0x00), + ROCE_EVENT_TYPE_PATH_MIG = (CQM_AEQ_BASE_T_ROCE + 0x01), /* RSVD */ + ROCE_EVENT_TYPE_COMM_EST = (CQM_AEQ_BASE_T_ROCE + 0x02), + ROCE_EVENT_TYPE_SQ_DRAINED = (CQM_AEQ_BASE_T_ROCE + 0x03), + ROCE_EVENT_TYPE_SRQ_QP_LAST_WQE = (CQM_AEQ_BASE_T_ROCE + 0x04), + + /* 5 */ + ROCE_EVENT_TYPE_WQ_CATAS_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x05), + ROCE_EVENT_TYPE_PATH_MIG_FAILED = (CQM_AEQ_BASE_T_ROCE + 0x06), + ROCE_EVENT_TYPE_WQ_INVAL_REQ_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x07), + ROCE_EVENT_TYPE_WQ_ACCESS_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x08), + ROCE_EVENT_TYPE_CQ_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x09), + + /* 10 */ + ROCE_EVENT_TYPE_SRQ_LIMIT = (CQM_AEQ_BASE_T_ROCE + 0x0a), + ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x0b), + ROCE_EVENT_TYPE_LOCAL_CATAS_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x0c), /* RSVD */ + ROCE_EVENT_TYPE_MR_SIG_ERR = (CQM_AEQ_BASE_T_ROCE + 0x0e), + + ROCE_EVENT_TYPE_ODP_PAGE_FAULT = (CQM_AEQ_BASE_T_ROCE + 0x0f), + /* ROCE NOF AA */ + ROCE_EVENT_TYPE_SWITCH_HOST = (CQM_AEQ_BASE_T_ROCE + 0x10), + ROCE_EVENT_TYPE_HOST_FAILOVER = (CQM_AEQ_BASE_T_ROCE + 0x11), + ROCE_EVENT_NOFAA_STUB = (CQM_AEQ_BASE_T_ROCE + 0x12), + + /* * RSVE */ + ROCE_EVENT_TYPE_EEC_CATAS_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x30), + ROCE_EVENT_TYPE_PORT_CHANGE = (CQM_AEQ_BASE_T_ROCE + 0x31), + ROCE_EVENT_TYPE_ECC_DETECT = (CQM_AEQ_BASE_T_ROCE + 0x32), + ROCE_EVENT_TYPE_VEP_UPDATE = (CQM_AEQ_BASE_T_ROCE + 0x33), + ROCE_EVENT_TYPE_FATAL_WARNING = (CQM_AEQ_BASE_T_ROCE + 0x34), + ROCE_EVENT_TYPE_FLR_EVENT = (CQM_AEQ_BASE_T_ROCE + 0x35), + ROCE_EVENT_TYPE_PORT_MNG_CHG_EVENT = (CQM_AEQ_BASE_T_ROCE + 0x36), + ROCE_EVENT_TYPE_XRC_DOMAIN_VIOLATION_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x37), + ROCE_EVENT_TYPE_INVALID_XRCETH_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x38), + ROCE_EVENT_TYPE_FLUSH_WQE_ERROR = (CQM_AEQ_BASE_T_ROCE + 0x39), + + ROCE_EVENT_TYPE_EQ_OVERFLOW = (CQM_AEQ_BASE_T_ROCE + 0x40), + ROCE_EVENT_TYPE_CMD = (CQM_AEQ_BASE_T_ROCE + 0x41), + ROCE_EVENT_TYPE_COMM_CHANNEL = (CQM_AEQ_BASE_T_ROCE + 0x42), + ROCE_EVENT_TYPE_OP_REQUIRED = (CQM_AEQ_BASE_T_ROCE + 0x43), + + ROCE_EVENT_TYPE_NONE = (CQM_AEQ_BASE_T_ROCE + 0x50) +}; + + +enum { + /* GID CMD */ + ROCE_CMD_UPDATE_GID = 0x60, + ROCE_CMD_QUERY_GID = 0x61, + ROCE_CMD_CLEAR_GID = 0x62, + + /* IP CMD */ + ROCE_CMD_ADD_IP_ENTRY = 0x68, + ROCE_CMD_DEL_IP_ENTRY = 0x69, + ROCE_CMD_LOOKUP_IP_ENTRY = 0x6a, + ROCE_CMD_UPDATE_IP_ENTRY = 0x6b, + + /* TPT CMD */ + ROCE_CMD_SW2HW_MPT = 0x70, + ROCE_CMD_HW2SW_MPT = 0x71, + ROCE_CMD_MODIFY_MPT = 0x72, + ROCE_CMD_QUERY_MPT = 0x73, + ROCE_CMD_FLUSH_TPT = 0x74, + ROCE_CMD_SYNC_TPT = 0x75, + + /* CQ CMD */ + ROCE_CMD_SW2HW_CQ = 0x80, + ROCE_CMD_RESIZE_CQ = 0x81, + ROCE_CMD_MODIFY_CQ = 0x82, + ROCE_CMD_HW2SW_CQ = 0x83, + ROCE_CMD_QUERY_CQ = 0x84, + + /* SRQ CMD */ + ROCE_CMD_SW2HW_SRQ = 0x90, + ROCE_CMD_ARM_SRQ = 0x91, + ROCE_CMD_HW2SW_SRQ = 0x92, + ROCE_CMD_QUERY_SRQ = 0x93, + + /* QP CMD */ + ROCE_CMD_QP_BASE = 0xa0, + ROCE_CMD_RST2INIT_QP = 0xa0, + ROCE_CMD_INIT2INIT_QP = 0xa1, + ROCE_CMD_INIT2RTR_QP = 0xa2, + ROCE_CMD_RTR2RTS_QP = 0xa3, + ROCE_CMD_RTS2RTS_QP = 0xa4, + ROCE_CMD_SQERR2RTS_QP = 0xa5, + ROCE_CMD_2ERR_QP = 0xa6, + ROCE_CMD_RTS2SQD_QP = 0xa7, + ROCE_CMD_SQD2SQD_QP = 0xa8, + ROCE_CMD_SQD2RTS_QP = 0xa9, + ROCE_CMD_2RST_QP = 0xaa, + ROCE_CMD_QUERY_QP = 0xab, + ROCE_CMD_MIRROR_QP = 0xac, /* DFX RoCE +/- packet mirroring */ + ROCE_CMD_MODIFY_HASH_VALUE_QP = 0xad, + ROCE_CMD_GET_QP_RX_PORT = 0xae, + ROCE_CMD_MODIFY_UDP_SRC_PORT_QP = 0xaf, + ROCE_CMD_GET_UDP_SRC_PORT_QP = 0xb0, + ROCE_CMD_GET_QP_FUNC_TABLE = 0xb1, + ROCE_CMD_QP_MAX = 0xb1, + /* Miscellaneous CMD */ + // ROCE_CMD_NOP = 0xb0, + + /* MTT commands */ + ROCE_CMD_QUERY_MTT = 0xc0, + + ROCE_CMD_MODIFY_CONTEXT = 0xd0, + ROCE_CMD_EN_QP_CAP_PKT = 0xd1, + ROCE_CMD_DIS_QP_CAP_PKT = 0xd2, + + ROCE_CMD_MISC_CACHE_INVLD = 0xe0, + + ROCE_CMD_MISC_CQ_CACHE_INVLD = 0xf0, + + ROCE_CMD_CREAT_SLAVE_QP = 0xf1, + ROCE_CMD_QUERY_MASTER_QP_BITMAP = 0xf2, + ROCE_CMD_GET_MASTER_QPN = 0xf3, + ROCE_CMD_SET_CONN_STAT = 0xf4, + ROCE_CMD_DISCONNECT_QP = 0xf5, + ROCE_CMD_SET_SHARD_CFG = 0xf6 +}; + +enum roce3_cmd_type { + COMMON_CMD_TX_INFO = 1, + COMMON_CMD_Q_NUM, + COMMON_CMD_TX_WQE_INFO, + COMMON_CMD_TX_MAPPING, + COMMON_CMD_RX_INFO, + COMMON_CMD_RX_WQE_INFO, + COMMON_CMD_RX_CQE_INFO, + COMMON_CMD_UPRINT_FUNC_EN, + COMMON_CMD_UPRINT_FUNC_RESET, + COMMON_CMD_UPRINT_SET_PATH, + COMMON_CMD_UPRINT_GET_STATISTICS, + COMMON_CMD_FUNC_TYPE, + COMMON_CMD_GET_FUNC_IDX, + COMMON_CMD_GET_INTER_NUM, + COMMON_CMD_CLOSE_TX_STREAM, + COMMON_CMD_GET_DRV_VERSION, + COMMON_CMD_CLEAR_FUNC_STASTIC, + COMMON_CMD_GET_HW_STATS, + COMMON_CMD_CLEAR_HW_STATS, + COMMON_CMD_GET_SELF_TEST_RES, + COMMON_CMD_GET_CHIP_FAULT_STATS, + COMMON_CMD_NIC_RSVD1, + COMMON_CMD_NIC_RSVD2, + COMMON_CMD_NIC_RSVD3, + COMMON_CMD_GET_CHIP_ID, + COMMON_CMD_GET_SINGLE_CARD_INFO, + COMMON_CMD_GET_FIRMWARE_ACTIVE_STATUS, + COMMON_CMD_ROCE_DFX_FUNC, + COMMON_CMD_GET_DEVICE_ID, + COMMON_CMD_GET_PF_DEV_INFO, + COMMON_CMD_CMD_FREE_MEM, + COMMON_CMD_GET_LOOPBACK_MODE = 32, + COMMON_CMD_SET_LOOPBACK_MODE, + COMMON_CMD_SET_LINK_MODE, + COMMON_CMD_SET_PF_BW_LIMIT, + COMMON_CMD_GET_PF_BW_LIMIT, + COMMON_CMD_ROCE_CMD, + COMMON_CMD_GET_POLL_WEIGHT, + COMMON_CMD_SET_POLL_WEIGHT, + COMMON_CMD_GET_HOMOLOGUE, + COMMON_CMD_SET_HOMOLOGUE, + COMMON_CMD_GET_SSET_COUNT, + COMMON_CMD_GET_SSET_ITEMS, + COMMON_CMD_IS_DRV_IN_VM, + COMMON_CMD_LRO_ADPT_MGMT, + COMMON_CMD_SET_INTER_COAL_PARAM, + COMMON_CMD_GET_INTER_COAL_PARAM, + COMMON_CMD_GET_CHIP_INFO, + COMMON_CMD_GET_NIC_STATS_LEN, + COMMON_CMD_GET_NIC_STATS_STRING, + COMMON_CMD_GET_NIC_STATS_INFO, + COMMON_CMD_GET_PF_ID, + COMMON_CMD_NIC_RSVD4, + COMMON_CMD_NIC_RSVD5, + COMMON_CMD_DCB_QOS_INFO, + COMMON_CMD_DCB_PFC_STATE, + COMMON_CMD_DCB_ETS_STATE, + COMMON_CMD_DCB_STATE, + COMMON_CMD_QOS_DEV, + COMMON_CMD_NIC_RSVD7, + COMMON_CMD_GET_ULD_DEV_NAME, + + COMMON_CMD_RSS_CFG = 0x40, + COMMON_CMD_RSS_INDIR, + COMMON_CMD_PORT_ID, + + COMMON_CMD_GET_FUNC_CAP = 0x50, + + COMMON_CMD_GET_WIN_STAT = 0x60, + COMMON_CMD_WIN_CSR_READ = 0x61, + COMMON_CMD_WIN_CSR_WRITE = 0x62, + COMMON_CMD_WIN_API_CMD_RD = 0x63, + + ROCE_CMD_GET_QPC_FROM_CACHE = 0x80, + ROCE_CMD_GET_QPC_FROM_HOST = 0x81, + ROCE_CMD_GET_CQC_FROM_CACHE = 0x82, + ROCE_CMD_GET_CQC_FROM_HOST = 0x83, + ROCE_CMD_GET_SRQC_FROM_CACHE = 0x84, + ROCE_CMD_GET_SRQC_FROM_HOST = 0x85, + ROCE_CMD_GET_MPT_FROM_CACHE = 0x86, + ROCE_CMD_GET_MPT_FROM_HOST = 0x87, + ROCE_CMD_GET_GID_FROM_CACHE = 0x88, + ROCE_CMD_GET_QPC_CQC_PI_CI = 0x89, + ROCE_CMD_GET_QP_COUNT = 0x8a, + ROCE_CMD_GET_DEV_ALGO = 0x8b, + + ROCE_CMD_START_CAP_PACKET = 0x90, + ROCE_CMD_STOP_CAP_PACKET = 0x91, + ROCE_CMD_QUERY_CAP_INFO = 0x92, + ROCE_CMD_ENABLE_QP_CAP_PACKET = 0x93, + ROCE_CMD_DISABLE_QP_CAP_PACKET = 0x94, + ROCE_CMD_QUERY_QP_CAP_INFO = 0x95, + + ROCE_CMD_ENABLE_BW_CTRL = 0xa0, + ROCE_CMD_DISABLE_BW_CTRL = 0xa1, + ROCE_CMD_CHANGE_BW_CTRL_PARAM = 0xa2, + ROCE_CMD_QUERY_BW_CTRL_PARAM = 0xa3, + + ROCE_CMD_TIMEOUT_ALARM = 0xb0, + COMMON_CMD_VM_COMPAT_TEST = 0xFF +}; + +enum roce3_cmd_ctx_type { + ROCE_CMD_CTX_MODIFY_QPC = 0X0, + ROCE_CMD_CTX_MODIFY_MPT = 0X1, + ROCE_CMD_CTX_MODIFY_CQC = 0X2, + ROCE_CMD_CTX_MODIFY_SRQC = 0X3, + ROCE_CMD_CTX_MODIFY_WQE_PI_CI = 0X4, + ROCE_CMD_CTX_FETCH_WQE = 0X5, + ROCE_CMD_CTX_DEL_TIMER = 0X6, + ROCE_CMD_CTX_LB_SQDB = 0X7 +}; + +enum roce3_modify_fetch_wqe_cmd_type { + ROCE_CMD_FCH_WQE_ACKCI = 1, + ROCE_CMD_FCH_WQE_UPDATE = 2 +}; + +enum roce3_gid_type { + ROCE_IPv4_ROCEv2_GID = 0, + ROCE_IPv6_ROCEv2_GID = 1, + ROCE_ROCEv1_GID = 2, + ROCE_INV_GID +}; + +#endif /* ROCE_PUB_CMD_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_ulp.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_ulp.h new file mode 100644 index 000000000..9a242b343 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_ulp.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA upper level macros. + * Create: 2021-12-30 + */ + +#ifndef ROCE_ULP_H +#define ROCE_ULP_H + +#include "pub_base_defs.h" + +/* *********ECN alpha SHIFT******* */ +#define ECN_ALPHA_MAGNIFICATION_SHIFT (21) + +/* ********************** NOFAA start ************************ */ +enum ROCE_NOFAA_QP_CTX_OFF_E { + ROCE_NOFAA_CTX_TIMER_OFF = 0, + ROCE_NOFAA_CTX_SW_OFF = 32, + ROCE_NOFAA_CTX_SW_SQC_OFF = 96, + ROCE_NOFAA_CTX_SW_SQAC_OFF = 116, + ROCE_NOFAA_CTX_SW_RQC_OFF = 148, + ROCE_NOFAA_CTX_SW_RQAC_OFF = 168 +}; + +#define ROCE_VERBS_NOFAA_TIMERC_OFFSET_16B_ALIGN (ROCE_NOFAA_CTX_TIMER_OFF >> 4) +#define ROCE_VERBS_NOFAA_SW_OFFSET_16B_ALIGN (ROCE_NOFAA_CTX_SW_OFF >> 4) + +/* API */ +#define ROCE_NOFAA_WQE2HOST_SM_NODE NODE_ID_SMF0 +#define ROCE_NOFAA_CMIDINFO_SM_MODE NODE_ID_SMF0 +#define SML_INST_MASTER_QPC 20 + +#define ROCE_BMP_LOAD_BYTE 64 +#define ROCE_BMP_ENTRY_BY_64B ((ROCE_QPC_TABLE_SIZE>>6) + 1) +#define ROCE_BMP_RSVD_BYTE 32 +#define ROCE_NOFAA_QPN_RSVD 0x2 +#define ROCE_REVERSE_PER_64B_SHIFT 4 + +#define ROCE_MQP_LT_RSVD 100 // (64 + 12kbit / 8) / 16 +#define ROCE_ACT_HOST_LT_RSVD 4 // (64) / 16 +#define ROCE_HASH_LT_RSVD 17920 // (0xA1000 - 0x5B000) / 16 +#define ROCE_SHARD_HASH_LT_RSVD 8960 // (0x8DC00 - 0x6AC00) / 16 +#define ROCE_HASH_LT_RSVD_MUL_SML (ROCE_HASH_LT_RSVD >> ROCE_NOFAA_PORT_NUM_SHIFT) +#define ROCE_LT_64B_IDX_SHIFT 2 +#define ROCE_LT_64B_ENTRY_NUM 4 + +#define ROCE_NOFAA_HASH_WORD_EN 0x400 +#define ROCE_NOFAA_HASH_API_KEY_LEN 4 +#define ROCE_NOFAA_BITHEAP_ID0 0 +#define ROCE_NOFAA_RSVD_BMPIDX_NUM 2 +#define ROCE_NOFAA_MASTER_BMPIDX_BASE 0x3002 +#define ROCE_NOFAA_CM_QPN_INDEX 0x3001 +#define ROCE_NOFAA_FLR_STUB_INDEX 0x2fff +#define ROCE_NOFAA_QPN2BMPIDX(xid) ((xid) + ROCE_NOFAA_MASTER_BMPIDX_BASE - ROCE_NOFAA_QPN_RSVD) +#define ROCE_NOFAA_BMPIDX2QPN(bmp_idx) ((bmp_idx) + ROCE_NOFAA_QPN_RSVD - ROCE_NOFAA_MASTER_BMPIDX_BASE) +#define ROCE_NOFAA_GET_ACT_HOST_IDX(xid, host_id) (((xid) << 2) + (((host_id) & 0x3) ^ 0x3)) + +#define ROCE_NOFAA_GIDIDX_MASK 0x3f +#define ROCE_NOFAA_GIDIDX_RSVD_MASK 0xc0 + +/* cfg */ +#define NOFAA_SRC_TAG_L (global_share_space.global_config.dw6.bs.master_func) +#define ROCE_NOFAA_HOSTID_MASK (global_share_space.global_config.dw6.bs.host_mask) +#define ROCE_NOFAA_HOST_NUM (global_share_space.global_config.dw6.bs.host_num) +#define ROCE_NOFAA_PORT_NUM (global_share_space.global_config.dw6.bs.port_num) +#define ROCE_NOFAA_HOST_NUM_SHIFT (global_share_space.global_config.dw6.bs.host_shift) +#define ROCE_NOFAA_PORT_NUM_SHIFT (global_share_space.global_config.dw6.bs.port_shift) +#define ROCE_NOFAA_PORT_NUM_MASK (global_share_space.global_config.dw6.bs.port_mask) +#define ROCE_NOFAA_MAX_HOST_NUM 4 +#define ROCE_NOFAA_HASH_POOL_IO_NUM (ROCE_NOFAA_MAX_HASH_NUM >> ROCE_NOFAA_PORT_NUM_SHIFT) +#define ROCE_NOFAA_SRQN_BASE 2 +#define ROCE_NOFAA_SRQN_MASK 0x7 +#define ROCE_NOFAA_SRQN_NUM 8 + +#define ROCE_NOFAA_MAX_QPN_SHIFT 12 +#define ROCE_NOFAA_PORT_QP_NUM_SHIFT (ROCE_NOFAA_MAX_QPN_SHIFT - ROCE_NOFAA_PORT_NUM_SHIFT) +#define ROCE_NOFAA_PORT_QP_NUM (1u << ROCE_NOFAA_PORT_QP_NUM_SHIFT) +#define ROCE_NOFAA_PORT_QP_NUM_MASK (ROCE_NOFAA_PORT_QP_NUM - 1) +#define ROCE_AA_SWITCH_QP_NUM 4 +#define ROCE_AA_SWITCH_QPN (4095 + 1) +#define ROCE_AA_SWITCH_MAX_QPN (ROCE_AA_SWITCH_QPN + ROCE_AA_SWITCH_QP_NUM) +#define ROCE_QP0 0x0 +#define ROCE_CM_QPN 0x1 +#define ROCE_AA_QID_NUM 9 +#define ROCE_NVME_QID_GP_SHIFT 1 +#define ROCE_NVME_QID_GP_MASK 1 + +#define NEXT_IO_SPF_GET(start_spf, index) ((start_spf) + ((index) << 7)) +#define NEXT_SPF_GET(start_spf, index) ((start_spf) + ((index) << 6)) + +#define ROCE_NOFAA_VFID2HOSTIDX(vf_id) (((vf_id) >> ROCE_NOFAA_PORT_NUM_SHIFT) & ROCE_NOFAA_HOSTID_MASK) +#define ROCE_NOFAA_VFID2PORTID(vf_id) ((vf_id) & ROCE_NOFAA_PORT_NUM_MASK) +#define ROCE_NOFAA_GET_VFID(hostid, er_fwd_id) (u16)((((hostid) & ROCE_NOFAA_HOSTID_MASK) << \ + ROCE_NOFAA_PORT_NUM_SHIFT) + ((er_fwd_id) & ROCE_NOFAA_PORT_NUM_MASK)) +#define ROCE_NOFAA_SLAVE_ALIVE_GET(active_bmp, slave_id) ((active_bmp) & (1u << ((slave_id) & ROCE_NOFAA_HOSTID_MASK))) +#define ROCE_AA_SRCCHNL2HOST(src_chnl) (((src_chnl) >> 3) & 0x3) +#define ROCE_NOFAA_GET_GID_IDX(qpc, host_id) (*((u8 *)&((qpc)->nofaa_ctx.dw1.value) + (host_id)) & 0x3f) +/* ROCE NOFAA(QPC512):CID[19:0] = {XID[12:4],XID[12:4],XID[3:2]} */ +#define roce_nofaa_calc_cid_by_xid(xid) ((((xid)&0x3ffe0) << 6) | (((xid)&0x7ff8) >> 3)) +#define ROCE_NOFAA_BITMAP_CLEAR(bmp, idx) ((bmp) &= ((1u << (idx)) ^ 0xffffffff)) +#define ROCE_NOFAA_BITMAP_SET(bmp, idx) ((bmp) |= (1u << (idx))) +#define ROCE_NOFAA_BITMAP_GET(bmp, idx) ((bmp) & (1u << (idx))) +#define ROCE_NOFAA_BITWISE_COMPARE(x, y) ((x) ^ (y)) +/* GET CMINFO TABLE */ +#define ROCE_GET_CMINFO_ADDR(sp_addr, index) \ + ((roce_nof_cm_ctx_s *)(sp_addr) + (((index) >> ROCE_LT_XID_LB_SHIFT) & ROCE_CMINFO_PER_16B_MASK)) + +#define ROCE_NOFAA_QUERY_BMP_SIZE ((ROCE_NOFAA_PORT_QP_NUM) >> 3) +#define ROCE_NOFAA_GET_PORT_QPNUM_BYTE(port_id) ((u32)((port_id) << ROCE_NOFAA_PORT_QP_NUM_SHIFT) >> 3) + +/* switch */ +#define ROCE_SWITCH_COUNTER_BASE 0x4000 + +/* timer */ +#define ROCE_NOFAA_TIME_DLY_STEP 2047 +#define ROCEAA_TIMER_DLY_STEP(dly_step) (((dly_step) < ROCE_NOFAA_TIME_DLY_STEP) ? \ + (dly_step) : ROCE_NOFAA_TIME_DLY_STEP) + +/* data struct */ +typedef struct tag_roce_nof_cm_ctx { + u32 local_comm_id; + u32 remote_comm_id; +} roce_nof_cm_ctx_s; + +typedef struct tag_nofaa_shard_hash_key { + u32 xid : 16; + u32 lun_id : 16; +} nofaa_shard_hash_key; + +typedef struct tag_nofaa_shard_hash_item { + struct { + u32 volume_id : 24; + u32 dd_id : 8; + } bs; + + u8 hash_low_cnt; + u8 hash_high_cnt; + u8 hash_low_offset; + u8 hash_high_offset; +} nofaa_shard_hash_item; + +typedef struct tag_nofaa_shard_hash_entry { + nofaa_shard_hash_key key; + nofaa_shard_hash_item item; +} nofaa_shard_hash_entry; + +typedef struct tag_nofaa_shard_hash_value { + union { + struct { + u32 code : 2; + u32 rsvd0 : 30; + } bs; + u32 value; + } dw0; + u32 rsvd0; + nofaa_shard_hash_item item; +} nofaa_shard_hash_value_s; + +typedef struct tag_nofaa_shard_lt_value { + union { + struct { + u32 v : 1; + u32 s : 1; + u32 b : 1; + u32 rsvd0 : 5; + u32 hash_value : 16; + u32 rsvd1 : 8; + } bs; + u32 value; + } dw0; + nofaa_shard_hash_key key; + nofaa_shard_hash_item item; +} nofaa_shard_lt_value_s; + +/* ********************** NOFAA end ************************ */ + +#endif /* ROCE_ULP_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_vbs_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_vbs_format.h new file mode 100644 index 000000000..f030367ce --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_vbs_format.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA offloaded VBS context. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VBS_FORMAT_H +#define ROCE_VBS_FORMAT_H + +#include "roce_wqe_format.h" +#include "roce_xqe_format.h" + +#ifdef ROCE_VBS_EN + +typedef struct roce_wqe_vbs_rdma_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; /* Length of the data sent by the SQ WQE */ + + /* DW2 */ + u32 dw2; + + /* DW3 */ + roce3_wqe_tsk_misc_seg_u dw3; +} roce_wqe_vbs_rdma_tsk_seg_s; +#else + +typedef union roce_wqe_vbs_tsk_misc_seg { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 request_id : 16; + u32 xts_vld : 1; + u32 rq_buf_shift : 4; + u32 sio_grp_num : 3; + u32 sio_grp4_len : 8; + + u32 sio_grp3_len : 8; + u32 sio_grp2_len : 8; + u32 sio_grp1_len : 8; + u32 sio_grp0_len : 8; +#else + u32 sio_grp0_len : 8; + u32 sio_grp1_len : 8; + u32 sio_grp2_len : 8; + u32 sio_grp3_len : 8; + + u32 sio_grp4_len : 8; + u32 sio_grp_num : 3; + u32 rq_buf_shift : 4; + u32 xts_vld : 1; + u32 request_id : 16; +#endif + } bs; + u64 value; +} roce_wqe_vbs_tsk_misc_seg_u; + +typedef struct roce_wqe_vbs_aad_seg { + union { + struct { + u32 pdu_difx_en : 1; + u32 pad_len_vld : 1; + u32 pdu_pad_len : 2; + u32 smd_tp : 4; + u32 rsvd0 : 1; + u32 msg_hdr_vld : 1; + u32 msg_hdr_len : 2; + u32 rd_difx_rslt : 1; + u32 vbs_difx : 1; + u32 rsvd1 : 1; + u32 pdu_difx_cnt : 9; + u32 rsvd2 : 4; + u32 sio_num : 4; + } bs; + u32 value; + } dw0; + + union { + struct { + u32 fst_pdu : 1; + u32 fst_sct : 1; + u32 last_pdu : 1; + u32 rsp_indiv : 1; + u32 sct_sz : 1; + u32 dsgl : 1; + u32 rsp_vld : 1; + u32 rsp_len : 5; + u32 app_esc : 1; + u32 ref_esc : 1; + u32 sct_v_tp : 2; + u32 grd_v_en : 1; + u32 grd_rid : 2; + u32 grd_v_agm : 1; + u32 grd_ri_agm : 1; + u32 grd_agm_ini : 1; + u32 crc16_ini : 1; + u32 ipcs_ini : 1; + u32 ref_v_en : 1; + u32 ref_rid : 2; + u32 ref_v_inc : 1; + u32 ref_ri_inc : 1; + u32 app_v_en : 1; + u32 app_rid : 2; + } bs; + u32 value; + } dw1; + + union { + struct { + u32 task_tag : 16; + u32 rep_app_tag : 16; + } bs; + u32 value; + } dw2; + + union { + struct { + u32 cmp_app_tag : 16; + u32 cmp_app_tag_msk : 16; + } bs; + u32 value; + } dw3; + + u32 cmp_ref_tag; + + u32 rep_ref_tag; + + union { + struct { + u32 pdu_sd_ofs : 13; + u32 rsvd0 : 1; + u32 pdu_sd_len : 18; + } bs; + u32 value; + } dw6; +} roce_wqe_vbs_aad_seg_s; + +typedef struct roce_wqe_vbs_subinfo { + union { + struct { + u32 sio0_size : 4; + u32 sio1_size : 4; + u32 sio2_size : 4; + u32 sio3_size : 4; + u32 sio4_size : 4; + u32 sio5_size : 4; + u32 sio6_size : 4; + u32 sio7_size : 4; + } bs; + u32 value; + } dw0; + + union { + struct { + u32 sio0_crc2_ini : 16; + u32 sio1_crc2_ini : 16; + } bs; + u32 value; + } dw1; + + union { + struct { + u32 sio2_crc2_ini : 16; + u32 sio3_crc2_ini : 16; + } bs; + u32 value; + } dw2; + + union { + struct { + u32 sio4_crc2_ini : 16; + u32 sio5_crc2_ini : 16; + } bs; + u32 value; + } dw3; + + union { + struct { + u32 sio6_crc2_ini : 16; + u32 sio7_crc2_ini : 16; + } bs; + u32 value; + } dw4; +} roce_wqe_vbs_subinfo_s; + +typedef struct roce_wqe_vbs_rdma_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; /* Length of the data sent by the SQ WQE */ + + /* DW2 */ + u32 wqe_ext_len; /* This parameter is valid for the immediate data operation or SEND invalidate. */ + + /* DW3 */ + roce3_wqe_tsk_misc_seg_u dw3; + + /* DW4~5 */ + roce_wqe_vbs_tsk_misc_seg_u misc; + + u32 rsvd[2]; + + roce_wqe_vbs_aad_seg_s vbs_aad; +} roce_wqe_vbs_rdma_tsk_seg_s; + +#endif + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr.h new file mode 100644 index 000000000..e558e9a9b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr.h @@ -0,0 +1,400 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq attribute context. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_ATTR_H +#define ROCE_VERBS_ATTR_H + +#include "roce_verbs_mr_attr.h" +#include "roce_verbs_gid_attr.h" +#include "roce_verbs_cq_attr.h" +#include "roce_verbs_srq_attr.h" +#include "roce_verbs_attr_qpc_chip.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#define ROCE_VERBS_SQ_WQEBB_SIZE (2) +#define ROCE_VERBS_SQ_PI_VLD (1) + +#pragma pack(4) +/* qpc_attr_com info ,12*4B */ +typedef struct tag_roce_verbs_qpc_attr_com { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 service_type : 3; + u32 fre : 1; + u32 rwe : 1; + u32 rre : 1; + u32 rae : 1; + u32 rkey_en : 1; + u32 dest_qp : 24; +#else + u32 dest_qp : 24; /* Destination QP number, which is extended to 24 bits in consideration of interconnection + with commercial devices. */ + u32 rkey_en : 1; + u32 rae : 1; + u32 rre : 1; + u32 rwe : 1; + u32 fre : 1; /* Indicates whether the local FRPMR is enabled. */ + u32 service_type : 3; /* Transmission Type + * 000:RC + * 001:UC + * 010:RD + * 011 UD + * 101:XRC + * Other:Reserved + */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sra_max : 3; + u32 rra_max : 3; + u32 rnr_retry_limit : 3; + u32 to_retry_limit : 3; + u32 local_qp : 20; +#else + u32 local_qp : 20; /* Local QP number */ + u32 to_retry_limit : 3; /* Number of ACK retransmissions. The value 7 indicates unlimited times, and the + value 0 indicates no retransmission. */ + u32 rnr_retry_limit : 3; /* The maximum number of RNR retransmissions is 7. The value 7 indicates that the + maximum number of retransmissions is 7, and the value 0 indicates that the + retransmission is not performed. */ + u32 rra_max : 3; /* The maximum value of responser resource is 128. */ + u32 sra_max : 3; /* The maximum value of initiator depth is 128. */ +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ack_to : 5; + u32 min_rnr_nak : 5; + u32 cont_size : 2; + u32 cont_en : 1; + u32 srq_en : 1; + u32 xrc_srq_en : 1; + u32 vroce_en : 1; + u32 host_oqid : 16; +#else + u32 host_oqid : 16; + u32 vroce_en : 1; + u32 xrc_srq_en : 1; + u32 srq_en : 1; + u32 cont_en : 1; + u32 cont_size : 2; + u32 min_rnr_nak : 5; /* NAK code of RNR. This parameter is mandatory when INIT2RNR and + RTR2RTS\SQE2RTS\SQD2SQD\SQD2RTS is optional. */ + u32 ack_to : 5; +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 tss_timer_num : 3; + u32 xrc_vld : 1; + u32 srq_container : 1; + u32 invalid_credit : 1; + u32 ext_md : 1; + u32 ext_mtu : 1; + u32 dsgl_en : 1; + u32 dif_en : 1; + u32 pmtu : 3; + u32 base_mtu_n : 1; + u32 pd : 18; +#else + u32 pd : 18; + u32 base_mtu_n : 1; + u32 pmtu : 3; + u32 dif_en : 1; + u32 dsgl_en : 1; + u32 ext_mtu : 1; + u32 ext_md : 1; + u32 invalid_credit : 1; + u32 srq_container : 1; + u32 xrc_vld : 1; + u32 tss_timer_num : 3; +#endif + } bs; + + u32 value; + } dw3; + + /* DW4 */ + u32 q_key; + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ulp_type : 8; + u32 oor_en : 1; + u32 capture_en : 1; + u32 rsvd : 1; + u32 acx_mark : 1; + u32 mtu_code : 4; + u32 port : 2; + u32 ep : 3; + u32 cos : 3; + u32 so_ro : 2; + u32 dma_attr_idx : 6; +#else + u32 dma_attr_idx : 6; + u32 so_ro : 2; + u32 cos : 3; + u32 ep : 3; + u32 port : 2; + u32 mtu_code : 4; + u32 acx_mark : 1; + u32 rsvd : 1; + u32 capture_en : 1; + u32 oor_en : 1; + u32 ulp_type : 8; +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sd_mpt_idx : 12; + u32 rsvd : 20; +#else + u32 rsvd : 20; + u32 sd_mpt_idx : 12; +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 10; + u32 sq_cqn_lb : 1; + u32 rq_cqn_lb : 1; + u32 rq_cqn : 20; +#else + u32 rq_cqn : 20; + u32 rq_cqn_lb : 1; + u32 sq_cqn_lb : 1; + u32 rsvd : 10; +#endif + } bs; + u32 value; + } dw7; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 next_send_psn : 24; +#else + u32 next_send_psn : 24; + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw8; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 next_rcv_psn : 24; +#else + u32 next_rcv_psn : 24; + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw9; + + /* DW10 */ + u32 lsn; + + /* DW11 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 17; + u32 set_mpt_indx : 1; + u32 fake : 1; + u32 vf_id : 13; +#else + u32 vf_id : 13; + u32 fake : 1; + u32 set_mpt_indx : 1; + u32 rsvd : 17; +#endif + } bs; + u32 value; + } dw11; + + /* DW12 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ccf_app_id : 8; + u32 rsvd : 24; +#else + u32 rsvd : 24; + u32 ccf_app_id : 8; +#endif + } bs; + u32 value; + } dw12; +} roce_verbs_qpc_attr_com_s; + +typedef struct tag_roce_verbs_qpc_attr_path { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 bond_tx_hash_value : 16; + u32 dmac_h16 : 16; +#else + u32 dmac_h16 : 16; + u32 bond_tx_hash_value : 16; +#endif + } bs; + u32 value; + } dw0; + + u32 dmac_l32; + + /* DW2~5 */ + u8 dgid[16]; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 4; + u32 tclass : 8; + u32 flow_label : 20; +#else + u32 flow_label : 20; /* GRH flow lable */ + u32 tclass : 8; + u32 rsvd : 4; +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sl : 3; + u32 loop : 1; + u32 udp_src_port : 8; + u32 rsvd : 4; + u32 base_sgid_n : 1; + u32 sgid_index : 7; + u32 hoplmt : 8; +#else + u32 hoplmt : 8; + u32 sgid_index : 7; + u32 base_sgid_n : 1; + u32 rsvd : 4; + u32 udp_src_port : 8; + u32 loop : 1; + u32 sl : 3; +#endif + } bs; + u32 value; + } dw7; +} roce_verbs_qpc_attr_path_s; + +typedef struct roce_verbs_qpc_attr_nof_aa { + u32 gid_index; + u32 qid; + u32 local_comm_id; + u32 remote_comm_id; +} roce_verbs_qpc_attr_nof_aa_s; + +typedef struct roce_verbs_qpc_attr_vbs { + u32 sqpc_ci_record_addr_h; + u32 sqpc_ci_record_addr_l; +} roce_verbs_qpc_attr_vbs_s; + +typedef struct roce_verbs_qpc_attr_ext { + roce_verbs_qpc_attr_nof_aa_s nof_aa_info; + roce_verbs_qpc_attr_vbs_s vbs_info; +} roce_verbs_qpc_attr_ext_s; + +/* QPC Struct */ +typedef struct tag_roce_verbs_qp_attr { + /* com seg, DW0 ~ DW11 */ + roce_verbs_qpc_attr_com_s com_info; + + /* path seg, DW0 ~ DW7 */ + roce_verbs_qpc_attr_path_s path_info; + + /* chip seg, DW0 ~ DW19 */ + roce_verbs_qpc_attr_chip_s chip_seg; + + /* ext seg */ + roce_verbs_qpc_attr_ext_s ext_seg; +} roce_verbs_qp_attr_s; + + +typedef struct tag_roce_verbs_qp_hw2sw_info { + /* DW0~1 */ + u32 sq_buf_len; /* Buffer length of the SQ queue */ + u32 rq_buf_len; /* Buffer length of the RQ queue */ + + /* DW2~6 */ + roce_verbs_mtt_cacheout_info_s cmtt_cache; + + /* DW7~8 */ + union { + u64 wb_gpa; /* Address written back by the ucode after processing */ + + struct { + u32 syn_gpa_hi32; /* Upper 32 bits of the start address of mr or mw */ + u32 syn_gpa_lo32; /* Lower 32 bits of the start address of mr or mw */ + } gpa_dw; + }; + union { + struct { + u32 rsvd : 16; + u32 host_oqid : 16; + } bs; + + u32 value; + } dw9; + roce_verbs_wqe_cacheout_info_s wqe_cache; +} roce_verbs_qp_hw2sw_info_s; + +typedef struct tag_roce_verbs_modify_ctx_info { + u32 ctx_type; + u32 offset; + u32 value; + u32 mask; +} roce_verbs_modify_ctx_info_s; + +#pragma pack() + +#endif /* ROCE_VERBS_ATTR_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr_qpc_chip.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr_qpc_chip.h new file mode 100644 index 000000000..6542f838e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr_qpc_chip.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq attribute qpc chip of context . + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_ATTR_QPC_CHIP_H +#define ROCE_VERBS_ATTR_QPC_CHIP_H + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#pragma pack(4) +typedef struct tag_roce_verbs_qpc_attr_chip { + /* DW0~1 */ + union { + u64 sq_rq_l0mtt_gpa; /* hi[63:32],lo[31:03],sq_rq_gpa_sign[02:00] */ + struct { + u32 sq_rq_l0mtt_gpa_hi; + u32 sq_rq_l0mtt_gpa_lo; + } bs; + } dw0; + + /* DW2~3 */ + union { + u64 sq_rq_pi_record_gpa_at_hop_num; /* hi[63:32],lo[31:02],sq_rq_at_hop_num[01:00] */ + struct { + u32 sq_rq_pi_record_gpa_hi; + u32 sq_rq_pi_record_gpa_lo_at_hop_num; /* at_hop_num: bit[01:00] */ + } bs; + } dw2; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 qp_page_size : 4; + u32 sq_rq_mtt_page_size : 4; + u32 rsvd1 : 3; + u32 qp_signature : 5; + u32 rsvd0 : 1; + u32 dsgl : 1; + u32 rrw_mtt_prefetch_maxlen : 2; + u32 rc_size : 4; + u32 rc_max_size : 3; + u32 rq_base_ci : 5; +#else + u32 rq_base_ci : 5; + u32 rc_max_size : 3; + u32 rc_size : 4; + u32 rrw_mtt_prefetch_maxlen : 2; + u32 dsgl : 1; + u32 rsvd0 : 1; + u32 qp_signature : 5; + u32 rsvd1 : 3; + u32 sq_rq_mtt_page_size : 4; + u32 qp_page_size : 4; +#endif + } bs; + u32 value; + } dw4; + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_wqe_prefetch_maxnum : 3; + u32 sq_wqe_prefetch_minnum : 3; + u32 sq_wqe_cache_thd_sel : 2; + u32 sq_wqecnt_lth : 4; + u32 sq_wqecnt_rctl_en : 1; + u32 sq_wqecnt_rctl : 1; + u32 sq_prefetch_one_wqe : 1; + u32 sq_prewqe_mode : 1; + u32 sqa_wqe_prefetch_maxnum : 3; + u32 sqa_wqe_prefetch_minnum : 3; + u32 sqa_wqe_cache_thd_sel : 2; + u32 sq_wqe_check_en : 1; + u32 sq_pi_on_chip : 1; + u32 sq_inline_en : 1; + u32 sq_size : 5; +#else + u32 sq_size : 5; + u32 sq_inline_en : 1; + u32 sq_pi_on_chip : 1; + u32 sq_wqe_check_en : 1; + u32 sqa_wqe_cache_thd_sel : 2; + u32 sqa_wqe_prefetch_minnum : 3; + u32 sqa_wqe_prefetch_maxnum : 3; + u32 sq_prewqe_mode : 1; + u32 sq_prefetch_one_wqe : 1; + u32 sq_wqecnt_rctl : 1; + u32 sq_wqecnt_rctl_en : 1; + u32 sq_wqecnt_lth : 4; + u32 sq_wqe_cache_thd_sel : 2; + u32 sq_wqe_prefetch_minnum : 3; + u32 sq_wqe_prefetch_maxnum : 3; +#endif + } bs; + u32 value; + } dw5; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sq_wqe_prefetch_mode : 1; + u32 sq_mtt_prefetch_maxlen : 3; + u32 sqa_mtt_prefetch_maxlen : 3; + u32 srq_pd : 18; + u32 rsvd : 7; +#else + u32 rsvd : 7; + u32 srq_pd : 18; + u32 sqa_mtt_prefetch_maxlen : 3; + u32 sq_mtt_prefetch_maxlen : 3; + u32 sq_wqe_prefetch_mode : 1; +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rq_wqe_prefetch_maxnum : 3; + u32 rq_wqe_prefetch_minnum : 3; + u32 rq_wqe_cache_thd_sel : 2; + u32 rq_wqecnt_lth : 4; + u32 rq_wqecnt_rctl_en : 1; + u32 rq_wqecnt_rctl : 1; + u32 srqn : 18; +#else + u32 srqn : 18; + u32 rq_wqecnt_rctl : 1; + u32 rq_wqecnt_rctl_en : 1; + u32 rq_wqecnt_lth : 4; + u32 rq_wqe_cache_thd_sel : 2; + u32 rq_wqe_prefetch_minnum : 3; + u32 rq_wqe_prefetch_maxnum : 3; +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 srq_wqe_rthd_sel : 2; + u32 srq_rqecnt_th : 4; + u32 rq_pi_on_chip : 1; + u32 rq_inline_en : 1; + u32 rq_wqebb_size : 3; + u32 rq_size : 5; + u32 xrcd : 16; +#else + u32 xrcd : 16; + u32 rq_size : 5; + u32 rq_wqebb_size : 3; + u32 rq_inline_en : 1; + u32 rq_pi_on_chip : 1; + u32 srq_rqecnt_th : 4; + u32 srq_wqe_rthd_sel : 2; +#endif + } bs; + u32 value; + } dw8; + + /* DW9 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 container_en : 1; + u32 container_sz : 2; + u32 srq_warth_flag : 1; + u32 srq_mtt_prefetch_maxlen1 : 2; + u32 rq_mtt_prefetch_maxwqe : 3; + u32 rq_mtt_prefetch_maxlen0 : 2; + u32 rq_mtt_prefetch_maxlen1 : 2; + u32 rsvd : 19; +#else + u32 rsvd : 19; + u32 rq_mtt_prefetch_maxlen1 : 2; + u32 rq_mtt_prefetch_maxlen0 : 2; + u32 rq_mtt_prefetch_maxwqe : 3; + u32 srq_mtt_prefetch_maxlen1 : 2; + u32 srq_warth_flag : 1; + u32 container_sz : 2; + u32 container_en : 1; +#endif + } bs; + u32 value; + } dw9; + + /* DW10 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rc_entry_prefetch_maxnum : 3; + u32 rc_mtt_prefetch_maxlen : 2; + u32 rsvd : 1; + u32 rc_entry_size : 2; + u32 rc_page_gpa_h : 24; +#else + u32 rc_page_gpa_h : 24; /* bit[63:40] Indicates the start GPA of RDMARC table. The driver needs to allocate + * continuous physical address for the RDMARC table.Configured by Driver */ + u32 rc_entry_size : 2; + u32 rsvd : 1; + u32 rc_mtt_prefetch_maxlen : 2; + u32 rc_entry_prefetch_maxnum : 3; /* Maximum number of prefetch Entries for RDMARC table.000: prefetch + * number equals to zero; Others: prefetch number equals to + * (2^(rc_entry_prefetch_maxnum-1)). Configured by Driver */ +#endif + } bs; + u32 value; + } dw10; + + /* DW11 */ + u32 rc_page_gpa_l; /* bit[39:8] */ + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 1; + u32 srq_pd : 18; + u32 srq_wqebb_size : 3; + u32 srq_page_size : 4; + u32 srq_size : 5; + u32 srq_rkey_en : 1; +#else + u32 srq_rkey_en : 1; + u32 srq_size : 5; + u32 srq_page_size : 4; + u32 srq_wqebb_size : 3; + u32 srq_pd : 18; + u32 rsvd : 1; +#endif + } bs; + u32 value; + } dw12; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 srq_cqn : 20; + u32 srq_state : 4; +#else + u32 srq_state : 4; + u32 srq_cqn : 20; + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw13; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 15; + u32 qp_rkey_en : 1; + u32 srq_xrcd : 16; +#else + u32 srq_xrcd : 16; + u32 qp_rkey_en : 1; + u32 rsvd : 15; +#endif + } bs; + u32 value; + } dw14; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 4; + u32 rq_page_size : 4; + u32 rq_pd : 18; + u32 rq_rkey_en : 1; + u32 rq_size : 5; +#else + u32 rq_size : 5; + u32 rq_rkey_en : 1; + u32 rq_pd : 18; + u32 rq_page_size : 4; + u32 rsvd : 4; +#endif + } bs; + u32 value; + } dw15; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 6; + u32 sq_wqebb_size : 3; + u32 sq_pd : 18; + u32 sq_page_size : 4; + u32 sq_rkey_en : 1; +#else + u32 sq_rkey_en : 1; + u32 sq_page_size : 4; + u32 sq_pd : 18; + u32 sq_wqebb_size : 3; + u32 rsvd : 6; +#endif + } bs; + u32 value; + } dw16; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 12; + u32 sqa_cqn : 20; +#else + u32 sqa_cqn : 20; + u32 rsvd : 12; +#endif + } bs; + u32 value; + } dw17; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 14; + u32 ud_pd : 18; +#else + u32 ud_pd : 18; + u32 rsvd : 14; +#endif + } bs; + u32 value; + } dw18; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 14; + u32 qp_pd : 18; +#else + u32 qp_pd : 18; + u32 rsvd : 14; +#endif + } bs; + u32 value; + } dw19; +} roce_verbs_qpc_attr_chip_s; + +#pragma pack() + +#endif /* ROCE_VERBS_ATTR_QPC_CHIP_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cmd.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cmd.h new file mode 100644 index 000000000..d7ebf00f0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cmd.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq commands. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_CMD_H +#define ROCE_VERBS_CMD_H + +#include "rdma_context_format.h" +#include "roce_verbs_pub.h" + + +/* ************************************************* */ +typedef struct tag_roce_verbs_cmd_com { + union { + u32 value; + + struct { + u32 version : 8; + u32 rsvd : 8; + u32 cmd_bitmask : 16; // CMD_TYPE_BITMASK_E + } bs; + } dw0; + + u32 index; // qpn/cqn/srqn/mpt_index/gid idx +} roce_verbs_cmd_com_s; + +typedef struct tag_roce_cmd_gid { + roce_verbs_cmd_com_s com; + + u32 port; + u32 rsvd; + struct roce_gid_context gid_entry; +} roce_cmd_update_gid_s; + +typedef struct tag_roce_clear_gid { + roce_verbs_cmd_com_s com; + + u32 port; + u32 gid_num; +} roce_cmd_clear_gid_s; + +typedef struct tag_roce_qurey_gid { + roce_verbs_cmd_com_s com; + + u32 port; + u32 rsvd; +} roce_cmd_query_gid_s; + +typedef struct tag_roce_flush_mpt { + roce_verbs_cmd_com_s com; +} roce_cmd_mpt_s; + +typedef struct tag_roce_cmd_flush_mpt { + roce_verbs_cmd_com_s com; +} roce_cmd_flush_mpt_s; + +typedef struct tag_roce_cmd_mpt_query { + roce_verbs_cmd_com_s com; +} roce_cmd_mpt_query_s; + +typedef struct tag_roce_sw2hw_mpt { + roce_verbs_cmd_com_s com; + struct roce_mpt_context mpt_entry; /* When creating a MR/MW, you need to enter the content of the MPT Context. */ +} roce_cmd_mpt_sw2hw_s; + +typedef struct tag_roce_cmd_modify_mpt { + roce_verbs_cmd_com_s com; + + u32 new_key; + + /* DW2~3 */ + union { + u64 length; /* Length of mr or mw */ + + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw2; + }; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; +} roce_cmd_modify_mpt_s; + +typedef struct tag_roce_cmd_mpt_hw2sw { + roce_verbs_cmd_com_s com; + + u32 dmtt_flags; + u32 dmtt_num; + u32 dmtt_cache_line_start; + u32 dmtt_cache_line_end; + u32 dmtt_cache_line_size; +} roce_cmd_mpt_hw2sw_s; + +typedef struct tag_roce_cmd_query_mtt { + roce_verbs_cmd_com_s com; + + u32 mtt_addr_start_hi32; + u32 mtt_addr_start_lo32; + u32 mtt_num; + u32 rsvd; +} roce_cmd_query_mtt_s; + +typedef struct tag_roce_cmd_creat_cq { + roce_verbs_cmd_com_s com; + roce_cq_context_s cqc; +} roce_cmd_creat_cq_s; + +typedef struct tag_roce_cmd_resize_cq { + roce_verbs_cmd_com_s com; + + u32 rsvd; + u32 page_size; /* Size of the resize buf page. */ + u32 log_cq_size; /* Cq depth after resize */ + u32 mtt_layer_num; /* Number of mtt levels after resize */ + /* DW4~5 */ + union { + u64 mtt_base_addr; /* Start address of mr or mw */ + u32 cqc_l0mtt_gpa[2]; + }; + u32 mtt_page_size; /* Size of the mtt page after resize. */ + roce_xq_mtt_info_s mtt_info; +} roce_cmd_resize_cq_s; + +typedef struct tag_roce_cmd_modify_cq { + roce_verbs_cmd_com_s com; + u32 max_cnt; + u32 timeout; +} roce_cmd_modify_cq_s; + +typedef struct tag_roce_cmd_cq_hw2sw { + roce_verbs_cmd_com_s com; +} roce_cmd_cq_hw2sw_s; + +typedef struct tag_roce_cmd_cq_cache_invalidate { + roce_verbs_cmd_com_s com; + roce_xq_mtt_info_s mtt_info; +} roce_cmd_cq_cache_invalidate_s; + +typedef struct tag_roce_cmd_roce_cq_query { + roce_verbs_cmd_com_s com; +} roce_cmd_cq_query_s; + +typedef struct tag_roce_cmd_creat_srq { + roce_verbs_cmd_com_s com; + roce_srq_context_s srqc; +} roce_cmd_creat_srq_s; + +typedef struct tag_roce_cmd_srq_arm { + roce_verbs_cmd_com_s com; + union { + u32 limitwater; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 lwm : 16; + u32 warth : 4; + u32 th_up_en : 1; + u32 cont_en : 1; + u32 rsvd : 10; +#else + u32 rsvd : 10; + u32 cont_en : 1; + u32 th_up_en : 1; + u32 warth : 4; + u32 lwm : 16; +#endif + } bs; + }; +} roce_cmd_srq_arm_s; + +typedef struct tag_roce_cmd_srq_hw2sw { + roce_verbs_cmd_com_s com; + roce_xq_mtt_info_s mtt_info; + u32 srq_buf_len; + u32 wqe_cache_line_start; + u32 wqe_cache_line_end; + u32 wqe_cache_line_size; +} roce_cmd_srq_hw2sw_s; + +typedef struct tag_roce_cmd_srq_query { + roce_verbs_cmd_com_s com; +} roce_cmd_srq_query_s; + +typedef struct tag_roce_cmd_modify_qpc { + roce_verbs_cmd_com_s com; + + u32 opt; + u32 rsvd[3]; + roce_qp_context_s qpc; +} roce_cmd_modify_qpc_s; + +typedef struct tag_roce_cmd_qp_modify2rst { + roce_verbs_cmd_com_s com; +} roce_cmd_qp_modify2rst_s; + +typedef struct tag_roce_cmd_qp_modify_rts2sqd { + roce_verbs_cmd_com_s com; + + u32 sqd_event_en; + u32 rsvd; +} roce_cmd_qp_modify_rts2sqd_s; + +typedef struct tag_roce_cmd_qp_query { + roce_verbs_cmd_com_s com; +} roce_cmd_qp_query_s; + +typedef struct tag_roce_cmd_modify_ctx { + roce_verbs_cmd_com_s com; + u32 ctx_type; + u32 offset; + u32 value; + u32 mask; +} roce_cmd_modify_ctx_s; + +typedef struct tag_roce_cmd_cap_pkt { + roce_verbs_cmd_com_s com; +} roce_cmd_cap_pkt_s; + +typedef struct tag_roce_modify_hash_value { + roce_verbs_cmd_com_s com; + u32 hash_value; +} roce_modify_hash_value_s; + +typedef struct tag_roce_modify_udp_src_port { + roce_verbs_cmd_com_s com; + u32 udp_src_port; +} roce_modify_udp_src_port_s; + +typedef struct roce_get_qp_udp_src_port { + roce_verbs_cmd_com_s com; +} roce_get_qp_udp_src_port_s; + +typedef struct tag_roce_get_qp_rx_port { + roce_verbs_cmd_com_s com; +} roce_get_qp_rx_port_s; + +typedef struct tag_roce_get_qp_func_table { + roce_verbs_cmd_com_s com; +} roce_get_qp_func_table_s; + +#endif /* ROCE_VERBS_CMD_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cq_attr.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cq_attr.h new file mode 100644 index 000000000..69b7ac932 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cq_attr.h @@ -0,0 +1,170 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq cq attribute context. + * Create: 2021-04-22 + */ + +#ifndef ROCE_VERBS_CQ_ATTR_H +#define ROCE_VERBS_CQ_ATTR_H + +#include "roce_verbs_mr_attr.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#pragma pack(4) +typedef struct roce_verbs_cq_attr { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 signature : 5; + u32 ci_on_chip : 1; + u32 cnt_clear_en : 1; + u32 cnt_adjust_en : 1; + u32 rsvd : 3; + u32 timer_mode : 1; + u32 arm_timer_en : 1; + u32 tss_timer_num : 3; + u32 mtt_page_size : 4; + u32 cqe_size : 3; + u32 page_size : 4; + u32 size : 5; +#else + u32 size : 5; /* Completion Queue size, equals to (2^cq_size)*CQE. + The maximum CQ size is 2^23 CQEs. */ + u32 page_size : 4; /* Page size of CQ, equals to (2^cq_page_size)*4KB. */ + u32 cqe_size : 3; /* Completion Queue Entry (CQE) size in bytes is (2^cq_cqe_size)*16B. + The minimum size is 32B and the values 0, 3, 4, 5, 6, 7 are reserved. */ + u32 mtt_page_size : 4; + u32 tss_timer_num : 3; + u32 arm_timer_en : 1; + u32 timer_mode : 1; + u32 rsvd : 3; + u32 cnt_adjust_en : 1; + u32 cnt_clear_en : 1; + u32 ci_on_chip : 1; /* If set, the CI of Complete Queue is stored in the chip, + the counter is absolute value. */ + u32 signature : 5; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 state : 4; + u32 rsvd : 14; + u32 ep : 3; + u32 cos : 3; + u32 so_ro : 2; + u32 dma_attr_idx : 6; +#else + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + * This filed is only valid when processing CQ's CQEs. */ + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + * This field is only valid when processing CQ's CQEs. + * 2'b00: Strict Ordering; + * 2'b01: Relaxed Ordering; + * 2'b10: ID Based Ordering; + * 2'b11: Both Relaxed Ordering and ID Based Ordering. */ + u32 cos : 3; + u32 ep : 3; + u32 rsvd : 14; + u32 state : 4; +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ceqn : 8; + u32 rsvd : 1; + u32 arm_ceqe_en : 1; + u32 ceqe_en : 1; + u32 cqecnt_rctl_en : 1; + u32 cqecnt_lth : 4; + u32 idle_max_count : 16; +#else + u32 idle_max_count : 16; + u32 cqecnt_lth : 4; + u32 cqecnt_rctl_en : 1; + u32 ceqe_en : 1; + u32 arm_ceqe_en : 1; + u32 rsvd : 1; + u32 ceqn : 8; +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 max_cnt : 16; + u32 timeout : 16; +#else + u32 timeout : 16; /* Completion Event Moderation timer in microseconds. + 0x0: interrupt moderation disabled. */ + u32 max_cnt : 16; /* Completion Event Moderation counters. + 0x0: interrupt moderation disabled. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4 - DW5 */ + union { + u64 cqc_l0mtt_gpa; /* The GPA of Layer 0 MTT. It may point to the CQ's buffer directly.low 3bits(cq_gpa_sign) */ + struct { + u32 cqc_l0mtt_gpa_hi; + u32 cqc_l0mtt_gpa_lo; + } dw4_dw5; + }; + + /* DW6 - DW7 */ + union { + u64 ci_record_gpa_at_hop_num; /* The GPA of stored CI of Complete Queue. + * Address translation hop numbers. + 0x0: the 'cq_l0mtt_gpa' points to the buffer of CQ directly. + 0x1: it need to perform one hop address translation to get the buffer's + address of CQ; 0x2: there is two hop address translation to get the buffer's + address of CQ; 0x3: reserved. */ + struct { + u32 ci_record_gpa_hi; + u32 ci_record_gpa_lo_at_hop_num; /* bit[1:0] Address translation hop numbers */ + } dw6_dw7; + }; +} roce_verbs_cq_attr_s; + +typedef struct tag_roce_verbs_cq_resize_info { + /* DW0~3 */ + u32 mtt_page_size; /* Size of the mtt page after resize. */ + u32 page_size; /* Size of the resize buf page. */ + u32 log_cq_size; /* Cq depth after resize */ + u32 mtt_layer_num; /* Number of mtt levels after resize */ + + /* DW4~5 */ + union { + u64 mtt_base_addr; /* Start address of mr or mw */ + u32 cqc_l0mtt_gpa[2]; + }; + + /* DW6~10 */ + roce_verbs_mtt_cacheout_info_s cmtt_cache; +} roce_verbs_cq_resize_info_s; + +typedef struct tag_roce_verbs_modify_cq_info { + u32 max_cnt; + u32 timeout; +} roce_verbs_modify_cq_info_s; +#pragma pack() + +#endif /* ROCE_VERBS_CQ_ATTR_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ext_attr.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ext_attr.h new file mode 100644 index 000000000..0b445cc33 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ext_attr.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq extended attributes. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_EXT_ATTR_H +#define ROCE_VERBS_EXT_ATTR_H + +#include "roce_verbs_pub.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +enum VERBS_ATTR_EXT_TYPE_E { + VERBS_ATTR_EXT_TYPE_NONE = 0, + VERBS_ATTR_EXT_TYPE_SQP, + VERBS_ATTR_EXT_TYPE_RSVD = 0xff +}; + +#define ROCE_VERBS_SQP_WQE_SIZE (2) + +#pragma pack(4) + +typedef struct tag_roce_verbs_sqp_attr { + /* DW0 */ + roce_verbs_segment_hdr_s seg_hdr; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd0 : 26; + u32 sqp_wqecnt_lth : 4; + u32 sqp_wqecnt_rctl_en : 1; + u32 sqp_ci_on_chip : 1; +#else + u32 sqp_ci_on_chip : 1; + u32 sqp_wqecnt_rctl_en : 1; + u32 sqp_wqecnt_lth : 4; + u32 rsvd0 : 26; +#endif + } bs; + u32 value; + } dw1; +} roce_verbs_sqp_attr_s; + +#pragma pack() + +#endif /* ROCE_VERBS_EXT_ATTR_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_format.h new file mode 100644 index 000000000..4473c8a20 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_format.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq command format. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_FORMAT_H +#define ROCE_VERBS_FORMAT_H + +#include "roce_verbs_pub.h" +#include "roce_verbs_attr.h" + + +/* ********************************************************************************** */ +/* * verbs struct */ +typedef struct tag_roce_uni_cmd_gid { + roce_verbs_cmd_header_s com; + roce_verbs_gid_attr_s gid_attr; +} roce_uni_cmd_update_gid_s; + +typedef struct tag_roce_uni_cmd_clear_gid { + roce_verbs_cmd_header_s com; + roce_verbs_clear_gid_info_s gid_clear; +} roce_uni_cmd_clear_gid_s; + +typedef struct tag_roce_uni_cmd_qurey_gid { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_query_gid_s; + +typedef struct tag_roce_uni_cmd_flush_mpt { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_flush_mpt_s; + +typedef struct tag_roce_uni_cmd_mpt_query { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_mpt_query_s; + +typedef struct tag_roce_uni_cmd_sw2hw_mpt { + roce_verbs_cmd_header_s com; + roce_verbs_mr_attr_s mr_attr; /* When creating a MR/MW, you need to enter the content of the MPT Context. */ +} roce_uni_cmd_mpt_sw2hw_s; + +typedef struct tag_roce_uni_cmd_modify_mpt { + roce_verbs_cmd_header_s com; + roce_verbs_mr_sge_s mr_sge; +} roce_uni_cmd_modify_mpt_s; + +typedef struct tag_roce_uni_cmd_mpt_hw2sw { + roce_verbs_cmd_header_s com; + roce_verbs_mtt_cacheout_info_s dmtt_cache; +} roce_uni_cmd_mpt_hw2sw_s; + +typedef struct tag_roce_uni_cmd_query_mtt { + roce_verbs_cmd_header_s com; + roce_verbs_query_mtt_info_s mtt_query; +} roce_uni_cmd_query_mtt_s; + +typedef struct tag_roce_uni_cmd_creat_cq { + roce_verbs_cmd_header_s com; + roce_verbs_cq_attr_s cq_attr; +} roce_uni_cmd_creat_cq_s; + +typedef struct tag_roce_uni_cmd_resize_cq { + roce_verbs_cmd_header_s com; + roce_verbs_cq_resize_info_s cq_resize; +} roce_uni_cmd_resize_cq_s; + +typedef struct tag_roce_uni_cmd_modify_cq { + roce_verbs_cmd_header_s com; + roce_verbs_modify_cq_info_s cq_modify; +} roce_uni_cmd_modify_cq_s; + +typedef struct tag_roce_uni_cmd_cq_hw2sw { + roce_verbs_cmd_header_s com; + roce_verbs_mtt_cacheout_info_s cmtt_cache; +} roce_uni_cmd_cq_hw2sw_s; + +typedef struct tag_roce_uni_cmd_roce_cq_query { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_cq_query_s; + +typedef struct tag_roce_uni_cmd_creat_srq { + roce_verbs_cmd_header_s com; + roce_verbs_srq_attr_s srq_attr; +} roce_uni_cmd_creat_srq_s; + +typedef struct tag_roce_uni_cmd_srq_arm { + roce_verbs_cmd_header_s com; + roce_verbs_arm_srq_info_u srq_arm; +} roce_uni_cmd_srq_arm_s; + +typedef struct tag_roce_uni_cmd_srq_hw2sw { + roce_verbs_cmd_header_s com; + roce_verbs_srq_hw2sw_info_s srq_cache; +} roce_uni_cmd_srq_hw2sw_s; + +typedef struct tag_roce_uni_cmd_srq_query { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_srq_query_s; + +typedef struct tag_roce_uni_cmd_modify_qpc { + roce_verbs_cmd_header_s com; + roce_verbs_qp_attr_s qp_attr; +} roce_uni_cmd_modify_qpc_s; + +typedef struct tag_roce_uni_cmd_qp_modify2rst { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_qp_modify2rst_s; + +typedef struct tag_roce_uni_cmd_qp_modify_rts2sqd { + roce_verbs_cmd_header_s com; + u32 sqd_event_en; +} roce_uni_cmd_qp_modify_rts2sqd_s; + +typedef struct tag_roce_uni_cmd_qp_query { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_qp_query_s; + +typedef struct tag_roce_uni_cmd_qp_cache_invalid { + roce_verbs_cmd_header_s com; + roce_verbs_qp_hw2sw_info_s qp_cache; +} roce_uni_cmd_qp_cache_invalid_s; + +typedef struct tag_roce_uni_cmd_modify_ctx { + roce_verbs_cmd_header_s com; + roce_verbs_modify_ctx_info_s ctx_modify; +} roce_uni_cmd_modify_ctx_s; + +typedef struct tag_roce_uni_cmd_cap_pkt { + roce_verbs_cmd_header_s com; +} roce_uni_cmd_cap_pkt_s; + + +#endif /* ROCE_VERBS_FORMAT_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_gid_attr.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_gid_attr.h new file mode 100644 index 000000000..265fee58e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_gid_attr.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq gid attribute context. + * Create: 2021-04-22 + */ +#ifndef ROCE_VERBS_GID_ATTR_H +#define ROCE_VERBS_GID_ATTR_H + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#pragma pack(4) +typedef struct tag_roce_verbs_gid_ipv4_attr { + /* DW0 */ + union { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 udpudp_len_gap : 8; + u32 rsvd : 8; + u32 bth_addr : 16; +#else + u32 bth_addr : 16; + u32 rsvd : 8; + u32 udpudp_len_gap : 8; +#endif + u32 value; + } dw0; + + /* DW1 */ + union { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ip_addr : 16; + u32 udp_addr : 16; +#else + u32 udp_addr : 16; + u32 ip_addr : 16; +#endif + u32 value; + } dw1; +} roce_verbs_gid_ipv4_attr_s; + +typedef struct tag_roce_verbs_gid_attr { + /* DW0~3 */ + u32 gid[4]; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd0 : 12; + u32 cvlan : 12; + u32 rsvd : 8; +#else + u32 rsvd : 8; + u32 cvlan : 12; + u32 rsvd0 : 12; +#endif + } bs; + u32 value; + } dw4; + + /* DW5 */ + union { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ppersp_pad_len : 8; + u32 l2_len : 8; + u32 ipv4_hdr_len : 8; + u32 pkthdr_len : 8; +#else + u32 pkthdr_len : 8; + u32 ipv4_hdr_len : 8; + u32 l2_len : 8; + u32 ppersp_pad_len : 8; +#endif + u32 value; + } dw5; + + /* DW6 */ + union { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 7; + u32 o_ip_type : 1; + u32 o_tag : 2; + u32 gid_update : 1; + u32 rsvd0 : 1; + u32 gid_type : 2; + u32 tag : 2; + u32 smac_hi16 : 16; +#else + u32 smac_hi16 : 16; + u32 tag : 2; + u32 gid_type : 2; /* 0:ROCE V1; 1:ROCE V2 IPV4; 2:ROCE V2 IPV6; other:rsvd */ + u32 rsvd0 : 1; + u32 gid_update : 1; + u32 o_tag : 2; + u32 o_ip_type : 1; + u32 rsvd : 7; +#endif + u32 value; + } dw6; + + u32 smac_lo32; + + roce_verbs_gid_ipv4_attr_s ipv4; +} roce_verbs_gid_attr_s; + +typedef struct tag_roce_verbs_clear_gid_info { + u32 gid_num; +} roce_verbs_clear_gid_info_s; +#pragma pack() + +#endif /* ROCE_VERBS_GID_ATTR_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_mr_attr.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_mr_attr.h new file mode 100644 index 000000000..b88430986 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_mr_attr.h @@ -0,0 +1,299 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq extended MR attributes. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_MR_ATTR_H +#define ROCE_VERBS_MR_ATTR_H + + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#pragma pack(4) +typedef struct tag_roce_verbs_mr_sge { + u32 rsvd; + u32 new_key; + + /* DW2~3 */ + union { + u64 length; /* Length of mr or mw */ + + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw2; + }; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; +} roce_verbs_mr_sge_s; + +typedef struct tag_roce_verbs_mtt_cacheout_info { + u32 mtt_flags; /* Indicates whether to kick out cache. by queue (0) or VF(1). */ + u32 mtt_num; /* Number of cmtt, which needs to be assigned by the driver when the is kicked out by queue. */ + u32 mtt_cache_line_start; /* The driver needs to read the driver from the configuration file. */ + u32 mtt_cache_line_end; /* The driver needs to read the driver from the configuration file. */ + u32 mtt_cache_line_size; /* 0:256B,1:512B */ +} roce_verbs_mtt_cacheout_info_s; + +typedef struct tag_roce_verbs_wqe_cacheout_info { + u32 wqe_flags; /* Indicates whether to kick out cache. by queue (0) or VF(1). */ + u32 wqe_num; /* Number of wqe, which needs to be assigned by the driver when the is kicked out by queue. */ + u32 wqe_cache_line_start; /* The driver needs to read the driver from the configuration file. */ + u32 wqe_cache_line_end; /* The driver needs to read the driver from the configuration file. */ + u32 wqe_cache_line_size; /* 0:256B,1:512B */ +} roce_verbs_wqe_cacheout_info_s; + + +typedef struct tag_roce_verbs_query_mtt_info { + u32 mtt_addr_start_hi32; + u32 mtt_addr_start_lo32; + u32 mtt_num; + u32 rsvd; +} roce_verbs_query_mtt_info_s; + +typedef struct tag_roce_dif_user_data_s { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 smd_tp : 2; + u32 app_esc : 1; + u32 ref_esc : 1; + u32 sct_v_tp : 2; + u32 sct_sz : 1; + u32 md_sz : 1; + u32 hdr_vld : 1; + u32 sec_num : 23; +#else + u32 sec_num : 23; + u32 hdr_vld : 1; // tx: 0->no nvme hdr, 1: hdr + u32 md_sz : 1; + u32 sct_sz : 1; + u32 sct_v_tp : 2; + u32 ref_esc : 1; + u32 app_esc : 1; + u32 smd_tp : 2; +#endif + }bs; + u32 value; + }dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rep_app_tag : 16; + u32 grd_v_en : 1; + u32 grd_rid : 2; + u32 grd_v_agm : 1; + u32 grd_ri_agm : 1; + u32 grd_agm_ini : 1; + u32 crc16_ini : 1; + u32 ipcs_ini : 1; + u32 ref_v_en : 1; + u32 ref_rid : 2; + u32 ref_v_inc : 1; + u32 ref_ri_inc : 1; + u32 app_v_en : 1; + u32 app_rid : 2; +#else + u32 app_rid : 2; + u32 app_v_en : 1; + u32 ref_ri_inc : 1; + u32 ref_v_inc : 1; + u32 ref_rid : 2; + u32 ref_v_en : 1; + u32 ipcs_ini : 1; + u32 crc16_ini : 1; + u32 grd_agm_ini : 1; + u32 grd_ri_agm : 1; + u32 grd_v_agm : 1; + u32 grd_rid : 2; + u32 grd_v_en : 1; + u32 rep_app_tag : 16; +#endif + } bs; + u32 value; + } dw1; + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cmp_app_tag : 16; + u32 cmp_app_tag_mask : 16; +#else + u32 cmp_app_tag_mask : 16; + u32 cmp_app_tag : 16; +#endif + } bs; + u32 value; + } dw2; + + u32 cmp_ref_tag; + u32 rep_ref_tag; +} roce_dif_user_data_s; + +typedef struct tag_roce_verbs_mr_attr { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 buf_page_size : 4; /* Page_size of the buffer */ + u32 mtt_layer_num : 3; /* Mtt level */ + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 rsvd2 : 4; + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 bqp : 1; /* 1: Bound to qp */ + u32 dif_mode : 1; + u32 rkey : 1; + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 r_w : 1; /* Mr or mw. The value 1 indicates MR, and the value 0 indicates MW. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ +#else + u32 access_bind : 1; /* Whether the mr supports the binding of the mw */ + u32 remote_access_en : 1; /* Indicates whether the FRMR can specify remote rights. */ + u32 fast_reg_en : 1; /* Indicates whether the FRMR operation is supported. */ + u32 invalid_en : 1; /* Indicates whether to support the INVALID operation. */ + u32 remote_invalid_en : 1; /* Indicates whether to support the remote INVALID operation. */ + u32 r_w : 1; /* Mr or mw */ + u32 pa : 1; /* Flag bit of DMA_MR */ + u32 rkey : 1; + u32 dif_mode : 1; + u32 bqp : 1; /* 1: Bound to qp */ + u32 bpd : 1; /* 1: Bound to pd */ + u32 access_ra : 1; /* The value 1 indicates that the remote Atomic permission is supported. */ + u32 access_rw : 1; /* 1: The remote write permission is supported. */ + u32 access_rr : 1; /* 1: Indicates that the remote read permission is supported. */ + u32 access_lw : 1; /* The value 1 indicates that the local write permission is supported. */ + u32 access_lr : 1; /* 1: Indicates that the local read permission is supported. */ + u32 zbva : 1; /* The value 1 indicates that ZBVA is supported, that is, iova = 0. */ + u32 rsvd2 : 4; + u32 mtt_page_size : 4; /* Page_size of mtt */ + u32 mtt_layer_num : 3; /* Number of mtt levels */ + u32 buf_page_size : 4; /* Page_size of the buffer */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 so_ro : 2; + u32 dma_attr_idx : 6; + u32 sector_size : 1; + u32 ep : 3; + u32 qpn : 20; +#else + u32 qpn : 20; /* Qp bound to mw */ + u32 ep : 3; + u32 sector_size : 1; /* 0:512B, 1:4KB */ + u32 dma_attr_idx : 6; /* Dma attribute index */ + u32 so_ro : 2; /* Dma order-preserving flag */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 status : 4; + u32 indirect_mr : 1; + u32 cos : 3; + u32 block_size : 6; + u32 pdn : 18; +#else + u32 pdn : 18; /* Pd bound to mr or mw */ + u32 block_size : 6; /* 2^(page_size+12) + 8*block_size */ + u32 cos : 3; + u32 indirect_mr : 1; + u32 status : 4; /* Mpt status. Valid values are VALID, FREE, and INVALID. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 mkey : 8; + u32 sw_dif_en : 1; + u32 page_mode : 1; + u32 fbo : 22; +#else + u32 fbo : 22; + u32 page_mode : 1; + u32 sw_dif_en : 1; + u32 mkey : 8; /* The index is not included. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4~5 */ + union { + u64 iova; /* Start address of mr or mw */ + struct { + u32 iova_hi; /* Upper 32 bits of the start address of mr or mw */ + u32 iova_lo; /* Lower 32 bits of the start address of mr or mw */ + } dw4; + }; + + /* DW6~7 */ + union { + u64 length; /* Length of mr or mw */ + struct { + u32 length_hi; /* Length of mr or mw */ + u32 length_lo; /* Length of mr or mw */ + } dw6; + }; + + /* DW8~9 */ + union { + u64 mtt_base_addr; /* Mtt base address (pa),low 3bits(gpa_sign) */ + struct { + u32 mtt_base_addr_hi; /* Mtt base address (pa) upper 32 bits */ + u32 mtt_base_addr_lo; /* Lower 32 bits of mtt base address (pa),low 3bits(gpa_sign) */ + } dw8; + }; + + /* DW10 */ + union { + u32 mr_mkey; /* This parameter is valid for MW. */ + u32 mw_cnt; /* This parameter is valid when the MR is used. */ + }; + + /* DW11 */ + u32 mtt_sz; + + /* DW12~16 */ + roce_dif_user_data_s dif_info; + + /* DW17 */ + u32 rsvd; +} roce_verbs_mr_attr_s; +#pragma pack() + +#endif /* ROCE_VERBS_MR_ATTR_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_pub.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_pub.h new file mode 100644 index 000000000..d699798a3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_pub.h @@ -0,0 +1,226 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq public commands. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_PUB_H +#define ROCE_VERBS_PUB_H + + +enum CMD_TYPE_BITMASK_E { + CMD_TYPE_BITMASK_EXT = 0, + CMD_TYPE_BITMASK_RSVD1, + CMD_TYPE_BITMASK_RSVD0, + CMD_TYPE_BITMASK_PLUGIN_RET, + CMD_TYPE_BITMASK_VBS, + CMD_TYPE_BITMASK_DSW, + CMD_TYPE_BITMASK_NOFAA, + CMD_TYPE_BITMASK_PLOG, + CMD_TYPE_BITMASK_DBG = 8, + CMD_TYPE_BITMASK_VROCE, + CMD_TYPE_BITMASK_CCF, + CMD_TYPE_BITMASK_GID, + CMD_TYPE_BITMASK_MR, + CMD_TYPE_BITMASK_SRQ, + CMD_TYPE_BITMASK_CQ, + CMD_TYPE_BITMASK_QP = 15 +}; + +#define VERBS_CMD_TYPE_QP_BITMASK (1u << CMD_TYPE_BITMASK_QP) +#define VERBS_CMD_TYPE_CQ_BITMASK (1u << CMD_TYPE_BITMASK_CQ) +#define VERBS_CMD_TYPE_SRQ_BITMASK (1u << CMD_TYPE_BITMASK_SRQ) +#define VERBS_CMD_TYPE_MR_BITMASK (1u << CMD_TYPE_BITMASK_MR) +#define VERBS_CMD_TYPE_GID_BITMASK (1u << CMD_TYPE_BITMASK_GID) +#define VERBS_CMD_TYPE_CCF_BITMASK (1u << CMD_TYPE_BITMASK_CCF) +#define VERBS_CMD_TYPE_VROCE_BITMASK (1u << CMD_TYPE_BITMASK_VROCE) +#define VERBS_CMD_TYPE_DEBUG_BITMASK (1u << CMD_TYPE_BITMASK_DBG) +#define VERBS_CMD_TYPE_PLOG_BITMASK (1u << CMD_TYPE_BITMASK_PLOG) +#define VERBS_CMD_TYPE_NOFAA_BITMASK (1u << CMD_TYPE_BITMASK_NOFAA) +#define VERBS_CMD_TYPE_DSW_BITMASK (1u << CMD_TYPE_BITMASK_DSW) +#define VERBS_CMD_TYPE_VBS_BITMASK (1u << CMD_TYPE_BITMASK_VBS) +#define VERBS_CMD_TYPE_EXT_BITMASK (1u << CMD_TYPE_BITMASK_EXT) + +enum roce3_cmd_ret_status { + ROCE_CMD_RET_SUCCESS = 0x0, + + ROCE_CMD_RET_FLR_ERR = 0x1, + ROCE_CMD_RET_FUNC_INVLD, + ROCE_CMD_RET_CMDMISC_UNSUPPORT, + ROCE_CMD_RET_CMDTYPE_UNSUPPORT, + ROCE_CMD_RET_RET_ADDR_INVLD, + ROCE_CMD_RET_INDEX_INVLD, + ROCE_CMD_RET_LOCAL_UNSUPPORT, + ROCE_CMD_RET_QPC_RSP_ERR = 0x10, + ROCE_CMD_RET_QPC_STATE_UNEXPECT, + ROCE_CMD_RET_MODIFY_QP_OPT_ERR, + ROCE_CMD_RET_MODIFY_QP_EXTEND_OP_API_ERR, + ROCE_CMD_RET_SQD_QP_FETCH_WQE_ERR, + ROCE_CMD_RET_RDMARC_SYNC_EXTEND_OP_API_ERR, + ROCE_CMD_RET_MODIFY_QP_OQID_ERR, + ROCE_CMD_RET_CQC_STATE_UNEXPECT = 0x18, + ROCE_CMD_RET_CQC_MISC_API_ERR, + ROCE_CMD_RET_CQC_CREATE_CACHE_OUT_ERR, + ROCE_CMD_RET_CQ_RESIZE_API_ERR, + ROCE_CMD_RET_CQ_EXTEND_OP_API_ERR, + ROCE_CMD_RET_CQ_TIEMR_DEL_ERR, + ROCE_CMD_RET_CQ_TIEMR_REM_ERR, + ROCE_CMD_RET_SRQC_STATE_UNEXPECT = 0x20, + ROCE_CMD_RET_SRQ_ARM_SRQ_CONT_EN_ERR, + ROCE_CMD_RET_SRQ_ARM_SRQ_API_ERR, + ROCE_CMD_RET_SRQ_EXTEND_OP_API_ERR, + ROCE_CMD_RET_MR_STATE_ERR = 0x28, + ROCE_CMD_RET_MR_BIND_MW_API_ERR, + ROCE_CMD_RET_MR_EXTEND_OP_API_ERR, + ROCE_CMD_RET_MR_MISC_LOAD_API_ERR, + ROCE_CMD_RET_MR_MPTC_SYNC_ERR, + ROCE_CMD_RET_MR_MISC_STORE_API_ERR, + ROCE_CMD_RET_MR_CACHE_OUT_MPT_ERR, + ROCE_CMD_RET_MR_CACHE_OUT_MTT_ERR, + ROCE_CMD_RET_DBG_EXTEND_OP_API_ERR = 0x30, + ROCE_CMD_RET_DBG_WQE_UPDATE_PI_ERR, + ROCE_CMD_RET_QU_FLUSH_API_ERR, + ROCE_CMD_RET_CC_HASH_API_ERR, + ROCE_CMD_RET_CMD_OP_LB_ERR, + ROCE_CMD_RET_CMD_OP_SRQN_ERR, + ROCE_CMD_RET_DIF_TASKID_ALLOC_ERR, + ROCE_CMD_RET_QP_EXTEND_OP_ERR, + ROCE_CMD_RET_LOAD_ERR, + ROCE_CMD_RET_STORE_ERR, + ROCE_CMD_RET_LOAD_HOST_GPA_ERR, + ROCE_CMD_RET_CACHE_OUT_ERR, + ROCE_CMD_RET_CACHE_OUT_MTT_ERR, + ROCE_CMD_RET_BANK_GPA_FLUSH_ERR, + ROCE_CMD_RET_INVALID_PARAM_ERR, + ROCE_CMD_RET_RSVD_ERR = 0xff, +}; + +enum roce3_cmd_ret_extend_op_err { + ROCE_CMD_RET_EXTEND_OP_NONE = 0x0, + + ROCE_CMD_RET_EXTEND_OP_RCC_RRE = 0x1, + ROCE_CMD_RET_EXTEND_OP_RCC_RAE, + ROCE_CMD_RET_EXTEND_OP_RRWC_RWE, + ROCE_CMD_RET_EXTEND_OP_RRWC_STA, + ROCE_CMD_RET_EXTEND_OP_RCC_STA, + ROCE_CMD_RET_EXTEND_OP_SQC_STA, + ROCE_CMD_RET_EXTEND_OP_SQAC_STA, + ROCE_CMD_RET_EXTEND_OP_RQC_STA, + ROCE_CMD_RET_EXTEND_OP_CQC_TIMEOUT = 0x10, + ROCE_CMD_RET_EXTEND_OP_CQC_STA, + ROCE_CMD_RET_EXTEND_OP_SRQC_STA = 0x18, + ROCE_CMD_RET_EXTEND_OP_MPT_STA = 0x20, + ROCE_CMD_RET_EXTEND_OP_QPC_DBG_EDIT = 0x28, + ROCE_CMD_RET_EXTEND_OP_CQC_SRQC_DBG_EDIT +}; + +/* Mask description of *********ROCE verbs modify qp ******* */ +/* ****************************************************************** + opt INIT2INIT INIT2RTR RTR2RTS RTS2RTS SQERR2RTS SQD2SQD SQD2RTS +QP_OPTPAR_ALT_ADDR_PATH 0 √ √ √ √ √ +QP_OPTPAR_RRE 1 √ √ √ √ √ √ √ +QP_OPTPAR_RAE 2 √ √ √ √ √ √ √ +QP_OPTPAR_RWE 3 √ √ √ √ √ √ √ +QP_OPTPAR_PKEY_INDEX 4 +QP_OPTPAR_Q_KEY 5 √ √ √ √ √ √ √ +QP_OPTPAR_RNR_TIMEOUT 6 √ √ √ √ √ +QP_OPTPAR_PRIMARY_ADDR_PATH 7 √ √ +QP_OPTPAR_SRA_MAX 8 √ √ +QP_OPTPAR_RRA_MAX 9 √ √ +QP_OPTPAR_PM_STATE 10 √ √ √ √ +QP_OPTPAR_RETRY_COUNT 11 √ √ +QP_OPTPAR_RNR_RETRY 12 √ √ +QP_OPTPAR_ACK_TIMEOUT 13 √ √ +QP_OPTPAR_SCHED_QUEUE 14 +QP_OPTPAR_COUNTER_INDEX 15 +******************************************************************** */ +enum QP_OPTPAR_E { + QP_OPTPAR_ALT_ADDR_PATH = 0, + QP_OPTPAR_RRE, + QP_OPTPAR_RAE, + QP_OPTPAR_RWE, + QP_OPTPAR_PKEY_INDEX, + QP_OPTPAR_Q_KEY, + QP_OPTPAR_RNR_TIMEOUT, + QP_OPTPAR_PRIMARY_ADDR_PATH, + QP_OPTPAR_SRA_MAX = 8, + QP_OPTPAR_RRA_MAX, + QP_OPTPAR_PM_STATE, + QP_OPTPAR_RETRY_COUNT, + QP_OPTPAR_RNR_RETRY, + QP_OPTPAR_ACK_TIMEOUT, + QP_OPTPAR_SCHED_QUEUE, + QP_OPTPAR_COUNTER_INDEX = 15 +}; + +#define ROCE_QP_ALT_ADDR_PATH_OPT (1u << QP_OPTPAR_ALT_ADDR_PATH) +#define ROCE_QP_RRE_OPT (1u << QP_OPTPAR_RRE) +#define ROCE_QP_RAE_OPT (1u << QP_OPTPAR_RAE) +#define ROCE_QP_RWE_OPT (1u << QP_OPTPAR_RWE) +#define ROCE_QP_PKEY_INDEX_OPT (1u << QP_OPTPAR_PKEY_INDEX) +#define ROCE_QP_Q_KEY_OPT (1u << QP_OPTPAR_Q_KEY) +#define ROCE_QP_RNR_TIMEOUT_OPT (1u << QP_OPTPAR_RNR_TIMEOUT) +#define ROCE_QP_PRIMARY_ADDR_PATH_OPT (1u << QP_OPTPAR_PRIMARY_ADDR_PATH) +#define ROCE_QP_SRA_MAX_OPT (1u << QP_OPTPAR_SRA_MAX) +#define ROCE_QP_RRA_MAX_OPT (1u << QP_OPTPAR_RRA_MAX) +#define ROCE_QP_PM_STATE_OPT (1u << QP_OPTPAR_PM_STATE) +#define ROCE_QP_RETRY_COUNT_OPT (1u << QP_OPTPAR_RETRY_COUNT) +#define ROCE_QP_RNR_RETRY_OPT (1u << QP_OPTPAR_RNR_RETRY) +#define ROCE_QP_ACK_TIMEOUT_OPT (1u << QP_OPTPAR_ACK_TIMEOUT) +#define ROCE_QP_SCHED_QUEUE_OPT (1u << QP_OPTPAR_SCHED_QUEUE) +#define ROCE_QP_COUNTER_INDEX_OPT (1u << QP_OPTPAR_COUNTER_INDEX) + +#define ROCE_MODIFY_QP_INIT2INIT_OPT (~0x402e) +#define ROCE_MODIFY_QP_INIT2RTR_OPT (~0x2ee) +#define ROCE_MODIFY_QP_RTR2RTS_OPT (~0x3d6e) +#define ROCE_MODIFY_QP_RTS2RTS_OPT (~0x46e) +#define ROCE_MODIFY_QP_SQERR2RTS_OPT (~0x2e) +#define ROCE_MODIFY_QP_SQD2SQD_OPT (~0x7fee) +#define ROCE_MODIFY_QP_SQD2RTS_OPT (~0x46e) +#define ROCE_MODIFY_QP_RTS2RTS_EXP_OPT (~0x10000) + +#define ROCE_MODIFY_QP_RTS2SQD_SQD_EVENT_OPT (0x80000000) +/* ************************************************* */ + +#pragma pack(4) +typedef struct tag_roce_verbs_cmd_header { + union { + u32 value; + + struct { + u32 version : 8; + u32 rsvd : 8; + u32 cmd_bitmask : 16; // CMD_TYPE_BITMASK_E + } bs; + } dw0; + + u32 index; // qpn/cqn/srqn/mpt_index/gid idx + + u32 opt; // + + union { + u32 value; + + struct { + u32 cmd_type : 8; + u32 rsvd : 7; + u32 seg_ext : 1; + u32 cmd_len : 16; // verbs cmd total len(include cmd_com),unit:byte + } bs; + } dw3; +} roce_verbs_cmd_header_s; + +typedef union tag_roce_verbs_seg_hdr { + u32 value; + + struct { + u32 seg_type : 16; + u32 rsvd : 7; + u32 last_seg : 1; + u32 seg_len : 8; // seg info len,unit:4B + } bs; +} roce_verbs_segment_hdr_s; + +#pragma pack() + +#endif /* ROCE_VERBS_PUB_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_srq_attr.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_srq_attr.h new file mode 100644 index 000000000..5697d5731 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_srq_attr.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq srq attribute context. + * Create: 2021-04-22 + */ + +#ifndef ROCE_VERBS_SRQ_ATTR_H +#define ROCE_VERBS_SRQ_ATTR_H + +#include "roce_verbs_mr_attr.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#pragma pack(4) +typedef struct tag_roce_verbs_srq_cont_attr { + /* DW0 */ + u32 head_gpa_h; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 head_gpa_l : 20; + u32 rsvd : 11; + u32 head_gpa_vld : 1; +#else + u32 head_gpa_vld : 1; + u32 rsvd : 11; + u32 head_gpa_l : 20; +#endif + } bs; + u32 value; + } dw1; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cont_size : 2; + u32 rsvd : 10; + u32 warn_th : 4; + u32 head_idx : 16; +#else + u32 head_idx : 16; + u32 warn_th : 4; + u32 rsvd : 10; + u32 cont_size : 2; +#endif + } bs; + u32 value; + } dw2; +} roce_verbs_srq_cont_attr_s; + +typedef struct tag_roce_verbs_srq_attr { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 xrcd : 16; + u32 mtt_page_size : 4; + u32 wqebb_size : 3; + u32 page_size : 4; + u32 size : 5; +#else + u32 size : 5; /* Shared Receive Queue size, equals to (2^srq_size)*WQEBB, + * the maximum SRQ size is 16K WQEs, so this field doesn't exceed 14. */ + u32 page_size : 4; /* Page size of SRQ, equals to (2^srq_page_size)*4KB */ + u32 wqebb_size : 3; /* Shared Receive WQE Basic Block (WQEBB) size in bytes is (2^rq_wqebb_size)*16B. + The minimum size is 32B and the values 0, 4, 5, 6, 7 are reserved */ + u32 mtt_page_size : 4; /* Page size of MTT for SRQ, equals to (2^srq_mtt_page_size)*4KB. */ + u32 xrcd : 16; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 state : 4; + u32 rsvd : 14; + u32 ep : 3; + u32 cos : 3; + u32 so_ro : 2; + u32 dma_attr_idx : 6; +#else + u32 dma_attr_idx : 6; /* It specifies the outbound PCIe TLP header attribute of the DMA operation. + * This filed is only valid when processing CQ's CQEs. */ + u32 so_ro : 2; /* It specifies the ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation. + * This field is only valid when processing CQ's CQEs. + * 2'b00: Strict Ordering; + * 2'b01: Relaxed Ordering; + * 2'b10: ID Based Ordering; + * 2'b11: Both Relaxed Ordering and ID Based Ordering. */ + u32 cos : 3; + u32 ep : 3; + u32 rsvd : 14; + u32 state : 4; +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqe_prefetch_max_num : 3; + u32 wqe_prefetch_min_num : 3; + u32 wqe_cache_thd_sel : 2; + u32 wqecnt_lth : 4; + u32 wqecnt_ctrl_en : 1; + u32 wqecnt_rctl : 1; + u32 mtt_prefetch_maxlen : 2; + u32 next_wqe_idx : 16; +#else + u32 next_wqe_idx : 16; /* The current WQE index; uses this field to get the corresponding WQE from SRQ. */ + u32 mtt_prefetch_maxlen : 2; + u32 wqecnt_rctl : 1; /* The hardware clear it to zero when performing a SRQ PCnt updating, and driver + set it to one to indicate the hardware can performing SRQ PCnt updating. */ + u32 wqecnt_ctrl_en : 1; + u32 wqecnt_lth : 4; + u32 wqe_cache_thd_sel : 2; /* Maximum length of prefetch MTTs for SRQ. + 000: prefetch length equals to zero; + Others: prefetch length equals to + (2^(srq_mtt_prefetch_maxlen-1)*1KB). */ + u32 wqe_prefetch_min_num : 3; /* Minimum number of prefetch WQEBBs for SRQ. + 000: prefetch number equals to zero; + Others: prefetch number equals to (2^(srq_wqe_prefetch_minnum-1)). + */ + u32 wqe_prefetch_max_num : 3; /* Maximum number of prefetch WQEBBs for SRQ. + 000: prefetch number equals to zero; + Others: prefetch number equals to (2^srq_wqe_prefetch_maxnum). */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 container : 1; + u32 pcnt_on_chip : 1; + u32 lth_pre_en : 1; + u32 rkey_en : 1; + u32 wqe_check_en : 1; + u32 lth_gap : 4; + u32 rsvd : 5; + u32 pd : 18; +#else + u32 pd : 18; + u32 rsvd : 5; + u32 lth_gap : 4; + u32 wqe_check_en : 1; + u32 rkey_en : 1; + u32 lth_pre_en : 1; + u32 pcnt_on_chip : 1; + u32 container : 1; +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 srqn; + + /* DW5 */ + u32 xrc_cqn; + + /* DW6~7 */ + union { + u64 l0mtt_gpa; /* The GPA of Layer 0 MTT. It may point to the CQ's buffer directly.low 3bits(cq_gpa_sign) */ + struct { + u32 l0mtt_gpa_hi; + u32 l0mtt_gpa_lo; + } dw6_dw7; + }; + + /* DW8~9 */ + union { + u64 record_gpa_at_hop_num; /* The GPA of stored CI of Complete Queue. + * Address translation hop numbers. + * 0x0: the 'cq_l0mtt_gpa' points to the buffer of CQ directly. + * 0x1: it need to perform one hop address translation to get the buffer's + * address of CQ; 0x2: there is two hop address translation to get the buffer's + * address of CQ; 0x3: reserved. */ + struct { + u32 record_gpa_hi; + u32 record_gpa_lo_at_hop_num; /* bit[1:0] Address translation hop numbers */ + } dw8_dw9; + }; + + roce_verbs_srq_cont_attr_s cont; +} roce_verbs_srq_attr_s; + +typedef struct tag_roce_verbs_srq_hw2sw_info { + /* DW0~3 */ + u32 srq_buf_len; + u32 wqe_cache_line_start; + u32 wqe_cache_line_end; + u32 wqe_cache_line_size; + + /* DW4~8 */ + roce_verbs_mtt_cacheout_info_s cmtt_cache; +} roce_verbs_srq_hw2sw_info_s; + +typedef union tag_roce_verbs_arm_srq_info { + u32 limitwater; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 lwm : 16; + u32 warth : 4; + u32 th_up_en : 1; + u32 cont_en : 1; + u32 rsvd : 10; +#else + u32 rsvd : 10; + u32 cont_en : 1; + u32 th_up_en : 1; + u32 warth : 4; + u32 lwm : 16; +#endif + } bs; +} roce_verbs_arm_srq_info_u; +#pragma pack() + +#endif /* ROCE_VERBS_SRQ_ATTR_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ulp_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ulp_format.h new file mode 100644 index 000000000..3b69c0014 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ulp_format.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA cmdq commands upper level format. + * Create: 2021-12-30 + */ + +#ifndef ROCE_VERBS_ULP_FORMAT_H +#define ROCE_VERBS_ULP_FORMAT_H +#include "roce_verbs_cmd.h" +#include "roce_ccf_format.h" + +/*******************AA*******************/ +typedef struct tag_roce_aa_master_modify_qpc { + roce_verbs_cmd_com_s com; + u32 opt; + u32 qid; + u32 local_comm_id; + u32 remote_comm_id; + + roce_qp_context_s qpc; +} roce_aa_master_modify_qpc_s; + +typedef struct tag_roce_aa_slave_modify_qpc { + roce_verbs_cmd_com_s com; + u32 gid_index; + u32 qid; + u32 local_comm_id; + u32 remote_comm_id; + + roce_qp_context_s qpc; +} roce_aa_slave_modify_qpc_s; + +typedef struct roce_aa_set_conn_stat_inbuf { + roce_verbs_cmd_com_s com; + u32 qid; + u32 io_qpn[9]; +} roce_set_conn_sts_s; + +typedef struct roce_aa_get_master_qpn_inbuf { + roce_verbs_cmd_com_s com; +} roce_aa_get_master_qpn_inbuf_s; + +typedef struct roce_aa_disconnect_inbuf { + roce_verbs_cmd_com_s com; + u32 tid_h; + u32 tid_l; + u32 rsvd4; + u32 rsvd5; + u32 local_cmid; + u32 remote_cmid; + u32 remote_qpn; +} roce_aa_disconnect_inbuf_s; + +struct roce_shard_map_entry { + u32 volume_id; + u32 hash_low_cnt : 8; + u32 dd_id : 8; + u32 lun_id : 16; + + u32 rsvd : 8; + u32 hash_high_offset : 8; + u32 hash_low_offset : 8; + u32 hash_high_cnt : 8; + u32 admin_qpn; +}; + +typedef struct roce_aa_set_shard_cfg_inbuf { + roce_verbs_cmd_com_s com; + u32 op; + u32 entry_num; + struct roce_shard_map_entry shard_info[64]; +} roce_aa_set_shard_cfg_s; + +typedef struct roce_master_qp_modify2rst_inbuf { + roce_verbs_cmd_com_s com; +} roce_master_qp_modify2rst_s; + +typedef struct tag_roce_aa_query_master_qp_bitmap { + roce_verbs_cmd_com_s com; +} roce_aa_query_master_qp_bitmap_s; + +/*******************VBS*******************/ +typedef struct tag_roce_vbs_master_modify_qpc { + roce_verbs_cmd_com_s com; + + u32 opt; + u32 sqpc_ci_record_addr_h; + u32 sqpc_ci_record_addr_l; + u32 rsvd; + + roce_qp_context_s qpc; +} roce_vbs_master_modify_qpc_s; + +#endif /* ROCE_VERBS_ULP_FORMAT_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_wqe_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_wqe_format.h new file mode 100644 index 000000000..3dabbdc26 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_wqe_format.h @@ -0,0 +1,825 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA wqe structure format. + * Create: 2021-12-30 + */ + +#ifndef ROCE_WQE_FORMAT_H +#define ROCE_WQE_FORMAT_H + +/* **************************************************************** */ +struct roce3_wqe_ctrl_seg { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 owner : 1; + u32 ctrlsl : 2; + u32 csl : 2; + u32 difsl : 3; + u32 cr : 1; + u32 df : 1; + u32 va : 1; + u32 tsl : 5; + u32 cf : 1; + u32 wf : 1; + u32 rsvd : 4; + u32 drvsl : 2; + u32 bdsl : 8; +#else + u32 bdsl : 8; /* Data segment length, in the unit of 1B. When inline is used, the length of inline is + described. The total length of the data segment must be aligned to 8B. */ + u32 drvsl : 2; /* Indicates the length of the driver section. The value is counted by 8B, and the value of + RoCE is 0. */ + u32 rsvd : 4; + u32 wf : 1; /* 0-Normal WQE, 1-link WQE */ + u32 cf : 1; /* Complete segment format flag. The 0-complete segment directly contains the status information. + 1: SGL */ + u32 tsl : 5; /* Length of the task segment. The value ranges from 8 to 48. The value of RoCE ranges from 8 + to 48. */ + u32 va : 1; /* SGE address format flag. The 0-SGE contains the physical address and length. The 1-SGE + contains the virtual address, length, and key. The value of RoCE is 1. */ + u32 df : 1; /* Data segment format flag bit. 0-describes data in SGE format. 1: Data is described in inline + format. */ + u32 cr : 1; /* The CQE generates the request flag. The 0-does not generate the CQE. 1: Generate CQE */ + u32 difsl : 3; /* DIF segment length. The value is counted by 8 bytes. The value of RoCE is 0. */ + u32 csl : 2; /* Length of the completed segment. The value is counted by 8B. The value of RoCE is 0. */ + u32 ctrlsl : 2; /* Length of the control segment. The value is 8 bytes and the value of RoCE is 16. */ + u32 owner : 1; /* Owner bit. The value 1 indicates all hardware, and the value 0 indicates all software. The + meaning of the queue owner bit is reversed every time the queue owner is traversed. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cl : 4; + u32 signature : 8; + u32 rsvd : 4; + u32 mask_pi : 16; +#else + u32 mask_pi : 16; /* Pi is the value of the queue depth mask. It is valid when direct wqe. */ + u32 rsvd : 4; + u32 signature : 8; + u32 cl : 4; /* The length of CQE is generated in the task segment. */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 type : 2; + u32 rsvd1 : 3; + u32 cos : 3; + u32 cp_flag : 1; + u32 rsvd : 1; + u32 ctx_size : 2; + u32 qpn : 20; +#else + u32 qpn : 20; + u32 ctx_size : 2; /* RoCE QPC size, 512B */ + u32 rsvd : 1; + u32 cp_flag : 1; /* control plane flag */ + u32 cos : 3; /* Scheduling priority. The value source is SL. */ + u32 rsvd1 : 3; + u32 type : 2; /* Set RoCE SQ Doorbell to 2 and RoCE Arm CQ Doorbell to 3. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sub_type : 4; /* */ + u32 sgid_index : 7; /* gid index */ + u32 mtu_shift : 3; /* 256B:0;512B:1;1024B:2;2048B:3;4096B:4 */ + u32 rsvd : 1; + u32 xrc_vld : 1; /* 1:XRC service type */ + u32 pi : 16; /* host sw write the sq produce index high 8bit to this section; */ +#else + u32 pi : 16; /* host sw write the sq produce index high 8bit to this section; */ + u32 xrc_vld : 1; + u32 rsvd : 1; + u32 mtu_shift : 3; + u32 sgid_index : 7; + u32 sub_type : 4; +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 queue_id : 4; + u32 rsvd : 12; + u32 pi : 16; +#else + u32 pi : 16; + u32 rsvd : 12; + u32 queue_id : 4; +#endif + } bs1; + u32 value; + } dw3; +}; + +typedef union roce3_wqe_tsk_com_seg { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 se : 1; + u32 f : 1; + u32 c : 1; + u32 op_type : 5; + u32 so : 1; + u32 cs_len_mul : 3; + u32 dif_en : 1; + u32 ext_vld : 1; + u32 xrc_srqn : 18; +#else + u32 xrc_srqn : 18; /* The XRC is valid, and the remote SRQN is specified. */ + u32 ext_vld : 1; + u32 dif_en : 1; + u32 cs_len_mul : 3; /* * atomic cmp swap N len:atomic datalen=8*(cs_len_mul + 1) */ + u32 so : 1; /* Strong order-preserving flag, valid only for Local invalidate\Type 2 Bind MW and FRPMR (consider + the implementation at the bottom layer) */ + u32 op_type : 5; /* Operation type of the SQ WQE. + * 8'h00-Send + * 8'h01-Send with Invalidate + * 8'h02-Send with Immediate Data + * 8'h03-rsvd + * 8'h04-RDMA Write + * 8'h05-RDMA Write with Immediate Data + * 8'h06-RDMA WRITE CMD64 + * 8'h07-rsvd + * 8'h08-RDMA READ + * 8'h09-ATOMIC WRITE + * 8'h0a-FLUSH + * 8'h0b-rsvd + * 8'h0c-Atomic compare & swap + * 8'h0d-Atomic Fetch & ADD + * 8'h0e-Atomic Masked Compare & Swap (Extended Atomic operation) + * 8'h0f-Atomic Masked Fetch & Add (Extended Atomic operation) + * 8'h10-Fast Register PMR + * 8'h11-Local Invalidate + * 8'h12-Bind Memory Window Type1/2 + * 8'h13-Local operation(extended for further local operation) + * other-Reserved */ + u32 c : 1; /* Indicates whether the SQ generates the CQE, which is required by the microcode. */ + u32 f : 1; /* Indicates whether the SQ requires order-preserving. */ + u32 se : 1; /* Indicates whether the packet carries the SE flag. */ +#endif + } bs; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 se : 1; + u32 f : 1; + u32 c : 1; + u32 op_type : 5; + u32 so : 1; + u32 rsvd : 2; + u32 vbs_vld : 1; + u32 dif_en : 1; + u32 ext_vld : 1; + u32 xrc_srqn : 18; +#else + u32 xrc_srqn : 18; + u32 ext_vld : 1; + u32 dif_en : 1; + u32 vbs_vld : 1; + u32 rsvd : 2; + u32 so : 1; + u32 op_type : 5; + u32 c : 1; + u32 f : 1; + u32 se : 1; +#endif + } bs1; + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 14; + u32 sticky : 1; + u32 repeat : 1; + u32 cmdid : 16; +#else + u32 cmdid : 16; + u32 repeat : 1; + u32 sticky : 1; + u32 rsvd : 14; +#endif + } nofaa; + u32 value; +} roce_wqe_tsk_com_seg_u; + +typedef union roce3_wqe_tsk_misc_seg { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 ext_last : 1; + u32 nxt_ext_hdr : 7; + u32 cmd_len : 8; + u32 rsvd : 8; + u32 last_ext_len : 8; +#else + u32 last_ext_len : 8; + u32 rsvd : 8; + u32 cmd_len : 8; + u32 nxt_ext_hdr : 7; + u32 ext_last : 1; +#endif + } bs; + + u32 value; +} roce3_wqe_tsk_misc_seg_u; + +typedef struct roce3_wqe_tsk_rdma_sge_seg { + /* DW4~5 */ + union { + u64 va; + struct { + u32 va_h32; + u32 va_l32; + } dw4; + }; + + /* DW6 */ + u32 rkey; + + /* DW7 */ + u32 sig_key; +} roce3_wqe_tsk_rdma_sge_seg_s; + +/* * + * Struct name: sq_wqe_task_remote_common_s. + * @brief : SQ WQE common. + * Description: + */ +typedef struct tag_sq_wqe_task_remote_common { + roce_wqe_tsk_com_seg_u common; + + u32 data_len; /* SQ WQE DMA LEN */ + + u32 immdata_invkey; /* SEND invalidate or immedate */ + + roce3_wqe_tsk_misc_seg_u dw3; +} sq_wqe_task_remote_common_s; + +/* Send WQE/Send with imme WQE/Send with invalid(inline or not inline) */ +typedef struct roce3_wqe_send_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; /* Length of the data sent by the SQ WQE */ + + /* DW2 */ + u32 immdata_invkey; /* This parameter is valid for the immediate data operation or SEND invalidate. */ + + /* DW3 */ + roce3_wqe_tsk_misc_seg_u dw3; +} roce3_wqe_send_tsk_seg_s; + +/* RDMA Read WQE/RDMA Write WQE/RDMA Write with imme WQE(inline or non-inline) */ +typedef struct roce3_wqe_rdma_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; + + /* DW2 */ + u32 imm_data; + + /* DW3 */ + roce3_wqe_tsk_misc_seg_u dw3; + + /* DW4~5 */ + union { + u64 va; + struct { + u32 va_h32; + u32 va_l32; + } dw4; + }; + + /* DW6 */ + u32 rkey; + + /* DW7 */ + u32 sig_key; +} roce3_wqe_rdma_tsk_seg_s; + +/* RDMA Read WQE/RDMA Write WQE/RDMA Write with imme WQE(inline or non-inline) */ +typedef struct roce3_wqe_rdma_ext_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; + + /* DW2 */ + u32 imm_data; + + /* DW3 */ + roce3_wqe_tsk_misc_seg_u dw3; + + /* DW4~5 */ + roce3_wqe_tsk_rdma_sge_seg_s rdma; + + u32 ulp_cmd[24]; +} roce3_wqe_rdma_ext_tsk_seg_s; + +/* Atomic WQE */ +typedef struct roce3_wqe_atomic_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 key; + + /* DW2~3 */ + union { + u64 va; + struct { + u32 va_h32; + u32 va_l32; + } dw2; + }; + + /* DW4~5 */ + union { + u64 swap_add_data; + struct { + u32 swap_add_data_h32; + u32 swap_add_data_l32; + } dw4; + }; + + /* DW6~7 */ + union { + u64 cmp_data; + struct { + u32 cmp_data_h32; + u32 cmp_data_l32; + } dw6; + }; +} roce3_wqe_atomic_tsk_seg_s; + +/* ext Atomic WQE */ +#define ROCE_WQE_ATOMIC_DATA_SIZE 32 +#define ROCE_WQE_ATOMIC_DATA_SIZE_2B_ALIGN (ROCE_WQE_ATOMIC_DATA_SIZE >> 1) +typedef struct roce3_wqe_ext_atomic_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 key; + + /* DW2~3 */ + union { + u64 va; + struct { + u32 va_h32; + u32 va_l32; + } dw2; + }; + + u32 atomic_data[ROCE_WQE_ATOMIC_DATA_SIZE]; +} roce3_wqe_ext_atomic_tsk_seg_s; + +/* Mask Atomic WQE */ +typedef struct roce3_wqe_mask_atomic_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 rkey; + + /* DW2~3 */ + union { + u64 va; + struct { + u32 va_h32; + u32 va_l32; + } dw2; + }; + + /* DW4~5 */ + union { + u64 swap_add_data; + struct { + u32 swap_add_data_h32; + u32 swap_add_data_l32; + } dw4; + }; + + /* DW6~7 */ + union { + u64 cmp_data; + struct { + u32 cmp_data_h32; + u32 cmp_data_l32; + } dw6; + }; + + /* DW8~9 */ + union { + u64 swap_msk; + struct { + u32 swap_msk_h32; + u32 swap_msk_l32; + } dw8; + }; + + /* DW9~10 */ + union { + u64 cmp_msk; + struct { + u32 cmp_msk_h32; + u32 cmp_msk_l32; + } dw10; + }; +} roce3_wqe_mask_atomic_tsk_seg_s; + +/* UD send WQE */ +typedef struct roce3_wqe_ud_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW1 */ + u32 data_len; + + /* DW2 */ + u32 immdata_invkey; + + roce3_wqe_tsk_misc_seg_u dw2; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 fl : 1; + u32 wqe_cos : 3; /* DB cos or Path cos or MQM cos */ + u32 stat_rate : 4; + u32 rsvd : 6; + u32 pd : 18; +#else + u32 pd : 18; /* Used to verify the PD in the QPC. */ + u32 rsvd : 6; + u32 stat_rate : 4; /* Maximum static rate control 0: No limit on the static rate (100% port speed) + * 1-6: reserved + * 7: 2.5 Gb/s. 8: 10 Gb/s. 9: 30 Gb/s. 10: 5 Gb/s. 11: 20 Gb/s. + * 12: 40 Gb/s. 13: 60 Gb/s. 14: 80 Gb/s.15: 120 Gb/s. */ + u32 wqe_cos : 3; /* DB cos or Path cos or MQM cos */ + u32 fl : 1; +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 tc : 8; + u32 rsvd : 4; + u32 port : 4; + u32 vlan_en : 1; + u32 sgid_idx : 7; + u32 hop_limit : 8; +#else + u32 hop_limit : 8; + u32 sgid_idx : 7; + u32 vlan_en : 1; + u32 port : 4; + u32 rsvd : 4; + u32 tc : 8; +#endif + } bs; + u32 value; + } dw4; + + /* DW5 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 2; + u32 smac_index : 10; + u32 flow_label : 20; +#else + u32 flow_label : 20; + u32 smac_index : 10; + u32 rsvd : 2; +#endif + } bs; + u32 value; + } dw5; + + /* DW6~9 */ + u8 dgid[16]; + + /* DW10 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 dst_qp : 24; +#else + u32 dst_qp : 24; + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw10; + + /* DW11 */ + u32 qkey; + + /* DW12 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 vlan_pri : 3; /* send pkt pri */ + u32 cfi : 1; + u32 vlan_id : 12; + u32 dmac_h16 : 16; +#else + u32 dmac_h16 : 16; + u32 vlan_id : 12; + u32 cfi : 1; + u32 vlan_pri : 3; /* send pkt pri */ +#endif + } bs; + u32 value; + } dw12; + + /* DW14 */ + u32 dmac_l32; + + /* DW15 */ + u32 rsvd; +} roce3_wqe_ud_tsk_seg_s; + +typedef struct roce3_wqe_data_seg { + /* DW0~1 */ + union { + u64 addr; + struct { + u32 addr_h32; + u32 addr_l32; + } bs; + }; + + /* DW2~3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 1; + u32 len : 31; +#else + u32 len : 31; + u32 rsvd : 1; +#endif + } bs; + u32 value; + } dw2; + + /* DW4 */ + u32 key; +} roce3_wqe_data_seg_s; + +/* Type1/2 MW Bind WQE */ +typedef struct roce3_wqe_bind_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW0~2 */ + u32 rsvd0[3]; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rae : 1; + u32 rwe : 1; + u32 rre : 1; + u32 type : 1; + u32 rsvd : 28; +#else + u32 rsvd : 28; + u32 type : 1; /* MW type: 0-Type1 Window 1-Type2B Window */ + u32 rre : 1; /* Remote read enable */ + u32 rwe : 1; /* Remote write enable */ + u32 rae : 1; /* Indicates whether remote Atomic is enabled. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 new_rkey; /* The MW corresponds to the MPT key and is indexed to the MPT through the New_Rkey. For the type1 MW, + * This parameter is valid only when the value of New_Rkey is the same as the value of mem_key in the + * MPT. For type 2 MW, it is valid only when New_Rkey is equal to mem_key+1 in MPT. + * If this parameter is valid, the corresponding field in the MPT is replaced with the entire + * section. */ + + /* DW5 */ + u32 lkey; /* Indicates the mem_key of the MR bound to the MW. */ + + /* DW6 */ + u32 rsvd1; + + /* DW7~8 */ + union { + u64 va; /* Indicates the start virtual IP address of the MW. */ + struct { + u32 va_h32; + u32 va_l32; + } bs; + } dw7; + + /* DW9~10 */ + union { + u64 len; /* Indicates the length of the data corresponding to the MW. */ + struct { + u32 len_h32; + u32 len_l32; + } bs; + } dw9; +} roce3_wqe_bind_tsk_seg_s; + +/* Fast Register PMR WQE */ +typedef struct roce3_wqe_frmr_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW0~1 */ + u32 rsvd[2]; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 fbo : 22; + u32 rsvd : 10; +#else + u32 rsvd : 10; + u32 fbo : 22; /* This parameter is valid when ZERO_BASE is set to 1. */ +#endif + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rae : 1; + u32 rwe : 1; + u32 rre : 1; + u32 lwe : 1; + u32 lre : 1; + u32 be : 1; + u32 zbva : 1; + u32 block : 1; + u32 rsvd : 2; + u32 page_size : 6; + u32 pa_num : 16; +#else + u32 pa_num : 16; /* Number of registered PAs, which is calculated by the length/page_size. */ + u32 page_size : 6; /* Memory Region page size */ + u32 rsvd : 2; + u32 block : 1; + u32 zbva : 1; /* ZERO_BASED Permission */ + u32 be : 1; /* Indicates whether the binding operation is enabled. */ + u32 lre : 1; /* Local read enable */ + u32 lwe : 1; /* Local write enable */ + u32 rre : 1; /* Remote read enable */ + u32 rwe : 1; /* Remote write enable */ + u32 rae : 1; /* Indicates whether remote Atomic is enabled. */ +#endif + } bs; + u32 value; + } dw3; + + /* DW4 */ + u32 m_key; /* Key of the Memory Region. */ + + /* DW5~6 */ + union { + u64 va; /* Start virtual address of Memory Region. This parameter is valid only when ZBVA is not set to 1. */ + struct { + u32 va_h32; + u32 va_l32; + } bs; + } dw5; + + /* DW7~8 */ + union { + u64 len; /* Length of Memory Region */ + struct { + u32 len_h32; + u32 len_l32; + } bs; + } dw7; + + /* DW9~10 */ + union { + u64 pbl_addr; /* Physical address for storing the cache of the PA table. */ + struct { + u32 pbl_addr_h32; + u32 pbl_addr_l32; + } bs; + } dw9; +} roce3_wqe_frmr_tsk_seg_s; + +typedef struct roce3_sge_info { + union { + u64 sge_vaddr; + struct { + u32 sge_vaddr_hi; + u32 sge_vaddr_lo; + } bs; + } dw0; + + u32 sge_length; + u32 sge_key; +} roce3_sge_info_s; + + +/* Local Invalidate WQE */ +typedef struct roce3_wqe_local_inv_tsk_seg { + roce_wqe_tsk_com_seg_u common; + + /* DW0 */ + u32 rsvd; + + /* DW1 */ + u32 inv_key; /* Mem_Key for invalidate */ + + /* DW2 */ + u32 rsvd1; +} roce3_wqe_local_inv_tsk_seg_s; + +/* * SRQ Data Format start */ +typedef struct roce3_wqe_srq_data_seg { + /* DW0~1 */ + union { + u64 addr; + + struct { + u32 addr_h32; + u32 addr_l32; + } bs; + }; + + /* DW2 */ + union { + struct { + u32 rsv : 1; /* Reserved field */ + u32 len : 31; /* Data length. The value can be [0 or 2G-1]. */ + } bs; + u32 length; + } dw2; + + /* DW3 */ + union { + struct { + u32 last : 1; /* Last flag. The 0-also has the next SGE. 1: The current SGE is the last one. */ + u32 ext : 1; /* Extended flag. The value 0-is normal and does not need to be extended. 1: Extended mode. The + address of the current SGE points to SGL. The key and len are invalid. For RoCE, the value + is fixed to 0. */ + u32 key : 30; /* Local_key. The least significant eight bits are keys, and the most significant 22 bits are + indexes. The most significant two bits are reserved and only 20 bits are used. */ + } bs; + u32 lkey; + } dw3; +} roce3_wqe_srq_data_seg_s; +/* * SRQ Data Format end */ + +typedef struct roce_osd_srq_link_wqe { + u32 cont_gpa_h; + + union { + struct { + u32 cont_gpa_l : 24; + u32 rsvd : 8; + } bs; + u32 value; + } dw1; + + u32 rsvd; + + union { + struct { + u32 rsvd : 1; + u32 link_flag : 1; + u32 rsvd1 : 30; + } bs; + u32 value; + } dw3; + + union { + struct { + u32 cur_container_idx : 16; + u32 container_idx : 16; + } bs; + u32 value; + } dw4; +} roce_osd_srq_link_wqe_s; + + +#endif // ROCE_WQE_FORMAT_H diff --git a/drivers/infiniband/hw/hiroce3/include/rdma/roce_xqe_format.h b/drivers/infiniband/hw/hiroce3/include/rdma/roce_xqe_format.h new file mode 100644 index 000000000..9faccbc49 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/rdma/roce_xqe_format.h @@ -0,0 +1,500 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * Description: RDMA XQE format. + * Create: 2021-12-30 + */ + +#ifndef ROCE_XQE_FORMAT_H +#define ROCE_XQE_FORMAT_H + +/* * SQ DB Format start */ +typedef struct roce_sq_db_seg { + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 type : 5; + u32 cos : 3; + u32 cp_flag : 1; + u32 rsvd : 1; + u32 ctx_size : 2; + u32 qpn : 20; +#else + u32 qpn : 20; + u32 ctx_size : 2; /* RoCE QPC size, 512B */ + u32 rsvd : 1; + u32 cp_flag : 1; /* control plane flag */ + u32 cos : 3; /* Scheduling priority. The value source is SL. */ + u32 type : 5; /* Set RoCE SQ Doorbell to 2 and RoCE Arm CQ Doorbell to 3. */ +#endif + } bs; + u32 value; + } dw0; + + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 sub_type : 4; /* */ + u32 sgid_index : 7; /* gid index */ + u32 mtu_shift : 3; /* 256B:0;512B:1;1024B:2;2048B:3;4096B:4 */ + u32 rsvd : 1; + u32 xrc_vld : 1; /* 1:XRC service type */ + u32 resv : 8; + u32 pi : 8; /* host sw write the sq produce index high 8bit to this section; */ +#else + u32 pi : 8; /* host sw write the sq produce index high 8bit to this section; */ + u32 resv : 8; + u32 xrc_vld : 1; + u32 rsvd : 1; + u32 mtu_shift : 3; + u32 sgid_index : 7; + u32 sub_type : 4; +#endif + } bs; + u32 value; + } dw1; +} roce_sq_db_seg_s; + +union roce_sq_db { + roce_sq_db_seg_s sq_db_seg; + union { + u64 sq_db_val; + struct { + u32 sq_db_val_h32; + u32 sq_db_val_l32; + } dw2; + }; +}; + +/* *SQ DB Format end */ + +/* * ARM CQ DB Format start */ +typedef struct roce_db_cq_arm { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 type : 5; /* dB type. The value of RoCE ARM CQ DB is 3. */ + u32 cos : 3; /* ARM CQ DB Not required */ + u32 cp : 1; /* the control plane flag of a DB */ + u32 non_filter : 1; + u32 cqc_type : 2; /* Cq type, 0: RDMA/1:T/IFOE/2.3: Rsv */ + u32 cqn : 20; +#else + u32 cqn : 20; + u32 cqc_type : 2; /* Cq type, 0: RDMA/1:T/IFOE/2.3: Rsv */ + u32 non_filter : 1; + u32 cp : 1; /* the control plane flag of a DB */ + u32 cos : 3; /* ARM CQ DB Not required */ + u32 type : 5; /* dB type. The value of RoCE ARM CQ DB is 3. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 cmd_sn : 2; /* The ArmCQ DB carries the CmdSn, which is compared with the CmdSn in the chip. If the is + * different from the in the chip, the is valid. If the is the same, the needs to be + * checked. -- + * Each time a CEQE is generated, the CmdSn of the chip is updated to the CmdSn of the + * latest ArmCq DB. */ + u32 cmd : 2; /* Run the Arm command. 0-non-Arm After receiving the next CQE with the SE, the 1-ARM SOLICITED + generates the CEQE. The * 2-ARM NEXT generates the CEQE after receiving the next CQE. */ + u32 rsv1 : 4; + u32 ci : 24; /* Consumer pointer */ +#else + u32 ci : 24; /* Consumer pointer */ + u32 rsv1 : 4; + u32 cmd : 2; /* Run the Arm command. 0-non-Arm After receiving the next CQE with the SE, the 1-ARM SOLICITED + generates the CEQE. The * 2-ARM NEXT generates the CEQE after receiving the next CQE. */ + + u32 cmd_sn : 2; /* The ArmCQ DB carries the CmdSn, which is compared with the CmdSn in the chip. If the + * values are different, the is valid. If the values are the same, the needs to be checked. + * -- Each time a CEQE is generated, the CmdSn of the chip is updated to the CmdSn of the + * latest ArmCq DB. */ +#endif + } bs; + u32 value; + } dw1; +} roce_db_cq_arm_s; +/* * ARM CQ DB Format end */ + +/* * CQE Format start */ +typedef struct roce_cqe { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 owner : 1; /* Owner bit. During initialization, 0 indicates all hardware, and 1 indicates all software. + * This bit is modified when the hardware writes the CQE. + * The meaning of each queue owner bit is reversed. */ + u32 size : 2; /* For roce, this field is reserved. */ + u32 dif_en : 1; /* For roce, this field is reserved. */ + u32 wq_id : 4; /* For roce, this field is reserved. */ + u32 error_code : 4; /* For roce, this field is reserved. */ + u32 qpn : 20; /* Local QPN, which is used in all cases. The driver finds the software QPC based on the QPN. */ +#else + u32 qpn : 20; /* Local QPN, which is used in all cases. The driver finds the software QPC based on the QPN. */ + u32 error_code : 4; /* For roce, this field is reserved. */ + u32 wq_id : 4; /* For roce, this field is reserved. */ + u32 dif_en : 1; /* For roce, this field is reserved. */ + u32 size : 2; /* For roce, this field is reserved. */ + u32 owner : 1; /* Owner bit. During initialization, 0 indicates all hardware, and 1 indicates all software. + * This bit is modified when the hardware writes the CQE. + * The meaning of each queue owner bit is reversed. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 op_type : 5; /* The same as what is for SQ WQE. For details, see the enumeration roce_cqe_opcode */ + u32 s_r : 1; /* Indicates SQ CQE or RQ CQE. 1-Send Completion; 0-Receive Completion */ + u32 inline_r : 1; /* Indicates whether RQ inline; SQ ignores this bit */ + u32 flush_op : 1; + u32 fake : 1; /* Indicates whether the CQE is a fake one. When fake, optype & syndronme should be 0 */ + u32 rsvd : 3; + u32 wqebb_cnt : 20; /* The WQEBB index and SQ/RQ/SRQ are valid. */ +#else + u32 wqebb_cnt : 20; /* The WQEBB index and SQ/RQ/SRQ are valid. */ + u32 rsvd : 3; + u32 fake : 1; /* Indicates whether the CQE is a fake one. When fake, optype & syndronme should be 0 */ + u32 flush_op : 1; + u32 inline_r : 1; /* Indicates whether RQ inline; SQ ignores this bit */ + u32 s_r : 1; /* Indicates SQ CQE or RQ CQE. 1-Send Completion; 0-Receive Completion */ + u32 op_type : 5; /* The same as what is for SQ WQE. For details, see the enumeration roce_cqe_opcode */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + u32 byte_cnt; /* Indicates the number of transmitted bytes. This field is valid for the RDMA read and receive + operations. For the recv of RDMA write imm, the value is 0. */ + + /* DW3 */ + u32 imm_invalid_rkey; /* The receiving is complete and valid. */ + + /* DW4 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 vlan_id : 12; + u32 rsvd : 1; + u32 vlan_pri : 3; + u32 smac_h : 16; +#else + u32 smac_h : 16; + u32 vlan_pri : 3; + u32 rsvd : 1; + u32 vlan_id : 12; +#endif + } bs; /* for ud only */ + u32 value; + } dw4; + + /* DW5 */ + u32 smac_l; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 vlan_pre : 2; /* The for ud only:UD receive end is valid. The 00-packet does not contain a VLAN ID. The + 01-packet contains a VLAN ID. */ + u32 fl : 1; /* This field is valid only for UD. Force loopback */ + u32 stp : 2; + u32 rsvd : 3; + u32 srqn_rqpn : 24; /* The XRC at the receive end is valid. When the XRCSRQ at the receive end is received, + the ;UD at the remote end refers to the QPN at the remote end. */ +#else + u32 srqn_rqpn : 24; /* The XRC at the receive end is valid. When the ;UD at XRCSRQ is received, the at the + remote end is the QPN at the remote end. */ + u32 rsvd : 3; + u32 stp : 2; + u32 fl : 1; /* This field is valid only for UD. Force loopback */ + u32 vlan_pre : 2; /* The for ud only:UD receive end is valid. The 00-packet does not contain a VLAN ID. The + 01-packet contains a VLAN ID. */ +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqe_cnt : 16; /* WQE index, valid SQ */ + u32 rsvd : 8; + u32 syndrome : 8; /* 0 indicates that the operation is complete. This parameter is valid when Op_type is set + to ROCE_OPCODE_ERR. For details about the definition, see the enumeration + roce_cqe_syndrome. */ +#else + u32 syndrome : 8; /* 0 indicates that the operation is complete. This field is valid when Op_type is set to + ROCE_OPCODE_ERR. For details, see the enumeration roce_cqe_syndrome. */ + u32 rsvd : 8; + u32 wqe_cnt : 16; /* WQE index, valid SQ */ +#endif + } bs; + u32 value; + } dw7; + + u32 timestamp_h; + u32 timestamp_l; + u32 common_rsvd[6]; +} roce_cqe_s; + +typedef struct roce_resize_cqe { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 owner : 1; /* Owner bit. During initialization, 0 indicates all hardware, and 1 indicates all software. + * This bit is overwritten when the hardware writes the CQE. The meaning of the queue owner + * bit is reversed every time the queue owner is traversed. */ + u32 rsvd : 31; +#else + u32 rsvd : 31; + u32 owner : 1; /* Owner bit. During initialization, 0 indicates all hardware, and 1 indicates all software. + * This bit is modified when the hardware writes the CQE. The meaning of the queue owner bit + * is reversed every time the queue owner is traversed. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see the enumeration + roce_cqe_opcode. */ + u32 s_r : 1; /* Indicates whether SQ CQE or RQ CQE is used. 1-Send Completion; 0-Receive Completion */ + u32 rsvd : 26; +#else + u32 rsvd : 26; + u32 s_r : 1; /* Indicates whether SQ CQE or RQ CQE is used. 1-Send Completion; 0-Receive Completion */ + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see the enumeration + roce_cqe_opcode. */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2~7 */ + u32 rsvd[6]; + + u32 common_rsvd[8]; +} roce_resize_cqe_s; + +typedef struct roce_err_cqe { + /* DW0 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 owner : 1; /* Owner bit. During initialization, 0 indicates all hardware, and 1 indicates all software. + * This bit is overwritten when the hardware writes the CQE. The meaning of the queue owner + * bit is reversed every time the queue owner is traversed. */ + u32 rsvd : 11; /* For RoCE, this field is reserved. */ + u32 qpn : 20; /* Local QPN, which is used in all cases. The driver finds the software QPC based on the QPN. */ +#else + u32 qpn : 20; /* Local QPN, which is used in all cases. The driver finds the software QPC based on the QPN. */ + u32 rsvd : 11; /* For roce, this field is reserved. */ + u32 owner : 1; /* Owner bit. During initialization, 0 indicates all hardware, and 1 indicates all software. + * This bit is overwritten when the hardware writes the CQE. The meaning of the queue owner + * bit is reversed every time the queue owner is traversed. */ +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see roce_cqe_opcode. */ + u32 s_r : 1; /* Indicates the SQ CQE or RQ CQE. 1-Send Completion; 0-Receive Completion */ + u32 inline_r : 1; + u32 flush_op : 1; + u32 fake : 1; + u32 rsvd : 3; + u32 wqebb_cnt : 20; /* The WQEBB index and SQ/RQ/SRQ are valid. */ +#else + u32 wqebb_cnt : 20; /* The WQEBB index and SQ/RQ/SRQ are valid. */ + u32 rsvd : 3; + u32 fake : 1; /* Indicates whether this CQE is a fake cqe or not.when fake = 1, optype & syndronme should be + 0 */ + u32 flush_op : 1; + u32 inline_r : 1; + u32 s_r : 1; /* Indicates the SQ CQE or RQ CQE. 1-Send Completion; 0-Receive Completion */ + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see roce_cqe_opcode. */ +#endif + } bs; + u32 value; + } dw1; + + /* DW2~5 */ + u32 rsvd[3]; + + u32 wqe_num; + + /* DW6 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 rsvd : 8; + u32 srqn : 24; /* The XRC at the receive end is valid, which is XRCSRQ. */ +#else + u32 srqn : 24; /* The XRC at the receive end is valid, which is the XRCSRQ number. */ + u32 rsvd : 8; +#endif + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 wqe_cnt : 16; /* WQE index: Indicates that the SQ is valid. */ + u32 vendor_err : 8; + u32 syndrome : 8; /* 0 indicates that the operation is successful. The value is valid when Op_type is + ROCE_OPCODE_ERR. For details, see the enumeration roce_cqe_syndrome. */ +#else + u32 syndrome : 8; /* 0 indicates that the operation is complete. This parameter is valid when Op_type is set + to ROCE_OPCODE_ERR. For details about the definition, see the enumeration + roce_cqe_syndrome. */ + u32 vendor_err : 8; + u32 wqe_cnt : 16; /* WQE index, valid SQ */ +#endif + } bs; + u32 value; + } dw7; + + u32 timestamp_h; + u32 timestamp_l; + u32 common_rsvd[6]; +} roce_err_cqe_s; + + +typedef struct roce_vbs_cqe { + /* DW0 */ + union { + struct { + u32 owner : 1; + u32 size : 2; + u32 dif_en : 1; + u32 wq_id : 4; + u32 error_code : 4; + u32 qpn : 20; + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see the enumeration + roce_cqe_opcode. */ + u32 s_r : 1; /* Indicates whether SQ CQE or RQ CQE is used. 1-Send Completion; 0-Receive Completion */ + u32 inline_r : 1; /* Indicates whether the RQ inline;SQ ignores this bit. */ + u32 rsvd : 5; + u32 msg_fst_wqe_ci : 20; + } bs; + u32 value; + } dw1; + + /* DW2 */ + u32 byte_cnt; /* Indicates the number of transmitted bytes. This field is valid for the RDMA read and receive + operations. For the recv of RDMA write imm, the value is 0. */ + + /* DW3 */ + u32 imm_invalid_rkey; /* The receiving is complete and valid. */ + + /* DW4 */ + u32 rsvd; + + /* DW5 */ + u32 wqe_num; + + /* DW6 */ + union { + struct { + u32 vlan_pre : 2; /* The for ud only:UD receive end is valid. The 00-packet does not contain a VLAN ID. The + 01-packet contains a VLAN ID. */ + u32 fl : 1; /* This field is valid only for UD. Force loopback */ + u32 stp : 2; + u32 rsvd : 3; + u32 srqn_rqpn : 24; /* The XRC at the receive end is valid. When the XRCSRQ at the receive end is received, + the ;UD at the remote end refers to the QPN at the remote end. */ + } bs; + u32 value; + } dw6; + + /* DW7 */ + union { + struct { + u32 wqe_cnt : 16; /* WQE index, valid SQ */ + u32 vendor_err : 8; + u32 syndrome : 8; /* 0 indicates that the operation is complete. This parameter is valid when Op_type is set + to ROCE_OPCODE_ERR. For details about the definition, see the enumeration + roce_cqe_syndrome. */ + } bs; + u32 value; + } dw7; + + u16 srq_container_idx[16]; +} roce_vbs_cqe_s; + +typedef struct roce_nofaa_cqe { + /* DW0 */ + u32 common_dw0; + + /* DW1 */ + union { + struct { +#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && ((BYTE_ORDER == BIG_ENDIAN)) + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see the enumeration + roce_cqe_opcode. */ + u32 s_r : 1; /* Indicates whether SQ CQE or RQ CQE is used. 1-Send Completion; 0-Receive Completion */ + u32 inline_r : 1; /* Indicates whether the RQ inline;SQ ignores this bit. */ + u32 flush_op : 1; + u32 fake : 1; + u32 repeat : 1; + u32 host_id : 2; + u32 wqebb_cnt : 20; /* The WQEBB index and SQ/RQ/SRQ are valid. */ +#else + u32 wqebb_cnt : 20; /* The WQEBB index and SQ/RQ/SRQ are valid. */ + u32 host_id : 2; + u32 repeat : 1; + u32 fake : 1; /* Indicates whether this CQE is a fake cqe or not.when fake = 1, optype & syndronme should be + 0 */ + u32 flush_op : 1; + u32 inline_r : 1; /* Indicates whether RQ inline;SQ ignores this bit. */ + u32 s_r : 1; /* Indicates the SQ CQE or RQ CQE. 1-Send Completion; 0-Receive Completion */ + u32 op_type : 5; /* The operation type is the same as that of SQ WQE. For details, see the enumeration + roce_cqe_opcode. */ +#endif + } bs; + u32 value; + } dw1; + + u32 common_rsvd[13]; + + union { + struct { + u32 rsvd : 4; + u32 sw_times : 2; + u32 sw_slave_id : 6; + u32 io_time : 20; + } bs; + u32 value; + } io_status; +} roce_nofaa_cqe_s; + +#endif // RDMA_XQE_FORMAT_H diff --git a/drivers/infiniband/hw/hiroce3/include/readme.txt b/drivers/infiniband/hw/hiroce3/include/readme.txt new file mode 100644 index 000000000..ff76dff0e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/readme.txt @@ -0,0 +1 @@ +本目录是主机软件代码中共享的业务头文件实现的代码目录 \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/roce_cdev_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_cdev_extension.h new file mode 100644 index 000000000..bb58340ac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_cdev_extension.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_cdev_extension.h + * Version : v1.0 + * Created : 2022/1/27 + * Last Modified : 2022/1/27 + * Description : The definition of RoCE async event module standard callback function prototypes, macros etc., + */ + +#ifndef ROCE_CDEV_EXTENSION_H +#define ROCE_CDEV_EXTENSION_H + +#include "roce.h" + +#define NOT_SUPOORT_TYPE 0xFFFFFFFF + +long ioctl_non_bonding_extend(unsigned int cmd, struct roce3_device *rdev, unsigned long arg); + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/roce_event_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_event_extension.h new file mode 100644 index 000000000..a4ad1dbb1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_event_extension.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_event_extension.h + * Version : v1.0 + * Created : 2022/1/27 + * Last Modified : 2022/1/27 + * Description : The definition of RoCE async event module standard callback function prototypes, macros etc., + */ + +#ifndef ROCE_EVENT_EXTENSION_H +#define ROCE_EVENT_EXTENSION_H + +#include "roce_event.h" + +void roce3_event_report_extend(const struct roce3_device *rdev, int event_str_index); + +int roce3_async_event_handle_extend(u8 event_type, u8 *val, struct roce3_device *rdev); + +#endif /* ROCE_EVENT_EXTENSION_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/roce_main_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_main_extension.h new file mode 100644 index 000000000..e5b5be792 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_main_extension.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_main_extension.h + * Version : v1.0 + * Created : 2021/10/18 + * Last Modified : 2021/11/2 + * Description : The definition of RoCE MAIN extended functions prototype. + */ + +#ifndef ROCE_MAIN_EXTENSION_H +#define ROCE_MAIN_EXTENSION_H + +#include <linux/pci.h> + +#include "hinic3_hw.h" +#include "hinic3_crm.h" +#include "hinic3_lld.h" +#include "hinic3_mbox.h" +#include "hinic3_srv_nic.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_qp.h" +#include "roce_dfx.h" +#include "roce_cmd.h" +#include "rdma_comp.h" +#include "hmm_mr.h" +#include "roce_qp_post_send_extension.h" + +#define ROCE_MAX_WQES_COMPUTE (4 * K_UNIT - 1) +#define RDMA_MAX_SQ_DESC_SZ_COMPUTE 512 +#define ROCE_MAX_SQ_INLINE_DATA_SZ_COMPUTE 448 + +struct hinic3_uld_info *roce3_info_get(void); + +void roce3_service_init_pre(void); + +void roce3_service_init_ext(void); + +void roce3_lock_rdev(void); + +void roce3_unlock_rdev(void); + +int roce3_get_rdev_by_uld(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev, + struct hinic3_event_info *event); + +void roce3_init_dev_ext_handlers(struct roce3_device *rdev); + +int roce3_board_cfg_check(struct roce3_device *rdev); + +int roce3_init_dev_ext(struct roce3_device *rdev); + +void roce3_remove_clean_res_ext(struct roce3_device *rdev); + +int roce3_set_comm_event(const struct roce3_device *rdev, const struct hinic3_event_info *event); + +bool roce3_hca_is_present(const struct roce3_device *rdev); + +int roce3_mmap_ext(struct roce3_device *rdev, struct roce3_ucontext *ucontext, struct vm_area_struct *vma); + +int roce3_dfx_mem_alloc(struct roce3_device *rdev); + +void roce3_dfx_mem_free(struct roce3_device *rdev); + +int ib_copy_to_udata_ext(struct ib_udata *udata, struct roce3_alloc_ucontext_resp *resp); + +void *roce3_ucontext_alloc_ext(void); + +void roce3_resp_set_ext(struct roce3_device *rdev, struct roce3_alloc_ucontext_resp *resp); + +void *roce3_resp_alloc_ext(void); + +void roce3_ucontext_set_ext(struct roce3_device *rdev, struct roce3_ucontext *context); + +void *roce3_rdev_alloc_ext(void); + +void roce3_rdev_set_ext(struct roce3_device *rdev); + +void roce3_rdma_cap_ext(struct rdma_service_cap *rdma_cap); + +#endif /* ROCE_MAIN_EXTENSION_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/roce_mr_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_mr_extension.h new file mode 100644 index 000000000..7f8ffad04 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_mr_extension.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mr_extension.h + * Version : v1.0 + * Created : 2021/1/27 + * Last Modified : 2022/1/27 + * Description : The definition of RoCE MR module standard callback function prototypes, macros etc., + */ + +#ifndef ROCE_MR_EXTEND_H +#define ROCE_MR_EXTEND_H + +#include <rdma/ib_verbs.h> + +#include "hinic3_rdma.h" + +#include "roce.h" + +int roce3_check_alloc_mr_type(enum ib_mr_type mr_type); +enum rdma_mr_type roce3_get_mrtype(enum ib_mr_type ib_mr_type); + +#endif + diff --git a/drivers/infiniband/hw/hiroce3/include/roce_netdev_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_netdev_extension.h new file mode 100644 index 000000000..b393fd3e0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_netdev_extension.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_netdev_extension.h + * Version : v1.1 + * Created : 2021/10/18 + * Last Modified : 2022/1/26 + * Description : The definition of RoCE net devices realated extended function prototypes, macros etc,. + */ + +#ifndef ROCE_NETDEV_EXTENSION_H +#define ROCE_NETDEV_EXTENSION_H + +#include "roce_netdev.h" + +int roce3_add_real_device_mac(struct roce3_device *rdev, struct net_device *netdev); + +int roce3_add_vlan_device_mac(struct roce3_device *rdev, struct net_device *netdev); + +void roce3_del_real_device_mac(struct roce3_device *rdev); + +void roce3_del_vlan_device_mac(struct roce3_device *rdev, struct roce3_vlan_dev_list *old_list); + +void roce3_event_up_extend(struct roce3_device *rdev); + +#endif /* ROCE_NETDEV_EXTENSION_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/roce_qp_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_qp_extension.h new file mode 100644 index 000000000..921825e31 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_qp_extension.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_extension.h + * Version : v1.0 + * Created : 2021/12/20 + * Last Modified : 2021/12/20 + * Description : Define extended kernel QP realted function prototype. + */ + +#ifndef ROCE_QP_EXTENSION_H +#define ROCE_QP_EXTENSION_H + +#include <rdma/ib_verbs.h> + +#include "roce_qp.h" +#include "roce_qp_exp.h" + +int to_roce3_qp_type(enum ib_qp_type qp_type); + +bool roce3_check_qp_modify_ok(enum ib_qp_state cur_state, enum ib_qp_state next_state, enum ib_qp_type type, + enum ib_qp_attr_mask mask, enum rdma_link_layer ll); + +int roce3_create_qp_pre_ext(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr); + +int roce3_create_qp_user_pre_ext(struct ib_qp_init_attr *init_attr, struct roce3_qp *rqp, u32 *qpn); + +int roce3_create_qp_user_post_ext(struct ib_pd *ibpd, struct roce3_device *rdev, struct roce3_qp *rqp, + struct ib_qp_init_attr *init_attr); + +int roce3_qp_modify_cmd_ext(cqm_cmd_buf_s *cqm_cmd_inbuf, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr, + u32 optpar); + +bool roce3_need_qpn_lb1_consistent_srqn(const struct roce3_qp *rqp, const struct roce3_device *rdev, + const struct ib_qp_init_attr *init_attr); + +int roce3_is_qp_normal(struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr); + +void roce3_set_qp_dif_attr(struct roce3_qp *rqp, const struct ib_qp_init_attr *init_attr, + const struct roce3_device *rdev); + +int roce3_qp_modify_pre_extend(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata); + +#ifdef ROCE_EXTEND + +#define QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC 204800 // 200K + +#define ROCE_QP_VBS_FLAG (1U << 22) + +struct roce3_set_qp_ext_attr_cmd { + u32 qpn; + u32 attr_mask; +}; + +struct roce3_modify_qp_vbs_cmd { + u32 qpn; + u64 ci_record_addr; +}; + +struct roce3_vbs_qp { + cqm_qpc_mpt_s *vbs_sqpc_info; /* vbs private data */ + struct roce3_db db; /* to record ci_record_pa */ +}; + +long roce3_set_qp_ext_attr(struct roce3_device *rdev, void *buf); +long roce3_vbs_create_sqpc(struct roce3_device *rdev, void *buf); +#endif + +#endif /* ROCE_QP_EXTENSION_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/roce_qp_post_send_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_qp_post_send_extension.h new file mode 100644 index 000000000..08c04b2e4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_qp_post_send_extension.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_post_send_extend.h + * Version : v1.1 + * Created : 2021/8/20 + * Last Modified : 2021/9/22 + * Description : Define extended kernel post_send realted function prototype. + */ + +#ifndef ROCE_QP_POST_SEND_EXTEND_H +#define ROCE_QP_POST_SEND_EXTEND_H + +#include <rdma/ib_verbs.h> +#include "roce_qp.h" + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr); +#else +int roce3_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, struct ib_send_wr **bad_wr); +#endif + +#endif // ROCE_QP_POST_SEND_EXTEND_H diff --git a/drivers/infiniband/hw/hiroce3/include/roce_srq_extension.h b/drivers/infiniband/hw/hiroce3/include/roce_srq_extension.h new file mode 100644 index 000000000..7204ff7eb --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/roce_srq_extension.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq_extension.h + * Version : v1.0 + * Created : 2021/12/7 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE SRQ module standard callback function prototypes, macros etc., + */ + +#ifndef ROCE_SRQ_EXTENSION_H +#define ROCE_SRQ_EXTENSION_H + +#include "roce_srq.h" + +void roce3_srq_container_init(struct ib_srq_init_attr *init_attr, struct roce3_srq *rsrq, struct roce3_device *rdev); + +void roce3_create_user_srq_update_ext(u32 *cqn, u32 srqn); + +#endif /* ROCE_SRQ_EXTENSION_H */ diff --git a/drivers/infiniband/hw/hiroce3/mr/roce_mr.c b/drivers/infiniband/hw/hiroce3/mr/roce_mr.c new file mode 100755 index 000000000..335b85506 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/mr/roce_mr.c @@ -0,0 +1,1305 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mr.c + * Version : v2.0 + * Created : 2021/4/24 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE MR realted functions. + */ + +#include "roce_mr.h" +#include "roce_mr_extension.h" +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : get_key_from_index + Description : get_key_from_index + Input : u32 mpt_index + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static u32 get_key_from_index(u32 mpt_index) +{ + /* Algorithm of mr key is obtained by index shift calculation */ + return (mpt_index >> MR_KEY_RIGHT_SHIFT_OFS) | (mpt_index << MR_KEY_LEFT_SHIFT_OFS); +} + +/* **************************************************************************** + Prototype : convert_ib_access + Description : convert ib access to rdma comp access + Input : int access_flag + Output : None + + 1.Date : 2015/7/16 + Modification : Created function + +**************************************************************************** */ +static u32 convert_ib_access(int access_flag) +{ + u32 u_access_flag = (u32)access_flag; + u32 access; + + access = (u32)((((u_access_flag & IB_ACCESS_REMOTE_ATOMIC) != 0) ? RDMA_IB_ACCESS_REMOTE_ATOMIC : 0) | + (((u_access_flag & IB_ACCESS_REMOTE_WRITE) != 0) ? RDMA_IB_ACCESS_REMOTE_WRITE : 0) | + (((u_access_flag & IB_ACCESS_REMOTE_READ) != 0) ? RDMA_IB_ACCESS_REMOTE_READ : 0) | + (((u_access_flag & IB_ACCESS_LOCAL_WRITE) != 0) ? RDMA_IB_ACCESS_LOCAL_WRITE : 0) | + (((u_access_flag & IB_ACCESS_MW_BIND) != 0) ? RDMA_IB_ACCESS_MW_BIND : 0) | + (((u_access_flag & IB_ZERO_BASED) != 0) ? RDMA_IB_ACCESS_ZERO_BASED : 0)); + + return access; +} + +/* **************************************************************************** + Prototype : check_ib_access + Description : check remote access without local write + Input : int access_flag + Output : None + + 1.Date : 2017/11/18 + Modification : Created function + +**************************************************************************** */ +static int check_ib_access(int access_flag) +{ + /* + * Local write permission is required if remote write or + * remote atomic permission is also requested. + */ + + if (((((u32)access_flag) & (IB_ACCESS_REMOTE_ATOMIC | IB_ACCESS_REMOTE_WRITE)) != 0) && + ((((u32)access_flag) & IB_ACCESS_LOCAL_WRITE) == 0)) { + return -EINVAL; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_alloc_tpt + Description : alloc mpt and mtt + Input : struct roce3_device *rdev + struct rdma_mr *mr + u32 npages + u32 page_shift + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +int roce3_alloc_tpt(struct roce3_device *rdev, struct rdma_mr *mr, u32 npages, u32 page_shift) +{ + int ret = 0; + + ret = hmm_rdma_mpt_alloc(rdev->hwdev, &mr->mpt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mpt, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + return ret; + } + + mr->enabled = RDMA_MPT_EN_SW; + + /* npages = 0 is a legal case, when npages = 0 or npages = 1, MTT does not need to do address translation */ + ret = hmm_rdma_mtt_alloc(rdev->hwdev, npages, page_shift, &mr->mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mtt, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + goto err_alloc_mtt; + } + + return 0; + +err_alloc_mtt: + hmm_rdma_mpt_free(rdev->hwdev, &mr->mpt); + mr->enabled = RDMA_MPT_DISABLED; + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_free_tpt + Description : free mpt and mtt + Input : struct roce3_device *rdev + struct rdma_mr *mr + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +void roce3_free_tpt(struct roce3_device *rdev, struct rdma_mr *mr) +{ + hmm_rdma_mtt_free(rdev->hwdev, &mr->mtt, SERVICE_T_ROCE); + + hmm_rdma_mpt_free(rdev->hwdev, &mr->mpt); + + mr->enabled = RDMA_MPT_DISABLED; +} + +/* **************************************************************************** + Prototype : roce3_set_rdma_mr + Description : set the member of rdma_mr + Input : struct rdma_mr *mr + enum rdma_mr_type mr_type + u32 pdn + u64 iova + u64 size + u32 access + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +void roce3_set_rdma_mr(struct rdma_mr *mr, enum rdma_mr_type mr_type, u32 pdn, u64 iova, u64 size, u32 access) +{ + mr->iova = iova; + mr->size = size; + mr->pdn = pdn; + mr->access = convert_ib_access((int)access); /* Convert ib permissions to rdma component permissions */ + mr->key = get_key_from_index(mr->mpt.mpt_index); /* Convert from mpt index to key */ + mr->mr_type = mr_type; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +static void roce3_set_rdma_fmr(struct rdma_fmr *fmr, struct ib_fmr_attr *fmr_attr, u32 pdn, u32 access) +{ + roce3_set_rdma_mr(&fmr->mr, RDMA_FMR, pdn, 0ULL, 0ULL, access); + + fmr->max_maps = (u32)fmr_attr->max_maps; + fmr->max_pages = (u32)fmr_attr->max_pages; + fmr->page_shift = fmr_attr->page_shift; + fmr->maps = 0; +} +#endif + +/* **************************************************************************** + Prototype : roce3_set_rdma_mw + Description : set the member of rdma_mw + Input : struct rdma_mw *mw + u32 pdn + enum ib_mw_type type + Output : None + + 1.Date : 2016/6/25 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_rdma_mw(struct rdma_mw *mw, u32 pdn, enum ib_mw_type type) +{ + mw->enabled = RDMA_MPT_EN_SW; + mw->pdn = pdn; + mw->key = get_key_from_index(mw->mpt.mpt_index); + + if (type == IB_MW_TYPE_1) { + mw->type = RDMA_MW_TYPE_1; + } else { + mw->type = RDMA_MW_TYPE_2; + } +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +static int roce3_check_fmr_attr(struct roce3_device *rdev, const struct ib_fmr_attr *fmr_attr) +{ + int max_fmr_maps = 0; /* Maximum number of mappings, obtained from configuration management */ + u32 page_size_cap = 0; /* The page size supported by the current function, each bit indicates support for one */ + + /* Get page_size_cap through roce3_dev */ + page_size_cap = rdev->rdma_cap.page_size_cap; + max_fmr_maps = (int)rdev->rdma_cap.max_fmr_maps; + + if (fmr_attr->max_maps > max_fmr_maps) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Max_maps of fmr_attr exceed max_fmr_maps, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + if (((u64)((u32)fmr_attr->max_pages) * sizeof(u64)) > PAGE_SIZE) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Max_pages of fmr_attr exceed page num which can record in one page, func_id(%d)\n", + __func__, rdev->glb_func_id); + return -EINVAL; + } + + /* Check if page_shift is supported */ + if (((1UL << fmr_attr->page_shift) & page_size_cap) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Page_shift of fmr_attr not supported, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} +#endif + +/* **************************************************************************** + Prototype : roce3_get_dma_mr + Description : register DMA_MR + Input : struct ib_pd *ibpd + int access + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +struct ib_mr *roce3_get_dma_mr(struct ib_pd *ibpd, int access) +{ + int ret = 0; + struct roce3_mr *mr = NULL; + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + if ((ibpd == NULL) || (check_ib_access(access) != 0)) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Invalid Param.p1:%d\n", __func__, access); + goto err_out; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + ret = -EPERM; + goto err_out; + } + + mr = (struct roce3_mr *)kzalloc(sizeof *mr, GFP_KERNEL); + if (mr == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for dma mr, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + + mr->rdmamr.mtt.mtt_type = MTT_DMTT_TYPE; + ret = roce3_alloc_tpt(rdev, &mr->rdmamr, 0, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mpt and mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_alloc_tpt; + } + + /* Set the content in rdma_mr */ + roce3_set_rdma_mr(&mr->rdmamr, RDMA_DMA_MR, pd->pdn, 0ULL, ROCE_DMA_MR_SIZE, (u32)access); + + ret = hmm_rdma_enable_mr_mpt(rdev->hwdev, &(mr->rdmamr), HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to enable mpt of DMA mr, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_enable_mpt; + } + + mr->ibmr.lkey = mr->rdmamr.key; + mr->ibmr.rkey = mr->rdmamr.key; + + return &mr->ibmr; + +err_enable_mpt: + roce3_free_tpt(rdev, &mr->rdmamr); + +err_alloc_tpt: + kfree(mr); + +err_out: + return (struct ib_mr *)ERR_PTR((long)ret); +} + +static int roce3_alloc_priv_pages(struct ib_device *ibdev, struct roce3_mr *rmr, u32 max_pages) +{ + int ret; + +#ifndef __PC_LINT__ + rmr->page_map_size = roundup(max_pages * sizeof(u64), ROCE3_MR_PAGES_ALIGN); +#endif + rmr->pages = (__be64 *)(void *)(uintptr_t)get_zeroed_page(GFP_KERNEL); + if (rmr->pages == NULL) { + pr_err("[ROCE] %s: Failed to alloc rmr->pages\n", __func__); + ret = -ENOMEM; + goto err_out; + } + + rmr->page_map = dma_map_single(ibdev->dev.parent, rmr->pages, rmr->page_map_size, DMA_TO_DEVICE); + if (dma_mapping_error(ibdev->dev.parent, rmr->page_map) != 0) { + pr_err("[ROCE] %s: Failed to do dma mapping\n", __func__); + ret = -ENOMEM; + goto err_free_pages; + } + + return 0; + +err_free_pages: + free_page((unsigned long)(uintptr_t)(void *)rmr->pages); + +err_out: + return ret; +} + +static void roce3_free_priv_pages(struct roce3_mr *rmr) +{ + struct ib_device *ib_dev = rmr->ibmr.device; + + if (rmr->pages) { + ib_dev = rmr->ibmr.device; + dma_unmap_single(ib_dev->dev.parent, rmr->page_map, rmr->page_map_size, DMA_TO_DEVICE); + free_page((unsigned long)(uintptr_t)(void *)rmr->pages); + rmr->pages = NULL; + } +} + +static int roce3_alloc_mr_param_validate(const struct ib_pd *ibpd, enum ib_mr_type mr_type, u32 max_num_sg) +{ + int ret = 0; + + if (ibpd == NULL) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Ibpd is null\n", __func__); + goto err_out; + } + + /*lint -e746*/ + ret = roce3_check_alloc_mr_type(mr_type); + /*lint +e746*/ + if (ret != 0) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: mr_type is invalid \n", __func__); + goto err_out; + } + + if (max_num_sg >= ROCE_FRMR_MAX_PAGES) { + pr_err("[ROCE] %s: Invalid max_num_sg(%d)\n", __func__, max_num_sg); + ret = -EINVAL; + goto err_out; + } + + return 0; + +err_out: + return ret; +} + +static int roce3_alloc_mr_param_check(struct roce3_device *rdev, struct roce3_mr **mr, u32 max_num_sg) +{ + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + *mr = (struct roce3_mr *)kzalloc(sizeof(struct roce3_mr), GFP_KERNEL); + if ((*mr) == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mr memory, func(%d)\n", __func__, rdev->glb_func_id); + return -ENOMEM; + } + + (*mr)->max_pages = max_num_sg; + return 0; +} +/* **************************************************************************** + Prototype : roce3_alloc_mr + Description : register DMA_MR + Input : struct ib_pd *ibpd + enum ib_mr_type mr_type + u32 max_num_sg + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +struct ib_mr *roce3_alloc_mr(struct ib_pd *ibpd, enum ib_mr_type mr_type, u32 max_num_sg) +{ + int ret = 0; + struct roce3_mr *mr = NULL; + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_alloc_mr_param_validate(ibpd, mr_type, max_num_sg); + if (ret != 0) { + goto err_out; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + + ret = roce3_alloc_mr_param_check(rdev, &mr, max_num_sg); + if (ret != 0) { + goto err_out; + } + + mr->rdmamr.mtt.mtt_type = MTT_DMTT_TYPE; + ret = roce3_alloc_tpt(rdev, &mr->rdmamr, max_num_sg, 0); // alloc mptc and mtt + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc tpt, func(%d)\n", __func__, rdev->glb_func_id); + goto err_alloc_tpt; + } + + ret = roce3_alloc_priv_pages(ibpd->device, mr, max_num_sg); // alloc memory to store pa + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to alloc memory, func(%u)\n", __func__, rdev->glb_func_id); + goto err_alloc_priv_pages; + } + + /*lint -e746*/ + roce3_set_rdma_mr(&mr->rdmamr, RDMA_FRMR, pd->pdn, 0ULL, 0, 0); + /*lint +e746*/ + + ret = hmm_rdma_enable_mr_mpt(rdev->hwdev, &(mr->rdmamr), HINIC3_CHANNEL_ROCE); // send to chip by cmdq + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to enable mpt, func(%d)\n", __func__, rdev->glb_func_id); + goto err_enale_mpt; + } + + mr->ibmr.lkey = mr->rdmamr.key; + mr->ibmr.rkey = mr->rdmamr.key; + + return &mr->ibmr; + +err_enale_mpt: + roce3_free_priv_pages(mr); + +err_alloc_priv_pages: + roce3_free_tpt(rdev, &mr->rdmamr); + +err_alloc_tpt: + kfree(mr); + +err_out: + return (struct ib_mr *)ERR_PTR((long)ret); +} + +static int roce3_set_page(struct ib_mr *ibmr, u64 addr) +{ + struct roce3_mr *rmr = NULL; + + if (ibmr == NULL) { + pr_err("[ROCE] %s: Ibmr is null\n", __func__); + return -EINVAL; + } + + rmr = to_roce3_mr(ibmr); + if (ROCE_UNLIKELY(rmr->npages >= rmr->max_pages)) { + pr_err("[ROCE] %s: Invalid npages(0x%x), can't set page\n", __func__, rmr->npages); + return -ENOMEM; + } + + rmr->pages[rmr->npages] = cpu_to_be64(addr | 0x1); + rmr->npages++; + + return 0; +} + +int roce3_map_kernel_frmr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, unsigned int *sg_offset) +{ + int ret; + struct roce3_mr *rmr = NULL; + + /* sg_offset can be null */ + if ((ibmr == NULL) || (sg == NULL)) { + pr_err("[ROCE] %s: Ibmr or sg is null\n", __func__); + return -EINVAL; + } + + rmr = to_roce3_mr(ibmr); + rmr->npages = 0; + + if (ROCE_UNLIKELY(((u32)sg_nents) >= rmr->max_pages)) { + pr_err("[ROCE] %s: Invalid sg_nents(0x%x), ,max(0x%x)\n", __func__, sg_nents, rmr->max_pages); + return -EINVAL; + } + + ib_dma_sync_single_for_cpu(ibmr->device, rmr->page_map, rmr->page_map_size, DMA_TO_DEVICE); + + ret = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, roce3_set_page); + + ib_dma_sync_single_for_device(ibmr->device, rmr->page_map, rmr->page_map_size, DMA_TO_DEVICE); + + return ret; +} + +static int roce3_umem_write_mtt_check(const struct roce3_device *rdev, const struct rdma_mtt *mtt, + const struct ib_umem *umem) +{ + if ((rdev == NULL) || (mtt == NULL) || (umem == NULL)) { + pr_err("[ROCE, ERR] %s: Rdev or mtt or umem is null\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int roce3_umem_write_mtt_update(struct roce3_device *rdev, struct rdma_mtt *mtt, struct ib_umem *umem, + u64 *page_list) +{ + int ret = 0; + int i = 0; + u32 j = 0; + u32 pages_in_chunk = 0; /* The number of pages of a single memory block in umem_chunk */ + u32 npages = 0; /* The number of recorded pages */ + u32 start_index = 0; /* page need to be written to mtt */ + struct scatterlist *sg = NULL; + u64 page_size = BIT(mtt->buf_page_shift); + u64 page_mask = ~(page_size - 1); + u64 dma_addr; + + for_each_sgtable_dma_sg(&umem->sgt_append.sgt, sg, i) { + /* Calculate the number of pages in a memory block, the page size is 1 << page_shift */ + dma_addr = sg_dma_address(sg) & page_mask; + pages_in_chunk = DIV_ROUND_UP(sg_dma_len(sg), page_size); + for (j = 0; j < pages_in_chunk; ++j) { + page_list[npages] = dma_addr + (page_size * j); + npages++; + + /* The size of the memory pointed to by page_list is one page, which can store up to PAGE_SIZE / sizeof(u64) + pas. After a page is full, mtt needs to be written, else continue */ + if (npages != PAGE_SIZE / sizeof(u64)) { + continue; + } + + ret = hmm_rdma_write_mtt(rdev->hwdev, mtt, start_index, npages, page_list, SERVICE_T_ROCE); + if (ret) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ret; + } + start_index += npages; + npages = 0; + } + } + + if (npages != 0) { + ret = hmm_rdma_write_mtt(rdev->hwdev, mtt, start_index, npages, page_list, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt, ret(%d), start_index(%u), func_id(%hu)\n", + __func__, ret, start_index, rdev->glb_func_id); + } + } + + return ret; +} + +int roce3_umem_write_mtt(struct roce3_device *rdev, struct rdma_mtt *mtt, struct ib_umem *umem) +{ + int ret = 0; + u64 *page_list = NULL; /* page_list to write to mtt */ + + ret = roce3_umem_write_mtt_check(rdev, mtt, umem); + if (ret != 0) { + return ret; + } + + page_list = (u64 *)kzalloc(PAGE_SIZE, GFP_KERNEL); + if (page_list == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for page list, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + ret = roce3_umem_write_mtt_update(rdev, mtt, umem, page_list); + kfree(page_list); + return ret; +} + +/* **************************************************************************** + Prototype : roce3_buf_write_mtt + Description : roce3_buf_write_mtt + Input : struct roce3_device *rdev + struct rdma_mtt *mtt + struct tag_cqm_buf *buf + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +int roce3_buf_write_mtt(struct roce3_device *rdev, struct rdma_mtt *mtt, struct tag_cqm_buf *buf) +{ + u64 *page_list = NULL; + int ret = 0; + u32 i = 0; + + if ((rdev == NULL) || (mtt == NULL) || (buf == NULL)) { + pr_err("[ROCE, ERR] %s: Rdev or mtt or buf is null\n", __func__); + return (-EINVAL); + } + + page_list = (u64 *)kzalloc(buf->buf_number * sizeof *page_list, GFP_KERNEL); + if (page_list == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for page list, func_id(%d)\n", __func__, + rdev->glb_func_id); + return (-ENOMEM); + } + + /* Each buf is written to MTT as a page, buf_size is 2^n times PAGE_SIZE */ + for (i = 0; i < buf->buf_number; ++i) { + page_list[i] = buf->buf_list[i].pa; + } + + ret = hmm_rdma_write_mtt(rdev->hwdev, mtt, 0, buf->buf_number, page_list, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt, func_id(%d)\n", __func__, rdev->glb_func_id); + } + + kfree(page_list); + + return ret; +} + +int roce3_user_mr_reg(struct roce3_device *rdev, struct roce3_mr *mr, u32 pdn, u64 virt_addr, + u64 length, int access) +{ + int ret = 0; + u32 npages = 0; + u32 page_shift = PAGE_SHIFT; + struct hinic3_hwdev *hwdev = (struct hinic3_hwdev *)rdev->hwdev; + + if (hwdev == NULL) { + pr_err("[HMM, ERR] %s(%d): hwdev is null\n", __func__, __LINE__); + return 0; + } + + mr->rdmamr.mtt.mtt_type = MTT_DMTT_TYPE; + npages = (u32)ib_umem_num_pages(mr->umem); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +#ifdef CONFIG_CENTRALIZED_STORAGE + if (mr->umem->is_umm_mem) { + page_shift = PAGE_SHIFT_2M; + npages = ib_umem_num_dma_blocks(mr->umem, BIT(page_shift)); + } +#endif +#else + page_shift = (u32)(mr->umem->page_shift); +#endif + ret = roce3_alloc_tpt(rdev, &mr->rdmamr, npages, page_shift); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[ROCE, ERR] %s(%d): Failed to alloc mpt and mtt, func_id(%hu)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_alloc_tpt; + } + + roce3_set_rdma_mr(&mr->rdmamr, RDMA_USER_MR, pdn, virt_addr, length, (u32)access); + + ret = roce3_umem_write_mtt(rdev, &mr->rdmamr.mtt, mr->umem); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[ROCE, ERR] %s(%d): Failed to write mtt, func_id(%hu)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_write_mtt; + } + + ret = hmm_rdma_enable_mr_mpt(hwdev, &mr->rdmamr, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[ROCE, ERR] %s(%d): Failed to enable mpt of user mr, func_id(%hu)\n", + __func__, __LINE__, hinic3_global_func_id(hwdev)); + goto err_write_mtt; + } + + return 0; + +err_write_mtt: + roce3_free_tpt(rdev, &mr->rdmamr); + +err_alloc_tpt: + return ret; +} + +static int roce3_check_mr_param(struct ib_pd *ibpd) +{ + struct roce3_device *rdev = NULL; + + if (ibpd == NULL) { + pr_err("[ROCE, ERR] %s: Ibpd is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibpd->device); + if (roce3_hca_is_present(rdev) == 0) { + pr_err("[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, rdev->glb_func_id); + return -EPERM; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_reg_user_mr + Description : register MR for user + Input : struct ib_pd *ibpd + u64 start + u64 length + u64 virt_addr + int access + struct ib_udata *udata + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +struct ib_mr *roce3_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 length, u64 virt_addr, int access, + struct ib_udata *udata) +{ + int ret; + struct roce3_mr *mr = NULL; + struct roce3_device *rdev = NULL; + struct roce3_pd *pd; + + ret = roce3_check_mr_param(ibpd); + if (ret != 0) { + goto err_out; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + + mr = (struct roce3_mr *)kzalloc(sizeof(*mr), GFP_KERNEL); + if (mr == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for roce mr, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + mr->umem = ib_umem_get(&rdev->ib_dev, start, (size_t)length, access); +#elif defined(OFED_MLNX_5_8) + mr->umem = ib_umem_get(udata, start, (size_t)length, access); +#else + mr->umem = ib_umem_get(ibpd->uobject->context, start, (size_t)length, access, 0); +#endif + + if (IS_ERR(mr->umem)) { + ret = (int)PTR_ERR(mr->umem); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get ib umem, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_get_umem; + } + + ret = roce3_user_mr_reg(rdev, mr, pd->pdn, virt_addr, length, access); + if (ret != 0) { + goto err_mr_update; + } + + mr->ibmr.lkey = mr->rdmamr.key; + mr->ibmr.rkey = mr->rdmamr.key; + + return &mr->ibmr; + +err_mr_update: + ib_umem_release(mr->umem); + +err_get_umem: + kfree(mr); + +err_out: + return (struct ib_mr *)ERR_PTR((long)ret); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata) +#else +int roce3_dereg_mr(struct ib_mr *ibmr) +#endif +{ + int ret = 0; + struct roce3_mr *mr = NULL; + struct roce3_device *rdev = NULL; + + if (ibmr == NULL) { + pr_err("[ROCE, ERR] %s: Ibmr is null\n", __func__); + return -EINVAL; + } + + mr = to_roce3_mr(ibmr); + rdev = to_roce3_dev(ibmr->device); + + roce3_free_priv_pages(mr); + + ret = hmm_rdma_disable_mr_mpt(rdev->hwdev, &mr->rdmamr, SERVICE_T_ROCE, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to disable mpt of mr, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Mr may has mw bind on it, mr_key(%#x), func_id(%d)\n", __func__, + mr->rdmamr.key, rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return ret; + } + + roce3_free_tpt(rdev, &mr->rdmamr); + + if (mr->umem) { + ib_umem_release(mr->umem); + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + kfree(mr); +#endif + + return 0; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +static int roce3_alloc_fmr_update(struct roce3_device *rdev, struct roce3_pd *pd, int access, + struct ib_fmr_attr *fmr_attr, struct roce3_fmr *fmr) +{ + int ret = 0; + u32 max_pages = 0; + u32 page_shift = fmr_attr->page_shift; + + max_pages = (u32)((fmr_attr->max_pages > 1) ? fmr_attr->max_pages : ROCE3_MIN_PAGE); + fmr->rdmafmr.mr.mtt.mtt_type = MTT_DMTT_TYPE; + ret = roce3_alloc_tpt(rdev, &fmr->rdmafmr.mr, max_pages, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mpt and mtt, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + goto err_alloc_tpt; + } + + roce3_set_rdma_fmr(&fmr->rdmafmr, fmr_attr, pd->pdn, (u32)access); + + ret = hmm_rdma_enable_mr_mpt(rdev->hwdev, &fmr->rdmafmr.mr, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to enable mpt of fmr, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + goto err_enable_mpt; + } + + return 0; + +err_enable_mpt: + roce3_free_tpt(rdev, &(fmr->rdmafmr.mr)); + +err_alloc_tpt: + kfree(fmr); + + return ret; +} + +static int roce3_alloc_fmr_param_check(const struct ib_pd *ibpd, int access, const struct ib_fmr_attr *fmr_attr) +{ + int ret = 0; + + if ((ibpd == NULL) || (fmr_attr == NULL)) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Ibpd or fmr_attr is null\n", __func__); + } + + ret = check_ib_access(access); + if (ret != 0) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Set remote access without local write\n", __func__); + } + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_alloc_fmr + Description : alloc fmr and it only can be used after mapping + Input : struct ib_pd *ibpd + int access + struct ib_fmr_attr *fmr_attr + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +struct ib_fmr *roce3_alloc_fmr(struct ib_pd *ibpd, int access, struct ib_fmr_attr *fmr_attr) +{ + int ret = 0; + struct roce3_fmr *fmr = NULL; + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_alloc_fmr_param_check(ibpd, access, fmr_attr); + if (ret != 0) { + goto err_out; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + ret = -EPERM; + goto err_out; + } + + ret = roce3_check_fmr_attr(rdev, fmr_attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Fmr_attr is invalid, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + goto err_out; + } + + fmr = (struct roce3_fmr *)kzalloc(sizeof *fmr, GFP_KERNEL); + if (fmr == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for roce fmr, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + + ret = roce3_alloc_fmr_update(rdev, pd, access, fmr_attr, fmr); + if (ret != 0) { + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + goto err_out; + } + + fmr->ibfmr.lkey = fmr->rdmafmr.mr.key; + fmr->ibfmr.rkey = fmr->rdmafmr.mr.key; + + fmr->sig.sig_status_checked = true; + + return &fmr->ibfmr; + +err_out: + return (struct ib_fmr *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : roce3_map_phys_fmr + Description : map fmr and later the fmr can be used when succeed + Input : struct ib_fmr *ibfmr + u64 *page_list + int npages + u64 iova + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +int roce3_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, int npages, u64 iova) +{ + int ret = 0; + struct roce3_fmr *fmr = NULL; + struct roce3_device *rdev = NULL; + + if ((ibfmr == NULL) || (page_list == NULL)) { + pr_err("[ROCE, ERR] %s: Ibfmr or page_list is null\n", __func__); + return -EINVAL; + } + + if (npages < 1) { + pr_err("[ROCE, ERR] %s: Page list len is invalid, npages(%d)\n", __func__, npages); + return -EINVAL; + } + + fmr = to_roce3_fmr(ibfmr); + rdev = to_roce3_dev(ibfmr->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = roce3_rdma_map_phys_fmr(rdev->hwdev, &fmr->rdmafmr, page_list, npages, iova, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to map phys fmr, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return ret; + } + + ibfmr->lkey = ibfmr->rkey = fmr->rdmafmr.mr.key; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_unmap_fmr + Description : umap a fmr list and flush the cache of MPT and MTT in this function + Input : struct list_head *fmr_list + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +int roce3_unmap_fmr(struct list_head *fmr_list) +{ + int ret = 0; + struct ib_fmr *ibfmr = NULL; + struct roce3_fmr *fmr = NULL; + struct roce3_device *rdev = NULL; + + if (fmr_list == NULL) { + pr_err("[ROCE, ERR] %s: Fmr_list is null\n", __func__); + return -EINVAL; + } + + /* Check if the fmr chain corresponds to the same dev */ + /*lint -e826*/ + list_for_each_entry(ibfmr, fmr_list, list) + /*lint +e826*/ + { + if (rdev && (to_roce3_dev(ibfmr->device) != rdev)) { + pr_err("[ROCE, ERR] %s: Fmr in list belong to different roce dev\n", __func__); + return -EINVAL; + } + rdev = to_roce3_dev(ibfmr->device); + } + + /* No ibfmr on chain */ + if (rdev == NULL) { + return 0; + } + + /*lint -e826*/ + list_for_each_entry(ibfmr, fmr_list, list) + /*lint +e826*/ + { + fmr = to_roce3_fmr(ibfmr); + + ret = roce3_rdma_unmap_fmr(rdev->hwdev, &fmr->rdmafmr, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to unmap fmr, func_id(%d)\n", __func__, rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return ret; + } + + ibfmr->lkey = ibfmr->rkey = fmr->rdmafmr.mr.key; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_dealloc_fmr + Description : dealloc fmr and release its resource + Input : struct ib_fmr *ibfmr + Output : None + + 1.Date : 2015/4/24 + Modification : Created function + +**************************************************************************** */ +int roce3_dealloc_fmr(struct ib_fmr *ibfmr) +{ + int ret = 0; + struct roce3_fmr *fmr = NULL; + struct roce3_device *rdev = NULL; + + if (ibfmr == NULL) { + pr_err("[ROCE, ERR] %s: Ibfmr is null\n", __func__); + return -EINVAL; + } + + fmr = to_roce3_fmr(ibfmr); + rdev = to_roce3_dev(ibfmr->device); + if (fmr->rdmafmr.maps != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Fmr is still in use, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EBUSY; + } + + ret = hmm_rdma_disable_mr_mpt(rdev->hwdev, &fmr->rdmafmr.mr, SERVICE_T_ROCE, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to disable mpt of fmr, func_id(%d)\n", __func__, + rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return ret; + } + + roce3_free_tpt(rdev, &(fmr->rdmafmr.mr)); + + kfree(fmr); + + return 0; +} +#endif + +static void roce3_err_enable_mpt_handler(void *hwdev, struct roce3_mw *mw) +{ + hmm_rdma_mpt_free(hwdev, &mw->rdmamw.mpt); + mw->rdmamw.enabled = RDMA_MPT_DISABLED; + return; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata) +{ + int ret; + struct roce3_mw *mw = to_roce3_mw(ibmw); + struct roce3_pd *pd = to_roce3_pd(ibmw->pd); + struct roce3_device *rdev = to_roce3_dev(ibmw->device); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = hmm_rdma_mpt_alloc(rdev->hwdev, &mw->rdmamw.mpt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mpt, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err; + } + + roce3_set_rdma_mw(&mw->rdmamw, pd->pdn, ibmw->type); + ret = roce3_rdma_enable_mw_mpt(rdev->hwdev, &mw->rdmamw, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to enable mpt of mw, func_id(%hu)\n", __func__, + rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + goto err_enable_mpt; + } + + mw->ibmw.rkey = mw->rdmamw.key; + return 0; +err_enable_mpt: + roce3_err_enable_mpt_handler(rdev->hwdev, mw); +err: + return ret; +} +#else +struct ib_mw *roce3_alloc_mw(struct ib_pd *ibpd, enum ib_mw_type type, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_mw *mw = NULL; + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + if (ibpd == NULL) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Ibpd is null\n", __func__); + goto err_out; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + ret = -EPERM; + goto err_out; + } + + mw = (struct roce3_mw *)kzalloc(sizeof *mw, GFP_KERNEL); + if (mw == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for roce mw, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + + ret = hmm_rdma_mpt_alloc(rdev->hwdev, &mw->rdmamw.mpt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc mpt, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_alloc_mpt; + } + + roce3_set_rdma_mw(&mw->rdmamw, pd->pdn, type); + + ret = roce3_rdma_enable_mw_mpt(rdev->hwdev, &mw->rdmamw, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to enable mpt of mw, func_id(%hu)\n", __func__, + rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + goto err_enable_mpt; + } + + mw->ibmw.rkey = mw->rdmamw.key; + + return &mw->ibmw; + +err_enable_mpt: + roce3_err_enable_mpt_handler(rdev->hwdev, mw); + +err_alloc_mpt: + kfree(mw); + +err_out: + return (struct ib_mw *)ERR_PTR((long)ret); +} +#endif + +int roce3_dealloc_mw(struct ib_mw *ibmw) +{ + int ret = 0; + struct roce3_mw *mw = NULL; + struct roce3_device *rdev = NULL; + + if (ibmw == NULL) { + pr_err("[ROCE, ERR] %s: Ibmw is null\n", __func__); + return -EINVAL; + } + + mw = to_roce3_mw(ibmw); + rdev = to_roce3_dev(ibmw->device); + ret = roce3_rdma_disable_mw_mpt(rdev->hwdev, &mw->rdmamw, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to disable mpt of mw, func_id(%d)\n", __func__, + rdev->glb_func_id); + if (ret == (-RDMA_CMDQ_TIMEOUT)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return ret; + } + + hmm_rdma_mpt_free(rdev->hwdev, &mw->rdmamw.mpt); + + mw->rdmamw.enabled = RDMA_MPT_DISABLED; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + kfree(mw); +#endif + + return 0; +} + +int roce3_check_mr_status(struct ib_mr *ibmr, u32 check_mask, struct ib_mr_status *mr_status) +{ + int ret = 0; + struct roce3_mr *mr = NULL; + + if ((ibmr == NULL) || (mr_status == NULL)) { + pr_err("[ROCE, ERR] ibmr or mr_status is NULL ptr. \n"); + return -EINVAL; + } + + mr = to_roce3_mr(ibmr); + if ((check_mask & (~IB_MR_CHECK_SIG_STATUS)) != 0) { + pr_err("[ROCE, ERR] check_mask(%#x) invalid\n", check_mask); + return -EINVAL; + } + + if (!mr->signature_en) { + pr_err("[ROCE, ERR] mr not configure dif info\n"); + ret = -EINVAL; + return ret; + } + + mr->sig.sig_status_checked = true; + mr_status->fail_status = 0; + + /* If err does not exist, return 0 */ + if (!mr->sig.sig_err_exists) { + return 0; + } + + memcpy((void *)&mr_status->sig_err, (void *)&mr->sig.sig_err_item, + sizeof(struct ib_sig_err)); + mr->sig.sig_err_exists = false; + mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS; + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/mr/roce_mr.h b/drivers/infiniband/hw/hiroce3/mr/roce_mr.h new file mode 100644 index 000000000..dc6c39ac2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/mr/roce_mr.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mr.h + * Version : v2.0 + * Created : 2021/4/24 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE MR realted functions. + */ + +#ifndef ROCE_MR_H +#define ROCE_MR_H + +#include <rdma/ib_verbs.h> +#include <rdma/ib_umem.h> +#include <linux/pci.h> +#include <linux/dma-mapping.h> +#include <linux/vmalloc.h> + +#include "hinic3_rdma.h" + +#include "roce.h" +#include "roce_compat.h" +#include "roce_pd.h" +#include "roce_user.h" + +#include "hmm_mr.h" +#include "hmm_comp.h" +#include "hinic3_hmm.h" + +#define ROCE3_MR_DEFAULT_ACCESS \ + (IB_ACCESS_REMOTE_READ | IB_ACCESS_REMOTE_WRITE | IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_ATOMIC) + +#define ROCE3_MR_PAGES_ALIGN 64 +#define ROCE3_MIN_PAGE 2 + +#define FRMR_PAGE_SIZE 4096 + +struct roce3_sig_ctx { + struct ib_sig_attrs sig_attrs; /* recorded when submitting WR */ + struct ib_sig_err sig_err_item; /* Get information configuration from CQE when polling CQE */ + bool sig_status_checked; /* Indicates whether the status is checked */ + bool sig_err_exists; /* Indicates if an error exists */ + u32 sig_err_count; /* Count the number of wrong CQEs */ +}; + +struct roce3_mr { + struct ib_mr ibmr; /* mr structure provided by ofed */ + struct ib_umem *umem; /* Maintain the structure where the user-mode allocated buffer */ + struct rdma_mr rdmamr; /* mr structure provided by rdma component */ + struct roce3_sig_ctx sig; /* Record signature related information */ + bool signature_en; /* Whether the logo contains signature information */ + __be64 *pages; + u32 npages; + u32 max_pages; + size_t page_map_size; + dma_addr_t page_map; +}; + +struct roce3_mw { + struct ib_mw ibmw; /* mw structure provided by ofed */ + struct rdma_mw rdmamw; /* mw structure provided by rdma component */ +}; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +struct roce3_fmr { + struct ib_fmr ibfmr; /* fmr structure provided by ofed */ + struct rdma_fmr rdmafmr; /* The fmr structure provided by the rdma component */ + struct roce3_sig_ctx sig; /* Record signature related information */ + bool signature_en; /* Whether the logo contains signature information */ +}; + +/* through ibfmroce3_e_fmr */ +static inline struct roce3_fmr *to_roce3_fmr(const struct ib_fmr *ibfmr) +{ + return container_of(ibfmr, struct roce3_fmr, ibfmr); +} +#endif + +/* through ibmroce3_e_mr */ +static inline struct roce3_mr *to_roce3_mr(const struct ib_mr *ibmr) +{ + return container_of(ibmr, struct roce3_mr, ibmr); +} + +/* through ibmroce3_e_mw */ +static inline struct roce3_mw *to_roce3_mw(const struct ib_mw *ibmw) +{ + return container_of(ibmw, struct roce3_mw, ibmw); +} + +/* through rdmam find roce3_mr */ +static inline struct roce3_mr *rdma_mr_to_roce3_mr(const struct rdma_mr *rdmamr) +{ + return container_of(rdmamr, struct roce3_mr, rdmamr); +} + +int roce3_alloc_tpt(struct roce3_device *rdev, struct rdma_mr *mr, u32 npages, u32 page_shift); +void roce3_free_tpt(struct roce3_device *rdev, struct rdma_mr *mr); +void roce3_set_rdma_mr(struct rdma_mr *mr, enum rdma_mr_type mr_type, u32 pdn, u64 iova, u64 size, u32 access); + +int roce3_user_mr_reg(struct roce3_device *rdev, struct roce3_mr *mr, u32 pdn, u64 virt_addr, + u64 length, int access); + +#endif // __ROCE_MR_H_ diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_post.h b/drivers/infiniband/hw/hiroce3/qp/roce_post.h new file mode 100644 index 000000000..dbdc9d64c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_post.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_post.h + * Version : v1.0 + * Created : 2022/6/5 + * Last Modified : 2022/6/5 + * Description : Define standard kernel RoCE QP post send/recv realted function prototypes, macros etc,. + */ + +#ifndef ROCE_POST_H +#define ROCE_POST_H + +#include <linux/types.h> + +#include <rdma/ib_verbs.h> + +#include "roce_wqe_format.h" +#include "roce_xqe_format.h" + +#define ROCE_SQ_DB_TYPE 2 +#define ROCE_UD_MTU_SHIFT 3 /* 4K mtu */ +#define ROCE_IMM_EXT_LEN 4 +#define ROCE_TASK_SEG_ALIGN 8 + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) +#define ROCE_ATOMIC_WR atomic_wr +#define ROCE_RDMA_WR rdma_wr +#define ROCE_REG_WR reg_wr +#define ROCE_UD_WR ud_wr +#else +static inline const struct ib_atomic_wr *const_atomic_wr(const struct ib_send_wr *wr) +{ + return container_of(wr, struct ib_atomic_wr, wr); +} + +static inline const struct ib_rdma_wr *const_rdma_wr(const struct ib_send_wr *wr) +{ + return container_of(wr, struct ib_rdma_wr, wr); +} + +static inline const struct ib_ud_wr *const_ud_wr(const struct ib_send_wr *wr) +{ + return container_of(wr, struct ib_ud_wr, wr); +} + +static inline const struct ib_reg_wr *const_reg_wr(const struct ib_send_wr *wr) +{ + return container_of(wr, struct ib_reg_wr, wr); +} + +#define ROCE_ATOMIC_WR const_atomic_wr +#define ROCE_RDMA_WR const_rdma_wr +#define ROCE_REG_WR const_reg_wr +#define ROCE_UD_WR const_ud_wr +#endif + +enum roce_tsl_8_byte_aligned_size_e { + ROCE_SEND_LOCAL_WQE_TSL = 2, + ROCE_RDMA_WQE_TSL = 4, + ROCE_ATOMIC_CWP_WQE_TSL = 6, + ROCE_UD_WQE_COM_TSL = 8 +}; + +enum { + ROCE_WQE_OPCODE_SEND = 0x00, + ROCE_WQE_OPCODE_SEND_INVAL = 0x01, + ROCE_WQE_OPCODE_SEND_IMM = 0x02, + + ROCE_WQE_OPCODE_RDMA_WRITE = 0x04, + ROCE_WQE_OPCODE_RDMA_WRITE_IMM = 0x05, + + ROCE_WQE_OPCODE_RDMA_READ = 0x08, + + ROCE_WQE_OPCODE_ATOMIC_CMP_SWP = 0x0c, + ROCE_WQE_OPCODE_ATOMIC_FETCH_ADD = 0x0d, + ROCE_WQE_OPCODE_MASKED_ATOMIC_CMP_SWP = 0x0e, + ROCE_WQE_OPCODE_MASKED_ATOMIC_FETCH_ADD = 0x0f, + + ROCE_WQE_OPCODE_FRMR = 0x10, + ROCE_WQE_OPCODE_LOCAL_INVAL = 0x11, + ROCE_WQE_OPCODE_BIND_MW = 0x12, + ROCE_WQE_OPCODE_REG_SIG_MR = 0x13 /* Extended for further local opreation */ +}; + +enum { + ROCE_DWQE_DB_SUBTYPE_SEND = 0x1, + ROCE_DWQE_DB_SUBTYPE_SEND_IMM = 0x2, + ROCE_DWQE_DB_SUBTYPE_RDMA_WRITE = 0x3, + ROCE_DWQE_DB_SUBTYPE_RDMA_WRITE_IMM = 0x4, + ROCE_DWQE_DB_SUBTYPE_RDMA_READ = 0x5, + ROCE_DWQE_DB_SUBTYPE_ATOMIC_CMP_SWP = 0x6, + ROCE_DWQE_DB_SUBTYPE_ATOMIC_FETCH_ADD = 0x7 +}; + +/* UD send WQE task seg1 */ +struct roce3_wqe_ud_tsk_seg_cycle1 { + roce_wqe_tsk_com_seg_u common; + + /* DW0 */ + u32 data_len; + + /* DW1 */ + u32 immdata_invkey; + + /* DW2 */ + union { + struct { + u32 pd : 18; + u32 rsvd0 : 6; + u32 stat_rate : 4; /* 0: No limit on the static rate (100% port speed) + 1-6: reserved + 7: 2.5 Gb/s. 8: 10 Gb/s. 9: 30 Gb/s. 10: 5 Gb/s. 11: 20 Gb/s. + 12: 40 Gb/s. 13: 60 Gb/s. 14: 80 Gb/s.15: 120 Gb/s. */ + u32 rsvd1 : 3; + u32 fl : 1; + } bs; + u32 value; + } dw2; + + /* DW3 */ + union { + struct { + u32 hop_limit : 8; + u32 sgid_idx : 7; + u32 rsvd0 : 1; + u32 port : 4; + u32 rsvd1 : 4; + u32 tc : 8; + } bs; + u32 value; + } dw3; + + /* DW4 */ + union { + struct { + u32 flow_label : 20; + u32 rsvd0 : 4; + u32 smac_index : 3; + u32 rsvd1 : 5; + } bs; + u32 value; + } dw4; + + /* DW5~8 */ + u8 dgid[16]; + + /* DW9 */ + union { + struct { + u32 dst_qp : 24; + u32 rsvd : 8; + } bs; + u32 value; + } dw9; + + /* DW10 */ + u32 qkey; +}; + +/* UD send WQE task seg2; */ +struct roce3_wqe_ud_tsk_seg_cycle2 { + /* DW0 */ + union { + struct { + u32 dmac_h16 : 16; + u32 vlan_id : 12; + u32 cfi : 1; + u32 vlan_prio : 3; + } bs; + u32 value; + } dw0; + + /* DW1 */ + u32 dmac_l32; +}; + +struct roce3_post_send_normal_param { + struct roce3_wqe_ctrl_seg *ctrl_seg; + union roce3_wqe_tsk_com_seg *tsk_com_seg; + u32 wqe_size; + u8 *wqe; + struct roce3_wqe_data_seg *dseg; + union roce_sq_db sq_db; + u32 wr_num; /* record posted WR numbers */ + u32 index; /* WQEBB id */ + int inline_flag; /* Inline flag */ + u32 data_len; + u32 *data_len_addr; + u32 sq_rmd_size; + s32 opcode; + s32 cycle; + struct roce3_wqe_ctrl_seg ctrl_seg_tmp; + + unsigned long flags; +}; + +#endif /* ROCE_POST_H */ diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp.h b/drivers/infiniband/hw/hiroce3/qp/roce_qp.h new file mode 100644 index 000000000..9068b3f9d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp.h + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/20 + * Description : Define standard kernel RoCE QP realted function prototypes, macros etc,. + */ + +#ifndef ROCE_QP_H +#define ROCE_QP_H + +#include <linux/types.h> + +#include <rdma/ib_verbs.h> + +#include "hinic3_rdma.h" +#include "hinic3_cqm.h" + +#include "roce.h" +#include "roce_cq.h" +#include "roce_db.h" +#include "roce_pd.h" + +#include "rdma_context_format.h" + +#define ROCE_RQ_MIN_SGE 4 +#define ROCE_RQ_MID_SGE 8 +#define ROCE_RQ_MAX_SGE 16 + +#define ROCE_WQE_NEXT_SGE_INVALID (1UL << 31) + +#define ROCE_QP_TIMER_CHECK_VALUE 0xce +#define ROCE_QP_DESTROY_CHECK_VALUE 0xffffffff +#define ROCE_RDMARC_DESTROY_CHECK_VALUE 0xcece5a5a +#define ROCE_CACHE_LINE_SIZE 256 +#define RDMARC_NUM_PER_CACHELINE 8 +#define RDMARC_TABLE_ENTRY_SIZE 32 +#define ROCE_STATIC_RDMARC_NUM 65536 +#define ROCE_QP_MAX_PFETCH_MTT_LAYER 3 +#define ROCE_QP_MAX_TIMER_NUM 5 + +#define ROCE_QP_SMI_QP_NUM 0x0 +#define ROCE_QP_GSI_QP_NUM 0x1 +#define ROCE_QP_INVLID_QP_NUM CQM_INDEX_INVALID + +#define ROCE_QP_MAX_DWQE_SIZE 256 +#define ROCE_QP_DEFAULT_WQE_SHIFT 6 + +#define ROCE_QP_MODIFY_CMD_OUT_BUF_SIZE 512 + +#define ROCE_QP_STATE_MEM_INIT 0xa + +#define ROCE_UD_MAX_INLINE_LEN_SUB (40) + +#define ROCE_QP_GPA_SIG_LEN 3 +#define ROCE_WR_MIN_NUM 2 + +#define ROCE_QPC_PMTU_TRANSLATE(pmtu) ((1U << ((pmtu) - 1)) - 1) + +#define ROCE_QP_OPTPAR_ALT_ADDR_PATH (1 << 0) +#define ROCE_QP_OPTPAR_RRE (1 << 1) +#define ROCE_QP_OPTPAR_RAE (1 << 2) +#define ROCE_QP_OPTPAR_RWE (1 << 3) +#define ROCE_QP_OPTPAR_PKEY_INDEX (1 << 4) +#define ROCE_QP_OPTPAR_Q_KEY (1 << 5) +#define ROCE_QP_OPTPAR_RNR_TIMEOUT (1 << 6) +#define ROCE_QP_OPTPAR_PRIMARY_ADDR_PATH (1 << 7) +#define ROCE_QP_OPTPAR_SRA_MAX (1 << 8) +#define ROCE_QP_OPTPAR_RRA_MAX (1 << 9) +#define ROCE_QP_OPTPAR_PM_STATE (1 << 10) +#define ROCE_QP_OPTPAR_RETRY_COUNT (1 << 11) +#define ROCE_QP_OPTPAR_RNR_RETRY (1 << 12) +#define ROCE_QP_OPTPAR_ACK_TIMEOUT (1 << 13) +#define ROCE_QP_OPTPAR_SCHED_QUEUE (1 << 14) +#define ROCE_QP_OPTPAR_COUNTER_INDEX (1 << 15) + +#define ROCE3_LB1_MASK 0x3 +#define ROCE3_QPN_BIT_INDEX 29U +#define ROCE3_QPN_CTRL_BIT_NUM 3U + +#define ROCE_VLAN_DIS 0xFFFF + +enum roce_qp_state { + ROCE_QP_STATE_RST = 0, + ROCE_QP_STATE_INIT = 1, + ROCE_QP_STATE_RTR = 2, + ROCE_QP_STATE_RTS = 3, + ROCE_QP_STATE_SQER = 4, + ROCE_QP_STATE_SQD = 5, + ROCE_QP_STATE_ERR = 6, + ROCE_QP_STATE_SQ_DRAINING = 7, + ROCE_QP_STATE_NUM +}; + +enum roce_fake_vf_start_e { + ROCE_VLD_PF_NUM_10 = 10, + ROCE_VLD_PF_NUM_11 = 11, + ROCE_VLD_PF_NUM_12 = 12 +}; + +enum { + ROCE_QP_PM_MIGRATED = 0x3, + ROCE_QP_PM_ARMED = 0x0, + ROCE_QP_PM_REARM = 0x1 +}; + +enum { + ROCE_QP_ST_RC = 0x0, /* 000 */ + ROCE_QP_ST_UC = 0x1, /* 001 */ + ROCE_QP_ST_RD = 0x2, /* 010 */ + ROCE_QP_ST_UD = 0x3, /* 011 */ + ROCE_QP_ST_XRC = 0x6, /* 110 */ + ROCE_QP_ST_PRIV = 0x7 /* 111 */ +}; + +enum { + ROCE_QP_NO_SRQ, + ROCE_QP_HAS_SRQ +}; + +enum { + ROCE_QP = 0, + ROCE_QP_EXT +}; + +struct roce3_wq { + u64 *wrid; + spinlock_t lock; + u32 wqebb_cnt; + u32 max_post; + u32 max_sge; + u32 offset; + u32 wqe_shift; + u32 head; + u32 tail; +}; + +struct roce3_qp { + struct ib_qp ibqp; + u32 qpn; + struct roce3_db db; + cqm_queue_s *qp_buf_info; + cqm_qpc_mpt_s *qpc_info; + struct roce3_wq rq; + u32 sq_signal_bits; + unsigned int sq_next_wqe; + u32 sq_max_wqes_per_wr; + struct roce3_wq sq; + struct ib_umem *umem; + struct rdma_mtt mtt; + struct roce3_buf buf; + int buf_size; + struct mutex mutex; + u32 xrcdn; + u8 port; + u8 atomic_rd_en; + u8 qp_state; + u8 qp_ext; + u32 qp_type; + u32 max_inline_data; + int max_dwqe_size; + struct rdma_rdmarc rdmarc; + u16 rsp_depth; + u8 sl; + bool has_rq; + u8 *sq_head_addr; + u8 *sq_tail_addr; + bool signature_en; + u8 double_sgl_mode; + u8 ext_mtu; + u8 ext_mtu_mode; + + u8 db_sgid_index; + u8 db_path_mtu; + + u32 qid; + u32 local_comm_id; /* used by NOF AA to reuse qpn when disconnection happens */ + u32 remote_comm_id; + + /* hot-plug record */ + struct list_head qps_list; + struct list_head cq_recv_list; + struct list_head cq_send_list; +#if defined(ROCE_VBS_EN) || defined(ROCE_EXTEND) + void *vbs_qp_ptr; +#endif +#ifdef ROCE_BONDING_EN + u32 tx_hash_value; +#endif +}; + +struct roce3_sqp { + struct roce3_qp qp; + int pkey_index; + u32 qkey; + u32 send_psn; +}; + +static inline struct roce3_qp *to_roce3_qp(const struct ib_qp *ibqp) +{ + return container_of(ibqp, struct roce3_qp, ibqp); +} + +static inline struct roce3_qp *cqmobj_to_roce_qp(const cqm_object_s *object) +{ + cqm_qpc_mpt_s *qpc_info; + qpc_info = container_of(object, cqm_qpc_mpt_s, object); + return (struct roce3_qp *)qpc_info->priv; +} + +static inline struct roce3_sqp *to_roce3_sqp(const struct roce3_qp *rqp) +{ + return container_of(rqp, struct roce3_sqp, qp); +} + +struct roce3_qp_query_outbuf { + struct roce_qp_context qpc; +}; + +void roce3_qp_async_event(struct roce3_device *rdev, struct roce3_qp *qp, int type); +u8 roce3_get_db_cos_from_vlan_pri(struct roce3_device *rdev, u8 vlan_pri); + +void roce3_free_opt_rdmarc(struct roce3_qp *rqp); +void roce3_get_cqs(struct roce3_qp *rqp, struct roce3_cq **send_cq, struct roce3_cq **recv_cq); +int roce3_qp_modify_2rst_cmd(struct roce3_device *rdev, u32 qpn); +int roce3_qp_cache_out_cmd(struct roce3_device *rdev, struct roce3_qp *rqp); +struct roce3_pd *roce3_get_pd(struct roce3_qp *rqp); +int roce3_sqp_check(const struct roce3_qp *qp); +void *roce3_get_wqe(struct roce3_qp *rqp, u32 offset); +int roce3_wq_overflow(struct roce3_wq *wq, u32 wr_num, struct ib_cq *ibcq); +void roce3_set_data_seg(struct roce3_wqe_data_seg *dseg, struct ib_sge *sge); +void roce3_qpc_to_be(roce_verbs_qp_attr_s *qp_attr, struct roce3_qp *rqp, u32 *be_ctx); +void roce3_qp_rst2init(struct roce3_qp *rqp, const struct ib_qp_attr *attr, roce_verbs_qp_attr_s *qp_attr); +#ifdef OFED_MLNX_5_8 +int roce3_create_qp_common(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata, + struct roce3_qp *rqp, int qp_ext); +#else +struct ib_qp *roce3_create_qp_common(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata, + int qp_ext); +#endif +int roce3_send_qp_lb_cmd(u32 qpn, struct roce3_device *rdev, u8 cmd, cqm_cmd_buf_s *buf_in, cqm_cmd_buf_s *buf_out, + u32 timeout); + +int roce3_qp_query(struct roce3_device *rdev, u32 qpn, u32 *context, int qpc_size); +int roce3_post_send_standard(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr); +void qpc_seg_to_le32(struct roce_qp_context *be_ctx, struct roce_qp_context *le_ctx, u32 srq_vld); +void roce3_be32_2_le32(void *context, u32 *le_ctx, u32 ctx_size); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +#define IB_QP_CREATE_SIGNATURE_EN IB_QP_CREATE_INTEGRITY_EN +#endif + +#endif // ROCE_QP_H diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_create.c b/drivers/infiniband/hw/hiroce3/qp/roce_qp_create.c new file mode 100755 index 000000000..c7cd41f26 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_create.c @@ -0,0 +1,1296 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_create.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : The definition of RoCE QP service create realated functions in kernel space. + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include <rdma/ib_verbs.h> + +#include "roce_compat.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_mr.h" +#include "roce_user.h" +#include "roce_xrc.h" +#include "roce_pd.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_qp.h" +#include "roce_pub_cmd.h" +#include "roce_qp_extension.h" +#include "roce_main_extension.h" + +#include "hinic3_hmm.h" +#ifdef __ROCE_DFX__ +#include "roce_dfx.h" +#endif + +/* **************************************************************************** + Prototype : roce3_check_rq_size + Description : roce3_check_rq_size + Input : struct roce3_device *rdev + struct roce3_qp *rqp + struct ib_qp_cap *cap + bool has_rq + Output : None + + 1.Date : 2017/4/27 + Modification : Created function +**************************************************************************** */ +static int roce3_check_rq_size(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr, + bool has_rq) +{ + u32 max_sge_num; + struct ib_qp_cap *cap = &init_attr->cap; + + max_sge_num = (u32)ROCE_MIN(rdev->rdma_cap.max_sq_sg, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_rq_sg); + if ((cap->max_recv_wr > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_wqes) || (cap->max_recv_sge > max_sge_num)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to check rq size, over range, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + if (has_rq && ((cap->max_recv_wr == 0) || (cap->max_recv_sge == 0))) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Has rq, cap->max_recv_wr(%d), cap->max_recv_sge(%d), func_id(%d)\n", + __func__, cap->max_recv_wr, cap->max_recv_sge, rdev->glb_func_id); + return -EINVAL; + } + + if ((!has_rq) && (cap->max_recv_wr != 0)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Not has rq, cap->max_recv_wr(%d), func_id(%d)\n", __func__, + cap->max_recv_wr, rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_set_rq_size + Description : roce3_set_rq_size + Input : struct roce3_device *rdev + struct roce3_qp *rqp + struct ib_qp_cap *cap + bool is_user + bool has_rq + Output : None + + 1.Date : 2015/4/29 + Modification : Created function +**************************************************************************** */ +/* **************************************************************************** +* +* 1 there is SQ or RQ +* SQ/RQ depth must be power of 2 +* if max_send_wr=0, no need to alloc buf for SQ/RQ + +* RQ WQE SIZE equals 64 or128 +* SQ WQE SIZE equals multi of wqebb size + +* SQ max_gs, max 8 and min 0 +* RQ max_gs, can be 4 or 8, but can not be 0. + +* 2 there is no SQ or RQ +* all related params should be 0 +* + +**************************************************************************** */ +static int roce3_set_rq_size(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr, + bool is_user, bool has_rq) +{ + int ret; + u32 wqebb_num = 0; + u32 sge_total_len = 0; + u32 sge_num = 0; + struct ib_qp_cap *cap = &init_attr->cap; + + ret = roce3_check_rq_size(rdev, rqp, init_attr, has_rq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to check rq size, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + if (has_rq) { + wqebb_num = ROCE_MAX(2U, cap->max_recv_wr); + /*lint -e587*/ + rqp->rq.wqebb_cnt = (u32)(ROCE_ROUNDUP_POW_OF_TWO(wqebb_num) & 0xffffffff); + /*lint +e587*/ + + /* RQ SGE range [0,4] select 4,[5,8] select 8 */ + rqp->rq.max_sge = (cap->max_recv_sge <= ROCE_RQ_MIN_SGE) ? + ROCE_RQ_MIN_SGE : + ((cap->max_recv_sge <= ROCE_RQ_MID_SGE) ? ROCE_RQ_MID_SGE : ROCE_RQ_MAX_SGE); + + sge_total_len = (u32)((u32)rqp->rq.max_sge * sizeof(struct roce3_wqe_data_seg)); + rqp->rq.wqe_shift = (u32)ROCE_ILOG2(sge_total_len); + + if ((u32)((u32)rqp->rq.wqebb_cnt << (unsigned)rqp->rq.wqe_shift) < PAGE_SIZE) { + rqp->rq.wqebb_cnt = (PAGE_SIZE >> (unsigned)rqp->rq.wqe_shift); + } + + /* leave userspace return values as they were, so as not to break ABI */ + if (is_user) { + rqp->rq.max_post = ROCE_MIN(rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_wqes, rqp->rq.wqebb_cnt); + cap->max_recv_wr = (u32)rqp->rq.max_post; + cap->max_recv_sge = (u32)rqp->rq.max_sge; + } else { + rqp->rq.max_post = ROCE_MIN(rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_wqes, rqp->rq.wqebb_cnt); + cap->max_recv_wr = (u32)rqp->rq.max_post; + sge_num = ROCE_MIN(rdev->rdma_cap.max_sq_sg, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_rq_sg); + cap->max_recv_sge = ROCE_MIN((u32)rqp->rq.max_sge, sge_num); + } + } else { + rqp->rq.wqebb_cnt = 0; + rqp->rq.max_sge = 0; + rqp->rq.wqe_shift = ROCE_QP_DEFAULT_WQE_SHIFT; + rqp->rq.max_post = 0; + cap->max_recv_sge = 0; + } + + rqp->rq.head = 0; + rqp->rq.tail = 0; + + return 0; +} + +static int roce3_set_user_sq_size_check(struct roce3_device *rdev, const struct ib_qp_cap *cap, + const struct roce3_qp *rqp) +{ + u32 ud_max_inline_size; + + if (cap->max_send_wr > (rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_wqes)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Log_sq_bb_count over range, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + if (rqp->qp_type == IB_QPT_UD) { + ud_max_inline_size = + (rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz > ROCE_UD_MAX_INLINE_LEN_SUB) ? + (rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz - ROCE_UD_MAX_INLINE_LEN_SUB) : + rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz; + } else { + ud_max_inline_size = rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz; + } + + /* RC:192B inline data, UD:176B */ + if (cap->max_inline_data > ud_max_inline_size) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: SQ max inline data over range, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} +/* **************************************************************************** + Prototype : roce3_set_user_sq_size + Description : roce3_set_user_sq_size + Input : struct roce3_device *rdev + struct ib_qp_cap *cap + struct roce3_qp *rqp + struct roce3_create_qp *ucmd + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +static int roce3_set_user_sq_size(struct roce3_device *rdev, struct ib_qp_cap *cap, struct roce3_qp *rqp, + struct create_qp_cmd *ucmd) +{ + u32 tmp_max_sq_wqe_sz = 0; + u32 sq_buf_sz = 0; + int ret = 0; + + ret = roce3_set_user_sq_size_check(rdev, cap, rqp); + if (ret != 0) { + return ret; + } + + if (rqp->qp_type != IB_QPT_XRC_TGT) { + /* between max and min */ + /*lint -e587*/ + tmp_max_sq_wqe_sz = (u32)(ROCE_ROUNDUP_POW_OF_TWO(rdev->rdma_cap.max_sq_desc_sz) & 0xffffffff); + /*lint +e587*/ + if ((ucmd->log_sq_stride > ROCE_ILOG2(tmp_max_sq_wqe_sz)) || + (ucmd->log_sq_stride < ROCE_ILOG2(rdev->rdma_cap.wqebb_size))) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: WQE size invalid, func_id(%d) log_sq_stride:%d wqebb_size:%d " + "tmp_max_sq_wqe_sz:%d\n", + __func__, rdev->glb_func_id, ucmd->log_sq_stride, rdev->rdma_cap.wqebb_size, tmp_max_sq_wqe_sz); + return -EINVAL; + } + + rqp->sq.wqebb_cnt = (u32)(1U << ucmd->log_sq_bb_count); + rqp->sq.wqe_shift = ucmd->log_sq_stride; + + if ((u32)((u64)rqp->sq.wqebb_cnt << (unsigned)rqp->sq.wqe_shift) < PAGE_SIZE) { + rqp->sq.wqebb_cnt = (PAGE_SIZE >> (unsigned)rqp->sq.wqe_shift); + } + + sq_buf_sz = (u32)ROCE_ALIGN((u64)rqp->sq.wqebb_cnt << (unsigned)rqp->sq.wqe_shift, PAGE_SIZE); + rqp->buf_size = (int)ROCE_ALIGN( + ((unsigned)sq_buf_sz + ((unsigned)rqp->rq.wqebb_cnt << (unsigned)rqp->rq.wqe_shift)), PAGE_SIZE); + + rqp->sq.offset = 0; + rqp->rq.offset = sq_buf_sz; + + rqp->max_inline_data = cap->max_inline_data; + } else { + rqp->sq.wqebb_cnt = 0; + rqp->sq.wqe_shift = ucmd->log_sq_stride; + rqp->buf_size = 0; + rqp->sq.offset = 0; + rqp->rq.offset = 0; + rqp->max_inline_data = 0; + cap->max_inline_data = 0; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_send_wqe_overhead + Description : roce3_send_wqe_overhead + Input : enum ib_qp_type qp_type + Output : None + + 1.Date : 2015/5/7 + Modification : Created function + +**************************************************************************** */ +static int roce3_send_wqe_overhead(enum ib_qp_type qp_type) +{ + switch (qp_type) { + case IB_QPT_RC: + return sizeof(struct roce3_wqe_ctrl_seg) + sizeof(struct roce3_wqe_mask_atomic_tsk_seg); + + case IB_QPT_UC: + return sizeof(struct roce3_wqe_ctrl_seg) + sizeof(struct roce3_wqe_send_tsk_seg); + + case IB_QPT_UD: + return sizeof(struct roce3_wqe_ctrl_seg) + sizeof(struct roce3_wqe_ud_tsk_seg); + + case IB_QPT_GSI: + return sizeof(struct roce3_wqe_ctrl_seg) + sizeof(struct roce3_wqe_ud_tsk_seg); + + case IB_QPT_XRC_TGT: + return 0; + + case IB_QPT_XRC_INI: + return sizeof(struct roce3_wqe_ctrl_seg) + sizeof(struct roce3_wqe_mask_atomic_tsk_seg); + + default: + pr_err("[ROCE, ERR] %s: Not supported this qp_type\n", __func__); + return -1; + } +} + +static int roce3_set_kernel_sq_size_check(const struct roce3_device *rdev, const struct ib_qp_cap *cap, + int *sq_max_wqe_size, enum ib_qp_type qp_type) +{ + int wqe_overhead = 0; + int ret = 0; + + if (cap->max_send_wr > (u32)rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_wqes) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: SQ WR over range, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + if (cap->max_send_sge > + (u32)ROCE_MIN(rdev->rdma_cap.max_sq_sg, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_rq_sg)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: SQ SGE over range, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + if (cap->max_inline_data > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: SQ max inline data over range, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + wqe_overhead = roce3_send_wqe_overhead(qp_type); + if (wqe_overhead < 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Invalid service type(%d), func_id(%d)\n", __func__, (int)qp_type, + rdev->glb_func_id); + return -EINVAL; + } + + *sq_max_wqe_size = + ROCE_MAX((int)(cap->max_send_sge * sizeof(struct roce3_wqe_data_seg)), (int)cap->max_inline_data) + + wqe_overhead; + if (*sq_max_wqe_size > (int)rdev->rdma_cap.max_sq_desc_sz) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: SQ WQE size over range, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + return ret; +} +/* **************************************************************************** + Prototype : roce3_set_kernel_sq_size + Description : roce3_set_kernel_sq_size + Input : struct roce3_device *rdev + struct ib_qp_cap *cap + enum roce3_qp_type qp_type + struct roce3_qp *rqp + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +static int roce3_set_kernel_sq_size(struct roce3_device *rdev, struct ib_qp_cap *cap, enum ib_qp_type qp_type, + struct roce3_qp *rqp) + +{ + u32 sq_buf_sz = 0; + int sq_max_wqe_size = 0; + int ret = 0; + + ret = roce3_set_kernel_sq_size_check(rdev, cap, &sq_max_wqe_size, qp_type); + if (ret != 0) { + return ret; + } + + if (rqp->qp_type != IB_QPT_XRC_TGT) { + rqp->sq.wqe_shift = (u32)ROCE_ILOG2(rdev->rdma_cap.wqebb_size); + rqp->sq_max_wqes_per_wr = + (u32)ROCE_DIV_ROUND_UP((unsigned)sq_max_wqe_size, (u32)(1UL << (unsigned)rqp->sq.wqe_shift)); + + /* + * As one wqebb ought to be reserved for invalidate wqebb, 1 is added to sq.wqebb_cnt here + * to satisfy the actual IB_MAD_QP_SEND_SIZE set by applications + */ + rqp->sq.wqebb_cnt = (u32)((int)cap->max_send_wr * rqp->sq_max_wqes_per_wr + 1); + /*lint -e587*/ + rqp->sq.wqebb_cnt = (u32)(ROCE_ROUNDUP_POW_OF_TWO(rqp->sq.wqebb_cnt) & 0xffffffff); + /*lint +e587*/ + + if ((u32)((u64)rqp->sq.wqebb_cnt << (u32)rqp->sq.wqe_shift) < PAGE_SIZE) { + rqp->sq.wqebb_cnt = (PAGE_SIZE >> ((u32)rqp->sq.wqe_shift)); + } + + rqp->sq.max_sge = (u32)(((u64)rqp->sq_max_wqes_per_wr << (unsigned)rqp->sq.wqe_shift) - + (unsigned)roce3_send_wqe_overhead(qp_type)); + rqp->sq.max_sge = + (u32)ROCE_MIN(rdev->rdma_cap.max_sq_desc_sz, rqp->sq.max_sge) / (int)sizeof(struct roce3_wqe_data_seg); + + sq_buf_sz = (u32)ALIGN((u64)rqp->sq.wqebb_cnt << (unsigned)rqp->sq.wqe_shift, PAGE_SIZE); + rqp->buf_size = + (int)ALIGN(((unsigned)sq_buf_sz + ((unsigned)rqp->rq.wqebb_cnt << (unsigned)rqp->rq.wqe_shift)), PAGE_SIZE); + + rqp->sq.offset = 0u; + rqp->rq.offset = sq_buf_sz; + + if (((rqp->sq.wqebb_cnt - 1) / rqp->sq_max_wqes_per_wr) == 1) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s:Only one WR,please check,func_id(%d)\n", __func__, rdev->glb_func_id); + rqp->sq.max_post = ROCE_WR_MIN_NUM; + cap->max_send_wr = rqp->sq.max_post; + } else { + rqp->sq.max_post = (rqp->sq.wqebb_cnt - 1) / rqp->sq_max_wqes_per_wr; + cap->max_send_wr = (u32)rqp->sq.max_post; + } + + cap->max_send_sge = (u32)ROCE_MIN(rdev->rdma_cap.max_sq_sg, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_rq_sg); + cap->max_send_sge = (u32)ROCE_MIN(rqp->sq.max_sge, cap->max_send_sge); + rqp->max_inline_data = cap->max_inline_data; + } else { + rqp->sq.wqebb_cnt = 0; + rqp->sq.wqe_shift = ROCE_QP_DEFAULT_WQE_SHIFT; + rqp->buf_size = 0; + rqp->sq.offset = 0; + rqp->rq.offset = 0; + rqp->max_inline_data = 0; + cap->max_inline_data = 0; + } + + rqp->sq.head = 0; + rqp->sq.tail = 0; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_qp_async_event + Description : roce3_qp_async_event + Input : struct roce3_device *rdev + struct roce3_qp *qp + int type + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +void roce3_qp_async_event(struct roce3_device *rdev, struct roce3_qp *qp, int type) +{ + struct ib_event event; + struct ib_qp *ibqp = &qp->ibqp; + + memset(&event, 0, sizeof(event)); + + if (ibqp->event_handler) { + event.device = ibqp->device; + event.element.qp = ibqp; + + switch (type) { + case ROCE_EVENT_TYPE_COMM_EST: + event.event = IB_EVENT_COMM_EST; + break; + + case ROCE_EVENT_TYPE_SQ_DRAINED: + event.event = IB_EVENT_SQ_DRAINED; + break; + + case ROCE_EVENT_TYPE_SRQ_QP_LAST_WQE: + event.event = IB_EVENT_QP_LAST_WQE_REACHED; + break; + + case ROCE_EVENT_TYPE_WQ_CATAS_ERROR: + event.event = IB_EVENT_QP_FATAL; + break; + + case ROCE_EVENT_TYPE_WQ_INVAL_REQ_ERROR: + event.event = IB_EVENT_QP_REQ_ERR; + break; + + case ROCE_EVENT_TYPE_WQ_ACCESS_ERROR: + event.event = IB_EVENT_QP_ACCESS_ERR; + break; + + default: + return; + } + + ibqp->event_handler(&event, ibqp->qp_context); + } +} + +static void *roce3_buf_offset(struct roce3_buf *buf, u32 offset) +{ + return (void *)((char *)buf->direct.buf + offset); +} + +void *roce3_get_wqe(struct roce3_qp *rqp, u32 offset) +{ + return roce3_buf_offset(&rqp->buf, offset); +} + +static void *roce3_get_send_wqe_head(struct roce3_qp *rqp) +{ + return roce3_get_wqe(rqp, rqp->sq.offset); +} + +/* **************************************************************************** + Prototype : roce3_get_send_wqe_tail + Description : roce3_get_send_wqe_tail + Input : struct roce3_qp *rqp + Output : None + + 1.Date : 2015/8/8 + Modification : Created function + +**************************************************************************** */ +static void *roce3_get_send_wqe_tail(struct roce3_qp *rqp) +{ + return roce3_get_wqe(rqp, rqp->sq.offset + (rqp->sq.wqebb_cnt << (u32)rqp->sq.wqe_shift)); +} + +/* **************************************************************************** + Prototype : roce3_sq_buf_init + Description : roce3_sq_buf_init + Input : struct roce3_qp *qp + Output : None + + 1.Date : 2015/11/9 + Modification : Created function + +**************************************************************************** */ +static void roce3_sq_buf_init(struct roce3_qp *qp) +{ + u32 entries = qp->rq.offset / (1U << qp->sq.wqe_shift); + u8 *wqe = NULL; + struct roce3_wqe_ctrl_seg *wqe_ctrl = NULL; + u32 i; + + for (i = 0; i < entries; i++) { + wqe = (u8 *)qp->buf.direct.buf + (int)(i * (int)(1U << ((u32)qp->sq.wqe_shift))); + wqe_ctrl = (struct roce3_wqe_ctrl_seg *)((void *)wqe); + wqe_ctrl->dw0.value = be32_to_cpu(wqe_ctrl->dw0.value); + wqe_ctrl->dw0.bs.owner = 1; + wqe_ctrl->dw0.value = cpu_to_be32(wqe_ctrl->dw0.value); + } +} + +static int roce3_check_and_get_umem(struct roce3_device *rdev, struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, + struct ib_udata *udata, struct roce3_qp *rqp, struct create_qp_cmd *ucmd) +{ + int ret = 0; + + if ((udata == NULL) || (ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)) != 0)) { + ret = -EFAULT; + return ret; + } + + ret = roce3_set_user_sq_size(rdev, &init_attr->cap, rqp, ucmd); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set user sq_size, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + rqp->umem = ib_umem_get(&rdev->ib_dev, ucmd->buf_addr, (size_t)rqp->buf_size, 0); +#elif defined(OFED_MLNX_5_8) + rqp->umem = ib_umem_get(udata, ucmd->buf_addr, (size_t)(unsigned)rqp->buf_size, 0); +#else + rqp->umem = ib_umem_get(ibpd->uobject->context, ucmd->buf_addr, (size_t)(unsigned)rqp->buf_size, 0, 0); +#endif + if (IS_ERR(rqp->umem)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get ib_umem, func_id(%d)\n", __func__, rdev->glb_func_id); + ret = (int)PTR_ERR(rqp->umem); + return ret; + } + + return ret; +} + +static int roce3_alloc_qpc(struct roce3_qp *rqp, struct roce3_device *rdev, u32 qpn, struct ib_qp_init_attr *init_attr) +{ + cqm_qpc_mpt_s *qpc_info = NULL; + int ret; + struct roce3_srq *rsrq; + u32 qpn_tmp = qpn; + bool low2bit_align_en = false; + + if (roce3_need_qpn_lb1_consistent_srqn(rqp, rdev, init_attr)) { + rsrq = to_roce3_srq(init_attr->srq); + qpn_tmp = ((rsrq->srqn & ROCE3_LB1_MASK) << ROCE3_QPN_BIT_INDEX) | qpn_tmp >> ROCE3_QPN_CTRL_BIT_NUM; + low2bit_align_en = true; + } + + qpc_info = cqm_object_qpc_mpt_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_SERVICE_CTX, + rdev->rdma_cap.dev_rdma_cap.roce_own_cap.qpc_entry_sz, rqp, qpn_tmp, low2bit_align_en); + if (qpc_info == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qpc mpt by cqm object, func_id(%d), qpn(%u)\n", + __func__, rdev->glb_func_id, qpn_tmp); + return ret; + } + + rqp->qpc_info = qpc_info; + rqp->qpn = rqp->qpc_info->xid; + if (roce3_need_qpn_lb1_consistent_srqn(rqp, rdev, init_attr)) { + rsrq = to_roce3_srq(init_attr->srq); + if ((rsrq->srqn & ROCE3_LB1_MASK) != (rqp->qpn & ROCE3_LB1_MASK)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qpc LB srqn, func_id(%d), qpn(%u) srqn(%u)\n", + __func__, rdev->glb_func_id, rqp->qpn, rsrq->srqn); + } + } + return 0; +} + +static int roce3_create_qp_user_mtt(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + u32 npages; + int ret; + + npages = (u32)ib_umem_num_pages(rqp->umem); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + rqp->buf.page_shift = PAGE_SHIFT; +#else + rqp->buf.page_shift = rqp->umem->page_shift; +#endif + + rqp->mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, npages, (u32)rqp->buf.page_shift, &rqp->mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma_mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + ret = roce3_umem_write_mtt(rdev, &rqp->mtt, rqp->umem); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_write_mtt; + } + + return 0; + +err_write_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &rqp->mtt, SERVICE_T_ROCE); + return ret; +} + +static void roce3_destroy_qp_user_mtt(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + hmm_rdma_mtt_free(rdev->hwdev, &rqp->mtt, SERVICE_T_ROCE); +} + +/* **************************************************************************** + Prototype : roce3_create_qp_user + Description : create qp resource for user space qp + Input : struct roce3_device *rdev + struct ib_pd *ibpd + struct ib_qp_init_attr *init_attr + struct ib_udata *udata + struct roce3_qp *rqp + Output : None + + 1.Date : 2016/01/30 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_qp_user(struct roce3_device *rdev, struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, + struct ib_udata *udata, struct roce3_qp *rqp) +{ + int ret = 0; + struct roce3_ucontext *roce3_uctx = NULL; + struct create_qp_cmd ucmd = { 0 }; + u32 qpn = 0; + + ret = roce3_create_qp_user_pre_ext(init_attr, rqp, &qpn); + if (ret != 0) { + return ret; + } + + roce3_uctx = to_roce3_ucontext(ibpd->uobject->context); + + ret = roce3_check_and_get_umem(rdev, ibpd, init_attr, udata, rqp, &ucmd); + if (ret != 0) { + return ret; + } + + ret = roce3_create_qp_user_mtt(rdev, rqp); + if (ret != 0) { + goto err_create_mtt; + } + + if (init_attr->qp_type != IB_QPT_XRC_TGT) { + ret = roce3_db_map_user(roce3_uctx, ucmd.db_addr, &rqp->db); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to map db page to user, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_map_db; + } + } + + ret = roce3_alloc_qpc(rqp, rdev, qpn, init_attr); + if (ret != 0) { + goto err_alloc_qpc; + } + + ret = roce3_create_qp_user_post_ext(ibpd, rdev, rqp, init_attr); + if (ret != 0) { + goto err_extend_post; + } + + return 0; + +err_extend_post: + hiudk_cqm_object_delete(rdev->hwdev, &(rqp->qpc_info->object)); + +err_alloc_qpc: + if (init_attr->qp_type != IB_QPT_XRC_TGT) { + roce3_db_unmap_user(roce3_uctx, &rqp->db); + } + +err_map_db: + roce3_destroy_qp_user_mtt(rdev, rqp); + +err_create_mtt: + ib_umem_release(rqp->umem); + + return ret; +} + +static void roce3_free_wrid(struct roce3_qp *rqp) +{ + if (rqp->rq.wrid) { + kvfree(rqp->rq.wrid); + } + + if (rqp->sq.wrid) { + kvfree(rqp->sq.wrid); + } +} + +static int roce3_get_wrid(struct roce3_qp *rqp, struct roce3_device *rdev) +{ + int ret = 0; + + rqp->sq.wrid = (u64 *)kzalloc((unsigned)rqp->sq.wqebb_cnt * sizeof(u64), GFP_KERNEL); + if (rqp->sq.wrid == NULL) { + rqp->sq.wrid = (u64 *)(void *)vzalloc((size_t)(rqp->sq.wqebb_cnt * sizeof(u64))); + } + + rqp->rq.wrid = (u64 *)kzalloc((unsigned)rqp->rq.wqebb_cnt * sizeof(u64), GFP_KERNEL); + if (rqp->rq.wrid == NULL) { + rqp->rq.wrid = (u64 *)(void *)vzalloc((size_t)(rqp->rq.wqebb_cnt * sizeof(u64))); + } + + if ((rqp->sq.wrid == NULL) || (rqp->rq.wrid == NULL)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc wrid of sq or rq, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -ENOMEM; + } + + return ret; +} + +static void roce3_create_qp_kernel_set_attr(struct roce3_qp *rqp, cqm_queue_s *qp_buf_info) +{ + memset(qp_buf_info->q_room_buf_1.direct.va, 0, + (size_t)((unsigned)rqp->buf_size)); + rqp->buf.direct.buf = qp_buf_info->q_room_buf_1.direct.va; + rqp->buf.direct.map = qp_buf_info->q_room_buf_1.direct.pa; + rqp->buf.page_shift = ROCE_ILOG2(qp_buf_info->q_room_buf_1.buf_size); + + roce3_sq_buf_init(rqp); + + rqp->db.db_record = (__be32 *)(void *)(&qp_buf_info->q_header_vaddr->doorbell_record); + rqp->db.dma = qp_buf_info->q_header_paddr; + + qp_buf_info->q_header_vaddr->doorbell_record = 0; + + rqp->qp_buf_info = qp_buf_info; + + rqp->sq_head_addr = (u8 *)roce3_get_send_wqe_head(rqp); + rqp->sq_tail_addr = (u8 *)roce3_get_send_wqe_tail(rqp); + rqp->max_dwqe_size = 0; + + if (rqp->max_inline_data != 0) { + rqp->max_dwqe_size = ROCE_QP_MAX_DWQE_SIZE; + } +} + +static int roce3_create_qp_kernel_normal(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + int ret; + cqm_queue_s *qp_buf_info = NULL; + + qp_buf_info = cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_QP, (u32)rqp->buf_size, rqp, + true, ROCE_QP_INVLID_QP_NUM); + if (qp_buf_info == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create rdma queue by cqm object, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -1; + } + + roce3_create_qp_kernel_set_attr(rqp, qp_buf_info); + + rqp->mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, qp_buf_info->q_room_buf_1.buf_number, (u32)rqp->buf.page_shift, &rqp->mtt, + SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_alloc_mtt; + } + ret = roce3_buf_write_mtt(rdev, &rqp->mtt, &rqp->qp_buf_info->q_room_buf_1); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_write_mtt; + } + + ret = roce3_get_wrid(rqp, rdev); + if (ret != 0) { + goto err_alloc_wrid; + } + + return 0; + +err_alloc_wrid: + roce3_free_wrid(rqp); + +err_write_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &rqp->mtt, SERVICE_T_ROCE); + +err_alloc_mtt: + hiudk_cqm_object_delete(rdev->hwdev, &rqp->qp_buf_info->object); + + return ret; +} + +static void roce3_destroy_qp_kernel_normal(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + roce3_free_wrid(rqp); + hmm_rdma_mtt_free(rdev->hwdev, &rqp->mtt, SERVICE_T_ROCE); + hiudk_cqm_object_delete(rdev->hwdev, &rqp->qp_buf_info->object); +} + +/* **************************************************************************** + Prototype : roce3_create_qp_kernel + Description : create qp resource for kernel space qp + Input : struct roce3_device *rdev + struct ib_qp_init_attr *init_attr + struct roce3_qp *rqp + u32 qpn + Output : None + + 1.Date : 2016/01/30 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_qp_kernel(struct roce3_device *rdev, struct ib_qp_init_attr *init_attr, struct roce3_qp *rqp, + u32 qpn) +{ + int ret = 0; + + ret = roce3_set_kernel_sq_size(rdev, &init_attr->cap, (enum ib_qp_type)rqp->qp_type, rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set sq buffer size in kernel, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + if (rqp->qp_type != IB_QPT_XRC_TGT) { + ret = roce3_create_qp_kernel_normal(rdev, rqp); + if (ret != 0) { + return ret; + } + } + + ret = roce3_alloc_qpc(rqp, rdev, qpn, init_attr); + if (ret != 0) { + goto err_alloc_qpc; + } + + return 0; + +err_alloc_qpc: + if (rqp->qp_type != IB_QPT_XRC_TGT) { + roce3_destroy_qp_kernel_normal(rdev, rqp); + } + + return ret; +} + +static void roce3_qp_add_cq_list(struct ib_qp_init_attr *init_attr, struct roce3_qp *rqp, struct roce3_device *rdev) +{ + struct roce3_cq *send_rcq = to_roce3_cq(init_attr->send_cq); + struct roce3_cq *recv_rcq = to_roce3_cq(init_attr->recv_cq); + unsigned long flags; + + spin_lock_irqsave(&rdev->reset_flow_resource_lock, flags); + roce3_lock_cqs(send_rcq, recv_rcq); + list_add_tail(&rqp->qps_list, &rdev->qp_list); + list_add_tail(&rqp->cq_send_list, &send_rcq->send_qp_list); + list_add_tail(&rqp->cq_recv_list, &recv_rcq->recv_qp_list); + roce3_unlock_cqs(send_rcq, recv_rcq); + spin_unlock_irqrestore(&rdev->reset_flow_resource_lock, flags); +} + +static void roce3_init_qp_state(struct roce3_qp *rqp, struct roce3_device *rdev) +{ + struct roce_qp_context *qpc = (struct roce_qp_context *)((void *)rqp->qpc_info->vaddr); + + if (!cqm_need_secure_mem(rdev->hwdev)) { + qpc->sw_seg.drv_seg.dw0.bs.state = ROCE_QP_STATE_MEM_INIT; + qpc->sw_seg.drv_seg.dw0.value = cpu_to_be32(qpc->sw_seg.drv_seg.dw0.value); + } + + return; +} + +/* **************************************************************************** + Prototype : roce3_create_qp_common + Description : roce3_create_qp_common + Input : struct roce3_device *rdev + struct roce3_qp *rqp + struct ib_pd *ibpd + struct ib_qp_init_attr *init_attr + struct ib_udata *udata + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +static int roce3_do_create_qp(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_pd *ibpd, + struct ib_qp_init_attr *init_attr, struct ib_udata *udata) +{ + int ret = 0; + + mutex_init(&rqp->mutex); + /*lint -e708 -e413 */ + spin_lock_init(&rqp->sq.lock); + spin_lock_init(&rqp->rq.lock); + /*lint +e708 +e413 */ + + rqp->qp_state = IB_QPS_RESET; + rqp->qp_type = init_attr->qp_type; + rqp->sq_signal_bits = (u32)(init_attr->sq_sig_type == IB_SIGNAL_ALL_WR); + + if (ibpd->uobject) { + ret = roce3_set_rq_size(rdev, rqp, init_attr, true, rqp->has_rq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set rq size, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + ret = roce3_create_qp_pre_ext(rdev, rqp, init_attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to handle qp create pre extension, func_id(%d)\n", + rdev->glb_func_id); + return ret; + } + + ret = roce3_create_qp_user(rdev, ibpd, init_attr, udata, rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to create qp user, func_id(%d)\n", rdev->glb_func_id); + return ret; + } + } else { + ret = roce3_set_rq_size(rdev, rqp, init_attr, false, rqp->has_rq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set rq size, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + ret = roce3_create_qp_kernel(rdev, init_attr, rqp, ROCE_QP_INVLID_QP_NUM); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp kernel, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + roce3_qp_add_cq_list(init_attr, rqp, rdev); + } + + if (roce3_is_qp_normal(rqp, init_attr) != 0) { + roce3_init_qp_state(rqp, rdev); + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_create_qp_gsi + Description : roce3_create_qp_gsi + Input : struct roce3_device *rdev + struct ib_pd *ibpd + struct ib_qp_init_attr *init_attr + Output : None + + 1.Date : 2017/04/27 + Modification : Created function + +**************************************************************************** */ +#if defined(OFED_MLNX_5_8) +static int roce3_create_qp_gsi(struct roce3_device *rdev, struct ib_pd *ibpd, + struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr) +{ + int ret; + + mutex_init(&rqp->mutex); + /*lint -e708*/ + spin_lock_init(&rqp->sq.lock); + spin_lock_init(&rqp->rq.lock); + /*lint +e708*/ + rqp->qp_state = (u8)IB_QPS_RESET; + rqp->qp_type = init_attr->qp_type; + rqp->sq_signal_bits = (u32)(init_attr->sq_sig_type == IB_SIGNAL_ALL_WR); + rqp->has_rq = !init_attr->srq; + + ret = roce3_set_rq_size(rdev, rqp, init_attr, false, rqp->has_rq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set rq size, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + ret = roce3_create_qp_kernel(rdev, init_attr, rqp, ROCE_QP_GSI_QP_NUM); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp kernel, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + rqp->qpn = ROCE_QP_GSI_QP_NUM; + + roce3_init_qp_state(rqp, rdev); + roce3_qp_add_cq_list(init_attr, rqp, rdev); + + return 0; +} +#else +static struct roce3_qp *roce3_create_qp_gsi(struct roce3_device *rdev, struct ib_pd *ibpd, + struct ib_qp_init_attr *init_attr) +{ + int ret; + struct roce3_qp *rqp = NULL; + struct roce3_sqp *sqp = NULL; + + sqp = (struct roce3_sqp *)kzalloc(sizeof(struct roce3_sqp), GFP_KERNEL); + if (sqp == NULL) { + pr_err("[ROCE, ERR] %s: Failed to alloc sqp\n", __func__); + return (struct roce3_qp *)ERR_PTR((long)-ENOMEM); + } + + rqp = &sqp->qp; + + mutex_init(&rqp->mutex); + /*lint -e708*/ + spin_lock_init(&rqp->sq.lock); + spin_lock_init(&rqp->rq.lock); + /*lint +e708*/ + rqp->qp_state = (u8)IB_QPS_RESET; + rqp->qp_type = init_attr->qp_type; + rqp->sq_signal_bits = (u32)(init_attr->sq_sig_type == IB_SIGNAL_ALL_WR); + rqp->has_rq = !init_attr->srq; + + ret = roce3_set_rq_size(rdev, rqp, init_attr, false, rqp->has_rq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set rq size, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_out; + } + + ret = roce3_create_qp_kernel(rdev, init_attr, rqp, ROCE_QP_GSI_QP_NUM); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp kernel, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + + rqp->qpn = ROCE_QP_GSI_QP_NUM; + + roce3_init_qp_state(rqp, rdev); + roce3_qp_add_cq_list(init_attr, rqp, rdev); + + return rqp; + +err_out: + kfree(sqp); + + return (struct roce3_qp *)ERR_PTR((long)ret); +} +#endif + +static int roce3_create_check_init_attr(const struct ib_pd *ibpd, const struct ib_qp_init_attr *init_attr, + const struct ib_udata *udata) +{ + if (init_attr == NULL) { + pr_err("[ROCE, ERR] %s: init_attr is null\n", __func__); + return (-EINVAL); + } + + if ((ibpd == NULL) && (init_attr->qp_type != IB_QPT_XRC_TGT)) { + pr_err("[ROCE, ERR] %s: Ibpd is null and qp_type is not IB_QPT_XRC_TGT\n", __func__); + return (-EINVAL); + } + + if ((udata) && (init_attr->qp_type == IB_QPT_GSI)) { + pr_err("[ROCE, ERR] %s: Udata is not null and qp_type is IB_QPT_GSI\n", __func__); + return (-EINVAL); + } + + return 0; +} + +static int roce3_set_qp_attr(struct ib_qp_init_attr *init_attr, struct roce3_qp *rqp, struct roce3_device *rdev, + struct ib_pd **ibpd, int qp_ext) +{ + u16 xrcdn = 0; + + rqp->qp_ext = (u8)qp_ext; + if (init_attr->qp_type == IB_QPT_XRC_TGT) { + *ibpd = to_roce3_xrcd(init_attr->xrcd)->pd; + xrcdn = (u16)to_roce3_xrcd(init_attr->xrcd)->xrcdn; + init_attr->send_cq = to_roce3_xrcd(init_attr->xrcd)->cq; + init_attr->recv_cq = init_attr->send_cq; + + rqp->has_rq = false; + rqp->xrcdn = xrcdn; + } else if ((init_attr->qp_type == IB_QPT_XRC_INI) && roce3_is_roceaa(rdev->cfg_info.scence_id)) { + init_attr->recv_cq = init_attr->send_cq; + rqp->has_rq = false; + } else if (init_attr->qp_type == IB_QPT_XRC_INI) { + init_attr->recv_cq = init_attr->send_cq; + rqp->has_rq = false; + if (rdev->is_vroce) { + rqp->sl = rdev->group_xrc_cos; + } + } else if ((init_attr->qp_type == IB_QPT_RC) || (init_attr->qp_type == IB_QPT_UC) || + (init_attr->qp_type == IB_QPT_UD)) { + rqp->has_rq = !init_attr->srq; + if (init_attr->qp_type == IB_QPT_RC && rdev->is_vroce) { + rqp->sl = rdev->group_rc_cos; + } else if (rdev->is_vroce) { + rqp->sl = rdev->group_ud_cos; + } + } else { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Unknow QP Type(%u), func_id(%d)\n", __func__, init_attr->qp_type, + rdev->glb_func_id); + return (-EINVAL); + } + return 0; +} + +#if defined(OFED_MLNX_5_8) +static int roce3_create_gsi_qp_result(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, + struct roce3_qp *rqp, struct roce3_device *rdev) +{ + int ret; + + ret = roce3_create_qp_gsi(rdev, ibpd, rqp, init_attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp gsi, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ret; + } + + rqp->ibqp.qp_num = rqp->qpn; + + return 0; +} + +int roce3_create_qp_common(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata, + struct roce3_qp *rqp, int qp_ext) +{ + int ret = 0; + struct ib_device *ibdev = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_create_check_init_attr(ibpd, init_attr, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check init attr\n", __func__); + return ret; + } + + ibdev = ibpd ? ibpd->device : init_attr->xrcd->device; + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if (init_attr->qp_type == IB_QPT_GSI) { + return roce3_create_gsi_qp_result(ibpd, init_attr, rqp, rdev); + } + + ret = roce3_set_qp_attr(init_attr, rqp, rdev, &ibpd, qp_ext); + if (ret != 0) { + return ret; + } + + ret = roce3_do_create_qp(rdev, rqp, ibpd, init_attr, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp in common process, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + roce3_set_qp_dif_attr(rqp, init_attr, rdev); + rqp->ibqp.qp_num = rqp->qpn; + rqp->rsp_depth = 0; + + mutex_lock(&rdev->qp_cnt.cur_qps_mutex); + rdev->qp_cnt.alloc_qp_cnt++; + mutex_unlock(&rdev->qp_cnt.cur_qps_mutex); + + return 0; +} + +int roce3_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *qp_init_attr, struct ib_udata *udata) +{ + struct roce3_qp *rqp = to_roce3_qp(qp); + return roce3_create_qp_common(qp->pd, qp_init_attr, udata, rqp, ROCE_QP); +} +#else +static struct ib_qp *roce3_create_gsi_qp_result(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, + struct roce3_device *rdev) +{ + int ret; + struct roce3_qp *rqp = NULL; + + rqp = roce3_create_qp_gsi(rdev, ibpd, init_attr); + if (IS_ERR(rqp)) { + ret = (int)PTR_ERR(rqp); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp gsi, func_id(%d)\n", __func__, rdev->glb_func_id); + return (struct ib_qp *)ERR_PTR((long)ret); + } + + rqp->ibqp.qp_num = rqp->qpn; + return &rqp->ibqp; +} + +struct ib_qp *roce3_create_qp_common(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata, + int qp_ext) +{ + int ret = 0; + struct roce3_qp *rqp = NULL; + struct ib_device *ibdev = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_create_check_init_attr(ibpd, init_attr, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check init attr\n", __func__); + return (struct ib_qp *)ERR_PTR((long)ret); + } + + ibdev = ibpd ? ibpd->device : init_attr->xrcd->device; + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return (struct ib_qp *)ERR_PTR((long)-EPERM); + } + + if (init_attr->qp_type == IB_QPT_GSI) { + return roce3_create_gsi_qp_result(ibpd, init_attr, rdev); + } + + rqp = (struct roce3_qp *)kzalloc(sizeof(*rqp), GFP_KERNEL); + if (rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rqp, func_id(%d)\n", __func__, rdev->glb_func_id); + return (struct ib_qp *)ERR_PTR((long)-ENOMEM); + } + + ret = roce3_set_qp_attr(init_attr, rqp, rdev, &ibpd, qp_ext); + if (ret != 0) { + goto err_create_qp; + } + + ret = roce3_do_create_qp(rdev, rqp, ibpd, init_attr, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create qp in common process, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_create_qp; + } + + roce3_set_qp_dif_attr(rqp, init_attr, rdev); + rqp->ibqp.qp_num = rqp->qpn; + rqp->rsp_depth = 0; + + mutex_lock(&rdev->qp_cnt.cur_qps_mutex); + rdev->qp_cnt.alloc_qp_cnt++; + mutex_unlock(&rdev->qp_cnt.cur_qps_mutex); + + return &rqp->ibqp; + +err_create_qp: + kfree(rqp); + + return (struct ib_qp *)ERR_PTR((long)ret); +} + +struct ib_qp *roce3_create_qp(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata) +{ + return roce3_create_qp_common(ibpd, init_attr, udata, ROCE_QP); +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_destroy.c b/drivers/infiniband/hw/hiroce3/qp/roce_qp_destroy.c new file mode 100644 index 000000000..f0b5bcfdb --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_destroy.c @@ -0,0 +1,289 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_destroy.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/20 + * Description : Define standard kernel RoCE QP destroy realted functions. + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include <rdma/ib_verbs.h> + +#include "roce_compat.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_mr.h" +#include "roce_xrc.h" +#include "roce_pd.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_qp.h" +#ifdef __ROCE_DFX__ +#include "roce_dfx.h" +#endif +#include "hinic3_hmm.h" + +#ifdef ROCE_VBS_EN +#include "roce_vbs_qp.h" +#endif + +static void roce3_clean_qp_user(struct roce3_device *rdev, struct roce3_qp *rqp, + struct roce3_ucontext *ucontext) +{ + roce3_free_opt_rdmarc(rqp); + + hiudk_cqm_object_delete(rdev->hwdev, &(rqp->qpc_info->object)); + +#ifdef ROCE_VBS_EN + if (rqp->vbs_qp_ptr) { + roce3_vbs_destroy_sqpc(rdev->hwdev, rqp); + } +#endif + + if (rqp->qp_type != IB_QPT_XRC_TGT) { + roce3_db_unmap_user(ucontext, &rqp->db); + } + + hmm_rdma_mtt_free(rdev->hwdev, &rqp->mtt, SERVICE_T_ROCE); + + ib_umem_release(rqp->umem); +} + +/* **************************************************************************** + Prototype : roce3_cq_clean_process + Description : roce3_cq_clean_process + Input : struct roce3_cq *cq + u32 qpn + struct roce3_srq *srq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_clean_process(struct roce3_cq *cq, u32 qpn, struct roce3_srq *srq) +{ + u32 prod_index = 0; + int nfreed = 0; + struct roce_cqe *cqe = NULL; + struct roce_cqe *dest = NULL; + u8 owner_bit = 0; + + /* + * First we need to find the current producer index, so we + * know where to start cleaning from. It doesn't matter if HW + * adds new entries after this loop -- the QP we're worried + * about is already in RESET, so the new entries won't come + * from our QP and therefore don't need to be checked. + */ + for (prod_index = cq->cons_index; roce3_get_sw_cqe(cq, prod_index); ++prod_index) { + if (prod_index == (u32)((int)cq->cons_index + cq->ibcq.cqe)) { + break; + } + } + + /* + * Now sweep backwards through the CQ, removing CQ entries + * that match our QP by copying older entries on top of them. + */ + /* xcqe:qpn's cqe. + CI + +--------+------+------+------+----------+ + b4_clean: | | cqe1 | xcqe2| cqe3 | | + +--------+------+------+------+----------+ + \ + \ + +---------------+------+------+----------+ + af_clean: | | cqe1 | cqe3 | | + +---------------+------+------+----------+ + */ + while ((int)--prod_index - (int)cq->cons_index >= 0) { + cqe = (struct roce_cqe *)roce3_get_cqe(cq, prod_index & (u32)cq->ibcq.cqe); + + cqe->dw0.value = roce3_convert_cpu32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_cpu32(cqe->dw1.value); + cqe->dw7.value = roce3_convert_cpu32(cqe->dw7.value); + + if (cqe->dw0.bs.qpn == qpn) { + if (srq && (cqe->dw1.bs.s_r == ROCE_CQE_RECV_COMP)) { + roce3_free_srq_wqe(srq, cqe->dw7.bs.wqe_cnt); + } + + ++nfreed; + } else if (nfreed != 0) { + dest = (struct roce_cqe *)roce3_get_cqe(cq, + (unsigned int)((int)prod_index + nfreed) & (unsigned int)cq->ibcq.cqe); + dest->dw0.value = roce3_convert_cpu32(dest->dw0.value); + owner_bit = dest->dw0.bs.owner; + memcpy((void *)dest, (void *)cqe, sizeof(struct roce_cqe)); + dest->dw0.bs.owner = owner_bit; + dest->dw0.value = roce3_convert_be32(dest->dw0.value); + dest->dw1.value = roce3_convert_be32(dest->dw1.value); + dest->dw7.value = roce3_convert_be32(dest->dw7.value); + } else { + pr_info("[ROCE] %s: Nothing need to do\n", __func__); + } + + cqe->dw0.value = roce3_convert_be32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_be32(cqe->dw1.value); + cqe->dw7.value = roce3_convert_be32(cqe->dw7.value); + } + + if (nfreed != 0) { + cq->cons_index += (u32)nfreed; + /* + * Make sure update of buffer contents is done before + * updating consumer index. + */ + wmb(); + + roce3_cq_set_ci(cq); + } +} + +/* **************************************************************************** + Prototype : roce3_clean_qp_kernel + Description : roce3_clean_qp_kernel + Input : struct roce3_device *rdev + struct roce3_qp *rqp + Output : None + + 1.Date : 2017/04/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_clean_qp_kernel(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + struct roce3_cq *send_cq = NULL; + struct roce3_cq *recv_cq = NULL; + unsigned long flags; + + roce3_free_opt_rdmarc(rqp); + + roce3_get_cqs(rqp, &send_cq, &recv_cq); + + spin_lock_irqsave(&rdev->reset_flow_resource_lock, flags); + roce3_lock_cqs(send_cq, recv_cq); + /* del from lists under both locks above to protect reset flow paths */ + list_del(&rqp->qps_list); + list_del(&rqp->cq_send_list); + list_del(&rqp->cq_recv_list); + + roce3_cq_clean_process(recv_cq, rqp->qpn, rqp->ibqp.srq ? to_roce3_srq(rqp->ibqp.srq) : NULL); + + if (send_cq != recv_cq) { + roce3_cq_clean_process(send_cq, rqp->qpn, NULL); + } + + roce3_unlock_cqs(send_cq, recv_cq); + spin_unlock_irqrestore(&rdev->reset_flow_resource_lock, flags); + + hiudk_cqm_object_delete(rdev->hwdev, &(rqp->qpc_info->object)); + + if (rqp->sq.wrid) { + kvfree(rqp->sq.wrid); + rqp->sq.wrid = NULL; + } + + if (rqp->rq.wrid) { + kvfree(rqp->rq.wrid); + rqp->rq.wrid = NULL; + } + + if (rqp->qp_type != IB_QPT_XRC_TGT) { + hiudk_cqm_object_delete(rdev->hwdev, &(rqp->qp_buf_info->object)); + } + + hmm_rdma_mtt_free(rdev->hwdev, &rqp->mtt, SERVICE_T_ROCE); +} + +static int roce3_qp_destroy(struct roce3_qp *rqp, struct roce3_device *rdev) +{ + int ret = 0; + + ret = roce3_qp_modify_2rst_cmd(rdev, rqp->qpn); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify QP(0x%06x) to RESET, func_id(%d)\n", __func__, + rqp->qpn, rdev->glb_func_id); + return ret; + } + + ret = roce3_qp_cache_out_cmd(rdev, rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: QP(0x%06x) cache invalid, func_id(%d)\n", __func__, rqp->qpn, + rdev->glb_func_id); + return ret; + } + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) +#else +int roce3_destroy_qp(struct ib_qp *ibqp) +#endif +{ + int ret = 0; + struct roce3_qp *rqp = NULL; + struct roce3_device *rdev = NULL; +#if !defined(OFED_MLNX_5_8) + struct roce3_sqp *rsqp = NULL; +#endif + struct roce3_ucontext *ucontext = NULL; + + if (ibqp == NULL) { + pr_err("[ROCE, ERR] %s: Ibqp is null\n", __func__); + return -EINVAL; + } + + rqp = to_roce3_qp(ibqp); + rdev = to_roce3_dev(ibqp->device); + + if (rqp->qp_state != IB_QPS_RESET) { + ret = roce3_qp_destroy(rqp, rdev); + if (ret != 0) { + return ret; + } + + rqp->qp_state = IB_QPS_RESET; + } + + if (ibqp->uobject) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + ucontext = rdma_udata_to_drv_context(udata, struct roce3_ucontext, ibucontext); +#else + ucontext = to_roce3_ucontext(ibqp->uobject->context); +#endif + roce3_clean_qp_user(rdev, rqp, ucontext); +#if !defined(OFED_MLNX_5_8) + kfree(rqp); +#endif + goto out; + } + + roce3_clean_qp_kernel(rdev, rqp); +#if !defined(OFED_MLNX_5_8) + if (roce3_sqp_check(rqp) != 0) { + rsqp = to_roce3_sqp(rqp); + kfree(rsqp); + + goto out; + } + + kfree(rqp); +#endif +out: + mutex_lock(&rdev->qp_cnt.cur_qps_mutex); + rdev->qp_cnt.del_qp_cnt++; + mutex_unlock(&rdev->qp_cnt.cur_qps_mutex); + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_exp.h b/drivers/infiniband/hw/hiroce3/qp/roce_qp_exp.h new file mode 100644 index 000000000..c18aab654 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_exp.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_exp.h + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/20 + * Description : The definition of RoCE QP expanded function prototype, macros etc,. in kernel space. + */ + +#ifndef ROCE_QP_EXP_H +#define ROCE_QP_EXP_H + +#include <linux/io-mapping.h> +#include <linux/list.h> +#include <linux/cdev.h> + +#include <rdma/ib_verbs.h> + +#include "hinic3_rdma.h" +#include "hinic3_cqm.h" + +#include "rdma_context_format.h" + +#include "roce.h" +#include "roce_db.h" +#include "roce_cq.h" +#include "roce_qp.h" + +#define EXP_OK (0) +#define EXP_PARAM_ERR (1) +#define EXP_FUNC_ERR (2) + +#define QPC_MIN_SIZE (512) +#define CONTX_SZ (sizeof(struct roce_qp_context) / QPC_MIN_SIZE) + +#define BUFFER_SZ (sizeof(struct roce_qp_context) / sizeof(u32)) + +#define TYPE_LEN (8) +#define DEV_NUM (32) +#define QPN_MAX (0xFFFFF) +#define QPN_MIN (0) +#define IB_QP_EXP_CMD (1 << 23) +#define ROCE_OPTPAR_EXP (1 << 16) +#define VA_OFFSET (8) + +struct roce3_device_list { + struct ib_device *ib_dev[DEV_NUM]; + int ib_dev_num; + struct mutex mutex; +}; + +struct ib_qp_info { + dma_addr_t sq_pg_base_addr[64]; + dma_addr_t hw_doorbell_addr; + dma_addr_t sw_doorbell_addr; + + u32 sq_depth; + u32 qpn; + u8 sq_pg_cnt; + u8 qp_cos; + u8 cntx_sz; + u8 sq_wqe_size; +}; + +struct ib_qp_attr_data { + u32 data_type; // plog:1 + u32 data_len; + u8 *data_buf; +}; + +struct ib_qp_attr_exp { + struct ib_qp_attr qp_attr; + struct ib_qp_attr_data qp_attr_data; +}; + +struct roce3_device_list *roce3_get_plog_device_info(void); + +int ib_get_qp_info(char *dev_name, int qpn, struct ib_qp_info *qp_info); +struct ib_qp *ib_get_qp(const char *dev_name, int qpn); +int ib_put_qp(struct ib_qp *ibqp); +int roce3_qp_modify_exp(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, + enum ib_qp_state cur_state, enum ib_qp_state new_state, u16 vlan_id); +int roce3_modify_extend_qp(struct ib_qp_attr *attr, int attr_mask, struct ib_qp *ibqp); + +#endif // ROCE_QP_EXP_H diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_modify.c b/drivers/infiniband/hw/hiroce3/qp/roce_qp_modify.c new file mode 100755 index 000000000..25b154ecf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_modify.c @@ -0,0 +1,2162 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_modify.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/20 + * Description : Define standard kernel RoCE QP realted functions. + */ + +#include <rdma/ib_verbs.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include "roce_compat.h" +#include "hinic3_srv_nic.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_mr.h" +#include "roce_user.h" +#include "roce_xrc.h" +#include "roce_pd.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_qp.h" +#include "roce_qp_exp.h" +#include "roce_qp_extension.h" +#include "roce_main_extension.h" +#include "roce_pub_cmd.h" +#include "roce_verbs_attr.h" +#include "roce_verbs_ext_attr.h" +#include "rdma_context_format.h" + +#ifdef ROCE_VBS_EN +#include "roce_vbs_qp.h" +#endif + +#ifdef ROCE_ANTI_ATTACK +#include "roce_anti_attack.h" +#include "roce_cmd.h" +#endif + +#ifdef __ROCE_DFX__ +#include "roce_dfx.h" +#endif + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#define ROCE_MTT_GPA_VALID 0x1 +#define ROCE_WQE_PREFETCH_MAXNUM 4 +#define ROCE_SQ_WQEBB_SIZE_SHIFT 4 +#define ROCE_SQ_WQEBB_SIZE_MASK 0x7 +#define ROCE_SQ_PD_MASK 0x3ffff +#define ROCE_SQ_PAGE_SIZE_MASK 0xf +#define ROCE_SQ_WQECNT_LTH 4 +#define ROCE_SQ_PREFETCH_MINNUM 2 +#define ROCE_SQ_PREFETCH_MAXNUM 4 +#define ROCE_SQ_SIZE_MASK 0x1f +#define ROCE_SQ_CQN_MASK 0xfffff +#define ROCE_RQ_WQECNT_LTH 0xe +#define ROCE_RQ_MTT_PREFETCH_MAXLEN0 3 +#define ROCE_RQ_MTT_PREFETCH_MAXWQE 7 +#define ROCE_RQ_WQE_PREFETCH_MAXNUM 7 +#define ROCE_SRQ_INIT_STATE 0xf +#define ROCE_MAX_PI_ON_CHIP_QPN 1024 + +enum { + ROCE_IPSUTX_CHANNEL_5 = 0x0, /* 00 */ + ROCE_IPSUTX_CHANNEL_10 = 0x1, /* 01 */ + ROCE_IPSUTX_CHANNEL_15 = 0x2, /* 10 */ + ROCE_IPSUTX_CHANNEL_20 = 0x3, /* 01 */ +}; + +enum { + BIT_LENGTH_IB_MTU_256 = 8, + BIT_LENGTH_IB_MTU_512, + BIT_LENGTH_IB_MTU_1024, + BIT_LENGTH_IB_MTU_2048, + BIT_LENGTH_IB_MTU_4096 +}; + +enum { + CACHE_INVLAID_ALLOC, + CACHE_INVLAID_CMDQ, + CACHE_INVLAID_RDMARC_CHECK, + CACHE_INVLAID_QP_CHECK, + MODIFY_2RST_CMDQ, + CMDQ_SDKCALL_BUTT +}; + +#define ROCE_CMDQ_TIMEOUT 1000 +#define ROCE_CMDQ_TIMEOUT_10MS 10 + + +#ifdef ROCE_COMPUTE +static int g_sq_cqn_lb = 0; +module_param(g_sq_cqn_lb, int, 0444); //lint !e806 +MODULE_PARM_DESC(g_sq_cqn_lb, "default: 0"); + +static int g_rq_cqn_lb = 0; +module_param(g_rq_cqn_lb, int, 0444); //lint !e806 +MODULE_PARM_DESC(g_rq_cqn_lb, "default: 0"); +#else +static int g_sq_cqn_lb = 1; +module_param(g_sq_cqn_lb, int, 0444); //lint !e806 +MODULE_PARM_DESC(g_sq_cqn_lb, "default: 1"); + +static int g_rq_cqn_lb = 1; +module_param(g_rq_cqn_lb, int, 0444); //lint !e806 +MODULE_PARM_DESC(g_rq_cqn_lb, "default: 1"); +#endif + +static void roce3_timeout_check(struct roce3_device *rdev, const struct timespec64 *tv_start, + int func_id, int times) +{ + uint64_t cost; + struct timespec64 delta; + struct timespec64 tv_end = { 0 }; + + ktime_get_ts64(&tv_end); + delta = timespec64_sub(tv_end, *tv_start); + cost = delta.tv_sec * USEC_PER_SEC + delta.tv_nsec / NSEC_PER_USEC; + + if (cost >= ROCE_CMDQ_TIMEOUT) { + dev_warn_ratelimited(rdev->hwdev_hdl, "[ROCE, WARN] %s:destroy qp exec too long, func_id(%d), cost(%llu),\ + times:%d\n", __func__, func_id, cost, times); + } + return; +} + +#ifdef ROCE_SIGN_EN +enum mtt_check_type_e { + MTT_CHECK_TYPE_0 = 0, + MTT_CHECK_TYPE_1 +}; + +#define ROCE_QP_QPCC_SIGN_WIDTH 5 +#define ROCE_QP_QPCC_SIGN_SPLITNUM 4 +#define ROCE_QP_QPCC_SIGN_CHECKBITS (ROCE_QP_QPCC_SIGN_WIDTH * ROCE_QP_QPCC_SIGN_SPLITNUM) + +#define ROCE_QP_SUB_SIGN_WIDTH 3 +#define ROCE_QP_SUB_SIGN_SPLITNUM 5 +#define ROCE_QP_SUB_SIGN_CHECKBITS (ROCE_QP_SUB_SIGN_WIDTH * ROCE_QP_SUB_SIGN_SPLITNUM) + +#define ROCE_QP_GPA_SIGN_WIDTH 3 +#define ROCE_QP_GPA_SIGN_SPLITNUM 11 +#define ROCE_QP_GPA_SIGN_CHECKBITS (ROCE_QP_GPA_SIGN_WIDTH * ROCE_QP_GPA_SIGN_SPLITNUM) + +#define ROCE_SQ_WQE_SIGN_WIDTH 8 +#define ROCE_SQ_WQE_SIGN_SPLITNUM 9 +#define ROCE_SQ_WQE_SIGN_CHECKBITS_1 32 +#define ROCE_SQ_WQE_SIGN_CHECKBITS_2 20 +#define ROCE_SQ_WQE_SIGN_CHECKBITS_12 (ROCE_SQ_WQE_SIGN_CHECKBITS_2 + ROCE_SQ_WQE_SIGN_CHECKBITS_1) +#define ROCE_SQ_WQE_SIGN_CHECKBITS_3 20 +#define ROCE_SQ_WQE_SIGN_CHECKBITS_123 (ROCE_SQ_WQE_SIGN_CHECKBITS_3 + ROCE_SQ_WQE_SIGN_CHECKBITS_12) +#define ROCE_SQ_WQE_SIGN_CHECKBITS (ROCE_SQ_WQE_SIGN_WIDTH * ROCE_SQ_WQE_SIGN_SPLITNUM) + +#define ROCE_MTT_SIGN_WIDTH 11 +#define ROCE_MTT_SIGN_SPLITNUM 5 +#define ROCE_MTT_SIGN_CHECKBITS_1 22 +#define ROCE_MTT_SIGN_CHECKBITS_2 33 +#define ROCE_MTT_SIGN_CHECKBITS_12 (ROCE_MTT_SIGN_CHECKBITS_1 + ROCE_MTT_SIGN_CHECKBITS_2) +#define ROCE_MTT_SIGN_CHECKBITS (ROCE_MTT_SIGN_WIDTH * ROCE_MTT_SIGN_SPLITNUM) + +#define ROCE_MTT_BLOCK_SIGN_WIDTH 5 +#define ROCE_MTT_BLOCK_SIGN_SPLITNUM 11 + +/* **************************************************************************** + Prototype : roce3_caculate_sign_bit + Description : roce3_caculate_signature + Input : u32 *check_bit + u32 sign_width + u32 sign_split + u32 *sign_bit + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static void roce3_caculate_sign_bit(u32 *check_bit, u32 sign_width, u32 sign_split, u32 *sign_bit) +{ + u32 i = 0; + u32 j = 0; + + for (i = 0; i < sign_width; i++) { + sign_bit[i] = 0; + for (j = 0; j < sign_split; j++) { + sign_bit[i] = sign_bit[i] ^ check_bit[i + sign_width * j]; + } + + sign_bit[i] = (~sign_bit[i]) & 0x1; + } +} + +/* **************************************************************************** + Prototype : roce3_caculate_signature + Description : roce3_caculate_signature + Input : u32 *sign_bit + u32 sign_width + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_caculate_signature(u32 *sign_bit, u32 sign_width) +{ + u32 i = 0; + u32 signature = 0; + + for (i = 0; i < sign_width; i++) { + signature |= sign_bit[i] << i; + } + + return (signature & ((1U << sign_width) - 1)); +} + +/* **************************************************************************** + Prototype : roce3_gen_sq_rq_gpa_sign + Description : Signature 3bit + CheckedBits = sq_rq_l0mtt_gpa[32:00] + Input : u64 sq_rq_l0mtt_gpa + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_sq_rq_gpa_sign(u64 sq_rq_l0mtt_gpa) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_GPA_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_GPA_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_GPA_SIGN_CHECKBITS; i++) { + if ((sq_rq_l0mtt_gpa >> ROCE_QP_GPA_SIG_LEN) & (1ULL << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_GPA_SIGN_WIDTH, ROCE_QP_GPA_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_GPA_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_qp_qpcc_sign + Description : Signature 5bit + CheckedBits = QPn[19:0] + Input : u32 qpn + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_qp_qpcc_sign(u32 qpn) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_QPCC_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_QPCC_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_QPCC_SIGN_CHECKBITS; i++) { + if (qpn & (1U << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_QPCC_SIGN_WIDTH, ROCE_QP_QPCC_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_QPCC_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_qp_rcc_sign + Description : Signature 3bit + CheckedBits = QPn[14:0] + Input : u32 qpn + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_qp_rcc_sign(u32 qpn) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_SUB_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_SUB_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_SUB_SIGN_CHECKBITS; i++) { + if (qpn & (1U << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_SUB_SIGN_WIDTH, ROCE_QP_SUB_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_SUB_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_qp_sqc_sign + Description : Signature 3bit + CheckedBits = QPn[14:0] + Input : u32 qpn + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_qp_sqc_sign(u32 qpn) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_SUB_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_SUB_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_SUB_SIGN_CHECKBITS; i++) { + if (qpn & (1U << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_SUB_SIGN_WIDTH, ROCE_QP_SUB_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_SUB_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_qp_sqac_sign + Description : Signature 3bit + CheckedBits = QPn[14:0] + Input : u32 qpn + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_qp_sqac_sign(u32 qpn) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_SUB_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_SUB_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_SUB_SIGN_CHECKBITS; i++) { + if (qpn & (1U << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_SUB_SIGN_WIDTH, ROCE_QP_SUB_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_SUB_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_qp_rqc_sign + Description : Signature 3bit + CheckedBits = QPn[14:0] + Input : u32 qpn + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_qp_rqc_sign(u32 qpn) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_SUB_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_SUB_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_SUB_SIGN_CHECKBITS; i++) { + if (qpn & (1U << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_SUB_SIGN_WIDTH, ROCE_QP_SUB_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_SUB_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_qp_rrwc_sign + Description : Signature 3bit + CheckedBits = QPn[14:0] + Input : u32 qpn + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_qp_rrwc_sign(u32 qpn) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_QP_SUB_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_QP_SUB_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_QP_SUB_SIGN_CHECKBITS; i++) { + if (qpn & (1U << i)) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_QP_SUB_SIGN_WIDTH, ROCE_QP_SUB_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_QP_SUB_SIGN_WIDTH); + + return signature; +} + +/* **************************************************************************** + Prototype : roce3_gen_sq_wqe_sign + Description : Signature 8bit + CheckedBits = {QPn[19:0], WQECI[19:0], WQE.Header[31:0]} + Input : u32 qpn + u32 wqe_ci + u32 wqe_header + Output : None + + 1.Date : 2017/4/1 + Modification : Created function + +**************************************************************************** */ +static u32 roce3_gen_sq_wqe_sign(u32 qpn, u32 wqe_ci, u32 wqe_header) +{ + u32 i; + u32 signature = 0; + u32 sign_bit[ROCE_SQ_WQE_SIGN_WIDTH] = {0}; + u32 check_bit[ROCE_SQ_WQE_SIGN_CHECKBITS] = {0}; + + for (i = 0; i < ROCE_SQ_WQE_SIGN_CHECKBITS_1; i++) { + if (wqe_header & (1U << i)) { + check_bit[i] = 1; + } + } + + for (i = ROCE_SQ_WQE_SIGN_CHECKBITS_1; i < ROCE_SQ_WQE_SIGN_CHECKBITS_12; i++) { + if (wqe_ci & (1U << (i - ROCE_SQ_WQE_SIGN_CHECKBITS_1))) { + check_bit[i] = 1; + } + } + + for (i = ROCE_SQ_WQE_SIGN_CHECKBITS_12; i < ROCE_SQ_WQE_SIGN_CHECKBITS_123; i++) { + if (qpn & (1U << (i - ROCE_SQ_WQE_SIGN_CHECKBITS_12))) { + check_bit[i] = 1; + } + } + + roce3_caculate_sign_bit(check_bit, ROCE_SQ_WQE_SIGN_WIDTH, ROCE_SQ_WQE_SIGN_SPLITNUM, sign_bit); + + signature = roce3_caculate_signature(sign_bit, ROCE_SQ_WQE_SIGN_WIDTH); + + return signature; +} +#endif + +static void roce3_qp_set_path(const struct roce3_device *rdev, struct rdma_ah_attr *ah_attr, + roce_verbs_qpc_attr_path_s *path_info) +{ + u8 *dmac = ah_attr->roce.dmac; + + path_info->dw7.bs.hoplmt = (u8)ah_attr->grh.hop_limit; + path_info->dw6.bs.tclass = (u8)(ah_attr->grh.traffic_class | 0x2); + path_info->dw6.bs.flow_label = ah_attr->grh.flow_label & 0xfffff; /* flow_label: 20bit */ + path_info->dw7.bs.sgid_index = ah_attr->grh.sgid_index & 0x7f; /* sgid_index: 7bit */ + + path_info->dw7.bs.base_sgid_n = (path_info->dw7.bs.sgid_index != ROCE_BASE_GID_IDX); + + memcpy((void *)path_info->dgid, (void *)ah_attr->grh.dgid.raw, + sizeof(path_info->dgid)); + + memcpy((void *)&path_info->dmac_l32, (void *)&dmac[ROCE_RAH_DMAC_L32_START], + sizeof(path_info->dmac_l32)); + path_info->dmac_l32 = cpu_to_be32(path_info->dmac_l32); + path_info->dw0.bs.dmac_h16 = (dmac[0] << ROCE_RAH_DMAC_H16_SHIFT) | dmac[1]; // shift dmac[0] left by 8 bits + path_info->dw7.bs.sl = (ah_attr->sl & 0x7); /* sl: 3bit */ +} + +struct roce3_pd *roce3_get_pd(struct roce3_qp *rqp) +{ + if (rqp->qp_type == IB_QPT_XRC_TGT) { + return to_roce3_pd(to_roce3_xrcd(rqp->ibqp.xrcd)->pd); + } else { + return to_roce3_pd(rqp->ibqp.pd); + } +} + +void roce3_get_cqs(struct roce3_qp *rqp, struct roce3_cq **send_cq, struct roce3_cq **recv_cq) +{ + switch (rqp->qp_type) { + case IB_QPT_XRC_TGT: + *send_cq = to_roce3_cq(to_roce3_xrcd(rqp->ibqp.xrcd)->cq); + *recv_cq = *send_cq; + break; + + case IB_QPT_XRC_INI: + *send_cq = to_roce3_cq(rqp->ibqp.send_cq); + *recv_cq = *send_cq; + break; + + default: + *send_cq = to_roce3_cq(rqp->ibqp.send_cq); + *recv_cq = to_roce3_cq(rqp->ibqp.recv_cq); + break; + } +} + +/* **************************************************************************** + Prototype : roce3_set_access_flags + Description : roce3_set_access_flags + Input : struct roce3_qp *rqp + roce_verbs_qp_attr_s *qp_attr + struct ib_qp_attr *attr + int attr_mask + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + 2.Date : 2016/2/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_access_flags(struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr, struct ib_qp_attr *attr, + int attr_mask) +{ + u16 dest_rd_atomic = 0; + u32 access_flags = 0; + + if ((((u32)attr_mask) & IB_QP_MAX_DEST_RD_ATOMIC) != 0) { + dest_rd_atomic = attr->max_dest_rd_atomic; + } else { + dest_rd_atomic = rqp->rsp_depth; + } + + if ((((u32)attr_mask) & IB_QP_ACCESS_FLAGS) != 0) { + access_flags = (u32)attr->qp_access_flags; + } else { + access_flags = rqp->atomic_rd_en; + } + + if (dest_rd_atomic == 0) { + access_flags &= IB_ACCESS_REMOTE_WRITE; + } + + if ((access_flags & IB_ACCESS_REMOTE_READ) != 0) { + qp_attr->com_info.dw0.bs.rre = 1; /* rc_rre: 1bits */ + } + + if ((access_flags & IB_ACCESS_REMOTE_ATOMIC) != 0) { + qp_attr->com_info.dw0.bs.rae = 1; /* rc_rae: 1bits */ + } + + if ((access_flags & IB_ACCESS_REMOTE_WRITE) != 0) { + qp_attr->com_info.dw0.bs.rwe = 1; /* rrw_rwe: 1bits */ + } +} + +int roce3_sqp_check(const struct roce3_qp *qp) +{ + if (((qp->qp_type == IB_QPT_GSI) && (qp->qpn == ROCE_QP_SMI_QP_NUM)) || (qp->qpn == ROCE_QP_GSI_QP_NUM)) { + return 1; + } + + return 0; +} + +/* **************************************************************************** + Prototype : store_sqp_attrs + Description : save the special + Input : struct roce3_sqp *sqp + const struct ib_qp_attr *attr + int attr_mask + Output : None + + 1.Date : 2015/7/24 + Modification : Created function + +**************************************************************************** */ +static void store_sqp_attrs(struct roce3_sqp *sqp, const struct ib_qp_attr *attr, int attr_mask) +{ + if (((u32)attr_mask & IB_QP_PKEY_INDEX) != 0) { + sqp->pkey_index = attr->pkey_index; + } + + if ((((u32)attr_mask) & IB_QP_QKEY) != 0) { + sqp->qkey = attr->qkey; + } + + if ((((u32)attr_mask) & IB_QP_SQ_PSN) != 0) { + sqp->send_psn = attr->sq_psn; + } +} + +/* **************************************************************************** + Prototype : qpc_seg_to_be + Input : struct roce_qp_context *be_ctx + struct roce_qp_context *le_ctx + struct roce3_qp *rqp + Output : None + + 1.Date : 2015/7/29 + Modification : Created function + +**************************************************************************** */ +static void qpc_seg_to_be(roce_verbs_qp_attr_s *be_ctx, roce_verbs_qp_attr_s *le_ctx, struct roce3_qp *rqp) +{ + /* DRV Seg */ + memcpy((void *)be_ctx->path_info.dgid, (void *)le_ctx->path_info.dgid, + sizeof(le_ctx->path_info.dgid)); + + /* CHIP Seg */ + be_ctx->chip_seg.dw0.sq_rq_l0mtt_gpa = cpu_to_be64(le_ctx->chip_seg.dw0.sq_rq_l0mtt_gpa); + + be_ctx->chip_seg.dw2.sq_rq_pi_record_gpa_at_hop_num = + cpu_to_be64(le_ctx->chip_seg.dw2.sq_rq_pi_record_gpa_at_hop_num); +} + +/* **************************************************************************** + Prototype : roce3_qpc_to_be + Description : translate big endian + Input : roce_verbs_qp_attr_s *qp_attr + struct roce3_qp *rqp + u32 *be_ctx + Output : None + + 1.Date : 2015/7/29 + Modification : Created function + +**************************************************************************** */ +void roce3_qpc_to_be(roce_verbs_qp_attr_s *qp_attr, struct roce3_qp *rqp, u32 *be_ctx) +{ + u32 *ctx = NULL; + u32 *ctx1 = NULL; + u32 i = 0; + u32 ctx_size = 0; + + ctx = be_ctx; + ctx1 = (u32 *)qp_attr; + ctx_size = sizeof(roce_verbs_qp_attr_s) / sizeof(u32); + + for (i = 0; i < ctx_size; ++i, ++ctx1, ++ctx) { + *ctx = cpu_to_be32(*ctx1); + } + + qpc_seg_to_be((roce_verbs_qp_attr_s *)((void *)be_ctx), qp_attr, rqp); +} + +/* **************************************************************************** + Prototype : roce3_alloc_opt_rdmarc + Description : alloc rdmarc when modify qp + Input : struct roce3_qp *rqp + struct ib_qp_attr *attr + int attr_mask + Output : None + + 1.Date : 2016/01/30 + Modification : Created function + +**************************************************************************** */ +static int roce3_alloc_opt_rdmarc(struct roce3_qp *rqp, const struct ib_qp_attr *attr, int attr_mask) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + u32 response_depth = 0; + + rdev = to_roce3_dev(rqp->ibqp.device); + /*lint -e587*/ + response_depth = (attr->max_dest_rd_atomic == 0) ? 1 : (u32)ROCE_ROUNDUP_POW_OF_TWO((u32)attr->max_dest_rd_atomic); + /*lint +e587*/ + if (rqp->rsp_depth != response_depth) { + if (rqp->rsp_depth > 0) { + roce3_rdma_rdmarc_free(rdev->hwdev, &rqp->rdmarc); + } + + ret = roce3_rdma_rdmarc_alloc(rdev->hwdev, response_depth, &rqp->rdmarc); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma rdmarc, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + rqp->rsp_depth = (u16)response_depth; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_free_opt_rdmarc + Description : free rdmarc when modify qp failed or destory qp + Input : struct roce3_qp *rqp + Output : None + + 1.Date : 2016/01/30 + Modification : Created function + +**************************************************************************** */ +void roce3_free_opt_rdmarc(struct roce3_qp *rqp) +{ + struct roce3_device *rdev = NULL; + + rdev = to_roce3_dev(rqp->ibqp.device); + + if (rqp->rsp_depth > 0) { + roce3_rdma_rdmarc_free(rdev->hwdev, &rqp->rdmarc); + } + + rqp->rsp_depth = 0; +} + +/* **************************************************************************** + Prototype : roce3_set_opt_rdmarc + Description : set opt rdmarc field + Input : struct roce3_device *rdev + struct roce3_qp *rqp + roce_verbs_qp_attr_s *qp_attr + Output : None + + 1.Date : 2017/04/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_opt_rdmarc(struct roce3_device *rdev, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr) +{ + qp_attr->chip_seg.dw10.bs.rc_page_gpa_h = (rqp->rdmarc.dma_addr >> 40) & 0xffffff; /* high:24bit, 64-24= 40 */ + qp_attr->chip_seg.rc_page_gpa_l = (u32)(rqp->rdmarc.dma_addr >> 8); // bit[39:8] + qp_attr->chip_seg.dw4.bs.rc_size = rqp->rdmarc.order; + qp_attr->com_info.dw1.bs.rra_max = ((u8)fls(rqp->rsp_depth - 1)) & 0x7; /* rra_max:3bit */ + qp_attr->chip_seg.dw4.bs.rc_max_size = rqp->rdmarc.ext_order - 3; +} + +static void roce3_set_opt_mtu(roce_verbs_qp_attr_s *qp_attr, const struct ib_qp_attr *attr) +{ + u32 pmtu = (u32)attr->path_mtu & 0x7; + + qp_attr->com_info.dw3.bs.pmtu = pmtu; /* 1,2,3,4,5 */ + qp_attr->com_info.dw5.bs.mtu_code = ROCE_QPC_PMTU_TRANSLATE(pmtu); /* 0,1,3,7,15 */ + if (qp_attr->com_info.dw3.bs.pmtu == IB_MTU_1024) { + qp_attr->com_info.dw3.bs.base_mtu_n = 0; + } else { + qp_attr->com_info.dw3.bs.base_mtu_n = 1; + } +} + +/* **************************************************************************** + Prototype : roce3_set_opt_sra + Description : set opt sra + Input : roce_verbs_qp_attr_s *qp_attr + struct ib_qp_attr *attr + Output : None + + 1.Date : 2017/04/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_opt_sra(roce_verbs_qp_attr_s *qp_attr, struct ib_qp_attr *attr) +{ + u8 initiator_depth; + + /*lint -e587*/ + initiator_depth = (attr->max_rd_atomic == 0) ? 1 : (u8)ROCE_ROUNDUP_POW_OF_TWO((u32)attr->max_rd_atomic); + /*lint +e587*/ + qp_attr->com_info.dw1.bs.sra_max = ((u32)ROCE_FLS(initiator_depth - 1)) & 0x7; /* sra_max:3bit */ +} + +u8 roce3_get_db_cos_from_vlan_pri(struct roce3_device *rdev, u8 vlan_pri) +{ + u8 db_cos; + int ret; + + ret = hinic3_get_cos_by_pri(rdev->hwdev, vlan_pri, &db_cos); + if (ret != 0) { + printk("roce3_get_db_cos_from_vlan_pri, ret:%d vlan_pri:%u\n", ret, vlan_pri); + db_cos = 0; + } + + return db_cos; +} + +static void roce3_set_opt_attr_av(struct roce3_qp *rqp, struct roce3_device *rdev, struct ib_qp_attr *attr, + roce_verbs_qp_attr_s *qp_attr, u32 *optpar) +{ + u8 cos; + roce3_get_cos_inbuf_s inbuf = { 0 }; + + roce3_qp_set_path(rdev, &attr->ah_attr, &qp_attr->path_info); + qp_attr->com_info.dw3.bs.ext_mtu = rqp->ext_mtu & 0x1; + qp_attr->com_info.dw3.bs.ext_md = rqp->ext_mtu_mode & 0x1; + qp_attr->com_info.dw2.bs.vroce_en = (u32)rdev->is_vroce; + *optpar |= ROCE_QP_OPTPAR_PRIMARY_ADDR_PATH; + + inbuf.sl = attr->ah_attr.sl; + inbuf.sgid_index = attr->ah_attr.grh.sgid_index; + inbuf.port_num = attr->ah_attr.port_num; + inbuf.traffic_class = attr->ah_attr.grh.traffic_class; + (void)roce3_get_dcb_cfg_cos(rdev, &inbuf, &cos); + if (rdev->is_vroce) { + cos = rqp->sl; + } + qp_attr->com_info.dw5.bs.cos = cos & 0x7; + + rqp->db_sgid_index = attr->ah_attr.grh.sgid_index & 0x7f; +} + +static void roce3_set_opt_field_attr(struct roce3_qp *rqp, const struct ib_qp_attr *attr, int attr_mask, + roce_verbs_qp_attr_s *qp_attr, u32 *optpar) +{ + /* RTR2RTS/SQD2SQD RETRY_CNT */ + if ((((u32)attr_mask) & IB_QP_RETRY_CNT) != 0) { + qp_attr->com_info.dw1.bs.to_retry_limit = attr->retry_cnt & 0x7; /* to_retry_limit:3 */ + *optpar |= ROCE_QP_OPTPAR_RETRY_COUNT; + } + + /* RTR2RTS/SQD2SQD RNR_RETRY */ + if ((((u32)attr_mask) & IB_QP_RNR_RETRY) != 0) { + qp_attr->com_info.dw1.bs.rnr_retry_limit = attr->rnr_retry & 0x7; /* rnr_retry_limit:3bits */ + *optpar |= ROCE_QP_OPTPAR_RNR_RETRY; + } + + /* INIT2RTR/SQD2SQD/RTR2RTS/RTS2RTS MIN_RNR_TIMER */ + if ((((u32)attr_mask) & IB_QP_MIN_RNR_TIMER) != 0) { + qp_attr->com_info.dw2.bs.min_rnr_nak = attr->min_rnr_timer & 0x1f; /* min_rnr_nak:5bits */ + *optpar |= ROCE_QP_OPTPAR_RNR_TIMEOUT; + } + + if ((((u32)attr_mask) & IB_QP_SQ_PSN) != 0) { + qp_attr->com_info.dw8.bs.next_send_psn = attr->sq_psn & 0xffffff; /* next_rcv_psn:24bit */ + } + + if ((((u32)attr_mask) & IB_QP_RQ_PSN) != 0) { + qp_attr->com_info.dw9.bs.next_rcv_psn = attr->rq_psn & 0xffffff; /* next_rcv_psn:24bit */ + } + + if ((((u32)attr_mask) & IB_QP_DEST_QPN) != 0) { + qp_attr->com_info.dw0.bs.dest_qp = attr->dest_qp_num & 0xffffff; /* dest_qp:24bit */ + } + +#ifdef ROCE_VBS_EN + if ((((u32)attr_mask) & ROCE_QP_VBS_FLAG) != 0) { /* IBV_QP_VBS_OSD_FLAG */ + roce3_vbs_set_attr(rqp, qp_attr, attr_mask); + } +#endif +} + +static s32 roce3_set_db_path_mtu(const struct ib_qp_attr *attr, struct roce3_qp *rqp, struct roce3_device *rdev) +{ + switch (attr->path_mtu) { +#ifdef ROCE_VROCE_EN + case IB_MTU_256: + rqp->db_path_mtu = BIT_LENGTH_IB_MTU_256; + break; + case IB_MTU_512: + rqp->db_path_mtu = BIT_LENGTH_IB_MTU_512; + break; +#else + case IB_MTU_256: + case IB_MTU_512: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s:Only support mtu larger than 1K.func_id(%d) mtu:%u\n", __func__, + rdev->glb_func_id, attr->path_mtu); + return -EINVAL; +#endif + case IB_MTU_1024: + rqp->db_path_mtu = BIT_LENGTH_IB_MTU_1024; + break; + case IB_MTU_2048: + rqp->db_path_mtu = BIT_LENGTH_IB_MTU_2048; + break; + case IB_MTU_4096: + rqp->db_path_mtu = BIT_LENGTH_IB_MTU_4096; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int roce3_set_opt_field(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, + roce_verbs_qp_attr_s *qp_attr, u32 *optpar) +{ + struct roce3_device *rdev = to_roce3_dev(rqp->ibqp.device); + int ret = 0; + + if ((((u32)attr_mask) & IB_QP_QKEY) != 0) { + qp_attr->com_info.q_key = attr->qkey; + *optpar |= ROCE_QP_OPTPAR_Q_KEY; + } + + if ((((u32)attr_mask) & IB_QP_AV) != 0) { + if (rdev->is_vroce) { + if (rqp->qp_type == (u32)IB_QPT_RC) { + attr->ah_attr.sl = rdev->group_rc_cos; + rqp->sl = rdev->group_rc_cos; + } else if (rqp->qp_type == (u32)IB_QPT_UD) { + attr->ah_attr.sl = rdev->group_ud_cos; + rqp->sl = rdev->group_ud_cos; + } else { + attr->ah_attr.sl = rdev->group_xrc_cos; + rqp->sl = rdev->group_xrc_cos; + } + } + roce3_set_opt_attr_av(rqp, rdev, attr, qp_attr, optpar); + } + + if ((((u32)attr_mask) & IB_QP_PORT) != 0) { + qp_attr->com_info.dw5.bs.port = attr->port_num & 0x7; /* port: 3bits */ + *optpar |= ROCE_QP_OPTPAR_SCHED_QUEUE; + } + + if ((((u32)attr_mask) & IB_QP_MAX_DEST_RD_ATOMIC) != 0) { + roce3_set_opt_rdmarc(rdev, rqp, qp_attr); + *optpar |= ROCE_QP_OPTPAR_RRA_MAX; + } + + /* RTR2RTS/SQD2SQD SRA_MAX */ + if ((((u32)attr_mask) & IB_QP_MAX_QP_RD_ATOMIC) != 0) { + roce3_set_opt_sra(qp_attr, attr); + *optpar |= ROCE_QP_OPTPAR_SRA_MAX; + } + + /* RWE/RRE/RAE,RST2INIT */ + if ((((u32)attr_mask) & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) != 0) { + roce3_set_access_flags(rqp, qp_attr, attr, attr_mask); + *optpar |= ROCE_QP_OPTPAR_RWE | ROCE_QP_OPTPAR_RRE | ROCE_QP_OPTPAR_RAE; + } + + /* RTR2RTS/SQD2SQD ACK TIMEOUT */ + if ((((u32)attr_mask) & IB_QP_TIMEOUT) != 0) { + qp_attr->com_info.dw2.bs.ack_to = attr->timeout & 0x1f; /* ack_to:5bits */ + *optpar |= ROCE_QP_OPTPAR_ACK_TIMEOUT; + } + + if ((((u32)attr_mask) & IB_QP_PATH_MTU) != 0) { + ret = roce3_set_db_path_mtu(attr, rqp, rdev); + if (ret != 0) { + return ret; + } + roce3_set_opt_mtu(qp_attr, attr); + } + + roce3_set_opt_field_attr(rqp, attr, attr_mask, qp_attr, optpar); + return ret; +} + +static void roce3_set_qp_srq_attr(struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr, struct roce3_pd *pd, + const struct roce3_cq *recv_cq) +{ + struct roce3_srq *rsrq = to_roce3_srq(rqp->ibqp.srq); + struct roce_srq_context temp; + + if (rsrq->container_flag != 0) { + struct roce_srq_context *srqc = (struct roce_srq_context *)((void *)rsrq->cqm_srq->q_ctx_vaddr); + temp.dw0.value = be32_to_cpu(srqc->dw0.value); + qp_attr->chip_seg.dw12.bs.srq_pd = temp.dw0.bs.pdn & 0x3ffff; /* srq_pd:18bits */ + qp_attr->chip_seg.dw12.bs.srq_wqebb_size = temp.dw0.bs.wqebb_size; + qp_attr->chip_seg.dw12.bs.srq_page_size = temp.dw0.bs.page_size; + qp_attr->chip_seg.dw12.bs.srq_size = temp.dw0.bs.size; + + temp.dw1.value = be32_to_cpu(srqc->dw1.value); + qp_attr->com_info.dw5.bs.so_ro = temp.dw1.bs_c.so_ro; + qp_attr->com_info.dw5.bs.dma_attr_idx = temp.dw1.bs_c.dma_attr_idx; + + qp_attr->chip_seg.dw9.bs.container_sz = MAX_SUPPORT_CONTAINER_MODE - rsrq->container_mode; + qp_attr->chip_seg.dw9.bs.container_en = 1; + + qp_attr->com_info.dw3.bs.srq_container = 1; + + if (rsrq->rqe_cnt_th > 0) { + qp_attr->chip_seg.dw9.bs.srq_warth_flag = 1; + qp_attr->chip_seg.dw8.bs.srq_rqecnt_th = rsrq->rqe_cnt_th & 0xf; /* srq_rqecnt_th:4bits */ + } + + qp_attr->chip_seg.dw7.bs.srqn = rsrq->srqn & 0x3ffff; /* srqn:18bits */ + } else { + qp_attr->chip_seg.dw7.bs.srqn = rsrq->srqn & 0x3ffff; /* srqn:18bits */ + } + + qp_attr->com_info.dw2.bs.srq_en = 1; + qp_attr->chip_seg.dw12.bs.srq_rkey_en = 1; + qp_attr->com_info.dw0.bs.rkey_en = 1; + qp_attr->chip_seg.dw13.bs.srq_cqn = recv_cq->cqn & 0xfffff; /* rq_cqn:20bits */ + qp_attr->chip_seg.dw9.bs.srq_mtt_prefetch_maxlen1 = 1; +} + +static void roce3_set_qp_rst2init_attr(struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr, struct roce3_pd *pd, + struct roce3_cq *recv_cq) +{ + qp_attr->chip_seg.dw4.bs.rq_base_ci = (u32)(ROCE_ILOG2(rqp->rq.offset >> rqp->rq.wqe_shift)); + qp_attr->chip_seg.dw19.bs.qp_pd = pd->pdn & 0x3ffff; /* pd:18bits */ + qp_attr->com_info.dw3.bs.dsgl_en = rqp->double_sgl_mode & 0x1; + + if (rqp->ibqp.srq) { + roce3_set_qp_srq_attr(rqp, qp_attr, pd, recv_cq); + } else { + qp_attr->chip_seg.dw15.bs.rq_size = (rqp->rq.wqebb_cnt > 0) ? (((u32)ROCE_ILOG2(rqp->rq.wqebb_cnt)) & 0x1f) : 0; + qp_attr->chip_seg.dw15.bs.rq_page_size = + ((u32)((u32)rqp->buf.page_shift - PAGE_SHIFT_4K)) & ROCE_SQ_PAGE_SIZE_MASK; + qp_attr->chip_seg.dw15.bs.rq_pd = pd->pdn & 0x3ffff; /* pd:18bits */ + qp_attr->chip_seg.dw8.bs.rq_wqebb_size = (u32)(rqp->rq.wqe_shift - BYTES_TO_16B_SHIFT) & 0x7; + qp_attr->com_info.dw7.bs.rq_cqn = recv_cq->cqn & 0xfffff; /* rq_cqn:20bits */ + qp_attr->com_info.dw7.bs.rq_cqn_lb = g_rq_cqn_lb; + qp_attr->chip_seg.dw15.bs.rq_rkey_en = 1; + + qp_attr->chip_seg.dw8.bs.rq_pi_on_chip = 0; + qp_attr->chip_seg.dw7.bs.rq_wqecnt_lth = ROCE_RQ_WQECNT_LTH; + qp_attr->chip_seg.dw7.bs.rq_wqecnt_rctl_en = 0; + qp_attr->chip_seg.dw7.bs.rq_wqe_cache_thd_sel = 0; + qp_attr->chip_seg.dw7.bs.rq_wqecnt_rctl = 0; + qp_attr->chip_seg.dw9.bs.rq_mtt_prefetch_maxlen0 = ROCE_RQ_MTT_PREFETCH_MAXLEN0; + qp_attr->chip_seg.dw9.bs.rq_mtt_prefetch_maxlen1 = 0; + qp_attr->chip_seg.dw9.bs.rq_mtt_prefetch_maxwqe = ROCE_RQ_MTT_PREFETCH_MAXWQE; + qp_attr->chip_seg.dw7.bs.rq_wqe_prefetch_minnum = 0; + qp_attr->chip_seg.dw7.bs.rq_wqe_prefetch_maxnum = ROCE_RQ_WQE_PREFETCH_MAXNUM; + } +} + +static void roce3_qp_rst2init_set_qpcc(roce_verbs_qp_attr_s *qp_attr, const struct roce3_qp *rqp, + const struct roce3_device *rdev) +{ + qp_attr->chip_seg.dw0.sq_rq_l0mtt_gpa = rqp->mtt.mtt_paddr; + qp_attr->chip_seg.dw2.sq_rq_pi_record_gpa_at_hop_num = rqp->db.dma & (~0x3ULL); /* bits:63-2 */ + qp_attr->chip_seg.dw2.sq_rq_pi_record_gpa_at_hop_num |= rqp->mtt.mtt_layers & 0x3; /* bits:1-0 */ + if (rqp->qp_type == IB_QPT_XRC_TGT) { + qp_attr->chip_seg.dw2.sq_rq_pi_record_gpa_at_hop_num = rqp->qpc_info->paddr & (~0x3ULL); /* bits:63-2 */ + } + + qp_attr->chip_seg.dw4.bs.sq_rq_mtt_page_size = rqp->mtt.mtt_page_shift - PAGE_SHIFT_4K; + /* rc_entry_size:2bits */ + qp_attr->chip_seg.dw10.bs.rc_entry_size = + ((u32)ROCE_ILOG2(rdev->rdma_cap.dev_rdma_cap.roce_own_cap.rdmarc_entry_sz >> BYTES_TO_16B_SHIFT) & 0x3); + qp_attr->chip_seg.dw14.bs.qp_rkey_en = 1; + qp_attr->chip_seg.dw10.bs.rc_entry_prefetch_maxnum = 0; +} + +static void roce3_qp_rst2init_set_sqc_sqac(roce_verbs_qp_attr_s *qp_attr, const struct roce3_qp *rqp, + const struct roce3_pd *pd, const struct roce3_cq *send_cq) +{ +#ifdef ROCE_COMPUTE + u8 sq_pi_on_chip = (u8)((rqp->qpn <= ROCE_MAX_PI_ON_CHIP_QPN) && (rqp->qp_type != IB_QPT_UD)); + qp_attr->chip_seg.dw5.bs.sq_pi_on_chip = sq_pi_on_chip; +#else + qp_attr->chip_seg.dw5.bs.sq_pi_on_chip = 0; +#endif + qp_attr->chip_seg.dw16.bs.sq_wqebb_size = + ((u32)(rqp->sq.wqe_shift - ROCE_SQ_WQEBB_SIZE_SHIFT)) & ROCE_SQ_WQEBB_SIZE_MASK; + qp_attr->chip_seg.dw16.bs.sq_pd = ((u32)pd->pdn) & 0x3ffff; /* pd:18bits */ + qp_attr->chip_seg.dw16.bs.sq_page_size = ((u32)(rqp->buf.page_shift - PAGE_SHIFT_4K)) & ROCE_SQ_PAGE_SIZE_MASK; + qp_attr->chip_seg.dw5.bs.sq_inline_en = rqp->max_inline_data > 0 ? 1 : 0; + + qp_attr->chip_seg.dw16.bs.sq_rkey_en = 1; + + qp_attr->chip_seg.dw5.bs.sq_wqecnt_lth = ROCE_SQ_WQECNT_LTH; + qp_attr->chip_seg.dw5.bs.sq_wqecnt_rctl_en = 0; + qp_attr->chip_seg.dw5.bs.sq_wqecnt_rctl = 0; + qp_attr->chip_seg.dw5.bs.sq_wqe_prefetch_minnum = ROCE_SQ_PREFETCH_MINNUM; + qp_attr->chip_seg.dw5.bs.sq_wqe_prefetch_maxnum = ROCE_SQ_PREFETCH_MAXNUM; + qp_attr->chip_seg.dw5.bs.sq_wqe_cache_thd_sel = 0; + qp_attr->chip_seg.dw6.bs.sq_wqe_prefetch_mode = 0; + qp_attr->chip_seg.dw6.bs.sq_mtt_prefetch_maxlen = 0; + + if (rqp->sq.wqebb_cnt != 0) { + qp_attr->chip_seg.dw5.bs.sq_size = (u32)(ROCE_ILOG2((u32)rqp->sq.wqebb_cnt)) & ROCE_SQ_SIZE_MASK; + } + + qp_attr->com_info.dw7.bs.sq_cqn_lb = g_sq_cqn_lb; + qp_attr->chip_seg.dw17.bs.sqa_cqn = send_cq->cqn & ROCE_SQ_CQN_MASK; + + qp_attr->chip_seg.dw5.bs.sqa_wqe_prefetch_minnum = ROCE_SQ_PREFETCH_MINNUM; + qp_attr->chip_seg.dw5.bs.sqa_wqe_prefetch_maxnum = ROCE_WQE_PREFETCH_MAXNUM; + qp_attr->chip_seg.dw6.bs.sqa_mtt_prefetch_maxlen = 0; + qp_attr->chip_seg.dw5.bs.sqa_wqe_cache_thd_sel = 0; +} + +static void roce3_qp_rst2init_set_drv(roce_verbs_qp_attr_s *qp_attr, struct roce3_qp *rqp, struct roce3_device *rdev) +{ + u16 host_oqid = 0; + u8 host_id = 0; + + host_id = hinic3_host_id(rdev->hwdev); + if (host_id == ROCE_SPU_HOST_ID) { + host_id = ROCE_SPU_OQID_HOST_ID; + host_oqid = (u16)ROCE_GET_SPU_HOST_OQID(host_id, rdev->glb_func_id, rqp->qpn); + } else { + host_oqid = (u16)ROCE_GET_HOST_OQID(host_id, rqp->qpn); + } + + qp_attr->com_info.dw0.bs.service_type = (u32)to_roce3_qp_type((enum ib_qp_type)rqp->qp_type) & 0x7; + if (rdev->is_vroce) { + if (qp_attr->com_info.dw0.bs.service_type == ROCE_QP_ST_RC) { + qp_attr->path_info.dw7.bs.sl = rdev->group_rc_cos; + rqp->sl = rdev->group_rc_cos; + } else if (qp_attr->com_info.dw0.bs.service_type == ROCE_QP_ST_UD) { + qp_attr->path_info.dw7.bs.sl = rdev->group_ud_cos; + rqp->sl = rdev->group_ud_cos; + } else { + qp_attr->path_info.dw7.bs.sl = rdev->group_xrc_cos; + rqp->sl = rdev->group_xrc_cos; + } + } + qp_attr->com_info.dw3.bs.dif_en = (u32)rqp->signature_en; + qp_attr->com_info.dw2.bs.vroce_en = (u32)rdev->is_vroce; + + if (!rqp->ibqp.uobject) { + qp_attr->com_info.dw0.bs.fre = 1; + } + + qp_attr->com_info.dw3.bs.xrc_vld = (u32)(rqp->qp_type == IB_QPT_XRC_INI); + qp_attr->com_info.dw1.bs.local_qp = rqp->qpn & 0xffffff; /* local_qp:24bits */ + qp_attr->com_info.dw5.bs.ep = rdev->hw_info.ep_id; + if (rdev->is_vroce) { + qp_attr->com_info.dw2.bs.host_oqid = (host_oqid & 0xfffc) | ROCE_IPSUTX_CHANNEL_15; + } else { + qp_attr->com_info.dw2.bs.host_oqid = host_oqid & 0xffff; /* host_oqid:16bits */ + } + + qp_attr->chip_seg.dw4.bs.dsgl = rqp->double_sgl_mode & 0x1; + qp_attr->path_info.dw7.bs.udp_src_port = (qp_attr->com_info.dw1.bs.local_qp & 0xff); +} + +static void roce3_qp_rst2init_set_common(roce_verbs_qp_attr_s *qp_attr, const struct roce3_pd *pd) +{ + qp_attr->com_info.dw12.bs.ccf_app_id = ROCE_CC_DISABLE; // STUB + qp_attr->chip_seg.dw18.bs.ud_pd = pd->pdn & 0x3ffff; /* pd:18bits */ +} + +static void roce3_qp_rst2init_set_dcqcn(roce_verbs_qp_attr_s *qp_attr) +{ + /* ecn ver */ + /* b300 nic do not support the func + context->sw_seg.ucode_seg.common.dw1.bs.ecn_ver = rdev->ecn_ctx.ecn_ver & 0xf; + */ +} + +static void roce3_qp_rst2init_set_fake_vf(const struct roce3_device *rdev, const struct roce3_pd *pd, + roce_verbs_qp_attr_s *qp_attr) +{ + u32 fake_vf_id = 0; + struct roce3_ucontext *roce3_uctx = NULL; + u32 db_offset; + + fake_vf_id = ((u32)rdev->glb_func_id) << rdev->cfg_info.pf_start_bit; + if (rdev->cfg_info.pf_end_bit < ROCE_VLD_PF_NUM_10) { + fake_vf_id |= 0x1C00; /* 12 11 10 bit 1 */ + } else if (rdev->cfg_info.pf_end_bit < ROCE_VLD_PF_NUM_11) { + fake_vf_id |= 0x1800; /* 12 11 bit 1 */ + } else if (rdev->cfg_info.pf_end_bit < ROCE_VLD_PF_NUM_12) { + fake_vf_id |= 0x1000; /* 12 bit 1 */ + } + + if (pd->ibpd.uobject) { + roce3_uctx = to_roce3_ucontext(pd->ibpd.uobject->context); + db_offset = (u32)((roce3_uctx->db_dma_addr >> (12UL + rdev->cfg_info.page_bit)) & + ((1UL << rdev->cfg_info.pf_start_bit) - 1)); + qp_attr->com_info.dw11.bs.vf_id = fake_vf_id | db_offset; + printk("[ROCE] func_id:%u The fake_id:%u ,start:%u end:%u page_bit:%u roce3_uctx->db_dma_addr:%llu \n", + rdev->glb_func_id, qp_attr->com_info.dw11.bs.vf_id, rdev->cfg_info.pf_start_bit, rdev->cfg_info.pf_end_bit, + rdev->cfg_info.page_bit, roce3_uctx->db_dma_addr); + qp_attr->com_info.dw11.bs.fake = 1; + } else { + printk("[ROCE] kernel not support fake_vf currently. func:%u \n", rdev->glb_func_id); + } +} + +static void roce3_qp_rst2init_set_xrc_attr(const struct roce3_qp *rqp, const struct ib_qp_attr *attr, + roce_verbs_qp_attr_s *qp_attr, const struct roce3_device *rdev, const struct roce3_cq *recv_cq) +{ + qp_attr->com_info.dw2.bs.xrc_srq_en = 1; + + if ((((u32)attr->qp_access_flags & XRC_CONTAINER_FLAG) != 0) || (rdev->cfg_info.srq_container_en != 0)) { + qp_attr->chip_seg.dw9.bs.container_en = 1; + qp_attr->com_info.dw3.bs.srq_container = 1; + qp_attr->chip_seg.dw8.bs.xrcd = rqp->xrcdn & 0xffff; /* xrcd:16bits */ + qp_attr->com_info.dw2.bs.srq_en = 1; + qp_attr->chip_seg.dw8.bs.srq_rqecnt_th = 1; + qp_attr->com_info.dw3.bs.xrc_vld = 1; + qp_attr->chip_seg.dw13.bs.srq_state = ROCE_SRQ_INIT_STATE; + } else { + qp_attr->chip_seg.dw12.bs.srq_rkey_en = 1; + qp_attr->com_info.dw2.bs.srq_en = 1; + qp_attr->chip_seg.dw8.bs.xrcd = rqp->xrcdn & 0xffff; /* xrcd:16bits */ + qp_attr->chip_seg.dw9.bs.srq_mtt_prefetch_maxlen1 = 1; + qp_attr->com_info.dw3.bs.xrc_vld = 1; + qp_attr->chip_seg.dw14.bs.srq_xrcd = rqp->xrcdn & 0xffff; /* xrcd:16bits */ + } + if (recv_cq != NULL) { + qp_attr->chip_seg.dw13.bs.srq_cqn = recv_cq->cqn & 0xfffff; /* rq_cqn:20bits */ + } +} + +/* **************************************************************************** + Prototype : roce3_qp_rst2init + Description : parameter set when QP is from RESET to INIT + Input : struct roce3_qp *rqp + const struct ib_qp_attr *attr + roce_verbs_qp_attr_s *qp_attr + Output : None + + 1.Date : 2015/8/6 + Modification : Created function + +**************************************************************************** */ +void roce3_qp_rst2init(struct roce3_qp *rqp, const struct ib_qp_attr *attr, roce_verbs_qp_attr_s *qp_attr) +{ + struct roce3_pd *pd = NULL; + struct roce3_cq *send_cq = NULL; + struct roce3_cq *recv_cq = NULL; + struct roce3_device *rdev = NULL; + + rdev = to_roce3_dev(rqp->ibqp.device); + pd = roce3_get_pd(rqp); + roce3_get_cqs(rqp, &send_cq, &recv_cq); + + /* CHIP_SEG: QPCC */ + roce3_qp_rst2init_set_qpcc(qp_attr, rqp, rdev); + + /* CHIP_SEG: SQC & SQAC */ + roce3_qp_rst2init_set_sqc_sqac(qp_attr, rqp, pd, send_cq); + + /* RRWC */ + qp_attr->chip_seg.dw4.bs.rrw_mtt_prefetch_maxlen = 0; + + /* RCC */ + qp_attr->chip_seg.dw10.bs.rc_mtt_prefetch_maxlen = ROCE_QP_MAX_PFETCH_MTT_LAYER; + + /* TIMER_SEG */ + qp_attr->com_info.dw3.bs.tss_timer_num = ROCE_QP_MAX_TIMER_NUM; + + /* DRV_SEG */ + roce3_qp_rst2init_set_drv(qp_attr, rqp, rdev); + + /* UCODE COM_SEG */ + roce3_qp_rst2init_set_common(qp_attr, pd); + + /* EXT DCQCN SEG */ + roce3_qp_rst2init_set_dcqcn(qp_attr); + + if (rdev->cfg_info.fake_en != 0) { + roce3_qp_rst2init_set_fake_vf(rdev, pd, qp_attr); + } + + if (rqp->qp_type == IB_QPT_XRC_TGT) { + roce3_qp_rst2init_set_xrc_attr(rqp, attr, qp_attr, rdev, recv_cq); + } else { + roce3_set_qp_rst2init_attr(rqp, qp_attr, pd, recv_cq); + } + +#ifdef ROCE_BONDING_EN + roce3_bond_rr_set_flow(rdev, rqp, qp_attr); +#endif +} + +/* **************************************************************************** + Prototype : roce3_qp_init2rtr + Description : init2rtr attributes modify + Input : struct roce3_qp *rqp + const struct ib_qp_attr *attr + roce_verbs_qp_attr_s *qp_attr + Output : None + + 1.Date : 2015/8/1 + Modification : Created function + +**************************************************************************** */ +static void roce3_qp_init2rtr(struct roce3_qp *rqp, const struct ib_qp_attr *attr, roce_verbs_qp_attr_s *qp_attr) +{ + if (rqp->ibqp.srq || (rqp->qp_type == IB_QPT_XRC_TGT) || (rqp->qp_type == IB_QPT_XRC_INI) || + (rqp->qp_type == IB_QPT_UD) || (rqp->qp_type == IB_QPT_UC) || (rqp->qp_type == IB_QPT_GSI)) { + qp_attr->com_info.dw3.bs.invalid_credit = 1; + } + + if ((rqp->qp_type == IB_QPT_GSI) || (rqp->qp_type == IB_QPT_UD)) { + qp_attr->com_info.dw3.bs.pmtu = IB_MTU_4096 & 0x7; /* for UD, mtu = 4096 */ + qp_attr->com_info.dw5.bs.mtu_code = ROCE_MTU_CODE_4K; + } + + qp_attr->com_info.dw2.bs.ack_to = 0xf; /* ack_to:5bits */ + qp_attr->com_info.dw0.bs.service_type = + (u32)to_roce3_qp_type((enum ib_qp_type)rqp->qp_type) & 0x7; /* service_type: 3bit */ +} + +/* **************************************************************************** + Prototype : roce3_qp_rtr2rts + Description : roce3_qp_rtr2rts + Input : struct roce3_qp *rqp + const struct ib_qp_attr *attr + roce_verbs_qp_attr_s *qp_attr + Output : None + + 1.Date : 2015/8/2 + Modification : Created function + +**************************************************************************** */ +static void roce3_qp_rtr2rts(struct roce3_qp *rqp, const struct ib_qp_attr *attr, roce_verbs_qp_attr_s *qp_attr) {} + +static void roce3_qp_2err(struct roce3_qp *rqp, const struct ib_qp_attr *attr, roce_verbs_qp_attr_s *qp_attr) {} + +/* **************************************************************************** + Prototype : roce3_set_abs_field + Description : set abs field to qpc + Input : struct roce3_qp *rqp + struct ib_qp_attr *attr + roce_verbs_qp_attr_s *qp_attr + enum ib_qp_state cur_state + enum ib_qp_state new_state + Output : None + + 1.Date : 2016/01/30 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_abs_field(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, + roce_verbs_qp_attr_s *qp_attr) +{ + enum ib_qp_state cur_state, new_state; + + cur_state = (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_CUR_STATE) != 0) ? attr->cur_qp_state : rqp->qp_state); + new_state = ((((u32)attr_mask) & IB_QP_STATE) != 0) ? attr->qp_state : cur_state; + if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { + roce3_qp_rst2init(rqp, attr, qp_attr); + } + + if ((cur_state == IB_QPS_INIT) && (new_state == IB_QPS_RTR)) { + roce3_qp_init2rtr(rqp, attr, qp_attr); + } + + if ((cur_state == IB_QPS_RTR) && (new_state == IB_QPS_RTS)) { + roce3_qp_rtr2rts(rqp, attr, qp_attr); + } + + if (new_state == IB_QPS_ERR) { + roce3_qp_2err(rqp, attr, qp_attr); + } + return; +} + +/* **************************************************************************** + Prototype : roce3_record_opt_field + Description : set opt field to roce3_qp after send cmd modify_qp + Input : struct roce3_qp *rqp + struct ib_qp_attr *attr + int attr_mask + Output : None + + 1.Date : 2016/01/30 + Modification : Created function + +**************************************************************************** */ +static void roce3_record_opt_field(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask) +{ + enum ib_qp_state cur_state, new_state; + + cur_state = (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_CUR_STATE) != 0) ? attr->cur_qp_state : rqp->qp_state); + new_state = ((((u32)attr_mask) & IB_QP_STATE) != 0) ? attr->qp_state : cur_state; + rqp->qp_state = new_state; + + if ((((u32)attr_mask) & IB_QP_AV) != 0) { + rqp->sl = attr->ah_attr.sl & 0x7; + } + + if ((((u32)attr_mask) & IB_QP_ACCESS_FLAGS) != 0) { + rqp->atomic_rd_en = (u8)attr->qp_access_flags; + } + + if ((((u32)attr_mask) & IB_QP_PORT) != 0) { + rqp->port = attr->port_num; + } + + if (roce3_sqp_check(rqp) != 0) { + store_sqp_attrs(to_roce3_sqp(rqp), attr, attr_mask); + } + return; +} + +/* **************************************************************************** + Prototype : roce3_qp_modify_2rst_cmd + Description : cache out qpc mtt + Input : struct roce3_device *rdev + struct roce3_qp *rqp + Output : None + + 1.Date : 2016/6/17 + Modification : Created function + + 2.Date : 2017/04/26 + Modification : Modify function + +**************************************************************************** */ +int roce3_qp_modify_2rst_cmd(struct roce3_device *rdev, u32 qpn) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_uni_cmd_qp_modify2rst_s *qp_moidfy2rst_inbuf = NULL; + struct timespec64 tv_start; + + ktime_get_ts64(&tv_start); + ret = + roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_qp_modify2rst_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + qp_moidfy2rst_inbuf = (roce_uni_cmd_qp_modify2rst_s *)cqm_cmd_inbuf->buf; + qp_moidfy2rst_inbuf->com.index = cpu_to_be32(qpn); + if (!roce3_is_roceaa(rdev->cfg_info.scence_id)) { + qp_moidfy2rst_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); //lint !e778 + } else { + qp_moidfy2rst_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_NOFAA_BITMASK); //lint !e778 + } + + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_2RST_QP, cqm_cmd_inbuf, NULL, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send 2RST_QP command, qpn(0x%x), func_id(%d), ret(0x%x)\n", + __func__, qpn, rdev->glb_func_id, ret); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(2RST_QP), qpn(0x%x), func_id(%hu)\n", __func__, qpn, + rdev->glb_func_id); + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return -1; + } + } + roce3_timeout_check(rdev, &tv_start, MODIFY_2RST_CMDQ, 0); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return 0; +} + +/* **************************************************************************** + Prototype : roce3_qp_check_rdmarc + Description : roce3_qp_check_rdmarc + Input : struct roce3_device *rdev + struct roce3_qp *rqp + Output : None + + 1.Date : 2017/04/26 + Modification : Create function + +**************************************************************************** */ +static int roce3_qp_check_rdmarc(struct roce3_device *rdev, struct roce3_qp *rqp, int *cost) +{ + int times = 0; + u32 rc_num = 0; + u32 rc_check_index = 0; + void *rdmarc_vaddr = NULL; + dma_addr_t rdmarc_paddr = 0; + + rc_num = (u32)(((u32)1 << rqp->rdmarc.order) / RDMARC_NUM_PER_CACHELINE); + rdmarc_vaddr = rqp->rdmarc.vaddr; + rdmarc_paddr = rqp->rdmarc.dma_addr; + + times = rdev->try_times; + do { + if (roce3_hca_is_present(rdev) == 0) { + return 0; + } + + if ((*((u32 *)rdmarc_vaddr) == ROCE_RDMARC_DESTROY_CHECK_VALUE) && + (cpu_to_be32(*((u32 *)rdmarc_vaddr + 1)) == rqp->qpn) && + (cpu_to_be64(*((u64 *)rdmarc_vaddr + 1)) == + ((u64)rdmarc_paddr + ((u64)ROCE_CACHE_LINE_SIZE * (u64)rc_check_index)))) { + rdmarc_vaddr = (void *)((u8 *)rdmarc_vaddr + ROCE_CACHE_LINE_SIZE); + rc_check_index++; + if (rc_num == rc_check_index) { + break; + } + } else { + ROCE_UDELAY(US_PERF_DELAY); + times--; + } + } while (times != 0); + + if (rc_num != rc_check_index) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to read rdmarc field back after try %d times, func_id(%d) rc_check_index:%u " + "rc_num:%u\n", + __func__, ((rdev->try_times - times) + 1), rdev->glb_func_id, rc_check_index, rc_num); + *cost = (rdev->try_times - times) + 1; + return -1; + } + *cost = (rdev->try_times - times) + 1; + return 0; +} + +static int roce3_qp_check_state(struct roce3_device *rdev, const struct roce3_qp *rqp, const u32 *wb_va, int *cost) +{ + int times = 0; + int read_back_flag = 0; + + times = rdev->try_times; + while ((times--) != 0) { + if (roce3_hca_is_present(rdev) == 0) { + return 0; + } + + if (*(u32 *)wb_va == ROCE_QP_DESTROY_CHECK_VALUE) { + read_back_flag = 1; + break; + } + ROCE_UDELAY(US_PERF_DELAY); + } + + if (read_back_flag == 0) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to read QP field back after try %d times,qpn(0x%x), " + "wb_data(0x%x), func_id(%d)\n", + __func__, ((rdev->try_times - times) + 1), rqp->qpn, *(u32 *)wb_va, rdev->glb_func_id); + *cost = (rdev->try_times - times) + 1; + return -1; + } + *cost = (rdev->try_times - times) + 1; + return 0; +} + +static void roce3_qp_fill_cacheout_inbuf(struct roce3_device *rdev, struct roce3_qp *rqp, dma_addr_t wb_dma, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + roce_uni_cmd_qp_cache_invalid_s *qp_cacheout_inbuf = NULL; + struct rdma_service_cap *rdma_cap = NULL; + u16 host_oqid = 0; + u8 host_id = 0; + + host_id = hinic3_host_id(rdev->hwdev); + if (host_id == ROCE_SPU_HOST_ID) { + host_id = ROCE_SPU_OQID_HOST_ID; + host_oqid = (u16)ROCE_GET_SPU_HOST_OQID(host_id, rdev->glb_func_id, rqp->qpn); + } else { + host_oqid = (u16)ROCE_GET_HOST_OQID(host_id, rqp->qpn); + } + + qp_cacheout_inbuf = (roce_uni_cmd_qp_cache_invalid_s *)(cqm_cmd_inbuf)->buf; + rdma_cap = &rdev->rdma_cap; + + if (!roce3_is_roceaa(rdev->cfg_info.scence_id)) { + qp_cacheout_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); //lint !e778 + } else { + qp_cacheout_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_NOFAA_BITMASK); //lint !e778 + } + + qp_cacheout_inbuf->com.index = cpu_to_be32(rqp->qpn); + qp_cacheout_inbuf->qp_cache.sq_buf_len = + cpu_to_be32(ALIGN(((u32)rqp->sq.wqebb_cnt) << ((u32)rqp->sq.wqe_shift), PAGE_SIZE)); + qp_cacheout_inbuf->qp_cache.rq_buf_len = + cpu_to_be32(ALIGN(((u32)rqp->rq.wqebb_cnt) << ((u32)rqp->sq.wqe_shift), PAGE_SIZE)); + qp_cacheout_inbuf->qp_cache.cmtt_cache.mtt_flags = 0; + qp_cacheout_inbuf->qp_cache.cmtt_cache.mtt_num = 0; + qp_cacheout_inbuf->qp_cache.cmtt_cache.mtt_cache_line_start = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_start); + qp_cacheout_inbuf->qp_cache.cmtt_cache.mtt_cache_line_end = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_end); + qp_cacheout_inbuf->qp_cache.cmtt_cache.mtt_cache_line_size = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_sz); + qp_cacheout_inbuf->qp_cache.wb_gpa = cpu_to_be64(wb_dma); + qp_cacheout_inbuf->qp_cache.dw9.bs.host_oqid = cpu_to_be16(host_oqid); + qp_cacheout_inbuf->qp_cache.wqe_cache.wqe_flags = 0; + qp_cacheout_inbuf->qp_cache.wqe_cache.wqe_num = 0; + qp_cacheout_inbuf->qp_cache.wqe_cache.wqe_cache_line_start = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.wqe_cl_start); + qp_cacheout_inbuf->qp_cache.wqe_cache.wqe_cache_line_end = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.wqe_cl_end); + qp_cacheout_inbuf->qp_cache.wqe_cache.wqe_cache_line_size = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.wqe_cl_sz); +} + +static int roce3_qp_send_cache_out_cmd(struct roce3_device *rdev, struct roce3_qp *rqp, void *wb_va, dma_addr_t wb_dma, + int *cost) +{ + unsigned long end; + int times = 0; + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_qp_cache_invalid_s), NULL, + 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + roce3_qp_fill_cacheout_inbuf(rdev, rqp, wb_dma, cqm_cmd_inbuf); + + end = jiffies + (ROCE_CMDQ_TIMEOUT_10MS * HZ); + while (time_before(jiffies, end)) { + times++; + ret = + roce3_send_qp_lb_cmd(rqp->qpn, rdev, ROCE_CMD_MISC_CACHE_INVLD, cqm_cmd_inbuf, NULL, ROCE_CMD_TIME_CLASS_C); + if (ret <= 0) { /* return success or exception happened */ + break; + } + + /*lint -e160 -e522*/ + cond_resched(); + /*lint +e160 +e522*/ + }; + + if (ret != 0) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed MISC_CACHE_INVLD command after try %d times, ret(%d), func_id(%d) qpn(%d)\n", + __func__, times, ret, rdev->glb_func_id, rqp->qpn); + /* Card not present need to return OK */ + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return ok), QPN(0x%x), ret(%d), func_id(%d)\n", + __func__, rqp->qpn, ret, rdev->glb_func_id); + goto out; + } + + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: CMDq timeout, func_id(%d)\n", __func__, rdev->glb_func_id); + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + *cost = times; + return (-EINVAL); + } + +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + *cost = (rdev->try_times - times) + 1; + return 0; +} + +/* **************************************************************************** + Prototype : roce3_qp_cache_out_cmd + Description : cache out qpc mtt + Input : struct roce3_device *rdev + struct roce3_qp *rqp + Output : None + + 1.Date : 2016/9/24 + Modification : Created function + + 2.Date : 2017/04/26 + Modification : Modify function + +**************************************************************************** */ +int roce3_qp_cache_out_cmd(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + int ret = 0; + int cost = 0; + void *wb_va = NULL; + dma_addr_t wb_dma = 0; + struct timespec64 tv_start; + + ktime_get_ts64(&tv_start); + wb_va = dma_alloc_coherent(&rdev->pdev->dev, (size_t)4UL, &wb_dma, GFP_KERNEL); + if (wb_va == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc wb_va, func_id(%d)\n", __func__, rdev->glb_func_id); + return -ENOMEM; + } + roce3_timeout_check(rdev, &tv_start, CACHE_INVLAID_ALLOC, cost); + + ret = roce3_qp_send_cache_out_cmd(rdev, rqp, wb_va, wb_dma, &cost); + if (ret != 0) { + goto err; + } + roce3_timeout_check(rdev, &tv_start, CACHE_INVLAID_CMDQ, cost); + if (rqp->rsp_depth > 0) { + ret = roce3_qp_check_rdmarc(rdev, rqp, &cost); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to check qp rdmarc, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err; + } + roce3_timeout_check(rdev, &tv_start, CACHE_INVLAID_RDMARC_CHECK, cost); + } + ret = roce3_qp_check_state(rdev, rqp, (u32 *)wb_va, &cost); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to check qp state, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err; + } + roce3_timeout_check(rdev, &tv_start, CACHE_INVLAID_QP_CHECK, cost); + +err: + dma_free_coherent(&rdev->pdev->dev, sizeof(u32), wb_va, wb_dma); + + return ret; +} + +static u8 roce3_get_qp_cmdq_cmd(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask) +{ + static u16 op[ROCE_QP_STATE_NUM][ROCE_QP_STATE_NUM]; + enum ib_qp_state cur_state, new_state; + + cur_state = (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_CUR_STATE) != 0) ? attr->cur_qp_state : rqp->qp_state); + new_state = ((((u32)attr_mask) & IB_QP_STATE) != 0) ? attr->qp_state : cur_state; + if ((cur_state > IB_QPS_ERR) || (new_state > IB_QPS_ERR)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: QP state modify invalid, cur_state(%d), new_state(%d), func_id(%d)\n", + __func__, cur_state, new_state, rdev->glb_func_id); + return 0; + } + op[IB_QPS_RESET][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + op[IB_QPS_RESET][IB_QPS_INIT] = ROCE_CMD_RST2INIT_QP; + + op[IB_QPS_INIT][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + op[IB_QPS_INIT][IB_QPS_INIT] = ROCE_CMD_INIT2INIT_QP; + op[IB_QPS_INIT][IB_QPS_RTR] = ROCE_CMD_INIT2RTR_QP; + + op[IB_QPS_RTR][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + op[IB_QPS_RTR][IB_QPS_RTS] = ROCE_CMD_RTR2RTS_QP; + + op[IB_QPS_RTS][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + op[IB_QPS_RTS][IB_QPS_RTS] = ROCE_CMD_RTS2RTS_QP; + op[IB_QPS_RTS][IB_QPS_SQD] = ROCE_CMD_RTS2SQD_QP; + + op[IB_QPS_SQD][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + op[IB_QPS_SQD][IB_QPS_RTS] = ROCE_CMD_SQD2RTS_QP; + op[IB_QPS_SQD][IB_QPS_SQD] = ROCE_CMD_SQD2SQD_QP; + + op[IB_QPS_SQE][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + op[IB_QPS_SQE][IB_QPS_RTS] = ROCE_CMD_SQERR2RTS_QP; + + op[IB_QPS_ERR][IB_QPS_ERR] = ROCE_CMD_2ERR_QP; + + return (u8)op[cur_state][new_state]; +} + +static int roce3_qp_rts2sqd_cmd(struct roce3_device *rdev, struct roce3_qp *rqp, const struct ib_qp_attr *attr, + int attr_mask) +{ + int ret = 0; + int sqd_event = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_uni_cmd_qp_modify_rts2sqd_s *qp_rts2sqd_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_qp_modify_rts2sqd_s), + NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + sqd_event = ((((u32)attr_mask) & IB_QP_EN_SQD_ASYNC_NOTIFY) != 0) && (attr->en_sqd_async_notify != 0); + qp_rts2sqd_inbuf = (roce_uni_cmd_qp_modify_rts2sqd_s *)cqm_cmd_inbuf->buf; + qp_rts2sqd_inbuf->com.index = cpu_to_be32(rqp->qpn); + qp_rts2sqd_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); //lint !e778 + qp_rts2sqd_inbuf->sqd_event_en = cpu_to_be32((u32)(sqd_event != 0)); + + ret = roce3_send_qp_lb_cmd(rqp->qpn, rdev, ROCE_CMD_RTS2SQD_QP, cqm_cmd_inbuf, NULL, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send RTS2SQD_QP cmd, func_id(%d), ret(0x%x)\n", __func__, + rdev->glb_func_id, ret); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return 0; +} + +static void roce3_qp_fill_modify_inbuf(cqm_cmd_buf_s *cqm_cmd_inbuf, struct roce3_qp *rqp, + roce_verbs_qp_attr_s *qp_attr, u32 optpar) +{ + roce_uni_cmd_modify_qpc_s *qp_modify_inbuf = NULL; + + qp_modify_inbuf = (roce_uni_cmd_modify_qpc_s *)cqm_cmd_inbuf->buf; + roce3_qpc_to_be(qp_attr, rqp, (u32 *)&qp_modify_inbuf->qp_attr); + + qp_modify_inbuf->com.index = cpu_to_be32(rqp->qpn); + qp_modify_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); //lint !e778 + qp_modify_inbuf->com.opt = cpu_to_be32(optpar); + +#ifdef ROCE_VBS_EN + if (rqp->vbs_qp_ptr) { // vbs_en, transmit record addr to ucode + roce3_vbs_transmit_sqpc_ci_record_addr(rqp, cqm_cmd_inbuf->buf); + } +#endif + + return; +} + +static int roce3_qp_handle_err(struct roce3_device *rdev, const struct roce3_qp *rqp, int ret) +{ + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send MODIFY_QP command, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(MODIFY_QP), qpn(0x%x), func_id(%hu)\n", __func__, rqp->qpn, + rdev->glb_func_id); + + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + + return -1; + } + + return 0; +} + +static int roce3_qp_modify_cmd(struct roce3_device *rdev, struct roce3_qp *rqp, u8 cmd, roce_verbs_qp_attr_s *qp_attr, + u32 optpar) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_modify_qpc_s), + &cqm_cmd_outbuf, ROCE_QP_MODIFY_CMD_OUT_BUF_SIZE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return (-ENOMEM); + } + + if (!roce3_is_roceaa(rdev->cfg_info.scence_id)) { + roce3_qp_fill_modify_inbuf(cqm_cmd_inbuf, rqp, qp_attr, optpar); + } else { + roce3_qp_modify_cmd_ext(cqm_cmd_inbuf, rqp, qp_attr, optpar); + } + + ret = roce3_send_qp_lb_cmd(rqp->qpn, rdev, cmd, cqm_cmd_inbuf, cqm_cmd_outbuf, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + ret = roce3_qp_handle_err(rdev, rqp, ret); + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return ret; +} + +void roce3_cq_clean(struct roce3_cq *cq, u32 qpn, struct roce3_srq *srq) +{ + spin_lock_irq(&cq->lock); + roce3_cq_clean_process(cq, qpn, srq); + spin_unlock_irq(&cq->lock); +} + +static int roce3_qp_clean_kernel_res(struct roce3_qp *rqp) +{ + struct roce3_cq *send_cq = NULL; + struct roce3_cq *recv_cq = NULL; + + roce3_get_cqs(rqp, &send_cq, &recv_cq); + + roce3_cq_clean(recv_cq, rqp->qpn, rqp->ibqp.srq ? to_roce3_srq(rqp->ibqp.srq) : NULL); + if (send_cq != recv_cq) { + roce3_cq_clean(send_cq, rqp->qpn, NULL); + } + + rqp->rq.head = 0; + rqp->rq.tail = 0; + + rqp->sq.head = 0; + rqp->sq.tail = 0; + + rqp->sq_next_wqe = 0; + + *(rqp->db.db_record) = 0; + + if (rqp->qp_type != IB_QPT_XRC_TGT) { + if (rqp->has_rq && rqp->qp_buf_info->q_header_vaddr) { + memset(rqp->qp_buf_info->q_header_vaddr, 0, sizeof(u64)); + } + } + + return 0; +} + +static int roce3_qp_modify_2rst(struct roce3_device *rdev, struct roce3_qp *rqp) +{ + int ret = 0; + + ret = roce3_qp_modify_2rst_cmd(rdev, rqp->qpn); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify QP(0x%06x) to RESET, func_id(%d)\n", __func__, + rqp->qpn, rdev->glb_func_id); + return ret; + } + + ret = roce3_qp_cache_out_cmd(rdev, rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: QP(0x%06x) cache invalid failed, func_id(%d)\n", __func__, rqp->qpn, + rdev->glb_func_id); + return ret; + } + + rqp->qp_state = IB_QPS_RESET; + + if (rqp->ibqp.uobject == NULL) { + ret = roce3_qp_clean_kernel_res(rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Clean kernel QP(0x%06x) failed, func_id(%d)\n", __func__, + rqp->qpn, rdev->glb_func_id); + return ret; + } + } + + return 0; +} + +static int roce3_qp_modify(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask) +{ + int ret = 0; + u32 optpar = 0; + roce_verbs_qp_attr_s qp_attr; + u8 cmd = 0; + + memset(&qp_attr, 0, sizeof(qp_attr)); + + if ((((u32)attr_mask) & IB_QP_MAX_DEST_RD_ATOMIC) != 0) { + ret = roce3_alloc_opt_rdmarc(rqp, attr, attr_mask); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdmarc, func(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + } + + ret = roce3_set_opt_field(rqp, attr, attr_mask, &qp_attr, &optpar); + if (ret != 0) { + goto err_out; + } + + roce3_set_abs_field(rqp, attr, attr_mask, &qp_attr); + + cmd = roce3_get_qp_cmdq_cmd(rdev, rqp, attr, attr_mask); + if (cmd == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Invalid cmd, func_id(%d), qpn(%d), cmd(%d)\n", __func__, + rdev->glb_func_id, rqp->qpn, cmd); + ret = (-EINVAL); + goto err_out; + } + if (cmd == ROCE_CMD_RTS2SQD_QP) { + ret = roce3_qp_rts2sqd_cmd(rdev, rqp, attr, attr_mask); + } else { + ret = roce3_qp_modify_cmd(rdev, rqp, cmd, &qp_attr, optpar); + } + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send modify cmd(%d), func(%d), qpn(%d), ret(%d)\n", + __func__, cmd, rdev->glb_func_id, rqp->qpn, ret); + goto err_out; + } + + roce3_record_opt_field(rqp, attr, attr_mask); + return 0; + +err_out: + if ((((u32)attr_mask) & IB_QP_MAX_DEST_RD_ATOMIC) != 0) { + roce3_free_opt_rdmarc(rqp); + } + + return ret; +} + +static int roce3_qp_get_path(struct roce3_device *rdev, struct roce3_qp *rqp, struct rdma_ah_attr *ah_attr) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + int ret = 0; + u16 vlan_id; + + if ((ah_attr->ah_flags & IB_AH_GRH) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Not supported, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + ret = roce3_resolve_grh(rdev, ah_attr, &vlan_id, NULL); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to find dmac by grh, func_id(%u)\n", __func__, + (u32)rdev->glb_func_id); + return ret; + } +#endif + return 0; +} + +static int roce3_qp_modify_check_rd_and_mtu(const struct roce3_qp *rqp, const struct ib_qp_attr *attr, int attr_mask, + const struct rdma_service_cap *rdma_cap) +{ + enum ib_qp_state cur_state = + (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_CUR_STATE) != 0) ? attr->cur_qp_state : rqp->qp_state); + enum ib_qp_state new_state = + (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_STATE) != 0) ? attr->qp_state : cur_state); + + if (((((u32)attr_mask) & IB_QP_MAX_QP_RD_ATOMIC) != 0) && + (attr->max_rd_atomic > rdma_cap->dev_rdma_cap.roce_own_cap.max_qp_init_rdma)) { + pr_err("[ROCE, ERR] %s: Qpn(0x%x), max_rd_atomic (%d) too large. Transition %d to %d. qp_type(%d)\n", __func__, + rqp->ibqp.qp_num, attr->max_rd_atomic, cur_state, new_state, rqp->ibqp.qp_type); + return -EINVAL; + } + + if (((((u32)attr_mask) & IB_QP_MAX_DEST_RD_ATOMIC) != 0) && + (attr->max_dest_rd_atomic > rdma_cap->dev_rdma_cap.roce_own_cap.max_qp_dest_rdma)) { + pr_err("[ROCE, ERR] %s: Qpn(0x%x), max_dest_rd_atomic (%d) too large. Transition %d to %d. qp_type(%d)\n", + __func__, rqp->ibqp.qp_num, attr->max_dest_rd_atomic, cur_state, new_state, rqp->ibqp.qp_type); + return -EINVAL; + } + + if (((((u32)attr_mask) & IB_QP_PATH_MTU) != 0) && + ((attr->path_mtu < IB_MTU_256) || (attr->path_mtu > IB_MTU_4096))) { + pr_err("[ROCE, ERR] %s: Input path MTU(%u) is invalid\n", __func__, attr->path_mtu); + return -EINVAL; + } + + return 0; +} + +static int roce3_qp_modify_check(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, + struct rdma_service_cap *rdma_cap) +{ + int ret; + enum ib_qp_state cur_state, new_state; + cur_state = (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_CUR_STATE) != 0) ? attr->cur_qp_state : rqp->qp_state); + new_state = (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_STATE) != 0) ? attr->qp_state : cur_state); + + if (!roce3_check_qp_modify_ok(cur_state, new_state, (enum ib_qp_type)(rqp->ibqp.qp_type), + (enum ib_qp_attr_mask)attr_mask, IB_LINK_LAYER_ETHERNET)) { + pr_err("[ROCE, ERR] %s: Qpn(0x%x), invalid attribute mask specified for transition %d to %d, qp_type(%d), " + "attr_mask(0x%x)\n", + __func__, rqp->ibqp.qp_num, cur_state, new_state, rqp->ibqp.qp_type, attr_mask); + return (-EINVAL); + } + + if (((((u32)attr_mask) & IB_QP_PORT) != 0) && (attr->port_num != ROCE_DEFAULT_PORT_NUM)) { + pr_err("[ROCE, ERR] %s: Qpn(0x%x), invalid port number(%d) specified for transition %d to %d. qp_type(%d)\n", + __func__, rqp->ibqp.qp_num, attr->port_num, cur_state, new_state, rqp->ibqp.qp_type); + return (-EINVAL); + } + + if ((((u32)attr_mask) & IB_QP_PKEY_INDEX) != 0) { + if (attr->pkey_index > 0) { + pr_err("[ROCE, ERR] %s: Qpn(0x%x), invalid pkey index (%d) specified for transition %d to %d. " + "qp_type(%d)\n", + __func__, rqp->ibqp.qp_num, attr->pkey_index, cur_state, new_state, rqp->ibqp.qp_type); + return (-EINVAL); + } + } + + ret = roce3_qp_modify_check_rd_and_mtu(rqp, attr, attr_mask, rdma_cap); + + return ret; +} + +#define ROCE3_QP_HANDLE 0 +#define ROCE3_QP_CONTINUE 1 +static int roce3_modify_qp_pre(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata) +{ + int ret; + struct roce3_qp *rqp = NULL; + struct roce3_device *rdev = NULL; + enum ib_qp_state cur_state, new_state; + + rqp = to_roce3_qp(ibqp); + rdev = to_roce3_dev(ibqp->device); + cur_state = (enum ib_qp_state)(((((u32)attr_mask) & IB_QP_CUR_STATE) != 0) ? attr->cur_qp_state : rqp->qp_state); + new_state = ((((u32)attr_mask) & IB_QP_STATE) != 0) ? attr->qp_state : cur_state; + + ret = roce3_qp_modify_check(rqp, attr, attr_mask, &rdev->rdma_cap); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed qp modify check, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + if (new_state == IB_QPS_RESET) { + if (cur_state != new_state) { + ret = roce3_qp_modify_2rst(rdev, rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify 2rst, func_id(%d)\n", __func__, + rdev->glb_func_id); + } + } + return ROCE3_QP_HANDLE; + } + + ret = roce3_qp_modify_pre_extend(rqp, attr, attr_mask, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify extend qp, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + return ROCE3_QP_CONTINUE; +} + +int roce3_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_qp *rqp = NULL; + struct roce3_device *rdev = NULL; + + rqp = to_roce3_qp(ibqp); + rdev = to_roce3_dev(ibqp->device); + + mutex_lock(&rqp->mutex); + + ret = roce3_modify_qp_pre(ibqp, attr, attr_mask, udata); + if ((ret == ROCE3_QP_HANDLE) || (ret < 0)) { + goto out; + } + + if ((((u32)attr_mask) & IB_QP_AV) != 0) { + ret = roce3_qp_get_path(rdev, rqp, &attr->ah_attr); + if (ret != 0) { + goto out; + } + } + + ret = roce3_qp_modify(rdev, rqp, attr, attr_mask); + if (ret != 0) { + goto out; + } + +out: + mutex_unlock(&rqp->mutex); + return ret; +} + +int roce3_send_qp_lb_cmd(u32 qpn, struct roce3_device *rdev, u8 cmd, cqm_cmd_buf_s *buf_in, cqm_cmd_buf_s *buf_out, + u32 timeout) +{ + int ret = 0; + struct timespec64 tv_start; + + ktime_get_ts64(&tv_start); + if ((rdev->cfg_info.lb_en != 0) && (rdev->cfg_info.lb_mode == ROCE_LB_MODE_1)) { + u8 cos = qpn & 0x3; + ret = cqm_lb_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, cmd, cos, buf_in, buf_out, NULL, timeout, + HINIC3_CHANNEL_ROCE); + } else { + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, cmd, buf_in, buf_out, NULL, timeout, HINIC3_CHANNEL_ROCE); + } + + roce3_timeout_check(rdev, &tv_start, CMDQ_SDKCALL_BUTT, 0); + return ret; +} \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_post_recv.c b/drivers/infiniband/hw/hiroce3/qp/roce_qp_post_recv.c new file mode 100644 index 000000000..51310777f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_post_recv.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_post_recv.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/20 + * Description : Define standard kernel RoCE QP Post rq/srq receive wqe functions. + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include <rdma/ib_verbs.h> + +#include "roce_compat.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_mr.h" +#include "roce_xrc.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_qp.h" +#include "roce_main_extension.h" +#ifdef __ROCE_DFX__ +#include "roce_dfx.h" +#endif + +/* **************************************************************************** + Prototype : roce3_get_recv_wqe + Description : roce3_get_recv_wqe + Input : struct roce3_qp *rqp + int n + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +static void *roce3_get_recv_wqe(struct roce3_qp *rqp, u32 n) +{ + return roce3_get_wqe(rqp, rqp->rq.offset + (n << (unsigned)rqp->rq.wqe_shift)); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +static int roce3_post_recv_check_qp(const struct roce3_qp *qp, const struct roce3_device *rdev, + const struct ib_recv_wr **bad_wr, const struct ib_recv_wr *wr) +#else +static int roce3_post_recv_check_qp(const struct roce3_qp *qp, const struct roce3_device *rdev, + struct ib_recv_wr **bad_wr, struct ib_recv_wr *wr) +#endif +{ + if (ROCE_UNLIKELY((qp->qp_type == IB_QPT_XRC_INI) || (qp->qp_type == IB_QPT_XRC_TGT))) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Can't post WQE when TGT XRC QP, func_id(%d)\n", __func__, + rdev->glb_func_id); + *bad_wr = wr; + return -EINVAL; + } + + if (ROCE_UNLIKELY(qp->qp_state == IB_QPS_RESET)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Can't post WQE when QP is RST state, func_id(%d)\n", __func__, + rdev->glb_func_id); + *bad_wr = wr; + return -EINVAL; + } + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +static int roce3_post_recv_check_wr(struct roce3_qp *qp, const struct ib_recv_wr **bad_wr, const struct ib_recv_wr *wr, + u32 wr_num) +#else +static int roce3_post_recv_check_wr(struct roce3_qp *qp, struct ib_recv_wr **bad_wr, struct ib_recv_wr *wr, u32 wr_num) +#endif +{ + if (roce3_wq_overflow(&qp->rq, wr_num, qp->ibqp.recv_cq) != 0) { + /*lint -e160 -e522*/ + pr_err_once("[ROCE, ERR] %s: SQ is full head:%x, tali:%x, wr_num:%d \n", __func__, (&qp->rq)->head, + (&qp->rq)->tail, wr_num); + /*lint +e160 +e522*/ + *bad_wr = wr; + return -ENOMEM; + } + + if (ROCE_UNLIKELY(((u32)wr->num_sge) > qp->rq.max_sge)) { + *bad_wr = wr; + return -EINVAL; + } + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +static int roce3_post_recv_check_length(struct roce3_device *rdev, const struct ib_recv_wr **bad_wr, + const struct ib_recv_wr *wr, int i) +#else +static int roce3_post_recv_check_length(struct roce3_device *rdev, struct ib_recv_wr **bad_wr, + struct ib_recv_wr *wr, int i) +#endif +{ + u32 data_len = 0; + + /* single SGEָ signs data len should less than (2G-1)B */ + if (ROCE_UNLIKELY(wr->sg_list[i].length > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz - 1)) { + *bad_wr = wr; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Sge data len is over range, sg_list(%d), length(0x%x), \ + max_msg_sz(0x%x), func_id(%d)\n", + __func__, i, wr->sg_list[i].length, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz, rdev->glb_func_id); + return -EINVAL; + } + + data_len += wr->sg_list[i].length; + /* all SGEָ signs data len should less than 2GB */ + if (ROCE_UNLIKELY(data_len > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz)) { + *bad_wr = wr; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Data_len is over range, data_len(%d), max_msg_sz(%d), func_id(%d)\n", + __func__, data_len, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz, rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +static int roce3_post_recv_set_data_seg(const struct ib_recv_wr *wr, struct roce3_device *rdev, + const struct ib_recv_wr **bad_wr, struct roce3_qp *qp, u32 index) +#else +static int roce3_post_recv_set_data_seg(struct ib_recv_wr *wr, struct roce3_device *rdev, + struct ib_recv_wr **bad_wr, struct roce3_qp *qp, u32 index) +#endif +{ + int i = 0; + int ret = 0; + struct roce3_wqe_data_seg *dseg = NULL; + + dseg = (struct roce3_wqe_data_seg *)roce3_get_recv_wqe(qp, index); + for (i = 0; i < wr->num_sge; ++i) { + ret = roce3_post_recv_check_length(rdev, bad_wr, wr, i); + if (ret != 0) { + return ret; + } + + roce3_set_data_seg(dseg, wr->sg_list + i); + dseg++; + } + + if (wr->num_sge != 0) { + dseg--; + dseg->key = cpu_to_be32((u32)(wr->sg_list[wr->num_sge - 1].lkey | ROCE_WQE_NEXT_SGE_INVALID)); + } else { + dseg->key = ROCE_WQE_NEXT_SGE_INVALID; + dseg->key = cpu_to_be32(dseg->key); + dseg->dw2.bs.len = 0; + } + + return 0; +} +/* **************************************************************************** + Prototype : roce3_post_recv + Description : roce3_post_recv + Input : struct ib_qp *ibqp + struct ib_recv_wr *wr + struct ib_recv_wr **bad_wr + Output : None + Return Value : + Calls : + Called By : + + History : + 1.Date : 2015/4/29 + Author : + Modification : Created function + +**************************************************************************** */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr) +#else +int roce3_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, struct ib_recv_wr **bad_wr) +#endif +{ + struct roce3_qp *qp = to_roce3_qp(ibqp); + + struct roce3_device *rdev = to_roce3_dev(ibqp->device); + unsigned long flags = 0; + int ret = 0; + u32 wr_num = 0; + u32 index = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) + const struct ib_recv_wr *wr_tmp = wr; +#else + struct ib_recv_wr *wr_tmp = wr; +#endif + ret = roce3_post_recv_check_qp(qp, rdev, bad_wr, wr_tmp); + if (ret != 0) { + return ret; + } + + spin_lock_irqsave(&qp->rq.lock, flags); + + index = (unsigned int)qp->rq.head & ((unsigned int)qp->rq.wqebb_cnt - 1); + + for (wr_num = 0; wr_tmp != NULL; ++wr_num, wr_tmp = wr_tmp->next) { + ret = roce3_post_recv_check_wr(qp, bad_wr, wr_tmp, wr_num); + if (ret != 0) { + goto out; + } + + ret = roce3_post_recv_set_data_seg(wr_tmp, rdev, bad_wr, qp, index); + if (ret != 0) { + goto out; + } + + qp->rq.wrid[index] = wr_tmp->wr_id; + + index = (index + 1) & (qp->rq.wqebb_cnt - 1); + } + +out: + if (ROCE_LIKELY(wr_num != 0)) { + qp->rq.head += (u32)wr_num; + + wmb(); + + /* SQ need head 4B,RQ need tail 4B */ + *(qp->db.db_record + 1) = cpu_to_be32(qp->rq.head & 0xffff); + } + + spin_unlock_irqrestore(&qp->rq.lock, flags); + + return ret; +} + +void roce3_drain_rq(struct ib_qp *ibqp) +{ + +} diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_post_send.c b/drivers/infiniband/hw/hiroce3/qp/roce_qp_post_send.c new file mode 100644 index 000000000..9babf4329 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_post_send.c @@ -0,0 +1,1257 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_post_send.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/11/23 + * Description : Define standard kernel RoCE QP Post send realted functions. + */ + +#include <rdma/ib_verbs.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include "roce_compat.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_mr.h" +#include "roce_user.h" +#include "roce_xrc.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_qp.h" +#include "roce_post.h" +#include "roce_dif_format.h" +#include "roce_main_extension.h" + +#ifdef __ROCE_DFX__ +#include "roce_dfx.h" +#endif + +#define GOTO_LOCAL 1 + +#define GOTO_OUT 2 + +#define ROCE_NEED_JUMP 1 + +#define BYTE_MASK 255 + +#define ROCE_CTRL_SEG_SL 2 +/* **************************************************************************** + Prototype : roce3_get_send_wqe + Description : roce3_get_send_wqe + Input : struct roce3_qp *rqp + u32 n + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +static void *roce3_get_send_wqe(struct roce3_qp *rqp, u32 n) +{ + u32 wqebb_index = (n & (((u32)rqp->sq.wqebb_cnt) - 1)); + u32 wqebb_pos = wqebb_index << rqp->sq.wqe_shift; + return roce3_get_wqe(rqp, rqp->sq.offset + wqebb_pos); +} + +/* **************************************************************************** + Prototype : roce3_wq_overflow + Description : roce3_wq_overflow + Input : struct roce3_wq *wq + int wr_num + struct ib_cq *ibcq + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +int roce3_wq_overflow(struct roce3_wq *wq, u32 wr_num, struct ib_cq *ibcq) +{ + unsigned int cur = 0; + struct roce3_cq *cq = NULL; + + cur = wq->head - wq->tail; + if (ROCE_LIKELY((cur + wr_num) < (unsigned int)wq->max_post)) { + return 0; + } + + cq = to_roce3_cq(ibcq); + spin_lock(&cq->lock); + cur = wq->head - wq->tail; + spin_unlock(&cq->lock); + + return ((cur + (unsigned int)wr_num) >= (unsigned int)wq->max_post); +} + +/* **************************************************************************** + Prototype : roce3_ib_opcode + Description : + Input : + Output : None + Return Value : + Calls : + Called By : + + History : + 1.Date : 2015/7/30 + Author : + Modification : Created function + +**************************************************************************** */ +static const u32 roce3_ib_opcode[] = { + ROCE_WQE_OPCODE_RDMA_WRITE, /* [IB_WR_RDMA_WRITE] : 0 */ + ROCE_WQE_OPCODE_RDMA_WRITE_IMM, /* [IB_WR_RDMA_WRITE_WITH_IMM] : 1 */ + ROCE_WQE_OPCODE_SEND, /* [IB_WR_SEND] : 2 */ + ROCE_WQE_OPCODE_SEND_IMM, /* [IB_WR_SEND_WITH_IMM] : 3 */ + ROCE_WQE_OPCODE_RDMA_READ, /* [IB_WR_RDMA_READ] : 4 */ + ROCE_WQE_OPCODE_ATOMIC_CMP_SWP, /* [IB_WR_ATOMIC_CMP_AND_SWP] : 5 */ + ROCE_WQE_OPCODE_ATOMIC_FETCH_ADD, /* [IB_WR_ATOMIC_FETCH_AND_ADD] : 6 */ + 0, /* [IB_WR_LSO] : 7 NO SUPPORT */ + ROCE_WQE_OPCODE_SEND_INVAL, /* [IB_WR_SEND_WITH_INV] : 8 */ + 0, /* [IB_WR_RDMA_READ_WITH_INV] : 9 */ + ROCE_WQE_OPCODE_LOCAL_INVAL, /* [IB_WR_LOCAL_INV] : 10 */ + ROCE_WQE_OPCODE_FRMR, /* [IB_WR_REG_MR] : 11 */ + ROCE_WQE_OPCODE_MASKED_ATOMIC_CMP_SWP, /* [IBV_EXP_WR_EXT_MASKED_ATOMIC_CMP_AND_SWP] : 12 */ + ROCE_WQE_OPCODE_MASKED_ATOMIC_FETCH_ADD, /* [IBV_EXP_WR_EXT_MASKED_ATOMIC_FETCH_AND_ADD] : 13 */ + ROCE_WQE_OPCODE_REG_SIG_MR, /* [IB_WR_REG_SIG_MR] : 14 */ + + /* 15-64 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, /* IBV_EXP_WR_SEND_ENABLE 96 */ + 0, /* IBV_EXP_WR_RECV_ENABLE 97 */ + 0, /* IBV_EXP_WR_CQE_WAIT 98 */ + + /* ex */ + ROCE_WQE_OPCODE_FRMR, /* [IB_WR_FAST_REG_MR] : 11 */ +}; + +/* **************************************************************************** + Prototype : roce3_set_send_seg + Description : roce3_set_send_seg + Input : struct roce3_wqe_snd_tsk_seg *snd_tsk_seg + struct ib_send_wr *wr + Output : None + + 1.Date : 2017/5/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_send_seg(struct roce3_wqe_send_tsk_seg *snd_tsk_seg, const struct ib_send_wr *wr) +{ + if (wr->opcode == IB_WR_SEND_WITH_IMM) { + snd_tsk_seg->immdata_invkey = wr->ex.imm_data; + } + + if (wr->opcode == IB_WR_SEND_WITH_INV) { + snd_tsk_seg->immdata_invkey = cpu_to_be32(wr->ex.invalidate_rkey); + } +} + +/* **************************************************************************** + Prototype : roce3_set_atomic_seg + Description : roce3_set_atomic_seg + Input : struct roce3_wqe_atomic_tsk_seg *atomic_tsk_seg + struct ib_send_wr *wr + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ + +static void roce3_set_atomic_seg(struct roce3_wqe_atomic_tsk_seg *atomic_tsk_seg, const struct ib_send_wr *wr) +{ + const struct ib_atomic_wr *atomic = ROCE_ATOMIC_WR(wr); + + atomic_tsk_seg->key = cpu_to_be32(atomic->rkey); + atomic_tsk_seg->va = cpu_to_be64(atomic->remote_addr); + + if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) { + atomic_tsk_seg->swap_add_data = cpu_to_be64(atomic->swap); + atomic_tsk_seg->cmp_data = cpu_to_be64(atomic->compare_add); + } else if (wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) { + atomic_tsk_seg->swap_add_data = cpu_to_be64(atomic->compare_add); + atomic_tsk_seg->cmp_data = 0; + } else { + /* IB_WR_MASKED_ATOMIC_FETCH_AND_ADD */ + atomic_tsk_seg->swap_add_data = cpu_to_be64(atomic->compare_add); + atomic_tsk_seg->cmp_data = cpu_to_be64(atomic->compare_add_mask); + } +} + +/* **************************************************************************** + Prototype : roce3_set_masked_atomic_seg + Description : roce3_set_masked_atomic_seg + Input : struct roce3_wqe_mask_atomic_tsk_seg *mask_atomic_tsk_seg + struct ib_send_wr *wr + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_masked_atomic_seg(struct roce3_wqe_mask_atomic_tsk_seg *mask_atomic_tsk_seg, + const struct ib_send_wr *wr) +{ + const struct ib_atomic_wr *atomic = ROCE_ATOMIC_WR(wr); + + mask_atomic_tsk_seg->rkey = cpu_to_be32(atomic->rkey); + mask_atomic_tsk_seg->va = cpu_to_be64(atomic->remote_addr); + + mask_atomic_tsk_seg->swap_add_data = cpu_to_be64(atomic->swap); + mask_atomic_tsk_seg->swap_msk = cpu_to_be64(atomic->swap_mask); + mask_atomic_tsk_seg->cmp_data = cpu_to_be64(atomic->compare_add); + mask_atomic_tsk_seg->cmp_msk = cpu_to_be64(atomic->compare_add_mask); +} + +/* **************************************************************************** + Prototype : roce3_set_rdma_seg + Description : roce3_set_rdma_seg + Input : struct roce3_wqe_rdma_tsk_seg *rdma_tsk_seg + struct ib_send_wr *wr + Output : None + Return Value : + Calls : + Called By : + + History : + 1.Date : 2015/5/26 + Author : + Modification : Created function + +**************************************************************************** */ +static __always_inline void roce3_set_rdma_seg(struct roce3_wqe_rdma_tsk_seg *rdma_tsk_seg, const struct ib_send_wr *wr) +{ + const struct ib_rdma_wr *rdma = ROCE_RDMA_WR(wr); + + rdma_tsk_seg->va = cpu_to_be64(rdma->remote_addr); + rdma_tsk_seg->rkey = cpu_to_be32(rdma->rkey); + + if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) { + rdma_tsk_seg->imm_data = wr->ex.imm_data; + } +} + +/* **************************************************************************** + Prototype : roce3_set_local_inv_seg + Description : roce3_set_local_inv_seg + Input : struct roce3_wqe_local_inv_tsk_seg *inv_tsk_seg + struct ib_send_wr *wr + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_local_inv_seg(struct roce3_wqe_local_inv_tsk_seg *inv_tsk_seg, const struct ib_send_wr *wr) +{ + inv_tsk_seg->inv_key = cpu_to_be32(wr->ex.invalidate_rkey); +} + +/* **************************************************************************** + Prototype : roce3_set_ud_seg_cycle1 + Description : set ud type task segment before cycled + Input : struct roce3_wqe_ud_tsk_seg_cycle1 *ud_tsk_seg_cycle1 + struct ib_send_wr *wr + Output : None + + 1.Date : 2015/8/8 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_ud_seg_cycle1(struct roce3_wqe_ud_tsk_seg_cycle1 *ud_tsk_seg_cycle1, const struct ib_send_wr *wr) +{ + const struct ib_ud_wr *ud = ROCE_UD_WR(wr); + struct roce3_ah *rah = to_roce3_ah(ud->ah); + + if (wr->opcode == IB_WR_SEND_WITH_IMM) { + ud_tsk_seg_cycle1->immdata_invkey = wr->ex.imm_data; + } + + ud_tsk_seg_cycle1->dw2.value = rah->priv_ah.dw0.value; + ud_tsk_seg_cycle1->dw3.value = rah->priv_ah.dw1.value; + ud_tsk_seg_cycle1->dw4.value = rah->priv_ah.dw2.value; + memcpy((void *)ud_tsk_seg_cycle1->dgid, (void *)rah->priv_ah.dgid, ROCE_GID_LEN); + ud_tsk_seg_cycle1->dw9.value = cpu_to_be32(ud->remote_qpn); + ud_tsk_seg_cycle1->qkey = cpu_to_be32(ud->remote_qkey); +} + +/* **************************************************************************** + Prototype : roce3_set_ud_seg_cycle2 + Description : set ud type task segment after cycled + Input : struct roce3_wqe_ud_tsk_seg_cycle2 *ud_tsk_seg_cycle2 + struct ib_send_wr *wr + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_ud_seg_cycle2(struct roce3_wqe_ud_tsk_seg_cycle2 *ud_tsk_seg_cycle2, const struct ib_send_wr *wr) +{ + const struct ib_ud_wr *ud = ROCE_UD_WR(wr); + struct roce3_ah *rah = to_roce3_ah(ud->ah); + + ud_tsk_seg_cycle2->dw0.value = rah->priv_ah.dw7.value; + ud_tsk_seg_cycle2->dmac_l32 = rah->priv_ah.dmac_l32; +} + +/* **************************************************************************** + Prototype : roce3_set_ud_seg + Description : roce3_set_ud_seg + Input : struct roce3_wqe_ud_tsk_seg *ud_tsk_seg + struct ib_send_wr *wr + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_ud_seg(struct roce3_wqe_ud_tsk_seg *ud_tsk_seg, const struct ib_send_wr *wr) +{ + const struct ib_ud_wr *ud = ROCE_UD_WR(wr); + struct roce3_ah *rah = to_roce3_ah(ud->ah); + + if (wr->opcode == IB_WR_SEND_WITH_IMM) { + ud_tsk_seg->immdata_invkey = wr->ex.imm_data; + } + + ud_tsk_seg->dw3.value = rah->priv_ah.dw0.value; + ud_tsk_seg->dw4.value = rah->priv_ah.dw1.value; + ud_tsk_seg->dw5.value = rah->priv_ah.dw2.value; + memcpy((void *)ud_tsk_seg->dgid, (void *)rah->priv_ah.dgid, + sizeof(ud_tsk_seg->dgid)); + ud_tsk_seg->dw10.value = cpu_to_be32(ud->remote_qpn); + ud_tsk_seg->qkey = cpu_to_be32(ud->remote_qkey); + ud_tsk_seg->dw12.value = rah->priv_ah.dw7.value; + ud_tsk_seg->dmac_l32 = rah->priv_ah.dmac_l32; +} + +/* **************************************************************************** + Prototype : roce3_set_data_seg + Description : roce3_set_data_seg + Input : struct roce3_wqe_data_seg *dseg + struct ib_sge *sge + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +void roce3_set_data_seg(struct roce3_wqe_data_seg *dseg, struct ib_sge *sge) +{ + dseg->addr = cpu_to_be64(sge->addr); + + dseg->dw2.bs.len = sge->length & 0x7fffffff; + dseg->dw2.bs.rsvd = 0; + + dseg->dw2.value = cpu_to_be32(dseg->dw2.value); + + dseg->key = cpu_to_be32(sge->lkey); +} + +static void roce3_set_dwqe_db(struct roce3_qp *qp, struct roce3_wqe_ctrl_seg *ctrl_seg, unsigned int index) +{ + struct roce3_device *rdev = to_roce3_dev(qp->ibqp.device); + + ctrl_seg->dw2.bs.qpn = qp->qpn & 0xfffff; + ctrl_seg->dw2.bs.ctx_size = 1; /* 512B */ + ctrl_seg->dw2.bs.cp_flag = 0; + ctrl_seg->dw2.bs.cos = roce3_get_db_cos_from_vlan_pri(rdev, qp->sl & 0x7); + ctrl_seg->dw2.bs.type = ROCE_SQ_DB_TYPE; + + ctrl_seg->dw3.bs.pi = index & 0xffff; + ctrl_seg->dw3.bs.sub_type = 0; + + ctrl_seg->dw3.bs.mtu_shift = qp->db_path_mtu; + ctrl_seg->dw3.bs.sgid_index = qp->db_sgid_index; + if (qp->qp_type == IB_QPT_RC) { + // ctrl_seg->dw3.bs.rc_flag = 1; + } else if (qp->qp_type == IB_QPT_UD) { + // ctrl_seg->dw3.bs.ud_vld = 1; + ctrl_seg->dw3.bs.mtu_shift = 3; + } else if (qp->qp_type == IB_QPT_XRC_INI || qp->qp_type == IB_QPT_XRC_TGT) { + ctrl_seg->dw3.bs.xrc_vld = 1; + // ctrl_seg->dw3.bs.rc_flag = 1; + } + // ctrl_seg->dw3.bs.local_trans = 0; + + ctrl_seg->dw1.value = cpu_to_be32(ctrl_seg->dw1.value); + ctrl_seg->dw2.value = cpu_to_be32(ctrl_seg->dw2.value); + ctrl_seg->dw3.value = cpu_to_be32(ctrl_seg->dw3.value); +} + +static void roce3_set_sq_db(struct roce3_qp *qp, struct roce_sq_db_seg *db, unsigned int index) +{ + struct roce3_device *rdev = to_roce3_dev(qp->ibqp.device); + + db->dw0.bs.qpn = qp->qpn & 0xfffff; + db->dw0.bs.ctx_size = 1; /* 512B */ + db->dw0.bs.cp_flag = 0; + db->dw0.bs.cos = roce3_get_db_cos_from_vlan_pri(rdev, qp->sl & 0x7); + db->dw0.bs.type = ROCE_SQ_DB_TYPE; + + db->dw1.bs.pi = ((index & 0xffff) >> 8) & 0xff; /* 8bits */ + db->dw1.bs.sub_type = 0; + db->dw1.bs.mtu_shift = qp->db_path_mtu; + db->dw1.bs.sgid_index = qp->db_sgid_index; + if (qp->qp_type == IB_QPT_RC) { + } else if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) { + db->dw1.bs.mtu_shift = ROCE_UD_MTU_SHIFT; + } else if (qp->qp_type == IB_QPT_XRC_INI || qp->qp_type == IB_QPT_XRC_TGT) { + db->dw1.bs.xrc_vld = 1; + } + + db->dw0.value = roce3_convert_be32(db->dw0.value); + db->dw1.value = roce3_convert_be32(db->dw1.value); +} + +static void roce3_set_inline_data(void *start_addr, struct ib_sge *sge) +{ + memcpy(start_addr, (void *)(uintptr_t)sge->addr, sge->length); +} + +static void roce3_set_inline_data_cycle1(void *start_addr, struct ib_sge *sge, u32 size) +{ + memcpy(start_addr, (void *)(uintptr_t)sge->addr, size); +} + +static void roce3_set_inline_data_cycle2(void *start_addr, struct ib_sge *sge, u32 size) +{ + memcpy(start_addr, (void *)((u8 *)(void *)(uintptr_t)sge->addr + size), size); +} + +/* **************************************************************************** + Prototype : roce3_dwqe_copy + Description : roce3_dwqe_copy + Input : unsigned long *dst + unsigned long *src + unsigned int bytecnt + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +/* + * Avoid using memcpy() to copy to DWQE Page, since memcpy() + * implementations may use move-string-buffer assembler instructions, + * which do not guarantee order of copying. + * 假设DWQE页首地址是VA，WQE大小为size，WQE地址为wqe + size=64, iowrite64_copy(va + 256, wqe, size) + size=128, iowrite64_copy(va + 256*2, wqe, size) + size=192, iowrite64_copy(va + 256*3, wqe, size) + 当前芯片支持，但软件wqe_size按2的幂对齐，用不上，可不考虑 + size=256, __iowrite64_copy(va, wqe, size) + + formula: + __iowrite64_copy(va + ((size & 255) << 2), wqe, size) + */ +static void roce3_dwqe_copy(unsigned long *dst, unsigned long *src, unsigned int bytecnt) +{ + unsigned long *src_tmp = src; + unsigned int bytecnt_tmp = bytecnt; + unsigned long *dst_tmp = (unsigned long *)((u64)dst + ((bytecnt_tmp & BYTE_MASK) << 2)); // 2 is addr offset + + while ((int)bytecnt_tmp > 0) { + wmb(); + *dst_tmp++ = *src_tmp++; + bytecnt_tmp -= (unsigned int)sizeof(u64); + } +} + +/* **************************************************************************** + Prototype : roce3_set_gsi_seg + Input : struct roce3_sqp *sqp + struct ib_send_wr *wr + void *wqe + Output : None + + 1.Date : 2015/8/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_set_gsi_seg(struct roce3_sqp *sqp, const struct ib_send_wr *wr, void *wqe) +{ + struct roce3_wqe_ud_tsk_seg *ud_tsk_seg = (struct roce3_wqe_ud_tsk_seg *)wqe; + struct ib_ud_wr *ud_wr = (struct ib_ud_wr *)(void *)wr; + struct roce3_ah *rah = to_roce3_ah(ud_wr->ah); + + if (wr->opcode == IB_WR_SEND_WITH_IMM) { + ud_tsk_seg->immdata_invkey = wr->ex.imm_data; + ud_tsk_seg->dw2.bs.last_ext_len = ROCE_IMM_EXT_LEN; + ud_tsk_seg->dw2.value = cpu_to_be32(ud_tsk_seg->dw2.value); + } + + ud_tsk_seg->common.bs.c = 1; + ud_tsk_seg->dw3.value = rah->priv_ah.dw0.value; + ud_tsk_seg->dw4.value = rah->priv_ah.dw1.value; + ud_tsk_seg->dw5.value = rah->priv_ah.dw2.value; + memcpy((void *)ud_tsk_seg->dgid, (void *)rah->priv_ah.dgid, + sizeof(ud_tsk_seg->dgid)); + ud_tsk_seg->dw10.value = cpu_to_be32(ud_wr->remote_qpn); + ud_tsk_seg->qkey = cpu_to_be32(((ud_wr->remote_qkey & 0x80000000) != 0) ? sqp->qkey : ud_wr->remote_qkey); + ud_tsk_seg->dw12.value = rah->priv_ah.dw7.value; + ud_tsk_seg->dmac_l32 = rah->priv_ah.dmac_l32; + + return; +} + +/* **************************************************************************** + Prototype : write_invalid_wqe + Description : set the next wqe invalidate + Input : struct roce3_qp *qp + u32 index + Output : None + + 1.Date : 2015/9/8 + Modification : Created function + +**************************************************************************** */ +static void write_invalid_wqe(struct roce3_qp *qp, u32 index) +{ + u32 invalid_wqe_dw0 = 0; + struct roce3_wqe_ctrl_seg *ctrl_seg = NULL; + + ctrl_seg = (struct roce3_wqe_ctrl_seg *)roce3_get_send_wqe(qp, index); + invalid_wqe_dw0 = ((index & (u32)qp->sq.wqebb_cnt) == 0) ? 0xff000000 : 0x7f000000; + ctrl_seg->dw0.value = cpu_to_be32(invalid_wqe_dw0); +} + +/* **************************************************************************** + Prototype : roce3_validate_wr + Description : roce3_validate_wr + Input : struct roce3_qp *rqp + struct ib_send_wr *wr + int wr_num + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_validate_wr(struct roce3_qp *rqp, const struct ib_send_wr *wr, u32 wr_num) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +#define IB_WR_REG_SIG_MR IB_WR_REG_MR_INTEGRITY +#endif + if (roce3_wq_overflow(&rqp->sq, wr_num, rqp->ibqp.send_cq) != 0) { + pr_err("[ROCE] %s: SQ is full\n", __func__); + return -ENOMEM; + } + + if (ROCE_UNLIKELY(((u32)wr->num_sge) > rqp->sq.max_sge)) { + pr_err("[ROCE, ERR] %s: Sge num is invalide, wr->num_sge(%d), rqp->sq.max_sge(%d)\n", __func__, wr->num_sge, + rqp->sq.max_sge); + return -EINVAL; + } + + if (ROCE_UNLIKELY((wr->opcode == IB_WR_LSO) || (wr->opcode > IB_WR_REG_SIG_MR))) { + pr_err("[ROCE, ERR] %s: wr->opcode(%d)\n", __func__, wr->opcode); + return -EINVAL; + } + + return 0; +} + +static void roce3_set_rc_wqe_for_optype_send(const struct ib_send_wr *wr, struct roce3_post_send_normal_param *param) +{ + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_SEND_LOCAL_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + roce3_set_send_seg((struct roce3_wqe_send_tsk_seg *)param->wqe, wr); + param->data_len_addr = &((struct roce3_wqe_send_tsk_seg *)param->wqe)->data_len; + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_send_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_send_tsk_seg); +} + +static void roce3_set_rc_wqe_for_optype_atomic(const struct ib_send_wr *wr, struct roce3_post_send_normal_param *param) +{ + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_RDMA_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + roce3_set_atomic_seg((struct roce3_wqe_atomic_tsk_seg *)param->wqe, wr); + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_atomic_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_atomic_tsk_seg); +} + +static void roce3_set_rc_wqe_for_optype_cmp_and_swap(const struct ib_send_wr *wr, + struct roce3_post_send_normal_param *param) +{ + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_ATOMIC_CWP_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + roce3_set_masked_atomic_seg((struct roce3_wqe_mask_atomic_tsk_seg *)param->wqe, wr); + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_mask_atomic_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_atomic_tsk_seg); +} + +static void roce3_set_rc_wqe_for_optype_write(const struct ib_send_wr *wr, struct roce3_post_send_normal_param *param) +{ + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_RDMA_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + roce3_set_rdma_seg((struct roce3_wqe_rdma_tsk_seg *)param->wqe, wr); + param->data_len_addr = &((struct roce3_wqe_rdma_tsk_seg *)param->wqe)->data_len; + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_rdma_tsk_seg)); + param->wqe_size += (u32)(sizeof(struct roce3_wqe_rdma_tsk_seg)); +} + +static void roce3_set_rc_wqe_for_optype_local(const struct ib_send_wr *wr, struct roce3_post_send_normal_param *param) +{ + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_SEND_LOCAL_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + param->tsk_com_seg->bs.so = 1; + roce3_set_local_inv_seg((struct roce3_wqe_local_inv_tsk_seg *)param->wqe, wr); + param->wqe_size += (u32)sizeof(struct roce3_wqe_local_inv_tsk_seg); + param->inline_flag = 0; + param->ctrl_seg_tmp.dw0.bs.df = 0; +} + +static void roce3_set_wqe_last_len(u8 *wqe) +{ + struct roce3_wqe_send_tsk_seg *snd_task = (struct roce3_wqe_send_tsk_seg *)(void *)wqe; + snd_task->dw3.value = 0; + snd_task->dw3.bs.last_ext_len = ROCE_IMM_EXT_LEN; + snd_task->dw3.value = cpu_to_be32(snd_task->dw3.value); +} + +static inline u32 roce3_log2(u32 x) +{ + u32 shift; + + for (shift = 0; (1U << shift) < x; ++shift) { + ; + } + + return shift; +} + +static int set_frmr_wqe_section(const struct ib_send_wr *wr, struct roce3_post_send_normal_param *param) +{ + u64 iova; + u32 fbo; + u32 page_num; + struct ib_reg_wr *frmr_reg_wr = NULL; + struct roce3_mr *roce3_kernel_frmr = NULL; + struct roce3_wqe_frmr_tsk_seg *frmr_wqe_task = NULL; + + frmr_reg_wr = (struct ib_reg_wr *)reg_wr(wr); //lint !e605 + + roce3_kernel_frmr = to_roce3_mr(frmr_reg_wr->mr); + page_num = (u32)((frmr_reg_wr->mr->length + frmr_reg_wr->mr->page_size - 1) / frmr_reg_wr->mr->page_size); + if (page_num > ROCE_FRMR_MAX_PAGES) { + return -EINVAL; + } + + /* base section set */ + param->wqe_size += sizeof(struct roce3_wqe_frmr_tsk_seg); + + frmr_wqe_task = (struct roce3_wqe_frmr_tsk_seg *)((void *)param->tsk_com_seg); + + param->dseg = (roce3_wqe_data_seg_s *) (((u8 *)param->tsk_com_seg) + sizeof(struct roce3_wqe_frmr_tsk_seg)); + + param->ctrl_seg_tmp.dw0.bs.tsl = sizeof(struct roce3_wqe_frmr_tsk_seg) / ROCE_TASK_SEG_ALIGN; + /* fill wqe ctrl head section:cl bit */ + param->ctrl_seg_tmp.dw1.bs.cl = 1; //lint !e572 !e778 !e845 + + /* local invalidate associated section set */ + param->tsk_com_seg->bs.so = 1; + + iova = (u64)(void *)(frmr_reg_wr->mr->iova); + fbo = (u32)(iova & (FRMR_PAGE_SIZE - 1)); + frmr_wqe_task->dw2.bs.fbo = fbo & 0x3FFFFF; + frmr_wqe_task->dw2.value = cpu_to_be32(frmr_wqe_task->dw2.value); + + frmr_wqe_task->dw5.va = ((u32)frmr_reg_wr->access & IB_ZERO_BASED) ? 0 : cpu_to_be64(iova); + + /* 填写访问权限 */ + frmr_wqe_task->dw3.bs.zbva = (u32)(!!((u32)frmr_reg_wr->access & IB_ZERO_BASED)); + frmr_wqe_task->dw3.bs.be = (u32)(!!((u32)frmr_reg_wr->access & IB_ACCESS_MW_BIND)); /* 绑定操作使能 */ + frmr_wqe_task->dw3.bs.lre = 1; /* 本地读使能 */ + frmr_wqe_task->dw3.bs.lwe = (u32)(!!((u32)frmr_reg_wr->access & IB_ACCESS_LOCAL_WRITE)); /* 本地写使能 */ + frmr_wqe_task->dw3.bs.rre = (u32)(!!((u32)frmr_reg_wr->access & IB_ACCESS_REMOTE_READ)); /* 远端读使能 */ + frmr_wqe_task->dw3.bs.rwe = (u32)(!!((u32)frmr_reg_wr->access & IB_ACCESS_REMOTE_WRITE)); /* 远端写使能 */ + frmr_wqe_task->dw3.bs.rae = (u32)(!!((u32)frmr_reg_wr->access & IB_ACCESS_REMOTE_ATOMIC)); /* 远端Atomic使能 */ + frmr_wqe_task->dw3.bs.block = 1; + frmr_wqe_task->dw3.bs.rsvd = 0; + frmr_wqe_task->dw3.bs.pa_num = page_num; + /* MR内存页大小。equals to (2^page_size)*4KB */ + frmr_wqe_task->dw3.bs.page_size = roce3_log2(frmr_reg_wr->mr->page_size) - PAGE_4K_SHIFT; + frmr_wqe_task->dw3.value = cpu_to_be32(frmr_wqe_task->dw3.value); + + frmr_wqe_task->m_key = cpu_to_be32(frmr_reg_wr->key); + frmr_wqe_task->dw7.len = cpu_to_be64(frmr_reg_wr->mr->length); + frmr_wqe_task->dw9.pbl_addr = cpu_to_be64(roce3_kernel_frmr->page_map); + /* set inline and direct wqe handle section */ + frmr_wqe_task->rsvd[0] = 0; + frmr_wqe_task->rsvd[1] = 0; + + param->inline_flag = 0; + + return 0; +} + + +static int roce3_post_send_rc(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + const struct ib_send_wr *wr) +{ + int ret = 0; + switch (wr->opcode) { + case IB_WR_SEND_WITH_IMM: + case IB_WR_SEND_WITH_INV: + roce3_set_wqe_last_len(param->wqe); + roce3_set_rc_wqe_for_optype_send(wr, param); + break; + case IB_WR_SEND: + roce3_set_rc_wqe_for_optype_send(wr, param); + break; + + case IB_WR_ATOMIC_CMP_AND_SWP: + case IB_WR_ATOMIC_FETCH_AND_ADD: + case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: + roce3_set_rc_wqe_for_optype_atomic(wr, param); + break; + + case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: + roce3_set_rc_wqe_for_optype_cmp_and_swap(wr, param); + break; + + case IB_WR_RDMA_WRITE_WITH_IMM: + roce3_set_wqe_last_len(param->wqe); + roce3_set_rc_wqe_for_optype_write(wr, param); + break; + + case IB_WR_RDMA_READ: + case IB_WR_RDMA_WRITE: + roce3_set_rc_wqe_for_optype_write(wr, param); + break; + + case IB_WR_LOCAL_INV: + roce3_set_rc_wqe_for_optype_local(wr, param); + ret = ROCE_NEED_JUMP; + break; + + case IB_WR_REG_MR: + set_frmr_wqe_section(wr, param); + ret = ROCE_NEED_JUMP; + break; + + default: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Invalid opcode, func_id(%d)\n", __func__, rdev->glb_func_id); + break; + } + + return ret; +} + +static int roce3_post_send_uc(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + const struct ib_send_wr *wr) +{ + switch (wr->opcode) { + case IB_WR_SEND_WITH_IMM: + case IB_WR_SEND: + if (wr->opcode == IB_WR_SEND_WITH_IMM) { + roce3_set_wqe_last_len(param->wqe); + } + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_SEND_LOCAL_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + roce3_set_send_seg((struct roce3_wqe_send_tsk_seg *)param->wqe, wr); + param->data_len_addr = &((struct roce3_wqe_send_tsk_seg *)param->wqe)->data_len; + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_send_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_send_tsk_seg); + break; + + case IB_WR_RDMA_WRITE_WITH_IMM: + case IB_WR_RDMA_WRITE: + if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) { + roce3_set_wqe_last_len(param->wqe); + } + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_RDMA_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + roce3_set_rdma_seg((struct roce3_wqe_rdma_tsk_seg *)param->wqe, wr); + param->data_len_addr = &((struct roce3_wqe_rdma_tsk_seg *)param->wqe)->data_len; + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_rdma_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_rdma_tsk_seg); + break; + + case IB_WR_LOCAL_INV: + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_SEND_LOCAL_WQE_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + param->tsk_com_seg->bs.so = 1; + roce3_set_local_inv_seg((struct roce3_wqe_local_inv_tsk_seg *)param->wqe, wr); + param->wqe_size += (u32)sizeof(struct roce3_wqe_local_inv_tsk_seg); + return ROCE_NEED_JUMP; + + default: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Invalid opcode, func_id(%d)\n", __func__, rdev->glb_func_id); + break; + } + + return 0; +} + +static int roce3_post_send_ud(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + struct roce3_qp *rqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +{ + struct roce3_wqe_ud_tsk_seg *tsk_sg = (struct roce3_wqe_ud_tsk_seg *)param->wqe; + + if (ROCE_UNLIKELY((wr->opcode != IB_WR_SEND) && (wr->opcode != IB_WR_SEND_WITH_IMM))) { + // ret = -EINVAL; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Wr->opcode(%d), func_id(%d)\n", __func__, wr->opcode, + rdev->glb_func_id); + *bad_wr = wr; + return ROCE_NEED_JUMP; + } + + if (wr->opcode == IB_WR_SEND_WITH_IMM) { + tsk_sg->dw2.bs.last_ext_len = ROCE_IMM_EXT_LEN; + tsk_sg->dw2.value = cpu_to_be32(tsk_sg->dw2.value); + } + + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_UD_WQE_COM_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + param->data_len_addr = &((struct roce3_wqe_ud_tsk_seg *)param->wqe)->data_len; + + if (param->sq_rmd_size > (1UL << (unsigned int)rqp->sq.wqe_shift)) { + roce3_set_ud_seg((struct roce3_wqe_ud_tsk_seg *)(param->wqe), wr); + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_ud_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_ud_tsk_seg); + } else { + roce3_set_ud_seg_cycle1((struct roce3_wqe_ud_tsk_seg_cycle1 *)param->wqe, wr); + param->wqe = rqp->sq_head_addr; + param->wqe_size += (u32)sizeof(struct roce3_wqe_ud_tsk_seg_cycle1); + roce3_set_ud_seg_cycle2((struct roce3_wqe_ud_tsk_seg_cycle2 *)param->wqe, wr); + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_ud_tsk_seg_cycle2)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_ud_tsk_seg_cycle2); + } + + return 0; +} + +static void roce3_post_send_set_normal_data_seg(const struct ib_send_wr *wr, struct roce3_wqe_data_seg **dseg, + struct roce3_qp *rqp) +{ + if (wr->num_sge != 0) { + if ((u8 *)(*dseg) == rqp->sq_head_addr) { + *dseg = (struct roce3_wqe_data_seg *)((void *)(rqp->sq_tail_addr - sizeof(struct roce3_wqe_data_seg))); + } else { + (*dseg)--; + } + (*dseg)->key = (u32)wr->sg_list[wr->num_sge - 1].lkey | ROCE_WQE_NEXT_SGE_INVALID; + (*dseg)->key = cpu_to_be32((*dseg)->key); + } +} + +static int roce3_post_send_set_normal_sge(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + struct roce3_qp *rqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +{ + int i; + + param->data_len = 0; + param->dseg = (struct roce3_wqe_data_seg *)param->wqe; + param->wqe_size += (u32)(wr->num_sge * (int)sizeof(struct roce3_wqe_data_seg)); + for (i = 0; i < wr->num_sge; ++i) { + if (param->sq_rmd_size < sizeof(struct roce3_wqe_data_seg)) { + param->dseg = (struct roce3_wqe_data_seg *)((void *)rqp->sq_head_addr); + } + + if (ROCE_UNLIKELY(wr->sg_list[i].length > (rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz))) { + *bad_wr = wr; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Sge_data length is over range, sg_list(%d), \ + length(0x%x), max_msg_sz(0x%x), func_id(%d)\n", + __func__, i, wr->sg_list[i].length, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz, + rdev->glb_func_id); + return ROCE_NEED_JUMP; + } + + param->data_len += wr->sg_list[i].length; + if (ROCE_UNLIKELY(param->data_len > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz)) { + *bad_wr = wr; + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Data len is over range, data_len(%d), max_msg_sz(%d), func_id(%d)\n", __func__, + param->data_len, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz, rdev->glb_func_id); + return ROCE_NEED_JUMP; + } + roce3_set_data_seg(param->dseg, wr->sg_list + i); + + (param->dseg)++; + param->sq_rmd_size = (u32)(rqp->sq_tail_addr - (u8 *)param->dseg); + } + + return 0; +} + +static void roce3_copy_inline_data(struct roce3_post_send_normal_param *param, const struct ib_send_wr *wr, + struct roce3_qp *rqp, int i) +{ + if (param->sq_rmd_size >= wr->sg_list[i].length) { + roce3_set_inline_data(param->wqe, wr->sg_list + i); + param->wqe = ((u8 *)param->wqe + wr->sg_list[i].length); + if ((u8 *)param->wqe == rqp->sq_tail_addr) { + param->wqe = rqp->sq_head_addr; + } + } else { + roce3_set_inline_data_cycle1(param->wqe, wr->sg_list + i, param->sq_rmd_size); + param->wqe = rqp->sq_head_addr; + + roce3_set_inline_data_cycle2(param->wqe, wr->sg_list + i, wr->sg_list[i].length - param->sq_rmd_size); + param->wqe = ((u8 *)param->wqe + wr->sg_list[i].length - param->sq_rmd_size); + + param->cycle = 1; + } +} + +static int roce3_post_send_set_data_seg(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + struct roce3_qp *rqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +{ + int i; + int ret; + + if ((((unsigned int)wr->send_flags & (unsigned int)IB_SEND_INLINE) != 0) && (wr->num_sge != 0) && + (param->inline_flag != 0)) { + param->data_len = 0; + + for (i = 0; i < wr->num_sge; ++i) { + param->wqe_size += wr->sg_list[i].length; + param->data_len += wr->sg_list[i].length; + if (param->data_len > rqp->max_inline_data) { + *bad_wr = wr; + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Data len is too big, data_len(%d), max_inline_data(%d), func_id(%d)\n", __func__, + param->data_len, rqp->max_inline_data, rdev->glb_func_id); + return ROCE_NEED_JUMP; + } + + if ((u8 *)param->wqe == rqp->sq_head_addr) { + param->cycle = 1; + } + + roce3_copy_inline_data(param, wr, rqp, i); + + param->sq_rmd_size = (u32)(rqp->sq_tail_addr - (u8 *)param->wqe); + } + param->ctrl_seg_tmp.dw0.bs.bdsl = + (ALIGN((u32)(param->data_len), ROCE_TASK_SEG_ALIGN) / ROCE_TASK_SEG_ALIGN) & 0x7ff; + param->ctrl_seg_tmp.dw0.bs.df = 1; + param->inline_flag = 1; + } else { + ret = roce3_post_send_set_normal_sge(param, rdev, rqp, wr, bad_wr); + if (ret != 0) { + return ret; + } + + roce3_post_send_set_normal_data_seg(wr, ¶m->dseg, rqp); + + param->ctrl_seg_tmp.dw0.bs.bdsl = + (u32)((wr->num_sge * (int)sizeof(struct roce3_wqe_data_seg)) / ROCE_TASK_SEG_ALIGN) & 0x7ff; + param->ctrl_seg_tmp.dw0.bs.df = 0; + } + + return 0; +} + +static int roce3_post_send_ring_db(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + struct roce3_qp *rqp) +{ + int ret = 0; + + if ((rdev->kernel_dwqe_map != NULL) && (param->wr_num == 1) && (param->inline_flag != 0) && + (param->wqe_size > (u32)sizeof(struct roce3_wqe_ctrl_seg)) && ((int)param->wqe_size <= rqp->max_dwqe_size) && + (param->cycle == 0)) { + wmb(); + + param->ctrl_seg->dw1.value = be32_to_cpu(param->ctrl_seg->dw1.value); + param->ctrl_seg->dw1.bs.mask_pi = (u32)((param->index & ((unsigned)rqp->sq.wqebb_cnt - 1)) & 0xfffff); + + roce3_set_dwqe_db(rqp, param->ctrl_seg, param->index); + + param->wqe_size = ALIGN((u32)param->wqe_size, ROCE_SQ_WQEBB_SIZE); + + *(rqp->db.db_record) = cpu_to_be32(param->index); + + wmb(); + + ++rqp->sq.head; + roce3_dwqe_copy((unsigned long *)rdev->kernel_dwqe_map, (unsigned long *)param->ctrl_seg, (u32)param->wqe_size); + wc_wmb(); + } else if (param->wr_num != 0) { + rqp->sq.head += param->wr_num; + + wmb(); + + memset(&(param->sq_db.sq_db_val), 0, sizeof(u64)); + roce3_set_sq_db(rqp, &(param->sq_db.sq_db_seg), param->index); + + *(rqp->db.db_record) = cpu_to_be32(param->index & 0xffff); + + wmb(); + ret = cqm_ring_hardware_db(rdev->hwdev, SERVICE_T_ROCE, param->index & 0xff, param->sq_db.sq_db_val); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + wmb(); +#else + /* + * Make sure doorbells don't leak out of SQ spinlock + * and reach the HCA out of order. + */ + mmiowb(); +#endif + } + + return ret; +} + +static void roce3_fill_task_data_len(u32 *data_len_addr, u32 data_len) +{ + if (data_len_addr) { + *data_len_addr = cpu_to_be32(data_len); + } +} + +static int roce3_construct_wqe(struct roce3_post_send_normal_param *param, struct roce3_device *rdev, + struct roce3_qp *rqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +{ + int need_goto = 0; + + switch (rqp->qp_type) { + case IB_QPT_RC: + need_goto = roce3_post_send_rc(param, rdev, wr); + if (need_goto == ROCE_NEED_JUMP) { + return GOTO_LOCAL; + } + break; + + case IB_QPT_UC: + need_goto = roce3_post_send_uc(param, rdev, wr); + if (need_goto == ROCE_NEED_JUMP) { + return GOTO_LOCAL; + } + break; + + case IB_QPT_UD: + need_goto = roce3_post_send_ud(param, rdev, rqp, wr, bad_wr); + if (need_goto == ROCE_NEED_JUMP) { + // ret = -EINVAL; + return GOTO_OUT; + } + break; + + case IB_QPT_GSI: + param->ctrl_seg_tmp.dw0.bs.tsl = ROCE_UD_WQE_COM_TSL; + param->ctrl_seg_tmp.dw1.bs.cl = 1; + + roce3_set_gsi_seg(to_roce3_sqp(rqp), wr, param->wqe); + + param->data_len_addr = &((struct roce3_wqe_ud_tsk_seg *)param->wqe)->data_len; + param->wqe = ((u8 *)param->wqe + sizeof(struct roce3_wqe_ud_tsk_seg)); + param->wqe_size += (u32)sizeof(struct roce3_wqe_ud_tsk_seg); + break; + + default: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Unknown qp type, func_id(%d)\n", __func__, rdev->glb_func_id); + break; + } + + return 0; +} + +static void roce3_init_ctrl_seg(struct roce3_post_send_normal_param *param, const struct ib_send_wr *wr, + const struct roce3_qp *rqp) +{ + param->ctrl_seg_tmp.dw0.bs.owner = ((param->index & (u32)rqp->sq.wqebb_cnt) != 0) ? 1 : 0; + param->ctrl_seg_tmp.dw0.bs.drvsl = 0; + param->ctrl_seg_tmp.dw0.bs.wf = 0; + param->ctrl_seg_tmp.dw0.bs.cf = 0; + param->ctrl_seg_tmp.dw0.bs.va = 1; + param->ctrl_seg_tmp.dw0.bs.df = 0; /* va:1bits, 0-sge,1-inline */ + param->ctrl_seg_tmp.dw0.bs.cr = (u32)(!(((((u32)wr->send_flags) & IB_SEND_SIGNALED) | rqp->sq_signal_bits) == 0)); + param->ctrl_seg_tmp.dw0.bs.difsl = 0; + param->ctrl_seg_tmp.dw0.bs.csl = 0; + param->ctrl_seg_tmp.dw0.bs.ctrlsl = ROCE_CTRL_SEG_SL; + param->ctrl_seg_tmp.dw0.bs.bdsl = 0; +} + +static void roce3_init_task_com_seg(union roce3_wqe_tsk_com_seg **tsk_com_seg, u8 *wqe, const struct ib_send_wr *wr, + const struct roce3_qp *rqp) +{ + *tsk_com_seg = (union roce3_wqe_tsk_com_seg *)(void *)wqe; + + (*tsk_com_seg)->bs.c = + (u32)(!((((unsigned)wr->send_flags & (unsigned)IB_SEND_SIGNALED) | rqp->sq_signal_bits) == 0)); + (*tsk_com_seg)->bs.se = (u32)(!(((unsigned)wr->send_flags & (unsigned)IB_SEND_SOLICITED) == 0)); + (*tsk_com_seg)->bs.f = (u32)(!(((unsigned)wr->send_flags & (unsigned)IB_SEND_FENCE) == 0)); + (*tsk_com_seg)->bs.op_type = roce3_ib_opcode[wr->opcode] & 0x1f; + if (wr->opcode == IB_WR_REG_MR) { + (*tsk_com_seg)->bs.op_type = ROCE_WQE_OPCODE_FRMR; + } +} + +static void roce3_post_send_local_operation(struct roce3_post_send_normal_param *param, struct roce3_qp *rqp, + struct roce3_device *rdev) +{ + param->opcode = param->tsk_com_seg->bs.op_type; + param->tsk_com_seg->value = cpu_to_be32(param->tsk_com_seg->value); + param->ctrl_seg->dw1.value = cpu_to_be32(param->ctrl_seg_tmp.dw1.value); + param->index += (u32)DIV_ROUND_UP(param->wqe_size, 1U << (u32)rqp->sq.wqe_shift); + + write_invalid_wqe(rqp, param->index); + + /* + * Make sure descriptor is fully written before + * setting ownership bit (because HW can start + * executing as soon as we do). + */ + wmb(); + + param->ctrl_seg->dw0.value = cpu_to_be32(param->ctrl_seg_tmp.dw0.value); +} +/* **************************************************************************** + Prototype : roce3_post_send_normal + Description : roce3_post_send_normal + Input : struct roce3_device *rdev + struct roce3_qp *rqp + struct ib_send_wr *wr + struct ib_send_wr **bad_wr + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + + 2.Date : 2015/8/8 + Modification : Modify function + +**************************************************************************** */ +static int roce3_post_send_normal(struct roce3_device *rdev, struct roce3_qp *rqp, const struct ib_send_wr *wr, + const struct ib_send_wr **bad_wr) +{ + int need_goto = 0; + int ret = 0; + struct roce3_post_send_normal_param param = { 0 }; + const struct ib_send_wr *wr_tmp = wr; + + spin_lock_irqsave(&rqp->sq.lock, param.flags); + + param.index = rqp->sq_next_wqe; + + for (param.wr_num = 0; wr_tmp != NULL; ++(param.wr_num), wr_tmp = wr_tmp->next) { + ret = roce3_validate_wr(rqp, wr_tmp, param.wr_num); + if (ret != 0) { + *bad_wr = wr_tmp; + pr_err("[ROCE, ERR] %s: Failed to validate wr, func(%d) qpn(%u)\n", __func__, rdev->glb_func_id, rqp->qpn); + goto out; + } + + param.wqe = (u8 *)roce3_get_send_wqe(rqp, param.index); + param.ctrl_seg = (struct roce3_wqe_ctrl_seg *)param.wqe; + + param.sq_rmd_size = (u32)(rqp->sq_tail_addr - (u8 *)param.wqe); + + rqp->sq.wrid[(rqp->sq.head + param.wr_num) & (u32)(rqp->sq.wqebb_cnt - 1)] = wr_tmp->wr_id; + + roce3_init_ctrl_seg(¶m, wr_tmp, rqp); + + param.wqe = ((u8 *)param.wqe + sizeof(*(param.ctrl_seg))); + param.wqe_size = (u32)sizeof(*param.ctrl_seg); + roce3_init_task_com_seg(¶m.tsk_com_seg, param.wqe, wr_tmp, rqp); + + ret = roce3_construct_wqe(¶m, rdev, rqp, wr_tmp, bad_wr); + if (ret == GOTO_LOCAL) { + ret = 0; + goto local; + } else if (ret == GOTO_OUT) { + ret = -EINVAL; + goto out; + } + + param.sq_rmd_size = (u32)(rqp->sq_tail_addr - (u8 *)param.wqe); + + need_goto = roce3_post_send_set_data_seg(¶m, rdev, rqp, wr_tmp, bad_wr); + if (need_goto == ROCE_NEED_JUMP) { + ret = -EINVAL; + goto out; + } + + roce3_fill_task_data_len(param.data_len_addr, param.data_len); + + local: + roce3_post_send_local_operation(¶m, rqp, rdev); + } + +out: + + ret = roce3_post_send_ring_db(¶m, rdev, rqp); + + if (ROCE_LIKELY(param.wr_num != 0)) { + rqp->sq_next_wqe = param.index; + } + + spin_unlock_irqrestore(&rqp->sq.lock, param.flags); + + return ret; +} + +static int roce3_post_send_check_qp_type(const struct roce3_qp *rqp) +{ + if (ROCE_UNLIKELY(rqp->qp_type == IB_QPT_XRC_TGT)) { + pr_err("[ROCE, ERR] %s: Can't post WQE when TGT XRC QP\n", __func__); + return -EINVAL; + } + + if (ROCE_UNLIKELY(rqp->qp_type == IB_QPT_XRC_INI)) { + pr_err("[ROCE, ERR] %s: not support xrc in kernel space\n", __func__); + return -EINVAL; + } + + if (ROCE_UNLIKELY((rqp->qp_state == IB_QPS_RESET) || (rqp->qp_state == IB_QPS_INIT) || + (rqp->qp_state == IB_QPS_RTR))) { + pr_err("[ROCE, ERR] %s: Can't post WQE when QP is RST/INIT/RTR state\n", __func__); + return -EINVAL; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_post_send + Description : roce3_post_send + Input : struct ib_qp *ibqp + struct ib_send_wr *wr + const struct ib_send_wr **bad_wr + Output : None +**************************************************************************** */ +int roce3_post_send_standard(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +{ + int ret = 0; + struct roce3_qp *rqp = to_roce3_qp(ibqp); + struct roce3_device *rdev = to_roce3_dev(ibqp->device); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = roce3_post_send_check_qp_type(rqp); + if (ret != 0) { + *bad_wr = wr; + pr_err("[ROCE, ERR] %s: Failed to check qp.ret(%d)\n", __func__, ret); + return ret; + } + + ret = roce3_post_send_normal(rdev, rqp, wr, bad_wr); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to post send normal wr, ret(%d)\n", __func__, ret); + return ret; + } + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/qp/roce_qp_query.c b/drivers/infiniband/hw/hiroce3/qp/roce_qp_query.c new file mode 100644 index 000000000..e3e544c00 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/qp/roce_qp_query.c @@ -0,0 +1,386 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_query.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : Define standard kernel RoCE QP Query realted functions. + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> + +#include <rdma/ib_verbs.h> + +#include "roce_compat.h" + +#include "hinic3_crm.h" + +#include "roce.h" +#include "roce_mix.h" +#include "roce_mr.h" +#include "roce_xrc.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_qp.h" +#include "roce_pub_cmd.h" +#include "roce_main_extension.h" +#ifdef __ROCE_DFX__ +#include "roce_dfx.h" +#endif + +static enum ib_mig_state to_ib_mig_state(int roce3_mig_state) +{ + switch (roce3_mig_state) { + case ROCE_QP_PM_ARMED: + return IB_MIG_ARMED; + + case ROCE_QP_PM_REARM: + return IB_MIG_REARM; + + case ROCE_QP_PM_MIGRATED: + return IB_MIG_MIGRATED; + + default: + return (enum ib_mig_state)(-1); + } +} + +static int to_ib_qp_access_flags(const struct roce_qp_context *context) +{ + unsigned int ib_flags = 0; + u32 tmp = 0; + + /* RRE */ + if (context->chip_seg.qpcc.dw5.bs.qp_rre != 0) { + tmp = ib_flags | IB_ACCESS_REMOTE_READ; + ib_flags = tmp; + } + + /* RWE */ + if (context->chip_seg.qpcc.dw5.bs.qp_rwe != 0) { + tmp = ib_flags | IB_ACCESS_REMOTE_WRITE; + ib_flags = tmp; + } + + /* RAE */ + if (context->chip_seg.qpcc.dw5.bs.qp_rae != 0) { + tmp = ib_flags | IB_ACCESS_REMOTE_ATOMIC; + ib_flags = tmp; + } + + return (int)ib_flags; +} + +/* **************************************************************************** + Prototype : to_ib_ah_attr + Description : to_ib_ah_attr + Input : struct roce3_device *rdev + struct ib_ah_attr *ah_attr(struct rdma_ah_attr *ah_attr) + struct roce_qp_context *context + Output : None + Return Value : + Calls : + Called By : + + History : + 1.Date : 2015/5/26 + Author : + Modification : Created function + +**************************************************************************** */ +static void to_ib_ah_attr(struct roce3_device *rdev, struct rdma_ah_attr *ah_attr, struct roce_qp_context *context) +{ + struct drv_path_info *path_seg = &context->sw_seg.path_seg; + + memset(ah_attr, 0, sizeof(*ah_attr)); + + ah_attr->port_num = context->sw_seg.ucode_seg.common.dw0.bs.port; + + ah_attr->sl = 0x7 - path_seg->dw7.bs.sl; + + ah_attr->static_rate = 0; + + ah_attr->ah_flags = IB_AH_GRH; + + ah_attr->grh.sgid_index = path_seg->dw7.bs.sgid_index; + ah_attr->grh.hop_limit = path_seg->dw7.bs.hoplmt; + ah_attr->grh.traffic_class = path_seg->dw6.bs.tclass; + ah_attr->grh.flow_label = path_seg->dw6.bs.flow_label; + + memcpy((void *)ah_attr->grh.dgid.raw, (void *)path_seg->dgid, + sizeof(ah_attr->grh.dgid.raw)); +} + +/* **************************************************************************** + Prototype : roce3_qp_query + Description : roce3_qp_query + Input : struct roce3_device *rdev + struct roce3_qp *qp + struct roce_qp_context *context + Output : None + + 1.Date : 2015/5/26 + Modification : Created function + +**************************************************************************** */ +int roce3_qp_query(struct roce3_device *rdev, u32 qpn, u32 *context, int qpc_size) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_qp_query_s *qp_query_inbuf = NULL; + struct roce3_qp_query_outbuf *qp_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_qp_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_qp_query_outbuf)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + qp_query_inbuf = (roce_cmd_qp_query_s *)cqm_cmd_inbuf->buf; + qp_query_outbuf = (struct roce3_qp_query_outbuf *)cqm_cmd_outbuf->buf; + qp_query_inbuf->com.index = cpu_to_be32(qpn); + qp_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); //lint !e778 + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_QUERY_QP, cqm_cmd_inbuf, cqm_cmd_outbuf, ROCE_CMD_TIME_CLASS_B); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send QUERY_QP command, func_id(%d)\n", __func__, + rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(QUERY_QP), qpn(0x%x), func_id(%hu)\n", __func__, qpn, + rdev->glb_func_id); + + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + ret = -1; + goto free_cqm_buf; + } + + memcpy((void *)context, (void *)&qp_query_outbuf->qpc, (size_t)qpc_size); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return 0; + +free_cqm_buf: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* **************************************************************************** + Prototype : qpc_seg_to_le32 + Input : struct roce_qp_context *le_ctx + struct roce_qp_context *be_ctx + struct roce3_qp *rqp + Output : None + + 1.Date : 2015/8/15 + Modification : Created function + +**************************************************************************** */ +void qpc_seg_to_le32(struct roce_qp_context *be_ctx, struct roce_qp_context *le_ctx, u32 srq_vld) +{ + /* DRV Seg */ + memcpy((void *)le_ctx->sw_seg.path_seg.dgid, + (void *)be_ctx->sw_seg.path_seg.dgid, sizeof(be_ctx->sw_seg.path_seg.dgid)); + + /* CHIP Seg */ + le_ctx->chip_seg.qpcc.sq_rq_l0mtt_gpa = be64_to_cpu(be_ctx->chip_seg.qpcc.sq_rq_l0mtt_gpa); + + le_ctx->chip_seg.qpcc.sq_rq_pi_record_gpa_at_hop_num = + cpu_to_be64(be_ctx->chip_seg.qpcc.sq_rq_pi_record_gpa_at_hop_num); + + le_ctx->chip_seg.rcc.rc_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.rcc.rc_curt_sge_va); + + le_ctx->chip_seg.sqc.sq_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.sqc.sq_curt_sge_va); + + le_ctx->chip_seg.sqac.sqa_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.sqac.sqa_curt_sge_va); + + if (srq_vld != 0) { + le_ctx->chip_seg.srqc.srq_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.srqc.srq_curt_sge_va); + } else { + le_ctx->chip_seg.rqc.rq_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.rqc.rq_curt_sge_va); + } + + le_ctx->chip_seg.rrwc.rrw_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.rrwc.rrw_curt_sge_va); + + le_ctx->chip_seg.rrwc.rrw_curt_sge_va = be64_to_cpu(be_ctx->chip_seg.rrwc.rrw_curt_sge_va); +} + +void roce3_be32_2_le32(void *context, u32 *le_ctx, u32 ctx_size) +{ + u32 *ctx = NULL, *ctx1 = NULL; + u32 i = 0; + + ctx = le_ctx; + ctx1 = (u32 *)context; + + for (i = 0; i < ctx_size; ++i, ++ctx1, ++ctx) { + *ctx = be32_to_cpu(*ctx1); + } + + return; +} + +static void roce3_get_ah_attr(const struct roce3_qp *rqp, struct ib_qp_attr *qp_attr, struct roce3_device *rdev, + struct roce_qp_context *context) +{ + if ((rqp->qp_type == IB_QPT_RC) || (rqp->qp_type == IB_QPT_UC)) { + to_ib_ah_attr(rdev, &qp_attr->ah_attr, context); + } +} + +static void roce3_query_set_common_attr(struct ib_qp_attr *qp_attr, const struct ib_qp *ibqp, struct roce3_qp *rqp, + struct ib_qp_init_attr *qp_init_attr) +{ + qp_attr->cur_qp_state = qp_attr->qp_state; + qp_attr->cap.max_recv_wr = (u32)rqp->rq.wqebb_cnt; + qp_attr->cap.max_recv_sge = (u32)rqp->rq.max_sge; + + if (!ibqp->uobject) { + qp_attr->cap.max_send_wr = (u32)rqp->sq.max_post; + qp_attr->cap.max_send_sge = (u32)rqp->sq.max_sge; + } else { + qp_attr->cap.max_send_wr = 0; + qp_attr->cap.max_send_sge = 0; + } + + qp_attr->cap.max_inline_data = rqp->max_inline_data; + + qp_init_attr->cap = qp_attr->cap; + + qp_init_attr->create_flags = (enum ib_qp_create_flags)0; + + qp_init_attr->sq_sig_type = (rqp->sq_signal_bits == 1) ? IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; +} + +static void roce3_query_set_attr(struct ib_qp_attr *qp_attr, u8 tmp_qp_state, struct roce3_qp *rqp, + struct roce_qp_context context, struct roce3_device *rdev) +{ + qp_attr->qp_state = (enum ib_qp_state)rqp->qp_state; + qp_attr->path_mtu = (enum ib_mtu)context.sw_seg.drv_seg.dw2.bs.pmtu; + qp_attr->path_mig_state = (enum ib_mig_state)to_ib_mig_state(ROCE_QP_PM_MIGRATED); + qp_attr->qkey = context.sw_seg.ucode_seg.common.dw2.qkey; + qp_attr->rq_psn = context.sw_seg.ucode_seg.rq_ctx.dw20.bs.next_rcv_psn; + qp_attr->sq_psn = context.sw_seg.ucode_seg.sq_ctx.dw8.bs.next_send_psn; + qp_attr->dest_qp_num = context.sw_seg.drv_seg.dw0.bs.dest_qp; + qp_attr->qp_access_flags = to_ib_qp_access_flags(&context); + + roce3_get_ah_attr(rqp, qp_attr, rdev, &context); + + qp_attr->pkey_index = 0; + + if (qp_attr->qp_state == IB_QPS_INIT) { + qp_attr->port_num = rqp->port; + } else { + qp_attr->port_num = context.sw_seg.ucode_seg.common.dw0.bs.port; + } + + /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ + + /* SQ Draining FLAG */ + qp_attr->sq_draining = (tmp_qp_state == ROCE_QP_STATE_SQ_DRAINING); + + qp_attr->max_rd_atomic = (1 << context.sw_seg.drv_seg.dw3.bs.sra_max); + qp_attr->max_dest_rd_atomic = (1 << context.sw_seg.drv_seg.dw3.bs.rra_max); + + qp_attr->min_rnr_timer = context.sw_seg.drv_seg.dw2.bs.min_rnr_nak; + qp_attr->timeout = context.sw_seg.drv_seg.dw2.bs.ack_to; + qp_attr->retry_cnt = context.sw_seg.drv_seg.dw2.bs.to_retry_limit; + qp_attr->rnr_retry = context.sw_seg.drv_seg.dw2.bs.rnr_retry_limit; +} + +static int roce3_query_qp_struct_clean(struct ib_qp_attr *qp_attr, struct ib_qp_init_attr *qp_init_attr, + struct roce_qp_context *be_ctx, struct roce_qp_context *context) +{ + memset(qp_attr, 0, sizeof(struct ib_qp_attr)); + memset(qp_init_attr, 0, sizeof(struct ib_qp_init_attr)); + memset(be_ctx, 0, sizeof(struct roce_qp_context)); + memset(context, 0, sizeof(struct roce_qp_context)); + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_query_qp + Description : roce3_query_qp + Input : struct ib_qp *ibqp + struct ib_qp_attr *qp_attr + int qp_attr_mask + struct ib_qp_init_attr *qp_init_attr + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +int roce3_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, + struct ib_qp_init_attr *qp_init_attr) +{ + int ret = 0; + struct roce3_qp *rqp = NULL; + struct roce3_device *rdev = NULL; + struct roce_qp_context be_ctx; /* BE context structure */ + struct roce_qp_context context; /* LE context structure */ + u32 srq_vld; + u8 tmp_qp_state = 0; + + ret = roce3_query_qp_struct_clean(qp_attr, qp_init_attr, &be_ctx, &context); + if (ret != 0) { + return ret; + } + + rqp = to_roce3_qp(ibqp); + rdev = to_roce3_dev(ibqp->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + mutex_lock(&rqp->mutex); + + if (rqp->qp_state == IB_QPS_RESET) { + qp_attr->qp_state = IB_QPS_RESET; + goto done; + } + + ret = roce3_qp_query(rdev, rqp->qpn, (u32 *)(void *)(&be_ctx), sizeof(be_ctx)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to query qp, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + mutex_unlock(&rqp->mutex); + return ret; + } + + srq_vld = (!(rqp->ibqp.srq)) ? ROCE_QP_NO_SRQ : ROCE_QP_HAS_SRQ; + roce3_be32_2_le32(&be_ctx, (u32 *)(void *)&context, sizeof(struct roce_qp_context) / sizeof(u32)); + + qpc_seg_to_le32(&be_ctx, &context, srq_vld); + + rqp->qp_state = context.sw_seg.drv_seg.dw0.bs.state; /* state:4bits */ + + tmp_qp_state = rqp->qp_state; + if (rqp->qp_state == ROCE_QP_STATE_SQ_DRAINING) { + rqp->qp_state = IB_QPS_SQD; + } + + roce3_query_set_attr(qp_attr, tmp_qp_state, rqp, context, rdev); + +done: + roce3_query_set_common_attr(qp_attr, ibqp, rqp, qp_init_attr); + + mutex_unlock(&rqp->mutex); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.c new file mode 100644 index 000000000..8efd303c2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_bitmap.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : The the management of RoCE bitmap. + */ + +#include <linux/slab.h> + +#include "rdma_comp.h" +#include "rdma_bitmap.h" + +u32 rdma_bitmap_alloc(struct rdma_bitmap *bitmap) +{ + u32 index = 0; + + if (bitmap == NULL) { + pr_err("%s: Bitmap is null\n", __FUNCTION__); + return RDMA_INVALID_INDEX; + } + + spin_lock(&bitmap->lock); + + index = (u32)find_next_zero_bit(bitmap->table, (unsigned long)bitmap->max_num, (unsigned long)bitmap->last); + if (index >= bitmap->max_num) { + bitmap->top = (bitmap->top + bitmap->max_num + bitmap->reserved_top) & bitmap->mask; + index = (u32)find_first_zero_bit(bitmap->table, (unsigned long)bitmap->max_num); + } + + if (index < bitmap->max_num) { + set_bit(index, bitmap->table); + bitmap->last = index + 1; + if (bitmap->last == bitmap->max_num) { + bitmap->last = 0; + } + + index |= bitmap->top; + --bitmap->avail; + } else { + pr_err("%s: Get a invalid index\n", __FUNCTION__); + spin_unlock(&bitmap->lock); + return RDMA_INVALID_INDEX; + } + + spin_unlock(&bitmap->lock); + + return index; +} + +void rdma_bitmap_free(struct rdma_bitmap *bitmap, u32 index) +{ + u32 index_tmp = index; + if (bitmap == NULL) { + pr_err("%s: Bitmap is null\n", __FUNCTION__); + return; + } + + if (index_tmp >= bitmap->max_num) { + pr_err("%s: Index(%d) is bigger or equal than max(%d)\n", __FUNCTION__, index_tmp, bitmap->max_num); + return; + } + + index_tmp &= bitmap->max_num + bitmap->reserved_top - 1; + + spin_lock(&bitmap->lock); + + bitmap->last = min(bitmap->last, index_tmp); + bitmap->top = (bitmap->top + bitmap->max_num + bitmap->reserved_top) & bitmap->mask; + + bitmap_clear(bitmap->table, (int)index_tmp, 1); + ++bitmap->avail; + spin_unlock(&bitmap->lock); + + return; +} + +int rdma_bitmap_init(struct rdma_bitmap *bitmap, u32 num, u32 mask, u32 reserved_bot, u32 reserved_top) +{ + if (bitmap == NULL) { + pr_err("%s: Bitmap is null\n", __FUNCTION__); + return -EINVAL; + } + + /*lint -e587 */ + if (num != (u32)(ROCE_BITMAP_ROUNDUP_POW_OF_TWO(num) & 0xffffffff)) { + pr_err("%s: Num(%d) isn't pow of two, err(%d)\n", __FUNCTION__, num, -EINVAL); + return -EINVAL; + } + /*lint +e587 */ + + if (num <= (reserved_bot + reserved_top)) { + pr_err("%s: Reserved num is bigger than total num, err(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + bitmap->last = 0; + bitmap->top = 0; + bitmap->max_num = num - reserved_top; + bitmap->mask = mask; + bitmap->reserved_top = reserved_top; + bitmap->avail = (num - reserved_top) - reserved_bot; + + /*lint -e708*/ + spin_lock_init(&bitmap->lock); + /*lint +e708*/ + bitmap->table = (unsigned long *)kzalloc(BITS_TO_LONGS(bitmap->max_num) * sizeof(long), GFP_KERNEL); + if (bitmap->table == NULL) { + pr_warn("%s: Failed to kzalloc bitmap->table, size(0x%lx)\n", + __FUNCTION__, BITS_TO_LONGS(bitmap->max_num) * sizeof(long)); + bitmap->table = (unsigned long *)vzalloc((size_t)(BITS_TO_LONGS(bitmap->max_num) * sizeof(long))); + if (bitmap->table == NULL) { + pr_err("%s: Failed to vzalloc bitmap->table, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + } + + bitmap_set(bitmap->table, 0, (int)reserved_bot); + + return 0; +} + +void rdma_bitmap_cleanup(struct rdma_bitmap *bitmap) +{ + if (bitmap == NULL) { + pr_err("%s: Bitmap is null\n", __FUNCTION__); + return; + } + + if (is_vmalloc_addr(bitmap->table)) { + vfree(bitmap->table); + } else { + kfree(bitmap->table); + } + + bitmap->table = NULL; + + return; +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.h b/drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.h new file mode 100644 index 000000000..b171e15c6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_bitmap.h + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : define RoCE bitmap related macro and structure + */ + +#ifndef RDMA_BITMAP_H +#define RDMA_BITMAP_H + +#include <linux/spinlock.h> + +#ifndef RDMA_INVALID_INDEX +#define RDMA_INVALID_INDEX 0xFFFFFFFF +#endif + +#define ROCE_BITMAP_ROUNDUP_POW_OF_TWO(n) /*lint -e866 -e587*/ roundup_pow_of_two(n) /*lint +e866 +e587*/ + +struct rdma_bitmap { + u32 last; /* bottom of available id */ + u32 top; /* top value of non zone of id */ + u32 max_num; /* max id num */ + u32 reserved_top; /* unavailable top num */ + u32 mask; /* mask of id */ + u32 avail; /* num of available id */ + spinlock_t lock; /* spinlock of bitmap */ + unsigned long *table; /* memory of bitmap */ +}; + +u32 rdma_bitmap_alloc(struct rdma_bitmap *bitmap); + +void rdma_bitmap_free(struct rdma_bitmap *bitmap, u32 index); + +int rdma_bitmap_init(struct rdma_bitmap *bitmap, u32 num, u32 mask, u32 reserved_bot, u32 reserved_top); + +void rdma_bitmap_cleanup(struct rdma_bitmap *bitmap); + +#endif // __RDMA_BITMAP_H__ diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp.c new file mode 100644 index 000000000..46b9137e1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : implement the management of PDID, XRCD, MPT, MTT, RDMARC, + * GID and GUID + */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "rdma_comp.h" + + +struct rdma_comp_priv *get_rdma_comp_priv(void *hwdev) +{ + struct rdma_comp_priv *comp_private = NULL; + comp_private = (struct rdma_comp_priv *)hinic3_get_service_adapter(hwdev, SERVICE_T_ROCE); + return comp_private; +} + +void rdma_cleanup_pd_table(struct rdma_comp_priv *comp_priv) +{ + rdma_bitmap_cleanup(&comp_priv->pd_bitmap); +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp.h b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp.h new file mode 100644 index 000000000..cca24c10c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp.h + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : define rdma component related macro, structure and interface + */ + +#ifndef RDMA_COMP_H +#define RDMA_COMP_H + +/* x86 */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +#include <linux/delay.h> +#include <linux/types.h> + +#include "rdma_context_format.h" +#include "hinic3_crm.h" +#include "hinic3_cqm.h" +#include "hinic3_rdma.h" + +#include "roce_verbs_cmd.h" +#include "roce_verbs_ulp_format.h" + +#include "rdma_bitmap.h" +#include "hmm_buddy.h" +#include "hmm_em.h" +#include "hmm_comp.h" + +#ifndef pr_fmt +#define pr_fmt(fmt) KBUILD_MODNAME ": [RDMA]" fmt +#endif + +#define RDMA_DEFAULT_GID_SUBNET_PREFIX 0xFE80000000000000ULL + +#define RDMA_KEY_MASK 0xFFFFFF00 + +#define RDMA_INVALID_GUID 0 + +#define RDMA_SERVICE_TYPE_ROCE SERVICE_T_ROCE + +#define RDMA_BIT_SHIFT_1 1 +#define RDMA_BIT_SHIFT_2 2 +#define RDMA_BIT_SHIFT_4 4 +#define RDMA_BIT_SHIFT_8 8 +#define RDMA_BIT_SHIFT_16 16 + +#define ROCE3_RDMARC_MIN_DEPTH 1 +#define ROCE3_RDMARC_MAX_DEPTH 512 +#define ROCE3_RDMARC_MIN_ENTRY 8 /* min entry aligned required by engine */ +#define ROCE3_RDMARC_EXT_ENTRY 384 // 384 /* ext tbl 12K. 12k/32 = 384 */ + +extern u32 g_mtt_page_size; + +#define RDMA_EM_MIN_ORDER 2 /* rdma rc extend table at least 4 page */ + +#define ROCE_MTT_PAGE_SIZE_4K 4096 +#define ROCE_MTT_PAGE_SIZE_64K (64 * 1024) +#define ROCE_MTT_PAGE_SIZE_2M (2 * 1024 * 1024) +#define ROCE_MTT_PAGE_SIZE_4K_SHIFT 12 +#define ROCE_MTT_PAGE_SIZE_64K_SHIFT 16 +#define ROCE_MTT_PAGE_SIZE_2M_SHIFT 21 + +enum { + ROCE3_RDMA_MTT_PAGE_SIZE_4K = 0, + ROCE3_RDMA_MTT_PAGE_SIZE_64K = 1, + ROCE3_RDMA_MTT_PAGE_SIZE_2M = 2 +}; + +enum { + ROCE3_RDMA_CMD_TIME_OUT_A = 30000, + ROCE3_RDMA_CMD_TIME_OUT_B = 40000, + ROCE3_RDMA_CMD_TIME_OUT_C = 50000 +}; + +enum rdma_roce3_cmd { + RDMA_ROCE_CMD_UPDATE_GID = 0x60, + RDMA_ROCE_CMD_QUERY_GID = 0x61, + RDMA_ROCE_CMD_CLEAR_GID = 0x62 +}; + +struct rdma_comp_priv { + struct rdma_comp_resource rdma_comp_res; /* gid & guid */ + + struct hmm_buddy mtt_buddy; + struct hmm_em_table mtt_em_table; + void *hwdev; + struct pci_dev *pdev; + struct rdma_mr rsvd_lkey; + struct rdma_mr fixed_mr; + u32 mtt_page_size; /* 4K, 8K, 16K, 32K */ + u32 mtt_page_shift; /* 12, 13, 14, 15 */ + struct rdma_service_cap rdma_cap; + + struct rdma_bitmap pd_bitmap; + struct rdma_bitmap xrcd_bitmap; + + struct hmm_buddy rdmarc_buddy; + struct hmm_em_table rdmarc_em_table; +}; + +struct rdma_gid_update_inbuf { + roce_verbs_cmd_com_s com; + __be32 port; + __be32 rsvd; + struct rdma_gid_entry gid_entry; +}; + +struct rdma_gid_clear_inbuf { + __be32 port; + __be32 gid_num; +}; + +/* for llt to set stub */ +void rdma_cleanup_pd_table(struct rdma_comp_priv *comp_priv); + +struct rdma_comp_priv *get_rdma_comp_priv(void *hwdev); + +int rdma_gid_entry_cmp(struct rdma_gid_entry *gid_tbl_entry, struct rdma_gid_entry *gid_entry); + +int roce3_rdma_init_rsvd_lkey(void *hwdev); + +void roce3_rdma_free_rsvd_lkey(void *hwdev); + +#endif // RDMA_COMP_H diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_gid.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_gid.c new file mode 100644 index 000000000..c0bcd9251 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_gid.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp_gid.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : implement the management of GID + */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "rdma_comp.h" +#include "roce.h" +#include "roce_cqm_cmd.h" + +static int rdma_update_gid(struct rdma_comp_priv *comp_priv, struct rdma_gid_entry *new_gid_entry, int port, + int gid_index) +{ + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct rdma_gid_update_inbuf *gid_update_inbuf = NULL; + int ret; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(comp_priv->hwdev, &cqm_cmd_inbuf, (u16)sizeof(struct rdma_gid_update_inbuf), + NULL, 0); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, ret(%d)\n", __func__, ret); + return -ENOMEM; + } + + gid_update_inbuf = (struct rdma_gid_update_inbuf *)cqm_cmd_inbuf->buf; + gid_update_inbuf->port = cpu_to_be32((u32)port); + gid_update_inbuf->com.index = cpu_to_be32((u32)gid_index); + gid_update_inbuf->gid_entry.global.subnet_prefix = new_gid_entry->global.subnet_prefix; + gid_update_inbuf->gid_entry.global.interface_id = new_gid_entry->global.interface_id; + gid_update_inbuf->gid_entry.dw4.value = cpu_to_be32(new_gid_entry->dw4.value); + gid_update_inbuf->gid_entry.dw6_h.value = cpu_to_be16(new_gid_entry->dw6_h.value); + gid_update_inbuf->gid_entry.hdr_len_value = cpu_to_be32(new_gid_entry->hdr_len_value); + gid_update_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_GID_BITMASK); //lint !e778 + + memcpy(&gid_update_inbuf->gid_entry.smac[0], &new_gid_entry->smac[0], ETH_ALEN); + + pr_info("[ROCE] %s:gid_index:0x%x gid:0x%x %x %x %x %x %x %x %x\n", __func__, gid_update_inbuf->com.index, + *((u32 *)(void *)new_gid_entry + 0), *((u32 *)(void *)new_gid_entry + 1), // 0 1 is gid array idx + *((u32 *)(void *)new_gid_entry + 2), *((u32 *)(void *)new_gid_entry + 3), // 2 3 is gid array idx + *((u32 *)(void *)new_gid_entry + 4), *((u32 *)(void *)new_gid_entry + 5), // 4 5 is gid array idx + *((u32 *)(void *)new_gid_entry + 6), *((u32 *)(void *)new_gid_entry + 7)); // 6 7 is gid array idx + ret = cqm_send_cmd_box(comp_priv->hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_UPDATE_GID, cqm_cmd_inbuf, NULL, NULL, + ROCE3_RDMA_CMD_TIME_OUT_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("%s: Send cmd update_gid failed, ret(%d)\n", __FUNCTION__, ret); + ret = -1; + } + + roce3_cqm_cmd_free_inoutbuf(comp_priv->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +int rdma_gid_entry_cmp(struct rdma_gid_entry *gid_tbl_entry, struct rdma_gid_entry *gid_entry) +{ + struct rdma_gid_entry entry1; + struct rdma_gid_entry entry2; + + memcpy(&entry1, gid_tbl_entry, sizeof(struct rdma_gid_entry)); + memcpy(&entry2, gid_entry, sizeof(struct rdma_gid_entry)); + + /* compare ip+vlan, compare after clear smac */ + memset((void *)entry1.smac, 0, sizeof(entry1.smac)); + memset((void *)entry2.smac, 0, sizeof(entry2.smac)); + return memcmp((void *)&entry1, (void *)&entry2, sizeof(struct rdma_gid_entry)); +} + +static int rdma_reset_gid(struct rdma_comp_priv *comp_priv, u32 port, u32 gid_num) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_clear_gid_s *gid_clear_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(comp_priv->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_clear_gid_s), NULL, 0); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, ret(%d)\n", __func__, ret); + return -ENOMEM; + } + + gid_clear_inbuf = (roce_cmd_clear_gid_s *)cqm_cmd_inbuf->buf; + gid_clear_inbuf->port = cpu_to_be32(port); + gid_clear_inbuf->com.index = 0; // cpu_to_be32(gid_num); + gid_clear_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_GID_BITMASK); //lint !e778 + + ret = cqm_send_cmd_box(comp_priv->hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_CLEAR_GID, cqm_cmd_inbuf, NULL, NULL, + ROCE3_RDMA_CMD_TIME_OUT_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("%s: Send cmd clear_gid failed, ret(%d)\n", __FUNCTION__, ret); + ret = -1; + } + + roce3_cqm_cmd_free_inoutbuf(comp_priv->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +int roce3_rdma_update_gid_mac(void *hwdev, u32 port, struct rdma_gid_entry *gid_entry) +{ + struct rdma_comp_priv *comp_priv = NULL; + struct rdma_gid_entry **gid_table = NULL; + u32 gid_index = 0; + int update_index = -1; /* -1 is initvalue, indicating no need to update */ + int ret = 0; + if ((hwdev == NULL) || (gid_entry == NULL)) { + pr_err("%s: Hwdev or gid_tbl is null\n", __FUNCTION__); + return -EINVAL; + } + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + /* port num index from zero */ + if (port >= comp_priv->rdma_cap.num_ports) { + pr_err("%s: Input port(%d) is invalid\n", __FUNCTION__, port); + return -EINVAL; + } + /* invalid gid cause of with the head fe80:: of IPV6 */ + if (cpu_to_be64(gid_entry->global.subnet_prefix) == RDMA_DEFAULT_GID_SUBNET_PREFIX) { + return 0; + } + gid_table = comp_priv->rdma_comp_res.gid_table; + mutex_lock(&comp_priv->rdma_comp_res.mutex); + /* loop all gid, ensure all gid cleared not exist */ + for (gid_index = 1; gid_index < comp_priv->rdma_cap.max_gid_per_port; gid_index++) { + if (rdma_gid_entry_cmp(&gid_table[port][gid_index], gid_entry) == 0) { + update_index = (int)gid_index; + break; + } + } + if (update_index > 0) { + ret = rdma_update_gid(comp_priv, gid_entry, (int)port, update_index); + if (ret != 0) { + pr_err("%s: Update gid tbl failed, ret(%d)\n", __FUNCTION__, ret); + mutex_unlock(&comp_priv->rdma_comp_res.mutex); + return ret; + } + /* update gid table after CMDQ */ + memcpy((void *)&gid_table[port][update_index], (void *)gid_entry, + sizeof(*gid_entry)); + + mutex_unlock(&comp_priv->rdma_comp_res.mutex); + return 0; + } + mutex_unlock(&comp_priv->rdma_comp_res.mutex); + return 0; +} + +int roce3_rdma_update_gid(void *hwdev, u32 port, u32 update_index, struct rdma_gid_entry *gid_entry) +{ + int ret = 0; + u32 port_num = 0; + struct rdma_comp_priv *comp_priv = NULL; + struct rdma_gid_entry **gid_table; + + if ((hwdev == NULL) || (gid_entry == NULL)) { + pr_err("%s: Hwdev or gid_tbl is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + gid_table = comp_priv->rdma_comp_res.gid_table; + + /* port start from zero */ + port_num = comp_priv->rdma_cap.num_ports; + if (port >= port_num) { + pr_err("%s: Input port(%d) is invalid\n", __FUNCTION__, port); + return -EINVAL; + } + + mutex_lock(&comp_priv->rdma_comp_res.mutex); + ret = rdma_update_gid(comp_priv, gid_entry, (int)port, (int)update_index); + if (ret != 0) { + pr_err("%s: Rdma_update_gid failed\n", __FUNCTION__); + mutex_unlock(&comp_priv->rdma_comp_res.mutex); + return ret; + } + + memcpy((void *)&gid_table[port][update_index], (void *)gid_entry, sizeof(*gid_entry)); + mutex_unlock(&comp_priv->rdma_comp_res.mutex); + + return 0; +} + +int roce3_rdma_reset_gid_table(void *hwdev, u32 port) +{ + struct rdma_comp_priv *comp_priv = NULL; + struct rdma_gid_entry **gid_table = NULL; + int ret = 0; + u32 gids_per_port = 0; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + gid_table = comp_priv->rdma_comp_res.gid_table; + if (gid_table == NULL) { + pr_err("%s: Gid_table is null\n", __FUNCTION__); + return -EINVAL; + } + + gids_per_port = comp_priv->rdma_cap.max_gid_per_port; + if (gids_per_port == 0) { + pr_err("%s: Gids_per_port(%d) is invalid\n", __FUNCTION__, gids_per_port); + return -EINVAL; + } + + memset(&gid_table[port][0], 0, + gids_per_port * sizeof(struct rdma_gid_entry)); + ret = rdma_reset_gid(comp_priv, port, gids_per_port); + if (ret != 0) { + pr_err("%s: Reset gid table failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +int roce3_rdma_get_gid(void *hwdev, u32 port, u32 gid_index, struct rdma_gid_entry *gid) +{ + struct rdma_service_cap *rdma_cap = NULL; + struct rdma_comp_priv *comp_priv = NULL; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return -EINVAL; + } + + if (gid == NULL) { + pr_err("%s: Gid is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + rdma_cap = &comp_priv->rdma_cap; + if (port < 1 || port > rdma_cap->num_ports) { + pr_err("%s: Port(%d) invalid\n", __FUNCTION__, port); + return -EINVAL; + } + + if (gid_index >= rdma_cap->max_gid_per_port) { + pr_err("%s: gid_index(%d) invalid\n", __FUNCTION__, gid_index); + return -EINVAL; + } + + memcpy((void *)gid, (void *)&comp_priv->rdma_comp_res.gid_table[port - 1][gid_index], + sizeof(*gid)); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_init.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_init.c new file mode 100644 index 000000000..8879062ac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_init.c @@ -0,0 +1,387 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp_init.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : implement the initialization of RoCE bitmap resources + */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "rdma_comp.h" +#include "hinic3_hmm.h" + +#define ROCE_MAX_RDMA_RC_EXTEND 384 /* 12K */ + +static int rdma_init_pd_table(struct rdma_comp_priv *comp_priv) +{ + int ret = 0; + u32 num = 0; + u32 reserved_bot = 0; + + num = comp_priv->rdma_cap.num_pds; + reserved_bot = comp_priv->rdma_cap.reserved_pds; + + ret = rdma_bitmap_init(&comp_priv->pd_bitmap, num, num - 1, reserved_bot, 0); + if (ret != 0) { + pr_err("%s: Can't initialize pd's bitmap, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +static void rdma_cleanup_gid_table(struct rdma_comp_priv *comp_priv) +{ + struct rdma_gid_entry **gid_table = NULL; + int i = 0; + int port_num = 0; + + gid_table = comp_priv->rdma_comp_res.gid_table; + if (gid_table == NULL) { + pr_err("%s: Gid_table is null\n", __FUNCTION__); + return; + } + + port_num = (int)comp_priv->rdma_cap.num_ports; + for (i = 0; i < port_num; i++) { + if (gid_table[i]) { + kfree(gid_table[i]); + gid_table[i] = NULL; + } + } + + kfree(gid_table); + comp_priv->rdma_comp_res.gid_table = NULL; + + return; +} + +static int rdma_init_gid_table(struct rdma_comp_priv *comp_priv) +{ + struct rdma_gid_entry **gid_table = NULL; + u32 i = 0; + u32 port_num = 0; + u32 gids_per_port = 0; + + port_num = comp_priv->rdma_cap.num_ports; + gids_per_port = comp_priv->rdma_cap.max_gid_per_port; + if ((port_num == 0) || (gids_per_port == 0)) { + pr_err("%s: Alloc memory for gid_tbl failed, port_num(%d), gids_per_ports(%d)\n", __FUNCTION__, port_num, + gids_per_port); + return -EINVAL; + } + + gid_table = (struct rdma_gid_entry **)kzalloc(port_num * sizeof(struct rdma_gid_entry *), GFP_KERNEL); + if (gid_table == NULL) { + pr_err("%s: Alloc memory for gid_tbl failed, ret(%d), port_num(%d)\n", __FUNCTION__, -ENOMEM, port_num); + return -ENOMEM; + } + + comp_priv->rdma_comp_res.gid_table = gid_table; + + for (i = 0; i < port_num; i++) { + gid_table[i] = (struct rdma_gid_entry *)kzalloc(gids_per_port * sizeof(struct rdma_gid_entry), GFP_KERNEL); + if (gid_table[i] == NULL) { + pr_err("%s: Alloc memory for gid_tbl[%d] failed, ret(%d), gids_per_ports(%d)\n", __FUNCTION__, i, -ENOMEM, + gids_per_port); + goto err_out; + } + } + return 0; +err_out: + for (i = 0; i < port_num; i++) { + if (gid_table[i]) { + kfree(gid_table[i]); + gid_table[i] = NULL; + } + } + kfree(gid_table); + comp_priv->rdma_comp_res.gid_table = NULL; + + return -ENOMEM; +} + +static int rdma_init_xrcd_table(struct rdma_comp_priv *comp_priv) +{ + int ret = 0; + u32 num = 0; + u32 reserved_bot = 0; + + num = comp_priv->rdma_cap.max_xrcds; + reserved_bot = comp_priv->rdma_cap.reserved_xrcds; + + ret = rdma_bitmap_init(&comp_priv->xrcd_bitmap, num, num - 1, reserved_bot, 0); + if (ret != 0) { + pr_err("%s: Can't initialize xrcd's bitmap!, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +static void rdma_cleanup_xrcd_table(struct rdma_comp_priv *comp_priv) +{ + rdma_bitmap_cleanup(&comp_priv->xrcd_bitmap); +} + +static int rdma_init_rdmarc_table(struct rdma_comp_priv *comp_priv) +{ + int ret = 0; + u32 i = 0; + u32 max_order = 0; /* rdmarc buddy max priority num */ + u32 qp_num = 0; + u32 rdmarc_per_qp = 0; /* rdmarc num per qp */ + u32 rdmarc_size = 0; + u32 log_rdmarc_per_seg = 0; /* min num of entry, 2^log_rdmarc_per_seg */ + u32 rdmarc_pow_of_two = 0; + + qp_num = comp_priv->rdma_cap.dev_rdma_cap.roce_own_cap.max_qps; + rdmarc_per_qp = comp_priv->rdma_cap.dev_rdma_cap.roce_own_cap.max_qp_dest_rdma + ROCE_MAX_RDMA_RC_EXTEND; + rdmarc_size = comp_priv->rdma_cap.dev_rdma_cap.roce_own_cap.rdmarc_entry_sz; + log_rdmarc_per_seg = comp_priv->rdma_cap.log_rdmarc_seg; + for (i = 1; i < qp_num * rdmarc_per_qp; i <<= 1) { + max_order++; + } + + max_order = (max_order > log_rdmarc_per_seg) ? (max_order - log_rdmarc_per_seg) : 0; + + ret = hmm_buddy_init(&comp_priv->rdmarc_buddy, max_order); + if (ret != 0) { + pr_err("%s: Initialize rdmarc's buddy failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + /*lint -e587*/ + rdmarc_pow_of_two = (u32)(HMM_EM_ROUNDUP_POW_OF_TWO((u32)(qp_num * rdmarc_per_qp)) & 0xffffffff); + /*lint +e587*/ + ret = hmm_em_init_table(comp_priv->pdev, &comp_priv->rdmarc_em_table, rdmarc_size, rdmarc_pow_of_two, 0, + RDMA_EM_MIN_ORDER); + if (ret != 0) { + pr_err("%s: Initialize rdmarc's em_table failed, ret(%d)\n", __FUNCTION__, ret); + goto err_out; + } + + return 0; + +err_out: + hmm_buddy_cleanup(&comp_priv->rdmarc_buddy); + + return -ENOMEM; +} + +static int roce3_rdma_init_pd_table(struct rdma_comp_priv *comp_priv) +{ + int ret = 0; + ret = rdma_init_pd_table(comp_priv); + if (ret != 0) { + pr_err("%s: Initialize pd's table failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +static int roce3_rdma_init_mtt_table(struct rdma_comp_priv *comp_priv) +{ + int ret = 0; + ret = hmm_init_mtt_table((struct hmm_comp_priv *)(void *)comp_priv); + if (ret != 0) { + pr_err("%s: Initialize mtt's table failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +static int roce3_rdma_init_bitmap(struct rdma_comp_priv *comp_priv) +{ + int ret; + ret = roce3_rdma_init_pd_table(comp_priv); + if (ret != 0) { + return ret; + } + + ret = roce3_rdma_init_mtt_table(comp_priv); + if (ret != 0) { + rdma_cleanup_pd_table(comp_priv); + return ret; + } + + return 0; +} + +static void roce3_rdma_unit_bitmap(struct rdma_comp_priv *comp_priv) +{ + hmm_cleanup_mtt_table((struct hmm_comp_priv *)(void *)comp_priv); + rdma_cleanup_pd_table(comp_priv); +} + +static int roce3_rdma_init_table(void *hwdev, struct rdma_comp_priv *comp_priv) +{ + int ret = 0; + + ret = roce3_rdma_init_bitmap(comp_priv); + if (ret != 0) { + return ret; + } + + if (hinic3_support_roce(hwdev, NULL)) { + ret = rdma_init_gid_table(comp_priv); + if (ret != 0) { + pr_err("%s: Initialize gid table failed, ret(%d)\n", __FUNCTION__, ret); + goto err_init_gid_table; + } + ret = rdma_init_xrcd_table(comp_priv); + if (ret != 0) { + pr_err("%s: Initialize xrcd's table failed, ret(%d)\n", __FUNCTION__, ret); + goto err_init_xrcd; + } + ret = rdma_init_rdmarc_table(comp_priv); + if (ret != 0) { + pr_err("%s: Initialize rdmarc's table failed, ret(%d)\n", __FUNCTION__, ret); + goto err_init_rdmarc_table; + } + } + + pr_info("%s: Rdma init resource successful\n", __FUNCTION__); + return 0; +err_init_rdmarc_table: + rdma_cleanup_xrcd_table(comp_priv); +err_init_xrcd: + rdma_cleanup_gid_table(comp_priv); +err_init_gid_table: + roce3_rdma_unit_bitmap(comp_priv); + return ret; +} + +static void rdma_cleanup_rdmarc_table(struct rdma_comp_priv *comp_priv) +{ + hmm_em_cleanup_table(comp_priv->pdev, &comp_priv->rdmarc_em_table); + + hmm_buddy_cleanup(&comp_priv->rdmarc_buddy); + + return; +} + +static void roce3_rdma_unit_table(void *hwdev, struct rdma_comp_priv *comp_priv) +{ + if (hinic3_support_roce(hwdev, NULL)) { + rdma_cleanup_rdmarc_table(comp_priv); + rdma_cleanup_xrcd_table(comp_priv); + rdma_cleanup_gid_table(comp_priv); + } + + roce3_rdma_unit_bitmap(comp_priv); +} + +void roce3_rdma_cleanup_resource(void *hwdev) +{ + struct rdma_comp_priv *comp_priv = NULL; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return; + } + + if (!hinic3_support_rdma(hwdev, NULL)) { + pr_err("%s: Not support rdma service\n", __FUNCTION__); + return; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + roce3_rdma_unit_table(hwdev, comp_priv); + + kfree(comp_priv); + + hinic3_unregister_service_adapter((void *)hwdev, SERVICE_T_ROCE); + + pr_info("%s: Rdma cleanup resource successful", __FUNCTION__); + + return; +} + +static int roce3_rdma_init_comp_priv(struct rdma_comp_priv *comp_priv, void *hwdev, struct rdma_service_cap *rdma_cap) +{ + int ret; + + mutex_init(&comp_priv->rdma_comp_res.mutex); + comp_priv->hwdev = hwdev; + comp_priv->pdev = (struct pci_dev *)((struct hinic3_hwdev *)hwdev)->pcidev_hdl; + memcpy((void *)&comp_priv->rdma_cap, (void *)rdma_cap, + sizeof(struct rdma_service_cap)); + // to adapt hmm struct + comp_priv->rdma_cap.dmtt_cl_start = rdma_cap->dev_rdma_cap.roce_own_cap.dmtt_cl_start; + comp_priv->rdma_cap.dmtt_cl_end = rdma_cap->dev_rdma_cap.roce_own_cap.dmtt_cl_end; + comp_priv->rdma_cap.dmtt_cl_sz = rdma_cap->dev_rdma_cap.roce_own_cap.dmtt_cl_sz; + + switch (g_mtt_page_size) { + case ROCE3_RDMA_MTT_PAGE_SIZE_4K: + comp_priv->mtt_page_size = ROCE_MTT_PAGE_SIZE_4K; + comp_priv->mtt_page_shift = ROCE_MTT_PAGE_SIZE_4K_SHIFT; + break; + case ROCE3_RDMA_MTT_PAGE_SIZE_64K: + comp_priv->mtt_page_size = ROCE_MTT_PAGE_SIZE_64K; + comp_priv->mtt_page_shift = ROCE_MTT_PAGE_SIZE_64K_SHIFT; + break; + case ROCE3_RDMA_MTT_PAGE_SIZE_2M: + comp_priv->mtt_page_size = ROCE_MTT_PAGE_SIZE_2M; + comp_priv->mtt_page_shift = ROCE_MTT_PAGE_SIZE_2M_SHIFT; + break; + default: + comp_priv->mtt_page_size = ROCE_MTT_PAGE_SIZE_4K; + comp_priv->mtt_page_shift = ROCE_MTT_PAGE_SIZE_4K_SHIFT; + break; + } + ret = roce3_rdma_init_table(hwdev, comp_priv); + if (ret != 0) { + return ret; + } + + ret = hinic3_register_service_adapter((void *)hwdev, (void *)comp_priv, SERVICE_T_ROCE); + if (ret != 0) { + roce3_rdma_unit_table(hwdev, comp_priv); + pr_err("%s: put rdma_comp_res failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + return ret; +} + +int roce3_rdma_init_resource(void *hwdev) +{ + struct rdma_comp_priv *comp_priv = NULL; + struct rdma_service_cap rdma_cap; + int ret = 0; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return -EINVAL; + } + + if (!hinic3_support_rdma(hwdev, &rdma_cap)) { + pr_info("%s: Neither ROCE nor IWARP\n", __FUNCTION__); + return 0; + } + + comp_priv = (struct rdma_comp_priv *)kzalloc(sizeof(struct rdma_comp_priv), GFP_KERNEL); + if (comp_priv == NULL) { + pr_err("%s: Alloc memory for comp_priv failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + ret = roce3_rdma_init_comp_priv(comp_priv, hwdev, &rdma_cap); + if (ret != 0) { + kfree(comp_priv); + return ret; + } + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_mw_mr.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_mw_mr.c new file mode 100644 index 000000000..51e6f809f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_mw_mr.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp_mw_mr.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : implement the management of MR/MW + */ +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "rdma_comp.h" +#include "roce_cqm_cmd.h" +#include "hmm_mr.h" + +static void rdma_roce3_mpt_to_big_endian(struct roce_mpt_context *mpt_ctx) +{ + mpt_ctx->dw0.value = cpu_to_be32(mpt_ctx->dw0.value); + mpt_ctx->dw1.value = cpu_to_be32(mpt_ctx->dw1.value); + mpt_ctx->dw2.value = cpu_to_be32(mpt_ctx->dw2.value); + mpt_ctx->dw3.value = cpu_to_be32(mpt_ctx->dw3.value); + mpt_ctx->iova = cpu_to_be64(mpt_ctx->iova); + mpt_ctx->length = cpu_to_be64(mpt_ctx->length); + mpt_ctx->mtt_base_addr = cpu_to_be64(mpt_ctx->mtt_base_addr); + mpt_ctx->mtt_sz = cpu_to_be32(mpt_ctx->mtt_sz); +} + +static void rdma_set_roce3_mw_cmd_buf(struct roce_mpt_context *mpt_ctx, struct rdma_mw *mw) +{ + /* fill mpt_entry */ + mpt_ctx->dw0.bs.bpd = 1; + mpt_ctx->dw0.bs.r_w = RDMA_MPT_MW; + mpt_ctx->dw0.bs.access_lr = 1; + mpt_ctx->dw0.bs.access_lw = 1; + + mpt_ctx->dw1.bs.dma_attr_idx = RDMA_MPT_DMA_ATTR_IDX; + mpt_ctx->dw1.bs.so_ro = RDMA_MPT_SO_RO; + + mpt_ctx->dw2.bs.pdn = mw->pdn; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + + mpt_ctx->dw3.bs.mkey = mw->key & 0xFF; + + /* only type2 mw binds with QP and suppoort invalid operation, init value is FREE */ + if (mw->type == RDMA_MW_TYPE_2) { + mpt_ctx->dw0.bs.invalid_en = 1; + mpt_ctx->dw0.bs.remote_invalid_en = 1; + mpt_ctx->dw0.bs.bqp = 1; + + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + } + + rdma_roce3_mpt_to_big_endian(mpt_ctx); +} + +int roce3_rdma_enable_mw_mpt(void *hwdev, struct rdma_mw *mw, u32 service_type) +{ + int ret = 0; + struct rdma_comp_priv *comp_priv = NULL; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct roce_mpt_context *mpt_entry = NULL; + roce_cmd_mpt_sw2hw_s *mpt_sw2hw_inbuf = NULL; + + if ((hwdev == NULL) || (mw == NULL)) { + pr_err("%s: Hwdev or mw is null\n", __FUNCTION__); + return -EINVAL; + } + + if (service_type != RDMA_SERVICE_TYPE_ROCE) { + pr_err("%s: service_type not support \n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + ret = roce3_cqm_cmd_zalloc_inoutbuf(hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_mpt_sw2hw_s), NULL, 0); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, ret(%d)\n", __func__, ret); + return -ENOMEM; + } + + /* cmd_buf: mpt_index + mpt_entry */ + mpt_sw2hw_inbuf = (roce_cmd_mpt_sw2hw_s *)cqm_cmd_inbuf->buf; + mpt_sw2hw_inbuf->com.index = cpu_to_be32(mw->mpt.mpt_index); + mpt_sw2hw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); //lint !e778 + mpt_entry = &mpt_sw2hw_inbuf->mpt_entry; + rdma_set_roce3_mw_cmd_buf(mpt_entry, mw); + ret = hmm_enable_roce_mpt(hwdev, cqm_cmd_inbuf, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("%s: Enable mr's mpt failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + mw->enabled = RDMA_MPT_EN_HW; +out: + roce3_cqm_cmd_free_inoutbuf(hwdev, cqm_cmd_inbuf, NULL); + return ret; +} + +int roce3_rdma_disable_mw_mpt(void *hwdev, struct rdma_mw *mw, u32 service_type) +{ + struct rdma_comp_priv *comp_priv = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mw == NULL)) { + pr_err("%s: Hwdev or mw is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + if (mw->enabled == RDMA_MPT_EN_HW) { + if (service_type == RDMA_SERVICE_TYPE_ROCE) { + ret = hmm_disable_roce_mpt((struct hmm_comp_priv *)(void *)comp_priv, &mw->mpt, HINIC3_CHANNEL_ROCE); + } else { + pr_err("%s: service_type not support \n", __FUNCTION__); + return -EINVAL; + } + + if (ret != 0) { + pr_err("%s: Disable mw's mpt failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + mw->enabled = RDMA_MPT_EN_SW; + } + + return 0; +} + +static int rdma_mpt_alloc_rsvd_lkey(struct rdma_comp_priv *comp_priv, struct rdma_mpt *mpt) +{ + struct rdma_mpt_entry *mpt_entry = NULL; + u32 mpt_entry_size = 0; + + mpt_entry_size = comp_priv->rdma_cap.mpt_entry_sz; + + /* 调用cqm接口分配mpt，并将mpt_index和vaddr保存在rdma_mpt结构 */ + mpt->mpt_object = (void *)cqm_object_qpc_mpt_create(comp_priv->hwdev, RDMA_SERVICE_TYPE_ROCE, CQM_OBJECT_MPT, + mpt_entry_size, mpt, mpt->mpt_index, false); + if (mpt->mpt_object == NULL) { + pr_err("[ROCE, ERR]%s: Alloc mpt_object failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + mpt->vaddr = (void *)((cqm_qpc_mpt_s *)mpt->mpt_object)->vaddr; + if (!cqm_need_secure_mem(comp_priv->hwdev)) { + memset(mpt->vaddr, 0, sizeof(struct rdma_mpt_entry)); + + mpt_entry = (struct rdma_mpt_entry *)mpt->vaddr; + mpt_entry->roce_mpt_ctx.dw2.bs.status = RDMA_MPT_STATUS_MEM_INIT; + mpt_entry->roce_mpt_ctx.dw2.value = cpu_to_be32(mpt_entry->roce_mpt_ctx.dw2.value); + } + + return 0; +} + +int roce3_rdma_init_rsvd_lkey(void *hwdev) +{ + struct rdma_mr *mr = NULL; + struct rdma_service_cap *rdma_cap = NULL; + struct rdma_comp_priv *comp_priv = NULL; + int ret = 0; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR]%s: Hwdev is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("[ROCE, ERR]%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + rdma_cap = &comp_priv->rdma_cap; + mr = &comp_priv->rsvd_lkey; + mr->mpt.mpt_index = rdma_cap->reserved_lkey >> MR_KEY_LEFT_SHIFT_OFS; + if (mr->mpt.mpt_index >= rdma_cap->reserved_mrws) { + pr_err("[ROCE, ERR]%s: Cfg err, reserved_lkey(0x%x), reserved_mrws(0x%x)\n", __FUNCTION__, + rdma_cap->reserved_lkey, rdma_cap->reserved_mrws); + return -EINVAL; + } + /* Alloc MPT */ + ret = rdma_mpt_alloc_rsvd_lkey(comp_priv, &mr->mpt); + if (ret != 0) { + pr_err("[ROCE, ERR]%s: Rdma_mpt_alloc_rsvd_lkey failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + mr->mtt.mtt_layers = 0; + mr->iova = 0; + mr->size = ~0ULL; + mr->key = comp_priv->rdma_cap.reserved_lkey; + mr->mr_type = RDMA_RSVD_LKEY; + mr->access = RDMA_IB_ACCESS_LOCAL_WRITE; + /* Enable MPT */ + ret = hmm_rdma_enable_mr_mpt(hwdev, mr, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR]%s: Rdma_enable_mr_mpt failed, ret(%d)\n", __FUNCTION__, ret); + goto err_out; + } + return 0; +err_out: + hmm_rdma_mpt_free(hwdev, &mr->mpt); + return ret; +} + +void roce3_rdma_free_rsvd_lkey(void *hwdev) +{ + struct rdma_mr *mr = NULL; + struct rdma_comp_priv *comp_priv = NULL; + int ret = 0; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR]%s: Hwdev is null\n", __FUNCTION__); + return; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("[ROCE, ERR]%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + mr = &comp_priv->rsvd_lkey; + ret = hmm_rdma_disable_mr_mpt(hwdev, mr, RDMA_SERVICE_TYPE_ROCE, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR]%s: Disable mpt of mr failed, ret(%d)\n", __FUNCTION__, ret); + return; + } + + hmm_rdma_mpt_free(hwdev, &mr->mpt); + + return; +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_pd.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_pd.c new file mode 100644 index 000000000..fc3283a93 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_pd.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp_pds.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : implement the management of PD + */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "rdma_comp.h" + +int roce3_rdma_pd_alloc(void *hwdev, u32 *pdn) +{ + struct rdma_comp_priv *comp_priv = NULL; + + if ((hwdev == NULL) || (pdn == NULL)) { + pr_err("%s: Hwdev or pdn is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + *pdn = rdma_bitmap_alloc(&comp_priv->pd_bitmap); + if (*pdn == RDMA_INVALID_INDEX) { + pr_err("%s: Can't get valid pdn, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + return 0; +} + +void roce3_rdma_pd_free(void *hwdev, u32 pdn) +{ + struct rdma_comp_priv *comp_priv = NULL; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + rdma_bitmap_free(&comp_priv->pd_bitmap, pdn); +} diff --git a/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_res.c b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_res.c new file mode 100644 index 000000000..69b0653ad --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/rdma/rdma_comp_res.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : rdma_comp_res.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : implement the support function for management of bitmap resources + */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "rdma_comp.h" +#include "hmm_em.h" +#include "hmm_buddy.h" + +static int rdma_check_map_param(const void *hwdev, const struct rdma_fmr *fmr, const u64 *page_list, int npages, + u64 iova) +{ + u32 page_mask = 0; + + if ((hwdev == NULL) || (fmr == NULL) || (page_list == NULL)) { + pr_err("%s: Hwdev or fmr or page_list is null\n", __FUNCTION__); + return -EINVAL; + } + + if ((u32)npages > fmr->max_pages) { + pr_err("%s: Npages is bigger than fmr->max_pages, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + page_mask = (1U << fmr->page_shift) - 1; + if ((iova & (u64)page_mask) != 0) { + pr_err("%s: Iova isn't page aligned, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + if (fmr->maps >= fmr->max_maps) { + pr_err("%s: Maps over range(fmr->max_maps), ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + return 0; +} + +int roce3_rdma_map_phys_fmr(void *hwdev, struct rdma_fmr *fmr, u64 *page_list, int npages, u64 iova, u32 service_type) +{ + __be64 *mtt_vaddr = NULL; + struct rdma_comp_priv *comp_priv = NULL; + int ret = 0; + int i = 0; + u32 mpt_index = 0; + u64 length = 0; + u32 new_key = 0; + u64 iova_tmp = iova; + u16 sign_val = 0; + ret = rdma_check_map_param(hwdev, fmr, page_list, npages, iova_tmp); + if (ret != 0) { + pr_err("%s: Rdma check map param failed\n", __FUNCTION__); + return ret; + } + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + fmr->mr.enabled = RDMA_MPT_EN_SW; + mpt_index = fmr->mr.mpt.mpt_index; + length = (u64)((unsigned)npages * (1UL << fmr->page_shift)); + if ((fmr->mr.access & RDMA_IB_ACCESS_ZERO_BASED) != 0) { + iova_tmp = 0; + } + + new_key = (fmr->mr.key & (~0xFF)) | ((fmr->mr.key + 1) & 0xFF); + ret = hmm_modify_roce_mpt(hwdev, mpt_index, new_key, length, iova_tmp, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("%s: Modify mpt failed, ret(%d), new_key(%d)\n", __FUNCTION__, ret, new_key); + return ret; + } +#ifdef RDMA_SIGN_MTT_EN + sign_val = hmm_gen_mtt_sign(fmr->mr.mtt.mtt_paddr, fmr->mr.mtt.mtt_type); +#endif + mtt_vaddr = fmr->mr.mtt.mtt_vaddr; + for (i = 0; i < npages; i++) { + mtt_vaddr[i] = cpu_to_be64(page_list[i] | RDMA_MTT_PA_VALID | (sign_val << 1)); + } + fmr->maps++; + fmr->mr.key = new_key; + fmr->mr.enabled = RDMA_MPT_EN_HW; + return 0; +} + +int roce3_rdma_unmap_fmr(void *hwdev, struct rdma_fmr *fmr, u32 service_type) +{ + struct rdma_comp_priv *comp_priv = NULL; + int ret = 0; + u32 new_key = 0; + + if ((hwdev == NULL) || (fmr == NULL)) { + pr_err("%s: Hwdev or fmr is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + if (fmr->maps == 0) { + return 0; + } + + new_key = fmr->mr.key & RDMA_KEY_MASK; + + if (service_type == RDMA_SERVICE_TYPE_ROCE) { + ret = hmm_modify_roce_mpt(hwdev, fmr->mr.mpt.mpt_index, new_key, 0ULL, 0ULL, HINIC3_CHANNEL_ROCE); + } else { + pr_err("%s: service_type not support \n", __FUNCTION__); + return -EINVAL; + } + + if (ret != 0) { + pr_err("%s: Modify mpt failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + fmr->maps = 0; + fmr->mr.key = new_key; + + return 0; +} + +static int roce3_rdma_rdmarc_alloc_check(struct rdma_comp_priv **comp_priv, void *hwdev, + const struct rdma_rdmarc *rdmarc, u32 *log_rdmarc_per_seg, u32 num) +{ + if ((hwdev == NULL) || (rdmarc == NULL)) { + pr_err("%s: Hwdev or rdmarc is null\n", __FUNCTION__); + return -EINVAL; + } + + *comp_priv = get_rdma_comp_priv(hwdev); + if (*comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + *log_rdmarc_per_seg = (*comp_priv)->rdma_cap.log_rdmarc_seg; + + if ((num < ROCE3_RDMARC_MIN_DEPTH) || (num > ROCE3_RDMARC_MAX_DEPTH)) { + pr_err("%s: Num is invalid, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + return 0; +} + +static void roce3_rdma_rdmarc_order_set(struct rdma_rdmarc *rdmarc, u32 order, u32 ext_order, u32 log_rdmarc_per_seg) +{ + rdmarc->order = order; + rdmarc->ext_order = ext_order + log_rdmarc_per_seg; + return; +} + +int roce3_rdma_rdmarc_alloc(void *hwdev, u32 num, struct rdma_rdmarc *rdmarc) +{ + struct rdma_comp_priv *comp_priv = NULL; + int ret = 0; + u32 i = 0; + u32 order = 0; + u32 ext_order = 0; + u32 ext_num = num + ROCE3_RDMARC_EXT_ENTRY; + u32 offset = 0; + void *vaddr = NULL; + u32 log_rdmarc_per_seg = 0; + u32 chip_num = (num < ROCE3_RDMARC_MIN_ENTRY) ? ROCE3_RDMARC_MIN_ENTRY : num; + ret = roce3_rdma_rdmarc_alloc_check(&comp_priv, hwdev, rdmarc, &log_rdmarc_per_seg, num); + if (ret != 0) { + return ret; + } + for (i = 1; i < chip_num; i <<= 1) { + order++; + } + for (i = 1; i < ext_num; i <<= 1) { + ext_order++; + } + ext_order = ext_order > log_rdmarc_per_seg ? (ext_order - log_rdmarc_per_seg) : 0; + roce3_rdma_rdmarc_order_set(rdmarc, order, ext_order, log_rdmarc_per_seg); + offset = hmm_buddy_alloc(&comp_priv->rdmarc_buddy, ext_order); + if (offset == RDMA_INVALID_INDEX) { + pr_err("%s: Alloc rdmarc index failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + rdmarc->offset = offset << log_rdmarc_per_seg; + ret = hmm_em_table_get_range(comp_priv->pdev, &comp_priv->rdmarc_em_table, rdmarc->offset, + rdmarc->offset + (1U << rdmarc->ext_order) - 1); + if (ret != 0) { + pr_err("%s: Alloc rdmarc entry failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + goto err_table_get; + } + vaddr = hmm_em_table_find(&comp_priv->rdmarc_em_table, rdmarc->offset, &rdmarc->dma_addr); + if (vaddr == NULL) { + ret = -ENOMEM; + pr_err("%s: Can't find va and pa of rdmarc entry, ret(%d)\n", __FUNCTION__, -ENOMEM); + goto err_rdmarc_find; + } + rdmarc->vaddr = vaddr; + return 0; +err_rdmarc_find: + hmm_em_table_put_range(comp_priv->pdev, &comp_priv->rdmarc_em_table, rdmarc->offset, + rdmarc->offset + (1U << rdmarc->ext_order) - 1); +err_table_get: + hmm_buddy_free(&comp_priv->rdmarc_buddy, offset, ext_order); + return ret; +} + +void roce3_rdma_rdmarc_free(void *hwdev, struct rdma_rdmarc *rdmarc) +{ + struct rdma_comp_priv *comp_priv = NULL; + u32 order = 0; + u32 offset = 0; + u32 log_rdmarc_per_seg = 0; + + if ((hwdev == NULL) || (rdmarc == NULL)) { + pr_err("%s: Hwdev or rdmarc is null\n", __FUNCTION__); + return; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + hmm_em_table_put_range(comp_priv->pdev, &comp_priv->rdmarc_em_table, rdmarc->offset, + rdmarc->offset + (1U << rdmarc->ext_order) - 1); + + log_rdmarc_per_seg = comp_priv->rdma_cap.log_rdmarc_seg; + + order = rdmarc->ext_order - log_rdmarc_per_seg; + offset = rdmarc->offset >> log_rdmarc_per_seg; + + hmm_buddy_free(&comp_priv->rdmarc_buddy, offset, order); +} diff --git a/drivers/infiniband/hw/hiroce3/roce.h b/drivers/infiniband/hw/hiroce3/roce.h new file mode 100755 index 000000000..22679246a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce.h @@ -0,0 +1,635 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce.h + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/17 + * Description : The definition of RoCE MAIN function prototype, macros etc,. in kernel space. + */ + +#ifndef ROCE_H +#define ROCE_H + +#include <linux/types.h> +#include <linux/io-mapping.h> +#include <linux/list.h> +#include <linux/cdev.h> +#include <linux/version.h> + +#include <rdma/ib_verbs.h> +#include <rdma/ib_user_verbs.h> +#include <rdma/ib_umem.h> + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(OFED_MLNX_5_8) +#include <rdma/uverbs_ioctl.h> +#endif + +#include "hinic3_hw.h" +#include "hinic3_crm.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_lld.h" +#include "hinic3_cqm.h" +#include "hinic3_rdma.h" + +#include "nic_mpu_cmd_defs.h" + +#include "roce_db.h" +#include "roce_sysfs.h" + +#include "roce_verbs_cmd.h" +#include "roce_verbs_format.h" +#include "roce_verbs_ulp_format.h" + +#define HIROCE3_DRV_NAME "roce3_drv" +#define HIROCE3_DRV_AUTHOR "Huawei Technologies CO., Ltd" +#define HIROCE3_DRV_DESC "Huawei(R) Intelligent Network Interface Card, RoCE Driver" +#define HIROCE3_DRV_VERSION GLOBAL_VERSION_STR + +#define ROCE_IB_UVERBS_ABI_VERSION 1 +#define ROCE_ULD_DEV_NAME_LEN 16 + +#define MAX_CEQ_NEED 256 +#define MS_DELAY 5 +#define US_PERF_DELAY 100 + +#define DEV_ADDR_FIRST_BYTE_VAL_MASK 2 + +#define ROCE_NODE_DESC_LEN 5 + +#define ROCE_SQ_WQEBB_SIZE 64 + +#define ROCE_GID_LEN 16 + +#define ROCE_PCI_CFG_REGS_BAR0 0 +#define ROCE_PCI_CFG_REGS_BAR3 3 + +#define DEFAULT_ROCE_DEV_NODE_PRI 0640 + +#define ALPHA_THREADHOLD_UNIT_SHIFT 3 + +#define PAGE_4K_SHIFT 12 + +#define ROCE_MAX_PORT_NUM 8 + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +#define MAX_ROCE_DEV (28 * 4) + +enum { + ROCE3_2_PORT_NUM = 2, + ROCE3_4_PORT_NUM = 4 +}; + +enum { + ROCE3_25G_PORT_SPEED = 25, + ROCE3_100G_PORT_SPEED = 100 +}; + +enum { + ROCE3_INVALID_HCA = -1, + ROCE3_2_100G_HCA = 0, + ROCE3_4_25G_HCA = 1, + ROCE3_2_25G_HCA = 2 +}; + +enum ROCE3_100G_BW_PARAM_E { + ROCE3_100G_CIR = 46500000, + ROCE3_100G_PIR = 52500000, + ROCE3_100G_CNP = 100 +}; + +enum ROCE3_25G_BW_PARAM_E { + ROCE3_25G_CIR = 23200000, + ROCE3_25G_PIR = 25500000, + ROCE3_25G_CNP = 3 +}; + +enum roce_bitshift_e { + BYTES_TO_2B_SHIFT = 1, + BYTES_TO_4B_SHIFT, + BYTES_TO_8B_SHIFT, + BYTES_TO_16B_SHIFT, + BYTES_TO_32B_SHIFT +}; + +#define roce3_pr_emerg_once(fmt, ...) printk_once(KERN_EMERG pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_alert_once(fmt, ...) printk_once(KERN_ALERT pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_crit_once(fmt, ...) printk_once(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_err_once(fmt, ...) printk_once(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_warn_once(fmt, ...) printk_once(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_warn pr_warning +#define roce3_pr_notice_once(fmt, ...) printk_once(KERN_NOTICE pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_info_once(fmt, ...) printk_once(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__) +#define roce3_pr_cont_once(fmt, ...) printk_once(KERN_CONT pr_fmt(fmt), ##__VA_ARGS__) + +/* BIG/LITTLE ENGIAN switch */ +#ifdef HW_CONVERT_ENDIAN +#define roce3_convert_be32(val) (val) +#define roce3_convert_cpu32(val) (val) +#define roce3_more_be32(val) cpu_to_be32(val) +#else +#define roce3_convert_be32(val) cpu_to_be32(val) +#define roce3_convert_cpu32(val) be32_to_cpu(val) +#define roce3_more_be32(val) (val) +#endif + +enum roce3_aeq_type { + /* ofed err */ + OFED_ET_PATH_MIG = 0, + OFED_ET_COMM_EST, + OFED_ET_SQ_DRAINED, + OFED_ET_SRQ_QP_LAST_WQE, + OFED_ET_WQ_CATAS_ERR, + + OFED_ET_PATH_MIG_FAILED = 5, + OFED_ET_WQ_INVAL_REQ_ERR, + OFED_ET_WQ_ACCESS_ERR, + OFED_ET_CQ_ERR, + OFED_ET_SRQ_LIMIT, + OFED_ET_SRQ_CATAS_ERR, + + /* non ofed err */ + NON_OFED_ET_QPC_LOOKUP_ERR = 11, + NON_OFED_ET_OTHER_TYPE_ERR, + + /* NOF AA err */ + OFED_NOF_AA_QP_DISCONNECT = 64, + OFED_NOF_AA_MASTER_CHANGE, + + INVAL_ET_ERR +}; + +enum { + ROCE_CMD_TIME_CLASS_A = 3000, + ROCE_CMD_TIME_CLASS_B = 4000, + ROCE_CMD_TIME_CLASS_C = 5000 +}; + +enum roce3_sgl_mode { + ROCE_DOUBLE_SGL = 0, + ROCE_SINGLE_SGL +}; + +enum roce3_qpc_mtucode { + ROCE_MTU_CODE_256 = 0x0, + ROCE_MTU_CODE_512 = 0x1, + ROCE_MTU_CODE_1K = 0x3, + ROCE_MTU_CODE_2K = 0x7, + ROCE_MTU_CODE_4K = 0xf +}; + +enum roce3_ctrl_status { + ROCE3_PORT_EVENT = BIT(0) +}; + +#define ROCE_DEFAULT_PORT_NUM 1 + +#if defined(ROCE_VBS_EN) || defined(ROCE_CHIP_TEST) +#define ROCE_UVERBS_CMD_MASK \ + ((1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | \ + (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | \ + (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | (1ULL << IB_USER_VERBS_CMD_CREATE_AH) | \ + (1ULL << IB_USER_VERBS_CMD_DESTROY_AH) | (1ULL << IB_USER_VERBS_CMD_REG_MR) | \ + (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | \ + (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | (1ULL << IB_USER_VERBS_CMD_RESIZE_CQ) | \ + (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | \ + (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | \ + (1ULL << IB_USER_VERBS_CMD_DESTROY_QP) | (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | \ + (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | \ + (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | (1ULL << IB_USER_VERBS_CMD_CREATE_XSRQ) | \ + (1ULL << IB_USER_VERBS_CMD_CREATE_DCT) | (1ULL << IB_USER_VERBS_CMD_QUERY_DCT) | \ + (1ULL << IB_USER_VERBS_CMD_ARM_DCT) | (1ULL << IB_USER_VERBS_CMD_DESTROY_DCT) | \ + (1ULL << IB_USER_VERBS_CMD_CREATE_MR) | (1ULL << IB_USER_VERBS_CMD_REG_FAST_MR) | \ + (1ULL << IB_USER_VERBS_CMD_DEREG_FAST_MR) | (1ULL << IB_USER_VERBS_CMD_MAP_FRMR_SG) | \ + (1ULL << IB_USER_VERBS_CMD_OPEN_QP)) +#else +#define ROCE_UVERBS_CMD_MASK \ + ((1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) | (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) | \ + (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) | (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) | \ + (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) | (1ULL << IB_USER_VERBS_CMD_CREATE_AH) | \ + (1ULL << IB_USER_VERBS_CMD_DESTROY_AH) | (1ULL << IB_USER_VERBS_CMD_REG_MR) | \ + (1ULL << IB_USER_VERBS_CMD_REREG_MR) | (1ULL << IB_USER_VERBS_CMD_DEREG_MR) | \ + (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | \ + (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW) | (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) | \ + (1ULL << IB_USER_VERBS_CMD_RESIZE_CQ) | (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) | \ + (1ULL << IB_USER_VERBS_CMD_CREATE_QP) | (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) | \ + (1ULL << IB_USER_VERBS_CMD_QUERY_QP) | (1ULL << IB_USER_VERBS_CMD_DESTROY_QP) | \ + (1ULL << IB_USER_VERBS_CMD_ATTACH_MCAST) | (1ULL << IB_USER_VERBS_CMD_DETACH_MCAST) | \ + (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) | (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) | \ + (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) | (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) | \ + (1ULL << IB_USER_VERBS_CMD_OPEN_XRCD) | (1ULL << IB_USER_VERBS_CMD_CLOSE_XRCD) | \ + (1ULL << IB_USER_VERBS_CMD_CREATE_XSRQ) | (1ULL << IB_USER_VERBS_CMD_OPEN_QP)) +#endif + +#define ROCE_UVERBS_EXT_CMD_MASK (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ) + +enum roce3_load_balance_mode_e { + ROCE_LB_MODE_0 = 0, + ROCE_LB_MODE_1, + ROCE_LB_MODE_2, + ROCE_LB_MODE_N, +}; + +enum push_ofed_device_status { + ROCE_DEV_STATUS_NORMAL = 0, + ROCE_DEV_STATUS_CMDQ_TIMEOUT +}; + +enum roce3_func_state { + ROCE_FUNC_DISABLE = 0, + ROCE_FUNC_ENABLE +}; + +enum { + ROCE_Cl_TYPE_QPC = 0x0, /* cl_start: 0x0, cl_end: 0x7f, cl_size: 0 */ + ROCE_CL_TYPE_MPT = 0x1, /* cl_start: 0x150, cl_end: 0x15f, cl_size: 0 */ + ROCE_CL_TYPE_SQ_WQE = 0x2, /* cl_start: 0x80, cl_end: 0xff, cl_size: 0 */ + ROCE_CL_TYPE_RQ_WQE = 0x3, /* cl_start: 0x80, cl_end: 0xff, cl_size: 0 */ + ROCE_CL_TYPE_CQC_SRQC = 0x4, /* cl_start: 0x120, cl_end: 0x13f, cl_size: 0 */ + ROCE_CL_TYPE_RDMARC = 0x5, /* cl_start: 0x120, cl_end: 0x13f, cl_size: 0 */ + ROCE_CL_TYPE_CMTT = 0x6, /* cl_start: 0x100, cl_end: 0x11f, cl_size: 0 */ + ROCE_CL_TYPE_DMTT = 0x7 /* cl_start: 0x100, cl_end: 0x11f, cl_size: 0 */ +}; + +#define XRC_CONTAINER_FLAG ((int)(1L << 20)) + +struct roce3_notifier { + struct notifier_block nb; + struct notifier_block nb_inet; + struct notifier_block nb_inet6; +}; + +struct roce3_buf_list { + void *buf; + dma_addr_t map; +}; + +struct roce3_buf { + struct roce3_buf_list direct; + struct roce3_buf_list *page_list; + int nbufs; + + int npages; + int page_shift; +}; + +struct roce3_ucontext { + struct ib_ucontext ibucontext; + void __iomem *db_map; + void __iomem *dwqe_map; + u64 db_dma_addr; + u64 dwqe_dma_addr; + struct list_head db_page_list; + struct mutex db_page_mutex; +}; + +struct roce3_qp_cnt { + struct mutex cur_qps_mutex; + u32 alloc_qp_cnt; + u32 del_qp_cnt; +}; + +struct roce3_cdev_file { + struct roce3_cdev *cdev; +}; + +struct roce3_cdev { + struct cdev cdev; + /*lint -e104 -e808*/ + struct class *cdev_class; + /*lint +e104 +e808*/ + struct device *dev; + int dev_num; + dev_t dev_major; +}; + +struct roce3_netlink { + int dev_num; +}; + +struct roce3_dev_hw_info { + int config_num_ports; /* Number of ports from configuration file */ + int hca_type; /* HCA version: 4x25G or 2x100G */ + u8 phy_port; + u8 ep_id; /* EP ID */ + u8 cpu_endian; + u8 rsvd; + + bool is_vf; +}; + +bool roce3_is_roceaa(u8 scence_id); + +struct roce3_dev_cfg_info { + u8 scence_id; /* load scenes ID as aa_en */ + u8 lb_en; /* load balance enable */ + u8 lb_mode; /* load balance mode */ + u8 rsvd; + + u8 srq_container_en; + u8 srq_container_mode; + u8 xrc_srq_container_mode; + u8 warn_th; + + u8 fake_en; + u8 page_bit; + u8 pf_start_bit; + u8 pf_end_bit; + + u8 port_num; /* cfg data port num */ + u8 host_num; /* cfg data host num */ + u8 master_func; /* nofaa master func */ + u8 rsvd1; +}; + +struct roce3_device { + struct ib_device ib_dev; + struct hinic3_lld_dev *lld_dev; + struct net_device *ndev; + struct pci_dev *pdev; + void *hwdev; + void *hwdev_hdl; + // struct dev_version_info dev_ver; /*version info */ + struct hinic3_board_info board_info; + struct roce3_cdev cdev; + struct roce3_netlink netlink_dev; + + struct roce3_notifier notifier; + void __iomem *kernel_db_map; + void __iomem *kernel_dwqe_map; + spinlock_t node_desc_lock; + struct mutex cap_mask_mutex; + struct rdma_service_cap rdma_cap; + + u8 mac[6]; /* Mac addr. */ + u16 glb_func_id; + unsigned long status; + int ceq_num; + int ceqn[MAX_CEQ_NEED]; + int try_times; + bool ib_active; + + u8 group_rc_cos; + u8 group_ud_cos; + u8 group_xrc_cos; + + struct roce3_dev_hw_info hw_info; /* Hw info read from nic/pcie */ + struct roce3_dev_cfg_info cfg_info; /* Cfg data info read from MPU */ + +#ifdef ROCE_BONDING_EN + int want_bond_slave_cnt; + int want_bond_slave_bits[2]; /* The maximum number of bonds supported is 2 */ + enum ib_port_state port_state; + struct hinic3_dcb_state dcb_info; + char *sdi_bond_name; + struct roce3_bond_device *bond_dev; +#endif + + struct mutex mac_vlan_mutex; + struct list_head mac_vlan_list_head; + struct net_device **gid_dev; + + struct roce3_ecn_ctx ecn_ctx; + struct roce3_dfx_ctx dfx_ctx; + + struct roce3_qp_cnt qp_cnt; + + struct srcu_struct mr_srcu; + atomic_t num_prefetch; + struct completion comp_prefetch; + enum push_ofed_device_status dev_status_to_ofed; + + spinlock_t reset_flow_resource_lock; + struct list_head qp_list; + + void *fake_data_buf; + dma_addr_t fake_data_page_addr; + void *pri_roce_dev[ROCE_MAX_PORT_NUM]; // mailbox, ppf store all pf's roce device, to improve the effiency. + bool is_vroce; +}; + +static inline struct roce3_device *to_roce3_dev(const struct ib_device *ibdev) +{ + return container_of(ibdev, struct roce3_device, ib_dev); +} + +static inline struct roce3_ucontext *to_roce3_ucontext(const struct ib_ucontext *ibucontext) +{ + return container_of(ibucontext, struct roce3_ucontext, ibucontext); +} + +int roce3_db_map_user(struct roce3_ucontext *context, unsigned long virt, struct roce3_db *db); +void roce3_db_unmap_user(struct roce3_ucontext *context, struct roce3_db *db); + +int roce3_buf_write_mtt(struct roce3_device *rdev, struct rdma_mtt *mtt, struct tag_cqm_buf *buf); +int roce3_umem_write_mtt(struct roce3_device *rdev, struct rdma_mtt *mtt, struct ib_umem *umem); + +int roce3_query_device(struct ib_device *ibdev, struct ib_device_attr *props, struct ib_udata *uhw); + +int roce3_modify_device(struct ib_device *ibdev, int mask, struct ib_device_modify *props); + +int roce3_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_create_cq(struct ib_cq *cq, const struct ib_cq_init_attr *attr, struct ib_udata *udata); + +int roce3_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata); + +int roce3_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata); + +int roce3_create_srq(struct ib_srq *ibsrq, struct ib_srq_init_attr *init_attr, struct ib_udata *udata); + +int roce3_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); + +int roce3_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); + +int roce3_alloc_ucontext(struct ib_ucontext *ibucontext, struct ib_udata *udata); + +void roce3_dealloc_ucontext(struct ib_ucontext *ibcontext); + +int roce3_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); + +int roce3_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); + +int roce3_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *init_attr, struct ib_udata *udata); + +int roce3_destroy_ah(struct ib_ah *ibah, u32 flags); + +int roce3_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata); + +int roce3_dealloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata); + +int roce3_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata); + +int roce3_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); + + +int roce3_query_port(struct ib_device *device, u32 port_num, struct ib_port_attr *port_attr); + +int roce3_query_gid(struct ib_device *ibdev, u32 port, int index, union ib_gid *gid); + +int roce3_modify_port(struct ib_device *ibdev, u32 port, int mask, struct ib_port_modify *props); + +int roce3_port_immutable(struct ib_device *ibdev, u32 port_num, struct ib_port_immutable *immutable); + +struct net_device *roce3_ib_get_netdev(struct ib_device *ibdev, u32 port_num); + +enum rdma_link_layer roce3_port_link_layer(struct ib_device *ibdev, u32 port_num); + +int roce3_query_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey); + +int roce3_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *qp_init_attr, struct ib_udata *udata); +#else + +struct ib_cq *roce3_create_cq(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata); + +int roce3_destroy_cq(struct ib_cq *ibcq); + +int roce3_destroy_qp(struct ib_qp *ibqp); + +struct ib_srq *roce3_create_srq(struct ib_pd *ibpd, struct ib_srq_init_attr *init_attr, struct ib_udata *udata); + +int roce3_destroy_srq(struct ib_srq *ibsrq); + +int roce3_dereg_mr(struct ib_mr *ibmr); + +struct ib_ucontext *roce3_alloc_ucontext(struct ib_device *ibdev, struct ib_udata *udata); + +int roce3_dealloc_ucontext(struct ib_ucontext *ibcontext); + +struct ib_pd *roce3_alloc_pd(struct ib_device *ibdev, struct ib_ucontext *ibcontext, struct ib_udata *udata); + +int roce3_dealloc_pd(struct ib_pd *ibpd); + +#if LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +struct ib_ah *roce3_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, u32 flags, struct ib_udata *udata); +#else +struct ib_ah *roce3_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, struct ib_udata *udata); +#endif + +int roce3_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); + +#if LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +int roce3_destroy_ah(struct ib_ah *ibah, u32 flags); +#else +int roce3_destroy_ah(struct ib_ah *ibah); +#endif + +struct ib_xrcd *roce3_alloc_xrcd(struct ib_device *ibdev, struct ib_ucontext *ibcontext, struct ib_udata *udata); + +int roce3_dealloc_xrcd(struct ib_xrcd *ibxrcd); + +struct ib_mw *roce3_alloc_mw(struct ib_pd *ibpd, enum ib_mw_type type, struct ib_udata *udata); + +struct ib_qp *roce3_create_qp(struct ib_pd *ibpd, struct ib_qp_init_attr *init_attr, struct ib_udata *udata); + +int roce3_query_port(struct ib_device *ibdev, u8 port, struct ib_port_attr *props); + +enum rdma_link_layer roce3_port_link_layer(struct ib_device *ibdev, u8 port_num); + +int roce3_query_gid(struct ib_device *ibdev, u8 port, int index, union ib_gid *gid); + +int roce3_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey); + +int roce3_modify_port(struct ib_device *ibdev, u8 port, int mask, struct ib_port_modify *props); + +int roce3_port_immutable(struct ib_device *ibdev, u8 port_num, struct ib_port_immutable *immutable); + +struct net_device *roce3_ib_get_netdev(struct ib_device *ibdev, u8 port_num); +#endif // OFED_MLNX_5_8 + +int roce3_modify_cq(struct ib_cq *ibcq, u16 cq_count, u16 cq_period); + +int roce3_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); + +int roce3_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); + +int roce3_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); + + +int roce3_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata); + +int roce3_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, + struct ib_qp_init_attr *qp_init_attr); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr); +int roce3_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr); +#else +int roce3_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, struct ib_recv_wr **bad_wr); +int roce3_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, struct ib_recv_wr **bad_wr); +#endif + +void roce3_drain_rq(struct ib_qp *ibqp); + +int roce3_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, enum ib_srq_attr_mask attr_mask, + struct ib_udata *udata); + +int roce3_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); + +struct ib_mr *roce3_get_dma_mr(struct ib_pd *ibpd, int access); +struct ib_mr *roce3_alloc_mr(struct ib_pd *ibpd, enum ib_mr_type mr_type, u32 max_num_sg); +struct ib_mr *roce3_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 length, u64 virt_addr, int access, + struct ib_udata *udata); + +int roce3_map_kernel_frmr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, unsigned int *sg_offset); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + +struct ib_fmr *roce3_alloc_fmr(struct ib_pd *ibpd, int access, struct ib_fmr_attr *fmr_attr); + +int roce3_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list, int npages, u64 iova); + +int roce3_unmap_fmr(struct list_head *fmr_list); + +int roce3_dealloc_fmr(struct ib_fmr *ibfmr); + +#endif + +int roce3_dealloc_mw(struct ib_mw *ibmw); + +int roce3_query_device_status(struct ib_device *ibdev, int *dev_status); +int roce3_init_cdev(struct roce3_device *rdev); +void roce3_remove_cdev(struct roce3_device *rdev); +int roce3_bond_get_dcb_info(struct roce3_device *rdev); + +int roce3_init_sysfs(struct roce3_device *rdev); +void roce3_remove_sysfs(struct roce3_device *rdev); + +int roce3_is_eth_port_of_netdev(struct net_device *rdma_ndev, struct net_device *cookie); + +void roce3_async_event(void *svc_hd, u8 event_type, u8 *val); +u8 roce3_async_event_level(void *svc_hd, u8 event_type, u8 *val); +void roce3_cq_completion(void *svc_hd, u32 cqn, void *cq_handler); +void roce3_unregister_netdev_event(struct roce3_device *rdev); +int roce3_ifconfig_up_down_event_report(struct roce3_device *rdev, u8 net_event); +int roce3_register_netdev_event(struct roce3_device *rdev); +void roce3_clean_vlan_device_mac(struct roce3_device *rdev); +void roce3_clean_real_device_mac(struct roce3_device *rdev); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_ib_add_gid(const struct ib_gid_attr *attr, __always_unused void **context); +#else +int roce3_ib_add_gid(const union ib_gid *gid, const struct ib_gid_attr *attr, __always_unused void **context); +#endif + +int roce3_ib_del_gid(const struct ib_gid_attr *attr, __always_unused void **context); + +void roce3_remove_dev_file(struct roce3_device *rdev); +int roce3_init_dev_file(struct roce3_device *rdev); + +#endif // ROCE_H diff --git a/drivers/infiniband/hw/hiroce3/roce_cdev.c b/drivers/infiniband/hw/hiroce3/roce_cdev.c new file mode 100755 index 000000000..782a6c6fc --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_cdev.c @@ -0,0 +1,1218 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cdev.c + * Version : v2.0 + * Created : 2021/3/2 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE CHar device related functions. + */ + +#include <asm/io.h> +#include <linux/sched.h> +#include <asm/uaccess.h> +#include <asm/atomic.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/fs.h> +#include <linux/errno.h> +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/cdev.h> +#include <linux/timer.h> +#include <linux/slab.h> +#include <linux/device.h> +#include <linux/if_ether.h> + +#include "hinic3_hw.h" +#include "hinic3_srv_nic.h" + +#include "roce.h" +#include "roce_compat.h" +#include "roce_mix.h" +#include "roce_netdev.h" +#include "roce_k_ioctl.h" +#include "roce_cqm_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_cdev_extension.h" +#include "roce_verbs_cmd.h" +#include "roce_cmd.h" +#include "roce_srq.h" +#include "roce_qp.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#ifdef ROCE_EXTEND +#include "roce_qp_extension.h" +#endif + +#define P2PCOS_MAX_VALUE 2 +#define MAX_COS_NUM 0x7 + +static long roce3_cdev_create_ah(struct roce3_device *rdev, void *buf) +{ + long ret; + struct rdma_ah_attr attr; + union roce3_create_ah_buf ah_buf; + struct ib_udata udata; + + ret = (long)copy_from_user(&ah_buf, buf, sizeof(ah_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + + attr.sl = ah_buf.cmd.attr.sl; + attr.static_rate = ah_buf.cmd.attr.static_rate; + attr.ah_flags = (ah_buf.cmd.attr.is_global != 0) ? IB_AH_GRH : 0; + attr.port_num = ah_buf.cmd.attr.port_num; + attr.grh.flow_label = ah_buf.cmd.attr.grh.flow_label; + attr.grh.sgid_index = ah_buf.cmd.attr.grh.sgid_index; + attr.grh.hop_limit = ah_buf.cmd.attr.grh.hop_limit; + attr.grh.traffic_class = ah_buf.cmd.attr.grh.traffic_class; + memset(attr.roce.dmac, 0, sizeof(attr.roce.dmac)); + memcpy(attr.grh.dgid.raw, ah_buf.cmd.attr.grh.dgid, ROCE_GID_LEN); + + memset(&udata, 0, sizeof(struct ib_udata)); + if (roce3_resolve_grh(rdev, &attr, &ah_buf.resp.vlan_id, &udata) != 0) { + pr_err("[ROCE, ERR] %s: Failed to resolve grh\n", __func__); + return -EINVAL; + } + + memcpy(ah_buf.resp.dmac, attr.roce.dmac, ETH_ALEN); + + ret = (long)copy_to_user((void __user *)buf, &ah_buf, sizeof(ah_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; +} + +#ifdef ROCE_BONDING_EN + +struct roce3_get_rx_port { + __be32 rx_port; +}; + +struct roce3_get_func_table { + __be32 func_table_val; +}; + +struct roce3_get_udp_src_port { + __be32 udp_src_port; +}; + +static struct roce3_qp *roce3_cdev_lookup_rqp(struct roce3_device *rdev, u32 qpn) +{ + cqm_object_s *cqm_obj_qp = NULL; + struct roce3_qp *rqp = NULL; + + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, qpn, false); + if (cqm_obj_qp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Can't find rqp according to qpn(0x%x), func_id(%d)\n", __func__, qpn, + rdev->glb_func_id); + return NULL; + } + + rqp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + + return rqp; +} + +static int roce3_get_qp_func_table(struct roce3_device *rdev, u32 qpn, u32 *func_table_val) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_get_qp_func_table_s *get_func_tbl_inbuf = NULL; + struct roce3_get_func_table *get_func_tbl_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_get_qp_func_table_s), + &cqm_cmd_outbuf, (u16)sizeof(roce_get_qp_func_table_s)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + get_func_tbl_inbuf = (roce_get_qp_func_table_s *)cqm_cmd_inbuf->buf; + get_func_tbl_inbuf->com.index = cpu_to_be32(qpn); + get_func_tbl_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_GET_QP_FUNC_TABLE, + cqm_cmd_inbuf, cqm_cmd_outbuf, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send ROCE_CMD_GET_QP_FUNC_TABLE command, func_id(%d)\n", + __func__, rdev->glb_func_id); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return -1; + } + get_func_tbl_outbuf = (struct roce3_get_func_table *)cqm_cmd_outbuf->buf; + *func_table_val = be32_to_cpu(get_func_tbl_outbuf->func_table_val); + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return 0; +} + +static long roce3_cdev_query_qp_tx_port(struct roce3_device *rdev, void *buf) +{ + long ret; + u32 slave_cnt; + struct roce3_qp *rqp = NULL; + struct roce3_qp_port_buf qp_port_buf; + u32 func_tbl_value = 0; + + memset(&qp_port_buf, 0, sizeof(qp_port_buf)); + ret = (long)copy_from_user(&qp_port_buf, buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + + rqp = roce3_cdev_lookup_rqp(rdev, qp_port_buf.qpn); + if (rqp == NULL) { + pr_err("[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return EINVAL; + } + + if (!roce3_bond_is_active(rdev)) { + qp_port_buf.port = 0; + + ret = (long)copy_to_user((void __user *)buf, &qp_port_buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; + } + + ret = (long)roce3_get_qp_func_table(rdev, qp_port_buf.qpn, &func_tbl_value); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get func_tbl, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + slave_cnt = func_tbl_value & 0xf; + if (slave_cnt == 0) { + pr_err("[ROCE, ERR] %s: slave_cnt is 0\n", __func__); + return EINVAL; + } + + qp_port_buf.port = (func_tbl_value >> + (ROCE_BOND_FWD_ID_TBL_ALL_BITS - ((rqp->tx_hash_value % slave_cnt + 1) * ROCE_BOND_FWD_ID_TBL_PER_BITS))) & + ROCE_BOND_FWD_ID_TBL_PER_BITS_MASK; + + ret = (long)copy_to_user((void __user *)buf, &qp_port_buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; +} + +static int roce3_modify_bond_hash_value(struct roce3_device *rdev, u32 qpn, u32 new_hash_value) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_modify_hash_value_s *modify_hash_value = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_modify_hash_value_s), NULL, + 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + modify_hash_value = (roce_modify_hash_value_s *)cqm_cmd_inbuf->buf; + + modify_hash_value->com.index = cpu_to_be32(qpn); + modify_hash_value->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + modify_hash_value->hash_value = cpu_to_be32(new_hash_value); + + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_MODIFY_HASH_VALUE_QP, cqm_cmd_inbuf, NULL, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send MODIFY_HASH_VALUE_QP command, func_id(%d)\n", __func__, + rdev->glb_func_id); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return 0; +} + +static long roce3_cdev_set_qp_tx_port(struct roce3_device *rdev, const void *buf) +{ + long ret; + u32 new_tx_hash_value; + u32 slave_cnt; + u32 target_hash_port; + u32 old_hash_port; + struct roce3_qp *rqp = NULL; + struct roce3_qp_port_buf qp_port_buf; + u32 func_tbl_value = 0; + + ret = (long)copy_from_user(&qp_port_buf, buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + + /* check qp exist */ + rqp = roce3_cdev_lookup_rqp(rdev, qp_port_buf.qpn); + if (rqp == NULL) { + pr_err("[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return -EINVAL; + } + + if (!roce3_bond_is_active(rdev)) { + return 0; + } + + ret = (long)roce3_get_qp_func_table(rdev, qp_port_buf.qpn, &func_tbl_value); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get func_tbl, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + slave_cnt = func_tbl_value & 0xf; + if (slave_cnt == 0) { + pr_err("[ROCE, ERR] %s: slave_cnt is 0\n", __func__); + return EINVAL; + } + target_hash_port = qp_port_buf.port & ROCE_BOND_FWD_ID_TBL_PER_BITS_MASK; + + old_hash_port = (func_tbl_value >> + (ROCE_BOND_FWD_ID_TBL_ALL_BITS - ((rqp->tx_hash_value % slave_cnt + 1) * ROCE_BOND_FWD_ID_TBL_PER_BITS))) & + ROCE_BOND_FWD_ID_TBL_PER_BITS_MASK; + + if (target_hash_port == old_hash_port) { + return 0; + } + + new_tx_hash_value = rqp->tx_hash_value + (((slave_cnt - old_hash_port) + target_hash_port) % slave_cnt); + + ret = (long)roce3_modify_bond_hash_value(rdev, rqp->qpn, new_tx_hash_value); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify QP(0x%06x) hash value, func_id(%d)\n", __func__, + rqp->qpn, rdev->glb_func_id); + return EIO; + } + + rqp->tx_hash_value = new_tx_hash_value; + + return 0; +} + +static int roce3_get_qp_rx_port(struct roce3_device *rdev, u32 qpn, u32 *rx_port) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_get_qp_rx_port_s *get_rx_port_inbuf = NULL; + struct roce3_get_rx_port *get_rx_port_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_get_qp_rx_port_s), + &cqm_cmd_outbuf, (u16)sizeof(roce_get_qp_rx_port_s)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + get_rx_port_inbuf = (roce_get_qp_rx_port_s *)cqm_cmd_inbuf->buf; + get_rx_port_inbuf->com.index = cpu_to_be32(qpn); + get_rx_port_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_GET_QP_RX_PORT, + cqm_cmd_inbuf, cqm_cmd_outbuf, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send ROCE_CMD_GET_QP_RX_PORT command, func_id(%d)\n", + __func__, rdev->glb_func_id); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return -1; + } + get_rx_port_outbuf = (struct roce3_get_rx_port *)cqm_cmd_outbuf->buf; + *rx_port = be32_to_cpu(get_rx_port_outbuf->rx_port); + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return 0; +} + +static long roce3_cdev_query_qp_rx_port(struct roce3_device *rdev, void *buf) +{ + long ret; + u32 rx_port = 0; + struct roce3_qp *rqp = NULL; + struct roce3_qp_port_buf qp_port_buf; + + memset(&qp_port_buf, 0, sizeof(qp_port_buf)); + ret = (long)copy_from_user(&qp_port_buf, buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + + rqp = roce3_cdev_lookup_rqp(rdev, qp_port_buf.qpn); + if (rqp == NULL) { + pr_err("[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return EINVAL; + } + + if (rqp->qp_type != IB_QPT_RC) { + pr_err("[ROCE, ERR] %s: not support qp type(%d), only support RC.\n", __func__, rqp->qp_type); + return EINVAL; + } + + if (!roce3_bond_is_active(rdev)) { + qp_port_buf.port = 0; + + ret = (long)copy_to_user((void __user *)buf, &qp_port_buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; + } + + ret = (long)roce3_get_qp_rx_port(rdev, qp_port_buf.qpn, &rx_port); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get QP(0x%06x) rx port\n", __func__, qp_port_buf.qpn); + return ret; + } + + qp_port_buf.port = rx_port; + + ret = (long)copy_to_user((void __user *)buf, &qp_port_buf, sizeof(qp_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; +} + +static long roce3_cdev_query_next_wqe_idx(struct roce3_device *rdev, void *buf) +{ + long ret; + int ret_adm; + struct roce3_dfx_query_inbuf dfx_query_inbuf = {0}; + u32 out_size = (u32)sizeof(union roce3_dfx_query_outbuf); + union roce3_dfx_query_outbuf dfx_query_outbuf; + int next_wqe_idx; + + ret = (long)copy_from_user(&dfx_query_inbuf, buf, sizeof(dfx_query_inbuf)); + if (ret != 0) { + (void)pr_err("[ROCE] %s: Failed to copy data from user, ret(0x%lux)\n", __func__, ret); + return ret; + } + + dfx_query_inbuf.cmd_type = ROCE_CMD_GET_SRQC_FROM_CACHE; + ret_adm = roce3_adm_dfx_query(rdev, &dfx_query_inbuf, sizeof(dfx_query_inbuf), &dfx_query_outbuf, &out_size); + if (ret_adm != 0) { + (void)pr_err("[ROCE] %s: Failed to do roce_adm_dfx_query, ret(%d)\n", __func__, ret_adm); + return EINVAL; + } + + dfx_query_outbuf.srq_ctx.dw2.value = be32_to_cpu(dfx_query_outbuf.srq_ctx.dw2.value); + dfx_query_outbuf.srq_ctx.dw3.value = be32_to_cpu(dfx_query_outbuf.srq_ctx.dw3.value); + dfx_query_outbuf.srq_ctx.dw5.value = be32_to_cpu(dfx_query_outbuf.srq_ctx.dw5.value); + + if (dfx_query_outbuf.srq_ctx.dw2.bs.container_en == 0) { + next_wqe_idx = (int)(dfx_query_outbuf.srq_ctx.dw5.bs.next_wqe_idx); + } else { + u32 container_mode = MAX_SUPPORT_CONTAINER_MODE - dfx_query_outbuf.srq_ctx.dw2.bs_c.container_size; + u32 container_size = roce3_get_container_sz(container_mode); + next_wqe_idx = (int)(container_size * dfx_query_outbuf.srq_ctx.dw3.bs_c.head_index); + } + ret = (long)copy_to_user((void __user *)buf, &next_wqe_idx, sizeof(int)); + if (ret != 0) { + (void)pr_err("[ROCE] %s: Failed to copy next_wqe_idx to user, ret(0x%lx)\n", __func__, ret); + return ret; + } + + return 0; +} + +static void roce3_cdev_set_bond_port_info( + struct roce3_bond_device *bond_dev, u32 func_tbl_value, struct roce3_bond_port_info_buf *bond_port_info_buf) +{ + u32 i; + + bond_port_info_buf->original_port_num = bond_dev->slave_cnt; + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + bond_port_info_buf->original_port[i] = bond_dev->slaves[i].func_id; + } + mutex_unlock(&bond_dev->slave_lock); + + bond_port_info_buf->alive_port_num = func_tbl_value & 0xf; + for (i = 0; i < bond_port_info_buf->alive_port_num; i++) { + bond_port_info_buf->alive_port[i] = + (func_tbl_value >> (ROCE_BOND_FWD_ID_TBL_ALL_BITS - ((i + 1) * ROCE_BOND_FWD_ID_TBL_PER_BITS))) & + ROCE_BOND_FWD_ID_TBL_PER_BITS_MASK; + } +} + +static long roce3_cdev_query_bond_port_info(struct roce3_device *rdev, void *buf) +{ + long ret; + struct roce3_bond_device *bond_dev = NULL; + struct roce3_bond_port_info_buf bond_port_info_buf; + u32 func_tbl_value = 0; + + memset(&bond_port_info_buf, 0, sizeof(bond_port_info_buf)); + + if (!roce3_bond_is_active(rdev)) { + ret = (long)copy_to_user((void __user *)buf, &bond_port_info_buf, sizeof(bond_port_info_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; + } + + bond_dev = rdev->bond_dev; + if (bond_dev == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Can't find bond_dev, func_id(%d)\n", __func__, rdev->glb_func_id); + return EINVAL; + } + + ret = roce3_get_func_table(rdev->hwdev, rdev->glb_func_id, &func_tbl_value); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get func_tbl, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + roce3_cdev_set_bond_port_info(bond_dev, func_tbl_value, &bond_port_info_buf); + + ret = (long)copy_to_user((void __user *)buf, &bond_port_info_buf, sizeof(bond_port_info_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; +} + +static int roce3_modify_udp_src_port(struct roce3_device *rdev, u32 qpn, u32 new_udp_src_port) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_modify_udp_src_port_s *modify_udp_src_port = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_modify_udp_src_port_s), + NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + modify_udp_src_port = (roce_modify_udp_src_port_s *)cqm_cmd_inbuf->buf; + modify_udp_src_port->com.index = cpu_to_be32(qpn); + modify_udp_src_port->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + modify_udp_src_port->udp_src_port = cpu_to_be32(new_udp_src_port); + + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_MODIFY_UDP_SRC_PORT_QP, cqm_cmd_inbuf, NULL, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send MODIFY_HASH_VALUE_QP command, func_id(%d)\n", __func__, + rdev->glb_func_id); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return 0; +} + +static long roce3_cdev_set_qp_udp_src_port(struct roce3_device *rdev, const void *buf) +{ + long ret; + struct roce3_qp *rqp = NULL; + struct roce3_qp_udp_src_port_buf qp_udp_src_port_buf; + + ret = (long)copy_from_user(&qp_udp_src_port_buf, buf, sizeof(qp_udp_src_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + + /* check qp exist */ + rqp = roce3_cdev_lookup_rqp(rdev, qp_udp_src_port_buf.qpn); + if (rqp == NULL) { + pr_err("[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return EINVAL; + } + + ret = (long)roce3_modify_udp_src_port(rdev, rqp->qpn, qp_udp_src_port_buf.udp_src_port); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify QP(0x%06x) hash value, func_id(%d)\n", __func__, + rqp->qpn, rdev->glb_func_id); + return EIO; + } + + return 0; +} + +static int roce3_get_qp_udp_src_port(struct roce3_device *rdev, u32 qpn, u32 *udp_src_port) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_get_qp_udp_src_port_s *get_udp_src_port = NULL; + struct roce3_get_udp_src_port *get_udp_src_port_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_get_qp_udp_src_port_s), + &cqm_cmd_outbuf, (u16)sizeof(roce_get_qp_udp_src_port_s)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + get_udp_src_port = (roce_get_qp_udp_src_port_s *)cqm_cmd_inbuf->buf; + get_udp_src_port->com.index = cpu_to_be32(qpn); + get_udp_src_port->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + + ret = roce3_send_qp_lb_cmd(qpn, rdev, ROCE_CMD_GET_UDP_SRC_PORT_QP, + cqm_cmd_inbuf, cqm_cmd_outbuf, ROCE_CMD_TIME_CLASS_A); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send ROCE_CMD_GET_QP_RX_PORT command, func_id(%d)\n", + __func__, rdev->glb_func_id); + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return -1; + } + + get_udp_src_port_outbuf = (struct roce3_get_udp_src_port *)cqm_cmd_outbuf->buf; + *udp_src_port = be32_to_cpu(get_udp_src_port_outbuf->udp_src_port); + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return 0; +} + +static long roce3_cdev_query_qp_udp_src_port(struct roce3_device *rdev, void *buf) +{ + long ret; + u32 udp_src_port = 0; + struct roce3_qp_udp_src_port_buf qp_udp_src_port_buf; + + memset(&qp_udp_src_port_buf, 0, sizeof(qp_udp_src_port_buf)); + ret = (long)copy_from_user(&qp_udp_src_port_buf, buf, sizeof(qp_udp_src_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + + ret = (long)roce3_get_qp_udp_src_port(rdev, qp_udp_src_port_buf.qpn, &udp_src_port); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get QP(0x%06x) udp src port\n", __func__, qp_udp_src_port_buf.qpn); + return ret; + } + + qp_udp_src_port_buf.udp_src_port = udp_src_port; + + ret = (long)copy_to_user((void __user *)buf, &qp_udp_src_port_buf, sizeof(qp_udp_src_port_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + + return 0; +} + +#endif + +static int roce3_cdev_open(struct inode *inode, struct file *filp) +{ + struct roce3_cdev *dev = NULL; + struct roce3_cdev_file *file = NULL; + + file = kzalloc(sizeof(*file), GFP_KERNEL); + if (file == NULL) { + pr_err("[ROCE, ERR] %s: Failed to open cdev\n", __func__); + return -ENOMEM; + } + + dev = container_of(inode->i_cdev, struct roce3_cdev, cdev); + file->cdev = dev; + filp->private_data = file; + + return 0; +} + +static int roce3_cdev_close(struct inode *inode, struct file *filp) +{ + struct roce3_cdev_file *file = filp->private_data; + + kfree(file); + + return 0; +} + +static ssize_t roce3_cdev_read(struct file *fp, char __user *buf, size_t size, loff_t *pos) +{ + (void)(fp); + (void)(buf); + (void)(size); + (void)(pos); + return -EOPNOTSUPP; +} + +static ssize_t roce3_cdev_write(struct file *fp, const char __user *buf, size_t size, loff_t *pos) +{ + (void)(fp); + (void)(buf); + (void)(size); + (void)(pos); + return -EOPNOTSUPP; +} + +#ifdef ROCE_BONDING_EN +static long roce3_cdev_bonding_ioctl_part_1(unsigned int cmd, unsigned long arg, struct roce3_device *rdev) +{ + long ret = 0; + + switch (cmd) { + case ROCE_CMD_QUERY_QP_TX_PORT: + ret = roce3_cdev_query_qp_tx_port(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_query_qp_tx_port failed.\n", __func__); + return ret; + } + break; + + case ROCE_CMD_SET_QP_TX_PORT: + ret = roce3_cdev_set_qp_tx_port(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_set_qp_tx_port failed.\n", __func__); + return ret; + } + break; + case ROCE_CMD_QUERY_QP_RX_PORT: + ret = roce3_cdev_query_qp_rx_port(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_query_qp_rx_port failed.\n", __func__); + return ret; + } + break; + default: + pr_err("[ROCE, ERR] %s: Not supported cmd(%d).\n", __func__, cmd); + ret = -1; + return ret; + } + + return ret; +} + +static long roce3_cdev_bonding_ioctl_part_2(unsigned int cmd, unsigned long arg, struct roce3_device *rdev) +{ + long ret = 0; + + switch (cmd) { + case ROCE_CMD_QUERY_BOND_PORT_INFO: + ret = roce3_cdev_query_bond_port_info(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_query_qp_tx_port failed.\n", __func__); + return ret; + } + break; + + case ROCE_CMD_SET_QP_UDP_SRC_PORT: + ret = roce3_cdev_set_qp_udp_src_port(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_set_qp_tx_port failed.\n", __func__); + return ret; + } + break; + case ROCE_CMD_QUERY_QP_UDP_SRC_PORT: + ret = roce3_cdev_query_qp_udp_src_port(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_query_qp_rx_port failed.\n", __func__); + return ret; + } + break; + + case ROCE_CMD_QUERY_NEXT_WQE_IDX: + ret = roce3_cdev_query_next_wqe_idx(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_query_next_wqe_idx failed.\n", __func__); + return ret; + } + break; + + default: + pr_err("[ROCE, ERR] %s: Not supported cmd(%d).\n", __func__, cmd); + ret = -1; + return ret; + } + + return ret; +} +static long roce3_cdev_ioctl_bonding(unsigned int cmd, unsigned long arg, struct roce3_device *rdev) +{ + long ret = 0; + + if (cmd < ROCE_CMD_QUERY_BOND_PORT_INFO) { + ret = roce3_cdev_bonding_ioctl_part_1(cmd, arg, rdev); + if (ret != 0) { + return ret; + } + } else { + ret = roce3_cdev_bonding_ioctl_part_2(cmd, arg, rdev); + if (ret != 0) { + return ret; + } + } + + return ret; +} + +static int roce3_bond_get_dcb_info_from_buddy(struct roce3_device *rdev, struct roce3_bond_device *bond_dev) +{ + int i; + int ret; + struct roce3_bond_slave *slave = NULL; + struct hinic3_lld_dev *lld_dev = NULL; + struct hinic3_dcb_state dcb_info, buddy_dcb_info; + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id == rdev->glb_func_id) { + continue; + } + + if ((bond_dev->attr.active_slaves & (1U << slave->func_id)) == 0) { + continue; + } + + memset(&buddy_dcb_info, 0, sizeof(buddy_dcb_info)); + + lld_dev = hinic3_get_lld_dev_by_netdev(slave->netdev); + if (!lld_dev) { + mutex_unlock(&bond_dev->slave_lock); + return -ENODEV; + } + ret = hinic3_get_dcb_state(lld_dev->hwdev, &buddy_dcb_info); + if (ret != 0) { + mutex_unlock(&bond_dev->slave_lock); + pr_err("[ROCE, ERR] %s: Failed to get dcb state, ret(%d)\n", __func__, ret); + return ret; + } + + memset(&dcb_info, 0, sizeof(dcb_info)); + + ret = hinic3_get_dcb_state(rdev->hwdev, &dcb_info); + if (ret != 0) { + mutex_unlock(&bond_dev->slave_lock); + pr_err("[ROCE, ERR] %s: Failed to get dcb state, ret(%d)\n", __func__, ret); + return ret; + } + + buddy_dcb_info.default_cos = dcb_info.default_cos; + for (i = 0; i < NIC_DCB_UP_MAX; i++) { + if (buddy_dcb_info.pcp2cos[i] > P2PCOS_MAX_VALUE) { + buddy_dcb_info.pcp2cos[i] = dcb_info.default_cos; + } + } + + memcpy(&rdev->dcb_info, &buddy_dcb_info, sizeof(buddy_dcb_info)); + + mutex_unlock(&bond_dev->slave_lock); + return ret; + } + + mutex_unlock(&bond_dev->slave_lock); + return 0; +} + +int roce3_bond_get_dcb_info(struct roce3_device *rdev) +{ + bool bond_dev_up; + int ret; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!roce3_bond_is_active(rdev)) { + return 0; + } + + bond_dev_up = (bond_dev->attr.active_slaves & ((unsigned int)1 << rdev->glb_func_id)) != 0; + if (!bond_dev_up) { + ret = hinic3_get_dcb_state(rdev->hwdev, &rdev->dcb_info); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get dcb state, ret(%d)\n", __func__, ret); + return ret; + } + } else { + ret = roce3_bond_get_dcb_info_from_buddy(rdev, bond_dev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get dcb state from buddy, ret(%d)\n", __func__, ret); + return ret; + } + } + + return 0; +} +#endif + +static long roce3_cdev_query_dcb(struct roce3_device *rdev, void *buf) +{ + union roce3_query_dcb_buf dcb_buf; + long ret; + int get_group_id; + struct roce_group_id group_id = {0}; + u8 cos; + ret = (long)copy_from_user(&dcb_buf, buf, sizeof(dcb_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return ret; + } + +#ifdef ROCE_BONDING_EN + if (roce3_bond_get_dcb_info(rdev) != 0) { + pr_err("[ROCE, ERR] %s: Failed to get dcb info, ret(%lu)\n", __func__, ret); + return (-EINVAL); + } +#endif + + ret = (long)roce3_get_dcb_cfg_cos(rdev, (roce3_get_cos_inbuf_s *)(void *)(&dcb_buf), &cos); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get cos from dcb info, ret:%ld\n", __func__, ret); + return ret; + } + + dcb_buf.resp.cos = cos; + + if (rdev->is_vroce) { + get_group_id = roce3_get_group_id(rdev->glb_func_id, rdev->hwdev, &group_id); + if (get_group_id != 0) { + pr_warn("Failed to get group id, ret(%d)", get_group_id); + } else { + rdev->group_rc_cos = group_id.group_rc_cos; + rdev->group_ud_cos = group_id.group_ud_cos; + rdev->group_xrc_cos = group_id.group_xrc_cos; + } + if (dcb_buf.cmd.dscp_type == (u8)IB_QPT_RC) { + dcb_buf.resp.cos = rdev->group_rc_cos & MAX_COS_NUM; + } else if (dcb_buf.cmd.dscp_type == (u8)IB_QPT_UD) { + dcb_buf.resp.cos = rdev->group_ud_cos & MAX_COS_NUM; + } else { + dcb_buf.resp.cos = rdev->group_xrc_cos & MAX_COS_NUM; + } + } + + ret = (long)copy_to_user((void __user *)buf, &dcb_buf, sizeof(dcb_buf)); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to copy data to user\n", __func__); + return ret; + } + return 0; +} + +static long roce3_cdev_ioctl_non_bonding(unsigned int cmd, struct roce3_device *rdev, unsigned long arg) +{ + long ret = 0; + + switch (cmd) { + case ROCE_CMD_QUERY_DCB: + ret = roce3_cdev_query_dcb(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_query_dcb failed.\n", __func__); + return ret; + } + break; + + case ROCE_CMD_CREATE_AH: + ret = roce3_cdev_create_ah(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_cdev_create_ah failed.\n", __func__); + return ret; + } + break; + + default: + ret = ioctl_non_bonding_extend(cmd, rdev, arg); + if (ret != NOT_SUPOORT_TYPE) { + return ret; + } + pr_err("[ROCE, ERR] %s: Not supported cmd(%d).\n", __func__, cmd); + ret = -1; + return ret; + } + + return ret; +} + +static long roce3_ioctrl_version(struct roce3_device *rdev, void *buf); +static long roce3_ioctrl_reserved_1(struct roce3_device *rdev, void *buf); +static long roce3_ioctrl_reserved_2(struct roce3_device *rdev, void *buf); +static long roce3_ioctrl_reserved_3(struct roce3_device *rdev, void *buf); +static long roce3_ioctrl_reserved_4(struct roce3_device *rdev, void *buf); +static long roce3_ioctrl_reserved_5(struct roce3_device *rdev, void *buf); +static long roce3_ioctrl_reserved_6(struct roce3_device *rdev, void *buf); + +typedef struct tag_HW_ROCE_IOCTL_ACTION { + unsigned int cmd; + long (*action_func)(struct roce3_device *rdev, void *buf); +}HW_ROCE_IOCTL_ACTION; + +static HW_ROCE_IOCTL_ACTION ioctl_reserved_tbl[] = { + {HW_ROCE_CMD_VERSION, roce3_ioctrl_version}, + {HW_ROCE_CMD_RESERVED_1, roce3_ioctrl_reserved_1}, + {HW_ROCE_CMD_RESERVED_2, roce3_ioctrl_reserved_2}, + {HW_ROCE_CMD_RESERVED_3, roce3_ioctrl_reserved_3}, + {HW_ROCE_CMD_RESERVED_4, roce3_ioctrl_reserved_4}, + {HW_ROCE_CMD_RESERVED_5, roce3_ioctrl_reserved_5}, + {HW_ROCE_CMD_RESERVED_6, roce3_ioctrl_reserved_6}, +}; + +static long roce3_cdev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + long ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_cdev_file *cdev_file = NULL; + unsigned int idx = 0; + + if (_IOC_TYPE(cmd) != ROCE_IOCTL_MAGIC) { + pr_err("[ROCE, ERR] %s: ROCE_IOCTL_MAGIC check failed.\n", __func__); + return -EINVAL; + } + + cdev_file = filp->private_data; + rdev = container_of(cdev_file->cdev, struct roce3_device, cdev); + + if (cmd < ROCE_CMD_QUERY_QP_TX_PORT) { + ret = roce3_cdev_ioctl_non_bonding(cmd, rdev, arg); + return ret; + } +#ifdef ROCE_BONDING_EN + else if (cmd < ROCE_CMD_MAX) { + ret = roce3_cdev_ioctl_bonding(cmd, arg, rdev); + return ret; + } +#endif +#ifdef ROCE_EXTEND + else if (cmd == HW_ROCE_EXT_CMD_SET_QP_ATTR) { + ret = (long)roce3_set_qp_ext_attr(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_set_qp_ext_attr failed.\n", __func__); + } + return ret; + } else if (cmd == HW_ROCE_EXT_CMD_CREATE_SQPC) { + ret = (long)roce3_vbs_create_sqpc(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: roce3_vbs_create_sqpc failed.\n", __func__); + } + return ret; + } +#endif + + for (idx = 0; idx < sizeof(ioctl_reserved_tbl) / sizeof((ioctl_reserved_tbl)[0]); idx++) { + if (cmd == ioctl_reserved_tbl[idx].cmd && ioctl_reserved_tbl[idx].action_func != NULL) { + ret = ioctl_reserved_tbl[idx].action_func(rdev, (void *)(uintptr_t)arg); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: cmd 0x%x ioctl action failed ret %ld.\n", __func__, cmd, ret); + } + return ret; // cmd excute end + } + } + // unsupport cmd + pr_err("[ROCE, ERR] %s: Not supported cmd(%d).\n", __func__, cmd); + return -EOPNOTSUPP; +} + +static const struct file_operations roce3_cdev_fops = { + .owner = THIS_MODULE, + .open = roce3_cdev_open, + .release = roce3_cdev_close, + .read = roce3_cdev_read, + .write = roce3_cdev_write, + .unlocked_ioctl = roce3_cdev_ioctl, +}; + +#define ROCE_BASE_CDEV_MAJOR 232 +#define ROCE_BASE_CDEV_MINOR 256 +#define ROCE_MAX_DEVICES 256 + +/*lint -e708*/ +static DEFINE_SPINLOCK(map_lock); +/*lint +e708*/ +static DECLARE_BITMAP(dev_map, ROCE_MAX_DEVICES); + +static char *roce3_devnode(const struct device *dev, umode_t *mode) +{ + if (mode) { + *mode = DEFAULT_ROCE_DEV_NODE_PRI; + } + + return kasprintf(GFP_KERNEL, "%s", dev_name(dev)); +} + +static int roce3_init_cdev_info(struct roce3_device *rdev) +{ + int ret; + + cdev_init(&rdev->cdev.cdev, &roce3_cdev_fops); + rdev->cdev.cdev.owner = THIS_MODULE; + rdev->cdev.cdev.ops = &roce3_cdev_fops; + + ret = cdev_add(&rdev->cdev.cdev, rdev->cdev.dev_major, 1); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Add cdev failed, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_add_cdev; + } + + /*lint -e160*/ + rdev->cdev.cdev_class = class_create(rdev->ib_dev.name); + /*lint +e160*/ + if (IS_ERR(rdev->cdev.cdev_class)) { + ret = (int)PTR_ERR(rdev->cdev.cdev_class); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Create class failed, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_create_class; + } + + /*lint -e10 -e40 -e63*/ + rdev->cdev.cdev_class->devnode = roce3_devnode; + /*lint +e10 +e40 +e63*/ + + rdev->cdev.dev = device_create(rdev->cdev.cdev_class, NULL, rdev->cdev.dev_major, NULL, "%s", rdev->ib_dev.name); + if (IS_ERR(rdev->cdev.dev)) { + ret = (int)PTR_ERR(rdev->cdev.dev); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Create device failed, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_create_device; + } + + return 0; + +err_create_device: + class_destroy(rdev->cdev.cdev_class); + +err_create_class: + cdev_del(&rdev->cdev.cdev); + +err_add_cdev: + return ret; +} + +int roce3_init_cdev(struct roce3_device *rdev) +{ + int ret; + + spin_lock(&map_lock); + rdev->cdev.dev_num = (int)find_first_zero_bit(dev_map, ROCE_MAX_DEVICES); + if (rdev->cdev.dev_num >= ROCE_MAX_DEVICES) { + spin_unlock(&map_lock); + return -ENOMEM; + } + + rdev->cdev.dev_major = MKDEV(ROCE_BASE_CDEV_MAJOR, (u32)rdev->cdev.dev_num + ROCE_BASE_CDEV_MINOR); + set_bit((u32)rdev->cdev.dev_num, dev_map); + spin_unlock(&map_lock); + + ret = register_chrdev_region(rdev->cdev.dev_major, 1, rdev->ib_dev.name); + if (ret == -EBUSY) { + /* alloc dynamic cdev by OS */ + ret = alloc_chrdev_region(&(rdev->cdev.dev_major), ROCE_BASE_CDEV_MINOR, 1, rdev->ib_dev.name); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: alloc cdev region, major(%d), minor(%d), func_id(%d), ret(%d)\n", + __func__, MAJOR(rdev->cdev.dev_major), MINOR(rdev->cdev.dev_major), rdev->glb_func_id, ret); + } + + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Register region failed, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + goto err_register_region; + } + + ret = roce3_init_cdev_info(rdev); + if (ret != 0) { + goto err_init_cdev_info; + } + + return 0; + +err_init_cdev_info: + unregister_chrdev_region(rdev->cdev.dev_major, 1); + +err_register_region: + clear_bit(rdev->cdev.dev_num, dev_map); + + return ret; +} + +void roce3_remove_cdev(struct roce3_device *rdev) +{ + device_destroy(rdev->cdev.cdev_class, rdev->cdev.dev_major); + + class_destroy(rdev->cdev.cdev_class); + + cdev_del(&rdev->cdev.cdev); + + unregister_chrdev_region(rdev->cdev.dev_major, 1); + + clear_bit(rdev->cdev.dev_num, dev_map); +} + +// get version +static long roce3_ioctrl_version(struct roce3_device *rdev, void *buf) +{ + char ver[VERSION_LEN] = "1.01"; + long ret = copy_to_user(buf, ver, VERSION_LEN); + return ret; +} + +static long roce3_ioctrl_reserved_1(struct roce3_device *rdev, void *buf) +{ + (void)(rdev); + (void)(buf); + return NOT_SUPOORT_TYPE; +} + +static long roce3_ioctrl_reserved_2(struct roce3_device *rdev, void *buf) +{ + (void)(rdev); + (void)(buf); + return NOT_SUPOORT_TYPE; +} + +static long roce3_ioctrl_reserved_3(struct roce3_device *rdev, void *buf) +{ + (void)(rdev); + (void)(buf); + return NOT_SUPOORT_TYPE; +} + +static long roce3_ioctrl_reserved_4(struct roce3_device *rdev, void *buf) +{ + (void)(rdev); + (void)(buf); + return NOT_SUPOORT_TYPE; +} + +static long roce3_ioctrl_reserved_5(struct roce3_device *rdev, void *buf) +{ + (void)(rdev); + (void)(buf); + return NOT_SUPOORT_TYPE; +} + +static long roce3_ioctrl_reserved_6(struct roce3_device *rdev, void *buf) +{ + (void)(rdev); + (void)(buf); + return NOT_SUPOORT_TYPE; +} + diff --git a/drivers/infiniband/hw/hiroce3/roce_cmd.c b/drivers/infiniband/hw/hiroce3/roce_cmd.c new file mode 100755 index 000000000..13f816960 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_cmd.c @@ -0,0 +1,753 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cmd.c + * Version : v2.1 + * Created : 2021/3/14 + * Last Modified : 2021/11/26 + * Description : The definition of RoCE cmd functions to call chip MGMT functions. + */ + +#include <linux/errno.h> +#include <linux/if_ether.h> +#include <linux/moduleparam.h> + +#include "rdma_comp.h" +#include "roce_compat.h" +#include "roce_mpu_common.h" +#include "roce_cmd.h" +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +int roce3_cfg_func_tbl_er_fwd_id_compact(void *hwdev, u32 bond_tbl_val, u16 func_id) +{ + roce_bond_cfg_er_fwd_id_cmd_s cfg_er_fwd_id_comp_info; + u16 out_size = (u16)sizeof(cfg_er_fwd_id_comp_info); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&cfg_er_fwd_id_comp_info, 0, sizeof(cfg_er_fwd_id_comp_info)); + cfg_er_fwd_id_comp_info.func_id = func_id; + cfg_er_fwd_id_comp_info.bond_tbl_val = bond_tbl_val; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_BOND_ER_FWD_ID_COMPACT, &cfg_er_fwd_id_comp_info, + sizeof(cfg_er_fwd_id_comp_info), &cfg_er_fwd_id_comp_info, &out_size); + if ((ret != 0) || (out_size == 0) || (cfg_er_fwd_id_comp_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cfg func er_fwd_id(compact), err(%d), status(0x%x), out size(0x%x)\n", + __func__, ret, cfg_er_fwd_id_comp_info.head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int roce3_set_port_tbl_bond_state(void *hwdev, u8 bond_state, u16 func_id) +{ + roce_bond_cfg_state_cmd_s set_bond_state_info; + u16 out_size = (u16)sizeof(set_bond_state_info); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&set_bond_state_info, 0, sizeof(set_bond_state_info)); + set_bond_state_info.func_id = func_id; + set_bond_state_info.bond_en = bond_state; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_BOND_SET_STATE, &set_bond_state_info, sizeof(set_bond_state_info), + &set_bond_state_info, &out_size); + if ((ret != 0) || (out_size == 0) || (set_bond_state_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cfg bond state, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + set_bond_state_info.head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int roce3_add_mac_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 er_fwd_id, u16 func_id) +{ + roce_cfg_mac_cmd_s add_mac_entry_info; + u16 out_size = (u16)sizeof(add_mac_entry_info); + int ret; + + if ((hwdev == NULL) || (mac_addr == NULL)) { + pr_err("[ROCE, ERR] %s: Hwdev or mac_addr is null\n", __func__); + return -EINVAL; + } + +#ifdef ROCE_VROCE_EN + /* vroce uses vlan_id as vni the length of which is 24 bits */ + if (vlan_id > ROCE_VNI_N_VID) { + pr_err("[ROCE, ERR] %s: Invalid vlan_id(%d)\n", __func__, vlan_id); + return -EINVAL; + } +#else + if ((vlan_id & ROCE_VLAN_ID_MASK) >= ROCE_VLAN_N_VID) { + pr_err("[ROCE, ERR] %s: Invalid vlan_id(%d)\n", __func__, vlan_id); + return -EINVAL; + } +#endif + + memset(&add_mac_entry_info, 0, sizeof(add_mac_entry_info)); + +#ifdef ROCE_VROCE_EN + /* vroce uses vlan_id as vni */ + add_mac_entry_info.vni_en = 1; +#else + add_mac_entry_info.vni_en = 0; +#endif + add_mac_entry_info.func_id = func_id; + add_mac_entry_info.vlan_id = vlan_id; + add_mac_entry_info.er_fwd_id = er_fwd_id; + memcpy(add_mac_entry_info.mac, mac_addr, ETH_ALEN); + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_ADD_MAC, &add_mac_entry_info, sizeof(add_mac_entry_info), + &add_mac_entry_info, &out_size); + if ((ret != 0) || (out_size == 0) || (add_mac_entry_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to add mac entry, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + add_mac_entry_info.head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int roce3_del_mac_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 er_fwd_id, u16 func_id) +{ + roce_cfg_mac_cmd_s del_mac_tbl_info; + u16 out_size = (u16)sizeof(del_mac_tbl_info); + int ret; + + if ((hwdev == NULL) || (mac_addr == NULL)) { + pr_err("[ROCE, ERR] %s: Hwdev or mac_addr is null\n", __func__); + return -EINVAL; + } + +#ifdef ROCE_VROCE_EN + /* vroce uses vlan_id as vni the length of which is 24 bits */ + if (vlan_id > ROCE_VNI_N_VID) { + pr_err("[ROCE, ERR] %s: Invalid vlan_id(%d)\n", __func__, vlan_id); + return -EINVAL; + } +#else + if ((vlan_id & ROCE_VLAN_ID_MASK) >= ROCE_VLAN_N_VID) { + pr_err("[ROCE, ERR] %s: Invalid vlan_id(%d)\n", __func__, vlan_id); + return -EINVAL; + } +#endif + + memset(&del_mac_tbl_info, 0, sizeof(del_mac_tbl_info)); +#ifdef ROCE_VROCE_EN + /* vroce uses vlan_id as vni */ + del_mac_tbl_info.vni_en = 1; +#else + del_mac_tbl_info.vni_en = 0; +#endif + del_mac_tbl_info.func_id = func_id; + del_mac_tbl_info.vlan_id = vlan_id; + del_mac_tbl_info.er_fwd_id = er_fwd_id; + memcpy(del_mac_tbl_info.mac, mac_addr, ETH_ALEN); + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DEL_MAC, &del_mac_tbl_info, sizeof(del_mac_tbl_info), + &del_mac_tbl_info, &out_size); + if ((ret != 0) || (out_size == 0) || (del_mac_tbl_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to del mac entry, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + del_mac_tbl_info.head.status, out_size); + return -EINVAL; + } + + return 0; +} + +void roce3_add_ipsu_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 func_id, u8 er_id) +{ + roce_cfg_ipsu_mac_cmd_s ipsu_add_mac_entry_info; + u16 out_size = (u16)sizeof(ipsu_add_mac_entry_info); + int ret; + +#ifdef ROCE_BONDING_EN + if (!roce3_get_bond_ipsurx_en()) { + pr_err("[ROCE, INFO] %s: No need to add ipsu tbl mac entry \n", __func__); + return; + } +#endif + + if ((hwdev == NULL) || (mac_addr == NULL)) { + pr_err("[ROCE, ERR] %s: Hwdev or mac_addr is null\n", __func__); + return; + } + + if ((vlan_id & ROCE_VLAN_ID_MASK) >= ROCE_VLAN_N_VID) { + pr_err("[ROCE, ERR] %s: Invalid vlan_id(%d)\n", __func__, vlan_id); + } + + memset(&ipsu_add_mac_entry_info, 0, sizeof(ipsu_add_mac_entry_info)); + ipsu_add_mac_entry_info.func_id = func_id; + ipsu_add_mac_entry_info.vlanid_vni = vlan_id & ROCE_VLAN_ID_MASK; + ipsu_add_mac_entry_info.vni_en = 0; + memcpy(ipsu_add_mac_entry_info.mac, mac_addr, ETH_ALEN); + ipsu_add_mac_entry_info.er_id = er_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_ADD_IPSU_MAC, &ipsu_add_mac_entry_info, + sizeof(ipsu_add_mac_entry_info), &ipsu_add_mac_entry_info, &out_size); + if ((ret != 0) || (out_size == 0) || + ((ipsu_add_mac_entry_info.head.status != 0) && (ipsu_add_mac_entry_info.head.status != ERR_EXIST))) { + pr_err("[ROCE, ERR] %s: Failed to add mac entry to IPSU, err(%d), status(0x%x), out size(0x%x)\n", __func__, + ret, ipsu_add_mac_entry_info.head.status, out_size); + return; + } + + if (ipsu_add_mac_entry_info.head.status == ERR_EXIST) { + pr_info("[ROCE, INFO] %s: This mac entry has been added to IPSU\n", __func__); + } + + return; +} + +void roce3_del_ipsu_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 func_id, u8 er_id) +{ + roce_cfg_ipsu_mac_cmd_s ipsu_del_mac_entry_info; + u16 out_size = (u16)sizeof(ipsu_del_mac_entry_info); + int ret; + + if ((hwdev == NULL) || (mac_addr == NULL)) { + pr_err("[ROCE, ERR] %s: Hwdev or mac_addr is null\n", __func__); + return; + } + +#ifdef ROCE_BONDING_EN + if (!roce3_get_bond_ipsurx_en()) { + pr_err("[ROCE, INFO] %s: No need to del ipsu tbl mac entry \n", __func__); + return; + } +#endif + + if ((vlan_id & ROCE_VLAN_ID_MASK) >= ROCE_VLAN_N_VID) { + pr_err("[ROCE, ERR] %s: Invalid vlan_id(%d)\n", __func__, vlan_id); + return; + } + + memset(&ipsu_del_mac_entry_info, 0, sizeof(ipsu_del_mac_entry_info)); + ipsu_del_mac_entry_info.func_id = func_id; + ipsu_del_mac_entry_info.vlanid_vni = vlan_id & ROCE_VLAN_ID_MASK; + ipsu_del_mac_entry_info.vni_en = 0; + memcpy(ipsu_del_mac_entry_info.mac, mac_addr, ETH_ALEN); + ipsu_del_mac_entry_info.er_id = er_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DEL_IPSU_MAC, &ipsu_del_mac_entry_info, + sizeof(ipsu_del_mac_entry_info), &ipsu_del_mac_entry_info, &out_size); + if ((ret != 0) || (out_size == 0) || + ((ipsu_del_mac_entry_info.head.status != 0) && (ipsu_del_mac_entry_info.head.status != ERR_NOT_FOUND))) { + pr_err("[ROCE, ERR] %s: Failed to del mac entry, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + ipsu_del_mac_entry_info.head.status, out_size); + return; + } + + if (ipsu_del_mac_entry_info.head.status == ERR_NOT_FOUND) { + pr_info("[ROCE, INFO] %s: This mac entry of ipsu has been deleted\n", __func__); + } + + return; +} + +int roce3_do_cache_out(void *hwdev, u8 cl_id, u16 func_id) +{ + roce_dfx_cache_out_cmd_s cache_out_info; + u16 out_size = (u16)sizeof(cache_out_info); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&cache_out_info, 0, sizeof(cache_out_info)); + cache_out_info.func_idx = func_id; + cache_out_info.cache_index = cl_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DFX_CACHE_OUT, &cache_out_info, sizeof(cache_out_info), + &cache_out_info, &out_size); + if ((ret != 0) || (out_size == 0) || (cache_out_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cache out, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + cache_out_info.head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int roce3_set_cfg_ccf_param(void *hwdev, u16 func_id, u32 *ccf_param) +{ + roce_cc_cfg_param_cmd_s cfg_ccf_param; + u16 out_size = (u16)sizeof(cfg_ccf_param); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&cfg_ccf_param, 0, sizeof(cfg_ccf_param)); + cfg_ccf_param.func_id = func_id; + cfg_ccf_param.param[0] = ccf_param[0]; // 0 is param array idx + cfg_ccf_param.param[1] = ccf_param[1]; // 1 is param array idx + cfg_ccf_param.param[2] = ccf_param[2]; // 2 is param array idx + cfg_ccf_param.param[3] = ccf_param[3]; // 3 is param array idx + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_CC_CFG_CCF_PARAM, &cfg_ccf_param, sizeof(cfg_ccf_param), + &cfg_ccf_param, &out_size); + if ((ret != 0) || (out_size == 0) || (cfg_ccf_param.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cfg ccf param, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + cfg_ccf_param.head.status, out_size); + + return -EINVAL; + } + + return 0; +} + +int roce3_set_cfg_dcqcn_param(void *hwdev, u16 func_id, u32 *dcqcn_param) +{ + roce_cc_cfg_param_cmd_s cfg_dcqcn_param; + u16 out_size = (u16)sizeof(cfg_dcqcn_param); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&cfg_dcqcn_param, 0, sizeof(cfg_dcqcn_param)); + cfg_dcqcn_param.func_id = func_id; + cfg_dcqcn_param.param[0] = dcqcn_param[0]; // 0 is param array idx + cfg_dcqcn_param.param[1] = dcqcn_param[1]; // 1 is param array idx + cfg_dcqcn_param.param[2] = dcqcn_param[2]; // 2 is param array idx + cfg_dcqcn_param.param[3] = dcqcn_param[3]; // 3 is param array idx + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_CC_CFG_DCQCN_PARAM, &cfg_dcqcn_param, sizeof(cfg_dcqcn_param), + &cfg_dcqcn_param, &out_size); + if ((ret != 0) || (out_size == 0) || (cfg_dcqcn_param.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cfg dcqcn param, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + cfg_dcqcn_param.head.status, out_size); + + return -EINVAL; + } + + return 0; +} + +int roce3_set_cfg_ipqcn_param(void *hwdev, u16 func_id, u32 *ipqcn_param) +{ + roce_cc_cfg_param_cmd_s cfg_ipqcn_param; + u16 out_size = (u16)sizeof(cfg_ipqcn_param); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&cfg_ipqcn_param, 0, sizeof(cfg_ipqcn_param)); + cfg_ipqcn_param.func_id = func_id; + cfg_ipqcn_param.param[0] = ipqcn_param[0]; // 0 is param array idx + cfg_ipqcn_param.param[1] = ipqcn_param[1]; // 1 is param array idx + cfg_ipqcn_param.param[2] = ipqcn_param[2]; // 2 is param array idx + cfg_ipqcn_param.param[3] = ipqcn_param[3]; // 3 is param array idx + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_CC_CFG_IPQCN_PARAM, &cfg_ipqcn_param, sizeof(cfg_ipqcn_param), + &cfg_ipqcn_param, &out_size); + if ((ret != 0) || (out_size == 0) || (cfg_ipqcn_param.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cfg ipqcn param, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + cfg_ipqcn_param.head.status, out_size); + + return -EINVAL; + } + + return 0; +} + +int roce3_set_cfg_ldcp_param(void *hwdev, u16 func_id, u32 *ldcp_param) +{ + roce_cc_cfg_param_cmd_s cfg_ldcp_param; + u16 out_size = (u16)sizeof(cfg_ldcp_param); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&cfg_ldcp_param, 0, sizeof(cfg_ldcp_param)); + cfg_ldcp_param.func_id = func_id; + cfg_ldcp_param.param[0] = ldcp_param[0]; // 0 is param array idx + cfg_ldcp_param.param[1] = ldcp_param[1]; // 1 is param array idx + cfg_ldcp_param.param[2] = ldcp_param[2]; // 2 is param array idx + cfg_ldcp_param.param[3] = ldcp_param[3]; // 3 is param array idx + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_CC_CFG_LDCP_PARAM, &cfg_ldcp_param, sizeof(cfg_ldcp_param), + &cfg_ldcp_param, &out_size); + if ((ret != 0) || (out_size == 0) || (cfg_ldcp_param.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to cfg ldcp param, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + cfg_ldcp_param.head.status, out_size); + + return -EINVAL; + } + + return 0; +} + +int roce3_set_cap_cfg(void *hwdev, u16 index, u32 *cap_cfg) +{ + roce_dfx_cfg_cap_param_cmd_s set_cap_cfg; + u16 out_size = (u16)sizeof(set_cap_cfg); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&set_cap_cfg, 0, sizeof(set_cap_cfg)); + set_cap_cfg.index = index; + set_cap_cfg.param[0] = cap_cfg[0]; // 0 is param array idx + set_cap_cfg.param[1] = cap_cfg[1]; // 1 is param array idx + set_cap_cfg.param[2] = cap_cfg[2]; // 2 is param array idx + set_cap_cfg.param[3] = cap_cfg[3]; // 3 is param array idx + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DFX_SET_CAP_CFG, &set_cap_cfg, sizeof(set_cap_cfg), &set_cap_cfg, + &out_size); + if ((ret != 0) || (out_size == 0) || (set_cap_cfg.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to set cap cfg, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + set_cap_cfg.head.status, out_size); + + return -EINVAL; + } + + return 0; +} + +int roce3_get_cap_cfg(void *hwdev, u16 index, u32 *cap_cfg) +{ + roce_dfx_cfg_cap_param_cmd_s get_cap_cfg; + u16 out_size = (u16)sizeof(get_cap_cfg); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&get_cap_cfg, 0, sizeof(get_cap_cfg)); + get_cap_cfg.index = index; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DFX_GET_CAP_CFG, &get_cap_cfg, sizeof(get_cap_cfg), &get_cap_cfg, + &out_size); + if ((ret != 0) || (out_size == 0) || (get_cap_cfg.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to get cap cfg, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + get_cap_cfg.head.status, out_size); + + return -EINVAL; + } + + memcpy(cap_cfg, get_cap_cfg.param, sizeof(get_cap_cfg.param)); + + return 0; +} + +int roce3_clear_cap_counter(void *hwdev, u16 index, u32 *value) +{ + roce_dfx_cap_ctr_cmd_s clear_cap_counter; + u16 out_size = (u16)sizeof(clear_cap_counter); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&clear_cap_counter, 0, sizeof(clear_cap_counter)); + clear_cap_counter.index = index; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DFX_CLEAR_CAP_CTR, &clear_cap_counter, sizeof(clear_cap_counter), + &clear_cap_counter, &out_size); + if ((ret != 0) || (out_size == 0) || (clear_cap_counter.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to clear cap counter, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + clear_cap_counter.head.status, out_size); + + return -EINVAL; + } + + *value = clear_cap_counter.value; + + return 0; +} + +int roce3_read_cap_counter(void *hwdev, u16 index, u32 *value) +{ + roce_dfx_cap_ctr_cmd_s read_cap_counter; + u16 out_size = (u16)sizeof(read_cap_counter); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&read_cap_counter, 0, sizeof(read_cap_counter)); + read_cap_counter.index = index; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_DFX_READ_CAP_CTR, &read_cap_counter, sizeof(read_cap_counter), + &read_cap_counter, &out_size); + if ((ret != 0) || (out_size == 0) || (read_cap_counter.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to read cap counter, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + read_cap_counter.head.status, out_size); + + return -EINVAL; + } + + *value = read_cap_counter.value; + + return 0; +} + +int roce3_set_func_tbl_func_state(struct roce3_device *rdev, u8 func_state) +{ + void *hwdev = rdev->hwdev; + u16 func_id = rdev->glb_func_id; + roce_set_func_state_cmd_s set_func_state_info; + u16 out_size = (u16)sizeof(set_func_state_info); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return (-EINVAL); + } + + memset(&set_func_state_info, 0, sizeof(set_func_state_info)); + set_func_state_info.func_id = func_id; + set_func_state_info.func_en = func_state; + set_func_state_info.tag = 0; +#ifdef ROCE_VROCE_EN + if (rdev->is_vroce) { + set_func_state_info.tag = 1; + } +#endif + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_SET_FUNC_STATE, &set_func_state_info, sizeof(set_func_state_info), + &set_func_state_info, &out_size); + if ((ret != 0) || (out_size == 0) || (set_func_state_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to set func state(%d), err(%d), status(0x%x), out size(0x%x), func_id(%d)\n", + __func__, func_state, ret, set_func_state_info.head.status, out_size, func_id); + return (-EINVAL); + } + + return 0; +} + +int roce3_get_func_table(void *hwdev, u16 func_id, u32 *func_tbl_value) +{ + roce_get_func_table_cmd_s get_func_table; + roce_get_func_table_rsp_s get_func_table_rsp; + u16 out_size = (u16)sizeof(get_func_table_rsp); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return (-EINVAL); + } + + memset(&get_func_table, 0, sizeof(get_func_table)); + memset(&get_func_table_rsp, 0, out_size); + get_func_table.func_id = func_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_GET_FUNC_TABLE, &get_func_table, sizeof(get_func_table), + &get_func_table_rsp, &out_size); + if ((ret != 0) || (out_size == 0) || (get_func_table_rsp.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to get func table, err(%d), status(0x%x), out size(0x%x), func_id(%d)\n", + __func__, ret, get_func_table_rsp.head.status, out_size, func_id); + return (-EINVAL); + } + + *func_tbl_value = get_func_table_rsp.func_tbl_value; + + return 0; +} + +int roce3_set_func_tbl_cpu_endian(void *hwdev, u8 cpu_endian, u16 func_id) +{ + roce_set_cpu_endian_cmd_s set_cpu_endian_info; + u16 out_size = (u16)sizeof(set_cpu_endian_info); + int ret; + + if (hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return -EINVAL; + } + + memset(&set_cpu_endian_info, 0, sizeof(set_cpu_endian_info)); + set_cpu_endian_info.func_id = func_id; + set_cpu_endian_info.cpu_endian = cpu_endian; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_SET_CPU_ENDIAN, &set_cpu_endian_info, sizeof(set_cpu_endian_info), + &set_cpu_endian_info, &out_size); + if ((ret != 0) || (out_size == 0) || (set_cpu_endian_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to set func state, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + set_cpu_endian_info.head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int roce3_init_cfg_info(struct roce3_device *rdev) +{ + roce_get_cfg_info_cmd_s get_cfg_info; + roce_get_cfg_info_resp_s resp; + u16 out_size = (u16)sizeof(resp); + int ret = 0; + + if (rdev->hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return (-EINVAL); + } + + memset(&get_cfg_info, 0, sizeof(get_cfg_info)); + memset(&resp, 0, sizeof(resp)); + + get_cfg_info.func_id = rdev->glb_func_id; + + ret = roce3_msg_to_mgmt_sync(rdev->hwdev, ROCE_MPU_CMD_GET_CFG_INFO, &get_cfg_info, sizeof(get_cfg_info), &resp, + &out_size); + if ((ret != 0) || (out_size == 0) || (get_cfg_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to roce3_init_cfg_info, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + get_cfg_info.head.status, out_size); + return (-EINVAL); + } + + rdev->cfg_info.scence_id = resp.scence_id; + rdev->cfg_info.lb_en = resp.lb_en; + rdev->cfg_info.lb_mode = resp.lb_mode; + rdev->cfg_info.srq_container_en = (resp.container_mode != ROCE_CHIP_SRQ_MODE_N); + rdev->cfg_info.srq_container_mode = roce3_srq_mode_chip_adapt(resp.container_mode); + rdev->cfg_info.xrc_srq_container_mode = ROCE_SRQ_MODE_3; + rdev->cfg_info.warn_th = 0; + + rdev->cfg_info.fake_en = resp.fake_en; + rdev->cfg_info.pf_start_bit = resp.pf_start_bit; + rdev->cfg_info.pf_end_bit = resp.pf_end_bit; + rdev->cfg_info.page_bit = resp.page_bit; + + rdev->cfg_info.port_num = resp.port_num; + rdev->cfg_info.host_num = resp.host_num; + rdev->cfg_info.master_func = (u8)(resp.port_num * resp.host_num); + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: RoCE init,func_id(%d),lb_en(%d),lb_mode(%d),srq_mode(%d),aa_en(%d)\n", + __func__, rdev->glb_func_id, rdev->cfg_info.lb_en, rdev->cfg_info.lb_mode, rdev->cfg_info.srq_container_mode, + rdev->cfg_info.scence_id); + return 0; +} + +int roce3_get_group_id(u16 func_id, void *hwdev, struct roce_group_id *group_id) +{ + struct roce_cmd_get_group_id group_id_info; + u16 out_size = (u16)sizeof(group_id_info); + int ret; + + if (hwdev == NULL) { + (void)pr_err("[ROCE] %s(%d): Hwdev is null\n", __func__, __LINE__); + return -EINVAL; + } + + /* 组命令并下发给uP */ + memset(&group_id_info, 0, sizeof(group_id_info)); + group_id_info.func_id = func_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_GET_GROUP_ID, + &group_id_info, sizeof(group_id_info), &group_id_info, &out_size); + if (!!ret || (!out_size) || !!group_id_info.status) { + (void)pr_err("[ROCE] %s(%d): Failed to get group id, ret(%d), status(%u), out size(0x%hx)\n", + __func__, __LINE__, ret, group_id_info.status, out_size); + return -EINVAL; + } + + group_id->group_rc_cos = group_id_info.group_rc_cos; + group_id->group_ud_cos = group_id_info.group_ud_cos; + group_id->group_xrc_cos = group_id_info.group_xrc_cos; + + return 0; +} + +int roce3_del_func_res(struct roce3_device *rdev) +{ + roce_set_func_state_cmd_s del_func_res_info; + u16 out_size = (u16)sizeof(del_func_res_info); + int ret; + + if ((rdev == NULL) || (rdev->hwdev == NULL)) { + pr_err("[ROCE, ERR] %s: rdev/Hwdev is null\n", __func__); + return (-EINVAL); + } + + memset(&del_func_res_info, 0, sizeof(del_func_res_info)); + del_func_res_info.func_id = rdev->glb_func_id; + ret = roce3_msg_to_mgmt_sync(rdev->hwdev, ROCE_MPU_CMD_DEL_FUNC_RES, &del_func_res_info, sizeof(del_func_res_info), + &del_func_res_info, &out_size); + if ((ret != 0) || (out_size == 0) || (del_func_res_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to set func state, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + del_func_res_info.head.status, out_size); + return (-EINVAL); + } + + return 0; +} + +int roce3_set_bw_ctrl_state(struct roce3_device *rdev, u8 cmd, struct roce3_bw_ctrl_inbuf *inbuf) +{ + int ret = 0; + roce_cc_cfg_bw_ctrl_cmd_s set_bw_ctrl; + u16 out_size = (u16)sizeof(set_bw_ctrl); + + if (rdev->hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return (-EINVAL); + } + + memset(&set_bw_ctrl, 0, sizeof(set_bw_ctrl)); + + set_bw_ctrl.func_id = rdev->glb_func_id; + set_bw_ctrl.cmd = cmd; + set_bw_ctrl.cir = inbuf->ctrl_param.cir; + set_bw_ctrl.pir = inbuf->ctrl_param.pir; + set_bw_ctrl.cnp = inbuf->ctrl_param.cnp; + pr_info("[ROCE, DEBUG] %s: func_id:%u, cmd:%u, cir:%u, pir:%u, cnp:%u\n", __func__, rdev->glb_func_id, + set_bw_ctrl.cmd, set_bw_ctrl.cir, set_bw_ctrl.pir, set_bw_ctrl.cnp); + ret = roce3_msg_to_mgmt_sync(rdev->hwdev, ROCE_MPU_CMD_CC_SET_BW_CTRL, &set_bw_ctrl, sizeof(set_bw_ctrl), + &set_bw_ctrl, &out_size); + if ((ret != 0) || (out_size == 0) || (set_bw_ctrl.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to set set_bw_ctrl cmd, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + set_bw_ctrl.head.status, out_size); + return (-EINVAL); + } + + return 0; +} + +int roce3_query_bw_ctrl_state(struct roce3_device *rdev, struct roce3_bw_ctrl_param *bw_ctrl_param) +{ + int ret = 0; + roce_cc_cfg_bw_ctrl_cmd_s query_bw_ctrl; + u16 out_size = (u16)sizeof(query_bw_ctrl); + + if (rdev->hwdev == NULL) { + pr_err("[ROCE, ERR] %s: Hwdev is null\n", __func__); + return (-EINVAL); + } + + memset(&query_bw_ctrl, 0, sizeof(query_bw_ctrl)); + + query_bw_ctrl.func_id = rdev->glb_func_id; + ret = roce3_msg_to_mgmt_sync(rdev->hwdev, ROCE_MPU_CMD_CC_QUERY_BW_CTRL, &query_bw_ctrl, sizeof(query_bw_ctrl), + &query_bw_ctrl, &out_size); + if ((ret != 0) || (out_size == 0) || (query_bw_ctrl.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to set query_bw_ctrl cmd, err(%d), status(0x%x), out size(0x%x)\n", __func__, + ret, query_bw_ctrl.head.status, out_size); + return (-EINVAL); + } + + memcpy((void *)bw_ctrl_param, + (void *)((u8 *)(&query_bw_ctrl) + ROCE_CMD_DEFAULT_SIZE), sizeof(struct roce3_bw_ctrl_param)); + + pr_info("[ROCE, DEBUG] %s: query_bw_ctrl_state:func_id:%u, cir:%u, pir:%u, cnp:%u\n", __func__, rdev->glb_func_id, + bw_ctrl_param->cir, bw_ctrl_param->pir, bw_ctrl_param->cnp); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/roce_cmd.h b/drivers/infiniband/hw/hiroce3/roce_cmd.h new file mode 100755 index 000000000..a564abc80 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_cmd.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cmd.h + * Version : v2.0 + * Created : 2021/3/14 + * Last Modified : 2021/11/2 + * Description : The definition of RoCE cmd function prototypes, macros etc. + */ + +#ifndef ROCE_CMD_H +#define ROCE_CMD_H + +#include "roce.h" +#include "roce_dfx.h" +#include "roce_srq.h" + +#define ROCE_VLAN_ID_MASK 0x7FFF +#define ROCE_VLAN_N_VID 4096 +#define ROCE_VNI_N_VID 0xFFFFFF +#define ROCE_CMD_DEFAULT_SIZE 12 + +#define ERR_EXIST 6 +#define ERR_NOT_FOUND 13 +struct roce_cmd_get_group_id { + u8 status; + u8 version; + u8 rsvd0[6]; + + u16 func_id; + u8 group_rc_cos; + u8 group_ud_cos; + u8 group_xrc_cos; +}; + +struct roce_group_id { + u8 group_rc_cos; + u8 group_ud_cos; + u8 group_xrc_cos; + u8 rsvd; +}; + +#define roce3_msg_to_mgmt_sync(hwdev, cmd, buf_in, in_size, buf_out, out_size) \ + hinic3_msg_to_mgmt_sync(hwdev, HINIC3_MOD_ROCE, cmd, buf_in, in_size, buf_out, out_size, 0, HINIC3_CHANNEL_ROCE) + +int roce3_cfg_func_tbl_er_fwd_id_compact(void *hwdev, u32 bond_tbl_val, u16 func_id); + +int roce3_set_port_tbl_bond_state(void *hwdev, u8 bond_state, u16 func_id); + +int roce3_add_mac_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 er_fwd_id, u16 func_id); +int roce3_del_mac_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 er_fwd_id, u16 func_id); +typedef int (*roce3_modify_mac_tbl)(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 er_fwd_id, u16 func_id); +void roce3_add_ipsu_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 func_id, u8 er_id); +void roce3_del_ipsu_tbl_mac_entry(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 func_id, u8 er_id); +typedef void (*roce3_modify_ipsu_tbl_mac)(void *hwdev, u8 *mac_addr, u32 vlan_id, u16 func_id, u8 er_id); + +int roce3_do_cache_out(void *hwdev, u8 cl_id, u16 func_id); + +int roce3_set_cfg_ccf_param(void *hwdev, u16 func_id, u32 *ccf_param); +int roce3_set_cfg_ipqcn_param(void *hwdev, u16 func_id, u32 *ipqcn_param); +int roce3_set_cfg_ldcp_param(void *hwdev, u16 func_id, u32 *ldcp_param); +int roce3_set_cfg_dcqcn_param(void *hwdev, u16 func_id, u32 *dcqcn_param); +int roce3_set_bw_ctrl_state(struct roce3_device *rdev, u8 cmd, struct roce3_bw_ctrl_inbuf *inbuf); +int roce3_query_bw_ctrl_state(struct roce3_device *rdev, struct roce3_bw_ctrl_param *bw_ctrl_param); + +int roce3_set_cap_cfg(void *hwdev, u16 index, u32 *cap_cfg); +int roce3_get_cap_cfg(void *hwdev, u16 index, u32 *cap_cfg); +int roce3_clear_cap_counter(void *hwdev, u16 index, u32 *value); +int roce3_read_cap_counter(void *hwdev, u16 index, u32 *value); + +int roce3_set_func_tbl_func_state(struct roce3_device *rdev, u8 func_state); +int roce3_get_func_table(void *hwdev, u16 func_id, u32 *func_tbl_value); +int roce3_set_func_tbl_cpu_endian(void *hwdev, u8 cpu_endian, u16 func_id); +int roce3_init_cfg_info(struct roce3_device *rdev); +int roce3_del_func_res(struct roce3_device *rdev); +int roce3_get_group_id(u16 func_id, void *hwdev, struct roce_group_id *group_id); + +#endif /* ROCE_CMD_H */ diff --git a/drivers/infiniband/hw/hiroce3/roce_compat.h b/drivers/infiniband/hw/hiroce3/roce_compat.h new file mode 100644 index 000000000..4fe3e9ffa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_compat.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_compat.h + * Version : v2.0 + * Created : 2021/3/14 + * Last Modified : 2021/11/2 + * Description : The definition of RoCE common macros. + */ + +#ifndef ROCE_COMPAT_H +#define ROCE_COMPAT_H + +#include <linux/delay.h> + +#define ROCE_LIKELY(x) /*lint -e730*/ likely(x) /*lint +e730*/ + +#define ROCE_UNLIKELY(x) /*lint -e730*/ unlikely(x) /*lint +e730*/ + +#define ROCE_ILOG2(n) /*lint -e866*/ ilog2(n) /*lint +e866*/ + +#define ROCE_ROUNDUP_POW_OF_TWO(n) /*lint -e866*/ roundup_pow_of_two(n) /*lint +e866*/ + +#ifndef _lint +/*lint -e506 -e160 -e522*/ +#define ROCE_MDELAY(n) mdelay(n) +#define ROCE_UDELAY(n) udelay(n) +/*lint +e506 +e160 +e522*/ +#else +#define ROCE_MDELAY(n) ((void)n) +#define ROCE_UDELAY(n) ((void)n) +#endif + +#define ROCE_ALIGN(a, b) ALIGN(a, b) +#define ROCE_MAX(a, b) max(a, b) +#define ROCE_MIN(a, b) min(a, b) +#define ROCE_DIV_ROUND_UP(a, b) DIV_ROUND_UP(a, b) +#define ROCE_FLS(n) fls(n) + +#define ROCE_MEMCMP(a, b, count) memcmp(a, b, count) +#define ROCE_IO_MAPPING_MAP_WC(mapping, offset) io_mapping_map_wc(mapping, offset) +#define ROCE_IOREMAP(phys_addr, size) ioremap(phys_addr, size) +#define ROCE_IOUNMAP(addr) iounmap(addr) +#define ROCE_IO_MAPPING_UNMAP(vaddr) io_mapping_unmap(vaddr) + +#ifndef wc_wmb + +#if defined(__i386__) +#define wc_wmb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory") +#elif defined(__x86_64__) +#define wc_wmb() asm volatile("sfence" ::: "memory") +#elif defined(__ia64__) +#define wc_wmb() asm volatile("fwb" ::: "memory") +#else +#define wc_wmb() wmb() +#endif + +#endif + +#endif // ROCE_COMPAT_H diff --git a/drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c b/drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c new file mode 100644 index 000000000..ce6f4dca2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cpm_cmd.c + * Created : 2021/3/10 + * Description : implement of roce cqm cmd management + */ + +#include "roce_cqm_cmd.h" + +void roce3_cqm_cmd_free_inoutbuf(void *ex_handle, cqm_cmd_buf_s *cqm_cmd_inbuf, cqm_cmd_buf_s *cqm_cmd_outbuf) +{ + if (cqm_cmd_outbuf != NULL) { + cqm_cmd_free(ex_handle, cqm_cmd_outbuf); + } + + if (cqm_cmd_inbuf != NULL) { + cqm_cmd_free(ex_handle, cqm_cmd_inbuf); + } +} + +int roce3_cqm_cmd_zalloc_inoutbuf(void *ex_handle, cqm_cmd_buf_s **cqm_cmd_inbuf, u16 inbuf_size, + cqm_cmd_buf_s **cqm_cmd_outbuf, u16 outbuf_size) +{ + int ret; + + if (cqm_cmd_inbuf != NULL) { + *cqm_cmd_inbuf = cqm_cmd_alloc(ex_handle); + + if (*cqm_cmd_inbuf == NULL) { + ret = -ENOMEM; + goto err; + } + (*cqm_cmd_inbuf)->size = inbuf_size; + + memset((*cqm_cmd_inbuf)->buf, 0, inbuf_size); + } + + if (cqm_cmd_outbuf != NULL) { + *cqm_cmd_outbuf = cqm_cmd_alloc(ex_handle); + + if (*cqm_cmd_outbuf == NULL) { + ret = -ENOMEM; + goto err; + } + (*cqm_cmd_outbuf)->size = outbuf_size; + + memset((*cqm_cmd_outbuf)->buf, 0, outbuf_size); + } + + return 0; +err: + roce3_cqm_cmd_free_inoutbuf(ex_handle, *cqm_cmd_inbuf, *cqm_cmd_outbuf); + *cqm_cmd_inbuf = NULL; + *cqm_cmd_outbuf = NULL; + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h b/drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h new file mode 100644 index 000000000..d9239cf17 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cpm_cmd.h + * Created : 2021/3/10 + * Description : The definition of roce cqm cmd management + */ + +#ifndef ROCE_CQM_CMD_H +#define ROCE_CQM_CMD_H + +#include "hinic3_cqm.h" + +#include "roce.h" + +void roce3_cqm_cmd_free_inoutbuf(void *ex_handle, cqm_cmd_buf_s *cqm_cmd_inbuf, cqm_cmd_buf_s *cqm_cmd_outbuf); +int roce3_cqm_cmd_zalloc_inoutbuf(void *ex_handle, cqm_cmd_buf_s **cqm_cmd_inbuf, u16 inbuf_size, + cqm_cmd_buf_s **cqm_cmd_outbuf, u16 outbuf_size); + +#endif // ROCE_CQM_CMD_H diff --git a/drivers/infiniband/hw/hiroce3/roce_db.c b/drivers/infiniband/hw/hiroce3/roce_db.c new file mode 100755 index 000000000..856ebb300 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_db.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_db.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of functions for RoCE DB. + */ + +#include <linux/kernel.h> + +#include "roce.h" + +/* **************************************************************************** + Prototype : roce3_db_map_user + Description : roce3_db_map_user + Input : struct roce3_ucontext *context + unsigned long virt + struct roce3_db *db + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +int roce3_db_map_user(struct roce3_ucontext *context, unsigned long virt, struct roce3_db *db) +{ + int ret = 0; + struct roce3_db_page *db_page = NULL; +#if defined(OFED_MLNX_5_8) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + struct ib_ucontext *ibucontext = &context->ibucontext; + struct uverbs_attr_bundle *attrs = container_of(&ibucontext, struct uverbs_attr_bundle, context); +#endif + + mutex_lock(&context->db_page_mutex); + + list_for_each_entry(db_page, &context->db_page_list, list) + { + if (db_page->user_virt == (virt & PAGE_MASK)) { + goto found; + } + } + + db_page = (struct roce3_db_page *)kmalloc(sizeof(*db_page), GFP_KERNEL); + if (db_page == NULL) { + ret = -ENOMEM; + pr_err("[ROCE, ERR] %s: Failed to alloc DB page\n", __func__); + goto out; + } + + db_page->user_virt = (virt & PAGE_MASK); + db_page->refcnt = 0; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + db_page->umem = ib_umem_get(context->ibucontext.device, virt & PAGE_MASK, PAGE_SIZE, 0); +#elif defined(OFED_MLNX_5_8) + db_page->umem = ib_umem_get(&attrs->driver_udata, virt & PAGE_MASK, PAGE_SIZE, 0); +#else + db_page->umem = ib_umem_get(&context->ibucontext, virt & PAGE_MASK, PAGE_SIZE, 0, 0); +#endif + if (IS_ERR(db_page->umem)) { + ret = (int)PTR_ERR(db_page->umem); + pr_err("[ROCE, ERR] %s: Failed to get ib_umem ret:%d\n", __func__, ret); + kfree(db_page); + goto out; + } + + list_add(&db_page->list, &context->db_page_list); + +found: + db->dma = sg_dma_address(db_page->umem->sgt_append.sgt.sgl) + (virt & ~PAGE_MASK); + db->user_page = db_page; + ++db_page->refcnt; + +out: + mutex_unlock(&context->db_page_mutex); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_db_unmap_user + Description : roce3_db_unmap_user + Input : struct roce3_ucontext *context + struct roce3_db *db + Output : None + + 1.Date : 2015/4/29 + Modification : Created function + +**************************************************************************** */ +void roce3_db_unmap_user(struct roce3_ucontext *context, struct roce3_db *db) +{ + mutex_lock(&context->db_page_mutex); + + if ((--db->user_page->refcnt) == 0) { + list_del(&db->user_page->list); + ib_umem_release(db->user_page->umem); + kfree(db->user_page); + } + + mutex_unlock(&context->db_page_mutex); +} diff --git a/drivers/infiniband/hw/hiroce3/roce_db.h b/drivers/infiniband/hw/hiroce3/roce_db.h new file mode 100644 index 000000000..88dec7dea --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_db.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_db.h + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of struct for RoCE DB. + */ + +#ifndef ROCE_DB_H +#define ROCE_DB_H + +#include <rdma/ib_umem.h> +#include <linux/types.h> +#include <linux/list.h> + +struct roce3_db_page { + struct list_head list; + struct ib_umem *umem; + unsigned long user_virt; + int refcnt; +}; + +struct roce3_db { + __be32 *db_record; + dma_addr_t dma; + struct roce3_db_page *user_page; +}; + +static inline void roce3_write64(u32 val[2], void __iomem *dest) +{ + __raw_writeq(*(u64 *)(void *)val, dest); +} + +#endif // ROCE_DB_H diff --git a/drivers/infiniband/hw/hiroce3/roce_event.c b/drivers/infiniband/hw/hiroce3/roce_event.c new file mode 100644 index 000000000..500ac564a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_event.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_event.c + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : The definition of RoCE Async Event realated functions in kernel space. + */ + +#include "roce_event.h" +#include "roce_event_extension.h" +#include "roce_pub_cmd.h" +#include "hinic3_mt.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +static void roce3_event_report_common_a(const struct roce3_device *rdev, int event_str_index) +{ + switch (event_str_index) { + case OFED_ET_PATH_MIG: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Path mig. function id: %hu \n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_COMM_EST: + /*lint -e160 -e522*/ + roce3_pr_err_once("[ROCE] %s: [ofed event type] Communication establish. function id: %hu\n", __func__, + rdev->glb_func_id); + /*lint +e160 +e522*/ + break; + + case OFED_ET_SQ_DRAINED: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Sq drained. function id: %hu\n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_SRQ_QP_LAST_WQE: + /*lint -e160 -e522*/ + roce3_pr_err_once("[ROCE] %s: [ofed event type] Srq/qp last wqe. function id: %hu\n", __func__, + rdev->glb_func_id); + /*lint +e160 +e522*/ + break; + + case OFED_ET_WQ_CATAS_ERR: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Wq catas error. function id: %hu\n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_PATH_MIG_FAILED: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Path mig failed. function id: %u\n", __func__, + rdev->glb_func_id); + break; + default: + break; + } +} + +static void roce3_event_report_common_b(const struct roce3_device *rdev, int event_str_index) +{ + switch (event_str_index) { + case OFED_ET_WQ_INVAL_REQ_ERR: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Wq inval req error. function id: %u\n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_WQ_ACCESS_ERR: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Wq access error. function id: %u \n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_CQ_ERR: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Cq error. function id: %u \n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_SRQ_LIMIT: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Srq limit. function id: %u \n", __func__, + rdev->glb_func_id); + break; + + case OFED_ET_SRQ_CATAS_ERR: + pr_err_ratelimited("[ROCE] %s: [ofed event type] Srq catas error. function id: %u\n", __func__, + rdev->glb_func_id); + break; + + case NON_OFED_ET_QPC_LOOKUP_ERR: + pr_err_ratelimited("[ROCE] %s: [non ofed event type] Qpc lookup error. function id: %u\n", __func__, + rdev->glb_func_id); + break; + + case NON_OFED_ET_OTHER_TYPE_ERR: + /*lint -e160 -e522*/ + roce3_pr_err_once("[ROCE] %s: [non ofed event type] other type error. function id: %u\n", __func__, + rdev->glb_func_id); + /*lint +e160 +e522*/ + break; + default: + break; + } +} + +static void roce3_event_report_common(const struct roce3_device *rdev, int event_str_index) +{ + if (event_str_index <= OFED_ET_PATH_MIG_FAILED) { + roce3_event_report_common_a(rdev, event_str_index); + } else { + roce3_event_report_common_b(rdev, event_str_index); + } +} + +/* **************************************************************************** + Prototype : roce3_event_report + Description : roce3_event_report + Input : struct roce3_device *rdev + int event_str_index + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static void roce3_event_report(struct roce3_device *rdev, int event_str_index) +{ + if (event_str_index <= NON_OFED_ET_OTHER_TYPE_ERR) { + roce3_event_report_common(rdev, event_str_index); + } else { + roce3_event_report_extend(rdev, event_str_index); + } +} + +/* **************************************************************************** + Prototype : to_qp_event_str_index + Description : to_qp_event_str_index + Input : u8 event_type + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int to_qp_event_str_index(u8 event_type) +{ + switch (event_type) { + case ROCE_EVENT_TYPE_PATH_MIG: + return OFED_ET_PATH_MIG; + + case ROCE_EVENT_TYPE_COMM_EST: + return OFED_ET_COMM_EST; + + case ROCE_EVENT_TYPE_SQ_DRAINED: + return OFED_ET_SQ_DRAINED; + + case ROCE_EVENT_TYPE_SRQ_QP_LAST_WQE: + return OFED_ET_SRQ_QP_LAST_WQE; + + case ROCE_EVENT_TYPE_WQ_CATAS_ERROR: + return OFED_ET_WQ_CATAS_ERR; + + case ROCE_EVENT_TYPE_PATH_MIG_FAILED: + return OFED_ET_PATH_MIG_FAILED; + + case ROCE_EVENT_TYPE_WQ_INVAL_REQ_ERROR: + return OFED_ET_WQ_INVAL_REQ_ERR; + + default: + return OFED_ET_WQ_ACCESS_ERR; + } +} + +int to_unkown_event_str_index(u8 event_type, const u8 *val) +{ + switch (event_type) { + case ROCE_EVENT_TYPE_OFED_NO_DEF: + if (*((u64 *)val) == QPC_LOOKUP_ERR_VALUE) { + return NON_OFED_ET_QPC_LOOKUP_ERR; + } + return NON_OFED_ET_OTHER_TYPE_ERR; + + case ROCE_EVENT_TYPE_LOCAL_CATAS_ERROR: + return NON_OFED_ET_OTHER_TYPE_ERR; + + default: + return INVAL_ET_ERR; + } +} + +/* **************************************************************************** + Prototype : roce3_handle_qp_async_event + Description : roce3_handle_qp_async_event + Input : struct roce3_device *rdev + u32 qpn + u8 event_type + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static void roce3_handle_qp_async_event(struct roce3_device *rdev, u32 qpn, u8 event_type) +{ + struct roce3_qp *rqp = NULL; + cqm_object_s *cqm_obj_queue = NULL; + + cqm_obj_queue = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, qpn, false); + if (cqm_obj_queue == NULL) { + dev_err_ratelimited(rdev->hwdev_hdl, "[ROCE] %s: Failed to get cqm obj queue, func_id(%d), qpn:%u,\ + event_type:%u\n", __func__, rdev->glb_func_id, qpn, event_type); + return; + } + + rqp = cqmobj_to_roce_qp(cqm_obj_queue); + roce3_qp_async_event(rdev, rqp, (int)event_type); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_queue); +} + +/* **************************************************************************** + Prototype : roce3_handle_cq_async_event + Description : roce3_handle_cq_async_event + Input : struct roce3_device *rdev + u32 cqn + u8 event_type + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static void roce3_handle_cq_async_event(struct roce3_device *rdev, u32 cqn, u8 event_type) +{ + struct roce3_cq *rcq = NULL; + cqm_object_s *cqm_obj_queue = NULL; + + cqm_obj_queue = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SCQ, cqn, false); + if (cqm_obj_queue == NULL) { + dev_err_ratelimited(rdev->hwdev_hdl, "[ROCE] %s: Failed to get cqm obj queue, func_id(%d), cqn:%u,\ + event_type:%u\n", __func__, rdev->glb_func_id, cqn, event_type); + return; + } + + rcq = cqmobj_to_roce3_cq(cqm_obj_queue); + roce3_cq_async_event(rdev, rcq, (int)event_type); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_queue); +} + +/* **************************************************************************** + Prototype : roce3_handle_srq_async_event + Description : roce3_handle_srq_async_event + Input : struct roce3_device *rdev + u32 srqn + u8 event_type + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static void roce3_handle_srq_async_event(struct roce3_device *rdev, u32 srqn, u8 event_type) +{ + struct roce3_srq *rsrq = NULL; + cqm_object_s *cqm_obj_queue = NULL; + + cqm_obj_queue = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srqn, false); + if (cqm_obj_queue == NULL) { + dev_err_ratelimited(rdev->hwdev_hdl, "[ROCE] %s: Failed to get cqm obj queue, func_id(%d), srqn:%u,\ + event_type:%u\n", __func__, rdev->glb_func_id, srqn, event_type); + return; + } + + rsrq = cqmobj_to_roce3_srq(cqm_obj_queue); + roce3_srq_async_event(rdev, rsrq, (int)event_type); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_queue); +} + +static bool roce3_async_event_need_reset(u8 event_status) +{ + if ((event_status == API_FORMAT_ERROR) || (event_status == UNKNOWN_RESERVED_ERROR1)) { + return true; + } + + return false; +} + +u8 roce3_async_event_level(void *svc_hd, u8 event_type, u8 *val) +{ + u8 event_level = FAULT_LEVEL_MAX; + u8 event_status; + u64 param = *((u64 *)val); + + if (svc_hd == NULL) { + pr_err("[ROCE, ERR] %s: Svc_hd is null\n", __func__); + return FAULT_LEVEL_SUGGESTION; + } + + event_status = param & 0xff; + + switch (event_type) { + case ROCE_EVENT_TYPE_PATH_MIG: + case ROCE_EVENT_TYPE_COMM_EST: + case ROCE_EVENT_TYPE_SQ_DRAINED: + case ROCE_EVENT_TYPE_SRQ_QP_LAST_WQE: + case ROCE_EVENT_TYPE_SRQ_LIMIT: + case ROCE_EVENT_TYPE_PORT_MNG_CHG_EVENT: + case ROCE_EVENT_TYPE_PORT_CHANGE: + case ROCE_EVENT_TYPE_ECC_DETECT: + case ROCE_EVENT_TYPE_CMD: + case ROCE_EVENT_TYPE_COMM_CHANNEL: + case ROCE_EVENT_TYPE_OP_REQUIRED: + event_level = FAULT_LEVEL_SUGGESTION; + break; + + case ROCE_EVENT_TYPE_LOCAL_CATAS_ERROR: + case ROCE_EVENT_TYPE_WQ_INVAL_REQ_ERROR: // ROCE_AEQE_EVENT_QP_REQ_ERR + if (event_status == API_FORMAT_ERROR) { + return FAULT_LEVEL_SERIOUS_RESET; + } + break; + + case ROCE_EVENT_TYPE_WQ_CATAS_ERROR: // ROCE_AEQE_EVENT_WQE_CATAS + if (roce3_async_event_need_reset(event_status)) { + return FAULT_LEVEL_SERIOUS_RESET; + } + break; + + case ROCE_EVENT_TYPE_CQ_ERROR: // CQ ERR + if (roce3_async_event_need_reset(event_status)) { + return FAULT_LEVEL_SERIOUS_RESET; + } + break; + + default: + event_level = FAULT_LEVEL_GENERAL; + break; + } + + return event_level; +} + +static int roce3_async_event_handle_common(u8 event_type, u8 *val, struct roce3_device *rdev) +{ + u32 xid = 0; + int event_str_index = 0; + + switch (event_type) { + case ROCE_EVENT_TYPE_PATH_MIG: + case ROCE_EVENT_TYPE_COMM_EST: + case ROCE_EVENT_TYPE_SQ_DRAINED: + case ROCE_EVENT_TYPE_SRQ_QP_LAST_WQE: + case ROCE_EVENT_TYPE_WQ_CATAS_ERROR: + case ROCE_EVENT_TYPE_PATH_MIG_FAILED: + case ROCE_EVENT_TYPE_WQ_INVAL_REQ_ERROR: + case ROCE_EVENT_TYPE_WQ_ACCESS_ERROR: + xid = *((u32 *)val); + roce3_handle_qp_async_event(rdev, xid, event_type); + event_str_index = to_qp_event_str_index(event_type); + break; + + case ROCE_EVENT_TYPE_CQ_ERROR: + xid = *((u32 *)val); + roce3_handle_cq_async_event(rdev, xid, event_type); + event_str_index = OFED_ET_CQ_ERR; + break; + + case ROCE_EVENT_TYPE_SRQ_LIMIT: + xid = *((u32 *)val); + roce3_handle_srq_async_event(rdev, xid, event_type); + event_str_index = OFED_ET_SRQ_LIMIT; + break; + + case ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: + xid = *((u32 *)val); + roce3_handle_srq_async_event(rdev, xid, event_type); + event_str_index = OFED_ET_SRQ_CATAS_ERR; + break; + + default: + event_str_index = to_unkown_event_str_index(event_type, val); + break; + } + + return event_str_index; +} + +/* **************************************************************************** + Prototype : roce3_async_event + Description : roce3_async_event + Input : void *svc_hd + u8 event_type + u64 val + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_async_event(void *svc_hd, u8 event_type, u8 *val) +{ + int event_str_index = 0; + struct roce3_device *rdev = NULL; + + if (svc_hd == NULL) { + pr_err_ratelimited("[ROCE, ERR] %s: Svc_hd is null\n", __func__); + return; + } + + rdev = (struct roce3_device *)svc_hd; + if (event_type <= ROCE_EVENT_TYPE_ODP_PAGE_FAULT) { + event_str_index = roce3_async_event_handle_common(event_type, val, rdev); + } else { + event_str_index = roce3_async_event_handle_extend(event_type, val, rdev); + } + + roce3_event_report(rdev, event_str_index); +} + +static void roce3_handle_sq_hot_plug(struct roce3_qp *rqp, unsigned long flags_qp, struct list_head *cq_notify_list) +{ + struct roce3_cq *send_rcq = NULL; + unsigned long flags_cq = 0; + unsigned long flags_qp_tmp = flags_qp; + + spin_lock_irqsave(&rqp->sq.lock, flags_qp_tmp); + if (rqp->sq.tail == rqp->sq.head) { + goto roce_sq_hot_plug_end; + } + send_rcq = to_roce3_cq(rqp->ibqp.send_cq); + spin_lock_irqsave(&send_rcq->lock, flags_cq); + if (send_rcq->reset_flow_comp && rqp->ibqp.send_cq->comp_handler) { + if (send_rcq->reset_notify_added == 0) { + send_rcq->reset_notify_added = 1; + list_add_tail(&send_rcq->reset_notify, cq_notify_list); + } + } + spin_unlock_irqrestore(&send_rcq->lock, flags_cq); + +roce_sq_hot_plug_end: + spin_unlock_irqrestore(&rqp->sq.lock, flags_qp_tmp); + return; +} + +static void roce3_handle_rq_hot_plug(struct roce3_qp *rqp, unsigned long flags_qp, struct list_head *cq_notify_list) +{ + struct roce3_cq *recv_rcq = NULL; + unsigned long flags_cq = 0; + unsigned long flags_qp_tmp = flags_qp; + + spin_lock_irqsave(&rqp->rq.lock, flags_qp_tmp); + /* no handling is needed for SRQ */ + if (rqp->ibqp.srq != NULL) { + goto roce_rq_hot_plug_end; + } else if (rqp->rq.tail == rqp->rq.head) { + goto roce_rq_hot_plug_end; + } + recv_rcq = to_roce3_cq(rqp->ibqp.recv_cq); + spin_lock_irqsave(&recv_rcq->lock, flags_cq); + if (recv_rcq->reset_flow_comp && rqp->ibqp.recv_cq->comp_handler) { + if (recv_rcq->reset_notify_added == 0) { + recv_rcq->reset_notify_added = 1; + list_add_tail(&recv_rcq->reset_notify, cq_notify_list); + } + } + spin_unlock_irqrestore(&recv_rcq->lock, flags_cq); +roce_rq_hot_plug_end: + spin_unlock_irqrestore(&rqp->rq.lock, flags_qp_tmp); + return; +} + +void roce3_handle_hotplug_arm_cq(struct roce3_device *rdev) +{ + struct roce3_qp *rqp = NULL; + struct roce3_cq *rcq = NULL; + unsigned long flags_qp = 0; + unsigned long flags = 0; + struct list_head cq_notify_list; + + pr_err("[ROCE, ERR] %s: Hotplug arm cq start:\n", __func__); + + INIT_LIST_HEAD(&cq_notify_list); + + /* Go over qp list reside on that rdev, sync with create/destroy qp */ + spin_lock_irqsave(&rdev->reset_flow_resource_lock, flags); + list_for_each_entry(rqp, &rdev->qp_list, qps_list) + { + roce3_handle_sq_hot_plug(rqp, flags_qp, &cq_notify_list); + roce3_handle_rq_hot_plug(rqp, flags_qp, &cq_notify_list); + } + + list_for_each_entry(rcq, &cq_notify_list, reset_notify) + { + rcq->reset_flow_comp(rcq); + } + spin_unlock_irqrestore(&rdev->reset_flow_resource_lock, flags); + + pr_err("[ROCE, ERR] %s: Hotplug arm cq end!\n", __func__); +} + +void roce3_kernel_hotplug_event_trigger(struct roce3_device *rdev) +{ + int carrier_ok = 0; + + if (rdev->ndev) { + carrier_ok = netif_carrier_ok(rdev->ndev); + if (carrier_ok != 0) { + dev_info(rdev->hwdev_hdl, "[ROCE] %s: Turn off, func_id(%hu), name(%s), pci(%s),\n", + __func__, rdev->glb_func_id, rdev->ib_dev.name, pci_name(rdev->pdev)); + netif_carrier_off(rdev->ndev); + } + + ROCE_MDELAY(ROCE_M_DELAY); + return; + } + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: rdev->ndev is NULL\n", __func__); + return; +} + +#ifdef ROCE_BONDING_EN +void roce3_handle_bonded_port_state_event(struct roce3_device *rdev) +{ + struct net_device *master = netdev_master_upper_dev_get_rcu(rdev->ndev); + enum ib_port_state bonded_port_state = IB_PORT_NOP; + struct roce3_bond_device *bond_dev = NULL; + enum ib_port_state curr_port_state; + enum ib_event_type event; + struct roce3_bond_slave *slave = NULL; + int i; + + if (master == NULL) { + return; + } + + bond_dev = rdev->bond_dev; + if (bond_dev == NULL) { + pr_err("[ROCE, ERR] %s: No bond_dev found\n", __func__); + return; + } + + if (netif_running(master) != 0) { + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->netdev == NULL) { + continue; + } + + curr_port_state = (netif_running(slave->netdev) && + netif_carrier_ok(slave->netdev)) ? + IB_PORT_ACTIVE : + IB_PORT_DOWN; + + bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ? curr_port_state : IB_PORT_ACTIVE; + } + mutex_unlock(&bond_dev->slave_lock); + } else { + bonded_port_state = IB_PORT_DOWN; + } + + if (rdev->port_state != bonded_port_state) { + event = (bonded_port_state == IB_PORT_ACTIVE) ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; + if (roce3_ifconfig_up_down_event_report(rdev, event) != 0) { + return; + } + rdev->port_state = bonded_port_state; + } +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/roce_event.h b/drivers/infiniband/hw/hiroce3/roce_event.h new file mode 100644 index 000000000..7e11d13ac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_event.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_event.h + * Version : v2.0 + * Created : 2021/3/10 + * Last Modified : 2021/12/23 + * Description : The definition of RoCE async event relatedfunction prototypes, macros etc. + */ + +#ifndef ROCE_EVENT_H +#define ROCE_EVENT_H + +#include <net/ipv6.h> +#include <net/addrconf.h> +#include <net/bonding.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/pci.h> +#include <linux/inetdevice.h> +#include <linux/if_vlan.h> + +#include <rdma/ib_user_verbs.h> +#include <rdma/ib_addr.h> + +#include "roce.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_qp.h" +#include "roce_cmd.h" + +#define ROCE_M_DELAY 100 +#define API_FORMAT_ERROR 0x2 +#define UNKNOWN_RESERVED_ERROR1 0xe +#define QPC_LOOKUP_ERR_VALUE 0x300d00016 + +int to_unkown_event_str_index(u8 event_type, const u8 *val); + +void roce3_handle_hotplug_arm_cq(struct roce3_device *rdev); +void roce3_kernel_hotplug_event_trigger(struct roce3_device *rdev); + +#endif /* ROCE_EVENT_H */ diff --git a/drivers/infiniband/hw/hiroce3/roce_k_ioctl.h b/drivers/infiniband/hw/hiroce3/roce_k_ioctl.h new file mode 100755 index 000000000..33dbc86f3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_k_ioctl.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_k_ioctl.h + * Version : v2.0 + * Created : 2021/3/2 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE kernel2user comm related functions. + */ + +#ifndef ROCE_K_IOCTL_H +#define ROCE_K_IOCTL_H + +#include <rdma/ib_verbs.h> +#include <rdma/ib_user_verbs.h> + +#define ROCE_IOCTL_MAGIC 'R' +#define ROCE_CMD_QUERY_DCB _IO(ROCE_IOCTL_MAGIC, 0) +#define ROCE_CMD_CREATE_AH _IO(ROCE_IOCTL_MAGIC, 1) + +#define ROCE_CMD_QUERY_QP_TX_PORT _IO(ROCE_IOCTL_MAGIC, 3) +#define ROCE_CMD_SET_QP_TX_PORT _IO(ROCE_IOCTL_MAGIC, 4) +#define ROCE_CMD_QUERY_QP_RX_PORT _IO(ROCE_IOCTL_MAGIC, 5) +#define ROCE_CMD_QUERY_BOND_PORT_INFO _IO(ROCE_IOCTL_MAGIC, 6) +#define ROCE_CMD_SET_QP_UDP_SRC_PORT _IO(ROCE_IOCTL_MAGIC, 7) +#define ROCE_CMD_QUERY_QP_UDP_SRC_PORT _IO(ROCE_IOCTL_MAGIC, 8) +#define ROCE_CMD_QUERY_NEXT_WQE_IDX _IO(ROCE_IOCTL_MAGIC, 9) + +#define ROCE_CMD_MAX _IO(ROCE_IOCTL_MAGIC, 10) + +#ifdef ROCE_EXTEND +#define HW_ROCE_EXT_CMD_SET_QP_ATTR _IO(ROCE_IOCTL_MAGIC, 11) +#define HW_ROCE_EXT_CMD_CREATE_SQPC _IO(ROCE_IOCTL_MAGIC, 12) +#endif + +// roce3_ioctrl_version +#define VERSION_LEN (20) +#define HW_ROCE_CMD_VERSION _IO(ROCE_IOCTL_MAGIC, 20) +// reserved op code +#define HW_ROCE_CMD_RESERVED_1 _IO(ROCE_IOCTL_MAGIC, 21) +#define HW_ROCE_CMD_RESERVED_2 _IO(ROCE_IOCTL_MAGIC, 22) +#define HW_ROCE_CMD_RESERVED_3 _IO(ROCE_IOCTL_MAGIC, 23) +#define HW_ROCE_CMD_RESERVED_4 _IO(ROCE_IOCTL_MAGIC, 24) +#define HW_ROCE_CMD_RESERVED_5 _IO(ROCE_IOCTL_MAGIC, 25) +#define HW_ROCE_CMD_RESERVED_6 _IO(ROCE_IOCTL_MAGIC, 26) + +#define ROCE_DEV_NAME_MAX 64 + +union roce3_query_dcb_buf { + struct roce3_query_dcb_cmd { + u8 sl; + u8 sgid_idx; + u8 port; + u8 traffic_class; // dscp + u8 dscp_type; + u8 rsvd[3]; + } cmd; + + struct roce3_query_dcb_resp { + u8 cos; + u8 rsvd[7]; + } resp; +}; + +union roce3_create_ah_buf { + struct roce3_create_ah_cmd { + struct ib_uverbs_ah_attr attr; + } cmd; + + struct roce3_create_ah_resp { + u8 dmac[ETH_ALEN]; + u16 vlan_id; + } resp; +}; + +struct roce3_qp_port_buf { + u32 qpn; + u32 port; +}; + +struct roce3_bond_port_info_buf { + int original_port_num; + char original_port[8]; + int rsvd1; + + int alive_port_num; + char alive_port[8]; + int rsvd2; +}; + +struct roce3_qp_udp_src_port_buf { + u32 qpn; + u32 udp_src_port; +}; + +#endif diff --git a/drivers/infiniband/hw/hiroce3/roce_main.c b/drivers/infiniband/hw/hiroce3/roce_main.c new file mode 100755 index 000000000..4f3c90333 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_main.c @@ -0,0 +1,1752 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_main.c + * Version : v2.0 + * Created : 2021/3/2 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE MAIN related functions. + */ + +#include <net/ipv6.h> +#include <net/addrconf.h> +#include <net/bonding.h> +#include <rdma/ib_verbs.h> +#include <rdma/ib_addr.h> +#include <rdma/ib_user_verbs.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/errno.h> +#include <linux/inetdevice.h> +#include <linux/if_vlan.h> + +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "hinic3_hwdev.h" +#include "hinic3_srv_nic.h" +#include "hinic3_rdma.h" +#include "hinic3_bond.h" +#include "hinic3_pci_id_tbl.h" + +#include "roce_event.h" +#include "roce_compat.h" +#include "roce_dfx.h" +#include "roce_mr.h" +#include "roce_main_extension.h" + +#ifdef ROCE_NETLINK_EN +#include "roce_netlink.h" +#endif + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#include "roce_pub_cmd.h" + +MODULE_AUTHOR(HIROCE3_DRV_AUTHOR); +MODULE_DESCRIPTION(HIROCE3_DRV_DESC); +MODULE_VERSION(HIROCE3_DRV_VERSION); +MODULE_LICENSE("GPL"); + +static int g_loop_times = 50000; +module_param(g_loop_times, int, 0444); //lint !e806 +MODULE_PARM_DESC(g_loop_times, "default: 50000"); + +static bool g_ppf_stateful_init = false; +static u8 g_vf_stateful_num = 0; + +#ifdef ROCE_BONDING_EN +static int g_want_bond_slave_cnt = ROCE_BOND_WANT_TWO_SLAVES; +module_param(g_want_bond_slave_cnt, int, 0444); +MODULE_PARM_DESC(g_want_bond_slave_cnt, "default: 2, 2: two slaves, 3: three slaves, 4: four slaves"); + +static int g_want_bond0_slave_bits = 0x3; /* 0011 */ +module_param(g_want_bond0_slave_bits, int, 0444); +MODULE_PARM_DESC(g_want_bond0_slave_bits, "default: 0x3(PF0+PF1), 4bits"); + +static char *g_bond_name = NULL; +module_param(g_bond_name, charp, 0444); +MODULE_PARM_DESC(g_bond_name, "bond name for sdi"); +#endif + +struct roce3_func_info { + u16 func_id; + struct list_head node; +}; + +LIST_HEAD(g_roce_device_list); +static void roce3_remove_device_from_list(struct hinic3_lld_dev *lld_dev); +static int roce3_add_device_to_list(struct hinic3_lld_dev *lld_dev); +static void roce3_wait_probe(struct hinic3_lld_dev *lld_dev); +DECLARE_WAIT_QUEUE_HEAD(g_roce_probe_queue); + +/* **************************************************************************** + Prototype : roce3_cq_completion + Description : RoCE's callback function for CQ's completion events on ARM CQs + Input : void *svc_hd + u32 cqn + void *cq_handler + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_completion(void *svc_hd, u32 cqn, void *cq_handler) +{ + struct roce3_cq *cq = NULL; + struct ib_cq *ibcq = NULL; + + if (cq_handler == NULL) { + pr_err("[ROCE, ERR] %s: Cq_handler is null\n", __func__); + return; + } + + cq = (struct roce3_cq *)cq_handler; + + ++cq->arm_sn; + cq->arm_flag = 0; + + ibcq = &cq->ibcq; + + ibcq->comp_handler(ibcq, ibcq->cq_context); +} + +/* **************************************************************************** + Prototype : get_cpu_endian + Description : Acquire CPU's enianness + Return Value : 0: little endian; 1: big endian + + 1.Date : 2016/6/23 + Modification : Created function + +**************************************************************************** */ +static int get_cpu_endian(void) +{ + int cpu_mode = 0; + union { + unsigned int i; + unsigned char s[4]; + } c; + c.i = 0x12345678; + + if (c.s[0] == 0x12) { + pr_info("[ROCE] %s: CPU is be\n", __func__); + cpu_mode = 1; + } else { + pr_info("[ROCE] %s: CPU is le\n", __func__); + cpu_mode = 0; + } + + return cpu_mode; +} + +static int roce3_alloc_hw_resource(struct roce3_device *rdev) +{ + int ret; + + ret = roce3_rdma_init_rsvd_lkey(rdev->hwdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to init rsvd lkey, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ret; + } + + ret = roce3_rdma_reset_gid_table(rdev->hwdev, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR]: Failed to reset gid_table, func_id(%hu)\n", rdev->glb_func_id); + goto err_gid_reset; + } + + return 0; + +err_gid_reset: + roce3_rdma_free_rsvd_lkey(rdev->hwdev); + + return ret; +} + +static void roce3_dealloc_hw_resource(struct roce3_device *rdev) +{ + roce3_rdma_free_rsvd_lkey(rdev->hwdev); +} + +static struct roce3_device *roce3_rdev_alloc(struct hinic3_lld_dev *lld_dev, void **uld_dev, + const struct rdma_service_cap *rdma_cap) +{ + struct roce3_device *rdev = NULL; + + rdev = (struct roce3_device *)roce3_rdev_alloc_ext(); + if (rdev == NULL) { + pr_err("[ROCE, ERR] %s: Failed to alloc rdev\n", __func__); + return NULL; + } + + *uld_dev = (void *)rdev; + rdev->lld_dev = lld_dev; + rdev->hwdev = lld_dev->hwdev; + rdev->pdev = lld_dev->pdev; + mutex_init(&rdev->qp_cnt.cur_qps_mutex); + + rdev->hwdev_hdl = ((struct hinic3_hwdev *)(rdev->hwdev))->dev_hdl; + memcpy((void *)&rdev->rdma_cap, (void *)rdma_cap, sizeof(*rdma_cap)); + + rdev->ndev = hinic3_get_netdev_by_lld(rdev->lld_dev); + if (rdev->ndev == NULL) { + pr_err("[ROCE, ERR] %s roce add failed, netdev is null.\n", __func__); + ib_dealloc_device(&rdev->ib_dev); + return NULL; + } + + roce3_rdev_set_ext(rdev); + + return rdev; +} + +static int roce3_board_info_get(struct roce3_device *rdev) +{ + int ret = 0; + + ret = hinic3_get_board_info(rdev->hwdev, &rdev->board_info, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get board info\n", __func__); + return ret; + } + + pr_info("[ROCE] Get board info success, board_type:0x%x, port_num:0x%x, pf_num:0x%x, vf_total_num:0x%x, " + "work_mode:0x%x, " + "service_mode:0x%x, speed:0x%x.\n", + rdev->board_info.board_type, rdev->board_info.port_num, rdev->board_info.pf_num, rdev->board_info.vf_total_num, + rdev->board_info.work_mode, rdev->board_info.service_mode, rdev->board_info.port_speed); + +#ifdef ROCE_BONDING_EN + ret = roce3_bond_attach(rdev); + if (ret != 0) { + return ret; + } +#endif + + ret = roce3_board_cfg_check(rdev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check board cfg info\n", __func__); + return ret; + } + + return ret; +} + +static int roce3_init_info_get(struct roce3_device *rdev) +{ + int ret = 0; + + ret = roce3_board_info_get(rdev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get board info\n", __func__); + return ret; + } + + return ret; +} + +static void roce3_fix_ibdev_name(struct roce3_device *rdev) +{ +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + strcpy(rdev->ib_dev.name, "hrn3_bond_%d"); + return; + } +#endif + { + strcpy(rdev->ib_dev.name, (rdev->is_vroce ? "efi_%d" : "hrn3_%d")); + } +} + +static int roce3_register_template(struct roce3_device *rdev) +{ + service_register_template_s svc_template; + int ret; + + memset(&svc_template, 0, sizeof(svc_template)); + + svc_template.service_type = SERVICE_T_ROCE; + svc_template.scq_ctx_size = rdev->rdma_cap.cqc_entry_sz; + svc_template.srq_ctx_size = rdev->rdma_cap.dev_rdma_cap.roce_own_cap.srqc_entry_sz; + svc_template.service_handle = rdev; + svc_template.embedded_cq_ceq_callback = NULL; + svc_template.no_cq_ceq_callback = NULL; + + svc_template.shared_cq_ceq_callback = roce3_cq_completion; + svc_template.aeq_level_callback = roce3_async_event_level; + svc_template.aeq_callback = roce3_async_event; + + ret = cqm_service_register(rdev->hwdev, &svc_template); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to register cqm_service, func(%hu)\n", __func__, + rdev->glb_func_id); + return ret; + } + + return 0; +} + +int roce3_init_dev_file(struct roce3_device *rdev) +{ + int ret = 0; + + ret = roce3_init_sysfs(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to init sysfs, func_id(%hu) ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return ret; + } + + ret = roce3_init_cdev(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to init cdev, func_id(%hu)\n", __func__, rdev->glb_func_id); + roce3_remove_sysfs(rdev); + } + + return ret; +} + +void roce3_remove_dev_file(struct roce3_device *rdev) +{ + roce3_remove_cdev(rdev); + + roce3_remove_sysfs(rdev); +} + +/* Alloc CEQs and alloc CEQN */ +static int roce3_alloc_ceq(struct roce3_device *rdev) +{ + int ret; + + ret = hinic3_alloc_ceqs(rdev->hwdev, SERVICE_T_ROCE, rdev->ib_dev.num_comp_vectors, rdev->ceqn, &rdev->ceq_num); + if (ret < 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqes, num_comp_vectors(%d), func_id(%hu)\n", __func__, + rdev->ib_dev.num_comp_vectors, rdev->glb_func_id); + return ret; + } + + return 0; +} + +static void roce3_free_ceq(struct roce3_device *rdev) +{ + int i; + + for (i = 0; i < rdev->ceq_num; ++i) { + hinic3_free_ceq(rdev->hwdev, SERVICE_T_ROCE, rdev->ceqn[i]); + } +} + +static void roce3_init_hw_info(struct roce3_device *rdev) +{ + int ret; + struct roce_group_id group_id = {0}; + + rdev->hw_info.config_num_ports = (int)rdev->rdma_cap.num_ports; + rdev->hw_info.ep_id = hinic3_ep_id(rdev->hwdev); + rdev->hw_info.phy_port = 1; + rdev->hw_info.is_vf = (hinic3_func_type(rdev->hwdev) == TYPE_VF); + rdev->hw_info.cpu_endian = (u8)get_cpu_endian(); + + if (!rdev->is_vroce) { + return; + } + + ret = roce3_get_group_id(rdev->glb_func_id, rdev->hwdev, &group_id); + if (!!ret) { + dev_info(rdev->hwdev_hdl, "[ROCE , INFO] Failed to get group id, ret(%d)", ret); + return; + } + + rdev->group_rc_cos = group_id.group_rc_cos; + rdev->group_ud_cos = group_id.group_ud_cos; + rdev->group_xrc_cos = group_id.group_xrc_cos; + dev_info(rdev->hwdev_hdl, "[ROCE , INFO] group id rc(%hhu), ud(%hhu), xrc(%hhu)", + group_id.group_rc_cos, group_id.group_ud_cos, group_id.group_xrc_cos); +} + +static int roce3_init_dev_upper(struct roce3_device *rdev) +{ + int ret; + + /* Set function table to ENABLE */ + ret = roce3_set_func_tbl_func_state(rdev, ROCE_FUNC_ENABLE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set func_tbl, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_set_func_tbl; + } + return 0; + +err_set_func_tbl: + return ret; +} + +static void roce3_deinit_dev_upper(struct roce3_device *rdev) +{ + (void)roce3_set_func_tbl_func_state(rdev, ROCE_FUNC_DISABLE); +} + +static int roce3_init_dev_info(struct roce3_device *rdev) +{ + int ret; + + ret = roce3_set_func_tbl_cpu_endian(rdev->hwdev, rdev->hw_info.cpu_endian, rdev->glb_func_id); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR]: Failed to set func_tbl cpu_endian, func_id(%hu)\n", rdev->glb_func_id); + goto err_init_endianess; + } + + ret = roce3_init_dev_ext(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR]: Failed to init extended service for func_id(%hu)\n", rdev->glb_func_id); + goto err_init_dev_ext; + } + + ret = roce3_dfx_mem_alloc(rdev); + if (ret != 0) { + goto err_init_dev_dfx; + } + + ret = roce3_init_dev_upper(rdev); + if (ret != 0) { + goto err_init_dev_upper; + } + + return 0; + +err_init_dev_upper: + roce3_dfx_mem_free(rdev); +err_init_dev_dfx: + roce3_remove_clean_res_ext(rdev); +err_init_dev_ext: +err_init_endianess: + return ret; +} + +static void roce3_deinit_dev_info(struct roce3_device *rdev) +{ + roce3_deinit_dev_upper(rdev); + roce3_dfx_mem_free(rdev); + roce3_remove_clean_res_ext(rdev); +} +#ifdef ROCE_BONDING_EN +static int roce3_ib_register_bond_device(struct roce3_device *rdev) +{ +#if defined(KY10_OFED_4_19) || defined(EULER_2_10_OFED_4_18) + return ib_register_device(&rdev->ib_dev, "hrn3_bond_%d", NULL); +#elif defined(EULER_2_10_OFED_4_19) + roce3_fix_ibdev_name(rdev); + return ib_register_device(&rdev->ib_dev, NULL); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + return ib_register_device(&rdev->ib_dev, "hrn3_bond_%d", &rdev->pdev->dev); +#endif +} +#endif // ROCE_BONDING_EN + +static int roce3_ib_register_unbond_device(struct roce3_device *rdev) +{ +#if defined(KY10_OFED_4_19) || defined(EULER_2_10_OFED_4_18) + return ib_register_device(&rdev->ib_dev, "hrn3_%d", NULL); +#elif defined(EULER_2_10_OFED_4_19) + roce3_fix_ibdev_name(rdev); + return ib_register_device(&rdev->ib_dev, NULL); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + return ib_register_device(&rdev->ib_dev, "hrn3_%d", &rdev->pdev->dev); +#endif +} + +static int roce3_ib_register_device(struct roce3_device *rdev) +{ +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + return roce3_ib_register_bond_device(rdev); + } +#endif + return roce3_ib_register_unbond_device(rdev); +} + +static int roce3_init_dev(struct roce3_device *rdev, char *uld_dev_name) +{ + int ret; + + ret = roce3_init_dev_info(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to init dev info, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_init_dev_info; + } + + /* Clear gid table before register for a new IB device */ + ret = roce3_alloc_hw_resource(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc hw res, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_alloc_hw_res; + } + + roce3_wait_probe(rdev->lld_dev); + + ret = roce3_ib_register_device(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to reg ibdev, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_reg_dev; + } + + roce3_remove_device_from_list(rdev->lld_dev); + + memcpy(uld_dev_name, rdev->ib_dev.name, ROCE_ULD_DEV_NAME_LEN); + + ret = roce3_register_netdev_event(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to reg netdev, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_memcpy_uld; + } + + ret = roce3_init_dev_file(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to init sysfs, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_init_dev_file; + } + rdev->ib_active = true; + dev_info(rdev->hwdev_hdl, "[ROCE] %s: RoCE add init all ok, func_id(%hu), dev_name(%s)\n", __func__, + rdev->glb_func_id, rdev->ib_dev.name); + + return 0; + +err_init_dev_file: + roce3_unregister_netdev_event(rdev); +err_memcpy_uld: + ib_unregister_device(&rdev->ib_dev); +err_reg_dev: + roce3_dealloc_hw_resource(rdev); +err_alloc_hw_res: + roce3_deinit_dev_info(rdev); +err_init_dev_info: + return ret; +} + +static int roce3_add_rdev_init(struct roce3_device *rdev) +{ + int ret = 0; + + ret = roce3_init_info_get(rdev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check\n", __func__); + return ret; + } + + rdev->gid_dev = + (struct net_device **)kzalloc(rdev->rdma_cap.max_gid_per_port * sizeof(struct net_device *), GFP_KERNEL); + if (rdev->gid_dev == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc gid dev memory, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + ret = roce3_rdma_init_resource(rdev->hwdev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to init rdma resources.\n", __func__); + goto err_init_resource; + } + + pr_info("[ROCE] %s: Initializing(%s)\n", __func__, pci_name(rdev->pdev)); + + rdev->glb_func_id = hinic3_global_func_id(rdev->hwdev); + + rdev->is_vroce = false; +#ifdef ROCE_VROCE_EN + ret = hinic3_is_slave_func(rdev->hwdev, &rdev->is_vroce); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to get slave_func.\n", __func__); + } +#endif + + roce3_init_hw_info(rdev); + + ret = roce3_init_cfg_info(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR]%s: Failed to get roce cfg, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_init_cfg; + } + + return 0; + +err_init_cfg: + roce3_rdma_cleanup_resource(rdev->hwdev); + +err_init_resource: + if (rdev->gid_dev != NULL) { + kfree(rdev->gid_dev); + } + return ret; +} + +static void roce3_add_rdev_unit(struct roce3_device *rdev) +{ + roce3_rdma_cleanup_resource(rdev->hwdev); + if (rdev->gid_dev != NULL) { + kfree(rdev->gid_dev); + } +} + +static __be64 rdma_gen_node_guid(u8 *dev_mac) +{ + u8 guid[8]; + u8 mac_addr[6]; + __be64 node_guid = 0; + + if (dev_mac == NULL) { + pr_err("[ROCE, ERR]%s: Dev_mac is null\n", __FUNCTION__); + return RDMA_INVALID_GUID; + } + + memcpy((void *)&mac_addr[0], (void *)dev_mac, sizeof(mac_addr)); + + guid[0] = mac_addr[0] ^ DEV_ADDR_FIRST_BYTE_VAL_MASK; // 0 is mac & guid array idx + guid[1] = mac_addr[1]; // 1 is mac & guid array idx + guid[2] = mac_addr[2]; // 2 is mac & guid array idx + guid[3] = 0xff; // 3 is guid array idx + guid[4] = 0xfe; // 4 is guid array idx + guid[5] = mac_addr[3]; // 5 is guid array idx, 3 is mac array idx + guid[6] = mac_addr[4]; // 6 is guid array idx, 4 is mac array idx + guid[7] = mac_addr[5]; // 7 is guid array idx, 5 is mac array idx + + /* node_guid is calculated by guid. */ + node_guid = ((u64)guid[0] << 56) | // 0 is guid array idx, 56 is guid offset + ((u64)guid[1] << 48) | // 1 is guid array idx, 48 is guid offset + ((u64)guid[2] << 40) | // 2 is guid array idx, 40 is guid offset + ((u64)guid[3] << 32) | // 3 is guid array idx, 32 is guid offset + ((u64)guid[4] << 24) | // 4 is guid array idx, 24 is guid offset + ((u64)guid[5] << 16) | // 5 is guid array idx, 16 is guid offset + ((u64)guid[6] << 8) | // 6 is guid array idx, 8 is guid offset + (u64)guid[7]; // 7 is guid array idx + + return (__be64)cpu_to_be64(node_guid); +} + +static __be64 roce3_rdma_init_guid(void *hwdev, struct net_device *netdev) +{ + struct rdma_comp_priv *comp_priv = NULL; + + if ((hwdev == NULL) || (netdev == NULL)) { + pr_err("[ROCE, ERR]%s: Hwdev or netdev is null\n", __FUNCTION__); + return ~0ULL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("[ROCE, ERR]%s: Comp_priv is null\n", __FUNCTION__); + return ~0ULL; + } + + comp_priv->rdma_comp_res.node_guid = rdma_gen_node_guid((u8 *)netdev->dev_addr); + + return comp_priv->rdma_comp_res.node_guid; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) || defined(OFED_MLNX_5_8) +static const struct ib_device_ops dev_ops = { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + .owner = THIS_MODULE, + .uverbs_abi_ver = ROCE_IB_UVERBS_ABI_VERSION, +#endif + + .create_qp = roce3_create_qp, + .modify_qp = roce3_modify_qp, + .query_qp = roce3_query_qp, + .destroy_qp = roce3_destroy_qp, + .post_send = roce3_post_send, + .post_recv = roce3_post_recv, + .create_cq = roce3_create_cq, + .modify_cq = roce3_modify_cq, + .resize_cq = roce3_resize_cq, + .destroy_cq = roce3_destroy_cq, + .poll_cq = roce3_poll_cq, + .req_notify_cq = roce3_arm_cq, + .create_srq = roce3_create_srq, + .modify_srq = roce3_modify_srq, + .query_srq = roce3_query_srq, + .destroy_srq = roce3_destroy_srq, + .post_srq_recv = roce3_post_srq_recv, + .map_mr_sg = roce3_map_kernel_frmr_sg, + .get_dma_mr = roce3_get_dma_mr, + .reg_user_mr = roce3_reg_user_mr, + .dereg_mr = roce3_dereg_mr, + .alloc_mr = roce3_alloc_mr, + .alloc_mw = roce3_alloc_mw, + .dealloc_mw = roce3_dealloc_mw, + .query_device = roce3_query_device, + .query_port = roce3_query_port, + .get_link_layer = roce3_port_link_layer, + .query_gid = roce3_query_gid, + .add_gid = roce3_ib_add_gid, + .del_gid = roce3_ib_del_gid, + .query_pkey = roce3_query_pkey, + .modify_device = roce3_modify_device, + .modify_port = roce3_modify_port, + .alloc_ucontext = roce3_alloc_ucontext, + .dealloc_ucontext = roce3_dealloc_ucontext, + .mmap = roce3_mmap, + .alloc_pd = roce3_alloc_pd, + .dealloc_pd = roce3_dealloc_pd, + .create_ah = roce3_create_ah, + .query_ah = roce3_query_ah, + .destroy_ah = roce3_destroy_ah, + .alloc_xrcd = roce3_alloc_xrcd, + .dealloc_xrcd = roce3_dealloc_xrcd, + .get_port_immutable = roce3_port_immutable, + .get_netdev = roce3_ib_get_netdev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + INIT_RDMA_OBJ_SIZE(ib_qp, roce3_qp, ibqp), + INIT_RDMA_OBJ_SIZE(ib_ah, roce3_ah, ibah), + INIT_RDMA_OBJ_SIZE(ib_cq, roce3_cq, ibcq), + INIT_RDMA_OBJ_SIZE(ib_pd, roce3_pd, ibpd), + INIT_RDMA_OBJ_SIZE(ib_srq, roce3_srq, ibsrq), + INIT_RDMA_OBJ_SIZE(ib_ucontext, roce3_ucontext, ibucontext), + INIT_RDMA_OBJ_SIZE(ib_xrcd, roce3_xrcd, ibxrcd), + INIT_RDMA_OBJ_SIZE(ib_mw, roce3_mw, ibmw), +#endif +}; + +static void roce3_add_init(struct roce3_device *rdev) +{ + struct ib_device *ib_dev = &rdev->ib_dev; + + ib_dev->local_dma_lkey = rdev->rdma_cap.reserved_lkey; + ib_dev->phys_port_cnt = (u8)rdev->rdma_cap.num_ports; + ib_dev->num_comp_vectors = + (rdev->rdma_cap.num_comp_vectors <= MAX_CEQ_NEED) ? (int)rdev->rdma_cap.num_comp_vectors : MAX_CEQ_NEED; + ib_dev->node_type = RDMA_NODE_IB_CA; + ib_dev->node_guid = roce3_rdma_init_guid(rdev->hwdev, rdev->ndev); + ib_dev->dma_device = &rdev->pdev->dev; + ib_dev->dev.parent = ib_dev->dma_device; + strcpy(ib_dev->node_desc, "hrn3"); + + rdev->ib_dev.uverbs_cmd_mask = ROCE_UVERBS_CMD_MASK; +#ifndef OFED_MLNX_5_8 + rdev->ib_dev.uverbs_ex_cmd_mask = ROCE_UVERBS_EXT_CMD_MASK; +#endif + ib_set_device_ops(ib_dev, &dev_ops); + roce3_init_dev_ext_handlers(rdev); + + return; +} + +#else // (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) +static void roce3_init_dev_qp_handlers(struct roce3_device *rdev) +{ +#ifndef __PC_LINT__ + rdev->ib_dev.create_qp = roce3_create_qp; + rdev->ib_dev.modify_qp = roce3_modify_qp; + rdev->ib_dev.query_qp = roce3_query_qp; + rdev->ib_dev.destroy_qp = roce3_destroy_qp; + rdev->ib_dev.post_send = roce3_post_send; + rdev->ib_dev.post_recv = roce3_post_recv; + rdev->ib_dev.drain_rq = roce3_drain_rq; +#endif +} + +static void roce3_init_dev_cq_handlers(struct roce3_device *rdev) +{ + rdev->ib_dev.create_cq = roce3_create_cq; + rdev->ib_dev.modify_cq = roce3_modify_cq; + rdev->ib_dev.resize_cq = roce3_resize_cq; + rdev->ib_dev.destroy_cq = roce3_destroy_cq; + rdev->ib_dev.poll_cq = roce3_poll_cq; + rdev->ib_dev.req_notify_cq = roce3_arm_cq; +} + +static void roce3_init_dev_srq_handlers(struct roce3_device *rdev) +{ + rdev->ib_dev.create_srq = roce3_create_srq; + rdev->ib_dev.modify_srq = roce3_modify_srq; + rdev->ib_dev.query_srq = roce3_query_srq; + rdev->ib_dev.destroy_srq = roce3_destroy_srq; + rdev->ib_dev.post_srq_recv = roce3_post_srq_recv; +} + +static void roce3_init_dev_mr_handlers(struct roce3_device *rdev) +{ + rdev->ib_dev.map_mr_sg = roce3_map_kernel_frmr_sg; + + rdev->ib_dev.get_dma_mr = roce3_get_dma_mr; + rdev->ib_dev.reg_user_mr = roce3_reg_user_mr; + rdev->ib_dev.dereg_mr = roce3_dereg_mr; + rdev->ib_dev.alloc_mr = roce3_alloc_mr; + + rdev->ib_dev.alloc_fmr = roce3_alloc_fmr; + rdev->ib_dev.map_phys_fmr = roce3_map_phys_fmr; + rdev->ib_dev.unmap_fmr = roce3_unmap_fmr; + rdev->ib_dev.dealloc_fmr = roce3_dealloc_fmr; + rdev->ib_dev.alloc_mw = roce3_alloc_mw; + rdev->ib_dev.dealloc_mw = roce3_dealloc_mw; + rdev->ib_dev.uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) | (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW); +} + +static void roce3_init_dev_handlers(struct roce3_device *rdev) +{ + rdev->ib_dev.query_device = roce3_query_device; + rdev->ib_dev.query_port = roce3_query_port; + rdev->ib_dev.get_link_layer = roce3_port_link_layer; + rdev->ib_dev.query_gid = roce3_query_gid; + rdev->ib_dev.add_gid = roce3_ib_add_gid; + rdev->ib_dev.del_gid = roce3_ib_del_gid; + rdev->ib_dev.query_pkey = roce3_query_pkey; + rdev->ib_dev.modify_device = roce3_modify_device; + rdev->ib_dev.modify_port = roce3_modify_port; + + rdev->ib_dev.alloc_ucontext = roce3_alloc_ucontext; + rdev->ib_dev.dealloc_ucontext = roce3_dealloc_ucontext; + rdev->ib_dev.mmap = roce3_mmap; + + rdev->ib_dev.alloc_pd = roce3_alloc_pd; + rdev->ib_dev.dealloc_pd = roce3_dealloc_pd; + + rdev->ib_dev.create_ah = roce3_create_ah; + rdev->ib_dev.query_ah = roce3_query_ah; + rdev->ib_dev.destroy_ah = roce3_destroy_ah; + + roce3_init_dev_qp_handlers(rdev); + roce3_init_dev_cq_handlers(rdev); + roce3_init_dev_srq_handlers(rdev); + roce3_init_dev_mr_handlers(rdev); + + rdev->ib_dev.alloc_xrcd = roce3_alloc_xrcd; + rdev->ib_dev.dealloc_xrcd = roce3_dealloc_xrcd; + rdev->ib_dev.uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_OPEN_XRCD) | (1ULL << IB_USER_VERBS_CMD_CLOSE_XRCD); + + rdev->ib_dev.get_port_immutable = roce3_port_immutable; + rdev->ib_dev.get_netdev = roce3_ib_get_netdev; +} + +static void roce3_add_init(struct roce3_device *rdev) +{ + rdev->ib_dev.owner = THIS_MODULE; + rdev->ib_dev.node_type = RDMA_NODE_IB_CA; + rdev->ib_dev.local_dma_lkey = rdev->rdma_cap.reserved_lkey; + rdev->ib_dev.phys_port_cnt = (u8)rdev->rdma_cap.num_ports; + rdev->ib_dev.num_comp_vectors = + (rdev->rdma_cap.num_comp_vectors <= MAX_CEQ_NEED) ? (int)rdev->rdma_cap.num_comp_vectors : MAX_CEQ_NEED; + rdev->ib_dev.dma_device = &rdev->pdev->dev; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + rdev->ib_dev.dev.parent = rdev->ib_dev.dma_device; +#endif + rdev->ib_dev.uverbs_abi_ver = ROCE_IB_UVERBS_ABI_VERSION; + rdev->ib_dev.node_guid = roce3_rdma_init_guid(rdev->hwdev, rdev->ndev); + memcpy((void *)rdev->ib_dev.node_desc, "hrn3", ROCE_NODE_DESC_LEN); + + rdev->ib_dev.uverbs_cmd_mask = ROCE_UVERBS_CMD_MASK; + rdev->ib_dev.uverbs_ex_cmd_mask = ROCE_UVERBS_EXT_CMD_MASK; + + roce3_init_dev_handlers(rdev); + roce3_init_dev_ext_handlers(rdev); + return; +} +#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + +static void roce3_mod_param_parse(struct roce3_device *rdev) +{ + rdev->try_times = g_loop_times; + +#ifdef ROCE_BONDING_EN + if (g_bond_name != NULL) { + rdev->want_bond_slave_cnt = SDI_BOND_SUPPORT_ROCE_FUNC_CNT; + rdev->want_bond_slave_bits[0] = SDI_BOND_SUPPORT_ROCE_FUNC_BIT; + rdev->want_bond_slave_bits[1] = 0; + rdev->sdi_bond_name = g_bond_name; + return; + } + rdev->want_bond_slave_cnt = g_want_bond_slave_cnt; + rdev->want_bond_slave_bits[0] = g_want_bond0_slave_bits; + rdev->want_bond_slave_bits[1] = 0; + rdev->sdi_bond_name = NULL; +#endif + + return; +} + +static void *roce3_get_ppf_lld_dev(struct roce3_device *rdev) +{ + struct hinic3_lld_dev *ppf_lld_dev = NULL; + + ppf_lld_dev = hinic3_get_ppf_lld_dev_unsafe(rdev->lld_dev); + if (!ppf_lld_dev) { + pr_err("[ROCE, ERR] %s: Failed to get ppf lld_dev\n", __func__); + return ERR_PTR(-EINVAL); + } + + return ppf_lld_dev->hwdev; +} + +static int roce3_rdev_init(struct roce3_device *rdev) +{ + int ret; + void *ppf_hwdev = NULL; + + if (!hinic3_is_vm_slave_host(rdev->hwdev)) { + if ((hinic3_func_type(rdev->hwdev) == TYPE_VF) && (g_ppf_stateful_init == false) && (g_vf_stateful_num == 0)) { + ppf_hwdev = roce3_get_ppf_lld_dev(rdev); + ret = hinic3_stateful_init(ppf_hwdev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to init ppf stateful resource\n", __func__); + return ret; + } + } + + if (hinic3_func_type(rdev->hwdev) == TYPE_PPF) { + g_ppf_stateful_init = true; + } + } + + // BM:When the device is PPF, stateful_init is performed only when g_vf_stateful_num is 0. + if (hinic3_is_vm_slave_host(rdev->hwdev) || (hinic3_func_type(rdev->hwdev) != TYPE_PPF) || !g_vf_stateful_num) { + ret = hinic3_stateful_init(rdev->hwdev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to init stateful resource\n", __func__); + goto err_stateful_init; + } + } + + ret = roce3_add_rdev_init(rdev); + if (ret != 0) { + goto err_rdev_init; + } + + /*lint -e708*/ + spin_lock_init(&rdev->node_desc_lock); + /*lint +e708*/ + + mutex_init(&rdev->cap_mask_mutex); + INIT_LIST_HEAD(&rdev->mac_vlan_list_head); + mutex_init(&rdev->mac_vlan_mutex); + /*lint -e708*/ + spin_lock_init(&rdev->reset_flow_resource_lock); + /*lint +e708*/ + INIT_LIST_HEAD(&rdev->qp_list); + roce3_mod_param_parse(rdev); + + roce3_fix_ibdev_name(rdev); + + if (hinic3_func_type(rdev->hwdev) == TYPE_VF) { + g_vf_stateful_num++; + } + + return 0; + +err_rdev_init: + hinic3_stateful_deinit(rdev->hwdev); +err_stateful_init: + if ((g_vf_stateful_num == 0) && (g_ppf_stateful_init == false)) { + hinic3_stateful_deinit(ppf_hwdev); + } + return ret; +} + +static void roce3_stateful_unit(struct roce3_device *rdev) +{ + void *ppf_hwdev = NULL; + + if (!hinic3_is_vm_slave_host(rdev->hwdev)) { + if (hinic3_func_type(rdev->hwdev) == TYPE_VF) { + hinic3_stateful_deinit(rdev->hwdev); + g_vf_stateful_num--; + if ((g_vf_stateful_num == 0) && (g_ppf_stateful_init == false)) { // Delete the last VF when no PF is added + ppf_hwdev = roce3_get_ppf_lld_dev(rdev); + hinic3_stateful_deinit(ppf_hwdev); + } + } else { + if (g_vf_stateful_num == 0) { + hinic3_stateful_deinit(rdev->hwdev); + } + } + } else { + hinic3_stateful_deinit(rdev->hwdev); + } +} + +#ifdef ROCE_NETLINK_EN +static void roce3_adapt_unit(struct roce3_device *rdev) +{ + hiroce_netlink_dev_s *adp_dev; + int offset = 0; + + offset = get_instance_of_func_id(rdev->glb_func_id); + if (offset >= MAX_FUNCTION_NUM) { + pr_err("[ROCE, ERR] %s: offset is over size\n", __func__); + return; + } + adp_dev = hiroce_get_adp(); + mutex_lock(&adp_dev->mutex_dev); + adp_dev->used_dev_num--; + + if (adp_dev->used_dev_num <= 0 && adp_dev->netlink) { + kfree(adp_dev->netlink); + } + mutex_unlock(&adp_dev->mutex_dev); +} +#endif + +static void roce3_rdev_unit(struct roce3_device *rdev) +{ + /* FLR by MPU when hotplug, don't need deinit anymore */ + if (hinic3_func_type(rdev->hwdev) == TYPE_PPF) { + g_ppf_stateful_init = false; + } + + if (roce3_hca_is_present(rdev) != 0) { + roce3_stateful_unit(rdev); + } + +#ifdef ROCE_NETLINK_EN + roce3_netlink_unit(); + roce3_adapt_unit(rdev); +#endif + roce3_add_rdev_unit(rdev); +} + +#ifdef ROCE_NETLINK_EN +static int roce3_adapt_init(struct roce3_device *rdev) +{ + int offset = 0; + hiroce_netlink_dev_s *adp_dev = NULL; + + offset = get_instance_of_func_id(rdev->glb_func_id); + if (offset >= ROCE_MAX_FUNCTION) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get offset , func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + adp_dev = hiroce_get_adp(); + mutex_lock(&adp_dev->mutex_dev); + if (adp_dev->used_dev_num == 0 && adp_dev->netlink == NULL) { + adp_dev->netlink = kzalloc(sizeof(netlink_dev_s), GFP_KERNEL); + if (adp_dev->netlink == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR]%s, Fail to alloc netlink\n", __func__); + mutex_unlock(&adp_dev->mutex_dev); + return -EINVAL; + } + } + + adp_dev->used_dev_num++; + mutex_unlock(&adp_dev->mutex_dev); + adp_dev->netlink->rdev[offset] = rdev; + + return 0; +} +#endif + +static int roce3_add_do_init(struct roce3_device *rdev, char *uld_dev_name) +{ + int ret; + + ret = roce3_rdev_init(rdev); + if (ret != 0) { + goto err_init_rdev; + } + + ret = roce3_register_template(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to register cqm_service, func_id(%hu) ret(%d)\n", __func__, + rdev->glb_func_id, ret); + goto err_cqm_register; + } + + ret = hinic3_alloc_db_addr(rdev->hwdev, &rdev->kernel_db_map, &rdev->kernel_dwqe_map); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc db or dwqe, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_alloc_db; + } + + roce3_add_init(rdev); + + ret = roce3_alloc_ceq(rdev); + if (ret < 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR]: Failed to alloc ceqs, func_id(%hu)\n", rdev->glb_func_id); + goto err_alloc_ceq; + } + + ret = roce3_init_dev(rdev, uld_dev_name); + if (ret != 0) { + goto err_init_dev; + } + +#ifdef ROCE_NETLINK_EN + ret = roce3_adapt_init(rdev); + if (ret != 0) { + goto err_init_adp; + } + + roce3_netlink_init(); + + return 0; +err_init_adp: + roce3_adapt_unit(rdev); +#else + return 0; +#endif + +err_init_dev: + roce3_free_ceq(rdev); + +err_alloc_ceq: + hinic3_free_db_addr(rdev->hwdev, rdev->kernel_db_map, rdev->kernel_dwqe_map); + +err_alloc_db: + cqm_service_unregister(rdev->hwdev, SERVICE_T_ROCE); + +err_cqm_register: + roce3_rdev_unit(rdev); + +err_init_rdev: + roce3_remove_device_from_list(rdev->lld_dev); + return ret; +} + +#ifndef ROCE_VROCE_EN +static bool is_device_v100(const struct hinic3_lld_dev *lld_dev) +{ + struct pci_dev *pdev = lld_dev->pdev; + unsigned short ssdid = pdev->subsystem_device; + + return (ssdid == HINIC3_DEV_SSID_2X25G) || (ssdid == HINIC3_DEV_SSID_4X25G) || (ssdid == HINIC3_DEV_SSID_2X100G); +} +#else +static bool pci_support_vroce(const struct hinic3_lld_dev *lld_dev) +{ + struct pci_dev *pdev = lld_dev->pdev; + unsigned short ssdid = pdev->subsystem_device; + + if (hinic3_func_type(lld_dev->hwdev) == TYPE_VF) { + if (ssdid == HINIC3_DEV_SDI_5_1_SSDID_VF) + return true; + } else { // PF or PPF + if ((ssdid & HINIC3_DEV_SDI_V100_SSDID_MASK) == 0) + return true; + } + + return false; +} +#endif + +static int roce3_add_check(const struct hinic3_lld_dev *lld_dev) +{ + int ret = 0; + u16 func_id; + u8 enable_roce = false; + bool is_slave_func = false; + + if (lld_dev == NULL) { + pr_err("[ROCE, ERR] %s: Lld_dev is null\n", __func__); + return (-EINVAL); + } + +#ifndef ROCE_VROCE_EN + if (!is_device_v100(lld_dev)) { + pr_err("[ROCE, ERR] %s: ssdid 0x%x is NOT standard Card\n", __func__, lld_dev->pdev->subsystem_device); + return -ENXIO; + } +#endif + + ret = hinic3_is_slave_func(lld_dev->hwdev, &is_slave_func); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get slave_func.\n", __func__); + } + if (!is_slave_func) { + return 0; + } + +#ifdef ROCE_VROCE_EN + if (!pci_support_vroce(lld_dev)) { + pr_err("[ROCE, ERR] Pcidev ssdid %x doesn't support vroce, please change driver.\n", + lld_dev->pdev->subsystem_device); + return -EFAULT; + } +#endif + + func_id = hinic3_global_func_id(lld_dev->hwdev); + ret = hinic3_get_func_vroce_enable(lld_dev->hwdev, func_id, &enable_roce); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get roce state.\n", __func__); + return ret; + } + if (!enable_roce) { + pr_warn("[ROCE] %s: %s RoCE dev is not enable, func: %hu\n", __func__, + pci_name(lld_dev->pdev), func_id); + return (-EPERM); + } + + return 0; +} + +static void roce3_remove_device_from_list(struct hinic3_lld_dev *lld_dev) +{ + struct roce3_func_info *info; + struct roce3_func_info *tmp; + + if (list_empty(&g_roce_device_list)) { + return; + } + + list_for_each_entry_safe(info, tmp, &g_roce_device_list, node) { + if (info->func_id == hinic3_global_func_id(lld_dev->hwdev)) { + list_del(&info->node); + kfree(info); + } + } + + wake_up(&g_roce_probe_queue); + return; +} + +static int roce3_add_device_to_list(struct hinic3_lld_dev *lld_dev) +{ + struct roce3_func_info *info = (struct roce3_func_info *)kzalloc(sizeof(struct roce3_func_info), GFP_ATOMIC); + if (info == NULL) { + pr_err("[ROCE, ERR] %s: no memory\n", __func__); + return -ENOMEM; + } + + info->func_id = hinic3_global_func_id(lld_dev->hwdev); + list_add_tail(&info->node, &g_roce_device_list); + + return 0; +} + +static void roce3_wait_probe(struct hinic3_lld_dev *lld_dev) +{ + struct roce3_func_info *info = NULL; + bool wait_flg = false; + DECLARE_WAITQUEUE(wait_queue, current); + + add_wait_queue(&g_roce_probe_queue, &wait_queue); + pr_info("[ROCE] %s func %hu start to wait\n", __func__, hinic3_global_func_id(lld_dev->hwdev)); + + do { + might_sleep(); + info = list_first_entry(&g_roce_device_list, struct roce3_func_info, node); + wait_flg = (info->func_id == hinic3_global_func_id(lld_dev->hwdev)) ? true : false; + if (!wait_flg) { + set_current_state(TASK_INTERRUPTIBLE); + schedule(); + if (signal_pending(current)) { /* if alarmed by signal */ + goto out; + } + } + } while (!wait_flg); + + set_current_state(TASK_RUNNING); + remove_wait_queue(&g_roce_probe_queue, &wait_queue); + + pr_info("[ROCE] %s func %hu wait finished\n", __func__, hinic3_global_func_id(lld_dev->hwdev)); + return; +out: + pr_info("[ROCE] %s func %hu wait fail\n", __func__, hinic3_global_func_id(lld_dev->hwdev)); + remove_wait_queue(&g_roce_probe_queue, &wait_queue); + set_current_state(TASK_RUNNING); + return; +} + +/* **************************************************************************** + Prototype : roce3_add + Description : roce3_add + Input : struct hinic_lld_dev *lld_dev + void **uld_dev + char *uld_dev_name + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_add(struct hinic3_lld_dev *lld_dev, void **uld_dev, char *uld_dev_name) +{ + struct roce3_device *rdev = NULL; + struct rdma_service_cap rdma_cap; + int ret = 0; + + ret = roce3_add_check(lld_dev); + if (ret != 0) { + goto err_check; + } + + pr_info("[ROCE] %s: Initializing pci(%s)\n", __func__, pci_name(lld_dev->pdev)); + + /* return 0 if the rdev don't support ROCE, make sure it probe success */ + if (!hinic3_support_roce(lld_dev->hwdev, &rdma_cap)) { + pr_err("[ROCE, ERR] %s: %s Not support RoCE, func: %hu\n", __func__, pci_name(lld_dev->pdev), + hinic3_global_func_id(lld_dev->hwdev)); + goto err_check; + } + + /* make sure roce device probe in order */ + ret = roce3_add_device_to_list(lld_dev); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to add device to list, ret: %d, func: %hu\n", __func__, + ret, hinic3_global_func_id(lld_dev->hwdev)); + return ret; + } + + roce3_rdma_cap_ext(&rdma_cap); + + rdev = roce3_rdev_alloc(lld_dev, uld_dev, &rdma_cap); + if (rdev == NULL) { + roce3_remove_device_from_list(lld_dev); + pr_err("[ROCE, ERR] %s: Failed to alloc rdev, func: %hu\n", __func__, hinic3_global_func_id(lld_dev->hwdev)); + return -EINVAL; + } + + ret = roce3_add_do_init(rdev, uld_dev_name); + if (ret != 0) { + goto err_do_init; + } + + return 0; + +err_do_init: + ib_dealloc_device(&rdev->ib_dev); +err_check: + *uld_dev = NULL; + return ret; +} + +static void roce3_do_remove(struct roce3_device *rdev, u16 glb_func_id, const char *dev_name) +{ + roce3_remove_dev_file(rdev); + + roce3_unregister_netdev_event(rdev); + + if (roce3_hca_is_present(rdev) == 0) { + roce3_handle_hotplug_arm_cq(rdev); + roce3_kernel_hotplug_event_trigger(rdev); + } + + ib_unregister_device(&rdev->ib_dev); + pr_info("[ROCE] %s: Unregister IB device ok, func_id(%hu), name(%s), pci(%s)\n", __func__, glb_func_id, dev_name, + pci_name(rdev->pdev)); + + roce3_dealloc_hw_resource(rdev); + + roce3_deinit_dev_info(rdev); + +#ifdef ROCE_BONDING_EN + roce3_set_bond_ipsurx_en(true); +#endif + + roce3_clean_vlan_device_mac(rdev); + roce3_clean_real_device_mac(rdev); + + roce3_free_ceq(rdev); + + hinic3_free_db_addr(rdev->hwdev, rdev->kernel_db_map, rdev->kernel_dwqe_map); + + cqm_service_unregister(rdev->hwdev, SERVICE_T_ROCE); + + roce3_del_func_res(rdev); + pr_info("[ROCE] %s: Function level resource clear ok, func_id(%hu), name(%s), pci(%s)\n", __func__, glb_func_id, + dev_name, pci_name(rdev->pdev)); + + roce3_do_cache_out(rdev->hwdev, ROCE_CL_TYPE_CQC_SRQC, rdev->glb_func_id); + + roce3_rdev_unit(rdev); + pr_info("[ROCE] %s: RoCE rdev uninit ok, func_id(%hu), name(%s)\n", __func__, glb_func_id, dev_name); + + ib_dealloc_device(&rdev->ib_dev); +} + +static int roce3_remove_check(const struct hinic3_lld_dev *lld_dev, const void *uld_dev) +{ + if ((uld_dev == NULL) || (lld_dev == NULL)) { + pr_err("[ROCE, ERR] %s: input param is null\n", __func__); + return (-EINVAL); + } + + return 0; +} + +static void roce3_remove(struct hinic3_lld_dev *lld_dev, void *uld_dev) +{ + struct roce3_device *rdev = NULL; + char *dev_name = NULL; + u16 glb_func_id; + int ret; + + ret = roce3_remove_check(lld_dev, uld_dev); + if (ret != 0) { + return; + } + + rdev = (struct roce3_device *)uld_dev; + rdev->ib_active = false; + dev_name = rdev->ib_dev.name; + glb_func_id = rdev->glb_func_id; + + if (!hinic3_support_roce(rdev->hwdev, NULL)) { + pr_err("[ROCE, ERR] %s: Not support RoCE\n", __func__); + return; + } + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: RoCE remove start, func_id(%hu), name(%s), pci(%s)\n", __func__, + rdev->glb_func_id, dev_name, pci_name(rdev->pdev)); + + roce3_do_remove(rdev, glb_func_id, dev_name); + + pr_info("[ROCE] %s: RoCE remove end, func_id(%hu), name(%s)\n", __func__, glb_func_id, dev_name); + return; +} + +bool roce3_need_proc_link_event(void *hwdev) +{ + int ret = 0; + u16 func_id; + u8 roce_enable = false; + bool is_slave_func = false; + struct hinic3_hw_bond_infos hw_bond_infos = {0}; + + ret = hinic3_is_slave_func(hwdev, &is_slave_func); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: lld_dev is null\n", __func__); + return true; + } + + if (!is_slave_func) { + return true; + } + + func_id = hinic3_global_func_id(hwdev); + ret = hinic3_get_func_vroce_enable(hwdev, func_id, &roce_enable); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get vroce info\n", __func__); + return true; + } + if (!roce_enable) { + return true; + } + + hw_bond_infos.bond_id = HINIC_OVS_BOND_DEFAULT_ID; + + ret = hinic3_get_hw_bond_infos(hwdev, &hw_bond_infos, HINIC3_CHANNEL_COMM); + if (ret != 0) { + pr_err("[ROCE, ERR] Get chipf bond info failed (%d)\n", ret); + return true; + } + + if (!hw_bond_infos.valid) { + return true; + } + + return false; +} + +bool roce3_need_proc_bond_event(void *hwdev) +{ + return !roce3_need_proc_link_event(hwdev); +} + +static int roce3_proc_bond_status_change(struct roce3_device *rdev, + const struct hinic3_event_info *event) +{ + switch (event->type) { + case EVENT_NIC_BOND_UP: + if (!roce3_need_proc_bond_event(rdev->hwdev)) { + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE don't need proc bond event\n", __func__); + return -1; + } + if (test_and_set_bit(ROCE3_PORT_EVENT, &rdev->status) != 0) { + return -1; + } + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE report NIC BOND_UP, func_id(%u)\n", __func__, + rdev->glb_func_id); + return IB_EVENT_PORT_ACTIVE; + + case EVENT_NIC_BOND_DOWN: + if (!roce3_need_proc_bond_event(rdev->hwdev)) { + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE don't need proc bond event\n", __func__); + return -1; + } + + if (test_and_clear_bit(ROCE3_PORT_EVENT, &rdev->status) == 0) { + return -1; + } + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE report NIC BOND_DOWN, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return IB_EVENT_PORT_ERR; + + default: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Nic event unsupported, func_id(%hu), event(%hu)\n", __func__, + rdev->glb_func_id, event->type); + return -1; + } +} + +static int roce3_set_nic_event(struct roce3_device *rdev, + const struct hinic3_event_info *event) +{ + switch (event->type) { + case EVENT_NIC_LINK_UP: + if (test_and_set_bit(ROCE3_PORT_EVENT, &rdev->status) != 0) { + return -1; + } + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE report NIC LINK_UP, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return IB_EVENT_PORT_ACTIVE; + + case EVENT_NIC_LINK_DOWN: + if (!roce3_need_proc_link_event(rdev->hwdev)) { + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE don't need proc link event\n", __func__); + return -1; + } + + if (test_and_clear_bit(ROCE3_PORT_EVENT, &rdev->status) == 0) { + return -1; + } + dev_info(rdev->hwdev_hdl, "[ROCE, WARN] %s: RoCE report NIC LINK_DOWN, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return IB_EVENT_PORT_ERR; + + case EVENT_NIC_BOND_UP: + case EVENT_NIC_BOND_DOWN: + return roce3_proc_bond_status_change(rdev, event); + + case EVENT_NIC_DCB_STATE_CHANGE: + dev_info(rdev->hwdev_hdl, "[ROCE]%s: DCB state change no longer requires RoCE involvement, func_id(%hu)\n", + __func__, rdev->glb_func_id); + return -1; + + default: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Nic event unsupported, func_id(%hu), event(%hu)\n", __func__, + rdev->glb_func_id, event->type); + return -1; + } +} + +static int roce3_set_ib_event(struct roce3_device *rdev, const struct hinic3_event_info *event) +{ + switch (event->service) { + case EVENT_SRV_NIC: + return roce3_set_nic_event(rdev, event); + + case EVENT_SRV_COMM: + return roce3_set_comm_event(rdev, event); + + default: + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: func_id(%hu) event from svc(%hu) is not supported, event(%hu)\n", + __func__, rdev->glb_func_id, event->service, event->type); + return -1; + } +} + +void roce3_event(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct hinic3_event_info *event) +{ + struct ib_event ibevent; + struct roce3_device *rdev = NULL; + int type; + int ret = 0; + + roce3_lock_rdev(); + + ret = roce3_get_rdev_by_uld(lld_dev, uld_dev, &rdev, event); + if (ret != 0) { + pr_err("[ROCE] %s: find rdev failed, ret(%d)\n", __func__, ret); + goto err_unlock; + } +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + roce3_handle_bonded_port_state_event(rdev); + goto err_unlock; + } +#endif + type = roce3_set_ib_event(rdev, event); + if (type == -1) { + goto err_unlock; + } + + ibevent.event = (enum ib_event_type)type; + ibevent.device = &rdev->ib_dev; + ibevent.element.port_num = ROCE_DEFAULT_PORT_NUM; + + if (rdev->ib_active) { + ib_dispatch_event(&ibevent); + } + +err_unlock: + roce3_unlock_rdev(); + return; +} + +typedef int (*roce3_adm_func_t)(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, + u32 *out_size); + +/*lint -e26*/ +static roce3_adm_func_t g_roce3_adm_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [COMMON_CMD_GET_DRV_VERSION] = roce3_get_drv_version, + +#ifdef __ROCE_DFX__ + [ROCE_CMD_GET_QPC_FROM_CACHE] = roce3_adm_dfx_query, + [ROCE_CMD_GET_QPC_FROM_HOST] = roce3_adm_dfx_query, + [ROCE_CMD_GET_CQC_FROM_CACHE] = roce3_adm_dfx_query, + [ROCE_CMD_GET_CQC_FROM_HOST] = roce3_adm_dfx_query, + [ROCE_CMD_GET_SRQC_FROM_CACHE] = roce3_adm_dfx_query, + [ROCE_CMD_GET_SRQC_FROM_HOST] = roce3_adm_dfx_query, + [ROCE_CMD_GET_MPT_FROM_CACHE] = roce3_adm_dfx_query, + [ROCE_CMD_GET_MPT_FROM_HOST] = roce3_adm_dfx_query, + [ROCE_CMD_GET_GID_FROM_CACHE] = roce3_adm_dfx_query, + [ROCE_CMD_GET_QPC_CQC_PI_CI] = roce3_adm_dfx_query, + [ROCE_CMD_GET_QP_COUNT] = roce3_adm_dfx_query, + [ROCE_CMD_GET_DEV_ALGO] = roce3_adm_dfx_query, +#ifdef ROCE_PKT_CAP_EN + [ROCE_CMD_START_CAP_PACKET] = roce3_adm_dfx_capture, + [ROCE_CMD_STOP_CAP_PACKET] = roce3_adm_dfx_capture, + [ROCE_CMD_QUERY_CAP_INFO] = roce3_adm_dfx_capture, + [ROCE_CMD_ENABLE_QP_CAP_PACKET] = roce3_adm_dfx_capture, + [ROCE_CMD_DISABLE_QP_CAP_PACKET] = roce3_adm_dfx_capture, + [ROCE_CMD_QUERY_QP_CAP_INFO] = roce3_adm_dfx_capture, +#endif /* ROCE_PKT_CAP_EN */ +#endif /* __ROCE_DFX__ */ + + [ROCE_CMD_ENABLE_BW_CTRL] = roce3_adm_dfx_bw_ctrl, + [ROCE_CMD_DISABLE_BW_CTRL] = roce3_adm_dfx_bw_ctrl, + [ROCE_CMD_CHANGE_BW_CTRL_PARAM] = roce3_adm_dfx_bw_ctrl, + [ROCE_CMD_QUERY_BW_CTRL_PARAM] = roce3_adm_dfx_bw_ctrl, +}; +/*lint +e26*/ + +static int roce3_adm(void *uld_dev, u32 cmd, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct roce3_device *rdev = (struct roce3_device *)uld_dev; + roce3_adm_func_t roce3_adm_func; + + if (uld_dev == NULL || buf_in == NULL || buf_out == NULL || out_size == NULL) { + pr_err("[ROCE] %s: Input params is null\n", __func__); + return -EINVAL; + } + + if (!hinic3_support_roce(rdev->hwdev, NULL)) { + pr_err("[ROCE, ERR] %s: %s Not support RoCE\n", __func__, pci_name(rdev->pdev)); + return -EINVAL; + } + + rdev = (struct roce3_device *)uld_dev; + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if (cmd >= COMMON_CMD_VM_COMPAT_TEST) { + dev_err(rdev->hwdev_hdl, "Not support this type(%u)", cmd); + return -EINVAL; + } + + roce3_adm_func = g_roce3_adm_funcs[cmd]; + if (roce3_adm_func == NULL) { + dev_err(rdev->hwdev_hdl, "Not support this type(%u)", cmd); + return -EINVAL; + } + + return roce3_adm_func(rdev, buf_in, in_size, buf_out, out_size); +} + +struct hinic3_uld_info roce3_info = { + .probe = roce3_add, + .remove = roce3_remove, + .suspend = NULL, + .resume = NULL, + .event = roce3_event, + .ioctl = roce3_adm, +}; + +struct hinic3_uld_info *roce3_info_get(void) +{ + return &roce3_info; +} + +/* **************************************************************************** + Prototype : roce3_service_init + Description : + Input : void + Output : None + Return Value : + Calls : + Called By : + + History : + 1.Date : 2015/5/27 + Author : + Modification : Created function + +**************************************************************************** */ +static int __init roce3_service_init(void) +{ + int ret; + + INIT_LIST_HEAD(&g_roce_device_list); + init_waitqueue_head(&g_roce_probe_queue); + roce3_service_init_pre(); +#ifdef ROCE_NETLINK_EN + /* init mutex */ + mutex_init(&hiroce_get_adp()->mutex_dev); +#endif + ret = hinic3_register_uld(SERVICE_T_ROCE, roce3_info_get()); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to register uld. ret(%d)\n", __func__, ret); + return ret; + } + + roce3_service_init_ext(); +#ifdef ROCE_BONDING_EN + ret = roce3_bond_init(); +#endif + pr_info("[ROCE] %s: Register roce service done, ret(%d).\n", __func__, ret); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_service_exit + Description : roce service disable + Input : void + Output : None + Return Value : + Calls : + Called By : + + History : + 1.Date : 2015/5/27 + Author : + Modification : Created function + +**************************************************************************** */ +static void __exit roce3_service_exit(void) +{ +#ifdef ROCE_BONDING_EN + roce3_bond_pre_exit(); +#endif + hinic3_unregister_uld(SERVICE_T_ROCE); + +#ifdef ROCE_BONDING_EN + pr_info("[ROCE] %s: Bond remove all.\n", __func__); + roce3_bond_exit(); +#endif + + pr_info("[ROCE] %s: Unregister roce service successful\n", __func__); +} + +bool roce3_is_roceaa(u8 scence_id) +{ + if ((scence_id == SCENES_ID_STORAGE_ROCEAA_2x100) || (scence_id == SCENES_ID_STORAGE_ROCEAA_4x25)) { + return true; + } + + return false; +} + +module_init(roce3_service_init); +module_exit(roce3_service_exit); diff --git a/drivers/infiniband/hw/hiroce3/roce_mix.c b/drivers/infiniband/hw/hiroce3/roce_mix.c new file mode 100755 index 000000000..1a7eb5a64 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_mix.c @@ -0,0 +1,1402 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mix.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of callback functions and internal functions of RoCE mix features. + */ + +#include <rdma/ib_mad.h> +#include <rdma/ib_verbs.h> +#include <linux/pci.h> + +#include <rdma/ib_addr.h> +#include <rdma/ib_cache.h> + +#include "hinic3_crm.h" +#include "hinic3_srv_nic.h" + +#include "roce.h" +#include "roce_compat.h" +#include "roce_user.h" +#include "roce_pd.h" +#include "roce_qp.h" +#include "roce_cmd.h" +#include "roce_netdev.h" +#include "roce_main_extension.h" +#include "roce_pub_cmd.h" + +#include "roce_mix.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#ifdef OFED_MLNX_5_8 +struct net_device *roce3_ib_get_netdev(struct ib_device *ibdev, u32 port_num) +#else +struct net_device *roce3_ib_get_netdev(struct ib_device *ibdev, u8 port_num) +#endif +{ + struct roce3_device *rdev = NULL; + struct net_device *netdev = NULL; + + if (ibdev == NULL) { + pr_err("[ROCE] %s: Ibdev is null \n", __func__); + return NULL; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + pr_err("[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, rdev->glb_func_id); + return NULL; + } + +#ifdef ROCE_BONDING_EN + netdev = roce3_bond_get_netdev(rdev); + if (netdev != NULL) { + return netdev; + } +#endif + + netdev = rdev->ndev; + + dev_hold(netdev); + + return netdev; +} + +static void roce3_parse_fw_version(struct roce3_device *rdev, u64 *fw_ver) +{ + int ret; + int i = 0; + struct hinic3_fw_version fw_version; + char *fw_str = (char *)fw_version.microcode_ver; + char *fw_temp = NULL; + u64 fw_verion[ROCE_FW_VERSION_LEN] = {0}; + + ret = hinic3_get_fw_version(rdev->hwdev, &fw_version, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + pr_warn("[ROCE] %s: get fw version failed\n", __func__); + *fw_ver = ROCE_FW_VER; + return; + } + pr_info("[ROCE] %s: fw ver:%s - %s - %s\n", __func__, fw_version.boot_ver, fw_version.mgmt_ver, + fw_version.microcode_ver); + + while (((fw_temp = strsep(&fw_str, ".")) != NULL) && (i < ROCE_FW_VERSION_LEN)) { + ret = sscanf(fw_temp, "%llu", &fw_verion[i]); + if (ret != 1) { + pr_warn("[ROCE] %s: parse fw version failed\n", __func__); + *fw_ver = ROCE_FW_VER; + return; + } + + i++; + } + + *fw_ver = (((fw_verion[0] & 0xffffffff) << 32) | // 0 is fw_version array idx, 32 is offset + ((fw_verion[1] & 0xffff) << 16) | // 1 is fw_version array idx, 16 is offset + ((fw_verion[2] & 0xff) << 8) | // 2 is fw_version array idx, 8 is offset + (fw_verion[3] & 0xff)); // 3 is fw_version array idx +} + +static void roce3_set_local_cap_flag(const struct rdma_service_cap *rdma_cap, struct ib_device_attr *props) +{ + if (((rdma_cap->flags & RDMA_BMME_FLAG_LOCAL_INV) != 0) && ((rdma_cap->flags & RDMA_BMME_FLAG_REMOTE_INV) != 0) && + ((rdma_cap->flags & RDMA_BMME_FLAG_FAST_REG_WR) != 0)) { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_MEM_MGT_EXTENSIONS; + } +} + +static void roce3_set_bmme_cap_flag(const struct rdma_service_cap *rdma_cap, struct ib_device_attr *props) +{ + if ((rdma_cap->flags & RDMA_BMME_FLAG_TYPE_2_WIN) != 0) { + if ((rdma_cap->flags & RDMA_BMME_FLAG_WIN_TYPE_2B) != 0) { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_MEM_WINDOW_TYPE_2B; + } else { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_MEM_WINDOW_TYPE_2A; + } + } +} + +static void roce3_query_device_props_set(struct roce3_device *rdev, struct rdma_service_cap *rdma_cap, + struct ib_device_attr *props) +{ + props->vendor_id = rdev->pdev->vendor; + props->vendor_part_id = rdev->pdev->device; + roce3_parse_fw_version(rdev, &props->fw_ver); + props->hw_ver = ROCE_HW_VER; + + /* sys_image_guid equal GID */ + props->sys_image_guid = rdev->ib_dev.node_guid; + + props->max_mr_size = ~0ULL; + props->page_size_cap = rdma_cap->page_size_cap; + props->max_qp = (int)(rdma_cap->dev_rdma_cap.roce_own_cap.max_qps - rdma_cap->reserved_qps); + props->max_qp_wr = (int)rdma_cap->dev_rdma_cap.roce_own_cap.max_wqes; + /* + * 4.19 ofed will return the smaller of sq/rq sge num to user space. + * 4.17 We use max_sge to only represent max sq sge num, max_rq_sge is a fixed macro of 16. + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) + props->max_send_sge = rdma_cap->max_sq_sg; + props->max_recv_sge = rdma_cap->dev_rdma_cap.roce_own_cap.max_rq_sg; +#else + props->max_sge = (int)rdma_cap->max_sq_sg; +#endif + props->max_cq = (int)(rdma_cap->dev_rdma_cap.roce_own_cap.max_cqs - rdma_cap->reserved_cqs); + props->max_cqe = (int)rdma_cap->max_cqes; + + if ((rdev->board_info.port_num == ROCE_PORT_NUM_2) && (rdev->board_info.port_speed == ROCE_25G_PORT_SPEED)) { + // 2 smf for 64B cache + props->max_mr = (int)(rdma_cap->dev_rdma_cap.roce_own_cap.max_mpts - rdma_cap->reserved_mrws) / MEND_CAP_DEVIDE; + props->max_srq = + (int)(rdma_cap->dev_rdma_cap.roce_own_cap.max_srqs - rdma_cap->dev_rdma_cap.roce_own_cap.reserved_srqs) / + MEND_CAP_DEVIDE; + } else { + props->max_mr = (int)(rdma_cap->dev_rdma_cap.roce_own_cap.max_mpts - rdma_cap->reserved_mrws); + props->max_srq = + (int)(rdma_cap->dev_rdma_cap.roce_own_cap.max_srqs - rdma_cap->dev_rdma_cap.roce_own_cap.reserved_srqs); + } + + props->max_mw = props->max_mr; + props->max_pd = (int)(rdma_cap->num_pds - rdma_cap->reserved_pds); + props->max_qp_rd_atom = (int)rdma_cap->dev_rdma_cap.roce_own_cap.max_qp_dest_rdma; + props->max_qp_init_rd_atom = (int)rdma_cap->dev_rdma_cap.roce_own_cap.max_qp_init_rdma; + props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; + + props->max_srq_wr = (int)rdma_cap->dev_rdma_cap.roce_own_cap.max_srq_wqes; + props->max_srq_sge = (int)rdma_cap->dev_rdma_cap.roce_own_cap.max_srq_sge; + props->max_fast_reg_page_list_len = rdma_cap->max_frpl_len; + props->local_ca_ack_delay = (u8)rdma_cap->local_ca_ack_delay; + props->atomic_cap = ((rdma_cap->flags & RDMA_DEV_CAP_FLAG_ATOMIC) != 0) ? IB_ATOMIC_HCA : IB_ATOMIC_NONE; + props->masked_atomic_cap = props->atomic_cap; + props->max_pkeys = (u16)rdma_cap->max_pkeys; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +#ifdef ROCE_COMPUTE + props->max_map_per_fmr = 0; +#else + props->max_map_per_fmr = (int)rdma_cap->max_fmr_maps; +#endif + props->max_fmr = props->max_map_per_fmr; +#endif + props->max_ah = INT_MAX; + return; +} +/* **************************************************************************** + Prototype : roce3_query_device + Description : query device attribute + Input : struct ib_device *ibdev + struct ib_device_attr *props + struct ib_udata *uhw + Output : struct ib_device_attr *props + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +int roce3_query_device(struct ib_device *ibdev, struct ib_device_attr *props, struct ib_udata *uhw) +{ + struct roce3_device *rdev = NULL; + struct rdma_service_cap *rdma_cap = NULL; + + if ((ibdev == NULL) || (props == NULL)) { + pr_err("[ROCE] %s: Ibdev or props is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + memset(props, 0, sizeof(*props)); + + rdma_cap = &rdev->rdma_cap; + + props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_RC_RNR_NAK_GEN; + + /* APM */ + if ((rdma_cap->flags & RDMA_DEV_CAP_FLAG_APM) != 0) { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_AUTO_PATH_MIG; + } + + /* rsvd_lKey */ + if ((rdma_cap->flags & RDMA_BMME_FLAG_RESERVED_LKEY) != 0) { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_LOCAL_DMA_LKEY; + } + + roce3_set_local_cap_flag(rdma_cap, props); + +#ifndef ROCE_COMPUTE + /* support XRC */ + if ((rdma_cap->flags & RDMA_DEV_CAP_FLAG_XRC) != 0) { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_XRC; + } +#endif + + /* support MW */ + if ((rdma_cap->flags & RDMA_DEV_CAP_FLAG_MEM_WINDOW) != 0) { + props->device_cap_flags = props->device_cap_flags | IB_DEVICE_MEM_WINDOW; + } + + roce3_set_bmme_cap_flag(rdma_cap, props); + + roce3_query_device_props_set(rdev, rdma_cap, props); + return 0; +} + +static void eth_link_get_speed(struct ib_port_attr *props, enum mag_cmd_port_speed speed) +{ + switch (speed) { + /* 10G <==> 1X x 10G */ + case PORT_SPEED_10GB: + props->active_width = IB_WIDTH_1X; + props->active_speed = IB_SPEED_QDR; + break; + + /* 25G <==> 1X x 25G */ + case PORT_SPEED_25GB: + props->active_width = IB_WIDTH_1X; + props->active_speed = IB_SPEED_EDR; + break; + + /* 40G <==> 4X x 10G */ + case PORT_SPEED_40GB: + props->active_width = IB_WIDTH_4X; + props->active_speed = IB_SPEED_QDR; + break; + + /* 100G <==> 4X x 25G */ + case PORT_SPEED_100GB: + props->active_width = IB_WIDTH_4X; + props->active_speed = IB_SPEED_EDR; + break; + + default: + props->active_width = 0; + props->active_speed = 0; + break; + } +} + +static void roce3_set_ib_port_attr(struct ib_port_attr *props, struct roce3_device *rdev) +{ + props->port_cap_flags = IB_PORT_CM_SUP; + props->gid_tbl_len = (int)rdev->rdma_cap.max_gid_per_port; + props->max_msg_sz = rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz; + props->pkey_tbl_len = (u16)rdev->rdma_cap.max_pkeys; + props->max_mtu = IB_MTU_4096; + props->state = IB_PORT_DOWN; + props->phys_state = ROCE_PORT_PHYS_STATE_DISABLED; + props->active_mtu = IB_MTU_256; +} +#ifdef OFED_MLNX_5_8 +static void eth_link_query_port(struct ib_device *ibdev, u8 port, struct ib_port_attr *props) +#else +static void eth_link_query_port(struct ib_device *ibdev, u32 port, struct ib_port_attr *props) +#endif +{ + struct roce3_device *rdev = NULL; + struct net_device *netdev = NULL; +#ifdef ROCE_BONDING_EN + struct net_device *upper = NULL; +#endif + enum ib_mtu mtu; + enum mag_cmd_port_speed speed = PORT_SPEED_10GB; + int ret = 0; + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu), dev_name(%s).\n", __func__, + rdev->glb_func_id, ibdev->name); + return; + } + + roce3_set_ib_port_attr(props, rdev); + + ret = hinic3_get_speed(rdev->hwdev, &speed, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get speed, func_id(%d)\n", __func__, rdev->glb_func_id); + props->active_width = 0; + props->active_speed = 0; + return; + } + + eth_link_get_speed(props, speed); + + netdev = roce3_ib_get_netdev(ibdev, ROCE_DEFAULT_PORT_NUM); + if (netdev == NULL) { + return; + } + +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + rcu_read_lock(); + upper = netdev_master_upper_dev_get_rcu(netdev); + if (upper != NULL) { + dev_put(netdev); + netdev = upper; + dev_hold(netdev); + } + rcu_read_unlock(); + } +#endif + + if (netif_running(netdev) && netif_carrier_ok(netdev)) { + props->state = IB_PORT_ACTIVE; + props->phys_state = ROCE_PORT_PHYS_STATE_LINKUP; + } + + mtu = (enum ib_mtu)iboe_get_mtu((int)netdev->mtu); + + dev_put(netdev); + + props->active_mtu = ROCE_MIN(props->max_mtu, mtu); +} + +/* **************************************************************************** + Prototype : roce3_query_port + Description : query port attribute + Input : struct ib_device *ibdev + u8 port + struct ib_port_attr *props + Output : struct ib_port_attr *props + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +#ifdef OFED_MLNX_5_8 +int roce3_query_port(struct ib_device *ibdev, u32 port, struct ib_port_attr *props) +#else +int roce3_query_port(struct ib_device *ibdev, u8 port, struct ib_port_attr *props) +#endif +{ + if ((ibdev == NULL) || (props == NULL)) { + pr_err("[ROCE] %s: Ibdev or props is null\n", __func__); + return -EINVAL; + } + + memset(props, 0, sizeof(*props)); + + eth_link_query_port(ibdev, port, props); + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_query_gid + Description : query gid + Input : struct ib_device *ibdev + u8 port + int index + union ib_gid *gid + Output : union ib_gid *gid + + 1.Date : 2015/5/8 + Modification : Created function + + 2.Date : 2015/6/8 + Modification : Modify function + +**************************************************************************** */ +#ifdef OFED_MLNX_5_8 +int roce3_query_gid(struct ib_device *ibdev, u32 port, int index, union ib_gid *gid) +#else +int roce3_query_gid(struct ib_device *ibdev, u8 port, int index, union ib_gid *gid) +#endif +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct rdma_gid_entry gid_entry; + + if ((ibdev == NULL) || (gid == NULL)) { + pr_err("[ROCE] %s: Ibdev or gid is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = roce3_rdma_get_gid(rdev->hwdev, (u32)port, (u32)index, &gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get gid, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + memcpy((void *)gid->raw, (void *)gid_entry.raw, sizeof(*gid)); + + // 按照OFED的gid生成方式转换GID, 仅IPv4场景需要转换 + if (gid_entry.dw6_h.bs.gid_type == ROCE_IPv4_ROCEv2_GID) { + // 未add的gid直接返回，不需要转换 + if ((gid->global.subnet_prefix == 0) && (gid->global.interface_id == 0)) { + return 0; + } + ipv6_addr_set_v4mapped(*((u32 *)(void *)gid + ROCE_GID_IP_IDX), (struct in6_addr *)gid); + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_query_pkey + Description : query pkey + Input : struct ib_device *ibdev + u8 port + u16 index + u16 *pkey + Output : u16 *pkey + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +#ifdef OFED_MLNX_5_8 +int roce3_query_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey) +#else +int roce3_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey) +#endif +{ + struct roce3_device *rdev = NULL; + if ((ibdev == NULL) || (pkey == NULL)) { + pr_err("[ROCE] %s: Ibdev or pkey is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if (pkey == NULL) { + pr_err("[ROCE] %s: Pkey is null\n", __func__); + return -EINVAL; + } + + *pkey = 0xffff; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_modify_device + Description : modify device attribute + Input : struct ib_device *ibdev + int mask + struct ib_device_modify *props + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +int roce3_modify_device(struct ib_device *ibdev, int mask, struct ib_device_modify *props) +{ + unsigned long flags = 0; + struct roce3_device *rdev = NULL; + + if ((ibdev == NULL) || (props == NULL)) { + pr_err("[ROCE] %s: Ibdev or props is null\n", __func__); + return -EINVAL; + } + + if (((unsigned int)mask & ~IB_DEVICE_MODIFY_NODE_DESC) != 0) { + pr_err("[ROCE] %s: Not supported to modify node description\n", __func__); + return -EOPNOTSUPP; + } + + if ((((u32)mask) & IB_DEVICE_MODIFY_NODE_DESC) == 0) { + pr_info("[ROCE] %s: No need to modify node description\n", __func__); + return 0; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + spin_lock_irqsave(&rdev->node_desc_lock, flags); + memcpy((void *)ibdev->node_desc, (void *)props->node_desc, IB_DEVICE_NODE_DESC_MAX); + spin_unlock_irqrestore(&rdev->node_desc_lock, flags); + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_modify_port + Description : modify port attribute + Input : struct ib_device *ibdev + u8 port + int mask + struct ib_port_modify *props + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +#ifdef OFED_MLNX_5_8 +int roce3_modify_port(struct ib_device *ibdev, u32 port, int mask, struct ib_port_modify *props) +#else +int roce3_modify_port(struct ib_device *ibdev, u8 port, int mask, struct ib_port_modify *props) +#endif +{ + int ret = 0; + struct ib_port_attr attr; + struct roce3_device *rdev = NULL; + + if (ibdev == NULL) { + pr_err("[ROCE] %s: Ibdev is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + memset(&attr, 0, sizeof(struct ib_port_attr)); + + mutex_lock(&rdev->cap_mask_mutex); + + ret = roce3_query_port(ibdev, port, &attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to query port, func_id(%d)\n", __func__, rdev->glb_func_id); + } + + mutex_unlock(&rdev->cap_mask_mutex); + + return ret; +} + +static void roce3_alloc_ucontext_set(struct roce3_device *rdev, struct roce3_alloc_ucontext_resp *resp) +{ + struct rdma_service_cap *rdma_cap = NULL; + + rdma_cap = &rdev->rdma_cap; + + resp->num_qps = rdma_cap->dev_rdma_cap.roce_own_cap.max_qps; + resp->num_xsrqs = rdma_cap->dev_rdma_cap.roce_own_cap.max_srqs; + resp->cqe_size = rdma_cap->cqe_size; + resp->wqebb_size = rdma_cap->wqebb_size; + resp->dwqe_size = rdma_cap->direct_wqe_size; + resp->max_msg_size = rdma_cap->dev_rdma_cap.roce_own_cap.max_msg_sz; + resp->max_comp_vector = rdma_cap->num_comp_vectors; + resp->max_inline_size = rdma_cap->dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz; + + resp->storage_aa_en = roce3_is_roceaa(rdev->cfg_info.scence_id); + resp->phy_port = rdev->hw_info.phy_port; + resp->srq_container_en = rdev->cfg_info.srq_container_en; + resp->srq_container_mode = rdev->cfg_info.srq_container_mode; + resp->xrc_srq_container_mode = rdev->cfg_info.xrc_srq_container_mode; + resp->warn_th = rdev->cfg_info.warn_th; + + roce3_resp_set_ext(rdev, resp); + return; +} + +static int roce3_alloc_ucontext_pre_check(struct ib_device *ibdev, const struct ib_udata *udata) +{ + struct roce3_device *rdev = NULL; + + if ((ibdev == NULL) || (udata == NULL)) { + pr_err("[ROCE] %s: Ibdev or udata is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if (!rdev->ib_active) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Device is abnormal, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EAGAIN; + } + + return 0; +} + +static int roce3_alloc_ucontext_return(struct roce3_device *rdev, struct ib_udata *udata, + struct roce3_ucontext *context, struct roce3_alloc_ucontext_resp *resp) +{ + int ret; + + resp->db_offset = context->db_dma_addr & ((1 << PAGE_SHIFT) - 1); + resp->dwqe_offset = context->dwqe_dma_addr & ((1 << PAGE_SHIFT) - 1); + + if (context->dwqe_dma_addr == 0) { + resp->dwqe_size = 0; + } + + roce3_ucontext_set_ext(rdev, context); + + INIT_LIST_HEAD(&context->db_page_list); + mutex_init(&context->db_page_mutex); + + /* Copy data to user space */ + ret = ib_copy_to_udata_ext(udata, resp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data to user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + return 0; +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_alloc_ucontext(struct ib_ucontext *ibucontext, struct ib_udata *udata) +{ + int ret; + struct roce3_ucontext *context = rdma_udata_to_drv_context( + udata, struct roce3_ucontext, ibucontext); + struct roce3_device *rdev = to_roce3_dev(ibucontext->device); + struct roce3_alloc_ucontext_resp *resp = NULL; + + ret = roce3_alloc_ucontext_pre_check(ibucontext->device, udata); + if (ret != 0) { + return ret; + } + + resp = roce3_resp_alloc_ext(); + if (resp == NULL) { + ret = (-ENOMEM); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc ucontext, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err; + } + + roce3_alloc_ucontext_set(rdev, resp); + /* Alloc user space context Doorbell and DWQE */ + ret = hinic3_alloc_db_phy_addr(rdev->hwdev, &context->db_dma_addr, &context->dwqe_dma_addr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc DB pa, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + goto err_db; + } + + /* Copy data to user space */ + ret = roce3_alloc_ucontext_return(rdev, udata, context, resp); + if (ret != 0) { + goto err_return; + } + + kfree(resp); + + return 0; +err_return: + hinic3_free_db_phy_addr(rdev->hwdev, context->db_dma_addr, context->dwqe_dma_addr); +err_db: + kfree(resp); +err: + return ret; +} + +void roce3_dealloc_ucontext(struct ib_ucontext *ibcontext) +{ + struct roce3_ucontext *context = NULL; + struct roce3_device *rdev = NULL; + + if (ibcontext == NULL) { + pr_err("[ROCE] %s: Ibcontext is null\n", __func__); + return; + } + + context = to_roce3_ucontext(ibcontext); + rdev = to_roce3_dev(ibcontext->device); + + hinic3_free_db_phy_addr(rdev->hwdev, context->db_dma_addr, context->dwqe_dma_addr); + + return; +} +#else +struct ib_ucontext *roce3_alloc_ucontext(struct ib_device *ibdev, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_ucontext *context = NULL; + struct roce3_alloc_ucontext_resp *resp = NULL; + + ret = roce3_alloc_ucontext_pre_check(ibdev, udata); + if (ret != 0) { + return (struct ib_ucontext *)ERR_PTR((long)ret); + } + + rdev = to_roce3_dev(ibdev); + + resp = roce3_resp_alloc_ext(); + if (resp == NULL) { + ret = (-ENOMEM); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc ucontext, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_resp_alloc; + } + + roce3_alloc_ucontext_set(rdev, resp); + + context = roce3_ucontext_alloc_ext(); + if (context == NULL) { + ret = (-ENOMEM); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc ucontext, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_ucontext_alloc; + } + + /* Alloc user space context Doorbell and DWQE */ + ret = hinic3_alloc_db_phy_addr(rdev->hwdev, &context->db_dma_addr, &context->dwqe_dma_addr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc DB pa, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + goto err_db_phy_addr_alloc; + } + + /* Copy data to user space */ + ret = roce3_alloc_ucontext_return(rdev, udata, context, resp); + if (ret != 0) { + goto err_return; + } + + kfree(resp); + + return (struct ib_ucontext *)&context->ibucontext; + +err_return: + hinic3_free_db_phy_addr(rdev->hwdev, context->db_dma_addr, context->dwqe_dma_addr); +err_db_phy_addr_alloc: + kfree(context); +err_ucontext_alloc: + kfree(resp); +err_resp_alloc: + return (struct ib_ucontext *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : roce3_dealloc_ucontext + Description : dealloc ucontext + Input : struct ib_ucontext *ibcontext + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +int roce3_dealloc_ucontext(struct ib_ucontext *ibcontext) +{ + struct roce3_ucontext *context = NULL; + struct roce3_device *rdev = NULL; + + if (ibcontext == NULL) { + pr_err("[ROCE] %s: Ibcontext is null\n", __func__); + return -EINVAL; + } + + context = to_roce3_ucontext(ibcontext); + rdev = to_roce3_dev(ibcontext->device); + + hinic3_free_db_phy_addr(rdev->hwdev, context->db_dma_addr, context->dwqe_dma_addr); + kfree(context); + + return 0; +} +#endif + +/* **************************************************************************** + Prototype : roce3_mmap + Description : memory map + Input : struct ib_ucontext *ibcontext + struct vm_area_struct *vma + Output : None + + 1.Date : 2015/5/8 + Modification : Created function + +**************************************************************************** */ +int roce3_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) +{ + struct roce3_device *rdev = NULL; + struct roce3_ucontext *ucontext = NULL; + unsigned long db_pfn = 0; + unsigned long dwqe_pfn = 0; + int res = 0; + + if ((ibcontext == NULL) || (vma == NULL)) { + pr_err("[ROCE] %s: Ibcontext or vma is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcontext->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ucontext = to_roce3_ucontext(ibcontext); + db_pfn = ucontext->db_dma_addr >> PAGE_SHIFT; + dwqe_pfn = ucontext->dwqe_dma_addr >> PAGE_SHIFT; + + if ((vma->vm_end - vma->vm_start) != PAGE_SIZE) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: (Vm_end - vm_start) is not equal to PAGE_SIZE, func_id(%d)\n", + __func__, rdev->glb_func_id); + return -EINVAL; + } + + /* map hw DB to physical page from user */ + if (vma->vm_pgoff == USR_MMAP_DB_OFFSET) { + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + /* construct vm_start~vm_start+PAGE_SIZE page table + * db_pfn is page number + * vm_page_prot means attr + */ + if (io_remap_pfn_range(vma, vma->vm_start, db_pfn, PAGE_SIZE, vma->vm_page_prot) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to do db io remap, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EAGAIN; + } + return 0; + } + + if ((vma->vm_pgoff == USR_MMAP_DWQE_OFFSET) && (rdev->rdma_cap.direct_wqe_size != 0)) { // DWQE mmap +#ifdef __aarch64__ + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); +#else + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); +#endif + + if (io_remap_pfn_range(vma, vma->vm_start, dwqe_pfn, PAGE_SIZE, vma->vm_page_prot) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to do dwqe io remap, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EAGAIN; + } + return 0; + } + + res = roce3_mmap_ext(rdev, ucontext, vma); + return res; +} +#ifdef OFED_MLNX_5_8 +enum rdma_link_layer roce3_port_link_layer(struct ib_device *ibdev, u32 port_num) +#else +enum rdma_link_layer roce3_port_link_layer(struct ib_device *ibdev, u8 port_num) +#endif +{ + struct roce3_device *rdev = NULL; + + if (ibdev == NULL) { + return IB_LINK_LAYER_UNSPECIFIED; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return IB_LINK_LAYER_UNSPECIFIED; + } + + if (port_num != ROCE_DEFAULT_PORT_NUM) { + return IB_LINK_LAYER_UNSPECIFIED; + } + + return IB_LINK_LAYER_ETHERNET; +} + +static void roce3_resolve_cb(int status, struct sockaddr *src_addr, struct rdma_dev_addr *addr, void *context) +{ + ((struct roce3_resolve_cb_context *)context)->status = status; + complete(&((struct roce3_resolve_cb_context *)context)->comp); +} + +static int roce3_rdma_addr_find_l2_eth_by_grh(const union ib_gid *sgid, const union ib_gid *dgid, u8 *dmac, + const struct net_device *ndev, int *hoplimit, struct roce3_device *rdev) +{ + struct rdma_dev_addr dev_addr; + struct roce3_resolve_cb_context ctx; + union { + struct sockaddr _sockaddr; + struct sockaddr_in _sockaddr_in; + struct sockaddr_in6 _sockaddr_in6; + } sgid_addr, dgid_addr; + int ret; + + rdma_gid2ip((struct sockaddr *)&sgid_addr, sgid); + rdma_gid2ip((struct sockaddr *)&dgid_addr, dgid); + + memset(&dev_addr, 0, sizeof(dev_addr)); + + if (ndev) { + dev_addr.bound_dev_if = ndev->ifindex; + dev_addr.net = dev_net(ndev); + } else { + dev_addr.net = &init_net; + } + + init_completion(&ctx.comp); +#if LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90) + ret = rdma_resolve_ip(&sgid_addr._sockaddr, &dgid_addr._sockaddr, &dev_addr, RESOLVE_IP_TIME_OUT, + roce3_resolve_cb, &ctx); +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) \ + || defined(OFED_MLNX_5_8) + ret = rdma_resolve_ip(&sgid_addr._sockaddr, &dgid_addr._sockaddr, &dev_addr, RESOLVE_IP_TIME_OUT, + roce3_resolve_cb, false, &ctx); +#else + ret = rdma_resolve_ip(&roce3_self, &sgid_addr._sockaddr, &dgid_addr._sockaddr, &dev_addr, RESOLVE_IP_TIME_OUT, + roce3_resolve_cb, &ctx); +#endif + if (ret != 0) { + pr_err("[ROCE] %s: rdma_resolve_ip failed. Igonore the err.\n", __func__); + roce3_resolve_cb(0, &sgid_addr._sockaddr, &dev_addr, &ctx); + } + + wait_for_completion(&ctx.comp); + + memcpy(dmac, dev_addr.dst_dev_addr, ETH_ALEN); + if (hoplimit) { + *hoplimit = dev_addr.hoplimit; + } + + return 0; +} + +static int roce3_ah_valid_check(struct ib_global_route *grh, u16 *vlan_id, u8 *dmac) +{ + u8 unicast_gid0[ROCE_GID_LEN] = { 0 }; + u8 unicast_gid1[ROCE_GID_LEN] = { 0 }; + + /* check gid(unicast gid can not be 0 or 1) */ + unicast_gid0[ROCE_GID_HIGHEST_BYTE] = 0; + unicast_gid1[ROCE_GID_HIGHEST_BYTE] = 1; + + if ((ROCE_MEMCMP(grh->dgid.raw, unicast_gid0, sizeof(union ib_gid)) == 0) || + (ROCE_MEMCMP(grh->dgid.raw, unicast_gid1, sizeof(union ib_gid)) == 0)) { + pr_err("[ROCE] %s: Invalid unicast dgid\n", __func__); + return (-EINVAL); + } + + if (rdma_link_local_addr((struct in6_addr *)grh->dgid.raw) != 0) { + rdma_get_ll_mac((struct in6_addr *)grh->dgid.raw, dmac); + *vlan_id = ROCE_DEFAULT_VLAN_ID; + } + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +static int roce3_fill_gid_attr(struct roce3_device *rdev, struct rdma_ah_attr *ah_attr, union ib_gid *sgid, + const struct ib_gid_attr **sgid_attr) +{ + int ret = 0; + + ret = rdma_query_gid(&rdev->ib_dev, ah_attr->port_num, ah_attr->grh.sgid_index, sgid); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to query gid func_id(%hu),port_num(%d),gid_index(%d),ret(%d)\n", + rdev->glb_func_id, ah_attr->port_num, ah_attr->grh.sgid_index, ret); + return ret; + } + + *sgid_attr = rdma_get_gid_attr(&rdev->ib_dev, ah_attr->port_num, ah_attr->grh.sgid_index); + if (IS_ERR_OR_NULL(*sgid_attr)) { + ret = (int)PTR_ERR(*sgid_attr); + dev_err(rdev->hwdev_hdl, "[ROCE] : Failed to get sgid_attr, func_id(%hu), ret(%d).\n", rdev->glb_func_id, ret); + return ret; + } + + return ret; +} + +static void roce3_release_gid_ref_cnt(const struct ib_gid_attr *sgid_attr) +{ + rdma_put_gid_attr(sgid_attr); +} +#else +static int roce3_fill_gid_attr(struct roce3_device *rdev, struct rdma_ah_attr *ah_attr, union ib_gid *sgid, + const struct ib_gid_attr **sgid_attr) +{ + int ret = 0; + struct ib_gid_attr *temp_sgid_attr = NULL; + + temp_sgid_attr = (struct ib_gid_attr *)kzalloc(sizeof(struct ib_gid_attr), GFP_KERNEL); + if (temp_sgid_attr == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to kzalloc in roce3_fill_gid_attr\n"); + return -ENOMEM; + } + + ret = ib_query_gid(&rdev->ib_dev, ah_attr->port_num, ah_attr->grh.sgid_index, sgid, temp_sgid_attr); + if ((ret != 0) || (temp_sgid_attr->ndev == 0)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to query gid func_id(%hu),port_num(%d),gid_index(%d),ret(%d)\n", + rdev->glb_func_id, ah_attr->port_num, ah_attr->grh.sgid_index, ret); + + if (ret == 0) { + ret = -ENXIO; + } + return ret; + } + *sgid_attr = temp_sgid_attr; + + return ret; +} + +static void roce3_release_gid_ref_cnt(const struct ib_gid_attr *sgid_attr) +{ + dev_put(sgid_attr->ndev); +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +static struct net_device *roce3_fill_netdev(struct roce3_device *rdev, union ib_gid *sgid) +{ + struct net_device *netdev = NULL; + union { + struct sockaddr _sockaddr; + struct sockaddr_in _sockaddr_in; + struct sockaddr_in6 _sockaddr_in6; + } socket_addr; + + rdma_gid2ip((struct sockaddr *)&socket_addr, sgid); + + /* find netdev,rdev->ndevis not valid in vlan scenario */ + netdev = ip_dev_find(&init_net, ((const struct sockaddr_in *)&socket_addr._sockaddr)->sin_addr.s_addr); + if (netdev) { + dev_put(netdev); + } + + return netdev; +} +#else +static struct net_device *roce3_fill_netdev(struct roce3_device *rdev, union ib_gid *sgid) +{ + return NULL; +} +#endif + +int roce3_resolve_grh(struct roce3_device *rdev, struct rdma_ah_attr *ah_attr, u16 *vlan_id, struct ib_udata *udata) +{ + int ret = 0; + u8 zero_mac[ETH_ALEN] = { 0 }; + u8 *dmac = NULL; + union ib_gid sgid; + const struct ib_gid_attr *sgid_attr = NULL; + struct net_device *netdev = NULL; + + if ((rdev == NULL) || (ah_attr == NULL) || (vlan_id == NULL)) { + pr_err("[ROCE, ERR] %s: Input pointer is NULL, rdev(%px), ah_attr(%px), vlan_id(%px).\n", __func__, + rdev, ah_attr, vlan_id); + return (-EINVAL); + } + + dmac = ah_attr->roce.dmac; + ret = roce3_ah_valid_check(&ah_attr->grh, vlan_id, dmac); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to check grh input, func_id(%hu), ret(%d).\n", + rdev->glb_func_id, ret); + return ret; + } + if (ROCE_MEMCMP(dmac, zero_mac, ETH_ALEN) != 0) { + return 0; + } + + ret = roce3_fill_gid_attr(rdev, ah_attr, &sgid, &sgid_attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to fill gid attr, func_id(%hu), ret(%d)\n", rdev->glb_func_id, + ret); + return ret; + } + + netdev = roce3_fill_netdev(rdev, &sgid); + + /* reparse dmac avoiding invalid damc from OFED */ + ret = roce3_rdma_addr_find_l2_eth_by_grh(&sgid, &ah_attr->grh.dgid, dmac, netdev, NULL, rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to find dmac by grh, func_id(%hu)\n", rdev->glb_func_id); + goto resolve_grh_end; + } + + if (ROCE_MEMCMP(dmac, zero_mac, ETH_ALEN) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to find valid dmac, func_id(%hu)\n", rdev->glb_func_id); + ret = (-EINVAL); + goto resolve_grh_end; + } + + *vlan_id = rdma_vlan_dev_vlan_id(sgid_attr->ndev); + +resolve_grh_end: + roce3_release_gid_ref_cnt(sgid_attr); + + return ret; +} + +static int ah_get_vlan_id(struct roce3_device *rdev, struct ib_pd *pd, struct rdma_ah_attr *ah_attr, u32 *vlan_id) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) + struct net_device *ndev; + + rcu_read_lock(); + ndev = rcu_dereference(ah_attr->grh.sgid_attr->ndev); + if (ndev == NULL) { + rcu_read_unlock(); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Net device is NULL, func_id(%hu)\n", rdev->glb_func_id); + return -EINVAL; + } + *vlan_id = rdma_vlan_dev_vlan_id(ndev); + rcu_read_unlock(); +#else + struct ib_gid_attr gid_attr; + union ib_gid sgid; + int ret; + /* Get SGID */ + ret = ib_get_cached_gid(pd->device, rdma_ah_get_port_num(ah_attr), ah_attr->grh.sgid_index, &sgid, &gid_attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to get sgid, ret(%d), func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + return -EFAULT; + } + + *vlan_id = rdma_vlan_dev_vlan_id(gid_attr.ndev); + dev_put(gid_attr.ndev); +#endif + return 0; +} + +static int create_ib_ah(struct roce3_device *rdev, struct ib_pd *pd, struct roce3_ah *rah, + struct rdma_ah_attr *ah_attr) +{ + int ret; + u8 *dmac = ah_attr->roce.dmac; + u32 vlan_id = 0; + + ret = ah_get_vlan_id(rdev, pd, ah_attr, &vlan_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get vlan_id (ret:%d)\n", __func__, ret); + return -EFAULT; + } + + if (((u32)rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) != 0) { + memcpy((void *)rah->priv_ah.dgid, (void *)ah_attr->grh.dgid.raw, + sizeof(rah->priv_ah.dgid)); + rah->priv_ah.dw2.bs.flow_label = ah_attr->grh.flow_label & 0xfffff; + rah->priv_ah.dw1.bs.sgid_index = ah_attr->grh.sgid_index & 0x7f; + rah->priv_ah.dw1.bs.hoplimit = ah_attr->grh.hop_limit; + rah->priv_ah.dw1.bs.tclass = (u8)(ah_attr->grh.traffic_class | 0x2); + } + rah->priv_ah.dw0.bs.pd = to_roce3_pd(pd)->pdn & 0x3ffff; + rah->priv_ah.dw0.bs.wqe_cos = roce3_get_db_cos_from_vlan_pri(rdev, ah_attr->sl); + rah->priv_ah.dw0.value = cpu_to_be32(rah->priv_ah.dw0.value); + + rah->priv_ah.dw1.bs.port = ah_attr->port_num & 0xf; + rah->priv_ah.dw2.bs.smac_index = rdev->glb_func_id; /* set global Function ID */ + rah->priv_ah.dw2.value = cpu_to_be32(rah->priv_ah.dw2.value); + + rah->priv_ah.dw1.bs.resv = 0; + rah->priv_ah.dw7.bs.vlan_id = vlan_id & 0xfff; + rah->priv_ah.dw7.bs.vlan_pri = ah_attr->sl & 0x7; + + rah->priv_ah.dw1.value = cpu_to_be32(rah->priv_ah.dw1.value); + + rah->priv_ah.dw7.bs.dmac_h16 = (dmac[0] << ROCE_RAH_DMAC_H16_SHIFT) | dmac[1]; + rah->priv_ah.dw7.value = cpu_to_be32(rah->priv_ah.dw7.value); + + memcpy((void *)&rah->priv_ah.dmac_l32, + (void *)&dmac[ROCE_RAH_DMAC_L32_START], sizeof(rah->priv_ah.dmac_l32)); + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *init_attr, struct ib_udata *udata) +{ + struct roce3_ah *rah = to_roce3_ah(ibah); + struct roce3_device *rdev = to_roce3_dev(ibah->device); + struct rdma_ah_attr *ah_attr = init_attr->ah_attr; + enum rdma_ah_attr_type ah_type = ah_attr->type; + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if ((ah_type == RDMA_AH_ATTR_TYPE_ROCE) && (((u32)rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) == 0)) { + return -EINVAL; + } + + return create_ib_ah(rdev, ibah->pd, rah, ah_attr); +} +#else +#if LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +struct ib_ah *roce3_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, u32 flags, struct ib_udata *udata) +#else +struct ib_ah *roce3_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr, struct ib_udata *udata) +#endif +{ + struct roce3_ah *rah = NULL; + struct roce3_device *rdev = to_roce3_dev(pd->device); + enum rdma_ah_attr_type ah_type = ah_attr->type; + int ret; + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ERR_PTR(-EPERM); + } + + if ((ah_type == RDMA_AH_ATTR_TYPE_ROCE) && (((u32)rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) == 0)) { + return ERR_PTR(-EINVAL); + } + + rah = kzalloc(sizeof(*rah), GFP_ATOMIC); + if (!rah) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc ah, func_id(%d)\n", __func__, rdev->glb_func_id); + return ERR_PTR(-ENOMEM); + } + + ret = create_ib_ah(rdev, pd, rah, ah_attr); + if (ret) { + kfree(rah); + return ERR_PTR(ret); + } + + return &rah->ibah; +} +#endif + +int roce3_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr) +{ + struct roce3_ah *ah = NULL; + struct roce3_priv_ah priv_ah; + + if ((ibah == NULL) || (ah_attr == NULL)) { + pr_err("[ROCE] %s: Ibah or ah_attr is null\n", __func__); + return -EINVAL; + } + + ah = to_roce3_ah(ibah); + memset(ah_attr, 0, sizeof *ah_attr); + + priv_ah.dw1.value = be32_to_cpu(ah->priv_ah.dw1.value); + priv_ah.dw2.value = be32_to_cpu(ah->priv_ah.dw2.value); + priv_ah.dw7.value = be32_to_cpu(ah->priv_ah.dw7.value); + + ah_attr->ah_flags = IB_AH_GRH; + ah_attr->sl = priv_ah.dw7.bs.vlan_pri; + ah_attr->port_num = priv_ah.dw1.bs.port; + ah_attr->grh.traffic_class = priv_ah.dw1.bs.tclass; + ah_attr->grh.hop_limit = priv_ah.dw1.bs.hoplimit; + ah_attr->grh.sgid_index = priv_ah.dw1.bs.sgid_index; + ah_attr->grh.flow_label = priv_ah.dw2.bs.flow_label; + + memcpy((void *)ah_attr->grh.dgid.raw, (void *)ah->priv_ah.dgid, + sizeof(ah->priv_ah.dgid)); + return 0; +} + +#ifdef OFED_MLNX_5_8 +int roce3_destroy_ah(struct ib_ah *ibah, u32 flags) +{ + return 0; +} +#else +#if LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +int roce3_destroy_ah(struct ib_ah *ibah, u32 flags) +#else +int roce3_destroy_ah(struct ib_ah *ibah) +#endif +{ + struct roce3_ah *rah = NULL; + + if (ibah == NULL) { + pr_err("[ROCE] %s: Ibah is null\n", __func__); + return -EINVAL; + } + + rah = to_roce3_ah(ibah); + + kfree(rah); + + return 0; +} +#endif +#ifdef OFED_MLNX_5_8 +int roce3_port_immutable(struct ib_device *ibdev, u32 port_num, struct ib_port_immutable *immutable) +#else +int roce3_port_immutable(struct ib_device *ibdev, u8 port_num, struct ib_port_immutable *immutable) +#endif +{ + struct ib_port_attr attr; + int err; + struct roce3_device *rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; // only rocev2 + + err = ib_query_port(ibdev, port_num, &attr); + if (err != 0) { + pr_err("[ROCE] %s: query ib port failed\n", __func__); + return err; + } + + immutable->pkey_tbl_len = attr.pkey_tbl_len; + immutable->gid_tbl_len = attr.gid_tbl_len; + immutable->max_mad_size = IB_MGMT_MAD_SIZE; + + return 0; +} + +int roce3_get_dcb_cfg_cos(struct roce3_device *rdev, roce3_get_cos_inbuf_s *inbuf, u8 *cos) +{ + int ret; + u8 pri; + struct rdma_gid_entry gid; + struct hinic3_dcb_state dcb = { 0 }; + + ret = roce3_rdma_get_gid(rdev->hwdev, inbuf->port_num, inbuf->sgid_index, &gid); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to init gid info\n", __func__); + return (-EINVAL); + } + + ret = hinic3_get_dcb_state(rdev->hwdev, &dcb); + if (ret != 0) { + pr_err("[ROCE] %s: hinic3_get_dcb_state failed.ret: %d.\n", __func__, ret); + return (-EINVAL); + } + + *cos = dcb.default_cos; + gid.dw6_h.value = cpu_to_le16(gid.dw6_h.value); + if ((dcb.trust == ROCE3_DCB_PCP) && (gid.dw6_h.bs.tag == ROCE_GID_VLAN_INVALID)) { + // pcp cfg & no vlan should use default cos + return 0; + } + + pri = (dcb.trust == ROCE3_DCB_PCP) ? inbuf->sl : (inbuf->traffic_class >> ROCE3_DSCP_IDX); + ret = hinic3_get_cos_by_pri(rdev->hwdev, pri, cos); + if (ret != 0) { + pr_err("[ROCE] %s: get_cos_by_pri failed.ret: %d, pri:%u, dcb_on:%u, trust:%u.\n", __func__, ret, pri, + dcb.dcb_on, dcb.trust); + return (-EINVAL); + } + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/roce_mix.h b/drivers/infiniband/hw/hiroce3/roce_mix.h new file mode 100755 index 000000000..e7c52e45e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_mix.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mix.h + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/10/13 + * Description : The definition of macros, data structure, function prototype etc of RoCE mix features. + */ + +#ifndef ROCE_MIX_H +#define ROCE_MIX_H + +#include <net/arp.h> +#include <net/neighbour.h> +#include <net/route.h> +#include <net/addrconf.h> +#include <net/ip6_route.h> +#include <linux/mutex.h> +#include <linux/inetdevice.h> +#include <linux/slab.h> +#include <linux/workqueue.h> +#include <linux/module.h> + +#include <rdma/ib_addr.h> +#include <rdma/ib_verbs.h> + +#include "roce.h" + +#define IB_DEVICE_LOCAL_DMA_LKEY (1 << 15) + +#define ROCE_HW_VER 0ULL +#define ROCE_FW_VER_0 1ULL +#define ROCE_FW_VER_1 4ULL +#define ROCE_FW_VER_2 0ULL +#define ROCE_FW_VER_3 0ULL +#define ROCE_FW_VER ((ROCE_FW_VER_0 << 32) | (ROCE_FW_VER_1 << 16) | (ROCE_FW_VER_2 << 8) | ROCE_FW_VER_3) + +#define RESOLVE_IP_TIME_OUT 1000 +#define ROCE_GID_HIGHEST_BYTE 15 +#define ROCE_FW_VERSION_LEN 4 +#define ROCE_DEFAULT_VLAN_ID 0xFFFF +#define ROCE_RAH_TC_SHIFT 2 +#define ROCE_RAH_DMAC_H16_SHIFT 8 +#define ROCE_RAH_DMAC_L32_START 2 + +#define ROCE3_DCB_PCP 0 +#define ROCE3_DCB_DSCP 1 + +#define ROCE3_DSCP_IDX 2 // dscp begin from bit 2 in traffic_class + +#define IB_DEVICE_NODE_DESC_MAX 64 + +#define MEND_CAP_DEVIDE 2 // to avoid chip cache problem +#define ROCE_PORT_NUM_2 2 +#define ROCE_25G_PORT_SPEED 25 + +#define ROCE_GID_IP_IDX 3 + +enum { + USR_MMAP_DB_OFFSET = 0, + USR_MMAP_DWQE_OFFSET, + USR_MMAP_DFX_OFFSET, + USR_MMAP_DBAR3_OFFSET +}; + +enum roce_port_state_e { + ROCE_PORT_PHYS_STATE_NO_CHANGE = 0, + ROCE_PORT_PHYS_STATE_SLEEP, + ROCE_PORT_PHYS_STATE_POLLING, + ROCE_PORT_PHYS_STATE_DISABLED = 3, + ROCE_PORT_PHYS_STATE_PORTCONFTRAIN, + ROCE_PORT_PHYS_STATE_LINKUP = 5, + ROCE_PORT_PHYS_STATE_LINKERRRECOVER, + ROCE_PORT_PHYS_STATE_PHYTEST +}; + +enum ROCE_MBOX_CMD { + ROCE_MBOX_CMD_SEND_MAIL_BOX, + ROCE_MBOX_CMD_MAX +}; + +struct roce3_priv_ah { + /* DW0 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 pd : 18; + u32 rsvd0 : 6; + u32 stat_rate : 4; + u32 wqe_cos : 3; + u32 fl : 1; /* forcelock flag, it is used in multicast communication */ +#else + u32 f1 : 1; + u32 wqe_cos : 3; + u32 stat_rate : 4; + u32 rsvd0 : 6; + u32 pd : 18; +#endif + } bs; + u32 value; + } dw0; + + /* DW1 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 hoplimit : 8; + u32 sgid_index : 7; + u32 resv : 1; + u32 port : 4; + u32 rsvd1 : 4; + u32 tclass : 8; +#else + u32 tclass : 8; + u32 rsvd1 : 4; + u32 port : 4; + u32 resv : 1; + u32 sgid_index : 7; + u32 hoplimit : 8; +#endif + } bs; + u32 value; + } dw1; + + /* DW2 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 flow_label : 20; + u32 smac_index : 10; + u32 rsvd : 2; +#else + u32 rsvd : 2; + u32 smac_index : 10; + u32 flow_label : 20; +#endif + } bs; + u32 value; + } dw2; + + /* DW3~6 */ + u8 dgid[16]; + + /* DW7 */ + union { + struct { +#if (BYTE_ORDER != BIG_ENDIAN) + u32 dmac_h16 : 16; + u32 vlan_id : 12; + u32 rsvd : 1; + u32 vlan_pri : 3; +#else + u32 vlan_pri : 3; + u32 rsvd : 1; + u32 vlan_id : 12; + u32 dmac_h16 : 16; +#endif + } bs; + u32 value; + } dw7; + + /* DW8 */ + u32 dmac_l32; +}; + +struct roce3_ah { + struct ib_ah ibah; + struct roce3_priv_ah priv_ah; +}; + +union gid_addr { + struct sockaddr _sockaddr; + struct sockaddr_in _sockaddr_in; + struct sockaddr_in6 _sockaddr_in6; +}; + +struct mailbox_header { + u32 dest_host_id; + u32 dest_global_function_id; +}; + +struct roce3_mail_box_buffer { + struct mailbox_header header; + u32 data[0]; //lint !e1501 +}; + +struct roce3_resolve_cb_context { + struct completion comp; + int status; +}; + +typedef struct roce3_get_cos_inbuf { + u8 sl; + u8 sgid_index; + u8 port_num; + u8 traffic_class; +} roce3_get_cos_inbuf_s; + +/* Find struct roce3_ah through ibah */ +static inline struct roce3_ah *to_roce3_ah(const struct ib_ah *ibah) +{ + return container_of(ibah, struct roce3_ah, ibah); +} + +int roce3_resolve_grh(struct roce3_device *rdev, struct rdma_ah_attr *ah_attr, u16 *vlan_id, struct ib_udata *udata); +int roce3_get_dcb_cfg_cos(struct roce3_device *rdev, roce3_get_cos_inbuf_s *inbuf, u8 *cos); + + +#endif /* ROCE_MIX_H */ diff --git a/drivers/infiniband/hw/hiroce3/roce_netdev.c b/drivers/infiniband/hw/hiroce3/roce_netdev.c new file mode 100644 index 000000000..e0f482ca3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_netdev.c @@ -0,0 +1,858 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_netdev.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of callback functions and internal functions of RoCE net device features. + */ + +#include "roce_netdev.h" +#include "roce_netdev_extension.h" +#include "roce_main_extension.h" +#include "roce_pub_cmd.h" +#include "hinic3_rdma.h" +#include "roce.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +/* **************************************************************************** + Prototype : roce3_fill_gid_type + Description : fill gid type + Input : struct rdma_gid_entry *gid_entry + Output : None + + 1.Date : 2016/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_fill_gid_type(struct rdma_gid_entry *gid_entry, enum roce3_gid_type new_gid_type) +{ + static u32 index_roce3_gid_mapping[32][4] = { + {0x120E1436, 3452, 224529784, 0x180E252A}, {0x120E004A, 3472, 224660876, 0x6C0E403E}, + {0x120E0042, 3464, 224660836, 0x840E4036}, {0x120E0042, 3464, 224398688, 0xC00E0036}, + {0x1212143A, 3456, 224791932, 0x1812252E}, {0x1212004E, 3476, 224923024, 0x6C124042}, + {0x12120046, 3468, 224922984, 0x8412403A}, {0x12120046, 3468, 224660836, 0xC012003A}, + {0x1216143E, 3460, 225054080, 0x18162532}, {0x12160052, 3480, 225185172, 0x6C164046}, + {0x1216004A, 3472, 225185132, 0x8416403E}, {0x1216004A, 3472, 224922984, 0xC016003E}, + {0x10301458, 3484, 226626968, 0x1830254C}, {0x1030006C, 3504, 226758060, 0x6C304060}, + {0x10300064, 3496, 226758020, 0x84304058}, {0x10300064, 3496, 226495872, 0xC0300058}, + {0x10401468, 838864300, 227675560, 0x1840255C}, {0x1040007C, 1174408640, 227806652, 0x6C404070}, + {0x10400074, 1040190904, 227806612, 0x84404068}, {0x10400074, 1040190904, 227544464, 0xC0400068}, + {0x1044146C, 905973168, 227937708, 0x18442560}, {0x10440080, 1241517508, 228068800, 0x6C444074}, + {0x10440078, 1107299772, 228068760, 0x8444406C}, {0x10440078, 1107299772, 227806612, 0xC044006C}, + {0x10481470, 973082036, 228199856, 0x18482564}, {0x10480084, 1308626376, 228330948, 0x6C484078}, + {0x1048007C, 1174408640, 228330908, 0x84484070}, {0x1048007C, 1174408640, 228068760, 0xC0480070}, + {0x1262148A, 1040190928, 230034892, 0x1862257E}, {0x1262009E, 1375735268, 230165984, 0x6C624092}, + {0x12620096, 1241517532, 230165944, 0x8462408A}, {0x12620096, 1241517532, 229903796, 0xC062008A}, + }; + + u8 i = 0; + gid_entry->dw6_h.bs.gid_type = new_gid_type; + gid_entry->dw6_h.bs.gid_update = (new_gid_type == ROCE_IPv4_ROCEv2_GID); + + i = ROCE_GID_MAP_TBL_IDX_GET(gid_entry->dw6_h.bs.tunnel, gid_entry->dw6_h.bs.tag, (u16)new_gid_type); + gid_entry->hdr_len_value = index_roce3_gid_mapping[i][0]; + if (new_gid_type == ROCE_IPv4_ROCEv2_GID) { + *((u32 *)(void *)gid_entry + 1) = cpu_to_be32(index_roce3_gid_mapping[i][1]); + *((u32 *)(void *)gid_entry + ROCE_GID_MAP_TBL_IDX2) = + cpu_to_be32(index_roce3_gid_mapping[i][ROCE_GID_MAP_TBL_IDX2]); + } +} + +static void roce3_fill_gid_smac(struct net_device *net_dev, struct rdma_gid_entry *gid_entry) +{ + memcpy((void *)gid_entry->smac, (void *)net_dev->dev_addr, sizeof(gid_entry->smac)); +} + +static void roce3_fill_gid_vlan(struct roce3_device *rdev, struct net_device *net_dev, struct rdma_gid_entry *gid_entry) +{ + gid_entry->dw6_h.bs.tunnel = ROCE_GID_TUNNEL_INVALID; + if (rdma_vlan_dev_vlan_id(net_dev) != 0xffff) { + gid_entry->dw4.bs.cvlan = rdma_vlan_dev_vlan_id(net_dev) & 0xfff; + gid_entry->dw6_h.bs.tag = ROCE_GID_VLAN_VALID; + } + +#ifdef ROCE_VROCE_EN + if (rdev->is_vroce) { + gid_entry->dw4.bs.is_vroce = 1; + gid_entry->dw6_h.bs.outer_tag = ROCE_GID_VLAN_VALID; + gid_entry->dw6_h.bs.tunnel = ROCE_GID_TUNNEL_VALID; + gid_entry->dw6_h.bs.tag = ROCE_GID_VLAN_INVALID; + } +#endif +} + +/* **************************************************************************** + Prototype : roce3_dispatch_event + Description : roce3_dispatch_event + Input : struct roce3_device *rdev + int port_num + enum ib_event_type type + Output : None + + 1.Date : 2016/3/29 + Modification : Created function + +**************************************************************************** */ +static void roce3_dispatch_event(struct roce3_device *rdev, int port_num, enum ib_event_type type) +{ + struct ib_event event; + + if (rdev == NULL) { + pr_err("[ROCE, ERR] %s: Rdev is null\n", __func__); + return; + } + + memset(&event, 0, sizeof(event)); + + event.device = &rdev->ib_dev; + event.element.port_num = (u8)port_num; + event.event = type; + + ib_dispatch_event(&event); +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +static int roce3_netdev_event_ipv4_dev_scan(struct roce3_device *rdev, struct net_device *event_netdev, + struct rdma_gid_entry *gid_entry) +{ + struct in_device *in_dev = NULL; + int ret; + + in_dev = in_dev_get(event_netdev); + if (in_dev) { + for_ifa(in_dev) + { + ipv6_addr_set_v4mapped(ifa->ifa_address, (struct in6_addr *)gid_entry->raw); + + roce3_fill_gid_vlan(rdev, event_netdev, gid_entry); + roce3_fill_gid_smac(event_netdev, gid_entry); + + /* RoCE V1 */ + if (rdma_protocol_roce_eth_encap(&rdev->ib_dev, ROCE_DEFAULT_PORT_NUM)) { + roce3_fill_gid_type(gid_entry, ROCE_ROCEv1_GID); + ret = roce3_rdma_update_gid_mac(rdev->hwdev, 0, gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to update V1 gid(IPv4) when process netdev's event, func_id(%d)\n", + __func__, rdev->glb_func_id); + in_dev_put(in_dev); + return ret; + } + } + + /* RoCE V2 */ + if (rdma_protocol_roce_udp_encap(&rdev->ib_dev, ROCE_DEFAULT_PORT_NUM)) { + roce3_fill_gid_type(gid_entry, ROCE_IPv4_ROCEv2_GID); + ret = roce3_rdma_update_gid_mac(rdev->hwdev, 0, gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to update V2 gid(IPv4) when process netdev's event, func_id(%d)\n", + __func__, rdev->glb_func_id); + in_dev_put(in_dev); + return ret; + } + } + + roce3_dispatch_event(rdev, ROCE_DEFAULT_PORT_NUM, IB_EVENT_GID_CHANGE); + } + endfor_ifa(in_dev); + in_dev_put(in_dev); + } + + return 0; +} +#endif + +#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) +struct sin6_list { + struct list_head list; + struct sockaddr_in6 sin6; +}; + +static int roce3_gid_fill(struct roce3_device *rdev, struct rdma_gid_entry *gid_entry, struct net_device *event_netdev, + struct sin6_list *sin6_iter) +{ + int ret = 0; + + if (cpu_to_be64(gid_entry->global.subnet_prefix) == ROCE_DEFAULT_GID_SUBNET_PREFIX) { + return ret; + } + + roce3_fill_gid_vlan(rdev, event_netdev, gid_entry); + roce3_fill_gid_smac(event_netdev, gid_entry); + + /* RoCE V2 */ + if (rdma_protocol_roce_udp_encap(&rdev->ib_dev, ROCE_DEFAULT_PORT_NUM)) { + roce3_fill_gid_type(gid_entry, ROCE_IPv6_ROCEv2_GID); + ret = roce3_rdma_update_gid_mac(rdev->hwdev, 0, gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to update V2 gid(IPv6), func_id(%d)\n", __func__, + rdev->glb_func_id); + list_del(&sin6_iter->list); + kfree(sin6_iter); + return ret; + } + } + + roce3_dispatch_event(rdev, ROCE_DEFAULT_PORT_NUM, IB_EVENT_GID_CHANGE); + + return ret; +} + +static int roce3_netdev_event_ipv6_dev_scan(struct roce3_device *rdev, struct net_device *event_netdev, + struct rdma_gid_entry *gid_entry) +{ + struct sin6_list *sin6_temp = NULL; + struct sin6_list *sin6_iter = NULL; + struct inet6_dev *in6_dev = NULL; + struct inet6_ifaddr *ifp = NULL; + struct sin6_list *entry = NULL; + int ret; + + LIST_HEAD(sin6_init_list); + + in6_dev = in6_dev_get(event_netdev); + if (in6_dev == NULL) { + return 0; + } + + read_lock_bh(&in6_dev->lock); + list_for_each_entry(ifp, &in6_dev->addr_list, if_list) + { + entry = kzalloc(sizeof(*entry), GFP_ATOMIC); + if (entry == NULL) { + continue; + } + + entry->sin6.sin6_family = AF_INET6; + entry->sin6.sin6_addr = ifp->addr; + list_add_tail(&entry->list, &sin6_init_list); + } + + read_unlock_bh(&in6_dev->lock); + in6_dev_put(in6_dev); + + list_for_each_entry_safe(sin6_iter, sin6_temp, &sin6_init_list, list) + { + memcpy((void *)gid_entry->raw, (void *)&sin6_iter->sin6.sin6_addr, sizeof(union ib_gid)); + + ret = roce3_gid_fill(rdev, gid_entry, event_netdev, sin6_iter); + if (ret != 0) { + goto err_free; + } + + list_del(&sin6_iter->list); + kfree(sin6_iter); + } + + return 0; + +err_free: + list_for_each_entry_safe(sin6_iter, sin6_temp, &sin6_init_list, list) + { + list_del(&sin6_iter->list); + kfree(sin6_iter); + } + return ret; +} +#endif + +static int roce3_netdev_event_ip_dev_scan(struct roce3_device *rdev, struct net_device *event_netdev) +{ + struct rdma_gid_entry gid_entry; + int ret; + + memset(&gid_entry, 0, sizeof(gid_entry)); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + ret = roce3_netdev_event_ipv4_dev_scan(rdev, event_netdev, &gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to scan IPv4, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } +#endif + +#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) + ret = roce3_netdev_event_ipv6_dev_scan(rdev, event_netdev, &gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to scan IPv6, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } +#endif + + return 0; +} + +static struct roce3_vlan_dev_list *roce3_find_vlan_device_list(const struct list_head *mac_list, + const struct net_device *netdev) +{ + struct roce3_vlan_dev_list *vlan_dev_list = NULL; + + list_for_each_entry(vlan_dev_list, mac_list, list) + { + if (vlan_dev_list->net_dev == netdev) { + return vlan_dev_list; + } + } + + return NULL; +} + +static int roce3_add_vlan_device(struct roce3_device *rdev, struct net_device *netdev) +{ + struct roce3_vlan_dev_list *new_list; + + new_list = (struct roce3_vlan_dev_list *)kzalloc(sizeof(*new_list), GFP_KERNEL); + if (new_list == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Malloc mac_vlan list_head is NULL, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + new_list->ref_cnt = 1; + new_list->net_dev = netdev; + new_list->vlan_id = ROCE_GID_SET_VLAN_32BIT_VLAID(((u32)rdma_vlan_dev_vlan_id(netdev))); + memcpy(new_list->mac, netdev->dev_addr, ROCE_MAC_ADDR_LEN); + INIT_LIST_HEAD(&new_list->list); + list_add_tail(&new_list->list, &rdev->mac_vlan_list_head); + + return 0; +} + +static void roce3_del_vlan_device(struct roce3_device *rdev, struct roce3_vlan_dev_list *old_list) +{ + list_del(&old_list->list); + kfree(old_list); +} + +static int roce3_update_vlan_device_mac(struct roce3_device *rdev, struct net_device *netdev) +{ + struct roce3_vlan_dev_list *old_list = NULL; + int ret; + + mutex_lock(&rdev->mac_vlan_mutex); + old_list = roce3_find_vlan_device_list(&rdev->mac_vlan_list_head, netdev); + if (old_list == NULL) { + mutex_unlock(&rdev->mac_vlan_mutex); + return 0; + } + + if (ROCE_MEMCMP(old_list->mac, netdev->dev_addr, ROCE_MAC_ADDR_LEN) != 0) { + roce3_del_vlan_device_mac(rdev, old_list); + + ret = roce3_add_vlan_device_mac(rdev, netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to add mac_vlan, func_id(%d)\n", __func__, + rdev->glb_func_id); + mutex_unlock(&rdev->mac_vlan_mutex); + return ret; + } + + memcpy(old_list->mac, netdev->dev_addr, ROCE_MAC_ADDR_LEN); + } + + mutex_unlock(&rdev->mac_vlan_mutex); + + return 0; +} + +static int roce3_update_real_device_mac(struct roce3_device *rdev, struct net_device *netdev) +{ + int ret; + + roce3_del_real_device_mac(rdev); + + ret = roce3_add_real_device_mac(rdev, netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to add real device ipsu mac, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + return 0; +} + +void roce3_clean_vlan_device_mac(struct roce3_device *rdev) +{ + struct roce3_vlan_dev_list *pos = NULL; + struct roce3_vlan_dev_list *tmp = NULL; + + mutex_lock(&rdev->mac_vlan_mutex); + list_for_each_entry_safe(pos, tmp, &rdev->mac_vlan_list_head, list) + { +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + (void)roce3_del_bond_vlan_slave_mac(rdev, pos->mac, (u16)pos->vlan_id); + } +#endif + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, pos->mac, pos->vlan_id, rdev->glb_func_id, hinic3_er_id(rdev->hwdev)); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, pos->mac, pos->vlan_id, rdev->glb_func_id, rdev->glb_func_id); + + list_del(&pos->list); + kfree(pos); + } + mutex_unlock(&rdev->mac_vlan_mutex); +} + +void roce3_clean_real_device_mac(struct roce3_device *rdev) +{ +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + (void)roce3_del_bond_real_slave_mac(rdev); + } +#endif + + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, rdev->mac, 0, rdev->glb_func_id, hinic3_er_id(rdev->hwdev)); +} + +static bool roce3_rdma_is_upper_dev_rcu(struct net_device *dev, struct net_device *upper) +{ + struct net_device *rdev_upper = NULL; + struct net_device *master = NULL; + bool ret = false; + + if ((upper == NULL) || (dev == NULL)) { + ret = false; + } else { + rdev_upper = rdma_vlan_dev_real_dev(upper); + master = netdev_master_upper_dev_get_rcu(dev); + ret = ((upper == master) || (rdev_upper && (rdev_upper == master)) || (rdev_upper == dev)); + } + + return ret; +} + +/* check bonding device */ +int roce3_is_eth_port_of_netdev(struct net_device *rdma_ndev, struct net_device *cookie) +{ + struct net_device *real_dev = NULL; + int res; + + if (rdma_ndev == NULL) { + return 0; + } + + rcu_read_lock(); + real_dev = rdma_vlan_dev_real_dev(cookie); + if (real_dev == NULL) { + real_dev = cookie; + } + + res = (roce3_rdma_is_upper_dev_rcu(rdma_ndev, cookie) || (real_dev == rdma_ndev)); + rcu_read_unlock(); + return res; +} + +int roce3_ifconfig_up_down_event_report(struct roce3_device *rdev, u8 net_event) +{ + struct ib_event event = { 0 }; + + if ((net_event == IB_EVENT_PORT_ACTIVE) && (test_and_set_bit(ROCE3_PORT_EVENT, &rdev->status) != 0)) { + return -1; + } + + if ((net_event == IB_EVENT_PORT_ERR) && (test_and_clear_bit(ROCE3_PORT_EVENT, &rdev->status) == 0)) { + return -1; + } + + event.device = &rdev->ib_dev; + event.event = net_event; + event.element.port_num = ROCE_DEFAULT_PORT_NUM; + + ib_dispatch_event(&event); + return 0; +} + +static int roce3_netdev_event_raw_dev(unsigned long event, struct roce3_device *rdev, struct net_device *event_netdev) +{ + int ret; + + if (event == NETDEV_REGISTER) { + ret = roce3_add_real_device_mac(rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to add real device mac, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + +#ifdef ROCE_VROCE_EN + if (event == NETDEV_UNREGISTER) { + roce3_del_real_device_mac(rdev); + return 0; + } +#endif + + if (event == NETDEV_CHANGEADDR) { + ret = roce3_update_real_device_mac(rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to update readl device mac, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + ret = roce3_netdev_event_ip_dev_scan(rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to scan ip_dev, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + if ((event == NETDEV_DOWN) || (event == NETDEV_UP)) { + roce3_handle_bonded_port_state_event(rdev); + } + } else { + if (event == NETDEV_DOWN) { + roce3_ifconfig_up_down_event_report(rdev, IB_EVENT_PORT_ERR); + } + if (event == NETDEV_UP) { + roce3_event_up_extend(rdev); + } + } +#else + if (event == NETDEV_DOWN) { + roce3_ifconfig_up_down_event_report(rdev, IB_EVENT_PORT_ERR); + } + if (event == NETDEV_UP) { + roce3_event_up_extend(rdev); + } +#endif + return 0; +} + +static int roce3_netdev_event_vlan_dev(unsigned long event, struct roce3_device *rdev, struct net_device *event_netdev) +{ + int ret; + + if (event == NETDEV_CHANGEADDR) { + ret = roce3_update_vlan_device_mac(rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to update vlan device mac, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + ret = roce3_netdev_event_ip_dev_scan(rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to scan vlan device ip list, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + + return 0; +} + +static bool roce3_is_port_of_net_dev(struct roce3_device *rdev, struct net_device *event_netdev) +{ +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + if (roce3_bond_is_eth_port_of_netdev(rdev, event_netdev) == 0) { + return false; + } + } else +#endif + { + if (roce3_is_eth_port_of_netdev(rdev->ndev, event_netdev) == 0) { + return false; + } + } + return true; +} + +static int roce3_netdev_event(struct notifier_block *nb, unsigned long event, void *ptr) +{ + struct net_device *event_netdev; + struct roce3_device *rdev = NULL; + struct roce3_notifier *notifier = NULL; + struct net_device *real_dev = NULL; + int ret; + + if (nb == NULL || ptr == NULL) { + goto err_out; + } + + event_netdev = netdev_notifier_info_to_dev(ptr); + if (event_netdev->type != ARPHRD_ETHER) { + goto err_out; + } + + notifier = container_of(nb, struct roce3_notifier, nb); + rdev = container_of(notifier, struct roce3_device, notifier); + + if (roce3_hca_is_present(rdev) == 0) { + goto err_out; + } + + if (!roce3_is_port_of_net_dev(rdev, (void *)event_netdev)) { + goto err_out; + } + + /* get raw netdev from event_netdev */ + real_dev = (rdma_vlan_dev_real_dev(event_netdev) != 0) ? rdma_vlan_dev_real_dev(event_netdev) : event_netdev; + if (real_dev == event_netdev) { + ret = roce3_netdev_event_raw_dev(event, rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to deal with raw device, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + } else { + ret = roce3_netdev_event_vlan_dev(event, rdev, event_netdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to deal with vlan device, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + } + +err_out: + return NOTIFY_DONE; +} + +/* **************************************************************************** + Prototype : roce3_unregister_netdev_event + Description : unregister netdev event related function + Input : struct roce3_device *rdev + Output : None + + 1.Date : 2015/6/18 + Modification : Created function + +**************************************************************************** */ +void roce3_unregister_netdev_event(struct roce3_device *rdev) +{ + int ret = 0; + struct roce3_notifier *notifier = &rdev->notifier; + + if (notifier->nb.notifier_call) { + ret = unregister_netdevice_notifier(¬ifier->nb); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to unregister netdev notifier, func_id(%d)\n", __func__, + rdev->glb_func_id); + } + + notifier->nb.notifier_call = NULL; + } +} + +/* **************************************************************************** + Prototype : roce3_register_netdev_event + Description : register netdev event related function + Input : struct roce3_device *rdev + Output : None + + 1.Date : 2015/6/18 + Modification : Created function + +**************************************************************************** */ +int roce3_register_netdev_event(struct roce3_device *rdev) +{ + struct roce3_notifier *notifier = &rdev->notifier; + int ret; + + notifier->nb.notifier_call = roce3_netdev_event; + ret = register_netdevice_notifier(¬ifier->nb); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to register netdev notifier, func_id(%d)\n", __func__, + rdev->glb_func_id); + notifier->nb.notifier_call = NULL; + return ret; + } + + return 0; +} + +static int roce3_set_gid_entry(struct roce3_device *rdev, struct rdma_gid_entry *gid_entry, + const struct ib_gid_attr *attr, const union ib_gid *gid) +{ + static enum roce3_gid_type gid_type_map[ROCE_NETWORK_GID_TYPE_MAX] = {0}; + enum rdma_network_type network_type; + enum roce3_gid_type roce_gid_type; + + gid_type_map[RDMA_NETWORK_IPV4] = ROCE_IPv4_ROCEv2_GID; + gid_type_map[RDMA_NETWORK_IPV6] = ROCE_IPv6_ROCEv2_GID; + + memset(gid_entry, 0, sizeof(*gid_entry)); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) + network_type = rdma_gid_attr_network_type(attr); + memcpy((void *)gid_entry->raw, (void *)(&attr->gid), sizeof(union ib_gid)); +#else + network_type = ib_gid_to_network_type(attr->gid_type, (union ib_gid *)gid); + memcpy((void *)gid_entry->raw, (void *)gid, sizeof(*gid)); +#endif + if ((network_type == RDMA_NETWORK_IB) || (network_type == RDMA_NETWORK_ROCE_V1)) { + pr_err("[ROCE, ERR] %s: IB or RoCE v1 is no longer supported, network_type(%d)\n", __func__, network_type); + return (-EINVAL); + } + + roce_gid_type = gid_type_map[network_type]; + roce3_fill_gid_vlan(rdev, attr->ndev, gid_entry); + roce3_fill_gid_type(gid_entry, roce_gid_type); + roce3_fill_gid_smac(attr->ndev, gid_entry); + + return 0; +} + +static int roce3_check_and_set_gid_entry(const struct ib_gid_attr *attr, const union ib_gid *gid, + struct rdma_gid_entry *gid_entry, struct roce3_device *rdev, unsigned int index) +{ + if ((cpu_to_be64(gid->global.subnet_prefix) == ROCE_DEFAULT_GID_SUBNET_PREFIX) && (index > 1)) { + return -EINVAL; + } + + memset(gid_entry, 0, sizeof(struct rdma_gid_entry)); + if (roce3_set_gid_entry(rdev, gid_entry, attr, gid) != 0) { + pr_err("[ROCE, ERR] %s: Failed to set gid entry.\n", __func__); + return (-EINVAL); + } + + return 0; +} + +/* add vlan_mac list or ref_cnt + 1 + * add mac_vlan when new list add + */ +static int roce3_notify_vlan(struct roce3_device *rdev, const struct ib_gid_attr *attr) +{ + int ret; + struct roce3_vlan_dev_list *old_list = NULL; + + mutex_lock(&rdev->mac_vlan_mutex); + printk("[ROCE] ADD vlan: Func_id:%d, Netdev:%s\n", rdev->glb_func_id, attr->ndev->name); + old_list = roce3_find_vlan_device_list(&rdev->mac_vlan_list_head, attr->ndev); + if (old_list != NULL) { + old_list->ref_cnt++; + mutex_unlock(&rdev->mac_vlan_mutex); + return 0; + } + + ret = roce3_add_vlan_device(rdev, attr->ndev); + if (ret != 0) { + mutex_unlock(&rdev->mac_vlan_mutex); + return ret; + } + + ret = roce3_add_vlan_device_mac(rdev, attr->ndev); + if (ret != 0) { + old_list = roce3_find_vlan_device_list(&rdev->mac_vlan_list_head, attr->ndev); + if (old_list) { + roce3_del_vlan_device(rdev, old_list); + } + + mutex_unlock(&rdev->mac_vlan_mutex); + return ret; + } + mutex_unlock(&rdev->mac_vlan_mutex); + + return 0; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_ib_add_gid(const struct ib_gid_attr *attr, __always_unused void **context) +#else +int roce3_ib_add_gid(const union ib_gid *gid, const struct ib_gid_attr *attr, __always_unused void **context) +#endif +{ + int ret; + struct rdma_gid_entry gid_entry; + struct roce3_device *rdev = to_roce3_dev(attr->device); /*lint !e78 !e530*/ + unsigned int index = attr->index; /*lint !e530*/ + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) + ret = roce3_check_and_set_gid_entry(attr, &(attr->gid), &gid_entry, rdev, index); /*lint !e40*/ +#else + ret = roce3_check_and_set_gid_entry(attr, gid, &gid_entry, rdev, index); +#endif + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: set gid err, func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ret; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + // 添加第一个gid时，设置ipsu mac + if (index == 0) { + ret = roce3_update_real_device_mac(rdev, attr->ndev); + if (ret != 0) { + return ret; + } + } +#endif + + ret = roce3_rdma_update_gid(rdev->hwdev, 0, index, &gid_entry); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to update gid. ret(%d),func_id(%d)\n", __func__, ret, + rdev->glb_func_id); + return ret; + } + + rdev->gid_dev[index] = attr->ndev; + + if (rdma_vlan_dev_real_dev(attr->ndev)) { + ret = roce3_notify_vlan(rdev, attr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to nofify vlan, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return ret; + } + } + + return 0; +} + +int roce3_ib_del_gid(const struct ib_gid_attr *attr, __always_unused void **context) +{ + struct roce3_vlan_dev_list *old_list = NULL; + struct roce3_device *rdev = NULL; + u32 index = 0; + + if ((attr == NULL) || (attr->device == NULL)) { /*lint !e55 !e58 !e78*/ + pr_err("[ROCE] %s: Attr or attr->device is null\n", __func__); + return (-EINVAL); + } + + rdev = to_roce3_dev(attr->device); /*lint !e78*/ + index = attr->index; + if (index >= rdev->rdma_cap.max_gid_per_port) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Invalid gid index(%u), func_id(%d)\n", __func__, index, rdev->glb_func_id); + return (-EINVAL); + } + + /* del vlan_mac list or ref_cnt - 1 */ + /* del mac_vlan when ref_cnt = 0 */ + if (rdev->ndev != rdev->gid_dev[index]) { + mutex_lock(&rdev->mac_vlan_mutex); + old_list = roce3_find_vlan_device_list(&rdev->mac_vlan_list_head, rdev->gid_dev[index]); + if (old_list) { + old_list->ref_cnt--; + if (old_list->ref_cnt == 0) { + roce3_del_vlan_device_mac(rdev, old_list); + + roce3_del_vlan_device(rdev, old_list); + } + } + mutex_unlock(&rdev->mac_vlan_mutex); + } + /* + * delete gid no longer send cmd to ucode which write 0s to target entry, + * preventing PPE from building malformed packets. */ + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/roce_netdev.h b/drivers/infiniband/hw/hiroce3/roce_netdev.h new file mode 100644 index 000000000..6821ec390 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_netdev.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_netdev.h + * Version : v1.0 + * Created : 2021/1/27 + * Last Modified : 2022/1/27 + * Description : The definition of RoCE async event relatedfunction prototypes, macros etc. + */ + +#ifndef ROCE_NETDEV_H +#define ROCE_NETDEV_H + +#include <net/ipv6.h> +#include <net/bonding.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/inetdevice.h> +#include <linux/if_vlan.h> + +#include <rdma/ib_user_verbs.h> +#include <rdma/ib_addr.h> + +#include "roce.h" +#include "roce_compat.h" +#include "roce_mix.h" +#include "roce_cmd.h" + +#ifdef ROCE_BONDING_EN +#include "hinic3_srv_nic.h" +#endif + +#define ROCE_GID_SET_VLAN_32BIT_VLAID(vlan_id) ((vlan_id) | (((u32)1) << 31)) /* the 31 bit is vlan eable bit */ +#define ROCE_MAC_ADDR_LEN 6 + +/* ipv4 header len. unit:4B */ +#define IPV4_HDR_LEN 5 + +#define ROCE_DEFAULT_GID_SUBNET_PREFIX 0xFE80000000000000ULL + +#define ROCE_GID_MAP_TBL_IDX_GET(tunnel, tag, new_gid_type) ((u8)(((tunnel) << 4) | ((tag) << 2) | (new_gid_type))) + +#define ROCE_GID_MAP_TBL_IDX2 2 + +#define ROCE_NETWORK_GID_TYPE_MAX 4 + +enum roce3_gid_tunnel_type { + ROCE_GID_TUNNEL_INVALID = 0, + ROCE_GID_TUNNEL_VALID +}; + +enum roce3_gid_vlan_type { + ROCE_GID_VLAN_INVALID = 0, + ROCE_GID_VLAN_VALID +}; + +struct roce3_vlan_dev_list { + u8 mac[6]; + u32 vlan_id; + u32 ref_cnt; + struct net_device *net_dev; + struct list_head list; +}; + +#endif /* ROCE_NETDEV_H */ diff --git a/drivers/infiniband/hw/hiroce3/roce_netlink.c b/drivers/infiniband/hw/hiroce3/roce_netlink.c new file mode 100755 index 000000000..50d138c3f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_netlink.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * + * File Name : roce_netlink.c + * Version : v2.0 + * Created : 2023/8/29 + * Last Modified : 2023/8/29 + * Description : The definition of RoCE CHar device related functions. + */ + +#include <net/net_namespace.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/netlink.h> + +#include "roce_mix.h" +#include "roce_cmd.h" +#include "roce_netlink.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#ifdef ROCE_EXTEND +#include "roce_qp_extension.h" +#endif + +#ifdef ROCE_NETLINK_EN + +static hiroce_netlink_dev_s g_roce_adapter = {0, 0}; + +hiroce_netlink_dev_s *hiroce_get_adp(void) +{ + return &g_roce_adapter; +} + +int roce3_drv_cmd_execute(struct sk_buff *skb, struct genl_info *nl_info); + +static void roce3_nlahdr_push(struct sk_buff *skb, u16 type) +{ + u16 attrlen = (u16)skb->len; + struct nlattr *nlahdr; + u32 padlen = nla_padlen(attrlen); + + nlahdr = (struct nlattr *)skb_push(skb, NLA_HDRLEN); + nlahdr->nla_len = (u16)nla_attr_size(attrlen); + nlahdr->nla_type = type; + + if ((skb->end - skb->tail) >= padlen) { + (void)skb_put(skb, padlen); + } + + return; +} + +static struct nlmsghdr *nlmsg_push(struct sk_buff *skb, u32 portid, u32 seq, int type, int len, int flags) +{ + struct nlmsghdr *nlh; + u32 size = (u32)nlmsg_msg_size(len); + + nlh = (struct nlmsghdr *)skb_push(skb, NLMSG_ALIGN(size)); + if (nlh == NULL) { + return NULL; + } + + nlh->nlmsg_type = (u16)type; + nlh->nlmsg_len = skb->len; + nlh->nlmsg_flags = (u16)flags; + nlh->nlmsg_pid = portid; + nlh->nlmsg_seq = seq; + + if (!__builtin_constant_p(size) || NLMSG_ALIGN(size) - size != 0) { + memset((char *)nlmsg_data(nlh) + len, 0, NLMSG_ALIGN(size) - size); + } + + return nlh; +} + +static inline struct nlmsghdr *roce3_nlmsg_push(struct sk_buff *skb, u32 portid, u32 seq, int type, int payload, + int flags) +{ + if (unlikely(skb_headroom(skb) < (unsigned int)nlmsg_total_size(payload))) { + return NULL; + } + + return nlmsg_push(skb, portid, seq, type, payload, flags); +} + +static void *roce3_genlmsg_push(struct sk_buff *skb, u32 portid, u32 seq, const struct genl_family *family, int flags, + u8 cmd) +{ + struct nlmsghdr *nlh; + struct genlmsghdr *hdr = NULL; + + nlh = roce3_nlmsg_push(skb, portid, seq, (int)family->id, (int)(GENL_HDRLEN + family->hdrsize), flags); + if (nlh == NULL) { + return NULL; + } + + hdr = nlmsg_data(nlh); + hdr->cmd = cmd; + hdr->version = (u8)family->version; + hdr->reserved = 0; + + return (void *)nlh; +} + +static long roce3_netlink_query_dcb(struct roce3_device *rdev, union roce3_query_dcb_buf * buf_in, + union roce3_query_dcb_buf * dcb_buf) +{ + int ret; + int get_group_id; + struct roce_group_id group_id = {0}; + roce3_get_cos_inbuf_s in_buf; + u8 cos; + +#ifdef ROCE_BONDING_EN + if (roce3_bond_get_dcb_info(rdev) != 0) { + pr_err("[ROCE, ERR] %s: Failed to get dcb info\n", __func__); + return (-EINVAL); + } +#endif + in_buf.port_num = buf_in->cmd.port; + in_buf.sl = buf_in->cmd.sl; + in_buf.sgid_index = buf_in->cmd.sgid_idx; + in_buf.traffic_class = buf_in->cmd.traffic_class; + ret = roce3_get_dcb_cfg_cos(rdev, &in_buf, &cos); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get cos from dcb info, ret:%d\n", __func__, ret); + return ret; + } + + dcb_buf->resp.cos = cos; + + if (rdev->is_vroce) { + get_group_id = roce3_get_group_id(rdev->glb_func_id, rdev->hwdev, &group_id); + if (get_group_id != 0) { + pr_warn("Failed to get group id, ret(%d)", get_group_id); + } else { + rdev->group_rc_cos = group_id.group_rc_cos; + rdev->group_ud_cos = group_id.group_ud_cos; + rdev->group_xrc_cos = group_id.group_xrc_cos; + } + if (buf_in->cmd.dscp_type == (u8)IB_QPT_RC) { + dcb_buf->resp.cos = rdev->group_rc_cos & MAX_COS_NUM; + } else if (buf_in->cmd.dscp_type == (u8)IB_QPT_UD) { + dcb_buf->resp.cos = rdev->group_ud_cos & MAX_COS_NUM; + } else { + dcb_buf->resp.cos = rdev->group_xrc_cos & MAX_COS_NUM; + } + } + + return 0; +} + +int roce3_drv_dcb_info_get(void *buf_in, void *buf_out, u32 *out_size) +{ + hiroce_dev_dcbinfo_get_s *cmd; + hiroce_dev_dcbinfo_rsp_s *rsp; + struct roce3_device *rdev = NULL; + int offset = 0; + int ret; + + cmd = (hiroce_dev_dcbinfo_get_s *)buf_in; + rsp = (hiroce_dev_dcbinfo_rsp_s *)buf_out; + offset = get_instance_of_func_id(cmd->func_id); + rdev = hiroce_get_adp()->netlink->rdev[offset]; + if (rdev == NULL) { + pr_err("[ROCE, ERR]: offset is invild, please check\n"); + return -EINVAL; + } + ret = roce3_netlink_query_dcb(rdev, &cmd->dcb_info, &rsp->dcb_info); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get dcb info, ret:%d\n", __func__, ret); + return ret; + } + rsp->hdr.cmd = HIROCE_DRV_CMD_DCB_GET; + rsp->hdr.msg_len = (u32)sizeof(*rsp); + rsp->hdr.err_code = 0; + *out_size = (u32)sizeof(*rsp); + + return 0; +} + +static long roce3_netlink_create_ah(struct roce3_device *rdev, union roce3_create_ah_buf *buf, + union roce3_create_ah_buf *rsp) +{ + struct rdma_ah_attr attr; + struct ib_udata udata; + + attr.sl = buf->cmd.attr.sl; + attr.static_rate = buf->cmd.attr.static_rate; + attr.ah_flags = (buf->cmd.attr.is_global != 0) ? IB_AH_GRH : 0; + attr.port_num = buf->cmd.attr.port_num; + attr.grh.flow_label = buf->cmd.attr.grh.flow_label; + attr.grh.sgid_index = buf->cmd.attr.grh.sgid_index; + attr.grh.hop_limit = buf->cmd.attr.grh.hop_limit; + attr.grh.traffic_class = buf->cmd.attr.grh.traffic_class; + memset(attr.roce.dmac, 0, sizeof(attr.roce.dmac)); + memcpy(attr.grh.dgid.raw, buf->cmd.attr.grh.dgid, ROCE_GID_LEN); + + memset(&udata, 0, sizeof(struct ib_udata)); + if (roce3_resolve_grh(rdev, &attr, &buf->resp.vlan_id, &udata) != 0) { + pr_err("[ROCE, ERR] %s: Failed to resolve grh\n", __func__); + return -EINVAL; + } + + memcpy(buf->resp.dmac, attr.roce.dmac, ETH_ALEN); + memcpy(rsp, buf, sizeof(*buf)); + + return 0; +} + +int roce3_drv_create_ah(void *buf_in, void *buf_out, u32 *out_size) +{ + hiroce_dev_ah_info_s *cmd; + hiroce_dev_ah_info_s *rsp; + struct roce3_device *rdev = NULL; + int offset; + int ret; + + cmd = (hiroce_dev_ah_info_s *)buf_in; + rsp = (hiroce_dev_ah_info_s *)buf_out; + offset = get_instance_of_func_id(cmd->func_id); + rdev = hiroce_get_adp()->netlink->rdev[offset]; + if (rdev == NULL) { + pr_err("[ROCE, ERR]: offset is invild, please check\n"); + return -EINVAL; + } + ret = roce3_netlink_create_ah(rdev, &cmd->ah_info, &rsp->ah_info); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to create ah, ret:%d\n", __func__, ret); + return ret; + } + rsp->hdr.cmd = HIROCE_DRV_CMD_CREATE_AH; + rsp->hdr.msg_len = (u32)sizeof(*rsp); + rsp->hdr.err_code = 0; + *out_size = (u32)sizeof(*rsp); + + return 0; +} + +static int roce3_drv_cmd_process(usrnl_drv_msg_hdr_s *hdr, struct sk_buff *reply, u32 *out_size) +{ + int ret = 0; + void *buf_out = (void *)reply->data; + void *buf_in = (void *)hdr; + + switch (hdr->cmd) { + case HIROCE_DRV_CMD_DCB_GET: + ret = roce3_drv_dcb_info_get(buf_in, buf_out, out_size); + break; + case HIROCE_DRV_CMD_CREATE_AH: + ret = roce3_drv_create_ah(buf_in, buf_out, out_size); + break; + default: + pr_err("invalid drv cmd:0x%x", hdr->cmd); + ret = -EINVAL; + break; + } + return ret; +} + +static const struct nla_policy roce3_policy[USRNL_GENL_ATTR_MAX + 1] = { + [USRNL_GENL_ATTR] = { .type = NLA_UNSPEC }, //lint !e26 +}; + +static const struct genl_ops roce3_genl_ops[] = { + { .cmd = USRNL_DEV_DRV_CMD_EXECUTE, + .flags = CAP_NET_ADMIN, /* Requires CAP_NET_ADMIN privilege. */ + .policy = roce3_policy, + .doit = roce3_drv_cmd_execute, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) + .validate = GENL_DONT_VALIDATE_STRICT +#endif + }, +}; + +/* + * Netlink Ops + */ +#define ROCE_GENL_OPS_ARRAY_SIZE 1 + +static struct genl_family roce3_genl_family = { + .hdrsize = 0, + .name = ROCE3_FAMILY, + .version = ROCE3_VERSION, + .maxattr = USRNL_GENL_ATTR_MAX, + .netnsok = true, + .parallel_ops = true, + .ops = roce3_genl_ops, + .n_ops = ROCE_GENL_OPS_ARRAY_SIZE, +}; + +struct genl_family *roce3_genl_families[] = { + &roce3_genl_family, +}; + +int roce3_drv_cmd_execute(struct sk_buff *skb, struct genl_info *nl_info) +{ + u8 cmd; + int rc; + u32 out_size = 0; + struct sk_buff *reply = NULL; + struct nlattr *cmd_attr; + usrnl_drv_msg_hdr_s *hdr = NULL; + struct nlattr **ppstAttr = nl_info->attrs; + + cmd_attr = ppstAttr[USRNL_GENL_ATTR]; + if (cmd_attr == NULL) { + pr_err("[ROCE, ERR] %s: Do drv cmd failed for NULL attr!", __func__); + return -ENOMEM; + } + + hdr = (usrnl_drv_msg_hdr_s *)nla_data(cmd_attr); + + reply = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); + if (reply == NULL) { + pr_err("Alloc reply buf for drv cmd:%d failed!", hdr->cmd); + return -ENOMEM; + } + skb_reserve(reply, NLMSG_HDRLEN + GENL_HDRLEN + NLA_HDRLEN); + + cmd = hdr->cmd; + rc = roce3_drv_cmd_process(hdr, reply, &out_size); + if (rc != 0) { + pr_err("Do drv cmd:%u failed, errcode %d", cmd, rc); + nlmsg_free(reply); + return -EIO; + } + + hdr = (usrnl_drv_msg_hdr_s *)reply->data; + hdr->msg_len = out_size; + hdr->cmd = cmd; + (void)skb_put(reply, out_size); + + roce3_nlahdr_push(reply, USRNL_GENL_ATTR); + roce3_genlmsg_push(reply, nl_info->snd_portid, nl_info->snd_seq, &roce3_genl_family, 0, USRNL_DEV_DRV_CMD_EXECUTE); + genlmsg_reply(reply, nl_info); + + return rc; +} + +/* pf use 32, vf use 96 */ +int get_instance_of_func_id(int glb_func_id) +{ + return glb_func_id > PF_MAX_SIZE ? glb_func_id % VF_USE_SIZE + PF_MAX_SIZE : + glb_func_id; +} + +int roce3_netlink_init(void) +{ + int err; + + err = genl_register_family(&roce3_genl_family); + + return err; +} + +void roce3_netlink_unit(void) +{ + genl_unregister_family(&roce3_genl_family); + + return ; +} + +#endif //ROCE_NETLINK_EN \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/roce_netlink.h b/drivers/infiniband/hw/hiroce3/roce_netlink.h new file mode 100644 index 000000000..139970d08 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_netlink.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * + * File Name : roce_netlink.h + * Version : v2.0 + * Created : 2023/8/29 + * Last Modified : 2023/8/29 + * Description : The definition of RoCE CHar device related functions. + */ + +#ifndef _ROCE_NETLINK_H_ +#define _ROCE_NETLINK_H_ +#ifdef ROCE_NETLINK_EN +#include <net/netlink.h> +#include <net/net_namespace.h> +#include <linux/netlink.h> + +#include "udk_usrnl.h" +#include "roce_k_ioctl.h" +#include "roce.h" + +#define USRNL_GENL_ATTR_MAX (__USRNL_GENL_ATTR_MAX - 1) + +/* netlink server info in roce ko */ +#define ROCE3_FAMILY "ROCE" +#define ROCE3_VERSION 0x1 +#define ROCE_MAX_FUNCTION 128 +#define PF_MAX_SIZE 32 +#define VF_USE_SIZE 96 + +#define P2PCOS_MAX_VALUE 2 +#define MAX_COS_NUM 0x7 + +#ifndef __NET_GENERIC_NETLINK_H +/* 解决genentlink 头文件冲突问题 */ + struct genlmsghdr { + u8 cmd; + u8 version; + u16 reserved; +}; +#define USER_PTR_SIZE 2 + +/* length of family name */ + +#define GENL_NAMSIZ 16 +#define GENL_HDRLEN NLMSG_ALIGN(sizeof(struct genlmsghdr)) + +struct genl_info { + u32 snd_seq; + u32 snd_portid; + struct nlmsghdr *nlhdr; + struct genlmsghdr *genlhdr; + void *userhdr; + struct nlattr **attrs; + possible_net_t _net; + void *user_ptr[USER_PTR_SIZE]; + struct netlink_ext_ack *extack; +}; + +struct genl_ops { + int (*doit)(struct sk_buff *skb, struct genl_info *info); + int (*start)(struct netlink_callback *cb); + int (*dumpit)(struct sk_buff *skb, struct netlink_callback *cb); + int (*done)(struct netlink_callback *cb); + const struct nla_policy *policy; + unsigned int maxattr; + u8 cmd; + u8 internal_flags; + u8 flags; + u8 validate; +}; + +struct genl_small_ops { + int (*doit)(struct sk_buff *skb, struct genl_info *info); + int (*dumpit)(struct sk_buff *skb, struct netlink_callback *cb); + u8 cmd; + u8 internal_flags; + u8 flags; + u8 validate; +}; + +struct genl_multicast_group { + char name[GENL_NAMSIZ]; +}; + +struct genl_family { +/* private */ + int id; + unsigned int hdrsize; + char name[GENL_NAMSIZ]; + unsigned int version; + unsigned int maxattr; + unsigned int mcgrp_offset; + u8 netnsok : 1; + u8 parallel_ops : 1; + u8 n_ops; + u8 n_small_ops; + u8 n_mcgrps; + const struct nla_policy *policy; + int (*pre_doit)(const struct genl_ops *ops, + struct sk_buff *skb, + struct genl_info *info); + void (*post_doit)(const struct genl_ops *ops, + struct sk_buff *skb, + struct genl_info *info); + const struct genl_ops * ops; + const struct genl_small_ops *small_ops; + const struct genl_multicast_group *mcgrps; + struct module *module; +}; + +static inline int genlmsg_unicast(struct net *net, struct sk_buff *skb, u32 portid) +{ + return nlmsg_unicast(net->genl_sock, skb, portid); +} + +static inline struct net *genl_info_net(struct genl_info *info) +{ + return read_pnet(&info->_net); +} + +static inline int genlmsg_reply(struct sk_buff *skb, struct genl_info *info) +{ + return genlmsg_unicast(genl_info_net(info), skb, info->snd_portid); +} +extern int genl_register_family(struct genl_family *family); +extern int genl_unregister_family(const struct genl_family *family); + +#endif +enum hiroce_drv_cmd_type { + HIROCE_DRV_CMD_DCB_GET = 100, + HIROCE_DRV_CMD_CREATE_AH, + HIROCE_DRV_CMD_MAX +}; + +typedef struct hiroce_dev_dcbinfo_get { + usrnl_drv_msg_hdr_s hdr; + union roce3_query_dcb_buf dcb_info; + uint16_t func_id; + uint16_t rsvd; +}hiroce_dev_dcbinfo_get_s; + +typedef struct hiroce_dev_dcbinfo_rsp { + usrnl_drv_msg_hdr_s hdr; + union roce3_query_dcb_buf dcb_info; +}hiroce_dev_dcbinfo_rsp_s; + +typedef struct hiroce_dev_ah_info { + usrnl_drv_msg_hdr_s hdr; + union roce3_create_ah_buf ah_info; + uint16_t func_id; + uint16_t rsvd; +}hiroce_dev_ah_info_s; + +typedef struct netlink_dev { + struct roce3_device *rdev[ROCE_MAX_FUNCTION]; +}netlink_dev_s; + +typedef struct hiroce_netlink_dev { + int used_dev_num; + netlink_dev_s *netlink; + struct mutex mutex_dev; +}hiroce_netlink_dev_s; + +int get_instance_of_func_id(int glb_func_id); +hiroce_netlink_dev_s *hiroce_get_adp(void); +int roce3_netlink_init(void); +void roce3_netlink_unit(void); + +#endif // ROCE_NETLINK_EN +#endif diff --git a/drivers/infiniband/hw/hiroce3/roce_pd.c b/drivers/infiniband/hw/hiroce3/roce_pd.c new file mode 100644 index 000000000..2d75f9c8b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_pd.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_pd.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : implement of alloc and dealloc of pd + */ + +#include <linux/slab.h> + +#include "roce.h" +#include "roce_main_extension.h" +#include "roce_pd.h" + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) +{ + int ret; + struct roce3_pd *pd = to_roce3_pd(ibpd); + struct roce3_device *rdev = to_roce3_dev(ibpd->device); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = roce3_rdma_pd_alloc(rdev->hwdev, &pd->pdn); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc pdn, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + goto err_out; + } + + pd->func_id = rdev->glb_func_id; + if (udata) { + if (ib_copy_to_udata(udata, &pd->pdn, PD_RESP_SIZE) != 0) { + ret = -EFAULT; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data to user space, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_copy_to_user; + } + } + + return 0; + +err_copy_to_user: + roce3_rdma_pd_free(rdev->hwdev, pd->pdn); +err_out: + return ret; +} +#else +struct ib_pd *roce3_alloc_pd(struct ib_device *ibdev, struct ib_ucontext *ibcontext, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + if (ibdev == NULL) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Ibdev is null\n", __func__); + goto err_out; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + ret = -EPERM; + goto err_out; + } + + pd = (struct roce3_pd *)kmalloc(sizeof *pd, GFP_KERNEL); + if (pd == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for roce pd, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + + ret = roce3_rdma_pd_alloc(rdev->hwdev, &pd->pdn); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc pdn, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + goto err_alloc_pdn; + } + + pd->func_id = rdev->glb_func_id; + if (ibcontext) { + if (ib_copy_to_udata(udata, &pd->pdn, PD_RESP_SIZE) != 0) { + ret = -EFAULT; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data to user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_copy_to_user; + } + } + + return &pd->ibpd; + +err_copy_to_user: + roce3_rdma_pd_free(rdev->hwdev, pd->pdn); + +err_alloc_pdn: + kfree(pd); + +err_out: + return (struct ib_pd *)ERR_PTR((long)ret); +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) +#else +int roce3_dealloc_pd(struct ib_pd *ibpd) +#endif +{ + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + if (ibpd == NULL) { + pr_err("[ROCE, ERR] %s: Ibpd is null\n", __func__); + return -EINVAL; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + + roce3_rdma_pd_free(rdev->hwdev, pd->pdn); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + kfree(pd); +#endif + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/roce_pd.h b/drivers/infiniband/hw/hiroce3/roce_pd.h new file mode 100644 index 000000000..397489d9c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_pd.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_pd.h + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : struct related to pd + */ + +#ifndef ROCE_PD_H +#define ROCE_PD_H + +#include <rdma/ib_verbs.h> + +#include "roce.h" + +#define PD_RESP_SIZE (2 * sizeof(u32)) +struct roce3_pd { + struct ib_pd ibpd; + u32 pdn; + u16 func_id; + u16 rsvd; +}; + +static inline struct roce3_pd *to_roce3_pd(const struct ib_pd *ibpd) +{ + return container_of(ibpd, struct roce3_pd, ibpd); +} + +#endif // ROCE_PD_H diff --git a/drivers/infiniband/hw/hiroce3/roce_sysfs.c b/drivers/infiniband/hw/hiroce3/roce_sysfs.c new file mode 100755 index 000000000..cc3b1fb91 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_sysfs.c @@ -0,0 +1,1787 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_sysfs.c + * Version : v2.0 + * Created : 2021/3/14 + * Last Modified : 2022/02/19 + * Description : RoCE sysfs for cc_algo. + */ + +#include <linux/types.h> + +#include "hinic3_hw.h" +#include "rdma_context_format.h" +#include "roce.h" +#include "roce_dfx.h" +#include "roce_cmd.h" +#include "roce_qp.h" + +#include "roce_sysfs.h" + +#define ROCE_DEFAULT_IP_EABLE_EN 1 +#define ROCE_DEFAULT_IP_EABLE_DIS 0 +#define ROCE_DEFAULT_MIN_CNP_PERIOD 16 +#define ROCE_DEFAULT_ALPHA_DEC_PERIOD 160 +#define ROCE_DEFAULT_RATE_DEC_PERIOD 32 +#define ROCE_DEFAULT_RATE_INC_PERIOD 480 +#define ROCE_DEFAULT_ALPHA_THRESHOLD 4 // 32, uint 8 +#define ROCE_DEFAULT_CNP_CNT_THRESHOLD 6 +#define ROCE_DEFAULT_PORT_MODE_25G 0 +#define ROCE_DEFAULT_FACTOR_GITA 7 +#define ROCE_DEFAULT_INITIAL_ALPHA 1023 +#define ROCE_DEFAULT_RATE_INC_AI 2 +#define ROCE_DEFAULT_RATE_INC_HAI 8 +#define ROCE_DEFAULT_RATE_FIRST_SET 1024 +#define ROCE_DEFAULT_RATE_TARGET_CLAMP 1 +#define ROCE_DEFAULT_QUICK_AJ_ENABLE 0 +#define ROCE_DEFAULT_CNP_PRIO_ENABLE 0 +#define ROCE_DEFAULT_CNP_PRIO 0 +#define ROCE_DEFAULT_TOKEN_PERIOD 16 +#define ROCE_DEFAULT_MIN_RATE 1 +#define ROCE_DEFAULT_WND_RESET_RATIO 0 +#define ROCE_DEFAULT_WND_RESET_TIMEOUT 0 +#define ROCE_PORT_MODE_MASK 0xfffffffe +#define ROCE_QUICK_AJ_EN_MASK 0xfffffffe +#define ROCE_CNP_PRIO_EN_MASK 0xfffffffe +#define ROCE_RT_CLAMP_MASK 0xfffffffe +#define ROCE_PRIO_EN_MASK 0xfffffffe +#define ROCE_MIN_RATE_INC_HAI 1 +#define ROCE_MAX_RATE_INC_HAI 255 +#define ROCE_MIN_RATE_INC_AI 1 +#define ROCE_MAX_RATE_INC_AI 63 +#define ROCE_MIN_INITIAL_ALPHA 127 +#define ROCE_MAX_INITIAL_ALPHA 1023 +#define ROCE_MIN_RATE_INC_PERIOD 1 +#define ROCE_MAX_RATE_INC_PERIOD 1024 +#define ROCE_MIN_ALPHA_DEC_PERIOD 1 +#define ROCE_MAX_ALPHA_DEC_PERIOD 1024 +#define ROCE_MIN_TOKEN_PERIOD 4 +#define ROCE_MAX_TOKEN_PERIOD 255 +#define ROCE_MIN_FLOW_MIN_RATE 1 +#define ROCE_MAX_FLOW_MIN_RATE 64 +#define ROCE_MIN_WND_RESET_RATIO 0 +#define ROCE_MAX_WND_RESET_RATIO 0xf +#define ROCE_MIN_WND_RESET_TIMEOUT 0 +#define ROCE_MAX_WND_RESET_TIMEOUT 0xf +#define ROCE_MIN_ALPHA_THRESHOLD 8 +#define ROCE_MAX_ALPHA_THRESHOLD 248 +#define ROCE_MIN_CNP_CNT_THRESHOLD 1 +#define ROCE_MAX_CNP_CNT_THRESHOLD 15 +#define ROCE_MIN_RATE_DEC_PERIOD 1 +#define ROCE_MAX_RATE_DEC_PERIOD 255 +#define ROCE_MIN_MIN_CNP_PERIOD 1 +#define ROCE_MAX_MIN_CNP_PERIOD 255 +#define ROCE_MIN_FACTOR_GITA 1 +#define ROCE_MAX_FACTOR_GITA 15 +#define ROCE_MIN_RATE_FIRST_SET 128 +#define ROCE_MAX_RATE_FIRST_SET 8191 + +#define MAX_STRING_FORMAT_LEN 64 + +/* ECN VER */ +#define ECN_VER_DCQCN 0 +#define ECN_VER_PATHQCN 1 + +enum { + ROCE_DCQCN_NP = 0, + ROCE_DCQCN_RP = 1 +}; + +#define to_roce3_ecn_ctx(_kobj) container_of(_kobj, struct roce3_ecn_ctx, ecn_root) +#define to_roce3_ecn_np_ctx(_kobj) container_of(_kobj, struct roce3_ecn_np_ctx, ecn_np_root) +#define to_roce3_ecn_rp_ctx(_kobj) container_of(_kobj, struct roce3_ecn_rp_ctx, ecn_rp_root) + +#define INIT_ROCE_KOBJ_ATTR(_name, _mode, _show, _store) \ + { \ + .attr = { .name = __stringify(_name), .mode = _mode }, \ + .show = (_show), \ + .store = (_store), \ + } + +#define ROCE_ATTR_RW(_name, _show, _store) \ + static struct kobj_attribute roce_attr_##_name = \ + INIT_ROCE_KOBJ_ATTR(_name, (S_IWUSR | S_IRUSR | S_IRGRP), _show, _store) + +#define ROCE_ATTR_PTR(_name) (&roce_attr_##_name.attr) + +static int roce3_update_cfg_ccf_param(struct roce3_device *rdev, const struct roce3_ecn_ctx *ecn_ctx) +{ + const struct roce3_prio_enable_ctx *prio_enable_ctx = NULL; + const struct roce3_ip_prio_enable_ctx *ip_prio_enable_ctx = NULL; + struct roce_ccf_param ccf_param; + int ret, i; + + memset(&ccf_param, 0, sizeof(ccf_param)); + + for (i = 0; i < PRI_ARRAY_LEN; i++) { + prio_enable_ctx = &ecn_ctx->np_ctx.enable_ctx.prio_enable[i]; + ccf_param.dw0.bs.np_enable |= (prio_enable_ctx->prio_en << prio_enable_ctx->prio); + prio_enable_ctx = &ecn_ctx->rp_ctx.enable_ctx.prio_enable[i]; + ccf_param.dw0.bs.rp_enable |= (prio_enable_ctx->prio_en << prio_enable_ctx->prio); + ip_prio_enable_ctx = &ecn_ctx->ip_enable_ctx.ip_prio_enable[i]; + ccf_param.dw0.bs.ip_enable |= (ip_prio_enable_ctx->prio_en << ip_prio_enable_ctx->prio); + } + + ccf_param.dw0.bs.cnp_prio_enable = ecn_ctx->np_ctx.cnp_prio_enable; + ccf_param.dw0.bs.port_mode = ecn_ctx->np_ctx.port_mode; + ccf_param.dw1.bs.cnp_prio = ecn_ctx->np_ctx.cnp_prio; + ccf_param.dw1.bs.cnp_cos = roce3_get_db_cos_from_vlan_pri(rdev, ccf_param.dw1.bs.cnp_prio); + ccf_param.dw1.bs.ccf_appid = ecn_ctx->cc_algo; + + ret = roce3_set_cfg_ccf_param(rdev->hwdev, rdev->glb_func_id, (u32 *)&ccf_param); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to set ccf param, func_id(%d) ret(%d)\n", rdev->glb_func_id, + ret); + } + + return ret; +} + +static int roce3_update_dcqcn_param(struct roce3_device *rdev, const struct roce3_ecn_ctx *ecn_ctx) +{ + struct roce_dcqcn_param dcqcn_param; + int ret; + + memset(&dcqcn_param, 0, sizeof(dcqcn_param)); + + dcqcn_param.dw0.bs.token_period = ecn_ctx->rp_ctx.token_period; + dcqcn_param.dw0.bs.flow_min_rate = ecn_ctx->rp_ctx.min_rate; + dcqcn_param.dw1.bs.rate_inc_period = ecn_ctx->rp_ctx.rate_inc_period; + dcqcn_param.dw1.bs.alpha_threshold = ecn_ctx->rp_ctx.alpha_threshold; + dcqcn_param.dw1.bs.cnp_cnt_threshold = ecn_ctx->rp_ctx.cnp_cnt_threshold; + dcqcn_param.dw1.bs.alpha_dec_period = ecn_ctx->rp_ctx.alpha_dec_period; + dcqcn_param.dw2.bs.rate_inc_ai = ecn_ctx->rp_ctx.rate_inc_ai; + dcqcn_param.dw2.bs.rate_inc_hai = ecn_ctx->rp_ctx.rate_inc_hai; + dcqcn_param.dw2.bs.rate_dec_period = ecn_ctx->rp_ctx.rate_dec_period; + dcqcn_param.dw2.bs.min_cnp_period = ecn_ctx->np_ctx.min_cnp_period; + dcqcn_param.dw3.bs.factor_gita = ecn_ctx->rp_ctx.factor_gita; + dcqcn_param.dw3.bs.rt_clamp = ecn_ctx->rp_ctx.rate_target_clamp; + dcqcn_param.dw3.bs.initial_alpha = ecn_ctx->rp_ctx.initial_alpha; + // adjust_en + dcqcn_param.dw3.bs.rate_first_set = ecn_ctx->rp_ctx.rate_first_set; + + ret = roce3_set_cfg_dcqcn_param(rdev->hwdev, rdev->glb_func_id, (u32 *)(void *)&dcqcn_param); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to set dcqcn param, func_id(%d), ret(%d)\n", rdev->glb_func_id, + ret); + } + + return ret; +} + +static int roce3_update_ipqcn_param(struct roce3_device *rdev, const struct roce3_ecn_ctx *ecn_ctx) +{ + struct roce_ipqcn_param ipqcn_param; + int ret; + + memset(&ipqcn_param, 0, sizeof(ipqcn_param)); + + ipqcn_param.dw0.bs.token_period = ecn_ctx->rp_ctx.token_period; + ipqcn_param.dw0.bs.flow_min_rate = ecn_ctx->rp_ctx.min_rate; + ipqcn_param.dw1.bs.rate_inc_period = ecn_ctx->rp_ctx.rate_inc_period; + ipqcn_param.dw1.bs.alpha_threshold = ecn_ctx->rp_ctx.alpha_threshold; + ipqcn_param.dw1.bs.cnp_cnt_threshold = ecn_ctx->rp_ctx.cnp_cnt_threshold; + ipqcn_param.dw1.bs.alpha_dec_period = ecn_ctx->rp_ctx.alpha_dec_period; + ipqcn_param.dw2.bs.rate_inc_ai = ecn_ctx->rp_ctx.rate_inc_ai; + ipqcn_param.dw2.bs.rate_inc_hai = ecn_ctx->rp_ctx.rate_inc_hai; + ipqcn_param.dw2.bs.rate_dec_period = ecn_ctx->rp_ctx.rate_dec_period; + ipqcn_param.dw2.bs.min_cnp_period = ecn_ctx->np_ctx.min_cnp_period; + ipqcn_param.dw3.bs.factor_gita = ecn_ctx->rp_ctx.factor_gita; + ipqcn_param.dw3.bs.rt_clamp = ecn_ctx->rp_ctx.rate_target_clamp; + ipqcn_param.dw3.bs.initial_alpha = ecn_ctx->rp_ctx.initial_alpha; + ipqcn_param.dw3.bs.rate_first_set = ecn_ctx->rp_ctx.rate_first_set; + + ret = roce3_set_cfg_ipqcn_param(rdev->hwdev, rdev->glb_func_id, (u32 *)(void *)&ipqcn_param); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] : Failed to set ipqcn param, func_id(%d) ret(%d)\n", rdev->glb_func_id, + ret); + } + + return ret; +} + +typedef int (*roce3_update_param_t)(struct roce3_device *rdev, const struct roce3_ecn_ctx *ecn_ctx); + +static roce3_update_param_t roce3_update_param_funcs[] = { + roce3_update_cfg_ccf_param, + roce3_update_dcqcn_param, + roce3_update_ipqcn_param, +}; + +int roce3_update_ecn_param(const struct roce3_ecn_ctx *ecn_ctx) +{ + unsigned int i; + int ret = 0; + struct roce3_device *rdev = container_of(ecn_ctx, struct roce3_device, ecn_ctx); + + for (i = 0; i < (sizeof(roce3_update_param_funcs) / sizeof(roce3_update_param_t)); i++) { + ret = roce3_update_param_funcs[i](rdev, ecn_ctx); + if (ret != 0) { + ret = -EINVAL; + } + } + + return ret; +} + +static ssize_t roce3_show_cc_algo(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj); + + if ((attr == NULL) || (buf == NULL)) { + pr_err("[ROCE] %s: attr or buf is null\n", __func__); + return -EINVAL; + } + + switch ((int)ecn_ctx->cc_algo) { + case ROCE_CC_DISABLE: + return sprintf(buf, "%s\n", "disable"); + case ROCE_CC_DCQCN_ALGO: + return sprintf(buf, "%s\n", "dcqcn"); + case ROCE_CC_LDCP_ALGO: + return sprintf(buf, "%s\n", "ldcp"); + case ROCE_CC_IPQCN_ALGO: + return sprintf(buf, "%s\n", "hc3_1/ipqcn"); + default: + return sprintf(buf, "%s\n", "error_type"); + } +} + +static ssize_t roce3_store_cc_algo(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj); + u32 old_cc_algo = 0; + int cc_algo = 0; + ssize_t ret; + + if ((attr == NULL) || (buf == NULL)) { + pr_err("[ROCE] %s: attr or buf is null\n", __func__); + return -EINVAL; + } + + /* dcqcn -> 0x0, ldcp -> 0x2, hc3_1 -> 0x80 */ + if (strncmp(buf, "disable", strlen("disable")) == 0) { + cc_algo = ROCE_CC_DISABLE; + } else if (strncmp(buf, "dcqcn", strlen("dcqcn")) == 0) { + cc_algo = ROCE_CC_DCQCN_ALGO; + } else if ((strncmp(buf, "ipqcn", strlen("ipqcn")) == 0) || (strncmp(buf, "hc3_1", strlen("hc3_1")) == 0)) { + cc_algo = ROCE_CC_IPQCN_ALGO; + } else if (strncmp(buf, "ldcp", strlen("ldcp")) == 0) { + cc_algo = ROCE_CC_LDCP_ALGO; + } else { + pr_err("[ROCE] %s: Invalid cc_algo(%d),buf(%s)\n", __func__, cc_algo, buf); + return -EIO; + } + + if (ecn_ctx->cc_algo != (u32)cc_algo) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_cc_algo = ecn_ctx->cc_algo; + ecn_ctx->cc_algo = (u32)cc_algo; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to update cc_algo param, ret(%d)", __func__, (int)ret); + ecn_ctx->cc_algo = old_cc_algo; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_ecn_prio_enable(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_prio_enable_ctx *prio_enable_ctx = container_of(attr, struct roce3_prio_enable_ctx, enable); + + return sprintf(buf, "%d\n", (int)prio_enable_ctx->prio_en); +} + +static ssize_t roce3_store_ecn_prio_enable(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int prio_en = 0; + u32 old_prio_en = 0; + struct roce3_ecn_rp_ctx *rp_ctx = NULL; + struct roce3_ecn_np_ctx *np_ctx = NULL; + struct roce3_ecn_ctx *ecn_ctx = NULL; + struct roce3_prio_enable_ctx *prio_enable_ctx = container_of(attr, struct roce3_prio_enable_ctx, enable); + struct roce3_ecn_enable_ctx *ecn_enable_ctx = (struct roce3_ecn_enable_ctx *)prio_enable_ctx->ecn_enable_ctx; + + if (ecn_enable_ctx->np_rp == ROCE_DCQCN_NP) { + np_ctx = container_of(ecn_enable_ctx, struct roce3_ecn_np_ctx, enable_ctx); + ecn_ctx = container_of(np_ctx, struct roce3_ecn_ctx, np_ctx); + } else { + rp_ctx = container_of(ecn_enable_ctx, struct roce3_ecn_rp_ctx, enable_ctx); + ecn_ctx = container_of(rp_ctx, struct roce3_ecn_ctx, rp_ctx); + } + + ret = sscanf(buf, "%d", &prio_en); + if (ret != 1) { + return -EIO; + } + + if (((u32)prio_en & ROCE_PRIO_EN_MASK) != 0) { + return -EIO; + } + + if (prio_enable_ctx->prio_en != (u32)prio_en) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_prio_en = prio_enable_ctx->prio_en; + prio_enable_ctx->prio_en = (u32)prio_en; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + prio_enable_ctx->prio_en = old_prio_en; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_ecn_ip_prio_enable(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ip_prio_enable_ctx *ip_prio_enable_ctx = + container_of(attr, struct roce3_ip_prio_enable_ctx, ip_enable); + + return sprintf(buf, "%d\n", (int)ip_prio_enable_ctx->prio_en); +} + +static ssize_t roce3_store_ecn_ip_prio_enable(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int prio_en = 0; + u32 old_prio_en = 0; + struct roce3_ip_prio_enable_ctx *ip_prio_enable_ctx = + container_of(attr, struct roce3_ip_prio_enable_ctx, ip_enable); + struct roce3_ecn_ip_enable_ctx *ip_enable_ctx = + (struct roce3_ecn_ip_enable_ctx *)ip_prio_enable_ctx->ecn_ip_enable_ctx; + struct roce3_ecn_ctx *ecn_ctx = container_of(ip_enable_ctx, struct roce3_ecn_ctx, ip_enable_ctx); + + ret = sscanf(buf, "%d", &prio_en); + if (ret != 1) { + return -EIO; + } + + if (((u32)prio_en & ROCE_PRIO_EN_MASK) != 0) { + return -EIO; + } + + if (ip_prio_enable_ctx->prio_en != (u32)prio_en) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_prio_en = ip_prio_enable_ctx->prio_en; + ip_prio_enable_ctx->prio_en = (u32)prio_en; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ip_prio_enable_ctx->prio_en = old_prio_en; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_rate_inc_hai(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->rate_inc_hai); +} + +static ssize_t roce3_store_rate_inc_hai(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int rate_inc_hai = 0; + u32 old_rate_inc_hai = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &rate_inc_hai); + if (ret != 1) { + return -EIO; + } + + if ((rate_inc_hai < ROCE_MIN_RATE_INC_HAI) || (rate_inc_hai > ROCE_MAX_RATE_INC_HAI)) { + return -EIO; + } + + if (ecn_rp_ctx->rate_inc_hai != (u32)rate_inc_hai) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_rate_inc_hai = ecn_rp_ctx->rate_inc_hai; + ecn_rp_ctx->rate_inc_hai = (u32)rate_inc_hai; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->rate_inc_hai = old_rate_inc_hai; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_rate_inc_ai(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->rate_inc_ai); +} + +static ssize_t roce3_store_rate_inc_ai(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + ssize_t ret = 0; + int rate_inc_ai = 0; + u32 old_rate_inc_ai = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &rate_inc_ai); + if (ret != 1) { + return -EIO; + } + + if ((rate_inc_ai < ROCE_MIN_RATE_INC_AI) || (rate_inc_ai > ROCE_MAX_RATE_INC_AI)) { + return -EIO; + } + + if (ecn_rp_ctx->rate_inc_ai != (u32)rate_inc_ai) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_rate_inc_ai = ecn_rp_ctx->rate_inc_ai; + ecn_rp_ctx->rate_inc_ai = (u32)rate_inc_ai; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->rate_inc_ai = old_rate_inc_ai; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_initial_alpha(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->initial_alpha); +} + +static ssize_t roce3_store_initial_alpha(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int initial_alpha = 0; + u32 old_initial_alpha = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &initial_alpha); + if (ret != 1) { + return -EIO; + } + + if ((initial_alpha < ROCE_MIN_INITIAL_ALPHA) || (initial_alpha > ROCE_MAX_INITIAL_ALPHA)) { + return -EIO; + } + + if (ecn_rp_ctx->initial_alpha != (u32)initial_alpha) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_initial_alpha = ecn_rp_ctx->initial_alpha; + ecn_rp_ctx->initial_alpha = (u32)initial_alpha; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->initial_alpha = old_initial_alpha; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_factor_gita(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->factor_gita); +} + +static ssize_t roce3_store_factor_gita(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + ssize_t ret = 0; + int factor_gita = 0; + u32 old_factor_gita = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &factor_gita); + if (ret != 1) { + return -EIO; + } + + if ((factor_gita < ROCE_MIN_FACTOR_GITA) || (factor_gita > ROCE_MAX_FACTOR_GITA)) { + return -EIO; + } + + if (ecn_rp_ctx->factor_gita != (u32)factor_gita) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_factor_gita = ecn_rp_ctx->factor_gita; + ecn_rp_ctx->factor_gita = (u32)factor_gita; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->factor_gita = old_factor_gita; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_rate_inc_period(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->rate_inc_period); +} + +static ssize_t roce3_store_rate_inc_period(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int rate_inc_period = 0; + u32 old_rate_inc_period = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &rate_inc_period); + if (ret != 1) { + return -EIO; + } + + if ((rate_inc_period < ROCE_MIN_RATE_INC_PERIOD) || (rate_inc_period > ROCE_MAX_RATE_INC_PERIOD)) { + return -EIO; + } + + if (ecn_rp_ctx->rate_inc_period != (u32)rate_inc_period) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_rate_inc_period = ecn_rp_ctx->rate_inc_period; + ecn_rp_ctx->rate_inc_period = (u32)rate_inc_period; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->rate_inc_period = old_rate_inc_period; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_cnp_cnt_threshold(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->cnp_cnt_threshold); +} + +static ssize_t roce3_store_cnp_cnt_threshold(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int cnp_cnt_threshold = 0; + u32 old_cnp_cnt_threshold = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &cnp_cnt_threshold); + if (ret != 1) { + return -EIO; + } + + if ((cnp_cnt_threshold < ROCE_MIN_CNP_CNT_THRESHOLD) || (cnp_cnt_threshold > ROCE_MAX_CNP_CNT_THRESHOLD)) { + return -EIO; + } + + if (ecn_rp_ctx->cnp_cnt_threshold != (u32)cnp_cnt_threshold) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_cnp_cnt_threshold = ecn_rp_ctx->cnp_cnt_threshold; + ecn_rp_ctx->cnp_cnt_threshold = (u32)cnp_cnt_threshold; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->cnp_cnt_threshold = old_cnp_cnt_threshold; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_alpha_threshold(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", + (int)(ecn_rp_ctx->alpha_threshold << ALPHA_THREADHOLD_UNIT_SHIFT)); +} + +static ssize_t roce3_store_alpha_threshold(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + u32 alpha_threshold = 0; + u32 old_alpha_threshold = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%u", &alpha_threshold); + if (ret != 1) { + return -EIO; + } + + if ((alpha_threshold < ROCE_MIN_ALPHA_THRESHOLD) || (alpha_threshold > ROCE_MAX_ALPHA_THRESHOLD)) { + return -EIO; + } + alpha_threshold = ((u32)alpha_threshold >> ALPHA_THREADHOLD_UNIT_SHIFT); + + if (ecn_rp_ctx->alpha_threshold != (u32)alpha_threshold) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_alpha_threshold = ecn_rp_ctx->alpha_threshold; + ecn_rp_ctx->alpha_threshold = (u32)alpha_threshold; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->alpha_threshold = old_alpha_threshold; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_rate_dec_period(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->rate_dec_period); +} + +static ssize_t roce3_store_rate_dec_period(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int rate_dec_period = 0; + u32 old_rate_dec_period = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &rate_dec_period); + if (ret != 1) { + return -EIO; + } + + if ((rate_dec_period < ROCE_MIN_RATE_DEC_PERIOD) || (rate_dec_period > ROCE_MAX_RATE_DEC_PERIOD)) { + return -EIO; + } + + if (ecn_rp_ctx->rate_dec_period != (u32)rate_dec_period) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_rate_dec_period = ecn_rp_ctx->rate_dec_period; + ecn_rp_ctx->rate_dec_period = (u32)rate_dec_period; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->rate_dec_period = old_rate_dec_period; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_token_period(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->token_period); +} + +static ssize_t roce3_store_token_period(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int token_period = 0; + u32 old_token_period = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &token_period); + if (ret != 1) { + return -EIO; + } + + if ((token_period < ROCE_MIN_TOKEN_PERIOD) || (token_period > ROCE_MAX_TOKEN_PERIOD)) { + return -EIO; + } + + if (ecn_rp_ctx->token_period != (u32)token_period) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_token_period = ecn_rp_ctx->token_period; + ecn_rp_ctx->token_period = (u32)token_period; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->token_period = old_token_period; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_min_rate(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->min_rate); +} + +static ssize_t roce3_store_min_rate(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + ssize_t ret = 0; + int min_rate = 0; + u32 old_min_rate = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &min_rate); + if (ret != 1) { + return -EIO; + } + + if ((min_rate < ROCE_MIN_FLOW_MIN_RATE) || (min_rate > ROCE_MAX_FLOW_MIN_RATE)) { + return -EIO; + } + + if (ecn_rp_ctx->token_period != (u32)min_rate) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_min_rate = ecn_rp_ctx->min_rate; + ecn_rp_ctx->min_rate = (u32)min_rate; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->min_rate = old_min_rate; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_alpha_dec_period(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->alpha_dec_period); +} + +static ssize_t roce3_store_alpha_dec_period(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int alpha_dec_period = 0; + u32 old_alpha_dec_period = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &alpha_dec_period); + if (ret != 1) { + return -EIO; + } + + if ((alpha_dec_period < ROCE_MIN_ALPHA_DEC_PERIOD) || (alpha_dec_period > ROCE_MAX_ALPHA_DEC_PERIOD)) { + return -EIO; + } + + if (ecn_rp_ctx->alpha_dec_period != (u32)alpha_dec_period) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_alpha_dec_period = ecn_rp_ctx->alpha_dec_period; + ecn_rp_ctx->alpha_dec_period = (u32)alpha_dec_period; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->alpha_dec_period = old_alpha_dec_period; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_rate_first_set(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->rate_first_set); +} + +static ssize_t roce3_store_rate_first_set(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int rate_first_set = 0; + u32 old_rate_first_set = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &rate_first_set); + if (ret != 1) { + return -EIO; + } + + if ((rate_first_set < ROCE_MIN_RATE_FIRST_SET) || (rate_first_set > ROCE_MAX_RATE_FIRST_SET)) { + return -EIO; + } + + if (ecn_rp_ctx->rate_first_set != (u32)rate_first_set) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_rate_first_set = ecn_rp_ctx->rate_first_set; + ecn_rp_ctx->rate_first_set = (u32)rate_first_set; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->rate_first_set = old_rate_first_set; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_rate_target_clamp(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_rp_ctx->rate_target_clamp); +} + +static ssize_t roce3_store_rate_target_clamp(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int rate_target_clamp = 0; + u32 old_rate_target_clamp = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_rp_ctx *ecn_rp_ctx = to_roce3_ecn_rp_ctx(kobj); + + ret = sscanf(buf, "%d", &rate_target_clamp); + if (ret != 1) { + return -EIO; + } + + if (((u32)rate_target_clamp & ROCE_RT_CLAMP_MASK) != 0) { + return -EIO; + } + + if (ecn_rp_ctx->rate_target_clamp != (u32)rate_target_clamp) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_rate_target_clamp = ecn_rp_ctx->rate_target_clamp; + ecn_rp_ctx->rate_target_clamp = (u32)rate_target_clamp; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_rp_ctx->rate_target_clamp = old_rate_target_clamp; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_min_cnp_period(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_np_ctx->min_cnp_period); +} + +static ssize_t roce3_store_min_cnp_period(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int min_cnp_period = 0; + u32 old_min_cnp_period = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + ret = sscanf(buf, "%d", &min_cnp_period); + if (ret != 1) { + return -EIO; + } + + if ((min_cnp_period < ROCE_MIN_MIN_CNP_PERIOD) || (min_cnp_period > ROCE_MAX_MIN_CNP_PERIOD)) { + return -EIO; + } + + if (ecn_np_ctx->min_cnp_period != (u32)min_cnp_period) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_min_cnp_period = ecn_np_ctx->min_cnp_period; + ecn_np_ctx->min_cnp_period = (u32)min_cnp_period; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_np_ctx->min_cnp_period = old_min_cnp_period; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_port_mode(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_np_ctx->port_mode); +} + +static ssize_t roce3_store_port_mode(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + ssize_t ret = 0; + int port_mode = 0; + u32 old_port_mode = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + ret = sscanf(buf, "%d", &port_mode); + if (ret != 1) { + return -EIO; + } + + if (((u32)port_mode & ROCE_PORT_MODE_MASK) != 0) { + return -EIO; + } + + if (ecn_np_ctx->port_mode != (u32)port_mode) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_port_mode = ecn_np_ctx->port_mode; + ecn_np_ctx->port_mode = (u32)port_mode; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_np_ctx->port_mode = old_port_mode; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_quick_adjust_en(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_np_ctx->quick_adjust_en); +} + +static ssize_t roce3_store_quick_adjust_en(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int quick_adjust_en = 0; + u32 old_quick_adjust_en = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + ret = sscanf(buf, "%d", &quick_adjust_en); + if (ret != 1) { + return -EIO; + } + + if (((u32)quick_adjust_en & ROCE_QUICK_AJ_EN_MASK) != 0) { + return -EIO; + } + + if (ecn_np_ctx->quick_adjust_en != (u32)quick_adjust_en) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_quick_adjust_en = ecn_np_ctx->quick_adjust_en; + ecn_np_ctx->quick_adjust_en = (u32)quick_adjust_en; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_np_ctx->quick_adjust_en = old_quick_adjust_en; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_cnp_prio_enable(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_np_ctx->cnp_prio_enable); +} + +static ssize_t roce3_store_cnp_prio_enable(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, + size_t count) +{ + ssize_t ret = 0; + int cnp_prio_enable = 0; + u32 old_cnp_prio_enable = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + ret = sscanf(buf, "%d", &cnp_prio_enable); + if (ret != 1) { + return -EIO; + } + + if (((u32)cnp_prio_enable & ROCE_CNP_PRIO_EN_MASK) != 0) { + return -EIO; + } + + if (ecn_np_ctx->cnp_prio_enable != (u32)cnp_prio_enable) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_cnp_prio_enable = ecn_np_ctx->cnp_prio_enable; + ecn_np_ctx->cnp_prio_enable = (u32)cnp_prio_enable; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_np_ctx->cnp_prio_enable = old_cnp_prio_enable; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static ssize_t roce3_show_cnp_prio(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_np_ctx->cnp_prio); +} + +static ssize_t roce3_store_cnp_prio(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + ssize_t ret = 0; + int cnp_prio = 0; + u32 old_cnp_prio = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj->parent); + struct roce3_ecn_np_ctx *ecn_np_ctx = to_roce3_ecn_np_ctx(kobj); + + ret = sscanf(buf, "%d", &cnp_prio); + if (ret != 1) { + return -EIO; + } + + if (((u32)cnp_prio) > (PRI_ARRAY_LEN - 1)) { + return -EIO; + } + + if (ecn_np_ctx->cnp_prio != (u32)cnp_prio) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_cnp_prio = ecn_np_ctx->cnp_prio; + ecn_np_ctx->cnp_prio = (u32)cnp_prio; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_np_ctx->cnp_prio = old_cnp_prio; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +static int roce3_init_ecn_enable_sysfs(struct kobject *kobj, struct roce3_ecn_enable_ctx *ecn_enable_ctx) +{ + int ret = 0; + int i = 0; + int j = 0; + const char *prio_arr[8] = {"0", "1", "2", "3", "4", "5", "6", "7"}; + struct roce3_prio_enable_ctx *prio_enable = NULL; + + ecn_enable_ctx->enable_root = kobject_create_and_add("enable", kobj); + if (ecn_enable_ctx->enable_root == NULL) { + pr_err("[ROCE, ERR] %s: Failed to create kobject for ecn enable.(ret:%d)\n", __func__, ret); + return -ENOMEM; + } + + for (i = 0; i < PRI_ARRAY_LEN; i++) { + prio_enable = &ecn_enable_ctx->prio_enable[i]; + prio_enable->ecn_enable_ctx = (void *)ecn_enable_ctx; + prio_enable->prio = (u32)i; + prio_enable->prio_en = 1; + sysfs_attr_init(&prio_enable->enable.attr); + prio_enable->enable.attr.name = prio_arr[i]; + prio_enable->enable.attr.mode = (S_IWUSR | S_IRUSR | S_IRGRP); + prio_enable->enable.show = roce3_show_ecn_prio_enable; + prio_enable->enable.store = roce3_store_ecn_prio_enable; + ret = sysfs_create_file(ecn_enable_ctx->enable_root, &prio_enable->enable.attr); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to create file for ecn enable.(ret:%d)\n", __func__, ret); + goto err_create_file; + } + } + + return 0; + +err_create_file: + for (j = i - 1; j >= 0; j--) { + sysfs_remove_file(ecn_enable_ctx->enable_root, &ecn_enable_ctx->prio_enable[i].enable.attr); + } + + kobject_put(ecn_enable_ctx->enable_root); + + return ret; +} + +static void roce3_remove_ecn_enable_sysfs(struct kobject *kobj, struct roce3_ecn_enable_ctx *ecn_enable_ctx) +{ + int i; + + for (i = 0; i < PRI_ARRAY_LEN; i++) { + sysfs_remove_file(ecn_enable_ctx->enable_root, &ecn_enable_ctx->prio_enable[i].enable.attr); + } + + kobject_put(ecn_enable_ctx->enable_root); +} + +static int roce3_init_ecn_ip_enable_sysfs(struct kobject *kobj, struct roce3_ecn_ip_enable_ctx *ip_enable_ctx) +{ + int ret = 0; + int i = 0; + int j = 0; + const char *prio_arr[8] = {"0", "1", "2", "3", "4", "5", "6", "7"}; + struct roce3_ip_prio_enable_ctx *ip_prio_enable = NULL; + ip_enable_ctx->ip_enable_root = kobject_create_and_add("ip_enable", kobj); + if (ip_enable_ctx->ip_enable_root == NULL) { + pr_err("[ROCE, ERR] %s: Failed to create kobject for ecn ip enable.(ret:%d)\n", __func__, ret); + return -ENOMEM; + } + + for (i = 0; i < PRI_ARRAY_LEN; i++) { + ip_prio_enable = &ip_enable_ctx->ip_prio_enable[i]; + ip_prio_enable->ecn_ip_enable_ctx = (void *)ip_enable_ctx; + ip_prio_enable->prio = (u32)i; + ip_prio_enable->prio_en = ROCE_DEFAULT_IP_EABLE_EN; + sysfs_attr_init(&ip_prio_enable->ip_enable.attr); + ip_prio_enable->ip_enable.attr.name = prio_arr[i]; + ip_prio_enable->ip_enable.attr.mode = (S_IWUSR | S_IRUSR | S_IRGRP); + ip_prio_enable->ip_enable.show = roce3_show_ecn_ip_prio_enable; + ip_prio_enable->ip_enable.store = roce3_store_ecn_ip_prio_enable; + ret = sysfs_create_file(ip_enable_ctx->ip_enable_root, &ip_prio_enable->ip_enable.attr); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to create file for ecn ip enable.(ret:%d)\n", __func__, ret); + goto err_create_file; + } + } + + return 0; + +err_create_file: + for (j = i - 1; j >= 0; j--) { + sysfs_remove_file(ip_enable_ctx->ip_enable_root, &ip_enable_ctx->ip_prio_enable[i].ip_enable.attr); + } + + kobject_put(ip_enable_ctx->ip_enable_root); + + return ret; +} + +static void roce3_remove_ecn_ip_enable_sysfs(struct kobject *kobj, struct roce3_ecn_ip_enable_ctx *ip_enable_ctx) +{ + int i; + + for (i = 0; i < PRI_ARRAY_LEN; i++) { + sysfs_remove_file(ip_enable_ctx->ip_enable_root, &ip_enable_ctx->ip_prio_enable[i].ip_enable.attr); + } + + kobject_put(ip_enable_ctx->ip_enable_root); +} + +ROCE_ATTR_RW(alpha_dec_period, roce3_show_alpha_dec_period, roce3_store_alpha_dec_period); +ROCE_ATTR_RW(rate_dec_period, roce3_show_rate_dec_period, roce3_store_rate_dec_period); +ROCE_ATTR_RW(rate_inc_period, roce3_show_rate_inc_period, roce3_store_rate_inc_period); +ROCE_ATTR_RW(cnp_cnt_threshold, roce3_show_cnp_cnt_threshold, roce3_store_cnp_cnt_threshold); +ROCE_ATTR_RW(alpha_threshold, roce3_show_alpha_threshold, roce3_store_alpha_threshold); +ROCE_ATTR_RW(factor_gita, roce3_show_factor_gita, roce3_store_factor_gita); +ROCE_ATTR_RW(initial_alpha, roce3_show_initial_alpha, roce3_store_initial_alpha); +ROCE_ATTR_RW(rate_inc_ai, roce3_show_rate_inc_ai, roce3_store_rate_inc_ai); +ROCE_ATTR_RW(rate_inc_hai, roce3_show_rate_inc_hai, roce3_store_rate_inc_hai); +ROCE_ATTR_RW(rate_first_set, roce3_show_rate_first_set, roce3_store_rate_first_set); +ROCE_ATTR_RW(rate_target_clamp, roce3_show_rate_target_clamp, roce3_store_rate_target_clamp); +ROCE_ATTR_RW(token_period, roce3_show_token_period, roce3_store_token_period); +ROCE_ATTR_RW(min_rate, roce3_show_min_rate, roce3_store_min_rate); + +static struct attribute *ecn_rp_ctx_attrs[] = { + ROCE_ATTR_PTR(alpha_dec_period), + ROCE_ATTR_PTR(rate_dec_period), + ROCE_ATTR_PTR(rate_inc_period), + ROCE_ATTR_PTR(cnp_cnt_threshold), + ROCE_ATTR_PTR(alpha_threshold), + ROCE_ATTR_PTR(factor_gita), + ROCE_ATTR_PTR(initial_alpha), + ROCE_ATTR_PTR(rate_inc_ai), + ROCE_ATTR_PTR(rate_inc_hai), + ROCE_ATTR_PTR(rate_first_set), + ROCE_ATTR_PTR(rate_target_clamp), + ROCE_ATTR_PTR(token_period), + ROCE_ATTR_PTR(min_rate), + NULL, +}; +ATTRIBUTE_GROUPS(ecn_rp_ctx); + +static void roce_ecn_rp_sysfs_release(struct kobject *kobj) {} + +static struct kobj_type roce_ecn_rp_ktype = { + .sysfs_ops = &kobj_sysfs_ops, + .release = roce_ecn_rp_sysfs_release, + .default_groups = ecn_rp_ctx_groups, +}; + +static int roce3_init_ecn_rp_sysfs(struct kobject *kobj, struct roce3_ecn_rp_ctx *ecn_rp_ctx) +{ + int ret = 0; + + ecn_rp_ctx->alpha_dec_period = ROCE_DEFAULT_ALPHA_DEC_PERIOD; + ecn_rp_ctx->rate_dec_period = ROCE_DEFAULT_RATE_DEC_PERIOD; + ecn_rp_ctx->rate_inc_period = ROCE_DEFAULT_RATE_INC_PERIOD; + ecn_rp_ctx->alpha_threshold = ROCE_DEFAULT_ALPHA_THRESHOLD; + ecn_rp_ctx->cnp_cnt_threshold = ROCE_DEFAULT_CNP_CNT_THRESHOLD; + ecn_rp_ctx->factor_gita = ROCE_DEFAULT_FACTOR_GITA; + ecn_rp_ctx->initial_alpha = ROCE_DEFAULT_INITIAL_ALPHA; + ecn_rp_ctx->rate_inc_ai = ROCE_DEFAULT_RATE_INC_AI; + ecn_rp_ctx->rate_inc_hai = ROCE_DEFAULT_RATE_INC_HAI; + ecn_rp_ctx->rate_first_set = ROCE_DEFAULT_RATE_FIRST_SET; + ecn_rp_ctx->rate_target_clamp = ROCE_DEFAULT_RATE_TARGET_CLAMP; + ecn_rp_ctx->token_period = ROCE_DEFAULT_TOKEN_PERIOD; + ecn_rp_ctx->min_rate = ROCE_DEFAULT_MIN_RATE; + ret = kobject_init_and_add(&ecn_rp_ctx->ecn_rp_root, &roce_ecn_rp_ktype, kobj, "roce3_rp"); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to add kobject roce3_rp.(ret:%d)\n", __func__, ret); + kobject_put(&ecn_rp_ctx->ecn_rp_root); + return ret; + } + + ecn_rp_ctx->enable_ctx.np_rp = ROCE_DCQCN_RP; + ret = roce3_init_ecn_enable_sysfs(&ecn_rp_ctx->ecn_rp_root, &ecn_rp_ctx->enable_ctx); + if (ret != 0) { + goto err_init_prio_enable_sysfs; + } + + return 0; + +err_init_prio_enable_sysfs: + kobject_put(&ecn_rp_ctx->ecn_rp_root); + + return ret; +} + +static void roce3_remove_ecn_rp_sysfs(struct kobject *kobj, struct roce3_ecn_rp_ctx *ecn_rp_ctx) +{ + roce3_remove_ecn_enable_sysfs(&ecn_rp_ctx->ecn_rp_root, &ecn_rp_ctx->enable_ctx); + + kobject_put(&ecn_rp_ctx->ecn_rp_root); +} + +ROCE_ATTR_RW(min_cnp_period, roce3_show_min_cnp_period, roce3_store_min_cnp_period); +ROCE_ATTR_RW(quick_adjust_en, roce3_show_quick_adjust_en, roce3_store_quick_adjust_en); +ROCE_ATTR_RW(port_mode, roce3_show_port_mode, roce3_store_port_mode); +ROCE_ATTR_RW(cnp_prio_enable, roce3_show_cnp_prio_enable, roce3_store_cnp_prio_enable); +ROCE_ATTR_RW(cnp_prio, roce3_show_cnp_prio, roce3_store_cnp_prio); + +static struct attribute *ecn_np_ctx_attrs[] = { + ROCE_ATTR_PTR(min_cnp_period), + ROCE_ATTR_PTR(quick_adjust_en), + ROCE_ATTR_PTR(port_mode), + ROCE_ATTR_PTR(cnp_prio_enable), + ROCE_ATTR_PTR(cnp_prio), + NULL, +}; +ATTRIBUTE_GROUPS(ecn_np_ctx); + +static void roce_ecn_np_sysfs_release(struct kobject *kobj) {} + +static struct kobj_type roce_ecn_np_ktype = { + .sysfs_ops = &kobj_sysfs_ops, + .release = roce_ecn_np_sysfs_release, + .default_groups = ecn_np_ctx_groups, +}; + +static int roce3_init_ecn_np_sysfs(struct kobject *kobj, struct roce3_ecn_np_ctx *ecn_np_ctx) +{ + int ret = 0; + + ecn_np_ctx->min_cnp_period = ROCE_DEFAULT_MIN_CNP_PERIOD; + ecn_np_ctx->quick_adjust_en = ROCE_DEFAULT_QUICK_AJ_ENABLE; + ecn_np_ctx->port_mode = ROCE_DEFAULT_PORT_MODE_25G; + ecn_np_ctx->cnp_prio_enable = ROCE_DEFAULT_CNP_PRIO_ENABLE; + ecn_np_ctx->cnp_prio = ROCE_DEFAULT_CNP_PRIO; + ret = kobject_init_and_add(&ecn_np_ctx->ecn_np_root, &roce_ecn_np_ktype, kobj, "roce3_np"); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to add kobject roce3_np.(ret:%d)\n", __func__, ret); + kobject_put(&ecn_np_ctx->ecn_np_root); + return ret; + } + + ecn_np_ctx->enable_ctx.np_rp = ROCE_DCQCN_NP; + ret = roce3_init_ecn_enable_sysfs(&ecn_np_ctx->ecn_np_root, &ecn_np_ctx->enable_ctx); + if (ret != 0) { + goto err_init_prio_enable_sysfs; + } + + return 0; + +err_init_prio_enable_sysfs: + kobject_put(&ecn_np_ctx->ecn_np_root); + return ret; +} + +static void roce3_remove_ecn_np_sysfs(struct kobject *kobj, struct roce3_ecn_np_ctx *ecn_np_ctx) +{ + roce3_remove_ecn_enable_sysfs(&ecn_np_ctx->ecn_np_root, &ecn_np_ctx->enable_ctx); + + kobject_put(&ecn_np_ctx->ecn_np_root); +} + +static ssize_t roce3_show_ecn_ver(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj); + + return sprintf(buf, "%d\n", (int)ecn_ctx->ecn_ver); +} + +static ssize_t roce3_store_ecn_ver(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + ssize_t ret = 0; + int ecn_ver = 0; + u32 old_ecn_ver = 0; + struct roce3_ecn_ctx *ecn_ctx = to_roce3_ecn_ctx(kobj); + + ret = sscanf(buf, "%d", &ecn_ver); + if (ret != 1) { + return -EIO; + } + + if ((ecn_ver < ECN_VER_DCQCN) || (ecn_ver > ECN_VER_PATHQCN)) { + return -EIO; + } + + if (ecn_ctx->ecn_ver != (u32)ecn_ver) { + mutex_lock(&ecn_ctx->ecn_mutex); + old_ecn_ver = ecn_ctx->ecn_ver; + ecn_ctx->ecn_ver = (u32)ecn_ver; + ret = (ssize_t)roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + ecn_ctx->ecn_ver = old_ecn_ver; + mutex_unlock(&ecn_ctx->ecn_mutex); + return -EIO; + } + mutex_unlock(&ecn_ctx->ecn_mutex); + } + + return (ssize_t)count; +} + +ROCE_ATTR_RW(ecn_ver, roce3_show_ecn_ver, roce3_store_ecn_ver); +ROCE_ATTR_RW(cc_algo, roce3_show_cc_algo, roce3_store_cc_algo); + +static struct attribute *ecn_ctx_attrs[] = { + ROCE_ATTR_PTR(ecn_ver), + ROCE_ATTR_PTR(cc_algo), + NULL, +}; +ATTRIBUTE_GROUPS(ecn_ctx); + +static void roce_ecn_sysfs_release(struct kobject *kobj) {} + +static struct kobj_type roce_ecn_ktype = { + .sysfs_ops = &kobj_sysfs_ops, + .release = roce_ecn_sysfs_release, + .default_groups = ecn_ctx_groups, +}; + +static int roce3_init_ecn_sysfs(struct net_device *ndev, struct roce3_ecn_ctx *ecn_ctx) +{ + int ret = 0; + + memset(ecn_ctx, 0, sizeof(*ecn_ctx)); + + mutex_init(&ecn_ctx->ecn_mutex); + + ecn_ctx->ecn_ver = ECN_VER_DCQCN; +#ifdef ROCE_COMPUTE +#ifdef EULER_2_10_OFED_4_18 + ecn_ctx->cc_algo = ROCE_CC_LDCP_ALGO; +#else + ecn_ctx->cc_algo = ROCE_CC_DCQCN_ALGO; +#endif +#elif defined(ROCE_VBS_EN) || defined(ROCE_STANDARD) + ecn_ctx->cc_algo = ROCE_CC_LDCP_ALGO; +#else + ecn_ctx->cc_algo = ROCE_CC_DISABLE; +#endif + + ret = kobject_init_and_add(&ecn_ctx->ecn_root, &roce_ecn_ktype, &ndev->dev.kobj, "ecn"); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to add kobject ecn.(ret:%d)\n", __func__, ret); + kobject_put(&ecn_ctx->ecn_root); + return ret; + } + + ret = roce3_init_ecn_np_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->np_ctx); + if (ret != 0) { + goto err_init_np_sysfs; + } + + ret = roce3_init_ecn_rp_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->rp_ctx); + if (ret != 0) { + goto err_init_rp_sysfs; + } + + ret = roce3_init_ecn_ip_enable_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->ip_enable_ctx); + if (ret != 0) { + goto err_init_ip_enable_sysfs; + } + + ret = roce3_update_ecn_param(ecn_ctx); + if (ret != 0) { + goto err_update; + } + + return 0; + +err_update: + roce3_remove_ecn_ip_enable_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->ip_enable_ctx); +err_init_ip_enable_sysfs: + roce3_remove_ecn_rp_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->rp_ctx); +err_init_rp_sysfs: + roce3_remove_ecn_np_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->np_ctx); +err_init_np_sysfs: + kobject_put(&ecn_ctx->ecn_root); + return ret; +} + +static void roce3_prase_qpc(struct roce_qp_context *qpc) +{ + qpc->chip_seg.sqc.dw2.value = be32_to_cpu(qpc->chip_seg.sqc.dw2.value); + qpc->chip_seg.sqc.dw3.value = be32_to_cpu(qpc->chip_seg.sqc.dw3.value); + qpc->chip_seg.sqac.dw3.value = be32_to_cpu(qpc->chip_seg.sqac.dw3.value); + qpc->chip_seg.sqac.dw7.value = be32_to_cpu(qpc->chip_seg.sqac.dw7.value); + qpc->chip_seg.rqc.dw3.value = be32_to_cpu(qpc->chip_seg.rqc.dw3.value); + qpc->chip_seg.rqc.dw7.value = be32_to_cpu(qpc->chip_seg.rqc.dw7.value); + qpc->sw_seg.ucode_seg.common.dw3.value = be32_to_cpu(qpc->sw_seg.ucode_seg.common.dw3.value); + qpc->sw_seg.ucode_seg.sq_ctx.dw9.value = be32_to_cpu(qpc->sw_seg.ucode_seg.sq_ctx.dw9.value); + qpc->sw_seg.ucode_seg.sq_ctx.ack_ctx.dw15.value = be32_to_cpu(qpc->sw_seg.ucode_seg.sq_ctx.ack_ctx.dw15.value); + qpc->sw_seg.ucode_seg.rq_ctx.dw22.value = be32_to_cpu(qpc->sw_seg.ucode_seg.rq_ctx.dw22.value); + qpc->sw_seg.ucode_seg.rq_ctx.ack_ctx.dw27.value = be32_to_cpu(qpc->sw_seg.ucode_seg.rq_ctx.ack_ctx.dw27.value); +} + +static ssize_t roce3_store_dfx_qpc(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + int ret; + u32 qpn; + struct roce3_dfx_qpc_ctx *qpc_ctx = NULL; + struct roce3_dfx_ctx *dfx_ctx = NULL; + struct roce3_device *rdev = NULL; + struct roce_qp_context qpc; + struct rdma_service_cap *rdma_cap = NULL; + + if (kobj == NULL || attr == NULL || buf == NULL || count == 0) { + pr_err("[ROCE] %s: Invalid input para\n", __func__); + return -EINVAL; + } + + qpc_ctx = container_of(attr, struct roce3_dfx_qpc_ctx, kattr); + dfx_ctx = container_of(qpc_ctx, struct roce3_dfx_ctx, qpc_ctx); + rdev = container_of(dfx_ctx, struct roce3_device, dfx_ctx); + + memset(&qpc, 0, sizeof(struct roce_qp_context)); + + ret = (int)sscanf(buf, "%u", &qpn); + if (ret != 1) { + pr_err("[ROCE] %s: Failed to do sscanf_s, ret(%d)\n", __func__, ret); + return -EIO; + } + + rdma_cap = &rdev->rdma_cap; + if ((qpn >= rdma_cap->dev_rdma_cap.roce_own_cap.max_qps) || (qpn < ROCE_MIN_QPN)) { + pr_err("[ROCE] %s: Invalid qpn(%u), max_qps(%u)\n", __func__, qpn, rdma_cap->dev_rdma_cap.roce_own_cap.max_qps); + return -EIO; + } + + ret = roce3_dfx_cmd_query_qp(rdev, qpn, &qpc); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to query qpc, ret(%d)\n", __func__, ret); + return (ssize_t)ret; + } + + roce3_prase_qpc(&qpc); + + roce3_dfx_print("qpn(0x%x): sqc pi(0x%x), sqc ci(0x%x), ccf_appid(0x%x)\n", qpn, qpc.chip_seg.sqc.dw2.bs.sq_pi, + qpc.chip_seg.sqc.dw3.bs.sq_ci, qpc.sw_seg.ucode_seg.common.dw0.bs.ccf_appid); + roce3_dfx_print("sqac ci(0x%x), sqac wqe_prefetch_ci(0x%x), rqc pi(0x%x), rqc ci(0x%x)\n", + qpc.chip_seg.sqac.dw3.bs.sqa_ci, qpc.chip_seg.sqac.dw7.bs.sqa_wqe_prefetch_ci, qpc.chip_seg.rqc.dw7.bs.rq_pi, + qpc.chip_seg.rqc.dw3.bs.rq_ci); + roce3_dfx_print("sq_ssn(0x%x), sq_rcv_msn(0x%x), rq_last_msn(0x%x), rqa_msn(0x%x)\n", + qpc.sw_seg.ucode_seg.sq_ctx.dw9.bs.ssn, qpc.sw_seg.ucode_seg.sq_ctx.ack_ctx.dw15.bs.sq_rcv_msn, + qpc.sw_seg.ucode_seg.rq_ctx.dw22.bs.last_msn, qpc.sw_seg.ucode_seg.rq_ctx.ack_ctx.dw27.bs.msn); + + return (ssize_t)count; +} + +static ssize_t roce3_store_dfx_cqc(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + int ret; + u32 cqn; + struct roce3_dfx_cqc_ctx *cqc_ctx = NULL; + struct roce3_dfx_ctx *dfx_ctx = NULL; + struct roce3_device *rdev = NULL; + struct roce_cq_context cqc; + struct rdma_service_cap *rdma_cap = NULL; + + if (kobj == NULL || attr == NULL || buf == NULL || count == 0) { + pr_err("[ROCE] %s: Invalid input para\n", __func__); + return -EINVAL; + } + + cqc_ctx = container_of(attr, struct roce3_dfx_cqc_ctx, kattr); + dfx_ctx = container_of(cqc_ctx, struct roce3_dfx_ctx, cqc_ctx); + rdev = container_of(dfx_ctx, struct roce3_device, dfx_ctx); + + memset(&cqc, 0, sizeof(struct roce_cq_context)); + + ret = (int)sscanf(buf, "%u", &cqn); + if (ret != 1) { + pr_err("[ROCE] %s: Failed to do sscanf_s, ret(%d)\n", __func__, ret); + return -EIO; + } + + rdma_cap = &rdev->rdma_cap; + if (cqn >= rdma_cap->dev_rdma_cap.roce_own_cap.max_cqs) { + pr_err("[ROCE] %s: Invalid cqn(%u), max_cqs(%u)\n", __func__, cqn, rdma_cap->dev_rdma_cap.roce_own_cap.max_cqs); + return -EIO; + } + + ret = roce3_dfx_cmd_query_cq(rdev, cqn, &cqc); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to query cqc, ret(%d)\n", __func__, ret); + return (ssize_t)ret; + } + + cqc.dw2.value = be32_to_cpu(cqc.dw2.value); + cqc.dw1.value = be32_to_cpu(cqc.dw1.value); + + roce3_dfx_print("cqn(0x%x): pi(0x%x), ci(0x%x)\n", cqn, cqc.dw2.bs.pi, cqc.dw1.bs.ci); + + return (ssize_t)count; +} + +static ssize_t roce3_store_dfx_srqc(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) +{ + int ret; + u32 srqn; + struct roce3_dfx_srqc_ctx *srqc_ctx = NULL; + struct roce3_dfx_ctx *dfx_ctx = NULL; + struct roce3_device *rdev = NULL; + struct roce_srq_context srqc; + struct rdma_service_cap *rdma_cap = NULL; + + if (kobj == NULL || attr == NULL || buf == NULL || count == 0) { + pr_err("[ROCE] %s: Invalid input para\n", __func__); + return -EINVAL; + } + + srqc_ctx = container_of(attr, struct roce3_dfx_srqc_ctx, kattr); + dfx_ctx = container_of(srqc_ctx, struct roce3_dfx_ctx, srqc_ctx); + rdev = container_of(dfx_ctx, struct roce3_device, dfx_ctx); + + memset(&srqc, 0, sizeof(struct roce_srq_context)); + + ret = (int)sscanf(buf, "%u", &srqn); + if (ret != 1) { + pr_err("[ROCE] %s: Failed to do sscanf_s, ret(%d)\n", __func__, ret); + return -EIO; + } + + rdma_cap = &rdev->rdma_cap; + if (srqn >= rdma_cap->dev_rdma_cap.roce_own_cap.max_srqs) { + pr_err("[ROCE] %s: Invalid srqn(%u), max_srqs(%u)\n", __func__, srqn, + rdma_cap->dev_rdma_cap.roce_own_cap.max_srqs); + return -EIO; + } + + ret = roce3_dfx_cmd_query_srq(rdev, srqn, &srqc); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to query srqc, ret(%d)\n", __func__, ret); + return (ssize_t)ret; + } + + srqc.dw4.value = be32_to_cpu(srqc.dw4.value); + + roce3_dfx_print("srqn(0x%x): pcnt(0x%x), ccnt(0x%x)\n", srqn, srqc.dw4.bs.pcnt, srqc.dw4.bs.ccnt); + + return (ssize_t)count; +} + +static int roce3_init_dfx_sub_ctx_sysfs(struct kobject *kobj, struct roce3_dfx_ctx *dfx_ctx) +{ + int ret; + struct kobj_attribute *qpc_kattr = NULL; + struct kobj_attribute *cqc_kattr = NULL; + struct kobj_attribute *srqc_kattr = NULL; + + if (kobj == NULL || dfx_ctx == NULL) { + pr_err("[ROCE] %s: Invalid kobj or dfx_ctx\n", __func__); + return -EINVAL; + } + + qpc_kattr = &dfx_ctx->qpc_ctx.kattr; + cqc_kattr = &dfx_ctx->cqc_ctx.kattr; + srqc_kattr = &dfx_ctx->srqc_ctx.kattr; + + sysfs_attr_init(&qpc_kattr->attr); + qpc_kattr->attr.name = "qpc"; + qpc_kattr->attr.mode = (S_IWUSR | S_IRUSR | S_IRGRP); + qpc_kattr->store = roce3_store_dfx_qpc; + ret = sysfs_create_file(kobj, &qpc_kattr->attr); + if (ret != 0) { + pr_err("[ROCE] %s: QPC failed to do sysfs_create_file, ret(%d)\n", __func__, ret); + return ret; + } + + sysfs_attr_init(&cqc_kattr->attr); + cqc_kattr->attr.name = "cqc"; + cqc_kattr->attr.mode = (S_IWUSR | S_IRUSR | S_IRGRP); + cqc_kattr->store = roce3_store_dfx_cqc; + ret = sysfs_create_file(kobj, &cqc_kattr->attr); + if (ret != 0) { + pr_err("[ROCE] %s: CQC failed to do sysfs_create_file, ret(%d)\n", __func__, ret); + goto err_create_cqc_sysfs; + } + + sysfs_attr_init(&srqc_kattr->attr); + srqc_kattr->attr.name = "srqc"; + srqc_kattr->attr.mode = (S_IWUSR | S_IRUSR | S_IRGRP); + srqc_kattr->store = roce3_store_dfx_srqc; + ret = sysfs_create_file(kobj, &srqc_kattr->attr); + if (ret != 0) { + pr_err("[ROCE] %s: SRQC failed to do sysfs_create_file, ret(%d)\n", __func__, ret); + goto err_create_srqc_sysfs; + } + + return 0; + +err_create_srqc_sysfs: + sysfs_remove_file(kobj, &cqc_kattr->attr); + +err_create_cqc_sysfs: + sysfs_remove_file(kobj, &qpc_kattr->attr); + + return ret; +} + +static int roce3_init_dfx_sysfs(struct net_device *ndev, struct roce3_dfx_ctx *dfx_ctx) +{ + int ret; + + memset(dfx_ctx, 0, sizeof(*dfx_ctx)); + + dfx_ctx->dfx_root = kobject_create_and_add("roce3_dfx", &ndev->dev.kobj); + if (dfx_ctx->dfx_root == NULL) { + pr_err("[ROCE] %s: Failed to do kobject_create_and_add\n", __func__); + return -ENOMEM; + } + + ret = roce3_init_dfx_sub_ctx_sysfs(dfx_ctx->dfx_root, dfx_ctx); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to init dfx sub ctx sysfs, ret(%d)\n", __func__, ret); + kobject_put(dfx_ctx->dfx_root); + return ret; + } + + return 0; +} + +static void roce3_remove_ecn_sysfs(struct roce3_ecn_ctx *ecn_ctx) +{ + roce3_remove_ecn_ip_enable_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->ip_enable_ctx); + + roce3_remove_ecn_rp_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->rp_ctx); + + roce3_remove_ecn_np_sysfs(&ecn_ctx->ecn_root, &ecn_ctx->np_ctx); + + kobject_put(&ecn_ctx->ecn_root); +} + +int roce3_init_sysfs(struct roce3_device *rdev) +{ + int ret; + + ret = roce3_init_ecn_sysfs(rdev->ndev, &rdev->ecn_ctx); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to init ecn sysfs, ret(%d)\n", __func__, ret); + return ret; + } + + ret = roce3_init_dfx_sysfs(rdev->ndev, &rdev->dfx_ctx); + if (ret != 0) { + pr_err("[ROCE] %s: Failed to init dfx sysfs, ret(%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +static void roce3_remove_dfx_sub_sysfs(struct roce3_dfx_ctx *dfx_ctx) +{ + if (dfx_ctx->dfx_root != NULL) { + sysfs_remove_file(dfx_ctx->dfx_root, &dfx_ctx->srqc_ctx.kattr.attr); + + sysfs_remove_file(dfx_ctx->dfx_root, &dfx_ctx->cqc_ctx.kattr.attr); + + sysfs_remove_file(dfx_ctx->dfx_root, &dfx_ctx->qpc_ctx.kattr.attr); + + kobject_put(dfx_ctx->dfx_root); + + dfx_ctx->dfx_root = NULL; + } +} + + +void roce3_remove_sysfs(struct roce3_device *rdev) +{ + roce3_remove_dfx_sub_sysfs(&rdev->dfx_ctx); + roce3_remove_ecn_sysfs(&rdev->ecn_ctx); +} diff --git a/drivers/infiniband/hw/hiroce3/roce_sysfs.h b/drivers/infiniband/hw/hiroce3/roce_sysfs.h new file mode 100644 index 000000000..fe2de75a9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_sysfs.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_sysfs.h + * Version : v1.0 + * Created : 2021/3/2 + * Last Modified : 2022/3/2 + * Description : The definition of RoCE sysfs functions in kernel space. + */ + +#ifndef ROCE_SYSFS_H +#define ROCE_SYSFS_H + +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/device.h> +#include <linux/netdevice.h> +#include <linux/kobject.h> + +#define ROCE_MIN_QPN 2 +#define BYTE_TO_BIT 8 + +#define PRI_ARRAY_LEN 8 + +#define ROCE_MAX_PORT_CNT 8 + +#define HRN0_K_MAGIC_NUM_3_SYSFS 3 +#define HRN0_K_MAGIC_NUM_7_SYSFS 7 +#define HRN0_K_MAGIC_NUM_8_SYSFS 8 +#define HRN0_K_MAGIC_NUM_M_SYSFS 1000000 + +struct roce3_prio_enable_ctx { + struct kobj_attribute enable; + void *ecn_enable_ctx; + u32 prio_en; + u32 prio; +}; +struct roce3_ip_prio_enable_ctx { + struct kobj_attribute ip_enable; + void *ecn_ip_enable_ctx; + u32 prio_en; + u32 prio; +}; + +struct roce3_ecn_ip_enable_ctx { + struct kobject *ip_enable_root; + struct roce3_ip_prio_enable_ctx ip_prio_enable[PRI_ARRAY_LEN]; +}; + +struct roce3_ecn_enable_ctx { + struct kobject *enable_root; + struct roce3_prio_enable_ctx prio_enable[PRI_ARRAY_LEN]; + u32 np_rp; +}; + +struct roce3_dfx_qpc_ctx { + struct kobj_attribute kattr; +}; + +struct roce3_dfx_cqc_ctx { + struct kobj_attribute kattr; +}; + +struct roce3_dfx_srqc_ctx { + struct kobj_attribute kattr; +}; + +struct roce3_dfx_ctx { + struct kobject *dfx_root; + struct roce3_dfx_qpc_ctx qpc_ctx; + struct roce3_dfx_cqc_ctx cqc_ctx; + struct roce3_dfx_srqc_ctx srqc_ctx; +}; + +struct roce3_ecn_rp_ctx { + struct kobject ecn_rp_root; + u32 alpha_dec_period; + u32 rate_dec_period; + u32 rate_inc_period; + u32 alpha_threshold; + u32 cnp_cnt_threshold; + u32 factor_gita; + u32 initial_alpha; + u32 rate_inc_ai; + u32 rate_inc_hai; + u32 rate_first_set; + u32 rate_target_clamp; + u32 token_period; + u32 min_rate; + struct roce3_ecn_enable_ctx enable_ctx; +}; + +struct roce3_ecn_np_ctx { + struct kobject ecn_np_root; + u32 min_cnp_period; + u32 quick_adjust_en; + u32 port_mode; + u32 cnp_prio_enable; + u32 cnp_prio; + struct roce3_ecn_enable_ctx enable_ctx; +}; + +struct roce3_ecn_ctx { + struct kobject ecn_root; + struct mutex ecn_mutex; + u32 ecn_ver; + u32 cc_algo; + struct roce3_ecn_np_ctx np_ctx; + struct roce3_ecn_rp_ctx rp_ctx; + struct roce3_ecn_ip_enable_ctx ip_enable_ctx; +}; + +int roce3_update_ecn_param(const struct roce3_ecn_ctx *ecn_ctx); + +#endif // ROCE_SYSFS_H diff --git a/drivers/infiniband/hw/hiroce3/roce_user.h b/drivers/infiniband/hw/hiroce3/roce_user.h new file mode 100644 index 000000000..95ed0eab2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_user.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_user.h + * Version : v2.1 + * Created : 2021/3/2 + * Last Modified : 2021/12/24 + * Description : The definition of RoCE user space related functions in kernel space. + */ + +#ifndef ROCE_USER_H +#define ROCE_USER_H + +#include <linux/types.h> + +struct roce3_alloc_ucontext_resp { + u32 num_qps; + u32 num_xsrqs; + u32 cqe_size; + u32 wqebb_size; /* 64B or 128B */ + u32 dwqe_size; /* 256B */ + u32 max_msg_size; /* (2G -1)B */ + u32 max_comp_vector; + u32 max_inline_size; + u32 dev_caps; + u8 phy_port; + u8 storage_aa_en; + u16 rsvd; + u16 db_offset; + u16 dwqe_offset; + u8 srq_container_en; + u8 srq_container_mode; + u8 xrc_srq_container_mode; + u8 warn_th; +}; + +struct roce3_create_cq_cmd { + u64 buf_addr; + u64 db_addr; +}; + +struct roce3_resize_cq_cmd { + u64 buf_addr; /* resize cq's 'buf vaַ */ + u64 stage; /* describe the resize stage,0 or 1; */ +}; + +struct roce3_create_srq_cmd { + u64 buf_addr; + u64 db_addr; + u32 rsvd; +}; + +struct create_qp_cmd { + u64 buf_addr; /* describe the qp buf address that used to store cqe; */ + u64 db_addr; /* describe the qp sw db address */ + u32 comp_mask; /* kernel can judge whether handle receive inline through comp_mask */ + u8 log_sq_bb_count; /* wqebb number = 2 << log_sq_bb_count */ + u8 log_sq_stride; /* wqebb size = 2 << log_sq_stride */ + u16 reserved; /* reserved is used to aligned cmd */ +}; + +struct roce3_modify_srq_cmd { + u8 container_flag; + u8 container_warn_th; + u16 rsvd; +}; + +struct roce3_reg_frmr_cmd { + u64 pbl_vaddr; +}; + +#endif // ROCE_USER_H diff --git a/drivers/infiniband/hw/hiroce3/roce_xrc.c b/drivers/infiniband/hw/hiroce3/roce_xrc.c new file mode 100644 index 000000000..c7f4849dd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_xrc.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_xrc.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of functions for RoCE XRC features. + */ + +#include <linux/slab.h> + +#include "roce.h" +#include "roce_main_extension.h" +#include "roce_xrc.h" + +static int roce3_rdma_xrcd_alloc(void *hwdev, u32 *xrcdn) +{ + struct rdma_comp_priv *comp_priv = NULL; + + if ((hwdev == NULL) || (xrcdn == NULL)) { + pr_err("%s: Hwdev or xrcdn is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + *xrcdn = rdma_bitmap_alloc(&comp_priv->xrcd_bitmap); + if (*xrcdn == RDMA_INVALID_INDEX) { + pr_err("%s: Can't get valid xrcdn, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + return 0; +} + +static void roce3_rdma_xrcd_free(void *hwdev, u32 xrcdn) +{ + struct rdma_comp_priv *comp_priv = NULL; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return; + } + + comp_priv = get_rdma_comp_priv(hwdev); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + rdma_bitmap_free(&comp_priv->xrcd_bitmap, xrcdn); +} + +static int roce3_init_xrcd(struct ib_device *ibdev, struct roce3_device *rdev, struct roce3_xrcd *xrcd) +{ + int ret = 0; + struct ib_cq_init_attr cq_attr = { 0 }; + + ret = roce3_rdma_xrcd_alloc(rdev->hwdev, &xrcd->xrcdn); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma xrcd, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_alloc_xrcdn; + } + + xrcd->pd = ib_alloc_pd(ibdev, 0); /*lint !e119*/ + + if (IS_ERR(xrcd->pd)) { + ret = (int)PTR_ERR(xrcd->pd); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc pd, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_alloc_pd; + } + + cq_attr.cqe = 1; + xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr); + if (IS_ERR(xrcd->cq)) { + ret = (int)PTR_ERR(xrcd->cq); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create cq, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_create_cq; + } + return 0; + +err_create_cq: + ib_dealloc_pd(xrcd->pd); + +err_alloc_pd: + roce3_rdma_xrcd_free(rdev->hwdev, xrcd->xrcdn); + +err_alloc_xrcdn: + return ret; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) +{ + struct roce3_device *rdev = to_roce3_dev(ibxrcd->device); + struct roce3_xrcd *xrcd = to_roce3_xrcd(ibxrcd); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", + __func__, rdev->glb_func_id); + return -EPERM; + } + + return roce3_init_xrcd(ibxrcd->device, rdev, xrcd); +} +#else +struct ib_xrcd *roce3_alloc_xrcd(struct ib_device *ibdev, struct ib_ucontext *ibcontext, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_xrcd *xrcd = NULL; + + if (ibdev == NULL) { + pr_err("[ROCE, ERR] %s: Ibdev is null\n", __func__); + ret = (-EINVAL); + goto err_out; + } + + rdev = to_roce3_dev(ibdev); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", + __func__, rdev->glb_func_id); + ret = (-EPERM); + goto err_out; + } + + xrcd = (struct roce3_xrcd *)kzalloc(sizeof(*xrcd), GFP_KERNEL); + if (xrcd == NULL) { + ret = -ENOMEM; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc memory for xrcd, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_out; + } + + ret = roce3_init_xrcd(ibdev, rdev, xrcd); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to init xrcd, func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_init_xrcd; + } + return &xrcd->ibxrcd; + +err_init_xrcd: + kfree(xrcd); + +err_out: + return (struct ib_xrcd *)ERR_PTR((long)ret); +} + +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_dealloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata) +{ + struct roce3_device *rdev = NULL; + struct roce3_xrcd *xrcd = NULL; + + if (ibxrcd == NULL) { + pr_err("[ROCE, ERR] %s: Ibxrcd is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibxrcd->device); + xrcd = to_roce3_xrcd(ibxrcd); + ib_destroy_cq(xrcd->cq); + + ib_dealloc_pd(xrcd->pd); + roce3_rdma_xrcd_free(rdev->hwdev, xrcd->xrcdn); + return 0; +} +#else +int roce3_dealloc_xrcd(struct ib_xrcd *ibxrcd) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_xrcd *xrcd = NULL; + + if (ibxrcd == NULL) { + pr_err("[ROCE, ERR] %s: Ibxrcd is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibxrcd->device); + xrcd = to_roce3_xrcd(ibxrcd); + ret = ib_destroy_cq(xrcd->cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to destroy cq, func_id(%hu)\n", __func__, rdev->glb_func_id); + return ret; + } + + ib_dealloc_pd(xrcd->pd); + + roce3_rdma_xrcd_free(rdev->hwdev, xrcd->xrcdn); + kfree(xrcd); + + return 0; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/roce_xrc.h b/drivers/infiniband/hw/hiroce3/roce_xrc.h new file mode 100644 index 000000000..ab76341b5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/roce_xrc.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_xrc.h + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of data structures of RoCE XRC features. + */ + +#ifndef ROCE_XRC_H +#define ROCE_XRC_H + +#include <rdma/ib_verbs.h> + +#include "roce.h" + +struct roce3_xrcd { + struct ib_xrcd ibxrcd; + u32 xrcdn; + struct ib_pd *pd; + struct ib_cq *cq; +}; + +static inline struct roce3_xrcd *to_roce3_xrcd(const struct ib_xrcd *ibxrcd) +{ + return container_of(ibxrcd, struct roce3_xrcd, ibxrcd); +} + +#endif // ROCE_XRC_H diff --git a/drivers/infiniband/hw/hiroce3/srq/roce_srq.h b/drivers/infiniband/hw/hiroce3/srq/roce_srq.h new file mode 100644 index 000000000..54cb9ccbe --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/srq/roce_srq.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq.h + * Version : v2.2 + * Created : 2021/3/12 + * Last Modified : 2021/12/28 + * Description : The definition of RoCE SRQ function prototype, macros etc in kernel space. + */ + +#ifndef ROCE_SRQ_H +#define ROCE_SRQ_H + +#include <linux/types.h> + +#include <rdma/ib_verbs.h> + +#include "hinic3_rdma.h" +#include "hinic3_cqm.h" + +#include "roce.h" +#include "roce_pd.h" +#include "roce_db.h" + +#include "rdma_context_format.h" + +#define ROCE_SRQ_MAX_SGE 15 +#define ROCE_SRQ_MID_SGE 7 +#define ROCE_SRQ_MIN_SGE 3 + +#define ROCE_SRQN_INVLD 0XFFFFFFFF +#define ROCE_SRQ_CONTAINER_LWM_MASK 0xFFFF +#define ROCE_SRQ_CONTAINER_WARTH_MASK 0xF + +#define MAX_SUPPORT_CONTAINER_MODE 3 +#define DWORD_LEN 32 +#define XRC_CQN_FIRST_LEN 10 +#define XRC_CQN_SECOND_LEN 3 +#define SRQ_GPA_SIG_LEN 3 +#define SRQ_WQEBB_SIZE_CAL_SECTTOR 4 /* (2^rq_wqebb_size)*16B => divide 16 means shift need to minus 4 */ +#define RDMA_PREFETCH_WQE_MAX 7 +#define RDMA_PREFETCH_MTT_LEN_MAX 3 +#define ROCE_WQE_BB_SIZE_MIN 64 + +#define LAST_SGE_NO_PRESENT 0x80000000UL /* Lbit:0 - The next SGE is present in the list \ + * Lbit:1 - The last SGE, no SGE is present in the list */ +#define NORMAL_FMT_AND_NEXT_SGE_PRESENT 0x3FFFFFFFUL /* Ebit:b0 - Normal format, without extension. \ + * Ebit:b1 - The pointer inside of SGE points to the next SGL. \ + * "Length" and "Key" fields are */ +#define NORMAL_FMT_AND_LAST_SGE_NO_PRESENT 0xBFFFFFFFUL + +/** + * container_mode: + * mode: 0 -> container_size: 16 + * mode: 1 -> container_size: 8 + * mode: 2 -> container_size: 4 + * mode: 3 -> container_size: 2 + */ +enum roce3_srq_mode { + ROCE_SRQ_MODE_0 = 0, + ROCE_SRQ_MODE_1, + ROCE_SRQ_MODE_2, + ROCE_SRQ_MODE_3 +}; + +/** + * CHIP container_mode: + * chip mode: 0 -> Not container + * chip mode: 1 -> container_size: 2 + * chip mode: 2 -> container_size: 4 + * chip mode: 3 -> container_size: 8 + * chip mode: 4 -> container_size: 16 + */ +enum roce3_chip_srq_mode { + ROCE_CHIP_SRQ_MODE_N = 0, + ROCE_CHIP_SRQ_MODE_1, + ROCE_CHIP_SRQ_MODE_2, + ROCE_CHIP_SRQ_MODE_3, + ROCE_CHIP_SRQ_MODE_4 +}; + +enum roce3_srq_cont_num_mode { + ROCE_SRQ_CONT_NUM_MODE3 = 2, + ROCE_SRQ_CONT_NUM_MODE2 = 4, + ROCE_SRQ_CONT_NUM_MODE1 = 8, + ROCE_SRQ_CONT_NUM_MODE0 = 16 +}; + +enum srq_state { + ROCE_SRQ_STATE_INVALID = 0x0, + ROCE_SRQ_STATE_ERR = 0x1, + ROCE_SRQ_STATE_VALID = 0xf, + ROCE_SRQ_STATE_MEM_INIT = 0xa +}; + +#define ROCE_SRQ_STATE_CHECK_VALUE 0x0 + +struct roce3_srq_query_outbuf { + struct roce_srq_context srqc; + u32 srq_ctr_vld; + u32 srq_empty_ctr; + u32 reserved[6]; +}; + +struct roce3_wqe_srq_next_seg { + u16 reserved1; + __be16 pcnt; /* indicate the pi */ + u8 signature; + u8 reserved2; + __be16 next_wqe_index; + u32 reserved3[2]; +}; + +struct roce3_wqe_container_srq_next_seg { + u32 next_gpa_h; + + struct { + u32 rsvd : 11; + u32 next_gpa_vd : 1; + u32 next_gpa_h : 20; /* indicate the pi */ + } dw1; + + struct { + u32 next_idx : 16; + u32 rsvd : 16; + } dw2; + + struct { + u32 rsvd2 : 30; + u32 link_flag : 1; + u32 rsvd : 1; + } dw3; + + struct { + u32 osd_next_idx : 16; + u32 osd_cur_idx : 16; + } dw4; +}; + +#define ROCE_SRQ_SGE_LAST 1 +#define ROCE_SRQ_SGE_NLAST 0 + +#define ROCE_SRQ_SGE_LKEY_NOEXT 0 +#define ROCE_SRQ_SGE_LKEY_EXT 1 + +struct roce3_srq { + struct ib_srq ibsrq; /* ibsrq */ + cqm_queue_s *cqm_srq; + + u32 srqn; + int max_depth; + int max_gs; + int wqe_shift; + + cqm_buf_s *buf; + struct roce3_db db; + u64 *wrid; + spinlock_t lock; + int head; + int tail; + u16 wqe_ctr; + u8 xrc_en; + u8 rsvd; + struct ib_umem *umem; + struct rdma_mtt mtt; + struct mutex mutex; + u32 rqe_cnt_th; + u8 container_flag; + u8 container_size; + u8 container_mode; + u8 container_warn_th; + + int buf_sz; +}; + +static inline struct roce3_srq *to_roce3_srq(const struct ib_srq *ibsrq) +{ + return container_of(ibsrq, struct roce3_srq, ibsrq); +} + +static inline struct roce3_srq *cqmobj_to_roce3_srq(const cqm_object_s *object) +{ + cqm_queue_s *cqm_srq; + cqm_srq = container_of(object, cqm_queue_s, object); + return (struct roce3_srq *)cqm_srq->priv; +} + +void roce3_free_srq_wqe(struct roce3_srq *srq, int wqe_index); +void roce3_srq_async_event(struct roce3_device *rdev, struct roce3_srq *srq, int type); +void *roce3_srq_get_wqe(struct roce3_srq *srq, int n); +u8 roce3_get_container_sz(u32 container_mode); +u8 roce3_calculate_cont_th(u32 srq_limit); +u8 roce3_srq_mode_chip_adapt(u8 cfg_mode); +u32 roce3_srq_max_avail_wr_set(struct roce3_srq *rsrq); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_create_srq_common(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd, + struct ib_srq_init_attr *init_attr, struct ib_udata *udata, u32 index); +#else +struct ib_srq *roce3_create_srq_common(struct ib_pd *ibpd, struct ib_srq_init_attr *init_attr, struct ib_udata *udata, + u32 index); +#endif + +#endif // ROCE_SRQ_H diff --git a/drivers/infiniband/hw/hiroce3/srq/roce_srq_comm.c b/drivers/infiniband/hw/hiroce3/srq/roce_srq_comm.c new file mode 100644 index 000000000..e9e63757f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/srq/roce_srq_comm.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq_comm.c + * Version : v2.0 + * Created : 2021/3/12 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE SRQ common functions. + */ + +#include <linux/slab.h> +#include <linux/vmalloc.h> + +#include "roce.h" +#include "roce_compat.h" +#include "roce_xrc.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_pub_cmd.h" + +u8 roce3_srq_mode_chip_adapt(u8 cfg_mode) +{ + switch (cfg_mode) { + case ROCE_CHIP_SRQ_MODE_1: + return ROCE_SRQ_MODE_3; + case ROCE_CHIP_SRQ_MODE_2: + return ROCE_SRQ_MODE_2; + case ROCE_CHIP_SRQ_MODE_3: + return ROCE_SRQ_MODE_1; + case ROCE_CHIP_SRQ_MODE_4: + return ROCE_SRQ_MODE_0; + default: + return ROCE_SRQ_MODE_3; + } +} + +static void *roce3_srq_buf_offset(struct tag_cqm_buf *buf, int offset) +{ + return (void *)((char *)buf->direct.va + offset); +} + +void *roce3_srq_get_wqe(struct roce3_srq *srq, int n) +{ + return roce3_srq_buf_offset(srq->buf, (int)((u32)n << (unsigned)srq->wqe_shift)); +} + +void roce3_srq_async_event(struct roce3_device *rdev, struct roce3_srq *srq, int type) +{ + struct ib_srq *ibsrq = &srq->ibsrq; + struct ib_event event; + + memset(&event, 0, sizeof(event)); + if (ibsrq->event_handler) { + event.device = ibsrq->device; + event.element.srq = ibsrq; + switch (type) { + case ROCE_EVENT_TYPE_SRQ_LIMIT: + event.event = IB_EVENT_SRQ_LIMIT_REACHED; + break; + + case ROCE_EVENT_TYPE_SRQ_CATAS_ERROR: + event.event = IB_EVENT_SRQ_ERR; + break; + + default: + dev_warn_ratelimited(rdev->hwdev_hdl, "[ROCE] %s: unexpected event type(%d) on SRQ(%06x),\ + func_id(%d)\n", __func__, type, srq->srqn, rdev->glb_func_id); + return; + } + + ibsrq->event_handler(&event, ibsrq->srq_context); + } +} + +/* **************************************************************************** + Prototype : roce3_free_srq_wqe + Description : roce3_free_srq_wqe + Input : struct roce3_srq *srq + int wqe_index + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_free_srq_wqe(struct roce3_srq *srq, int wqe_index) +{ + struct roce3_wqe_srq_next_seg *next = NULL; + + spin_lock(&srq->lock); + + next = (struct roce3_wqe_srq_next_seg *)roce3_srq_get_wqe(srq, srq->tail); + next->next_wqe_index = (u16)wqe_index; + srq->tail = wqe_index; + + spin_unlock(&srq->lock); +} diff --git a/drivers/infiniband/hw/hiroce3/srq/roce_srq_create.c b/drivers/infiniband/hw/hiroce3/srq/roce_srq_create.c new file mode 100644 index 000000000..ebeba1531 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/srq/roce_srq_create.c @@ -0,0 +1,710 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq_create.c + * Version : v2.2 + * Created : 2021/3/12 + * Last Modified : 2021/12/24 + * Description : The definition of RoCE SRQ functions for createing a new SRQ. + */ + +#include <linux/slab.h> +#include <linux/vmalloc.h> +#ifndef __PC_LINT__ +#include <linux/kernel.h> +#endif + +#include "roce.h" +#include "roce_compat.h" +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_user.h" +#include "roce_xrc.h" +#include "roce_pd.h" +#include "roce_srq.h" +#include "roce_verbs_attr.h" +#include "roce_verbs_format.h" + +#include "roce_srq_extension.h" +#include "roce_main_extension.h" +#include "hinic3_hmm.h" +#include "roce_pub_cmd.h" + +/* **************************************************************************** + Prototype : roce3_srq_sw2hw + Description : roce3_srq_sw2hw + Input : struct roce3_device *rdev + struct roce3_srq *rsrq + u32 pdn + u32 cqn + u16 xrcdn + int page_shift + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + + 1.Date : 2015/7/27 + Modification : modify function +**************************************************************************** */ +static void roce3_srq_sw2hw_set(roce_verbs_srq_attr_s *srq_attr, struct roce3_srq *rsrq, u32 pdn, u32 cqn, u16 xrcdn, + int page_shift) +{ + srq_attr->dw0.bs.size = (u32)(ROCE_ILOG2((unsigned)rsrq->max_depth)); + srq_attr->dw0.bs.page_size = (u32)page_shift; + srq_attr->dw0.bs.wqebb_size = (u32)rsrq->wqe_shift - SRQ_WQEBB_SIZE_CAL_SECTTOR; + srq_attr->dw0.bs.mtt_page_size = (rsrq->mtt.mtt_page_shift - PAGE_SHIFT_4K); + srq_attr->dw0.bs.xrcd = xrcdn; + + srq_attr->dw1.bs.dma_attr_idx = 0; + srq_attr->dw1.bs.so_ro = 1; + srq_attr->dw1.bs.state = ROCE_SRQ_STATE_VALID; + + srq_attr->dw3.bs.container = rsrq->container_flag; + srq_attr->dw3.bs.lth_pre_en = (rsrq->container_flag == 0); // rdma engine prefetch + srq_attr->dw3.bs.pcnt_on_chip = 0; + srq_attr->dw3.bs.rkey_en = 1; + srq_attr->dw3.bs.pd = pdn; + + srq_attr->srqn = cpu_to_be32(rsrq->srqn); + srq_attr->xrc_cqn = cpu_to_be32(cqn); + + if (rsrq->container_flag == 0) { // normal srq + srq_attr->dw1.bs.ep = 0; + srq_attr->dw1.bs.cos = 0; + + srq_attr->dw2.value = 0; + srq_attr->dw2.bs.wqe_prefetch_max_num = RDMA_PREFETCH_WQE_MAX; // rdma engine wqe prefetch max num + // srq_attr->dw2.bs.wqe_prefetch_min_num = 0; + // srq_attr->dw2.bs.wqe_cache_thd_sel = 0; + srq_attr->dw2.bs.wqecnt_lth = 0xe; + // srq_attr->dw2.bs.wqecnt_ctrl_en = 0; + // srq_attr->dw2.bs.wqecnt_rctl = 0; + srq_attr->dw2.bs.mtt_prefetch_maxlen = 0; // rdma engine mtt prefetch max len + // srq_attr->dw2.bs.next_wqe_idx = 0; + + srq_attr->dw3.bs.lth_pre_en = 1; // rdma engine prefetch + srq_attr->dw3.bs.lth_gap = 0; + } else { + srq_attr->cont.dw2.bs.head_idx = 0; + srq_attr->cont.dw2.bs.warn_th = 0; // Do NOT init warn_th until user arm srq + srq_attr->cont.dw2.bs.cont_size = (MAX_SUPPORT_CONTAINER_MODE - rsrq->container_mode) & 0x3; + srq_attr->cont.dw2.value = cpu_to_be32(srq_attr->cont.dw2.value); + srq_attr->record_gpa_at_hop_num = cpu_to_be64((rsrq->mtt.mtt_layers & 0x3)); + } + + srq_attr->dw0.value = cpu_to_be32(srq_attr->dw0.value); + srq_attr->dw1.value = cpu_to_be32(srq_attr->dw1.value); + srq_attr->dw2.value = cpu_to_be32(srq_attr->dw2.value); + srq_attr->dw3.value = cpu_to_be32(srq_attr->dw3.value); + + srq_attr->l0mtt_gpa = rsrq->mtt.mtt_paddr; + + srq_attr->l0mtt_gpa = cpu_to_be64(srq_attr->l0mtt_gpa); + + srq_attr->record_gpa_at_hop_num = cpu_to_be64(rsrq->db.dma | (rsrq->mtt.mtt_layers & 0x3)); + + return; +} + +static int roce3_srq_sw2hw(struct roce3_device *rdev, struct roce3_srq *rsrq, u32 pdn, u32 cqn, u16 xrcdn, + int page_shift) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_verbs_srq_attr_s *srq_attr = NULL; + roce_uni_cmd_creat_srq_s *srq_sw2hw_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_creat_srq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + srq_sw2hw_inbuf = (roce_uni_cmd_creat_srq_s *)cqm_cmd_inbuf->buf; + srq_sw2hw_inbuf->com.index = cpu_to_be32((u32)rsrq->srqn); + srq_sw2hw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_SRQ_BITMASK); //lint !e778 + srq_attr = &srq_sw2hw_inbuf->srq_attr; + + roce3_srq_sw2hw_set(srq_attr, rsrq, pdn, cqn, xrcdn, page_shift); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_SW2HW_SRQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send SW2HW_SRQ command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(SW2HW_SRQ), srqn(0x%x), func_id(%hu)\n", __func__, + rsrq->srqn, rdev->glb_func_id); + + /* update dev status after cmdq timeout or exception, notify PCIe reset */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + ret = -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +static int roce3_create_srq_check(const struct ib_pd *ibpd, const struct ib_srq_init_attr *init_attr) +{ + struct roce3_device *rdev = to_roce3_dev(ibpd->device); + + if ((init_attr->attr.max_wr > (u32)rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_srq_wqes) || + (init_attr->attr.max_sge > (u32)rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_srq_sge)) { + pr_err("[ROCE, ERR] %s: Invalid input parms\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int roce3_create_srq_write_mtt_and_db(struct roce3_device *rdev, struct roce3_srq *rsrq, + struct roce3_create_srq_cmd *ucmd, struct roce3_pd *pd) +{ + int ret = 0; + + ret = roce3_umem_write_mtt(rdev, &rsrq->mtt, rsrq->umem); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + ret = roce3_db_map_user(to_roce3_ucontext(pd->ibpd.uobject->context), ucmd->db_addr, &rsrq->db); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to map db to user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + return ret; +} + +static int roce3_create_srq_get_umem(struct roce3_create_srq_cmd *ucmd, struct ib_udata *udata, struct roce3_srq *rsrq, + struct roce3_device *rdev, struct roce3_pd *pd) +{ + int ret = 0; + + if (ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)) != 0) { + ret = -EFAULT; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + rsrq->umem = ib_umem_get(&rdev->ib_dev, ucmd->buf_addr, (size_t)rsrq->buf_sz, 0); +#elif defined(OFED_MLNX_5_8) + rsrq->umem = ib_umem_get(udata, ucmd->buf_addr, (size_t)(unsigned)rsrq->buf_sz, 0); +#else + rsrq->umem = ib_umem_get(pd->ibpd.uobject->context, ucmd->buf_addr, (size_t)(unsigned)rsrq->buf_sz, 0, 0); +#endif + if (IS_ERR(rsrq->umem)) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to get ib_umem, func_id(%d) rsrq->buf_sz:%u\n", __func__, + rdev->glb_func_id, rsrq->buf_sz); + ret = (int)PTR_ERR(rsrq->umem); + return ret; + } + + return ret; +} + +static int roce3_create_user_srq_update(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd, + struct ib_srq_init_attr *init_attr, struct ib_udata *udata, int page_shift) +{ + u32 cqn = 0; + u16 xrcdn = 0; + struct roce_srq_context *srqc = NULL; + int ret = 0; + +#if defined(OFED_MLNX_5_8) || defined(OFED_VER_4_19) || (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + cqn = (u32)((init_attr->srq_type == IB_SRQT_XRC) ? to_roce3_cq(init_attr->ext.cq)->cqn : 0); /*lint !e40*/ +#endif + xrcdn = (init_attr->srq_type == IB_SRQT_XRC) ? (u16)(to_roce3_xrcd(init_attr->ext.xrc.xrcd)->xrcdn) : + (u16)rdev->rdma_cap.reserved_xrcds; + roce3_create_user_srq_update_ext(&cqn, rsrq->srqn); + + srqc = (struct roce_srq_context *)((void *)rsrq->cqm_srq->q_ctx_vaddr); + srqc->dw2.bs.state = ROCE_SRQ_STATE_MEM_INIT; + srqc->dw2.value = cpu_to_be32(srqc->dw2.value); + + /* set SRQC */ + ret = roce3_srq_sw2hw(rdev, rsrq, pd->pdn, cqn, xrcdn, (page_shift - PAGE_SHIFT_4K)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle srq_sw2hw, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_unmap; + } + + rsrq->ibsrq.ext.xrc.srq_num = (u32)rsrq->srqn; + + if (ib_copy_to_udata(udata, &rsrq->srqn, sizeof(u32)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data to user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EFAULT; + goto err_unmap; + } + + return 0; + +err_unmap: + roce3_db_unmap_user(to_roce3_ucontext(pd->ibpd.uobject->context), &rsrq->db); + return ret; +} + +u32 roce3_srq_max_avail_wr_set(struct roce3_srq *rsrq) +{ + u32 link_wqe_count = 0; + + if (rsrq->container_flag != 0) { + link_wqe_count = (u32)rsrq->max_depth / rsrq->container_size; + return ((u32)rsrq->max_depth - link_wqe_count) - (rsrq->container_size - 1); + } else { + return (u32)rsrq->max_depth - 1; + } +} + +/* **************************************************************************** + Prototype : roce3_create_user_srq + Description : roce3_create_user_srq + Input : struct roce3_device *rdev + struct roce3_srq *rsrq + struct roce3_pd *pd + struct ib_srq_init_attr *init_attr + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_user_srq(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd, + struct ib_srq_init_attr *init_attr, struct ib_udata *udata, u32 index) +{ + int ret = 0; + u32 npages = 0; + int page_shift = 0; + struct roce3_create_srq_cmd ucmd = { 0 }; + + /* dispatch SRQN and SRQC */ + rsrq->cqm_srq = + cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_SRQ, 0, rsrq, false, index); + if (rsrq->cqm_srq == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create rdma queue by cqm_object, func_id(%d) index(%d)\n", + __func__, rdev->glb_func_id, index); + return (-ENOMEM); + } + + rsrq->srqn = rsrq->cqm_srq->index; + + ret = roce3_create_srq_get_umem(&ucmd, udata, rsrq, rdev, pd); + if (ret != 0) { + goto err_free_cqm_srq; + } + + npages = (u32)ib_umem_num_pages(rsrq->umem); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(OFED_MLNX_5_8) + page_shift = PAGE_SHIFT; +#else + page_shift = rsrq->umem->page_shift; +#endif + + rsrq->mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, npages, (u32)page_shift, &rsrq->mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma_mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_release_umem; + } + + ret = roce3_create_srq_write_mtt_and_db(rdev, rsrq, &ucmd, pd); + if (ret != 0) { + goto err_free_mtt; + } + + ret = roce3_create_user_srq_update(rdev, rsrq, pd, init_attr, udata, page_shift); + if (ret != 0) { + goto err_free_mtt; + } + + init_attr->attr.max_wr = roce3_srq_max_avail_wr_set(rsrq); + + return 0; + +err_free_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &rsrq->mtt, SERVICE_T_ROCE); + +err_release_umem: + ib_umem_release(rsrq->umem); + +err_free_cqm_srq: + hiudk_cqm_object_delete(rdev->hwdev, &rsrq->cqm_srq->object); + + return ret; +} + +static void roce3_get_cqn_xrcdn(u32 *cqn, u16 *xrcdn, struct ib_srq_init_attr *init_attr, struct roce3_device *rdev) +{ +#if defined(OFED_MLNX_5_8) || defined(OFED_VER_4_19) || (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) + *cqn = (u32)((init_attr->srq_type == IB_SRQT_XRC) ? to_roce3_cq(init_attr->ext.cq)->cqn : 0); /*lint !e40*/ +#endif + *xrcdn = (init_attr->srq_type == IB_SRQT_XRC) ? (u16)(to_roce3_xrcd(init_attr->ext.xrc.xrcd)->xrcdn) : + (u16)rdev->rdma_cap.reserved_xrcds; +} + +static int roce3_create_kernel_srq_update(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd, + struct ib_srq_init_attr *init_attr, int page_shift) +{ + u32 cqn = 0; + u16 xrcdn = 0; + struct roce_srq_context *srqc = NULL; + int ret; + ret = roce3_buf_write_mtt(rdev, &rsrq->mtt, rsrq->buf); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_free_mtt; + } + + rsrq->wrid = (u64 *)kmalloc((size_t)((u32)rsrq->max_depth * sizeof(u64)), GFP_KERNEL); + if (rsrq->wrid == NULL) { + rsrq->wrid = (u64 *)vzalloc((size_t)((u32)rsrq->max_depth * sizeof(u64))); + if (rsrq->wrid == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc srq wrid, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -ENOMEM; + goto err_free_mtt; + } + } + + roce3_get_cqn_xrcdn(&cqn, &xrcdn, init_attr, rdev); + + srqc = (struct roce_srq_context *)((void *)rsrq->cqm_srq->q_ctx_vaddr); + srqc->dw2.bs.state = ROCE_SRQ_STATE_MEM_INIT; + srqc->dw2.value = cpu_to_be32(srqc->dw2.value); + + ret = roce3_srq_sw2hw(rdev, rsrq, pd->pdn, cqn, xrcdn, (page_shift - PAGE_SHIFT_4K)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle srq sw2hw, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_wrid; + } + + return 0; + +err_free_wrid: + kvfree(rsrq->wrid); + rsrq->wrid = NULL; + +err_free_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &rsrq->mtt, SERVICE_T_ROCE); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_create_kernel_srq + Description : roce3_create_kernel_srq + Input : struct roce3_device *rdev + struct roce3_srq *rsrq + struct roce3_pd *pd + struct ib_srq_init_attr *init_attr + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_kernel_srq(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd, + struct ib_srq_init_attr *init_attr, u32 index) +{ + int i = 0; + int ret = 0; + int page_shift = 0; + struct roce3_wqe_srq_next_seg *next = NULL; + struct roce3_wqe_srq_data_seg *scatter = NULL; + + /* alloc queue Buf/ Soft DB/SRQN/SRQC */ + rsrq->cqm_srq = cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_SRQ, (u32)rsrq->buf_sz, + rsrq, true, index); + if (rsrq->cqm_srq == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create rdma queue by cqm_object, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + rsrq->srqn = rsrq->cqm_srq->index; + rsrq->buf = &rsrq->cqm_srq->q_room_buf_1; + + /* set Soft DB */ + rsrq->db.db_record = (__be32 *)(void *)(&rsrq->cqm_srq->q_header_vaddr->doorbell_record); + rsrq->db.dma = rsrq->cqm_srq->q_header_paddr; + *rsrq->db.db_record = 0; + + rsrq->head = 0; + rsrq->tail = rsrq->max_depth - 1; + rsrq->wqe_ctr = 0; + + for (i = 0; i < rsrq->max_depth; ++i) { + next = (struct roce3_wqe_srq_next_seg *)roce3_srq_get_wqe(rsrq, i); + next->next_wqe_index = cpu_to_be16((u16)((u32)(i + 1) & (u32)(rsrq->max_depth - 1))); + + scatter = (struct roce3_wqe_srq_data_seg *)(next + 1); + scatter->dw2.length = 0; + + /* first SGE = last SGE */ + scatter->dw3.lkey = LAST_SGE_NO_PRESENT; + scatter->dw3.lkey = cpu_to_be32(scatter->dw3.lkey); + } + + page_shift = ROCE_ILOG2(rsrq->buf->buf_size); + rsrq->mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, rsrq->buf->buf_number, (u32)page_shift, &rsrq->mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma rdma_mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_cqm_srq; + } + + ret = roce3_create_kernel_srq_update(rdev, rsrq, pd, init_attr, page_shift); + if (ret != 0) { + goto err_free_cqm_srq; + } + + rsrq->ibsrq.ext.xrc.srq_num = (u32)rsrq->srqn; + init_attr->attr.max_wr = (u32)rsrq->max_depth - 1; + return 0; + +err_free_cqm_srq: + hiudk_cqm_object_delete(rdev->hwdev, &rsrq->cqm_srq->object); + + return ret; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) +static int roce3_create_srq_prepare(struct ib_pd *ibpd, struct ib_srq_init_attr *init_attr, struct roce3_srq **rsrq) +{ + int ret = 0; + struct roce3_device *rdev = to_roce3_dev(ibpd->device); + + if ((ibpd == NULL) || (init_attr == NULL)) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: Ibpd or init_attr is null\n", __func__); + return ret; + } + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = roce3_create_srq_check(ibpd, init_attr); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check srq info\n", __func__); + return ret; + } + + *rsrq = (struct roce3_srq *)kzalloc(sizeof(**rsrq), GFP_KERNEL); + if (*rsrq == NULL) { + ret = -ENOMEM; + pr_err("[ROCE, ERR] %s: Failed to alloc srq\n", __func__); + return ret; + } + + return ret; +} +#endif + +u8 roce3_get_container_sz(u32 container_mode) +{ + switch (container_mode) { + case ROCE_SRQ_MODE_0: + return ROCE_SRQ_CONT_NUM_MODE0; + case ROCE_SRQ_MODE_1: + return ROCE_SRQ_CONT_NUM_MODE1; + case ROCE_SRQ_MODE_2: + return ROCE_SRQ_CONT_NUM_MODE2; + case ROCE_SRQ_MODE_3: + return ROCE_SRQ_CONT_NUM_MODE3; + default: + return ROCE_SRQ_CONT_NUM_MODE3; + } +} + +static void roce3_set_srq_depth(struct ib_srq_init_attr *init_attr, struct roce3_srq *rsrq) +{ + u32 link_wqe_count = 0; + u32 remain_wqe_count = 0; + + /* + * +---+---+---+---+---+---+---+---+ + * |wqe|wqe|wqe|wqe|wqe|wqe|wqe|nil| + * +---+---+---+---+---+---+---+---+ + * ^ + * | + * full condition:head==tail==nil + */ + if (rsrq->container_flag != 0) { + link_wqe_count = init_attr->attr.max_wr / (rsrq->container_size - 1u); + remain_wqe_count = init_attr->attr.max_wr % (rsrq->container_size - 1u); + link_wqe_count += ((remain_wqe_count == 0) ? 0 : (rsrq->container_size - remain_wqe_count)); + rsrq->max_depth = (int)(init_attr->attr.max_wr + link_wqe_count + rsrq->container_size); + } else { + rsrq->max_depth = (int)(init_attr->attr.max_wr + 1); + } + rsrq->max_depth = (int)((ROCE_ROUNDUP_POW_OF_TWO((u32)rsrq->max_depth)) & 0xffffffff); //lint !e587 +} + +static void roce3_rsrq_init(struct ib_srq_init_attr *init_attr, struct roce3_srq *rsrq, struct roce3_device *rdev) +{ + int buf_size = 0; + int desc_size = 0; + + roce3_srq_container_init(init_attr, rsrq, rdev); + + mutex_init(&rsrq->mutex); + /*lint -e708*/ + spin_lock_init(&rsrq->lock); + /*lint +e708*/ + + roce3_set_srq_depth(init_attr, rsrq); + + rsrq->max_gs = (init_attr->attr.max_sge <= ROCE_SRQ_MIN_SGE) ? + ROCE_SRQ_MIN_SGE : + ((init_attr->attr.max_sge <= ROCE_SRQ_MID_SGE) ? ROCE_SRQ_MID_SGE : ROCE_SRQ_MAX_SGE); + init_attr->attr.max_sge = (u32)rsrq->max_gs; + + /* 0 <= max_gs <= 3, desc_size = 64 + * 4 <= max_gs <= 7, desc_size = 128 + */ + desc_size = (int)sizeof(struct roce3_wqe_srq_next_seg) + rsrq->max_gs * (int)sizeof(struct roce3_wqe_srq_data_seg); + desc_size = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)desc_size)); //lint !e587 + desc_size = ROCE_MAX(ROCE_WQE_BB_SIZE_MIN, desc_size); // align with min bb_size + rsrq->wqe_shift = ROCE_ILOG2((unsigned)desc_size); + buf_size = rsrq->max_depth * desc_size; + + /* WQEBB align 1 PAGE */ + if (buf_size < (int)PAGE_SIZE) { + rsrq->max_depth = (int)((u64)PAGE_SIZE >> (unsigned int)rsrq->wqe_shift); + } + + /* align with PAGE SIZE */ + buf_size = (int)ROCE_ALIGN((u32)buf_size, PAGE_SIZE); + rsrq->buf_sz = buf_size; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +int roce3_create_srq_common(struct roce3_device *rdev, struct roce3_srq *rsrq, struct roce3_pd *pd, + struct ib_srq_init_attr *init_attr, struct ib_udata *udata, u32 index) +{ + int ret; + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + ret = roce3_create_srq_check(&pd->ibpd, init_attr); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check srq info\n", __func__); + return ret; + } + + roce3_rsrq_init(init_attr, rsrq, rdev); + if (rsrq->ibsrq.uobject) { + ret = roce3_create_user_srq(rdev, rsrq, pd, init_attr, udata, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create user srq, func_id(%hu), index(%u)\n", __func__, + rdev->glb_func_id, index); + } + } else { + ret = roce3_create_kernel_srq(rdev, rsrq, pd, init_attr, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create kernel srq, func_id(%hu)\n", __func__, + rdev->glb_func_id); + } + } + + return ret; +} + +int roce3_create_srq(struct ib_srq *ibsrq, struct ib_srq_init_attr *init_attr, struct ib_udata *udata) +{ + struct roce3_pd *pd = to_roce3_pd(ibsrq->pd); + struct roce3_device *rdev = to_roce3_dev(ibsrq->device); + struct roce3_srq *rsrq = to_roce3_srq(ibsrq); + + return roce3_create_srq_common(rdev, rsrq, pd, init_attr, udata, ROCE_SRQN_INVLD); +} +#else +struct ib_srq *roce3_create_srq_common(struct ib_pd *ibpd, struct ib_srq_init_attr *init_attr, struct ib_udata *udata, + u32 index) +{ + int ret = 0; + struct roce3_srq *rsrq = NULL; + struct roce3_pd *pd = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_create_srq_prepare(ibpd, init_attr, &rsrq); + if (ret != 0) { + goto err_out; + } + + pd = to_roce3_pd(ibpd); + rdev = to_roce3_dev(ibpd->device); + roce3_rsrq_init(init_attr, rsrq, rdev); + + if (ibpd->uobject) { + ret = roce3_create_user_srq(rdev, rsrq, pd, init_attr, udata, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create user srq, func_id(%hu), index(%u)\n", __func__, + rdev->glb_func_id, index); + goto err_free_srq; + } + } else { + ret = roce3_create_kernel_srq(rdev, rsrq, pd, init_attr, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create kernel srq, func_id(%hu)\n", __func__, + rdev->glb_func_id); + goto err_free_srq; + } + } + + return &rsrq->ibsrq; + +err_free_srq: + kfree(rsrq); + +err_out: + return (struct ib_srq *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : roce3_create_srq + Description : init_attr->attr.max_wr belong to [1, max_srq_wqes), + Input : struct ib_pd *ibpd + struct ib_srq_init_attr *init_attr + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + 3.Date : 2021/1/6 + Modification : Modified function + +**************************************************************************** */ +struct ib_srq *roce3_create_srq(struct ib_pd *ibpd, struct ib_srq_init_attr *init_attr, struct ib_udata *udata) +{ + return roce3_create_srq_common(ibpd, init_attr, udata, ROCE_SRQN_INVLD); +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/srq/roce_srq_ctrl.c b/drivers/infiniband/hw/hiroce3/srq/roce_srq_ctrl.c new file mode 100644 index 000000000..94161d493 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/srq/roce_srq_ctrl.c @@ -0,0 +1,634 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq_ctrl.c + * Version : v2.1 + * Created : 2021/3/12 + * Last Modified : 2021/12/28 + * Description : The definition of RoCE SRQ control functions. + */ + +#include <linux/slab.h> +#include <linux/vmalloc.h> + +#include "roce.h" +#include "roce_compat.h" +#include "roce_user.h" +#include "roce_xrc.h" +#include "roce_srq.h" +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "hinic3_hmm.h" +#include "roce_main_extension.h" +#include "roce_pub_cmd.h" + +u8 roce3_calculate_cont_th(u32 srq_limit) +{ + u8 cont_th = 0; + u32 srq_limit_tmp = srq_limit; + + srq_limit_tmp >>= 1; + while (srq_limit_tmp != 0) { + srq_limit_tmp >>= 1; + ++cont_th; + } + + return cont_th; +} + +static u8 roce3_cal_srq_container_num(u32 avail_wr, struct roce3_srq *srq) +{ + u32 container_num = 0; + u32 srqe_num = 0; + + /* cal container_num by avail_wr from user */ + srqe_num = srq->container_size - 1; + + /* explain the formula: round up by srqe_num */ + container_num = (avail_wr + srqe_num - 1) / srqe_num; + return roce3_calculate_cont_th(container_num); +} + +/* **************************************************************************** + Prototype : roce3_srq_arm + Description : roce3_srq_arm + Input : struct roce3_device *rdev + struct roce3_srq *srq + u32 srq_limit + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_srq_arm(struct roce3_device *rdev, struct roce3_srq *srq, u32 srq_limit) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_srq_arm_s *srq_arm_inbuf = NULL; + u8 warth = 0; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_srq_arm_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + srq_arm_inbuf = (roce_cmd_srq_arm_s *)cqm_cmd_inbuf->buf; + srq_arm_inbuf->com.index = cpu_to_be32((u32)(srq->srqn)); + srq_arm_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_SRQ_BITMASK); //lint !e778 + if (srq->container_flag != 0) { + srq_arm_inbuf->bs.cont_en = srq->container_flag; + srq_arm_inbuf->bs.th_up_en = 1; // Valid for setting up container warn_threshold + warth = roce3_cal_srq_container_num(srq_limit, srq); + srq_arm_inbuf->bs.warth = warth & ROCE_SRQ_CONTAINER_WARTH_MASK; + srq_arm_inbuf->limitwater = cpu_to_be32(srq_arm_inbuf->limitwater); + } else { + srq_arm_inbuf->bs.lwm = srq_limit; + srq_arm_inbuf->limitwater = cpu_to_be32(srq_arm_inbuf->limitwater); + } + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_ARM_SRQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s:send ARM_SRQ command Failed, ret(%d), func_id(%d), warth(%d)\n", + __func__, ret, rdev->glb_func_id, warth); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(ARM_SRQ), srqn(0x%x), func_id(%hu)\n", __func__, + srq->srqn, rdev->glb_func_id); + + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + ret = -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_modify_srq + Description : roce3_modify_srq + Input : struct ib_srq *ibsrq + struct ib_srq_attr *attr + enum ib_srq_attr_mask attr_mask + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, enum ib_srq_attr_mask attr_mask, + struct ib_udata *udata) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_srq *srq = NULL; + struct roce3_modify_srq_cmd ucmd = { 0 }; + u32 max_avail_wr = 0; + + if ((ibsrq == NULL) || (attr == NULL)) { + pr_err("[ROCE, ERR] %s: Ibsrq or attr is null\n", __func__); + return (-EINVAL); + } + + if (((unsigned int)attr_mask & IB_SRQ_MAX_WR) != 0) { + pr_err("[ROCE, ERR] %s: Not support resizing SRQs\n", __func__); + return (-EINVAL); + } + + rdev = to_roce3_dev(ibsrq->device); + srq = to_roce3_srq(ibsrq); + + if ((udata != NULL) && (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: SRQN:(%d), Failed to copy from user space, func_id(%d)\n", __func__, + srq->srqn, rdev->glb_func_id); + return (-EFAULT); + } + + if (((unsigned int)attr_mask & IB_SRQ_LIMIT) != 0) { + /* calculate max_wr */ + max_avail_wr = roce3_srq_max_avail_wr_set(srq); + if (attr->srq_limit > max_avail_wr) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: srq_limit > max_wr, func_id(%d), max_avail_wr(%d)\n", __func__, + rdev->glb_func_id, max_avail_wr); + return (-EINVAL); + } + + mutex_lock(&srq->mutex); + ret = roce3_srq_arm(rdev, srq, attr->srq_limit); + mutex_unlock(&srq->mutex); + + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle srq arm, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_srq_query + Description : roce3_srq_query + Input : struct roce3_device *rdev + struct roce3_srq *srq + u32 *srq_limit + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_srq_query(struct roce3_device *rdev, struct roce3_srq *srq, u32 *srq_limit) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_srq_query_s *srq_query_inbuf = NULL; + struct roce3_srq_query_outbuf *srq_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_srq_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_srq_query_outbuf)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + srq_query_inbuf = (roce_cmd_srq_query_s *)cqm_cmd_inbuf->buf; + srq_query_outbuf = (struct roce3_srq_query_outbuf *)cqm_cmd_outbuf->buf; + srq_query_inbuf->com.index = cpu_to_be32((u32)srq->srqn); + srq_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_SRQ_BITMASK); //lint !e778 + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_SRQ, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send QUERY_SRQ command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(QUERY_SRQ), srqn(0x%x), func_id(%hu)\n", __func__, + srq->srqn, rdev->glb_func_id); + + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + ret = -1; + goto err_cmd; + } + + srq_query_outbuf->srqc.dw3.value = be32_to_cpu(srq_query_outbuf->srqc.dw3.value); + *srq_limit = srq_query_outbuf->srqc.dw3.bs.lth; + + if (srq->container_flag != 0) { + /* parse srqc to get warn_th */ + u32 warn_th = srq_query_outbuf->srqc.dw2.bs_c.warn_th; + *srq_limit = (warn_th == 0) ? 0 : ((u32)((srq->container_size - 1) * (1U << warn_th))); + } + +err_cmd: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_query_srq + Description : roce3_query_srq + Input : struct ib_srq *ibsrq + struct ib_srq_attr *srq_attr + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr) +{ + int ret = 0; + u32 limit_water = 0; + struct roce3_device *rdev = NULL; + struct roce3_srq *rsrq = NULL; + + if ((ibsrq == NULL) || (srq_attr == NULL)) { + pr_err("[ROCE, ERR] %s: Ibsrq or srq_attr is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibsrq->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s): HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + rsrq = to_roce3_srq(ibsrq); + + ret = roce3_srq_query(rdev, rsrq, &limit_water); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to query srq, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + srq_attr->srq_limit = limit_water; + srq_attr->max_wr = roce3_srq_max_avail_wr_set(rsrq); + srq_attr->max_sge = (u32)rsrq->max_gs; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_srq_hw2sw + Description : roce3_srq_hw2sw + Input : struct roce3_device *rdev + struct roce3_srq *srq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_srq_hw2sw(struct roce3_device *rdev, struct roce3_srq *srq) +{ + int ret = 0; + struct rdma_service_cap *rdma_cap = NULL; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_srq_hw2sw_s *srq_hw2sw_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_srq_hw2sw_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + srq_hw2sw_inbuf = (roce_cmd_srq_hw2sw_s *)cqm_cmd_inbuf->buf; + rdma_cap = &rdev->rdma_cap; + srq_hw2sw_inbuf->com.index = cpu_to_be32((u32)srq->srqn); + srq_hw2sw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_SRQ_BITMASK); //lint !e778 + srq_hw2sw_inbuf->srq_buf_len = cpu_to_be32((u32)srq->buf_sz); + + srq_hw2sw_inbuf->mtt_info.mtt_flags = 0; + srq_hw2sw_inbuf->mtt_info.mtt_num = 0; + srq_hw2sw_inbuf->mtt_info.mtt_cache_line_start = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_start); + srq_hw2sw_inbuf->mtt_info.mtt_cache_line_end = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_end); + srq_hw2sw_inbuf->mtt_info.mtt_cache_line_size = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_sz); + + srq_hw2sw_inbuf->wqe_cache_line_start = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.wqe_cl_start); + srq_hw2sw_inbuf->wqe_cache_line_end = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.wqe_cl_end); + srq_hw2sw_inbuf->wqe_cache_line_size = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.wqe_cl_sz); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_HW2SW_SRQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send HW2SW_SRQ command, func_id(%d)\n", __func__, + rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) == 0) { + ret = 0; + } else { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(HW2SW_SRQ), srqn(0x%x), func_id(%hu)\n", __func__, + srq->srqn, rdev->glb_func_id); + + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + + ret = -1; + } + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +static void roce3_free_srq(struct ib_srq *ibsrq, struct roce3_device *rdev, + struct roce3_srq *srq, struct ib_udata *udata) +{ + hmm_rdma_mtt_free(rdev->hwdev, &srq->mtt, SERVICE_T_ROCE); + + if (ibsrq->uobject) { + struct roce3_ucontext *ucontext = rdma_udata_to_drv_context( + udata, struct roce3_ucontext, ibucontext); + roce3_db_unmap_user(ucontext, &srq->db); + ib_umem_release(srq->umem); + } else { + kfree(srq->wrid); + } + + hiudk_cqm_object_delete(rdev->hwdev, &srq->cqm_srq->object); +} + +int roce3_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata) +{ + int ret = 0; + int times = 0; + int read_back_flag = 0; + struct roce3_device *rdev = NULL; + struct roce3_srq *srq = NULL; + struct roce_srq_context *srqc = NULL; + struct roce_srq_context check_srqc; + + if (ibsrq == NULL) { + pr_err("[ROCE, ERR] %s: Ibsrq is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibsrq->device); + srq = to_roce3_srq(ibsrq); + times = rdev->try_times; + + ret = roce3_srq_hw2sw(rdev, srq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle srq hw2sw, func_id(%hu), ret:%d\n", __func__, + rdev->glb_func_id, ret); + return ret; + } + + srqc = (struct roce_srq_context *)((void *)srq->cqm_srq->q_ctx_vaddr); + while ((times--) != 0) { + if (roce3_hca_is_present(rdev) == 0) { + goto err_roce_srq_free; + } + check_srqc.dw2.value = be32_to_cpu(srqc->dw2.value); + if (check_srqc.dw2.bs.state == ROCE_SRQ_STATE_CHECK_VALUE) { + read_back_flag = 1; + break; + } + + ROCE_UDELAY(US_PERF_DELAY); + } + + if (read_back_flag == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read srq state back after try %d times, func_id(%hu), " + "Srqn(0x%x), state_dw(0x%x)\n", __func__, rdev->try_times, rdev->glb_func_id, srq->srqn, srqc->dw2.value); + return -1; + } + +err_roce_srq_free: + roce3_free_srq(ibsrq, rdev, srq, udata); + + return 0; +} + +#else + +static void roce3_free_srq(struct ib_srq *ibsrq, struct roce3_device *rdev, struct roce3_srq *srq) +{ + hmm_rdma_mtt_free(rdev->hwdev, &srq->mtt, SERVICE_T_ROCE); + + if (ibsrq->uobject) { + roce3_db_unmap_user(to_roce3_ucontext(ibsrq->uobject->context), &srq->db); + ib_umem_release(srq->umem); + } else { + kfree(srq->wrid); + } + + hiudk_cqm_object_delete(rdev->hwdev, &srq->cqm_srq->object); + + kfree(srq); +} + +/* **************************************************************************** + Prototype : roce3_destroy_srq + Description : roce3_destroy_srq + Input : struct ib_srq *ibsrq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function +**************************************************************************** */ +int roce3_destroy_srq(struct ib_srq *ibsrq) +{ + int ret = 0; + int times = 0; + int read_back_flag = 0; + struct roce3_device *rdev = NULL; + struct roce3_srq *srq = NULL; + struct roce_srq_context *srqc = NULL; + struct roce_srq_context check_srqc; + + if (ibsrq == NULL) { + pr_err("[ROCE, ERR] %s: Ibsrq is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibsrq->device); + srq = to_roce3_srq(ibsrq); + times = rdev->try_times; + + ret = roce3_srq_hw2sw(rdev, srq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle srq hw2sw, func_id(%hu), ret:%d\n", __func__, + rdev->glb_func_id, ret); + return ret; + } + + srqc = (struct roce_srq_context *)((void *)srq->cqm_srq->q_ctx_vaddr); + while ((times--) != 0) { + if (roce3_hca_is_present(rdev) == 0) { + goto err_roce_srq_free; + } + check_srqc.dw2.value = be32_to_cpu(srqc->dw2.value); + if (check_srqc.dw2.bs.state == ROCE_SRQ_STATE_CHECK_VALUE) { + read_back_flag = 1; + break; + } + + ROCE_UDELAY(US_PERF_DELAY); + } + + if (read_back_flag == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read srq state back after try %d times, func_id(%hu)\n", + __func__, rdev->try_times, rdev->glb_func_id); + + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Srqn(0x%x), state_dw(0x%x), func_id(%hu)\n", __func__, srq->srqn, + srqc->dw2.value, rdev->glb_func_id); + return -1; + } + +err_roce_srq_free: + roce3_free_srq(ibsrq, rdev, srq); + + return 0; +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +static int roce3_check_sge_length(const struct ib_recv_wr *wr, struct roce3_device *rdev, + const struct ib_recv_wr **bad_wr, struct roce3_wqe_srq_data_seg *scat) +#else +static int roce3_check_sge_length(struct ib_recv_wr *wr, struct roce3_device *rdev, struct ib_recv_wr **bad_wr, + struct roce3_wqe_srq_data_seg *scat) +#endif +{ + int i = 0; + int ret = 0; + u32 data_len = 0; + + for (i = 0; i < wr->num_sge; ++i) { + if (ROCE_UNLIKELY(wr->sg_list[i].length > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz - 1)) { + ret = -EINVAL; + *bad_wr = wr; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Sge data length is over range, sg_list(%d), length(0x%x), \ + max_msg_sz(0x%x), func_id(%d)\n", + __func__, i, wr->sg_list[i].length, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz, + rdev->glb_func_id); + + scat[0].dw2.length = 0; + scat[0].dw3.lkey = LAST_SGE_NO_PRESENT; + scat[0].dw3.lkey = cpu_to_be32(scat[0].dw3.lkey); + return ret; + } + + data_len += wr->sg_list[i].length; + if (ROCE_UNLIKELY(data_len > rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz)) { + ret = -EINVAL; + *bad_wr = wr; + scat[0].dw2.length = 0; + scat[0].dw3.lkey = LAST_SGE_NO_PRESENT; + scat[0].dw3.lkey = cpu_to_be32(scat[0].dw3.lkey); + + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Data length is over range, data_len(0x%x), max_msg_sz(0x%x), func_id(%d)\n", __func__, + data_len, rdev->rdma_cap.dev_rdma_cap.roce_own_cap.max_msg_sz, rdev->glb_func_id); + return ret; + } + + scat[i].dw2.length = cpu_to_be32(wr->sg_list[i].length); + scat[i].dw3.lkey = cpu_to_be32((u32)(wr->sg_list[i].lkey & NORMAL_FMT_AND_NEXT_SGE_PRESENT)); + scat[i].addr = cpu_to_be64(wr->sg_list[i].addr); + } + + if (ROCE_UNLIKELY(i == 0)) { + scat[0].dw3.lkey = LAST_SGE_NO_PRESENT; + scat[0].dw3.lkey = cpu_to_be32(scat[0].dw3.lkey); + scat[0].dw2.length = 0; + } else { + scat[i - 1].dw3.lkey = + cpu_to_be32((u32)((wr->sg_list[i - 1].lkey | LAST_SGE_NO_PRESENT) & NORMAL_FMT_AND_LAST_SGE_NO_PRESENT)); + } + + return ret; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr) +#else +int roce3_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr, struct ib_recv_wr **bad_wr) +#endif +{ + int ret = 0; + int nreq = 0; + unsigned long flags = 0; + struct roce3_srq *srq = to_roce3_srq(ibsrq); + struct roce3_device *rdev = NULL; + struct roce3_wqe_srq_next_seg *next = NULL; + struct roce3_wqe_srq_data_seg *scat = NULL; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) + const struct ib_recv_wr *wr_tmp = wr; +#else + struct ib_recv_wr *wr_tmp = wr; +#endif + rdev = to_roce3_dev(ibsrq->device); + if (roce3_hca_is_present(rdev) == 0) { + return -EPERM; + } + + spin_lock_irqsave(&srq->lock, flags); + + for (nreq = 0; wr_tmp; ++nreq, wr_tmp = wr_tmp->next) { + if (ROCE_UNLIKELY((wr_tmp->num_sge > srq->max_gs) || (srq->head == srq->tail))) { + ret = (wr_tmp->num_sge > srq->max_gs) ? (-EINVAL) : (-ENOMEM); + *bad_wr = wr_tmp; + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Num_sge(%d) > max_gs(%d) or \ + srq is empty(head(%d) == tail(%d)), func_id(%d)\n", + __func__, wr_tmp->num_sge, srq->max_gs, rdev->glb_func_id, srq->head, srq->tail); + break; + } + + next = (struct roce3_wqe_srq_next_seg *)roce3_srq_get_wqe(srq, srq->head); + scat = (struct roce3_wqe_srq_data_seg *)(next + 1); + + ret = roce3_check_sge_length(wr_tmp, rdev, bad_wr, scat); + if (ret != 0) { + goto sge_len_err; + } + + next->pcnt = (u16)cpu_to_be16(srq->wqe_ctr + (u16)nreq); + srq->wrid[srq->head] = wr_tmp->wr_id; + srq->head = be16_to_cpu(next->next_wqe_index); + } + +sge_len_err: + if (ROCE_UNLIKELY(nreq != 0)) { + srq->wqe_ctr += (u16)nreq; + + /* + * Make sure that descriptors are written before + * doorbell record. + */ + wmb(); + + *srq->db.db_record = cpu_to_be32(srq->wqe_ctr); + } + + spin_unlock_irqrestore(&srq->lock, flags); + + return ret; +} -- 2.33.0